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/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SDFRTN_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HDLL__SDFRTN_FUNCTIONAL_PP_V
/**
* sdfrtn: Scan delay flop, inverted reset, inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_hdll__udp_mux_2to1.v"
`include "../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_hdll__udp_dff_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hdll__sdfrtn (
Q ,
CLK_N ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK_N ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
wire intclk ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
not not1 (intclk , CLK_N );
sky130_fd_sc_hdll__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_hdll__udp_dff$PR_pp$PG$N `UNIT_DELAY dff0 (buf_Q , mux_out, intclk, RESET, , VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SDFRTN_FUNCTIONAL_PP_V
|
// Simplistic packetizer mod supporting circular buffer
// The mod relies on following RAM writer module address rolling over
// The paketizer lets through data to RAM writer untill trigger signal,
// then lets through cfg_data number of beats and stops
// The start position is recorded
// Requirement: trigger signal transisions once and stays true
// CNTR_WIDTH*AXIS_TDATA_WIDTH must equal writer's ADDR_WIDTH*clogb2((AXI_DATA_WIDTH/8)-1)
`timescale 1 ns / 1 ps
module axis_circular_packetizer #
(
parameter integer AXIS_TDATA_WIDTH = 32,
parameter integer AXIS_TDATA_PHASE_WIDTH = 32,
parameter integer CNTR_WIDTH = 32,
parameter CONTINUOUS = "FALSE",
parameter NON_BLOCKING = "FALSE"
)
(
// System signals
input wire aclk,
input wire aresetn,
input wire [CNTR_WIDTH-1:0] cfg_data,
output wire [CNTR_WIDTH-1:0] trigger_pos,
input wire trigger,
output wire enabled,
output wire complete,
output wire [AXIS_TDATA_PHASE_WIDTH-1:0] phase,
// Slave side
output wire s_axis_tready,
input wire [AXIS_TDATA_WIDTH+AXIS_TDATA_PHASE_WIDTH-1:0] s_axis_tdata,
input wire s_axis_tvalid,
// Master side
input wire m_axis_tready,
output wire [AXIS_TDATA_WIDTH-1:0] m_axis_tdata,
output wire m_axis_tvalid,
output wire m_axis_tlast
);
reg [CNTR_WIDTH-1:0] int_cntr_reg, int_cntr_next, int_trigger_pos, int_trigger_pos_next;
reg int_enbl_reg, int_enbl_next;
reg [AXIS_TDATA_PHASE_WIDTH-1:0] int_phase_reg, int_phase_next;
reg int_complete_reg, int_complete_next;
wire int_comp_wire, int_tvalid_wire, int_tlast_wire;
always @(posedge aclk)
begin
if(~aresetn)
begin
int_cntr_reg <= {(CNTR_WIDTH){1'b0}};
int_trigger_pos <= {(CNTR_WIDTH){1'b0}};
int_enbl_reg <= 1'b0;
int_complete_reg <= 1'b0;
int_phase_reg <= {(AXIS_TDATA_PHASE_WIDTH){1'b0}};
end
else
begin
int_cntr_reg <= int_cntr_next;
int_trigger_pos <= int_trigger_pos_next;
int_enbl_reg <= int_enbl_next;
int_complete_reg <= int_complete_next;
int_phase_reg <= int_phase_next;
end
end
assign int_comp_wire = int_cntr_reg < cfg_data;
assign int_tvalid_wire = int_enbl_reg & s_axis_tvalid;
assign int_tlast_wire = ~int_comp_wire;
generate
if(CONTINUOUS == "TRUE")
begin : CONTINUOUS_LABEL
always @*
begin
int_cntr_next = int_cntr_reg;
int_enbl_next = int_enbl_reg;
int_complete_next = int_complete_reg;
int_trigger_pos_next = int_trigger_pos;
if(~int_enbl_reg & int_comp_wire)
begin
int_enbl_next = 1'b1;
end
if(m_axis_tready & int_tvalid_wire & int_comp_wire)
begin
int_cntr_next = int_cntr_reg + 1'b1;
end
if(m_axis_tready & int_tvalid_wire & int_tlast_wire)
begin
int_cntr_next = {(CNTR_WIDTH){1'b0}};
end
end
end
else
begin : STOP
always @*
begin
int_cntr_next = int_cntr_reg;
int_trigger_pos_next = int_trigger_pos;
int_enbl_next = int_enbl_reg;
int_complete_next = int_complete_reg;
int_phase_next = int_phase_reg;
if(~int_enbl_reg & int_comp_wire)
begin
int_enbl_next = 1'b1;
end
if(m_axis_tready & int_tvalid_wire & int_comp_wire)
begin
if(trigger)
int_cntr_next = int_cntr_reg + 1'b1;
else
begin
int_trigger_pos_next = int_trigger_pos + 1'b1;
int_phase_next = s_axis_tdata[(AXIS_TDATA_WIDTH+AXIS_TDATA_PHASE_WIDTH-1):AXIS_TDATA_WIDTH];
end
end
if(m_axis_tready & int_tvalid_wire & int_tlast_wire)
begin
int_enbl_next = 1'b0;
int_complete_next = 1'b1;
end
end
end
endgenerate
if(NON_BLOCKING == "TRUE")
assign s_axis_tready = ~int_enbl_reg | m_axis_tready;
else
assign s_axis_tready = int_enbl_reg & m_axis_tready;
assign m_axis_tdata = s_axis_tdata[AXIS_TDATA_WIDTH-1:0];
assign m_axis_tvalid = int_tvalid_wire;
assign m_axis_tlast = int_enbl_reg & int_tlast_wire;
assign trigger_pos = int_trigger_pos;
assign enabled = int_enbl_reg;
assign complete = int_complete_reg;
assign phase = int_phase_reg;
endmodule
|
/**
* This file is part of pyBAR.
*
* pyBAR is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* pyBAR is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with pyBAR. If not, see <http://www.gnu.org/licenses/>.
*/
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps / 1ps
`default_nettype none
module mmc3_8_chip_multi_tx_eth_SHIP(
input wire RESET_N,
input wire clkin,
output wire [3:0] rgmii_txd,
output wire rgmii_tx_ctl,
output wire rgmii_txc,
input wire [3:0] rgmii_rxd,
input wire rgmii_rx_ctl,
input wire rgmii_rxc,
output wire mdio_phy_mdc,
inout wire mdio_phy_mdio,
output wire phy_rst_n,
output wire [7:0] LED,
output wire [7:0] CMD_CLK_P, CMD_CLK_N,
output wire [7:0] CMD_DATA_P, CMD_DATA_N,
input wire [7:0] RJ45_HITOR_N, RJ45_HITOR_P,
input wire [7:0] DOBOUT_N, DOBOUT_P,
output wire RJ45_BUSY_LEMO_TX1, RJ45_CLK_LEMO_TX0,
output wire [1:0] LEMO_TX, // individual LEMO TX only available on MMC3 revision 1.2
input wire RJ45_TRIGGER, RJ45_RESET,
input wire [1:0] LEMO_RX,
inout wire [7:0] PMOD // 2-row PMOD header for general purpose IOs
);
wire RST;
wire CLK125PLLTX, CLK125PLLTX90;
wire PLL_FEEDBACK, LOCKED;
PLLE2_BASE #(
.BANDWIDTH("OPTIMIZED"), // OPTIMIZED, HIGH, LOW
.CLKFBOUT_MULT(10), // Multiply value for all CLKOUT, (2-64)
.CLKFBOUT_PHASE(0.0), // Phase offset in degrees of CLKFB, (-360.000-360.000).
.CLKIN1_PERIOD(10.000), // Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz).
.CLKOUT0_DIVIDE(8), // Divide amount for CLKOUT0 (1-128)
.CLKOUT0_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT0 (0.001-0.999).
.CLKOUT0_PHASE(0.0), // Phase offset for CLKOUT0 (-360.000-360.000).
.CLKOUT1_DIVIDE(8), // Divide amount for CLKOUT0 (1-128)
.CLKOUT1_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT0 (0.001-0.999).
.CLKOUT1_PHASE(90.0), // Phase offset for CLKOUT0 (-360.000-360.000).
.DIVCLK_DIVIDE(1), // Master division value, (1-56)
.REF_JITTER1(0.0), // Reference input jitter in UI, (0.000-0.999).
.STARTUP_WAIT("FALSE") // Delay DONE until PLL Locks, ("TRUE"/"FALSE")
) PLLE2_BASE_inst (
.CLKOUT0(CLK125PLLTX),
.CLKOUT1(CLK125PLLTX90),
.CLKOUT2(),
.CLKOUT3(),
.CLKOUT4(),
.CLKOUT5(),
.CLKFBOUT(PLL_FEEDBACK),
.LOCKED(LOCKED), // 1-bit output: LOCK
// Input 100 MHz clock
.CLKIN1(clkin),
// Control Ports
.PWRDWN(0),
.RST(!RESET_N),
// Feedback
.CLKFBIN(PLL_FEEDBACK)
);
wire CLK160_PLL, CLK320_PLL, CLK40_PLL, CLK16_PLL, BUS_CLK_PLL;
wire PLL_FEEDBACK2, LOCKED2;
PLLE2_BASE #(
.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT(16),
.CLKFBOUT_PHASE(0.0),
.CLKIN1_PERIOD(10.000),
.CLKOUT0_DIVIDE(10),
.CLKOUT0_DUTY_CYCLE(0.5),
.CLKOUT0_PHASE(0.0),
.CLKOUT1_DIVIDE(40),
.CLKOUT1_DUTY_CYCLE(0.5),
.CLKOUT1_PHASE(0.0),
.CLKOUT2_DIVIDE(5),
.CLKOUT2_DUTY_CYCLE(0.5),
.CLKOUT2_PHASE(0.0),
.CLKOUT3_DIVIDE(100),
.CLKOUT3_DUTY_CYCLE(0.5),
.CLKOUT3_PHASE(0.0),
.CLKOUT4_DIVIDE(12),
.CLKOUT4_DUTY_CYCLE(0.5),
.CLKOUT4_PHASE(0.0),
.DIVCLK_DIVIDE(1),
.REF_JITTER1(0.0),
.STARTUP_WAIT("FALSE")
) PLLE2_BASE_inst_2 (
.CLKOUT0(CLK160_PLL),
.CLKOUT1(CLK40_PLL),
.CLKOUT2(CLK320_PLL),
.CLKOUT3(CLK16_PLL),
.CLKOUT4(BUS_CLK_PLL),
.CLKOUT5(),
.CLKFBOUT(PLL_FEEDBACK2),
.LOCKED(LOCKED2), // 1-bit output: LOCK
.CLKIN1(clkin),
.PWRDWN(0),
.RST(!RESET_N),
.CLKFBIN(PLL_FEEDBACK2)
);
wire CLK160, CLK40, CLK320, CLK16, BUS_CLK;
BUFG BUFG_inst_160 (.O(CLK160), .I(CLK160_PLL));
BUFG BUFG_inst_40 (.O(CLK40), .I(CLK40_PLL));
BUFG BUFG_inst_320 (.O(CLK320), .I(CLK320_PLL));
BUFG BUFG_inst_16 (.O(CLK16), .I(CLK16_PLL));
BUFG BUFG_inst_BUS_CLK (.O(BUS_CLK), .I(BUS_CLK_PLL));
// BUFG BUFG_inst_200 (.O(CLK200), .I(CLK200_PLL));
// wire IDELAYCTRL_RDY;
// IDELAYCTRL IDELAYCTRL_inst (
// .RDY(IDELAYCTRL_RDY),
// .REFCLK(CLK200),
// .RST(!LOCKED2)
// );
wire CLK125TX, CLK125TX90, CLK125RX;
BUFG BUFG_inst_CLK125TX(.O(CLK125TX), .I(CLK125PLLTX));
BUFG BUFG_inst_CLK125TX90(.O(CLK125TX90), .I(CLK125PLLTX90));
BUFG BUFG_inst_CLK125RX(.O(CLK125RX), .I(rgmii_rxc));
assign RST = !RESET_N | !LOCKED | !LOCKED2;
wire gmii_tx_clk;
wire gmii_tx_en;
wire [7:0] gmii_txd;
wire gmii_tx_er;
wire gmii_crs;
wire gmii_col;
wire gmii_rx_clk;
wire gmii_rx_dv;
wire [7:0] gmii_rxd;
wire gmii_rx_er;
wire mdio_gem_mdc;
wire mdio_gem_i;
wire mdio_gem_o;
wire mdio_gem_t;
wire link_status;
wire [1:0] clock_speed;
wire duplex_status;
rgmii_io rgmii
(
.rgmii_txd(rgmii_txd),
.rgmii_tx_ctl(rgmii_tx_ctl),
.rgmii_txc(rgmii_txc),
.rgmii_rxd(rgmii_rxd),
.rgmii_rx_ctl(rgmii_rx_ctl),
.gmii_txd_int(gmii_txd), // Internal gmii_txd signal.
.gmii_tx_en_int(gmii_tx_en),
.gmii_tx_er_int(gmii_tx_er),
.gmii_col_int(gmii_col),
.gmii_crs_int(gmii_crs),
.gmii_rxd_reg(gmii_rxd), // RGMII double data rate data valid.
.gmii_rx_dv_reg(gmii_rx_dv), // gmii_rx_dv_ibuf registered in IOBs.
.gmii_rx_er_reg(gmii_rx_er), // gmii_rx_er_ibuf registered in IOBs.
.eth_link_status(link_status),
.eth_clock_speed(clock_speed),
.eth_duplex_status(duplex_status),
// Following are generated by DCMs
.tx_rgmii_clk_int(CLK125TX), // Internal RGMII transmitter clock.
.tx_rgmii_clk90_int(CLK125TX90), // Internal RGMII transmitter clock w/ 90 deg phase
.rx_rgmii_clk_int(CLK125RX), // Internal RGMII receiver clock
.reset(!phy_rst_n)
);
// Instantiate tri-state buffer for MDIO
IOBUF i_iobuf_mdio(
.O(mdio_gem_i),
.IO(mdio_phy_mdio),
.I(mdio_gem_o),
.T(mdio_gem_t));
wire EEPROM_CS, EEPROM_SK, EEPROM_DI;
wire TCP_CLOSE_REQ;
wire RBCP_ACT, RBCP_WE, RBCP_RE;
wire [7:0] RBCP_WD, RBCP_RD;
wire [31:0] RBCP_ADDR;
wire TCP_RX_WR;
wire [7:0] TCP_RX_DATA;
wire [15:0] TCP_RX_WC;
wire RBCP_ACK;
wire SiTCP_RST;
wire TCP_TX_FULL;
wire TCP_TX_WR;
wire [7:0] TCP_TX_DATA;
wire [7:0] PMOD_O;
IOBUF iobuf_pmod [7:0] (
.O(PMOD_O),
.IO(PMOD),
.I({8'b1111_0000}),
.T({8'b0000_1111})
);
wire [7:0] IP_ADDR_SEL;
assign IP_ADDR_SEL = {4'b0, PMOD_O[3], PMOD_O[2], PMOD_O[1], PMOD_O[0]}; // MSB: PMOD[3]; LSB: PMOD[0]
WRAP_SiTCP_GMII_XC7K_32K sitcp(
.CLK(BUS_CLK), // in : System Clock >129MHz
.RST(RST), // in : System reset
// Configuration parameters
.FORCE_DEFAULTn(1'b0), // in : Load default parameters
.EXT_IP_ADDR({8'd192, 8'd168, 8'd10 + IP_ADDR_SEL, 8'd11}), // in : IP address[31:0] //192.168.10.11
.EXT_TCP_PORT(16'd24), // in : TCP port #[15:0]
.EXT_RBCP_PORT(16'd4660), // in : RBCP port #[15:0]
.PHY_ADDR(5'd3), // in : PHY-device MIF address[4:0]
// EEPROM
.EEPROM_CS(EEPROM_CS), // out : Chip select
.EEPROM_SK(EEPROM_SK), // out : Serial data clock
.EEPROM_DI(EEPROM_DI), // out : Serial write data
.EEPROM_DO(1'b0), // in : Serial read data
// user data, intialial values are stored in the EEPROM, 0xFFFF_FC3C-3F
.USR_REG_X3C(), // out : Stored at 0xFFFF_FF3C
.USR_REG_X3D(), // out : Stored at 0xFFFF_FF3D
.USR_REG_X3E(), // out : Stored at 0xFFFF_FF3E
.USR_REG_X3F(), // out : Stored at 0xFFFF_FF3F
// MII interface
.GMII_RSTn(phy_rst_n), // out : PHY reset
.GMII_1000M(1'b1), // in : GMII mode (0:MII, 1:GMII)
// TX
.GMII_TX_CLK(CLK125TX), // in : Tx clock
.GMII_TX_EN(gmii_tx_en), // out : Tx enable
.GMII_TXD(gmii_txd), // out : Tx data[7:0]
.GMII_TX_ER(gmii_tx_er), // out : TX error
// RX
.GMII_RX_CLK(CLK125RX), // in : Rx clock
.GMII_RX_DV(gmii_rx_dv), // in : Rx data valid
.GMII_RXD(gmii_rxd), // in : Rx data[7:0]
.GMII_RX_ER(gmii_rx_er), // in : Rx error
.GMII_CRS(gmii_crs), // in : Carrier sense
.GMII_COL(gmii_col), // in : Collision detected
// Management IF
.GMII_MDC(mdio_phy_mdc), // out : Clock for MDIO
.GMII_MDIO_IN(mdio_gem_i), // in : Data
.GMII_MDIO_OUT(mdio_gem_o), // out : Data
.GMII_MDIO_OE(mdio_gem_t), // out : MDIO output enable
// User I/F
.SiTCP_RST(SiTCP_RST), // out : Reset for SiTCP and related circuits
// TCP connection control
.TCP_OPEN_REQ(1'b0), // in : Reserved input, shoud be 0
.TCP_OPEN_ACK(), // out : Acknowledge for open (=Socket busy)
.TCP_ERROR(), // out : TCP error, its active period is equal to MSL
.TCP_CLOSE_REQ(TCP_CLOSE_REQ), // out : Connection close request
.TCP_CLOSE_ACK(TCP_CLOSE_REQ), // in : Acknowledge for closing
// FIFO I/F
.TCP_RX_WC(TCP_RX_WC), // in : Rx FIFO write count[15:0] (Unused bits should be set 1)
.TCP_RX_WR(TCP_RX_WR), // out : Write enable
.TCP_RX_DATA(TCP_RX_DATA), // out : Write data[7:0]
.TCP_TX_FULL(TCP_TX_FULL), // out : Almost full flag
.TCP_TX_WR(TCP_TX_WR), // in : Write enable
.TCP_TX_DATA(TCP_TX_DATA), // in : Write data[7:0]
// RBCP
.RBCP_ACT(RBCP_ACT), // out : RBCP active
.RBCP_ADDR(RBCP_ADDR), // out : Address[31:0]
.RBCP_WD(RBCP_WD), // out : Data[7:0]
.RBCP_WE(RBCP_WE), // out : Write enable
.RBCP_RE(RBCP_RE), // out : Read enable
.RBCP_ACK(RBCP_ACK), // in : Access acknowledge
.RBCP_RD(RBCP_RD) // in : Read data[7:0]
);
// ------- BUS SIGNALLING ------- //
wire BUS_WR, BUS_RD, BUS_RST;
wire [31:0] BUS_ADD;
wire [7:0] BUS_DATA;
wire INVALID;
assign BUS_RST = SiTCP_RST;
tcp_to_bus itcp_to_bus(
.BUS_RST(BUS_RST),
.BUS_CLK(BUS_CLK),
.TCP_RX_WC(TCP_RX_WC),
.TCP_RX_WR(TCP_RX_WR),
.TCP_RX_DATA(TCP_RX_DATA),
.RBCP_ACT(RBCP_ACT),
.RBCP_ADDR(RBCP_ADDR),
.RBCP_WD(RBCP_WD),
.RBCP_WE(RBCP_WE),
.RBCP_RE(RBCP_RE),
.RBCP_ACK(RBCP_ACK),
.RBCP_RD(RBCP_RD),
.BUS_WR(BUS_WR),
.BUS_RD(BUS_RD),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA),
.INVALID(INVALID)
);
// ------- MODULE ADDRESSES ------- //
localparam CMD_BASEADDR = 32'h0000;
localparam CMD_HIGHADDR = 32'h8000-1;
localparam TLU_BASEADDR = 32'h40000;
localparam TLU_HIGHADDR = 32'h40100-1;
localparam RX_BASEADDR = 32'h41000;
localparam RX_HIGHADDR = 32'h41100-1;
localparam TDC_BASEADDR = 32'h41fff;
localparam TDC_HIGHADDR = 32'h420ff-1;
localparam GPIO_DLY_BASEADDR = 32'h430ef;
localparam GPIO_DLY_HIGHADDR = 32'h631ef-1;
// ------- USER MODULES ------- //
wire [47:0] GPIO_DLY_IO;
gpio
#(
.BASEADDR(GPIO_DLY_BASEADDR),
.HIGHADDR(GPIO_DLY_HIGHADDR),
.IO_WIDTH(48),
.IO_DIRECTION(48'hffffffffffff),
.IO_TRI(48'h000000000000),
.ABUSWIDTH(32)
) i_gpio
(
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.IO(GPIO_DLY_IO)
);
wire [4:0] IDELAYE_CINVCTRL;
wire [4:0] IDELAYE_LD;
wire [4:0] IDELAYE_CNTVALUEIN [4:0];
wire [2:0] SEL_CLK40;
assign IDELAYE_LD[0] = GPIO_DLY_IO[7];
assign IDELAYE_CINVCTRL[0] = GPIO_DLY_IO[6];
assign IDELAYE_CNTVALUEIN[0] = GPIO_DLY_IO[4:0];
assign IDELAYE_LD[1] = GPIO_DLY_IO[7+1*8];
assign IDELAYE_CINVCTRL[1] = GPIO_DLY_IO[6+1*8];
assign IDELAYE_CNTVALUEIN[1] = GPIO_DLY_IO[4+1*8:0+1*8];
assign IDELAYE_LD[2] = GPIO_DLY_IO[7+2*8];
assign IDELAYE_CINVCTRL[2] = GPIO_DLY_IO[6+2*8];
assign IDELAYE_CNTVALUEIN[2] = GPIO_DLY_IO[4+2*8:0+2*8];
assign IDELAYE_LD[3] = GPIO_DLY_IO[7+3*8];
assign IDELAYE_CINVCTRL[3] = GPIO_DLY_IO[6+3*8];
assign IDELAYE_CNTVALUEIN[3] = GPIO_DLY_IO[4+3*8:0+3*8];
assign IDELAYE_LD[4] = GPIO_DLY_IO[7+4*8];
assign IDELAYE_CINVCTRL[4] = GPIO_DLY_IO[6+4*8];
assign IDELAYE_CNTVALUEIN[4] = GPIO_DLY_IO[4+4*8:0+4*8];
assign SEL_CLK40 = GPIO_DLY_IO[42:40];
wire [7:0] CMD_DATA, CMD_CLK;
wire [7:0] TRIGGER_ENABLE; // from CMD FSM
wire [7:0] CMD_READY; // from CMD FSM
wire [7:0] CMD_START_FLAG;
wire [7:0] TRIGGER_ACCEPTED_FLAG;
wire [7:0] CMD_EXT_START_FLAG;
assign CMD_EXT_START_FLAG = TRIGGER_ACCEPTED_FLAG;
wire [7:0] EXT_TRIGGER_ENABLE;
reg [7:0] CLK_SR;
reg CLK40_OUT_SEL;
always@(posedge CLK320)
CLK_SR <= {CLK_SR[6:0],CLK40};
always@(posedge CLK320)
CLK40_OUT_SEL <= CLK_SR[SEL_CLK40];
wire BROADCAST_CMD;
genvar h;
generate
for (h = 0; h < 8; h = h + 1) begin: cmd_gen
cmd_seq #(
.BASEADDR(CMD_BASEADDR+32'h8000*h),
.HIGHADDR(CMD_HIGHADDR+32'h8000*h),
.ABUSWIDTH(32),
.OUTPUTS(1)
) i_cmd_seq (
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.CMD_CLK_IN(CLK40),
.CMD_CLK_OUT(CMD_CLK[h]),
.CMD_DATA(CMD_DATA[h]),
.CMD_EXT_START_FLAG(BROADCAST_CMD ? CMD_EXT_START_FLAG[0] : CMD_EXT_START_FLAG[h]),
.CMD_EXT_START_ENABLE(EXT_TRIGGER_ENABLE[h]),
.CMD_READY(CMD_READY[h]),
.CMD_START_FLAG(CMD_START_FLAG[h])
);
OBUFDS #(
.IOSTANDARD("LVDS_25"),
.SLEW("SLOW")
) OBUFDS_inst_cmd_clk_out_h (
.O(CMD_CLK_P[h]),
.OB(CMD_CLK_N[h]),
.I(CLK40_OUT_SEL)
);
OBUFDS #(
.IOSTANDARD("LVDS_25"),
.SLEW("SLOW")
) OBUFDS_inst_cmd_data_h (
.O(CMD_DATA_P[h]),
.OB(CMD_DATA_N[h]),
.I(CMD_DATA[h])
);
end
endgenerate
// external trigger and reset on LEMO RX0
wire EXT_TRG_CLK;
wire PLL_FEEDBACK3, LOCKED3;
PLLE2_BASE #(
.BANDWIDTH("OPTIMIZED"), // OPTIMIZED, HIGH, LOW
.CLKFBOUT_MULT(30), // Multiply value for all CLKOUT, (2-64)
.CLKFBOUT_PHASE(0.0), // Phase offset in degrees of CLKFB, (-360.000-360.000).
.CLKIN1_PERIOD(25.000), // Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz).
.CLKOUT0_DIVIDE(30), // Divide amount for CLKOUT0 (1-128)
.CLKOUT0_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT0 (0.001-0.999).
.CLKOUT0_PHASE(0.0), // Phase offset for CLKOUT0 (-360.000-360.000).
.DIVCLK_DIVIDE(1), // Master division value, (1-56)
.REF_JITTER1(0.0), // Reference input jitter in UI, (0.000-0.999).
.STARTUP_WAIT("FALSE") // Delay DONE until PLL Locks, ("TRUE"/"FALSE")
) PLLE2_BASE_inst_3 (
.CLKOUT0(EXT_TRG_CLK),
.CLKOUT1(),
.CLKOUT2(),
.CLKOUT3(),
.CLKOUT4(),
.CLKOUT5(),
.CLKFBOUT(PLL_FEEDBACK3),
.LOCKED(LOCKED3), // 1-bit output: LOCK
// Input 40 MHz clock
.CLKIN1(LEMO_RX[1]),
// Control Ports
.PWRDWN(0),
.RST(!RESET_N),
// Feedback
.CLKFBIN(PLL_FEEDBACK3)
);
wire TIMESTAMP_RESET_SYNC;
three_stage_synchronizer three_stage_trigger_ts_reset_synchronizer (
.CLK(EXT_TRG_CLK),
.IN(PMOD[4]),
.OUT(TIMESTAMP_RESET_SYNC)
);
//reg TIMESTAMP_RESET_SYNC_FF;
//always @ (posedge EXT_TRG_CLK)
// TIMESTAMP_RESET_SYNC_FF <= TIMESTAMP_RESET_SYNC;
//wire TIMESTAMP_RESET_FLAG;
//assign TIMESTAMP_RESET_FLAG = ~TIMESTAMP_RESET_SYNC_FF & TIMESTAMP_RESET_SYNC;
reg RST_FF, RST_FF2, BUS_RST_FF, BUS_RST_FF2;
always @(posedge BUS_CLK) begin
BUS_RST_FF <= BUS_RST;
BUS_RST_FF2 <= BUS_RST_FF;
end
wire BUS_RST_FLAG;
assign BUS_RST_FLAG = BUS_RST_FF2 & ~BUS_RST_FF; // trailing edge
wire BUS_RST_FLAG_SYNC;
flag_domain_crossing bus_reset_te_flag_domain_crossing (
.CLK_A(BUS_CLK),
.CLK_B(EXT_TRG_CLK),
.FLAG_IN_CLK_A(BUS_RST_FLAG),
.FLAG_OUT_CLK_B(BUS_RST_FLAG_SYNC)
);
always @ (posedge EXT_TRG_CLK)
begin
if (BUS_RST_FLAG_SYNC || TIMESTAMP_RESET_SYNC)
EXT_TRG_TIMESTAMP <= 32'b0;
else
EXT_TRG_TIMESTAMP <= EXT_TRG_TIMESTAMP + 1;
end
wire LEMO_RX0_SYNC;
three_stage_synchronizer #(
.WIDTH(1)
) three_stage_ext_trigger_synchronizer (
.CLK(EXT_TRG_CLK),
.IN(LEMO_RX[0]),
.OUT(LEMO_RX0_SYNC)
);
reg LEMO_RX0_SYNC_FF;
always @ (posedge EXT_TRG_CLK)
begin
LEMO_RX0_SYNC_FF <= LEMO_RX0_SYNC;
end
wire LEMO_RX0_SYNC_LE;
assign LEMO_RX0_SYNC_LE = ~LEMO_RX0_SYNC_FF & LEMO_RX0_SYNC; // leading edge
reg [31:0] EXT_TRG_TIMESTAMP_BUF;
always @ (posedge EXT_TRG_CLK)
begin
if (LEMO_RX0_SYNC_LE==1'b1)
EXT_TRG_TIMESTAMP_BUF <= EXT_TRG_TIMESTAMP;
else
EXT_TRG_TIMESTAMP_BUF <= EXT_TRG_TIMESTAMP_BUF;
end
wire LEMO_RX0_LE_CLK40;
flag_domain_crossing ext_trigger_le_flag_domain_crossing (
.CLK_A(EXT_TRG_CLK),
.CLK_B(CLK40),
.FLAG_IN_CLK_A(LEMO_RX0_SYNC_LE),
.FLAG_OUT_CLK_B(LEMO_RX0_LE_CLK40)
);
reg [31:0] EXT_TRG_TIMESTAMP_BUF_CLK40;
always @ (posedge CLK40)
begin
if (LEMO_RX0_LE_CLK40==1'b1)
EXT_TRG_TIMESTAMP_BUF_CLK40 <= EXT_TRG_TIMESTAMP_BUF;
else
EXT_TRG_TIMESTAMP_BUF_CLK40 <= EXT_TRG_TIMESTAMP_BUF_CLK40;
end
wire [7:0] TRIGGER_ACKNOWLEDGE_FLAG; // to TLU FSM
reg [7:0] CMD_READY_FF;
always @ (posedge CLK40)
begin
CMD_READY_FF <= CMD_READY;
end
assign TRIGGER_ACKNOWLEDGE_FLAG = CMD_READY & ~CMD_READY_FF;
reg CMD_READY_BROADCAST;
always @ (posedge CLK40)
begin
if (!BROADCAST_CMD)
CMD_READY_BROADCAST <= 1'b1;
else
CMD_READY_BROADCAST <= ~|(~CMD_READY & EXT_TRIGGER_ENABLE);
end
wire CMD_READY_BROADCAST_FLAG;
reg CMD_READY_BROADCAST_FF;
always @ (posedge CLK40)
begin
CMD_READY_BROADCAST_FF <= CMD_READY_BROADCAST;
end
assign CMD_READY_BROADCAST_FLAG = CMD_READY_BROADCAST & ~CMD_READY_BROADCAST_FF;
wire [7:0] RX_ENABLED, RX_ENABLED_CLK40;
three_stage_synchronizer #(
.WIDTH(8)
) three_stage_sync_rx_enable_clk40 (
.CLK(CLK40),
.IN(RX_ENABLED),
.OUT(RX_ENABLED_CLK40)
);
wire [7:0] FE_FIFO_EMPTY, FE_FIFO_EMPTY_CLK40;
three_stage_synchronizer #(
.WIDTH(8)
) three_stage_sync_fe_fifo_empty_clk40 (
.CLK(CLK40),
.IN(FE_FIFO_EMPTY),
.OUT(FE_FIFO_EMPTY_CLK40)
);
parameter max_wait_cycles = 64;
reg STARTED_READY_COUNTER_BROADCAST;
reg CMD_FIFO_READY_BROADCAST;
integer fifo_empty_counter_broadcast;
always @(posedge CLK40)
begin
STARTED_READY_COUNTER_BROADCAST <= STARTED_READY_COUNTER_BROADCAST;
CMD_FIFO_READY_BROADCAST <= CMD_FIFO_READY_BROADCAST;
fifo_empty_counter_broadcast <= fifo_empty_counter_broadcast;
if (!BROADCAST_CMD)
begin
STARTED_READY_COUNTER_BROADCAST <= 1'b0;
CMD_FIFO_READY_BROADCAST <= 1'b1;
fifo_empty_counter_broadcast <= 0;
end
else if (STARTED_READY_COUNTER_BROADCAST == 1'b0 && CMD_READY_BROADCAST_FLAG == 1'b1)
begin
STARTED_READY_COUNTER_BROADCAST <= 1'b1;
CMD_FIFO_READY_BROADCAST <= 1'b0;
fifo_empty_counter_broadcast <= 0;
end
else if (STARTED_READY_COUNTER_BROADCAST == 1'b1 && |(~FE_FIFO_EMPTY_CLK40 & RX_ENABLED_CLK40))
begin
fifo_empty_counter_broadcast <= 0;
end
else if (STARTED_READY_COUNTER_BROADCAST == 1'b1 && fifo_empty_counter_broadcast == max_wait_cycles)
begin
STARTED_READY_COUNTER_BROADCAST <= 1'b0;
CMD_FIFO_READY_BROADCAST <= 1'b1;
end
else if (STARTED_READY_COUNTER_BROADCAST == 1'b1 && &(FE_FIFO_EMPTY_CLK40 | ~RX_ENABLED_CLK40))
begin
fifo_empty_counter_broadcast <= fifo_empty_counter_broadcast + 1'b1;
end
end
wire CMD_FIFO_READY_BROADCAST_FLAG;
reg CMD_FIFO_READY_BROADCAST_FF;
always @ (posedge CLK40)
begin
CMD_FIFO_READY_BROADCAST_FF <= CMD_FIFO_READY_BROADCAST;
end
assign CMD_FIFO_READY_BROADCAST_FLAG = CMD_FIFO_READY_BROADCAST & ~CMD_FIFO_READY_BROADCAST_FF;
reg STARTED_READY_COUNTER [7:0];
reg CMD_FIFO_READY [7:0];
integer fifo_empty_counter [7:0];
wire CMD_FIFO_READY_FLAG [7:0];
reg CMD_FIFO_READY_FF [7:0];
wire [7:0] TRIGGER_FIFO_READ;
wire [7:0] TRIGGER_FIFO_EMPTY;
wire [31:0] TRIGGER_FIFO_DATA [7:0];
wire [7:0] TRIGGER_FIFO_PREEMPT_REQ;
wire [31:0] TIMESTAMP [7:0];
wire [7:0] TDC_OUT;
wire [7:0] RX_READY, RX_8B10B_DECODER_ERR, RX_FIFO_OVERFLOW_ERR, RX_FIFO_FULL;
wire FIFO_FULL;
wire TLU_BUSY, TLU_CLOCK;
wire [7:0] TRIGGER_ENABLED, TLU_ENABLED;
wire [9:0] TRIGGER_SELECTED [7:0];
reg [31:0] EXT_TRG_TIMESTAMP;
assign RJ45_BUSY_LEMO_TX1 = BROADCAST_CMD ? TLU_BUSY : 1'b1;
assign LEMO_TX[1] = RJ45_BUSY_LEMO_TX1; // add LEMO TX0 and TX1 for MMC3 revision 1.2; LEMO TX0 and TX1 are not connected to RJ45_CLK_LEMO_TX0 and RJ45_BUSY_LEMO_TX1 anymore
assign RJ45_CLK_LEMO_TX0 = TLU_CLOCK;
assign LEMO_TX[0] = RJ45_CLK_LEMO_TX0; // add LEMO TX0 and TX1 for MMC3 revision 1.2; LEMO TX0 and TX1 are not connected to RJ45_CLK_LEMO_TX0 and RJ45_BUSY_LEMO_TX1 anymore
genvar k;
generate
for (k = 1; k < 8; k = k + 1) begin: tlu_gen
always @(posedge CLK40)
begin
if (~EXT_TRIGGER_ENABLE[k] || ~TRIGGER_ENABLED[k])
begin
STARTED_READY_COUNTER[k] <= 1'b0;
CMD_FIFO_READY[k] <= 1'b1;
fifo_empty_counter[k] <= 0;
end
else if (STARTED_READY_COUNTER[k] == 1'b0 && TRIGGER_ACKNOWLEDGE_FLAG[k] == 1'b1)
begin
STARTED_READY_COUNTER[k] <= 1'b1;
CMD_FIFO_READY[k] <= 1'b0;
fifo_empty_counter[k] <= 0;
end
else if (STARTED_READY_COUNTER[k] == 1'b1 && |(~FE_FIFO_EMPTY_CLK40[k] & RX_ENABLED_CLK40[k]))
begin
fifo_empty_counter[k] <= 0;
end
else if (STARTED_READY_COUNTER[k] == 1'b1 && fifo_empty_counter[k] == max_wait_cycles)
begin
STARTED_READY_COUNTER[k] <= 1'b0;
CMD_FIFO_READY[k] <= 1'b1;
end
else if (STARTED_READY_COUNTER[k] == 1'b1 && &(FE_FIFO_EMPTY_CLK40[k] | ~RX_ENABLED_CLK40[k]))
begin
fifo_empty_counter[k] <= fifo_empty_counter[k] + 1'b1;
end
end
always @ (posedge CLK40)
begin
CMD_FIFO_READY_FF[k] <= CMD_FIFO_READY[k];
end
assign CMD_FIFO_READY_FLAG[k] = CMD_FIFO_READY[k] & ~CMD_FIFO_READY_FF[k];
tlu_controller #(
.BASEADDR(TLU_BASEADDR+32'h0100*k),
.HIGHADDR(TLU_HIGHADDR+32'h0100*k),
.DIVISOR(8),
.ABUSWIDTH(32),
.WIDTH(10),
.TLU_TRIGGER_MAX_CLOCK_CYCLES(32)
) i_tlu_controller (
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.TRIGGER_CLK(CLK40),
.FIFO_READ(TRIGGER_FIFO_READ[k]),
.FIFO_EMPTY(TRIGGER_FIFO_EMPTY[k]),
.FIFO_DATA(TRIGGER_FIFO_DATA[k]),
.FIFO_PREEMPT_REQ(TRIGGER_FIFO_PREEMPT_REQ[k]),
.TRIGGER_ENABLED(TRIGGER_ENABLED[k]),
.TRIGGER_SELECTED(TRIGGER_SELECTED[k]),
.TLU_ENABLED(TLU_ENABLED[k]),
.TRIGGER({LEMO_RX0_LE_CLK40, TDC_OUT, LEMO_RX[0]}),
.TRIGGER_VETO({1'b0, RX_FIFO_FULL, FIFO_FULL}),
.TIMESTAMP_RESET(1'b0),
.EXT_TRIGGER_ENABLE(BROADCAST_CMD ? 1'b0 : EXT_TRIGGER_ENABLE[k]),
.TRIGGER_ACKNOWLEDGE(BROADCAST_CMD ? 1'b0 : CMD_FIFO_READY_FLAG[k]),
.TRIGGER_ACCEPTED_FLAG(TRIGGER_ACCEPTED_FLAG[k]),
.TLU_TRIGGER(1'b0),
.TLU_RESET(1'b0),
.TLU_BUSY(),
.TLU_CLOCK(),
.EXT_TIMESTAMP(EXT_TRG_TIMESTAMP_BUF_CLK40),
.TIMESTAMP(TIMESTAMP[k])
);
end
endgenerate
always @(posedge CLK40)
begin
if (~EXT_TRIGGER_ENABLE[0] || ~TRIGGER_ENABLED[0])
begin
STARTED_READY_COUNTER[0] <= 1'b0;
CMD_FIFO_READY[0] <= 1'b1;
fifo_empty_counter[0] <= 0;
end
else if (STARTED_READY_COUNTER[0] == 1'b0 && TRIGGER_ACKNOWLEDGE_FLAG[0] == 1'b1)
begin
STARTED_READY_COUNTER[0] <= 1'b1;
CMD_FIFO_READY[0] <= 1'b0;
fifo_empty_counter[0] <= 0;
end
else if (STARTED_READY_COUNTER[0] == 1'b1 && |(~FE_FIFO_EMPTY_CLK40[0] & RX_ENABLED_CLK40[0]))
begin
fifo_empty_counter[0] <= 0;
end
else if (STARTED_READY_COUNTER[0] == 1'b1 && fifo_empty_counter[0] == max_wait_cycles)
begin
STARTED_READY_COUNTER[0] <= 1'b0;
CMD_FIFO_READY[0] <= 1'b1;
end
else if (STARTED_READY_COUNTER[0] == 1'b1 && &(FE_FIFO_EMPTY_CLK40[0] | ~RX_ENABLED_CLK40[0]))
begin
fifo_empty_counter[0] <= fifo_empty_counter[0] + 1;
end
end
always @ (posedge CLK40)
begin
CMD_FIFO_READY_FF[0] <= CMD_FIFO_READY[0];
end
assign CMD_FIFO_READY_FLAG[0] = CMD_FIFO_READY[0] & ~CMD_FIFO_READY_FF[0];
tlu_controller #(
.BASEADDR(TLU_BASEADDR),
.HIGHADDR(TLU_HIGHADDR),
.DIVISOR(8),
.ABUSWIDTH(32),
.WIDTH(10),
.TLU_TRIGGER_MAX_CLOCK_CYCLES(32)
) i_tlu_controller_0 (
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.TRIGGER_CLK(CLK40),
.FIFO_READ(TRIGGER_FIFO_READ[0]),
.FIFO_EMPTY(TRIGGER_FIFO_EMPTY[0]),
.FIFO_DATA(TRIGGER_FIFO_DATA[0]),
.FIFO_PREEMPT_REQ(TRIGGER_FIFO_PREEMPT_REQ[0]),
.TRIGGER_ENABLED(TRIGGER_ENABLED[0]),
.TRIGGER_SELECTED(TRIGGER_SELECTED[0]),
.TLU_ENABLED(TLU_ENABLED[0]),
.TRIGGER({LEMO_RX0_LE_CLK40, TDC_OUT, LEMO_RX[0]}),
.TRIGGER_VETO({1'b0, RX_FIFO_FULL, FIFO_FULL}),
.TIMESTAMP_RESET(PMOD[4]),
.EXT_TRIGGER_ENABLE(BROADCAST_CMD ? |EXT_TRIGGER_ENABLE : EXT_TRIGGER_ENABLE[0]),
.TRIGGER_ACKNOWLEDGE(BROADCAST_CMD ? CMD_FIFO_READY_BROADCAST_FLAG : CMD_FIFO_READY_FLAG[0]),
.TRIGGER_ACCEPTED_FLAG(TRIGGER_ACCEPTED_FLAG[0]),
.TLU_TRIGGER(RJ45_TRIGGER),
.TLU_RESET(RJ45_RESET),
.TLU_BUSY(TLU_BUSY),
.TLU_CLOCK(TLU_CLOCK),
.EXT_TIMESTAMP(EXT_TRG_TIMESTAMP_BUF_CLK40),
.TIMESTAMP(TIMESTAMP[0])
);
assign BROADCAST_CMD = (TRIGGER_ENABLED == 1);
//reg [31:0] timestamp_gray;
//always@(posedge BUS_CLK)
// timestamp_gray <= ((TIMESTAMP[0])>>1) ^ (TIMESTAMP[0]);
wire [7:0] FE_FIFO_READ;
//wire [7:0] FE_FIFO_EMPTY;
wire [31:0] FE_FIFO_DATA [7:0];
wire [7:0] TDC_FIFO_READ;
wire [7:0] TDC_FIFO_EMPTY;
wire [31:0] TDC_FIFO_DATA [7:0];
genvar i;
generate
for (i = 0; i < 8; i = i + 1) begin: rx_gen
wire DOBOUT;
reg DOBOUT_DLY;
fei4_rx #(
.BASEADDR(RX_BASEADDR+32'h0100*i),
.HIGHADDR(RX_HIGHADDR+32'h0100*i),
.DSIZE(10),
.DATA_IDENTIFIER(i),
.ABUSWIDTH(32)
) i_fei4_rx (
.RX_CLK(CLK160),
.RX_CLK2X(CLK320),
.DATA_CLK(CLK16),
.RX_DATA(DOBOUT_DLY),
.RX_READY(RX_READY[i]),
.RX_8B10B_DECODER_ERR(RX_8B10B_DECODER_ERR[i]),
.RX_FIFO_OVERFLOW_ERR(RX_FIFO_OVERFLOW_ERR[i]),
.FIFO_CLK(1'b0),
.FIFO_READ(FE_FIFO_READ[i]),
.FIFO_EMPTY(FE_FIFO_EMPTY[i]),
.FIFO_DATA(FE_FIFO_DATA[i]),
.RX_FIFO_FULL(RX_FIFO_FULL[i]),
.RX_ENABLED(RX_ENABLED[i]),
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR)
);
IBUFDS #(
.DIFF_TERM("TRUE"),
.IBUF_LOW_PWR("FALSE"),
.IOSTANDARD("LVDS_25")
) IBUFDS_inst_i (
.O(DOBOUT),
.I(DOBOUT_P[i]),
.IB(DOBOUT_N[i])
);
/*
reg [1:0] DOBOUT_DDR;
wire DOBOUT_IDELAYE;
IDELAYE2 #(
.CINVCTRL_SEL("FALSE"), // Enable dynamic clock inversion (FALSE, TRUE)
.DELAY_SRC("IDATAIN"), // Delay input (IDATAIN, DATAIN)
.HIGH_PERFORMANCE_MODE("FALSE"), // Reduced jitter ("TRUE"), Reduced power ("FALSE")
.IDELAY_TYPE("VAR_LOAD"), // FIXED, VARIABLE, VAR_LOAD, VAR_LOAD_PIPE
.IDELAY_VALUE(0), // Input delay tap setting (0-31)
.PIPE_SEL("FALSE"), // Select pipelined mode, FALSE, TRUE
.REFCLK_FREQUENCY(200.0), // IDELAYCTRL clock input frequency in MHz (190.0-210.0, 290.0-310.0).
.SIGNAL_PATTERN("DATA") // DATA, CLOCK input signal
)
IDELAYE2_inst (
.CNTVALUEOUT(), // 5-bit output: Counter value output
.DATAOUT(DOBOUT_IDELAYE), // 1-bit output: Delayed data output
.C(BUS_CLK), // 1-bit input: Clock input
.CE(1'b0), // 1-bit input: Active high enable increment/decrement input
.CINVCTRL(1'b0), // 1-bit input: Dynamic clock inversion input
.CNTVALUEIN(IDELAYE_CNTVALUEIN[i]), // 5-bit input: Counter value input
.DATAIN(1'b0), // 1-bit input: Internal delay data input
.IDATAIN(DOBOUT), // 1-bit input: Data input from the I/O
.INC(1'b0), // 1-bit input: Increment / Decrement tap delay input
.LD(IDELAYE_LD[i]), // 1-bit input: Load IDELAY_VALUE input
.LDPIPEEN(1'b0), // 1-bit input: Enable PIPELINE register to load data input
.REGRST(!LOCKED2) // 1-bit input: Active-high reset tap-delay input
);
always@(posedge CLK160)
DOBOUT_DDR[0] <= DOBOUT_IDELAYE;
always@(negedge CLK160)
DOBOUT_DDR[1] <= DOBOUT_IDELAYE;
always@(posedge CLK160)
DOBOUT_DLY <= IDELAYE_CINVCTRL[i] ? DOBOUT_DDR[1] : DOBOUT_DDR[0];
*/
always@(*) DOBOUT_DLY = DOBOUT;
end
endgenerate
wire [7:0] RJ45_HITOR;
genvar j;
generate
for (j = 0; j < 7; j = j + 1) begin: tdc_gen
tdc_s3 #(
.BASEADDR(TDC_BASEADDR+32'h0100*j),
.HIGHADDR(TDC_HIGHADDR+32'h0100*j),
.ABUSWIDTH(32),
.CLKDV(4),
.DATA_IDENTIFIER(4'b0001 + j),
.FAST_TDC(1),
.FAST_TRIGGER(0)
) i_tdc (
.CLK320(CLK320),
.CLK160(CLK160),
.DV_CLK(CLK40),
.TDC_IN(RJ45_HITOR[j]),
.TDC_OUT(TDC_OUT[j]),
.TRIG_IN(1'b0),
.TRIG_OUT(),
.FAST_TRIGGER_IN(),
.FAST_TRIGGER_OUT(),
.FIFO_READ(TDC_FIFO_READ[j]),
.FIFO_EMPTY(TDC_FIFO_EMPTY[j]),
.FIFO_DATA(TDC_FIFO_DATA[j]),
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.ARM_TDC(CMD_START_FLAG[j]), // arm TDC by sending commands
.EXT_EN(1'b0),
.TIMESTAMP(TIMESTAMP[j][15:0])
);
IBUFDS #(
.DIFF_TERM("TRUE"),
.IBUF_LOW_PWR("FALSE"),
.IOSTANDARD("LVDS_25")
) IBUFDS_inst_RJ45_HITOR (
.O(RJ45_HITOR[j]),
.I(RJ45_HITOR_P[j]),
.IB(RJ45_HITOR_N[j])
);
end
endgenerate
tdc_s3 #(
.BASEADDR(TDC_BASEADDR+32'h0100*7),
.HIGHADDR(TDC_HIGHADDR+32'h0100*7),
.ABUSWIDTH(32),
.CLKDV(4),
.DATA_IDENTIFIER(4'b0001),
.FAST_TDC(1),
.FAST_TRIGGER(0)
) i_tdc_7 (
.CLK320(CLK320),
.CLK160(CLK160),
.DV_CLK(CLK40),
.TDC_IN(RJ45_HITOR[7]),
.TDC_OUT(TDC_OUT[7]),
.TRIG_IN(1'b0),
.TRIG_OUT(),
.FAST_TRIGGER_IN(),
.FAST_TRIGGER_OUT(),
.FIFO_READ(TDC_FIFO_READ[7]),
.FIFO_EMPTY(TDC_FIFO_EMPTY[7]),
.FIFO_DATA(TDC_FIFO_DATA[7]),
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.ARM_TDC(CMD_START_FLAG[7]), // arm TDC by sending commands
.EXT_EN(1'b0),
.TIMESTAMP(TIMESTAMP[7][15:0])
);
IBUFDS #(
.DIFF_TERM("TRUE"),
.IBUF_LOW_PWR("FALSE"),
.IOSTANDARD("LVDS_25")
) IBUFDS_inst_RJ45_HITOR_7 (
.O(RJ45_HITOR[7]),
.I(RJ45_HITOR_P[7]),
.IB(RJ45_HITOR_N[7])
);
wire ARB_READY_OUT, ARB_WRITE_OUT;
wire [31:0] ARB_DATA_OUT;
wire [23:0] READ_GRANT;
rrp_arbiter #(
.WIDTH(24)
) i_rrp_arbiter (
.RST(BUS_RST),
.CLK(BUS_CLK),
.WRITE_REQ({~TDC_FIFO_EMPTY, ~FE_FIFO_EMPTY, ~TRIGGER_FIFO_EMPTY}),
.HOLD_REQ({16'b0, TRIGGER_FIFO_PREEMPT_REQ}),
.DATA_IN({TDC_FIFO_DATA[7], TDC_FIFO_DATA[6], TDC_FIFO_DATA[5], TDC_FIFO_DATA[4], TDC_FIFO_DATA[3], TDC_FIFO_DATA[2], TDC_FIFO_DATA[1], TDC_FIFO_DATA[0], FE_FIFO_DATA[7], FE_FIFO_DATA[6], FE_FIFO_DATA[5], FE_FIFO_DATA[4], FE_FIFO_DATA[3], FE_FIFO_DATA[2], FE_FIFO_DATA[1], FE_FIFO_DATA[0], TRIGGER_FIFO_DATA[7], TRIGGER_FIFO_DATA[6], TRIGGER_FIFO_DATA[5], TRIGGER_FIFO_DATA[4], TRIGGER_FIFO_DATA[3], TRIGGER_FIFO_DATA[2], TRIGGER_FIFO_DATA[1], TRIGGER_FIFO_DATA[0]}),
.READ_GRANT(READ_GRANT),
.READY_OUT(ARB_READY_OUT),
.WRITE_OUT(ARB_WRITE_OUT),
.DATA_OUT(ARB_DATA_OUT)
);
assign TRIGGER_FIFO_READ = READ_GRANT[7:0];
assign FE_FIFO_READ = READ_GRANT[15:8];
assign TDC_FIFO_READ = READ_GRANT[23:16];
//cdc_fifo is for timing reasons
wire [31:0] cdc_data_out;
wire full_32to8, cdc_fifo_empty;
wire FIFO_EMPTY;
cdc_syncfifo #(.DSIZE(32), .ASIZE(3)) cdc_syncfifo_i
(
.rdata(cdc_data_out),
.wfull(FIFO_FULL),
.rempty(cdc_fifo_empty),
.wdata(ARB_DATA_OUT),
.winc(ARB_WRITE_OUT), .wclk(BUS_CLK), .wrst(BUS_RST),
.rinc(!full_32to8), .rclk(BUS_CLK), .rrst(BUS_RST)
);
assign ARB_READY_OUT = !FIFO_FULL;
fifo_32_to_8 #(.DEPTH(256*1024)) i_data_fifo (
.RST(BUS_RST),
.CLK(BUS_CLK),
.WRITE(!cdc_fifo_empty),
.READ(TCP_TX_WR),
.DATA_IN(cdc_data_out),
.FULL(full_32to8),
.EMPTY(FIFO_EMPTY),
.DATA_OUT(TCP_TX_DATA)
);
assign TCP_TX_WR = !TCP_TX_FULL && !FIFO_EMPTY;
wire CLK_1HZ;
clock_divider #(
.DIVISOR(40000000)
) i_clock_divisor_40MHz_to_1Hz (
.CLK(CLK40),
.RESET(1'b0),
.CE(),
.CLOCK(CLK_1HZ)
);
wire CLK_3HZ;
clock_divider #(
.DIVISOR(13333333)
) i_clock_divisor_40MHz_to_3Hz (
.CLK(CLK40),
.RESET(1'b0),
.CE(),
.CLOCK(CLK_3HZ)
);
reg [7:0] RX_ENABLED_CLK40_FF;
wire [7:0] RX_ENABLED_CLK40_FLAG;
always @ (posedge CLK40)
begin
RX_ENABLED_CLK40_FF <= RX_ENABLED_CLK40;
end
assign RX_ENABLED_CLK40_FLAG = RX_ENABLED_CLK40 & ~RX_ENABLED_CLK40_FF;
reg [7:0] RX_ENABLED_CLK40_BUF;
always @ (posedge CLK40)
begin
if (|RX_ENABLED_CLK40_FLAG)
RX_ENABLED_CLK40_BUF <= RX_ENABLED_CLK40;
else
RX_ENABLED_CLK40_BUF <= RX_ENABLED_CLK40_BUF;
end
assign LED[7:4] = 4'hf;
assign LED[0] = ~((CLK_1HZ | FIFO_FULL) & LOCKED & LOCKED2);
assign LED[1] = ~(((|(~RX_READY & RX_ENABLED_CLK40_BUF) || |(RX_8B10B_DECODER_ERR & RX_ENABLED_CLK40_BUF))? CLK_3HZ : CLK_1HZ) | (|(RX_FIFO_OVERFLOW_ERR & RX_ENABLED_CLK40_BUF)) | (|(RX_FIFO_FULL & RX_ENABLED_CLK40_BUF)));
assign LED[2] = ~ LEMO_RX[1];
assign LED[3] = 1'b1;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A221O_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__A221O_FUNCTIONAL_PP_V
/**
* a221o: 2-input AND into first two inputs of 3-input OR.
*
* X = ((A1 & A2) | (B1 & B2) | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__a221o (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire and1_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
and and1 (and1_out , A1, A2 );
or or0 (or0_out_X , and1_out, and0_out, C1);
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND );
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__A221O_FUNCTIONAL_PP_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__UDP_DFF_NSR_SYMBOL_V
`define SKY130_FD_SC_LS__UDP_DFF_NSR_SYMBOL_V
/**
* udp_dff$NSR: Negative edge triggered D flip-flop (Q output UDP)
* with both active high reset and set (set dominate).
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__udp_dff$NSR (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET,
input SET ,
//# {{clocks|Clocking}}
input CLK_N
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__UDP_DFF_NSR_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DIODE_SYMBOL_V
`define SKY130_FD_SC_LP__DIODE_SYMBOL_V
/**
* diode: Antenna tie-down diode.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__diode (
//# {{power|Power}}
input DIODE
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DIODE_SYMBOL_V
|
/*
Copyright (c) 2015-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI4-Stream GMII frame receiver (GMII in, AXI out)
*/
module axis_gmii_rx #
(
parameter DATA_WIDTH = 8,
parameter PTP_TS_ENABLE = 0,
parameter PTP_TS_WIDTH = 96,
parameter USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1
)
(
input wire clk,
input wire rst,
/*
* GMII input
*/
input wire [DATA_WIDTH-1:0] gmii_rxd,
input wire gmii_rx_dv,
input wire gmii_rx_er,
/*
* AXI output
*/
output wire [DATA_WIDTH-1:0] m_axis_tdata,
output wire m_axis_tvalid,
output wire m_axis_tlast,
output wire [USER_WIDTH-1:0] m_axis_tuser,
/*
* PTP
*/
input wire [PTP_TS_WIDTH-1:0] ptp_ts,
/*
* Control
*/
input wire clk_enable,
input wire mii_select,
/*
* Status
*/
output wire start_packet,
output wire error_bad_frame,
output wire error_bad_fcs
);
// bus width assertions
initial begin
if (DATA_WIDTH != 8) begin
$error("Error: Interface width must be 8");
$finish;
end
end
localparam [7:0]
ETH_PRE = 8'h55,
ETH_SFD = 8'hD5;
localparam [2:0]
STATE_IDLE = 3'd0,
STATE_PAYLOAD = 3'd1,
STATE_WAIT_LAST = 3'd2;
reg [2:0] state_reg = STATE_IDLE, state_next;
// datapath control signals
reg reset_crc;
reg update_crc;
reg mii_odd = 1'b0;
reg mii_locked = 1'b0;
reg [DATA_WIDTH-1:0] gmii_rxd_d0 = {DATA_WIDTH{1'b0}};
reg [DATA_WIDTH-1:0] gmii_rxd_d1 = {DATA_WIDTH{1'b0}};
reg [DATA_WIDTH-1:0] gmii_rxd_d2 = {DATA_WIDTH{1'b0}};
reg [DATA_WIDTH-1:0] gmii_rxd_d3 = {DATA_WIDTH{1'b0}};
reg [DATA_WIDTH-1:0] gmii_rxd_d4 = {DATA_WIDTH{1'b0}};
reg gmii_rx_dv_d0 = 1'b0;
reg gmii_rx_dv_d1 = 1'b0;
reg gmii_rx_dv_d2 = 1'b0;
reg gmii_rx_dv_d3 = 1'b0;
reg gmii_rx_dv_d4 = 1'b0;
reg gmii_rx_er_d0 = 1'b0;
reg gmii_rx_er_d1 = 1'b0;
reg gmii_rx_er_d2 = 1'b0;
reg gmii_rx_er_d3 = 1'b0;
reg gmii_rx_er_d4 = 1'b0;
reg [DATA_WIDTH-1:0] m_axis_tdata_reg = {DATA_WIDTH{1'b0}}, m_axis_tdata_next;
reg m_axis_tvalid_reg = 1'b0, m_axis_tvalid_next;
reg m_axis_tlast_reg = 1'b0, m_axis_tlast_next;
reg m_axis_tuser_reg = 1'b0, m_axis_tuser_next;
reg start_packet_reg = 1'b0, start_packet_next;
reg error_bad_frame_reg = 1'b0, error_bad_frame_next;
reg error_bad_fcs_reg = 1'b0, error_bad_fcs_next;
reg [PTP_TS_WIDTH-1:0] ptp_ts_reg = 0, ptp_ts_next;
reg [31:0] crc_state = 32'hFFFFFFFF;
wire [31:0] crc_next;
assign m_axis_tdata = m_axis_tdata_reg;
assign m_axis_tvalid = m_axis_tvalid_reg;
assign m_axis_tlast = m_axis_tlast_reg;
assign m_axis_tuser = PTP_TS_ENABLE ? {ptp_ts_reg, m_axis_tuser_reg} : m_axis_tuser_reg;
assign start_packet = start_packet_reg;
assign error_bad_frame = error_bad_frame_reg;
assign error_bad_fcs = error_bad_fcs_reg;
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.LFSR_FEED_FORWARD(0),
.REVERSE(1),
.DATA_WIDTH(8),
.STYLE("AUTO")
)
eth_crc_8 (
.data_in(gmii_rxd_d4),
.state_in(crc_state),
.data_out(),
.state_out(crc_next)
);
always @* begin
state_next = STATE_IDLE;
reset_crc = 1'b0;
update_crc = 1'b0;
m_axis_tdata_next = {DATA_WIDTH{1'b0}};
m_axis_tvalid_next = 1'b0;
m_axis_tlast_next = 1'b0;
m_axis_tuser_next = 1'b0;
start_packet_next = 1'b0;
error_bad_frame_next = 1'b0;
error_bad_fcs_next = 1'b0;
ptp_ts_next = ptp_ts_reg;
if (!clk_enable) begin
// clock disabled - hold state
state_next = state_reg;
end else if (mii_select && !mii_odd) begin
// MII even cycle - hold state
state_next = state_reg;
end else begin
case (state_reg)
STATE_IDLE: begin
// idle state - wait for packet
reset_crc = 1'b1;
if (gmii_rx_dv_d4 && !gmii_rx_er_d4 && gmii_rxd_d4 == ETH_SFD) begin
ptp_ts_next = ptp_ts;
start_packet_next = 1'b1;
state_next = STATE_PAYLOAD;
end else begin
state_next = STATE_IDLE;
end
end
STATE_PAYLOAD: begin
// read payload
update_crc = 1'b1;
m_axis_tdata_next = gmii_rxd_d4;
m_axis_tvalid_next = 1'b1;
if (gmii_rx_dv_d4 && gmii_rx_er_d4) begin
// error
m_axis_tlast_next = 1'b1;
m_axis_tuser_next = 1'b1;
error_bad_frame_next = 1'b1;
state_next = STATE_WAIT_LAST;
end else if (!gmii_rx_dv) begin
// end of packet
m_axis_tlast_next = 1'b1;
if (gmii_rx_er_d0 || gmii_rx_er_d1 || gmii_rx_er_d2 || gmii_rx_er_d3) begin
// error received in FCS bytes
m_axis_tuser_next = 1'b1;
error_bad_frame_next = 1'b1;
end else if ({gmii_rxd_d0, gmii_rxd_d1, gmii_rxd_d2, gmii_rxd_d3} == ~crc_next) begin
// FCS good
m_axis_tuser_next = 1'b0;
end else begin
// FCS bad
m_axis_tuser_next = 1'b1;
error_bad_frame_next = 1'b1;
error_bad_fcs_next = 1'b1;
end
state_next = STATE_IDLE;
end else begin
state_next = STATE_PAYLOAD;
end
end
STATE_WAIT_LAST: begin
// wait for end of packet
if (~gmii_rx_dv) begin
state_next = STATE_IDLE;
end else begin
state_next = STATE_WAIT_LAST;
end
end
endcase
end
end
always @(posedge clk) begin
if (rst) begin
state_reg <= STATE_IDLE;
m_axis_tvalid_reg <= 1'b0;
start_packet_reg <= 1'b0;
error_bad_frame_reg <= 1'b0;
error_bad_fcs_reg <= 1'b0;
crc_state <= 32'hFFFFFFFF;
mii_locked <= 1'b0;
mii_odd <= 1'b0;
gmii_rx_dv_d0 <= 1'b0;
gmii_rx_dv_d1 <= 1'b0;
gmii_rx_dv_d2 <= 1'b0;
gmii_rx_dv_d3 <= 1'b0;
gmii_rx_dv_d4 <= 1'b0;
end else begin
state_reg <= state_next;
m_axis_tvalid_reg <= m_axis_tvalid_next;
start_packet_reg <= start_packet_next;
error_bad_frame_reg <= error_bad_frame_next;
error_bad_fcs_reg <= error_bad_fcs_next;
// datapath
if (reset_crc) begin
crc_state <= 32'hFFFFFFFF;
end else if (update_crc) begin
crc_state <= crc_next;
end
if (clk_enable) begin
if (mii_select) begin
mii_odd <= !mii_odd;
if (mii_locked) begin
mii_locked <= gmii_rx_dv;
end else if (gmii_rx_dv && {gmii_rxd[3:0], gmii_rxd_d0[7:4]} == ETH_SFD) begin
mii_locked <= 1'b1;
mii_odd <= 1'b1;
end
if (mii_odd) begin
gmii_rx_dv_d0 <= gmii_rx_dv & gmii_rx_dv_d0;
gmii_rx_dv_d1 <= gmii_rx_dv_d0 & gmii_rx_dv;
gmii_rx_dv_d2 <= gmii_rx_dv_d1 & gmii_rx_dv;
gmii_rx_dv_d3 <= gmii_rx_dv_d2 & gmii_rx_dv;
gmii_rx_dv_d4 <= gmii_rx_dv_d3 & gmii_rx_dv;
end else begin
gmii_rx_dv_d0 <= gmii_rx_dv;
end
end else begin
gmii_rx_dv_d0 <= gmii_rx_dv;
gmii_rx_dv_d1 <= gmii_rx_dv_d0 & gmii_rx_dv;
gmii_rx_dv_d2 <= gmii_rx_dv_d1 & gmii_rx_dv;
gmii_rx_dv_d3 <= gmii_rx_dv_d2 & gmii_rx_dv;
gmii_rx_dv_d4 <= gmii_rx_dv_d3 & gmii_rx_dv;
end
end
end
ptp_ts_reg <= ptp_ts_next;
m_axis_tdata_reg <= m_axis_tdata_next;
m_axis_tlast_reg <= m_axis_tlast_next;
m_axis_tuser_reg <= m_axis_tuser_next;
// delay input
if (clk_enable) begin
if (mii_select) begin
gmii_rxd_d0 <= {gmii_rxd[3:0], gmii_rxd_d0[7:4]};
if (mii_odd) begin
gmii_rxd_d1 <= gmii_rxd_d0;
gmii_rxd_d2 <= gmii_rxd_d1;
gmii_rxd_d3 <= gmii_rxd_d2;
gmii_rxd_d4 <= gmii_rxd_d3;
gmii_rx_er_d0 <= gmii_rx_er | gmii_rx_er_d0;
gmii_rx_er_d1 <= gmii_rx_er_d0;
gmii_rx_er_d2 <= gmii_rx_er_d1;
gmii_rx_er_d3 <= gmii_rx_er_d2;
gmii_rx_er_d4 <= gmii_rx_er_d3;
end else begin
gmii_rx_er_d0 <= gmii_rx_er;
end
end else begin
gmii_rxd_d0 <= gmii_rxd;
gmii_rxd_d1 <= gmii_rxd_d0;
gmii_rxd_d2 <= gmii_rxd_d1;
gmii_rxd_d3 <= gmii_rxd_d2;
gmii_rxd_d4 <= gmii_rxd_d3;
gmii_rx_er_d0 <= gmii_rx_er;
gmii_rx_er_d1 <= gmii_rx_er_d0;
gmii_rx_er_d2 <= gmii_rx_er_d1;
gmii_rx_er_d3 <= gmii_rx_er_d2;
gmii_rx_er_d4 <= gmii_rx_er_d3;
end
end
end
endmodule
|
// system_acl_iface_acl_kernel_clk_mm_interconnect_0.v
// This file was auto-generated from altera_mm_interconnect_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 14.0 200 at 2015.05.04.18:11:55
`timescale 1 ps / 1 ps
module system_acl_iface_acl_kernel_clk_mm_interconnect_0 (
input wire clk_clk_clk, // clk_clk.clk
input wire global_routing_kernel_clk_global_clk_clk, // global_routing_kernel_clk_global_clk.clk
input wire counter_clk_reset_reset_bridge_in_reset_reset, // counter_clk_reset_reset_bridge_in_reset.reset
input wire ctrl_reset_reset_bridge_in_reset_reset, // ctrl_reset_reset_bridge_in_reset.reset
input wire [10:0] ctrl_m0_address, // ctrl_m0.address
output wire ctrl_m0_waitrequest, // .waitrequest
input wire [0:0] ctrl_m0_burstcount, // .burstcount
input wire [3:0] ctrl_m0_byteenable, // .byteenable
input wire ctrl_m0_read, // .read
output wire [31:0] ctrl_m0_readdata, // .readdata
output wire ctrl_m0_readdatavalid, // .readdatavalid
input wire ctrl_m0_write, // .write
input wire [31:0] ctrl_m0_writedata, // .writedata
input wire ctrl_m0_debugaccess, // .debugaccess
output wire [1:0] counter_s_address, // counter_s.address
output wire counter_s_write, // .write
output wire counter_s_read, // .read
input wire [31:0] counter_s_readdata, // .readdata
output wire [31:0] counter_s_writedata, // .writedata
output wire [3:0] counter_s_byteenable, // .byteenable
input wire counter_s_readdatavalid, // .readdatavalid
input wire counter_s_waitrequest, // .waitrequest
output wire pll_lock_avs_0_s_read, // pll_lock_avs_0_s.read
input wire [31:0] pll_lock_avs_0_s_readdata, // .readdata
output wire [5:0] pll_reconfig_0_mgmt_avalon_slave_address, // pll_reconfig_0_mgmt_avalon_slave.address
output wire pll_reconfig_0_mgmt_avalon_slave_write, // .write
output wire pll_reconfig_0_mgmt_avalon_slave_read, // .read
input wire [31:0] pll_reconfig_0_mgmt_avalon_slave_readdata, // .readdata
output wire [31:0] pll_reconfig_0_mgmt_avalon_slave_writedata, // .writedata
input wire pll_reconfig_0_mgmt_avalon_slave_waitrequest, // .waitrequest
output wire [7:0] pll_rom_s1_address, // pll_rom_s1.address
output wire pll_rom_s1_write, // .write
input wire [31:0] pll_rom_s1_readdata, // .readdata
output wire [31:0] pll_rom_s1_writedata, // .writedata
output wire [3:0] pll_rom_s1_byteenable, // .byteenable
output wire pll_rom_s1_chipselect, // .chipselect
output wire pll_rom_s1_clken, // .clken
output wire pll_rom_s1_debugaccess, // .debugaccess
output wire pll_sw_reset_s_write, // pll_sw_reset_s.write
output wire pll_sw_reset_s_read, // .read
input wire [31:0] pll_sw_reset_s_readdata, // .readdata
output wire [31:0] pll_sw_reset_s_writedata, // .writedata
output wire [3:0] pll_sw_reset_s_byteenable, // .byteenable
input wire pll_sw_reset_s_waitrequest, // .waitrequest
output wire version_id_0_s_read, // version_id_0_s.read
input wire [31:0] version_id_0_s_readdata // .readdata
);
wire ctrl_m0_translator_avalon_universal_master_0_waitrequest; // ctrl_m0_agent:av_waitrequest -> ctrl_m0_translator:uav_waitrequest
wire [2:0] ctrl_m0_translator_avalon_universal_master_0_burstcount; // ctrl_m0_translator:uav_burstcount -> ctrl_m0_agent:av_burstcount
wire [31:0] ctrl_m0_translator_avalon_universal_master_0_writedata; // ctrl_m0_translator:uav_writedata -> ctrl_m0_agent:av_writedata
wire [10:0] ctrl_m0_translator_avalon_universal_master_0_address; // ctrl_m0_translator:uav_address -> ctrl_m0_agent:av_address
wire ctrl_m0_translator_avalon_universal_master_0_lock; // ctrl_m0_translator:uav_lock -> ctrl_m0_agent:av_lock
wire ctrl_m0_translator_avalon_universal_master_0_write; // ctrl_m0_translator:uav_write -> ctrl_m0_agent:av_write
wire ctrl_m0_translator_avalon_universal_master_0_read; // ctrl_m0_translator:uav_read -> ctrl_m0_agent:av_read
wire [31:0] ctrl_m0_translator_avalon_universal_master_0_readdata; // ctrl_m0_agent:av_readdata -> ctrl_m0_translator:uav_readdata
wire ctrl_m0_translator_avalon_universal_master_0_debugaccess; // ctrl_m0_translator:uav_debugaccess -> ctrl_m0_agent:av_debugaccess
wire [3:0] ctrl_m0_translator_avalon_universal_master_0_byteenable; // ctrl_m0_translator:uav_byteenable -> ctrl_m0_agent:av_byteenable
wire ctrl_m0_translator_avalon_universal_master_0_readdatavalid; // ctrl_m0_agent:av_readdatavalid -> ctrl_m0_translator:uav_readdatavalid
wire pll_reconfig_0_mgmt_avalon_slave_agent_m0_waitrequest; // pll_reconfig_0_mgmt_avalon_slave_translator:uav_waitrequest -> pll_reconfig_0_mgmt_avalon_slave_agent:m0_waitrequest
wire [2:0] pll_reconfig_0_mgmt_avalon_slave_agent_m0_burstcount; // pll_reconfig_0_mgmt_avalon_slave_agent:m0_burstcount -> pll_reconfig_0_mgmt_avalon_slave_translator:uav_burstcount
wire [31:0] pll_reconfig_0_mgmt_avalon_slave_agent_m0_writedata; // pll_reconfig_0_mgmt_avalon_slave_agent:m0_writedata -> pll_reconfig_0_mgmt_avalon_slave_translator:uav_writedata
wire [10:0] pll_reconfig_0_mgmt_avalon_slave_agent_m0_address; // pll_reconfig_0_mgmt_avalon_slave_agent:m0_address -> pll_reconfig_0_mgmt_avalon_slave_translator:uav_address
wire pll_reconfig_0_mgmt_avalon_slave_agent_m0_write; // pll_reconfig_0_mgmt_avalon_slave_agent:m0_write -> pll_reconfig_0_mgmt_avalon_slave_translator:uav_write
wire pll_reconfig_0_mgmt_avalon_slave_agent_m0_lock; // pll_reconfig_0_mgmt_avalon_slave_agent:m0_lock -> pll_reconfig_0_mgmt_avalon_slave_translator:uav_lock
wire pll_reconfig_0_mgmt_avalon_slave_agent_m0_read; // pll_reconfig_0_mgmt_avalon_slave_agent:m0_read -> pll_reconfig_0_mgmt_avalon_slave_translator:uav_read
wire [31:0] pll_reconfig_0_mgmt_avalon_slave_agent_m0_readdata; // pll_reconfig_0_mgmt_avalon_slave_translator:uav_readdata -> pll_reconfig_0_mgmt_avalon_slave_agent:m0_readdata
wire pll_reconfig_0_mgmt_avalon_slave_agent_m0_readdatavalid; // pll_reconfig_0_mgmt_avalon_slave_translator:uav_readdatavalid -> pll_reconfig_0_mgmt_avalon_slave_agent:m0_readdatavalid
wire pll_reconfig_0_mgmt_avalon_slave_agent_m0_debugaccess; // pll_reconfig_0_mgmt_avalon_slave_agent:m0_debugaccess -> pll_reconfig_0_mgmt_avalon_slave_translator:uav_debugaccess
wire [3:0] pll_reconfig_0_mgmt_avalon_slave_agent_m0_byteenable; // pll_reconfig_0_mgmt_avalon_slave_agent:m0_byteenable -> pll_reconfig_0_mgmt_avalon_slave_translator:uav_byteenable
wire pll_reconfig_0_mgmt_avalon_slave_agent_rf_source_endofpacket; // pll_reconfig_0_mgmt_avalon_slave_agent:rf_source_endofpacket -> pll_reconfig_0_mgmt_avalon_slave_agent_rsp_fifo:in_endofpacket
wire pll_reconfig_0_mgmt_avalon_slave_agent_rf_source_valid; // pll_reconfig_0_mgmt_avalon_slave_agent:rf_source_valid -> pll_reconfig_0_mgmt_avalon_slave_agent_rsp_fifo:in_valid
wire pll_reconfig_0_mgmt_avalon_slave_agent_rf_source_startofpacket; // pll_reconfig_0_mgmt_avalon_slave_agent:rf_source_startofpacket -> pll_reconfig_0_mgmt_avalon_slave_agent_rsp_fifo:in_startofpacket
wire [85:0] pll_reconfig_0_mgmt_avalon_slave_agent_rf_source_data; // pll_reconfig_0_mgmt_avalon_slave_agent:rf_source_data -> pll_reconfig_0_mgmt_avalon_slave_agent_rsp_fifo:in_data
wire pll_reconfig_0_mgmt_avalon_slave_agent_rf_source_ready; // pll_reconfig_0_mgmt_avalon_slave_agent_rsp_fifo:in_ready -> pll_reconfig_0_mgmt_avalon_slave_agent:rf_source_ready
wire pll_reconfig_0_mgmt_avalon_slave_agent_rsp_fifo_out_endofpacket; // pll_reconfig_0_mgmt_avalon_slave_agent_rsp_fifo:out_endofpacket -> pll_reconfig_0_mgmt_avalon_slave_agent:rf_sink_endofpacket
wire pll_reconfig_0_mgmt_avalon_slave_agent_rsp_fifo_out_valid; // pll_reconfig_0_mgmt_avalon_slave_agent_rsp_fifo:out_valid -> pll_reconfig_0_mgmt_avalon_slave_agent:rf_sink_valid
wire pll_reconfig_0_mgmt_avalon_slave_agent_rsp_fifo_out_startofpacket; // pll_reconfig_0_mgmt_avalon_slave_agent_rsp_fifo:out_startofpacket -> pll_reconfig_0_mgmt_avalon_slave_agent:rf_sink_startofpacket
wire [85:0] pll_reconfig_0_mgmt_avalon_slave_agent_rsp_fifo_out_data; // pll_reconfig_0_mgmt_avalon_slave_agent_rsp_fifo:out_data -> pll_reconfig_0_mgmt_avalon_slave_agent:rf_sink_data
wire pll_reconfig_0_mgmt_avalon_slave_agent_rsp_fifo_out_ready; // pll_reconfig_0_mgmt_avalon_slave_agent:rf_sink_ready -> pll_reconfig_0_mgmt_avalon_slave_agent_rsp_fifo:out_ready
wire pll_reconfig_0_mgmt_avalon_slave_agent_rdata_fifo_src_valid; // pll_reconfig_0_mgmt_avalon_slave_agent:rdata_fifo_src_valid -> pll_reconfig_0_mgmt_avalon_slave_agent:rdata_fifo_sink_valid
wire [33:0] pll_reconfig_0_mgmt_avalon_slave_agent_rdata_fifo_src_data; // pll_reconfig_0_mgmt_avalon_slave_agent:rdata_fifo_src_data -> pll_reconfig_0_mgmt_avalon_slave_agent:rdata_fifo_sink_data
wire pll_reconfig_0_mgmt_avalon_slave_agent_rdata_fifo_src_ready; // pll_reconfig_0_mgmt_avalon_slave_agent:rdata_fifo_sink_ready -> pll_reconfig_0_mgmt_avalon_slave_agent:rdata_fifo_src_ready
wire cmd_mux_src_endofpacket; // cmd_mux:src_endofpacket -> pll_reconfig_0_mgmt_avalon_slave_agent:cp_endofpacket
wire cmd_mux_src_valid; // cmd_mux:src_valid -> pll_reconfig_0_mgmt_avalon_slave_agent:cp_valid
wire cmd_mux_src_startofpacket; // cmd_mux:src_startofpacket -> pll_reconfig_0_mgmt_avalon_slave_agent:cp_startofpacket
wire [84:0] cmd_mux_src_data; // cmd_mux:src_data -> pll_reconfig_0_mgmt_avalon_slave_agent:cp_data
wire [5:0] cmd_mux_src_channel; // cmd_mux:src_channel -> pll_reconfig_0_mgmt_avalon_slave_agent:cp_channel
wire cmd_mux_src_ready; // pll_reconfig_0_mgmt_avalon_slave_agent:cp_ready -> cmd_mux:src_ready
wire pll_rom_s1_agent_m0_waitrequest; // pll_rom_s1_translator:uav_waitrequest -> pll_rom_s1_agent:m0_waitrequest
wire [2:0] pll_rom_s1_agent_m0_burstcount; // pll_rom_s1_agent:m0_burstcount -> pll_rom_s1_translator:uav_burstcount
wire [31:0] pll_rom_s1_agent_m0_writedata; // pll_rom_s1_agent:m0_writedata -> pll_rom_s1_translator:uav_writedata
wire [10:0] pll_rom_s1_agent_m0_address; // pll_rom_s1_agent:m0_address -> pll_rom_s1_translator:uav_address
wire pll_rom_s1_agent_m0_write; // pll_rom_s1_agent:m0_write -> pll_rom_s1_translator:uav_write
wire pll_rom_s1_agent_m0_lock; // pll_rom_s1_agent:m0_lock -> pll_rom_s1_translator:uav_lock
wire pll_rom_s1_agent_m0_read; // pll_rom_s1_agent:m0_read -> pll_rom_s1_translator:uav_read
wire [31:0] pll_rom_s1_agent_m0_readdata; // pll_rom_s1_translator:uav_readdata -> pll_rom_s1_agent:m0_readdata
wire pll_rom_s1_agent_m0_readdatavalid; // pll_rom_s1_translator:uav_readdatavalid -> pll_rom_s1_agent:m0_readdatavalid
wire pll_rom_s1_agent_m0_debugaccess; // pll_rom_s1_agent:m0_debugaccess -> pll_rom_s1_translator:uav_debugaccess
wire [3:0] pll_rom_s1_agent_m0_byteenable; // pll_rom_s1_agent:m0_byteenable -> pll_rom_s1_translator:uav_byteenable
wire pll_rom_s1_agent_rf_source_endofpacket; // pll_rom_s1_agent:rf_source_endofpacket -> pll_rom_s1_agent_rsp_fifo:in_endofpacket
wire pll_rom_s1_agent_rf_source_valid; // pll_rom_s1_agent:rf_source_valid -> pll_rom_s1_agent_rsp_fifo:in_valid
wire pll_rom_s1_agent_rf_source_startofpacket; // pll_rom_s1_agent:rf_source_startofpacket -> pll_rom_s1_agent_rsp_fifo:in_startofpacket
wire [85:0] pll_rom_s1_agent_rf_source_data; // pll_rom_s1_agent:rf_source_data -> pll_rom_s1_agent_rsp_fifo:in_data
wire pll_rom_s1_agent_rf_source_ready; // pll_rom_s1_agent_rsp_fifo:in_ready -> pll_rom_s1_agent:rf_source_ready
wire pll_rom_s1_agent_rsp_fifo_out_endofpacket; // pll_rom_s1_agent_rsp_fifo:out_endofpacket -> pll_rom_s1_agent:rf_sink_endofpacket
wire pll_rom_s1_agent_rsp_fifo_out_valid; // pll_rom_s1_agent_rsp_fifo:out_valid -> pll_rom_s1_agent:rf_sink_valid
wire pll_rom_s1_agent_rsp_fifo_out_startofpacket; // pll_rom_s1_agent_rsp_fifo:out_startofpacket -> pll_rom_s1_agent:rf_sink_startofpacket
wire [85:0] pll_rom_s1_agent_rsp_fifo_out_data; // pll_rom_s1_agent_rsp_fifo:out_data -> pll_rom_s1_agent:rf_sink_data
wire pll_rom_s1_agent_rsp_fifo_out_ready; // pll_rom_s1_agent:rf_sink_ready -> pll_rom_s1_agent_rsp_fifo:out_ready
wire pll_rom_s1_agent_rdata_fifo_src_valid; // pll_rom_s1_agent:rdata_fifo_src_valid -> pll_rom_s1_agent:rdata_fifo_sink_valid
wire [33:0] pll_rom_s1_agent_rdata_fifo_src_data; // pll_rom_s1_agent:rdata_fifo_src_data -> pll_rom_s1_agent:rdata_fifo_sink_data
wire pll_rom_s1_agent_rdata_fifo_src_ready; // pll_rom_s1_agent:rdata_fifo_sink_ready -> pll_rom_s1_agent:rdata_fifo_src_ready
wire cmd_mux_001_src_endofpacket; // cmd_mux_001:src_endofpacket -> pll_rom_s1_agent:cp_endofpacket
wire cmd_mux_001_src_valid; // cmd_mux_001:src_valid -> pll_rom_s1_agent:cp_valid
wire cmd_mux_001_src_startofpacket; // cmd_mux_001:src_startofpacket -> pll_rom_s1_agent:cp_startofpacket
wire [84:0] cmd_mux_001_src_data; // cmd_mux_001:src_data -> pll_rom_s1_agent:cp_data
wire [5:0] cmd_mux_001_src_channel; // cmd_mux_001:src_channel -> pll_rom_s1_agent:cp_channel
wire cmd_mux_001_src_ready; // pll_rom_s1_agent:cp_ready -> cmd_mux_001:src_ready
wire counter_s_agent_m0_waitrequest; // counter_s_translator:uav_waitrequest -> counter_s_agent:m0_waitrequest
wire [2:0] counter_s_agent_m0_burstcount; // counter_s_agent:m0_burstcount -> counter_s_translator:uav_burstcount
wire [31:0] counter_s_agent_m0_writedata; // counter_s_agent:m0_writedata -> counter_s_translator:uav_writedata
wire [10:0] counter_s_agent_m0_address; // counter_s_agent:m0_address -> counter_s_translator:uav_address
wire counter_s_agent_m0_write; // counter_s_agent:m0_write -> counter_s_translator:uav_write
wire counter_s_agent_m0_lock; // counter_s_agent:m0_lock -> counter_s_translator:uav_lock
wire counter_s_agent_m0_read; // counter_s_agent:m0_read -> counter_s_translator:uav_read
wire [31:0] counter_s_agent_m0_readdata; // counter_s_translator:uav_readdata -> counter_s_agent:m0_readdata
wire counter_s_agent_m0_readdatavalid; // counter_s_translator:uav_readdatavalid -> counter_s_agent:m0_readdatavalid
wire counter_s_agent_m0_debugaccess; // counter_s_agent:m0_debugaccess -> counter_s_translator:uav_debugaccess
wire [3:0] counter_s_agent_m0_byteenable; // counter_s_agent:m0_byteenable -> counter_s_translator:uav_byteenable
wire counter_s_agent_rf_source_endofpacket; // counter_s_agent:rf_source_endofpacket -> counter_s_agent_rsp_fifo:in_endofpacket
wire counter_s_agent_rf_source_valid; // counter_s_agent:rf_source_valid -> counter_s_agent_rsp_fifo:in_valid
wire counter_s_agent_rf_source_startofpacket; // counter_s_agent:rf_source_startofpacket -> counter_s_agent_rsp_fifo:in_startofpacket
wire [85:0] counter_s_agent_rf_source_data; // counter_s_agent:rf_source_data -> counter_s_agent_rsp_fifo:in_data
wire counter_s_agent_rf_source_ready; // counter_s_agent_rsp_fifo:in_ready -> counter_s_agent:rf_source_ready
wire counter_s_agent_rsp_fifo_out_endofpacket; // counter_s_agent_rsp_fifo:out_endofpacket -> counter_s_agent:rf_sink_endofpacket
wire counter_s_agent_rsp_fifo_out_valid; // counter_s_agent_rsp_fifo:out_valid -> counter_s_agent:rf_sink_valid
wire counter_s_agent_rsp_fifo_out_startofpacket; // counter_s_agent_rsp_fifo:out_startofpacket -> counter_s_agent:rf_sink_startofpacket
wire [85:0] counter_s_agent_rsp_fifo_out_data; // counter_s_agent_rsp_fifo:out_data -> counter_s_agent:rf_sink_data
wire counter_s_agent_rsp_fifo_out_ready; // counter_s_agent:rf_sink_ready -> counter_s_agent_rsp_fifo:out_ready
wire counter_s_agent_rdata_fifo_src_valid; // counter_s_agent:rdata_fifo_src_valid -> counter_s_agent_rdata_fifo:in_valid
wire [33:0] counter_s_agent_rdata_fifo_src_data; // counter_s_agent:rdata_fifo_src_data -> counter_s_agent_rdata_fifo:in_data
wire counter_s_agent_rdata_fifo_src_ready; // counter_s_agent_rdata_fifo:in_ready -> counter_s_agent:rdata_fifo_src_ready
wire counter_s_agent_rdata_fifo_out_valid; // counter_s_agent_rdata_fifo:out_valid -> counter_s_agent:rdata_fifo_sink_valid
wire [33:0] counter_s_agent_rdata_fifo_out_data; // counter_s_agent_rdata_fifo:out_data -> counter_s_agent:rdata_fifo_sink_data
wire counter_s_agent_rdata_fifo_out_ready; // counter_s_agent:rdata_fifo_sink_ready -> counter_s_agent_rdata_fifo:out_ready
wire cmd_mux_002_src_endofpacket; // cmd_mux_002:src_endofpacket -> counter_s_agent:cp_endofpacket
wire cmd_mux_002_src_valid; // cmd_mux_002:src_valid -> counter_s_agent:cp_valid
wire cmd_mux_002_src_startofpacket; // cmd_mux_002:src_startofpacket -> counter_s_agent:cp_startofpacket
wire [84:0] cmd_mux_002_src_data; // cmd_mux_002:src_data -> counter_s_agent:cp_data
wire [5:0] cmd_mux_002_src_channel; // cmd_mux_002:src_channel -> counter_s_agent:cp_channel
wire cmd_mux_002_src_ready; // counter_s_agent:cp_ready -> cmd_mux_002:src_ready
wire pll_sw_reset_s_agent_m0_waitrequest; // pll_sw_reset_s_translator:uav_waitrequest -> pll_sw_reset_s_agent:m0_waitrequest
wire [2:0] pll_sw_reset_s_agent_m0_burstcount; // pll_sw_reset_s_agent:m0_burstcount -> pll_sw_reset_s_translator:uav_burstcount
wire [31:0] pll_sw_reset_s_agent_m0_writedata; // pll_sw_reset_s_agent:m0_writedata -> pll_sw_reset_s_translator:uav_writedata
wire [10:0] pll_sw_reset_s_agent_m0_address; // pll_sw_reset_s_agent:m0_address -> pll_sw_reset_s_translator:uav_address
wire pll_sw_reset_s_agent_m0_write; // pll_sw_reset_s_agent:m0_write -> pll_sw_reset_s_translator:uav_write
wire pll_sw_reset_s_agent_m0_lock; // pll_sw_reset_s_agent:m0_lock -> pll_sw_reset_s_translator:uav_lock
wire pll_sw_reset_s_agent_m0_read; // pll_sw_reset_s_agent:m0_read -> pll_sw_reset_s_translator:uav_read
wire [31:0] pll_sw_reset_s_agent_m0_readdata; // pll_sw_reset_s_translator:uav_readdata -> pll_sw_reset_s_agent:m0_readdata
wire pll_sw_reset_s_agent_m0_readdatavalid; // pll_sw_reset_s_translator:uav_readdatavalid -> pll_sw_reset_s_agent:m0_readdatavalid
wire pll_sw_reset_s_agent_m0_debugaccess; // pll_sw_reset_s_agent:m0_debugaccess -> pll_sw_reset_s_translator:uav_debugaccess
wire [3:0] pll_sw_reset_s_agent_m0_byteenable; // pll_sw_reset_s_agent:m0_byteenable -> pll_sw_reset_s_translator:uav_byteenable
wire pll_sw_reset_s_agent_rf_source_endofpacket; // pll_sw_reset_s_agent:rf_source_endofpacket -> pll_sw_reset_s_agent_rsp_fifo:in_endofpacket
wire pll_sw_reset_s_agent_rf_source_valid; // pll_sw_reset_s_agent:rf_source_valid -> pll_sw_reset_s_agent_rsp_fifo:in_valid
wire pll_sw_reset_s_agent_rf_source_startofpacket; // pll_sw_reset_s_agent:rf_source_startofpacket -> pll_sw_reset_s_agent_rsp_fifo:in_startofpacket
wire [85:0] pll_sw_reset_s_agent_rf_source_data; // pll_sw_reset_s_agent:rf_source_data -> pll_sw_reset_s_agent_rsp_fifo:in_data
wire pll_sw_reset_s_agent_rf_source_ready; // pll_sw_reset_s_agent_rsp_fifo:in_ready -> pll_sw_reset_s_agent:rf_source_ready
wire pll_sw_reset_s_agent_rsp_fifo_out_endofpacket; // pll_sw_reset_s_agent_rsp_fifo:out_endofpacket -> pll_sw_reset_s_agent:rf_sink_endofpacket
wire pll_sw_reset_s_agent_rsp_fifo_out_valid; // pll_sw_reset_s_agent_rsp_fifo:out_valid -> pll_sw_reset_s_agent:rf_sink_valid
wire pll_sw_reset_s_agent_rsp_fifo_out_startofpacket; // pll_sw_reset_s_agent_rsp_fifo:out_startofpacket -> pll_sw_reset_s_agent:rf_sink_startofpacket
wire [85:0] pll_sw_reset_s_agent_rsp_fifo_out_data; // pll_sw_reset_s_agent_rsp_fifo:out_data -> pll_sw_reset_s_agent:rf_sink_data
wire pll_sw_reset_s_agent_rsp_fifo_out_ready; // pll_sw_reset_s_agent:rf_sink_ready -> pll_sw_reset_s_agent_rsp_fifo:out_ready
wire pll_sw_reset_s_agent_rdata_fifo_src_valid; // pll_sw_reset_s_agent:rdata_fifo_src_valid -> pll_sw_reset_s_agent:rdata_fifo_sink_valid
wire [33:0] pll_sw_reset_s_agent_rdata_fifo_src_data; // pll_sw_reset_s_agent:rdata_fifo_src_data -> pll_sw_reset_s_agent:rdata_fifo_sink_data
wire pll_sw_reset_s_agent_rdata_fifo_src_ready; // pll_sw_reset_s_agent:rdata_fifo_sink_ready -> pll_sw_reset_s_agent:rdata_fifo_src_ready
wire cmd_mux_003_src_endofpacket; // cmd_mux_003:src_endofpacket -> pll_sw_reset_s_agent:cp_endofpacket
wire cmd_mux_003_src_valid; // cmd_mux_003:src_valid -> pll_sw_reset_s_agent:cp_valid
wire cmd_mux_003_src_startofpacket; // cmd_mux_003:src_startofpacket -> pll_sw_reset_s_agent:cp_startofpacket
wire [84:0] cmd_mux_003_src_data; // cmd_mux_003:src_data -> pll_sw_reset_s_agent:cp_data
wire [5:0] cmd_mux_003_src_channel; // cmd_mux_003:src_channel -> pll_sw_reset_s_agent:cp_channel
wire cmd_mux_003_src_ready; // pll_sw_reset_s_agent:cp_ready -> cmd_mux_003:src_ready
wire pll_lock_avs_0_s_agent_m0_waitrequest; // pll_lock_avs_0_s_translator:uav_waitrequest -> pll_lock_avs_0_s_agent:m0_waitrequest
wire [2:0] pll_lock_avs_0_s_agent_m0_burstcount; // pll_lock_avs_0_s_agent:m0_burstcount -> pll_lock_avs_0_s_translator:uav_burstcount
wire [31:0] pll_lock_avs_0_s_agent_m0_writedata; // pll_lock_avs_0_s_agent:m0_writedata -> pll_lock_avs_0_s_translator:uav_writedata
wire [10:0] pll_lock_avs_0_s_agent_m0_address; // pll_lock_avs_0_s_agent:m0_address -> pll_lock_avs_0_s_translator:uav_address
wire pll_lock_avs_0_s_agent_m0_write; // pll_lock_avs_0_s_agent:m0_write -> pll_lock_avs_0_s_translator:uav_write
wire pll_lock_avs_0_s_agent_m0_lock; // pll_lock_avs_0_s_agent:m0_lock -> pll_lock_avs_0_s_translator:uav_lock
wire pll_lock_avs_0_s_agent_m0_read; // pll_lock_avs_0_s_agent:m0_read -> pll_lock_avs_0_s_translator:uav_read
wire [31:0] pll_lock_avs_0_s_agent_m0_readdata; // pll_lock_avs_0_s_translator:uav_readdata -> pll_lock_avs_0_s_agent:m0_readdata
wire pll_lock_avs_0_s_agent_m0_readdatavalid; // pll_lock_avs_0_s_translator:uav_readdatavalid -> pll_lock_avs_0_s_agent:m0_readdatavalid
wire pll_lock_avs_0_s_agent_m0_debugaccess; // pll_lock_avs_0_s_agent:m0_debugaccess -> pll_lock_avs_0_s_translator:uav_debugaccess
wire [3:0] pll_lock_avs_0_s_agent_m0_byteenable; // pll_lock_avs_0_s_agent:m0_byteenable -> pll_lock_avs_0_s_translator:uav_byteenable
wire pll_lock_avs_0_s_agent_rf_source_endofpacket; // pll_lock_avs_0_s_agent:rf_source_endofpacket -> pll_lock_avs_0_s_agent_rsp_fifo:in_endofpacket
wire pll_lock_avs_0_s_agent_rf_source_valid; // pll_lock_avs_0_s_agent:rf_source_valid -> pll_lock_avs_0_s_agent_rsp_fifo:in_valid
wire pll_lock_avs_0_s_agent_rf_source_startofpacket; // pll_lock_avs_0_s_agent:rf_source_startofpacket -> pll_lock_avs_0_s_agent_rsp_fifo:in_startofpacket
wire [85:0] pll_lock_avs_0_s_agent_rf_source_data; // pll_lock_avs_0_s_agent:rf_source_data -> pll_lock_avs_0_s_agent_rsp_fifo:in_data
wire pll_lock_avs_0_s_agent_rf_source_ready; // pll_lock_avs_0_s_agent_rsp_fifo:in_ready -> pll_lock_avs_0_s_agent:rf_source_ready
wire pll_lock_avs_0_s_agent_rsp_fifo_out_endofpacket; // pll_lock_avs_0_s_agent_rsp_fifo:out_endofpacket -> pll_lock_avs_0_s_agent:rf_sink_endofpacket
wire pll_lock_avs_0_s_agent_rsp_fifo_out_valid; // pll_lock_avs_0_s_agent_rsp_fifo:out_valid -> pll_lock_avs_0_s_agent:rf_sink_valid
wire pll_lock_avs_0_s_agent_rsp_fifo_out_startofpacket; // pll_lock_avs_0_s_agent_rsp_fifo:out_startofpacket -> pll_lock_avs_0_s_agent:rf_sink_startofpacket
wire [85:0] pll_lock_avs_0_s_agent_rsp_fifo_out_data; // pll_lock_avs_0_s_agent_rsp_fifo:out_data -> pll_lock_avs_0_s_agent:rf_sink_data
wire pll_lock_avs_0_s_agent_rsp_fifo_out_ready; // pll_lock_avs_0_s_agent:rf_sink_ready -> pll_lock_avs_0_s_agent_rsp_fifo:out_ready
wire pll_lock_avs_0_s_agent_rdata_fifo_src_valid; // pll_lock_avs_0_s_agent:rdata_fifo_src_valid -> pll_lock_avs_0_s_agent:rdata_fifo_sink_valid
wire [33:0] pll_lock_avs_0_s_agent_rdata_fifo_src_data; // pll_lock_avs_0_s_agent:rdata_fifo_src_data -> pll_lock_avs_0_s_agent:rdata_fifo_sink_data
wire pll_lock_avs_0_s_agent_rdata_fifo_src_ready; // pll_lock_avs_0_s_agent:rdata_fifo_sink_ready -> pll_lock_avs_0_s_agent:rdata_fifo_src_ready
wire cmd_mux_004_src_endofpacket; // cmd_mux_004:src_endofpacket -> pll_lock_avs_0_s_agent:cp_endofpacket
wire cmd_mux_004_src_valid; // cmd_mux_004:src_valid -> pll_lock_avs_0_s_agent:cp_valid
wire cmd_mux_004_src_startofpacket; // cmd_mux_004:src_startofpacket -> pll_lock_avs_0_s_agent:cp_startofpacket
wire [84:0] cmd_mux_004_src_data; // cmd_mux_004:src_data -> pll_lock_avs_0_s_agent:cp_data
wire [5:0] cmd_mux_004_src_channel; // cmd_mux_004:src_channel -> pll_lock_avs_0_s_agent:cp_channel
wire cmd_mux_004_src_ready; // pll_lock_avs_0_s_agent:cp_ready -> cmd_mux_004:src_ready
wire version_id_0_s_agent_m0_waitrequest; // version_id_0_s_translator:uav_waitrequest -> version_id_0_s_agent:m0_waitrequest
wire [2:0] version_id_0_s_agent_m0_burstcount; // version_id_0_s_agent:m0_burstcount -> version_id_0_s_translator:uav_burstcount
wire [31:0] version_id_0_s_agent_m0_writedata; // version_id_0_s_agent:m0_writedata -> version_id_0_s_translator:uav_writedata
wire [10:0] version_id_0_s_agent_m0_address; // version_id_0_s_agent:m0_address -> version_id_0_s_translator:uav_address
wire version_id_0_s_agent_m0_write; // version_id_0_s_agent:m0_write -> version_id_0_s_translator:uav_write
wire version_id_0_s_agent_m0_lock; // version_id_0_s_agent:m0_lock -> version_id_0_s_translator:uav_lock
wire version_id_0_s_agent_m0_read; // version_id_0_s_agent:m0_read -> version_id_0_s_translator:uav_read
wire [31:0] version_id_0_s_agent_m0_readdata; // version_id_0_s_translator:uav_readdata -> version_id_0_s_agent:m0_readdata
wire version_id_0_s_agent_m0_readdatavalid; // version_id_0_s_translator:uav_readdatavalid -> version_id_0_s_agent:m0_readdatavalid
wire version_id_0_s_agent_m0_debugaccess; // version_id_0_s_agent:m0_debugaccess -> version_id_0_s_translator:uav_debugaccess
wire [3:0] version_id_0_s_agent_m0_byteenable; // version_id_0_s_agent:m0_byteenable -> version_id_0_s_translator:uav_byteenable
wire version_id_0_s_agent_rf_source_endofpacket; // version_id_0_s_agent:rf_source_endofpacket -> version_id_0_s_agent_rsp_fifo:in_endofpacket
wire version_id_0_s_agent_rf_source_valid; // version_id_0_s_agent:rf_source_valid -> version_id_0_s_agent_rsp_fifo:in_valid
wire version_id_0_s_agent_rf_source_startofpacket; // version_id_0_s_agent:rf_source_startofpacket -> version_id_0_s_agent_rsp_fifo:in_startofpacket
wire [85:0] version_id_0_s_agent_rf_source_data; // version_id_0_s_agent:rf_source_data -> version_id_0_s_agent_rsp_fifo:in_data
wire version_id_0_s_agent_rf_source_ready; // version_id_0_s_agent_rsp_fifo:in_ready -> version_id_0_s_agent:rf_source_ready
wire version_id_0_s_agent_rsp_fifo_out_endofpacket; // version_id_0_s_agent_rsp_fifo:out_endofpacket -> version_id_0_s_agent:rf_sink_endofpacket
wire version_id_0_s_agent_rsp_fifo_out_valid; // version_id_0_s_agent_rsp_fifo:out_valid -> version_id_0_s_agent:rf_sink_valid
wire version_id_0_s_agent_rsp_fifo_out_startofpacket; // version_id_0_s_agent_rsp_fifo:out_startofpacket -> version_id_0_s_agent:rf_sink_startofpacket
wire [85:0] version_id_0_s_agent_rsp_fifo_out_data; // version_id_0_s_agent_rsp_fifo:out_data -> version_id_0_s_agent:rf_sink_data
wire version_id_0_s_agent_rsp_fifo_out_ready; // version_id_0_s_agent:rf_sink_ready -> version_id_0_s_agent_rsp_fifo:out_ready
wire version_id_0_s_agent_rdata_fifo_src_valid; // version_id_0_s_agent:rdata_fifo_src_valid -> version_id_0_s_agent:rdata_fifo_sink_valid
wire [33:0] version_id_0_s_agent_rdata_fifo_src_data; // version_id_0_s_agent:rdata_fifo_src_data -> version_id_0_s_agent:rdata_fifo_sink_data
wire version_id_0_s_agent_rdata_fifo_src_ready; // version_id_0_s_agent:rdata_fifo_sink_ready -> version_id_0_s_agent:rdata_fifo_src_ready
wire cmd_mux_005_src_endofpacket; // cmd_mux_005:src_endofpacket -> version_id_0_s_agent:cp_endofpacket
wire cmd_mux_005_src_valid; // cmd_mux_005:src_valid -> version_id_0_s_agent:cp_valid
wire cmd_mux_005_src_startofpacket; // cmd_mux_005:src_startofpacket -> version_id_0_s_agent:cp_startofpacket
wire [84:0] cmd_mux_005_src_data; // cmd_mux_005:src_data -> version_id_0_s_agent:cp_data
wire [5:0] cmd_mux_005_src_channel; // cmd_mux_005:src_channel -> version_id_0_s_agent:cp_channel
wire cmd_mux_005_src_ready; // version_id_0_s_agent:cp_ready -> cmd_mux_005:src_ready
wire ctrl_m0_agent_cp_endofpacket; // ctrl_m0_agent:cp_endofpacket -> router:sink_endofpacket
wire ctrl_m0_agent_cp_valid; // ctrl_m0_agent:cp_valid -> router:sink_valid
wire ctrl_m0_agent_cp_startofpacket; // ctrl_m0_agent:cp_startofpacket -> router:sink_startofpacket
wire [84:0] ctrl_m0_agent_cp_data; // ctrl_m0_agent:cp_data -> router:sink_data
wire ctrl_m0_agent_cp_ready; // router:sink_ready -> ctrl_m0_agent:cp_ready
wire pll_reconfig_0_mgmt_avalon_slave_agent_rp_endofpacket; // pll_reconfig_0_mgmt_avalon_slave_agent:rp_endofpacket -> router_001:sink_endofpacket
wire pll_reconfig_0_mgmt_avalon_slave_agent_rp_valid; // pll_reconfig_0_mgmt_avalon_slave_agent:rp_valid -> router_001:sink_valid
wire pll_reconfig_0_mgmt_avalon_slave_agent_rp_startofpacket; // pll_reconfig_0_mgmt_avalon_slave_agent:rp_startofpacket -> router_001:sink_startofpacket
wire [84:0] pll_reconfig_0_mgmt_avalon_slave_agent_rp_data; // pll_reconfig_0_mgmt_avalon_slave_agent:rp_data -> router_001:sink_data
wire pll_reconfig_0_mgmt_avalon_slave_agent_rp_ready; // router_001:sink_ready -> pll_reconfig_0_mgmt_avalon_slave_agent:rp_ready
wire router_001_src_endofpacket; // router_001:src_endofpacket -> rsp_demux:sink_endofpacket
wire router_001_src_valid; // router_001:src_valid -> rsp_demux:sink_valid
wire router_001_src_startofpacket; // router_001:src_startofpacket -> rsp_demux:sink_startofpacket
wire [84:0] router_001_src_data; // router_001:src_data -> rsp_demux:sink_data
wire [5:0] router_001_src_channel; // router_001:src_channel -> rsp_demux:sink_channel
wire router_001_src_ready; // rsp_demux:sink_ready -> router_001:src_ready
wire pll_rom_s1_agent_rp_endofpacket; // pll_rom_s1_agent:rp_endofpacket -> router_002:sink_endofpacket
wire pll_rom_s1_agent_rp_valid; // pll_rom_s1_agent:rp_valid -> router_002:sink_valid
wire pll_rom_s1_agent_rp_startofpacket; // pll_rom_s1_agent:rp_startofpacket -> router_002:sink_startofpacket
wire [84:0] pll_rom_s1_agent_rp_data; // pll_rom_s1_agent:rp_data -> router_002:sink_data
wire pll_rom_s1_agent_rp_ready; // router_002:sink_ready -> pll_rom_s1_agent:rp_ready
wire router_002_src_endofpacket; // router_002:src_endofpacket -> rsp_demux_001:sink_endofpacket
wire router_002_src_valid; // router_002:src_valid -> rsp_demux_001:sink_valid
wire router_002_src_startofpacket; // router_002:src_startofpacket -> rsp_demux_001:sink_startofpacket
wire [84:0] router_002_src_data; // router_002:src_data -> rsp_demux_001:sink_data
wire [5:0] router_002_src_channel; // router_002:src_channel -> rsp_demux_001:sink_channel
wire router_002_src_ready; // rsp_demux_001:sink_ready -> router_002:src_ready
wire counter_s_agent_rp_endofpacket; // counter_s_agent:rp_endofpacket -> router_003:sink_endofpacket
wire counter_s_agent_rp_valid; // counter_s_agent:rp_valid -> router_003:sink_valid
wire counter_s_agent_rp_startofpacket; // counter_s_agent:rp_startofpacket -> router_003:sink_startofpacket
wire [84:0] counter_s_agent_rp_data; // counter_s_agent:rp_data -> router_003:sink_data
wire counter_s_agent_rp_ready; // router_003:sink_ready -> counter_s_agent:rp_ready
wire router_003_src_endofpacket; // router_003:src_endofpacket -> rsp_demux_002:sink_endofpacket
wire router_003_src_valid; // router_003:src_valid -> rsp_demux_002:sink_valid
wire router_003_src_startofpacket; // router_003:src_startofpacket -> rsp_demux_002:sink_startofpacket
wire [84:0] router_003_src_data; // router_003:src_data -> rsp_demux_002:sink_data
wire [5:0] router_003_src_channel; // router_003:src_channel -> rsp_demux_002:sink_channel
wire router_003_src_ready; // rsp_demux_002:sink_ready -> router_003:src_ready
wire pll_sw_reset_s_agent_rp_endofpacket; // pll_sw_reset_s_agent:rp_endofpacket -> router_004:sink_endofpacket
wire pll_sw_reset_s_agent_rp_valid; // pll_sw_reset_s_agent:rp_valid -> router_004:sink_valid
wire pll_sw_reset_s_agent_rp_startofpacket; // pll_sw_reset_s_agent:rp_startofpacket -> router_004:sink_startofpacket
wire [84:0] pll_sw_reset_s_agent_rp_data; // pll_sw_reset_s_agent:rp_data -> router_004:sink_data
wire pll_sw_reset_s_agent_rp_ready; // router_004:sink_ready -> pll_sw_reset_s_agent:rp_ready
wire router_004_src_endofpacket; // router_004:src_endofpacket -> rsp_demux_003:sink_endofpacket
wire router_004_src_valid; // router_004:src_valid -> rsp_demux_003:sink_valid
wire router_004_src_startofpacket; // router_004:src_startofpacket -> rsp_demux_003:sink_startofpacket
wire [84:0] router_004_src_data; // router_004:src_data -> rsp_demux_003:sink_data
wire [5:0] router_004_src_channel; // router_004:src_channel -> rsp_demux_003:sink_channel
wire router_004_src_ready; // rsp_demux_003:sink_ready -> router_004:src_ready
wire pll_lock_avs_0_s_agent_rp_endofpacket; // pll_lock_avs_0_s_agent:rp_endofpacket -> router_005:sink_endofpacket
wire pll_lock_avs_0_s_agent_rp_valid; // pll_lock_avs_0_s_agent:rp_valid -> router_005:sink_valid
wire pll_lock_avs_0_s_agent_rp_startofpacket; // pll_lock_avs_0_s_agent:rp_startofpacket -> router_005:sink_startofpacket
wire [84:0] pll_lock_avs_0_s_agent_rp_data; // pll_lock_avs_0_s_agent:rp_data -> router_005:sink_data
wire pll_lock_avs_0_s_agent_rp_ready; // router_005:sink_ready -> pll_lock_avs_0_s_agent:rp_ready
wire router_005_src_endofpacket; // router_005:src_endofpacket -> rsp_demux_004:sink_endofpacket
wire router_005_src_valid; // router_005:src_valid -> rsp_demux_004:sink_valid
wire router_005_src_startofpacket; // router_005:src_startofpacket -> rsp_demux_004:sink_startofpacket
wire [84:0] router_005_src_data; // router_005:src_data -> rsp_demux_004:sink_data
wire [5:0] router_005_src_channel; // router_005:src_channel -> rsp_demux_004:sink_channel
wire router_005_src_ready; // rsp_demux_004:sink_ready -> router_005:src_ready
wire version_id_0_s_agent_rp_endofpacket; // version_id_0_s_agent:rp_endofpacket -> router_006:sink_endofpacket
wire version_id_0_s_agent_rp_valid; // version_id_0_s_agent:rp_valid -> router_006:sink_valid
wire version_id_0_s_agent_rp_startofpacket; // version_id_0_s_agent:rp_startofpacket -> router_006:sink_startofpacket
wire [84:0] version_id_0_s_agent_rp_data; // version_id_0_s_agent:rp_data -> router_006:sink_data
wire version_id_0_s_agent_rp_ready; // router_006:sink_ready -> version_id_0_s_agent:rp_ready
wire router_006_src_endofpacket; // router_006:src_endofpacket -> rsp_demux_005:sink_endofpacket
wire router_006_src_valid; // router_006:src_valid -> rsp_demux_005:sink_valid
wire router_006_src_startofpacket; // router_006:src_startofpacket -> rsp_demux_005:sink_startofpacket
wire [84:0] router_006_src_data; // router_006:src_data -> rsp_demux_005:sink_data
wire [5:0] router_006_src_channel; // router_006:src_channel -> rsp_demux_005:sink_channel
wire router_006_src_ready; // rsp_demux_005:sink_ready -> router_006:src_ready
wire router_src_endofpacket; // router:src_endofpacket -> ctrl_m0_limiter:cmd_sink_endofpacket
wire router_src_valid; // router:src_valid -> ctrl_m0_limiter:cmd_sink_valid
wire router_src_startofpacket; // router:src_startofpacket -> ctrl_m0_limiter:cmd_sink_startofpacket
wire [84:0] router_src_data; // router:src_data -> ctrl_m0_limiter:cmd_sink_data
wire [5:0] router_src_channel; // router:src_channel -> ctrl_m0_limiter:cmd_sink_channel
wire router_src_ready; // ctrl_m0_limiter:cmd_sink_ready -> router:src_ready
wire ctrl_m0_limiter_cmd_src_endofpacket; // ctrl_m0_limiter:cmd_src_endofpacket -> cmd_demux:sink_endofpacket
wire ctrl_m0_limiter_cmd_src_startofpacket; // ctrl_m0_limiter:cmd_src_startofpacket -> cmd_demux:sink_startofpacket
wire [84:0] ctrl_m0_limiter_cmd_src_data; // ctrl_m0_limiter:cmd_src_data -> cmd_demux:sink_data
wire [5:0] ctrl_m0_limiter_cmd_src_channel; // ctrl_m0_limiter:cmd_src_channel -> cmd_demux:sink_channel
wire ctrl_m0_limiter_cmd_src_ready; // cmd_demux:sink_ready -> ctrl_m0_limiter:cmd_src_ready
wire rsp_mux_src_endofpacket; // rsp_mux:src_endofpacket -> ctrl_m0_limiter:rsp_sink_endofpacket
wire rsp_mux_src_valid; // rsp_mux:src_valid -> ctrl_m0_limiter:rsp_sink_valid
wire rsp_mux_src_startofpacket; // rsp_mux:src_startofpacket -> ctrl_m0_limiter:rsp_sink_startofpacket
wire [84:0] rsp_mux_src_data; // rsp_mux:src_data -> ctrl_m0_limiter:rsp_sink_data
wire [5:0] rsp_mux_src_channel; // rsp_mux:src_channel -> ctrl_m0_limiter:rsp_sink_channel
wire rsp_mux_src_ready; // ctrl_m0_limiter:rsp_sink_ready -> rsp_mux:src_ready
wire ctrl_m0_limiter_rsp_src_endofpacket; // ctrl_m0_limiter:rsp_src_endofpacket -> ctrl_m0_agent:rp_endofpacket
wire ctrl_m0_limiter_rsp_src_valid; // ctrl_m0_limiter:rsp_src_valid -> ctrl_m0_agent:rp_valid
wire ctrl_m0_limiter_rsp_src_startofpacket; // ctrl_m0_limiter:rsp_src_startofpacket -> ctrl_m0_agent:rp_startofpacket
wire [84:0] ctrl_m0_limiter_rsp_src_data; // ctrl_m0_limiter:rsp_src_data -> ctrl_m0_agent:rp_data
wire [5:0] ctrl_m0_limiter_rsp_src_channel; // ctrl_m0_limiter:rsp_src_channel -> ctrl_m0_agent:rp_channel
wire ctrl_m0_limiter_rsp_src_ready; // ctrl_m0_agent:rp_ready -> ctrl_m0_limiter:rsp_src_ready
wire cmd_demux_src0_endofpacket; // cmd_demux:src0_endofpacket -> cmd_mux:sink0_endofpacket
wire cmd_demux_src0_valid; // cmd_demux:src0_valid -> cmd_mux:sink0_valid
wire cmd_demux_src0_startofpacket; // cmd_demux:src0_startofpacket -> cmd_mux:sink0_startofpacket
wire [84:0] cmd_demux_src0_data; // cmd_demux:src0_data -> cmd_mux:sink0_data
wire [5:0] cmd_demux_src0_channel; // cmd_demux:src0_channel -> cmd_mux:sink0_channel
wire cmd_demux_src0_ready; // cmd_mux:sink0_ready -> cmd_demux:src0_ready
wire cmd_demux_src1_endofpacket; // cmd_demux:src1_endofpacket -> cmd_mux_001:sink0_endofpacket
wire cmd_demux_src1_valid; // cmd_demux:src1_valid -> cmd_mux_001:sink0_valid
wire cmd_demux_src1_startofpacket; // cmd_demux:src1_startofpacket -> cmd_mux_001:sink0_startofpacket
wire [84:0] cmd_demux_src1_data; // cmd_demux:src1_data -> cmd_mux_001:sink0_data
wire [5:0] cmd_demux_src1_channel; // cmd_demux:src1_channel -> cmd_mux_001:sink0_channel
wire cmd_demux_src1_ready; // cmd_mux_001:sink0_ready -> cmd_demux:src1_ready
wire cmd_demux_src3_endofpacket; // cmd_demux:src3_endofpacket -> cmd_mux_003:sink0_endofpacket
wire cmd_demux_src3_valid; // cmd_demux:src3_valid -> cmd_mux_003:sink0_valid
wire cmd_demux_src3_startofpacket; // cmd_demux:src3_startofpacket -> cmd_mux_003:sink0_startofpacket
wire [84:0] cmd_demux_src3_data; // cmd_demux:src3_data -> cmd_mux_003:sink0_data
wire [5:0] cmd_demux_src3_channel; // cmd_demux:src3_channel -> cmd_mux_003:sink0_channel
wire cmd_demux_src3_ready; // cmd_mux_003:sink0_ready -> cmd_demux:src3_ready
wire cmd_demux_src4_endofpacket; // cmd_demux:src4_endofpacket -> cmd_mux_004:sink0_endofpacket
wire cmd_demux_src4_valid; // cmd_demux:src4_valid -> cmd_mux_004:sink0_valid
wire cmd_demux_src4_startofpacket; // cmd_demux:src4_startofpacket -> cmd_mux_004:sink0_startofpacket
wire [84:0] cmd_demux_src4_data; // cmd_demux:src4_data -> cmd_mux_004:sink0_data
wire [5:0] cmd_demux_src4_channel; // cmd_demux:src4_channel -> cmd_mux_004:sink0_channel
wire cmd_demux_src4_ready; // cmd_mux_004:sink0_ready -> cmd_demux:src4_ready
wire cmd_demux_src5_endofpacket; // cmd_demux:src5_endofpacket -> cmd_mux_005:sink0_endofpacket
wire cmd_demux_src5_valid; // cmd_demux:src5_valid -> cmd_mux_005:sink0_valid
wire cmd_demux_src5_startofpacket; // cmd_demux:src5_startofpacket -> cmd_mux_005:sink0_startofpacket
wire [84:0] cmd_demux_src5_data; // cmd_demux:src5_data -> cmd_mux_005:sink0_data
wire [5:0] cmd_demux_src5_channel; // cmd_demux:src5_channel -> cmd_mux_005:sink0_channel
wire cmd_demux_src5_ready; // cmd_mux_005:sink0_ready -> cmd_demux:src5_ready
wire rsp_demux_src0_endofpacket; // rsp_demux:src0_endofpacket -> rsp_mux:sink0_endofpacket
wire rsp_demux_src0_valid; // rsp_demux:src0_valid -> rsp_mux:sink0_valid
wire rsp_demux_src0_startofpacket; // rsp_demux:src0_startofpacket -> rsp_mux:sink0_startofpacket
wire [84:0] rsp_demux_src0_data; // rsp_demux:src0_data -> rsp_mux:sink0_data
wire [5:0] rsp_demux_src0_channel; // rsp_demux:src0_channel -> rsp_mux:sink0_channel
wire rsp_demux_src0_ready; // rsp_mux:sink0_ready -> rsp_demux:src0_ready
wire rsp_demux_001_src0_endofpacket; // rsp_demux_001:src0_endofpacket -> rsp_mux:sink1_endofpacket
wire rsp_demux_001_src0_valid; // rsp_demux_001:src0_valid -> rsp_mux:sink1_valid
wire rsp_demux_001_src0_startofpacket; // rsp_demux_001:src0_startofpacket -> rsp_mux:sink1_startofpacket
wire [84:0] rsp_demux_001_src0_data; // rsp_demux_001:src0_data -> rsp_mux:sink1_data
wire [5:0] rsp_demux_001_src0_channel; // rsp_demux_001:src0_channel -> rsp_mux:sink1_channel
wire rsp_demux_001_src0_ready; // rsp_mux:sink1_ready -> rsp_demux_001:src0_ready
wire rsp_demux_003_src0_endofpacket; // rsp_demux_003:src0_endofpacket -> rsp_mux:sink3_endofpacket
wire rsp_demux_003_src0_valid; // rsp_demux_003:src0_valid -> rsp_mux:sink3_valid
wire rsp_demux_003_src0_startofpacket; // rsp_demux_003:src0_startofpacket -> rsp_mux:sink3_startofpacket
wire [84:0] rsp_demux_003_src0_data; // rsp_demux_003:src0_data -> rsp_mux:sink3_data
wire [5:0] rsp_demux_003_src0_channel; // rsp_demux_003:src0_channel -> rsp_mux:sink3_channel
wire rsp_demux_003_src0_ready; // rsp_mux:sink3_ready -> rsp_demux_003:src0_ready
wire rsp_demux_004_src0_endofpacket; // rsp_demux_004:src0_endofpacket -> rsp_mux:sink4_endofpacket
wire rsp_demux_004_src0_valid; // rsp_demux_004:src0_valid -> rsp_mux:sink4_valid
wire rsp_demux_004_src0_startofpacket; // rsp_demux_004:src0_startofpacket -> rsp_mux:sink4_startofpacket
wire [84:0] rsp_demux_004_src0_data; // rsp_demux_004:src0_data -> rsp_mux:sink4_data
wire [5:0] rsp_demux_004_src0_channel; // rsp_demux_004:src0_channel -> rsp_mux:sink4_channel
wire rsp_demux_004_src0_ready; // rsp_mux:sink4_ready -> rsp_demux_004:src0_ready
wire rsp_demux_005_src0_endofpacket; // rsp_demux_005:src0_endofpacket -> rsp_mux:sink5_endofpacket
wire rsp_demux_005_src0_valid; // rsp_demux_005:src0_valid -> rsp_mux:sink5_valid
wire rsp_demux_005_src0_startofpacket; // rsp_demux_005:src0_startofpacket -> rsp_mux:sink5_startofpacket
wire [84:0] rsp_demux_005_src0_data; // rsp_demux_005:src0_data -> rsp_mux:sink5_data
wire [5:0] rsp_demux_005_src0_channel; // rsp_demux_005:src0_channel -> rsp_mux:sink5_channel
wire rsp_demux_005_src0_ready; // rsp_mux:sink5_ready -> rsp_demux_005:src0_ready
wire cmd_demux_src2_endofpacket; // cmd_demux:src2_endofpacket -> crosser:in_endofpacket
wire cmd_demux_src2_valid; // cmd_demux:src2_valid -> crosser:in_valid
wire cmd_demux_src2_startofpacket; // cmd_demux:src2_startofpacket -> crosser:in_startofpacket
wire [84:0] cmd_demux_src2_data; // cmd_demux:src2_data -> crosser:in_data
wire [5:0] cmd_demux_src2_channel; // cmd_demux:src2_channel -> crosser:in_channel
wire cmd_demux_src2_ready; // crosser:in_ready -> cmd_demux:src2_ready
wire crosser_out_endofpacket; // crosser:out_endofpacket -> cmd_mux_002:sink0_endofpacket
wire crosser_out_valid; // crosser:out_valid -> cmd_mux_002:sink0_valid
wire crosser_out_startofpacket; // crosser:out_startofpacket -> cmd_mux_002:sink0_startofpacket
wire [84:0] crosser_out_data; // crosser:out_data -> cmd_mux_002:sink0_data
wire [5:0] crosser_out_channel; // crosser:out_channel -> cmd_mux_002:sink0_channel
wire crosser_out_ready; // cmd_mux_002:sink0_ready -> crosser:out_ready
wire rsp_demux_002_src0_endofpacket; // rsp_demux_002:src0_endofpacket -> crosser_001:in_endofpacket
wire rsp_demux_002_src0_valid; // rsp_demux_002:src0_valid -> crosser_001:in_valid
wire rsp_demux_002_src0_startofpacket; // rsp_demux_002:src0_startofpacket -> crosser_001:in_startofpacket
wire [84:0] rsp_demux_002_src0_data; // rsp_demux_002:src0_data -> crosser_001:in_data
wire [5:0] rsp_demux_002_src0_channel; // rsp_demux_002:src0_channel -> crosser_001:in_channel
wire rsp_demux_002_src0_ready; // crosser_001:in_ready -> rsp_demux_002:src0_ready
wire crosser_001_out_endofpacket; // crosser_001:out_endofpacket -> rsp_mux:sink2_endofpacket
wire crosser_001_out_valid; // crosser_001:out_valid -> rsp_mux:sink2_valid
wire crosser_001_out_startofpacket; // crosser_001:out_startofpacket -> rsp_mux:sink2_startofpacket
wire [84:0] crosser_001_out_data; // crosser_001:out_data -> rsp_mux:sink2_data
wire [5:0] crosser_001_out_channel; // crosser_001:out_channel -> rsp_mux:sink2_channel
wire crosser_001_out_ready; // rsp_mux:sink2_ready -> crosser_001:out_ready
wire [5:0] ctrl_m0_limiter_cmd_valid_data; // ctrl_m0_limiter:cmd_src_valid -> cmd_demux:sink_valid
altera_merlin_master_translator #(
.AV_ADDRESS_W (11),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (11),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (1),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (0)
) ctrl_m0_translator (
.clk (clk_clk_clk), // clk.clk
.reset (ctrl_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (ctrl_m0_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (ctrl_m0_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (ctrl_m0_translator_avalon_universal_master_0_read), // .read
.uav_write (ctrl_m0_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (ctrl_m0_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (ctrl_m0_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (ctrl_m0_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (ctrl_m0_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (ctrl_m0_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (ctrl_m0_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (ctrl_m0_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (ctrl_m0_address), // avalon_anti_master_0.address
.av_waitrequest (ctrl_m0_waitrequest), // .waitrequest
.av_burstcount (ctrl_m0_burstcount), // .burstcount
.av_byteenable (ctrl_m0_byteenable), // .byteenable
.av_read (ctrl_m0_read), // .read
.av_readdata (ctrl_m0_readdata), // .readdata
.av_readdatavalid (ctrl_m0_readdatavalid), // .readdatavalid
.av_write (ctrl_m0_write), // .write
.av_writedata (ctrl_m0_writedata), // .writedata
.av_debugaccess (ctrl_m0_debugaccess), // .debugaccess
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_lock (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponserequest (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponserequest (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (6),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (11),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (3),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) pll_reconfig_0_mgmt_avalon_slave_translator (
.clk (clk_clk_clk), // clk.clk
.reset (ctrl_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (pll_reconfig_0_mgmt_avalon_slave_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (pll_reconfig_0_mgmt_avalon_slave_agent_m0_burstcount), // .burstcount
.uav_read (pll_reconfig_0_mgmt_avalon_slave_agent_m0_read), // .read
.uav_write (pll_reconfig_0_mgmt_avalon_slave_agent_m0_write), // .write
.uav_waitrequest (pll_reconfig_0_mgmt_avalon_slave_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (pll_reconfig_0_mgmt_avalon_slave_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (pll_reconfig_0_mgmt_avalon_slave_agent_m0_byteenable), // .byteenable
.uav_readdata (pll_reconfig_0_mgmt_avalon_slave_agent_m0_readdata), // .readdata
.uav_writedata (pll_reconfig_0_mgmt_avalon_slave_agent_m0_writedata), // .writedata
.uav_lock (pll_reconfig_0_mgmt_avalon_slave_agent_m0_lock), // .lock
.uav_debugaccess (pll_reconfig_0_mgmt_avalon_slave_agent_m0_debugaccess), // .debugaccess
.av_address (pll_reconfig_0_mgmt_avalon_slave_address), // avalon_anti_slave_0.address
.av_write (pll_reconfig_0_mgmt_avalon_slave_write), // .write
.av_read (pll_reconfig_0_mgmt_avalon_slave_read), // .read
.av_readdata (pll_reconfig_0_mgmt_avalon_slave_readdata), // .readdata
.av_writedata (pll_reconfig_0_mgmt_avalon_slave_writedata), // .writedata
.av_waitrequest (pll_reconfig_0_mgmt_avalon_slave_waitrequest), // .waitrequest
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (8),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (11),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (2),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) pll_rom_s1_translator (
.clk (clk_clk_clk), // clk.clk
.reset (ctrl_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (pll_rom_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (pll_rom_s1_agent_m0_burstcount), // .burstcount
.uav_read (pll_rom_s1_agent_m0_read), // .read
.uav_write (pll_rom_s1_agent_m0_write), // .write
.uav_waitrequest (pll_rom_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (pll_rom_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (pll_rom_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (pll_rom_s1_agent_m0_readdata), // .readdata
.uav_writedata (pll_rom_s1_agent_m0_writedata), // .writedata
.uav_lock (pll_rom_s1_agent_m0_lock), // .lock
.uav_debugaccess (pll_rom_s1_agent_m0_debugaccess), // .debugaccess
.av_address (pll_rom_s1_address), // avalon_anti_slave_0.address
.av_write (pll_rom_s1_write), // .write
.av_readdata (pll_rom_s1_readdata), // .readdata
.av_writedata (pll_rom_s1_writedata), // .writedata
.av_byteenable (pll_rom_s1_byteenable), // .byteenable
.av_chipselect (pll_rom_s1_chipselect), // .chipselect
.av_clken (pll_rom_s1_clken), // .clken
.av_debugaccess (pll_rom_s1_debugaccess), // .debugaccess
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (11),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) counter_s_translator (
.clk (global_routing_kernel_clk_global_clk_clk), // clk.clk
.reset (counter_clk_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (counter_s_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (counter_s_agent_m0_burstcount), // .burstcount
.uav_read (counter_s_agent_m0_read), // .read
.uav_write (counter_s_agent_m0_write), // .write
.uav_waitrequest (counter_s_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (counter_s_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (counter_s_agent_m0_byteenable), // .byteenable
.uav_readdata (counter_s_agent_m0_readdata), // .readdata
.uav_writedata (counter_s_agent_m0_writedata), // .writedata
.uav_lock (counter_s_agent_m0_lock), // .lock
.uav_debugaccess (counter_s_agent_m0_debugaccess), // .debugaccess
.av_address (counter_s_address), // avalon_anti_slave_0.address
.av_write (counter_s_write), // .write
.av_read (counter_s_read), // .read
.av_readdata (counter_s_readdata), // .readdata
.av_writedata (counter_s_writedata), // .writedata
.av_byteenable (counter_s_byteenable), // .byteenable
.av_readdatavalid (counter_s_readdatavalid), // .readdatavalid
.av_waitrequest (counter_s_waitrequest), // .waitrequest
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (1),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (11),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) pll_sw_reset_s_translator (
.clk (clk_clk_clk), // clk.clk
.reset (ctrl_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (pll_sw_reset_s_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (pll_sw_reset_s_agent_m0_burstcount), // .burstcount
.uav_read (pll_sw_reset_s_agent_m0_read), // .read
.uav_write (pll_sw_reset_s_agent_m0_write), // .write
.uav_waitrequest (pll_sw_reset_s_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (pll_sw_reset_s_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (pll_sw_reset_s_agent_m0_byteenable), // .byteenable
.uav_readdata (pll_sw_reset_s_agent_m0_readdata), // .readdata
.uav_writedata (pll_sw_reset_s_agent_m0_writedata), // .writedata
.uav_lock (pll_sw_reset_s_agent_m0_lock), // .lock
.uav_debugaccess (pll_sw_reset_s_agent_m0_debugaccess), // .debugaccess
.av_write (pll_sw_reset_s_write), // avalon_anti_slave_0.write
.av_read (pll_sw_reset_s_read), // .read
.av_readdata (pll_sw_reset_s_readdata), // .readdata
.av_writedata (pll_sw_reset_s_writedata), // .writedata
.av_byteenable (pll_sw_reset_s_byteenable), // .byteenable
.av_waitrequest (pll_sw_reset_s_waitrequest), // .waitrequest
.av_address (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (1),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (11),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) pll_lock_avs_0_s_translator (
.clk (clk_clk_clk), // clk.clk
.reset (ctrl_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (pll_lock_avs_0_s_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (pll_lock_avs_0_s_agent_m0_burstcount), // .burstcount
.uav_read (pll_lock_avs_0_s_agent_m0_read), // .read
.uav_write (pll_lock_avs_0_s_agent_m0_write), // .write
.uav_waitrequest (pll_lock_avs_0_s_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (pll_lock_avs_0_s_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (pll_lock_avs_0_s_agent_m0_byteenable), // .byteenable
.uav_readdata (pll_lock_avs_0_s_agent_m0_readdata), // .readdata
.uav_writedata (pll_lock_avs_0_s_agent_m0_writedata), // .writedata
.uav_lock (pll_lock_avs_0_s_agent_m0_lock), // .lock
.uav_debugaccess (pll_lock_avs_0_s_agent_m0_debugaccess), // .debugaccess
.av_read (pll_lock_avs_0_s_read), // avalon_anti_slave_0.read
.av_readdata (pll_lock_avs_0_s_readdata), // .readdata
.av_address (), // (terminated)
.av_write (), // (terminated)
.av_writedata (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (1),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (11),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) version_id_0_s_translator (
.clk (clk_clk_clk), // clk.clk
.reset (ctrl_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (version_id_0_s_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (version_id_0_s_agent_m0_burstcount), // .burstcount
.uav_read (version_id_0_s_agent_m0_read), // .read
.uav_write (version_id_0_s_agent_m0_write), // .write
.uav_waitrequest (version_id_0_s_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (version_id_0_s_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (version_id_0_s_agent_m0_byteenable), // .byteenable
.uav_readdata (version_id_0_s_agent_m0_readdata), // .readdata
.uav_writedata (version_id_0_s_agent_m0_writedata), // .writedata
.uav_lock (version_id_0_s_agent_m0_lock), // .lock
.uav_debugaccess (version_id_0_s_agent_m0_debugaccess), // .debugaccess
.av_read (version_id_0_s_read), // avalon_anti_slave_0.read
.av_readdata (version_id_0_s_readdata), // .readdata
.av_address (), // (terminated)
.av_write (), // (terminated)
.av_writedata (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_master_agent #(
.PKT_PROTECTION_H (75),
.PKT_PROTECTION_L (73),
.PKT_BEGIN_BURST (64),
.PKT_BURSTWRAP_H (56),
.PKT_BURSTWRAP_L (56),
.PKT_BURST_SIZE_H (59),
.PKT_BURST_SIZE_L (57),
.PKT_BURST_TYPE_H (61),
.PKT_BURST_TYPE_L (60),
.PKT_BYTE_CNT_H (55),
.PKT_BYTE_CNT_L (53),
.PKT_ADDR_H (46),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (47),
.PKT_TRANS_POSTED (48),
.PKT_TRANS_WRITE (49),
.PKT_TRANS_READ (50),
.PKT_TRANS_LOCK (51),
.PKT_TRANS_EXCLUSIVE (52),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (68),
.PKT_SRC_ID_L (66),
.PKT_DEST_ID_H (71),
.PKT_DEST_ID_L (69),
.PKT_THREAD_ID_H (72),
.PKT_THREAD_ID_L (72),
.PKT_CACHE_H (79),
.PKT_CACHE_L (76),
.PKT_DATA_SIDEBAND_H (63),
.PKT_DATA_SIDEBAND_L (63),
.PKT_QOS_H (65),
.PKT_QOS_L (65),
.PKT_ADDR_SIDEBAND_H (62),
.PKT_ADDR_SIDEBAND_L (62),
.PKT_RESPONSE_STATUS_H (81),
.PKT_RESPONSE_STATUS_L (80),
.PKT_ORI_BURST_SIZE_L (82),
.PKT_ORI_BURST_SIZE_H (84),
.ST_DATA_W (85),
.ST_CHANNEL_W (6),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (0),
.BURSTWRAP_VALUE (1),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) ctrl_m0_agent (
.clk (clk_clk_clk), // clk.clk
.reset (ctrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (ctrl_m0_translator_avalon_universal_master_0_address), // av.address
.av_write (ctrl_m0_translator_avalon_universal_master_0_write), // .write
.av_read (ctrl_m0_translator_avalon_universal_master_0_read), // .read
.av_writedata (ctrl_m0_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (ctrl_m0_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (ctrl_m0_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (ctrl_m0_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (ctrl_m0_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (ctrl_m0_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (ctrl_m0_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (ctrl_m0_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (ctrl_m0_agent_cp_valid), // cp.valid
.cp_data (ctrl_m0_agent_cp_data), // .data
.cp_startofpacket (ctrl_m0_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (ctrl_m0_agent_cp_endofpacket), // .endofpacket
.cp_ready (ctrl_m0_agent_cp_ready), // .ready
.rp_valid (ctrl_m0_limiter_rsp_src_valid), // rp.valid
.rp_data (ctrl_m0_limiter_rsp_src_data), // .data
.rp_channel (ctrl_m0_limiter_rsp_src_channel), // .channel
.rp_startofpacket (ctrl_m0_limiter_rsp_src_startofpacket), // .startofpacket
.rp_endofpacket (ctrl_m0_limiter_rsp_src_endofpacket), // .endofpacket
.rp_ready (ctrl_m0_limiter_rsp_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponserequest (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (64),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (46),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (47),
.PKT_TRANS_POSTED (48),
.PKT_TRANS_WRITE (49),
.PKT_TRANS_READ (50),
.PKT_TRANS_LOCK (51),
.PKT_SRC_ID_H (68),
.PKT_SRC_ID_L (66),
.PKT_DEST_ID_H (71),
.PKT_DEST_ID_L (69),
.PKT_BURSTWRAP_H (56),
.PKT_BURSTWRAP_L (56),
.PKT_BYTE_CNT_H (55),
.PKT_BYTE_CNT_L (53),
.PKT_PROTECTION_H (75),
.PKT_PROTECTION_L (73),
.PKT_RESPONSE_STATUS_H (81),
.PKT_RESPONSE_STATUS_L (80),
.PKT_BURST_SIZE_H (59),
.PKT_BURST_SIZE_L (57),
.PKT_ORI_BURST_SIZE_L (82),
.PKT_ORI_BURST_SIZE_H (84),
.ST_CHANNEL_W (6),
.ST_DATA_W (85),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) pll_reconfig_0_mgmt_avalon_slave_agent (
.clk (clk_clk_clk), // clk.clk
.reset (ctrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (pll_reconfig_0_mgmt_avalon_slave_agent_m0_address), // m0.address
.m0_burstcount (pll_reconfig_0_mgmt_avalon_slave_agent_m0_burstcount), // .burstcount
.m0_byteenable (pll_reconfig_0_mgmt_avalon_slave_agent_m0_byteenable), // .byteenable
.m0_debugaccess (pll_reconfig_0_mgmt_avalon_slave_agent_m0_debugaccess), // .debugaccess
.m0_lock (pll_reconfig_0_mgmt_avalon_slave_agent_m0_lock), // .lock
.m0_readdata (pll_reconfig_0_mgmt_avalon_slave_agent_m0_readdata), // .readdata
.m0_readdatavalid (pll_reconfig_0_mgmt_avalon_slave_agent_m0_readdatavalid), // .readdatavalid
.m0_read (pll_reconfig_0_mgmt_avalon_slave_agent_m0_read), // .read
.m0_waitrequest (pll_reconfig_0_mgmt_avalon_slave_agent_m0_waitrequest), // .waitrequest
.m0_writedata (pll_reconfig_0_mgmt_avalon_slave_agent_m0_writedata), // .writedata
.m0_write (pll_reconfig_0_mgmt_avalon_slave_agent_m0_write), // .write
.rp_endofpacket (pll_reconfig_0_mgmt_avalon_slave_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (pll_reconfig_0_mgmt_avalon_slave_agent_rp_ready), // .ready
.rp_valid (pll_reconfig_0_mgmt_avalon_slave_agent_rp_valid), // .valid
.rp_data (pll_reconfig_0_mgmt_avalon_slave_agent_rp_data), // .data
.rp_startofpacket (pll_reconfig_0_mgmt_avalon_slave_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_src_ready), // cp.ready
.cp_valid (cmd_mux_src_valid), // .valid
.cp_data (cmd_mux_src_data), // .data
.cp_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_src_channel), // .channel
.rf_sink_ready (pll_reconfig_0_mgmt_avalon_slave_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (pll_reconfig_0_mgmt_avalon_slave_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (pll_reconfig_0_mgmt_avalon_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (pll_reconfig_0_mgmt_avalon_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (pll_reconfig_0_mgmt_avalon_slave_agent_rsp_fifo_out_data), // .data
.rf_source_ready (pll_reconfig_0_mgmt_avalon_slave_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (pll_reconfig_0_mgmt_avalon_slave_agent_rf_source_valid), // .valid
.rf_source_startofpacket (pll_reconfig_0_mgmt_avalon_slave_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (pll_reconfig_0_mgmt_avalon_slave_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (pll_reconfig_0_mgmt_avalon_slave_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (pll_reconfig_0_mgmt_avalon_slave_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (pll_reconfig_0_mgmt_avalon_slave_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (pll_reconfig_0_mgmt_avalon_slave_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (pll_reconfig_0_mgmt_avalon_slave_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (pll_reconfig_0_mgmt_avalon_slave_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (pll_reconfig_0_mgmt_avalon_slave_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (86),
.FIFO_DEPTH (4),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) pll_reconfig_0_mgmt_avalon_slave_agent_rsp_fifo (
.clk (clk_clk_clk), // clk.clk
.reset (ctrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (pll_reconfig_0_mgmt_avalon_slave_agent_rf_source_data), // in.data
.in_valid (pll_reconfig_0_mgmt_avalon_slave_agent_rf_source_valid), // .valid
.in_ready (pll_reconfig_0_mgmt_avalon_slave_agent_rf_source_ready), // .ready
.in_startofpacket (pll_reconfig_0_mgmt_avalon_slave_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (pll_reconfig_0_mgmt_avalon_slave_agent_rf_source_endofpacket), // .endofpacket
.out_data (pll_reconfig_0_mgmt_avalon_slave_agent_rsp_fifo_out_data), // out.data
.out_valid (pll_reconfig_0_mgmt_avalon_slave_agent_rsp_fifo_out_valid), // .valid
.out_ready (pll_reconfig_0_mgmt_avalon_slave_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (pll_reconfig_0_mgmt_avalon_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (pll_reconfig_0_mgmt_avalon_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (64),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (46),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (47),
.PKT_TRANS_POSTED (48),
.PKT_TRANS_WRITE (49),
.PKT_TRANS_READ (50),
.PKT_TRANS_LOCK (51),
.PKT_SRC_ID_H (68),
.PKT_SRC_ID_L (66),
.PKT_DEST_ID_H (71),
.PKT_DEST_ID_L (69),
.PKT_BURSTWRAP_H (56),
.PKT_BURSTWRAP_L (56),
.PKT_BYTE_CNT_H (55),
.PKT_BYTE_CNT_L (53),
.PKT_PROTECTION_H (75),
.PKT_PROTECTION_L (73),
.PKT_RESPONSE_STATUS_H (81),
.PKT_RESPONSE_STATUS_L (80),
.PKT_BURST_SIZE_H (59),
.PKT_BURST_SIZE_L (57),
.PKT_ORI_BURST_SIZE_L (82),
.PKT_ORI_BURST_SIZE_H (84),
.ST_CHANNEL_W (6),
.ST_DATA_W (85),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) pll_rom_s1_agent (
.clk (clk_clk_clk), // clk.clk
.reset (ctrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (pll_rom_s1_agent_m0_address), // m0.address
.m0_burstcount (pll_rom_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (pll_rom_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (pll_rom_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (pll_rom_s1_agent_m0_lock), // .lock
.m0_readdata (pll_rom_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (pll_rom_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (pll_rom_s1_agent_m0_read), // .read
.m0_waitrequest (pll_rom_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (pll_rom_s1_agent_m0_writedata), // .writedata
.m0_write (pll_rom_s1_agent_m0_write), // .write
.rp_endofpacket (pll_rom_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (pll_rom_s1_agent_rp_ready), // .ready
.rp_valid (pll_rom_s1_agent_rp_valid), // .valid
.rp_data (pll_rom_s1_agent_rp_data), // .data
.rp_startofpacket (pll_rom_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_001_src_ready), // cp.ready
.cp_valid (cmd_mux_001_src_valid), // .valid
.cp_data (cmd_mux_001_src_data), // .data
.cp_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_001_src_channel), // .channel
.rf_sink_ready (pll_rom_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (pll_rom_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (pll_rom_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (pll_rom_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (pll_rom_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (pll_rom_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (pll_rom_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (pll_rom_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (pll_rom_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (pll_rom_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (pll_rom_s1_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (pll_rom_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (pll_rom_s1_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (pll_rom_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (pll_rom_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (pll_rom_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (86),
.FIFO_DEPTH (3),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) pll_rom_s1_agent_rsp_fifo (
.clk (clk_clk_clk), // clk.clk
.reset (ctrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (pll_rom_s1_agent_rf_source_data), // in.data
.in_valid (pll_rom_s1_agent_rf_source_valid), // .valid
.in_ready (pll_rom_s1_agent_rf_source_ready), // .ready
.in_startofpacket (pll_rom_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (pll_rom_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (pll_rom_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (pll_rom_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (pll_rom_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (pll_rom_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (pll_rom_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (64),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (46),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (47),
.PKT_TRANS_POSTED (48),
.PKT_TRANS_WRITE (49),
.PKT_TRANS_READ (50),
.PKT_TRANS_LOCK (51),
.PKT_SRC_ID_H (68),
.PKT_SRC_ID_L (66),
.PKT_DEST_ID_H (71),
.PKT_DEST_ID_L (69),
.PKT_BURSTWRAP_H (56),
.PKT_BURSTWRAP_L (56),
.PKT_BYTE_CNT_H (55),
.PKT_BYTE_CNT_L (53),
.PKT_PROTECTION_H (75),
.PKT_PROTECTION_L (73),
.PKT_RESPONSE_STATUS_H (81),
.PKT_RESPONSE_STATUS_L (80),
.PKT_BURST_SIZE_H (59),
.PKT_BURST_SIZE_L (57),
.PKT_ORI_BURST_SIZE_L (82),
.PKT_ORI_BURST_SIZE_H (84),
.ST_CHANNEL_W (6),
.ST_DATA_W (85),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) counter_s_agent (
.clk (global_routing_kernel_clk_global_clk_clk), // clk.clk
.reset (counter_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (counter_s_agent_m0_address), // m0.address
.m0_burstcount (counter_s_agent_m0_burstcount), // .burstcount
.m0_byteenable (counter_s_agent_m0_byteenable), // .byteenable
.m0_debugaccess (counter_s_agent_m0_debugaccess), // .debugaccess
.m0_lock (counter_s_agent_m0_lock), // .lock
.m0_readdata (counter_s_agent_m0_readdata), // .readdata
.m0_readdatavalid (counter_s_agent_m0_readdatavalid), // .readdatavalid
.m0_read (counter_s_agent_m0_read), // .read
.m0_waitrequest (counter_s_agent_m0_waitrequest), // .waitrequest
.m0_writedata (counter_s_agent_m0_writedata), // .writedata
.m0_write (counter_s_agent_m0_write), // .write
.rp_endofpacket (counter_s_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (counter_s_agent_rp_ready), // .ready
.rp_valid (counter_s_agent_rp_valid), // .valid
.rp_data (counter_s_agent_rp_data), // .data
.rp_startofpacket (counter_s_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_002_src_ready), // cp.ready
.cp_valid (cmd_mux_002_src_valid), // .valid
.cp_data (cmd_mux_002_src_data), // .data
.cp_startofpacket (cmd_mux_002_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_002_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_002_src_channel), // .channel
.rf_sink_ready (counter_s_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (counter_s_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (counter_s_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (counter_s_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (counter_s_agent_rsp_fifo_out_data), // .data
.rf_source_ready (counter_s_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (counter_s_agent_rf_source_valid), // .valid
.rf_source_startofpacket (counter_s_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (counter_s_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (counter_s_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (counter_s_agent_rdata_fifo_out_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (counter_s_agent_rdata_fifo_out_valid), // .valid
.rdata_fifo_sink_data (counter_s_agent_rdata_fifo_out_data), // .data
.rdata_fifo_src_ready (counter_s_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (counter_s_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (counter_s_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (86),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) counter_s_agent_rsp_fifo (
.clk (global_routing_kernel_clk_global_clk_clk), // clk.clk
.reset (counter_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (counter_s_agent_rf_source_data), // in.data
.in_valid (counter_s_agent_rf_source_valid), // .valid
.in_ready (counter_s_agent_rf_source_ready), // .ready
.in_startofpacket (counter_s_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (counter_s_agent_rf_source_endofpacket), // .endofpacket
.out_data (counter_s_agent_rsp_fifo_out_data), // out.data
.out_valid (counter_s_agent_rsp_fifo_out_valid), // .valid
.out_ready (counter_s_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (counter_s_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (counter_s_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (34),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (0),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (0),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) counter_s_agent_rdata_fifo (
.clk (global_routing_kernel_clk_global_clk_clk), // clk.clk
.reset (counter_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (counter_s_agent_rdata_fifo_src_data), // in.data
.in_valid (counter_s_agent_rdata_fifo_src_valid), // .valid
.in_ready (counter_s_agent_rdata_fifo_src_ready), // .ready
.out_data (counter_s_agent_rdata_fifo_out_data), // out.data
.out_valid (counter_s_agent_rdata_fifo_out_valid), // .valid
.out_ready (counter_s_agent_rdata_fifo_out_ready), // .ready
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_startofpacket (1'b0), // (terminated)
.in_endofpacket (1'b0), // (terminated)
.out_startofpacket (), // (terminated)
.out_endofpacket (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (64),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (46),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (47),
.PKT_TRANS_POSTED (48),
.PKT_TRANS_WRITE (49),
.PKT_TRANS_READ (50),
.PKT_TRANS_LOCK (51),
.PKT_SRC_ID_H (68),
.PKT_SRC_ID_L (66),
.PKT_DEST_ID_H (71),
.PKT_DEST_ID_L (69),
.PKT_BURSTWRAP_H (56),
.PKT_BURSTWRAP_L (56),
.PKT_BYTE_CNT_H (55),
.PKT_BYTE_CNT_L (53),
.PKT_PROTECTION_H (75),
.PKT_PROTECTION_L (73),
.PKT_RESPONSE_STATUS_H (81),
.PKT_RESPONSE_STATUS_L (80),
.PKT_BURST_SIZE_H (59),
.PKT_BURST_SIZE_L (57),
.PKT_ORI_BURST_SIZE_L (82),
.PKT_ORI_BURST_SIZE_H (84),
.ST_CHANNEL_W (6),
.ST_DATA_W (85),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) pll_sw_reset_s_agent (
.clk (clk_clk_clk), // clk.clk
.reset (ctrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (pll_sw_reset_s_agent_m0_address), // m0.address
.m0_burstcount (pll_sw_reset_s_agent_m0_burstcount), // .burstcount
.m0_byteenable (pll_sw_reset_s_agent_m0_byteenable), // .byteenable
.m0_debugaccess (pll_sw_reset_s_agent_m0_debugaccess), // .debugaccess
.m0_lock (pll_sw_reset_s_agent_m0_lock), // .lock
.m0_readdata (pll_sw_reset_s_agent_m0_readdata), // .readdata
.m0_readdatavalid (pll_sw_reset_s_agent_m0_readdatavalid), // .readdatavalid
.m0_read (pll_sw_reset_s_agent_m0_read), // .read
.m0_waitrequest (pll_sw_reset_s_agent_m0_waitrequest), // .waitrequest
.m0_writedata (pll_sw_reset_s_agent_m0_writedata), // .writedata
.m0_write (pll_sw_reset_s_agent_m0_write), // .write
.rp_endofpacket (pll_sw_reset_s_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (pll_sw_reset_s_agent_rp_ready), // .ready
.rp_valid (pll_sw_reset_s_agent_rp_valid), // .valid
.rp_data (pll_sw_reset_s_agent_rp_data), // .data
.rp_startofpacket (pll_sw_reset_s_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_003_src_ready), // cp.ready
.cp_valid (cmd_mux_003_src_valid), // .valid
.cp_data (cmd_mux_003_src_data), // .data
.cp_startofpacket (cmd_mux_003_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_003_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_003_src_channel), // .channel
.rf_sink_ready (pll_sw_reset_s_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (pll_sw_reset_s_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (pll_sw_reset_s_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (pll_sw_reset_s_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (pll_sw_reset_s_agent_rsp_fifo_out_data), // .data
.rf_source_ready (pll_sw_reset_s_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (pll_sw_reset_s_agent_rf_source_valid), // .valid
.rf_source_startofpacket (pll_sw_reset_s_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (pll_sw_reset_s_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (pll_sw_reset_s_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (pll_sw_reset_s_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (pll_sw_reset_s_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (pll_sw_reset_s_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (pll_sw_reset_s_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (pll_sw_reset_s_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (pll_sw_reset_s_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (86),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) pll_sw_reset_s_agent_rsp_fifo (
.clk (clk_clk_clk), // clk.clk
.reset (ctrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (pll_sw_reset_s_agent_rf_source_data), // in.data
.in_valid (pll_sw_reset_s_agent_rf_source_valid), // .valid
.in_ready (pll_sw_reset_s_agent_rf_source_ready), // .ready
.in_startofpacket (pll_sw_reset_s_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (pll_sw_reset_s_agent_rf_source_endofpacket), // .endofpacket
.out_data (pll_sw_reset_s_agent_rsp_fifo_out_data), // out.data
.out_valid (pll_sw_reset_s_agent_rsp_fifo_out_valid), // .valid
.out_ready (pll_sw_reset_s_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (pll_sw_reset_s_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (pll_sw_reset_s_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (64),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (46),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (47),
.PKT_TRANS_POSTED (48),
.PKT_TRANS_WRITE (49),
.PKT_TRANS_READ (50),
.PKT_TRANS_LOCK (51),
.PKT_SRC_ID_H (68),
.PKT_SRC_ID_L (66),
.PKT_DEST_ID_H (71),
.PKT_DEST_ID_L (69),
.PKT_BURSTWRAP_H (56),
.PKT_BURSTWRAP_L (56),
.PKT_BYTE_CNT_H (55),
.PKT_BYTE_CNT_L (53),
.PKT_PROTECTION_H (75),
.PKT_PROTECTION_L (73),
.PKT_RESPONSE_STATUS_H (81),
.PKT_RESPONSE_STATUS_L (80),
.PKT_BURST_SIZE_H (59),
.PKT_BURST_SIZE_L (57),
.PKT_ORI_BURST_SIZE_L (82),
.PKT_ORI_BURST_SIZE_H (84),
.ST_CHANNEL_W (6),
.ST_DATA_W (85),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) pll_lock_avs_0_s_agent (
.clk (clk_clk_clk), // clk.clk
.reset (ctrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (pll_lock_avs_0_s_agent_m0_address), // m0.address
.m0_burstcount (pll_lock_avs_0_s_agent_m0_burstcount), // .burstcount
.m0_byteenable (pll_lock_avs_0_s_agent_m0_byteenable), // .byteenable
.m0_debugaccess (pll_lock_avs_0_s_agent_m0_debugaccess), // .debugaccess
.m0_lock (pll_lock_avs_0_s_agent_m0_lock), // .lock
.m0_readdata (pll_lock_avs_0_s_agent_m0_readdata), // .readdata
.m0_readdatavalid (pll_lock_avs_0_s_agent_m0_readdatavalid), // .readdatavalid
.m0_read (pll_lock_avs_0_s_agent_m0_read), // .read
.m0_waitrequest (pll_lock_avs_0_s_agent_m0_waitrequest), // .waitrequest
.m0_writedata (pll_lock_avs_0_s_agent_m0_writedata), // .writedata
.m0_write (pll_lock_avs_0_s_agent_m0_write), // .write
.rp_endofpacket (pll_lock_avs_0_s_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (pll_lock_avs_0_s_agent_rp_ready), // .ready
.rp_valid (pll_lock_avs_0_s_agent_rp_valid), // .valid
.rp_data (pll_lock_avs_0_s_agent_rp_data), // .data
.rp_startofpacket (pll_lock_avs_0_s_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_004_src_ready), // cp.ready
.cp_valid (cmd_mux_004_src_valid), // .valid
.cp_data (cmd_mux_004_src_data), // .data
.cp_startofpacket (cmd_mux_004_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_004_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_004_src_channel), // .channel
.rf_sink_ready (pll_lock_avs_0_s_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (pll_lock_avs_0_s_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (pll_lock_avs_0_s_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (pll_lock_avs_0_s_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (pll_lock_avs_0_s_agent_rsp_fifo_out_data), // .data
.rf_source_ready (pll_lock_avs_0_s_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (pll_lock_avs_0_s_agent_rf_source_valid), // .valid
.rf_source_startofpacket (pll_lock_avs_0_s_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (pll_lock_avs_0_s_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (pll_lock_avs_0_s_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (pll_lock_avs_0_s_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (pll_lock_avs_0_s_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (pll_lock_avs_0_s_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (pll_lock_avs_0_s_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (pll_lock_avs_0_s_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (pll_lock_avs_0_s_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (86),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) pll_lock_avs_0_s_agent_rsp_fifo (
.clk (clk_clk_clk), // clk.clk
.reset (ctrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (pll_lock_avs_0_s_agent_rf_source_data), // in.data
.in_valid (pll_lock_avs_0_s_agent_rf_source_valid), // .valid
.in_ready (pll_lock_avs_0_s_agent_rf_source_ready), // .ready
.in_startofpacket (pll_lock_avs_0_s_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (pll_lock_avs_0_s_agent_rf_source_endofpacket), // .endofpacket
.out_data (pll_lock_avs_0_s_agent_rsp_fifo_out_data), // out.data
.out_valid (pll_lock_avs_0_s_agent_rsp_fifo_out_valid), // .valid
.out_ready (pll_lock_avs_0_s_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (pll_lock_avs_0_s_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (pll_lock_avs_0_s_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (64),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (46),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (47),
.PKT_TRANS_POSTED (48),
.PKT_TRANS_WRITE (49),
.PKT_TRANS_READ (50),
.PKT_TRANS_LOCK (51),
.PKT_SRC_ID_H (68),
.PKT_SRC_ID_L (66),
.PKT_DEST_ID_H (71),
.PKT_DEST_ID_L (69),
.PKT_BURSTWRAP_H (56),
.PKT_BURSTWRAP_L (56),
.PKT_BYTE_CNT_H (55),
.PKT_BYTE_CNT_L (53),
.PKT_PROTECTION_H (75),
.PKT_PROTECTION_L (73),
.PKT_RESPONSE_STATUS_H (81),
.PKT_RESPONSE_STATUS_L (80),
.PKT_BURST_SIZE_H (59),
.PKT_BURST_SIZE_L (57),
.PKT_ORI_BURST_SIZE_L (82),
.PKT_ORI_BURST_SIZE_H (84),
.ST_CHANNEL_W (6),
.ST_DATA_W (85),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) version_id_0_s_agent (
.clk (clk_clk_clk), // clk.clk
.reset (ctrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (version_id_0_s_agent_m0_address), // m0.address
.m0_burstcount (version_id_0_s_agent_m0_burstcount), // .burstcount
.m0_byteenable (version_id_0_s_agent_m0_byteenable), // .byteenable
.m0_debugaccess (version_id_0_s_agent_m0_debugaccess), // .debugaccess
.m0_lock (version_id_0_s_agent_m0_lock), // .lock
.m0_readdata (version_id_0_s_agent_m0_readdata), // .readdata
.m0_readdatavalid (version_id_0_s_agent_m0_readdatavalid), // .readdatavalid
.m0_read (version_id_0_s_agent_m0_read), // .read
.m0_waitrequest (version_id_0_s_agent_m0_waitrequest), // .waitrequest
.m0_writedata (version_id_0_s_agent_m0_writedata), // .writedata
.m0_write (version_id_0_s_agent_m0_write), // .write
.rp_endofpacket (version_id_0_s_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (version_id_0_s_agent_rp_ready), // .ready
.rp_valid (version_id_0_s_agent_rp_valid), // .valid
.rp_data (version_id_0_s_agent_rp_data), // .data
.rp_startofpacket (version_id_0_s_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_005_src_ready), // cp.ready
.cp_valid (cmd_mux_005_src_valid), // .valid
.cp_data (cmd_mux_005_src_data), // .data
.cp_startofpacket (cmd_mux_005_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_005_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_005_src_channel), // .channel
.rf_sink_ready (version_id_0_s_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (version_id_0_s_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (version_id_0_s_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (version_id_0_s_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (version_id_0_s_agent_rsp_fifo_out_data), // .data
.rf_source_ready (version_id_0_s_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (version_id_0_s_agent_rf_source_valid), // .valid
.rf_source_startofpacket (version_id_0_s_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (version_id_0_s_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (version_id_0_s_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (version_id_0_s_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (version_id_0_s_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (version_id_0_s_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (version_id_0_s_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (version_id_0_s_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (version_id_0_s_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (86),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) version_id_0_s_agent_rsp_fifo (
.clk (clk_clk_clk), // clk.clk
.reset (ctrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (version_id_0_s_agent_rf_source_data), // in.data
.in_valid (version_id_0_s_agent_rf_source_valid), // .valid
.in_ready (version_id_0_s_agent_rf_source_ready), // .ready
.in_startofpacket (version_id_0_s_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (version_id_0_s_agent_rf_source_endofpacket), // .endofpacket
.out_data (version_id_0_s_agent_rsp_fifo_out_data), // out.data
.out_valid (version_id_0_s_agent_rsp_fifo_out_valid), // .valid
.out_ready (version_id_0_s_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (version_id_0_s_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (version_id_0_s_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
system_acl_iface_acl_kernel_clk_mm_interconnect_0_router router (
.sink_ready (ctrl_m0_agent_cp_ready), // sink.ready
.sink_valid (ctrl_m0_agent_cp_valid), // .valid
.sink_data (ctrl_m0_agent_cp_data), // .data
.sink_startofpacket (ctrl_m0_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (ctrl_m0_agent_cp_endofpacket), // .endofpacket
.clk (clk_clk_clk), // clk.clk
.reset (ctrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_src_ready), // src.ready
.src_valid (router_src_valid), // .valid
.src_data (router_src_data), // .data
.src_channel (router_src_channel), // .channel
.src_startofpacket (router_src_startofpacket), // .startofpacket
.src_endofpacket (router_src_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_clk_mm_interconnect_0_router_001 router_001 (
.sink_ready (pll_reconfig_0_mgmt_avalon_slave_agent_rp_ready), // sink.ready
.sink_valid (pll_reconfig_0_mgmt_avalon_slave_agent_rp_valid), // .valid
.sink_data (pll_reconfig_0_mgmt_avalon_slave_agent_rp_data), // .data
.sink_startofpacket (pll_reconfig_0_mgmt_avalon_slave_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (pll_reconfig_0_mgmt_avalon_slave_agent_rp_endofpacket), // .endofpacket
.clk (clk_clk_clk), // clk.clk
.reset (ctrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_001_src_ready), // src.ready
.src_valid (router_001_src_valid), // .valid
.src_data (router_001_src_data), // .data
.src_channel (router_001_src_channel), // .channel
.src_startofpacket (router_001_src_startofpacket), // .startofpacket
.src_endofpacket (router_001_src_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_clk_mm_interconnect_0_router_001 router_002 (
.sink_ready (pll_rom_s1_agent_rp_ready), // sink.ready
.sink_valid (pll_rom_s1_agent_rp_valid), // .valid
.sink_data (pll_rom_s1_agent_rp_data), // .data
.sink_startofpacket (pll_rom_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (pll_rom_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_clk_clk), // clk.clk
.reset (ctrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_002_src_ready), // src.ready
.src_valid (router_002_src_valid), // .valid
.src_data (router_002_src_data), // .data
.src_channel (router_002_src_channel), // .channel
.src_startofpacket (router_002_src_startofpacket), // .startofpacket
.src_endofpacket (router_002_src_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_clk_mm_interconnect_0_router_003 router_003 (
.sink_ready (counter_s_agent_rp_ready), // sink.ready
.sink_valid (counter_s_agent_rp_valid), // .valid
.sink_data (counter_s_agent_rp_data), // .data
.sink_startofpacket (counter_s_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (counter_s_agent_rp_endofpacket), // .endofpacket
.clk (global_routing_kernel_clk_global_clk_clk), // clk.clk
.reset (counter_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_003_src_ready), // src.ready
.src_valid (router_003_src_valid), // .valid
.src_data (router_003_src_data), // .data
.src_channel (router_003_src_channel), // .channel
.src_startofpacket (router_003_src_startofpacket), // .startofpacket
.src_endofpacket (router_003_src_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_clk_mm_interconnect_0_router_001 router_004 (
.sink_ready (pll_sw_reset_s_agent_rp_ready), // sink.ready
.sink_valid (pll_sw_reset_s_agent_rp_valid), // .valid
.sink_data (pll_sw_reset_s_agent_rp_data), // .data
.sink_startofpacket (pll_sw_reset_s_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (pll_sw_reset_s_agent_rp_endofpacket), // .endofpacket
.clk (clk_clk_clk), // clk.clk
.reset (ctrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_004_src_ready), // src.ready
.src_valid (router_004_src_valid), // .valid
.src_data (router_004_src_data), // .data
.src_channel (router_004_src_channel), // .channel
.src_startofpacket (router_004_src_startofpacket), // .startofpacket
.src_endofpacket (router_004_src_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_clk_mm_interconnect_0_router_001 router_005 (
.sink_ready (pll_lock_avs_0_s_agent_rp_ready), // sink.ready
.sink_valid (pll_lock_avs_0_s_agent_rp_valid), // .valid
.sink_data (pll_lock_avs_0_s_agent_rp_data), // .data
.sink_startofpacket (pll_lock_avs_0_s_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (pll_lock_avs_0_s_agent_rp_endofpacket), // .endofpacket
.clk (clk_clk_clk), // clk.clk
.reset (ctrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_005_src_ready), // src.ready
.src_valid (router_005_src_valid), // .valid
.src_data (router_005_src_data), // .data
.src_channel (router_005_src_channel), // .channel
.src_startofpacket (router_005_src_startofpacket), // .startofpacket
.src_endofpacket (router_005_src_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_clk_mm_interconnect_0_router_001 router_006 (
.sink_ready (version_id_0_s_agent_rp_ready), // sink.ready
.sink_valid (version_id_0_s_agent_rp_valid), // .valid
.sink_data (version_id_0_s_agent_rp_data), // .data
.sink_startofpacket (version_id_0_s_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (version_id_0_s_agent_rp_endofpacket), // .endofpacket
.clk (clk_clk_clk), // clk.clk
.reset (ctrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_006_src_ready), // src.ready
.src_valid (router_006_src_valid), // .valid
.src_data (router_006_src_data), // .data
.src_channel (router_006_src_channel), // .channel
.src_startofpacket (router_006_src_startofpacket), // .startofpacket
.src_endofpacket (router_006_src_endofpacket) // .endofpacket
);
altera_merlin_traffic_limiter #(
.PKT_DEST_ID_H (71),
.PKT_DEST_ID_L (69),
.PKT_SRC_ID_H (68),
.PKT_SRC_ID_L (66),
.PKT_TRANS_POSTED (48),
.PKT_TRANS_WRITE (49),
.MAX_OUTSTANDING_RESPONSES (5),
.PIPELINED (0),
.ST_DATA_W (85),
.ST_CHANNEL_W (6),
.VALID_WIDTH (6),
.ENFORCE_ORDER (1),
.PREVENT_HAZARDS (0),
.PKT_BYTE_CNT_H (55),
.PKT_BYTE_CNT_L (53),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.REORDER (0)
) ctrl_m0_limiter (
.clk (clk_clk_clk), // clk.clk
.reset (ctrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.cmd_sink_ready (router_src_ready), // cmd_sink.ready
.cmd_sink_valid (router_src_valid), // .valid
.cmd_sink_data (router_src_data), // .data
.cmd_sink_channel (router_src_channel), // .channel
.cmd_sink_startofpacket (router_src_startofpacket), // .startofpacket
.cmd_sink_endofpacket (router_src_endofpacket), // .endofpacket
.cmd_src_ready (ctrl_m0_limiter_cmd_src_ready), // cmd_src.ready
.cmd_src_data (ctrl_m0_limiter_cmd_src_data), // .data
.cmd_src_channel (ctrl_m0_limiter_cmd_src_channel), // .channel
.cmd_src_startofpacket (ctrl_m0_limiter_cmd_src_startofpacket), // .startofpacket
.cmd_src_endofpacket (ctrl_m0_limiter_cmd_src_endofpacket), // .endofpacket
.rsp_sink_ready (rsp_mux_src_ready), // rsp_sink.ready
.rsp_sink_valid (rsp_mux_src_valid), // .valid
.rsp_sink_channel (rsp_mux_src_channel), // .channel
.rsp_sink_data (rsp_mux_src_data), // .data
.rsp_sink_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.rsp_sink_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.rsp_src_ready (ctrl_m0_limiter_rsp_src_ready), // rsp_src.ready
.rsp_src_valid (ctrl_m0_limiter_rsp_src_valid), // .valid
.rsp_src_data (ctrl_m0_limiter_rsp_src_data), // .data
.rsp_src_channel (ctrl_m0_limiter_rsp_src_channel), // .channel
.rsp_src_startofpacket (ctrl_m0_limiter_rsp_src_startofpacket), // .startofpacket
.rsp_src_endofpacket (ctrl_m0_limiter_rsp_src_endofpacket), // .endofpacket
.cmd_src_valid (ctrl_m0_limiter_cmd_valid_data) // cmd_valid.data
);
system_acl_iface_acl_kernel_clk_mm_interconnect_0_cmd_demux cmd_demux (
.clk (clk_clk_clk), // clk.clk
.reset (ctrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (ctrl_m0_limiter_cmd_src_ready), // sink.ready
.sink_channel (ctrl_m0_limiter_cmd_src_channel), // .channel
.sink_data (ctrl_m0_limiter_cmd_src_data), // .data
.sink_startofpacket (ctrl_m0_limiter_cmd_src_startofpacket), // .startofpacket
.sink_endofpacket (ctrl_m0_limiter_cmd_src_endofpacket), // .endofpacket
.sink_valid (ctrl_m0_limiter_cmd_valid_data), // sink_valid.data
.src0_ready (cmd_demux_src0_ready), // src0.ready
.src0_valid (cmd_demux_src0_valid), // .valid
.src0_data (cmd_demux_src0_data), // .data
.src0_channel (cmd_demux_src0_channel), // .channel
.src0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_src0_endofpacket), // .endofpacket
.src1_ready (cmd_demux_src1_ready), // src1.ready
.src1_valid (cmd_demux_src1_valid), // .valid
.src1_data (cmd_demux_src1_data), // .data
.src1_channel (cmd_demux_src1_channel), // .channel
.src1_startofpacket (cmd_demux_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_demux_src1_endofpacket), // .endofpacket
.src2_ready (cmd_demux_src2_ready), // src2.ready
.src2_valid (cmd_demux_src2_valid), // .valid
.src2_data (cmd_demux_src2_data), // .data
.src2_channel (cmd_demux_src2_channel), // .channel
.src2_startofpacket (cmd_demux_src2_startofpacket), // .startofpacket
.src2_endofpacket (cmd_demux_src2_endofpacket), // .endofpacket
.src3_ready (cmd_demux_src3_ready), // src3.ready
.src3_valid (cmd_demux_src3_valid), // .valid
.src3_data (cmd_demux_src3_data), // .data
.src3_channel (cmd_demux_src3_channel), // .channel
.src3_startofpacket (cmd_demux_src3_startofpacket), // .startofpacket
.src3_endofpacket (cmd_demux_src3_endofpacket), // .endofpacket
.src4_ready (cmd_demux_src4_ready), // src4.ready
.src4_valid (cmd_demux_src4_valid), // .valid
.src4_data (cmd_demux_src4_data), // .data
.src4_channel (cmd_demux_src4_channel), // .channel
.src4_startofpacket (cmd_demux_src4_startofpacket), // .startofpacket
.src4_endofpacket (cmd_demux_src4_endofpacket), // .endofpacket
.src5_ready (cmd_demux_src5_ready), // src5.ready
.src5_valid (cmd_demux_src5_valid), // .valid
.src5_data (cmd_demux_src5_data), // .data
.src5_channel (cmd_demux_src5_channel), // .channel
.src5_startofpacket (cmd_demux_src5_startofpacket), // .startofpacket
.src5_endofpacket (cmd_demux_src5_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_clk_mm_interconnect_0_cmd_mux cmd_mux (
.clk (clk_clk_clk), // clk.clk
.reset (ctrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_src_ready), // src.ready
.src_valid (cmd_mux_src_valid), // .valid
.src_data (cmd_mux_src_data), // .data
.src_channel (cmd_mux_src_channel), // .channel
.src_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src0_ready), // sink0.ready
.sink0_valid (cmd_demux_src0_valid), // .valid
.sink0_channel (cmd_demux_src0_channel), // .channel
.sink0_data (cmd_demux_src0_data), // .data
.sink0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src0_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_clk_mm_interconnect_0_cmd_mux cmd_mux_001 (
.clk (clk_clk_clk), // clk.clk
.reset (ctrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_001_src_ready), // src.ready
.src_valid (cmd_mux_001_src_valid), // .valid
.src_data (cmd_mux_001_src_data), // .data
.src_channel (cmd_mux_001_src_channel), // .channel
.src_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src1_ready), // sink0.ready
.sink0_valid (cmd_demux_src1_valid), // .valid
.sink0_channel (cmd_demux_src1_channel), // .channel
.sink0_data (cmd_demux_src1_data), // .data
.sink0_startofpacket (cmd_demux_src1_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src1_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_clk_mm_interconnect_0_cmd_mux_002 cmd_mux_002 (
.clk (global_routing_kernel_clk_global_clk_clk), // clk.clk
.reset (counter_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_002_src_ready), // src.ready
.src_valid (cmd_mux_002_src_valid), // .valid
.src_data (cmd_mux_002_src_data), // .data
.src_channel (cmd_mux_002_src_channel), // .channel
.src_startofpacket (cmd_mux_002_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_002_src_endofpacket), // .endofpacket
.sink0_ready (crosser_out_ready), // sink0.ready
.sink0_valid (crosser_out_valid), // .valid
.sink0_channel (crosser_out_channel), // .channel
.sink0_data (crosser_out_data), // .data
.sink0_startofpacket (crosser_out_startofpacket), // .startofpacket
.sink0_endofpacket (crosser_out_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_clk_mm_interconnect_0_cmd_mux cmd_mux_003 (
.clk (clk_clk_clk), // clk.clk
.reset (ctrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_003_src_ready), // src.ready
.src_valid (cmd_mux_003_src_valid), // .valid
.src_data (cmd_mux_003_src_data), // .data
.src_channel (cmd_mux_003_src_channel), // .channel
.src_startofpacket (cmd_mux_003_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_003_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src3_ready), // sink0.ready
.sink0_valid (cmd_demux_src3_valid), // .valid
.sink0_channel (cmd_demux_src3_channel), // .channel
.sink0_data (cmd_demux_src3_data), // .data
.sink0_startofpacket (cmd_demux_src3_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src3_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_clk_mm_interconnect_0_cmd_mux cmd_mux_004 (
.clk (clk_clk_clk), // clk.clk
.reset (ctrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_004_src_ready), // src.ready
.src_valid (cmd_mux_004_src_valid), // .valid
.src_data (cmd_mux_004_src_data), // .data
.src_channel (cmd_mux_004_src_channel), // .channel
.src_startofpacket (cmd_mux_004_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_004_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src4_ready), // sink0.ready
.sink0_valid (cmd_demux_src4_valid), // .valid
.sink0_channel (cmd_demux_src4_channel), // .channel
.sink0_data (cmd_demux_src4_data), // .data
.sink0_startofpacket (cmd_demux_src4_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src4_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_clk_mm_interconnect_0_cmd_mux cmd_mux_005 (
.clk (clk_clk_clk), // clk.clk
.reset (ctrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_005_src_ready), // src.ready
.src_valid (cmd_mux_005_src_valid), // .valid
.src_data (cmd_mux_005_src_data), // .data
.src_channel (cmd_mux_005_src_channel), // .channel
.src_startofpacket (cmd_mux_005_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_005_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src5_ready), // sink0.ready
.sink0_valid (cmd_demux_src5_valid), // .valid
.sink0_channel (cmd_demux_src5_channel), // .channel
.sink0_data (cmd_demux_src5_data), // .data
.sink0_startofpacket (cmd_demux_src5_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src5_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_clk_mm_interconnect_0_rsp_demux rsp_demux (
.clk (clk_clk_clk), // clk.clk
.reset (ctrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_001_src_ready), // sink.ready
.sink_channel (router_001_src_channel), // .channel
.sink_data (router_001_src_data), // .data
.sink_startofpacket (router_001_src_startofpacket), // .startofpacket
.sink_endofpacket (router_001_src_endofpacket), // .endofpacket
.sink_valid (router_001_src_valid), // .valid
.src0_ready (rsp_demux_src0_ready), // src0.ready
.src0_valid (rsp_demux_src0_valid), // .valid
.src0_data (rsp_demux_src0_data), // .data
.src0_channel (rsp_demux_src0_channel), // .channel
.src0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_src0_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_clk_mm_interconnect_0_rsp_demux rsp_demux_001 (
.clk (clk_clk_clk), // clk.clk
.reset (ctrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_002_src_ready), // sink.ready
.sink_channel (router_002_src_channel), // .channel
.sink_data (router_002_src_data), // .data
.sink_startofpacket (router_002_src_startofpacket), // .startofpacket
.sink_endofpacket (router_002_src_endofpacket), // .endofpacket
.sink_valid (router_002_src_valid), // .valid
.src0_ready (rsp_demux_001_src0_ready), // src0.ready
.src0_valid (rsp_demux_001_src0_valid), // .valid
.src0_data (rsp_demux_001_src0_data), // .data
.src0_channel (rsp_demux_001_src0_channel), // .channel
.src0_startofpacket (rsp_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_001_src0_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_clk_mm_interconnect_0_rsp_demux_002 rsp_demux_002 (
.clk (global_routing_kernel_clk_global_clk_clk), // clk.clk
.reset (counter_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_003_src_ready), // sink.ready
.sink_channel (router_003_src_channel), // .channel
.sink_data (router_003_src_data), // .data
.sink_startofpacket (router_003_src_startofpacket), // .startofpacket
.sink_endofpacket (router_003_src_endofpacket), // .endofpacket
.sink_valid (router_003_src_valid), // .valid
.src0_ready (rsp_demux_002_src0_ready), // src0.ready
.src0_valid (rsp_demux_002_src0_valid), // .valid
.src0_data (rsp_demux_002_src0_data), // .data
.src0_channel (rsp_demux_002_src0_channel), // .channel
.src0_startofpacket (rsp_demux_002_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_002_src0_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_clk_mm_interconnect_0_rsp_demux rsp_demux_003 (
.clk (clk_clk_clk), // clk.clk
.reset (ctrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_004_src_ready), // sink.ready
.sink_channel (router_004_src_channel), // .channel
.sink_data (router_004_src_data), // .data
.sink_startofpacket (router_004_src_startofpacket), // .startofpacket
.sink_endofpacket (router_004_src_endofpacket), // .endofpacket
.sink_valid (router_004_src_valid), // .valid
.src0_ready (rsp_demux_003_src0_ready), // src0.ready
.src0_valid (rsp_demux_003_src0_valid), // .valid
.src0_data (rsp_demux_003_src0_data), // .data
.src0_channel (rsp_demux_003_src0_channel), // .channel
.src0_startofpacket (rsp_demux_003_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_003_src0_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_clk_mm_interconnect_0_rsp_demux rsp_demux_004 (
.clk (clk_clk_clk), // clk.clk
.reset (ctrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_005_src_ready), // sink.ready
.sink_channel (router_005_src_channel), // .channel
.sink_data (router_005_src_data), // .data
.sink_startofpacket (router_005_src_startofpacket), // .startofpacket
.sink_endofpacket (router_005_src_endofpacket), // .endofpacket
.sink_valid (router_005_src_valid), // .valid
.src0_ready (rsp_demux_004_src0_ready), // src0.ready
.src0_valid (rsp_demux_004_src0_valid), // .valid
.src0_data (rsp_demux_004_src0_data), // .data
.src0_channel (rsp_demux_004_src0_channel), // .channel
.src0_startofpacket (rsp_demux_004_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_004_src0_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_clk_mm_interconnect_0_rsp_demux rsp_demux_005 (
.clk (clk_clk_clk), // clk.clk
.reset (ctrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_006_src_ready), // sink.ready
.sink_channel (router_006_src_channel), // .channel
.sink_data (router_006_src_data), // .data
.sink_startofpacket (router_006_src_startofpacket), // .startofpacket
.sink_endofpacket (router_006_src_endofpacket), // .endofpacket
.sink_valid (router_006_src_valid), // .valid
.src0_ready (rsp_demux_005_src0_ready), // src0.ready
.src0_valid (rsp_demux_005_src0_valid), // .valid
.src0_data (rsp_demux_005_src0_data), // .data
.src0_channel (rsp_demux_005_src0_channel), // .channel
.src0_startofpacket (rsp_demux_005_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_005_src0_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_clk_mm_interconnect_0_rsp_mux rsp_mux (
.clk (clk_clk_clk), // clk.clk
.reset (ctrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_src_ready), // src.ready
.src_valid (rsp_mux_src_valid), // .valid
.src_data (rsp_mux_src_data), // .data
.src_channel (rsp_mux_src_channel), // .channel
.src_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_src0_ready), // sink0.ready
.sink0_valid (rsp_demux_src0_valid), // .valid
.sink0_channel (rsp_demux_src0_channel), // .channel
.sink0_data (rsp_demux_src0_data), // .data
.sink0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_src0_endofpacket), // .endofpacket
.sink1_ready (rsp_demux_001_src0_ready), // sink1.ready
.sink1_valid (rsp_demux_001_src0_valid), // .valid
.sink1_channel (rsp_demux_001_src0_channel), // .channel
.sink1_data (rsp_demux_001_src0_data), // .data
.sink1_startofpacket (rsp_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (rsp_demux_001_src0_endofpacket), // .endofpacket
.sink2_ready (crosser_001_out_ready), // sink2.ready
.sink2_valid (crosser_001_out_valid), // .valid
.sink2_channel (crosser_001_out_channel), // .channel
.sink2_data (crosser_001_out_data), // .data
.sink2_startofpacket (crosser_001_out_startofpacket), // .startofpacket
.sink2_endofpacket (crosser_001_out_endofpacket), // .endofpacket
.sink3_ready (rsp_demux_003_src0_ready), // sink3.ready
.sink3_valid (rsp_demux_003_src0_valid), // .valid
.sink3_channel (rsp_demux_003_src0_channel), // .channel
.sink3_data (rsp_demux_003_src0_data), // .data
.sink3_startofpacket (rsp_demux_003_src0_startofpacket), // .startofpacket
.sink3_endofpacket (rsp_demux_003_src0_endofpacket), // .endofpacket
.sink4_ready (rsp_demux_004_src0_ready), // sink4.ready
.sink4_valid (rsp_demux_004_src0_valid), // .valid
.sink4_channel (rsp_demux_004_src0_channel), // .channel
.sink4_data (rsp_demux_004_src0_data), // .data
.sink4_startofpacket (rsp_demux_004_src0_startofpacket), // .startofpacket
.sink4_endofpacket (rsp_demux_004_src0_endofpacket), // .endofpacket
.sink5_ready (rsp_demux_005_src0_ready), // sink5.ready
.sink5_valid (rsp_demux_005_src0_valid), // .valid
.sink5_channel (rsp_demux_005_src0_channel), // .channel
.sink5_data (rsp_demux_005_src0_data), // .data
.sink5_startofpacket (rsp_demux_005_src0_startofpacket), // .startofpacket
.sink5_endofpacket (rsp_demux_005_src0_endofpacket) // .endofpacket
);
altera_avalon_st_handshake_clock_crosser #(
.DATA_WIDTH (85),
.BITS_PER_SYMBOL (85),
.USE_PACKETS (1),
.USE_CHANNEL (1),
.CHANNEL_WIDTH (6),
.USE_ERROR (0),
.ERROR_WIDTH (1),
.VALID_SYNC_DEPTH (2),
.READY_SYNC_DEPTH (2),
.USE_OUTPUT_PIPELINE (0)
) crosser (
.in_clk (clk_clk_clk), // in_clk.clk
.in_reset (ctrl_reset_reset_bridge_in_reset_reset), // in_clk_reset.reset
.out_clk (global_routing_kernel_clk_global_clk_clk), // out_clk.clk
.out_reset (counter_clk_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset
.in_ready (cmd_demux_src2_ready), // in.ready
.in_valid (cmd_demux_src2_valid), // .valid
.in_startofpacket (cmd_demux_src2_startofpacket), // .startofpacket
.in_endofpacket (cmd_demux_src2_endofpacket), // .endofpacket
.in_channel (cmd_demux_src2_channel), // .channel
.in_data (cmd_demux_src2_data), // .data
.out_ready (crosser_out_ready), // out.ready
.out_valid (crosser_out_valid), // .valid
.out_startofpacket (crosser_out_startofpacket), // .startofpacket
.out_endofpacket (crosser_out_endofpacket), // .endofpacket
.out_channel (crosser_out_channel), // .channel
.out_data (crosser_out_data), // .data
.in_empty (1'b0), // (terminated)
.in_error (1'b0), // (terminated)
.out_empty (), // (terminated)
.out_error () // (terminated)
);
altera_avalon_st_handshake_clock_crosser #(
.DATA_WIDTH (85),
.BITS_PER_SYMBOL (85),
.USE_PACKETS (1),
.USE_CHANNEL (1),
.CHANNEL_WIDTH (6),
.USE_ERROR (0),
.ERROR_WIDTH (1),
.VALID_SYNC_DEPTH (2),
.READY_SYNC_DEPTH (2),
.USE_OUTPUT_PIPELINE (0)
) crosser_001 (
.in_clk (global_routing_kernel_clk_global_clk_clk), // in_clk.clk
.in_reset (counter_clk_reset_reset_bridge_in_reset_reset), // in_clk_reset.reset
.out_clk (clk_clk_clk), // out_clk.clk
.out_reset (ctrl_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset
.in_ready (rsp_demux_002_src0_ready), // in.ready
.in_valid (rsp_demux_002_src0_valid), // .valid
.in_startofpacket (rsp_demux_002_src0_startofpacket), // .startofpacket
.in_endofpacket (rsp_demux_002_src0_endofpacket), // .endofpacket
.in_channel (rsp_demux_002_src0_channel), // .channel
.in_data (rsp_demux_002_src0_data), // .data
.out_ready (crosser_001_out_ready), // out.ready
.out_valid (crosser_001_out_valid), // .valid
.out_startofpacket (crosser_001_out_startofpacket), // .startofpacket
.out_endofpacket (crosser_001_out_endofpacket), // .endofpacket
.out_channel (crosser_001_out_channel), // .channel
.out_data (crosser_001_out_data), // .data
.in_empty (1'b0), // (terminated)
.in_error (1'b0), // (terminated)
.out_empty (), // (terminated)
.out_error () // (terminated)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__BUF_PP_BLACKBOX_V
`define SKY130_FD_SC_HVL__BUF_PP_BLACKBOX_V
/**
* buf: Buffer.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__buf (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__BUF_PP_BLACKBOX_V
|
//------------------------------------------------------------------------------
// File : axi_lite_sm.v
// Author : Xilinx Inc.
// -----------------------------------------------------------------------------
// (c) Copyright 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
// -----------------------------------------------------------------------------
// Description: This module is reponsible for bringing up both the MAC and the
// attached PHY (if any) to enable basic packet transfer in both directions.
// It is intended to be directly usable on a xilinx demo platform to demonstrate
// simple bring up and data transfer. The mac speed is set via inputs (which
// can be connected to dip switches) and the PHY is configured to ONLY advertise the
// specified speed. To maximise compatibility on boards only IEEE registers are used
// and the PHY address can be set via a parameter.
//
//------------------------------------------------------------------------------
`timescale 1 ps/1 ps
module axi_lite_sm #(
parameter MAC_BASE_ADDR = 32'h0
) (
input s_axi_aclk,
input s_axi_resetn,
input [1:0] mac_speed,
input update_speed,
input serial_command,
output serial_response,
input phy_loopback,
output reg [31:0] s_axi_awaddr,
output reg s_axi_awvalid,
input s_axi_awready,
output reg [31:0] s_axi_wdata,
output reg s_axi_wvalid,
input s_axi_wready,
input [1:0] s_axi_bresp,
input s_axi_bvalid,
output reg s_axi_bready,
output reg [31:0] s_axi_araddr,
output reg s_axi_arvalid,
input s_axi_arready,
input [31:0] s_axi_rdata,
input [1:0] s_axi_rresp,
input s_axi_rvalid,
output reg s_axi_rready
);
parameter RUN_HALF_DUPLEX = 0;
// main state machine
parameter STARTUP = 0,
MDIO_RD = 1,
MDIO_POLL_CHECK = 2,
MDIO_1G = 3,
MDIO_10_100 = 4,
MDIO_RESTART = 11,
MDIO_LOOPBACK = 12,
MDIO_STATS = 13,
MDIO_STATS_POLL_CHECK = 14,
UPDATE_SPEED = 15,
RESET_MAC_TX = 16,
RESET_MAC_RX = 17,
CNFG_MDIO = 18,
CNFG_FLOW = 19,
CNFG_LO_ADDR = 20,
CNFG_HI_ADDR = 21,
CNFG_FILTER = 22,
CNFG_HD1 = 23,
CNFG_HD2 = 24,
CHECK_SPEED = 25;
// MDIO State machine
parameter IDLE = 0,
SET_DATA = 1,
INIT = 2,
POLL = 3;
// AXI State Machine
parameter READ = 1,
WRITE = 2,
DONE = 3;
// Management configuration register address (0x500)
parameter CONFIG_MANAGEMENT_ADD = MAC_BASE_ADDR + 18'h500;
// Flow control configuration register address (0x40C)
parameter CONFIG_FLOW_CTRL_ADD = MAC_BASE_ADDR + 18'h40C;
// Receiver configuration register address (0x404)
parameter RECEIVER_ADD = MAC_BASE_ADDR + 18'h404;
// Transmitter configuration register address (0x408)
parameter TRANSMITTER_ADD = MAC_BASE_ADDR + 18'h408;
// Speed configuration register address (0x410)
parameter SPEED_CONFIG_ADD = MAC_BASE_ADDR + 18'h410;
// Unicast Word 0 configuration register address (0x700)
parameter CONFIG_UNI0_CTRL_ADD = MAC_BASE_ADDR + 18'h700;
// Unicast Word 1 configuration register address (0x704)
parameter CONFIG_UNI1_CTRL_ADD = MAC_BASE_ADDR + 18'h704;
// Address Filter configuration register address (0x708)
parameter CONFIG_ADDR_CTRL_ADD = MAC_BASE_ADDR + 18'h708;
// MDIO registers
parameter MDIO_CONTROL = MAC_BASE_ADDR + 18'h504;
parameter MDIO_TX_DATA = MAC_BASE_ADDR + 18'h508;
parameter MDIO_RX_DATA = MAC_BASE_ADDR + 18'h50C;
parameter MDIO_OP_RD = 2'b10;
parameter MDIO_OP_WR = 2'b01;
// PHY Registers
// phy address is actually a 6 bit field but other bits are reserved so simpler to specify as 8 bit
parameter PHY_ADDR = 8'h7;
parameter PHY_CONTROL_REG = 8'h0;
parameter PHY_STATUS_REG = 8'h1;
parameter PHY_ABILITY_REG = 8'h4;
parameter PHY_1000BASET_CONTROL_REG = 8'h9;
//-------------------------------------------------
// Wire/reg declarations
reg [4:0] axi_status; // used to keep track of axi transactions
reg mdio_ready; // captured to acknowledge the end of mdio transactions
reg [31:0] axi_rd_data;
reg [31:0] axi_wr_data;
reg [31:0] mdio_wr_data;
reg [4:0] axi_state; // main state machine to configure example design
reg [1:0] mdio_access_sm; // mdio state machine to handle mdio register config
reg [1:0] axi_access_sm; // axi state machine - handles the 5 channels
reg start_access; // used to kick the axi acees state machine
reg start_mdio; // used to kick the mdio state machine
reg drive_mdio; // selects between mdio fields and direct sm control
reg [1:0] mdio_op;
reg [7:0] mdio_reg_addr;
reg writenread;
reg [17:0] addr;
reg [1:0] speed;
reg update_speed_reg;
reg [20:0] count_shift = {21{1'b1}};
reg [36:0] serial_command_shift;
reg load_data;
reg capture_data;
reg write_access;
reg read_access;
wire s_axi_reset;
assign s_axi_reset = !s_axi_resetn;
always @(posedge s_axi_aclk)
begin
if (s_axi_reset) begin
update_speed_reg <= 0;
end
else begin
update_speed_reg <= update_speed;
end
end
//----------------------------------------------------------------------------
// Management process. This process sets up the configuration by
// turning off flow control, then checks gathered statistics at the
// end of transmission
//----------------------------------------------------------------------------
always @(posedge s_axi_aclk)
begin
if (s_axi_reset) begin
axi_state <= STARTUP;
start_access <= 0;
start_mdio <= 0;
drive_mdio <= 0;
mdio_op <= 0;
mdio_reg_addr <= 0;
writenread <= 0;
addr <= 0;
axi_wr_data <= 0;
speed <= mac_speed;
end
// main state machine is kicking off multi cycle accesses in each state so has to
// stall while they take place
else if (axi_access_sm == IDLE && mdio_access_sm == IDLE && !start_access && !start_mdio) begin
case (axi_state)
STARTUP : begin
// this state will be ran after reset to wait for count_shift
if (count_shift[20] === 1'b0) begin
// set up MDC frequency. Write 2E to Management configuration
// register (Add=340). This will enable MDIO and set MDC to 2.5MHz
// (set CLOCK_DIVIDE value to 50 dec. for 125MHz s_axi_aclk and
// enable mdio)
$display("** Note: Setting MDC Frequency to 2.5MHZ....");
start_access <= 1;
writenread <= 1;
addr <= CONFIG_MANAGEMENT_ADD;
axi_wr_data <= 32'h68;
axi_state <= MDIO_RD;
end
end
MDIO_RD : begin
// read phy status - if response is all ones then do not perform any
// further MDIO accesses
speed <= mac_speed;
$display("** Note: Checking for PHY");
drive_mdio <= 1; // switch axi transactions to use mdio values..
start_mdio <= 1;
writenread <= 0;
mdio_reg_addr <= PHY_STATUS_REG;
mdio_op <= MDIO_OP_RD;
axi_state <= MDIO_POLL_CHECK;
end
MDIO_POLL_CHECK : begin
if (axi_rd_data[16:0] == 17'h1ffff)
// if status is all ones then no PHY exists at this address
// (this is used by the demo_tb to avoid performing lots of phy accesses)
axi_state <= UPDATE_SPEED;
else
axi_state <= MDIO_1G;
end
MDIO_1G : begin
// set 1G advertisement
$display("** Note: Setting PHY 1G advertisement");
start_mdio <= 1;
mdio_reg_addr <= PHY_1000BASET_CONTROL_REG;
mdio_op <= MDIO_OP_WR;
// 0x200 is 1G full duplex, 0x100 is 1G half duplex
// only advertise the mode we want..
if (RUN_HALF_DUPLEX)
axi_wr_data <= {16'h0, 7'h0, speed[1], 8'h0};
else
axi_wr_data <= {16'h0, 6'h0, speed[1], 9'h0};
axi_state <= MDIO_10_100;
end
MDIO_10_100 : begin
// set 10/100 advertisement
$display("** Note: Setting PHY 10/100M advertisement");
start_mdio <= 1;
mdio_reg_addr <= PHY_ABILITY_REG;
mdio_op <= MDIO_OP_WR;
// bit8 : full 100M, bit7 : half 100M, bit6 : full 10M, bit5 : half 10M
// only advertise the mode we want..
if (RUN_HALF_DUPLEX)
axi_wr_data <= {16'h0, 8'h0, !speed[1] & speed[0], 1'b0, !speed[1] & !speed[0], 5'h0};
else
axi_wr_data <= {16'h0, 7'h0, !speed[1] & speed[0], 1'b0, !speed[1] & !speed[0], 6'h0};
axi_state <= MDIO_RESTART;
end
MDIO_RESTART : begin
// set autoneg and reset
// if loopback is selected then do not set autonegotiate and program the required speed directly
// otherwise set autonegotiate
$display("** Note: Applying PHY software reset");
start_mdio <= 1;
mdio_reg_addr <= PHY_CONTROL_REG;
mdio_op <= MDIO_OP_WR;
if (phy_loopback) begin
// bit15: software reset, bit13 : speed LSB, bit 8 : full duplex, bit 6 : speed MSB
axi_wr_data <= {16'h0, 2'b10, !speed[1] & speed[0], 4'h0, 1'b1, 1'b0, speed[1], 6'h0};
axi_state <= MDIO_LOOPBACK;
end
else begin
// bit15: software reset, bit12 : AN enable (set after power up)
axi_wr_data <= {16'h0, 4'h9, 12'h0};
axi_state <= MDIO_STATS;
end
end
MDIO_LOOPBACK : begin
// set phy loopback
$display("** Note: Settling PHY Loopback");
start_mdio <= 1;
mdio_reg_addr <= PHY_CONTROL_REG;
mdio_op <= MDIO_OP_WR;
// bit14: loopback, bit13 : speed LSB, bit 8 : full duplex, bit 6 : speed MSB
axi_wr_data <= {16'h0, 2'b01, !speed[1] & speed[0], 4'h0, 1'b1, 1'b0, speed[1], 6'h0};
axi_state <= UPDATE_SPEED;
end
MDIO_STATS : begin
start_mdio <= 1;
$display("** Note: Wait for Autonegotiation to complete");
mdio_reg_addr <= PHY_STATUS_REG;
mdio_op <= MDIO_OP_RD;
axi_state <= MDIO_STATS_POLL_CHECK;
end
MDIO_STATS_POLL_CHECK : begin
// bit 5 is autoneg complete - assume required speed is selected
if (axi_rd_data[5] === 1'b1 && axi_rd_data[16] === 1'b1)
axi_state <= UPDATE_SPEED;
else
axi_state <= MDIO_STATS;
end
// once here the PHY is ACTIVE - NOTE only IEEE registers are used
// program the MAC to the required speed
UPDATE_SPEED : begin
$display("** Note: Programming MAC speed");
drive_mdio <= 0;
start_access <= 1;
writenread <= 1;
addr <= SPEED_CONFIG_ADD;
// bits 31:30 are used
axi_wr_data <= {speed, 30'h0};
axi_state <= RESET_MAC_RX;
end
// this state will drive the reset to the example design (apart from this block)
// this will be separately captured and synched into the various clock domains
RESET_MAC_RX : begin
$display("** Note: Reseting MAC RX");
start_access <= 1;
writenread <= 1;
addr <= RECEIVER_ADD;
axi_wr_data <= 32'h90000000;
axi_state <= RESET_MAC_TX;
end
// this state will drive the reset to the example design (apart from this block)
// this will be separately captured and synched into the various clock domains
RESET_MAC_TX : begin
$display("** Note: Reseting MAC TX");
start_access <= 1;
writenread <= 1;
addr <= TRANSMITTER_ADD;
axi_wr_data <= 32'h90000000;
axi_state <= CNFG_MDIO;
end
CNFG_MDIO : begin
// set up MDC frequency. Write 2E to Management configuration
// register (Add=340). This will enable MDIO and set MDC to 2.5MHz
// (set CLOCK_DIVIDE value to 50 dec. for 125MHz s_axi_aclk and
// enable mdio)
$display("** Note: Setting MDC Frequency to 2.5MHZ....");
start_access <= 1;
writenread <= 1;
addr <= CONFIG_MANAGEMENT_ADD;
axi_wr_data <= 32'h68;
axi_state <= CNFG_FLOW;
end
CNFG_FLOW : begin
$display("** Note: Disabling Flow control....");
start_access <= 1;
writenread <= 1;
addr <= CONFIG_FLOW_CTRL_ADD;
axi_wr_data <= 32'h0;
axi_state <= CNFG_LO_ADDR;
end
CNFG_LO_ADDR : begin
$display("** Note: Configuring unicast address(low word)....");
start_access <= 1;
writenread <= 1;
addr <= CONFIG_UNI0_CTRL_ADD;
axi_wr_data <= 32'h040302DA;
axi_state <= CNFG_HI_ADDR;
end
CNFG_HI_ADDR : begin
$display("** Note: Configuring unicast address(high word)....");
start_access <= 1;
writenread <= 1;
addr <= CONFIG_UNI1_CTRL_ADD;
axi_wr_data <= 32'h0605;
axi_state <= CNFG_FILTER;
end
CNFG_FILTER : begin
$display("** Note: Setting core to promiscuous mode....");
start_access <= 1;
writenread <= 1;
addr <= CONFIG_ADDR_CTRL_ADD;
axi_wr_data <= 32'h80000000;
if (RUN_HALF_DUPLEX)
axi_state <= CNFG_HD1;
else
axi_state <= CHECK_SPEED;
end
CNFG_HD1 : begin
start_access <= 1;
writenread <= 1;
addr <= RECEIVER_ADD;
axi_wr_data <= 32'h14000000;
axi_state <= CNFG_HD2;
end
CNFG_HD2 : begin
start_access <= 1;
writenread <= 1;
addr <= TRANSMITTER_ADD;
axi_wr_data <= 32'h14000000;
axi_state <= CHECK_SPEED;
end
CHECK_SPEED : begin
if (update_speed_reg) begin
axi_state <= MDIO_RD;
end
else begin
if (capture_data)
axi_wr_data <= serial_command_shift[33:2];
if (write_access || read_access) begin
addr <= serial_command_shift[13:2];
start_access <= 1;
writenread <= write_access;
end
end
end
default : begin
axi_state <= STARTUP;
end
endcase
end
else begin
start_access <= 0;
start_mdio <= 0;
end
end
//------------------------------------------------
// MDIO setup - split from main state machine to make more manageable
always @(posedge s_axi_aclk)
begin
if (s_axi_reset) begin
mdio_access_sm <= IDLE;
end
else if (axi_access_sm == IDLE || axi_access_sm == DONE) begin
case (mdio_access_sm)
IDLE : begin
if (start_mdio) begin
if (mdio_op == MDIO_OP_WR) begin
mdio_access_sm <= SET_DATA;
mdio_wr_data <= axi_wr_data;
end
else begin
mdio_access_sm <= INIT;
mdio_wr_data <= {PHY_ADDR, mdio_reg_addr, mdio_op, 3'h1, 11'h0};
end
end
end
SET_DATA : begin
mdio_access_sm <= INIT;
mdio_wr_data <= {PHY_ADDR, mdio_reg_addr, mdio_op, 3'h1, 11'h0};
end
INIT : begin
mdio_access_sm <= POLL;
end
POLL : begin
if (mdio_ready)
mdio_access_sm <= IDLE;
end
endcase
end
else if (mdio_access_sm == POLL && mdio_ready) begin
mdio_access_sm <= IDLE;
end
end
//-------------------------------------------------------------------------------------------
// processes to generate the axi transactions - only simple reads and write can be generated
always @(posedge s_axi_aclk)
begin
if (s_axi_reset) begin
axi_access_sm <= IDLE;
end
else begin
case (axi_access_sm)
IDLE : begin
if (start_access || start_mdio || mdio_access_sm != IDLE) begin
if (mdio_access_sm == POLL) begin
axi_access_sm <= READ;
end
else if ((start_access && writenread) ||
(mdio_access_sm == SET_DATA || mdio_access_sm == INIT) || start_mdio) begin
axi_access_sm <= WRITE;
end
else begin
axi_access_sm <= READ;
end
end
end
WRITE : begin
// wait in this state until axi_status signals the write is complete
if (axi_status[4:2] == 3'b111)
axi_access_sm <= DONE;
end
READ : begin
// wait in this state until axi_status signals the read is complete
if (axi_status[1:0] == 2'b11)
axi_access_sm <= DONE;
end
DONE : begin
axi_access_sm <= IDLE;
end
endcase
end
end
// need a process per axi interface (i.e 5)
// in each case the interface is driven accordingly and once acknowledged a sticky
// status bit is set and the process waits until the access_sm moves on
// READ ADDR
always @(posedge s_axi_aclk)
begin
if (axi_access_sm == READ) begin
if (!axi_status[0]) begin
if (drive_mdio) begin
s_axi_araddr <= MDIO_RX_DATA;
end
else begin
s_axi_araddr <= addr;
end
s_axi_arvalid <= 1'b1;
if (s_axi_arready === 1'b1 && s_axi_arvalid) begin
axi_status[0] <= 1;
s_axi_araddr <= 0;
s_axi_arvalid <= 0;
end
end
end
else begin
axi_status[0] <= 0;
s_axi_araddr <= 0;
s_axi_arvalid <= 0;
end
end
// READ DATA/RESP
always @(posedge s_axi_aclk)
begin
if (axi_access_sm == READ) begin
if (!axi_status[1]) begin
s_axi_rready <= 1'b1;
if (s_axi_rvalid === 1'b1 && s_axi_rready) begin
axi_status[1] <= 1;
s_axi_rready <= 0;
axi_rd_data <= s_axi_rdata;
if (drive_mdio & s_axi_rdata[16])
mdio_ready <= 1;
end
end
end
else begin
s_axi_rready <= 0;
axi_status[1] <= 0;
if (axi_access_sm == IDLE & (start_access || start_mdio)) begin
mdio_ready <= 0;
axi_rd_data <= 0;
end
end
end
// WRITE ADDR
always @(posedge s_axi_aclk)
begin
if (axi_access_sm == WRITE) begin
if (!axi_status[2]) begin
if (drive_mdio) begin
if (mdio_access_sm == SET_DATA)
s_axi_awaddr <= MDIO_TX_DATA;
else
s_axi_awaddr <= MDIO_CONTROL;
end
else begin
s_axi_awaddr <= addr;
end
s_axi_awvalid <= 1'b1;
if (s_axi_awready === 1'b1 && s_axi_awvalid) begin
axi_status[2] <= 1;
s_axi_awaddr <= 0;
s_axi_awvalid <= 0;
end
end
end
else begin
s_axi_awaddr <= 0;
s_axi_awvalid <= 0;
axi_status[2] <= 0;
end
end
// WRITE DATA
always @(posedge s_axi_aclk)
begin
if (axi_access_sm == WRITE) begin
if (!axi_status[3]) begin
if (drive_mdio) begin
s_axi_wdata <= mdio_wr_data;
end
else begin
s_axi_wdata <= axi_wr_data;
end
s_axi_wvalid <= 1'b1;
if (s_axi_wready === 1'b1 && s_axi_wvalid) begin
axi_status[3] <= 1;
s_axi_wdata <= 0;
s_axi_wvalid <= 0;
end
end
end
else begin
s_axi_wdata <= 0;
s_axi_wvalid <= 0;
axi_status[3] <= 0;
end
end
// WRITE RESP
always @(posedge s_axi_aclk)
begin
if (axi_access_sm == WRITE) begin
if (!axi_status[4]) begin
s_axi_bready <= 1'b1;
if (s_axi_bvalid === 1'b1 && s_axi_bready) begin
axi_status[4] <= 1;
s_axi_bready <= 0;
end
end
end
else begin
s_axi_bready <= 0;
axi_status[4] <= 0;
end
end
//-------------------------------------------------------------------------------------------------------
// to avoid logic being stripped a serial input is included which enables an address/data and control to be setup for
// a user config access..
always @(posedge s_axi_aclk)
begin
if (load_data)
serial_command_shift <= {serial_command_shift[35:33], axi_rd_data, serial_command_shift[0], serial_command};
else
serial_command_shift <= {serial_command_shift[35:0], serial_command};
end
// only deassert serial_response once we reach the state in which we can use the serial_command
assign serial_response = (axi_state == CHECK_SPEED) ? serial_command_shift[35] : 1'b1;
// the serial command is expected to have a start and stop bit - to avoid a counter -
// and a two bit code field in the uppper two bits.
// these decode as follows:
// 00 - read address
// 01 - write address
// 10 - write data
// 11 - read data - slightly more involved - when detected the read data is registered into the shift and passed out
// 11 is used for read data as if the input is tied high the output will simply reflect whatever was
// captured but will not result in any activity
// it is expected that the write data is setup BEFORE the write address
always @(posedge s_axi_aclk)
begin
load_data <= 0;
capture_data <= 0;
write_access <= 0;
read_access <= 0;
if (!serial_command_shift[36] & serial_command_shift[35] & serial_command_shift[0])
if (serial_command_shift[34] & serial_command_shift[33]) // READ DATA
load_data <= 1;
else if (serial_command_shift[34] & !serial_command_shift[33]) // WRITE DATA
capture_data <= 1;
else if (!serial_command_shift[34] & serial_command_shift[33]) // WRITE ADDRESS
write_access <= 1;
else // READ ADDRESS
read_access <= 1;
end
// don't reset this - it will always be updated before it is used..
// it does need an init value (all ones)
always @(posedge s_axi_aclk)
begin
count_shift <= {count_shift[19:0], s_axi_reset};
end
endmodule
|
/* This file is part of JT12.
JT12 program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JT12 program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JT12. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 27-1-2017
*/
// Accumulates an arbitrary number of inputs with saturation
// restart the sum when input "zero" is high
module jt12_single_acc #(parameter
win=14, // input data width
wout=16 // output data width
)(
input clk,
input clk_en /* synthesis direct_enable */,
input [win-1:0] op_result,
input sum_en,
input zero,
output reg [wout-1:0] snd
);
// for full resolution use win=14, wout=16
// for cut down resolution use win=9, wout=12
// wout-win should be > 0
reg signed [wout-1:0] next, acc, current;
reg overflow;
wire [wout-1:0] plus_inf = { 1'b0, {(wout-1){1'b1}} }; // maximum positive value
wire [wout-1:0] minus_inf = { 1'b1, {(wout-1){1'b0}} }; // minimum negative value
always @(*) begin
current = sum_en ? { {(wout-win){op_result[win-1]}}, op_result } : {wout{1'b0}};
next = zero ? current : current + acc;
overflow = !zero &&
(current[wout-1] == acc[wout-1]) &&
(acc[wout-1]!=next[wout-1]);
end
always @(posedge clk) if( clk_en ) begin
acc <= overflow ? (acc[wout-1] ? minus_inf : plus_inf) : next;
if(zero) snd <= acc;
end
endmodule // jt12_single_acc
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NOR4B_BEHAVIORAL_V
`define SKY130_FD_SC_MS__NOR4B_BEHAVIORAL_V
/**
* nor4b: 4-input NOR, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__nor4b (
Y ,
A ,
B ,
C ,
D_N
);
// Module ports
output Y ;
input A ;
input B ;
input C ;
input D_N;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire not0_out ;
wire nor0_out_Y;
// Name Output Other arguments
not not0 (not0_out , D_N );
nor nor0 (nor0_out_Y, A, B, C, not0_out);
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__NOR4B_BEHAVIORAL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__CLKDLYINV5SD2_BLACKBOX_V
`define SKY130_FD_SC_LS__CLKDLYINV5SD2_BLACKBOX_V
/**
* clkdlyinv5sd2: Clock Delay Inverter 5-stage 0.25um length inner
* stage gate.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__clkdlyinv5sd2 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__CLKDLYINV5SD2_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O41A_SYMBOL_V
`define SKY130_FD_SC_HS__O41A_SYMBOL_V
/**
* o41a: 4-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3 | A4) & B1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__o41a (
//# {{data|Data Signals}}
input A1,
input A2,
input A3,
input A4,
input B1,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__O41A_SYMBOL_V
|
`timescale 1ns / 1ps
`include "aDefinitions.v"
////////////////////////////////////////////////////////////////////////////////////
//
// pGB, yet another FPGA fully functional and super fun GB classic clone!
// Copyright (C) 2015-2016 Diego Valverde ([email protected])
//
// This program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public License
// as published by the Free Software Foundation; either version 2
// of the License, or (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
//
////////////////////////////////////////////////////////////////////////////////////
module pGB
(
input wire iClock,
`ifdef VGA_ENABLED
output wire [3:0] oVgaRed,
output wire [3:0] oVgaGreen,
output wire [3:0] oVgaBlue,
output wire oVgaHsync,
output wire oVgaVsync,
`endif
//IO input ports
//ASCII IMAGE BUTTON MATRIX
input wire [5:0] iButtonRegister, //Pressed button
`ifndef XILINX_IP
output wire oFrameBufferWe,
output wire [15:0] oFrameBufferData,
output wire [15:0] oFrameBufferAddr,
`endif
input wire iReset
);
wire [15:0] wdZCPU_2_MMU_Addr, wGPU_2_MCU_Addr;
wire [7:0] wdZCPU_2_MMU_WriteData, wMMU_ReadData;
wire wdZCPU_2_MMU_We, wdZCPU_2_MMU_ReadRequest;
wire[7:0] wGPU_2_MCU_LCDC;
wire[7:0] wGPU_2_MCU_STAT;
wire[7:0] wGPU_2_MCU_SCY;
wire[7:0] wGPU_2_MCU_SCX;
wire[7:0] wGPU_2_MCU_LY;
wire[7:0] wGPU_2_MCU_LYC;
wire[7:0] wGPU_2_MCU_DMA;
wire[7:0] wGPU_2_MCU_BGP;
wire[7:0] wGPU_2_MCU_OBP0;
wire[7:0] wGPU_2_MCU_OBP1;
wire[7:0] wGPU_2_MCU_WY;
wire[7:0] wGPU_2_MCU_WX, wMMU_RegData, wMMU_2_GPU_VmemReadData;
wire[7:0] wButtonRegister;
wire[7:0] wCurrentZ80Insn;
wire[15:0] wGpuAddr;
wire [2:0] wMMU_RegWe;
wire[3:0] wMMU_RegSelect, wMCU_2_TIMER_RegSelect;
wire wGPU_2_MCU_ReadRequest, wMCU_2_TIMER_We;
wire wIOInterruptTrigger, wdZCPU_Eof, wdZCPU_BranchTaken, wDZCPU_2_Timer_IntDetected;
wire [7:0] wInterruptRequest,wInt_2_MMU_InterruptFlag, wInt_2_MMU_IntEnable;
wire wInterrupt0x50;
dzcpu DZCPU
(
.iClock( iClock ),
.iReset( iReset ),
.iMCUData( wMMU_ReadData ),
.oMCUAddr( wdZCPU_2_MMU_Addr ),
.oMCUwe( wdZCPU_2_MMU_We ),
.oMCUData( wdZCPU_2_MMU_WriteData ),
.oMcuReadRequest( wdZCPU_2_MMU_ReadRequest ),
.oCurrentZ80Insn( wCurrentZ80Insn ),
.oEof( wdZCPU_Eof ),
.iInterruptRequests( wInterruptRequest ),
.oInterruptJump( wDZCPU_2_Timer_IntDetected ),
.oBranchTaken( wdZCPU_BranchTaken )
);
interrupt_controller INTERRUPTS
(
.iClock(iClock ),
.iReset( iReset ),
.iMcuWe( wMMU_RegWe[2] ),
.iMcuRegSelect(wMMU_RegSelect ), //control register select comes from cpu
.iMcuWriteData( wMMU_RegData ), //what does the cpu want to write
.oInterruptEnableRegister( wInt_2_MMU_IntEnable ),
.oInterruptFlag( wInt_2_MMU_InterruptFlag),
.iInterruptRequest( {5'b0, wInterrupt0x50, 2'b0} ),
.oInterruptResquestPending( wInterruptRequest )
);
timers TIMERS
(
.iClock( iClock ),
.iReset( iReset ),
.iOpcode( wCurrentZ80Insn ),
.iBranchTaken( wdZCPU_BranchTaken ),
.iEof( wdZCPU_Eof ),
.iMcuWe( wMMU_RegWe[1] ),
.iMcuRegSelect( wMMU_RegSelect ),
.iInterrupt( wDZCPU_2_Timer_IntDetected ),
.iMcuWriteData( wMMU_RegData ),
//output wire oInterrupt0x50
.oInterrupt0x50( wInterrupt0x50 )
);
assign wButtonRegister[7:6] = 2'b0;
//IO unit is in charge of marshalling the GameBoy push butons
io IO
(
.Clock( iClock ),
.Reset( iReset ),
.iP( iButtonRegister ),
.oP( wButtonRegister[5:0] ),
.oIE( wIOInterruptTrigger )
);
mmu MMU
(
.iClock( iClock ),
.iReset( iReset ),
//CPU
.iCpuReadRequest( wdZCPU_2_MMU_ReadRequest ),
.iGpuReadRequest( wGPU_2_MCU_ReadRequest ),
.iCpuAddr( wdZCPU_2_MMU_Addr ),
.iCpuWe( wdZCPU_2_MMU_We ),
.iCpuData( wdZCPU_2_MMU_WriteData ),
.oCpuData( wMMU_ReadData ),
//GPU
.oGpuVmemReadData( wMMU_2_GPU_VmemReadData ),
.iGpuAddr( wGPU_2_MCU_Addr ),
.oRegData( wMMU_RegData ),
.oRegSelect( wMMU_RegSelect ),
.oRegWe( wMMU_RegWe ),
.iGPU_LCDC( wGPU_2_MCU_LCDC ),
.iGPU_STAT( wGPU_2_MCU_STAT ),
.iGPU_SCY( wGPU_2_MCU_SCY ),
.iGPU_SCX( wGPU_2_MCU_SCX ),
.iGPU_LY( wGPU_2_MCU_LY ),
.iGPU_LYC( wGPU_2_MCU_LYC ),
.iGPU_DMA( wGPU_2_MCU_DMA ),
.iGPU_BGP( wGPU_2_MCU_BGP ),
.iGPU_OBP0( wGPU_2_MCU_OBP0 ),
.iGPU_OBP1( wGPU_2_MCU_OBP1 ),
.iGPU_WY( wGPU_2_MCU_WY ),
.iGPU_WX( wGPU_2_MCU_WX ),
.iInterruptEnable( wInt_2_MMU_IntEnable ),
.iInterruptFlag( wInt_2_MMU_InterruptFlag ),
//IO
.iButtonRegister( wButtonRegister )
);
`ifdef VGA_ENABLED
wire [15:0] wFramBufferWriteData, wVgaFBReadData, wVgaFBReadData_Pre, wFrameBufferReadAddress, wFramBufferWriteAddress;
wire [15:0] wVgaRow, wVgaCol;
wire [3:0] wVgaR, wVgaG, wVgaB;
wire [9:0] wVgaFBReadAddr;
wire [1:0] wVgaColor2Bits;
wire wFramBufferWe;
RAM_SINGLE_READ_PORT # ( .DATA_WIDTH(16), .ADDR_WIDTH(10), .MEM_SIZE(8192) ) FBUFFER
(
.Clock( iClock ), //TODO: Should we use graphic clock here?
.iWriteEnable( wFramBufferWe ),
//.iReadAddress0( {3'b0,wFrameBufferReadAddress[15:3]} ), //Divide by 8
.iReadAddress0( wFrameBufferReadAddress ), //Divide by 8
.iWriteAddress( wFramBufferWriteAddress ),
.iDataIn( wFramBufferWriteData ),
.oDataOut0( wVgaFBReadData_Pre )
);
assign wFrameBufferReadAddress = (wVgaRow << 5) + (wVgaCol >> 3);
MUXFULLPARALELL_3SEL_GENERIC # (2) MUX_COLOR (
.Sel( wVgaCol[2:0] ),
.I7( wVgaFBReadData_Pre[1:0]),
.I6( wVgaFBReadData_Pre[3:2]),
.I5( wVgaFBReadData_Pre[5:4]),
.I4( wVgaFBReadData_Pre[7:6]) ,
.I3( wVgaFBReadData_Pre[9:8]),
.I2( wVgaFBReadData_Pre[11:10]),
.I1( wVgaFBReadData_Pre[13:12]),
.I0( wVgaFBReadData_Pre[15:14]) ,
.O( wVgaColor2Bits )
);
wire [3:0] wRed,wGreen,wBlue;
MUXFULLPARALELL_2SEL_GENERIC # (12) MUX_COLOR_OUT (
.Sel( wVgaColor2Bits ),
.I0( {4'b0000, 4'b0000, 4'b0000 } ),
.I1( {4'b1111, 4'b0000, 4'b0000 } ),
.I2( {4'b0000, 4'b1111, 4'b0000 } ),
.I3( {4'b0000, 4'b0000, 4'b1111 }) ,
.O( {wRed,wGreen,wBlue} )
);
assign oVgaRed = ( wVgaRow >= 16'd255 || wVgaCol >= 255 ) ? 4'b0111 : wRed;
assign oVgaGreen = ( wVgaRow >= 16'd255 || wVgaCol >= 255 ) ? 4'b0111 : wGreen;
assign oVgaBlue = ( wVgaRow >= 16'd255 || wVgaCol >= 255 ) ? 4'b0111 : wBlue;
VgaController VGA
(
.Clock(iClock),
.Reset(iReset),
.oVgaVsync( oVgaVsync ),
.oVgaHsync( oVgaHsync ),
/*.oVgaRed( oVgaRed ),
.oVgaGreen( oVgaGreen ),
.oVgaBlue( oVgaBlue ),*/
.oRow( wVgaRow ),
.oCol( wVgaCol )
);
`ifndef XILINX_IP
assign oFrameBufferAddr = wFramBufferWriteAddress;
assign oFrameBufferData = wFramBufferWriteData;
assign oFrameBufferWe = wFramBufferWe;
`endif
`endif
gpu GPU
(
.iClock( iClock ),
.iReset( iReset ),
`ifndef VGA_ENABLED
.oFramBufferWe( oFrameBufferWe ),
.oFramBufferData( oFrameBufferData ),
.oFramBufferAddr( oFrameBufferAddr ),
`else
.oFramBufferWe( wFramBufferWe ),
.oFramBufferData( wFramBufferWriteData ),
.oFramBufferAddr( wFramBufferWriteAddress ),
`endif
.oMcuAddr( wGPU_2_MCU_Addr ),
.oMcuReadRequest( wGPU_2_MCU_ReadRequest ),
.iMcuRegSelect( wMMU_RegSelect),
.iMcuWriteData( wMMU_RegData ),
.iMcuReadData( wMMU_2_GPU_VmemReadData ),
.iMcuWe( wMMU_RegWe[0] ),
.oSTAT( wGPU_2_MCU_STAT ),
.oLCDC( wGPU_2_MCU_LCDC ),
.oSCY( wGPU_2_MCU_SCY ),
.oSCX( wGPU_2_MCU_SCX ),
.oLY( wGPU_2_MCU_LY ),
.oLYC( wGPU_2_MCU_LYC ),
.oDMA( wGPU_2_MCU_DMA ),
.oBGP( wGPU_2_MCU_BGP ),
.oOBP0( wGPU_2_MCU_OBP0 ),
.oOBP1( wGPU_2_MCU_OBP1 ),
.oWY( wGPU_2_MCU_WY ),
.oWX( wGPU_2_MCU_WX )
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__BUFBUF_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__BUFBUF_BEHAVIORAL_PP_V
/**
* bufbuf: Double buffer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__bufbuf (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__BUFBUF_BEHAVIORAL_PP_V
|
// This file has been automatically generated by goFB and should not be edited by hand
// Compiler written by Hammond Pearce and available at github.com/kiwih/goFB
// Verilog support is EXPERIMENTAL ONLY
// This file represents the Basic Function Block for BfbOneWayCtrl
//defines for state names used internally
`define STATE_s_init 0
`define STATE_s_wait 1
`define STATE_s_green 2
`define STATE_s_green_count 3
`define STATE_s_yellow 4
`define STATE_s_yellow_count 5
`define STATE_s_red 6
`define STATE_s_red_count 7
module FB_BfbOneWayCtrl
(
input wire clk,
//input events
input wire Tick_eI,
input wire SpecialInstr_eI,
input wire BeginSeq_eI,
input wire PedStatusChange_eI,
//output events
output wire DoneSeq_eO,
output wire PedGrant_eO,
output wire LightCtrlChange_eO,
//input variables
input wire HoldGreen_I,
input wire PedRequest_I,
input wire PedRunning_I,
//output variables
output reg LightRed_O = 0,
output reg LightYellow_O = 0,
output reg LightGreen_O = 0,
input reset
);
////BEGIN internal copies of I/O
//input events
wire Tick;
assign Tick = Tick_eI;
wire SpecialInstr;
assign SpecialInstr = SpecialInstr_eI;
wire BeginSeq;
assign BeginSeq = BeginSeq_eI;
wire PedStatusChange;
assign PedStatusChange = PedStatusChange_eI;
//output events
reg DoneSeq;
assign DoneSeq_eO = DoneSeq;
reg PedGrant;
assign PedGrant_eO = PedGrant;
reg LightCtrlChange;
assign LightCtrlChange_eO = LightCtrlChange;
//input variables
reg HoldGreen = 0;
reg PedRequest = 0;
reg PedRunning = 0;
//output variables
reg LightRed = 0;
reg LightYellow = 0;
reg LightGreen = 0;
////END internal copies of I/O
////BEGIN internal vars
reg unsigned [31:0] d = 0;
reg unsigned [31:0] greenTicks = 15000000;
reg unsigned [31:0] yellowTicks = 5000000;
reg unsigned [31:0] redTicks = 2000000;
////END internal vars
//BEGIN STATE variables
reg [2:0] state = `STATE_s_init;
reg entered = 1'b0;
//END STATE variables
//BEGIN algorithm triggers
reg s_green_alg0_alg_en = 1'b0;
reg s_green_count_alg0_alg_en = 1'b0;
reg s_yellow_alg0_alg_en = 1'b0;
reg s_yellow_count_alg0_alg_en = 1'b0;
reg s_red_alg0_alg_en = 1'b0;
reg s_red_count_alg0_alg_en = 1'b0;
reg LightsRed_alg_en = 1'b0;
reg LightsYellow_alg_en = 1'b0;
reg LightsGreen_alg_en = 1'b0;
//END algorithm triggers
always@(posedge clk) begin
if(reset) begin
//reset state
state = `STATE_s_init;
//reset I/O registers
DoneSeq = 1'b0;
PedGrant = 1'b0;
LightCtrlChange = 1'b0;
HoldGreen = 0;
PedRequest = 0;
PedRunning = 0;
LightRed = 0;
LightYellow = 0;
LightGreen = 0;
//reset internal vars
d = 0;
greenTicks = 15000000;
yellowTicks = 5000000;
redTicks = 2000000;
end else begin
//BEGIN clear output events
DoneSeq = 1'b0;
PedGrant = 1'b0;
LightCtrlChange = 1'b0;
//END clear output events
//BEGIN update internal inputs on relevant events
if(SpecialInstr) begin
HoldGreen = HoldGreen_I;
end
if(PedStatusChange) begin
PedRequest = PedRequest_I;
PedRunning = PedRunning_I;
end
//END update internal inputs
//BEGIN ecc
entered = 1'b0;
case(state)
`STATE_s_init: begin
if(1) begin
state = `STATE_s_wait;
entered = 1'b1;
end
end
`STATE_s_wait: begin
if(BeginSeq) begin
state = `STATE_s_green;
entered = 1'b1;
end
end
`STATE_s_green: begin
if(1) begin
state = `STATE_s_green_count;
entered = 1'b1;
end
end
`STATE_s_green_count: begin
if(d > greenTicks && HoldGreen == 0 && PedRunning == 0) begin
state = `STATE_s_yellow;
entered = 1'b1;
end else if(Tick) begin
state = `STATE_s_green_count;
entered = 1'b1;
end
end
`STATE_s_yellow: begin
if(1) begin
state = `STATE_s_yellow_count;
entered = 1'b1;
end
end
`STATE_s_yellow_count: begin
if(d > yellowTicks) begin
state = `STATE_s_red;
entered = 1'b1;
end else if(Tick) begin
state = `STATE_s_yellow_count;
entered = 1'b1;
end
end
`STATE_s_red: begin
if(1) begin
state = `STATE_s_red_count;
entered = 1'b1;
end
end
`STATE_s_red_count: begin
if(d > redTicks) begin
state = `STATE_s_wait;
entered = 1'b1;
end else if(Tick) begin
state = `STATE_s_red_count;
entered = 1'b1;
end
end
default: begin
state = 0;
end
endcase
//END ecc
//BEGIN triggers
s_green_alg0_alg_en = 1'b0;
s_green_count_alg0_alg_en = 1'b0;
s_yellow_alg0_alg_en = 1'b0;
s_yellow_count_alg0_alg_en = 1'b0;
s_red_alg0_alg_en = 1'b0;
s_red_count_alg0_alg_en = 1'b0;
LightsRed_alg_en = 1'b0;
LightsYellow_alg_en = 1'b0;
LightsGreen_alg_en = 1'b0;
if(entered) begin
case(state)
`STATE_s_init: begin
end
`STATE_s_wait: begin
LightCtrlChange = 1'b1;
DoneSeq = 1'b1;
LightsRed_alg_en = 1'b1;
end
`STATE_s_green: begin
LightCtrlChange = 1'b1;
PedGrant = 1'b1;
LightsGreen_alg_en = 1'b1;
s_green_alg0_alg_en = 1'b1;
end
`STATE_s_green_count: begin
s_green_count_alg0_alg_en = 1'b1;
end
`STATE_s_yellow: begin
LightCtrlChange = 1'b1;
s_yellow_alg0_alg_en = 1'b1;
LightsYellow_alg_en = 1'b1;
end
`STATE_s_yellow_count: begin
s_yellow_count_alg0_alg_en = 1'b1;
end
`STATE_s_red: begin
LightCtrlChange = 1'b1;
s_red_alg0_alg_en = 1'b1;
LightsRed_alg_en = 1'b1;
end
`STATE_s_red_count: begin
s_red_count_alg0_alg_en = 1'b1;
end
default: begin
end
endcase
end
//END triggers
//BEGIN algorithms
if(s_green_alg0_alg_en) begin
d = 0;
end
if(s_green_count_alg0_alg_en) begin
if (d <= greenTicks) begin
d = d + 1;
end
end
if(s_yellow_alg0_alg_en) begin
d = 0;
end
if(s_yellow_count_alg0_alg_en) begin
d = d + 1;
end
if(s_red_alg0_alg_en) begin
d = 0;
end
if(s_red_count_alg0_alg_en) begin
d = d + 1;
end
if(LightsRed_alg_en) begin
LightRed = 1;
LightYellow = 0;
LightGreen = 0;
end
if(LightsYellow_alg_en) begin
LightRed = 0;
LightYellow = 1;
LightGreen = 0;
end
if(LightsGreen_alg_en) begin
LightRed = 0;
LightYellow = 0;
LightGreen = 1;
end
//END algorithms
//BEGIN update external output variables on relevant events
if(LightCtrlChange) begin
LightRed_O = LightRed;
LightYellow_O = LightYellow;
LightGreen_O = LightGreen;
end
//END update external output variables
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__OR4_PP_SYMBOL_V
`define SKY130_FD_SC_LS__OR4_PP_SYMBOL_V
/**
* or4: 4-input OR.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__or4 (
//# {{data|Data Signals}}
input A ,
input B ,
input C ,
input D ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__OR4_PP_SYMBOL_V
|
module fork_fflop(
input clk,
input reset,
input [7:0] inp,
input inp_Valid,
output inp_Retry,
output [7:0] out_a,
output out_aValid,
input out_aRetry,
output [7:0] out_b,
output out_bValid,
input out_bRetry
);
logic inp_aValid;
logic inp_bValid;
logic inp_aRetry;
logic inp_bRetry;
always_comb begin
inp_bValid = inp_Valid & !inp_aRetry;
inp_aValid = inp_Valid & !inp_bRetry;
end
always_comb begin
inp_Retry = inp_aRetry || inp_bRetry;
end
fflop #(.Size(8)) ff_a (
.clk (clk),
.reset (reset),
.din (inp),
.dinValid (inp_aValid),
.dinRetry (inp_aRetry),
.q (out_a),
.qValid (out_aValid),
.qRetry (out_aRetry)
);
fflop #(.Size(8)) ff_b (
.clk (clk),
.reset (reset),
.din (inp),
.dinValid (inp_bValid),
.dinRetry (inp_bRetry),
.q (out_b),
.qValid (out_bValid),
.qRetry (out_bRetry)
);
endmodule
|
//
// Conformal-LEC Version 16.10-d005 ( 21-Apr-2016 ) ( 64 bit executable )
//
module top ( n0 , n1 , n2 , n3 , n4 , n5 , n6 , n7 , n8 , n9 , n10 , n11 , n12 , n13 , n14 , n15 , n16 , n17 , n18 , n19 , n20 , n21 , n22 , n23 , n24 , n25 , n26 , n27 , n28 , n29 , n30 , n31 , n32 , n33 , n34 , n35 , n36 , n37 , n38 , n39 , n40 , n41 , n42 , n43 , n44 , n45 , n46 , n47 , n48 , n49 , n50 , n51 , n52 , n53 , n54 , n55 , n56 , n57 , n58 , n59 , n60 , n61 , n62 , n63 , n64 , n65 , n66 , n67 , n68 , n69 , n70 , n71 , n72 , n73 , n74 , n75 , n76 , n77 , n78 , n79 , n80 , n81 , n82 , n83 , n84 , n85 , n86 , n87 , n88 , n89 , n90 , n91 , n92 , n93 , n94 , n95 , n96 , n97 , n98 , n99 , n100 , n101 , n102 , n103 , n104 , n105 , n106 , n107 , n108 , n109 , n110 , n111 , n112 , n113 , n114 , n115 , n116 , n117 , n118 , n119 , n120 , n121 , n122 , n123 , n124 , n125 , n126 , n127 , n128 , n129 , n130 , n131 , n132 , n133 , n134 , n135 , n136 , n137 , n138 , n139 , n140 , n141 , n142 , n143 , n144 , n145 , n146 , n147 , n148 , n149 , n150 , n151 , n152 , n153 , n154 , n155 , n156 , n157 , n158 , n159 , n160 , n161 , n162 , n163 , n164 , n165 , n166 , n167 , n168 , n169 , n170 , n171 , n172 , n173 , n174 , n175 , n176 , n177 , n178 , n179 , n180 , n181 , n182 , n183 , n184 , n185 , n186 , n187 , n188 , n189 , n190 , n191 , n192 , n193 , n194 , n195 , n196 , n197 , n198 , n199 , n200 , n201 , n202 , n203 , n204 , n205 , n206 , n207 , n208 , n209 , n210 , n211 , n212 , n213 , n214 , n215 , n216 , n217 , n218 , n219 , n220 , n221 , n222 , n223 , n224 , n225 , n226 , n227 , n228 , n229 , n230 , n231 , n232 , n233 , n234 , n235 , n236 , n237 , n238 , n239 , n240 , n241 , n242 , n243 , n244 , n245 , n246 , n247 , n248 , n249 , n250 , n251 , n252 , n253 , n254 , n255 , n256 , n257 , n258 , n259 , n260 , n261 , n262 , n263 , n264 , n265 , n266 , n267 , n268 , n269 , n270 , n271 , n272 , n273 , n274 , n275 , n276 , n277 , n278 , n279 , n280 , n281 , n282 , n283 , n284 , n285 , n286 , n287 , n288 , n289 , n290 , n291 , n292 , n293 , n294 , n295 , n296 , n297 , n298 , n299 , n300 , n301 , n302 , n303 , n304 , n305 , n306 , n307 , n308 , n309 , n310 , n311 , n312 , n313 , n314 , n315 , n316 , n317 , n318 , n319 , n320 , n321 , n322 , n323 , n324 , n325 , n326 , n327 , n328 , n329 , n330 , n331 , n332 , n333 , n334 , n335 , n336 , n337 , n338 , n339 , n340 , n341 , n342 , n343 , n344 , n345 , n346 , n347 , n348 , n349 , n350 , n351 , n352 , n353 , n354 , n355 , n356 , n357 , n358 , n359 , n360 , n361 , n362 , n363 , n364 , n365 , n366 , n367 , n368 , n369 , n370 , n371 , n372 , n373 , n374 , n375 , n376 , n377 , n378 , n379 , n380 , n381 , n382 , n383 , n384 , n385 , n386 , n387 , n388 , n389 , n390 , n391 , n392 , n393 , n394 , n395 , n396 , n397 , n398 , n399 , n400 , n401 , n402 , n403 , n404 , n405 , n406 , n407 , n408 , n409 , n410 , n411 , n412 , n413 , n414 , n415 , n416 , n417 , n418 , n419 , n420 , n421 , n422 , n423 , n424 , n425 , n426 , n427 , n428 , n429 , n430 , n431 , n432 , n433 , n434 , n435 , n436 , n437 , n438 , n439 , n440 , n441 , n442 , n443 , n444 , n445 , n446 , n447 , n448 , n449 , n450 , n451 , n452 , n453 , n454 , n455 , n456 , n457 , n458 , n459 , n460 , n461 , n462 , n463 , n464 , n465 , n466 , n467 , n468 , n469 , n470 , n471 , n472 , n473 , n474 , n475 , n476 , n477 , n478 , n479 , n480 , n481 , n482 , n483 , n484 , n485 , n486 , n487 , n488 , n489 , n490 , n491 , n492 , n493 , n494 , n495 , n496 , n497 , n498 , n499 , n500 , n501 , n502 , n503 , n504 , n505 , n506 , n507 , n508 , n509 , n510 , n511 , n512 , n513 , n514 , n515 , n516 , n517 , n518 , n519 , n520 , n521 , n522 , n523 , n524 , n525 , n526 , n527 , n528 , n529 , n530 , n531 , n532 , n533 , n534 , n535 , n536 , n537 , n538 , n539 , n540 , n541 , n542 , n543 , n544 , n545 , n546 , n547 , n548 , n549 , n550 , n551 , n552 , n553 , n554 , n555 , n556 , n557 , n558 , n559 , n560 , n561 , n562 , n563 , n564 , n565 , n566 , n567 , n568 , n569 , n570 , n571 , n572 , n573 , n574 , n575 , n576 , n577 , n578 , n579 , n580 , n581 , n582 , n583 , n584 , n585 , n586 , n587 , n588 , n589 , n590 , n591 , n592 , n593 , n594 , n595 , n596 , n597 , n598 , n599 , n600 , n601 , n602 , n603 , n604 , n605 , n606 , n607 , n608 , n609 , n610 , n611 , n612 , n613 , n614 , n615 , n616 , n617 , n618 , n619 , n620 , n621 , n622 , n623 , n624 , n625 , n626 , n627 , n628 , n629 , n630 , n631 , n632 , n633 , n634 , n635 , n636 , n637 , n638 , n639 , n640 , n641 , n642 , n643 , n644 , n645 , n646 , n647 , n648 , n649 , n650 , n651 , n652 , n653 , n654 , n655 , n656 , n657 , n658 , n659 , n660 , n661 , n662 , n663 , n664 , n665 , n666 , n667 , n668 , n669 , n670 , n671 , n672 , n673 , n674 , n675 , n676 , n677 , n678 , n679 , n680 , n681 , n682 , n683 , n684 , n685 , n686 , n687 , n688 , n689 , n690 , n691 , n692 , n693 , n694 , n695 , n696 , n697 , n698 , n699 , n700 , n701 , n702 , n703 , n704 , n705 , n706 , n707 , n708 , n709 , n710 , n711 , n712 , n713 , n714 , n715 , n716 , n717 , n718 , n719 , n720 , n721 , n722 , n723 , n724 , n725 , n726 , n727 , n728 , n729 , n730 , n731 , n732 , n733 , n734 , n735 , n736 , n737 , n738 , n739 , n740 , n741 , n742 , n743 , n744 , n745 , n746 , n747 , n748 , n749 , n750 , n751 , n752 , n753 , n754 , n755 , n756 , n757 , n758 , n759 , n760 , n761 , n762 , n763 , n764 , n765 , n766 , n767 , n768 , n769 , n770 , n771 , n772 , n773 , n774 , n775 , n776 , n777 , n778 , n779 , n780 , n781 , n782 , n783 , n784 , n785 , n786 , n787 , n788 , n789 , n790 , n791 , n792 , n793 , n794 , n795 , n796 , n797 , n798 , n799 , n800 , n801 , n802 , n803 , n804 , n805 , n806 , n807 , n808 , n809 , n810 , n811 , n812 , n813 , n814 , n815 , n816 , n817 , n818 , n819 , n820 , n821 , n822 , n823 , n824 , n825 , n826 , n827 , n828 , n829 , n830 , n831 , n832 , n833 , n834 , n835 , n836 , n837 , n838 , n839 , n840 , n841 , n842 , n843 , n844 , n845 , n846 , n847 , n848 , n849 , n850 , n851 , n852 , n853 , n854 , n855 , n856 , n857 , n858 , n859 , n860 , n861 , n862 , n863 , n864 , n865 , n866 , n867 , n868 , n869 , n870 , n871 , n872 , n873 , n874 , n875 , n876 , n877 , n878 , n879 , n880 , n881 , n882 , n883 , n884 , n885 , n886 , n887 , n888 , n889 , n890 , n891 , n892 , n893 , n894 , n895 , n896 , n897 , n898 , n899 , n900 , n901 , n902 , n903 , n904 , n905 , n906 , n907 , n908 , n909 , n910 , n911 , n912 , n913 , n914 , n915 , n916 , n917 , n918 , n919 , n920 , n921 , n922 , n923 , n924 , n925 , n926 , n927 , n928 , n929 , n930 , n931 , n932 , n933 , n934 , n935 , n936 , n937 , n938 , n939 , n940 , n941 , n942 , n943 , n944 , n945 , n946 , n947 , n948 , n949 , n950 , n951 , n952 , n953 , n954 , n955 , n956 , n957 , n958 , n959 , n960 , n961 , n962 , n963 , n964 , n965 , n966 , n967 , n968 , n969 , n970 , n971 , n972 , n973 , n974 , n975 , n976 , n977 , n978 , n979 , n980 , n981 , n982 , n983 , n984 , n985 , n986 , n987 , n988 , n989 , n990 , n991 , n992 , n993 , n994 , n995 , n996 , n997 , n998 , n999 , n1000 , n1001 , n1002 , n1003 , n1004 , n1005 , n1006 , n1007 , n1008 , n1009 , n1010 , n1011 , n1012 , n1013 , n1014 , n1015 , n1016 , n1017 , n1018 , n1019 , n1020 , n1021 , n1022 , n1023 , n1024 , n1025 , n1026 , n1027 , n1028 , n1029 , n1030 , n1031 , n1032 , n1033 , n1034 , n1035 , n1036 , n1037 , n1038 , n1039 , n1040 , n1041 , n1042 , n1043 , n1044 , n1045 , n1046 , n1047 , n1048 , n1049 , n1050 , n1051 , n1052 , n1053 , n1054 , n1055 , n1056 , n1057 , n1058 , n1059 , n1060 , n1061 , n1062 , n1063 , n1064 , n1065 , n1066 , n1067 , n1068 , n1069 , n1070 , n1071 , n1072 , n1073 , n1074 , n1075 , n1076 , n1077 , n1078 , n1079 , n1080 , n1081 , n1082 , n1083 , n1084 , n1085 , n1086 , n1087 , n1088 , n1089 , n1090 , n1091 , n1092 , n1093 , n1094 , n1095 , n1096 , n1097 , n1098 , n1099 , n1100 , n1101 , n1102 , n1103 , n1104 , n1105 , n1106 , n1107 , n1108 , n1109 , n1110 , n1111 , n1112 , n1113 , n1114 , n1115 , n1116 , n1117 , n1118 , n1119 , n1120 , n1121 , n1122 , n1123 , n1124 , n1125 , n1126 , n1127 , n1128 , n1129 , n1130 , n1131 , n1132 , n1133 , n1134 , n1135 , n1136 , n1137 , n1138 , n1139 , n1140 , n1141 , n1142 , n1143 , n1144 , n1145 , n1146 , n1147 , n1148 , n1149 , n1150 , n1151 , n1152 , n1153 , n1154 , n1155 , n1156 , n1157 , n1158 , n1159 , n1160 , n1161 , n1162 , n1163 , n1164 , n1165 , n1166 , n1167 , n1168 , n1169 , n1170 , n1171 , n1172 , n1173 , n1174 , n1175 , n1176 , n1177 , n1178 , n1179 , n1180 , n1181 , n1182 , n1183 , n1184 , n1185 , n1186 , n1187 , n1188 , n1189 , n1190 , n1191 , n1192 , n1193 , n1194 , n1195 , n1196 , n1197 , n1198 , n1199 , n1200 , n1201 , n1202 , n1203 , n1204 , n1205 , n1206 , n1207 , n1208 , n1209 , n1210 , n1211 , n1212 , n1213 , n1214 , n1215 , n1216 , n1217 , n1218 , n1219 , n1220 , n1221 , n1222 , n1223 , n1224 , n1225 , n1226 , n1227 , n1228 , n1229 , n1230 , n1231 , n1232 , n1233 , n1234 , n1235 , n1236 , n1237 , n1238 , n1239 , n1240 , n1241 , n1242 , n1243 , n1244 , n1245 , n1246 , n1247 , n1248 , n1249 , n1250 , n1251 , n1252 , n1253 , n1254 , n1255 , n1256 , n1257 , n1258 , n1259 , n1260 , n1261 , n1262 , n1263 , n1264 , n1265 , n1266 , n1267 , n1268 , n1269 , n1270 , n1271 , n1272 , n1273 , n1274 , n1275 , n1276 , n1277 , n1278 , n1279 , n1280 , n1281 , n1282 , n1283 , n1284 , n1285 , n1286 , n1287 , n1288 , n1289 , n1290 , n1291 , n1292 , n1293 , n1294 , n1295 , n1296 , n1297 , n1298 , n1299 , n1300 , n1301 , n1302 , n1303 , n1304 , n1305 , n1306 , n1307 , n1308 , n1309 , n1310 , n1311 , n1312 , n1313 , n1314 , n1315 , n1316 , n1317 , n1318 , n1319 , n1320 , n1321 , n1322 , n1323 , n1324 , n1325 , n1326 , n1327 , n1328 , n1329 , n1330 , n1331 , n1332 , n1333 , n1334 , n1335 , n1336 , n1337 , n1338 , n1339 , n1340 , n1341 , n1342 , n1343 , n1344 , n1345 , n1346 , n1347 , n1348 , n1349 , n1350 , n1351 , n1352 , n1353 , n1354 , n1355 , n1356 , n1357 , n1358 , n1359 , n1360 , n1361 , n1362 , n1363 , n1364 , n1365 , n1366 , n1367 , n1368 , n1369 , n1370 , n1371 , n1372 , n1373 , n1374 , n1375 , n1376 , n1377 , n1378 , n1379 , n1380 , n1381 , n1382 , n1383 , n1384 , n1385 , n1386 , n1387 , n1388 , n1389 , n1390 , n1391 , n1392 , n1393 , n1394 , n1395 , n1396 , n1397 , n1398 , n1399 , n1400 , n1401 , n1402 , n1403 , n1404 , n1405 , n1406 , n1407 , n1408 , n1409 , n1410 , n1411 , n1412 , n1413 , n1414 , n1415 , n1416 , n1417 , n1418 , n1419 , n1420 , n1421 , n1422 , n1423 , n1424 , n1425 , n1426 , n1427 , n1428 , n1429 , n1430 , n1431 , n1432 , n1433 , n1434 , n1435 , n1436 , n1437 , n1438 , n1439 , n1440 , n1441 , n1442 , n1443 , n1444 , n1445 , n1446 , n1447 , n1448 , n1449 , n1450 , n1451 , n1452 , n1453 , n1454 , n1455 , n1456 , n1457 , n1458 , n1459 , n1460 , n1461 , n1462 , n1463 , n1464 , n1465 , n1466 , n1467 , n1468 , n1469 , n1470 , n1471 , n1472 , n1473 , n1474 , n1475 , n1476 , n1477 , n1478 , n1479 , n1480 , n1481 , n1482 , n1483 , n1484 , n1485 , n1486 , n1487 , n1488 , n1489 , n1490 , n1491 , n1492 , n1493 , n1494 , n1495 , n1496 , n1497 , n1498 , n1499 , n1500 , n1501 , n1502 , n1503 , n1504 , n1505 , n1506 , n1507 , n1508 , n1509 , n1510 , n1511 , n1512 , n1513 , n1514 , n1515 , n1516 , n1517 , n1518 , n1519 , n1520 , n1521 , n1522 , n1523 , n1524 , n1525 , n1526 , n1527 , n1528 , n1529 , n1530 , n1531 , n1532 , n1533 , n1534 , n1535 , n1536 , n1537 , n1538 , n1539 , n1540 , n1541 , n1542 , n1543 , n1544 , n1545 , n1546 , n1547 , n1548 , n1549 , n1550 , n1551 , n1552 , n1553 , n1554 , n1555 , n1556 , n1557 , n1558 , n1559 , n1560 , n1561 , n1562 , n1563 , n1564 , n1565 , n1566 , n1567 , n1568 , n1569 , n1570 , n1571 , n1572 , n1573 , n1574 , n1575 , n1576 , n1577 , n1578 , n1579 , n1580 , n1581 , n1582 , n1583 , n1584 , n1585 , n1586 , n1587 , n1588 , n1589 , n1590 , n1591 , n1592 , n1593 , n1594 , n1595 , n1596 , n1597 , n1598 , n1599 , n1600 , n1601 , n1602 , n1603 , n1604 , n1605 , n1606 , n1607 , n1608 , n1609 , n1610 , n1611 , n1612 , n1613 , n1614 , n1615 , n1616 , n1617 , n1618 , n1619 , n1620 , n1621 , n1622 , n1623 , n1624 , n1625 , n1626 , n1627 , n1628 , n1629 , n1630 , n1631 , n1632 , n1633 , n1634 , n1635 , n1636 , n1637 , n1638 , n1639 , n1640 , n1641 , n1642 , n1643 , n1644 , n1645 , n1646 , n1647 , n1648 , n1649 , n1650 , n1651 , n1652 , n1653 , n1654 , n1655 , n1656 , n1657 , n1658 , n1659 , n1660 , n1661 , n1662 , n1663 , n1664 , n1665 , n1666 , n1667 , n1668 , n1669 , n1670 , n1671 , n1672 , n1673 , n1674 , n1675 , n1676 , n1677 , n1678 , n1679 , n1680 , n1681 , n1682 , n1683 , n1684 , n1685 , n1686 , n1687 , n1688 , n1689 , n1690 , n1691 , n1692 , n1693 , n1694 , n1695 , n1696 , n1697 , n1698 , n1699 , n1700 , n1701 , n1702 , n1703 , n1704 , n1705 , n1706 , n1707 , n1708 , n1709 , n1710 , n1711 , n1712 , n1713 , n1714 , n1715 , n1716 , n1717 , n1718 , n1719 , n1720 , n1721 , n1722 , n1723 , n1724 , n1725 , n1726 , n1727 , n1728 , n1729 , n1730 , n1731 , n1732 , n1733 , n1734 , n1735 , n1736 , n1737 , n1738 , n1739 , n1740 , n1741 , n1742 , n1743 , n1744 , n1745 , n1746 , n1747 , n1748 , n1749 , n1750 , n1751 , n1752 , n1753 , n1754 , n1755 , n1756 , n1757 , n1758 , n1759 , n1760 , n1761 , n1762 , n1763 , n1764 , n1765 , n1766 , n1767 , n1768 , n1769 , n1770 , n1771 , n1772 , n1773 , n1774 , n1775 , n1776 , n1777 , n1778 , n1779 , n1780 , n1781 , n1782 , n1783 , n1784 , n1785 , n1786 , n1787 , n1788 , n1789 , n1790 , n1791 , n1792 , n1793 , n1794 , n1795 , n1796 , n1797 , n1798 , n1799 , n1800 , n1801 , n1802 , n1803 , n1804 , n1805 , n1806 , n1807 , n1808 , n1809 , n1810 , n1811 , n1812 , n1813 , n1814 , n1815 , n1816 , n1817 , n1818 , n1819 , n1820 , n1821 , n1822 , n1823 , n1824 , n1825 , n1826 , n1827 , n1828 , n1829 , n1830 , n1831 , n1832 , n1833 , n1834 , n1835 , n1836 , n1837 , n1838 , n1839 , n1840 , n1841 , n1842 , n1843 , n1844 , n1845 , n1846 , n1847 , n1848 , n1849 , n1850 , n1851 , n1852 , n1853 , n1854 , n1855 , n1856 , n1857 , n1858 , n1859 , n1860 , n1861 , n1862 , n1863 , n1864 , n1865 , n1866 , n1867 , n1868 , n1869 , n1870 , n1871 , n1872 , n1873 , n1874 , n1875 , n1876 , n1877 , n1878 , n1879 , n1880 , n1881 , n1882 , n1883 , n1884 , n1885 , n1886 , n1887 , n1888 , n1889 , n1890 , n1891 , n1892 , n1893 , n1894 , n1895 , n1896 , n1897 , n1898 , n1899 , n1900 , n1901 , n1902 , n1903 , n1904 , n1905 , n1906 , n1907 , n1908 , n1909 , n1910 , n1911 , n1912 , n1913 , n1914 , n1915 , n1916 , n1917 , n1918 , n1919 , n1920 , n1921 , n1922 , n1923 , n1924 , n1925 , n1926 , n1927 , n1928 , n1929 , n1930 , n1931 , n1932 , n1933 , n1934 , n1935 , n1936 , n1937 , n1938 , n1939 , n1940 , n1941 , n1942 , n1943 , n1944 , n1945 , n1946 , n1947 , n1948 , n1949 , n1950 , n1951 , n1952 , n1953 , n1954 , n1955 , n1956 , n1957 , n1958 , n1959 , n1960 , n1961 , n1962 , n1963 , n1964 , n1965 , n1966 , n1967 , n1968 , n1969 , n1970 , n1971 , n1972 , n1973 , n1974 , n1975 , n1976 , n1977 , n1978 , n1979 , n1980 , n1981 , n1982 , n1983 , n1984 , n1985 , n1986 , n1987 , n1988 , n1989 , n1990 , n1991 , n1992 , n1993 , n1994 , n1995 , n1996 , n1997 , n1998 , n1999 , n2000 , n2001 , n2002 , n2003 , n2004 , n2005 , n2006 , n2007 , n2008 , n2009 , n2010 , n2011 , n2012 , n2013 , n2014 , n2015 , n2016 , n2017 , n2018 , n2019 , n2020 , n2021 , n2022 , n2023 , n2024 , n2025 , n2026 , n2027 , n2028 , n2029 , n2030 , n2031 , n2032 , n2033 , n2034 , n2035 , n2036 , n2037 , n2038 , n2039 , n2040 , n2041 , n2042 , n2043 , n2044 , n2045 , n2046 , n2047 , n2048 , n2049 , n2050 , n2051 , n2052 , n2053 , n2054 , n2055 , n2056 , n2057 , n2058 , n2059 , n2060 , n2061 , n2062 , n2063 , n2064 , n2065 , n2066 , n2067 , n2068 , n2069 , n2070 , n2071 , n2072 , n2073 , n2074 , n2075 , n2076 , n2077 , n2078 , n2079 , n2080 , n2081 , n2082 , n2083 , n2084 , n2085 , n2086 , n2087 , n2088 , n2089 , n2090 , n2091 , n2092 , n2093 , n2094 , n2095 , n2096 , n2097 , n2098 , n2099 , n2100 , n2101 , n2102 , n2103 , n2104 , n2105 , n2106 , n2107 , n2108 , n2109 , n2110 , n2111 , n2112 , n2113 , n2114 , n2115 , n2116 , n2117 , n2118 , n2119 , n2120 , n2121 , n2122 , n2123 , n2124 , n2125 , n2126 , n2127 , n2128 , n2129 , n2130 , n2131 , n2132 , n2133 , n2134 , n2135 , n2136 , n2137 , n2138 , n2139 , n2140 , n2141 , n2142 , n2143 , n2144 , n2145 , n2146 , n2147 , n2148 , n2149 , n2150 , n2151 , n2152 , n2153 , n2154 , n2155 , n2156 , n2157 , n2158 , n2159 , n2160 );
input n0 , n1 , n2 , n3 , n4 , n5 , n6 , n7 , n8 , n9 , n10 , n11 , n12 , n13 , n14 , n15 , n16 , n17 , n18 , n19 , n20 , n21 , n22 , n23 , n24 , n25 , n26 , n27 , n28 , n29 , n30 , n31 , n32 , n33 , n34 , n35 , n36 , n37 , n38 , n39 , n40 , n41 , n42 , n43 , n44 , n45 , n46 , n47 , n48 , n49 , n50 , n51 , n52 , n53 , n54 , n55 , n56 , n57 , n58 , n59 , n60 , n61 , n62 , n63 , n64 , n65 , n66 , n67 , n68 , n69 , n70 , n71 , n72 , n73 , n74 , n75 , n76 , n77 , n78 , n79 , n80 , n81 , n82 , n83 , n84 , n85 , n86 , n87 , n88 , n89 , n90 , n91 , n92 , n93 , n94 , n95 , n96 , n97 , n98 , n99 , n100 , n101 , n102 , n103 , n104 , n105 , n106 , n107 , n108 , n109 , n110 , n111 , n112 , n113 , n114 , n115 , n116 , n117 , n118 , n119 , n120 , n121 , n122 , n123 , n124 , n125 , n126 , n127 , n128 , n129 , n130 , n131 , n132 , n133 , n134 , n135 , n136 , n137 , n138 , n139 , n140 , n141 , n142 , n143 , n144 , n145 , n146 , n147 , n148 , n149 , n150 , n151 , n152 , n153 , n154 , n155 , n156 , n157 , n158 , n159 , n160 , n161 , n162 , n163 , n164 , n165 , n166 , n167 , n168 , n169 , n170 , n171 , n172 , n173 , n174 , n175 , n176 , n177 , n178 , n179 , n180 , n181 , n182 , n183 , n184 , n185 , n186 , n187 , n188 , n189 , n190 , n191 , n192 , n193 , n194 , n195 , n196 , n197 , n198 , n199 , n200 , n201 , n202 , n203 , n204 , n205 , n206 , n207 , n208 , n209 , n210 , n211 , n212 , n213 , n214 , n215 , n216 , n217 , n218 , n219 , n220 , n221 , n222 , n223 , n224 , n225 , n226 , n227 , n228 , n229 , n230 , n231 , n232 , n233 , n234 , n235 , n236 , n237 , n238 , n239 , n240 , n241 , n242 , n243 , n244 , n245 , n246 , n247 , n248 , n249 , n250 , n251 , n252 , n253 , n254 , n255 , n256 , n257 , n258 , n259 , n260 , n261 , n262 , n263 , n264 , n265 , n266 , n267 , n268 , n269 , n270 , n271 , n272 , n273 , n274 , n275 , n276 , n277 , n278 , n279 , n280 , n281 , n282 , n283 , n284 , n285 , n286 , n287 , n288 , n289 , n290 , n291 , n292 , n293 , n294 , n295 , n296 , n297 , n298 , n299 , n300 , n301 , n302 , n303 , n304 , n305 , n306 , n307 , n308 , n309 , n310 , n311 , n312 , n313 , n314 , n315 , n316 , n317 , n318 , n319 , n320 , n321 , n322 , n323 , n324 , n325 , n326 , n327 , n328 , n329 , n330 , n331 , n332 , n333 , n334 , n335 , n336 , n337 , n338 , n339 , n340 , n341 , n342 , n343 , n344 , n345 , n346 , n347 , n348 , n349 , n350 , n351 , n352 , n353 , n354 , n355 , n356 , n357 , n358 , n359 , n360 , n361 , n362 , n363 , n364 , n365 , n366 , n367 , n368 , n369 , n370 , n371 , n372 , n373 , n374 , n375 , n376 , n377 , n378 , n379 , n380 , n381 , n382 , n383 , n384 , n385 , n386 , n387 , n388 , n389 , n390 , n391 , n392 , n393 , n394 , n395 , n396 , n397 , n398 , n399 , n400 , n401 , n402 , n403 , n404 , n405 , n406 , n407 , n408 , n409 , n410 , n411 , n412 , n413 , n414 , n415 , n416 , n417 , n418 , n419 , n420 , n421 , n422 , n423 , n424 , n425 , n426 , n427 , n428 , n429 , n430 , n431 , n432 , n433 , n434 , n435 , n436 , n437 , n438 , n439 , n440 , n441 , n442 , n443 , n444 , n445 , n446 , n447 , n448 , n449 , n450 , n451 , n452 , n453 , n454 , n455 , n456 , n457 , n458 , n459 , n460 , n461 , n462 , n463 , n464 , n465 , n466 , n467 , n468 , n469 , n470 , n471 , n472 , n473 , n474 , n475 , n476 , n477 , n478 , n479 , n480 , n481 , n482 , n483 , n484 , n485 , n486 , n487 , n488 , n489 , n490 , n491 , n492 , n493 , n494 , n495 , n496 , n497 , n498 , n499 , n500 , n501 , n502 , n503 , n504 , n505 , n506 , n507 , n508 , n509 , n510 , n511 , n512 , n513 , n514 , n515 , n516 , n517 , n518 , n519 , n520 , n521 , n522 , n523 , n524 , n525 , n526 , n527 , n528 , n529 , n530 , n531 , n532 , n533 , n534 , n535 , n536 , n537 , n538 , n539 , n540 , n541 , n542 , n543 , n544 , n545 , n546 , n547 , n548 , n549 , n550 , n551 , n552 , n553 , n554 , n555 , n556 , n557 , n558 , n559 , n560 , n561 , n562 , n563 , n564 , n565 , n566 , n567 , n568 , n569 , n570 , n571 , n572 , n573 , n574 , n575 , n576 , n577 , n578 , n579 , n580 , n581 , n582 , n583 , n584 , n585 , n586 , n587 , n588 , n589 , n590 , n591 , n592 , n593 , n594 , n595 , n596 , n597 , n598 , n599 , n600 , n601 , n602 , n603 , n604 , n605 , n606 , n607 , n608 , n609 , n610 , n611 , n612 , n613 , n614 , n615 , n616 , n617 , n618 , n619 , n620 , n621 , n622 , n623 , n624 , n625 , n626 , n627 , n628 , n629 , n630 , n631 , n632 , n633 , n634 , n635 , n636 , n637 , n638 , n639 , n640 , n641 , n642 , n643 , n644 , n645 , n646 , n647 , n648 , n649 , n650 , n651 , n652 , n653 , n654 , n655 , n656 , n657 , n658 , n659 , n660 , n661 , n662 , n663 , n664 , n665 , n666 , n667 , n668 , n669 , n670 , n671 , n672 , n673 , n674 , n675 , n676 , n677 , n678 , n679 , n680 , n681 , n682 , n683 , n684 , n685 , n686 , n687 , n688 , n689 , n690 , n691 , n692 , n693 , n694 , n695 , n696 , n697 , n698 , n699 , n700 , n701 , n702 , n703 , n704 , n705 , n706 , n707 , n708 , n709 , n710 , n711 , n712 , n713 , n714 , n715 , n716 , n717 , n718 , n719 , n720 , n721 , n722 , n723 , n724 , n725 , n726 , n727 , n728 , n729 , n730 , n731 , n732 , n733 , n734 , n735 , n736 , n737 , n738 , n739 , n740 , n741 , n742 , n743 , n744 , n745 , n746 , n747 , n748 , n749 , n750 , n751 , n752 , n753 , n754 , n755 , n756 , n757 , n758 , n759 , n760 , n761 , n762 , n763 , n764 , n765 , n766 , n767 , n768 , n769 , n770 , n771 , n772 , n773 , n774 , n775 , n776 , n777 , n778 , n779 , n780 , n781 , n782 , n783 , n784 , n785 , n786 , n787 , n788 , n789 , n790 , n791 , n792 , n793 , n794 , n795 , n796 , n797 , n798 , n799 , n800 , n801 , n802 , n803 , n804 , n805 , n806 , n807 , n808 , n809 , n810 , n811 , n812 , n813 , n814 , n815 , n816 , n817 , n818 , n819 , n820 , n821 , n822 , n823 , n824 , n825 , n826 , n827 , n828 , n829 , n830 , n831 , n832 , n833 , n834 , n835 , n836 , n837 , n838 , n839 , n840 , n841 , n842 , n843 , n844 , n845 , n846 , n847 , n848 , n849 , n850 , n851 , n852 , n853 , n854 , n855 , n856 , n857 , n858 , n859 , n860 , n861 , n862 , n863 , n864 , n865 , n866 , n867 , n868 , n869 , n870 , n871 , n872 , n873 , n874 , n875 , n876 , n877 , n878 , n879 , n880 , n881 , n882 , n883 , n884 , n885 , n886 , n887 , n888 , n889 , n890 , n891 , n892 , n893 , n894 , n895 , n896 , n897 , n898 , n899 , n900 , n901 , n902 , n903 , n904 , n905 , n906 , n907 , n908 , n909 , n910 , n911 , n912 , n913 , n914 , n915 , n916 , n917 , n918 , n919 , n920 , n921 , n922 , n923 , n924 , n925 , n926 , n927 , n928 , n929 , n930 , n931 , n932 , n933 , n934 , n935 , n936 , n937 , n938 , n939 , n940 , n941 , n942 , n943 , n944 , n945 , n946 , n947 , n948 , n949 , n950 , n951 , n952 , n953 , n954 , n955 , n956 , n957 , n958 , n959 , n960 , n961 , n962 , n963 , n964 , n965 , n966 , n967 , n968 , n969 , n970 , n971 , n972 , n973 , n974 , n975 , n976 , n977 , n978 , n979 , n980 , n981 , n982 , n983 , n984 , n985 , n986 , n987 , n988 , n989 , n990 , n991 , n992 , n993 , n994 , n995 , n996 , n997 , n998 , n999 , n1000 , n1001 , n1002 , n1003 , n1004 , n1005 , n1006 , n1007 , n1008 , n1009 , n1010 , n1011 , n1012 , n1013 , n1014 , n1015 , n1016 , n1017 , n1018 , n1019 , n1020 , n1021 , n1022 , n1023 , n1024 , n1025 , n1026 , n1027 , n1028 , n1029 , n1030 , n1031 , n1032 , n1033 , n1034 , n1035 , n1036 , n1037 , n1038 , n1039 , n1040 , n1041 , n1042 , n1043 , n1044 , n1045 , n1046 , n1047 , n1048 , n1049 , n1050 , n1051 , n1052 , n1053 , n1054 , n1055 , n1056 , n1057 , n1058 , n1059 , n1060 , n1061 , n1062 , n1063 , n1064 , n1065 , n1066 , n1067 , n1068 , n1069 , n1070 , n1071 , n1072 , n1073 , n1074 , n1075 , n1076 , n1077 , n1078 , n1079 , n1080 , n1081 , n1082 , n1083 , n1084 , n1085 , n1086 , n1087 , n1088 , n1089 , n1090 , n1091 , n1092 , n1093 , n1094 , n1095 , n1096 , n1097 , n1098 , n1099 , n1100 , n1101 , n1102 , n1103 , n1104 , n1105 , n1106 , n1107 , n1108 , n1109 , n1110 , n1111 , n1112 , n1113 , n1114 , n1115 , n1116 , n1117 , n1118 , n1119 , n1120 , n1121 , n1122 , n1123 , n1124 , n1125 , n1126 , n1127 , n1128 , n1129 , n1130 , n1131 , n1132 , n1133 , n1134 , n1135 , n1136 , n1137 , n1138 , n1139 , n1140 , n1141 , n1142 , n1143 , n1144 , n1145 , n1146 , n1147 , n1148 , n1149 , n1150 , n1151 , n1152 , n1153 , n1154 , n1155 , n1156 , n1157 , n1158 , n1159 , n1160 , n1161 , n1162 , n1163 , n1164 , n1165 , n1166 , n1167 , n1168 , n1169 , n1170 , n1171 , n1172 , n1173 , n1174 , n1175 , n1176 , n1177 , n1178 , n1179 , n1180 , n1181 , n1182 , n1183 , n1184 , n1185 , n1186 , n1187 , n1188 , n1189 , n1190 , n1191 , n1192 , n1193 , n1194 , n1195 , n1196 , n1197 , n1198 , n1199 , n1200 , n1201 , n1202 , n1203 , n1204 , n1205 , n1206 , n1207 , n1208 , n1209 , n1210 , n1211 , n1212 , n1213 , n1214 , n1215 , n1216 , n1217 , n1218 , n1219 , n1220 , n1221 , n1222 , n1223 , n1224 , n1225 , n1226 , n1227 , n1228 , n1229 , n1230 , n1231 , n1232 , n1233 , n1234 , n1235 , n1236 , n1237 , n1238 , n1239 , n1240 , n1241 , n1242 , n1243 , n1244 , n1245 , n1246 , n1247 , n1248 , n1249 , n1250 , n1251 , n1252 , n1253 , n1254 , n1255 , n1256 , n1257 , n1258 , n1259 , n1260 , n1261 , n1262 , n1263 , n1264 , n1265 , n1266 , n1267 , n1268 , n1269 , n1270 , n1271 , n1272 , n1273 , n1274 , n1275 , n1276 , n1277 , n1278 , n1279 , n1280 , n1281 , n1282 , n1283 , n1284 , n1285 , n1286 , n1287 , n1288 , n1289 , n1290 , n1291 , n1292 , n1293 , n1294 , n1295 , n1296 , n1297 , n1298 , n1299 , n1300 , n1301 , n1302 , n1303 , n1304 , n1305 , n1306 , n1307 , n1308 , n1309 , n1310 , n1311 , n1312 , n1313 , n1314 , n1315 , n1316 , n1317 , n1318 , n1319 , n1320 , n1321 , n1322 , n1323 , n1324 , n1325 , n1326 , n1327 , n1328 , n1329 , n1330 , n1331 , n1332 , n1333 , n1334 , n1335 , n1336 , n1337 , n1338 , n1339 , n1340 , n1341 , n1342 , n1343 , n1344 , n1345 , n1346 , n1347 , n1348 , n1349 , n1350 , n1351 , n1352 , n1353 , n1354 , n1355 , n1356 , n1357 , n1358 , n1359 , n1360 , n1361 , n1362 , n1363 , n1364 , n1365 , n1366 , n1367 , n1368 , n1369 , n1370 , n1371 , n1372 , n1373 , n1374 , n1375 , n1376 , n1377 , n1378 , n1379 , n1380 , n1381 , n1382 , n1383 , n1384 , n1385 , n1386 , n1387 , n1388 , n1389 , n1390 , n1391 , n1392 , n1393 , n1394 , n1395 , n1396 , n1397 , n1398 , n1399 , n1400 , n1401 , n1402 , n1403 , n1404 , n1405 , n1406 , n1407 , n1408 , n1409 , n1410 , n1411 , n1412 , n1413 , n1414 , n1415 , n1416 , n1417 , n1418 , n1419 , n1420 , n1421 , n1422 , n1423 , n1424 , n1425 , n1426 , n1427 , n1428 , n1429 , n1430 , n1431 , n1432 , n1433 , n1434 , n1435 , n1436 , n1437 , n1438 , n1439 , n1440 , n1441 , n1442 , n1443 , n1444 , n1445 , n1446 , n1447 , n1448 , n1449 , n1450 , n1451 , n1452 , n1453 , n1454 , n1455 , n1456 , n1457 , n1458 , n1459 , n1460 , n1461 , n1462 , n1463 , n1464 , n1465 , n1466 , n1467 , n1468 , n1469 , n1470 , n1471 , n1472 , n1473 , n1474 , n1475 , n1476 , n1477 , n1478 , n1479 , n1480 , n1481 , n1482 , n1483 , n1484 , n1485 , n1486 , n1487 , n1488 , n1489 , n1490 , n1491 , n1492 , n1493 , n1494 , n1495 , n1496 , n1497 , n1498 , n1499 , n1500 , n1501 , n1502 , n1503 , n1504 , n1505 , n1506 , n1507 , n1508 , n1509 , n1510 , n1511 , n1512 , n1513 , n1514 , n1515 , n1516 , n1517 , n1518 , n1519 , n1520 , n1521 , n1522 , n1523 , n1524 , n1525 , n1526 , n1527 , n1528 , n1529 , n1530 , n1531 , n1532 , n1533 , n1534 , n1535 , n1536 , n1537 , n1538 , n1539 , n1540 , n1541 , n1542 , n1543 , n1544 , n1545 , n1546 , n1547 , n1548 , n1549 , n1550 , n1551 , n1552 , n1553 , n1554 , n1555 , n1556 , n1557 , n1558 , n1559 , n1560 , n1561 , n1562 , n1563 , n1564 , n1565 , n1566 , n1567 , n1568 , n1569 , n1570 , n1571 , n1572 , n1573 , n1574 , n1575 , n1576 , n1577 , n1578 , n1579 , n1580 , n1581 , n1582 , n1583 , n1584 , n1585 , n1586 , n1587 , n1588 , n1589 , n1590 , n1591 , n1592 , n1593 , n1594 , n1595 , n1596 , n1597 , n1598 , n1599 , n1600 , n1601 , n1602 , n1603 , n1604 , n1605 , n1606 , n1607 , n1608 , n1609 , n1610 , n1611 , n1612 , n1613 , n1614 , n1615 , n1616 , n1617 , n1618 , n1619 , n1620 , n1621 , n1622 , n1623 , n1624 , n1625 , n1626 , n1627 , n1628 , n1629 , n1630 , n1631 , n1632 , n1633 , n1634 , n1635 , n1636 , n1637 , n1638 , n1639 , n1640 , n1641 , n1642 , n1643 , n1644 , n1645 , n1646 , n1647 , n1648 , n1649 , n1650 , n1651 , n1652 , n1653 , n1654 , n1655 , n1656 , n1657 , n1658 , n1659 , n1660 , n1661 , n1662 , n1663 , n1664 , n1665 , n1666 , n1667 , n1668 , n1669 , n1670 , n1671 , n1672 , n1673 , n1674 , n1675 , n1676 , n1677 , n1678 , n1679 , n1680 , n1681 , n1682 , n1683 , n1684 , n1685 , n1686 , n1687 , n1688 , n1689 , n1690 , n1691 , n1692 , n1693 , n1694 , n1695 , n1696 , n1697 , n1698 , n1699 , n1700 , n1701 , n1702 , n1703 , n1704 , n1705 , n1706 , n1707 , n1708 , n1709 , n1710 , n1711 , n1712 , n1713 , n1714 , n1715 , n1716 , n1717 , n1718 , n1719 , n1720 , n1721 , n1722 , n1723 , n1724 , n1725 , n1726 , n1727 , n1728 , n1729 , n1730 , n1731 , n1732 , n1733 , n1734 , n1735 , n1736 , n1737 , n1738 , n1739 , n1740 , n1741 , n1742 , n1743 , n1744 , n1745 , n1746 , n1747 , n1748 , n1749 , n1750 , n1751 , n1752 , n1753 , n1754 , n1755 , n1756 , n1757 , n1758 , n1759 , n1760 , n1761 , n1762 , n1763 , n1764 , n1765 , n1766 , n1767 , n1768 , n1769 , n1770 , n1771 , n1772 , n1773 , n1774 , n1775 , n1776 , n1777 , n1778 , n1779 , n1780 , n1781 , n1782 , n1783 , n1784 , n1785 , n1786 , n1787 , n1788 , n1789 , n1790 , n1791 , n1792 , n1793 , n1794 , n1795 , n1796 , n1797 , n1798 , n1799 , n1800 , n1801 , n1802 , n1803 , n1804 , n1805 , n1806 , n1807 , n1808 , n1809 , n1810 , n1811 , n1812 , n1813 , n1814 , n1815 , n1816 , n1817 , n1818 , n1819 , n1820 , n1821 , n1822 , n1823 , n1824 , n1825 , n1826 , n1827 , n1828 , n1829 , n1830 , n1831 , n1832 , n1833 , n1834 , n1835 , n1836 , n1837 , n1838 , n1839 , n1840 , n1841 , n1842 , n1843 , n1844 , n1845 , n1846 , n1847 , n1848 , n1849 , n1850 , n1851 , n1852 , n1853 , n1854 , n1855 , n1856 , n1857 , n1858 , n1859 , n1860 , n1861 , n1862 , n1863 , n1864 , n1865 , n1866 , n1867 , n1868 , n1869 , n1870 , n1871 , n1872 , n1873 , n1874 , n1875 , n1876 , n1877 , n1878 , n1879 , n1880 , n1881 , n1882 , n1883 , n1884 , n1885 , n1886 , n1887 , n1888 , n1889 , n1890 , n1891 , n1892 , n1893 , n1894 , n1895 , n1896 , n1897 , n1898 , n1899 , n1900 , n1901 , n1902 , n1903 , n1904 , n1905 , n1906 , n1907 , n1908 , n1909 , n1910 , n1911 , n1912 , n1913 , n1914 , n1915 , n1916 , n1917 , n1918 , n1919 , n1920 , n1921 , n1922 , n1923 , n1924 , n1925 , n1926 , n1927 , n1928 , n1929 , n1930 , n1931 , n1932 , n1933 , n1934 , n1935 , n1936 , n1937 , n1938 , n1939 , n1940 , n1941 , n1942 , n1943 , n1944 , n1945 , n1946 , n1947 , n1948 , n1949 , n1950 , n1951 , n1952 , n1953 , n1954 , n1955 , n1956 , n1957 , n1958 , n1959 , n1960 , n1961 , n1962 , n1963 , n1964 , n1965 , n1966 , n1967 , n1968 , n1969 , n1970 , n1971 , n1972 , n1973 , n1974 , n1975 , n1976 , n1977 , n1978 , n1979 , n1980 , n1981 , n1982 , n1983 , n1984 , n1985 , n1986 , n1987 , n1988 , n1989 , n1990 , n1991 , n1992 , n1993 , n1994 , n1995 , n1996 , n1997 , n1998 , n1999 , n2000 , n2001 , n2002 , n2003 , n2004 , n2005 , n2006 , n2007 , n2008 , n2009 , n2010 , n2011 , n2012 , n2013 , n2014 , n2015 , n2016 , n2017 , n2018 , n2019 , n2020 , n2021 , n2022 , n2023 , n2024 , n2025 , n2026 , n2027 , n2028 , n2029 , n2030 , n2031 , n2032 , n2033 , n2034 , n2035 , n2036 , n2037 , n2038 , n2039 , n2040 , n2041 , n2042 , n2043 , n2044 , n2045 , n2046 , n2047 , n2048 , n2049 , n2050 , n2051 , n2052 , n2053 , n2054 , n2055 , n2056 , n2057 , n2058 , n2059 , n2060 , n2061 , n2062 , n2063 , n2064 , n2065 , n2066 , n2067 , n2068 , n2069 , n2070 , n2071 , n2072 , n2073 , n2074 , n2075 , n2076 , n2077 , n2078 , n2079 , n2080 , n2081 , n2082 , n2083 , n2084 , n2085 , n2086 , n2087 , n2088 , n2089 , n2090 , n2091 , n2092 , n2093 , n2094 , n2095 , n2096 , n2097 , n2098 , n2099 , n2100 , n2101 , n2102 , n2103 , n2104 , n2105 , n2106 , n2107 , n2108 , n2109 , n2110 , n2111 , n2112 , n2113 , n2114 , n2115 , n2116 , n2117 , n2118 , n2119 , n2120 , n2121 , n2122 , n2123 , n2124 , n2125 , n2126 , n2127 , n2128 , n2129 , n2130 , n2131 , n2132 , n2133 , n2134 , n2135 , n2136 , n2137 , n2138 , n2139 , n2140 , n2141 , n2142 , n2143 , n2144 , n2145 , n2146 , n2147 , n2148 , n2149 , n2150 ;
output n2151 , n2152 , n2153 , n2154 , n2155 , n2156 , n2157 , n2158 , n2159 , n2160 ;
wire n4322 , n4323 , n4324 , n4325 , n4326 , n4327 , n4328 , n4329 , n4330 ,
n4331 , n4332 , n4333 , n4334 , n4335 , n4336 , n4337 , n4338 , n4339 , n4340 ,
n4341 , n4342 , n4343 , n4344 , n4345 , n4346 , n4347 , n4348 , n4349 , n4350 ,
n4351 , n4352 , n4353 , n4354 , n4355 , n4356 , n4357 , n4358 , n4359 , n4360 ,
n4361 , n4362 , n4363 , n4364 , n4365 , n4366 , n4367 , n4368 , n4369 , n4370 ,
n4371 , n4372 , n4373 , n4374 , n4375 , n4376 , n4377 , n4378 , n4379 , n4380 ,
n4381 , n4382 , n4383 , n4384 , n4385 , n4386 , n4387 , n4388 , n4389 , n4390 ,
n4391 , n4392 , n4393 , n4394 , n4395 , n4396 , n4397 , n4398 , n4399 , n4400 ,
n4401 , n4402 , n4403 , n4404 , n4405 , n4406 , n4407 , n4408 , n4409 , n4410 ,
n4411 , n4412 , n4413 , n4414 , n4415 , n4416 , n4417 , n4418 , n4419 , n4420 ,
n4421 , n4422 , n4423 , n4424 , n4425 , n4426 , n4427 , n4428 , n4429 , n4430 ,
n4431 , n4432 , n4433 , n4434 , n4435 , n4436 , n4437 , n4438 , n4439 , n4440 ,
n4441 , n4442 , n4443 , n4444 , n4445 , n4446 , n4447 , n4448 , n4449 , n4450 ,
n4451 , n4452 , n4453 , n4454 , n4455 , n4456 , n4457 , n4458 , n4459 , n4460 ,
n4461 , n4462 , n4463 , n4464 , n4465 , n4466 , n4467 , n4468 , n4469 , n4470 ,
n4471 , n4472 , n4473 , n4474 , n4475 , n4476 , n4477 , n4478 , n4479 , n4480 ,
n4481 , n4482 , n4483 , n4484 , n4485 , n4486 , n4487 , n4488 , n4489 , n4490 ,
n4491 , n4492 , n4493 , n4494 , n4495 , n4496 , n4497 , n4498 , n4499 , n4500 ,
n4501 , n4502 , n4503 , n4504 , n4505 , n4506 , n4507 , n4508 , n4509 , n4510 ,
n4511 , n4512 , n4513 , n4514 , n4515 , n4516 , n4517 , n4518 , n4519 , n4520 ,
n4521 , n4522 , n4523 , n4524 , n4525 , n4526 , n4527 , n4528 , n4529 , n4530 ,
n4531 , n4532 , n4533 , n4534 , n4535 , n4536 , n4537 , n4538 , n4539 , n4540 ,
n4541 , n4542 , n4543 , n4544 , n4545 , n4546 , n4547 , n4548 , n4549 , n4550 ,
n4551 , n4552 , n4553 , n4554 , n4555 , n4556 , n4557 , n4558 , n4559 , n4560 ,
n4561 , n4562 , n4563 , n4564 , n4565 , n4566 , n4567 , n4568 , n4569 , n4570 ,
n4571 , n4572 , n4573 , n4574 , n4575 , n4576 , n4577 , n4578 , n4579 , n4580 ,
n4581 , n4582 , n4583 , n4584 , n4585 , n4586 , n4587 , n4588 , n4589 , n4590 ,
n4591 , n4592 , n4593 , n4594 , n4595 , n4596 , n4597 , n4598 , n4599 , n4600 ,
n4601 , n4602 , n4603 , n4604 , n4605 , n4606 , n4607 , n4608 , n4609 , n4610 ,
n4611 , n4612 , n4613 , n4614 , n4615 , n4616 , n4617 , n4618 , n4619 , n4620 ,
n4621 , n4622 , n4623 , n4624 , n4625 , n4626 , n4627 , n4628 , n4629 , n4630 ,
n4631 , n4632 , n4633 , n4634 , n4635 , n4636 , n4637 , n4638 , n4639 , n4640 ,
n4641 , n4642 , n4643 , n4644 , n4645 , n4646 , n4647 , n4648 , n4649 , n4650 ,
n4651 , n4652 , n4653 , n4654 , n4655 , n4656 , n4657 , n4658 , n4659 , n4660 ,
n4661 , n4662 , n4663 , n4664 , n4665 , n4666 , n4667 , n4668 , n4669 , n4670 ,
n4671 , n4672 , n4673 , n4674 , n4675 , n4676 , n4677 , n4678 , n4679 , n4680 ,
n4681 , n4682 , n4683 , n4684 , n4685 , n4686 , n4687 , n4688 , n4689 , n4690 ,
n4691 , n4692 , n4693 , n4694 , n4695 , n4696 , n4697 , n4698 , n4699 , n4700 ,
n4701 , n4702 , n4703 , n4704 , n4705 , n4706 , n4707 , n4708 , n4709 , n4710 ,
n4711 , n4712 , n4713 , n4714 , n4715 , n4716 , n4717 , n4718 , n4719 , n4720 ,
n4721 , n4722 , n4723 , n4724 , n4725 , n4726 , n4727 , n4728 , n4729 , n4730 ,
n4731 , n4732 , n4733 , n4734 , n4735 , n4736 , n4737 , n4738 , n4739 , n4740 ,
n4741 , n4742 , n4743 , n4744 , n4745 , n4746 , n4747 , n4748 , n4749 , n4750 ,
n4751 , n4752 , n4753 , n4754 , n4755 , n4756 , n4757 , n4758 , n4759 , n4760 ,
n4761 , n4762 , n4763 , n4764 , n4765 , n4766 , n4767 , n4768 , n4769 , n4770 ,
n4771 , n4772 , n4773 , n4774 , n4775 , n4776 , n4777 , n4778 , n4779 , n4780 ,
n4781 , n4782 , n4783 , n4784 , n4785 , n4786 , n4787 , n4788 , n4789 , n4790 ,
n4791 , n4792 , n4793 , n4794 , n4795 , n4796 , n4797 , n4798 , n4799 , n4800 ,
n4801 , n4802 , n4803 , n4804 , n4805 , n4806 , n4807 , n4808 , n4809 , n4810 ,
n4811 , n4812 , n4813 , n4814 , n4815 , n4816 , n4817 , n4818 , n4819 , n4820 ,
n4821 , n4822 , n4823 , n4824 , n4825 , n4826 , n4827 , n4828 , n4829 , n4830 ,
n4831 , n4832 , n4833 , n4834 , n4835 , n4836 , n4837 , n4838 , n4839 , n4840 ,
n4841 , n4842 , n4843 , n4844 , n4845 , n4846 , n4847 , n4848 , n4849 , n4850 ,
n4851 , n4852 , n4853 , n4854 , n4855 , n4856 , n4857 , n4858 , n4859 , n4860 ,
n4861 , n4862 , n4863 , n4864 , n4865 , n4866 , n4867 , n4868 , n4869 , n4870 ,
n4871 , n4872 , n4873 , n4874 , n4875 , n4876 , n4877 , n4878 , n4879 , n4880 ,
n4881 , n4882 , n4883 , n4884 , n4885 , n4886 , n4887 , n4888 , n4889 , n4890 ,
n4891 , n4892 , n4893 , n4894 , n4895 , n4896 , n4897 , n4898 , n4899 , n4900 ,
n4901 , n4902 , n4903 , n4904 , n4905 , n4906 , n4907 , n4908 , n4909 , n4910 ,
n4911 , n4912 , n4913 , n4914 , n4915 , n4916 , n4917 , n4918 , n4919 , n4920 ,
n4921 , n4922 , n4923 , n4924 , n4925 , n4926 , n4927 , n4928 , n4929 , n4930 ,
n4931 , n4932 , n4933 , n4934 , n4935 , n4936 , n4937 , n4938 , n4939 , n4940 ,
n4941 , n4942 , n4943 , n4944 , n4945 , n4946 , n4947 , n4948 , n4949 , n4950 ,
n4951 , n4952 , n4953 , n4954 , n4955 , n4956 , n4957 , n4958 , n4959 , n4960 ,
n4961 , n4962 , n4963 , n4964 , n4965 , n4966 , n4967 , n4968 , n4969 , n4970 ,
n4971 , n4972 , n4973 , n4974 , n4975 , n4976 , n4977 , n4978 , n4979 , n4980 ,
n4981 , n4982 , n4983 , n4984 , n4985 , n4986 , n4987 , n4988 , n4989 , n4990 ,
n4991 , n4992 , n4993 , n4994 , n4995 , n4996 , n4997 , n4998 , n4999 , n5000 ,
n5001 , n5002 , n5003 , n5004 , n5005 , n5006 , n5007 , n5008 , n5009 , n5010 ,
n5011 , n5012 , n5013 , n5014 , n5015 , n5016 , n5017 , n5018 , n5019 , n5020 ,
n5021 , n5022 , n5023 , n5024 , n5025 , n5026 , n5027 , n5028 , n5029 , n5030 ,
n5031 , n5032 , n5033 , n5034 , n5035 , n5036 , n5037 , n5038 , n5039 , n5040 ,
n5041 , n5042 , n5043 , n5044 , n5045 , n5046 , n5047 , n5048 , n5049 , n5050 ,
n5051 , n5052 , n5053 , n5054 , n5055 , n5056 , n5057 , n5058 , n5059 , n5060 ,
n5061 , n5062 , n5063 , n5064 , n5065 , n5066 , n5067 , n5068 , n5069 , n5070 ,
n5071 , n5072 , n5073 , n5074 , n5075 , n5076 , n5077 , n5078 , n5079 , n5080 ,
n5081 , n5082 , n5083 , n5084 , n5085 , n5086 , n5087 , n5088 , n5089 , n5090 ,
n5091 , n5092 , n5093 , n5094 , n5095 , n5096 , n5097 , n5098 , n5099 , n5100 ,
n5101 , n5102 , n5103 , n5104 , n5105 , n5106 , n5107 , n5108 , n5109 , n5110 ,
n5111 , n5112 , n5113 , n5114 , n5115 , n5116 , n5117 , n5118 , n5119 , n5120 ,
n5121 , n5122 , n5123 , n5124 , n5125 , n5126 , n5127 , n5128 , n5129 , n5130 ,
n5131 , n5132 , n5133 , n5134 , n5135 , n5136 , n5137 , n5138 , n5139 , n5140 ,
n5141 , n5142 , n5143 , n5144 , n5145 , n5146 , n5147 , n5148 , n5149 , n5150 ,
n5151 , n5152 , n5153 , n5154 , n5155 , n5156 , n5157 , n5158 , n5159 , n5160 ,
n5161 , n5162 , n5163 , n5164 , n5165 , n5166 , n5167 , n5168 , n5169 , n5170 ,
n5171 , n5172 , n5173 , n5174 , n5175 , n5176 , n5177 , n5178 , n5179 , n5180 ,
n5181 , n5182 , n5183 , n5184 , n5185 , n5186 , n5187 , n5188 , n5189 , n5190 ,
n5191 , n5192 , n5193 , n5194 , n5195 , n5196 , n5197 , n5198 , n5199 , n5200 ,
n5201 , n5202 , n5203 , n5204 , n5205 , n5206 , n5207 , n5208 , n5209 , n5210 ,
n5211 , n5212 , n5213 , n5214 , n5215 , n5216 , n5217 , n5218 , n5219 , n5220 ,
n5221 , n5222 , n5223 , n5224 , n5225 , n5226 , n5227 , n5228 , n5229 , n5230 ,
n5231 , n5232 , n5233 , n5234 , n5235 , n5236 , n5237 , n5238 , n5239 , n5240 ,
n5241 , n5242 , n5243 , n5244 , n5245 , n5246 , n5247 , n5248 , n5249 , n5250 ,
n5251 , n5252 , n5253 , n5254 , n5255 , n5256 , n5257 , n5258 , n5259 , n5260 ,
n5261 , n5262 , n5263 , n5264 , n5265 , n5266 , n5267 , n5268 , n5269 , n5270 ,
n5271 , n5272 , n5273 , n5274 , n5275 , n5276 , n5277 , n5278 , n5279 , n5280 ,
n5281 , n5282 , n5283 , n5284 , n5285 , n5286 , n5287 , n5288 , n5289 , n5290 ,
n5291 , n5292 , n5293 , n5294 , n5295 , n5296 , n5297 , n5298 , n5299 , n5300 ,
n5301 , n5302 , n5303 , n5304 , n5305 , n5306 , n5307 , n5308 , n5309 , n5310 ,
n5311 , n5312 , n5313 , n5314 , n5315 , n5316 , n5317 , n5318 , n5319 , n5320 ,
n5321 , n5322 , n5323 , n5324 , n5325 , n5326 , n5327 , n5328 , n5329 , n5330 ,
n5331 , n5332 , n5333 , n5334 , n5335 , n5336 , n5337 , n5338 , n5339 , n5340 ,
n5341 , n5342 , n5343 , n5344 , n5345 , n5346 , n5347 , n5348 , n5349 , n5350 ,
n5351 , n5352 , n5353 , n5354 , n5355 , n5356 , n5357 , n5358 , n5359 , n5360 ,
n5361 , n5362 , n5363 , n5364 , n5365 , n5366 , n5367 , n5368 , n5369 , n5370 ,
n5371 , n5372 , n5373 , n5374 , n5375 , n5376 , n5377 , n5378 , n5379 , n5380 ,
n5381 , n5382 , n5383 , n5384 , n5385 , n5386 , n5387 , n5388 , n5389 , n5390 ,
n5391 , n5392 , n5393 , n5394 , n5395 , n5396 , n5397 , n5398 , n5399 , n5400 ,
n5401 , n5402 , n5403 , n5404 , n5405 , n5406 , n5407 , n5408 , n5409 , n5410 ,
n5411 , n5412 , n5413 , n5414 , n5415 , n5416 , n5417 , n5418 , n5419 , n5420 ,
n5421 , n5422 , n5423 , n5424 , n5425 , n5426 , n5427 , n5428 , n5429 , n5430 ,
n5431 , n5432 , n5433 , n5434 , n5435 , n5436 , n5437 , n5438 , n5439 , n5440 ,
n5441 , n5442 , n5443 , n5444 , n5445 , n5446 , n5447 , n5448 , n5449 , n5450 ,
n5451 , n5452 , n5453 , n5454 , n5455 , n5456 , n5457 , n5458 , n5459 , n5460 ,
n5461 , n5462 , n5463 , n5464 , n5465 , n5466 , n5467 , n5468 , n5469 , n5470 ,
n5471 , n5472 , n5473 , n5474 , n5475 , n5476 , n5477 , n5478 , n5479 , n5480 ,
n5481 , n5482 , n5483 , n5484 , n5485 , n5486 , n5487 , n5488 , n5489 , n5490 ,
n5491 , n5492 , n5493 , n5494 , n5495 , n5496 , n5497 , n5498 , n5499 , n5500 ,
n5501 , n5502 , n5503 , n5504 , n5505 , n5506 , n5507 , n5508 , n5509 , n5510 ,
n5511 , n5512 , n5513 , n5514 , n5515 , n5516 , n5517 , n5518 , n5519 , n5520 ,
n5521 , n5522 , n5523 , n5524 , n5525 , n5526 , n5527 , n5528 , n5529 , n5530 ,
n5531 , n5532 , n5533 , n5534 , n5535 , n5536 , n5537 , n5538 , n5539 , n5540 ,
n5541 , n5542 , n5543 , n5544 , n5545 , n5546 , n5547 , n5548 , n5549 , n5550 ,
n5551 , n5552 , n5553 , n5554 , n5555 , n5556 , n5557 , n5558 , n5559 , n5560 ,
n5561 , n5562 , n5563 , n5564 , n5565 , n5566 , n5567 , n5568 , n5569 , n5570 ,
n5571 , n5572 , n5573 , n5574 , n5575 , n5576 , n5577 , n5578 , n5579 , n5580 ,
n5581 , n5582 , n5583 , n5584 , n5585 , n5586 , n5587 , n5588 , n5589 , n5590 ,
n5591 , n5592 , n5593 , n5594 , n5595 , n5596 , n5597 , n5598 , n5599 , n5600 ,
n5601 , n5602 , n5603 , n5604 , n5605 , n5606 , n5607 , n5608 , n5609 , n5610 ,
n5611 , n5612 , n5613 , n5614 , n5615 , n5616 , n5617 , n5618 , n5619 , n5620 ,
n5621 , n5622 , n5623 , n5624 , n5625 , n5626 , n5627 , n5628 , n5629 , n5630 ,
n5631 , n5632 , n5633 , n5634 , n5635 , n5636 , n5637 , n5638 , n5639 , n5640 ,
n5641 , n5642 , n5643 , n5644 , n5645 , n5646 , n5647 , n5648 , n5649 , n5650 ,
n5651 , n5652 , n5653 , n5654 , n5655 , n5656 , n5657 , n5658 , n5659 , n5660 ,
n5661 , n5662 , n5663 , n5664 , n5665 , n5666 , n5667 , n5668 , n5669 , n5670 ,
n5671 , n5672 , n5673 , n5674 , n5675 , n5676 , n5677 , n5678 , n5679 , n5680 ,
n5681 , n5682 , n5683 , n5684 , n5685 , n5686 , n5687 , n5688 , n5689 , n5690 ,
n5691 , n5692 , n5693 , n5694 , n5695 , n5696 , n5697 , n5698 , n5699 , n5700 ,
n5701 , n5702 , n5703 , n5704 , n5705 , n5706 , n5707 , n5708 , n5709 , n5710 ,
n5711 , n5712 , n5713 , n5714 , n5715 , n5716 , n5717 , n5718 , n5719 , n5720 ,
n5721 , n5722 , n5723 , n5724 , n5725 , n5726 , n5727 , n5728 , n5729 , n5730 ,
n5731 , n5732 , n5733 , n5734 , n5735 , n5736 , n5737 , n5738 , n5739 , n5740 ,
n5741 , n5742 , n5743 , n5744 , n5745 , n5746 , n5747 , n5748 , n5749 , n5750 ,
n5751 , n5752 , n5753 , n5754 , n5755 , n5756 , n5757 , n5758 , n5759 , n5760 ,
n5761 , n5762 , n5763 , n5764 , n5765 , n5766 , n5767 , n5768 , n5769 , n5770 ,
n5771 , n5772 , n5773 , n5774 , n5775 , n5776 , n5777 , n5778 , n5779 , n5780 ,
n5781 , n5782 , n5783 , n5784 , n5785 , n5786 , n5787 , n5788 , n5789 , n5790 ,
n5791 , n5792 , n5793 , n5794 , n5795 , n5796 , n5797 , n5798 , n5799 , n5800 ,
n5801 , n5802 , n5803 , n5804 , n5805 , n5806 , n5807 , n5808 , n5809 , n5810 ,
n5811 , n5812 , n5813 , n5814 , n5815 , n5816 , n5817 , n5818 , n5819 , n5820 ,
n5821 , n5822 , n5823 , n5824 , n5825 , n5826 , n5827 , n5828 , n5829 , n5830 ,
n5831 , n5832 , n5833 , n5834 , n5835 , n5836 , n5837 , n5838 , n5839 , n5840 ,
n5841 , n5842 , n5843 , n5844 , n5845 , n5846 , n5847 , n5848 , n5849 , n5850 ,
n5851 , n5852 , n5853 , n5854 , n5855 , n5856 , n5857 , n5858 , n5859 , n5860 ,
n5861 , n5862 , n5863 , n5864 , n5865 , n5866 , n5867 , n5868 , n5869 , n5870 ,
n5871 , n5872 , n5873 , n5874 , n5875 , n5876 , n5877 , n5878 , n5879 , n5880 ,
n5881 , n5882 , n5883 , n5884 , n5885 , n5886 , n5887 , n5888 , n5889 , n5890 ,
n5891 , n5892 , n5893 , n5894 , n5895 , n5896 , n5897 , n5898 , n5899 , n5900 ,
n5901 , n5902 , n5903 , n5904 , n5905 , n5906 , n5907 , n5908 , n5909 , n5910 ,
n5911 , n5912 , n5913 , n5914 , n5915 , n5916 , n5917 , n5918 , n5919 , n5920 ,
n5921 , n5922 , n5923 , n5924 , n5925 , n5926 , n5927 , n5928 , n5929 , n5930 ,
n5931 , n5932 , n5933 , n5934 , n5935 , n5936 , n5937 , n5938 , n5939 , n5940 ,
n5941 , n5942 , n5943 , n5944 , n5945 , n5946 , n5947 , n5948 , n5949 , n5950 ,
n5951 , n5952 , n5953 , n5954 , n5955 , n5956 , n5957 , n5958 , n5959 , n5960 ,
n5961 , n5962 , n5963 , n5964 , n5965 , n5966 , n5967 , n5968 , n5969 , n5970 ,
n5971 , n5972 , n5973 , n5974 , n5975 , n5976 , n5977 , n5978 , n5979 , n5980 ,
n5981 , n5982 , n5983 , n5984 , n5985 , n5986 , n5987 , n5988 , n5989 , n5990 ,
n5991 , n5992 , n5993 , n5994 , n5995 , n5996 , n5997 , n5998 , n5999 , n6000 ,
n6001 , n6002 , n6003 , n6004 , n6005 , n6006 , n6007 , n6008 , n6009 , n6010 ,
n6011 , n6012 , n6013 , n6014 , n6015 , n6016 , n6017 , n6018 , n6019 , n6020 ,
n6021 , n6022 , n6023 , n6024 , n6025 , n6026 , n6027 , n6028 , n6029 , n6030 ,
n6031 , n6032 , n6033 , n6034 , n6035 , n6036 , n6037 , n6038 , n6039 , n6040 ,
n6041 , n6042 , n6043 , n6044 , n6045 , n6046 , n6047 , n6048 , n6049 , n6050 ,
n6051 , n6052 , n6053 , n6054 , n6055 , n6056 , n6057 , n6058 , n6059 , n6060 ,
n6061 , n6062 , n6063 , n6064 , n6065 , n6066 , n6067 , n6068 , n6069 , n6070 ,
n6071 , n6072 , n6073 , n6074 , n6075 , n6076 , n6077 , n6078 , n6079 , n6080 ,
n6081 , n6082 , n6083 , n6084 , n6085 , n6086 , n6087 , n6088 , n6089 , n6090 ,
n6091 , n6092 , n6093 , n6094 , n6095 , n6096 , n6097 , n6098 , n6099 , n6100 ,
n6101 , n6102 , n6103 , n6104 , n6105 , n6106 , n6107 , n6108 , n6109 , n6110 ,
n6111 , n6112 , n6113 , n6114 , n6115 , n6116 , n6117 , n6118 , n6119 , n6120 ,
n6121 , n6122 , n6123 , n6124 , n6125 , n6126 , n6127 , n6128 , n6129 , n6130 ,
n6131 , n6132 , n6133 , n6134 , n6135 , n6136 , n6137 , n6138 , n6139 , n6140 ,
n6141 , n6142 , n6143 , n6144 , n6145 , n6146 , n6147 , n6148 , n6149 , n6150 ,
n6151 , n6152 , n6153 , n6154 , n6155 , n6156 , n6157 , n6158 , n6159 , n6160 ,
n6161 , n6162 , n6163 , n6164 , n6165 , n6166 , n6167 , n6168 , n6169 , n6170 ,
n6171 , n6172 , n6173 , n6174 , n6175 , n6176 , n6177 , n6178 , n6179 , n6180 ,
n6181 , n6182 , n6183 , n6184 , n6185 , n6186 , n6187 , n6188 , n6189 , n6190 ,
n6191 , n6192 , n6193 , n6194 , n6195 , n6196 , n6197 , n6198 , n6199 , n6200 ,
n6201 , n6202 , n6203 , n6204 , n6205 , n6206 , n6207 , n6208 , n6209 , n6210 ,
n6211 , n6212 , n6213 , n6214 , n6215 , n6216 , n6217 , n6218 , n6219 , n6220 ,
n6221 , n6222 , n6223 , n6224 , n6225 , n6226 , n6227 , n6228 , n6229 , n6230 ,
n6231 , n6232 , n6233 , n6234 , n6235 , n6236 , n6237 , n6238 , n6239 , n6240 ,
n6241 , n6242 , n6243 , n6244 , n6245 , n6246 , n6247 , n6248 , n6249 , n6250 ,
n6251 , n6252 , n6253 , n6254 , n6255 , n6256 , n6257 , n6258 , n6259 , n6260 ,
n6261 , n6262 , n6263 , n6264 , n6265 , n6266 , n6267 , n6268 , n6269 , n6270 ,
n6271 , n6272 , n6273 , n6274 , n6275 , n6276 , n6277 , n6278 , n6279 , n6280 ,
n6281 , n6282 , n6283 , n6284 , n6285 , n6286 , n6287 , n6288 , n6289 , n6290 ,
n6291 , n6292 , n6293 , n6294 , n6295 , n6296 , n6297 , n6298 , n6299 , n6300 ,
n6301 , n6302 , n6303 , n6304 , n6305 , n6306 , n6307 , n6308 , n6309 , n6310 ,
n6311 , n6312 , n6313 , n6314 , n6315 , n6316 , n6317 , n6318 , n6319 , n6320 ,
n6321 , n6322 , n6323 , n6324 , n6325 , n6326 , n6327 , n6328 , n6329 , n6330 ,
n6331 , n6332 , n6333 , n6334 , n6335 , n6336 , n6337 , n6338 , n6339 , n6340 ,
n6341 , n6342 , n6343 , n6344 , n6345 , n6346 , n6347 , n6348 , n6349 , n6350 ,
n6351 , n6352 , n6353 , n6354 , n6355 , n6356 , n6357 , n6358 , n6359 , n6360 ,
n6361 , n6362 , n6363 , n6364 , n6365 , n6366 , n6367 , n6368 , n6369 , n6370 ,
n6371 , n6372 , n6373 , n6374 , n6375 , n6376 , n6377 , n6378 , n6379 , n6380 ,
n6381 , n6382 , n6383 , n6384 , n6385 , n6386 , n6387 , n6388 , n6389 , n6390 ,
n6391 , n6392 , n6393 , n6394 , n6395 , n6396 , n6397 , n6398 , n6399 , n6400 ,
n6401 , n6402 , n6403 , n6404 , n6405 , n6406 , n6407 , n6408 , n6409 , n6410 ,
n6411 , n6412 , n6413 , n6414 , n6415 , n6416 , n6417 , n6418 , n6419 , n6420 ,
n6421 , n6422 , n6423 , n6424 , n6425 , n6426 , n6427 , n6428 , n6429 , n6430 ,
n6431 , n6432 , n6433 , n6434 , n6435 , n6436 , n6437 , n6438 , n6439 , n6440 ,
n6441 , n6442 , n6443 , n6444 , n6445 , n6446 , n6447 , n6448 , n6449 , n6450 ,
n6451 , n6452 , n6453 , n6454 , n6455 , n6456 , n6457 , n6458 , n6459 , n6460 ,
n6461 , n6462 , n6463 , n6464 , n6465 , n6466 , n6467 , n6468 , n6469 , n6470 ,
n6471 , n6472 , n6473 , n6474 , n6475 , n6476 , n6477 , n6478 , n6479 , n6480 ,
n6481 , n6482 , n6483 , n6484 , n6485 , n6486 , n6487 , n6488 , n6489 , n6490 ,
n6491 , n6492 , n6493 , n6494 , n6495 , n6496 , n6497 , n6498 , n6499 , n6500 ,
n6501 , n6502 , n6503 , n6504 , n6505 , n6506 , n6507 , n6508 , n6509 , n6510 ,
n6511 , n6512 , n6513 , n6514 , n6515 , n6516 , n6517 , n6518 , n6519 , n6520 ,
n6521 , n6522 , n6523 , n6524 , n6525 , n6526 , n6527 , n6528 , n6529 , n6530 ,
n6531 , n6532 , n6533 , n6534 , n6535 , n6536 , n6537 , n6538 , n6539 , n6540 ,
n6541 , n6542 , n6543 , n6544 , n6545 , n6546 , n6547 , n6548 , n6549 , n6550 ,
n6551 , n6552 , n6553 , n6554 , n6555 , n6556 , n6557 , n6558 , n6559 , n6560 ,
n6561 , n6562 , n6563 , n6564 , n6565 , n6566 , n6567 , n6568 , n6569 , n6570 ,
n6571 , n6572 , n6573 , n6574 , n6575 , n6576 , n6577 , n6578 , n6579 , n6580 ,
n6581 , n6582 , n6583 , n6584 , n6585 , n6586 , n6587 , n6588 , n6589 , n6590 ,
n6591 , n6592 , n6593 , n6594 , n6595 , n6596 , n6597 , n6598 , n6599 , n6600 ,
n6601 , n6602 , n6603 , n6604 , n6605 , n6606 , n6607 , n6608 , n6609 , n6610 ,
n6611 , n6612 , n6613 , n6614 , n6615 , n6616 , n6617 , n6618 , n6619 , n6620 ,
n6621 , n6622 , n6623 , n6624 , n6625 , n6626 , n6627 , n6628 , n6629 , n6630 ,
n6631 , n6632 , n6633 , n6634 , n6635 , n6636 , n6637 , n6638 , n6639 , n6640 ,
n6641 , n6642 , n6643 , n6644 , n6645 , n6646 , n6647 , n6648 , n6649 , n6650 ,
n6651 , n6652 , n6653 , n6654 , n6655 , n6656 , n6657 , n6658 , n6659 , n6660 ,
n6661 , n6662 , n6663 , n6664 , n6665 , n6666 , n6667 , n6668 , n6669 , n6670 ,
n6671 , n6672 , n6673 , n6674 , n6675 , n6676 , n6677 , n6678 , n6679 , n6680 ,
n6681 , n6682 , n6683 , n6684 , n6685 , n6686 , n6687 , n6688 , n6689 , n6690 ,
n6691 , n6692 , n6693 , n6694 , n6695 , n6696 , n6697 , n6698 , n6699 , n6700 ,
n6701 , n6702 , n6703 , n6704 , n6705 , n6706 , n6707 , n6708 , n6709 , n6710 ,
n6711 , n6712 , n6713 , n6714 , n6715 , n6716 , n6717 , n6718 , n6719 , n6720 ,
n6721 , n6722 , n6723 , n6724 , n6725 , n6726 , n6727 , n6728 , n6729 , n6730 ,
n6731 , n6732 , n6733 , n6734 , n6735 , n6736 , n6737 , n6738 , n6739 , n6740 ,
n6741 , n6742 , n6743 , n6744 , n6745 , n6746 , n6747 , n6748 , n6749 , n6750 ,
n6751 , n6752 , n6753 , n6754 , n6755 , n6756 , n6757 , n6758 , n6759 , n6760 ,
n6761 , n6762 , n6763 , n6764 , n6765 , n6766 , n6767 , n6768 , n6769 , n6770 ,
n6771 , n6772 , n6773 , n6774 , n6775 , n6776 , n6777 , n6778 , n6779 , n6780 ,
n6781 , n6782 , n6783 , n6784 , n6785 , n6786 , n6787 , n6788 , n6789 , n6790 ,
n6791 , n6792 , n6793 , n6794 , n6795 , n6796 , n6797 , n6798 , n6799 , n6800 ,
n6801 , n6802 , n6803 , n6804 , n6805 , n6806 , n6807 , n6808 , n6809 , n6810 ,
n6811 , n6812 , n6813 , n6814 , n6815 , n6816 , n6817 , n6818 , n6819 , n6820 ,
n6821 , n6822 , n6823 , n6824 , n6825 , n6826 , n6827 , n6828 , n6829 , n6830 ,
n6831 , n6832 , n6833 , n6834 , n6835 , n6836 , n6837 , n6838 , n6839 , n6840 ,
n6841 , n6842 , n6843 , n6844 , n6845 , n6846 , n6847 , n6848 , n6849 , n6850 ,
n6851 , n6852 , n6853 , n6854 , n6855 , n6856 , n6857 , n6858 , n6859 , n6860 ,
n6861 , n6862 , n6863 , n6864 , n6865 , n6866 , n6867 , n6868 , n6869 , n6870 ,
n6871 , n6872 , n6873 , n6874 , n6875 , n6876 , n6877 , n6878 , n6879 , n6880 ,
n6881 , n6882 , n6883 , n6884 , n6885 , n6886 , n6887 , n6888 , n6889 , n6890 ,
n6891 , n6892 , n6893 , n6894 , n6895 , n6896 , n6897 , n6898 , n6899 , n6900 ,
n6901 , n6902 , n6903 , n6904 , n6905 , n6906 , n6907 , n6908 , n6909 , n6910 ,
n6911 , n6912 , n6913 , n6914 , n6915 , n6916 , n6917 , n6918 , n6919 , n6920 ,
n6921 , n6922 , n6923 , n6924 , n6925 , n6926 , n6927 , n6928 , n6929 , n6930 ,
n6931 , n6932 , n6933 , n6934 , n6935 , n6936 , n6937 , n6938 , n6939 , n6940 ,
n6941 , n6942 , n6943 , n6944 , n6945 , n6946 , n6947 , n6948 , n6949 , n6950 ,
n6951 , n6952 , n6953 , n6954 , n6955 , n6956 , n6957 , n6958 , n6959 , n6960 ,
n6961 , n6962 , n6963 , n6964 , n6965 , n6966 , n6967 , n6968 , n6969 , n6970 ,
n6971 , n6972 , n6973 , n6974 , n6975 , n6976 , n6977 , n6978 , n6979 , n6980 ,
n6981 , n6982 , n6983 , n6984 , n6985 , n6986 , n6987 , n6988 , n6989 , n6990 ,
n6991 , n6992 , n6993 , n6994 , n6995 , n6996 , n6997 , n6998 , n6999 , n7000 ,
n7001 , n7002 , n7003 , n7004 , n7005 , n7006 , n7007 , n7008 , n7009 , n7010 ,
n7011 , n7012 , n7013 , n7014 , n7015 , n7016 , n7017 , n7018 , n7019 , n7020 ,
n7021 , n7022 , n7023 , n7024 , n7025 , n7026 , n7027 , n7028 , n7029 , n7030 ,
n7031 , n7032 , n7033 , n7034 , n7035 , n7036 , n7037 , n7038 , n7039 , n7040 ,
n7041 , n7042 , n7043 , n7044 , n7045 , n7046 , n7047 , n7048 , n7049 , n7050 ,
n7051 , n7052 , n7053 , n7054 , n7055 , n7056 , n7057 , n7058 , n7059 , n7060 ,
n7061 , n7062 , n7063 , n7064 , n7065 , n7066 , n7067 , n7068 , n7069 , n7070 ,
n7071 , n7072 , n7073 , n7074 , n7075 , n7076 , n7077 , n7078 , n7079 , n7080 ,
n7081 , n7082 , n7083 , n7084 , n7085 , n7086 , n7087 , n7088 , n7089 , n7090 ,
n7091 , n7092 , n7093 , n7094 , n7095 , n7096 , n7097 , n7098 , n7099 , n7100 ,
n7101 , n7102 , n7103 , n7104 , n7105 , n7106 , n7107 , n7108 , n7109 , n7110 ,
n7111 , n7112 , n7113 , n7114 , n7115 , n7116 , n7117 , n7118 , n7119 , n7120 ,
n7121 , n7122 , n7123 , n7124 , n7125 , n7126 , n7127 , n7128 , n7129 , n7130 ,
n7131 , n7132 , n7133 , n7134 , n7135 , n7136 , n7137 , n7138 , n7139 , n7140 ,
n7141 , n7142 , n7143 , n7144 , n7145 , n7146 , n7147 , n7148 , n7149 , n7150 ,
n7151 , n7152 , n7153 , n7154 , n7155 , n7156 , n7157 , n7158 , n7159 , n7160 ,
n7161 , n7162 , n7163 , n7164 , n7165 , n7166 , n7167 , n7168 , n7169 , n7170 ,
n7171 , n7172 , n7173 , n7174 , n7175 , n7176 , n7177 , n7178 , n7179 , n7180 ,
n7181 , n7182 , n7183 , n7184 , n7185 , n7186 , n7187 , n7188 , n7189 , n7190 ,
n7191 , n7192 , n7193 , n7194 , n7195 , n7196 , n7197 , n7198 , n7199 , n7200 ,
n7201 , n7202 , n7203 , n7204 , n7205 , n7206 , n7207 , n7208 , n7209 , n7210 ,
n7211 , n7212 , n7213 , n7214 , n7215 , n7216 , n7217 , n7218 , n7219 , n7220 ,
n7221 , n7222 , n7223 , n7224 , n7225 , n7226 , n7227 , n7228 , n7229 , n7230 ,
n7231 , n7232 , n7233 , n7234 , n7235 , n7236 , n7237 , n7238 , n7239 , n7240 ,
n7241 , n7242 , n7243 , n7244 , n7245 , n7246 , n7247 , n7248 , n7249 , n7250 ,
n7251 , n7252 , n7253 , n7254 , n7255 , n7256 , n7257 , n7258 , n7259 , n7260 ,
n7261 , n7262 , n7263 , n7264 , n7265 , n7266 , n7267 , n7268 , n7269 , n7270 ,
n7271 , n7272 , n7273 , n7274 , n7275 , n7276 , n7277 , n7278 , n7279 , n7280 ,
n7281 , n7282 , n7283 , n7284 , n7285 , n7286 , n7287 , n7288 , n7289 , n7290 ,
n7291 , n7292 , n7293 , n7294 , n7295 , n7296 , n7297 , n7298 , n7299 , n7300 ,
n7301 , n7302 , n7303 , n7304 , n7305 , n7306 , n7307 , n7308 , n7309 , n7310 ,
n7311 , n7312 , n7313 , n7314 , n7315 , n7316 , n7317 , n7318 , n7319 , n7320 ,
n7321 , n7322 , n7323 , n7324 , n7325 , n7326 , n7327 , n7328 , n7329 , n7330 ,
n7331 , n7332 , n7333 , n7334 , n7335 , n7336 , n7337 , n7338 , n7339 , n7340 ,
n7341 , n7342 , n7343 , n7344 , n7345 , n7346 , n7347 , n7348 , n7349 , n7350 ,
n7351 , n7352 , n7353 , n7354 , n7355 , n7356 , n7357 , n7358 , n7359 , n7360 ,
n7361 , n7362 , n7363 , n7364 , n7365 , n7366 , n7367 , n7368 , n7369 , n7370 ,
n7371 , n7372 , n7373 , n7374 , n7375 , n7376 , n7377 , n7378 , n7379 , n7380 ,
n7381 , n7382 , n7383 , n7384 , n7385 , n7386 , n7387 , n7388 , n7389 , n7390 ,
n7391 , n7392 , n7393 , n7394 , n7395 , n7396 , n7397 , n7398 , n7399 , n7400 ,
n7401 , n7402 , n7403 , n7404 , n7405 , n7406 , n7407 , n7408 , n7409 , n7410 ,
n7411 , n7412 , n7413 , n7414 , n7415 , n7416 , n7417 , n7418 , n7419 , n7420 ,
n7421 , n7422 , n7423 , n7424 , n7425 , n7426 , n7427 , n7428 , n7429 , n7430 ,
n7431 , n7432 , n7433 , n7434 , n7435 , n7436 , n7437 , n7438 , n7439 , n7440 ,
n7441 , n7442 , n7443 , n7444 , n7445 , n7446 , n7447 , n7448 , n7449 , n7450 ,
n7451 , n7452 , n7453 , n7454 , n7455 , n7456 , n7457 , n7458 , n7459 , n7460 ,
n7461 , n7462 , n7463 , n7464 , n7465 , n7466 , n7467 , n7468 , n7469 , n7470 ,
n7471 , n7472 , n7473 , n7474 , n7475 , n7476 , n7477 , n7478 , n7479 , n7480 ,
n7481 , n7482 , n7483 , n7484 , n7485 , n7486 , n7487 , n7488 , n7489 , n7490 ,
n7491 , n7492 , n7493 , n7494 , n7495 , n7496 , n7497 , n7498 , n7499 , n7500 ,
n7501 , n7502 , n7503 , n7504 , n7505 , n7506 , n7507 , n7508 , n7509 , n7510 ,
n7511 , n7512 , n7513 , n7514 , n7515 , n7516 , n7517 , n7518 , n7519 , n7520 ,
n7521 , n7522 , n7523 , n7524 , n7525 , n7526 , n7527 , n7528 , n7529 , n7530 ,
n7531 , n7532 , n7533 , n7534 , n7535 , n7536 , n7537 , n7538 , n7539 , n7540 ,
n7541 , n7542 , n7543 , n7544 , n7545 , n7546 , n7547 , n7548 , n7549 , n7550 ,
n7551 , n7552 , n7553 , n7554 , n7555 , n7556 , n7557 , n7558 , n7559 , n7560 ,
n7561 , n7562 , n7563 , n7564 , n7565 , n7566 , n7567 , n7568 , n7569 , n7570 ,
n7571 , n7572 , n7573 , n7574 , n7575 , n7576 , n7577 , n7578 , n7579 , n7580 ,
n7581 , n7582 , n7583 , n7584 , n7585 , n7586 , n7587 , n7588 , n7589 , n7590 ,
n7591 , n7592 , n7593 , n7594 , n7595 , n7596 , n7597 , n7598 , n7599 , n7600 ,
n7601 , n7602 , n7603 , n7604 , n7605 , n7606 , n7607 , n7608 , n7609 , n7610 ,
n7611 , n7612 , n7613 , n7614 , n7615 , n7616 , n7617 , n7618 , n7619 , n7620 ,
n7621 , n7622 , n7623 , n7624 , n7625 , n7626 , n7627 , n7628 , n7629 , n7630 ,
n7631 , n7632 , n7633 , n7634 , n7635 , n7636 , n7637 , n7638 , n7639 , n7640 ,
n7641 , n7642 , n7643 , n7644 , n7645 , n7646 , n7647 , n7648 , n7649 , n7650 ,
n7651 , n7652 , n7653 , n7654 , n7655 , n7656 , n7657 , n7658 , n7659 , n7660 ,
n7661 , n7662 , n7663 , n7664 , n7665 , n7666 , n7667 , n7668 , n7669 , n7670 ,
n7671 , n7672 , n7673 , n7674 , n7675 , n7676 , n7677 , n7678 , n7679 , n7680 ,
n7681 , n7682 , n7683 , n7684 , n7685 , n7686 , n7687 , n7688 , n7689 , n7690 ,
n7691 , n7692 , n7693 , n7694 , n7695 , n7696 , n7697 , n7698 , n7699 , n7700 ,
n7701 , n7702 , n7703 , n7704 , n7705 , n7706 , n7707 , n7708 , n7709 , n7710 ,
n7711 , n7712 , n7713 , n7714 , n7715 , n7716 , n7717 , n7718 , n7719 , n7720 ,
n7721 , n7722 , n7723 , n7724 , n7725 , n7726 , n7727 , n7728 , n7729 , n7730 ,
n7731 , n7732 , n7733 , n7734 , n7735 , n7736 , n7737 , n7738 , n7739 , n7740 ,
n7741 , n7742 , n7743 , n7744 , n7745 , n7746 , n7747 , n7748 , n7749 , n7750 ,
n7751 , n7752 , n7753 , n7754 , n7755 , n7756 , n7757 , n7758 , n7759 , n7760 ,
n7761 , n7762 , n7763 , n7764 , n7765 , n7766 , n7767 , n7768 , n7769 , n7770 ,
n7771 , n7772 , n7773 , n7774 , n7775 , n7776 , n7777 , n7778 , n7779 , n7780 ,
n7781 , n7782 , n7783 , n7784 , n7785 , n7786 , n7787 , n7788 , n7789 , n7790 ,
n7791 , n7792 , n7793 , n7794 , n7795 , n7796 , n7797 , n7798 , n7799 , n7800 ,
n7801 , n7802 , n7803 , n7804 , n7805 , n7806 , n7807 , n7808 , n7809 , n7810 ,
n7811 , n7812 , n7813 , n7814 , n7815 , n7816 , n7817 , n7818 , n7819 , n7820 ,
n7821 , n7822 , n7823 , n7824 , n7825 , n7826 , n7827 , n7828 , n7829 , n7830 ,
n7831 , n7832 , n7833 , n7834 , n7835 , n7836 , n7837 , n7838 , n7839 , n7840 ,
n7841 , n7842 , n7843 , n7844 , n7845 , n7846 , n7847 , n7848 , n7849 , n7850 ,
n7851 , n7852 , n7853 , n7854 , n7855 , n7856 , n7857 , n7858 , n7859 , n7860 ,
n7861 , n7862 , n7863 , n7864 , n7865 , n7866 , n7867 , n7868 , n7869 , n7870 ,
n7871 , n7872 , n7873 , n7874 , n7875 , n7876 , n7877 , n7878 , n7879 , n7880 ,
n7881 , n7882 , n7883 , n7884 , n7885 , n7886 , n7887 , n7888 , n7889 , n7890 ,
n7891 , n7892 , n7893 , n7894 , n7895 , n7896 , n7897 , n7898 , n7899 , n7900 ,
n7901 , n7902 , n7903 , n7904 , n7905 , n7906 , n7907 , n7908 , n7909 , n7910 ,
n7911 , n7912 , n7913 , n7914 , n7915 , n7916 , n7917 , n7918 , n7919 , n7920 ,
n7921 , n7922 , n7923 , n7924 , n7925 , n7926 , n7927 , n7928 , n7929 , n7930 ,
n7931 , n7932 , n7933 , n7934 , n7935 , n7936 , n7937 , n7938 , n7939 , n7940 ,
n7941 , n7942 , n7943 , n7944 , n7945 , n7946 , n7947 , n7948 , n7949 , n7950 ,
n7951 , n7952 , n7953 , n7954 , n7955 , n7956 , n7957 , n7958 , n7959 , n7960 ,
n7961 , n7962 , n7963 , n7964 , n7965 , n7966 , n7967 , n7968 , n7969 , n7970 ,
n7971 , n7972 , n7973 , n7974 , n7975 , n7976 , n7977 , n7978 , n7979 , n7980 ,
n7981 , n7982 , n7983 , n7984 , n7985 , n7986 , n7987 , n7988 , n7989 , n7990 ,
n7991 , n7992 , n7993 , n7994 , n7995 , n7996 , n7997 , n7998 , n7999 , n8000 ,
n8001 , n8002 , n8003 , n8004 , n8005 , n8006 , n8007 , n8008 , n8009 , n8010 ,
n8011 , n8012 , n8013 , n8014 , n8015 , n8016 , n8017 , n8018 , n8019 , n8020 ,
n8021 , n8022 , n8023 , n8024 , n8025 , n8026 , n8027 , n8028 , n8029 , n8030 ,
n8031 , n8032 , n8033 , n8034 , n8035 , n8036 , n8037 , n8038 , n8039 , n8040 ,
n8041 , n8042 , n8043 , n8044 , n8045 , n8046 , n8047 , n8048 , n8049 , n8050 ,
n8051 , n8052 , n8053 , n8054 , n8055 , n8056 , n8057 , n8058 , n8059 , n8060 ,
n8061 , n8062 , n8063 , n8064 , n8065 , n8066 , n8067 , n8068 , n8069 , n8070 ,
n8071 , n8072 , n8073 , n8074 , n8075 , n8076 , n8077 , n8078 , n8079 , n8080 ,
n8081 , n8082 , n8083 , n8084 , n8085 , n8086 , n8087 , n8088 , n8089 , n8090 ,
n8091 , n8092 , n8093 , n8094 , n8095 , n8096 , n8097 , n8098 , n8099 , n8100 ,
n8101 , n8102 , n8103 , n8104 , n8105 , n8106 , n8107 , n8108 , n8109 , n8110 ,
n8111 , n8112 , n8113 , n8114 , n8115 , n8116 , n8117 , n8118 , n8119 , n8120 ,
n8121 , n8122 , n8123 , n8124 , n8125 , n8126 , n8127 , n8128 , n8129 , n8130 ,
n8131 , n8132 , n8133 , n8134 , n8135 , n8136 , n8137 , n8138 , n8139 , n8140 ,
n8141 , n8142 , n8143 , n8144 , n8145 , n8146 , n8147 , n8148 , n8149 , n8150 ,
n8151 , n8152 , n8153 , n8154 , n8155 , n8156 , n8157 , n8158 , n8159 , n8160 ,
n8161 , n8162 , n8163 , n8164 , n8165 , n8166 , n8167 , n8168 , n8169 , n8170 ,
n8171 , n8172 , n8173 , n8174 , n8175 , n8176 , n8177 , n8178 , n8179 , n8180 ,
n8181 , n8182 , n8183 , n8184 , n8185 , n8186 , n8187 , n8188 , n8189 , n8190 ,
n8191 , n8192 , n8193 , n8194 , n8195 , n8196 , n8197 , n8198 , n8199 , n8200 ,
n8201 , n8202 , n8203 , n8204 , n8205 , n8206 , n8207 , n8208 , n8209 , n8210 ,
n8211 , n8212 , n8213 , n8214 , n8215 , n8216 , n8217 , n8218 , n8219 , n8220 ,
n8221 , n8222 , n8223 , n8224 , n8225 , n8226 , n8227 , n8228 , n8229 , n8230 ,
n8231 , n8232 , n8233 , n8234 , n8235 , n8236 , n8237 , n8238 , n8239 , n8240 ,
n8241 , n8242 , n8243 , n8244 , n8245 , n8246 , n8247 , n8248 , n8249 , n8250 ,
n8251 , n8252 , n8253 , n8254 , n8255 , n8256 , n8257 , n8258 , n8259 , n8260 ,
n8261 , n8262 , n8263 , n8264 , n8265 , n8266 , n8267 , n8268 , n8269 , n8270 ,
n8271 , n8272 , n8273 , n8274 , n8275 , n8276 , n8277 , n8278 , n8279 , n8280 ,
n8281 , n8282 , n8283 , n8284 , n8285 , n8286 , n8287 , n8288 , n8289 , n8290 ,
n8291 , n8292 , n8293 , n8294 , n8295 , n8296 , n8297 , n8298 , n8299 , n8300 ,
n8301 , n8302 , n8303 , n8304 , n8305 , n8306 , n8307 , n8308 , n8309 , n8310 ,
n8311 , n8312 , n8313 , n8314 , n8315 , n8316 , n8317 , n8318 , n8319 , n8320 ,
n8321 , n8322 , n8323 , n8324 , n8325 , n8326 , n8327 , n8328 , n8329 , n8330 ,
n8331 , n8332 , n8333 , n8334 , n8335 , n8336 , n8337 , n8338 , n8339 , n8340 ,
n8341 , n8342 , n8343 , n8344 , n8345 , n8346 , n8347 , n8348 , n8349 , n8350 ,
n8351 , n8352 , n8353 , n8354 , n8355 , n8356 , n8357 , n8358 , n8359 , n8360 ,
n8361 , n8362 , n8363 , n8364 , n8365 , n8366 , n8367 , n8368 , n8369 , n8370 ,
n8371 , n8372 , n8373 , n8374 , n8375 , n8376 , n8377 , n8378 , n8379 , n8380 ,
n8381 , n8382 , n8383 , n8384 , n8385 , n8386 , n8387 , n8388 , n8389 , n8390 ,
n8391 , n8392 , n8393 , n8394 , n8395 , n8396 , n8397 , n8398 , n8399 , n8400 ,
n8401 , n8402 , n8403 , n8404 , n8405 , n8406 , n8407 , n8408 , n8409 , n8410 ,
n8411 , n8412 , n8413 , n8414 , n8415 , n8416 , n8417 , n8418 , n8419 , n8420 ,
n8421 , n8422 , n8423 , n8424 , n8425 , n8426 , n8427 , n8428 , n8429 , n8430 ,
n8431 , n8432 , n8433 , n8434 , n8435 , n8436 , n8437 , n8438 , n8439 , n8440 ,
n8441 , n8442 , n8443 , n8444 , n8445 , n8446 , n8447 , n8448 , n8449 , n8450 ,
n8451 , n8452 , n8453 , n8454 , n8455 , n8456 , n8457 , n8458 , n8459 , n8460 ,
n8461 , n8462 , n8463 , n8464 , n8465 , n8466 , n8467 , n8468 , n8469 , n8470 ,
n8471 , n8472 , n8473 , n8474 , n8475 , n8476 , n8477 , n8478 , n8479 , n8480 ,
n8481 , n8482 , n8483 , n8484 , n8485 , n8486 , n8487 , n8488 , n8489 , n8490 ,
n8491 , n8492 , n8493 , n8494 , n8495 , n8496 , n8497 , n8498 , n8499 , n8500 ,
n8501 , n8502 , n8503 , n8504 , n8505 , n8506 , n8507 , n8508 , n8509 , n8510 ,
n8511 , n8512 , n8513 , n8514 , n8515 , n8516 , n8517 , n8518 , n8519 , n8520 ,
n8521 , n8522 , n8523 , n8524 , n8525 , n8526 , n8527 , n8528 , n8529 , n8530 ,
n8531 , n8532 , n8533 , n8534 , n8535 , n8536 , n8537 , n8538 , n8539 , n8540 ,
n8541 , n8542 , n8543 , n8544 , n8545 , n8546 , n8547 , n8548 , n8549 , n8550 ,
n8551 , n8552 , n8553 , n8554 , n8555 , n8556 , n8557 , n8558 , n8559 , n8560 ,
n8561 , n8562 , n8563 , n8564 , n8565 , n8566 , n8567 , n8568 , n8569 , n8570 ,
n8571 , n8572 , n8573 , n8574 , n8575 , n8576 , n8577 , n8578 , n8579 , n8580 ,
n8581 , n8582 , n8583 , n8584 , n8585 , n8586 , n8587 , n8588 , n8589 , n8590 ,
n8591 , n8592 , n8593 , n8594 , n8595 , n8596 , n8597 , n8598 , n8599 , n8600 ,
n8601 , n8602 , n8603 , n8604 , n8605 , n8606 , n8607 , n8608 , n8609 , n8610 ,
n8611 , n8612 , n8613 , n8614 , n8615 , n8616 , n8617 , n8618 , n8619 , n8620 ,
n8621 , n8622 , n8623 , n8624 , n8625 , n8626 , n8627 , n8628 , n8629 , n8630 ,
n8631 , n8632 , n8633 , n8634 , n8635 , n8636 , n8637 , n8638 , n8639 , n8640 ,
n8641 , n8642 , n8643 , n8644 , n8645 , n8646 , n8647 , n8648 , n8649 , n8650 ,
n8651 , n8652 , n8653 , n8654 , n8655 , n8656 , n8657 , n8658 , n8659 , n8660 ,
n8661 , n8662 , n8663 , n8664 , n8665 , n8666 , n8667 , n8668 , n8669 , n8670 ,
n8671 , n8672 , n8673 , n8674 , n8675 , n8676 , n8677 , n8678 , n8679 , n8680 ,
n8681 , n8682 , n8683 , n8684 , n8685 , n8686 , n8687 , n8688 , n8689 , n8690 ,
n8691 , n8692 , n8693 , n8694 , n8695 , n8696 , n8697 , n8698 , n8699 , n8700 ,
n8701 , n8702 , n8703 , n8704 , n8705 , n8706 , n8707 , n8708 , n8709 , n8710 ,
n8711 , n8712 , n8713 , n8714 , n8715 , n8716 , n8717 , n8718 , n8719 , n8720 ,
n8721 , n8722 , n8723 , n8724 , n8725 , n8726 , n8727 , n8728 , n8729 , n8730 ,
n8731 , n8732 , n8733 , n8734 , n8735 , n8736 , n8737 , n8738 , n8739 , n8740 ,
n8741 , n8742 , n8743 , n8744 , n8745 , n8746 , n8747 , n8748 , n8749 , n8750 ,
n8751 , n8752 , n8753 , n8754 , n8755 , n8756 , n8757 , n8758 , n8759 , n8760 ,
n8761 , n8762 , n8763 , n8764 , n8765 , n8766 , n8767 , n8768 , n8769 , n8770 ,
n8771 , n8772 , n8773 , n8774 , n8775 , n8776 , n8777 , n8778 , n8779 , n8780 ,
n8781 , n8782 , n8783 , n8784 , n8785 , n8786 , n8787 , n8788 , n8789 , n8790 ,
n8791 , n8792 , n8793 , n8794 , n8795 , n8796 , n8797 , n8798 , n8799 , n8800 ,
n8801 , n8802 , n8803 , n8804 , n8805 , n8806 , n8807 , n8808 , n8809 , n8810 ,
n8811 , n8812 , n8813 , n8814 , n8815 , n8816 , n8817 , n8818 , n8819 , n8820 ,
n8821 , n8822 , n8823 , n8824 , n8825 , n8826 , n8827 , n8828 , n8829 , n8830 ,
n8831 , n8832 , n8833 , n8834 , n8835 , n8836 , n8837 , n8838 , n8839 , n8840 ,
n8841 , n8842 , n8843 , n8844 , n8845 , n8846 , n8847 , n8848 , n8849 , n8850 ,
n8851 , n8852 , n8853 , n8854 , n8855 , n8856 , n8857 , n8858 , n8859 , n8860 ,
n8861 , n8862 , n8863 , n8864 , n8865 , n8866 , n8867 , n8868 , n8869 , n8870 ,
n8871 , n8872 , n8873 , n8874 , n8875 , n8876 , n8877 , n8878 , n8879 , n8880 ,
n8881 , n8882 , n8883 , n8884 , n8885 , n8886 , n8887 , n8888 , n8889 , n8890 ,
n8891 , n8892 , n8893 , n8894 , n8895 , n8896 , n8897 , n8898 , n8899 , n8900 ,
n8901 , n8902 , n8903 , n8904 , n8905 , n8906 , n8907 , n8908 , n8909 , n8910 ,
n8911 , n8912 , n8913 , n8914 , n8915 , n8916 , n8917 , n8918 , n8919 , n8920 ,
n8921 , n8922 , n8923 , n8924 , n8925 , n8926 , n8927 , n8928 , n8929 , n8930 ,
n8931 , n8932 , n8933 , n8934 , n8935 , n8936 , n8937 , n8938 , n8939 , n8940 ,
n8941 , n8942 , n8943 , n8944 , n8945 , n8946 , n8947 , n8948 , n8949 , n8950 ,
n8951 , n8952 , n8953 , n8954 , n8955 , n8956 , n8957 , n8958 , n8959 , n8960 ,
n8961 , n8962 , n8963 , n8964 , n8965 , n8966 , n8967 , n8968 , n8969 , n8970 ,
n8971 , n8972 , n8973 , n8974 , n8975 , n8976 , n8977 , n8978 , n8979 , n8980 ,
n8981 , n8982 , n8983 , n8984 , n8985 , n8986 , n8987 , n8988 , n8989 , n8990 ,
n8991 , n8992 , n8993 , n8994 , n8995 , n8996 , n8997 , n8998 , n8999 , n9000 ,
n9001 , n9002 , n9003 , n9004 , n9005 , n9006 , n9007 , n9008 , n9009 , n9010 ,
n9011 , n9012 , n9013 , n9014 , n9015 , n9016 , n9017 , n9018 , n9019 , n9020 ,
n9021 , n9022 , n9023 , n9024 , n9025 , n9026 , n9027 , n9028 , n9029 , n9030 ,
n9031 , n9032 , n9033 , n9034 , n9035 , n9036 , n9037 , n9038 , n9039 , n9040 ,
n9041 , n9042 , n9043 , n9044 , n9045 , n9046 , n9047 , n9048 , n9049 , n9050 ,
n9051 , n9052 , n9053 , n9054 , n9055 , n9056 , n9057 , n9058 , n9059 , n9060 ,
n9061 , n9062 , n9063 , n9064 , n9065 , n9066 , n9067 , n9068 , n9069 , n9070 ,
n9071 , n9072 , n9073 , n9074 , n9075 , n9076 , n9077 , n9078 , n9079 , n9080 ,
n9081 , n9082 , n9083 , n9084 , n9085 , n9086 , n9087 , n9088 , n9089 , n9090 ,
n9091 , n9092 , n9093 , n9094 , n9095 , n9096 , n9097 , n9098 , n9099 , n9100 ,
n9101 , n9102 , n9103 , n9104 , n9105 , n9106 , n9107 , n9108 , n9109 , n9110 ,
n9111 , n9112 , n9113 , n9114 , n9115 , n9116 , n9117 , n9118 , n9119 , n9120 ,
n9121 , n9122 , n9123 , n9124 , n9125 , n9126 , n9127 , n9128 , n9129 , n9130 ,
n9131 , n9132 , n9133 , n9134 , n9135 , n9136 , n9137 , n9138 , n9139 , n9140 ,
n9141 , n9142 , n9143 , n9144 , n9145 , n9146 , n9147 , n9148 , n9149 , n9150 ,
n9151 , n9152 , n9153 , n9154 , n9155 , n9156 , n9157 , n9158 , n9159 , n9160 ,
n9161 , n9162 , n9163 , n9164 , n9165 , n9166 , n9167 , n9168 , n9169 , n9170 ,
n9171 , n9172 , n9173 , n9174 , n9175 , n9176 , n9177 , n9178 , n9179 , n9180 ,
n9181 , n9182 , n9183 , n9184 , n9185 , n9186 , n9187 , n9188 , n9189 , n9190 ,
n9191 , n9192 , n9193 , n9194 , n9195 , n9196 , n9197 , n9198 , n9199 , n9200 ,
n9201 , n9202 , n9203 , n9204 , n9205 , n9206 , n9207 , n9208 , n9209 , n9210 ,
n9211 , n9212 , n9213 , n9214 , n9215 , n9216 , n9217 , n9218 , n9219 , n9220 ,
n9221 , n9222 , n9223 , n9224 , n9225 , n9226 , n9227 , n9228 , n9229 , n9230 ,
n9231 , n9232 , n9233 , n9234 , n9235 , n9236 , n9237 , n9238 , n9239 , n9240 ,
n9241 , n9242 , n9243 , n9244 , n9245 , n9246 , n9247 , n9248 , n9249 , n9250 ,
n9251 , n9252 , n9253 , n9254 , n9255 , n9256 , n9257 , n9258 , n9259 , n9260 ,
n9261 , n9262 , n9263 , n9264 , n9265 , n9266 , n9267 , n9268 , n9269 , n9270 ,
n9271 , n9272 , n9273 , n9274 , n9275 , n9276 , n9277 , n9278 , n9279 , n9280 ,
n9281 , n9282 , n9283 , n9284 , n9285 , n9286 , n9287 , n9288 , n9289 , n9290 ,
n9291 , n9292 , n9293 , n9294 , n9295 , n9296 , n9297 , n9298 , n9299 , n9300 ,
n9301 , n9302 , n9303 , n9304 , n9305 , n9306 , n9307 , n9308 , n9309 , n9310 ,
n9311 , n9312 , n9313 , n9314 , n9315 , n9316 , n9317 , n9318 , n9319 , n9320 ,
n9321 , n9322 , n9323 , n9324 , n9325 , n9326 , n9327 , n9328 , n9329 , n9330 ,
n9331 , n9332 , n9333 , n9334 , n9335 , n9336 , n9337 , n9338 , n9339 , n9340 ,
n9341 , n9342 , n9343 , n9344 , n9345 , n9346 , n9347 , n9348 , n9349 , n9350 ,
n9351 , n9352 , n9353 , n9354 , n9355 , n9356 , n9357 , n9358 , n9359 , n9360 ,
n9361 , n9362 , n9363 , n9364 , n9365 , n9366 , n9367 , n9368 , n9369 , n9370 ,
n9371 , n9372 , n9373 , n9374 , n9375 , n9376 , n9377 , n9378 , n9379 , n9380 ,
n9381 , n9382 , n9383 , n9384 , n9385 , n9386 , n9387 , n9388 , n9389 , n9390 ,
n9391 , n9392 , n9393 , n9394 , n9395 , n9396 , n9397 , n9398 , n9399 , n9400 ,
n9401 , n9402 , n9403 , n9404 , n9405 , n9406 , n9407 , n9408 , n9409 , n9410 ,
n9411 , n9412 , n9413 , n9414 , n9415 , n9416 , n9417 , n9418 , n9419 , n9420 ,
n9421 , n9422 , n9423 , n9424 , n9425 , n9426 , n9427 , n9428 , n9429 , n9430 ,
n9431 , n9432 , n9433 , n9434 , n9435 , n9436 , n9437 , n9438 , n9439 , n9440 ,
n9441 , n9442 , n9443 , n9444 , n9445 , n9446 , n9447 , n9448 , n9449 , n9450 ,
n9451 , n9452 , n9453 , n9454 , n9455 , n9456 , n9457 , n9458 , n9459 , n9460 ,
n9461 , n9462 , n9463 , n9464 , n9465 , n9466 , n9467 , n9468 , n9469 , n9470 ,
n9471 , n9472 , n9473 , n9474 , n9475 , n9476 , n9477 , n9478 , n9479 , n9480 ,
n9481 , n9482 , n9483 , n9484 , n9485 , n9486 , n9487 , n9488 , n9489 , n9490 ,
n9491 , n9492 , n9493 , n9494 , n9495 , n9496 , n9497 , n9498 , n9499 , n9500 ,
n9501 , n9502 , n9503 , n9504 , n9505 , n9506 , n9507 , n9508 , n9509 , n9510 ,
n9511 , n9512 , n9513 , n9514 , n9515 , n9516 , n9517 , n9518 , n9519 , n9520 ,
n9521 , n9522 , n9523 , n9524 , n9525 , n9526 , n9527 , n9528 , n9529 , n9530 ,
n9531 , n9532 , n9533 , n9534 , n9535 , n9536 , n9537 , n9538 , n9539 , n9540 ,
n9541 , n9542 , n9543 , n9544 , n9545 , n9546 , n9547 , n9548 , n9549 , n9550 ,
n9551 , n9552 , n9553 , n9554 , n9555 , n9556 , n9557 , n9558 , n9559 , n9560 ,
n9561 , n9562 , n9563 , n9564 , n9565 , n9566 , n9567 , n9568 , n9569 , n9570 ,
n9571 , n9572 , n9573 , n9574 , n9575 , n9576 , n9577 , n9578 , n9579 , n9580 ,
n9581 , n9582 , n9583 , n9584 , n9585 , n9586 , n9587 , n9588 , n9589 , n9590 ,
n9591 , n9592 , n9593 , n9594 , n9595 , n9596 , n9597 , n9598 , n9599 , n9600 ,
n9601 , n9602 , n9603 , n9604 , n9605 , n9606 , n9607 , n9608 , n9609 , n9610 ,
n9611 , n9612 , n9613 , n9614 , n9615 , n9616 , n9617 , n9618 , n9619 , n9620 ,
n9621 , n9622 , n9623 , n9624 , n9625 , n9626 , n9627 , n9628 , n9629 , n9630 ,
n9631 , n9632 , n9633 , n9634 , n9635 , n9636 , n9637 , n9638 , n9639 , n9640 ,
n9641 , n9642 , n9643 , n9644 , n9645 , n9646 , n9647 , n9648 , n9649 , n9650 ,
n9651 , n9652 , n9653 , n9654 , n9655 , n9656 , n9657 , n9658 , n9659 , n9660 ,
n9661 , n9662 , n9663 , n9664 , n9665 , n9666 , n9667 , n9668 , n9669 , n9670 ,
n9671 , n9672 , n9673 , n9674 , n9675 , n9676 , n9677 , n9678 , n9679 , n9680 ,
n9681 , n9682 , n9683 , n9684 , n9685 , n9686 , n9687 , n9688 , n9689 , n9690 ,
n9691 , n9692 , n9693 , n9694 , n9695 , n9696 , n9697 , n9698 , n9699 , n9700 ,
n9701 , n9702 , n9703 , n9704 , n9705 , n9706 , n9707 , n9708 , n9709 , n9710 ,
n9711 , n9712 , n9713 , n9714 , n9715 , n9716 , n9717 , n9718 , n9719 , n9720 ,
n9721 , n9722 , n9723 , n9724 , n9725 , n9726 , n9727 , n9728 , n9729 , n9730 ,
n9731 , n9732 , n9733 , n9734 , n9735 , n9736 , n9737 , n9738 , n9739 , n9740 ,
n9741 , n9742 , n9743 , n9744 , n9745 , n9746 , n9747 , n9748 , n9749 , n9750 ,
n9751 , n9752 , n9753 , n9754 , n9755 , n9756 , n9757 , n9758 , n9759 , n9760 ,
n9761 , n9762 , n9763 , n9764 , n9765 , n9766 , n9767 , n9768 , n9769 , n9770 ,
n9771 , n9772 , n9773 , n9774 , n9775 , n9776 , n9777 , n9778 , n9779 , n9780 ,
n9781 , n9782 , n9783 , n9784 , n9785 , n9786 , n9787 , n9788 , n9789 , n9790 ,
n9791 , n9792 , n9793 , n9794 , n9795 , n9796 , n9797 , n9798 , n9799 , n9800 ,
n9801 , n9802 , n9803 , n9804 , n9805 , n9806 , n9807 , n9808 , n9809 , n9810 ,
n9811 , n9812 , n9813 , n9814 , n9815 , n9816 , n9817 , n9818 , n9819 , n9820 ,
n9821 , n9822 , n9823 , n9824 , n9825 , n9826 , n9827 , n9828 , n9829 , n9830 ,
n9831 , n9832 , n9833 , n9834 , n9835 , n9836 , n9837 , n9838 , n9839 , n9840 ,
n9841 , n9842 , n9843 , n9844 , n9845 , n9846 , n9847 , n9848 , n9849 , n9850 ,
n9851 , n9852 , n9853 , n9854 , n9855 , n9856 , n9857 , n9858 , n9859 , n9860 ,
n9861 , n9862 , n9863 , n9864 , n9865 , n9866 , n9867 , n9868 , n9869 , n9870 ,
n9871 , n9872 , n9873 , n9874 , n9875 , n9876 , n9877 , n9878 , n9879 , n9880 ,
n9881 , n9882 , n9883 , n9884 , n9885 , n9886 , n9887 , n9888 , n9889 , n9890 ,
n9891 , n9892 , n9893 , n9894 , n9895 , n9896 , n9897 , n9898 , n9899 , n9900 ,
n9901 , n9902 , n9903 , n9904 , n9905 , n9906 , n9907 , n9908 , n9909 , n9910 ,
n9911 , n9912 , n9913 , n9914 , n9915 , n9916 , n9917 , n9918 , n9919 , n9920 ,
n9921 , n9922 , n9923 , n9924 , n9925 , n9926 , n9927 , n9928 , n9929 , n9930 ,
n9931 , n9932 , n9933 , n9934 , n9935 , n9936 , n9937 , n9938 , n9939 , n9940 ,
n9941 , n9942 , n9943 , n9944 , n9945 , n9946 , n9947 , n9948 , n9949 , n9950 ,
n9951 , n9952 , n9953 , n9954 , n9955 , n9956 , n9957 , n9958 , n9959 , n9960 ,
n9961 , n9962 , n9963 , n9964 , n9965 , n9966 , n9967 , n9968 , n9969 , n9970 ,
n9971 , n9972 , n9973 , n9974 , n9975 , n9976 , n9977 , n9978 , n9979 , n9980 ,
n9981 , n9982 , n9983 , n9984 , n9985 , n9986 , n9987 , n9988 , n9989 , n9990 ,
n9991 , n9992 , n9993 , n9994 , n9995 , n9996 , n9997 , n9998 , n9999 , n10000 ,
n10001 , n10002 , n10003 , n10004 , n10005 , n10006 , n10007 , n10008 , n10009 , n10010 ,
n10011 , n10012 , n10013 , n10014 , n10015 , n10016 , n10017 , n10018 , n10019 , n10020 ,
n10021 , n10022 , n10023 , n10024 , n10025 , n10026 , n10027 , n10028 , n10029 , n10030 ,
n10031 , n10032 , n10033 , n10034 , n10035 , n10036 , n10037 , n10038 , n10039 , n10040 ,
n10041 , n10042 , n10043 , n10044 , n10045 , n10046 , n10047 , n10048 , n10049 , n10050 ,
n10051 , n10052 , n10053 , n10054 , n10055 , n10056 , n10057 , n10058 , n10059 , n10060 ,
n10061 , n10062 , n10063 , n10064 , n10065 , n10066 , n10067 , n10068 , n10069 , n10070 ,
n10071 , n10072 , n10073 , n10074 , n10075 , n10076 , n10077 , n10078 , n10079 , n10080 ,
n10081 , n10082 , n10083 , n10084 , n10085 , n10086 , n10087 , n10088 , n10089 , n10090 ,
n10091 , n10092 , n10093 , n10094 , n10095 , n10096 , n10097 , n10098 , n10099 , n10100 ,
n10101 , n10102 , n10103 , n10104 , n10105 , n10106 , n10107 , n10108 , n10109 , n10110 ,
n10111 , n10112 , n10113 , n10114 , n10115 , n10116 , n10117 , n10118 , n10119 , n10120 ,
n10121 , n10122 , n10123 , n10124 , n10125 , n10126 , n10127 , n10128 , n10129 , n10130 ,
n10131 , n10132 , n10133 , n10134 , n10135 , n10136 , n10137 , n10138 , n10139 , n10140 ,
n10141 , n10142 , n10143 , n10144 , n10145 , n10146 , n10147 , n10148 , n10149 , n10150 ,
n10151 , n10152 , n10153 , n10154 , n10155 , n10156 , n10157 , n10158 , n10159 , n10160 ,
n10161 , n10162 , n10163 , n10164 , n10165 , n10166 , n10167 , n10168 , n10169 , n10170 ,
n10171 , n10172 , n10173 , n10174 , n10175 , n10176 , n10177 , n10178 , n10179 , n10180 ,
n10181 , n10182 , n10183 , n10184 , n10185 , n10186 , n10187 , n10188 , n10189 , n10190 ,
n10191 , n10192 , n10193 , n10194 , n10195 , n10196 , n10197 , n10198 , n10199 , n10200 ,
n10201 , n10202 , n10203 , n10204 , n10205 , n10206 , n10207 , n10208 , n10209 , n10210 ,
n10211 , n10212 , n10213 , n10214 , n10215 , n10216 , n10217 , n10218 , n10219 , n10220 ,
n10221 , n10222 , n10223 , n10224 , n10225 , n10226 , n10227 , n10228 , n10229 , n10230 ,
n10231 , n10232 , n10233 , n10234 , n10235 , n10236 , n10237 , n10238 , n10239 , n10240 ,
n10241 , n10242 , n10243 , n10244 , n10245 , n10246 , n10247 , n10248 , n10249 , n10250 ,
n10251 , n10252 , n10253 , n10254 , n10255 , n10256 , n10257 , n10258 , n10259 , n10260 ,
n10261 , n10262 , n10263 , n10264 , n10265 , n10266 , n10267 , n10268 , n10269 , n10270 ,
n10271 , n10272 , n10273 , n10274 , n10275 , n10276 , n10277 , n10278 , n10279 , n10280 ,
n10281 , n10282 , n10283 , n10284 , n10285 , n10286 , n10287 , n10288 , n10289 , n10290 ,
n10291 , n10292 , n10293 , n10294 , n10295 , n10296 , n10297 , n10298 , n10299 , n10300 ,
n10301 , n10302 , n10303 , n10304 , n10305 , n10306 , n10307 , n10308 , n10309 , n10310 ,
n10311 , n10312 , n10313 , n10314 , n10315 , n10316 , n10317 , n10318 , n10319 , n10320 ,
n10321 , n10322 , n10323 , n10324 , n10325 , n10326 , n10327 , n10328 , n10329 , n10330 ,
n10331 , n10332 , n10333 , n10334 , n10335 , n10336 , n10337 , n10338 , n10339 , n10340 ,
n10341 , n10342 , n10343 , n10344 , n10345 , n10346 , n10347 , n10348 , n10349 , n10350 ,
n10351 , n10352 , n10353 , n10354 , n10355 , n10356 , n10357 , n10358 , n10359 , n10360 ,
n10361 , n10362 , n10363 , n10364 , n10365 , n10366 , n10367 , n10368 , n10369 , n10370 ,
n10371 , n10372 , n10373 , n10374 , n10375 , n10376 , n10377 , n10378 , n10379 , n10380 ,
n10381 , n10382 , n10383 , n10384 , n10385 , n10386 , n10387 , n10388 , n10389 , n10390 ,
n10391 , n10392 , n10393 , n10394 , n10395 , n10396 , n10397 , n10398 , n10399 , n10400 ,
n10401 , n10402 , n10403 , n10404 , n10405 , n10406 , n10407 , n10408 , n10409 , n10410 ,
n10411 , n10412 , n10413 , n10414 , n10415 , n10416 , n10417 , n10418 , n10419 , n10420 ,
n10421 , n10422 , n10423 , n10424 , n10425 , n10426 , n10427 , n10428 , n10429 , n10430 ,
n10431 , n10432 , n10433 , n10434 , n10435 , n10436 , n10437 , n10438 , n10439 , n10440 ,
n10441 , n10442 , n10443 , n10444 , n10445 , n10446 , n10447 , n10448 , n10449 , n10450 ,
n10451 , n10452 , n10453 , n10454 , n10455 , n10456 , n10457 , n10458 , n10459 , n10460 ,
n10461 , n10462 , n10463 , n10464 , n10465 , n10466 , n10467 , n10468 , n10469 , n10470 ,
n10471 , n10472 , n10473 , n10474 , n10475 , n10476 , n10477 , n10478 , n10479 , n10480 ,
n10481 , n10482 , n10483 , n10484 , n10485 , n10486 , n10487 , n10488 , n10489 , n10490 ,
n10491 , n10492 , n10493 , n10494 , n10495 , n10496 , n10497 , n10498 , n10499 , n10500 ,
n10501 , n10502 , n10503 , n10504 , n10505 , n10506 , n10507 , n10508 , n10509 , n10510 ,
n10511 , n10512 , n10513 , n10514 , n10515 , n10516 , n10517 , n10518 , n10519 , n10520 ,
n10521 , n10522 , n10523 , n10524 , n10525 , n10526 , n10527 , n10528 , n10529 , n10530 ,
n10531 , n10532 , n10533 , n10534 , n10535 , n10536 , n10537 , n10538 , n10539 , n10540 ,
n10541 , n10542 , n10543 , n10544 , n10545 , n10546 , n10547 , n10548 , n10549 , n10550 ,
n10551 , n10552 , n10553 , n10554 , n10555 , n10556 , n10557 , n10558 , n10559 , n10560 ,
n10561 , n10562 , n10563 , n10564 , n10565 , n10566 , n10567 , n10568 , n10569 , n10570 ,
n10571 , n10572 , n10573 , n10574 , n10575 , n10576 , n10577 , n10578 , n10579 , n10580 ,
n10581 , n10582 , n10583 , n10584 , n10585 , n10586 , n10587 , n10588 , n10589 , n10590 ,
n10591 , n10592 , n10593 , n10594 , n10595 , n10596 , n10597 , n10598 , n10599 , n10600 ,
n10601 , n10602 , n10603 , n10604 , n10605 , n10606 , n10607 , n10608 , n10609 , n10610 ,
n10611 , n10612 , n10613 , n10614 , n10615 , n10616 , n10617 , n10618 , n10619 , n10620 ,
n10621 , n10622 , n10623 , n10624 , n10625 , n10626 , n10627 , n10628 , n10629 , n10630 ,
n10631 , n10632 , n10633 , n10634 , n10635 , n10636 , n10637 , n10638 , n10639 , n10640 ,
n10641 , n10642 , n10643 , n10644 , n10645 , n10646 , n10647 , n10648 , n10649 , n10650 ,
n10651 , n10652 , n10653 , n10654 , n10655 , n10656 , n10657 , n10658 , n10659 , n10660 ,
n10661 , n10662 , n10663 , n10664 , n10665 , n10666 , n10667 , n10668 , n10669 , n10670 ,
n10671 , n10672 , n10673 , n10674 , n10675 , n10676 , n10677 , n10678 , n10679 , n10680 ,
n10681 , n10682 , n10683 , n10684 , n10685 , n10686 , n10687 , n10688 , n10689 , n10690 ,
n10691 , n10692 , n10693 , n10694 , n10695 , n10696 , n10697 , n10698 , n10699 , n10700 ,
n10701 , n10702 , n10703 , n10704 , n10705 , n10706 , n10707 , n10708 , n10709 , n10710 ,
n10711 , n10712 , n10713 , n10714 , n10715 , n10716 , n10717 , n10718 , n10719 , n10720 ,
n10721 , n10722 , n10723 , n10724 , n10725 , n10726 , n10727 , n10728 , n10729 , n10730 ,
n10731 , n10732 , n10733 , n10734 , n10735 , n10736 , n10737 , n10738 , n10739 , n10740 ,
n10741 , n10742 , n10743 , n10744 , n10745 , n10746 , n10747 , n10748 , n10749 , n10750 ,
n10751 , n10752 , n10753 , n10754 , n10755 , n10756 , n10757 , n10758 , n10759 , n10760 ,
n10761 , n10762 , n10763 , n10764 , n10765 , n10766 , n10767 , n10768 , n10769 , n10770 ,
n10771 , n10772 , n10773 , n10774 , n10775 , n10776 , n10777 , n10778 , n10779 , n10780 ,
n10781 , n10782 , n10783 , n10784 , n10785 , n10786 , n10787 , n10788 , n10789 , n10790 ,
n10791 , n10792 , n10793 , n10794 , n10795 , n10796 , n10797 , n10798 , n10799 , n10800 ,
n10801 , n10802 , n10803 , n10804 , n10805 , n10806 , n10807 , n10808 , n10809 , n10810 ,
n10811 , n10812 , n10813 , n10814 , n10815 , n10816 , n10817 , n10818 , n10819 , n10820 ,
n10821 , n10822 , n10823 , n10824 , n10825 , n10826 , n10827 , n10828 , n10829 , n10830 ,
n10831 , n10832 , n10833 , n10834 , n10835 , n10836 , n10837 , n10838 , n10839 , n10840 ,
n10841 , n10842 , n10843 , n10844 , n10845 , n10846 , n10847 , n10848 , n10849 , n10850 ,
n10851 , n10852 , n10853 , n10854 , n10855 , n10856 , n10857 , n10858 , n10859 , n10860 ,
n10861 , n10862 , n10863 , n10864 , n10865 , n10866 , n10867 , n10868 , n10869 , n10870 ,
n10871 , n10872 , n10873 , n10874 , n10875 , n10876 , n10877 , n10878 , n10879 , n10880 ,
n10881 , n10882 , n10883 , n10884 , n10885 , n10886 , n10887 , n10888 , n10889 , n10890 ,
n10891 , n10892 , n10893 , n10894 , n10895 , n10896 , n10897 , n10898 , n10899 , n10900 ,
n10901 , n10902 , n10903 , n10904 , n10905 , n10906 , n10907 , n10908 , n10909 , n10910 ,
n10911 , n10912 , n10913 , n10914 , n10915 , n10916 , n10917 , n10918 , n10919 , n10920 ,
n10921 , n10922 , n10923 , n10924 , n10925 , n10926 , n10927 , n10928 , n10929 , n10930 ,
n10931 , n10932 , n10933 , n10934 , n10935 , n10936 , n10937 , n10938 , n10939 , n10940 ,
n10941 , n10942 , n10943 , n10944 , n10945 , n10946 , n10947 , n10948 , n10949 , n10950 ,
n10951 , n10952 , n10953 , n10954 , n10955 , n10956 , n10957 , n10958 , n10959 , n10960 ,
n10961 , n10962 , n10963 , n10964 , n10965 , n10966 , n10967 , n10968 , n10969 , n10970 ,
n10971 , n10972 , n10973 , n10974 , n10975 , n10976 , n10977 , n10978 , n10979 , n10980 ,
n10981 , n10982 , n10983 , n10984 , n10985 , n10986 , n10987 , n10988 , n10989 , n10990 ,
n10991 , n10992 , n10993 , n10994 , n10995 , n10996 , n10997 , n10998 , n10999 , n11000 ,
n11001 , n11002 , n11003 , n11004 , n11005 , n11006 , n11007 , n11008 , n11009 , n11010 ,
n11011 , n11012 , n11013 , n11014 , n11015 , n11016 , n11017 , n11018 , n11019 , n11020 ,
n11021 , n11022 , n11023 , n11024 , n11025 , n11026 , n11027 , n11028 , n11029 , n11030 ,
n11031 , n11032 , n11033 , n11034 , n11035 , n11036 , n11037 , n11038 , n11039 , n11040 ,
n11041 , n11042 , n11043 , n11044 , n11045 , n11046 , n11047 , n11048 , n11049 , n11050 ,
n11051 , n11052 , n11053 , n11054 , n11055 , n11056 , n11057 , n11058 , n11059 , n11060 ,
n11061 , n11062 , n11063 , n11064 , n11065 , n11066 , n11067 , n11068 , n11069 , n11070 ,
n11071 , n11072 , n11073 , n11074 , n11075 , n11076 , n11077 , n11078 , n11079 , n11080 ,
n11081 , n11082 , n11083 , n11084 , n11085 , n11086 , n11087 , n11088 , n11089 , n11090 ,
n11091 , n11092 , n11093 , n11094 , n11095 , n11096 , n11097 , n11098 , n11099 , n11100 ,
n11101 , n11102 , n11103 , n11104 , n11105 , n11106 , n11107 , n11108 , n11109 , n11110 ,
n11111 , n11112 , n11113 , n11114 , n11115 , n11116 , n11117 , n11118 , n11119 , n11120 ,
n11121 , n11122 , n11123 , n11124 , n11125 , n11126 , n11127 , n11128 , n11129 , n11130 ,
n11131 , n11132 , n11133 , n11134 , n11135 , n11136 , n11137 , n11138 , n11139 , n11140 ,
n11141 , n11142 , n11143 , n11144 , n11145 , n11146 , n11147 , n11148 , n11149 , n11150 ,
n11151 , n11152 , n11153 , n11154 , n11155 , n11156 , n11157 , n11158 , n11159 , n11160 ,
n11161 , n11162 , n11163 , n11164 , n11165 , n11166 , n11167 , n11168 , n11169 , n11170 ,
n11171 , n11172 , n11173 , n11174 , n11175 , n11176 , n11177 , n11178 , n11179 , n11180 ,
n11181 , n11182 , n11183 , n11184 , n11185 , n11186 , n11187 , n11188 , n11189 , n11190 ,
n11191 , n11192 , n11193 , n11194 , n11195 , n11196 , n11197 , n11198 , n11199 , n11200 ,
n11201 , n11202 , n11203 , n11204 , n11205 , n11206 , n11207 , n11208 , n11209 , n11210 ,
n11211 , n11212 , n11213 , n11214 , n11215 , n11216 , n11217 , n11218 , n11219 , n11220 ,
n11221 , n11222 , n11223 , n11224 , n11225 , n11226 , n11227 , n11228 , n11229 , n11230 ,
n11231 , n11232 , n11233 , n11234 , n11235 , n11236 , n11237 , n11238 , n11239 , n11240 ,
n11241 , n11242 , n11243 , n11244 , n11245 , n11246 , n11247 , n11248 , n11249 , n11250 ,
n11251 , n11252 , n11253 , n11254 , n11255 , n11256 , n11257 , n11258 , n11259 , n11260 ,
n11261 , n11262 , n11263 , n11264 , n11265 , n11266 , n11267 , n11268 , n11269 , n11270 ,
n11271 , n11272 , n11273 , n11274 , n11275 , n11276 , n11277 , n11278 , n11279 , n11280 ,
n11281 , n11282 , n11283 , n11284 , n11285 , n11286 , n11287 , n11288 , n11289 , n11290 ,
n11291 , n11292 , n11293 , n11294 , n11295 , n11296 , n11297 , n11298 , n11299 , n11300 ,
n11301 , n11302 , n11303 , n11304 , n11305 , n11306 , n11307 , n11308 , n11309 , n11310 ,
n11311 , n11312 , n11313 , n11314 , n11315 , n11316 , n11317 , n11318 , n11319 , n11320 ,
n11321 , n11322 , n11323 , n11324 , n11325 , n11326 , n11327 , n11328 , n11329 , n11330 ,
n11331 , n11332 , n11333 , n11334 , n11335 , n11336 , n11337 , n11338 , n11339 , n11340 ,
n11341 , n11342 , n11343 , n11344 , n11345 , n11346 , n11347 , n11348 , n11349 , n11350 ,
n11351 , n11352 , n11353 , n11354 , n11355 , n11356 , n11357 , n11358 , n11359 , n11360 ,
n11361 , n11362 , n11363 , n11364 , n11365 , n11366 , n11367 , n11368 , n11369 , n11370 ,
n11371 , n11372 , n11373 , n11374 , n11375 , n11376 , n11377 , n11378 , n11379 , n11380 ,
n11381 , n11382 , n11383 , n11384 , n11385 , n11386 , n11387 , n11388 , n11389 , n11390 ,
n11391 , n11392 , n11393 , n11394 , n11395 , n11396 , n11397 , n11398 , n11399 , n11400 ,
n11401 , n11402 , n11403 , n11404 , n11405 , n11406 , n11407 , n11408 , n11409 , n11410 ,
n11411 , n11412 , n11413 , n11414 , n11415 , n11416 , n11417 , n11418 , n11419 , n11420 ,
n11421 , n11422 , n11423 , n11424 , n11425 , n11426 , n11427 , n11428 , n11429 , n11430 ,
n11431 , n11432 , n11433 , n11434 , n11435 , n11436 , n11437 , n11438 , n11439 , n11440 ,
n11441 , n11442 , n11443 , n11444 , n11445 , n11446 , n11447 , n11448 , n11449 , n11450 ,
n11451 , n11452 , n11453 , n11454 , n11455 , n11456 , n11457 , n11458 , n11459 , n11460 ,
n11461 , n11462 , n11463 , n11464 , n11465 , n11466 , n11467 , n11468 , n11469 , n11470 ,
n11471 , n11472 , n11473 , n11474 , n11475 , n11476 , n11477 , n11478 , n11479 , n11480 ,
n11481 , n11482 , n11483 , n11484 , n11485 , n11486 , n11487 , n11488 , n11489 , n11490 ,
n11491 , n11492 , n11493 , n11494 , n11495 , n11496 , n11497 , n11498 , n11499 , n11500 ,
n11501 , n11502 , n11503 , n11504 , n11505 , n11506 , n11507 , n11508 , n11509 , n11510 ,
n11511 , n11512 , n11513 , n11514 , n11515 , n11516 , n11517 , n11518 , n11519 , n11520 ,
n11521 , n11522 , n11523 , n11524 , n11525 , n11526 , n11527 , n11528 , n11529 , n11530 ,
n11531 , n11532 , n11533 , n11534 , n11535 , n11536 , n11537 , n11538 , n11539 , n11540 ,
n11541 , n11542 , n11543 , n11544 , n11545 , n11546 , n11547 , n11548 , n11549 , n11550 ,
n11551 , n11552 , n11553 , n11554 , n11555 , n11556 , n11557 , n11558 , n11559 , n11560 ,
n11561 , n11562 , n11563 , n11564 , n11565 , n11566 , n11567 , n11568 , n11569 , n11570 ,
n11571 , n11572 , n11573 , n11574 , n11575 , n11576 , n11577 , n11578 , n11579 , n11580 ,
n11581 , n11582 , n11583 , n11584 , n11585 , n11586 , n11587 , n11588 , n11589 , n11590 ,
n11591 , n11592 , n11593 , n11594 , n11595 , n11596 , n11597 , n11598 , n11599 , n11600 ,
n11601 , n11602 , n11603 , n11604 , n11605 , n11606 , n11607 , n11608 , n11609 , n11610 ,
n11611 , n11612 , n11613 , n11614 , n11615 , n11616 , n11617 , n11618 , n11619 , n11620 ,
n11621 , n11622 , n11623 , n11624 , n11625 , n11626 , n11627 , n11628 , n11629 , n11630 ,
n11631 , n11632 , n11633 , n11634 , n11635 , n11636 , n11637 , n11638 , n11639 , n11640 ,
n11641 , n11642 , n11643 , n11644 , n11645 , n11646 , n11647 , n11648 , n11649 , n11650 ,
n11651 , n11652 , n11653 , n11654 , n11655 , n11656 , n11657 , n11658 , n11659 , n11660 ,
n11661 , n11662 , n11663 , n11664 , n11665 , n11666 , n11667 , n11668 , n11669 , n11670 ,
n11671 , n11672 , n11673 , n11674 , n11675 , n11676 , n11677 , n11678 , n11679 , n11680 ,
n11681 , n11682 , n11683 , n11684 , n11685 , n11686 , n11687 , n11688 , n11689 , n11690 ,
n11691 , n11692 , n11693 , n11694 , n11695 , n11696 , n11697 , n11698 , n11699 , n11700 ,
n11701 , n11702 , n11703 , n11704 , n11705 , n11706 , n11707 , n11708 , n11709 , n11710 ,
n11711 , n11712 , n11713 , n11714 , n11715 , n11716 , n11717 , n11718 , n11719 , n11720 ,
n11721 , n11722 , n11723 , n11724 , n11725 , n11726 , n11727 , n11728 , n11729 , n11730 ,
n11731 , n11732 , n11733 , n11734 , n11735 , n11736 , n11737 , n11738 , n11739 , n11740 ,
n11741 , n11742 , n11743 , n11744 , n11745 , n11746 , n11747 , n11748 , n11749 , n11750 ,
n11751 , n11752 , n11753 , n11754 , n11755 , n11756 , n11757 , n11758 , n11759 , n11760 ,
n11761 , n11762 , n11763 , n11764 , n11765 , n11766 , n11767 , n11768 , n11769 , n11770 ,
n11771 , n11772 , n11773 , n11774 , n11775 , n11776 , n11777 , n11778 , n11779 , n11780 ,
n11781 , n11782 , n11783 , n11784 , n11785 , n11786 , n11787 , n11788 , n11789 , n11790 ,
n11791 , n11792 , n11793 , n11794 , n11795 , n11796 , n11797 , n11798 , n11799 , n11800 ,
n11801 , n11802 , n11803 , n11804 , n11805 , n11806 , n11807 , n11808 , n11809 , n11810 ,
n11811 , n11812 , n11813 , n11814 , n11815 , n11816 , n11817 , n11818 , n11819 , n11820 ,
n11821 , n11822 , n11823 , n11824 , n11825 , n11826 , n11827 , n11828 , n11829 , n11830 ,
n11831 , n11832 , n11833 , n11834 , n11835 , n11836 , n11837 , n11838 , n11839 , n11840 ,
n11841 , n11842 , n11843 , n11844 , n11845 , n11846 , n11847 , n11848 , n11849 , n11850 ,
n11851 , n11852 , n11853 , n11854 , n11855 , n11856 , n11857 , n11858 , n11859 , n11860 ,
n11861 , n11862 , n11863 , n11864 , n11865 , n11866 , n11867 , n11868 , n11869 , n11870 ,
n11871 , n11872 , n11873 , n11874 , n11875 , n11876 , n11877 , n11878 , n11879 , n11880 ,
n11881 , n11882 , n11883 , n11884 , n11885 , n11886 , n11887 , n11888 , n11889 , n11890 ,
n11891 , n11892 , n11893 , n11894 , n11895 , n11896 , n11897 , n11898 , n11899 , n11900 ,
n11901 , n11902 , n11903 , n11904 , n11905 , n11906 , n11907 , n11908 , n11909 , n11910 ,
n11911 , n11912 , n11913 , n11914 , n11915 , n11916 , n11917 , n11918 , n11919 , n11920 ,
n11921 , n11922 , n11923 , n11924 , n11925 , n11926 , n11927 , n11928 , n11929 , n11930 ,
n11931 , n11932 , n11933 , n11934 , n11935 , n11936 , n11937 , n11938 , n11939 , n11940 ,
n11941 , n11942 , n11943 , n11944 , n11945 , n11946 , n11947 , n11948 , n11949 , n11950 ,
n11951 , n11952 , n11953 , n11954 , n11955 , n11956 , n11957 , n11958 , n11959 , n11960 ,
n11961 , n11962 , n11963 , n11964 , n11965 , n11966 , n11967 , n11968 , n11969 , n11970 ,
n11971 , n11972 , n11973 , n11974 , n11975 , n11976 , n11977 , n11978 , n11979 , n11980 ,
n11981 , n11982 , n11983 , n11984 , n11985 , n11986 , n11987 , n11988 , n11989 , n11990 ,
n11991 , n11992 , n11993 , n11994 , n11995 , n11996 , n11997 , n11998 , n11999 , n12000 ,
n12001 , n12002 , n12003 , n12004 , n12005 , n12006 , n12007 , n12008 , n12009 , n12010 ,
n12011 , n12012 , n12013 , n12014 , n12015 , n12016 , n12017 , n12018 , n12019 , n12020 ,
n12021 , n12022 , n12023 , n12024 , n12025 , n12026 , n12027 , n12028 , n12029 , n12030 ,
n12031 , n12032 , n12033 , n12034 , n12035 , n12036 , n12037 , n12038 , n12039 , n12040 ,
n12041 , n12042 , n12043 , n12044 , n12045 , n12046 , n12047 , n12048 , n12049 , n12050 ,
n12051 , n12052 , n12053 , n12054 , n12055 , n12056 , n12057 , n12058 , n12059 , n12060 ,
n12061 , n12062 , n12063 , n12064 , n12065 , n12066 , n12067 , n12068 , n12069 , n12070 ,
n12071 , n12072 , n12073 , n12074 , n12075 , n12076 , n12077 , n12078 , n12079 , n12080 ,
n12081 , n12082 , n12083 , n12084 , n12085 , n12086 , n12087 , n12088 , n12089 , n12090 ,
n12091 , n12092 , n12093 , n12094 , n12095 , n12096 , n12097 , n12098 , n12099 , n12100 ,
n12101 , n12102 , n12103 , n12104 , n12105 , n12106 , n12107 , n12108 , n12109 , n12110 ,
n12111 , n12112 , n12113 , n12114 , n12115 , n12116 , n12117 , n12118 , n12119 , n12120 ,
n12121 , n12122 , n12123 , n12124 , n12125 , n12126 , n12127 , n12128 , n12129 , n12130 ,
n12131 , n12132 , n12133 , n12134 , n12135 , n12136 , n12137 , n12138 , n12139 , n12140 ,
n12141 , n12142 , n12143 , n12144 , n12145 , n12146 , n12147 , n12148 , n12149 , n12150 ,
n12151 , n12152 , n12153 , n12154 , n12155 , n12156 , n12157 , n12158 , n12159 , n12160 ,
n12161 , n12162 , n12163 , n12164 , n12165 , n12166 , n12167 , n12168 , n12169 , n12170 ,
n12171 , n12172 , n12173 , n12174 , n12175 , n12176 , n12177 , n12178 , n12179 , n12180 ,
n12181 , n12182 , n12183 , n12184 , n12185 , n12186 , n12187 , n12188 , n12189 , n12190 ,
n12191 , n12192 , n12193 , n12194 , n12195 , n12196 , n12197 , n12198 , n12199 , n12200 ,
n12201 , n12202 , n12203 , n12204 , n12205 , n12206 , n12207 , n12208 , n12209 , n12210 ,
n12211 , n12212 , n12213 , n12214 , n12215 , n12216 , n12217 , n12218 , n12219 , n12220 ,
n12221 , n12222 , n12223 , n12224 , n12225 , n12226 , n12227 , n12228 , n12229 , n12230 ,
n12231 , n12232 , n12233 , n12234 , n12235 , n12236 , n12237 , n12238 , n12239 , n12240 ,
n12241 , n12242 , n12243 , n12244 , n12245 , n12246 , n12247 , n12248 , n12249 , n12250 ,
n12251 , n12252 , n12253 , n12254 , n12255 , n12256 , n12257 , n12258 , n12259 , n12260 ,
n12261 , n12262 , n12263 , n12264 , n12265 , n12266 , n12267 , n12268 , n12269 , n12270 ,
n12271 , n12272 , n12273 , n12274 , n12275 , n12276 , n12277 , n12278 , n12279 , n12280 ,
n12281 , n12282 , n12283 , n12284 , n12285 , n12286 , n12287 , n12288 , n12289 , n12290 ,
n12291 , n12292 , n12293 , n12294 , n12295 , n12296 , n12297 , n12298 , n12299 , n12300 ,
n12301 , n12302 , n12303 , n12304 , n12305 , n12306 , n12307 , n12308 , n12309 , n12310 ,
n12311 , n12312 , n12313 , n12314 , n12315 , n12316 , n12317 , n12318 , n12319 , n12320 ,
n12321 , n12322 , n12323 , n12324 , n12325 , n12326 , n12327 , n12328 , n12329 , n12330 ,
n12331 , n12332 , n12333 , n12334 , n12335 , n12336 , n12337 , n12338 , n12339 , n12340 ,
n12341 , n12342 , n12343 , n12344 , n12345 , n12346 , n12347 , n12348 , n12349 , n12350 ,
n12351 , n12352 , n12353 , n12354 , n12355 , n12356 , n12357 , n12358 , n12359 , n12360 ,
n12361 , n12362 , n12363 , n12364 , n12365 , n12366 , n12367 , n12368 , n12369 , n12370 ,
n12371 , n12372 , n12373 , n12374 , n12375 , n12376 , n12377 , n12378 , n12379 , n12380 ,
n12381 , n12382 , n12383 , n12384 , n12385 , n12386 , n12387 , n12388 , n12389 , n12390 ,
n12391 , n12392 , n12393 , n12394 , n12395 , n12396 , n12397 , n12398 , n12399 , n12400 ,
n12401 , n12402 , n12403 , n12404 , n12405 , n12406 , n12407 , n12408 , n12409 , n12410 ,
n12411 , n12412 , n12413 , n12414 , n12415 , n12416 , n12417 , n12418 , n12419 , n12420 ,
n12421 , n12422 , n12423 , n12424 , n12425 , n12426 , n12427 , n12428 , n12429 , n12430 ,
n12431 , n12432 , n12433 , n12434 , n12435 , n12436 , n12437 , n12438 , n12439 , n12440 ,
n12441 , n12442 , n12443 , n12444 , n12445 , n12446 , n12447 , n12448 , n12449 , n12450 ,
n12451 , n12452 , n12453 , n12454 , n12455 , n12456 , n12457 , n12458 , n12459 , n12460 ,
n12461 , n12462 , n12463 , n12464 , n12465 , n12466 , n12467 , n12468 , n12469 , n12470 ,
n12471 , n12472 , n12473 , n12474 , n12475 , n12476 , n12477 , n12478 , n12479 , n12480 ,
n12481 , n12482 , n12483 , n12484 , n12485 , n12486 , n12487 , n12488 , n12489 , n12490 ,
n12491 , n12492 , n12493 , n12494 , n12495 , n12496 , n12497 , n12498 , n12499 , n12500 ,
n12501 , n12502 , n12503 , n12504 , n12505 , n12506 , n12507 , n12508 , n12509 , n12510 ,
n12511 , n12512 , n12513 , n12514 , n12515 , n12516 , n12517 , n12518 , n12519 , n12520 ,
n12521 , n12522 , n12523 , n12524 , n12525 , n12526 , n12527 , n12528 , n12529 , n12530 ,
n12531 , n12532 , n12533 , n12534 , n12535 , n12536 , n12537 , n12538 , n12539 , n12540 ,
n12541 , n12542 , n12543 , n12544 , n12545 , n12546 , n12547 , n12548 , n12549 , n12550 ,
n12551 , n12552 , n12553 , n12554 , n12555 , n12556 , n12557 , n12558 , n12559 , n12560 ,
n12561 , n12562 , n12563 , n12564 , n12565 , n12566 , n12567 , n12568 , n12569 , n12570 ,
n12571 , n12572 , n12573 , n12574 , n12575 , n12576 , n12577 , n12578 , n12579 , n12580 ,
n12581 , n12582 , n12583 , n12584 , n12585 , n12586 , n12587 , n12588 , n12589 , n12590 ,
n12591 , n12592 , n12593 , n12594 , n12595 , n12596 , n12597 , n12598 , n12599 , n12600 ,
n12601 , n12602 , n12603 , n12604 , n12605 , n12606 , n12607 , n12608 , n12609 , n12610 ,
n12611 , n12612 , n12613 , n12614 , n12615 , n12616 , n12617 , n12618 , n12619 , n12620 ,
n12621 , n12622 , n12623 , n12624 , n12625 , n12626 , n12627 , n12628 , n12629 , n12630 ,
n12631 , n12632 , n12633 , n12634 , n12635 , n12636 , n12637 , n12638 , n12639 , n12640 ,
n12641 , n12642 , n12643 , n12644 , n12645 , n12646 , n12647 , n12648 , n12649 , n12650 ,
n12651 , n12652 , n12653 , n12654 , n12655 , n12656 , n12657 , n12658 , n12659 , n12660 ,
n12661 , n12662 , n12663 , n12664 , n12665 , n12666 , n12667 , n12668 , n12669 , n12670 ,
n12671 , n12672 , n12673 , n12674 , n12675 , n12676 , n12677 , n12678 , n12679 , n12680 ,
n12681 , n12682 , n12683 , n12684 , n12685 , n12686 , n12687 , n12688 , n12689 , n12690 ,
n12691 , n12692 , n12693 , n12694 , n12695 , n12696 , n12697 , n12698 , n12699 , n12700 ,
n12701 , n12702 , n12703 , n12704 , n12705 , n12706 , n12707 , n12708 , n12709 , n12710 ,
n12711 , n12712 , n12713 , n12714 , n12715 , n12716 , n12717 , n12718 , n12719 , n12720 ,
n12721 , n12722 , n12723 , n12724 , n12725 , n12726 , n12727 , n12728 , n12729 , n12730 ,
n12731 , n12732 , n12733 , n12734 , n12735 , n12736 , n12737 , n12738 , n12739 , n12740 ,
n12741 , n12742 , n12743 , n12744 , n12745 , n12746 , n12747 , n12748 , n12749 , n12750 ,
n12751 , n12752 , n12753 , n12754 , n12755 , n12756 , n12757 , n12758 , n12759 , n12760 ,
n12761 , n12762 , n12763 , n12764 , n12765 , n12766 , n12767 , n12768 , n12769 , n12770 ,
n12771 , n12772 , n12773 , n12774 , n12775 , n12776 , n12777 , n12778 , n12779 , n12780 ,
n12781 , n12782 , n12783 , n12784 , n12785 , n12786 , n12787 , n12788 , n12789 , n12790 ,
n12791 , n12792 , n12793 , n12794 , n12795 , n12796 , n12797 , n12798 , n12799 , n12800 ,
n12801 , n12802 , n12803 , n12804 , n12805 , n12806 , n12807 , n12808 , n12809 , n12810 ,
n12811 , n12812 , n12813 , n12814 , n12815 , n12816 , n12817 , n12818 , n12819 , n12820 ,
n12821 , n12822 , n12823 , n12824 , n12825 , n12826 , n12827 , n12828 , n12829 , n12830 ,
n12831 , n12832 , n12833 , n12834 , n12835 , n12836 , n12837 , n12838 , n12839 , n12840 ,
n12841 , n12842 , n12843 , n12844 , n12845 , n12846 , n12847 , n12848 , n12849 , n12850 ,
n12851 , n12852 , n12853 , n12854 , n12855 , n12856 , n12857 , n12858 , n12859 , n12860 ,
n12861 , n12862 , n12863 , n12864 , n12865 , n12866 , n12867 , n12868 , n12869 , n12870 ,
n12871 , n12872 , n12873 , n12874 , n12875 , n12876 , n12877 , n12878 , n12879 , n12880 ,
n12881 , n12882 , n12883 , n12884 , n12885 , n12886 , n12887 , n12888 , n12889 , n12890 ,
n12891 , n12892 , n12893 , n12894 , n12895 , n12896 , n12897 , n12898 , n12899 , n12900 ,
n12901 , n12902 , n12903 , n12904 , n12905 , n12906 , n12907 , n12908 , n12909 , n12910 ,
n12911 , n12912 , n12913 , n12914 , n12915 , n12916 , n12917 , n12918 , n12919 , n12920 ,
n12921 , n12922 , n12923 , n12924 , n12925 , n12926 , n12927 , n12928 , n12929 , n12930 ,
n12931 , n12932 , n12933 , n12934 , n12935 , n12936 , n12937 , n12938 , n12939 , n12940 ,
n12941 , n12942 , n12943 , n12944 , n12945 , n12946 , n12947 , n12948 , n12949 , n12950 ,
n12951 , n12952 , n12953 , n12954 , n12955 , n12956 , n12957 , n12958 , n12959 , n12960 ,
n12961 , n12962 , n12963 , n12964 , n12965 , n12966 , n12967 , n12968 , n12969 , n12970 ,
n12971 , n12972 , n12973 , n12974 , n12975 , n12976 , n12977 , n12978 , n12979 , n12980 ,
n12981 , n12982 , n12983 , n12984 , n12985 , n12986 , n12987 , n12988 , n12989 , n12990 ,
n12991 , n12992 , n12993 , n12994 , n12995 , n12996 , n12997 , n12998 , n12999 , n13000 ,
n13001 , n13002 , n13003 , n13004 , n13005 , n13006 , n13007 , n13008 , n13009 , n13010 ,
n13011 , n13012 , n13013 , n13014 , n13015 , n13016 , n13017 , n13018 , n13019 , n13020 ,
n13021 , n13022 , n13023 , n13024 , n13025 , n13026 , n13027 , n13028 , n13029 , n13030 ,
n13031 , n13032 , n13033 , n13034 , n13035 , n13036 , n13037 , n13038 , n13039 , n13040 ,
n13041 , n13042 , n13043 , n13044 , n13045 , n13046 , n13047 , n13048 , n13049 , n13050 ,
n13051 , n13052 , n13053 , n13054 , n13055 , n13056 , n13057 , n13058 , n13059 , n13060 ,
n13061 , n13062 , n13063 , n13064 , n13065 , n13066 , n13067 , n13068 , n13069 , n13070 ,
n13071 , n13072 , n13073 , n13074 , n13075 , n13076 , n13077 , n13078 , n13079 , n13080 ,
n13081 , n13082 , n13083 , n13084 , n13085 , n13086 , n13087 , n13088 , n13089 , n13090 ,
n13091 , n13092 , n13093 , n13094 , n13095 , n13096 , n13097 , n13098 , n13099 , n13100 ,
n13101 , n13102 , n13103 , n13104 , n13105 , n13106 , n13107 , n13108 , n13109 , n13110 ,
n13111 , n13112 , n13113 , n13114 , n13115 , n13116 , n13117 , n13118 , n13119 , n13120 ,
n13121 , n13122 , n13123 , n13124 , n13125 , n13126 , n13127 , n13128 , n13129 , n13130 ,
n13131 , n13132 , n13133 , n13134 , n13135 , n13136 , n13137 , n13138 , n13139 , n13140 ,
n13141 , n13142 , n13143 , n13144 , n13145 , n13146 , n13147 , n13148 , n13149 , n13150 ,
n13151 , n13152 , n13153 , n13154 , n13155 , n13156 , n13157 , n13158 , n13159 , n13160 ,
n13161 , n13162 , n13163 , n13164 , n13165 , n13166 , n13167 , n13168 , n13169 , n13170 ,
n13171 , n13172 , n13173 , n13174 , n13175 , n13176 , n13177 , n13178 , n13179 , n13180 ,
n13181 , n13182 , n13183 , n13184 , n13185 , n13186 , n13187 , n13188 , n13189 , n13190 ,
n13191 , n13192 , n13193 , n13194 , n13195 , n13196 , n13197 , n13198 , n13199 , n13200 ,
n13201 , n13202 , n13203 , n13204 , n13205 , n13206 , n13207 , n13208 , n13209 , n13210 ,
n13211 , n13212 , n13213 , n13214 , n13215 , n13216 , n13217 , n13218 , n13219 , n13220 ,
n13221 , n13222 , n13223 , n13224 , n13225 , n13226 , n13227 , n13228 , n13229 , n13230 ,
n13231 , n13232 , n13233 , n13234 , n13235 , n13236 , n13237 , n13238 , n13239 , n13240 ,
n13241 , n13242 , n13243 , n13244 , n13245 , n13246 , n13247 , n13248 , n13249 , n13250 ,
n13251 , n13252 , n13253 , n13254 , n13255 , n13256 , n13257 , n13258 , n13259 , n13260 ,
n13261 , n13262 , n13263 , n13264 , n13265 , n13266 , n13267 , n13268 , n13269 , n13270 ,
n13271 , n13272 , n13273 , n13274 , n13275 , n13276 , n13277 , n13278 , n13279 , n13280 ,
n13281 , n13282 , n13283 , n13284 , n13285 , n13286 , n13287 , n13288 , n13289 , n13290 ,
n13291 , n13292 , n13293 , n13294 , n13295 , n13296 , n13297 , n13298 , n13299 , n13300 ,
n13301 , n13302 , n13303 , n13304 , n13305 , n13306 , n13307 , n13308 , n13309 , n13310 ,
n13311 , n13312 , n13313 , n13314 , n13315 , n13316 , n13317 , n13318 , n13319 , n13320 ,
n13321 , n13322 , n13323 , n13324 , n13325 , n13326 , n13327 , n13328 , n13329 , n13330 ,
n13331 , n13332 , n13333 , n13334 , n13335 , n13336 , n13337 , n13338 , n13339 , n13340 ,
n13341 , n13342 , n13343 , n13344 , n13345 , n13346 , n13347 , n13348 , n13349 , n13350 ,
n13351 , n13352 , n13353 , n13354 , n13355 , n13356 , n13357 , n13358 , n13359 , n13360 ,
n13361 , n13362 , n13363 , n13364 , n13365 , n13366 , n13367 , n13368 , n13369 , n13370 ,
n13371 , n13372 , n13373 , n13374 , n13375 , n13376 , n13377 , n13378 , n13379 , n13380 ,
n13381 , n13382 , n13383 , n13384 , n13385 , n13386 , n13387 , n13388 , n13389 , n13390 ,
n13391 , n13392 , n13393 , n13394 , n13395 , n13396 , n13397 , n13398 , n13399 , n13400 ,
n13401 , n13402 , n13403 , n13404 , n13405 , n13406 , n13407 , n13408 , n13409 , n13410 ,
n13411 , n13412 , n13413 , n13414 , n13415 , n13416 , n13417 , n13418 , n13419 , n13420 ,
n13421 , n13422 , n13423 , n13424 , n13425 , n13426 , n13427 , n13428 , n13429 , n13430 ,
n13431 , n13432 , n13433 , n13434 , n13435 , n13436 , n13437 , n13438 , n13439 , n13440 ,
n13441 , n13442 , n13443 , n13444 , n13445 , n13446 , n13447 , n13448 , n13449 , n13450 ,
n13451 , n13452 , n13453 , n13454 , n13455 , n13456 , n13457 , n13458 , n13459 , n13460 ,
n13461 , n13462 , n13463 , n13464 , n13465 , n13466 , n13467 , n13468 , n13469 , n13470 ,
n13471 , n13472 , n13473 , n13474 , n13475 , n13476 , n13477 , n13478 , n13479 , n13480 ,
n13481 , n13482 , n13483 , n13484 , n13485 , n13486 , n13487 , n13488 , n13489 , n13490 ,
n13491 , n13492 , n13493 , n13494 , n13495 , n13496 , n13497 , n13498 , n13499 , n13500 ,
n13501 , n13502 , n13503 , n13504 , n13505 , n13506 , n13507 , n13508 , n13509 , n13510 ,
n13511 , n13512 , n13513 , n13514 , n13515 , n13516 , n13517 , n13518 , n13519 , n13520 ,
n13521 , n13522 , n13523 , n13524 , n13525 , n13526 , n13527 , n13528 , n13529 , n13530 ,
n13531 , n13532 , n13533 , n13534 , n13535 , n13536 , n13537 , n13538 , n13539 , n13540 ,
n13541 , n13542 , n13543 , n13544 , n13545 , n13546 , n13547 , n13548 , n13549 , n13550 ,
n13551 , n13552 , n13553 , n13554 , n13555 , n13556 , n13557 , n13558 , n13559 , n13560 ,
n13561 , n13562 , n13563 , n13564 , n13565 , n13566 , n13567 , n13568 , n13569 , n13570 ,
n13571 , n13572 , n13573 , n13574 , n13575 , n13576 , n13577 , n13578 , n13579 , n13580 ,
n13581 , n13582 , n13583 , n13584 , n13585 , n13586 , n13587 , n13588 , n13589 , n13590 ,
n13591 , n13592 , n13593 , n13594 , n13595 , n13596 , n13597 , n13598 , n13599 , n13600 ,
n13601 , n13602 , n13603 , n13604 , n13605 , n13606 , n13607 , n13608 , n13609 , n13610 ,
n13611 , n13612 , n13613 , n13614 , n13615 , n13616 , n13617 , n13618 , n13619 , n13620 ,
n13621 , n13622 , n13623 , n13624 , n13625 , n13626 , n13627 , n13628 , n13629 , n13630 ,
n13631 , n13632 , n13633 , n13634 , n13635 , n13636 , n13637 , n13638 , n13639 , n13640 ,
n13641 , n13642 , n13643 , n13644 , n13645 , n13646 , n13647 , n13648 , n13649 , n13650 ,
n13651 , n13652 , n13653 , n13654 , n13655 , n13656 , n13657 , n13658 , n13659 , n13660 ,
n13661 , n13662 , n13663 , n13664 , n13665 , n13666 , n13667 , n13668 , n13669 , n13670 ,
n13671 , n13672 , n13673 , n13674 , n13675 , n13676 , n13677 , n13678 , n13679 , n13680 ,
n13681 , n13682 , n13683 , n13684 , n13685 , n13686 , n13687 , n13688 , n13689 , n13690 ,
n13691 , n13692 , n13693 , n13694 , n13695 , n13696 , n13697 , n13698 , n13699 , n13700 ,
n13701 , n13702 , n13703 , n13704 , n13705 , n13706 , n13707 , n13708 , n13709 , n13710 ,
n13711 , n13712 , n13713 , n13714 , n13715 , n13716 , n13717 , n13718 , n13719 , n13720 ,
n13721 , n13722 , n13723 , n13724 , n13725 , n13726 , n13727 , n13728 , n13729 , n13730 ,
n13731 , n13732 , n13733 , n13734 , n13735 , n13736 , n13737 , n13738 , n13739 , n13740 ,
n13741 , n13742 , n13743 , n13744 , n13745 , n13746 , n13747 , n13748 , n13749 , n13750 ,
n13751 , n13752 , n13753 , n13754 , n13755 , n13756 , n13757 , n13758 , n13759 , n13760 ,
n13761 , n13762 , n13763 , n13764 , n13765 , n13766 , n13767 , n13768 , n13769 , n13770 ,
n13771 , n13772 , n13773 , n13774 , n13775 , n13776 , n13777 , n13778 , n13779 , n13780 ,
n13781 , n13782 , n13783 , n13784 , n13785 , n13786 , n13787 , n13788 , n13789 , n13790 ,
n13791 , n13792 , n13793 , n13794 , n13795 , n13796 , n13797 , n13798 , n13799 , n13800 ,
n13801 , n13802 , n13803 , n13804 , n13805 , n13806 , n13807 , n13808 , n13809 , n13810 ,
n13811 , n13812 , n13813 , n13814 , n13815 , n13816 , n13817 , n13818 , n13819 , n13820 ,
n13821 , n13822 , n13823 , n13824 , n13825 , n13826 , n13827 , n13828 , n13829 , n13830 ,
n13831 , n13832 , n13833 , n13834 , n13835 , n13836 , n13837 , n13838 , n13839 , n13840 ,
n13841 , n13842 , n13843 , n13844 , n13845 , n13846 , n13847 , n13848 , n13849 , n13850 ,
n13851 , n13852 , n13853 , n13854 , n13855 , n13856 , n13857 , n13858 , n13859 , n13860 ,
n13861 , n13862 , n13863 , n13864 , n13865 , n13866 , n13867 , n13868 , n13869 , n13870 ,
n13871 , n13872 , n13873 , n13874 , n13875 , n13876 , n13877 , n13878 , n13879 , n13880 ,
n13881 , n13882 , n13883 , n13884 , n13885 , n13886 , n13887 , n13888 , n13889 , n13890 ,
n13891 , n13892 , n13893 , n13894 , n13895 , n13896 , n13897 , n13898 , n13899 , n13900 ,
n13901 , n13902 , n13903 , n13904 , n13905 , n13906 , n13907 , n13908 , n13909 , n13910 ,
n13911 , n13912 , n13913 , n13914 , n13915 , n13916 , n13917 , n13918 , n13919 , n13920 ,
n13921 , n13922 , n13923 , n13924 , n13925 , n13926 , n13927 , n13928 , n13929 , n13930 ,
n13931 , n13932 , n13933 , n13934 , n13935 , n13936 , n13937 , n13938 , n13939 , n13940 ,
n13941 , n13942 , n13943 , n13944 , n13945 , n13946 , n13947 , n13948 , n13949 , n13950 ,
n13951 , n13952 , n13953 , n13954 , n13955 , n13956 , n13957 , n13958 , n13959 , n13960 ,
n13961 , n13962 , n13963 , n13964 , n13965 , n13966 , n13967 , n13968 , n13969 , n13970 ,
n13971 , n13972 , n13973 , n13974 , n13975 , n13976 , n13977 , n13978 , n13979 , n13980 ,
n13981 , n13982 , n13983 , n13984 , n13985 , n13986 , n13987 , n13988 , n13989 , n13990 ,
n13991 , n13992 , n13993 , n13994 , n13995 , n13996 , n13997 , n13998 , n13999 , n14000 ,
n14001 , n14002 , n14003 , n14004 , n14005 , n14006 , n14007 , n14008 , n14009 , n14010 ,
n14011 , n14012 , n14013 , n14014 , n14015 , n14016 , n14017 , n14018 , n14019 , n14020 ,
n14021 , n14022 , n14023 , n14024 , n14025 , n14026 , n14027 , n14028 , n14029 , n14030 ,
n14031 , n14032 , n14033 , n14034 , n14035 , n14036 , n14037 , n14038 , n14039 , n14040 ,
n14041 , n14042 , n14043 , n14044 , n14045 , n14046 , n14047 , n14048 , n14049 , n14050 ,
n14051 , n14052 , n14053 , n14054 , n14055 , n14056 , n14057 , n14058 , n14059 , n14060 ,
n14061 , n14062 , n14063 , n14064 , n14065 , n14066 , n14067 , n14068 , n14069 , n14070 ,
n14071 , n14072 , n14073 , n14074 , n14075 , n14076 , n14077 , n14078 , n14079 , n14080 ,
n14081 , n14082 , n14083 , n14084 , n14085 , n14086 , n14087 , n14088 , n14089 , n14090 ,
n14091 , n14092 , n14093 , n14094 , n14095 , n14096 , n14097 , n14098 , n14099 , n14100 ,
n14101 , n14102 , n14103 , n14104 , n14105 , n14106 , n14107 , n14108 , n14109 , n14110 ,
n14111 , n14112 , n14113 , n14114 , n14115 , n14116 , n14117 , n14118 , n14119 , n14120 ,
n14121 , n14122 , n14123 , n14124 , n14125 , n14126 , n14127 , n14128 , n14129 , n14130 ,
n14131 , n14132 , n14133 , n14134 , n14135 , n14136 , n14137 , n14138 , n14139 , n14140 ,
n14141 , n14142 , n14143 , n14144 , n14145 , n14146 , n14147 , n14148 , n14149 , n14150 ,
n14151 , n14152 , n14153 , n14154 , n14155 , n14156 , n14157 , n14158 , n14159 , n14160 ,
n14161 , n14162 , n14163 , n14164 , n14165 , n14166 , n14167 , n14168 , n14169 , n14170 ,
n14171 , n14172 , n14173 , n14174 , n14175 , n14176 , n14177 , n14178 , n14179 , n14180 ,
n14181 , n14182 , n14183 , n14184 , n14185 , n14186 , n14187 , n14188 , n14189 , n14190 ,
n14191 , n14192 , n14193 , n14194 , n14195 , n14196 , n14197 , n14198 , n14199 , n14200 ,
n14201 , n14202 , n14203 , n14204 , n14205 , n14206 , n14207 , n14208 , n14209 , n14210 ,
n14211 , n14212 , n14213 , n14214 , n14215 , n14216 , n14217 , n14218 , n14219 , n14220 ,
n14221 , n14222 , n14223 , n14224 , n14225 , n14226 , n14227 , n14228 , n14229 , n14230 ,
n14231 , n14232 , n14233 , n14234 , n14235 , n14236 , n14237 , n14238 , n14239 , n14240 ,
n14241 , n14242 , n14243 , n14244 , n14245 , n14246 , n14247 , n14248 , n14249 , n14250 ,
n14251 , n14252 , n14253 , n14254 , n14255 , n14256 , n14257 , n14258 , n14259 , n14260 ,
n14261 , n14262 , n14263 , n14264 , n14265 , n14266 , n14267 , n14268 , n14269 , n14270 ,
n14271 , n14272 , n14273 , n14274 , n14275 , n14276 , n14277 , n14278 , n14279 , n14280 ,
n14281 , n14282 , n14283 , n14284 , n14285 , n14286 , n14287 , n14288 , n14289 , n14290 ,
n14291 , n14292 , n14293 , n14294 , n14295 , n14296 , n14297 , n14298 , n14299 , n14300 ,
n14301 , n14302 , n14303 , n14304 , n14305 , n14306 , n14307 , n14308 , n14309 , n14310 ,
n14311 , n14312 , n14313 , n14314 , n14315 , n14316 , n14317 , n14318 , n14319 , n14320 ,
n14321 , n14322 , n14323 , n14324 , n14325 , n14326 , n14327 , n14328 , n14329 , n14330 ,
n14331 , n14332 , n14333 , n14334 , n14335 , n14336 , n14337 , n14338 , n14339 , n14340 ,
n14341 , n14342 , n14343 , n14344 , n14345 , n14346 , n14347 , n14348 , n14349 , n14350 ,
n14351 , n14352 , n14353 , n14354 , n14355 , n14356 , n14357 , n14358 , n14359 , n14360 ,
n14361 , n14362 , n14363 , n14364 , n14365 , n14366 , n14367 , n14368 , n14369 , n14370 ,
n14371 , n14372 , n14373 , n14374 , n14375 , n14376 , n14377 , n14378 , n14379 , n14380 ,
n14381 , n14382 , n14383 , n14384 , n14385 , n14386 , n14387 , n14388 , n14389 , n14390 ,
n14391 , n14392 , n14393 , n14394 , n14395 , n14396 , n14397 , n14398 , n14399 , n14400 ,
n14401 , n14402 , n14403 , n14404 , n14405 , n14406 , n14407 , n14408 , n14409 , n14410 ,
n14411 , n14412 , n14413 , n14414 , n14415 , n14416 , n14417 , n14418 , n14419 , n14420 ,
n14421 , n14422 , n14423 , n14424 , n14425 , n14426 , n14427 , n14428 , n14429 , n14430 ,
n14431 , n14432 , n14433 , n14434 , n14435 , n14436 , n14437 , n14438 , n14439 , n14440 ,
n14441 , n14442 , n14443 , n14444 , n14445 , n14446 , n14447 , n14448 , n14449 , n14450 ,
n14451 , n14452 , n14453 , n14454 , n14455 , n14456 , n14457 , n14458 , n14459 , n14460 ,
n14461 , n14462 , n14463 , n14464 , n14465 , n14466 , n14467 , n14468 , n14469 , n14470 ,
n14471 , n14472 , n14473 , n14474 , n14475 , n14476 , n14477 , n14478 , n14479 , n14480 ,
n14481 , n14482 , n14483 , n14484 , n14485 , n14486 , n14487 , n14488 , n14489 , n14490 ,
n14491 , n14492 , n14493 , n14494 , n14495 , n14496 , n14497 , n14498 , n14499 , n14500 ,
n14501 , n14502 , n14503 , n14504 , n14505 , n14506 , n14507 , n14508 , n14509 , n14510 ,
n14511 , n14512 , n14513 , n14514 , n14515 , n14516 , n14517 , n14518 , n14519 , n14520 ,
n14521 , n14522 , n14523 , n14524 , n14525 , n14526 , n14527 , n14528 , n14529 , n14530 ,
n14531 , n14532 , n14533 , n14534 , n14535 , n14536 , n14537 , n14538 , n14539 , n14540 ,
n14541 , n14542 , n14543 , n14544 , n14545 , n14546 , n14547 , n14548 , n14549 , n14550 ,
n14551 , n14552 , n14553 , n14554 , n14555 , n14556 , n14557 , n14558 , n14559 , n14560 ,
n14561 , n14562 , n14563 , n14564 , n14565 , n14566 , n14567 , n14568 , n14569 , n14570 ,
n14571 , n14572 , n14573 , n14574 , n14575 , n14576 , n14577 , n14578 , n14579 , n14580 ,
n14581 , n14582 , n14583 , n14584 , n14585 , n14586 , n14587 , n14588 , n14589 , n14590 ,
n14591 , n14592 , n14593 , n14594 , n14595 , n14596 , n14597 , n14598 , n14599 , n14600 ,
n14601 , n14602 , n14603 , n14604 , n14605 , n14606 , n14607 , n14608 , n14609 , n14610 ,
n14611 , n14612 , n14613 , n14614 , n14615 , n14616 , n14617 , n14618 , n14619 , n14620 ,
n14621 , n14622 , n14623 , n14624 , n14625 , n14626 , n14627 , n14628 , n14629 , n14630 ,
n14631 , n14632 , n14633 , n14634 , n14635 , n14636 , n14637 , n14638 , n14639 , n14640 ,
n14641 , n14642 , n14643 , n14644 , n14645 , n14646 , n14647 , n14648 , n14649 , n14650 ,
n14651 , n14652 , n14653 , n14654 , n14655 , n14656 , n14657 , n14658 , n14659 , n14660 ,
n14661 , n14662 , n14663 , n14664 , n14665 , n14666 , n14667 , n14668 , n14669 , n14670 ,
n14671 , n14672 , n14673 , n14674 , n14675 , n14676 , n14677 , n14678 , n14679 , n14680 ,
n14681 , n14682 , n14683 , n14684 , n14685 , n14686 , n14687 , n14688 , n14689 , n14690 ,
n14691 , n14692 , n14693 , n14694 , n14695 , n14696 , n14697 , n14698 , n14699 , n14700 ,
n14701 , n14702 , n14703 , n14704 , n14705 , n14706 , n14707 , n14708 , n14709 , n14710 ,
n14711 , n14712 , n14713 , n14714 , n14715 , n14716 , n14717 , n14718 , n14719 , n14720 ,
n14721 , n14722 , n14723 , n14724 , n14725 , n14726 , n14727 , n14728 , n14729 , n14730 ,
n14731 , n14732 , n14733 , n14734 , n14735 , n14736 , n14737 , n14738 , n14739 , n14740 ,
n14741 , n14742 , n14743 , n14744 , n14745 , n14746 , n14747 , n14748 , n14749 , n14750 ,
n14751 , n14752 , n14753 , n14754 , n14755 , n14756 , n14757 , n14758 , n14759 , n14760 ,
n14761 , n14762 , n14763 , n14764 , n14765 , n14766 , n14767 , n14768 , n14769 , n14770 ,
n14771 , n14772 , n14773 , n14774 , n14775 , n14776 , n14777 , n14778 , n14779 , n14780 ,
n14781 , n14782 , n14783 , n14784 , n14785 , n14786 , n14787 , n14788 , n14789 , n14790 ,
n14791 , n14792 , n14793 , n14794 , n14795 , n14796 , n14797 , n14798 , n14799 , n14800 ,
n14801 , n14802 , n14803 , n14804 , n14805 , n14806 , n14807 , n14808 , n14809 , n14810 ,
n14811 , n14812 , n14813 , n14814 , n14815 , n14816 , n14817 , n14818 , n14819 , n14820 ,
n14821 , n14822 , n14823 , n14824 , n14825 , n14826 , n14827 , n14828 , n14829 , n14830 ,
n14831 , n14832 , n14833 , n14834 , n14835 , n14836 , n14837 , n14838 , n14839 , n14840 ,
n14841 , n14842 , n14843 , n14844 , n14845 , n14846 , n14847 , n14848 , n14849 , n14850 ,
n14851 , n14852 , n14853 , n14854 , n14855 , n14856 , n14857 , n14858 , n14859 , n14860 ,
n14861 , n14862 , n14863 , n14864 , n14865 , n14866 , n14867 , n14868 , n14869 , n14870 ,
n14871 , n14872 , n14873 , n14874 , n14875 , n14876 , n14877 , n14878 , n14879 , n14880 ,
n14881 , n14882 , n14883 , n14884 , n14885 , n14886 , n14887 , n14888 , n14889 , n14890 ,
n14891 , n14892 , n14893 , n14894 , n14895 , n14896 , n14897 , n14898 , n14899 , n14900 ,
n14901 , n14902 , n14903 , n14904 , n14905 , n14906 , n14907 , n14908 , n14909 , n14910 ,
n14911 , n14912 , n14913 , n14914 , n14915 , n14916 , n14917 , n14918 , n14919 , n14920 ,
n14921 , n14922 , n14923 , n14924 , n14925 , n14926 , n14927 , n14928 , n14929 , n14930 ,
n14931 , n14932 , n14933 , n14934 , n14935 , n14936 , n14937 , n14938 , n14939 , n14940 ,
n14941 , n14942 , n14943 , n14944 , n14945 , n14946 , n14947 , n14948 , n14949 , n14950 ,
n14951 , n14952 , n14953 , n14954 , n14955 , n14956 , n14957 , n14958 , n14959 , n14960 ,
n14961 , n14962 , n14963 , n14964 , n14965 , n14966 , n14967 , n14968 , n14969 , n14970 ,
n14971 , n14972 , n14973 , n14974 , n14975 , n14976 , n14977 , n14978 , n14979 , n14980 ,
n14981 , n14982 , n14983 , n14984 , n14985 , n14986 , n14987 , n14988 , n14989 , n14990 ,
n14991 , n14992 , n14993 , n14994 , n14995 , n14996 , n14997 , n14998 , n14999 , n15000 ,
n15001 , n15002 , n15003 , n15004 , n15005 , n15006 , n15007 , n15008 , n15009 , n15010 ,
n15011 , n15012 , n15013 , n15014 , n15015 , n15016 , n15017 , n15018 , n15019 , n15020 ,
n15021 , n15022 , n15023 , n15024 , n15025 , n15026 , n15027 , n15028 , n15029 , n15030 ,
n15031 , n15032 , n15033 , n15034 , n15035 , n15036 , n15037 , n15038 , n15039 , n15040 ,
n15041 , n15042 , n15043 , n15044 , n15045 , n15046 , n15047 , n15048 , n15049 , n15050 ,
n15051 , n15052 , n15053 , n15054 , n15055 , n15056 , n15057 , n15058 , n15059 , n15060 ,
n15061 , n15062 , n15063 , n15064 , n15065 , n15066 , n15067 , n15068 , n15069 , n15070 ,
n15071 , n15072 , n15073 , n15074 , n15075 , n15076 , n15077 , n15078 , n15079 , n15080 ,
n15081 , n15082 , n15083 , n15084 , n15085 , n15086 , n15087 , n15088 , n15089 , n15090 ,
n15091 , n15092 , n15093 , n15094 , n15095 , n15096 , n15097 , n15098 , n15099 , n15100 ,
n15101 , n15102 , n15103 , n15104 , n15105 , n15106 , n15107 , n15108 , n15109 , n15110 ,
n15111 , n15112 , n15113 , n15114 , n15115 , n15116 , n15117 , n15118 , n15119 , n15120 ,
n15121 , n15122 , n15123 , n15124 , n15125 , n15126 , n15127 , n15128 , n15129 , n15130 ,
n15131 , n15132 , n15133 , n15134 , n15135 , n15136 , n15137 , n15138 , n15139 , n15140 ,
n15141 , n15142 , n15143 , n15144 , n15145 , n15146 , n15147 , n15148 , n15149 , n15150 ,
n15151 , n15152 , n15153 , n15154 , n15155 , n15156 , n15157 , n15158 , n15159 , n15160 ,
n15161 , n15162 , n15163 , n15164 , n15165 , n15166 , n15167 , n15168 , n15169 , n15170 ,
n15171 , n15172 , n15173 , n15174 , n15175 , n15176 , n15177 , n15178 , n15179 , n15180 ,
n15181 , n15182 , n15183 , n15184 , n15185 , n15186 , n15187 , n15188 , n15189 , n15190 ,
n15191 , n15192 , n15193 , n15194 , n15195 , n15196 , n15197 , n15198 , n15199 , n15200 ,
n15201 , n15202 , n15203 , n15204 , n15205 , n15206 , n15207 , n15208 , n15209 , n15210 ,
n15211 , n15212 , n15213 , n15214 , n15215 , n15216 , n15217 , n15218 , n15219 , n15220 ,
n15221 , n15222 , n15223 , n15224 , n15225 , n15226 , n15227 , n15228 , n15229 , n15230 ,
n15231 , n15232 , n15233 , n15234 , n15235 , n15236 , n15237 , n15238 , n15239 , n15240 ,
n15241 , n15242 , n15243 , n15244 , n15245 , n15246 , n15247 , n15248 , n15249 , n15250 ,
n15251 , n15252 , n15253 , n15254 , n15255 , n15256 , n15257 , n15258 , n15259 , n15260 ,
n15261 , n15262 , n15263 , n15264 , n15265 , n15266 , n15267 , n15268 , n15269 , n15270 ,
n15271 , n15272 , n15273 , n15274 , n15275 , n15276 , n15277 , n15278 , n15279 , n15280 ,
n15281 , n15282 , n15283 , n15284 , n15285 , n15286 , n15287 , n15288 , n15289 , n15290 ,
n15291 , n15292 , n15293 , n15294 , n15295 , n15296 , n15297 , n15298 , n15299 , n15300 ,
n15301 , n15302 , n15303 , n15304 , n15305 , n15306 , n15307 , n15308 , n15309 , n15310 ,
n15311 , n15312 , n15313 , n15314 , n15315 , n15316 , n15317 , n15318 , n15319 , n15320 ,
n15321 , n15322 , n15323 , n15324 , n15325 , n15326 , n15327 , n15328 , n15329 , n15330 ,
n15331 , n15332 , n15333 , n15334 , n15335 , n15336 , n15337 , n15338 , n15339 , n15340 ,
n15341 , n15342 , n15343 , n15344 , n15345 , n15346 , n15347 , n15348 , n15349 , n15350 ,
n15351 , n15352 , n15353 , n15354 , n15355 , n15356 , n15357 , n15358 , n15359 , n15360 ,
n15361 , n15362 , n15363 , n15364 , n15365 , n15366 , n15367 , n15368 , n15369 , n15370 ,
n15371 , n15372 , n15373 , n15374 , n15375 , n15376 , n15377 , n15378 , n15379 , n15380 ,
n15381 , n15382 , n15383 , n15384 , n15385 , n15386 , n15387 , n15388 , n15389 , n15390 ,
n15391 , n15392 , n15393 , n15394 , n15395 , n15396 , n15397 , n15398 , n15399 , n15400 ,
n15401 , n15402 , n15403 , n15404 , n15405 , n15406 , n15407 , n15408 , n15409 , n15410 ,
n15411 , n15412 , n15413 , n15414 , n15415 , n15416 , n15417 , n15418 , n15419 , n15420 ,
n15421 , n15422 , n15423 , n15424 , n15425 , n15426 , n15427 , n15428 , n15429 , n15430 ,
n15431 , n15432 , n15433 , n15434 , n15435 , n15436 , n15437 , n15438 , n15439 , n15440 ,
n15441 , n15442 , n15443 , n15444 , n15445 , n15446 , n15447 , n15448 , n15449 , n15450 ,
n15451 , n15452 , n15453 , n15454 , n15455 , n15456 , n15457 , n15458 , n15459 , n15460 ,
n15461 , n15462 , n15463 , n15464 , n15465 , n15466 , n15467 , n15468 , n15469 , n15470 ,
n15471 , n15472 , n15473 , n15474 , n15475 , n15476 , n15477 , n15478 , n15479 , n15480 ,
n15481 , n15482 , n15483 , n15484 , n15485 , n15486 , n15487 , n15488 , n15489 , n15490 ,
n15491 , n15492 , n15493 , n15494 , n15495 , n15496 , n15497 , n15498 , n15499 , n15500 ,
n15501 , n15502 , n15503 , n15504 , n15505 , n15506 , n15507 , n15508 , n15509 , n15510 ,
n15511 , n15512 , n15513 , n15514 , n15515 , n15516 , n15517 , n15518 , n15519 , n15520 ,
n15521 , n15522 , n15523 , n15524 , n15525 , n15526 , n15527 , n15528 , n15529 , n15530 ,
n15531 , n15532 , n15533 , n15534 , n15535 , n15536 , n15537 , n15538 , n15539 , n15540 ,
n15541 , n15542 , n15543 , n15544 , n15545 , n15546 , n15547 , n15548 , n15549 , n15550 ,
n15551 , n15552 , n15553 , n15554 , n15555 , n15556 , n15557 , n15558 , n15559 , n15560 ,
n15561 , n15562 , n15563 , n15564 , n15565 , n15566 , n15567 , n15568 , n15569 , n15570 ,
n15571 , n15572 , n15573 , n15574 , n15575 , n15576 , n15577 , n15578 , n15579 , n15580 ,
n15581 , n15582 , n15583 , n15584 , n15585 , n15586 , n15587 , n15588 , n15589 , n15590 ,
n15591 , n15592 , n15593 , n15594 , n15595 , n15596 , n15597 , n15598 , n15599 , n15600 ,
n15601 , n15602 , n15603 , n15604 , n15605 , n15606 , n15607 , n15608 , n15609 , n15610 ,
n15611 , n15612 , n15613 , n15614 , n15615 , n15616 , n15617 , n15618 , n15619 , n15620 ,
n15621 , n15622 , n15623 , n15624 , n15625 , n15626 , n15627 , n15628 , n15629 , n15630 ,
n15631 , n15632 , n15633 , n15634 , n15635 , n15636 , n15637 , n15638 , n15639 , n15640 ,
n15641 , n15642 , n15643 , n15644 , n15645 , n15646 , n15647 , n15648 , n15649 , n15650 ,
n15651 , n15652 , n15653 , n15654 , n15655 , n15656 , n15657 , n15658 , n15659 , n15660 ,
n15661 , n15662 , n15663 , n15664 , n15665 , n15666 , n15667 , n15668 , n15669 , n15670 ,
n15671 , n15672 , n15673 , n15674 , n15675 , n15676 , n15677 , n15678 , n15679 , n15680 ,
n15681 , n15682 , n15683 , n15684 , n15685 , n15686 , n15687 , n15688 , n15689 , n15690 ,
n15691 , n15692 , n15693 , n15694 , n15695 , n15696 , n15697 , n15698 , n15699 , n15700 ,
n15701 , n15702 , n15703 , n15704 , n15705 , n15706 , n15707 , n15708 , n15709 , n15710 ,
n15711 , n15712 , n15713 , n15714 , n15715 , n15716 , n15717 , n15718 , n15719 , n15720 ,
n15721 , n15722 , n15723 , n15724 , n15725 , n15726 , n15727 , n15728 , n15729 , n15730 ,
n15731 , n15732 , n15733 , n15734 , n15735 , n15736 , n15737 , n15738 , n15739 , n15740 ,
n15741 , n15742 , n15743 , n15744 , n15745 , n15746 , n15747 , n15748 , n15749 , n15750 ,
n15751 , n15752 , n15753 , n15754 , n15755 , n15756 , n15757 , n15758 , n15759 , n15760 ,
n15761 , n15762 , n15763 , n15764 , n15765 , n15766 , n15767 , n15768 , n15769 , n15770 ,
n15771 , n15772 , n15773 , n15774 , n15775 , n15776 , n15777 , n15778 , n15779 , n15780 ,
n15781 , n15782 , n15783 , n15784 , n15785 , n15786 , n15787 , n15788 , n15789 , n15790 ,
n15791 , n15792 , n15793 , n15794 , n15795 , n15796 , n15797 , n15798 , n15799 , n15800 ,
n15801 , n15802 , n15803 , n15804 , n15805 , n15806 , n15807 , n15808 , n15809 , n15810 ,
n15811 , n15812 , n15813 , n15814 , n15815 , n15816 , n15817 , n15818 , n15819 , n15820 ,
n15821 , n15822 , n15823 , n15824 , n15825 , n15826 , n15827 , n15828 , n15829 , n15830 ,
n15831 , n15832 , n15833 , n15834 , n15835 , n15836 , n15837 , n15838 , n15839 , n15840 ,
n15841 , n15842 , n15843 , n15844 , n15845 , n15846 , n15847 , n15848 , n15849 , n15850 ,
n15851 , n15852 , n15853 , n15854 , n15855 , n15856 , n15857 , n15858 , n15859 , n15860 ,
n15861 , n15862 , n15863 , n15864 , n15865 , n15866 , n15867 , n15868 , n15869 , n15870 ,
n15871 , n15872 , n15873 , n15874 , n15875 , n15876 , n15877 , n15878 , n15879 , n15880 ,
n15881 , n15882 , n15883 , n15884 , n15885 , n15886 , n15887 , n15888 , n15889 , n15890 ,
n15891 , n15892 , n15893 , n15894 , n15895 , n15896 , n15897 , n15898 , n15899 , n15900 ,
n15901 , n15902 , n15903 , n15904 , n15905 , n15906 , n15907 , n15908 , n15909 , n15910 ,
n15911 , n15912 , n15913 , n15914 , n15915 , n15916 , n15917 , n15918 , n15919 , n15920 ,
n15921 , n15922 , n15923 , n15924 , n15925 , n15926 , n15927 , n15928 , n15929 , n15930 ,
n15931 , n15932 , n15933 , n15934 , n15935 , n15936 , n15937 , n15938 , n15939 , n15940 ,
n15941 , n15942 , n15943 , n15944 , n15945 , n15946 , n15947 , n15948 , n15949 , n15950 ,
n15951 , n15952 , n15953 , n15954 , n15955 , n15956 , n15957 , n15958 , n15959 , n15960 ,
n15961 , n15962 , n15963 , n15964 , n15965 , n15966 , n15967 , n15968 , n15969 , n15970 ,
n15971 , n15972 , n15973 , n15974 , n15975 , n15976 , n15977 , n15978 , n15979 , n15980 ,
n15981 , n15982 , n15983 , n15984 , n15985 , n15986 , n15987 , n15988 , n15989 , n15990 ,
n15991 , n15992 , n15993 , n15994 , n15995 , n15996 , n15997 , n15998 , n15999 , n16000 ,
n16001 , n16002 , n16003 , n16004 , n16005 , n16006 , n16007 , n16008 , n16009 , n16010 ,
n16011 , n16012 , n16013 , n16014 , n16015 , n16016 , n16017 , n16018 , n16019 , n16020 ,
n16021 , n16022 , n16023 , n16024 , n16025 , n16026 , n16027 , n16028 , n16029 , n16030 ,
n16031 , n16032 , n16033 , n16034 , n16035 , n16036 , n16037 , n16038 , n16039 , n16040 ,
n16041 , n16042 , n16043 , n16044 , n16045 , n16046 , n16047 , n16048 , n16049 , n16050 ,
n16051 , n16052 , n16053 , n16054 , n16055 , n16056 , n16057 , n16058 , n16059 , n16060 ,
n16061 , n16062 , n16063 , n16064 , n16065 , n16066 , n16067 , n16068 , n16069 , n16070 ,
n16071 , n16072 , n16073 , n16074 , n16075 , n16076 , n16077 , n16078 , n16079 , n16080 ,
n16081 , n16082 , n16083 , n16084 , n16085 , n16086 , n16087 , n16088 , n16089 , n16090 ,
n16091 , n16092 , n16093 , n16094 , n16095 , n16096 , n16097 , n16098 , n16099 , n16100 ,
n16101 , n16102 , n16103 , n16104 , n16105 , n16106 , n16107 , n16108 , n16109 , n16110 ,
n16111 , n16112 , n16113 , n16114 , n16115 , n16116 , n16117 , n16118 , n16119 , n16120 ,
n16121 , n16122 , n16123 , n16124 , n16125 , n16126 , n16127 , n16128 , n16129 , n16130 ,
n16131 , n16132 , n16133 , n16134 , n16135 , n16136 , n16137 , n16138 , n16139 , n16140 ,
n16141 , n16142 , n16143 , n16144 , n16145 , n16146 , n16147 , n16148 , n16149 , n16150 ,
n16151 , n16152 , n16153 , n16154 , n16155 , n16156 , n16157 , n16158 , n16159 , n16160 ,
n16161 , n16162 , n16163 , n16164 , n16165 , n16166 , n16167 , n16168 , n16169 , n16170 ,
n16171 , n16172 , n16173 , n16174 , n16175 , n16176 , n16177 , n16178 , n16179 , n16180 ,
n16181 , n16182 , n16183 , n16184 , n16185 , n16186 , n16187 , n16188 , n16189 , n16190 ,
n16191 , n16192 , n16193 , n16194 , n16195 , n16196 , n16197 , n16198 , n16199 , n16200 ,
n16201 , n16202 , n16203 , n16204 , n16205 , n16206 , n16207 , n16208 , n16209 , n16210 ,
n16211 , n16212 , n16213 , n16214 , n16215 , n16216 , n16217 , n16218 , n16219 , n16220 ,
n16221 , n16222 , n16223 , n16224 , n16225 , n16226 , n16227 , n16228 , n16229 , n16230 ,
n16231 , n16232 , n16233 , n16234 , n16235 , n16236 , n16237 , n16238 , n16239 , n16240 ,
n16241 , n16242 , n16243 , n16244 , n16245 , n16246 , n16247 , n16248 , n16249 , n16250 ,
n16251 , n16252 , n16253 , n16254 , n16255 , n16256 , n16257 , n16258 , n16259 , n16260 ,
n16261 , n16262 , n16263 , n16264 , n16265 , n16266 , n16267 , n16268 , n16269 , n16270 ,
n16271 , n16272 , n16273 , n16274 , n16275 , n16276 , n16277 , n16278 , n16279 , n16280 ,
n16281 , n16282 , n16283 , n16284 , n16285 , n16286 , n16287 , n16288 , n16289 , n16290 ,
n16291 , n16292 , n16293 , n16294 , n16295 , n16296 , n16297 , n16298 , n16299 , n16300 ,
n16301 , n16302 , n16303 , n16304 , n16305 , n16306 , n16307 , n16308 , n16309 , n16310 ,
n16311 , n16312 , n16313 , n16314 , n16315 , n16316 , n16317 , n16318 , n16319 , n16320 ,
n16321 , n16322 , n16323 , n16324 , n16325 , n16326 , n16327 , n16328 , n16329 , n16330 ,
n16331 , n16332 , n16333 , n16334 , n16335 , n16336 , n16337 , n16338 , n16339 , n16340 ,
n16341 , n16342 , n16343 , n16344 , n16345 , n16346 , n16347 , n16348 , n16349 , n16350 ,
n16351 , n16352 , n16353 , n16354 , n16355 , n16356 , n16357 , n16358 , n16359 , n16360 ,
n16361 , n16362 , n16363 , n16364 , n16365 , n16366 , n16367 , n16368 , n16369 , n16370 ,
n16371 , n16372 , n16373 , n16374 , n16375 , n16376 , n16377 , n16378 , n16379 , n16380 ,
n16381 , n16382 , n16383 , n16384 , n16385 , n16386 , n16387 , n16388 , n16389 , n16390 ,
n16391 , n16392 , n16393 , n16394 , n16395 , n16396 , n16397 , n16398 , n16399 , n16400 ,
n16401 , n16402 , n16403 , n16404 , n16405 , n16406 , n16407 , n16408 , n16409 , n16410 ,
n16411 , n16412 , n16413 , n16414 , n16415 , n16416 , n16417 , n16418 , n16419 , n16420 ,
n16421 , n16422 , n16423 , n16424 , n16425 , n16426 , n16427 , n16428 , n16429 , n16430 ,
n16431 , n16432 , n16433 , n16434 , n16435 , n16436 , n16437 , n16438 , n16439 , n16440 ,
n16441 , n16442 , n16443 , n16444 , n16445 , n16446 , n16447 , n16448 , n16449 , n16450 ,
n16451 , n16452 , n16453 , n16454 , n16455 , n16456 , n16457 , n16458 , n16459 , n16460 ,
n16461 , n16462 , n16463 , n16464 , n16465 , n16466 , n16467 , n16468 , n16469 , n16470 ,
n16471 , n16472 , n16473 , n16474 , n16475 , n16476 , n16477 , n16478 , n16479 , n16480 ,
n16481 , n16482 , n16483 , n16484 , n16485 , n16486 , n16487 , n16488 , n16489 , n16490 ,
n16491 , n16492 , n16493 , n16494 , n16495 , n16496 , n16497 , n16498 , n16499 , n16500 ,
n16501 , n16502 , n16503 , n16504 , n16505 , n16506 , n16507 , n16508 , n16509 , n16510 ,
n16511 , n16512 , n16513 , n16514 , n16515 , n16516 , n16517 , n16518 , n16519 , n16520 ,
n16521 , n16522 , n16523 , n16524 , n16525 , n16526 , n16527 , n16528 , n16529 , n16530 ,
n16531 , n16532 , n16533 , n16534 , n16535 , n16536 , n16537 , n16538 , n16539 , n16540 ,
n16541 , n16542 , n16543 , n16544 , n16545 , n16546 , n16547 , n16548 , n16549 , n16550 ,
n16551 , n16552 , n16553 , n16554 , n16555 , n16556 , n16557 , n16558 , n16559 , n16560 ,
n16561 , n16562 , n16563 , n16564 , n16565 , n16566 , n16567 , n16568 , n16569 , n16570 ,
n16571 , n16572 , n16573 , n16574 , n16575 , n16576 , n16577 , n16578 , n16579 , n16580 ,
n16581 , n16582 , n16583 , n16584 , n16585 , n16586 , n16587 , n16588 , n16589 , n16590 ,
n16591 , n16592 , n16593 , n16594 , n16595 , n16596 , n16597 , n16598 , n16599 , n16600 ,
n16601 , n16602 , n16603 , n16604 , n16605 , n16606 , n16607 , n16608 , n16609 , n16610 ,
n16611 , n16612 , n16613 , n16614 , n16615 , n16616 , n16617 , n16618 , n16619 , n16620 ,
n16621 , n16622 , n16623 , n16624 , n16625 , n16626 , n16627 , n16628 , n16629 , n16630 ,
n16631 , n16632 , n16633 , n16634 , n16635 , n16636 , n16637 , n16638 , n16639 , n16640 ,
n16641 , n16642 , n16643 , n16644 , n16645 , n16646 , n16647 , n16648 , n16649 , n16650 ,
n16651 , n16652 , n16653 , n16654 , n16655 , n16656 , n16657 , n16658 , n16659 , n16660 ,
n16661 , n16662 , n16663 , n16664 , n16665 , n16666 , n16667 , n16668 , n16669 , n16670 ,
n16671 , n16672 , n16673 , n16674 , n16675 , n16676 , n16677 , n16678 , n16679 , n16680 ,
n16681 , n16682 , n16683 , n16684 , n16685 , n16686 , n16687 , n16688 , n16689 , n16690 ,
n16691 , n16692 , n16693 , n16694 , n16695 , n16696 , n16697 , n16698 , n16699 , n16700 ,
n16701 , n16702 , n16703 , n16704 , n16705 , n16706 , n16707 , n16708 , n16709 , n16710 ,
n16711 , n16712 , n16713 , n16714 , n16715 , n16716 , n16717 , n16718 , n16719 , n16720 ,
n16721 , n16722 , n16723 , n16724 , n16725 , n16726 , n16727 , n16728 , n16729 , n16730 ,
n16731 , n16732 , n16733 , n16734 , n16735 , n16736 , n16737 , n16738 , n16739 , n16740 ,
n16741 , n16742 , n16743 , n16744 , n16745 , n16746 , n16747 , n16748 , n16749 , n16750 ,
n16751 , n16752 , n16753 , n16754 , n16755 , n16756 , n16757 , n16758 , n16759 , n16760 ,
n16761 , n16762 , n16763 , n16764 , n16765 , n16766 , n16767 , n16768 , n16769 , n16770 ,
n16771 , n16772 , n16773 , n16774 , n16775 , n16776 , n16777 , n16778 , n16779 , n16780 ,
n16781 , n16782 , n16783 , n16784 , n16785 , n16786 , n16787 , n16788 , n16789 , n16790 ,
n16791 , n16792 , n16793 , n16794 , n16795 , n16796 , n16797 , n16798 , n16799 , n16800 ,
n16801 , n16802 , n16803 , n16804 , n16805 , n16806 , n16807 , n16808 , n16809 , n16810 ,
n16811 , n16812 , n16813 , n16814 , n16815 , n16816 , n16817 , n16818 , n16819 , n16820 ,
n16821 , n16822 , n16823 , n16824 , n16825 , n16826 , n16827 , n16828 , n16829 , n16830 ,
n16831 , n16832 , n16833 , n16834 , n16835 , n16836 , n16837 , n16838 , n16839 , n16840 ,
n16841 , n16842 , n16843 , n16844 , n16845 , n16846 , n16847 , n16848 , n16849 , n16850 ,
n16851 , n16852 , n16853 , n16854 , n16855 , n16856 , n16857 , n16858 , n16859 , n16860 ,
n16861 , n16862 , n16863 , n16864 , n16865 , n16866 , n16867 , n16868 , n16869 , n16870 ,
n16871 , n16872 , n16873 , n16874 , n16875 , n16876 , n16877 , n16878 , n16879 , n16880 ,
n16881 , n16882 , n16883 , n16884 , n16885 , n16886 , n16887 , n16888 , n16889 , n16890 ,
n16891 , n16892 , n16893 , n16894 , n16895 , n16896 , n16897 , n16898 , n16899 , n16900 ,
n16901 , n16902 , n16903 , n16904 , n16905 , n16906 , n16907 , n16908 , n16909 , n16910 ,
n16911 , n16912 , n16913 , n16914 , n16915 , n16916 , n16917 , n16918 , n16919 , n16920 ,
n16921 , n16922 , n16923 , n16924 , n16925 , n16926 , n16927 , n16928 , n16929 , n16930 ,
n16931 , n16932 , n16933 , n16934 , n16935 , n16936 , n16937 , n16938 , n16939 , n16940 ,
n16941 , n16942 , n16943 , n16944 , n16945 , n16946 , n16947 , n16948 , n16949 , n16950 ,
n16951 , n16952 , n16953 , n16954 , n16955 , n16956 , n16957 , n16958 , n16959 , n16960 ,
n16961 , n16962 , n16963 , n16964 , n16965 , n16966 , n16967 , n16968 , n16969 , n16970 ,
n16971 , n16972 , n16973 , n16974 , n16975 , n16976 , n16977 , n16978 , n16979 , n16980 ,
n16981 , n16982 , n16983 , n16984 , n16985 , n16986 , n16987 , n16988 , n16989 , n16990 ,
n16991 , n16992 , n16993 , n16994 , n16995 , n16996 , n16997 , n16998 , n16999 , n17000 ,
n17001 , n17002 , n17003 , n17004 , n17005 , n17006 , n17007 , n17008 , n17009 , n17010 ,
n17011 , n17012 , n17013 , n17014 , n17015 , n17016 , n17017 , n17018 , n17019 , n17020 ,
n17021 , n17022 , n17023 , n17024 , n17025 , n17026 , n17027 , n17028 , n17029 , n17030 ,
n17031 , n17032 , n17033 , n17034 , n17035 , n17036 , n17037 , n17038 , n17039 , n17040 ,
n17041 , n17042 , n17043 , n17044 , n17045 , n17046 , n17047 , n17048 , n17049 , n17050 ,
n17051 , n17052 , n17053 , n17054 , n17055 , n17056 , n17057 , n17058 , n17059 , n17060 ,
n17061 , n17062 , n17063 , n17064 , n17065 , n17066 , n17067 , n17068 , n17069 , n17070 ,
n17071 , n17072 , n17073 , n17074 , n17075 , n17076 , n17077 , n17078 , n17079 , n17080 ,
n17081 , n17082 , n17083 , n17084 , n17085 , n17086 , n17087 , n17088 , n17089 , n17090 ,
n17091 , n17092 , n17093 , n17094 , n17095 , n17096 , n17097 , n17098 , n17099 , n17100 ,
n17101 , n17102 , n17103 , n17104 , n17105 , n17106 , n17107 , n17108 , n17109 , n17110 ,
n17111 , n17112 , n17113 , n17114 , n17115 , n17116 , n17117 , n17118 , n17119 , n17120 ,
n17121 , n17122 , n17123 , n17124 , n17125 , n17126 , n17127 , n17128 , n17129 , n17130 ,
n17131 , n17132 , n17133 , n17134 , n17135 , n17136 , n17137 , n17138 , n17139 , n17140 ,
n17141 , n17142 , n17143 , n17144 , n17145 , n17146 , n17147 , n17148 , n17149 , n17150 ,
n17151 , n17152 , n17153 , n17154 , n17155 , n17156 , n17157 , n17158 , n17159 , n17160 ,
n17161 , n17162 , n17163 , n17164 , n17165 , n17166 , n17167 , n17168 , n17169 , n17170 ,
n17171 , n17172 , n17173 , n17174 , n17175 , n17176 , n17177 , n17178 , n17179 , n17180 ,
n17181 , n17182 , n17183 , n17184 , n17185 , n17186 , n17187 , n17188 , n17189 , n17190 ,
n17191 , n17192 , n17193 , n17194 , n17195 , n17196 , n17197 , n17198 , n17199 , n17200 ,
n17201 , n17202 , n17203 , n17204 , n17205 , n17206 , n17207 , n17208 , n17209 , n17210 ,
n17211 , n17212 , n17213 , n17214 , n17215 , n17216 , n17217 , n17218 , n17219 , n17220 ,
n17221 , n17222 , n17223 , n17224 , n17225 , n17226 , n17227 , n17228 , n17229 , n17230 ,
n17231 , n17232 , n17233 , n17234 , n17235 , n17236 , n17237 , n17238 , n17239 , n17240 ,
n17241 , n17242 , n17243 , n17244 , n17245 , n17246 , n17247 , n17248 , n17249 , n17250 ,
n17251 , n17252 , n17253 , n17254 , n17255 , n17256 , n17257 , n17258 , n17259 , n17260 ,
n17261 , n17262 , n17263 , n17264 , n17265 , n17266 , n17267 , n17268 , n17269 , n17270 ,
n17271 , n17272 , n17273 , n17274 , n17275 , n17276 , n17277 , n17278 , n17279 , n17280 ,
n17281 , n17282 , n17283 , n17284 , n17285 , n17286 , n17287 , n17288 , n17289 , n17290 ,
n17291 , n17292 , n17293 , n17294 , n17295 , n17296 , n17297 , n17298 , n17299 , n17300 ,
n17301 , n17302 , n17303 , n17304 , n17305 , n17306 , n17307 , n17308 , n17309 , n17310 ,
n17311 , n17312 , n17313 , n17314 , n17315 , n17316 , n17317 , n17318 , n17319 , n17320 ,
n17321 , n17322 , n17323 , n17324 , n17325 , n17326 , n17327 , n17328 , n17329 , n17330 ,
n17331 , n17332 , n17333 , n17334 , n17335 , n17336 , n17337 , n17338 , n17339 , n17340 ,
n17341 , n17342 , n17343 , n17344 , n17345 , n17346 , n17347 , n17348 , n17349 , n17350 ,
n17351 , n17352 , n17353 , n17354 , n17355 , n17356 , n17357 , n17358 , n17359 , n17360 ,
n17361 , n17362 , n17363 , n17364 , n17365 , n17366 , n17367 , n17368 , n17369 , n17370 ,
n17371 , n17372 , n17373 , n17374 , n17375 , n17376 , n17377 , n17378 , n17379 , n17380 ,
n17381 , n17382 , n17383 , n17384 , n17385 , n17386 , n17387 , n17388 , n17389 , n17390 ,
n17391 , n17392 , n17393 , n17394 , n17395 , n17396 , n17397 , n17398 , n17399 , n17400 ,
n17401 , n17402 , n17403 , n17404 , n17405 , n17406 , n17407 , n17408 , n17409 , n17410 ,
n17411 , n17412 , n17413 , n17414 , n17415 , n17416 , n17417 , n17418 , n17419 , n17420 ,
n17421 , n17422 , n17423 , n17424 , n17425 , n17426 , n17427 , n17428 , n17429 , n17430 ,
n17431 , n17432 , n17433 , n17434 , n17435 , n17436 , n17437 , n17438 , n17439 , n17440 ,
n17441 , n17442 , n17443 , n17444 , n17445 , n17446 , n17447 , n17448 , n17449 , n17450 ,
n17451 , n17452 , n17453 , n17454 , n17455 , n17456 , n17457 , n17458 , n17459 , n17460 ,
n17461 , n17462 , n17463 , n17464 , n17465 , n17466 , n17467 , n17468 , n17469 , n17470 ,
n17471 , n17472 , n17473 , n17474 , n17475 , n17476 , n17477 , n17478 , n17479 , n17480 ,
n17481 , n17482 , n17483 , n17484 , n17485 , n17486 , n17487 , n17488 , n17489 , n17490 ,
n17491 , n17492 , n17493 , n17494 , n17495 , n17496 , n17497 , n17498 , n17499 , n17500 ,
n17501 , n17502 , n17503 , n17504 , n17505 , n17506 , n17507 , n17508 , n17509 , n17510 ,
n17511 , n17512 , n17513 , n17514 , n17515 , n17516 , n17517 , n17518 , n17519 , n17520 ,
n17521 , n17522 , n17523 , n17524 , n17525 , n17526 , n17527 , n17528 , n17529 , n17530 ,
n17531 , n17532 , n17533 , n17534 , n17535 , n17536 , n17537 , n17538 , n17539 , n17540 ,
n17541 , n17542 , n17543 , n17544 , n17545 , n17546 , n17547 , n17548 , n17549 , n17550 ,
n17551 , n17552 , n17553 , n17554 , n17555 , n17556 , n17557 , n17558 , n17559 , n17560 ,
n17561 , n17562 , n17563 , n17564 , n17565 , n17566 , n17567 , n17568 , n17569 , n17570 ,
n17571 , n17572 , n17573 , n17574 , n17575 , n17576 , n17577 , n17578 , n17579 , n17580 ,
n17581 , n17582 , n17583 , n17584 , n17585 , n17586 , n17587 , n17588 , n17589 , n17590 ,
n17591 , n17592 , n17593 , n17594 , n17595 , n17596 , n17597 , n17598 , n17599 , n17600 ,
n17601 , n17602 , n17603 , n17604 , n17605 , n17606 , n17607 , n17608 , n17609 , n17610 ,
n17611 , n17612 , n17613 , n17614 , n17615 , n17616 , n17617 , n17618 , n17619 , n17620 ,
n17621 , n17622 , n17623 , n17624 , n17625 , n17626 , n17627 , n17628 , n17629 , n17630 ,
n17631 , n17632 , n17633 , n17634 , n17635 , n17636 , n17637 , n17638 , n17639 , n17640 ,
n17641 , n17642 , n17643 , n17644 , n17645 , n17646 , n17647 , n17648 , n17649 , n17650 ,
n17651 , n17652 , n17653 , n17654 , n17655 , n17656 , n17657 , n17658 , n17659 , n17660 ,
n17661 , n17662 , n17663 , n17664 , n17665 , n17666 , n17667 , n17668 , n17669 , n17670 ,
n17671 , n17672 , n17673 , n17674 , n17675 , n17676 , n17677 , n17678 , n17679 , n17680 ,
n17681 , n17682 , n17683 , n17684 , n17685 , n17686 , n17687 , n17688 , n17689 , n17690 ,
n17691 , n17692 , n17693 , n17694 , n17695 , n17696 , n17697 , n17698 , n17699 , n17700 ,
n17701 , n17702 , n17703 , n17704 , n17705 , n17706 , n17707 , n17708 , n17709 , n17710 ,
n17711 , n17712 , n17713 , n17714 , n17715 , n17716 , n17717 , n17718 , n17719 , n17720 ,
n17721 , n17722 , n17723 , n17724 , n17725 , n17726 , n17727 , n17728 , n17729 , n17730 ,
n17731 , n17732 , n17733 , n17734 , n17735 , n17736 , n17737 , n17738 , n17739 , n17740 ,
n17741 , n17742 , n17743 , n17744 , n17745 , n17746 , n17747 , n17748 , n17749 , n17750 ,
n17751 , n17752 , n17753 , n17754 , n17755 , n17756 , n17757 , n17758 , n17759 , n17760 ,
n17761 , n17762 , n17763 , n17764 , n17765 , n17766 , n17767 , n17768 , n17769 , n17770 ,
n17771 , n17772 , n17773 , n17774 , n17775 , n17776 , n17777 , n17778 , n17779 , n17780 ,
n17781 , n17782 , n17783 , n17784 , n17785 , n17786 , n17787 , n17788 , n17789 , n17790 ,
n17791 , n17792 , n17793 , n17794 , n17795 , n17796 , n17797 , n17798 , n17799 , n17800 ,
n17801 , n17802 , n17803 , n17804 , n17805 , n17806 , n17807 , n17808 , n17809 , n17810 ,
n17811 , n17812 , n17813 , n17814 , n17815 , n17816 , n17817 , n17818 , n17819 , n17820 ,
n17821 , n17822 , n17823 , n17824 , n17825 , n17826 , n17827 , n17828 , n17829 , n17830 ,
n17831 , n17832 , n17833 , n17834 , n17835 , n17836 , n17837 , n17838 , n17839 , n17840 ,
n17841 , n17842 , n17843 , n17844 , n17845 , n17846 , n17847 , n17848 , n17849 , n17850 ,
n17851 , n17852 , n17853 , n17854 , n17855 , n17856 , n17857 , n17858 , n17859 , n17860 ,
n17861 , n17862 , n17863 , n17864 , n17865 , n17866 , n17867 , n17868 , n17869 , n17870 ,
n17871 , n17872 , n17873 , n17874 , n17875 , n17876 , n17877 , n17878 , n17879 , n17880 ,
n17881 , n17882 , n17883 , n17884 , n17885 , n17886 , n17887 , n17888 , n17889 , n17890 ,
n17891 , n17892 , n17893 , n17894 , n17895 , n17896 , n17897 , n17898 , n17899 , n17900 ,
n17901 , n17902 , n17903 , n17904 , n17905 , n17906 , n17907 , n17908 , n17909 , n17910 ,
n17911 , n17912 , n17913 , n17914 , n17915 , n17916 , n17917 , n17918 , n17919 , n17920 ,
n17921 , n17922 , n17923 , n17924 , n17925 , n17926 , n17927 , n17928 , n17929 , n17930 ,
n17931 , n17932 , n17933 , n17934 , n17935 , n17936 , n17937 , n17938 , n17939 , n17940 ,
n17941 , n17942 , n17943 , n17944 , n17945 , n17946 , n17947 , n17948 , n17949 , n17950 ,
n17951 , n17952 , n17953 , n17954 , n17955 , n17956 , n17957 , n17958 , n17959 , n17960 ,
n17961 , n17962 , n17963 , n17964 , n17965 , n17966 , n17967 , n17968 , n17969 , n17970 ,
n17971 , n17972 , n17973 , n17974 , n17975 , n17976 , n17977 , n17978 , n17979 , n17980 ,
n17981 , n17982 , n17983 , n17984 , n17985 , n17986 , n17987 , n17988 , n17989 , n17990 ,
n17991 , n17992 , n17993 , n17994 , n17995 , n17996 , n17997 , n17998 , n17999 , n18000 ,
n18001 , n18002 , n18003 , n18004 , n18005 , n18006 , n18007 , n18008 , n18009 , n18010 ,
n18011 , n18012 , n18013 , n18014 , n18015 , n18016 , n18017 , n18018 , n18019 , n18020 ,
n18021 , n18022 , n18023 , n18024 , n18025 , n18026 , n18027 , n18028 , n18029 , n18030 ,
n18031 , n18032 , n18033 , n18034 , n18035 , n18036 , n18037 , n18038 , n18039 , n18040 ,
n18041 , n18042 , n18043 , n18044 , n18045 , n18046 , n18047 , n18048 , n18049 , n18050 ,
n18051 , n18052 , n18053 , n18054 , n18055 , n18056 , n18057 , n18058 , n18059 , n18060 ,
n18061 , n18062 , n18063 , n18064 , n18065 , n18066 , n18067 , n18068 , n18069 , n18070 ,
n18071 , n18072 , n18073 , n18074 , n18075 , n18076 , n18077 , n18078 , n18079 , n18080 ,
n18081 , n18082 , n18083 , n18084 , n18085 , n18086 , n18087 , n18088 , n18089 , n18090 ,
n18091 , n18092 , n18093 , n18094 , n18095 , n18096 , n18097 , n18098 , n18099 , n18100 ,
n18101 , n18102 , n18103 , n18104 , n18105 , n18106 , n18107 , n18108 , n18109 , n18110 ,
n18111 , n18112 , n18113 , n18114 , n18115 , n18116 , n18117 , n18118 , n18119 , n18120 ,
n18121 , n18122 , n18123 , n18124 , n18125 , n18126 , n18127 , n18128 , n18129 , n18130 ,
n18131 , n18132 , n18133 , n18134 , n18135 , n18136 , n18137 , n18138 , n18139 , n18140 ,
n18141 , n18142 , n18143 , n18144 , n18145 , n18146 , n18147 , n18148 , n18149 , n18150 ,
n18151 , n18152 , n18153 , n18154 , n18155 , n18156 , n18157 , n18158 , n18159 , n18160 ,
n18161 , n18162 , n18163 , n18164 , n18165 , n18166 , n18167 , n18168 , n18169 , n18170 ,
n18171 , n18172 , n18173 , n18174 , n18175 , n18176 , n18177 , n18178 , n18179 , n18180 ,
n18181 , n18182 , n18183 , n18184 , n18185 , n18186 , n18187 , n18188 , n18189 , n18190 ,
n18191 , n18192 , n18193 , n18194 , n18195 , n18196 , n18197 , n18198 , n18199 , n18200 ,
n18201 , n18202 , n18203 , n18204 , n18205 , n18206 , n18207 , n18208 , n18209 , n18210 ,
n18211 , n18212 , n18213 , n18214 , n18215 , n18216 , n18217 , n18218 , n18219 , n18220 ,
n18221 , n18222 , n18223 , n18224 , n18225 , n18226 , n18227 , n18228 , n18229 , n18230 ,
n18231 , n18232 , n18233 , n18234 , n18235 , n18236 , n18237 , n18238 , n18239 , n18240 ,
n18241 , n18242 , n18243 , n18244 , n18245 , n18246 , n18247 , n18248 , n18249 , n18250 ,
n18251 , n18252 , n18253 , n18254 , n18255 , n18256 , n18257 , n18258 , n18259 , n18260 ,
n18261 , n18262 , n18263 , n18264 , n18265 , n18266 , n18267 , n18268 , n18269 , n18270 ,
n18271 , n18272 , n18273 , n18274 , n18275 , n18276 , n18277 , n18278 , n18279 , n18280 ,
n18281 , n18282 , n18283 , n18284 , n18285 , n18286 , n18287 , n18288 , n18289 , n18290 ,
n18291 , n18292 , n18293 , n18294 , n18295 , n18296 , n18297 , n18298 , n18299 , n18300 ,
n18301 , n18302 , n18303 , n18304 , n18305 , n18306 , n18307 , n18308 , n18309 , n18310 ,
n18311 , n18312 , n18313 , n18314 , n18315 , n18316 , n18317 , n18318 , n18319 , n18320 ,
n18321 , n18322 , n18323 , n18324 , n18325 , n18326 , n18327 , n18328 , n18329 , n18330 ,
n18331 , n18332 , n18333 , n18334 , n18335 , n18336 , n18337 , n18338 , n18339 , n18340 ,
n18341 , n18342 , n18343 , n18344 , n18345 , n18346 , n18347 , n18348 , n18349 , n18350 ,
n18351 , n18352 , n18353 , n18354 , n18355 , n18356 , n18357 , n18358 , n18359 , n18360 ,
n18361 , n18362 , n18363 , n18364 , n18365 , n18366 , n18367 , n18368 , n18369 , n18370 ,
n18371 , n18372 , n18373 , n18374 , n18375 , n18376 , n18377 , n18378 , n18379 , n18380 ,
n18381 , n18382 , n18383 , n18384 , n18385 , n18386 , n18387 , n18388 , n18389 , n18390 ,
n18391 , n18392 , n18393 , n18394 , n18395 , n18396 , n18397 , n18398 , n18399 , n18400 ,
n18401 , n18402 , n18403 , n18404 , n18405 , n18406 , n18407 , n18408 , n18409 , n18410 ,
n18411 , n18412 , n18413 , n18414 , n18415 , n18416 , n18417 , n18418 , n18419 , n18420 ,
n18421 , n18422 , n18423 , n18424 , n18425 , n18426 , n18427 , n18428 , n18429 , n18430 ,
n18431 , n18432 , n18433 , n18434 , n18435 , n18436 , n18437 , n18438 , n18439 , n18440 ,
n18441 , n18442 , n18443 , n18444 , n18445 , n18446 , n18447 , n18448 , n18449 , n18450 ,
n18451 , n18452 , n18453 , n18454 , n18455 , n18456 , n18457 , n18458 , n18459 , n18460 ,
n18461 , n18462 , n18463 , n18464 , n18465 , n18466 , n18467 , n18468 , n18469 , n18470 ,
n18471 , n18472 , n18473 , n18474 , n18475 , n18476 , n18477 , n18478 , n18479 , n18480 ,
n18481 , n18482 , n18483 , n18484 , n18485 , n18486 , n18487 , n18488 , n18489 , n18490 ,
n18491 , n18492 , n18493 , n18494 , n18495 , n18496 , n18497 , n18498 , n18499 , n18500 ,
n18501 , n18502 , n18503 , n18504 , n18505 , n18506 , n18507 , n18508 , n18509 , n18510 ,
n18511 , n18512 , n18513 , n18514 , n18515 , n18516 , n18517 , n18518 , n18519 , n18520 ,
n18521 , n18522 , n18523 , n18524 , n18525 , n18526 , n18527 , n18528 , n18529 , n18530 ,
n18531 , n18532 , n18533 , n18534 , n18535 , n18536 , n18537 , n18538 , n18539 , n18540 ,
n18541 , n18542 , n18543 , n18544 , n18545 , n18546 , n18547 , n18548 , n18549 , n18550 ,
n18551 , n18552 , n18553 , n18554 , n18555 , n18556 , n18557 , n18558 , n18559 , n18560 ,
n18561 , n18562 , n18563 , n18564 , n18565 , n18566 , n18567 , n18568 , n18569 , n18570 ,
n18571 , n18572 , n18573 , n18574 , n18575 , n18576 , n18577 , n18578 , n18579 , n18580 ,
n18581 , n18582 , n18583 , n18584 , n18585 , n18586 , n18587 , n18588 , n18589 , n18590 ,
n18591 , n18592 , n18593 , n18594 , n18595 , n18596 , n18597 , n18598 , n18599 , n18600 ,
n18601 , n18602 , n18603 , n18604 , n18605 , n18606 , n18607 , n18608 , n18609 , n18610 ,
n18611 , n18612 , n18613 , n18614 , n18615 , n18616 , n18617 , n18618 , n18619 , n18620 ,
n18621 , n18622 , n18623 , n18624 , n18625 , n18626 , n18627 , n18628 , n18629 , n18630 ,
n18631 , n18632 , n18633 , n18634 , n18635 , n18636 , n18637 , n18638 , n18639 , n18640 ,
n18641 , n18642 , n18643 , n18644 , n18645 , n18646 , n18647 , n18648 , n18649 , n18650 ,
n18651 , n18652 , n18653 , n18654 , n18655 , n18656 , n18657 , n18658 , n18659 , n18660 ,
n18661 , n18662 , n18663 , n18664 , n18665 , n18666 , n18667 , n18668 , n18669 , n18670 ,
n18671 , n18672 , n18673 , n18674 , n18675 , n18676 , n18677 , n18678 , n18679 , n18680 ,
n18681 , n18682 , n18683 , n18684 , n18685 , n18686 , n18687 , n18688 , n18689 , n18690 ,
n18691 , n18692 , n18693 , n18694 , n18695 , n18696 , n18697 , n18698 , n18699 , n18700 ,
n18701 , n18702 , n18703 , n18704 , n18705 , n18706 , n18707 , n18708 , n18709 , n18710 ,
n18711 , n18712 , n18713 , n18714 , n18715 , n18716 , n18717 , n18718 , n18719 , n18720 ,
n18721 , n18722 , n18723 , n18724 , n18725 , n18726 , n18727 , n18728 , n18729 , n18730 ,
n18731 , n18732 , n18733 , n18734 , n18735 , n18736 , n18737 , n18738 , n18739 , n18740 ,
n18741 , n18742 , n18743 , n18744 , n18745 , n18746 , n18747 , n18748 , n18749 , n18750 ,
n18751 , n18752 , n18753 , n18754 , n18755 , n18756 , n18757 , n18758 , n18759 , n18760 ,
n18761 , n18762 , n18763 , n18764 , n18765 , n18766 , n18767 , n18768 , n18769 , n18770 ,
n18771 , n18772 , n18773 , n18774 , n18775 , n18776 , n18777 , n18778 , n18779 , n18780 ,
n18781 , n18782 , n18783 , n18784 , n18785 , n18786 , n18787 , n18788 , n18789 , n18790 ,
n18791 , n18792 , n18793 , n18794 , n18795 , n18796 , n18797 , n18798 , n18799 , n18800 ,
n18801 , n18802 , n18803 , n18804 , n18805 , n18806 , n18807 , n18808 , n18809 , n18810 ,
n18811 , n18812 , n18813 , n18814 , n18815 , n18816 , n18817 , n18818 , n18819 , n18820 ,
n18821 , n18822 , n18823 , n18824 , n18825 , n18826 , n18827 , n18828 , n18829 , n18830 ,
n18831 , n18832 , n18833 , n18834 , n18835 , n18836 , n18837 , n18838 , n18839 , n18840 ,
n18841 , n18842 , n18843 , n18844 , n18845 , n18846 , n18847 , n18848 , n18849 , n18850 ,
n18851 , n18852 , n18853 , n18854 , n18855 , n18856 , n18857 , n18858 , n18859 , n18860 ,
n18861 , n18862 , n18863 , n18864 , n18865 , n18866 , n18867 , n18868 , n18869 , n18870 ,
n18871 , n18872 , n18873 , n18874 , n18875 , n18876 , n18877 , n18878 , n18879 , n18880 ,
n18881 , n18882 , n18883 , n18884 , n18885 , n18886 , n18887 , n18888 , n18889 , n18890 ,
n18891 , n18892 , n18893 , n18894 , n18895 , n18896 , n18897 , n18898 , n18899 , n18900 ,
n18901 , n18902 , n18903 , n18904 , n18905 , n18906 , n18907 , n18908 , n18909 , n18910 ,
n18911 , n18912 , n18913 , n18914 , n18915 , n18916 , n18917 , n18918 , n18919 , n18920 ,
n18921 , n18922 , n18923 , n18924 , n18925 , n18926 , n18927 , n18928 , n18929 , n18930 ,
n18931 , n18932 , n18933 , n18934 , n18935 , n18936 , n18937 , n18938 , n18939 , n18940 ,
n18941 , n18942 , n18943 , n18944 , n18945 , n18946 , n18947 , n18948 , n18949 , n18950 ,
n18951 , n18952 , n18953 , n18954 , n18955 , n18956 , n18957 , n18958 , n18959 , n18960 ,
n18961 , n18962 , n18963 , n18964 , n18965 , n18966 , n18967 , n18968 , n18969 , n18970 ,
n18971 , n18972 , n18973 , n18974 , n18975 , n18976 , n18977 , n18978 , n18979 , n18980 ,
n18981 , n18982 , n18983 , n18984 , n18985 , n18986 , n18987 , n18988 , n18989 , n18990 ,
n18991 , n18992 , n18993 , n18994 , n18995 , n18996 , n18997 , n18998 , n18999 , n19000 ,
n19001 , n19002 , n19003 , n19004 , n19005 , n19006 , n19007 , n19008 , n19009 , n19010 ,
n19011 , n19012 , n19013 , n19014 , n19015 , n19016 , n19017 , n19018 , n19019 , n19020 ,
n19021 , n19022 , n19023 , n19024 , n19025 , n19026 , n19027 , n19028 , n19029 , n19030 ,
n19031 , n19032 , n19033 , n19034 , n19035 , n19036 , n19037 , n19038 , n19039 , n19040 ,
n19041 , n19042 , n19043 , n19044 , n19045 , n19046 , n19047 , n19048 , n19049 , n19050 ,
n19051 , n19052 , n19053 , n19054 , n19055 , n19056 , n19057 , n19058 , n19059 , n19060 ,
n19061 , n19062 , n19063 , n19064 , n19065 , n19066 , n19067 , n19068 , n19069 , n19070 ,
n19071 , n19072 , n19073 , n19074 , n19075 , n19076 , n19077 , n19078 , n19079 , n19080 ,
n19081 , n19082 , n19083 , n19084 , n19085 , n19086 , n19087 , n19088 , n19089 , n19090 ,
n19091 , n19092 , n19093 , n19094 , n19095 , n19096 , n19097 , n19098 , n19099 , n19100 ,
n19101 , n19102 , n19103 , n19104 , n19105 , n19106 , n19107 , n19108 , n19109 , n19110 ,
n19111 , n19112 , n19113 , n19114 , n19115 , n19116 , n19117 , n19118 , n19119 , n19120 ,
n19121 , n19122 , n19123 , n19124 , n19125 , n19126 , n19127 , n19128 , n19129 , n19130 ,
n19131 , n19132 , n19133 , n19134 , n19135 , n19136 , n19137 , n19138 , n19139 , n19140 ,
n19141 , n19142 , n19143 , n19144 , n19145 , n19146 , n19147 , n19148 , n19149 , n19150 ,
n19151 , n19152 , n19153 , n19154 , n19155 , n19156 , n19157 , n19158 , n19159 , n19160 ,
n19161 , n19162 , n19163 , n19164 , n19165 , n19166 , n19167 , n19168 , n19169 , n19170 ,
n19171 , n19172 , n19173 , n19174 , n19175 , n19176 , n19177 , n19178 , n19179 , n19180 ,
n19181 , n19182 , n19183 , n19184 , n19185 , n19186 , n19187 , n19188 , n19189 , n19190 ,
n19191 , n19192 , n19193 , n19194 , n19195 , n19196 , n19197 , n19198 , n19199 , n19200 ,
n19201 , n19202 , n19203 , n19204 , n19205 , n19206 , n19207 , n19208 , n19209 , n19210 ,
n19211 , n19212 , n19213 , n19214 , n19215 , n19216 , n19217 , n19218 , n19219 , n19220 ,
n19221 , n19222 , n19223 , n19224 , n19225 , n19226 , n19227 , n19228 , n19229 , n19230 ,
n19231 , n19232 , n19233 , n19234 , n19235 , n19236 , n19237 , n19238 , n19239 , n19240 ,
n19241 , n19242 , n19243 , n19244 , n19245 , n19246 , n19247 , n19248 , n19249 , n19250 ,
n19251 , n19252 , n19253 , n19254 , n19255 , n19256 , n19257 , n19258 , n19259 , n19260 ,
n19261 , n19262 , n19263 , n19264 , n19265 , n19266 , n19267 , n19268 , n19269 , n19270 ,
n19271 , n19272 , n19273 , n19274 , n19275 , n19276 , n19277 , n19278 , n19279 , n19280 ,
n19281 , n19282 , n19283 , n19284 , n19285 , n19286 , n19287 , n19288 , n19289 , n19290 ,
n19291 , n19292 , n19293 , n19294 , n19295 , n19296 , n19297 , n19298 , n19299 , n19300 ,
n19301 , n19302 , n19303 , n19304 , n19305 , n19306 , n19307 , n19308 , n19309 , n19310 ,
n19311 , n19312 , n19313 , n19314 , n19315 , n19316 , n19317 , n19318 , n19319 , n19320 ,
n19321 , n19322 , n19323 , n19324 , n19325 , n19326 , n19327 , n19328 , n19329 , n19330 ,
n19331 , n19332 , n19333 , n19334 , n19335 , n19336 , n19337 , n19338 , n19339 , n19340 ,
n19341 , n19342 , n19343 , n19344 , n19345 , n19346 , n19347 , n19348 , n19349 , n19350 ,
n19351 , n19352 , n19353 , n19354 , n19355 , n19356 , n19357 , n19358 , n19359 , n19360 ,
n19361 , n19362 , n19363 , n19364 , n19365 , n19366 , n19367 , n19368 , n19369 , n19370 ,
n19371 , n19372 , n19373 , n19374 , n19375 , n19376 , n19377 , n19378 , n19379 , n19380 ,
n19381 , n19382 , n19383 , n19384 , n19385 , n19386 , n19387 , n19388 , n19389 , n19390 ,
n19391 , n19392 , n19393 , n19394 , n19395 , n19396 , n19397 , n19398 , n19399 , n19400 ,
n19401 , n19402 , n19403 , n19404 , n19405 , n19406 , n19407 , n19408 , n19409 , n19410 ,
n19411 , n19412 , n19413 , n19414 , n19415 , n19416 , n19417 , n19418 , n19419 , n19420 ,
n19421 , n19422 , n19423 , n19424 , n19425 , n19426 , n19427 , n19428 , n19429 , n19430 ,
n19431 , n19432 , n19433 , n19434 , n19435 , n19436 , n19437 , n19438 , n19439 , n19440 ,
n19441 , n19442 , n19443 , n19444 , n19445 , n19446 , n19447 , n19448 , n19449 , n19450 ,
n19451 , n19452 , n19453 , n19454 , n19455 , n19456 , n19457 , n19458 , n19459 , n19460 ,
n19461 , n19462 , n19463 , n19464 , n19465 , n19466 , n19467 , n19468 , n19469 , n19470 ,
n19471 , n19472 , n19473 , n19474 , n19475 , n19476 , n19477 , n19478 , n19479 , n19480 ,
n19481 , n19482 , n19483 , n19484 , n19485 , n19486 , n19487 , n19488 , n19489 , n19490 ,
n19491 , n19492 , n19493 , n19494 , n19495 , n19496 , n19497 , n19498 , n19499 , n19500 ,
n19501 , n19502 , n19503 , n19504 , n19505 , n19506 , n19507 , n19508 , n19509 , n19510 ,
n19511 , n19512 , n19513 , n19514 , n19515 , n19516 , n19517 , n19518 , n19519 , n19520 ,
n19521 , n19522 , n19523 , n19524 , n19525 , n19526 , n19527 , n19528 , n19529 , n19530 ,
n19531 , n19532 , n19533 , n19534 , n19535 , n19536 , n19537 , n19538 , n19539 , n19540 ,
n19541 , n19542 , n19543 , n19544 , n19545 , n19546 , n19547 , n19548 , n19549 , n19550 ,
n19551 , n19552 , n19553 , n19554 , n19555 , n19556 , n19557 , n19558 , n19559 , n19560 ,
n19561 , n19562 , n19563 , n19564 , n19565 , n19566 , n19567 , n19568 , n19569 , n19570 ,
n19571 , n19572 , n19573 , n19574 , n19575 , n19576 , n19577 , n19578 , n19579 , n19580 ,
n19581 , n19582 , n19583 , n19584 , n19585 , n19586 , n19587 , n19588 , n19589 , n19590 ,
n19591 , n19592 , n19593 , n19594 , n19595 , n19596 , n19597 , n19598 , n19599 , n19600 ,
n19601 , n19602 , n19603 , n19604 , n19605 , n19606 , n19607 , n19608 , n19609 , n19610 ,
n19611 , n19612 , n19613 , n19614 , n19615 , n19616 , n19617 , n19618 , n19619 , n19620 ,
n19621 , n19622 , n19623 , n19624 , n19625 , n19626 , n19627 , n19628 , n19629 , n19630 ,
n19631 , n19632 , n19633 , n19634 , n19635 , n19636 , n19637 , n19638 , n19639 , n19640 ,
n19641 , n19642 , n19643 , n19644 , n19645 , n19646 , n19647 , n19648 , n19649 , n19650 ,
n19651 , n19652 , n19653 , n19654 , n19655 , n19656 , n19657 , n19658 , n19659 , n19660 ,
n19661 , n19662 , n19663 , n19664 , n19665 , n19666 , n19667 , n19668 , n19669 , n19670 ,
n19671 , n19672 , n19673 , n19674 , n19675 , n19676 , n19677 , n19678 , n19679 , n19680 ,
n19681 , n19682 , n19683 , n19684 , n19685 , n19686 , n19687 , n19688 , n19689 , n19690 ,
n19691 , n19692 , n19693 , n19694 , n19695 , n19696 , n19697 , n19698 , n19699 , n19700 ,
n19701 , n19702 , n19703 , n19704 , n19705 , n19706 , n19707 , n19708 , n19709 , n19710 ,
n19711 , n19712 , n19713 , n19714 , n19715 , n19716 , n19717 , n19718 , n19719 , n19720 ,
n19721 , n19722 , n19723 , n19724 , n19725 , n19726 , n19727 , n19728 , n19729 , n19730 ,
n19731 , n19732 , n19733 , n19734 , n19735 , n19736 , n19737 , n19738 , n19739 , n19740 ,
n19741 , n19742 , n19743 , n19744 , n19745 , n19746 , n19747 , n19748 , n19749 , n19750 ,
n19751 , n19752 , n19753 , n19754 , n19755 , n19756 , n19757 , n19758 , n19759 , n19760 ,
n19761 , n19762 , n19763 , n19764 , n19765 , n19766 , n19767 , n19768 , n19769 , n19770 ,
n19771 , n19772 , n19773 , n19774 , n19775 , n19776 , n19777 , n19778 , n19779 , n19780 ,
n19781 , n19782 , n19783 , n19784 , n19785 , n19786 , n19787 , n19788 , n19789 , n19790 ,
n19791 , n19792 , n19793 , n19794 , n19795 , n19796 , n19797 , n19798 , n19799 , n19800 ,
n19801 , n19802 , n19803 , n19804 , n19805 , n19806 , n19807 , n19808 , n19809 , n19810 ,
n19811 , n19812 , n19813 , n19814 , n19815 , n19816 , n19817 , n19818 , n19819 , n19820 ,
n19821 , n19822 , n19823 , n19824 , n19825 , n19826 , n19827 , n19828 , n19829 , n19830 ,
n19831 , n19832 , n19833 , n19834 , n19835 , n19836 , n19837 , n19838 , n19839 , n19840 ,
n19841 , n19842 , n19843 , n19844 , n19845 , n19846 , n19847 , n19848 , n19849 , n19850 ,
n19851 , n19852 , n19853 , n19854 , n19855 , n19856 , n19857 , n19858 , n19859 , n19860 ,
n19861 , n19862 , n19863 , n19864 , n19865 , n19866 , n19867 , n19868 , n19869 , n19870 ,
n19871 , n19872 , n19873 , n19874 , n19875 , n19876 , n19877 , n19878 , n19879 , n19880 ,
n19881 , n19882 , n19883 , n19884 , n19885 , n19886 , n19887 , n19888 , n19889 , n19890 ,
n19891 , n19892 , n19893 , n19894 , n19895 , n19896 , n19897 , n19898 , n19899 , n19900 ,
n19901 , n19902 , n19903 , n19904 , n19905 , n19906 , n19907 , n19908 , n19909 , n19910 ,
n19911 , n19912 , n19913 , n19914 , n19915 , n19916 , n19917 , n19918 , n19919 , n19920 ,
n19921 , n19922 , n19923 , n19924 , n19925 , n19926 , n19927 , n19928 , n19929 , n19930 ,
n19931 , n19932 , n19933 , n19934 , n19935 , n19936 , n19937 , n19938 , n19939 , n19940 ,
n19941 , n19942 , n19943 , n19944 , n19945 , n19946 , n19947 , n19948 , n19949 , n19950 ,
n19951 , n19952 , n19953 , n19954 , n19955 , n19956 , n19957 , n19958 , n19959 , n19960 ,
n19961 , n19962 , n19963 , n19964 , n19965 , n19966 , n19967 , n19968 , n19969 , n19970 ,
n19971 , n19972 , n19973 , n19974 , n19975 , n19976 , n19977 , n19978 , n19979 , n19980 ,
n19981 , n19982 , n19983 , n19984 , n19985 , n19986 , n19987 , n19988 , n19989 , n19990 ,
n19991 , n19992 , n19993 , n19994 , n19995 , n19996 , n19997 , n19998 , n19999 , n20000 ,
n20001 , n20002 , n20003 , n20004 , n20005 , n20006 , n20007 , n20008 , n20009 , n20010 ,
n20011 , n20012 , n20013 , n20014 , n20015 , n20016 , n20017 , n20018 , n20019 , n20020 ,
n20021 , n20022 , n20023 , n20024 , n20025 , n20026 , n20027 , n20028 , n20029 , n20030 ,
n20031 , n20032 , n20033 , n20034 , n20035 , n20036 , n20037 , n20038 , n20039 , n20040 ,
n20041 , n20042 , n20043 , n20044 , n20045 , n20046 , n20047 , n20048 , n20049 , n20050 ,
n20051 , n20052 , n20053 , n20054 , n20055 , n20056 , n20057 , n20058 , n20059 , n20060 ,
n20061 , n20062 , n20063 , n20064 , n20065 , n20066 , n20067 , n20068 , n20069 , n20070 ,
n20071 , n20072 , n20073 , n20074 , n20075 , n20076 , n20077 , n20078 , n20079 , n20080 ,
n20081 , n20082 , n20083 , n20084 , n20085 , n20086 , n20087 , n20088 , n20089 , n20090 ,
n20091 , n20092 , n20093 , n20094 , n20095 , n20096 , n20097 , n20098 , n20099 , n20100 ,
n20101 , n20102 , n20103 , n20104 , n20105 , n20106 , n20107 , n20108 , n20109 , n20110 ,
n20111 , n20112 , n20113 , n20114 , n20115 , n20116 , n20117 , n20118 , n20119 , n20120 ,
n20121 , n20122 , n20123 , n20124 , n20125 , n20126 , n20127 , n20128 , n20129 , n20130 ,
n20131 , n20132 , n20133 , n20134 , n20135 , n20136 , n20137 , n20138 , n20139 , n20140 ,
n20141 , n20142 , n20143 , n20144 , n20145 , n20146 , n20147 , n20148 , n20149 , n20150 ,
n20151 , n20152 , n20153 , n20154 , n20155 , n20156 , n20157 , n20158 , n20159 , n20160 ,
n20161 , n20162 , n20163 , n20164 , n20165 , n20166 , n20167 , n20168 , n20169 , n20170 ,
n20171 , n20172 , n20173 , n20174 , n20175 , n20176 , n20177 , n20178 , n20179 , n20180 ,
n20181 , n20182 , n20183 , n20184 , n20185 , n20186 , n20187 , n20188 , n20189 , n20190 ,
n20191 , n20192 , n20193 , n20194 , n20195 , n20196 , n20197 , n20198 , n20199 , n20200 ,
n20201 , n20202 , n20203 , n20204 , n20205 , n20206 , n20207 , n20208 , n20209 , n20210 ,
n20211 , n20212 , n20213 , n20214 , n20215 , n20216 , n20217 , n20218 , n20219 , n20220 ,
n20221 , n20222 , n20223 , n20224 , n20225 , n20226 , n20227 , n20228 , n20229 , n20230 ,
n20231 , n20232 , n20233 , n20234 , n20235 , n20236 , n20237 , n20238 , n20239 , n20240 ,
n20241 , n20242 , n20243 , n20244 , n20245 , n20246 , n20247 , n20248 , n20249 , n20250 ,
n20251 , n20252 , n20253 , n20254 , n20255 , n20256 , n20257 , n20258 , n20259 , n20260 ,
n20261 , n20262 , n20263 , n20264 , n20265 , n20266 , n20267 , n20268 , n20269 , n20270 ,
n20271 , n20272 , n20273 , n20274 , n20275 , n20276 , n20277 , n20278 , n20279 , n20280 ,
n20281 , n20282 , n20283 , n20284 , n20285 , n20286 , n20287 , n20288 , n20289 , n20290 ,
n20291 , n20292 , n20293 , n20294 , n20295 , n20296 , n20297 , n20298 , n20299 , n20300 ,
n20301 , n20302 , n20303 , n20304 , n20305 , n20306 , n20307 , n20308 , n20309 , n20310 ,
n20311 , n20312 , n20313 , n20314 , n20315 , n20316 , n20317 , n20318 , n20319 , n20320 ,
n20321 , n20322 , n20323 , n20324 , n20325 , n20326 , n20327 , n20328 , n20329 , n20330 ,
n20331 , n20332 , n20333 , n20334 , n20335 , n20336 , n20337 , n20338 , n20339 , n20340 ,
n20341 , n20342 , n20343 , n20344 , n20345 , n20346 , n20347 , n20348 , n20349 , n20350 ,
n20351 , n20352 , n20353 , n20354 , n20355 , n20356 , n20357 , n20358 , n20359 , n20360 ,
n20361 , n20362 , n20363 , n20364 , n20365 , n20366 , n20367 , n20368 , n20369 , n20370 ,
n20371 , n20372 , n20373 , n20374 , n20375 , n20376 , n20377 , n20378 , n20379 , n20380 ,
n20381 , n20382 , n20383 , n20384 , n20385 , n20386 , n20387 , n20388 , n20389 , n20390 ,
n20391 , n20392 , n20393 , n20394 , n20395 , n20396 , n20397 , n20398 , n20399 , n20400 ,
n20401 , n20402 , n20403 , n20404 , n20405 , n20406 , n20407 , n20408 , n20409 , n20410 ,
n20411 , n20412 , n20413 , n20414 , n20415 , n20416 , n20417 , n20418 , n20419 , n20420 ,
n20421 , n20422 , n20423 , n20424 , n20425 , n20426 , n20427 , n20428 , n20429 , n20430 ,
n20431 , n20432 , n20433 , n20434 , n20435 , n20436 , n20437 , n20438 , n20439 , n20440 ,
n20441 , n20442 , n20443 , n20444 , n20445 , n20446 , n20447 , n20448 , n20449 , n20450 ,
n20451 , n20452 , n20453 , n20454 , n20455 , n20456 , n20457 , n20458 , n20459 , n20460 ,
n20461 , n20462 , n20463 , n20464 , n20465 , n20466 , n20467 , n20468 , n20469 , n20470 ,
n20471 , n20472 , n20473 , n20474 , n20475 , n20476 , n20477 , n20478 , n20479 , n20480 ,
n20481 , n20482 , n20483 , n20484 , n20485 , n20486 , n20487 , n20488 , n20489 , n20490 ,
n20491 , n20492 , n20493 , n20494 , n20495 , n20496 , n20497 , n20498 , n20499 , n20500 ,
n20501 , n20502 , n20503 , n20504 , n20505 , n20506 , n20507 , n20508 , n20509 , n20510 ,
n20511 , n20512 , n20513 , n20514 , n20515 , n20516 , n20517 , n20518 , n20519 , n20520 ,
n20521 , n20522 , n20523 , n20524 , n20525 , n20526 , n20527 , n20528 , n20529 , n20530 ,
n20531 , n20532 , n20533 , n20534 , n20535 , n20536 , n20537 , n20538 , n20539 , n20540 ,
n20541 , n20542 , n20543 , n20544 , n20545 , n20546 , n20547 , n20548 , n20549 , n20550 ,
n20551 , n20552 , n20553 , n20554 , n20555 , n20556 , n20557 , n20558 , n20559 , n20560 ,
n20561 , n20562 , n20563 , n20564 , n20565 , n20566 , n20567 , n20568 , n20569 , n20570 ,
n20571 , n20572 , n20573 , n20574 , n20575 , n20576 , n20577 , n20578 , n20579 , n20580 ,
n20581 , n20582 , n20583 , n20584 , n20585 , n20586 , n20587 , n20588 , n20589 , n20590 ,
n20591 , n20592 , n20593 , n20594 , n20595 , n20596 , n20597 , n20598 , n20599 , n20600 ,
n20601 , n20602 , n20603 , n20604 , n20605 , n20606 , n20607 , n20608 , n20609 , n20610 ,
n20611 , n20612 , n20613 , n20614 , n20615 , n20616 , n20617 , n20618 , n20619 , n20620 ,
n20621 , n20622 , n20623 , n20624 , n20625 , n20626 , n20627 , n20628 , n20629 , n20630 ,
n20631 , n20632 , n20633 , n20634 , n20635 , n20636 , n20637 , n20638 , n20639 , n20640 ,
n20641 , n20642 , n20643 , n20644 , n20645 , n20646 , n20647 , n20648 , n20649 , n20650 ,
n20651 , n20652 , n20653 , n20654 , n20655 , n20656 , n20657 , n20658 , n20659 , n20660 ,
n20661 , n20662 , n20663 , n20664 , n20665 , n20666 , n20667 , n20668 , n20669 , n20670 ,
n20671 , n20672 , n20673 , n20674 , n20675 , n20676 , n20677 , n20678 , n20679 , n20680 ,
n20681 , n20682 , n20683 , n20684 , n20685 , n20686 , n20687 , n20688 , n20689 , n20690 ,
n20691 , n20692 , n20693 , n20694 , n20695 , n20696 , n20697 , n20698 , n20699 , n20700 ,
n20701 , n20702 , n20703 , n20704 , n20705 , n20706 , n20707 , n20708 , n20709 , n20710 ,
n20711 , n20712 , n20713 , n20714 , n20715 , n20716 , n20717 , n20718 , n20719 , n20720 ,
n20721 , n20722 , n20723 , n20724 , n20725 , n20726 , n20727 , n20728 , n20729 , n20730 ,
n20731 , n20732 , n20733 , n20734 , n20735 , n20736 , n20737 , n20738 , n20739 , n20740 ,
n20741 , n20742 , n20743 , n20744 , n20745 , n20746 , n20747 , n20748 , n20749 , n20750 ,
n20751 , n20752 , n20753 , n20754 , n20755 , n20756 , n20757 , n20758 , n20759 , n20760 ,
n20761 , n20762 , n20763 , n20764 , n20765 , n20766 , n20767 , n20768 , n20769 , n20770 ,
n20771 , n20772 , n20773 , n20774 , n20775 , n20776 , n20777 , n20778 , n20779 , n20780 ,
n20781 , n20782 , n20783 , n20784 , n20785 , n20786 , n20787 , n20788 , n20789 , n20790 ,
n20791 , n20792 , n20793 , n20794 , n20795 , n20796 , n20797 , n20798 , n20799 , n20800 ,
n20801 , n20802 , n20803 , n20804 , n20805 , n20806 , n20807 , n20808 , n20809 , n20810 ,
n20811 , n20812 , n20813 , n20814 , n20815 , n20816 , n20817 , n20818 , n20819 , n20820 ,
n20821 , n20822 , n20823 , n20824 , n20825 , n20826 , n20827 , n20828 , n20829 , n20830 ,
n20831 , n20832 , n20833 , n20834 , n20835 , n20836 , n20837 , n20838 , n20839 , n20840 ,
n20841 , n20842 , n20843 , n20844 , n20845 , n20846 , n20847 , n20848 , n20849 , n20850 ,
n20851 , n20852 , n20853 , n20854 , n20855 , n20856 , n20857 , n20858 , n20859 , n20860 ,
n20861 , n20862 , n20863 , n20864 , n20865 , n20866 , n20867 , n20868 , n20869 , n20870 ,
n20871 , n20872 , n20873 , n20874 , n20875 , n20876 , n20877 , n20878 , n20879 , n20880 ,
n20881 , n20882 , n20883 , n20884 , n20885 , n20886 , n20887 , n20888 , n20889 , n20890 ,
n20891 , n20892 , n20893 , n20894 , n20895 , n20896 , n20897 , n20898 , n20899 , n20900 ,
n20901 , n20902 , n20903 , n20904 , n20905 , n20906 , n20907 , n20908 , n20909 , n20910 ,
n20911 , n20912 , n20913 , n20914 , n20915 , n20916 , n20917 , n20918 , n20919 , n20920 ,
n20921 , n20922 , n20923 , n20924 , n20925 , n20926 , n20927 , n20928 , n20929 , n20930 ,
n20931 , n20932 , n20933 , n20934 , n20935 , n20936 , n20937 , n20938 , n20939 , n20940 ,
n20941 , n20942 , n20943 , n20944 , n20945 , n20946 , n20947 , n20948 , n20949 , n20950 ,
n20951 , n20952 , n20953 , n20954 , n20955 , n20956 , n20957 , n20958 , n20959 , n20960 ,
n20961 , n20962 , n20963 , n20964 , n20965 , n20966 , n20967 , n20968 , n20969 , n20970 ,
n20971 , n20972 , n20973 , n20974 , n20975 , n20976 , n20977 , n20978 , n20979 , n20980 ,
n20981 , n20982 , n20983 , n20984 , n20985 , n20986 , n20987 , n20988 , n20989 , n20990 ,
n20991 , n20992 , n20993 , n20994 , n20995 , n20996 , n20997 , n20998 , n20999 , n21000 ,
n21001 , n21002 , n21003 , n21004 , n21005 , n21006 , n21007 , n21008 , n21009 , n21010 ,
n21011 , n21012 , n21013 , n21014 , n21015 , n21016 , n21017 , n21018 , n21019 , n21020 ,
n21021 , n21022 , n21023 , n21024 , n21025 , n21026 , n21027 , n21028 , n21029 , n21030 ,
n21031 , n21032 , n21033 , n21034 , n21035 , n21036 , n21037 , n21038 , n21039 , n21040 ,
n21041 , n21042 , n21043 , n21044 , n21045 , n21046 , n21047 , n21048 , n21049 , n21050 ,
n21051 , n21052 , n21053 , n21054 , n21055 , n21056 , n21057 , n21058 , n21059 , n21060 ,
n21061 , n21062 , n21063 , n21064 , n21065 , n21066 , n21067 , n21068 , n21069 , n21070 ,
n21071 , n21072 , n21073 , n21074 , n21075 , n21076 , n21077 , n21078 , n21079 , n21080 ,
n21081 , n21082 , n21083 , n21084 , n21085 , n21086 , n21087 , n21088 , n21089 , n21090 ,
n21091 , n21092 , n21093 , n21094 , n21095 , n21096 , n21097 , n21098 , n21099 , n21100 ,
n21101 , n21102 , n21103 , n21104 , n21105 , n21106 , n21107 , n21108 , n21109 , n21110 ,
n21111 , n21112 , n21113 , n21114 , n21115 , n21116 , n21117 , n21118 , n21119 , n21120 ,
n21121 , n21122 , n21123 , n21124 , n21125 , n21126 , n21127 , n21128 , n21129 , n21130 ,
n21131 , n21132 , n21133 , n21134 , n21135 , n21136 , n21137 , n21138 , n21139 , n21140 ,
n21141 , n21142 , n21143 , n21144 , n21145 , n21146 , n21147 , n21148 , n21149 , n21150 ,
n21151 , n21152 , n21153 , n21154 , n21155 , n21156 , n21157 , n21158 , n21159 , n21160 ,
n21161 , n21162 , n21163 , n21164 , n21165 , n21166 , n21167 , n21168 , n21169 , n21170 ,
n21171 , n21172 , n21173 , n21174 , n21175 , n21176 , n21177 , n21178 , n21179 , n21180 ,
n21181 , n21182 , n21183 , n21184 , n21185 , n21186 , n21187 , n21188 , n21189 , n21190 ,
n21191 , n21192 , n21193 , n21194 , n21195 , n21196 , n21197 , n21198 , n21199 , n21200 ,
n21201 , n21202 , n21203 , n21204 , n21205 , n21206 , n21207 , n21208 , n21209 , n21210 ,
n21211 , n21212 , n21213 , n21214 , n21215 , n21216 , n21217 , n21218 , n21219 , n21220 ,
n21221 , n21222 , n21223 , n21224 , n21225 , n21226 , n21227 , n21228 , n21229 , n21230 ,
n21231 , n21232 , n21233 , n21234 , n21235 , n21236 , n21237 , n21238 , n21239 , n21240 ,
n21241 , n21242 , n21243 , n21244 , n21245 , n21246 , n21247 , n21248 , n21249 , n21250 ,
n21251 , n21252 , n21253 , n21254 , n21255 , n21256 , n21257 , n21258 , n21259 , n21260 ,
n21261 , n21262 , n21263 , n21264 , n21265 , n21266 , n21267 , n21268 , n21269 , n21270 ,
n21271 , n21272 , n21273 , n21274 , n21275 , n21276 , n21277 , n21278 , n21279 , n21280 ,
n21281 , n21282 , n21283 , n21284 , n21285 , n21286 , n21287 , n21288 , n21289 , n21290 ,
n21291 , n21292 , n21293 , n21294 , n21295 , n21296 , n21297 , n21298 , n21299 , n21300 ,
n21301 , n21302 , n21303 , n21304 , n21305 , n21306 , n21307 , n21308 , n21309 , n21310 ,
n21311 , n21312 , n21313 , n21314 , n21315 , n21316 , n21317 , n21318 , n21319 , n21320 ,
n21321 , n21322 , n21323 , n21324 , n21325 , n21326 , n21327 , n21328 , n21329 , n21330 ,
n21331 , n21332 , n21333 , n21334 , n21335 , n21336 , n21337 , n21338 , n21339 , n21340 ,
n21341 , n21342 , n21343 , n21344 , n21345 , n21346 , n21347 , n21348 , n21349 , n21350 ,
n21351 , n21352 , n21353 , n21354 , n21355 , n21356 , n21357 , n21358 , n21359 , n21360 ,
n21361 , n21362 , n21363 , n21364 , n21365 , n21366 , n21367 , n21368 , n21369 , n21370 ,
n21371 , n21372 , n21373 , n21374 , n21375 , n21376 , n21377 , n21378 , n21379 , n21380 ,
n21381 , n21382 , n21383 , n21384 , n21385 , n21386 , n21387 , n21388 , n21389 , n21390 ,
n21391 , n21392 , n21393 , n21394 , n21395 , n21396 , n21397 , n21398 , n21399 , n21400 ,
n21401 , n21402 , n21403 , n21404 , n21405 , n21406 , n21407 , n21408 , n21409 , n21410 ,
n21411 , n21412 , n21413 , n21414 , n21415 , n21416 , n21417 , n21418 , n21419 , n21420 ,
n21421 , n21422 , n21423 , n21424 , n21425 , n21426 , n21427 , n21428 , n21429 , n21430 ,
n21431 , n21432 , n21433 , n21434 , n21435 , n21436 , n21437 , n21438 , n21439 , n21440 ,
n21441 , n21442 , n21443 , n21444 , n21445 , n21446 , n21447 , n21448 , n21449 , n21450 ,
n21451 , n21452 , n21453 , n21454 , n21455 , n21456 , n21457 , n21458 , n21459 , n21460 ,
n21461 , n21462 , n21463 , n21464 , n21465 , n21466 , n21467 , n21468 , n21469 , n21470 ,
n21471 , n21472 , n21473 , n21474 , n21475 , n21476 , n21477 , n21478 , n21479 , n21480 ,
n21481 , n21482 , n21483 , n21484 , n21485 , n21486 , n21487 , n21488 , n21489 , n21490 ,
n21491 , n21492 , n21493 , n21494 , n21495 , n21496 , n21497 , n21498 , n21499 , n21500 ,
n21501 , n21502 , n21503 , n21504 , n21505 , n21506 , n21507 , n21508 , n21509 , n21510 ,
n21511 , n21512 , n21513 , n21514 , n21515 , n21516 , n21517 , n21518 , n21519 , n21520 ,
n21521 , n21522 , n21523 , n21524 , n21525 , n21526 , n21527 , n21528 , n21529 , n21530 ,
n21531 , n21532 , n21533 , n21534 , n21535 , n21536 , n21537 , n21538 , n21539 , n21540 ,
n21541 , n21542 , n21543 , n21544 , n21545 , n21546 , n21547 , n21548 , n21549 , n21550 ,
n21551 , n21552 , n21553 , n21554 , n21555 , n21556 , n21557 , n21558 , n21559 , n21560 ,
n21561 , n21562 , n21563 , n21564 , n21565 , n21566 , n21567 , n21568 , n21569 , n21570 ,
n21571 , n21572 , n21573 , n21574 , n21575 , n21576 , n21577 , n21578 , n21579 , n21580 ,
n21581 , n21582 , n21583 , n21584 , n21585 , n21586 , n21587 , n21588 , n21589 , n21590 ,
n21591 , n21592 , n21593 , n21594 , n21595 , n21596 , n21597 , n21598 , n21599 , n21600 ,
n21601 , n21602 , n21603 , n21604 , n21605 , n21606 , n21607 , n21608 , n21609 , n21610 ,
n21611 , n21612 , n21613 , n21614 , n21615 , n21616 , n21617 , n21618 , n21619 , n21620 ,
n21621 , n21622 , n21623 , n21624 , n21625 , n21626 , n21627 , n21628 , n21629 , n21630 ,
n21631 , n21632 , n21633 , n21634 , n21635 , n21636 , n21637 , n21638 , n21639 , n21640 ,
n21641 , n21642 , n21643 , n21644 , n21645 , n21646 , n21647 , n21648 , n21649 , n21650 ,
n21651 , n21652 , n21653 , n21654 , n21655 , n21656 , n21657 , n21658 , n21659 , n21660 ,
n21661 , n21662 , n21663 , n21664 , n21665 , n21666 , n21667 , n21668 , n21669 , n21670 ,
n21671 , n21672 , n21673 , n21674 , n21675 , n21676 , n21677 , n21678 , n21679 , n21680 ,
n21681 , n21682 , n21683 , n21684 , n21685 , n21686 , n21687 , n21688 , n21689 , n21690 ,
n21691 , n21692 , n21693 , n21694 , n21695 , n21696 , n21697 , n21698 , n21699 , n21700 ,
n21701 , n21702 , n21703 , n21704 , n21705 , n21706 , n21707 , n21708 , n21709 , n21710 ,
n21711 , n21712 , n21713 , n21714 , n21715 , n21716 , n21717 , n21718 , n21719 , n21720 ,
n21721 , n21722 , n21723 , n21724 , n21725 , n21726 , n21727 , n21728 , n21729 , n21730 ,
n21731 , n21732 , n21733 , n21734 , n21735 , n21736 , n21737 , n21738 , n21739 , n21740 ,
n21741 , n21742 , n21743 , n21744 , n21745 , n21746 , n21747 , n21748 , n21749 , n21750 ,
n21751 , n21752 , n21753 , n21754 , n21755 , n21756 , n21757 , n21758 , n21759 , n21760 ,
n21761 , n21762 , n21763 , n21764 , n21765 , n21766 , n21767 , n21768 , n21769 , n21770 ,
n21771 , n21772 , n21773 , n21774 , n21775 , n21776 , n21777 , n21778 , n21779 , n21780 ,
n21781 , n21782 , n21783 , n21784 , n21785 , n21786 , n21787 , n21788 , n21789 , n21790 ,
n21791 , n21792 , n21793 , n21794 , n21795 , n21796 , n21797 , n21798 , n21799 , n21800 ,
n21801 , n21802 , n21803 , n21804 , n21805 , n21806 , n21807 , n21808 , n21809 , n21810 ,
n21811 , n21812 , n21813 , n21814 , n21815 , n21816 , n21817 , n21818 , n21819 , n21820 ,
n21821 , n21822 , n21823 , n21824 , n21825 , n21826 , n21827 , n21828 , n21829 , n21830 ,
n21831 , n21832 , n21833 , n21834 , n21835 , n21836 , n21837 , n21838 , n21839 , n21840 ,
n21841 , n21842 , n21843 , n21844 , n21845 , n21846 , n21847 , n21848 , n21849 , n21850 ,
n21851 , n21852 , n21853 , n21854 , n21855 , n21856 , n21857 , n21858 , n21859 , n21860 ,
n21861 , n21862 , n21863 , n21864 , n21865 , n21866 , n21867 , n21868 , n21869 , n21870 ,
n21871 , n21872 , n21873 , n21874 , n21875 , n21876 , n21877 , n21878 , n21879 , n21880 ,
n21881 , n21882 , n21883 , n21884 , n21885 , n21886 , n21887 , n21888 , n21889 , n21890 ,
n21891 , n21892 , n21893 , n21894 , n21895 , n21896 , n21897 , n21898 , n21899 , n21900 ,
n21901 , n21902 , n21903 , n21904 , n21905 , n21906 , n21907 , n21908 , n21909 , n21910 ,
n21911 , n21912 , n21913 , n21914 , n21915 , n21916 , n21917 , n21918 , n21919 , n21920 ,
n21921 , n21922 , n21923 , n21924 , n21925 , n21926 , n21927 , n21928 , n21929 , n21930 ,
n21931 , n21932 , n21933 , n21934 , n21935 , n21936 , n21937 , n21938 , n21939 , n21940 ,
n21941 , n21942 , n21943 , n21944 , n21945 , n21946 , n21947 , n21948 , n21949 , n21950 ,
n21951 , n21952 , n21953 , n21954 , n21955 , n21956 , n21957 , n21958 , n21959 , n21960 ,
n21961 , n21962 , n21963 , n21964 , n21965 , n21966 , n21967 , n21968 , n21969 , n21970 ,
n21971 , n21972 , n21973 , n21974 , n21975 , n21976 , n21977 , n21978 , n21979 , n21980 ,
n21981 , n21982 , n21983 , n21984 , n21985 , n21986 , n21987 , n21988 , n21989 , n21990 ,
n21991 , n21992 , n21993 , n21994 , n21995 , n21996 , n21997 , n21998 , n21999 , n22000 ,
n22001 , n22002 , n22003 , n22004 , n22005 , n22006 , n22007 , n22008 , n22009 , n22010 ,
n22011 , n22012 , n22013 , n22014 , n22015 , n22016 , n22017 , n22018 , n22019 , n22020 ,
n22021 , n22022 , n22023 , n22024 , n22025 , n22026 , n22027 , n22028 , n22029 , n22030 ,
n22031 , n22032 , n22033 , n22034 , n22035 , n22036 , n22037 , n22038 , n22039 , n22040 ,
n22041 , n22042 , n22043 , n22044 , n22045 , n22046 , n22047 , n22048 , n22049 , n22050 ,
n22051 , n22052 , n22053 , n22054 , n22055 , n22056 , n22057 , n22058 , n22059 , n22060 ,
n22061 , n22062 , n22063 , n22064 , n22065 , n22066 , n22067 , n22068 , n22069 , n22070 ,
n22071 , n22072 , n22073 , n22074 , n22075 , n22076 , n22077 , n22078 , n22079 , n22080 ,
n22081 , n22082 , n22083 , n22084 , n22085 , n22086 , n22087 , n22088 , n22089 , n22090 ,
n22091 , n22092 , n22093 , n22094 , n22095 , n22096 , n22097 , n22098 , n22099 , n22100 ,
n22101 , n22102 , n22103 , n22104 , n22105 , n22106 , n22107 , n22108 , n22109 , n22110 ,
n22111 , n22112 , n22113 , n22114 , n22115 , n22116 , n22117 , n22118 , n22119 , n22120 ,
n22121 , n22122 , n22123 , n22124 , n22125 , n22126 , n22127 , n22128 , n22129 , n22130 ,
n22131 , n22132 , n22133 , n22134 , n22135 , n22136 , n22137 , n22138 , n22139 , n22140 ,
n22141 , n22142 , n22143 , n22144 , n22145 , n22146 , n22147 , n22148 , n22149 , n22150 ,
n22151 , n22152 , n22153 , n22154 , n22155 , n22156 , n22157 , n22158 , n22159 , n22160 ,
n22161 , n22162 , n22163 , n22164 , n22165 , n22166 , n22167 , n22168 , n22169 , n22170 ,
n22171 , n22172 , n22173 , n22174 , n22175 , n22176 , n22177 , n22178 , n22179 , n22180 ,
n22181 , n22182 , n22183 , n22184 , n22185 , n22186 , n22187 , n22188 , n22189 , n22190 ,
n22191 , n22192 , n22193 , n22194 , n22195 , n22196 , n22197 , n22198 , n22199 , n22200 ,
n22201 , n22202 , n22203 , n22204 , n22205 , n22206 , n22207 , n22208 , n22209 , n22210 ,
n22211 , n22212 , n22213 , n22214 , n22215 , n22216 , n22217 , n22218 , n22219 , n22220 ,
n22221 , n22222 , n22223 , n22224 , n22225 , n22226 , n22227 , n22228 , n22229 , n22230 ,
n22231 , n22232 , n22233 , n22234 , n22235 , n22236 , n22237 , n22238 , n22239 , n22240 ,
n22241 , n22242 , n22243 , n22244 , n22245 , n22246 , n22247 , n22248 , n22249 , n22250 ,
n22251 , n22252 , n22253 , n22254 , n22255 , n22256 , n22257 , n22258 , n22259 , n22260 ,
n22261 , n22262 , n22263 , n22264 , n22265 , n22266 , n22267 , n22268 , n22269 , n22270 ,
n22271 , n22272 , n22273 , n22274 , n22275 , n22276 , n22277 , n22278 , n22279 , n22280 ,
n22281 , n22282 , n22283 , n22284 , n22285 , n22286 , n22287 , n22288 , n22289 , n22290 ,
n22291 , n22292 , n22293 , n22294 , n22295 , n22296 , n22297 , n22298 , n22299 , n22300 ,
n22301 , n22302 , n22303 , n22304 , n22305 , n22306 , n22307 , n22308 , n22309 , n22310 ,
n22311 , n22312 , n22313 , n22314 , n22315 , n22316 , n22317 , n22318 , n22319 , n22320 ,
n22321 , n22322 , n22323 , n22324 , n22325 , n22326 , n22327 , n22328 , n22329 , n22330 ,
n22331 , n22332 , n22333 , n22334 , n22335 , n22336 , n22337 , n22338 , n22339 , n22340 ,
n22341 , n22342 , n22343 , n22344 , n22345 , n22346 , n22347 , n22348 , n22349 , n22350 ,
n22351 , n22352 , n22353 , n22354 , n22355 , n22356 , n22357 , n22358 , n22359 , n22360 ,
n22361 , n22362 , n22363 , n22364 , n22365 , n22366 , n22367 , n22368 , n22369 , n22370 ,
n22371 , n22372 , n22373 , n22374 , n22375 , n22376 , n22377 , n22378 , n22379 , n22380 ,
n22381 , n22382 , n22383 , n22384 , n22385 , n22386 , n22387 , n22388 , n22389 , n22390 ,
n22391 , n22392 , n22393 , n22394 , n22395 , n22396 , n22397 , n22398 , n22399 , n22400 ,
n22401 , n22402 , n22403 , n22404 , n22405 , n22406 , n22407 , n22408 , n22409 , n22410 ,
n22411 , n22412 , n22413 , n22414 , n22415 , n22416 , n22417 , n22418 , n22419 , n22420 ,
n22421 , n22422 , n22423 , n22424 , n22425 , n22426 , n22427 , n22428 , n22429 , n22430 ,
n22431 , n22432 , n22433 , n22434 , n22435 , n22436 , n22437 , n22438 , n22439 , n22440 ,
n22441 , n22442 , n22443 , n22444 , n22445 , n22446 , n22447 , n22448 , n22449 , n22450 ,
n22451 , n22452 , n22453 , n22454 , n22455 , n22456 , n22457 , n22458 , n22459 , n22460 ,
n22461 , n22462 , n22463 , n22464 , n22465 , n22466 , n22467 , n22468 , n22469 , n22470 ,
n22471 , n22472 , n22473 , n22474 , n22475 , n22476 , n22477 , n22478 , n22479 , n22480 ,
n22481 , n22482 , n22483 , n22484 , n22485 , n22486 , n22487 , n22488 , n22489 , n22490 ,
n22491 , n22492 , n22493 , n22494 , n22495 , n22496 , n22497 , n22498 , n22499 , n22500 ,
n22501 , n22502 , n22503 , n22504 , n22505 , n22506 , n22507 , n22508 , n22509 , n22510 ,
n22511 , n22512 , n22513 , n22514 , n22515 , n22516 , n22517 , n22518 , n22519 , n22520 ,
n22521 , n22522 , n22523 , n22524 , n22525 , n22526 , n22527 , n22528 , n22529 , n22530 ,
n22531 , n22532 , n22533 , n22534 , n22535 , n22536 , n22537 , n22538 , n22539 , n22540 ,
n22541 , n22542 , n22543 , n22544 , n22545 , n22546 , n22547 , n22548 , n22549 , n22550 ,
n22551 , n22552 , n22553 , n22554 , n22555 , n22556 , n22557 , n22558 , n22559 , n22560 ,
n22561 , n22562 , n22563 , n22564 , n22565 , n22566 , n22567 , n22568 , n22569 , n22570 ,
n22571 , n22572 , n22573 , n22574 , n22575 , n22576 , n22577 , n22578 , n22579 , n22580 ,
n22581 , n22582 , n22583 , n22584 , n22585 , n22586 , n22587 , n22588 , n22589 , n22590 ,
n22591 , n22592 , n22593 , n22594 , n22595 , n22596 , n22597 , n22598 , n22599 , n22600 ,
n22601 , n22602 , n22603 , n22604 , n22605 , n22606 , n22607 , n22608 , n22609 , n22610 ,
n22611 , n22612 , n22613 , n22614 , n22615 , n22616 , n22617 , n22618 , n22619 , n22620 ,
n22621 , n22622 , n22623 , n22624 , n22625 , n22626 , n22627 , n22628 , n22629 , n22630 ,
n22631 , n22632 , n22633 , n22634 , n22635 , n22636 , n22637 , n22638 , n22639 , n22640 ,
n22641 , n22642 , n22643 , n22644 , n22645 , n22646 , n22647 , n22648 , n22649 , n22650 ,
n22651 , n22652 , n22653 , n22654 , n22655 , n22656 , n22657 , n22658 , n22659 , n22660 ,
n22661 , n22662 , n22663 , n22664 , n22665 , n22666 , n22667 , n22668 , n22669 , n22670 ,
n22671 , n22672 , n22673 , n22674 , n22675 , n22676 , n22677 , n22678 , n22679 , n22680 ,
n22681 , n22682 , n22683 , n22684 , n22685 , n22686 , n22687 , n22688 , n22689 , n22690 ,
n22691 , n22692 , n22693 , n22694 , n22695 , n22696 , n22697 , n22698 , n22699 , n22700 ,
n22701 , n22702 , n22703 , n22704 , n22705 , n22706 , n22707 , n22708 , n22709 , n22710 ,
n22711 , n22712 , n22713 , n22714 , n22715 , n22716 , n22717 , n22718 , n22719 , n22720 ,
n22721 , n22722 , n22723 , n22724 , n22725 , n22726 , n22727 , n22728 , n22729 , n22730 ,
n22731 , n22732 , n22733 , n22734 , n22735 , n22736 , n22737 , n22738 , n22739 , n22740 ,
n22741 , n22742 , n22743 , n22744 , n22745 , n22746 , n22747 , n22748 , n22749 , n22750 ,
n22751 , n22752 , n22753 , n22754 , n22755 , n22756 , n22757 , n22758 , n22759 , n22760 ,
n22761 , n22762 , n22763 , n22764 , n22765 , n22766 , n22767 , n22768 , n22769 , n22770 ,
n22771 , n22772 , n22773 , n22774 , n22775 , n22776 , n22777 , n22778 , n22779 , n22780 ,
n22781 , n22782 , n22783 , n22784 , n22785 , n22786 , n22787 , n22788 , n22789 , n22790 ,
n22791 , n22792 , n22793 , n22794 , n22795 , n22796 , n22797 , n22798 , n22799 , n22800 ,
n22801 , n22802 , n22803 , n22804 , n22805 , n22806 , n22807 , n22808 , n22809 , n22810 ,
n22811 , n22812 , n22813 , n22814 , n22815 , n22816 , n22817 , n22818 , n22819 , n22820 ,
n22821 , n22822 , n22823 , n22824 , n22825 , n22826 , n22827 , n22828 , n22829 , n22830 ,
n22831 , n22832 , n22833 , n22834 , n22835 , n22836 , n22837 , n22838 , n22839 , n22840 ,
n22841 , n22842 , n22843 , n22844 , n22845 , n22846 , n22847 , n22848 , n22849 , n22850 ,
n22851 , n22852 , n22853 , n22854 , n22855 , n22856 , n22857 , n22858 , n22859 , n22860 ,
n22861 , n22862 , n22863 , n22864 , n22865 , n22866 , n22867 , n22868 , n22869 , n22870 ,
n22871 , n22872 , n22873 , n22874 , n22875 , n22876 , n22877 , n22878 , n22879 , n22880 ,
n22881 , n22882 , n22883 , n22884 , n22885 , n22886 , n22887 , n22888 , n22889 , n22890 ,
n22891 , n22892 , n22893 , n22894 , n22895 , n22896 , n22897 , n22898 , n22899 , n22900 ,
n22901 , n22902 , n22903 , n22904 , n22905 , n22906 , n22907 , n22908 , n22909 , n22910 ,
n22911 , n22912 , n22913 , n22914 , n22915 , n22916 , n22917 , n22918 , n22919 , n22920 ,
n22921 , n22922 , n22923 , n22924 , n22925 , n22926 , n22927 , n22928 , n22929 , n22930 ,
n22931 , n22932 , n22933 , n22934 , n22935 , n22936 , n22937 , n22938 , n22939 , n22940 ,
n22941 , n22942 , n22943 , n22944 , n22945 , n22946 , n22947 , n22948 , n22949 , n22950 ,
n22951 , n22952 , n22953 , n22954 , n22955 , n22956 , n22957 , n22958 , n22959 , n22960 ,
n22961 , n22962 , n22963 , n22964 , n22965 , n22966 , n22967 , n22968 , n22969 , n22970 ,
n22971 , n22972 , n22973 , n22974 , n22975 , n22976 , n22977 , n22978 , n22979 , n22980 ,
n22981 , n22982 , n22983 , n22984 , n22985 , n22986 , n22987 , n22988 , n22989 , n22990 ,
n22991 , n22992 , n22993 , n22994 , n22995 , n22996 , n22997 , n22998 , n22999 , n23000 ,
n23001 , n23002 , n23003 , n23004 , n23005 , n23006 , n23007 , n23008 , n23009 , n23010 ,
n23011 , n23012 , n23013 , n23014 , n23015 , n23016 , n23017 , n23018 , n23019 , n23020 ,
n23021 , n23022 , n23023 , n23024 , n23025 , n23026 , n23027 , n23028 , n23029 , n23030 ,
n23031 , n23032 , n23033 , n23034 , n23035 , n23036 , n23037 , n23038 , n23039 , n23040 ,
n23041 , n23042 , n23043 , n23044 , n23045 , n23046 , n23047 , n23048 , n23049 , n23050 ,
n23051 , n23052 , n23053 , n23054 , n23055 , n23056 , n23057 , n23058 , n23059 , n23060 ,
n23061 , n23062 , n23063 , n23064 , n23065 , n23066 , n23067 , n23068 , n23069 , n23070 ,
n23071 , n23072 , n23073 , n23074 , n23075 , n23076 , n23077 , n23078 , n23079 , n23080 ,
n23081 , n23082 , n23083 , n23084 , n23085 , n23086 , n23087 , n23088 , n23089 , n23090 ,
n23091 , n23092 , n23093 , n23094 , n23095 , n23096 , n23097 , n23098 , n23099 , n23100 ,
n23101 , n23102 , n23103 , n23104 , n23105 , n23106 , n23107 , n23108 , n23109 , n23110 ,
n23111 , n23112 , n23113 , n23114 , n23115 , n23116 , n23117 , n23118 , n23119 , n23120 ,
n23121 , n23122 , n23123 , n23124 , n23125 , n23126 , n23127 , n23128 , n23129 , n23130 ,
n23131 , n23132 , n23133 , n23134 , n23135 , n23136 , n23137 , n23138 , n23139 , n23140 ,
n23141 , n23142 , n23143 , n23144 , n23145 , n23146 , n23147 , n23148 , n23149 , n23150 ,
n23151 , n23152 , n23153 , n23154 , n23155 , n23156 , n23157 , n23158 , n23159 , n23160 ,
n23161 , n23162 , n23163 , n23164 , n23165 , n23166 , n23167 , n23168 , n23169 , n23170 ,
n23171 , n23172 , n23173 , n23174 , n23175 , n23176 , n23177 , n23178 , n23179 , n23180 ,
n23181 , n23182 , n23183 , n23184 , n23185 , n23186 , n23187 , n23188 , n23189 , n23190 ,
n23191 , n23192 , n23193 , n23194 , n23195 , n23196 , n23197 , n23198 , n23199 , n23200 ,
n23201 , n23202 , n23203 , n23204 , n23205 , n23206 , n23207 , n23208 , n23209 , n23210 ,
n23211 , n23212 , n23213 , n23214 , n23215 , n23216 , n23217 , n23218 , n23219 , n23220 ,
n23221 , n23222 , n23223 , n23224 , n23225 , n23226 , n23227 , n23228 , n23229 , n23230 ,
n23231 , n23232 , n23233 , n23234 , n23235 , n23236 , n23237 , n23238 , n23239 , n23240 ,
n23241 , n23242 , n23243 , n23244 , n23245 , n23246 , n23247 , n23248 , n23249 , n23250 ,
n23251 , n23252 , n23253 , n23254 , n23255 , n23256 , n23257 , n23258 , n23259 , n23260 ,
n23261 , n23262 , n23263 , n23264 , n23265 , n23266 , n23267 , n23268 , n23269 , n23270 ,
n23271 , n23272 , n23273 , n23274 , n23275 , n23276 , n23277 , n23278 , n23279 , n23280 ,
n23281 , n23282 , n23283 , n23284 , n23285 , n23286 , n23287 , n23288 , n23289 , n23290 ,
n23291 , n23292 , n23293 , n23294 , n23295 , n23296 , n23297 , n23298 , n23299 , n23300 ,
n23301 , n23302 , n23303 , n23304 , n23305 , n23306 , n23307 , n23308 , n23309 , n23310 ,
n23311 , n23312 , n23313 , n23314 , n23315 , n23316 , n23317 , n23318 , n23319 , n23320 ,
n23321 , n23322 , n23323 , n23324 , n23325 , n23326 , n23327 , n23328 , n23329 , n23330 ,
n23331 , n23332 , n23333 , n23334 , n23335 , n23336 , n23337 , n23338 , n23339 , n23340 ,
n23341 , n23342 , n23343 , n23344 , n23345 , n23346 , n23347 , n23348 , n23349 , n23350 ,
n23351 , n23352 , n23353 , n23354 , n23355 , n23356 , n23357 , n23358 , n23359 , n23360 ,
n23361 , n23362 , n23363 , n23364 , n23365 , n23366 , n23367 , n23368 , n23369 , n23370 ,
n23371 , n23372 , n23373 , n23374 , n23375 , n23376 , n23377 , n23378 , n23379 , n23380 ,
n23381 , n23382 , n23383 , n23384 , n23385 , n23386 , n23387 , n23388 , n23389 , n23390 ,
n23391 , n23392 , n23393 , n23394 , n23395 , n23396 , n23397 , n23398 , n23399 , n23400 ,
n23401 , n23402 , n23403 , n23404 , n23405 , n23406 , n23407 , n23408 , n23409 , n23410 ,
n23411 , n23412 , n23413 , n23414 , n23415 , n23416 , n23417 , n23418 , n23419 , n23420 ,
n23421 , n23422 , n23423 , n23424 , n23425 , n23426 , n23427 , n23428 , n23429 , n23430 ,
n23431 , n23432 , n23433 , n23434 , n23435 , n23436 , n23437 , n23438 , n23439 , n23440 ,
n23441 , n23442 , n23443 , n23444 , n23445 , n23446 , n23447 , n23448 , n23449 , n23450 ,
n23451 , n23452 , n23453 , n23454 , n23455 , n23456 , n23457 , n23458 , n23459 , n23460 ,
n23461 , n23462 , n23463 , n23464 , n23465 , n23466 , n23467 , n23468 , n23469 , n23470 ,
n23471 , n23472 , n23473 , n23474 , n23475 , n23476 , n23477 , n23478 , n23479 , n23480 ,
n23481 , n23482 , n23483 , n23484 , n23485 , n23486 , n23487 , n23488 , n23489 , n23490 ,
n23491 , n23492 , n23493 , n23494 , n23495 , n23496 , n23497 , n23498 , n23499 , n23500 ,
n23501 , n23502 , n23503 , n23504 , n23505 , n23506 , n23507 , n23508 , n23509 , n23510 ,
n23511 , n23512 , n23513 , n23514 , n23515 , n23516 , n23517 , n23518 , n23519 , n23520 ,
n23521 , n23522 , n23523 , n23524 , n23525 , n23526 , n23527 , n23528 , n23529 , n23530 ,
n23531 , n23532 , n23533 , n23534 , n23535 , n23536 , n23537 , n23538 , n23539 , n23540 ,
n23541 , n23542 , n23543 , n23544 , n23545 , n23546 , n23547 , n23548 , n23549 , n23550 ,
n23551 , n23552 , n23553 , n23554 , n23555 , n23556 , n23557 , n23558 , n23559 , n23560 ,
n23561 , n23562 , n23563 , n23564 , n23565 , n23566 , n23567 , n23568 , n23569 , n23570 ,
n23571 , n23572 , n23573 , n23574 , n23575 , n23576 , n23577 , n23578 , n23579 , n23580 ,
n23581 , n23582 , n23583 , n23584 , n23585 , n23586 , n23587 , n23588 , n23589 , n23590 ,
n23591 , n23592 , n23593 , n23594 , n23595 , n23596 , n23597 , n23598 , n23599 , n23600 ,
n23601 , n23602 , n23603 , n23604 , n23605 , n23606 , n23607 , n23608 , n23609 , n23610 ,
n23611 , n23612 , n23613 , n23614 , n23615 , n23616 , n23617 , n23618 , n23619 , n23620 ,
n23621 , n23622 , n23623 , n23624 , n23625 , n23626 , n23627 , n23628 , n23629 , n23630 ,
n23631 , n23632 , n23633 , n23634 , n23635 , n23636 , n23637 , n23638 , n23639 , n23640 ,
n23641 , n23642 , n23643 , n23644 , n23645 , n23646 , n23647 , n23648 , n23649 , n23650 ,
n23651 , n23652 , n23653 , n23654 , n23655 , n23656 , n23657 , n23658 , n23659 , n23660 ,
n23661 , n23662 , n23663 , n23664 , n23665 , n23666 , n23667 , n23668 , n23669 , n23670 ,
n23671 , n23672 , n23673 , n23674 , n23675 , n23676 , n23677 , n23678 , n23679 , n23680 ,
n23681 , n23682 , n23683 , n23684 , n23685 , n23686 , n23687 , n23688 , n23689 , n23690 ,
n23691 , n23692 , n23693 , n23694 , n23695 , n23696 , n23697 , n23698 , n23699 , n23700 ,
n23701 , n23702 , n23703 , n23704 , n23705 , n23706 , n23707 , n23708 , n23709 , n23710 ,
n23711 , n23712 , n23713 , n23714 , n23715 , n23716 , n23717 , n23718 , n23719 , n23720 ,
n23721 , n23722 , n23723 , n23724 , n23725 , n23726 , n23727 , n23728 , n23729 , n23730 ,
n23731 , n23732 , n23733 , n23734 , n23735 , n23736 , n23737 , n23738 , n23739 , n23740 ,
n23741 , n23742 , n23743 , n23744 , n23745 , n23746 , n23747 , n23748 , n23749 , n23750 ,
n23751 , n23752 , n23753 , n23754 , n23755 , n23756 , n23757 , n23758 , n23759 , n23760 ,
n23761 , n23762 , n23763 , n23764 , n23765 , n23766 , n23767 , n23768 , n23769 , n23770 ,
n23771 , n23772 , n23773 , n23774 , n23775 , n23776 , n23777 , n23778 , n23779 , n23780 ,
n23781 , n23782 , n23783 , n23784 , n23785 , n23786 , n23787 , n23788 , n23789 , n23790 ,
n23791 , n23792 , n23793 , n23794 , n23795 , n23796 , n23797 , n23798 , n23799 , n23800 ,
n23801 , n23802 , n23803 , n23804 , n23805 , n23806 , n23807 , n23808 , n23809 , n23810 ,
n23811 , n23812 , n23813 , n23814 , n23815 , n23816 , n23817 , n23818 , n23819 , n23820 ,
n23821 , n23822 , n23823 , n23824 , n23825 , n23826 , n23827 , n23828 , n23829 , n23830 ,
n23831 , n23832 , n23833 , n23834 , n23835 , n23836 , n23837 , n23838 , n23839 , n23840 ,
n23841 , n23842 , n23843 , n23844 , n23845 , n23846 , n23847 , n23848 , n23849 , n23850 ,
n23851 , n23852 , n23853 , n23854 , n23855 , n23856 , n23857 , n23858 , n23859 , n23860 ,
n23861 , n23862 , n23863 , n23864 , n23865 , n23866 , n23867 , n23868 , n23869 , n23870 ,
n23871 , n23872 , n23873 , n23874 , n23875 , n23876 , n23877 , n23878 , n23879 , n23880 ,
n23881 , n23882 , n23883 , n23884 , n23885 , n23886 , n23887 , n23888 , n23889 , n23890 ,
n23891 , n23892 , n23893 , n23894 , n23895 , n23896 , n23897 , n23898 , n23899 , n23900 ,
n23901 , n23902 , n23903 , n23904 , n23905 , n23906 , n23907 , n23908 , n23909 , n23910 ,
n23911 , n23912 , n23913 , n23914 , n23915 , n23916 , n23917 , n23918 , n23919 , n23920 ,
n23921 , n23922 , n23923 , n23924 , n23925 , n23926 , n23927 , n23928 , n23929 , n23930 ,
n23931 , n23932 , n23933 , n23934 , n23935 , n23936 , n23937 , n23938 , n23939 , n23940 ,
n23941 , n23942 , n23943 , n23944 , n23945 , n23946 , n23947 , n23948 , n23949 , n23950 ,
n23951 , n23952 , n23953 , n23954 , n23955 , n23956 , n23957 , n23958 , n23959 , n23960 ,
n23961 , n23962 , n23963 , n23964 , n23965 , n23966 , n23967 , n23968 , n23969 , n23970 ,
n23971 , n23972 , n23973 , n23974 , n23975 , n23976 , n23977 , n23978 , n23979 , n23980 ,
n23981 , n23982 , n23983 , n23984 , n23985 , n23986 , n23987 , n23988 , n23989 , n23990 ,
n23991 , n23992 , n23993 , n23994 , n23995 , n23996 , n23997 , n23998 , n23999 , n24000 ,
n24001 , n24002 , n24003 , n24004 , n24005 , n24006 , n24007 , n24008 , n24009 , n24010 ,
n24011 , n24012 , n24013 , n24014 , n24015 , n24016 , n24017 , n24018 , n24019 , n24020 ,
n24021 , n24022 , n24023 , n24024 , n24025 , n24026 , n24027 , n24028 , n24029 , n24030 ,
n24031 , n24032 , n24033 , n24034 , n24035 , n24036 , n24037 , n24038 , n24039 , n24040 ,
n24041 , n24042 , n24043 , n24044 , n24045 , n24046 , n24047 , n24048 , n24049 , n24050 ,
n24051 , n24052 , n24053 , n24054 , n24055 , n24056 , n24057 , n24058 , n24059 , n24060 ,
n24061 , n24062 , n24063 , n24064 , n24065 , n24066 , n24067 , n24068 , n24069 , n24070 ,
n24071 , n24072 , n24073 , n24074 , n24075 , n24076 , n24077 , n24078 , n24079 , n24080 ,
n24081 , n24082 , n24083 , n24084 , n24085 , n24086 , n24087 , n24088 , n24089 , n24090 ,
n24091 , n24092 , n24093 , n24094 , n24095 , n24096 , n24097 , n24098 , n24099 , n24100 ,
n24101 , n24102 , n24103 , n24104 , n24105 , n24106 , n24107 , n24108 , n24109 , n24110 ,
n24111 , n24112 , n24113 , n24114 , n24115 , n24116 , n24117 , n24118 , n24119 , n24120 ,
n24121 , n24122 , n24123 , n24124 , n24125 , n24126 , n24127 , n24128 , n24129 , n24130 ,
n24131 , n24132 , n24133 , n24134 , n24135 , n24136 , n24137 , n24138 , n24139 , n24140 ,
n24141 , n24142 , n24143 , n24144 , n24145 , n24146 , n24147 , n24148 , n24149 , n24150 ,
n24151 , n24152 , n24153 , n24154 , n24155 , n24156 , n24157 , n24158 , n24159 , n24160 ,
n24161 , n24162 , n24163 , n24164 , n24165 , n24166 , n24167 , n24168 , n24169 , n24170 ,
n24171 , n24172 , n24173 , n24174 , n24175 , n24176 , n24177 , n24178 , n24179 , n24180 ,
n24181 , n24182 , n24183 , n24184 , n24185 , n24186 , n24187 , n24188 , n24189 , n24190 ,
n24191 , n24192 , n24193 , n24194 , n24195 , n24196 , n24197 , n24198 , n24199 , n24200 ,
n24201 , n24202 , n24203 , n24204 , n24205 , n24206 , n24207 , n24208 , n24209 , n24210 ,
n24211 , n24212 , n24213 , n24214 , n24215 , n24216 , n24217 , n24218 , n24219 , n24220 ,
n24221 , n24222 , n24223 , n24224 , n24225 , n24226 , n24227 , n24228 , n24229 , n24230 ,
n24231 , n24232 , n24233 , n24234 , n24235 , n24236 , n24237 , n24238 , n24239 , n24240 ,
n24241 , n24242 , n24243 , n24244 , n24245 , n24246 , n24247 , n24248 , n24249 , n24250 ,
n24251 , n24252 , n24253 , n24254 , n24255 , n24256 , n24257 , n24258 , n24259 , n24260 ,
n24261 , n24262 , n24263 , n24264 , n24265 , n24266 , n24267 , n24268 , n24269 , n24270 ,
n24271 , n24272 , n24273 , n24274 , n24275 , n24276 , n24277 , n24278 , n24279 , n24280 ,
n24281 , n24282 , n24283 , n24284 , n24285 , n24286 , n24287 , n24288 , n24289 , n24290 ,
n24291 , n24292 , n24293 , n24294 , n24295 , n24296 , n24297 , n24298 , n24299 , n24300 ,
n24301 , n24302 , n24303 , n24304 , n24305 , n24306 , n24307 , n24308 , n24309 , n24310 ,
n24311 , n24312 , n24313 , n24314 , n24315 , n24316 , n24317 , n24318 , n24319 , n24320 ,
n24321 , n24322 , n24323 , n24324 , n24325 , n24326 , n24327 , n24328 , n24329 , n24330 ,
n24331 , n24332 , n24333 , n24334 , n24335 , n24336 , n24337 , n24338 , n24339 , n24340 ,
n24341 , n24342 , n24343 , n24344 , n24345 , n24346 , n24347 , n24348 , n24349 , n24350 ,
n24351 , n24352 , n24353 , n24354 , n24355 , n24356 , n24357 , n24358 , n24359 , n24360 ,
n24361 , n24362 , n24363 , n24364 , n24365 , n24366 , n24367 , n24368 , n24369 , n24370 ,
n24371 , n24372 , n24373 , n24374 , n24375 , n24376 , n24377 , n24378 , n24379 , n24380 ,
n24381 , n24382 , n24383 , n24384 , n24385 , n24386 , n24387 , n24388 , n24389 , n24390 ,
n24391 , n24392 , n24393 , n24394 , n24395 , n24396 , n24397 , n24398 , n24399 , n24400 ,
n24401 , n24402 , n24403 , n24404 , n24405 , n24406 , n24407 , n24408 , n24409 , n24410 ,
n24411 , n24412 , n24413 , n24414 , n24415 , n24416 , n24417 , n24418 , n24419 , n24420 ,
n24421 , n24422 , n24423 , n24424 , n24425 , n24426 , n24427 , n24428 , n24429 , n24430 ,
n24431 , n24432 , n24433 , n24434 , n24435 , n24436 , n24437 , n24438 , n24439 , n24440 ,
n24441 , n24442 , n24443 , n24444 , n24445 , n24446 , n24447 , n24448 , n24449 , n24450 ,
n24451 , n24452 , n24453 , n24454 , n24455 , n24456 , n24457 , n24458 , n24459 , n24460 ,
n24461 , n24462 , n24463 , n24464 , n24465 , n24466 , n24467 , n24468 , n24469 , n24470 ,
n24471 , n24472 , n24473 , n24474 , n24475 , n24476 , n24477 , n24478 , n24479 , n24480 ,
n24481 , n24482 , n24483 , n24484 , n24485 , n24486 , n24487 , n24488 , n24489 , n24490 ,
n24491 , n24492 , n24493 , n24494 , n24495 , n24496 , n24497 , n24498 , n24499 , n24500 ,
n24501 , n24502 , n24503 , n24504 , n24505 , n24506 , n24507 , n24508 , n24509 , n24510 ,
n24511 , n24512 , n24513 , n24514 , n24515 , n24516 , n24517 , n24518 , n24519 , n24520 ,
n24521 , n24522 , n24523 , n24524 , n24525 , n24526 , n24527 , n24528 , n24529 , n24530 ,
n24531 , n24532 , n24533 , n24534 , n24535 , n24536 , n24537 , n24538 , n24539 , n24540 ,
n24541 , n24542 , n24543 , n24544 , n24545 , n24546 , n24547 , n24548 , n24549 , n24550 ,
n24551 , n24552 , n24553 , n24554 , n24555 , n24556 , n24557 , n24558 , n24559 , n24560 ,
n24561 , n24562 , n24563 , n24564 , n24565 , n24566 , n24567 , n24568 , n24569 , n24570 ,
n24571 , n24572 , n24573 , n24574 , n24575 , n24576 , n24577 , n24578 , n24579 , n24580 ,
n24581 , n24582 , n24583 , n24584 , n24585 , n24586 , n24587 , n24588 , n24589 , n24590 ,
n24591 , n24592 , n24593 , n24594 , n24595 , n24596 , n24597 , n24598 , n24599 , n24600 ,
n24601 , n24602 , n24603 , n24604 , n24605 , n24606 , n24607 , n24608 , n24609 , n24610 ,
n24611 , n24612 , n24613 , n24614 , n24615 , n24616 , n24617 , n24618 , n24619 , n24620 ,
n24621 , n24622 , n24623 , n24624 , n24625 , n24626 , n24627 , n24628 , n24629 , n24630 ,
n24631 , n24632 , n24633 , n24634 , n24635 , n24636 , n24637 , n24638 , n24639 , n24640 ,
n24641 , n24642 , n24643 , n24644 , n24645 , n24646 , n24647 , n24648 , n24649 , n24650 ,
n24651 , n24652 , n24653 , n24654 , n24655 , n24656 , n24657 , n24658 , n24659 , n24660 ,
n24661 , n24662 , n24663 , n24664 , n24665 , n24666 , n24667 , n24668 , n24669 , n24670 ,
n24671 , n24672 , n24673 , n24674 , n24675 , n24676 , n24677 , n24678 , n24679 , n24680 ,
n24681 , n24682 , n24683 , n24684 , n24685 , n24686 , n24687 , n24688 , n24689 , n24690 ,
n24691 , n24692 , n24693 , n24694 , n24695 , n24696 , n24697 , n24698 , n24699 , n24700 ,
n24701 , n24702 , n24703 , n24704 , n24705 , n24706 , n24707 , n24708 , n24709 , n24710 ,
n24711 , n24712 , n24713 , n24714 , n24715 , n24716 , n24717 , n24718 , n24719 , n24720 ,
n24721 , n24722 , n24723 , n24724 , n24725 , n24726 , n24727 , n24728 , n24729 , n24730 ,
n24731 , n24732 , n24733 , n24734 , n24735 , n24736 , n24737 , n24738 , n24739 , n24740 ,
n24741 , n24742 , n24743 , n24744 , n24745 , n24746 , n24747 , n24748 , n24749 , n24750 ,
n24751 , n24752 , n24753 , n24754 , n24755 , n24756 , n24757 , n24758 , n24759 , n24760 ,
n24761 , n24762 , n24763 , n24764 , n24765 , n24766 , n24767 , n24768 , n24769 , n24770 ,
n24771 , n24772 , n24773 , n24774 , n24775 , n24776 , n24777 , n24778 , n24779 , n24780 ,
n24781 , n24782 , n24783 , n24784 , n24785 , n24786 , n24787 , n24788 , n24789 , n24790 ,
n24791 , n24792 , n24793 , n24794 , n24795 , n24796 , n24797 , n24798 , n24799 , n24800 ,
n24801 , n24802 , n24803 , n24804 , n24805 , n24806 , n24807 , n24808 , n24809 , n24810 ,
n24811 , n24812 , n24813 , n24814 , n24815 , n24816 , n24817 , n24818 , n24819 , n24820 ,
n24821 , n24822 , n24823 , n24824 , n24825 , n24826 , n24827 , n24828 , n24829 , n24830 ,
n24831 , n24832 , n24833 , n24834 , n24835 , n24836 , n24837 , n24838 , n24839 , n24840 ,
n24841 , n24842 , n24843 , n24844 , n24845 , n24846 , n24847 , n24848 , n24849 , n24850 ,
n24851 , n24852 , n24853 , n24854 , n24855 , n24856 , n24857 , n24858 , n24859 , n24860 ,
n24861 , n24862 , n24863 , n24864 , n24865 , n24866 , n24867 , n24868 , n24869 , n24870 ,
n24871 , n24872 , n24873 , n24874 , n24875 , n24876 , n24877 , n24878 , n24879 , n24880 ,
n24881 , n24882 , n24883 , n24884 , n24885 , n24886 , n24887 , n24888 , n24889 , n24890 ,
n24891 , n24892 , n24893 , n24894 , n24895 , n24896 , n24897 , n24898 , n24899 , n24900 ,
n24901 , n24902 , n24903 , n24904 , n24905 , n24906 , n24907 , n24908 , n24909 , n24910 ,
n24911 , n24912 , n24913 , n24914 , n24915 , n24916 , n24917 , n24918 , n24919 , n24920 ,
n24921 , n24922 , n24923 , n24924 , n24925 , n24926 , n24927 , n24928 , n24929 , n24930 ,
n24931 , n24932 , n24933 , n24934 , n24935 , n24936 , n24937 , n24938 , n24939 , n24940 ,
n24941 , n24942 , n24943 , n24944 , n24945 , n24946 , n24947 , n24948 , n24949 , n24950 ,
n24951 , n24952 , n24953 , n24954 , n24955 , n24956 , n24957 , n24958 , n24959 , n24960 ,
n24961 , n24962 , n24963 , n24964 , n24965 , n24966 , n24967 , n24968 , n24969 , n24970 ,
n24971 , n24972 , n24973 , n24974 , n24975 , n24976 , n24977 , n24978 , n24979 , n24980 ,
n24981 , n24982 , n24983 , n24984 , n24985 , n24986 , n24987 , n24988 , n24989 , n24990 ,
n24991 , n24992 , n24993 , n24994 , n24995 , n24996 , n24997 , n24998 , n24999 , n25000 ,
n25001 , n25002 , n25003 , n25004 , n25005 , n25006 , n25007 , n25008 , n25009 , n25010 ,
n25011 , n25012 , n25013 , n25014 , n25015 , n25016 , n25017 , n25018 , n25019 , n25020 ,
n25021 , n25022 , n25023 , n25024 , n25025 , n25026 , n25027 , n25028 , n25029 , n25030 ,
n25031 , n25032 , n25033 , n25034 , n25035 , n25036 , n25037 , n25038 , n25039 , n25040 ,
n25041 , n25042 , n25043 , n25044 , n25045 , n25046 , n25047 , n25048 , n25049 , n25050 ,
n25051 , n25052 , n25053 , n25054 , n25055 , n25056 , n25057 , n25058 , n25059 , n25060 ,
n25061 , n25062 , n25063 , n25064 , n25065 , n25066 , n25067 , n25068 , n25069 , n25070 ,
n25071 , n25072 , n25073 , n25074 , n25075 , n25076 , n25077 , n25078 , n25079 , n25080 ,
n25081 , n25082 , n25083 , n25084 , n25085 , n25086 , n25087 , n25088 , n25089 , n25090 ,
n25091 , n25092 , n25093 , n25094 , n25095 , n25096 , n25097 , n25098 , n25099 , n25100 ,
n25101 , n25102 , n25103 , n25104 , n25105 , n25106 , n25107 , n25108 , n25109 , n25110 ,
n25111 , n25112 , n25113 , n25114 , n25115 , n25116 , n25117 , n25118 , n25119 , n25120 ,
n25121 , n25122 , n25123 , n25124 , n25125 , n25126 , n25127 , n25128 , n25129 , n25130 ,
n25131 , n25132 , n25133 , n25134 , n25135 , n25136 , n25137 , n25138 , n25139 , n25140 ,
n25141 , n25142 , n25143 , n25144 , n25145 , n25146 , n25147 , n25148 , n25149 , n25150 ,
n25151 , n25152 , n25153 , n25154 , n25155 , n25156 , n25157 , n25158 , n25159 , n25160 ,
n25161 , n25162 , n25163 , n25164 , n25165 , n25166 , n25167 , n25168 , n25169 , n25170 ,
n25171 , n25172 , n25173 , n25174 , n25175 , n25176 , n25177 , n25178 , n25179 , n25180 ,
n25181 , n25182 , n25183 , n25184 , n25185 , n25186 , n25187 , n25188 , n25189 , n25190 ,
n25191 , n25192 , n25193 , n25194 , n25195 , n25196 , n25197 , n25198 , n25199 , n25200 ,
n25201 , n25202 , n25203 , n25204 , n25205 , n25206 , n25207 , n25208 , n25209 , n25210 ,
n25211 , n25212 , n25213 , n25214 , n25215 , n25216 , n25217 , n25218 , n25219 , n25220 ,
n25221 , n25222 , n25223 , n25224 , n25225 , n25226 , n25227 , n25228 , n25229 , n25230 ,
n25231 , n25232 , n25233 , n25234 , n25235 , n25236 , n25237 , n25238 , n25239 , n25240 ,
n25241 , n25242 , n25243 , n25244 , n25245 , n25246 , n25247 , n25248 , n25249 , n25250 ,
n25251 , n25252 , n25253 , n25254 , n25255 , n25256 , n25257 , n25258 , n25259 , n25260 ,
n25261 , n25262 , n25263 , n25264 , n25265 , n25266 , n25267 , n25268 , n25269 , n25270 ,
n25271 , n25272 , n25273 , n25274 , n25275 , n25276 , n25277 , n25278 , n25279 , n25280 ,
n25281 , n25282 , n25283 , n25284 , n25285 , n25286 , n25287 , n25288 , n25289 , n25290 ,
n25291 , n25292 , n25293 , n25294 , n25295 , n25296 , n25297 , n25298 , n25299 , n25300 ,
n25301 , n25302 , n25303 , n25304 , n25305 , n25306 , n25307 , n25308 , n25309 , n25310 ,
n25311 , n25312 , n25313 , n25314 , n25315 , n25316 , n25317 , n25318 , n25319 , n25320 ,
n25321 , n25322 , n25323 , n25324 , n25325 , n25326 , n25327 , n25328 , n25329 , n25330 ,
n25331 , n25332 , n25333 , n25334 , n25335 , n25336 , n25337 , n25338 , n25339 , n25340 ,
n25341 , n25342 , n25343 , n25344 , n25345 , n25346 , n25347 , n25348 , n25349 , n25350 ,
n25351 , n25352 , n25353 , n25354 , n25355 , n25356 , n25357 , n25358 , n25359 , n25360 ,
n25361 , n25362 , n25363 , n25364 , n25365 , n25366 , n25367 , n25368 , n25369 , n25370 ,
n25371 , n25372 , n25373 , n25374 , n25375 , n25376 , n25377 , n25378 , n25379 , n25380 ,
n25381 , n25382 , n25383 , n25384 , n25385 , n25386 , n25387 , n25388 , n25389 , n25390 ,
n25391 , n25392 , n25393 , n25394 , n25395 , n25396 , n25397 , n25398 , n25399 , n25400 ,
n25401 , n25402 , n25403 , n25404 , n25405 , n25406 , n25407 , n25408 , n25409 , n25410 ,
n25411 , n25412 , n25413 , n25414 , n25415 , n25416 , n25417 , n25418 , n25419 , n25420 ,
n25421 , n25422 , n25423 , n25424 , n25425 , n25426 , n25427 , n25428 , n25429 , n25430 ,
n25431 , n25432 , n25433 , n25434 , n25435 , n25436 , n25437 , n25438 , n25439 , n25440 ,
n25441 , n25442 , n25443 , n25444 , n25445 , n25446 , n25447 , n25448 , n25449 , n25450 ,
n25451 , n25452 , n25453 , n25454 , n25455 , n25456 , n25457 , n25458 , n25459 , n25460 ,
n25461 , n25462 , n25463 , n25464 , n25465 , n25466 , n25467 , n25468 , n25469 , n25470 ,
n25471 , n25472 , n25473 , n25474 , n25475 , n25476 , n25477 , n25478 , n25479 , n25480 ,
n25481 , n25482 , n25483 , n25484 , n25485 , n25486 , n25487 , n25488 , n25489 , n25490 ,
n25491 , n25492 , n25493 , n25494 , n25495 , n25496 , n25497 , n25498 , n25499 , n25500 ,
n25501 , n25502 , n25503 , n25504 , n25505 , n25506 , n25507 , n25508 , n25509 , n25510 ,
n25511 , n25512 , n25513 , n25514 , n25515 , n25516 , n25517 , n25518 , n25519 , n25520 ,
n25521 , n25522 , n25523 , n25524 , n25525 , n25526 , n25527 , n25528 , n25529 , n25530 ,
n25531 , n25532 , n25533 , n25534 , n25535 , n25536 , n25537 , n25538 , n25539 , n25540 ,
n25541 , n25542 , n25543 , n25544 , n25545 , n25546 , n25547 , n25548 , n25549 , n25550 ,
n25551 , n25552 , n25553 , n25554 , n25555 , n25556 , n25557 , n25558 , n25559 , n25560 ,
n25561 , n25562 , n25563 , n25564 , n25565 , n25566 , n25567 , n25568 , n25569 , n25570 ,
n25571 , n25572 , n25573 , n25574 , n25575 , n25576 , n25577 , n25578 , n25579 , n25580 ,
n25581 , n25582 , n25583 , n25584 , n25585 , n25586 , n25587 , n25588 , n25589 , n25590 ,
n25591 , n25592 , n25593 , n25594 , n25595 , n25596 , n25597 , n25598 , n25599 , n25600 ,
n25601 , n25602 , n25603 , n25604 , n25605 , n25606 , n25607 , n25608 , n25609 , n25610 ,
n25611 , n25612 , n25613 , n25614 , n25615 , n25616 , n25617 , n25618 , n25619 , n25620 ,
n25621 , n25622 , n25623 , n25624 , n25625 , n25626 , n25627 , n25628 , n25629 , n25630 ,
n25631 , n25632 , n25633 , n25634 , n25635 , n25636 , n25637 , n25638 , n25639 , n25640 ,
n25641 , n25642 , n25643 , n25644 , n25645 , n25646 , n25647 , n25648 , n25649 , n25650 ,
n25651 , n25652 , n25653 , n25654 , n25655 , n25656 , n25657 , n25658 , n25659 , n25660 ,
n25661 , n25662 , n25663 , n25664 , n25665 , n25666 , n25667 , n25668 , n25669 , n25670 ,
n25671 , n25672 , n25673 , n25674 , n25675 , n25676 , n25677 , n25678 , n25679 , n25680 ,
n25681 , n25682 , n25683 , n25684 , n25685 , n25686 , n25687 , n25688 , n25689 , n25690 ,
n25691 , n25692 , n25693 , n25694 , n25695 , n25696 , n25697 , n25698 , n25699 , n25700 ,
n25701 , n25702 , n25703 , n25704 , n25705 , n25706 , n25707 , n25708 , n25709 , n25710 ,
n25711 , n25712 , n25713 , n25714 , n25715 , n25716 , n25717 , n25718 , n25719 , n25720 ,
n25721 , n25722 , n25723 , n25724 , n25725 , n25726 , n25727 , n25728 , n25729 , n25730 ,
n25731 , n25732 , n25733 , n25734 , n25735 , n25736 , n25737 , n25738 , n25739 , n25740 ,
n25741 , n25742 , n25743 , n25744 , n25745 , n25746 , n25747 , n25748 , n25749 , n25750 ,
n25751 , n25752 , n25753 , n25754 , n25755 , n25756 , n25757 , n25758 , n25759 , n25760 ,
n25761 , n25762 , n25763 , n25764 , n25765 , n25766 , n25767 , n25768 , n25769 , n25770 ,
n25771 , n25772 , n25773 , n25774 , n25775 , n25776 , n25777 , n25778 , n25779 , n25780 ,
n25781 , n25782 , n25783 , n25784 , n25785 , n25786 , n25787 , n25788 , n25789 , n25790 ,
n25791 , n25792 , n25793 , n25794 , n25795 , n25796 , n25797 , n25798 , n25799 , n25800 ,
n25801 , n25802 , n25803 , n25804 , n25805 , n25806 , n25807 , n25808 , n25809 , n25810 ,
n25811 , n25812 , n25813 , n25814 , n25815 , n25816 , n25817 , n25818 , n25819 , n25820 ,
n25821 , n25822 , n25823 , n25824 , n25825 , n25826 , n25827 , n25828 , n25829 , n25830 ,
n25831 , n25832 , n25833 , n25834 , n25835 , n25836 , n25837 , n25838 , n25839 , n25840 ,
n25841 , n25842 , n25843 , n25844 , n25845 , n25846 , n25847 , n25848 , n25849 , n25850 ,
n25851 , n25852 , n25853 , n25854 , n25855 , n25856 , n25857 , n25858 , n25859 , n25860 ,
n25861 , n25862 , n25863 , n25864 , n25865 , n25866 , n25867 , n25868 , n25869 , n25870 ,
n25871 , n25872 , n25873 , n25874 , n25875 , n25876 , n25877 , n25878 , n25879 , n25880 ,
n25881 , n25882 , n25883 , n25884 , n25885 , n25886 , n25887 , n25888 , n25889 , n25890 ,
n25891 , n25892 , n25893 , n25894 , n25895 , n25896 , n25897 , n25898 , n25899 , n25900 ,
n25901 , n25902 , n25903 , n25904 , n25905 , n25906 , n25907 , n25908 , n25909 , n25910 ,
n25911 , n25912 , n25913 , n25914 , n25915 , n25916 , n25917 , n25918 , n25919 , n25920 ,
n25921 , n25922 , n25923 , n25924 , n25925 , n25926 , n25927 , n25928 , n25929 , n25930 ,
n25931 , n25932 , n25933 , n25934 , n25935 , n25936 , n25937 , n25938 , n25939 , n25940 ,
n25941 , n25942 , n25943 , n25944 , n25945 , n25946 , n25947 , n25948 , n25949 , n25950 ,
n25951 , n25952 , n25953 , n25954 , n25955 , n25956 , n25957 , n25958 , n25959 , n25960 ,
n25961 , n25962 , n25963 , n25964 , n25965 , n25966 , n25967 , n25968 , n25969 , n25970 ,
n25971 , n25972 , n25973 , n25974 , n25975 , n25976 , n25977 , n25978 , n25979 , n25980 ,
n25981 , n25982 , n25983 , n25984 , n25985 , n25986 , n25987 , n25988 , n25989 , n25990 ,
n25991 , n25992 , n25993 , n25994 , n25995 , n25996 , n25997 , n25998 , n25999 , n26000 ,
n26001 , n26002 , n26003 , n26004 , n26005 , n26006 , n26007 , n26008 , n26009 , n26010 ,
n26011 , n26012 , n26013 , n26014 , n26015 , n26016 , n26017 , n26018 , n26019 , n26020 ,
n26021 , n26022 , n26023 , n26024 , n26025 , n26026 , n26027 , n26028 , n26029 , n26030 ,
n26031 , n26032 , n26033 , n26034 , n26035 , n26036 , n26037 , n26038 , n26039 , n26040 ,
n26041 , n26042 , n26043 , n26044 , n26045 , n26046 , n26047 , n26048 , n26049 , n26050 ,
n26051 , n26052 , n26053 , n26054 , n26055 , n26056 , n26057 , n26058 , n26059 , n26060 ,
n26061 , n26062 , n26063 , n26064 , n26065 , n26066 , n26067 , n26068 , n26069 , n26070 ,
n26071 , n26072 , n26073 , n26074 , n26075 , n26076 , n26077 , n26078 , n26079 , n26080 ,
n26081 , n26082 , n26083 , n26084 , n26085 , n26086 , n26087 , n26088 , n26089 , n26090 ,
n26091 , n26092 , n26093 , n26094 , n26095 , n26096 , n26097 , n26098 , n26099 , n26100 ,
n26101 , n26102 , n26103 , n26104 , n26105 , n26106 , n26107 , n26108 , n26109 , n26110 ,
n26111 , n26112 , n26113 , n26114 , n26115 , n26116 , n26117 , n26118 , n26119 , n26120 ,
n26121 , n26122 , n26123 , n26124 , n26125 , n26126 , n26127 , n26128 , n26129 , n26130 ,
n26131 , n26132 , n26133 , n26134 , n26135 , n26136 , n26137 , n26138 , n26139 , n26140 ,
n26141 , n26142 , n26143 , n26144 , n26145 , n26146 , n26147 , n26148 , n26149 , n26150 ,
n26151 , n26152 , n26153 , n26154 , n26155 , n26156 , n26157 , n26158 , n26159 , n26160 ,
n26161 , n26162 , n26163 , n26164 , n26165 , n26166 , n26167 , n26168 , n26169 , n26170 ,
n26171 , n26172 , n26173 , n26174 , n26175 , n26176 , n26177 , n26178 , n26179 , n26180 ,
n26181 , n26182 , n26183 , n26184 , n26185 , n26186 , n26187 , n26188 , n26189 , n26190 ,
n26191 , n26192 , n26193 , n26194 , n26195 , n26196 , n26197 , n26198 , n26199 , n26200 ,
n26201 , n26202 , n26203 , n26204 , n26205 , n26206 , n26207 , n26208 , n26209 , n26210 ,
n26211 , n26212 , n26213 , n26214 , n26215 , n26216 , n26217 , n26218 , n26219 , n26220 ,
n26221 , n26222 , n26223 , n26224 , n26225 , n26226 , n26227 , n26228 , n26229 , n26230 ,
n26231 , n26232 , n26233 , n26234 , n26235 , n26236 , n26237 , n26238 , n26239 , n26240 ,
n26241 , n26242 , n26243 , n26244 , n26245 , n26246 , n26247 , n26248 , n26249 , n26250 ,
n26251 , n26252 , n26253 , n26254 , n26255 , n26256 , n26257 , n26258 , n26259 , n26260 ,
n26261 , n26262 , n26263 , n26264 , n26265 , n26266 , n26267 , n26268 , n26269 , n26270 ,
n26271 , n26272 , n26273 , n26274 , n26275 , n26276 , n26277 , n26278 , n26279 , n26280 ,
n26281 , n26282 , n26283 , n26284 , n26285 , n26286 , n26287 , n26288 , n26289 , n26290 ,
n26291 , n26292 , n26293 , n26294 , n26295 , n26296 , n26297 , n26298 , n26299 , n26300 ,
n26301 , n26302 , n26303 , n26304 , n26305 , n26306 , n26307 , n26308 , n26309 , n26310 ,
n26311 , n26312 , n26313 , n26314 , n26315 , n26316 , n26317 , n26318 , n26319 , n26320 ,
n26321 , n26322 , n26323 , n26324 , n26325 , n26326 , n26327 , n26328 , n26329 , n26330 ,
n26331 , n26332 , n26333 , n26334 , n26335 , n26336 , n26337 , n26338 , n26339 , n26340 ,
n26341 , n26342 , n26343 , n26344 , n26345 , n26346 , n26347 , n26348 , n26349 , n26350 ,
n26351 , n26352 , n26353 , n26354 , n26355 , n26356 , n26357 , n26358 , n26359 , n26360 ,
n26361 , n26362 , n26363 , n26364 , n26365 , n26366 , n26367 , n26368 , n26369 , n26370 ,
n26371 , n26372 , n26373 , n26374 , n26375 , n26376 , n26377 , n26378 , n26379 , n26380 ,
n26381 , n26382 , n26383 , n26384 , n26385 , n26386 , n26387 , n26388 , n26389 , n26390 ,
n26391 , n26392 , n26393 , n26394 , n26395 , n26396 , n26397 , n26398 , n26399 , n26400 ,
n26401 , n26402 , n26403 , n26404 , n26405 , n26406 , n26407 , n26408 , n26409 , n26410 ,
n26411 , n26412 , n26413 , n26414 , n26415 , n26416 , n26417 , n26418 , n26419 , n26420 ,
n26421 , n26422 , n26423 , n26424 , n26425 , n26426 , n26427 , n26428 , n26429 , n26430 ,
n26431 , n26432 , n26433 , n26434 , n26435 , n26436 , n26437 , n26438 , n26439 , n26440 ,
n26441 , n26442 , n26443 , n26444 , n26445 , n26446 , n26447 , n26448 , n26449 , n26450 ,
n26451 , n26452 , n26453 , n26454 , n26455 , n26456 , n26457 , n26458 , n26459 , n26460 ,
n26461 , n26462 , n26463 , n26464 , n26465 , n26466 , n26467 , n26468 , n26469 , n26470 ,
n26471 , n26472 , n26473 , n26474 , n26475 , n26476 , n26477 , n26478 , n26479 , n26480 ,
n26481 , n26482 , n26483 , n26484 , n26485 , n26486 , n26487 , n26488 , n26489 , n26490 ,
n26491 , n26492 , n26493 , n26494 , n26495 , n26496 , n26497 , n26498 , n26499 , n26500 ,
n26501 , n26502 , n26503 , n26504 , n26505 , n26506 , n26507 , n26508 , n26509 , n26510 ,
n26511 , n26512 , n26513 , n26514 , n26515 , n26516 , n26517 , n26518 , n26519 , n26520 ,
n26521 , n26522 , n26523 , n26524 , n26525 , n26526 , n26527 , n26528 , n26529 , n26530 ,
n26531 , n26532 , n26533 , n26534 , n26535 , n26536 , n26537 , n26538 , n26539 , n26540 ,
n26541 , n26542 , n26543 , n26544 , n26545 , n26546 , n26547 , n26548 , n26549 , n26550 ,
n26551 , n26552 , n26553 , n26554 , n26555 , n26556 , n26557 , n26558 , n26559 , n26560 ,
n26561 , n26562 , n26563 , n26564 , n26565 , n26566 , n26567 , n26568 , n26569 , n26570 ,
n26571 , n26572 , n26573 , n26574 , n26575 , n26576 , n26577 , n26578 , n26579 , n26580 ,
n26581 , n26582 , n26583 , n26584 , n26585 , n26586 , n26587 , n26588 , n26589 , n26590 ,
n26591 , n26592 , n26593 , n26594 , n26595 , n26596 , n26597 , n26598 , n26599 , n26600 ,
n26601 , n26602 , n26603 , n26604 , n26605 , n26606 , n26607 , n26608 , n26609 , n26610 ,
n26611 , n26612 , n26613 , n26614 , n26615 , n26616 , n26617 , n26618 , n26619 , n26620 ,
n26621 , n26622 , n26623 , n26624 , n26625 , n26626 , n26627 , n26628 , n26629 , n26630 ,
n26631 , n26632 , n26633 , n26634 , n26635 , n26636 , n26637 , n26638 , n26639 , n26640 ,
n26641 , n26642 , n26643 , n26644 , n26645 , n26646 , n26647 , n26648 , n26649 , n26650 ,
n26651 , n26652 , n26653 , n26654 , n26655 , n26656 , n26657 , n26658 , n26659 , n26660 ,
n26661 , n26662 , n26663 , n26664 , n26665 , n26666 , n26667 , n26668 , n26669 , n26670 ,
n26671 , n26672 , n26673 , n26674 , n26675 , n26676 , n26677 , n26678 , n26679 , n26680 ,
n26681 , n26682 , n26683 , n26684 , n26685 , n26686 , n26687 , n26688 , n26689 , n26690 ,
n26691 , n26692 , n26693 , n26694 , n26695 , n26696 , n26697 , n26698 , n26699 , n26700 ,
n26701 , n26702 , n26703 , n26704 , n26705 , n26706 , n26707 , n26708 , n26709 , n26710 ,
n26711 , n26712 , n26713 , n26714 , n26715 , n26716 , n26717 , n26718 , n26719 , n26720 ,
n26721 , n26722 , n26723 , n26724 , n26725 , n26726 , n26727 , n26728 , n26729 , n26730 ,
n26731 , n26732 , n26733 , n26734 , n26735 , n26736 , n26737 , n26738 , n26739 , n26740 ,
n26741 , n26742 , n26743 , n26744 , n26745 , n26746 , n26747 , n26748 , n26749 , n26750 ,
n26751 , n26752 , n26753 , n26754 , n26755 , n26756 , n26757 , n26758 , n26759 , n26760 ,
n26761 , n26762 , n26763 , n26764 , n26765 , n26766 , n26767 , n26768 , n26769 , n26770 ,
n26771 , n26772 , n26773 , n26774 , n26775 , n26776 , n26777 , n26778 , n26779 , n26780 ,
n26781 , n26782 , n26783 , n26784 , n26785 , n26786 , n26787 , n26788 , n26789 , n26790 ,
n26791 , n26792 , n26793 , n26794 , n26795 , n26796 , n26797 , n26798 , n26799 , n26800 ,
n26801 , n26802 , n26803 , n26804 , n26805 , n26806 , n26807 , n26808 , n26809 , n26810 ,
n26811 , n26812 , n26813 , n26814 , n26815 , n26816 , n26817 , n26818 , n26819 , n26820 ,
n26821 , n26822 , n26823 , n26824 , n26825 , n26826 , n26827 , n26828 , n26829 , n26830 ,
n26831 , n26832 , n26833 , n26834 , n26835 , n26836 , n26837 , n26838 , n26839 , n26840 ,
n26841 , n26842 , n26843 , n26844 , n26845 , n26846 , n26847 , n26848 , n26849 , n26850 ,
n26851 , n26852 , n26853 , n26854 , n26855 , n26856 , n26857 , n26858 , n26859 , n26860 ,
n26861 , n26862 , n26863 , n26864 , n26865 , n26866 , n26867 , n26868 , n26869 , n26870 ,
n26871 , n26872 , n26873 , n26874 , n26875 , n26876 , n26877 , n26878 , n26879 , n26880 ,
n26881 , n26882 , n26883 , n26884 , n26885 , n26886 , n26887 , n26888 , n26889 , n26890 ,
n26891 , n26892 , n26893 , n26894 , n26895 , n26896 , n26897 , n26898 , n26899 , n26900 ,
n26901 , n26902 , n26903 , n26904 , n26905 , n26906 , n26907 , n26908 , n26909 , n26910 ,
n26911 , n26912 , n26913 , n26914 , n26915 , n26916 , n26917 , n26918 , n26919 , n26920 ,
n26921 , n26922 , n26923 , n26924 , n26925 , n26926 , n26927 , n26928 , n26929 , n26930 ,
n26931 , n26932 , n26933 , n26934 , n26935 , n26936 , n26937 , n26938 , n26939 , n26940 ,
n26941 , n26942 , n26943 , n26944 , n26945 , n26946 , n26947 , n26948 , n26949 , n26950 ,
n26951 , n26952 , n26953 , n26954 , n26955 , n26956 , n26957 , n26958 , n26959 , n26960 ,
n26961 , n26962 , n26963 , n26964 , n26965 , n26966 , n26967 , n26968 , n26969 , n26970 ,
n26971 , n26972 , n26973 , n26974 , n26975 , n26976 , n26977 , n26978 , n26979 , n26980 ,
n26981 , n26982 , n26983 , n26984 , n26985 , n26986 , n26987 , n26988 , n26989 , n26990 ,
n26991 , n26992 , n26993 , n26994 , n26995 , n26996 , n26997 , n26998 , n26999 , n27000 ,
n27001 , n27002 , n27003 , n27004 , n27005 , n27006 , n27007 , n27008 , n27009 , n27010 ,
n27011 , n27012 , n27013 , n27014 , n27015 , n27016 , n27017 , n27018 , n27019 , n27020 ,
n27021 , n27022 , n27023 , n27024 , n27025 , n27026 , n27027 , n27028 , n27029 , n27030 ,
n27031 , n27032 , n27033 , n27034 , n27035 , n27036 , n27037 , n27038 , n27039 , n27040 ,
n27041 , n27042 , n27043 , n27044 , n27045 , n27046 , n27047 , n27048 , n27049 , n27050 ,
n27051 , n27052 , n27053 , n27054 , n27055 , n27056 , n27057 , n27058 , n27059 , n27060 ,
n27061 , n27062 , n27063 , n27064 , n27065 , n27066 , n27067 , n27068 , n27069 , n27070 ,
n27071 , n27072 , n27073 , n27074 , n27075 , n27076 , n27077 , n27078 , n27079 , n27080 ,
n27081 , n27082 , n27083 , n27084 , n27085 , n27086 , n27087 , n27088 , n27089 , n27090 ,
n27091 , n27092 , n27093 , n27094 , n27095 , n27096 , n27097 , n27098 , n27099 , n27100 ,
n27101 , n27102 , n27103 , n27104 , n27105 , n27106 , n27107 , n27108 , n27109 , n27110 ,
n27111 , n27112 , n27113 , n27114 , n27115 , n27116 , n27117 , n27118 , n27119 , n27120 ,
n27121 , n27122 , n27123 , n27124 , n27125 , n27126 , n27127 , n27128 , n27129 , n27130 ,
n27131 , n27132 , n27133 , n27134 , n27135 , n27136 , n27137 , n27138 , n27139 , n27140 ,
n27141 , n27142 , n27143 , n27144 , n27145 , n27146 , n27147 , n27148 , n27149 , n27150 ,
n27151 , n27152 , n27153 , n27154 , n27155 , n27156 , n27157 , n27158 , n27159 , n27160 ,
n27161 , n27162 , n27163 , n27164 , n27165 , n27166 , n27167 , n27168 , n27169 , n27170 ,
n27171 , n27172 , n27173 , n27174 , n27175 , n27176 , n27177 , n27178 , n27179 , n27180 ,
n27181 , n27182 , n27183 , n27184 , n27185 , n27186 , n27187 , n27188 , n27189 , n27190 ,
n27191 , n27192 , n27193 , n27194 , n27195 , n27196 , n27197 , n27198 , n27199 , n27200 ,
n27201 , n27202 , n27203 , n27204 , n27205 , n27206 , n27207 , n27208 , n27209 , n27210 ,
n27211 , n27212 , n27213 , n27214 , n27215 , n27216 , n27217 , n27218 , n27219 , n27220 ,
n27221 , n27222 , n27223 , n27224 , n27225 , n27226 , n27227 , n27228 , n27229 , n27230 ,
n27231 , n27232 , n27233 , n27234 , n27235 , n27236 , n27237 , n27238 , n27239 , n27240 ,
n27241 , n27242 , n27243 , n27244 , n27245 , n27246 , n27247 , n27248 , n27249 , n27250 ,
n27251 , n27252 , n27253 , n27254 , n27255 , n27256 , n27257 , n27258 , n27259 , n27260 ,
n27261 , n27262 , n27263 , n27264 , n27265 , n27266 , n27267 , n27268 , n27269 , n27270 ,
n27271 , n27272 , n27273 , n27274 , n27275 , n27276 , n27277 , n27278 , n27279 , n27280 ,
n27281 , n27282 , n27283 , n27284 , n27285 , n27286 , n27287 , n27288 , n27289 , n27290 ,
n27291 , n27292 , n27293 , n27294 , n27295 , n27296 , n27297 , n27298 , n27299 , n27300 ,
n27301 , n27302 , n27303 , n27304 , n27305 , n27306 , n27307 , n27308 , n27309 , n27310 ,
n27311 , n27312 , n27313 , n27314 , n27315 , n27316 , n27317 , n27318 , n27319 , n27320 ,
n27321 , n27322 , n27323 , n27324 , n27325 , n27326 , n27327 , n27328 , n27329 , n27330 ,
n27331 , n27332 , n27333 , n27334 , n27335 , n27336 , n27337 , n27338 , n27339 , n27340 ,
n27341 , n27342 , n27343 , n27344 , n27345 , n27346 , n27347 , n27348 , n27349 , n27350 ,
n27351 , n27352 , n27353 , n27354 , n27355 , n27356 , n27357 , n27358 , n27359 , n27360 ,
n27361 , n27362 , n27363 , n27364 , n27365 , n27366 , n27367 , n27368 , n27369 , n27370 ,
n27371 , n27372 , n27373 , n27374 , n27375 , n27376 , n27377 , n27378 , n27379 , n27380 ,
n27381 , n27382 , n27383 , n27384 , n27385 , n27386 , n27387 , n27388 , n27389 , n27390 ,
n27391 , n27392 , n27393 , n27394 , n27395 , n27396 , n27397 , n27398 , n27399 , n27400 ,
n27401 , n27402 , n27403 , n27404 , n27405 , n27406 , n27407 , n27408 , n27409 , n27410 ,
n27411 , n27412 , n27413 , n27414 , n27415 , n27416 , n27417 , n27418 , n27419 , n27420 ,
n27421 , n27422 , n27423 , n27424 , n27425 , n27426 , n27427 , n27428 , n27429 , n27430 ,
n27431 , n27432 , n27433 , n27434 , n27435 , n27436 , n27437 , n27438 , n27439 , n27440 ,
n27441 , n27442 , n27443 , n27444 , n27445 , n27446 , n27447 , n27448 , n27449 , n27450 ,
n27451 , n27452 , n27453 , n27454 , n27455 , n27456 , n27457 , n27458 , n27459 , n27460 ,
n27461 , n27462 , n27463 , n27464 , n27465 , n27466 , n27467 , n27468 , n27469 , n27470 ,
n27471 , n27472 , n27473 , n27474 , n27475 , n27476 , n27477 , n27478 , n27479 , n27480 ,
n27481 , n27482 , n27483 , n27484 , n27485 , n27486 , n27487 , n27488 , n27489 , n27490 ,
n27491 , n27492 , n27493 , n27494 , n27495 , n27496 , n27497 , n27498 , n27499 , n27500 ,
n27501 , n27502 , n27503 , n27504 , n27505 , n27506 , n27507 , n27508 , n27509 , n27510 ,
n27511 , n27512 , n27513 , n27514 , n27515 , n27516 , n27517 , n27518 , n27519 , n27520 ,
n27521 , n27522 , n27523 , n27524 , n27525 , n27526 , n27527 , n27528 , n27529 , n27530 ,
n27531 , n27532 , n27533 , n27534 , n27535 , n27536 , n27537 , n27538 , n27539 , n27540 ,
n27541 , n27542 , n27543 , n27544 , n27545 , n27546 , n27547 , n27548 , n27549 , n27550 ,
n27551 , n27552 , n27553 , n27554 , n27555 , n27556 , n27557 , n27558 , n27559 , n27560 ,
n27561 , n27562 , n27563 , n27564 , n27565 , n27566 , n27567 , n27568 , n27569 , n27570 ,
n27571 , n27572 , n27573 , n27574 , n27575 , n27576 , n27577 , n27578 , n27579 , n27580 ,
n27581 , n27582 , n27583 , n27584 , n27585 , n27586 , n27587 , n27588 , n27589 , n27590 ,
n27591 , n27592 , n27593 , n27594 , n27595 , n27596 , n27597 , n27598 , n27599 , n27600 ,
n27601 , n27602 , n27603 , n27604 , n27605 , n27606 , n27607 , n27608 , n27609 , n27610 ,
n27611 , n27612 , n27613 , n27614 , n27615 , n27616 , n27617 , n27618 , n27619 , n27620 ,
n27621 , n27622 , n27623 , n27624 , n27625 , n27626 , n27627 , n27628 , n27629 , n27630 ,
n27631 , n27632 , n27633 , n27634 , n27635 , n27636 , n27637 , n27638 , n27639 , n27640 ,
n27641 , n27642 , n27643 , n27644 , n27645 , n27646 , n27647 , n27648 , n27649 , n27650 ,
n27651 , n27652 , n27653 , n27654 , n27655 , n27656 , n27657 , n27658 , n27659 , n27660 ,
n27661 , n27662 , n27663 , n27664 , n27665 , n27666 , n27667 , n27668 , n27669 , n27670 ,
n27671 , n27672 , n27673 , n27674 , n27675 , n27676 , n27677 , n27678 , n27679 , n27680 ,
n27681 , n27682 , n27683 , n27684 , n27685 , n27686 , n27687 , n27688 , n27689 , n27690 ,
n27691 , n27692 , n27693 , n27694 , n27695 , n27696 , n27697 , n27698 , n27699 , n27700 ,
n27701 , n27702 , n27703 , n27704 , n27705 , n27706 , n27707 , n27708 , n27709 , n27710 ,
n27711 , n27712 , n27713 , n27714 , n27715 , n27716 , n27717 , n27718 , n27719 , n27720 ,
n27721 , n27722 , n27723 , n27724 , n27725 , n27726 , n27727 , n27728 , n27729 , n27730 ,
n27731 , n27732 , n27733 , n27734 , n27735 , n27736 , n27737 , n27738 , n27739 , n27740 ,
n27741 , n27742 , n27743 , n27744 , n27745 , n27746 , n27747 , n27748 , n27749 , n27750 ,
n27751 , n27752 , n27753 , n27754 , n27755 , n27756 , n27757 , n27758 , n27759 , n27760 ,
n27761 , n27762 , n27763 , n27764 , n27765 , n27766 , n27767 , n27768 , n27769 , n27770 ,
n27771 , n27772 , n27773 , n27774 , n27775 , n27776 , n27777 , n27778 , n27779 , n27780 ,
n27781 , n27782 , n27783 , n27784 , n27785 , n27786 , n27787 , n27788 , n27789 , n27790 ,
n27791 , n27792 , n27793 , n27794 , n27795 , n27796 , n27797 , n27798 , n27799 , n27800 ,
n27801 , n27802 , n27803 , n27804 , n27805 , n27806 , n27807 , n27808 , n27809 , n27810 ,
n27811 , n27812 , n27813 , n27814 , n27815 , n27816 , n27817 , n27818 , n27819 , n27820 ,
n27821 , n27822 , n27823 , n27824 , n27825 , n27826 , n27827 , n27828 , n27829 , n27830 ,
n27831 , n27832 , n27833 , n27834 , n27835 , n27836 , n27837 , n27838 , n27839 , n27840 ,
n27841 , n27842 , n27843 , n27844 , n27845 , n27846 , n27847 , n27848 , n27849 , n27850 ,
n27851 , n27852 , n27853 , n27854 , n27855 , n27856 , n27857 , n27858 , n27859 , n27860 ,
n27861 , n27862 , n27863 , n27864 , n27865 , n27866 , n27867 , n27868 , n27869 , n27870 ,
n27871 , n27872 , n27873 , n27874 , n27875 , n27876 , n27877 , n27878 , n27879 , n27880 ,
n27881 , n27882 , n27883 , n27884 , n27885 , n27886 , n27887 , n27888 , n27889 , n27890 ,
n27891 , n27892 , n27893 , n27894 , n27895 , n27896 , n27897 , n27898 , n27899 , n27900 ,
n27901 , n27902 , n27903 , n27904 , n27905 , n27906 , n27907 , n27908 , n27909 , n27910 ,
n27911 , n27912 , n27913 , n27914 , n27915 , n27916 , n27917 , n27918 , n27919 , n27920 ,
n27921 , n27922 , n27923 , n27924 , n27925 , n27926 , n27927 , n27928 , n27929 , n27930 ,
n27931 , n27932 , n27933 , n27934 , n27935 , n27936 , n27937 , n27938 , n27939 , n27940 ,
n27941 , n27942 , n27943 , n27944 , n27945 , n27946 , n27947 , n27948 , n27949 , n27950 ,
n27951 , n27952 , n27953 , n27954 , n27955 , n27956 , n27957 , n27958 , n27959 , n27960 ,
n27961 , n27962 , n27963 , n27964 , n27965 , n27966 , n27967 , n27968 , n27969 , n27970 ,
n27971 , n27972 , n27973 , n27974 , n27975 , n27976 , n27977 , n27978 , n27979 , n27980 ,
n27981 , n27982 , n27983 , n27984 , n27985 , n27986 , n27987 , n27988 , n27989 , n27990 ,
n27991 , n27992 , n27993 , n27994 , n27995 , n27996 , n27997 , n27998 , n27999 , n28000 ,
n28001 , n28002 , n28003 , n28004 , n28005 , n28006 , n28007 , n28008 , n28009 , n28010 ,
n28011 , n28012 , n28013 , n28014 , n28015 , n28016 , n28017 , n28018 , n28019 , n28020 ,
n28021 , n28022 , n28023 , n28024 , n28025 , n28026 , n28027 , n28028 , n28029 , n28030 ,
n28031 , n28032 , n28033 , n28034 , n28035 , n28036 , n28037 , n28038 , n28039 , n28040 ,
n28041 , n28042 , n28043 , n28044 , n28045 , n28046 , n28047 , n28048 , n28049 , n28050 ,
n28051 , n28052 , n28053 , n28054 , n28055 , n28056 , n28057 , n28058 , n28059 , n28060 ,
n28061 , n28062 , n28063 , n28064 , n28065 , n28066 , n28067 , n28068 , n28069 , n28070 ,
n28071 , n28072 , n28073 , n28074 , n28075 , n28076 , n28077 , n28078 , n28079 , n28080 ,
n28081 , n28082 , n28083 , n28084 , n28085 , n28086 , n28087 , n28088 , n28089 , n28090 ,
n28091 , n28092 , n28093 , n28094 , n28095 , n28096 , n28097 , n28098 , n28099 , n28100 ,
n28101 , n28102 , n28103 , n28104 , n28105 , n28106 , n28107 , n28108 , n28109 , n28110 ,
n28111 , n28112 , n28113 , n28114 , n28115 , n28116 , n28117 , n28118 , n28119 , n28120 ,
n28121 , n28122 , n28123 , n28124 , n28125 , n28126 , n28127 , n28128 , n28129 , n28130 ,
n28131 , n28132 , n28133 , n28134 , n28135 , n28136 , n28137 , n28138 , n28139 , n28140 ,
n28141 , n28142 , n28143 , n28144 , n28145 , n28146 , n28147 , n28148 , n28149 , n28150 ,
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buf ( n6105 , n654 );
buf ( n6106 , n692 );
buf ( n6107 , n1110 );
buf ( n6108 , n334 );
buf ( n6109 , n1223 );
buf ( n6110 , n463 );
buf ( n6111 , n1084 );
buf ( n6112 , n512 );
buf ( n6113 , n1833 );
buf ( n6114 , n1814 );
buf ( n6115 , n842 );
buf ( n6116 , n789 );
buf ( n6117 , n1867 );
buf ( n6118 , n1680 );
buf ( n6119 , n1835 );
buf ( n6120 , n106 );
buf ( n6121 , n1797 );
buf ( n6122 , n1058 );
buf ( n6123 , n163 );
buf ( n6124 , n128 );
buf ( n6125 , n2122 );
buf ( n6126 , n480 );
buf ( n6127 , n430 );
buf ( n6128 , n902 );
buf ( n6129 , n258 );
buf ( n6130 , n349 );
buf ( n6131 , n178 );
buf ( n6132 , n544 );
buf ( n6133 , n1388 );
buf ( n6134 , n1292 );
buf ( n6135 , n241 );
buf ( n6136 , n1813 );
buf ( n6137 , n275 );
buf ( n6138 , n263 );
buf ( n6139 , n451 );
buf ( n6140 , n910 );
buf ( n6141 , n697 );
buf ( n6142 , n374 );
buf ( n6143 , n1681 );
buf ( n6144 , n424 );
buf ( n6145 , n657 );
buf ( n6146 , n276 );
buf ( n6147 , n811 );
buf ( n6148 , n1819 );
buf ( n6149 , n89 );
buf ( n6150 , n1397 );
buf ( n6151 , n1995 );
buf ( n6152 , n329 );
buf ( n6153 , n1826 );
buf ( n6154 , n1274 );
buf ( n6155 , n802 );
buf ( n6156 , n1245 );
buf ( n6157 , n647 );
buf ( n6158 , n1999 );
buf ( n6159 , n1152 );
buf ( n6160 , n949 );
buf ( n6161 , n2014 );
buf ( n6162 , n208 );
buf ( n6163 , n2088 );
buf ( n6164 , n1061 );
buf ( n6165 , n1180 );
buf ( n6166 , n521 );
buf ( n6167 , n1601 );
buf ( n6168 , n630 );
buf ( n6169 , n1869 );
buf ( n6170 , n639 );
buf ( n6171 , n914 );
buf ( n6172 , n251 );
buf ( n6173 , n751 );
buf ( n6174 , n95 );
buf ( n6175 , n747 );
buf ( n6176 , n179 );
buf ( n6177 , n1580 );
buf ( n6178 , n1467 );
buf ( n6179 , n1768 );
buf ( n6180 , n82 );
buf ( n6181 , n1555 );
buf ( n6182 , n1723 );
buf ( n6183 , n141 );
buf ( n6184 , n953 );
buf ( n6185 , n38 );
buf ( n6186 , n1682 );
buf ( n6187 , n2098 );
buf ( n6188 , n938 );
buf ( n6189 , n239 );
buf ( n6190 , n583 );
buf ( n6191 , n1757 );
buf ( n6192 , n55 );
buf ( n6193 , n1634 );
buf ( n6194 , n66 );
buf ( n6195 , n467 );
buf ( n6196 , n1534 );
buf ( n6197 , n60 );
buf ( n6198 , n1328 );
buf ( n6199 , n1403 );
buf ( n6200 , n2035 );
buf ( n6201 , n884 );
buf ( n6202 , n918 );
buf ( n6203 , n51 );
buf ( n6204 , n928 );
buf ( n6205 , n1763 );
buf ( n6206 , n1427 );
buf ( n6207 , n1241 );
buf ( n6208 , n345 );
buf ( n6209 , n1408 );
buf ( n6210 , n315 );
buf ( n6211 , n1172 );
buf ( n6212 , n1071 );
buf ( n6213 , n1829 );
buf ( n6214 , n1783 );
buf ( n6215 , n1923 );
buf ( n6216 , n535 );
buf ( n6217 , n183 );
buf ( n6218 , n965 );
buf ( n6219 , n1213 );
buf ( n6220 , n20 );
buf ( n6221 , n1782 );
buf ( n6222 , n1646 );
buf ( n6223 , n609 );
buf ( n6224 , n975 );
buf ( n6225 , n1798 );
buf ( n6226 , n174 );
buf ( n6227 , n1038 );
buf ( n6228 , n1416 );
buf ( n6229 , n1423 );
buf ( n6230 , n204 );
buf ( n6231 , n1918 );
buf ( n6232 , n1748 );
buf ( n6233 , n596 );
buf ( n6234 , n1949 );
buf ( n6235 , n400 );
buf ( n6236 , n768 );
buf ( n6237 , n1128 );
buf ( n6238 , n310 );
buf ( n6239 , n386 );
buf ( n6240 , n1771 );
buf ( n6241 , n1522 );
buf ( n6242 , n1770 );
buf ( n6243 , n703 );
buf ( n6244 , n1320 );
buf ( n6245 , n533 );
buf ( n6246 , n2069 );
buf ( n6247 , n2081 );
buf ( n6248 , n1785 );
buf ( n6249 , n2044 );
buf ( n6250 , n1399 );
buf ( n6251 , n955 );
buf ( n6252 , n773 );
buf ( n6253 , n1446 );
buf ( n6254 , n1480 );
buf ( n6255 , n1605 );
buf ( n6256 , n434 );
buf ( n6257 , n1362 );
buf ( n6258 , n1381 );
buf ( n6259 , n1910 );
buf ( n6260 , n1769 );
buf ( n6261 , n1853 );
buf ( n6262 , n1710 );
buf ( n6263 , n947 );
buf ( n6264 , n672 );
buf ( n6265 , n1437 );
buf ( n6266 , n112 );
buf ( n6267 , n380 );
buf ( n6268 , n1451 );
buf ( n6269 , n321 );
buf ( n6270 , n1494 );
buf ( n6271 , n1996 );
buf ( n6272 , n1258 );
buf ( n6273 , n2060 );
buf ( n6274 , n1802 );
buf ( n6275 , n1517 );
buf ( n6276 , n2010 );
buf ( n6277 , n1068 );
buf ( n6278 , n393 );
buf ( n6279 , n759 );
buf ( n6280 , n1216 );
buf ( n6281 , n764 );
buf ( n6282 , n1367 );
buf ( n6283 , n519 );
buf ( n6284 , n1615 );
buf ( n6285 , n304 );
buf ( n6286 , n348 );
buf ( n6287 , n506 );
buf ( n6288 , n1644 );
buf ( n6289 , n300 );
buf ( n6290 , n320 );
buf ( n6291 , n1892 );
buf ( n6292 , n831 );
buf ( n6293 , n1329 );
buf ( n6294 , n1066 );
buf ( n6295 , n1684 );
buf ( n6296 , n482 );
buf ( n6297 , n1199 );
buf ( n6298 , n194 );
buf ( n6299 , n1588 );
buf ( n6300 , n1896 );
buf ( n6301 , n833 );
buf ( n6302 , n1346 );
buf ( n6303 , n547 );
buf ( n6304 , n536 );
buf ( n6305 , n935 );
buf ( n6306 , n1307 );
buf ( n6307 , n862 );
buf ( n6308 , n1188 );
buf ( n6309 , n892 );
buf ( n6310 , n1519 );
buf ( n6311 , n170 );
buf ( n6312 , n474 );
buf ( n6313 , n1698 );
buf ( n6314 , n696 );
buf ( n6315 , n1662 );
buf ( n6316 , n855 );
buf ( n6317 , n1395 );
buf ( n6318 , n1087 );
buf ( n6319 , n446 );
buf ( n6320 , n1750 );
buf ( n6321 , n1571 );
buf ( n6322 , n144 );
buf ( n6323 , n1373 );
buf ( n6324 , n628 );
buf ( n6325 , n1468 );
buf ( n6326 , n977 );
buf ( n6327 , n1988 );
buf ( n6328 , n1823 );
buf ( n6329 , n1260 );
buf ( n6330 , n1142 );
buf ( n6331 , n1904 );
buf ( n6332 , n1545 );
buf ( n6333 , n787 );
buf ( n6334 , n2073 );
buf ( n6335 , n1809 );
buf ( n6336 , n1563 );
buf ( n6337 , n164 );
buf ( n6338 , n1975 );
buf ( n6339 , n238 );
buf ( n6340 , n1411 );
buf ( n6341 , n390 );
buf ( n6342 , n1070 );
buf ( n6343 , n2111 );
buf ( n6344 , n627 );
buf ( n6345 , n1483 );
buf ( n6346 , n256 );
buf ( n6347 , n1418 );
buf ( n6348 , n1560 );
buf ( n6349 , n1642 );
buf ( n6350 , n1114 );
buf ( n6351 , n1917 );
buf ( n6352 , n952 );
buf ( n6353 , n1203 );
buf ( n6354 , n1184 );
buf ( n6355 , n2125 );
buf ( n6356 , n2041 );
buf ( n6357 , n1883 );
buf ( n6358 , n817 );
buf ( n6359 , n1044 );
buf ( n6360 , n711 );
buf ( n6361 , n1376 );
buf ( n6362 , n1504 );
buf ( n6363 , n1664 );
buf ( n6364 , n1442 );
buf ( n6365 , n1424 );
buf ( n6366 , n809 );
buf ( n6367 , n934 );
buf ( n6368 , n1148 );
buf ( n6369 , n342 );
buf ( n6370 , n1743 );
buf ( n6371 , n2128 );
buf ( n6372 , n1736 );
buf ( n6373 , n973 );
buf ( n6374 , n1907 );
buf ( n6375 , n2003 );
buf ( n6376 , n1018 );
buf ( n6377 , n2115 );
buf ( n6378 , n1653 );
buf ( n6379 , n1389 );
buf ( n6380 , n216 );
buf ( n6381 , n1336 );
buf ( n6382 , n7 );
buf ( n6383 , n1930 );
buf ( n6384 , n220 );
buf ( n6385 , n1276 );
buf ( n6386 , n693 );
buf ( n6387 , n1141 );
buf ( n6388 , n1210 );
buf ( n6389 , n883 );
buf ( n6390 , n1419 );
buf ( n6391 , n656 );
buf ( n6392 , n1123 );
buf ( n6393 , n561 );
buf ( n6394 , n1015 );
buf ( n6395 , n1377 );
buf ( n6396 , n309 );
buf ( n6397 , n1096 );
buf ( n6398 , n2050 );
buf ( n6399 , n1926 );
buf ( n6400 , n801 );
buf ( n6401 , n2067 );
buf ( n6402 , n1724 );
buf ( n6403 , n900 );
buf ( n6404 , n1801 );
buf ( n6405 , n1143 );
buf ( n6406 , n1331 );
buf ( n6407 , n1731 );
buf ( n6408 , n1535 );
buf ( n6409 , n1151 );
buf ( n6410 , n1604 );
buf ( n6411 , n932 );
buf ( n6412 , n196 );
buf ( n6413 , n419 );
buf ( n6414 , n1957 );
buf ( n6415 , n1002 );
buf ( n6416 , n43 );
buf ( n6417 , n244 );
buf ( n6418 , n1840 );
buf ( n6419 , n175 );
buf ( n6420 , n2017 );
buf ( n6421 , n542 );
buf ( n6422 , n927 );
buf ( n6423 , n67 );
buf ( n6424 , n685 );
buf ( n6425 , n1661 );
buf ( n6426 , n1502 );
buf ( n6427 , n1382 );
buf ( n6428 , n156 );
buf ( n6429 , n188 );
buf ( n6430 , n538 );
buf ( n6431 , n1082 );
buf ( n6432 , n1462 );
buf ( n6433 , n11 );
buf ( n6434 , n2055 );
buf ( n6435 , n2042 );
buf ( n6436 , n2130 );
buf ( n6437 , n1791 );
buf ( n6438 , n785 );
buf ( n6439 , n445 );
buf ( n6440 , n879 );
buf ( n6441 , n493 );
buf ( n6442 , n1476 );
buf ( n6443 , n489 );
buf ( n6444 , n527 );
buf ( n6445 , n843 );
buf ( n6446 , n145 );
buf ( n6447 , n1313 );
buf ( n6448 , n1541 );
buf ( n6449 , n193 );
buf ( n6450 , n31 );
buf ( n6451 , n1787 );
buf ( n6452 , n1196 );
buf ( n6453 , n44 );
buf ( n6454 , n187 );
buf ( n6455 , n154 );
buf ( n6456 , n1578 );
buf ( n6457 , n712 );
buf ( n6458 , n854 );
buf ( n6459 , n1581 );
buf ( n6460 , n1496 );
buf ( n6461 , n330 );
buf ( n6462 , n1050 );
buf ( n6463 , n1344 );
buf ( n6464 , n912 );
buf ( n6465 , n625 );
buf ( n6466 , n1935 );
buf ( n6467 , n25 );
buf ( n6468 , n454 );
buf ( n6469 , n2093 );
buf ( n6470 , n73 );
buf ( n6471 , n265 );
buf ( n6472 , n1238 );
buf ( n6473 , n1510 );
buf ( n6474 , n1708 );
buf ( n6475 , n4324 );
not ( n6476 , n6475 );
not ( n6477 , n6476 );
buf ( n6478 , n4325 );
buf ( n6479 , n6478 );
not ( n6480 , n6479 );
buf ( n6481 , n4326 );
not ( n6482 , n6481 );
not ( n6483 , n6482 );
or ( n6484 , n6480 , n6483 );
not ( n6485 , n6478 );
buf ( n6486 , n6481 );
nand ( n6487 , n6485 , n6486 );
nand ( n6488 , n6484 , n6487 );
buf ( n6489 , n4327 );
buf ( n6490 , n6489 );
and ( n6491 , n6488 , n6490 );
not ( n6492 , n6488 );
not ( n6493 , n6489 );
and ( n6494 , n6492 , n6493 );
nor ( n6495 , n6491 , n6494 );
buf ( n6496 , n4328 );
not ( n6497 , n6496 );
buf ( n6498 , n4329 );
nand ( n6499 , n6497 , n6498 );
not ( n6500 , n6499 );
buf ( n6501 , n6500 );
buf ( n6502 , n6501 );
buf ( n6503 , n4330 );
nand ( n6504 , n6502 , n6503 );
buf ( n6505 , n4331 );
buf ( n6506 , n6505 );
and ( n6507 , n6504 , n6506 );
not ( n6508 , n6504 );
not ( n6509 , n6505 );
and ( n6510 , n6508 , n6509 );
nor ( n6511 , n6507 , n6510 );
xor ( n6512 , n6495 , n6511 );
buf ( n6513 , n6500 );
buf ( n6514 , n6513 );
buf ( n6515 , n6514 );
buf ( n6516 , n4332 );
nand ( n6517 , n6515 , n6516 );
buf ( n6518 , n4333 );
buf ( n6519 , n6518 );
and ( n6520 , n6517 , n6519 );
not ( n6521 , n6517 );
not ( n6522 , n6518 );
and ( n6523 , n6521 , n6522 );
nor ( n6524 , n6520 , n6523 );
xnor ( n6525 , n6512 , n6524 );
not ( n6526 , n6525 );
not ( n6527 , n6526 );
or ( n6528 , n6477 , n6527 );
not ( n6529 , n6476 );
nand ( n6530 , n6529 , n6525 );
nand ( n6531 , n6528 , n6530 );
buf ( n6532 , n4334 );
buf ( n6533 , n6532 );
not ( n6534 , n6533 );
buf ( n6535 , n4335 );
not ( n6536 , n6535 );
not ( n6537 , n6536 );
or ( n6538 , n6534 , n6537 );
not ( n6539 , n6532 );
buf ( n6540 , n6535 );
nand ( n6541 , n6539 , n6540 );
nand ( n6542 , n6538 , n6541 );
buf ( n6543 , n4336 );
buf ( n6544 , n6543 );
and ( n6545 , n6542 , n6544 );
not ( n6546 , n6542 );
not ( n6547 , n6543 );
and ( n6548 , n6546 , n6547 );
nor ( n6549 , n6545 , n6548 );
buf ( n6550 , n4337 );
nand ( n6551 , n6502 , n6550 );
buf ( n6552 , n4338 );
xor ( n6553 , n6551 , n6552 );
xor ( n6554 , n6549 , n6553 );
buf ( n6555 , n6500 );
buf ( n6556 , n6555 );
buf ( n6557 , n6556 );
buf ( n6558 , n6557 );
buf ( n6559 , n4339 );
nand ( n6560 , n6558 , n6559 );
buf ( n6561 , n4340 );
buf ( n6562 , n6561 );
and ( n6563 , n6560 , n6562 );
not ( n6564 , n6560 );
not ( n6565 , n6561 );
and ( n6566 , n6564 , n6565 );
nor ( n6567 , n6563 , n6566 );
xnor ( n6568 , n6554 , n6567 );
not ( n6569 , n6568 );
and ( n6570 , n6531 , n6569 );
not ( n6571 , n6531 );
buf ( n6572 , n6568 );
and ( n6573 , n6571 , n6572 );
nor ( n6574 , n6570 , n6573 );
not ( n6575 , n6574 );
buf ( n6576 , n6555 );
buf ( n6577 , n6576 );
buf ( n6578 , n4341 );
nand ( n6579 , n6577 , n6578 );
buf ( n6580 , n4342 );
buf ( n6581 , n6580 );
and ( n6582 , n6579 , n6581 );
not ( n6583 , n6579 );
not ( n6584 , n6580 );
and ( n6585 , n6583 , n6584 );
nor ( n6586 , n6582 , n6585 );
buf ( n6587 , n6586 );
not ( n6588 , n6587 );
buf ( n6589 , n4343 );
buf ( n6590 , n4344 );
not ( n6591 , n6590 );
buf ( n6592 , n4345 );
buf ( n6593 , n6592 );
and ( n6594 , n6591 , n6593 );
not ( n6595 , n6591 );
not ( n6596 , n6592 );
and ( n6597 , n6595 , n6596 );
nor ( n6598 , n6594 , n6597 );
not ( n6599 , n6598 );
xor ( n6600 , n6589 , n6599 );
buf ( n6601 , n4346 );
buf ( n6602 , n4347 );
xor ( n6603 , n6601 , n6602 );
buf ( n6604 , n6556 );
buf ( n6605 , n6604 );
buf ( n6606 , n4348 );
nand ( n6607 , n6605 , n6606 );
xnor ( n6608 , n6603 , n6607 );
xnor ( n6609 , n6600 , n6608 );
not ( n6610 , n6609 );
not ( n6611 , n6610 );
or ( n6612 , n6588 , n6611 );
or ( n6613 , n6610 , n6587 );
nand ( n6614 , n6612 , n6613 );
buf ( n6615 , n4349 );
buf ( n6616 , n6615 );
not ( n6617 , n6616 );
buf ( n6618 , n4350 );
not ( n6619 , n6618 );
not ( n6620 , n6619 );
or ( n6621 , n6617 , n6620 );
not ( n6622 , n6615 );
buf ( n6623 , n6618 );
nand ( n6624 , n6622 , n6623 );
nand ( n6625 , n6621 , n6624 );
buf ( n6626 , n4351 );
not ( n6627 , n6626 );
and ( n6628 , n6625 , n6627 );
not ( n6629 , n6625 );
buf ( n6630 , n6626 );
and ( n6631 , n6629 , n6630 );
nor ( n6632 , n6628 , n6631 );
buf ( n6633 , n6513 );
buf ( n6634 , n6633 );
buf ( n6635 , n4352 );
nand ( n6636 , n6634 , n6635 );
buf ( n6637 , n4353 );
buf ( n6638 , n6637 );
and ( n6639 , n6636 , n6638 );
not ( n6640 , n6636 );
not ( n6641 , n6637 );
and ( n6642 , n6640 , n6641 );
nor ( n6643 , n6639 , n6642 );
xor ( n6644 , n6632 , n6643 );
buf ( n6645 , n6500 );
buf ( n6646 , n6645 );
buf ( n6647 , n6646 );
buf ( n6648 , n4354 );
nand ( n6649 , n6647 , n6648 );
buf ( n6650 , n4355 );
buf ( n6651 , n6650 );
and ( n6652 , n6649 , n6651 );
not ( n6653 , n6649 );
not ( n6654 , n6650 );
and ( n6655 , n6653 , n6654 );
nor ( n6656 , n6652 , n6655 );
not ( n6657 , n6656 );
xnor ( n6658 , n6644 , n6657 );
buf ( n6659 , n6658 );
and ( n6660 , n6614 , n6659 );
not ( n6661 , n6614 );
not ( n6662 , n6659 );
and ( n6663 , n6661 , n6662 );
nor ( n6664 , n6660 , n6663 );
not ( n6665 , n6664 );
nand ( n6666 , n6575 , n6665 );
not ( n6667 , n6666 );
buf ( n6668 , n4356 );
buf ( n6669 , n4357 );
not ( n6670 , n6669 );
buf ( n6671 , n4358 );
buf ( n6672 , n6671 );
nand ( n6673 , n6670 , n6672 );
not ( n6674 , n6671 );
buf ( n6675 , n6669 );
nand ( n6676 , n6674 , n6675 );
and ( n6677 , n6673 , n6676 );
xor ( n6678 , n6668 , n6677 );
buf ( n6679 , n4359 );
buf ( n6680 , n4360 );
xor ( n6681 , n6679 , n6680 );
buf ( n6682 , n4361 );
nand ( n6683 , n6605 , n6682 );
xnor ( n6684 , n6681 , n6683 );
xnor ( n6685 , n6678 , n6684 );
not ( n6686 , n6685 );
buf ( n6687 , n4362 );
buf ( n6688 , n6687 );
not ( n6689 , n6688 );
buf ( n6690 , n4363 );
buf ( n6691 , n6690 );
not ( n6692 , n6691 );
buf ( n6693 , n4364 );
not ( n6694 , n6693 );
not ( n6695 , n6694 );
or ( n6696 , n6692 , n6695 );
not ( n6697 , n6690 );
buf ( n6698 , n6693 );
nand ( n6699 , n6697 , n6698 );
nand ( n6700 , n6696 , n6699 );
buf ( n6701 , n4365 );
not ( n6702 , n6701 );
and ( n6703 , n6700 , n6702 );
not ( n6704 , n6700 );
buf ( n6705 , n6701 );
and ( n6706 , n6704 , n6705 );
nor ( n6707 , n6703 , n6706 );
buf ( n6708 , n4366 );
nand ( n6709 , n6502 , n6708 );
buf ( n6710 , n4367 );
buf ( n6711 , n6710 );
and ( n6712 , n6709 , n6711 );
not ( n6713 , n6709 );
not ( n6714 , n6710 );
and ( n6715 , n6713 , n6714 );
nor ( n6716 , n6712 , n6715 );
xor ( n6717 , n6707 , n6716 );
buf ( n6718 , n6513 );
buf ( n6719 , n6718 );
buf ( n6720 , n4368 );
nand ( n6721 , n6719 , n6720 );
buf ( n6722 , n4369 );
buf ( n6723 , n6722 );
and ( n6724 , n6721 , n6723 );
not ( n6725 , n6721 );
not ( n6726 , n6722 );
and ( n6727 , n6725 , n6726 );
nor ( n6728 , n6724 , n6727 );
xor ( n6729 , n6717 , n6728 );
not ( n6730 , n6729 );
not ( n6731 , n6730 );
not ( n6732 , n6731 );
or ( n6733 , n6689 , n6732 );
not ( n6734 , n6729 );
not ( n6735 , n6687 );
nand ( n6736 , n6734 , n6735 );
nand ( n6737 , n6733 , n6736 );
not ( n6738 , n6737 );
not ( n6739 , n6738 );
or ( n6740 , n6686 , n6739 );
not ( n6741 , n6685 );
nand ( n6742 , n6741 , n6737 );
nand ( n6743 , n6740 , n6742 );
not ( n6744 , n6743 );
and ( n6745 , n6667 , n6744 );
not ( n6746 , n6574 );
nand ( n6747 , n6746 , n6665 );
and ( n6748 , n6747 , n6743 );
nor ( n6749 , n6745 , n6748 );
not ( n6750 , n6749 );
not ( n6751 , n6750 );
buf ( n6752 , n4370 );
buf ( n6753 , n6752 );
not ( n6754 , n6753 );
buf ( n6755 , n4371 );
not ( n6756 , n6755 );
not ( n6757 , n6756 );
or ( n6758 , n6754 , n6757 );
not ( n6759 , n6752 );
buf ( n6760 , n6755 );
nand ( n6761 , n6759 , n6760 );
nand ( n6762 , n6758 , n6761 );
buf ( n6763 , n4372 );
not ( n6764 , n6763 );
and ( n6765 , n6762 , n6764 );
not ( n6766 , n6762 );
buf ( n6767 , n6763 );
and ( n6768 , n6766 , n6767 );
nor ( n6769 , n6765 , n6768 );
buf ( n6770 , n6501 );
buf ( n6771 , n4373 );
nand ( n6772 , n6770 , n6771 );
buf ( n6773 , n4374 );
buf ( n6774 , n6773 );
and ( n6775 , n6772 , n6774 );
not ( n6776 , n6772 );
not ( n6777 , n6773 );
and ( n6778 , n6776 , n6777 );
nor ( n6779 , n6775 , n6778 );
xor ( n6780 , n6769 , n6779 );
buf ( n6781 , n4375 );
nand ( n6782 , n6557 , n6781 );
buf ( n6783 , n4376 );
buf ( n6784 , n6783 );
and ( n6785 , n6782 , n6784 );
not ( n6786 , n6782 );
not ( n6787 , n6783 );
and ( n6788 , n6786 , n6787 );
nor ( n6789 , n6785 , n6788 );
not ( n6790 , n6789 );
xnor ( n6791 , n6780 , n6790 );
buf ( n6792 , n6791 );
not ( n6793 , n6792 );
buf ( n6794 , n4377 );
buf ( n6795 , n6794 );
not ( n6796 , n6795 );
buf ( n6797 , n4378 );
buf ( n6798 , n6797 );
not ( n6799 , n6798 );
buf ( n6800 , n4379 );
not ( n6801 , n6800 );
not ( n6802 , n6801 );
or ( n6803 , n6799 , n6802 );
not ( n6804 , n6797 );
buf ( n6805 , n6800 );
nand ( n6806 , n6804 , n6805 );
nand ( n6807 , n6803 , n6806 );
buf ( n6808 , n4380 );
not ( n6809 , n6808 );
and ( n6810 , n6807 , n6809 );
not ( n6811 , n6807 );
buf ( n6812 , n6808 );
and ( n6813 , n6811 , n6812 );
nor ( n6814 , n6810 , n6813 );
buf ( n6815 , n6645 );
buf ( n6816 , n6815 );
buf ( n6817 , n4381 );
nand ( n6818 , n6816 , n6817 );
buf ( n6819 , n4382 );
buf ( n6820 , n6819 );
and ( n6821 , n6818 , n6820 );
not ( n6822 , n6818 );
not ( n6823 , n6819 );
and ( n6824 , n6822 , n6823 );
nor ( n6825 , n6821 , n6824 );
xor ( n6826 , n6814 , n6825 );
buf ( n6827 , n6555 );
buf ( n6828 , n6827 );
buf ( n6829 , n4383 );
nand ( n6830 , n6828 , n6829 );
buf ( n6831 , n4384 );
buf ( n6832 , n6831 );
and ( n6833 , n6830 , n6832 );
not ( n6834 , n6830 );
not ( n6835 , n6831 );
and ( n6836 , n6834 , n6835 );
nor ( n6837 , n6833 , n6836 );
not ( n6838 , n6837 );
xnor ( n6839 , n6826 , n6838 );
not ( n6840 , n6839 );
or ( n6841 , n6796 , n6840 );
xor ( n6842 , n6814 , n6837 );
buf ( n6843 , n6825 );
xnor ( n6844 , n6842 , n6843 );
not ( n6845 , n6794 );
nand ( n6846 , n6844 , n6845 );
nand ( n6847 , n6841 , n6846 );
not ( n6848 , n6847 );
or ( n6849 , n6793 , n6848 );
or ( n6850 , n6847 , n6791 );
nand ( n6851 , n6849 , n6850 );
not ( n6852 , n6851 );
buf ( n6853 , n4385 );
buf ( n6854 , n6853 );
not ( n6855 , n6854 );
buf ( n6856 , n4386 );
not ( n6857 , n6856 );
not ( n6858 , n6857 );
or ( n6859 , n6855 , n6858 );
not ( n6860 , n6853 );
buf ( n6861 , n6856 );
nand ( n6862 , n6860 , n6861 );
nand ( n6863 , n6859 , n6862 );
buf ( n6864 , n4387 );
not ( n6865 , n6864 );
and ( n6866 , n6863 , n6865 );
not ( n6867 , n6863 );
buf ( n6868 , n6864 );
and ( n6869 , n6867 , n6868 );
nor ( n6870 , n6866 , n6869 );
buf ( n6871 , n6827 );
buf ( n6872 , n4388 );
nand ( n6873 , n6871 , n6872 );
buf ( n6874 , n4389 );
buf ( n6875 , n6874 );
and ( n6876 , n6873 , n6875 );
not ( n6877 , n6873 );
not ( n6878 , n6874 );
and ( n6879 , n6877 , n6878 );
nor ( n6880 , n6876 , n6879 );
xor ( n6881 , n6870 , n6880 );
buf ( n6882 , n4390 );
nand ( n6883 , n6647 , n6882 );
buf ( n6884 , n4391 );
not ( n6885 , n6884 );
and ( n6886 , n6883 , n6885 );
not ( n6887 , n6883 );
buf ( n6888 , n6884 );
and ( n6889 , n6887 , n6888 );
nor ( n6890 , n6886 , n6889 );
xnor ( n6891 , n6881 , n6890 );
not ( n6892 , n6891 );
not ( n6893 , n6892 );
not ( n6894 , n6893 );
buf ( n6895 , n4392 );
buf ( n6896 , n6895 );
not ( n6897 , n6896 );
buf ( n6898 , n4393 );
buf ( n6899 , n6898 );
not ( n6900 , n6899 );
buf ( n6901 , n4394 );
not ( n6902 , n6901 );
not ( n6903 , n6902 );
or ( n6904 , n6900 , n6903 );
not ( n6905 , n6898 );
buf ( n6906 , n6901 );
nand ( n6907 , n6905 , n6906 );
nand ( n6908 , n6904 , n6907 );
buf ( n6909 , n4395 );
buf ( n6910 , n6909 );
and ( n6911 , n6908 , n6910 );
not ( n6912 , n6908 );
not ( n6913 , n6909 );
and ( n6914 , n6912 , n6913 );
nor ( n6915 , n6911 , n6914 );
buf ( n6916 , n6827 );
buf ( n6917 , n4396 );
nand ( n6918 , n6916 , n6917 );
buf ( n6919 , n4397 );
buf ( n6920 , n6919 );
and ( n6921 , n6918 , n6920 );
not ( n6922 , n6918 );
not ( n6923 , n6919 );
and ( n6924 , n6922 , n6923 );
nor ( n6925 , n6921 , n6924 );
xor ( n6926 , n6915 , n6925 );
buf ( n6927 , n6645 );
buf ( n6928 , n4398 );
nand ( n6929 , n6927 , n6928 );
buf ( n6930 , n4399 );
buf ( n6931 , n6930 );
and ( n6932 , n6929 , n6931 );
not ( n6933 , n6929 );
not ( n6934 , n6930 );
and ( n6935 , n6933 , n6934 );
nor ( n6936 , n6932 , n6935 );
xnor ( n6937 , n6926 , n6936 );
not ( n6938 , n6937 );
or ( n6939 , n6897 , n6938 );
xor ( n6940 , n6915 , n6936 );
not ( n6941 , n6925 );
xnor ( n6942 , n6940 , n6941 );
not ( n6943 , n6895 );
nand ( n6944 , n6942 , n6943 );
nand ( n6945 , n6939 , n6944 );
not ( n6946 , n6945 );
or ( n6947 , n6894 , n6946 );
buf ( n6948 , n6891 );
buf ( n6949 , n6948 );
or ( n6950 , n6945 , n6949 );
nand ( n6951 , n6947 , n6950 );
nand ( n6952 , n6852 , n6951 );
buf ( n6953 , n4400 );
not ( n6954 , n6953 );
not ( n6955 , n6954 );
buf ( n6956 , n4401 );
buf ( n6957 , n4402 );
buf ( n6958 , n6957 );
not ( n6959 , n6958 );
buf ( n6960 , n4403 );
not ( n6961 , n6960 );
not ( n6962 , n6961 );
or ( n6963 , n6959 , n6962 );
not ( n6964 , n6957 );
buf ( n6965 , n6960 );
nand ( n6966 , n6964 , n6965 );
nand ( n6967 , n6963 , n6966 );
not ( n6968 , n6967 );
xor ( n6969 , n6956 , n6968 );
buf ( n6970 , n4404 );
buf ( n6971 , n4405 );
xor ( n6972 , n6970 , n6971 );
buf ( n6973 , n6916 );
buf ( n6974 , n4406 );
nand ( n6975 , n6973 , n6974 );
xnor ( n6976 , n6972 , n6975 );
xnor ( n6977 , n6969 , n6976 );
not ( n6978 , n6977 );
or ( n6979 , n6955 , n6978 );
not ( n6980 , n6954 );
xor ( n6981 , n6956 , n6967 );
xnor ( n6982 , n6981 , n6976 );
nand ( n6983 , n6980 , n6982 );
nand ( n6984 , n6979 , n6983 );
buf ( n6985 , n4407 );
buf ( n6986 , n6985 );
not ( n6987 , n6986 );
buf ( n6988 , n4408 );
not ( n6989 , n6988 );
not ( n6990 , n6989 );
or ( n6991 , n6987 , n6990 );
not ( n6992 , n6985 );
buf ( n6993 , n6988 );
nand ( n6994 , n6992 , n6993 );
nand ( n6995 , n6991 , n6994 );
buf ( n6996 , n4409 );
buf ( n6997 , n6996 );
and ( n6998 , n6995 , n6997 );
not ( n6999 , n6995 );
not ( n7000 , n6996 );
and ( n7001 , n6999 , n7000 );
nor ( n7002 , n6998 , n7001 );
buf ( n7003 , n4410 );
nand ( n7004 , n6514 , n7003 );
buf ( n7005 , n4411 );
buf ( n7006 , n7005 );
and ( n7007 , n7004 , n7006 );
not ( n7008 , n7004 );
not ( n7009 , n7005 );
and ( n7010 , n7008 , n7009 );
nor ( n7011 , n7007 , n7010 );
xor ( n7012 , n7002 , n7011 );
buf ( n7013 , n6513 );
buf ( n7014 , n7013 );
buf ( n7015 , n4412 );
nand ( n7016 , n7014 , n7015 );
buf ( n7017 , n4413 );
not ( n7018 , n7017 );
and ( n7019 , n7016 , n7018 );
not ( n7020 , n7016 );
buf ( n7021 , n7017 );
and ( n7022 , n7020 , n7021 );
nor ( n7023 , n7019 , n7022 );
xnor ( n7024 , n7012 , n7023 );
buf ( n7025 , n7024 );
not ( n7026 , n7025 );
and ( n7027 , n6984 , n7026 );
not ( n7028 , n6984 );
not ( n7029 , n7024 );
not ( n7030 , n7029 );
and ( n7031 , n7028 , n7030 );
nor ( n7032 , n7027 , n7031 );
and ( n7033 , n6952 , n7032 );
not ( n7034 , n6952 );
not ( n7035 , n7032 );
and ( n7036 , n7034 , n7035 );
nor ( n7037 , n7033 , n7036 );
not ( n7038 , n7037 );
not ( n7039 , n7038 );
not ( n7040 , n6743 );
nand ( n7041 , n7040 , n6574 );
not ( n7042 , n7041 );
buf ( n7043 , n4414 );
buf ( n7044 , n7043 );
not ( n7045 , n7044 );
buf ( n7046 , n4415 );
not ( n7047 , n7046 );
not ( n7048 , n7047 );
or ( n7049 , n7045 , n7048 );
not ( n7050 , n7043 );
buf ( n7051 , n7046 );
nand ( n7052 , n7050 , n7051 );
nand ( n7053 , n7049 , n7052 );
not ( n7054 , n7053 );
buf ( n7055 , n4416 );
not ( n7056 , n7055 );
buf ( n7057 , n4417 );
nand ( n7058 , n6577 , n7057 );
buf ( n7059 , n4418 );
buf ( n7060 , n7059 );
and ( n7061 , n7058 , n7060 );
not ( n7062 , n7058 );
not ( n7063 , n7059 );
and ( n7064 , n7062 , n7063 );
nor ( n7065 , n7061 , n7064 );
xor ( n7066 , n7056 , n7065 );
buf ( n7067 , n6770 );
buf ( n7068 , n4419 );
nand ( n7069 , n7067 , n7068 );
buf ( n7070 , n4420 );
not ( n7071 , n7070 );
and ( n7072 , n7069 , n7071 );
not ( n7073 , n7069 );
buf ( n7074 , n7070 );
and ( n7075 , n7073 , n7074 );
nor ( n7076 , n7072 , n7075 );
xnor ( n7077 , n7066 , n7076 );
not ( n7078 , n7077 );
or ( n7079 , n7054 , n7078 );
not ( n7080 , n7077 );
not ( n7081 , n7053 );
nand ( n7082 , n7080 , n7081 );
nand ( n7083 , n7079 , n7082 );
not ( n7084 , n7083 );
not ( n7085 , n7084 );
buf ( n7086 , n4421 );
buf ( n7087 , n7086 );
not ( n7088 , n7087 );
buf ( n7089 , n4422 );
buf ( n7090 , n7089 );
not ( n7091 , n7090 );
buf ( n7092 , n4423 );
not ( n7093 , n7092 );
not ( n7094 , n7093 );
or ( n7095 , n7091 , n7094 );
not ( n7096 , n7089 );
buf ( n7097 , n7092 );
nand ( n7098 , n7096 , n7097 );
nand ( n7099 , n7095 , n7098 );
buf ( n7100 , n4424 );
not ( n7101 , n7100 );
and ( n7102 , n7099 , n7101 );
not ( n7103 , n7099 );
buf ( n7104 , n7100 );
and ( n7105 , n7103 , n7104 );
nor ( n7106 , n7102 , n7105 );
buf ( n7107 , n6718 );
buf ( n7108 , n4425 );
nand ( n7109 , n7107 , n7108 );
buf ( n7110 , n4426 );
buf ( n7111 , n7110 );
and ( n7112 , n7109 , n7111 );
not ( n7113 , n7109 );
not ( n7114 , n7110 );
and ( n7115 , n7113 , n7114 );
nor ( n7116 , n7112 , n7115 );
xor ( n7117 , n7106 , n7116 );
buf ( n7118 , n4427 );
nand ( n7119 , n7067 , n7118 );
buf ( n7120 , n4428 );
buf ( n7121 , n7120 );
and ( n7122 , n7119 , n7121 );
not ( n7123 , n7119 );
not ( n7124 , n7120 );
and ( n7125 , n7123 , n7124 );
nor ( n7126 , n7122 , n7125 );
xnor ( n7127 , n7117 , n7126 );
buf ( n7128 , n7127 );
not ( n7129 , n7128 );
not ( n7130 , n7129 );
or ( n7131 , n7088 , n7130 );
or ( n7132 , n7129 , n7087 );
nand ( n7133 , n7131 , n7132 );
not ( n7134 , n7133 );
and ( n7135 , n7085 , n7134 );
not ( n7136 , n7083 );
and ( n7137 , n7136 , n7133 );
nor ( n7138 , n7135 , n7137 );
not ( n7139 , n7138 );
not ( n7140 , n7139 );
and ( n7141 , n7042 , n7140 );
and ( n7142 , n7041 , n7139 );
nor ( n7143 , n7141 , n7142 );
not ( n7144 , n7143 );
not ( n7145 , n7144 );
or ( n7146 , n7039 , n7145 );
nand ( n7147 , n7143 , n7037 );
nand ( n7148 , n7146 , n7147 );
buf ( n7149 , n4429 );
buf ( n7150 , n7149 );
buf ( n7151 , n4430 );
buf ( n7152 , n7151 );
not ( n7153 , n7152 );
buf ( n7154 , n4431 );
not ( n7155 , n7154 );
not ( n7156 , n7155 );
or ( n7157 , n7153 , n7156 );
not ( n7158 , n7151 );
buf ( n7159 , n7154 );
nand ( n7160 , n7158 , n7159 );
nand ( n7161 , n7157 , n7160 );
buf ( n7162 , n4432 );
buf ( n7163 , n7162 );
and ( n7164 , n7161 , n7163 );
not ( n7165 , n7161 );
not ( n7166 , n7162 );
and ( n7167 , n7165 , n7166 );
nor ( n7168 , n7164 , n7167 );
buf ( n7169 , n4433 );
nand ( n7170 , n6604 , n7169 );
buf ( n7171 , n4434 );
buf ( n7172 , n7171 );
and ( n7173 , n7170 , n7172 );
not ( n7174 , n7170 );
not ( n7175 , n7171 );
and ( n7176 , n7174 , n7175 );
nor ( n7177 , n7173 , n7176 );
xor ( n7178 , n7168 , n7177 );
buf ( n7179 , n4435 );
nand ( n7180 , n6816 , n7179 );
buf ( n7181 , n4436 );
not ( n7182 , n7181 );
and ( n7183 , n7180 , n7182 );
not ( n7184 , n7180 );
buf ( n7185 , n7181 );
and ( n7186 , n7184 , n7185 );
nor ( n7187 , n7183 , n7186 );
xnor ( n7188 , n7178 , n7187 );
buf ( n7189 , n7188 );
xor ( n7190 , n7150 , n7189 );
buf ( n7191 , n4437 );
buf ( n7192 , n4438 );
not ( n7193 , n7192 );
xor ( n7194 , n7191 , n7193 );
buf ( n7195 , n4439 );
not ( n7196 , n7195 );
buf ( n7197 , n6827 );
buf ( n7198 , n4440 );
nand ( n7199 , n7197 , n7198 );
not ( n7200 , n7199 );
or ( n7201 , n7196 , n7200 );
buf ( n7202 , n6576 );
nand ( n7203 , n7202 , n7198 );
or ( n7204 , n7203 , n7195 );
nand ( n7205 , n7201 , n7204 );
xnor ( n7206 , n7194 , n7205 );
not ( n7207 , n7206 );
not ( n7208 , n7207 );
buf ( n7209 , n4441 );
buf ( n7210 , n7209 );
not ( n7211 , n7210 );
buf ( n7212 , n4442 );
not ( n7213 , n7212 );
not ( n7214 , n7213 );
or ( n7215 , n7211 , n7214 );
not ( n7216 , n7209 );
buf ( n7217 , n7212 );
nand ( n7218 , n7216 , n7217 );
nand ( n7219 , n7215 , n7218 );
not ( n7220 , n7219 );
and ( n7221 , n7208 , n7220 );
and ( n7222 , n7207 , n7219 );
nor ( n7223 , n7221 , n7222 );
buf ( n7224 , n7223 );
xnor ( n7225 , n7190 , n7224 );
not ( n7226 , n7225 );
buf ( n7227 , n4443 );
not ( n7228 , n7227 );
buf ( n7229 , n4444 );
buf ( n7230 , n7229 );
not ( n7231 , n7230 );
buf ( n7232 , n4445 );
not ( n7233 , n7232 );
not ( n7234 , n7233 );
or ( n7235 , n7231 , n7234 );
not ( n7236 , n7229 );
buf ( n7237 , n7232 );
nand ( n7238 , n7236 , n7237 );
nand ( n7239 , n7235 , n7238 );
buf ( n7240 , n4446 );
not ( n7241 , n7240 );
and ( n7242 , n7239 , n7241 );
not ( n7243 , n7239 );
buf ( n7244 , n7240 );
and ( n7245 , n7243 , n7244 );
nor ( n7246 , n7242 , n7245 );
buf ( n7247 , n6514 );
buf ( n7248 , n4447 );
nand ( n7249 , n7247 , n7248 );
buf ( n7250 , n4448 );
buf ( n7251 , n7250 );
and ( n7252 , n7249 , n7251 );
not ( n7253 , n7249 );
not ( n7254 , n7250 );
and ( n7255 , n7253 , n7254 );
nor ( n7256 , n7252 , n7255 );
xor ( n7257 , n7246 , n7256 );
buf ( n7258 , n6514 );
buf ( n7259 , n7258 );
buf ( n7260 , n4449 );
nand ( n7261 , n7259 , n7260 );
buf ( n7262 , n4450 );
not ( n7263 , n7262 );
and ( n7264 , n7261 , n7263 );
not ( n7265 , n7261 );
buf ( n7266 , n7262 );
and ( n7267 , n7265 , n7266 );
nor ( n7268 , n7264 , n7267 );
xnor ( n7269 , n7257 , n7268 );
buf ( n7270 , n7269 );
not ( n7271 , n7270 );
or ( n7272 , n7228 , n7271 );
or ( n7273 , n7270 , n7227 );
nand ( n7274 , n7272 , n7273 );
buf ( n7275 , n4451 );
buf ( n7276 , n7275 );
not ( n7277 , n7276 );
buf ( n7278 , n4452 );
not ( n7279 , n7278 );
not ( n7280 , n7279 );
or ( n7281 , n7277 , n7280 );
not ( n7282 , n7275 );
buf ( n7283 , n7278 );
nand ( n7284 , n7282 , n7283 );
nand ( n7285 , n7281 , n7284 );
buf ( n7286 , n4453 );
not ( n7287 , n7286 );
and ( n7288 , n7285 , n7287 );
not ( n7289 , n7285 );
buf ( n7290 , n7286 );
and ( n7291 , n7289 , n7290 );
nor ( n7292 , n7288 , n7291 );
buf ( n7293 , n6576 );
buf ( n7294 , n4454 );
nand ( n7295 , n7293 , n7294 );
buf ( n7296 , n4455 );
buf ( n7297 , n7296 );
and ( n7298 , n7295 , n7297 );
not ( n7299 , n7295 );
not ( n7300 , n7296 );
and ( n7301 , n7299 , n7300 );
nor ( n7302 , n7298 , n7301 );
xor ( n7303 , n7292 , n7302 );
buf ( n7304 , n4456 );
nand ( n7305 , n7247 , n7304 );
buf ( n7306 , n4457 );
not ( n7307 , n7306 );
and ( n7308 , n7305 , n7307 );
not ( n7309 , n7305 );
buf ( n7310 , n7306 );
and ( n7311 , n7309 , n7310 );
nor ( n7312 , n7308 , n7311 );
xnor ( n7313 , n7303 , n7312 );
buf ( n7314 , n7313 );
buf ( n7315 , n7314 );
and ( n7316 , n7274 , n7315 );
not ( n7317 , n7274 );
not ( n7318 , n7314 );
and ( n7319 , n7317 , n7318 );
nor ( n7320 , n7316 , n7319 );
not ( n7321 , n7320 );
nand ( n7322 , n7226 , n7321 );
buf ( n7323 , n4458 );
buf ( n7324 , n7323 );
not ( n7325 , n7324 );
buf ( n7326 , n4459 );
buf ( n7327 , n7326 );
not ( n7328 , n7327 );
buf ( n7329 , n4460 );
not ( n7330 , n7329 );
not ( n7331 , n7330 );
or ( n7332 , n7328 , n7331 );
not ( n7333 , n7326 );
buf ( n7334 , n7329 );
nand ( n7335 , n7333 , n7334 );
nand ( n7336 , n7332 , n7335 );
buf ( n7337 , n4461 );
buf ( n7338 , n7337 );
and ( n7339 , n7336 , n7338 );
not ( n7340 , n7336 );
not ( n7341 , n7337 );
and ( n7342 , n7340 , n7341 );
nor ( n7343 , n7339 , n7342 );
buf ( n7344 , n6576 );
buf ( n7345 , n4462 );
nand ( n7346 , n7344 , n7345 );
buf ( n7347 , n4463 );
buf ( n7348 , n7347 );
and ( n7349 , n7346 , n7348 );
not ( n7350 , n7346 );
not ( n7351 , n7347 );
and ( n7352 , n7350 , n7351 );
nor ( n7353 , n7349 , n7352 );
xor ( n7354 , n7343 , n7353 );
buf ( n7355 , n6718 );
buf ( n7356 , n4464 );
nand ( n7357 , n7355 , n7356 );
buf ( n7358 , n4465 );
buf ( n7359 , n7358 );
and ( n7360 , n7357 , n7359 );
not ( n7361 , n7357 );
not ( n7362 , n7358 );
and ( n7363 , n7361 , n7362 );
nor ( n7364 , n7360 , n7363 );
not ( n7365 , n7364 );
xnor ( n7366 , n7354 , n7365 );
not ( n7367 , n7366 );
not ( n7368 , n7367 );
or ( n7369 , n7325 , n7368 );
not ( n7370 , n7366 );
or ( n7371 , n7370 , n7324 );
nand ( n7372 , n7369 , n7371 );
buf ( n7373 , n4466 );
buf ( n7374 , n7373 );
not ( n7375 , n7374 );
buf ( n7376 , n4467 );
not ( n7377 , n7376 );
not ( n7378 , n7377 );
or ( n7379 , n7375 , n7378 );
not ( n7380 , n7373 );
buf ( n7381 , n7376 );
nand ( n7382 , n7380 , n7381 );
nand ( n7383 , n7379 , n7382 );
buf ( n7384 , n4468 );
not ( n7385 , n7384 );
and ( n7386 , n7383 , n7385 );
not ( n7387 , n7383 );
buf ( n7388 , n7384 );
and ( n7389 , n7387 , n7388 );
nor ( n7390 , n7386 , n7389 );
buf ( n7391 , n4469 );
nand ( n7392 , n6815 , n7391 );
buf ( n7393 , n4470 );
not ( n7394 , n7393 );
and ( n7395 , n7392 , n7394 );
not ( n7396 , n7392 );
buf ( n7397 , n7393 );
and ( n7398 , n7396 , n7397 );
nor ( n7399 , n7395 , n7398 );
xor ( n7400 , n7390 , n7399 );
buf ( n7401 , n4471 );
nand ( n7402 , n6634 , n7401 );
buf ( n7403 , n4472 );
not ( n7404 , n7403 );
and ( n7405 , n7402 , n7404 );
not ( n7406 , n7402 );
buf ( n7407 , n7403 );
and ( n7408 , n7406 , n7407 );
nor ( n7409 , n7405 , n7408 );
xnor ( n7410 , n7400 , n7409 );
not ( n7411 , n7410 );
buf ( n7412 , n7411 );
and ( n7413 , n7372 , n7412 );
not ( n7414 , n7372 );
and ( n7415 , n7414 , n7410 );
nor ( n7416 , n7413 , n7415 );
buf ( n7417 , n7416 );
xnor ( n7418 , n7322 , n7417 );
not ( n7419 , n7418 );
and ( n7420 , n7148 , n7419 );
not ( n7421 , n7148 );
and ( n7422 , n7421 , n7418 );
nor ( n7423 , n7420 , n7422 );
not ( n7424 , n7423 );
not ( n7425 , n7424 );
buf ( n7426 , n4473 );
buf ( n7427 , n7426 );
not ( n7428 , n7427 );
buf ( n7429 , n4474 );
buf ( n7430 , n4475 );
buf ( n7431 , n7430 );
not ( n7432 , n7431 );
buf ( n7433 , n4476 );
not ( n7434 , n7433 );
not ( n7435 , n7434 );
or ( n7436 , n7432 , n7435 );
not ( n7437 , n7430 );
buf ( n7438 , n7433 );
nand ( n7439 , n7437 , n7438 );
nand ( n7440 , n7436 , n7439 );
xor ( n7441 , n7429 , n7440 );
buf ( n7442 , n4477 );
buf ( n7443 , n4478 );
not ( n7444 , n7443 );
xor ( n7445 , n7442 , n7444 );
buf ( n7446 , n4479 );
nand ( n7447 , n7067 , n7446 );
xnor ( n7448 , n7445 , n7447 );
xnor ( n7449 , n7441 , n7448 );
not ( n7450 , n7449 );
not ( n7451 , n7450 );
or ( n7452 , n7428 , n7451 );
not ( n7453 , n7449 );
or ( n7454 , n7453 , n7427 );
nand ( n7455 , n7452 , n7454 );
buf ( n7456 , n4480 );
not ( n7457 , n7456 );
buf ( n7458 , n4481 );
nand ( n7459 , n6514 , n7458 );
buf ( n7460 , n4482 );
buf ( n7461 , n7460 );
and ( n7462 , n7459 , n7461 );
not ( n7463 , n7459 );
not ( n7464 , n7460 );
and ( n7465 , n7463 , n7464 );
nor ( n7466 , n7462 , n7465 );
xor ( n7467 , n7457 , n7466 );
buf ( n7468 , n4483 );
nand ( n7469 , n6828 , n7468 );
buf ( n7470 , n4484 );
buf ( n7471 , n7470 );
and ( n7472 , n7469 , n7471 );
not ( n7473 , n7469 );
not ( n7474 , n7470 );
and ( n7475 , n7473 , n7474 );
nor ( n7476 , n7472 , n7475 );
xnor ( n7477 , n7467 , n7476 );
not ( n7478 , n7477 );
buf ( n7479 , n4485 );
buf ( n7480 , n7479 );
not ( n7481 , n7480 );
buf ( n7482 , n4486 );
not ( n7483 , n7482 );
not ( n7484 , n7483 );
or ( n7485 , n7481 , n7484 );
not ( n7486 , n7479 );
buf ( n7487 , n7482 );
nand ( n7488 , n7486 , n7487 );
nand ( n7489 , n7485 , n7488 );
not ( n7490 , n7489 );
not ( n7491 , n7490 );
and ( n7492 , n7478 , n7491 );
and ( n7493 , n7477 , n7490 );
nor ( n7494 , n7492 , n7493 );
buf ( n7495 , n7494 );
xor ( n7496 , n7455 , n7495 );
not ( n7497 , n7496 );
buf ( n7498 , n4487 );
buf ( n7499 , n7498 );
not ( n7500 , n7499 );
buf ( n7501 , n4488 );
buf ( n7502 , n7501 );
not ( n7503 , n7502 );
buf ( n7504 , n4489 );
not ( n7505 , n7504 );
not ( n7506 , n7505 );
or ( n7507 , n7503 , n7506 );
not ( n7508 , n7501 );
buf ( n7509 , n7504 );
nand ( n7510 , n7508 , n7509 );
nand ( n7511 , n7507 , n7510 );
buf ( n7512 , n4490 );
buf ( n7513 , n7512 );
and ( n7514 , n7511 , n7513 );
not ( n7515 , n7511 );
not ( n7516 , n7512 );
and ( n7517 , n7515 , n7516 );
nor ( n7518 , n7514 , n7517 );
buf ( n7519 , n4491 );
nand ( n7520 , n6634 , n7519 );
buf ( n7521 , n4492 );
buf ( n7522 , n7521 );
and ( n7523 , n7520 , n7522 );
not ( n7524 , n7520 );
not ( n7525 , n7521 );
and ( n7526 , n7524 , n7525 );
nor ( n7527 , n7523 , n7526 );
xor ( n7528 , n7518 , n7527 );
buf ( n7529 , n4493 );
nand ( n7530 , n6515 , n7529 );
buf ( n7531 , n4494 );
buf ( n7532 , n7531 );
and ( n7533 , n7530 , n7532 );
not ( n7534 , n7530 );
not ( n7535 , n7531 );
and ( n7536 , n7534 , n7535 );
nor ( n7537 , n7533 , n7536 );
buf ( n7538 , n7537 );
xnor ( n7539 , n7528 , n7538 );
buf ( n7540 , n7539 );
not ( n7541 , n7540 );
or ( n7542 , n7500 , n7541 );
or ( n7543 , n7540 , n7499 );
nand ( n7544 , n7542 , n7543 );
buf ( n7545 , n4495 );
buf ( n7546 , n7545 );
not ( n7547 , n7546 );
buf ( n7548 , n4496 );
not ( n7549 , n7548 );
not ( n7550 , n7549 );
or ( n7551 , n7547 , n7550 );
not ( n7552 , n7545 );
buf ( n7553 , n7548 );
nand ( n7554 , n7552 , n7553 );
nand ( n7555 , n7551 , n7554 );
buf ( n7556 , n4497 );
buf ( n7557 , n7556 );
and ( n7558 , n7555 , n7557 );
not ( n7559 , n7555 );
not ( n7560 , n7556 );
and ( n7561 , n7559 , n7560 );
nor ( n7562 , n7558 , n7561 );
buf ( n7563 , n6556 );
buf ( n7564 , n4498 );
nand ( n7565 , n7563 , n7564 );
buf ( n7566 , n4499 );
xor ( n7567 , n7565 , n7566 );
xor ( n7568 , n7562 , n7567 );
buf ( n7569 , n6502 );
buf ( n7570 , n4500 );
nand ( n7571 , n7569 , n7570 );
buf ( n7572 , n4501 );
buf ( n7573 , n7572 );
and ( n7574 , n7571 , n7573 );
not ( n7575 , n7571 );
not ( n7576 , n7572 );
and ( n7577 , n7575 , n7576 );
nor ( n7578 , n7574 , n7577 );
xnor ( n7579 , n7568 , n7578 );
buf ( n7580 , n7579 );
and ( n7581 , n7544 , n7580 );
not ( n7582 , n7544 );
not ( n7583 , n7580 );
and ( n7584 , n7582 , n7583 );
nor ( n7585 , n7581 , n7584 );
nand ( n7586 , n7497 , n7585 );
not ( n7587 , n7586 );
buf ( n7588 , n4502 );
buf ( n7589 , n7588 );
not ( n7590 , n7589 );
buf ( n7591 , n4503 );
not ( n7592 , n7591 );
not ( n7593 , n7592 );
or ( n7594 , n7590 , n7593 );
not ( n7595 , n7588 );
buf ( n7596 , n7591 );
nand ( n7597 , n7595 , n7596 );
nand ( n7598 , n7594 , n7597 );
buf ( n7599 , n4504 );
buf ( n7600 , n7599 );
and ( n7601 , n7598 , n7600 );
not ( n7602 , n7598 );
not ( n7603 , n7599 );
and ( n7604 , n7602 , n7603 );
nor ( n7605 , n7601 , n7604 );
buf ( n7606 , n6556 );
buf ( n7607 , n4505 );
nand ( n7608 , n7606 , n7607 );
buf ( n7609 , n4506 );
buf ( n7610 , n7609 );
and ( n7611 , n7608 , n7610 );
not ( n7612 , n7608 );
not ( n7613 , n7609 );
and ( n7614 , n7612 , n7613 );
nor ( n7615 , n7611 , n7614 );
xor ( n7616 , n7605 , n7615 );
buf ( n7617 , n4507 );
nand ( n7618 , n7606 , n7617 );
buf ( n7619 , n4508 );
buf ( n7620 , n7619 );
and ( n7621 , n7618 , n7620 );
not ( n7622 , n7618 );
not ( n7623 , n7619 );
and ( n7624 , n7622 , n7623 );
nor ( n7625 , n7621 , n7624 );
not ( n7626 , n7625 );
xor ( n7627 , n7616 , n7626 );
buf ( n7628 , n4509 );
buf ( n7629 , n7628 );
nand ( n7630 , n7627 , n7629 );
not ( n7631 , n7630 );
nor ( n7632 , n7627 , n7629 );
nor ( n7633 , n7631 , n7632 );
not ( n7634 , n7633 );
buf ( n7635 , n4510 );
buf ( n7636 , n7635 );
not ( n7637 , n7636 );
buf ( n7638 , n4511 );
not ( n7639 , n7638 );
not ( n7640 , n7639 );
or ( n7641 , n7637 , n7640 );
not ( n7642 , n7635 );
buf ( n7643 , n7638 );
nand ( n7644 , n7642 , n7643 );
nand ( n7645 , n7641 , n7644 );
not ( n7646 , n7645 );
not ( n7647 , n7646 );
buf ( n7648 , n4512 );
buf ( n7649 , n4513 );
not ( n7650 , n7649 );
xor ( n7651 , n7648 , n7650 );
buf ( n7652 , n4514 );
nand ( n7653 , n7247 , n7652 );
buf ( n7654 , n4515 );
not ( n7655 , n7654 );
and ( n7656 , n7653 , n7655 );
not ( n7657 , n7653 );
buf ( n7658 , n7654 );
and ( n7659 , n7657 , n7658 );
nor ( n7660 , n7656 , n7659 );
xnor ( n7661 , n7651 , n7660 );
not ( n7662 , n7661 );
or ( n7663 , n7647 , n7662 );
or ( n7664 , n7661 , n7646 );
nand ( n7665 , n7663 , n7664 );
buf ( n7666 , n7665 );
not ( n7667 , n7666 );
or ( n7668 , n7634 , n7667 );
or ( n7669 , n7666 , n7633 );
nand ( n7670 , n7668 , n7669 );
buf ( n7671 , n7670 );
not ( n7672 , n7671 );
and ( n7673 , n7587 , n7672 );
and ( n7674 , n7586 , n7671 );
nor ( n7675 , n7673 , n7674 );
not ( n7676 , n7675 );
not ( n7677 , n7676 );
buf ( n7678 , n4516 );
buf ( n7679 , n7678 );
buf ( n7680 , n4517 );
buf ( n7681 , n7680 );
not ( n7682 , n7681 );
buf ( n7683 , n4518 );
not ( n7684 , n7683 );
not ( n7685 , n7684 );
or ( n7686 , n7682 , n7685 );
not ( n7687 , n7680 );
buf ( n7688 , n7683 );
nand ( n7689 , n7687 , n7688 );
nand ( n7690 , n7686 , n7689 );
buf ( n7691 , n4519 );
buf ( n7692 , n7691 );
and ( n7693 , n7690 , n7692 );
not ( n7694 , n7690 );
not ( n7695 , n7691 );
and ( n7696 , n7694 , n7695 );
nor ( n7697 , n7693 , n7696 );
buf ( n7698 , n6513 );
buf ( n7699 , n4520 );
nand ( n7700 , n7698 , n7699 );
buf ( n7701 , n4521 );
buf ( n7702 , n7701 );
and ( n7703 , n7700 , n7702 );
not ( n7704 , n7700 );
not ( n7705 , n7701 );
and ( n7706 , n7704 , n7705 );
nor ( n7707 , n7703 , n7706 );
xor ( n7708 , n7697 , n7707 );
buf ( n7709 , n7197 );
buf ( n7710 , n4522 );
nand ( n7711 , n7709 , n7710 );
buf ( n7712 , n4523 );
not ( n7713 , n7712 );
and ( n7714 , n7711 , n7713 );
not ( n7715 , n7711 );
buf ( n7716 , n7712 );
and ( n7717 , n7715 , n7716 );
nor ( n7718 , n7714 , n7717 );
xnor ( n7719 , n7708 , n7718 );
buf ( n7720 , n7719 );
xor ( n7721 , n7679 , n7720 );
buf ( n7722 , n4524 );
buf ( n7723 , n4525 );
nand ( n7724 , n6927 , n7723 );
buf ( n7725 , n4526 );
buf ( n7726 , n7725 );
and ( n7727 , n7724 , n7726 );
not ( n7728 , n7724 );
not ( n7729 , n7725 );
and ( n7730 , n7728 , n7729 );
nor ( n7731 , n7727 , n7730 );
xor ( n7732 , n7722 , n7731 );
buf ( n7733 , n4527 );
nand ( n7734 , n7067 , n7733 );
buf ( n7735 , n4528 );
not ( n7736 , n7735 );
and ( n7737 , n7734 , n7736 );
not ( n7738 , n7734 );
buf ( n7739 , n7735 );
and ( n7740 , n7738 , n7739 );
nor ( n7741 , n7737 , n7740 );
xnor ( n7742 , n7732 , n7741 );
not ( n7743 , n7742 );
buf ( n7744 , n4529 );
not ( n7745 , n7744 );
buf ( n7746 , n4530 );
buf ( n7747 , n7746 );
and ( n7748 , n7745 , n7747 );
not ( n7749 , n7745 );
not ( n7750 , n7746 );
and ( n7751 , n7749 , n7750 );
nor ( n7752 , n7748 , n7751 );
not ( n7753 , n7752 );
and ( n7754 , n7743 , n7753 );
and ( n7755 , n7742 , n7752 );
nor ( n7756 , n7754 , n7755 );
xnor ( n7757 , n7721 , n7756 );
not ( n7758 , n7757 );
buf ( n7759 , n4531 );
buf ( n7760 , n7759 );
not ( n7761 , n7760 );
buf ( n7762 , n4532 );
not ( n7763 , n7762 );
buf ( n7764 , n4533 );
buf ( n7765 , n7764 );
not ( n7766 , n7765 );
buf ( n7767 , n4534 );
not ( n7768 , n7767 );
not ( n7769 , n7768 );
or ( n7770 , n7766 , n7769 );
not ( n7771 , n7764 );
buf ( n7772 , n7767 );
nand ( n7773 , n7771 , n7772 );
nand ( n7774 , n7770 , n7773 );
not ( n7775 , n7774 );
xor ( n7776 , n7763 , n7775 );
buf ( n7777 , n4535 );
nand ( n7778 , n7698 , n7777 );
buf ( n7779 , n4536 );
buf ( n7780 , n7779 );
and ( n7781 , n7778 , n7780 );
not ( n7782 , n7778 );
not ( n7783 , n7779 );
and ( n7784 , n7782 , n7783 );
nor ( n7785 , n7781 , n7784 );
not ( n7786 , n7785 );
buf ( n7787 , n6576 );
buf ( n7788 , n4537 );
nand ( n7789 , n7787 , n7788 );
buf ( n7790 , n4538 );
not ( n7791 , n7790 );
and ( n7792 , n7789 , n7791 );
not ( n7793 , n7789 );
buf ( n7794 , n7790 );
and ( n7795 , n7793 , n7794 );
nor ( n7796 , n7792 , n7795 );
not ( n7797 , n7796 );
or ( n7798 , n7786 , n7797 );
or ( n7799 , n7785 , n7796 );
nand ( n7800 , n7798 , n7799 );
xnor ( n7801 , n7776 , n7800 );
not ( n7802 , n7801 );
not ( n7803 , n7802 );
not ( n7804 , n7803 );
or ( n7805 , n7761 , n7804 );
or ( n7806 , n7803 , n7760 );
nand ( n7807 , n7805 , n7806 );
buf ( n7808 , n4539 );
buf ( n7809 , n7808 );
buf ( n7810 , n4540 );
buf ( n7811 , n7810 );
not ( n7812 , n7811 );
buf ( n7813 , n4541 );
not ( n7814 , n7813 );
not ( n7815 , n7814 );
or ( n7816 , n7812 , n7815 );
not ( n7817 , n7810 );
buf ( n7818 , n7813 );
nand ( n7819 , n7817 , n7818 );
nand ( n7820 , n7816 , n7819 );
xor ( n7821 , n7809 , n7820 );
buf ( n7822 , n4542 );
buf ( n7823 , n4543 );
xor ( n7824 , n7822 , n7823 );
buf ( n7825 , n4544 );
nand ( n7826 , n7067 , n7825 );
xnor ( n7827 , n7824 , n7826 );
xnor ( n7828 , n7821 , n7827 );
not ( n7829 , n7828 );
not ( n7830 , n7829 );
and ( n7831 , n7807 , n7830 );
not ( n7832 , n7807 );
buf ( n7833 , n7828 );
not ( n7834 , n7833 );
and ( n7835 , n7832 , n7834 );
nor ( n7836 , n7831 , n7835 );
not ( n7837 , n7836 );
nand ( n7838 , n7758 , n7837 );
not ( n7839 , n7838 );
buf ( n7840 , n4545 );
buf ( n7841 , n7840 );
not ( n7842 , n7841 );
buf ( n7843 , n4546 );
not ( n7844 , n7843 );
not ( n7845 , n7844 );
or ( n7846 , n7842 , n7845 );
not ( n7847 , n7840 );
buf ( n7848 , n7843 );
nand ( n7849 , n7847 , n7848 );
nand ( n7850 , n7846 , n7849 );
buf ( n7851 , n4547 );
buf ( n7852 , n7851 );
and ( n7853 , n7850 , n7852 );
not ( n7854 , n7850 );
not ( n7855 , n7851 );
and ( n7856 , n7854 , n7855 );
nor ( n7857 , n7853 , n7856 );
buf ( n7858 , n4548 );
nand ( n7859 , n6633 , n7858 );
buf ( n7860 , n4549 );
not ( n7861 , n7860 );
and ( n7862 , n7859 , n7861 );
not ( n7863 , n7859 );
buf ( n7864 , n7860 );
and ( n7865 , n7863 , n7864 );
nor ( n7866 , n7862 , n7865 );
xor ( n7867 , n7857 , n7866 );
buf ( n7868 , n6827 );
buf ( n7869 , n4550 );
nand ( n7870 , n7868 , n7869 );
buf ( n7871 , n4551 );
not ( n7872 , n7871 );
and ( n7873 , n7870 , n7872 );
not ( n7874 , n7870 );
buf ( n7875 , n7871 );
and ( n7876 , n7874 , n7875 );
nor ( n7877 , n7873 , n7876 );
xnor ( n7878 , n7867 , n7877 );
buf ( n7879 , n7878 );
not ( n7880 , n7879 );
buf ( n7881 , n4552 );
buf ( n7882 , n7881 );
not ( n7883 , n7882 );
buf ( n7884 , n4553 );
buf ( n7885 , n7884 );
not ( n7886 , n7885 );
buf ( n7887 , n4554 );
not ( n7888 , n7887 );
not ( n7889 , n7888 );
or ( n7890 , n7886 , n7889 );
not ( n7891 , n7884 );
buf ( n7892 , n7887 );
nand ( n7893 , n7891 , n7892 );
nand ( n7894 , n7890 , n7893 );
buf ( n7895 , n4555 );
not ( n7896 , n7895 );
and ( n7897 , n7894 , n7896 );
not ( n7898 , n7894 );
buf ( n7899 , n7895 );
and ( n7900 , n7898 , n7899 );
nor ( n7901 , n7897 , n7900 );
buf ( n7902 , n4556 );
nand ( n7903 , n6828 , n7902 );
buf ( n7904 , n4557 );
not ( n7905 , n7904 );
and ( n7906 , n7903 , n7905 );
not ( n7907 , n7903 );
buf ( n7908 , n7904 );
and ( n7909 , n7907 , n7908 );
nor ( n7910 , n7906 , n7909 );
xor ( n7911 , n7901 , n7910 );
buf ( n7912 , n6645 );
buf ( n7913 , n4558 );
nand ( n7914 , n7912 , n7913 );
buf ( n7915 , n4559 );
not ( n7916 , n7915 );
and ( n7917 , n7914 , n7916 );
not ( n7918 , n7914 );
buf ( n7919 , n7915 );
and ( n7920 , n7918 , n7919 );
nor ( n7921 , n7917 , n7920 );
xnor ( n7922 , n7911 , n7921 );
not ( n7923 , n7922 );
not ( n7924 , n7923 );
or ( n7925 , n7883 , n7924 );
buf ( n7926 , n7922 );
not ( n7927 , n7926 );
or ( n7928 , n7927 , n7882 );
nand ( n7929 , n7925 , n7928 );
not ( n7930 , n7929 );
or ( n7931 , n7880 , n7930 );
or ( n7932 , n7929 , n7879 );
nand ( n7933 , n7931 , n7932 );
not ( n7934 , n7933 );
not ( n7935 , n7934 );
not ( n7936 , n7935 );
and ( n7937 , n7839 , n7936 );
and ( n7938 , n7838 , n7935 );
nor ( n7939 , n7937 , n7938 );
not ( n7940 , n7939 );
or ( n7941 , n7677 , n7940 );
not ( n7942 , n7939 );
nand ( n7943 , n7942 , n7675 );
nand ( n7944 , n7941 , n7943 );
not ( n7945 , n7944 );
and ( n7946 , n7425 , n7945 );
and ( n7947 , n7424 , n7944 );
nor ( n7948 , n7946 , n7947 );
not ( n7949 , n7948 );
or ( n7950 , n6751 , n7949 );
not ( n7951 , n6750 );
not ( n7952 , n7423 );
not ( n7953 , n7944 );
not ( n7954 , n7953 );
or ( n7955 , n7952 , n7954 );
nand ( n7956 , n7424 , n7944 );
nand ( n7957 , n7955 , n7956 );
nand ( n7958 , n7951 , n7957 );
nand ( n7959 , n7950 , n7958 );
buf ( n7960 , n4560 );
not ( n7961 , n7960 );
buf ( n7962 , n4561 );
buf ( n7963 , n7962 );
not ( n7964 , n7963 );
buf ( n7965 , n4562 );
not ( n7966 , n7965 );
not ( n7967 , n7966 );
or ( n7968 , n7964 , n7967 );
not ( n7969 , n7962 );
buf ( n7970 , n7965 );
nand ( n7971 , n7969 , n7970 );
nand ( n7972 , n7968 , n7971 );
xor ( n7973 , n7961 , n7972 );
buf ( n7974 , n4563 );
not ( n7975 , n7974 );
not ( n7976 , n7975 );
buf ( n7977 , n6576 );
buf ( n7978 , n4564 );
nand ( n7979 , n7977 , n7978 );
buf ( n7980 , n4565 );
not ( n7981 , n7980 );
and ( n7982 , n7979 , n7981 );
not ( n7983 , n7979 );
buf ( n7984 , n7980 );
and ( n7985 , n7983 , n7984 );
nor ( n7986 , n7982 , n7985 );
not ( n7987 , n7986 );
or ( n7988 , n7976 , n7987 );
or ( n7989 , n7986 , n7975 );
nand ( n7990 , n7988 , n7989 );
xnor ( n7991 , n7973 , n7990 );
buf ( n7992 , n7991 );
not ( n7993 , n7992 );
buf ( n7994 , n4566 );
nand ( n7995 , n6558 , n7994 );
buf ( n7996 , n4567 );
buf ( n7997 , n7996 );
and ( n7998 , n7995 , n7997 );
not ( n7999 , n7995 );
not ( n8000 , n7996 );
and ( n8001 , n7999 , n8000 );
nor ( n8002 , n7998 , n8001 );
buf ( n8003 , n8002 );
buf ( n8004 , n4568 );
buf ( n8005 , n8004 );
not ( n8006 , n8005 );
buf ( n8007 , n4569 );
not ( n8008 , n8007 );
not ( n8009 , n8008 );
or ( n8010 , n8006 , n8009 );
not ( n8011 , n8004 );
buf ( n8012 , n8007 );
nand ( n8013 , n8011 , n8012 );
nand ( n8014 , n8010 , n8013 );
buf ( n8015 , n4570 );
not ( n8016 , n8015 );
and ( n8017 , n8014 , n8016 );
not ( n8018 , n8014 );
buf ( n8019 , n8015 );
and ( n8020 , n8018 , n8019 );
nor ( n8021 , n8017 , n8020 );
buf ( n8022 , n4571 );
nand ( n8023 , n7698 , n8022 );
buf ( n8024 , n4572 );
buf ( n8025 , n8024 );
and ( n8026 , n8023 , n8025 );
not ( n8027 , n8023 );
not ( n8028 , n8024 );
and ( n8029 , n8027 , n8028 );
nor ( n8030 , n8026 , n8029 );
xor ( n8031 , n8021 , n8030 );
buf ( n8032 , n7698 );
buf ( n8033 , n4573 );
nand ( n8034 , n8032 , n8033 );
buf ( n8035 , n4574 );
not ( n8036 , n8035 );
and ( n8037 , n8034 , n8036 );
not ( n8038 , n8034 );
buf ( n8039 , n8035 );
and ( n8040 , n8038 , n8039 );
nor ( n8041 , n8037 , n8040 );
xnor ( n8042 , n8031 , n8041 );
and ( n8043 , n8003 , n8042 );
not ( n8044 , n8003 );
xor ( n8045 , n8021 , n8030 );
xnor ( n8046 , n8045 , n8041 );
not ( n8047 , n8046 );
and ( n8048 , n8044 , n8047 );
nor ( n8049 , n8043 , n8048 );
xor ( n8050 , n7993 , n8049 );
buf ( n8051 , n4575 );
not ( n8052 , n8051 );
not ( n8053 , n6688 );
buf ( n8054 , n4576 );
not ( n8055 , n8054 );
not ( n8056 , n8055 );
or ( n8057 , n8053 , n8056 );
buf ( n8058 , n8054 );
nand ( n8059 , n6735 , n8058 );
nand ( n8060 , n8057 , n8059 );
buf ( n8061 , n4577 );
not ( n8062 , n8061 );
and ( n8063 , n8060 , n8062 );
not ( n8064 , n8060 );
buf ( n8065 , n8061 );
and ( n8066 , n8064 , n8065 );
nor ( n8067 , n8063 , n8066 );
buf ( n8068 , n6500 );
buf ( n8069 , n8068 );
buf ( n8070 , n8069 );
buf ( n8071 , n4578 );
nand ( n8072 , n8070 , n8071 );
buf ( n8073 , n4579 );
buf ( n8074 , n8073 );
and ( n8075 , n8072 , n8074 );
not ( n8076 , n8072 );
not ( n8077 , n8073 );
and ( n8078 , n8076 , n8077 );
nor ( n8079 , n8075 , n8078 );
xor ( n8080 , n8067 , n8079 );
buf ( n8081 , n4580 );
nand ( n8082 , n7107 , n8081 );
buf ( n8083 , n4581 );
buf ( n8084 , n8083 );
and ( n8085 , n8082 , n8084 );
not ( n8086 , n8082 );
not ( n8087 , n8083 );
and ( n8088 , n8086 , n8087 );
nor ( n8089 , n8085 , n8088 );
not ( n8090 , n8089 );
xnor ( n8091 , n8080 , n8090 );
not ( n8092 , n8091 );
or ( n8093 , n8052 , n8092 );
or ( n8094 , n8091 , n8051 );
nand ( n8095 , n8093 , n8094 );
buf ( n8096 , n4582 );
buf ( n8097 , n8096 );
not ( n8098 , n8097 );
buf ( n8099 , n4583 );
not ( n8100 , n8099 );
not ( n8101 , n8100 );
or ( n8102 , n8098 , n8101 );
not ( n8103 , n8096 );
buf ( n8104 , n8099 );
nand ( n8105 , n8103 , n8104 );
nand ( n8106 , n8102 , n8105 );
buf ( n8107 , n4584 );
buf ( n8108 , n8107 );
and ( n8109 , n8106 , n8108 );
not ( n8110 , n8106 );
not ( n8111 , n8107 );
and ( n8112 , n8110 , n8111 );
nor ( n8113 , n8109 , n8112 );
buf ( n8114 , n4585 );
nand ( n8115 , n6577 , n8114 );
buf ( n8116 , n4586 );
buf ( n8117 , n8116 );
and ( n8118 , n8115 , n8117 );
not ( n8119 , n8115 );
not ( n8120 , n8116 );
and ( n8121 , n8119 , n8120 );
nor ( n8122 , n8118 , n8121 );
xor ( n8123 , n8113 , n8122 );
buf ( n8124 , n6645 );
buf ( n8125 , n8124 );
buf ( n8126 , n4587 );
nand ( n8127 , n8125 , n8126 );
buf ( n8128 , n4588 );
buf ( n8129 , n8128 );
and ( n8130 , n8127 , n8129 );
not ( n8131 , n8127 );
not ( n8132 , n8128 );
and ( n8133 , n8131 , n8132 );
nor ( n8134 , n8130 , n8133 );
xnor ( n8135 , n8123 , n8134 );
not ( n8136 , n8135 );
and ( n8137 , n8095 , n8136 );
not ( n8138 , n8095 );
not ( n8139 , n8135 );
not ( n8140 , n8139 );
and ( n8141 , n8138 , n8140 );
nor ( n8142 , n8137 , n8141 );
nand ( n8143 , n8050 , n8142 );
not ( n8144 , n8143 );
buf ( n8145 , n4589 );
buf ( n8146 , n8145 );
not ( n8147 , n8146 );
buf ( n8148 , n4590 );
buf ( n8149 , n8148 );
not ( n8150 , n8149 );
buf ( n8151 , n4591 );
not ( n8152 , n8151 );
not ( n8153 , n8152 );
or ( n8154 , n8150 , n8153 );
not ( n8155 , n8148 );
buf ( n8156 , n8151 );
nand ( n8157 , n8155 , n8156 );
nand ( n8158 , n8154 , n8157 );
buf ( n8159 , n4592 );
buf ( n8160 , n8159 );
and ( n8161 , n8158 , n8160 );
not ( n8162 , n8158 );
not ( n8163 , n8159 );
and ( n8164 , n8162 , n8163 );
nor ( n8165 , n8161 , n8164 );
buf ( n8166 , n4593 );
nand ( n8167 , n6828 , n8166 );
buf ( n8168 , n4594 );
buf ( n8169 , n8168 );
and ( n8170 , n8167 , n8169 );
not ( n8171 , n8167 );
not ( n8172 , n8168 );
and ( n8173 , n8171 , n8172 );
nor ( n8174 , n8170 , n8173 );
xor ( n8175 , n8165 , n8174 );
buf ( n8176 , n6827 );
buf ( n8177 , n4595 );
nand ( n8178 , n8176 , n8177 );
buf ( n8179 , n4596 );
buf ( n8180 , n8179 );
and ( n8181 , n8178 , n8180 );
not ( n8182 , n8178 );
not ( n8183 , n8179 );
and ( n8184 , n8182 , n8183 );
nor ( n8185 , n8181 , n8184 );
xnor ( n8186 , n8175 , n8185 );
not ( n8187 , n8186 );
or ( n8188 , n8147 , n8187 );
not ( n8189 , n8146 );
xor ( n8190 , n8165 , n8185 );
not ( n8191 , n8174 );
xnor ( n8192 , n8190 , n8191 );
nand ( n8193 , n8189 , n8192 );
nand ( n8194 , n8188 , n8193 );
buf ( n8195 , n4597 );
buf ( n8196 , n8195 );
not ( n8197 , n8196 );
buf ( n8198 , n4598 );
not ( n8199 , n8198 );
not ( n8200 , n8199 );
or ( n8201 , n8197 , n8200 );
not ( n8202 , n8195 );
buf ( n8203 , n8198 );
nand ( n8204 , n8202 , n8203 );
nand ( n8205 , n8201 , n8204 );
buf ( n8206 , n4599 );
not ( n8207 , n8206 );
and ( n8208 , n8205 , n8207 );
not ( n8209 , n8205 );
buf ( n8210 , n8206 );
and ( n8211 , n8209 , n8210 );
nor ( n8212 , n8208 , n8211 );
buf ( n8213 , n4600 );
nand ( n8214 , n7247 , n8213 );
buf ( n8215 , n4601 );
buf ( n8216 , n8215 );
and ( n8217 , n8214 , n8216 );
not ( n8218 , n8214 );
not ( n8219 , n8215 );
and ( n8220 , n8218 , n8219 );
nor ( n8221 , n8217 , n8220 );
xor ( n8222 , n8212 , n8221 );
buf ( n8223 , n7698 );
buf ( n8224 , n4602 );
nand ( n8225 , n8223 , n8224 );
buf ( n8226 , n4603 );
buf ( n8227 , n8226 );
and ( n8228 , n8225 , n8227 );
not ( n8229 , n8225 );
not ( n8230 , n8226 );
and ( n8231 , n8229 , n8230 );
nor ( n8232 , n8228 , n8231 );
xnor ( n8233 , n8222 , n8232 );
buf ( n8234 , n8233 );
and ( n8235 , n8194 , n8234 );
not ( n8236 , n8194 );
not ( n8237 , n8234 );
and ( n8238 , n8236 , n8237 );
nor ( n8239 , n8235 , n8238 );
not ( n8240 , n8239 );
and ( n8241 , n8144 , n8240 );
and ( n8242 , n8143 , n8239 );
nor ( n8243 , n8241 , n8242 );
not ( n8244 , n8243 );
buf ( n8245 , n4604 );
buf ( n8246 , n4605 );
not ( n8247 , n8246 );
buf ( n8248 , n4606 );
buf ( n8249 , n8248 );
and ( n8250 , n8247 , n8249 );
not ( n8251 , n8247 );
not ( n8252 , n8248 );
and ( n8253 , n8251 , n8252 );
nor ( n8254 , n8250 , n8253 );
xor ( n8255 , n8245 , n8254 );
buf ( n8256 , n4607 );
buf ( n8257 , n4608 );
buf ( n8258 , n8257 );
xor ( n8259 , n8256 , n8258 );
buf ( n8260 , n6770 );
buf ( n8261 , n4609 );
nand ( n8262 , n8260 , n8261 );
xnor ( n8263 , n8259 , n8262 );
xnor ( n8264 , n8255 , n8263 );
not ( n8265 , n8264 );
buf ( n8266 , n4610 );
nand ( n8267 , n7067 , n8266 );
buf ( n8268 , n4611 );
buf ( n8269 , n8268 );
and ( n8270 , n8267 , n8269 );
not ( n8271 , n8267 );
not ( n8272 , n8268 );
and ( n8273 , n8271 , n8272 );
nor ( n8274 , n8270 , n8273 );
buf ( n8275 , n8274 );
not ( n8276 , n8275 );
and ( n8277 , n8265 , n8276 );
and ( n8278 , n8264 , n8275 );
nor ( n8279 , n8277 , n8278 );
buf ( n8280 , n4612 );
nand ( n8281 , n7293 , n8280 );
buf ( n8282 , n4613 );
buf ( n8283 , n8282 );
and ( n8284 , n8281 , n8283 );
not ( n8285 , n8281 );
not ( n8286 , n8282 );
and ( n8287 , n8285 , n8286 );
nor ( n8288 , n8284 , n8287 );
xor ( n8289 , n7227 , n8288 );
buf ( n8290 , n4614 );
nand ( n8291 , n7258 , n8290 );
buf ( n8292 , n4615 );
not ( n8293 , n8292 );
and ( n8294 , n8291 , n8293 );
not ( n8295 , n8291 );
buf ( n8296 , n8292 );
and ( n8297 , n8295 , n8296 );
nor ( n8298 , n8294 , n8297 );
xnor ( n8299 , n8289 , n8298 );
not ( n8300 , n8299 );
buf ( n8301 , n4616 );
not ( n8302 , n8301 );
buf ( n8303 , n4617 );
buf ( n8304 , n8303 );
and ( n8305 , n8302 , n8304 );
not ( n8306 , n8302 );
not ( n8307 , n8303 );
and ( n8308 , n8306 , n8307 );
nor ( n8309 , n8305 , n8308 );
not ( n8310 , n8309 );
and ( n8311 , n8300 , n8310 );
and ( n8312 , n8299 , n8309 );
nor ( n8313 , n8311 , n8312 );
buf ( n8314 , n8313 );
and ( n8315 , n8279 , n8314 );
not ( n8316 , n8279 );
not ( n8317 , n8313 );
and ( n8318 , n8316 , n8317 );
nor ( n8319 , n8315 , n8318 );
not ( n8320 , n8319 );
not ( n8321 , n6792 );
buf ( n8322 , n6513 );
buf ( n8323 , n8322 );
buf ( n8324 , n4618 );
nand ( n8325 , n8323 , n8324 );
buf ( n8326 , n4619 );
not ( n8327 , n8326 );
and ( n8328 , n8325 , n8327 );
not ( n8329 , n8325 );
buf ( n8330 , n8326 );
and ( n8331 , n8329 , n8330 );
nor ( n8332 , n8328 , n8331 );
not ( n8333 , n8332 );
not ( n8334 , n6839 );
or ( n8335 , n8333 , n8334 );
not ( n8336 , n8332 );
nand ( n8337 , n8336 , n6844 );
nand ( n8338 , n8335 , n8337 );
not ( n8339 , n8338 );
or ( n8340 , n8321 , n8339 );
or ( n8341 , n8338 , n6792 );
nand ( n8342 , n8340 , n8341 );
nand ( n8343 , n8320 , n8342 );
buf ( n8344 , n4620 );
not ( n8345 , n8344 );
buf ( n8346 , n4621 );
buf ( n8347 , n8346 );
not ( n8348 , n8347 );
buf ( n8349 , n4622 );
not ( n8350 , n8349 );
not ( n8351 , n8350 );
or ( n8352 , n8348 , n8351 );
not ( n8353 , n8346 );
buf ( n8354 , n8349 );
nand ( n8355 , n8353 , n8354 );
nand ( n8356 , n8352 , n8355 );
buf ( n8357 , n4623 );
not ( n8358 , n8357 );
and ( n8359 , n8356 , n8358 );
not ( n8360 , n8356 );
buf ( n8361 , n8357 );
and ( n8362 , n8360 , n8361 );
nor ( n8363 , n8359 , n8362 );
buf ( n8364 , n6718 );
buf ( n8365 , n4624 );
nand ( n8366 , n8364 , n8365 );
buf ( n8367 , n4625 );
buf ( n8368 , n8367 );
and ( n8369 , n8366 , n8368 );
not ( n8370 , n8366 );
not ( n8371 , n8367 );
and ( n8372 , n8370 , n8371 );
nor ( n8373 , n8369 , n8372 );
xor ( n8374 , n8363 , n8373 );
buf ( n8375 , n8069 );
buf ( n8376 , n4626 );
nand ( n8377 , n8375 , n8376 );
buf ( n8378 , n4627 );
not ( n8379 , n8378 );
and ( n8380 , n8377 , n8379 );
not ( n8381 , n8377 );
buf ( n8382 , n8378 );
and ( n8383 , n8381 , n8382 );
nor ( n8384 , n8380 , n8383 );
xnor ( n8385 , n8374 , n8384 );
not ( n8386 , n8385 );
or ( n8387 , n8345 , n8386 );
not ( n8388 , n8344 );
not ( n8389 , n8373 );
not ( n8390 , n8384 );
or ( n8391 , n8389 , n8390 );
or ( n8392 , n8373 , n8384 );
nand ( n8393 , n8391 , n8392 );
not ( n8394 , n8363 );
and ( n8395 , n8393 , n8394 );
not ( n8396 , n8393 );
and ( n8397 , n8396 , n8363 );
nor ( n8398 , n8395 , n8397 );
nand ( n8399 , n8388 , n8398 );
nand ( n8400 , n8387 , n8399 );
buf ( n8401 , n4628 );
buf ( n8402 , n8401 );
not ( n8403 , n8402 );
buf ( n8404 , n4629 );
not ( n8405 , n8404 );
not ( n8406 , n8405 );
or ( n8407 , n8403 , n8406 );
not ( n8408 , n8401 );
buf ( n8409 , n8404 );
nand ( n8410 , n8408 , n8409 );
nand ( n8411 , n8407 , n8410 );
buf ( n8412 , n4630 );
not ( n8413 , n8412 );
and ( n8414 , n8411 , n8413 );
not ( n8415 , n8411 );
buf ( n8416 , n8412 );
and ( n8417 , n8415 , n8416 );
nor ( n8418 , n8414 , n8417 );
buf ( n8419 , n4631 );
nand ( n8420 , n7107 , n8419 );
buf ( n8421 , n4632 );
buf ( n8422 , n8421 );
and ( n8423 , n8420 , n8422 );
not ( n8424 , n8420 );
not ( n8425 , n8421 );
and ( n8426 , n8424 , n8425 );
nor ( n8427 , n8423 , n8426 );
xor ( n8428 , n8418 , n8427 );
buf ( n8429 , n4633 );
nand ( n8430 , n7912 , n8429 );
buf ( n8431 , n4634 );
buf ( n8432 , n8431 );
and ( n8433 , n8430 , n8432 );
not ( n8434 , n8430 );
not ( n8435 , n8431 );
and ( n8436 , n8434 , n8435 );
nor ( n8437 , n8433 , n8436 );
xor ( n8438 , n8428 , n8437 );
buf ( n8439 , n8438 );
not ( n8440 , n8439 );
and ( n8441 , n8400 , n8440 );
not ( n8442 , n8400 );
and ( n8443 , n8442 , n8439 );
nor ( n8444 , n8441 , n8443 );
not ( n8445 , n8444 );
and ( n8446 , n8343 , n8445 );
not ( n8447 , n8343 );
and ( n8448 , n8447 , n8444 );
nor ( n8449 , n8446 , n8448 );
not ( n8450 , n8449 );
or ( n8451 , n8244 , n8450 );
or ( n8452 , n8449 , n8243 );
nand ( n8453 , n8451 , n8452 );
buf ( n8454 , n6513 );
buf ( n8455 , n8454 );
buf ( n8456 , n4635 );
nand ( n8457 , n8455 , n8456 );
buf ( n8458 , n4636 );
buf ( n8459 , n8458 );
and ( n8460 , n8457 , n8459 );
not ( n8461 , n8457 );
not ( n8462 , n8458 );
and ( n8463 , n8461 , n8462 );
nor ( n8464 , n8460 , n8463 );
not ( n8465 , n8464 );
buf ( n8466 , n4637 );
buf ( n8467 , n8466 );
not ( n8468 , n8467 );
buf ( n8469 , n4638 );
not ( n8470 , n8469 );
not ( n8471 , n8470 );
or ( n8472 , n8468 , n8471 );
not ( n8473 , n8466 );
buf ( n8474 , n8469 );
nand ( n8475 , n8473 , n8474 );
nand ( n8476 , n8472 , n8475 );
buf ( n8477 , n4639 );
buf ( n8478 , n8477 );
and ( n8479 , n8476 , n8478 );
not ( n8480 , n8476 );
not ( n8481 , n8477 );
and ( n8482 , n8480 , n8481 );
nor ( n8483 , n8479 , n8482 );
buf ( n8484 , n4640 );
nand ( n8485 , n6916 , n8484 );
buf ( n8486 , n4641 );
buf ( n8487 , n8486 );
and ( n8488 , n8485 , n8487 );
not ( n8489 , n8485 );
not ( n8490 , n8486 );
and ( n8491 , n8489 , n8490 );
nor ( n8492 , n8488 , n8491 );
xor ( n8493 , n8483 , n8492 );
buf ( n8494 , n4642 );
nand ( n8495 , n6927 , n8494 );
buf ( n8496 , n4643 );
buf ( n8497 , n8496 );
and ( n8498 , n8495 , n8497 );
not ( n8499 , n8495 );
not ( n8500 , n8496 );
and ( n8501 , n8499 , n8500 );
nor ( n8502 , n8498 , n8501 );
not ( n8503 , n8502 );
xnor ( n8504 , n8493 , n8503 );
not ( n8505 , n8504 );
or ( n8506 , n8465 , n8505 );
or ( n8507 , n8504 , n8464 );
nand ( n8508 , n8506 , n8507 );
buf ( n8509 , n4644 );
buf ( n8510 , n8509 );
not ( n8511 , n8510 );
buf ( n8512 , n4645 );
not ( n8513 , n8512 );
not ( n8514 , n8513 );
or ( n8515 , n8511 , n8514 );
not ( n8516 , n8509 );
buf ( n8517 , n8512 );
nand ( n8518 , n8516 , n8517 );
nand ( n8519 , n8515 , n8518 );
buf ( n8520 , n4646 );
not ( n8521 , n8520 );
and ( n8522 , n8519 , n8521 );
not ( n8523 , n8519 );
buf ( n8524 , n8520 );
and ( n8525 , n8523 , n8524 );
nor ( n8526 , n8522 , n8525 );
buf ( n8527 , n4647 );
nand ( n8528 , n6770 , n8527 );
buf ( n8529 , n4648 );
buf ( n8530 , n8529 );
and ( n8531 , n8528 , n8530 );
not ( n8532 , n8528 );
not ( n8533 , n8529 );
and ( n8534 , n8532 , n8533 );
nor ( n8535 , n8531 , n8534 );
xor ( n8536 , n8526 , n8535 );
buf ( n8537 , n8068 );
buf ( n8538 , n4649 );
nand ( n8539 , n8537 , n8538 );
buf ( n8540 , n4650 );
not ( n8541 , n8540 );
and ( n8542 , n8539 , n8541 );
not ( n8543 , n8539 );
buf ( n8544 , n8540 );
and ( n8545 , n8543 , n8544 );
nor ( n8546 , n8542 , n8545 );
xnor ( n8547 , n8536 , n8546 );
buf ( n8548 , n8547 );
not ( n8549 , n8548 );
and ( n8550 , n8508 , n8549 );
not ( n8551 , n8508 );
and ( n8552 , n8551 , n8548 );
nor ( n8553 , n8550 , n8552 );
not ( n8554 , n8553 );
buf ( n8555 , n4651 );
nand ( n8556 , n6557 , n8555 );
buf ( n8557 , n4652 );
buf ( n8558 , n8557 );
and ( n8559 , n8556 , n8558 );
not ( n8560 , n8556 );
not ( n8561 , n8557 );
and ( n8562 , n8560 , n8561 );
nor ( n8563 , n8559 , n8562 );
buf ( n8564 , n8563 );
not ( n8565 , n8564 );
not ( n8566 , n7802 );
or ( n8567 , n8565 , n8566 );
buf ( n8568 , n7801 );
not ( n8569 , n8568 );
or ( n8570 , n8569 , n8564 );
nand ( n8571 , n8567 , n8570 );
not ( n8572 , n8571 );
not ( n8573 , n7833 );
and ( n8574 , n8572 , n8573 );
and ( n8575 , n8571 , n7830 );
nor ( n8576 , n8574 , n8575 );
not ( n8577 , n8576 );
nand ( n8578 , n8554 , n8577 );
buf ( n8579 , n4653 );
buf ( n8580 , n8579 );
not ( n8581 , n8580 );
buf ( n8582 , n4654 );
buf ( n8583 , n8582 );
not ( n8584 , n8583 );
not ( n8585 , n6954 );
or ( n8586 , n8584 , n8585 );
not ( n8587 , n8582 );
buf ( n8588 , n6953 );
nand ( n8589 , n8587 , n8588 );
nand ( n8590 , n8586 , n8589 );
buf ( n8591 , n4655 );
not ( n8592 , n8591 );
and ( n8593 , n8590 , n8592 );
not ( n8594 , n8590 );
buf ( n8595 , n8591 );
and ( n8596 , n8594 , n8595 );
nor ( n8597 , n8593 , n8596 );
buf ( n8598 , n4656 );
nand ( n8599 , n7107 , n8598 );
buf ( n8600 , n4657 );
buf ( n8601 , n8600 );
and ( n8602 , n8599 , n8601 );
not ( n8603 , n8599 );
not ( n8604 , n8600 );
and ( n8605 , n8603 , n8604 );
nor ( n8606 , n8602 , n8605 );
xor ( n8607 , n8597 , n8606 );
buf ( n8608 , n6815 );
buf ( n8609 , n4658 );
nand ( n8610 , n8608 , n8609 );
buf ( n8611 , n4659 );
not ( n8612 , n8611 );
and ( n8613 , n8610 , n8612 );
not ( n8614 , n8610 );
buf ( n8615 , n8611 );
and ( n8616 , n8614 , n8615 );
nor ( n8617 , n8613 , n8616 );
xnor ( n8618 , n8607 , n8617 );
buf ( n8619 , n8618 );
buf ( n8620 , n8619 );
not ( n8621 , n8620 );
or ( n8622 , n8581 , n8621 );
or ( n8623 , n8620 , n8580 );
nand ( n8624 , n8622 , n8623 );
buf ( n8625 , n4660 );
buf ( n8626 , n8625 );
not ( n8627 , n8626 );
buf ( n8628 , n4661 );
not ( n8629 , n8628 );
not ( n8630 , n8629 );
or ( n8631 , n8627 , n8630 );
not ( n8632 , n8625 );
buf ( n8633 , n8628 );
nand ( n8634 , n8632 , n8633 );
nand ( n8635 , n8631 , n8634 );
buf ( n8636 , n4662 );
not ( n8637 , n8636 );
and ( n8638 , n8635 , n8637 );
not ( n8639 , n8635 );
buf ( n8640 , n8636 );
and ( n8641 , n8639 , n8640 );
nor ( n8642 , n8638 , n8641 );
buf ( n8643 , n4663 );
nand ( n8644 , n6927 , n8643 );
buf ( n8645 , n4664 );
buf ( n8646 , n8645 );
and ( n8647 , n8644 , n8646 );
not ( n8648 , n8644 );
not ( n8649 , n8645 );
and ( n8650 , n8648 , n8649 );
nor ( n8651 , n8647 , n8650 );
xor ( n8652 , n8642 , n8651 );
buf ( n8653 , n4665 );
nand ( n8654 , n8455 , n8653 );
buf ( n8655 , n4666 );
buf ( n8656 , n8655 );
and ( n8657 , n8654 , n8656 );
not ( n8658 , n8654 );
not ( n8659 , n8655 );
and ( n8660 , n8658 , n8659 );
nor ( n8661 , n8657 , n8660 );
xnor ( n8662 , n8652 , n8661 );
not ( n8663 , n8662 );
xor ( n8664 , n8624 , n8663 );
and ( n8665 , n8578 , n8664 );
not ( n8666 , n8578 );
not ( n8667 , n8664 );
and ( n8668 , n8666 , n8667 );
nor ( n8669 , n8665 , n8668 );
and ( n8670 , n8453 , n8669 );
not ( n8671 , n8453 );
not ( n8672 , n8669 );
and ( n8673 , n8671 , n8672 );
nor ( n8674 , n8670 , n8673 );
buf ( n8675 , n6871 );
buf ( n8676 , n4667 );
nand ( n8677 , n8675 , n8676 );
buf ( n8678 , n4668 );
not ( n8679 , n8678 );
and ( n8680 , n8677 , n8679 );
not ( n8681 , n8677 );
buf ( n8682 , n8678 );
and ( n8683 , n8681 , n8682 );
nor ( n8684 , n8680 , n8683 );
buf ( n8685 , n4669 );
buf ( n8686 , n8685 );
not ( n8687 , n8686 );
buf ( n8688 , n4670 );
not ( n8689 , n8688 );
not ( n8690 , n8689 );
or ( n8691 , n8687 , n8690 );
not ( n8692 , n8685 );
buf ( n8693 , n8688 );
nand ( n8694 , n8692 , n8693 );
nand ( n8695 , n8691 , n8694 );
buf ( n8696 , n4671 );
buf ( n8697 , n8696 );
and ( n8698 , n8695 , n8697 );
not ( n8699 , n8695 );
not ( n8700 , n8696 );
and ( n8701 , n8699 , n8700 );
nor ( n8702 , n8698 , n8701 );
buf ( n8703 , n4672 );
nand ( n8704 , n8176 , n8703 );
buf ( n8705 , n4673 );
buf ( n8706 , n8705 );
and ( n8707 , n8704 , n8706 );
not ( n8708 , n8704 );
not ( n8709 , n8705 );
and ( n8710 , n8708 , n8709 );
nor ( n8711 , n8707 , n8710 );
xor ( n8712 , n8702 , n8711 );
buf ( n8713 , n4674 );
nand ( n8714 , n6558 , n8713 );
buf ( n8715 , n4675 );
not ( n8716 , n8715 );
and ( n8717 , n8714 , n8716 );
not ( n8718 , n8714 );
buf ( n8719 , n8715 );
and ( n8720 , n8718 , n8719 );
nor ( n8721 , n8717 , n8720 );
xnor ( n8722 , n8712 , n8721 );
buf ( n8723 , n8722 );
not ( n8724 , n8723 );
xor ( n8725 , n8684 , n8724 );
buf ( n8726 , n4676 );
not ( n8727 , n8726 );
buf ( n8728 , n4677 );
buf ( n8729 , n8728 );
and ( n8730 , n8727 , n8729 );
not ( n8731 , n8727 );
not ( n8732 , n8728 );
and ( n8733 , n8731 , n8732 );
nor ( n8734 , n8730 , n8733 );
not ( n8735 , n8734 );
buf ( n8736 , n4678 );
buf ( n8737 , n4679 );
nand ( n8738 , n7698 , n8737 );
buf ( n8739 , n4680 );
buf ( n8740 , n8739 );
and ( n8741 , n8738 , n8740 );
not ( n8742 , n8738 );
not ( n8743 , n8739 );
and ( n8744 , n8742 , n8743 );
nor ( n8745 , n8741 , n8744 );
xor ( n8746 , n8736 , n8745 );
buf ( n8747 , n4681 );
nand ( n8748 , n6828 , n8747 );
buf ( n8749 , n4682 );
not ( n8750 , n8749 );
and ( n8751 , n8748 , n8750 );
not ( n8752 , n8748 );
buf ( n8753 , n8749 );
and ( n8754 , n8752 , n8753 );
nor ( n8755 , n8751 , n8754 );
xnor ( n8756 , n8746 , n8755 );
not ( n8757 , n8756 );
or ( n8758 , n8735 , n8757 );
or ( n8759 , n8756 , n8734 );
nand ( n8760 , n8758 , n8759 );
buf ( n8761 , n8760 );
not ( n8762 , n8761 );
xnor ( n8763 , n8725 , n8762 );
buf ( n8764 , n4683 );
buf ( n8765 , n4684 );
buf ( n8766 , n8765 );
not ( n8767 , n8766 );
buf ( n8768 , n4685 );
not ( n8769 , n8768 );
not ( n8770 , n8769 );
or ( n8771 , n8767 , n8770 );
not ( n8772 , n8765 );
buf ( n8773 , n8768 );
nand ( n8774 , n8772 , n8773 );
nand ( n8775 , n8771 , n8774 );
xor ( n8776 , n8764 , n8775 );
buf ( n8777 , n4686 );
not ( n8778 , n8777 );
buf ( n8779 , n4687 );
xor ( n8780 , n8778 , n8779 );
buf ( n8781 , n6827 );
buf ( n8782 , n4688 );
nand ( n8783 , n8781 , n8782 );
xnor ( n8784 , n8780 , n8783 );
xnor ( n8785 , n8776 , n8784 );
buf ( n8786 , n8785 );
not ( n8787 , n8786 );
buf ( n8788 , n4689 );
nand ( n8789 , n7606 , n8788 );
buf ( n8790 , n4690 );
buf ( n8791 , n8790 );
and ( n8792 , n8789 , n8791 );
not ( n8793 , n8789 );
not ( n8794 , n8790 );
and ( n8795 , n8793 , n8794 );
nor ( n8796 , n8792 , n8795 );
buf ( n8797 , n8796 );
not ( n8798 , n8797 );
and ( n8799 , n8787 , n8798 );
and ( n8800 , n8786 , n8797 );
nor ( n8801 , n8799 , n8800 );
buf ( n8802 , n4691 );
buf ( n8803 , n8802 );
not ( n8804 , n8803 );
buf ( n8805 , n4692 );
not ( n8806 , n8805 );
not ( n8807 , n8806 );
or ( n8808 , n8804 , n8807 );
not ( n8809 , n8802 );
buf ( n8810 , n8805 );
nand ( n8811 , n8809 , n8810 );
nand ( n8812 , n8808 , n8811 );
not ( n8813 , n8812 );
buf ( n8814 , n4693 );
not ( n8815 , n8814 );
buf ( n8816 , n4694 );
nand ( n8817 , n6815 , n8816 );
not ( n8818 , n8817 );
buf ( n8819 , n4695 );
not ( n8820 , n8819 );
and ( n8821 , n8818 , n8820 );
nand ( n8822 , n8537 , n8816 );
and ( n8823 , n8822 , n8819 );
nor ( n8824 , n8821 , n8823 );
xor ( n8825 , n8815 , n8824 );
buf ( n8826 , n4696 );
nand ( n8827 , n7247 , n8826 );
not ( n8828 , n8827 );
buf ( n8829 , n4697 );
not ( n8830 , n8829 );
and ( n8831 , n8828 , n8830 );
nand ( n8832 , n8375 , n8826 );
and ( n8833 , n8832 , n8829 );
nor ( n8834 , n8831 , n8833 );
xnor ( n8835 , n8825 , n8834 );
not ( n8836 , n8835 );
not ( n8837 , n8836 );
or ( n8838 , n8813 , n8837 );
not ( n8839 , n8812 );
nand ( n8840 , n8839 , n8835 );
nand ( n8841 , n8838 , n8840 );
buf ( n8842 , n8841 );
not ( n8843 , n8842 );
and ( n8844 , n8801 , n8843 );
not ( n8845 , n8801 );
and ( n8846 , n8845 , n8842 );
nor ( n8847 , n8844 , n8846 );
nand ( n8848 , n8763 , n8847 );
buf ( n8849 , n4698 );
buf ( n8850 , n8849 );
not ( n8851 , n8850 );
buf ( n8852 , n4699 );
not ( n8853 , n8852 );
not ( n8854 , n8853 );
or ( n8855 , n8851 , n8854 );
not ( n8856 , n8849 );
buf ( n8857 , n8852 );
nand ( n8858 , n8856 , n8857 );
nand ( n8859 , n8855 , n8858 );
buf ( n8860 , n4700 );
buf ( n8861 , n8860 );
and ( n8862 , n8859 , n8861 );
not ( n8863 , n8859 );
not ( n8864 , n8860 );
and ( n8865 , n8863 , n8864 );
nor ( n8866 , n8862 , n8865 );
buf ( n8867 , n4701 );
nand ( n8868 , n7107 , n8867 );
buf ( n8869 , n4702 );
buf ( n8870 , n8869 );
and ( n8871 , n8868 , n8870 );
not ( n8872 , n8868 );
not ( n8873 , n8869 );
and ( n8874 , n8872 , n8873 );
nor ( n8875 , n8871 , n8874 );
xor ( n8876 , n8866 , n8875 );
buf ( n8877 , n4703 );
nand ( n8878 , n7355 , n8877 );
buf ( n8879 , n4704 );
buf ( n8880 , n8879 );
and ( n8881 , n8878 , n8880 );
not ( n8882 , n8878 );
not ( n8883 , n8879 );
and ( n8884 , n8882 , n8883 );
nor ( n8885 , n8881 , n8884 );
not ( n8886 , n8885 );
xnor ( n8887 , n8876 , n8886 );
not ( n8888 , n8887 );
buf ( n8889 , n4705 );
buf ( n8890 , n8889 );
nor ( n8891 , n8888 , n8890 );
not ( n8892 , n8891 );
nand ( n8893 , n8888 , n8890 );
nand ( n8894 , n8892 , n8893 );
buf ( n8895 , n4706 );
buf ( n8896 , n4707 );
not ( n8897 , n8896 );
buf ( n8898 , n4708 );
buf ( n8899 , n8898 );
and ( n8900 , n8897 , n8899 );
not ( n8901 , n8897 );
not ( n8902 , n8898 );
and ( n8903 , n8901 , n8902 );
nor ( n8904 , n8900 , n8903 );
xor ( n8905 , n8895 , n8904 );
buf ( n8906 , n4709 );
buf ( n8907 , n8906 );
buf ( n8908 , n4710 );
xor ( n8909 , n8907 , n8908 );
buf ( n8910 , n4711 );
nand ( n8911 , n6719 , n8910 );
xnor ( n8912 , n8909 , n8911 );
xnor ( n8913 , n8905 , n8912 );
and ( n8914 , n8894 , n8913 );
not ( n8915 , n8894 );
not ( n8916 , n8913 );
and ( n8917 , n8915 , n8916 );
nor ( n8918 , n8914 , n8917 );
not ( n8919 , n8918 );
and ( n8920 , n8848 , n8919 );
not ( n8921 , n8848 );
and ( n8922 , n8921 , n8918 );
nor ( n8923 , n8920 , n8922 );
not ( n8924 , n8923 );
buf ( n8925 , n4712 );
nand ( n8926 , n7787 , n8925 );
buf ( n8927 , n4713 );
buf ( n8928 , n8927 );
and ( n8929 , n8926 , n8928 );
not ( n8930 , n8926 );
not ( n8931 , n8927 );
and ( n8932 , n8930 , n8931 );
nor ( n8933 , n8929 , n8932 );
buf ( n8934 , n8933 );
not ( n8935 , n8934 );
buf ( n8936 , n4714 );
buf ( n8937 , n8936 );
not ( n8938 , n8937 );
buf ( n8939 , n4715 );
not ( n8940 , n8939 );
not ( n8941 , n8940 );
or ( n8942 , n8938 , n8941 );
not ( n8943 , n8936 );
buf ( n8944 , n8939 );
nand ( n8945 , n8943 , n8944 );
nand ( n8946 , n8942 , n8945 );
buf ( n8947 , n4716 );
buf ( n8948 , n8947 );
and ( n8949 , n8946 , n8948 );
not ( n8950 , n8946 );
not ( n8951 , n8947 );
and ( n8952 , n8950 , n8951 );
nor ( n8953 , n8949 , n8952 );
buf ( n8954 , n8322 );
buf ( n8955 , n4717 );
nand ( n8956 , n8954 , n8955 );
buf ( n8957 , n4718 );
buf ( n8958 , n8957 );
and ( n8959 , n8956 , n8958 );
not ( n8960 , n8956 );
not ( n8961 , n8957 );
and ( n8962 , n8960 , n8961 );
nor ( n8963 , n8959 , n8962 );
buf ( n8964 , n8963 );
xor ( n8965 , n8953 , n8964 );
buf ( n8966 , n6827 );
buf ( n8967 , n4719 );
nand ( n8968 , n8966 , n8967 );
buf ( n8969 , n4720 );
not ( n8970 , n8969 );
and ( n8971 , n8968 , n8970 );
not ( n8972 , n8968 );
buf ( n8973 , n8969 );
and ( n8974 , n8972 , n8973 );
nor ( n8975 , n8971 , n8974 );
buf ( n8976 , n8975 );
xnor ( n8977 , n8965 , n8976 );
buf ( n8978 , n8977 );
not ( n8979 , n8978 );
or ( n8980 , n8935 , n8979 );
or ( n8981 , n8978 , n8934 );
nand ( n8982 , n8980 , n8981 );
xor ( n8983 , n7518 , n7537 );
not ( n8984 , n7527 );
xnor ( n8985 , n8983 , n8984 );
buf ( n8986 , n8985 );
and ( n8987 , n8982 , n8986 );
not ( n8988 , n8982 );
and ( n8989 , n8988 , n7540 );
nor ( n8990 , n8987 , n8989 );
not ( n8991 , n8298 );
buf ( n8992 , n7270 );
not ( n8993 , n8992 );
or ( n8994 , n8991 , n8993 );
not ( n8995 , n8298 );
not ( n8996 , n8992 );
nand ( n8997 , n8995 , n8996 );
nand ( n8998 , n8994 , n8997 );
and ( n8999 , n8998 , n7315 );
not ( n9000 , n8998 );
not ( n9001 , n7315 );
and ( n9002 , n9000 , n9001 );
nor ( n9003 , n8999 , n9002 );
and ( n9004 , n8990 , n9003 );
buf ( n9005 , n4721 );
buf ( n9006 , n9005 );
buf ( n9007 , n4722 );
buf ( n9008 , n9007 );
not ( n9009 , n9008 );
buf ( n9010 , n4723 );
not ( n9011 , n9010 );
not ( n9012 , n9011 );
or ( n9013 , n9009 , n9012 );
not ( n9014 , n9007 );
buf ( n9015 , n9010 );
nand ( n9016 , n9014 , n9015 );
nand ( n9017 , n9013 , n9016 );
buf ( n9018 , n4724 );
buf ( n9019 , n9018 );
and ( n9020 , n9017 , n9019 );
not ( n9021 , n9017 );
not ( n9022 , n9018 );
and ( n9023 , n9021 , n9022 );
nor ( n9024 , n9020 , n9023 );
buf ( n9025 , n4725 );
nand ( n9026 , n8124 , n9025 );
buf ( n9027 , n4726 );
buf ( n9028 , n9027 );
and ( n9029 , n9026 , n9028 );
not ( n9030 , n9026 );
not ( n9031 , n9027 );
and ( n9032 , n9030 , n9031 );
nor ( n9033 , n9029 , n9032 );
xor ( n9034 , n9024 , n9033 );
buf ( n9035 , n4727 );
nand ( n9036 , n7202 , n9035 );
buf ( n9037 , n4728 );
not ( n9038 , n9037 );
and ( n9039 , n9036 , n9038 );
not ( n9040 , n9036 );
buf ( n9041 , n9037 );
and ( n9042 , n9040 , n9041 );
nor ( n9043 , n9039 , n9042 );
buf ( n9044 , n9043 );
xnor ( n9045 , n9034 , n9044 );
buf ( n9046 , n9045 );
xor ( n9047 , n9006 , n9046 );
buf ( n9048 , n4729 );
not ( n9049 , n9048 );
buf ( n9050 , n4730 );
not ( n9051 , n9050 );
buf ( n9052 , n4731 );
buf ( n9053 , n9052 );
nand ( n9054 , n9051 , n9053 );
not ( n9055 , n9052 );
buf ( n9056 , n9050 );
nand ( n9057 , n9055 , n9056 );
and ( n9058 , n9054 , n9057 );
xor ( n9059 , n9049 , n9058 );
buf ( n9060 , n4732 );
buf ( n9061 , n4733 );
xor ( n9062 , n9060 , n9061 );
buf ( n9063 , n4734 );
nand ( n9064 , n7569 , n9063 );
xnor ( n9065 , n9062 , n9064 );
xnor ( n9066 , n9059 , n9065 );
buf ( n9067 , n9066 );
xnor ( n9068 , n9047 , n9067 );
not ( n9069 , n9068 );
and ( n9070 , n9004 , n9069 );
not ( n9071 , n9004 );
and ( n9072 , n9071 , n9068 );
nor ( n9073 , n9070 , n9072 );
not ( n9074 , n9073 );
and ( n9075 , n8924 , n9074 );
and ( n9076 , n8923 , n9073 );
nor ( n9077 , n9075 , n9076 );
and ( n9078 , n8674 , n9077 );
not ( n9079 , n8674 );
not ( n9080 , n9077 );
and ( n9081 , n9079 , n9080 );
nor ( n9082 , n9078 , n9081 );
buf ( n9083 , n9082 );
and ( n9084 , n7959 , n9083 );
not ( n9085 , n7959 );
not ( n9086 , n9077 );
not ( n9087 , n8674 );
or ( n9088 , n9086 , n9087 );
not ( n9089 , n8674 );
nand ( n9090 , n9089 , n9080 );
nand ( n9091 , n9088 , n9090 );
buf ( n9092 , n9091 );
and ( n9093 , n9085 , n9092 );
nor ( n9094 , n9084 , n9093 );
not ( n9095 , n9094 );
buf ( n9096 , n4735 );
buf ( n9097 , n9096 );
buf ( n9098 , n4736 );
buf ( n9099 , n9098 );
not ( n9100 , n9099 );
buf ( n9101 , n4737 );
not ( n9102 , n9101 );
not ( n9103 , n9102 );
or ( n9104 , n9100 , n9103 );
not ( n9105 , n9098 );
buf ( n9106 , n9101 );
nand ( n9107 , n9105 , n9106 );
nand ( n9108 , n9104 , n9107 );
buf ( n9109 , n4738 );
not ( n9110 , n9109 );
and ( n9111 , n9108 , n9110 );
not ( n9112 , n9108 );
buf ( n9113 , n9109 );
and ( n9114 , n9112 , n9113 );
nor ( n9115 , n9111 , n9114 );
buf ( n9116 , n4739 );
nand ( n9117 , n7698 , n9116 );
buf ( n9118 , n4740 );
buf ( n9119 , n9118 );
and ( n9120 , n9117 , n9119 );
not ( n9121 , n9117 );
not ( n9122 , n9118 );
and ( n9123 , n9121 , n9122 );
nor ( n9124 , n9120 , n9123 );
xor ( n9125 , n9115 , n9124 );
buf ( n9126 , n4741 );
nand ( n9127 , n8781 , n9126 );
buf ( n9128 , n4742 );
buf ( n9129 , n9128 );
and ( n9130 , n9127 , n9129 );
not ( n9131 , n9127 );
not ( n9132 , n9128 );
and ( n9133 , n9131 , n9132 );
nor ( n9134 , n9130 , n9133 );
xnor ( n9135 , n9125 , n9134 );
buf ( n9136 , n9135 );
not ( n9137 , n9136 );
and ( n9138 , n9097 , n9137 );
not ( n9139 , n9097 );
and ( n9140 , n9139 , n9136 );
or ( n9141 , n9138 , n9140 );
buf ( n9142 , n4743 );
buf ( n9143 , n9142 );
not ( n9144 , n9143 );
buf ( n9145 , n4744 );
not ( n9146 , n9145 );
not ( n9147 , n9146 );
or ( n9148 , n9144 , n9147 );
not ( n9149 , n9142 );
buf ( n9150 , n9145 );
nand ( n9151 , n9149 , n9150 );
nand ( n9152 , n9148 , n9151 );
buf ( n9153 , n4745 );
not ( n9154 , n9153 );
and ( n9155 , n9152 , n9154 );
not ( n9156 , n9152 );
buf ( n9157 , n9153 );
and ( n9158 , n9156 , n9157 );
nor ( n9159 , n9155 , n9158 );
buf ( n9160 , n6556 );
buf ( n9161 , n4746 );
nand ( n9162 , n9160 , n9161 );
buf ( n9163 , n4747 );
buf ( n9164 , n9163 );
and ( n9165 , n9162 , n9164 );
not ( n9166 , n9162 );
not ( n9167 , n9163 );
and ( n9168 , n9166 , n9167 );
nor ( n9169 , n9165 , n9168 );
xor ( n9170 , n9159 , n9169 );
buf ( n9171 , n4748 );
nand ( n9172 , n7355 , n9171 );
buf ( n9173 , n4749 );
buf ( n9174 , n9173 );
and ( n9175 , n9172 , n9174 );
not ( n9176 , n9172 );
not ( n9177 , n9173 );
and ( n9178 , n9176 , n9177 );
nor ( n9179 , n9175 , n9178 );
xor ( n9180 , n9170 , n9179 );
buf ( n9181 , n9180 );
and ( n9182 , n9141 , n9181 );
not ( n9183 , n9141 );
not ( n9184 , n9181 );
and ( n9185 , n9183 , n9184 );
nor ( n9186 , n9182 , n9185 );
not ( n9187 , n9186 );
buf ( n9188 , n4750 );
nand ( n9189 , n8032 , n9188 );
buf ( n9190 , n4751 );
buf ( n9191 , n9190 );
and ( n9192 , n9189 , n9191 );
not ( n9193 , n9189 );
not ( n9194 , n9190 );
and ( n9195 , n9193 , n9194 );
nor ( n9196 , n9192 , n9195 );
not ( n9197 , n9196 );
buf ( n9198 , n4752 );
buf ( n9199 , n9198 );
not ( n9200 , n9199 );
buf ( n9201 , n4753 );
not ( n9202 , n9201 );
not ( n9203 , n9202 );
or ( n9204 , n9200 , n9203 );
not ( n9205 , n9198 );
buf ( n9206 , n9201 );
nand ( n9207 , n9205 , n9206 );
nand ( n9208 , n9204 , n9207 );
buf ( n9209 , n4754 );
buf ( n9210 , n9209 );
and ( n9211 , n9208 , n9210 );
not ( n9212 , n9208 );
not ( n9213 , n9209 );
and ( n9214 , n9212 , n9213 );
nor ( n9215 , n9211 , n9214 );
buf ( n9216 , n4755 );
nand ( n9217 , n6604 , n9216 );
buf ( n9218 , n4756 );
not ( n9219 , n9218 );
and ( n9220 , n9217 , n9219 );
not ( n9221 , n9217 );
buf ( n9222 , n9218 );
and ( n9223 , n9221 , n9222 );
nor ( n9224 , n9220 , n9223 );
xor ( n9225 , n9215 , n9224 );
buf ( n9226 , n4757 );
nand ( n9227 , n6647 , n9226 );
buf ( n9228 , n4758 );
not ( n9229 , n9228 );
and ( n9230 , n9227 , n9229 );
not ( n9231 , n9227 );
buf ( n9232 , n9228 );
and ( n9233 , n9231 , n9232 );
nor ( n9234 , n9230 , n9233 );
xnor ( n9235 , n9225 , n9234 );
not ( n9236 , n9235 );
not ( n9237 , n9236 );
or ( n9238 , n9197 , n9237 );
or ( n9239 , n9236 , n9196 );
nand ( n9240 , n9238 , n9239 );
not ( n9241 , n9240 );
not ( n9242 , n9241 );
buf ( n9243 , n4759 );
not ( n9244 , n9243 );
buf ( n9245 , n4760 );
buf ( n9246 , n9245 );
not ( n9247 , n9246 );
buf ( n9248 , n4761 );
not ( n9249 , n9248 );
not ( n9250 , n9249 );
or ( n9251 , n9247 , n9250 );
not ( n9252 , n9245 );
buf ( n9253 , n9248 );
nand ( n9254 , n9252 , n9253 );
nand ( n9255 , n9251 , n9254 );
xor ( n9256 , n9244 , n9255 );
not ( n9257 , n8051 );
buf ( n9258 , n4762 );
nand ( n9259 , n6577 , n9258 );
buf ( n9260 , n4763 );
buf ( n9261 , n9260 );
and ( n9262 , n9259 , n9261 );
not ( n9263 , n9259 );
not ( n9264 , n9260 );
and ( n9265 , n9263 , n9264 );
nor ( n9266 , n9262 , n9265 );
not ( n9267 , n9266 );
or ( n9268 , n9257 , n9267 );
or ( n9269 , n9266 , n8051 );
nand ( n9270 , n9268 , n9269 );
xnor ( n9271 , n9256 , n9270 );
buf ( n9272 , n9271 );
not ( n9273 , n9272 );
or ( n9274 , n9242 , n9273 );
buf ( n9275 , n9243 );
xor ( n9276 , n9275 , n9255 );
xnor ( n9277 , n9276 , n9270 );
nand ( n9278 , n9277 , n9240 );
nand ( n9279 , n9274 , n9278 );
buf ( n9280 , n4764 );
not ( n9281 , n9280 );
buf ( n9282 , n4765 );
buf ( n9283 , n9282 );
not ( n9284 , n9283 );
buf ( n9285 , n4766 );
not ( n9286 , n9285 );
not ( n9287 , n9286 );
or ( n9288 , n9284 , n9287 );
not ( n9289 , n9282 );
buf ( n9290 , n9285 );
nand ( n9291 , n9289 , n9290 );
nand ( n9292 , n9288 , n9291 );
buf ( n9293 , n4767 );
not ( n9294 , n9293 );
and ( n9295 , n9292 , n9294 );
not ( n9296 , n9292 );
buf ( n9297 , n9293 );
and ( n9298 , n9296 , n9297 );
nor ( n9299 , n9295 , n9298 );
buf ( n9300 , n4768 );
nand ( n9301 , n6927 , n9300 );
buf ( n9302 , n4769 );
buf ( n9303 , n9302 );
and ( n9304 , n9301 , n9303 );
not ( n9305 , n9301 );
not ( n9306 , n9302 );
and ( n9307 , n9305 , n9306 );
nor ( n9308 , n9304 , n9307 );
xor ( n9309 , n9299 , n9308 );
buf ( n9310 , n7013 );
buf ( n9311 , n4770 );
nand ( n9312 , n9310 , n9311 );
buf ( n9313 , n4771 );
not ( n9314 , n9313 );
and ( n9315 , n9312 , n9314 );
not ( n9316 , n9312 );
buf ( n9317 , n9313 );
and ( n9318 , n9316 , n9317 );
nor ( n9319 , n9315 , n9318 );
xnor ( n9320 , n9309 , n9319 );
not ( n9321 , n9320 );
not ( n9322 , n9321 );
not ( n9323 , n9322 );
or ( n9324 , n9281 , n9323 );
not ( n9325 , n9280 );
nand ( n9326 , n9325 , n9321 );
nand ( n9327 , n9324 , n9326 );
buf ( n9328 , n4772 );
nand ( n9329 , n8364 , n9328 );
buf ( n9330 , n4773 );
buf ( n9331 , n9330 );
and ( n9332 , n9329 , n9331 );
not ( n9333 , n9329 );
not ( n9334 , n9330 );
and ( n9335 , n9333 , n9334 );
nor ( n9336 , n9332 , n9335 );
not ( n9337 , n9336 );
buf ( n9338 , n4774 );
nand ( n9339 , n6770 , n9338 );
buf ( n9340 , n4775 );
not ( n9341 , n9340 );
and ( n9342 , n9339 , n9341 );
not ( n9343 , n9339 );
buf ( n9344 , n9340 );
and ( n9345 , n9343 , n9344 );
nor ( n9346 , n9342 , n9345 );
not ( n9347 , n9346 );
or ( n9348 , n9337 , n9347 );
or ( n9349 , n9336 , n9346 );
nand ( n9350 , n9348 , n9349 );
buf ( n9351 , n4776 );
buf ( n9352 , n9351 );
not ( n9353 , n9352 );
buf ( n9354 , n4777 );
not ( n9355 , n9354 );
not ( n9356 , n9355 );
or ( n9357 , n9353 , n9356 );
not ( n9358 , n9351 );
buf ( n9359 , n9354 );
nand ( n9360 , n9358 , n9359 );
nand ( n9361 , n9357 , n9360 );
buf ( n9362 , n4778 );
not ( n9363 , n9362 );
and ( n9364 , n9361 , n9363 );
not ( n9365 , n9361 );
buf ( n9366 , n9362 );
and ( n9367 , n9365 , n9366 );
nor ( n9368 , n9364 , n9367 );
not ( n9369 , n9368 );
and ( n9370 , n9350 , n9369 );
not ( n9371 , n9350 );
and ( n9372 , n9371 , n9368 );
nor ( n9373 , n9370 , n9372 );
not ( n9374 , n9373 );
and ( n9375 , n9327 , n9374 );
not ( n9376 , n9327 );
not ( n9377 , n9374 );
and ( n9378 , n9376 , n9377 );
nor ( n9379 , n9375 , n9378 );
nor ( n9380 , n9279 , n9379 );
not ( n9381 , n9380 );
or ( n9382 , n9187 , n9381 );
or ( n9383 , n9380 , n9186 );
nand ( n9384 , n9382 , n9383 );
not ( n9385 , n9384 );
nand ( n9386 , n9186 , n9279 );
not ( n9387 , n9386 );
buf ( n9388 , n4779 );
buf ( n9389 , n9388 );
not ( n9390 , n9389 );
buf ( n9391 , n4780 );
buf ( n9392 , n9391 );
not ( n9393 , n9392 );
buf ( n9394 , n4781 );
not ( n9395 , n9394 );
not ( n9396 , n9395 );
or ( n9397 , n9393 , n9396 );
not ( n9398 , n9391 );
buf ( n9399 , n9394 );
nand ( n9400 , n9398 , n9399 );
nand ( n9401 , n9397 , n9400 );
buf ( n9402 , n4782 );
not ( n9403 , n9402 );
and ( n9404 , n9401 , n9403 );
not ( n9405 , n9401 );
buf ( n9406 , n9402 );
and ( n9407 , n9405 , n9406 );
nor ( n9408 , n9404 , n9407 );
xor ( n9409 , n9408 , n8796 );
buf ( n9410 , n4783 );
nand ( n9411 , n6605 , n9410 );
buf ( n9412 , n4784 );
buf ( n9413 , n9412 );
and ( n9414 , n9411 , n9413 );
not ( n9415 , n9411 );
not ( n9416 , n9412 );
and ( n9417 , n9415 , n9416 );
nor ( n9418 , n9414 , n9417 );
xor ( n9419 , n9409 , n9418 );
not ( n9420 , n9419 );
or ( n9421 , n9390 , n9420 );
or ( n9422 , n9419 , n9389 );
nand ( n9423 , n9421 , n9422 );
buf ( n9424 , n4785 );
buf ( n9425 , n9424 );
not ( n9426 , n9425 );
buf ( n9427 , n4786 );
not ( n9428 , n9427 );
not ( n9429 , n9428 );
or ( n9430 , n9426 , n9429 );
not ( n9431 , n9424 );
buf ( n9432 , n9427 );
nand ( n9433 , n9431 , n9432 );
nand ( n9434 , n9430 , n9433 );
buf ( n9435 , n4787 );
not ( n9436 , n9435 );
and ( n9437 , n9434 , n9436 );
not ( n9438 , n9434 );
buf ( n9439 , n9435 );
and ( n9440 , n9438 , n9439 );
nor ( n9441 , n9437 , n9440 );
buf ( n9442 , n4788 );
nand ( n9443 , n8124 , n9442 );
buf ( n9444 , n4789 );
not ( n9445 , n9444 );
and ( n9446 , n9443 , n9445 );
not ( n9447 , n9443 );
buf ( n9448 , n9444 );
and ( n9449 , n9447 , n9448 );
nor ( n9450 , n9446 , n9449 );
xor ( n9451 , n9441 , n9450 );
buf ( n9452 , n4790 );
nand ( n9453 , n6816 , n9452 );
buf ( n9454 , n4791 );
not ( n9455 , n9454 );
and ( n9456 , n9453 , n9455 );
not ( n9457 , n9453 );
buf ( n9458 , n9454 );
and ( n9459 , n9457 , n9458 );
nor ( n9460 , n9456 , n9459 );
xnor ( n9461 , n9451 , n9460 );
buf ( n9462 , n9461 );
and ( n9463 , n9423 , n9462 );
not ( n9464 , n9423 );
not ( n9465 , n9462 );
and ( n9466 , n9464 , n9465 );
nor ( n9467 , n9463 , n9466 );
not ( n9468 , n9467 );
and ( n9469 , n9387 , n9468 );
buf ( n9470 , n9279 );
nand ( n9471 , n9186 , n9470 );
and ( n9472 , n9471 , n9467 );
nor ( n9473 , n9469 , n9472 );
not ( n9474 , n9473 );
buf ( n9475 , n4792 );
buf ( n9476 , n9475 );
not ( n9477 , n9476 );
buf ( n9478 , n4793 );
not ( n9479 , n9478 );
not ( n9480 , n9479 );
or ( n9481 , n9477 , n9480 );
not ( n9482 , n9475 );
buf ( n9483 , n9478 );
nand ( n9484 , n9482 , n9483 );
nand ( n9485 , n9481 , n9484 );
buf ( n9486 , n4794 );
buf ( n9487 , n9486 );
and ( n9488 , n9485 , n9487 );
not ( n9489 , n9485 );
not ( n9490 , n9486 );
and ( n9491 , n9489 , n9490 );
nor ( n9492 , n9488 , n9491 );
buf ( n9493 , n4795 );
nand ( n9494 , n7563 , n9493 );
buf ( n9495 , n4796 );
buf ( n9496 , n9495 );
and ( n9497 , n9494 , n9496 );
not ( n9498 , n9494 );
not ( n9499 , n9495 );
and ( n9500 , n9498 , n9499 );
nor ( n9501 , n9497 , n9500 );
xor ( n9502 , n9492 , n9501 );
buf ( n9503 , n4797 );
nand ( n9504 , n8223 , n9503 );
buf ( n9505 , n4798 );
not ( n9506 , n9505 );
and ( n9507 , n9504 , n9506 );
not ( n9508 , n9504 );
buf ( n9509 , n9505 );
and ( n9510 , n9508 , n9509 );
nor ( n9511 , n9507 , n9510 );
xnor ( n9512 , n9502 , n9511 );
not ( n9513 , n9512 );
not ( n9514 , n9513 );
buf ( n9515 , n4799 );
not ( n9516 , n9515 );
and ( n9517 , n9514 , n9516 );
buf ( n9518 , n9512 );
not ( n9519 , n9518 );
and ( n9520 , n9519 , n9515 );
nor ( n9521 , n9517 , n9520 );
buf ( n9522 , n4800 );
buf ( n9523 , n9522 );
not ( n9524 , n9523 );
buf ( n9525 , n4801 );
not ( n9526 , n9525 );
not ( n9527 , n9526 );
or ( n9528 , n9524 , n9527 );
not ( n9529 , n9522 );
buf ( n9530 , n9525 );
nand ( n9531 , n9529 , n9530 );
nand ( n9532 , n9528 , n9531 );
buf ( n9533 , n4802 );
not ( n9534 , n9533 );
and ( n9535 , n9532 , n9534 );
not ( n9536 , n9532 );
buf ( n9537 , n9533 );
and ( n9538 , n9536 , n9537 );
nor ( n9539 , n9535 , n9538 );
not ( n9540 , n9539 );
buf ( n9541 , n4803 );
nand ( n9542 , n6604 , n9541 );
buf ( n9543 , n4804 );
xor ( n9544 , n9542 , n9543 );
xor ( n9545 , n9540 , n9544 );
buf ( n9546 , n4805 );
nand ( n9547 , n7569 , n9546 );
buf ( n9548 , n4806 );
buf ( n9549 , n9548 );
and ( n9550 , n9547 , n9549 );
not ( n9551 , n9547 );
not ( n9552 , n9548 );
and ( n9553 , n9551 , n9552 );
nor ( n9554 , n9550 , n9553 );
xnor ( n9555 , n9545 , n9554 );
not ( n9556 , n9555 );
not ( n9557 , n9556 );
and ( n9558 , n9521 , n9557 );
not ( n9559 , n9521 );
xor ( n9560 , n9539 , n9544 );
xnor ( n9561 , n9560 , n9554 );
buf ( n9562 , n9561 );
and ( n9563 , n9559 , n9562 );
nor ( n9564 , n9558 , n9563 );
not ( n9565 , n9564 );
buf ( n9566 , n4807 );
nand ( n9567 , n7868 , n9566 );
buf ( n9568 , n4808 );
not ( n9569 , n9568 );
and ( n9570 , n9567 , n9569 );
not ( n9571 , n9567 );
buf ( n9572 , n9568 );
and ( n9573 , n9571 , n9572 );
nor ( n9574 , n9570 , n9573 );
buf ( n9575 , n9574 );
not ( n9576 , n9575 );
buf ( n9577 , n4809 );
buf ( n9578 , n4810 );
buf ( n9579 , n9578 );
not ( n9580 , n9579 );
buf ( n9581 , n4811 );
not ( n9582 , n9581 );
not ( n9583 , n9582 );
or ( n9584 , n9580 , n9583 );
not ( n9585 , n9578 );
buf ( n9586 , n9581 );
nand ( n9587 , n9585 , n9586 );
nand ( n9588 , n9584 , n9587 );
xor ( n9589 , n9577 , n9588 );
buf ( n9590 , n4812 );
buf ( n9591 , n4813 );
not ( n9592 , n9591 );
xor ( n9593 , n9590 , n9592 );
buf ( n9594 , n4814 );
nand ( n9595 , n8323 , n9594 );
xnor ( n9596 , n9593 , n9595 );
xnor ( n9597 , n9589 , n9596 );
not ( n9598 , n9597 );
not ( n9599 , n9598 );
or ( n9600 , n9576 , n9599 );
not ( n9601 , n9575 );
nand ( n9602 , n9601 , n9597 );
nand ( n9603 , n9600 , n9602 );
buf ( n9604 , n4815 );
buf ( n9605 , n9604 );
not ( n9606 , n9605 );
buf ( n9607 , n4816 );
not ( n9608 , n9607 );
not ( n9609 , n9608 );
or ( n9610 , n9606 , n9609 );
not ( n9611 , n9604 );
buf ( n9612 , n9607 );
nand ( n9613 , n9611 , n9612 );
nand ( n9614 , n9610 , n9613 );
buf ( n9615 , n4817 );
buf ( n9616 , n9615 );
and ( n9617 , n9614 , n9616 );
not ( n9618 , n9614 );
not ( n9619 , n9615 );
and ( n9620 , n9618 , n9619 );
nor ( n9621 , n9617 , n9620 );
buf ( n9622 , n4818 );
nand ( n9623 , n8781 , n9622 );
buf ( n9624 , n4819 );
buf ( n9625 , n9624 );
and ( n9626 , n9623 , n9625 );
not ( n9627 , n9623 );
not ( n9628 , n9624 );
and ( n9629 , n9627 , n9628 );
nor ( n9630 , n9626 , n9629 );
xor ( n9631 , n9621 , n9630 );
buf ( n9632 , n4820 );
nand ( n9633 , n6828 , n9632 );
buf ( n9634 , n4821 );
buf ( n9635 , n9634 );
and ( n9636 , n9633 , n9635 );
not ( n9637 , n9633 );
not ( n9638 , n9634 );
and ( n9639 , n9637 , n9638 );
nor ( n9640 , n9636 , n9639 );
not ( n9641 , n9640 );
xnor ( n9642 , n9631 , n9641 );
not ( n9643 , n9642 );
not ( n9644 , n9643 );
and ( n9645 , n9603 , n9644 );
not ( n9646 , n9603 );
xor ( n9647 , n9621 , n9640 );
not ( n9648 , n9630 );
xor ( n9649 , n9647 , n9648 );
buf ( n9650 , n9649 );
and ( n9651 , n9646 , n9650 );
nor ( n9652 , n9645 , n9651 );
nand ( n9653 , n9565 , n9652 );
buf ( n9654 , n4822 );
buf ( n9655 , n9654 );
not ( n9656 , n9655 );
buf ( n9657 , n4823 );
buf ( n9658 , n9657 );
not ( n9659 , n9658 );
buf ( n9660 , n4824 );
not ( n9661 , n9660 );
not ( n9662 , n9661 );
or ( n9663 , n9659 , n9662 );
not ( n9664 , n9657 );
buf ( n9665 , n9660 );
nand ( n9666 , n9664 , n9665 );
nand ( n9667 , n9663 , n9666 );
buf ( n9668 , n4825 );
buf ( n9669 , n9668 );
and ( n9670 , n9667 , n9669 );
not ( n9671 , n9667 );
not ( n9672 , n9668 );
and ( n9673 , n9671 , n9672 );
nor ( n9674 , n9670 , n9673 );
buf ( n9675 , n4826 );
nand ( n9676 , n8124 , n9675 );
buf ( n9677 , n4827 );
buf ( n9678 , n9677 );
and ( n9679 , n9676 , n9678 );
not ( n9680 , n9676 );
not ( n9681 , n9677 );
and ( n9682 , n9680 , n9681 );
nor ( n9683 , n9679 , n9682 );
xor ( n9684 , n9674 , n9683 );
buf ( n9685 , n4828 );
nand ( n9686 , n8375 , n9685 );
buf ( n9687 , n4829 );
not ( n9688 , n9687 );
and ( n9689 , n9686 , n9688 );
not ( n9690 , n9686 );
buf ( n9691 , n9687 );
and ( n9692 , n9690 , n9691 );
nor ( n9693 , n9689 , n9692 );
xnor ( n9694 , n9684 , n9693 );
not ( n9695 , n9694 );
not ( n9696 , n9695 );
or ( n9697 , n9656 , n9696 );
not ( n9698 , n9655 );
nand ( n9699 , n9698 , n9694 );
nand ( n9700 , n9697 , n9699 );
not ( n9701 , n9700 );
buf ( n9702 , n4830 );
buf ( n9703 , n9702 );
not ( n9704 , n9703 );
buf ( n9705 , n4831 );
not ( n9706 , n9705 );
not ( n9707 , n9706 );
or ( n9708 , n9704 , n9707 );
not ( n9709 , n9702 );
buf ( n9710 , n9705 );
nand ( n9711 , n9709 , n9710 );
nand ( n9712 , n9708 , n9711 );
not ( n9713 , n9712 );
xor ( n9714 , n6476 , n9713 );
buf ( n9715 , n4832 );
not ( n9716 , n9715 );
buf ( n9717 , n4833 );
nand ( n9718 , n8966 , n9717 );
buf ( n9719 , n4834 );
buf ( n9720 , n9719 );
and ( n9721 , n9718 , n9720 );
not ( n9722 , n9718 );
not ( n9723 , n9719 );
and ( n9724 , n9722 , n9723 );
nor ( n9725 , n9721 , n9724 );
not ( n9726 , n9725 );
or ( n9727 , n9716 , n9726 );
or ( n9728 , n9725 , n9715 );
nand ( n9729 , n9727 , n9728 );
xnor ( n9730 , n9714 , n9729 );
buf ( n9731 , n9730 );
not ( n9732 , n9731 );
and ( n9733 , n9701 , n9732 );
and ( n9734 , n9731 , n9700 );
nor ( n9735 , n9733 , n9734 );
and ( n9736 , n9653 , n9735 );
not ( n9737 , n9653 );
not ( n9738 , n9735 );
and ( n9739 , n9737 , n9738 );
nor ( n9740 , n9736 , n9739 );
not ( n9741 , n9740 );
or ( n9742 , n9474 , n9741 );
or ( n9743 , n9740 , n9473 );
nand ( n9744 , n9742 , n9743 );
buf ( n9745 , n4835 );
buf ( n9746 , n9745 );
not ( n9747 , n9746 );
buf ( n9748 , n4836 );
buf ( n9749 , n9748 );
not ( n9750 , n9749 );
buf ( n9751 , n4837 );
not ( n9752 , n9751 );
not ( n9753 , n9752 );
or ( n9754 , n9750 , n9753 );
not ( n9755 , n9748 );
buf ( n9756 , n9751 );
nand ( n9757 , n9755 , n9756 );
nand ( n9758 , n9754 , n9757 );
buf ( n9759 , n4838 );
not ( n9760 , n9759 );
and ( n9761 , n9758 , n9760 );
not ( n9762 , n9758 );
buf ( n9763 , n9759 );
and ( n9764 , n9762 , n9763 );
nor ( n9765 , n9761 , n9764 );
buf ( n9766 , n4839 );
nand ( n9767 , n6927 , n9766 );
buf ( n9768 , n4840 );
buf ( n9769 , n9768 );
and ( n9770 , n9767 , n9769 );
not ( n9771 , n9767 );
not ( n9772 , n9768 );
and ( n9773 , n9771 , n9772 );
nor ( n9774 , n9770 , n9773 );
xor ( n9775 , n9765 , n9774 );
buf ( n9776 , n4841 );
nand ( n9777 , n9310 , n9776 );
buf ( n9778 , n4842 );
not ( n9779 , n9778 );
and ( n9780 , n9777 , n9779 );
not ( n9781 , n9777 );
buf ( n9782 , n9778 );
and ( n9783 , n9781 , n9782 );
nor ( n9784 , n9780 , n9783 );
xnor ( n9785 , n9775 , n9784 );
not ( n9786 , n9785 );
or ( n9787 , n9747 , n9786 );
buf ( n9788 , n9785 );
or ( n9789 , n9788 , n9746 );
nand ( n9790 , n9787 , n9789 );
not ( n9791 , n9790 );
not ( n9792 , n9791 );
buf ( n9793 , n4843 );
not ( n9794 , n9793 );
buf ( n9795 , n4844 );
buf ( n9796 , n9795 );
and ( n9797 , n9794 , n9796 );
not ( n9798 , n9794 );
not ( n9799 , n9795 );
and ( n9800 , n9798 , n9799 );
nor ( n9801 , n9797 , n9800 );
buf ( n9802 , n4845 );
nand ( n9803 , n9160 , n9802 );
buf ( n9804 , n4846 );
buf ( n9805 , n9804 );
and ( n9806 , n9803 , n9805 );
not ( n9807 , n9803 );
not ( n9808 , n9804 );
and ( n9809 , n9807 , n9808 );
nor ( n9810 , n9806 , n9809 );
not ( n9811 , n9810 );
buf ( n9812 , n8322 );
buf ( n9813 , n4847 );
nand ( n9814 , n9812 , n9813 );
buf ( n9815 , n4848 );
not ( n9816 , n9815 );
and ( n9817 , n9814 , n9816 );
not ( n9818 , n9814 );
buf ( n9819 , n9815 );
and ( n9820 , n9818 , n9819 );
nor ( n9821 , n9817 , n9820 );
not ( n9822 , n9821 );
or ( n9823 , n9811 , n9822 );
not ( n9824 , n9821 );
not ( n9825 , n9810 );
nand ( n9826 , n9824 , n9825 );
nand ( n9827 , n9823 , n9826 );
buf ( n9828 , n4849 );
not ( n9829 , n9828 );
and ( n9830 , n9827 , n9829 );
not ( n9831 , n9827 );
buf ( n9832 , n9828 );
and ( n9833 , n9831 , n9832 );
nor ( n9834 , n9830 , n9833 );
not ( n9835 , n9834 );
and ( n9836 , n9801 , n9835 );
not ( n9837 , n9801 );
and ( n9838 , n9837 , n9834 );
nor ( n9839 , n9836 , n9838 );
not ( n9840 , n9839 );
not ( n9841 , n9840 );
or ( n9842 , n9792 , n9841 );
xor ( n9843 , n9829 , n9801 );
xnor ( n9844 , n9843 , n9827 );
nand ( n9845 , n9844 , n9790 );
nand ( n9846 , n9842 , n9845 );
not ( n9847 , n9846 );
buf ( n9848 , n4850 );
nand ( n9849 , n8124 , n9848 );
buf ( n9850 , n4851 );
xor ( n9851 , n9849 , n9850 );
not ( n9852 , n9851 );
buf ( n9853 , n4852 );
nand ( n9854 , n7606 , n9853 );
buf ( n9855 , n4853 );
buf ( n9856 , n9855 );
and ( n9857 , n9854 , n9856 );
not ( n9858 , n9854 );
not ( n9859 , n9855 );
and ( n9860 , n9858 , n9859 );
nor ( n9861 , n9857 , n9860 );
not ( n9862 , n9861 );
buf ( n9863 , n4854 );
nand ( n9864 , n7344 , n9863 );
buf ( n9865 , n4855 );
not ( n9866 , n9865 );
and ( n9867 , n9864 , n9866 );
not ( n9868 , n9864 );
buf ( n9869 , n9865 );
and ( n9870 , n9868 , n9869 );
nor ( n9871 , n9867 , n9870 );
not ( n9872 , n9871 );
or ( n9873 , n9862 , n9872 );
or ( n9874 , n9861 , n9871 );
nand ( n9875 , n9873 , n9874 );
buf ( n9876 , n4856 );
buf ( n9877 , n9876 );
not ( n9878 , n9877 );
buf ( n9879 , n4857 );
not ( n9880 , n9879 );
not ( n9881 , n9880 );
or ( n9882 , n9878 , n9881 );
not ( n9883 , n9876 );
buf ( n9884 , n9879 );
nand ( n9885 , n9883 , n9884 );
nand ( n9886 , n9882 , n9885 );
buf ( n9887 , n4858 );
not ( n9888 , n9887 );
and ( n9889 , n9886 , n9888 );
not ( n9890 , n9886 );
buf ( n9891 , n9887 );
and ( n9892 , n9890 , n9891 );
nor ( n9893 , n9889 , n9892 );
not ( n9894 , n9893 );
and ( n9895 , n9875 , n9894 );
not ( n9896 , n9875 );
and ( n9897 , n9896 , n9893 );
nor ( n9898 , n9895 , n9897 );
not ( n9899 , n9898 );
or ( n9900 , n9852 , n9899 );
or ( n9901 , n9898 , n9851 );
nand ( n9902 , n9900 , n9901 );
buf ( n9903 , n4859 );
buf ( n9904 , n9903 );
not ( n9905 , n9904 );
buf ( n9906 , n4860 );
not ( n9907 , n9906 );
not ( n9908 , n9907 );
or ( n9909 , n9905 , n9908 );
not ( n9910 , n9903 );
buf ( n9911 , n9906 );
nand ( n9912 , n9910 , n9911 );
nand ( n9913 , n9909 , n9912 );
buf ( n9914 , n4861 );
buf ( n9915 , n9914 );
and ( n9916 , n9913 , n9915 );
not ( n9917 , n9913 );
not ( n9918 , n9914 );
and ( n9919 , n9917 , n9918 );
nor ( n9920 , n9916 , n9919 );
buf ( n9921 , n4862 );
nand ( n9922 , n7787 , n9921 );
buf ( n9923 , n4863 );
buf ( n9924 , n9923 );
and ( n9925 , n9922 , n9924 );
not ( n9926 , n9922 );
not ( n9927 , n9923 );
and ( n9928 , n9926 , n9927 );
nor ( n9929 , n9925 , n9928 );
xor ( n9930 , n9920 , n9929 );
buf ( n9931 , n4864 );
nand ( n9932 , n7247 , n9931 );
buf ( n9933 , n4865 );
buf ( n9934 , n9933 );
and ( n9935 , n9932 , n9934 );
not ( n9936 , n9932 );
not ( n9937 , n9933 );
and ( n9938 , n9936 , n9937 );
nor ( n9939 , n9935 , n9938 );
xnor ( n9940 , n9930 , n9939 );
not ( n9941 , n9940 );
not ( n9942 , n9941 );
and ( n9943 , n9902 , n9942 );
not ( n9944 , n9902 );
and ( n9945 , n9944 , n9941 );
nor ( n9946 , n9943 , n9945 );
not ( n9947 , n9946 );
nand ( n9948 , n9847 , n9947 );
buf ( n9949 , n4866 );
buf ( n9950 , n9949 );
buf ( n9951 , n4867 );
buf ( n9952 , n9951 );
not ( n9953 , n9952 );
buf ( n9954 , n4868 );
not ( n9955 , n9954 );
not ( n9956 , n9955 );
or ( n9957 , n9953 , n9956 );
not ( n9958 , n9951 );
buf ( n9959 , n9954 );
nand ( n9960 , n9958 , n9959 );
nand ( n9961 , n9957 , n9960 );
buf ( n9962 , n4869 );
buf ( n9963 , n9962 );
and ( n9964 , n9961 , n9963 );
not ( n9965 , n9961 );
not ( n9966 , n9962 );
and ( n9967 , n9965 , n9966 );
nor ( n9968 , n9964 , n9967 );
not ( n9969 , n9968 );
buf ( n9970 , n4870 );
nand ( n9971 , n7698 , n9970 );
buf ( n9972 , n4871 );
buf ( n9973 , n9972 );
and ( n9974 , n9971 , n9973 );
not ( n9975 , n9971 );
not ( n9976 , n9972 );
and ( n9977 , n9975 , n9976 );
nor ( n9978 , n9974 , n9977 );
xor ( n9979 , n9969 , n9978 );
buf ( n9980 , n4872 );
nand ( n9981 , n7569 , n9980 );
buf ( n9982 , n4873 );
buf ( n9983 , n9982 );
and ( n9984 , n9981 , n9983 );
not ( n9985 , n9981 );
not ( n9986 , n9982 );
and ( n9987 , n9985 , n9986 );
nor ( n9988 , n9984 , n9987 );
xnor ( n9989 , n9979 , n9988 );
buf ( n9990 , n9989 );
xor ( n9991 , n9950 , n9990 );
buf ( n9992 , n4874 );
not ( n9993 , n9992 );
buf ( n9994 , n4875 );
not ( n9995 , n9994 );
buf ( n9996 , n4876 );
buf ( n9997 , n9996 );
and ( n9998 , n9995 , n9997 );
not ( n9999 , n9995 );
not ( n10000 , n9996 );
and ( n10001 , n9999 , n10000 );
nor ( n10002 , n9998 , n10001 );
xor ( n10003 , n9993 , n10002 );
buf ( n10004 , n4877 );
buf ( n10005 , n4878 );
xor ( n10006 , n10004 , n10005 );
buf ( n10007 , n4879 );
nand ( n10008 , n6558 , n10007 );
xnor ( n10009 , n10006 , n10008 );
xnor ( n10010 , n10003 , n10009 );
buf ( n10011 , n10010 );
xnor ( n10012 , n9991 , n10011 );
not ( n10013 , n10012 );
and ( n10014 , n9948 , n10013 );
not ( n10015 , n9948 );
and ( n10016 , n10015 , n10012 );
nor ( n10017 , n10014 , n10016 );
not ( n10018 , n10017 );
and ( n10019 , n9744 , n10018 );
not ( n10020 , n9744 );
and ( n10021 , n10020 , n10017 );
nor ( n10022 , n10019 , n10021 );
not ( n10023 , n10022 );
buf ( n10024 , n4880 );
buf ( n10025 , n10024 );
not ( n10026 , n10025 );
not ( n10027 , n8963 );
not ( n10028 , n8975 );
or ( n10029 , n10027 , n10028 );
or ( n10030 , n8963 , n8975 );
nand ( n10031 , n10029 , n10030 );
not ( n10032 , n8953 );
and ( n10033 , n10031 , n10032 );
not ( n10034 , n10031 );
and ( n10035 , n10034 , n8953 );
nor ( n10036 , n10033 , n10035 );
buf ( n10037 , n10036 );
not ( n10038 , n10037 );
or ( n10039 , n10026 , n10038 );
not ( n10040 , n10025 );
nand ( n10041 , n10040 , n8978 );
nand ( n10042 , n10039 , n10041 );
and ( n10043 , n10042 , n8986 );
not ( n10044 , n10042 );
and ( n10045 , n10044 , n7540 );
nor ( n10046 , n10043 , n10045 );
not ( n10047 , n10046 );
buf ( n10048 , n4881 );
buf ( n10049 , n10048 );
not ( n10050 , n10049 );
buf ( n10051 , n4882 );
buf ( n10052 , n10051 );
not ( n10053 , n10052 );
buf ( n10054 , n4883 );
not ( n10055 , n10054 );
not ( n10056 , n10055 );
or ( n10057 , n10053 , n10056 );
not ( n10058 , n10051 );
buf ( n10059 , n10054 );
nand ( n10060 , n10058 , n10059 );
nand ( n10061 , n10057 , n10060 );
buf ( n10062 , n4884 );
buf ( n10063 , n10062 );
and ( n10064 , n10061 , n10063 );
not ( n10065 , n10061 );
not ( n10066 , n10062 );
and ( n10067 , n10065 , n10066 );
nor ( n10068 , n10064 , n10067 );
buf ( n10069 , n4885 );
nand ( n10070 , n6502 , n10069 );
buf ( n10071 , n4886 );
buf ( n10072 , n10071 );
and ( n10073 , n10070 , n10072 );
not ( n10074 , n10070 );
not ( n10075 , n10071 );
and ( n10076 , n10074 , n10075 );
nor ( n10077 , n10073 , n10076 );
xor ( n10078 , n10068 , n10077 );
buf ( n10079 , n4887 );
nand ( n10080 , n8125 , n10079 );
buf ( n10081 , n4888 );
not ( n10082 , n10081 );
and ( n10083 , n10080 , n10082 );
not ( n10084 , n10080 );
buf ( n10085 , n10081 );
and ( n10086 , n10084 , n10085 );
nor ( n10087 , n10083 , n10086 );
xnor ( n10088 , n10078 , n10087 );
buf ( n10089 , n10088 );
not ( n10090 , n10089 );
not ( n10091 , n10090 );
or ( n10092 , n10050 , n10091 );
not ( n10093 , n10048 );
nand ( n10094 , n10089 , n10093 );
nand ( n10095 , n10092 , n10094 );
buf ( n10096 , n4889 );
buf ( n10097 , n10096 );
buf ( n10098 , n4890 );
buf ( n10099 , n10098 );
not ( n10100 , n10099 );
buf ( n10101 , n4891 );
not ( n10102 , n10101 );
not ( n10103 , n10102 );
or ( n10104 , n10100 , n10103 );
not ( n10105 , n10098 );
buf ( n10106 , n10101 );
nand ( n10107 , n10105 , n10106 );
nand ( n10108 , n10104 , n10107 );
xor ( n10109 , n10097 , n10108 );
buf ( n10110 , n4892 );
not ( n10111 , n10110 );
buf ( n10112 , n4893 );
nand ( n10113 , n7355 , n10112 );
buf ( n10114 , n4894 );
buf ( n10115 , n10114 );
and ( n10116 , n10113 , n10115 );
not ( n10117 , n10113 );
not ( n10118 , n10114 );
and ( n10119 , n10117 , n10118 );
nor ( n10120 , n10116 , n10119 );
not ( n10121 , n10120 );
or ( n10122 , n10111 , n10121 );
or ( n10123 , n10120 , n10110 );
nand ( n10124 , n10122 , n10123 );
xnor ( n10125 , n10109 , n10124 );
buf ( n10126 , n10125 );
buf ( n10127 , n10126 );
xnor ( n10128 , n10095 , n10127 );
not ( n10129 , n10128 );
buf ( n10130 , n9064 );
not ( n10131 , n10130 );
not ( n10132 , n9061 );
and ( n10133 , n10131 , n10132 );
and ( n10134 , n10130 , n9061 );
nor ( n10135 , n10133 , n10134 );
not ( n10136 , n10135 );
buf ( n10137 , n4895 );
buf ( n10138 , n10137 );
not ( n10139 , n10138 );
buf ( n10140 , n4896 );
not ( n10141 , n10140 );
not ( n10142 , n10141 );
or ( n10143 , n10139 , n10142 );
not ( n10144 , n10137 );
buf ( n10145 , n10140 );
nand ( n10146 , n10144 , n10145 );
nand ( n10147 , n10143 , n10146 );
buf ( n10148 , n4897 );
buf ( n10149 , n10148 );
and ( n10150 , n10147 , n10149 );
not ( n10151 , n10147 );
not ( n10152 , n10148 );
and ( n10153 , n10151 , n10152 );
nor ( n10154 , n10150 , n10153 );
buf ( n10155 , n4898 );
nand ( n10156 , n6828 , n10155 );
buf ( n10157 , n4899 );
buf ( n10158 , n10157 );
and ( n10159 , n10156 , n10158 );
not ( n10160 , n10156 );
not ( n10161 , n10157 );
and ( n10162 , n10160 , n10161 );
nor ( n10163 , n10159 , n10162 );
xor ( n10164 , n10154 , n10163 );
buf ( n10165 , n7013 );
buf ( n10166 , n4900 );
nand ( n10167 , n10165 , n10166 );
buf ( n10168 , n4901 );
buf ( n10169 , n10168 );
and ( n10170 , n10167 , n10169 );
not ( n10171 , n10167 );
not ( n10172 , n10168 );
and ( n10173 , n10171 , n10172 );
nor ( n10174 , n10170 , n10173 );
xor ( n10175 , n10164 , n10174 );
not ( n10176 , n10175 );
or ( n10177 , n10136 , n10176 );
or ( n10178 , n10175 , n10135 );
nand ( n10179 , n10177 , n10178 );
not ( n10180 , n10179 );
buf ( n10181 , n4902 );
nand ( n10182 , n6916 , n10181 );
buf ( n10183 , n4903 );
buf ( n10184 , n10183 );
and ( n10185 , n10182 , n10184 );
not ( n10186 , n10182 );
not ( n10187 , n10183 );
and ( n10188 , n10186 , n10187 );
nor ( n10189 , n10185 , n10188 );
not ( n10190 , n10189 );
buf ( n10191 , n4904 );
nand ( n10192 , n8966 , n10191 );
buf ( n10193 , n4905 );
not ( n10194 , n10193 );
and ( n10195 , n10192 , n10194 );
not ( n10196 , n10192 );
buf ( n10197 , n10193 );
and ( n10198 , n10196 , n10197 );
nor ( n10199 , n10195 , n10198 );
not ( n10200 , n10199 );
or ( n10201 , n10190 , n10200 );
or ( n10202 , n10189 , n10199 );
nand ( n10203 , n10201 , n10202 );
buf ( n10204 , n4906 );
buf ( n10205 , n10204 );
not ( n10206 , n10205 );
buf ( n10207 , n4907 );
not ( n10208 , n10207 );
not ( n10209 , n10208 );
or ( n10210 , n10206 , n10209 );
not ( n10211 , n10204 );
buf ( n10212 , n10207 );
nand ( n10213 , n10211 , n10212 );
nand ( n10214 , n10210 , n10213 );
buf ( n10215 , n4908 );
buf ( n10216 , n10215 );
and ( n10217 , n10214 , n10216 );
not ( n10218 , n10214 );
not ( n10219 , n10215 );
and ( n10220 , n10218 , n10219 );
nor ( n10221 , n10217 , n10220 );
not ( n10222 , n10221 );
and ( n10223 , n10203 , n10222 );
not ( n10224 , n10203 );
and ( n10225 , n10224 , n10221 );
nor ( n10226 , n10223 , n10225 );
buf ( n10227 , n10226 );
buf ( n10228 , n10227 );
not ( n10229 , n10228 );
and ( n10230 , n10180 , n10229 );
and ( n10231 , n10179 , n10227 );
nor ( n10232 , n10230 , n10231 );
not ( n10233 , n10232 );
nand ( n10234 , n10129 , n10233 );
not ( n10235 , n10234 );
or ( n10236 , n10047 , n10235 );
or ( n10237 , n10046 , n10234 );
nand ( n10238 , n10236 , n10237 );
not ( n10239 , n7896 );
buf ( n10240 , n4909 );
buf ( n10241 , n10240 );
not ( n10242 , n10241 );
buf ( n10243 , n4910 );
not ( n10244 , n10243 );
not ( n10245 , n10244 );
or ( n10246 , n10242 , n10245 );
not ( n10247 , n10240 );
buf ( n10248 , n10243 );
nand ( n10249 , n10247 , n10248 );
nand ( n10250 , n10246 , n10249 );
not ( n10251 , n10250 );
buf ( n10252 , n4911 );
buf ( n10253 , n4912 );
xor ( n10254 , n10252 , n10253 );
buf ( n10255 , n4913 );
nand ( n10256 , n6577 , n10255 );
buf ( n10257 , n4914 );
not ( n10258 , n10257 );
and ( n10259 , n10256 , n10258 );
not ( n10260 , n10256 );
buf ( n10261 , n10257 );
and ( n10262 , n10260 , n10261 );
nor ( n10263 , n10259 , n10262 );
xnor ( n10264 , n10254 , n10263 );
not ( n10265 , n10264 );
or ( n10266 , n10251 , n10265 );
not ( n10267 , n10264 );
not ( n10268 , n10250 );
nand ( n10269 , n10267 , n10268 );
nand ( n10270 , n10266 , n10269 );
buf ( n10271 , n10270 );
not ( n10272 , n10271 );
or ( n10273 , n10239 , n10272 );
or ( n10274 , n10271 , n7896 );
nand ( n10275 , n10273 , n10274 );
buf ( n10276 , n4915 );
buf ( n10277 , n4916 );
nand ( n10278 , n8537 , n10277 );
buf ( n10279 , n4917 );
buf ( n10280 , n10279 );
and ( n10281 , n10278 , n10280 );
not ( n10282 , n10278 );
not ( n10283 , n10279 );
and ( n10284 , n10282 , n10283 );
nor ( n10285 , n10281 , n10284 );
xor ( n10286 , n10276 , n10285 );
buf ( n10287 , n4918 );
nand ( n10288 , n9310 , n10287 );
buf ( n10289 , n4919 );
not ( n10290 , n10289 );
and ( n10291 , n10288 , n10290 );
not ( n10292 , n10288 );
buf ( n10293 , n10289 );
and ( n10294 , n10292 , n10293 );
nor ( n10295 , n10291 , n10294 );
xnor ( n10296 , n10286 , n10295 );
not ( n10297 , n10296 );
buf ( n10298 , n4920 );
not ( n10299 , n10298 );
buf ( n10300 , n4921 );
buf ( n10301 , n10300 );
and ( n10302 , n10299 , n10301 );
not ( n10303 , n10299 );
not ( n10304 , n10300 );
and ( n10305 , n10303 , n10304 );
nor ( n10306 , n10302 , n10305 );
not ( n10307 , n10306 );
and ( n10308 , n10297 , n10307 );
and ( n10309 , n10296 , n10306 );
nor ( n10310 , n10308 , n10309 );
buf ( n10311 , n10310 );
and ( n10312 , n10275 , n10311 );
not ( n10313 , n10275 );
not ( n10314 , n10311 );
and ( n10315 , n10313 , n10314 );
nor ( n10316 , n10312 , n10315 );
buf ( n10317 , n4922 );
buf ( n10318 , n4923 );
nand ( n10319 , n9160 , n10318 );
buf ( n10320 , n4924 );
buf ( n10321 , n10320 );
and ( n10322 , n10319 , n10321 );
not ( n10323 , n10319 );
not ( n10324 , n10320 );
and ( n10325 , n10323 , n10324 );
nor ( n10326 , n10322 , n10325 );
xor ( n10327 , n10317 , n10326 );
buf ( n10328 , n4925 );
nand ( n10329 , n6605 , n10328 );
buf ( n10330 , n4926 );
not ( n10331 , n10330 );
and ( n10332 , n10329 , n10331 );
not ( n10333 , n10329 );
buf ( n10334 , n10330 );
and ( n10335 , n10333 , n10334 );
nor ( n10336 , n10332 , n10335 );
xnor ( n10337 , n10327 , n10336 );
not ( n10338 , n10337 );
buf ( n10339 , n4927 );
not ( n10340 , n10339 );
not ( n10341 , n10340 );
buf ( n10342 , n4928 );
not ( n10343 , n10342 );
and ( n10344 , n10341 , n10343 );
and ( n10345 , n10342 , n10340 );
nor ( n10346 , n10344 , n10345 );
not ( n10347 , n10346 );
and ( n10348 , n10338 , n10347 );
and ( n10349 , n10337 , n10346 );
nor ( n10350 , n10348 , n10349 );
buf ( n10351 , n10350 );
not ( n10352 , n10351 );
not ( n10353 , n9648 );
buf ( n10354 , n4929 );
buf ( n10355 , n10354 );
not ( n10356 , n10355 );
buf ( n10357 , n4930 );
not ( n10358 , n10357 );
not ( n10359 , n10358 );
or ( n10360 , n10356 , n10359 );
not ( n10361 , n10354 );
buf ( n10362 , n10357 );
nand ( n10363 , n10361 , n10362 );
nand ( n10364 , n10360 , n10363 );
buf ( n10365 , n4931 );
not ( n10366 , n10365 );
and ( n10367 , n10364 , n10366 );
not ( n10368 , n10364 );
buf ( n10369 , n10365 );
and ( n10370 , n10368 , n10369 );
nor ( n10371 , n10367 , n10370 );
buf ( n10372 , n6718 );
buf ( n10373 , n4932 );
nand ( n10374 , n10372 , n10373 );
buf ( n10375 , n4933 );
buf ( n10376 , n10375 );
and ( n10377 , n10374 , n10376 );
not ( n10378 , n10374 );
not ( n10379 , n10375 );
and ( n10380 , n10378 , n10379 );
nor ( n10381 , n10377 , n10380 );
xor ( n10382 , n10371 , n10381 );
buf ( n10383 , n6927 );
buf ( n10384 , n4934 );
nand ( n10385 , n10383 , n10384 );
buf ( n10386 , n4935 );
buf ( n10387 , n10386 );
and ( n10388 , n10385 , n10387 );
not ( n10389 , n10385 );
not ( n10390 , n10386 );
and ( n10391 , n10389 , n10390 );
nor ( n10392 , n10388 , n10391 );
xnor ( n10393 , n10382 , n10392 );
not ( n10394 , n10393 );
not ( n10395 , n10394 );
or ( n10396 , n10353 , n10395 );
not ( n10397 , n9648 );
buf ( n10398 , n10393 );
nand ( n10399 , n10397 , n10398 );
nand ( n10400 , n10396 , n10399 );
not ( n10401 , n10400 );
and ( n10402 , n10352 , n10401 );
and ( n10403 , n10351 , n10400 );
nor ( n10404 , n10402 , n10403 );
not ( n10405 , n10404 );
nand ( n10406 , n10316 , n10405 );
not ( n10407 , n10406 );
buf ( n10408 , n6590 );
not ( n10409 , n10408 );
not ( n10410 , n8548 );
or ( n10411 , n10409 , n10410 );
or ( n10412 , n8548 , n10408 );
nand ( n10413 , n10411 , n10412 );
buf ( n10414 , n4936 );
buf ( n10415 , n10414 );
not ( n10416 , n10415 );
buf ( n10417 , n4937 );
not ( n10418 , n10417 );
not ( n10419 , n10418 );
or ( n10420 , n10416 , n10419 );
not ( n10421 , n10414 );
buf ( n10422 , n10417 );
nand ( n10423 , n10421 , n10422 );
nand ( n10424 , n10420 , n10423 );
buf ( n10425 , n4938 );
not ( n10426 , n10425 );
and ( n10427 , n10424 , n10426 );
not ( n10428 , n10424 );
buf ( n10429 , n10425 );
and ( n10430 , n10428 , n10429 );
nor ( n10431 , n10427 , n10430 );
buf ( n10432 , n4939 );
nand ( n10433 , n10372 , n10432 );
buf ( n10434 , n4940 );
buf ( n10435 , n10434 );
and ( n10436 , n10433 , n10435 );
not ( n10437 , n10433 );
not ( n10438 , n10434 );
and ( n10439 , n10437 , n10438 );
nor ( n10440 , n10436 , n10439 );
xor ( n10441 , n10431 , n10440 );
xnor ( n10442 , n10441 , n8274 );
buf ( n10443 , n10442 );
and ( n10444 , n10413 , n10443 );
not ( n10445 , n10413 );
not ( n10446 , n10442 );
buf ( n10447 , n10446 );
and ( n10448 , n10445 , n10447 );
nor ( n10449 , n10444 , n10448 );
not ( n10450 , n10449 );
and ( n10451 , n10407 , n10450 );
and ( n10452 , n10406 , n10449 );
nor ( n10453 , n10451 , n10452 );
and ( n10454 , n10238 , n10453 );
not ( n10455 , n10238 );
not ( n10456 , n10453 );
and ( n10457 , n10455 , n10456 );
nor ( n10458 , n10454 , n10457 );
not ( n10459 , n10458 );
not ( n10460 , n10459 );
and ( n10461 , n10023 , n10460 );
and ( n10462 , n10459 , n10022 );
nor ( n10463 , n10461 , n10462 );
not ( n10464 , n10463 );
or ( n10465 , n9385 , n10464 );
not ( n10466 , n9384 );
not ( n10467 , n10459 );
not ( n10468 , n10022 );
or ( n10469 , n10467 , n10468 );
not ( n10470 , n10022 );
nand ( n10471 , n10470 , n10458 );
nand ( n10472 , n10469 , n10471 );
nand ( n10473 , n10466 , n10472 );
nand ( n10474 , n10465 , n10473 );
buf ( n10475 , n4941 );
nand ( n10476 , n7912 , n10475 );
buf ( n10477 , n4942 );
buf ( n10478 , n10477 );
and ( n10479 , n10476 , n10478 );
not ( n10480 , n10476 );
not ( n10481 , n10477 );
and ( n10482 , n10480 , n10481 );
nor ( n10483 , n10479 , n10482 );
not ( n10484 , n10483 );
not ( n10485 , n10089 );
or ( n10486 , n10484 , n10485 );
or ( n10487 , n10089 , n10483 );
nand ( n10488 , n10486 , n10487 );
not ( n10489 , n10488 );
not ( n10490 , n10489 );
not ( n10491 , n10125 );
not ( n10492 , n10491 );
or ( n10493 , n10490 , n10492 );
nand ( n10494 , n10126 , n10488 );
nand ( n10495 , n10493 , n10494 );
not ( n10496 , n10495 );
buf ( n10497 , n4943 );
buf ( n10498 , n10497 );
not ( n10499 , n10498 );
buf ( n10500 , n4944 );
not ( n10501 , n10500 );
not ( n10502 , n10501 );
or ( n10503 , n10499 , n10502 );
not ( n10504 , n10497 );
buf ( n10505 , n10500 );
nand ( n10506 , n10504 , n10505 );
nand ( n10507 , n10503 , n10506 );
buf ( n10508 , n4945 );
buf ( n10509 , n10508 );
and ( n10510 , n10507 , n10509 );
not ( n10511 , n10507 );
not ( n10512 , n10508 );
and ( n10513 , n10511 , n10512 );
nor ( n10514 , n10510 , n10513 );
buf ( n10515 , n4946 );
nand ( n10516 , n7197 , n10515 );
buf ( n10517 , n4947 );
buf ( n10518 , n10517 );
and ( n10519 , n10516 , n10518 );
not ( n10520 , n10516 );
not ( n10521 , n10517 );
and ( n10522 , n10520 , n10521 );
nor ( n10523 , n10519 , n10522 );
xor ( n10524 , n10514 , n10523 );
buf ( n10525 , n4948 );
nand ( n10526 , n8537 , n10525 );
buf ( n10527 , n4949 );
buf ( n10528 , n10527 );
and ( n10529 , n10526 , n10528 );
not ( n10530 , n10526 );
not ( n10531 , n10527 );
and ( n10532 , n10530 , n10531 );
nor ( n10533 , n10529 , n10532 );
xor ( n10534 , n10524 , n10533 );
not ( n10535 , n10534 );
not ( n10536 , n10535 );
buf ( n10537 , n4950 );
buf ( n10538 , n10537 );
not ( n10539 , n10538 );
and ( n10540 , n10536 , n10539 );
not ( n10541 , n10534 );
and ( n10542 , n10541 , n10538 );
nor ( n10543 , n10540 , n10542 );
not ( n10544 , n9950 );
buf ( n10545 , n4951 );
not ( n10546 , n10545 );
not ( n10547 , n10546 );
or ( n10548 , n10544 , n10547 );
not ( n10549 , n9949 );
buf ( n10550 , n10545 );
nand ( n10551 , n10549 , n10550 );
nand ( n10552 , n10548 , n10551 );
buf ( n10553 , n4952 );
not ( n10554 , n10553 );
and ( n10555 , n10552 , n10554 );
not ( n10556 , n10552 );
buf ( n10557 , n10553 );
and ( n10558 , n10556 , n10557 );
nor ( n10559 , n10555 , n10558 );
buf ( n10560 , n4953 );
nand ( n10561 , n6719 , n10560 );
buf ( n10562 , n4954 );
buf ( n10563 , n10562 );
and ( n10564 , n10561 , n10563 );
not ( n10565 , n10561 );
not ( n10566 , n10562 );
and ( n10567 , n10565 , n10566 );
nor ( n10568 , n10564 , n10567 );
xor ( n10569 , n10559 , n10568 );
buf ( n10570 , n7355 );
buf ( n10571 , n4955 );
nand ( n10572 , n10570 , n10571 );
buf ( n10573 , n4956 );
not ( n10574 , n10573 );
and ( n10575 , n10572 , n10574 );
not ( n10576 , n10572 );
buf ( n10577 , n10573 );
and ( n10578 , n10576 , n10577 );
nor ( n10579 , n10575 , n10578 );
xnor ( n10580 , n10569 , n10579 );
buf ( n10581 , n10580 );
and ( n10582 , n10543 , n10581 );
not ( n10583 , n10543 );
not ( n10584 , n10568 );
xor ( n10585 , n10559 , n10584 );
xnor ( n10586 , n10585 , n10579 );
buf ( n10587 , n10586 );
and ( n10588 , n10583 , n10587 );
nor ( n10589 , n10582 , n10588 );
nand ( n10590 , n10496 , n10589 );
not ( n10591 , n10590 );
buf ( n10592 , n4957 );
buf ( n10593 , n10592 );
not ( n10594 , n10593 );
buf ( n10595 , n4958 );
not ( n10596 , n10595 );
not ( n10597 , n10596 );
or ( n10598 , n10594 , n10597 );
not ( n10599 , n10592 );
buf ( n10600 , n10595 );
nand ( n10601 , n10599 , n10600 );
nand ( n10602 , n10598 , n10601 );
not ( n10603 , n10602 );
not ( n10604 , n7759 );
xor ( n10605 , n10604 , n8563 );
buf ( n10606 , n4959 );
nand ( n10607 , n8537 , n10606 );
buf ( n10608 , n4960 );
buf ( n10609 , n10608 );
and ( n10610 , n10607 , n10609 );
not ( n10611 , n10607 );
not ( n10612 , n10608 );
and ( n10613 , n10611 , n10612 );
nor ( n10614 , n10610 , n10613 );
xnor ( n10615 , n10605 , n10614 );
xor ( n10616 , n10603 , n10615 );
not ( n10617 , n10616 );
buf ( n10618 , n4961 );
nand ( n10619 , n6719 , n10618 );
buf ( n10620 , n4962 );
buf ( n10621 , n10620 );
and ( n10622 , n10619 , n10621 );
not ( n10623 , n10619 );
not ( n10624 , n10620 );
and ( n10625 , n10623 , n10624 );
nor ( n10626 , n10622 , n10625 );
buf ( n10627 , n10626 );
not ( n10628 , n10627 );
buf ( n10629 , n4963 );
buf ( n10630 , n10629 );
not ( n10631 , n10630 );
buf ( n10632 , n4964 );
not ( n10633 , n10632 );
not ( n10634 , n10633 );
or ( n10635 , n10631 , n10634 );
not ( n10636 , n10629 );
buf ( n10637 , n10632 );
nand ( n10638 , n10636 , n10637 );
nand ( n10639 , n10635 , n10638 );
buf ( n10640 , n4965 );
not ( n10641 , n10640 );
and ( n10642 , n10639 , n10641 );
not ( n10643 , n10639 );
buf ( n10644 , n10640 );
and ( n10645 , n10643 , n10644 );
nor ( n10646 , n10642 , n10645 );
buf ( n10647 , n4966 );
nand ( n10648 , n6577 , n10647 );
buf ( n10649 , n4967 );
buf ( n10650 , n10649 );
and ( n10651 , n10648 , n10650 );
not ( n10652 , n10648 );
not ( n10653 , n10649 );
and ( n10654 , n10652 , n10653 );
nor ( n10655 , n10651 , n10654 );
xor ( n10656 , n10646 , n10655 );
buf ( n10657 , n4968 );
nand ( n10658 , n6770 , n10657 );
buf ( n10659 , n4969 );
buf ( n10660 , n10659 );
and ( n10661 , n10658 , n10660 );
not ( n10662 , n10658 );
not ( n10663 , n10659 );
and ( n10664 , n10662 , n10663 );
nor ( n10665 , n10661 , n10664 );
xnor ( n10666 , n10656 , n10665 );
not ( n10667 , n10666 );
or ( n10668 , n10628 , n10667 );
or ( n10669 , n10666 , n10627 );
nand ( n10670 , n10668 , n10669 );
not ( n10671 , n10670 );
and ( n10672 , n10617 , n10671 );
not ( n10673 , n10602 );
not ( n10674 , n10615 );
not ( n10675 , n10674 );
or ( n10676 , n10673 , n10675 );
nand ( n10677 , n10615 , n10603 );
nand ( n10678 , n10676 , n10677 );
not ( n10679 , n10678 );
and ( n10680 , n10679 , n10670 );
nor ( n10681 , n10672 , n10680 );
not ( n10682 , n10681 );
not ( n10683 , n10682 );
and ( n10684 , n10591 , n10683 );
and ( n10685 , n10590 , n10682 );
nor ( n10686 , n10684 , n10685 );
not ( n10687 , n10686 );
not ( n10688 , n9839 );
buf ( n10689 , n4970 );
nand ( n10690 , n10372 , n10689 );
buf ( n10691 , n4971 );
xor ( n10692 , n10690 , n10691 );
buf ( n10693 , n10692 );
not ( n10694 , n10693 );
not ( n10695 , n9785 );
not ( n10696 , n10695 );
or ( n10697 , n10694 , n10696 );
or ( n10698 , n10695 , n10693 );
nand ( n10699 , n10697 , n10698 );
not ( n10700 , n10699 );
and ( n10701 , n10688 , n10700 );
and ( n10702 , n9839 , n10699 );
nor ( n10703 , n10701 , n10702 );
buf ( n10704 , n4972 );
buf ( n10705 , n10704 );
not ( n10706 , n10705 );
buf ( n10707 , n4973 );
buf ( n10708 , n10707 );
not ( n10709 , n10708 );
buf ( n10710 , n4974 );
not ( n10711 , n10710 );
not ( n10712 , n10711 );
or ( n10713 , n10709 , n10712 );
not ( n10714 , n10707 );
buf ( n10715 , n10710 );
nand ( n10716 , n10714 , n10715 );
nand ( n10717 , n10713 , n10716 );
buf ( n10718 , n4975 );
not ( n10719 , n10718 );
and ( n10720 , n10717 , n10719 );
not ( n10721 , n10717 );
buf ( n10722 , n10718 );
and ( n10723 , n10721 , n10722 );
nor ( n10724 , n10720 , n10723 );
buf ( n10725 , n4976 );
nand ( n10726 , n7013 , n10725 );
buf ( n10727 , n4977 );
buf ( n10728 , n10727 );
and ( n10729 , n10726 , n10728 );
not ( n10730 , n10726 );
not ( n10731 , n10727 );
and ( n10732 , n10730 , n10731 );
nor ( n10733 , n10729 , n10732 );
xor ( n10734 , n10724 , n10733 );
buf ( n10735 , n4978 );
nand ( n10736 , n6605 , n10735 );
buf ( n10737 , n4979 );
not ( n10738 , n10737 );
and ( n10739 , n10736 , n10738 );
not ( n10740 , n10736 );
buf ( n10741 , n10737 );
and ( n10742 , n10740 , n10741 );
nor ( n10743 , n10739 , n10742 );
xnor ( n10744 , n10734 , n10743 );
not ( n10745 , n10744 );
or ( n10746 , n10706 , n10745 );
not ( n10747 , n10724 );
xor ( n10748 , n10747 , n10733 );
xnor ( n10749 , n10748 , n10743 );
not ( n10750 , n10704 );
nand ( n10751 , n10749 , n10750 );
nand ( n10752 , n10746 , n10751 );
not ( n10753 , n10752 );
not ( n10754 , n9067 );
or ( n10755 , n10753 , n10754 );
or ( n10756 , n9067 , n10752 );
nand ( n10757 , n10755 , n10756 );
buf ( n10758 , n4980 );
nand ( n10759 , n8454 , n10758 );
buf ( n10760 , n4981 );
buf ( n10761 , n10760 );
and ( n10762 , n10759 , n10761 );
not ( n10763 , n10759 );
not ( n10764 , n10760 );
and ( n10765 , n10763 , n10764 );
nor ( n10766 , n10762 , n10765 );
not ( n10767 , n10766 );
not ( n10768 , n8504 );
or ( n10769 , n10767 , n10768 );
or ( n10770 , n8504 , n10766 );
nand ( n10771 , n10769 , n10770 );
not ( n10772 , n10771 );
not ( n10773 , n8547 );
not ( n10774 , n10773 );
not ( n10775 , n10774 );
and ( n10776 , n10772 , n10775 );
and ( n10777 , n10771 , n10774 );
nor ( n10778 , n10776 , n10777 );
nand ( n10779 , n10757 , n10778 );
xor ( n10780 , n10703 , n10779 );
not ( n10781 , n10780 );
or ( n10782 , n10687 , n10781 );
or ( n10783 , n10780 , n10686 );
nand ( n10784 , n10782 , n10783 );
buf ( n10785 , n8721 );
buf ( n10786 , n4982 );
buf ( n10787 , n10786 );
not ( n10788 , n10787 );
buf ( n10789 , n4983 );
not ( n10790 , n10789 );
not ( n10791 , n10790 );
or ( n10792 , n10788 , n10791 );
not ( n10793 , n10786 );
buf ( n10794 , n10789 );
nand ( n10795 , n10793 , n10794 );
nand ( n10796 , n10792 , n10795 );
buf ( n10797 , n4984 );
buf ( n10798 , n10797 );
and ( n10799 , n10796 , n10798 );
not ( n10800 , n10796 );
not ( n10801 , n10797 );
and ( n10802 , n10800 , n10801 );
nor ( n10803 , n10799 , n10802 );
buf ( n10804 , n4985 );
nand ( n10805 , n6828 , n10804 );
buf ( n10806 , n4986 );
buf ( n10807 , n10806 );
and ( n10808 , n10805 , n10807 );
not ( n10809 , n10805 );
not ( n10810 , n10806 );
and ( n10811 , n10809 , n10810 );
nor ( n10812 , n10808 , n10811 );
xor ( n10813 , n10803 , n10812 );
buf ( n10814 , n4987 );
nand ( n10815 , n7344 , n10814 );
buf ( n10816 , n4988 );
buf ( n10817 , n10816 );
and ( n10818 , n10815 , n10817 );
not ( n10819 , n10815 );
not ( n10820 , n10816 );
and ( n10821 , n10819 , n10820 );
nor ( n10822 , n10818 , n10821 );
not ( n10823 , n10822 );
xnor ( n10824 , n10813 , n10823 );
not ( n10825 , n10824 );
not ( n10826 , n10825 );
xor ( n10827 , n10785 , n10826 );
buf ( n10828 , n4989 );
buf ( n10829 , n10828 );
buf ( n10830 , n4990 );
buf ( n10831 , n10830 );
not ( n10832 , n10831 );
buf ( n10833 , n4991 );
not ( n10834 , n10833 );
not ( n10835 , n10834 );
or ( n10836 , n10832 , n10835 );
not ( n10837 , n10830 );
buf ( n10838 , n10833 );
nand ( n10839 , n10837 , n10838 );
nand ( n10840 , n10836 , n10839 );
xor ( n10841 , n10829 , n10840 );
buf ( n10842 , n4992 );
buf ( n10843 , n10842 );
buf ( n10844 , n4993 );
xor ( n10845 , n10843 , n10844 );
buf ( n10846 , n4994 );
nand ( n10847 , n7569 , n10846 );
xnor ( n10848 , n10845 , n10847 );
xnor ( n10849 , n10841 , n10848 );
not ( n10850 , n10849 );
not ( n10851 , n10850 );
xnor ( n10852 , n10827 , n10851 );
not ( n10853 , n10852 );
buf ( n10854 , n4995 );
buf ( n10855 , n10854 );
not ( n10856 , n10855 );
not ( n10857 , n8619 );
or ( n10858 , n10856 , n10857 );
not ( n10859 , n8620 );
not ( n10860 , n10854 );
nand ( n10861 , n10859 , n10860 );
nand ( n10862 , n10858 , n10861 );
not ( n10863 , n10862 );
buf ( n10864 , n8662 );
not ( n10865 , n10864 );
not ( n10866 , n10865 );
and ( n10867 , n10863 , n10866 );
and ( n10868 , n10862 , n10865 );
nor ( n10869 , n10867 , n10868 );
not ( n10870 , n10869 );
nand ( n10871 , n10853 , n10870 );
buf ( n10872 , n4996 );
not ( n10873 , n10872 );
buf ( n10874 , n8176 );
buf ( n10875 , n4997 );
nand ( n10876 , n10874 , n10875 );
buf ( n10877 , n10876 );
not ( n10878 , n10877 );
or ( n10879 , n10873 , n10878 );
or ( n10880 , n10877 , n10872 );
nand ( n10881 , n10879 , n10880 );
not ( n10882 , n10881 );
buf ( n10883 , n4998 );
buf ( n10884 , n10883 );
not ( n10885 , n10884 );
buf ( n10886 , n4999 );
not ( n10887 , n10886 );
not ( n10888 , n10887 );
or ( n10889 , n10885 , n10888 );
not ( n10890 , n10883 );
buf ( n10891 , n10886 );
nand ( n10892 , n10890 , n10891 );
nand ( n10893 , n10889 , n10892 );
buf ( n10894 , n5000 );
buf ( n10895 , n10894 );
and ( n10896 , n10893 , n10895 );
not ( n10897 , n10893 );
not ( n10898 , n10894 );
and ( n10899 , n10897 , n10898 );
nor ( n10900 , n10896 , n10899 );
buf ( n10901 , n5001 );
nand ( n10902 , n7293 , n10901 );
buf ( n10903 , n5002 );
buf ( n10904 , n10903 );
and ( n10905 , n10902 , n10904 );
not ( n10906 , n10902 );
not ( n10907 , n10903 );
and ( n10908 , n10906 , n10907 );
nor ( n10909 , n10905 , n10908 );
xor ( n10910 , n10900 , n10909 );
xnor ( n10911 , n10910 , n9196 );
buf ( n10912 , n10911 );
not ( n10913 , n10912 );
or ( n10914 , n10882 , n10913 );
not ( n10915 , n10881 );
not ( n10916 , n10911 );
nand ( n10917 , n10915 , n10916 );
nand ( n10918 , n10914 , n10917 );
buf ( n10919 , n5003 );
buf ( n10920 , n10919 );
not ( n10921 , n10920 );
buf ( n10922 , n5004 );
not ( n10923 , n10922 );
not ( n10924 , n10923 );
or ( n10925 , n10921 , n10924 );
not ( n10926 , n10919 );
buf ( n10927 , n10922 );
nand ( n10928 , n10926 , n10927 );
nand ( n10929 , n10925 , n10928 );
buf ( n10930 , n5005 );
buf ( n10931 , n10930 );
and ( n10932 , n10929 , n10931 );
not ( n10933 , n10929 );
not ( n10934 , n10930 );
and ( n10935 , n10933 , n10934 );
nor ( n10936 , n10932 , n10935 );
buf ( n10937 , n5006 );
nand ( n10938 , n7202 , n10937 );
buf ( n10939 , n5007 );
buf ( n10940 , n10939 );
and ( n10941 , n10938 , n10940 );
not ( n10942 , n10938 );
not ( n10943 , n10939 );
and ( n10944 , n10942 , n10943 );
nor ( n10945 , n10941 , n10944 );
xor ( n10946 , n10936 , n10945 );
buf ( n10947 , n9160 );
buf ( n10948 , n5008 );
nand ( n10949 , n10947 , n10948 );
buf ( n10950 , n5009 );
buf ( n10951 , n10950 );
and ( n10952 , n10949 , n10951 );
not ( n10953 , n10949 );
not ( n10954 , n10950 );
and ( n10955 , n10953 , n10954 );
nor ( n10956 , n10952 , n10955 );
xnor ( n10957 , n10946 , n10956 );
buf ( n10958 , n10957 );
buf ( n10959 , n10958 );
not ( n10960 , n10959 );
and ( n10961 , n10918 , n10960 );
not ( n10962 , n10918 );
and ( n10963 , n10962 , n10959 );
nor ( n10964 , n10961 , n10963 );
buf ( n10965 , n10964 );
not ( n10966 , n10965 );
and ( n10967 , n10871 , n10966 );
not ( n10968 , n10871 );
and ( n10969 , n10968 , n10965 );
nor ( n10970 , n10967 , n10969 );
and ( n10971 , n10784 , n10970 );
not ( n10972 , n10784 );
not ( n10973 , n10970 );
and ( n10974 , n10972 , n10973 );
nor ( n10975 , n10971 , n10974 );
not ( n10976 , n10975 );
not ( n10977 , n10976 );
buf ( n10978 , n5010 );
not ( n10979 , n9655 );
buf ( n10980 , n5011 );
not ( n10981 , n10980 );
not ( n10982 , n10981 );
or ( n10983 , n10979 , n10982 );
not ( n10984 , n9654 );
buf ( n10985 , n10980 );
nand ( n10986 , n10984 , n10985 );
nand ( n10987 , n10983 , n10986 );
buf ( n10988 , n5012 );
buf ( n10989 , n10988 );
and ( n10990 , n10987 , n10989 );
not ( n10991 , n10987 );
not ( n10992 , n10988 );
and ( n10993 , n10991 , n10992 );
nor ( n10994 , n10990 , n10993 );
buf ( n10995 , n5013 );
nand ( n10996 , n6634 , n10995 );
buf ( n10997 , n5014 );
buf ( n10998 , n10997 );
and ( n10999 , n10996 , n10998 );
not ( n11000 , n10996 );
not ( n11001 , n10997 );
and ( n11002 , n11000 , n11001 );
nor ( n11003 , n10999 , n11002 );
xor ( n11004 , n10994 , n11003 );
buf ( n11005 , n5015 );
nand ( n11006 , n7247 , n11005 );
buf ( n11007 , n5016 );
buf ( n11008 , n11007 );
and ( n11009 , n11006 , n11008 );
not ( n11010 , n11006 );
not ( n11011 , n11007 );
and ( n11012 , n11010 , n11011 );
nor ( n11013 , n11009 , n11012 );
not ( n11014 , n11013 );
xnor ( n11015 , n11004 , n11014 );
xor ( n11016 , n10978 , n11015 );
buf ( n11017 , n5017 );
buf ( n11018 , n11017 );
not ( n11019 , n11018 );
buf ( n11020 , n5018 );
not ( n11021 , n11020 );
not ( n11022 , n11021 );
or ( n11023 , n11019 , n11022 );
not ( n11024 , n11017 );
buf ( n11025 , n11020 );
nand ( n11026 , n11024 , n11025 );
nand ( n11027 , n11023 , n11026 );
buf ( n11028 , n5019 );
buf ( n11029 , n11028 );
and ( n11030 , n11027 , n11029 );
not ( n11031 , n11027 );
not ( n11032 , n11028 );
and ( n11033 , n11031 , n11032 );
nor ( n11034 , n11030 , n11033 );
buf ( n11035 , n5020 );
nand ( n11036 , n7107 , n11035 );
buf ( n11037 , n5021 );
buf ( n11038 , n11037 );
and ( n11039 , n11036 , n11038 );
not ( n11040 , n11036 );
not ( n11041 , n11037 );
and ( n11042 , n11040 , n11041 );
nor ( n11043 , n11039 , n11042 );
xor ( n11044 , n11034 , n11043 );
buf ( n11045 , n5022 );
nand ( n11046 , n8675 , n11045 );
buf ( n11047 , n5023 );
buf ( n11048 , n11047 );
and ( n11049 , n11046 , n11048 );
not ( n11050 , n11046 );
not ( n11051 , n11047 );
and ( n11052 , n11050 , n11051 );
nor ( n11053 , n11049 , n11052 );
xnor ( n11054 , n11044 , n11053 );
not ( n11055 , n11054 );
xnor ( n11056 , n11016 , n11055 );
not ( n11057 , n11056 );
not ( n11058 , n11057 );
buf ( n11059 , n5024 );
buf ( n11060 , n11059 );
not ( n11061 , n11060 );
buf ( n11062 , n5025 );
not ( n11063 , n11062 );
buf ( n11064 , n5026 );
buf ( n11065 , n11064 );
not ( n11066 , n11065 );
buf ( n11067 , n5027 );
not ( n11068 , n11067 );
not ( n11069 , n11068 );
or ( n11070 , n11066 , n11069 );
not ( n11071 , n11064 );
buf ( n11072 , n11067 );
nand ( n11073 , n11071 , n11072 );
nand ( n11074 , n11070 , n11073 );
xor ( n11075 , n11063 , n11074 );
buf ( n11076 , n5028 );
buf ( n11077 , n5029 );
xor ( n11078 , n11076 , n11077 );
buf ( n11079 , n5030 );
nand ( n11080 , n7197 , n11079 );
xnor ( n11081 , n11078 , n11080 );
xor ( n11082 , n11075 , n11081 );
not ( n11083 , n11082 );
or ( n11084 , n11061 , n11083 );
or ( n11085 , n11082 , n11060 );
nand ( n11086 , n11084 , n11085 );
not ( n11087 , n11086 );
not ( n11088 , n6937 );
not ( n11089 , n11088 );
not ( n11090 , n11089 );
and ( n11091 , n11087 , n11090 );
and ( n11092 , n11086 , n11089 );
nor ( n11093 , n11091 , n11092 );
not ( n11094 , n11093 );
nand ( n11095 , n11058 , n11094 );
not ( n11096 , n11095 );
not ( n11097 , n8079 );
not ( n11098 , n6730 );
or ( n11099 , n11097 , n11098 );
or ( n11100 , n6730 , n8079 );
nand ( n11101 , n11099 , n11100 );
not ( n11102 , n11101 );
xor ( n11103 , n6668 , n6677 );
xnor ( n11104 , n11103 , n6684 );
not ( n11105 , n11104 );
not ( n11106 , n11105 );
or ( n11107 , n11102 , n11106 );
not ( n11108 , n6685 );
or ( n11109 , n11108 , n11101 );
nand ( n11110 , n11107 , n11109 );
buf ( n11111 , n11110 );
not ( n11112 , n11111 );
and ( n11113 , n11096 , n11112 );
and ( n11114 , n11095 , n11111 );
nor ( n11115 , n11113 , n11114 );
not ( n11116 , n11115 );
buf ( n11117 , n10392 );
not ( n11118 , n11117 );
not ( n11119 , n7808 );
xor ( n11120 , n11119 , n7820 );
xor ( n11121 , n11120 , n7827 );
not ( n11122 , n11121 );
not ( n11123 , n11122 );
or ( n11124 , n11118 , n11123 );
or ( n11125 , n11122 , n11117 );
nand ( n11126 , n11124 , n11125 );
buf ( n11127 , n5031 );
buf ( n11128 , n11127 );
not ( n11129 , n11128 );
buf ( n11130 , n5032 );
not ( n11131 , n11130 );
not ( n11132 , n11131 );
or ( n11133 , n11129 , n11132 );
not ( n11134 , n11127 );
buf ( n11135 , n11130 );
nand ( n11136 , n11134 , n11135 );
nand ( n11137 , n11133 , n11136 );
not ( n11138 , n9745 );
and ( n11139 , n11137 , n11138 );
not ( n11140 , n11137 );
and ( n11141 , n11140 , n9746 );
nor ( n11142 , n11139 , n11141 );
xor ( n11143 , n11142 , n10692 );
buf ( n11144 , n5033 );
nand ( n11145 , n10570 , n11144 );
buf ( n11146 , n5034 );
not ( n11147 , n11146 );
and ( n11148 , n11145 , n11147 );
not ( n11149 , n11145 );
buf ( n11150 , n11146 );
and ( n11151 , n11149 , n11150 );
nor ( n11152 , n11148 , n11151 );
xnor ( n11153 , n11143 , n11152 );
buf ( n11154 , n11153 );
buf ( n11155 , n11154 );
not ( n11156 , n11155 );
and ( n11157 , n11126 , n11156 );
not ( n11158 , n11126 );
and ( n11159 , n11158 , n11155 );
nor ( n11160 , n11157 , n11159 );
not ( n11161 , n11160 );
not ( n11162 , n9462 );
not ( n11163 , n11162 );
buf ( n11164 , n5035 );
not ( n11165 , n11164 );
buf ( n11166 , n5036 );
nand ( n11167 , n7912 , n11166 );
not ( n11168 , n11167 );
or ( n11169 , n11165 , n11168 );
nand ( n11170 , n8070 , n11166 );
or ( n11171 , n11170 , n11164 );
nand ( n11172 , n11169 , n11171 );
not ( n11173 , n11172 );
not ( n11174 , n9419 );
not ( n11175 , n11174 );
not ( n11176 , n11175 );
or ( n11177 , n11173 , n11176 );
not ( n11178 , n11172 );
nand ( n11179 , n11174 , n11178 );
nand ( n11180 , n11177 , n11179 );
not ( n11181 , n11180 );
or ( n11182 , n11163 , n11181 );
or ( n11183 , n11180 , n9465 );
nand ( n11184 , n11182 , n11183 );
not ( n11185 , n11184 );
buf ( n11186 , n5037 );
buf ( n11187 , n11186 );
not ( n11188 , n11187 );
buf ( n11189 , n5038 );
buf ( n11190 , n11189 );
not ( n11191 , n11190 );
buf ( n11192 , n5039 );
not ( n11193 , n11192 );
not ( n11194 , n11193 );
or ( n11195 , n11191 , n11194 );
not ( n11196 , n11189 );
buf ( n11197 , n11192 );
nand ( n11198 , n11196 , n11197 );
nand ( n11199 , n11195 , n11198 );
buf ( n11200 , n5040 );
not ( n11201 , n11200 );
and ( n11202 , n11199 , n11201 );
not ( n11203 , n11199 );
buf ( n11204 , n11200 );
and ( n11205 , n11203 , n11204 );
nor ( n11206 , n11202 , n11205 );
buf ( n11207 , n5041 );
nand ( n11208 , n6604 , n11207 );
buf ( n11209 , n5042 );
buf ( n11210 , n11209 );
and ( n11211 , n11208 , n11210 );
not ( n11212 , n11208 );
not ( n11213 , n11209 );
and ( n11214 , n11212 , n11213 );
nor ( n11215 , n11211 , n11214 );
xor ( n11216 , n11206 , n11215 );
buf ( n11217 , n5043 );
nand ( n11218 , n8375 , n11217 );
buf ( n11219 , n5044 );
not ( n11220 , n11219 );
and ( n11221 , n11218 , n11220 );
not ( n11222 , n11218 );
buf ( n11223 , n11219 );
and ( n11224 , n11222 , n11223 );
nor ( n11225 , n11221 , n11224 );
xnor ( n11226 , n11216 , n11225 );
not ( n11227 , n11226 );
not ( n11228 , n11227 );
not ( n11229 , n11228 );
or ( n11230 , n11188 , n11229 );
not ( n11231 , n11187 );
nand ( n11232 , n11231 , n11227 );
nand ( n11233 , n11230 , n11232 );
buf ( n11234 , n5045 );
buf ( n11235 , n11234 );
not ( n11236 , n11235 );
buf ( n11237 , n5046 );
not ( n11238 , n11237 );
not ( n11239 , n11238 );
or ( n11240 , n11236 , n11239 );
not ( n11241 , n11234 );
buf ( n11242 , n11237 );
nand ( n11243 , n11241 , n11242 );
nand ( n11244 , n11240 , n11243 );
buf ( n11245 , n5047 );
buf ( n11246 , n11245 );
and ( n11247 , n11244 , n11246 );
not ( n11248 , n11244 );
not ( n11249 , n11245 );
and ( n11250 , n11248 , n11249 );
nor ( n11251 , n11247 , n11250 );
buf ( n11252 , n5048 );
nand ( n11253 , n8454 , n11252 );
buf ( n11254 , n5049 );
buf ( n11255 , n11254 );
and ( n11256 , n11253 , n11255 );
not ( n11257 , n11253 );
not ( n11258 , n11254 );
and ( n11259 , n11257 , n11258 );
nor ( n11260 , n11256 , n11259 );
xor ( n11261 , n11251 , n11260 );
buf ( n11262 , n5050 );
nand ( n11263 , n9310 , n11262 );
buf ( n11264 , n5051 );
buf ( n11265 , n11264 );
and ( n11266 , n11263 , n11265 );
not ( n11267 , n11263 );
not ( n11268 , n11264 );
and ( n11269 , n11267 , n11268 );
nor ( n11270 , n11266 , n11269 );
xnor ( n11271 , n11261 , n11270 );
buf ( n11272 , n11271 );
and ( n11273 , n11233 , n11272 );
not ( n11274 , n11233 );
not ( n11275 , n11272 );
and ( n11276 , n11274 , n11275 );
nor ( n11277 , n11273 , n11276 );
not ( n11278 , n11277 );
nand ( n11279 , n11185 , n11278 );
not ( n11280 , n11279 );
or ( n11281 , n11161 , n11280 );
or ( n11282 , n11279 , n11160 );
nand ( n11283 , n11281 , n11282 );
not ( n11284 , n11283 );
and ( n11285 , n11116 , n11284 );
and ( n11286 , n11115 , n11283 );
nor ( n11287 , n11285 , n11286 );
not ( n11288 , n11287 );
not ( n11289 , n11288 );
and ( n11290 , n10977 , n11289 );
and ( n11291 , n10976 , n11288 );
nor ( n11292 , n11290 , n11291 );
buf ( n11293 , n11292 );
and ( n11294 , n10474 , n11293 );
not ( n11295 , n10474 );
not ( n11296 , n11287 );
not ( n11297 , n10975 );
or ( n11298 , n11296 , n11297 );
not ( n11299 , n11287 );
nand ( n11300 , n11299 , n10976 );
nand ( n11301 , n11298 , n11300 );
buf ( n11302 , n11301 );
and ( n11303 , n11295 , n11302 );
nor ( n11304 , n11294 , n11303 );
xor ( n11305 , n8245 , n8254 );
xnor ( n11306 , n11305 , n8263 );
buf ( n11307 , n11306 );
not ( n11308 , n8517 );
buf ( n11309 , n5052 );
buf ( n11310 , n11309 );
not ( n11311 , n11310 );
buf ( n11312 , n5053 );
not ( n11313 , n11312 );
not ( n11314 , n11313 );
or ( n11315 , n11311 , n11314 );
not ( n11316 , n11309 );
buf ( n11317 , n11312 );
nand ( n11318 , n11316 , n11317 );
nand ( n11319 , n11315 , n11318 );
buf ( n11320 , n5054 );
buf ( n11321 , n11320 );
and ( n11322 , n11319 , n11321 );
not ( n11323 , n11319 );
not ( n11324 , n11320 );
and ( n11325 , n11323 , n11324 );
nor ( n11326 , n11322 , n11325 );
buf ( n11327 , n5055 );
nand ( n11328 , n7202 , n11327 );
buf ( n11329 , n5056 );
not ( n11330 , n11329 );
and ( n11331 , n11328 , n11330 );
not ( n11332 , n11328 );
buf ( n11333 , n11329 );
and ( n11334 , n11332 , n11333 );
nor ( n11335 , n11331 , n11334 );
xor ( n11336 , n11326 , n11335 );
buf ( n11337 , n7606 );
buf ( n11338 , n5057 );
nand ( n11339 , n11337 , n11338 );
buf ( n11340 , n5058 );
not ( n11341 , n11340 );
and ( n11342 , n11339 , n11341 );
not ( n11343 , n11339 );
buf ( n11344 , n11340 );
and ( n11345 , n11343 , n11344 );
nor ( n11346 , n11342 , n11345 );
xnor ( n11347 , n11336 , n11346 );
buf ( n11348 , n11347 );
not ( n11349 , n11348 );
or ( n11350 , n11308 , n11349 );
or ( n11351 , n11348 , n8517 );
nand ( n11352 , n11350 , n11351 );
and ( n11353 , n11307 , n11352 );
not ( n11354 , n11307 );
not ( n11355 , n11352 );
and ( n11356 , n11354 , n11355 );
nor ( n11357 , n11353 , n11356 );
buf ( n11358 , n5059 );
nand ( n11359 , n10947 , n11358 );
buf ( n11360 , n5060 );
not ( n11361 , n11360 );
and ( n11362 , n11359 , n11361 );
not ( n11363 , n11359 );
buf ( n11364 , n11360 );
and ( n11365 , n11363 , n11364 );
nor ( n11366 , n11362 , n11365 );
not ( n11367 , n11366 );
buf ( n11368 , n5061 );
buf ( n11369 , n11368 );
not ( n11370 , n11369 );
not ( n11371 , n6845 );
or ( n11372 , n11370 , n11371 );
not ( n11373 , n11368 );
nand ( n11374 , n11373 , n6795 );
nand ( n11375 , n11372 , n11374 );
buf ( n11376 , n5062 );
buf ( n11377 , n11376 );
and ( n11378 , n11375 , n11377 );
not ( n11379 , n11375 );
not ( n11380 , n11376 );
and ( n11381 , n11379 , n11380 );
nor ( n11382 , n11378 , n11381 );
buf ( n11383 , n5063 );
nand ( n11384 , n6927 , n11383 );
buf ( n11385 , n5064 );
buf ( n11386 , n11385 );
and ( n11387 , n11384 , n11386 );
not ( n11388 , n11384 );
not ( n11389 , n11385 );
and ( n11390 , n11388 , n11389 );
nor ( n11391 , n11387 , n11390 );
xor ( n11392 , n11382 , n11391 );
xor ( n11393 , n11392 , n8332 );
buf ( n11394 , n11393 );
not ( n11395 , n11394 );
or ( n11396 , n11367 , n11395 );
or ( n11397 , n11366 , n11394 );
nand ( n11398 , n11396 , n11397 );
buf ( n11399 , n5065 );
buf ( n11400 , n11399 );
not ( n11401 , n11400 );
buf ( n11402 , n5066 );
not ( n11403 , n11402 );
not ( n11404 , n11403 );
or ( n11405 , n11401 , n11404 );
not ( n11406 , n11399 );
buf ( n11407 , n11402 );
nand ( n11408 , n11406 , n11407 );
nand ( n11409 , n11405 , n11408 );
buf ( n11410 , n5067 );
not ( n11411 , n11410 );
and ( n11412 , n11409 , n11411 );
not ( n11413 , n11409 );
buf ( n11414 , n11410 );
and ( n11415 , n11413 , n11414 );
nor ( n11416 , n11412 , n11415 );
buf ( n11417 , n5068 );
nand ( n11418 , n9812 , n11417 );
buf ( n11419 , n5069 );
buf ( n11420 , n11419 );
and ( n11421 , n11418 , n11420 );
not ( n11422 , n11418 );
not ( n11423 , n11419 );
and ( n11424 , n11422 , n11423 );
nor ( n11425 , n11421 , n11424 );
xor ( n11426 , n11416 , n11425 );
buf ( n11427 , n5070 );
nand ( n11428 , n11337 , n11427 );
buf ( n11429 , n5071 );
not ( n11430 , n11429 );
and ( n11431 , n11428 , n11430 );
not ( n11432 , n11428 );
buf ( n11433 , n11429 );
and ( n11434 , n11432 , n11433 );
nor ( n11435 , n11431 , n11434 );
xnor ( n11436 , n11426 , n11435 );
buf ( n11437 , n11436 );
buf ( n11438 , n11437 );
and ( n11439 , n11398 , n11438 );
not ( n11440 , n11398 );
not ( n11441 , n11438 );
and ( n11442 , n11440 , n11441 );
nor ( n11443 , n11439 , n11442 );
nand ( n11444 , n11357 , n11443 );
not ( n11445 , n11444 );
buf ( n11446 , n5072 );
nand ( n11447 , n6515 , n11446 );
buf ( n11448 , n5073 );
buf ( n11449 , n11448 );
and ( n11450 , n11447 , n11449 );
not ( n11451 , n11447 );
not ( n11452 , n11448 );
and ( n11453 , n11451 , n11452 );
nor ( n11454 , n11450 , n11453 );
not ( n11455 , n11454 );
not ( n11456 , n11455 );
not ( n11457 , n7411 );
or ( n11458 , n11456 , n11457 );
not ( n11459 , n11455 );
not ( n11460 , n7411 );
nand ( n11461 , n11459 , n11460 );
nand ( n11462 , n11458 , n11461 );
buf ( n11463 , n5074 );
buf ( n11464 , n11463 );
not ( n11465 , n11464 );
buf ( n11466 , n5075 );
not ( n11467 , n11466 );
not ( n11468 , n11467 );
or ( n11469 , n11465 , n11468 );
not ( n11470 , n11463 );
buf ( n11471 , n11466 );
nand ( n11472 , n11470 , n11471 );
nand ( n11473 , n11469 , n11472 );
buf ( n11474 , n5076 );
not ( n11475 , n11474 );
and ( n11476 , n11473 , n11475 );
not ( n11477 , n11473 );
buf ( n11478 , n11474 );
and ( n11479 , n11477 , n11478 );
nor ( n11480 , n11476 , n11479 );
buf ( n11481 , n5077 );
nand ( n11482 , n7787 , n11481 );
buf ( n11483 , n5078 );
not ( n11484 , n11483 );
and ( n11485 , n11482 , n11484 );
not ( n11486 , n11482 );
buf ( n11487 , n11483 );
and ( n11488 , n11486 , n11487 );
nor ( n11489 , n11485 , n11488 );
xor ( n11490 , n11480 , n11489 );
buf ( n11491 , n5079 );
nand ( n11492 , n7247 , n11491 );
buf ( n11493 , n5080 );
buf ( n11494 , n11493 );
and ( n11495 , n11492 , n11494 );
not ( n11496 , n11492 );
not ( n11497 , n11493 );
and ( n11498 , n11496 , n11497 );
nor ( n11499 , n11495 , n11498 );
xor ( n11500 , n11490 , n11499 );
not ( n11501 , n11500 );
buf ( n11502 , n11501 );
not ( n11503 , n11502 );
and ( n11504 , n11462 , n11503 );
not ( n11505 , n11462 );
not ( n11506 , n11500 );
buf ( n11507 , n11506 );
not ( n11508 , n11507 );
not ( n11509 , n11508 );
and ( n11510 , n11505 , n11509 );
nor ( n11511 , n11504 , n11510 );
not ( n11512 , n11511 );
not ( n11513 , n11512 );
not ( n11514 , n11513 );
and ( n11515 , n11445 , n11514 );
and ( n11516 , n11444 , n11513 );
nor ( n11517 , n11515 , n11516 );
not ( n11518 , n11517 );
not ( n11519 , n11518 );
buf ( n11520 , n5081 );
nand ( n11521 , n8675 , n11520 );
buf ( n11522 , n5082 );
not ( n11523 , n11522 );
and ( n11524 , n11521 , n11523 );
not ( n11525 , n11521 );
buf ( n11526 , n11522 );
and ( n11527 , n11525 , n11526 );
nor ( n11528 , n11524 , n11527 );
buf ( n11529 , n5083 );
buf ( n11530 , n5084 );
not ( n11531 , n11530 );
nand ( n11532 , n11531 , n7324 );
not ( n11533 , n7323 );
buf ( n11534 , n11530 );
nand ( n11535 , n11533 , n11534 );
and ( n11536 , n11532 , n11535 );
xor ( n11537 , n11529 , n11536 );
buf ( n11538 , n5085 );
buf ( n11539 , n5086 );
xor ( n11540 , n11538 , n11539 );
buf ( n11541 , n5087 );
nand ( n11542 , n7709 , n11541 );
xnor ( n11543 , n11540 , n11542 );
xnor ( n11544 , n11537 , n11543 );
xor ( n11545 , n11528 , n11544 );
buf ( n11546 , n5088 );
buf ( n11547 , n11546 );
not ( n11548 , n11547 );
buf ( n11549 , n5089 );
not ( n11550 , n11549 );
not ( n11551 , n11550 );
or ( n11552 , n11548 , n11551 );
not ( n11553 , n11546 );
buf ( n11554 , n11549 );
nand ( n11555 , n11553 , n11554 );
nand ( n11556 , n11552 , n11555 );
buf ( n11557 , n5090 );
not ( n11558 , n11557 );
and ( n11559 , n11556 , n11558 );
not ( n11560 , n11556 );
buf ( n11561 , n11557 );
and ( n11562 , n11560 , n11561 );
nor ( n11563 , n11559 , n11562 );
xor ( n11564 , n11563 , n11454 );
buf ( n11565 , n5091 );
nand ( n11566 , n6647 , n11565 );
buf ( n11567 , n5092 );
buf ( n11568 , n11567 );
and ( n11569 , n11566 , n11568 );
not ( n11570 , n11566 );
not ( n11571 , n11567 );
and ( n11572 , n11570 , n11571 );
nor ( n11573 , n11569 , n11572 );
not ( n11574 , n11573 );
xnor ( n11575 , n11564 , n11574 );
xnor ( n11576 , n11545 , n11575 );
not ( n11577 , n11576 );
not ( n11578 , n7466 );
buf ( n11579 , n5093 );
buf ( n11580 , n11579 );
not ( n11581 , n11580 );
buf ( n11582 , n5094 );
not ( n11583 , n11582 );
not ( n11584 , n11583 );
or ( n11585 , n11581 , n11584 );
not ( n11586 , n11579 );
buf ( n11587 , n11582 );
nand ( n11588 , n11586 , n11587 );
nand ( n11589 , n11585 , n11588 );
not ( n11590 , n9005 );
and ( n11591 , n11589 , n11590 );
not ( n11592 , n11589 );
and ( n11593 , n11592 , n9006 );
nor ( n11594 , n11591 , n11593 );
buf ( n11595 , n5095 );
nand ( n11596 , n6633 , n11595 );
buf ( n11597 , n5096 );
buf ( n11598 , n11597 );
and ( n11599 , n11596 , n11598 );
not ( n11600 , n11596 );
not ( n11601 , n11597 );
and ( n11602 , n11600 , n11601 );
nor ( n11603 , n11599 , n11602 );
xor ( n11604 , n11594 , n11603 );
buf ( n11605 , n5097 );
nand ( n11606 , n8781 , n11605 );
buf ( n11607 , n5098 );
not ( n11608 , n11607 );
and ( n11609 , n11606 , n11608 );
not ( n11610 , n11606 );
buf ( n11611 , n11607 );
and ( n11612 , n11610 , n11611 );
nor ( n11613 , n11609 , n11612 );
xnor ( n11614 , n11604 , n11613 );
not ( n11615 , n11614 );
not ( n11616 , n11615 );
or ( n11617 , n11578 , n11616 );
or ( n11618 , n11615 , n7466 );
nand ( n11619 , n11617 , n11618 );
buf ( n11620 , n9235 );
and ( n11621 , n11619 , n11620 );
not ( n11622 , n11619 );
not ( n11623 , n11620 );
and ( n11624 , n11622 , n11623 );
nor ( n11625 , n11621 , n11624 );
not ( n11626 , n11625 );
nand ( n11627 , n11577 , n11626 );
buf ( n11628 , n5099 );
not ( n11629 , n11628 );
buf ( n11630 , n5100 );
nand ( n11631 , n7293 , n11630 );
buf ( n11632 , n5101 );
buf ( n11633 , n11632 );
and ( n11634 , n11631 , n11633 );
not ( n11635 , n11631 );
not ( n11636 , n11632 );
and ( n11637 , n11635 , n11636 );
nor ( n11638 , n11634 , n11637 );
not ( n11639 , n11638 );
buf ( n11640 , n5102 );
nand ( n11641 , n8070 , n11640 );
buf ( n11642 , n5103 );
not ( n11643 , n11642 );
and ( n11644 , n11641 , n11643 );
not ( n11645 , n11641 );
buf ( n11646 , n11642 );
and ( n11647 , n11645 , n11646 );
nor ( n11648 , n11644 , n11647 );
not ( n11649 , n11648 );
or ( n11650 , n11639 , n11649 );
or ( n11651 , n11638 , n11648 );
nand ( n11652 , n11650 , n11651 );
buf ( n11653 , n5104 );
buf ( n11654 , n11653 );
not ( n11655 , n11654 );
buf ( n11656 , n5105 );
not ( n11657 , n11656 );
not ( n11658 , n11657 );
or ( n11659 , n11655 , n11658 );
not ( n11660 , n11653 );
buf ( n11661 , n11656 );
nand ( n11662 , n11660 , n11661 );
nand ( n11663 , n11659 , n11662 );
buf ( n11664 , n5106 );
buf ( n11665 , n11664 );
and ( n11666 , n11663 , n11665 );
not ( n11667 , n11663 );
not ( n11668 , n11664 );
and ( n11669 , n11667 , n11668 );
nor ( n11670 , n11666 , n11669 );
not ( n11671 , n11670 );
xor ( n11672 , n11652 , n11671 );
not ( n11673 , n11672 );
or ( n11674 , n11629 , n11673 );
or ( n11675 , n11672 , n11628 );
nand ( n11676 , n11674 , n11675 );
not ( n11677 , n11676 );
buf ( n11678 , n5107 );
nand ( n11679 , n8781 , n11678 );
buf ( n11680 , n5108 );
buf ( n11681 , n11680 );
and ( n11682 , n11679 , n11681 );
not ( n11683 , n11679 );
not ( n11684 , n11680 );
and ( n11685 , n11683 , n11684 );
nor ( n11686 , n11682 , n11685 );
not ( n11687 , n11686 );
buf ( n11688 , n7293 );
buf ( n11689 , n5109 );
nand ( n11690 , n11688 , n11689 );
buf ( n11691 , n5110 );
not ( n11692 , n11691 );
and ( n11693 , n11690 , n11692 );
not ( n11694 , n11690 );
buf ( n11695 , n11691 );
and ( n11696 , n11694 , n11695 );
nor ( n11697 , n11693 , n11696 );
not ( n11698 , n11697 );
or ( n11699 , n11687 , n11698 );
or ( n11700 , n11686 , n11697 );
nand ( n11701 , n11699 , n11700 );
buf ( n11702 , n5111 );
buf ( n11703 , n11702 );
not ( n11704 , n11703 );
buf ( n11705 , n5112 );
not ( n11706 , n11705 );
not ( n11707 , n11706 );
or ( n11708 , n11704 , n11707 );
not ( n11709 , n11702 );
buf ( n11710 , n11705 );
nand ( n11711 , n11709 , n11710 );
nand ( n11712 , n11708 , n11711 );
buf ( n11713 , n5113 );
not ( n11714 , n11713 );
and ( n11715 , n11712 , n11714 );
not ( n11716 , n11712 );
buf ( n11717 , n11713 );
and ( n11718 , n11716 , n11717 );
nor ( n11719 , n11715 , n11718 );
and ( n11720 , n11701 , n11719 );
not ( n11721 , n11701 );
not ( n11722 , n11719 );
and ( n11723 , n11721 , n11722 );
nor ( n11724 , n11720 , n11723 );
not ( n11725 , n11724 );
and ( n11726 , n11677 , n11725 );
buf ( n11727 , n11724 );
and ( n11728 , n11676 , n11727 );
nor ( n11729 , n11726 , n11728 );
not ( n11730 , n11729 );
xnor ( n11731 , n11627 , n11730 );
not ( n11732 , n11731 );
not ( n11733 , n11732 );
buf ( n11734 , n5114 );
buf ( n11735 , n5115 );
buf ( n11736 , n11735 );
not ( n11737 , n11736 );
buf ( n11738 , n5116 );
not ( n11739 , n11738 );
not ( n11740 , n11739 );
or ( n11741 , n11737 , n11740 );
not ( n11742 , n11735 );
buf ( n11743 , n11738 );
nand ( n11744 , n11742 , n11743 );
nand ( n11745 , n11741 , n11744 );
xor ( n11746 , n11734 , n11745 );
buf ( n11747 , n5117 );
buf ( n11748 , n5118 );
buf ( n11749 , n11748 );
xor ( n11750 , n11747 , n11749 );
buf ( n11751 , n5119 );
nand ( n11752 , n8675 , n11751 );
xnor ( n11753 , n11750 , n11752 );
not ( n11754 , n11753 );
xnor ( n11755 , n11746 , n11754 );
not ( n11756 , n11755 );
not ( n11757 , n7313 );
not ( n11758 , n11757 );
buf ( n11759 , n5120 );
nand ( n11760 , n8124 , n11759 );
buf ( n11761 , n5121 );
buf ( n11762 , n11761 );
and ( n11763 , n11760 , n11762 );
not ( n11764 , n11760 );
not ( n11765 , n11761 );
and ( n11766 , n11764 , n11765 );
nor ( n11767 , n11763 , n11766 );
buf ( n11768 , n11767 );
not ( n11769 , n11768 );
and ( n11770 , n11758 , n11769 );
and ( n11771 , n11757 , n11768 );
nor ( n11772 , n11770 , n11771 );
not ( n11773 , n11772 );
or ( n11774 , n11756 , n11773 );
buf ( n11775 , n11755 );
or ( n11776 , n11775 , n11772 );
nand ( n11777 , n11774 , n11776 );
not ( n11778 , n11777 );
buf ( n11779 , n5122 );
buf ( n11780 , n11779 );
not ( n11781 , n11780 );
buf ( n11782 , n5123 );
not ( n11783 , n11782 );
not ( n11784 , n11783 );
or ( n11785 , n11781 , n11784 );
not ( n11786 , n11779 );
buf ( n11787 , n11782 );
nand ( n11788 , n11786 , n11787 );
nand ( n11789 , n11785 , n11788 );
buf ( n11790 , n5124 );
buf ( n11791 , n11790 );
and ( n11792 , n11789 , n11791 );
not ( n11793 , n11789 );
not ( n11794 , n11790 );
and ( n11795 , n11793 , n11794 );
nor ( n11796 , n11792 , n11795 );
buf ( n11797 , n5125 );
buf ( n11798 , n5126 );
buf ( n11799 , n11798 );
not ( n11800 , n11799 );
buf ( n11801 , n5127 );
nand ( n11802 , n7912 , n11801 );
not ( n11803 , n11802 );
or ( n11804 , n11800 , n11803 );
not ( n11805 , n11798 );
nand ( n11806 , n6927 , n11805 , n11801 );
nand ( n11807 , n11804 , n11806 );
xor ( n11808 , n11797 , n11807 );
buf ( n11809 , n5128 );
nand ( n11810 , n7107 , n11809 );
buf ( n11811 , n5129 );
not ( n11812 , n11811 );
and ( n11813 , n11810 , n11812 );
not ( n11814 , n11810 );
buf ( n11815 , n11811 );
and ( n11816 , n11814 , n11815 );
nor ( n11817 , n11813 , n11816 );
xnor ( n11818 , n11808 , n11817 );
not ( n11819 , n11818 );
xor ( n11820 , n11796 , n11819 );
not ( n11821 , n11060 );
buf ( n11822 , n5130 );
not ( n11823 , n11822 );
not ( n11824 , n11823 );
or ( n11825 , n11821 , n11824 );
not ( n11826 , n11059 );
buf ( n11827 , n11822 );
nand ( n11828 , n11826 , n11827 );
nand ( n11829 , n11825 , n11828 );
buf ( n11830 , n5131 );
not ( n11831 , n11830 );
and ( n11832 , n11829 , n11831 );
not ( n11833 , n11829 );
buf ( n11834 , n11830 );
and ( n11835 , n11833 , n11834 );
nor ( n11836 , n11832 , n11835 );
buf ( n11837 , n5132 );
nand ( n11838 , n6828 , n11837 );
buf ( n11839 , n5133 );
buf ( n11840 , n11839 );
and ( n11841 , n11838 , n11840 );
not ( n11842 , n11838 );
not ( n11843 , n11839 );
and ( n11844 , n11842 , n11843 );
nor ( n11845 , n11841 , n11844 );
xor ( n11846 , n11836 , n11845 );
buf ( n11847 , n8954 );
buf ( n11848 , n5134 );
nand ( n11849 , n11847 , n11848 );
buf ( n11850 , n5135 );
not ( n11851 , n11850 );
and ( n11852 , n11849 , n11851 );
not ( n11853 , n11849 );
buf ( n11854 , n11850 );
and ( n11855 , n11853 , n11854 );
nor ( n11856 , n11852 , n11855 );
xnor ( n11857 , n11846 , n11856 );
not ( n11858 , n11857 );
xnor ( n11859 , n11820 , n11858 );
not ( n11860 , n11859 );
nand ( n11861 , n11778 , n11860 );
buf ( n11862 , n5136 );
buf ( n11863 , n11862 );
not ( n11864 , n11863 );
not ( n11865 , n11226 );
or ( n11866 , n11864 , n11865 );
or ( n11867 , n11226 , n11863 );
nand ( n11868 , n11866 , n11867 );
xor ( n11869 , n11868 , n11271 );
not ( n11870 , n11869 );
and ( n11871 , n11861 , n11870 );
not ( n11872 , n11861 );
and ( n11873 , n11872 , n11869 );
nor ( n11874 , n11871 , n11873 );
not ( n11875 , n11874 );
not ( n11876 , n11875 );
or ( n11877 , n11733 , n11876 );
nand ( n11878 , n11874 , n11731 );
nand ( n11879 , n11877 , n11878 );
buf ( n11880 , n5137 );
nand ( n11881 , n8537 , n11880 );
buf ( n11882 , n5138 );
buf ( n11883 , n11882 );
and ( n11884 , n11881 , n11883 );
not ( n11885 , n11881 );
not ( n11886 , n11882 );
and ( n11887 , n11885 , n11886 );
nor ( n11888 , n11884 , n11887 );
not ( n11889 , n9389 );
buf ( n11890 , n5139 );
not ( n11891 , n11890 );
not ( n11892 , n11891 );
or ( n11893 , n11889 , n11892 );
not ( n11894 , n9388 );
buf ( n11895 , n11890 );
nand ( n11896 , n11894 , n11895 );
nand ( n11897 , n11893 , n11896 );
not ( n11898 , n11897 );
buf ( n11899 , n5140 );
buf ( n11900 , n5141 );
nand ( n11901 , n8069 , n11900 );
not ( n11902 , n11901 );
buf ( n11903 , n5142 );
not ( n11904 , n11903 );
and ( n11905 , n11902 , n11904 );
nand ( n11906 , n7013 , n11900 );
and ( n11907 , n11906 , n11903 );
nor ( n11908 , n11905 , n11907 );
xor ( n11909 , n11899 , n11908 );
xnor ( n11910 , n11909 , n11172 );
not ( n11911 , n11910 );
not ( n11912 , n11911 );
or ( n11913 , n11898 , n11912 );
not ( n11914 , n11897 );
nand ( n11915 , n11910 , n11914 );
nand ( n11916 , n11913 , n11915 );
xor ( n11917 , n11888 , n11916 );
buf ( n11918 , n5143 );
buf ( n11919 , n11918 );
not ( n11920 , n11919 );
buf ( n11921 , n5144 );
not ( n11922 , n11921 );
not ( n11923 , n11922 );
or ( n11924 , n11920 , n11923 );
not ( n11925 , n11918 );
buf ( n11926 , n11921 );
nand ( n11927 , n11925 , n11926 );
nand ( n11928 , n11924 , n11927 );
buf ( n11929 , n5145 );
not ( n11930 , n11929 );
and ( n11931 , n11928 , n11930 );
not ( n11932 , n11928 );
buf ( n11933 , n11929 );
and ( n11934 , n11932 , n11933 );
nor ( n11935 , n11931 , n11934 );
buf ( n11936 , n5146 );
nand ( n11937 , n6770 , n11936 );
buf ( n11938 , n5147 );
buf ( n11939 , n11938 );
and ( n11940 , n11937 , n11939 );
not ( n11941 , n11937 );
not ( n11942 , n11938 );
and ( n11943 , n11941 , n11942 );
nor ( n11944 , n11940 , n11943 );
xor ( n11945 , n11935 , n11944 );
buf ( n11946 , n8454 );
buf ( n11947 , n5148 );
nand ( n11948 , n11946 , n11947 );
buf ( n11949 , n5149 );
not ( n11950 , n11949 );
and ( n11951 , n11948 , n11950 );
not ( n11952 , n11948 );
buf ( n11953 , n11949 );
and ( n11954 , n11952 , n11953 );
nor ( n11955 , n11951 , n11954 );
xnor ( n11956 , n11945 , n11955 );
buf ( n11957 , n11956 );
not ( n11958 , n11957 );
xnor ( n11959 , n11917 , n11958 );
not ( n11960 , n11959 );
buf ( n11961 , n5150 );
nand ( n11962 , n7202 , n11961 );
buf ( n11963 , n5151 );
buf ( n11964 , n11963 );
and ( n11965 , n11962 , n11964 );
not ( n11966 , n11962 );
not ( n11967 , n11963 );
and ( n11968 , n11966 , n11967 );
nor ( n11969 , n11965 , n11968 );
buf ( n11970 , n11969 );
not ( n11971 , n11970 );
not ( n11972 , n11971 );
buf ( n11973 , n5152 );
buf ( n11974 , n11973 );
not ( n11975 , n11974 );
buf ( n11976 , n5153 );
not ( n11977 , n11976 );
not ( n11978 , n11977 );
or ( n11979 , n11975 , n11978 );
not ( n11980 , n11973 );
buf ( n11981 , n11976 );
nand ( n11982 , n11980 , n11981 );
nand ( n11983 , n11979 , n11982 );
buf ( n11984 , n5154 );
buf ( n11985 , n11984 );
and ( n11986 , n11983 , n11985 );
not ( n11987 , n11983 );
not ( n11988 , n11984 );
and ( n11989 , n11987 , n11988 );
nor ( n11990 , n11986 , n11989 );
buf ( n11991 , n5155 );
nand ( n11992 , n7013 , n11991 );
buf ( n11993 , n5156 );
buf ( n11994 , n11993 );
and ( n11995 , n11992 , n11994 );
not ( n11996 , n11992 );
not ( n11997 , n11993 );
and ( n11998 , n11996 , n11997 );
nor ( n11999 , n11995 , n11998 );
xor ( n12000 , n11990 , n11999 );
buf ( n12001 , n5157 );
nand ( n12002 , n8375 , n12001 );
buf ( n12003 , n5158 );
not ( n12004 , n12003 );
and ( n12005 , n12002 , n12004 );
not ( n12006 , n12002 );
buf ( n12007 , n12003 );
and ( n12008 , n12006 , n12007 );
nor ( n12009 , n12005 , n12008 );
xnor ( n12010 , n12000 , n12009 );
buf ( n12011 , n12010 );
not ( n12012 , n12011 );
not ( n12013 , n12012 );
or ( n12014 , n11972 , n12013 );
nand ( n12015 , n12011 , n11970 );
nand ( n12016 , n12014 , n12015 );
not ( n12017 , n12016 );
buf ( n12018 , n5159 );
not ( n12019 , n12018 );
buf ( n12020 , n5160 );
not ( n12021 , n12020 );
buf ( n12022 , n5161 );
buf ( n12023 , n12022 );
nand ( n12024 , n12021 , n12023 );
not ( n12025 , n12022 );
buf ( n12026 , n12020 );
nand ( n12027 , n12025 , n12026 );
and ( n12028 , n12024 , n12027 );
xor ( n12029 , n12019 , n12028 );
buf ( n12030 , n5162 );
buf ( n12031 , n5163 );
buf ( n12032 , n12031 );
xor ( n12033 , n12030 , n12032 );
buf ( n12034 , n5164 );
nand ( n12035 , n6719 , n12034 );
xnor ( n12036 , n12033 , n12035 );
xnor ( n12037 , n12029 , n12036 );
buf ( n12038 , n12037 );
not ( n12039 , n12038 );
and ( n12040 , n12017 , n12039 );
and ( n12041 , n12038 , n12016 );
nor ( n12042 , n12040 , n12041 );
not ( n12043 , n12042 );
nand ( n12044 , n11960 , n12043 );
buf ( n12045 , n5165 );
buf ( n12046 , n12045 );
not ( n12047 , n12046 );
not ( n12048 , n7150 );
buf ( n12049 , n5166 );
not ( n12050 , n12049 );
not ( n12051 , n12050 );
or ( n12052 , n12048 , n12051 );
not ( n12053 , n7149 );
buf ( n12054 , n12049 );
nand ( n12055 , n12053 , n12054 );
nand ( n12056 , n12052 , n12055 );
buf ( n12057 , n5167 );
buf ( n12058 , n12057 );
and ( n12059 , n12056 , n12058 );
not ( n12060 , n12056 );
not ( n12061 , n12057 );
and ( n12062 , n12060 , n12061 );
nor ( n12063 , n12059 , n12062 );
buf ( n12064 , n5168 );
nand ( n12065 , n7014 , n12064 );
buf ( n12066 , n5169 );
not ( n12067 , n12066 );
and ( n12068 , n12065 , n12067 );
not ( n12069 , n12065 );
buf ( n12070 , n12066 );
and ( n12071 , n12069 , n12070 );
nor ( n12072 , n12068 , n12071 );
xor ( n12073 , n12063 , n12072 );
buf ( n12074 , n5170 );
nand ( n12075 , n8223 , n12074 );
buf ( n12076 , n5171 );
not ( n12077 , n12076 );
and ( n12078 , n12075 , n12077 );
not ( n12079 , n12075 );
buf ( n12080 , n12076 );
and ( n12081 , n12079 , n12080 );
nor ( n12082 , n12078 , n12081 );
xnor ( n12083 , n12073 , n12082 );
not ( n12084 , n12083 );
or ( n12085 , n12047 , n12084 );
not ( n12086 , n12083 );
not ( n12087 , n12086 );
or ( n12088 , n12087 , n12046 );
nand ( n12089 , n12085 , n12088 );
buf ( n12090 , n5172 );
buf ( n12091 , n12090 );
not ( n12092 , n12091 );
buf ( n12093 , n5173 );
not ( n12094 , n12093 );
not ( n12095 , n12094 );
or ( n12096 , n12092 , n12095 );
not ( n12097 , n12090 );
buf ( n12098 , n12093 );
nand ( n12099 , n12097 , n12098 );
nand ( n12100 , n12096 , n12099 );
buf ( n12101 , n5174 );
buf ( n12102 , n12101 );
and ( n12103 , n12100 , n12102 );
not ( n12104 , n12100 );
not ( n12105 , n12101 );
and ( n12106 , n12104 , n12105 );
nor ( n12107 , n12103 , n12106 );
buf ( n12108 , n5175 );
nand ( n12109 , n6502 , n12108 );
buf ( n12110 , n5176 );
buf ( n12111 , n12110 );
and ( n12112 , n12109 , n12111 );
not ( n12113 , n12109 );
not ( n12114 , n12110 );
and ( n12115 , n12113 , n12114 );
nor ( n12116 , n12112 , n12115 );
xor ( n12117 , n12107 , n12116 );
buf ( n12118 , n5177 );
nand ( n12119 , n8675 , n12118 );
buf ( n12120 , n5178 );
not ( n12121 , n12120 );
and ( n12122 , n12119 , n12121 );
not ( n12123 , n12119 );
buf ( n12124 , n12120 );
and ( n12125 , n12123 , n12124 );
nor ( n12126 , n12122 , n12125 );
xor ( n12127 , n12117 , n12126 );
buf ( n12128 , n12127 );
and ( n12129 , n12089 , n12128 );
not ( n12130 , n12089 );
not ( n12131 , n12128 );
and ( n12132 , n12130 , n12131 );
nor ( n12133 , n12129 , n12132 );
and ( n12134 , n12044 , n12133 );
not ( n12135 , n12044 );
not ( n12136 , n12133 );
and ( n12137 , n12135 , n12136 );
nor ( n12138 , n12134 , n12137 );
and ( n12139 , n11879 , n12138 );
not ( n12140 , n11879 );
not ( n12141 , n12138 );
and ( n12142 , n12140 , n12141 );
nor ( n12143 , n12139 , n12142 );
not ( n12144 , n12143 );
not ( n12145 , n12144 );
not ( n12146 , n11443 );
nand ( n12147 , n11512 , n12146 );
not ( n12148 , n12147 );
not ( n12149 , n11154 );
xor ( n12150 , n10369 , n12149 );
xor ( n12151 , n12150 , n7833 );
not ( n12152 , n12151 );
not ( n12153 , n12152 );
or ( n12154 , n12148 , n12153 );
or ( n12155 , n12152 , n12147 );
nand ( n12156 , n12154 , n12155 );
not ( n12157 , n12156 );
not ( n12158 , n12157 );
buf ( n12159 , n5179 );
nand ( n12160 , n6927 , n12159 );
buf ( n12161 , n5180 );
buf ( n12162 , n12161 );
and ( n12163 , n12160 , n12162 );
not ( n12164 , n12160 );
not ( n12165 , n12161 );
and ( n12166 , n12164 , n12165 );
nor ( n12167 , n12163 , n12166 );
buf ( n12168 , n5181 );
buf ( n12169 , n12168 );
not ( n12170 , n12169 );
buf ( n12171 , n5182 );
not ( n12172 , n12171 );
not ( n12173 , n12172 );
or ( n12174 , n12170 , n12173 );
not ( n12175 , n12168 );
buf ( n12176 , n12171 );
nand ( n12177 , n12175 , n12176 );
nand ( n12178 , n12174 , n12177 );
buf ( n12179 , n5183 );
buf ( n12180 , n12179 );
and ( n12181 , n12178 , n12180 );
not ( n12182 , n12178 );
not ( n12183 , n12179 );
and ( n12184 , n12182 , n12183 );
nor ( n12185 , n12181 , n12184 );
not ( n12186 , n12185 );
buf ( n12187 , n5184 );
nand ( n12188 , n6646 , n12187 );
buf ( n12189 , n5185 );
buf ( n12190 , n12189 );
and ( n12191 , n12188 , n12190 );
not ( n12192 , n12188 );
not ( n12193 , n12189 );
and ( n12194 , n12192 , n12193 );
nor ( n12195 , n12191 , n12194 );
xor ( n12196 , n12186 , n12195 );
buf ( n12197 , n5186 );
nand ( n12198 , n6816 , n12197 );
buf ( n12199 , n5187 );
not ( n12200 , n12199 );
and ( n12201 , n12198 , n12200 );
not ( n12202 , n12198 );
buf ( n12203 , n12199 );
and ( n12204 , n12202 , n12203 );
nor ( n12205 , n12201 , n12204 );
xnor ( n12206 , n12196 , n12205 );
xor ( n12207 , n12167 , n12206 );
buf ( n12208 , n5188 );
not ( n12209 , n12208 );
buf ( n12210 , n5189 );
buf ( n12211 , n12210 );
and ( n12212 , n12209 , n12211 );
not ( n12213 , n12209 );
not ( n12214 , n12210 );
and ( n12215 , n12213 , n12214 );
nor ( n12216 , n12212 , n12215 );
not ( n12217 , n12216 );
buf ( n12218 , n5190 );
buf ( n12219 , n5191 );
not ( n12220 , n12219 );
xor ( n12221 , n12218 , n12220 );
buf ( n12222 , n5192 );
nand ( n12223 , n6816 , n12222 );
buf ( n12224 , n5193 );
not ( n12225 , n12224 );
and ( n12226 , n12223 , n12225 );
not ( n12227 , n12223 );
buf ( n12228 , n12224 );
and ( n12229 , n12227 , n12228 );
nor ( n12230 , n12226 , n12229 );
xnor ( n12231 , n12221 , n12230 );
not ( n12232 , n12231 );
or ( n12233 , n12217 , n12232 );
or ( n12234 , n12231 , n12216 );
nand ( n12235 , n12233 , n12234 );
buf ( n12236 , n12235 );
xnor ( n12237 , n12207 , n12236 );
not ( n12238 , n12237 );
buf ( n12239 , n5194 );
not ( n12240 , n12239 );
buf ( n12241 , n5195 );
nand ( n12242 , n7569 , n12241 );
not ( n12243 , n12242 );
or ( n12244 , n12240 , n12243 );
or ( n12245 , n12242 , n12239 );
nand ( n12246 , n12244 , n12245 );
not ( n12247 , n12246 );
buf ( n12248 , n5196 );
buf ( n12249 , n12248 );
not ( n12250 , n12249 );
buf ( n12251 , n5197 );
not ( n12252 , n12251 );
not ( n12253 , n12252 );
or ( n12254 , n12250 , n12253 );
not ( n12255 , n12248 );
buf ( n12256 , n12251 );
nand ( n12257 , n12255 , n12256 );
nand ( n12258 , n12254 , n12257 );
buf ( n12259 , n5198 );
not ( n12260 , n12259 );
and ( n12261 , n12258 , n12260 );
not ( n12262 , n12258 );
buf ( n12263 , n12259 );
and ( n12264 , n12262 , n12263 );
nor ( n12265 , n12261 , n12264 );
buf ( n12266 , n5199 );
nand ( n12267 , n7107 , n12266 );
buf ( n12268 , n5200 );
buf ( n12269 , n12268 );
and ( n12270 , n12267 , n12269 );
not ( n12271 , n12267 );
not ( n12272 , n12268 );
and ( n12273 , n12271 , n12272 );
nor ( n12274 , n12270 , n12273 );
xor ( n12275 , n12265 , n12274 );
buf ( n12276 , n5201 );
nand ( n12277 , n7107 , n12276 );
buf ( n12278 , n5202 );
buf ( n12279 , n12278 );
and ( n12280 , n12277 , n12279 );
not ( n12281 , n12277 );
not ( n12282 , n12278 );
and ( n12283 , n12281 , n12282 );
nor ( n12284 , n12280 , n12283 );
not ( n12285 , n12284 );
xnor ( n12286 , n12275 , n12285 );
buf ( n12287 , n12286 );
not ( n12288 , n12287 );
or ( n12289 , n12247 , n12288 );
or ( n12290 , n12246 , n12286 );
nand ( n12291 , n12289 , n12290 );
not ( n12292 , n8619 );
and ( n12293 , n12291 , n12292 );
not ( n12294 , n12291 );
and ( n12295 , n12294 , n8620 );
nor ( n12296 , n12293 , n12295 );
not ( n12297 , n12296 );
nand ( n12298 , n12238 , n12297 );
not ( n12299 , n12298 );
buf ( n12300 , n5203 );
buf ( n12301 , n12300 );
not ( n12302 , n12301 );
buf ( n12303 , n5204 );
buf ( n12304 , n12303 );
not ( n12305 , n12304 );
buf ( n12306 , n5205 );
not ( n12307 , n12306 );
not ( n12308 , n12307 );
or ( n12309 , n12305 , n12308 );
not ( n12310 , n12303 );
buf ( n12311 , n12306 );
nand ( n12312 , n12310 , n12311 );
nand ( n12313 , n12309 , n12312 );
buf ( n12314 , n5206 );
not ( n12315 , n12314 );
and ( n12316 , n12313 , n12315 );
not ( n12317 , n12313 );
buf ( n12318 , n12314 );
and ( n12319 , n12317 , n12318 );
nor ( n12320 , n12316 , n12319 );
buf ( n12321 , n5207 );
nand ( n12322 , n8176 , n12321 );
buf ( n12323 , n5208 );
buf ( n12324 , n12323 );
and ( n12325 , n12322 , n12324 );
not ( n12326 , n12322 );
not ( n12327 , n12323 );
and ( n12328 , n12326 , n12327 );
nor ( n12329 , n12325 , n12328 );
xor ( n12330 , n12320 , n12329 );
buf ( n12331 , n5209 );
nand ( n12332 , n6916 , n12331 );
buf ( n12333 , n5210 );
buf ( n12334 , n12333 );
and ( n12335 , n12332 , n12334 );
not ( n12336 , n12332 );
not ( n12337 , n12333 );
and ( n12338 , n12336 , n12337 );
nor ( n12339 , n12335 , n12338 );
not ( n12340 , n12339 );
xnor ( n12341 , n12330 , n12340 );
buf ( n12342 , n12341 );
not ( n12343 , n12342 );
or ( n12344 , n12302 , n12343 );
or ( n12345 , n12342 , n12301 );
nand ( n12346 , n12344 , n12345 );
not ( n12347 , n12346 );
buf ( n12348 , n5211 );
not ( n12349 , n12348 );
buf ( n12350 , n5212 );
buf ( n12351 , n12350 );
not ( n12352 , n12351 );
not ( n12353 , n10537 );
not ( n12354 , n12353 );
or ( n12355 , n12352 , n12354 );
not ( n12356 , n12350 );
nand ( n12357 , n12356 , n10538 );
nand ( n12358 , n12355 , n12357 );
xor ( n12359 , n12349 , n12358 );
buf ( n12360 , n5213 );
nand ( n12361 , n8176 , n12360 );
buf ( n12362 , n5214 );
buf ( n12363 , n12362 );
and ( n12364 , n12361 , n12363 );
not ( n12365 , n12361 );
not ( n12366 , n12362 );
and ( n12367 , n12365 , n12366 );
nor ( n12368 , n12364 , n12367 );
not ( n12369 , n12368 );
buf ( n12370 , n5215 );
not ( n12371 , n12370 );
and ( n12372 , n12369 , n12371 );
and ( n12373 , n12368 , n12370 );
nor ( n12374 , n12372 , n12373 );
xor ( n12375 , n12359 , n12374 );
not ( n12376 , n12375 );
not ( n12377 , n12376 );
and ( n12378 , n12347 , n12377 );
buf ( n12379 , n12376 );
and ( n12380 , n12346 , n12379 );
nor ( n12381 , n12378 , n12380 );
not ( n12382 , n12381 );
not ( n12383 , n12382 );
and ( n12384 , n12299 , n12383 );
and ( n12385 , n12298 , n12382 );
nor ( n12386 , n12384 , n12385 );
not ( n12387 , n12386 );
not ( n12388 , n12387 );
or ( n12389 , n12158 , n12388 );
nand ( n12390 , n12386 , n12156 );
nand ( n12391 , n12389 , n12390 );
not ( n12392 , n12391 );
and ( n12393 , n12145 , n12392 );
and ( n12394 , n12144 , n12391 );
nor ( n12395 , n12393 , n12394 );
not ( n12396 , n12395 );
or ( n12397 , n11519 , n12396 );
not ( n12398 , n11518 );
and ( n12399 , n12143 , n12391 );
not ( n12400 , n12143 );
not ( n12401 , n12391 );
and ( n12402 , n12400 , n12401 );
nor ( n12403 , n12399 , n12402 );
nand ( n12404 , n12398 , n12403 );
nand ( n12405 , n12397 , n12404 );
buf ( n12406 , n5216 );
buf ( n12407 , n12406 );
not ( n12408 , n12407 );
buf ( n12409 , n5217 );
buf ( n12410 , n12409 );
not ( n12411 , n12410 );
buf ( n12412 , n5218 );
not ( n12413 , n12412 );
not ( n12414 , n12413 );
or ( n12415 , n12411 , n12414 );
not ( n12416 , n12409 );
buf ( n12417 , n12412 );
nand ( n12418 , n12416 , n12417 );
nand ( n12419 , n12415 , n12418 );
buf ( n12420 , n5219 );
buf ( n12421 , n12420 );
and ( n12422 , n12419 , n12421 );
not ( n12423 , n12419 );
not ( n12424 , n12420 );
and ( n12425 , n12423 , n12424 );
nor ( n12426 , n12422 , n12425 );
buf ( n12427 , n5220 );
nand ( n12428 , n8364 , n12427 );
buf ( n12429 , n5221 );
xor ( n12430 , n12428 , n12429 );
xor ( n12431 , n12426 , n12430 );
buf ( n12432 , n5222 );
nand ( n12433 , n9310 , n12432 );
buf ( n12434 , n5223 );
not ( n12435 , n12434 );
and ( n12436 , n12433 , n12435 );
not ( n12437 , n12433 );
buf ( n12438 , n12434 );
and ( n12439 , n12437 , n12438 );
nor ( n12440 , n12436 , n12439 );
xor ( n12441 , n12431 , n12440 );
buf ( n12442 , n12441 );
not ( n12443 , n12442 );
or ( n12444 , n12408 , n12443 );
or ( n12445 , n12442 , n12407 );
nand ( n12446 , n12444 , n12445 );
not ( n12447 , n12446 );
buf ( n12448 , n5224 );
buf ( n12449 , n5225 );
not ( n12450 , n12449 );
buf ( n12451 , n5226 );
buf ( n12452 , n12451 );
and ( n12453 , n12450 , n12452 );
not ( n12454 , n12450 );
not ( n12455 , n12451 );
and ( n12456 , n12454 , n12455 );
nor ( n12457 , n12453 , n12456 );
xor ( n12458 , n12448 , n12457 );
buf ( n12459 , n5227 );
xor ( n12460 , n12459 , n12239 );
xnor ( n12461 , n12460 , n12242 );
xnor ( n12462 , n12458 , n12461 );
not ( n12463 , n12462 );
not ( n12464 , n12463 );
and ( n12465 , n12447 , n12464 );
not ( n12466 , n12462 );
and ( n12467 , n12446 , n12466 );
nor ( n12468 , n12465 , n12467 );
buf ( n12469 , n5228 );
buf ( n12470 , n12469 );
not ( n12471 , n12470 );
buf ( n12472 , n5229 );
buf ( n12473 , n12472 );
not ( n12474 , n12473 );
buf ( n12475 , n5230 );
not ( n12476 , n12475 );
not ( n12477 , n12476 );
or ( n12478 , n12474 , n12477 );
not ( n12479 , n12472 );
buf ( n12480 , n12475 );
nand ( n12481 , n12479 , n12480 );
nand ( n12482 , n12478 , n12481 );
and ( n12483 , n12482 , n10093 );
not ( n12484 , n12482 );
and ( n12485 , n12484 , n10049 );
nor ( n12486 , n12483 , n12485 );
xor ( n12487 , n12486 , n10483 );
buf ( n12488 , n5231 );
nand ( n12489 , n6558 , n12488 );
buf ( n12490 , n5232 );
not ( n12491 , n12490 );
and ( n12492 , n12489 , n12491 );
not ( n12493 , n12489 );
buf ( n12494 , n12490 );
and ( n12495 , n12493 , n12494 );
nor ( n12496 , n12492 , n12495 );
xnor ( n12497 , n12487 , n12496 );
buf ( n12498 , n12497 );
not ( n12499 , n12498 );
or ( n12500 , n12471 , n12499 );
or ( n12501 , n12498 , n12470 );
nand ( n12502 , n12500 , n12501 );
not ( n12503 , n12502 );
buf ( n12504 , n5233 );
buf ( n12505 , n12504 );
not ( n12506 , n12505 );
buf ( n12507 , n5234 );
not ( n12508 , n12507 );
not ( n12509 , n12508 );
or ( n12510 , n12506 , n12509 );
not ( n12511 , n12504 );
buf ( n12512 , n12507 );
nand ( n12513 , n12511 , n12512 );
nand ( n12514 , n12510 , n12513 );
buf ( n12515 , n5235 );
not ( n12516 , n12515 );
and ( n12517 , n12514 , n12516 );
not ( n12518 , n12514 );
buf ( n12519 , n12515 );
and ( n12520 , n12518 , n12519 );
nor ( n12521 , n12517 , n12520 );
buf ( n12522 , n5236 );
nand ( n12523 , n6770 , n12522 );
buf ( n12524 , n5237 );
buf ( n12525 , n12524 );
and ( n12526 , n12523 , n12525 );
not ( n12527 , n12523 );
not ( n12528 , n12524 );
and ( n12529 , n12527 , n12528 );
nor ( n12530 , n12526 , n12529 );
xor ( n12531 , n12521 , n12530 );
buf ( n12532 , n5238 );
nand ( n12533 , n6719 , n12532 );
buf ( n12534 , n5239 );
not ( n12535 , n12534 );
and ( n12536 , n12533 , n12535 );
not ( n12537 , n12533 );
buf ( n12538 , n12534 );
and ( n12539 , n12537 , n12538 );
nor ( n12540 , n12536 , n12539 );
xor ( n12541 , n12531 , n12540 );
not ( n12542 , n12541 );
buf ( n12543 , n12542 );
not ( n12544 , n12543 );
and ( n12545 , n12503 , n12544 );
buf ( n12546 , n12542 );
and ( n12547 , n12502 , n12546 );
nor ( n12548 , n12545 , n12547 );
not ( n12549 , n12548 );
nand ( n12550 , n12468 , n12549 );
not ( n12551 , n12550 );
not ( n12552 , n6790 );
not ( n12553 , n12552 );
buf ( n12554 , n5240 );
buf ( n12555 , n12554 );
not ( n12556 , n12555 );
buf ( n12557 , n5241 );
not ( n12558 , n12557 );
not ( n12559 , n12558 );
or ( n12560 , n12556 , n12559 );
not ( n12561 , n12554 );
buf ( n12562 , n12557 );
nand ( n12563 , n12561 , n12562 );
nand ( n12564 , n12560 , n12563 );
buf ( n12565 , n5242 );
not ( n12566 , n12565 );
and ( n12567 , n12564 , n12566 );
not ( n12568 , n12564 );
buf ( n12569 , n12565 );
and ( n12570 , n12568 , n12569 );
nor ( n12571 , n12567 , n12570 );
buf ( n12572 , n5243 );
nand ( n12573 , n7912 , n12572 );
buf ( n12574 , n5244 );
buf ( n12575 , n12574 );
and ( n12576 , n12573 , n12575 );
not ( n12577 , n12573 );
not ( n12578 , n12574 );
and ( n12579 , n12577 , n12578 );
nor ( n12580 , n12576 , n12579 );
xor ( n12581 , n12571 , n12580 );
buf ( n12582 , n5245 );
nand ( n12583 , n7912 , n12582 );
buf ( n12584 , n5246 );
buf ( n12585 , n12584 );
and ( n12586 , n12583 , n12585 );
not ( n12587 , n12583 );
not ( n12588 , n12584 );
and ( n12589 , n12587 , n12588 );
nor ( n12590 , n12586 , n12589 );
xnor ( n12591 , n12581 , n12590 );
not ( n12592 , n12591 );
or ( n12593 , n12553 , n12592 );
not ( n12594 , n12591 );
not ( n12595 , n12594 );
or ( n12596 , n12595 , n12552 );
nand ( n12597 , n12593 , n12596 );
buf ( n12598 , n5247 );
buf ( n12599 , n12598 );
not ( n12600 , n12599 );
buf ( n12601 , n5248 );
not ( n12602 , n12601 );
not ( n12603 , n12602 );
or ( n12604 , n12600 , n12603 );
not ( n12605 , n12598 );
buf ( n12606 , n12601 );
nand ( n12607 , n12605 , n12606 );
nand ( n12608 , n12604 , n12607 );
buf ( n12609 , n5249 );
buf ( n12610 , n12609 );
and ( n12611 , n12608 , n12610 );
not ( n12612 , n12608 );
not ( n12613 , n12609 );
and ( n12614 , n12612 , n12613 );
nor ( n12615 , n12611 , n12614 );
buf ( n12616 , n5250 );
nand ( n12617 , n7293 , n12616 );
buf ( n12618 , n5251 );
buf ( n12619 , n12618 );
and ( n12620 , n12617 , n12619 );
not ( n12621 , n12617 );
not ( n12622 , n12618 );
and ( n12623 , n12621 , n12622 );
nor ( n12624 , n12620 , n12623 );
xor ( n12625 , n12615 , n12624 );
buf ( n12626 , n5252 );
nand ( n12627 , n11946 , n12626 );
buf ( n12628 , n5253 );
buf ( n12629 , n12628 );
and ( n12630 , n12627 , n12629 );
not ( n12631 , n12627 );
not ( n12632 , n12628 );
and ( n12633 , n12631 , n12632 );
nor ( n12634 , n12630 , n12633 );
xnor ( n12635 , n12625 , n12634 );
buf ( n12636 , n12635 );
buf ( n12637 , n12636 );
not ( n12638 , n12637 );
and ( n12639 , n12597 , n12638 );
not ( n12640 , n12597 );
and ( n12641 , n12640 , n12637 );
nor ( n12642 , n12639 , n12641 );
not ( n12643 , n12642 );
and ( n12644 , n12551 , n12643 );
and ( n12645 , n12550 , n12642 );
nor ( n12646 , n12644 , n12645 );
not ( n12647 , n12646 );
not ( n12648 , n12647 );
xor ( n12649 , n10646 , n10665 );
not ( n12650 , n10655 );
xnor ( n12651 , n12649 , n12650 );
not ( n12652 , n12651 );
buf ( n12653 , n5254 );
buf ( n12654 , n12653 );
not ( n12655 , n12654 );
and ( n12656 , n12652 , n12655 );
and ( n12657 , n12651 , n12654 );
nor ( n12658 , n12656 , n12657 );
and ( n12659 , n12658 , n10679 );
not ( n12660 , n12658 );
and ( n12661 , n12660 , n10678 );
nor ( n12662 , n12659 , n12661 );
buf ( n12663 , n5255 );
buf ( n12664 , n12663 );
not ( n12665 , n12664 );
buf ( n12666 , n5256 );
nand ( n12667 , n6770 , n12666 );
buf ( n12668 , n5257 );
buf ( n12669 , n12668 );
and ( n12670 , n12667 , n12669 );
not ( n12671 , n12667 );
not ( n12672 , n12668 );
and ( n12673 , n12671 , n12672 );
nor ( n12674 , n12670 , n12673 );
not ( n12675 , n12674 );
buf ( n12676 , n5258 );
nand ( n12677 , n7868 , n12676 );
buf ( n12678 , n5259 );
not ( n12679 , n12678 );
and ( n12680 , n12677 , n12679 );
not ( n12681 , n12677 );
buf ( n12682 , n12678 );
and ( n12683 , n12681 , n12682 );
nor ( n12684 , n12680 , n12683 );
not ( n12685 , n12684 );
or ( n12686 , n12675 , n12685 );
or ( n12687 , n12674 , n12684 );
nand ( n12688 , n12686 , n12687 );
buf ( n12689 , n5260 );
buf ( n12690 , n12689 );
not ( n12691 , n12690 );
buf ( n12692 , n5261 );
not ( n12693 , n12692 );
not ( n12694 , n12693 );
or ( n12695 , n12691 , n12694 );
not ( n12696 , n12689 );
buf ( n12697 , n12692 );
nand ( n12698 , n12696 , n12697 );
nand ( n12699 , n12695 , n12698 );
buf ( n12700 , n5262 );
buf ( n12701 , n12700 );
and ( n12702 , n12699 , n12701 );
not ( n12703 , n12699 );
not ( n12704 , n12700 );
and ( n12705 , n12703 , n12704 );
nor ( n12706 , n12702 , n12705 );
xnor ( n12707 , n12688 , n12706 );
not ( n12708 , n12707 );
or ( n12709 , n12665 , n12708 );
not ( n12710 , n12664 );
xor ( n12711 , n12706 , n12674 );
buf ( n12712 , n12684 );
xnor ( n12713 , n12711 , n12712 );
nand ( n12714 , n12710 , n12713 );
nand ( n12715 , n12709 , n12714 );
not ( n12716 , n12715 );
buf ( n12717 , n5263 );
buf ( n12718 , n12717 );
not ( n12719 , n12718 );
buf ( n12720 , n5264 );
not ( n12721 , n12720 );
not ( n12722 , n12721 );
or ( n12723 , n12719 , n12722 );
not ( n12724 , n12717 );
buf ( n12725 , n12720 );
nand ( n12726 , n12724 , n12725 );
nand ( n12727 , n12723 , n12726 );
buf ( n12728 , n5265 );
not ( n12729 , n12728 );
and ( n12730 , n12727 , n12729 );
not ( n12731 , n12727 );
buf ( n12732 , n12728 );
and ( n12733 , n12731 , n12732 );
nor ( n12734 , n12730 , n12733 );
buf ( n12735 , n5266 );
nand ( n12736 , n7977 , n12735 );
buf ( n12737 , n5267 );
buf ( n12738 , n12737 );
and ( n12739 , n12736 , n12738 );
not ( n12740 , n12736 );
not ( n12741 , n12737 );
and ( n12742 , n12740 , n12741 );
nor ( n12743 , n12739 , n12742 );
xor ( n12744 , n12734 , n12743 );
buf ( n12745 , n5268 );
nand ( n12746 , n11946 , n12745 );
buf ( n12747 , n5269 );
not ( n12748 , n12747 );
and ( n12749 , n12746 , n12748 );
not ( n12750 , n12746 );
buf ( n12751 , n12747 );
and ( n12752 , n12750 , n12751 );
nor ( n12753 , n12749 , n12752 );
xnor ( n12754 , n12744 , n12753 );
buf ( n12755 , n12754 );
buf ( n12756 , n12755 );
not ( n12757 , n12756 );
and ( n12758 , n12716 , n12757 );
and ( n12759 , n12715 , n12755 );
nor ( n12760 , n12758 , n12759 );
nand ( n12761 , n12662 , n12760 );
not ( n12762 , n12761 );
buf ( n12763 , n5270 );
nand ( n12764 , n11337 , n12763 );
buf ( n12765 , n5271 );
not ( n12766 , n12765 );
and ( n12767 , n12764 , n12766 );
not ( n12768 , n12764 );
buf ( n12769 , n12765 );
and ( n12770 , n12768 , n12769 );
nor ( n12771 , n12767 , n12770 );
buf ( n12772 , n5272 );
buf ( n12773 , n12772 );
not ( n12774 , n12773 );
buf ( n12775 , n5273 );
not ( n12776 , n12775 );
not ( n12777 , n12776 );
or ( n12778 , n12774 , n12777 );
not ( n12779 , n12772 );
buf ( n12780 , n12775 );
nand ( n12781 , n12779 , n12780 );
nand ( n12782 , n12778 , n12781 );
buf ( n12783 , n5274 );
not ( n12784 , n12783 );
and ( n12785 , n12782 , n12784 );
not ( n12786 , n12782 );
buf ( n12787 , n12783 );
and ( n12788 , n12786 , n12787 );
nor ( n12789 , n12785 , n12788 );
buf ( n12790 , n5275 );
nand ( n12791 , n8954 , n12790 );
buf ( n12792 , n5276 );
buf ( n12793 , n12792 );
and ( n12794 , n12791 , n12793 );
not ( n12795 , n12791 );
not ( n12796 , n12792 );
and ( n12797 , n12795 , n12796 );
nor ( n12798 , n12794 , n12797 );
xor ( n12799 , n12789 , n12798 );
buf ( n12800 , n5277 );
nand ( n12801 , n6871 , n12800 );
buf ( n12802 , n5278 );
buf ( n12803 , n12802 );
and ( n12804 , n12801 , n12803 );
not ( n12805 , n12801 );
not ( n12806 , n12802 );
and ( n12807 , n12805 , n12806 );
nor ( n12808 , n12804 , n12807 );
xor ( n12809 , n12799 , n12808 );
not ( n12810 , n12809 );
buf ( n12811 , n12810 );
xor ( n12812 , n12771 , n12811 );
buf ( n12813 , n5279 );
buf ( n12814 , n12813 );
buf ( n12815 , n5280 );
buf ( n12816 , n12815 );
not ( n12817 , n12816 );
buf ( n12818 , n5281 );
not ( n12819 , n12818 );
not ( n12820 , n12819 );
or ( n12821 , n12817 , n12820 );
not ( n12822 , n12815 );
buf ( n12823 , n12818 );
nand ( n12824 , n12822 , n12823 );
nand ( n12825 , n12821 , n12824 );
xor ( n12826 , n12814 , n12825 );
buf ( n12827 , n5282 );
xor ( n12828 , n9280 , n12827 );
buf ( n12829 , n5283 );
nand ( n12830 , n10874 , n12829 );
xnor ( n12831 , n12828 , n12830 );
xnor ( n12832 , n12826 , n12831 );
buf ( n12833 , n12832 );
xnor ( n12834 , n12812 , n12833 );
not ( n12835 , n12834 );
or ( n12836 , n12762 , n12835 );
or ( n12837 , n12834 , n12761 );
nand ( n12838 , n12836 , n12837 );
not ( n12839 , n12838 );
not ( n12840 , n12839 );
or ( n12841 , n12648 , n12840 );
nand ( n12842 , n12838 , n12646 );
nand ( n12843 , n12841 , n12842 );
buf ( n12844 , n5284 );
buf ( n12845 , n5285 );
buf ( n12846 , n12845 );
not ( n12847 , n12846 );
buf ( n12848 , n5286 );
not ( n12849 , n12848 );
not ( n12850 , n12849 );
or ( n12851 , n12847 , n12850 );
not ( n12852 , n12845 );
buf ( n12853 , n12848 );
nand ( n12854 , n12852 , n12853 );
nand ( n12855 , n12851 , n12854 );
xor ( n12856 , n12844 , n12855 );
buf ( n12857 , n5287 );
buf ( n12858 , n5288 );
not ( n12859 , n12858 );
xor ( n12860 , n12857 , n12859 );
buf ( n12861 , n5289 );
nand ( n12862 , n8260 , n12861 );
xnor ( n12863 , n12860 , n12862 );
xnor ( n12864 , n12856 , n12863 );
buf ( n12865 , n12864 );
not ( n12866 , n12865 );
buf ( n12867 , n5290 );
buf ( n12868 , n12867 );
not ( n12869 , n12868 );
buf ( n12870 , n5291 );
not ( n12871 , n12870 );
not ( n12872 , n12871 );
or ( n12873 , n12869 , n12872 );
not ( n12874 , n12867 );
buf ( n12875 , n12870 );
nand ( n12876 , n12874 , n12875 );
nand ( n12877 , n12873 , n12876 );
and ( n12878 , n12877 , n6943 );
not ( n12879 , n12877 );
and ( n12880 , n12879 , n6896 );
nor ( n12881 , n12878 , n12880 );
buf ( n12882 , n5292 );
nand ( n12883 , n8322 , n12882 );
buf ( n12884 , n5293 );
buf ( n12885 , n12884 );
and ( n12886 , n12883 , n12885 );
not ( n12887 , n12883 );
not ( n12888 , n12884 );
and ( n12889 , n12887 , n12888 );
nor ( n12890 , n12886 , n12889 );
xor ( n12891 , n12881 , n12890 );
buf ( n12892 , n5294 );
nand ( n12893 , n8454 , n12892 );
buf ( n12894 , n5295 );
not ( n12895 , n12894 );
xor ( n12896 , n12893 , n12895 );
xnor ( n12897 , n12891 , n12896 );
buf ( n12898 , n5296 );
buf ( n12899 , n12898 );
nand ( n12900 , n12897 , n12899 );
not ( n12901 , n12900 );
nor ( n12902 , n12897 , n12899 );
nor ( n12903 , n12901 , n12902 );
not ( n12904 , n12903 );
or ( n12905 , n12866 , n12904 );
not ( n12906 , n12864 );
not ( n12907 , n12906 );
or ( n12908 , n12907 , n12903 );
nand ( n12909 , n12905 , n12908 );
not ( n12910 , n7477 );
buf ( n12911 , n5297 );
not ( n12912 , n12911 );
nand ( n12913 , n7489 , n12912 );
not ( n12914 , n12913 );
nor ( n12915 , n7489 , n12912 );
nor ( n12916 , n12914 , n12915 );
not ( n12917 , n12916 );
and ( n12918 , n12910 , n12917 );
and ( n12919 , n7477 , n12916 );
nor ( n12920 , n12918 , n12919 );
not ( n12921 , n12920 );
not ( n12922 , n10916 );
and ( n12923 , n12921 , n12922 );
and ( n12924 , n12920 , n10916 );
nor ( n12925 , n12923 , n12924 );
nand ( n12926 , n12909 , n12925 );
not ( n12927 , n9044 );
not ( n12928 , n10226 );
or ( n12929 , n12927 , n12928 );
not ( n12930 , n9044 );
buf ( n12931 , n10189 );
xor ( n12932 , n10221 , n12931 );
xnor ( n12933 , n12932 , n10199 );
nand ( n12934 , n12930 , n12933 );
nand ( n12935 , n12929 , n12934 );
not ( n12936 , n6734 );
and ( n12937 , n12935 , n12936 );
not ( n12938 , n12935 );
not ( n12939 , n6731 );
and ( n12940 , n12938 , n12939 );
nor ( n12941 , n12937 , n12940 );
and ( n12942 , n12926 , n12941 );
not ( n12943 , n12926 );
not ( n12944 , n12941 );
and ( n12945 , n12943 , n12944 );
nor ( n12946 , n12942 , n12945 );
not ( n12947 , n12946 );
not ( n12948 , n12947 );
not ( n12949 , n10957 );
buf ( n12950 , n5298 );
buf ( n12951 , n12950 );
not ( n12952 , n12951 );
and ( n12953 , n12949 , n12952 );
and ( n12954 , n10957 , n12951 );
nor ( n12955 , n12953 , n12954 );
buf ( n12956 , n5299 );
buf ( n12957 , n12956 );
not ( n12958 , n12957 );
buf ( n12959 , n5300 );
not ( n12960 , n12959 );
not ( n12961 , n12960 );
or ( n12962 , n12958 , n12961 );
not ( n12963 , n12956 );
buf ( n12964 , n12959 );
nand ( n12965 , n12963 , n12964 );
nand ( n12966 , n12962 , n12965 );
buf ( n12967 , n5301 );
not ( n12968 , n12967 );
and ( n12969 , n12966 , n12968 );
not ( n12970 , n12966 );
buf ( n12971 , n12967 );
and ( n12972 , n12970 , n12971 );
nor ( n12973 , n12969 , n12972 );
buf ( n12974 , n5302 );
nand ( n12975 , n6646 , n12974 );
buf ( n12976 , n5303 );
buf ( n12977 , n12976 );
and ( n12978 , n12975 , n12977 );
not ( n12979 , n12975 );
not ( n12980 , n12976 );
and ( n12981 , n12979 , n12980 );
nor ( n12982 , n12978 , n12981 );
xor ( n12983 , n12973 , n12982 );
buf ( n12984 , n5304 );
nand ( n12985 , n6927 , n12984 );
buf ( n12986 , n5305 );
not ( n12987 , n12986 );
and ( n12988 , n12985 , n12987 );
not ( n12989 , n12985 );
buf ( n12990 , n12986 );
and ( n12991 , n12989 , n12990 );
nor ( n12992 , n12988 , n12991 );
xnor ( n12993 , n12983 , n12992 );
buf ( n12994 , n12993 );
and ( n12995 , n12955 , n12994 );
not ( n12996 , n12955 );
not ( n12997 , n12982 );
not ( n12998 , n12992 );
or ( n12999 , n12997 , n12998 );
or ( n13000 , n12982 , n12992 );
nand ( n13001 , n12999 , n13000 );
not ( n13002 , n12973 );
and ( n13003 , n13001 , n13002 );
not ( n13004 , n13001 );
and ( n13005 , n13004 , n12973 );
nor ( n13006 , n13003 , n13005 );
buf ( n13007 , n13006 );
and ( n13008 , n12996 , n13007 );
nor ( n13009 , n12995 , n13008 );
buf ( n13010 , n5306 );
not ( n13011 , n13010 );
not ( n13012 , n13011 );
buf ( n13013 , n5307 );
buf ( n13014 , n13013 );
not ( n13015 , n13014 );
buf ( n13016 , n5308 );
not ( n13017 , n13016 );
not ( n13018 , n13017 );
or ( n13019 , n13015 , n13018 );
not ( n13020 , n13013 );
buf ( n13021 , n13016 );
nand ( n13022 , n13020 , n13021 );
nand ( n13023 , n13019 , n13022 );
not ( n13024 , n13023 );
or ( n13025 , n13012 , n13024 );
or ( n13026 , n13023 , n13011 );
nand ( n13027 , n13025 , n13026 );
not ( n13028 , n13027 );
buf ( n13029 , n5309 );
buf ( n13030 , n5310 );
not ( n13031 , n13030 );
xor ( n13032 , n13029 , n13031 );
buf ( n13033 , n5311 );
not ( n13034 , n13033 );
buf ( n13035 , n5312 );
nand ( n13036 , n6577 , n13035 );
not ( n13037 , n13036 );
or ( n13038 , n13034 , n13037 );
nand ( n13039 , n8070 , n13035 );
or ( n13040 , n13039 , n13033 );
nand ( n13041 , n13038 , n13040 );
xnor ( n13042 , n13032 , n13041 );
not ( n13043 , n13042 );
not ( n13044 , n13043 );
or ( n13045 , n13028 , n13044 );
or ( n13046 , n13043 , n13027 );
nand ( n13047 , n13045 , n13046 );
not ( n13048 , n13047 );
buf ( n13049 , n5313 );
buf ( n13050 , n13049 );
not ( n13051 , n13050 );
buf ( n13052 , n5314 );
not ( n13053 , n13052 );
not ( n13054 , n13053 );
or ( n13055 , n13051 , n13054 );
not ( n13056 , n13049 );
buf ( n13057 , n13052 );
nand ( n13058 , n13056 , n13057 );
nand ( n13059 , n13055 , n13058 );
buf ( n13060 , n5315 );
not ( n13061 , n13060 );
and ( n13062 , n13059 , n13061 );
not ( n13063 , n13059 );
buf ( n13064 , n13060 );
and ( n13065 , n13063 , n13064 );
nor ( n13066 , n13062 , n13065 );
buf ( n13067 , n5316 );
nand ( n13068 , n7344 , n13067 );
buf ( n13069 , n5317 );
buf ( n13070 , n13069 );
and ( n13071 , n13068 , n13070 );
not ( n13072 , n13068 );
not ( n13073 , n13069 );
and ( n13074 , n13072 , n13073 );
nor ( n13075 , n13071 , n13074 );
xor ( n13076 , n13066 , n13075 );
buf ( n13077 , n5318 );
nand ( n13078 , n8954 , n13077 );
buf ( n13079 , n5319 );
buf ( n13080 , n13079 );
and ( n13081 , n13078 , n13080 );
not ( n13082 , n13078 );
not ( n13083 , n13079 );
and ( n13084 , n13082 , n13083 );
nor ( n13085 , n13081 , n13084 );
not ( n13086 , n13085 );
xnor ( n13087 , n13076 , n13086 );
buf ( n13088 , n13087 );
not ( n13089 , n13088 );
and ( n13090 , n13048 , n13089 );
and ( n13091 , n13088 , n13047 );
nor ( n13092 , n13090 , n13091 );
nand ( n13093 , n13009 , n13092 );
not ( n13094 , n13093 );
buf ( n13095 , n5320 );
buf ( n13096 , n13095 );
not ( n13097 , n13096 );
buf ( n13098 , n5321 );
not ( n13099 , n13098 );
not ( n13100 , n13099 );
or ( n13101 , n13097 , n13100 );
not ( n13102 , n13095 );
buf ( n13103 , n13098 );
nand ( n13104 , n13102 , n13103 );
nand ( n13105 , n13101 , n13104 );
buf ( n13106 , n5322 );
buf ( n13107 , n13106 );
and ( n13108 , n13105 , n13107 );
not ( n13109 , n13105 );
not ( n13110 , n13106 );
and ( n13111 , n13109 , n13110 );
nor ( n13112 , n13108 , n13111 );
buf ( n13113 , n5323 );
nand ( n13114 , n7563 , n13113 );
buf ( n13115 , n5324 );
buf ( n13116 , n13115 );
and ( n13117 , n13114 , n13116 );
not ( n13118 , n13114 );
not ( n13119 , n13115 );
and ( n13120 , n13118 , n13119 );
nor ( n13121 , n13117 , n13120 );
xor ( n13122 , n13112 , n13121 );
buf ( n13123 , n5325 );
nand ( n13124 , n8454 , n13123 );
buf ( n13125 , n5326 );
buf ( n13126 , n13125 );
and ( n13127 , n13124 , n13126 );
not ( n13128 , n13124 );
not ( n13129 , n13125 );
and ( n13130 , n13128 , n13129 );
nor ( n13131 , n13127 , n13130 );
xnor ( n13132 , n13122 , n13131 );
buf ( n13133 , n13132 );
not ( n13134 , n13133 );
not ( n13135 , n11076 );
buf ( n13136 , n5327 );
buf ( n13137 , n13136 );
not ( n13138 , n13137 );
buf ( n13139 , n5328 );
not ( n13140 , n13139 );
not ( n13141 , n13140 );
or ( n13142 , n13138 , n13141 );
not ( n13143 , n13136 );
buf ( n13144 , n13139 );
nand ( n13145 , n13143 , n13144 );
nand ( n13146 , n13142 , n13145 );
not ( n13147 , n13146 );
not ( n13148 , n13147 );
or ( n13149 , n13135 , n13148 );
or ( n13150 , n13147 , n11076 );
nand ( n13151 , n13149 , n13150 );
not ( n13152 , n13151 );
buf ( n13153 , n5329 );
nand ( n13154 , n8454 , n13153 );
not ( n13155 , n13154 );
buf ( n13156 , n5330 );
not ( n13157 , n13156 );
and ( n13158 , n13155 , n13157 );
nand ( n13159 , n6557 , n13153 );
and ( n13160 , n13159 , n13156 );
nor ( n13161 , n13158 , n13160 );
not ( n13162 , n13161 );
buf ( n13163 , n5331 );
nand ( n13164 , n6577 , n13163 );
buf ( n13165 , n5332 );
not ( n13166 , n13165 );
and ( n13167 , n13164 , n13166 );
not ( n13168 , n13164 );
buf ( n13169 , n13165 );
and ( n13170 , n13168 , n13169 );
nor ( n13171 , n13167 , n13170 );
not ( n13172 , n13171 );
or ( n13173 , n13162 , n13172 );
not ( n13174 , n13171 );
not ( n13175 , n13161 );
nand ( n13176 , n13174 , n13175 );
nand ( n13177 , n13173 , n13176 );
buf ( n13178 , n5333 );
not ( n13179 , n13178 );
and ( n13180 , n13177 , n13179 );
not ( n13181 , n13177 );
buf ( n13182 , n13178 );
and ( n13183 , n13181 , n13182 );
nor ( n13184 , n13180 , n13183 );
not ( n13185 , n13184 );
or ( n13186 , n13152 , n13185 );
or ( n13187 , n13184 , n13151 );
nand ( n13188 , n13186 , n13187 );
not ( n13189 , n13188 );
and ( n13190 , n13134 , n13189 );
and ( n13191 , n13133 , n13188 );
nor ( n13192 , n13190 , n13191 );
not ( n13193 , n13192 );
not ( n13194 , n13193 );
and ( n13195 , n13094 , n13194 );
and ( n13196 , n13093 , n13193 );
nor ( n13197 , n13195 , n13196 );
not ( n13198 , n13197 );
not ( n13199 , n13198 );
or ( n13200 , n12948 , n13199 );
nand ( n13201 , n12946 , n13197 );
nand ( n13202 , n13200 , n13201 );
buf ( n13203 , n5334 );
buf ( n13204 , n13203 );
not ( n13205 , n13204 );
not ( n13206 , n8385 );
or ( n13207 , n13205 , n13206 );
not ( n13208 , n13204 );
nand ( n13209 , n13208 , n8398 );
nand ( n13210 , n13207 , n13209 );
and ( n13211 , n13210 , n8439 );
not ( n13212 , n13210 );
and ( n13213 , n13212 , n8440 );
nor ( n13214 , n13211 , n13213 );
buf ( n13215 , n5335 );
not ( n13216 , n13215 );
buf ( n13217 , n5336 );
nand ( n13218 , n8069 , n13217 );
buf ( n13219 , n5337 );
buf ( n13220 , n13219 );
and ( n13221 , n13218 , n13220 );
not ( n13222 , n13218 );
not ( n13223 , n13219 );
and ( n13224 , n13222 , n13223 );
nor ( n13225 , n13221 , n13224 );
xor ( n13226 , n13216 , n13225 );
buf ( n13227 , n5338 );
nand ( n13228 , n7344 , n13227 );
buf ( n13229 , n5339 );
buf ( n13230 , n13229 );
and ( n13231 , n13228 , n13230 );
not ( n13232 , n13228 );
not ( n13233 , n13229 );
and ( n13234 , n13232 , n13233 );
nor ( n13235 , n13231 , n13234 );
xnor ( n13236 , n13226 , n13235 );
not ( n13237 , n13236 );
buf ( n13238 , n5340 );
buf ( n13239 , n13238 );
not ( n13240 , n13239 );
buf ( n13241 , n5341 );
not ( n13242 , n13241 );
not ( n13243 , n13242 );
or ( n13244 , n13240 , n13243 );
not ( n13245 , n13238 );
buf ( n13246 , n13241 );
nand ( n13247 , n13245 , n13246 );
nand ( n13248 , n13244 , n13247 );
not ( n13249 , n13248 );
not ( n13250 , n13249 );
and ( n13251 , n13237 , n13250 );
and ( n13252 , n13236 , n13249 );
nor ( n13253 , n13251 , n13252 );
buf ( n13254 , n13253 );
not ( n13255 , n13254 );
buf ( n13256 , n5342 );
buf ( n13257 , n13256 );
not ( n13258 , n13257 );
buf ( n13259 , n5343 );
buf ( n13260 , n5344 );
buf ( n13261 , n13260 );
not ( n13262 , n13261 );
buf ( n13263 , n5345 );
not ( n13264 , n13263 );
not ( n13265 , n13264 );
or ( n13266 , n13262 , n13265 );
not ( n13267 , n13260 );
buf ( n13268 , n13263 );
nand ( n13269 , n13267 , n13268 );
nand ( n13270 , n13266 , n13269 );
xor ( n13271 , n13259 , n13270 );
buf ( n13272 , n5346 );
buf ( n13273 , n5347 );
not ( n13274 , n13273 );
xor ( n13275 , n13272 , n13274 );
buf ( n13276 , n5348 );
nand ( n13277 , n7293 , n13276 );
xnor ( n13278 , n13275 , n13277 );
xnor ( n13279 , n13271 , n13278 );
not ( n13280 , n13279 );
not ( n13281 , n13280 );
or ( n13282 , n13258 , n13281 );
or ( n13283 , n13280 , n13257 );
nand ( n13284 , n13282 , n13283 );
not ( n13285 , n13284 );
and ( n13286 , n13255 , n13285 );
and ( n13287 , n13254 , n13284 );
nor ( n13288 , n13286 , n13287 );
not ( n13289 , n13288 );
nand ( n13290 , n13214 , n13289 );
not ( n13291 , n13290 );
xor ( n13292 , n12320 , n12339 );
not ( n13293 , n12329 );
xor ( n13294 , n13292 , n13293 );
buf ( n13295 , n5349 );
nand ( n13296 , n7258 , n13295 );
buf ( n13297 , n5350 );
buf ( n13298 , n13297 );
and ( n13299 , n13296 , n13298 );
not ( n13300 , n13296 );
not ( n13301 , n13297 );
and ( n13302 , n13300 , n13301 );
nor ( n13303 , n13299 , n13302 );
nor ( n13304 , n13294 , n13303 );
not ( n13305 , n13304 );
nand ( n13306 , n13303 , n13294 );
nand ( n13307 , n13305 , n13306 );
not ( n13308 , n12376 );
and ( n13309 , n13307 , n13308 );
not ( n13310 , n13307 );
and ( n13311 , n13310 , n12379 );
nor ( n13312 , n13309 , n13311 );
not ( n13313 , n13312 );
and ( n13314 , n13291 , n13313 );
and ( n13315 , n13290 , n13312 );
nor ( n13316 , n13314 , n13315 );
and ( n13317 , n13202 , n13316 );
not ( n13318 , n13202 );
not ( n13319 , n13316 );
and ( n13320 , n13318 , n13319 );
nor ( n13321 , n13317 , n13320 );
xor ( n13322 , n12843 , n13321 );
buf ( n13323 , n13322 );
and ( n13324 , n12405 , n13323 );
not ( n13325 , n12405 );
not ( n13326 , n13321 );
not ( n13327 , n13326 );
not ( n13328 , n12843 );
not ( n13329 , n13328 );
or ( n13330 , n13327 , n13329 );
nand ( n13331 , n13321 , n12843 );
nand ( n13332 , n13330 , n13331 );
buf ( n13333 , n13332 );
and ( n13334 , n13325 , n13333 );
nor ( n13335 , n13324 , n13334 );
not ( n13336 , n13335 );
nand ( n13337 , n11304 , n13336 );
buf ( n13338 , n11337 );
buf ( n13339 , n6496 );
nor ( n13340 , n13338 , n13339 );
buf ( n13341 , n5351 );
not ( n13342 , n13341 );
not ( n13343 , n13342 );
or ( n13344 , n13340 , n13343 );
buf ( n13345 , n13344 );
buf ( n13346 , n13345 );
not ( n13347 , n13346 );
nand ( n13348 , n9095 , n13337 , n13347 );
buf ( n13349 , n13345 );
nor ( n13350 , n13335 , n13349 );
nand ( n13351 , n9094 , n13350 , n11304 );
and ( n13352 , n13340 , n13342 );
buf ( n13353 , n13352 );
buf ( n13354 , n5352 );
buf ( n13355 , n13354 );
nand ( n13356 , n13353 , n13355 );
nand ( n13357 , n13348 , n13351 , n13356 );
buf ( n13358 , n13357 );
buf ( n13359 , n13358 );
buf ( n13360 , n5353 );
buf ( n13361 , n13360 );
not ( n13362 , n13361 );
buf ( n13363 , n5354 );
not ( n13364 , n13363 );
not ( n13365 , n13364 );
or ( n13366 , n13362 , n13365 );
not ( n13367 , n13360 );
buf ( n13368 , n13363 );
nand ( n13369 , n13367 , n13368 );
nand ( n13370 , n13366 , n13369 );
buf ( n13371 , n5355 );
buf ( n13372 , n13371 );
and ( n13373 , n13370 , n13372 );
not ( n13374 , n13370 );
not ( n13375 , n13371 );
and ( n13376 , n13374 , n13375 );
nor ( n13377 , n13373 , n13376 );
buf ( n13378 , n5356 );
nand ( n13379 , n8454 , n13378 );
buf ( n13380 , n5357 );
buf ( n13381 , n13380 );
and ( n13382 , n13379 , n13381 );
not ( n13383 , n13379 );
not ( n13384 , n13380 );
and ( n13385 , n13383 , n13384 );
nor ( n13386 , n13382 , n13385 );
not ( n13387 , n13386 );
xor ( n13388 , n13377 , n13387 );
buf ( n13389 , n5358 );
nand ( n13390 , n11946 , n13389 );
buf ( n13391 , n5359 );
not ( n13392 , n13391 );
and ( n13393 , n13390 , n13392 );
not ( n13394 , n13390 );
buf ( n13395 , n13391 );
and ( n13396 , n13394 , n13395 );
nor ( n13397 , n13393 , n13396 );
xnor ( n13398 , n13388 , n13397 );
buf ( n13399 , n13398 );
not ( n13400 , n13399 );
buf ( n13401 , n5360 );
buf ( n13402 , n13401 );
not ( n13403 , n13402 );
buf ( n13404 , n5361 );
nand ( n13405 , n8454 , n13404 );
buf ( n13406 , n5362 );
buf ( n13407 , n13406 );
and ( n13408 , n13405 , n13407 );
not ( n13409 , n13405 );
not ( n13410 , n13406 );
and ( n13411 , n13409 , n13410 );
nor ( n13412 , n13408 , n13411 );
not ( n13413 , n13412 );
buf ( n13414 , n5363 );
nand ( n13415 , n6577 , n13414 );
buf ( n13416 , n5364 );
not ( n13417 , n13416 );
and ( n13418 , n13415 , n13417 );
not ( n13419 , n13415 );
buf ( n13420 , n13416 );
and ( n13421 , n13419 , n13420 );
nor ( n13422 , n13418 , n13421 );
not ( n13423 , n13422 );
or ( n13424 , n13413 , n13423 );
or ( n13425 , n13412 , n13422 );
nand ( n13426 , n13424 , n13425 );
buf ( n13427 , n5365 );
buf ( n13428 , n13427 );
not ( n13429 , n13428 );
buf ( n13430 , n5366 );
not ( n13431 , n13430 );
not ( n13432 , n13431 );
or ( n13433 , n13429 , n13432 );
not ( n13434 , n13427 );
buf ( n13435 , n13430 );
nand ( n13436 , n13434 , n13435 );
nand ( n13437 , n13433 , n13436 );
buf ( n13438 , n5367 );
not ( n13439 , n13438 );
and ( n13440 , n13437 , n13439 );
not ( n13441 , n13437 );
buf ( n13442 , n13438 );
and ( n13443 , n13441 , n13442 );
nor ( n13444 , n13440 , n13443 );
xor ( n13445 , n13426 , n13444 );
buf ( n13446 , n13445 );
not ( n13447 , n13446 );
or ( n13448 , n13403 , n13447 );
or ( n13449 , n13446 , n13402 );
nand ( n13450 , n13448 , n13449 );
not ( n13451 , n13450 );
or ( n13452 , n13400 , n13451 );
or ( n13453 , n13450 , n13399 );
nand ( n13454 , n13452 , n13453 );
not ( n13455 , n13454 );
xor ( n13456 , n9968 , n9978 );
xnor ( n13457 , n13456 , n9988 );
buf ( n13458 , n13457 );
xor ( n13459 , n10557 , n13458 );
xnor ( n13460 , n13459 , n10011 );
not ( n13461 , n13460 );
nand ( n13462 , n13455 , n13461 );
not ( n13463 , n13462 );
buf ( n13464 , n5368 );
buf ( n13465 , n13464 );
not ( n13466 , n13465 );
buf ( n13467 , n5369 );
not ( n13468 , n13467 );
not ( n13469 , n13468 );
or ( n13470 , n13466 , n13469 );
not ( n13471 , n13464 );
buf ( n13472 , n13467 );
nand ( n13473 , n13471 , n13472 );
nand ( n13474 , n13470 , n13473 );
buf ( n13475 , n5370 );
not ( n13476 , n13475 );
and ( n13477 , n13474 , n13476 );
not ( n13478 , n13474 );
buf ( n13479 , n13475 );
and ( n13480 , n13478 , n13479 );
nor ( n13481 , n13477 , n13480 );
buf ( n13482 , n5371 );
nand ( n13483 , n7698 , n13482 );
buf ( n13484 , n5372 );
buf ( n13485 , n13484 );
and ( n13486 , n13483 , n13485 );
not ( n13487 , n13483 );
not ( n13488 , n13484 );
and ( n13489 , n13487 , n13488 );
nor ( n13490 , n13486 , n13489 );
xor ( n13491 , n13481 , n13490 );
buf ( n13492 , n5373 );
nand ( n13493 , n10165 , n13492 );
buf ( n13494 , n5374 );
not ( n13495 , n13494 );
and ( n13496 , n13493 , n13495 );
not ( n13497 , n13493 );
buf ( n13498 , n13494 );
and ( n13499 , n13497 , n13498 );
nor ( n13500 , n13496 , n13499 );
buf ( n13501 , n13500 );
xnor ( n13502 , n13491 , n13501 );
buf ( n13503 , n5375 );
buf ( n13504 , n13503 );
nand ( n13505 , n13502 , n13504 );
not ( n13506 , n13505 );
nor ( n13507 , n13502 , n13504 );
nor ( n13508 , n13506 , n13507 );
not ( n13509 , n13508 );
not ( n13510 , n7219 );
not ( n13511 , n13510 );
not ( n13512 , n7206 );
or ( n13513 , n13511 , n13512 );
or ( n13514 , n7206 , n13510 );
nand ( n13515 , n13513 , n13514 );
buf ( n13516 , n13515 );
not ( n13517 , n13516 );
or ( n13518 , n13509 , n13517 );
or ( n13519 , n13516 , n13508 );
nand ( n13520 , n13518 , n13519 );
not ( n13521 , n13520 );
not ( n13522 , n13521 );
not ( n13523 , n13522 );
and ( n13524 , n13463 , n13523 );
not ( n13525 , n13454 );
nand ( n13526 , n13525 , n13461 );
and ( n13527 , n13526 , n13522 );
nor ( n13528 , n13524 , n13527 );
buf ( n13529 , n13528 );
not ( n13530 , n13529 );
not ( n13531 , n11789 );
not ( n13532 , n13531 );
not ( n13533 , n11818 );
not ( n13534 , n13533 );
or ( n13535 , n13532 , n13534 );
nand ( n13536 , n11818 , n11789 );
nand ( n13537 , n13535 , n13536 );
not ( n13538 , n13537 );
not ( n13539 , n13538 );
not ( n13540 , n10342 );
not ( n13541 , n11154 );
or ( n13542 , n13540 , n13541 );
or ( n13543 , n11154 , n10342 );
nand ( n13544 , n13542 , n13543 );
not ( n13545 , n13544 );
and ( n13546 , n13539 , n13545 );
buf ( n13547 , n13538 );
and ( n13548 , n13547 , n13544 );
nor ( n13549 , n13546 , n13548 );
not ( n13550 , n8786 );
not ( n13551 , n13550 );
buf ( n13552 , n5376 );
buf ( n13553 , n13552 );
not ( n13554 , n13553 );
not ( n13555 , n11187 );
buf ( n13556 , n5377 );
not ( n13557 , n13556 );
not ( n13558 , n13557 );
or ( n13559 , n13555 , n13558 );
not ( n13560 , n11186 );
buf ( n13561 , n13556 );
nand ( n13562 , n13560 , n13561 );
nand ( n13563 , n13559 , n13562 );
and ( n13564 , n13563 , n11863 );
not ( n13565 , n13563 );
not ( n13566 , n11862 );
and ( n13567 , n13565 , n13566 );
nor ( n13568 , n13564 , n13567 );
not ( n13569 , n13568 );
buf ( n13570 , n5378 );
nand ( n13571 , n8375 , n13570 );
buf ( n13572 , n5379 );
buf ( n13573 , n13572 );
and ( n13574 , n13571 , n13573 );
not ( n13575 , n13571 );
not ( n13576 , n13572 );
and ( n13577 , n13575 , n13576 );
nor ( n13578 , n13574 , n13577 );
buf ( n13579 , n13578 );
xor ( n13580 , n13569 , n13579 );
buf ( n13581 , n6577 );
buf ( n13582 , n5380 );
nand ( n13583 , n13581 , n13582 );
buf ( n13584 , n5381 );
not ( n13585 , n13584 );
and ( n13586 , n13583 , n13585 );
not ( n13587 , n13583 );
buf ( n13588 , n13584 );
and ( n13589 , n13587 , n13588 );
nor ( n13590 , n13586 , n13589 );
xnor ( n13591 , n13580 , n13590 );
not ( n13592 , n13591 );
or ( n13593 , n13554 , n13592 );
xor ( n13594 , n13568 , n13578 );
xnor ( n13595 , n13594 , n13590 );
not ( n13596 , n13552 );
nand ( n13597 , n13595 , n13596 );
nand ( n13598 , n13593 , n13597 );
not ( n13599 , n13598 );
and ( n13600 , n13551 , n13599 );
and ( n13601 , n13550 , n13598 );
nor ( n13602 , n13600 , n13601 );
not ( n13603 , n13602 );
nand ( n13604 , n13549 , n13603 );
buf ( n13605 , n5382 );
buf ( n13606 , n13605 );
buf ( n13607 , n5383 );
buf ( n13608 , n13607 );
not ( n13609 , n13608 );
buf ( n13610 , n5384 );
not ( n13611 , n13610 );
not ( n13612 , n13611 );
or ( n13613 , n13609 , n13612 );
not ( n13614 , n13607 );
buf ( n13615 , n13610 );
nand ( n13616 , n13614 , n13615 );
nand ( n13617 , n13613 , n13616 );
xor ( n13618 , n13606 , n13617 );
buf ( n13619 , n5385 );
nand ( n13620 , n6633 , n13619 );
buf ( n13621 , n5386 );
buf ( n13622 , n13621 );
and ( n13623 , n13620 , n13622 );
not ( n13624 , n13620 );
not ( n13625 , n13621 );
and ( n13626 , n13624 , n13625 );
nor ( n13627 , n13623 , n13626 );
not ( n13628 , n13627 );
buf ( n13629 , n5387 );
nand ( n13630 , n6815 , n13629 );
buf ( n13631 , n5388 );
not ( n13632 , n13631 );
and ( n13633 , n13630 , n13632 );
not ( n13634 , n13630 );
buf ( n13635 , n13631 );
and ( n13636 , n13634 , n13635 );
nor ( n13637 , n13633 , n13636 );
not ( n13638 , n13637 );
or ( n13639 , n13628 , n13638 );
or ( n13640 , n13627 , n13637 );
nand ( n13641 , n13639 , n13640 );
xnor ( n13642 , n13618 , n13641 );
not ( n13643 , n13642 );
buf ( n13644 , n5389 );
buf ( n13645 , n13644 );
not ( n13646 , n13645 );
buf ( n13647 , n5390 );
not ( n13648 , n13647 );
not ( n13649 , n13648 );
or ( n13650 , n13646 , n13649 );
not ( n13651 , n13644 );
buf ( n13652 , n13647 );
nand ( n13653 , n13651 , n13652 );
nand ( n13654 , n13650 , n13653 );
buf ( n13655 , n5391 );
buf ( n13656 , n13655 );
and ( n13657 , n13654 , n13656 );
not ( n13658 , n13654 );
not ( n13659 , n13655 );
and ( n13660 , n13658 , n13659 );
nor ( n13661 , n13657 , n13660 );
buf ( n13662 , n5392 );
nand ( n13663 , n6815 , n13662 );
buf ( n13664 , n5393 );
xor ( n13665 , n13663 , n13664 );
xor ( n13666 , n13661 , n13665 );
buf ( n13667 , n5394 );
nand ( n13668 , n8260 , n13667 );
buf ( n13669 , n5395 );
not ( n13670 , n13669 );
and ( n13671 , n13668 , n13670 );
not ( n13672 , n13668 );
buf ( n13673 , n13669 );
and ( n13674 , n13672 , n13673 );
nor ( n13675 , n13671 , n13674 );
xnor ( n13676 , n13666 , n13675 );
not ( n13677 , n13676 );
buf ( n13678 , n5396 );
nand ( n13679 , n7698 , n13678 );
buf ( n13680 , n5397 );
buf ( n13681 , n13680 );
and ( n13682 , n13679 , n13681 );
not ( n13683 , n13679 );
not ( n13684 , n13680 );
and ( n13685 , n13683 , n13684 );
nor ( n13686 , n13682 , n13685 );
buf ( n13687 , n13686 );
not ( n13688 , n13687 );
and ( n13689 , n13677 , n13688 );
not ( n13690 , n13676 );
not ( n13691 , n13690 );
and ( n13692 , n13691 , n13687 );
nor ( n13693 , n13689 , n13692 );
not ( n13694 , n13693 );
and ( n13695 , n13643 , n13694 );
not ( n13696 , n13643 );
and ( n13697 , n13696 , n13693 );
nor ( n13698 , n13695 , n13697 );
not ( n13699 , n13698 );
and ( n13700 , n13604 , n13699 );
not ( n13701 , n13604 );
and ( n13702 , n13701 , n13698 );
nor ( n13703 , n13700 , n13702 );
not ( n13704 , n13703 );
not ( n13705 , n13704 );
buf ( n13706 , n5398 );
buf ( n13707 , n13706 );
not ( n13708 , n13707 );
not ( n13709 , n7450 );
or ( n13710 , n13708 , n13709 );
buf ( n13711 , n7449 );
not ( n13712 , n13711 );
or ( n13713 , n13712 , n13707 );
nand ( n13714 , n13710 , n13713 );
not ( n13715 , n13714 );
not ( n13716 , n7495 );
and ( n13717 , n13715 , n13716 );
buf ( n13718 , n7494 );
and ( n13719 , n13714 , n13718 );
nor ( n13720 , n13717 , n13719 );
buf ( n13721 , n5399 );
buf ( n13722 , n13721 );
not ( n13723 , n13722 );
buf ( n13724 , n11857 );
not ( n13725 , n13724 );
or ( n13726 , n13723 , n13725 );
not ( n13727 , n13722 );
nand ( n13728 , n13727 , n11858 );
nand ( n13729 , n13726 , n13728 );
not ( n13730 , n12897 );
not ( n13731 , n13730 );
and ( n13732 , n13729 , n13731 );
not ( n13733 , n13729 );
not ( n13734 , n12881 );
not ( n13735 , n12890 );
not ( n13736 , n12896 );
or ( n13737 , n13735 , n13736 );
or ( n13738 , n12890 , n12896 );
nand ( n13739 , n13737 , n13738 );
not ( n13740 , n13739 );
or ( n13741 , n13734 , n13740 );
or ( n13742 , n13739 , n12881 );
nand ( n13743 , n13741 , n13742 );
buf ( n13744 , n13743 );
and ( n13745 , n13733 , n13744 );
nor ( n13746 , n13732 , n13745 );
not ( n13747 , n13746 );
nand ( n13748 , n13720 , n13747 );
not ( n13749 , n13748 );
buf ( n13750 , n5400 );
buf ( n13751 , n13750 );
not ( n13752 , n13751 );
buf ( n13753 , n5401 );
not ( n13754 , n13753 );
not ( n13755 , n13754 );
or ( n13756 , n13752 , n13755 );
not ( n13757 , n13750 );
buf ( n13758 , n13753 );
nand ( n13759 , n13757 , n13758 );
nand ( n13760 , n13756 , n13759 );
buf ( n13761 , n5402 );
not ( n13762 , n13761 );
and ( n13763 , n13760 , n13762 );
not ( n13764 , n13760 );
buf ( n13765 , n13761 );
and ( n13766 , n13764 , n13765 );
nor ( n13767 , n13763 , n13766 );
buf ( n13768 , n5403 );
nand ( n13769 , n6502 , n13768 );
buf ( n13770 , n5404 );
buf ( n13771 , n13770 );
and ( n13772 , n13769 , n13771 );
not ( n13773 , n13769 );
not ( n13774 , n13770 );
and ( n13775 , n13773 , n13774 );
nor ( n13776 , n13772 , n13775 );
xor ( n13777 , n13767 , n13776 );
buf ( n13778 , n5405 );
nand ( n13779 , n7912 , n13778 );
not ( n13780 , n13354 );
and ( n13781 , n13779 , n13780 );
not ( n13782 , n13779 );
and ( n13783 , n13782 , n13355 );
nor ( n13784 , n13781 , n13783 );
xor ( n13785 , n13777 , n13784 );
not ( n13786 , n13785 );
not ( n13787 , n13786 );
buf ( n13788 , n5406 );
buf ( n13789 , n13788 );
not ( n13790 , n13789 );
buf ( n13791 , n5407 );
nand ( n13792 , n8966 , n13791 );
buf ( n13793 , n5408 );
buf ( n13794 , n13793 );
and ( n13795 , n13792 , n13794 );
not ( n13796 , n13792 );
not ( n13797 , n13793 );
and ( n13798 , n13796 , n13797 );
nor ( n13799 , n13795 , n13798 );
not ( n13800 , n13799 );
buf ( n13801 , n5409 );
nand ( n13802 , n8954 , n13801 );
buf ( n13803 , n5410 );
not ( n13804 , n13803 );
and ( n13805 , n13802 , n13804 );
not ( n13806 , n13802 );
buf ( n13807 , n13803 );
and ( n13808 , n13806 , n13807 );
nor ( n13809 , n13805 , n13808 );
not ( n13810 , n13809 );
or ( n13811 , n13800 , n13810 );
or ( n13812 , n13799 , n13809 );
nand ( n13813 , n13811 , n13812 );
buf ( n13814 , n5411 );
buf ( n13815 , n13814 );
not ( n13816 , n13815 );
buf ( n13817 , n5412 );
not ( n13818 , n13817 );
not ( n13819 , n13818 );
or ( n13820 , n13816 , n13819 );
not ( n13821 , n13814 );
buf ( n13822 , n13817 );
nand ( n13823 , n13821 , n13822 );
nand ( n13824 , n13820 , n13823 );
buf ( n13825 , n5413 );
not ( n13826 , n13825 );
and ( n13827 , n13824 , n13826 );
not ( n13828 , n13824 );
buf ( n13829 , n13825 );
and ( n13830 , n13828 , n13829 );
nor ( n13831 , n13827 , n13830 );
xor ( n13832 , n13813 , n13831 );
not ( n13833 , n13832 );
or ( n13834 , n13790 , n13833 );
not ( n13835 , n13809 );
xor ( n13836 , n13831 , n13835 );
buf ( n13837 , n13799 );
xnor ( n13838 , n13836 , n13837 );
not ( n13839 , n13788 );
nand ( n13840 , n13838 , n13839 );
nand ( n13841 , n13834 , n13840 );
not ( n13842 , n13841 );
or ( n13843 , n13787 , n13842 );
or ( n13844 , n13841 , n13786 );
nand ( n13845 , n13843 , n13844 );
buf ( n13846 , n13845 );
not ( n13847 , n13846 );
and ( n13848 , n13749 , n13847 );
and ( n13849 , n13748 , n13846 );
nor ( n13850 , n13848 , n13849 );
not ( n13851 , n13850 );
not ( n13852 , n13851 );
or ( n13853 , n13705 , n13852 );
nand ( n13854 , n13850 , n13703 );
nand ( n13855 , n13853 , n13854 );
buf ( n13856 , n5414 );
buf ( n13857 , n13856 );
not ( n13858 , n9643 );
xor ( n13859 , n13857 , n13858 );
xnor ( n13860 , n13859 , n9598 );
buf ( n13861 , n5415 );
buf ( n13862 , n13861 );
not ( n13863 , n13862 );
not ( n13864 , n9181 );
or ( n13865 , n13863 , n13864 );
or ( n13866 , n9181 , n13862 );
nand ( n13867 , n13865 , n13866 );
buf ( n13868 , n5416 );
buf ( n13869 , n13868 );
not ( n13870 , n13869 );
buf ( n13871 , n5417 );
not ( n13872 , n13871 );
not ( n13873 , n13872 );
or ( n13874 , n13870 , n13873 );
not ( n13875 , n13868 );
buf ( n13876 , n13871 );
nand ( n13877 , n13875 , n13876 );
nand ( n13878 , n13874 , n13877 );
buf ( n13879 , n5418 );
buf ( n13880 , n13879 );
and ( n13881 , n13878 , n13880 );
not ( n13882 , n13878 );
not ( n13883 , n13879 );
and ( n13884 , n13882 , n13883 );
nor ( n13885 , n13881 , n13884 );
buf ( n13886 , n5419 );
nand ( n13887 , n8124 , n13886 );
buf ( n13888 , n5420 );
buf ( n13889 , n13888 );
and ( n13890 , n13887 , n13889 );
not ( n13891 , n13887 );
not ( n13892 , n13888 );
and ( n13893 , n13891 , n13892 );
nor ( n13894 , n13890 , n13893 );
xor ( n13895 , n13885 , n13894 );
buf ( n13896 , n5421 );
nand ( n13897 , n8125 , n13896 );
buf ( n13898 , n5422 );
not ( n13899 , n13898 );
and ( n13900 , n13897 , n13899 );
not ( n13901 , n13897 );
buf ( n13902 , n13898 );
and ( n13903 , n13901 , n13902 );
nor ( n13904 , n13900 , n13903 );
xnor ( n13905 , n13895 , n13904 );
not ( n13906 , n13905 );
not ( n13907 , n13906 );
and ( n13908 , n13867 , n13907 );
not ( n13909 , n13867 );
and ( n13910 , n13909 , n13906 );
nor ( n13911 , n13908 , n13910 );
not ( n13912 , n13911 );
nand ( n13913 , n13860 , n13912 );
not ( n13914 , n13913 );
buf ( n13915 , n5423 );
buf ( n13916 , n13915 );
buf ( n13917 , n5424 );
buf ( n13918 , n13917 );
not ( n13919 , n13918 );
buf ( n13920 , n5425 );
not ( n13921 , n13920 );
not ( n13922 , n13921 );
or ( n13923 , n13919 , n13922 );
not ( n13924 , n13917 );
buf ( n13925 , n13920 );
nand ( n13926 , n13924 , n13925 );
nand ( n13927 , n13923 , n13926 );
xor ( n13928 , n13916 , n13927 );
buf ( n13929 , n5426 );
buf ( n13930 , n5427 );
xor ( n13931 , n13929 , n13930 );
buf ( n13932 , n5428 );
nand ( n13933 , n11847 , n13932 );
xnor ( n13934 , n13931 , n13933 );
xnor ( n13935 , n13928 , n13934 );
buf ( n13936 , n13935 );
not ( n13937 , n13936 );
not ( n13938 , n9511 );
buf ( n13939 , n5429 );
nand ( n13940 , n7344 , n13939 );
buf ( n13941 , n5430 );
buf ( n13942 , n13941 );
and ( n13943 , n13940 , n13942 );
not ( n13944 , n13940 );
not ( n13945 , n13941 );
and ( n13946 , n13944 , n13945 );
nor ( n13947 , n13943 , n13946 );
not ( n13948 , n13947 );
buf ( n13949 , n5431 );
nand ( n13950 , n6871 , n13949 );
buf ( n13951 , n5432 );
not ( n13952 , n13951 );
and ( n13953 , n13950 , n13952 );
not ( n13954 , n13950 );
buf ( n13955 , n13951 );
and ( n13956 , n13954 , n13955 );
nor ( n13957 , n13953 , n13956 );
not ( n13958 , n13957 );
or ( n13959 , n13948 , n13958 );
or ( n13960 , n13947 , n13957 );
nand ( n13961 , n13959 , n13960 );
buf ( n13962 , n5433 );
buf ( n13963 , n13962 );
not ( n13964 , n13963 );
buf ( n13965 , n5434 );
not ( n13966 , n13965 );
not ( n13967 , n13966 );
or ( n13968 , n13964 , n13967 );
not ( n13969 , n13962 );
buf ( n13970 , n13965 );
nand ( n13971 , n13969 , n13970 );
nand ( n13972 , n13968 , n13971 );
buf ( n13973 , n5435 );
not ( n13974 , n13973 );
and ( n13975 , n13972 , n13974 );
not ( n13976 , n13972 );
buf ( n13977 , n13973 );
and ( n13978 , n13976 , n13977 );
nor ( n13979 , n13975 , n13978 );
and ( n13980 , n13961 , n13979 );
not ( n13981 , n13961 );
not ( n13982 , n13979 );
and ( n13983 , n13981 , n13982 );
nor ( n13984 , n13980 , n13983 );
not ( n13985 , n13984 );
or ( n13986 , n13938 , n13985 );
not ( n13987 , n9511 );
not ( n13988 , n13957 );
xor ( n13989 , n13979 , n13988 );
buf ( n13990 , n13947 );
xnor ( n13991 , n13989 , n13990 );
nand ( n13992 , n13987 , n13991 );
nand ( n13993 , n13986 , n13992 );
not ( n13994 , n13993 );
and ( n13995 , n13937 , n13994 );
and ( n13996 , n13936 , n13993 );
nor ( n13997 , n13995 , n13996 );
not ( n13998 , n13997 );
not ( n13999 , n13998 );
and ( n14000 , n13914 , n13999 );
and ( n14001 , n13913 , n13998 );
nor ( n14002 , n14000 , n14001 );
not ( n14003 , n14002 );
and ( n14004 , n13855 , n14003 );
not ( n14005 , n13855 );
and ( n14006 , n14005 , n14002 );
nor ( n14007 , n14004 , n14006 );
nand ( n14008 , n13454 , n13521 );
not ( n14009 , n14008 );
buf ( n14010 , n6716 );
not ( n14011 , n14010 );
not ( n14012 , n12951 );
buf ( n14013 , n5436 );
not ( n14014 , n14013 );
not ( n14015 , n14014 );
or ( n14016 , n14012 , n14015 );
not ( n14017 , n12950 );
buf ( n14018 , n14013 );
nand ( n14019 , n14017 , n14018 );
nand ( n14020 , n14016 , n14019 );
buf ( n14021 , n5437 );
not ( n14022 , n14021 );
and ( n14023 , n14020 , n14022 );
not ( n14024 , n14020 );
buf ( n14025 , n14021 );
and ( n14026 , n14024 , n14025 );
nor ( n14027 , n14023 , n14026 );
buf ( n14028 , n5438 );
nand ( n14029 , n6927 , n14028 );
buf ( n14030 , n5439 );
buf ( n14031 , n14030 );
and ( n14032 , n14029 , n14031 );
not ( n14033 , n14029 );
not ( n14034 , n14030 );
and ( n14035 , n14033 , n14034 );
nor ( n14036 , n14032 , n14035 );
xor ( n14037 , n14027 , n14036 );
buf ( n14038 , n5440 );
nand ( n14039 , n8455 , n14038 );
buf ( n14040 , n5441 );
not ( n14041 , n14040 );
and ( n14042 , n14039 , n14041 );
not ( n14043 , n14039 );
buf ( n14044 , n14040 );
and ( n14045 , n14043 , n14044 );
nor ( n14046 , n14042 , n14045 );
xnor ( n14047 , n14037 , n14046 );
not ( n14048 , n14047 );
not ( n14049 , n14048 );
or ( n14050 , n14011 , n14049 );
buf ( n14051 , n14047 );
not ( n14052 , n14051 );
or ( n14053 , n14052 , n14010 );
nand ( n14054 , n14050 , n14053 );
buf ( n14055 , n5442 );
buf ( n14056 , n14055 );
not ( n14057 , n14056 );
buf ( n14058 , n5443 );
not ( n14059 , n14058 );
not ( n14060 , n14059 );
or ( n14061 , n14057 , n14060 );
not ( n14062 , n14055 );
buf ( n14063 , n14058 );
nand ( n14064 , n14062 , n14063 );
nand ( n14065 , n14061 , n14064 );
buf ( n14066 , n5444 );
not ( n14067 , n14066 );
and ( n14068 , n14065 , n14067 );
not ( n14069 , n14065 );
buf ( n14070 , n14066 );
and ( n14071 , n14069 , n14070 );
nor ( n14072 , n14068 , n14071 );
buf ( n14073 , n5445 );
nand ( n14074 , n6577 , n14073 );
buf ( n14075 , n5446 );
buf ( n14076 , n14075 );
and ( n14077 , n14074 , n14076 );
not ( n14078 , n14074 );
not ( n14079 , n14075 );
and ( n14080 , n14078 , n14079 );
nor ( n14081 , n14077 , n14080 );
xor ( n14082 , n14072 , n14081 );
buf ( n14083 , n5447 );
nand ( n14084 , n10383 , n14083 );
buf ( n14085 , n5448 );
buf ( n14086 , n14085 );
and ( n14087 , n14084 , n14086 );
not ( n14088 , n14084 );
not ( n14089 , n14085 );
and ( n14090 , n14088 , n14089 );
nor ( n14091 , n14087 , n14090 );
xnor ( n14092 , n14082 , n14091 );
not ( n14093 , n14092 );
not ( n14094 , n14093 );
not ( n14095 , n14094 );
xor ( n14096 , n14054 , n14095 );
not ( n14097 , n14096 );
not ( n14098 , n14097 );
and ( n14099 , n14009 , n14098 );
and ( n14100 , n14008 , n14097 );
nor ( n14101 , n14099 , n14100 );
not ( n14102 , n14101 );
buf ( n14103 , n5449 );
nand ( n14104 , n6577 , n14103 );
buf ( n14105 , n5450 );
buf ( n14106 , n14105 );
and ( n14107 , n14104 , n14106 );
not ( n14108 , n14104 );
not ( n14109 , n14105 );
and ( n14110 , n14108 , n14109 );
nor ( n14111 , n14107 , n14110 );
buf ( n14112 , n14111 );
buf ( n14113 , n5451 );
buf ( n14114 , n14113 );
not ( n14115 , n14114 );
buf ( n14116 , n5452 );
not ( n14117 , n14116 );
not ( n14118 , n14117 );
or ( n14119 , n14115 , n14118 );
not ( n14120 , n14113 );
buf ( n14121 , n14116 );
nand ( n14122 , n14120 , n14121 );
nand ( n14123 , n14119 , n14122 );
buf ( n14124 , n5453 );
buf ( n14125 , n14124 );
and ( n14126 , n14123 , n14125 );
not ( n14127 , n14123 );
not ( n14128 , n14124 );
and ( n14129 , n14127 , n14128 );
nor ( n14130 , n14126 , n14129 );
buf ( n14131 , n5454 );
nand ( n14132 , n6647 , n14131 );
buf ( n14133 , n5455 );
buf ( n14134 , n14133 );
and ( n14135 , n14132 , n14134 );
not ( n14136 , n14132 );
not ( n14137 , n14133 );
and ( n14138 , n14136 , n14137 );
nor ( n14139 , n14135 , n14138 );
xor ( n14140 , n14130 , n14139 );
buf ( n14141 , n5456 );
nand ( n14142 , n7014 , n14141 );
buf ( n14143 , n5457 );
buf ( n14144 , n14143 );
and ( n14145 , n14142 , n14144 );
not ( n14146 , n14142 );
not ( n14147 , n14143 );
and ( n14148 , n14146 , n14147 );
nor ( n14149 , n14145 , n14148 );
not ( n14150 , n14149 );
xnor ( n14151 , n14140 , n14150 );
buf ( n14152 , n14151 );
not ( n14153 , n14152 );
xor ( n14154 , n14112 , n14153 );
buf ( n14155 , n5458 );
buf ( n14156 , n5459 );
buf ( n14157 , n14156 );
not ( n14158 , n14157 );
buf ( n14159 , n5460 );
not ( n14160 , n14159 );
not ( n14161 , n14160 );
or ( n14162 , n14158 , n14161 );
not ( n14163 , n14156 );
buf ( n14164 , n14159 );
nand ( n14165 , n14163 , n14164 );
nand ( n14166 , n14162 , n14165 );
xor ( n14167 , n14155 , n14166 );
buf ( n14168 , n5461 );
buf ( n14169 , n5462 );
xor ( n14170 , n14168 , n14169 );
buf ( n14171 , n5463 );
nand ( n14172 , n6719 , n14171 );
xnor ( n14173 , n14170 , n14172 );
xnor ( n14174 , n14167 , n14173 );
not ( n14175 , n14174 );
xnor ( n14176 , n14154 , n14175 );
not ( n14177 , n14176 );
not ( n14178 , n14177 );
buf ( n14179 , n5464 );
buf ( n14180 , n14179 );
not ( n14181 , n14180 );
buf ( n14182 , n5465 );
buf ( n14183 , n14182 );
not ( n14184 , n14183 );
buf ( n14185 , n5466 );
not ( n14186 , n14185 );
not ( n14187 , n14186 );
or ( n14188 , n14184 , n14187 );
not ( n14189 , n14182 );
buf ( n14190 , n14185 );
nand ( n14191 , n14189 , n14190 );
nand ( n14192 , n14188 , n14191 );
buf ( n14193 , n5467 );
buf ( n14194 , n14193 );
and ( n14195 , n14192 , n14194 );
not ( n14196 , n14192 );
not ( n14197 , n14193 );
and ( n14198 , n14196 , n14197 );
nor ( n14199 , n14195 , n14198 );
buf ( n14200 , n5468 );
nand ( n14201 , n7868 , n14200 );
buf ( n14202 , n5469 );
not ( n14203 , n14202 );
and ( n14204 , n14201 , n14203 );
not ( n14205 , n14201 );
buf ( n14206 , n14202 );
and ( n14207 , n14205 , n14206 );
nor ( n14208 , n14204 , n14207 );
xor ( n14209 , n14199 , n14208 );
buf ( n14210 , n5470 );
nand ( n14211 , n6973 , n14210 );
buf ( n14212 , n5471 );
not ( n14213 , n14212 );
and ( n14214 , n14211 , n14213 );
not ( n14215 , n14211 );
buf ( n14216 , n14212 );
and ( n14217 , n14215 , n14216 );
nor ( n14218 , n14214 , n14217 );
xnor ( n14219 , n14209 , n14218 );
not ( n14220 , n14219 );
not ( n14221 , n14220 );
not ( n14222 , n14221 );
or ( n14223 , n14181 , n14222 );
buf ( n14224 , n14219 );
not ( n14225 , n14224 );
not ( n14226 , n14179 );
nand ( n14227 , n14225 , n14226 );
nand ( n14228 , n14223 , n14227 );
buf ( n14229 , n5472 );
buf ( n14230 , n14229 );
not ( n14231 , n14230 );
buf ( n14232 , n5473 );
not ( n14233 , n14232 );
not ( n14234 , n14233 );
or ( n14235 , n14231 , n14234 );
not ( n14236 , n14229 );
buf ( n14237 , n14232 );
nand ( n14238 , n14236 , n14237 );
nand ( n14239 , n14235 , n14238 );
buf ( n14240 , n5474 );
not ( n14241 , n14240 );
and ( n14242 , n14239 , n14241 );
not ( n14243 , n14239 );
buf ( n14244 , n14240 );
and ( n14245 , n14243 , n14244 );
nor ( n14246 , n14242 , n14245 );
buf ( n14247 , n5475 );
nand ( n14248 , n7977 , n14247 );
buf ( n14249 , n5476 );
buf ( n14250 , n14249 );
and ( n14251 , n14248 , n14250 );
not ( n14252 , n14248 );
not ( n14253 , n14249 );
and ( n14254 , n14252 , n14253 );
nor ( n14255 , n14251 , n14254 );
xor ( n14256 , n14246 , n14255 );
buf ( n14257 , n5477 );
nand ( n14258 , n7258 , n14257 );
buf ( n14259 , n5478 );
buf ( n14260 , n14259 );
and ( n14261 , n14258 , n14260 );
not ( n14262 , n14258 );
not ( n14263 , n14259 );
and ( n14264 , n14262 , n14263 );
nor ( n14265 , n14261 , n14264 );
not ( n14266 , n14265 );
xnor ( n14267 , n14256 , n14266 );
buf ( n14268 , n14267 );
and ( n14269 , n14228 , n14268 );
not ( n14270 , n14228 );
xor ( n14271 , n14246 , n14265 );
xnor ( n14272 , n14271 , n14255 );
buf ( n14273 , n14272 );
and ( n14274 , n14270 , n14273 );
nor ( n14275 , n14269 , n14274 );
not ( n14276 , n11981 );
not ( n14277 , n10824 );
not ( n14278 , n14277 );
or ( n14279 , n14276 , n14278 );
not ( n14280 , n14277 );
nand ( n14281 , n14280 , n11977 );
nand ( n14282 , n14279 , n14281 );
buf ( n14283 , n5479 );
buf ( n14284 , n14283 );
not ( n14285 , n14284 );
buf ( n14286 , n5480 );
not ( n14287 , n14286 );
not ( n14288 , n14287 );
or ( n14289 , n14285 , n14288 );
not ( n14290 , n14283 );
buf ( n14291 , n14286 );
nand ( n14292 , n14290 , n14291 );
nand ( n14293 , n14289 , n14292 );
not ( n14294 , n12300 );
and ( n14295 , n14293 , n14294 );
not ( n14296 , n14293 );
and ( n14297 , n14296 , n12301 );
nor ( n14298 , n14295 , n14297 );
xor ( n14299 , n14298 , n13303 );
buf ( n14300 , n5481 );
nand ( n14301 , n8675 , n14300 );
buf ( n14302 , n5482 );
buf ( n14303 , n14302 );
and ( n14304 , n14301 , n14303 );
not ( n14305 , n14301 );
not ( n14306 , n14302 );
and ( n14307 , n14305 , n14306 );
nor ( n14308 , n14304 , n14307 );
xnor ( n14309 , n14299 , n14308 );
buf ( n14310 , n14309 );
not ( n14311 , n14310 );
buf ( n14312 , n14311 );
not ( n14313 , n14312 );
and ( n14314 , n14282 , n14313 );
not ( n14315 , n14282 );
and ( n14316 , n14315 , n14312 );
nor ( n14317 , n14314 , n14316 );
nand ( n14318 , n14275 , n14317 );
not ( n14319 , n14318 );
or ( n14320 , n14178 , n14319 );
nand ( n14321 , n14275 , n14317 );
or ( n14322 , n14321 , n14177 );
nand ( n14323 , n14320 , n14322 );
not ( n14324 , n14323 );
or ( n14325 , n14102 , n14324 );
or ( n14326 , n14323 , n14101 );
nand ( n14327 , n14325 , n14326 );
buf ( n14328 , n14327 );
xnor ( n14329 , n14007 , n14328 );
not ( n14330 , n14329 );
not ( n14331 , n14330 );
or ( n14332 , n13530 , n14331 );
xor ( n14333 , n14002 , n13855 );
xor ( n14334 , n14333 , n14327 );
not ( n14335 , n14334 );
or ( n14336 , n14335 , n13529 );
nand ( n14337 , n14332 , n14336 );
not ( n14338 , n14337 );
buf ( n14339 , n5483 );
buf ( n14340 , n5484 );
nand ( n14341 , n6827 , n14340 );
buf ( n14342 , n5485 );
buf ( n14343 , n14342 );
and ( n14344 , n14341 , n14343 );
not ( n14345 , n14341 );
not ( n14346 , n14342 );
and ( n14347 , n14345 , n14346 );
nor ( n14348 , n14344 , n14347 );
xor ( n14349 , n14339 , n14348 );
buf ( n14350 , n5486 );
nand ( n14351 , n6557 , n14350 );
buf ( n14352 , n5487 );
not ( n14353 , n14352 );
and ( n14354 , n14351 , n14353 );
not ( n14355 , n14351 );
buf ( n14356 , n14352 );
and ( n14357 , n14355 , n14356 );
nor ( n14358 , n14354 , n14357 );
xnor ( n14359 , n14349 , n14358 );
not ( n14360 , n14359 );
buf ( n14361 , n5488 );
not ( n14362 , n14361 );
buf ( n14363 , n5489 );
buf ( n14364 , n14363 );
and ( n14365 , n14362 , n14364 );
not ( n14366 , n14362 );
not ( n14367 , n14363 );
and ( n14368 , n14366 , n14367 );
nor ( n14369 , n14365 , n14368 );
not ( n14370 , n14369 );
and ( n14371 , n14360 , n14370 );
and ( n14372 , n14359 , n14369 );
nor ( n14373 , n14371 , n14372 );
not ( n14374 , n14373 );
xor ( n14375 , n7076 , n14374 );
buf ( n14376 , n5490 );
buf ( n14377 , n5491 );
not ( n14378 , n14377 );
buf ( n14379 , n5492 );
buf ( n14380 , n14379 );
nand ( n14381 , n14378 , n14380 );
not ( n14382 , n14379 );
buf ( n14383 , n14377 );
nand ( n14384 , n14382 , n14383 );
and ( n14385 , n14381 , n14384 );
xor ( n14386 , n14376 , n14385 );
buf ( n14387 , n5493 );
buf ( n14388 , n5494 );
xor ( n14389 , n14387 , n14388 );
buf ( n14390 , n5495 );
nand ( n14391 , n8223 , n14390 );
xnor ( n14392 , n14389 , n14391 );
xnor ( n14393 , n14386 , n14392 );
xor ( n14394 , n14375 , n14393 );
not ( n14395 , n9669 );
xor ( n14396 , n12789 , n12808 );
xor ( n14397 , n14396 , n12798 );
not ( n14398 , n14397 );
or ( n14399 , n14395 , n14398 );
or ( n14400 , n14397 , n9669 );
nand ( n14401 , n14399 , n14400 );
not ( n14402 , n6526 );
and ( n14403 , n14401 , n14402 );
not ( n14404 , n14401 );
buf ( n14405 , n6525 );
not ( n14406 , n14405 );
and ( n14407 , n14404 , n14406 );
nor ( n14408 , n14403 , n14407 );
nand ( n14409 , n14394 , n14408 );
not ( n14410 , n14409 );
buf ( n14411 , n5496 );
buf ( n14412 , n14411 );
not ( n14413 , n14412 );
buf ( n14414 , n5497 );
not ( n14415 , n14414 );
not ( n14416 , n14415 );
or ( n14417 , n14413 , n14416 );
not ( n14418 , n14411 );
buf ( n14419 , n14414 );
nand ( n14420 , n14418 , n14419 );
nand ( n14421 , n14417 , n14420 );
and ( n14422 , n14421 , n8146 );
not ( n14423 , n14421 );
not ( n14424 , n8145 );
and ( n14425 , n14423 , n14424 );
nor ( n14426 , n14422 , n14425 );
buf ( n14427 , n5498 );
nand ( n14428 , n6770 , n14427 );
buf ( n14429 , n5499 );
buf ( n14430 , n14429 );
and ( n14431 , n14428 , n14430 );
not ( n14432 , n14428 );
not ( n14433 , n14429 );
and ( n14434 , n14432 , n14433 );
nor ( n14435 , n14431 , n14434 );
xor ( n14436 , n14426 , n14435 );
buf ( n14437 , n5500 );
nand ( n14438 , n8032 , n14437 );
buf ( n14439 , n5501 );
not ( n14440 , n14439 );
and ( n14441 , n14438 , n14440 );
not ( n14442 , n14438 );
buf ( n14443 , n14439 );
and ( n14444 , n14442 , n14443 );
nor ( n14445 , n14441 , n14444 );
xnor ( n14446 , n14436 , n14445 );
not ( n14447 , n14446 );
not ( n14448 , n14447 );
not ( n14449 , n14448 );
not ( n14450 , n14449 );
not ( n14451 , n6899 );
not ( n14452 , n13132 );
or ( n14453 , n14451 , n14452 );
or ( n14454 , n13132 , n6899 );
nand ( n14455 , n14453 , n14454 );
not ( n14456 , n14455 );
or ( n14457 , n14450 , n14456 );
not ( n14458 , n14448 );
or ( n14459 , n14455 , n14458 );
nand ( n14460 , n14457 , n14459 );
not ( n14461 , n14460 );
and ( n14462 , n14410 , n14461 );
not ( n14463 , n14408 );
not ( n14464 , n14463 );
nand ( n14465 , n14464 , n14394 );
and ( n14466 , n14465 , n14460 );
nor ( n14467 , n14462 , n14466 );
not ( n14468 , n14467 );
buf ( n14469 , n5502 );
buf ( n14470 , n14469 );
not ( n14471 , n14470 );
buf ( n14472 , n5503 );
not ( n14473 , n14472 );
not ( n14474 , n14473 );
or ( n14475 , n14471 , n14474 );
not ( n14476 , n14469 );
buf ( n14477 , n14472 );
nand ( n14478 , n14476 , n14477 );
nand ( n14479 , n14475 , n14478 );
buf ( n14480 , n5504 );
buf ( n14481 , n14480 );
and ( n14482 , n14479 , n14481 );
not ( n14483 , n14479 );
not ( n14484 , n14480 );
and ( n14485 , n14483 , n14484 );
nor ( n14486 , n14482 , n14485 );
buf ( n14487 , n5505 );
nand ( n14488 , n7563 , n14487 );
buf ( n14489 , n5506 );
not ( n14490 , n14489 );
and ( n14491 , n14488 , n14490 );
not ( n14492 , n14488 );
buf ( n14493 , n14489 );
and ( n14494 , n14492 , n14493 );
nor ( n14495 , n14491 , n14494 );
xor ( n14496 , n14486 , n14495 );
buf ( n14497 , n5507 );
nand ( n14498 , n10383 , n14497 );
buf ( n14499 , n5508 );
not ( n14500 , n14499 );
and ( n14501 , n14498 , n14500 );
not ( n14502 , n14498 );
buf ( n14503 , n14499 );
and ( n14504 , n14502 , n14503 );
nor ( n14505 , n14501 , n14504 );
xnor ( n14506 , n14496 , n14505 );
not ( n14507 , n14506 );
buf ( n14508 , n14507 );
not ( n14509 , n14508 );
not ( n14510 , n14509 );
not ( n14511 , n7961 );
buf ( n14512 , n5509 );
buf ( n14513 , n14512 );
not ( n14514 , n14513 );
buf ( n14515 , n5510 );
not ( n14516 , n14515 );
not ( n14517 , n14516 );
or ( n14518 , n14514 , n14517 );
not ( n14519 , n14512 );
buf ( n14520 , n14515 );
nand ( n14521 , n14519 , n14520 );
nand ( n14522 , n14518 , n14521 );
buf ( n14523 , n5511 );
not ( n14524 , n14523 );
and ( n14525 , n14522 , n14524 );
not ( n14526 , n14522 );
buf ( n14527 , n14523 );
and ( n14528 , n14526 , n14527 );
nor ( n14529 , n14525 , n14528 );
xor ( n14530 , n14529 , n11969 );
buf ( n14531 , n5512 );
nand ( n14532 , n9310 , n14531 );
buf ( n14533 , n5513 );
buf ( n14534 , n14533 );
and ( n14535 , n14532 , n14534 );
not ( n14536 , n14532 );
not ( n14537 , n14533 );
and ( n14538 , n14536 , n14537 );
nor ( n14539 , n14535 , n14538 );
xnor ( n14540 , n14530 , n14539 );
buf ( n14541 , n14540 );
not ( n14542 , n14541 );
or ( n14543 , n14511 , n14542 );
not ( n14544 , n14540 );
buf ( n14545 , n7960 );
nand ( n14546 , n14544 , n14545 );
nand ( n14547 , n14543 , n14546 );
not ( n14548 , n14547 );
or ( n14549 , n14510 , n14548 );
or ( n14550 , n14547 , n14509 );
nand ( n14551 , n14549 , n14550 );
not ( n14552 , n14551 );
not ( n14553 , n8427 );
not ( n14554 , n14553 );
buf ( n14555 , n5514 );
not ( n14556 , n14555 );
buf ( n14557 , n5515 );
buf ( n14558 , n14557 );
not ( n14559 , n14558 );
buf ( n14560 , n5516 );
not ( n14561 , n14560 );
not ( n14562 , n14561 );
or ( n14563 , n14559 , n14562 );
not ( n14564 , n14557 );
buf ( n14565 , n14560 );
nand ( n14566 , n14564 , n14565 );
nand ( n14567 , n14563 , n14566 );
not ( n14568 , n14567 );
xor ( n14569 , n14556 , n14568 );
buf ( n14570 , n5517 );
buf ( n14571 , n5518 );
xor ( n14572 , n14570 , n14571 );
buf ( n14573 , n7293 );
buf ( n14574 , n5519 );
nand ( n14575 , n14573 , n14574 );
xnor ( n14576 , n14572 , n14575 );
xnor ( n14577 , n14569 , n14576 );
not ( n14578 , n14577 );
or ( n14579 , n14554 , n14578 );
not ( n14580 , n14553 );
not ( n14581 , n14577 );
nand ( n14582 , n14580 , n14581 );
nand ( n14583 , n14579 , n14582 );
buf ( n14584 , n5520 );
buf ( n14585 , n14584 );
not ( n14586 , n14585 );
buf ( n14587 , n5521 );
not ( n14588 , n14587 );
not ( n14589 , n14588 );
or ( n14590 , n14586 , n14589 );
not ( n14591 , n14584 );
buf ( n14592 , n14587 );
nand ( n14593 , n14591 , n14592 );
nand ( n14594 , n14590 , n14593 );
not ( n14595 , n14594 );
buf ( n14596 , n5522 );
not ( n14597 , n14596 );
buf ( n14598 , n5523 );
nand ( n14599 , n6633 , n14598 );
buf ( n14600 , n5524 );
buf ( n14601 , n14600 );
and ( n14602 , n14599 , n14601 );
not ( n14603 , n14599 );
not ( n14604 , n14600 );
and ( n14605 , n14603 , n14604 );
nor ( n14606 , n14602 , n14605 );
xor ( n14607 , n14597 , n14606 );
buf ( n14608 , n5525 );
nand ( n14609 , n7868 , n14608 );
buf ( n14610 , n5526 );
buf ( n14611 , n14610 );
and ( n14612 , n14609 , n14611 );
not ( n14613 , n14609 );
not ( n14614 , n14610 );
and ( n14615 , n14613 , n14614 );
nor ( n14616 , n14612 , n14615 );
xnor ( n14617 , n14607 , n14616 );
not ( n14618 , n14617 );
not ( n14619 , n14618 );
or ( n14620 , n14595 , n14619 );
not ( n14621 , n14594 );
nand ( n14622 , n14617 , n14621 );
nand ( n14623 , n14620 , n14622 );
buf ( n14624 , n14623 );
and ( n14625 , n14583 , n14624 );
not ( n14626 , n14583 );
not ( n14627 , n14624 );
and ( n14628 , n14626 , n14627 );
nor ( n14629 , n14625 , n14628 );
nand ( n14630 , n14552 , n14629 );
buf ( n14631 , n5527 );
buf ( n14632 , n5528 );
buf ( n14633 , n14632 );
not ( n14634 , n14633 );
buf ( n14635 , n5529 );
not ( n14636 , n14635 );
not ( n14637 , n14636 );
or ( n14638 , n14634 , n14637 );
not ( n14639 , n14632 );
buf ( n14640 , n14635 );
nand ( n14641 , n14639 , n14640 );
nand ( n14642 , n14638 , n14641 );
xor ( n14643 , n14631 , n14642 );
buf ( n14644 , n5530 );
buf ( n14645 , n5531 );
not ( n14646 , n14645 );
xor ( n14647 , n14644 , n14646 );
buf ( n14648 , n5532 );
nand ( n14649 , n8223 , n14648 );
xnor ( n14650 , n14647 , n14649 );
xnor ( n14651 , n14643 , n14650 );
not ( n14652 , n14651 );
not ( n14653 , n14652 );
not ( n14654 , n11242 );
buf ( n14655 , n5533 );
buf ( n14656 , n14655 );
not ( n14657 , n14656 );
buf ( n14658 , n5534 );
not ( n14659 , n14658 );
not ( n14660 , n14659 );
or ( n14661 , n14657 , n14660 );
not ( n14662 , n14655 );
buf ( n14663 , n14658 );
nand ( n14664 , n14662 , n14663 );
nand ( n14665 , n14661 , n14664 );
buf ( n14666 , n5535 );
buf ( n14667 , n14666 );
and ( n14668 , n14665 , n14667 );
not ( n14669 , n14665 );
not ( n14670 , n14666 );
and ( n14671 , n14669 , n14670 );
nor ( n14672 , n14668 , n14671 );
xor ( n14673 , n14672 , n11888 );
buf ( n14674 , n5536 );
nand ( n14675 , n11688 , n14674 );
buf ( n14676 , n5537 );
not ( n14677 , n14676 );
and ( n14678 , n14675 , n14677 );
not ( n14679 , n14675 );
buf ( n14680 , n14676 );
and ( n14681 , n14679 , n14680 );
nor ( n14682 , n14678 , n14681 );
xnor ( n14683 , n14673 , n14682 );
not ( n14684 , n14683 );
not ( n14685 , n14684 );
or ( n14686 , n14654 , n14685 );
nand ( n14687 , n14683 , n11238 );
nand ( n14688 , n14686 , n14687 );
not ( n14689 , n14688 );
and ( n14690 , n14653 , n14689 );
buf ( n14691 , n14651 );
not ( n14692 , n14691 );
and ( n14693 , n14692 , n14688 );
nor ( n14694 , n14690 , n14693 );
buf ( n14695 , n14694 );
and ( n14696 , n14630 , n14695 );
not ( n14697 , n14630 );
not ( n14698 , n14695 );
and ( n14699 , n14697 , n14698 );
nor ( n14700 , n14696 , n14699 );
not ( n14701 , n14700 );
or ( n14702 , n14468 , n14701 );
or ( n14703 , n14700 , n14467 );
nand ( n14704 , n14702 , n14703 );
buf ( n14705 , n5538 );
nand ( n14706 , n6502 , n14705 );
buf ( n14707 , n5539 );
not ( n14708 , n14707 );
and ( n14709 , n14706 , n14708 );
not ( n14710 , n14706 );
buf ( n14711 , n14707 );
and ( n14712 , n14710 , n14711 );
nor ( n14713 , n14709 , n14712 );
buf ( n14714 , n8398 );
xor ( n14715 , n14713 , n14714 );
buf ( n14716 , n5540 );
buf ( n14717 , n14716 );
not ( n14718 , n14717 );
buf ( n14719 , n5541 );
not ( n14720 , n14719 );
not ( n14721 , n14720 );
or ( n14722 , n14718 , n14721 );
not ( n14723 , n14716 );
buf ( n14724 , n14719 );
nand ( n14725 , n14723 , n14724 );
nand ( n14726 , n14722 , n14725 );
not ( n14727 , n14726 );
buf ( n14728 , n5542 );
buf ( n14729 , n14728 );
buf ( n14730 , n5543 );
nand ( n14731 , n8454 , n14730 );
buf ( n14732 , n5544 );
buf ( n14733 , n14732 );
and ( n14734 , n14731 , n14733 );
not ( n14735 , n14731 );
not ( n14736 , n14732 );
and ( n14737 , n14735 , n14736 );
nor ( n14738 , n14734 , n14737 );
xor ( n14739 , n14729 , n14738 );
buf ( n14740 , n5545 );
nand ( n14741 , n8032 , n14740 );
buf ( n14742 , n5546 );
not ( n14743 , n14742 );
and ( n14744 , n14741 , n14743 );
not ( n14745 , n14741 );
buf ( n14746 , n14742 );
and ( n14747 , n14745 , n14746 );
nor ( n14748 , n14744 , n14747 );
xnor ( n14749 , n14739 , n14748 );
and ( n14750 , n14727 , n14749 );
not ( n14751 , n14727 );
not ( n14752 , n14749 );
and ( n14753 , n14751 , n14752 );
nor ( n14754 , n14750 , n14753 );
buf ( n14755 , n14754 );
xnor ( n14756 , n14715 , n14755 );
buf ( n14757 , n13215 );
not ( n14758 , n14757 );
not ( n14759 , n13707 );
buf ( n14760 , n5547 );
not ( n14761 , n14760 );
not ( n14762 , n14761 );
or ( n14763 , n14759 , n14762 );
not ( n14764 , n13706 );
buf ( n14765 , n14760 );
nand ( n14766 , n14764 , n14765 );
nand ( n14767 , n14763 , n14766 );
not ( n14768 , n7426 );
and ( n14769 , n14767 , n14768 );
not ( n14770 , n14767 );
and ( n14771 , n14770 , n7427 );
nor ( n14772 , n14769 , n14771 );
buf ( n14773 , n5548 );
nand ( n14774 , n7202 , n14773 );
buf ( n14775 , n5549 );
buf ( n14776 , n14775 );
and ( n14777 , n14774 , n14776 );
not ( n14778 , n14774 );
not ( n14779 , n14775 );
and ( n14780 , n14778 , n14779 );
nor ( n14781 , n14777 , n14780 );
xor ( n14782 , n14772 , n14781 );
buf ( n14783 , n5550 );
nand ( n14784 , n9310 , n14783 );
buf ( n14785 , n5551 );
buf ( n14786 , n14785 );
and ( n14787 , n14784 , n14786 );
not ( n14788 , n14784 );
not ( n14789 , n14785 );
and ( n14790 , n14788 , n14789 );
nor ( n14791 , n14787 , n14790 );
xnor ( n14792 , n14782 , n14791 );
buf ( n14793 , n14792 );
not ( n14794 , n14793 );
not ( n14795 , n14794 );
or ( n14796 , n14758 , n14795 );
not ( n14797 , n14792 );
buf ( n14798 , n14797 );
not ( n14799 , n14798 );
not ( n14800 , n14799 );
or ( n14801 , n14800 , n14757 );
nand ( n14802 , n14796 , n14801 );
buf ( n14803 , n5552 );
buf ( n14804 , n14803 );
not ( n14805 , n14804 );
not ( n14806 , n12912 );
or ( n14807 , n14805 , n14806 );
not ( n14808 , n14803 );
buf ( n14809 , n12911 );
nand ( n14810 , n14808 , n14809 );
nand ( n14811 , n14807 , n14810 );
buf ( n14812 , n5553 );
buf ( n14813 , n14812 );
and ( n14814 , n14811 , n14813 );
not ( n14815 , n14811 );
not ( n14816 , n14812 );
and ( n14817 , n14815 , n14816 );
nor ( n14818 , n14814 , n14817 );
buf ( n14819 , n5554 );
nand ( n14820 , n6770 , n14819 );
buf ( n14821 , n5555 );
buf ( n14822 , n14821 );
and ( n14823 , n14820 , n14822 );
not ( n14824 , n14820 );
not ( n14825 , n14821 );
and ( n14826 , n14824 , n14825 );
nor ( n14827 , n14823 , n14826 );
xor ( n14828 , n14818 , n14827 );
buf ( n14829 , n5556 );
nand ( n14830 , n8608 , n14829 );
buf ( n14831 , n5557 );
not ( n14832 , n14831 );
and ( n14833 , n14830 , n14832 );
not ( n14834 , n14830 );
buf ( n14835 , n14831 );
and ( n14836 , n14834 , n14835 );
nor ( n14837 , n14833 , n14836 );
xnor ( n14838 , n14828 , n14837 );
not ( n14839 , n14838 );
not ( n14840 , n14839 );
and ( n14841 , n14802 , n14840 );
not ( n14842 , n14802 );
not ( n14843 , n14827 );
xor ( n14844 , n14818 , n14843 );
xnor ( n14845 , n14844 , n14837 );
not ( n14846 , n14845 );
not ( n14847 , n14846 );
and ( n14848 , n14842 , n14847 );
nor ( n14849 , n14841 , n14848 );
not ( n14850 , n14849 );
nand ( n14851 , n14756 , n14850 );
xor ( n14852 , n10355 , n11155 );
xnor ( n14853 , n14852 , n7833 );
and ( n14854 , n14851 , n14853 );
not ( n14855 , n14851 );
not ( n14856 , n14853 );
and ( n14857 , n14855 , n14856 );
nor ( n14858 , n14854 , n14857 );
not ( n14859 , n14858 );
and ( n14860 , n14704 , n14859 );
not ( n14861 , n14704 );
and ( n14862 , n14861 , n14858 );
nor ( n14863 , n14860 , n14862 );
not ( n14864 , n7513 );
buf ( n14865 , n5558 );
nand ( n14866 , n6646 , n14865 );
buf ( n14867 , n5559 );
buf ( n14868 , n14867 );
and ( n14869 , n14866 , n14868 );
not ( n14870 , n14866 );
not ( n14871 , n14867 );
and ( n14872 , n14870 , n14871 );
nor ( n14873 , n14869 , n14872 );
not ( n14874 , n14873 );
buf ( n14875 , n5560 );
nand ( n14876 , n6927 , n14875 );
buf ( n14877 , n5561 );
not ( n14878 , n14877 );
and ( n14879 , n14876 , n14878 );
not ( n14880 , n14876 );
buf ( n14881 , n14877 );
and ( n14882 , n14880 , n14881 );
nor ( n14883 , n14879 , n14882 );
not ( n14884 , n14883 );
or ( n14885 , n14874 , n14884 );
or ( n14886 , n14873 , n14883 );
nand ( n14887 , n14885 , n14886 );
buf ( n14888 , n5562 );
buf ( n14889 , n14888 );
not ( n14890 , n14889 );
buf ( n14891 , n5563 );
not ( n14892 , n14891 );
not ( n14893 , n14892 );
or ( n14894 , n14890 , n14893 );
not ( n14895 , n14888 );
buf ( n14896 , n14891 );
nand ( n14897 , n14895 , n14896 );
nand ( n14898 , n14894 , n14897 );
buf ( n14899 , n5564 );
not ( n14900 , n14899 );
and ( n14901 , n14898 , n14900 );
not ( n14902 , n14898 );
buf ( n14903 , n14899 );
and ( n14904 , n14902 , n14903 );
nor ( n14905 , n14901 , n14904 );
buf ( n14906 , n14905 );
and ( n14907 , n14887 , n14906 );
not ( n14908 , n14887 );
not ( n14909 , n14906 );
and ( n14910 , n14908 , n14909 );
nor ( n14911 , n14907 , n14910 );
not ( n14912 , n14911 );
not ( n14913 , n14912 );
not ( n14914 , n14913 );
or ( n14915 , n14864 , n14914 );
xor ( n14916 , n14905 , n14873 );
not ( n14917 , n14883 );
xnor ( n14918 , n14916 , n14917 );
not ( n14919 , n14918 );
not ( n14920 , n14919 );
nand ( n14921 , n14920 , n7516 );
nand ( n14922 , n14915 , n14921 );
buf ( n14923 , n5565 );
not ( n14924 , n14923 );
buf ( n14925 , n5566 );
not ( n14926 , n14925 );
buf ( n14927 , n5567 );
buf ( n14928 , n14927 );
nand ( n14929 , n14926 , n14928 );
not ( n14930 , n14927 );
buf ( n14931 , n14925 );
nand ( n14932 , n14930 , n14931 );
and ( n14933 , n14929 , n14932 );
xor ( n14934 , n14924 , n14933 );
buf ( n14935 , n5568 );
buf ( n14936 , n5569 );
not ( n14937 , n14936 );
xor ( n14938 , n14935 , n14937 );
buf ( n14939 , n5570 );
nand ( n14940 , n9310 , n14939 );
xnor ( n14941 , n14938 , n14940 );
xnor ( n14942 , n14934 , n14941 );
buf ( n14943 , n14942 );
and ( n14944 , n14922 , n14943 );
not ( n14945 , n14922 );
buf ( n14946 , n14923 );
xor ( n14947 , n14946 , n14933 );
xnor ( n14948 , n14947 , n14941 );
buf ( n14949 , n14948 );
and ( n14950 , n14945 , n14949 );
nor ( n14951 , n14944 , n14950 );
not ( n14952 , n14951 );
buf ( n14953 , n13041 );
not ( n14954 , n14953 );
buf ( n14955 , n5571 );
buf ( n14956 , n14955 );
not ( n14957 , n14956 );
buf ( n14958 , n5572 );
not ( n14959 , n14958 );
not ( n14960 , n14959 );
or ( n14961 , n14957 , n14960 );
not ( n14962 , n14955 );
buf ( n14963 , n14958 );
nand ( n14964 , n14962 , n14963 );
nand ( n14965 , n14961 , n14964 );
buf ( n14966 , n5573 );
buf ( n14967 , n14966 );
and ( n14968 , n14965 , n14967 );
not ( n14969 , n14965 );
not ( n14970 , n14966 );
and ( n14971 , n14969 , n14970 );
nor ( n14972 , n14968 , n14971 );
buf ( n14973 , n5574 );
nand ( n14974 , n8176 , n14973 );
buf ( n14975 , n5575 );
buf ( n14976 , n14975 );
and ( n14977 , n14974 , n14976 );
not ( n14978 , n14974 );
not ( n14979 , n14975 );
and ( n14980 , n14978 , n14979 );
nor ( n14981 , n14977 , n14980 );
xor ( n14982 , n14972 , n14981 );
buf ( n14983 , n5576 );
nand ( n14984 , n6816 , n14983 );
buf ( n14985 , n5577 );
not ( n14986 , n14985 );
and ( n14987 , n14984 , n14986 );
not ( n14988 , n14984 );
buf ( n14989 , n14985 );
and ( n14990 , n14988 , n14989 );
nor ( n14991 , n14987 , n14990 );
xnor ( n14992 , n14982 , n14991 );
not ( n14993 , n14992 );
not ( n14994 , n14993 );
or ( n14995 , n14954 , n14994 );
not ( n14996 , n14953 );
not ( n14997 , n14993 );
nand ( n14998 , n14996 , n14997 );
nand ( n14999 , n14995 , n14998 );
buf ( n15000 , n5578 );
nand ( n15001 , n7977 , n15000 );
buf ( n15002 , n5579 );
buf ( n15003 , n15002 );
and ( n15004 , n15001 , n15003 );
not ( n15005 , n15001 );
not ( n15006 , n15002 );
and ( n15007 , n15005 , n15006 );
nor ( n15008 , n15004 , n15007 );
not ( n15009 , n15008 );
buf ( n15010 , n5580 );
nand ( n15011 , n7868 , n15010 );
buf ( n15012 , n5581 );
not ( n15013 , n15012 );
and ( n15014 , n15011 , n15013 );
not ( n15015 , n15011 );
buf ( n15016 , n15012 );
and ( n15017 , n15015 , n15016 );
nor ( n15018 , n15014 , n15017 );
not ( n15019 , n15018 );
or ( n15020 , n15009 , n15019 );
or ( n15021 , n15008 , n15018 );
nand ( n15022 , n15020 , n15021 );
buf ( n15023 , n5582 );
buf ( n15024 , n15023 );
not ( n15025 , n15024 );
buf ( n15026 , n5583 );
not ( n15027 , n15026 );
not ( n15028 , n15027 );
or ( n15029 , n15025 , n15028 );
not ( n15030 , n15023 );
buf ( n15031 , n15026 );
nand ( n15032 , n15030 , n15031 );
nand ( n15033 , n15029 , n15032 );
buf ( n15034 , n5584 );
not ( n15035 , n15034 );
and ( n15036 , n15033 , n15035 );
not ( n15037 , n15033 );
buf ( n15038 , n15034 );
and ( n15039 , n15037 , n15038 );
nor ( n15040 , n15036 , n15039 );
and ( n15041 , n15022 , n15040 );
not ( n15042 , n15022 );
not ( n15043 , n15040 );
and ( n15044 , n15042 , n15043 );
nor ( n15045 , n15041 , n15044 );
buf ( n15046 , n15045 );
buf ( n15047 , n15046 );
and ( n15048 , n14999 , n15047 );
not ( n15049 , n14999 );
not ( n15050 , n15008 );
xor ( n15051 , n15040 , n15050 );
xnor ( n15052 , n15051 , n15018 );
buf ( n15053 , n15052 );
not ( n15054 , n15053 );
not ( n15055 , n15054 );
and ( n15056 , n15049 , n15055 );
nor ( n15057 , n15048 , n15056 );
not ( n15058 , n15057 );
nand ( n15059 , n14952 , n15058 );
not ( n15060 , n12304 );
buf ( n15061 , n5585 );
buf ( n15062 , n15061 );
not ( n15063 , n15062 );
buf ( n15064 , n5586 );
not ( n15065 , n15064 );
not ( n15066 , n15065 );
or ( n15067 , n15063 , n15066 );
not ( n15068 , n15061 );
buf ( n15069 , n15064 );
nand ( n15070 , n15068 , n15069 );
nand ( n15071 , n15067 , n15070 );
buf ( n15072 , n5587 );
buf ( n15073 , n15072 );
and ( n15074 , n15071 , n15073 );
not ( n15075 , n15071 );
not ( n15076 , n15072 );
and ( n15077 , n15075 , n15076 );
nor ( n15078 , n15074 , n15077 );
buf ( n15079 , n5588 );
nand ( n15080 , n7014 , n15079 );
buf ( n15081 , n5589 );
buf ( n15082 , n15081 );
and ( n15083 , n15080 , n15082 );
not ( n15084 , n15080 );
not ( n15085 , n15081 );
and ( n15086 , n15084 , n15085 );
nor ( n15087 , n15083 , n15086 );
xor ( n15088 , n15078 , n15087 );
buf ( n15089 , n5590 );
nand ( n15090 , n10874 , n15089 );
buf ( n15091 , n5591 );
buf ( n15092 , n15091 );
and ( n15093 , n15090 , n15092 );
not ( n15094 , n15090 );
not ( n15095 , n15091 );
and ( n15096 , n15094 , n15095 );
nor ( n15097 , n15093 , n15096 );
xnor ( n15098 , n15088 , n15097 );
buf ( n15099 , n15098 );
buf ( n15100 , n15099 );
not ( n15101 , n15100 );
or ( n15102 , n15060 , n15101 );
or ( n15103 , n15100 , n12304 );
nand ( n15104 , n15102 , n15103 );
not ( n15105 , n10535 );
not ( n15106 , n15105 );
and ( n15107 , n15104 , n15106 );
not ( n15108 , n15104 );
and ( n15109 , n15108 , n15105 );
nor ( n15110 , n15107 , n15109 );
buf ( n15111 , n15110 );
xor ( n15112 , n15059 , n15111 );
not ( n15113 , n15112 );
buf ( n15114 , n5592 );
not ( n15115 , n15114 );
not ( n15116 , n15115 );
buf ( n15117 , n5593 );
buf ( n15118 , n5594 );
not ( n15119 , n15118 );
buf ( n15120 , n5595 );
buf ( n15121 , n15120 );
and ( n15122 , n15119 , n15121 );
not ( n15123 , n15119 );
not ( n15124 , n15120 );
and ( n15125 , n15123 , n15124 );
nor ( n15126 , n15122 , n15125 );
xor ( n15127 , n15117 , n15126 );
buf ( n15128 , n5596 );
nand ( n15129 , n6770 , n15128 );
not ( n15130 , n15129 );
buf ( n15131 , n5597 );
not ( n15132 , n15131 );
and ( n15133 , n15130 , n15132 );
nand ( n15134 , n6515 , n15128 );
and ( n15135 , n15134 , n15131 );
nor ( n15136 , n15133 , n15135 );
not ( n15137 , n15136 );
buf ( n15138 , n5598 );
not ( n15139 , n15138 );
and ( n15140 , n15137 , n15139 );
and ( n15141 , n15136 , n15138 );
nor ( n15142 , n15140 , n15141 );
xnor ( n15143 , n15127 , n15142 );
buf ( n15144 , n15143 );
not ( n15145 , n15144 );
not ( n15146 , n15145 );
or ( n15147 , n15116 , n15146 );
not ( n15148 , n15144 );
or ( n15149 , n15148 , n15115 );
nand ( n15150 , n15147 , n15149 );
buf ( n15151 , n5599 );
not ( n15152 , n15151 );
not ( n15153 , n15152 );
buf ( n15154 , n5600 );
not ( n15155 , n15154 );
and ( n15156 , n15153 , n15155 );
and ( n15157 , n15154 , n15152 );
nor ( n15158 , n15156 , n15157 );
not ( n15159 , n15158 );
not ( n15160 , n15159 );
buf ( n15161 , n5601 );
not ( n15162 , n15161 );
buf ( n15163 , n5602 );
nand ( n15164 , n6502 , n15163 );
buf ( n15165 , n5603 );
buf ( n15166 , n15165 );
and ( n15167 , n15164 , n15166 );
not ( n15168 , n15164 );
not ( n15169 , n15165 );
and ( n15170 , n15168 , n15169 );
nor ( n15171 , n15167 , n15170 );
xor ( n15172 , n15162 , n15171 );
buf ( n15173 , n5604 );
nand ( n15174 , n8966 , n15173 );
buf ( n15175 , n5605 );
buf ( n15176 , n15175 );
and ( n15177 , n15174 , n15176 );
not ( n15178 , n15174 );
not ( n15179 , n15175 );
and ( n15180 , n15178 , n15179 );
nor ( n15181 , n15177 , n15180 );
xnor ( n15182 , n15172 , n15181 );
not ( n15183 , n15182 );
not ( n15184 , n15183 );
or ( n15185 , n15160 , n15184 );
nand ( n15186 , n15182 , n15158 );
nand ( n15187 , n15185 , n15186 );
and ( n15188 , n15150 , n15187 );
not ( n15189 , n15150 );
not ( n15190 , n15187 );
and ( n15191 , n15189 , n15190 );
nor ( n15192 , n15188 , n15191 );
not ( n15193 , n15192 );
buf ( n15194 , n14616 );
not ( n15195 , n15194 );
not ( n15196 , n15195 );
not ( n15197 , n13257 );
buf ( n15198 , n5606 );
not ( n15199 , n15198 );
not ( n15200 , n15199 );
or ( n15201 , n15197 , n15200 );
not ( n15202 , n13256 );
buf ( n15203 , n15198 );
nand ( n15204 , n15202 , n15203 );
nand ( n15205 , n15201 , n15204 );
buf ( n15206 , n5607 );
buf ( n15207 , n15206 );
and ( n15208 , n15205 , n15207 );
not ( n15209 , n15205 );
not ( n15210 , n15206 );
and ( n15211 , n15209 , n15210 );
nor ( n15212 , n15208 , n15211 );
buf ( n15213 , n5608 );
nand ( n15214 , n6770 , n15213 );
buf ( n15215 , n5609 );
buf ( n15216 , n15215 );
and ( n15217 , n15214 , n15216 );
not ( n15218 , n15214 );
not ( n15219 , n15215 );
and ( n15220 , n15218 , n15219 );
nor ( n15221 , n15217 , n15220 );
xor ( n15222 , n15212 , n15221 );
buf ( n15223 , n5610 );
nand ( n15224 , n6634 , n15223 );
buf ( n15225 , n5611 );
not ( n15226 , n15225 );
and ( n15227 , n15224 , n15226 );
not ( n15228 , n15224 );
buf ( n15229 , n15225 );
and ( n15230 , n15228 , n15229 );
nor ( n15231 , n15227 , n15230 );
xnor ( n15232 , n15222 , n15231 );
not ( n15233 , n15232 );
buf ( n15234 , n15233 );
not ( n15235 , n15234 );
or ( n15236 , n15196 , n15235 );
buf ( n15237 , n15232 );
nand ( n15238 , n15237 , n15194 );
nand ( n15239 , n15236 , n15238 );
not ( n15240 , n10749 );
not ( n15241 , n15240 );
buf ( n15242 , n15241 );
and ( n15243 , n15239 , n15242 );
not ( n15244 , n15239 );
buf ( n15245 , n10744 );
and ( n15246 , n15244 , n15245 );
nor ( n15247 , n15243 , n15246 );
nand ( n15248 , n15193 , n15247 );
not ( n15249 , n15248 );
buf ( n15250 , n5612 );
buf ( n15251 , n15250 );
not ( n15252 , n15251 );
buf ( n15253 , n5613 );
buf ( n15254 , n15253 );
not ( n15255 , n15254 );
buf ( n15256 , n5614 );
not ( n15257 , n15256 );
not ( n15258 , n15257 );
or ( n15259 , n15255 , n15258 );
not ( n15260 , n15253 );
buf ( n15261 , n15256 );
nand ( n15262 , n15260 , n15261 );
nand ( n15263 , n15259 , n15262 );
buf ( n15264 , n5615 );
buf ( n15265 , n15264 );
and ( n15266 , n15263 , n15265 );
not ( n15267 , n15263 );
not ( n15268 , n15264 );
and ( n15269 , n15267 , n15268 );
nor ( n15270 , n15266 , n15269 );
buf ( n15271 , n5616 );
nand ( n15272 , n6557 , n15271 );
buf ( n15273 , n5617 );
not ( n15274 , n15273 );
and ( n15275 , n15272 , n15274 );
not ( n15276 , n15272 );
buf ( n15277 , n15273 );
and ( n15278 , n15276 , n15277 );
nor ( n15279 , n15275 , n15278 );
xor ( n15280 , n15270 , n15279 );
buf ( n15281 , n5618 );
nand ( n15282 , n8223 , n15281 );
buf ( n15283 , n5619 );
not ( n15284 , n15283 );
and ( n15285 , n15282 , n15284 );
not ( n15286 , n15282 );
buf ( n15287 , n15283 );
and ( n15288 , n15286 , n15287 );
nor ( n15289 , n15285 , n15288 );
xnor ( n15290 , n15280 , n15289 );
buf ( n15291 , n15290 );
not ( n15292 , n15291 );
or ( n15293 , n15252 , n15292 );
or ( n15294 , n15291 , n15251 );
nand ( n15295 , n15293 , n15294 );
not ( n15296 , n15295 );
not ( n15297 , n14224 );
not ( n15298 , n15297 );
not ( n15299 , n15298 );
and ( n15300 , n15296 , n15299 );
and ( n15301 , n15295 , n14221 );
nor ( n15302 , n15300 , n15301 );
not ( n15303 , n15302 );
not ( n15304 , n15303 );
and ( n15305 , n15249 , n15304 );
and ( n15306 , n15248 , n15303 );
nor ( n15307 , n15305 , n15306 );
not ( n15308 , n15307 );
or ( n15309 , n15113 , n15308 );
not ( n15310 , n15112 );
not ( n15311 , n15307 );
nand ( n15312 , n15310 , n15311 );
nand ( n15313 , n15309 , n15312 );
and ( n15314 , n14863 , n15313 );
not ( n15315 , n14863 );
not ( n15316 , n15313 );
and ( n15317 , n15315 , n15316 );
nor ( n15318 , n15314 , n15317 );
buf ( n15319 , n15318 );
not ( n15320 , n15319 );
and ( n15321 , n14338 , n15320 );
and ( n15322 , n14337 , n15319 );
nor ( n15323 , n15321 , n15322 );
buf ( n15324 , n13344 );
buf ( n15325 , n15324 );
buf ( n15326 , n15325 );
not ( n15327 , n15326 );
nand ( n15328 , n15323 , n15327 );
buf ( n15329 , n5620 );
buf ( n15330 , n15329 );
not ( n15331 , n15330 );
buf ( n15332 , n5621 );
not ( n15333 , n15332 );
not ( n15334 , n15333 );
or ( n15335 , n15331 , n15334 );
not ( n15336 , n15329 );
buf ( n15337 , n15332 );
nand ( n15338 , n15336 , n15337 );
nand ( n15339 , n15335 , n15338 );
buf ( n15340 , n15339 );
not ( n15341 , n15340 );
buf ( n15342 , n5622 );
buf ( n15343 , n5623 );
not ( n15344 , n15343 );
xor ( n15345 , n15342 , n15344 );
buf ( n15346 , n5624 );
nand ( n15347 , n7247 , n15346 );
buf ( n15348 , n5625 );
not ( n15349 , n15348 );
and ( n15350 , n15347 , n15349 );
not ( n15351 , n15347 );
buf ( n15352 , n15348 );
and ( n15353 , n15351 , n15352 );
nor ( n15354 , n15350 , n15353 );
xnor ( n15355 , n15345 , n15354 );
not ( n15356 , n15355 );
not ( n15357 , n15356 );
or ( n15358 , n15341 , n15357 );
not ( n15359 , n15340 );
nand ( n15360 , n15359 , n15355 );
nand ( n15361 , n15358 , n15360 );
not ( n15362 , n15361 );
not ( n15363 , n11500 );
buf ( n15364 , n5626 );
nand ( n15365 , n6557 , n15364 );
buf ( n15366 , n5627 );
buf ( n15367 , n15366 );
and ( n15368 , n15365 , n15367 );
not ( n15369 , n15365 );
not ( n15370 , n15366 );
and ( n15371 , n15369 , n15370 );
nor ( n15372 , n15368 , n15371 );
buf ( n15373 , n15372 );
not ( n15374 , n15373 );
and ( n15375 , n15363 , n15374 );
not ( n15376 , n11501 );
and ( n15377 , n15376 , n15373 );
nor ( n15378 , n15375 , n15377 );
not ( n15379 , n15378 );
and ( n15380 , n15362 , n15379 );
buf ( n15381 , n15361 );
and ( n15382 , n15381 , n15378 );
nor ( n15383 , n15380 , n15382 );
not ( n15384 , n15383 );
not ( n15385 , n10087 );
buf ( n15386 , n5628 );
buf ( n15387 , n15386 );
not ( n15388 , n15387 );
buf ( n15389 , n5629 );
not ( n15390 , n15389 );
not ( n15391 , n15390 );
or ( n15392 , n15388 , n15391 );
not ( n15393 , n15386 );
buf ( n15394 , n15389 );
nand ( n15395 , n15393 , n15394 );
nand ( n15396 , n15392 , n15395 );
buf ( n15397 , n5630 );
not ( n15398 , n15397 );
and ( n15399 , n15396 , n15398 );
not ( n15400 , n15396 );
buf ( n15401 , n15397 );
and ( n15402 , n15400 , n15401 );
nor ( n15403 , n15399 , n15402 );
buf ( n15404 , n5631 );
nand ( n15405 , n6502 , n15404 );
buf ( n15406 , n5632 );
buf ( n15407 , n15406 );
and ( n15408 , n15405 , n15407 );
not ( n15409 , n15405 );
not ( n15410 , n15406 );
and ( n15411 , n15409 , n15410 );
nor ( n15412 , n15408 , n15411 );
xor ( n15413 , n15403 , n15412 );
buf ( n15414 , n5633 );
nand ( n15415 , n6647 , n15414 );
buf ( n15416 , n5634 );
not ( n15417 , n15416 );
and ( n15418 , n15415 , n15417 );
not ( n15419 , n15415 );
buf ( n15420 , n15416 );
and ( n15421 , n15419 , n15420 );
nor ( n15422 , n15418 , n15421 );
xor ( n15423 , n15413 , n15422 );
not ( n15424 , n15423 );
not ( n15425 , n15424 );
or ( n15426 , n15385 , n15425 );
not ( n15427 , n10087 );
not ( n15428 , n15423 );
not ( n15429 , n15428 );
nand ( n15430 , n15427 , n15429 );
nand ( n15431 , n15426 , n15430 );
buf ( n15432 , n5635 );
buf ( n15433 , n15432 );
not ( n15434 , n15433 );
buf ( n15435 , n5636 );
not ( n15436 , n15435 );
not ( n15437 , n15436 );
or ( n15438 , n15434 , n15437 );
not ( n15439 , n15432 );
buf ( n15440 , n15435 );
nand ( n15441 , n15439 , n15440 );
nand ( n15442 , n15438 , n15441 );
buf ( n15443 , n5637 );
buf ( n15444 , n15443 );
and ( n15445 , n15442 , n15444 );
not ( n15446 , n15442 );
not ( n15447 , n15443 );
and ( n15448 , n15446 , n15447 );
nor ( n15449 , n15445 , n15448 );
buf ( n15450 , n5638 );
nand ( n15451 , n9812 , n15450 );
buf ( n15452 , n5639 );
buf ( n15453 , n15452 );
and ( n15454 , n15451 , n15453 );
not ( n15455 , n15451 );
not ( n15456 , n15452 );
and ( n15457 , n15455 , n15456 );
nor ( n15458 , n15454 , n15457 );
xor ( n15459 , n15449 , n15458 );
buf ( n15460 , n5640 );
nand ( n15461 , n10947 , n15460 );
buf ( n15462 , n5641 );
not ( n15463 , n15462 );
and ( n15464 , n15461 , n15463 );
not ( n15465 , n15461 );
buf ( n15466 , n15462 );
and ( n15467 , n15465 , n15466 );
nor ( n15468 , n15464 , n15467 );
xor ( n15469 , n15459 , n15468 );
buf ( n15470 , n15469 );
not ( n15471 , n15470 );
and ( n15472 , n15431 , n15471 );
not ( n15473 , n15431 );
not ( n15474 , n15469 );
not ( n15475 , n15474 );
and ( n15476 , n15473 , n15475 );
nor ( n15477 , n15472 , n15476 );
not ( n15478 , n15477 );
nand ( n15479 , n15384 , n15478 );
buf ( n15480 , n5642 );
buf ( n15481 , n15480 );
not ( n15482 , n15481 );
buf ( n15483 , n5643 );
not ( n15484 , n15483 );
not ( n15485 , n15484 );
or ( n15486 , n15482 , n15485 );
not ( n15487 , n15480 );
buf ( n15488 , n15483 );
nand ( n15489 , n15487 , n15488 );
nand ( n15490 , n15486 , n15489 );
buf ( n15491 , n5644 );
not ( n15492 , n15491 );
and ( n15493 , n15490 , n15492 );
not ( n15494 , n15490 );
buf ( n15495 , n15491 );
and ( n15496 , n15494 , n15495 );
nor ( n15497 , n15493 , n15496 );
buf ( n15498 , n5645 );
nand ( n15499 , n8124 , n15498 );
buf ( n15500 , n5646 );
buf ( n15501 , n15500 );
and ( n15502 , n15499 , n15501 );
not ( n15503 , n15499 );
not ( n15504 , n15500 );
and ( n15505 , n15503 , n15504 );
nor ( n15506 , n15502 , n15505 );
xor ( n15507 , n15497 , n15506 );
buf ( n15508 , n5647 );
nand ( n15509 , n6816 , n15508 );
buf ( n15510 , n5648 );
buf ( n15511 , n15510 );
and ( n15512 , n15509 , n15511 );
not ( n15513 , n15509 );
not ( n15514 , n15510 );
and ( n15515 , n15513 , n15514 );
nor ( n15516 , n15512 , n15515 );
xnor ( n15517 , n15507 , n15516 );
not ( n15518 , n15517 );
nor ( n15519 , n15518 , n14125 );
not ( n15520 , n15519 );
buf ( n15521 , n15517 );
not ( n15522 , n15521 );
nand ( n15523 , n15522 , n14125 );
nand ( n15524 , n15520 , n15523 );
buf ( n15525 , n5649 );
buf ( n15526 , n15525 );
not ( n15527 , n15526 );
buf ( n15528 , n5650 );
not ( n15529 , n15528 );
not ( n15530 , n15529 );
or ( n15531 , n15527 , n15530 );
not ( n15532 , n15525 );
buf ( n15533 , n15528 );
nand ( n15534 , n15532 , n15533 );
nand ( n15535 , n15531 , n15534 );
not ( n15536 , n9096 );
and ( n15537 , n15535 , n15536 );
not ( n15538 , n15535 );
and ( n15539 , n15538 , n9097 );
nor ( n15540 , n15537 , n15539 );
buf ( n15541 , n5651 );
nand ( n15542 , n7698 , n15541 );
buf ( n15543 , n5652 );
not ( n15544 , n15543 );
and ( n15545 , n15542 , n15544 );
not ( n15546 , n15542 );
buf ( n15547 , n15543 );
and ( n15548 , n15546 , n15547 );
nor ( n15549 , n15545 , n15548 );
not ( n15550 , n15549 );
xor ( n15551 , n15540 , n15550 );
buf ( n15552 , n5653 );
nand ( n15553 , n6557 , n15552 );
buf ( n15554 , n5654 );
buf ( n15555 , n15554 );
and ( n15556 , n15553 , n15555 );
not ( n15557 , n15553 );
not ( n15558 , n15554 );
and ( n15559 , n15557 , n15558 );
nor ( n15560 , n15556 , n15559 );
buf ( n15561 , n15560 );
xnor ( n15562 , n15551 , n15561 );
buf ( n15563 , n15562 );
and ( n15564 , n15524 , n15563 );
not ( n15565 , n15524 );
not ( n15566 , n15560 );
not ( n15567 , n15549 );
or ( n15568 , n15566 , n15567 );
or ( n15569 , n15560 , n15549 );
nand ( n15570 , n15568 , n15569 );
and ( n15571 , n15570 , n15540 );
not ( n15572 , n15570 );
not ( n15573 , n15540 );
and ( n15574 , n15572 , n15573 );
nor ( n15575 , n15571 , n15574 );
buf ( n15576 , n15575 );
and ( n15577 , n15565 , n15576 );
nor ( n15578 , n15564 , n15577 );
not ( n15579 , n15578 );
and ( n15580 , n15479 , n15579 );
not ( n15581 , n15479 );
and ( n15582 , n15581 , n15578 );
nor ( n15583 , n15580 , n15582 );
not ( n15584 , n15583 );
buf ( n15585 , n5655 );
buf ( n15586 , n15585 );
not ( n15587 , n15586 );
not ( n15588 , n13203 );
not ( n15589 , n15588 );
or ( n15590 , n15587 , n15589 );
not ( n15591 , n15585 );
nand ( n15592 , n15591 , n13204 );
nand ( n15593 , n15590 , n15592 );
xor ( n15594 , n8344 , n15593 );
buf ( n15595 , n5656 );
buf ( n15596 , n5657 );
not ( n15597 , n15596 );
xor ( n15598 , n15595 , n15597 );
buf ( n15599 , n5658 );
nand ( n15600 , n8675 , n15599 );
xnor ( n15601 , n15598 , n15600 );
xnor ( n15602 , n15594 , n15601 );
not ( n15603 , n15602 );
not ( n15604 , n15603 );
buf ( n15605 , n5659 );
buf ( n15606 , n15605 );
not ( n15607 , n15606 );
buf ( n15608 , n5660 );
not ( n15609 , n15608 );
not ( n15610 , n15609 );
or ( n15611 , n15607 , n15610 );
not ( n15612 , n15605 );
buf ( n15613 , n15608 );
nand ( n15614 , n15612 , n15613 );
nand ( n15615 , n15611 , n15614 );
buf ( n15616 , n5661 );
buf ( n15617 , n15616 );
and ( n15618 , n15615 , n15617 );
not ( n15619 , n15615 );
not ( n15620 , n15616 );
and ( n15621 , n15619 , n15620 );
nor ( n15622 , n15618 , n15621 );
xor ( n15623 , n15622 , n14713 );
buf ( n15624 , n5662 );
nand ( n15625 , n14573 , n15624 );
buf ( n15626 , n5663 );
not ( n15627 , n15626 );
and ( n15628 , n15625 , n15627 );
not ( n15629 , n15625 );
buf ( n15630 , n15626 );
and ( n15631 , n15629 , n15630 );
nor ( n15632 , n15628 , n15631 );
xnor ( n15633 , n15623 , n15632 );
not ( n15634 , n15633 );
not ( n15635 , n15634 );
buf ( n15636 , n6524 );
not ( n15637 , n15636 );
and ( n15638 , n15635 , n15637 );
not ( n15639 , n15633 );
and ( n15640 , n15639 , n15636 );
nor ( n15641 , n15638 , n15640 );
xor ( n15642 , n15604 , n15641 );
not ( n15643 , n15642 );
buf ( n15644 , n5664 );
buf ( n15645 , n15644 );
not ( n15646 , n15645 );
buf ( n15647 , n5665 );
buf ( n15648 , n15647 );
not ( n15649 , n15648 );
buf ( n15650 , n5666 );
not ( n15651 , n15650 );
not ( n15652 , n15651 );
or ( n15653 , n15649 , n15652 );
not ( n15654 , n15647 );
buf ( n15655 , n15650 );
nand ( n15656 , n15654 , n15655 );
nand ( n15657 , n15653 , n15656 );
buf ( n15658 , n5667 );
not ( n15659 , n15658 );
and ( n15660 , n15657 , n15659 );
not ( n15661 , n15657 );
buf ( n15662 , n15658 );
and ( n15663 , n15661 , n15662 );
nor ( n15664 , n15660 , n15663 );
buf ( n15665 , n5668 );
nand ( n15666 , n10165 , n15665 );
buf ( n15667 , n5669 );
buf ( n15668 , n15667 );
and ( n15669 , n15666 , n15668 );
not ( n15670 , n15666 );
not ( n15671 , n15667 );
and ( n15672 , n15670 , n15671 );
nor ( n15673 , n15669 , n15672 );
xor ( n15674 , n15664 , n15673 );
buf ( n15675 , n5670 );
nand ( n15676 , n8323 , n15675 );
buf ( n15677 , n5671 );
buf ( n15678 , n15677 );
and ( n15679 , n15676 , n15678 );
not ( n15680 , n15676 );
not ( n15681 , n15677 );
and ( n15682 , n15680 , n15681 );
nor ( n15683 , n15679 , n15682 );
not ( n15684 , n15683 );
xnor ( n15685 , n15674 , n15684 );
not ( n15686 , n15685 );
or ( n15687 , n15646 , n15686 );
not ( n15688 , n15645 );
not ( n15689 , n15685 );
nand ( n15690 , n15688 , n15689 );
nand ( n15691 , n15687 , n15690 );
not ( n15692 , n12498 );
and ( n15693 , n15691 , n15692 );
not ( n15694 , n15691 );
and ( n15695 , n15694 , n12498 );
nor ( n15696 , n15693 , n15695 );
not ( n15697 , n15696 );
nand ( n15698 , n15643 , n15697 );
not ( n15699 , n15698 );
not ( n15700 , n15062 );
buf ( n15701 , n14506 );
not ( n15702 , n15701 );
or ( n15703 , n15700 , n15702 );
not ( n15704 , n14507 );
or ( n15705 , n15704 , n15062 );
nand ( n15706 , n15703 , n15705 );
buf ( n15707 , n5672 );
buf ( n15708 , n15707 );
not ( n15709 , n15708 );
buf ( n15710 , n5673 );
not ( n15711 , n15710 );
not ( n15712 , n15711 );
or ( n15713 , n15709 , n15712 );
not ( n15714 , n15707 );
buf ( n15715 , n15710 );
nand ( n15716 , n15714 , n15715 );
nand ( n15717 , n15713 , n15716 );
buf ( n15718 , n5674 );
not ( n15719 , n15718 );
and ( n15720 , n15717 , n15719 );
not ( n15721 , n15717 );
buf ( n15722 , n15718 );
and ( n15723 , n15721 , n15722 );
nor ( n15724 , n15720 , n15723 );
buf ( n15725 , n5675 );
nand ( n15726 , n6604 , n15725 );
buf ( n15727 , n5676 );
not ( n15728 , n15727 );
and ( n15729 , n15726 , n15728 );
not ( n15730 , n15726 );
buf ( n15731 , n15727 );
and ( n15732 , n15730 , n15731 );
nor ( n15733 , n15729 , n15732 );
xor ( n15734 , n15724 , n15733 );
buf ( n15735 , n5677 );
nand ( n15736 , n7258 , n15735 );
buf ( n15737 , n5678 );
buf ( n15738 , n15737 );
and ( n15739 , n15736 , n15738 );
not ( n15740 , n15736 );
not ( n15741 , n15737 );
and ( n15742 , n15740 , n15741 );
nor ( n15743 , n15739 , n15742 );
xor ( n15744 , n15734 , n15743 );
not ( n15745 , n15744 );
and ( n15746 , n15706 , n15745 );
not ( n15747 , n15706 );
not ( n15748 , n15744 );
not ( n15749 , n15748 );
not ( n15750 , n15749 );
not ( n15751 , n15750 );
and ( n15752 , n15747 , n15751 );
nor ( n15753 , n15746 , n15752 );
not ( n15754 , n15753 );
not ( n15755 , n15754 );
and ( n15756 , n15699 , n15755 );
and ( n15757 , n15698 , n15754 );
nor ( n15758 , n15756 , n15757 );
not ( n15759 , n15758 );
buf ( n15760 , n12712 );
not ( n15761 , n15760 );
buf ( n15762 , n5679 );
not ( n15763 , n15762 );
buf ( n15764 , n5680 );
buf ( n15765 , n15764 );
not ( n15766 , n15765 );
buf ( n15767 , n5681 );
not ( n15768 , n15767 );
not ( n15769 , n15768 );
or ( n15770 , n15766 , n15769 );
not ( n15771 , n15764 );
buf ( n15772 , n15767 );
nand ( n15773 , n15771 , n15772 );
nand ( n15774 , n15770 , n15773 );
xor ( n15775 , n15763 , n15774 );
buf ( n15776 , n5682 );
nand ( n15777 , n7606 , n15776 );
buf ( n15778 , n5683 );
buf ( n15779 , n15778 );
and ( n15780 , n15777 , n15779 );
not ( n15781 , n15777 );
not ( n15782 , n15778 );
and ( n15783 , n15781 , n15782 );
nor ( n15784 , n15780 , n15783 );
not ( n15785 , n15784 );
buf ( n15786 , n5684 );
not ( n15787 , n15786 );
and ( n15788 , n15785 , n15787 );
and ( n15789 , n15784 , n15786 );
nor ( n15790 , n15788 , n15789 );
xnor ( n15791 , n15775 , n15790 );
not ( n15792 , n15791 );
or ( n15793 , n15761 , n15792 );
or ( n15794 , n15791 , n15760 );
nand ( n15795 , n15793 , n15794 );
buf ( n15796 , n5685 );
buf ( n15797 , n15796 );
not ( n15798 , n15797 );
buf ( n15799 , n5686 );
not ( n15800 , n15799 );
not ( n15801 , n15800 );
or ( n15802 , n15798 , n15801 );
not ( n15803 , n15796 );
buf ( n15804 , n15799 );
nand ( n15805 , n15803 , n15804 );
nand ( n15806 , n15802 , n15805 );
buf ( n15807 , n5687 );
buf ( n15808 , n15807 );
and ( n15809 , n15806 , n15808 );
not ( n15810 , n15806 );
not ( n15811 , n15807 );
and ( n15812 , n15810 , n15811 );
nor ( n15813 , n15809 , n15812 );
buf ( n15814 , n5688 );
nand ( n15815 , n6927 , n15814 );
buf ( n15816 , n5689 );
buf ( n15817 , n15816 );
and ( n15818 , n15815 , n15817 );
not ( n15819 , n15815 );
not ( n15820 , n15816 );
and ( n15821 , n15819 , n15820 );
nor ( n15822 , n15818 , n15821 );
xor ( n15823 , n15813 , n15822 );
buf ( n15824 , n5690 );
nand ( n15825 , n14573 , n15824 );
buf ( n15826 , n5691 );
not ( n15827 , n15826 );
and ( n15828 , n15825 , n15827 );
not ( n15829 , n15825 );
buf ( n15830 , n15826 );
and ( n15831 , n15829 , n15830 );
nor ( n15832 , n15828 , n15831 );
xor ( n15833 , n15823 , n15832 );
not ( n15834 , n15833 );
not ( n15835 , n15834 );
and ( n15836 , n15795 , n15835 );
not ( n15837 , n15795 );
xor ( n15838 , n15813 , n15822 );
xnor ( n15839 , n15838 , n15832 );
buf ( n15840 , n15839 );
and ( n15841 , n15837 , n15840 );
nor ( n15842 , n15836 , n15841 );
not ( n15843 , n15842 );
not ( n15844 , n8547 );
not ( n15845 , n6589 );
and ( n15846 , n15844 , n15845 );
and ( n15847 , n8547 , n6589 );
nor ( n15848 , n15846 , n15847 );
not ( n15849 , n10443 );
and ( n15850 , n15848 , n15849 );
not ( n15851 , n15848 );
and ( n15852 , n15851 , n10443 );
nor ( n15853 , n15850 , n15852 );
not ( n15854 , n15853 );
nand ( n15855 , n15843 , n15854 );
buf ( n15856 , n5692 );
not ( n15857 , n7499 );
buf ( n15858 , n5693 );
not ( n15859 , n15858 );
not ( n15860 , n15859 );
or ( n15861 , n15857 , n15860 );
not ( n15862 , n7498 );
buf ( n15863 , n15858 );
nand ( n15864 , n15862 , n15863 );
nand ( n15865 , n15861 , n15864 );
xor ( n15866 , n15856 , n15865 );
buf ( n15867 , n5694 );
buf ( n15868 , n5695 );
buf ( n15869 , n15868 );
xor ( n15870 , n15867 , n15869 );
buf ( n15871 , n5696 );
nand ( n15872 , n6973 , n15871 );
xnor ( n15873 , n15870 , n15872 );
xnor ( n15874 , n15866 , n15873 );
not ( n15875 , n15874 );
buf ( n15876 , n5697 );
buf ( n15877 , n15876 );
not ( n15878 , n15877 );
not ( n15879 , n10025 );
buf ( n15880 , n5698 );
not ( n15881 , n15880 );
not ( n15882 , n15881 );
or ( n15883 , n15879 , n15882 );
not ( n15884 , n10024 );
buf ( n15885 , n15880 );
nand ( n15886 , n15884 , n15885 );
nand ( n15887 , n15883 , n15886 );
buf ( n15888 , n5699 );
buf ( n15889 , n15888 );
and ( n15890 , n15887 , n15889 );
not ( n15891 , n15887 );
not ( n15892 , n15888 );
and ( n15893 , n15891 , n15892 );
nor ( n15894 , n15890 , n15893 );
xor ( n15895 , n15894 , n8933 );
buf ( n15896 , n5700 );
nand ( n15897 , n6515 , n15896 );
buf ( n15898 , n5701 );
not ( n15899 , n15898 );
and ( n15900 , n15897 , n15899 );
not ( n15901 , n15897 );
buf ( n15902 , n15898 );
and ( n15903 , n15901 , n15902 );
nor ( n15904 , n15900 , n15903 );
xnor ( n15905 , n15895 , n15904 );
not ( n15906 , n15905 );
not ( n15907 , n15906 );
or ( n15908 , n15878 , n15907 );
or ( n15909 , n15906 , n15877 );
nand ( n15910 , n15908 , n15909 );
and ( n15911 , n15875 , n15910 );
not ( n15912 , n15875 );
not ( n15913 , n15910 );
and ( n15914 , n15912 , n15913 );
nor ( n15915 , n15911 , n15914 );
not ( n15916 , n15915 );
and ( n15917 , n15855 , n15916 );
not ( n15918 , n15855 );
and ( n15919 , n15918 , n15915 );
nor ( n15920 , n15917 , n15919 );
not ( n15921 , n15920 );
or ( n15922 , n15759 , n15921 );
or ( n15923 , n15920 , n15758 );
nand ( n15924 , n15922 , n15923 );
nand ( n15925 , n15579 , n15477 );
not ( n15926 , n15925 );
buf ( n15927 , n5702 );
buf ( n15928 , n15927 );
buf ( n15929 , n5703 );
nand ( n15930 , n6557 , n15929 );
buf ( n15931 , n5704 );
buf ( n15932 , n15931 );
and ( n15933 , n15930 , n15932 );
not ( n15934 , n15930 );
not ( n15935 , n15931 );
and ( n15936 , n15934 , n15935 );
nor ( n15937 , n15933 , n15936 );
not ( n15938 , n15937 );
buf ( n15939 , n5705 );
nand ( n15940 , n7197 , n15939 );
buf ( n15941 , n5706 );
not ( n15942 , n15941 );
and ( n15943 , n15940 , n15942 );
not ( n15944 , n15940 );
buf ( n15945 , n15941 );
and ( n15946 , n15944 , n15945 );
nor ( n15947 , n15943 , n15946 );
not ( n15948 , n15947 );
or ( n15949 , n15938 , n15948 );
or ( n15950 , n15937 , n15947 );
nand ( n15951 , n15949 , n15950 );
buf ( n15952 , n5707 );
buf ( n15953 , n15952 );
not ( n15954 , n15953 );
buf ( n15955 , n5708 );
not ( n15956 , n15955 );
not ( n15957 , n15956 );
or ( n15958 , n15954 , n15957 );
not ( n15959 , n15952 );
buf ( n15960 , n15955 );
nand ( n15961 , n15959 , n15960 );
nand ( n15962 , n15958 , n15961 );
buf ( n15963 , n5709 );
not ( n15964 , n15963 );
and ( n15965 , n15962 , n15964 );
not ( n15966 , n15962 );
buf ( n15967 , n15963 );
and ( n15968 , n15966 , n15967 );
nor ( n15969 , n15965 , n15968 );
and ( n15970 , n15951 , n15969 );
not ( n15971 , n15951 );
not ( n15972 , n15969 );
and ( n15973 , n15971 , n15972 );
nor ( n15974 , n15970 , n15973 );
not ( n15975 , n15974 );
not ( n15976 , n15975 );
xor ( n15977 , n15928 , n15976 );
buf ( n15978 , n5710 );
buf ( n15979 , n15978 );
not ( n15980 , n15979 );
buf ( n15981 , n5711 );
not ( n15982 , n15981 );
not ( n15983 , n15982 );
or ( n15984 , n15980 , n15983 );
not ( n15985 , n15978 );
buf ( n15986 , n15981 );
nand ( n15987 , n15985 , n15986 );
nand ( n15988 , n15984 , n15987 );
not ( n15989 , n15988 );
not ( n15990 , n15989 );
buf ( n15991 , n5712 );
buf ( n15992 , n5713 );
not ( n15993 , n15992 );
xor ( n15994 , n15991 , n15993 );
buf ( n15995 , n5714 );
not ( n15996 , n15995 );
buf ( n15997 , n5715 );
nand ( n15998 , n6646 , n15997 );
not ( n15999 , n15998 );
or ( n16000 , n15996 , n15999 );
nand ( n16001 , n6604 , n15997 );
or ( n16002 , n16001 , n15995 );
nand ( n16003 , n16000 , n16002 );
xnor ( n16004 , n15994 , n16003 );
not ( n16005 , n16004 );
or ( n16006 , n15990 , n16005 );
or ( n16007 , n16004 , n15989 );
nand ( n16008 , n16006 , n16007 );
buf ( n16009 , n16008 );
not ( n16010 , n16009 );
xnor ( n16011 , n15977 , n16010 );
not ( n16012 , n16011 );
not ( n16013 , n16012 );
and ( n16014 , n15926 , n16013 );
and ( n16015 , n15925 , n16012 );
nor ( n16016 , n16014 , n16015 );
and ( n16017 , n15924 , n16016 );
not ( n16018 , n15924 );
not ( n16019 , n16016 );
and ( n16020 , n16018 , n16019 );
nor ( n16021 , n16017 , n16020 );
not ( n16022 , n16021 );
not ( n16023 , n16022 );
not ( n16024 , n16023 );
buf ( n16025 , n15822 );
not ( n16026 , n16025 );
not ( n16027 , n16026 );
buf ( n16028 , n5716 );
buf ( n16029 , n16028 );
not ( n16030 , n16029 );
buf ( n16031 , n5717 );
not ( n16032 , n16031 );
not ( n16033 , n16032 );
or ( n16034 , n16030 , n16033 );
not ( n16035 , n16028 );
buf ( n16036 , n16031 );
nand ( n16037 , n16035 , n16036 );
nand ( n16038 , n16034 , n16037 );
buf ( n16039 , n5718 );
not ( n16040 , n16039 );
and ( n16041 , n16038 , n16040 );
not ( n16042 , n16038 );
buf ( n16043 , n16039 );
and ( n16044 , n16042 , n16043 );
nor ( n16045 , n16041 , n16044 );
xor ( n16046 , n16045 , n14111 );
buf ( n16047 , n5719 );
nand ( n16048 , n6647 , n16047 );
buf ( n16049 , n5720 );
buf ( n16050 , n16049 );
and ( n16051 , n16048 , n16050 );
not ( n16052 , n16048 );
not ( n16053 , n16049 );
and ( n16054 , n16052 , n16053 );
nor ( n16055 , n16051 , n16054 );
xnor ( n16056 , n16046 , n16055 );
buf ( n16057 , n16056 );
not ( n16058 , n16057 );
not ( n16059 , n16058 );
or ( n16060 , n16027 , n16059 );
buf ( n16061 , n16057 );
nand ( n16062 , n16061 , n16025 );
nand ( n16063 , n16060 , n16062 );
buf ( n16064 , n5721 );
buf ( n16065 , n5722 );
not ( n16066 , n16065 );
buf ( n16067 , n5723 );
buf ( n16068 , n16067 );
nand ( n16069 , n16066 , n16068 );
not ( n16070 , n16067 );
buf ( n16071 , n16065 );
nand ( n16072 , n16070 , n16071 );
and ( n16073 , n16069 , n16072 );
xor ( n16074 , n16064 , n16073 );
buf ( n16075 , n5724 );
nand ( n16076 , n6633 , n16075 );
buf ( n16077 , n5725 );
buf ( n16078 , n16077 );
and ( n16079 , n16076 , n16078 );
not ( n16080 , n16076 );
not ( n16081 , n16077 );
and ( n16082 , n16080 , n16081 );
nor ( n16083 , n16079 , n16082 );
not ( n16084 , n16083 );
buf ( n16085 , n5726 );
nand ( n16086 , n6815 , n16085 );
buf ( n16087 , n5727 );
not ( n16088 , n16087 );
and ( n16089 , n16086 , n16088 );
not ( n16090 , n16086 );
buf ( n16091 , n16087 );
and ( n16092 , n16090 , n16091 );
nor ( n16093 , n16089 , n16092 );
not ( n16094 , n16093 );
or ( n16095 , n16084 , n16094 );
or ( n16096 , n16083 , n16093 );
nand ( n16097 , n16095 , n16096 );
xnor ( n16098 , n16074 , n16097 );
buf ( n16099 , n16098 );
not ( n16100 , n16099 );
and ( n16101 , n16063 , n16100 );
not ( n16102 , n16063 );
not ( n16103 , n16098 );
not ( n16104 , n16103 );
and ( n16105 , n16102 , n16104 );
nor ( n16106 , n16101 , n16105 );
not ( n16107 , n16106 );
buf ( n16108 , n5728 );
buf ( n16109 , n16108 );
buf ( n16110 , n5729 );
buf ( n16111 , n16110 );
not ( n16112 , n16111 );
buf ( n16113 , n5730 );
not ( n16114 , n16113 );
not ( n16115 , n16114 );
or ( n16116 , n16112 , n16115 );
not ( n16117 , n16110 );
buf ( n16118 , n16113 );
nand ( n16119 , n16117 , n16118 );
nand ( n16120 , n16116 , n16119 );
buf ( n16121 , n5731 );
not ( n16122 , n16121 );
and ( n16123 , n16120 , n16122 );
not ( n16124 , n16120 );
buf ( n16125 , n16121 );
and ( n16126 , n16124 , n16125 );
nor ( n16127 , n16123 , n16126 );
buf ( n16128 , n5732 );
nand ( n16129 , n8537 , n16128 );
buf ( n16130 , n5733 );
buf ( n16131 , n16130 );
and ( n16132 , n16129 , n16131 );
not ( n16133 , n16129 );
not ( n16134 , n16130 );
and ( n16135 , n16133 , n16134 );
nor ( n16136 , n16132 , n16135 );
xor ( n16137 , n16127 , n16136 );
buf ( n16138 , n5734 );
nand ( n16139 , n7014 , n16138 );
buf ( n16140 , n5735 );
not ( n16141 , n16140 );
and ( n16142 , n16139 , n16141 );
not ( n16143 , n16139 );
buf ( n16144 , n16140 );
and ( n16145 , n16143 , n16144 );
nor ( n16146 , n16142 , n16145 );
xnor ( n16147 , n16137 , n16146 );
not ( n16148 , n16147 );
not ( n16149 , n16148 );
xor ( n16150 , n16109 , n16149 );
not ( n16151 , n11775 );
xnor ( n16152 , n16150 , n16151 );
nand ( n16153 , n16107 , n16152 );
not ( n16154 , n16153 );
buf ( n16155 , n8896 );
xor ( n16156 , n16155 , n13690 );
buf ( n16157 , n5736 );
buf ( n16158 , n16157 );
not ( n16159 , n16158 );
buf ( n16160 , n5737 );
not ( n16161 , n16160 );
not ( n16162 , n16161 );
or ( n16163 , n16159 , n16162 );
not ( n16164 , n16157 );
buf ( n16165 , n16160 );
nand ( n16166 , n16164 , n16165 );
nand ( n16167 , n16163 , n16166 );
not ( n16168 , n16167 );
buf ( n16169 , n5738 );
buf ( n16170 , n5739 );
nand ( n16171 , n8454 , n16170 );
buf ( n16172 , n5740 );
buf ( n16173 , n16172 );
and ( n16174 , n16171 , n16173 );
not ( n16175 , n16171 );
not ( n16176 , n16172 );
and ( n16177 , n16175 , n16176 );
nor ( n16178 , n16174 , n16177 );
xor ( n16179 , n16169 , n16178 );
buf ( n16180 , n5741 );
nand ( n16181 , n6647 , n16180 );
buf ( n16182 , n5742 );
not ( n16183 , n16182 );
and ( n16184 , n16181 , n16183 );
not ( n16185 , n16181 );
buf ( n16186 , n16182 );
and ( n16187 , n16185 , n16186 );
nor ( n16188 , n16184 , n16187 );
xnor ( n16189 , n16179 , n16188 );
not ( n16190 , n16189 );
not ( n16191 , n16190 );
or ( n16192 , n16168 , n16191 );
not ( n16193 , n16167 );
nand ( n16194 , n16189 , n16193 );
nand ( n16195 , n16192 , n16194 );
buf ( n16196 , n16195 );
not ( n16197 , n16196 );
xnor ( n16198 , n16156 , n16197 );
not ( n16199 , n16198 );
not ( n16200 , n16199 );
and ( n16201 , n16154 , n16200 );
and ( n16202 , n16153 , n16199 );
nor ( n16203 , n16201 , n16202 );
not ( n16204 , n16203 );
not ( n16205 , n12410 );
not ( n16206 , n6659 );
or ( n16207 , n16205 , n16206 );
or ( n16208 , n6659 , n12410 );
nand ( n16209 , n16207 , n16208 );
and ( n16210 , n16209 , n12287 );
not ( n16211 , n16209 );
not ( n16212 , n12287 );
and ( n16213 , n16211 , n16212 );
nor ( n16214 , n16210 , n16213 );
not ( n16215 , n16214 );
not ( n16216 , n16215 );
buf ( n16217 , n5743 );
not ( n16218 , n16217 );
not ( n16219 , n12128 );
or ( n16220 , n16218 , n16219 );
or ( n16221 , n12128 , n16217 );
nand ( n16222 , n16220 , n16221 );
not ( n16223 , n13023 );
not ( n16224 , n13043 );
or ( n16225 , n16223 , n16224 );
not ( n16226 , n13023 );
nand ( n16227 , n13042 , n16226 );
nand ( n16228 , n16225 , n16227 );
buf ( n16229 , n16228 );
buf ( n16230 , n16229 );
and ( n16231 , n16222 , n16230 );
not ( n16232 , n16222 );
not ( n16233 , n16229 );
and ( n16234 , n16232 , n16233 );
nor ( n16235 , n16231 , n16234 );
not ( n16236 , n16235 );
buf ( n16237 , n5744 );
nand ( n16238 , n10947 , n16237 );
buf ( n16239 , n16238 );
buf ( n16240 , n5745 );
buf ( n16241 , n16240 );
and ( n16242 , n16239 , n16241 );
not ( n16243 , n16239 );
not ( n16244 , n16240 );
and ( n16245 , n16243 , n16244 );
nor ( n16246 , n16242 , n16245 );
not ( n16247 , n16246 );
not ( n16248 , n16247 );
xor ( n16249 , n10994 , n11013 );
xnor ( n16250 , n16249 , n11003 );
buf ( n16251 , n16250 );
not ( n16252 , n16251 );
or ( n16253 , n16248 , n16252 );
buf ( n16254 , n11015 );
nand ( n16255 , n16254 , n16246 );
nand ( n16256 , n16253 , n16255 );
buf ( n16257 , n11054 );
not ( n16258 , n16257 );
buf ( n16259 , n16258 );
and ( n16260 , n16256 , n16259 );
not ( n16261 , n16256 );
not ( n16262 , n16259 );
and ( n16263 , n16261 , n16262 );
nor ( n16264 , n16260 , n16263 );
nand ( n16265 , n16236 , n16264 );
not ( n16266 , n16265 );
or ( n16267 , n16216 , n16266 );
or ( n16268 , n16265 , n16215 );
nand ( n16269 , n16267 , n16268 );
not ( n16270 , n16269 );
and ( n16271 , n16204 , n16270 );
and ( n16272 , n16203 , n16269 );
nor ( n16273 , n16271 , n16272 );
not ( n16274 , n16273 );
not ( n16275 , n16274 );
and ( n16276 , n16024 , n16275 );
and ( n16277 , n16023 , n16274 );
nor ( n16278 , n16276 , n16277 );
not ( n16279 , n16278 );
or ( n16280 , n15584 , n16279 );
not ( n16281 , n15583 );
not ( n16282 , n16273 );
not ( n16283 , n16282 );
not ( n16284 , n16021 );
or ( n16285 , n16283 , n16284 );
nand ( n16286 , n16022 , n16273 );
nand ( n16287 , n16285 , n16286 );
nand ( n16288 , n16281 , n16287 );
nand ( n16289 , n16280 , n16288 );
buf ( n16290 , n5746 );
nand ( n16291 , n7107 , n16290 );
buf ( n16292 , n5747 );
buf ( n16293 , n16292 );
and ( n16294 , n16291 , n16293 );
not ( n16295 , n16291 );
not ( n16296 , n16292 );
and ( n16297 , n16295 , n16296 );
nor ( n16298 , n16294 , n16297 );
not ( n16299 , n16298 );
not ( n16300 , n16299 );
buf ( n16301 , n5748 );
buf ( n16302 , n16301 );
not ( n16303 , n16302 );
buf ( n16304 , n5749 );
not ( n16305 , n16304 );
not ( n16306 , n16305 );
or ( n16307 , n16303 , n16306 );
not ( n16308 , n16301 );
buf ( n16309 , n16304 );
nand ( n16310 , n16308 , n16309 );
nand ( n16311 , n16307 , n16310 );
buf ( n16312 , n5750 );
not ( n16313 , n16312 );
and ( n16314 , n16311 , n16313 );
not ( n16315 , n16311 );
buf ( n16316 , n16312 );
and ( n16317 , n16315 , n16316 );
nor ( n16318 , n16314 , n16317 );
buf ( n16319 , n5751 );
nand ( n16320 , n7013 , n16319 );
buf ( n16321 , n5752 );
buf ( n16322 , n16321 );
and ( n16323 , n16320 , n16322 );
not ( n16324 , n16320 );
not ( n16325 , n16321 );
and ( n16326 , n16324 , n16325 );
nor ( n16327 , n16323 , n16326 );
xor ( n16328 , n16318 , n16327 );
buf ( n16329 , n5753 );
nand ( n16330 , n8176 , n16329 );
buf ( n16331 , n5754 );
not ( n16332 , n16331 );
and ( n16333 , n16330 , n16332 );
not ( n16334 , n16330 );
buf ( n16335 , n16331 );
and ( n16336 , n16334 , n16335 );
nor ( n16337 , n16333 , n16336 );
xnor ( n16338 , n16328 , n16337 );
not ( n16339 , n16338 );
xor ( n16340 , n16300 , n16339 );
buf ( n16341 , n5755 );
buf ( n16342 , n16341 );
not ( n16343 , n13401 );
buf ( n16344 , n5756 );
buf ( n16345 , n16344 );
and ( n16346 , n16343 , n16345 );
not ( n16347 , n16343 );
not ( n16348 , n16344 );
and ( n16349 , n16347 , n16348 );
nor ( n16350 , n16346 , n16349 );
xor ( n16351 , n16342 , n16350 );
buf ( n16352 , n5757 );
buf ( n16353 , n5758 );
xor ( n16354 , n16352 , n16353 );
buf ( n16355 , n5759 );
nand ( n16356 , n8223 , n16355 );
xnor ( n16357 , n16354 , n16356 );
xnor ( n16358 , n16351 , n16357 );
buf ( n16359 , n16358 );
xnor ( n16360 , n16340 , n16359 );
not ( n16361 , n16360 );
not ( n16362 , n6906 );
not ( n16363 , n13133 );
or ( n16364 , n16362 , n16363 );
or ( n16365 , n13133 , n6906 );
nand ( n16366 , n16364 , n16365 );
not ( n16367 , n16366 );
not ( n16368 , n14458 );
and ( n16369 , n16367 , n16368 );
and ( n16370 , n16366 , n14458 );
nor ( n16371 , n16369 , n16370 );
not ( n16372 , n16371 );
nand ( n16373 , n16361 , n16372 );
not ( n16374 , n16373 );
buf ( n16375 , n9725 );
not ( n16376 , n16375 );
not ( n16377 , n6526 );
or ( n16378 , n16376 , n16377 );
or ( n16379 , n6526 , n16375 );
nand ( n16380 , n16378 , n16379 );
not ( n16381 , n6572 );
and ( n16382 , n16380 , n16381 );
not ( n16383 , n16380 );
and ( n16384 , n16383 , n6572 );
nor ( n16385 , n16382 , n16384 );
not ( n16386 , n16385 );
and ( n16387 , n16374 , n16386 );
and ( n16388 , n16373 , n16385 );
nor ( n16389 , n16387 , n16388 );
not ( n16390 , n16389 );
not ( n16391 , n16390 );
not ( n16392 , n16229 );
buf ( n16393 , n5760 );
nand ( n16394 , n8781 , n16393 );
buf ( n16395 , n5761 );
buf ( n16396 , n16395 );
and ( n16397 , n16394 , n16396 );
not ( n16398 , n16394 );
not ( n16399 , n16395 );
and ( n16400 , n16398 , n16399 );
nor ( n16401 , n16397 , n16400 );
buf ( n16402 , n16401 );
not ( n16403 , n12127 );
and ( n16404 , n16402 , n16403 );
not ( n16405 , n16402 );
xor ( n16406 , n12107 , n12116 );
not ( n16407 , n12126 );
xnor ( n16408 , n16406 , n16407 );
and ( n16409 , n16405 , n16408 );
nor ( n16410 , n16404 , n16409 );
not ( n16411 , n16410 );
and ( n16412 , n16392 , n16411 );
and ( n16413 , n16229 , n16410 );
nor ( n16414 , n16412 , n16413 );
buf ( n16415 , n5762 );
buf ( n16416 , n16415 );
not ( n16417 , n16416 );
buf ( n16418 , n5763 );
not ( n16419 , n16418 );
not ( n16420 , n16419 );
or ( n16421 , n16417 , n16420 );
not ( n16422 , n16415 );
buf ( n16423 , n16418 );
nand ( n16424 , n16422 , n16423 );
nand ( n16425 , n16421 , n16424 );
buf ( n16426 , n5764 );
buf ( n16427 , n16426 );
and ( n16428 , n16425 , n16427 );
not ( n16429 , n16425 );
not ( n16430 , n16426 );
and ( n16431 , n16429 , n16430 );
nor ( n16432 , n16428 , n16431 );
buf ( n16433 , n5765 );
nand ( n16434 , n9160 , n16433 );
buf ( n16435 , n5766 );
not ( n16436 , n16435 );
and ( n16437 , n16434 , n16436 );
not ( n16438 , n16434 );
buf ( n16439 , n16435 );
and ( n16440 , n16438 , n16439 );
nor ( n16441 , n16437 , n16440 );
xor ( n16442 , n16432 , n16441 );
buf ( n16443 , n5767 );
nand ( n16444 , n6647 , n16443 );
buf ( n16445 , n5768 );
not ( n16446 , n16445 );
and ( n16447 , n16444 , n16446 );
not ( n16448 , n16444 );
buf ( n16449 , n16445 );
and ( n16450 , n16448 , n16449 );
nor ( n16451 , n16447 , n16450 );
xnor ( n16452 , n16442 , n16451 );
not ( n16453 , n16452 );
not ( n16454 , n16453 );
not ( n16455 , n16454 );
not ( n16456 , n7643 );
and ( n16457 , n16455 , n16456 );
buf ( n16458 , n16452 );
and ( n16459 , n16458 , n7643 );
nor ( n16460 , n16457 , n16459 );
not ( n16461 , n15928 );
buf ( n16462 , n5769 );
not ( n16463 , n16462 );
not ( n16464 , n16463 );
or ( n16465 , n16461 , n16464 );
not ( n16466 , n15927 );
buf ( n16467 , n16462 );
nand ( n16468 , n16466 , n16467 );
nand ( n16469 , n16465 , n16468 );
buf ( n16470 , n5770 );
not ( n16471 , n16470 );
and ( n16472 , n16469 , n16471 );
not ( n16473 , n16469 );
buf ( n16474 , n16470 );
and ( n16475 , n16473 , n16474 );
nor ( n16476 , n16472 , n16475 );
buf ( n16477 , n5771 );
nand ( n16478 , n7698 , n16477 );
buf ( n16479 , n5772 );
xor ( n16480 , n16478 , n16479 );
xor ( n16481 , n16476 , n16480 );
buf ( n16482 , n5773 );
nand ( n16483 , n13581 , n16482 );
buf ( n16484 , n5774 );
not ( n16485 , n16484 );
and ( n16486 , n16483 , n16485 );
not ( n16487 , n16483 );
buf ( n16488 , n16484 );
and ( n16489 , n16487 , n16488 );
nor ( n16490 , n16486 , n16489 );
xnor ( n16491 , n16481 , n16490 );
not ( n16492 , n16491 );
not ( n16493 , n16492 );
and ( n16494 , n16460 , n16493 );
not ( n16495 , n16460 );
buf ( n16496 , n16491 );
not ( n16497 , n16496 );
and ( n16498 , n16495 , n16497 );
nor ( n16499 , n16494 , n16498 );
nand ( n16500 , n16414 , n16499 );
not ( n16501 , n16500 );
buf ( n16502 , n5775 );
buf ( n16503 , n16502 );
not ( n16504 , n16503 );
buf ( n16505 , n5776 );
not ( n16506 , n16505 );
not ( n16507 , n16506 );
or ( n16508 , n16504 , n16507 );
not ( n16509 , n16502 );
buf ( n16510 , n16505 );
nand ( n16511 , n16509 , n16510 );
nand ( n16512 , n16508 , n16511 );
buf ( n16513 , n5777 );
not ( n16514 , n16513 );
and ( n16515 , n16512 , n16514 );
not ( n16516 , n16512 );
buf ( n16517 , n16513 );
and ( n16518 , n16516 , n16517 );
nor ( n16519 , n16515 , n16518 );
buf ( n16520 , n5778 );
nand ( n16521 , n8537 , n16520 );
buf ( n16522 , n5779 );
buf ( n16523 , n16522 );
and ( n16524 , n16521 , n16523 );
not ( n16525 , n16521 );
not ( n16526 , n16522 );
and ( n16527 , n16525 , n16526 );
nor ( n16528 , n16524 , n16527 );
xor ( n16529 , n16519 , n16528 );
buf ( n16530 , n5780 );
nand ( n16531 , n7107 , n16530 );
buf ( n16532 , n5781 );
buf ( n16533 , n16532 );
and ( n16534 , n16531 , n16533 );
not ( n16535 , n16531 );
not ( n16536 , n16532 );
and ( n16537 , n16535 , n16536 );
nor ( n16538 , n16534 , n16537 );
not ( n16539 , n16538 );
xor ( n16540 , n16529 , n16539 );
not ( n16541 , n16540 );
not ( n16542 , n16541 );
buf ( n16543 , n5782 );
nand ( n16544 , n8364 , n16543 );
buf ( n16545 , n5783 );
buf ( n16546 , n16545 );
and ( n16547 , n16544 , n16546 );
not ( n16548 , n16544 );
not ( n16549 , n16545 );
and ( n16550 , n16548 , n16549 );
nor ( n16551 , n16547 , n16550 );
buf ( n16552 , n16551 );
not ( n16553 , n16552 );
not ( n16554 , n16553 );
buf ( n16555 , n5784 );
buf ( n16556 , n16555 );
not ( n16557 , n16556 );
buf ( n16558 , n5785 );
not ( n16559 , n16558 );
not ( n16560 , n16559 );
or ( n16561 , n16557 , n16560 );
not ( n16562 , n16555 );
buf ( n16563 , n16558 );
nand ( n16564 , n16562 , n16563 );
nand ( n16565 , n16561 , n16564 );
buf ( n16566 , n5786 );
not ( n16567 , n16566 );
and ( n16568 , n16565 , n16567 );
not ( n16569 , n16565 );
buf ( n16570 , n16566 );
and ( n16571 , n16569 , n16570 );
nor ( n16572 , n16568 , n16571 );
buf ( n16573 , n5787 );
nand ( n16574 , n9160 , n16573 );
buf ( n16575 , n5788 );
not ( n16576 , n16575 );
and ( n16577 , n16574 , n16576 );
not ( n16578 , n16574 );
buf ( n16579 , n16575 );
and ( n16580 , n16578 , n16579 );
nor ( n16581 , n16577 , n16580 );
xor ( n16582 , n16572 , n16581 );
buf ( n16583 , n5789 );
nand ( n16584 , n7258 , n16583 );
buf ( n16585 , n5790 );
not ( n16586 , n16585 );
and ( n16587 , n16584 , n16586 );
not ( n16588 , n16584 );
buf ( n16589 , n16585 );
and ( n16590 , n16588 , n16589 );
nor ( n16591 , n16587 , n16590 );
xnor ( n16592 , n16582 , n16591 );
not ( n16593 , n16592 );
not ( n16594 , n16593 );
or ( n16595 , n16554 , n16594 );
not ( n16596 , n16592 );
not ( n16597 , n16596 );
nand ( n16598 , n16597 , n16552 );
nand ( n16599 , n16595 , n16598 );
not ( n16600 , n16599 );
or ( n16601 , n16542 , n16600 );
or ( n16602 , n16599 , n16541 );
nand ( n16603 , n16601 , n16602 );
not ( n16604 , n16603 );
and ( n16605 , n16501 , n16604 );
and ( n16606 , n16500 , n16603 );
nor ( n16607 , n16605 , n16606 );
not ( n16608 , n16607 );
not ( n16609 , n16195 );
not ( n16610 , n16609 );
and ( n16611 , n9642 , n8885 );
not ( n16612 , n9642 );
and ( n16613 , n16612 , n8886 );
or ( n16614 , n16611 , n16613 );
not ( n16615 , n16614 );
and ( n16616 , n16610 , n16615 );
and ( n16617 , n16609 , n16614 );
nor ( n16618 , n16616 , n16617 );
not ( n16619 , n9290 );
buf ( n16620 , n5791 );
buf ( n16621 , n16620 );
not ( n16622 , n16621 );
buf ( n16623 , n5792 );
not ( n16624 , n16623 );
not ( n16625 , n16624 );
or ( n16626 , n16622 , n16625 );
not ( n16627 , n16620 );
buf ( n16628 , n16623 );
nand ( n16629 , n16627 , n16628 );
nand ( n16630 , n16626 , n16629 );
buf ( n16631 , n5793 );
buf ( n16632 , n16631 );
and ( n16633 , n16630 , n16632 );
not ( n16634 , n16630 );
not ( n16635 , n16631 );
and ( n16636 , n16634 , n16635 );
nor ( n16637 , n16633 , n16636 );
buf ( n16638 , n5794 );
nand ( n16639 , n7868 , n16638 );
buf ( n16640 , n5795 );
buf ( n16641 , n16640 );
and ( n16642 , n16639 , n16641 );
not ( n16643 , n16639 );
not ( n16644 , n16640 );
and ( n16645 , n16643 , n16644 );
nor ( n16646 , n16642 , n16645 );
xor ( n16647 , n16637 , n16646 );
buf ( n16648 , n5796 );
nand ( n16649 , n7912 , n16648 );
buf ( n16650 , n5797 );
buf ( n16651 , n16650 );
and ( n16652 , n16649 , n16651 );
not ( n16653 , n16649 );
not ( n16654 , n16650 );
and ( n16655 , n16653 , n16654 );
nor ( n16656 , n16652 , n16655 );
xnor ( n16657 , n16647 , n16656 );
buf ( n16658 , n16657 );
not ( n16659 , n16658 );
or ( n16660 , n16619 , n16659 );
not ( n16661 , n16657 );
not ( n16662 , n16661 );
or ( n16663 , n16662 , n9290 );
nand ( n16664 , n16660 , n16663 );
buf ( n16665 , n5798 );
buf ( n16666 , n16665 );
buf ( n16667 , n5799 );
buf ( n16668 , n16667 );
not ( n16669 , n16668 );
buf ( n16670 , n5800 );
not ( n16671 , n16670 );
not ( n16672 , n16671 );
or ( n16673 , n16669 , n16672 );
not ( n16674 , n16667 );
buf ( n16675 , n16670 );
nand ( n16676 , n16674 , n16675 );
nand ( n16677 , n16673 , n16676 );
xor ( n16678 , n16666 , n16677 );
xor ( n16679 , n10978 , n16244 );
xnor ( n16680 , n16679 , n16238 );
xnor ( n16681 , n16678 , n16680 );
not ( n16682 , n16681 );
and ( n16683 , n16664 , n16682 );
not ( n16684 , n16664 );
not ( n16685 , n16682 );
and ( n16686 , n16684 , n16685 );
or ( n16687 , n16683 , n16686 );
nand ( n16688 , n16618 , n16687 );
not ( n16689 , n14150 );
not ( n16690 , n15518 );
or ( n16691 , n16689 , n16690 );
not ( n16692 , n14150 );
nand ( n16693 , n16692 , n15521 );
nand ( n16694 , n16691 , n16693 );
and ( n16695 , n16694 , n15563 );
not ( n16696 , n16694 );
and ( n16697 , n16696 , n15576 );
nor ( n16698 , n16695 , n16697 );
not ( n16699 , n16698 );
and ( n16700 , n16688 , n16699 );
not ( n16701 , n16688 );
and ( n16702 , n16701 , n16698 );
nor ( n16703 , n16700 , n16702 );
not ( n16704 , n16703 );
or ( n16705 , n16608 , n16704 );
or ( n16706 , n16703 , n16607 );
nand ( n16707 , n16705 , n16706 );
not ( n16708 , n16707 );
not ( n16709 , n16708 );
or ( n16710 , n16391 , n16709 );
nand ( n16711 , n16707 , n16389 );
nand ( n16712 , n16710 , n16711 );
buf ( n16713 , n14555 );
xor ( n16714 , n16713 , n14567 );
xnor ( n16715 , n16714 , n14576 );
buf ( n16716 , n16715 );
not ( n16717 , n16716 );
buf ( n16718 , n8373 );
not ( n16719 , n16718 );
not ( n16720 , n7679 );
buf ( n16721 , n5801 );
not ( n16722 , n16721 );
not ( n16723 , n16722 );
or ( n16724 , n16720 , n16723 );
not ( n16725 , n7678 );
buf ( n16726 , n16721 );
nand ( n16727 , n16725 , n16726 );
nand ( n16728 , n16724 , n16727 );
buf ( n16729 , n5802 );
buf ( n16730 , n16729 );
and ( n16731 , n16728 , n16730 );
not ( n16732 , n16728 );
not ( n16733 , n16729 );
and ( n16734 , n16732 , n16733 );
nor ( n16735 , n16731 , n16734 );
buf ( n16736 , n5803 );
nand ( n16737 , n8364 , n16736 );
buf ( n16738 , n5804 );
buf ( n16739 , n16738 );
and ( n16740 , n16737 , n16739 );
not ( n16741 , n16737 );
not ( n16742 , n16738 );
and ( n16743 , n16741 , n16742 );
nor ( n16744 , n16740 , n16743 );
xor ( n16745 , n16735 , n16744 );
buf ( n16746 , n5805 );
nand ( n16747 , n8608 , n16746 );
buf ( n16748 , n5806 );
buf ( n16749 , n16748 );
and ( n16750 , n16747 , n16749 );
not ( n16751 , n16747 );
not ( n16752 , n16748 );
and ( n16753 , n16751 , n16752 );
nor ( n16754 , n16750 , n16753 );
xnor ( n16755 , n16745 , n16754 );
not ( n16756 , n16755 );
not ( n16757 , n16756 );
or ( n16758 , n16719 , n16757 );
or ( n16759 , n16756 , n16718 );
nand ( n16760 , n16758 , n16759 );
not ( n16761 , n16760 );
and ( n16762 , n16717 , n16761 );
not ( n16763 , n16715 );
not ( n16764 , n16763 );
and ( n16765 , n16764 , n16760 );
nor ( n16766 , n16762 , n16765 );
not ( n16767 , n16766 );
not ( n16768 , n16767 );
not ( n16769 , n11710 );
buf ( n16770 , n5807 );
not ( n16771 , n16770 );
buf ( n16772 , n5808 );
not ( n16773 , n16772 );
nand ( n16774 , n16773 , n13862 );
not ( n16775 , n13861 );
buf ( n16776 , n16772 );
nand ( n16777 , n16775 , n16776 );
and ( n16778 , n16774 , n16777 );
xor ( n16779 , n16771 , n16778 );
buf ( n16780 , n5809 );
nand ( n16781 , n8176 , n16780 );
buf ( n16782 , n5810 );
buf ( n16783 , n16782 );
and ( n16784 , n16781 , n16783 );
not ( n16785 , n16781 );
not ( n16786 , n16782 );
and ( n16787 , n16785 , n16786 );
nor ( n16788 , n16784 , n16787 );
not ( n16789 , n16788 );
buf ( n16790 , n5811 );
not ( n16791 , n16790 );
and ( n16792 , n16789 , n16791 );
and ( n16793 , n16788 , n16790 );
nor ( n16794 , n16792 , n16793 );
xnor ( n16795 , n16779 , n16794 );
not ( n16796 , n16795 );
not ( n16797 , n16796 );
or ( n16798 , n16769 , n16797 );
or ( n16799 , n16796 , n11710 );
nand ( n16800 , n16798 , n16799 );
buf ( n16801 , n12651 );
and ( n16802 , n16800 , n16801 );
not ( n16803 , n16800 );
buf ( n16804 , n10666 );
and ( n16805 , n16803 , n16804 );
nor ( n16806 , n16802 , n16805 );
not ( n16807 , n16806 );
not ( n16808 , n15877 );
buf ( n16809 , n5812 );
not ( n16810 , n16809 );
not ( n16811 , n16810 );
or ( n16812 , n16808 , n16811 );
not ( n16813 , n15876 );
buf ( n16814 , n16809 );
nand ( n16815 , n16813 , n16814 );
nand ( n16816 , n16812 , n16815 );
buf ( n16817 , n5813 );
buf ( n16818 , n16817 );
and ( n16819 , n16816 , n16818 );
not ( n16820 , n16816 );
not ( n16821 , n16817 );
and ( n16822 , n16820 , n16821 );
nor ( n16823 , n16819 , n16822 );
buf ( n16824 , n5814 );
nand ( n16825 , n6577 , n16824 );
buf ( n16826 , n5815 );
xor ( n16827 , n16825 , n16826 );
xor ( n16828 , n16823 , n16827 );
buf ( n16829 , n5816 );
nand ( n16830 , n7569 , n16829 );
buf ( n16831 , n5817 );
buf ( n16832 , n16831 );
and ( n16833 , n16830 , n16832 );
not ( n16834 , n16830 );
not ( n16835 , n16831 );
and ( n16836 , n16834 , n16835 );
nor ( n16837 , n16833 , n16836 );
xnor ( n16838 , n16828 , n16837 );
not ( n16839 , n16838 );
not ( n16840 , n13929 );
and ( n16841 , n16839 , n16840 );
and ( n16842 , n16838 , n13929 );
nor ( n16843 , n16841 , n16842 );
buf ( n16844 , n5818 );
buf ( n16845 , n16844 );
not ( n16846 , n16845 );
buf ( n16847 , n5819 );
not ( n16848 , n16847 );
not ( n16849 , n16848 );
or ( n16850 , n16846 , n16849 );
not ( n16851 , n16844 );
buf ( n16852 , n16847 );
nand ( n16853 , n16851 , n16852 );
nand ( n16854 , n16850 , n16853 );
buf ( n16855 , n5820 );
buf ( n16856 , n16855 );
and ( n16857 , n16854 , n16856 );
not ( n16858 , n16854 );
not ( n16859 , n16855 );
and ( n16860 , n16858 , n16859 );
nor ( n16861 , n16857 , n16860 );
buf ( n16862 , n5821 );
nand ( n16863 , n8364 , n16862 );
buf ( n16864 , n5822 );
buf ( n16865 , n16864 );
and ( n16866 , n16863 , n16865 );
not ( n16867 , n16863 );
not ( n16868 , n16864 );
and ( n16869 , n16867 , n16868 );
nor ( n16870 , n16866 , n16869 );
xor ( n16871 , n16861 , n16870 );
buf ( n16872 , n5823 );
nand ( n16873 , n8125 , n16872 );
buf ( n16874 , n5824 );
not ( n16875 , n16874 );
and ( n16876 , n16873 , n16875 );
not ( n16877 , n16873 );
buf ( n16878 , n16874 );
and ( n16879 , n16877 , n16878 );
nor ( n16880 , n16876 , n16879 );
xnor ( n16881 , n16871 , n16880 );
buf ( n16882 , n16881 );
xor ( n16883 , n16843 , n16882 );
buf ( n16884 , n16883 );
nand ( n16885 , n16807 , n16884 );
not ( n16886 , n16885 );
or ( n16887 , n16768 , n16886 );
or ( n16888 , n16885 , n16767 );
nand ( n16889 , n16887 , n16888 );
not ( n16890 , n16889 );
buf ( n16891 , n15087 );
not ( n16892 , n16891 );
not ( n16893 , n14507 );
or ( n16894 , n16892 , n16893 );
not ( n16895 , n15701 );
or ( n16896 , n16895 , n16891 );
nand ( n16897 , n16894 , n16896 );
buf ( n16898 , n15748 );
and ( n16899 , n16897 , n16898 );
not ( n16900 , n16897 );
and ( n16901 , n16900 , n15751 );
nor ( n16902 , n16899 , n16901 );
not ( n16903 , n11974 );
xor ( n16904 , n10803 , n10822 );
not ( n16905 , n10812 );
xnor ( n16906 , n16904 , n16905 );
not ( n16907 , n16906 );
not ( n16908 , n16907 );
or ( n16909 , n16903 , n16908 );
not ( n16910 , n10824 );
or ( n16911 , n16910 , n11974 );
nand ( n16912 , n16909 , n16911 );
not ( n16913 , n14309 );
not ( n16914 , n16913 );
and ( n16915 , n16912 , n16914 );
not ( n16916 , n16912 );
not ( n16917 , n16914 );
and ( n16918 , n16916 , n16917 );
nor ( n16919 , n16915 , n16918 );
buf ( n16920 , n16919 );
nand ( n16921 , n16902 , n16920 );
not ( n16922 , n16921 );
not ( n16923 , n16055 );
not ( n16924 , n14175 );
or ( n16925 , n16923 , n16924 );
or ( n16926 , n14175 , n16055 );
nand ( n16927 , n16925 , n16926 );
and ( n16928 , n16927 , n14153 );
not ( n16929 , n16927 );
and ( n16930 , n16929 , n14152 );
nor ( n16931 , n16928 , n16930 );
not ( n16932 , n16931 );
not ( n16933 , n16932 );
and ( n16934 , n16922 , n16933 );
and ( n16935 , n16921 , n16932 );
nor ( n16936 , n16934 , n16935 );
not ( n16937 , n16936 );
and ( n16938 , n16890 , n16937 );
and ( n16939 , n16889 , n16936 );
nor ( n16940 , n16938 , n16939 );
and ( n16941 , n16712 , n16940 );
not ( n16942 , n16712 );
not ( n16943 , n16940 );
and ( n16944 , n16942 , n16943 );
nor ( n16945 , n16941 , n16944 );
buf ( n16946 , n16945 );
and ( n16947 , n16289 , n16946 );
not ( n16948 , n16289 );
not ( n16949 , n16946 );
and ( n16950 , n16948 , n16949 );
nor ( n16951 , n16947 , n16950 );
not ( n16952 , n16951 );
not ( n16953 , n15444 );
buf ( n16954 , n5825 );
buf ( n16955 , n16954 );
not ( n16956 , n16955 );
buf ( n16957 , n5826 );
not ( n16958 , n16957 );
not ( n16959 , n16958 );
or ( n16960 , n16956 , n16959 );
not ( n16961 , n16954 );
buf ( n16962 , n16957 );
nand ( n16963 , n16961 , n16962 );
nand ( n16964 , n16960 , n16963 );
buf ( n16965 , n5827 );
buf ( n16966 , n16965 );
and ( n16967 , n16964 , n16966 );
not ( n16968 , n16964 );
not ( n16969 , n16965 );
and ( n16970 , n16968 , n16969 );
nor ( n16971 , n16967 , n16970 );
xor ( n16972 , n16971 , n16551 );
buf ( n16973 , n5828 );
nand ( n16974 , n6605 , n16973 );
buf ( n16975 , n5829 );
not ( n16976 , n16975 );
and ( n16977 , n16974 , n16976 );
not ( n16978 , n16974 );
buf ( n16979 , n16975 );
and ( n16980 , n16978 , n16979 );
nor ( n16981 , n16977 , n16980 );
xnor ( n16982 , n16972 , n16981 );
buf ( n16983 , n16982 );
not ( n16984 , n16983 );
not ( n16985 , n16984 );
or ( n16986 , n16953 , n16985 );
or ( n16987 , n16984 , n15444 );
nand ( n16988 , n16986 , n16987 );
buf ( n16989 , n15762 );
xor ( n16990 , n16989 , n15774 );
xnor ( n16991 , n16990 , n15790 );
not ( n16992 , n16991 );
not ( n16993 , n16992 );
and ( n16994 , n16988 , n16993 );
not ( n16995 , n16988 );
and ( n16996 , n16995 , n16992 );
nor ( n16997 , n16994 , n16996 );
not ( n16998 , n16997 );
nand ( n16999 , n16998 , n10964 );
not ( n17000 , n16999 );
not ( n17001 , n14889 );
buf ( n17002 , n5830 );
buf ( n17003 , n17002 );
not ( n17004 , n17003 );
buf ( n17005 , n5831 );
not ( n17006 , n17005 );
not ( n17007 , n17006 );
or ( n17008 , n17004 , n17007 );
not ( n17009 , n17002 );
buf ( n17010 , n17005 );
nand ( n17011 , n17009 , n17010 );
nand ( n17012 , n17008 , n17011 );
buf ( n17013 , n5832 );
not ( n17014 , n17013 );
and ( n17015 , n17012 , n17014 );
not ( n17016 , n17012 );
buf ( n17017 , n17013 );
and ( n17018 , n17016 , n17017 );
nor ( n17019 , n17015 , n17018 );
buf ( n17020 , n5833 );
nand ( n17021 , n8454 , n17020 );
buf ( n17022 , n5834 );
buf ( n17023 , n17022 );
and ( n17024 , n17021 , n17023 );
not ( n17025 , n17021 );
not ( n17026 , n17022 );
and ( n17027 , n17025 , n17026 );
nor ( n17028 , n17024 , n17027 );
xor ( n17029 , n17019 , n17028 );
buf ( n17030 , n5835 );
nand ( n17031 , n6634 , n17030 );
buf ( n17032 , n5836 );
not ( n17033 , n17032 );
and ( n17034 , n17031 , n17033 );
not ( n17035 , n17031 );
buf ( n17036 , n17032 );
and ( n17037 , n17035 , n17036 );
nor ( n17038 , n17034 , n17037 );
xnor ( n17039 , n17029 , n17038 );
buf ( n17040 , n17039 );
not ( n17041 , n17040 );
or ( n17042 , n17001 , n17041 );
not ( n17043 , n17039 );
not ( n17044 , n17043 );
or ( n17045 , n17044 , n14889 );
nand ( n17046 , n17042 , n17045 );
buf ( n17047 , n5837 );
buf ( n17048 , n17047 );
not ( n17049 , n17048 );
buf ( n17050 , n5838 );
not ( n17051 , n17050 );
not ( n17052 , n17051 );
or ( n17053 , n17049 , n17052 );
not ( n17054 , n17047 );
buf ( n17055 , n17050 );
nand ( n17056 , n17054 , n17055 );
nand ( n17057 , n17053 , n17056 );
buf ( n17058 , n5839 );
not ( n17059 , n17058 );
and ( n17060 , n17057 , n17059 );
not ( n17061 , n17057 );
buf ( n17062 , n17058 );
and ( n17063 , n17061 , n17062 );
nor ( n17064 , n17060 , n17063 );
buf ( n17065 , n5840 );
nand ( n17066 , n7202 , n17065 );
buf ( n17067 , n5841 );
buf ( n17068 , n17067 );
and ( n17069 , n17066 , n17068 );
not ( n17070 , n17066 );
not ( n17071 , n17067 );
and ( n17072 , n17070 , n17071 );
nor ( n17073 , n17069 , n17072 );
xor ( n17074 , n17064 , n17073 );
buf ( n17075 , n5842 );
nand ( n17076 , n11946 , n17075 );
buf ( n17077 , n5843 );
buf ( n17078 , n17077 );
and ( n17079 , n17076 , n17078 );
not ( n17080 , n17076 );
not ( n17081 , n17077 );
and ( n17082 , n17080 , n17081 );
nor ( n17083 , n17079 , n17082 );
xnor ( n17084 , n17074 , n17083 );
not ( n17085 , n17084 );
buf ( n17086 , n17085 );
xor ( n17087 , n17046 , n17086 );
not ( n17088 , n17087 );
not ( n17089 , n17088 );
and ( n17090 , n17000 , n17089 );
and ( n17091 , n16999 , n17088 );
nor ( n17092 , n17090 , n17091 );
buf ( n17093 , n17092 );
not ( n17094 , n17093 );
buf ( n17095 , n5844 );
not ( n17096 , n17095 );
not ( n17097 , n17096 );
not ( n17098 , n15143 );
not ( n17099 , n17098 );
or ( n17100 , n17097 , n17099 );
not ( n17101 , n15144 );
or ( n17102 , n17101 , n17096 );
nand ( n17103 , n17100 , n17102 );
buf ( n17104 , n15187 );
not ( n17105 , n17104 );
and ( n17106 , n17103 , n17105 );
not ( n17107 , n17103 );
and ( n17108 , n17107 , n17104 );
nor ( n17109 , n17106 , n17108 );
buf ( n17110 , n13642 );
xor ( n17111 , n13661 , n13665 );
xnor ( n17112 , n17111 , n13675 );
not ( n17113 , n17112 );
not ( n17114 , n17113 );
buf ( n17115 , n5845 );
buf ( n17116 , n17115 );
not ( n17117 , n17116 );
and ( n17118 , n17114 , n17117 );
and ( n17119 , n13690 , n17116 );
nor ( n17120 , n17118 , n17119 );
not ( n17121 , n17120 );
xor ( n17122 , n17110 , n17121 );
not ( n17123 , n17122 );
nand ( n17124 , n17109 , n17123 );
not ( n17125 , n10589 );
and ( n17126 , n17124 , n17125 );
not ( n17127 , n17124 );
and ( n17128 , n17127 , n10589 );
nor ( n17129 , n17126 , n17128 );
not ( n17130 , n17129 );
not ( n17131 , n17130 );
not ( n17132 , n11094 );
buf ( n17133 , n5846 );
buf ( n17134 , n17133 );
not ( n17135 , n17134 );
buf ( n17136 , n9861 );
xor ( n17137 , n9893 , n17136 );
buf ( n17138 , n9871 );
xnor ( n17139 , n17137 , n17138 );
not ( n17140 , n17139 );
or ( n17141 , n17135 , n17140 );
not ( n17142 , n17134 );
nand ( n17143 , n17142 , n9898 );
nand ( n17144 , n17141 , n17143 );
not ( n17145 , n9940 );
buf ( n17146 , n17145 );
and ( n17147 , n17144 , n17146 );
not ( n17148 , n17144 );
and ( n17149 , n17148 , n9942 );
nor ( n17150 , n17147 , n17149 );
not ( n17151 , n8803 );
buf ( n17152 , n5847 );
buf ( n17153 , n17152 );
not ( n17154 , n17153 );
buf ( n17155 , n5848 );
not ( n17156 , n17155 );
not ( n17157 , n17156 );
or ( n17158 , n17154 , n17157 );
not ( n17159 , n17152 );
buf ( n17160 , n17155 );
nand ( n17161 , n17159 , n17160 );
nand ( n17162 , n17158 , n17161 );
buf ( n17163 , n5849 );
buf ( n17164 , n17163 );
and ( n17165 , n17162 , n17164 );
not ( n17166 , n17162 );
not ( n17167 , n17163 );
and ( n17168 , n17166 , n17167 );
nor ( n17169 , n17165 , n17168 );
buf ( n17170 , n5850 );
nand ( n17171 , n6634 , n17170 );
buf ( n17172 , n5851 );
buf ( n17173 , n17172 );
and ( n17174 , n17171 , n17173 );
not ( n17175 , n17171 );
not ( n17176 , n17172 );
and ( n17177 , n17175 , n17176 );
nor ( n17178 , n17174 , n17177 );
xor ( n17179 , n17169 , n17178 );
buf ( n17180 , n5852 );
nand ( n17181 , n8323 , n17180 );
buf ( n17182 , n5853 );
buf ( n17183 , n17182 );
and ( n17184 , n17181 , n17183 );
not ( n17185 , n17181 );
not ( n17186 , n17182 );
and ( n17187 , n17185 , n17186 );
nor ( n17188 , n17184 , n17187 );
buf ( n17189 , n17188 );
xnor ( n17190 , n17179 , n17189 );
not ( n17191 , n17190 );
or ( n17192 , n17151 , n17191 );
or ( n17193 , n17190 , n8803 );
nand ( n17194 , n17192 , n17193 );
buf ( n17195 , n5854 );
buf ( n17196 , n17195 );
not ( n17197 , n17196 );
buf ( n17198 , n5855 );
not ( n17199 , n17198 );
not ( n17200 , n17199 );
or ( n17201 , n17197 , n17200 );
not ( n17202 , n17195 );
buf ( n17203 , n17198 );
nand ( n17204 , n17202 , n17203 );
nand ( n17205 , n17201 , n17204 );
buf ( n17206 , n5856 );
buf ( n17207 , n17206 );
and ( n17208 , n17205 , n17207 );
not ( n17209 , n17205 );
not ( n17210 , n17206 );
and ( n17211 , n17209 , n17210 );
nor ( n17212 , n17208 , n17211 );
buf ( n17213 , n5857 );
nand ( n17214 , n7977 , n17213 );
buf ( n17215 , n5858 );
buf ( n17216 , n17215 );
and ( n17217 , n17214 , n17216 );
not ( n17218 , n17214 );
not ( n17219 , n17215 );
and ( n17220 , n17218 , n17219 );
nor ( n17221 , n17217 , n17220 );
xor ( n17222 , n17212 , n17221 );
buf ( n17223 , n5859 );
nand ( n17224 , n7355 , n17223 );
buf ( n17225 , n5860 );
buf ( n17226 , n17225 );
and ( n17227 , n17224 , n17226 );
not ( n17228 , n17224 );
not ( n17229 , n17225 );
and ( n17230 , n17228 , n17229 );
nor ( n17231 , n17227 , n17230 );
not ( n17232 , n17231 );
xor ( n17233 , n17222 , n17232 );
not ( n17234 , n17233 );
not ( n17235 , n17234 );
and ( n17236 , n17194 , n17235 );
not ( n17237 , n17194 );
buf ( n17238 , n17233 );
not ( n17239 , n17238 );
and ( n17240 , n17237 , n17239 );
nor ( n17241 , n17236 , n17240 );
nand ( n17242 , n17150 , n17241 );
not ( n17243 , n17242 );
or ( n17244 , n17132 , n17243 );
or ( n17245 , n17242 , n11094 );
nand ( n17246 , n17244 , n17245 );
not ( n17247 , n15603 );
not ( n17248 , n15633 );
not ( n17249 , n6479 );
and ( n17250 , n17248 , n17249 );
and ( n17251 , n15633 , n6479 );
nor ( n17252 , n17250 , n17251 );
and ( n17253 , n17247 , n17252 );
not ( n17254 , n17247 );
not ( n17255 , n17252 );
and ( n17256 , n17254 , n17255 );
nor ( n17257 , n17253 , n17256 );
not ( n17258 , n16881 );
not ( n17259 , n17258 );
not ( n17260 , n13915 );
not ( n17261 , n17260 );
xor ( n17262 , n16823 , n16827 );
xor ( n17263 , n17262 , n16837 );
not ( n17264 , n17263 );
or ( n17265 , n17261 , n17264 );
or ( n17266 , n17263 , n17260 );
nand ( n17267 , n17265 , n17266 );
not ( n17268 , n17267 );
or ( n17269 , n17259 , n17268 );
or ( n17270 , n17267 , n17258 );
nand ( n17271 , n17269 , n17270 );
nand ( n17272 , n17257 , n17271 );
not ( n17273 , n17272 );
not ( n17274 , n11278 );
and ( n17275 , n17273 , n17274 );
and ( n17276 , n17272 , n11278 );
nor ( n17277 , n17275 , n17276 );
nor ( n17278 , n17246 , n17277 );
not ( n17279 , n17278 );
nand ( n17280 , n17246 , n17277 );
nand ( n17281 , n17279 , n17280 );
not ( n17282 , n17281 );
and ( n17283 , n17131 , n17282 );
and ( n17284 , n17130 , n17281 );
nor ( n17285 , n17283 , n17284 );
not ( n17286 , n17285 );
not ( n17287 , n17286 );
nand ( n17288 , n16997 , n17087 );
not ( n17289 , n17288 );
not ( n17290 , n10870 );
and ( n17291 , n17289 , n17290 );
and ( n17292 , n17288 , n10870 );
nor ( n17293 , n17291 , n17292 );
not ( n17294 , n17293 );
buf ( n17295 , n8246 );
not ( n17296 , n17295 );
buf ( n17297 , n5861 );
buf ( n17298 , n17297 );
not ( n17299 , n17298 );
not ( n17300 , n12406 );
not ( n17301 , n17300 );
or ( n17302 , n17299 , n17301 );
not ( n17303 , n17297 );
nand ( n17304 , n17303 , n12407 );
nand ( n17305 , n17302 , n17304 );
buf ( n17306 , n5862 );
not ( n17307 , n17306 );
and ( n17308 , n17305 , n17307 );
not ( n17309 , n17305 );
buf ( n17310 , n17306 );
and ( n17311 , n17309 , n17310 );
nor ( n17312 , n17308 , n17311 );
buf ( n17313 , n5863 );
nand ( n17314 , n7563 , n17313 );
buf ( n17315 , n5864 );
buf ( n17316 , n17315 );
and ( n17317 , n17314 , n17316 );
not ( n17318 , n17314 );
not ( n17319 , n17315 );
and ( n17320 , n17318 , n17319 );
nor ( n17321 , n17317 , n17320 );
xor ( n17322 , n17312 , n17321 );
buf ( n17323 , n5865 );
nand ( n17324 , n6515 , n17323 );
buf ( n17325 , n5866 );
not ( n17326 , n17325 );
and ( n17327 , n17324 , n17326 );
not ( n17328 , n17324 );
buf ( n17329 , n17325 );
and ( n17330 , n17328 , n17329 );
nor ( n17331 , n17327 , n17330 );
xnor ( n17332 , n17322 , n17331 );
buf ( n17333 , n17332 );
not ( n17334 , n17333 );
or ( n17335 , n17296 , n17334 );
not ( n17336 , n17321 );
not ( n17337 , n17331 );
or ( n17338 , n17336 , n17337 );
or ( n17339 , n17321 , n17331 );
nand ( n17340 , n17338 , n17339 );
not ( n17341 , n17312 );
and ( n17342 , n17340 , n17341 );
not ( n17343 , n17340 );
and ( n17344 , n17343 , n17312 );
nor ( n17345 , n17342 , n17344 );
not ( n17346 , n17345 );
not ( n17347 , n17346 );
nand ( n17348 , n17347 , n8247 );
nand ( n17349 , n17335 , n17348 );
and ( n17350 , n17349 , n8996 );
not ( n17351 , n17349 );
and ( n17352 , n17351 , n8992 );
nor ( n17353 , n17350 , n17352 );
not ( n17354 , n17353 );
buf ( n17355 , n5867 );
buf ( n17356 , n17355 );
xor ( n17357 , n12185 , n12195 );
xnor ( n17358 , n17357 , n12205 );
buf ( n17359 , n17358 );
xor ( n17360 , n17356 , n17359 );
not ( n17361 , n12236 );
xnor ( n17362 , n17360 , n17361 );
nand ( n17363 , n17354 , n17362 );
not ( n17364 , n10757 );
and ( n17365 , n17363 , n17364 );
not ( n17366 , n17363 );
and ( n17367 , n17366 , n10757 );
nor ( n17368 , n17365 , n17367 );
not ( n17369 , n17368 );
or ( n17370 , n17294 , n17369 );
or ( n17371 , n17368 , n17293 );
nand ( n17372 , n17370 , n17371 );
not ( n17373 , n17372 );
not ( n17374 , n17373 );
or ( n17375 , n17287 , n17374 );
nand ( n17376 , n17285 , n17372 );
nand ( n17377 , n17375 , n17376 );
not ( n17378 , n17377 );
or ( n17379 , n17094 , n17378 );
or ( n17380 , n17377 , n17093 );
nand ( n17381 , n17379 , n17380 );
xor ( n17382 , n8895 , n8904 );
xnor ( n17383 , n17382 , n8912 );
xor ( n17384 , n9784 , n17383 );
buf ( n17385 , n5868 );
buf ( n17386 , n17385 );
not ( n17387 , n17386 );
buf ( n17388 , n5869 );
not ( n17389 , n17388 );
not ( n17390 , n17389 );
or ( n17391 , n17387 , n17390 );
not ( n17392 , n17385 );
buf ( n17393 , n17388 );
nand ( n17394 , n17392 , n17393 );
nand ( n17395 , n17391 , n17394 );
not ( n17396 , n17115 );
and ( n17397 , n17395 , n17396 );
not ( n17398 , n17395 );
and ( n17399 , n17398 , n17116 );
nor ( n17400 , n17397 , n17399 );
xor ( n17401 , n17400 , n13686 );
buf ( n17402 , n5870 );
nand ( n17403 , n11688 , n17402 );
buf ( n17404 , n5871 );
not ( n17405 , n17404 );
and ( n17406 , n17403 , n17405 );
not ( n17407 , n17403 );
buf ( n17408 , n17404 );
and ( n17409 , n17407 , n17408 );
nor ( n17410 , n17406 , n17409 );
xnor ( n17411 , n17401 , n17410 );
not ( n17412 , n17411 );
xnor ( n17413 , n17384 , n17412 );
not ( n17414 , n17238 );
buf ( n17415 , n8824 );
not ( n17416 , n17415 );
xor ( n17417 , n17169 , n17188 );
not ( n17418 , n17178 );
xnor ( n17419 , n17417 , n17418 );
not ( n17420 , n17419 );
or ( n17421 , n17416 , n17420 );
or ( n17422 , n17419 , n17415 );
nand ( n17423 , n17421 , n17422 );
not ( n17424 , n17423 );
or ( n17425 , n17414 , n17424 );
buf ( n17426 , n17233 );
or ( n17427 , n17423 , n17426 );
nand ( n17428 , n17425 , n17427 );
nand ( n17429 , n17413 , n17428 );
not ( n17430 , n17429 );
not ( n17431 , n15856 );
not ( n17432 , n7539 );
or ( n17433 , n17431 , n17432 );
not ( n17434 , n15856 );
nand ( n17435 , n17434 , n8985 );
nand ( n17436 , n17433 , n17435 );
and ( n17437 , n17436 , n7580 );
not ( n17438 , n17436 );
not ( n17439 , n7580 );
and ( n17440 , n17438 , n17439 );
nor ( n17441 , n17437 , n17440 );
not ( n17442 , n17441 );
not ( n17443 , n17442 );
and ( n17444 , n17430 , n17443 );
and ( n17445 , n17429 , n17442 );
nor ( n17446 , n17444 , n17445 );
not ( n17447 , n13006 );
not ( n17448 , n14091 );
and ( n17449 , n17447 , n17448 );
and ( n17450 , n13006 , n14091 );
nor ( n17451 , n17449 , n17450 );
not ( n17452 , n16341 );
xor ( n17453 , n17452 , n16350 );
xnor ( n17454 , n17453 , n16357 );
buf ( n17455 , n17454 );
and ( n17456 , n17451 , n17455 );
not ( n17457 , n17451 );
and ( n17458 , n17457 , n16359 );
nor ( n17459 , n17456 , n17458 );
not ( n17460 , n9715 );
not ( n17461 , n6525 );
or ( n17462 , n17460 , n17461 );
or ( n17463 , n6525 , n9715 );
nand ( n17464 , n17462 , n17463 );
and ( n17465 , n17464 , n6572 );
not ( n17466 , n17464 );
and ( n17467 , n17466 , n16381 );
nor ( n17468 , n17465 , n17467 );
nor ( n17469 , n17459 , n17468 );
not ( n17470 , n17469 );
not ( n17471 , n10616 );
buf ( n17472 , n5872 );
buf ( n17473 , n17472 );
not ( n17474 , n17473 );
not ( n17475 , n12651 );
or ( n17476 , n17474 , n17475 );
or ( n17477 , n12651 , n17473 );
nand ( n17478 , n17476 , n17477 );
not ( n17479 , n17478 );
and ( n17480 , n17471 , n17479 );
and ( n17481 , n10616 , n17478 );
nor ( n17482 , n17480 , n17481 );
not ( n17483 , n17482 );
or ( n17484 , n17470 , n17483 );
not ( n17485 , n17469 );
not ( n17486 , n17482 );
nand ( n17487 , n17485 , n17486 );
nand ( n17488 , n17484 , n17487 );
xor ( n17489 , n17446 , n17488 );
not ( n17490 , n16992 );
buf ( n17491 , n15468 );
not ( n17492 , n17491 );
not ( n17493 , n16982 );
not ( n17494 , n17493 );
or ( n17495 , n17492 , n17494 );
not ( n17496 , n17491 );
nand ( n17497 , n17496 , n16983 );
nand ( n17498 , n17495 , n17497 );
not ( n17499 , n17498 );
and ( n17500 , n17490 , n17499 );
not ( n17501 , n16991 );
and ( n17502 , n17501 , n17498 );
nor ( n17503 , n17500 , n17502 );
not ( n17504 , n17503 );
buf ( n17505 , n7796 );
not ( n17506 , n17505 );
buf ( n17507 , n5873 );
buf ( n17508 , n17507 );
not ( n17509 , n17508 );
buf ( n17510 , n5874 );
not ( n17511 , n17510 );
not ( n17512 , n17511 );
or ( n17513 , n17509 , n17512 );
not ( n17514 , n17507 );
buf ( n17515 , n17510 );
nand ( n17516 , n17514 , n17515 );
nand ( n17517 , n17513 , n17516 );
buf ( n17518 , n5875 );
not ( n17519 , n17518 );
and ( n17520 , n17517 , n17519 );
not ( n17521 , n17517 );
buf ( n17522 , n17518 );
and ( n17523 , n17521 , n17522 );
nor ( n17524 , n17520 , n17523 );
buf ( n17525 , n5876 );
nand ( n17526 , n7247 , n17525 );
buf ( n17527 , n5877 );
buf ( n17528 , n17527 );
and ( n17529 , n17526 , n17528 );
not ( n17530 , n17526 );
not ( n17531 , n17527 );
and ( n17532 , n17530 , n17531 );
nor ( n17533 , n17529 , n17532 );
xor ( n17534 , n17524 , n17533 );
buf ( n17535 , n5878 );
nand ( n17536 , n7709 , n17535 );
buf ( n17537 , n5879 );
buf ( n17538 , n17537 );
and ( n17539 , n17536 , n17538 );
not ( n17540 , n17536 );
not ( n17541 , n17537 );
and ( n17542 , n17540 , n17541 );
nor ( n17543 , n17539 , n17542 );
xnor ( n17544 , n17534 , n17543 );
buf ( n17545 , n17544 );
not ( n17546 , n17545 );
not ( n17547 , n17546 );
or ( n17548 , n17506 , n17547 );
not ( n17549 , n17505 );
nand ( n17550 , n17549 , n17545 );
nand ( n17551 , n17548 , n17550 );
buf ( n17552 , n5880 );
buf ( n17553 , n17552 );
not ( n17554 , n17553 );
buf ( n17555 , n5881 );
not ( n17556 , n17555 );
not ( n17557 , n17556 );
or ( n17558 , n17554 , n17557 );
not ( n17559 , n17552 );
buf ( n17560 , n17555 );
nand ( n17561 , n17559 , n17560 );
nand ( n17562 , n17558 , n17561 );
and ( n17563 , n17562 , n8890 );
not ( n17564 , n17562 );
not ( n17565 , n8889 );
and ( n17566 , n17564 , n17565 );
nor ( n17567 , n17563 , n17566 );
buf ( n17568 , n5882 );
nand ( n17569 , n8375 , n17568 );
buf ( n17570 , n5883 );
not ( n17571 , n17570 );
and ( n17572 , n17569 , n17571 );
not ( n17573 , n17569 );
buf ( n17574 , n17570 );
and ( n17575 , n17573 , n17574 );
nor ( n17576 , n17572 , n17575 );
not ( n17577 , n17576 );
xor ( n17578 , n17567 , n17577 );
buf ( n17579 , n5884 );
nand ( n17580 , n11688 , n17579 );
buf ( n17581 , n5885 );
buf ( n17582 , n17581 );
and ( n17583 , n17580 , n17582 );
not ( n17584 , n17580 );
not ( n17585 , n17581 );
and ( n17586 , n17584 , n17585 );
nor ( n17587 , n17583 , n17586 );
buf ( n17588 , n17587 );
xnor ( n17589 , n17578 , n17588 );
buf ( n17590 , n17589 );
and ( n17591 , n17551 , n17590 );
not ( n17592 , n17551 );
not ( n17593 , n17587 );
not ( n17594 , n17576 );
or ( n17595 , n17593 , n17594 );
or ( n17596 , n17587 , n17576 );
nand ( n17597 , n17595 , n17596 );
and ( n17598 , n17597 , n17567 );
not ( n17599 , n17597 );
not ( n17600 , n17567 );
and ( n17601 , n17599 , n17600 );
nor ( n17602 , n17598 , n17601 );
buf ( n17603 , n17602 );
and ( n17604 , n17592 , n17603 );
nor ( n17605 , n17591 , n17604 );
nand ( n17606 , n17504 , n17605 );
not ( n17607 , n17606 );
buf ( n17608 , n5886 );
buf ( n17609 , n17608 );
not ( n17610 , n17609 );
not ( n17611 , n11858 );
not ( n17612 , n17611 );
or ( n17613 , n17610 , n17612 );
buf ( n17614 , n11858 );
not ( n17615 , n17608 );
nand ( n17616 , n17614 , n17615 );
nand ( n17617 , n17613 , n17616 );
and ( n17618 , n17617 , n13744 );
not ( n17619 , n17617 );
and ( n17620 , n17619 , n13731 );
nor ( n17621 , n17618 , n17620 );
not ( n17622 , n17621 );
and ( n17623 , n17607 , n17622 );
and ( n17624 , n17606 , n17621 );
nor ( n17625 , n17623 , n17624 );
xor ( n17626 , n17489 , n17625 );
not ( n17627 , n17410 );
nor ( n17628 , n17627 , n17112 );
not ( n17629 , n17628 );
not ( n17630 , n17410 );
nand ( n17631 , n17630 , n17112 );
nand ( n17632 , n17629 , n17631 );
and ( n17633 , n17632 , n13643 );
not ( n17634 , n17632 );
not ( n17635 , n13643 );
and ( n17636 , n17634 , n17635 );
nor ( n17637 , n17633 , n17636 );
not ( n17638 , n17637 );
not ( n17639 , n11346 );
buf ( n17640 , n5887 );
buf ( n17641 , n17640 );
not ( n17642 , n17641 );
buf ( n17643 , n5888 );
not ( n17644 , n17643 );
not ( n17645 , n17644 );
or ( n17646 , n17642 , n17645 );
not ( n17647 , n17640 );
buf ( n17648 , n17643 );
nand ( n17649 , n17647 , n17648 );
nand ( n17650 , n17646 , n17649 );
buf ( n17651 , n5889 );
not ( n17652 , n17651 );
and ( n17653 , n17650 , n17652 );
not ( n17654 , n17650 );
buf ( n17655 , n17651 );
and ( n17656 , n17654 , n17655 );
nor ( n17657 , n17653 , n17656 );
buf ( n17658 , n5890 );
nand ( n17659 , n6502 , n17658 );
buf ( n17660 , n5891 );
xor ( n17661 , n17659 , n17660 );
xor ( n17662 , n17657 , n17661 );
buf ( n17663 , n5892 );
nand ( n17664 , n7709 , n17663 );
buf ( n17665 , n5893 );
not ( n17666 , n17665 );
and ( n17667 , n17664 , n17666 );
not ( n17668 , n17664 );
buf ( n17669 , n17665 );
and ( n17670 , n17668 , n17669 );
nor ( n17671 , n17667 , n17670 );
xnor ( n17672 , n17662 , n17671 );
not ( n17673 , n17672 );
or ( n17674 , n17639 , n17673 );
not ( n17675 , n11346 );
not ( n17676 , n17672 );
nand ( n17677 , n17675 , n17676 );
nand ( n17678 , n17674 , n17677 );
and ( n17679 , n17678 , n17333 );
not ( n17680 , n17678 );
and ( n17681 , n17680 , n17347 );
nor ( n17682 , n17679 , n17681 );
not ( n17683 , n17682 );
nand ( n17684 , n17638 , n17683 );
buf ( n17685 , n5894 );
buf ( n17686 , n17685 );
xor ( n17687 , n17686 , n12811 );
buf ( n17688 , n12833 );
xor ( n17689 , n17687 , n17688 );
not ( n17690 , n17689 );
and ( n17691 , n17684 , n17690 );
not ( n17692 , n17684 );
and ( n17693 , n17692 , n17689 );
nor ( n17694 , n17691 , n17693 );
not ( n17695 , n17694 );
not ( n17696 , n17695 );
buf ( n17697 , n5895 );
nand ( n17698 , n11847 , n17697 );
buf ( n17699 , n5896 );
not ( n17700 , n17699 );
and ( n17701 , n17698 , n17700 );
not ( n17702 , n17698 );
buf ( n17703 , n17699 );
and ( n17704 , n17702 , n17703 );
nor ( n17705 , n17701 , n17704 );
buf ( n17706 , n17705 );
not ( n17707 , n15099 );
xor ( n17708 , n17706 , n17707 );
xnor ( n17709 , n17708 , n7993 );
not ( n17710 , n8091 );
buf ( n17711 , n9266 );
nor ( n17712 , n17710 , n17711 );
not ( n17713 , n17712 );
not ( n17714 , n8067 );
xor ( n17715 , n17714 , n8089 );
xnor ( n17716 , n17715 , n8079 );
buf ( n17717 , n17716 );
not ( n17718 , n17717 );
nand ( n17719 , n17711 , n17718 );
nand ( n17720 , n17713 , n17719 );
not ( n17721 , n8140 );
and ( n17722 , n17720 , n17721 );
not ( n17723 , n17720 );
not ( n17724 , n8136 );
and ( n17725 , n17723 , n17724 );
nor ( n17726 , n17722 , n17725 );
not ( n17727 , n17726 );
nand ( n17728 , n17709 , n17727 );
not ( n17729 , n16517 );
buf ( n17730 , n5897 );
buf ( n17731 , n17730 );
not ( n17732 , n17731 );
buf ( n17733 , n5898 );
not ( n17734 , n17733 );
not ( n17735 , n17734 );
or ( n17736 , n17732 , n17735 );
not ( n17737 , n17730 );
buf ( n17738 , n17733 );
nand ( n17739 , n17737 , n17738 );
nand ( n17740 , n17736 , n17739 );
buf ( n17741 , n5899 );
buf ( n17742 , n17741 );
and ( n17743 , n17740 , n17742 );
not ( n17744 , n17740 );
not ( n17745 , n17741 );
and ( n17746 , n17744 , n17745 );
nor ( n17747 , n17743 , n17746 );
buf ( n17748 , n5900 );
nand ( n17749 , n6557 , n17748 );
buf ( n17750 , n5901 );
not ( n17751 , n17750 );
and ( n17752 , n17749 , n17751 );
not ( n17753 , n17749 );
buf ( n17754 , n17750 );
and ( n17755 , n17753 , n17754 );
nor ( n17756 , n17752 , n17755 );
xor ( n17757 , n17747 , n17756 );
buf ( n17758 , n5902 );
nand ( n17759 , n7067 , n17758 );
buf ( n17760 , n5903 );
not ( n17761 , n17760 );
and ( n17762 , n17759 , n17761 );
not ( n17763 , n17759 );
buf ( n17764 , n17760 );
and ( n17765 , n17763 , n17764 );
nor ( n17766 , n17762 , n17765 );
xnor ( n17767 , n17757 , n17766 );
not ( n17768 , n17767 );
not ( n17769 , n17768 );
not ( n17770 , n17769 );
or ( n17771 , n17729 , n17770 );
not ( n17772 , n17767 );
not ( n17773 , n17772 );
or ( n17774 , n17773 , n16517 );
nand ( n17775 , n17771 , n17774 );
not ( n17776 , n14175 );
and ( n17777 , n17775 , n17776 );
not ( n17778 , n17775 );
and ( n17779 , n17778 , n14175 );
nor ( n17780 , n17777 , n17779 );
and ( n17781 , n17728 , n17780 );
not ( n17782 , n17728 );
not ( n17783 , n17780 );
and ( n17784 , n17782 , n17783 );
nor ( n17785 , n17781 , n17784 );
not ( n17786 , n17785 );
not ( n17787 , n17786 );
or ( n17788 , n17696 , n17787 );
nand ( n17789 , n17785 , n17694 );
nand ( n17790 , n17788 , n17789 );
and ( n17791 , n17626 , n17790 );
not ( n17792 , n17626 );
not ( n17793 , n17790 );
and ( n17794 , n17792 , n17793 );
nor ( n17795 , n17791 , n17794 );
not ( n17796 , n17795 );
not ( n17797 , n17796 );
and ( n17798 , n17381 , n17797 );
not ( n17799 , n17381 );
buf ( n17800 , n17795 );
not ( n17801 , n17800 );
and ( n17802 , n17799 , n17801 );
nor ( n17803 , n17798 , n17802 );
not ( n17804 , n17803 );
nand ( n17805 , n16952 , n17804 );
or ( n17806 , n15328 , n17805 );
buf ( n17807 , n13344 );
not ( n17808 , n17807 );
buf ( n17809 , n17808 );
not ( n17810 , n17809 );
nor ( n17811 , n15323 , n17810 );
nand ( n17812 , n17811 , n17805 );
buf ( n17813 , n13353 );
nand ( n17814 , n17813 , n13573 );
nand ( n17815 , n17806 , n17812 , n17814 );
buf ( n17816 , n17815 );
buf ( n17817 , n17816 );
not ( n17818 , n12738 );
buf ( n17819 , n13352 );
buf ( n17820 , n17819 );
not ( n17821 , n17820 );
or ( n17822 , n17818 , n17821 );
buf ( n17823 , n5904 );
buf ( n17824 , n17823 );
not ( n17825 , n17824 );
buf ( n17826 , n5905 );
not ( n17827 , n17826 );
not ( n17828 , n17827 );
or ( n17829 , n17825 , n17828 );
not ( n17830 , n17823 );
buf ( n17831 , n17826 );
nand ( n17832 , n17830 , n17831 );
nand ( n17833 , n17829 , n17832 );
buf ( n17834 , n5906 );
not ( n17835 , n17834 );
and ( n17836 , n17833 , n17835 );
not ( n17837 , n17833 );
buf ( n17838 , n17834 );
and ( n17839 , n17837 , n17838 );
nor ( n17840 , n17836 , n17839 );
buf ( n17841 , n5907 );
nand ( n17842 , n7258 , n17841 );
buf ( n17843 , n5908 );
buf ( n17844 , n17843 );
and ( n17845 , n17842 , n17844 );
not ( n17846 , n17842 );
not ( n17847 , n17843 );
and ( n17848 , n17846 , n17847 );
nor ( n17849 , n17845 , n17848 );
xor ( n17850 , n17840 , n17849 );
buf ( n17851 , n5909 );
nand ( n17852 , n7569 , n17851 );
buf ( n17853 , n5910 );
not ( n17854 , n17853 );
and ( n17855 , n17852 , n17854 );
not ( n17856 , n17852 );
buf ( n17857 , n17853 );
and ( n17858 , n17856 , n17857 );
nor ( n17859 , n17855 , n17858 );
xnor ( n17860 , n17850 , n17859 );
not ( n17861 , n17860 );
not ( n17862 , n17861 );
xor ( n17863 , n14183 , n17862 );
buf ( n17864 , n5911 );
not ( n17865 , n17864 );
buf ( n17866 , n5912 );
not ( n17867 , n17866 );
buf ( n17868 , n5913 );
buf ( n17869 , n17868 );
and ( n17870 , n17867 , n17869 );
not ( n17871 , n17867 );
not ( n17872 , n17868 );
and ( n17873 , n17871 , n17872 );
nor ( n17874 , n17870 , n17873 );
xor ( n17875 , n17865 , n17874 );
buf ( n17876 , n5914 );
buf ( n17877 , n5915 );
xor ( n17878 , n17876 , n17877 );
buf ( n17879 , n5916 );
nand ( n17880 , n6828 , n17879 );
xnor ( n17881 , n17878 , n17880 );
xnor ( n17882 , n17875 , n17881 );
buf ( n17883 , n17882 );
xnor ( n17884 , n17863 , n17883 );
buf ( n17885 , n5917 );
buf ( n17886 , n17885 );
not ( n17887 , n17886 );
not ( n17888 , n12707 );
or ( n17889 , n17887 , n17888 );
not ( n17890 , n17885 );
nand ( n17891 , n12713 , n17890 );
nand ( n17892 , n17889 , n17891 );
not ( n17893 , n12756 );
and ( n17894 , n17892 , n17893 );
not ( n17895 , n17892 );
and ( n17896 , n17895 , n12756 );
nor ( n17897 , n17894 , n17896 );
nand ( n17898 , n17884 , n17897 );
not ( n17899 , n16345 );
not ( n17900 , n13445 );
or ( n17901 , n17899 , n17900 );
xor ( n17902 , n13444 , n13412 );
buf ( n17903 , n13422 );
xnor ( n17904 , n17902 , n17903 );
or ( n17905 , n16345 , n17904 );
nand ( n17906 , n17901 , n17905 );
xor ( n17907 , n13377 , n13386 );
xnor ( n17908 , n17907 , n13397 );
and ( n17909 , n17906 , n17908 );
not ( n17910 , n17906 );
and ( n17911 , n17910 , n13399 );
nor ( n17912 , n17909 , n17911 );
not ( n17913 , n17912 );
and ( n17914 , n17898 , n17913 );
not ( n17915 , n17898 );
and ( n17916 , n17915 , n17912 );
nor ( n17917 , n17914 , n17916 );
not ( n17918 , n17917 );
not ( n17919 , n11747 );
buf ( n17920 , n5918 );
buf ( n17921 , n17920 );
not ( n17922 , n17921 );
buf ( n17923 , n5919 );
not ( n17924 , n17923 );
not ( n17925 , n17924 );
or ( n17926 , n17922 , n17925 );
not ( n17927 , n17920 );
buf ( n17928 , n17923 );
nand ( n17929 , n17927 , n17928 );
nand ( n17930 , n17926 , n17929 );
buf ( n17931 , n5920 );
not ( n17932 , n17931 );
and ( n17933 , n17930 , n17932 );
not ( n17934 , n17930 );
buf ( n17935 , n17931 );
and ( n17936 , n17934 , n17935 );
nor ( n17937 , n17933 , n17936 );
buf ( n17938 , n5921 );
nand ( n17939 , n6828 , n17938 );
buf ( n17940 , n5922 );
buf ( n17941 , n17940 );
and ( n17942 , n17939 , n17941 );
not ( n17943 , n17939 );
not ( n17944 , n17940 );
and ( n17945 , n17943 , n17944 );
nor ( n17946 , n17942 , n17945 );
xor ( n17947 , n17937 , n17946 );
buf ( n17948 , n5923 );
nand ( n17949 , n8675 , n17948 );
buf ( n17950 , n5924 );
not ( n17951 , n17950 );
and ( n17952 , n17949 , n17951 );
not ( n17953 , n17949 );
buf ( n17954 , n17950 );
and ( n17955 , n17953 , n17954 );
nor ( n17956 , n17952 , n17955 );
xnor ( n17957 , n17947 , n17956 );
not ( n17958 , n17957 );
not ( n17959 , n17958 );
not ( n17960 , n17959 );
or ( n17961 , n17919 , n17960 );
not ( n17962 , n11747 );
nand ( n17963 , n17962 , n17958 );
nand ( n17964 , n17961 , n17963 );
buf ( n17965 , n5925 );
buf ( n17966 , n17965 );
not ( n17967 , n17966 );
buf ( n17968 , n5926 );
not ( n17969 , n17968 );
not ( n17970 , n17969 );
or ( n17971 , n17967 , n17970 );
not ( n17972 , n17965 );
buf ( n17973 , n17968 );
nand ( n17974 , n17972 , n17973 );
nand ( n17975 , n17971 , n17974 );
buf ( n17976 , n5927 );
buf ( n17977 , n17976 );
and ( n17978 , n17975 , n17977 );
not ( n17979 , n17975 );
not ( n17980 , n17976 );
and ( n17981 , n17979 , n17980 );
nor ( n17982 , n17978 , n17981 );
buf ( n17983 , n5928 );
nand ( n17984 , n6502 , n17983 );
buf ( n17985 , n5929 );
not ( n17986 , n17985 );
and ( n17987 , n17984 , n17986 );
not ( n17988 , n17984 );
buf ( n17989 , n17985 );
and ( n17990 , n17988 , n17989 );
nor ( n17991 , n17987 , n17990 );
xor ( n17992 , n17982 , n17991 );
buf ( n17993 , n5930 );
nand ( n17994 , n6828 , n17993 );
buf ( n17995 , n5931 );
not ( n17996 , n17995 );
and ( n17997 , n17994 , n17996 );
not ( n17998 , n17994 );
buf ( n17999 , n17995 );
and ( n18000 , n17998 , n17999 );
nor ( n18001 , n17997 , n18000 );
xnor ( n18002 , n17992 , n18001 );
buf ( n18003 , n18002 );
not ( n18004 , n18003 );
and ( n18005 , n17964 , n18004 );
not ( n18006 , n17964 );
and ( n18007 , n18006 , n18003 );
nor ( n18008 , n18005 , n18007 );
not ( n18009 , n18008 );
not ( n18010 , n16036 );
not ( n18011 , n14174 );
or ( n18012 , n18010 , n18011 );
or ( n18013 , n14174 , n16036 );
nand ( n18014 , n18012 , n18013 );
not ( n18015 , n14151 );
and ( n18016 , n18014 , n18015 );
not ( n18017 , n18014 );
and ( n18018 , n18017 , n14152 );
nor ( n18019 , n18016 , n18018 );
not ( n18020 , n8722 );
not ( n18021 , n18020 );
buf ( n18022 , n5932 );
buf ( n18023 , n18022 );
not ( n18024 , n18023 );
and ( n18025 , n18021 , n18024 );
and ( n18026 , n18020 , n18023 );
nor ( n18027 , n18025 , n18026 );
not ( n18028 , n12010 );
and ( n18029 , n18027 , n18028 );
not ( n18030 , n18027 );
and ( n18031 , n18030 , n12011 );
nor ( n18032 , n18029 , n18031 );
nand ( n18033 , n18019 , n18032 );
not ( n18034 , n18033 );
or ( n18035 , n18009 , n18034 );
or ( n18036 , n18033 , n18008 );
nand ( n18037 , n18035 , n18036 );
not ( n18038 , n18037 );
not ( n18039 , n8760 );
not ( n18040 , n18039 );
buf ( n18041 , n5933 );
buf ( n18042 , n18041 );
not ( n18043 , n18042 );
buf ( n18044 , n5934 );
buf ( n18045 , n18044 );
not ( n18046 , n18045 );
buf ( n18047 , n5935 );
not ( n18048 , n18047 );
not ( n18049 , n18048 );
or ( n18050 , n18046 , n18049 );
not ( n18051 , n18044 );
buf ( n18052 , n18047 );
nand ( n18053 , n18051 , n18052 );
nand ( n18054 , n18050 , n18053 );
buf ( n18055 , n5936 );
buf ( n18056 , n18055 );
and ( n18057 , n18054 , n18056 );
not ( n18058 , n18054 );
not ( n18059 , n18055 );
and ( n18060 , n18058 , n18059 );
nor ( n18061 , n18057 , n18060 );
buf ( n18062 , n5937 );
nand ( n18063 , n8323 , n18062 );
buf ( n18064 , n5938 );
buf ( n18065 , n18064 );
and ( n18066 , n18063 , n18065 );
not ( n18067 , n18063 );
not ( n18068 , n18064 );
and ( n18069 , n18067 , n18068 );
nor ( n18070 , n18066 , n18069 );
xor ( n18071 , n18061 , n18070 );
buf ( n18072 , n5939 );
nand ( n18073 , n8675 , n18072 );
buf ( n18074 , n5940 );
buf ( n18075 , n18074 );
and ( n18076 , n18073 , n18075 );
not ( n18077 , n18073 );
not ( n18078 , n18074 );
and ( n18079 , n18077 , n18078 );
nor ( n18080 , n18076 , n18079 );
xnor ( n18081 , n18071 , n18080 );
buf ( n18082 , n18081 );
not ( n18083 , n18082 );
or ( n18084 , n18043 , n18083 );
or ( n18085 , n18082 , n18042 );
nand ( n18086 , n18084 , n18085 );
not ( n18087 , n18086 );
and ( n18088 , n18040 , n18087 );
and ( n18089 , n18039 , n18086 );
nor ( n18090 , n18088 , n18089 );
buf ( n18091 , n5941 );
buf ( n18092 , n18091 );
not ( n18093 , n18092 );
buf ( n18094 , n5942 );
not ( n18095 , n18094 );
not ( n18096 , n18095 );
or ( n18097 , n18093 , n18096 );
not ( n18098 , n18091 );
buf ( n18099 , n18094 );
nand ( n18100 , n18098 , n18099 );
nand ( n18101 , n18097 , n18100 );
xor ( n18102 , n9515 , n18101 );
buf ( n18103 , n5943 );
buf ( n18104 , n5944 );
not ( n18105 , n18104 );
xor ( n18106 , n18103 , n18105 );
buf ( n18107 , n5945 );
nand ( n18108 , n8375 , n18107 );
xnor ( n18109 , n18106 , n18108 );
xnor ( n18110 , n18102 , n18109 );
not ( n18111 , n18110 );
buf ( n18112 , n18111 );
not ( n18113 , n18112 );
buf ( n18114 , n5946 );
buf ( n18115 , n18114 );
not ( n18116 , n18115 );
buf ( n18117 , n5947 );
buf ( n18118 , n18117 );
not ( n18119 , n18118 );
buf ( n18120 , n5948 );
not ( n18121 , n18120 );
not ( n18122 , n18121 );
or ( n18123 , n18119 , n18122 );
not ( n18124 , n18117 );
buf ( n18125 , n18120 );
nand ( n18126 , n18124 , n18125 );
nand ( n18127 , n18123 , n18126 );
buf ( n18128 , n5949 );
buf ( n18129 , n18128 );
and ( n18130 , n18127 , n18129 );
not ( n18131 , n18127 );
not ( n18132 , n18128 );
and ( n18133 , n18131 , n18132 );
nor ( n18134 , n18130 , n18133 );
buf ( n18135 , n5950 );
nand ( n18136 , n6815 , n18135 );
buf ( n18137 , n5951 );
not ( n18138 , n18137 );
and ( n18139 , n18136 , n18138 );
not ( n18140 , n18136 );
buf ( n18141 , n18137 );
and ( n18142 , n18140 , n18141 );
nor ( n18143 , n18139 , n18142 );
xor ( n18144 , n18134 , n18143 );
buf ( n18145 , n5952 );
nand ( n18146 , n7014 , n18145 );
buf ( n18147 , n5953 );
buf ( n18148 , n18147 );
and ( n18149 , n18146 , n18148 );
not ( n18150 , n18146 );
not ( n18151 , n18147 );
and ( n18152 , n18150 , n18151 );
nor ( n18153 , n18149 , n18152 );
xor ( n18154 , n18144 , n18153 );
not ( n18155 , n18154 );
or ( n18156 , n18116 , n18155 );
or ( n18157 , n18154 , n18115 );
nand ( n18158 , n18156 , n18157 );
not ( n18159 , n18158 );
and ( n18160 , n18113 , n18159 );
and ( n18161 , n18112 , n18158 );
nor ( n18162 , n18160 , n18161 );
not ( n18163 , n18162 );
nand ( n18164 , n18090 , n18163 );
not ( n18165 , n18164 );
buf ( n18166 , n8046 );
not ( n18167 , n18166 );
buf ( n18168 , n15947 );
not ( n18169 , n18168 );
buf ( n18170 , n5954 );
buf ( n18171 , n18170 );
not ( n18172 , n18171 );
buf ( n18173 , n5955 );
not ( n18174 , n18173 );
not ( n18175 , n18174 );
or ( n18176 , n18172 , n18175 );
not ( n18177 , n18170 );
buf ( n18178 , n18173 );
nand ( n18179 , n18177 , n18178 );
nand ( n18180 , n18176 , n18179 );
buf ( n18181 , n5956 );
buf ( n18182 , n18181 );
and ( n18183 , n18180 , n18182 );
not ( n18184 , n18180 );
not ( n18185 , n18181 );
and ( n18186 , n18184 , n18185 );
nor ( n18187 , n18183 , n18186 );
buf ( n18188 , n5957 );
nand ( n18189 , n11946 , n18188 );
buf ( n18190 , n5958 );
buf ( n18191 , n18190 );
and ( n18192 , n18189 , n18191 );
not ( n18193 , n18189 );
not ( n18194 , n18190 );
and ( n18195 , n18193 , n18194 );
nor ( n18196 , n18192 , n18195 );
xor ( n18197 , n18187 , n18196 );
buf ( n18198 , n5959 );
nand ( n18199 , n7107 , n18198 );
buf ( n18200 , n5960 );
buf ( n18201 , n18200 );
and ( n18202 , n18199 , n18201 );
not ( n18203 , n18199 );
not ( n18204 , n18200 );
and ( n18205 , n18203 , n18204 );
nor ( n18206 , n18202 , n18205 );
xor ( n18207 , n18197 , n18206 );
not ( n18208 , n18207 );
not ( n18209 , n18208 );
or ( n18210 , n18169 , n18209 );
not ( n18211 , n18168 );
xor ( n18212 , n18187 , n18206 );
not ( n18213 , n18196 );
xnor ( n18214 , n18212 , n18213 );
nand ( n18215 , n18211 , n18214 );
nand ( n18216 , n18210 , n18215 );
not ( n18217 , n18216 );
or ( n18218 , n18167 , n18217 );
or ( n18219 , n18216 , n18166 );
nand ( n18220 , n18218 , n18219 );
not ( n18221 , n18220 );
and ( n18222 , n18165 , n18221 );
and ( n18223 , n18164 , n18220 );
nor ( n18224 , n18222 , n18223 );
not ( n18225 , n18224 );
or ( n18226 , n18038 , n18225 );
or ( n18227 , n18037 , n18224 );
nand ( n18228 , n18226 , n18227 );
not ( n18229 , n17884 );
nand ( n18230 , n18229 , n17913 );
not ( n18231 , n18230 );
not ( n18232 , n7365 );
not ( n18233 , n17233 );
or ( n18234 , n18232 , n18233 );
xor ( n18235 , n17212 , n17231 );
not ( n18236 , n17221 );
xnor ( n18237 , n18235 , n18236 );
nand ( n18238 , n18237 , n7364 );
nand ( n18239 , n18234 , n18238 );
not ( n18240 , n18239 );
buf ( n18241 , n5961 );
buf ( n18242 , n5962 );
buf ( n18243 , n18242 );
not ( n18244 , n18243 );
buf ( n18245 , n5963 );
not ( n18246 , n18245 );
not ( n18247 , n18246 );
or ( n18248 , n18244 , n18247 );
not ( n18249 , n18242 );
buf ( n18250 , n18245 );
nand ( n18251 , n18249 , n18250 );
nand ( n18252 , n18248 , n18251 );
xor ( n18253 , n18241 , n18252 );
buf ( n18254 , n5964 );
buf ( n18255 , n5965 );
xor ( n18256 , n18254 , n18255 );
buf ( n18257 , n5966 );
nand ( n18258 , n8455 , n18257 );
xnor ( n18259 , n18256 , n18258 );
xnor ( n18260 , n18253 , n18259 );
buf ( n18261 , n18260 );
not ( n18262 , n18261 );
and ( n18263 , n18240 , n18262 );
and ( n18264 , n18239 , n18261 );
nor ( n18265 , n18263 , n18264 );
not ( n18266 , n18265 );
not ( n18267 , n18266 );
and ( n18268 , n18231 , n18267 );
and ( n18269 , n18230 , n18266 );
nor ( n18270 , n18268 , n18269 );
not ( n18271 , n18270 );
and ( n18272 , n18228 , n18271 );
not ( n18273 , n18228 );
and ( n18274 , n18273 , n18270 );
nor ( n18275 , n18272 , n18274 );
not ( n18276 , n18275 );
not ( n18277 , n18276 );
not ( n18278 , n11128 );
not ( n18279 , n9788 );
or ( n18280 , n18278 , n18279 );
or ( n18281 , n9788 , n11128 );
nand ( n18282 , n18280 , n18281 );
not ( n18283 , n18282 );
not ( n18284 , n9839 );
or ( n18285 , n18283 , n18284 );
not ( n18286 , n9840 );
or ( n18287 , n18286 , n18282 );
nand ( n18288 , n18285 , n18287 );
not ( n18289 , n18288 );
buf ( n18290 , n5967 );
not ( n18291 , n18290 );
not ( n18292 , n8483 );
xor ( n18293 , n18292 , n8502 );
not ( n18294 , n8492 );
xnor ( n18295 , n18293 , n18294 );
not ( n18296 , n18295 );
not ( n18297 , n18296 );
not ( n18298 , n18297 );
or ( n18299 , n18291 , n18298 );
not ( n18300 , n18296 );
or ( n18301 , n18300 , n18290 );
nand ( n18302 , n18299 , n18301 );
and ( n18303 , n18302 , n8548 );
not ( n18304 , n18302 );
and ( n18305 , n18304 , n8549 );
nor ( n18306 , n18303 , n18305 );
not ( n18307 , n18306 );
nand ( n18308 , n18289 , n18307 );
not ( n18309 , n18308 );
xor ( n18310 , n12931 , n14052 );
buf ( n18311 , n5968 );
buf ( n18312 , n5969 );
not ( n18313 , n18312 );
buf ( n18314 , n5970 );
buf ( n18315 , n18314 );
and ( n18316 , n18313 , n18315 );
not ( n18317 , n18313 );
not ( n18318 , n18314 );
and ( n18319 , n18317 , n18318 );
nor ( n18320 , n18316 , n18319 );
xor ( n18321 , n18311 , n18320 );
buf ( n18322 , n5971 );
xor ( n18323 , n18322 , n10872 );
xnor ( n18324 , n18323 , n10876 );
xnor ( n18325 , n18321 , n18324 );
buf ( n18326 , n18325 );
xnor ( n18327 , n18310 , n18326 );
not ( n18328 , n18327 );
and ( n18329 , n18309 , n18328 );
and ( n18330 , n18308 , n18327 );
nor ( n18331 , n18329 , n18330 );
not ( n18332 , n18331 );
xor ( n18333 , n9579 , n10398 );
xnor ( n18334 , n18333 , n10679 );
buf ( n18335 , n5972 );
buf ( n18336 , n18335 );
not ( n18337 , n18336 );
buf ( n18338 , n5973 );
not ( n18339 , n18338 );
not ( n18340 , n18339 );
or ( n18341 , n18337 , n18340 );
not ( n18342 , n18335 );
buf ( n18343 , n18338 );
nand ( n18344 , n18342 , n18343 );
nand ( n18345 , n18341 , n18344 );
buf ( n18346 , n5974 );
buf ( n18347 , n18346 );
and ( n18348 , n18345 , n18347 );
not ( n18349 , n18345 );
not ( n18350 , n18346 );
and ( n18351 , n18349 , n18350 );
nor ( n18352 , n18348 , n18351 );
buf ( n18353 , n5975 );
nand ( n18354 , n7355 , n18353 );
buf ( n18355 , n5976 );
buf ( n18356 , n18355 );
and ( n18357 , n18354 , n18356 );
not ( n18358 , n18354 );
not ( n18359 , n18355 );
and ( n18360 , n18358 , n18359 );
nor ( n18361 , n18357 , n18360 );
xor ( n18362 , n18352 , n18361 );
buf ( n18363 , n5977 );
nand ( n18364 , n6647 , n18363 );
buf ( n18365 , n5978 );
not ( n18366 , n18365 );
and ( n18367 , n18364 , n18366 );
not ( n18368 , n18364 );
buf ( n18369 , n18365 );
and ( n18370 , n18368 , n18369 );
nor ( n18371 , n18367 , n18370 );
xnor ( n18372 , n18362 , n18371 );
and ( n18373 , n17055 , n18372 );
not ( n18374 , n17055 );
not ( n18375 , n18371 );
xor ( n18376 , n18352 , n18375 );
buf ( n18377 , n18361 );
xor ( n18378 , n18376 , n18377 );
not ( n18379 , n18378 );
and ( n18380 , n18374 , n18379 );
or ( n18381 , n18373 , n18380 );
not ( n18382 , n18381 );
not ( n18383 , n10271 );
or ( n18384 , n18382 , n18383 );
or ( n18385 , n10271 , n18381 );
nand ( n18386 , n18384 , n18385 );
buf ( n18387 , n18386 );
not ( n18388 , n18387 );
nand ( n18389 , n18334 , n18388 );
buf ( n18390 , n5979 );
nand ( n18391 , n8675 , n18390 );
buf ( n18392 , n5980 );
not ( n18393 , n18392 );
and ( n18394 , n18391 , n18393 );
not ( n18395 , n18391 );
buf ( n18396 , n18392 );
and ( n18397 , n18395 , n18396 );
nor ( n18398 , n18394 , n18397 );
buf ( n18399 , n18398 );
not ( n18400 , n18399 );
not ( n18401 , n17139 );
or ( n18402 , n18400 , n18401 );
not ( n18403 , n18399 );
nand ( n18404 , n18403 , n9898 );
nand ( n18405 , n18402 , n18404 );
and ( n18406 , n18405 , n9942 );
not ( n18407 , n18405 );
and ( n18408 , n18407 , n17146 );
nor ( n18409 , n18406 , n18408 );
and ( n18410 , n18389 , n18409 );
not ( n18411 , n18389 );
not ( n18412 , n18409 );
and ( n18413 , n18411 , n18412 );
nor ( n18414 , n18410 , n18413 );
not ( n18415 , n18414 );
or ( n18416 , n18332 , n18415 );
not ( n18417 , n18414 );
not ( n18418 , n18331 );
nand ( n18419 , n18417 , n18418 );
nand ( n18420 , n18416 , n18419 );
not ( n18421 , n18420 );
and ( n18422 , n18277 , n18421 );
and ( n18423 , n18276 , n18420 );
nor ( n18424 , n18422 , n18423 );
not ( n18425 , n18424 );
or ( n18426 , n17918 , n18425 );
not ( n18427 , n17917 );
not ( n18428 , n18275 );
not ( n18429 , n18420 );
not ( n18430 , n18429 );
or ( n18431 , n18428 , n18430 );
nand ( n18432 , n18276 , n18420 );
nand ( n18433 , n18431 , n18432 );
nand ( n18434 , n18427 , n18433 );
nand ( n18435 , n18426 , n18434 );
not ( n18436 , n16057 );
and ( n18437 , n15808 , n18436 );
not ( n18438 , n15808 );
and ( n18439 , n18438 , n16057 );
nor ( n18440 , n18437 , n18439 );
not ( n18441 , n18440 );
and ( n18442 , n16100 , n18441 );
not ( n18443 , n16100 );
and ( n18444 , n18443 , n18440 );
nor ( n18445 , n18442 , n18444 );
buf ( n18446 , n5981 );
nand ( n18447 , n6927 , n18446 );
buf ( n18448 , n5982 );
buf ( n18449 , n18448 );
and ( n18450 , n18447 , n18449 );
not ( n18451 , n18447 );
not ( n18452 , n18448 );
and ( n18453 , n18451 , n18452 );
nor ( n18454 , n18450 , n18453 );
buf ( n18455 , n18454 );
not ( n18456 , n18455 );
not ( n18457 , n15689 );
or ( n18458 , n18456 , n18457 );
xor ( n18459 , n15664 , n15683 );
not ( n18460 , n15673 );
xnor ( n18461 , n18459 , n18460 );
not ( n18462 , n18461 );
or ( n18463 , n18462 , n18455 );
nand ( n18464 , n18458 , n18463 );
buf ( n18465 , n12498 );
and ( n18466 , n18464 , n18465 );
not ( n18467 , n18464 );
and ( n18468 , n18467 , n15692 );
nor ( n18469 , n18466 , n18468 );
not ( n18470 , n18469 );
nand ( n18471 , n18445 , n18470 );
not ( n18472 , n18471 );
buf ( n18473 , n5983 );
buf ( n18474 , n18473 );
buf ( n18475 , n18082 );
xor ( n18476 , n18474 , n18475 );
xnor ( n18477 , n18476 , n7665 );
not ( n18478 , n18477 );
or ( n18479 , n18472 , n18478 );
or ( n18480 , n18477 , n18471 );
nand ( n18481 , n18479 , n18480 );
not ( n18482 , n18481 );
not ( n18483 , n18482 );
not ( n18484 , n12540 );
not ( n18485 , n10126 );
or ( n18486 , n18484 , n18485 );
not ( n18487 , n12540 );
nand ( n18488 , n18487 , n10491 );
nand ( n18489 , n18486 , n18488 );
buf ( n18490 , n5984 );
buf ( n18491 , n18490 );
not ( n18492 , n18491 );
not ( n18493 , n12663 );
not ( n18494 , n18493 );
or ( n18495 , n18492 , n18494 );
not ( n18496 , n18490 );
nand ( n18497 , n18496 , n12664 );
nand ( n18498 , n18495 , n18497 );
not ( n18499 , n18498 );
buf ( n18500 , n5985 );
nand ( n18501 , n7606 , n18500 );
buf ( n18502 , n5986 );
buf ( n18503 , n18502 );
and ( n18504 , n18501 , n18503 );
not ( n18505 , n18501 );
not ( n18506 , n18502 );
and ( n18507 , n18505 , n18506 );
nor ( n18508 , n18504 , n18507 );
xor ( n18509 , n17886 , n18508 );
buf ( n18510 , n5987 );
nand ( n18511 , n7709 , n18510 );
buf ( n18512 , n5988 );
not ( n18513 , n18512 );
and ( n18514 , n18511 , n18513 );
not ( n18515 , n18511 );
buf ( n18516 , n18512 );
and ( n18517 , n18515 , n18516 );
nor ( n18518 , n18514 , n18517 );
xnor ( n18519 , n18509 , n18518 );
not ( n18520 , n18519 );
not ( n18521 , n18520 );
or ( n18522 , n18499 , n18521 );
not ( n18523 , n18498 );
nand ( n18524 , n18523 , n18519 );
nand ( n18525 , n18522 , n18524 );
and ( n18526 , n18489 , n18525 );
not ( n18527 , n18489 );
not ( n18528 , n18525 );
and ( n18529 , n18527 , n18528 );
nor ( n18530 , n18526 , n18529 );
buf ( n18531 , n5989 );
buf ( n18532 , n18531 );
not ( n18533 , n18532 );
buf ( n18534 , n5990 );
not ( n18535 , n18534 );
not ( n18536 , n18535 );
or ( n18537 , n18533 , n18536 );
not ( n18538 , n18531 );
buf ( n18539 , n18534 );
nand ( n18540 , n18538 , n18539 );
nand ( n18541 , n18537 , n18540 );
buf ( n18542 , n5991 );
not ( n18543 , n18542 );
and ( n18544 , n18541 , n18543 );
not ( n18545 , n18541 );
buf ( n18546 , n18542 );
and ( n18547 , n18545 , n18546 );
nor ( n18548 , n18544 , n18547 );
xor ( n18549 , n18548 , n6586 );
buf ( n18550 , n5992 );
nand ( n18551 , n7247 , n18550 );
buf ( n18552 , n5993 );
not ( n18553 , n18552 );
and ( n18554 , n18551 , n18553 );
not ( n18555 , n18551 );
buf ( n18556 , n18552 );
and ( n18557 , n18555 , n18556 );
nor ( n18558 , n18554 , n18557 );
xor ( n18559 , n18549 , n18558 );
not ( n18560 , n18559 );
not ( n18561 , n18560 );
buf ( n18562 , n5994 );
not ( n18563 , n18562 );
not ( n18564 , n8233 );
not ( n18565 , n18564 );
or ( n18566 , n18563 , n18565 );
not ( n18567 , n8233 );
or ( n18568 , n18567 , n18562 );
nand ( n18569 , n18566 , n18568 );
not ( n18570 , n18569 );
or ( n18571 , n18561 , n18570 );
buf ( n18572 , n18559 );
not ( n18573 , n18572 );
or ( n18574 , n18569 , n18573 );
nand ( n18575 , n18571 , n18574 );
not ( n18576 , n18575 );
nand ( n18577 , n18530 , n18576 );
not ( n18578 , n18577 );
not ( n18579 , n13935 );
not ( n18580 , n9476 );
not ( n18581 , n13984 );
or ( n18582 , n18580 , n18581 );
not ( n18583 , n9476 );
nand ( n18584 , n18583 , n13991 );
nand ( n18585 , n18582 , n18584 );
xor ( n18586 , n18579 , n18585 );
buf ( n18587 , n18586 );
not ( n18588 , n18587 );
and ( n18589 , n18578 , n18588 );
and ( n18590 , n18577 , n18587 );
nor ( n18591 , n18589 , n18590 );
not ( n18592 , n18591 );
not ( n18593 , n18592 );
or ( n18594 , n18483 , n18593 );
nand ( n18595 , n18591 , n18481 );
nand ( n18596 , n18594 , n18595 );
not ( n18597 , n18596 );
buf ( n18598 , n5995 );
buf ( n18599 , n18598 );
not ( n18600 , n18599 );
not ( n18601 , n11501 );
or ( n18602 , n18600 , n18601 );
or ( n18603 , n11501 , n18599 );
nand ( n18604 , n18602 , n18603 );
and ( n18605 , n18604 , n15361 );
not ( n18606 , n18604 );
not ( n18607 , n15340 );
not ( n18608 , n15356 );
or ( n18609 , n18607 , n18608 );
or ( n18610 , n15356 , n15340 );
nand ( n18611 , n18609 , n18610 );
not ( n18612 , n18611 );
and ( n18613 , n18606 , n18612 );
or ( n18614 , n18605 , n18613 );
not ( n18615 , n9374 );
buf ( n18616 , n12830 );
xor ( n18617 , n18616 , n12827 );
not ( n18618 , n18617 );
not ( n18619 , n9321 );
or ( n18620 , n18618 , n18619 );
or ( n18621 , n9321 , n18617 );
nand ( n18622 , n18620 , n18621 );
not ( n18623 , n18622 );
or ( n18624 , n18615 , n18623 );
or ( n18625 , n18622 , n9374 );
nand ( n18626 , n18624 , n18625 );
nand ( n18627 , n18614 , n18626 );
not ( n18628 , n11310 );
not ( n18629 , n17672 );
or ( n18630 , n18628 , n18629 );
not ( n18631 , n17672 );
not ( n18632 , n18631 );
or ( n18633 , n18632 , n11310 );
nand ( n18634 , n18630 , n18633 );
not ( n18635 , n18634 );
not ( n18636 , n17333 );
and ( n18637 , n18635 , n18636 );
and ( n18638 , n18634 , n17333 );
nor ( n18639 , n18637 , n18638 );
and ( n18640 , n18627 , n18639 );
not ( n18641 , n18627 );
not ( n18642 , n18639 );
and ( n18643 , n18641 , n18642 );
nor ( n18644 , n18640 , n18643 );
not ( n18645 , n18644 );
buf ( n18646 , n6767 );
not ( n18647 , n18646 );
not ( n18648 , n12594 );
or ( n18649 , n18647 , n18648 );
not ( n18650 , n12591 );
or ( n18651 , n18650 , n18646 );
nand ( n18652 , n18649 , n18651 );
and ( n18653 , n18652 , n12636 );
not ( n18654 , n18652 );
not ( n18655 , n12636 );
and ( n18656 , n18654 , n18655 );
nor ( n18657 , n18653 , n18656 );
buf ( n18658 , n11003 );
not ( n18659 , n18658 );
not ( n18660 , n9694 );
or ( n18661 , n18659 , n18660 );
or ( n18662 , n9694 , n18658 );
nand ( n18663 , n18661 , n18662 );
buf ( n18664 , n6475 );
xor ( n18665 , n18664 , n9712 );
not ( n18666 , n9729 );
xnor ( n18667 , n18665 , n18666 );
buf ( n18668 , n18667 );
and ( n18669 , n18663 , n18668 );
not ( n18670 , n18663 );
and ( n18671 , n18670 , n9731 );
nor ( n18672 , n18669 , n18671 );
nand ( n18673 , n18657 , n18672 );
not ( n18674 , n18673 );
not ( n18675 , n10787 );
buf ( n18676 , n5996 );
buf ( n18677 , n18676 );
not ( n18678 , n18677 );
buf ( n18679 , n5997 );
not ( n18680 , n18679 );
not ( n18681 , n18680 );
or ( n18682 , n18678 , n18681 );
not ( n18683 , n18676 );
buf ( n18684 , n18679 );
nand ( n18685 , n18683 , n18684 );
nand ( n18686 , n18682 , n18685 );
buf ( n18687 , n5998 );
buf ( n18688 , n18687 );
and ( n18689 , n18686 , n18688 );
not ( n18690 , n18686 );
not ( n18691 , n18687 );
and ( n18692 , n18690 , n18691 );
nor ( n18693 , n18689 , n18692 );
buf ( n18694 , n5999 );
nand ( n18695 , n7355 , n18694 );
buf ( n18696 , n6000 );
buf ( n18697 , n18696 );
and ( n18698 , n18695 , n18697 );
not ( n18699 , n18695 );
not ( n18700 , n18696 );
and ( n18701 , n18699 , n18700 );
nor ( n18702 , n18698 , n18701 );
not ( n18703 , n18702 );
xor ( n18704 , n18693 , n18703 );
xnor ( n18705 , n18704 , n17705 );
not ( n18706 , n18705 );
or ( n18707 , n18675 , n18706 );
not ( n18708 , n10787 );
xor ( n18709 , n18693 , n18702 );
xnor ( n18710 , n18709 , n17705 );
nand ( n18711 , n18708 , n18710 );
nand ( n18712 , n18707 , n18711 );
not ( n18713 , n13294 );
not ( n18714 , n18713 );
and ( n18715 , n18712 , n18714 );
not ( n18716 , n18712 );
and ( n18717 , n18716 , n12342 );
nor ( n18718 , n18715 , n18717 );
not ( n18719 , n18718 );
not ( n18720 , n18719 );
not ( n18721 , n18720 );
and ( n18722 , n18674 , n18721 );
and ( n18723 , n18673 , n18720 );
nor ( n18724 , n18722 , n18723 );
not ( n18725 , n18724 );
and ( n18726 , n18645 , n18725 );
and ( n18727 , n18644 , n18724 );
nor ( n18728 , n18726 , n18727 );
xor ( n18729 , n8595 , n7025 );
buf ( n18730 , n6982 );
xnor ( n18731 , n18729 , n18730 );
not ( n18732 , n18731 );
not ( n18733 , n12713 );
buf ( n18734 , n18508 );
not ( n18735 , n18734 );
and ( n18736 , n18733 , n18735 );
and ( n18737 , n12713 , n18734 );
nor ( n18738 , n18736 , n18737 );
and ( n18739 , n18738 , n12755 );
not ( n18740 , n18738 );
and ( n18741 , n18740 , n17893 );
nor ( n18742 , n18739 , n18741 );
nand ( n18743 , n18732 , n18742 );
not ( n18744 , n7818 );
not ( n18745 , n17590 );
or ( n18746 , n18744 , n18745 );
nand ( n18747 , n17603 , n7814 );
nand ( n18748 , n18746 , n18747 );
and ( n18749 , n18748 , n10695 );
not ( n18750 , n18748 );
not ( n18751 , n10695 );
and ( n18752 , n18750 , n18751 );
nor ( n18753 , n18749 , n18752 );
buf ( n18754 , n18753 );
not ( n18755 , n18754 );
and ( n18756 , n18743 , n18755 );
not ( n18757 , n18743 );
and ( n18758 , n18757 , n18754 );
nor ( n18759 , n18756 , n18758 );
not ( n18760 , n18759 );
and ( n18761 , n18728 , n18760 );
not ( n18762 , n18728 );
and ( n18763 , n18762 , n18759 );
nor ( n18764 , n18761 , n18763 );
not ( n18765 , n18764 );
not ( n18766 , n18765 );
or ( n18767 , n18597 , n18766 );
not ( n18768 , n18596 );
nand ( n18769 , n18764 , n18768 );
nand ( n18770 , n18767 , n18769 );
buf ( n18771 , n18770 );
not ( n18772 , n18771 );
and ( n18773 , n18435 , n18772 );
not ( n18774 , n18435 );
and ( n18775 , n18774 , n18771 );
nor ( n18776 , n18773 , n18775 );
not ( n18777 , n18776 );
buf ( n18778 , n6001 );
nand ( n18779 , n11847 , n18778 );
buf ( n18780 , n6002 );
not ( n18781 , n18780 );
and ( n18782 , n18779 , n18781 );
not ( n18783 , n18779 );
buf ( n18784 , n18780 );
and ( n18785 , n18783 , n18784 );
nor ( n18786 , n18782 , n18785 );
xor ( n18787 , n18786 , n16149 );
xnor ( n18788 , n18787 , n11775 );
not ( n18789 , n18788 );
not ( n18790 , n18789 );
buf ( n18791 , n6003 );
buf ( n18792 , n18791 );
not ( n18793 , n18792 );
not ( n18794 , n7086 );
not ( n18795 , n18794 );
or ( n18796 , n18793 , n18795 );
not ( n18797 , n18791 );
nand ( n18798 , n18797 , n7087 );
nand ( n18799 , n18796 , n18798 );
buf ( n18800 , n6004 );
buf ( n18801 , n18800 );
and ( n18802 , n18799 , n18801 );
not ( n18803 , n18799 );
not ( n18804 , n18800 );
and ( n18805 , n18803 , n18804 );
nor ( n18806 , n18802 , n18805 );
buf ( n18807 , n6005 );
nand ( n18808 , n6927 , n18807 );
buf ( n18809 , n6006 );
xor ( n18810 , n18808 , n18809 );
xor ( n18811 , n18806 , n18810 );
buf ( n18812 , n6007 );
nand ( n18813 , n8260 , n18812 );
buf ( n18814 , n6008 );
buf ( n18815 , n18814 );
and ( n18816 , n18813 , n18815 );
not ( n18817 , n18813 );
not ( n18818 , n18814 );
and ( n18819 , n18817 , n18818 );
nor ( n18820 , n18816 , n18819 );
xnor ( n18821 , n18811 , n18820 );
buf ( n18822 , n18821 );
buf ( n18823 , n18822 );
not ( n18824 , n18823 );
buf ( n18825 , n6009 );
buf ( n18826 , n18825 );
not ( n18827 , n18826 );
buf ( n18828 , n6010 );
not ( n18829 , n18828 );
not ( n18830 , n18829 );
or ( n18831 , n18827 , n18830 );
not ( n18832 , n18825 );
buf ( n18833 , n18828 );
nand ( n18834 , n18832 , n18833 );
nand ( n18835 , n18831 , n18834 );
buf ( n18836 , n6011 );
buf ( n18837 , n18836 );
and ( n18838 , n18835 , n18837 );
not ( n18839 , n18835 );
not ( n18840 , n18836 );
and ( n18841 , n18839 , n18840 );
nor ( n18842 , n18838 , n18841 );
buf ( n18843 , n6012 );
nand ( n18844 , n6577 , n18843 );
buf ( n18845 , n6013 );
not ( n18846 , n18845 );
and ( n18847 , n18844 , n18846 );
not ( n18848 , n18844 );
buf ( n18849 , n18845 );
and ( n18850 , n18848 , n18849 );
nor ( n18851 , n18847 , n18850 );
xor ( n18852 , n18842 , n18851 );
buf ( n18853 , n6014 );
nand ( n18854 , n6515 , n18853 );
buf ( n18855 , n6015 );
not ( n18856 , n18855 );
and ( n18857 , n18854 , n18856 );
not ( n18858 , n18854 );
buf ( n18859 , n18855 );
and ( n18860 , n18858 , n18859 );
nor ( n18861 , n18857 , n18860 );
xor ( n18862 , n18852 , n18861 );
buf ( n18863 , n18862 );
xor ( n18864 , n7159 , n18863 );
not ( n18865 , n18864 );
or ( n18866 , n18824 , n18865 );
or ( n18867 , n18864 , n18823 );
nand ( n18868 , n18866 , n18867 );
buf ( n18869 , n6016 );
buf ( n18870 , n18869 );
not ( n18871 , n18870 );
not ( n18872 , n18461 );
or ( n18873 , n18871 , n18872 );
not ( n18874 , n18869 );
nand ( n18875 , n18462 , n18874 );
nand ( n18876 , n18873 , n18875 );
not ( n18877 , n18876 );
not ( n18878 , n18465 );
and ( n18879 , n18877 , n18878 );
and ( n18880 , n18876 , n18465 );
nor ( n18881 , n18879 , n18880 );
nor ( n18882 , n18868 , n18881 );
not ( n18883 , n18882 );
and ( n18884 , n18790 , n18883 );
and ( n18885 , n18789 , n18882 );
nor ( n18886 , n18884 , n18885 );
not ( n18887 , n18886 );
not ( n18888 , n18887 );
not ( n18889 , n7370 );
not ( n18890 , n18889 );
xor ( n18891 , n9460 , n18890 );
xnor ( n18892 , n18891 , n8843 );
not ( n18893 , n17560 );
not ( n18894 , n8888 );
or ( n18895 , n18893 , n18894 );
not ( n18896 , n17560 );
not ( n18897 , n8888 );
nand ( n18898 , n18896 , n18897 );
nand ( n18899 , n18895 , n18898 );
not ( n18900 , n18899 );
not ( n18901 , n8916 );
and ( n18902 , n18900 , n18901 );
and ( n18903 , n18899 , n8916 );
nor ( n18904 , n18902 , n18903 );
not ( n18905 , n18904 );
nand ( n18906 , n18892 , n18905 );
buf ( n18907 , n6017 );
nand ( n18908 , n6871 , n18907 );
buf ( n18909 , n6018 );
xor ( n18910 , n18908 , n18909 );
buf ( n18911 , n18910 );
not ( n18912 , n18911 );
not ( n18913 , n18912 );
not ( n18914 , n10581 );
or ( n18915 , n18913 , n18914 );
nand ( n18916 , n10587 , n18911 );
nand ( n18917 , n18915 , n18916 );
buf ( n18918 , n6019 );
buf ( n18919 , n18918 );
not ( n18920 , n18919 );
buf ( n18921 , n6020 );
not ( n18922 , n18921 );
not ( n18923 , n18922 );
or ( n18924 , n18920 , n18923 );
not ( n18925 , n18918 );
buf ( n18926 , n18921 );
nand ( n18927 , n18925 , n18926 );
nand ( n18928 , n18924 , n18927 );
buf ( n18929 , n6021 );
buf ( n18930 , n18929 );
and ( n18931 , n18928 , n18930 );
not ( n18932 , n18928 );
not ( n18933 , n18929 );
and ( n18934 , n18932 , n18933 );
nor ( n18935 , n18931 , n18934 );
buf ( n18936 , n6022 );
nand ( n18937 , n6646 , n18936 );
buf ( n18938 , n6023 );
buf ( n18939 , n18938 );
and ( n18940 , n18937 , n18939 );
not ( n18941 , n18937 );
not ( n18942 , n18938 );
and ( n18943 , n18941 , n18942 );
nor ( n18944 , n18940 , n18943 );
xor ( n18945 , n18935 , n18944 );
buf ( n18946 , n6024 );
nand ( n18947 , n10372 , n18946 );
buf ( n18948 , n6025 );
not ( n18949 , n18948 );
and ( n18950 , n18947 , n18949 );
not ( n18951 , n18947 );
buf ( n18952 , n18948 );
and ( n18953 , n18951 , n18952 );
nor ( n18954 , n18950 , n18953 );
xor ( n18955 , n18945 , n18954 );
buf ( n18956 , n18955 );
not ( n18957 , n18956 );
and ( n18958 , n18917 , n18957 );
not ( n18959 , n18917 );
and ( n18960 , n18959 , n18956 );
nor ( n18961 , n18958 , n18960 );
not ( n18962 , n18961 );
and ( n18963 , n18906 , n18962 );
not ( n18964 , n18906 );
and ( n18965 , n18964 , n18961 );
nor ( n18966 , n18963 , n18965 );
not ( n18967 , n18966 );
not ( n18968 , n18967 );
nand ( n18969 , n18789 , n18868 );
not ( n18970 , n18969 );
buf ( n18971 , n6026 );
nand ( n18972 , n8781 , n18971 );
not ( n18973 , n18972 );
buf ( n18974 , n6027 );
not ( n18975 , n18974 );
and ( n18976 , n18973 , n18975 );
and ( n18977 , n18972 , n18974 );
nor ( n18978 , n18976 , n18977 );
xor ( n18979 , n18978 , n17614 );
xnor ( n18980 , n18979 , n13547 );
not ( n18981 , n18980 );
not ( n18982 , n18981 );
and ( n18983 , n18970 , n18982 );
and ( n18984 , n18969 , n18981 );
nor ( n18985 , n18983 , n18984 );
not ( n18986 , n18985 );
not ( n18987 , n18986 );
or ( n18988 , n18968 , n18987 );
nand ( n18989 , n18985 , n18966 );
nand ( n18990 , n18988 , n18989 );
not ( n18991 , n18990 );
buf ( n18992 , n6028 );
nand ( n18993 , n6605 , n18992 );
buf ( n18994 , n6029 );
not ( n18995 , n18994 );
and ( n18996 , n18993 , n18995 );
not ( n18997 , n18993 );
buf ( n18998 , n18994 );
and ( n18999 , n18997 , n18998 );
nor ( n19000 , n18996 , n18999 );
not ( n19001 , n19000 );
not ( n19002 , n19001 );
not ( n19003 , n19002 );
buf ( n19004 , n12348 );
xor ( n19005 , n19004 , n12358 );
xnor ( n19006 , n19005 , n12374 );
not ( n19007 , n19006 );
not ( n19008 , n19007 );
or ( n19009 , n19003 , n19008 );
not ( n19010 , n19002 );
nand ( n19011 , n19010 , n19006 );
nand ( n19012 , n19009 , n19011 );
buf ( n19013 , n6030 );
buf ( n19014 , n19013 );
not ( n19015 , n19014 );
buf ( n19016 , n6031 );
not ( n19017 , n19016 );
not ( n19018 , n19017 );
or ( n19019 , n19015 , n19018 );
not ( n19020 , n19013 );
buf ( n19021 , n19016 );
nand ( n19022 , n19020 , n19021 );
nand ( n19023 , n19019 , n19022 );
buf ( n19024 , n6032 );
buf ( n19025 , n19024 );
and ( n19026 , n19023 , n19025 );
not ( n19027 , n19023 );
not ( n19028 , n19024 );
and ( n19029 , n19027 , n19028 );
nor ( n19030 , n19026 , n19029 );
xor ( n19031 , n19030 , n18910 );
buf ( n19032 , n6033 );
nand ( n19033 , n7569 , n19032 );
buf ( n19034 , n6034 );
not ( n19035 , n19034 );
and ( n19036 , n19033 , n19035 );
not ( n19037 , n19033 );
buf ( n19038 , n19034 );
and ( n19039 , n19037 , n19038 );
nor ( n19040 , n19036 , n19039 );
xor ( n19041 , n19031 , n19040 );
not ( n19042 , n19041 );
and ( n19043 , n19012 , n19042 );
not ( n19044 , n19012 );
buf ( n19045 , n19041 );
and ( n19046 , n19044 , n19045 );
nor ( n19047 , n19043 , n19046 );
not ( n19048 , n19047 );
not ( n19049 , n10306 );
not ( n19050 , n7848 );
and ( n19051 , n19049 , n19050 );
and ( n19052 , n10306 , n7848 );
nor ( n19053 , n19051 , n19052 );
not ( n19054 , n19053 );
not ( n19055 , n10296 );
or ( n19056 , n19054 , n19055 );
or ( n19057 , n10296 , n19053 );
nand ( n19058 , n19056 , n19057 );
and ( n19059 , n19058 , n9322 );
not ( n19060 , n19058 );
buf ( n19061 , n9321 );
and ( n19062 , n19060 , n19061 );
nor ( n19063 , n19059 , n19062 );
not ( n19064 , n19063 );
not ( n19065 , n12205 );
buf ( n19066 , n6035 );
buf ( n19067 , n19066 );
not ( n19068 , n19067 );
buf ( n19069 , n6036 );
not ( n19070 , n19069 );
not ( n19071 , n19070 );
or ( n19072 , n19068 , n19071 );
not ( n19073 , n19066 );
buf ( n19074 , n19069 );
nand ( n19075 , n19073 , n19074 );
nand ( n19076 , n19072 , n19075 );
and ( n19077 , n19076 , n17686 );
not ( n19078 , n19076 );
not ( n19079 , n17685 );
and ( n19080 , n19078 , n19079 );
nor ( n19081 , n19077 , n19080 );
buf ( n19082 , n6037 );
nand ( n19083 , n6719 , n19082 );
buf ( n19084 , n6038 );
buf ( n19085 , n19084 );
and ( n19086 , n19083 , n19085 );
not ( n19087 , n19083 );
not ( n19088 , n19084 );
and ( n19089 , n19087 , n19088 );
nor ( n19090 , n19086 , n19089 );
not ( n19091 , n19090 );
xor ( n19092 , n19081 , n19091 );
xnor ( n19093 , n19092 , n12771 );
not ( n19094 , n19093 );
or ( n19095 , n19065 , n19094 );
not ( n19096 , n12205 );
xor ( n19097 , n19081 , n19090 );
xnor ( n19098 , n19097 , n12771 );
nand ( n19099 , n19096 , n19098 );
nand ( n19100 , n19095 , n19099 );
buf ( n19101 , n9694 );
not ( n19102 , n19101 );
and ( n19103 , n19100 , n19102 );
not ( n19104 , n19100 );
not ( n19105 , n9695 );
and ( n19106 , n19104 , n19105 );
nor ( n19107 , n19103 , n19106 );
nand ( n19108 , n19064 , n19107 );
not ( n19109 , n19108 );
and ( n19110 , n19048 , n19109 );
and ( n19111 , n19108 , n19047 );
nor ( n19112 , n19110 , n19111 );
not ( n19113 , n19112 );
not ( n19114 , n19113 );
buf ( n19115 , n6039 );
buf ( n19116 , n19115 );
not ( n19117 , n19116 );
buf ( n19118 , n6040 );
buf ( n19119 , n19118 );
not ( n19120 , n19119 );
buf ( n19121 , n6041 );
not ( n19122 , n19121 );
not ( n19123 , n19122 );
or ( n19124 , n19120 , n19123 );
not ( n19125 , n19118 );
buf ( n19126 , n19121 );
nand ( n19127 , n19125 , n19126 );
nand ( n19128 , n19124 , n19127 );
not ( n19129 , n19128 );
not ( n19130 , n19129 );
or ( n19131 , n19117 , n19130 );
not ( n19132 , n19115 );
nand ( n19133 , n19128 , n19132 );
nand ( n19134 , n19131 , n19133 );
not ( n19135 , n19134 );
buf ( n19136 , n6042 );
buf ( n19137 , n6043 );
nand ( n19138 , n6815 , n19137 );
buf ( n19139 , n6044 );
buf ( n19140 , n19139 );
and ( n19141 , n19138 , n19140 );
not ( n19142 , n19138 );
not ( n19143 , n19139 );
and ( n19144 , n19142 , n19143 );
nor ( n19145 , n19141 , n19144 );
xor ( n19146 , n19136 , n19145 );
buf ( n19147 , n6045 );
nand ( n19148 , n7247 , n19147 );
buf ( n19149 , n6046 );
buf ( n19150 , n19149 );
and ( n19151 , n19148 , n19150 );
not ( n19152 , n19148 );
not ( n19153 , n19149 );
and ( n19154 , n19152 , n19153 );
nor ( n19155 , n19151 , n19154 );
xnor ( n19156 , n19146 , n19155 );
buf ( n19157 , n19156 );
not ( n19158 , n19157 );
or ( n19159 , n19135 , n19158 );
or ( n19160 , n19157 , n19134 );
nand ( n19161 , n19159 , n19160 );
buf ( n19162 , n6047 );
buf ( n19163 , n19162 );
not ( n19164 , n19163 );
buf ( n19165 , n6048 );
not ( n19166 , n19165 );
not ( n19167 , n19166 );
or ( n19168 , n19164 , n19167 );
not ( n19169 , n19162 );
buf ( n19170 , n19165 );
nand ( n19171 , n19169 , n19170 );
nand ( n19172 , n19168 , n19171 );
buf ( n19173 , n6049 );
not ( n19174 , n19173 );
and ( n19175 , n19172 , n19174 );
not ( n19176 , n19172 );
buf ( n19177 , n19173 );
and ( n19178 , n19176 , n19177 );
nor ( n19179 , n19175 , n19178 );
buf ( n19180 , n6050 );
nand ( n19181 , n9812 , n19180 );
buf ( n19182 , n6051 );
buf ( n19183 , n19182 );
and ( n19184 , n19181 , n19183 );
not ( n19185 , n19181 );
not ( n19186 , n19182 );
and ( n19187 , n19185 , n19186 );
nor ( n19188 , n19184 , n19187 );
xor ( n19189 , n19179 , n19188 );
buf ( n19190 , n6052 );
nand ( n19191 , n8675 , n19190 );
buf ( n19192 , n6053 );
not ( n19193 , n19192 );
and ( n19194 , n19191 , n19193 );
not ( n19195 , n19191 );
buf ( n19196 , n19192 );
and ( n19197 , n19195 , n19196 );
nor ( n19198 , n19194 , n19197 );
xnor ( n19199 , n19189 , n19198 );
buf ( n19200 , n19199 );
and ( n19201 , n19161 , n19200 );
not ( n19202 , n19161 );
xor ( n19203 , n19179 , n19188 );
xor ( n19204 , n19203 , n19198 );
and ( n19205 , n19202 , n19204 );
nor ( n19206 , n19201 , n19205 );
buf ( n19207 , n6054 );
buf ( n19208 , n19207 );
not ( n19209 , n19208 );
buf ( n19210 , n6055 );
not ( n19211 , n19210 );
buf ( n19212 , n6056 );
buf ( n19213 , n19212 );
and ( n19214 , n19211 , n19213 );
not ( n19215 , n19211 );
not ( n19216 , n19212 );
and ( n19217 , n19215 , n19216 );
nor ( n19218 , n19214 , n19217 );
not ( n19219 , n19218 );
or ( n19220 , n19209 , n19219 );
or ( n19221 , n19218 , n19208 );
nand ( n19222 , n19220 , n19221 );
not ( n19223 , n19222 );
buf ( n19224 , n6057 );
not ( n19225 , n19224 );
xor ( n19226 , n13789 , n19225 );
buf ( n19227 , n6058 );
nand ( n19228 , n6916 , n19227 );
buf ( n19229 , n6059 );
not ( n19230 , n19229 );
and ( n19231 , n19228 , n19230 );
not ( n19232 , n19228 );
buf ( n19233 , n19229 );
and ( n19234 , n19232 , n19233 );
nor ( n19235 , n19231 , n19234 );
xnor ( n19236 , n19226 , n19235 );
not ( n19237 , n19236 );
not ( n19238 , n19237 );
or ( n19239 , n19223 , n19238 );
or ( n19240 , n19237 , n19222 );
nand ( n19241 , n19239 , n19240 );
not ( n19242 , n19241 );
buf ( n19243 , n11226 );
not ( n19244 , n19243 );
and ( n19245 , n19242 , n19244 );
and ( n19246 , n19241 , n11228 );
nor ( n19247 , n19245 , n19246 );
not ( n19248 , n19247 );
nand ( n19249 , n19206 , n19248 );
not ( n19250 , n19249 );
buf ( n19251 , n13161 );
xor ( n19252 , n19251 , n13642 );
buf ( n19253 , n6060 );
buf ( n19254 , n6061 );
buf ( n19255 , n19254 );
not ( n19256 , n19255 );
buf ( n19257 , n6062 );
not ( n19258 , n19257 );
not ( n19259 , n19258 );
or ( n19260 , n19256 , n19259 );
not ( n19261 , n19254 );
buf ( n19262 , n19257 );
nand ( n19263 , n19261 , n19262 );
nand ( n19264 , n19260 , n19263 );
xor ( n19265 , n19253 , n19264 );
buf ( n19266 , n6063 );
buf ( n19267 , n6064 );
not ( n19268 , n19267 );
xor ( n19269 , n19266 , n19268 );
buf ( n19270 , n6065 );
nand ( n19271 , n8032 , n19270 );
xnor ( n19272 , n19269 , n19271 );
xnor ( n19273 , n19265 , n19272 );
buf ( n19274 , n19273 );
and ( n19275 , n19252 , n19274 );
not ( n19276 , n19252 );
not ( n19277 , n19274 );
and ( n19278 , n19276 , n19277 );
nor ( n19279 , n19275 , n19278 );
not ( n19280 , n19279 );
or ( n19281 , n19250 , n19280 );
or ( n19282 , n19279 , n19249 );
nand ( n19283 , n19281 , n19282 );
not ( n19284 , n19283 );
not ( n19285 , n19284 );
or ( n19286 , n19114 , n19285 );
nand ( n19287 , n19283 , n19112 );
nand ( n19288 , n19286 , n19287 );
not ( n19289 , n13925 );
buf ( n19290 , n16838 );
not ( n19291 , n19290 );
or ( n19292 , n19289 , n19291 );
buf ( n19293 , n17263 );
nand ( n19294 , n19293 , n13921 );
nand ( n19295 , n19292 , n19294 );
not ( n19296 , n19295 );
not ( n19297 , n16881 );
buf ( n19298 , n19297 );
not ( n19299 , n19298 );
and ( n19300 , n19296 , n19299 );
and ( n19301 , n19295 , n19298 );
nor ( n19302 , n19300 , n19301 );
not ( n19303 , n19302 );
buf ( n19304 , n6066 );
not ( n19305 , n15251 );
buf ( n19306 , n6067 );
not ( n19307 , n19306 );
not ( n19308 , n19307 );
or ( n19309 , n19305 , n19308 );
not ( n19310 , n15250 );
buf ( n19311 , n19306 );
nand ( n19312 , n19310 , n19311 );
nand ( n19313 , n19309 , n19312 );
xor ( n19314 , n19304 , n19313 );
buf ( n19315 , n6068 );
buf ( n19316 , n6069 );
not ( n19317 , n19316 );
xor ( n19318 , n19315 , n19317 );
buf ( n19319 , n6070 );
nand ( n19320 , n7912 , n19319 );
xnor ( n19321 , n19318 , n19320 );
xnor ( n19322 , n19314 , n19321 );
buf ( n19323 , n19322 );
not ( n19324 , n19323 );
not ( n19325 , n19324 );
not ( n19326 , n17903 );
buf ( n19327 , n6071 );
buf ( n19328 , n19327 );
not ( n19329 , n19328 );
buf ( n19330 , n6072 );
not ( n19331 , n19330 );
not ( n19332 , n19331 );
or ( n19333 , n19329 , n19332 );
not ( n19334 , n19327 );
buf ( n19335 , n19330 );
nand ( n19336 , n19334 , n19335 );
nand ( n19337 , n19333 , n19336 );
buf ( n19338 , n6073 );
not ( n19339 , n19338 );
and ( n19340 , n19337 , n19339 );
not ( n19341 , n19337 );
buf ( n19342 , n19338 );
and ( n19343 , n19341 , n19342 );
nor ( n19344 , n19340 , n19343 );
buf ( n19345 , n6074 );
nand ( n19346 , n7698 , n19345 );
buf ( n19347 , n6075 );
not ( n19348 , n19347 );
and ( n19349 , n19346 , n19348 );
not ( n19350 , n19346 );
buf ( n19351 , n19347 );
and ( n19352 , n19350 , n19351 );
nor ( n19353 , n19349 , n19352 );
xor ( n19354 , n19344 , n19353 );
buf ( n19355 , n6076 );
nand ( n19356 , n11946 , n19355 );
buf ( n19357 , n6077 );
not ( n19358 , n19357 );
and ( n19359 , n19356 , n19358 );
not ( n19360 , n19356 );
buf ( n19361 , n19357 );
and ( n19362 , n19360 , n19361 );
nor ( n19363 , n19359 , n19362 );
xnor ( n19364 , n19354 , n19363 );
buf ( n19365 , n19364 );
not ( n19366 , n19365 );
not ( n19367 , n19366 );
or ( n19368 , n19326 , n19367 );
not ( n19369 , n17903 );
not ( n19370 , n19364 );
not ( n19371 , n19370 );
nand ( n19372 , n19369 , n19371 );
nand ( n19373 , n19368 , n19372 );
not ( n19374 , n19373 );
or ( n19375 , n19325 , n19374 );
or ( n19376 , n19324 , n19373 );
nand ( n19377 , n19375 , n19376 );
not ( n19378 , n19377 );
nand ( n19379 , n19303 , n19378 );
not ( n19380 , n19379 );
not ( n19381 , n12009 );
not ( n19382 , n16910 );
or ( n19383 , n19381 , n19382 );
not ( n19384 , n12009 );
nand ( n19385 , n19384 , n10824 );
nand ( n19386 , n19383 , n19385 );
xor ( n19387 , n19386 , n16917 );
not ( n19388 , n19387 );
not ( n19389 , n19388 );
and ( n19390 , n19380 , n19389 );
and ( n19391 , n19379 , n19388 );
nor ( n19392 , n19390 , n19391 );
and ( n19393 , n19288 , n19392 );
not ( n19394 , n19288 );
not ( n19395 , n19392 );
and ( n19396 , n19394 , n19395 );
nor ( n19397 , n19393 , n19396 );
not ( n19398 , n19397 );
and ( n19399 , n18991 , n19398 );
and ( n19400 , n18990 , n19397 );
nor ( n19401 , n19399 , n19400 );
not ( n19402 , n19401 );
or ( n19403 , n18888 , n19402 );
not ( n19404 , n18887 );
not ( n19405 , n19397 );
and ( n19406 , n18990 , n19405 );
not ( n19407 , n18990 );
and ( n19408 , n19407 , n19397 );
nor ( n19409 , n19406 , n19408 );
nand ( n19410 , n19404 , n19409 );
nand ( n19411 , n19403 , n19410 );
xor ( n19412 , n16043 , n14152 );
xnor ( n19413 , n19412 , n14175 );
not ( n19414 , n19413 );
not ( n19415 , n7217 );
buf ( n19416 , n6078 );
buf ( n19417 , n19416 );
not ( n19418 , n19417 );
buf ( n19419 , n6079 );
not ( n19420 , n19419 );
not ( n19421 , n19420 );
or ( n19422 , n19418 , n19421 );
not ( n19423 , n19416 );
buf ( n19424 , n19419 );
nand ( n19425 , n19423 , n19424 );
nand ( n19426 , n19422 , n19425 );
and ( n19427 , n19426 , n18599 );
not ( n19428 , n19426 );
not ( n19429 , n18598 );
and ( n19430 , n19428 , n19429 );
nor ( n19431 , n19427 , n19430 );
xor ( n19432 , n19431 , n15372 );
buf ( n19433 , n6080 );
nand ( n19434 , n7107 , n19433 );
buf ( n19435 , n6081 );
buf ( n19436 , n19435 );
and ( n19437 , n19434 , n19436 );
not ( n19438 , n19434 );
not ( n19439 , n19435 );
and ( n19440 , n19438 , n19439 );
nor ( n19441 , n19437 , n19440 );
xnor ( n19442 , n19432 , n19441 );
buf ( n19443 , n19442 );
not ( n19444 , n19443 );
or ( n19445 , n19415 , n19444 );
not ( n19446 , n19442 );
buf ( n19447 , n19446 );
nand ( n19448 , n19447 , n7213 );
nand ( n19449 , n19445 , n19448 );
not ( n19450 , n18862 );
buf ( n19451 , n19450 );
xor ( n19452 , n19449 , n19451 );
nand ( n19453 , n19414 , n19452 );
buf ( n19454 , n6082 );
buf ( n19455 , n6083 );
buf ( n19456 , n19455 );
not ( n19457 , n19456 );
buf ( n19458 , n6084 );
not ( n19459 , n19458 );
not ( n19460 , n19459 );
or ( n19461 , n19457 , n19460 );
not ( n19462 , n19455 );
buf ( n19463 , n19458 );
nand ( n19464 , n19462 , n19463 );
nand ( n19465 , n19461 , n19464 );
not ( n19466 , n19465 );
xor ( n19467 , n19454 , n19466 );
xor ( n19468 , n11791 , n18974 );
xnor ( n19469 , n19468 , n18972 );
xnor ( n19470 , n19467 , n19469 );
not ( n19471 , n19470 );
xor ( n19472 , n16165 , n19471 );
xnor ( n19473 , n19472 , n10351 );
not ( n19474 , n19473 );
and ( n19475 , n19453 , n19474 );
not ( n19476 , n19453 );
and ( n19477 , n19476 , n19473 );
nor ( n19478 , n19475 , n19477 );
not ( n19479 , n19478 );
buf ( n19480 , n14373 );
not ( n19481 , n19480 );
not ( n19482 , n7097 );
buf ( n19483 , n6085 );
nand ( n19484 , n8323 , n19483 );
buf ( n19485 , n6086 );
buf ( n19486 , n19485 );
and ( n19487 , n19484 , n19486 );
not ( n19488 , n19484 );
not ( n19489 , n19485 );
and ( n19490 , n19488 , n19489 );
nor ( n19491 , n19487 , n19490 );
not ( n19492 , n19491 );
buf ( n19493 , n6087 );
nand ( n19494 , n6502 , n19493 );
buf ( n19495 , n6088 );
not ( n19496 , n19495 );
and ( n19497 , n19494 , n19496 );
not ( n19498 , n19494 );
buf ( n19499 , n19495 );
and ( n19500 , n19498 , n19499 );
nor ( n19501 , n19497 , n19500 );
not ( n19502 , n19501 );
or ( n19503 , n19492 , n19502 );
or ( n19504 , n19491 , n19501 );
nand ( n19505 , n19503 , n19504 );
buf ( n19506 , n6089 );
buf ( n19507 , n19506 );
not ( n19508 , n19507 );
not ( n19509 , n13011 );
or ( n19510 , n19508 , n19509 );
not ( n19511 , n19506 );
buf ( n19512 , n13010 );
nand ( n19513 , n19511 , n19512 );
nand ( n19514 , n19510 , n19513 );
buf ( n19515 , n6090 );
not ( n19516 , n19515 );
and ( n19517 , n19514 , n19516 );
not ( n19518 , n19514 );
buf ( n19519 , n19515 );
and ( n19520 , n19518 , n19519 );
nor ( n19521 , n19517 , n19520 );
and ( n19522 , n19505 , n19521 );
not ( n19523 , n19505 );
not ( n19524 , n19521 );
and ( n19525 , n19523 , n19524 );
nor ( n19526 , n19522 , n19525 );
buf ( n19527 , n19526 );
not ( n19528 , n19527 );
or ( n19529 , n19482 , n19528 );
or ( n19530 , n19527 , n7097 );
nand ( n19531 , n19529 , n19530 );
not ( n19532 , n19531 );
and ( n19533 , n19481 , n19532 );
and ( n19534 , n19480 , n19531 );
nor ( n19535 , n19533 , n19534 );
not ( n19536 , n19535 );
not ( n19537 , n19536 );
not ( n19538 , n10059 );
not ( n19539 , n15428 );
or ( n19540 , n19538 , n19539 );
not ( n19541 , n15424 );
nand ( n19542 , n19541 , n10055 );
nand ( n19543 , n19540 , n19542 );
and ( n19544 , n19543 , n15475 );
not ( n19545 , n19543 );
and ( n19546 , n19545 , n15471 );
or ( n19547 , n19544 , n19546 );
not ( n19548 , n19547 );
not ( n19549 , n7666 );
xor ( n19550 , n7605 , n7625 );
not ( n19551 , n7615 );
xnor ( n19552 , n19550 , n19551 );
buf ( n19553 , n6091 );
not ( n19554 , n19553 );
and ( n19555 , n19552 , n19554 );
not ( n19556 , n19552 );
buf ( n19557 , n19553 );
and ( n19558 , n19556 , n19557 );
nor ( n19559 , n19555 , n19558 );
not ( n19560 , n19559 );
and ( n19561 , n19549 , n19560 );
and ( n19562 , n7666 , n19559 );
nor ( n19563 , n19561 , n19562 );
not ( n19564 , n19563 );
nand ( n19565 , n19548 , n19564 );
not ( n19566 , n19565 );
or ( n19567 , n19537 , n19566 );
or ( n19568 , n19565 , n19536 );
nand ( n19569 , n19567 , n19568 );
not ( n19570 , n19569 );
and ( n19571 , n19479 , n19570 );
and ( n19572 , n19478 , n19569 );
nor ( n19573 , n19571 , n19572 );
not ( n19574 , n19573 );
not ( n19575 , n13758 );
buf ( n19576 , n6092 );
not ( n19577 , n19576 );
buf ( n19578 , n6093 );
not ( n19579 , n19578 );
buf ( n19580 , n6094 );
buf ( n19581 , n19580 );
nand ( n19582 , n19579 , n19581 );
not ( n19583 , n19580 );
buf ( n19584 , n19578 );
nand ( n19585 , n19583 , n19584 );
and ( n19586 , n19582 , n19585 );
xor ( n19587 , n19577 , n19586 );
buf ( n19588 , n6095 );
buf ( n19589 , n6096 );
xor ( n19590 , n19588 , n19589 );
buf ( n19591 , n6097 );
nand ( n19592 , n8608 , n19591 );
xnor ( n19593 , n19590 , n19592 );
xor ( n19594 , n19587 , n19593 );
not ( n19595 , n19594 );
not ( n19596 , n19595 );
or ( n19597 , n19575 , n19596 );
or ( n19598 , n19595 , n13758 );
nand ( n19599 , n19597 , n19598 );
not ( n19600 , n11910 );
not ( n19601 , n11914 );
and ( n19602 , n19600 , n19601 );
and ( n19603 , n11910 , n11914 );
nor ( n19604 , n19602 , n19603 );
buf ( n19605 , n19604 );
and ( n19606 , n19599 , n19605 );
not ( n19607 , n19599 );
buf ( n19608 , n11916 );
and ( n19609 , n19607 , n19608 );
nor ( n19610 , n19606 , n19609 );
not ( n19611 , n19610 );
not ( n19612 , n19611 );
not ( n19613 , n11054 );
not ( n19614 , n14717 );
and ( n19615 , n19613 , n19614 );
and ( n19616 , n11054 , n14717 );
nor ( n19617 , n19615 , n19616 );
not ( n19618 , n16756 );
buf ( n19619 , n19618 );
and ( n19620 , n19617 , n19619 );
not ( n19621 , n19617 );
not ( n19622 , n19618 );
and ( n19623 , n19621 , n19622 );
nor ( n19624 , n19620 , n19623 );
not ( n19625 , n19624 );
not ( n19626 , n11985 );
not ( n19627 , n16907 );
or ( n19628 , n19626 , n19627 );
not ( n19629 , n16906 );
or ( n19630 , n19629 , n11985 );
nand ( n19631 , n19628 , n19630 );
and ( n19632 , n19631 , n16914 );
not ( n19633 , n19631 );
and ( n19634 , n19633 , n14311 );
nor ( n19635 , n19632 , n19634 );
nand ( n19636 , n19625 , n19635 );
not ( n19637 , n19636 );
or ( n19638 , n19612 , n19637 );
buf ( n19639 , n19635 );
nand ( n19640 , n19625 , n19639 );
or ( n19641 , n19640 , n19611 );
nand ( n19642 , n19638 , n19641 );
not ( n19643 , n19642 );
buf ( n19644 , n6098 );
buf ( n19645 , n19644 );
not ( n19646 , n19645 );
buf ( n19647 , n6099 );
not ( n19648 , n19647 );
not ( n19649 , n19648 );
or ( n19650 , n19646 , n19649 );
not ( n19651 , n19644 );
buf ( n19652 , n19647 );
nand ( n19653 , n19651 , n19652 );
nand ( n19654 , n19650 , n19653 );
and ( n19655 , n19654 , n17134 );
not ( n19656 , n19654 );
not ( n19657 , n17133 );
and ( n19658 , n19656 , n19657 );
nor ( n19659 , n19655 , n19658 );
not ( n19660 , n19659 );
xor ( n19661 , n19660 , n9851 );
xnor ( n19662 , n19661 , n18398 );
and ( n19663 , n9143 , n19662 );
not ( n19664 , n9143 );
xor ( n19665 , n19659 , n9851 );
xnor ( n19666 , n19665 , n18398 );
and ( n19667 , n19664 , n19666 );
nor ( n19668 , n19663 , n19667 );
not ( n19669 , n19668 );
not ( n19670 , n19669 );
buf ( n19671 , n6100 );
not ( n19672 , n19671 );
buf ( n19673 , n6101 );
not ( n19674 , n19673 );
buf ( n19675 , n6102 );
buf ( n19676 , n19675 );
and ( n19677 , n19674 , n19676 );
not ( n19678 , n19674 );
not ( n19679 , n19675 );
and ( n19680 , n19678 , n19679 );
nor ( n19681 , n19677 , n19680 );
xor ( n19682 , n19672 , n19681 );
buf ( n19683 , n6103 );
buf ( n19684 , n6104 );
xor ( n19685 , n19683 , n19684 );
buf ( n19686 , n6105 );
nand ( n19687 , n6973 , n19686 );
xnor ( n19688 , n19685 , n19687 );
xnor ( n19689 , n19682 , n19688 );
not ( n19690 , n19689 );
or ( n19691 , n19670 , n19690 );
not ( n19692 , n19689 );
nand ( n19693 , n19692 , n19668 );
nand ( n19694 , n19691 , n19693 );
not ( n19695 , n19694 );
not ( n19696 , n12635 );
buf ( n19697 , n6106 );
not ( n19698 , n19697 );
and ( n19699 , n19696 , n19698 );
and ( n19700 , n12635 , n19697 );
nor ( n19701 , n19699 , n19700 );
buf ( n19702 , n6107 );
buf ( n19703 , n19702 );
not ( n19704 , n19703 );
buf ( n19705 , n6108 );
not ( n19706 , n19705 );
not ( n19707 , n19706 );
or ( n19708 , n19704 , n19707 );
not ( n19709 , n19702 );
buf ( n19710 , n19705 );
nand ( n19711 , n19709 , n19710 );
nand ( n19712 , n19708 , n19711 );
buf ( n19713 , n6109 );
not ( n19714 , n19713 );
and ( n19715 , n19712 , n19714 );
not ( n19716 , n19712 );
buf ( n19717 , n19713 );
and ( n19718 , n19716 , n19717 );
nor ( n19719 , n19715 , n19718 );
buf ( n19720 , n6110 );
nand ( n19721 , n7197 , n19720 );
buf ( n19722 , n6111 );
buf ( n19723 , n19722 );
and ( n19724 , n19721 , n19723 );
not ( n19725 , n19721 );
not ( n19726 , n19722 );
and ( n19727 , n19725 , n19726 );
nor ( n19728 , n19724 , n19727 );
xor ( n19729 , n19719 , n19728 );
buf ( n19730 , n6112 );
nand ( n19731 , n7067 , n19730 );
buf ( n19732 , n6113 );
not ( n19733 , n19732 );
and ( n19734 , n19731 , n19733 );
not ( n19735 , n19731 );
buf ( n19736 , n19732 );
and ( n19737 , n19735 , n19736 );
nor ( n19738 , n19734 , n19737 );
xnor ( n19739 , n19729 , n19738 );
not ( n19740 , n19739 );
not ( n19741 , n19740 );
and ( n19742 , n19701 , n19741 );
not ( n19743 , n19701 );
not ( n19744 , n19728 );
xor ( n19745 , n19719 , n19744 );
xnor ( n19746 , n19745 , n19738 );
buf ( n19747 , n19746 );
and ( n19748 , n19743 , n19747 );
nor ( n19749 , n19742 , n19748 );
nand ( n19750 , n19695 , n19749 );
not ( n19751 , n19750 );
not ( n19752 , n16621 );
not ( n19753 , n12206 );
or ( n19754 , n19752 , n19753 );
or ( n19755 , n12206 , n16621 );
nand ( n19756 , n19754 , n19755 );
not ( n19757 , n19756 );
not ( n19758 , n16250 );
and ( n19759 , n19757 , n19758 );
and ( n19760 , n19756 , n16250 );
nor ( n19761 , n19759 , n19760 );
not ( n19762 , n19761 );
not ( n19763 , n19762 );
and ( n19764 , n19751 , n19763 );
and ( n19765 , n19750 , n19762 );
nor ( n19766 , n19764 , n19765 );
not ( n19767 , n19766 );
or ( n19768 , n19643 , n19767 );
or ( n19769 , n19766 , n19642 );
nand ( n19770 , n19768 , n19769 );
not ( n19771 , n19770 );
not ( n19772 , n7891 );
not ( n19773 , n10270 );
not ( n19774 , n19773 );
not ( n19775 , n19774 );
or ( n19776 , n19772 , n19775 );
or ( n19777 , n10271 , n7891 );
nand ( n19778 , n19776 , n19777 );
and ( n19779 , n19778 , n10314 );
not ( n19780 , n19778 );
and ( n19781 , n19780 , n10311 );
nor ( n19782 , n19779 , n19781 );
not ( n19783 , n19782 );
buf ( n19784 , n15161 );
not ( n19785 , n19784 );
buf ( n19786 , n6114 );
buf ( n19787 , n19786 );
not ( n19788 , n19787 );
not ( n19789 , n19207 );
not ( n19790 , n19789 );
or ( n19791 , n19788 , n19790 );
not ( n19792 , n19786 );
nand ( n19793 , n19792 , n19208 );
nand ( n19794 , n19791 , n19793 );
buf ( n19795 , n6115 );
not ( n19796 , n19795 );
and ( n19797 , n19794 , n19796 );
not ( n19798 , n19794 );
buf ( n19799 , n19795 );
and ( n19800 , n19798 , n19799 );
nor ( n19801 , n19797 , n19800 );
buf ( n19802 , n6116 );
nand ( n19803 , n6770 , n19802 );
buf ( n19804 , n6117 );
not ( n19805 , n19804 );
and ( n19806 , n19803 , n19805 );
not ( n19807 , n19803 );
buf ( n19808 , n19804 );
and ( n19809 , n19807 , n19808 );
nor ( n19810 , n19806 , n19809 );
xor ( n19811 , n19801 , n19810 );
buf ( n19812 , n6118 );
nand ( n19813 , n7259 , n19812 );
buf ( n19814 , n6119 );
not ( n19815 , n19814 );
and ( n19816 , n19813 , n19815 );
not ( n19817 , n19813 );
buf ( n19818 , n19814 );
and ( n19819 , n19817 , n19818 );
nor ( n19820 , n19816 , n19819 );
xnor ( n19821 , n19811 , n19820 );
not ( n19822 , n19821 );
not ( n19823 , n19822 );
or ( n19824 , n19785 , n19823 );
not ( n19825 , n19784 );
not ( n19826 , n19822 );
nand ( n19827 , n19825 , n19826 );
nand ( n19828 , n19824 , n19827 );
buf ( n19829 , n13595 );
buf ( n19830 , n19829 );
and ( n19831 , n19828 , n19830 );
not ( n19832 , n19828 );
buf ( n19833 , n13591 );
buf ( n19834 , n19833 );
and ( n19835 , n19832 , n19834 );
nor ( n19836 , n19831 , n19835 );
nand ( n19837 , n19783 , n19836 );
not ( n19838 , n19837 );
not ( n19839 , n7580 );
nor ( n19840 , n7539 , n15863 );
not ( n19841 , n19840 );
nand ( n19842 , n7539 , n15863 );
nand ( n19843 , n19841 , n19842 );
not ( n19844 , n19843 );
or ( n19845 , n19839 , n19844 );
or ( n19846 , n19843 , n7580 );
nand ( n19847 , n19845 , n19846 );
not ( n19848 , n19847 );
and ( n19849 , n19838 , n19848 );
and ( n19850 , n19837 , n19847 );
nor ( n19851 , n19849 , n19850 );
not ( n19852 , n19851 );
or ( n19853 , n19771 , n19852 );
or ( n19854 , n19851 , n19770 );
nand ( n19855 , n19853 , n19854 );
not ( n19856 , n19855 );
or ( n19857 , n19574 , n19856 );
or ( n19858 , n19855 , n19573 );
nand ( n19859 , n19857 , n19858 );
buf ( n19860 , n19859 );
buf ( n19861 , n19860 );
not ( n19862 , n19861 );
and ( n19863 , n19411 , n19862 );
not ( n19864 , n19411 );
not ( n19865 , n19860 );
not ( n19866 , n19865 );
and ( n19867 , n19864 , n19866 );
nor ( n19868 , n19863 , n19867 );
nand ( n19869 , n18777 , n19868 );
buf ( n19870 , n10665 );
not ( n19871 , n19870 );
not ( n19872 , n13905 );
or ( n19873 , n19871 , n19872 );
buf ( n19874 , n13905 );
or ( n19875 , n19874 , n19870 );
nand ( n19876 , n19873 , n19875 );
not ( n19877 , n19876 );
not ( n19878 , n7803 );
or ( n19879 , n19877 , n19878 );
not ( n19880 , n7802 );
or ( n19881 , n19880 , n19876 );
nand ( n19882 , n19879 , n19881 );
not ( n19883 , n19882 );
not ( n19884 , n16716 );
not ( n19885 , n8354 );
buf ( n19886 , n16755 );
not ( n19887 , n19886 );
or ( n19888 , n19885 , n19887 );
or ( n19889 , n19886 , n8354 );
nand ( n19890 , n19888 , n19889 );
not ( n19891 , n19890 );
or ( n19892 , n19884 , n19891 );
or ( n19893 , n19890 , n16716 );
nand ( n19894 , n19892 , n19893 );
buf ( n19895 , n13627 );
not ( n19896 , n19895 );
not ( n19897 , n13722 );
buf ( n19898 , n6120 );
not ( n19899 , n19898 );
not ( n19900 , n19899 );
or ( n19901 , n19897 , n19900 );
not ( n19902 , n13721 );
buf ( n19903 , n19898 );
nand ( n19904 , n19902 , n19903 );
nand ( n19905 , n19901 , n19904 );
and ( n19906 , n19905 , n17615 );
not ( n19907 , n19905 );
and ( n19908 , n19907 , n17609 );
nor ( n19909 , n19906 , n19908 );
buf ( n19910 , n6121 );
nand ( n19911 , n7563 , n19910 );
buf ( n19912 , n6122 );
buf ( n19913 , n19912 );
and ( n19914 , n19911 , n19913 );
not ( n19915 , n19911 );
not ( n19916 , n19912 );
and ( n19917 , n19915 , n19916 );
nor ( n19918 , n19914 , n19917 );
xor ( n19919 , n19909 , n19918 );
buf ( n19920 , n6123 );
nand ( n19921 , n14573 , n19920 );
buf ( n19922 , n6124 );
not ( n19923 , n19922 );
and ( n19924 , n19921 , n19923 );
not ( n19925 , n19921 );
buf ( n19926 , n19922 );
and ( n19927 , n19925 , n19926 );
nor ( n19928 , n19924 , n19927 );
xnor ( n19929 , n19919 , n19928 );
not ( n19930 , n19929 );
not ( n19931 , n19930 );
or ( n19932 , n19896 , n19931 );
or ( n19933 , n19930 , n19895 );
nand ( n19934 , n19932 , n19933 );
not ( n19935 , n12899 );
buf ( n19936 , n6125 );
not ( n19937 , n19936 );
not ( n19938 , n19937 );
or ( n19939 , n19935 , n19938 );
not ( n19940 , n12898 );
buf ( n19941 , n19936 );
nand ( n19942 , n19940 , n19941 );
nand ( n19943 , n19939 , n19942 );
buf ( n19944 , n6126 );
not ( n19945 , n19944 );
and ( n19946 , n19943 , n19945 );
not ( n19947 , n19943 );
buf ( n19948 , n19944 );
and ( n19949 , n19947 , n19948 );
nor ( n19950 , n19946 , n19949 );
buf ( n19951 , n6127 );
nand ( n19952 , n7977 , n19951 );
buf ( n19953 , n6128 );
buf ( n19954 , n19953 );
and ( n19955 , n19952 , n19954 );
not ( n19956 , n19952 );
not ( n19957 , n19953 );
and ( n19958 , n19956 , n19957 );
nor ( n19959 , n19955 , n19958 );
xor ( n19960 , n19950 , n19959 );
buf ( n19961 , n6129 );
nand ( n19962 , n6816 , n19961 );
buf ( n19963 , n6130 );
not ( n19964 , n19963 );
and ( n19965 , n19962 , n19964 );
not ( n19966 , n19962 );
buf ( n19967 , n19963 );
and ( n19968 , n19966 , n19967 );
nor ( n19969 , n19965 , n19968 );
xnor ( n19970 , n19960 , n19969 );
not ( n19971 , n19970 );
not ( n19972 , n19971 );
xor ( n19973 , n19934 , n19972 );
nand ( n19974 , n19894 , n19973 );
not ( n19975 , n19974 );
or ( n19976 , n19883 , n19975 );
or ( n19977 , n19882 , n19974 );
nand ( n19978 , n19976 , n19977 );
not ( n19979 , n19978 );
buf ( n19980 , n6131 );
nand ( n19981 , n6577 , n19980 );
buf ( n19982 , n6132 );
buf ( n19983 , n19982 );
and ( n19984 , n19981 , n19983 );
not ( n19985 , n19981 );
not ( n19986 , n19982 );
and ( n19987 , n19985 , n19986 );
nor ( n19988 , n19984 , n19987 );
buf ( n19989 , n19988 );
and ( n19990 , n19989 , n10749 );
not ( n19991 , n19989 );
and ( n19992 , n19991 , n10744 );
nor ( n19993 , n19990 , n19992 );
not ( n19994 , n19993 );
and ( n19995 , n9067 , n19994 );
not ( n19996 , n9067 );
and ( n19997 , n19996 , n19993 );
nor ( n19998 , n19995 , n19997 );
not ( n19999 , n10252 );
buf ( n20000 , n6133 );
buf ( n20001 , n20000 );
not ( n20002 , n20001 );
buf ( n20003 , n6134 );
not ( n20004 , n20003 );
not ( n20005 , n20004 );
or ( n20006 , n20002 , n20005 );
not ( n20007 , n20000 );
buf ( n20008 , n20003 );
nand ( n20009 , n20007 , n20008 );
nand ( n20010 , n20006 , n20009 );
buf ( n20011 , n6135 );
not ( n20012 , n20011 );
and ( n20013 , n20010 , n20012 );
not ( n20014 , n20010 );
buf ( n20015 , n20011 );
and ( n20016 , n20014 , n20015 );
nor ( n20017 , n20013 , n20016 );
buf ( n20018 , n6136 );
nand ( n20019 , n7563 , n20018 );
buf ( n20020 , n6137 );
buf ( n20021 , n20020 );
and ( n20022 , n20019 , n20021 );
not ( n20023 , n20019 );
not ( n20024 , n20020 );
and ( n20025 , n20023 , n20024 );
nor ( n20026 , n20022 , n20025 );
xor ( n20027 , n20017 , n20026 );
buf ( n20028 , n6138 );
nand ( n20029 , n7709 , n20028 );
buf ( n20030 , n6139 );
not ( n20031 , n20030 );
and ( n20032 , n20029 , n20031 );
not ( n20033 , n20029 );
buf ( n20034 , n20030 );
and ( n20035 , n20033 , n20034 );
nor ( n20036 , n20032 , n20035 );
xnor ( n20037 , n20027 , n20036 );
not ( n20038 , n20037 );
not ( n20039 , n20038 );
not ( n20040 , n20039 );
or ( n20041 , n19999 , n20040 );
not ( n20042 , n10252 );
nand ( n20043 , n20042 , n20038 );
nand ( n20044 , n20041 , n20043 );
buf ( n20045 , n6140 );
buf ( n20046 , n20045 );
not ( n20047 , n20046 );
buf ( n20048 , n6141 );
not ( n20049 , n20048 );
not ( n20050 , n20049 );
or ( n20051 , n20047 , n20050 );
not ( n20052 , n20045 );
buf ( n20053 , n20048 );
nand ( n20054 , n20052 , n20053 );
nand ( n20055 , n20051 , n20054 );
and ( n20056 , n20055 , n17356 );
not ( n20057 , n20055 );
not ( n20058 , n17355 );
and ( n20059 , n20057 , n20058 );
nor ( n20060 , n20056 , n20059 );
buf ( n20061 , n6142 );
nand ( n20062 , n6828 , n20061 );
buf ( n20063 , n6143 );
buf ( n20064 , n20063 );
and ( n20065 , n20062 , n20064 );
not ( n20066 , n20062 );
not ( n20067 , n20063 );
and ( n20068 , n20066 , n20067 );
nor ( n20069 , n20065 , n20068 );
xor ( n20070 , n20060 , n20069 );
xor ( n20071 , n20070 , n12167 );
not ( n20072 , n20071 );
not ( n20073 , n20072 );
and ( n20074 , n20044 , n20073 );
not ( n20075 , n20044 );
xor ( n20076 , n20060 , n12167 );
xnor ( n20077 , n20076 , n20069 );
buf ( n20078 , n20077 );
and ( n20079 , n20075 , n20078 );
nor ( n20080 , n20074 , n20079 );
nand ( n20081 , n19998 , n20080 );
not ( n20082 , n20081 );
not ( n20083 , n19128 );
not ( n20084 , n19156 );
or ( n20085 , n20083 , n20084 );
not ( n20086 , n19156 );
nand ( n20087 , n20086 , n19129 );
nand ( n20088 , n20085 , n20087 );
not ( n20089 , n20088 );
not ( n20090 , n20089 );
not ( n20091 , n12732 );
not ( n20092 , n15833 );
or ( n20093 , n20091 , n20092 );
nand ( n20094 , n15839 , n12729 );
nand ( n20095 , n20093 , n20094 );
not ( n20096 , n20095 );
and ( n20097 , n20090 , n20096 );
and ( n20098 , n20089 , n20095 );
nor ( n20099 , n20097 , n20098 );
not ( n20100 , n20099 );
not ( n20101 , n20100 );
and ( n20102 , n20082 , n20101 );
and ( n20103 , n20081 , n20100 );
nor ( n20104 , n20102 , n20103 );
not ( n20105 , n20104 );
not ( n20106 , n20105 );
not ( n20107 , n11686 );
not ( n20108 , n20107 );
not ( n20109 , n16796 );
or ( n20110 , n20108 , n20109 );
not ( n20111 , n20107 );
nand ( n20112 , n20111 , n16795 );
nand ( n20113 , n20110 , n20112 );
and ( n20114 , n20113 , n16804 );
not ( n20115 , n20113 );
and ( n20116 , n20115 , n16801 );
nor ( n20117 , n20114 , n20116 );
not ( n20118 , n20117 );
buf ( n20119 , n9978 );
not ( n20120 , n20119 );
buf ( n20121 , n17095 );
not ( n20122 , n20121 );
buf ( n20123 , n6144 );
not ( n20124 , n20123 );
not ( n20125 , n20124 );
or ( n20126 , n20122 , n20125 );
buf ( n20127 , n20123 );
nand ( n20128 , n17096 , n20127 );
nand ( n20129 , n20126 , n20128 );
and ( n20130 , n20129 , n15115 );
not ( n20131 , n20129 );
buf ( n20132 , n15114 );
and ( n20133 , n20131 , n20132 );
nor ( n20134 , n20130 , n20133 );
buf ( n20135 , n6145 );
nand ( n20136 , n8781 , n20135 );
buf ( n20137 , n6146 );
not ( n20138 , n20137 );
and ( n20139 , n20136 , n20138 );
not ( n20140 , n20136 );
buf ( n20141 , n20137 );
and ( n20142 , n20140 , n20141 );
nor ( n20143 , n20139 , n20142 );
xor ( n20144 , n20134 , n20143 );
buf ( n20145 , n6147 );
nand ( n20146 , n10570 , n20145 );
buf ( n20147 , n6148 );
not ( n20148 , n20147 );
and ( n20149 , n20146 , n20148 );
not ( n20150 , n20146 );
buf ( n20151 , n20147 );
and ( n20152 , n20150 , n20151 );
nor ( n20153 , n20149 , n20152 );
xnor ( n20154 , n20144 , n20153 );
not ( n20155 , n20154 );
or ( n20156 , n20120 , n20155 );
or ( n20157 , n20154 , n20119 );
nand ( n20158 , n20156 , n20157 );
buf ( n20159 , n6149 );
buf ( n20160 , n20159 );
not ( n20161 , n20160 );
buf ( n20162 , n6150 );
not ( n20163 , n20162 );
not ( n20164 , n20163 );
or ( n20165 , n20161 , n20164 );
not ( n20166 , n20159 );
buf ( n20167 , n20162 );
nand ( n20168 , n20166 , n20167 );
nand ( n20169 , n20165 , n20168 );
buf ( n20170 , n6151 );
buf ( n20171 , n20170 );
and ( n20172 , n20169 , n20171 );
not ( n20173 , n20169 );
not ( n20174 , n20170 );
and ( n20175 , n20173 , n20174 );
nor ( n20176 , n20172 , n20175 );
buf ( n20177 , n6152 );
nand ( n20178 , n8781 , n20177 );
buf ( n20179 , n6153 );
not ( n20180 , n20179 );
and ( n20181 , n20178 , n20180 );
not ( n20182 , n20178 );
buf ( n20183 , n20179 );
and ( n20184 , n20182 , n20183 );
nor ( n20185 , n20181 , n20184 );
xor ( n20186 , n20176 , n20185 );
buf ( n20187 , n6154 );
nand ( n20188 , n14573 , n20187 );
buf ( n20189 , n6155 );
not ( n20190 , n20189 );
and ( n20191 , n20188 , n20190 );
not ( n20192 , n20188 );
buf ( n20193 , n20189 );
and ( n20194 , n20192 , n20193 );
nor ( n20195 , n20191 , n20194 );
xnor ( n20196 , n20186 , n20195 );
not ( n20197 , n20196 );
not ( n20198 , n20197 );
not ( n20199 , n20198 );
and ( n20200 , n20158 , n20199 );
not ( n20201 , n20158 );
not ( n20202 , n20196 );
not ( n20203 , n20202 );
and ( n20204 , n20201 , n20203 );
nor ( n20205 , n20200 , n20204 );
nand ( n20206 , n20118 , n20205 );
not ( n20207 , n11734 );
buf ( n20208 , n17957 );
not ( n20209 , n20208 );
or ( n20210 , n20207 , n20209 );
or ( n20211 , n20208 , n11734 );
nand ( n20212 , n20210 , n20211 );
and ( n20213 , n20212 , n18003 );
not ( n20214 , n20212 );
and ( n20215 , n20214 , n18004 );
nor ( n20216 , n20213 , n20215 );
buf ( n20217 , n20216 );
xor ( n20218 , n20206 , n20217 );
not ( n20219 , n20218 );
not ( n20220 , n20219 );
or ( n20221 , n20106 , n20220 );
nand ( n20222 , n20218 , n20104 );
nand ( n20223 , n20221 , n20222 );
not ( n20224 , n16093 );
not ( n20225 , n18015 );
or ( n20226 , n20224 , n20225 );
not ( n20227 , n16093 );
nand ( n20228 , n20227 , n14151 );
nand ( n20229 , n20226 , n20228 );
xor ( n20230 , n11670 , n11638 );
xnor ( n20231 , n20230 , n11648 );
buf ( n20232 , n20231 );
xnor ( n20233 , n20229 , n20232 );
buf ( n20234 , n6156 );
nand ( n20235 , n6828 , n20234 );
buf ( n20236 , n6157 );
buf ( n20237 , n20236 );
and ( n20238 , n20235 , n20237 );
not ( n20239 , n20235 );
not ( n20240 , n20236 );
and ( n20241 , n20239 , n20240 );
nor ( n20242 , n20238 , n20241 );
buf ( n20243 , n20242 );
not ( n20244 , n20243 );
buf ( n20245 , n6158 );
buf ( n20246 , n20245 );
not ( n20247 , n20246 );
buf ( n20248 , n6159 );
not ( n20249 , n20248 );
not ( n20250 , n20249 );
or ( n20251 , n20247 , n20250 );
not ( n20252 , n20245 );
buf ( n20253 , n20248 );
nand ( n20254 , n20252 , n20253 );
nand ( n20255 , n20251 , n20254 );
buf ( n20256 , n6160 );
buf ( n20257 , n20256 );
and ( n20258 , n20255 , n20257 );
not ( n20259 , n20255 );
not ( n20260 , n20256 );
and ( n20261 , n20259 , n20260 );
nor ( n20262 , n20258 , n20261 );
buf ( n20263 , n6161 );
nand ( n20264 , n8364 , n20263 );
buf ( n20265 , n6162 );
not ( n20266 , n20265 );
and ( n20267 , n20264 , n20266 );
not ( n20268 , n20264 );
buf ( n20269 , n20265 );
and ( n20270 , n20268 , n20269 );
nor ( n20271 , n20267 , n20270 );
xor ( n20272 , n20262 , n20271 );
xnor ( n20273 , n20272 , n11366 );
not ( n20274 , n20273 );
not ( n20275 , n20274 );
or ( n20276 , n20244 , n20275 );
or ( n20277 , n20274 , n20243 );
nand ( n20278 , n20276 , n20277 );
buf ( n20279 , n6163 );
buf ( n20280 , n6164 );
buf ( n20281 , n20280 );
not ( n20282 , n20281 );
buf ( n20283 , n6165 );
not ( n20284 , n20283 );
not ( n20285 , n20284 );
or ( n20286 , n20282 , n20285 );
not ( n20287 , n20280 );
buf ( n20288 , n20283 );
nand ( n20289 , n20287 , n20288 );
nand ( n20290 , n20286 , n20289 );
xor ( n20291 , n20279 , n20290 );
buf ( n20292 , n6166 );
buf ( n20293 , n6167 );
not ( n20294 , n20293 );
xor ( n20295 , n20292 , n20294 );
buf ( n20296 , n6168 );
nand ( n20297 , n6558 , n20296 );
xnor ( n20298 , n20295 , n20297 );
xnor ( n20299 , n20291 , n20298 );
not ( n20300 , n20299 );
not ( n20301 , n20300 );
and ( n20302 , n20278 , n20301 );
not ( n20303 , n20278 );
buf ( n20304 , n20300 );
and ( n20305 , n20303 , n20304 );
nor ( n20306 , n20302 , n20305 );
buf ( n20307 , n20306 );
nand ( n20308 , n20233 , n20307 );
not ( n20309 , n17522 );
not ( n20310 , n13857 );
buf ( n20311 , n6169 );
not ( n20312 , n20311 );
not ( n20313 , n20312 );
or ( n20314 , n20310 , n20313 );
not ( n20315 , n13856 );
buf ( n20316 , n20311 );
nand ( n20317 , n20315 , n20316 );
nand ( n20318 , n20314 , n20317 );
buf ( n20319 , n6170 );
buf ( n20320 , n20319 );
and ( n20321 , n20318 , n20320 );
not ( n20322 , n20318 );
not ( n20323 , n20319 );
and ( n20324 , n20322 , n20323 );
nor ( n20325 , n20321 , n20324 );
xor ( n20326 , n20325 , n9574 );
buf ( n20327 , n6171 );
nand ( n20328 , n9310 , n20327 );
buf ( n20329 , n6172 );
not ( n20330 , n20329 );
and ( n20331 , n20328 , n20330 );
not ( n20332 , n20328 );
buf ( n20333 , n20329 );
and ( n20334 , n20332 , n20333 );
nor ( n20335 , n20331 , n20334 );
xnor ( n20336 , n20326 , n20335 );
buf ( n20337 , n20336 );
buf ( n20338 , n20337 );
not ( n20339 , n20338 );
or ( n20340 , n20309 , n20339 );
not ( n20341 , n20338 );
nand ( n20342 , n20341 , n17519 );
nand ( n20343 , n20340 , n20342 );
buf ( n20344 , n8888 );
not ( n20345 , n20344 );
and ( n20346 , n20343 , n20345 );
not ( n20347 , n20343 );
and ( n20348 , n20347 , n20344 );
nor ( n20349 , n20346 , n20348 );
not ( n20350 , n20349 );
and ( n20351 , n20308 , n20350 );
not ( n20352 , n20308 );
and ( n20353 , n20352 , n20349 );
nor ( n20354 , n20351 , n20353 );
and ( n20355 , n20223 , n20354 );
not ( n20356 , n20223 );
not ( n20357 , n20354 );
and ( n20358 , n20356 , n20357 );
nor ( n20359 , n20355 , n20358 );
not ( n20360 , n20359 );
not ( n20361 , n14800 );
buf ( n20362 , n13277 );
buf ( n20363 , n13273 );
and ( n20364 , n20362 , n20363 );
not ( n20365 , n20362 );
and ( n20366 , n20365 , n13274 );
nor ( n20367 , n20364 , n20366 );
not ( n20368 , n20367 );
buf ( n20369 , n6173 );
buf ( n20370 , n20369 );
not ( n20371 , n20370 );
buf ( n20372 , n6174 );
not ( n20373 , n20372 );
not ( n20374 , n20373 );
or ( n20375 , n20371 , n20374 );
not ( n20376 , n20369 );
buf ( n20377 , n20372 );
nand ( n20378 , n20376 , n20377 );
nand ( n20379 , n20375 , n20378 );
buf ( n20380 , n6175 );
not ( n20381 , n20380 );
and ( n20382 , n20379 , n20381 );
not ( n20383 , n20379 );
buf ( n20384 , n20380 );
and ( n20385 , n20383 , n20384 );
nor ( n20386 , n20382 , n20385 );
buf ( n20387 , n6176 );
nand ( n20388 , n6828 , n20387 );
buf ( n20389 , n6177 );
buf ( n20390 , n20389 );
and ( n20391 , n20388 , n20390 );
not ( n20392 , n20388 );
not ( n20393 , n20389 );
and ( n20394 , n20392 , n20393 );
nor ( n20395 , n20391 , n20394 );
xor ( n20396 , n20386 , n20395 );
buf ( n20397 , n6178 );
nand ( n20398 , n8966 , n20397 );
buf ( n20399 , n6179 );
buf ( n20400 , n20399 );
and ( n20401 , n20398 , n20400 );
not ( n20402 , n20398 );
not ( n20403 , n20399 );
and ( n20404 , n20402 , n20403 );
nor ( n20405 , n20401 , n20404 );
not ( n20406 , n20405 );
xor ( n20407 , n20396 , n20406 );
not ( n20408 , n20407 );
or ( n20409 , n20368 , n20408 );
buf ( n20410 , n20407 );
or ( n20411 , n20410 , n20367 );
nand ( n20412 , n20409 , n20411 );
not ( n20413 , n20412 );
or ( n20414 , n20361 , n20413 );
buf ( n20415 , n14794 );
or ( n20416 , n20412 , n20415 );
nand ( n20417 , n20414 , n20416 );
not ( n20418 , n20417 );
buf ( n20419 , n6180 );
nand ( n20420 , n7709 , n20419 );
buf ( n20421 , n6181 );
not ( n20422 , n20421 );
and ( n20423 , n20420 , n20422 );
not ( n20424 , n20420 );
buf ( n20425 , n20421 );
and ( n20426 , n20424 , n20425 );
nor ( n20427 , n20423 , n20426 );
not ( n20428 , n18082 );
xor ( n20429 , n20427 , n20428 );
xnor ( n20430 , n20429 , n7665 );
not ( n20431 , n20430 );
nand ( n20432 , n20418 , n20431 );
not ( n20433 , n20432 );
not ( n20434 , n11414 );
not ( n20435 , n6792 );
or ( n20436 , n20434 , n20435 );
xor ( n20437 , n6769 , n6789 );
xnor ( n20438 , n20437 , n6779 );
buf ( n20439 , n20438 );
nand ( n20440 , n20439 , n11411 );
nand ( n20441 , n20436 , n20440 );
not ( n20442 , n20441 );
buf ( n20443 , n6182 );
buf ( n20444 , n20443 );
not ( n20445 , n20444 );
buf ( n20446 , n6183 );
not ( n20447 , n20446 );
not ( n20448 , n20447 );
or ( n20449 , n20445 , n20448 );
not ( n20450 , n20443 );
buf ( n20451 , n20446 );
nand ( n20452 , n20450 , n20451 );
nand ( n20453 , n20449 , n20452 );
xor ( n20454 , n19697 , n20453 );
buf ( n20455 , n6184 );
buf ( n20456 , n6185 );
not ( n20457 , n20456 );
xor ( n20458 , n20455 , n20457 );
buf ( n20459 , n6186 );
nand ( n20460 , n6647 , n20459 );
xnor ( n20461 , n20458 , n20460 );
xnor ( n20462 , n20454 , n20461 );
buf ( n20463 , n20462 );
not ( n20464 , n20463 );
not ( n20465 , n20464 );
and ( n20466 , n20442 , n20465 );
and ( n20467 , n20464 , n20441 );
nor ( n20468 , n20466 , n20467 );
not ( n20469 , n20468 );
not ( n20470 , n20469 );
and ( n20471 , n20433 , n20470 );
and ( n20472 , n20432 , n20469 );
nor ( n20473 , n20471 , n20472 );
not ( n20474 , n20473 );
not ( n20475 , n19882 );
not ( n20476 , n19973 );
nand ( n20477 , n20475 , n20476 );
not ( n20478 , n20477 );
buf ( n20479 , n6187 );
buf ( n20480 , n20479 );
not ( n20481 , n20480 );
buf ( n20482 , n6188 );
not ( n20483 , n20482 );
not ( n20484 , n20483 );
or ( n20485 , n20481 , n20484 );
not ( n20486 , n20479 );
buf ( n20487 , n20482 );
nand ( n20488 , n20486 , n20487 );
nand ( n20489 , n20485 , n20488 );
buf ( n20490 , n6189 );
buf ( n20491 , n20490 );
and ( n20492 , n20489 , n20491 );
not ( n20493 , n20489 );
not ( n20494 , n20490 );
and ( n20495 , n20493 , n20494 );
nor ( n20496 , n20492 , n20495 );
buf ( n20497 , n6190 );
nand ( n20498 , n8781 , n20497 );
buf ( n20499 , n6191 );
buf ( n20500 , n20499 );
and ( n20501 , n20498 , n20500 );
not ( n20502 , n20498 );
not ( n20503 , n20499 );
and ( n20504 , n20502 , n20503 );
nor ( n20505 , n20501 , n20504 );
xor ( n20506 , n20496 , n20505 );
buf ( n20507 , n6192 );
nand ( n20508 , n6719 , n20507 );
buf ( n20509 , n6193 );
buf ( n20510 , n20509 );
and ( n20511 , n20508 , n20510 );
not ( n20512 , n20508 );
not ( n20513 , n20509 );
and ( n20514 , n20512 , n20513 );
nor ( n20515 , n20511 , n20514 );
not ( n20516 , n20515 );
xnor ( n20517 , n20506 , n20516 );
buf ( n20518 , n20517 );
xor ( n20519 , n16856 , n20518 );
not ( n20520 , n15874 );
not ( n20521 , n20520 );
buf ( n20522 , n20521 );
xnor ( n20523 , n20519 , n20522 );
not ( n20524 , n20523 );
or ( n20525 , n20478 , n20524 );
or ( n20526 , n20523 , n20477 );
nand ( n20527 , n20525 , n20526 );
not ( n20528 , n20527 );
and ( n20529 , n20474 , n20528 );
and ( n20530 , n20473 , n20527 );
nor ( n20531 , n20529 , n20530 );
not ( n20532 , n20531 );
and ( n20533 , n20360 , n20532 );
not ( n20534 , n20360 );
and ( n20535 , n20534 , n20531 );
nor ( n20536 , n20533 , n20535 );
not ( n20537 , n20536 );
or ( n20538 , n19979 , n20537 );
not ( n20539 , n19978 );
not ( n20540 , n20531 );
not ( n20541 , n20359 );
or ( n20542 , n20540 , n20541 );
nand ( n20543 , n20360 , n20532 );
nand ( n20544 , n20542 , n20543 );
nand ( n20545 , n20539 , n20544 );
nand ( n20546 , n20538 , n20545 );
not ( n20547 , n9756 );
not ( n20548 , n8916 );
or ( n20549 , n20547 , n20548 );
not ( n20550 , n9756 );
nand ( n20551 , n20550 , n8913 );
nand ( n20552 , n20549 , n20551 );
buf ( n20553 , n17411 );
not ( n20554 , n20553 );
and ( n20555 , n20552 , n20554 );
not ( n20556 , n20552 );
buf ( n20557 , n17412 );
not ( n20558 , n20557 );
and ( n20559 , n20556 , n20558 );
nor ( n20560 , n20555 , n20559 );
not ( n20561 , n20560 );
not ( n20562 , n11190 );
xor ( n20563 , n13767 , n13776 );
xor ( n20564 , n20563 , n13784 );
not ( n20565 , n20564 );
not ( n20566 , n20565 );
or ( n20567 , n20562 , n20566 );
not ( n20568 , n11190 );
nand ( n20569 , n20568 , n20564 );
nand ( n20570 , n20567 , n20569 );
buf ( n20571 , n14684 );
not ( n20572 , n20571 );
and ( n20573 , n20570 , n20572 );
not ( n20574 , n20570 );
buf ( n20575 , n14683 );
not ( n20576 , n20575 );
and ( n20577 , n20574 , n20576 );
nor ( n20578 , n20573 , n20577 );
nand ( n20579 , n20561 , n20578 );
not ( n20580 , n20579 );
not ( n20581 , n12218 );
buf ( n20582 , n6194 );
buf ( n20583 , n20582 );
not ( n20584 , n20583 );
buf ( n20585 , n6195 );
not ( n20586 , n20585 );
not ( n20587 , n20586 );
or ( n20588 , n20584 , n20587 );
not ( n20589 , n20582 );
buf ( n20590 , n20585 );
nand ( n20591 , n20589 , n20590 );
nand ( n20592 , n20588 , n20591 );
buf ( n20593 , n6196 );
not ( n20594 , n20593 );
and ( n20595 , n20592 , n20594 );
not ( n20596 , n20592 );
buf ( n20597 , n20593 );
and ( n20598 , n20596 , n20597 );
nor ( n20599 , n20595 , n20598 );
buf ( n20600 , n6197 );
nand ( n20601 , n7014 , n20600 );
buf ( n20602 , n6198 );
buf ( n20603 , n20602 );
and ( n20604 , n20601 , n20603 );
not ( n20605 , n20601 );
not ( n20606 , n20602 );
and ( n20607 , n20605 , n20606 );
nor ( n20608 , n20604 , n20607 );
xor ( n20609 , n20599 , n20608 );
buf ( n20610 , n6199 );
nand ( n20611 , n7344 , n20610 );
buf ( n20612 , n6200 );
buf ( n20613 , n20612 );
and ( n20614 , n20611 , n20613 );
not ( n20615 , n20611 );
not ( n20616 , n20612 );
and ( n20617 , n20615 , n20616 );
nor ( n20618 , n20614 , n20617 );
xor ( n20619 , n20609 , n20618 );
not ( n20620 , n20619 );
or ( n20621 , n20581 , n20620 );
not ( n20622 , n12218 );
xor ( n20623 , n20599 , n20618 );
buf ( n20624 , n20608 );
xnor ( n20625 , n20623 , n20624 );
nand ( n20626 , n20622 , n20625 );
nand ( n20627 , n20621 , n20626 );
buf ( n20628 , n19098 );
and ( n20629 , n20627 , n20628 );
not ( n20630 , n20627 );
buf ( n20631 , n19093 );
and ( n20632 , n20630 , n20631 );
nor ( n20633 , n20629 , n20632 );
not ( n20634 , n20633 );
and ( n20635 , n20580 , n20634 );
and ( n20636 , n20579 , n20633 );
nor ( n20637 , n20635 , n20636 );
xor ( n20638 , n13259 , n13270 );
xnor ( n20639 , n20638 , n13278 );
not ( n20640 , n20639 );
not ( n20641 , n20640 );
not ( n20642 , n7688 );
buf ( n20643 , n6201 );
buf ( n20644 , n20643 );
not ( n20645 , n20644 );
buf ( n20646 , n6202 );
not ( n20647 , n20646 );
not ( n20648 , n20647 );
or ( n20649 , n20645 , n20648 );
not ( n20650 , n20643 );
buf ( n20651 , n20646 );
nand ( n20652 , n20650 , n20651 );
nand ( n20653 , n20649 , n20652 );
buf ( n20654 , n6203 );
buf ( n20655 , n20654 );
and ( n20656 , n20653 , n20655 );
not ( n20657 , n20653 );
not ( n20658 , n20654 );
and ( n20659 , n20657 , n20658 );
nor ( n20660 , n20656 , n20659 );
buf ( n20661 , n6204 );
nand ( n20662 , n6828 , n20661 );
buf ( n20663 , n6205 );
buf ( n20664 , n20663 );
and ( n20665 , n20662 , n20664 );
not ( n20666 , n20662 );
not ( n20667 , n20663 );
and ( n20668 , n20666 , n20667 );
nor ( n20669 , n20665 , n20668 );
xor ( n20670 , n20660 , n20669 );
buf ( n20671 , n6206 );
nand ( n20672 , n6916 , n20671 );
buf ( n20673 , n6207 );
buf ( n20674 , n20673 );
and ( n20675 , n20672 , n20674 );
not ( n20676 , n20672 );
not ( n20677 , n20673 );
and ( n20678 , n20676 , n20677 );
nor ( n20679 , n20675 , n20678 );
not ( n20680 , n20679 );
xor ( n20681 , n20670 , n20680 );
not ( n20682 , n20681 );
or ( n20683 , n20642 , n20682 );
or ( n20684 , n20681 , n7688 );
nand ( n20685 , n20683 , n20684 );
not ( n20686 , n20685 );
or ( n20687 , n20641 , n20686 );
or ( n20688 , n20685 , n20640 );
nand ( n20689 , n20687 , n20688 );
buf ( n20690 , n20689 );
not ( n20691 , n20690 );
buf ( n20692 , n6208 );
buf ( n20693 , n20692 );
not ( n20694 , n20693 );
not ( n20695 , n8234 );
not ( n20696 , n20695 );
or ( n20697 , n20694 , n20696 );
not ( n20698 , n20692 );
nand ( n20699 , n8234 , n20698 );
nand ( n20700 , n20697 , n20699 );
buf ( n20701 , n18560 );
not ( n20702 , n20701 );
and ( n20703 , n20700 , n20702 );
not ( n20704 , n20700 );
and ( n20705 , n20704 , n18573 );
nor ( n20706 , n20703 , n20705 );
nand ( n20707 , n20691 , n20706 );
not ( n20708 , n20707 );
buf ( n20709 , n12890 );
not ( n20710 , n20709 );
not ( n20711 , n6942 );
or ( n20712 , n20710 , n20711 );
or ( n20713 , n6942 , n20709 );
nand ( n20714 , n20712 , n20713 );
and ( n20715 , n20714 , n6893 );
not ( n20716 , n20714 );
and ( n20717 , n20716 , n6892 );
nor ( n20718 , n20715 , n20717 );
not ( n20719 , n20718 );
not ( n20720 , n20719 );
and ( n20721 , n20708 , n20720 );
and ( n20722 , n20707 , n20719 );
nor ( n20723 , n20721 , n20722 );
not ( n20724 , n20723 );
not ( n20725 , n6623 );
not ( n20726 , n10446 );
or ( n20727 , n20725 , n20726 );
not ( n20728 , n6623 );
nand ( n20729 , n20728 , n10443 );
nand ( n20730 , n20727 , n20729 );
buf ( n20731 , n6209 );
nand ( n20732 , n9160 , n20731 );
buf ( n20733 , n6210 );
buf ( n20734 , n20733 );
and ( n20735 , n20732 , n20734 );
not ( n20736 , n20732 );
not ( n20737 , n20733 );
and ( n20738 , n20736 , n20737 );
nor ( n20739 , n20735 , n20738 );
not ( n20740 , n20739 );
buf ( n20741 , n6211 );
nand ( n20742 , n7107 , n20741 );
buf ( n20743 , n6212 );
not ( n20744 , n20743 );
and ( n20745 , n20742 , n20744 );
not ( n20746 , n20742 );
buf ( n20747 , n20743 );
and ( n20748 , n20746 , n20747 );
nor ( n20749 , n20745 , n20748 );
not ( n20750 , n20749 );
or ( n20751 , n20740 , n20750 );
or ( n20752 , n20739 , n20749 );
nand ( n20753 , n20751 , n20752 );
buf ( n20754 , n6213 );
buf ( n20755 , n20754 );
not ( n20756 , n20755 );
buf ( n20757 , n6214 );
not ( n20758 , n20757 );
not ( n20759 , n20758 );
or ( n20760 , n20756 , n20759 );
not ( n20761 , n20754 );
buf ( n20762 , n20757 );
nand ( n20763 , n20761 , n20762 );
nand ( n20764 , n20760 , n20763 );
buf ( n20765 , n6215 );
not ( n20766 , n20765 );
and ( n20767 , n20764 , n20766 );
not ( n20768 , n20764 );
buf ( n20769 , n20765 );
and ( n20770 , n20768 , n20769 );
nor ( n20771 , n20767 , n20770 );
not ( n20772 , n20771 );
and ( n20773 , n20753 , n20772 );
not ( n20774 , n20753 );
and ( n20775 , n20774 , n20771 );
nor ( n20776 , n20773 , n20775 );
not ( n20777 , n20776 );
not ( n20778 , n20777 );
and ( n20779 , n20730 , n20778 );
not ( n20780 , n20730 );
xor ( n20781 , n20771 , n20739 );
xnor ( n20782 , n20781 , n20749 );
not ( n20783 , n20782 );
buf ( n20784 , n20783 );
not ( n20785 , n20784 );
and ( n20786 , n20780 , n20785 );
nor ( n20787 , n20779 , n20786 );
not ( n20788 , n20787 );
not ( n20789 , n13963 );
buf ( n20790 , n6216 );
buf ( n20791 , n20790 );
not ( n20792 , n20791 );
buf ( n20793 , n6217 );
not ( n20794 , n20793 );
not ( n20795 , n20794 );
or ( n20796 , n20792 , n20795 );
not ( n20797 , n20790 );
buf ( n20798 , n20793 );
nand ( n20799 , n20797 , n20798 );
nand ( n20800 , n20796 , n20799 );
buf ( n20801 , n6218 );
buf ( n20802 , n20801 );
and ( n20803 , n20800 , n20802 );
not ( n20804 , n20800 );
not ( n20805 , n20801 );
and ( n20806 , n20804 , n20805 );
nor ( n20807 , n20803 , n20806 );
buf ( n20808 , n6219 );
nand ( n20809 , n9160 , n20808 );
buf ( n20810 , n6220 );
buf ( n20811 , n20810 );
and ( n20812 , n20809 , n20811 );
not ( n20813 , n20809 );
not ( n20814 , n20810 );
and ( n20815 , n20813 , n20814 );
nor ( n20816 , n20812 , n20815 );
xor ( n20817 , n20807 , n20816 );
buf ( n20818 , n6221 );
nand ( n20819 , n8323 , n20818 );
buf ( n20820 , n6222 );
not ( n20821 , n20820 );
and ( n20822 , n20819 , n20821 );
not ( n20823 , n20819 );
buf ( n20824 , n20820 );
and ( n20825 , n20823 , n20824 );
nor ( n20826 , n20822 , n20825 );
xor ( n20827 , n20817 , n20826 );
not ( n20828 , n20827 );
not ( n20829 , n20828 );
not ( n20830 , n20829 );
or ( n20831 , n20789 , n20830 );
or ( n20832 , n20829 , n13963 );
nand ( n20833 , n20831 , n20832 );
and ( n20834 , n20833 , n19293 );
not ( n20835 , n20833 );
not ( n20836 , n19290 );
not ( n20837 , n20836 );
and ( n20838 , n20835 , n20837 );
nor ( n20839 , n20834 , n20838 );
nand ( n20840 , n20788 , n20839 );
not ( n20841 , n20840 );
xor ( n20842 , n16490 , n16009 );
not ( n20843 , n15937 );
xor ( n20844 , n15969 , n20843 );
xnor ( n20845 , n20844 , n18168 );
buf ( n20846 , n20845 );
xnor ( n20847 , n20842 , n20846 );
not ( n20848 , n20847 );
not ( n20849 , n20848 );
and ( n20850 , n20841 , n20849 );
and ( n20851 , n20840 , n20848 );
nor ( n20852 , n20850 , n20851 );
not ( n20853 , n20852 );
not ( n20854 , n20853 );
or ( n20855 , n20724 , n20854 );
not ( n20856 , n20723 );
nand ( n20857 , n20856 , n20852 );
nand ( n20858 , n20855 , n20857 );
xor ( n20859 , n20637 , n20858 );
not ( n20860 , n18926 );
not ( n20861 , n13457 );
or ( n20862 , n20860 , n20861 );
nand ( n20863 , n9989 , n18922 );
nand ( n20864 , n20862 , n20863 );
not ( n20865 , n20864 );
buf ( n20866 , n13832 );
not ( n20867 , n20866 );
and ( n20868 , n20865 , n20867 );
and ( n20869 , n20864 , n20866 );
nor ( n20870 , n20868 , n20869 );
and ( n20871 , n9283 , n16658 );
not ( n20872 , n9283 );
not ( n20873 , n16658 );
and ( n20874 , n20872 , n20873 );
nor ( n20875 , n20871 , n20874 );
and ( n20876 , n20875 , n16685 );
not ( n20877 , n20875 );
not ( n20878 , n16681 );
and ( n20879 , n20877 , n20878 );
nor ( n20880 , n20876 , n20879 );
not ( n20881 , n20880 );
nand ( n20882 , n20870 , n20881 );
buf ( n20883 , n15171 );
not ( n20884 , n20883 );
not ( n20885 , n19821 );
or ( n20886 , n20884 , n20885 );
or ( n20887 , n19826 , n20883 );
nand ( n20888 , n20886 , n20887 );
and ( n20889 , n20888 , n19829 );
not ( n20890 , n20888 );
and ( n20891 , n20890 , n19833 );
nor ( n20892 , n20889 , n20891 );
not ( n20893 , n20892 );
and ( n20894 , n20882 , n20893 );
not ( n20895 , n20882 );
and ( n20896 , n20895 , n20892 );
nor ( n20897 , n20894 , n20896 );
not ( n20898 , n20897 );
not ( n20899 , n20898 );
buf ( n20900 , n6223 );
buf ( n20901 , n20900 );
not ( n20902 , n20901 );
not ( n20903 , n12375 );
not ( n20904 , n20903 );
or ( n20905 , n20902 , n20904 );
not ( n20906 , n20901 );
nand ( n20907 , n20906 , n19006 );
nand ( n20908 , n20905 , n20907 );
not ( n20909 , n19045 );
and ( n20910 , n20908 , n20909 );
not ( n20911 , n20908 );
not ( n20912 , n19041 );
not ( n20913 , n20912 );
and ( n20914 , n20911 , n20913 );
nor ( n20915 , n20910 , n20914 );
not ( n20916 , n7963 );
not ( n20917 , n14540 );
not ( n20918 , n20917 );
or ( n20919 , n20916 , n20918 );
or ( n20920 , n20917 , n7963 );
nand ( n20921 , n20919 , n20920 );
and ( n20922 , n20921 , n15701 );
not ( n20923 , n20921 );
and ( n20924 , n20923 , n14508 );
nor ( n20925 , n20922 , n20924 );
buf ( n20926 , n20925 );
nand ( n20927 , n20915 , n20926 );
not ( n20928 , n20927 );
buf ( n20929 , n11435 );
and ( n20930 , n20929 , n6791 );
not ( n20931 , n20929 );
and ( n20932 , n20931 , n20438 );
nor ( n20933 , n20930 , n20932 );
not ( n20934 , n20933 );
not ( n20935 , n20462 );
or ( n20936 , n20934 , n20935 );
not ( n20937 , n20462 );
not ( n20938 , n20937 );
or ( n20939 , n20938 , n20933 );
nand ( n20940 , n20936 , n20939 );
buf ( n20941 , n20940 );
not ( n20942 , n20941 );
and ( n20943 , n20928 , n20942 );
and ( n20944 , n20927 , n20941 );
nor ( n20945 , n20943 , n20944 );
not ( n20946 , n20945 );
not ( n20947 , n20946 );
or ( n20948 , n20899 , n20947 );
nand ( n20949 , n20945 , n20897 );
nand ( n20950 , n20948 , n20949 );
xor ( n20951 , n20859 , n20950 );
buf ( n20952 , n20951 );
and ( n20953 , n20546 , n20952 );
not ( n20954 , n20546 );
not ( n20955 , n20858 );
not ( n20956 , n20955 );
not ( n20957 , n20637 );
and ( n20958 , n20950 , n20957 );
not ( n20959 , n20950 );
and ( n20960 , n20959 , n20637 );
nor ( n20961 , n20958 , n20960 );
not ( n20962 , n20961 );
or ( n20963 , n20956 , n20962 );
not ( n20964 , n20961 );
nand ( n20965 , n20964 , n20858 );
nand ( n20966 , n20963 , n20965 );
buf ( n20967 , n20966 );
and ( n20968 , n20954 , n20967 );
nor ( n20969 , n20953 , n20968 );
not ( n20970 , n20969 );
and ( n20971 , n19869 , n20970 );
not ( n20972 , n19869 );
and ( n20973 , n20972 , n20969 );
nor ( n20974 , n20971 , n20973 );
buf ( n20975 , n15324 );
buf ( n20976 , n20975 );
buf ( n20977 , n20976 );
or ( n20978 , n20974 , n20977 );
nand ( n20979 , n17822 , n20978 );
buf ( n20980 , n20979 );
buf ( n20981 , n20980 );
not ( n20982 , n15207 );
buf ( n20983 , n13352 );
buf ( n20984 , n20983 );
not ( n20985 , n20984 );
or ( n20986 , n20982 , n20985 );
buf ( n20987 , n14435 );
not ( n20988 , n20987 );
not ( n20989 , n20988 );
not ( n20990 , n8186 );
or ( n20991 , n20989 , n20990 );
nand ( n20992 , n8192 , n20987 );
nand ( n20993 , n20991 , n20992 );
not ( n20994 , n20993 );
not ( n20995 , n8233 );
not ( n20996 , n20995 );
and ( n20997 , n20994 , n20996 );
and ( n20998 , n20993 , n20995 );
nor ( n20999 , n20997 , n20998 );
not ( n21000 , n20999 );
nand ( n21001 , n10404 , n21000 );
not ( n21002 , n21001 );
not ( n21003 , n10316 );
not ( n21004 , n21003 );
or ( n21005 , n21002 , n21004 );
or ( n21006 , n21003 , n21001 );
nand ( n21007 , n21005 , n21006 );
not ( n21008 , n21007 );
not ( n21009 , n10463 );
or ( n21010 , n21008 , n21009 );
not ( n21011 , n21007 );
nand ( n21012 , n21011 , n10472 );
nand ( n21013 , n21010 , n21012 );
and ( n21014 , n21013 , n11293 );
not ( n21015 , n21013 );
and ( n21016 , n21015 , n11302 );
nor ( n21017 , n21014 , n21016 );
not ( n21018 , n21017 );
not ( n21019 , n9518 );
not ( n21020 , n21019 );
not ( n21021 , n18129 );
not ( n21022 , n16147 );
or ( n21023 , n21021 , n21022 );
or ( n21024 , n16147 , n18129 );
nand ( n21025 , n21023 , n21024 );
not ( n21026 , n21025 );
or ( n21027 , n21020 , n21026 );
or ( n21028 , n21025 , n21019 );
nand ( n21029 , n21027 , n21028 );
not ( n21030 , n21029 );
not ( n21031 , n13550 );
buf ( n21032 , n6224 );
nand ( n21033 , n8675 , n21032 );
buf ( n21034 , n6225 );
buf ( n21035 , n21034 );
and ( n21036 , n21033 , n21035 );
not ( n21037 , n21033 );
not ( n21038 , n21034 );
and ( n21039 , n21037 , n21038 );
nor ( n21040 , n21036 , n21039 );
buf ( n21041 , n21040 );
not ( n21042 , n21041 );
not ( n21043 , n21042 );
not ( n21044 , n13591 );
or ( n21045 , n21043 , n21044 );
nand ( n21046 , n13595 , n21041 );
nand ( n21047 , n21045 , n21046 );
not ( n21048 , n21047 );
and ( n21049 , n21031 , n21048 );
and ( n21050 , n13550 , n21047 );
nor ( n21051 , n21049 , n21050 );
not ( n21052 , n21051 );
nand ( n21053 , n21030 , n21052 );
not ( n21054 , n21053 );
not ( n21055 , n9099 );
not ( n21056 , n19199 );
or ( n21057 , n21055 , n21056 );
or ( n21058 , n19199 , n9099 );
nand ( n21059 , n21057 , n21058 );
buf ( n21060 , n19662 );
and ( n21061 , n21059 , n21060 );
not ( n21062 , n21059 );
buf ( n21063 , n19666 );
and ( n21064 , n21062 , n21063 );
nor ( n21065 , n21061 , n21064 );
not ( n21066 , n21065 );
not ( n21067 , n21066 );
and ( n21068 , n21054 , n21067 );
and ( n21069 , n21053 , n21066 );
nor ( n21070 , n21068 , n21069 );
not ( n21071 , n21070 );
nand ( n21072 , n21065 , n21029 );
not ( n21073 , n21072 );
not ( n21074 , n12206 );
not ( n21075 , n20053 );
not ( n21076 , n12216 );
or ( n21077 , n21075 , n21076 );
or ( n21078 , n12216 , n20053 );
nand ( n21079 , n21077 , n21078 );
not ( n21080 , n21079 );
not ( n21081 , n12231 );
not ( n21082 , n21081 );
or ( n21083 , n21080 , n21082 );
or ( n21084 , n21081 , n21079 );
nand ( n21085 , n21083 , n21084 );
not ( n21086 , n21085 );
and ( n21087 , n21074 , n21086 );
and ( n21088 , n21085 , n12206 );
nor ( n21089 , n21087 , n21088 );
not ( n21090 , n21089 );
not ( n21091 , n21090 );
and ( n21092 , n21073 , n21091 );
and ( n21093 , n21072 , n21090 );
nor ( n21094 , n21092 , n21093 );
not ( n21095 , n21094 );
buf ( n21096 , n6226 );
buf ( n21097 , n21096 );
not ( n21098 , n21097 );
not ( n21099 , n8042 );
or ( n21100 , n21098 , n21099 );
or ( n21101 , n8042 , n21097 );
nand ( n21102 , n21100 , n21101 );
not ( n21103 , n21102 );
not ( n21104 , n21103 );
not ( n21105 , n7992 );
or ( n21106 , n21104 , n21105 );
nand ( n21107 , n7993 , n21102 );
nand ( n21108 , n21106 , n21107 );
not ( n21109 , n21108 );
not ( n21110 , n14092 );
not ( n21111 , n21110 );
not ( n21112 , n6668 );
and ( n21113 , n21111 , n21112 );
and ( n21114 , n21110 , n6668 );
nor ( n21115 , n21113 , n21114 );
buf ( n21116 , n6227 );
buf ( n21117 , n21116 );
not ( n21118 , n21117 );
buf ( n21119 , n6228 );
not ( n21120 , n21119 );
not ( n21121 , n21120 );
or ( n21122 , n21118 , n21121 );
not ( n21123 , n21116 );
buf ( n21124 , n21119 );
nand ( n21125 , n21123 , n21124 );
nand ( n21126 , n21122 , n21125 );
buf ( n21127 , n6229 );
not ( n21128 , n21127 );
and ( n21129 , n21126 , n21128 );
not ( n21130 , n21126 );
buf ( n21131 , n21127 );
and ( n21132 , n21130 , n21131 );
nor ( n21133 , n21129 , n21132 );
xor ( n21134 , n21133 , n16298 );
buf ( n21135 , n6230 );
nand ( n21136 , n10165 , n21135 );
buf ( n21137 , n6231 );
buf ( n21138 , n21137 );
and ( n21139 , n21136 , n21138 );
not ( n21140 , n21136 );
not ( n21141 , n21137 );
and ( n21142 , n21140 , n21141 );
nor ( n21143 , n21139 , n21142 );
not ( n21144 , n21143 );
xnor ( n21145 , n21134 , n21144 );
buf ( n21146 , n21145 );
and ( n21147 , n21115 , n21146 );
not ( n21148 , n21115 );
not ( n21149 , n21145 );
and ( n21150 , n21148 , n21149 );
nor ( n21151 , n21147 , n21150 );
nand ( n21152 , n21109 , n21151 );
not ( n21153 , n20089 );
and ( n21154 , n12725 , n15833 );
not ( n21155 , n12725 );
and ( n21156 , n21155 , n15839 );
nor ( n21157 , n21154 , n21156 );
not ( n21158 , n21157 );
not ( n21159 , n21158 );
or ( n21160 , n21153 , n21159 );
nand ( n21161 , n21157 , n20088 );
nand ( n21162 , n21160 , n21161 );
not ( n21163 , n21162 );
and ( n21164 , n21152 , n21163 );
not ( n21165 , n21152 );
and ( n21166 , n21165 , n21162 );
nor ( n21167 , n21164 , n21166 );
not ( n21168 , n21167 );
or ( n21169 , n21095 , n21168 );
or ( n21170 , n21167 , n21094 );
nand ( n21171 , n21169 , n21170 );
not ( n21172 , n12505 );
not ( n21173 , n10126 );
or ( n21174 , n21172 , n21173 );
not ( n21175 , n12505 );
nand ( n21176 , n21175 , n10491 );
nand ( n21177 , n21174 , n21176 );
not ( n21178 , n21177 );
not ( n21179 , n18528 );
and ( n21180 , n21178 , n21179 );
and ( n21181 , n21177 , n18528 );
nor ( n21182 , n21180 , n21181 );
buf ( n21183 , n6232 );
buf ( n21184 , n21183 );
nor ( n21185 , n7923 , n21184 );
not ( n21186 , n21185 );
nand ( n21187 , n7927 , n21184 );
nand ( n21188 , n21186 , n21187 );
not ( n21189 , n7879 );
and ( n21190 , n21188 , n21189 );
not ( n21191 , n21188 );
and ( n21192 , n21191 , n7879 );
nor ( n21193 , n21190 , n21192 );
nand ( n21194 , n21182 , n21193 );
not ( n21195 , n20451 );
not ( n21196 , n12636 );
or ( n21197 , n21195 , n21196 );
or ( n21198 , n12636 , n20451 );
nand ( n21199 , n21197 , n21198 );
buf ( n21200 , n19747 );
and ( n21201 , n21199 , n21200 );
not ( n21202 , n21199 );
buf ( n21203 , n19739 );
and ( n21204 , n21202 , n21203 );
nor ( n21205 , n21201 , n21204 );
not ( n21206 , n21205 );
and ( n21207 , n21194 , n21206 );
not ( n21208 , n21194 );
and ( n21209 , n21208 , n21205 );
nor ( n21210 , n21207 , n21209 );
and ( n21211 , n21171 , n21210 );
not ( n21212 , n21171 );
not ( n21213 , n21210 );
and ( n21214 , n21212 , n21213 );
nor ( n21215 , n21211 , n21214 );
not ( n21216 , n21215 );
not ( n21217 , n15291 );
xor ( n21218 , n19328 , n21217 );
buf ( n21219 , n6233 );
buf ( n21220 , n21219 );
not ( n21221 , n21220 );
buf ( n21222 , n6234 );
not ( n21223 , n21222 );
not ( n21224 , n21223 );
or ( n21225 , n21221 , n21224 );
not ( n21226 , n21219 );
buf ( n21227 , n21222 );
nand ( n21228 , n21226 , n21227 );
nand ( n21229 , n21225 , n21228 );
not ( n21230 , n21229 );
buf ( n21231 , n6235 );
nand ( n21232 , n6634 , n21231 );
buf ( n21233 , n6236 );
buf ( n21234 , n21233 );
and ( n21235 , n21232 , n21234 );
not ( n21236 , n21232 );
not ( n21237 , n21233 );
and ( n21238 , n21236 , n21237 );
nor ( n21239 , n21235 , n21238 );
not ( n21240 , n21239 );
buf ( n21241 , n6237 );
nand ( n21242 , n6647 , n21241 );
buf ( n21243 , n6238 );
buf ( n21244 , n21243 );
and ( n21245 , n21242 , n21244 );
not ( n21246 , n21242 );
not ( n21247 , n21243 );
and ( n21248 , n21246 , n21247 );
nor ( n21249 , n21245 , n21248 );
not ( n21250 , n21249 );
not ( n21251 , n21250 );
or ( n21252 , n21240 , n21251 );
not ( n21253 , n21239 );
nand ( n21254 , n21249 , n21253 );
nand ( n21255 , n21252 , n21254 );
buf ( n21256 , n6239 );
buf ( n21257 , n21256 );
and ( n21258 , n21255 , n21257 );
not ( n21259 , n21255 );
not ( n21260 , n21256 );
and ( n21261 , n21259 , n21260 );
nor ( n21262 , n21258 , n21261 );
and ( n21263 , n21230 , n21262 );
not ( n21264 , n21230 );
not ( n21265 , n21262 );
and ( n21266 , n21264 , n21265 );
nor ( n21267 , n21263 , n21266 );
not ( n21268 , n21267 );
xnor ( n21269 , n21218 , n21268 );
not ( n21270 , n11307 );
not ( n21271 , n21270 );
not ( n21272 , n8524 );
not ( n21273 , n11348 );
or ( n21274 , n21272 , n21273 );
or ( n21275 , n11348 , n8524 );
nand ( n21276 , n21274 , n21275 );
not ( n21277 , n21276 );
or ( n21278 , n21271 , n21277 );
or ( n21279 , n21276 , n21270 );
nand ( n21280 , n21278 , n21279 );
nand ( n21281 , n21269 , n21280 );
not ( n21282 , n21281 );
not ( n21283 , n13246 );
not ( n21284 , n14794 );
or ( n21285 , n21283 , n21284 );
nand ( n21286 , n14799 , n13242 );
nand ( n21287 , n21285 , n21286 );
not ( n21288 , n21287 );
not ( n21289 , n14847 );
and ( n21290 , n21288 , n21289 );
and ( n21291 , n21287 , n14847 );
nor ( n21292 , n21290 , n21291 );
not ( n21293 , n21292 );
not ( n21294 , n21293 );
and ( n21295 , n21282 , n21294 );
nand ( n21296 , n21269 , n21280 );
and ( n21297 , n21296 , n21293 );
nor ( n21298 , n21295 , n21297 );
not ( n21299 , n21298 );
buf ( n21300 , n6240 );
buf ( n21301 , n21300 );
xor ( n21302 , n21301 , n20428 );
not ( n21303 , n7665 );
not ( n21304 , n21303 );
xor ( n21305 , n21302 , n21304 );
not ( n21306 , n14564 );
not ( n21307 , n7720 );
or ( n21308 , n21306 , n21307 );
not ( n21309 , n7719 );
nand ( n21310 , n21309 , n14558 );
nand ( n21311 , n21308 , n21310 );
not ( n21312 , n21311 );
not ( n21313 , n15237 );
not ( n21314 , n21313 );
and ( n21315 , n21312 , n21314 );
and ( n21316 , n21311 , n21313 );
nor ( n21317 , n21315 , n21316 );
nand ( n21318 , n21305 , n21317 );
not ( n21319 , n17098 );
not ( n21320 , n21319 );
not ( n21321 , n21320 );
buf ( n21322 , n6241 );
buf ( n21323 , n21322 );
not ( n21324 , n21323 );
buf ( n21325 , n6242 );
not ( n21326 , n21325 );
not ( n21327 , n21326 );
or ( n21328 , n21324 , n21327 );
not ( n21329 , n21322 );
buf ( n21330 , n21325 );
nand ( n21331 , n21329 , n21330 );
nand ( n21332 , n21328 , n21331 );
buf ( n21333 , n6243 );
not ( n21334 , n21333 );
and ( n21335 , n21332 , n21334 );
not ( n21336 , n21332 );
buf ( n21337 , n21333 );
and ( n21338 , n21336 , n21337 );
nor ( n21339 , n21335 , n21338 );
buf ( n21340 , n6244 );
nand ( n21341 , n7202 , n21340 );
buf ( n21342 , n6245 );
buf ( n21343 , n21342 );
and ( n21344 , n21341 , n21343 );
not ( n21345 , n21341 );
not ( n21346 , n21342 );
and ( n21347 , n21345 , n21346 );
nor ( n21348 , n21344 , n21347 );
xor ( n21349 , n21339 , n21348 );
buf ( n21350 , n6246 );
nand ( n21351 , n6605 , n21350 );
buf ( n21352 , n6247 );
not ( n21353 , n21352 );
and ( n21354 , n21351 , n21353 );
not ( n21355 , n21351 );
buf ( n21356 , n21352 );
and ( n21357 , n21355 , n21356 );
nor ( n21358 , n21354 , n21357 );
xnor ( n21359 , n21349 , n21358 );
not ( n21360 , n21359 );
not ( n21361 , n21360 );
not ( n21362 , n21361 );
buf ( n21363 , n6248 );
buf ( n21364 , n21363 );
not ( n21365 , n21364 );
and ( n21366 , n21362 , n21365 );
and ( n21367 , n21361 , n21364 );
nor ( n21368 , n21366 , n21367 );
not ( n21369 , n21368 );
and ( n21370 , n21321 , n21369 );
and ( n21371 , n21320 , n21368 );
nor ( n21372 , n21370 , n21371 );
and ( n21373 , n21318 , n21372 );
not ( n21374 , n21318 );
not ( n21375 , n21372 );
and ( n21376 , n21374 , n21375 );
nor ( n21377 , n21373 , n21376 );
not ( n21378 , n21377 );
nand ( n21379 , n21299 , n21378 );
nand ( n21380 , n21298 , n21377 );
nand ( n21381 , n21379 , n21380 );
not ( n21382 , n21381 );
not ( n21383 , n21382 );
or ( n21384 , n21216 , n21383 );
not ( n21385 , n21215 );
nand ( n21386 , n21385 , n21381 );
nand ( n21387 , n21384 , n21386 );
not ( n21388 , n21387 );
or ( n21389 , n21071 , n21388 );
or ( n21390 , n21387 , n21070 );
nand ( n21391 , n21389 , n21390 );
not ( n21392 , n13977 );
not ( n21393 , n20827 );
or ( n21394 , n21392 , n21393 );
not ( n21395 , n13977 );
not ( n21396 , n20827 );
nand ( n21397 , n21395 , n21396 );
nand ( n21398 , n21394 , n21397 );
and ( n21399 , n21398 , n19290 );
not ( n21400 , n21398 );
and ( n21401 , n21400 , n19293 );
nor ( n21402 , n21399 , n21401 );
not ( n21403 , n21402 );
not ( n21404 , n21403 );
not ( n21405 , n14683 );
buf ( n21406 , n11270 );
not ( n21407 , n21406 );
and ( n21408 , n21405 , n21407 );
and ( n21409 , n14683 , n21406 );
nor ( n21410 , n21408 , n21409 );
xor ( n21411 , n14651 , n21410 );
buf ( n21412 , n18705 );
not ( n21413 , n21412 );
not ( n21414 , n10842 );
not ( n21415 , n21414 );
not ( n21416 , n21097 );
buf ( n21417 , n6249 );
not ( n21418 , n21417 );
not ( n21419 , n21418 );
or ( n21420 , n21416 , n21419 );
not ( n21421 , n21096 );
buf ( n21422 , n21417 );
nand ( n21423 , n21421 , n21422 );
nand ( n21424 , n21420 , n21423 );
buf ( n21425 , n6250 );
not ( n21426 , n21425 );
and ( n21427 , n21424 , n21426 );
not ( n21428 , n21424 );
buf ( n21429 , n21425 );
and ( n21430 , n21428 , n21429 );
nor ( n21431 , n21427 , n21430 );
buf ( n21432 , n6251 );
nand ( n21433 , n7606 , n21432 );
buf ( n21434 , n6252 );
buf ( n21435 , n21434 );
and ( n21436 , n21433 , n21435 );
not ( n21437 , n21433 );
not ( n21438 , n21434 );
and ( n21439 , n21437 , n21438 );
nor ( n21440 , n21436 , n21439 );
xor ( n21441 , n21431 , n21440 );
xnor ( n21442 , n21441 , n8002 );
not ( n21443 , n21442 );
not ( n21444 , n21443 );
not ( n21445 , n21444 );
or ( n21446 , n21415 , n21445 );
not ( n21447 , n21442 );
nand ( n21448 , n21447 , n10843 );
nand ( n21449 , n21446 , n21448 );
not ( n21450 , n21449 );
or ( n21451 , n21413 , n21450 );
not ( n21452 , n18705 );
not ( n21453 , n21452 );
or ( n21454 , n21449 , n21453 );
nand ( n21455 , n21451 , n21454 );
nand ( n21456 , n21411 , n21455 );
not ( n21457 , n21456 );
or ( n21458 , n21404 , n21457 );
or ( n21459 , n21456 , n21403 );
nand ( n21460 , n21458 , n21459 );
not ( n21461 , n21460 );
buf ( n21462 , n8535 );
not ( n21463 , n21462 );
not ( n21464 , n11335 );
xor ( n21465 , n11326 , n21464 );
xnor ( n21466 , n21465 , n11346 );
not ( n21467 , n21466 );
or ( n21468 , n21463 , n21467 );
or ( n21469 , n21466 , n21462 );
nand ( n21470 , n21468 , n21469 );
xor ( n21471 , n11307 , n21470 );
buf ( n21472 , n15904 );
not ( n21473 , n21472 );
not ( n21474 , n10036 );
or ( n21475 , n21473 , n21474 );
not ( n21476 , n21472 );
nand ( n21477 , n21476 , n8977 );
nand ( n21478 , n21475 , n21477 );
and ( n21479 , n21478 , n7540 );
not ( n21480 , n21478 );
and ( n21481 , n21480 , n8986 );
nor ( n21482 , n21479 , n21481 );
nand ( n21483 , n21471 , n21482 );
not ( n21484 , n21483 );
not ( n21485 , n10276 );
not ( n21486 , n20077 );
or ( n21487 , n21485 , n21486 );
not ( n21488 , n10276 );
nand ( n21489 , n21488 , n20071 );
nand ( n21490 , n21487 , n21489 );
buf ( n21491 , n16661 );
and ( n21492 , n21490 , n21491 );
not ( n21493 , n21490 );
not ( n21494 , n21491 );
and ( n21495 , n21493 , n21494 );
nor ( n21496 , n21492 , n21495 );
not ( n21497 , n21496 );
and ( n21498 , n21484 , n21497 );
and ( n21499 , n21483 , n21496 );
nor ( n21500 , n21498 , n21499 );
not ( n21501 , n21500 );
or ( n21502 , n21461 , n21501 );
or ( n21503 , n21460 , n21500 );
nand ( n21504 , n21502 , n21503 );
buf ( n21505 , n6253 );
buf ( n21506 , n21505 );
not ( n21507 , n21506 );
not ( n21508 , n7881 );
not ( n21509 , n21508 );
or ( n21510 , n21507 , n21509 );
not ( n21511 , n21505 );
nand ( n21512 , n21511 , n7882 );
nand ( n21513 , n21510 , n21512 );
xor ( n21514 , n21184 , n21513 );
buf ( n21515 , n6254 );
nand ( n21516 , n8537 , n21515 );
buf ( n21517 , n6255 );
buf ( n21518 , n21517 );
and ( n21519 , n21516 , n21518 );
not ( n21520 , n21516 );
not ( n21521 , n21517 );
and ( n21522 , n21520 , n21521 );
nor ( n21523 , n21519 , n21522 );
not ( n21524 , n21523 );
buf ( n21525 , n6256 );
nand ( n21526 , n6815 , n21525 );
buf ( n21527 , n6257 );
buf ( n21528 , n21527 );
and ( n21529 , n21526 , n21528 );
not ( n21530 , n21526 );
not ( n21531 , n21527 );
and ( n21532 , n21530 , n21531 );
nor ( n21533 , n21529 , n21532 );
not ( n21534 , n21533 );
not ( n21535 , n21534 );
or ( n21536 , n21524 , n21535 );
not ( n21537 , n21523 );
nand ( n21538 , n21533 , n21537 );
nand ( n21539 , n21536 , n21538 );
xnor ( n21540 , n21514 , n21539 );
not ( n21541 , n21540 );
buf ( n21542 , n7578 );
not ( n21543 , n21542 );
not ( n21544 , n14942 );
or ( n21545 , n21543 , n21544 );
or ( n21546 , n14942 , n21542 );
nand ( n21547 , n21545 , n21546 );
not ( n21548 , n21547 );
or ( n21549 , n21541 , n21548 );
or ( n21550 , n21547 , n21540 );
nand ( n21551 , n21549 , n21550 );
not ( n21552 , n21551 );
not ( n21553 , n9124 );
not ( n21554 , n19204 );
or ( n21555 , n21553 , n21554 );
or ( n21556 , n19204 , n9124 );
nand ( n21557 , n21555 , n21556 );
and ( n21558 , n21557 , n21060 );
not ( n21559 , n21557 );
and ( n21560 , n21559 , n21063 );
nor ( n21561 , n21558 , n21560 );
not ( n21562 , n21561 );
nand ( n21563 , n21552 , n21562 );
not ( n21564 , n21563 );
not ( n21565 , n17452 );
not ( n21566 , n13445 );
not ( n21567 , n21566 );
or ( n21568 , n21565 , n21567 );
or ( n21569 , n21566 , n17452 );
nand ( n21570 , n21568 , n21569 );
and ( n21571 , n21570 , n17908 );
not ( n21572 , n21570 );
and ( n21573 , n21572 , n13399 );
nor ( n21574 , n21571 , n21573 );
buf ( n21575 , n21574 );
not ( n21576 , n21575 );
and ( n21577 , n21564 , n21576 );
and ( n21578 , n21563 , n21575 );
nor ( n21579 , n21577 , n21578 );
and ( n21580 , n21504 , n21579 );
not ( n21581 , n21504 );
not ( n21582 , n21579 );
and ( n21583 , n21581 , n21582 );
nor ( n21584 , n21580 , n21583 );
not ( n21585 , n21584 );
buf ( n21586 , n6837 );
not ( n21587 , n12591 );
xor ( n21588 , n21586 , n21587 );
xnor ( n21589 , n21588 , n14393 );
not ( n21590 , n21589 );
not ( n21591 , n19589 );
not ( n21592 , n19592 );
or ( n21593 , n21591 , n21592 );
or ( n21594 , n19592 , n19589 );
nand ( n21595 , n21593 , n21594 );
not ( n21596 , n21595 );
buf ( n21597 , n6258 );
buf ( n21598 , n21597 );
not ( n21599 , n21598 );
not ( n21600 , n13596 );
or ( n21601 , n21599 , n21600 );
not ( n21602 , n21597 );
nand ( n21603 , n21602 , n13553 );
nand ( n21604 , n21601 , n21603 );
buf ( n21605 , n6259 );
not ( n21606 , n21605 );
and ( n21607 , n21604 , n21606 );
not ( n21608 , n21604 );
buf ( n21609 , n21605 );
and ( n21610 , n21608 , n21609 );
nor ( n21611 , n21607 , n21610 );
buf ( n21612 , n6260 );
nand ( n21613 , n6577 , n21612 );
buf ( n21614 , n6261 );
buf ( n21615 , n21614 );
and ( n21616 , n21613 , n21615 );
not ( n21617 , n21613 );
not ( n21618 , n21614 );
and ( n21619 , n21617 , n21618 );
nor ( n21620 , n21616 , n21619 );
xor ( n21621 , n21611 , n21620 );
xnor ( n21622 , n21621 , n21040 );
nor ( n21623 , n21596 , n21622 );
not ( n21624 , n21623 );
not ( n21625 , n21595 );
nand ( n21626 , n21625 , n21622 );
nand ( n21627 , n21624 , n21626 );
buf ( n21628 , n11175 );
not ( n21629 , n21628 );
and ( n21630 , n21627 , n21629 );
not ( n21631 , n21627 );
not ( n21632 , n11174 );
and ( n21633 , n21631 , n21632 );
nor ( n21634 , n21630 , n21633 );
not ( n21635 , n21634 );
nand ( n21636 , n21590 , n21635 );
not ( n21637 , n17310 );
not ( n21638 , n12442 );
or ( n21639 , n21637 , n21638 );
or ( n21640 , n12442 , n17310 );
nand ( n21641 , n21639 , n21640 );
and ( n21642 , n21641 , n12462 );
not ( n21643 , n21641 );
and ( n21644 , n21643 , n12466 );
nor ( n21645 , n21642 , n21644 );
xor ( n21646 , n21636 , n21645 );
not ( n21647 , n21646 );
buf ( n21648 , n15974 );
xor ( n21649 , n16474 , n21648 );
not ( n21650 , n16009 );
xnor ( n21651 , n21649 , n21650 );
not ( n21652 , n21651 );
not ( n21653 , n21652 );
xor ( n21654 , n16744 , n21309 );
xor ( n21655 , n21654 , n7756 );
not ( n21656 , n21655 );
buf ( n21657 , n21533 );
not ( n21658 , n21657 );
not ( n21659 , n7926 );
or ( n21660 , n21658 , n21659 );
or ( n21661 , n7926 , n21657 );
nand ( n21662 , n21660 , n21661 );
not ( n21663 , n21662 );
not ( n21664 , n7879 );
and ( n21665 , n21663 , n21664 );
and ( n21666 , n21662 , n7879 );
nor ( n21667 , n21665 , n21666 );
nand ( n21668 , n21656 , n21667 );
not ( n21669 , n21668 );
or ( n21670 , n21653 , n21669 );
not ( n21671 , n21667 );
not ( n21672 , n21671 );
nand ( n21673 , n21672 , n21656 );
or ( n21674 , n21673 , n21652 );
nand ( n21675 , n21670 , n21674 );
not ( n21676 , n21675 );
or ( n21677 , n21647 , n21676 );
or ( n21678 , n21675 , n21646 );
nand ( n21679 , n21677 , n21678 );
not ( n21680 , n21679 );
and ( n21681 , n21585 , n21680 );
and ( n21682 , n21584 , n21679 );
nor ( n21683 , n21681 , n21682 );
buf ( n21684 , n21683 );
buf ( n21685 , n21684 );
and ( n21686 , n21391 , n21685 );
not ( n21687 , n21391 );
not ( n21688 , n21685 );
and ( n21689 , n21687 , n21688 );
nor ( n21690 , n21686 , n21689 );
nand ( n21691 , n21018 , n21690 );
not ( n21692 , n21691 );
not ( n21693 , n13549 );
not ( n21694 , n21693 );
not ( n21695 , n21453 );
not ( n21696 , n10829 );
not ( n21697 , n21447 );
or ( n21698 , n21696 , n21697 );
not ( n21699 , n21447 );
not ( n21700 , n10828 );
nand ( n21701 , n21699 , n21700 );
nand ( n21702 , n21698 , n21701 );
not ( n21703 , n21702 );
or ( n21704 , n21695 , n21703 );
buf ( n21705 , n18705 );
or ( n21706 , n21702 , n21705 );
nand ( n21707 , n21704 , n21706 );
nand ( n21708 , n13602 , n21707 );
not ( n21709 , n21708 );
or ( n21710 , n21694 , n21709 );
or ( n21711 , n21708 , n21693 );
nand ( n21712 , n21710 , n21711 );
not ( n21713 , n21712 );
not ( n21714 , n21713 );
not ( n21715 , n14334 );
not ( n21716 , n21715 );
or ( n21717 , n21714 , n21716 );
not ( n21718 , n14334 );
or ( n21719 , n21718 , n21713 );
nand ( n21720 , n21717 , n21719 );
and ( n21721 , n21720 , n15319 );
not ( n21722 , n21720 );
not ( n21723 , n15313 );
not ( n21724 , n14863 );
or ( n21725 , n21723 , n21724 );
or ( n21726 , n14863 , n15313 );
nand ( n21727 , n21725 , n21726 );
buf ( n21728 , n21727 );
and ( n21729 , n21722 , n21728 );
nor ( n21730 , n21721 , n21729 );
not ( n21731 , n21730 );
not ( n21732 , n21731 );
and ( n21733 , n21692 , n21732 );
and ( n21734 , n21691 , n21731 );
nor ( n21735 , n21733 , n21734 );
not ( n21736 , n15324 );
buf ( n21737 , n21736 );
not ( n21738 , n21737 );
or ( n21739 , n21735 , n21738 );
nand ( n21740 , n20986 , n21739 );
buf ( n21741 , n21740 );
buf ( n21742 , n21741 );
not ( n21743 , n12124 );
buf ( n21744 , n13353 );
not ( n21745 , n21744 );
or ( n21746 , n21743 , n21745 );
buf ( n21747 , n12624 );
not ( n21748 , n21747 );
buf ( n21749 , n6262 );
buf ( n21750 , n21749 );
not ( n21751 , n21750 );
not ( n21752 , n18874 );
or ( n21753 , n21751 , n21752 );
not ( n21754 , n21749 );
nand ( n21755 , n21754 , n18870 );
nand ( n21756 , n21753 , n21755 );
not ( n21757 , n15644 );
and ( n21758 , n21756 , n21757 );
not ( n21759 , n21756 );
and ( n21760 , n21759 , n15645 );
nor ( n21761 , n21758 , n21760 );
buf ( n21762 , n6263 );
nand ( n21763 , n10372 , n21762 );
buf ( n21764 , n6264 );
buf ( n21765 , n21764 );
and ( n21766 , n21763 , n21765 );
not ( n21767 , n21763 );
not ( n21768 , n21764 );
and ( n21769 , n21767 , n21768 );
nor ( n21770 , n21766 , n21769 );
xor ( n21771 , n21761 , n21770 );
xnor ( n21772 , n21771 , n18454 );
not ( n21773 , n21772 );
or ( n21774 , n21748 , n21773 );
or ( n21775 , n21772 , n21747 );
nand ( n21776 , n21774 , n21775 );
not ( n21777 , n21776 );
not ( n21778 , n21777 );
buf ( n21779 , n6265 );
buf ( n21780 , n21779 );
not ( n21781 , n12469 );
buf ( n21782 , n6266 );
buf ( n21783 , n21782 );
and ( n21784 , n21781 , n21783 );
not ( n21785 , n21781 );
not ( n21786 , n21782 );
and ( n21787 , n21785 , n21786 );
nor ( n21788 , n21784 , n21787 );
xor ( n21789 , n21780 , n21788 );
buf ( n21790 , n6267 );
buf ( n21791 , n6268 );
xor ( n21792 , n21790 , n21791 );
buf ( n21793 , n6269 );
nand ( n21794 , n11337 , n21793 );
xnor ( n21795 , n21792 , n21794 );
xnor ( n21796 , n21789 , n21795 );
buf ( n21797 , n21796 );
not ( n21798 , n21797 );
or ( n21799 , n21778 , n21798 );
not ( n21800 , n21779 );
xor ( n21801 , n21800 , n21788 );
xnor ( n21802 , n21801 , n21795 );
buf ( n21803 , n21802 );
nand ( n21804 , n21803 , n21776 );
nand ( n21805 , n21799 , n21804 );
nand ( n21806 , n21805 , n9946 );
not ( n21807 , n21806 );
not ( n21808 , n9846 );
or ( n21809 , n21807 , n21808 );
or ( n21810 , n9846 , n21806 );
nand ( n21811 , n21809 , n21810 );
not ( n21812 , n21811 );
not ( n21813 , n10463 );
or ( n21814 , n21812 , n21813 );
not ( n21815 , n21811 );
nand ( n21816 , n21815 , n10472 );
nand ( n21817 , n21814 , n21816 );
and ( n21818 , n21817 , n11293 );
not ( n21819 , n21817 );
and ( n21820 , n21819 , n11302 );
nor ( n21821 , n21818 , n21820 );
not ( n21822 , n21821 );
xor ( n21823 , n15606 , n14714 );
not ( n21824 , n14755 );
xnor ( n21825 , n21823 , n21824 );
not ( n21826 , n21825 );
not ( n21827 , n21826 );
not ( n21828 , n9915 );
not ( n21829 , n12654 );
buf ( n21830 , n6270 );
not ( n21831 , n21830 );
not ( n21832 , n21831 );
or ( n21833 , n21829 , n21832 );
not ( n21834 , n12653 );
buf ( n21835 , n21830 );
nand ( n21836 , n21834 , n21835 );
nand ( n21837 , n21833 , n21836 );
not ( n21838 , n17472 );
and ( n21839 , n21837 , n21838 );
not ( n21840 , n21837 );
and ( n21841 , n21840 , n17473 );
nor ( n21842 , n21839 , n21841 );
buf ( n21843 , n6271 );
nand ( n21844 , n8454 , n21843 );
buf ( n21845 , n6272 );
buf ( n21846 , n21845 );
and ( n21847 , n21844 , n21846 );
not ( n21848 , n21844 );
not ( n21849 , n21845 );
and ( n21850 , n21848 , n21849 );
nor ( n21851 , n21847 , n21850 );
xor ( n21852 , n21842 , n21851 );
xnor ( n21853 , n21852 , n10626 );
not ( n21854 , n21853 );
not ( n21855 , n21854 );
or ( n21856 , n21828 , n21855 );
buf ( n21857 , n21853 );
nand ( n21858 , n21857 , n9918 );
nand ( n21859 , n21856 , n21858 );
buf ( n21860 , n9598 );
xor ( n21861 , n21859 , n21860 );
not ( n21862 , n7660 );
not ( n21863 , n21862 );
not ( n21864 , n16458 );
not ( n21865 , n21864 );
or ( n21866 , n21863 , n21865 );
or ( n21867 , n21864 , n21862 );
nand ( n21868 , n21866 , n21867 );
not ( n21869 , n16493 );
and ( n21870 , n21868 , n21869 );
not ( n21871 , n21868 );
not ( n21872 , n16497 );
and ( n21873 , n21871 , n21872 );
nor ( n21874 , n21870 , n21873 );
nand ( n21875 , n21861 , n21874 );
not ( n21876 , n21875 );
and ( n21877 , n21827 , n21876 );
and ( n21878 , n21826 , n21875 );
nor ( n21879 , n21877 , n21878 );
not ( n21880 , n21879 );
not ( n21881 , n21880 );
not ( n21882 , n13606 );
buf ( n21883 , n19929 );
not ( n21884 , n21883 );
or ( n21885 , n21882 , n21884 );
not ( n21886 , n13605 );
nand ( n21887 , n19930 , n21886 );
nand ( n21888 , n21885 , n21887 );
not ( n21889 , n21888 );
not ( n21890 , n19972 );
and ( n21891 , n21889 , n21890 );
not ( n21892 , n19970 );
not ( n21893 , n21892 );
buf ( n21894 , n21893 );
and ( n21895 , n21888 , n21894 );
nor ( n21896 , n21891 , n21895 );
not ( n21897 , n21896 );
not ( n21898 , n15045 );
not ( n21899 , n13050 );
and ( n21900 , n21898 , n21899 );
and ( n21901 , n15045 , n13050 );
nor ( n21902 , n21900 , n21901 );
buf ( n21903 , n20274 );
not ( n21904 , n21903 );
and ( n21905 , n21902 , n21904 );
not ( n21906 , n21902 );
and ( n21907 , n21906 , n21903 );
nor ( n21908 , n21905 , n21907 );
not ( n21909 , n21908 );
nand ( n21910 , n21897 , n21909 );
not ( n21911 , n21910 );
xor ( n21912 , n12448 , n12457 );
xnor ( n21913 , n21912 , n12461 );
xor ( n21914 , n7237 , n21913 );
buf ( n21915 , n6273 );
buf ( n21916 , n21915 );
not ( n21917 , n21916 );
not ( n21918 , n10860 );
or ( n21919 , n21917 , n21918 );
not ( n21920 , n21915 );
nand ( n21921 , n21920 , n10855 );
nand ( n21922 , n21919 , n21921 );
not ( n21923 , n8579 );
and ( n21924 , n21922 , n21923 );
not ( n21925 , n21922 );
and ( n21926 , n21925 , n8580 );
nor ( n21927 , n21924 , n21926 );
buf ( n21928 , n6274 );
nand ( n21929 , n7197 , n21928 );
buf ( n21930 , n6275 );
buf ( n21931 , n21930 );
and ( n21932 , n21929 , n21931 );
not ( n21933 , n21929 );
not ( n21934 , n21930 );
and ( n21935 , n21933 , n21934 );
nor ( n21936 , n21932 , n21935 );
xor ( n21937 , n21927 , n21936 );
buf ( n21938 , n6276 );
nand ( n21939 , n8032 , n21938 );
buf ( n21940 , n6277 );
not ( n21941 , n21940 );
and ( n21942 , n21939 , n21941 );
not ( n21943 , n21939 );
buf ( n21944 , n21940 );
and ( n21945 , n21943 , n21944 );
nor ( n21946 , n21942 , n21945 );
xnor ( n21947 , n21937 , n21946 );
not ( n21948 , n21947 );
buf ( n21949 , n21948 );
xnor ( n21950 , n21914 , n21949 );
not ( n21951 , n21950 );
not ( n21952 , n21951 );
and ( n21953 , n21911 , n21952 );
nand ( n21954 , n21897 , n21909 );
and ( n21955 , n21954 , n21951 );
nor ( n21956 , n21953 , n21955 );
not ( n21957 , n21956 );
not ( n21958 , n9277 );
not ( n21959 , n10884 );
not ( n21960 , n9235 );
or ( n21961 , n21959 , n21960 );
or ( n21962 , n9235 , n10884 );
nand ( n21963 , n21961 , n21962 );
not ( n21964 , n21963 );
or ( n21965 , n21958 , n21964 );
not ( n21966 , n21963 );
nand ( n21967 , n21966 , n9272 );
nand ( n21968 , n21965 , n21967 );
not ( n21969 , n21968 );
not ( n21970 , n16666 );
not ( n21971 , n16250 );
or ( n21972 , n21970 , n21971 );
not ( n21973 , n16666 );
nand ( n21974 , n21973 , n11015 );
nand ( n21975 , n21972 , n21974 );
and ( n21976 , n21975 , n16257 );
not ( n21977 , n21975 );
and ( n21978 , n21977 , n16258 );
nor ( n21979 , n21976 , n21978 );
not ( n21980 , n21979 );
nand ( n21981 , n21969 , n21980 );
not ( n21982 , n12091 );
not ( n21983 , n7188 );
not ( n21984 , n21983 );
or ( n21985 , n21982 , n21984 );
not ( n21986 , n12091 );
xor ( n21987 , n7168 , n7177 );
xnor ( n21988 , n21987 , n7187 );
nand ( n21989 , n21986 , n21988 );
nand ( n21990 , n21985 , n21989 );
not ( n21991 , n14992 );
buf ( n21992 , n21991 );
and ( n21993 , n21990 , n21992 );
not ( n21994 , n21990 );
and ( n21995 , n21994 , n14997 );
nor ( n21996 , n21993 , n21995 );
buf ( n21997 , n21996 );
and ( n21998 , n21981 , n21997 );
not ( n21999 , n21981 );
not ( n22000 , n21997 );
and ( n22001 , n21999 , n22000 );
nor ( n22002 , n21998 , n22001 );
not ( n22003 , n22002 );
or ( n22004 , n21957 , n22003 );
or ( n22005 , n22002 , n21956 );
nand ( n22006 , n22004 , n22005 );
buf ( n22007 , n6278 );
buf ( n22008 , n22007 );
not ( n22009 , n22008 );
buf ( n22010 , n6279 );
not ( n22011 , n22010 );
not ( n22012 , n22011 );
or ( n22013 , n22009 , n22012 );
not ( n22014 , n22007 );
buf ( n22015 , n22010 );
nand ( n22016 , n22014 , n22015 );
nand ( n22017 , n22013 , n22016 );
and ( n22018 , n22017 , n12046 );
not ( n22019 , n22017 );
not ( n22020 , n12045 );
and ( n22021 , n22019 , n22020 );
nor ( n22022 , n22018 , n22021 );
not ( n22023 , n22022 );
buf ( n22024 , n6280 );
nand ( n22025 , n7258 , n22024 );
buf ( n22026 , n6281 );
buf ( n22027 , n22026 );
and ( n22028 , n22025 , n22027 );
not ( n22029 , n22025 );
not ( n22030 , n22026 );
and ( n22031 , n22029 , n22030 );
nor ( n22032 , n22028 , n22031 );
xor ( n22033 , n22023 , n22032 );
buf ( n22034 , n6282 );
nand ( n22035 , n7107 , n22034 );
buf ( n22036 , n6283 );
buf ( n22037 , n22036 );
and ( n22038 , n22035 , n22037 );
not ( n22039 , n22035 );
not ( n22040 , n22036 );
and ( n22041 , n22039 , n22040 );
nor ( n22042 , n22038 , n22041 );
buf ( n22043 , n22042 );
xnor ( n22044 , n22033 , n22043 );
not ( n22045 , n22044 );
not ( n22046 , n22045 );
xor ( n22047 , n7374 , n22046 );
xnor ( n22048 , n22047 , n18261 );
not ( n22049 , n22048 );
not ( n22050 , n6630 );
not ( n22051 , n10446 );
or ( n22052 , n22050 , n22051 );
nand ( n22053 , n10443 , n6627 );
nand ( n22054 , n22052 , n22053 );
and ( n22055 , n22054 , n20785 );
not ( n22056 , n22054 );
and ( n22057 , n22056 , n20778 );
nor ( n22058 , n22055 , n22057 );
not ( n22059 , n22058 );
nand ( n22060 , n22049 , n22059 );
not ( n22061 , n14640 );
not ( n22062 , n11957 );
or ( n22063 , n22061 , n22062 );
or ( n22064 , n14640 , n11956 );
nand ( n22065 , n22063 , n22064 );
buf ( n22066 , n6284 );
buf ( n22067 , n22066 );
not ( n22068 , n22067 );
buf ( n22069 , n6285 );
not ( n22070 , n22069 );
not ( n22071 , n22070 );
or ( n22072 , n22068 , n22071 );
not ( n22073 , n22066 );
buf ( n22074 , n22069 );
nand ( n22075 , n22073 , n22074 );
nand ( n22076 , n22072 , n22075 );
buf ( n22077 , n6286 );
buf ( n22078 , n22077 );
and ( n22079 , n22076 , n22078 );
not ( n22080 , n22076 );
not ( n22081 , n22077 );
and ( n22082 , n22080 , n22081 );
nor ( n22083 , n22079 , n22082 );
buf ( n22084 , n6287 );
nand ( n22085 , n8954 , n22084 );
buf ( n22086 , n6288 );
buf ( n22087 , n22086 );
and ( n22088 , n22085 , n22087 );
not ( n22089 , n22085 );
not ( n22090 , n22086 );
and ( n22091 , n22089 , n22090 );
nor ( n22092 , n22088 , n22091 );
xor ( n22093 , n22083 , n22092 );
xnor ( n22094 , n22093 , n11528 );
buf ( n22095 , n22094 );
not ( n22096 , n22095 );
not ( n22097 , n22096 );
and ( n22098 , n22065 , n22097 );
not ( n22099 , n22065 );
not ( n22100 , n22094 );
and ( n22101 , n22099 , n22100 );
nor ( n22102 , n22098 , n22101 );
not ( n22103 , n22102 );
and ( n22104 , n22060 , n22103 );
not ( n22105 , n22060 );
and ( n22106 , n22105 , n22102 );
nor ( n22107 , n22104 , n22106 );
not ( n22108 , n22107 );
and ( n22109 , n22006 , n22108 );
not ( n22110 , n22006 );
and ( n22111 , n22110 , n22107 );
nor ( n22112 , n22109 , n22111 );
not ( n22113 , n22112 );
not ( n22114 , n15207 );
not ( n22115 , n20640 );
or ( n22116 , n22114 , n22115 );
or ( n22117 , n20640 , n15207 );
nand ( n22118 , n22116 , n22117 );
not ( n22119 , n22118 );
not ( n22120 , n13254 );
and ( n22121 , n22119 , n22120 );
and ( n22122 , n22118 , n13254 );
nor ( n22123 , n22121 , n22122 );
not ( n22124 , n22123 );
not ( n22125 , n19298 );
not ( n22126 , n13918 );
not ( n22127 , n19290 );
or ( n22128 , n22126 , n22127 );
not ( n22129 , n20836 );
or ( n22130 , n22129 , n13918 );
nand ( n22131 , n22128 , n22130 );
not ( n22132 , n22131 );
or ( n22133 , n22125 , n22132 );
or ( n22134 , n22131 , n19298 );
nand ( n22135 , n22133 , n22134 );
not ( n22136 , n22135 );
nand ( n22137 , n22124 , n22136 );
not ( n22138 , n17882 );
not ( n22139 , n22138 );
not ( n22140 , n22139 );
not ( n22141 , n15261 );
buf ( n22142 , n6289 );
buf ( n22143 , n22142 );
not ( n22144 , n22143 );
buf ( n22145 , n6290 );
not ( n22146 , n22145 );
not ( n22147 , n22146 );
or ( n22148 , n22144 , n22147 );
not ( n22149 , n22142 );
buf ( n22150 , n22145 );
nand ( n22151 , n22149 , n22150 );
nand ( n22152 , n22148 , n22151 );
buf ( n22153 , n6291 );
not ( n22154 , n22153 );
and ( n22155 , n22152 , n22154 );
not ( n22156 , n22152 );
buf ( n22157 , n22153 );
and ( n22158 , n22156 , n22157 );
nor ( n22159 , n22155 , n22158 );
buf ( n22160 , n6292 );
nand ( n22161 , n8364 , n22160 );
buf ( n22162 , n6293 );
buf ( n22163 , n22162 );
and ( n22164 , n22161 , n22163 );
not ( n22165 , n22161 );
not ( n22166 , n22162 );
and ( n22167 , n22165 , n22166 );
nor ( n22168 , n22164 , n22167 );
xor ( n22169 , n22159 , n22168 );
buf ( n22170 , n6294 );
nand ( n22171 , n6502 , n22170 );
buf ( n22172 , n6295 );
buf ( n22173 , n22172 );
and ( n22174 , n22171 , n22173 );
not ( n22175 , n22171 );
not ( n22176 , n22172 );
and ( n22177 , n22175 , n22176 );
nor ( n22178 , n22174 , n22177 );
not ( n22179 , n22178 );
xnor ( n22180 , n22169 , n22179 );
not ( n22181 , n22180 );
or ( n22182 , n22141 , n22181 );
not ( n22183 , n15261 );
not ( n22184 , n22159 );
xor ( n22185 , n22184 , n22178 );
not ( n22186 , n22168 );
xnor ( n22187 , n22185 , n22186 );
nand ( n22188 , n22183 , n22187 );
nand ( n22189 , n22182 , n22188 );
not ( n22190 , n22189 );
or ( n22191 , n22140 , n22190 );
or ( n22192 , n17883 , n22189 );
nand ( n22193 , n22191 , n22192 );
not ( n22194 , n22193 );
and ( n22195 , n22137 , n22194 );
not ( n22196 , n22137 );
and ( n22197 , n22196 , n22193 );
nor ( n22198 , n22195 , n22197 );
not ( n22199 , n21861 );
nand ( n22200 , n21825 , n22199 );
not ( n22201 , n22200 );
not ( n22202 , n20487 );
not ( n22203 , n7580 );
or ( n22204 , n22202 , n22203 );
or ( n22205 , n7580 , n20487 );
nand ( n22206 , n22204 , n22205 );
not ( n22207 , n22206 );
buf ( n22208 , n6296 );
buf ( n22209 , n22208 );
not ( n22210 , n22209 );
buf ( n22211 , n6297 );
not ( n22212 , n22211 );
not ( n22213 , n22212 );
or ( n22214 , n22210 , n22213 );
not ( n22215 , n22208 );
buf ( n22216 , n22211 );
nand ( n22217 , n22215 , n22216 );
nand ( n22218 , n22214 , n22217 );
buf ( n22219 , n6298 );
not ( n22220 , n22219 );
and ( n22221 , n22218 , n22220 );
not ( n22222 , n22218 );
buf ( n22223 , n22219 );
and ( n22224 , n22222 , n22223 );
nor ( n22225 , n22221 , n22224 );
buf ( n22226 , n6299 );
nand ( n22227 , n6927 , n22226 );
buf ( n22228 , n6300 );
not ( n22229 , n22228 );
and ( n22230 , n22227 , n22229 );
not ( n22231 , n22227 );
buf ( n22232 , n22228 );
and ( n22233 , n22231 , n22232 );
nor ( n22234 , n22230 , n22233 );
xor ( n22235 , n22225 , n22234 );
buf ( n22236 , n6301 );
nand ( n22237 , n6770 , n22236 );
buf ( n22238 , n6302 );
buf ( n22239 , n22238 );
and ( n22240 , n22237 , n22239 );
not ( n22241 , n22237 );
not ( n22242 , n22238 );
and ( n22243 , n22241 , n22242 );
nor ( n22244 , n22240 , n22243 );
xor ( n22245 , n22235 , n22244 );
not ( n22246 , n22245 );
buf ( n22247 , n22246 );
not ( n22248 , n22247 );
and ( n22249 , n22207 , n22248 );
and ( n22250 , n22206 , n22247 );
nor ( n22251 , n22249 , n22250 );
not ( n22252 , n22251 );
not ( n22253 , n22252 );
and ( n22254 , n22201 , n22253 );
and ( n22255 , n22200 , n22252 );
nor ( n22256 , n22254 , n22255 );
and ( n22257 , n22198 , n22256 );
not ( n22258 , n22198 );
not ( n22259 , n22256 );
and ( n22260 , n22258 , n22259 );
nor ( n22261 , n22257 , n22260 );
not ( n22262 , n22261 );
not ( n22263 , n22262 );
and ( n22264 , n22113 , n22263 );
and ( n22265 , n22112 , n22262 );
nor ( n22266 , n22264 , n22265 );
not ( n22267 , n22266 );
or ( n22268 , n21881 , n22267 );
not ( n22269 , n21880 );
not ( n22270 , n22262 );
not ( n22271 , n22112 );
or ( n22272 , n22270 , n22271 );
not ( n22273 , n22112 );
nand ( n22274 , n22273 , n22261 );
nand ( n22275 , n22272 , n22274 );
nand ( n22276 , n22269 , n22275 );
nand ( n22277 , n22268 , n22276 );
not ( n22278 , n6574 );
not ( n22279 , n13086 );
not ( n22280 , n22279 );
not ( n22281 , n15052 );
or ( n22282 , n22280 , n22281 );
or ( n22283 , n15052 , n22279 );
nand ( n22284 , n22282 , n22283 );
and ( n22285 , n22284 , n21904 );
not ( n22286 , n22284 );
not ( n22287 , n20274 );
not ( n22288 , n22287 );
and ( n22289 , n22286 , n22288 );
nor ( n22290 , n22285 , n22289 );
not ( n22291 , n22290 );
nand ( n22292 , n22291 , n6664 );
not ( n22293 , n22292 );
or ( n22294 , n22278 , n22293 );
not ( n22295 , n22290 );
nand ( n22296 , n22295 , n6664 );
or ( n22297 , n22296 , n6574 );
nand ( n22298 , n22294 , n22297 );
not ( n22299 , n14445 );
not ( n22300 , n8186 );
or ( n22301 , n22299 , n22300 );
not ( n22302 , n14445 );
nand ( n22303 , n22302 , n8192 );
nand ( n22304 , n22301 , n22303 );
not ( n22305 , n8234 );
and ( n22306 , n22304 , n22305 );
not ( n22307 , n22304 );
and ( n22308 , n22307 , n8233 );
nor ( n22309 , n22306 , n22308 );
not ( n22310 , n9598 );
not ( n22311 , n22310 );
buf ( n22312 , n9929 );
and ( n22313 , n22312 , n21853 );
not ( n22314 , n22312 );
and ( n22315 , n22314 , n21854 );
or ( n22316 , n22313 , n22315 );
not ( n22317 , n22316 );
not ( n22318 , n22317 );
or ( n22319 , n22311 , n22318 );
nand ( n22320 , n22316 , n9598 );
nand ( n22321 , n22319 , n22320 );
nand ( n22322 , n22309 , n22321 );
and ( n22323 , n22322 , n7320 );
not ( n22324 , n22322 );
and ( n22325 , n22324 , n7321 );
nor ( n22326 , n22323 , n22325 );
and ( n22327 , n22298 , n22326 );
not ( n22328 , n22298 );
not ( n22329 , n22326 );
and ( n22330 , n22328 , n22329 );
nor ( n22331 , n22327 , n22330 );
not ( n22332 , n22331 );
not ( n22333 , n8745 );
not ( n22334 , n22333 );
buf ( n22335 , n6303 );
buf ( n22336 , n22335 );
buf ( n22337 , n6304 );
buf ( n22338 , n22337 );
not ( n22339 , n22338 );
buf ( n22340 , n6305 );
not ( n22341 , n22340 );
not ( n22342 , n22341 );
or ( n22343 , n22339 , n22342 );
not ( n22344 , n22337 );
buf ( n22345 , n22340 );
nand ( n22346 , n22344 , n22345 );
nand ( n22347 , n22343 , n22346 );
buf ( n22348 , n22347 );
xor ( n22349 , n22336 , n22348 );
buf ( n22350 , n6306 );
nand ( n22351 , n10372 , n22350 );
buf ( n22352 , n6307 );
not ( n22353 , n22352 );
and ( n22354 , n22351 , n22353 );
not ( n22355 , n22351 );
buf ( n22356 , n22352 );
and ( n22357 , n22355 , n22356 );
nor ( n22358 , n22354 , n22357 );
not ( n22359 , n22358 );
not ( n22360 , n22359 );
buf ( n22361 , n6308 );
nand ( n22362 , n10372 , n22361 );
buf ( n22363 , n6309 );
buf ( n22364 , n22363 );
and ( n22365 , n22362 , n22364 );
not ( n22366 , n22362 );
not ( n22367 , n22363 );
and ( n22368 , n22366 , n22367 );
nor ( n22369 , n22365 , n22368 );
not ( n22370 , n22369 );
not ( n22371 , n22370 );
or ( n22372 , n22360 , n22371 );
nand ( n22373 , n22369 , n22358 );
nand ( n22374 , n22372 , n22373 );
xnor ( n22375 , n22349 , n22374 );
not ( n22376 , n22375 );
or ( n22377 , n22334 , n22376 );
not ( n22378 , n22335 );
xor ( n22379 , n22378 , n22347 );
xor ( n22380 , n22379 , n22374 );
or ( n22381 , n22380 , n22333 );
nand ( n22382 , n22377 , n22381 );
and ( n22383 , n22382 , n10851 );
not ( n22384 , n22382 );
not ( n22385 , n10851 );
and ( n22386 , n22384 , n22385 );
nor ( n22387 , n22383 , n22386 );
not ( n22388 , n10959 );
not ( n22389 , n18322 );
not ( n22390 , n10916 );
not ( n22391 , n22390 );
or ( n22392 , n22389 , n22391 );
not ( n22393 , n18322 );
nand ( n22394 , n22393 , n10916 );
nand ( n22395 , n22392 , n22394 );
not ( n22396 , n22395 );
or ( n22397 , n22388 , n22396 );
or ( n22398 , n22395 , n10959 );
nand ( n22399 , n22397 , n22398 );
nand ( n22400 , n22387 , n22399 );
not ( n22401 , n22400 );
not ( n22402 , n6951 );
and ( n22403 , n22401 , n22402 );
and ( n22404 , n22400 , n6951 );
nor ( n22405 , n22403 , n22404 );
not ( n22406 , n22405 );
or ( n22407 , n22332 , n22406 );
or ( n22408 , n22331 , n22405 );
nand ( n22409 , n22407 , n22408 );
not ( n22410 , n7837 );
not ( n22411 , n13784 );
buf ( n22412 , n19576 );
xor ( n22413 , n22412 , n19586 );
xnor ( n22414 , n22413 , n19593 );
not ( n22415 , n22414 );
not ( n22416 , n22415 );
or ( n22417 , n22411 , n22416 );
not ( n22418 , n13784 );
nand ( n22419 , n22418 , n22414 );
nand ( n22420 , n22417 , n22419 );
and ( n22421 , n22420 , n19608 );
not ( n22422 , n22420 );
and ( n22423 , n22422 , n19605 );
nor ( n22424 , n22421 , n22423 );
buf ( n22425 , n16003 );
not ( n22426 , n22425 );
buf ( n22427 , n6310 );
buf ( n22428 , n22427 );
not ( n22429 , n22428 );
buf ( n22430 , n6311 );
not ( n22431 , n22430 );
not ( n22432 , n22431 );
or ( n22433 , n22429 , n22432 );
not ( n22434 , n22427 );
buf ( n22435 , n22430 );
nand ( n22436 , n22434 , n22435 );
nand ( n22437 , n22433 , n22436 );
buf ( n22438 , n6312 );
not ( n22439 , n22438 );
and ( n22440 , n22437 , n22439 );
not ( n22441 , n22437 );
buf ( n22442 , n22438 );
and ( n22443 , n22441 , n22442 );
nor ( n22444 , n22440 , n22443 );
buf ( n22445 , n6313 );
nand ( n22446 , n7977 , n22445 );
buf ( n22447 , n6314 );
not ( n22448 , n22447 );
and ( n22449 , n22446 , n22448 );
not ( n22450 , n22446 );
buf ( n22451 , n22447 );
and ( n22452 , n22450 , n22451 );
nor ( n22453 , n22449 , n22452 );
xor ( n22454 , n22444 , n22453 );
buf ( n22455 , n6315 );
nand ( n22456 , n8032 , n22455 );
buf ( n22457 , n6316 );
buf ( n22458 , n22457 );
and ( n22459 , n22456 , n22458 );
not ( n22460 , n22456 );
not ( n22461 , n22457 );
and ( n22462 , n22460 , n22461 );
nor ( n22463 , n22459 , n22462 );
xor ( n22464 , n22454 , n22463 );
buf ( n22465 , n22464 );
not ( n22466 , n22465 );
not ( n22467 , n22466 );
or ( n22468 , n22426 , n22467 );
not ( n22469 , n22466 );
not ( n22470 , n22425 );
nand ( n22471 , n22469 , n22470 );
nand ( n22472 , n22468 , n22471 );
buf ( n22473 , n18208 );
and ( n22474 , n22472 , n22473 );
not ( n22475 , n22472 );
buf ( n22476 , n18207 );
and ( n22477 , n22475 , n22476 );
nor ( n22478 , n22474 , n22477 );
nand ( n22479 , n22424 , n22478 );
not ( n22480 , n22479 );
and ( n22481 , n22410 , n22480 );
and ( n22482 , n7837 , n22479 );
nor ( n22483 , n22481 , n22482 );
not ( n22484 , n22483 );
not ( n22485 , n22484 );
buf ( n22486 , n6643 );
and ( n22487 , n22486 , n10443 );
not ( n22488 , n22486 );
and ( n22489 , n22488 , n10446 );
nor ( n22490 , n22487 , n22489 );
not ( n22491 , n20784 );
and ( n22492 , n22490 , n22491 );
not ( n22493 , n22490 );
and ( n22494 , n22493 , n20778 );
nor ( n22495 , n22492 , n22494 );
not ( n22496 , n22495 );
not ( n22497 , n13988 );
not ( n22498 , n20828 );
or ( n22499 , n22497 , n22498 );
or ( n22500 , n21396 , n13988 );
nand ( n22501 , n22499 , n22500 );
and ( n22502 , n22501 , n19290 );
not ( n22503 , n22501 );
and ( n22504 , n22503 , n19293 );
nor ( n22505 , n22502 , n22504 );
not ( n22506 , n22505 );
nand ( n22507 , n22496 , n22506 );
not ( n22508 , n22507 );
not ( n22509 , n7497 );
or ( n22510 , n22508 , n22509 );
or ( n22511 , n7497 , n22507 );
nand ( n22512 , n22510 , n22511 );
not ( n22513 , n22512 );
not ( n22514 , n22513 );
or ( n22515 , n22485 , n22514 );
nand ( n22516 , n22483 , n22512 );
nand ( n22517 , n22515 , n22516 );
and ( n22518 , n22409 , n22517 );
not ( n22519 , n22409 );
not ( n22520 , n22517 );
and ( n22521 , n22519 , n22520 );
nor ( n22522 , n22518 , n22521 );
buf ( n22523 , n22522 );
and ( n22524 , n22277 , n22523 );
not ( n22525 , n22277 );
and ( n22526 , n22409 , n22520 );
not ( n22527 , n22409 );
and ( n22528 , n22527 , n22517 );
nor ( n22529 , n22526 , n22528 );
buf ( n22530 , n22529 );
and ( n22531 , n22525 , n22530 );
nor ( n22532 , n22524 , n22531 );
not ( n22533 , n22532 );
nand ( n22534 , n21822 , n22533 );
xor ( n22535 , n11529 , n11536 );
xnor ( n22536 , n22535 , n11543 );
buf ( n22537 , n22536 );
not ( n22538 , n22537 );
not ( n22539 , n22538 );
not ( n22540 , n22078 );
and ( n22541 , n22539 , n22540 );
not ( n22542 , n22537 );
and ( n22543 , n22542 , n22078 );
nor ( n22544 , n22541 , n22543 );
buf ( n22545 , n11575 );
and ( n22546 , n22544 , n22545 );
not ( n22547 , n22544 );
xor ( n22548 , n11563 , n11573 );
xor ( n22549 , n22548 , n11455 );
buf ( n22550 , n22549 );
and ( n22551 , n22547 , n22550 );
nor ( n22552 , n22546 , n22551 );
not ( n22553 , n10838 );
buf ( n22554 , n21447 );
not ( n22555 , n22554 );
or ( n22556 , n22553 , n22555 );
not ( n22557 , n21699 );
not ( n22558 , n22557 );
nand ( n22559 , n22558 , n10834 );
nand ( n22560 , n22556 , n22559 );
and ( n22561 , n22560 , n21453 );
not ( n22562 , n22560 );
buf ( n22563 , n18710 );
and ( n22564 , n22562 , n22563 );
nor ( n22565 , n22561 , n22564 );
nand ( n22566 , n22552 , n22565 );
not ( n22567 , n11407 );
not ( n22568 , n6792 );
or ( n22569 , n22567 , n22568 );
or ( n22570 , n6791 , n11407 );
nand ( n22571 , n22569 , n22570 );
and ( n22572 , n22571 , n20464 );
not ( n22573 , n22571 );
and ( n22574 , n22573 , n20463 );
nor ( n22575 , n22572 , n22574 );
and ( n22576 , n22566 , n22575 );
not ( n22577 , n22566 );
not ( n22578 , n22575 );
and ( n22579 , n22577 , n22578 );
nor ( n22580 , n22576 , n22579 );
not ( n22581 , n22580 );
and ( n22582 , n10442 , n6656 );
not ( n22583 , n10442 );
and ( n22584 , n22583 , n6657 );
or ( n22585 , n22582 , n22584 );
not ( n22586 , n20783 );
and ( n22587 , n22585 , n22586 );
not ( n22588 , n22585 );
and ( n22589 , n22588 , n20778 );
nor ( n22590 , n22587 , n22589 );
not ( n22591 , n22590 );
not ( n22592 , n22591 );
not ( n22593 , n16408 );
buf ( n22594 , n6317 );
not ( n22595 , n22594 );
and ( n22596 , n22593 , n22595 );
and ( n22597 , n16408 , n22594 );
nor ( n22598 , n22596 , n22597 );
not ( n22599 , n22598 );
not ( n22600 , n16229 );
or ( n22601 , n22599 , n22600 );
or ( n22602 , n16229 , n22598 );
nand ( n22603 , n22601 , n22602 );
not ( n22604 , n11317 );
xor ( n22605 , n17657 , n17661 );
xnor ( n22606 , n22605 , n17671 );
not ( n22607 , n22606 );
or ( n22608 , n22604 , n22607 );
or ( n22609 , n22606 , n11317 );
nand ( n22610 , n22608 , n22609 );
and ( n22611 , n22610 , n17332 );
not ( n22612 , n22610 );
and ( n22613 , n22612 , n17347 );
nor ( n22614 , n22611 , n22613 );
nand ( n22615 , n22603 , n22614 );
not ( n22616 , n22615 );
or ( n22617 , n22592 , n22616 );
or ( n22618 , n22615 , n22591 );
nand ( n22619 , n22617 , n22618 );
not ( n22620 , n22619 );
not ( n22621 , n13368 );
not ( n22622 , n19322 );
not ( n22623 , n22622 );
or ( n22624 , n22621 , n22623 );
not ( n22625 , n13368 );
nand ( n22626 , n22625 , n19322 );
nand ( n22627 , n22624 , n22626 );
buf ( n22628 , n6318 );
buf ( n22629 , n22628 );
not ( n22630 , n22629 );
not ( n22631 , n14226 );
or ( n22632 , n22630 , n22631 );
not ( n22633 , n22628 );
nand ( n22634 , n22633 , n14180 );
nand ( n22635 , n22632 , n22634 );
buf ( n22636 , n6319 );
not ( n22637 , n22636 );
and ( n22638 , n22635 , n22637 );
not ( n22639 , n22635 );
buf ( n22640 , n22636 );
and ( n22641 , n22639 , n22640 );
nor ( n22642 , n22638 , n22641 );
buf ( n22643 , n6320 );
nand ( n22644 , n7698 , n22643 );
buf ( n22645 , n6321 );
xor ( n22646 , n22644 , n22645 );
xor ( n22647 , n22642 , n22646 );
buf ( n22648 , n6322 );
nand ( n22649 , n10383 , n22648 );
buf ( n22650 , n6323 );
not ( n22651 , n22650 );
and ( n22652 , n22649 , n22651 );
not ( n22653 , n22649 );
buf ( n22654 , n22650 );
and ( n22655 , n22653 , n22654 );
nor ( n22656 , n22652 , n22655 );
xnor ( n22657 , n22647 , n22656 );
buf ( n22658 , n22657 );
xor ( n22659 , n22627 , n22658 );
not ( n22660 , n7270 );
buf ( n22661 , n8301 );
not ( n22662 , n22661 );
and ( n22663 , n22660 , n22662 );
and ( n22664 , n7270 , n22661 );
nor ( n22665 , n22663 , n22664 );
and ( n22666 , n22665 , n7315 );
not ( n22667 , n22665 );
and ( n22668 , n22667 , n9001 );
nor ( n22669 , n22666 , n22668 );
nand ( n22670 , n22659 , n22669 );
not ( n22671 , n22670 );
not ( n22672 , n7191 );
not ( n22673 , n19442 );
or ( n22674 , n22672 , n22673 );
not ( n22675 , n7191 );
nand ( n22676 , n22675 , n19446 );
nand ( n22677 , n22674 , n22676 );
and ( n22678 , n22677 , n18863 );
not ( n22679 , n22677 );
not ( n22680 , n18863 );
and ( n22681 , n22679 , n22680 );
nor ( n22682 , n22678 , n22681 );
not ( n22683 , n22682 );
and ( n22684 , n22671 , n22683 );
nand ( n22685 , n22659 , n22669 );
and ( n22686 , n22685 , n22682 );
nor ( n22687 , n22684 , n22686 );
not ( n22688 , n22687 );
or ( n22689 , n22620 , n22688 );
or ( n22690 , n22687 , n22619 );
nand ( n22691 , n22689 , n22690 );
buf ( n22692 , n6324 );
xor ( n22693 , n22692 , n18300 );
not ( n22694 , n12907 );
xnor ( n22695 , n22693 , n22694 );
not ( n22696 , n22695 );
xor ( n22697 , n11072 , n13133 );
xor ( n22698 , n13182 , n13146 );
xnor ( n22699 , n22698 , n13177 );
buf ( n22700 , n22699 );
xnor ( n22701 , n22697 , n22700 );
nand ( n22702 , n22696 , n22701 );
and ( n22703 , n9308 , n21491 );
not ( n22704 , n9308 );
buf ( n22705 , n16658 );
and ( n22706 , n22704 , n22705 );
or ( n22707 , n22703 , n22706 );
not ( n22708 , n16685 );
and ( n22709 , n22707 , n22708 );
not ( n22710 , n22707 );
and ( n22711 , n22710 , n16685 );
nor ( n22712 , n22709 , n22711 );
and ( n22713 , n22702 , n22712 );
not ( n22714 , n22702 );
not ( n22715 , n22712 );
and ( n22716 , n22714 , n22715 );
nor ( n22717 , n22713 , n22716 );
xor ( n22718 , n22691 , n22717 );
not ( n22719 , n22565 );
nand ( n22720 , n22575 , n22719 );
not ( n22721 , n8762 );
buf ( n22722 , n6325 );
nand ( n22723 , n6828 , n22722 );
buf ( n22724 , n6326 );
not ( n22725 , n22724 );
and ( n22726 , n22723 , n22725 );
not ( n22727 , n22723 );
buf ( n22728 , n22724 );
and ( n22729 , n22727 , n22728 );
nor ( n22730 , n22726 , n22729 );
buf ( n22731 , n22730 );
not ( n22732 , n22731 );
not ( n22733 , n18082 );
nor ( n22734 , n22732 , n22733 );
not ( n22735 , n22734 );
not ( n22736 , n22731 );
nand ( n22737 , n22736 , n20428 );
nand ( n22738 , n22735 , n22737 );
not ( n22739 , n22738 );
and ( n22740 , n22721 , n22739 );
not ( n22741 , n8761 );
and ( n22742 , n22741 , n22738 );
nor ( n22743 , n22740 , n22742 );
and ( n22744 , n22720 , n22743 );
not ( n22745 , n22720 );
not ( n22746 , n22743 );
and ( n22747 , n22745 , n22746 );
nor ( n22748 , n22744 , n22747 );
not ( n22749 , n22748 );
not ( n22750 , n15069 );
not ( n22751 , n14508 );
not ( n22752 , n22751 );
or ( n22753 , n22750 , n22752 );
nand ( n22754 , n14508 , n15065 );
nand ( n22755 , n22753 , n22754 );
not ( n22756 , n16898 );
not ( n22757 , n22756 );
and ( n22758 , n22755 , n22757 );
not ( n22759 , n22755 );
and ( n22760 , n22759 , n22756 );
nor ( n22761 , n22758 , n22760 );
not ( n22762 , n13561 );
not ( n22763 , n19243 );
or ( n22764 , n22762 , n22763 );
not ( n22765 , n11228 );
nand ( n22766 , n22765 , n13557 );
nand ( n22767 , n22764 , n22766 );
and ( n22768 , n22767 , n11272 );
not ( n22769 , n22767 );
and ( n22770 , n22769 , n11275 );
nor ( n22771 , n22768 , n22770 );
not ( n22772 , n22771 );
nand ( n22773 , n22761 , n22772 );
not ( n22774 , n22773 );
buf ( n22775 , n10381 );
xor ( n22776 , n22775 , n12149 );
xnor ( n22777 , n22776 , n7829 );
not ( n22778 , n22777 );
and ( n22779 , n22774 , n22778 );
and ( n22780 , n22773 , n22777 );
nor ( n22781 , n22779 , n22780 );
not ( n22782 , n22781 );
or ( n22783 , n22749 , n22782 );
or ( n22784 , n22781 , n22748 );
nand ( n22785 , n22783 , n22784 );
not ( n22786 , n22785 );
and ( n22787 , n22718 , n22786 );
not ( n22788 , n22718 );
and ( n22789 , n22788 , n22785 );
nor ( n22790 , n22787 , n22789 );
not ( n22791 , n22790 );
not ( n22792 , n22791 );
not ( n22793 , n22792 );
or ( n22794 , n22581 , n22793 );
not ( n22795 , n22580 );
nand ( n22796 , n22795 , n22791 );
nand ( n22797 , n22794 , n22796 );
not ( n22798 , n6490 );
not ( n22799 , n15639 );
not ( n22800 , n22799 );
or ( n22801 , n22798 , n22800 );
buf ( n22802 , n15634 );
not ( n22803 , n22802 );
or ( n22804 , n22803 , n6490 );
nand ( n22805 , n22801 , n22804 );
not ( n22806 , n15603 );
not ( n22807 , n22806 );
and ( n22808 , n22805 , n22807 );
not ( n22809 , n22805 );
and ( n22810 , n22809 , n15604 );
nor ( n22811 , n22808 , n22810 );
not ( n22812 , n10120 );
not ( n22813 , n15474 );
or ( n22814 , n22812 , n22813 );
or ( n22815 , n15474 , n10120 );
nand ( n22816 , n22814 , n22815 );
buf ( n22817 , n12707 );
and ( n22818 , n22816 , n22817 );
not ( n22819 , n22816 );
not ( n22820 , n12713 );
not ( n22821 , n22820 );
and ( n22822 , n22819 , n22821 );
nor ( n22823 , n22818 , n22822 );
not ( n22824 , n22823 );
nand ( n22825 , n22811 , n22824 );
not ( n22826 , n22825 );
not ( n22827 , n14656 );
not ( n22828 , n19604 );
or ( n22829 , n22827 , n22828 );
or ( n22830 , n19605 , n14656 );
nand ( n22831 , n22829 , n22830 );
and ( n22832 , n22831 , n11957 );
not ( n22833 , n22831 );
and ( n22834 , n22833 , n11958 );
nor ( n22835 , n22832 , n22834 );
not ( n22836 , n22835 );
not ( n22837 , n22836 );
and ( n22838 , n22826 , n22837 );
and ( n22839 , n22825 , n22836 );
nor ( n22840 , n22838 , n22839 );
not ( n22841 , n22840 );
buf ( n22842 , n22044 );
xor ( n22843 , n7388 , n22842 );
xnor ( n22844 , n22843 , n18261 );
not ( n22845 , n22844 );
not ( n22846 , n21249 );
xor ( n22847 , n21133 , n21143 );
xor ( n22848 , n22847 , n16299 );
not ( n22849 , n22848 );
or ( n22850 , n22846 , n22849 );
or ( n22851 , n21149 , n21249 );
nand ( n22852 , n22850 , n22851 );
and ( n22853 , n22852 , n22180 );
not ( n22854 , n22852 );
and ( n22855 , n22854 , n22187 );
nor ( n22856 , n22853 , n22855 );
not ( n22857 , n22856 );
nand ( n22858 , n22845 , n22857 );
not ( n22859 , n7970 );
not ( n22860 , n14541 );
not ( n22861 , n22860 );
or ( n22862 , n22859 , n22861 );
not ( n22863 , n14541 );
not ( n22864 , n22863 );
nand ( n22865 , n22864 , n7966 );
nand ( n22866 , n22862 , n22865 );
buf ( n22867 , n22751 );
and ( n22868 , n22866 , n22867 );
not ( n22869 , n22866 );
and ( n22870 , n22869 , n14508 );
nor ( n22871 , n22868 , n22870 );
and ( n22872 , n22858 , n22871 );
not ( n22873 , n22858 );
not ( n22874 , n22871 );
and ( n22875 , n22873 , n22874 );
nor ( n22876 , n22872 , n22875 );
not ( n22877 , n22876 );
or ( n22878 , n22841 , n22877 );
or ( n22879 , n22876 , n22840 );
nand ( n22880 , n22878 , n22879 );
not ( n22881 , n22880 );
not ( n22882 , n22881 );
not ( n22883 , n13398 );
not ( n22884 , n16316 );
and ( n22885 , n22883 , n22884 );
and ( n22886 , n13398 , n16316 );
nor ( n22887 , n22885 , n22886 );
not ( n22888 , n7627 );
not ( n22889 , n22888 );
and ( n22890 , n22887 , n22889 );
not ( n22891 , n22887 );
and ( n22892 , n22891 , n19552 );
nor ( n22893 , n22890 , n22892 );
not ( n22894 , n22893 );
buf ( n22895 , n9224 );
not ( n22896 , n22895 );
not ( n22897 , n9033 );
not ( n22898 , n9043 );
or ( n22899 , n22897 , n22898 );
or ( n22900 , n9033 , n9043 );
nand ( n22901 , n22899 , n22900 );
not ( n22902 , n9024 );
and ( n22903 , n22901 , n22902 );
not ( n22904 , n22901 );
and ( n22905 , n22904 , n9024 );
nor ( n22906 , n22903 , n22905 );
not ( n22907 , n22906 );
or ( n22908 , n22896 , n22907 );
not ( n22909 , n22895 );
nand ( n22910 , n22909 , n9045 );
nand ( n22911 , n22908 , n22910 );
not ( n22912 , n22911 );
not ( n22913 , n17717 );
and ( n22914 , n22912 , n22913 );
and ( n22915 , n22911 , n17717 );
nor ( n22916 , n22914 , n22915 );
not ( n22917 , n22916 );
nand ( n22918 , n22894 , n22917 );
not ( n22919 , n22918 );
buf ( n22920 , n6327 );
buf ( n22921 , n22920 );
not ( n22922 , n22921 );
buf ( n22923 , n6328 );
buf ( n22924 , n22923 );
not ( n22925 , n22924 );
not ( n22926 , n20698 );
or ( n22927 , n22925 , n22926 );
not ( n22928 , n22923 );
nand ( n22929 , n22928 , n20693 );
nand ( n22930 , n22927 , n22929 );
xor ( n22931 , n18562 , n22930 );
buf ( n22932 , n6329 );
buf ( n22933 , n6330 );
xor ( n22934 , n22932 , n22933 );
buf ( n22935 , n6331 );
nand ( n22936 , n8223 , n22935 );
xnor ( n22937 , n22934 , n22936 );
xnor ( n22938 , n22931 , n22937 );
not ( n22939 , n22938 );
or ( n22940 , n22922 , n22939 );
or ( n22941 , n22938 , n22921 );
nand ( n22942 , n22940 , n22941 );
buf ( n22943 , n17672 );
xnor ( n22944 , n22942 , n22943 );
not ( n22945 , n22944 );
and ( n22946 , n22919 , n22945 );
not ( n22947 , n22893 );
nand ( n22948 , n22947 , n22917 );
and ( n22949 , n22948 , n22944 );
nor ( n22950 , n22946 , n22949 );
not ( n22951 , n22950 );
not ( n22952 , n22951 );
not ( n22953 , n11104 );
not ( n22954 , n8134 );
and ( n22955 , n22953 , n22954 );
and ( n22956 , n11104 , n8134 );
nor ( n22957 , n22955 , n22956 );
xor ( n22958 , n21260 , n21230 );
xnor ( n22959 , n22958 , n21255 );
and ( n22960 , n22957 , n22959 );
not ( n22961 , n22957 );
and ( n22962 , n22961 , n21268 );
nor ( n22963 , n22960 , n22962 );
not ( n22964 , n19577 );
not ( n22965 , n21622 );
or ( n22966 , n22964 , n22965 );
or ( n22967 , n21622 , n19577 );
nand ( n22968 , n22966 , n22967 );
not ( n22969 , n21632 );
and ( n22970 , n22968 , n22969 );
not ( n22971 , n22968 );
and ( n22972 , n22971 , n21628 );
nor ( n22973 , n22970 , n22972 );
not ( n22974 , n22973 );
nand ( n22975 , n22963 , n22974 );
buf ( n22976 , n6332 );
not ( n22977 , n22976 );
buf ( n22978 , n6333 );
not ( n22979 , n22978 );
buf ( n22980 , n6334 );
buf ( n22981 , n22980 );
nand ( n22982 , n22979 , n22981 );
not ( n22983 , n22980 );
buf ( n22984 , n22978 );
nand ( n22985 , n22983 , n22984 );
and ( n22986 , n22982 , n22985 );
xor ( n22987 , n22977 , n22986 );
buf ( n22988 , n6335 );
buf ( n22989 , n6336 );
xor ( n22990 , n22988 , n22989 );
buf ( n22991 , n6337 );
nand ( n22992 , n7259 , n22991 );
xnor ( n22993 , n22990 , n22992 );
xnor ( n22994 , n22987 , n22993 );
not ( n22995 , n22994 );
not ( n22996 , n14956 );
not ( n22997 , n18821 );
or ( n22998 , n22996 , n22997 );
or ( n22999 , n18821 , n14956 );
nand ( n23000 , n22998 , n22999 );
not ( n23001 , n23000 );
and ( n23002 , n22995 , n23001 );
buf ( n23003 , n22994 );
and ( n23004 , n23003 , n23000 );
nor ( n23005 , n23002 , n23004 );
and ( n23006 , n22975 , n23005 );
not ( n23007 , n22975 );
not ( n23008 , n23005 );
and ( n23009 , n23007 , n23008 );
nor ( n23010 , n23006 , n23009 );
not ( n23011 , n23010 );
not ( n23012 , n23011 );
or ( n23013 , n22952 , n23012 );
nand ( n23014 , n22950 , n23010 );
nand ( n23015 , n23013 , n23014 );
xor ( n23016 , n14813 , n7494 );
xor ( n23017 , n23016 , n10912 );
not ( n23018 , n23017 );
not ( n23019 , n16539 );
not ( n23020 , n17769 );
or ( n23021 , n23019 , n23020 );
nand ( n23022 , n17772 , n16538 );
nand ( n23023 , n23021 , n23022 );
not ( n23024 , n23023 );
not ( n23025 , n17776 );
and ( n23026 , n23024 , n23025 );
and ( n23027 , n17776 , n23023 );
nor ( n23028 , n23026 , n23027 );
not ( n23029 , n23028 );
nand ( n23030 , n23018 , n23029 );
not ( n23031 , n21916 );
not ( n23032 , n8619 );
or ( n23033 , n23031 , n23032 );
not ( n23034 , n8618 );
not ( n23035 , n23034 );
or ( n23036 , n23035 , n21916 );
nand ( n23037 , n23033 , n23036 );
and ( n23038 , n23037 , n8662 );
not ( n23039 , n23037 );
and ( n23040 , n23039 , n8663 );
nor ( n23041 , n23038 , n23040 );
not ( n23042 , n23041 );
and ( n23043 , n23030 , n23042 );
not ( n23044 , n23030 );
and ( n23045 , n23044 , n23041 );
nor ( n23046 , n23043 , n23045 );
and ( n23047 , n23015 , n23046 );
not ( n23048 , n23015 );
not ( n23049 , n23046 );
and ( n23050 , n23048 , n23049 );
nor ( n23051 , n23047 , n23050 );
not ( n23052 , n23051 );
or ( n23053 , n22882 , n23052 );
or ( n23054 , n23051 , n22881 );
nand ( n23055 , n23053 , n23054 );
not ( n23056 , n23055 );
not ( n23057 , n23056 );
not ( n23058 , n23057 );
and ( n23059 , n22797 , n23058 );
not ( n23060 , n22797 );
and ( n23061 , n23060 , n23057 );
nor ( n23062 , n23059 , n23061 );
not ( n23063 , n23062 );
and ( n23064 , n22534 , n23063 );
not ( n23065 , n22534 );
and ( n23066 , n23065 , n23062 );
nor ( n23067 , n23064 , n23066 );
not ( n23068 , n21737 );
buf ( n23069 , n23068 );
or ( n23070 , n23067 , n23069 );
nand ( n23071 , n21746 , n23070 );
buf ( n23072 , n23071 );
buf ( n23073 , n23072 );
not ( n23074 , n12370 );
not ( n23075 , n10541 );
or ( n23076 , n23074 , n23075 );
not ( n23077 , n12370 );
nand ( n23078 , n23077 , n10534 );
nand ( n23079 , n23076 , n23078 );
and ( n23080 , n23079 , n10587 );
not ( n23081 , n23079 );
and ( n23082 , n23081 , n10581 );
nor ( n23083 , n23080 , n23082 );
not ( n23084 , n23083 );
and ( n23085 , n6533 , n15603 );
not ( n23086 , n6533 );
and ( n23087 , n23086 , n15602 );
nor ( n23088 , n23085 , n23087 );
buf ( n23089 , n6338 );
buf ( n23090 , n6339 );
nand ( n23091 , n8537 , n23090 );
buf ( n23092 , n6340 );
buf ( n23093 , n23092 );
and ( n23094 , n23091 , n23093 );
not ( n23095 , n23091 );
not ( n23096 , n23092 );
and ( n23097 , n23095 , n23096 );
nor ( n23098 , n23094 , n23097 );
xor ( n23099 , n23089 , n23098 );
buf ( n23100 , n6341 );
nand ( n23101 , n6647 , n23100 );
buf ( n23102 , n6342 );
not ( n23103 , n23102 );
and ( n23104 , n23101 , n23103 );
not ( n23105 , n23101 );
buf ( n23106 , n23102 );
and ( n23107 , n23105 , n23106 );
nor ( n23108 , n23104 , n23107 );
xnor ( n23109 , n23099 , n23108 );
not ( n23110 , n23109 );
buf ( n23111 , n6343 );
buf ( n23112 , n23111 );
not ( n23113 , n23112 );
buf ( n23114 , n6344 );
not ( n23115 , n23114 );
not ( n23116 , n23115 );
or ( n23117 , n23113 , n23116 );
not ( n23118 , n23111 );
buf ( n23119 , n23114 );
nand ( n23120 , n23118 , n23119 );
nand ( n23121 , n23117 , n23120 );
not ( n23122 , n23121 );
not ( n23123 , n23122 );
and ( n23124 , n23110 , n23123 );
and ( n23125 , n23109 , n23122 );
nor ( n23126 , n23124 , n23125 );
and ( n23127 , n23088 , n23126 );
not ( n23128 , n23088 );
not ( n23129 , n23126 );
and ( n23130 , n23128 , n23129 );
nor ( n23131 , n23127 , n23130 );
nand ( n23132 , n23084 , n23131 );
not ( n23133 , n23132 );
buf ( n23134 , n6345 );
nand ( n23135 , n13581 , n23134 );
buf ( n23136 , n6346 );
not ( n23137 , n23136 );
and ( n23138 , n23135 , n23137 );
not ( n23139 , n23135 );
buf ( n23140 , n23136 );
and ( n23141 , n23139 , n23140 );
nor ( n23142 , n23138 , n23141 );
buf ( n23143 , n23142 );
not ( n23144 , n23143 );
not ( n23145 , n13502 );
or ( n23146 , n23144 , n23145 );
not ( n23147 , n23143 );
not ( n23148 , n13490 );
not ( n23149 , n13500 );
or ( n23150 , n23148 , n23149 );
or ( n23151 , n13490 , n13500 );
nand ( n23152 , n23150 , n23151 );
xnor ( n23153 , n23152 , n13481 );
nand ( n23154 , n23147 , n23153 );
nand ( n23155 , n23146 , n23154 );
and ( n23156 , n23155 , n13516 );
not ( n23157 , n23155 );
and ( n23158 , n23157 , n7224 );
nor ( n23159 , n23156 , n23158 );
not ( n23160 , n23159 );
and ( n23161 , n23133 , n23160 );
not ( n23162 , n23083 );
nand ( n23163 , n23162 , n23131 );
and ( n23164 , n23163 , n23159 );
nor ( n23165 , n23161 , n23164 );
not ( n23166 , n23165 );
not ( n23167 , n23166 );
not ( n23168 , n23159 );
nand ( n23169 , n23168 , n23083 );
not ( n23170 , n18347 );
not ( n23171 , n20496 );
xor ( n23172 , n23171 , n20515 );
not ( n23173 , n20505 );
xnor ( n23174 , n23172 , n23173 );
not ( n23175 , n23174 );
or ( n23176 , n23170 , n23175 );
nand ( n23177 , n20517 , n18350 );
nand ( n23178 , n23176 , n23177 );
not ( n23179 , n23178 );
buf ( n23180 , n20037 );
not ( n23181 , n23180 );
and ( n23182 , n23179 , n23181 );
and ( n23183 , n23178 , n23180 );
nor ( n23184 , n23182 , n23183 );
not ( n23185 , n23184 );
and ( n23186 , n23169 , n23185 );
not ( n23187 , n23169 );
and ( n23188 , n23187 , n23184 );
nor ( n23189 , n23186 , n23188 );
not ( n23190 , n23189 );
not ( n23191 , n23190 );
not ( n23192 , n19091 );
not ( n23193 , n12813 );
not ( n23194 , n12825 );
xor ( n23195 , n23193 , n23194 );
xnor ( n23196 , n23195 , n12831 );
not ( n23197 , n23196 );
or ( n23198 , n23192 , n23197 );
or ( n23199 , n23196 , n19091 );
nand ( n23200 , n23198 , n23199 );
buf ( n23201 , n12809 );
and ( n23202 , n23200 , n23201 );
not ( n23203 , n23200 );
not ( n23204 , n23201 );
and ( n23205 , n23203 , n23204 );
nor ( n23206 , n23202 , n23205 );
buf ( n23207 , n17533 );
not ( n23208 , n23207 );
not ( n23209 , n20336 );
not ( n23210 , n23209 );
or ( n23211 , n23208 , n23210 );
or ( n23212 , n23209 , n23207 );
nand ( n23213 , n23211 , n23212 );
and ( n23214 , n23213 , n8888 );
not ( n23215 , n23213 );
and ( n23216 , n23215 , n18897 );
nor ( n23217 , n23214 , n23216 );
not ( n23218 , n23217 );
nand ( n23219 , n23206 , n23218 );
buf ( n23220 , n7649 );
not ( n23221 , n23220 );
not ( n23222 , n16452 );
or ( n23223 , n23221 , n23222 );
not ( n23224 , n23220 );
nand ( n23225 , n23224 , n16453 );
nand ( n23226 , n23223 , n23225 );
not ( n23227 , n23226 );
not ( n23228 , n16493 );
and ( n23229 , n23227 , n23228 );
and ( n23230 , n23226 , n16493 );
nor ( n23231 , n23229 , n23230 );
buf ( n23232 , n23231 );
xor ( n23233 , n23219 , n23232 );
not ( n23234 , n23233 );
not ( n23235 , n23234 );
or ( n23236 , n23191 , n23235 );
nand ( n23237 , n23233 , n23189 );
nand ( n23238 , n23236 , n23237 );
buf ( n23239 , n20619 );
xor ( n23240 , n22244 , n23239 );
not ( n23241 , n21513 );
and ( n23242 , n21539 , n21184 );
not ( n23243 , n21539 );
not ( n23244 , n21183 );
and ( n23245 , n23243 , n23244 );
nor ( n23246 , n23242 , n23245 );
not ( n23247 , n23246 );
not ( n23248 , n23247 );
or ( n23249 , n23241 , n23248 );
not ( n23250 , n21513 );
nand ( n23251 , n23246 , n23250 );
nand ( n23252 , n23249 , n23251 );
buf ( n23253 , n23252 );
xnor ( n23254 , n23240 , n23253 );
buf ( n23255 , n6347 );
nand ( n23256 , n7912 , n23255 );
buf ( n23257 , n6348 );
not ( n23258 , n23257 );
and ( n23259 , n23256 , n23258 );
not ( n23260 , n23256 );
buf ( n23261 , n23257 );
and ( n23262 , n23260 , n23261 );
nor ( n23263 , n23259 , n23262 );
not ( n23264 , n23263 );
not ( n23265 , n7315 );
or ( n23266 , n23264 , n23265 );
not ( n23267 , n23263 );
nand ( n23268 , n23267 , n7318 );
nand ( n23269 , n23266 , n23268 );
and ( n23270 , n23269 , n11755 );
not ( n23271 , n23269 );
and ( n23272 , n23271 , n16151 );
nor ( n23273 , n23270 , n23272 );
nand ( n23274 , n23254 , n23273 );
not ( n23275 , n23274 );
not ( n23276 , n14729 );
not ( n23277 , n16257 );
or ( n23278 , n23276 , n23277 );
not ( n23279 , n14728 );
nand ( n23280 , n16258 , n23279 );
nand ( n23281 , n23278 , n23280 );
and ( n23282 , n23281 , n19622 );
not ( n23283 , n23281 );
not ( n23284 , n19619 );
not ( n23285 , n23284 );
and ( n23286 , n23283 , n23285 );
nor ( n23287 , n23282 , n23286 );
not ( n23288 , n23287 );
and ( n23289 , n23275 , n23288 );
and ( n23290 , n23274 , n23287 );
nor ( n23291 , n23289 , n23290 );
and ( n23292 , n23238 , n23291 );
not ( n23293 , n23238 );
not ( n23294 , n23291 );
and ( n23295 , n23293 , n23294 );
nor ( n23296 , n23292 , n23295 );
not ( n23297 , n23296 );
not ( n23298 , n17935 );
not ( n23299 , n8663 );
or ( n23300 , n23298 , n23299 );
nand ( n23301 , n10864 , n17932 );
nand ( n23302 , n23300 , n23301 );
buf ( n23303 , n6349 );
buf ( n23304 , n6350 );
buf ( n23305 , n23304 );
not ( n23306 , n23305 );
buf ( n23307 , n6351 );
not ( n23308 , n23307 );
not ( n23309 , n23308 );
or ( n23310 , n23306 , n23309 );
not ( n23311 , n23304 );
buf ( n23312 , n23307 );
nand ( n23313 , n23311 , n23312 );
nand ( n23314 , n23310 , n23313 );
xor ( n23315 , n23303 , n23314 );
buf ( n23316 , n6352 );
buf ( n23317 , n6353 );
xor ( n23318 , n23316 , n23317 );
buf ( n23319 , n6354 );
nand ( n23320 , n10874 , n23319 );
xnor ( n23321 , n23318 , n23320 );
xnor ( n23322 , n23315 , n23321 );
buf ( n23323 , n23322 );
buf ( n23324 , n23323 );
not ( n23325 , n23324 );
and ( n23326 , n23302 , n23325 );
not ( n23327 , n23302 );
and ( n23328 , n23327 , n23324 );
nor ( n23329 , n23326 , n23328 );
not ( n23330 , n23329 );
not ( n23331 , n23330 );
not ( n23332 , n23331 );
buf ( n23333 , n11542 );
not ( n23334 , n23333 );
not ( n23335 , n11539 );
and ( n23336 , n23334 , n23335 );
and ( n23337 , n23333 , n11539 );
nor ( n23338 , n23336 , n23337 );
and ( n23339 , n23338 , n7367 );
not ( n23340 , n23338 );
not ( n23341 , n7370 );
and ( n23342 , n23340 , n23341 );
nor ( n23343 , n23339 , n23342 );
not ( n23344 , n7412 );
and ( n23345 , n23343 , n23344 );
not ( n23346 , n23343 );
and ( n23347 , n23346 , n7412 );
nor ( n23348 , n23345 , n23347 );
not ( n23349 , n23348 );
buf ( n23350 , n16596 );
xor ( n23351 , n19738 , n23350 );
xnor ( n23352 , n23351 , n21803 );
not ( n23353 , n23352 );
nand ( n23354 , n23349 , n23353 );
not ( n23355 , n23354 );
or ( n23356 , n23332 , n23355 );
or ( n23357 , n23354 , n23331 );
nand ( n23358 , n23356 , n23357 );
not ( n23359 , n23358 );
buf ( n23360 , n10743 );
xor ( n23361 , n10154 , n10174 );
buf ( n23362 , n10163 );
xnor ( n23363 , n23361 , n23362 );
buf ( n23364 , n23363 );
xor ( n23365 , n23360 , n23364 );
xnor ( n23366 , n23365 , n13254 );
not ( n23367 , n23366 );
buf ( n23368 , n12808 );
not ( n23369 , n23368 );
not ( n23370 , n23369 );
not ( n23371 , n9374 );
or ( n23372 , n23370 , n23371 );
not ( n23373 , n9374 );
nand ( n23374 , n23373 , n23368 );
nand ( n23375 , n23372 , n23374 );
not ( n23376 , n22802 );
buf ( n23377 , n23376 );
xnor ( n23378 , n23375 , n23377 );
not ( n23379 , n23378 );
nand ( n23380 , n23367 , n23379 );
not ( n23381 , n23380 );
xor ( n23382 , n18688 , n17707 );
not ( n23383 , n7991 );
buf ( n23384 , n23383 );
xnor ( n23385 , n23382 , n23384 );
not ( n23386 , n23385 );
and ( n23387 , n23381 , n23386 );
and ( n23388 , n23380 , n23385 );
nor ( n23389 , n23387 , n23388 );
not ( n23390 , n23389 );
or ( n23391 , n23359 , n23390 );
or ( n23392 , n23389 , n23358 );
nand ( n23393 , n23391 , n23392 );
not ( n23394 , n23393 );
or ( n23395 , n23297 , n23394 );
or ( n23396 , n23393 , n23296 );
nand ( n23397 , n23395 , n23396 );
buf ( n23398 , n23397 );
not ( n23399 , n23398 );
not ( n23400 , n23399 );
or ( n23401 , n23167 , n23400 );
not ( n23402 , n23166 );
nand ( n23403 , n23402 , n23398 );
nand ( n23404 , n23401 , n23403 );
not ( n23405 , n10351 );
not ( n23406 , n9641 );
not ( n23407 , n23406 );
not ( n23408 , n10394 );
not ( n23409 , n23408 );
or ( n23410 , n23407 , n23409 );
or ( n23411 , n10398 , n23406 );
nand ( n23412 , n23410 , n23411 );
not ( n23413 , n23412 );
and ( n23414 , n23405 , n23413 );
and ( n23415 , n10351 , n23412 );
nor ( n23416 , n23414 , n23415 );
not ( n23417 , n23416 );
not ( n23418 , n23417 );
not ( n23419 , n17544 );
not ( n23420 , n23419 );
not ( n23421 , n7772 );
and ( n23422 , n23420 , n23421 );
and ( n23423 , n23419 , n7772 );
nor ( n23424 , n23422 , n23423 );
and ( n23425 , n23424 , n17590 );
not ( n23426 , n23424 );
and ( n23427 , n23426 , n17603 );
nor ( n23428 , n23425 , n23427 );
not ( n23429 , n23428 );
buf ( n23430 , n6355 );
not ( n23431 , n23430 );
not ( n23432 , n18955 );
not ( n23433 , n23432 );
not ( n23434 , n23433 );
or ( n23435 , n23431 , n23434 );
or ( n23436 , n23433 , n23430 );
nand ( n23437 , n23435 , n23436 );
not ( n23438 , n23437 );
not ( n23439 , n19218 );
not ( n23440 , n23439 );
not ( n23441 , n19237 );
or ( n23442 , n23440 , n23441 );
nand ( n23443 , n19236 , n19218 );
nand ( n23444 , n23442 , n23443 );
not ( n23445 , n23444 );
not ( n23446 , n23445 );
or ( n23447 , n23438 , n23446 );
not ( n23448 , n23437 );
buf ( n23449 , n23444 );
nand ( n23450 , n23448 , n23449 );
nand ( n23451 , n23447 , n23450 );
nand ( n23452 , n23429 , n23451 );
not ( n23453 , n23452 );
or ( n23454 , n23418 , n23453 );
or ( n23455 , n23452 , n23417 );
nand ( n23456 , n23454 , n23455 );
not ( n23457 , n23456 );
not ( n23458 , n14577 );
not ( n23459 , n8409 );
and ( n23460 , n23458 , n23459 );
and ( n23461 , n14577 , n8409 );
nor ( n23462 , n23460 , n23461 );
and ( n23463 , n23462 , n14627 );
not ( n23464 , n23462 );
and ( n23465 , n23464 , n14624 );
nor ( n23466 , n23463 , n23465 );
not ( n23467 , n23466 );
not ( n23468 , n11131 );
nand ( n23469 , n23468 , n9785 );
not ( n23470 , n23469 );
nor ( n23471 , n9785 , n11135 );
nor ( n23472 , n23470 , n23471 );
not ( n23473 , n23472 );
not ( n23474 , n9844 );
not ( n23475 , n23474 );
or ( n23476 , n23473 , n23475 );
not ( n23477 , n23472 );
nand ( n23478 , n23477 , n9844 );
nand ( n23479 , n23476 , n23478 );
nand ( n23480 , n23467 , n23479 );
not ( n23481 , n23480 );
not ( n23482 , n10004 );
buf ( n23483 , n6356 );
buf ( n23484 , n23483 );
not ( n23485 , n23484 );
not ( n23486 , n21363 );
not ( n23487 , n23486 );
or ( n23488 , n23485 , n23487 );
not ( n23489 , n23483 );
nand ( n23490 , n23489 , n21364 );
nand ( n23491 , n23488 , n23490 );
buf ( n23492 , n6357 );
not ( n23493 , n23492 );
and ( n23494 , n23491 , n23493 );
not ( n23495 , n23491 );
buf ( n23496 , n23492 );
and ( n23497 , n23495 , n23496 );
nor ( n23498 , n23494 , n23497 );
buf ( n23499 , n6358 );
nand ( n23500 , n8954 , n23499 );
buf ( n23501 , n6359 );
buf ( n23502 , n23501 );
and ( n23503 , n23500 , n23502 );
not ( n23504 , n23500 );
not ( n23505 , n23501 );
and ( n23506 , n23504 , n23505 );
nor ( n23507 , n23503 , n23506 );
xor ( n23508 , n23498 , n23507 );
buf ( n23509 , n6360 );
nand ( n23510 , n8032 , n23509 );
buf ( n23511 , n6361 );
buf ( n23512 , n23511 );
and ( n23513 , n23510 , n23512 );
not ( n23514 , n23510 );
not ( n23515 , n23511 );
and ( n23516 , n23514 , n23515 );
nor ( n23517 , n23513 , n23516 );
xor ( n23518 , n23508 , n23517 );
not ( n23519 , n23518 );
not ( n23520 , n23519 );
not ( n23521 , n23520 );
or ( n23522 , n23482 , n23521 );
buf ( n23523 , n23518 );
or ( n23524 , n23523 , n10004 );
nand ( n23525 , n23522 , n23524 );
xor ( n23526 , n20134 , n20143 );
xnor ( n23527 , n23526 , n20153 );
not ( n23528 , n23527 );
not ( n23529 , n23528 );
not ( n23530 , n23529 );
and ( n23531 , n23525 , n23530 );
not ( n23532 , n23525 );
buf ( n23533 , n23527 );
and ( n23534 , n23532 , n23533 );
nor ( n23535 , n23531 , n23534 );
not ( n23536 , n23535 );
not ( n23537 , n23536 );
and ( n23538 , n23481 , n23537 );
and ( n23539 , n23480 , n23536 );
nor ( n23540 , n23538 , n23539 );
not ( n23541 , n23540 );
or ( n23542 , n23457 , n23541 );
or ( n23543 , n23540 , n23456 );
nand ( n23544 , n23542 , n23543 );
buf ( n23545 , n6362 );
buf ( n23546 , n23545 );
xor ( n23547 , n23546 , n19200 );
not ( n23548 , n20089 );
xnor ( n23549 , n23547 , n23548 );
not ( n23550 , n23549 );
xor ( n23551 , n11703 , n12651 );
buf ( n23552 , n16770 );
xor ( n23553 , n23552 , n16778 );
xor ( n23554 , n23553 , n16794 );
not ( n23555 , n23554 );
xnor ( n23556 , n23551 , n23555 );
not ( n23557 , n23556 );
nand ( n23558 , n23550 , n23557 );
not ( n23559 , n17956 );
not ( n23560 , n10865 );
or ( n23561 , n23559 , n23560 );
or ( n23562 , n10865 , n17956 );
nand ( n23563 , n23561 , n23562 );
and ( n23564 , n23563 , n23325 );
not ( n23565 , n23563 );
and ( n23566 , n23565 , n23324 );
nor ( n23567 , n23564 , n23566 );
not ( n23568 , n23567 );
and ( n23569 , n23558 , n23568 );
not ( n23570 , n23558 );
and ( n23571 , n23570 , n23567 );
nor ( n23572 , n23569 , n23571 );
and ( n23573 , n23544 , n23572 );
not ( n23574 , n23544 );
not ( n23575 , n23572 );
and ( n23576 , n23574 , n23575 );
nor ( n23577 , n23573 , n23576 );
not ( n23578 , n23577 );
not ( n23579 , n23578 );
not ( n23580 , n11926 );
not ( n23581 , n9461 );
not ( n23582 , n23581 );
or ( n23583 , n23580 , n23582 );
or ( n23584 , n9465 , n11926 );
nand ( n23585 , n23583 , n23584 );
not ( n23586 , n22536 );
not ( n23587 , n23586 );
xor ( n23588 , n23585 , n23587 );
not ( n23589 , n23588 );
not ( n23590 , n9253 );
not ( n23591 , n17716 );
or ( n23592 , n23590 , n23591 );
not ( n23593 , n17716 );
nand ( n23594 , n23593 , n9249 );
nand ( n23595 , n23592 , n23594 );
and ( n23596 , n23595 , n17721 );
not ( n23597 , n23595 );
buf ( n23598 , n8140 );
and ( n23599 , n23597 , n23598 );
nor ( n23600 , n23596 , n23599 );
nand ( n23601 , n23589 , n23600 );
not ( n23602 , n23601 );
xor ( n23603 , n14837 , n10912 );
xnor ( n23604 , n23603 , n13718 );
not ( n23605 , n23604 );
not ( n23606 , n23605 );
or ( n23607 , n23602 , n23606 );
or ( n23608 , n23605 , n23601 );
nand ( n23609 , n23607 , n23608 );
not ( n23610 , n23609 );
not ( n23611 , n21227 );
not ( n23612 , n21146 );
or ( n23613 , n23611 , n23612 );
not ( n23614 , n21146 );
nand ( n23615 , n23614 , n21223 );
nand ( n23616 , n23613 , n23615 );
buf ( n23617 , n22180 );
and ( n23618 , n23616 , n23617 );
not ( n23619 , n23616 );
buf ( n23620 , n22187 );
and ( n23621 , n23619 , n23620 );
nor ( n23622 , n23618 , n23621 );
not ( n23623 , n22345 );
not ( n23624 , n15974 );
or ( n23625 , n23623 , n23624 );
nand ( n23626 , n20846 , n22341 );
nand ( n23627 , n23625 , n23626 );
not ( n23628 , n22554 );
and ( n23629 , n23627 , n23628 );
not ( n23630 , n23627 );
and ( n23631 , n23630 , n22554 );
nor ( n23632 , n23629 , n23631 );
and ( n23633 , n23622 , n23632 );
buf ( n23634 , n12530 );
not ( n23635 , n23634 );
not ( n23636 , n10126 );
not ( n23637 , n23636 );
or ( n23638 , n23635 , n23637 );
or ( n23639 , n23636 , n23634 );
nand ( n23640 , n23638 , n23639 );
and ( n23641 , n23640 , n18528 );
not ( n23642 , n23640 );
not ( n23643 , n18528 );
and ( n23644 , n23642 , n23643 );
nor ( n23645 , n23641 , n23644 );
not ( n23646 , n23645 );
not ( n23647 , n23646 );
and ( n23648 , n23633 , n23647 );
not ( n23649 , n23633 );
and ( n23650 , n23649 , n23646 );
nor ( n23651 , n23648 , n23650 );
not ( n23652 , n23651 );
and ( n23653 , n23610 , n23652 );
and ( n23654 , n23609 , n23651 );
nor ( n23655 , n23653 , n23654 );
not ( n23656 , n23655 );
not ( n23657 , n23656 );
and ( n23658 , n23579 , n23657 );
and ( n23659 , n23578 , n23656 );
nor ( n23660 , n23658 , n23659 );
buf ( n23661 , n23660 );
and ( n23662 , n23404 , n23661 );
not ( n23663 , n23404 );
not ( n23664 , n23655 );
not ( n23665 , n23577 );
or ( n23666 , n23664 , n23665 );
not ( n23667 , n23577 );
nand ( n23668 , n23667 , n23656 );
nand ( n23669 , n23666 , n23668 );
not ( n23670 , n23669 );
not ( n23671 , n23670 );
and ( n23672 , n23663 , n23671 );
nor ( n23673 , n23662 , n23672 );
buf ( n23674 , n6363 );
buf ( n23675 , n23674 );
not ( n23676 , n23675 );
buf ( n23677 , n6364 );
not ( n23678 , n23677 );
not ( n23679 , n23678 );
or ( n23680 , n23676 , n23679 );
not ( n23681 , n23674 );
buf ( n23682 , n23677 );
nand ( n23683 , n23681 , n23682 );
nand ( n23684 , n23680 , n23683 );
buf ( n23685 , n6365 );
buf ( n23686 , n23685 );
and ( n23687 , n23684 , n23686 );
not ( n23688 , n23684 );
not ( n23689 , n23685 );
and ( n23690 , n23688 , n23689 );
nor ( n23691 , n23687 , n23690 );
xor ( n23692 , n23691 , n11767 );
xnor ( n23693 , n23692 , n23263 );
buf ( n23694 , n23693 );
xor ( n23695 , n20749 , n23694 );
xnor ( n23696 , n23695 , n8314 );
not ( n23697 , n23696 );
buf ( n23698 , n11082 );
xor ( n23699 , n11817 , n23698 );
xnor ( n23700 , n23699 , n9844 );
not ( n23701 , n13021 );
not ( n23702 , n21992 );
or ( n23703 , n23701 , n23702 );
nand ( n23704 , n14997 , n13017 );
nand ( n23705 , n23703 , n23704 );
and ( n23706 , n23705 , n15047 );
not ( n23707 , n23705 );
and ( n23708 , n23707 , n15055 );
nor ( n23709 , n23706 , n23708 );
not ( n23710 , n23709 );
nand ( n23711 , n23700 , n23710 );
not ( n23712 , n23711 );
or ( n23713 , n23697 , n23712 );
not ( n23714 , n23709 );
nand ( n23715 , n23714 , n23700 );
or ( n23716 , n23715 , n23696 );
nand ( n23717 , n23713 , n23716 );
not ( n23718 , n23717 );
not ( n23719 , n19315 );
not ( n23720 , n15290 );
or ( n23721 , n23719 , n23720 );
not ( n23722 , n19315 );
not ( n23723 , n15290 );
nand ( n23724 , n23722 , n23723 );
nand ( n23725 , n23721 , n23724 );
and ( n23726 , n23725 , n14225 );
not ( n23727 , n23725 );
and ( n23728 , n23727 , n14221 );
nor ( n23729 , n23726 , n23728 );
not ( n23730 , n23729 );
not ( n23731 , n9530 );
not ( n23732 , n13927 );
xor ( n23733 , n17260 , n23732 );
xnor ( n23734 , n23733 , n13934 );
not ( n23735 , n23734 );
or ( n23736 , n23731 , n23735 );
or ( n23737 , n23734 , n9530 );
nand ( n23738 , n23736 , n23737 );
not ( n23739 , n17040 );
and ( n23740 , n23738 , n23739 );
not ( n23741 , n23738 );
and ( n23742 , n23741 , n17044 );
nor ( n23743 , n23740 , n23742 );
nand ( n23744 , n23730 , n23743 );
not ( n23745 , n23744 );
not ( n23746 , n10533 );
not ( n23747 , n15744 );
or ( n23748 , n23746 , n23747 );
or ( n23749 , n15744 , n10533 );
nand ( n23750 , n23748 , n23749 );
nor ( n23751 , n23750 , n10010 );
not ( n23752 , n23751 );
nand ( n23753 , n10011 , n23750 );
nand ( n23754 , n23752 , n23753 );
not ( n23755 , n23754 );
and ( n23756 , n23745 , n23755 );
not ( n23757 , n23729 );
nand ( n23758 , n23757 , n23743 );
and ( n23759 , n23758 , n23754 );
nor ( n23760 , n23756 , n23759 );
not ( n23761 , n23760 );
not ( n23762 , n21750 );
not ( n23763 , n18461 );
or ( n23764 , n23762 , n23763 );
not ( n23765 , n21750 );
nand ( n23766 , n23765 , n15689 );
nand ( n23767 , n23764 , n23766 );
not ( n23768 , n18465 );
and ( n23769 , n23767 , n23768 );
not ( n23770 , n23767 );
and ( n23771 , n23770 , n18465 );
nor ( n23772 , n23769 , n23771 );
buf ( n23773 , n15412 );
not ( n23774 , n23773 );
not ( n23775 , n19746 );
or ( n23776 , n23774 , n23775 );
or ( n23777 , n19746 , n23773 );
nand ( n23778 , n23776 , n23777 );
not ( n23779 , n16983 );
and ( n23780 , n23778 , n23779 );
not ( n23781 , n23778 );
and ( n23782 , n23781 , n16983 );
nor ( n23783 , n23780 , n23782 );
nand ( n23784 , n23772 , n23783 );
buf ( n23785 , n6366 );
nand ( n23786 , n8966 , n23785 );
buf ( n23787 , n6367 );
not ( n23788 , n23787 );
and ( n23789 , n23786 , n23788 );
not ( n23790 , n23786 );
buf ( n23791 , n23787 );
and ( n23792 , n23790 , n23791 );
nor ( n23793 , n23789 , n23792 );
buf ( n23794 , n23793 );
not ( n23795 , n11745 );
xor ( n23796 , n11734 , n23795 );
xnor ( n23797 , n23796 , n11753 );
xor ( n23798 , n23794 , n23797 );
not ( n23799 , n16147 );
not ( n23800 , n23799 );
xnor ( n23801 , n23798 , n23800 );
not ( n23802 , n23801 );
and ( n23803 , n23784 , n23802 );
not ( n23804 , n23784 );
and ( n23805 , n23804 , n23801 );
nor ( n23806 , n23803 , n23805 );
not ( n23807 , n23806 );
and ( n23808 , n23761 , n23807 );
and ( n23809 , n23760 , n23806 );
nor ( n23810 , n23808 , n23809 );
not ( n23811 , n23810 );
or ( n23812 , n23718 , n23811 );
or ( n23813 , n23717 , n23810 );
nand ( n23814 , n23812 , n23813 );
not ( n23815 , n16146 );
not ( n23816 , n18003 );
or ( n23817 , n23815 , n23816 );
not ( n23818 , n16146 );
nand ( n23819 , n23818 , n18004 );
nand ( n23820 , n23817 , n23819 );
not ( n23821 , n13984 );
not ( n23822 , n23821 );
buf ( n23823 , n23822 );
and ( n23824 , n23820 , n23823 );
not ( n23825 , n23820 );
buf ( n23826 , n13991 );
buf ( n23827 , n23826 );
and ( n23828 , n23825 , n23827 );
nor ( n23829 , n23824 , n23828 );
not ( n23830 , n23829 );
not ( n23831 , n23830 );
buf ( n23832 , n22234 );
not ( n23833 , n23832 );
not ( n23834 , n21540 );
or ( n23835 , n23833 , n23834 );
or ( n23836 , n21540 , n23832 );
nand ( n23837 , n23835 , n23836 );
and ( n23838 , n23837 , n23239 );
not ( n23839 , n23837 );
buf ( n23840 , n20625 );
and ( n23841 , n23839 , n23840 );
nor ( n23842 , n23838 , n23841 );
not ( n23843 , n21422 );
not ( n23844 , n18166 );
or ( n23845 , n23843 , n23844 );
or ( n23846 , n18166 , n21422 );
nand ( n23847 , n23845 , n23846 );
and ( n23848 , n23847 , n7992 );
not ( n23849 , n23847 );
and ( n23850 , n23849 , n7993 );
nor ( n23851 , n23848 , n23850 );
nand ( n23852 , n23842 , n23851 );
not ( n23853 , n23852 );
or ( n23854 , n23831 , n23853 );
or ( n23855 , n23852 , n23830 );
nand ( n23856 , n23854 , n23855 );
not ( n23857 , n23856 );
buf ( n23858 , n22045 );
xor ( n23859 , n7409 , n23858 );
xnor ( n23860 , n23859 , n18261 );
not ( n23861 , n14724 );
not ( n23862 , n16257 );
or ( n23863 , n23861 , n23862 );
nand ( n23864 , n16258 , n14720 );
nand ( n23865 , n23863 , n23864 );
and ( n23866 , n23865 , n19622 );
not ( n23867 , n23865 );
and ( n23868 , n23867 , n23285 );
nor ( n23869 , n23866 , n23868 );
nand ( n23870 , n23860 , n23869 );
not ( n23871 , n23870 );
not ( n23872 , n12031 );
and ( n23873 , n12035 , n23872 );
not ( n23874 , n12035 );
and ( n23875 , n23874 , n12032 );
nor ( n23876 , n23873 , n23875 );
not ( n23877 , n23876 );
not ( n23878 , n14311 );
or ( n23879 , n23877 , n23878 );
or ( n23880 , n14311 , n23876 );
nand ( n23881 , n23879 , n23880 );
not ( n23882 , n20901 );
buf ( n23883 , n6368 );
not ( n23884 , n23883 );
not ( n23885 , n23884 );
or ( n23886 , n23882 , n23885 );
not ( n23887 , n20900 );
buf ( n23888 , n23883 );
nand ( n23889 , n23887 , n23888 );
nand ( n23890 , n23886 , n23889 );
buf ( n23891 , n6369 );
buf ( n23892 , n23891 );
and ( n23893 , n23890 , n23892 );
not ( n23894 , n23890 );
not ( n23895 , n23891 );
and ( n23896 , n23894 , n23895 );
nor ( n23897 , n23893 , n23896 );
not ( n23898 , n23897 );
xor ( n23899 , n23898 , n19000 );
buf ( n23900 , n6370 );
nand ( n23901 , n8455 , n23900 );
buf ( n23902 , n6371 );
buf ( n23903 , n23902 );
and ( n23904 , n23901 , n23903 );
not ( n23905 , n23901 );
not ( n23906 , n23902 );
and ( n23907 , n23905 , n23906 );
nor ( n23908 , n23904 , n23907 );
not ( n23909 , n23908 );
xnor ( n23910 , n23899 , n23909 );
not ( n23911 , n23910 );
not ( n23912 , n23911 );
and ( n23913 , n23881 , n23912 );
not ( n23914 , n23881 );
xor ( n23915 , n23897 , n23908 );
xnor ( n23916 , n23915 , n19001 );
buf ( n23917 , n23916 );
and ( n23918 , n23914 , n23917 );
nor ( n23919 , n23913 , n23918 );
not ( n23920 , n23919 );
and ( n23921 , n23871 , n23920 );
and ( n23922 , n23870 , n23919 );
nor ( n23923 , n23921 , n23922 );
not ( n23924 , n23923 );
or ( n23925 , n23857 , n23924 );
or ( n23926 , n23923 , n23856 );
nand ( n23927 , n23925 , n23926 );
and ( n23928 , n23814 , n23927 );
not ( n23929 , n23814 );
not ( n23930 , n23927 );
and ( n23931 , n23929 , n23930 );
nor ( n23932 , n23928 , n23931 );
not ( n23933 , n23932 );
not ( n23934 , n23933 );
not ( n23935 , n8617 );
not ( n23936 , n6982 );
or ( n23937 , n23935 , n23936 );
not ( n23938 , n8617 );
nand ( n23939 , n23938 , n6977 );
nand ( n23940 , n23937 , n23939 );
and ( n23941 , n23940 , n7029 );
not ( n23942 , n23940 );
and ( n23943 , n23942 , n7025 );
nor ( n23944 , n23941 , n23943 );
not ( n23945 , n18460 );
not ( n23946 , n23945 );
buf ( n23947 , n6372 );
buf ( n23948 , n23947 );
not ( n23949 , n23948 );
buf ( n23950 , n6373 );
not ( n23951 , n23950 );
not ( n23952 , n23951 );
or ( n23953 , n23949 , n23952 );
not ( n23954 , n23947 );
buf ( n23955 , n23950 );
nand ( n23956 , n23954 , n23955 );
nand ( n23957 , n23953 , n23956 );
buf ( n23958 , n6374 );
buf ( n23959 , n23958 );
and ( n23960 , n23957 , n23959 );
not ( n23961 , n23957 );
not ( n23962 , n23958 );
and ( n23963 , n23961 , n23962 );
nor ( n23964 , n23960 , n23963 );
buf ( n23965 , n6375 );
nand ( n23966 , n7197 , n23965 );
buf ( n23967 , n6376 );
buf ( n23968 , n23967 );
and ( n23969 , n23966 , n23968 );
not ( n23970 , n23966 );
not ( n23971 , n23967 );
and ( n23972 , n23970 , n23971 );
nor ( n23973 , n23969 , n23972 );
xor ( n23974 , n23964 , n23973 );
buf ( n23975 , n6377 );
nand ( n23976 , n8223 , n23975 );
buf ( n23977 , n6378 );
not ( n23978 , n23977 );
and ( n23979 , n23976 , n23978 );
not ( n23980 , n23976 );
buf ( n23981 , n23977 );
and ( n23982 , n23980 , n23981 );
nor ( n23983 , n23979 , n23982 );
xnor ( n23984 , n23974 , n23983 );
not ( n23985 , n23984 );
or ( n23986 , n23946 , n23985 );
or ( n23987 , n23984 , n23945 );
nand ( n23988 , n23986 , n23987 );
and ( n23989 , n23988 , n10090 );
not ( n23990 , n23988 );
not ( n23991 , n10088 );
not ( n23992 , n23991 );
and ( n23993 , n23990 , n23992 );
nor ( n23994 , n23989 , n23993 );
not ( n23995 , n23994 );
nand ( n23996 , n23944 , n23995 );
not ( n23997 , n23996 );
not ( n23998 , n13259 );
xor ( n23999 , n20386 , n20405 );
not ( n24000 , n20395 );
xnor ( n24001 , n23999 , n24000 );
not ( n24002 , n24001 );
or ( n24003 , n23998 , n24002 );
or ( n24004 , n24001 , n13259 );
nand ( n24005 , n24003 , n24004 );
and ( n24006 , n24005 , n14793 );
not ( n24007 , n24005 );
and ( n24008 , n24007 , n14794 );
nor ( n24009 , n24006 , n24008 );
not ( n24010 , n24009 );
and ( n24011 , n23997 , n24010 );
and ( n24012 , n23996 , n24009 );
nor ( n24013 , n24011 , n24012 );
buf ( n24014 , n24013 );
not ( n24015 , n24014 );
not ( n24016 , n24015 );
buf ( n24017 , n6379 );
buf ( n24018 , n24017 );
not ( n24019 , n24018 );
buf ( n24020 , n6380 );
not ( n24021 , n24020 );
not ( n24022 , n24021 );
or ( n24023 , n24019 , n24022 );
not ( n24024 , n24017 );
buf ( n24025 , n24020 );
nand ( n24026 , n24024 , n24025 );
nand ( n24027 , n24023 , n24026 );
buf ( n24028 , n6381 );
not ( n24029 , n24028 );
and ( n24030 , n24027 , n24029 );
not ( n24031 , n24027 );
buf ( n24032 , n24028 );
and ( n24033 , n24031 , n24032 );
nor ( n24034 , n24030 , n24033 );
buf ( n24035 , n6382 );
nand ( n24036 , n7977 , n24035 );
buf ( n24037 , n6383 );
buf ( n24038 , n24037 );
and ( n24039 , n24036 , n24038 );
not ( n24040 , n24036 );
not ( n24041 , n24037 );
and ( n24042 , n24040 , n24041 );
nor ( n24043 , n24039 , n24042 );
xor ( n24044 , n24034 , n24043 );
buf ( n24045 , n6384 );
nand ( n24046 , n11946 , n24045 );
buf ( n24047 , n6385 );
not ( n24048 , n24047 );
and ( n24049 , n24046 , n24048 );
not ( n24050 , n24046 );
buf ( n24051 , n24047 );
and ( n24052 , n24050 , n24051 );
nor ( n24053 , n24049 , n24052 );
xor ( n24054 , n24044 , n24053 );
buf ( n24055 , n24054 );
not ( n24056 , n24055 );
xor ( n24057 , n10931 , n24056 );
buf ( n24058 , n9277 );
xnor ( n24059 , n24057 , n24058 );
buf ( n24060 , n7011 );
not ( n24061 , n24060 );
buf ( n24062 , n6386 );
buf ( n24063 , n24062 );
not ( n24064 , n24063 );
buf ( n24065 , n6387 );
not ( n24066 , n24065 );
not ( n24067 , n24066 );
or ( n24068 , n24064 , n24067 );
not ( n24069 , n24062 );
buf ( n24070 , n24065 );
nand ( n24071 , n24069 , n24070 );
nand ( n24072 , n24068 , n24071 );
and ( n24073 , n24072 , n16109 );
not ( n24074 , n24072 );
not ( n24075 , n16108 );
and ( n24076 , n24074 , n24075 );
nor ( n24077 , n24073 , n24076 );
xor ( n24078 , n24077 , n23793 );
xnor ( n24079 , n24078 , n18786 );
not ( n24080 , n24079 );
buf ( n24081 , n24080 );
not ( n24082 , n24081 );
or ( n24083 , n24061 , n24082 );
or ( n24084 , n24081 , n24060 );
nand ( n24085 , n24083 , n24084 );
buf ( n24086 , n18154 );
and ( n24087 , n24085 , n24086 );
not ( n24088 , n24085 );
not ( n24089 , n24086 );
and ( n24090 , n24088 , n24089 );
nor ( n24091 , n24087 , n24090 );
not ( n24092 , n24091 );
nand ( n24093 , n24059 , n24092 );
not ( n24094 , n24093 );
buf ( n24095 , n12208 );
not ( n24096 , n24095 );
not ( n24097 , n23239 );
or ( n24098 , n24096 , n24097 );
or ( n24099 , n23239 , n24095 );
nand ( n24100 , n24098 , n24099 );
and ( n24101 , n24100 , n20631 );
not ( n24102 , n24100 );
and ( n24103 , n24102 , n20628 );
nor ( n24104 , n24101 , n24103 );
not ( n24105 , n24104 );
not ( n24106 , n24105 );
and ( n24107 , n24094 , n24106 );
and ( n24108 , n24093 , n24105 );
nor ( n24109 , n24107 , n24108 );
not ( n24110 , n24109 );
not ( n24111 , n24110 );
buf ( n24112 , n11062 );
xor ( n24113 , n24112 , n11074 );
xor ( n24114 , n24113 , n11081 );
buf ( n24115 , n24114 );
xor ( n24116 , n11797 , n24115 );
xnor ( n24117 , n24116 , n9844 );
not ( n24118 , n24117 );
buf ( n24119 , n7986 );
not ( n24120 , n24119 );
not ( n24121 , n22860 );
or ( n24122 , n24120 , n24121 );
not ( n24123 , n24119 );
nand ( n24124 , n24123 , n22864 );
nand ( n24125 , n24122 , n24124 );
and ( n24126 , n24125 , n22867 );
not ( n24127 , n24125 );
and ( n24128 , n24127 , n14508 );
nor ( n24129 , n24126 , n24128 );
not ( n24130 , n24129 );
nand ( n24131 , n24118 , n24130 );
not ( n24132 , n23363 );
not ( n24133 , n24132 );
xor ( n24134 , n10708 , n24133 );
xnor ( n24135 , n24134 , n13254 );
and ( n24136 , n24131 , n24135 );
not ( n24137 , n24131 );
not ( n24138 , n24135 );
and ( n24139 , n24137 , n24138 );
nor ( n24140 , n24136 , n24139 );
not ( n24141 , n24140 );
not ( n24142 , n24141 );
or ( n24143 , n24111 , n24142 );
nand ( n24144 , n24140 , n24109 );
nand ( n24145 , n24143 , n24144 );
not ( n24146 , n11321 );
not ( n24147 , n22606 );
or ( n24148 , n24146 , n24147 );
or ( n24149 , n22606 , n11321 );
nand ( n24150 , n24148 , n24149 );
and ( n24151 , n24150 , n17332 );
not ( n24152 , n24150 );
and ( n24153 , n24152 , n17347 );
nor ( n24154 , n24151 , n24153 );
not ( n24155 , n24154 );
not ( n24156 , n24155 );
not ( n24157 , n20903 );
buf ( n24158 , n14308 );
not ( n24159 , n24158 );
not ( n24160 , n24159 );
not ( n24161 , n12341 );
or ( n24162 , n24160 , n24161 );
nand ( n24163 , n13294 , n24158 );
nand ( n24164 , n24162 , n24163 );
not ( n24165 , n24164 );
and ( n24166 , n24157 , n24165 );
and ( n24167 , n12376 , n24164 );
nor ( n24168 , n24166 , n24167 );
not ( n24169 , n24168 );
nand ( n24170 , n24156 , n24169 );
not ( n24171 , n24170 );
not ( n24172 , n15387 );
not ( n24173 , n19739 );
or ( n24174 , n24172 , n24173 );
not ( n24175 , n15387 );
nand ( n24176 , n24175 , n19746 );
nand ( n24177 , n24174 , n24176 );
and ( n24178 , n24177 , n16984 );
not ( n24179 , n24177 );
and ( n24180 , n24179 , n16983 );
nor ( n24181 , n24178 , n24180 );
not ( n24182 , n24181 );
not ( n24183 , n24182 );
and ( n24184 , n24171 , n24183 );
and ( n24185 , n24170 , n24182 );
nor ( n24186 , n24184 , n24185 );
not ( n24187 , n24186 );
not ( n24188 , n24009 );
not ( n24189 , n23944 );
nand ( n24190 , n24188 , n24189 );
not ( n24191 , n17882 );
not ( n24192 , n15254 );
not ( n24193 , n22180 );
or ( n24194 , n24192 , n24193 );
not ( n24195 , n15254 );
nand ( n24196 , n24195 , n22187 );
nand ( n24197 , n24194 , n24196 );
not ( n24198 , n24197 );
or ( n24199 , n24191 , n24198 );
or ( n24200 , n22139 , n24197 );
nand ( n24201 , n24199 , n24200 );
buf ( n24202 , n24201 );
xnor ( n24203 , n24190 , n24202 );
not ( n24204 , n24203 );
or ( n24205 , n24187 , n24204 );
or ( n24206 , n24203 , n24186 );
nand ( n24207 , n24205 , n24206 );
not ( n24208 , n16212 );
not ( n24209 , n6658 );
not ( n24210 , n24209 );
buf ( n24211 , n12430 );
not ( n24212 , n24211 );
and ( n24213 , n24210 , n24212 );
not ( n24214 , n6659 );
and ( n24215 , n24214 , n24211 );
nor ( n24216 , n24213 , n24215 );
not ( n24217 , n24216 );
or ( n24218 , n24208 , n24217 );
or ( n24219 , n24216 , n16212 );
nand ( n24220 , n24218 , n24219 );
not ( n24221 , n16125 );
not ( n24222 , n18003 );
or ( n24223 , n24221 , n24222 );
or ( n24224 , n18003 , n16125 );
nand ( n24225 , n24223 , n24224 );
and ( n24226 , n24225 , n23827 );
not ( n24227 , n24225 );
and ( n24228 , n24227 , n23823 );
nor ( n24229 , n24226 , n24228 );
not ( n24230 , n24229 );
nand ( n24231 , n24220 , n24230 );
not ( n24232 , n24231 );
xor ( n24233 , n15024 , n11394 );
xnor ( n24234 , n24233 , n23003 );
not ( n24235 , n24234 );
not ( n24236 , n24235 );
and ( n24237 , n24232 , n24236 );
and ( n24238 , n24231 , n24235 );
nor ( n24239 , n24237 , n24238 );
and ( n24240 , n24207 , n24239 );
not ( n24241 , n24207 );
not ( n24242 , n24239 );
and ( n24243 , n24241 , n24242 );
nor ( n24244 , n24240 , n24243 );
xor ( n24245 , n24145 , n24244 );
not ( n24246 , n24245 );
or ( n24247 , n24016 , n24246 );
not ( n24248 , n24244 );
not ( n24249 , n24248 );
not ( n24250 , n24145 );
not ( n24251 , n24250 );
or ( n24252 , n24249 , n24251 );
nand ( n24253 , n24145 , n24244 );
nand ( n24254 , n24252 , n24253 );
nand ( n24255 , n24254 , n24014 );
nand ( n24256 , n24247 , n24255 );
not ( n24257 , n24256 );
or ( n24258 , n23934 , n24257 );
buf ( n24259 , n23932 );
not ( n24260 , n24259 );
or ( n24261 , n24256 , n24260 );
nand ( n24262 , n24258 , n24261 );
not ( n24263 , n24262 );
nand ( n24264 , n23673 , n24263 );
not ( n24265 , n20590 );
not ( n24266 , n7879 );
or ( n24267 , n24265 , n24266 );
or ( n24268 , n7879 , n20590 );
nand ( n24269 , n24267 , n24268 );
not ( n24270 , n12833 );
and ( n24271 , n24269 , n24270 );
not ( n24272 , n24269 );
and ( n24273 , n24272 , n17688 );
nor ( n24274 , n24271 , n24273 );
not ( n24275 , n24274 );
nand ( n24276 , n16199 , n24275 );
not ( n24277 , n24276 );
buf ( n24278 , n7785 );
not ( n24279 , n24278 );
not ( n24280 , n23419 );
not ( n24281 , n24280 );
or ( n24282 , n24279 , n24281 );
not ( n24283 , n17546 );
or ( n24284 , n24283 , n24278 );
nand ( n24285 , n24282 , n24284 );
buf ( n24286 , n17603 );
and ( n24287 , n24285 , n24286 );
not ( n24288 , n24285 );
and ( n24289 , n24288 , n17590 );
nor ( n24290 , n24287 , n24289 );
not ( n24291 , n24290 );
and ( n24292 , n24277 , n24291 );
and ( n24293 , n24276 , n24290 );
nor ( n24294 , n24292 , n24293 );
not ( n24295 , n24294 );
not ( n24296 , n24290 );
nand ( n24297 , n24274 , n24296 );
buf ( n24298 , n16106 );
and ( n24299 , n24297 , n24298 );
not ( n24300 , n24297 );
not ( n24301 , n24298 );
and ( n24302 , n24300 , n24301 );
nor ( n24303 , n24299 , n24302 );
not ( n24304 , n24303 );
not ( n24305 , n24304 );
buf ( n24306 , n8122 );
not ( n24307 , n24306 );
not ( n24308 , n6685 );
or ( n24309 , n24307 , n24308 );
or ( n24310 , n6685 , n24306 );
nand ( n24311 , n24309 , n24310 );
buf ( n24312 , n22959 );
and ( n24313 , n24311 , n24312 );
not ( n24314 , n24311 );
not ( n24315 , n22959 );
and ( n24316 , n24314 , n24315 );
nor ( n24317 , n24313 , n24316 );
not ( n24318 , n19903 );
not ( n24319 , n17611 );
or ( n24320 , n24318 , n24319 );
not ( n24321 , n17611 );
nand ( n24322 , n24321 , n19899 );
nand ( n24323 , n24320 , n24322 );
and ( n24324 , n24323 , n13744 );
not ( n24325 , n24323 );
and ( n24326 , n24325 , n13731 );
nor ( n24327 , n24324 , n24326 );
nand ( n24328 , n24317 , n24327 );
and ( n24329 , n24328 , n16264 );
not ( n24330 , n24328 );
not ( n24331 , n16264 );
and ( n24332 , n24330 , n24331 );
nor ( n24333 , n24329 , n24332 );
not ( n24334 , n24333 );
not ( n24335 , n24334 );
or ( n24336 , n24305 , n24335 );
nand ( n24337 , n24333 , n24303 );
nand ( n24338 , n24336 , n24337 );
not ( n24339 , n24338 );
not ( n24340 , n24339 );
not ( n24341 , n8012 );
buf ( n24342 , n6388 );
nand ( n24343 , n8537 , n24342 );
buf ( n24344 , n6389 );
buf ( n24345 , n24344 );
and ( n24346 , n24343 , n24345 );
not ( n24347 , n24343 );
not ( n24348 , n24344 );
and ( n24349 , n24347 , n24348 );
nor ( n24350 , n24346 , n24349 );
not ( n24351 , n24350 );
buf ( n24352 , n6390 );
nand ( n24353 , n7912 , n24352 );
buf ( n24354 , n6391 );
not ( n24355 , n24354 );
and ( n24356 , n24353 , n24355 );
not ( n24357 , n24353 );
buf ( n24358 , n24354 );
and ( n24359 , n24357 , n24358 );
nor ( n24360 , n24356 , n24359 );
not ( n24361 , n24360 );
or ( n24362 , n24351 , n24361 );
or ( n24363 , n24350 , n24360 );
nand ( n24364 , n24362 , n24363 );
not ( n24365 , n18023 );
buf ( n24366 , n6392 );
not ( n24367 , n24366 );
not ( n24368 , n24367 );
or ( n24369 , n24365 , n24368 );
not ( n24370 , n18022 );
buf ( n24371 , n24366 );
nand ( n24372 , n24370 , n24371 );
nand ( n24373 , n24369 , n24372 );
buf ( n24374 , n6393 );
buf ( n24375 , n24374 );
and ( n24376 , n24373 , n24375 );
not ( n24377 , n24373 );
not ( n24378 , n24374 );
and ( n24379 , n24377 , n24378 );
nor ( n24380 , n24376 , n24379 );
xnor ( n24381 , n24364 , n24380 );
not ( n24382 , n24381 );
or ( n24383 , n24341 , n24382 );
xor ( n24384 , n24380 , n24350 );
xnor ( n24385 , n24384 , n24360 );
nand ( n24386 , n24385 , n8008 );
nand ( n24387 , n24383 , n24386 );
not ( n24388 , n24387 );
not ( n24389 , n22863 );
and ( n24390 , n24388 , n24389 );
and ( n24391 , n24387 , n22860 );
nor ( n24392 , n24390 , n24391 );
not ( n24393 , n24392 );
not ( n24394 , n16905 );
not ( n24395 , n24394 );
not ( n24396 , n18710 );
or ( n24397 , n24395 , n24396 );
or ( n24398 , n18710 , n24394 );
nand ( n24399 , n24397 , n24398 );
and ( n24400 , n24399 , n12342 );
not ( n24401 , n24399 );
and ( n24402 , n24401 , n18714 );
nor ( n24403 , n24400 , n24402 );
nand ( n24404 , n24393 , n24403 );
and ( n24405 , n24404 , n15842 );
not ( n24406 , n24404 );
and ( n24407 , n24406 , n15843 );
nor ( n24408 , n24405 , n24407 );
not ( n24409 , n24408 );
not ( n24410 , n24409 );
not ( n24411 , n18474 );
buf ( n24412 , n6394 );
not ( n24413 , n24412 );
not ( n24414 , n24413 );
or ( n24415 , n24411 , n24414 );
not ( n24416 , n18473 );
buf ( n24417 , n24412 );
nand ( n24418 , n24416 , n24417 );
nand ( n24419 , n24415 , n24418 );
not ( n24420 , n21300 );
and ( n24421 , n24419 , n24420 );
not ( n24422 , n24419 );
and ( n24423 , n24422 , n21301 );
nor ( n24424 , n24421 , n24423 );
buf ( n24425 , n6395 );
nand ( n24426 , n10372 , n24425 );
buf ( n24427 , n6396 );
buf ( n24428 , n24427 );
and ( n24429 , n24426 , n24428 );
not ( n24430 , n24426 );
not ( n24431 , n24427 );
and ( n24432 , n24430 , n24431 );
nor ( n24433 , n24429 , n24432 );
xor ( n24434 , n24424 , n24433 );
xnor ( n24435 , n24434 , n20427 );
buf ( n24436 , n24435 );
not ( n24437 , n24436 );
not ( n24438 , n17872 );
buf ( n24439 , n6397 );
buf ( n24440 , n24439 );
not ( n24441 , n24440 );
not ( n24442 , n7628 );
not ( n24443 , n24442 );
or ( n24444 , n24441 , n24443 );
not ( n24445 , n24439 );
nand ( n24446 , n24445 , n7629 );
nand ( n24447 , n24444 , n24446 );
and ( n24448 , n24447 , n19557 );
not ( n24449 , n24447 );
and ( n24450 , n24449 , n19554 );
nor ( n24451 , n24448 , n24450 );
buf ( n24452 , n6398 );
nand ( n24453 , n8454 , n24452 );
buf ( n24454 , n6399 );
buf ( n24455 , n24454 );
and ( n24456 , n24453 , n24455 );
not ( n24457 , n24453 );
not ( n24458 , n24454 );
and ( n24459 , n24457 , n24458 );
nor ( n24460 , n24456 , n24459 );
xor ( n24461 , n24451 , n24460 );
buf ( n24462 , n6400 );
nand ( n24463 , n6558 , n24462 );
buf ( n24464 , n6401 );
not ( n24465 , n24464 );
and ( n24466 , n24463 , n24465 );
not ( n24467 , n24463 );
buf ( n24468 , n24464 );
and ( n24469 , n24467 , n24468 );
nor ( n24470 , n24466 , n24469 );
xnor ( n24471 , n24461 , n24470 );
buf ( n24472 , n24471 );
not ( n24473 , n24472 );
or ( n24474 , n24438 , n24473 );
not ( n24475 , n24451 );
xor ( n24476 , n24475 , n24460 );
xnor ( n24477 , n24476 , n24470 );
nand ( n24478 , n24477 , n17869 );
nand ( n24479 , n24474 , n24478 );
not ( n24480 , n24479 );
or ( n24481 , n24437 , n24480 );
or ( n24482 , n24479 , n24436 );
nand ( n24483 , n24481 , n24482 );
nand ( n24484 , n15383 , n24483 );
and ( n24485 , n24484 , n15477 );
not ( n24486 , n24484 );
and ( n24487 , n24486 , n15478 );
nor ( n24488 , n24485 , n24487 );
not ( n24489 , n24488 );
not ( n24490 , n24489 );
or ( n24491 , n24410 , n24490 );
nand ( n24492 , n24488 , n24408 );
nand ( n24493 , n24491 , n24492 );
buf ( n24494 , n6402 );
not ( n24495 , n24494 );
buf ( n24496 , n6403 );
buf ( n24497 , n24496 );
and ( n24498 , n24495 , n24497 );
not ( n24499 , n24495 );
not ( n24500 , n24496 );
and ( n24501 , n24499 , n24500 );
nor ( n24502 , n24498 , n24501 );
xor ( n24503 , n11628 , n24502 );
buf ( n24504 , n6404 );
not ( n24505 , n24504 );
buf ( n24506 , n6405 );
nand ( n24507 , n6916 , n24506 );
buf ( n24508 , n6406 );
buf ( n24509 , n24508 );
and ( n24510 , n24507 , n24509 );
not ( n24511 , n24507 );
not ( n24512 , n24508 );
and ( n24513 , n24511 , n24512 );
nor ( n24514 , n24510 , n24513 );
not ( n24515 , n24514 );
or ( n24516 , n24505 , n24515 );
or ( n24517 , n24514 , n24504 );
nand ( n24518 , n24516 , n24517 );
xnor ( n24519 , n24503 , n24518 );
xor ( n24520 , n19170 , n24519 );
buf ( n24521 , n17139 );
and ( n24522 , n24520 , n24521 );
not ( n24523 , n24520 );
buf ( n24524 , n9898 );
and ( n24525 , n24523 , n24524 );
nor ( n24526 , n24522 , n24525 );
not ( n24527 , n24526 );
not ( n24528 , n18103 );
not ( n24529 , n9513 );
or ( n24530 , n24528 , n24529 );
or ( n24531 , n9513 , n18103 );
nand ( n24532 , n24530 , n24531 );
xnor ( n24533 , n24532 , n9562 );
nand ( n24534 , n24527 , n24533 );
not ( n24535 , n24534 );
buf ( n24536 , n15642 );
not ( n24537 , n24536 );
not ( n24538 , n24537 );
and ( n24539 , n24535 , n24538 );
and ( n24540 , n24534 , n24537 );
nor ( n24541 , n24539 , n24540 );
and ( n24542 , n24493 , n24541 );
not ( n24543 , n24493 );
not ( n24544 , n24541 );
and ( n24545 , n24543 , n24544 );
nor ( n24546 , n24542 , n24545 );
not ( n24547 , n24546 );
not ( n24548 , n24547 );
or ( n24549 , n24340 , n24548 );
nand ( n24550 , n24546 , n24338 );
nand ( n24551 , n24549 , n24550 );
not ( n24552 , n24551 );
or ( n24553 , n24295 , n24552 );
or ( n24554 , n24551 , n24294 );
nand ( n24555 , n24553 , n24554 );
not ( n24556 , n24555 );
xor ( n24557 , n19456 , n17614 );
xnor ( n24558 , n24557 , n13547 );
not ( n24559 , n24558 );
buf ( n24560 , n20828 );
xor ( n24561 , n17977 , n24560 );
xor ( n24562 , n24561 , n23324 );
not ( n24563 , n24562 );
nand ( n24564 , n24559 , n24563 );
not ( n24565 , n16687 );
xor ( n24566 , n24564 , n24565 );
not ( n24567 , n24566 );
not ( n24568 , n24567 );
xor ( n24569 , n20755 , n23694 );
not ( n24570 , n8317 );
xnor ( n24571 , n24569 , n24570 );
not ( n24572 , n24571 );
not ( n24573 , n14967 );
not ( n24574 , n18821 );
not ( n24575 , n24574 );
not ( n24576 , n24575 );
or ( n24577 , n24573 , n24576 );
or ( n24578 , n18822 , n14967 );
nand ( n24579 , n24577 , n24578 );
and ( n24580 , n24579 , n23003 );
not ( n24581 , n24579 );
buf ( n24582 , n22976 );
xor ( n24583 , n24582 , n22986 );
xnor ( n24584 , n24583 , n22993 );
and ( n24585 , n24581 , n24584 );
nor ( n24586 , n24580 , n24585 );
not ( n24587 , n24586 );
nand ( n24588 , n24572 , n24587 );
not ( n24589 , n24588 );
not ( n24590 , n16372 );
and ( n24591 , n24589 , n24590 );
and ( n24592 , n24588 , n16372 );
nor ( n24593 , n24591 , n24592 );
not ( n24594 , n24593 );
not ( n24595 , n24594 );
or ( n24596 , n24568 , n24595 );
nand ( n24597 , n24593 , n24566 );
nand ( n24598 , n24596 , n24597 );
buf ( n24599 , n6407 );
not ( n24600 , n24599 );
not ( n24601 , n23916 );
or ( n24602 , n24600 , n24601 );
or ( n24603 , n23916 , n24599 );
nand ( n24604 , n24602 , n24603 );
and ( n24605 , n24604 , n21361 );
not ( n24606 , n24604 );
and ( n24607 , n24606 , n21360 );
nor ( n24608 , n24605 , n24607 );
not ( n24609 , n10063 );
not ( n24610 , n15428 );
or ( n24611 , n24609 , n24610 );
or ( n24612 , n15424 , n10063 );
nand ( n24613 , n24611 , n24612 );
and ( n24614 , n24613 , n15475 );
not ( n24615 , n24613 );
and ( n24616 , n24615 , n15474 );
nor ( n24617 , n24614 , n24616 );
not ( n24618 , n24617 );
nand ( n24619 , n24608 , n24618 );
not ( n24620 , n24619 );
not ( n24621 , n16807 );
and ( n24622 , n24620 , n24621 );
and ( n24623 , n24619 , n16807 );
nor ( n24624 , n24622 , n24623 );
not ( n24625 , n24624 );
not ( n24626 , n14949 );
not ( n24627 , n7502 );
not ( n24628 , n14911 );
or ( n24629 , n24627 , n24628 );
or ( n24630 , n14911 , n7502 );
nand ( n24631 , n24629 , n24630 );
not ( n24632 , n24631 );
or ( n24633 , n24626 , n24632 );
not ( n24634 , n24631 );
nand ( n24635 , n24634 , n14942 );
nand ( n24636 , n24633 , n24635 );
not ( n24637 , n24636 );
not ( n24638 , n8245 );
not ( n24639 , n17332 );
or ( n24640 , n24638 , n24639 );
not ( n24641 , n8245 );
nand ( n24642 , n24641 , n17345 );
nand ( n24643 , n24640 , n24642 );
and ( n24644 , n24643 , n8992 );
not ( n24645 , n24643 );
not ( n24646 , n7270 );
and ( n24647 , n24645 , n24646 );
nor ( n24648 , n24644 , n24647 );
not ( n24649 , n24648 );
nand ( n24650 , n24637 , n24649 );
not ( n24651 , n16920 );
and ( n24652 , n24650 , n24651 );
not ( n24653 , n24650 );
and ( n24654 , n24653 , n16920 );
nor ( n24655 , n24652 , n24654 );
not ( n24656 , n24655 );
or ( n24657 , n24625 , n24656 );
or ( n24658 , n24655 , n24624 );
nand ( n24659 , n24657 , n24658 );
not ( n24660 , n24385 );
not ( n24661 , n24660 );
xor ( n24662 , n18171 , n24661 );
buf ( n24663 , n6408 );
buf ( n24664 , n6409 );
buf ( n24665 , n24664 );
not ( n24666 , n24665 );
buf ( n24667 , n6410 );
not ( n24668 , n24667 );
not ( n24669 , n24668 );
or ( n24670 , n24666 , n24669 );
not ( n24671 , n24664 );
buf ( n24672 , n24667 );
nand ( n24673 , n24671 , n24672 );
nand ( n24674 , n24670 , n24673 );
xor ( n24675 , n24663 , n24674 );
buf ( n24676 , n6411 );
xor ( n24677 , n24676 , n8679 );
xnor ( n24678 , n24677 , n8677 );
xnor ( n24679 , n24675 , n24678 );
not ( n24680 , n24679 );
not ( n24681 , n24680 );
not ( n24682 , n24681 );
xnor ( n24683 , n24662 , n24682 );
not ( n24684 , n24683 );
not ( n24685 , n9113 );
not ( n24686 , n19200 );
or ( n24687 , n24685 , n24686 );
or ( n24688 , n19200 , n9113 );
nand ( n24689 , n24687 , n24688 );
and ( n24690 , n24689 , n21060 );
not ( n24691 , n24689 );
and ( n24692 , n24691 , n21063 );
nor ( n24693 , n24690 , n24692 );
not ( n24694 , n24693 );
nand ( n24695 , n24684 , n24694 );
not ( n24696 , n24695 );
buf ( n24697 , n16499 );
not ( n24698 , n24697 );
and ( n24699 , n24696 , n24698 );
and ( n24700 , n24695 , n24697 );
nor ( n24701 , n24699 , n24700 );
and ( n24702 , n24659 , n24701 );
not ( n24703 , n24659 );
not ( n24704 , n24701 );
and ( n24705 , n24703 , n24704 );
nor ( n24706 , n24702 , n24705 );
and ( n24707 , n24598 , n24706 );
not ( n24708 , n24598 );
not ( n24709 , n24706 );
and ( n24710 , n24708 , n24709 );
nor ( n24711 , n24707 , n24710 );
not ( n24712 , n24711 );
not ( n24713 , n24712 );
not ( n24714 , n24713 );
and ( n24715 , n24556 , n24714 );
and ( n24716 , n24555 , n24713 );
nor ( n24717 , n24715 , n24716 );
nor ( n24718 , n24717 , n20975 );
not ( n24719 , n24718 );
or ( n24720 , n24264 , n24719 );
not ( n24721 , n24717 );
not ( n24722 , n24721 );
not ( n24723 , n23673 );
or ( n24724 , n24722 , n24723 );
nor ( n24725 , n24263 , n17807 );
nand ( n24726 , n24724 , n24725 );
buf ( n24727 , n13353 );
nand ( n24728 , n24727 , n7374 );
nand ( n24729 , n24720 , n24726 , n24728 );
buf ( n24730 , n24729 );
buf ( n24731 , n24730 );
buf ( n24732 , n20975 );
not ( n24733 , n24732 );
not ( n24734 , n21770 );
not ( n24735 , n24734 );
not ( n24736 , n24735 );
not ( n24737 , n18462 );
or ( n24738 , n24736 , n24737 );
or ( n24739 , n18462 , n24735 );
nand ( n24740 , n24738 , n24739 );
and ( n24741 , n24740 , n18465 );
not ( n24742 , n24740 );
and ( n24743 , n24742 , n23768 );
nor ( n24744 , n24741 , n24743 );
not ( n24745 , n24744 );
buf ( n24746 , n7177 );
not ( n24747 , n24746 );
not ( n24748 , n18863 );
or ( n24749 , n24747 , n24748 );
not ( n24750 , n19450 );
or ( n24751 , n24750 , n24746 );
nand ( n24752 , n24749 , n24751 );
xor ( n24753 , n18806 , n18810 );
not ( n24754 , n18820 );
xnor ( n24755 , n24753 , n24754 );
and ( n24756 , n24752 , n24755 );
not ( n24757 , n24752 );
and ( n24758 , n24757 , n18823 );
nor ( n24759 , n24756 , n24758 );
not ( n24760 , n24759 );
nand ( n24761 , n24745 , n24760 );
not ( n24762 , n13656 );
not ( n24763 , n19471 );
or ( n24764 , n24762 , n24763 );
or ( n24765 , n19471 , n13656 );
nand ( n24766 , n24764 , n24765 );
not ( n24767 , n21883 );
not ( n24768 , n24767 );
and ( n24769 , n24766 , n24768 );
not ( n24770 , n24766 );
and ( n24771 , n24770 , n24767 );
nor ( n24772 , n24769 , n24771 );
and ( n24773 , n24761 , n24772 );
not ( n24774 , n24761 );
not ( n24775 , n24772 );
and ( n24776 , n24774 , n24775 );
nor ( n24777 , n24773 , n24776 );
not ( n24778 , n24777 );
not ( n24779 , n18111 );
buf ( n24780 , n6412 );
nand ( n24781 , n6633 , n24780 );
buf ( n24782 , n6413 );
buf ( n24783 , n24782 );
and ( n24784 , n24781 , n24783 );
not ( n24785 , n24781 );
not ( n24786 , n24782 );
and ( n24787 , n24785 , n24786 );
nor ( n24788 , n24784 , n24787 );
buf ( n24789 , n24788 );
not ( n24790 , n24789 );
not ( n24791 , n18154 );
not ( n24792 , n24791 );
or ( n24793 , n24790 , n24792 );
or ( n24794 , n24791 , n24789 );
nand ( n24795 , n24793 , n24794 );
and ( n24796 , n24779 , n24795 );
not ( n24797 , n24779 );
not ( n24798 , n24795 );
and ( n24799 , n24797 , n24798 );
nor ( n24800 , n24796 , n24799 );
not ( n24801 , n8812 );
not ( n24802 , n8836 );
or ( n24803 , n24801 , n24802 );
nand ( n24804 , n24803 , n8840 );
xor ( n24805 , n9439 , n24804 );
xnor ( n24806 , n24805 , n18889 );
nand ( n24807 , n24800 , n24806 );
not ( n24808 , n24807 );
not ( n24809 , n19366 );
not ( n24810 , n24018 );
not ( n24811 , n8135 );
or ( n24812 , n24810 , n24811 );
or ( n24813 , n8135 , n24018 );
nand ( n24814 , n24812 , n24813 );
not ( n24815 , n24814 );
or ( n24816 , n24809 , n24815 );
or ( n24817 , n24814 , n19370 );
nand ( n24818 , n24816 , n24817 );
not ( n24819 , n24818 );
and ( n24820 , n24808 , n24819 );
and ( n24821 , n24807 , n24818 );
nor ( n24822 , n24820 , n24821 );
not ( n24823 , n24822 );
not ( n24824 , n12072 );
not ( n24825 , n7223 );
or ( n24826 , n24824 , n24825 );
not ( n24827 , n12072 );
nand ( n24828 , n24827 , n13515 );
nand ( n24829 , n24826 , n24828 );
and ( n24830 , n24829 , n7189 );
not ( n24831 , n24829 );
not ( n24832 , n7189 );
and ( n24833 , n24831 , n24832 );
nor ( n24834 , n24830 , n24833 );
buf ( n24835 , n19671 );
not ( n24836 , n24835 );
not ( n24837 , n9940 );
or ( n24838 , n24836 , n24837 );
or ( n24839 , n9940 , n24835 );
nand ( n24840 , n24838 , n24839 );
xor ( n24841 , n24840 , n20337 );
nand ( n24842 , n24834 , n24841 );
not ( n24843 , n22938 );
not ( n24844 , n6861 );
not ( n24845 , n14447 );
or ( n24846 , n24844 , n24845 );
nand ( n24847 , n14446 , n6857 );
nand ( n24848 , n24846 , n24847 );
not ( n24849 , n24848 );
and ( n24850 , n24843 , n24849 );
and ( n24851 , n22938 , n24848 );
nor ( n24852 , n24850 , n24851 );
and ( n24853 , n24842 , n24852 );
not ( n24854 , n24842 );
not ( n24855 , n24852 );
and ( n24856 , n24854 , n24855 );
nor ( n24857 , n24853 , n24856 );
not ( n24858 , n24857 );
or ( n24859 , n24823 , n24858 );
or ( n24860 , n24857 , n24822 );
nand ( n24861 , n24859 , n24860 );
not ( n24862 , n13504 );
buf ( n24863 , n6414 );
not ( n24864 , n24863 );
not ( n24865 , n24864 );
or ( n24866 , n24862 , n24865 );
not ( n24867 , n13503 );
buf ( n24868 , n24863 );
nand ( n24869 , n24867 , n24868 );
nand ( n24870 , n24866 , n24869 );
buf ( n24871 , n6415 );
not ( n24872 , n24871 );
and ( n24873 , n24870 , n24872 );
not ( n24874 , n24870 );
buf ( n24875 , n24871 );
and ( n24876 , n24874 , n24875 );
nor ( n24877 , n24873 , n24876 );
buf ( n24878 , n6416 );
nand ( n24879 , n7247 , n24878 );
buf ( n24880 , n6417 );
buf ( n24881 , n24880 );
and ( n24882 , n24879 , n24881 );
not ( n24883 , n24879 );
not ( n24884 , n24880 );
and ( n24885 , n24883 , n24884 );
nor ( n24886 , n24882 , n24885 );
xor ( n24887 , n24877 , n24886 );
xnor ( n24888 , n24887 , n23142 );
not ( n24889 , n24888 );
buf ( n24890 , n24889 );
xor ( n24891 , n18236 , n24890 );
buf ( n24892 , n6418 );
buf ( n24893 , n24892 );
not ( n24894 , n24893 );
buf ( n24895 , n6419 );
not ( n24896 , n24895 );
not ( n24897 , n24896 );
or ( n24898 , n24894 , n24897 );
not ( n24899 , n24892 );
buf ( n24900 , n24895 );
nand ( n24901 , n24899 , n24900 );
nand ( n24902 , n24898 , n24901 );
not ( n24903 , n24902 );
buf ( n24904 , n6420 );
buf ( n24905 , n6421 );
nand ( n24906 , n6770 , n24905 );
buf ( n24907 , n6422 );
buf ( n24908 , n24907 );
and ( n24909 , n24906 , n24908 );
not ( n24910 , n24906 );
not ( n24911 , n24907 );
and ( n24912 , n24910 , n24911 );
nor ( n24913 , n24909 , n24912 );
xor ( n24914 , n24904 , n24913 );
buf ( n24915 , n6423 );
nand ( n24916 , n6515 , n24915 );
buf ( n24917 , n6424 );
not ( n24918 , n24917 );
and ( n24919 , n24916 , n24918 );
not ( n24920 , n24916 );
buf ( n24921 , n24917 );
and ( n24922 , n24920 , n24921 );
nor ( n24923 , n24919 , n24922 );
xnor ( n24924 , n24914 , n24923 );
xor ( n24925 , n24903 , n24924 );
xnor ( n24926 , n24891 , n24925 );
not ( n24927 , n7104 );
not ( n24928 , n19526 );
or ( n24929 , n24927 , n24928 );
or ( n24930 , n19527 , n7104 );
nand ( n24931 , n24929 , n24930 );
not ( n24932 , n24931 );
not ( n24933 , n19480 );
or ( n24934 , n24932 , n24933 );
or ( n24935 , n19480 , n24931 );
nand ( n24936 , n24934 , n24935 );
not ( n24937 , n24936 );
nand ( n24938 , n24926 , n24937 );
not ( n24939 , n24938 );
not ( n24940 , n14761 );
not ( n24941 , n13711 );
or ( n24942 , n24940 , n24941 );
not ( n24943 , n14761 );
nand ( n24944 , n24943 , n7450 );
nand ( n24945 , n24942 , n24944 );
xor ( n24946 , n24945 , n13718 );
not ( n24947 , n24946 );
not ( n24948 , n24947 );
and ( n24949 , n24939 , n24948 );
and ( n24950 , n24938 , n24947 );
nor ( n24951 , n24949 , n24950 );
and ( n24952 , n24861 , n24951 );
not ( n24953 , n24861 );
not ( n24954 , n24951 );
and ( n24955 , n24953 , n24954 );
nor ( n24956 , n24952 , n24955 );
nand ( n24957 , n24772 , n24759 );
not ( n24958 , n24957 );
not ( n24959 , n10099 );
xor ( n24960 , n15449 , n15458 );
xor ( n24961 , n24960 , n15468 );
not ( n24962 , n24961 );
or ( n24963 , n24959 , n24962 );
or ( n24964 , n15469 , n10099 );
nand ( n24965 , n24963 , n24964 );
and ( n24966 , n24965 , n22821 );
not ( n24967 , n24965 );
and ( n24968 , n24967 , n22817 );
nor ( n24969 , n24966 , n24968 );
not ( n24970 , n24969 );
and ( n24971 , n24958 , n24970 );
and ( n24972 , n24957 , n24969 );
nor ( n24973 , n24971 , n24972 );
not ( n24974 , n24973 );
not ( n24975 , n21359 );
and ( n24976 , n23496 , n24975 );
not ( n24977 , n23496 );
and ( n24978 , n24977 , n21361 );
or ( n24979 , n24976 , n24978 );
and ( n24980 , n24979 , n17098 );
not ( n24981 , n24979 );
and ( n24982 , n24981 , n21319 );
nor ( n24983 , n24980 , n24982 );
not ( n24984 , n11748 );
and ( n24985 , n11752 , n24984 );
not ( n24986 , n11752 );
and ( n24987 , n24986 , n11749 );
nor ( n24988 , n24985 , n24987 );
not ( n24989 , n24988 );
not ( n24990 , n20208 );
or ( n24991 , n24989 , n24990 );
not ( n24992 , n20208 );
not ( n24993 , n24988 );
nand ( n24994 , n24992 , n24993 );
nand ( n24995 , n24991 , n24994 );
and ( n24996 , n24995 , n18003 );
not ( n24997 , n24995 );
and ( n24998 , n24997 , n18004 );
nor ( n24999 , n24996 , n24998 );
not ( n25000 , n24999 );
nand ( n25001 , n24983 , n25000 );
not ( n25002 , n7765 );
not ( n25003 , n23419 );
or ( n25004 , n25002 , n25003 );
or ( n25005 , n17546 , n7765 );
nand ( n25006 , n25004 , n25005 );
and ( n25007 , n25006 , n24286 );
not ( n25008 , n25006 );
and ( n25009 , n25008 , n17590 );
nor ( n25010 , n25007 , n25009 );
not ( n25011 , n25010 );
and ( n25012 , n25001 , n25011 );
not ( n25013 , n25001 );
and ( n25014 , n25013 , n25010 );
nor ( n25015 , n25012 , n25014 );
not ( n25016 , n25015 );
or ( n25017 , n24974 , n25016 );
or ( n25018 , n25015 , n24973 );
nand ( n25019 , n25017 , n25018 );
and ( n25020 , n24956 , n25019 );
not ( n25021 , n24956 );
not ( n25022 , n25019 );
and ( n25023 , n25021 , n25022 );
nor ( n25024 , n25020 , n25023 );
not ( n25025 , n25024 );
or ( n25026 , n24778 , n25025 );
not ( n25027 , n24777 );
not ( n25028 , n25024 );
nand ( n25029 , n25027 , n25028 );
nand ( n25030 , n25026 , n25029 );
not ( n25031 , n6698 );
not ( n25032 , n14051 );
or ( n25033 , n25031 , n25032 );
not ( n25034 , n6698 );
nand ( n25035 , n25034 , n14048 );
nand ( n25036 , n25033 , n25035 );
and ( n25037 , n25036 , n14095 );
not ( n25038 , n25036 );
not ( n25039 , n14092 );
buf ( n25040 , n25039 );
not ( n25041 , n25040 );
and ( n25042 , n25038 , n25041 );
nor ( n25043 , n25037 , n25042 );
not ( n25044 , n25043 );
buf ( n25045 , n24043 );
not ( n25046 , n25045 );
not ( n25047 , n8139 );
or ( n25048 , n25046 , n25047 );
or ( n25049 , n8139 , n25045 );
nand ( n25050 , n25048 , n25049 );
and ( n25051 , n25050 , n19366 );
not ( n25052 , n25050 );
and ( n25053 , n25052 , n19371 );
nor ( n25054 , n25051 , n25053 );
nand ( n25055 , n25044 , n25054 );
not ( n25056 , n25055 );
buf ( n25057 , n18851 );
xor ( n25058 , n25057 , n7128 );
xnor ( n25059 , n25058 , n18612 );
not ( n25060 , n25059 );
or ( n25061 , n25056 , n25060 );
or ( n25062 , n25059 , n25055 );
nand ( n25063 , n25061 , n25062 );
not ( n25064 , n25063 );
not ( n25065 , n25064 );
not ( n25066 , n24975 );
buf ( n25067 , n23507 );
not ( n25068 , n25067 );
and ( n25069 , n25066 , n25068 );
and ( n25070 , n21360 , n25067 );
nor ( n25071 , n25069 , n25070 );
not ( n25072 , n25071 );
not ( n25073 , n17101 );
or ( n25074 , n25072 , n25073 );
or ( n25075 , n17101 , n25071 );
nand ( n25076 , n25074 , n25075 );
not ( n25077 , n25076 );
not ( n25078 , n14798 );
not ( n25079 , n25078 );
not ( n25080 , n25079 );
not ( n25081 , n13268 );
not ( n25082 , n24001 );
or ( n25083 , n25081 , n25082 );
buf ( n25084 , n24001 );
or ( n25085 , n25084 , n13268 );
nand ( n25086 , n25083 , n25085 );
not ( n25087 , n25086 );
or ( n25088 , n25080 , n25087 );
or ( n25089 , n25086 , n20415 );
nand ( n25090 , n25088 , n25089 );
nand ( n25091 , n25077 , n25090 );
not ( n25092 , n13490 );
not ( n25093 , n22549 );
or ( n25094 , n25092 , n25093 );
or ( n25095 , n22549 , n13490 );
nand ( n25096 , n25094 , n25095 );
not ( n25097 , n19447 );
and ( n25098 , n25096 , n25097 );
not ( n25099 , n25096 );
not ( n25100 , n19443 );
and ( n25101 , n25099 , n25100 );
nor ( n25102 , n25098 , n25101 );
not ( n25103 , n25102 );
and ( n25104 , n25091 , n25103 );
not ( n25105 , n25091 );
and ( n25106 , n25105 , n25102 );
nor ( n25107 , n25104 , n25106 );
not ( n25108 , n25107 );
not ( n25109 , n25108 );
or ( n25110 , n25065 , n25109 );
nand ( n25111 , n25063 , n25107 );
nand ( n25112 , n25110 , n25111 );
not ( n25113 , n12857 );
not ( n25114 , n6948 );
or ( n25115 , n25113 , n25114 );
not ( n25116 , n12857 );
nand ( n25117 , n25116 , n6892 );
nand ( n25118 , n25115 , n25117 );
not ( n25119 , n22921 );
buf ( n25120 , n6425 );
not ( n25121 , n25120 );
not ( n25122 , n25121 );
or ( n25123 , n25119 , n25122 );
not ( n25124 , n22920 );
buf ( n25125 , n25120 );
nand ( n25126 , n25124 , n25125 );
nand ( n25127 , n25123 , n25126 );
buf ( n25128 , n6426 );
buf ( n25129 , n25128 );
and ( n25130 , n25127 , n25129 );
not ( n25131 , n25127 );
not ( n25132 , n25128 );
and ( n25133 , n25131 , n25132 );
nor ( n25134 , n25130 , n25133 );
buf ( n25135 , n6427 );
nand ( n25136 , n7868 , n25135 );
buf ( n25137 , n6428 );
not ( n25138 , n25137 );
and ( n25139 , n25136 , n25138 );
not ( n25140 , n25136 );
buf ( n25141 , n25137 );
and ( n25142 , n25140 , n25141 );
nor ( n25143 , n25139 , n25142 );
xor ( n25144 , n25134 , n25143 );
buf ( n25145 , n6429 );
nand ( n25146 , n7259 , n25145 );
buf ( n25147 , n6430 );
not ( n25148 , n25147 );
and ( n25149 , n25146 , n25148 );
not ( n25150 , n25146 );
buf ( n25151 , n25147 );
and ( n25152 , n25150 , n25151 );
nor ( n25153 , n25149 , n25152 );
xnor ( n25154 , n25144 , n25153 );
buf ( n25155 , n25154 );
not ( n25156 , n25155 );
and ( n25157 , n25118 , n25156 );
not ( n25158 , n25118 );
buf ( n25159 , n25154 );
and ( n25160 , n25158 , n25159 );
nor ( n25161 , n25157 , n25160 );
not ( n25162 , n25161 );
not ( n25163 , n6801 );
not ( n25164 , n14393 );
or ( n25165 , n25163 , n25164 );
not ( n25166 , n6801 );
xor ( n25167 , n14376 , n14385 );
xor ( n25168 , n25167 , n14392 );
nand ( n25169 , n25166 , n25168 );
nand ( n25170 , n25165 , n25169 );
xor ( n25171 , n25170 , n12594 );
not ( n25172 , n25171 );
nand ( n25173 , n25162 , n25172 );
not ( n25174 , n25173 );
buf ( n25175 , n9501 );
not ( n25176 , n25175 );
not ( n25177 , n25176 );
not ( n25178 , n23822 );
or ( n25179 , n25177 , n25178 );
nand ( n25180 , n23826 , n25175 );
nand ( n25181 , n25179 , n25180 );
and ( n25182 , n25181 , n18579 );
not ( n25183 , n25181 );
not ( n25184 , n18579 );
and ( n25185 , n25183 , n25184 );
nor ( n25186 , n25182 , n25185 );
not ( n25187 , n25186 );
not ( n25188 , n25187 );
not ( n25189 , n25188 );
and ( n25190 , n25174 , n25189 );
and ( n25191 , n25173 , n25188 );
nor ( n25192 , n25190 , n25191 );
and ( n25193 , n25112 , n25192 );
not ( n25194 , n25112 );
not ( n25195 , n25192 );
and ( n25196 , n25194 , n25195 );
nor ( n25197 , n25193 , n25196 );
not ( n25198 , n11775 );
not ( n25199 , n23682 );
not ( n25200 , n7314 );
or ( n25201 , n25199 , n25200 );
buf ( n25202 , n11757 );
nand ( n25203 , n25202 , n23678 );
nand ( n25204 , n25201 , n25203 );
not ( n25205 , n25204 );
not ( n25206 , n25205 );
or ( n25207 , n25198 , n25206 );
nand ( n25208 , n16151 , n25204 );
nand ( n25209 , n25207 , n25208 );
not ( n25210 , n15475 );
not ( n25211 , n10077 );
not ( n25212 , n19541 );
or ( n25213 , n25211 , n25212 );
or ( n25214 , n19541 , n10077 );
nand ( n25215 , n25213 , n25214 );
not ( n25216 , n25215 );
or ( n25217 , n25210 , n25216 );
or ( n25218 , n25215 , n15470 );
nand ( n25219 , n25217 , n25218 );
not ( n25220 , n25219 );
nand ( n25221 , n25209 , n25220 );
not ( n25222 , n7126 );
not ( n25223 , n25222 );
not ( n25224 , n19526 );
or ( n25225 , n25223 , n25224 );
not ( n25226 , n19501 );
xor ( n25227 , n19521 , n25226 );
xnor ( n25228 , n25227 , n19491 );
nand ( n25229 , n25228 , n7126 );
nand ( n25230 , n25225 , n25229 );
not ( n25231 , n25230 );
not ( n25232 , n19480 );
or ( n25233 , n25231 , n25232 );
or ( n25234 , n19480 , n25230 );
nand ( n25235 , n25233 , n25234 );
and ( n25236 , n25221 , n25235 );
not ( n25237 , n25221 );
not ( n25238 , n25235 );
and ( n25239 , n25237 , n25238 );
nor ( n25240 , n25236 , n25239 );
not ( n25241 , n25240 );
buf ( n25242 , n11043 );
not ( n25243 , n25242 );
not ( n25244 , n18668 );
or ( n25245 , n25243 , n25244 );
or ( n25246 , n18668 , n25242 );
nand ( n25247 , n25245 , n25246 );
buf ( n25248 , n7756 );
and ( n25249 , n25247 , n25248 );
not ( n25250 , n25247 );
not ( n25251 , n7752 );
not ( n25252 , n25251 );
not ( n25253 , n7742 );
not ( n25254 , n25253 );
or ( n25255 , n25252 , n25254 );
nand ( n25256 , n7742 , n7752 );
nand ( n25257 , n25255 , n25256 );
buf ( n25258 , n25257 );
and ( n25259 , n25250 , n25258 );
nor ( n25260 , n25249 , n25259 );
not ( n25261 , n14121 );
not ( n25262 , n15518 );
or ( n25263 , n25261 , n25262 );
not ( n25264 , n14121 );
nand ( n25265 , n25264 , n15521 );
nand ( n25266 , n25263 , n25265 );
and ( n25267 , n25266 , n15576 );
not ( n25268 , n25266 );
and ( n25269 , n25268 , n15563 );
nor ( n25270 , n25267 , n25269 );
not ( n25271 , n25270 );
nand ( n25272 , n25260 , n25271 );
not ( n25273 , n25272 );
buf ( n25274 , n6431 );
buf ( n25275 , n25274 );
not ( n25276 , n25275 );
buf ( n25277 , n6432 );
not ( n25278 , n25277 );
not ( n25279 , n25278 );
or ( n25280 , n25276 , n25279 );
not ( n25281 , n25274 );
buf ( n25282 , n25277 );
nand ( n25283 , n25281 , n25282 );
nand ( n25284 , n25280 , n25283 );
buf ( n25285 , n6433 );
buf ( n25286 , n25285 );
and ( n25287 , n25284 , n25286 );
not ( n25288 , n25284 );
not ( n25289 , n25285 );
and ( n25290 , n25288 , n25289 );
nor ( n25291 , n25287 , n25290 );
buf ( n25292 , n6434 );
nand ( n25293 , n7014 , n25292 );
buf ( n25294 , n6435 );
not ( n25295 , n25294 );
and ( n25296 , n25293 , n25295 );
not ( n25297 , n25293 );
buf ( n25298 , n25294 );
and ( n25299 , n25297 , n25298 );
nor ( n25300 , n25296 , n25299 );
xor ( n25301 , n25291 , n25300 );
buf ( n25302 , n6436 );
nand ( n25303 , n6558 , n25302 );
buf ( n25304 , n6437 );
not ( n25305 , n25304 );
and ( n25306 , n25303 , n25305 );
not ( n25307 , n25303 );
buf ( n25308 , n25304 );
and ( n25309 , n25307 , n25308 );
nor ( n25310 , n25306 , n25309 );
xnor ( n25311 , n25301 , n25310 );
buf ( n25312 , n25311 );
not ( n25313 , n25312 );
not ( n25314 , n23317 );
not ( n25315 , n23320 );
or ( n25316 , n25314 , n25315 );
or ( n25317 , n23320 , n23317 );
nand ( n25318 , n25316 , n25317 );
not ( n25319 , n25318 );
not ( n25320 , n18115 );
buf ( n25321 , n6438 );
not ( n25322 , n25321 );
not ( n25323 , n25322 );
or ( n25324 , n25320 , n25323 );
not ( n25325 , n18114 );
buf ( n25326 , n25321 );
nand ( n25327 , n25325 , n25326 );
nand ( n25328 , n25324 , n25327 );
buf ( n25329 , n6439 );
not ( n25330 , n25329 );
and ( n25331 , n25328 , n25330 );
not ( n25332 , n25328 );
buf ( n25333 , n25329 );
and ( n25334 , n25332 , n25333 );
nor ( n25335 , n25331 , n25334 );
xor ( n25336 , n25335 , n24788 );
buf ( n25337 , n6440 );
nand ( n25338 , n8223 , n25337 );
buf ( n25339 , n6441 );
not ( n25340 , n25339 );
and ( n25341 , n25338 , n25340 );
not ( n25342 , n25338 );
buf ( n25343 , n25339 );
and ( n25344 , n25342 , n25343 );
nor ( n25345 , n25341 , n25344 );
xnor ( n25346 , n25336 , n25345 );
not ( n25347 , n25346 );
or ( n25348 , n25319 , n25347 );
or ( n25349 , n25318 , n25346 );
nand ( n25350 , n25348 , n25349 );
not ( n25351 , n25350 );
or ( n25352 , n25313 , n25351 );
or ( n25353 , n25350 , n25312 );
nand ( n25354 , n25352 , n25353 );
not ( n25355 , n25354 );
and ( n25356 , n25273 , n25355 );
and ( n25357 , n25272 , n25354 );
nor ( n25358 , n25356 , n25357 );
not ( n25359 , n25358 );
not ( n25360 , n25359 );
or ( n25361 , n25241 , n25360 );
not ( n25362 , n25240 );
nand ( n25363 , n25362 , n25358 );
nand ( n25364 , n25361 , n25363 );
not ( n25365 , n25364 );
and ( n25366 , n25197 , n25365 );
not ( n25367 , n25197 );
and ( n25368 , n25367 , n25364 );
nor ( n25369 , n25366 , n25368 );
buf ( n25370 , n25369 );
and ( n25371 , n25030 , n25370 );
not ( n25372 , n25030 );
and ( n25373 , n25197 , n25364 );
not ( n25374 , n25197 );
and ( n25375 , n25374 , n25365 );
nor ( n25376 , n25373 , n25375 );
buf ( n25377 , n25376 );
and ( n25378 , n25372 , n25377 );
nor ( n25379 , n25371 , n25378 );
nand ( n25380 , n24733 , n25379 );
not ( n25381 , n7143 );
not ( n25382 , n7671 );
not ( n25383 , n7585 );
nand ( n25384 , n25382 , n25383 );
not ( n25385 , n25384 );
not ( n25386 , n22506 );
and ( n25387 , n25385 , n25386 );
and ( n25388 , n25384 , n22506 );
nor ( n25389 , n25387 , n25388 );
not ( n25390 , n25389 );
not ( n25391 , n25390 );
nand ( n25392 , n7757 , n7934 );
not ( n25393 , n25392 );
not ( n25394 , n22424 );
and ( n25395 , n25393 , n25394 );
and ( n25396 , n25392 , n22424 );
nor ( n25397 , n25395 , n25396 );
not ( n25398 , n25397 );
or ( n25399 , n25391 , n25398 );
not ( n25400 , n25397 );
nand ( n25401 , n25400 , n25389 );
nand ( n25402 , n25399 , n25401 );
not ( n25403 , n25402 );
not ( n25404 , n25403 );
not ( n25405 , n22399 );
nand ( n25406 , n7032 , n6851 );
not ( n25407 , n25406 );
or ( n25408 , n25405 , n25407 );
or ( n25409 , n25406 , n22399 );
nand ( n25410 , n25408 , n25409 );
not ( n25411 , n25410 );
nand ( n25412 , n7138 , n6743 );
not ( n25413 , n25412 );
buf ( n25414 , n22290 );
not ( n25415 , n25414 );
not ( n25416 , n25415 );
and ( n25417 , n25413 , n25416 );
and ( n25418 , n25412 , n25415 );
nor ( n25419 , n25417 , n25418 );
not ( n25420 , n25419 );
or ( n25421 , n25411 , n25420 );
or ( n25422 , n25410 , n25419 );
nand ( n25423 , n25421 , n25422 );
not ( n25424 , n7226 );
nand ( n25425 , n25424 , n7417 );
xnor ( n25426 , n25425 , n22321 );
not ( n25427 , n25426 );
and ( n25428 , n25423 , n25427 );
not ( n25429 , n25423 );
and ( n25430 , n25429 , n25426 );
nor ( n25431 , n25428 , n25430 );
not ( n25432 , n25431 );
not ( n25433 , n25432 );
or ( n25434 , n25404 , n25433 );
not ( n25435 , n25432 );
not ( n25436 , n25403 );
nand ( n25437 , n25435 , n25436 );
nand ( n25438 , n25434 , n25437 );
not ( n25439 , n25438 );
or ( n25440 , n25381 , n25439 );
not ( n25441 , n7143 );
and ( n25442 , n25431 , n25402 );
not ( n25443 , n25431 );
and ( n25444 , n25443 , n25403 );
nor ( n25445 , n25442 , n25444 );
nand ( n25446 , n25441 , n25445 );
nand ( n25447 , n25440 , n25446 );
or ( n25448 , n8050 , n8239 );
not ( n25449 , n12555 );
buf ( n25450 , n6442 );
buf ( n25451 , n25450 );
not ( n25452 , n25451 );
buf ( n25453 , n6443 );
not ( n25454 , n25453 );
not ( n25455 , n25454 );
or ( n25456 , n25452 , n25455 );
not ( n25457 , n25450 );
buf ( n25458 , n25453 );
nand ( n25459 , n25457 , n25458 );
nand ( n25460 , n25456 , n25459 );
buf ( n25461 , n6444 );
buf ( n25462 , n25461 );
and ( n25463 , n25460 , n25462 );
not ( n25464 , n25460 );
not ( n25465 , n25461 );
and ( n25466 , n25464 , n25465 );
nor ( n25467 , n25463 , n25466 );
buf ( n25468 , n6445 );
nand ( n25469 , n6502 , n25468 );
buf ( n25470 , n6446 );
not ( n25471 , n25470 );
and ( n25472 , n25469 , n25471 );
not ( n25473 , n25469 );
buf ( n25474 , n25470 );
and ( n25475 , n25473 , n25474 );
nor ( n25476 , n25472 , n25475 );
xor ( n25477 , n25467 , n25476 );
buf ( n25478 , n6447 );
nand ( n25479 , n8455 , n25478 );
buf ( n25480 , n6448 );
not ( n25481 , n25480 );
and ( n25482 , n25479 , n25481 );
not ( n25483 , n25479 );
buf ( n25484 , n25480 );
and ( n25485 , n25483 , n25484 );
nor ( n25486 , n25482 , n25485 );
xnor ( n25487 , n25477 , n25486 );
not ( n25488 , n25487 );
or ( n25489 , n25449 , n25488 );
or ( n25490 , n25487 , n12555 );
nand ( n25491 , n25489 , n25490 );
xor ( n25492 , n21761 , n18454 );
xnor ( n25493 , n25492 , n24734 );
buf ( n25494 , n25493 );
and ( n25495 , n25491 , n25494 );
not ( n25496 , n25491 );
and ( n25497 , n25496 , n21772 );
nor ( n25498 , n25495 , n25497 );
not ( n25499 , n25498 );
and ( n25500 , n25448 , n25499 );
not ( n25501 , n25448 );
and ( n25502 , n25501 , n25498 );
nor ( n25503 , n25500 , n25502 );
not ( n25504 , n25503 );
not ( n25505 , n25504 );
nand ( n25506 , n8319 , n8445 );
not ( n25507 , n17455 );
not ( n25508 , n14056 );
not ( n25509 , n12993 );
or ( n25510 , n25508 , n25509 );
not ( n25511 , n14056 );
nand ( n25512 , n25511 , n13006 );
nand ( n25513 , n25510 , n25512 );
not ( n25514 , n25513 );
and ( n25515 , n25507 , n25514 );
and ( n25516 , n17455 , n25513 );
nor ( n25517 , n25515 , n25516 );
and ( n25518 , n25506 , n25517 );
not ( n25519 , n25506 );
not ( n25520 , n25517 );
and ( n25521 , n25519 , n25520 );
nor ( n25522 , n25518 , n25521 );
not ( n25523 , n25522 );
not ( n25524 , n25523 );
or ( n25525 , n25505 , n25524 );
nand ( n25526 , n25522 , n25503 );
nand ( n25527 , n25525 , n25526 );
nand ( n25528 , n8553 , n8664 );
xor ( n25529 , n18826 , n7129 );
xor ( n25530 , n25529 , n15361 );
not ( n25531 , n25530 );
and ( n25532 , n25528 , n25531 );
not ( n25533 , n25528 );
and ( n25534 , n25533 , n25530 );
nor ( n25535 , n25532 , n25534 );
and ( n25536 , n25527 , n25535 );
not ( n25537 , n25527 );
not ( n25538 , n25535 );
and ( n25539 , n25537 , n25538 );
nor ( n25540 , n25536 , n25539 );
not ( n25541 , n25540 );
not ( n25542 , n25541 );
and ( n25543 , n14931 , n17085 );
not ( n25544 , n14931 );
not ( n25545 , n17085 );
and ( n25546 , n25544 , n25545 );
or ( n25547 , n25543 , n25546 );
not ( n25548 , n7927 );
not ( n25549 , n25548 );
and ( n25550 , n25547 , n25549 );
not ( n25551 , n25547 );
not ( n25552 , n7923 );
and ( n25553 , n25551 , n25552 );
nor ( n25554 , n25550 , n25553 );
not ( n25555 , n25554 );
not ( n25556 , n25555 );
not ( n25557 , n9003 );
nand ( n25558 , n9069 , n25557 );
not ( n25559 , n25558 );
or ( n25560 , n25556 , n25559 );
not ( n25561 , n9003 );
nand ( n25562 , n25561 , n9069 );
or ( n25563 , n25562 , n25555 );
nand ( n25564 , n25560 , n25563 );
not ( n25565 , n25564 );
not ( n25566 , n8763 );
nand ( n25567 , n25566 , n8919 );
not ( n25568 , n25567 );
xor ( n25569 , n20644 , n20410 );
buf ( n25570 , n23126 );
xor ( n25571 , n25569 , n25570 );
not ( n25572 , n25571 );
not ( n25573 , n25572 );
and ( n25574 , n25568 , n25573 );
not ( n25575 , n8918 );
nand ( n25576 , n25575 , n25566 );
and ( n25577 , n25576 , n25572 );
nor ( n25578 , n25574 , n25577 );
not ( n25579 , n25578 );
or ( n25580 , n25565 , n25579 );
or ( n25581 , n25578 , n25564 );
nand ( n25582 , n25580 , n25581 );
not ( n25583 , n25582 );
not ( n25584 , n25583 );
or ( n25585 , n25542 , n25584 );
nand ( n25586 , n25540 , n25582 );
nand ( n25587 , n25585 , n25586 );
buf ( n25588 , n25587 );
not ( n25589 , n25588 );
and ( n25590 , n25447 , n25589 );
not ( n25591 , n25447 );
and ( n25592 , n25591 , n25588 );
nor ( n25593 , n25590 , n25592 );
not ( n25594 , n17150 );
nand ( n25595 , n25594 , n11110 );
not ( n25596 , n25595 );
not ( n25597 , n17241 );
not ( n25598 , n25597 );
and ( n25599 , n25596 , n25598 );
nand ( n25600 , n25594 , n11110 );
and ( n25601 , n25600 , n25597 );
nor ( n25602 , n25599 , n25601 );
not ( n25603 , n25602 );
not ( n25604 , n17377 );
or ( n25605 , n25603 , n25604 );
not ( n25606 , n25602 );
not ( n25607 , n17372 );
not ( n25608 , n17285 );
and ( n25609 , n25607 , n25608 );
and ( n25610 , n17372 , n17285 );
nor ( n25611 , n25609 , n25610 );
nand ( n25612 , n25606 , n25611 );
nand ( n25613 , n25605 , n25612 );
buf ( n25614 , n17796 );
and ( n25615 , n25613 , n25614 );
not ( n25616 , n25613 );
not ( n25617 , n25614 );
and ( n25618 , n25616 , n25617 );
nor ( n25619 , n25615 , n25618 );
nand ( n25620 , n25593 , n25619 );
or ( n25621 , n25380 , n25620 );
not ( n25622 , n25619 );
not ( n25623 , n25379 );
or ( n25624 , n25622 , n25623 );
buf ( n25625 , n15325 );
nor ( n25626 , n25593 , n25625 );
nand ( n25627 , n25624 , n25626 );
buf ( n25628 , n13353 );
nand ( n25629 , n25628 , n7244 );
nand ( n25630 , n25621 , n25627 , n25629 );
buf ( n25631 , n25630 );
buf ( n25632 , n25631 );
not ( n25633 , n10362 );
not ( n25634 , n11121 );
or ( n25635 , n25633 , n25634 );
or ( n25636 , n11121 , n10362 );
nand ( n25637 , n25635 , n25636 );
and ( n25638 , n25637 , n11155 );
not ( n25639 , n25637 );
and ( n25640 , n25639 , n11156 );
nor ( n25641 , n25638 , n25640 );
not ( n25642 , n25641 );
not ( n25643 , n20080 );
nand ( n25644 , n25642 , n25643 );
and ( n25645 , n25644 , n19998 );
not ( n25646 , n25644 );
not ( n25647 , n19998 );
and ( n25648 , n25646 , n25647 );
nor ( n25649 , n25645 , n25648 );
not ( n25650 , n25649 );
not ( n25651 , n20536 );
or ( n25652 , n25650 , n25651 );
not ( n25653 , n25649 );
nand ( n25654 , n25653 , n20544 );
nand ( n25655 , n25652 , n25654 );
and ( n25656 , n25655 , n20966 );
not ( n25657 , n25655 );
and ( n25658 , n25657 , n20952 );
nor ( n25659 , n25656 , n25658 );
buf ( n25660 , n13345 );
not ( n25661 , n25660 );
nand ( n25662 , n25659 , n25661 );
not ( n25663 , n12180 );
not ( n25664 , n20631 );
or ( n25665 , n25663 , n25664 );
nand ( n25666 , n20628 , n12183 );
nand ( n25667 , n25665 , n25666 );
and ( n25668 , n25667 , n19101 );
not ( n25669 , n25667 );
and ( n25670 , n25669 , n9695 );
nor ( n25671 , n25668 , n25670 );
not ( n25672 , n25671 );
not ( n25673 , n14883 );
not ( n25674 , n17040 );
or ( n25675 , n25673 , n25674 );
nand ( n25676 , n17043 , n14917 );
nand ( n25677 , n25675 , n25676 );
not ( n25678 , n25677 );
not ( n25679 , n17086 );
and ( n25680 , n25678 , n25679 );
not ( n25681 , n17084 );
buf ( n25682 , n25681 );
not ( n25683 , n25682 );
not ( n25684 , n25683 );
and ( n25685 , n25677 , n25684 );
nor ( n25686 , n25680 , n25685 );
not ( n25687 , n25686 );
nand ( n25688 , n25672 , n25687 );
not ( n25689 , n25688 );
xor ( n25690 , n16029 , n14152 );
xnor ( n25691 , n25690 , n14175 );
not ( n25692 , n25691 );
not ( n25693 , n25692 );
or ( n25694 , n25689 , n25693 );
or ( n25695 , n25692 , n25688 );
nand ( n25696 , n25694 , n25695 );
not ( n25697 , n25696 );
not ( n25698 , n14749 );
not ( n25699 , n14727 );
and ( n25700 , n25698 , n25699 );
and ( n25701 , n14749 , n14727 );
nor ( n25702 , n25700 , n25701 );
not ( n25703 , n25702 );
not ( n25704 , n16665 );
not ( n25705 , n16677 );
xor ( n25706 , n25704 , n25705 );
xnor ( n25707 , n25706 , n16680 );
and ( n25708 , n9359 , n25707 );
not ( n25709 , n9359 );
and ( n25710 , n25709 , n16682 );
nor ( n25711 , n25708 , n25710 );
not ( n25712 , n25711 );
and ( n25713 , n25703 , n25712 );
and ( n25714 , n14755 , n25711 );
nor ( n25715 , n25713 , n25714 );
not ( n25716 , n25715 );
not ( n25717 , n25716 );
not ( n25718 , n8568 );
not ( n25719 , n10637 );
not ( n25720 , n13906 );
or ( n25721 , n25719 , n25720 );
nand ( n25722 , n13905 , n10633 );
nand ( n25723 , n25721 , n25722 );
not ( n25724 , n25723 );
and ( n25725 , n25718 , n25724 );
not ( n25726 , n7802 );
and ( n25727 , n25726 , n25723 );
nor ( n25728 , n25725 , n25727 );
not ( n25729 , n15889 );
not ( n25730 , n10036 );
or ( n25731 , n25729 , n25730 );
not ( n25732 , n15889 );
nand ( n25733 , n25732 , n8977 );
nand ( n25734 , n25731 , n25733 );
and ( n25735 , n25734 , n8986 );
not ( n25736 , n25734 );
and ( n25737 , n25736 , n7540 );
nor ( n25738 , n25735 , n25737 );
nand ( n25739 , n25728 , n25738 );
not ( n25740 , n25739 );
or ( n25741 , n25717 , n25740 );
or ( n25742 , n25739 , n25716 );
nand ( n25743 , n25741 , n25742 );
not ( n25744 , n25743 );
and ( n25745 , n14284 , n12341 );
not ( n25746 , n14284 );
and ( n25747 , n25746 , n13294 );
nor ( n25748 , n25745 , n25747 );
xnor ( n25749 , n12376 , n25748 );
not ( n25750 , n19304 );
not ( n25751 , n15291 );
or ( n25752 , n25750 , n25751 );
not ( n25753 , n19304 );
nand ( n25754 , n25753 , n23723 );
nand ( n25755 , n25752 , n25754 );
and ( n25756 , n25755 , n15298 );
not ( n25757 , n25755 );
and ( n25758 , n25757 , n14220 );
nor ( n25759 , n25756 , n25758 );
not ( n25760 , n25759 );
nand ( n25761 , n25749 , n25760 );
not ( n25762 , n25761 );
not ( n25763 , n15533 );
not ( n25764 , n9136 );
not ( n25765 , n25764 );
or ( n25766 , n25763 , n25765 );
not ( n25767 , n9136 );
or ( n25768 , n25767 , n15533 );
nand ( n25769 , n25766 , n25768 );
and ( n25770 , n25769 , n9184 );
not ( n25771 , n25769 );
not ( n25772 , n9181 );
not ( n25773 , n25772 );
and ( n25774 , n25771 , n25773 );
nor ( n25775 , n25770 , n25774 );
not ( n25776 , n25775 );
not ( n25777 , n25776 );
not ( n25778 , n25777 );
and ( n25779 , n25762 , n25778 );
and ( n25780 , n25761 , n25777 );
nor ( n25781 , n25779 , n25780 );
not ( n25782 , n25781 );
or ( n25783 , n25744 , n25782 );
or ( n25784 , n25781 , n25743 );
nand ( n25785 , n25783 , n25784 );
nand ( n25786 , n25691 , n25671 );
not ( n25787 , n10106 );
not ( n25788 , n24961 );
or ( n25789 , n25787 , n25788 );
not ( n25790 , n10106 );
not ( n25791 , n24961 );
nand ( n25792 , n25790 , n25791 );
nand ( n25793 , n25789 , n25792 );
and ( n25794 , n25793 , n22821 );
not ( n25795 , n25793 );
and ( n25796 , n25795 , n22817 );
nor ( n25797 , n25794 , n25796 );
not ( n25798 , n25797 );
and ( n25799 , n25786 , n25798 );
not ( n25800 , n25786 );
and ( n25801 , n25800 , n25797 );
nor ( n25802 , n25799 , n25801 );
not ( n25803 , n25802 );
and ( n25804 , n25785 , n25803 );
not ( n25805 , n25785 );
and ( n25806 , n25805 , n25802 );
nor ( n25807 , n25804 , n25806 );
not ( n25808 , n25807 );
not ( n25809 , n12263 );
buf ( n25810 , n20782 );
not ( n25811 , n25810 );
or ( n25812 , n25809 , n25811 );
or ( n25813 , n22586 , n12263 );
nand ( n25814 , n25812 , n25813 );
buf ( n25815 , n6977 );
and ( n25816 , n25814 , n25815 );
not ( n25817 , n25814 );
and ( n25818 , n25817 , n18730 );
nor ( n25819 , n25816 , n25818 );
not ( n25820 , n7589 );
not ( n25821 , n22658 );
or ( n25822 , n25820 , n25821 );
or ( n25823 , n22658 , n7589 );
nand ( n25824 , n25822 , n25823 );
not ( n25825 , n16453 );
not ( n25826 , n25825 );
not ( n25827 , n25826 );
and ( n25828 , n25824 , n25827 );
not ( n25829 , n25824 );
buf ( n25830 , n21864 );
and ( n25831 , n25829 , n25830 );
nor ( n25832 , n25828 , n25831 );
nand ( n25833 , n25819 , n25832 );
not ( n25834 , n25833 );
not ( n25835 , n9015 );
not ( n25836 , n10227 );
or ( n25837 , n25835 , n25836 );
buf ( n25838 , n12933 );
nand ( n25839 , n25838 , n9011 );
nand ( n25840 , n25837 , n25839 );
not ( n25841 , n12936 );
and ( n25842 , n25840 , n25841 );
not ( n25843 , n25840 );
and ( n25844 , n25843 , n12936 );
nor ( n25845 , n25842 , n25844 );
not ( n25846 , n25845 );
and ( n25847 , n25834 , n25846 );
and ( n25848 , n25833 , n25845 );
nor ( n25849 , n25847 , n25848 );
not ( n25850 , n25849 );
buf ( n25851 , n24381 );
xor ( n25852 , n18182 , n25851 );
not ( n25853 , n24681 );
xnor ( n25854 , n25852 , n25853 );
not ( n25855 , n25854 );
not ( n25856 , n7431 );
buf ( n25857 , n6449 );
buf ( n25858 , n25857 );
not ( n25859 , n25858 );
not ( n25860 , n10750 );
or ( n25861 , n25859 , n25860 );
not ( n25862 , n25857 );
nand ( n25863 , n25862 , n10705 );
nand ( n25864 , n25861 , n25863 );
buf ( n25865 , n6450 );
not ( n25866 , n25865 );
and ( n25867 , n25864 , n25866 );
not ( n25868 , n25864 );
buf ( n25869 , n25865 );
and ( n25870 , n25868 , n25869 );
nor ( n25871 , n25867 , n25870 );
xor ( n25872 , n25871 , n19988 );
buf ( n25873 , n6451 );
nand ( n25874 , n7344 , n25873 );
buf ( n25875 , n6452 );
buf ( n25876 , n25875 );
and ( n25877 , n25874 , n25876 );
not ( n25878 , n25874 );
not ( n25879 , n25875 );
and ( n25880 , n25878 , n25879 );
nor ( n25881 , n25877 , n25880 );
not ( n25882 , n25881 );
xnor ( n25883 , n25872 , n25882 );
buf ( n25884 , n25883 );
not ( n25885 , n25884 );
or ( n25886 , n25856 , n25885 );
not ( n25887 , n25883 );
not ( n25888 , n25887 );
or ( n25889 , n25888 , n7431 );
nand ( n25890 , n25886 , n25889 );
buf ( n25891 , n11614 );
and ( n25892 , n25890 , n25891 );
not ( n25893 , n25890 );
not ( n25894 , n25891 );
and ( n25895 , n25893 , n25894 );
nor ( n25896 , n25892 , n25895 );
nand ( n25897 , n25855 , n25896 );
not ( n25898 , n13822 );
not ( n25899 , n20198 );
or ( n25900 , n25898 , n25899 );
buf ( n25901 , n20202 );
nand ( n25902 , n25901 , n13818 );
nand ( n25903 , n25900 , n25902 );
not ( n25904 , n22414 );
and ( n25905 , n25903 , n25904 );
not ( n25906 , n25903 );
and ( n25907 , n25906 , n22414 );
nor ( n25908 , n25905 , n25907 );
and ( n25909 , n25897 , n25908 );
not ( n25910 , n25897 );
not ( n25911 , n25908 );
and ( n25912 , n25910 , n25911 );
nor ( n25913 , n25909 , n25912 );
not ( n25914 , n25913 );
or ( n25915 , n25850 , n25914 );
or ( n25916 , n25913 , n25849 );
nand ( n25917 , n25915 , n25916 );
not ( n25918 , n25917 );
and ( n25919 , n25808 , n25918 );
not ( n25920 , n25808 );
and ( n25921 , n25920 , n25917 );
nor ( n25922 , n25919 , n25921 );
not ( n25923 , n25922 );
or ( n25924 , n25697 , n25923 );
not ( n25925 , n25696 );
not ( n25926 , n25918 );
not ( n25927 , n25807 );
not ( n25928 , n25927 );
or ( n25929 , n25926 , n25928 );
nand ( n25930 , n25807 , n25917 );
nand ( n25931 , n25929 , n25930 );
nand ( n25932 , n25925 , n25931 );
nand ( n25933 , n25924 , n25932 );
buf ( n25934 , n6453 );
nand ( n25935 , n7563 , n25934 );
buf ( n25936 , n6454 );
buf ( n25937 , n25936 );
and ( n25938 , n25935 , n25937 );
not ( n25939 , n25935 );
not ( n25940 , n25936 );
and ( n25941 , n25939 , n25940 );
nor ( n25942 , n25938 , n25941 );
buf ( n25943 , n25942 );
xor ( n25944 , n25943 , n14624 );
xor ( n25945 , n25944 , n25888 );
buf ( n25946 , n12195 );
not ( n25947 , n25946 );
not ( n25948 , n20628 );
or ( n25949 , n25947 , n25948 );
or ( n25950 , n20628 , n25946 );
nand ( n25951 , n25949 , n25950 );
not ( n25952 , n25951 );
not ( n25953 , n9695 );
and ( n25954 , n25952 , n25953 );
buf ( n25955 , n19102 );
and ( n25956 , n25951 , n25955 );
nor ( n25957 , n25954 , n25956 );
nand ( n25958 , n25945 , n25957 );
not ( n25959 , n8697 );
not ( n25960 , n10849 );
or ( n25961 , n25959 , n25960 );
or ( n25962 , n10849 , n8697 );
nand ( n25963 , n25961 , n25962 );
buf ( n25964 , n16910 );
not ( n25965 , n25964 );
and ( n25966 , n25963 , n25965 );
not ( n25967 , n25963 );
and ( n25968 , n25967 , n25964 );
nor ( n25969 , n25966 , n25968 );
xnor ( n25970 , n25958 , n25969 );
not ( n25971 , n25970 );
buf ( n25972 , n14645 );
and ( n25973 , n14649 , n25972 );
not ( n25974 , n14649 );
and ( n25975 , n25974 , n14646 );
nor ( n25976 , n25973 , n25975 );
xor ( n25977 , n25976 , n11957 );
not ( n25978 , n25977 );
not ( n25979 , n22100 );
and ( n25980 , n25978 , n25979 );
not ( n25981 , n22100 );
not ( n25982 , n25981 );
and ( n25983 , n25977 , n25982 );
nor ( n25984 , n25980 , n25983 );
not ( n25985 , n25984 );
not ( n25986 , n25985 );
buf ( n25987 , n19541 );
xor ( n25988 , n23983 , n25987 );
xnor ( n25989 , n25988 , n20464 );
nand ( n25990 , n25986 , n25989 );
not ( n25991 , n25990 );
not ( n25992 , n11755 );
not ( n25993 , n25992 );
not ( n25994 , n23686 );
not ( n25995 , n7314 );
or ( n25996 , n25994 , n25995 );
not ( n25997 , n23686 );
nand ( n25998 , n25997 , n25202 );
nand ( n25999 , n25996 , n25998 );
not ( n26000 , n25999 );
or ( n26001 , n25993 , n26000 );
or ( n26002 , n25992 , n25999 );
nand ( n26003 , n26001 , n26002 );
not ( n26004 , n26003 );
and ( n26005 , n25991 , n26004 );
not ( n26006 , n25985 );
nand ( n26007 , n26006 , n25989 );
and ( n26008 , n26007 , n26003 );
nor ( n26009 , n26005 , n26008 );
not ( n26010 , n26009 );
or ( n26011 , n25971 , n26010 );
or ( n26012 , n26009 , n25970 );
nand ( n26013 , n26011 , n26012 );
not ( n26014 , n26013 );
buf ( n26015 , n7353 );
not ( n26016 , n26015 );
not ( n26017 , n18237 );
or ( n26018 , n26016 , n26017 );
or ( n26019 , n18237 , n26015 );
nand ( n26020 , n26018 , n26019 );
xnor ( n26021 , n26020 , n18261 );
not ( n26022 , n26021 );
not ( n26023 , n23917 );
not ( n26024 , n12030 );
not ( n26025 , n16913 );
or ( n26026 , n26024 , n26025 );
or ( n26027 , n16913 , n12030 );
nand ( n26028 , n26026 , n26027 );
not ( n26029 , n26028 );
or ( n26030 , n26023 , n26029 );
not ( n26031 , n23916 );
not ( n26032 , n26031 );
or ( n26033 , n26028 , n26032 );
nand ( n26034 , n26030 , n26033 );
nand ( n26035 , n26022 , n26034 );
not ( n26036 , n26035 );
not ( n26037 , n17039 );
not ( n26038 , n14903 );
and ( n26039 , n26037 , n26038 );
and ( n26040 , n17039 , n14903 );
nor ( n26041 , n26039 , n26040 );
and ( n26042 , n26041 , n25682 );
not ( n26043 , n26041 );
and ( n26044 , n26043 , n25545 );
nor ( n26045 , n26042 , n26044 );
not ( n26046 , n26045 );
and ( n26047 , n26036 , n26046 );
and ( n26048 , n26035 , n26045 );
nor ( n26049 , n26047 , n26048 );
not ( n26050 , n26049 );
not ( n26051 , n25815 );
not ( n26052 , n20776 );
not ( n26053 , n12284 );
and ( n26054 , n26052 , n26053 );
not ( n26055 , n12285 );
and ( n26056 , n20776 , n26055 );
nor ( n26057 , n26054 , n26056 );
not ( n26058 , n26057 );
or ( n26059 , n26051 , n26058 );
or ( n26060 , n26057 , n25815 );
nand ( n26061 , n26059 , n26060 );
not ( n26062 , n18377 );
not ( n26063 , n20517 );
or ( n26064 , n26062 , n26063 );
or ( n26065 , n20517 , n18377 );
nand ( n26066 , n26064 , n26065 );
xor ( n26067 , n26066 , n23180 );
nand ( n26068 , n26061 , n26067 );
not ( n26069 , n12787 );
not ( n26070 , n9374 );
or ( n26071 , n26069 , n26070 );
not ( n26072 , n12787 );
nand ( n26073 , n26072 , n9373 );
nand ( n26074 , n26071 , n26073 );
and ( n26075 , n26074 , n22803 );
not ( n26076 , n26074 );
and ( n26077 , n26076 , n22802 );
nor ( n26078 , n26075 , n26077 );
and ( n26079 , n26068 , n26078 );
not ( n26080 , n26068 );
not ( n26081 , n26078 );
and ( n26082 , n26080 , n26081 );
nor ( n26083 , n26079 , n26082 );
not ( n26084 , n26083 );
or ( n26085 , n26050 , n26084 );
or ( n26086 , n26083 , n26049 );
nand ( n26087 , n26085 , n26086 );
not ( n26088 , n25726 );
not ( n26089 , n12650 );
not ( n26090 , n26089 );
not ( n26091 , n19874 );
or ( n26092 , n26090 , n26091 );
or ( n26093 , n19874 , n26089 );
nand ( n26094 , n26092 , n26093 );
not ( n26095 , n26094 );
and ( n26096 , n26088 , n26095 );
and ( n26097 , n8568 , n26094 );
nor ( n26098 , n26096 , n26097 );
not ( n26099 , n26098 );
buf ( n26100 , n20069 );
and ( n26101 , n26100 , n17358 );
not ( n26102 , n26100 );
and ( n26103 , n26102 , n12206 );
nor ( n26104 , n26101 , n26103 );
not ( n26105 , n26104 );
not ( n26106 , n26105 );
not ( n26107 , n17361 );
or ( n26108 , n26106 , n26107 );
nand ( n26109 , n12236 , n26104 );
nand ( n26110 , n26108 , n26109 );
not ( n26111 , n26110 );
nand ( n26112 , n26099 , n26111 );
not ( n26113 , n26112 );
buf ( n26114 , n17864 );
xor ( n26115 , n26114 , n24471 );
xnor ( n26116 , n26115 , n24435 );
not ( n26117 , n26116 );
and ( n26118 , n26113 , n26117 );
and ( n26119 , n26112 , n26116 );
nor ( n26120 , n26118 , n26119 );
and ( n26121 , n26087 , n26120 );
not ( n26122 , n26087 );
not ( n26123 , n26120 );
and ( n26124 , n26122 , n26123 );
nor ( n26125 , n26121 , n26124 );
not ( n26126 , n26125 );
or ( n26127 , n26014 , n26126 );
or ( n26128 , n26013 , n26125 );
nand ( n26129 , n26127 , n26128 );
buf ( n26130 , n26129 );
not ( n26131 , n26130 );
not ( n26132 , n26131 );
not ( n26133 , n26132 );
and ( n26134 , n25933 , n26133 );
not ( n26135 , n25933 );
not ( n26136 , n26130 );
not ( n26137 , n26136 );
and ( n26138 , n26135 , n26137 );
nor ( n26139 , n26134 , n26138 );
not ( n26140 , n21587 );
not ( n26141 , n6843 );
not ( n26142 , n26141 );
not ( n26143 , n25168 );
or ( n26144 , n26142 , n26143 );
nand ( n26145 , n14393 , n6843 );
nand ( n26146 , n26144 , n26145 );
not ( n26147 , n26146 );
or ( n26148 , n26140 , n26147 );
or ( n26149 , n26146 , n12594 );
nand ( n26150 , n26148 , n26149 );
not ( n26151 , n26150 );
not ( n26152 , n22656 );
not ( n26153 , n14224 );
or ( n26154 , n26152 , n26153 );
not ( n26155 , n22656 );
nand ( n26156 , n26155 , n14220 );
nand ( n26157 , n26154 , n26156 );
and ( n26158 , n26157 , n14268 );
not ( n26159 , n26157 );
and ( n26160 , n26159 , n14272 );
nor ( n26161 , n26158 , n26160 );
not ( n26162 , n26161 );
nand ( n26163 , n26151 , n26162 );
xor ( n26164 , n19454 , n13537 );
xnor ( n26165 , n26164 , n17614 );
buf ( n26166 , n26165 );
xor ( n26167 , n26163 , n26166 );
not ( n26168 , n26167 );
not ( n26169 , n26168 );
not ( n26170 , n14993 );
not ( n26171 , n12102 );
not ( n26172 , n21983 );
or ( n26173 , n26171 , n26172 );
nand ( n26174 , n21988 , n12105 );
nand ( n26175 , n26173 , n26174 );
not ( n26176 , n26175 );
or ( n26177 , n26170 , n26176 );
or ( n26178 , n26175 , n14993 );
nand ( n26179 , n26177 , n26178 );
not ( n26180 , n26179 );
not ( n26181 , n17083 );
not ( n26182 , n18378 );
or ( n26183 , n26181 , n26182 );
or ( n26184 , n18372 , n17083 );
nand ( n26185 , n26183 , n26184 );
buf ( n26186 , n19773 );
and ( n26187 , n26185 , n26186 );
not ( n26188 , n26185 );
and ( n26189 , n26188 , n10271 );
or ( n26190 , n26187 , n26189 );
nand ( n26191 , n26180 , n26190 );
not ( n26192 , n26191 );
not ( n26193 , n17824 );
not ( n26194 , n24435 );
or ( n26195 , n26193 , n26194 );
or ( n26196 , n24435 , n17824 );
nand ( n26197 , n26195 , n26196 );
buf ( n26198 , n6455 );
buf ( n26199 , n26198 );
not ( n26200 , n26199 );
not ( n26201 , n18041 );
not ( n26202 , n26201 );
or ( n26203 , n26200 , n26202 );
not ( n26204 , n26198 );
nand ( n26205 , n26204 , n18042 );
nand ( n26206 , n26203 , n26205 );
buf ( n26207 , n6456 );
buf ( n26208 , n26207 );
and ( n26209 , n26206 , n26208 );
not ( n26210 , n26206 );
not ( n26211 , n26207 );
and ( n26212 , n26210 , n26211 );
nor ( n26213 , n26209 , n26212 );
buf ( n26214 , n6457 );
nand ( n26215 , n6871 , n26214 );
buf ( n26216 , n6458 );
buf ( n26217 , n26216 );
and ( n26218 , n26215 , n26217 );
not ( n26219 , n26215 );
not ( n26220 , n26216 );
and ( n26221 , n26219 , n26220 );
nor ( n26222 , n26218 , n26221 );
xor ( n26223 , n26213 , n26222 );
xnor ( n26224 , n26223 , n22730 );
buf ( n26225 , n26224 );
not ( n26226 , n26225 );
and ( n26227 , n26197 , n26226 );
not ( n26228 , n26197 );
and ( n26229 , n26228 , n26225 );
nor ( n26230 , n26227 , n26229 );
not ( n26231 , n26230 );
not ( n26232 , n26231 );
and ( n26233 , n26192 , n26232 );
and ( n26234 , n26191 , n26231 );
nor ( n26235 , n26233 , n26234 );
not ( n26236 , n26235 );
nand ( n26237 , n26165 , n26150 );
not ( n26238 , n18730 );
not ( n26239 , n12256 );
not ( n26240 , n20782 );
or ( n26241 , n26239 , n26240 );
nand ( n26242 , n20776 , n12252 );
nand ( n26243 , n26241 , n26242 );
not ( n26244 , n26243 );
or ( n26245 , n26238 , n26244 );
not ( n26246 , n26243 );
nand ( n26247 , n26246 , n25815 );
nand ( n26248 , n26245 , n26247 );
not ( n26249 , n26248 );
and ( n26250 , n26237 , n26249 );
not ( n26251 , n26237 );
and ( n26252 , n26251 , n26248 );
nor ( n26253 , n26250 , n26252 );
not ( n26254 , n26253 );
or ( n26255 , n26236 , n26254 );
or ( n26256 , n26253 , n26235 );
nand ( n26257 , n26255 , n26256 );
not ( n26258 , n15662 );
not ( n26259 , n23973 );
xor ( n26260 , n23964 , n26259 );
xnor ( n26261 , n26260 , n23983 );
buf ( n26262 , n26261 );
not ( n26263 , n26262 );
or ( n26264 , n26258 , n26263 );
buf ( n26265 , n23984 );
buf ( n26266 , n26265 );
nand ( n26267 , n26266 , n15659 );
nand ( n26268 , n26264 , n26267 );
buf ( n26269 , n23991 );
not ( n26270 , n26269 );
and ( n26271 , n26268 , n26270 );
not ( n26272 , n26268 );
and ( n26273 , n26272 , n26269 );
nor ( n26274 , n26271 , n26273 );
not ( n26275 , n26274 );
not ( n26276 , n7136 );
not ( n26277 , n24754 );
not ( n26278 , n7127 );
not ( n26279 , n26278 );
or ( n26280 , n26277 , n26279 );
not ( n26281 , n24754 );
nand ( n26282 , n26281 , n7128 );
nand ( n26283 , n26280 , n26282 );
not ( n26284 , n26283 );
and ( n26285 , n26276 , n26284 );
and ( n26286 , n7136 , n26283 );
nor ( n26287 , n26285 , n26286 );
not ( n26288 , n26287 );
nand ( n26289 , n26275 , n26288 );
not ( n26290 , n8097 );
not ( n26291 , n11108 );
or ( n26292 , n26290 , n26291 );
or ( n26293 , n6741 , n8097 );
nand ( n26294 , n26292 , n26293 );
and ( n26295 , n26294 , n24315 );
not ( n26296 , n26294 );
and ( n26297 , n26296 , n24312 );
nor ( n26298 , n26295 , n26297 );
buf ( n26299 , n26298 );
xnor ( n26300 , n26289 , n26299 );
xnor ( n26301 , n26257 , n26300 );
buf ( n26302 , n24494 );
not ( n26303 , n26302 );
buf ( n26304 , n11672 );
not ( n26305 , n26304 );
or ( n26306 , n26303 , n26305 );
nand ( n26307 , n20232 , n24495 );
nand ( n26308 , n26306 , n26307 );
xor ( n26309 , n11719 , n20107 );
buf ( n26310 , n11697 );
xnor ( n26311 , n26309 , n26310 );
buf ( n26312 , n26311 );
buf ( n26313 , n26312 );
and ( n26314 , n26308 , n26313 );
not ( n26315 , n26308 );
buf ( n26316 , n11727 );
and ( n26317 , n26315 , n26316 );
nor ( n26318 , n26314 , n26317 );
not ( n26319 , n26318 );
xor ( n26320 , n25129 , n17676 );
buf ( n26321 , n22938 );
xnor ( n26322 , n26320 , n26321 );
not ( n26323 , n26322 );
not ( n26324 , n12590 );
not ( n26325 , n25487 );
not ( n26326 , n26325 );
or ( n26327 , n26324 , n26326 );
or ( n26328 , n26325 , n12590 );
nand ( n26329 , n26327 , n26328 );
and ( n26330 , n26329 , n25494 );
not ( n26331 , n26329 );
buf ( n26332 , n21772 );
and ( n26333 , n26331 , n26332 );
nor ( n26334 , n26330 , n26333 );
not ( n26335 , n26334 );
nand ( n26336 , n26323 , n26335 );
not ( n26337 , n26336 );
or ( n26338 , n26319 , n26337 );
not ( n26339 , n26335 );
not ( n26340 , n26339 );
nand ( n26341 , n26340 , n26323 );
or ( n26342 , n26341 , n26318 );
nand ( n26343 , n26338 , n26342 );
not ( n26344 , n26343 );
not ( n26345 , n11246 );
not ( n26346 , n20576 );
or ( n26347 , n26345 , n26346 );
nand ( n26348 , n20575 , n11249 );
nand ( n26349 , n26347 , n26348 );
not ( n26350 , n26349 );
not ( n26351 , n14692 );
and ( n26352 , n26350 , n26351 );
and ( n26353 , n14692 , n26349 );
nor ( n26354 , n26352 , n26353 );
buf ( n26355 , n15872 );
not ( n26356 , n15868 );
and ( n26357 , n26355 , n26356 );
not ( n26358 , n26355 );
and ( n26359 , n26358 , n15869 );
or ( n26360 , n26357 , n26359 );
not ( n26361 , n26360 );
not ( n26362 , n8986 );
or ( n26363 , n26361 , n26362 );
or ( n26364 , n8986 , n26360 );
nand ( n26365 , n26363 , n26364 );
and ( n26366 , n26365 , n7583 );
not ( n26367 , n26365 );
and ( n26368 , n26367 , n7580 );
nor ( n26369 , n26366 , n26368 );
nand ( n26370 , n26354 , n26369 );
not ( n26371 , n26370 );
not ( n26372 , n13615 );
buf ( n26373 , n21883 );
not ( n26374 , n26373 );
or ( n26375 , n26372 , n26374 );
nand ( n26376 , n24767 , n13611 );
nand ( n26377 , n26375 , n26376 );
not ( n26378 , n21892 );
not ( n26379 , n26378 );
xor ( n26380 , n26377 , n26379 );
not ( n26381 , n26380 );
and ( n26382 , n26371 , n26381 );
and ( n26383 , n26370 , n26380 );
nor ( n26384 , n26382 , n26383 );
not ( n26385 , n26384 );
and ( n26386 , n26344 , n26385 );
and ( n26387 , n26343 , n26384 );
nor ( n26388 , n26386 , n26387 );
and ( n26389 , n26301 , n26388 );
not ( n26390 , n26301 );
not ( n26391 , n26388 );
and ( n26392 , n26390 , n26391 );
nor ( n26393 , n26389 , n26392 );
not ( n26394 , n26393 );
or ( n26395 , n26169 , n26394 );
not ( n26396 , n26168 );
and ( n26397 , n26301 , n26391 );
not ( n26398 , n26301 );
and ( n26399 , n26398 , n26388 );
nor ( n26400 , n26397 , n26399 );
nand ( n26401 , n26396 , n26400 );
nand ( n26402 , n26395 , n26401 );
not ( n26403 , n16814 );
buf ( n26404 , n15905 );
not ( n26405 , n26404 );
not ( n26406 , n26405 );
or ( n26407 , n26403 , n26406 );
not ( n26408 , n26404 );
or ( n26409 , n26408 , n16814 );
nand ( n26410 , n26407 , n26409 );
not ( n26411 , n26410 );
not ( n26412 , n20520 );
not ( n26413 , n26412 );
and ( n26414 , n26411 , n26413 );
and ( n26415 , n26410 , n20522 );
nor ( n26416 , n26414 , n26415 );
not ( n26417 , n26416 );
not ( n26418 , n16083 );
not ( n26419 , n14152 );
or ( n26420 , n26418 , n26419 );
or ( n26421 , n14152 , n16083 );
nand ( n26422 , n26420 , n26421 );
and ( n26423 , n26422 , n20232 );
not ( n26424 , n26422 );
buf ( n26425 , n26304 );
and ( n26426 , n26424 , n26425 );
nor ( n26427 , n26423 , n26426 );
not ( n26428 , n26427 );
nand ( n26429 , n26417 , n26428 );
not ( n26430 , n26429 );
not ( n26431 , n15684 );
not ( n26432 , n26262 );
or ( n26433 , n26431 , n26432 );
not ( n26434 , n15684 );
nand ( n26435 , n26434 , n26265 );
nand ( n26436 , n26433 , n26435 );
and ( n26437 , n26436 , n26270 );
not ( n26438 , n26436 );
and ( n26439 , n26438 , n26269 );
nor ( n26440 , n26437 , n26439 );
not ( n26441 , n26440 );
and ( n26442 , n26430 , n26441 );
and ( n26443 , n26429 , n26440 );
nor ( n26444 , n26442 , n26443 );
not ( n26445 , n26444 );
not ( n26446 , n26445 );
not ( n26447 , n13718 );
not ( n26448 , n7450 );
buf ( n26449 , n14781 );
nor ( n26450 , n26448 , n26449 );
not ( n26451 , n26450 );
not ( n26452 , n7450 );
nand ( n26453 , n26449 , n26452 );
nand ( n26454 , n26451 , n26453 );
not ( n26455 , n26454 );
or ( n26456 , n26447 , n26455 );
or ( n26457 , n26454 , n7495 );
nand ( n26458 , n26456 , n26457 );
not ( n26459 , n26458 );
not ( n26460 , n17515 );
not ( n26461 , n20338 );
or ( n26462 , n26460 , n26461 );
nand ( n26463 , n20341 , n17511 );
nand ( n26464 , n26462 , n26463 );
and ( n26465 , n26464 , n20344 );
not ( n26466 , n26464 );
and ( n26467 , n26466 , n20345 );
nor ( n26468 , n26465 , n26467 );
not ( n26469 , n26468 );
nand ( n26470 , n26459 , n26469 );
buf ( n26471 , n14936 );
and ( n26472 , n14940 , n26471 );
not ( n26473 , n14940 );
and ( n26474 , n26473 , n14937 );
nor ( n26475 , n26472 , n26474 );
not ( n26476 , n26475 );
not ( n26477 , n25545 );
or ( n26478 , n26476 , n26477 );
or ( n26479 , n25683 , n26475 );
nand ( n26480 , n26478 , n26479 );
and ( n26481 , n26480 , n25552 );
not ( n26482 , n26480 );
and ( n26483 , n26482 , n25549 );
nor ( n26484 , n26481 , n26483 );
not ( n26485 , n26484 );
and ( n26486 , n26470 , n26485 );
not ( n26487 , n26470 );
and ( n26488 , n26487 , n26484 );
nor ( n26489 , n26486 , n26488 );
not ( n26490 , n26489 );
not ( n26491 , n26490 );
or ( n26492 , n26446 , n26491 );
nand ( n26493 , n26489 , n26444 );
nand ( n26494 , n26492 , n26493 );
not ( n26495 , n16458 );
not ( n26496 , n7596 );
xor ( n26497 , n22642 , n22646 );
xnor ( n26498 , n26497 , n22656 );
not ( n26499 , n26498 );
or ( n26500 , n26496 , n26499 );
or ( n26501 , n26498 , n7596 );
nand ( n26502 , n26500 , n26501 );
not ( n26503 , n26502 );
or ( n26504 , n26495 , n26503 );
or ( n26505 , n26502 , n25825 );
nand ( n26506 , n26504 , n26505 );
buf ( n26507 , n17849 );
not ( n26508 , n26507 );
not ( n26509 , n24433 );
xor ( n26510 , n24424 , n26509 );
xnor ( n26511 , n26510 , n20427 );
not ( n26512 , n26511 );
or ( n26513 , n26508 , n26512 );
or ( n26514 , n26511 , n26507 );
nand ( n26515 , n26513 , n26514 );
and ( n26516 , n26515 , n26226 );
not ( n26517 , n26515 );
not ( n26518 , n26224 );
not ( n26519 , n26518 );
and ( n26520 , n26517 , n26519 );
nor ( n26521 , n26516 , n26520 );
nand ( n26522 , n26506 , n26521 );
not ( n26523 , n25476 );
not ( n26524 , n20300 );
or ( n26525 , n26523 , n26524 );
or ( n26526 , n20300 , n25476 );
nand ( n26527 , n26525 , n26526 );
and ( n26528 , n26527 , n18462 );
not ( n26529 , n26527 );
buf ( n26530 , n18461 );
and ( n26531 , n26529 , n26530 );
nor ( n26532 , n26528 , n26531 );
not ( n26533 , n26532 );
and ( n26534 , n26522 , n26533 );
not ( n26535 , n26522 );
and ( n26536 , n26535 , n26532 );
nor ( n26537 , n26534 , n26536 );
not ( n26538 , n14691 );
buf ( n26539 , n11260 );
not ( n26540 , n26539 );
not ( n26541 , n14683 );
or ( n26542 , n26540 , n26541 );
or ( n26543 , n14683 , n26539 );
nand ( n26544 , n26542 , n26543 );
not ( n26545 , n26544 );
not ( n26546 , n26545 );
or ( n26547 , n26538 , n26546 );
nand ( n26548 , n14692 , n26544 );
nand ( n26549 , n26547 , n26548 );
not ( n26550 , n26549 );
not ( n26551 , n23598 );
not ( n26552 , n9246 );
not ( n26553 , n17717 );
or ( n26554 , n26552 , n26553 );
not ( n26555 , n23593 );
or ( n26556 , n26555 , n9246 );
nand ( n26557 , n26554 , n26556 );
not ( n26558 , n26557 );
or ( n26559 , n26551 , n26558 );
or ( n26560 , n26557 , n17724 );
nand ( n26561 , n26559 , n26560 );
nand ( n26562 , n26550 , n26561 );
not ( n26563 , n26562 );
buf ( n26564 , n6459 );
buf ( n26565 , n26564 );
not ( n26566 , n26565 );
buf ( n26567 , n6460 );
not ( n26568 , n26567 );
not ( n26569 , n26568 );
or ( n26570 , n26566 , n26569 );
not ( n26571 , n26564 );
buf ( n26572 , n26567 );
nand ( n26573 , n26571 , n26572 );
nand ( n26574 , n26570 , n26573 );
buf ( n26575 , n6461 );
not ( n26576 , n26575 );
and ( n26577 , n26574 , n26576 );
not ( n26578 , n26574 );
buf ( n26579 , n26575 );
and ( n26580 , n26578 , n26579 );
nor ( n26581 , n26577 , n26580 );
buf ( n26582 , n6462 );
nand ( n26583 , n8966 , n26582 );
buf ( n26584 , n6463 );
buf ( n26585 , n26584 );
and ( n26586 , n26583 , n26585 );
not ( n26587 , n26583 );
not ( n26588 , n26584 );
and ( n26589 , n26587 , n26588 );
nor ( n26590 , n26586 , n26589 );
xor ( n26591 , n26581 , n26590 );
xor ( n26592 , n26591 , n20242 );
buf ( n26593 , n26592 );
not ( n26594 , n26593 );
buf ( n26595 , n14348 );
not ( n26596 , n26595 );
not ( n26597 , n26596 );
not ( n26598 , n13087 );
or ( n26599 , n26597 , n26598 );
xor ( n26600 , n13066 , n13085 );
buf ( n26601 , n13075 );
xnor ( n26602 , n26600 , n26601 );
nand ( n26603 , n26602 , n26595 );
nand ( n26604 , n26599 , n26603 );
not ( n26605 , n26604 );
or ( n26606 , n26594 , n26605 );
or ( n26607 , n26604 , n26593 );
nand ( n26608 , n26606 , n26607 );
not ( n26609 , n26608 );
and ( n26610 , n26563 , n26609 );
and ( n26611 , n26562 , n26608 );
nor ( n26612 , n26610 , n26611 );
or ( n26613 , n26537 , n26612 );
nand ( n26614 , n26612 , n26537 );
nand ( n26615 , n26613 , n26614 );
not ( n26616 , n12512 );
not ( n26617 , n10096 );
not ( n26618 , n10108 );
xor ( n26619 , n26617 , n26618 );
xnor ( n26620 , n26619 , n10124 );
not ( n26621 , n26620 );
or ( n26622 , n26616 , n26621 );
or ( n26623 , n26620 , n12512 );
nand ( n26624 , n26622 , n26623 );
not ( n26625 , n26624 );
not ( n26626 , n18498 );
not ( n26627 , n18520 );
or ( n26628 , n26626 , n26627 );
nand ( n26629 , n26628 , n18524 );
not ( n26630 , n26629 );
not ( n26631 , n26630 );
and ( n26632 , n26625 , n26631 );
and ( n26633 , n26624 , n26630 );
nor ( n26634 , n26632 , n26633 );
not ( n26635 , n26634 );
not ( n26636 , n8619 );
not ( n26637 , n12459 );
xor ( n26638 , n12265 , n12284 );
not ( n26639 , n12274 );
xnor ( n26640 , n26638 , n26639 );
not ( n26641 , n26640 );
or ( n26642 , n26637 , n26641 );
or ( n26643 , n12286 , n12459 );
nand ( n26644 , n26642 , n26643 );
not ( n26645 , n26644 );
or ( n26646 , n26636 , n26645 );
or ( n26647 , n26644 , n8620 );
nand ( n26648 , n26646 , n26647 );
not ( n26649 , n26648 );
nand ( n26650 , n26635 , n26649 );
not ( n26651 , n26650 );
not ( n26652 , n12236 );
buf ( n26653 , n20036 );
not ( n26654 , n22245 );
and ( n26655 , n26653 , n26654 );
not ( n26656 , n26653 );
and ( n26657 , n26656 , n22245 );
nor ( n26658 , n26655 , n26657 );
not ( n26659 , n26658 );
and ( n26660 , n26652 , n26659 );
and ( n26661 , n12236 , n26658 );
nor ( n26662 , n26660 , n26661 );
not ( n26663 , n26662 );
not ( n26664 , n26663 );
and ( n26665 , n26651 , n26664 );
and ( n26666 , n26650 , n26663 );
nor ( n26667 , n26665 , n26666 );
and ( n26668 , n26615 , n26667 );
not ( n26669 , n26615 );
not ( n26670 , n26667 );
and ( n26671 , n26669 , n26670 );
nor ( n26672 , n26668 , n26671 );
and ( n26673 , n26494 , n26672 );
not ( n26674 , n26494 );
not ( n26675 , n26672 );
and ( n26676 , n26674 , n26675 );
nor ( n26677 , n26673 , n26676 );
not ( n26678 , n26677 );
not ( n26679 , n26678 );
and ( n26680 , n26402 , n26679 );
not ( n26681 , n26402 );
not ( n26682 , n26494 );
not ( n26683 , n26672 );
or ( n26684 , n26682 , n26683 );
not ( n26685 , n26494 );
nand ( n26686 , n26685 , n26675 );
nand ( n26687 , n26684 , n26686 );
buf ( n26688 , n26687 );
and ( n26689 , n26681 , n26688 );
nor ( n26690 , n26680 , n26689 );
nand ( n26691 , n26139 , n26690 );
or ( n26692 , n25662 , n26691 );
not ( n26693 , n25659 );
not ( n26694 , n26690 );
or ( n26695 , n26693 , n26694 );
buf ( n26696 , n13349 );
nor ( n26697 , n26139 , n26696 );
nand ( n26698 , n26695 , n26697 );
buf ( n26699 , n13353 );
nand ( n26700 , n26699 , n7431 );
nand ( n26701 , n26692 , n26698 , n26700 );
buf ( n26702 , n26701 );
buf ( n26703 , n26702 );
xor ( n26704 , n10920 , n24055 );
xnor ( n26705 , n26704 , n24058 );
not ( n26706 , n26705 );
not ( n26707 , n12569 );
not ( n26708 , n26325 );
not ( n26709 , n26708 );
or ( n26710 , n26707 , n26709 );
buf ( n26711 , n25487 );
not ( n26712 , n26711 );
nand ( n26713 , n26712 , n12566 );
nand ( n26714 , n26710 , n26713 );
and ( n26715 , n26714 , n25494 );
not ( n26716 , n26714 );
and ( n26717 , n26716 , n26332 );
nor ( n26718 , n26715 , n26717 );
not ( n26719 , n26718 );
nand ( n26720 , n26706 , n26719 );
not ( n26721 , n26720 );
not ( n26722 , n10227 );
not ( n26723 , n9053 );
not ( n26724 , n23363 );
or ( n26725 , n26723 , n26724 );
not ( n26726 , n9053 );
nand ( n26727 , n26726 , n10175 );
nand ( n26728 , n26725 , n26727 );
not ( n26729 , n26728 );
or ( n26730 , n26722 , n26729 );
or ( n26731 , n26728 , n10227 );
nand ( n26732 , n26730 , n26731 );
buf ( n26733 , n26732 );
not ( n26734 , n26733 );
and ( n26735 , n26721 , n26734 );
and ( n26736 , n26720 , n26733 );
nor ( n26737 , n26735 , n26736 );
not ( n26738 , n26737 );
not ( n26739 , n17298 );
not ( n26740 , n12441 );
or ( n26741 , n26739 , n26740 );
or ( n26742 , n12441 , n17298 );
nand ( n26743 , n26741 , n26742 );
xor ( n26744 , n12462 , n26743 );
not ( n26745 , n19335 );
not ( n26746 , n21230 );
or ( n26747 , n26745 , n26746 );
nand ( n26748 , n21229 , n19331 );
nand ( n26749 , n26747 , n26748 );
and ( n26750 , n26749 , n21265 );
not ( n26751 , n26749 );
and ( n26752 , n26751 , n21262 );
or ( n26753 , n26750 , n26752 );
and ( n26754 , n26753 , n15291 );
not ( n26755 , n26753 );
and ( n26756 , n26755 , n21217 );
nor ( n26757 , n26754 , n26756 );
nand ( n26758 , n26744 , n26757 );
not ( n26759 , n26758 );
not ( n26760 , n22889 );
buf ( n26761 , n16327 );
not ( n26762 , n26761 );
not ( n26763 , n17908 );
or ( n26764 , n26762 , n26763 );
or ( n26765 , n17908 , n26761 );
nand ( n26766 , n26764 , n26765 );
not ( n26767 , n26766 );
or ( n26768 , n26760 , n26767 );
or ( n26769 , n26766 , n22889 );
nand ( n26770 , n26768 , n26769 );
not ( n26771 , n26770 );
and ( n26772 , n26759 , n26771 );
and ( n26773 , n26758 , n26770 );
nor ( n26774 , n26772 , n26773 );
not ( n26775 , n26774 );
not ( n26776 , n23955 );
not ( n26777 , n20937 );
or ( n26778 , n26776 , n26777 );
not ( n26779 , n23955 );
nand ( n26780 , n26779 , n20462 );
nand ( n26781 , n26778 , n26780 );
not ( n26782 , n25987 );
and ( n26783 , n26781 , n26782 );
not ( n26784 , n26781 );
and ( n26785 , n26784 , n15429 );
nor ( n26786 , n26783 , n26785 );
not ( n26787 , n22629 );
not ( n26788 , n14219 );
or ( n26789 , n26787 , n26788 );
not ( n26790 , n14220 );
or ( n26791 , n26790 , n22629 );
nand ( n26792 , n26789 , n26791 );
and ( n26793 , n26792 , n14268 );
not ( n26794 , n26792 );
and ( n26795 , n26794 , n14272 );
nor ( n26796 , n26793 , n26795 );
not ( n26797 , n26796 );
nand ( n26798 , n26786 , n26797 );
not ( n26799 , n6601 );
not ( n26800 , n8547 );
or ( n26801 , n26799 , n26800 );
or ( n26802 , n8547 , n6601 );
nand ( n26803 , n26801 , n26802 );
and ( n26804 , n26803 , n15849 );
not ( n26805 , n26803 );
and ( n26806 , n26805 , n10443 );
nor ( n26807 , n26804 , n26806 );
buf ( n26808 , n26807 );
and ( n26809 , n26798 , n26808 );
not ( n26810 , n26798 );
not ( n26811 , n26808 );
and ( n26812 , n26810 , n26811 );
nor ( n26813 , n26809 , n26812 );
not ( n26814 , n26813 );
or ( n26815 , n26775 , n26814 );
or ( n26816 , n26813 , n26774 );
nand ( n26817 , n26815 , n26816 );
not ( n26818 , n26733 );
nand ( n26819 , n26818 , n26705 );
not ( n26820 , n26819 );
not ( n26821 , n22415 );
not ( n26822 , n13835 );
not ( n26823 , n20202 );
or ( n26824 , n26822 , n26823 );
or ( n26825 , n20199 , n13835 );
nand ( n26826 , n26824 , n26825 );
not ( n26827 , n26826 );
and ( n26828 , n26821 , n26827 );
not ( n26829 , n22415 );
not ( n26830 , n26829 );
and ( n26831 , n26830 , n26826 );
nor ( n26832 , n26828 , n26831 );
not ( n26833 , n26832 );
not ( n26834 , n26833 );
and ( n26835 , n26820 , n26834 );
and ( n26836 , n26819 , n26833 );
nor ( n26837 , n26835 , n26836 );
and ( n26838 , n26817 , n26837 );
not ( n26839 , n26817 );
not ( n26840 , n26837 );
and ( n26841 , n26839 , n26840 );
nor ( n26842 , n26838 , n26841 );
not ( n26843 , n26842 );
buf ( n26844 , n9793 );
not ( n26845 , n26844 );
not ( n26846 , n20557 );
not ( n26847 , n26846 );
or ( n26848 , n26845 , n26847 );
or ( n26849 , n20553 , n26844 );
nand ( n26850 , n26848 , n26849 );
not ( n26851 , n22700 );
and ( n26852 , n26850 , n26851 );
not ( n26853 , n26850 );
buf ( n26854 , n22700 );
and ( n26855 , n26853 , n26854 );
nor ( n26856 , n26852 , n26855 );
not ( n26857 , n9884 );
not ( n26858 , n11727 );
or ( n26859 , n26857 , n26858 );
nand ( n26860 , n26312 , n9880 );
nand ( n26861 , n26859 , n26860 );
and ( n26862 , n26861 , n21854 );
not ( n26863 , n26861 );
and ( n26864 , n26863 , n21857 );
nor ( n26865 , n26862 , n26864 );
nand ( n26866 , n26856 , n26865 );
and ( n26867 , n8437 , n16716 );
not ( n26868 , n8437 );
and ( n26869 , n26868 , n16763 );
or ( n26870 , n26867 , n26869 );
not ( n26871 , n14624 );
and ( n26872 , n26870 , n26871 );
not ( n26873 , n26870 );
not ( n26874 , n14624 );
not ( n26875 , n26874 );
and ( n26876 , n26873 , n26875 );
nor ( n26877 , n26872 , n26876 );
not ( n26878 , n26877 );
and ( n26879 , n26866 , n26878 );
not ( n26880 , n26866 );
and ( n26881 , n26880 , n26877 );
nor ( n26882 , n26879 , n26881 );
not ( n26883 , n26882 );
not ( n26884 , n25326 );
not ( n26885 , n24086 );
or ( n26886 , n26884 , n26885 );
not ( n26887 , n24791 );
not ( n26888 , n26887 );
nand ( n26889 , n26888 , n25322 );
nand ( n26890 , n26886 , n26889 );
xnor ( n26891 , n26890 , n18112 );
not ( n26892 , n26891 );
buf ( n26893 , n6464 );
buf ( n26894 , n26893 );
xor ( n26895 , n26894 , n19200 );
xnor ( n26896 , n26895 , n23548 );
nand ( n26897 , n26892 , n26896 );
not ( n26898 , n26897 );
buf ( n26899 , n6465 );
buf ( n26900 , n26899 );
not ( n26901 , n26900 );
buf ( n26902 , n6466 );
not ( n26903 , n26902 );
not ( n26904 , n26903 );
or ( n26905 , n26901 , n26904 );
not ( n26906 , n26899 );
buf ( n26907 , n26902 );
nand ( n26908 , n26906 , n26907 );
nand ( n26909 , n26905 , n26908 );
buf ( n26910 , n6467 );
not ( n26911 , n26910 );
and ( n26912 , n26909 , n26911 );
not ( n26913 , n26909 );
buf ( n26914 , n26910 );
and ( n26915 , n26913 , n26914 );
nor ( n26916 , n26912 , n26915 );
buf ( n26917 , n6468 );
nand ( n26918 , n7912 , n26917 );
buf ( n26919 , n6469 );
buf ( n26920 , n26919 );
and ( n26921 , n26918 , n26920 );
not ( n26922 , n26918 );
not ( n26923 , n26919 );
and ( n26924 , n26922 , n26923 );
nor ( n26925 , n26921 , n26924 );
xor ( n26926 , n26916 , n26925 );
buf ( n26927 , n6470 );
nand ( n26928 , n8455 , n26927 );
buf ( n26929 , n6471 );
buf ( n26930 , n26929 );
and ( n26931 , n26928 , n26930 );
not ( n26932 , n26928 );
not ( n26933 , n26929 );
and ( n26934 , n26932 , n26933 );
nor ( n26935 , n26931 , n26934 );
xor ( n26936 , n26926 , n26935 );
not ( n26937 , n26936 );
xor ( n26938 , n17766 , n26937 );
xnor ( n26939 , n26938 , n26630 );
not ( n26940 , n26939 );
and ( n26941 , n26898 , n26940 );
not ( n26942 , n26891 );
nand ( n26943 , n26942 , n26896 );
and ( n26944 , n26943 , n26939 );
nor ( n26945 , n26941 , n26944 );
not ( n26946 , n26945 );
or ( n26947 , n26883 , n26946 );
or ( n26948 , n26945 , n26882 );
nand ( n26949 , n26947 , n26948 );
not ( n26950 , n26949 );
or ( n26951 , n26843 , n26950 );
not ( n26952 , n26949 );
not ( n26953 , n26842 );
nand ( n26954 , n26952 , n26953 );
nand ( n26955 , n26951 , n26954 );
not ( n26956 , n26955 );
or ( n26957 , n26738 , n26956 );
not ( n26958 , n26737 );
not ( n26959 , n26952 );
not ( n26960 , n26953 );
and ( n26961 , n26959 , n26960 );
and ( n26962 , n26952 , n26953 );
nor ( n26963 , n26961 , n26962 );
nand ( n26964 , n26958 , n26963 );
nand ( n26965 , n26957 , n26964 );
buf ( n26966 , n26393 );
and ( n26967 , n26965 , n26966 );
not ( n26968 , n26965 );
buf ( n26969 , n26400 );
and ( n26970 , n26968 , n26969 );
nor ( n26971 , n26967 , n26970 );
not ( n26972 , n26971 );
not ( n26973 , n23398 );
not ( n26974 , n26973 );
not ( n26975 , n10011 );
not ( n26976 , n10498 );
not ( n26977 , n15748 );
or ( n26978 , n26976 , n26977 );
or ( n26979 , n15748 , n10498 );
nand ( n26980 , n26978 , n26979 );
not ( n26981 , n26980 );
and ( n26982 , n26975 , n26981 );
and ( n26983 , n10011 , n26980 );
nor ( n26984 , n26982 , n26983 );
not ( n26985 , n26984 );
not ( n26986 , n26985 );
not ( n26987 , n26116 );
nand ( n26988 , n26987 , n26110 );
not ( n26989 , n26988 );
or ( n26990 , n26986 , n26989 );
or ( n26991 , n26988 , n26985 );
nand ( n26992 , n26990 , n26991 );
not ( n26993 , n26992 );
not ( n26994 , n17508 );
not ( n26995 , n20337 );
or ( n26996 , n26994 , n26995 );
not ( n26997 , n17508 );
nand ( n26998 , n26997 , n23209 );
nand ( n26999 , n26996 , n26998 );
not ( n27000 , n18897 );
and ( n27001 , n26999 , n27000 );
not ( n27002 , n26999 );
and ( n27003 , n27002 , n18897 );
nor ( n27004 , n27001 , n27003 );
nand ( n27005 , n27004 , n26045 );
not ( n27006 , n27005 );
not ( n27007 , n7756 );
and ( n27008 , n11025 , n9730 );
not ( n27009 , n11025 );
and ( n27010 , n27009 , n18667 );
nor ( n27011 , n27008 , n27010 );
not ( n27012 , n27011 );
not ( n27013 , n27012 );
or ( n27014 , n27007 , n27013 );
nand ( n27015 , n27011 , n25257 );
nand ( n27016 , n27014 , n27015 );
not ( n27017 , n27016 );
or ( n27018 , n27006 , n27017 );
or ( n27019 , n27016 , n27005 );
nand ( n27020 , n27018 , n27019 );
not ( n27021 , n27020 );
not ( n27022 , n27021 );
nand ( n27023 , n26984 , n26116 );
not ( n27024 , n27023 );
not ( n27025 , n19652 );
not ( n27026 , n17139 );
or ( n27027 , n27025 , n27026 );
nand ( n27028 , n9898 , n19648 );
nand ( n27029 , n27027 , n27028 );
not ( n27030 , n27029 );
not ( n27031 , n9942 );
and ( n27032 , n27030 , n27031 );
and ( n27033 , n27029 , n9942 );
nor ( n27034 , n27032 , n27033 );
not ( n27035 , n27034 );
not ( n27036 , n27035 );
and ( n27037 , n27024 , n27036 );
and ( n27038 , n27023 , n27035 );
nor ( n27039 , n27037 , n27038 );
not ( n27040 , n27039 );
not ( n27041 , n27040 );
or ( n27042 , n27022 , n27041 );
nand ( n27043 , n27039 , n27020 );
nand ( n27044 , n27042 , n27043 );
not ( n27045 , n15481 );
buf ( n27046 , n6472 );
not ( n27047 , n26894 );
not ( n27048 , n23545 );
not ( n27049 , n27048 );
or ( n27050 , n27047 , n27049 );
not ( n27051 , n26893 );
nand ( n27052 , n27051 , n23546 );
nand ( n27053 , n27050 , n27052 );
xor ( n27054 , n27046 , n27053 );
not ( n27055 , n19132 );
buf ( n27056 , n6473 );
nand ( n27057 , n6557 , n27056 );
buf ( n27058 , n6474 );
buf ( n27059 , n27058 );
and ( n27060 , n27057 , n27059 );
not ( n27061 , n27057 );
not ( n27062 , n27058 );
and ( n27063 , n27061 , n27062 );
nor ( n27064 , n27060 , n27063 );
not ( n27065 , n27064 );
not ( n27066 , n27065 );
or ( n27067 , n27055 , n27066 );
nand ( n27068 , n27064 , n19116 );
nand ( n27069 , n27067 , n27068 );
xnor ( n27070 , n27054 , n27069 );
buf ( n27071 , n27070 );
not ( n27072 , n27071 );
or ( n27073 , n27045 , n27072 );
or ( n27074 , n27071 , n15481 );
nand ( n27075 , n27073 , n27074 );
and ( n27076 , n27075 , n25767 );
not ( n27077 , n27075 );
and ( n27078 , n27077 , n9136 );
nor ( n27079 , n27076 , n27078 );
nand ( n27080 , n27079 , n26081 );
not ( n27081 , n27080 );
xor ( n27082 , n16519 , n16538 );
not ( n27083 , n16528 );
xor ( n27084 , n27082 , n27083 );
not ( n27085 , n27084 );
not ( n27086 , n27085 );
not ( n27087 , n15772 );
and ( n27088 , n27086 , n27087 );
and ( n27089 , n16541 , n15772 );
nor ( n27090 , n27088 , n27089 );
and ( n27091 , n27090 , n16058 );
not ( n27092 , n27090 );
not ( n27093 , n16057 );
not ( n27094 , n27093 );
buf ( n27095 , n27094 );
and ( n27096 , n27092 , n27095 );
nor ( n27097 , n27091 , n27096 );
buf ( n27098 , n27097 );
not ( n27099 , n27098 );
and ( n27100 , n27081 , n27099 );
and ( n27101 , n27080 , n27098 );
nor ( n27102 , n27100 , n27101 );
not ( n27103 , n27102 );
and ( n27104 , n27044 , n27103 );
not ( n27105 , n27044 );
and ( n27106 , n27105 , n27102 );
nor ( n27107 , n27104 , n27106 );
not ( n27108 , n14230 );
buf ( n27109 , n17860 );
not ( n27110 , n27109 );
or ( n27111 , n27108 , n27110 );
or ( n27112 , n17862 , n14230 );
nand ( n27113 , n27111 , n27112 );
not ( n27114 , n27113 );
not ( n27115 , n22465 );
not ( n27116 , n27115 );
and ( n27117 , n27114 , n27116 );
not ( n27118 , n22464 );
buf ( n27119 , n27118 );
and ( n27120 , n27113 , n27119 );
nor ( n27121 , n27117 , n27120 );
nand ( n27122 , n26003 , n27121 );
not ( n27123 , n27122 );
not ( n27124 , n14018 );
not ( n27125 , n10958 );
or ( n27126 , n27124 , n27125 );
or ( n27127 , n10958 , n14018 );
nand ( n27128 , n27126 , n27127 );
and ( n27129 , n27128 , n13007 );
not ( n27130 , n27128 );
and ( n27131 , n27130 , n12994 );
nor ( n27132 , n27129 , n27131 );
not ( n27133 , n27132 );
and ( n27134 , n27123 , n27133 );
and ( n27135 , n27122 , n27132 );
nor ( n27136 , n27134 , n27135 );
not ( n27137 , n27136 );
not ( n27138 , n27137 );
not ( n27139 , n21598 );
not ( n27140 , n19833 );
or ( n27141 , n27139 , n27140 );
or ( n27142 , n19833 , n21598 );
nand ( n27143 , n27141 , n27142 );
not ( n27144 , n8786 );
and ( n27145 , n27143 , n27144 );
not ( n27146 , n27143 );
and ( n27147 , n27146 , n8786 );
nor ( n27148 , n27145 , n27147 );
not ( n27149 , n27148 );
not ( n27150 , n27149 );
not ( n27151 , n9056 );
not ( n27152 , n23363 );
or ( n27153 , n27151 , n27152 );
buf ( n27154 , n10175 );
nand ( n27155 , n27154 , n9051 );
nand ( n27156 , n27153 , n27155 );
and ( n27157 , n27156 , n10228 );
not ( n27158 , n27156 );
and ( n27159 , n27158 , n25838 );
nor ( n27160 , n27157 , n27159 );
nand ( n27161 , n25969 , n27160 );
not ( n27162 , n27161 );
or ( n27163 , n27150 , n27162 );
or ( n27164 , n27161 , n27149 );
nand ( n27165 , n27163 , n27164 );
not ( n27166 , n27165 );
not ( n27167 , n27166 );
or ( n27168 , n27138 , n27167 );
nand ( n27169 , n27165 , n27136 );
nand ( n27170 , n27168 , n27169 );
not ( n27171 , n27170 );
and ( n27172 , n27107 , n27171 );
not ( n27173 , n27107 );
and ( n27174 , n27173 , n27170 );
nor ( n27175 , n27172 , n27174 );
not ( n27176 , n27175 );
or ( n27177 , n26993 , n27176 );
not ( n27178 , n27175 );
not ( n27179 , n26992 );
nand ( n27180 , n27178 , n27179 );
nand ( n27181 , n27177 , n27180 );
not ( n27182 , n27181 );
and ( n27183 , n26974 , n27182 );
not ( n27184 , n23398 );
and ( n27185 , n27184 , n27181 );
nor ( n27186 , n27183 , n27185 );
nand ( n27187 , n26972 , n27186 );
not ( n27188 , n24155 );
not ( n27189 , n16352 );
not ( n27190 , n17904 );
or ( n27191 , n27189 , n27190 );
or ( n27192 , n17904 , n16352 );
nand ( n27193 , n27191 , n27192 );
and ( n27194 , n27193 , n17908 );
not ( n27195 , n27193 );
and ( n27196 , n27195 , n13399 );
nor ( n27197 , n27194 , n27196 );
nand ( n27198 , n24168 , n27197 );
not ( n27199 , n27198 );
or ( n27200 , n27188 , n27199 );
or ( n27201 , n27198 , n24155 );
nand ( n27202 , n27200 , n27201 );
not ( n27203 , n27202 );
not ( n27204 , n24245 );
or ( n27205 , n27203 , n27204 );
not ( n27206 , n27202 );
nand ( n27207 , n27206 , n24254 );
nand ( n27208 , n27205 , n27207 );
and ( n27209 , n27208 , n24259 );
not ( n27210 , n27208 );
and ( n27211 , n27210 , n23933 );
nor ( n27212 , n27209 , n27211 );
not ( n27213 , n27212 );
buf ( n27214 , n13345 );
nor ( n27215 , n27213 , n27214 );
not ( n27216 , n27215 );
or ( n27217 , n27187 , n27216 );
nand ( n27218 , n27212 , n27186 );
not ( n27219 , n20976 );
nand ( n27220 , n27218 , n26971 , n27219 );
nand ( n27221 , n17813 , n20455 );
nand ( n27222 , n27217 , n27220 , n27221 );
buf ( n27223 , n27222 );
buf ( n27224 , n27223 );
not ( n27225 , n8866 );
xor ( n27226 , n27225 , n8885 );
xnor ( n27227 , n27226 , n8875 );
and ( n27228 , n17588 , n27227 );
not ( n27229 , n17588 );
and ( n27230 , n27229 , n8888 );
nor ( n27231 , n27228 , n27230 );
buf ( n27232 , n8913 );
not ( n27233 , n27232 );
and ( n27234 , n27231 , n27233 );
not ( n27235 , n27231 );
and ( n27236 , n27235 , n27232 );
nor ( n27237 , n27234 , n27236 );
not ( n27238 , n27237 );
not ( n27239 , n10110 );
not ( n27240 , n24961 );
or ( n27241 , n27239 , n27240 );
not ( n27242 , n10110 );
nand ( n27243 , n27242 , n25791 );
nand ( n27244 , n27241 , n27243 );
and ( n27245 , n27244 , n12713 );
not ( n27246 , n27244 );
and ( n27247 , n27246 , n22817 );
nor ( n27248 , n27245 , n27247 );
nand ( n27249 , n27238 , n27248 );
not ( n27250 , n27249 );
not ( n27251 , n14244 );
not ( n27252 , n17860 );
not ( n27253 , n27252 );
not ( n27254 , n27253 );
or ( n27255 , n27251 , n27254 );
not ( n27256 , n14244 );
nand ( n27257 , n27256 , n17861 );
nand ( n27258 , n27255 , n27257 );
and ( n27259 , n27258 , n27119 );
not ( n27260 , n27258 );
not ( n27261 , n27115 );
and ( n27262 , n27260 , n27261 );
nor ( n27263 , n27259 , n27262 );
not ( n27264 , n27263 );
not ( n27265 , n27264 );
and ( n27266 , n27250 , n27265 );
and ( n27267 , n27249 , n27264 );
nor ( n27268 , n27266 , n27267 );
not ( n27269 , n27268 );
nand ( n27270 , n27237 , n27263 );
not ( n27271 , n27270 );
not ( n27272 , n21506 );
not ( n27273 , n7922 );
not ( n27274 , n27273 );
or ( n27275 , n27272 , n27274 );
or ( n27276 , n27273 , n21506 );
nand ( n27277 , n27275 , n27276 );
and ( n27278 , n27277 , n7879 );
not ( n27279 , n27277 );
and ( n27280 , n27279 , n21189 );
nor ( n27281 , n27278 , n27280 );
not ( n27282 , n27281 );
not ( n27283 , n27282 );
and ( n27284 , n27271 , n27283 );
and ( n27285 , n27270 , n27282 );
nor ( n27286 , n27284 , n27285 );
not ( n27287 , n27286 );
buf ( n27288 , n8711 );
not ( n27289 , n27288 );
not ( n27290 , n10850 );
or ( n27291 , n27289 , n27290 );
or ( n27292 , n10850 , n27288 );
nand ( n27293 , n27291 , n27292 );
and ( n27294 , n27293 , n10826 );
not ( n27295 , n27293 );
and ( n27296 , n27295 , n25964 );
nor ( n27297 , n27294 , n27296 );
buf ( n27298 , n13030 );
not ( n27299 , n27298 );
not ( n27300 , n21991 );
or ( n27301 , n27299 , n27300 );
or ( n27302 , n21991 , n27298 );
nand ( n27303 , n27301 , n27302 );
and ( n27304 , n27303 , n15046 );
not ( n27305 , n27303 );
and ( n27306 , n27305 , n15053 );
nor ( n27307 , n27304 , n27306 );
nand ( n27308 , n27297 , n27307 );
not ( n27309 , n17767 );
not ( n27310 , n16503 );
and ( n27311 , n27309 , n27310 );
and ( n27312 , n17767 , n16503 );
nor ( n27313 , n27311 , n27312 );
xor ( n27314 , n14175 , n27313 );
and ( n27315 , n27308 , n27314 );
not ( n27316 , n27308 );
not ( n27317 , n27314 );
and ( n27318 , n27316 , n27317 );
nor ( n27319 , n27315 , n27318 );
not ( n27320 , n27319 );
or ( n27321 , n27287 , n27320 );
or ( n27322 , n27319 , n27286 );
nand ( n27323 , n27321 , n27322 );
buf ( n27324 , n26222 );
not ( n27325 , n27324 );
not ( n27326 , n27325 );
not ( n27327 , n18082 );
or ( n27328 , n27326 , n27327 );
nand ( n27329 , n22733 , n27324 );
nand ( n27330 , n27328 , n27329 );
not ( n27331 , n27330 );
not ( n27332 , n8762 );
or ( n27333 , n27331 , n27332 );
or ( n27334 , n22741 , n27330 );
nand ( n27335 , n27333 , n27334 );
not ( n27336 , n15073 );
not ( n27337 , n15701 );
or ( n27338 , n27336 , n27337 );
or ( n27339 , n14509 , n15073 );
nand ( n27340 , n27338 , n27339 );
not ( n27341 , n27340 );
not ( n27342 , n16898 );
and ( n27343 , n27341 , n27342 );
and ( n27344 , n27340 , n22757 );
nor ( n27345 , n27343 , n27344 );
nand ( n27346 , n27335 , n27345 );
not ( n27347 , n10036 );
not ( n27348 , n27347 );
xor ( n27349 , n25275 , n27348 );
xnor ( n27350 , n27349 , n18112 );
and ( n27351 , n27346 , n27350 );
not ( n27352 , n27346 );
not ( n27353 , n27350 );
and ( n27354 , n27352 , n27353 );
nor ( n27355 , n27351 , n27354 );
xor ( n27356 , n27323 , n27355 );
not ( n27357 , n27356 );
not ( n27358 , n10823 );
not ( n27359 , n18705 );
or ( n27360 , n27358 , n27359 );
not ( n27361 , n10823 );
nand ( n27362 , n27361 , n22563 );
nand ( n27363 , n27360 , n27362 );
buf ( n27364 , n12342 );
and ( n27365 , n27363 , n27364 );
not ( n27366 , n27363 );
and ( n27367 , n27366 , n18714 );
nor ( n27368 , n27365 , n27367 );
not ( n27369 , n27368 );
xor ( n27370 , n23959 , n15428 );
xnor ( n27371 , n27370 , n20464 );
nand ( n27372 , n27369 , n27371 );
not ( n27373 , n27372 );
not ( n27374 , n8766 );
not ( n27375 , n11272 );
or ( n27376 , n27374 , n27375 );
or ( n27377 , n11272 , n8766 );
nand ( n27378 , n27376 , n27377 );
not ( n27379 , n17419 );
not ( n27380 , n27379 );
and ( n27381 , n27378 , n27380 );
not ( n27382 , n27378 );
buf ( n27383 , n17190 );
and ( n27384 , n27382 , n27383 );
nor ( n27385 , n27381 , n27384 );
not ( n27386 , n27385 );
and ( n27387 , n27373 , n27386 );
not ( n27388 , n27368 );
nand ( n27389 , n27371 , n27388 );
and ( n27390 , n27389 , n27385 );
nor ( n27391 , n27387 , n27390 );
not ( n27392 , n27391 );
and ( n27393 , n9595 , n9592 );
not ( n27394 , n9595 );
buf ( n27395 , n9591 );
and ( n27396 , n27394 , n27395 );
nor ( n27397 , n27393 , n27396 );
xor ( n27398 , n27397 , n23408 );
xnor ( n27399 , n27398 , n10679 );
not ( n27400 , n8065 );
not ( n27401 , n6729 );
or ( n27402 , n27400 , n27401 );
or ( n27403 , n6731 , n8065 );
nand ( n27404 , n27402 , n27403 );
not ( n27405 , n27404 );
not ( n27406 , n11108 );
and ( n27407 , n27405 , n27406 );
not ( n27408 , n6685 );
and ( n27409 , n27404 , n27408 );
nor ( n27410 , n27407 , n27409 );
nand ( n27411 , n27399 , n27410 );
not ( n27412 , n14362 );
buf ( n27413 , n26602 );
not ( n27414 , n27413 );
or ( n27415 , n27412 , n27414 );
or ( n27416 , n27413 , n14362 );
nand ( n27417 , n27415 , n27416 );
not ( n27418 , n26592 );
not ( n27419 , n27418 );
and ( n27420 , n27417 , n27419 );
not ( n27421 , n27417 );
xor ( n27422 , n26581 , n20242 );
buf ( n27423 , n26590 );
xnor ( n27424 , n27422 , n27423 );
not ( n27425 , n27424 );
not ( n27426 , n27425 );
and ( n27427 , n27421 , n27426 );
nor ( n27428 , n27420 , n27427 );
and ( n27429 , n27411 , n27428 );
not ( n27430 , n27411 );
not ( n27431 , n27428 );
and ( n27432 , n27430 , n27431 );
nor ( n27433 , n27429 , n27432 );
not ( n27434 , n27433 );
or ( n27435 , n27392 , n27434 );
or ( n27436 , n27433 , n27391 );
nand ( n27437 , n27435 , n27436 );
not ( n27438 , n27437 );
not ( n27439 , n27438 );
or ( n27440 , n27357 , n27439 );
not ( n27441 , n27356 );
nand ( n27442 , n27441 , n27437 );
nand ( n27443 , n27440 , n27442 );
not ( n27444 , n27443 );
or ( n27445 , n27269 , n27444 );
or ( n27446 , n27443 , n27268 );
nand ( n27447 , n27445 , n27446 );
not ( n27448 , n27447 );
buf ( n27449 , n21523 );
not ( n27450 , n27449 );
not ( n27451 , n7926 );
or ( n27452 , n27450 , n27451 );
or ( n27453 , n7926 , n27449 );
nand ( n27454 , n27452 , n27453 );
and ( n27455 , n27454 , n21189 );
not ( n27456 , n27454 );
and ( n27457 , n27456 , n7879 );
nor ( n27458 , n27455 , n27457 );
not ( n27459 , n18343 );
not ( n27460 , n23174 );
or ( n27461 , n27459 , n27460 );
or ( n27462 , n23174 , n18343 );
nand ( n27463 , n27461 , n27462 );
buf ( n27464 , n20038 );
not ( n27465 , n27464 );
and ( n27466 , n27463 , n27465 );
not ( n27467 , n27463 );
not ( n27468 , n20038 );
not ( n27469 , n27468 );
and ( n27470 , n27467 , n27469 );
nor ( n27471 , n27466 , n27470 );
nor ( n27472 , n27458 , n27471 );
xor ( n27473 , n18703 , n17707 );
xnor ( n27474 , n27473 , n23384 );
not ( n27475 , n27474 );
and ( n27476 , n27472 , n27475 );
not ( n27477 , n27472 );
and ( n27478 , n27477 , n27474 );
nor ( n27479 , n27476 , n27478 );
not ( n27480 , n27479 );
not ( n27481 , n27480 );
not ( n27482 , n10550 );
not ( n27483 , n10010 );
or ( n27484 , n27482 , n27483 );
or ( n27485 , n10010 , n10550 );
nand ( n27486 , n27484 , n27485 );
and ( n27487 , n27486 , n13457 );
not ( n27488 , n27486 );
and ( n27489 , n27488 , n9990 );
nor ( n27490 , n27487 , n27489 );
not ( n27491 , n27490 );
not ( n27492 , n15786 );
not ( n27493 , n16541 );
or ( n27494 , n27492 , n27493 );
not ( n27495 , n15786 );
nand ( n27496 , n27495 , n16540 );
nand ( n27497 , n27494 , n27496 );
and ( n27498 , n27497 , n16058 );
not ( n27499 , n27497 );
and ( n27500 , n27499 , n27095 );
nor ( n27501 , n27498 , n27500 );
nand ( n27502 , n27491 , n27501 );
not ( n27503 , n27502 );
not ( n27504 , n16178 );
buf ( n27505 , n19470 );
xor ( n27506 , n27504 , n27505 );
xnor ( n27507 , n27506 , n10351 );
not ( n27508 , n27507 );
or ( n27509 , n27503 , n27508 );
nand ( n27510 , n27491 , n27501 );
or ( n27511 , n27507 , n27510 );
nand ( n27512 , n27509 , n27511 );
not ( n27513 , n27512 );
not ( n27514 , n27513 );
or ( n27515 , n27481 , n27514 );
nand ( n27516 , n27512 , n27479 );
nand ( n27517 , n27515 , n27516 );
not ( n27518 , n27517 );
buf ( n27519 , n15097 );
not ( n27520 , n27519 );
not ( n27521 , n14507 );
or ( n27522 , n27520 , n27521 );
or ( n27523 , n14507 , n27519 );
nand ( n27524 , n27522 , n27523 );
and ( n27525 , n27524 , n22756 );
not ( n27526 , n27524 );
and ( n27527 , n27526 , n15745 );
nor ( n27528 , n27525 , n27527 );
not ( n27529 , n27528 );
buf ( n27530 , n13590 );
not ( n27531 , n27530 );
not ( n27532 , n19243 );
or ( n27533 , n27531 , n27532 );
or ( n27534 , n19243 , n27530 );
nand ( n27535 , n27533 , n27534 );
and ( n27536 , n27535 , n11272 );
not ( n27537 , n27535 );
and ( n27538 , n27537 , n11275 );
nor ( n27539 , n27536 , n27538 );
not ( n27540 , n9598 );
not ( n27541 , n9911 );
not ( n27542 , n21854 );
or ( n27543 , n27541 , n27542 );
or ( n27544 , n21854 , n9911 );
nand ( n27545 , n27543 , n27544 );
not ( n27546 , n27545 );
or ( n27547 , n27540 , n27546 );
or ( n27548 , n9598 , n27545 );
nand ( n27549 , n27547 , n27548 );
nand ( n27550 , n27539 , n27549 );
not ( n27551 , n27550 );
or ( n27552 , n27529 , n27551 );
or ( n27553 , n27550 , n27528 );
nand ( n27554 , n27552 , n27553 );
not ( n27555 , n27554 );
not ( n27556 , n11105 );
not ( n27557 , n8089 );
not ( n27558 , n6730 );
or ( n27559 , n27557 , n27558 );
not ( n27560 , n8090 );
or ( n27561 , n6734 , n27560 );
nand ( n27562 , n27559 , n27561 );
not ( n27563 , n27562 );
and ( n27564 , n27556 , n27563 );
and ( n27565 , n6741 , n27562 );
nor ( n27566 , n27564 , n27565 );
not ( n27567 , n25311 );
not ( n27568 , n27567 );
not ( n27569 , n27568 );
not ( n27570 , n23305 );
xor ( n27571 , n25335 , n24788 );
xnor ( n27572 , n27571 , n25345 );
not ( n27573 , n27572 );
or ( n27574 , n27570 , n27573 );
or ( n27575 , n27572 , n23305 );
nand ( n27576 , n27574 , n27575 );
not ( n27577 , n27576 );
or ( n27578 , n27569 , n27577 );
or ( n27579 , n27576 , n25312 );
nand ( n27580 , n27578 , n27579 );
nand ( n27581 , n27566 , n27580 );
not ( n27582 , n27581 );
not ( n27583 , n22370 );
not ( n27584 , n15974 );
or ( n27585 , n27583 , n27584 );
not ( n27586 , n22370 );
nand ( n27587 , n27586 , n20845 );
nand ( n27588 , n27585 , n27587 );
not ( n27589 , n27588 );
not ( n27590 , n22557 );
and ( n27591 , n27589 , n27590 );
not ( n27592 , n21444 );
and ( n27593 , n27588 , n27592 );
nor ( n27594 , n27591 , n27593 );
not ( n27595 , n27594 );
not ( n27596 , n27595 );
and ( n27597 , n27582 , n27596 );
and ( n27598 , n27581 , n27595 );
nor ( n27599 , n27597 , n27598 );
not ( n27600 , n27599 );
or ( n27601 , n27555 , n27600 );
or ( n27602 , n27599 , n27554 );
nand ( n27603 , n27601 , n27602 );
not ( n27604 , n7268 );
not ( n27605 , n12466 );
or ( n27606 , n27604 , n27605 );
not ( n27607 , n7268 );
nand ( n27608 , n27607 , n12462 );
nand ( n27609 , n27606 , n27608 );
not ( n27610 , n21949 );
buf ( n27611 , n27610 );
xor ( n27612 , n27609 , n27611 );
not ( n27613 , n11509 );
not ( n27614 , n11554 );
not ( n27615 , n7410 );
not ( n27616 , n27615 );
or ( n27617 , n27614 , n27616 );
or ( n27618 , n27615 , n11554 );
nand ( n27619 , n27617 , n27618 );
not ( n27620 , n27619 );
or ( n27621 , n27613 , n27620 );
or ( n27622 , n27619 , n11509 );
nand ( n27623 , n27621 , n27622 );
nand ( n27624 , n27612 , n27623 );
not ( n27625 , n27624 );
not ( n27626 , n7823 );
not ( n27627 , n7826 );
or ( n27628 , n27626 , n27627 );
or ( n27629 , n7826 , n7823 );
nand ( n27630 , n27628 , n27629 );
not ( n27631 , n27630 );
not ( n27632 , n17589 );
or ( n27633 , n27631 , n27632 );
not ( n27634 , n27630 );
nand ( n27635 , n27634 , n17602 );
nand ( n27636 , n27633 , n27635 );
and ( n27637 , n27636 , n10695 );
not ( n27638 , n27636 );
and ( n27639 , n27638 , n9788 );
nor ( n27640 , n27637 , n27639 );
buf ( n27641 , n27640 );
not ( n27642 , n27641 );
and ( n27643 , n27625 , n27642 );
and ( n27644 , n27624 , n27641 );
nor ( n27645 , n27643 , n27644 );
and ( n27646 , n27603 , n27645 );
not ( n27647 , n27603 );
not ( n27648 , n27645 );
and ( n27649 , n27647 , n27648 );
nor ( n27650 , n27646 , n27649 );
not ( n27651 , n27650 );
and ( n27652 , n27518 , n27651 );
and ( n27653 , n27517 , n27650 );
nor ( n27654 , n27652 , n27653 );
buf ( n27655 , n27654 );
not ( n27656 , n27655 );
and ( n27657 , n27448 , n27656 );
and ( n27658 , n27447 , n27655 );
nor ( n27659 , n27657 , n27658 );
buf ( n27660 , n21737 );
nand ( n27661 , n27659 , n27660 );
not ( n27662 , n11235 );
not ( n27663 , n20571 );
or ( n27664 , n27662 , n27663 );
or ( n27665 , n20576 , n11235 );
nand ( n27666 , n27664 , n27665 );
and ( n27667 , n27666 , n14691 );
not ( n27668 , n27666 );
and ( n27669 , n27668 , n14692 );
nor ( n27670 , n27667 , n27669 );
nand ( n27671 , n23366 , n27670 );
and ( n27672 , n27671 , n23378 );
not ( n27673 , n27671 );
and ( n27674 , n27673 , n23379 );
or ( n27675 , n27672 , n27674 );
not ( n27676 , n27675 );
not ( n27677 , n23399 );
or ( n27678 , n27676 , n27677 );
not ( n27679 , n27675 );
nand ( n27680 , n27679 , n23398 );
nand ( n27681 , n27678 , n27680 );
and ( n27682 , n27681 , n23671 );
not ( n27683 , n27681 );
and ( n27684 , n27683 , n23661 );
nor ( n27685 , n27682 , n27684 );
xor ( n27686 , n20171 , n21622 );
not ( n27687 , n15159 );
not ( n27688 , n15183 );
or ( n27689 , n27687 , n27688 );
nand ( n27690 , n27689 , n15186 );
xnor ( n27691 , n27686 , n27690 );
not ( n27692 , n27691 );
and ( n27693 , n26639 , n20782 );
not ( n27694 , n26639 );
and ( n27695 , n27694 , n20776 );
nor ( n27696 , n27693 , n27695 );
not ( n27697 , n27696 );
and ( n27698 , n25815 , n27697 );
not ( n27699 , n25815 );
and ( n27700 , n27699 , n27696 );
nor ( n27701 , n27698 , n27700 );
not ( n27702 , n8907 );
not ( n27703 , n16193 );
or ( n27704 , n27702 , n27703 );
not ( n27705 , n8906 );
nand ( n27706 , n16167 , n27705 );
nand ( n27707 , n27704 , n27706 );
not ( n27708 , n27707 );
not ( n27709 , n16190 );
or ( n27710 , n27708 , n27709 );
or ( n27711 , n16190 , n27707 );
nand ( n27712 , n27710 , n27711 );
and ( n27713 , n27712 , n13676 );
not ( n27714 , n27712 );
and ( n27715 , n27714 , n13690 );
nor ( n27716 , n27713 , n27715 );
not ( n27717 , n27716 );
nor ( n27718 , n27701 , n27717 );
not ( n27719 , n27718 );
and ( n27720 , n27692 , n27719 );
and ( n27721 , n27691 , n27718 );
nor ( n27722 , n27720 , n27721 );
not ( n27723 , n27722 );
not ( n27724 , n17189 );
not ( n27725 , n14651 );
or ( n27726 , n27724 , n27725 );
or ( n27727 , n14651 , n17189 );
nand ( n27728 , n27726 , n27727 );
and ( n27729 , n27728 , n24925 );
not ( n27730 , n27728 );
not ( n27731 , n24902 );
not ( n27732 , n24924 );
not ( n27733 , n27732 );
or ( n27734 , n27731 , n27733 );
nand ( n27735 , n24924 , n24903 );
nand ( n27736 , n27734 , n27735 );
and ( n27737 , n27730 , n27736 );
nor ( n27738 , n27729 , n27737 );
not ( n27739 , n13225 );
not ( n27740 , n14792 );
or ( n27741 , n27739 , n27740 );
or ( n27742 , n14792 , n13225 );
nand ( n27743 , n27741 , n27742 );
and ( n27744 , n27743 , n14845 );
not ( n27745 , n27743 );
and ( n27746 , n27745 , n14838 );
nor ( n27747 , n27744 , n27746 );
not ( n27748 , n27747 );
nand ( n27749 , n27738 , n27748 );
xor ( n27750 , n27046 , n19200 );
xnor ( n27751 , n27750 , n20089 );
and ( n27752 , n27749 , n27751 );
not ( n27753 , n27749 );
not ( n27754 , n27751 );
and ( n27755 , n27753 , n27754 );
nor ( n27756 , n27752 , n27755 );
not ( n27757 , n27756 );
or ( n27758 , n27723 , n27757 );
or ( n27759 , n27722 , n27756 );
nand ( n27760 , n27758 , n27759 );
not ( n27761 , n13579 );
not ( n27762 , n27761 );
not ( n27763 , n19243 );
or ( n27764 , n27762 , n27763 );
nand ( n27765 , n22765 , n13579 );
nand ( n27766 , n27764 , n27765 );
and ( n27767 , n27766 , n11275 );
not ( n27768 , n27766 );
and ( n27769 , n27768 , n11272 );
nor ( n27770 , n27767 , n27769 );
not ( n27771 , n27770 );
buf ( n27772 , n21440 );
not ( n27773 , n27772 );
not ( n27774 , n27773 );
not ( n27775 , n8046 );
or ( n27776 , n27774 , n27775 );
nand ( n27777 , n8047 , n27772 );
nand ( n27778 , n27776 , n27777 );
not ( n27779 , n27778 );
not ( n27780 , n7993 );
and ( n27781 , n27779 , n27780 );
and ( n27782 , n23384 , n27778 );
nor ( n27783 , n27781 , n27782 );
not ( n27784 , n27783 );
nand ( n27785 , n27771 , n27784 );
not ( n27786 , n27785 );
not ( n27787 , n11561 );
not ( n27788 , n27615 );
or ( n27789 , n27787 , n27788 );
not ( n27790 , n27615 );
nand ( n27791 , n27790 , n11558 );
nand ( n27792 , n27789 , n27791 );
xnor ( n27793 , n27792 , n11503 );
not ( n27794 , n27793 );
not ( n27795 , n27794 );
and ( n27796 , n27786 , n27795 );
and ( n27797 , n27785 , n27794 );
nor ( n27798 , n27796 , n27797 );
xor ( n27799 , n27760 , n27798 );
not ( n27800 , n26593 );
not ( n27801 , n14358 );
not ( n27802 , n13087 );
or ( n27803 , n27801 , n27802 );
not ( n27804 , n14358 );
nand ( n27805 , n27804 , n26602 );
nand ( n27806 , n27803 , n27805 );
not ( n27807 , n27806 );
or ( n27808 , n27800 , n27807 );
or ( n27809 , n27806 , n27419 );
nand ( n27810 , n27808 , n27809 );
not ( n27811 , n13502 );
not ( n27812 , n24913 );
not ( n27813 , n27812 );
not ( n27814 , n22100 );
or ( n27815 , n27813 , n27814 );
nand ( n27816 , n22095 , n24913 );
nand ( n27817 , n27815 , n27816 );
not ( n27818 , n27817 );
or ( n27819 , n27811 , n27818 );
not ( n27820 , n13502 );
not ( n27821 , n27820 );
or ( n27822 , n27817 , n27821 );
nand ( n27823 , n27819 , n27822 );
not ( n27824 , n27823 );
nand ( n27825 , n27810 , n27824 );
not ( n27826 , n27825 );
not ( n27827 , n20320 );
not ( n27828 , n9598 );
or ( n27829 , n27827 , n27828 );
or ( n27830 , n9598 , n20320 );
nand ( n27831 , n27829 , n27830 );
and ( n27832 , n27831 , n9650 );
not ( n27833 , n27831 );
and ( n27834 , n27833 , n9644 );
nor ( n27835 , n27832 , n27834 );
not ( n27836 , n27835 );
not ( n27837 , n27836 );
and ( n27838 , n27826 , n27837 );
and ( n27839 , n27825 , n27836 );
nor ( n27840 , n27838 , n27839 );
not ( n27841 , n27840 );
not ( n27842 , n27841 );
not ( n27843 , n8992 );
and ( n27844 , n8262 , n8258 );
not ( n27845 , n8262 );
not ( n27846 , n8257 );
and ( n27847 , n27845 , n27846 );
nor ( n27848 , n27844 , n27847 );
nor ( n27849 , n17345 , n27848 );
not ( n27850 , n27849 );
nand ( n27851 , n17345 , n27848 );
nand ( n27852 , n27850 , n27851 );
not ( n27853 , n27852 );
or ( n27854 , n27843 , n27853 );
or ( n27855 , n27852 , n7270 );
nand ( n27856 , n27854 , n27855 );
not ( n27857 , n27856 );
not ( n27858 , n7921 );
not ( n27859 , n19773 );
or ( n27860 , n27858 , n27859 );
not ( n27861 , n7921 );
nand ( n27862 , n27861 , n10270 );
nand ( n27863 , n27860 , n27862 );
and ( n27864 , n27863 , n10314 );
not ( n27865 , n27863 );
and ( n27866 , n27865 , n10311 );
nor ( n27867 , n27864 , n27866 );
nand ( n27868 , n27857 , n27867 );
not ( n27869 , n14527 );
not ( n27870 , n18028 );
or ( n27871 , n27869 , n27870 );
not ( n27872 , n14527 );
nand ( n27873 , n27872 , n12010 );
nand ( n27874 , n27871 , n27873 );
not ( n27875 , n27874 );
not ( n27876 , n12037 );
and ( n27877 , n27875 , n27876 );
and ( n27878 , n12037 , n27874 );
nor ( n27879 , n27877 , n27878 );
and ( n27880 , n27868 , n27879 );
not ( n27881 , n27868 );
not ( n27882 , n27879 );
and ( n27883 , n27881 , n27882 );
nor ( n27884 , n27880 , n27883 );
not ( n27885 , n27884 );
not ( n27886 , n27885 );
or ( n27887 , n27842 , n27886 );
nand ( n27888 , n27884 , n27840 );
nand ( n27889 , n27887 , n27888 );
and ( n27890 , n27799 , n27889 );
not ( n27891 , n27799 );
not ( n27892 , n27889 );
and ( n27893 , n27891 , n27892 );
nor ( n27894 , n27890 , n27893 );
buf ( n27895 , n27894 );
not ( n27896 , n27895 );
buf ( n27897 , n10337 );
not ( n27898 , n27897 );
not ( n27899 , n10346 );
not ( n27900 , n16158 );
and ( n27901 , n27899 , n27900 );
and ( n27902 , n10346 , n16158 );
nor ( n27903 , n27901 , n27902 );
not ( n27904 , n27903 );
and ( n27905 , n27898 , n27904 );
and ( n27906 , n27897 , n27903 );
nor ( n27907 , n27905 , n27906 );
not ( n27908 , n19471 );
and ( n27909 , n27907 , n27908 );
not ( n27910 , n27907 );
and ( n27911 , n27910 , n19471 );
nor ( n27912 , n27909 , n27911 );
not ( n27913 , n27912 );
not ( n27914 , n27913 );
buf ( n27915 , n9418 );
not ( n27916 , n27915 );
not ( n27917 , n8785 );
or ( n27918 , n27916 , n27917 );
or ( n27919 , n8785 , n27915 );
nand ( n27920 , n27918 , n27919 );
xor ( n27921 , n27920 , n8841 );
not ( n27922 , n14155 );
not ( n27923 , n26936 );
or ( n27924 , n27922 , n27923 );
or ( n27925 , n26936 , n14155 );
nand ( n27926 , n27924 , n27925 );
and ( n27927 , n27926 , n15521 );
not ( n27928 , n27926 );
and ( n27929 , n27928 , n15518 );
nor ( n27930 , n27927 , n27929 );
not ( n27931 , n27930 );
nand ( n27932 , n27921 , n27931 );
not ( n27933 , n27932 );
or ( n27934 , n27914 , n27933 );
nand ( n27935 , n27921 , n27931 );
or ( n27936 , n27935 , n27913 );
nand ( n27937 , n27934 , n27936 );
not ( n27938 , n27937 );
not ( n27939 , n18930 );
not ( n27940 , n13457 );
or ( n27941 , n27939 , n27940 );
or ( n27942 , n13457 , n18930 );
nand ( n27943 , n27941 , n27942 );
and ( n27944 , n27943 , n20866 );
not ( n27945 , n27943 );
buf ( n27946 , n13838 );
and ( n27947 , n27945 , n27946 );
nor ( n27948 , n27944 , n27947 );
not ( n27949 , n27948 );
not ( n27950 , n13239 );
not ( n27951 , n14797 );
or ( n27952 , n27950 , n27951 );
not ( n27953 , n14792 );
or ( n27954 , n27953 , n13239 );
nand ( n27955 , n27952 , n27954 );
and ( n27956 , n27955 , n14847 );
not ( n27957 , n27955 );
and ( n27958 , n27957 , n14840 );
nor ( n27959 , n27956 , n27958 );
nand ( n27960 , n27949 , n27959 );
not ( n27961 , n7381 );
not ( n27962 , n18260 );
or ( n27963 , n27961 , n27962 );
or ( n27964 , n18260 , n7381 );
nand ( n27965 , n27963 , n27964 );
and ( n27966 , n27965 , n22046 );
not ( n27967 , n27965 );
not ( n27968 , n22842 );
and ( n27969 , n27967 , n27968 );
nor ( n27970 , n27966 , n27969 );
not ( n27971 , n27970 );
and ( n27972 , n27960 , n27971 );
not ( n27973 , n27960 );
and ( n27974 , n27973 , n27970 );
nor ( n27975 , n27972 , n27974 );
not ( n27976 , n27975 );
nand ( n27977 , n27912 , n27930 );
not ( n27978 , n27977 );
not ( n27979 , n20651 );
not ( n27980 , n23122 );
or ( n27981 , n27979 , n27980 );
nand ( n27982 , n23121 , n20647 );
nand ( n27983 , n27981 , n27982 );
not ( n27984 , n27983 );
not ( n27985 , n23109 );
not ( n27986 , n27985 );
or ( n27987 , n27984 , n27986 );
or ( n27988 , n27985 , n27983 );
nand ( n27989 , n27987 , n27988 );
and ( n27990 , n27989 , n20410 );
not ( n27991 , n27989 );
not ( n27992 , n24001 );
not ( n27993 , n27992 );
and ( n27994 , n27991 , n27993 );
nor ( n27995 , n27990 , n27994 );
not ( n27996 , n27995 );
and ( n27997 , n27978 , n27996 );
and ( n27998 , n27977 , n27995 );
nor ( n27999 , n27997 , n27998 );
not ( n28000 , n27999 );
and ( n28001 , n27976 , n28000 );
and ( n28002 , n27975 , n27999 );
nor ( n28003 , n28001 , n28002 );
not ( n28004 , n28003 );
not ( n28005 , n28004 );
not ( n28006 , n11018 );
not ( n28007 , n9731 );
or ( n28008 , n28006 , n28007 );
or ( n28009 , n9731 , n11018 );
nand ( n28010 , n28008 , n28009 );
and ( n28011 , n28010 , n25248 );
not ( n28012 , n28010 );
and ( n28013 , n28012 , n25258 );
nor ( n28014 , n28011 , n28013 );
not ( n28015 , n24904 );
not ( n28016 , n22100 );
or ( n28017 , n28015 , n28016 );
or ( n28018 , n22096 , n24904 );
nand ( n28019 , n28017 , n28018 );
not ( n28020 , n28019 );
not ( n28021 , n27821 );
and ( n28022 , n28020 , n28021 );
and ( n28023 , n28019 , n27821 );
nor ( n28024 , n28022 , n28023 );
not ( n28025 , n28024 );
nand ( n28026 , n28014 , n28025 );
not ( n28027 , n12823 );
not ( n28028 , n9322 );
or ( n28029 , n28027 , n28028 );
or ( n28030 , n9322 , n12823 );
nand ( n28031 , n28029 , n28030 );
buf ( n28032 , n9374 );
and ( n28033 , n28031 , n28032 );
not ( n28034 , n28031 );
not ( n28035 , n28032 );
and ( n28036 , n28034 , n28035 );
nor ( n28037 , n28033 , n28036 );
and ( n28038 , n28026 , n28037 );
not ( n28039 , n28026 );
not ( n28040 , n28037 );
and ( n28041 , n28039 , n28040 );
nor ( n28042 , n28038 , n28041 );
not ( n28043 , n28042 );
not ( n28044 , n28043 );
or ( n28045 , n28005 , n28044 );
nand ( n28046 , n28003 , n28042 );
nand ( n28047 , n28045 , n28046 );
not ( n28048 , n21429 );
not ( n28049 , n18166 );
or ( n28050 , n28048 , n28049 );
or ( n28051 , n18166 , n21429 );
nand ( n28052 , n28050 , n28051 );
not ( n28053 , n28052 );
not ( n28054 , n7993 );
and ( n28055 , n28053 , n28054 );
and ( n28056 , n28052 , n23384 );
nor ( n28057 , n28055 , n28056 );
not ( n28058 , n28057 );
not ( n28059 , n16071 );
not ( n28060 , n18015 );
or ( n28061 , n28059 , n28060 );
or ( n28062 , n18015 , n16071 );
nand ( n28063 , n28061 , n28062 );
and ( n28064 , n28063 , n26425 );
not ( n28065 , n28063 );
and ( n28066 , n28065 , n20232 );
nor ( n28067 , n28064 , n28066 );
nand ( n28068 , n28058 , n28067 );
not ( n28069 , n28068 );
not ( n28070 , n15655 );
not ( n28071 , n26262 );
or ( n28072 , n28070 , n28071 );
nand ( n28073 , n26265 , n15651 );
nand ( n28074 , n28072 , n28073 );
and ( n28075 , n28074 , n26270 );
not ( n28076 , n28074 );
and ( n28077 , n28076 , n26269 );
nor ( n28078 , n28075 , n28077 );
not ( n28079 , n28078 );
and ( n28080 , n28069 , n28079 );
and ( n28081 , n28068 , n28078 );
nor ( n28082 , n28080 , n28081 );
not ( n28083 , n28082 );
xor ( n28084 , n13880 , n17546 );
buf ( n28085 , n19689 );
xnor ( n28086 , n28084 , n28085 );
not ( n28087 , n28086 );
not ( n28088 , n14383 );
not ( n28089 , n26593 );
or ( n28090 , n28088 , n28089 );
or ( n28091 , n26593 , n14383 );
nand ( n28092 , n28090 , n28091 );
and ( n28093 , n28092 , n26708 );
not ( n28094 , n28092 );
and ( n28095 , n28094 , n26712 );
nor ( n28096 , n28093 , n28095 );
nand ( n28097 , n28087 , n28096 );
not ( n28098 , n26321 );
not ( n28099 , n6854 );
not ( n28100 , n14447 );
or ( n28101 , n28099 , n28100 );
or ( n28102 , n14449 , n6854 );
nand ( n28103 , n28101 , n28102 );
not ( n28104 , n28103 );
or ( n28105 , n28098 , n28104 );
or ( n28106 , n28103 , n26321 );
nand ( n28107 , n28105 , n28106 );
not ( n28108 , n28107 );
and ( n28109 , n28097 , n28108 );
not ( n28110 , n28097 );
and ( n28111 , n28110 , n28107 );
nor ( n28112 , n28109 , n28111 );
not ( n28113 , n28112 );
or ( n28114 , n28083 , n28113 );
not ( n28115 , n28082 );
not ( n28116 , n28112 );
nand ( n28117 , n28115 , n28116 );
nand ( n28118 , n28114 , n28117 );
and ( n28119 , n28047 , n28118 );
not ( n28120 , n28047 );
not ( n28121 , n28118 );
and ( n28122 , n28120 , n28121 );
nor ( n28123 , n28119 , n28122 );
not ( n28124 , n28123 );
not ( n28125 , n28124 );
or ( n28126 , n27938 , n28125 );
not ( n28127 , n27937 );
and ( n28128 , n28047 , n28118 );
not ( n28129 , n28047 );
and ( n28130 , n28129 , n28121 );
nor ( n28131 , n28128 , n28130 );
nand ( n28132 , n28127 , n28131 );
nand ( n28133 , n28126 , n28132 );
not ( n28134 , n28133 );
or ( n28135 , n27896 , n28134 );
or ( n28136 , n28133 , n27895 );
nand ( n28137 , n28135 , n28136 );
not ( n28138 , n28137 );
nand ( n28139 , n27685 , n28138 );
or ( n28140 , n27661 , n28139 );
not ( n28141 , n27685 );
not ( n28142 , n27659 );
or ( n28143 , n28141 , n28142 );
buf ( n28144 , n15324 );
nor ( n28145 , n28138 , n28144 );
nand ( n28146 , n28143 , n28145 );
buf ( n28147 , n13353 );
nand ( n28148 , n28147 , n7566 );
nand ( n28149 , n28140 , n28146 , n28148 );
buf ( n28150 , n28149 );
buf ( n28151 , n28150 );
endmodule
|
module main(H0,H1,H2,H3,H4,H5,H6,H7,SW,KEY,LED,sysclk);
input wire [3:0]KEY;
input wire [17:0]SW;
input wire sysclk;
output wire [6:0]H0;
output wire [6:0]H1;
output wire [6:0]H2;
output wire [6:0]H3;
output wire [6:0]H4;
output wire [6:0]H5;
output wire [6:0]H6;
output wire [6:0]H7;
output wire [17:0]LED;
//CANCEL USELESS PINS
assign H0=7'b1111111;
assign H1=7'b1111111;
assign H2=7'b1111111;
assign H3=7'b1111111;
assign H4=7'b1111111;
assign H5=7'b1111111;
assign H6=7'b1111111;
assign H7=7'b1111111;
reg [1:0]model;
reg [1:0]Mode;
always@(posedge KEY[0]) model<=model+1;
always@(posedge KEY[1]) Mode<=model;
wire Reset; assign Reset=KEY[2];
wire [1:0]State;
wire DataWrong;
wire DataOut;
wire DataOutEn;
assign LED[1:0]=model;
assign LED[2]=DataWrong;
assign LED[3]=DataOutEn;
assign LED[5:4]=State;
reg led;
assign LED[17]=led;
initial led<=0;
always@(posedge inter) led<=~led;
reg led2;
assign LED[16]=led2;
initial led2<=0;
always@(posedge S) led2<=~led2;
reg led3;
assign LED[15]=led3;
initial led3<=0;
always@(posedge DataIn) led3<=~led3;
//DEFINE INPUTS
//LINK OUTPUT
//PROGRAM START
FrameTrans(Reset,sysclk,Mode,Clock,DataIn);
FramesyncFSM(Clock,Reset,DataIn,DataOut,DataOutEn,State,inter,S);
FrameDataCheck(Reset,
Clock,
DataOut,
DataOutEn,
DataWrong);
//OUTPUTDISPLAY
endmodule
|
// Accellera Standard V2.3 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2008. All rights reserved.
`ifdef OVL_ASSERT_ON
wire xzcheck_enable;
`ifdef OVL_XCHECK_OFF
assign xzcheck_enable = 1'b0;
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
assign xzcheck_enable = 1'b0;
`else
assign xzcheck_enable = 1'b1;
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
generate
case (property_type)
`OVL_ASSERT_2STATE,
`OVL_ASSERT: begin: assert_checks
assert_even_parity_assert #(
.width(width))
assert_even_parity_assert (
.clk(clk),
.reset_n(`OVL_RESET_SIGNAL),
.test_expr(test_expr),
.xzcheck_enable(xzcheck_enable));
end
`OVL_ASSUME_2STATE,
`OVL_ASSUME: begin: assume_checks
assert_even_parity_assume #(
.width(width))
assert_even_parity_assume (
.clk(clk),
.reset_n(`OVL_RESET_SIGNAL),
.test_expr(test_expr),
.xzcheck_enable(xzcheck_enable));
end
`OVL_IGNORE: begin: ovl_ignore
//do nothing
end
default: initial ovl_error_t(`OVL_FIRE_2STATE,"");
endcase
endgenerate
`endif
`ifdef OVL_COVER_ON
generate
if (coverage_level != `OVL_COVER_NONE)
begin: cover_checks
assert_even_parity_cover #(
.width(width),
.OVL_COVER_SANITY_ON(OVL_COVER_SANITY_ON))
assert_even_parity_cover (
.clk(clk),
.reset_n(`OVL_RESET_SIGNAL),
.test_expr(test_expr));
end
endgenerate
`endif
`endmodule //Required to pair up with already used "`module" in file assert_even_parity.vlib
//Module to be replicated for assert checks
//This module is bound to the PSL vunits with assert checks
module assert_even_parity_assert (clk, reset_n, test_expr, xzcheck_enable);
parameter width = 1;
input clk, reset_n;
input [width-1:0] test_expr;
input xzcheck_enable;
endmodule
//Module to be replicated for assume checks
//This module is bound to a PSL vunits with assume checks
module assert_even_parity_assume (clk, reset_n, test_expr, xzcheck_enable);
parameter width = 1;
input clk, reset_n;
input [width-1:0] test_expr;
input xzcheck_enable;
endmodule
//Module to be replicated for cover properties
//This module is bound to a PSL vunit with cover properties
module assert_even_parity_cover (clk, reset_n, test_expr);
parameter width = 1;
parameter OVL_COVER_SANITY_ON = 1;
input clk, reset_n;
input [width-1:0] test_expr;
endmodule
|
module dds_gen(clk, key1, key2, da_clk, da_db);
input wire clk;
input wire key1;
input wire key2;
output wire da_clk;
output wire [7:0] da_db;
wire clk100M;
pll100M gen_100MHz(.inclk0(clk),
.c0(clk100M));
reg [31:0] dds_accum; initial dds_accum <= 32'd0;
reg [31:0] dds_adder; initial dds_adder <= 32'd179272; // 440 Hz
reg [31:0] delay_cnt; initial delay_cnt <= 32'd0;
//assign clk100M = clk;
//трех битный буфер
reg [2:0] gate_buff1;
reg [2:0] gate_buff2;
always @ (posedge clk100M) begin
gate_buff1 <= {gate_buff1[1:0],~key1};
gate_buff2 <= {gate_buff2[1:0],~key2};
end
//буфферизированное значение
assign GATE1_D = (gate_buff1 == 3'b111);
assign GATE2_D = (gate_buff2 == 3'b111);
always @(posedge clk100M) begin
dds_accum <= dds_accum + dds_adder;
delay_cnt <= delay_cnt + 1'b1;
if(delay_cnt==32'd0) begin
delay_cnt <= 32'd1000000;
dds_adder <= (GATE1_D) ? dds_adder + 32'd100 :
(GATE2_D) ? dds_adder - 32'd100 : dds_adder;
end else begin
delay_cnt <= delay_cnt - 1'b1;
end
end
assign da_db = dds_accum[31:31-7]; //high bits of dds accum
assign da_clk = clk100M;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A2111OI_FUNCTIONAL_V
`define SKY130_FD_SC_LP__A2111OI_FUNCTIONAL_V
/**
* a2111oi: 2-input AND into first input of 4-input NOR.
*
* Y = !((A1 & A2) | B1 | C1 | D1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__a2111oi (
Y ,
A1,
A2,
B1,
C1,
D1
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Local signals
wire and0_out ;
wire nor0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out_Y, B1, C1, D1, and0_out);
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__A2111OI_FUNCTIONAL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__AND3_2_V
`define SKY130_FD_SC_HS__AND3_2_V
/**
* and3: 3-input AND.
*
* Verilog wrapper for and3 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__and3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__and3_2 (
X ,
A ,
B ,
C ,
VPWR,
VGND
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
sky130_fd_sc_hs__and3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__and3_2 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__and3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__AND3_2_V
|
// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_controllerHdl.v
// Created: 2014-09-08 14:12:04
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: controllerHdl_controllerHdl
// Source Path: controllerHdl
// Hierarchy Level: 1
//
// Simulink model description for controllerHdl:
//
// Controller Algorithm for Permanent Magnet Synchronous Machine
//
// Specifies controller software component for Permanent Magnet Synchronous Machine (PMSM) using Field-Oriented Control.
// The sensors bus/structure contains values returned by the Analog to Digital Converter (ADC) and quadrature encoder peripherals.
// The controller outputs compare values used by the Pulse Width Modulators (PWMs) to generate the phase voltages.
//
// Simulink subsystem description for controllerHdl:
//
// Controller Algorithm for Permanent Magnet Synchronous Machine
//
// Specifies controller software component for Permanent Magnet Synchronous Machine (PMSM) using Field-Oriented Control.
// The sensors bus/structure contains values returned by the Analog to Digital Converter (ADC) and quadrature encoder peripherals.
// The controller outputs compare values used by the Pulse Width Modulators (PWMs) to generate the phase voltages.
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module controllerHdl_controllerHdl
(
CLK_IN,
reset,
enb_1_2000_0,
adc_current_0,
adc_current_1,
encoder_valid,
encoder_count,
controller_mode,
command,
param_velocity_p_gain,
param_velocity_i_gain,
param_current_p_gain,
param_current_i_gain,
param_open_loop_bias,
param_open_loop_scalar,
param_encoder_zero_offset,
pwm_compare_0,
pwm_compare_1,
pwm_compare_2,
phase_voltages_0,
phase_voltages_1,
phase_voltages_2,
phase_currents_0,
phase_currents_1,
rotor_position,
electrical_position,
rotor_velocity,
dq_currents_0,
dq_currents_1,
electrical_position_err_reg
);
input CLK_IN;
input reset;
input enb_1_2000_0;
input signed [17:0] adc_current_0; // sfix18_En17
input signed [17:0] adc_current_1; // sfix18_En17
input encoder_valid;
input [15:0] encoder_count; // uint16
input [1:0] controller_mode; // ufix2
input signed [17:0] command; // sfix18_En8
input signed [17:0] param_velocity_p_gain; // sfix18_En16
input signed [17:0] param_velocity_i_gain; // sfix18_En15
input signed [17:0] param_current_p_gain; // sfix18_En10
input signed [17:0] param_current_i_gain; // sfix18_En2
input signed [17:0] param_open_loop_bias; // sfix18_En14
input signed [17:0] param_open_loop_scalar; // sfix18_En16
input signed [17:0] param_encoder_zero_offset; // sfix18_En14
output [15:0] pwm_compare_0; // uint16
output [15:0] pwm_compare_1; // uint16
output [15:0] pwm_compare_2; // uint16
output signed [19:0] phase_voltages_0; // sfix20_En12
output signed [19:0] phase_voltages_1; // sfix20_En12
output signed [19:0] phase_voltages_2; // sfix20_En12
output signed [17:0] phase_currents_0; // sfix18_En15
output signed [17:0] phase_currents_1; // sfix18_En15
output signed [17:0] rotor_position; // sfix18_En14
output signed [17:0] electrical_position; // sfix18_En14
output signed [17:0] rotor_velocity; // sfix18_En8
output signed [17:0] dq_currents_0; // sfix18_En15
output signed [17:0] dq_currents_1; // sfix18_En15
output signed [18:0] electrical_position_err_reg; // sfix19_En14
wire Encoder_To_Position_And_Velocity_out1;
wire signed [17:0] Encoder_To_Position_And_Velocity_out2; // sfix18_En14
wire signed [17:0] Encoder_To_Position_And_Velocity_out3; // sfix18_En14
wire signed [17:0] Encoder_To_Position_And_Velocity_out4; // sfix18_En8
wire signed [17:0] phase_currents_0_1; // sfix18_En15
wire signed [17:0] phase_currents_1_1; // sfix18_En15
wire signed [17:0] phase_currents [0:1]; // sfix18_En15 [2]
wire signed [19:0] Field_Oriented_Control_out1_0; // sfix20_En12
wire signed [19:0] Field_Oriented_Control_out1_1; // sfix20_En12
wire signed [19:0] Field_Oriented_Control_out1_2; // sfix20_En12
wire signed [17:0] Field_Oriented_Control_out2_0; // sfix18_En15
wire signed [17:0] Field_Oriented_Control_out2_1; // sfix18_En15
wire signed [17:0] Field_Oriented_Control_out3; // sfix18_En14
wire [15:0] pwm_compare_0_1; // uint16
wire [15:0] pwm_compare_1_1; // uint16
wire [15:0] pwm_compare_2_1; // uint16
wire [15:0] pwm_compare [0:2]; // uint16 [3]
wire signed [18:0] Add_sub_cast; // sfix19_En14
wire signed [18:0] Add_sub_cast_1; // sfix19_En14
wire signed [18:0] Add_out1; // sfix19_En14
wire signed [18:0] MATLAB_Function_out1; // sfix19_En14
// Controller HDL
//
// Copyright 2013 The MathWorks, Inc.
// <Root>/Encoder_To_Position_And_Velocity
controllerHdl_Encoder_To_Position_And_Velocity u_Encoder_To_Position_And_Velocity (.CLK_IN(CLK_IN),
.reset(reset),
.enb_1_2000_0(enb_1_2000_0),
.encoder_valid(encoder_valid),
.encoder_counter(encoder_count), // uint16
.param_zero_offset(param_encoder_zero_offset), // sfix18_En14
.position_valid(Encoder_To_Position_And_Velocity_out1),
.rotor_position(Encoder_To_Position_And_Velocity_out2), // sfix18_En14
.electrical_position(Encoder_To_Position_And_Velocity_out3), // sfix18_En14
.rotor_velocity(Encoder_To_Position_And_Velocity_out4) // sfix18_En8
);
// <Root>/ADC_Peripheral_To_Phase_Current
controllerHdl_ADC_Peripheral_To_Phase_Current u_ADC_Peripheral_To_Phase_Current (.adc_0(adc_current_0), // sfix18_En17
.adc_1(adc_current_1), // sfix18_En17
.phase_currents_0(phase_currents_0_1), // sfix18_En15
.phase_currents_1(phase_currents_1_1) // sfix18_En15
);
assign phase_currents[0] = phase_currents_0_1;
assign phase_currents[1] = phase_currents_1_1;
// <Root>/Field_Oriented_Control
controllerHdl_Field_Oriented_Control u_Field_Oriented_Control (.CLK_IN(CLK_IN),
.reset(reset),
.enb_1_2000_0(enb_1_2000_0),
.controller_mode(controller_mode), // ufix2
.command(command), // sfix18_En8
.electrical_postion(Encoder_To_Position_And_Velocity_out3), // sfix18_En14
.rotor_velocity(Encoder_To_Position_And_Velocity_out4), // sfix18_En8
.phase_currents_0(phase_currents[0]), // sfix18_En15
.phase_currents_1(phase_currents[1]), // sfix18_En15
.param_velocity_p_gain(param_velocity_p_gain), // sfix18_En16
.param_velocity_i_gain(param_velocity_i_gain), // sfix18_En15
.param_current_p_gain(param_current_p_gain), // sfix18_En10
.param_current_i_gain(param_current_i_gain), // sfix18_En2
.param_open_loop_bias(param_open_loop_bias), // sfix18_En14
.param_open_loop_scalar(param_open_loop_scalar), // sfix18_En16
.phase_voltages_0(Field_Oriented_Control_out1_0), // sfix20_En12
.phase_voltages_1(Field_Oriented_Control_out1_1), // sfix20_En12
.phase_voltages_2(Field_Oriented_Control_out1_2), // sfix20_En12
.dq_current_0(Field_Oriented_Control_out2_0), // sfix18_En15
.dq_current_1(Field_Oriented_Control_out2_1), // sfix18_En15
.electrical_position_ol(Field_Oriented_Control_out3) // sfix18_En14
);
// <Root>/Phase_Voltages_To_Compare_Values
controllerHdl_Phase_Voltages_To_Compare_Values u_Phase_Voltages_To_Compare_Values (.V_0(Field_Oriented_Control_out1_0), // sfix20_En12
.V_1(Field_Oriented_Control_out1_1), // sfix20_En12
.V_2(Field_Oriented_Control_out1_2), // sfix20_En12
.C_0(pwm_compare_0_1), // uint16
.C_1(pwm_compare_1_1), // uint16
.C_2(pwm_compare_2_1) // uint16
);
assign pwm_compare[0] = pwm_compare_0_1;
assign pwm_compare[1] = pwm_compare_1_1;
assign pwm_compare[2] = pwm_compare_2_1;
assign pwm_compare_0 = pwm_compare[0];
assign pwm_compare_1 = pwm_compare[1];
assign pwm_compare_2 = pwm_compare[2];
assign phase_voltages_0 = Field_Oriented_Control_out1_0;
assign phase_voltages_1 = Field_Oriented_Control_out1_1;
assign phase_voltages_2 = Field_Oriented_Control_out1_2;
assign phase_currents_0 = phase_currents[0];
assign phase_currents_1 = phase_currents[1];
assign rotor_position = Encoder_To_Position_And_Velocity_out2;
assign electrical_position = Encoder_To_Position_And_Velocity_out3;
assign rotor_velocity = Encoder_To_Position_And_Velocity_out4;
assign dq_currents_0 = Field_Oriented_Control_out2_0;
assign dq_currents_1 = Field_Oriented_Control_out2_1;
// <Root>/Add
assign Add_sub_cast = Field_Oriented_Control_out3;
assign Add_sub_cast_1 = Encoder_To_Position_And_Velocity_out3;
assign Add_out1 = Add_sub_cast - Add_sub_cast_1;
// <Root>/MATLAB Function
controllerHdl_MATLAB_Function_block3 u_MATLAB_Function (.CLK_IN(CLK_IN),
.reset(reset),
.enb_1_2000_0(enb_1_2000_0),
.u(Add_out1), // sfix19_En14
.y(MATLAB_Function_out1) // sfix19_En14
);
assign electrical_position_err_reg = MATLAB_Function_out1;
endmodule // controllerHdl_controllerHdl
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__XOR3_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__XOR3_PP_BLACKBOX_V
/**
* xor3: 3-input exclusive OR.
*
* X = A ^ B ^ C
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__xor3 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__XOR3_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__CLKINVLP_PP_SYMBOL_V
`define SKY130_FD_SC_HDLL__CLKINVLP_PP_SYMBOL_V
/**
* clkinvlp: Lower power Clock tree inverter.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__clkinvlp (
//# {{data|Data Signals}}
input A ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__CLKINVLP_PP_SYMBOL_V
|
/****************************************************************************************
*
* File Name: MT48LC8M16A2.V
* Version: 0.0f
* Date: July 8th, 1999
* Model: BUS Functional
* Simulator: Model Technology (PC version 5.2e PE)
*
* Dependencies: None
*
* Author: Son P. Huynh
* Email: [email protected]
* Phone: (208) 368-3825
* Company: Micron Technology, Inc.
* Model: MT48LC8M16A2 (2Meg x 16 x 4 Banks)
*
* Description: Micron 128Mb SDRAM Verilog model
*
* Limitation: - Doesn't check for 4096 cycle refresh
*
* Note: - Set simulator resolution to "ps" accuracy
* - Set Debug = 0 to disable $display messages
*
* Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY
* WHATSOEVER AND MICRON SPECIFICALLY DISCLAIMS ANY
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
* A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
*
* Copyright � 1998 Micron Semiconductor Products, Inc.
* All rights researved
*
* Rev Author Phone Date Changes
* ---- ---------------------------- ---------- ---------------------------------------
* 0.0f Son Huynh 208-368-3825 07/08/1999 - Fix tWR = 1 Clk + 7.5 ns (Auto)
* Micron Technology Inc. - Fix tWR = 15 ns (Manual)
* - Fix tRP (Autoprecharge to AutoRefresh)
*
* 0.0a Son Huynh 208-368-3825 05/13/1998 - First Release (from 64Mb rev 0.0e)
* Micron Technology Inc.
****************************************************************************************/
`timescale 1ns / 100ps
module mt48lc8m16a2 (Dq, Addr, Ba, Clk, Cke, Cs_n, Ras_n, Cas_n, We_n, Dqm);
parameter addr_bits = 12;
parameter data_bits = 16;
parameter col_bits = 9;
parameter mem_sizes = 2097151; // 2 Meg
inout [data_bits - 1 : 0] Dq;
input [addr_bits - 1 : 0] Addr;
input [1 : 0] Ba;
input Clk;
input Cke;
input Cs_n;
input Ras_n;
input Cas_n;
input We_n;
input [1 : 0] Dqm;
reg [data_bits - 1 : 0] Bank0 [0 : mem_sizes];
reg [data_bits - 1 : 0] Bank1 [0 : mem_sizes];
reg [data_bits - 1 : 0] Bank2 [0 : mem_sizes];
reg [data_bits - 1 : 0] Bank3 [0 : mem_sizes];
reg [1 : 0] Bank_addr [0 : 3]; // Bank Address Pipeline
reg [col_bits - 1 : 0] Col_addr [0 : 3]; // Column Address Pipeline
reg [3 : 0] Command [0 : 3]; // Command Operation Pipeline
reg [1 : 0] Dqm_reg0, Dqm_reg1; // DQM Operation Pipeline
reg [addr_bits - 1 : 0] B0_row_addr, B1_row_addr, B2_row_addr, B3_row_addr;
reg [addr_bits - 1 : 0] Mode_reg;
reg [data_bits - 1 : 0] Dq_reg, Dq_dqm;
reg [col_bits - 1 : 0] Col_temp, Burst_counter;
reg Act_b0, Act_b1, Act_b2, Act_b3; // Bank Activate
reg Pc_b0, Pc_b1, Pc_b2, Pc_b3; // Bank Precharge
reg [1 : 0] Bank_precharge [0 : 3]; // Precharge Command
reg A10_precharge [0 : 3]; // Addr[10] = 1 (All banks)
reg Auto_precharge [0 : 3]; // RW AutoPrecharge (Bank)
reg Read_precharge [0 : 3]; // R AutoPrecharge
reg Write_precharge [0 : 3]; // W AutoPrecharge
integer Count_precharge [0 : 3]; // RW AutoPrecharge (Counter)
reg RW_interrupt_read [0 : 3]; // RW Interrupt Read with Auto Precharge
reg RW_interrupt_write [0 : 3]; // RW Interrupt Write with Auto Precharge
reg Data_in_enable;
reg Data_out_enable;
reg [1 : 0] Bank, Previous_bank;
reg [addr_bits - 1 : 0] Row;
reg [col_bits - 1 : 0] Col, Col_brst;
// Internal system clock
reg CkeZ, Sys_clk;
// Commands Decode
wire Active_enable = ~Cs_n & ~Ras_n & Cas_n & We_n;
wire Aref_enable = ~Cs_n & ~Ras_n & ~Cas_n & We_n;
wire Burst_term = ~Cs_n & Ras_n & Cas_n & ~We_n;
wire Mode_reg_enable = ~Cs_n & ~Ras_n & ~Cas_n & ~We_n;
wire Prech_enable = ~Cs_n & ~Ras_n & Cas_n & ~We_n;
wire Read_enable = ~Cs_n & Ras_n & ~Cas_n & We_n;
wire Write_enable = ~Cs_n & Ras_n & ~Cas_n & ~We_n;
// Burst Length Decode
wire Burst_length_1 = ~Mode_reg[2] & ~Mode_reg[1] & ~Mode_reg[0];
wire Burst_length_2 = ~Mode_reg[2] & ~Mode_reg[1] & Mode_reg[0];
wire Burst_length_4 = ~Mode_reg[2] & Mode_reg[1] & ~Mode_reg[0];
wire Burst_length_8 = ~Mode_reg[2] & Mode_reg[1] & Mode_reg[0];
// CAS Latency Decode
wire Cas_latency_2 = ~Mode_reg[6] & Mode_reg[5] & ~Mode_reg[4];
wire Cas_latency_3 = ~Mode_reg[6] & Mode_reg[5] & Mode_reg[4];
// Write Burst Mode
wire Write_burst_mode = Mode_reg[9];
wire Debug = 1'b1; // Debug messages : 1 = On
wire Dq_chk = Sys_clk & Data_in_enable; // Check setup/hold time for DQ
assign Dq = Dq_reg; // DQ buffer
// Commands Operation
`define ACT 0
`define NOP 1
`define READ 2
`define READ_A 3
`define WRITE 4
`define WRITE_A 5
`define PRECH 6
`define A_REF 7
`define BST 8
`define LMR 9
// Timing Parameters for -75 (PC133) and CAS Latency = 2
parameter tAC = 6.0;
parameter tHZ = 7.0;
parameter tOH = 2.7;
parameter tMRD = 2.0; // 2 Clk Cycles
parameter tRAS = 44.0;
parameter tRC = 66.0;
parameter tRCD = 20.0;
parameter tRP = 20.0;
parameter tRRD = 15.0;
parameter tWRa = 7.5; // A2 Version - Auto precharge mode only (1 Clk + 7.5 ns)
parameter tWRp = 15.0; // A2 Version - Precharge mode only (15 ns)
// Timing Check variable
integer MRD_chk;
integer WR_counter [0 : 3];
time WR_chk [0 : 3];
time RC_chk, RRD_chk;
time RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3;
time RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3;
time RP_chk0, RP_chk1, RP_chk2, RP_chk3;
initial begin
Dq_reg = {data_bits{1'bz}};
{Data_in_enable, Data_out_enable} = 0;
{Act_b0, Act_b1, Act_b2, Act_b3} = 4'b0000;
{Pc_b0, Pc_b1, Pc_b2, Pc_b3} = 4'b0000;
{WR_chk[0], WR_chk[1], WR_chk[2], WR_chk[3]} = 0;
{WR_counter[0], WR_counter[1], WR_counter[2], WR_counter[3]} = 0;
{RW_interrupt_read[0], RW_interrupt_read[1], RW_interrupt_read[2], RW_interrupt_read[3]} = 0;
{RW_interrupt_write[0], RW_interrupt_write[1], RW_interrupt_write[2], RW_interrupt_write[3]} = 0;
{MRD_chk, RC_chk, RRD_chk} = 0;
{RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3} = 0;
{RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3} = 0;
{RP_chk0, RP_chk1, RP_chk2, RP_chk3} = 0;
$timeformat (-9, 0, " ns", 12);
//$readmemh("bank0.txt", Bank0);
//$readmemh("bank1.txt", Bank1);
//$readmemh("bank2.txt", Bank2);
//$readmemh("bank3.txt", Bank3);
end
// System clock generator
always begin
@ (posedge Clk) begin
Sys_clk = CkeZ;
CkeZ = Cke;
end
@ (negedge Clk) begin
Sys_clk = 1'b0;
end
end
always @ (posedge Sys_clk) begin
// Internal Commamd Pipelined
Command[0] = Command[1];
Command[1] = Command[2];
Command[2] = Command[3];
Command[3] = `NOP;
Col_addr[0] = Col_addr[1];
Col_addr[1] = Col_addr[2];
Col_addr[2] = Col_addr[3];
Col_addr[3] = {col_bits{1'b0}};
Bank_addr[0] = Bank_addr[1];
Bank_addr[1] = Bank_addr[2];
Bank_addr[2] = Bank_addr[3];
Bank_addr[3] = 2'b0;
Bank_precharge[0] = Bank_precharge[1];
Bank_precharge[1] = Bank_precharge[2];
Bank_precharge[2] = Bank_precharge[3];
Bank_precharge[3] = 2'b0;
A10_precharge[0] = A10_precharge[1];
A10_precharge[1] = A10_precharge[2];
A10_precharge[2] = A10_precharge[3];
A10_precharge[3] = 1'b0;
// Dqm pipeline for Read
Dqm_reg0 = Dqm_reg1;
Dqm_reg1 = Dqm;
// Read or Write with Auto Precharge Counter
if (Auto_precharge[0] == 1'b1) begin
Count_precharge[0] = Count_precharge[0] + 1;
end
if (Auto_precharge[1] == 1'b1) begin
Count_precharge[1] = Count_precharge[1] + 1;
end
if (Auto_precharge[2] == 1'b1) begin
Count_precharge[2] = Count_precharge[2] + 1;
end
if (Auto_precharge[3] == 1'b1) begin
Count_precharge[3] = Count_precharge[3] + 1;
end
// tMRD Counter
MRD_chk = MRD_chk + 1;
// tWR Counter for Write
WR_counter[0] = WR_counter[0] + 1;
WR_counter[1] = WR_counter[1] + 1;
WR_counter[2] = WR_counter[2] + 1;
WR_counter[3] = WR_counter[3] + 1;
// Auto Refresh
if (Aref_enable == 1'b1) begin
if (Debug) $display ("at time %t AREF : Auto Refresh", $time);
// Auto Refresh to Auto Refresh
if ($time - RC_chk < tRC) begin
$display ("at time %t ERROR: tRC violation during Auto Refresh", $time);
end
// Precharge to Auto Refresh
if ($time - RP_chk0 < tRP || $time - RP_chk1 < tRP || $time - RP_chk2 < tRP || $time - RP_chk3 < tRP) begin
$display ("at time %t ERROR: tRP violation during Auto Refresh", $time);
end
// Precharge to Refresh
if (Pc_b0 == 1'b0 || Pc_b1 == 1'b0 || Pc_b2 == 1'b0 || Pc_b3 == 1'b0) begin
$display ("at time %t ERROR: All banks must be Precharge before Auto Refresh", $time);
end
// Record Current tRC time
RC_chk = $time;
end
// Load Mode Register
if (Mode_reg_enable == 1'b1) begin
// Decode CAS Latency, Burst Length, Burst Type, and Write Burst Mode
if (Pc_b0 == 1'b1 && Pc_b1 == 1'b1 && Pc_b2 == 1'b1 && Pc_b3 == 1'b1) begin
Mode_reg = Addr;
if (Debug) begin
$display ("at time %t LMR : Load Mode Register", $time);
// CAS Latency
if (Addr[6 : 4] == 3'b010)
$display (" CAS Latency = 2");
else if (Addr[6 : 4] == 3'b011)
$display (" CAS Latency = 3");
else
$display (" CAS Latency = Reserved");
// Burst Length
if (Addr[2 : 0] == 3'b000)
$display (" Burst Length = 1");
else if (Addr[2 : 0] == 3'b001)
$display (" Burst Length = 2");
else if (Addr[2 : 0] == 3'b010)
$display (" Burst Length = 4");
else if (Addr[2 : 0] == 3'b011)
$display (" Burst Length = 8");
else if (Addr[3 : 0] == 4'b0111)
$display (" Burst Length = Full");
else
$display (" Burst Length = Reserved");
// Burst Type
if (Addr[3] == 1'b0)
$display (" Burst Type = Sequential");
else if (Addr[3] == 1'b1)
$display (" Burst Type = Interleaved");
else
$display (" Burst Type = Reserved");
// Write Burst Mode
if (Addr[9] == 1'b0)
$display (" Write Burst Mode = Programmed Burst Length");
else if (Addr[9] == 1'b1)
$display (" Write Burst Mode = Single Location Access");
else
$display (" Write Burst Mode = Reserved");
end
end else begin
$display ("at time %t ERROR: all banks must be Precharge before Load Mode Register", $time);
end
// REF to LMR
if ($time - RC_chk < tRC) begin
$display ("at time %t ERROR: tRC violation during Load Mode Register", $time);
end
// LMR to LMR
if (MRD_chk < tMRD) begin
$display ("at time %t ERROR: tMRD violation during Load Mode Register", $time);
end
MRD_chk = 0;
end
// Active Block (Latch Bank Address and Row Address)
if (Active_enable == 1'b1) begin
if (Ba == 2'b00 && Pc_b0 == 1'b1) begin
{Act_b0, Pc_b0} = 2'b10;
B0_row_addr = Addr [addr_bits - 1 : 0];
RCD_chk0 = $time;
RAS_chk0 = $time;
if (Debug) $display ("at time %t ACT : Bank = 0 Row = %d", $time, Addr);
// Precharge to Activate Bank 0
if ($time - RP_chk0 < tRP) begin
$display ("at time %t ERROR: tRP violation during Activate bank 0", $time);
end
end else if (Ba == 2'b01 && Pc_b1 == 1'b1) begin
{Act_b1, Pc_b1} = 2'b10;
B1_row_addr = Addr [addr_bits - 1 : 0];
RCD_chk1 = $time;
RAS_chk1 = $time;
if (Debug) $display ("at time %t ACT : Bank = 1 Row = %d", $time, Addr);
// Precharge to Activate Bank 1
if ($time - RP_chk1 < tRP) begin
$display ("at time %t ERROR: tRP violation during Activate bank 1", $time);
end
end else if (Ba == 2'b10 && Pc_b2 == 1'b1) begin
{Act_b2, Pc_b2} = 2'b10;
B2_row_addr = Addr [addr_bits - 1 : 0];
RCD_chk2 = $time;
RAS_chk2 = $time;
if (Debug) $display ("at time %t ACT : Bank = 2 Row = %d", $time, Addr);
// Precharge to Activate Bank 2
if ($time - RP_chk2 < tRP) begin
$display ("at time %t ERROR: tRP violation during Activate bank 2", $time);
end
end else if (Ba == 2'b11 && Pc_b3 == 1'b1) begin
{Act_b3, Pc_b3} = 2'b10;
B3_row_addr = Addr [addr_bits - 1 : 0];
RCD_chk3 = $time;
RAS_chk3 = $time;
if (Debug) $display ("at time %t ACT : Bank = 3 Row = %d", $time, Addr);
// Precharge to Activate Bank 3
if ($time - RP_chk3 < tRP) begin
$display ("at time %t ERROR: tRP violation during Activate bank 3", $time);
end
end else if (Ba == 2'b00 && Pc_b0 == 1'b0) begin
$display ("at time %t ERROR: Bank 0 is not Precharged.", $time);
end else if (Ba == 2'b01 && Pc_b1 == 1'b0) begin
$display ("at time %t ERROR: Bank 1 is not Precharged.", $time);
end else if (Ba == 2'b10 && Pc_b2 == 1'b0) begin
$display ("at time %t ERROR: Bank 2 is not Precharged.", $time);
end else if (Ba == 2'b11 && Pc_b3 == 1'b0) begin
$display ("at time %t ERROR: Bank 3 is not Precharged.", $time);
end
// Active Bank A to Active Bank B
if ((Previous_bank != Ba) && ($time - RRD_chk < tRRD)) begin
$display ("at time %t ERROR: tRRD violation during Activate bank = %d", $time, Ba);
end
// Load Mode Register to Active
if (MRD_chk < tMRD ) begin
$display ("at time %t ERROR: tMRD violation during Activate bank = %d", $time, Ba);
end
// Auto Refresh to Activate
if ($time - RC_chk < tRC) begin
$display ("at time %t ERROR: tRC violation during Activate bank = %d", $time, Ba);
end
// Record variables for checking violation
RRD_chk = $time;
Previous_bank = Ba;
end
// Precharge Block
if (Prech_enable == 1'b1) begin
if (Addr[10] == 1'b1) begin
{Pc_b0, Pc_b1, Pc_b2, Pc_b3} = 4'b1111;
{Act_b0, Act_b1, Act_b2, Act_b3} = 4'b0000;
RP_chk0 = $time;
RP_chk1 = $time;
RP_chk2 = $time;
RP_chk3 = $time;
if (Debug) $display ("at time %t PRE : Bank = ALL",$time);
// Activate to Precharge all banks
if (($time - RAS_chk0 < tRAS) || ($time - RAS_chk1 < tRAS) ||
($time - RAS_chk2 < tRAS) || ($time - RAS_chk3 < tRAS)) begin
$display ("at time %t ERROR: tRAS violation during Precharge all bank", $time);
end
// tWR violation check for write
if (($time - WR_chk[0] < tWRp) || ($time - WR_chk[1] < tWRp) ||
($time - WR_chk[2] < tWRp) || ($time - WR_chk[3] < tWRp)) begin
$display ("at time %t ERROR: tWR violation during Precharge all bank", $time);
end
end else if (Addr[10] == 1'b0) begin
if (Ba == 2'b00) begin
{Pc_b0, Act_b0} = 2'b10;
RP_chk0 = $time;
if (Debug) $display ("at time %t PRE : Bank = 0",$time);
// Activate to Precharge Bank 0
if ($time - RAS_chk0 < tRAS) begin
$display ("at time %t ERROR: tRAS violation during Precharge bank 0", $time);
end
end else if (Ba == 2'b01) begin
{Pc_b1, Act_b1} = 2'b10;
RP_chk1 = $time;
if (Debug) $display ("at time %t PRE : Bank = 1",$time);
// Activate to Precharge Bank 1
if ($time - RAS_chk1 < tRAS) begin
$display ("at time %t ERROR: tRAS violation during Precharge bank 1", $time);
end
end else if (Ba == 2'b10) begin
{Pc_b2, Act_b2} = 2'b10;
RP_chk2 = $time;
if (Debug) $display ("at time %t PRE : Bank = 2",$time);
// Activate to Precharge Bank 2
if ($time - RAS_chk2 < tRAS) begin
$display ("at time %t ERROR: tRAS violation during Precharge bank 2", $time);
end
end else if (Ba == 2'b11) begin
{Pc_b3, Act_b3} = 2'b10;
RP_chk3 = $time;
if (Debug) $display ("at time %t PRE : Bank = 3",$time);
// Activate to Precharge Bank 3
if ($time - RAS_chk3 < tRAS) begin
$display ("at time %t ERROR: tRAS violation during Precharge bank 3", $time);
end
end
// tWR violation check for write
if ($time - WR_chk[Ba] < tWRp) begin
$display ("at time %t ERROR: tWR violation during Precharge bank %d", $time, Ba);
end
end
// Terminate a Write Immediately (if same bank or all banks)
if (Data_in_enable == 1'b1 && (Bank == Ba || Addr[10] == 1'b1)) begin
Data_in_enable = 1'b0;
end
// Precharge Command Pipeline for Read
if (Cas_latency_3 == 1'b1) begin
Command[2] = `PRECH;
Bank_precharge[2] = Ba;
A10_precharge[2] = Addr[10];
end else if (Cas_latency_2 == 1'b1) begin
Command[1] = `PRECH;
Bank_precharge[1] = Ba;
A10_precharge[1] = Addr[10];
end
end
// Burst terminate
if (Burst_term == 1'b1) begin
// Terminate a Write Immediately
if (Data_in_enable == 1'b1) begin
Data_in_enable = 1'b0;
end
// Terminate a Read Depend on CAS Latency
if (Cas_latency_3 == 1'b1) begin
Command[2] = `BST;
end else if (Cas_latency_2 == 1'b1) begin
Command[1] = `BST;
end
if (Debug) $display ("at time %t BST : Burst Terminate",$time);
end
// Read, Write, Column Latch
if (Read_enable == 1'b1 || Write_enable == 1'b1) begin
// Check to see if bank is open (ACT)
if ((Ba == 2'b00 && Pc_b0 == 1'b1) || (Ba == 2'b01 && Pc_b1 == 1'b1) ||
(Ba == 2'b10 && Pc_b2 == 1'b1) || (Ba == 2'b11 && Pc_b3 == 1'b1)) begin
$display("at time %t ERROR: Cannot Read or Write - Bank %d is not Activated", $time, Ba);
end
// Activate to Read or Write
if ((Ba == 2'b00) && ($time - RCD_chk0 < tRCD))
$display("at time %t ERROR: tRCD violation during Read or Write to Bank 0", $time);
if ((Ba == 2'b01) && ($time - RCD_chk1 < tRCD))
$display("at time %t ERROR: tRCD violation during Read or Write to Bank 1", $time);
if ((Ba == 2'b10) && ($time - RCD_chk2 < tRCD))
$display("at time %t ERROR: tRCD violation during Read or Write to Bank 2", $time);
if ((Ba == 2'b11) && ($time - RCD_chk3 < tRCD))
$display("at time %t ERROR: tRCD violation during Read or Write to Bank 3", $time);
// Read Command
if (Read_enable == 1'b1) begin
// CAS Latency pipeline
if (Cas_latency_3 == 1'b1) begin
if (Addr[10] == 1'b1) begin
Command[2] = `READ_A;
end else begin
Command[2] = `READ;
end
Col_addr[2] = Addr;
Bank_addr[2] = Ba;
end else if (Cas_latency_2 == 1'b1) begin
if (Addr[10] == 1'b1) begin
Command[1] = `READ_A;
end else begin
Command[1] = `READ;
end
Col_addr[1] = Addr;
Bank_addr[1] = Ba;
end
// Read interrupt Write (terminate Write immediately)
if (Data_in_enable == 1'b1) begin
Data_in_enable = 1'b0;
end
// Write Command
end else if (Write_enable == 1'b1) begin
if (Addr[10] == 1'b1) begin
Command[0] = `WRITE_A;
end else begin
Command[0] = `WRITE;
end
Col_addr[0] = Addr;
Bank_addr[0] = Ba;
// Write interrupt Write (terminate Write immediately)
if (Data_in_enable == 1'b1) begin
Data_in_enable = 1'b0;
end
// Write interrupt Read (terminate Read immediately)
if (Data_out_enable == 1'b1) begin
Data_out_enable = 1'b0;
end
end
// Interrupting a Write with Autoprecharge
if (Auto_precharge[Bank] == 1'b1 && Write_precharge[Bank] == 1'b1) begin
RW_interrupt_write[Bank] = 1'b1;
if (Debug) $display ("at time %t NOTE : Read/Write Bank %d interrupt Write Bank %d with Autoprecharge", $time, Ba, Bank);
end
// Interrupting a Read with Autoprecharge
if (Auto_precharge[Bank] == 1'b1 && Read_precharge[Bank] == 1'b1) begin
RW_interrupt_read[Bank] = 1'b1;
if (Debug) $display ("at time %t NOTE : Read/Write Bank %d interrupt Read Bank %d with Autoprecharge", $time, Ba, Bank);
end
// Read or Write with Auto Precharge
if (Addr[10] == 1'b1) begin
Auto_precharge[Ba] = 1'b1;
Count_precharge[Ba] = 0;
if (Read_enable == 1'b1) begin
Read_precharge[Ba] = 1'b1;
end else if (Write_enable == 1'b1) begin
Write_precharge[Ba] = 1'b1;
end
end
end
// Read with Auto Precharge Calculation
// The device start internal precharge:
// 1. CAS Latency - 1 cycles before last burst
// and 2. Meet minimum tRAS requirement
// or 3. Interrupt by a Read or Write (with or without AutoPrecharge)
if ((Auto_precharge[0] == 1'b1) && (Read_precharge[0] == 1'b1)) begin
if ((($time - RAS_chk0 >= tRAS) && // Case 2
((Burst_length_1 == 1'b1 && Count_precharge[0] >= 1) || // Case 1
(Burst_length_2 == 1'b1 && Count_precharge[0] >= 2) ||
(Burst_length_4 == 1'b1 && Count_precharge[0] >= 4) ||
(Burst_length_8 == 1'b1 && Count_precharge[0] >= 8))) ||
(RW_interrupt_read[0] == 1'b1)) begin // Case 3
Pc_b0 = 1'b1;
Act_b0 = 1'b0;
RP_chk0 = $time;
Auto_precharge[0] = 1'b0;
Read_precharge[0] = 1'b0;
RW_interrupt_read[0] = 1'b0;
if (Debug) $display ("at time %t NOTE : Start Internal Auto Precharge for Bank 0", $time);
end
end
if ((Auto_precharge[1] == 1'b1) && (Read_precharge[1] == 1'b1)) begin
if ((($time - RAS_chk1 >= tRAS) &&
((Burst_length_1 == 1'b1 && Count_precharge[1] >= 1) ||
(Burst_length_2 == 1'b1 && Count_precharge[1] >= 2) ||
(Burst_length_4 == 1'b1 && Count_precharge[1] >= 4) ||
(Burst_length_8 == 1'b1 && Count_precharge[1] >= 8))) ||
(RW_interrupt_read[1] == 1'b1)) begin
Pc_b1 = 1'b1;
Act_b1 = 1'b0;
RP_chk1 = $time;
Auto_precharge[1] = 1'b0;
Read_precharge[1] = 1'b0;
RW_interrupt_read[1] = 1'b0;
if (Debug) $display ("at time %t NOTE : Start Internal Auto Precharge for Bank 1", $time);
end
end
if ((Auto_precharge[2] == 1'b1) && (Read_precharge[2] == 1'b1)) begin
if ((($time - RAS_chk2 >= tRAS) &&
((Burst_length_1 == 1'b1 && Count_precharge[2] >= 1) ||
(Burst_length_2 == 1'b1 && Count_precharge[2] >= 2) ||
(Burst_length_4 == 1'b1 && Count_precharge[2] >= 4) ||
(Burst_length_8 == 1'b1 && Count_precharge[2] >= 8))) ||
(RW_interrupt_read[2] == 1'b1)) begin
Pc_b2 = 1'b1;
Act_b2 = 1'b0;
RP_chk2 = $time;
Auto_precharge[2] = 1'b0;
Read_precharge[2] = 1'b0;
RW_interrupt_read[2] = 1'b0;
if (Debug) $display ("at time %t NOTE : Start Internal Auto Precharge for Bank 2", $time);
end
end
if ((Auto_precharge[3] == 1'b1) && (Read_precharge[3] == 1'b1)) begin
if ((($time - RAS_chk3 >= tRAS) &&
((Burst_length_1 == 1'b1 && Count_precharge[3] >= 1) ||
(Burst_length_2 == 1'b1 && Count_precharge[3] >= 2) ||
(Burst_length_4 == 1'b1 && Count_precharge[3] >= 4) ||
(Burst_length_8 == 1'b1 && Count_precharge[3] >= 8))) ||
(RW_interrupt_read[3] == 1'b1)) begin
Pc_b3 = 1'b1;
Act_b3 = 1'b0;
RP_chk3 = $time;
Auto_precharge[3] = 1'b0;
Read_precharge[3] = 1'b0;
RW_interrupt_read[3] = 1'b0;
if (Debug) $display ("at time %t NOTE : Start Internal Auto Precharge for Bank 3", $time);
end
end
// Internal Precharge or Bst
if (Command[0] == `PRECH) begin // Precharge terminate a read with same bank or all banks
if (Bank_precharge[0] == Bank || A10_precharge[0] == 1'b1) begin
if (Data_out_enable == 1'b1) begin
Data_out_enable = 1'b0;
end
end
end else if (Command[0] == `BST) begin // BST terminate a read to current bank
if (Data_out_enable == 1'b1) begin
Data_out_enable = 1'b0;
end
end
if (Data_out_enable == 1'b0) begin
Dq_reg <= #tOH {data_bits{1'bz}};
end
// Detect Read or Write command
if (Command[0] == `READ || Command[0] == `READ_A) begin
Bank = Bank_addr[0];
Col = Col_addr[0];
Col_brst = Col_addr[0];
if (Bank_addr[0] == 2'b00) begin
Row = B0_row_addr;
end else if (Bank_addr[0] == 2'b01) begin
Row = B1_row_addr;
end else if (Bank_addr[0] == 2'b10) begin
Row = B2_row_addr;
end else if (Bank_addr[0] == 2'b11) begin
Row = B3_row_addr;
end
Burst_counter = 0;
Data_in_enable = 1'b0;
Data_out_enable = 1'b1;
end else if (Command[0] == `WRITE || Command[0] == `WRITE_A) begin
Bank = Bank_addr[0];
Col = Col_addr[0];
Col_brst = Col_addr[0];
if (Bank_addr[0] == 2'b00) begin
Row = B0_row_addr;
end else if (Bank_addr[0] == 2'b01) begin
Row = B1_row_addr;
end else if (Bank_addr[0] == 2'b10) begin
Row = B2_row_addr;
end else if (Bank_addr[0] == 2'b11) begin
Row = B3_row_addr;
end
Burst_counter = 0;
Data_in_enable = 1'b1;
Data_out_enable = 1'b0;
end
// DQ buffer (Driver/Receiver)
if (Data_in_enable == 1'b1) begin // Writing Data to Memory
// Array buffer
if (Bank == 2'b00) Dq_dqm [15 : 0] = Bank0 [{Row, Col}];
if (Bank == 2'b01) Dq_dqm [15 : 0] = Bank1 [{Row, Col}];
if (Bank == 2'b10) Dq_dqm [15 : 0] = Bank2 [{Row, Col}];
if (Bank == 2'b11) Dq_dqm [15 : 0] = Bank3 [{Row, Col}];
// Dqm operation
if (Dqm[0] == 1'b0) Dq_dqm [ 7 : 0] = Dq [ 7 : 0];
if (Dqm[1] == 1'b0) Dq_dqm [15 : 8] = Dq [15 : 8];
// Write to memory
if (Bank == 2'b00) Bank0 [{Row, Col}] = Dq_dqm [15 : 0];
if (Bank == 2'b01) Bank1 [{Row, Col}] = Dq_dqm [15 : 0];
if (Bank == 2'b10) Bank2 [{Row, Col}] = Dq_dqm [15 : 0];
if (Bank == 2'b11) Bank3 [{Row, Col}] = Dq_dqm [15 : 0];
// Output result
if (Dqm == 2'b11) begin
if (Debug) $display("at time %t WRITE: Bank = %d Row = %d, Col = %d, Data = Hi-Z due to DQM", $time, Bank, Row, Col);
end else begin
if (Debug) $display("at time %t WRITE: Bank = %d Row = %d, Col = %d, Data = %d, Dqm = %b", $time, Bank, Row, Col, Dq_dqm, Dqm);
// Record tWR time and reset counter
WR_chk [Bank] = $time;
WR_counter [Bank] = 0;
end
// Advance burst counter subroutine
#tHZ Burst;
end else if (Data_out_enable == 1'b1) begin // Reading Data from Memory
// Array buffer
if (Bank == 2'b00) Dq_dqm [15 : 0] = Bank0 [{Row, Col}];
if (Bank == 2'b01) Dq_dqm [15 : 0] = Bank1 [{Row, Col}];
if (Bank == 2'b10) Dq_dqm [15 : 0] = Bank2 [{Row, Col}];
if (Bank == 2'b11) Dq_dqm [15 : 0] = Bank3 [{Row, Col}];
// Dqm operation
if (Dqm_reg0[0] == 1'b1) Dq_dqm [ 7 : 0] = 8'bz;
if (Dqm_reg0[1] == 1'b1) Dq_dqm [15 : 8] = 8'bz;
// Display result
Dq_reg [15 : 0] = #tAC Dq_dqm [15 : 0];
if (Dqm_reg0 == 2'b11) begin
if (Debug) $display("at time %t READ : Bank = %d Row = %d, Col = %d, Data = Hi-Z due to DQM", $time, Bank, Row, Col);
end else begin
if (Debug) $display("at time %t READ : Bank = %d Row = %d, Col = %d, Data = %d, Dqm = %b", $time, Bank, Row, Col, Dq_reg, Dqm_reg0);
end
// Advance burst counter subroutine
Burst;
end
end
// Write with Auto Precharge Calculation
// The device start internal precharge:
// 1. tWR Clock after last burst
// and 2. Meet minimum tRAS requirement
// or 3. Interrupt by a Read or Write (with or without AutoPrecharge)
always @ (WR_counter[0]) begin
if ((Auto_precharge[0] == 1'b1) && (Write_precharge[0] == 1'b1)) begin
if ((($time - RAS_chk0 >= tRAS) && // Case 2
(((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [0] >= 1) || // Case 1
(Burst_length_2 == 1'b1 && Count_precharge [0] >= 2) ||
(Burst_length_4 == 1'b1 && Count_precharge [0] >= 4) ||
(Burst_length_8 == 1'b1 && Count_precharge [0] >= 8))) ||
(RW_interrupt_write[0] == 1'b1 && WR_counter[0] >= 2)) begin // Case 3 (stop count when interrupt)
Auto_precharge[0] = 1'b0;
Write_precharge[0] = 1'b0;
RW_interrupt_write[0] = 1'b0;
#tWRa; // Wait for tWR
Pc_b0 = 1'b1;
Act_b0 = 1'b0;
RP_chk0 = $time;
if (Debug) $display ("at time %t NOTE : Start Internal Auto Precharge for Bank 0", $time);
end
end
end
always @ (WR_counter[1]) begin
if ((Auto_precharge[1] == 1'b1) && (Write_precharge[1] == 1'b1)) begin
if ((($time - RAS_chk1 >= tRAS) &&
(((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [1] >= 1) ||
(Burst_length_2 == 1'b1 && Count_precharge [1] >= 2) ||
(Burst_length_4 == 1'b1 && Count_precharge [1] >= 4) ||
(Burst_length_8 == 1'b1 && Count_precharge [1] >= 8))) ||
(RW_interrupt_write[1] == 1'b1 && WR_counter[1] >= 2)) begin
Auto_precharge[1] = 1'b0;
Write_precharge[1] = 1'b0;
RW_interrupt_write[1] = 1'b0;
#tWRa; // Wait for tWR
Pc_b1 = 1'b1;
Act_b1 = 1'b0;
RP_chk1 = $time;
if (Debug) $display ("at time %t NOTE : Start Internal Auto Precharge for Bank 1", $time);
end
end
end
always @ (WR_counter[2]) begin
if ((Auto_precharge[2] == 1'b1) && (Write_precharge[2] == 1'b1)) begin
if ((($time - RAS_chk2 >= tRAS) &&
(((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [2] >= 1) ||
(Burst_length_2 == 1'b1 && Count_precharge [2] >= 2) ||
(Burst_length_4 == 1'b1 && Count_precharge [2] >= 4) ||
(Burst_length_8 == 1'b1 && Count_precharge [2] >= 8))) ||
(RW_interrupt_write[2] == 1'b1 && WR_counter[2] >= 2)) begin
Auto_precharge[2] = 1'b0;
Write_precharge[2] = 1'b0;
RW_interrupt_write[2] = 1'b0;
#tWRa; // Wait for tWR
Pc_b2 = 1'b1;
Act_b2 = 1'b0;
RP_chk2 = $time;
if (Debug) $display ("at time %t NOTE : Start Internal Auto Precharge for Bank 2", $time);
end
end
end
always @ (WR_counter[3]) begin
if ((Auto_precharge[3] == 1'b1) && (Write_precharge[3] == 1'b1)) begin
if ((($time - RAS_chk3 >= tRAS) &&
(((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [3] >= 1) ||
(Burst_length_2 == 1'b1 && Count_precharge [3] >= 2) ||
(Burst_length_4 == 1'b1 && Count_precharge [3] >= 4) ||
(Burst_length_8 == 1'b1 && Count_precharge [3] >= 8))) ||
(RW_interrupt_write[3] == 1'b1 && WR_counter[3] >= 2)) begin
Auto_precharge[3] = 1'b0;
Write_precharge[3] = 1'b0;
RW_interrupt_write[3] = 1'b0;
#tWRa; // Wait for tWR
Pc_b3 = 1'b1;
Act_b3 = 1'b0;
RP_chk3 = $time;
if (Debug) $display ("at time %t NOTE : Start Internal Auto Precharge for Bank 3", $time);
end
end
end
task Burst;
begin
// Advance Burst Counter
Burst_counter = Burst_counter + 1;
// Burst Type
if (Mode_reg[3] == 1'b0) begin // Sequential Burst
Col_temp = Col + 1;
end else if (Mode_reg[3] == 1'b1) begin // Interleaved Burst
Col_temp[2] = Burst_counter[2] ^ Col_brst[2];
Col_temp[1] = Burst_counter[1] ^ Col_brst[1];
Col_temp[0] = Burst_counter[0] ^ Col_brst[0];
end
// Burst Length
if (Burst_length_2) begin // Burst Length = 2
Col [0] = Col_temp [0];
end else if (Burst_length_4) begin // Burst Length = 4
Col [1 : 0] = Col_temp [1 : 0];
end else if (Burst_length_8) begin // Burst Length = 8
Col [2 : 0] = Col_temp [2 : 0];
end else begin // Burst Length = FULL
Col = Col_temp;
end
// Burst Read Single Write
if (Write_burst_mode == 1'b1) begin
Data_in_enable = 1'b0;
end
// Data Counter
if (Burst_length_1 == 1'b1) begin
if (Burst_counter >= 1) begin
Data_in_enable = 1'b0;
Data_out_enable = 1'b0;
end
end else if (Burst_length_2 == 1'b1) begin
if (Burst_counter >= 2) begin
Data_in_enable = 1'b0;
Data_out_enable = 1'b0;
end
end else if (Burst_length_4 == 1'b1) begin
if (Burst_counter >= 4) begin
Data_in_enable = 1'b0;
Data_out_enable = 1'b0;
end
end else if (Burst_length_8 == 1'b1) begin
if (Burst_counter >= 8) begin
Data_in_enable = 1'b0;
Data_out_enable = 1'b0;
end
end
end
endtask
// Timing Parameters for -75 (PC133) and CAS Latency = 2
specify
specparam
tAH = 0.8, // Addr, Ba Hold Time
tAS = 1.5, // Addr, Ba Setup Time
tCH = 2.5, // Clock High-Level Width
tCL = 2.5, // Clock Low-Level Width
tCK = 10, // Clock Cycle Time
tDH = 0.8, // Data-in Hold Time
tDS = 1.5, // Data-in Setup Time
tCKH = 0.8, // CKE Hold Time
tCKS = 1.5, // CKE Setup Time
tCMH = 0.8, // CS#, RAS#, CAS#, WE#, DQM# Hold Time
tCMS = 1.5; // CS#, RAS#, CAS#, WE#, DQM# Setup Time
$width (posedge Clk, tCH);
$width (negedge Clk, tCL);
$period (negedge Clk, tCK);
$period (posedge Clk, tCK);
$setuphold(posedge Clk, Cke, tCKS, tCKH);
$setuphold(posedge Clk, Cs_n, tCMS, tCMH);
$setuphold(posedge Clk, Cas_n, tCMS, tCMH);
$setuphold(posedge Clk, Ras_n, tCMS, tCMH);
$setuphold(posedge Clk, We_n, tCMS, tCMH);
$setuphold(posedge Clk, Addr, tAS, tAH);
$setuphold(posedge Clk, Ba, tAS, tAH);
$setuphold(posedge Clk, Dqm, tCMS, tCMH);
$setuphold(posedge Dq_chk, Dq, tDS, tDH);
endspecify
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__MUX2_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HVL__MUX2_FUNCTIONAL_PP_V
/**
* mux2: 2-input multiplexer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v"
`include "../../models/udp_mux_2to1/sky130_fd_sc_hvl__udp_mux_2to1.v"
`celldefine
module sky130_fd_sc_hvl__mux2 (
X ,
A0 ,
A1 ,
S ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A0 ;
input A1 ;
input S ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire mux_2to10_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
sky130_fd_sc_hvl__udp_mux_2to1 mux_2to10 (mux_2to10_out_X , A0, A1, S );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, mux_2to10_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__MUX2_FUNCTIONAL_PP_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A221O_BEHAVIORAL_V
`define SKY130_FD_SC_LS__A221O_BEHAVIORAL_V
/**
* a221o: 2-input AND into first two inputs of 3-input OR.
*
* X = ((A1 & A2) | (B1 & B2) | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__a221o (
X ,
A1,
A2,
B1,
B2,
C1
);
// Module ports
output X ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out ;
wire and1_out ;
wire or0_out_X;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
and and1 (and1_out , A1, A2 );
or or0 (or0_out_X, and1_out, and0_out, C1);
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__A221O_BEHAVIORAL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DFXBP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__DFXBP_FUNCTIONAL_PP_V
/**
* dfxbp: Delay flop, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_hd__udp_dff_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hd__dfxbp (
Q ,
Q_N ,
CLK ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q;
// Delay Name Output Other arguments
sky130_fd_sc_hd__udp_dff$P_pp$PG$N `UNIT_DELAY dff0 (buf_Q , D, CLK, , VPWR, VGND);
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__DFXBP_FUNCTIONAL_PP_V
|
//*****************************************************************************
// (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 4.0
// \ \ Application : MIG
// / / Filename : ddr_axi_mig.v
// /___/ /\ Date Last Modified : $Date: 2011/06/02 08:35:03 $
// \ \ / \ Date Created : Fri Oct 14 2011
// \___\/\___\
//
// Device : 7 Series
// Design Name : DDR2 SDRAM
// Purpose :
// Top-level module. This module can be instantiated in the
// system and interconnect as shown in user design wrapper file (user top module).
// In addition to the memory controller, the module instantiates:
// 1. Clock generation/distribution, reset logic
// 2. IDELAY control block
// 3. Debug logic
// Reference :
// Revision History :
//*****************************************************************************
`timescale 1ps/1ps
module ddr_axi_mig #
(
parameter RST_ACT_LOW = 1,
// =1 for active low reset,
// =0 for active high.
//***************************************************************************
// The following parameters refer to width of various ports
//***************************************************************************
parameter BANK_WIDTH = 3,
// # of memory Bank Address bits.
parameter CK_WIDTH = 1,
// # of CK/CK# outputs to memory.
parameter COL_WIDTH = 10,
// # of memory Column Address bits.
parameter CS_WIDTH = 1,
// # of unique CS outputs to memory.
parameter nCS_PER_RANK = 1,
// # of unique CS outputs per rank for phy
parameter CKE_WIDTH = 1,
// # of CKE outputs to memory.
parameter DATA_BUF_ADDR_WIDTH = 4,
parameter DQ_CNT_WIDTH = 4,
// = ceil(log2(DQ_WIDTH))
parameter DQ_PER_DM = 8,
parameter DM_WIDTH = 2,
// # of DM (data mask)
parameter DQ_WIDTH = 16,
// # of DQ (data)
parameter DQS_WIDTH = 2,
parameter DQS_CNT_WIDTH = 1,
// = ceil(log2(DQS_WIDTH))
parameter DRAM_WIDTH = 8,
// # of DQ per DQS
parameter ECC = "OFF",
parameter DATA_WIDTH = 16,
parameter ECC_TEST = "OFF",
parameter PAYLOAD_WIDTH = (ECC_TEST == "OFF") ? DATA_WIDTH : DQ_WIDTH,
parameter MEM_ADDR_ORDER = "BANK_ROW_COLUMN",
//Possible Parameters
//1.BANK_ROW_COLUMN : Address mapping is
// in form of Bank Row Column.
//2.ROW_BANK_COLUMN : Address mapping is
// in the form of Row Bank Column.
//3.TG_TEST : Scrambles Address bits
// for distributed Addressing.
//parameter nBANK_MACHS = 4,
parameter nBANK_MACHS = 4,
parameter RANKS = 1,
// # of Ranks.
parameter ODT_WIDTH = 1,
// # of ODT outputs to memory.
parameter ROW_WIDTH = 13,
// # of memory Row Address bits.
parameter ADDR_WIDTH = 27,
// # = RANK_WIDTH + BANK_WIDTH
// + ROW_WIDTH + COL_WIDTH;
// Chip Select is always tied to low for
// single rank devices
parameter USE_CS_PORT = 1,
// # = 1, When Chip Select (CS#) output is enabled
// = 0, When Chip Select (CS#) output is disabled
// If CS_N disabled, user must connect
// DRAM CS_N input(s) to ground
parameter USE_DM_PORT = 1,
// # = 1, When Data Mask option is enabled
// = 0, When Data Mask option is disbaled
// When Data Mask option is disabled in
// MIG Controller Options page, the logic
// related to Data Mask should not get
// synthesized
parameter USE_ODT_PORT = 1,
// # = 1, When ODT output is enabled
// = 0, When ODT output is disabled
parameter PHY_CONTROL_MASTER_BANK = 0,
// The bank index where master PHY_CONTROL resides,
// equal to the PLL residing bank
parameter MEM_DENSITY = "1Gb",
// Indicates the density of the Memory part
// Added for the sake of Vivado simulations
parameter MEM_SPEEDGRADE = "25E",
// Indicates the Speed grade of Memory Part
// Added for the sake of Vivado simulations
parameter MEM_DEVICE_WIDTH = 16,
// Indicates the device width of the Memory Part
// Added for the sake of Vivado simulations
//***************************************************************************
// The following parameters are mode register settings
//***************************************************************************
parameter AL = "0",
// DDR3 SDRAM:
// Additive Latency (Mode Register 1).
// # = "0", "CL-1", "CL-2".
// DDR2 SDRAM:
// Additive Latency (Extended Mode Register).
parameter nAL = 0,
// # Additive Latency in number of clock
// cycles.
parameter BURST_MODE = "8",
// DDR3 SDRAM:
// Burst Length (Mode Register 0).
// # = "8", "4", "OTF".
// DDR2 SDRAM:
// Burst Length (Mode Register).
// # = "8", "4".
parameter BURST_TYPE = "SEQ",
// DDR3 SDRAM: Burst Type (Mode Register 0).
// DDR2 SDRAM: Burst Type (Mode Register).
// # = "SEQ" - (Sequential),
// = "INT" - (Interleaved).
parameter CL = 5,
// in number of clock cycles
// DDR3 SDRAM: CAS Latency (Mode Register 0).
// DDR2 SDRAM: CAS Latency (Mode Register).
parameter OUTPUT_DRV = "HIGH",
// Output Drive Strength (Extended Mode Register).
// # = "HIGH" - FULL,
// = "LOW" - REDUCED.
parameter RTT_NOM = "50",
// RTT (Nominal) (Extended Mode Register).
// = "150" - 150 Ohms,
// = "75" - 75 Ohms,
// = "50" - 50 Ohms.
parameter ADDR_CMD_MODE = "1T" ,
// # = "1T", "2T".
parameter REG_CTRL = "OFF",
// # = "ON" - RDIMMs,
// = "OFF" - Components, SODIMMs, UDIMMs.
//***************************************************************************
// The following parameters are multiplier and divisor factors for PLLE2.
// Based on the selected design frequency these parameters vary.
//***************************************************************************
parameter CLKIN_PERIOD = 4999,
// Input Clock Period
parameter CLKFBOUT_MULT = 6,
// write PLL VCO multiplier
parameter DIVCLK_DIVIDE = 1,
// write PLL VCO divisor
parameter CLKOUT0_PHASE = 0.0,
// Phase for PLL output clock (CLKOUT0)
parameter CLKOUT0_DIVIDE = 2,
// VCO output divisor for PLL output clock (CLKOUT0)
parameter CLKOUT1_DIVIDE = 4,
// VCO output divisor for PLL output clock (CLKOUT1)
parameter CLKOUT2_DIVIDE = 64,
// VCO output divisor for PLL output clock (CLKOUT2)
parameter CLKOUT3_DIVIDE = 8,
// VCO output divisor for PLL output clock (CLKOUT3)
parameter MMCM_VCO = 1200,
// Max Freq (MHz) of MMCM VCO
parameter MMCM_MULT_F = 7,
// write MMCM VCO multiplier
parameter MMCM_DIVCLK_DIVIDE = 1,
// write MMCM VCO divisor
//***************************************************************************
// Memory Timing Parameters. These parameters varies based on the selected
// memory part.
//***************************************************************************
parameter tCKE = 7500,
// memory tCKE paramter in pS
parameter tFAW = 45000,
// memory tRAW paramter in pS.
parameter tPRDI = 1_000_000,
// memory tPRDI paramter in pS.
parameter tRAS = 40000,
// memory tRAS paramter in pS.
parameter tRCD = 15000,
// memory tRCD paramter in pS.
parameter tREFI = 7800000,
// memory tREFI paramter in pS.
parameter tRFC = 127500,
// memory tRFC paramter in pS.
parameter tRP = 12500,
// memory tRP paramter in pS.
parameter tRRD = 10000,
// memory tRRD paramter in pS.
parameter tRTP = 7500,
// memory tRTP paramter in pS.
parameter tWTR = 7500,
// memory tWTR paramter in pS.
parameter tZQI = 128_000_000,
// memory tZQI paramter in nS.
parameter tZQCS = 64,
// memory tZQCS paramter in clock cycles.
//***************************************************************************
// Simulation parameters
//***************************************************************************
parameter SIM_BYPASS_INIT_CAL = "FAST",
// # = "OFF" - Complete memory init &
// calibration sequence
// # = "SKIP" - Not supported
// # = "FAST" - Complete memory init & use
// abbreviated calib sequence
parameter SIMULATION = "TRUE",
// Should be TRUE during design simulations and
// FALSE during implementations
//***************************************************************************
// The following parameters varies based on the pin out entered in MIG GUI.
// Do not change any of these parameters directly by editing the RTL.
// Any changes required should be done through GUI and the design regenerated.
//***************************************************************************
parameter BYTE_LANES_B0 = 4'b1111,
// Byte lanes used in an IO column.
parameter BYTE_LANES_B1 = 4'b0000,
// Byte lanes used in an IO column.
parameter BYTE_LANES_B2 = 4'b0000,
// Byte lanes used in an IO column.
parameter BYTE_LANES_B3 = 4'b0000,
// Byte lanes used in an IO column.
parameter BYTE_LANES_B4 = 4'b0000,
// Byte lanes used in an IO column.
parameter DATA_CTL_B0 = 4'b0101,
// Indicates Byte lane is data byte lane
// or control Byte lane. '1' in a bit
// position indicates a data byte lane and
// a '0' indicates a control byte lane
parameter DATA_CTL_B1 = 4'b0000,
// Indicates Byte lane is data byte lane
// or control Byte lane. '1' in a bit
// position indicates a data byte lane and
// a '0' indicates a control byte lane
parameter DATA_CTL_B2 = 4'b0000,
// Indicates Byte lane is data byte lane
// or control Byte lane. '1' in a bit
// position indicates a data byte lane and
// a '0' indicates a control byte lane
parameter DATA_CTL_B3 = 4'b0000,
// Indicates Byte lane is data byte lane
// or control Byte lane. '1' in a bit
// position indicates a data byte lane and
// a '0' indicates a control byte lane
parameter DATA_CTL_B4 = 4'b0000,
// Indicates Byte lane is data byte lane
// or control Byte lane. '1' in a bit
// position indicates a data byte lane and
// a '0' indicates a control byte lane
parameter PHY_0_BITLANES = 48'hFFC_3F7_FFF_3FE,
parameter PHY_1_BITLANES = 48'h000_000_000_000,
parameter PHY_2_BITLANES = 48'h000_000_000_000,
// control/address/data pin mapping parameters
parameter CK_BYTE_MAP
= 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_03,
parameter ADDR_MAP
= 192'h000_000_000_010_033_01A_019_032_03A_034_018_036_012_011_017_015,
parameter BANK_MAP = 36'h013_016_01B,
parameter CAS_MAP = 12'h039,
parameter CKE_ODT_BYTE_MAP = 8'h00,
parameter CKE_MAP = 96'h000_000_000_000_000_000_000_038,
parameter ODT_MAP = 96'h000_000_000_000_000_000_000_035,
parameter CS_MAP = 120'h000_000_000_000_000_000_000_000_000_037,
parameter PARITY_MAP = 12'h000,
parameter RAS_MAP = 12'h014,
parameter WE_MAP = 12'h03B,
parameter DQS_BYTE_MAP
= 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_02_00,
parameter DATA0_MAP = 96'h008_004_009_007_005_001_006_003,
parameter DATA1_MAP = 96'h022_028_020_024_027_025_026_021,
parameter DATA2_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA3_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA4_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA5_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA6_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA7_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA8_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA9_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA10_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA11_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA12_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA13_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA14_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA15_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA16_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA17_MAP = 96'h000_000_000_000_000_000_000_000,
parameter MASK0_MAP = 108'h000_000_000_000_000_000_000_029_002,
parameter MASK1_MAP = 108'h000_000_000_000_000_000_000_000_000,
parameter SLOT_0_CONFIG = 8'b0000_0001,
// Mapping of Ranks.
parameter SLOT_1_CONFIG = 8'b0000_0000,
// Mapping of Ranks.
//***************************************************************************
// IODELAY and PHY related parameters
//***************************************************************************
parameter IBUF_LPWR_MODE = "OFF",
// to phy_top
parameter DATA_IO_IDLE_PWRDWN = "OFF",
// # = "ON", "OFF"
parameter BANK_TYPE = "HR_IO",
// # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO"
parameter DATA_IO_PRIM_TYPE = "DEFAULT",
// # = "HP_LP", "HR_LP", "DEFAULT"
parameter CKE_ODT_AUX = "FALSE",
parameter USER_REFRESH = "OFF",
parameter WRLVL = "OFF",
// # = "ON" - DDR3 SDRAM
// = "OFF" - DDR2 SDRAM.
parameter ORDERING = "STRICT",
// # = "NORM", "STRICT", "RELAXED".
parameter CALIB_ROW_ADD = 16'h0000,
// Calibration row address will be used for
// calibration read and write operations
parameter CALIB_COL_ADD = 12'h000,
// Calibration column address will be used for
// calibration read and write operations
parameter CALIB_BA_ADD = 3'h0,
// Calibration bank address will be used for
// calibration read and write operations
parameter TCQ = 100,
parameter IODELAY_GRP0 = "DDR_AXI_IODELAY_MIG0",
// It is associated to a set of IODELAYs with
// an IDELAYCTRL that have same IODELAY CONTROLLER
// clock frequency (200MHz).
parameter SYSCLK_TYPE = "NO_BUFFER",
// System clock type DIFFERENTIAL, SINGLE_ENDED,
// NO_BUFFER
parameter REFCLK_TYPE = "USE_SYSTEM_CLOCK",
// Reference clock type DIFFERENTIAL, SINGLE_ENDED,
// NO_BUFFER, USE_SYSTEM_CLOCK
parameter SYS_RST_PORT = "FALSE",
// "TRUE" - if pin is selected for sys_rst
// and IBUF will be instantiated.
// "FALSE" - if pin is not selected for sys_rst
parameter CMD_PIPE_PLUS1 = "ON",
// add pipeline stage between MC and PHY
parameter DRAM_TYPE = "DDR2",
parameter CAL_WIDTH = "HALF",
parameter STARVE_LIMIT = 2,
// # = 2,3,4.
//***************************************************************************
// Referece clock frequency parameters
//***************************************************************************
parameter REFCLK_FREQ = 200.0,
// IODELAYCTRL reference clock frequency
parameter DIFF_TERM_REFCLK = "TRUE",
// Differential Termination for idelay
// reference clock input pins
//***************************************************************************
// System clock frequency parameters
//***************************************************************************
parameter tCK = 3333,
// memory tCK paramter.
// # = Clock Period in pS.
parameter nCK_PER_CLK = 2,
// # of memory CKs per fabric CLK
parameter DIFF_TERM_SYSCLK = "TRUE",
// Differential Termination for System
// clock input pins
//***************************************************************************
// AXI4 Shim parameters
//***************************************************************************
parameter UI_EXTRA_CLOCKS = "FALSE",
// Generates extra clocks as
// 1/2, 1/4 and 1/8 of fabrick clock.
// Valid for DDR2/DDR3 AXI interfaces
// based on GUI selection
parameter C_S_AXI_ID_WIDTH = 4,
// Width of all master and slave ID signals.
// # = >= 1.
parameter C_S_AXI_MEM_SIZE = "134217728",
// Address Space required for this component
parameter C_S_AXI_ADDR_WIDTH = 32,
// Width of S_AXI_AWADDR, S_AXI_ARADDR, M_AXI_AWADDR and
// M_AXI_ARADDR for all SI/MI slots.
// # = 32.
parameter C_S_AXI_DATA_WIDTH = 32,
// Width of WDATA and RDATA on SI slot.
// Must be <= APP_DATA_WIDTH.
// # = 32, 64, 128, 256.
parameter C_MC_nCK_PER_CLK = 2,
// Indicates whether to instatiate upsizer
// Range: 0, 1
parameter C_S_AXI_SUPPORTS_NARROW_BURST = 0,
// Indicates whether to instatiate upsizer
// Range: 0, 1
parameter C_RD_WR_ARB_ALGORITHM = "RD_PRI_REG",
// Indicates the Arbitration
// Allowed values - "TDM", "ROUND_ROBIN",
// "RD_PRI_REG", "RD_PRI_REG_STARVE_LIMIT"
// "WRITE_PRIORITY", "WRITE_PRIORITY_REG"
parameter C_S_AXI_REG_EN0 = 20'h00000,
// C_S_AXI_REG_EN0[00] = Reserved
// C_S_AXI_REG_EN0[04] = AW CHANNEL REGISTER SLICE
// C_S_AXI_REG_EN0[05] = W CHANNEL REGISTER SLICE
// C_S_AXI_REG_EN0[06] = B CHANNEL REGISTER SLICE
// C_S_AXI_REG_EN0[07] = R CHANNEL REGISTER SLICE
// C_S_AXI_REG_EN0[08] = AW CHANNEL UPSIZER REGISTER SLICE
// C_S_AXI_REG_EN0[09] = W CHANNEL UPSIZER REGISTER SLICE
// C_S_AXI_REG_EN0[10] = AR CHANNEL UPSIZER REGISTER SLICE
// C_S_AXI_REG_EN0[11] = R CHANNEL UPSIZER REGISTER SLICE
parameter C_S_AXI_REG_EN1 = 20'h00000,
// Instatiates register slices after the upsizer.
// The type of register is specified for each channel
// in a vector. 4 bits per channel are used.
// C_S_AXI_REG_EN1[03:00] = AW CHANNEL REGISTER SLICE
// C_S_AXI_REG_EN1[07:04] = W CHANNEL REGISTER SLICE
// C_S_AXI_REG_EN1[11:08] = B CHANNEL REGISTER SLICE
// C_S_AXI_REG_EN1[15:12] = AR CHANNEL REGISTER SLICE
// C_S_AXI_REG_EN1[20:16] = R CHANNEL REGISTER SLICE
// Possible values for each channel are:
//
// 0 => BYPASS = The channel is just wired through the
// module.
// 1 => FWD = The master VALID and payload signals
// are registrated.
// 2 => REV = The slave ready signal is registrated
// 3 => FWD_REV = Both FWD and REV
// 4 => SLAVE_FWD = All slave side signals and master
// VALID and payload are registrated.
// 5 => SLAVE_RDY = All slave side signals and master
// READY are registrated.
// 6 => INPUTS = Slave and Master side inputs are
// registrated.
// 7 => ADDRESS = Optimized for address channel
parameter C_S_AXI_CTRL_ADDR_WIDTH = 32,
// Width of AXI-4-Lite address bus
parameter C_S_AXI_CTRL_DATA_WIDTH = 32,
// Width of AXI-4-Lite data buses
parameter C_S_AXI_BASEADDR = 32'h0000_0000,
// Base address of AXI4 Memory Mapped bus.
parameter C_ECC_ONOFF_RESET_VALUE = 1,
// Controls ECC on/off value at startup/reset
parameter C_ECC_CE_COUNTER_WIDTH = 8,
// The external memory to controller clock ratio.
//***************************************************************************
// Debug parameters
//***************************************************************************
parameter DEBUG_PORT = "OFF",
// # = "ON" Enable debug signals/controls.
// = "OFF" Disable debug signals/controls.
//***************************************************************************
// Temparature monitor parameter
//***************************************************************************
parameter TEMP_MON_CONTROL = "EXTERNAL"
// # = "INTERNAL", "EXTERNAL"
// parameter RST_ACT_LOW = 1
// =1 for active low reset,
// =0 for active high.
)
(
// Inouts
inout [DQ_WIDTH-1:0] ddr2_dq,
inout [DQS_WIDTH-1:0] ddr2_dqs_n,
inout [DQS_WIDTH-1:0] ddr2_dqs_p,
// Outputs
output [ROW_WIDTH-1:0] ddr2_addr,
output [BANK_WIDTH-1:0] ddr2_ba,
output ddr2_ras_n,
output ddr2_cas_n,
output ddr2_we_n,
output [CK_WIDTH-1:0] ddr2_ck_p,
output [CK_WIDTH-1:0] ddr2_ck_n,
output [CKE_WIDTH-1:0] ddr2_cke,
output [(CS_WIDTH*nCS_PER_RANK)-1:0] ddr2_cs_n,
output [DM_WIDTH-1:0] ddr2_dm,
output [ODT_WIDTH-1:0] ddr2_odt,
// Inputs
// Single-ended system clock
input sys_clk_i,
// user interface signals
output ui_clk,
output ui_clk_sync_rst,
output mmcm_locked,
input aresetn,
input app_sr_req,
input app_ref_req,
input app_zq_req,
output app_sr_active,
output app_ref_ack,
output app_zq_ack,
// Slave Interface Write Address Ports
input [C_S_AXI_ID_WIDTH-1:0] s_axi_awid,
input [C_S_AXI_ADDR_WIDTH-1:0] s_axi_awaddr,
input [7:0] s_axi_awlen,
input [2:0] s_axi_awsize,
input [1:0] s_axi_awburst,
input [0:0] s_axi_awlock,
input [3:0] s_axi_awcache,
input [2:0] s_axi_awprot,
input [3:0] s_axi_awqos,
input s_axi_awvalid,
output s_axi_awready,
// Slave Interface Write Data Ports
input [C_S_AXI_DATA_WIDTH-1:0] s_axi_wdata,
input [(C_S_AXI_DATA_WIDTH/8)-1:0] s_axi_wstrb,
input s_axi_wlast,
input s_axi_wvalid,
output s_axi_wready,
// Slave Interface Write Response Ports
input s_axi_bready,
output [C_S_AXI_ID_WIDTH-1:0] s_axi_bid,
output [1:0] s_axi_bresp,
output s_axi_bvalid,
// Slave Interface Read Address Ports
input [C_S_AXI_ID_WIDTH-1:0] s_axi_arid,
input [C_S_AXI_ADDR_WIDTH-1:0] s_axi_araddr,
input [7:0] s_axi_arlen,
input [2:0] s_axi_arsize,
input [1:0] s_axi_arburst,
input [0:0] s_axi_arlock,
input [3:0] s_axi_arcache,
input [2:0] s_axi_arprot,
input [3:0] s_axi_arqos,
input s_axi_arvalid,
output s_axi_arready,
// Slave Interface Read Data Ports
input s_axi_rready,
output [C_S_AXI_ID_WIDTH-1:0] s_axi_rid,
output [C_S_AXI_DATA_WIDTH-1:0] s_axi_rdata,
output [1:0] s_axi_rresp,
output s_axi_rlast,
output s_axi_rvalid,
output init_calib_complete,
input [11:0] device_temp_i,
// The 12 MSB bits of the temperature sensor transfer
// function need to be connected to this port. This port
// will be synchronized w.r.t. to fabric clock internally.
// System reset - Default polarity of sys_rst pin is Active Low.
// System reset polarity will change based on the option
// selected in GUI.
input sys_rst
);
function integer clogb2 (input integer size);
begin
size = size - 1;
for (clogb2=1; size>1; clogb2=clogb2+1)
size = size >> 1;
end
endfunction // clogb2
localparam BM_CNT_WIDTH = clogb2(nBANK_MACHS);
localparam RANK_WIDTH = clogb2(RANKS);
localparam ECC_WIDTH = (ECC == "OFF")?
0 : (DATA_WIDTH <= 4)?
4 : (DATA_WIDTH <= 10)?
5 : (DATA_WIDTH <= 26)?
6 : (DATA_WIDTH <= 57)?
7 : (DATA_WIDTH <= 120)?
8 : (DATA_WIDTH <= 247)?
9 : 10;
localparam DATA_BUF_OFFSET_WIDTH = 1;
localparam MC_ERR_ADDR_WIDTH = ((CS_WIDTH == 1) ? 0 : RANK_WIDTH)
+ BANK_WIDTH + ROW_WIDTH + COL_WIDTH
+ DATA_BUF_OFFSET_WIDTH;
localparam APP_DATA_WIDTH = 2 * nCK_PER_CLK * PAYLOAD_WIDTH;
localparam APP_MASK_WIDTH = APP_DATA_WIDTH / 8;
localparam TEMP_MON_EN = (SIMULATION == "TRUE") ? "ON" : "OFF";
// Enable or disable the temp monitor module
localparam tTEMPSAMPLE = 10000000; // sample every 10 us
localparam XADC_CLK_PERIOD = 5000; // Use 200 MHz IODELAYCTRL clock
localparam TAPSPERKCLK = 56;
// Wire declarations
wire [BM_CNT_WIDTH-1:0] bank_mach_next;
wire clk;
wire [1:0] clk_ref;
wire [1:0] iodelay_ctrl_rdy;
wire clk_ref_in;
wire sys_rst_o;
wire clk_div2;
wire rst_div2;
wire freq_refclk ;
wire mem_refclk ;
wire pll_lock ;
wire sync_pulse;
wire mmcm_ps_clk;
wire poc_sample_pd;
wire psen;
wire psincdec;
wire psdone;
wire iddr_rst;
wire ref_dll_lock;
wire rst_phaser_ref;
wire pll_locked;
wire rst;
wire [(2*nCK_PER_CLK)-1:0] app_ecc_multiple_err;
wire [(2*nCK_PER_CLK)-1:0] app_ecc_single_err;
wire ddr2_reset_n;
wire ddr2_parity;
// AXI CTRL port
wire s_axi_ctrl_awvalid;
wire s_axi_ctrl_awready;
wire [C_S_AXI_CTRL_ADDR_WIDTH-1:0] s_axi_ctrl_awaddr;
// Slave Interface Write Data Ports
wire s_axi_ctrl_wvalid;
wire s_axi_ctrl_wready;
wire [C_S_AXI_CTRL_DATA_WIDTH-1:0] s_axi_ctrl_wdata;
// Slave Interface Write Response Ports
wire s_axi_ctrl_bvalid;
wire s_axi_ctrl_bready;
wire [1:0] s_axi_ctrl_bresp;
// Slave Interface Read Address Ports
wire s_axi_ctrl_arvalid;
wire s_axi_ctrl_arready;
wire [C_S_AXI_CTRL_ADDR_WIDTH-1:0] s_axi_ctrl_araddr;
// Slave Interface Read Data Ports
wire s_axi_ctrl_rvalid;
wire s_axi_ctrl_rready;
wire [C_S_AXI_CTRL_DATA_WIDTH-1:0] s_axi_ctrl_rdata;
wire [1:0] s_axi_ctrl_rresp;
// Interrupt output
wire interrupt;
wire sys_clk_p;
wire sys_clk_n;
wire mmcm_clk;
wire clk_ref_p;
wire clk_ref_n;
wire clk_ref_i;
wire [11:0] device_temp;
// Debug port signals
wire dbg_idel_down_all;
wire dbg_idel_down_cpt;
wire dbg_idel_up_all;
wire dbg_idel_up_cpt;
wire dbg_sel_all_idel_cpt;
wire [DQS_CNT_WIDTH-1:0] dbg_sel_idel_cpt;
wire dbg_sel_pi_incdec;
wire [DQS_CNT_WIDTH:0] dbg_byte_sel;
wire dbg_pi_f_inc;
wire dbg_pi_f_dec;
wire [5:0] dbg_pi_counter_read_val;
wire [8:0] dbg_po_counter_read_val;
wire [(6*DQS_WIDTH*RANKS)-1:0] dbg_cpt_tap_cnt;
wire [(5*DQS_WIDTH*RANKS)-1:0] dbg_dq_idelay_tap_cnt;
wire [255:0] dbg_calib_top;
wire [(6*DQS_WIDTH*RANKS)-1:0] dbg_cpt_first_edge_cnt;
wire [(6*DQS_WIDTH*RANKS)-1:0] dbg_cpt_second_edge_cnt;
wire [(6*RANKS)-1:0] dbg_rd_data_offset;
wire [255:0] dbg_phy_rdlvl;
wire [99:0] dbg_phy_wrcal;
wire [(6*DQS_WIDTH)-1:0] dbg_final_po_fine_tap_cnt;
wire [(3*DQS_WIDTH)-1:0] dbg_final_po_coarse_tap_cnt;
wire [255:0] dbg_phy_wrlvl;
wire [255:0] dbg_phy_init;
wire [255:0] dbg_prbs_rdlvl;
wire [255:0] dbg_dqs_found_cal;
wire dbg_pi_phaselock_start;
wire dbg_pi_phaselocked_done;
wire dbg_pi_phaselock_err;
wire dbg_pi_dqsfound_start;
wire dbg_pi_dqsfound_done;
wire dbg_pi_dqsfound_err;
wire dbg_wrcal_start;
wire dbg_wrcal_done;
wire dbg_wrcal_err;
wire [11:0] dbg_pi_dqs_found_lanes_phy4lanes;
wire [11:0] dbg_pi_phase_locked_phy4lanes;
wire dbg_oclkdelay_calib_start;
wire dbg_oclkdelay_calib_done;
wire [255:0] dbg_phy_oclkdelay_cal;
wire [(DRAM_WIDTH*16)-1:0] dbg_oclkdelay_rd_data;
wire [DQS_WIDTH-1:0] dbg_rd_data_edge_detect;
wire [(2*nCK_PER_CLK*DQ_WIDTH)-1:0] dbg_rddata;
wire dbg_rddata_valid;
wire [1:0] dbg_rdlvl_done;
wire [1:0] dbg_rdlvl_err;
wire [1:0] dbg_rdlvl_start;
wire [(6*DQS_WIDTH)-1:0] dbg_wrlvl_fine_tap_cnt;
wire [(3*DQS_WIDTH)-1:0] dbg_wrlvl_coarse_tap_cnt;
wire [5:0] dbg_tap_cnt_during_wrlvl;
wire dbg_wl_edge_detect_valid;
wire dbg_wrlvl_done;
wire dbg_wrlvl_err;
wire dbg_wrlvl_start;
reg [63:0] dbg_rddata_r;
reg dbg_rddata_valid_r;
wire [53:0] ocal_tap_cnt;
wire [4:0] dbg_dqs;
wire [8:0] dbg_bit;
wire [8:0] rd_data_edge_detect_r;
wire [53:0] wl_po_fine_cnt;
wire [26:0] wl_po_coarse_cnt;
wire [(6*RANKS)-1:0] dbg_calib_rd_data_offset_1;
wire [(6*RANKS)-1:0] dbg_calib_rd_data_offset_2;
wire [5:0] dbg_data_offset;
wire [5:0] dbg_data_offset_1;
wire [5:0] dbg_data_offset_2;
wire [390:0] ddr2_ila_wrpath_int;
wire [1023:0] ddr2_ila_rdpath_int;
wire [119:0] ddr2_ila_basic_int;
wire [(6*DQS_WIDTH*RANKS)-1:0] dbg_prbs_final_dqs_tap_cnt_r_int;
wire [(6*DQS_WIDTH*RANKS)-1:0] dbg_prbs_first_edge_taps_int;
wire [(6*DQS_WIDTH*RANKS)-1:0] dbg_prbs_second_edge_taps_int;
//***************************************************************************
assign ui_clk = clk;
assign ui_clk_sync_rst = rst;
assign sys_clk_p = 1'b0;
assign sys_clk_n = 1'b0;
assign clk_ref_i = 1'b0;
generate
if (REFCLK_TYPE == "USE_SYSTEM_CLOCK")
assign clk_ref_in = mmcm_clk;
else
assign clk_ref_in = clk_ref_i;
endgenerate
mig_7series_v4_0_iodelay_ctrl #
(
.TCQ (TCQ),
.IODELAY_GRP0 (IODELAY_GRP0),
.REFCLK_TYPE (REFCLK_TYPE),
.SYSCLK_TYPE (SYSCLK_TYPE),
.SYS_RST_PORT (SYS_RST_PORT),
.RST_ACT_LOW (RST_ACT_LOW),
.DIFF_TERM_REFCLK (DIFF_TERM_REFCLK)
)
u_iodelay_ctrl
(
// Outputs
.iodelay_ctrl_rdy (iodelay_ctrl_rdy),
.sys_rst_o (sys_rst_o),
.clk_ref (clk_ref),
// Inputs
.clk_ref_p (clk_ref_p),
.clk_ref_n (clk_ref_n),
.clk_ref_i (clk_ref_in),
.sys_rst (sys_rst)
);
mig_7series_v4_0_clk_ibuf #
(
.SYSCLK_TYPE (SYSCLK_TYPE),
.DIFF_TERM_SYSCLK (DIFF_TERM_SYSCLK)
)
u_ddr2_clk_ibuf
(
.sys_clk_p (sys_clk_p),
.sys_clk_n (sys_clk_n),
.sys_clk_i (sys_clk_i),
.mmcm_clk (mmcm_clk)
);
// Temperature monitoring logic
generate
if (TEMP_MON_EN == "ON") begin: temp_mon_enabled
mig_7series_v4_0_tempmon #
(
.TCQ (TCQ),
.TEMP_MON_CONTROL (TEMP_MON_CONTROL),
.XADC_CLK_PERIOD (XADC_CLK_PERIOD),
.tTEMPSAMPLE (tTEMPSAMPLE)
)
u_tempmon
(
.clk (clk),
.xadc_clk (clk_ref[0]),
.rst (rst),
.device_temp_i (device_temp_i),
.device_temp (device_temp)
);
end else begin: temp_mon_disabled
assign device_temp = 'b0;
end
endgenerate
mig_7series_v4_0_infrastructure #
(
.TCQ (TCQ),
.nCK_PER_CLK (nCK_PER_CLK),
.CLKIN_PERIOD (CLKIN_PERIOD),
.SYSCLK_TYPE (SYSCLK_TYPE),
.CLKFBOUT_MULT (CLKFBOUT_MULT),
.DIVCLK_DIVIDE (DIVCLK_DIVIDE),
.CLKOUT0_PHASE (CLKOUT0_PHASE),
.CLKOUT0_DIVIDE (CLKOUT0_DIVIDE),
.CLKOUT1_DIVIDE (CLKOUT1_DIVIDE),
.CLKOUT2_DIVIDE (CLKOUT2_DIVIDE),
.CLKOUT3_DIVIDE (CLKOUT3_DIVIDE),
.MMCM_VCO (MMCM_VCO),
.MMCM_MULT_F (MMCM_MULT_F),
.MMCM_DIVCLK_DIVIDE (MMCM_DIVCLK_DIVIDE),
.RST_ACT_LOW (RST_ACT_LOW),
.tCK (tCK),
.MEM_TYPE (DRAM_TYPE)
)
u_ddr2_infrastructure
(
// Outputs
.rstdiv0 (rst),
.clk (clk),
.clk_div2 (clk_div2),
.rst_div2 (rst_div2),
.mem_refclk (mem_refclk),
.freq_refclk (freq_refclk),
.sync_pulse (sync_pulse),
.mmcm_ps_clk (mmcm_ps_clk),
.poc_sample_pd (poc_sample_pd),
.psdone (psdone),
.iddr_rst (iddr_rst),
// .auxout_clk (),
.ui_addn_clk_0 (),
.ui_addn_clk_1 (),
.ui_addn_clk_2 (),
.ui_addn_clk_3 (),
.ui_addn_clk_4 (),
.pll_locked (pll_locked),
.mmcm_locked (mmcm_locked),
.rst_phaser_ref (rst_phaser_ref),
// Inputs
.psen (psen),
.psincdec (psincdec),
.mmcm_clk (mmcm_clk),
.sys_rst (sys_rst_o),
.iodelay_ctrl_rdy (iodelay_ctrl_rdy),
.ref_dll_lock (ref_dll_lock)
);
mig_7series_v4_0_memc_ui_top_axi #
(
.TCQ (TCQ),
.ADDR_CMD_MODE (ADDR_CMD_MODE),
.AL (AL),
.PAYLOAD_WIDTH (PAYLOAD_WIDTH),
.BANK_WIDTH (BANK_WIDTH),
.BM_CNT_WIDTH (BM_CNT_WIDTH),
.BURST_MODE (BURST_MODE),
.BURST_TYPE (BURST_TYPE),
.CK_WIDTH (CK_WIDTH),
.COL_WIDTH (COL_WIDTH),
.CMD_PIPE_PLUS1 (CMD_PIPE_PLUS1),
.CS_WIDTH (CS_WIDTH),
.nCS_PER_RANK (nCS_PER_RANK),
.CKE_WIDTH (CKE_WIDTH),
.DATA_WIDTH (DATA_WIDTH),
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
.DM_WIDTH (DM_WIDTH),
.DQ_CNT_WIDTH (DQ_CNT_WIDTH),
.DQ_WIDTH (DQ_WIDTH),
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.DQS_WIDTH (DQS_WIDTH),
.DRAM_TYPE (DRAM_TYPE),
.DRAM_WIDTH (DRAM_WIDTH),
.ECC (ECC),
.ECC_WIDTH (ECC_WIDTH),
.ECC_TEST (ECC_TEST),
.MC_ERR_ADDR_WIDTH (MC_ERR_ADDR_WIDTH),
.REFCLK_FREQ (REFCLK_FREQ),
.nAL (nAL),
.nBANK_MACHS (nBANK_MACHS),
.CKE_ODT_AUX (CKE_ODT_AUX),
.nCK_PER_CLK (nCK_PER_CLK),
.ORDERING (ORDERING),
.OUTPUT_DRV (OUTPUT_DRV),
.IBUF_LPWR_MODE (IBUF_LPWR_MODE),
.DATA_IO_IDLE_PWRDWN (DATA_IO_IDLE_PWRDWN),
.BANK_TYPE (BANK_TYPE),
.DATA_IO_PRIM_TYPE (DATA_IO_PRIM_TYPE),
.IODELAY_GRP0 (IODELAY_GRP0),
.REG_CTRL (REG_CTRL),
.RTT_NOM (RTT_NOM),
.CL (CL),
.tCK (tCK),
.tCKE (tCKE),
.tFAW (tFAW),
.tPRDI (tPRDI),
.tRAS (tRAS),
.tRCD (tRCD),
.tREFI (tREFI),
.tRFC (tRFC),
.tRP (tRP),
.tRRD (tRRD),
.tRTP (tRTP),
.tWTR (tWTR),
.tZQI (tZQI),
.tZQCS (tZQCS),
.USER_REFRESH (USER_REFRESH),
.TEMP_MON_EN (TEMP_MON_EN),
.WRLVL (WRLVL),
.DEBUG_PORT (DEBUG_PORT),
.CAL_WIDTH (CAL_WIDTH),
.RANK_WIDTH (RANK_WIDTH),
.RANKS (RANKS),
.ODT_WIDTH (ODT_WIDTH),
.ROW_WIDTH (ROW_WIDTH),
.ADDR_WIDTH (ADDR_WIDTH),
.APP_DATA_WIDTH (APP_DATA_WIDTH),
.APP_MASK_WIDTH (APP_MASK_WIDTH),
.SIM_BYPASS_INIT_CAL (SIM_BYPASS_INIT_CAL),
.BYTE_LANES_B0 (BYTE_LANES_B0),
.BYTE_LANES_B1 (BYTE_LANES_B1),
.BYTE_LANES_B2 (BYTE_LANES_B2),
.BYTE_LANES_B3 (BYTE_LANES_B3),
.BYTE_LANES_B4 (BYTE_LANES_B4),
.DATA_CTL_B0 (DATA_CTL_B0),
.DATA_CTL_B1 (DATA_CTL_B1),
.DATA_CTL_B2 (DATA_CTL_B2),
.DATA_CTL_B3 (DATA_CTL_B3),
.DATA_CTL_B4 (DATA_CTL_B4),
.PHY_0_BITLANES (PHY_0_BITLANES),
.PHY_1_BITLANES (PHY_1_BITLANES),
.PHY_2_BITLANES (PHY_2_BITLANES),
.CK_BYTE_MAP (CK_BYTE_MAP),
.ADDR_MAP (ADDR_MAP),
.BANK_MAP (BANK_MAP),
.CAS_MAP (CAS_MAP),
.CKE_ODT_BYTE_MAP (CKE_ODT_BYTE_MAP),
.CKE_MAP (CKE_MAP),
.ODT_MAP (ODT_MAP),
.CS_MAP (CS_MAP),
.PARITY_MAP (PARITY_MAP),
.RAS_MAP (RAS_MAP),
.WE_MAP (WE_MAP),
.DQS_BYTE_MAP (DQS_BYTE_MAP),
.DATA0_MAP (DATA0_MAP),
.DATA1_MAP (DATA1_MAP),
.DATA2_MAP (DATA2_MAP),
.DATA3_MAP (DATA3_MAP),
.DATA4_MAP (DATA4_MAP),
.DATA5_MAP (DATA5_MAP),
.DATA6_MAP (DATA6_MAP),
.DATA7_MAP (DATA7_MAP),
.DATA8_MAP (DATA8_MAP),
.DATA9_MAP (DATA9_MAP),
.DATA10_MAP (DATA10_MAP),
.DATA11_MAP (DATA11_MAP),
.DATA12_MAP (DATA12_MAP),
.DATA13_MAP (DATA13_MAP),
.DATA14_MAP (DATA14_MAP),
.DATA15_MAP (DATA15_MAP),
.DATA16_MAP (DATA16_MAP),
.DATA17_MAP (DATA17_MAP),
.MASK0_MAP (MASK0_MAP),
.MASK1_MAP (MASK1_MAP),
.CALIB_ROW_ADD (CALIB_ROW_ADD),
.CALIB_COL_ADD (CALIB_COL_ADD),
.CALIB_BA_ADD (CALIB_BA_ADD),
.IDELAY_ADJ ("OFF"),
.FINE_PER_BIT ("OFF"),
.CENTER_COMP_MODE ("OFF"),
.PI_VAL_ADJ ("OFF"),
.SLOT_0_CONFIG (SLOT_0_CONFIG),
.SLOT_1_CONFIG (SLOT_1_CONFIG),
.MEM_ADDR_ORDER (MEM_ADDR_ORDER),
.STARVE_LIMIT (STARVE_LIMIT),
.C_S_AXI_ID_WIDTH (C_S_AXI_ID_WIDTH),
.C_S_AXI_ADDR_WIDTH (C_S_AXI_ADDR_WIDTH),
.C_S_AXI_DATA_WIDTH (C_S_AXI_DATA_WIDTH),
.C_S_AXI_SUPPORTS_NARROW_BURST (C_S_AXI_SUPPORTS_NARROW_BURST),
.C_RD_WR_ARB_ALGORITHM (C_RD_WR_ARB_ALGORITHM),
.C_S_AXI_REG_EN0 (C_S_AXI_REG_EN0),
.C_S_AXI_REG_EN1 (C_S_AXI_REG_EN1),
.C_S_AXI_CTRL_ADDR_WIDTH (C_S_AXI_CTRL_ADDR_WIDTH),
.C_S_AXI_CTRL_DATA_WIDTH (C_S_AXI_CTRL_DATA_WIDTH),
.C_S_AXI_BASEADDR (C_S_AXI_BASEADDR),
.C_ECC_ONOFF_RESET_VALUE (C_ECC_ONOFF_RESET_VALUE),
.C_ECC_CE_COUNTER_WIDTH (C_ECC_CE_COUNTER_WIDTH),
.USE_CS_PORT (USE_CS_PORT),
.USE_DM_PORT (USE_DM_PORT),
.USE_ODT_PORT (USE_ODT_PORT),
.MASTER_PHY_CTL (PHY_CONTROL_MASTER_BANK),
.TAPSPERKCLK (TAPSPERKCLK),
.SKIP_CALIB ("FALSE"),
.FPGA_VOLT_TYPE ("N")
)
u_memc_ui_top_axi
(
.clk (clk),
.clk_div2 (clk_div2),
.rst_div2 (rst_div2),
.clk_ref (clk_ref),
.mem_refclk (mem_refclk), //memory clock
.freq_refclk (freq_refclk),
.pll_lock (pll_locked),
.sync_pulse (sync_pulse),
.mmcm_ps_clk (mmcm_ps_clk),
.poc_sample_pd (poc_sample_pd),
.psdone (psdone),
.iddr_rst (iddr_rst),
.psen (psen),
.psincdec (psincdec),
.rst (rst),
.rst_phaser_ref (rst_phaser_ref),
.ref_dll_lock (ref_dll_lock),
// Memory interface ports
.ddr_dq (ddr2_dq),
.ddr_dqs_n (ddr2_dqs_n),
.ddr_dqs (ddr2_dqs_p),
.ddr_addr (ddr2_addr),
.ddr_ba (ddr2_ba),
.ddr_cas_n (ddr2_cas_n),
.ddr_ck_n (ddr2_ck_n),
.ddr_ck (ddr2_ck_p),
.ddr_cke (ddr2_cke),
.ddr_cs_n (ddr2_cs_n),
.ddr_dm (ddr2_dm),
.ddr_odt (ddr2_odt),
.ddr_ras_n (ddr2_ras_n),
.ddr_reset_n (ddr2_reset_n),
.ddr_parity (ddr2_parity),
.ddr_we_n (ddr2_we_n),
.bank_mach_next (bank_mach_next),
// Application interface ports
.app_ecc_multiple_err_o (),
.app_ecc_single_err (),
.device_temp (device_temp),
.calib_tap_req (),
.calib_tap_load (1'b0),
.calib_tap_addr (7'b0),
.calib_tap_val (8'b0),
.calib_tap_load_done (1'b0),
// Debug logic ports
.dbg_idel_up_all (dbg_idel_up_all),
.dbg_idel_down_all (dbg_idel_down_all),
.dbg_idel_up_cpt (dbg_idel_up_cpt),
.dbg_idel_down_cpt (dbg_idel_down_cpt),
.dbg_sel_idel_cpt (dbg_sel_idel_cpt),
.dbg_sel_all_idel_cpt (dbg_sel_all_idel_cpt),
.dbg_sel_pi_incdec (dbg_sel_pi_incdec),
.dbg_sel_po_incdec (dbg_sel_po_incdec),
.dbg_byte_sel (dbg_byte_sel),
.dbg_pi_f_inc (dbg_pi_f_inc),
.dbg_pi_f_dec (dbg_pi_f_dec),
.dbg_po_f_inc (dbg_po_f_inc),
.dbg_po_f_stg23_sel (dbg_po_f_stg23_sel),
.dbg_po_f_dec (dbg_po_f_dec),
.dbg_cpt_tap_cnt (dbg_cpt_tap_cnt),
.dbg_dq_idelay_tap_cnt (dbg_dq_idelay_tap_cnt),
.dbg_calib_top (dbg_calib_top),
.dbg_cpt_first_edge_cnt (dbg_cpt_first_edge_cnt),
.dbg_cpt_second_edge_cnt (dbg_cpt_second_edge_cnt),
.dbg_rd_data_offset (dbg_rd_data_offset),
.dbg_phy_rdlvl (dbg_phy_rdlvl),
.dbg_phy_wrcal (dbg_phy_wrcal),
.dbg_final_po_fine_tap_cnt (dbg_final_po_fine_tap_cnt),
.dbg_final_po_coarse_tap_cnt (dbg_final_po_coarse_tap_cnt),
.dbg_rd_data_edge_detect (dbg_rd_data_edge_detect),
.dbg_rddata (dbg_rddata),
.dbg_rddata_valid (dbg_rddata_valid),
.dbg_rdlvl_done (dbg_rdlvl_done),
.dbg_rdlvl_err (dbg_rdlvl_err),
.dbg_rdlvl_start (dbg_rdlvl_start),
.dbg_wrlvl_fine_tap_cnt (dbg_wrlvl_fine_tap_cnt),
.dbg_wrlvl_coarse_tap_cnt (dbg_wrlvl_coarse_tap_cnt),
.dbg_tap_cnt_during_wrlvl (dbg_tap_cnt_during_wrlvl),
.dbg_wl_edge_detect_valid (dbg_wl_edge_detect_valid),
.dbg_wrlvl_done (dbg_wrlvl_done),
.dbg_wrlvl_err (dbg_wrlvl_err),
.dbg_wrlvl_start (dbg_wrlvl_start),
.dbg_phy_wrlvl (dbg_phy_wrlvl),
.dbg_phy_init (dbg_phy_init),
.dbg_prbs_rdlvl (dbg_prbs_rdlvl),
.dbg_pi_counter_read_val (dbg_pi_counter_read_val),
.dbg_po_counter_read_val (dbg_po_counter_read_val),
.dbg_prbs_final_dqs_tap_cnt_r (dbg_prbs_final_dqs_tap_cnt_r_int),
.dbg_prbs_first_edge_taps (dbg_prbs_first_edge_taps_int),
.dbg_prbs_second_edge_taps (dbg_prbs_second_edge_taps_int),
.dbg_pi_phaselock_start (dbg_pi_phaselock_start),
.dbg_pi_phaselocked_done (dbg_pi_phaselocked_done),
.dbg_pi_phaselock_err (dbg_pi_phaselock_err),
.dbg_pi_phase_locked_phy4lanes (dbg_pi_phase_locked_phy4lanes),
.dbg_pi_dqsfound_start (dbg_pi_dqsfound_start),
.dbg_pi_dqsfound_done (dbg_pi_dqsfound_done),
.dbg_pi_dqsfound_err (dbg_pi_dqsfound_err),
.dbg_pi_dqs_found_lanes_phy4lanes (dbg_pi_dqs_found_lanes_phy4lanes),
.dbg_calib_rd_data_offset_1 (dbg_calib_rd_data_offset_1),
.dbg_calib_rd_data_offset_2 (dbg_calib_rd_data_offset_2),
.dbg_data_offset (dbg_data_offset),
.dbg_data_offset_1 (dbg_data_offset_1),
.dbg_data_offset_2 (dbg_data_offset_2),
.dbg_wrcal_start (dbg_wrcal_start),
.dbg_wrcal_done (dbg_wrcal_done),
.dbg_wrcal_err (dbg_wrcal_err),
.dbg_phy_oclkdelay_cal (dbg_phy_oclkdelay_cal),
.dbg_oclkdelay_rd_data (dbg_oclkdelay_rd_data),
.dbg_oclkdelay_calib_start (dbg_oclkdelay_calib_start),
.dbg_oclkdelay_calib_done (dbg_oclkdelay_calib_done),
.dbg_dqs_found_cal (dbg_dqs_found_cal),
.aresetn (aresetn),
.app_sr_req (app_sr_req),
.app_sr_active (app_sr_active),
.app_ref_req (app_ref_req),
.app_ref_ack (app_ref_ack),
.app_zq_req (app_zq_req),
.app_zq_ack (app_zq_ack),
// Slave Interface Write Address Ports
.s_axi_awid (s_axi_awid),
.s_axi_awaddr (s_axi_awaddr),
.s_axi_awlen (s_axi_awlen),
.s_axi_awsize (s_axi_awsize),
.s_axi_awburst (s_axi_awburst),
.s_axi_awlock (s_axi_awlock),
.s_axi_awcache (s_axi_awcache),
.s_axi_awprot (s_axi_awprot),
.s_axi_awqos (s_axi_awqos),
.s_axi_awvalid (s_axi_awvalid),
.s_axi_awready (s_axi_awready),
// Slave Interface Write Data Ports
.s_axi_wdata (s_axi_wdata),
.s_axi_wstrb (s_axi_wstrb),
.s_axi_wlast (s_axi_wlast),
.s_axi_wvalid (s_axi_wvalid),
.s_axi_wready (s_axi_wready),
// Slave Interface Write Response Ports
.s_axi_bid (s_axi_bid),
.s_axi_bresp (s_axi_bresp),
.s_axi_bvalid (s_axi_bvalid),
.s_axi_bready (s_axi_bready),
// Slave Interface Read Address Ports
.s_axi_arid (s_axi_arid),
.s_axi_araddr (s_axi_araddr),
.s_axi_arlen (s_axi_arlen),
.s_axi_arsize (s_axi_arsize),
.s_axi_arburst (s_axi_arburst),
.s_axi_arlock (s_axi_arlock),
.s_axi_arcache (s_axi_arcache),
.s_axi_arprot (s_axi_arprot),
.s_axi_arqos (s_axi_arqos),
.s_axi_arvalid (s_axi_arvalid),
.s_axi_arready (s_axi_arready),
// Slave Interface Read Data Ports
.s_axi_rid (s_axi_rid),
.s_axi_rdata (s_axi_rdata),
.s_axi_rresp (s_axi_rresp),
.s_axi_rlast (s_axi_rlast),
.s_axi_rvalid (s_axi_rvalid),
.s_axi_rready (s_axi_rready),
// AXI CTRL port
.s_axi_ctrl_awvalid (s_axi_ctrl_awvalid),
.s_axi_ctrl_awready (s_axi_ctrl_awready),
.s_axi_ctrl_awaddr (s_axi_ctrl_awaddr),
// Slave Interface Write Data Ports
.s_axi_ctrl_wvalid (s_axi_ctrl_wvalid),
.s_axi_ctrl_wready (s_axi_ctrl_wready),
.s_axi_ctrl_wdata (s_axi_ctrl_wdata),
// Slave Interface Write Response Ports
.s_axi_ctrl_bvalid (s_axi_ctrl_bvalid),
.s_axi_ctrl_bready (s_axi_ctrl_bready),
.s_axi_ctrl_bresp (s_axi_ctrl_bresp),
// Slave Interface Read Address Ports
.s_axi_ctrl_arvalid (s_axi_ctrl_arvalid),
.s_axi_ctrl_arready (s_axi_ctrl_arready),
.s_axi_ctrl_araddr (s_axi_ctrl_araddr),
// Slave Interface Read Data Ports
.s_axi_ctrl_rvalid (s_axi_ctrl_rvalid),
.s_axi_ctrl_rready (s_axi_ctrl_rready),
.s_axi_ctrl_rdata (s_axi_ctrl_rdata),
.s_axi_ctrl_rresp (s_axi_ctrl_rresp),
// Interrupt output
.interrupt (interrupt),
.init_calib_complete (init_calib_complete),
.dbg_poc (dbg_poc)
);
//*********************************************************************
// Resetting all RTL debug inputs as the debug ports are not enabled
//*********************************************************************
assign dbg_idel_down_all = 1'b0;
assign dbg_idel_down_cpt = 1'b0;
assign dbg_idel_up_all = 1'b0;
assign dbg_idel_up_cpt = 1'b0;
assign dbg_sel_all_idel_cpt = 1'b0;
assign dbg_sel_idel_cpt = 'b0;
assign dbg_byte_sel = 'd0;
assign dbg_sel_pi_incdec = 1'b0;
assign dbg_pi_f_inc = 1'b0;
assign dbg_pi_f_dec = 1'b0;
assign dbg_po_f_inc = 'b0;
assign dbg_po_f_dec = 'b0;
assign dbg_po_f_stg23_sel = 'b0;
assign dbg_sel_po_incdec = 'b0;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__UDP_DFF_P_BLACKBOX_V
`define SKY130_FD_SC_HDLL__UDP_DFF_P_BLACKBOX_V
/**
* udp_dff$P: Positive edge triggered D flip-flop (Q output UDP).
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__udp_dff$P (
Q ,
D ,
CLK
);
output Q ;
input D ;
input CLK;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__UDP_DFF_P_BLACKBOX_V
|
`timescale 1ns / 1ps
`define clkperiodby2 10
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 05/04/2015 03:46:05 PM
// Design Name:
// Module Name: tb_mac
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module tb_mac;
// Inputs
reg clk;
reg [15 : 0] A, B;
reg sof;
// Outputs
wire [35 : 0] C;
// Instantiate the Unit Under Test (UUT)
MAC mult_acc (
.clk(clk),
.sof(sof),
.A(A),
.B(B),
.C(C)
);
initial begin
// Initialize Inputs
clk = 0;
sof = 0;
A = 0;
B = 0;
#310
sof = 1;
A = 1;
B = 15;
#20
A = 2;
B = 15;
#20
A = 3;
B = 15;
#20
A = 4;
B = 15;
#20
A = 5;
B = 15;
#20
sof = 0;
A = 6;
B = 15;
#20
A = 7;
B = 15;
#20
A = 8;
B = 15;
#20
A = 9;
B = 15;
#20
A = 10;
B = 15;
#20
A = 11;
B = 15;
#20
A = 12;
B = 15;
#20
#100
$stop;
end
always
#`clkperiodby2 clk <= ~clk;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__AND4BB_4_V
`define SKY130_FD_SC_HD__AND4BB_4_V
/**
* and4bb: 4-input AND, first two inputs inverted.
*
* Verilog wrapper for and4bb with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__and4bb.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__and4bb_4 (
X ,
A_N ,
B_N ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B_N ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__and4bb base (
.X(X),
.A_N(A_N),
.B_N(B_N),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__and4bb_4 (
X ,
A_N,
B_N,
C ,
D
);
output X ;
input A_N;
input B_N;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__and4bb base (
.X(X),
.A_N(A_N),
.B_N(B_N),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__AND4BB_4_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUSDRIVERNOVLPSLEEP_FUNCTIONAL_V
`define SKY130_FD_SC_LP__BUSDRIVERNOVLPSLEEP_FUNCTIONAL_V
/**
* busdrivernovlpsleep: Bus driver, enable gates pulldown only,
* non-inverted sleep input (on kapwr rail).
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__busdrivernovlpsleep (
Z ,
A ,
TE_B ,
SLEEP
);
// Module ports
output Z ;
input A ;
input TE_B ;
input SLEEP;
// Local signals
wire nor_teb_SLEEP;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUSDRIVERNOVLPSLEEP_FUNCTIONAL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NAND4BB_PP_SYMBOL_V
`define SKY130_FD_SC_HD__NAND4BB_PP_SYMBOL_V
/**
* nand4bb: 4-input NAND, first two inputs inverted.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__nand4bb (
//# {{data|Data Signals}}
input A_N ,
input B_N ,
input C ,
input D ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__NAND4BB_PP_SYMBOL_V
|
//////////////////////////////////////////////////////////////////////////////////
//
// This file is part of the N64 RGB/YPbPr DAC project.
//
// Copyright (C) 2015-2021 by Peter Bartmann <[email protected]>
//
// N64 RGB/YPbPr DAC is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
//////////////////////////////////////////////////////////////////////////////////
//
// Company: Circuit-Board.de
// Engineer: borti4938
//
// Module Name: n64adv_ppu_top
// Project Name: N64 Advanced RGB/YPbPr DAC Mod
// Target Devices: Cyclone IV: EP4CE10E22
// Cyclone 10 LP: 10CL010YE144
// Tool versions: Altera Quartus Prime
// Description:
//
//////////////////////////////////////////////////////////////////////////////////
module n64adv_ppu_top (
// N64 Video Input
VCLK,
nVRST,
nVDSYNC,
VD_i,
// Misc Information Exchange
PPUState,
ConfigSet,
OSDCLK,
OSD_VSync,
OSDWrVector,
OSDInfo,
// VCLK for video output
USE_VPLL,
VCLK_Tx_select,
VCLK_Tx,
nVRST_Tx,
// Video Output
// nBLANK,
VD_o,
nCSYNC, // nCSYNC and nCSYNC for ADV712x
// Jumper VGA Sync / Filter AddOn
UseVGA_HVSync,
nVSYNC_or_F2,
nHSYNC_or_F1
);
`include "vh/n64adv_cparams.vh"
`include "vh/n64adv_vparams.vh"
`include "vh/n64adv_ppuconfig.vh"
input VCLK;
input nVRST;
input nVDSYNC;
input [color_width_i-1:0] VD_i;
output [12:0] PPUState;
input [68:0] ConfigSet;
input OSDCLK;
output OSD_VSync;
input [24:0] OSDWrVector;
input [ 1:0] OSDInfo;
input USE_VPLL;
output [1:0] VCLK_Tx_select;
input VCLK_Tx;
input nVRST_Tx;
// output reg nBLANK = 1'b0;
output reg [`VDATA_O_CO_SLICE] VD_o = {3*color_width_o{1'b0}};
output reg [ 1:0] nCSYNC = 2'b00;
input UseVGA_HVSync;
output reg nVSYNC_or_F2 = 1'b0;
output reg nHSYNC_or_F1 = 1'b0;
// start of rtl
// parameter
localparam vcnt_width_1x = $clog2(`TOTAL_LINES_PAL_LX1);
localparam hcnt_width_1x = $clog2(`PIXEL_PER_LINE_MAX);
wire [1:0] vinfo_pass; // [1:0] {vmode,n64_480i}
wire palmode, n64_480i;
wire [1:0] OSDInfo_resynced;
wire [68:0] ConfigSet_rxclk_resynced, ConfigSet_txclk_resynced;
wire vdata_valid_w[0:2];
wire [`VDATA_I_SY_SLICE] vdata_w_sy_0;
wire [`VDATA_I_FU_SLICE] vdata_w[1:2];
wire vdata_tp_valid_w;
wire [`VDATA_I_FU_SLICE] vdata_tp_w;
wire vdata_valid_pp_w[0:3];
wire [`VDATA_I_FU_SLICE] vdata21_pp_w[0:1];
wire [`VDATA_O_FU_SLICE] vdata24_pp_w[2:3];
wire [3:0] Sync_pp_o;
wire [20:0] vinfo_mult;
wire [13:0] linex_timing;
wire AutoFilter_w;
reg [ 3:0] cfg_gamma;
reg cfg_testpat, cfg_nvideblur, cfg_n16bit_mode;
reg cfg_exchange_rb_o, cfg_nEN_YPbPr, cfg_nEN_RGsB;
reg cfg_ifix, cfg_SL_method, cfg_SL_id, cfg_SL_en;
reg [ 2:0] cfg_filter;
reg [ 1:0] cfg_linemult;
reg [ 4:0] cfg_SLHyb_str;
reg [ 7:0] cfg_SL_str;
reg cfg_dejitter;
reg [ 6:0] cfg_linex_hshift;
reg [ 5:0] cfg_linex_vshift;
reg [vcnt_width_1x-1:0] cfg_osd_voffset;
reg [hcnt_width_1x-1:0] cfg_osd_hoffset;
reg [1:2] Filter;
// apply some assignments
// ----------------------
assign palmode = vinfo_pass[1];
assign n64_480i = vinfo_pass[0];
assign VCLK_Tx_select = cfg_linemult;
assign vinfo_mult = {cfg_linemult,cfg_ifix,cfg_SLHyb_str,cfg_SL_str,cfg_SL_method,cfg_SL_id,cfg_SL_en,palmode,n64_480i};
assign linex_timing = {cfg_dejitter,cfg_linex_hshift,cfg_linex_vshift};
assign vdata_valid_pp_w[0] = cfg_testpat ? vdata_tp_valid_w : vdata_valid_w[2];
assign vdata21_pp_w[0] = cfg_testpat ? vdata_tp_w : vdata_w[2];
assign Sync_pp_o = vdata24_pp_w[3][`VDATA_O_SY_SLICE];
assign AutoFilter_w = cfg_filter == 3'b000;
assign PPUState[11:0] = {palmode,n64_480i,1'b0,cfg_linemult,~cfg_nEN_YPbPr,~cfg_nEN_RGsB,~cfg_nvideblur,~cfg_n16bit_mode,Filter,AutoFilter_w};
// write configuration register
// ----------------------------
register_sync #(
.reg_width(71),
.reg_preset(71'd0)
) synccfg4rxlogic_u(
.clk(VCLK),
.clk_en(1'b1),
.nrst(1'b1),
.reg_i({OSDInfo,ConfigSet}),
.reg_o({OSDInfo_resynced,ConfigSet_rxclk_resynced})
);
register_sync #(
.reg_width(69),
.reg_preset(69'd0)
) synccfg4txlogic_u(
.clk(VCLK_Tx),
.clk_en(1'b1),
.nrst(1'b1),
.reg_i(ConfigSet),
.reg_o(ConfigSet_txclk_resynced)
);
always @(posedge VCLK) begin
cfg_testpat <= ConfigSet_rxclk_resynced[`show_testpattern_bit];
cfg_gamma <= ConfigSet_rxclk_resynced[`gamma_slice];
cfg_n16bit_mode <= ~ConfigSet_rxclk_resynced[`n16bit_mode_bit];
if (!n64_480i) begin
cfg_nvideblur <= ~ConfigSet_rxclk_resynced[`videblur_bit];
end else begin
cfg_nvideblur <= 1'b1;
end
end
always @(posedge VCLK_Tx) begin
cfg_exchange_rb_o <= ConfigSet_txclk_resynced[`Exchange_RB_out_bit];
cfg_filter <= ConfigSet_txclk_resynced[`FilterSet_slice];
cfg_nEN_YPbPr <= ~ConfigSet_txclk_resynced[`YPbPr_bit];
cfg_nEN_RGsB <= ~ConfigSet_txclk_resynced[`RGsB_bit];
cfg_dejitter <= palmode & ConfigSet_txclk_resynced[`pal_dejitter_bit];
cfg_linex_hshift <= ConfigSet_txclk_resynced[`linex_hshift_slice];
cfg_linex_vshift <= ConfigSet_txclk_resynced[`linex_vshift_slice];
if (!n64_480i) begin
cfg_ifix <= 1'b0;
if (palmode | !USE_VPLL)
cfg_linemult <= {1'b0,^ConfigSet_txclk_resynced[`v240p_linemult_slice]}; // do not allow LineX3 in PAL mode or if PLL of VCLK (for LineX3) is not locked (or not used)
else
cfg_linemult <= ConfigSet_txclk_resynced[`v240p_linemult_slice];
cfg_SLHyb_str <= ConfigSet_txclk_resynced[`v240p_SL_hybrid_slice];
cfg_SL_str <= ((ConfigSet_txclk_resynced[`v240p_SL_str_slice]+8'h01)<<4)-1'b1;
cfg_SL_method <= ConfigSet_txclk_resynced[`v240p_SL_method_bit];
cfg_SL_id <= ConfigSet_txclk_resynced[`v240p_SL_ID_bit];
cfg_SL_en <= ConfigSet_txclk_resynced[`v240p_SL_En_bit];
end else begin
cfg_ifix <= ConfigSet_txclk_resynced[`v480i_field_fix_bit];
cfg_linemult <= {1'b0,ConfigSet_txclk_resynced[`v480i_linex2_bit]};
if (ConfigSet_txclk_resynced[`v480i_SL_linked_bit]) begin // check if SL mode is linked to 240p
cfg_SLHyb_str <= ConfigSet_txclk_resynced[`v240p_SL_hybrid_slice];
cfg_SL_str <= ((ConfigSet_txclk_resynced[`v240p_SL_str_slice]+8'h01)<<4)-1'b1;
cfg_SL_str <= ConfigSet_txclk_resynced[`v240p_SL_str_slice];
cfg_SL_id <= ConfigSet_txclk_resynced[`v240p_SL_ID_bit];
end else begin
cfg_SLHyb_str <= ConfigSet_txclk_resynced[`v480i_SL_hybrid_slice];
cfg_SL_str <= ((ConfigSet_txclk_resynced[`v480i_SL_str_slice]+8'h01)<<4)-1'b1;
cfg_SL_id <= ConfigSet_txclk_resynced[`v480i_SL_ID_bit];
end
cfg_SL_method <= 1'b0;
cfg_SL_en <= ConfigSet_txclk_resynced[`v480i_SL_En_bit];
end
end
// get vinfo
// =========
n64_vinfo_ext get_vinfo_u(
.VCLK(VCLK),
.nVDSYNC(nVDSYNC),
.nRST(nVRST),
.Sync_pre(vdata_w_sy_0),
.Sync_cur(VD_i[3:0]),
.vinfo_o(vinfo_pass)
);
// video data demux
// ================
n64a_vdemux video_demux_u(
.VCLK(VCLK),
.nVDSYNC(nVDSYNC),
.nRST(nVRST),
.VD_i(VD_i),
.demuxparams_i({palmode,cfg_nvideblur,cfg_n16bit_mode}),
.vdata_valid_0(vdata_valid_w[0]),
.vdata_r_sy_0(vdata_w_sy_0),
.vdata_valid_1(vdata_valid_w[1]),
.vdata_r_1(vdata_w[1])
);
// OSD Menu Injection
// ==================
always @(*)
if (!palmode) begin
cfg_osd_voffset <= 60; // (`VSTART_NTSC_LX1 + `ACTIVE_LINES_NTSC_LX1 - `OSD_WINDOW_VACTIVE)/2
// = 18 + (240 - 156)/2 = 60
cfg_osd_hoffset <= 220; // `HSTART_NTSC + (`ACTIVE_PIXEL_PER_LINE - `OSD_WINDOW_HACTIVE)/2
// = 116 + (640-431)/2 = 220,5
end else begin
cfg_osd_voffset <= 87; // (`VSTART_PAL_LX1 + `ACTIVE_LINES_PAL_LX1 - `OSD_WINDOW_VACTIVE)/2
// = 21 + (288 - 156)/2 = 87
cfg_osd_hoffset <= 240; // `HSTART_PAL + (`ACTIVE_PIXEL_PER_LINE - `OSD_WINDOW_HACTIVE)/2
// = 136 + (640-431)/2 = 240,5
end
osd_injection osd_injection_u(
.OSDCLK(OSDCLK),
.OSD_VSync(OSD_VSync),
.OSDWrVector(OSDWrVector),
.OSDInfo(OSDInfo_resynced),
.VCLK(VCLK),
.nVRST(nVRST),
.osd_vscale(3'b000),
.osd_hscale(2'b00),
.osd_voffset(cfg_osd_voffset),
.osd_hoffset(cfg_osd_hoffset),
.vdata_valid_i(vdata_valid_w[1]),
.vdata_i(vdata_w[1]),
.vdata_valid_o(vdata_valid_w[2]),
.vdata_o(vdata_w[2])
);
// Test Pattern Generator
// ======================
testpattern testpattern_u(
.VCLK(VCLK),
.nRST(nVRST),
.palmode(palmode),
.vdata_sync_valid_i(vdata_valid_w[0]),
.vdata_sync_i(vdata_w_sy_0),
.vdata_valid_o(vdata_tp_valid_w),
.vdata_o(vdata_tp_w)
);
// Post-Processing
// ===============
// Gamma Correction
// ----------------
gamma_module gamma_module_u(
.VCLK(VCLK),
.nRST(nVRST),
.gammaparams_i(cfg_gamma),
.vdata_valid_i(vdata_valid_pp_w[0]),
.vdata_i(vdata21_pp_w[0]),
.vdata_valid_o(vdata_valid_pp_w[1]),
.vdata_o(vdata21_pp_w[1])
);
// Line Multiplier
// ---------------
linemult linemult_u(
.VCLK_i(VCLK),
.nVRST_i(nVRST),
.vdata_valid_i(vdata_valid_pp_w[1]),
.vdata_i(vdata21_pp_w[1]),
.vinfo_mult(vinfo_mult),
.linex_timing(linex_timing),
.pal_pattern_fb_o(PPUState[12]),
.VCLK_o(VCLK_Tx),
.nVRST_o(nVRST_Tx),
.vdata_valid_o(vdata_valid_pp_w[2]),
.vdata_o(vdata24_pp_w[2])
);
// Color Transformation
// --------------------
vconv vconv_u(
.VCLK(VCLK_Tx),
.nRST(nVRST_Tx),
.nEN_YPbPr(cfg_nEN_YPbPr), // enables color transformation on '0'
.vdata_valid_i(vdata_valid_pp_w[2]),
.vdata_i(vdata24_pp_w[2]),
.vdata_valid_o(vdata_valid_pp_w[3]),
.vdata_o(vdata24_pp_w[3])
);
// Part 7: assign final outputs
// ============================
//
// Filter AddOn Notes:
// Filter setting from NIOS II core:
// - 000: Auto
// - 001: 9.5MHz
// - 010: 18.0MHz
// - 011: 36.0MHz
// - 100: Bypassed (i.e. 72MHz on non-flex)
//
// FILTER 1 | FILTER 2 | DESCRIPTION
// ---------+----------+--------------------
// 0 | 0 | SD filter ( 9.5MHz)
// 0 | 1 | ED filter (18.0MHz)
// 1 | 0 | HD filter (36.0MHz)
// 1 | 1 | FHD filter (72.0MHz)
//
// (Bypass SF is hard wired to 1)
//
always @(posedge VCLK_Tx or negedge nVRST_Tx)
if (!nVRST_Tx) begin
nVSYNC_or_F2 <= 1'b0;
nHSYNC_or_F1 <= 1'b0;
nCSYNC <= 2'b00;
VD_o <= {3*color_width_o{1'b0}};
end else begin
Filter <= AutoFilter_w ? cfg_linemult : cfg_filter[1:0] - 1'b1;
if (UseVGA_HVSync) begin
if (vdata_valid_pp_w[3]) begin
nVSYNC_or_F2 <= Sync_pp_o[3];
nHSYNC_or_F1 <= Sync_pp_o[1];
end
end else begin
nVSYNC_or_F2 <= Filter[2];
nHSYNC_or_F1 <= Filter[1];
end
if (vdata_valid_pp_w[3]) begin
// nBLANK <= Sync_pp_o[2];
nCSYNC[1] <= Sync_pp_o[0];
if (cfg_nEN_RGsB & cfg_nEN_YPbPr)
nCSYNC[0] <= 1'b0;
else
nCSYNC[0] <= Sync_pp_o[0];
VD_o <= cfg_exchange_rb_o ? {vdata24_pp_w[3][`VDATA_O_BL_SLICE],vdata24_pp_w[3][`VDATA_O_GR_SLICE],vdata24_pp_w[3][`VDATA_O_RE_SLICE]} : vdata24_pp_w[3][`VDATA_O_CO_SLICE];
end;
end
endmodule
|
// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_Mark_Extract_Bits.v
// Created: 2014-09-08 14:12:04
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: controllerHdl_Mark_Extract_Bits
// Source Path: controllerHdl/Encoder_To_Position_And_Velocity/Rotor_To_Electrical_Position/Mod_2pi_Scale_And_Bit_Slice/Mark_Extract_Bits
// Hierarchy Level: 5
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module controllerHdl_Mark_Extract_Bits
(
In1,
Out1
);
input [35:0] In1; // ufix36
output [17:0] Out1; // ufix18
wire [17:0] MATLAB_Function_out1; // ufix18
// <S12>/MATLAB Function
controllerHdl_MATLAB_Function u_MATLAB_Function (.u(In1), // ufix36
.y(MATLAB_Function_out1) // ufix18
);
assign Out1 = MATLAB_Function_out1;
endmodule // controllerHdl_Mark_Extract_Bits
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O21BAI_PP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__O21BAI_PP_BLACKBOX_V
/**
* o21bai: 2-input OR into first input of 2-input NAND, 2nd iput
* inverted.
*
* Y = !((A1 | A2) & !B1_N)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__o21bai (
Y ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O21BAI_PP_BLACKBOX_V
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module dma_core (
// dma interface
dma_clk,
dma_rst,
dma_valid,
dma_last,
dma_data,
dma_ready,
dma_ovf,
dma_unf,
dma_status,
dma_bw,
// data interface
adc_clk,
adc_rst,
adc_valid,
adc_data,
// processor interface
dma_start,
dma_stream,
dma_count);
// parameters
parameter DATA_WIDTH = 64;
localparam DW = DATA_WIDTH - 1;
localparam BUF_THRESHOLD_LO = 6'd3;
localparam BUF_THRESHOLD_HI = 6'd60;
localparam DATA_WIDTH_IN_BYTES = DATA_WIDTH/8;
// dma interface
input dma_clk;
input dma_rst;
output dma_valid;
output dma_last;
output [DW:0] dma_data;
input dma_ready;
output dma_ovf;
output dma_unf;
output dma_status;
output [31:0] dma_bw;
// data interface
input adc_clk;
input adc_rst;
input adc_valid;
input [DW:0] adc_data;
// processor interface
input dma_start;
input dma_stream;
input [31:0] dma_count;
// internal registers
reg dma_valid_int = 'd0;
reg dma_last_int = 'd0;
reg [DW:0] dma_data_int = 'd0;
reg dma_capture_enable = 'd0;
reg [31:0] dma_capture_count = 'd0;
reg dma_rd = 'd0;
reg [ 5:0] dma_raddr = 'd0;
reg dma_release_toggle_m1 = 'd0;
reg dma_release_toggle_m2 = 'd0;
reg dma_release_toggle_m3 = 'd0;
reg [ 5:0] dma_release_waddr = 'd0;
reg [ 5:0] dma_waddr_m1 = 'd0;
reg [ 5:0] dma_waddr_m2 = 'd0;
reg [ 5:0] dma_waddr = 'd0;
reg [ 5:0] dma_addr_diff = 'd0;
reg dma_almost_full = 'd0;
reg dma_almost_empty = 'd0;
reg dma_ovf = 'd0;
reg dma_unf = 'd0;
reg dma_resync = 'd0;
reg adc_wr = 'd0;
reg [ 5:0] adc_waddr = 'd0;
reg [ 5:0] adc_waddr_g = 'd0;
reg [ 3:0] adc_release_count = 'd0;
reg [DW:0] adc_wdata = 'd0;
reg adc_release_toggle = 'd0;
reg [ 5:0] adc_release_waddr = 'd0;
reg adc_resync_m1 = 'd0;
reg adc_resync_m2 = 'd0;
reg adc_resync = 'd0;
// internal signals
wire dma_rd_valid_s;
wire dma_last_s;
wire dma_ready_s;
wire dma_rd_s;
wire dma_release_s;
wire [ 6:0] dma_addr_diff_s;
wire dma_ovf_s;
wire dma_unf_s;
wire [DW:0] dma_rdata_s;
// binary to grey conversion
function [5:0] b2g;
input [5:0] b;
reg [5:0] g;
begin
g[5] = b[5];
g[4] = b[5] ^ b[4];
g[3] = b[4] ^ b[3];
g[2] = b[3] ^ b[2];
g[1] = b[2] ^ b[1];
g[0] = b[1] ^ b[0];
b2g = g;
end
endfunction
// grey to binary conversion
function [5:0] g2b;
input [5:0] g;
reg [5:0] b;
begin
b[5] = g[5];
b[4] = b[5] ^ g[4];
b[3] = b[4] ^ g[3];
b[2] = b[3] ^ g[2];
b[1] = b[2] ^ g[1];
b[0] = b[1] ^ g[0];
g2b = b;
end
endfunction
// dma read- user interface
assign dma_bw = DATA_WIDTH_IN_BYTES;
assign dma_status = dma_capture_enable;
always @(posedge dma_clk) begin
dma_valid_int <= dma_rd_valid_s;
dma_last_int <= dma_last_s;
dma_data_int <= dma_rdata_s;
end
// dma read- capture control signals
assign dma_rd_valid_s = dma_capture_enable & dma_rd;
assign dma_last_s = (dma_capture_count == dma_count) ? dma_rd_valid_s : 1'b0;
always @(posedge dma_clk) begin
if ((dma_stream == 1'b0) && (dma_last_s == 1'b1)) begin
dma_capture_enable <= 1'b0;
end else if (dma_start == 1'b1) begin
dma_capture_enable <= 1'b1;
end
if ((dma_capture_enable == 1'b0) || (dma_last_s == 1'b1)) begin
dma_capture_count <= dma_bw;
end else if (dma_rd == 1'b1) begin
dma_capture_count <= dma_capture_count + dma_bw;
end
end
// dma read- read data always and pass it to the external memory
assign dma_ready_s = (~dma_capture_enable) | dma_ready;
assign dma_rd_s = (dma_release_waddr == dma_raddr) ? 1'b0 : dma_ready_s;
always @(posedge dma_clk) begin
dma_rd <= dma_rd_s;
if ((dma_resync == 1'b1) || (dma_rst == 1'b1)) begin
dma_raddr <= 6'd0;
end else if (dma_rd_s == 1'b1) begin
dma_raddr <= dma_raddr + 1'b1;
end
end
// dma read- get bursts of adc data from the other side
assign dma_release_s = dma_release_toggle_m3 ^ dma_release_toggle_m2;
always @(posedge dma_clk) begin
if (dma_rst == 1'b1) begin
dma_release_toggle_m1 <= 'd0;
dma_release_toggle_m2 <= 'd0;
dma_release_toggle_m3 <= 'd0;
end else begin
dma_release_toggle_m1 <= adc_release_toggle;
dma_release_toggle_m2 <= dma_release_toggle_m1;
dma_release_toggle_m3 <= dma_release_toggle_m2;
end
if (dma_resync == 1'b1) begin
dma_release_waddr <= 6'd0;
end else if (dma_release_s == 1'b1) begin
dma_release_waddr <= adc_release_waddr;
end
end
// dma read- get free running write address for ovf/unf checking
assign dma_addr_diff_s = {1'b1, dma_waddr} - dma_raddr;
assign dma_ovf_s = (dma_addr_diff < BUF_THRESHOLD_LO) ? dma_almost_full : 1'b0;
assign dma_unf_s = (dma_addr_diff > BUF_THRESHOLD_HI) ? dma_almost_empty : 1'b0;
always @(posedge dma_clk) begin
if (dma_rst == 1'b1) begin
dma_waddr_m1 <= 'd0;
dma_waddr_m2 <= 'd0;
end else begin
dma_waddr_m1 <= adc_waddr_g;
dma_waddr_m2 <= dma_waddr_m1;
end
dma_waddr <= g2b(dma_waddr_m2);
dma_addr_diff <= dma_addr_diff_s[5:0];
if (dma_addr_diff > BUF_THRESHOLD_HI) begin
dma_almost_full <= 1'b1;
end else begin
dma_almost_full <= 1'b0;
end
if (dma_addr_diff < BUF_THRESHOLD_LO) begin
dma_almost_empty <= 1'b1;
end else begin
dma_almost_empty <= 1'b0;
end
dma_ovf <= dma_ovf_s;
dma_unf <= dma_unf_s;
dma_resync <= dma_ovf | dma_unf;
end
// adc write- used here to simply transfer data to the dma side
// address is released with a free running counter
always @(posedge adc_clk) begin
adc_wr <= adc_valid;
if ((adc_resync == 1'b1) || (adc_rst == 1'b1)) begin
adc_waddr <= 6'd0;
end else if (adc_wr == 1'b1) begin
adc_waddr <= adc_waddr + 1'b1;
end
adc_waddr_g <= b2g(adc_waddr);
adc_wdata <= adc_data;
adc_release_count <= adc_release_count + 1'b1;
if (adc_release_count == 4'hf) begin
adc_release_toggle <= ~adc_release_toggle;
adc_release_waddr <= adc_waddr;
end
if (adc_rst == 1'b1) begin
adc_resync_m1 <= 'd0;
adc_resync_m2 <= 'd0;
end else begin
adc_resync_m1 <= dma_resync;
adc_resync_m2 <= adc_resync_m1;
end
adc_resync <= adc_resync_m2;
end
// interface handler for ready
axis_inf #(.DATA_WIDTH(DATA_WIDTH)) i_axis_inf (
.clk (dma_clk),
.rst (dma_rst),
.valid (dma_valid_int),
.last (dma_last_int),
.data (dma_data_int),
.inf_valid (dma_valid),
.inf_last (dma_last),
.inf_data (dma_data),
.inf_ready (dma_ready));
// buffer (mainly for clock domain transfer)
mem #(.DATA_WIDTH(DATA_WIDTH), .ADDR_WIDTH(6)) i_mem (
.clka (adc_clk),
.wea (adc_wr),
.addra (adc_waddr),
.dina (adc_wdata),
.clkb (dma_clk),
.addrb (dma_raddr),
.doutb (dma_rdata_s));
endmodule
// ***************************************************************************
// ***************************************************************************
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__MUX2I_1_V
`define SKY130_FD_SC_HD__MUX2I_1_V
/**
* mux2i: 2-input multiplexer, output inverted.
*
* Verilog wrapper for mux2i with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__mux2i.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__mux2i_1 (
Y ,
A0 ,
A1 ,
S ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A0 ;
input A1 ;
input S ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__mux2i base (
.Y(Y),
.A0(A0),
.A1(A1),
.S(S),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__mux2i_1 (
Y ,
A0,
A1,
S
);
output Y ;
input A0;
input A1;
input S ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__mux2i base (
.Y(Y),
.A0(A0),
.A1(A1),
.S(S)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__MUX2I_1_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__TAPVGND_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__TAPVGND_BEHAVIORAL_PP_V
/**
* tapvgnd: Tap cell with tap to ground, isolated power connection 1
* row down.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__tapvgnd (
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
input VPWR;
input VGND;
input VPB ;
input VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__TAPVGND_BEHAVIORAL_PP_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A21BOI_PP_SYMBOL_V
`define SKY130_FD_SC_HDLL__A21BOI_PP_SYMBOL_V
/**
* a21boi: 2-input AND into first input of 2-input NOR,
* 2nd input inverted.
*
* Y = !((A1 & A2) | (!B1_N))
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__a21boi (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1_N,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A21BOI_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O221AI_2_V
`define SKY130_FD_SC_MS__O221AI_2_V
/**
* o221ai: 2-input OR into first two inputs of 3-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2) & C1)
*
* Verilog wrapper for o221ai with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__o221ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o221ai_2 (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__o221ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o221ai_2 (
Y ,
A1,
A2,
B1,
B2,
C1
);
output Y ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__o221ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__O221AI_2_V
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: jbi_ssi_sif.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
/////////////////////////////////////////////////////////////////////////
/*
// Description: SPI block
// Top level Module: jbi_ssi_sif
// Where Instantiated: jbi_ssi
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
`include "sys.h" // system level definition file which contains the
// time scale definition
`include "iop.h"
`include "jbi.h"
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
module jbi_ssi_sif(/*AUTOARG*/
// Outputs
sif_ucbif_timeout, sif_ucbif_timeout_rw, sif_ucbif_par_err,
sif_ucbif_busy, sif_ucbif_rdata, sif_ucbif_rdata_vld,
jbi_io_ssi_mosi, jbi_io_ssi_sck,
// Inputs
clk, rst_l, arst_l, ctu_jbi_ssiclk, ucbif_sif_timeval,
ucbif_sif_timeout_accpt, ucbif_sif_vld, ucbif_sif_rw, ucbif_sif_size,
ucbif_sif_addr, ucbif_sif_wdata, ucbif_sif_rdata_accpt,
io_jbi_ssi_miso
);
////////////////////////////////////////////////////////////////////////
// Interface signal list declarations
////////////////////////////////////////////////////////////////////////
input clk;
input rst_l;
input arst_l;
input ctu_jbi_ssiclk; // jbus clk divided by 4
// CSR
input [`JBI_SSI_CSR_TOUT_TIMEVAL_WIDTH-1:0] ucbif_sif_timeval;
input ucbif_sif_timeout_accpt;
output sif_ucbif_timeout; //assert until accepted
output sif_ucbif_timeout_rw; //timeout of a rd or wr
output sif_ucbif_par_err; //for rd par err, assert until accepted
//issue SSI command
output sif_ucbif_busy;
input ucbif_sif_vld;
input ucbif_sif_rw; //instr w/o data will have no dlen asserted
input [`JBI_SSI_SZ_WIDTH-1:0] ucbif_sif_size;
input [`JBI_SSI_ADDR_WIDTH-1:0] ucbif_sif_addr;
input [63:0] ucbif_sif_wdata;
//read return data
input ucbif_sif_rdata_accpt;
output [63:0] sif_ucbif_rdata;
output sif_ucbif_rdata_vld;
// SSI bus signals
input io_jbi_ssi_miso;
output jbi_io_ssi_mosi;
output jbi_io_ssi_sck;
////////////////////////////////////////////////////////////////////////
// Interface signal type declarations
////////////////////////////////////////////////////////////////////////
wire sif_ucbif_timeout;
wire sif_ucbif_timeout_rw;
wire sif_ucbif_par_err;
wire sif_ucbif_busy;
wire [63:0] sif_ucbif_rdata;
wire sif_ucbif_rdata_vld;
wire jbi_io_ssi_mosi;
wire jbi_io_ssi_sck;
////////////////////////////////////////////////////////////////////////
// Local signal declarations
////////////////////////////////////////////////////////////////////////
//
// Code start here
//
parameter SCK_CYC_CNT_WIDTH = 7;
parameter SSI_IDLE = 3'b000,
SSI_REQ = 3'b001,
SSI_WDATA = 3'b011,
SSI_REQ_PAR = 3'b101,
SSI_ACK = 3'b111,
SSI_RDATA = 3'b110,
SSI_ACK_PAR = 3'b010;
parameter SSI_SM_WIDTH = 3;
wire [63:0] wdata;
wire [2:0] wdata_sel;
wire [1:0] size;
wire rw;
wire [SSI_SM_WIDTH-1:0] ssi_sm;
wire [SCK_CYC_CNT_WIDTH-1:0] sck_cyc_cnt;
wire par;
wire [`JBI_SSI_CSR_TOUT_TIMEVAL_WIDTH-1:0] timeout_cnt;
wire [63:0] next_wdata;
wire [2:0] next_wdata_sel;
wire [1:0] next_size;
wire next_rw;
reg [SSI_SM_WIDTH-1:0] next_ssi_sm;
reg [SCK_CYC_CNT_WIDTH-1:0] next_sck_cyc_cnt;
reg next_par;
wire [`JBI_SSI_CSR_TOUT_TIMEVAL_WIDTH-1:0] next_timeout_cnt;
wire ctu_jbi_ssiclk_ff;
wire ctu_jbi_ssiclk_d1;
reg [63:0] next_sif_ucbif_rdata;
wire next_sif_ucbif_rdata_vld;
wire next_jbi_io_ssi_sck;
reg next_jbi_io_ssi_mosi;
wire next_sif_ucbif_par_err;
wire next_sif_ucbif_timeout;
wire wdata_en;
wire wdata_sel_en;
wire size_en;
wire rw_en;
wire sif_ucbif_rdata_en;
wire par_en;
wire timeout_cnt_en;
wire ssi_sm_rst_l;
wire sck_cyc_cnt_rst_l;
wire par_rst_l;
wire timeout_cnt_rst_l;
wire sif_ucbif_timeout_rst_l;
wire req_info_en;
wire sck_posedge;
wire sck_posedge_d1;
//wire sck_posedge_d2;
//wire sck_negedge;
wire sck_negedge_d1;
wire sck_negedge_d2;
wire [`JBI_SSI_REQ_WIDTH-1:0] ssi_req;
wire mosi_load_n;
reg [63:0] mosi_shreg_din;
wire mosi_shift_n;
reg mosi_wdata_bit;
wire mosi_shreg0_s_in;
wire mosi_shreg1_s_in;
wire mosi_shreg2_s_in;
wire mosi_shreg3_s_in;
wire mosi_shreg4_s_in;
wire mosi_shreg5_s_in;
wire mosi_shreg6_s_in;
wire mosi_shreg7_s_in;
wire [7:0] mosi_shreg0_p_in;
wire [7:0] mosi_shreg1_p_in;
wire [7:0] mosi_shreg2_p_in;
wire [7:0] mosi_shreg3_p_in;
wire [7:0] mosi_shreg4_p_in;
wire [7:0] mosi_shreg5_p_in;
wire [7:0] mosi_shreg6_p_in;
wire [7:0] mosi_shreg7_p_in;
wire [7:0] mosi_shreg0_p_out;
wire [7:0] mosi_shreg1_p_out;
wire [7:0] mosi_shreg2_p_out;
wire [7:0] mosi_shreg3_p_out;
wire [7:0] mosi_shreg4_p_out;
wire [7:0] mosi_shreg5_p_out;
wire [7:0] mosi_shreg6_p_out;
wire [7:0] mosi_shreg7_p_out;
wire rdata_shift_n;
wire [63:0] rdata_shreg;
wire io_jbi_ssi_miso_ff;
wire ack_par_rdy;
//*******************************************************************************
// Accept new request
//*******************************************************************************
assign sif_ucbif_busy = ssi_sm != SSI_IDLE
| sif_ucbif_rdata_vld
| sif_ucbif_timeout
| ~sck_posedge_d1;
assign req_info_en = ucbif_sif_vld & ~sif_ucbif_busy;
// Store command info
assign next_wdata = ucbif_sif_wdata;
assign wdata_en = req_info_en;
assign next_wdata_sel = ucbif_sif_addr[2:0];
assign wdata_sel_en = req_info_en;
assign next_size = ucbif_sif_size;
assign size_en = req_info_en;
assign next_rw = ucbif_sif_rw;
assign rw_en = req_info_en;
//*******************************************************************************
// SSI State Machine
//*******************************************************************************
assign ssi_sm_rst_l = rst_l & ~sif_ucbif_timeout; // stop processing after timeout
always @(/*AUTOSENSE*/io_jbi_ssi_miso_ff or rw or sck_cyc_cnt
or sck_posedge or sck_posedge_d1 or sif_ucbif_timeout or size
or ssi_sm or ucbif_sif_vld) begin
case(ssi_sm)
SSI_IDLE: begin
if (ucbif_sif_vld & sck_posedge_d1) // must line up with mosi
next_ssi_sm = SSI_REQ;
else
next_ssi_sm = SSI_IDLE;
end
SSI_REQ: begin
if (sck_cyc_cnt[5]) begin // == 32 which includes start bit
if (rw)
next_ssi_sm = SSI_REQ_PAR;
else
next_ssi_sm = SSI_WDATA;
end
else
next_ssi_sm = SSI_REQ;
end
SSI_WDATA: begin
if ( (size == `JBI_SSI_SZ_1BYTE & sck_cyc_cnt[3])
| (size == `JBI_SSI_SZ_2BYTE & sck_cyc_cnt[4])
| (size == `JBI_SSI_SZ_4BYTE & sck_cyc_cnt[5])
| (size == `JBI_SSI_SZ_8BYTE & sck_cyc_cnt[6]))
next_ssi_sm = SSI_REQ_PAR;
else
next_ssi_sm = SSI_WDATA;
end
SSI_REQ_PAR: begin
if (sck_cyc_cnt[0])
next_ssi_sm = SSI_ACK;
else
next_ssi_sm = SSI_REQ_PAR;
end
SSI_ACK: begin //sample at posedge of sck period + 4 cycle delay from sck gen to recv
if (sck_posedge & io_jbi_ssi_miso_ff) begin
if (rw)
next_ssi_sm = SSI_RDATA;
else
next_ssi_sm = SSI_ACK_PAR;
end
else if (sif_ucbif_timeout)
next_ssi_sm = SSI_IDLE;
else
next_ssi_sm = SSI_ACK;
end
SSI_RDATA: begin //sample at posedge of sck period + 4 cycle delay from sck gen to recv
if ( (size == `JBI_SSI_SZ_1BYTE & sck_cyc_cnt[3]) //cnt incr @ sck_posedge_d1 but FF miso @ sck_posedge
| (size == `JBI_SSI_SZ_2BYTE & sck_cyc_cnt[4])
| (size == `JBI_SSI_SZ_4BYTE & sck_cyc_cnt[5])
| (size == `JBI_SSI_SZ_8BYTE & sck_cyc_cnt[6]))
next_ssi_sm = SSI_ACK_PAR;
else
next_ssi_sm = SSI_RDATA;
end
SSI_ACK_PAR: begin
if (sck_cyc_cnt[0])
next_ssi_sm = SSI_IDLE;
else
next_ssi_sm = SSI_ACK_PAR;
end
// CoverMeter line_off
default: begin
next_ssi_sm = {SSI_SM_WIDTH{1'bx}};
//synopsys translate_off
$dispmon ("jbi_ssi_sif", 49, "%d %m: ssi_sm = %b", $time, ssi_sm);
//synopsys translate_on
end
// CoverMeter line_on
endcase
end
//*******************************************************************************
// SCK Dependencies
// - ctu_jbi_ssiclk is jbus clk divided by 4
//*******************************************************************************
assign sck_posedge_d1 = ~ctu_jbi_ssiclk_d1 & ctu_jbi_ssiclk_ff;
assign sck_negedge_d1 = ctu_jbi_ssiclk_d1 & ~ctu_jbi_ssiclk_ff;
assign sck_posedge = sck_negedge_d2;
//assign sck_negedge = sck_posedge_d2;
//sck cycle count increments at rising edge of sck
assign sck_cyc_cnt_rst_l = rst_l & ssi_sm == next_ssi_sm; //clear count when jumping into new state
always @(/*AUTOSENSE*/sck_cyc_cnt or sck_negedge_d1 or sck_posedge
or ssi_sm) begin
if ( ( (ssi_sm == SSI_RDATA | ssi_sm == SSI_ACK_PAR) & sck_negedge_d1)
| ( ~(ssi_sm == SSI_RDATA | ssi_sm == SSI_ACK_PAR) & sck_posedge))
next_sck_cyc_cnt = sck_cyc_cnt + 1'b1;
else
next_sck_cyc_cnt = sck_cyc_cnt;
end
assign next_jbi_io_ssi_sck = ctu_jbi_ssiclk_ff;
//*******************************************************************************
// SI generation
//*******************************************************************************
// | 0 | 1 | 2 | 3 | 4 | 5 | 6 |
// __ __ __ __ __ __ __ __
//clk __/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \
// ___________ ___________
//sck __/ \___________/ \_________
// ________ _______________________ _______________
//mosi ________X_________data__________X_______________
// __ _______________________ _____________________
//miso __X_________data__________X_____________________
// ^
// sample miso
// Load miso shift register
assign ssi_req[`JBI_SSI_REQ_ADDR_HI:`JBI_SSI_REQ_ADDR_LO] = ucbif_sif_addr;
assign ssi_req[`JBI_SSI_REQ_SZ_HI:`JBI_SSI_REQ_SZ_LO] = ucbif_sif_size;
assign ssi_req[`JBI_SSI_REQ_RW] = ucbif_sif_rw;
always @(/*AUTOSENSE*/ssi_req or ssi_sm or wdata) begin
if (ssi_sm == SSI_IDLE)
mosi_shreg_din[63:0] = { {33{1'b1}}, ssi_req };
else
mosi_shreg_din[63:0] = wdata;
end
assign mosi_load_n = ~(ssi_sm == SSI_IDLE
| (ssi_sm == SSI_REQ // & next_ssi_sm == SSI_WDATA
& sck_cyc_cnt[5]
& ~rw));
// Advance miso shift register
assign mosi_shift_n = ~(sck_posedge_d1
& (ssi_sm == SSI_REQ | ssi_sm == SSI_WDATA));
// Determine where wdata is to be taken
always @ ( /*AUTOSENSE*/mosi_shreg0_p_out or mosi_shreg1_p_out
or mosi_shreg2_p_out or mosi_shreg3_p_out
or mosi_shreg4_p_out or mosi_shreg5_p_out
or mosi_shreg6_p_out or mosi_shreg7_p_out or wdata_sel) begin
case(wdata_sel)
3'd0: mosi_wdata_bit = mosi_shreg7_p_out[7];
3'd1: mosi_wdata_bit = mosi_shreg6_p_out[7];
3'd2: mosi_wdata_bit = mosi_shreg5_p_out[7];
3'd3: mosi_wdata_bit = mosi_shreg4_p_out[7];
3'd4: mosi_wdata_bit = mosi_shreg3_p_out[7];
3'd5: mosi_wdata_bit = mosi_shreg2_p_out[7];
3'd6: mosi_wdata_bit = mosi_shreg1_p_out[7];
3'd7: mosi_wdata_bit = mosi_shreg0_p_out[7];
// CoverMeter line_off
default: mosi_wdata_bit = 1'bx;
// CoverMeter line_on
endcase
end
// Generate parity
assign par_en = ( sck_posedge_d1 // gen par
& (ssi_sm == SSI_REQ | ssi_sm == SSI_WDATA))
| ( sck_posedge // check par
& (ssi_sm == SSI_ACK | ssi_sm == SSI_RDATA | ssi_sm == SSI_ACK_PAR));
assign par_rst_l = rst_l
& ~( ssi_sm == SSI_IDLE
| ssi_sm == SSI_ACK & ~(sck_posedge & io_jbi_ssi_miso_ff));
always @ ( /*AUTOSENSE*/io_jbi_ssi_miso_ff or next_jbi_io_ssi_mosi
or par or ssi_sm) begin
case (ssi_sm)
SSI_REQ,
SSI_WDATA: next_par = par ^ next_jbi_io_ssi_mosi;
SSI_ACK,
SSI_RDATA,
SSI_ACK_PAR: next_par = par ^ io_jbi_ssi_miso_ff;
default: next_par = 1'b0;
endcase
end
// Output MOSI
always @ ( /*AUTOSENSE*/mosi_shreg3_p_out or mosi_wdata_bit or par
or ssi_sm) begin
case (ssi_sm)
SSI_REQ: next_jbi_io_ssi_mosi = mosi_shreg3_p_out[7]; // include start bit
SSI_WDATA: next_jbi_io_ssi_mosi = mosi_wdata_bit;
SSI_REQ_PAR: next_jbi_io_ssi_mosi = par;
default: next_jbi_io_ssi_mosi = 1'b0;
endcase
end
//------------------
// Shift Registers
//------------------
assign mosi_shreg0_s_in = 1'b0;
assign mosi_shreg1_s_in = mosi_shreg0_p_out[7];
assign mosi_shreg2_s_in = mosi_shreg1_p_out[7];
assign mosi_shreg3_s_in = mosi_shreg2_p_out[7];
assign mosi_shreg4_s_in = mosi_shreg3_p_out[7];
assign mosi_shreg5_s_in = mosi_shreg4_p_out[7];
assign mosi_shreg6_s_in = mosi_shreg5_p_out[7];
assign mosi_shreg7_s_in = mosi_shreg6_p_out[7];
assign mosi_shreg0_p_in = mosi_shreg_din[ 7: 0];
assign mosi_shreg1_p_in = mosi_shreg_din[15: 8];
assign mosi_shreg2_p_in = mosi_shreg_din[23:16];
assign mosi_shreg3_p_in = mosi_shreg_din[31:24];
assign mosi_shreg4_p_in = mosi_shreg_din[39:32];
assign mosi_shreg5_p_in = mosi_shreg_din[47:40];
assign mosi_shreg6_p_in = mosi_shreg_din[55:48];
assign mosi_shreg7_p_in = mosi_shreg_din[63:56];
jbi_shift_8 u_mosi_shreg0 (/*AUTOINST*/
// Outputs
.d_out (mosi_shreg0_p_out), // Templated
// Inputs
.ck (clk),
.ser_in (mosi_shreg0_s_in), // Templated
.d_in (mosi_shreg0_p_in), // Templated
.shift_l(mosi_shift_n), // Templated
.load_l(mosi_load_n)); // Templated
jbi_shift_8 u_mosi_shreg1 (/*AUTOINST*/
// Outputs
.d_out (mosi_shreg1_p_out), // Templated
// Inputs
.ck (clk),
.ser_in (mosi_shreg1_s_in), // Templated
.d_in (mosi_shreg1_p_in), // Templated
.shift_l(mosi_shift_n), // Templated
.load_l(mosi_load_n)); // Templated
jbi_shift_8 u_mosi_shreg2 (/*AUTOINST*/
// Outputs
.d_out (mosi_shreg2_p_out), // Templated
// Inputs
.ck (clk),
.ser_in (mosi_shreg2_s_in), // Templated
.d_in (mosi_shreg2_p_in), // Templated
.shift_l(mosi_shift_n), // Templated
.load_l(mosi_load_n)); // Templated
jbi_shift_8 u_mosi_shreg3 (/*AUTOINST*/
// Outputs
.d_out (mosi_shreg3_p_out), // Templated
// Inputs
.ck (clk),
.ser_in (mosi_shreg3_s_in), // Templated
.d_in (mosi_shreg3_p_in), // Templated
.shift_l(mosi_shift_n), // Templated
.load_l(mosi_load_n)); // Templated
jbi_shift_8 u_mosi_shreg4 (/*AUTOINST*/
// Outputs
.d_out (mosi_shreg4_p_out), // Templated
// Inputs
.ck (clk),
.ser_in (mosi_shreg4_s_in), // Templated
.d_in (mosi_shreg4_p_in), // Templated
.shift_l(mosi_shift_n), // Templated
.load_l(mosi_load_n)); // Templated
jbi_shift_8 u_mosi_shreg5 (/*AUTOINST*/
// Outputs
.d_out (mosi_shreg5_p_out), // Templated
// Inputs
.ck (clk),
.ser_in (mosi_shreg5_s_in), // Templated
.d_in (mosi_shreg5_p_in), // Templated
.shift_l(mosi_shift_n), // Templated
.load_l(mosi_load_n)); // Templated
jbi_shift_8 u_mosi_shreg6 (/*AUTOINST*/
// Outputs
.d_out (mosi_shreg6_p_out), // Templated
// Inputs
.ck (clk),
.ser_in (mosi_shreg6_s_in), // Templated
.d_in (mosi_shreg6_p_in), // Templated
.shift_l(mosi_shift_n), // Templated
.load_l(mosi_load_n)); // Templated
jbi_shift_8 u_mosi_shreg7 (/*AUTOINST*/
// Outputs
.d_out (mosi_shreg7_p_out), // Templated
// Inputs
.ck (clk),
.ser_in (mosi_shreg7_s_in), // Templated
.d_in (mosi_shreg7_p_in), // Templated
.shift_l(mosi_shift_n), // Templated
.load_l(mosi_load_n)); // Templated
//*******************************************************************************
// SO Packing
//*******************************************************************************
assign rdata_shift_n = ~(ssi_sm == SSI_RDATA & sck_posedge);
jbi_shift_64 u_rdata_shreg
(.ck(clk),
.ser_in(io_jbi_ssi_miso_ff),
.d_in({64{1'b0}}),
.shift_l(rdata_shift_n),
.load_l(rst_l),
.d_out(rdata_shreg)
);
// Signal read return data
assign sif_ucbif_rdata_en = ssi_sm == SSI_ACK_PAR;
always @ ( /*AUTOSENSE*/rdata_shreg or size) begin
case (size)
`JBI_SSI_SZ_1BYTE: next_sif_ucbif_rdata = {8{rdata_shreg[7:0]}};
`JBI_SSI_SZ_2BYTE: next_sif_ucbif_rdata = {4{rdata_shreg[15:0]}};
`JBI_SSI_SZ_4BYTE: next_sif_ucbif_rdata = {2{rdata_shreg[31:0]}};
`JBI_SSI_SZ_8BYTE: next_sif_ucbif_rdata = rdata_shreg;
// CoverMeter line_off
default: next_sif_ucbif_rdata = {64{1'bx}};
// CoverMeter line_on
endcase
end
assign next_sif_ucbif_rdata_vld = ack_par_rdy & rw
| (sif_ucbif_rdata_vld
& ~ucbif_sif_rdata_accpt);
//*******************************************************************************
// Error Handling
// - Ack Timeout
// - Parity
//*******************************************************************************
// Timeout
assign timeout_cnt_en = ssi_sm == SSI_ACK;
assign timeout_cnt_rst_l = rst_l & ssi_sm == SSI_ACK;
assign next_timeout_cnt = timeout_cnt + 1'b1;
assign sif_ucbif_timeout_rst_l = rst_l & ~ucbif_sif_timeout_accpt;
assign next_sif_ucbif_timeout = sif_ucbif_timeout | timeout_cnt == ucbif_sif_timeval;
assign sif_ucbif_timeout_rw = rw;
// Parity - even parity
assign ack_par_rdy = ssi_sm == SSI_ACK_PAR & next_ssi_sm != SSI_ACK_PAR;
assign next_sif_ucbif_par_err = ack_par_rdy & next_par
| (sif_ucbif_par_err
& sif_ucbif_rdata_vld
& ~ucbif_sif_rdata_accpt);
//*******************************************************************************
// Async Reset DFFRL Instantiations
//*******************************************************************************
dffrl_async_ns u_dffrl_async_ctu_jbi_ssiclk_ff
( .din (ctu_jbi_ssiclk),
.clk (clk),
.rst_l (arst_l),
.q (ctu_jbi_ssiclk_ff));
dffrl_async_ns #(1) u_dffrl_async_jbi_io_ssi_sck
(.din(next_jbi_io_ssi_sck),
.clk(clk),
.rst_l(arst_l),
.q(jbi_io_ssi_sck)
);
//*******************************************************************************
// DFF Instantiations
//*******************************************************************************
dff_ns #(1) u_dff_io_jbi_ssi_miso_ff
(.din(io_jbi_ssi_miso),
.clk(clk),
.q(io_jbi_ssi_miso_ff)
);
dff_ns #(1) u_dff_ctu_jbi_ssiclk_d1
(.din(ctu_jbi_ssiclk_ff),
.clk(clk),
.q(ctu_jbi_ssiclk_d1)
);
dff_ns #(1) u_dff_sck_negedge_d2
(.din(sck_negedge_d1),
.clk(clk),
.q(sck_negedge_d2)
);
//dff_ns #(1) u_dff_sck_posedge_d2
// (.din(sck_posedge_d1),
// .clk(clk),
// .q(sck_posedge_d2)
// );
//*******************************************************************************
// DFFR Instantiations
//*******************************************************************************
dffrl_ns #(SSI_SM_WIDTH) u_dffrl_ssi_sm
(.din(next_ssi_sm),
.clk(clk),
.rst_l(ssi_sm_rst_l),
.q(ssi_sm)
);
dffrl_ns #(SCK_CYC_CNT_WIDTH) u_dffrl_sck_cyc_cnt
(.din(next_sck_cyc_cnt),
.clk(clk),
.rst_l(sck_cyc_cnt_rst_l),
.q(sck_cyc_cnt)
);
dffrl_ns #(1) u_dffrl_sif_ucbif_rdata_vld
(.din(next_sif_ucbif_rdata_vld),
.clk(clk),
.rst_l(rst_l),
.q(sif_ucbif_rdata_vld)
);
dffrl_ns #(1) u_dffrl_sif_ucbif_timeout
(.din(next_sif_ucbif_timeout),
.clk(clk),
.rst_l(sif_ucbif_timeout_rst_l),
.q(sif_ucbif_timeout)
);
dffrl_ns #(1) u_dffrl_sif_ucbif_par_err
(.din(next_sif_ucbif_par_err),
.clk(clk),
.rst_l(rst_l),
.q(sif_ucbif_par_err)
);
dffrl_ns #(1) u_dffrl_jbi_io_ssi_mosi
(.din(next_jbi_io_ssi_mosi),
.clk(clk),
.rst_l(rst_l),
.q(jbi_io_ssi_mosi)
);
//*******************************************************************************
// DFFRE Instantiations
//*******************************************************************************
dffrle_ns #(1) u_dffrle_rw
(.din(next_rw),
.clk(clk),
.rst_l(rst_l),
.en(rw_en),
.q(rw)
);
dffrle_ns #(2) u_dffrle_size
(.din(next_size),
.clk(clk),
.rst_l(rst_l),
.en(size_en),
.q(size)
);
dffrle_ns #(64) u_dffrle_wdata
(.din(next_wdata),
.clk(clk),
.rst_l(rst_l),
.en(wdata_en),
.q(wdata)
);
dffrle_ns #(3) u_dffrle_wdata_sel
(.din(next_wdata_sel),
.clk(clk),
.rst_l(rst_l),
.en(wdata_sel_en),
.q(wdata_sel)
);
dffrle_ns #(64) u_dffrle_sif_ucbif_rdata
(.din(next_sif_ucbif_rdata),
.clk(clk),
.rst_l(rst_l),
.en(sif_ucbif_rdata_en),
.q(sif_ucbif_rdata)
);
dffrle_ns #(1) u_dffrle_par
(.din(next_par),
.clk(clk),
.rst_l(par_rst_l),
.en(par_en),
.q(par)
);
dffrle_ns #(`JBI_SSI_CSR_TOUT_TIMEVAL_WIDTH) u_dffrle_timeout_cnt
(.din(next_timeout_cnt),
.clk(clk),
.rst_l(timeout_cnt_rst_l),
.en(timeout_cnt_en),
.q(timeout_cnt)
);
endmodule
module jbi_shift_8
(ck, ser_in, d_in, shift_l, load_l, d_out);
input ck; // Clock
input ser_in; // Serial data in
input [7:0] d_in; // Data in
input shift_l; // Shift control Active low
input load_l; // Load control Active low
output [7:0] d_out; // Data out
reg [7:0] d, next_d;
always @(shift_l or load_l or ser_in or d_in or d)
begin
if (load_l == 1'b0) next_d = d_in;
else if (load_l == 1'b1)
begin
if (shift_l == 1'b1) next_d = d;
else if (shift_l == 1'b0)
begin
next_d = {d[6:0],ser_in};
end
else next_d = 8'bxxxx_xxxx;
end
else next_d = 8'bxxxx_xxxx;
end
always @(posedge ck) d <= next_d ;
assign d_out = d;
endmodule
module jbi_shift_64
(ck, ser_in, d_in, shift_l, load_l, d_out);
input ck; // Clock
input ser_in; // Serial data in
input [63:0] d_in; // Data in
input shift_l; // Shift control Active low
input load_l; // Load control Active low
output [63:0] d_out; // Data out
reg [63:0] d, next_d;
always @(shift_l or load_l or ser_in or d_in or d)
begin
if (load_l == 1'b0) next_d = d_in;
else if (load_l == 1'b1)
begin
if (shift_l == 1'b1) next_d = d;
else if (shift_l == 1'b0)
begin
next_d = {d[62:0],ser_in};
end
else next_d = {64{1'bx}};
end
else next_d = {64{1'bx}};
end
always @(posedge ck) d <= next_d ;
assign d_out = d;
endmodule
|
/*
Copyright (c) 2019 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI4-Stream 10GBASE-R frame transmitter (AXI in, 10GBASE-R out)
*/
module axis_baser_tx_64 #
(
parameter DATA_WIDTH = 64,
parameter KEEP_WIDTH = (DATA_WIDTH/8),
parameter HDR_WIDTH = 2,
parameter ENABLE_PADDING = 1,
parameter ENABLE_DIC = 1,
parameter MIN_FRAME_LENGTH = 64,
parameter PTP_PERIOD_NS = 4'h6,
parameter PTP_PERIOD_FNS = 16'h6666,
parameter PTP_TS_ENABLE = 0,
parameter PTP_TS_WIDTH = 96,
parameter PTP_TAG_ENABLE = PTP_TS_ENABLE,
parameter PTP_TAG_WIDTH = 16,
parameter USER_WIDTH = (PTP_TAG_ENABLE ? PTP_TAG_WIDTH : 0) + 1
)
(
input wire clk,
input wire rst,
/*
* AXI input
*/
input wire [DATA_WIDTH-1:0] s_axis_tdata,
input wire [KEEP_WIDTH-1:0] s_axis_tkeep,
input wire s_axis_tvalid,
output wire s_axis_tready,
input wire s_axis_tlast,
input wire [USER_WIDTH-1:0] s_axis_tuser,
/*
* 10GBASE-R encoded interface
*/
output wire [DATA_WIDTH-1:0] encoded_tx_data,
output wire [HDR_WIDTH-1:0] encoded_tx_hdr,
/*
* PTP
*/
input wire [PTP_TS_WIDTH-1:0] ptp_ts,
output wire [PTP_TS_WIDTH-1:0] m_axis_ptp_ts,
output wire [PTP_TAG_WIDTH-1:0] m_axis_ptp_ts_tag,
output wire m_axis_ptp_ts_valid,
/*
* Configuration
*/
input wire [7:0] ifg_delay,
/*
* Status
*/
output wire [1:0] start_packet,
output wire error_underflow
);
// bus width assertions
initial begin
if (DATA_WIDTH != 64) begin
$error("Error: Interface width must be 64");
$finish;
end
if (KEEP_WIDTH * 8 != DATA_WIDTH) begin
$error("Error: Interface requires byte (8-bit) granularity");
$finish;
end
if (HDR_WIDTH != 2) begin
$error("Error: HDR_WIDTH must be 2");
$finish;
end
end
localparam MIN_FL_NOCRC = MIN_FRAME_LENGTH-4;
localparam MIN_FL_NOCRC_MS = MIN_FL_NOCRC & 16'hfff8;
localparam MIN_FL_NOCRC_LS = MIN_FL_NOCRC & 16'h0007;
localparam [7:0]
ETH_PRE = 8'h55,
ETH_SFD = 8'hD5;
localparam [6:0]
CTRL_IDLE = 7'h00,
CTRL_LPI = 7'h06,
CTRL_ERROR = 7'h1e,
CTRL_RES_0 = 7'h2d,
CTRL_RES_1 = 7'h33,
CTRL_RES_2 = 7'h4b,
CTRL_RES_3 = 7'h55,
CTRL_RES_4 = 7'h66,
CTRL_RES_5 = 7'h78;
localparam [3:0]
O_SEQ_OS = 4'h0,
O_SIG_OS = 4'hf;
localparam [1:0]
SYNC_DATA = 2'b10,
SYNC_CTRL = 2'b01;
localparam [7:0]
BLOCK_TYPE_CTRL = 8'h1e, // C7 C6 C5 C4 C3 C2 C1 C0 BT
BLOCK_TYPE_OS_4 = 8'h2d, // D7 D6 D5 O4 C3 C2 C1 C0 BT
BLOCK_TYPE_START_4 = 8'h33, // D7 D6 D5 C3 C2 C1 C0 BT
BLOCK_TYPE_OS_START = 8'h66, // D7 D6 D5 O0 D3 D2 D1 BT
BLOCK_TYPE_OS_04 = 8'h55, // D7 D6 D5 O4 O0 D3 D2 D1 BT
BLOCK_TYPE_START_0 = 8'h78, // D7 D6 D5 D4 D3 D2 D1 BT
BLOCK_TYPE_OS_0 = 8'h4b, // C7 C6 C5 C4 O0 D3 D2 D1 BT
BLOCK_TYPE_TERM_0 = 8'h87, // C7 C6 C5 C4 C3 C2 C1 BT
BLOCK_TYPE_TERM_1 = 8'h99, // C7 C6 C5 C4 C3 C2 D0 BT
BLOCK_TYPE_TERM_2 = 8'haa, // C7 C6 C5 C4 C3 D1 D0 BT
BLOCK_TYPE_TERM_3 = 8'hb4, // C7 C6 C5 C4 D2 D1 D0 BT
BLOCK_TYPE_TERM_4 = 8'hcc, // C7 C6 C5 D3 D2 D1 D0 BT
BLOCK_TYPE_TERM_5 = 8'hd2, // C7 C6 D4 D3 D2 D1 D0 BT
BLOCK_TYPE_TERM_6 = 8'he1, // C7 D5 D4 D3 D2 D1 D0 BT
BLOCK_TYPE_TERM_7 = 8'hff; // D6 D5 D4 D3 D2 D1 D0 BT
localparam [3:0]
OUTPUT_TYPE_IDLE = 4'd0,
OUTPUT_TYPE_ERROR = 4'd1,
OUTPUT_TYPE_START_0 = 4'd2,
OUTPUT_TYPE_START_4 = 4'd3,
OUTPUT_TYPE_DATA = 4'd4,
OUTPUT_TYPE_TERM_0 = 4'd8,
OUTPUT_TYPE_TERM_1 = 4'd9,
OUTPUT_TYPE_TERM_2 = 4'd10,
OUTPUT_TYPE_TERM_3 = 4'd11,
OUTPUT_TYPE_TERM_4 = 4'd12,
OUTPUT_TYPE_TERM_5 = 4'd13,
OUTPUT_TYPE_TERM_6 = 4'd14,
OUTPUT_TYPE_TERM_7 = 4'd15;
localparam [2:0]
STATE_IDLE = 3'd0,
STATE_PAYLOAD = 3'd1,
STATE_PAD = 3'd2,
STATE_FCS_1 = 3'd3,
STATE_FCS_2 = 3'd4,
STATE_IFG = 3'd5,
STATE_WAIT_END = 3'd6;
reg [2:0] state_reg = STATE_IDLE, state_next;
// datapath control signals
reg reset_crc;
reg update_crc;
reg swap_lanes;
reg unswap_lanes;
reg lanes_swapped = 1'b0;
reg [31:0] swap_data = 32'd0;
reg delay_type_valid = 1'b0;
reg [3:0] delay_type = OUTPUT_TYPE_IDLE;
reg [DATA_WIDTH-1:0] s_axis_tdata_masked;
reg [DATA_WIDTH-1:0] s_tdata_reg = {DATA_WIDTH{1'b0}}, s_tdata_next;
reg [7:0] s_tkeep_reg = 8'd0, s_tkeep_next;
reg [DATA_WIDTH-1:0] fcs_output_data_0;
reg [DATA_WIDTH-1:0] fcs_output_data_1;
reg [3:0] fcs_output_type_0;
reg [3:0] fcs_output_type_1;
reg [7:0] ifg_offset;
reg extra_cycle;
reg [15:0] frame_ptr_reg = 16'd0, frame_ptr_next;
reg [7:0] ifg_count_reg = 8'd0, ifg_count_next;
reg [1:0] deficit_idle_count_reg = 2'd0, deficit_idle_count_next;
reg s_axis_tready_reg = 1'b0, s_axis_tready_next;
reg [PTP_TS_WIDTH-1:0] m_axis_ptp_ts_reg = 0, m_axis_ptp_ts_next;
reg [PTP_TAG_WIDTH-1:0] m_axis_ptp_ts_tag_reg = 0, m_axis_ptp_ts_tag_next;
reg m_axis_ptp_ts_valid_reg = 1'b0, m_axis_ptp_ts_valid_next;
reg m_axis_ptp_ts_valid_int_reg = 1'b0, m_axis_ptp_ts_valid_int_next;
reg [31:0] crc_state = 32'hFFFFFFFF;
wire [31:0] crc_next0;
wire [31:0] crc_next1;
wire [31:0] crc_next2;
wire [31:0] crc_next3;
wire [31:0] crc_next4;
wire [31:0] crc_next5;
wire [31:0] crc_next6;
wire [31:0] crc_next7;
reg [DATA_WIDTH-1:0] encoded_tx_data_reg = {{8{CTRL_IDLE}}, BLOCK_TYPE_CTRL};
reg [HDR_WIDTH-1:0] encoded_tx_hdr_reg = SYNC_CTRL;
reg [DATA_WIDTH-1:0] output_data_reg = {DATA_WIDTH{1'b0}}, output_data_next;
reg [3:0] output_type_reg = OUTPUT_TYPE_IDLE, output_type_next;
reg [1:0] start_packet_reg = 2'b00, start_packet_next;
reg error_underflow_reg = 1'b0, error_underflow_next;
assign s_axis_tready = s_axis_tready_reg;
assign encoded_tx_data = encoded_tx_data_reg;
assign encoded_tx_hdr = encoded_tx_hdr_reg;
assign m_axis_ptp_ts = PTP_TS_ENABLE ? m_axis_ptp_ts_reg : 0;
assign m_axis_ptp_ts_tag = PTP_TAG_ENABLE ? m_axis_ptp_ts_tag_reg : 0;
assign m_axis_ptp_ts_valid = PTP_TS_ENABLE || PTP_TAG_ENABLE ? m_axis_ptp_ts_valid_reg : 1'b0;
assign start_packet = start_packet_reg;
assign error_underflow = error_underflow_reg;
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.LFSR_FEED_FORWARD(0),
.REVERSE(1),
.DATA_WIDTH(8),
.STYLE("AUTO")
)
eth_crc_8 (
.data_in(s_tdata_reg[7:0]),
.state_in(crc_state),
.data_out(),
.state_out(crc_next0)
);
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.LFSR_FEED_FORWARD(0),
.REVERSE(1),
.DATA_WIDTH(16),
.STYLE("AUTO")
)
eth_crc_16 (
.data_in(s_tdata_reg[15:0]),
.state_in(crc_state),
.data_out(),
.state_out(crc_next1)
);
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.LFSR_FEED_FORWARD(0),
.REVERSE(1),
.DATA_WIDTH(24),
.STYLE("AUTO")
)
eth_crc_24 (
.data_in(s_tdata_reg[23:0]),
.state_in(crc_state),
.data_out(),
.state_out(crc_next2)
);
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.LFSR_FEED_FORWARD(0),
.REVERSE(1),
.DATA_WIDTH(32),
.STYLE("AUTO")
)
eth_crc_32 (
.data_in(s_tdata_reg[31:0]),
.state_in(crc_state),
.data_out(),
.state_out(crc_next3)
);
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.LFSR_FEED_FORWARD(0),
.REVERSE(1),
.DATA_WIDTH(40),
.STYLE("AUTO")
)
eth_crc_40 (
.data_in(s_tdata_reg[39:0]),
.state_in(crc_state),
.data_out(),
.state_out(crc_next4)
);
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.LFSR_FEED_FORWARD(0),
.REVERSE(1),
.DATA_WIDTH(48),
.STYLE("AUTO")
)
eth_crc_48 (
.data_in(s_tdata_reg[47:0]),
.state_in(crc_state),
.data_out(),
.state_out(crc_next5)
);
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.LFSR_FEED_FORWARD(0),
.REVERSE(1),
.DATA_WIDTH(56),
.STYLE("AUTO")
)
eth_crc_56 (
.data_in(s_tdata_reg[55:0]),
.state_in(crc_state),
.data_out(),
.state_out(crc_next6)
);
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.LFSR_FEED_FORWARD(0),
.REVERSE(1),
.DATA_WIDTH(64),
.STYLE("AUTO")
)
eth_crc_64 (
.data_in(s_tdata_reg[63:0]),
.state_in(crc_state),
.data_out(),
.state_out(crc_next7)
);
function [3:0] keep2count;
input [7:0] k;
casez (k)
8'bzzzzzzz0: keep2count = 4'd0;
8'bzzzzzz01: keep2count = 4'd1;
8'bzzzzz011: keep2count = 4'd2;
8'bzzzz0111: keep2count = 4'd3;
8'bzzz01111: keep2count = 4'd4;
8'bzz011111: keep2count = 4'd5;
8'bz0111111: keep2count = 4'd6;
8'b01111111: keep2count = 4'd7;
8'b11111111: keep2count = 4'd8;
endcase
endfunction
// Mask input data
integer j;
always @* begin
for (j = 0; j < 8; j = j + 1) begin
s_axis_tdata_masked[j*8 +: 8] = s_axis_tkeep[j] ? s_axis_tdata[j*8 +: 8] : 8'd0;
end
end
// FCS cycle calculation
always @* begin
casez (s_tkeep_reg)
8'bzzzzzz01: begin
fcs_output_data_0 = {24'd0, ~crc_next0[31:0], s_tdata_reg[7:0]};
fcs_output_data_1 = 64'd0;
fcs_output_type_0 = OUTPUT_TYPE_TERM_5;
fcs_output_type_1 = OUTPUT_TYPE_IDLE;
ifg_offset = 8'd3;
extra_cycle = 1'b0;
end
8'bzzzzz011: begin
fcs_output_data_0 = {16'd0, ~crc_next1[31:0], s_tdata_reg[15:0]};
fcs_output_data_1 = 64'd0;
fcs_output_type_0 = OUTPUT_TYPE_TERM_6;
fcs_output_type_1 = OUTPUT_TYPE_IDLE;
ifg_offset = 8'd2;
extra_cycle = 1'b0;
end
8'bzzzz0111: begin
fcs_output_data_0 = {8'd0, ~crc_next2[31:0], s_tdata_reg[23:0]};
fcs_output_data_1 = 64'd0;
fcs_output_type_0 = OUTPUT_TYPE_TERM_7;
fcs_output_type_1 = OUTPUT_TYPE_IDLE;
ifg_offset = 8'd1;
extra_cycle = 1'b0;
end
8'bzzz01111: begin
fcs_output_data_0 = {~crc_next3[31:0], s_tdata_reg[31:0]};
fcs_output_data_1 = 64'd0;
fcs_output_type_0 = OUTPUT_TYPE_DATA;
fcs_output_type_1 = OUTPUT_TYPE_TERM_0;
ifg_offset = 8'd8;
extra_cycle = 1'b1;
end
8'bzz011111: begin
fcs_output_data_0 = {~crc_next4[23:0], s_tdata_reg[39:0]};
fcs_output_data_1 = {56'd0, ~crc_next4[31:24]};
fcs_output_type_0 = OUTPUT_TYPE_DATA;
fcs_output_type_1 = OUTPUT_TYPE_TERM_1;
ifg_offset = 8'd7;
extra_cycle = 1'b1;
end
8'bz0111111: begin
fcs_output_data_0 = {~crc_next5[15:0], s_tdata_reg[47:0]};
fcs_output_data_1 = {48'd0, ~crc_next5[31:16]};
fcs_output_type_0 = OUTPUT_TYPE_DATA;
fcs_output_type_1 = OUTPUT_TYPE_TERM_2;
ifg_offset = 8'd6;
extra_cycle = 1'b1;
end
8'b01111111: begin
fcs_output_data_0 = {~crc_next6[7:0], s_tdata_reg[55:0]};
fcs_output_data_1 = {40'd0, ~crc_next6[31:8]};
fcs_output_type_0 = OUTPUT_TYPE_DATA;
fcs_output_type_1 = OUTPUT_TYPE_TERM_3;
ifg_offset = 8'd5;
extra_cycle = 1'b1;
end
8'b11111111: begin
fcs_output_data_0 = s_tdata_reg;
fcs_output_data_1 = {32'd0, ~crc_next7[31:0]};
fcs_output_type_0 = OUTPUT_TYPE_DATA;
fcs_output_type_1 = OUTPUT_TYPE_TERM_4;
ifg_offset = 8'd4;
extra_cycle = 1'b1;
end
default: begin
fcs_output_data_0 = 64'd0;
fcs_output_data_1 = 64'd0;
fcs_output_type_0 = OUTPUT_TYPE_ERROR;
fcs_output_type_1 = OUTPUT_TYPE_ERROR;
ifg_offset = 8'd0;
extra_cycle = 1'b1;
end
endcase
end
always @* begin
state_next = STATE_IDLE;
reset_crc = 1'b0;
update_crc = 1'b0;
swap_lanes = 1'b0;
unswap_lanes = 1'b0;
frame_ptr_next = frame_ptr_reg;
ifg_count_next = ifg_count_reg;
deficit_idle_count_next = deficit_idle_count_reg;
s_axis_tready_next = 1'b0;
s_tdata_next = s_tdata_reg;
s_tkeep_next = s_tkeep_reg;
m_axis_ptp_ts_next = m_axis_ptp_ts_reg;
m_axis_ptp_ts_tag_next = m_axis_ptp_ts_tag_reg;
m_axis_ptp_ts_valid_next = 1'b0;
m_axis_ptp_ts_valid_int_next = 1'b0;
output_data_next = s_tdata_reg;
output_type_next = OUTPUT_TYPE_IDLE;
start_packet_next = 2'b00;
error_underflow_next = 1'b0;
if (m_axis_ptp_ts_valid_int_reg) begin
m_axis_ptp_ts_valid_next = 1'b1;
if (PTP_TS_WIDTH == 96 && $signed({1'b0, m_axis_ptp_ts_reg[45:16]}) - $signed(31'd1000000000) > 0) begin
// ns field rollover
m_axis_ptp_ts_next[45:16] = $signed({1'b0, m_axis_ptp_ts_reg[45:16]}) - $signed(31'd1000000000);
m_axis_ptp_ts_next[95:48] = m_axis_ptp_ts_reg[95:48] + 1;
end
end
case (state_reg)
STATE_IDLE: begin
// idle state - wait for data
frame_ptr_next = 16'd8;
reset_crc = 1'b1;
s_axis_tready_next = 1'b1;
output_data_next = s_tdata_reg;
output_type_next = OUTPUT_TYPE_IDLE;
s_tdata_next = s_axis_tdata_masked;
s_tkeep_next = s_axis_tkeep;
if (s_axis_tvalid) begin
// XGMII start and preamble
if (ifg_count_reg > 8'd0) begin
// need to send more idles - swap lanes
swap_lanes = 1'b1;
if (PTP_TS_WIDTH == 96) begin
m_axis_ptp_ts_next[45:0] = ptp_ts[45:0] + (((PTP_PERIOD_NS * 2**16 + PTP_PERIOD_FNS) * 3) >> 1);
m_axis_ptp_ts_next[95:48] = ptp_ts[95:48];
end else begin
m_axis_ptp_ts_next = ptp_ts + (((PTP_PERIOD_NS * 2**16 + PTP_PERIOD_FNS) * 3) >> 1);
end
m_axis_ptp_ts_tag_next = s_axis_tuser >> 1;
m_axis_ptp_ts_valid_int_next = 1'b1;
start_packet_next = 2'b10;
end else begin
// no more idles - unswap
unswap_lanes = 1'b1;
if (PTP_TS_WIDTH == 96) begin
m_axis_ptp_ts_next[45:0] = ptp_ts[45:0] + (PTP_PERIOD_NS * 2**16 + PTP_PERIOD_FNS);
m_axis_ptp_ts_next[95:48] = ptp_ts[95:48];
end else begin
m_axis_ptp_ts_next = ptp_ts + (PTP_PERIOD_NS * 2**16 + PTP_PERIOD_FNS);
end
m_axis_ptp_ts_tag_next = s_axis_tuser >> 1;
m_axis_ptp_ts_valid_int_next = 1'b1;
start_packet_next = 2'b01;
end
output_data_next = {ETH_SFD, {7{ETH_PRE}}};
output_type_next = OUTPUT_TYPE_START_0;
s_axis_tready_next = 1'b1;
state_next = STATE_PAYLOAD;
end else begin
ifg_count_next = 8'd0;
deficit_idle_count_next = 2'd0;
unswap_lanes = 1'b1;
state_next = STATE_IDLE;
end
end
STATE_PAYLOAD: begin
// transfer payload
update_crc = 1'b1;
s_axis_tready_next = 1'b1;
frame_ptr_next = frame_ptr_reg + 16'd8;
output_data_next = s_tdata_reg;
output_type_next = OUTPUT_TYPE_DATA;
s_tdata_next = s_axis_tdata_masked;
s_tkeep_next = s_axis_tkeep;
if (s_axis_tvalid) begin
if (s_axis_tlast) begin
frame_ptr_next = frame_ptr_reg + keep2count(s_axis_tkeep);
s_axis_tready_next = 1'b0;
if (s_axis_tuser[0]) begin
output_type_next = OUTPUT_TYPE_ERROR;
frame_ptr_next = 16'd0;
ifg_count_next = 8'd8;
state_next = STATE_IFG;
end else begin
s_axis_tready_next = 1'b0;
if (ENABLE_PADDING && (frame_ptr_reg < MIN_FL_NOCRC_MS || (frame_ptr_reg == MIN_FL_NOCRC_MS && keep2count(s_axis_tkeep) < MIN_FL_NOCRC_LS))) begin
s_tkeep_next = 8'hff;
frame_ptr_next = frame_ptr_reg + 16'd8;
if (frame_ptr_reg < (MIN_FL_NOCRC_LS > 0 ? MIN_FL_NOCRC_MS : MIN_FL_NOCRC_MS-8)) begin
state_next = STATE_PAD;
end else begin
s_tkeep_next = 8'hff >> ((8-MIN_FL_NOCRC_LS) % 8);
state_next = STATE_FCS_1;
end
end else begin
state_next = STATE_FCS_1;
end
end
end else begin
state_next = STATE_PAYLOAD;
end
end else begin
// tvalid deassert, fail frame
output_type_next = OUTPUT_TYPE_ERROR;
frame_ptr_next = 16'd0;
ifg_count_next = 8'd8;
error_underflow_next = 1'b1;
state_next = STATE_WAIT_END;
end
end
STATE_PAD: begin
// pad frame to MIN_FRAME_LENGTH
s_axis_tready_next = 1'b0;
output_data_next = s_tdata_reg;
output_type_next = OUTPUT_TYPE_DATA;
s_tdata_next = 64'd0;
s_tkeep_next = 8'hff;
update_crc = 1'b1;
frame_ptr_next = frame_ptr_reg + 16'd8;
if (frame_ptr_reg < (MIN_FL_NOCRC_LS > 0 ? MIN_FL_NOCRC_MS : MIN_FL_NOCRC_MS-8)) begin
state_next = STATE_PAD;
end else begin
s_tkeep_next = 8'hff >> ((8-MIN_FL_NOCRC_LS) % 8);
state_next = STATE_FCS_1;
end
end
STATE_FCS_1: begin
// last cycle
s_axis_tready_next = 1'b0;
output_data_next = fcs_output_data_0;
output_type_next = fcs_output_type_0;
frame_ptr_next = 16'd0;
ifg_count_next = (ifg_delay > 8'd12 ? ifg_delay : 8'd12) - ifg_offset + (lanes_swapped ? 8'd4 : 8'd0) + deficit_idle_count_reg;
if (extra_cycle) begin
state_next = STATE_FCS_2;
end else begin
state_next = STATE_IFG;
end
end
STATE_FCS_2: begin
// last cycle
s_axis_tready_next = 1'b0;
output_data_next = fcs_output_data_1;
output_type_next = fcs_output_type_1;
reset_crc = 1'b1;
frame_ptr_next = 16'd0;
if (ENABLE_DIC) begin
if (ifg_count_next > 8'd7) begin
state_next = STATE_IFG;
end else begin
if (ifg_count_next >= 8'd4) begin
deficit_idle_count_next = ifg_count_next - 8'd4;
end else begin
deficit_idle_count_next = ifg_count_next;
ifg_count_next = 8'd0;
end
s_axis_tready_next = 1'b1;
state_next = STATE_IDLE;
end
end else begin
if (ifg_count_next > 8'd4) begin
state_next = STATE_IFG;
end else begin
s_axis_tready_next = 1'b1;
state_next = STATE_IDLE;
end
end
end
STATE_IFG: begin
// send IFG
if (ifg_count_reg > 8'd8) begin
ifg_count_next = ifg_count_reg - 8'd8;
end else begin
ifg_count_next = 8'd0;
end
reset_crc = 1'b1;
if (ENABLE_DIC) begin
if (ifg_count_next > 8'd7) begin
state_next = STATE_IFG;
end else begin
if (ifg_count_next >= 8'd4) begin
deficit_idle_count_next = ifg_count_next - 8'd4;
end else begin
deficit_idle_count_next = ifg_count_next;
ifg_count_next = 8'd0;
end
s_axis_tready_next = 1'b1;
state_next = STATE_IDLE;
end
end else begin
if (ifg_count_next > 8'd4) begin
state_next = STATE_IFG;
end else begin
s_axis_tready_next = 1'b1;
state_next = STATE_IDLE;
end
end
end
STATE_WAIT_END: begin
// wait for end of frame
s_axis_tready_next = 1'b1;
if (ifg_count_reg > 8'd4) begin
ifg_count_next = ifg_count_reg - 8'd4;
end else begin
ifg_count_next = 8'd0;
end
reset_crc = 1'b1;
if (s_axis_tvalid) begin
if (s_axis_tlast) begin
s_axis_tready_next = 1'b0;
if (ENABLE_DIC) begin
if (ifg_count_next > 8'd7) begin
state_next = STATE_IFG;
end else begin
if (ifg_count_next >= 8'd4) begin
deficit_idle_count_next = ifg_count_next - 8'd4;
end else begin
deficit_idle_count_next = ifg_count_next;
ifg_count_next = 8'd0;
end
s_axis_tready_next = 1'b1;
state_next = STATE_IDLE;
end
end else begin
if (ifg_count_next > 8'd4) begin
state_next = STATE_IFG;
end else begin
s_axis_tready_next = 1'b1;
state_next = STATE_IDLE;
end
end
end else begin
state_next = STATE_WAIT_END;
end
end else begin
state_next = STATE_WAIT_END;
end
end
endcase
end
always @(posedge clk) begin
if (rst) begin
state_reg <= STATE_IDLE;
frame_ptr_reg <= 16'd0;
ifg_count_reg <= 8'd0;
deficit_idle_count_reg <= 2'd0;
s_axis_tready_reg <= 1'b0;
m_axis_ptp_ts_valid_reg <= 1'b0;
m_axis_ptp_ts_valid_int_reg <= 1'b0;
encoded_tx_data_reg <= {{8{CTRL_IDLE}}, BLOCK_TYPE_CTRL};
encoded_tx_hdr_reg <= SYNC_CTRL;
output_data_reg <= {DATA_WIDTH{1'b0}};
output_type_reg <= OUTPUT_TYPE_IDLE;
start_packet_reg <= 2'b00;
error_underflow_reg <= 1'b0;
crc_state <= 32'hFFFFFFFF;
lanes_swapped <= 1'b0;
delay_type_valid <= 1'b0;
delay_type <= OUTPUT_TYPE_IDLE;
end else begin
state_reg <= state_next;
frame_ptr_reg <= frame_ptr_next;
ifg_count_reg <= ifg_count_next;
deficit_idle_count_reg <= deficit_idle_count_next;
s_axis_tready_reg <= s_axis_tready_next;
m_axis_ptp_ts_valid_reg <= m_axis_ptp_ts_valid_next;
m_axis_ptp_ts_valid_int_reg <= m_axis_ptp_ts_valid_int_next;
start_packet_reg <= start_packet_next;
error_underflow_reg <= error_underflow_next;
delay_type_valid <= 1'b0;
if (swap_lanes || (lanes_swapped && !unswap_lanes)) begin
lanes_swapped <= 1'b1;
output_data_reg <= {output_data_next[31:0], swap_data};
if (delay_type_valid) begin
output_type_reg <= delay_type;
end else if (output_type_next == OUTPUT_TYPE_START_0) begin
output_type_reg <= OUTPUT_TYPE_START_4;
end else if (output_type_next[3]) begin
// OUTPUT_TYPE_TERM_*
if (output_type_next[2]) begin
delay_type_valid <= 1'b1;
output_type_reg <= OUTPUT_TYPE_DATA;
end else begin
output_type_reg <= output_type_next ^ 4'd4;
end
end else begin
output_type_reg <= output_type_next;
end
end else begin
lanes_swapped <= 1'b0;
output_data_reg <= output_data_next;
output_type_reg <= output_type_next;
end
case (output_type_reg)
OUTPUT_TYPE_IDLE: begin
encoded_tx_data_reg <= {{8{CTRL_IDLE}}, BLOCK_TYPE_CTRL};
encoded_tx_hdr_reg <= SYNC_CTRL;
end
OUTPUT_TYPE_ERROR: begin
encoded_tx_data_reg <= {{8{CTRL_ERROR}}, BLOCK_TYPE_CTRL};
encoded_tx_hdr_reg <= SYNC_CTRL;
end
OUTPUT_TYPE_START_0: begin
encoded_tx_data_reg <= {output_data_reg[63:8], BLOCK_TYPE_START_0};
encoded_tx_hdr_reg <= SYNC_CTRL;
end
OUTPUT_TYPE_START_4: begin
encoded_tx_data_reg <= {output_data_reg[63:40], 4'd0, {4{CTRL_IDLE}}, BLOCK_TYPE_START_4};
encoded_tx_hdr_reg <= SYNC_CTRL;
end
OUTPUT_TYPE_DATA: begin
encoded_tx_data_reg <= output_data_reg;
encoded_tx_hdr_reg <= SYNC_DATA;
end
OUTPUT_TYPE_TERM_0: begin
encoded_tx_data_reg <= {{7{CTRL_IDLE}}, 7'd0, BLOCK_TYPE_TERM_0};
encoded_tx_hdr_reg <= SYNC_CTRL;
end
OUTPUT_TYPE_TERM_1: begin
encoded_tx_data_reg <= {{6{CTRL_IDLE}}, 6'd0, output_data_reg[7:0], BLOCK_TYPE_TERM_1};
encoded_tx_hdr_reg <= SYNC_CTRL;
end
OUTPUT_TYPE_TERM_2: begin
encoded_tx_data_reg <= {{5{CTRL_IDLE}}, 5'd0, output_data_reg[15:0], BLOCK_TYPE_TERM_2};
encoded_tx_hdr_reg <= SYNC_CTRL;
end
OUTPUT_TYPE_TERM_3: begin
encoded_tx_data_reg <= {{4{CTRL_IDLE}}, 4'd0, output_data_reg[23:0], BLOCK_TYPE_TERM_3};
encoded_tx_hdr_reg <= SYNC_CTRL;
end
OUTPUT_TYPE_TERM_4: begin
encoded_tx_data_reg <= {{3{CTRL_IDLE}}, 3'd0, output_data_reg[31:0], BLOCK_TYPE_TERM_4};
encoded_tx_hdr_reg <= SYNC_CTRL;
end
OUTPUT_TYPE_TERM_5: begin
encoded_tx_data_reg <= {{2{CTRL_IDLE}}, 2'd0, output_data_reg[39:0], BLOCK_TYPE_TERM_5};
encoded_tx_hdr_reg <= SYNC_CTRL;
end
OUTPUT_TYPE_TERM_6: begin
encoded_tx_data_reg <= {{1{CTRL_IDLE}}, 1'd0, output_data_reg[47:0], BLOCK_TYPE_TERM_6};
encoded_tx_hdr_reg <= SYNC_CTRL;
end
OUTPUT_TYPE_TERM_7: begin
encoded_tx_data_reg <= {output_data_reg[55:0], BLOCK_TYPE_TERM_7};
encoded_tx_hdr_reg <= SYNC_CTRL;
end
default: begin
encoded_tx_data_reg <= {{8{CTRL_ERROR}}, BLOCK_TYPE_CTRL};
encoded_tx_hdr_reg <= SYNC_CTRL;
end
endcase
// datapath
if (reset_crc) begin
crc_state <= 32'hFFFFFFFF;
end else if (update_crc) begin
crc_state <= crc_next7;
end
end
s_tdata_reg <= s_tdata_next;
s_tkeep_reg <= s_tkeep_next;
m_axis_ptp_ts_reg <= m_axis_ptp_ts_next;
m_axis_ptp_ts_tag_reg <= m_axis_ptp_ts_tag_next;
swap_data <= output_data_next[63:32];
delay_type <= output_type_next ^ 4'd4;
end
endmodule
|
// (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_protocol_converter:2.1
// IP Revision: 5
(* X_CORE_INFO = "axi_protocol_converter_v2_1_axi_protocol_converter,Vivado 2015.2.1" *)
(* CHECK_LICENSE_TYPE = "design_gpio_led_auto_pc_0,axi_protocol_converter_v2_1_axi_protocol_converter,{}" *)
(* CORE_GENERATION_INFO = "design_gpio_led_auto_pc_0,axi_protocol_converter_v2_1_axi_protocol_converter,{x_ipProduct=Vivado 2015.2.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_protocol_converter,x_ipVersion=2.1,x_ipCoreRevision=5,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_M_AXI_PROTOCOL=2,C_S_AXI_PROTOCOL=1,C_IGNORE_ID=0,C_AXI_ID_WIDTH=12,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=32,C_AXI_SUPPORTS_WRITE=1,C_AXI_SUPPORTS_READ=1,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_TRANSLATION_MODE=2}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_gpio_led_auto_pc_0 (
aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awprot,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arprot,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
input wire [11 : 0] s_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
input wire [3 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
input wire [2 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
input wire [1 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
input wire [1 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
input wire [3 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
input wire [3 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
input wire s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
output wire s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WID" *)
input wire [11 : 0] s_axi_wid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
input wire s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
input wire s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
output wire s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
output wire [11 : 0] s_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
output wire s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
input wire s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
input wire [11 : 0] s_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
input wire [3 : 0] s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
input wire [2 : 0] s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
input wire [1 : 0] s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
input wire [1 : 0] s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
input wire [3 : 0] s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
input wire [3 : 0] s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
input wire s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
output wire s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
output wire [11 : 0] s_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
output wire [31 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
output wire s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
output wire s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
input wire s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output wire [31 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output wire m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input wire m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [31 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
output wire [3 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output wire m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input wire m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input wire m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output wire m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
output wire [31 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
output wire [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
output wire m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
input wire m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
input wire [31 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input wire m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output wire m_axi_rready;
axi_protocol_converter_v2_1_axi_protocol_converter #(
.C_FAMILY("zynq"),
.C_M_AXI_PROTOCOL(2),
.C_S_AXI_PROTOCOL(1),
.C_IGNORE_ID(0),
.C_AXI_ID_WIDTH(12),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(32),
.C_AXI_SUPPORTS_WRITE(1),
.C_AXI_SUPPORTS_READ(1),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_TRANSLATION_MODE(2)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(s_axi_awid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awregion(4'H0),
.s_axi_awqos(s_axi_awqos),
.s_axi_awuser(1'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(s_axi_wid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wuser(1'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(s_axi_bid),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(s_axi_arid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arregion(4'H0),
.s_axi_arqos(s_axi_arqos),
.s_axi_aruser(1'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(s_axi_rid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(),
.m_axi_awqos(),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(12'H000),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(),
.m_axi_arqos(),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(12'H000),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(1'H1),
.m_axi_ruser(1'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__AND3_SYMBOL_V
`define SKY130_FD_SC_MS__AND3_SYMBOL_V
/**
* and3: 3-input AND.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__and3 (
//# {{data|Data Signals}}
input A,
input B,
input C,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__AND3_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O2BB2AI_SYMBOL_V
`define SKY130_FD_SC_HDLL__O2BB2AI_SYMBOL_V
/**
* o2bb2ai: 2-input NAND and 2-input OR into 2-input NAND.
*
* Y = !(!(A1 & A2) & (B1 | B2))
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__o2bb2ai (
//# {{data|Data Signals}}
input A1_N,
input A2_N,
input B1 ,
input B2 ,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O2BB2AI_SYMBOL_V
|
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* FPGA core logic
*/
module fpga_core #
(
parameter TARGET = "GENERIC"
)
(
/*
* Clock: 125MHz
* Synchronous reset
*/
input wire clk,
input wire clk90,
input wire rst,
/*
* GPIO
*/
input wire [3:0] btn,
input wire [2:0] sw,
output wire [3:0] led,
/*
* Ethernet: 1000BASE-T RGMII
*/
input wire phy_rx_clk,
input wire [3:0] phy_rxd,
input wire phy_rx_ctl,
output wire phy_tx_clk,
output wire [3:0] phy_txd,
output wire phy_tx_ctl,
output wire phy_reset_n,
input wire phy_int_n
);
// AXI between MAC and Ethernet modules
wire [7:0] rx_axis_tdata;
wire rx_axis_tvalid;
wire rx_axis_tready;
wire rx_axis_tlast;
wire rx_axis_tuser;
wire [7:0] tx_axis_tdata;
wire tx_axis_tvalid;
wire tx_axis_tready;
wire tx_axis_tlast;
wire tx_axis_tuser;
// Ethernet frame between Ethernet modules and UDP stack
wire rx_eth_hdr_ready;
wire rx_eth_hdr_valid;
wire [47:0] rx_eth_dest_mac;
wire [47:0] rx_eth_src_mac;
wire [15:0] rx_eth_type;
wire [7:0] rx_eth_payload_axis_tdata;
wire rx_eth_payload_axis_tvalid;
wire rx_eth_payload_axis_tready;
wire rx_eth_payload_axis_tlast;
wire rx_eth_payload_axis_tuser;
wire tx_eth_hdr_ready;
wire tx_eth_hdr_valid;
wire [47:0] tx_eth_dest_mac;
wire [47:0] tx_eth_src_mac;
wire [15:0] tx_eth_type;
wire [7:0] tx_eth_payload_axis_tdata;
wire tx_eth_payload_axis_tvalid;
wire tx_eth_payload_axis_tready;
wire tx_eth_payload_axis_tlast;
wire tx_eth_payload_axis_tuser;
// IP frame connections
wire rx_ip_hdr_valid;
wire rx_ip_hdr_ready;
wire [47:0] rx_ip_eth_dest_mac;
wire [47:0] rx_ip_eth_src_mac;
wire [15:0] rx_ip_eth_type;
wire [3:0] rx_ip_version;
wire [3:0] rx_ip_ihl;
wire [5:0] rx_ip_dscp;
wire [1:0] rx_ip_ecn;
wire [15:0] rx_ip_length;
wire [15:0] rx_ip_identification;
wire [2:0] rx_ip_flags;
wire [12:0] rx_ip_fragment_offset;
wire [7:0] rx_ip_ttl;
wire [7:0] rx_ip_protocol;
wire [15:0] rx_ip_header_checksum;
wire [31:0] rx_ip_source_ip;
wire [31:0] rx_ip_dest_ip;
wire [7:0] rx_ip_payload_axis_tdata;
wire rx_ip_payload_axis_tvalid;
wire rx_ip_payload_axis_tready;
wire rx_ip_payload_axis_tlast;
wire rx_ip_payload_axis_tuser;
wire tx_ip_hdr_valid;
wire tx_ip_hdr_ready;
wire [5:0] tx_ip_dscp;
wire [1:0] tx_ip_ecn;
wire [15:0] tx_ip_length;
wire [7:0] tx_ip_ttl;
wire [7:0] tx_ip_protocol;
wire [31:0] tx_ip_source_ip;
wire [31:0] tx_ip_dest_ip;
wire [7:0] tx_ip_payload_axis_tdata;
wire tx_ip_payload_axis_tvalid;
wire tx_ip_payload_axis_tready;
wire tx_ip_payload_axis_tlast;
wire tx_ip_payload_axis_tuser;
// UDP frame connections
wire rx_udp_hdr_valid;
wire rx_udp_hdr_ready;
wire [47:0] rx_udp_eth_dest_mac;
wire [47:0] rx_udp_eth_src_mac;
wire [15:0] rx_udp_eth_type;
wire [3:0] rx_udp_ip_version;
wire [3:0] rx_udp_ip_ihl;
wire [5:0] rx_udp_ip_dscp;
wire [1:0] rx_udp_ip_ecn;
wire [15:0] rx_udp_ip_length;
wire [15:0] rx_udp_ip_identification;
wire [2:0] rx_udp_ip_flags;
wire [12:0] rx_udp_ip_fragment_offset;
wire [7:0] rx_udp_ip_ttl;
wire [7:0] rx_udp_ip_protocol;
wire [15:0] rx_udp_ip_header_checksum;
wire [31:0] rx_udp_ip_source_ip;
wire [31:0] rx_udp_ip_dest_ip;
wire [15:0] rx_udp_source_port;
wire [15:0] rx_udp_dest_port;
wire [15:0] rx_udp_length;
wire [15:0] rx_udp_checksum;
wire [7:0] rx_udp_payload_axis_tdata;
wire rx_udp_payload_axis_tvalid;
wire rx_udp_payload_axis_tready;
wire rx_udp_payload_axis_tlast;
wire rx_udp_payload_axis_tuser;
wire tx_udp_hdr_valid;
wire tx_udp_hdr_ready;
wire [5:0] tx_udp_ip_dscp;
wire [1:0] tx_udp_ip_ecn;
wire [7:0] tx_udp_ip_ttl;
wire [31:0] tx_udp_ip_source_ip;
wire [31:0] tx_udp_ip_dest_ip;
wire [15:0] tx_udp_source_port;
wire [15:0] tx_udp_dest_port;
wire [15:0] tx_udp_length;
wire [15:0] tx_udp_checksum;
wire [7:0] tx_udp_payload_axis_tdata;
wire tx_udp_payload_axis_tvalid;
wire tx_udp_payload_axis_tready;
wire tx_udp_payload_axis_tlast;
wire tx_udp_payload_axis_tuser;
wire [7:0] rx_fifo_udp_payload_axis_tdata;
wire rx_fifo_udp_payload_axis_tvalid;
wire rx_fifo_udp_payload_axis_tready;
wire rx_fifo_udp_payload_axis_tlast;
wire rx_fifo_udp_payload_axis_tuser;
wire [7:0] tx_fifo_udp_payload_axis_tdata;
wire tx_fifo_udp_payload_axis_tvalid;
wire tx_fifo_udp_payload_axis_tready;
wire tx_fifo_udp_payload_axis_tlast;
wire tx_fifo_udp_payload_axis_tuser;
// Configuration
wire [47:0] local_mac = 48'h02_00_00_00_00_00;
wire [31:0] local_ip = {8'd192, 8'd168, 8'd1, 8'd128};
wire [31:0] gateway_ip = {8'd192, 8'd168, 8'd1, 8'd1};
wire [31:0] subnet_mask = {8'd255, 8'd255, 8'd255, 8'd0};
// IP ports not used
assign rx_ip_hdr_ready = 1;
assign rx_ip_payload_axis_tready = 1;
assign tx_ip_hdr_valid = 0;
assign tx_ip_dscp = 0;
assign tx_ip_ecn = 0;
assign tx_ip_length = 0;
assign tx_ip_ttl = 0;
assign tx_ip_protocol = 0;
assign tx_ip_source_ip = 0;
assign tx_ip_dest_ip = 0;
assign tx_ip_payload_axis_tdata = 0;
assign tx_ip_payload_axis_tvalid = 0;
assign tx_ip_payload_axis_tlast = 0;
assign tx_ip_payload_axis_tuser = 0;
// Loop back UDP
wire match_cond = rx_udp_dest_port == 1234;
wire no_match = !match_cond;
reg match_cond_reg = 0;
reg no_match_reg = 0;
always @(posedge clk) begin
if (rst) begin
match_cond_reg <= 0;
no_match_reg <= 0;
end else begin
if (rx_udp_payload_axis_tvalid) begin
if ((!match_cond_reg && !no_match_reg) ||
(rx_udp_payload_axis_tvalid && rx_udp_payload_axis_tready && rx_udp_payload_axis_tlast)) begin
match_cond_reg <= match_cond;
no_match_reg <= no_match;
end
end else begin
match_cond_reg <= 0;
no_match_reg <= 0;
end
end
end
assign tx_udp_hdr_valid = rx_udp_hdr_valid && match_cond;
assign rx_udp_hdr_ready = (tx_eth_hdr_ready && match_cond) || no_match;
assign tx_udp_ip_dscp = 0;
assign tx_udp_ip_ecn = 0;
assign tx_udp_ip_ttl = 64;
assign tx_udp_ip_source_ip = local_ip;
assign tx_udp_ip_dest_ip = rx_udp_ip_source_ip;
assign tx_udp_source_port = rx_udp_dest_port;
assign tx_udp_dest_port = rx_udp_source_port;
assign tx_udp_length = rx_udp_length;
assign tx_udp_checksum = 0;
assign tx_udp_payload_axis_tdata = tx_fifo_udp_payload_axis_tdata;
assign tx_udp_payload_axis_tvalid = tx_fifo_udp_payload_axis_tvalid;
assign tx_fifo_udp_payload_axis_tready = tx_udp_payload_axis_tready;
assign tx_udp_payload_axis_tlast = tx_fifo_udp_payload_axis_tlast;
assign tx_udp_payload_axis_tuser = tx_fifo_udp_payload_axis_tuser;
assign rx_fifo_udp_payload_axis_tdata = rx_udp_payload_axis_tdata;
assign rx_fifo_udp_payload_axis_tvalid = rx_udp_payload_axis_tvalid && match_cond_reg;
assign rx_udp_payload_axis_tready = (rx_fifo_udp_payload_axis_tready && match_cond_reg) || no_match_reg;
assign rx_fifo_udp_payload_axis_tlast = rx_udp_payload_axis_tlast;
assign rx_fifo_udp_payload_axis_tuser = rx_udp_payload_axis_tuser;
// Place first payload byte onto LEDs
reg valid_last = 0;
reg [7:0] led_reg = 0;
always @(posedge clk) begin
if (tx_udp_payload_axis_tvalid) begin
if (!valid_last) begin
led_reg <= tx_udp_payload_axis_tdata;
valid_last <= 1'b1;
end
if (tx_udp_payload_axis_tlast) begin
valid_last <= 1'b0;
end
end
if (rst) begin
led_reg <= 0;
end
end
//assign led = sw;
assign led = led_reg;
assign phy_reset_n = ~rst;
eth_mac_1g_rgmii_fifo #(
.TARGET(TARGET),
.USE_CLK90("TRUE"),
.ENABLE_PADDING(1),
.MIN_FRAME_LENGTH(64),
.TX_FIFO_DEPTH(4096),
.TX_FRAME_FIFO(1),
.RX_FIFO_DEPTH(4096),
.RX_FRAME_FIFO(1)
)
eth_mac_inst (
.gtx_clk(clk),
.gtx_clk90(clk90),
.gtx_rst(rst),
.logic_clk(clk),
.logic_rst(rst),
.tx_axis_tdata(tx_axis_tdata),
.tx_axis_tvalid(tx_axis_tvalid),
.tx_axis_tready(tx_axis_tready),
.tx_axis_tlast(tx_axis_tlast),
.tx_axis_tuser(tx_axis_tuser),
.rx_axis_tdata(rx_axis_tdata),
.rx_axis_tvalid(rx_axis_tvalid),
.rx_axis_tready(rx_axis_tready),
.rx_axis_tlast(rx_axis_tlast),
.rx_axis_tuser(rx_axis_tuser),
.rgmii_rx_clk(phy_rx_clk),
.rgmii_rxd(phy_rxd),
.rgmii_rx_ctl(phy_rx_ctl),
.rgmii_tx_clk(phy_tx_clk),
.rgmii_txd(phy_txd),
.rgmii_tx_ctl(phy_tx_ctl),
.tx_fifo_overflow(),
.tx_fifo_bad_frame(),
.tx_fifo_good_frame(),
.rx_error_bad_frame(),
.rx_error_bad_fcs(),
.rx_fifo_overflow(),
.rx_fifo_bad_frame(),
.rx_fifo_good_frame(),
.speed(),
.ifg_delay(12)
);
eth_axis_rx
eth_axis_rx_inst (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(rx_axis_tdata),
.s_axis_tvalid(rx_axis_tvalid),
.s_axis_tready(rx_axis_tready),
.s_axis_tlast(rx_axis_tlast),
.s_axis_tuser(rx_axis_tuser),
// Ethernet frame output
.m_eth_hdr_valid(rx_eth_hdr_valid),
.m_eth_hdr_ready(rx_eth_hdr_ready),
.m_eth_dest_mac(rx_eth_dest_mac),
.m_eth_src_mac(rx_eth_src_mac),
.m_eth_type(rx_eth_type),
.m_eth_payload_axis_tdata(rx_eth_payload_axis_tdata),
.m_eth_payload_axis_tvalid(rx_eth_payload_axis_tvalid),
.m_eth_payload_axis_tready(rx_eth_payload_axis_tready),
.m_eth_payload_axis_tlast(rx_eth_payload_axis_tlast),
.m_eth_payload_axis_tuser(rx_eth_payload_axis_tuser),
// Status signals
.busy(),
.error_header_early_termination()
);
eth_axis_tx
eth_axis_tx_inst (
.clk(clk),
.rst(rst),
// Ethernet frame input
.s_eth_hdr_valid(tx_eth_hdr_valid),
.s_eth_hdr_ready(tx_eth_hdr_ready),
.s_eth_dest_mac(tx_eth_dest_mac),
.s_eth_src_mac(tx_eth_src_mac),
.s_eth_type(tx_eth_type),
.s_eth_payload_axis_tdata(tx_eth_payload_axis_tdata),
.s_eth_payload_axis_tvalid(tx_eth_payload_axis_tvalid),
.s_eth_payload_axis_tready(tx_eth_payload_axis_tready),
.s_eth_payload_axis_tlast(tx_eth_payload_axis_tlast),
.s_eth_payload_axis_tuser(tx_eth_payload_axis_tuser),
// AXI output
.m_axis_tdata(tx_axis_tdata),
.m_axis_tvalid(tx_axis_tvalid),
.m_axis_tready(tx_axis_tready),
.m_axis_tlast(tx_axis_tlast),
.m_axis_tuser(tx_axis_tuser),
// Status signals
.busy()
);
udp_complete
udp_complete_inst (
.clk(clk),
.rst(rst),
// Ethernet frame input
.s_eth_hdr_valid(rx_eth_hdr_valid),
.s_eth_hdr_ready(rx_eth_hdr_ready),
.s_eth_dest_mac(rx_eth_dest_mac),
.s_eth_src_mac(rx_eth_src_mac),
.s_eth_type(rx_eth_type),
.s_eth_payload_axis_tdata(rx_eth_payload_axis_tdata),
.s_eth_payload_axis_tvalid(rx_eth_payload_axis_tvalid),
.s_eth_payload_axis_tready(rx_eth_payload_axis_tready),
.s_eth_payload_axis_tlast(rx_eth_payload_axis_tlast),
.s_eth_payload_axis_tuser(rx_eth_payload_axis_tuser),
// Ethernet frame output
.m_eth_hdr_valid(tx_eth_hdr_valid),
.m_eth_hdr_ready(tx_eth_hdr_ready),
.m_eth_dest_mac(tx_eth_dest_mac),
.m_eth_src_mac(tx_eth_src_mac),
.m_eth_type(tx_eth_type),
.m_eth_payload_axis_tdata(tx_eth_payload_axis_tdata),
.m_eth_payload_axis_tvalid(tx_eth_payload_axis_tvalid),
.m_eth_payload_axis_tready(tx_eth_payload_axis_tready),
.m_eth_payload_axis_tlast(tx_eth_payload_axis_tlast),
.m_eth_payload_axis_tuser(tx_eth_payload_axis_tuser),
// IP frame input
.s_ip_hdr_valid(tx_ip_hdr_valid),
.s_ip_hdr_ready(tx_ip_hdr_ready),
.s_ip_dscp(tx_ip_dscp),
.s_ip_ecn(tx_ip_ecn),
.s_ip_length(tx_ip_length),
.s_ip_ttl(tx_ip_ttl),
.s_ip_protocol(tx_ip_protocol),
.s_ip_source_ip(tx_ip_source_ip),
.s_ip_dest_ip(tx_ip_dest_ip),
.s_ip_payload_axis_tdata(tx_ip_payload_axis_tdata),
.s_ip_payload_axis_tvalid(tx_ip_payload_axis_tvalid),
.s_ip_payload_axis_tready(tx_ip_payload_axis_tready),
.s_ip_payload_axis_tlast(tx_ip_payload_axis_tlast),
.s_ip_payload_axis_tuser(tx_ip_payload_axis_tuser),
// IP frame output
.m_ip_hdr_valid(rx_ip_hdr_valid),
.m_ip_hdr_ready(rx_ip_hdr_ready),
.m_ip_eth_dest_mac(rx_ip_eth_dest_mac),
.m_ip_eth_src_mac(rx_ip_eth_src_mac),
.m_ip_eth_type(rx_ip_eth_type),
.m_ip_version(rx_ip_version),
.m_ip_ihl(rx_ip_ihl),
.m_ip_dscp(rx_ip_dscp),
.m_ip_ecn(rx_ip_ecn),
.m_ip_length(rx_ip_length),
.m_ip_identification(rx_ip_identification),
.m_ip_flags(rx_ip_flags),
.m_ip_fragment_offset(rx_ip_fragment_offset),
.m_ip_ttl(rx_ip_ttl),
.m_ip_protocol(rx_ip_protocol),
.m_ip_header_checksum(rx_ip_header_checksum),
.m_ip_source_ip(rx_ip_source_ip),
.m_ip_dest_ip(rx_ip_dest_ip),
.m_ip_payload_axis_tdata(rx_ip_payload_axis_tdata),
.m_ip_payload_axis_tvalid(rx_ip_payload_axis_tvalid),
.m_ip_payload_axis_tready(rx_ip_payload_axis_tready),
.m_ip_payload_axis_tlast(rx_ip_payload_axis_tlast),
.m_ip_payload_axis_tuser(rx_ip_payload_axis_tuser),
// UDP frame input
.s_udp_hdr_valid(tx_udp_hdr_valid),
.s_udp_hdr_ready(tx_udp_hdr_ready),
.s_udp_ip_dscp(tx_udp_ip_dscp),
.s_udp_ip_ecn(tx_udp_ip_ecn),
.s_udp_ip_ttl(tx_udp_ip_ttl),
.s_udp_ip_source_ip(tx_udp_ip_source_ip),
.s_udp_ip_dest_ip(tx_udp_ip_dest_ip),
.s_udp_source_port(tx_udp_source_port),
.s_udp_dest_port(tx_udp_dest_port),
.s_udp_length(tx_udp_length),
.s_udp_checksum(tx_udp_checksum),
.s_udp_payload_axis_tdata(tx_udp_payload_axis_tdata),
.s_udp_payload_axis_tvalid(tx_udp_payload_axis_tvalid),
.s_udp_payload_axis_tready(tx_udp_payload_axis_tready),
.s_udp_payload_axis_tlast(tx_udp_payload_axis_tlast),
.s_udp_payload_axis_tuser(tx_udp_payload_axis_tuser),
// UDP frame output
.m_udp_hdr_valid(rx_udp_hdr_valid),
.m_udp_hdr_ready(rx_udp_hdr_ready),
.m_udp_eth_dest_mac(rx_udp_eth_dest_mac),
.m_udp_eth_src_mac(rx_udp_eth_src_mac),
.m_udp_eth_type(rx_udp_eth_type),
.m_udp_ip_version(rx_udp_ip_version),
.m_udp_ip_ihl(rx_udp_ip_ihl),
.m_udp_ip_dscp(rx_udp_ip_dscp),
.m_udp_ip_ecn(rx_udp_ip_ecn),
.m_udp_ip_length(rx_udp_ip_length),
.m_udp_ip_identification(rx_udp_ip_identification),
.m_udp_ip_flags(rx_udp_ip_flags),
.m_udp_ip_fragment_offset(rx_udp_ip_fragment_offset),
.m_udp_ip_ttl(rx_udp_ip_ttl),
.m_udp_ip_protocol(rx_udp_ip_protocol),
.m_udp_ip_header_checksum(rx_udp_ip_header_checksum),
.m_udp_ip_source_ip(rx_udp_ip_source_ip),
.m_udp_ip_dest_ip(rx_udp_ip_dest_ip),
.m_udp_source_port(rx_udp_source_port),
.m_udp_dest_port(rx_udp_dest_port),
.m_udp_length(rx_udp_length),
.m_udp_checksum(rx_udp_checksum),
.m_udp_payload_axis_tdata(rx_udp_payload_axis_tdata),
.m_udp_payload_axis_tvalid(rx_udp_payload_axis_tvalid),
.m_udp_payload_axis_tready(rx_udp_payload_axis_tready),
.m_udp_payload_axis_tlast(rx_udp_payload_axis_tlast),
.m_udp_payload_axis_tuser(rx_udp_payload_axis_tuser),
// Status signals
.ip_rx_busy(),
.ip_tx_busy(),
.udp_rx_busy(),
.udp_tx_busy(),
.ip_rx_error_header_early_termination(),
.ip_rx_error_payload_early_termination(),
.ip_rx_error_invalid_header(),
.ip_rx_error_invalid_checksum(),
.ip_tx_error_payload_early_termination(),
.ip_tx_error_arp_failed(),
.udp_rx_error_header_early_termination(),
.udp_rx_error_payload_early_termination(),
.udp_tx_error_payload_early_termination(),
// Configuration
.local_mac(local_mac),
.local_ip(local_ip),
.gateway_ip(gateway_ip),
.subnet_mask(subnet_mask),
.clear_arp_cache(0)
);
axis_fifo #(
.DEPTH(8192),
.DATA_WIDTH(8),
.KEEP_ENABLE(0),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(1),
.FRAME_FIFO(0)
)
udp_payload_fifo (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(rx_fifo_udp_payload_axis_tdata),
.s_axis_tkeep(0),
.s_axis_tvalid(rx_fifo_udp_payload_axis_tvalid),
.s_axis_tready(rx_fifo_udp_payload_axis_tready),
.s_axis_tlast(rx_fifo_udp_payload_axis_tlast),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(rx_fifo_udp_payload_axis_tuser),
// AXI output
.m_axis_tdata(tx_fifo_udp_payload_axis_tdata),
.m_axis_tkeep(),
.m_axis_tvalid(tx_fifo_udp_payload_axis_tvalid),
.m_axis_tready(tx_fifo_udp_payload_axis_tready),
.m_axis_tlast(tx_fifo_udp_payload_axis_tlast),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(tx_fifo_udp_payload_axis_tuser),
// Status
.status_overflow(),
.status_bad_frame(),
.status_good_frame()
);
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
// Date : Thu Oct 26 22:45:02 2017
// Host : Juice-Laptop running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/RATCPU/Experiments/Experiment7-Its_Alive/IPI-BD/RAT/ip/RAT_Counter10bit_0_0/RAT_Counter10bit_0_0_stub.v
// Design : RAT_Counter10bit_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "Counter10bit,Vivado 2016.4" *)
module RAT_Counter10bit_0_0(Din, LOAD, INC, RESET, CLK, COUNT)
/* synthesis syn_black_box black_box_pad_pin="Din[0:9],LOAD,INC,RESET,CLK,COUNT[0:9]" */;
input [0:9]Din;
input LOAD;
input INC;
input RESET;
input CLK;
output [0:9]COUNT;
endmodule
|
//altpll_avalon avalon_use_separate_sysclk="NO" CBX_SINGLE_OUTPUT_FILE="ON" CBX_SUBMODULE_USED_PORTS="altpll:areset,clk,locked,inclk" address areset c0 c1 clk locked phasedone read readdata reset write writedata bandwidth_type="AUTO" clk0_divide_by=1 clk0_duty_cycle=50 clk0_multiply_by=1 clk0_phase_shift="-3000" clk1_divide_by=5 clk1_duty_cycle=50 clk1_multiply_by=1 clk1_phase_shift="0" compensate_clock="CLK0" device_family="CYCLONEIVE" inclk0_input_frequency=20000 intended_device_family="Cyclone IV E" operation_mode="normal" pll_type="AUTO" port_clk0="PORT_USED" port_clk1="PORT_USED" port_clk2="PORT_UNUSED" port_clk3="PORT_UNUSED" port_clk4="PORT_UNUSED" port_clk5="PORT_UNUSED" port_extclk0="PORT_UNUSED" port_extclk1="PORT_UNUSED" port_extclk2="PORT_UNUSED" port_extclk3="PORT_UNUSED" port_inclk1="PORT_UNUSED" port_phasecounterselect="PORT_UNUSED" port_phasedone="PORT_UNUSED" port_scandata="PORT_UNUSED" port_scandataout="PORT_UNUSED" width_clock=5
//VERSION_BEGIN 14.0 cbx_altclkbuf 2014:06:17:18:06:03:SJ cbx_altiobuf_bidir 2014:06:17:18:06:03:SJ cbx_altiobuf_in 2014:06:17:18:06:03:SJ cbx_altiobuf_out 2014:06:17:18:06:03:SJ cbx_altpll 2014:06:17:18:06:03:SJ cbx_altpll_avalon 2014:06:17:18:06:03:SJ cbx_cycloneii 2014:06:17:18:06:03:SJ cbx_lpm_add_sub 2014:06:17:18:06:03:SJ cbx_lpm_compare 2014:06:17:18:06:03:SJ cbx_lpm_counter 2014:06:17:18:06:03:SJ cbx_lpm_decode 2014:06:17:18:06:03:SJ cbx_lpm_mux 2014:06:17:18:06:03:SJ cbx_lpm_shiftreg 2014:06:17:18:06:03:SJ cbx_mgl 2014:06:17:18:10:38:SJ cbx_stratix 2014:06:17:18:06:03:SJ cbx_stratixii 2014:06:17:18:06:03:SJ cbx_stratixiii 2014:06:17:18:06:03:SJ cbx_stratixv 2014:06:17:18:06:03:SJ cbx_util_mgl 2014:06:17:18:06:03:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
// Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, the Altera Quartus II License Agreement,
// the Altera MegaCore Function License Agreement, or other
// applicable license agreement, including, without limitation,
// that your use is for the sole purpose of programming logic
// devices manufactured by Altera and sold by Altera or its
// authorized distributors. Please refer to the applicable
// agreement for further details.
//altera_std_synchronizer CBX_SINGLE_OUTPUT_FILE="ON" clk din dout reset_n
//VERSION_BEGIN 14.0 cbx_mgl 2014:06:17:18:10:38:SJ cbx_stratixii 2014:06:17:18:06:03:SJ cbx_util_mgl 2014:06:17:18:06:03:SJ VERSION_END
//dffpipe CBX_SINGLE_OUTPUT_FILE="ON" DELAY=3 WIDTH=1 clock clrn d q ALTERA_INTERNAL_OPTIONS=AUTO_SHIFT_REGISTER_RECOGNITION=OFF
//VERSION_BEGIN 14.0 cbx_mgl 2014:06:17:18:10:38:SJ cbx_stratixii 2014:06:17:18:06:03:SJ cbx_util_mgl 2014:06:17:18:06:03:SJ VERSION_END
//synthesis_resources = reg 3
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
(* ALTERA_ATTRIBUTE = {"AUTO_SHIFT_REGISTER_RECOGNITION=OFF"} *)
module usb_system_clocks_dffpipe_l2c
(
clock,
clrn,
d,
q) /* synthesis synthesis_clearbox=1 */;
input clock;
input clrn;
input [0:0] d;
output [0:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 clock;
tri1 clrn;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
reg [0:0] dffe4a;
reg [0:0] dffe5a;
reg [0:0] dffe6a;
wire ena;
wire prn;
wire sclr;
// synopsys translate_off
initial
dffe4a = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe4a <= {1{1'b1}};
else if (clrn == 1'b0) dffe4a <= 1'b0;
else if (ena == 1'b1) dffe4a <= (d & (~ sclr));
// synopsys translate_off
initial
dffe5a = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe5a <= {1{1'b1}};
else if (clrn == 1'b0) dffe5a <= 1'b0;
else if (ena == 1'b1) dffe5a <= (dffe4a & (~ sclr));
// synopsys translate_off
initial
dffe6a = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe6a <= {1{1'b1}};
else if (clrn == 1'b0) dffe6a <= 1'b0;
else if (ena == 1'b1) dffe6a <= (dffe5a & (~ sclr));
assign
ena = 1'b1,
prn = 1'b1,
q = dffe6a,
sclr = 1'b0;
endmodule //usb_system_clocks_dffpipe_l2c
//synthesis_resources = reg 3
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module usb_system_clocks_stdsync_sv6
(
clk,
din,
dout,
reset_n) /* synthesis synthesis_clearbox=1 */;
input clk;
input din;
output dout;
input reset_n;
wire [0:0] wire_dffpipe3_q;
usb_system_clocks_dffpipe_l2c dffpipe3
(
.clock(clk),
.clrn(reset_n),
.d(din),
.q(wire_dffpipe3_q));
assign
dout = wire_dffpipe3_q;
endmodule //usb_system_clocks_stdsync_sv6
//altpll bandwidth_type="AUTO" CBX_SINGLE_OUTPUT_FILE="ON" clk0_divide_by=1 clk0_duty_cycle=50 clk0_multiply_by=1 clk0_phase_shift="-3000" clk1_divide_by=5 clk1_duty_cycle=50 clk1_multiply_by=1 clk1_phase_shift="0" compensate_clock="CLK0" device_family="CYCLONEIVE" inclk0_input_frequency=20000 intended_device_family="Cyclone IV E" operation_mode="normal" pll_type="AUTO" port_clk0="PORT_USED" port_clk1="PORT_USED" port_clk2="PORT_UNUSED" port_clk3="PORT_UNUSED" port_clk4="PORT_UNUSED" port_clk5="PORT_UNUSED" port_extclk0="PORT_UNUSED" port_extclk1="PORT_UNUSED" port_extclk2="PORT_UNUSED" port_extclk3="PORT_UNUSED" port_inclk1="PORT_UNUSED" port_phasecounterselect="PORT_UNUSED" port_phasedone="PORT_UNUSED" port_scandata="PORT_UNUSED" port_scandataout="PORT_UNUSED" width_clock=5 areset clk inclk locked
//VERSION_BEGIN 14.0 cbx_altclkbuf 2014:06:17:18:06:03:SJ cbx_altiobuf_bidir 2014:06:17:18:06:03:SJ cbx_altiobuf_in 2014:06:17:18:06:03:SJ cbx_altiobuf_out 2014:06:17:18:06:03:SJ cbx_altpll 2014:06:17:18:06:03:SJ cbx_cycloneii 2014:06:17:18:06:03:SJ cbx_lpm_add_sub 2014:06:17:18:06:03:SJ cbx_lpm_compare 2014:06:17:18:06:03:SJ cbx_lpm_counter 2014:06:17:18:06:03:SJ cbx_lpm_decode 2014:06:17:18:06:03:SJ cbx_lpm_mux 2014:06:17:18:06:03:SJ cbx_mgl 2014:06:17:18:10:38:SJ cbx_stratix 2014:06:17:18:06:03:SJ cbx_stratixii 2014:06:17:18:06:03:SJ cbx_stratixiii 2014:06:17:18:06:03:SJ cbx_stratixv 2014:06:17:18:06:03:SJ cbx_util_mgl 2014:06:17:18:06:03:SJ VERSION_END
//synthesis_resources = cycloneive_pll 1 reg 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
(* ALTERA_ATTRIBUTE = {"SUPPRESS_DA_RULE_INTERNAL=C104;SUPPRESS_DA_RULE_INTERNAL=R101"} *)
module usb_system_clocks_altpll_pqa2
(
areset,
clk,
inclk,
locked) /* synthesis synthesis_clearbox=1 */;
input areset;
output [4:0] clk;
input [1:0] inclk;
output locked;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
tri0 [1:0] inclk;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
reg pll_lock_sync;
wire [4:0] wire_pll7_clk;
wire wire_pll7_fbout;
wire wire_pll7_locked;
// synopsys translate_off
initial
pll_lock_sync = 0;
// synopsys translate_on
always @ ( posedge wire_pll7_locked or posedge areset)
if (areset == 1'b1) pll_lock_sync <= 1'b0;
else pll_lock_sync <= 1'b1;
cycloneive_pll pll7
(
.activeclock(),
.areset(areset),
.clk(wire_pll7_clk),
.clkbad(),
.fbin(wire_pll7_fbout),
.fbout(wire_pll7_fbout),
.inclk(inclk),
.locked(wire_pll7_locked),
.phasedone(),
.scandataout(),
.scandone(),
.vcooverrange(),
.vcounderrange()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clkswitch(1'b0),
.configupdate(1'b0),
.pfdena(1'b1),
.phasecounterselect({3{1'b0}}),
.phasestep(1'b0),
.phaseupdown(1'b0),
.scanclk(1'b0),
.scanclkena(1'b1),
.scandata(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
pll7.bandwidth_type = "auto",
pll7.clk0_divide_by = 1,
pll7.clk0_duty_cycle = 50,
pll7.clk0_multiply_by = 1,
pll7.clk0_phase_shift = "-3000",
pll7.clk1_divide_by = 5,
pll7.clk1_duty_cycle = 50,
pll7.clk1_multiply_by = 1,
pll7.clk1_phase_shift = "0",
pll7.compensate_clock = "clk0",
pll7.inclk0_input_frequency = 20000,
pll7.operation_mode = "normal",
pll7.pll_type = "auto",
pll7.lpm_type = "cycloneive_pll";
assign
clk = {wire_pll7_clk[4:0]},
locked = (wire_pll7_locked & pll_lock_sync);
endmodule //usb_system_clocks_altpll_pqa2
//synthesis_resources = cycloneive_pll 1 reg 6
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module usb_system_clocks
(
address,
areset,
c0,
c1,
clk,
locked,
phasedone,
read,
readdata,
reset,
write,
writedata) /* synthesis synthesis_clearbox=1 */;
input [1:0] address;
input areset;
output c0;
output c1;
input clk;
output locked;
output phasedone;
input read;
output [31:0] readdata;
input reset;
input write;
input [31:0] writedata;
wire wire_stdsync2_dout;
wire [4:0] wire_sd1_clk;
wire wire_sd1_locked;
(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=HIGH"} *)
reg pfdena_reg;
wire wire_pfdena_reg_ena;
reg prev_reset;
wire w_locked;
wire w_pfdena;
wire w_phasedone;
wire w_pll_areset_in;
wire w_reset;
wire w_select_control;
wire w_select_status;
usb_system_clocks_stdsync_sv6 stdsync2
(
.clk(clk),
.din(wire_sd1_locked),
.dout(wire_stdsync2_dout),
.reset_n((~ reset)));
usb_system_clocks_altpll_pqa2 sd1
(
.areset((w_pll_areset_in | areset)),
.clk(wire_sd1_clk),
.inclk({{1{1'b0}}, clk}),
.locked(wire_sd1_locked));
// synopsys translate_off
initial
pfdena_reg = {1{1'b1}};
// synopsys translate_on
always @ ( posedge clk or posedge reset)
if (reset == 1'b1) pfdena_reg <= {1{1'b1}};
else if (wire_pfdena_reg_ena == 1'b1) pfdena_reg <= writedata[1];
assign
wire_pfdena_reg_ena = (write & w_select_control);
// synopsys translate_off
initial
prev_reset = 0;
// synopsys translate_on
always @ ( posedge clk or posedge reset)
if (reset == 1'b1) prev_reset <= 1'b0;
else prev_reset <= w_reset;
assign
c0 = wire_sd1_clk[0],
c1 = wire_sd1_clk[1],
locked = wire_sd1_locked,
phasedone = 1'b0,
readdata = {{30{1'b0}}, (read & ((w_select_control & w_pfdena) | (w_select_status & w_phasedone))), (read & ((w_select_control & w_pll_areset_in) | (w_select_status & w_locked)))},
w_locked = wire_stdsync2_dout,
w_pfdena = pfdena_reg,
w_phasedone = 1'b1,
w_pll_areset_in = prev_reset,
w_reset = ((write & w_select_control) & writedata[0]),
w_select_control = ((~ address[1]) & address[0]),
w_select_status = ((~ address[1]) & (~ address[0]));
endmodule //usb_system_clocks
//VALID FILE
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Thu Nov 3 18:18:04 2016
/////////////////////////////////////////////////////////////
module FPU_PIPELINED_FPADDSUB_W64_EW11_SW52_SWR55_EWR6 ( clk, rst, beg_OP,
Data_X, Data_Y, add_subt, busy, overflow_flag, underflow_flag,
zero_flag, ready, final_result_ieee );
input [63:0] Data_X;
input [63:0] Data_Y;
output [63:0] final_result_ieee;
input clk, rst, beg_OP, add_subt;
output busy, overflow_flag, underflow_flag, zero_flag, ready;
wire n4087, Shift_reg_FLAGS_7_6, Shift_reg_FLAGS_7_5, intAS, SIGN_FLAG_EXP,
OP_FLAG_EXP, ZERO_FLAG_EXP, SIGN_FLAG_SHT1, OP_FLAG_SHT1,
ZERO_FLAG_SHT1, ADD_OVRFLW_NRM, left_right_SHT2, bit_shift_SHT2,
SIGN_FLAG_SHT2, OP_FLAG_SHT2, ZERO_FLAG_SHT2, ADD_OVRFLW_NRM2,
SIGN_FLAG_SHT1SHT2, ZERO_FLAG_SHT1SHT2, SIGN_FLAG_NRM, ZERO_FLAG_NRM,
SIGN_FLAG_SFG, ZERO_FLAG_SFG, inst_FSM_INPUT_ENABLE_state_next_1_,
n1102, n1103, n1104, n1105, n1106, n1107, n1108, n1109, n1110, n1111,
n1112, n1113, n1114, n1115, n1116, n1117, n1118, n1119, n1120, n1121,
n1122, n1123, n1124, n1125, n1126, n1127, n1128, n1129, n1130, n1131,
n1132, n1133, n1134, n1135, n1136, n1137, n1138, n1139, n1140, n1141,
n1142, n1143, n1144, n1145, n1146, n1147, n1148, n1149, n1150, n1151,
n1152, n1153, n1154, n1155, n1156, n1157, n1158, n1159, n1160, n1161,
n1162, n1163, n1164, n1165, n1166, n1167, n1168, n1169, n1170, n1171,
n1172, n1173, n1174, n1175, n1176, n1177, n1178, n1179, n1180, n1181,
n1182, n1183, n1184, n1185, n1186, n1187, n1188, n1189, n1190, n1191,
n1192, n1193, n1194, n1195, n1196, n1197, n1198, n1199, n1200, n1201,
n1202, n1203, n1204, n1205, n1206, n1207, n1208, n1209, n1210, n1211,
n1212, n1213, n1214, n1215, n1216, n1217, n1218, n1219, n1220, n1221,
n1222, n1223, n1224, n1225, n1226, n1227, n1228, n1229, n1230, n1231,
n1232, n1233, n1234, n1235, n1236, n1237, n1238, n1239, n1240, n1241,
n1242, n1243, n1244, n1245, n1246, n1247, n1248, n1249, n1250, n1251,
n1252, n1253, n1254, n1255, n1256, n1257, n1258, n1259, n1260, n1261,
n1262, n1263, n1264, n1265, n1266, n1267, n1268, n1269, n1270, n1271,
n1272, n1273, n1274, n1275, n1276, n1277, n1278, n1279, n1280, n1281,
n1282, n1283, n1284, n1285, n1286, n1287, n1288, n1289, n1290, n1291,
n1292, n1293, n1294, n1295, n1296, n1297, n1298, n1299, n1300, n1301,
n1302, n1303, n1304, n1305, n1306, n1307, n1308, n1309, n1310, n1311,
n1312, n1313, n1314, n1315, n1316, n1317, n1318, n1319, n1320, n1321,
n1322, n1323, n1324, n1325, n1326, n1327, n1328, n1329, n1330, n1331,
n1332, n1333, n1334, n1335, n1336, n1337, n1338, n1339, n1340, n1341,
n1342, n1343, n1344, n1345, n1346, n1347, n1348, n1349, n1350, n1351,
n1352, n1353, n1354, n1355, n1356, n1357, n1358, n1359, n1360, n1361,
n1362, n1363, n1364, n1365, n1366, n1367, n1368, n1369, n1370, n1371,
n1372, n1373, n1374, n1375, n1376, n1377, n1378, n1379, n1380, n1381,
n1382, n1383, n1384, n1385, n1386, n1387, n1388, n1389, n1390, n1391,
n1392, n1393, n1394, n1395, n1396, n1397, n1398, n1399, n1400, n1401,
n1402, n1403, n1404, n1405, n1406, n1407, n1408, n1409, n1410, n1411,
n1412, n1413, n1414, n1415, n1416, n1417, n1418, n1419, n1420, n1421,
n1422, n1423, n1424, n1425, n1426, n1427, n1428, n1429, n1430, n1431,
n1432, n1433, n1434, n1435, n1436, n1437, n1438, n1439, n1440, n1441,
n1442, n1443, n1444, n1445, n1446, n1447, n1448, n1449, n1450, n1451,
n1452, n1453, n1454, n1455, n1456, n1457, n1458, n1459, n1460, n1461,
n1462, n1463, n1464, n1465, n1466, n1467, n1468, n1469, n1470, n1471,
n1472, n1473, n1474, n1475, n1476, n1477, n1478, n1479, n1480, n1481,
n1482, n1483, n1484, n1485, n1486, n1487, n1488, n1489, n1490, n1491,
n1492, n1493, n1494, n1495, n1496, n1497, n1498, n1499, n1500, n1501,
n1502, n1503, n1504, n1505, n1506, n1507, n1508, n1509, n1510, n1511,
n1512, n1513, n1514, n1515, n1516, n1517, n1518, n1519, n1520, n1521,
n1522, n1523, n1524, n1525, n1526, n1527, n1528, n1529, n1530, n1531,
n1532, n1533, n1534, n1535, n1536, n1537, n1538, n1539, n1540, n1541,
n1542, n1543, n1544, n1545, n1546, n1547, n1548, n1549, n1550, n1551,
n1552, n1553, n1554, n1555, n1556, n1557, n1558, n1559, n1560, n1561,
n1562, n1563, n1564, n1565, n1566, n1567, n1568, n1569, n1570, n1571,
n1572, n1573, n1574, n1575, n1576, n1577, n1578, n1579, n1580, n1581,
n1582, n1583, n1584, n1585, n1586, n1587, n1588, n1589, n1590, n1591,
n1592, n1593, n1594, n1595, n1596, n1597, n1598, n1599, n1600, n1601,
n1602, n1603, n1604, n1605, n1606, n1607, n1608, n1609, n1610, n1611,
n1612, n1613, n1614, n1615, n1616, n1617, n1618, n1619, n1620, n1621,
n1622, n1623, n1624, n1625, n1626, n1627, n1628, n1629, n1630, n1631,
n1632, n1633, n1634, n1635, n1636, n1637, n1638, n1639, n1640, n1641,
n1642, n1643, n1644, n1645, n1646, n1647, n1648, n1649, n1650, n1651,
n1652, n1653, n1654, n1655, n1656, n1657, n1658, n1659, n1660, n1661,
n1662, n1663, n1664, n1665, n1666, n1667, n1668, n1669, n1670, n1671,
n1672, n1673, n1674, n1675, n1676, n1677, n1678, n1679, n1680, n1681,
n1682, n1683, n1684, n1685, n1686, n1687, n1688, n1689, n1690, n1691,
n1692, n1693, n1695, n1696, n1697, n1698, n1699, n1700, n1701, n1702,
n1703, n1704, n1705, n1706, n1707, n1708, n1709, n1710, n1711, n1712,
n1713, n1714, n1715, n1716, n1717, n1718, n1719, n1720, n1721, n1722,
n1723, n1724, n1725, n1726, n1727, n1728, n1729, n1730, n1731, n1732,
n1733, n1734, n1735, n1736, n1737, n1738, n1739, n1740, n1741, n1742,
n1743, n1744, n1745, n1746, n1747, n1748, n1749, n1750, n1751, n1752,
n1753, n1754, n1755, n1756, n1757, n1758, n1759, n1760, n1761, n1762,
n1763, n1764, n1765, n1766, n1767, n1768, n1769, n1770, n1771, n1772,
n1773, n1774, n1775, n1776, n1777, n1778, n1779, n1780, n1781, n1782,
n1783, n1784, n1785, n1786, n1787, n1788, n1789, n1790, n1791, n1792,
n1793, n1794, n1795, n1796, n1797, n1798, n1799, n1800, n1801, n1802,
n1803, n1804, n1805, n1806, n1807, n1808, n1809, n1810, n1811, n1812,
n1813, n1814, n1815, n1816, n1817, n1818, n1819, n1820, n1821, n1822,
n1823, n1824, n1825, n1826, n1827, n1828, n1829, n1830, n1831, n1832,
n1833, n1834, n1835, n1836, n1837, n1838, n1839, n1840, n1841, n1842,
n1843, n1844, n1845, n1846, n1847, n1848, n1849, n1850, n1851, n1852,
n1853, n1854, n1855, n1856, n1857, n1858, n1859, n1860, n1861, n1862,
n1863, n1864, n1865, n1866, n1867, n1868, n1869, n1870, n1871, n1872,
n1873, n1874, n1875, n1876, n1877, n1878, n1879, n1880, n1881, n1882,
n1883, n1884, n1885, n1886, n1887, n1888, n1889, n1890, n1891, n1892,
DP_OP_15J180_122_2221_n22, DP_OP_15J180_122_2221_n21,
DP_OP_15J180_122_2221_n20, DP_OP_15J180_122_2221_n19,
DP_OP_15J180_122_2221_n18, DP_OP_15J180_122_2221_n17,
DP_OP_15J180_122_2221_n11, DP_OP_15J180_122_2221_n10,
DP_OP_15J180_122_2221_n9, DP_OP_15J180_122_2221_n8,
DP_OP_15J180_122_2221_n7, DP_OP_15J180_122_2221_n6,
DP_OP_15J180_122_2221_n5, DP_OP_15J180_122_2221_n4,
DP_OP_15J180_122_2221_n3, DP_OP_15J180_122_2221_n2,
DP_OP_15J180_122_2221_n1, n1895, n1896, n1897, n1898, n1899, n1900,
n1901, n1902, n1903, n1904, n1905, n1906, n1907, n1908, n1909, n1910,
n1911, n1912, n1913, n1914, n1915, n1916, n1917, n1918, n1919, n1920,
n1921, n1922, n1923, n1924, n1925, n1926, n1927, n1928, n1929, n1930,
n1931, n1932, n1933, n1934, n1935, n1936, n1937, n1938, n1939, n1940,
n1941, n1942, n1943, n1944, n1945, n1946, n1947, n1948, n1949, n1950,
n1951, n1952, n1953, n1954, n1955, n1956, n1957, n1958, n1959, n1960,
n1961, n1962, n1963, n1964, n1965, n1966, n1967, n1968, n1969, n1970,
n1971, n1972, n1973, n1974, n1975, n1976, n1977, n1978, n1979, n1980,
n1981, n1982, n1983, n1984, n1985, n1986, n1987, n1988, n1989, n1990,
n1991, n1992, n1993, n1994, n1995, n1996, n1997, n1998, n1999, n2000,
n2001, n2002, n2003, n2004, n2005, n2006, n2007, n2008, n2009, n2010,
n2011, n2012, n2013, n2014, n2015, n2016, n2017, n2018, n2019, n2020,
n2021, n2022, n2023, n2024, n2025, n2026, n2027, n2028, n2029, n2030,
n2031, n2032, n2033, n2034, n2035, n2036, n2037, n2038, n2039, n2040,
n2041, n2042, n2043, n2044, n2045, n2046, n2047, n2048, n2049, n2050,
n2051, n2052, n2053, n2054, n2055, n2056, n2057, n2058, n2059, n2060,
n2061, n2062, n2063, n2064, n2065, n2066, n2067, n2068, n2069, n2070,
n2071, n2072, n2073, n2074, n2075, n2076, n2077, n2078, n2079, n2080,
n2081, n2082, n2083, n2084, n2085, n2086, n2087, n2088, n2089, n2090,
n2091, n2092, n2093, n2094, n2095, n2096, n2097, n2098, n2099, n2100,
n2101, n2102, n2103, n2104, n2105, n2106, n2107, n2108, n2109, n2110,
n2111, n2112, n2113, n2114, n2115, n2116, n2117, n2118, n2119, n2120,
n2121, n2122, n2123, n2124, n2125, n2126, n2127, n2128, n2129, n2130,
n2131, n2132, n2133, n2134, n2135, n2136, n2137, n2138, n2139, n2140,
n2141, n2142, n2143, n2144, n2145, n2146, n2147, n2148, n2149, n2150,
n2151, n2152, n2153, n2154, n2155, n2156, n2157, n2158, n2159, n2160,
n2161, n2162, n2163, n2164, n2165, n2166, n2167, n2168, n2169, n2170,
n2171, n2172, n2173, n2174, n2175, n2176, n2177, n2178, n2179, n2180,
n2181, n2182, n2183, n2184, n2185, n2186, n2187, n2188, n2189, n2190,
n2191, n2192, n2193, n2194, n2195, n2196, n2197, n2198, n2199, n2200,
n2201, n2202, n2203, n2204, n2205, n2206, n2207, n2208, n2209, n2210,
n2211, n2212, n2213, n2214, n2215, n2216, n2217, n2218, n2219, n2220,
n2221, n2222, n2223, n2224, n2225, n2226, n2227, n2228, n2229, n2230,
n2231, n2232, n2233, n2234, n2235, n2236, n2237, n2238, n2239, n2240,
n2241, n2242, n2243, n2244, n2245, n2246, n2247, n2248, n2249, n2250,
n2251, n2252, n2253, n2254, n2255, n2256, n2257, n2258, n2259, n2260,
n2261, n2262, n2263, n2264, n2265, n2266, n2267, n2268, n2269, n2270,
n2271, n2272, n2273, n2274, n2275, n2276, n2277, n2278, n2279, n2280,
n2281, n2282, n2283, n2284, n2285, n2286, n2287, n2288, n2289, n2290,
n2291, n2292, n2293, n2294, n2295, n2296, n2297, n2298, n2299, n2300,
n2301, n2302, n2303, n2304, n2305, n2306, n2307, n2308, n2309, n2310,
n2311, n2312, n2313, n2314, n2315, n2316, n2317, n2318, n2319, n2320,
n2321, n2322, n2323, n2324, n2325, n2326, n2327, n2328, n2329, n2330,
n2331, n2332, n2333, n2334, n2335, n2336, n2337, n2338, n2339, n2340,
n2341, n2342, n2343, n2344, n2345, n2346, n2347, n2348, n2349, n2350,
n2351, n2352, n2353, n2354, n2355, n2356, n2357, n2358, n2359, n2360,
n2361, n2362, n2363, n2364, n2365, n2366, n2367, n2368, n2369, n2370,
n2371, n2372, n2373, n2374, n2375, n2376, n2377, n2378, n2379, n2380,
n2381, n2382, n2383, n2384, n2385, n2386, n2387, n2388, n2389, n2390,
n2391, n2392, n2393, n2394, n2395, n2396, n2397, n2398, n2399, n2400,
n2401, n2402, n2403, n2404, n2405, n2406, n2407, n2408, n2409, n2410,
n2411, n2412, n2413, n2414, n2415, n2416, n2417, n2418, n2419, n2420,
n2421, n2422, n2423, n2424, n2425, n2426, n2427, n2429, n2430, n2431,
n2432, n2433, n2434, n2435, n2436, n2437, n2438, n2439, n2440, n2441,
n2442, n2443, n2444, n2445, n2446, n2447, n2448, n2449, n2450, n2451,
n2452, n2453, n2454, n2455, n2456, n2457, n2458, n2459, n2460, n2461,
n2462, n2463, n2464, n2465, n2466, n2467, n2468, n2469, n2470, n2471,
n2472, n2473, n2474, n2475, n2476, n2477, n2478, n2479, n2480, n2481,
n2482, n2483, n2484, n2485, n2486, n2487, n2488, n2489, n2490, n2491,
n2492, n2493, n2494, n2495, n2496, n2497, n2498, n2499, n2500, n2501,
n2502, n2503, n2504, n2505, n2506, n2507, n2508, n2509, n2510, n2511,
n2512, n2513, n2514, n2515, n2516, n2517, n2518, n2519, n2520, n2521,
n2522, n2523, n2524, n2525, n2526, n2527, n2528, n2529, n2530, n2531,
n2532, n2533, n2534, n2535, n2536, n2537, n2538, n2539, n2540, n2541,
n2542, n2543, n2544, n2545, n2546, n2547, n2548, n2549, n2550, n2551,
n2552, n2553, n2554, n2555, n2556, n2557, n2558, n2559, n2560, n2561,
n2562, n2563, n2564, n2565, n2566, n2567, n2568, n2569, n2570, n2571,
n2572, n2573, n2574, n2575, n2576, n2577, n2578, n2579, n2580, n2581,
n2582, n2583, n2584, n2585, n2586, n2587, n2588, n2589, n2590, n2591,
n2592, n2593, n2594, n2595, n2596, n2597, n2598, n2599, n2600, n2601,
n2602, n2603, n2604, n2605, n2606, n2607, n2608, n2609, n2610, n2611,
n2612, n2613, n2614, n2615, n2616, n2617, n2618, n2619, n2620, n2621,
n2622, n2623, n2624, n2625, n2626, n2627, n2628, n2629, n2630, n2631,
n2632, n2633, n2634, n2635, n2636, n2637, n2638, n2639, n2640, n2641,
n2642, n2643, n2644, n2645, n2646, n2647, n2648, n2649, n2650, n2651,
n2652, n2653, n2654, n2655, n2656, n2657, n2658, n2659, n2660, n2661,
n2662, n2663, n2664, n2665, n2666, n2667, n2668, n2669, n2670, n2671,
n2672, n2673, n2674, n2675, n2676, n2677, n2678, n2679, n2680, n2681,
n2682, n2683, n2684, n2685, n2686, n2687, n2688, n2689, n2690, n2691,
n2692, n2693, n2694, n2695, n2696, n2697, n2698, n2699, n2700, n2701,
n2702, n2703, n2704, n2705, n2706, n2707, n2708, n2709, n2710, n2711,
n2712, n2713, n2714, n2715, n2716, n2717, n2718, n2719, n2720, n2721,
n2722, n2723, n2724, n2725, n2726, n2727, n2728, n2729, n2730, n2731,
n2732, n2733, n2734, n2735, n2736, n2737, n2738, n2739, n2740, n2741,
n2742, n2743, n2744, n2745, n2746, n2747, n2748, n2749, n2750, n2751,
n2752, n2753, n2754, n2755, n2757, n2758, n2759, n2760, n2761, n2762,
n2763, n2764, n2765, n2766, n2767, n2768, n2769, n2770, n2771, n2772,
n2773, n2774, n2775, n2776, n2777, n2778, n2779, n2780, n2781, n2782,
n2783, n2784, n2785, n2786, n2787, n2788, n2789, n2790, n2791, n2792,
n2793, n2794, n2795, n2796, n2797, n2798, n2799, n2800, n2801, n2802,
n2803, n2804, n2805, n2806, n2807, n2808, n2809, n2810, n2811, n2812,
n2813, n2814, n2815, n2816, n2817, n2818, n2819, n2820, n2821, n2822,
n2823, n2824, n2825, n2826, n2827, n2828, n2829, n2830, n2831, n2832,
n2833, n2834, n2835, n2836, n2837, n2838, n2839, n2840, n2841, n2842,
n2843, n2844, n2845, n2846, n2847, n2848, n2849, n2850, n2851, n2852,
n2853, n2854, n2855, n2856, n2857, n2858, n2859, n2860, n2861, n2862,
n2863, n2864, n2865, n2866, n2867, n2868, n2869, n2870, n2871, n2872,
n2873, n2874, n2875, n2876, n2877, n2878, n2879, n2880, n2881, n2882,
n2883, n2884, n2885, n2886, n2887, n2888, n2889, n2890, n2891, n2892,
n2893, n2894, n2895, n2896, n2897, n2898, n2899, n2900, n2901, n2902,
n2903, n2904, n2905, n2906, n2907, n2908, n2909, n2910, n2911, n2912,
n2913, n2914, n2915, n2916, n2917, n2918, n2919, n2920, n2921, n2922,
n2923, n2924, n2925, n2926, n2927, n2928, n2929, n2930, n2931, n2932,
n2933, n2934, n2935, n2936, n2937, n2938, n2939, n2940, n2941, n2942,
n2943, n2944, n2945, n2946, n2947, n2948, n2949, n2950, n2951, n2952,
n2953, n2954, n2955, n2956, n2957, n2958, n2959, n2960, n2961, n2962,
n2963, n2964, n2965, n2966, n2967, n2968, n2969, n2970, n2971, n2972,
n2973, n2974, n2975, n2976, n2977, n2978, n2979, n2980, n2981, n2982,
n2983, n2984, n2985, n2986, n2987, n2988, n2989, n2990, n2991, n2992,
n2993, n2994, n2995, n2996, n2997, n2998, n2999, n3000, n3001, n3002,
n3003, n3004, n3005, n3006, n3007, n3008, n3009, n3010, n3011, n3012,
n3013, n3014, n3015, n3016, n3017, n3018, n3019, n3020, n3021, n3022,
n3023, n3024, n3025, n3026, n3027, n3028, n3029, n3030, n3031, n3032,
n3033, n3034, n3035, n3036, n3037, n3038, n3039, n3040, n3041, n3042,
n3043, n3044, n3045, n3046, n3047, n3048, n3049, n3050, n3051, n3052,
n3053, n3054, n3055, n3056, n3057, n3058, n3059, n3060, n3061, n3062,
n3063, n3064, n3065, n3066, n3067, n3068, n3069, n3070, n3071, n3072,
n3073, n3074, n3075, n3076, n3077, n3078, n3079, n3080, n3081, n3082,
n3083, n3084, n3085, n3086, n3087, n3088, n3089, n3090, n3091, n3092,
n3093, n3094, n3095, n3096, n3097, n3098, n3099, n3100, n3101, n3102,
n3103, n3104, n3105, n3106, n3107, n3108, n3109, n3110, n3111, n3112,
n3113, n3114, n3115, n3116, n3117, n3118, n3119, n3120, n3121, n3122,
n3123, n3124, n3125, n3126, n3127, n3128, n3129, n3130, n3131, n3132,
n3133, n3134, n3135, n3136, n3137, n3138, n3139, n3140, n3141, n3142,
n3143, n3144, n3145, n3146, n3147, n3148, n3149, n3150, n3151, n3152,
n3153, n3154, n3155, n3156, n3157, n3158, n3159, n3160, n3161, n3162,
n3163, n3164, n3165, n3166, n3167, n3168, n3169, n3170, n3171, n3172,
n3173, n3174, n3175, n3176, n3177, n3178, n3179, n3180, n3181, n3182,
n3183, n3184, n3185, n3186, n3187, n3188, n3189, n3190, n3191, n3192,
n3193, n3194, n3195, n3196, n3197, n3198, n3199, n3200, n3201, n3202,
n3203, n3204, n3205, n3206, n3207, n3208, n3209, n3210, n3211, n3212,
n3213, n3214, n3215, n3216, n3217, n3218, n3219, n3220, n3221, n3222,
n3223, n3224, n3225, n3226, n3227, n3228, n3229, n3230, n3231, n3232,
n3233, n3234, n3235, n3236, n3237, n3238, n3239, n3240, n3241, n3242,
n3243, n3244, n3245, n3246, n3247, n3248, n3249, n3250, n3251, n3252,
n3253, n3254, n3255, n3256, n3257, n3258, n3259, n3260, n3261, n3262,
n3263, n3264, n3265, n3266, n3267, n3268, n3269, n3270, n3271, n3272,
n3273, n3274, n3275, n3276, n3277, n3278, n3279, n3280, n3281, n3282,
n3283, n3284, n3285, n3286, n3287, n3288, n3289, n3290, n3291, n3292,
n3293, n3294, n3295, n3296, n3297, n3298, n3299, n3300, n3301, n3302,
n3303, n3304, n3305, n3306, n3307, n3308, n3309, n3310, n3311, n3312,
n3313, n3314, n3315, n3316, n3317, n3318, n3319, n3320, n3321, n3322,
n3323, n3324, n3325, n3326, n3327, n3328, n3329, n3330, n3331, n3332,
n3333, n3334, n3335, n3336, n3337, n3338, n3339, n3340, n3341, n3342,
n3343, n3344, n3345, n3346, n3347, n3348, n3349, n3350, n3351, n3352,
n3353, n3354, n3355, n3356, n3357, n3358, n3359, n3360, n3361, n3362,
n3363, n3364, n3365, n3366, n3367, n3368, n3369, n3370, n3371, n3372,
n3373, n3374, n3375, n3376, n3377, n3378, n3379, n3380, n3381, n3382,
n3383, n3384, n3385, n3386, n3387, n3388, n3389, n3390, n3391, n3392,
n3393, n3394, n3395, n3396, n3397, n3398, n3399, n3400, n3401, n3402,
n3403, n3404, n3405, n3406, n3407, n3408, n3409, n3410, n3411, n3412,
n3413, n3414, n3415, n3416, n3417, n3418, n3419, n3420, n3421, n3422,
n3423, n3424, n3425, n3426, n3427, n3428, n3429, n3430, n3431, n3432,
n3433, n3434, n3435, n3436, n3437, n3438, n3439, n3440, n3441, n3442,
n3443, n3444, n3445, n3446, n3447, n3448, n3449, n3450, n3451, n3452,
n3453, n3454, n3455, n3456, n3457, n3458, n3459, n3460, n3461, n3462,
n3463, n3464, n3465, n3466, n3467, n3468, n3469, n3470, n3471, n3472,
n3473, n3474, n3475, n3476, n3477, n3478, n3479, n3480, n3481, n3482,
n3483, n3484, n3485, n3486, n3487, n3488, n3489, n3490, n3491, n3492,
n3493, n3494, n3495, n3496, n3497, n3498, n3499, n3500, n3501, n3502,
n3503, n3504, n3505, n3506, n3507, n3508, n3509, n3510, n3511, n3512,
n3513, n3514, n3515, n3516, n3517, n3518, n3519, n3520, n3521, n3522,
n3523, n3524, n3525, n3526, n3527, n3528, n3529, n3530, n3531, n3532,
n3533, n3534, n3535, n3536, n3537, n3538, n3539, n3540, n3541, n3542,
n3543, n3544, n3545, n3546, n3547, n3548, n3549, n3550, n3551, n3552,
n3553, n3554, n3555, n3556, n3557, n3558, n3559, n3560, n3561, n3562,
n3563, n3564, n3565, n3566, n3567, n3568, n3569, n3570, n3571, n3572,
n3573, n3574, n3575, n3576, n3577, n3578, n3579, n3580, n3581, n3582,
n3583, n3584, n3585, n3586, n3587, n3588, n3589, n3590, n3591, n3592,
n3593, n3594, n3595, n3596, n3597, n3598, n3599, n3600, n3601, n3602,
n3603, n3604, n3605, n3606, n3607, n3608, n3609, n3610, n3611, n3612,
n3613, n3614, n3615, n3616, n3617, n3618, n3619, n3620, n3621, n3622,
n3623, n3624, n3625, n3626, n3627, n3628, n3629, n3630, n3631, n3632,
n3633, n3634, n3635, n3636, n3637, n3638, n3639, n3640, n3641, n3642,
n3643, n3644, n3645, n3646, n3647, n3648, n3649, n3650, n3651, n3652,
n3653, n3654, n3655, n3656, n3657, n3658, n3659, n3660, n3661, n3662,
n3663, n3664, n3665, n3666, n3667, n3668, n3669, n3670, n3671, n3672,
n3673, n3674, n3675, n3676, n3677, n3678, n3679, n3680, n3681, n3682,
n3683, n3684, n3685, n3686, n3687, n3688, n3689, n3690, n3691, n3692,
n3693, n3694, n3695, n3696, n3697, n3698, n3699, n3700, n3701, n3702,
n3703, n3704, n3705, n3706, n3707, n3708, n3709, n3710, n3711, n3712,
n3713, n3714, n3715, n3716, n3717, n3718, n3719, n3720, n3721, n3722,
n3723, n3724, n3725, n3726, n3727, n3728, n3729, n3730, n3731, n3732,
n3733, n3734, n3735, n3736, n3737, n3738, n3739, n3740, n3741, n3742,
n3743, n3744, n3745, n3746, n3747, n3748, n3749, n3750, n3751, n3752,
n3753, n3754, n3755, n3756, n3757, n3758, n3759, n3760, n3761, n3762,
n3763, n3764, n3765, n3766, n3767, n3768, n3769, n3770, n3771, n3772,
n3773, n3774, n3775, n3776, n3777, n3778, n3779, n3780, n3781, n3782,
n3783, n3784, n3785, n3786, n3787, n3788, n3789, n3790, n3791, n3792,
n3793, n3794, n3795, n3796, n3797, n3798, n3799, n3800, n3801, n3802,
n3803, n3804, n3805, n3806, n3807, n3808, n3809, n3810, n3811, n3812,
n3813, n3814, n3815, n3816, n3817, n3818, n3819, n3820, n3821, n3822,
n3823, n3824, n3825, n3826, n3827, n3828, n3829, n3830, n3831, n3832,
n3833, n3834, n3835, n3836, n3837, n3838, n3839, n3840, n3841, n3842,
n3843, n3844, n3845, n3846, n3847, n3848, n3849, n3850, n3851, n3852,
n3853, n3854, n3855, n3856, n3857, n3858, n3859, n3860, n3861, n3862,
n3863, n3864, n3865, n3866, n3867, n3868, n3869, n3870, n3871, n3872,
n3873, n3874, n3875, n3876, n3877, n3878, n3879, n3880, n3881, n3882,
n3883, n3884, n3885, n3886, n3887, n3888, n3889, n3890, n3891, n3892,
n3893, n3894, n3895, n3896, n3897, n3898, n3899, n3900, n3901, n3902,
n3903, n3904, n3905, n3906, n3907, n3908, n3909, n3910, n3911, n3912,
n3913, n3914, n3915, n3916, n3917, n3918, n3919, n3920, n3921, n3922,
n3923, n3924, n3925, n3926, n3927, n3928, n3929, n3930, n3931, n3932,
n3933, n3934, n3935, n3936, n3937, n3938, n3939, n3940, n3941, n3942,
n3943, n3944, n3945, n3946, n3947, n3948, n3949, n3950, n3951, n3952,
n3953, n3954, n3955, n3956, n3957, n3958, n3959, n3960, n3961, n3962,
n3963, n3964, n3965, n3966, n3967, n3968, n3969, n3970, n3971, n3972,
n3973, n3974, n3975, n3976, n3977, n3978, n3979, n3980, n3981, n3982,
n3983, n3984, n3985, n3986, n3987, n3988, n3989, n3990, n3991, n3992,
n3993, n3994, n3995, n3996, n3997, n3998, n3999, n4000, n4001, n4002,
n4003, n4005, n4006, n4007, n4008, n4009, n4010, n4011, n4012, n4013,
n4014, n4015, n4016, n4017, n4018, n4019, n4020, n4021, n4022, n4023,
n4024, n4025, n4026, n4027, n4028, n4029, n4030, n4031, n4032, n4033,
n4034, n4035, n4036, n4037, n4038, n4039, n4040, n4041, n4042, n4043,
n4044, n4045, n4046, n4047, n4048, n4049, n4050, n4051, n4052, n4053,
n4054, n4055, n4056, n4057, n4058, n4059, n4060, n4061, n4062, n4063,
n4064, n4065, n4066, n4067, n4068, n4069, n4070, n4071, n4072, n4073,
n4074, n4075, n4076, n4077, n4078, n4079, n4080, n4081, n4082, n4083,
n4084, n4085, n4086;
wire [3:0] Shift_reg_FLAGS_7;
wire [63:0] intDX_EWSW;
wire [63:0] intDY_EWSW;
wire [62:0] DMP_EXP_EWSW;
wire [57:0] DmP_EXP_EWSW;
wire [62:0] DMP_SHT1_EWSW;
wire [51:0] DmP_mant_SHT1_SW;
wire [5:0] Shift_amount_SHT1_EWR;
wire [54:0] Raw_mant_NRM_SWR;
wire [54:0] Data_array_SWR;
wire [62:0] DMP_SHT2_EWSW;
wire [5:2] shift_value_SHT2_EWR;
wire [10:0] DMP_exp_NRM2_EW;
wire [10:0] DMP_exp_NRM_EW;
wire [5:0] LZD_output_NRM2_EW;
wire [10:0] exp_rslt_NRM2_EW1;
wire [62:0] DMP_SFG;
wire [54:0] DmP_mant_SFG_SWR;
wire [2:0] inst_FSM_INPUT_ENABLE_state_reg;
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_63_ ( .D(n1820), .CK(n4012), .RN(n2047),
.Q(intDX_EWSW[63]), .QN(n3921) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_51_ ( .D(n1749), .CK(n4017), .RN(n3931), .Q(
Data_array_SWR[51]), .QN(n3920) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_50_ ( .D(n1748), .CK(n4015), .RN(n4000), .Q(
Data_array_SWR[50]), .QN(n3919) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_49_ ( .D(n1747), .CK(n4014), .RN(n3946), .Q(
Data_array_SWR[49]), .QN(n3918) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_48_ ( .D(n1746), .CK(n4013), .RN(n2043), .Q(
Data_array_SWR[48]), .QN(n3917) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_1_ ( .D(n1155), .CK(n4063), .RN(n3991),
.Q(DmP_mant_SFG_SWR[1]), .QN(n3916) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_16_ ( .D(n1802), .CK(n4017), .RN(n4000),
.Q(intDY_EWSW[16]), .QN(n3915) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_27_ ( .D(n1242), .CK(n4073), .RN(n3983),
.Q(Raw_mant_NRM_SWR[27]), .QN(n3914) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_44_ ( .D(n1774), .CK(n4017), .RN(n3946),
.Q(intDY_EWSW[44]), .QN(n3909) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_22_ ( .D(n1796), .CK(n4015), .RN(n3930),
.Q(intDY_EWSW[22]), .QN(n3908) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_20_ ( .D(n1798), .CK(n4014), .RN(n3936),
.Q(intDY_EWSW[20]), .QN(n3907) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_39_ ( .D(n1844), .CK(n4073), .RN(n3926),
.Q(intDX_EWSW[39]), .QN(n3906) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_29_ ( .D(n1854), .CK(n4008), .RN(n3925),
.Q(intDX_EWSW[29]), .QN(n3905) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_20_ ( .D(n1863), .CK(n4017), .RN(n3925),
.Q(intDX_EWSW[20]), .QN(n3904) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_57_ ( .D(n1826), .CK(n4011), .RN(n3928),
.Q(intDX_EWSW[57]), .QN(n3902) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_44_ ( .D(n1839), .CK(n4026), .RN(n3927),
.Q(intDX_EWSW[44]), .QN(n3901) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_36_ ( .D(n1847), .CK(n4075), .RN(n3926),
.Q(intDX_EWSW[36]), .QN(n3900) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_31_ ( .D(n1852), .CK(n4072), .RN(n3926),
.Q(intDX_EWSW[31]), .QN(n3899) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_42_ ( .D(n1776), .CK(n4077), .RN(n3932),
.Q(intDY_EWSW[42]), .QN(n3897) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_28_ ( .D(n1726), .CK(n2025), .RN(n3938), .Q(
Data_array_SWR[28]), .QN(n3896) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_29_ ( .D(n1727), .CK(n4010), .RN(n3938), .Q(
Data_array_SWR[29]), .QN(n3895) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_30_ ( .D(n1728), .CK(n4029), .RN(n3938), .Q(
Data_array_SWR[30]), .QN(n3894) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_53_ ( .D(n1622), .CK(n4031), .RN(n3947), .Q(
DMP_EXP_EWSW[53]), .QN(n3893) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_52_ ( .D(n1623), .CK(n4035), .RN(n3936), .Q(
DMP_EXP_EWSW[52]), .QN(n3892) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_45_ ( .D(n1773), .CK(n4015), .RN(n2043),
.Q(intDY_EWSW[45]), .QN(n3891) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_38_ ( .D(n1780), .CK(n2271), .RN(n3932),
.Q(intDY_EWSW[38]), .QN(n3890) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_28_ ( .D(n1790), .CK(n4013), .RN(n2043),
.Q(intDY_EWSW[28]), .QN(n3889) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_8_ ( .D(n1810), .CK(n4013), .RN(n3929),
.Q(intDY_EWSW[8]), .QN(n3888) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_4_ ( .D(n1814), .CK(n4008), .RN(n3955),
.Q(intDY_EWSW[4]), .QN(n3887) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_50_ ( .D(n1833), .CK(n4049), .RN(n3928),
.Q(intDX_EWSW[50]), .QN(n3886) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_42_ ( .D(n1841), .CK(n4029), .RN(n3927),
.Q(intDX_EWSW[42]), .QN(n3885) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_34_ ( .D(n1849), .CK(n4009), .RN(n3926),
.Q(intDX_EWSW[34]), .QN(n3884) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_28_ ( .D(n1855), .CK(n4015), .RN(n3925),
.Q(intDX_EWSW[28]), .QN(n3883) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_12_ ( .D(n1871), .CK(n2024), .RN(n3924),
.Q(intDX_EWSW[12]), .QN(n3882) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_8_ ( .D(n1875), .CK(n4006), .RN(n3923),
.Q(intDX_EWSW[8]), .QN(n3881) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_21_ ( .D(n1797), .CK(n4008), .RN(n3931),
.Q(intDY_EWSW[21]), .QN(n3880) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_53_ ( .D(n1830), .CK(n4050), .RN(n3928),
.Q(intDX_EWSW[53]), .QN(n3879) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_0_ ( .D(n1607), .CK(n4035), .RN(n3948), .Q(
DMP_SFG[0]), .QN(n3878) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_34_ ( .D(n1784), .CK(n4016), .RN(n3932),
.Q(intDY_EWSW[34]), .QN(n3877) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_50_ ( .D(n1768), .CK(n4013), .RN(n3929),
.Q(intDY_EWSW[50]), .QN(n3876) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_9_ ( .D(n1809), .CK(n4017), .RN(n4000),
.Q(intDY_EWSW[9]), .QN(n3875) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_2_ ( .D(n1816), .CK(n4040), .RN(n4002),
.Q(intDY_EWSW[2]), .QN(n3874) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_22_ ( .D(n1861), .CK(n4014), .RN(n3925),
.Q(intDX_EWSW[22]), .QN(n3873) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_14_ ( .D(n1869), .CK(n4067), .RN(n3924),
.Q(intDX_EWSW[14]), .QN(n3872) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_7_ ( .D(n1876), .CK(n4016), .RN(n3923),
.Q(intDX_EWSW[7]), .QN(n3871) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_3_ ( .D(n1880), .CK(n4006), .RN(n3923),
.Q(intDX_EWSW[3]), .QN(n3870) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_18_ ( .D(n1251), .CK(n4067), .RN(n3982),
.Q(Raw_mant_NRM_SWR[18]), .QN(n3869) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_17_ ( .D(n1252), .CK(n4068), .RN(n3982),
.Q(Raw_mant_NRM_SWR[17]), .QN(n3868) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_0_ ( .D(n1269), .CK(n4007), .RN(n3981),
.Q(Raw_mant_NRM_SWR[0]), .QN(n3867) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_10_ ( .D(n1259), .CK(n4068), .RN(n3982),
.Q(Raw_mant_NRM_SWR[10]), .QN(n3866) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_26_ ( .D(n1243), .CK(n4075), .RN(n3983),
.Q(Raw_mant_NRM_SWR[26]), .QN(n3865) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_11_ ( .D(n1258), .CK(n4071), .RN(n3982),
.Q(Raw_mant_NRM_SWR[11]), .QN(n3864) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_13_ ( .D(n1805), .CK(n4015), .RN(n3930),
.Q(intDY_EWSW[13]), .QN(n3863) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_37_ ( .D(n1781), .CK(n4018), .RN(n3932),
.Q(intDY_EWSW[37]), .QN(n3862) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_27_ ( .D(n1791), .CK(n4014), .RN(n3946),
.Q(intDY_EWSW[27]), .QN(n3861) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_30_ ( .D(n1853), .CK(n4009), .RN(n3926),
.Q(intDX_EWSW[30]), .QN(n3860) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_4_ ( .D(n1879), .CK(n4006), .RN(n3923),
.Q(intDX_EWSW[4]), .QN(n3859) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_54_ ( .D(n1102), .CK(n4083), .RN(n3997),
.Q(DmP_mant_SFG_SWR[54]), .QN(n3858) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_55_ ( .D(n1291), .CK(n2028), .RN(n3979), .Q(
DmP_EXP_EWSW[55]), .QN(n3857) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_4_ ( .D(n1265), .CK(n4068), .RN(n3981),
.Q(Raw_mant_NRM_SWR[4]), .QN(n3856) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_53_ ( .D(n1216), .CK(n4009), .RN(n3986),
.Q(Raw_mant_NRM_SWR[53]), .QN(n3855) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_58_ ( .D(n1825), .CK(n4011), .RN(n3928),
.Q(intDX_EWSW[58]), .QN(n3853) );
DFFRX1TS SHT2_STAGE_SHFTVARS2_Q_reg_0_ ( .D(n1754), .CK(n4021), .RN(n3935),
.Q(bit_shift_SHT2), .QN(n3852) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_14_ ( .D(n1804), .CK(n4013), .RN(n3933),
.Q(intDY_EWSW[14]), .QN(n3851) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_37_ ( .D(n1846), .CK(n4070), .RN(n3926),
.Q(intDX_EWSW[37]), .QN(n3850) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_9_ ( .D(n1874), .CK(n4006), .RN(n3923),
.Q(intDX_EWSW[9]), .QN(n3849) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_49_ ( .D(n1107), .CK(n4084), .RN(n3996),
.Q(DmP_mant_SFG_SWR[49]), .QN(n3848) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_27_ ( .D(n1129), .CK(n2265), .RN(n3994),
.Q(DmP_mant_SFG_SWR[27]), .QN(n3847) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_21_ ( .D(n1135), .CK(n4028), .RN(n3993),
.Q(DmP_mant_SFG_SWR[21]), .QN(n3846) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_17_ ( .D(n1139), .CK(n4025), .RN(n3993),
.Q(DmP_mant_SFG_SWR[17]), .QN(n3845) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_15_ ( .D(n1141), .CK(n4030), .RN(n3993),
.Q(DmP_mant_SFG_SWR[15]), .QN(n3844) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_13_ ( .D(n1143), .CK(n4027), .RN(n3993),
.Q(DmP_mant_SFG_SWR[13]), .QN(n3843) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_5_ ( .D(n1151), .CK(n4055), .RN(n3992),
.Q(DmP_mant_SFG_SWR[5]), .QN(n3842) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_47_ ( .D(n1836), .CK(n2025), .RN(n3927),
.Q(intDX_EWSW[47]), .QN(n3840) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_48_ ( .D(n1835), .CK(n4024), .RN(n3927),
.Q(intDX_EWSW[48]), .QN(n3839) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_56_ ( .D(n1290), .CK(n4005), .RN(n3979), .Q(
DmP_EXP_EWSW[56]), .QN(n3838) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_54_ ( .D(n1292), .CK(n4062), .RN(n3978), .Q(
DmP_EXP_EWSW[54]), .QN(n3837) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_36_ ( .D(n1782), .CK(n4021), .RN(n3932),
.Q(intDY_EWSW[36]), .QN(n3836) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_19_ ( .D(n1799), .CK(n4008), .RN(n3931),
.Q(intDY_EWSW[19]), .QN(n3835) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_16_ ( .D(n1867), .CK(n4069), .RN(n3924),
.Q(intDX_EWSW[16]), .QN(n3834) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_12_ ( .D(n1806), .CK(n4015), .RN(n3930),
.Q(intDY_EWSW[12]), .QN(n3833) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_55_ ( .D(n1620), .CK(n4033), .RN(n3947), .Q(
DMP_EXP_EWSW[55]), .QN(n3832) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_22_ ( .D(n1247), .CK(n4071), .RN(n3983),
.Q(Raw_mant_NRM_SWR[22]), .QN(n3831) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_7_ ( .D(n1262), .CK(n4069), .RN(n3981),
.Q(Raw_mant_NRM_SWR[7]), .QN(n3830) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_3_ ( .D(n1266), .CK(n4071), .RN(n3981),
.Q(Raw_mant_NRM_SWR[3]), .QN(n3829) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_6_ ( .D(n1263), .CK(n2024), .RN(n3981),
.Q(Raw_mant_NRM_SWR[6]), .QN(n3828) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_14_ ( .D(n1255), .CK(n4007), .RN(n3982),
.Q(Raw_mant_NRM_SWR[14]), .QN(n3827) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_24_ ( .D(n1245), .CK(n4069), .RN(n3983),
.Q(Raw_mant_NRM_SWR[24]), .QN(n3826) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_39_ ( .D(n1230), .CK(n2024), .RN(n3985),
.Q(Raw_mant_NRM_SWR[39]), .QN(n3825) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_48_ ( .D(n1770), .CK(n4008), .RN(n3955),
.Q(intDY_EWSW[48]), .QN(n3824) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_10_ ( .D(n1873), .CK(n4007), .RN(n3924),
.Q(intDX_EWSW[10]), .QN(n3823) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_15_ ( .D(n1254), .CK(n4067), .RN(n3982),
.Q(Raw_mant_NRM_SWR[15]), .QN(n3822) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_13_ ( .D(n1256), .CK(n4068), .RN(n3982),
.Q(Raw_mant_NRM_SWR[13]), .QN(n3821) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_31_ ( .D(n1238), .CK(n4009), .RN(n3984),
.Q(Raw_mant_NRM_SWR[31]), .QN(n3820) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_32_ ( .D(n1237), .CK(n4070), .RN(n3984),
.Q(Raw_mant_NRM_SWR[32]), .QN(n3819) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_50_ ( .D(n1106), .CK(n4085), .RN(n3996),
.Q(DmP_mant_SFG_SWR[50]), .QN(n3818) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_48_ ( .D(n1108), .CK(n4083), .RN(n3996),
.Q(DmP_mant_SFG_SWR[48]), .QN(n3817) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_32_ ( .D(n1124), .CK(n4036), .RN(n3995),
.Q(DmP_mant_SFG_SWR[32]), .QN(n3816) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_22_ ( .D(n1134), .CK(n2273), .RN(n3994),
.Q(DmP_mant_SFG_SWR[22]), .QN(n3815) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_20_ ( .D(n1136), .CK(n4027), .RN(n3993),
.Q(DmP_mant_SFG_SWR[20]), .QN(n3814) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_18_ ( .D(n1138), .CK(n4028), .RN(n3993),
.Q(DmP_mant_SFG_SWR[18]), .QN(n3813) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_16_ ( .D(n1140), .CK(n4025), .RN(n3993),
.Q(DmP_mant_SFG_SWR[16]), .QN(n3812) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_14_ ( .D(n1142), .CK(n4030), .RN(n3993),
.Q(DmP_mant_SFG_SWR[14]), .QN(n3811) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_12_ ( .D(n1144), .CK(n4052), .RN(n3993),
.Q(DmP_mant_SFG_SWR[12]), .QN(n3810) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_6_ ( .D(n1150), .CK(n4054), .RN(n3992),
.Q(DmP_mant_SFG_SWR[6]), .QN(n3809) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_4_ ( .D(n1152), .CK(n4057), .RN(n3992),
.Q(DmP_mant_SFG_SWR[4]), .QN(n3808) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_45_ ( .D(n1838), .CK(n4024), .RN(n3927),
.Q(intDX_EWSW[45]), .QN(n3807) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_38_ ( .D(n1845), .CK(n4072), .RN(n3926),
.Q(intDX_EWSW[38]), .QN(n3806) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_36_ ( .D(n1233), .CK(n4007), .RN(n3984),
.Q(Raw_mant_NRM_SWR[36]), .QN(n3805) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_51_ ( .D(n1454), .CK(n4046), .RN(n3963), .Q(
DMP_SFG[51]), .QN(n3804) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_42_ ( .D(n1227), .CK(n4067), .RN(n3985),
.Q(Raw_mant_NRM_SWR[42]), .QN(n3803) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_57_ ( .D(n1761), .CK(n4016), .RN(n3934),
.Q(intDY_EWSW[57]), .QN(n3802) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_19_ ( .D(n1864), .CK(n4068), .RN(n3924),
.Q(intDX_EWSW[19]), .QN(n3801) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_47_ ( .D(n1771), .CK(n4014), .RN(n3930),
.Q(intDY_EWSW[47]), .QN(n3800) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_60_ ( .D(n1823), .CK(n4047), .RN(n4003),
.Q(intDX_EWSW[60]), .QN(n3799) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_49_ ( .D(n1834), .CK(n4029), .RN(n3927),
.Q(intDX_EWSW[49]), .QN(n3798) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_17_ ( .D(n1866), .CK(n4071), .RN(n3924),
.Q(intDX_EWSW[17]), .QN(n3797) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_15_ ( .D(n1868), .CK(n2024), .RN(n3924),
.Q(intDX_EWSW[15]), .QN(n3796) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_1_ ( .D(n1882), .CK(n4006), .RN(n3923),
.Q(intDX_EWSW[1]), .QN(n3795) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_50_ ( .D(n1457), .CK(n4045), .RN(n3963), .Q(
DMP_SFG[50]), .QN(n3794) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_44_ ( .D(n1475), .CK(n2266), .RN(n3961), .Q(
DMP_SFG[44]), .QN(n3793) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_42_ ( .D(n1481), .CK(n4046), .RN(n3961), .Q(
DMP_SFG[42]), .QN(n3792) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_40_ ( .D(n1487), .CK(n4045), .RN(n3960), .Q(
DMP_SFG[40]), .QN(n3791) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_38_ ( .D(n1493), .CK(n4043), .RN(n3959), .Q(
DMP_SFG[38]), .QN(n3790) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_36_ ( .D(n1499), .CK(n4040), .RN(n3959), .Q(
DMP_SFG[36]), .QN(n3789) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_34_ ( .D(n1505), .CK(n4048), .RN(n3958), .Q(
DMP_SFG[34]), .QN(n3788) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_32_ ( .D(n1511), .CK(n2266), .RN(n3958), .Q(
DMP_SFG[32]), .QN(n3787) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_28_ ( .D(n1523), .CK(n4041), .RN(n3956), .Q(
DMP_SFG[28]), .QN(n3786) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_26_ ( .D(n1529), .CK(n2022), .RN(n3956), .Q(
DMP_SFG[26]), .QN(n3785) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_24_ ( .D(n1535), .CK(n4040), .RN(n3933), .Q(
DMP_SFG[24]), .QN(n3784) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_22_ ( .D(n1541), .CK(n4047), .RN(n3931), .Q(
DMP_SFG[22]), .QN(n3783) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_8_ ( .D(n1583), .CK(n2265), .RN(n3950), .Q(
DMP_SFG[8]), .QN(n3782) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_6_ ( .D(n1589), .CK(n4031), .RN(n3950), .Q(
DMP_SFG[6]), .QN(n3781) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_56_ ( .D(n1827), .CK(n4051), .RN(n3928),
.Q(intDX_EWSW[56]), .QN(n3780) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_52_ ( .D(n1831), .CK(n4053), .RN(n3928),
.Q(intDX_EWSW[52]), .QN(n3779) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_48_ ( .D(n1221), .CK(n4073), .RN(n3985),
.Q(Raw_mant_NRM_SWR[48]), .QN(n3778) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_51_ ( .D(n1105), .CK(n4083), .RN(n3996),
.Q(DmP_mant_SFG_SWR[51]), .QN(n3777) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_47_ ( .D(n1109), .CK(n4085), .RN(n3996),
.Q(DmP_mant_SFG_SWR[47]), .QN(n3776) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_45_ ( .D(n1111), .CK(n4083), .RN(n3996),
.Q(DmP_mant_SFG_SWR[45]), .QN(n3775) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_43_ ( .D(n1113), .CK(n4084), .RN(n3996),
.Q(DmP_mant_SFG_SWR[43]), .QN(n3774) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_31_ ( .D(n1125), .CK(n4037), .RN(n3994),
.Q(DmP_mant_SFG_SWR[31]), .QN(n3773) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_29_ ( .D(n1127), .CK(n4039), .RN(n3994),
.Q(DmP_mant_SFG_SWR[29]), .QN(n3772) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_25_ ( .D(n1131), .CK(n4081), .RN(n3994),
.Q(DmP_mant_SFG_SWR[25]), .QN(n3771) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_23_ ( .D(n1133), .CK(n2265), .RN(n3994),
.Q(DmP_mant_SFG_SWR[23]), .QN(n3770) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_19_ ( .D(n1137), .CK(n2273), .RN(n3993),
.Q(DmP_mant_SFG_SWR[19]), .QN(n3769) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_11_ ( .D(n1145), .CK(n4079), .RN(n3992),
.Q(DmP_mant_SFG_SWR[11]), .QN(n3768) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_9_ ( .D(n1147), .CK(n4057), .RN(n3992),
.Q(DmP_mant_SFG_SWR[9]), .QN(n3767) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_7_ ( .D(n1149), .CK(n4055), .RN(n3992),
.Q(DmP_mant_SFG_SWR[7]), .QN(n3766) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_3_ ( .D(n1153), .CK(n4052), .RN(n3992),
.Q(DmP_mant_SFG_SWR[3]), .QN(n3765) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_54_ ( .D(n1764), .CK(n4018), .RN(n3934),
.Q(intDY_EWSW[54]), .QN(n3764) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_24_ ( .D(n1794), .CK(n4008), .RN(n3929),
.Q(intDY_EWSW[24]), .QN(n3763) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_28_ ( .D(n1241), .CK(n4072), .RN(n3983),
.Q(Raw_mant_NRM_SWR[28]), .QN(n3762) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_50_ ( .D(n1219), .CK(n4075), .RN(n3986),
.Q(Raw_mant_NRM_SWR[50]), .QN(n3761) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_52_ ( .D(n1217), .CK(n4070), .RN(n3986),
.Q(Raw_mant_NRM_SWR[52]), .QN(n3760) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_46_ ( .D(n1223), .CK(n4072), .RN(n3985),
.Q(Raw_mant_NRM_SWR[46]), .QN(n3759) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_21_ ( .D(n1862), .CK(n4013), .RN(n3925),
.Q(intDX_EWSW[21]), .QN(n3757) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_25_ ( .D(n1244), .CK(n2024), .RN(n3983),
.Q(Raw_mant_NRM_SWR[25]), .QN(n3756) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_37_ ( .D(n1232), .CK(n4068), .RN(n3984),
.Q(Raw_mant_NRM_SWR[37]), .QN(n3755) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_21_ ( .D(n1248), .CK(n4007), .RN(n3983),
.Q(Raw_mant_NRM_SWR[21]), .QN(n3754) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_11_ ( .D(n1807), .CK(n4014), .RN(n3936),
.Q(intDY_EWSW[11]), .QN(n3753) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_29_ ( .D(n1789), .CK(n4014), .RN(n3955),
.Q(intDY_EWSW[29]), .QN(n3752) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_33_ ( .D(n1236), .CK(n4009), .RN(n3984),
.Q(Raw_mant_NRM_SWR[33]), .QN(n3751) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_30_ ( .D(n1239), .CK(n4073), .RN(n3984),
.Q(Raw_mant_NRM_SWR[30]), .QN(n3750) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_32_ ( .D(n1786), .CK(n4013), .RN(n2043),
.Q(intDY_EWSW[32]), .QN(n3748) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_43_ ( .D(n1226), .CK(n4067), .RN(n3985),
.QN(n3747) );
DFFRX2TS inst_ShiftRegister_Q_reg_5_ ( .D(n1889), .CK(n2028), .RN(n3922),
.Q(Shift_reg_FLAGS_7_5), .QN(n3912) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_2_ ( .D(n1881), .CK(n4006), .RN(n3923),
.Q(intDX_EWSW[2]), .QN(n3744) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_53_ ( .D(n1293), .CK(n4065), .RN(n3978), .Q(
DmP_EXP_EWSW[53]), .QN(n3743) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_62_ ( .D(n1821), .CK(n4042), .RN(n4000),
.Q(intDX_EWSW[62]), .QN(n3742) );
DFFRX2TS inst_ShiftRegister_Q_reg_4_ ( .D(n1888), .CK(n4058), .RN(n3922),
.Q(n4087), .QN(n3854) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_41_ ( .D(n1115), .CK(n4082), .RN(n3995),
.Q(DmP_mant_SFG_SWR[41]), .QN(n3741) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_39_ ( .D(n1117), .CK(n4082), .RN(n3995),
.Q(DmP_mant_SFG_SWR[39]), .QN(n3740) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_37_ ( .D(n1119), .CK(n4082), .RN(n3995),
.Q(DmP_mant_SFG_SWR[37]), .QN(n3739) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_33_ ( .D(n1123), .CK(n4082), .RN(n3995),
.Q(DmP_mant_SFG_SWR[33]), .QN(n3738) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_55_ ( .D(n1828), .CK(n2026), .RN(n3928),
.Q(intDX_EWSW[55]), .QN(n3737) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_39_ ( .D(n1779), .CK(n4077), .RN(n3932),
.Q(intDY_EWSW[39]), .QN(n3736) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_54_ ( .D(n1215), .CK(n4009), .RN(n3986),
.Q(Raw_mant_NRM_SWR[54]), .QN(n3735) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_3_ ( .D(n1815), .CK(n4041), .RN(n2043),
.Q(intDY_EWSW[3]), .QN(n3734) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_42_ ( .D(n1114), .CK(n4082), .RN(n3996),
.Q(DmP_mant_SFG_SWR[42]), .QN(n3733) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_40_ ( .D(n1116), .CK(n4082), .RN(n3995),
.Q(DmP_mant_SFG_SWR[40]), .QN(n3732) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_38_ ( .D(n1118), .CK(n4082), .RN(n3995),
.Q(DmP_mant_SFG_SWR[38]), .QN(n3731) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_36_ ( .D(n1120), .CK(n4082), .RN(n3995),
.Q(DmP_mant_SFG_SWR[36]), .QN(n3730) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_34_ ( .D(n1122), .CK(n4082), .RN(n3995),
.Q(DmP_mant_SFG_SWR[34]), .QN(n3729) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_10_ ( .D(n1808), .CK(n4013), .RN(n3933),
.Q(intDY_EWSW[10]), .QN(n3728) );
DFFRX2TS SGF_STAGE_FLAGS_Q_reg_1_ ( .D(n1278), .CK(n4063), .RN(n3980), .Q(
n3675), .QN(n3903) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_48_ ( .D(n1463), .CK(n4043), .RN(n3962), .Q(
DMP_SFG[48]), .QN(n3727) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_46_ ( .D(n1469), .CK(n4042), .RN(n3962), .Q(
DMP_SFG[46]), .QN(n3726) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_30_ ( .D(n1517), .CK(n2022), .RN(n3957), .Q(
DMP_SFG[30]), .QN(n3725) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_20_ ( .D(n1547), .CK(n4037), .RN(n3954), .Q(
DMP_SFG[20]), .QN(n3724) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_18_ ( .D(n1553), .CK(n4039), .RN(n3953), .Q(
DMP_SFG[18]), .QN(n3723) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_16_ ( .D(n1559), .CK(n2023), .RN(n3953), .Q(
DMP_SFG[16]), .QN(n3722) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_14_ ( .D(n1565), .CK(n4081), .RN(n3952), .Q(
DMP_SFG[14]), .QN(n3721) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_12_ ( .D(n1571), .CK(n4036), .RN(n3952), .Q(
DMP_SFG[12]), .QN(n3720) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_10_ ( .D(n1577), .CK(n4036), .RN(n3951), .Q(
DMP_SFG[10]), .QN(n3719) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_4_ ( .D(n1595), .CK(n4037), .RN(n3949), .Q(
DMP_SFG[4]), .QN(n3718) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_2_ ( .D(n1601), .CK(n4039), .RN(n3949), .Q(
DMP_SFG[2]), .QN(n3717) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_35_ ( .D(n1121), .CK(n4082), .RN(n3995),
.Q(DmP_mant_SFG_SWR[35]), .QN(n3716) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_5_ ( .D(n1878), .CK(n4006), .RN(n3923),
.Q(intDX_EWSW[5]), .QN(n3714) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_0_ ( .D(n1883), .CK(n4006), .RN(n3923),
.Q(intDX_EWSW[0]), .QN(n3713) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_9_ ( .D(n1260), .CK(n4071), .RN(n3982),
.Q(Raw_mant_NRM_SWR[9]), .QN(n3712) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_5_ ( .D(n1264), .CK(n4007), .RN(n3981),
.Q(Raw_mant_NRM_SWR[5]), .QN(n3711) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_18_ ( .D(n1865), .CK(n4067), .RN(n3924),
.Q(intDX_EWSW[18]), .QN(n3710) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_13_ ( .D(n1870), .CK(n4069), .RN(n3924),
.Q(intDX_EWSW[13]), .QN(n3709) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_49_ ( .D(n1220), .CK(n4073), .RN(n3986),
.Q(Raw_mant_NRM_SWR[49]), .QN(n3708) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_23_ ( .D(n1246), .CK(n4067), .RN(n3983),
.Q(Raw_mant_NRM_SWR[23]), .QN(n3707) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_27_ ( .D(n1856), .CK(n4008), .RN(n3925),
.Q(intDX_EWSW[27]), .QN(n3706) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_44_ ( .D(n1225), .CK(n4071), .RN(n3985),
.Q(Raw_mant_NRM_SWR[44]), .QN(n3705) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_45_ ( .D(n1224), .CK(n4069), .RN(n3985),
.Q(Raw_mant_NRM_SWR[45]), .QN(n3704) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_12_ ( .D(n1257), .CK(n4069), .RN(n3982),
.Q(Raw_mant_NRM_SWR[12]), .QN(n3703) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_34_ ( .D(n1235), .CK(n4075), .RN(n3984),
.Q(Raw_mant_NRM_SWR[34]), .QN(n3702) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_6_ ( .D(n1877), .CK(n4006), .RN(n3923),
.Q(intDX_EWSW[6]), .QN(n3701) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_0_ ( .D(n1156), .CK(n4066), .RN(n3991),
.Q(DmP_mant_SFG_SWR[0]), .QN(n3700) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_35_ ( .D(n1234), .CK(n4070), .RN(n3984),
.Q(Raw_mant_NRM_SWR[35]), .QN(n3699) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_41_ ( .D(n1228), .CK(n2024), .RN(n3985),
.Q(Raw_mant_NRM_SWR[41]), .QN(n3698) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_44_ ( .D(n1112), .CK(n4085), .RN(n3996),
.Q(DmP_mant_SFG_SWR[44]), .QN(n3697) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_30_ ( .D(n1126), .CK(n4036), .RN(n3994),
.Q(DmP_mant_SFG_SWR[30]), .QN(n3696) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_28_ ( .D(n1128), .CK(n4037), .RN(n3994),
.Q(DmP_mant_SFG_SWR[28]), .QN(n3695) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_26_ ( .D(n1130), .CK(n4039), .RN(n3994),
.Q(DmP_mant_SFG_SWR[26]), .QN(n3694) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_24_ ( .D(n1132), .CK(n4081), .RN(n3994),
.Q(DmP_mant_SFG_SWR[24]), .QN(n3693) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_10_ ( .D(n1146), .CK(n4054), .RN(n3992),
.Q(DmP_mant_SFG_SWR[10]), .QN(n3692) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_8_ ( .D(n1148), .CK(n4079), .RN(n3992),
.Q(DmP_mant_SFG_SWR[8]), .QN(n3691) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_40_ ( .D(n1229), .CK(n4007), .RN(n3985),
.Q(Raw_mant_NRM_SWR[40]), .QN(n3690) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_30_ ( .D(n1788), .CK(n4015), .RN(n3930),
.Q(intDY_EWSW[30]), .QN(n3689) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_29_ ( .D(n1240), .CK(n4072), .RN(n3984),
.Q(Raw_mant_NRM_SWR[29]), .QN(n3688) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_25_ ( .D(n1793), .CK(n4008), .RN(n3929),
.Q(intDY_EWSW[25]), .QN(n3687) );
DFFRX2TS SGF_STAGE_DmP_mant_Q_reg_2_ ( .D(n1154), .CK(n2272), .RN(n3992),
.QN(n3686) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_38_ ( .D(n1231), .CK(n2024), .RN(n3984),
.Q(Raw_mant_NRM_SWR[38]), .QN(n3685) );
DFFRX2TS inst_FSM_INPUT_ENABLE_state_reg_reg_1_ ( .D(
inst_FSM_INPUT_ENABLE_state_next_1_), .CK(n4062), .RN(n3922), .Q(
inst_FSM_INPUT_ENABLE_state_reg[1]), .QN(n3684) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_19_ ( .D(n1250), .CK(n4068), .RN(n3983),
.Q(Raw_mant_NRM_SWR[19]), .QN(n3683) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_16_ ( .D(n1253), .CK(n4007), .RN(n3982),
.Q(Raw_mant_NRM_SWR[16]), .QN(n3682) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_31_ ( .D(n1787), .CK(n4017), .RN(n3955),
.Q(intDY_EWSW[31]), .QN(n3681) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_23_ ( .D(n1860), .CK(n4017), .RN(n3925),
.Q(intDX_EWSW[23]), .QN(n3680) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_33_ ( .D(n1785), .CK(n4014), .RN(n3936),
.Q(intDY_EWSW[33]), .QN(n3678) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_47_ ( .D(n1222), .CK(n4075), .RN(n3985),
.Q(Raw_mant_NRM_SWR[47]), .QN(n3677) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_51_ ( .D(n1218), .CK(n4070), .RN(n3986),
.Q(Raw_mant_NRM_SWR[51]), .QN(n3676) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_52_ ( .D(n1104), .CK(n4084), .RN(n3997),
.Q(DmP_mant_SFG_SWR[52]), .QN(n3674) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_46_ ( .D(n1110), .CK(n4084), .RN(n3996),
.Q(DmP_mant_SFG_SWR[46]), .QN(n3673) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_41_ ( .D(n1777), .CK(n2271), .RN(n3932),
.Q(intDY_EWSW[41]), .QN(n3672) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_59_ ( .D(n1759), .CK(n4077), .RN(n3934),
.Q(intDY_EWSW[59]), .QN(n3671) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_20_ ( .D(n1249), .CK(n4067), .RN(n3983),
.Q(Raw_mant_NRM_SWR[20]), .QN(n3670) );
DFFRX2TS inst_ShiftRegister_Q_reg_6_ ( .D(n1890), .CK(n4005), .RN(n3922),
.Q(Shift_reg_FLAGS_7_6), .QN(n3679) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_1_ ( .D(n1268), .CK(n4067), .RN(n3981),
.Q(Raw_mant_NRM_SWR[1]), .QN(n3669) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_46_ ( .D(n1772), .CK(n4017), .RN(n3936),
.Q(intDY_EWSW[46]), .QN(n3668) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_53_ ( .D(n1765), .CK(n4015), .RN(n3933),
.Q(intDY_EWSW[53]), .QN(n3667) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_55_ ( .D(n1763), .CK(n4077), .RN(n3934),
.Q(intDY_EWSW[55]), .QN(n3666) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_40_ ( .D(n1778), .CK(n4018), .RN(n3932),
.Q(intDY_EWSW[40]), .QN(n3665) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_51_ ( .D(n1767), .CK(n4008), .RN(n3946),
.Q(intDY_EWSW[51]), .QN(n3664) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_35_ ( .D(n1783), .CK(n4077), .RN(n3932),
.Q(intDY_EWSW[35]), .QN(n3663) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_43_ ( .D(n1775), .CK(n4016), .RN(n3932),
.Q(intDY_EWSW[43]), .QN(n3662) );
DFFRXLTS Ready_reg_Q_reg_0_ ( .D(n2037), .CK(n4040), .RN(n2043), .Q(ready)
);
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n1288), .CK(n2028), .RN(n3979), .Q(
underflow_flag) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(n1281), .CK(n4063), .RN(n3980), .Q(
zero_flag) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_63_ ( .D(n1270), .CK(n4068), .RN(n3981),
.Q(final_result_ieee[63]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_62_ ( .D(n1676), .CK(n4010), .RN(n3997),
.Q(final_result_ieee[62]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_25_ ( .D(n1208), .CK(n4073), .RN(n3986),
.Q(final_result_ieee[25]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_20_ ( .D(n1199), .CK(n4068), .RN(n3987),
.Q(final_result_ieee[20]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_30_ ( .D(n1198), .CK(n4074), .RN(n3987),
.Q(final_result_ieee[30]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_19_ ( .D(n1197), .CK(n4074), .RN(n3987),
.Q(final_result_ieee[19]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_31_ ( .D(n1196), .CK(n4074), .RN(n3987),
.Q(final_result_ieee[31]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_18_ ( .D(n1195), .CK(n4074), .RN(n3987),
.Q(final_result_ieee[18]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_32_ ( .D(n1194), .CK(n4074), .RN(n3988),
.Q(final_result_ieee[32]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_16_ ( .D(n1191), .CK(n4072), .RN(n3988),
.Q(final_result_ieee[16]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_34_ ( .D(n1190), .CK(n4009), .RN(n3988),
.Q(final_result_ieee[34]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_15_ ( .D(n1189), .CK(n4073), .RN(n3988),
.Q(final_result_ieee[15]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_35_ ( .D(n1188), .CK(n4075), .RN(n3988),
.Q(final_result_ieee[35]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_14_ ( .D(n1187), .CK(n4070), .RN(n3988),
.Q(final_result_ieee[14]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_36_ ( .D(n1186), .CK(n4072), .RN(n3988),
.Q(final_result_ieee[36]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_37_ ( .D(n1184), .CK(n4073), .RN(n3989),
.Q(final_result_ieee[37]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_12_ ( .D(n1183), .CK(n2266), .RN(n3989),
.Q(final_result_ieee[12]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_38_ ( .D(n1182), .CK(n4046), .RN(n3989),
.Q(final_result_ieee[38]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_11_ ( .D(n1181), .CK(n4045), .RN(n3989),
.Q(final_result_ieee[11]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_39_ ( .D(n1180), .CK(n4043), .RN(n3989),
.Q(final_result_ieee[39]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_10_ ( .D(n1179), .CK(n4048), .RN(n3989),
.Q(final_result_ieee[10]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_40_ ( .D(n1178), .CK(n2266), .RN(n3989),
.Q(final_result_ieee[40]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_4_ ( .D(n1167), .CK(n4077), .RN(n3990),
.Q(final_result_ieee[4]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_46_ ( .D(n1166), .CK(n2271), .RN(n3990),
.Q(final_result_ieee[46]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_3_ ( .D(n1165), .CK(n4016), .RN(n3990),
.Q(final_result_ieee[3]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_47_ ( .D(n1164), .CK(n4021), .RN(n3991),
.Q(final_result_ieee[47]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_2_ ( .D(n1163), .CK(n4064), .RN(n3991),
.Q(final_result_ieee[2]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_48_ ( .D(n1162), .CK(n4061), .RN(n3991),
.Q(final_result_ieee[48]) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(n1287), .CK(n4059), .RN(n3979), .Q(
overflow_flag) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_52_ ( .D(n1686), .CK(n4028), .RN(n3999),
.Q(final_result_ieee[52]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_53_ ( .D(n1685), .CK(n4025), .RN(n3998),
.Q(final_result_ieee[53]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_54_ ( .D(n1684), .CK(n4027), .RN(n2044),
.Q(final_result_ieee[54]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_55_ ( .D(n1683), .CK(n4029), .RN(n3999),
.Q(final_result_ieee[55]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_56_ ( .D(n1682), .CK(n2025), .RN(n3997),
.Q(final_result_ieee[56]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_57_ ( .D(n1681), .CK(n4023), .RN(n3997),
.Q(final_result_ieee[57]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_58_ ( .D(n1680), .CK(n4024), .RN(n3997),
.Q(final_result_ieee[58]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_59_ ( .D(n1679), .CK(n4029), .RN(n3997),
.Q(final_result_ieee[59]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_60_ ( .D(n1678), .CK(n4026), .RN(n3997),
.Q(final_result_ieee[60]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_61_ ( .D(n1677), .CK(n4010), .RN(n3997),
.Q(final_result_ieee[61]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_13_ ( .D(n1185), .CK(n4075), .RN(n3988),
.Q(final_result_ieee[13]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_0_ ( .D(n1608), .CK(n4035), .RN(n3948), .Q(
DMP_SHT2_EWSW[0]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_2_ ( .D(n1602), .CK(n4081), .RN(n3949), .Q(
DMP_SHT2_EWSW[2]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_4_ ( .D(n1596), .CK(n2265), .RN(n3949), .Q(
DMP_SHT2_EWSW[4]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_6_ ( .D(n1590), .CK(n4033), .RN(n3950), .Q(
DMP_SHT2_EWSW[6]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_8_ ( .D(n1584), .CK(n4038), .RN(n3950), .Q(
DMP_SHT2_EWSW[8]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_10_ ( .D(n1578), .CK(n4037), .RN(n3951), .Q(
DMP_SHT2_EWSW[10]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_12_ ( .D(n1572), .CK(n4037), .RN(n3952), .Q(
DMP_SHT2_EWSW[12]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_14_ ( .D(n1566), .CK(n4039), .RN(n3952), .Q(
DMP_SHT2_EWSW[14]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_16_ ( .D(n1560), .CK(n4033), .RN(n3953), .Q(
DMP_SHT2_EWSW[16]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_18_ ( .D(n1554), .CK(n4038), .RN(n3953), .Q(
DMP_SHT2_EWSW[18]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_20_ ( .D(n1548), .CK(n4036), .RN(n3954), .Q(
DMP_SHT2_EWSW[20]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_22_ ( .D(n1542), .CK(n4040), .RN(n3936), .Q(
DMP_SHT2_EWSW[22]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_24_ ( .D(n1536), .CK(n4047), .RN(n3933), .Q(
DMP_SHT2_EWSW[24]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_26_ ( .D(n1530), .CK(n4042), .RN(n3956), .Q(
DMP_SHT2_EWSW[26]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_28_ ( .D(n1524), .CK(n2022), .RN(n3956), .Q(
DMP_SHT2_EWSW[28]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_30_ ( .D(n1518), .CK(n4042), .RN(n3957), .Q(
DMP_SHT2_EWSW[30]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_32_ ( .D(n1512), .CK(n2266), .RN(n3958), .Q(
DMP_SHT2_EWSW[32]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_34_ ( .D(n1506), .CK(n2266), .RN(n3958), .Q(
DMP_SHT2_EWSW[34]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_36_ ( .D(n1500), .CK(n4044), .RN(n3959), .Q(
DMP_SHT2_EWSW[36]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_38_ ( .D(n1494), .CK(n4044), .RN(n3959), .Q(
DMP_SHT2_EWSW[38]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_40_ ( .D(n1488), .CK(n4043), .RN(n3960), .Q(
DMP_SHT2_EWSW[40]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_42_ ( .D(n1482), .CK(n4048), .RN(n3961), .Q(
DMP_SHT2_EWSW[42]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_44_ ( .D(n1476), .CK(n4046), .RN(n3961), .Q(
DMP_SHT2_EWSW[44]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_46_ ( .D(n1470), .CK(n4047), .RN(n3962), .Q(
DMP_SHT2_EWSW[46]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_48_ ( .D(n1464), .CK(n4042), .RN(n3962), .Q(
DMP_SHT2_EWSW[48]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_50_ ( .D(n1458), .CK(n4048), .RN(n3963), .Q(
DMP_SHT2_EWSW[50]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_51_ ( .D(n1455), .CK(n2266), .RN(n3963), .Q(
DMP_SHT2_EWSW[51]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_25_ ( .D(n1347), .CK(n2028), .RN(n3973),
.Q(DmP_mant_SHT1_SW[25]) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_1_ ( .D(n1279), .CK(n4066), .RN(n3980), .Q(
OP_FLAG_SHT2) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_1_ ( .D(n1612), .CK(n2023), .RN(n3948), .Q(
OP_FLAG_EXP) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_0_ ( .D(n1609), .CK(n4031), .RN(n3948), .Q(
DMP_SHT1_EWSW[0]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_1_ ( .D(n1606), .CK(n4033), .RN(n3948), .Q(
DMP_SHT1_EWSW[1]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_1_ ( .D(n1605), .CK(n4038), .RN(n3948), .Q(
DMP_SHT2_EWSW[1]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_2_ ( .D(n1603), .CK(n4036), .RN(n3948), .Q(
DMP_SHT1_EWSW[2]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_3_ ( .D(n1600), .CK(n4034), .RN(n3949), .Q(
DMP_SHT1_EWSW[3]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_3_ ( .D(n1599), .CK(n4034), .RN(n3949), .Q(
DMP_SHT2_EWSW[3]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_4_ ( .D(n1597), .CK(n4034), .RN(n3949), .Q(
DMP_SHT1_EWSW[4]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_5_ ( .D(n1594), .CK(n4034), .RN(n3949), .Q(
DMP_SHT1_EWSW[5]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_5_ ( .D(n1593), .CK(n4035), .RN(n3949), .Q(
DMP_SHT2_EWSW[5]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_6_ ( .D(n1591), .CK(n4033), .RN(n3950), .Q(
DMP_SHT1_EWSW[6]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_7_ ( .D(n1588), .CK(n4038), .RN(n3950), .Q(
DMP_SHT1_EWSW[7]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_7_ ( .D(n1587), .CK(n4035), .RN(n3950), .Q(
DMP_SHT2_EWSW[7]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_8_ ( .D(n1585), .CK(n4033), .RN(n3950), .Q(
DMP_SHT1_EWSW[8]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_9_ ( .D(n1582), .CK(n4039), .RN(n3951), .Q(
DMP_SHT1_EWSW[9]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_9_ ( .D(n1581), .CK(n4081), .RN(n3951), .Q(
DMP_SHT2_EWSW[9]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_10_ ( .D(n1579), .CK(n2265), .RN(n3951), .Q(
DMP_SHT1_EWSW[10]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_11_ ( .D(n1576), .CK(n2265), .RN(n3951), .Q(
DMP_SHT1_EWSW[11]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_11_ ( .D(n1575), .CK(n2265), .RN(n3951), .Q(
DMP_SHT2_EWSW[11]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_12_ ( .D(n1573), .CK(n4081), .RN(n3951), .Q(
DMP_SHT1_EWSW[12]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_13_ ( .D(n1570), .CK(n2265), .RN(n3952), .Q(
DMP_SHT1_EWSW[13]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_13_ ( .D(n1569), .CK(n4036), .RN(n3952), .Q(
DMP_SHT2_EWSW[13]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_14_ ( .D(n1567), .CK(n4037), .RN(n3952), .Q(
DMP_SHT1_EWSW[14]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_15_ ( .D(n1564), .CK(n4039), .RN(n3952), .Q(
DMP_SHT1_EWSW[15]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_15_ ( .D(n1563), .CK(n4035), .RN(n3952), .Q(
DMP_SHT2_EWSW[15]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_16_ ( .D(n1561), .CK(n2023), .RN(n3953), .Q(
DMP_SHT1_EWSW[16]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_17_ ( .D(n1558), .CK(n4033), .RN(n3953), .Q(
DMP_SHT1_EWSW[17]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_17_ ( .D(n1557), .CK(n4038), .RN(n3953), .Q(
DMP_SHT2_EWSW[17]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_18_ ( .D(n1555), .CK(n4035), .RN(n3953), .Q(
DMP_SHT1_EWSW[18]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_19_ ( .D(n1552), .CK(n4037), .RN(n3954), .Q(
DMP_SHT1_EWSW[19]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_19_ ( .D(n1551), .CK(n4039), .RN(n3954), .Q(
DMP_SHT2_EWSW[19]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_20_ ( .D(n1549), .CK(n4081), .RN(n3954), .Q(
DMP_SHT1_EWSW[20]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_21_ ( .D(n1546), .CK(n2265), .RN(n3954), .Q(
DMP_SHT1_EWSW[21]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_21_ ( .D(n1545), .CK(n4036), .RN(n3954), .Q(
DMP_SHT2_EWSW[21]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_22_ ( .D(n1543), .CK(n4042), .RN(n3954), .Q(
DMP_SHT1_EWSW[22]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_23_ ( .D(n1540), .CK(n4041), .RN(n3931), .Q(
DMP_SHT1_EWSW[23]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_23_ ( .D(n1539), .CK(n4012), .RN(n3929), .Q(
DMP_SHT2_EWSW[23]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_24_ ( .D(n1537), .CK(n2022), .RN(n3955), .Q(
DMP_SHT1_EWSW[24]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_25_ ( .D(n1534), .CK(n4040), .RN(n3946), .Q(
DMP_SHT1_EWSW[25]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_25_ ( .D(n1533), .CK(n4040), .RN(n3930), .Q(
DMP_SHT2_EWSW[25]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_26_ ( .D(n1531), .CK(n4047), .RN(n3956), .Q(
DMP_SHT1_EWSW[26]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_27_ ( .D(n1528), .CK(n4042), .RN(n3956), .Q(
DMP_SHT1_EWSW[27]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_27_ ( .D(n1527), .CK(n4044), .RN(n3956), .Q(
DMP_SHT2_EWSW[27]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_28_ ( .D(n1525), .CK(n4044), .RN(n3956), .Q(
DMP_SHT1_EWSW[28]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_29_ ( .D(n1522), .CK(n2022), .RN(n3957), .Q(
DMP_SHT1_EWSW[29]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_29_ ( .D(n1521), .CK(n4040), .RN(n3957), .Q(
DMP_SHT2_EWSW[29]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_30_ ( .D(n1519), .CK(n4047), .RN(n3957), .Q(
DMP_SHT1_EWSW[30]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_31_ ( .D(n1516), .CK(n4042), .RN(n3957), .Q(
DMP_SHT1_EWSW[31]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_31_ ( .D(n1515), .CK(n2022), .RN(n3957), .Q(
DMP_SHT2_EWSW[31]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_32_ ( .D(n1513), .CK(n2266), .RN(n3957), .Q(
DMP_SHT1_EWSW[32]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_33_ ( .D(n1510), .CK(n2266), .RN(n3958), .Q(
DMP_SHT1_EWSW[33]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_33_ ( .D(n1509), .CK(n4046), .RN(n3958), .Q(
DMP_SHT2_EWSW[33]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_34_ ( .D(n1507), .CK(n4045), .RN(n3958), .Q(
DMP_SHT1_EWSW[34]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_35_ ( .D(n1504), .CK(n4043), .RN(n3958), .Q(
DMP_SHT1_EWSW[35]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_35_ ( .D(n1503), .CK(n4044), .RN(n3958), .Q(
DMP_SHT2_EWSW[35]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_36_ ( .D(n1501), .CK(n4044), .RN(n3959), .Q(
DMP_SHT1_EWSW[36]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_37_ ( .D(n1498), .CK(n4044), .RN(n3959), .Q(
DMP_SHT1_EWSW[37]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_37_ ( .D(n1497), .CK(n4044), .RN(n3959), .Q(
DMP_SHT2_EWSW[37]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_38_ ( .D(n1495), .CK(n4044), .RN(n3959), .Q(
DMP_SHT1_EWSW[38]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_39_ ( .D(n1492), .CK(n4048), .RN(n3960), .Q(
DMP_SHT1_EWSW[39]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_39_ ( .D(n1491), .CK(n4046), .RN(n3960), .Q(
DMP_SHT2_EWSW[39]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_40_ ( .D(n1489), .CK(n4045), .RN(n3960), .Q(
DMP_SHT1_EWSW[40]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_41_ ( .D(n1486), .CK(n4043), .RN(n3960), .Q(
DMP_SHT1_EWSW[41]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_41_ ( .D(n1485), .CK(n4048), .RN(n3960), .Q(
DMP_SHT2_EWSW[41]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_42_ ( .D(n1483), .CK(n4045), .RN(n3960), .Q(
DMP_SHT1_EWSW[42]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_43_ ( .D(n1480), .CK(n4043), .RN(n3961), .Q(
DMP_SHT1_EWSW[43]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_43_ ( .D(n1479), .CK(n4048), .RN(n3961), .Q(
DMP_SHT2_EWSW[43]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_44_ ( .D(n1477), .CK(n4046), .RN(n3961), .Q(
DMP_SHT1_EWSW[44]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_45_ ( .D(n1474), .CK(n4045), .RN(n3961), .Q(
DMP_SHT1_EWSW[45]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_45_ ( .D(n1473), .CK(n4041), .RN(n3961), .Q(
DMP_SHT2_EWSW[45]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_46_ ( .D(n1471), .CK(n2022), .RN(n3962), .Q(
DMP_SHT1_EWSW[46]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_47_ ( .D(n1468), .CK(n4012), .RN(n3962), .Q(
DMP_SHT1_EWSW[47]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_47_ ( .D(n1467), .CK(n4040), .RN(n3962), .Q(
DMP_SHT2_EWSW[47]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_48_ ( .D(n1465), .CK(n4047), .RN(n3962), .Q(
DMP_SHT1_EWSW[48]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_49_ ( .D(n1462), .CK(n4046), .RN(n3963), .Q(
DMP_SHT1_EWSW[49]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_49_ ( .D(n1461), .CK(n4045), .RN(n3963), .Q(
DMP_SHT2_EWSW[49]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_50_ ( .D(n1459), .CK(n4043), .RN(n3963), .Q(
DMP_SHT1_EWSW[50]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_51_ ( .D(n1456), .CK(n4048), .RN(n3963), .Q(
DMP_SHT1_EWSW[51]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_52_ ( .D(n1453), .CK(n4049), .RN(n3963), .Q(
DMP_SHT1_EWSW[52]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_52_ ( .D(n1452), .CK(n4050), .RN(n3964), .Q(
DMP_SHT2_EWSW[52]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_52_ ( .D(n1451), .CK(n4011), .RN(n3964), .Q(
DMP_SFG[52]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_53_ ( .D(n1448), .CK(n4051), .RN(n3964), .Q(
DMP_SHT1_EWSW[53]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_53_ ( .D(n1447), .CK(n4053), .RN(n3964), .Q(
DMP_SHT2_EWSW[53]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_53_ ( .D(n1446), .CK(n2026), .RN(n3964), .Q(
DMP_SFG[53]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_54_ ( .D(n1443), .CK(n4011), .RN(n3964), .Q(
DMP_SHT1_EWSW[54]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_54_ ( .D(n1442), .CK(n4051), .RN(n3964), .Q(
DMP_SHT2_EWSW[54]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_54_ ( .D(n1441), .CK(n4053), .RN(n3964), .Q(
DMP_SFG[54]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_55_ ( .D(n1438), .CK(n2026), .RN(n3965), .Q(
DMP_SHT1_EWSW[55]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_55_ ( .D(n1437), .CK(n4049), .RN(n3965), .Q(
DMP_SHT2_EWSW[55]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_55_ ( .D(n1436), .CK(n4050), .RN(n3965), .Q(
DMP_SFG[55]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_56_ ( .D(n1433), .CK(n4053), .RN(n3965), .Q(
DMP_SHT1_EWSW[56]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_56_ ( .D(n1432), .CK(n2026), .RN(n3965), .Q(
DMP_SHT2_EWSW[56]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_56_ ( .D(n1431), .CK(n4049), .RN(n3965), .Q(
DMP_SFG[56]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_57_ ( .D(n1428), .CK(n4050), .RN(n3965), .Q(
DMP_SHT1_EWSW[57]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_57_ ( .D(n1427), .CK(n4011), .RN(n3966), .Q(
DMP_SHT2_EWSW[57]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_57_ ( .D(n1426), .CK(n2026), .RN(n3966), .Q(
DMP_SFG[57]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_58_ ( .D(n1423), .CK(n4054), .RN(n3966), .Q(
DMP_SHT1_EWSW[58]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_58_ ( .D(n1422), .CK(n4079), .RN(n3966), .Q(
DMP_SHT2_EWSW[58]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_58_ ( .D(n1421), .CK(n4055), .RN(n3966), .Q(
DMP_SFG[58]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_59_ ( .D(n1418), .CK(n4052), .RN(n3966), .Q(
DMP_SHT1_EWSW[59]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_59_ ( .D(n1417), .CK(n4057), .RN(n3966), .Q(
DMP_SHT2_EWSW[59]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_59_ ( .D(n1416), .CK(n4054), .RN(n3966), .Q(
DMP_SFG[59]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_60_ ( .D(n1413), .CK(n4011), .RN(n3967), .Q(
DMP_SHT1_EWSW[60]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_60_ ( .D(n1412), .CK(n2026), .RN(n3967), .Q(
DMP_SHT2_EWSW[60]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_60_ ( .D(n1411), .CK(n4049), .RN(n3967), .Q(
DMP_SFG[60]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_61_ ( .D(n1408), .CK(n4050), .RN(n3967), .Q(
DMP_SHT1_EWSW[61]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_61_ ( .D(n1407), .CK(n4011), .RN(n3967), .Q(
DMP_SHT2_EWSW[61]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_61_ ( .D(n1406), .CK(n2026), .RN(n3967), .Q(
DMP_SFG[61]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_62_ ( .D(n1403), .CK(n4055), .RN(n3967), .Q(
DMP_SHT1_EWSW[62]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_62_ ( .D(n1402), .CK(n4052), .RN(n3968), .Q(
DMP_SHT2_EWSW[62]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_62_ ( .D(n1401), .CK(n4054), .RN(n3968), .Q(
DMP_SFG[62]) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_0_ ( .D(n1286), .CK(n4062), .RN(n3979), .Q(
ZERO_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_0_ ( .D(n1285), .CK(n4005), .RN(n3979), .Q(
ZERO_FLAG_SHT2) );
DFFRXLTS SGF_STAGE_FLAGS_Q_reg_0_ ( .D(n1284), .CK(n4062), .RN(n3979), .Q(
ZERO_FLAG_SFG) );
DFFRXLTS NRM_STAGE_FLAGS_Q_reg_0_ ( .D(n1283), .CK(n4064), .RN(n3979), .Q(
ZERO_FLAG_NRM) );
DFFRXLTS SFT2FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(n1282), .CK(n4061), .RN(n3979),
.Q(ZERO_FLAG_SHT1SHT2) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_1_ ( .D(n1280), .CK(n2272), .RN(n3980), .Q(
OP_FLAG_SHT1) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_2_ ( .D(n1275), .CK(n2272), .RN(n3980), .Q(
SIGN_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_2_ ( .D(n1274), .CK(n2272), .RN(n3980), .Q(
SIGN_FLAG_SHT2) );
DFFRXLTS SGF_STAGE_FLAGS_Q_reg_2_ ( .D(n1273), .CK(n2024), .RN(n3980), .Q(
SIGN_FLAG_SFG) );
DFFRXLTS NRM_STAGE_FLAGS_Q_reg_1_ ( .D(n1272), .CK(n4007), .RN(n3980), .Q(
SIGN_FLAG_NRM) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_11_ ( .D(n1210), .CK(n4075), .RN(n3946),
.Q(LZD_output_NRM2_EW[0]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_24_ ( .D(n1207), .CK(n4009), .RN(n3986),
.Q(final_result_ieee[24]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_26_ ( .D(n1206), .CK(n4070), .RN(n3986),
.Q(final_result_ieee[26]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_23_ ( .D(n1205), .CK(n4072), .RN(n3986),
.Q(final_result_ieee[23]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_27_ ( .D(n1204), .CK(n4009), .RN(n3987),
.Q(final_result_ieee[27]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_22_ ( .D(n1203), .CK(n4074), .RN(n3987),
.Q(final_result_ieee[22]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_28_ ( .D(n1202), .CK(n4074), .RN(n3987),
.Q(final_result_ieee[28]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_21_ ( .D(n1201), .CK(n4074), .RN(n3987),
.Q(final_result_ieee[21]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_29_ ( .D(n1200), .CK(n4074), .RN(n3987),
.Q(final_result_ieee[29]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_17_ ( .D(n1193), .CK(n4009), .RN(n3988),
.Q(final_result_ieee[17]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_33_ ( .D(n1192), .CK(n4070), .RN(n3988),
.Q(final_result_ieee[33]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_9_ ( .D(n1177), .CK(n4046), .RN(n3989),
.Q(final_result_ieee[9]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_41_ ( .D(n1176), .CK(n4076), .RN(n3989),
.Q(final_result_ieee[41]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_8_ ( .D(n1175), .CK(n4076), .RN(n3989),
.Q(final_result_ieee[8]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_42_ ( .D(n1174), .CK(n4076), .RN(n3990),
.Q(final_result_ieee[42]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_7_ ( .D(n1173), .CK(n4018), .RN(n3990),
.Q(final_result_ieee[7]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_43_ ( .D(n1172), .CK(n4077), .RN(n3990),
.Q(final_result_ieee[43]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_6_ ( .D(n1171), .CK(n2271), .RN(n3990),
.Q(final_result_ieee[6]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_44_ ( .D(n1170), .CK(n4019), .RN(n3990),
.Q(final_result_ieee[44]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_5_ ( .D(n1169), .CK(n4019), .RN(n3990),
.Q(final_result_ieee[5]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_45_ ( .D(n1168), .CK(n4019), .RN(n3990),
.Q(final_result_ieee[45]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_1_ ( .D(n1161), .CK(n2272), .RN(n3991),
.Q(final_result_ieee[1]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_49_ ( .D(n1160), .CK(n4063), .RN(n3991),
.Q(final_result_ieee[49]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_0_ ( .D(n1159), .CK(n4066), .RN(n3991),
.Q(final_result_ieee[0]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_50_ ( .D(n1158), .CK(n4064), .RN(n3991),
.Q(final_result_ieee[50]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_51_ ( .D(n1157), .CK(n4061), .RN(n3991),
.Q(final_result_ieee[51]) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_0_ ( .D(n1611), .CK(n4035), .RN(n3948), .Q(
ZERO_FLAG_EXP) );
DFFRXLTS SFT2FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n1271), .CK(n4067), .RN(n3980),
.Q(SIGN_FLAG_SHT1SHT2) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_13_ ( .D(n1214), .CK(n4072), .RN(n3999),
.Q(LZD_output_NRM2_EW[2]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_15_ ( .D(n1211), .CK(n4073), .RN(n3998),
.Q(LZD_output_NRM2_EW[4]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_16_ ( .D(n1209), .CK(n4075), .RN(n3999),
.Q(LZD_output_NRM2_EW[5]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_24_ ( .D(n1349), .CK(n4062), .RN(n3973),
.Q(DmP_mant_SHT1_SW[24]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_51_ ( .D(n1295), .CK(n2272), .RN(n3978),
.Q(DmP_mant_SHT1_SW[51]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_0_ ( .D(n1450), .CK(n4049), .RN(n3964), .Q(
DMP_exp_NRM_EW[0]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_1_ ( .D(n1445), .CK(n4050), .RN(n3964), .Q(
DMP_exp_NRM_EW[1]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_2_ ( .D(n1440), .CK(n4011), .RN(n3965), .Q(
DMP_exp_NRM_EW[2]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_3_ ( .D(n1435), .CK(n4051), .RN(n3965), .Q(
DMP_exp_NRM_EW[3]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_4_ ( .D(n1430), .CK(n4049), .RN(n3965), .Q(
DMP_exp_NRM_EW[4]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_5_ ( .D(n1425), .CK(n4050), .RN(n3966), .Q(
DMP_exp_NRM_EW[5]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_6_ ( .D(n1420), .CK(n4079), .RN(n3966), .Q(
DMP_exp_NRM_EW[6]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_7_ ( .D(n1415), .CK(n4057), .RN(n3967), .Q(
DMP_exp_NRM_EW[7]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_8_ ( .D(n1410), .CK(n4049), .RN(n3967), .Q(
DMP_exp_NRM_EW[8]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_9_ ( .D(n1405), .CK(n4050), .RN(n3967), .Q(
DMP_exp_NRM_EW[9]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_10_ ( .D(n1400), .CK(n4079), .RN(n3968),
.Q(DMP_exp_NRM_EW[10]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_12_ ( .D(n1212), .CK(n4070), .RN(n3998),
.Q(LZD_output_NRM2_EW[1]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_0_ ( .D(n1692), .CK(n2273), .RN(n3941),
.Q(Shift_amount_SHT1_EWR[0]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_2_ ( .D(n1690), .CK(n4030), .RN(n3941),
.Q(Shift_amount_SHT1_EWR[2]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_3_ ( .D(n1689), .CK(n4027), .RN(n3941),
.Q(Shift_amount_SHT1_EWR[3]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_5_ ( .D(n1687), .CK(n4028), .RN(n3941),
.Q(Shift_amount_SHT1_EWR[5]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_1_ ( .D(n1691), .CK(n2273), .RN(n3941),
.Q(Shift_amount_SHT1_EWR[1]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_4_ ( .D(n1688), .CK(n4025), .RN(n3941),
.Q(Shift_amount_SHT1_EWR[4]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_0_ ( .D(n1397), .CK(n4057), .RN(n3968),
.Q(DmP_mant_SHT1_SW[0]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_1_ ( .D(n1395), .CK(n4055), .RN(n3968),
.Q(DmP_mant_SHT1_SW[1]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_2_ ( .D(n1393), .CK(n4054), .RN(n3968),
.Q(DmP_mant_SHT1_SW[2]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_3_ ( .D(n1391), .CK(n4079), .RN(n3969),
.Q(DmP_mant_SHT1_SW[3]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_4_ ( .D(n1389), .CK(n4057), .RN(n3969),
.Q(DmP_mant_SHT1_SW[4]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_5_ ( .D(n1387), .CK(n4055), .RN(n3969),
.Q(DmP_mant_SHT1_SW[5]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_6_ ( .D(n1385), .CK(n4052), .RN(n3969),
.Q(DmP_mant_SHT1_SW[6]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_7_ ( .D(n1383), .CK(n4011), .RN(n3969),
.Q(DmP_mant_SHT1_SW[7]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_8_ ( .D(n1381), .CK(n4056), .RN(n3970),
.Q(DmP_mant_SHT1_SW[8]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_9_ ( .D(n1379), .CK(n4056), .RN(n3970),
.Q(DmP_mant_SHT1_SW[9]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_10_ ( .D(n1377), .CK(n4056), .RN(n3970),
.Q(DmP_mant_SHT1_SW[10]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_11_ ( .D(n1375), .CK(n4056), .RN(n3970),
.Q(DmP_mant_SHT1_SW[11]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_12_ ( .D(n1373), .CK(n4057), .RN(n3970),
.Q(DmP_mant_SHT1_SW[12]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_13_ ( .D(n1371), .CK(n4055), .RN(n3971),
.Q(DmP_mant_SHT1_SW[13]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_14_ ( .D(n1369), .CK(n4052), .RN(n3971),
.Q(DmP_mant_SHT1_SW[14]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_15_ ( .D(n1367), .CK(n4054), .RN(n3971),
.Q(DmP_mant_SHT1_SW[15]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_16_ ( .D(n1365), .CK(n4079), .RN(n3971),
.Q(DmP_mant_SHT1_SW[16]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_17_ ( .D(n1363), .CK(n2028), .RN(n3971),
.Q(DmP_mant_SHT1_SW[17]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_18_ ( .D(n1361), .CK(n4059), .RN(n3972),
.Q(DmP_mant_SHT1_SW[18]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_19_ ( .D(n1359), .CK(n4005), .RN(n3972),
.Q(DmP_mant_SHT1_SW[19]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_20_ ( .D(n1357), .CK(n4058), .RN(n3972),
.Q(DmP_mant_SHT1_SW[20]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_21_ ( .D(n1355), .CK(n4059), .RN(n3972),
.Q(DmP_mant_SHT1_SW[21]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_22_ ( .D(n1353), .CK(n4065), .RN(n3972),
.Q(DmP_mant_SHT1_SW[22]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_23_ ( .D(n1351), .CK(n4062), .RN(n3973),
.Q(DmP_mant_SHT1_SW[23]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_26_ ( .D(n1345), .CK(n4060), .RN(n3973),
.Q(DmP_mant_SHT1_SW[26]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_27_ ( .D(n1343), .CK(n2028), .RN(n3973),
.Q(DmP_mant_SHT1_SW[27]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_28_ ( .D(n1341), .CK(n4059), .RN(n3974),
.Q(DmP_mant_SHT1_SW[28]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_29_ ( .D(n1339), .CK(n4058), .RN(n3974),
.Q(DmP_mant_SHT1_SW[29]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_30_ ( .D(n1337), .CK(n4062), .RN(n3974),
.Q(DmP_mant_SHT1_SW[30]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_31_ ( .D(n1335), .CK(n4005), .RN(n3974),
.Q(DmP_mant_SHT1_SW[31]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_32_ ( .D(n1333), .CK(n4063), .RN(n3974),
.Q(DmP_mant_SHT1_SW[32]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_33_ ( .D(n1331), .CK(n4066), .RN(n3975),
.Q(DmP_mant_SHT1_SW[33]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_34_ ( .D(n1329), .CK(n4064), .RN(n3975),
.Q(DmP_mant_SHT1_SW[34]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_35_ ( .D(n1327), .CK(n4061), .RN(n3975),
.Q(DmP_mant_SHT1_SW[35]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_36_ ( .D(n1325), .CK(n2272), .RN(n3975),
.Q(DmP_mant_SHT1_SW[36]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_37_ ( .D(n1323), .CK(n2028), .RN(n3975),
.Q(DmP_mant_SHT1_SW[37]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_38_ ( .D(n1321), .CK(n4062), .RN(n3976),
.Q(DmP_mant_SHT1_SW[38]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_39_ ( .D(n1319), .CK(n4059), .RN(n3976),
.Q(DmP_mant_SHT1_SW[39]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_40_ ( .D(n1317), .CK(n4058), .RN(n3976),
.Q(DmP_mant_SHT1_SW[40]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_41_ ( .D(n1315), .CK(n4060), .RN(n3976),
.Q(DmP_mant_SHT1_SW[41]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_42_ ( .D(n1313), .CK(n4063), .RN(n3976),
.Q(DmP_mant_SHT1_SW[42]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_43_ ( .D(n1311), .CK(n4066), .RN(n3977),
.Q(DmP_mant_SHT1_SW[43]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_44_ ( .D(n1309), .CK(n4064), .RN(n3977),
.Q(DmP_mant_SHT1_SW[44]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_45_ ( .D(n1307), .CK(n4061), .RN(n3977),
.Q(DmP_mant_SHT1_SW[45]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_46_ ( .D(n1305), .CK(n2272), .RN(n3977),
.Q(DmP_mant_SHT1_SW[46]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_47_ ( .D(n1303), .CK(n4063), .RN(n3977),
.Q(DmP_mant_SHT1_SW[47]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_48_ ( .D(n1301), .CK(n4066), .RN(n3978),
.Q(DmP_mant_SHT1_SW[48]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_49_ ( .D(n1299), .CK(n4064), .RN(n3978),
.Q(DmP_mant_SHT1_SW[49]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_50_ ( .D(n1297), .CK(n4061), .RN(n3978),
.Q(DmP_mant_SHT1_SW[50]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_0_ ( .D(n1675), .CK(n2025), .RN(n3941), .Q(
DMP_EXP_EWSW[0]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_1_ ( .D(n1674), .CK(n4023), .RN(n3941), .Q(
DMP_EXP_EWSW[1]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_2_ ( .D(n1673), .CK(n4027), .RN(n3941), .Q(
DMP_EXP_EWSW[2]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_3_ ( .D(n1672), .CK(n4028), .RN(n3942), .Q(
DMP_EXP_EWSW[3]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_4_ ( .D(n1671), .CK(n4025), .RN(n3942), .Q(
DMP_EXP_EWSW[4]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_5_ ( .D(n1670), .CK(n2273), .RN(n3942), .Q(
DMP_EXP_EWSW[5]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_6_ ( .D(n1669), .CK(n4030), .RN(n3942), .Q(
DMP_EXP_EWSW[6]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_7_ ( .D(n1668), .CK(n4027), .RN(n3942), .Q(
DMP_EXP_EWSW[7]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_8_ ( .D(n1667), .CK(n4028), .RN(n3942), .Q(
DMP_EXP_EWSW[8]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_9_ ( .D(n1666), .CK(n4025), .RN(n3942), .Q(
DMP_EXP_EWSW[9]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_10_ ( .D(n1665), .CK(n4030), .RN(n3942), .Q(
DMP_EXP_EWSW[10]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_11_ ( .D(n1664), .CK(n4027), .RN(n3942), .Q(
DMP_EXP_EWSW[11]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_12_ ( .D(n1663), .CK(n4028), .RN(n3942), .Q(
DMP_EXP_EWSW[12]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_13_ ( .D(n1662), .CK(n4025), .RN(n3943), .Q(
DMP_EXP_EWSW[13]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_14_ ( .D(n1661), .CK(n4030), .RN(n3943), .Q(
DMP_EXP_EWSW[14]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_15_ ( .D(n1660), .CK(n4027), .RN(n3943), .Q(
DMP_EXP_EWSW[15]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_16_ ( .D(n1659), .CK(n4028), .RN(n3943), .Q(
DMP_EXP_EWSW[16]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_17_ ( .D(n1658), .CK(n4025), .RN(n3943), .Q(
DMP_EXP_EWSW[17]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_18_ ( .D(n1657), .CK(n2273), .RN(n3943), .Q(
DMP_EXP_EWSW[18]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_19_ ( .D(n1656), .CK(n2273), .RN(n3943), .Q(
DMP_EXP_EWSW[19]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_20_ ( .D(n1655), .CK(n2273), .RN(n3943), .Q(
DMP_EXP_EWSW[20]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_21_ ( .D(n1654), .CK(n4030), .RN(n3943), .Q(
DMP_EXP_EWSW[21]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_22_ ( .D(n1653), .CK(n4023), .RN(n3943), .Q(
DMP_EXP_EWSW[22]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_23_ ( .D(n1652), .CK(n4029), .RN(n3944), .Q(
DMP_EXP_EWSW[23]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_24_ ( .D(n1651), .CK(n4023), .RN(n3944), .Q(
DMP_EXP_EWSW[24]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_25_ ( .D(n1650), .CK(n4024), .RN(n3944), .Q(
DMP_EXP_EWSW[25]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_26_ ( .D(n1649), .CK(n4026), .RN(n3944), .Q(
DMP_EXP_EWSW[26]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_27_ ( .D(n1648), .CK(n4010), .RN(n3944), .Q(
DMP_EXP_EWSW[27]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_28_ ( .D(n1647), .CK(n4029), .RN(n3944), .Q(
DMP_EXP_EWSW[28]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_29_ ( .D(n1646), .CK(n4024), .RN(n3944), .Q(
DMP_EXP_EWSW[29]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_30_ ( .D(n1645), .CK(n4023), .RN(n3944), .Q(
DMP_EXP_EWSW[30]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_31_ ( .D(n1644), .CK(n4026), .RN(n3944), .Q(
DMP_EXP_EWSW[31]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_32_ ( .D(n1643), .CK(n4030), .RN(n3944), .Q(
DMP_EXP_EWSW[32]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_33_ ( .D(n1642), .CK(n4027), .RN(n3945), .Q(
DMP_EXP_EWSW[33]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_34_ ( .D(n1641), .CK(n4028), .RN(n3945), .Q(
DMP_EXP_EWSW[34]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_35_ ( .D(n1640), .CK(n4025), .RN(n3945), .Q(
DMP_EXP_EWSW[35]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_36_ ( .D(n1639), .CK(n2273), .RN(n3945), .Q(
DMP_EXP_EWSW[36]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_37_ ( .D(n1638), .CK(n4030), .RN(n3945), .Q(
DMP_EXP_EWSW[37]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_38_ ( .D(n1637), .CK(n4027), .RN(n3945), .Q(
DMP_EXP_EWSW[38]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_39_ ( .D(n1636), .CK(n4080), .RN(n3945), .Q(
DMP_EXP_EWSW[39]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_40_ ( .D(n1635), .CK(n4080), .RN(n3945), .Q(
DMP_EXP_EWSW[40]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_41_ ( .D(n1634), .CK(n4080), .RN(n3945), .Q(
DMP_EXP_EWSW[41]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_42_ ( .D(n1633), .CK(n4038), .RN(n3945), .Q(
DMP_EXP_EWSW[42]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_43_ ( .D(n1632), .CK(n4032), .RN(n3933), .Q(
DMP_EXP_EWSW[43]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_44_ ( .D(n1631), .CK(n4032), .RN(n3931), .Q(
DMP_EXP_EWSW[44]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_45_ ( .D(n1630), .CK(n4032), .RN(n3929), .Q(
DMP_EXP_EWSW[45]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_46_ ( .D(n1629), .CK(n4032), .RN(n3955), .Q(
DMP_EXP_EWSW[46]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_47_ ( .D(n1628), .CK(n4032), .RN(n3946), .Q(
DMP_EXP_EWSW[47]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_48_ ( .D(n1627), .CK(n4032), .RN(n3930), .Q(
DMP_EXP_EWSW[48]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_49_ ( .D(n1626), .CK(n4032), .RN(n3936), .Q(
DMP_EXP_EWSW[49]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_50_ ( .D(n1625), .CK(n4032), .RN(n3933), .Q(
DMP_EXP_EWSW[50]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_51_ ( .D(n1624), .CK(n4032), .RN(n3931), .Q(
DMP_EXP_EWSW[51]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_58_ ( .D(n1617), .CK(n2023), .RN(n3947), .Q(
DMP_EXP_EWSW[58]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_59_ ( .D(n1616), .CK(n4031), .RN(n3947), .Q(
DMP_EXP_EWSW[59]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_60_ ( .D(n1615), .CK(n4033), .RN(n3947), .Q(
DMP_EXP_EWSW[60]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_61_ ( .D(n1614), .CK(n4038), .RN(n3947), .Q(
DMP_EXP_EWSW[61]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_62_ ( .D(n1613), .CK(n2023), .RN(n3947), .Q(
DMP_EXP_EWSW[62]) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_2_ ( .D(n1610), .CK(n4031), .RN(n3948), .Q(
SIGN_FLAG_EXP) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_0_ ( .D(n1398), .CK(n4052), .RN(n3968), .Q(
DmP_EXP_EWSW[0]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_1_ ( .D(n1396), .CK(n4054), .RN(n3968), .Q(
DmP_EXP_EWSW[1]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_2_ ( .D(n1394), .CK(n4079), .RN(n3968), .Q(
DmP_EXP_EWSW[2]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_3_ ( .D(n1392), .CK(n4054), .RN(n3968), .Q(
DmP_EXP_EWSW[3]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_4_ ( .D(n1390), .CK(n4079), .RN(n3969), .Q(
DmP_EXP_EWSW[4]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_5_ ( .D(n1388), .CK(n4057), .RN(n3969), .Q(
DmP_EXP_EWSW[5]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_6_ ( .D(n1386), .CK(n4055), .RN(n3969), .Q(
DmP_EXP_EWSW[6]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_7_ ( .D(n1384), .CK(n4052), .RN(n3969), .Q(
DmP_EXP_EWSW[7]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_8_ ( .D(n1382), .CK(n4056), .RN(n3969), .Q(
DmP_EXP_EWSW[8]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_9_ ( .D(n1380), .CK(n4056), .RN(n3970), .Q(
DmP_EXP_EWSW[9]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_10_ ( .D(n1378), .CK(n4056), .RN(n3970), .Q(
DmP_EXP_EWSW[10]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_11_ ( .D(n1376), .CK(n4056), .RN(n3970), .Q(
DmP_EXP_EWSW[11]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_12_ ( .D(n1374), .CK(n4056), .RN(n3970), .Q(
DmP_EXP_EWSW[12]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_13_ ( .D(n1372), .CK(n4055), .RN(n3970), .Q(
DmP_EXP_EWSW[13]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_14_ ( .D(n1370), .CK(n4052), .RN(n3971), .Q(
DmP_EXP_EWSW[14]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_15_ ( .D(n1368), .CK(n4057), .RN(n3971), .Q(
DmP_EXP_EWSW[15]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_16_ ( .D(n1366), .CK(n4079), .RN(n3971), .Q(
DmP_EXP_EWSW[16]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_17_ ( .D(n1364), .CK(n2268), .RN(n3971), .Q(
DmP_EXP_EWSW[17]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_18_ ( .D(n1362), .CK(n2028), .RN(n3971), .Q(
DmP_EXP_EWSW[18]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_19_ ( .D(n1360), .CK(n4058), .RN(n3972), .Q(
DmP_EXP_EWSW[19]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_20_ ( .D(n1358), .CK(n4065), .RN(n3972), .Q(
DmP_EXP_EWSW[20]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_21_ ( .D(n1356), .CK(n4065), .RN(n3972), .Q(
DmP_EXP_EWSW[21]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_22_ ( .D(n1354), .CK(n4060), .RN(n3972), .Q(
DmP_EXP_EWSW[22]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_23_ ( .D(n1352), .CK(n2028), .RN(n3972), .Q(
DmP_EXP_EWSW[23]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_24_ ( .D(n1350), .CK(n4058), .RN(n3973), .Q(
DmP_EXP_EWSW[24]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_25_ ( .D(n1348), .CK(n4005), .RN(n3973), .Q(
DmP_EXP_EWSW[25]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_26_ ( .D(n1346), .CK(n4059), .RN(n3973), .Q(
DmP_EXP_EWSW[26]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_27_ ( .D(n1344), .CK(n4005), .RN(n3973), .Q(
DmP_EXP_EWSW[27]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_28_ ( .D(n1342), .CK(n4005), .RN(n3973), .Q(
DmP_EXP_EWSW[28]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_29_ ( .D(n1340), .CK(n4059), .RN(n3974), .Q(
DmP_EXP_EWSW[29]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_30_ ( .D(n1338), .CK(n4058), .RN(n3974), .Q(
DmP_EXP_EWSW[30]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_31_ ( .D(n1336), .CK(n4062), .RN(n3974), .Q(
DmP_EXP_EWSW[31]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_32_ ( .D(n1334), .CK(n4005), .RN(n3974), .Q(
DmP_EXP_EWSW[32]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_33_ ( .D(n1332), .CK(n4063), .RN(n3974), .Q(
DmP_EXP_EWSW[33]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_34_ ( .D(n1330), .CK(n4066), .RN(n3975), .Q(
DmP_EXP_EWSW[34]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_35_ ( .D(n1328), .CK(n4061), .RN(n3975), .Q(
DmP_EXP_EWSW[35]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_36_ ( .D(n1326), .CK(n4064), .RN(n3975), .Q(
DmP_EXP_EWSW[36]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_37_ ( .D(n1324), .CK(n2272), .RN(n3975), .Q(
DmP_EXP_EWSW[37]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_38_ ( .D(n1322), .CK(n2028), .RN(n3975), .Q(
DmP_EXP_EWSW[38]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_39_ ( .D(n1320), .CK(n4005), .RN(n3976), .Q(
DmP_EXP_EWSW[39]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_40_ ( .D(n1318), .CK(n4058), .RN(n3976), .Q(
DmP_EXP_EWSW[40]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_41_ ( .D(n1316), .CK(n4059), .RN(n3976), .Q(
DmP_EXP_EWSW[41]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_42_ ( .D(n1314), .CK(n4058), .RN(n3976), .Q(
DmP_EXP_EWSW[42]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_43_ ( .D(n1312), .CK(n4063), .RN(n3976), .Q(
DmP_EXP_EWSW[43]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_44_ ( .D(n1310), .CK(n4066), .RN(n3977), .Q(
DmP_EXP_EWSW[44]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_45_ ( .D(n1308), .CK(n4064), .RN(n3977), .Q(
DmP_EXP_EWSW[45]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_46_ ( .D(n1306), .CK(n4078), .RN(n3977), .Q(
DmP_EXP_EWSW[46]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_47_ ( .D(n1304), .CK(n4078), .RN(n3977), .Q(
DmP_EXP_EWSW[47]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_48_ ( .D(n1302), .CK(n4063), .RN(n3977), .Q(
DmP_EXP_EWSW[48]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_49_ ( .D(n1300), .CK(n4066), .RN(n3978), .Q(
DmP_EXP_EWSW[49]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_50_ ( .D(n1298), .CK(n4064), .RN(n3978), .Q(
DmP_EXP_EWSW[50]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_51_ ( .D(n1296), .CK(n4061), .RN(n3978), .Q(
DmP_EXP_EWSW[51]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_0_ ( .D(n1698), .CK(n4024), .RN(n3940), .Q(
Data_array_SWR[0]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_3_ ( .D(n1701), .CK(n2025), .RN(n3940), .Q(
Data_array_SWR[3]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_2_ ( .D(n1700), .CK(n4026), .RN(n3940), .Q(
Data_array_SWR[2]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_1_ ( .D(n1699), .CK(n4022), .RN(n3940), .Q(
Data_array_SWR[1]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_0_ ( .D(n1449), .CK(n4049), .RN(n4001),
.Q(DMP_exp_NRM2_EW[0]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_1_ ( .D(n1444), .CK(n4050), .RN(n3998),
.Q(DMP_exp_NRM2_EW[1]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_2_ ( .D(n1439), .CK(n4011), .RN(n3999),
.Q(DMP_exp_NRM2_EW[2]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_3_ ( .D(n1434), .CK(n4051), .RN(n4003),
.Q(DMP_exp_NRM2_EW[3]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_4_ ( .D(n1429), .CK(n4053), .RN(n3998),
.Q(DMP_exp_NRM2_EW[4]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_5_ ( .D(n1424), .CK(n2026), .RN(n3999),
.Q(DMP_exp_NRM2_EW[5]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_6_ ( .D(n1419), .CK(n4057), .RN(n4002),
.Q(DMP_exp_NRM2_EW[6]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_7_ ( .D(n1414), .CK(n4055), .RN(n3998),
.Q(DMP_exp_NRM2_EW[7]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_8_ ( .D(n1409), .CK(n4049), .RN(n3999),
.Q(DMP_exp_NRM2_EW[8]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_9_ ( .D(n1404), .CK(n4050), .RN(n3998),
.Q(DMP_exp_NRM2_EW[9]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_10_ ( .D(n1399), .CK(n4052), .RN(n3998),
.Q(DMP_exp_NRM2_EW[10]) );
DFFRX1TS inst_ShiftRegister_Q_reg_3_ ( .D(n1887), .CK(n4059), .RN(n3922),
.Q(Shift_reg_FLAGS_7[3]) );
DFFRX1TS NRM_STAGE_FLAGS_Q_reg_2_ ( .D(n1277), .CK(n4064), .RN(n3980), .Q(
ADD_OVRFLW_NRM) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_57_ ( .D(n1289), .CK(n4065), .RN(n3979), .Q(
DmP_EXP_EWSW[57]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_52_ ( .D(n1294), .CK(n4061), .RN(n3978), .Q(
DmP_EXP_EWSW[52]) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_7_ ( .D(n1811), .CK(n4008), .RN(n3931),
.Q(intDY_EWSW[7]), .QN(n3758) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_7_ ( .D(n1705), .CK(n4022), .RN(n3940), .Q(
Data_array_SWR[7]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_6_ ( .D(n1704), .CK(n4010), .RN(n3940), .Q(
Data_array_SWR[6]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_5_ ( .D(n1703), .CK(n4026), .RN(n3940), .Q(
Data_array_SWR[5]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_4_ ( .D(n1702), .CK(n2025), .RN(n3940), .Q(
Data_array_SWR[4]) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_61_ ( .D(n1822), .CK(n4012), .RN(n2047),
.Q(intDX_EWSW[61]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_57_ ( .D(n1618), .CK(n4038), .RN(n3947), .Q(
DMP_EXP_EWSW[57]) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_58_ ( .D(n1760), .CK(n2271), .RN(n3934),
.Q(intDY_EWSW[58]) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_62_ ( .D(n1756), .CK(n4016), .RN(n3934),
.Q(intDY_EWSW[62]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_11_ ( .D(n1709), .CK(n4026), .RN(n3939), .Q(
Data_array_SWR[11]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_10_ ( .D(n1708), .CK(n4010), .RN(n3939), .Q(
Data_array_SWR[10]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_9_ ( .D(n1707), .CK(n4022), .RN(n3940), .Q(
Data_array_SWR[9]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_8_ ( .D(n1706), .CK(n4024), .RN(n3940), .Q(
Data_array_SWR[8]) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_60_ ( .D(n1758), .CK(n2271), .RN(n3934),
.Q(intDY_EWSW[60]) );
DFFRX2TS EXP_STAGE_DMP_Q_reg_54_ ( .D(n1621), .CK(n4033), .RN(n3947), .Q(
DMP_EXP_EWSW[54]) );
DFFRX2TS EXP_STAGE_DMP_Q_reg_56_ ( .D(n1619), .CK(n4038), .RN(n3947), .Q(
DMP_EXP_EWSW[56]) );
DFFRX2TS SHT2_STAGE_SHFTVARS1_Q_reg_2_ ( .D(n1697), .CK(n4021), .RN(n3935),
.Q(shift_value_SHT2_EWR[2]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_33_ ( .D(n1850), .CK(n4073), .RN(n3926),
.Q(intDX_EWSW[33]) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_1_ ( .D(n1817), .CK(n4040), .RN(n4002),
.Q(intDY_EWSW[1]) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_15_ ( .D(n1803), .CK(n4020), .RN(n3946),
.Q(intDY_EWSW[15]) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_17_ ( .D(n1801), .CK(n4020), .RN(n2043),
.Q(intDY_EWSW[17]) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_49_ ( .D(n1769), .CK(n4017), .RN(n3930),
.Q(intDY_EWSW[49]) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_52_ ( .D(n1766), .CK(n4015), .RN(n3936),
.Q(intDY_EWSW[52]) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_56_ ( .D(n1762), .CK(n4016), .RN(n3934),
.Q(intDY_EWSW[56]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_26_ ( .D(n1857), .CK(n4015), .RN(n3925),
.Q(intDX_EWSW[26]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_46_ ( .D(n1837), .CK(n4026), .RN(n3927),
.Q(intDX_EWSW[46]) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_0_ ( .D(n1818), .CK(n4047), .RN(n2047),
.Q(intDY_EWSW[0]) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_5_ ( .D(n1813), .CK(n4014), .RN(n3936),
.Q(intDY_EWSW[5]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_24_ ( .D(n1859), .CK(n4014), .RN(n3925),
.Q(intDX_EWSW[24]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_54_ ( .D(n1829), .CK(n4051), .RN(n3928),
.Q(intDX_EWSW[54]) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_6_ ( .D(n1812), .CK(n4013), .RN(n3933),
.Q(intDY_EWSW[6]) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_18_ ( .D(n1800), .CK(n4020), .RN(n3929),
.Q(intDY_EWSW[18]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_41_ ( .D(n1842), .CK(n2025), .RN(n3927),
.Q(intDX_EWSW[41]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_27_ ( .D(n1725), .CK(n4018), .RN(n3935), .Q(
Data_array_SWR[27]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_38_ ( .D(n1736), .CK(n4021), .RN(n3937), .Q(
Data_array_SWR[38]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_37_ ( .D(n1735), .CK(n4018), .RN(n3937), .Q(
Data_array_SWR[37]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_36_ ( .D(n1734), .CK(n2271), .RN(n3937), .Q(
Data_array_SWR[36]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_54_ ( .D(n1752), .CK(n4077), .RN(n3935), .Q(
Data_array_SWR[54]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_53_ ( .D(n1751), .CK(n4016), .RN(n3935), .Q(
Data_array_SWR[53]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_52_ ( .D(n1750), .CK(n4021), .RN(n3935), .Q(
Data_array_SWR[52]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_15_ ( .D(n1713), .CK(n4029), .RN(n3939), .Q(
Data_array_SWR[15]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_25_ ( .D(n1723), .CK(n2025), .RN(n3938), .Q(
Data_array_SWR[25]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_24_ ( .D(n1722), .CK(n4010), .RN(n3938), .Q(
Data_array_SWR[24]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_26_ ( .D(n1724), .CK(n4018), .RN(n3935), .Q(
Data_array_SWR[26]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_35_ ( .D(n1733), .CK(n2271), .RN(n3937), .Q(
Data_array_SWR[35]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_22_ ( .D(n1720), .CK(n4026), .RN(n3938), .Q(
Data_array_SWR[22]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_21_ ( .D(n1719), .CK(n4010), .RN(n3938), .Q(
Data_array_SWR[21]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_20_ ( .D(n1718), .CK(n4029), .RN(n3938), .Q(
Data_array_SWR[20]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_43_ ( .D(n1741), .CK(n4020), .RN(n3933), .Q(
Data_array_SWR[43]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_42_ ( .D(n1740), .CK(n4020), .RN(n3931), .Q(
Data_array_SWR[42]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_41_ ( .D(n1739), .CK(n2271), .RN(n3937), .Q(
Data_array_SWR[41]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_40_ ( .D(n1738), .CK(n4077), .RN(n3937), .Q(
Data_array_SWR[40]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_39_ ( .D(n1737), .CK(n2271), .RN(n3937), .Q(
Data_array_SWR[39]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_34_ ( .D(n1732), .CK(n4016), .RN(n3937), .Q(
Data_array_SWR[34]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_33_ ( .D(n1731), .CK(n4021), .RN(n3937), .Q(
Data_array_SWR[33]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_32_ ( .D(n1730), .CK(n4018), .RN(n3937), .Q(
Data_array_SWR[32]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_31_ ( .D(n1729), .CK(n2025), .RN(n3938), .Q(
Data_array_SWR[31]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_23_ ( .D(n1721), .CK(n4022), .RN(n3938), .Q(
Data_array_SWR[23]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_46_ ( .D(n1744), .CK(n4020), .RN(n2043), .Q(
Data_array_SWR[46]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_45_ ( .D(n1743), .CK(n4020), .RN(n3929), .Q(
Data_array_SWR[45]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_44_ ( .D(n1742), .CK(n4020), .RN(n3955), .Q(
Data_array_SWR[44]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_47_ ( .D(n1745), .CK(n4020), .RN(n4000), .Q(
Data_array_SWR[47]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_19_ ( .D(n1717), .CK(n4022), .RN(n3939), .Q(
Data_array_SWR[19]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_18_ ( .D(n1716), .CK(n2025), .RN(n3939), .Q(
Data_array_SWR[18]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_17_ ( .D(n1715), .CK(n4026), .RN(n3939), .Q(
Data_array_SWR[17]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_16_ ( .D(n1714), .CK(n4024), .RN(n3939), .Q(
Data_array_SWR[16]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_14_ ( .D(n1712), .CK(n4024), .RN(n3939), .Q(
Data_array_SWR[14]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_13_ ( .D(n1711), .CK(n4022), .RN(n3939), .Q(
Data_array_SWR[13]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_12_ ( .D(n1710), .CK(n4010), .RN(n3939), .Q(
Data_array_SWR[12]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_1_ ( .D(n1604), .CK(n4035), .RN(n3948), .Q(
DMP_SFG[1]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_3_ ( .D(n1598), .CK(n4036), .RN(n3949), .Q(
DMP_SFG[3]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_5_ ( .D(n1592), .CK(n4033), .RN(n3950), .Q(
DMP_SFG[5]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_7_ ( .D(n1586), .CK(n4038), .RN(n3950), .Q(
DMP_SFG[7]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_9_ ( .D(n1580), .CK(n4081), .RN(n3951), .Q(
DMP_SFG[9]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_11_ ( .D(n1574), .CK(n4036), .RN(n3951), .Q(
DMP_SFG[11]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_13_ ( .D(n1568), .CK(n4081), .RN(n3952), .Q(
DMP_SFG[13]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_15_ ( .D(n1562), .CK(n2023), .RN(n3953), .Q(
DMP_SFG[15]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_17_ ( .D(n1556), .CK(n4031), .RN(n3953), .Q(
DMP_SFG[17]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_19_ ( .D(n1550), .CK(n4037), .RN(n3954), .Q(
DMP_SFG[19]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_21_ ( .D(n1544), .CK(n4039), .RN(n3954), .Q(
DMP_SFG[21]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_23_ ( .D(n1538), .CK(n4047), .RN(n4000), .Q(
DMP_SFG[23]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_25_ ( .D(n1532), .CK(n4042), .RN(n3956), .Q(
DMP_SFG[25]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_27_ ( .D(n1526), .CK(n4041), .RN(n3956), .Q(
DMP_SFG[27]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_29_ ( .D(n1520), .CK(n2022), .RN(n3957), .Q(
DMP_SFG[29]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_31_ ( .D(n1514), .CK(n4012), .RN(n3957), .Q(
DMP_SFG[31]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_33_ ( .D(n1508), .CK(n4045), .RN(n3958), .Q(
DMP_SFG[33]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_35_ ( .D(n1502), .CK(n4012), .RN(n3959), .Q(
DMP_SFG[35]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_37_ ( .D(n1496), .CK(n2022), .RN(n3959), .Q(
DMP_SFG[37]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_39_ ( .D(n1490), .CK(n2266), .RN(n3960), .Q(
DMP_SFG[39]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_41_ ( .D(n1484), .CK(n4046), .RN(n3960), .Q(
DMP_SFG[41]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_43_ ( .D(n1478), .CK(n4048), .RN(n3961), .Q(
DMP_SFG[43]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_45_ ( .D(n1472), .CK(n4042), .RN(n3962), .Q(
DMP_SFG[45]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_47_ ( .D(n1466), .CK(n4041), .RN(n3962), .Q(
DMP_SFG[47]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_49_ ( .D(n1460), .CK(n4043), .RN(n3963), .Q(
DMP_SFG[49]) );
DFFRX2TS inst_FSM_INPUT_ENABLE_state_reg_reg_2_ ( .D(n1892), .CK(n4059),
.RN(n3922), .Q(inst_FSM_INPUT_ENABLE_state_reg[2]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_11_ ( .D(n1872), .CK(n2024), .RN(n3924),
.Q(intDX_EWSW[11]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_25_ ( .D(n1858), .CK(n4013), .RN(n3925),
.Q(intDX_EWSW[25]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_59_ ( .D(n1824), .CK(n4053), .RN(n3928),
.Q(intDX_EWSW[59]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_2_ ( .D(n1267), .CK(n4068), .RN(n3981),
.Q(Raw_mant_NRM_SWR[2]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_32_ ( .D(n1851), .CK(n4075), .RN(n3926),
.Q(intDX_EWSW[32]) );
DFFRX2TS SGF_STAGE_DmP_mant_Q_reg_53_ ( .D(n1103), .CK(n4083), .RN(n3997),
.Q(DmP_mant_SFG_SWR[53]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_40_ ( .D(n1843), .CK(n4024), .RN(n3927),
.Q(intDX_EWSW[40]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_8_ ( .D(n1261), .CK(n4007), .RN(n3981),
.Q(Raw_mant_NRM_SWR[8]) );
DFFRX2TS SFT2FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(n1276), .CK(n4066), .RN(n3999),
.Q(ADD_OVRFLW_NRM2), .QN(n1895) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_43_ ( .D(n1840), .CK(n4029), .RN(n3927),
.Q(intDX_EWSW[43]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_35_ ( .D(n1848), .CK(n4070), .RN(n3926),
.Q(intDX_EWSW[35]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_51_ ( .D(n1832), .CK(n2026), .RN(n3928),
.Q(intDX_EWSW[51]) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_23_ ( .D(n1795), .CK(n4020), .RN(n3955),
.Q(intDY_EWSW[23]) );
DFFRX2TS inst_ShiftRegister_Q_reg_2_ ( .D(n1886), .CK(n4062), .RN(n3922),
.Q(Shift_reg_FLAGS_7[2]), .QN(n3913) );
DFFRX2TS inst_ShiftRegister_Q_reg_0_ ( .D(n1884), .CK(n4065), .RN(n3922),
.Q(Shift_reg_FLAGS_7[0]), .QN(n3745) );
CMPR32X2TS DP_OP_15J180_122_2221_U12 ( .A(DMP_exp_NRM2_EW[0]), .B(n2029),
.C(DP_OP_15J180_122_2221_n22), .CO(DP_OP_15J180_122_2221_n11), .S(
exp_rslt_NRM2_EW1[0]) );
CMPR32X2TS DP_OP_15J180_122_2221_U11 ( .A(DP_OP_15J180_122_2221_n21), .B(
DMP_exp_NRM2_EW[1]), .C(DP_OP_15J180_122_2221_n11), .CO(
DP_OP_15J180_122_2221_n10), .S(exp_rslt_NRM2_EW1[1]) );
CMPR32X2TS DP_OP_15J180_122_2221_U10 ( .A(DP_OP_15J180_122_2221_n20), .B(
DMP_exp_NRM2_EW[2]), .C(DP_OP_15J180_122_2221_n10), .CO(
DP_OP_15J180_122_2221_n9), .S(exp_rslt_NRM2_EW1[2]) );
CMPR32X2TS DP_OP_15J180_122_2221_U9 ( .A(DP_OP_15J180_122_2221_n19), .B(
DMP_exp_NRM2_EW[3]), .C(DP_OP_15J180_122_2221_n9), .CO(
DP_OP_15J180_122_2221_n8), .S(exp_rslt_NRM2_EW1[3]) );
CMPR32X2TS DP_OP_15J180_122_2221_U8 ( .A(DP_OP_15J180_122_2221_n18), .B(
DMP_exp_NRM2_EW[4]), .C(DP_OP_15J180_122_2221_n8), .CO(
DP_OP_15J180_122_2221_n7), .S(exp_rslt_NRM2_EW1[4]) );
CMPR32X2TS DP_OP_15J180_122_2221_U7 ( .A(DP_OP_15J180_122_2221_n17), .B(
DMP_exp_NRM2_EW[5]), .C(DP_OP_15J180_122_2221_n7), .CO(
DP_OP_15J180_122_2221_n6), .S(exp_rslt_NRM2_EW1[5]) );
CMPR32X2TS DP_OP_15J180_122_2221_U6 ( .A(n2029), .B(DMP_exp_NRM2_EW[6]), .C(
DP_OP_15J180_122_2221_n6), .CO(DP_OP_15J180_122_2221_n5), .S(
exp_rslt_NRM2_EW1[6]) );
CMPR32X2TS DP_OP_15J180_122_2221_U5 ( .A(n2029), .B(DMP_exp_NRM2_EW[7]), .C(
DP_OP_15J180_122_2221_n5), .CO(DP_OP_15J180_122_2221_n4), .S(
exp_rslt_NRM2_EW1[7]) );
CMPR32X2TS DP_OP_15J180_122_2221_U4 ( .A(n2029), .B(DMP_exp_NRM2_EW[8]), .C(
DP_OP_15J180_122_2221_n4), .CO(DP_OP_15J180_122_2221_n3), .S(
exp_rslt_NRM2_EW1[8]) );
CMPR32X2TS DP_OP_15J180_122_2221_U3 ( .A(n2029), .B(DMP_exp_NRM2_EW[9]), .C(
DP_OP_15J180_122_2221_n3), .CO(DP_OP_15J180_122_2221_n2), .S(
exp_rslt_NRM2_EW1[9]) );
CMPR32X2TS DP_OP_15J180_122_2221_U2 ( .A(n2029), .B(DMP_exp_NRM2_EW[10]),
.C(DP_OP_15J180_122_2221_n2), .CO(DP_OP_15J180_122_2221_n1), .S(
exp_rslt_NRM2_EW1[10]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_14_ ( .D(n1213), .CK(n2274), .RN(n4086),
.Q(LZD_output_NRM2_EW[3]) );
DFFRX4TS SHT2_STAGE_SHFTVARS2_Q_reg_1_ ( .D(n1753), .CK(n4019), .RN(n3935),
.Q(left_right_SHT2), .QN(n3746) );
DFFRX2TS SHT2_STAGE_SHFTVARS1_Q_reg_3_ ( .D(n1696), .CK(n4021), .RN(n3935),
.Q(shift_value_SHT2_EWR[3]), .QN(n3910) );
DFFRX1TS inst_FSM_INPUT_ENABLE_state_reg_reg_0_ ( .D(n1891), .CK(n4058),
.RN(n3922), .Q(inst_FSM_INPUT_ENABLE_state_reg[0]), .QN(n3841) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_63_ ( .D(n1755), .CK(n4018), .RN(n3934),
.Q(intDY_EWSW[63]) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_61_ ( .D(n1757), .CK(n4021), .RN(n3934),
.Q(intDY_EWSW[61]), .QN(n3898) );
DFFRX2TS SHT2_STAGE_SHFTVARS1_Q_reg_5_ ( .D(n1693), .CK(n4030), .RN(n3941),
.Q(shift_value_SHT2_EWR[5]), .QN(n3911) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_26_ ( .D(n1792), .CK(n4017), .RN(n4000),
.Q(intDY_EWSW[26]), .QN(n3715) );
DFFRX1TS INPUT_STAGE_FLAGS_Q_reg_0_ ( .D(n1819), .CK(n4047), .RN(n4003), .Q(
intAS) );
DFFRX2TS SHT2_STAGE_SHFTVARS1_Q_reg_4_ ( .D(n1695), .CK(n4077), .RN(n3935),
.Q(shift_value_SHT2_EWR[4]) );
DFFRX2TS inst_ShiftRegister_Q_reg_1_ ( .D(n1885), .CK(n4060), .RN(n3922),
.Q(Shift_reg_FLAGS_7[1]), .QN(n3749) );
OR2X4TS U1897 ( .A(n2040), .B(n3295), .Y(n2406) );
AOI222X4TS U1898 ( .A0(DmP_mant_SFG_SWR[49]), .A1(DMP_SFG[47]), .B0(
DmP_mant_SFG_SWR[49]), .B1(n3619), .C0(DMP_SFG[47]), .C1(n3619), .Y(
n3626) );
OR2X4TS U1899 ( .A(shift_value_SHT2_EWR[2]), .B(shift_value_SHT2_EWR[3]),
.Y(n2946) );
AOI222X4TS U1900 ( .A0(n3877), .A1(intDX_EWSW[34]), .B0(n3663), .B1(
intDX_EWSW[35]), .C0(n3678), .C1(intDX_EWSW[33]), .Y(n2228) );
AOI222X4TS U1901 ( .A0(intDX_EWSW[35]), .A1(n3663), .B0(intDX_EWSW[35]),
.B1(n2201), .C0(n3663), .C1(n2201), .Y(n2097) );
AOI222X2TS U1902 ( .A0(DmP_mant_SFG_SWR[19]), .A1(DMP_SFG[17]), .B0(
DmP_mant_SFG_SWR[19]), .B1(n3426), .C0(DMP_SFG[17]), .C1(n3426), .Y(
n3432) );
AOI222X2TS U1903 ( .A0(DmP_mant_SFG_SWR[37]), .A1(DMP_SFG[35]), .B0(
DmP_mant_SFG_SWR[37]), .B1(n3539), .C0(DMP_SFG[35]), .C1(n3539), .Y(
n3545) );
AOI222X2TS U1904 ( .A0(DmP_mant_SFG_SWR[13]), .A1(DMP_SFG[11]), .B0(
DmP_mant_SFG_SWR[13]), .B1(n3389), .C0(DMP_SFG[11]), .C1(n3389), .Y(
n3395) );
AOI211X1TS U1905 ( .A0(n2032), .A1(n2283), .B0(n2327), .C0(n2282), .Y(n2479)
);
INVX2TS U1906 ( .A(n1957), .Y(n1958) );
INVX2TS U1907 ( .A(n2406), .Y(n2407) );
INVX2TS U1908 ( .A(Shift_reg_FLAGS_7[0]), .Y(n3136) );
OAI211X1TS U1909 ( .A0(n3085), .A1(n1948), .B0(n2744), .C0(n2743), .Y(n2749)
);
AO21XLTS U1910 ( .A0(n1947), .A1(n3051), .B0(n2640), .Y(n1932) );
AO21XLTS U1911 ( .A0(n1947), .A1(n3041), .B0(n2652), .Y(n1931) );
AO21XLTS U1912 ( .A0(n1969), .A1(n3054), .B0(n2824), .Y(n1933) );
CLKBUFX3TS U1913 ( .A(n2885), .Y(n3192) );
OAI222X1TS U1914 ( .A0(n3221), .A1(n1985), .B0(n3209), .B1(n2974), .C0(n3693), .C1(n3219), .Y(n1132) );
OAI222X1TS U1915 ( .A0(n3212), .A1(n2973), .B0(n3202), .B1(n2972), .C0(n3694), .C1(n3219), .Y(n1130) );
OAI222X1TS U1916 ( .A0(n3209), .A1(n2973), .B0(n3212), .B1(n2972), .C0(n3695), .C1(n3219), .Y(n1128) );
OAI222X1TS U1917 ( .A0(n3202), .A1(n2976), .B0(n1975), .B1(n2975), .C0(n3697), .C1(n3219), .Y(n1112) );
OAI222X1TS U1918 ( .A0(n3212), .A1(n3222), .B0(n3223), .B1(n3220), .C0(n3765), .C1(n3216), .Y(n1153) );
OAI222X1TS U1919 ( .A0(n3221), .A1(n3215), .B0(n3202), .B1(n3214), .C0(n3767), .C1(n3216), .Y(n1147) );
OAI222X1TS U1920 ( .A0(n3221), .A1(n3213), .B0(n3223), .B1(n3211), .C0(n3768), .C1(n3219), .Y(n1145) );
OAI222X1TS U1921 ( .A0(n1975), .A1(n3205), .B0(n3202), .B1(n3204), .C0(n3769), .C1(n3216), .Y(n1137) );
OAI222X1TS U1922 ( .A0(n3212), .A1(n1987), .B0(n3209), .B1(n3210), .C0(n3770), .C1(n3219), .Y(n1133) );
OAI222X1TS U1923 ( .A0(n3221), .A1(n1986), .B0(n3223), .B1(n3208), .C0(n3771), .C1(n3216), .Y(n1131) );
BUFX4TS U1924 ( .A(n4034), .Y(n4035) );
OA21XLTS U1925 ( .A0(n3750), .A1(n2564), .B0(n2341), .Y(n1896) );
OA21XLTS U1926 ( .A0(n3712), .A1(n3317), .B0(n2371), .Y(n1897) );
OA21XLTS U1927 ( .A0(n3761), .A1(n2943), .B0(n2503), .Y(n1898) );
OA21XLTS U1928 ( .A0(n3676), .A1(n2943), .B0(n2501), .Y(n1899) );
OA21XLTS U1929 ( .A0(n3760), .A1(n2943), .B0(n2336), .Y(n1900) );
OA21XLTS U1930 ( .A0(n3755), .A1(n2564), .B0(n2353), .Y(n1901) );
OA21XLTS U1931 ( .A0(n3690), .A1(n2585), .B0(n2348), .Y(n1902) );
OA21XLTS U1932 ( .A0(n3698), .A1(n2585), .B0(n2346), .Y(n1903) );
OA21XLTS U1933 ( .A0(n3699), .A1(n2564), .B0(n2528), .Y(n1904) );
OA21XLTS U1934 ( .A0(n3702), .A1(n2564), .B0(n2563), .Y(n1905) );
OA21XLTS U1935 ( .A0(n3751), .A1(n2564), .B0(n2440), .Y(n1906) );
OA21XLTS U1936 ( .A0(n3707), .A1(n2605), .B0(n2532), .Y(n1907) );
OA21XLTS U1937 ( .A0(n3705), .A1(n2585), .B0(n2546), .Y(n1908) );
OA21XLTS U1938 ( .A0(n3704), .A1(n2585), .B0(n2545), .Y(n1909) );
OA21XLTS U1939 ( .A0(n3759), .A1(n2585), .B0(n2542), .Y(n1910) );
OA21XLTS U1940 ( .A0(n3677), .A1(n2585), .B0(n2584), .Y(n1911) );
OA21XLTS U1941 ( .A0(n3754), .A1(n2605), .B0(n2536), .Y(n1912) );
OA21XLTS U1942 ( .A0(n3703), .A1(n2605), .B0(n2363), .Y(n1913) );
OA21XLTS U1943 ( .A0(n3711), .A1(n3317), .B0(n2385), .Y(n1914) );
OA21XLTS U1944 ( .A0(n3828), .A1(n3317), .B0(n2384), .Y(n1915) );
OA21XLTS U1945 ( .A0(n3830), .A1(n3317), .B0(n2380), .Y(n1916) );
OA21XLTS U1946 ( .A0(n3831), .A1(n2605), .B0(n2531), .Y(n1917) );
OA21XLTS U1947 ( .A0(n3803), .A1(n2585), .B0(n2550), .Y(n1918) );
OA21XLTS U1948 ( .A0(n3825), .A1(n2585), .B0(n2349), .Y(n1919) );
OA21XLTS U1949 ( .A0(n3805), .A1(n2564), .B0(n2357), .Y(n1920) );
OA21XLTS U1950 ( .A0(n3820), .A1(n2564), .B0(n2443), .Y(n1921) );
OA21XLTS U1951 ( .A0(n3819), .A1(n2564), .B0(n2442), .Y(n1922) );
OA21XLTS U1952 ( .A0(n3682), .A1(n2605), .B0(n2333), .Y(n1923) );
OA21XLTS U1953 ( .A0(n3821), .A1(n3317), .B0(n2362), .Y(n1924) );
OA21XLTS U1954 ( .A0(n3869), .A1(n2605), .B0(n2278), .Y(n1925) );
OA21XLTS U1955 ( .A0(n3670), .A1(n2605), .B0(n2539), .Y(n1926) );
OA21XLTS U1956 ( .A0(n3829), .A1(n2605), .B0(n2846), .Y(n1927) );
OA21XLTS U1957 ( .A0(n3685), .A1(n2585), .B0(n2347), .Y(n1928) );
CLKBUFX3TS U1958 ( .A(n3903), .Y(n3584) );
OA21XLTS U1959 ( .A0(shift_value_SHT2_EWR[4]), .A1(n1958), .B0(n3058), .Y(
n1929) );
OA21XLTS U1960 ( .A0(n3688), .A1(n2564), .B0(n2342), .Y(n1930) );
OR4X2TS U1961 ( .A(Raw_mant_NRM_SWR[12]), .B(Raw_mant_NRM_SWR[10]), .C(
Raw_mant_NRM_SWR[11]), .D(n2475), .Y(n1934) );
OA21XLTS U1962 ( .A0(n3762), .A1(n2605), .B0(n2339), .Y(n1935) );
OR3X1TS U1963 ( .A(n2485), .B(Raw_mant_NRM_SWR[18]), .C(Raw_mant_NRM_SWR[17]), .Y(n1936) );
OR2X1TS U1964 ( .A(n2434), .B(n2433), .Y(n1937) );
CLKBUFX3TS U1965 ( .A(clk), .Y(n2267) );
OR2X1TS U1966 ( .A(shift_value_SHT2_EWR[4]), .B(n3911), .Y(n1938) );
OR2X1TS U1967 ( .A(n1958), .B(n1973), .Y(n1939) );
AND2X2TS U1968 ( .A(n3130), .B(n1958), .Y(n1940) );
OR2X1TS U1969 ( .A(n2949), .B(n1955), .Y(n1941) );
OR2X1TS U1970 ( .A(n2946), .B(n1955), .Y(n1942) );
OR2X1TS U1971 ( .A(n2666), .B(n1955), .Y(n1943) );
OR2X1TS U1972 ( .A(n2803), .B(n1955), .Y(n1944) );
OR2X1TS U1973 ( .A(left_right_SHT2), .B(n1955), .Y(n1945) );
NAND2X1TS U1974 ( .A(n3911), .B(shift_value_SHT2_EWR[4]), .Y(n2953) );
CLKBUFX3TS U1975 ( .A(n3137), .Y(n3164) );
OAI21X1TS U1976 ( .A0(n1948), .A1(n2820), .B0(n3134), .Y(n1946) );
INVX2TS U1977 ( .A(n2953), .Y(n1947) );
INVX2TS U1978 ( .A(n1947), .Y(n1948) );
INVX2TS U1979 ( .A(n1939), .Y(n1949) );
INVX2TS U1980 ( .A(n1939), .Y(n1950) );
INVX2TS U1981 ( .A(n1940), .Y(n1951) );
INVX2TS U1982 ( .A(n1940), .Y(n1952) );
INVX2TS U1983 ( .A(n1945), .Y(n1953) );
INVX2TS U1984 ( .A(n1945), .Y(n1954) );
INVX2TS U1985 ( .A(n2035), .Y(n1955) );
INVX2TS U1986 ( .A(n2035), .Y(n1956) );
INVX2TS U1987 ( .A(n3746), .Y(n1957) );
INVX2TS U1988 ( .A(n1938), .Y(n1959) );
INVX2TS U1989 ( .A(n1938), .Y(n1960) );
INVX2TS U1990 ( .A(n1941), .Y(n1961) );
INVX2TS U1991 ( .A(n1941), .Y(n1962) );
INVX2TS U1992 ( .A(n1943), .Y(n1963) );
INVX2TS U1993 ( .A(n1943), .Y(n1964) );
INVX2TS U1994 ( .A(n1944), .Y(n1965) );
INVX2TS U1995 ( .A(n1944), .Y(n1966) );
INVX2TS U1996 ( .A(n1942), .Y(n1967) );
INVX2TS U1997 ( .A(n1942), .Y(n1968) );
INVX2TS U1998 ( .A(n2953), .Y(n1969) );
CLKINVX3TS U1999 ( .A(n2849), .Y(n3317) );
INVX2TS U2000 ( .A(n2849), .Y(n2605) );
NOR4X2TS U2001 ( .A(Raw_mant_NRM_SWR[46]), .B(Raw_mant_NRM_SWR[45]), .C(
Raw_mant_NRM_SWR[44]), .D(n2468), .Y(n2281) );
OAI21X1TS U2002 ( .A0(n3894), .A1(n2949), .B0(n2741), .Y(n2742) );
OAI21X1TS U2003 ( .A0(n3896), .A1(n2949), .B0(n2948), .Y(n2950) );
OAI222X1TS U2004 ( .A0(n3202), .A1(n1985), .B0(n1975), .B1(n2974), .C0(n3696), .C1(n3216), .Y(n1126) );
OAI222X1TS U2005 ( .A0(n3223), .A1(n3157), .B0(n3221), .B1(n3156), .C0(n3858), .C1(n3216), .Y(n1102) );
OAI222X1TS U2006 ( .A0(n3202), .A1(n1986), .B0(n1975), .B1(n3208), .C0(n3772), .C1(n3216), .Y(n1127) );
OAI222X1TS U2007 ( .A0(n3223), .A1(n3213), .B0(n3221), .B1(n3211), .C0(n3774), .C1(n3216), .Y(n1113) );
OAI222X1TS U2008 ( .A0(n2436), .A1(n2976), .B0(n3202), .B1(n2975), .C0(n3692), .C1(n3216), .Y(n1146) );
CLKINVX3TS U2009 ( .A(n3164), .Y(n3216) );
AOI211X1TS U2010 ( .A0(n1953), .A1(n3090), .B0(n3076), .C0(n3075), .Y(n3077)
);
INVX2TS U2011 ( .A(n1937), .Y(n1970) );
NAND2X2TS U2012 ( .A(n2661), .B(n2660), .Y(n3031) );
NOR2X2TS U2013 ( .A(n1934), .B(Raw_mant_NRM_SWR[9]), .Y(n2476) );
CLKBUFX3TS U2014 ( .A(n3164), .Y(n3145) );
INVX2TS U2015 ( .A(n1929), .Y(n1971) );
AOI211XLTS U2016 ( .A0(n2400), .A1(n2471), .B0(n2399), .C0(n2398), .Y(n2401)
);
AOI211X1TS U2017 ( .A0(n2459), .A1(Raw_mant_NRM_SWR[21]), .B0(n2471), .C0(
n2458), .Y(n2460) );
NOR2X2TS U2018 ( .A(n3831), .B(n2394), .Y(n2471) );
BUFX3TS U2019 ( .A(clk), .Y(n4085) );
INVX2TS U2020 ( .A(n3318), .Y(n1972) );
INVX2TS U2021 ( .A(n1972), .Y(n1973) );
AOI21X2TS U2022 ( .A0(Data_array_SWR[21]), .A1(n2635), .B0(n2430), .Y(n3074)
);
OAI21X1TS U2023 ( .A0(n3895), .A1(n2949), .B0(n2429), .Y(n2430) );
CLKBUFX3TS U2024 ( .A(n3250), .Y(n3255) );
AOI211XLTS U2025 ( .A0(Raw_mant_NRM_SWR[47]), .A1(n2296), .B0(n2293), .C0(
n2292), .Y(n2295) );
NOR2X2TS U2026 ( .A(Raw_mant_NRM_SWR[48]), .B(n2279), .Y(n2296) );
CLKINVX3TS U2027 ( .A(n3254), .Y(busy) );
CLKBUFX3TS U2028 ( .A(n3504), .Y(n3649) );
OAI21X2TS U2029 ( .A0(n3760), .A1(n2851), .B0(n2850), .Y(n2891) );
INVX2TS U2030 ( .A(n1935), .Y(n1974) );
NOR2X2TS U2031 ( .A(intDX_EWSW[26]), .B(n3715), .Y(n2198) );
OAI21X2TS U2032 ( .A0(n1956), .A1(n3102), .B0(n2765), .Y(n2739) );
CLKINVX3TS U2033 ( .A(n2518), .Y(n2565) );
CLKINVX3TS U2034 ( .A(n2518), .Y(n2890) );
CLKINVX3TS U2035 ( .A(n2518), .Y(n2941) );
CLKINVX3TS U2036 ( .A(n2519), .Y(n2597) );
CLKINVX3TS U2037 ( .A(n2519), .Y(n2631) );
INVX2TS U2038 ( .A(n2519), .Y(n2568) );
CLKBUFX3TS U2039 ( .A(n3590), .Y(n3622) );
CLKINVX3TS U2040 ( .A(rst), .Y(n4086) );
INVX2TS U2041 ( .A(n2498), .Y(n1975) );
OAI222X4TS U2042 ( .A0(n3209), .A1(n1987), .B0(n3212), .B1(n3210), .C0(n3773), .C1(n3305), .Y(n1125) );
OAI222X4TS U2043 ( .A0(n3202), .A1(n3205), .B0(n3212), .B1(n3204), .C0(n3716), .C1(n3305), .Y(n1121) );
OAI222X4TS U2044 ( .A0(n1975), .A1(n3218), .B0(n3223), .B1(n3217), .C0(n3766), .C1(n3305), .Y(n1149) );
OAI222X4TS U2045 ( .A0(n1975), .A1(n2979), .B0(n3209), .B1(n1978), .C0(n3686), .C1(n3305), .Y(n1154) );
OAI21X4TS U2046 ( .A0(Data_array_SWR[54]), .A1(n2946), .B0(n2945), .Y(n3123)
);
OAI21X4TS U2047 ( .A0(Data_array_SWR[52]), .A1(n2946), .B0(n2945), .Y(n3092)
);
OAI21X4TS U2048 ( .A0(Data_array_SWR[53]), .A1(n2946), .B0(n2945), .Y(n3102)
);
NAND2X2TS U2049 ( .A(n2946), .B(n3852), .Y(n2945) );
CLKINVX3TS U2050 ( .A(n2803), .Y(n2825) );
CLKINVX3TS U2051 ( .A(n2803), .Y(n2947) );
CLKINVX3TS U2052 ( .A(n2466), .Y(n2603) );
CLKINVX3TS U2053 ( .A(n2946), .Y(n2954) );
INVX2TS U2054 ( .A(n2578), .Y(n1976) );
INVX2TS U2055 ( .A(n1976), .Y(n1977) );
OAI21XLTS U2056 ( .A0(n3826), .A1(n2605), .B0(n2517), .Y(n2578) );
CLKINVX3TS U2057 ( .A(n2934), .Y(n2815) );
CLKINVX3TS U2058 ( .A(n2934), .Y(n2899) );
CLKINVX3TS U2059 ( .A(n2934), .Y(n2936) );
CLKINVX3TS U2060 ( .A(n2934), .Y(n2686) );
CLKINVX3TS U2061 ( .A(n2852), .Y(n2845) );
CLKINVX3TS U2062 ( .A(n2851), .Y(n2583) );
INVX2TS U2063 ( .A(n2971), .Y(n1978) );
INVX2TS U2064 ( .A(n1978), .Y(n1979) );
OAI21XLTS U2065 ( .A0(n1956), .A1(n3092), .B0(n2765), .Y(n2971) );
CLKINVX3TS U2066 ( .A(n3649), .Y(n3651) );
CLKINVX3TS U2067 ( .A(n3649), .Y(n3583) );
CLKINVX3TS U2068 ( .A(n2406), .Y(n2942) );
CLKINVX3TS U2069 ( .A(n2406), .Y(n2621) );
CLKINVX3TS U2070 ( .A(n2406), .Y(n2629) );
CLKINVX3TS U2071 ( .A(n2406), .Y(n2573) );
CLKBUFX3TS U2072 ( .A(n3137), .Y(n3250) );
INVX2TS U2073 ( .A(n3045), .Y(n1980) );
CLKINVX3TS U2074 ( .A(n1980), .Y(n1981) );
NAND2X1TS U2075 ( .A(shift_value_SHT2_EWR[4]), .B(n3058), .Y(n3045) );
INVX2TS U2076 ( .A(n3133), .Y(n1982) );
INVX2TS U2077 ( .A(n1982), .Y(n1983) );
OAI211X2TS U2078 ( .A0(n2666), .A1(n3919), .B0(n2641), .C0(n2801), .Y(n3043)
);
OAI211X2TS U2079 ( .A0(n2666), .A1(n3918), .B0(n2653), .C0(n2801), .Y(n3033)
);
OAI211X2TS U2080 ( .A0(n2666), .A1(n3917), .B0(n2665), .C0(n2801), .Y(n3024)
);
NAND2X2TS U2081 ( .A(n2960), .B(bit_shift_SHT2), .Y(n2801) );
NAND2X4TS U2082 ( .A(shift_value_SHT2_EWR[5]), .B(bit_shift_SHT2), .Y(n3134)
);
CLKINVX3TS U2083 ( .A(n3190), .Y(n3219) );
CLKBUFX3TS U2084 ( .A(n3145), .Y(n3190) );
INVX2TS U2085 ( .A(n1936), .Y(n1984) );
BUFX3TS U2086 ( .A(n4084), .Y(n4083) );
CLKBUFX3TS U2087 ( .A(n3297), .Y(n3302) );
CLKBUFX3TS U2088 ( .A(n3297), .Y(n3301) );
CLKBUFX3TS U2089 ( .A(n3297), .Y(n3321) );
AOI222X4TS U2090 ( .A0(n2345), .A1(DmP_mant_SHT1_SW[24]), .B0(
Raw_mant_NRM_SWR[26]), .B1(n2849), .C0(Raw_mant_NRM_SWR[28]), .C1(
n2603), .Y(n2582) );
CLKBUFX3TS U2091 ( .A(n2045), .Y(n2047) );
BUFX4TS U2092 ( .A(n2267), .Y(n4043) );
BUFX4TS U2093 ( .A(n4085), .Y(n4025) );
BUFX4TS U2094 ( .A(clk), .Y(n4039) );
BUFX4TS U2095 ( .A(n2276), .Y(n4021) );
BUFX4TS U2096 ( .A(n2276), .Y(n4018) );
BUFX4TS U2097 ( .A(n2275), .Y(n4072) );
BUFX4TS U2098 ( .A(n2267), .Y(n4048) );
BUFX4TS U2099 ( .A(n2270), .Y(n4061) );
BUFX4TS U2100 ( .A(n2269), .Y(n4054) );
AOI222X4TS U2101 ( .A0(n3383), .A1(n3810), .B0(n3383), .B1(n3719), .C0(n3810), .C1(n3719), .Y(n3389) );
AOI222X4TS U2102 ( .A0(DmP_mant_SFG_SWR[21]), .A1(DMP_SFG[19]), .B0(
DmP_mant_SFG_SWR[21]), .B1(n3438), .C0(DMP_SFG[19]), .C1(n3438), .Y(
n3444) );
AOI222X4TS U2103 ( .A0(n3432), .A1(n3814), .B0(n3432), .B1(n3723), .C0(n3814), .C1(n3723), .Y(n3438) );
AOI222X4TS U2104 ( .A0(DmP_mant_SFG_SWR[35]), .A1(DMP_SFG[33]), .B0(
DmP_mant_SFG_SWR[35]), .B1(n3527), .C0(DMP_SFG[33]), .C1(n3527), .Y(
n3533) );
AOI222X4TS U2105 ( .A0(n3521), .A1(n3729), .B0(n3521), .B1(n3787), .C0(n3729), .C1(n3787), .Y(n3527) );
AOI222X4TS U2106 ( .A0(DmP_mant_SFG_SWR[39]), .A1(DMP_SFG[37]), .B0(
DmP_mant_SFG_SWR[39]), .B1(n3551), .C0(DMP_SFG[37]), .C1(n3551), .Y(
n3558) );
AOI222X4TS U2107 ( .A0(n3545), .A1(n3731), .B0(n3545), .B1(n3789), .C0(n3731), .C1(n3789), .Y(n3551) );
AOI222X4TS U2108 ( .A0(DmP_mant_SFG_SWR[17]), .A1(DMP_SFG[15]), .B0(
DmP_mant_SFG_SWR[17]), .B1(n3414), .C0(DMP_SFG[15]), .C1(n3414), .Y(
n3420) );
AOI222X4TS U2109 ( .A0(n3408), .A1(n3812), .B0(n3408), .B1(n3721), .C0(n3812), .C1(n3721), .Y(n3414) );
AOI222X4TS U2110 ( .A0(DmP_mant_SFG_SWR[31]), .A1(DMP_SFG[29]), .B0(
DmP_mant_SFG_SWR[31]), .B1(n3501), .C0(DMP_SFG[29]), .C1(n3501), .Y(
n3508) );
AOI222X4TS U2111 ( .A0(n3495), .A1(n3696), .B0(n3495), .B1(n3786), .C0(n3696), .C1(n3786), .Y(n3501) );
AOI222X4TS U2112 ( .A0(DmP_mant_SFG_SWR[45]), .A1(DMP_SFG[43]), .B0(
DmP_mant_SFG_SWR[45]), .B1(n3594), .C0(DMP_SFG[43]), .C1(n3594), .Y(
n3601) );
AOI222X4TS U2113 ( .A0(n3587), .A1(n3697), .B0(n3587), .B1(n3792), .C0(n3697), .C1(n3792), .Y(n3594) );
AOI222X4TS U2114 ( .A0(DmP_mant_SFG_SWR[53]), .A1(DMP_SFG[51]), .B0(
DmP_mant_SFG_SWR[53]), .B1(n3645), .C0(DMP_SFG[51]), .C1(n3645), .Y(
n3654) );
AOI222X4TS U2115 ( .A0(n3639), .A1(n3674), .B0(n3639), .B1(n3794), .C0(n3674), .C1(n3794), .Y(n3645) );
AOI222X4TS U2116 ( .A0(DmP_mant_SFG_SWR[9]), .A1(DMP_SFG[7]), .B0(
DmP_mant_SFG_SWR[9]), .B1(n3364), .C0(DMP_SFG[7]), .C1(n3364), .Y(
n3370) );
AOI222X4TS U2117 ( .A0(n3166), .A1(n3691), .B0(n3166), .B1(n3781), .C0(n3691), .C1(n3781), .Y(n3364) );
AOI222X4TS U2118 ( .A0(DmP_mant_SFG_SWR[25]), .A1(DMP_SFG[23]), .B0(
DmP_mant_SFG_SWR[25]), .B1(n3463), .C0(DMP_SFG[23]), .C1(n3463), .Y(
n3470) );
AOI222X4TS U2119 ( .A0(n3457), .A1(n3693), .B0(n3457), .B1(n3783), .C0(n3693), .C1(n3783), .Y(n3463) );
CLKBUFX3TS U2120 ( .A(n2044), .Y(n4000) );
BUFX3TS U2121 ( .A(n2044), .Y(n2043) );
INVX2TS U2122 ( .A(n1932), .Y(n1985) );
INVX2TS U2123 ( .A(n1931), .Y(n1986) );
INVX2TS U2124 ( .A(n1933), .Y(n1987) );
NOR2X2TS U2125 ( .A(n2040), .B(n2593), .Y(n2496) );
INVX2TS U2126 ( .A(n1930), .Y(n1988) );
INVX2TS U2127 ( .A(n1896), .Y(n1989) );
INVX2TS U2128 ( .A(n1902), .Y(n1990) );
INVX2TS U2129 ( .A(n1910), .Y(n1991) );
INVX2TS U2130 ( .A(n1898), .Y(n1992) );
INVX2TS U2131 ( .A(n1908), .Y(n1993) );
INVX2TS U2132 ( .A(n1899), .Y(n1994) );
INVX2TS U2133 ( .A(n1912), .Y(n1995) );
OAI21X2TS U2134 ( .A0(n3690), .A1(n2466), .B0(n2360), .Y(n2622) );
CLKBUFX3TS U2135 ( .A(n2852), .Y(n2466) );
INVX2TS U2136 ( .A(n1909), .Y(n1996) );
INVX2TS U2137 ( .A(n1903), .Y(n1997) );
INVX2TS U2138 ( .A(n1913), .Y(n1998) );
INVX2TS U2139 ( .A(n1900), .Y(n1999) );
OAI21X2TS U2140 ( .A0(n3708), .A1(n2943), .B0(n2504), .Y(n2598) );
INVX2TS U2141 ( .A(n1907), .Y(n2000) );
INVX2TS U2142 ( .A(n1906), .Y(n2001) );
INVX2TS U2143 ( .A(n1905), .Y(n2002) );
INVX2TS U2144 ( .A(n1901), .Y(n2003) );
INVX2TS U2145 ( .A(n1914), .Y(n2004) );
INVX2TS U2146 ( .A(n1904), .Y(n2005) );
INVX2TS U2147 ( .A(n1911), .Y(n2006) );
INVX2TS U2148 ( .A(n1897), .Y(n2007) );
INVX2TS U2149 ( .A(n1919), .Y(n2008) );
INVX2TS U2150 ( .A(n1922), .Y(n2009) );
INVX2TS U2151 ( .A(n1917), .Y(n2010) );
INVX2TS U2152 ( .A(n1918), .Y(n2011) );
INVX2TS U2153 ( .A(n1924), .Y(n2012) );
INVX2TS U2154 ( .A(n1921), .Y(n2013) );
INVX2TS U2155 ( .A(n1920), .Y(n2014) );
INVX2TS U2156 ( .A(n1916), .Y(n2015) );
INVX2TS U2157 ( .A(n1915), .Y(n2016) );
INVX2TS U2158 ( .A(n1927), .Y(n2017) );
INVX2TS U2159 ( .A(n1926), .Y(n2018) );
INVX2TS U2160 ( .A(n1928), .Y(n2019) );
INVX2TS U2161 ( .A(n1923), .Y(n2020) );
INVX2TS U2162 ( .A(n1925), .Y(n2021) );
OAI21X2TS U2163 ( .A0(n3747), .A1(n2852), .B0(n2361), .Y(n2374) );
BUFX4TS U2164 ( .A(n4076), .Y(n2022) );
BUFX4TS U2165 ( .A(n4076), .Y(n4044) );
BUFX6TS U2166 ( .A(n4076), .Y(n4040) );
BUFX6TS U2167 ( .A(n4076), .Y(n4047) );
BUFX6TS U2168 ( .A(n4076), .Y(n4042) );
BUFX6TS U2169 ( .A(n2267), .Y(n4076) );
BUFX6TS U2170 ( .A(n4019), .Y(n4008) );
BUFX6TS U2171 ( .A(n4019), .Y(n4013) );
BUFX3TS U2172 ( .A(n4034), .Y(n2023) );
BUFX6TS U2173 ( .A(n4084), .Y(n4082) );
BUFX3TS U2174 ( .A(n4085), .Y(n4084) );
BUFX4TS U2175 ( .A(n4034), .Y(n4032) );
BUFX6TS U2176 ( .A(n4034), .Y(n4033) );
BUFX6TS U2177 ( .A(n4034), .Y(n4038) );
BUFX6TS U2178 ( .A(n4023), .Y(n4034) );
BUFX6TS U2179 ( .A(n4019), .Y(n4020) );
BUFX6TS U2180 ( .A(n4019), .Y(n4017) );
BUFX6TS U2181 ( .A(n4019), .Y(n4015) );
BUFX6TS U2182 ( .A(n4019), .Y(n4014) );
BUFX4TS U2183 ( .A(n4080), .Y(n4081) );
BUFX4TS U2184 ( .A(clk), .Y(n2265) );
BUFX6TS U2185 ( .A(clk), .Y(n4036) );
BUFX4TS U2186 ( .A(n2267), .Y(n4037) );
BUFX6TS U2187 ( .A(n2270), .Y(n4066) );
BUFX6TS U2188 ( .A(n2267), .Y(n2266) );
BUFX6TS U2189 ( .A(n2267), .Y(n4046) );
BUFX4TS U2190 ( .A(n2267), .Y(n4045) );
BUFX4TS U2191 ( .A(n2267), .Y(n2273) );
BUFX4TS U2192 ( .A(n2270), .Y(n4078) );
BUFX6TS U2193 ( .A(n2270), .Y(n4063) );
BUFX6TS U2194 ( .A(n2270), .Y(n4064) );
BUFX4TS U2195 ( .A(n2270), .Y(n2272) );
BUFX6TS U2196 ( .A(n2275), .Y(n4070) );
BUFX6TS U2197 ( .A(n4060), .Y(n4080) );
BUFX6TS U2198 ( .A(n4083), .Y(n4030) );
BUFX6TS U2199 ( .A(n4085), .Y(n4027) );
BUFX4TS U2200 ( .A(n2267), .Y(n4028) );
BUFX6TS U2201 ( .A(n2269), .Y(n4052) );
BUFX4TS U2202 ( .A(n2275), .Y(n2274) );
BUFX6TS U2203 ( .A(n2275), .Y(n4009) );
BUFX6TS U2204 ( .A(n2275), .Y(n4073) );
BUFX6TS U2205 ( .A(n2275), .Y(n4075) );
BUFX4TS U2206 ( .A(n2274), .Y(n2024) );
BUFX4TS U2207 ( .A(n2274), .Y(n4074) );
BUFX6TS U2208 ( .A(n2274), .Y(n4007) );
BUFX6TS U2209 ( .A(n2274), .Y(n4067) );
BUFX6TS U2210 ( .A(n2274), .Y(n4068) );
BUFX4TS U2211 ( .A(n2269), .Y(n2268) );
BUFX6TS U2212 ( .A(n2269), .Y(n4079) );
BUFX6TS U2213 ( .A(n2269), .Y(n4057) );
BUFX6TS U2214 ( .A(n2269), .Y(n4055) );
CLKINVX6TS U2215 ( .A(n2027), .Y(n2025) );
BUFX4TS U2216 ( .A(n2268), .Y(n2026) );
BUFX4TS U2217 ( .A(n2268), .Y(n4056) );
BUFX6TS U2218 ( .A(n2268), .Y(n4011) );
BUFX6TS U2219 ( .A(n2268), .Y(n4049) );
BUFX6TS U2220 ( .A(n2268), .Y(n4050) );
BUFX4TS U2221 ( .A(n4080), .Y(n4010) );
BUFX6TS U2222 ( .A(n4080), .Y(n4029) );
BUFX6TS U2223 ( .A(n4080), .Y(n4024) );
BUFX6TS U2224 ( .A(n4080), .Y(n4026) );
INVX2TS U2225 ( .A(n4060), .Y(n2027) );
CLKINVX6TS U2226 ( .A(n2027), .Y(n2028) );
BUFX6TS U2227 ( .A(n4078), .Y(n4005) );
BUFX6TS U2228 ( .A(n4078), .Y(n4059) );
BUFX6TS U2229 ( .A(n4078), .Y(n4058) );
BUFX6TS U2230 ( .A(n4078), .Y(n4062) );
BUFX6TS U2231 ( .A(n2276), .Y(n4077) );
BUFX6TS U2232 ( .A(n2276), .Y(n2271) );
BUFX4TS U2233 ( .A(n2276), .Y(n4016) );
INVX2TS U2234 ( .A(ADD_OVRFLW_NRM2), .Y(n2029) );
NOR2X2TS U2235 ( .A(Raw_mant_NRM_SWR[22]), .B(n2280), .Y(n2459) );
CLKBUFX2TS U2236 ( .A(n2728), .Y(n2030) );
OR4X2TS U2237 ( .A(Raw_mant_NRM_SWR[54]), .B(Raw_mant_NRM_SWR[53]), .C(
Raw_mant_NRM_SWR[52]), .D(Raw_mant_NRM_SWR[51]), .Y(n2395) );
INVX2TS U2238 ( .A(n2395), .Y(n2031) );
NOR4BBX2TS U2239 ( .AN(n2163), .BN(n2155), .C(n2154), .D(n2153), .Y(n2260)
);
CLKBUFX3TS U2240 ( .A(n3017), .Y(n3007) );
CLKINVX3TS U2241 ( .A(n3584), .Y(n3572) );
CLKINVX3TS U2242 ( .A(n3584), .Y(n3579) );
CLKINVX3TS U2243 ( .A(n3584), .Y(n3646) );
CLKBUFX3TS U2244 ( .A(n2724), .Y(n2856) );
CLKBUFX3TS U2245 ( .A(n2909), .Y(n2724) );
INVX2TS U2246 ( .A(n1934), .Y(n2032) );
AOI222X4TS U2247 ( .A0(DMP_SFG[0]), .A1(n3165), .B0(DMP_SFG[0]), .B1(n3686),
.C0(n3165), .C1(n3686), .Y(n3333) );
NOR2X2TS U2248 ( .A(DmP_mant_SFG_SWR[1]), .B(DmP_mant_SFG_SWR[0]), .Y(n3165)
);
NOR2X2TS U2249 ( .A(intDX_EWSW[22]), .B(n3908), .Y(n2225) );
NOR2X2TS U2250 ( .A(intDX_EWSW[46]), .B(n3668), .Y(n2246) );
AOI21X2TS U2251 ( .A0(Data_array_SWR[22]), .A1(n2635), .B0(n2742), .Y(n3085)
);
AOI21X2TS U2252 ( .A0(Data_array_SWR[20]), .A1(n2635), .B0(n2950), .Y(n3066)
);
CLKBUFX3TS U2253 ( .A(n2642), .Y(n2635) );
NOR2X2TS U2254 ( .A(Raw_mant_NRM_SWR[36]), .B(n2307), .Y(n2452) );
CLKBUFX3TS U2255 ( .A(n3148), .Y(n3236) );
NOR2X2TS U2256 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n3841), .Y(n3158) );
NOR2X2TS U2257 ( .A(Raw_mant_NRM_SWR[25]), .B(n2461), .Y(n2483) );
NAND2X2TS U2258 ( .A(n2472), .B(n3865), .Y(n2461) );
NOR2X2TS U2259 ( .A(intDX_EWSW[20]), .B(n3907), .Y(n2185) );
NAND2X2TS U2260 ( .A(shift_value_SHT2_EWR[3]), .B(bit_shift_SHT2), .Y(n2955)
);
CLKINVX3TS U2261 ( .A(n2518), .Y(n2577) );
CLKINVX3TS U2262 ( .A(n2519), .Y(n2606) );
OAI222X4TS U2263 ( .A0(n1975), .A1(n2978), .B0(n3209), .B1(n2977), .C0(n3691), .C1(n3305), .Y(n1148) );
AOI211XLTS U2264 ( .A0(intDX_EWSW[32]), .A1(n3748), .B0(n2232), .C0(n2148),
.Y(n2149) );
OAI211X2TS U2265 ( .A0(intDY_EWSW[36]), .A1(n3900), .B0(n2099), .C0(n2098),
.Y(n2232) );
CLKINVX3TS U2266 ( .A(n2803), .Y(n3015) );
AOI211X1TS U2267 ( .A0(n3915), .A1(intDX_EWSW[16]), .B0(n2126), .C0(n2125),
.Y(n2190) );
OAI22X2TS U2268 ( .A0(intDY_EWSW[19]), .A1(n3801), .B0(intDY_EWSW[18]), .B1(
n3710), .Y(n2126) );
CLKBUFX3TS U2269 ( .A(n2914), .Y(n2922) );
CLKINVX3TS U2270 ( .A(n3192), .Y(n2903) );
OAI222X1TS U2271 ( .A0(n3192), .A1(n3737), .B0(n3857), .B1(
Shift_reg_FLAGS_7_6), .C0(n3666), .C1(n3191), .Y(n1291) );
OAI222X1TS U2272 ( .A0(n3192), .A1(n3879), .B0(n3743), .B1(
Shift_reg_FLAGS_7_6), .C0(n3667), .C1(n3191), .Y(n1293) );
OAI222X1TS U2273 ( .A0(n3191), .A1(n3737), .B0(n3832), .B1(
Shift_reg_FLAGS_7_6), .C0(n3666), .C1(n3192), .Y(n1620) );
CLKBUFX3TS U2274 ( .A(n4002), .Y(n4003) );
CLKBUFX3TS U2275 ( .A(n2047), .Y(n4002) );
AOI222X4TS U2276 ( .A0(DmP_mant_SFG_SWR[3]), .A1(DMP_SFG[1]), .B0(
DmP_mant_SFG_SWR[3]), .B1(n3332), .C0(DMP_SFG[1]), .C1(n3332), .Y(
n3337) );
AOI222X4TS U2277 ( .A0(DmP_mant_SFG_SWR[5]), .A1(DMP_SFG[3]), .B0(
DmP_mant_SFG_SWR[5]), .B1(n3345), .C0(DMP_SFG[3]), .C1(n3345), .Y(
n3350) );
AOI222X4TS U2278 ( .A0(n3337), .A1(n3808), .B0(n3337), .B1(n3717), .C0(n3808), .C1(n3717), .Y(n3345) );
AOI222X4TS U2279 ( .A0(DmP_mant_SFG_SWR[23]), .A1(DMP_SFG[21]), .B0(
DmP_mant_SFG_SWR[23]), .B1(n3450), .C0(DMP_SFG[21]), .C1(n3450), .Y(
n3457) );
AOI222X4TS U2280 ( .A0(n3444), .A1(n3815), .B0(n3444), .B1(n3724), .C0(n3815), .C1(n3724), .Y(n3450) );
AOI222X4TS U2281 ( .A0(DmP_mant_SFG_SWR[41]), .A1(DMP_SFG[39]), .B0(
DmP_mant_SFG_SWR[41]), .B1(n3565), .C0(DMP_SFG[39]), .C1(n3565), .Y(
n3571) );
AOI222X4TS U2282 ( .A0(n3558), .A1(n3732), .B0(n3558), .B1(n3790), .C0(n3732), .C1(n3790), .Y(n3565) );
AOI222X4TS U2283 ( .A0(DmP_mant_SFG_SWR[47]), .A1(DMP_SFG[45]), .B0(
DmP_mant_SFG_SWR[47]), .B1(n3607), .C0(DMP_SFG[45]), .C1(n3607), .Y(
n3613) );
AOI222X4TS U2284 ( .A0(n3601), .A1(n3673), .B0(n3601), .B1(n3793), .C0(n3673), .C1(n3793), .Y(n3607) );
AOI222X4TS U2285 ( .A0(DmP_mant_SFG_SWR[27]), .A1(DMP_SFG[25]), .B0(
DmP_mant_SFG_SWR[27]), .B1(n3477), .C0(DMP_SFG[25]), .C1(n3477), .Y(
n3483) );
AOI222X4TS U2286 ( .A0(n3470), .A1(n3694), .B0(n3470), .B1(n3784), .C0(n3694), .C1(n3784), .Y(n3477) );
AOI222X4TS U2287 ( .A0(n3613), .A1(n3817), .B0(n3613), .B1(n3726), .C0(n3817), .C1(n3726), .Y(n3619) );
AOI222X4TS U2288 ( .A0(DmP_mant_SFG_SWR[51]), .A1(DMP_SFG[49]), .B0(
DmP_mant_SFG_SWR[51]), .B1(n3633), .C0(DMP_SFG[49]), .C1(n3633), .Y(
n3639) );
AOI222X4TS U2289 ( .A0(n3626), .A1(n3818), .B0(n3626), .B1(n3727), .C0(n3818), .C1(n3727), .Y(n3633) );
AOI222X4TS U2290 ( .A0(DmP_mant_SFG_SWR[29]), .A1(DMP_SFG[27]), .B0(
DmP_mant_SFG_SWR[29]), .B1(n3489), .C0(DMP_SFG[27]), .C1(n3489), .Y(
n3495) );
AOI222X4TS U2291 ( .A0(n3483), .A1(n3695), .B0(n3483), .B1(n3785), .C0(n3695), .C1(n3785), .Y(n3489) );
AOI222X4TS U2292 ( .A0(DmP_mant_SFG_SWR[43]), .A1(DMP_SFG[41]), .B0(
DmP_mant_SFG_SWR[43]), .B1(n3578), .C0(DMP_SFG[41]), .C1(n3578), .Y(
n3587) );
AOI222X4TS U2293 ( .A0(n3571), .A1(n3733), .B0(n3571), .B1(n3791), .C0(n3733), .C1(n3791), .Y(n3578) );
AOI222X4TS U2294 ( .A0(DmP_mant_SFG_SWR[11]), .A1(DMP_SFG[9]), .B0(
DmP_mant_SFG_SWR[11]), .B1(n3376), .C0(DMP_SFG[9]), .C1(n3376), .Y(
n3383) );
AOI222X4TS U2295 ( .A0(n3370), .A1(n3692), .B0(n3370), .B1(n3782), .C0(n3692), .C1(n3782), .Y(n3376) );
AOI222X4TS U2296 ( .A0(DmP_mant_SFG_SWR[33]), .A1(DMP_SFG[31]), .B0(
DmP_mant_SFG_SWR[33]), .B1(n3514), .C0(DMP_SFG[31]), .C1(n3514), .Y(
n3521) );
AOI222X4TS U2297 ( .A0(n3508), .A1(n3816), .B0(n3508), .B1(n3725), .C0(n3816), .C1(n3725), .Y(n3514) );
AOI222X4TS U2298 ( .A0(n3533), .A1(n3730), .B0(n3533), .B1(n3788), .C0(n3730), .C1(n3788), .Y(n3539) );
AOI222X4TS U2299 ( .A0(DmP_mant_SFG_SWR[15]), .A1(DMP_SFG[13]), .B0(
DmP_mant_SFG_SWR[15]), .B1(n3402), .C0(DMP_SFG[13]), .C1(n3402), .Y(
n3408) );
AOI222X4TS U2300 ( .A0(n3395), .A1(n3811), .B0(n3395), .B1(n3720), .C0(n3811), .C1(n3720), .Y(n3402) );
AOI222X4TS U2301 ( .A0(n3420), .A1(n3813), .B0(n3420), .B1(n3722), .C0(n3813), .C1(n3722), .Y(n3426) );
AOI222X4TS U2302 ( .A0(DmP_mant_SFG_SWR[7]), .A1(DMP_SFG[5]), .B0(
DmP_mant_SFG_SWR[7]), .B1(n3357), .C0(DMP_SFG[5]), .C1(n3357), .Y(
n3166) );
AOI222X4TS U2303 ( .A0(n3350), .A1(n3809), .B0(n3350), .B1(n3718), .C0(n3809), .C1(n3718), .Y(n3357) );
CLKBUFX3TS U2304 ( .A(n3254), .Y(n3299) );
CLKBUFX3TS U2305 ( .A(n3296), .Y(n3303) );
INVX2TS U2306 ( .A(n3629), .Y(n3343) );
CLKINVX3TS U2307 ( .A(n3629), .Y(n3399) );
CLKINVX3TS U2308 ( .A(n3629), .Y(n3661) );
CLKINVX3TS U2309 ( .A(n3629), .Y(n3518) );
CLKBUFX3TS U2310 ( .A(n3913), .Y(n3629) );
CLKBUFX3TS U2311 ( .A(n3227), .Y(n3225) );
CLKBUFX3TS U2312 ( .A(n3137), .Y(n3227) );
OAI211X2TS U2313 ( .A0(n2961), .A1(n2820), .B0(n2819), .C0(n1981), .Y(n3176)
);
OAI21X2TS U2314 ( .A0(n1956), .A1(n2820), .B0(n2765), .Y(n3199) );
OAI21X2TS U2315 ( .A0(Data_array_SWR[51]), .A1(n2946), .B0(n2945), .Y(n2820)
);
AOI22X2TS U2316 ( .A0(intDX_EWSW[27]), .A1(n3861), .B0(intDX_EWSW[26]), .B1(
n3715), .Y(n2182) );
OAI21X2TS U2317 ( .A0(n3778), .A1(n2943), .B0(n2502), .Y(n2596) );
OAI21X2TS U2318 ( .A0(n3705), .A1(n2466), .B0(n2367), .Y(n2414) );
OAI21X2TS U2319 ( .A0(n3759), .A1(n2852), .B0(n2375), .Y(n2415) );
CLKBUFX3TS U2320 ( .A(n2851), .Y(n2852) );
OAI21X2TS U2321 ( .A0(n3761), .A1(n2851), .B0(n2383), .Y(n2888) );
OAI21X2TS U2322 ( .A0(n3822), .A1(n3317), .B0(n2330), .Y(n2620) );
OAI21X2TS U2323 ( .A0(n3747), .A1(n2585), .B0(n2544), .Y(n2555) );
OAI21X2TS U2324 ( .A0(n3683), .A1(n3317), .B0(n2604), .Y(n2630) );
OAI21X2TS U2325 ( .A0(n3868), .A1(n2564), .B0(n2332), .Y(n2614) );
BUFX4TS U2326 ( .A(clk), .Y(n4006) );
BUFX6TS U2327 ( .A(n2276), .Y(n4019) );
OAI31XLTS U2328 ( .A0(n2697), .A1(n3192), .A2(n2696), .B0(n2695), .Y(n1610)
);
XNOR2X2TS U2329 ( .A(intDY_EWSW[63]), .B(intAS), .Y(n2696) );
INVX2TS U2330 ( .A(n3127), .Y(n2033) );
CLKBUFX2TS U2331 ( .A(n2832), .Y(n2034) );
OR2X1TS U2332 ( .A(shift_value_SHT2_EWR[4]), .B(shift_value_SHT2_EWR[5]),
.Y(n3132) );
INVX2TS U2333 ( .A(n3132), .Y(n2035) );
INVX2TS U2334 ( .A(n3132), .Y(n2036) );
AOI21X2TS U2335 ( .A0(n2036), .A1(n2818), .B0(n1946), .Y(n3204) );
AOI21X2TS U2336 ( .A0(n2035), .A1(n1983), .B0(n2997), .Y(n3211) );
AOI21X2TS U2337 ( .A0(n2036), .A1(n3024), .B0(n2997), .Y(n2975) );
AOI21X2TS U2338 ( .A0(n2035), .A1(n3033), .B0(n2997), .Y(n3214) );
AOI21X2TS U2339 ( .A0(n2036), .A1(n3043), .B0(n2997), .Y(n2977) );
AOI21X2TS U2340 ( .A0(n2035), .A1(n2982), .B0(n2997), .Y(n3217) );
NOR2X4TS U2341 ( .A(n2036), .B(n3852), .Y(n2997) );
INVX2TS U2342 ( .A(n3745), .Y(n2037) );
OAI31X2TS U2343 ( .A0(n2054), .A1(n2053), .A2(n2052), .B0(
Shift_reg_FLAGS_7[0]), .Y(n3327) );
OAI21X4TS U2344 ( .A0(shift_value_SHT2_EWR[4]), .A1(left_right_SHT2), .B0(
n3058), .Y(n3121) );
INVX2TS U2345 ( .A(Shift_reg_FLAGS_7[1]), .Y(n2038) );
INVX2TS U2346 ( .A(n2038), .Y(n2039) );
INVX2TS U2347 ( .A(n2038), .Y(n2040) );
INVX2TS U2348 ( .A(n2038), .Y(n2041) );
INVX2TS U2349 ( .A(n2038), .Y(n2042) );
NOR2XLTS U2350 ( .A(intDY_EWSW[9]), .B(n3849), .Y(n2113) );
NOR2XLTS U2351 ( .A(intDY_EWSW[13]), .B(n3709), .Y(n2122) );
NOR2XLTS U2352 ( .A(intDY_EWSW[29]), .B(n3905), .Y(n2144) );
OAI211XLTS U2353 ( .A0(n2137), .A1(n2136), .B0(n2135), .C0(n2134), .Y(n2138)
);
OAI211XLTS U2354 ( .A0(intDY_EWSW[31]), .A1(n3899), .B0(n2189), .C0(n2186),
.Y(n2140) );
NOR2XLTS U2355 ( .A(intDY_EWSW[57]), .B(n3902), .Y(n2081) );
OAI211XLTS U2356 ( .A0(n2152), .A1(n2151), .B0(n2150), .C0(n2149), .Y(n2157)
);
OAI21XLTS U2357 ( .A0(n3894), .A1(n2666), .B0(n2662), .Y(n2663) );
OAI21XLTS U2358 ( .A0(Raw_mant_NRM_SWR[4]), .A1(n3829), .B0(n3711), .Y(n2288) );
OAI21XLTS U2359 ( .A0(n3080), .A1(n3102), .B0(n1971), .Y(n3068) );
OAI21XLTS U2360 ( .A0(n3123), .A1(n3079), .B0(n3121), .Y(n3064) );
OAI21XLTS U2361 ( .A0(Raw_mant_NRM_SWR[8]), .A1(Raw_mant_NRM_SWR[7]), .B0(
n2476), .Y(n2314) );
OAI21XLTS U2362 ( .A0(DmP_mant_SFG_SWR[8]), .A1(n3781), .B0(n3363), .Y(n3167) );
OAI21XLTS U2363 ( .A0(DmP_EXP_EWSW[53]), .A1(n3893), .B0(n3260), .Y(n3258)
);
OAI211XLTS U2364 ( .A0(n2402), .A1(n3827), .B0(n2478), .C0(n2401), .Y(n2403)
);
OAI21XLTS U2365 ( .A0(DmP_mant_SFG_SWR[30]), .A1(n3786), .B0(n3500), .Y(
n3496) );
OAI21XLTS U2366 ( .A0(DmP_mant_SFG_SWR[46]), .A1(n3793), .B0(n3606), .Y(
n3602) );
OAI21XLTS U2367 ( .A0(n2823), .A1(n1956), .B0(n3134), .Y(n2824) );
OAI21XLTS U2368 ( .A0(DmP_mant_SFG_SWR[42]), .A1(n3791), .B0(n3577), .Y(
n3573) );
OAI21XLTS U2369 ( .A0(DmP_mant_SFG_SWR[24]), .A1(n3783), .B0(n3462), .Y(
n3458) );
OAI21XLTS U2370 ( .A0(DmP_mant_SFG_SWR[4]), .A1(n3717), .B0(n3339), .Y(n3340) );
OAI21XLTS U2371 ( .A0(DmP_mant_SFG_SWR[26]), .A1(n3784), .B0(n3475), .Y(
n3471) );
OAI211XLTS U2372 ( .A0(n1934), .A1(n3712), .B0(n2491), .C0(n2490), .Y(n2492)
);
OAI21XLTS U2373 ( .A0(n1970), .A1(n3209), .B0(n2437), .Y(n1103) );
OAI211XLTS U2374 ( .A0(n1904), .A1(n2576), .B0(n2572), .C0(n2571), .Y(n1730)
);
OAI211XLTS U2375 ( .A0(n1925), .A1(n2626), .B0(n2335), .C0(n2334), .Y(n1713)
);
OAI211XLTS U2376 ( .A0(n2378), .A1(n2626), .B0(n2377), .C0(n2376), .Y(n1706)
);
OAI21XLTS U2377 ( .A0(n3779), .A1(n3192), .B0(n2419), .Y(n1294) );
OAI21XLTS U2378 ( .A0(n3891), .A1(n2704), .B0(n2703), .Y(n1308) );
OAI21XLTS U2379 ( .A0(n3689), .A1(n2836), .B0(n2799), .Y(n1338) );
OAI21XLTS U2380 ( .A0(n3796), .A1(n2911), .B0(n2721), .Y(n1368) );
OAI21XLTS U2381 ( .A0(n3713), .A1(n2911), .B0(n2688), .Y(n1398) );
OAI21XLTS U2382 ( .A0(n3662), .A1(n2934), .B0(n2933), .Y(n1632) );
OAI21XLTS U2383 ( .A0(n3899), .A1(n2929), .B0(n2928), .Y(n1644) );
OAI21XLTS U2384 ( .A0(n3710), .A1(n2917), .B0(n2881), .Y(n1657) );
OAI21XLTS U2385 ( .A0(n3714), .A1(n2925), .B0(n2699), .Y(n1670) );
OAI21XLTS U2386 ( .A0(n2979), .A1(n1951), .B0(n2751), .Y(n1159) );
OAI21XLTS U2387 ( .A0(n1987), .A1(n2832), .B0(n2831), .Y(n1200) );
OAI21XLTS U2388 ( .A0(n2406), .A1(n3852), .B0(n2943), .Y(n1754) );
CLKBUFX3TS U2389 ( .A(n4086), .Y(n2045) );
CLKBUFX3TS U2390 ( .A(n4086), .Y(n4001) );
BUFX3TS U2391 ( .A(n4001), .Y(n3944) );
CLKBUFX3TS U2392 ( .A(n2045), .Y(n2044) );
BUFX3TS U2393 ( .A(n3930), .Y(n3943) );
BUFX3TS U2394 ( .A(n4003), .Y(n3942) );
BUFX3TS U2395 ( .A(n4003), .Y(n3945) );
BUFX3TS U2396 ( .A(n2045), .Y(n3967) );
BUFX3TS U2397 ( .A(n2046), .Y(n3966) );
BUFX3TS U2398 ( .A(n3998), .Y(n3965) );
BUFX3TS U2399 ( .A(n4001), .Y(n3941) );
BUFX3TS U2400 ( .A(n3929), .Y(n3993) );
BUFX3TS U2401 ( .A(n3946), .Y(n3990) );
BUFX3TS U2402 ( .A(n3955), .Y(n3987) );
CLKBUFX3TS U2403 ( .A(n2045), .Y(n2046) );
BUFX3TS U2404 ( .A(n2046), .Y(n3988) );
BUFX3TS U2405 ( .A(n3931), .Y(n3994) );
BUFX3TS U2406 ( .A(n3933), .Y(n3991) );
BUFX3TS U2407 ( .A(n3998), .Y(n3982) );
BUFX3TS U2408 ( .A(n3936), .Y(n3996) );
BUFX3TS U2409 ( .A(n2045), .Y(n3932) );
BUFX3TS U2410 ( .A(n4000), .Y(n3995) );
BUFX3TS U2411 ( .A(n2047), .Y(n3923) );
BUFX3TS U2412 ( .A(n3929), .Y(n3984) );
BUFX3TS U2413 ( .A(n3930), .Y(n3985) );
BUFX3TS U2414 ( .A(n4001), .Y(n3986) );
BUFX3TS U2415 ( .A(n3946), .Y(n3983) );
BUFX3TS U2416 ( .A(n2044), .Y(n3931) );
BUFX3TS U2417 ( .A(n2043), .Y(n3992) );
BUFX3TS U2418 ( .A(n4002), .Y(n3958) );
BUFX3TS U2419 ( .A(n4002), .Y(n3957) );
BUFX3TS U2420 ( .A(n4002), .Y(n3968) );
BUFX3TS U2421 ( .A(n4002), .Y(n3956) );
BUFX3TS U2422 ( .A(n2044), .Y(n3955) );
BUFX3TS U2423 ( .A(n2046), .Y(n3954) );
BUFX3TS U2424 ( .A(n4003), .Y(n3953) );
BUFX3TS U2425 ( .A(n3999), .Y(n3969) );
BUFX3TS U2426 ( .A(n2047), .Y(n3977) );
BUFX3TS U2427 ( .A(n2047), .Y(n3950) );
BUFX3TS U2428 ( .A(n2046), .Y(n3949) );
BUFX3TS U2429 ( .A(n2046), .Y(n3970) );
BUFX3TS U2430 ( .A(n2044), .Y(n3933) );
BUFX3TS U2431 ( .A(n3955), .Y(n3934) );
BUFX3TS U2432 ( .A(n4001), .Y(n3976) );
BUFX3TS U2433 ( .A(n4003), .Y(n3972) );
BUFX3TS U2434 ( .A(n4001), .Y(n3975) );
BUFX3TS U2435 ( .A(n2044), .Y(n3936) );
BUFX3TS U2436 ( .A(n2045), .Y(n3937) );
BUFX3TS U2437 ( .A(n4001), .Y(n3973) );
BUFX3TS U2438 ( .A(n4003), .Y(n3938) );
BUFX3TS U2439 ( .A(n4003), .Y(n3939) );
BUFX3TS U2440 ( .A(n4001), .Y(n3974) );
BUFX3TS U2441 ( .A(n4000), .Y(n3997) );
BUFX3TS U2442 ( .A(n4001), .Y(n3981) );
BUFX3TS U2443 ( .A(n2045), .Y(n3927) );
BUFX3TS U2444 ( .A(n2044), .Y(n3929) );
BUFX3TS U2445 ( .A(n2047), .Y(n3926) );
BUFX3TS U2446 ( .A(n2045), .Y(n3925) );
BUFX3TS U2447 ( .A(n2045), .Y(n3928) );
BUFX3TS U2448 ( .A(n2047), .Y(n3924) );
BUFX3TS U2449 ( .A(n2044), .Y(n3930) );
BUFX3TS U2450 ( .A(n4002), .Y(n3963) );
BUFX3TS U2451 ( .A(n4002), .Y(n3960) );
BUFX3TS U2452 ( .A(n2043), .Y(n3961) );
BUFX3TS U2453 ( .A(n2046), .Y(n3962) );
BUFX3TS U2454 ( .A(n2044), .Y(n3946) );
BUFX3TS U2455 ( .A(n2046), .Y(n3948) );
BUFX3TS U2456 ( .A(n2046), .Y(n3947) );
BUFX3TS U2457 ( .A(n4001), .Y(n3978) );
BUFX3TS U2458 ( .A(n2046), .Y(n3999) );
BUFX3TS U2459 ( .A(n2045), .Y(n3935) );
BUFX3TS U2460 ( .A(n4003), .Y(n3940) );
BUFX3TS U2461 ( .A(n2046), .Y(n3951) );
BUFX3TS U2462 ( .A(n2047), .Y(n3922) );
NOR4X1TS U2463 ( .A(exp_rslt_NRM2_EW1[0]), .B(exp_rslt_NRM2_EW1[3]), .C(
exp_rslt_NRM2_EW1[5]), .D(exp_rslt_NRM2_EW1[1]), .Y(n2050) );
NOR3XLTS U2464 ( .A(exp_rslt_NRM2_EW1[2]), .B(exp_rslt_NRM2_EW1[10]), .C(
exp_rslt_NRM2_EW1[9]), .Y(n2049) );
NOR4X1TS U2465 ( .A(exp_rslt_NRM2_EW1[7]), .B(exp_rslt_NRM2_EW1[6]), .C(
exp_rslt_NRM2_EW1[8]), .D(exp_rslt_NRM2_EW1[4]), .Y(n2048) );
XOR2X1TS U2466 ( .A(DP_OP_15J180_122_2221_n1), .B(ADD_OVRFLW_NRM2), .Y(n2053) );
AND4X1TS U2467 ( .A(n2050), .B(n2049), .C(n2048), .D(n2053), .Y(n3326) );
NAND4XLTS U2468 ( .A(exp_rslt_NRM2_EW1[0]), .B(exp_rslt_NRM2_EW1[3]), .C(
exp_rslt_NRM2_EW1[5]), .D(exp_rslt_NRM2_EW1[1]), .Y(n2054) );
AND4X1TS U2469 ( .A(exp_rslt_NRM2_EW1[7]), .B(exp_rslt_NRM2_EW1[6]), .C(
exp_rslt_NRM2_EW1[8]), .D(exp_rslt_NRM2_EW1[4]), .Y(n2051) );
NAND4XLTS U2470 ( .A(exp_rslt_NRM2_EW1[2]), .B(exp_rslt_NRM2_EW1[10]), .C(
exp_rslt_NRM2_EW1[9]), .D(n2051), .Y(n2052) );
NOR2XLTS U2471 ( .A(n3326), .B(n3327), .Y(n2055) );
INVX2TS U2472 ( .A(n2055), .Y(n3318) );
INVX2TS U2473 ( .A(n3318), .Y(n3130) );
NAND2X2TS U2474 ( .A(shift_value_SHT2_EWR[2]), .B(shift_value_SHT2_EWR[3]),
.Y(n2949) );
INVX2TS U2475 ( .A(n2949), .Y(n3017) );
NAND2X2TS U2476 ( .A(n3910), .B(shift_value_SHT2_EWR[2]), .Y(n2666) );
INVX2TS U2477 ( .A(n2666), .Y(n2642) );
CLKBUFX2TS U2478 ( .A(n2642), .Y(n3016) );
OR2X2TS U2479 ( .A(shift_value_SHT2_EWR[2]), .B(n3910), .Y(n2803) );
INVX2TS U2480 ( .A(n2946), .Y(n3014) );
AOI22X1TS U2481 ( .A0(Data_array_SWR[41]), .A1(n3015), .B0(
Data_array_SWR[33]), .B1(n2957), .Y(n2056) );
OAI2BB1X1TS U2482 ( .A0N(Data_array_SWR[37]), .A1N(n2642), .B0(n2056), .Y(
n2057) );
AOI21X2TS U2483 ( .A0(Data_array_SWR[45]), .A1(n3007), .B0(n2057), .Y(n3106)
);
NOR2X4TS U2484 ( .A(n1958), .B(n1956), .Y(n3111) );
INVX2TS U2485 ( .A(n3111), .Y(n3127) );
AOI22X1TS U2486 ( .A0(Data_array_SWR[29]), .A1(n2947), .B0(
Data_array_SWR[21]), .B1(n3014), .Y(n2060) );
CLKBUFX2TS U2487 ( .A(n3017), .Y(n2058) );
AOI22X1TS U2488 ( .A0(Data_array_SWR[33]), .A1(n2058), .B0(
Data_array_SWR[25]), .B1(n2642), .Y(n2059) );
NAND2X1TS U2489 ( .A(n2060), .B(n2059), .Y(n3104) );
NAND2X2TS U2490 ( .A(n1959), .B(n1958), .Y(n3122) );
INVX2TS U2491 ( .A(n3134), .Y(n3058) );
NOR2X4TS U2492 ( .A(left_right_SHT2), .B(n1948), .Y(n3119) );
AOI22X1TS U2493 ( .A0(Data_array_SWR[45]), .A1(n3015), .B0(
Data_array_SWR[37]), .B1(n2804), .Y(n2062) );
AOI22X1TS U2494 ( .A0(Data_array_SWR[49]), .A1(n2058), .B0(
Data_array_SWR[41]), .B1(n2642), .Y(n2061) );
NAND2X2TS U2495 ( .A(n2062), .B(n2061), .Y(n3099) );
NOR2X4TS U2496 ( .A(n1958), .B(n1948), .Y(n3117) );
AOI22X1TS U2497 ( .A0(Data_array_SWR[49]), .A1(n2954), .B0(
Data_array_SWR[53]), .B1(n2642), .Y(n2063) );
NAND2X2TS U2498 ( .A(n2063), .B(n2955), .Y(n3100) );
AOI22X1TS U2499 ( .A0(n3119), .A1(n3099), .B0(n3117), .B1(n3100), .Y(n2064)
);
OAI211XLTS U2500 ( .A0(n3102), .A1(n3122), .B0(n3121), .C0(n2064), .Y(n2065)
);
AOI21X1TS U2501 ( .A0(n1954), .A1(n3104), .B0(n2065), .Y(n2066) );
OAI21X1TS U2502 ( .A0(n3106), .A1(n3127), .B0(n2066), .Y(n3153) );
AO22XLTS U2503 ( .A0(n3130), .A1(n3153), .B0(final_result_ieee[19]), .B1(
n3745), .Y(n1197) );
INVX2TS U2504 ( .A(n3854), .Y(n3295) );
INVX2TS U2505 ( .A(n2039), .Y(n2345) );
NOR2XLTS U2506 ( .A(ADD_OVRFLW_NRM), .B(n2345), .Y(n2067) );
INVX2TS U2507 ( .A(n2067), .Y(n2851) );
OAI21XLTS U2508 ( .A0(n2406), .A1(n3746), .B0(n2852), .Y(n1753) );
INVX2TS U2509 ( .A(n3912), .Y(n3248) );
INVX2TS U2510 ( .A(Shift_reg_FLAGS_7_5), .Y(n3297) );
AO22XLTS U2511 ( .A0(n3248), .A1(DmP_EXP_EWSW[32]), .B0(n3301), .B1(
DmP_mant_SHT1_SW[32]), .Y(n1333) );
AO22XLTS U2512 ( .A0(n3248), .A1(DmP_EXP_EWSW[39]), .B0(n3302), .B1(
DmP_mant_SHT1_SW[39]), .Y(n1319) );
AO22XLTS U2513 ( .A0(n3248), .A1(DmP_EXP_EWSW[40]), .B0(n3301), .B1(
DmP_mant_SHT1_SW[40]), .Y(n1317) );
AO22XLTS U2514 ( .A0(n3248), .A1(DmP_EXP_EWSW[31]), .B0(n3302), .B1(
DmP_mant_SHT1_SW[31]), .Y(n1335) );
AOI2BB2X1TS U2515 ( .B0(intDX_EWSW[59]), .B1(n3671), .A0N(n3853), .A1N(
intDY_EWSW[58]), .Y(n2084) );
NAND2X1TS U2516 ( .A(n3898), .B(intDX_EWSW[61]), .Y(n2080) );
NOR2X1TS U2517 ( .A(intDY_EWSW[62]), .B(n3742), .Y(n2088) );
INVX2TS U2518 ( .A(n2088), .Y(n2068) );
OAI211X1TS U2519 ( .A0(n3799), .A1(intDY_EWSW[60]), .B0(n2080), .C0(n2068),
.Y(n2085) );
INVX2TS U2520 ( .A(n2085), .Y(n2069) );
OAI211XLTS U2521 ( .A0(intDY_EWSW[56]), .A1(n3780), .B0(n2084), .C0(n2069),
.Y(n2070) );
AOI21X1TS U2522 ( .A0(intDX_EWSW[57]), .A1(n3802), .B0(n2070), .Y(n2163) );
AOI22X1TS U2523 ( .A0(intDX_EWSW[51]), .A1(n3664), .B0(intDX_EWSW[50]), .B1(
n3876), .Y(n2155) );
NOR2X1TS U2524 ( .A(intDY_EWSW[49]), .B(n3798), .Y(n2154) );
NAND2X1TS U2525 ( .A(intDY_EWSW[49]), .B(n3798), .Y(n2237) );
OAI31X1TS U2526 ( .A0(intDX_EWSW[48]), .A1(n2154), .A2(n3824), .B0(n2237),
.Y(n2072) );
NAND2X1TS U2527 ( .A(intDY_EWSW[50]), .B(n3886), .Y(n2234) );
AOI222X1TS U2528 ( .A0(intDX_EWSW[51]), .A1(n3664), .B0(intDX_EWSW[51]),
.B1(n2234), .C0(n3664), .C1(n2234), .Y(n2071) );
AOI21X1TS U2529 ( .A0(n2155), .A1(n2072), .B0(n2071), .Y(n2079) );
AOI22X1TS U2530 ( .A0(intDX_EWSW[54]), .A1(n3764), .B0(intDX_EWSW[55]), .B1(
n3666), .Y(n2077) );
NAND2X1TS U2531 ( .A(intDX_EWSW[53]), .B(n3667), .Y(n2073) );
OAI211X1TS U2532 ( .A0(intDY_EWSW[52]), .A1(n3779), .B0(n2077), .C0(n2073),
.Y(n2153) );
INVX2TS U2533 ( .A(n2073), .Y(n2074) );
NAND2X1TS U2534 ( .A(intDY_EWSW[52]), .B(n3779), .Y(n2244) );
OAI22X1TS U2535 ( .A0(intDX_EWSW[53]), .A1(n3667), .B0(n2074), .B1(n2244),
.Y(n2076) );
NOR2X1TS U2536 ( .A(intDX_EWSW[54]), .B(n3764), .Y(n2241) );
NAND2X1TS U2537 ( .A(intDX_EWSW[55]), .B(n3666), .Y(n2075) );
AOI22X1TS U2538 ( .A0(n2077), .A1(n2076), .B0(n2241), .B1(n2075), .Y(n2078)
);
NAND2X1TS U2539 ( .A(intDY_EWSW[55]), .B(n3737), .Y(n2242) );
OAI211XLTS U2540 ( .A0(n2079), .A1(n2153), .B0(n2078), .C0(n2242), .Y(n2162)
);
OAI2BB2X1TS U2541 ( .B0(intDX_EWSW[61]), .B1(n3898), .A0N(n3742), .A1N(
intDY_EWSW[62]), .Y(n2175) );
AOI31XLTS U2542 ( .A0(intDY_EWSW[60]), .A1(n2080), .A2(n3799), .B0(n2175),
.Y(n2087) );
NAND2X1TS U2543 ( .A(intDY_EWSW[56]), .B(n3780), .Y(n2236) );
OAI22X1TS U2544 ( .A0(intDX_EWSW[57]), .A1(n3802), .B0(n2081), .B1(n2236),
.Y(n2083) );
NAND2X1TS U2545 ( .A(intDY_EWSW[58]), .B(n3853), .Y(n2251) );
AOI222X1TS U2546 ( .A0(intDX_EWSW[59]), .A1(n3671), .B0(intDX_EWSW[59]),
.B1(n2251), .C0(n3671), .C1(n2251), .Y(n2082) );
AOI21X1TS U2547 ( .A0(n2084), .A1(n2083), .B0(n2082), .Y(n2086) );
OAI22X1TS U2548 ( .A0(n2088), .A1(n2087), .B0(n2086), .B1(n2085), .Y(n2161)
);
AOI222X1TS U2549 ( .A0(intDY_EWSW[47]), .A1(n2246), .B0(intDY_EWSW[47]),
.B1(n3840), .C0(n2246), .C1(n3840), .Y(n2159) );
AOI222X1TS U2550 ( .A0(n3672), .A1(intDX_EWSW[41]), .B0(n3662), .B1(
intDX_EWSW[43]), .C0(n3897), .C1(intDX_EWSW[42]), .Y(n2103) );
OAI22X1TS U2551 ( .A0(intDX_EWSW[40]), .A1(n3665), .B0(intDX_EWSW[41]), .B1(
n3672), .Y(n2176) );
NAND2X1TS U2552 ( .A(intDY_EWSW[42]), .B(n3885), .Y(n2245) );
AOI222X1TS U2553 ( .A0(intDX_EWSW[43]), .A1(n3662), .B0(intDX_EWSW[43]),
.B1(n2245), .C0(n3662), .C1(n2245), .Y(n2089) );
AOI21X1TS U2554 ( .A0(n2103), .A1(n2176), .B0(n2089), .Y(n2094) );
AOI22X1TS U2555 ( .A0(intDX_EWSW[47]), .A1(n3800), .B0(intDX_EWSW[46]), .B1(
n3668), .Y(n2091) );
NAND2X1TS U2556 ( .A(intDX_EWSW[45]), .B(n3891), .Y(n2090) );
OAI211X1TS U2557 ( .A0(intDY_EWSW[44]), .A1(n3901), .B0(n2091), .C0(n2090),
.Y(n2104) );
NOR2X1TS U2558 ( .A(intDX_EWSW[44]), .B(n3909), .Y(n2248) );
AOI22X1TS U2559 ( .A0(intDY_EWSW[45]), .A1(n3807), .B0(n2248), .B1(n2090),
.Y(n2093) );
INVX2TS U2560 ( .A(n2091), .Y(n2092) );
OAI22X1TS U2561 ( .A0(n2094), .A1(n2104), .B0(n2093), .B1(n2092), .Y(n2106)
);
NOR2X1TS U2562 ( .A(intDX_EWSW[39]), .B(n3736), .Y(n2205) );
NOR2XLTS U2563 ( .A(intDY_EWSW[39]), .B(n3906), .Y(n2102) );
NAND2X1TS U2564 ( .A(intDX_EWSW[38]), .B(n3890), .Y(n2098) );
NOR2XLTS U2565 ( .A(intDY_EWSW[37]), .B(n3850), .Y(n2095) );
NAND2X1TS U2566 ( .A(intDY_EWSW[37]), .B(n3850), .Y(n2249) );
OAI31X1TS U2567 ( .A0(intDX_EWSW[36]), .A1(n2095), .A2(n3836), .B0(n2249),
.Y(n2096) );
AOI22X1TS U2568 ( .A0(intDY_EWSW[38]), .A1(n3806), .B0(n2098), .B1(n2096),
.Y(n2101) );
NAND2X1TS U2569 ( .A(intDY_EWSW[34]), .B(n3884), .Y(n2201) );
NOR2X1TS U2570 ( .A(intDX_EWSW[33]), .B(n3678), .Y(n2197) );
NOR2X1TS U2571 ( .A(intDX_EWSW[32]), .B(n3748), .Y(n2203) );
OAI32X1TS U2572 ( .A0(n2097), .A1(n2197), .A2(n2203), .B0(n2228), .B1(n2097),
.Y(n2100) );
AOI22X1TS U2573 ( .A0(intDX_EWSW[37]), .A1(n3862), .B0(intDX_EWSW[39]), .B1(
n3736), .Y(n2099) );
OAI22X1TS U2574 ( .A0(n2102), .A1(n2101), .B0(n2100), .B1(n2232), .Y(n2105)
);
NAND2BXLTS U2575 ( .AN(n2104), .B(n2103), .Y(n2233) );
AOI21X1TS U2576 ( .A0(intDX_EWSW[40]), .A1(n3665), .B0(n2233), .Y(n2150) );
OAI32X1TS U2577 ( .A0(n2106), .A1(n2205), .A2(n2105), .B0(n2150), .B1(n2106),
.Y(n2158) );
AOI222X1TS U2578 ( .A0(intDY_EWSW[27]), .A1(n2198), .B0(intDY_EWSW[27]),
.B1(n3706), .C0(n2198), .C1(n3706), .Y(n2143) );
AOI22X1TS U2579 ( .A0(intDX_EWSW[24]), .A1(n3763), .B0(intDX_EWSW[25]), .B1(
n3687), .Y(n2188) );
OAI22X1TS U2580 ( .A0(intDY_EWSW[23]), .A1(n3680), .B0(intDY_EWSW[22]), .B1(
n3873), .Y(n2137) );
AOI222X1TS U2581 ( .A0(intDY_EWSW[21]), .A1(n2185), .B0(intDY_EWSW[21]),
.B1(n3757), .C0(n2185), .C1(n3757), .Y(n2136) );
AOI222X1TS U2582 ( .A0(intDY_EWSW[23]), .A1(n2225), .B0(intDY_EWSW[23]),
.B1(n3680), .C0(n2225), .C1(n3680), .Y(n2135) );
NOR2X1TS U2583 ( .A(intDY_EWSW[17]), .B(n3797), .Y(n2125) );
NAND2X1TS U2584 ( .A(intDY_EWSW[16]), .B(n3834), .Y(n2170) );
NAND2X1TS U2585 ( .A(intDY_EWSW[17]), .B(n3797), .Y(n2169) );
OAI32X1TS U2586 ( .A0(n2126), .A1(n2125), .A2(n2170), .B0(n2169), .B1(n2126),
.Y(n2133) );
NOR2X1TS U2587 ( .A(intDY_EWSW[15]), .B(n3796), .Y(n2121) );
OAI22X1TS U2588 ( .A0(intDY_EWSW[13]), .A1(n3709), .B0(intDY_EWSW[14]), .B1(
n3872), .Y(n2174) );
AOI211X1TS U2589 ( .A0(intDX_EWSW[12]), .A1(n3833), .B0(n2121), .C0(n2174),
.Y(n2120) );
NAND2X1TS U2590 ( .A(n3753), .B(intDX_EWSW[11]), .Y(n2118) );
INVX2TS U2591 ( .A(n2118), .Y(n2215) );
AOI22X1TS U2592 ( .A0(intDY_EWSW[4]), .A1(n3859), .B0(intDY_EWSW[5]), .B1(
n3714), .Y(n2217) );
NAND2X1TS U2593 ( .A(intDX_EWSW[3]), .B(n3734), .Y(n2108) );
NAND2X1TS U2594 ( .A(intDX_EWSW[4]), .B(n3887), .Y(n2191) );
OAI22X1TS U2595 ( .A0(intDX_EWSW[3]), .A1(n3734), .B0(intDX_EWSW[2]), .B1(
n3874), .Y(n2178) );
NOR2X1TS U2596 ( .A(intDY_EWSW[0]), .B(n3713), .Y(n2194) );
NAND2X1TS U2597 ( .A(intDY_EWSW[1]), .B(n3795), .Y(n2206) );
NOR2X1TS U2598 ( .A(intDY_EWSW[1]), .B(n3795), .Y(n2209) );
OAI22X1TS U2599 ( .A0(intDY_EWSW[2]), .A1(n3744), .B0(intDY_EWSW[3]), .B1(
n3870), .Y(n2173) );
AOI211X1TS U2600 ( .A0(n2194), .A1(n2206), .B0(n2209), .C0(n2173), .Y(n2107)
);
AOI32X1TS U2601 ( .A0(n2108), .A1(n2191), .A2(n2178), .B0(n2107), .B1(n2191),
.Y(n2109) );
NOR2X1TS U2602 ( .A(intDY_EWSW[5]), .B(n3714), .Y(n2220) );
OAI22X1TS U2603 ( .A0(intDY_EWSW[6]), .A1(n3701), .B0(intDY_EWSW[7]), .B1(
n3871), .Y(n2177) );
AOI211XLTS U2604 ( .A0(n2217), .A1(n2109), .B0(n2220), .C0(n2177), .Y(n2111)
);
NAND2X1TS U2605 ( .A(intDY_EWSW[6]), .B(n3701), .Y(n2221) );
AOI222X1TS U2606 ( .A0(intDX_EWSW[7]), .A1(n3758), .B0(intDX_EWSW[7]), .B1(
n2221), .C0(n3758), .C1(n2221), .Y(n2110) );
AOI22X1TS U2607 ( .A0(intDX_EWSW[10]), .A1(n3728), .B0(intDX_EWSW[9]), .B1(
n3875), .Y(n2181) );
NAND2X1TS U2608 ( .A(intDX_EWSW[8]), .B(n3888), .Y(n2192) );
OAI211XLTS U2609 ( .A0(n2111), .A1(n2110), .B0(n2181), .C0(n2192), .Y(n2112)
);
OAI22X1TS U2610 ( .A0(intDX_EWSW[11]), .A1(n3753), .B0(n2215), .B1(n2112),
.Y(n2119) );
INVX2TS U2611 ( .A(n2120), .Y(n2116) );
NAND2X1TS U2612 ( .A(intDY_EWSW[8]), .B(n3881), .Y(n2212) );
NAND2X1TS U2613 ( .A(intDY_EWSW[9]), .B(n3849), .Y(n2211) );
OAI32X1TS U2614 ( .A0(n2116), .A1(n2113), .A2(n2212), .B0(n2211), .B1(n2116),
.Y(n2114) );
OAI21XLTS U2615 ( .A0(intDY_EWSW[10]), .A1(n3823), .B0(n2114), .Y(n2115) );
OAI31X1TS U2616 ( .A0(intDX_EWSW[10]), .A1(n2116), .A2(n3728), .B0(n2115),
.Y(n2117) );
AOI22X1TS U2617 ( .A0(n2120), .A1(n2119), .B0(n2118), .B1(n2117), .Y(n2129)
);
NAND2X1TS U2618 ( .A(intDY_EWSW[15]), .B(n3796), .Y(n2210) );
NAND2X1TS U2619 ( .A(intDX_EWSW[14]), .B(n3851), .Y(n2124) );
INVX2TS U2620 ( .A(n2121), .Y(n2213) );
NAND2X1TS U2621 ( .A(intDY_EWSW[12]), .B(n3882), .Y(n2193) );
OAI22X1TS U2622 ( .A0(intDX_EWSW[13]), .A1(n3863), .B0(n2122), .B1(n2193),
.Y(n2123) );
NOR2X1TS U2623 ( .A(intDX_EWSW[14]), .B(n3851), .Y(n2196) );
AOI32X1TS U2624 ( .A0(n2124), .A1(n2213), .A2(n2123), .B0(n2196), .B1(n2213),
.Y(n2128) );
INVX2TS U2625 ( .A(n2190), .Y(n2127) );
AOI31XLTS U2626 ( .A0(n2129), .A1(n2210), .A2(n2128), .B0(n2127), .Y(n2132)
);
NAND2X1TS U2627 ( .A(intDY_EWSW[18]), .B(n3710), .Y(n2222) );
AOI222X1TS U2628 ( .A0(intDX_EWSW[19]), .A1(n3835), .B0(intDX_EWSW[19]),
.B1(n2222), .C0(n3835), .C1(n2222), .Y(n2131) );
NOR2XLTS U2629 ( .A(intDY_EWSW[20]), .B(n3904), .Y(n2130) );
AOI211X1TS U2630 ( .A0(intDX_EWSW[21]), .A1(n3880), .B0(n2130), .C0(n2137),
.Y(n2229) );
OAI31X1TS U2631 ( .A0(n2133), .A1(n2132), .A2(n2131), .B0(n2229), .Y(n2134)
);
NAND3XLTS U2632 ( .A(n2182), .B(n2188), .C(n2138), .Y(n2142) );
NOR2X1TS U2633 ( .A(intDX_EWSW[24]), .B(n3763), .Y(n2200) );
NAND2X1TS U2634 ( .A(intDX_EWSW[25]), .B(n3687), .Y(n2139) );
NOR2X1TS U2635 ( .A(intDX_EWSW[25]), .B(n3687), .Y(n2199) );
AOI32X1TS U2636 ( .A0(n2200), .A1(n2182), .A2(n2139), .B0(n2199), .B1(n2182),
.Y(n2141) );
AOI22X1TS U2637 ( .A0(intDX_EWSW[29]), .A1(n3752), .B0(intDX_EWSW[30]), .B1(
n3689), .Y(n2189) );
NAND2X1TS U2638 ( .A(intDX_EWSW[28]), .B(n3889), .Y(n2186) );
AOI31XLTS U2639 ( .A0(n2143), .A1(n2142), .A2(n2141), .B0(n2140), .Y(n2152)
);
NAND2X1TS U2640 ( .A(intDX_EWSW[30]), .B(n3689), .Y(n2146) );
NAND2X1TS U2641 ( .A(intDY_EWSW[28]), .B(n3883), .Y(n2216) );
OAI22X1TS U2642 ( .A0(intDX_EWSW[29]), .A1(n3752), .B0(n2144), .B1(n2216),
.Y(n2145) );
AOI22X1TS U2643 ( .A0(intDY_EWSW[30]), .A1(n3860), .B0(n2146), .B1(n2145),
.Y(n2147) );
AOI222X1TS U2644 ( .A0(intDX_EWSW[31]), .A1(n2147), .B0(intDX_EWSW[31]),
.B1(n3681), .C0(n2147), .C1(n3681), .Y(n2151) );
INVX2TS U2645 ( .A(n2228), .Y(n2148) );
OAI21XLTS U2646 ( .A0(intDY_EWSW[48]), .A1(n3839), .B0(n2260), .Y(n2156) );
AOI31XLTS U2647 ( .A0(n2159), .A1(n2158), .A2(n2157), .B0(n2156), .Y(n2160)
);
AOI211X1TS U2648 ( .A0(n2163), .A1(n2162), .B0(n2161), .C0(n2160), .Y(n2164)
);
NAND2X2TS U2649 ( .A(n2164), .B(Shift_reg_FLAGS_7_6), .Y(n2938) );
INVX2TS U2650 ( .A(n2938), .Y(n2909) );
CLKBUFX2TS U2651 ( .A(n3679), .Y(n2868) );
NOR2XLTS U2652 ( .A(n2164), .B(n2868), .Y(n2165) );
INVX2TS U2653 ( .A(n2165), .Y(n2934) );
CLKBUFX2TS U2654 ( .A(n2868), .Y(n2812) );
CLKBUFX2TS U2655 ( .A(n2812), .Y(n2914) );
CLKBUFX3TS U2656 ( .A(n2922), .Y(n2907) );
CLKBUFX3TS U2657 ( .A(n2907), .Y(n2918) );
AOI22X1TS U2658 ( .A0(intDY_EWSW[61]), .A1(n2899), .B0(DMP_EXP_EWSW[61]),
.B1(n2918), .Y(n2166) );
OAI2BB1X1TS U2659 ( .A0N(intDX_EWSW[61]), .A1N(n2856), .B0(n2166), .Y(n1614)
);
CLKBUFX3TS U2660 ( .A(n2934), .Y(n2885) );
CLKBUFX3TS U2661 ( .A(n2885), .Y(n2921) );
INVX2TS U2662 ( .A(n2921), .Y(n2710) );
AOI22X1TS U2663 ( .A0(intDY_EWSW[11]), .A1(n2689), .B0(DMP_EXP_EWSW[11]),
.B1(n2922), .Y(n2167) );
OAI2BB1X1TS U2664 ( .A0N(intDX_EWSW[11]), .A1N(n2856), .B0(n2167), .Y(n1664)
);
INVX2TS U2665 ( .A(n2696), .Y(n2168) );
CLKBUFX3TS U2666 ( .A(n2914), .Y(n3320) );
AOI221X1TS U2667 ( .A0(n2168), .A1(intDX_EWSW[63]), .B0(n2696), .B1(n3921),
.C0(n3320), .Y(n2988) );
AOI22X1TS U2668 ( .A0(intDX_EWSW[40]), .A1(n3665), .B0(intDX_EWSW[48]), .B1(
n3824), .Y(n2172) );
AOI22X1TS U2669 ( .A0(intDX_EWSW[32]), .A1(n3748), .B0(intDX_EWSW[31]), .B1(
n3681), .Y(n2171) );
NAND4XLTS U2670 ( .A(n2172), .B(n2171), .C(n2170), .D(n2169), .Y(n2184) );
NOR2XLTS U2671 ( .A(n2174), .B(n2173), .Y(n2180) );
NOR4X1TS U2672 ( .A(n2178), .B(n2177), .C(n2176), .D(n2175), .Y(n2179) );
NAND4XLTS U2673 ( .A(n2182), .B(n2181), .C(n2180), .D(n2179), .Y(n2183) );
NOR4BX1TS U2674 ( .AN(n2186), .B(n2185), .C(n2184), .D(n2183), .Y(n2187) );
NAND4XLTS U2675 ( .A(n2190), .B(n2189), .C(n2188), .D(n2187), .Y(n2264) );
NAND4BXLTS U2676 ( .AN(n2194), .B(n2193), .C(n2192), .D(n2191), .Y(n2195) );
AOI211XLTS U2677 ( .A0(intDY_EWSW[13]), .A1(n3709), .B0(n2196), .C0(n2195),
.Y(n2208) );
NOR4X1TS U2678 ( .A(n2200), .B(n2199), .C(n2198), .D(n2197), .Y(n2202) );
NAND3BXLTS U2679 ( .AN(n2203), .B(n2202), .C(n2201), .Y(n2204) );
AOI211XLTS U2680 ( .A0(intDY_EWSW[38]), .A1(n3806), .B0(n2205), .C0(n2204),
.Y(n2207) );
NAND4BXLTS U2681 ( .AN(n2209), .B(n2208), .C(n2207), .D(n2206), .Y(n2263) );
NAND4XLTS U2682 ( .A(n2213), .B(n2212), .C(n2211), .D(n2210), .Y(n2214) );
AOI211XLTS U2683 ( .A0(intDX_EWSW[12]), .A1(n3833), .B0(n2215), .C0(n2214),
.Y(n2224) );
OAI22X1TS U2684 ( .A0(intDX_EWSW[30]), .A1(n3689), .B0(intDX_EWSW[11]), .B1(
n3753), .Y(n2219) );
OAI211XLTS U2685 ( .A0(intDX_EWSW[29]), .A1(n3752), .B0(n2217), .C0(n2216),
.Y(n2218) );
NOR4BX1TS U2686 ( .AN(n2221), .B(n2220), .C(n2219), .D(n2218), .Y(n2223) );
NAND4BXLTS U2687 ( .AN(n2225), .B(n2224), .C(n2223), .D(n2222), .Y(n2262) );
OAI22X1TS U2688 ( .A0(intDX_EWSW[31]), .A1(n3681), .B0(intDX_EWSW[7]), .B1(
n3758), .Y(n2231) );
AOI22X1TS U2689 ( .A0(intDY_EWSW[27]), .A1(n3706), .B0(intDY_EWSW[19]), .B1(
n3801), .Y(n2227) );
AOI22X1TS U2690 ( .A0(intDY_EWSW[21]), .A1(n3757), .B0(intDY_EWSW[23]), .B1(
n3680), .Y(n2226) );
NAND4XLTS U2691 ( .A(n2229), .B(n2228), .C(n2227), .D(n2226), .Y(n2230) );
NOR4X1TS U2692 ( .A(n2233), .B(n2232), .C(n2231), .D(n2230), .Y(n2259) );
OAI2BB1X1TS U2693 ( .A0N(n3799), .A1N(intDY_EWSW[60]), .B0(n2234), .Y(n2240)
);
NAND2X1TS U2694 ( .A(intDY_EWSW[48]), .B(n3839), .Y(n2238) );
NAND2X1TS U2695 ( .A(intDY_EWSW[57]), .B(n3902), .Y(n2235) );
NAND4XLTS U2696 ( .A(n2238), .B(n2237), .C(n2236), .D(n2235), .Y(n2239) );
NOR4BX1TS U2697 ( .AN(n2242), .B(n2241), .C(n2240), .D(n2239), .Y(n2258) );
NAND2X1TS U2698 ( .A(intDY_EWSW[53]), .B(n3879), .Y(n2243) );
NAND4BXLTS U2699 ( .AN(n2246), .B(n2245), .C(n2244), .D(n2243), .Y(n2247) );
AOI211X1TS U2700 ( .A0(intDY_EWSW[45]), .A1(n3807), .B0(n2248), .C0(n2247),
.Y(n2250) );
OAI211XLTS U2701 ( .A0(intDX_EWSW[36]), .A1(n3836), .B0(n2250), .C0(n2249),
.Y(n2256) );
OAI22X1TS U2702 ( .A0(intDX_EWSW[59]), .A1(n3671), .B0(intDX_EWSW[35]), .B1(
n3663), .Y(n2255) );
OAI22X1TS U2703 ( .A0(intDX_EWSW[43]), .A1(n3662), .B0(intDX_EWSW[47]), .B1(
n3800), .Y(n2254) );
AOI22X1TS U2704 ( .A0(intDY_EWSW[10]), .A1(n3823), .B0(intDY_EWSW[0]), .B1(
n3713), .Y(n2252) );
OAI211XLTS U2705 ( .A0(intDX_EWSW[51]), .A1(n3664), .B0(n2252), .C0(n2251),
.Y(n2253) );
NOR4X1TS U2706 ( .A(n2256), .B(n2255), .C(n2254), .D(n2253), .Y(n2257) );
NAND4XLTS U2707 ( .A(n2260), .B(n2259), .C(n2258), .D(n2257), .Y(n2261) );
NOR4X1TS U2708 ( .A(n2264), .B(n2263), .C(n2262), .D(n2261), .Y(n2697) );
AO22XLTS U2709 ( .A0(n2988), .A1(n2697), .B0(ZERO_FLAG_EXP), .B1(n2914), .Y(
n1611) );
INVX2TS U2710 ( .A(n3854), .Y(n3300) );
INVX2TS U2711 ( .A(n4087), .Y(n3313) );
CLKBUFX3TS U2712 ( .A(n3313), .Y(n2981) );
AO22XLTS U2713 ( .A0(n3300), .A1(DMP_SHT1_EWSW[27]), .B0(n2981), .B1(
DMP_SHT2_EWSW[27]), .Y(n1527) );
CLKBUFX2TS U2714 ( .A(clk), .Y(n2269) );
BUFX3TS U2715 ( .A(n4034), .Y(n4031) );
CLKBUFX2TS U2716 ( .A(clk), .Y(n2270) );
BUFX3TS U2717 ( .A(n4076), .Y(n4041) );
BUFX3TS U2718 ( .A(n2268), .Y(n4051) );
CLKBUFX2TS U2719 ( .A(clk), .Y(n2276) );
BUFX3TS U2720 ( .A(n2268), .Y(n4053) );
BUFX3TS U2721 ( .A(n4078), .Y(n4065) );
CLKBUFX2TS U2722 ( .A(clk), .Y(n2275) );
BUFX3TS U2723 ( .A(n4076), .Y(n4012) );
BUFX3TS U2724 ( .A(n4080), .Y(n4023) );
BUFX3TS U2725 ( .A(n4078), .Y(n4060) );
BUFX3TS U2726 ( .A(n2274), .Y(n4071) );
BUFX3TS U2727 ( .A(n4080), .Y(n4022) );
BUFX3TS U2728 ( .A(n2274), .Y(n4069) );
INVX2TS U2729 ( .A(n4087), .Y(n3254) );
BUFX3TS U2730 ( .A(n4086), .Y(n3964) );
BUFX3TS U2731 ( .A(n4086), .Y(n3989) );
BUFX3TS U2732 ( .A(n4086), .Y(n3959) );
BUFX3TS U2733 ( .A(n4086), .Y(n3952) );
BUFX3TS U2734 ( .A(n4086), .Y(n3971) );
BUFX3TS U2735 ( .A(n4086), .Y(n3980) );
BUFX3TS U2736 ( .A(n4086), .Y(n3979) );
BUFX3TS U2737 ( .A(n3999), .Y(n3998) );
NAND2X1TS U2738 ( .A(ADD_OVRFLW_NRM), .B(n2041), .Y(n2277) );
INVX2TS U2739 ( .A(n2277), .Y(n2849) );
CLKBUFX3TS U2740 ( .A(n2345), .Y(n2602) );
AOI22X1TS U2741 ( .A0(Raw_mant_NRM_SWR[36]), .A1(n2603), .B0(
DmP_mant_SHT1_SW[16]), .B1(n2602), .Y(n2278) );
CLKBUFX3TS U2742 ( .A(n2345), .Y(n3322) );
NAND3XLTS U2743 ( .A(n2031), .B(n3761), .C(n3708), .Y(n2279) );
NAND2X1TS U2744 ( .A(n2296), .B(n3677), .Y(n2468) );
NAND2X1TS U2745 ( .A(n2281), .B(n3747), .Y(n2389) );
NOR2X1TS U2746 ( .A(Raw_mant_NRM_SWR[42]), .B(n2389), .Y(n2322) );
INVX2TS U2747 ( .A(n2322), .Y(n2284) );
NOR3X1TS U2748 ( .A(n2284), .B(Raw_mant_NRM_SWR[40]), .C(
Raw_mant_NRM_SWR[39]), .Y(n2301) );
NOR2BX1TS U2749 ( .AN(n2301), .B(Raw_mant_NRM_SWR[41]), .Y(n2451) );
NAND3XLTS U2750 ( .A(n2451), .B(n3685), .C(n3755), .Y(n2307) );
NAND2X1TS U2751 ( .A(n2452), .B(n3699), .Y(n2457) );
NAND2BXLTS U2752 ( .AN(n2457), .B(n3702), .Y(n2291) );
NOR2X1TS U2753 ( .A(n2291), .B(Raw_mant_NRM_SWR[33]), .Y(n2311) );
NOR2BX1TS U2754 ( .AN(n2311), .B(Raw_mant_NRM_SWR[32]), .Y(n2290) );
NAND2X1TS U2755 ( .A(n2290), .B(n3820), .Y(n2467) );
INVX2TS U2756 ( .A(n2467), .Y(n2453) );
NAND2X1TS U2757 ( .A(n3750), .B(n2453), .Y(n2317) );
NOR3X1TS U2758 ( .A(n2317), .B(Raw_mant_NRM_SWR[29]), .C(
Raw_mant_NRM_SWR[28]), .Y(n2289) );
NOR2BX1TS U2759 ( .AN(n2289), .B(Raw_mant_NRM_SWR[27]), .Y(n2472) );
NAND3XLTS U2760 ( .A(n2483), .B(n3826), .C(n3707), .Y(n2280) );
NAND2X1TS U2761 ( .A(n2459), .B(n3754), .Y(n2391) );
NAND3BX1TS U2762 ( .AN(n2391), .B(n3670), .C(n3683), .Y(n2485) );
NAND3XLTS U2763 ( .A(n1984), .B(n3682), .C(n3822), .Y(n2402) );
NOR2X2TS U2764 ( .A(Raw_mant_NRM_SWR[14]), .B(n2402), .Y(n2487) );
NAND2X1TS U2765 ( .A(n2487), .B(n3821), .Y(n2475) );
OAI21XLTS U2766 ( .A0(Raw_mant_NRM_SWR[8]), .A1(n3830), .B0(n3712), .Y(n2283) );
NOR2BX1TS U2767 ( .AN(n2281), .B(n3747), .Y(n2327) );
OAI32X1TS U2768 ( .A0(n2461), .A1(Raw_mant_NRM_SWR[24]), .A2(n3707), .B0(
n3756), .B1(n2461), .Y(n2282) );
NOR3BX2TS U2769 ( .AN(n2476), .B(Raw_mant_NRM_SWR[8]), .C(
Raw_mant_NRM_SWR[7]), .Y(n2489) );
CLKAND2X2TS U2770 ( .A(n2489), .B(n3828), .Y(n2305) );
OAI32X1TS U2771 ( .A0(n2284), .A1(Raw_mant_NRM_SWR[40]), .A2(n3825), .B0(
n3698), .B1(n2284), .Y(n2287) );
INVX2TS U2772 ( .A(n2459), .Y(n2285) );
OAI32X1TS U2773 ( .A0(n2285), .A1(Raw_mant_NRM_SWR[20]), .A2(n3683), .B0(
n3754), .B1(n2285), .Y(n2286) );
AOI211X1TS U2774 ( .A0(n2305), .A1(n2288), .B0(n2287), .C0(n2286), .Y(n2480)
);
AOI22X1TS U2775 ( .A0(Raw_mant_NRM_SWR[31]), .A1(n2290), .B0(
Raw_mant_NRM_SWR[27]), .B1(n2289), .Y(n2308) );
INVX2TS U2776 ( .A(n2308), .Y(n2293) );
OAI22X1TS U2777 ( .A0(n3751), .A1(n2291), .B0(n3688), .B1(n2317), .Y(n2292)
);
AOI32X1TS U2778 ( .A0(Raw_mant_NRM_SWR[11]), .A1(n2487), .A2(n3703), .B0(
Raw_mant_NRM_SWR[13]), .B1(n2487), .Y(n2294) );
NAND3XLTS U2779 ( .A(n2480), .B(n2295), .C(n2294), .Y(n2404) );
AOI21X1TS U2780 ( .A0(Raw_mant_NRM_SWR[15]), .A1(n3682), .B0(
Raw_mant_NRM_SWR[17]), .Y(n2303) );
INVX2TS U2781 ( .A(n2296), .Y(n2299) );
OAI32X1TS U2782 ( .A0(Raw_mant_NRM_SWR[52]), .A1(Raw_mant_NRM_SWR[50]), .A2(
n3708), .B0(n3676), .B1(Raw_mant_NRM_SWR[52]), .Y(n2297) );
OAI21XLTS U2783 ( .A0(Raw_mant_NRM_SWR[53]), .A1(n2297), .B0(n3735), .Y(
n2298) );
OAI31X1TS U2784 ( .A0(Raw_mant_NRM_SWR[46]), .A1(n3704), .A2(n2299), .B0(
n2298), .Y(n2300) );
AOI31XLTS U2785 ( .A0(Raw_mant_NRM_SWR[37]), .A1(n2301), .A2(n3685), .B0(
n2300), .Y(n2302) );
OAI31X1TS U2786 ( .A0(Raw_mant_NRM_SWR[18]), .A1(n2303), .A2(n2485), .B0(
n2302), .Y(n2304) );
AOI211X1TS U2787 ( .A0(Raw_mant_NRM_SWR[35]), .A1(n2452), .B0(n2404), .C0(
n2304), .Y(n2306) );
NOR2X1TS U2788 ( .A(Raw_mant_NRM_SWR[4]), .B(Raw_mant_NRM_SWR[3]), .Y(n2316)
);
NAND2X1TS U2789 ( .A(n3711), .B(n2305), .Y(n2390) );
NOR2BX1TS U2790 ( .AN(n2316), .B(n2390), .Y(n2464) );
NOR2BX1TS U2791 ( .AN(n2464), .B(Raw_mant_NRM_SWR[2]), .Y(n2312) );
NAND2X1TS U2792 ( .A(Raw_mant_NRM_SWR[1]), .B(n2312), .Y(n2494) );
AOI31X1TS U2793 ( .A0(n2479), .A1(n2306), .A2(n2494), .B0(n3322), .Y(n3247)
);
AOI211X4TS U2794 ( .A0(Shift_amount_SHT1_EWR[0]), .A1(n3322), .B0(n2849),
.C0(n3247), .Y(n2340) );
INVX2TS U2795 ( .A(n2406), .Y(n2847) );
NOR2X1TS U2796 ( .A(Raw_mant_NRM_SWR[24]), .B(Raw_mant_NRM_SWR[23]), .Y(
n2400) );
INVX2TS U2797 ( .A(n2483), .Y(n2394) );
AOI21X1TS U2798 ( .A0(n3670), .A1(n3683), .B0(n2391), .Y(n2310) );
AOI31XLTS U2799 ( .A0(n3805), .A1(n3699), .A2(n2308), .B0(n2307), .Y(n2309)
);
AOI211X1TS U2800 ( .A0(n2311), .A1(Raw_mant_NRM_SWR[32]), .B0(n2310), .C0(
n2309), .Y(n2313) );
NAND3XLTS U2801 ( .A(Raw_mant_NRM_SWR[0]), .B(n2312), .C(n3669), .Y(n2495)
);
OAI211X1TS U2802 ( .A0(n2400), .A1(n2394), .B0(n2313), .C0(n2495), .Y(n2463)
);
INVX2TS U2803 ( .A(n2475), .Y(n2405) );
NAND2X1TS U2804 ( .A(n3703), .B(n3864), .Y(n2474) );
AOI22X1TS U2805 ( .A0(n1984), .A1(Raw_mant_NRM_SWR[15]), .B0(n2405), .B1(
n2474), .Y(n2315) );
OAI211X1TS U2806 ( .A0(n2316), .A1(n2390), .B0(n2315), .C0(n2314), .Y(n2493)
);
NOR2X1TS U2807 ( .A(n3762), .B(n2317), .Y(n2399) );
INVX2TS U2808 ( .A(n2399), .Y(n2325) );
NOR2X1TS U2809 ( .A(Raw_mant_NRM_SWR[50]), .B(Raw_mant_NRM_SWR[49]), .Y(
n2396) );
NOR2X1TS U2810 ( .A(Raw_mant_NRM_SWR[54]), .B(Raw_mant_NRM_SWR[53]), .Y(
n2321) );
NAND2X1TS U2811 ( .A(n3759), .B(n3704), .Y(n2318) );
OAI211XLTS U2812 ( .A0(n3705), .A1(n2318), .B0(n3778), .C0(n3677), .Y(n2320)
);
NAND2X1TS U2813 ( .A(n3760), .B(n3676), .Y(n2319) );
AOI32X1TS U2814 ( .A0(n2396), .A1(n2321), .A2(n2320), .B0(n2319), .B1(n2321),
.Y(n2324) );
OAI211XLTS U2815 ( .A0(Raw_mant_NRM_SWR[40]), .A1(Raw_mant_NRM_SWR[39]),
.B0(n2322), .C0(n3698), .Y(n2323) );
OAI211XLTS U2816 ( .A0(Raw_mant_NRM_SWR[29]), .A1(n2325), .B0(n2324), .C0(
n2323), .Y(n2326) );
NOR4X1TS U2817 ( .A(n2327), .B(n2463), .C(n2493), .D(n2326), .Y(n2328) );
OAI2BB1X1TS U2818 ( .A0N(Raw_mant_NRM_SWR[16]), .A1N(n1984), .B0(n2328), .Y(
n3276) );
AOI22X1TS U2819 ( .A0(n2583), .A1(n3276), .B0(Shift_amount_SHT1_EWR[1]),
.B1(n3322), .Y(n2329) );
NOR2X1TS U2820 ( .A(n2847), .B(n2329), .Y(n2331) );
INVX2TS U2821 ( .A(n2331), .Y(n2522) );
NOR2X2TS U2822 ( .A(n2340), .B(n2522), .Y(n2523) );
INVX2TS U2823 ( .A(n2523), .Y(n2543) );
CLKBUFX2TS U2824 ( .A(n2543), .Y(n2381) );
CLKBUFX3TS U2825 ( .A(n2381), .Y(n2626) );
INVX2TS U2826 ( .A(n2340), .Y(n2515) );
NAND2X1TS U2827 ( .A(n2329), .B(n2406), .Y(n2527) );
OR2X2TS U2828 ( .A(n2515), .B(n2527), .Y(n2518) );
INVX2TS U2829 ( .A(n2518), .Y(n2628) );
CLKBUFX3TS U2830 ( .A(n2345), .Y(n2844) );
AOI22X1TS U2831 ( .A0(Raw_mant_NRM_SWR[39]), .A1(n2562), .B0(
DmP_mant_SHT1_SW[13]), .B1(n2844), .Y(n2330) );
AOI22X1TS U2832 ( .A0(n2621), .A1(Data_array_SWR[15]), .B0(n2941), .B1(n2620), .Y(n2335) );
NAND2X1TS U2833 ( .A(n2331), .B(n2340), .Y(n2513) );
INVX2TS U2834 ( .A(n2513), .Y(n2586) );
CLKBUFX2TS U2835 ( .A(n2586), .Y(n2354) );
CLKBUFX3TS U2836 ( .A(n2354), .Y(n2632) );
CLKBUFX2TS U2837 ( .A(n2849), .Y(n2382) );
INVX2TS U2838 ( .A(n2382), .Y(n2564) );
AOI22X1TS U2839 ( .A0(Raw_mant_NRM_SWR[37]), .A1(n2603), .B0(
DmP_mant_SHT1_SW[15]), .B1(n2602), .Y(n2332) );
OR2X2TS U2840 ( .A(n2340), .B(n2527), .Y(n2519) );
AOI22X1TS U2841 ( .A0(Raw_mant_NRM_SWR[38]), .A1(n2562), .B0(
DmP_mant_SHT1_SW[14]), .B1(n2602), .Y(n2333) );
AOI22X1TS U2842 ( .A0(n2632), .A1(n2614), .B0(n2892), .B1(n2020), .Y(n2334)
);
INVX2TS U2843 ( .A(n2466), .Y(n2562) );
AOI222X4TS U2844 ( .A0(n2038), .A1(DmP_mant_SHT1_SW[51]), .B0(n2562), .B1(
Raw_mant_NRM_SWR[1]), .C0(Raw_mant_NRM_SWR[53]), .C1(n2849), .Y(n2514)
);
INVX2TS U2845 ( .A(n2382), .Y(n2943) );
AOI22X1TS U2846 ( .A0(n2583), .A1(Raw_mant_NRM_SWR[2]), .B0(
DmP_mant_SHT1_SW[50]), .B1(n3322), .Y(n2336) );
AOI22X1TS U2847 ( .A0(n2847), .A1(Data_array_SWR[52]), .B0(n2577), .B1(n1999), .Y(n2338) );
CLKBUFX3TS U2848 ( .A(n2893), .Y(n2853) );
OAI221X2TS U2849 ( .A0(n2603), .A1(n3735), .B0(n2851), .B1(n3867), .C0(n2042), .Y(n2940) );
NAND2X1TS U2850 ( .A(n2853), .B(n2940), .Y(n2337) );
OAI211XLTS U2851 ( .A0(n2514), .A1(n2519), .B0(n2338), .C0(n2337), .Y(n1750)
);
AO22XLTS U2852 ( .A0(n2041), .A1(Raw_mant_NRM_SWR[27]), .B0(n2038), .B1(
DmP_mant_SHT1_SW[25]), .Y(n2516) );
INVX2TS U2853 ( .A(n2466), .Y(n2848) );
CLKBUFX3TS U2854 ( .A(n2345), .Y(n2561) );
AOI22X1TS U2855 ( .A0(Raw_mant_NRM_SWR[26]), .A1(n2848), .B0(
DmP_mant_SHT1_SW[26]), .B1(n2561), .Y(n2339) );
AOI22X1TS U2856 ( .A0(n2340), .A1(n2516), .B0(n1974), .B1(n2515), .Y(n2424)
);
AOI22X1TS U2857 ( .A0(Raw_mant_NRM_SWR[24]), .A1(n2848), .B0(
DmP_mant_SHT1_SW[28]), .B1(n2561), .Y(n2341) );
AOI22X1TS U2858 ( .A0(n2629), .A1(Data_array_SWR[27]), .B0(n2523), .B1(n1989), .Y(n2344) );
AOI22X1TS U2859 ( .A0(Raw_mant_NRM_SWR[25]), .A1(n2848), .B0(
DmP_mant_SHT1_SW[27]), .B1(n2561), .Y(n2342) );
NAND2X1TS U2860 ( .A(n2853), .B(n1988), .Y(n2343) );
OAI211XLTS U2861 ( .A0(n2424), .A1(n2527), .B0(n2344), .C0(n2343), .Y(n1725)
);
INVX2TS U2862 ( .A(n2382), .Y(n2585) );
CLKBUFX3TS U2863 ( .A(n2345), .Y(n2549) );
AOI22X1TS U2864 ( .A0(n2845), .A1(Raw_mant_NRM_SWR[13]), .B0(
DmP_mant_SHT1_SW[39]), .B1(n2549), .Y(n2346) );
CLKBUFX2TS U2865 ( .A(n2543), .Y(n2441) );
CLKBUFX3TS U2866 ( .A(n2441), .Y(n2576) );
AOI22X1TS U2867 ( .A0(Raw_mant_NRM_SWR[16]), .A1(n2562), .B0(
DmP_mant_SHT1_SW[36]), .B1(n2549), .Y(n2347) );
AOI22X1TS U2868 ( .A0(n2573), .A1(Data_array_SWR[38]), .B0(n2565), .B1(n2019), .Y(n2351) );
AOI22X1TS U2869 ( .A0(n2845), .A1(Raw_mant_NRM_SWR[14]), .B0(
DmP_mant_SHT1_SW[38]), .B1(n2549), .Y(n2348) );
AOI22X1TS U2870 ( .A0(n2845), .A1(Raw_mant_NRM_SWR[15]), .B0(
DmP_mant_SHT1_SW[37]), .B1(n2549), .Y(n2349) );
AOI22X1TS U2871 ( .A0(n2586), .A1(n1990), .B0(n2631), .B1(n2008), .Y(n2350)
);
OAI211XLTS U2872 ( .A0(n1903), .A1(n2576), .B0(n2351), .C0(n2350), .Y(n1736)
);
AOI22X1TS U2873 ( .A0(n2847), .A1(Data_array_SWR[53]), .B0(n2597), .B1(n2940), .Y(n2352) );
OAI21XLTS U2874 ( .A0(n2514), .A1(n2518), .B0(n2352), .Y(n1751) );
INVX2TS U2875 ( .A(n2406), .Y(n2593) );
AOI22X1TS U2876 ( .A0(Raw_mant_NRM_SWR[17]), .A1(n2603), .B0(
DmP_mant_SHT1_SW[35]), .B1(n2549), .Y(n2353) );
AOI22X1TS U2877 ( .A0(n2593), .A1(Data_array_SWR[37]), .B0(n2565), .B1(n2003), .Y(n2356) );
CLKBUFX3TS U2878 ( .A(n2354), .Y(n2623) );
AOI22X1TS U2879 ( .A0(n2623), .A1(n2008), .B0(n2606), .B1(n2019), .Y(n2355)
);
OAI211XLTS U2880 ( .A0(n1902), .A1(n2576), .B0(n2356), .C0(n2355), .Y(n1735)
);
AOI22X1TS U2881 ( .A0(Raw_mant_NRM_SWR[18]), .A1(n2562), .B0(
DmP_mant_SHT1_SW[34]), .B1(n2549), .Y(n2357) );
AOI22X1TS U2882 ( .A0(n2629), .A1(Data_array_SWR[36]), .B0(n2565), .B1(n2014), .Y(n2359) );
AOI22X1TS U2883 ( .A0(n2586), .A1(n2019), .B0(n2892), .B1(n2003), .Y(n2358)
);
OAI211XLTS U2884 ( .A0(n1919), .A1(n2576), .B0(n2359), .C0(n2358), .Y(n1734)
);
AOI22X1TS U2885 ( .A0(n2849), .A1(Raw_mant_NRM_SWR[14]), .B0(
DmP_mant_SHT1_SW[12]), .B1(n2844), .Y(n2360) );
INVX2TS U2886 ( .A(n2622), .Y(n2366) );
AOI22X1TS U2887 ( .A0(n2382), .A1(Raw_mant_NRM_SWR[11]), .B0(
DmP_mant_SHT1_SW[9]), .B1(n2844), .Y(n2361) );
AOI22X1TS U2888 ( .A0(n2573), .A1(Data_array_SWR[11]), .B0(n2890), .B1(n2374), .Y(n2365) );
AOI22X1TS U2889 ( .A0(Raw_mant_NRM_SWR[41]), .A1(n2603), .B0(
DmP_mant_SHT1_SW[11]), .B1(n2844), .Y(n2362) );
AOI22X1TS U2890 ( .A0(Raw_mant_NRM_SWR[42]), .A1(n2562), .B0(
DmP_mant_SHT1_SW[10]), .B1(n2561), .Y(n2363) );
AOI22X1TS U2891 ( .A0(n2632), .A1(n2012), .B0(n2568), .B1(n1998), .Y(n2364)
);
OAI211XLTS U2892 ( .A0(n2366), .A1(n2626), .B0(n2365), .C0(n2364), .Y(n1709)
);
AOI22X1TS U2893 ( .A0(n2382), .A1(Raw_mant_NRM_SWR[10]), .B0(
DmP_mant_SHT1_SW[8]), .B1(n2844), .Y(n2367) );
AOI22X1TS U2894 ( .A0(n2629), .A1(Data_array_SWR[10]), .B0(n2577), .B1(n2414), .Y(n2369) );
CLKBUFX3TS U2895 ( .A(n2586), .Y(n2893) );
AOI22X1TS U2896 ( .A0(n2893), .A1(n1998), .B0(n2631), .B1(n2374), .Y(n2368)
);
OAI211XLTS U2897 ( .A0(n1924), .A1(n2626), .B0(n2369), .C0(n2368), .Y(n1708)
);
CLKBUFX3TS U2898 ( .A(n2724), .Y(n2932) );
CLKBUFX2TS U2899 ( .A(n2812), .Y(n2872) );
INVX2TS U2900 ( .A(n2921), .Y(n2689) );
AOI222X1TS U2901 ( .A0(n2932), .A1(intDX_EWSW[57]), .B0(DMP_EXP_EWSW[57]),
.B1(n2872), .C0(intDY_EWSW[57]), .C1(n2927), .Y(n2370) );
INVX2TS U2902 ( .A(n2370), .Y(n1618) );
AOI22X1TS U2903 ( .A0(Raw_mant_NRM_SWR[45]), .A1(n2845), .B0(
DmP_mant_SHT1_SW[7]), .B1(n2844), .Y(n2371) );
AOI22X1TS U2904 ( .A0(n2621), .A1(Data_array_SWR[9]), .B0(n2941), .B1(n2007),
.Y(n2373) );
AOI22X1TS U2905 ( .A0(n2893), .A1(n2374), .B0(n2606), .B1(n2414), .Y(n2372)
);
OAI211XLTS U2906 ( .A0(n1913), .A1(n2626), .B0(n2373), .C0(n2372), .Y(n1707)
);
INVX2TS U2907 ( .A(n2374), .Y(n2378) );
AOI22X1TS U2908 ( .A0(n2849), .A1(Raw_mant_NRM_SWR[8]), .B0(
DmP_mant_SHT1_SW[6]), .B1(n2844), .Y(n2375) );
AOI22X1TS U2909 ( .A0(n2573), .A1(Data_array_SWR[8]), .B0(n2890), .B1(n2415),
.Y(n2377) );
INVX2TS U2910 ( .A(n2519), .Y(n2892) );
AOI22X1TS U2911 ( .A0(n2893), .A1(n2414), .B0(n2631), .B1(n2007), .Y(n2376)
);
CLKBUFX3TS U2912 ( .A(n2724), .Y(n2919) );
AOI22X1TS U2913 ( .A0(intDX_EWSW[54]), .A1(n2919), .B0(DMP_EXP_EWSW[54]),
.B1(n2918), .Y(n2379) );
OAI21XLTS U2914 ( .A0(n3764), .A1(n2885), .B0(n2379), .Y(n1621) );
AOI22X1TS U2915 ( .A0(Raw_mant_NRM_SWR[47]), .A1(n2845), .B0(
DmP_mant_SHT1_SW[5]), .B1(n2844), .Y(n2380) );
CLKBUFX2TS U2916 ( .A(n2381), .Y(n2896) );
AOI22X1TS U2917 ( .A0(n2382), .A1(Raw_mant_NRM_SWR[4]), .B0(
DmP_mant_SHT1_SW[2]), .B1(n2038), .Y(n2383) );
AOI22X1TS U2918 ( .A0(n2942), .A1(Data_array_SWR[4]), .B0(n2577), .B1(n2888),
.Y(n2387) );
AOI22X1TS U2919 ( .A0(Raw_mant_NRM_SWR[48]), .A1(n2845), .B0(
DmP_mant_SHT1_SW[4]), .B1(n2844), .Y(n2384) );
AOI22X1TS U2920 ( .A0(Raw_mant_NRM_SWR[49]), .A1(n2845), .B0(
DmP_mant_SHT1_SW[3]), .B1(n2345), .Y(n2385) );
AOI22X1TS U2921 ( .A0(n2586), .A1(n2016), .B0(n2606), .B1(n2004), .Y(n2386)
);
OAI211XLTS U2922 ( .A0(n1916), .A1(n2896), .B0(n2387), .C0(n2386), .Y(n1702)
);
INVX2TS U2923 ( .A(n2724), .Y(n2839) );
AOI22X1TS U2924 ( .A0(intDY_EWSW[56]), .A1(n2686), .B0(DMP_EXP_EWSW[56]),
.B1(n2918), .Y(n2388) );
OAI21XLTS U2925 ( .A0(n3780), .A1(n2839), .B0(n2388), .Y(n1619) );
AOI21X1TS U2926 ( .A0(n3803), .A1(n3690), .B0(n2389), .Y(n2393) );
OAI22X1TS U2927 ( .A0(n3670), .A1(n2391), .B0(n2390), .B1(n3856), .Y(n2392)
);
AOI211X1TS U2928 ( .A0(n2489), .A1(Raw_mant_NRM_SWR[6]), .B0(n2393), .C0(
n2392), .Y(n2478) );
OAI2BB1X1TS U2929 ( .A0N(n2396), .A1N(n3778), .B0(n2031), .Y(n2397) );
AOI32X1TS U2930 ( .A0(n3702), .A1(n2397), .A2(n3819), .B0(n2457), .B1(n2397),
.Y(n2398) );
AOI211X1TS U2931 ( .A0(n2405), .A1(Raw_mant_NRM_SWR[12]), .B0(n2404), .C0(
n2403), .Y(n2736) );
AOI22X1TS U2932 ( .A0(n2942), .A1(shift_value_SHT2_EWR[2]), .B0(n2496), .B1(
Shift_amount_SHT1_EWR[2]), .Y(n2408) );
OAI21XLTS U2933 ( .A0(n2736), .A1(n2466), .B0(n2408), .Y(n1697) );
INVX2TS U2934 ( .A(n2415), .Y(n2411) );
AOI22X1TS U2935 ( .A0(n2942), .A1(Data_array_SWR[5]), .B0(n2628), .B1(n2004),
.Y(n2410) );
AOI22X1TS U2936 ( .A0(n2893), .A1(n2015), .B0(n2568), .B1(n2016), .Y(n2409)
);
OAI211XLTS U2937 ( .A0(n2411), .A1(n2896), .B0(n2410), .C0(n2409), .Y(n1703)
);
AOI22X1TS U2938 ( .A0(n2942), .A1(Data_array_SWR[6]), .B0(n2941), .B1(n2016),
.Y(n2413) );
AOI22X1TS U2939 ( .A0(n2893), .A1(n2415), .B0(n2631), .B1(n2015), .Y(n2412)
);
OAI211XLTS U2940 ( .A0(n1897), .A1(n2896), .B0(n2413), .C0(n2412), .Y(n1704)
);
INVX2TS U2941 ( .A(n2414), .Y(n2418) );
AOI22X1TS U2942 ( .A0(n2629), .A1(Data_array_SWR[7]), .B0(n2890), .B1(n2015),
.Y(n2417) );
AOI22X1TS U2943 ( .A0(n2893), .A1(n2007), .B0(n2606), .B1(n2415), .Y(n2416)
);
OAI211XLTS U2944 ( .A0(n2418), .A1(n2626), .B0(n2417), .C0(n2416), .Y(n1705)
);
AOI22X1TS U2945 ( .A0(intDY_EWSW[52]), .A1(n2909), .B0(DmP_EXP_EWSW[52]),
.B1(n3320), .Y(n2419) );
AOI22X1TS U2946 ( .A0(intDX_EWSW[57]), .A1(n2936), .B0(DmP_EXP_EWSW[57]),
.B1(n2918), .Y(n2420) );
OAI21XLTS U2947 ( .A0(n3802), .A1(n2839), .B0(n2420), .Y(n1289) );
AOI22X1TS U2948 ( .A0(Raw_mant_NRM_SWR[29]), .A1(n2848), .B0(
DmP_mant_SHT1_SW[23]), .B1(n2602), .Y(n2421) );
OAI21X1TS U2949 ( .A0(n3756), .A1(n3317), .B0(n2421), .Y(n2579) );
INVX2TS U2950 ( .A(n2579), .Y(n2535) );
OAI22X1TS U2951 ( .A0(n2582), .A1(n2519), .B0(n2535), .B1(n2518), .Y(n2422)
);
AOI21X1TS U2952 ( .A0(n2847), .A1(Data_array_SWR[25]), .B0(n2422), .Y(n2423)
);
OAI21XLTS U2953 ( .A0(n2522), .A1(n2424), .B0(n2423), .Y(n1723) );
INVX2TS U2954 ( .A(n2909), .Y(n3191) );
AOI22X1TS U2955 ( .A0(intDX_EWSW[54]), .A1(n2903), .B0(DmP_EXP_EWSW[54]),
.B1(n3320), .Y(n2425) );
OAI21XLTS U2956 ( .A0(n3764), .A1(n3191), .B0(n2425), .Y(n1292) );
CLKBUFX3TS U2957 ( .A(n2885), .Y(n2911) );
AOI22X1TS U2958 ( .A0(intDY_EWSW[56]), .A1(n2919), .B0(DmP_EXP_EWSW[56]),
.B1(n3320), .Y(n2426) );
OAI21XLTS U2959 ( .A0(n3780), .A1(n2911), .B0(n2426), .Y(n1290) );
AOI2BB2XLTS U2960 ( .B0(beg_OP), .B1(n3684), .A0N(n3684), .A1N(
inst_FSM_INPUT_ENABLE_state_reg[2]), .Y(n2427) );
NAND3XLTS U2961 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n3684), .C(
n3841), .Y(n3159) );
OAI21XLTS U2962 ( .A0(n3158), .A1(n2427), .B0(n3159), .Y(n1891) );
AOI22X1TS U2963 ( .A0(Data_array_SWR[17]), .A1(n2954), .B0(
Data_array_SWR[25]), .B1(n3015), .Y(n2429) );
AOI22X1TS U2964 ( .A0(Data_array_SWR[13]), .A1(n1961), .B0(Data_array_SWR[5]), .B1(n1963), .Y(n2432) );
AOI22X1TS U2965 ( .A0(Data_array_SWR[9]), .A1(n1965), .B0(Data_array_SWR[1]),
.B1(n1967), .Y(n2431) );
OAI211XLTS U2966 ( .A0(n3074), .A1(n1948), .B0(n2432), .C0(n2431), .Y(n2434)
);
INVX2TS U2967 ( .A(n3100), .Y(n3070) );
NAND2X2TS U2968 ( .A(shift_value_SHT2_EWR[4]), .B(shift_value_SHT2_EWR[5]),
.Y(n3012) );
INVX2TS U2969 ( .A(n1959), .Y(n2961) );
OAI22X1TS U2970 ( .A0(n3070), .A1(n3012), .B0(n3106), .B1(n2961), .Y(n2433)
);
CLKBUFX2TS U2971 ( .A(n3136), .Y(n3023) );
NAND2X1TS U2972 ( .A(Shift_reg_FLAGS_7[3]), .B(n3023), .Y(n3137) );
INVX2TS U2973 ( .A(n3145), .Y(n3305) );
NAND2X1TS U2974 ( .A(n1957), .B(n3305), .Y(n2435) );
INVX2TS U2975 ( .A(n2435), .Y(n2499) );
INVX2TS U2976 ( .A(n2499), .Y(n3202) );
NAND2X1TS U2977 ( .A(n3305), .B(n3746), .Y(n2436) );
INVX2TS U2978 ( .A(n2436), .Y(n2498) );
INVX2TS U2979 ( .A(n2997), .Y(n2765) );
AOI22X1TS U2980 ( .A0(DmP_mant_SFG_SWR[53]), .A1(n3190), .B0(n2498), .B1(
n2739), .Y(n2437) );
INVX2TS U2981 ( .A(n2909), .Y(n2902) );
AOI22X1TS U2982 ( .A0(intDY_EWSW[52]), .A1(n2936), .B0(DMP_EXP_EWSW[52]),
.B1(n2918), .Y(n2438) );
OAI21XLTS U2983 ( .A0(n3779), .A1(n2902), .B0(n2438), .Y(n1623) );
AOI22X1TS U2984 ( .A0(intDX_EWSW[53]), .A1(n2919), .B0(DMP_EXP_EWSW[53]),
.B1(n2918), .Y(n2439) );
OAI21XLTS U2985 ( .A0(n3667), .A1(n2885), .B0(n2439), .Y(n1622) );
AOI22X1TS U2986 ( .A0(Raw_mant_NRM_SWR[21]), .A1(n2848), .B0(
DmP_mant_SHT1_SW[31]), .B1(n2561), .Y(n2440) );
AOI22X1TS U2987 ( .A0(n2621), .A1(Data_array_SWR[30]), .B0(n2890), .B1(n1989), .Y(n2445) );
AOI22X1TS U2988 ( .A0(Raw_mant_NRM_SWR[22]), .A1(n2848), .B0(
DmP_mant_SHT1_SW[30]), .B1(n2561), .Y(n2442) );
AOI22X1TS U2989 ( .A0(Raw_mant_NRM_SWR[23]), .A1(n2848), .B0(
DmP_mant_SHT1_SW[29]), .B1(n2561), .Y(n2443) );
AOI22X1TS U2990 ( .A0(n2623), .A1(n2009), .B0(n2631), .B1(n2013), .Y(n2444)
);
OAI211XLTS U2991 ( .A0(n1906), .A1(n2441), .B0(n2445), .C0(n2444), .Y(n1728)
);
AOI22X1TS U2992 ( .A0(n2573), .A1(Data_array_SWR[29]), .B0(n2577), .B1(n1988), .Y(n2447) );
AOI22X1TS U2993 ( .A0(n2623), .A1(n2013), .B0(n2606), .B1(n1989), .Y(n2446)
);
OAI211XLTS U2994 ( .A0(n1922), .A1(n2381), .B0(n2447), .C0(n2446), .Y(n1727)
);
AOI22X1TS U2995 ( .A0(n2629), .A1(Data_array_SWR[28]), .B0(n2941), .B1(n1974), .Y(n2449) );
AOI22X1TS U2996 ( .A0(n2623), .A1(n1989), .B0(n2568), .B1(n1988), .Y(n2448)
);
OAI211XLTS U2997 ( .A0(n1921), .A1(n2441), .B0(n2449), .C0(n2448), .Y(n1726)
);
NAND2X1TS U2998 ( .A(n3685), .B(n3755), .Y(n2450) );
AOI22X1TS U2999 ( .A0(Raw_mant_NRM_SWR[34]), .A1(n2452), .B0(n2451), .B1(
n2450), .Y(n2456) );
NAND2X1TS U3000 ( .A(n3688), .B(n3762), .Y(n2454) );
OAI31X1TS U3001 ( .A0(Raw_mant_NRM_SWR[30]), .A1(Raw_mant_NRM_SWR[26]), .A2(
n2454), .B0(n2453), .Y(n2455) );
OAI211XLTS U3002 ( .A0(n3751), .A1(n2457), .B0(n2456), .C0(n2455), .Y(n2458)
);
OAI211XLTS U3003 ( .A0(n2461), .A1(n3756), .B0(n2460), .C0(n2494), .Y(n2462)
);
AOI211X1TS U3004 ( .A0(n2464), .A1(Raw_mant_NRM_SWR[2]), .B0(n2463), .C0(
n2462), .Y(n2731) );
AOI22X1TS U3005 ( .A0(n2942), .A1(shift_value_SHT2_EWR[4]), .B0(
Shift_amount_SHT1_EWR[4]), .B1(n2496), .Y(n2465) );
OAI21XLTS U3006 ( .A0(n2731), .A1(n2466), .B0(n2465), .Y(n1695) );
NOR3X1TS U3007 ( .A(Raw_mant_NRM_SWR[46]), .B(Raw_mant_NRM_SWR[45]), .C(
Raw_mant_NRM_SWR[44]), .Y(n2469) );
OAI22X1TS U3008 ( .A0(n2469), .A1(n2468), .B0(n3750), .B1(n2467), .Y(n2470)
);
AOI211X1TS U3009 ( .A0(n2472), .A1(Raw_mant_NRM_SWR[26]), .B0(n2471), .C0(
n2470), .Y(n2473) );
OAI31X1TS U3010 ( .A0(n2475), .A1(n3866), .A2(n2474), .B0(n2473), .Y(n2482)
);
NAND2X1TS U3011 ( .A(n2476), .B(Raw_mant_NRM_SWR[8]), .Y(n2477) );
NAND4XLTS U3012 ( .A(n2480), .B(n2479), .C(n2478), .D(n2477), .Y(n2481) );
AOI211X1TS U3013 ( .A0(Raw_mant_NRM_SWR[24]), .A1(n2483), .B0(n2482), .C0(
n2481), .Y(n2733) );
AOI22X1TS U3014 ( .A0(n2942), .A1(shift_value_SHT2_EWR[3]), .B0(n2496), .B1(
Shift_amount_SHT1_EWR[3]), .Y(n2484) );
OAI21XLTS U3015 ( .A0(n2733), .A1(n2852), .B0(n2484), .Y(n1696) );
NOR2XLTS U3016 ( .A(Raw_mant_NRM_SWR[18]), .B(Raw_mant_NRM_SWR[17]), .Y(
n2486) );
AOI31X1TS U3017 ( .A0(n2486), .A1(n3682), .A2(n3827), .B0(n2485), .Y(n2488)
);
OAI32X1TS U3018 ( .A0(n2488), .A1(Raw_mant_NRM_SWR[13]), .A2(
Raw_mant_NRM_SWR[10]), .B0(n2487), .B1(n2488), .Y(n2491) );
OAI31X1TS U3019 ( .A0(Raw_mant_NRM_SWR[5]), .A1(Raw_mant_NRM_SWR[6]), .A2(
Raw_mant_NRM_SWR[2]), .B0(n2489), .Y(n2490) );
NOR4BBX1TS U3020 ( .AN(n2495), .BN(n2494), .C(n2493), .D(n2492), .Y(n2728)
);
AOI22X1TS U3021 ( .A0(n2621), .A1(shift_value_SHT2_EWR[5]), .B0(n2496), .B1(
Shift_amount_SHT1_EWR[5]), .Y(n2497) );
OAI21XLTS U3022 ( .A0(n2030), .A1(n2851), .B0(n2497), .Y(n1693) );
INVX2TS U3023 ( .A(n2498), .Y(n3221) );
AOI22X1TS U3024 ( .A0(DmP_mant_SFG_SWR[1]), .A1(n3190), .B0(n2499), .B1(
n2739), .Y(n2500) );
OAI21XLTS U3025 ( .A0(n1970), .A1(n3212), .B0(n2500), .Y(n1155) );
AOI22X1TS U3026 ( .A0(n2583), .A1(Raw_mant_NRM_SWR[3]), .B0(
DmP_mant_SHT1_SW[49]), .B1(n3322), .Y(n2501) );
AOI22X1TS U3027 ( .A0(n2583), .A1(Raw_mant_NRM_SWR[6]), .B0(
DmP_mant_SHT1_SW[46]), .B1(n3322), .Y(n2502) );
AOI22X1TS U3028 ( .A0(n2847), .A1(Data_array_SWR[48]), .B0(n2628), .B1(n2596), .Y(n2506) );
AOI22X1TS U3029 ( .A0(n2583), .A1(Raw_mant_NRM_SWR[4]), .B0(
DmP_mant_SHT1_SW[48]), .B1(n2549), .Y(n2503) );
AOI22X1TS U3030 ( .A0(n2583), .A1(Raw_mant_NRM_SWR[5]), .B0(
DmP_mant_SHT1_SW[47]), .B1(n3322), .Y(n2504) );
AOI22X1TS U3031 ( .A0(n2853), .A1(n1992), .B0(n2597), .B1(n2598), .Y(n2505)
);
OAI211XLTS U3032 ( .A0(n1899), .A1(n2543), .B0(n2506), .C0(n2505), .Y(n1746)
);
AOI22X1TS U3033 ( .A0(n2847), .A1(Data_array_SWR[49]), .B0(n2941), .B1(n2598), .Y(n2508) );
AOI22X1TS U3034 ( .A0(n2853), .A1(n1994), .B0(n2597), .B1(n1992), .Y(n2507)
);
OAI211XLTS U3035 ( .A0(n1900), .A1(n2543), .B0(n2508), .C0(n2507), .Y(n1747)
);
AOI22X1TS U3036 ( .A0(n2593), .A1(Data_array_SWR[50]), .B0(n2890), .B1(n1992), .Y(n2510) );
AOI22X1TS U3037 ( .A0(n2853), .A1(n1999), .B0(n2597), .B1(n1994), .Y(n2509)
);
OAI211XLTS U3038 ( .A0(n2514), .A1(n2543), .B0(n2510), .C0(n2509), .Y(n1748)
);
AOI22X1TS U3039 ( .A0(n2847), .A1(Data_array_SWR[51]), .B0(n2577), .B1(n1994), .Y(n2512) );
AOI22X1TS U3040 ( .A0(n2523), .A1(n2940), .B0(n2597), .B1(n1999), .Y(n2511)
);
OAI211XLTS U3041 ( .A0(n2514), .A1(n2513), .B0(n2512), .C0(n2511), .Y(n1749)
);
AOI2BB2X1TS U3042 ( .B0(n2516), .B1(n2515), .A0N(n2515), .A1N(n2582), .Y(
n2526) );
AOI22X1TS U3043 ( .A0(Raw_mant_NRM_SWR[30]), .A1(n2848), .B0(
DmP_mant_SHT1_SW[22]), .B1(n2602), .Y(n2517) );
OAI22X1TS U3044 ( .A0(n2535), .A1(n2519), .B0(n1976), .B1(n2518), .Y(n2520)
);
AOI21X1TS U3045 ( .A0(n2407), .A1(Data_array_SWR[24]), .B0(n2520), .Y(n2521)
);
OAI21XLTS U3046 ( .A0(n2522), .A1(n2526), .B0(n2521), .Y(n1722) );
AOI22X1TS U3047 ( .A0(n2573), .A1(Data_array_SWR[26]), .B0(n2523), .B1(n1988), .Y(n2525) );
NAND2X1TS U3048 ( .A(n2853), .B(n1974), .Y(n2524) );
OAI211XLTS U3049 ( .A0(n2527), .A1(n2526), .B0(n2525), .C0(n2524), .Y(n1724)
);
AOI22X1TS U3050 ( .A0(Raw_mant_NRM_SWR[19]), .A1(n2603), .B0(
DmP_mant_SHT1_SW[33]), .B1(n2561), .Y(n2528) );
AOI22X1TS U3051 ( .A0(n2621), .A1(Data_array_SWR[35]), .B0(n2565), .B1(n2005), .Y(n2530) );
AOI22X1TS U3052 ( .A0(n2354), .A1(n2003), .B0(n2568), .B1(n2014), .Y(n2529)
);
OAI211XLTS U3053 ( .A0(n1928), .A1(n2576), .B0(n2530), .C0(n2529), .Y(n1733)
);
AOI22X1TS U3054 ( .A0(Raw_mant_NRM_SWR[32]), .A1(n2603), .B0(
DmP_mant_SHT1_SW[20]), .B1(n2602), .Y(n2531) );
AOI22X1TS U3055 ( .A0(n2629), .A1(Data_array_SWR[22]), .B0(n2890), .B1(n2010), .Y(n2534) );
AOI22X1TS U3056 ( .A0(Raw_mant_NRM_SWR[31]), .A1(n2848), .B0(
DmP_mant_SHT1_SW[21]), .B1(n2602), .Y(n2532) );
AOI22X1TS U3057 ( .A0(n2623), .A1(n1977), .B0(n2631), .B1(n2000), .Y(n2533)
);
OAI211XLTS U3058 ( .A0(n2535), .A1(n2381), .B0(n2534), .C0(n2533), .Y(n1720)
);
AOI22X1TS U3059 ( .A0(Raw_mant_NRM_SWR[33]), .A1(n2562), .B0(
DmP_mant_SHT1_SW[19]), .B1(n2602), .Y(n2536) );
AOI22X1TS U3060 ( .A0(n2621), .A1(Data_array_SWR[21]), .B0(n2577), .B1(n1995), .Y(n2538) );
AOI22X1TS U3061 ( .A0(n2632), .A1(n2000), .B0(n2606), .B1(n2010), .Y(n2537)
);
OAI211XLTS U3062 ( .A0(n1976), .A1(n2441), .B0(n2538), .C0(n2537), .Y(n1719)
);
AOI22X1TS U3063 ( .A0(Raw_mant_NRM_SWR[34]), .A1(n2603), .B0(
DmP_mant_SHT1_SW[18]), .B1(n2602), .Y(n2539) );
AOI22X1TS U3064 ( .A0(n2573), .A1(Data_array_SWR[20]), .B0(n2628), .B1(n2018), .Y(n2541) );
AOI22X1TS U3065 ( .A0(n2632), .A1(n2010), .B0(n2892), .B1(n1995), .Y(n2540)
);
OAI211XLTS U3066 ( .A0(n1907), .A1(n2381), .B0(n2541), .C0(n2540), .Y(n1718)
);
AOI22X1TS U3067 ( .A0(n2583), .A1(Raw_mant_NRM_SWR[8]), .B0(
DmP_mant_SHT1_SW[44]), .B1(n3322), .Y(n2542) );
CLKBUFX2TS U3068 ( .A(n2543), .Y(n2601) );
AOI22X1TS U3069 ( .A0(n2583), .A1(Raw_mant_NRM_SWR[11]), .B0(
DmP_mant_SHT1_SW[41]), .B1(n2561), .Y(n2544) );
AOI22X1TS U3070 ( .A0(n2593), .A1(Data_array_SWR[43]), .B0(n2565), .B1(n2555), .Y(n2548) );
AOI22X1TS U3071 ( .A0(n2583), .A1(Raw_mant_NRM_SWR[9]), .B0(
DmP_mant_SHT1_SW[43]), .B1(n2549), .Y(n2545) );
AOI22X1TS U3072 ( .A0(n2845), .A1(Raw_mant_NRM_SWR[10]), .B0(
DmP_mant_SHT1_SW[42]), .B1(n2549), .Y(n2546) );
AOI22X1TS U3073 ( .A0(n2586), .A1(n1996), .B0(n2597), .B1(n1993), .Y(n2547)
);
OAI211XLTS U3074 ( .A0(n1910), .A1(n2601), .B0(n2548), .C0(n2547), .Y(n1741)
);
AOI22X1TS U3075 ( .A0(n2845), .A1(Raw_mant_NRM_SWR[12]), .B0(
DmP_mant_SHT1_SW[40]), .B1(n2549), .Y(n2550) );
AOI22X1TS U3076 ( .A0(n2593), .A1(Data_array_SWR[42]), .B0(n2565), .B1(n2011), .Y(n2552) );
AOI22X1TS U3077 ( .A0(n2853), .A1(n1993), .B0(n2631), .B1(n2555), .Y(n2551)
);
OAI211XLTS U3078 ( .A0(n1909), .A1(n2601), .B0(n2552), .C0(n2551), .Y(n1740)
);
AOI22X1TS U3079 ( .A0(n2593), .A1(Data_array_SWR[41]), .B0(n2565), .B1(n1997), .Y(n2554) );
AOI22X1TS U3080 ( .A0(n2354), .A1(n2555), .B0(n2606), .B1(n2011), .Y(n2553)
);
OAI211XLTS U3081 ( .A0(n1908), .A1(n2601), .B0(n2554), .C0(n2553), .Y(n1739)
);
INVX2TS U3082 ( .A(n2555), .Y(n2558) );
AOI22X1TS U3083 ( .A0(n2593), .A1(Data_array_SWR[40]), .B0(n2565), .B1(n1990), .Y(n2557) );
AOI22X1TS U3084 ( .A0(n2354), .A1(n2011), .B0(n2892), .B1(n1997), .Y(n2556)
);
OAI211XLTS U3085 ( .A0(n2558), .A1(n2576), .B0(n2557), .C0(n2556), .Y(n1738)
);
AOI22X1TS U3086 ( .A0(n2593), .A1(Data_array_SWR[39]), .B0(n2565), .B1(n2008), .Y(n2560) );
AOI22X1TS U3087 ( .A0(n2354), .A1(n1997), .B0(n2568), .B1(n1990), .Y(n2559)
);
OAI211XLTS U3088 ( .A0(n1918), .A1(n2576), .B0(n2560), .C0(n2559), .Y(n1737)
);
AOI22X1TS U3089 ( .A0(Raw_mant_NRM_SWR[20]), .A1(n2562), .B0(
DmP_mant_SHT1_SW[32]), .B1(n2561), .Y(n2563) );
AOI22X1TS U3090 ( .A0(n2573), .A1(Data_array_SWR[34]), .B0(n2565), .B1(n2002), .Y(n2567) );
AOI22X1TS U3091 ( .A0(n2623), .A1(n2014), .B0(n2631), .B1(n2005), .Y(n2566)
);
OAI211XLTS U3092 ( .A0(n1901), .A1(n2576), .B0(n2567), .C0(n2566), .Y(n1732)
);
AOI22X1TS U3093 ( .A0(n2629), .A1(Data_array_SWR[33]), .B0(n2941), .B1(n2001), .Y(n2570) );
AOI22X1TS U3094 ( .A0(n2586), .A1(n2005), .B0(n2606), .B1(n2002), .Y(n2569)
);
OAI211XLTS U3095 ( .A0(n1920), .A1(n2576), .B0(n2570), .C0(n2569), .Y(n1731)
);
AOI22X1TS U3096 ( .A0(n2621), .A1(Data_array_SWR[32]), .B0(n2890), .B1(n2009), .Y(n2572) );
AOI22X1TS U3097 ( .A0(n2623), .A1(n2002), .B0(n2568), .B1(n2001), .Y(n2571)
);
AOI22X1TS U3098 ( .A0(n2573), .A1(Data_array_SWR[31]), .B0(n2577), .B1(n2013), .Y(n2575) );
AOI22X1TS U3099 ( .A0(n2623), .A1(n2001), .B0(n2631), .B1(n2009), .Y(n2574)
);
OAI211XLTS U3100 ( .A0(n1905), .A1(n2576), .B0(n2575), .C0(n2574), .Y(n1729)
);
AOI22X1TS U3101 ( .A0(n2629), .A1(Data_array_SWR[23]), .B0(n2628), .B1(n2000), .Y(n2581) );
AOI22X1TS U3102 ( .A0(n2623), .A1(n2579), .B0(n2606), .B1(n1977), .Y(n2580)
);
OAI211XLTS U3103 ( .A0(n2582), .A1(n2441), .B0(n2581), .C0(n2580), .Y(n1721)
);
INVX2TS U3104 ( .A(n2598), .Y(n2589) );
AOI22X1TS U3105 ( .A0(n2593), .A1(Data_array_SWR[46]), .B0(n2628), .B1(n1991), .Y(n2588) );
AOI22X1TS U3106 ( .A0(n2583), .A1(Raw_mant_NRM_SWR[7]), .B0(
DmP_mant_SHT1_SW[45]), .B1(n3322), .Y(n2584) );
AOI22X1TS U3107 ( .A0(n2586), .A1(n2596), .B0(n2597), .B1(n2006), .Y(n2587)
);
OAI211XLTS U3108 ( .A0(n2589), .A1(n2601), .B0(n2588), .C0(n2587), .Y(n1744)
);
INVX2TS U3109 ( .A(n2596), .Y(n2592) );
AOI22X1TS U3110 ( .A0(n2847), .A1(Data_array_SWR[45]), .B0(n2941), .B1(n1996), .Y(n2591) );
AOI22X1TS U3111 ( .A0(n2586), .A1(n2006), .B0(n2597), .B1(n1991), .Y(n2590)
);
OAI211XLTS U3112 ( .A0(n2592), .A1(n2601), .B0(n2591), .C0(n2590), .Y(n1743)
);
AOI22X1TS U3113 ( .A0(n2847), .A1(Data_array_SWR[44]), .B0(n2890), .B1(n1993), .Y(n2595) );
AOI22X1TS U3114 ( .A0(n2853), .A1(n1991), .B0(n2597), .B1(n1996), .Y(n2594)
);
OAI211XLTS U3115 ( .A0(n1911), .A1(n2601), .B0(n2595), .C0(n2594), .Y(n1742)
);
AOI22X1TS U3116 ( .A0(n2407), .A1(Data_array_SWR[47]), .B0(n2577), .B1(n2006), .Y(n2600) );
AOI22X1TS U3117 ( .A0(n2853), .A1(n2598), .B0(n2597), .B1(n2596), .Y(n2599)
);
OAI211XLTS U3118 ( .A0(n1898), .A1(n2601), .B0(n2600), .C0(n2599), .Y(n1745)
);
AOI22X1TS U3119 ( .A0(Raw_mant_NRM_SWR[35]), .A1(n2562), .B0(
DmP_mant_SHT1_SW[17]), .B1(n2602), .Y(n2604) );
AOI22X1TS U3120 ( .A0(n2621), .A1(Data_array_SWR[19]), .B0(n2941), .B1(n2630), .Y(n2608) );
AOI22X1TS U3121 ( .A0(n2632), .A1(n1995), .B0(n2892), .B1(n2018), .Y(n2607)
);
OAI211XLTS U3122 ( .A0(n1917), .A1(n2381), .B0(n2608), .C0(n2607), .Y(n1717)
);
AOI22X1TS U3123 ( .A0(n2573), .A1(Data_array_SWR[17]), .B0(n2890), .B1(n2614), .Y(n2610) );
AOI22X1TS U3124 ( .A0(n2632), .A1(n2630), .B0(n2892), .B1(n2021), .Y(n2609)
);
OAI211XLTS U3125 ( .A0(n1926), .A1(n2441), .B0(n2610), .C0(n2609), .Y(n1715)
);
INVX2TS U3126 ( .A(n2630), .Y(n2613) );
AOI22X1TS U3127 ( .A0(n2621), .A1(Data_array_SWR[16]), .B0(n2577), .B1(n2020), .Y(n2612) );
AOI22X1TS U3128 ( .A0(n2632), .A1(n2021), .B0(n2568), .B1(n2614), .Y(n2611)
);
OAI211XLTS U3129 ( .A0(n2613), .A1(n2626), .B0(n2612), .C0(n2611), .Y(n1714)
);
INVX2TS U3130 ( .A(n2614), .Y(n2617) );
AOI22X1TS U3131 ( .A0(n2573), .A1(Data_array_SWR[14]), .B0(n2628), .B1(n2622), .Y(n2616) );
AOI22X1TS U3132 ( .A0(n2632), .A1(n2020), .B0(n2631), .B1(n2620), .Y(n2615)
);
OAI211XLTS U3133 ( .A0(n2617), .A1(n2626), .B0(n2616), .C0(n2615), .Y(n1712)
);
AOI22X1TS U3134 ( .A0(n2629), .A1(Data_array_SWR[13]), .B0(n2628), .B1(n2012), .Y(n2619) );
AOI22X1TS U3135 ( .A0(n2632), .A1(n2620), .B0(n2606), .B1(n2622), .Y(n2618)
);
OAI211XLTS U3136 ( .A0(n1923), .A1(n2626), .B0(n2619), .C0(n2618), .Y(n1711)
);
INVX2TS U3137 ( .A(n2620), .Y(n2627) );
AOI22X1TS U3138 ( .A0(n2621), .A1(Data_array_SWR[12]), .B0(n2941), .B1(n1998), .Y(n2625) );
AOI22X1TS U3139 ( .A0(n2623), .A1(n2622), .B0(n2892), .B1(n2012), .Y(n2624)
);
OAI211XLTS U3140 ( .A0(n2627), .A1(n2626), .B0(n2625), .C0(n2624), .Y(n1710)
);
AOI22X1TS U3141 ( .A0(n2629), .A1(Data_array_SWR[18]), .B0(n2890), .B1(n2021), .Y(n2634) );
AOI22X1TS U3142 ( .A0(n2632), .A1(n2018), .B0(n2568), .B1(n2630), .Y(n2633)
);
OAI211XLTS U3143 ( .A0(n1912), .A1(n2543), .B0(n2634), .C0(n2633), .Y(n1716)
);
INVX2TS U3144 ( .A(n2946), .Y(n2957) );
AOI22X1TS U3145 ( .A0(Data_array_SWR[48]), .A1(n2825), .B0(
Data_array_SWR[40]), .B1(n2957), .Y(n2637) );
CLKBUFX3TS U3146 ( .A(n2635), .Y(n2994) );
AOI22X1TS U3147 ( .A0(Data_array_SWR[44]), .A1(n2994), .B0(
Data_array_SWR[52]), .B1(n3007), .Y(n2636) );
NAND2X1TS U3148 ( .A(n2637), .B(n2636), .Y(n3051) );
CLKBUFX2TS U3149 ( .A(n3007), .Y(n2960) );
AOI22X1TS U3150 ( .A0(Data_array_SWR[32]), .A1(n2825), .B0(
Data_array_SWR[24]), .B1(n3014), .Y(n2638) );
OAI21XLTS U3151 ( .A0(n3896), .A1(n2666), .B0(n2638), .Y(n2639) );
AOI21X1TS U3152 ( .A0(Data_array_SWR[36]), .A1(n2960), .B0(n2639), .Y(n2780)
);
OAI21XLTS U3153 ( .A0(n2780), .A1(n1956), .B0(n3134), .Y(n2640) );
AOI22X1TS U3154 ( .A0(Data_array_SWR[46]), .A1(n2954), .B0(
Data_array_SWR[54]), .B1(n2947), .Y(n2641) );
AOI22X1TS U3155 ( .A0(Data_array_SWR[38]), .A1(n2825), .B0(
Data_array_SWR[30]), .B1(n2804), .Y(n2644) );
AOI22X1TS U3156 ( .A0(Data_array_SWR[42]), .A1(n3007), .B0(
Data_array_SWR[34]), .B1(n2642), .Y(n2643) );
NAND2X1TS U3157 ( .A(n2644), .B(n2643), .Y(n3044) );
AOI22X1TS U3158 ( .A0(n1969), .A1(n3043), .B0(n2035), .B1(n3044), .Y(n2645)
);
NAND2X1TS U3159 ( .A(n2645), .B(n3134), .Y(n2967) );
AOI22X1TS U3160 ( .A0(n1949), .A1(n2967), .B0(final_result_ieee[22]), .B1(
n3745), .Y(n2646) );
OAI21XLTS U3161 ( .A0(n1985), .A1(n1951), .B0(n2646), .Y(n1203) );
INVX2TS U3162 ( .A(n2856), .Y(n2836) );
AOI22X1TS U3163 ( .A0(intDX_EWSW[33]), .A1(n2686), .B0(DmP_EXP_EWSW[33]),
.B1(n2812), .Y(n2647) );
OAI21XLTS U3164 ( .A0(n3678), .A1(n2836), .B0(n2647), .Y(n1332) );
INVX2TS U3165 ( .A(n2946), .Y(n2804) );
AOI22X1TS U3166 ( .A0(Data_array_SWR[49]), .A1(n2947), .B0(
Data_array_SWR[41]), .B1(n3014), .Y(n2649) );
AOI22X1TS U3167 ( .A0(Data_array_SWR[45]), .A1(n2994), .B0(
Data_array_SWR[53]), .B1(n2960), .Y(n2648) );
NAND2X1TS U3168 ( .A(n2649), .B(n2648), .Y(n3041) );
AOI22X1TS U3169 ( .A0(Data_array_SWR[33]), .A1(n2825), .B0(
Data_array_SWR[25]), .B1(n2957), .Y(n2650) );
OAI21XLTS U3170 ( .A0(n3895), .A1(n2666), .B0(n2650), .Y(n2651) );
AOI21X1TS U3171 ( .A0(Data_array_SWR[37]), .A1(n3017), .B0(n2651), .Y(n2787)
);
OAI21XLTS U3172 ( .A0(n2787), .A1(n1956), .B0(n3134), .Y(n2652) );
INVX2TS U3173 ( .A(n1949), .Y(n2832) );
INVX2TS U3174 ( .A(n1951), .Y(n2830) );
AOI22X1TS U3175 ( .A0(Data_array_SWR[45]), .A1(n2954), .B0(
Data_array_SWR[53]), .B1(n3015), .Y(n2653) );
AOI22X1TS U3176 ( .A0(Data_array_SWR[37]), .A1(n2825), .B0(
Data_array_SWR[29]), .B1(n3014), .Y(n2655) );
AOI22X1TS U3177 ( .A0(Data_array_SWR[41]), .A1(n2058), .B0(
Data_array_SWR[33]), .B1(n2635), .Y(n2654) );
NAND2X1TS U3178 ( .A(n2655), .B(n2654), .Y(n3034) );
AOI22X1TS U3179 ( .A0(n1969), .A1(n3033), .B0(n2036), .B1(n3034), .Y(n2656)
);
NAND2X1TS U3180 ( .A(n2656), .B(n3134), .Y(n3207) );
AOI22X1TS U3181 ( .A0(n2830), .A1(n3207), .B0(final_result_ieee[27]), .B1(
n3745), .Y(n2657) );
OAI21XLTS U3182 ( .A0(n1986), .A1(n2832), .B0(n2657), .Y(n1204) );
AOI22X1TS U3183 ( .A0(n1949), .A1(n3207), .B0(final_result_ieee[23]), .B1(
n3745), .Y(n2658) );
OAI21XLTS U3184 ( .A0(n1986), .A1(n1951), .B0(n2658), .Y(n1205) );
AOI22X1TS U3185 ( .A0(intDY_EWSW[6]), .A1(n2919), .B0(DmP_EXP_EWSW[6]), .B1(
n2914), .Y(n2659) );
OAI21XLTS U3186 ( .A0(n3701), .A1(n2911), .B0(n2659), .Y(n1386) );
AOI22X1TS U3187 ( .A0(Data_array_SWR[50]), .A1(n3015), .B0(
Data_array_SWR[42]), .B1(n2804), .Y(n2661) );
AOI22X1TS U3188 ( .A0(Data_array_SWR[46]), .A1(n2994), .B0(
Data_array_SWR[54]), .B1(n3007), .Y(n2660) );
AOI22X1TS U3189 ( .A0(Data_array_SWR[34]), .A1(n2947), .B0(
Data_array_SWR[26]), .B1(n2957), .Y(n2662) );
AOI21X1TS U3190 ( .A0(Data_array_SWR[38]), .A1(n2960), .B0(n2663), .Y(n2794)
);
NOR2X1TS U3191 ( .A(n2794), .B(n1956), .Y(n2664) );
AOI211X2TS U3192 ( .A0(n1969), .A1(n3031), .B0(n3058), .C0(n2664), .Y(n2973)
);
AOI22X1TS U3193 ( .A0(Data_array_SWR[44]), .A1(n2954), .B0(
Data_array_SWR[52]), .B1(n2947), .Y(n2665) );
AOI22X1TS U3194 ( .A0(Data_array_SWR[36]), .A1(n2825), .B0(
Data_array_SWR[28]), .B1(n3014), .Y(n2668) );
AOI22X1TS U3195 ( .A0(Data_array_SWR[40]), .A1(n2058), .B0(
Data_array_SWR[32]), .B1(n3016), .Y(n2667) );
NAND2X1TS U3196 ( .A(n2668), .B(n2667), .Y(n3025) );
AOI22X1TS U3197 ( .A0(n1969), .A1(n3024), .B0(n2035), .B1(n3025), .Y(n2669)
);
NAND2X1TS U3198 ( .A(n2669), .B(n3134), .Y(n2969) );
AOI22X1TS U3199 ( .A0(n2830), .A1(n2969), .B0(final_result_ieee[26]), .B1(
n3023), .Y(n2670) );
OAI21XLTS U3200 ( .A0(n2973), .A1(n2832), .B0(n2670), .Y(n1206) );
CLKBUFX2TS U3201 ( .A(n2812), .Y(n2833) );
AOI22X1TS U3202 ( .A0(intDX_EWSW[34]), .A1(n2936), .B0(DmP_EXP_EWSW[34]),
.B1(n2833), .Y(n2671) );
OAI21XLTS U3203 ( .A0(n3877), .A1(n2836), .B0(n2671), .Y(n1330) );
AOI22X1TS U3204 ( .A0(n1949), .A1(n2969), .B0(final_result_ieee[24]), .B1(
n3745), .Y(n2672) );
OAI21XLTS U3205 ( .A0(n2973), .A1(n1951), .B0(n2672), .Y(n1207) );
AOI22X1TS U3206 ( .A0(intDX_EWSW[35]), .A1(n2899), .B0(DmP_EXP_EWSW[35]),
.B1(n2812), .Y(n2673) );
OAI21XLTS U3207 ( .A0(n3663), .A1(n2836), .B0(n2673), .Y(n1328) );
AOI22X1TS U3208 ( .A0(intDY_EWSW[5]), .A1(n2919), .B0(DmP_EXP_EWSW[5]), .B1(
n2872), .Y(n2674) );
OAI21XLTS U3209 ( .A0(n3714), .A1(n2911), .B0(n2674), .Y(n1388) );
INVX2TS U3210 ( .A(n2856), .Y(n2704) );
AOI22X1TS U3211 ( .A0(intDX_EWSW[36]), .A1(n2686), .B0(DmP_EXP_EWSW[36]),
.B1(n2833), .Y(n2675) );
OAI21XLTS U3212 ( .A0(n3836), .A1(n2704), .B0(n2675), .Y(n1326) );
AOI22X1TS U3213 ( .A0(intDX_EWSW[4]), .A1(n2899), .B0(DmP_EXP_EWSW[4]), .B1(
n2914), .Y(n2676) );
OAI21XLTS U3214 ( .A0(n3887), .A1(n2839), .B0(n2676), .Y(n1390) );
AOI22X1TS U3215 ( .A0(intDX_EWSW[37]), .A1(n2936), .B0(DmP_EXP_EWSW[37]),
.B1(n2812), .Y(n2677) );
OAI21XLTS U3216 ( .A0(n3862), .A1(n2704), .B0(n2677), .Y(n1324) );
CLKBUFX3TS U3217 ( .A(n2833), .Y(n2712) );
AOI22X1TS U3218 ( .A0(intDX_EWSW[38]), .A1(n2899), .B0(DmP_EXP_EWSW[38]),
.B1(n2712), .Y(n2678) );
OAI21XLTS U3219 ( .A0(n3890), .A1(n2704), .B0(n2678), .Y(n1322) );
AOI22X1TS U3220 ( .A0(intDX_EWSW[3]), .A1(n2686), .B0(DmP_EXP_EWSW[3]), .B1(
n2872), .Y(n2679) );
OAI21XLTS U3221 ( .A0(n3734), .A1(n2839), .B0(n2679), .Y(n1392) );
AOI22X1TS U3222 ( .A0(intDX_EWSW[39]), .A1(n2686), .B0(DmP_EXP_EWSW[39]),
.B1(n2712), .Y(n2680) );
OAI21XLTS U3223 ( .A0(n3736), .A1(n2704), .B0(n2680), .Y(n1320) );
AOI22X1TS U3224 ( .A0(intDX_EWSW[2]), .A1(n2936), .B0(DmP_EXP_EWSW[2]), .B1(
n2914), .Y(n2681) );
OAI21XLTS U3225 ( .A0(n3874), .A1(n2839), .B0(n2681), .Y(n1394) );
AOI22X1TS U3226 ( .A0(intDX_EWSW[40]), .A1(n2936), .B0(DmP_EXP_EWSW[40]),
.B1(n2712), .Y(n2682) );
OAI21XLTS U3227 ( .A0(n3665), .A1(n2704), .B0(n2682), .Y(n1318) );
AOI22X1TS U3228 ( .A0(intDY_EWSW[1]), .A1(n2919), .B0(DmP_EXP_EWSW[1]), .B1(
n3679), .Y(n2683) );
OAI21XLTS U3229 ( .A0(n3795), .A1(n2911), .B0(n2683), .Y(n1396) );
AOI22X1TS U3230 ( .A0(intDX_EWSW[41]), .A1(n2899), .B0(DmP_EXP_EWSW[41]),
.B1(n2712), .Y(n2684) );
OAI21XLTS U3231 ( .A0(n3672), .A1(n2704), .B0(n2684), .Y(n1316) );
AOI22X1TS U3232 ( .A0(intDY_EWSW[0]), .A1(n2903), .B0(DMP_EXP_EWSW[0]), .B1(
n2868), .Y(n2685) );
OAI21XLTS U3233 ( .A0(n3713), .A1(n3191), .B0(n2685), .Y(n1675) );
AOI22X1TS U3234 ( .A0(intDX_EWSW[42]), .A1(n2686), .B0(DmP_EXP_EWSW[42]),
.B1(n2712), .Y(n2687) );
OAI21XLTS U3235 ( .A0(n3897), .A1(n2704), .B0(n2687), .Y(n1314) );
AOI22X1TS U3236 ( .A0(intDY_EWSW[0]), .A1(n2919), .B0(DmP_EXP_EWSW[0]), .B1(
n3679), .Y(n2688) );
INVX2TS U3237 ( .A(n2724), .Y(n2925) );
CLKBUFX3TS U3238 ( .A(n3679), .Y(n2709) );
AOI22X1TS U3239 ( .A0(intDY_EWSW[1]), .A1(n2710), .B0(DMP_EXP_EWSW[1]), .B1(
n2709), .Y(n2690) );
OAI21XLTS U3240 ( .A0(n3795), .A1(n2925), .B0(n2690), .Y(n1674) );
AOI22X1TS U3241 ( .A0(intDY_EWSW[2]), .A1(n2834), .B0(DMP_EXP_EWSW[2]), .B1(
n2709), .Y(n2691) );
OAI21XLTS U3242 ( .A0(n3744), .A1(n2902), .B0(n2691), .Y(n1673) );
AOI22X1TS U3243 ( .A0(intDX_EWSW[43]), .A1(n2903), .B0(DmP_EXP_EWSW[43]),
.B1(n2712), .Y(n2692) );
OAI21XLTS U3244 ( .A0(n3662), .A1(n2704), .B0(n2692), .Y(n1312) );
AOI22X1TS U3245 ( .A0(intDY_EWSW[3]), .A1(n2923), .B0(DMP_EXP_EWSW[3]), .B1(
n2709), .Y(n2693) );
OAI21XLTS U3246 ( .A0(n3870), .A1(n2902), .B0(n2693), .Y(n1672) );
OAI21XLTS U3247 ( .A0(n3320), .A1(n2696), .B0(n2902), .Y(n2694) );
AOI22X1TS U3248 ( .A0(intDX_EWSW[63]), .A1(n2694), .B0(SIGN_FLAG_EXP), .B1(
n3679), .Y(n2695) );
AOI22X1TS U3249 ( .A0(intDY_EWSW[4]), .A1(n2927), .B0(DMP_EXP_EWSW[4]), .B1(
n2709), .Y(n2698) );
OAI21XLTS U3250 ( .A0(n3859), .A1(n2925), .B0(n2698), .Y(n1671) );
AOI22X1TS U3251 ( .A0(intDY_EWSW[5]), .A1(n2710), .B0(DMP_EXP_EWSW[5]), .B1(
n2709), .Y(n2699) );
AOI22X1TS U3252 ( .A0(intDX_EWSW[44]), .A1(n2903), .B0(DmP_EXP_EWSW[44]),
.B1(n2712), .Y(n2700) );
OAI21XLTS U3253 ( .A0(n3909), .A1(n2704), .B0(n2700), .Y(n1310) );
AOI22X1TS U3254 ( .A0(intDY_EWSW[6]), .A1(n2689), .B0(DMP_EXP_EWSW[6]), .B1(
n2709), .Y(n2701) );
OAI21XLTS U3255 ( .A0(n3701), .A1(n2925), .B0(n2701), .Y(n1669) );
AOI22X1TS U3256 ( .A0(intDY_EWSW[62]), .A1(n2899), .B0(DMP_EXP_EWSW[62]),
.B1(n2907), .Y(n2702) );
OAI21XLTS U3257 ( .A0(n3742), .A1(n2839), .B0(n2702), .Y(n1613) );
AOI22X1TS U3258 ( .A0(intDX_EWSW[45]), .A1(n2903), .B0(DmP_EXP_EWSW[45]),
.B1(n2712), .Y(n2703) );
AOI22X1TS U3259 ( .A0(intDY_EWSW[7]), .A1(n2834), .B0(DMP_EXP_EWSW[7]), .B1(
n2709), .Y(n2705) );
OAI21XLTS U3260 ( .A0(n3871), .A1(n2925), .B0(n2705), .Y(n1668) );
AOI22X1TS U3261 ( .A0(intDY_EWSW[8]), .A1(n2923), .B0(DMP_EXP_EWSW[8]), .B1(
n2709), .Y(n2706) );
OAI21XLTS U3262 ( .A0(n3881), .A1(n2925), .B0(n2706), .Y(n1667) );
AOI22X1TS U3263 ( .A0(intDY_EWSW[9]), .A1(n2927), .B0(DMP_EXP_EWSW[9]), .B1(
n2709), .Y(n2707) );
OAI21XLTS U3264 ( .A0(n3849), .A1(n2925), .B0(n2707), .Y(n1666) );
AOI22X1TS U3265 ( .A0(intDX_EWSW[46]), .A1(n2903), .B0(DmP_EXP_EWSW[46]),
.B1(n2712), .Y(n2708) );
OAI21XLTS U3266 ( .A0(n3668), .A1(n3191), .B0(n2708), .Y(n1306) );
AOI22X1TS U3267 ( .A0(intDY_EWSW[10]), .A1(n2710), .B0(DMP_EXP_EWSW[10]),
.B1(n2709), .Y(n2711) );
OAI21XLTS U3268 ( .A0(n3823), .A1(n2925), .B0(n2711), .Y(n1665) );
AOI22X1TS U3269 ( .A0(intDX_EWSW[47]), .A1(n2903), .B0(DmP_EXP_EWSW[47]),
.B1(n2712), .Y(n2713) );
OAI21XLTS U3270 ( .A0(n3800), .A1(n3191), .B0(n2713), .Y(n1304) );
AOI22X1TS U3271 ( .A0(n2830), .A1(n2967), .B0(final_result_ieee[28]), .B1(
n3745), .Y(n2714) );
OAI21XLTS U3272 ( .A0(n1985), .A1(n2832), .B0(n2714), .Y(n1202) );
CLKBUFX3TS U3273 ( .A(n2872), .Y(n2754) );
AOI22X1TS U3274 ( .A0(intDY_EWSW[18]), .A1(n2856), .B0(DmP_EXP_EWSW[18]),
.B1(n2754), .Y(n2715) );
OAI21XLTS U3275 ( .A0(n3710), .A1(n3192), .B0(n2715), .Y(n1362) );
CLKBUFX3TS U3276 ( .A(n2872), .Y(n2814) );
AOI22X1TS U3277 ( .A0(intDY_EWSW[17]), .A1(n2909), .B0(DmP_EXP_EWSW[17]),
.B1(n2814), .Y(n2716) );
OAI21XLTS U3278 ( .A0(n3797), .A1(n2911), .B0(n2716), .Y(n1364) );
INVX2TS U3279 ( .A(n2856), .Y(n2753) );
AOI22X1TS U3280 ( .A0(intDX_EWSW[19]), .A1(n2815), .B0(DmP_EXP_EWSW[19]),
.B1(n2754), .Y(n2717) );
OAI21XLTS U3281 ( .A0(n3835), .A1(n2753), .B0(n2717), .Y(n1360) );
AOI22X1TS U3282 ( .A0(intDX_EWSW[20]), .A1(n2815), .B0(DmP_EXP_EWSW[20]),
.B1(n2754), .Y(n2718) );
OAI21XLTS U3283 ( .A0(n3907), .A1(n2753), .B0(n2718), .Y(n1358) );
AOI22X1TS U3284 ( .A0(intDY_EWSW[16]), .A1(n2724), .B0(DmP_EXP_EWSW[16]),
.B1(n2814), .Y(n2719) );
OAI21XLTS U3285 ( .A0(n3834), .A1(n2911), .B0(n2719), .Y(n1366) );
AOI22X1TS U3286 ( .A0(intDX_EWSW[21]), .A1(n2815), .B0(DmP_EXP_EWSW[21]),
.B1(n2754), .Y(n2720) );
OAI21XLTS U3287 ( .A0(n3880), .A1(n2753), .B0(n2720), .Y(n1356) );
AOI22X1TS U3288 ( .A0(intDY_EWSW[15]), .A1(n2909), .B0(DmP_EXP_EWSW[15]),
.B1(n2814), .Y(n2721) );
INVX2TS U3289 ( .A(n2921), .Y(n2834) );
AOI22X1TS U3290 ( .A0(intDX_EWSW[22]), .A1(n2710), .B0(DmP_EXP_EWSW[22]),
.B1(n2754), .Y(n2722) );
OAI21XLTS U3291 ( .A0(n3908), .A1(n2753), .B0(n2722), .Y(n1354) );
AOI22X1TS U3292 ( .A0(intDX_EWSW[14]), .A1(n2815), .B0(DmP_EXP_EWSW[14]),
.B1(n2814), .Y(n2723) );
OAI21XLTS U3293 ( .A0(n3851), .A1(n2753), .B0(n2723), .Y(n1370) );
AOI22X1TS U3294 ( .A0(intDY_EWSW[23]), .A1(n2724), .B0(DmP_EXP_EWSW[23]),
.B1(n2754), .Y(n2725) );
OAI21XLTS U3295 ( .A0(n3680), .A1(n2911), .B0(n2725), .Y(n1352) );
AOI22X1TS U3296 ( .A0(intDX_EWSW[24]), .A1(n2689), .B0(DmP_EXP_EWSW[24]),
.B1(n2754), .Y(n2726) );
OAI21XLTS U3297 ( .A0(n3763), .A1(n2753), .B0(n2726), .Y(n1350) );
NAND2X1TS U3298 ( .A(LZD_output_NRM2_EW[5]), .B(n3749), .Y(n2727) );
OAI21XLTS U3299 ( .A0(n2030), .A1(n3749), .B0(n2727), .Y(n1209) );
AOI22X1TS U3300 ( .A0(intDX_EWSW[13]), .A1(n2815), .B0(DmP_EXP_EWSW[13]),
.B1(n2814), .Y(n2729) );
OAI21XLTS U3301 ( .A0(n3863), .A1(n2753), .B0(n2729), .Y(n1372) );
NAND2X1TS U3302 ( .A(LZD_output_NRM2_EW[4]), .B(n3749), .Y(n2730) );
OAI21XLTS U3303 ( .A0(n2731), .A1(n3749), .B0(n2730), .Y(n1211) );
NAND2X1TS U3304 ( .A(LZD_output_NRM2_EW[3]), .B(n3749), .Y(n2732) );
OAI21XLTS U3305 ( .A0(n2733), .A1(n3749), .B0(n2732), .Y(n1213) );
AOI22X1TS U3306 ( .A0(intDX_EWSW[25]), .A1(n2834), .B0(DmP_EXP_EWSW[25]),
.B1(n2754), .Y(n2734) );
OAI21XLTS U3307 ( .A0(n3687), .A1(n2753), .B0(n2734), .Y(n1348) );
NAND2X1TS U3308 ( .A(LZD_output_NRM2_EW[2]), .B(n3749), .Y(n2735) );
OAI21XLTS U3309 ( .A0(n2736), .A1(n3749), .B0(n2735), .Y(n1214) );
AOI22X1TS U3310 ( .A0(intDX_EWSW[12]), .A1(n2815), .B0(DmP_EXP_EWSW[12]),
.B1(n2814), .Y(n2737) );
OAI21XLTS U3311 ( .A0(n3833), .A1(n2753), .B0(n2737), .Y(n1374) );
AOI22X1TS U3312 ( .A0(intDX_EWSW[26]), .A1(n2923), .B0(DmP_EXP_EWSW[26]),
.B1(n2754), .Y(n2738) );
OAI21XLTS U3313 ( .A0(n3715), .A1(n2836), .B0(n2738), .Y(n1346) );
CLKBUFX3TS U3314 ( .A(n3136), .Y(n2829) );
AOI22X1TS U3315 ( .A0(n2830), .A1(n2739), .B0(final_result_ieee[51]), .B1(
n2829), .Y(n2740) );
OAI21XLTS U3316 ( .A0(n1970), .A1(n2832), .B0(n2740), .Y(n1157) );
AOI22X1TS U3317 ( .A0(Data_array_SWR[18]), .A1(n2954), .B0(
Data_array_SWR[26]), .B1(n3015), .Y(n2741) );
AOI22X1TS U3318 ( .A0(Data_array_SWR[14]), .A1(n1961), .B0(Data_array_SWR[6]), .B1(n1963), .Y(n2744) );
AOI22X1TS U3319 ( .A0(Data_array_SWR[10]), .A1(n1965), .B0(Data_array_SWR[2]), .B1(n1967), .Y(n2743) );
AOI22X1TS U3320 ( .A0(Data_array_SWR[50]), .A1(n2954), .B0(
Data_array_SWR[54]), .B1(n2994), .Y(n2745) );
NAND2X2TS U3321 ( .A(n2745), .B(n2955), .Y(n3089) );
INVX2TS U3322 ( .A(n3089), .Y(n3081) );
AOI22X1TS U3323 ( .A0(Data_array_SWR[42]), .A1(n2947), .B0(
Data_array_SWR[34]), .B1(n2957), .Y(n2746) );
OAI2BB1X1TS U3324 ( .A0N(Data_array_SWR[38]), .A1N(n2635), .B0(n2746), .Y(
n2747) );
AOI21X2TS U3325 ( .A0(Data_array_SWR[46]), .A1(n3017), .B0(n2747), .Y(n3096)
);
OAI22X1TS U3326 ( .A0(n3081), .A1(n3012), .B0(n3096), .B1(n2961), .Y(n2748)
);
NOR2X2TS U3327 ( .A(n2749), .B(n2748), .Y(n2979) );
CLKBUFX3TS U3328 ( .A(n3023), .Y(n3324) );
AOI22X1TS U3329 ( .A0(n2830), .A1(n1979), .B0(final_result_ieee[50]), .B1(
n3324), .Y(n2750) );
OAI21XLTS U3330 ( .A0(n2979), .A1(n2832), .B0(n2750), .Y(n1158) );
AOI22X1TS U3331 ( .A0(n1949), .A1(n1979), .B0(final_result_ieee[0]), .B1(
n3324), .Y(n2751) );
AOI22X1TS U3332 ( .A0(intDX_EWSW[11]), .A1(n2815), .B0(DmP_EXP_EWSW[11]),
.B1(n2814), .Y(n2752) );
OAI21XLTS U3333 ( .A0(n3753), .A1(n2753), .B0(n2752), .Y(n1376) );
AOI22X1TS U3334 ( .A0(intDX_EWSW[27]), .A1(n2927), .B0(DmP_EXP_EWSW[27]),
.B1(n2754), .Y(n2755) );
OAI21XLTS U3335 ( .A0(n3861), .A1(n2836), .B0(n2755), .Y(n1344) );
CLKAND2X2TS U3336 ( .A(Data_array_SWR[15]), .B(n1962), .Y(n2764) );
AOI22X1TS U3337 ( .A0(Data_array_SWR[11]), .A1(n1965), .B0(Data_array_SWR[3]), .B1(n1967), .Y(n2762) );
AOI22X1TS U3338 ( .A0(Data_array_SWR[19]), .A1(n2954), .B0(
Data_array_SWR[27]), .B1(n2947), .Y(n2758) );
AOI22X1TS U3339 ( .A0(Data_array_SWR[31]), .A1(n2058), .B0(
Data_array_SWR[23]), .B1(n2994), .Y(n2757) );
NAND2X1TS U3340 ( .A(n2758), .B(n2757), .Y(n2817) );
AOI22X1TS U3341 ( .A0(Data_array_SWR[43]), .A1(n3015), .B0(
Data_array_SWR[35]), .B1(n3014), .Y(n2760) );
AOI22X1TS U3342 ( .A0(Data_array_SWR[47]), .A1(n3017), .B0(
Data_array_SWR[39]), .B1(n2994), .Y(n2759) );
NAND2X1TS U3343 ( .A(n2760), .B(n2759), .Y(n2818) );
AOI22X1TS U3344 ( .A0(n1969), .A1(n2817), .B0(n1959), .B1(n2818), .Y(n2761)
);
OAI211X1TS U3345 ( .A0(n3012), .A1(n2820), .B0(n2762), .C0(n2761), .Y(n2763)
);
AOI211X2TS U3346 ( .A0(n1963), .A1(Data_array_SWR[7]), .B0(n2764), .C0(n2763), .Y(n3222) );
AOI22X1TS U3347 ( .A0(n2830), .A1(n3199), .B0(final_result_ieee[49]), .B1(
n3324), .Y(n2766) );
OAI21XLTS U3348 ( .A0(n3222), .A1(n2832), .B0(n2766), .Y(n1160) );
AOI22X1TS U3349 ( .A0(n1949), .A1(n3199), .B0(final_result_ieee[1]), .B1(
n3324), .Y(n2767) );
OAI21XLTS U3350 ( .A0(n3222), .A1(n1951), .B0(n2767), .Y(n1161) );
AOI22X1TS U3351 ( .A0(Data_array_SWR[51]), .A1(n2994), .B0(
Data_array_SWR[47]), .B1(n2804), .Y(n2768) );
NAND2X1TS U3352 ( .A(n2768), .B(n2955), .Y(n2982) );
AOI22X1TS U3353 ( .A0(Data_array_SWR[19]), .A1(n1961), .B0(Data_array_SWR[7]), .B1(n1967), .Y(n2775) );
AOI22X1TS U3354 ( .A0(Data_array_SWR[15]), .A1(n1965), .B0(
Data_array_SWR[11]), .B1(n1963), .Y(n2774) );
AOI22X1TS U3355 ( .A0(Data_array_SWR[47]), .A1(n2825), .B0(
Data_array_SWR[39]), .B1(n2957), .Y(n2770) );
AOI22X1TS U3356 ( .A0(Data_array_SWR[51]), .A1(n2058), .B0(
Data_array_SWR[43]), .B1(n2635), .Y(n2769) );
NAND2X1TS U3357 ( .A(n2770), .B(n2769), .Y(n3054) );
AOI22X1TS U3358 ( .A0(Data_array_SWR[31]), .A1(n2825), .B0(
Data_array_SWR[23]), .B1(n3014), .Y(n2771) );
OAI2BB1X1TS U3359 ( .A0N(Data_array_SWR[27]), .A1N(n3016), .B0(n2771), .Y(
n2772) );
AOI21X1TS U3360 ( .A0(Data_array_SWR[35]), .A1(n2960), .B0(n2772), .Y(n2823)
);
AOI2BB2XLTS U3361 ( .B0(n1960), .B1(n3054), .A0N(n2823), .A1N(n1948), .Y(
n2773) );
NAND4X1TS U3362 ( .A(n2775), .B(n2774), .C(n2773), .D(n1981), .Y(n3200) );
AOI22X1TS U3363 ( .A0(n1950), .A1(n3200), .B0(final_result_ieee[45]), .B1(
n3324), .Y(n2776) );
OAI21XLTS U3364 ( .A0(n3217), .A1(n1952), .B0(n2776), .Y(n1168) );
AOI22X1TS U3365 ( .A0(intDX_EWSW[28]), .A1(n2710), .B0(DmP_EXP_EWSW[28]),
.B1(n2833), .Y(n2777) );
OAI21XLTS U3366 ( .A0(n3889), .A1(n2836), .B0(n2777), .Y(n1342) );
AOI22X1TS U3367 ( .A0(n2830), .A1(n3200), .B0(final_result_ieee[5]), .B1(
n3324), .Y(n2778) );
OAI21XLTS U3368 ( .A0(n3217), .A1(n2832), .B0(n2778), .Y(n1169) );
AOI22X1TS U3369 ( .A0(intDX_EWSW[10]), .A1(n2815), .B0(DmP_EXP_EWSW[10]),
.B1(n2814), .Y(n2779) );
OAI21XLTS U3370 ( .A0(n3728), .A1(n2839), .B0(n2779), .Y(n1378) );
AOI22X1TS U3371 ( .A0(Data_array_SWR[20]), .A1(n1961), .B0(Data_array_SWR[8]), .B1(n1968), .Y(n2783) );
AOI22X1TS U3372 ( .A0(Data_array_SWR[16]), .A1(n1965), .B0(
Data_array_SWR[12]), .B1(n1963), .Y(n2782) );
AOI2BB2XLTS U3373 ( .B0(n1960), .B1(n3051), .A0N(n2780), .A1N(n1948), .Y(
n2781) );
NAND4X1TS U3374 ( .A(n2783), .B(n2782), .C(n2781), .D(n1981), .Y(n2970) );
AOI22X1TS U3375 ( .A0(n1950), .A1(n2970), .B0(final_result_ieee[44]), .B1(
n3324), .Y(n2784) );
OAI21XLTS U3376 ( .A0(n2977), .A1(n1952), .B0(n2784), .Y(n1170) );
AOI22X1TS U3377 ( .A0(n1940), .A1(n2970), .B0(final_result_ieee[6]), .B1(
n3324), .Y(n2785) );
OAI21XLTS U3378 ( .A0(n2977), .A1(n2034), .B0(n2785), .Y(n1171) );
AOI22X1TS U3379 ( .A0(intDX_EWSW[29]), .A1(n2689), .B0(DmP_EXP_EWSW[29]),
.B1(n2833), .Y(n2786) );
OAI21XLTS U3380 ( .A0(n3752), .A1(n2836), .B0(n2786), .Y(n1340) );
AOI22X1TS U3381 ( .A0(Data_array_SWR[21]), .A1(n1961), .B0(Data_array_SWR[9]), .B1(n1968), .Y(n2790) );
AOI22X1TS U3382 ( .A0(Data_array_SWR[17]), .A1(n1965), .B0(
Data_array_SWR[13]), .B1(n1963), .Y(n2789) );
AOI2BB2XLTS U3383 ( .B0(n1960), .B1(n3041), .A0N(n2787), .A1N(n2953), .Y(
n2788) );
NAND4X1TS U3384 ( .A(n2790), .B(n2789), .C(n2788), .D(n1981), .Y(n3201) );
AOI22X1TS U3385 ( .A0(n1950), .A1(n3201), .B0(final_result_ieee[43]), .B1(
n2829), .Y(n2791) );
OAI21XLTS U3386 ( .A0(n3214), .A1(n1952), .B0(n2791), .Y(n1172) );
AOI22X1TS U3387 ( .A0(intDX_EWSW[9]), .A1(n2815), .B0(DmP_EXP_EWSW[9]), .B1(
n2814), .Y(n2792) );
OAI21XLTS U3388 ( .A0(n3875), .A1(n2839), .B0(n2792), .Y(n1380) );
AOI22X1TS U3389 ( .A0(n1940), .A1(n3201), .B0(final_result_ieee[7]), .B1(
n2829), .Y(n2793) );
OAI21XLTS U3390 ( .A0(n3214), .A1(n2034), .B0(n2793), .Y(n1173) );
AOI22X1TS U3391 ( .A0(Data_array_SWR[22]), .A1(n1961), .B0(
Data_array_SWR[10]), .B1(n1968), .Y(n2797) );
AOI22X1TS U3392 ( .A0(Data_array_SWR[18]), .A1(n1965), .B0(
Data_array_SWR[14]), .B1(n1963), .Y(n2796) );
AOI2BB2XLTS U3393 ( .B0(n1960), .B1(n3031), .A0N(n2794), .A1N(n1948), .Y(
n2795) );
NAND4X1TS U3394 ( .A(n2797), .B(n2796), .C(n2795), .D(n1981), .Y(n2966) );
AOI22X1TS U3395 ( .A0(n1950), .A1(n2966), .B0(final_result_ieee[42]), .B1(
n2829), .Y(n2798) );
OAI21XLTS U3396 ( .A0(n2975), .A1(n1952), .B0(n2798), .Y(n1174) );
AOI22X1TS U3397 ( .A0(intDX_EWSW[30]), .A1(n2834), .B0(DmP_EXP_EWSW[30]),
.B1(n2833), .Y(n2799) );
AOI22X1TS U3398 ( .A0(n1940), .A1(n2966), .B0(final_result_ieee[8]), .B1(
n2829), .Y(n2800) );
OAI21XLTS U3399 ( .A0(n2975), .A1(n2034), .B0(n2800), .Y(n1175) );
AOI22X1TS U3400 ( .A0(Data_array_SWR[47]), .A1(n2994), .B0(
Data_array_SWR[43]), .B1(n2804), .Y(n2802) );
OAI211X1TS U3401 ( .A0(n2803), .A1(n3920), .B0(n2802), .C0(n2801), .Y(n3133)
);
AOI22X1TS U3402 ( .A0(Data_array_SWR[23]), .A1(n1961), .B0(
Data_array_SWR[11]), .B1(n1968), .Y(n2809) );
AOI22X1TS U3403 ( .A0(Data_array_SWR[19]), .A1(n1965), .B0(
Data_array_SWR[15]), .B1(n1963), .Y(n2808) );
AOI22X1TS U3404 ( .A0(Data_array_SWR[35]), .A1(n2825), .B0(
Data_array_SWR[27]), .B1(n2804), .Y(n2806) );
AOI22X1TS U3405 ( .A0(Data_array_SWR[39]), .A1(n3017), .B0(
Data_array_SWR[31]), .B1(n2994), .Y(n2805) );
NAND2X1TS U3406 ( .A(n2806), .B(n2805), .Y(n3131) );
AOI22X1TS U3407 ( .A0(n1969), .A1(n3131), .B0(n1959), .B1(n1983), .Y(n2807)
);
NAND4X1TS U3408 ( .A(n2809), .B(n2808), .C(n2807), .D(n1981), .Y(n3203) );
AOI22X1TS U3409 ( .A0(n1950), .A1(n3203), .B0(final_result_ieee[41]), .B1(
n2829), .Y(n2810) );
OAI21XLTS U3410 ( .A0(n3211), .A1(n1952), .B0(n2810), .Y(n1176) );
AOI22X1TS U3411 ( .A0(n1940), .A1(n3203), .B0(final_result_ieee[9]), .B1(
n2829), .Y(n2811) );
OAI21XLTS U3412 ( .A0(n3211), .A1(n2034), .B0(n2811), .Y(n1177) );
AOI22X1TS U3413 ( .A0(intDX_EWSW[31]), .A1(n2923), .B0(DmP_EXP_EWSW[31]),
.B1(n2812), .Y(n2813) );
OAI21XLTS U3414 ( .A0(n3681), .A1(n2836), .B0(n2813), .Y(n1336) );
AOI22X1TS U3415 ( .A0(intDX_EWSW[8]), .A1(n2815), .B0(DmP_EXP_EWSW[8]), .B1(
n2814), .Y(n2816) );
OAI21XLTS U3416 ( .A0(n3888), .A1(n2839), .B0(n2816), .Y(n1382) );
AOI22X1TS U3417 ( .A0(n1969), .A1(n2818), .B0(n2036), .B1(n2817), .Y(n2819)
);
AOI22X1TS U3418 ( .A0(n1950), .A1(n3176), .B0(final_result_ieee[33]), .B1(
n2829), .Y(n2821) );
OAI21XLTS U3419 ( .A0(n3204), .A1(n1952), .B0(n2821), .Y(n1192) );
AOI22X1TS U3420 ( .A0(n1940), .A1(n3176), .B0(final_result_ieee[17]), .B1(
n2829), .Y(n2822) );
OAI21XLTS U3421 ( .A0(n3204), .A1(n2034), .B0(n2822), .Y(n1193) );
AOI22X1TS U3422 ( .A0(Data_array_SWR[39]), .A1(n2825), .B0(
Data_array_SWR[31]), .B1(n2804), .Y(n2827) );
AOI22X1TS U3423 ( .A0(Data_array_SWR[43]), .A1(n3007), .B0(
Data_array_SWR[35]), .B1(n3016), .Y(n2826) );
NAND2X1TS U3424 ( .A(n2827), .B(n2826), .Y(n2983) );
AOI22X1TS U3425 ( .A0(n1969), .A1(n2982), .B0(n2035), .B1(n2983), .Y(n2828)
);
NAND2X1TS U3426 ( .A(n2828), .B(n3134), .Y(n3206) );
AOI22X1TS U3427 ( .A0(n2830), .A1(n3206), .B0(final_result_ieee[29]), .B1(
n2829), .Y(n2831) );
AOI22X1TS U3428 ( .A0(intDX_EWSW[32]), .A1(n2927), .B0(DmP_EXP_EWSW[32]),
.B1(n2833), .Y(n2835) );
OAI21XLTS U3429 ( .A0(n3748), .A1(n2836), .B0(n2835), .Y(n1334) );
AOI22X1TS U3430 ( .A0(n1950), .A1(n3206), .B0(final_result_ieee[21]), .B1(
n3023), .Y(n2837) );
OAI21XLTS U3431 ( .A0(n1987), .A1(n1952), .B0(n2837), .Y(n1201) );
AOI22X1TS U3432 ( .A0(intDX_EWSW[7]), .A1(n2686), .B0(DmP_EXP_EWSW[7]), .B1(
n2907), .Y(n2838) );
OAI21XLTS U3433 ( .A0(n3758), .A1(n2839), .B0(n2838), .Y(n1384) );
INVX2TS U3434 ( .A(n2921), .Y(n2923) );
AOI22X1TS U3435 ( .A0(intDY_EWSW[12]), .A1(n2710), .B0(DMP_EXP_EWSW[12]),
.B1(n2907), .Y(n2840) );
OAI21XLTS U3436 ( .A0(n3882), .A1(n2925), .B0(n2840), .Y(n1663) );
CLKBUFX3TS U3437 ( .A(n2868), .Y(n2926) );
AOI22X1TS U3438 ( .A0(intDX_EWSW[35]), .A1(n2919), .B0(DMP_EXP_EWSW[35]),
.B1(n2926), .Y(n2841) );
OAI21XLTS U3439 ( .A0(n3663), .A1(n2921), .B0(n2841), .Y(n1640) );
INVX2TS U3440 ( .A(n2909), .Y(n2917) );
INVX2TS U3441 ( .A(n2921), .Y(n2927) );
AOI22X1TS U3442 ( .A0(intDY_EWSW[23]), .A1(n2710), .B0(DMP_EXP_EWSW[23]),
.B1(n2907), .Y(n2842) );
OAI21XLTS U3443 ( .A0(n3680), .A1(n2917), .B0(n2842), .Y(n1652) );
AOI22X1TS U3444 ( .A0(intDX_EWSW[24]), .A1(n2932), .B0(DMP_EXP_EWSW[24]),
.B1(n3679), .Y(n2843) );
OAI21XLTS U3445 ( .A0(n3763), .A1(n3192), .B0(n2843), .Y(n1651) );
AOI22X1TS U3446 ( .A0(Raw_mant_NRM_SWR[51]), .A1(n2845), .B0(
DmP_mant_SHT1_SW[1]), .B1(n2844), .Y(n2846) );
AOI22X1TS U3447 ( .A0(Raw_mant_NRM_SWR[54]), .A1(n2603), .B0(n2407), .B1(
Data_array_SWR[0]), .Y(n2855) );
AOI22X1TS U3448 ( .A0(n2849), .A1(Raw_mant_NRM_SWR[2]), .B0(
DmP_mant_SHT1_SW[0]), .B1(n2038), .Y(n2850) );
OAI22X1TS U3449 ( .A0(n3855), .A1(n2852), .B0(n3669), .B1(n3317), .Y(n2889)
);
AOI21X1TS U3450 ( .A0(n2853), .A1(n2891), .B0(n2889), .Y(n2854) );
OAI211XLTS U3451 ( .A0(n1927), .A1(n2896), .B0(n2855), .C0(n2854), .Y(n1698)
);
INVX2TS U3452 ( .A(n2856), .Y(n2929) );
AOI22X1TS U3453 ( .A0(intDY_EWSW[22]), .A1(n2689), .B0(DMP_EXP_EWSW[22]),
.B1(n2922), .Y(n2857) );
OAI21XLTS U3454 ( .A0(n3873), .A1(n2929), .B0(n2857), .Y(n1653) );
AOI22X1TS U3455 ( .A0(intDY_EWSW[36]), .A1(n2834), .B0(DMP_EXP_EWSW[36]),
.B1(n2926), .Y(n2858) );
OAI21XLTS U3456 ( .A0(n3900), .A1(n2929), .B0(n2858), .Y(n1639) );
AOI22X1TS U3457 ( .A0(n2942), .A1(Data_array_SWR[3]), .B0(n2577), .B1(n2017),
.Y(n2860) );
AOI22X1TS U3458 ( .A0(n2893), .A1(n2004), .B0(n2892), .B1(n2888), .Y(n2859)
);
OAI211XLTS U3459 ( .A0(n1915), .A1(n2896), .B0(n2860), .C0(n2859), .Y(n1701)
);
AOI22X1TS U3460 ( .A0(intDX_EWSW[51]), .A1(n2932), .B0(DMP_EXP_EWSW[51]),
.B1(n2918), .Y(n2861) );
OAI21XLTS U3461 ( .A0(n3664), .A1(n2885), .B0(n2861), .Y(n1624) );
AOI22X1TS U3462 ( .A0(intDY_EWSW[34]), .A1(n2923), .B0(DMP_EXP_EWSW[34]),
.B1(n2926), .Y(n2862) );
OAI21XLTS U3463 ( .A0(n3884), .A1(n2929), .B0(n2862), .Y(n1641) );
AOI22X1TS U3464 ( .A0(intDY_EWSW[21]), .A1(n2689), .B0(DMP_EXP_EWSW[21]),
.B1(n2922), .Y(n2863) );
OAI21XLTS U3465 ( .A0(n3757), .A1(n2917), .B0(n2863), .Y(n1654) );
CLKBUFX3TS U3466 ( .A(n2868), .Y(n2935) );
AOI22X1TS U3467 ( .A0(intDY_EWSW[47]), .A1(n2899), .B0(DMP_EXP_EWSW[47]),
.B1(n2935), .Y(n2864) );
OAI21XLTS U3468 ( .A0(n3840), .A1(n2902), .B0(n2864), .Y(n1628) );
AOI22X1TS U3469 ( .A0(intDX_EWSW[46]), .A1(n2919), .B0(DMP_EXP_EWSW[46]),
.B1(n2935), .Y(n2865) );
OAI21XLTS U3470 ( .A0(n3668), .A1(n2921), .B0(n2865), .Y(n1629) );
AOI22X1TS U3471 ( .A0(intDY_EWSW[37]), .A1(n2927), .B0(DMP_EXP_EWSW[37]),
.B1(n2926), .Y(n2866) );
OAI21XLTS U3472 ( .A0(n3850), .A1(n2929), .B0(n2866), .Y(n1638) );
AOI22X1TS U3473 ( .A0(intDY_EWSW[50]), .A1(n2686), .B0(DMP_EXP_EWSW[50]),
.B1(n2935), .Y(n2867) );
OAI21XLTS U3474 ( .A0(n3886), .A1(n2938), .B0(n2867), .Y(n1625) );
AOI22X1TS U3475 ( .A0(intDX_EWSW[25]), .A1(n2932), .B0(DMP_EXP_EWSW[25]),
.B1(n2868), .Y(n2869) );
OAI21XLTS U3476 ( .A0(n3687), .A1(n2934), .B0(n2869), .Y(n1650) );
AOI22X1TS U3477 ( .A0(intDX_EWSW[51]), .A1(n2903), .B0(DmP_EXP_EWSW[51]),
.B1(n3320), .Y(n2870) );
OAI21XLTS U3478 ( .A0(n3664), .A1(n3191), .B0(n2870), .Y(n1296) );
AOI22X1TS U3479 ( .A0(intDX_EWSW[26]), .A1(n2932), .B0(DMP_EXP_EWSW[26]),
.B1(n2922), .Y(n2871) );
OAI21XLTS U3480 ( .A0(n3715), .A1(n2885), .B0(n2871), .Y(n1649) );
AOI22X1TS U3481 ( .A0(intDY_EWSW[20]), .A1(n2834), .B0(DMP_EXP_EWSW[20]),
.B1(n2872), .Y(n2873) );
OAI21XLTS U3482 ( .A0(n3904), .A1(n2917), .B0(n2873), .Y(n1655) );
AOI22X1TS U3483 ( .A0(intDY_EWSW[38]), .A1(n2936), .B0(DMP_EXP_EWSW[38]),
.B1(n2926), .Y(n2874) );
OAI21XLTS U3484 ( .A0(n3806), .A1(n2929), .B0(n2874), .Y(n1637) );
AOI22X1TS U3485 ( .A0(intDY_EWSW[19]), .A1(n2923), .B0(DMP_EXP_EWSW[19]),
.B1(n2907), .Y(n2875) );
OAI21XLTS U3486 ( .A0(n3801), .A1(n2917), .B0(n2875), .Y(n1656) );
AOI22X1TS U3487 ( .A0(intDX_EWSW[33]), .A1(n2932), .B0(DMP_EXP_EWSW[33]),
.B1(n2926), .Y(n2876) );
OAI21XLTS U3488 ( .A0(n3678), .A1(n2885), .B0(n2876), .Y(n1642) );
AOI22X1TS U3489 ( .A0(intDY_EWSW[58]), .A1(n2936), .B0(DMP_EXP_EWSW[58]),
.B1(n2918), .Y(n2877) );
OAI21XLTS U3490 ( .A0(n3853), .A1(n2902), .B0(n2877), .Y(n1617) );
AOI22X1TS U3491 ( .A0(intDY_EWSW[39]), .A1(n2899), .B0(DMP_EXP_EWSW[39]),
.B1(n2926), .Y(n2878) );
OAI21XLTS U3492 ( .A0(n3906), .A1(n2929), .B0(n2878), .Y(n1636) );
AOI22X1TS U3493 ( .A0(n2942), .A1(Data_array_SWR[2]), .B0(n2628), .B1(n2891),
.Y(n2880) );
AOI22X1TS U3494 ( .A0(n2893), .A1(n2888), .B0(n2892), .B1(n2017), .Y(n2879)
);
OAI211XLTS U3495 ( .A0(n1914), .A1(n2896), .B0(n2880), .C0(n2879), .Y(n1700)
);
AOI22X1TS U3496 ( .A0(intDY_EWSW[18]), .A1(n2927), .B0(DMP_EXP_EWSW[18]),
.B1(n2907), .Y(n2881) );
AOI22X1TS U3497 ( .A0(intDY_EWSW[27]), .A1(n2710), .B0(DMP_EXP_EWSW[27]),
.B1(n2922), .Y(n2882) );
OAI21XLTS U3498 ( .A0(n3706), .A1(n2917), .B0(n2882), .Y(n1648) );
AOI22X1TS U3499 ( .A0(intDY_EWSW[45]), .A1(n2686), .B0(DMP_EXP_EWSW[45]),
.B1(n2935), .Y(n2883) );
OAI21XLTS U3500 ( .A0(n3807), .A1(n2938), .B0(n2883), .Y(n1630) );
AOI22X1TS U3501 ( .A0(intDX_EWSW[40]), .A1(n2932), .B0(DMP_EXP_EWSW[40]),
.B1(n2926), .Y(n2884) );
OAI21XLTS U3502 ( .A0(n3665), .A1(n2885), .B0(n2884), .Y(n1635) );
AOI22X1TS U3503 ( .A0(intDY_EWSW[17]), .A1(n2710), .B0(DMP_EXP_EWSW[17]),
.B1(n2922), .Y(n2886) );
OAI21XLTS U3504 ( .A0(n3797), .A1(n2917), .B0(n2886), .Y(n1658) );
AOI22X1TS U3505 ( .A0(intDX_EWSW[50]), .A1(n2903), .B0(DmP_EXP_EWSW[50]),
.B1(n3320), .Y(n2887) );
OAI21XLTS U3506 ( .A0(n3876), .A1(n3191), .B0(n2887), .Y(n1298) );
INVX2TS U3507 ( .A(n2888), .Y(n2897) );
AOI22X1TS U3508 ( .A0(n2942), .A1(Data_array_SWR[1]), .B0(n2941), .B1(n2889),
.Y(n2895) );
AOI22X1TS U3509 ( .A0(n2893), .A1(n2017), .B0(n2568), .B1(n2891), .Y(n2894)
);
OAI211XLTS U3510 ( .A0(n2897), .A1(n2896), .B0(n2895), .C0(n2894), .Y(n1699)
);
AOI22X1TS U3511 ( .A0(intDX_EWSW[32]), .A1(n2932), .B0(DMP_EXP_EWSW[32]),
.B1(n2926), .Y(n2898) );
OAI21XLTS U3512 ( .A0(n3748), .A1(n2934), .B0(n2898), .Y(n1643) );
AOI22X1TS U3513 ( .A0(intDY_EWSW[60]), .A1(n2899), .B0(DMP_EXP_EWSW[60]),
.B1(n2918), .Y(n2900) );
OAI21XLTS U3514 ( .A0(n3799), .A1(n2938), .B0(n2900), .Y(n1615) );
AOI22X1TS U3515 ( .A0(intDY_EWSW[49]), .A1(n2936), .B0(DMP_EXP_EWSW[49]),
.B1(n2935), .Y(n2901) );
OAI21XLTS U3516 ( .A0(n3798), .A1(n2902), .B0(n2901), .Y(n1626) );
AOI22X1TS U3517 ( .A0(intDX_EWSW[48]), .A1(n2903), .B0(DmP_EXP_EWSW[48]),
.B1(n3320), .Y(n2904) );
OAI21XLTS U3518 ( .A0(n3824), .A1(n3191), .B0(n2904), .Y(n1302) );
AOI22X1TS U3519 ( .A0(intDY_EWSW[28]), .A1(n2689), .B0(DMP_EXP_EWSW[28]),
.B1(n2907), .Y(n2905) );
OAI21XLTS U3520 ( .A0(n3883), .A1(n2929), .B0(n2905), .Y(n1647) );
AOI22X1TS U3521 ( .A0(intDY_EWSW[29]), .A1(n2834), .B0(DMP_EXP_EWSW[29]),
.B1(n2907), .Y(n2906) );
OAI21XLTS U3522 ( .A0(n3905), .A1(n2929), .B0(n2906), .Y(n1646) );
AOI22X1TS U3523 ( .A0(intDY_EWSW[16]), .A1(n2689), .B0(DMP_EXP_EWSW[16]),
.B1(n2907), .Y(n2908) );
OAI21XLTS U3524 ( .A0(n3834), .A1(n2917), .B0(n2908), .Y(n1659) );
AOI22X1TS U3525 ( .A0(intDY_EWSW[49]), .A1(n2909), .B0(DmP_EXP_EWSW[49]),
.B1(n3320), .Y(n2910) );
OAI21XLTS U3526 ( .A0(n3798), .A1(n2911), .B0(n2910), .Y(n1300) );
AOI22X1TS U3527 ( .A0(intDY_EWSW[14]), .A1(n2834), .B0(DMP_EXP_EWSW[14]),
.B1(n3679), .Y(n2912) );
OAI21XLTS U3528 ( .A0(n3872), .A1(n2917), .B0(n2912), .Y(n1661) );
AOI22X1TS U3529 ( .A0(intDX_EWSW[41]), .A1(n2932), .B0(DMP_EXP_EWSW[41]),
.B1(n2935), .Y(n2913) );
OAI21XLTS U3530 ( .A0(n3672), .A1(n2934), .B0(n2913), .Y(n1634) );
AOI22X1TS U3531 ( .A0(intDY_EWSW[30]), .A1(n2923), .B0(DMP_EXP_EWSW[30]),
.B1(n2914), .Y(n2915) );
OAI21XLTS U3532 ( .A0(n3860), .A1(n2929), .B0(n2915), .Y(n1645) );
AOI22X1TS U3533 ( .A0(intDY_EWSW[15]), .A1(n2923), .B0(DMP_EXP_EWSW[15]),
.B1(n3679), .Y(n2916) );
OAI21XLTS U3534 ( .A0(n3796), .A1(n2917), .B0(n2916), .Y(n1660) );
AOI22X1TS U3535 ( .A0(intDX_EWSW[59]), .A1(n2919), .B0(DMP_EXP_EWSW[59]),
.B1(n2918), .Y(n2920) );
OAI21XLTS U3536 ( .A0(n3671), .A1(n2921), .B0(n2920), .Y(n1616) );
AOI22X1TS U3537 ( .A0(intDY_EWSW[13]), .A1(n2927), .B0(DMP_EXP_EWSW[13]),
.B1(n2922), .Y(n2924) );
OAI21XLTS U3538 ( .A0(n3709), .A1(n2925), .B0(n2924), .Y(n1662) );
AOI22X1TS U3539 ( .A0(intDY_EWSW[31]), .A1(n2927), .B0(DMP_EXP_EWSW[31]),
.B1(n2926), .Y(n2928) );
AOI22X1TS U3540 ( .A0(intDY_EWSW[44]), .A1(n2899), .B0(DMP_EXP_EWSW[44]),
.B1(n2935), .Y(n2930) );
OAI21XLTS U3541 ( .A0(n3901), .A1(n2938), .B0(n2930), .Y(n1631) );
AOI22X1TS U3542 ( .A0(intDY_EWSW[42]), .A1(n2686), .B0(DMP_EXP_EWSW[42]),
.B1(n2935), .Y(n2931) );
OAI21XLTS U3543 ( .A0(n3885), .A1(n2938), .B0(n2931), .Y(n1633) );
AOI22X1TS U3544 ( .A0(intDX_EWSW[43]), .A1(n2932), .B0(DMP_EXP_EWSW[43]),
.B1(n2935), .Y(n2933) );
AOI22X1TS U3545 ( .A0(intDY_EWSW[48]), .A1(n2936), .B0(DMP_EXP_EWSW[48]),
.B1(n2935), .Y(n2937) );
OAI21XLTS U3546 ( .A0(n3839), .A1(n2938), .B0(n2937), .Y(n1627) );
AOI22X1TS U3547 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(n3158), .B0(
inst_FSM_INPUT_ENABLE_state_reg[2]), .B1(n3684), .Y(n2968) );
AND2X2TS U3548 ( .A(beg_OP), .B(n2968), .Y(n2939) );
CLKBUFX2TS U3549 ( .A(n2939), .Y(n3173) );
CLKBUFX2TS U3550 ( .A(n3173), .Y(n3171) );
INVX2TS U3551 ( .A(n2939), .Y(n3251) );
AO22XLTS U3552 ( .A0(n3171), .A1(Data_Y[5]), .B0(n3251), .B1(intDY_EWSW[5]),
.Y(n1813) );
MX2X1TS U3553 ( .A(DMP_exp_NRM2_EW[6]), .B(DMP_exp_NRM_EW[6]), .S0(n2040),
.Y(n1419) );
AO22XLTS U3554 ( .A0(n2037), .A1(ZERO_FLAG_SHT1SHT2), .B0(n3023), .B1(
zero_flag), .Y(n1281) );
CLKBUFX2TS U3555 ( .A(n3171), .Y(n3174) );
INVX2TS U3556 ( .A(n3174), .Y(n3195) );
CLKBUFX2TS U3557 ( .A(n2939), .Y(n3148) );
CLKBUFX3TS U3558 ( .A(n3148), .Y(n3231) );
AO22XLTS U3559 ( .A0(n3195), .A1(intDX_EWSW[63]), .B0(n3231), .B1(Data_X[63]), .Y(n1820) );
INVX2TS U3560 ( .A(n3302), .Y(n3310) );
INVX2TS U3561 ( .A(Shift_reg_FLAGS_7_5), .Y(n3296) );
CLKBUFX3TS U3562 ( .A(n3296), .Y(n3309) );
AO22XLTS U3563 ( .A0(n3310), .A1(DMP_EXP_EWSW[25]), .B0(n3309), .B1(
DMP_SHT1_EWSW[25]), .Y(n1534) );
AO22XLTS U3564 ( .A0(n4087), .A1(DMP_SHT1_EWSW[25]), .B0(n2981), .B1(
DMP_SHT2_EWSW[25]), .Y(n1533) );
AOI22X1TS U3565 ( .A0(n2942), .A1(Data_array_SWR[54]), .B0(n2628), .B1(n2940), .Y(n2944) );
NAND2X1TS U3566 ( .A(n2944), .B(n2943), .Y(n1752) );
INVX2TS U3567 ( .A(n3303), .Y(n3115) );
CLKBUFX3TS U3568 ( .A(n3296), .Y(n3114) );
AO22XLTS U3569 ( .A0(n3115), .A1(DMP_EXP_EWSW[12]), .B0(n3114), .B1(
DMP_SHT1_EWSW[12]), .Y(n1573) );
CLKBUFX3TS U3570 ( .A(n3023), .Y(n3107) );
AO22XLTS U3571 ( .A0(n2037), .A1(n3326), .B0(n3107), .B1(underflow_flag),
.Y(n1288) );
INVX2TS U3572 ( .A(n3254), .Y(n3316) );
CLKBUFX3TS U3573 ( .A(n3313), .Y(n3315) );
AO22XLTS U3574 ( .A0(n3316), .A1(DMP_SHT1_EWSW[36]), .B0(n3315), .B1(
DMP_SHT2_EWSW[36]), .Y(n1500) );
CLKBUFX3TS U3575 ( .A(n3148), .Y(n3272) );
INVX2TS U3576 ( .A(n3173), .Y(n3271) );
AO22XLTS U3577 ( .A0(n3272), .A1(Data_X[24]), .B0(n3271), .B1(intDX_EWSW[24]), .Y(n1859) );
INVX2TS U3578 ( .A(n3254), .Y(n3098) );
CLKBUFX3TS U3579 ( .A(n3313), .Y(n3097) );
AO22XLTS U3580 ( .A0(n3098), .A1(DMP_SHT1_EWSW[13]), .B0(n3097), .B1(
DMP_SHT2_EWSW[13]), .Y(n1569) );
INVX2TS U3581 ( .A(n3171), .Y(n3234) );
CLKBUFX2TS U3582 ( .A(n3148), .Y(n3147) );
CLKBUFX3TS U3583 ( .A(n3147), .Y(n3197) );
AO22XLTS U3584 ( .A0(n3234), .A1(intDY_EWSW[40]), .B0(n3197), .B1(Data_Y[40]), .Y(n1778) );
AO22XLTS U3585 ( .A0(n3115), .A1(DMP_EXP_EWSW[13]), .B0(n3114), .B1(
DMP_SHT1_EWSW[13]), .Y(n1570) );
INVX2TS U3586 ( .A(n3321), .Y(n2980) );
AO22XLTS U3587 ( .A0(n2980), .A1(DMP_EXP_EWSW[14]), .B0(n3114), .B1(
DMP_SHT1_EWSW[14]), .Y(n1567) );
AO22XLTS U3588 ( .A0(n3310), .A1(DMP_EXP_EWSW[24]), .B0(n3309), .B1(
DMP_SHT1_EWSW[24]), .Y(n1537) );
INVX2TS U3589 ( .A(n3173), .Y(n3237) );
AO22XLTS U3590 ( .A0(n3237), .A1(intDY_EWSW[55]), .B0(n3236), .B1(Data_Y[55]), .Y(n1763) );
CLKBUFX3TS U3591 ( .A(n3148), .Y(n3184) );
AO22XLTS U3592 ( .A0(n3237), .A1(intDY_EWSW[51]), .B0(n3184), .B1(Data_Y[51]), .Y(n1767) );
AO22XLTS U3593 ( .A0(n3237), .A1(intDY_EWSW[53]), .B0(n3236), .B1(Data_Y[53]), .Y(n1765) );
INVX2TS U3594 ( .A(n2499), .Y(n3223) );
AOI2BB1X1TS U3595 ( .A0N(n1956), .A1N(n3123), .B0(n2997), .Y(n3156) );
AOI22X1TS U3596 ( .A0(Data_array_SWR[16]), .A1(n2954), .B0(
Data_array_SWR[24]), .B1(n3015), .Y(n2948) );
AOI22X1TS U3597 ( .A0(Data_array_SWR[12]), .A1(n1961), .B0(Data_array_SWR[4]), .B1(n1964), .Y(n2952) );
AOI22X1TS U3598 ( .A0(Data_array_SWR[8]), .A1(n1966), .B0(Data_array_SWR[0]),
.B1(n1968), .Y(n2951) );
OAI211XLTS U3599 ( .A0(n3066), .A1(n2953), .B0(n2952), .C0(n2951), .Y(n2963)
);
AOI22X1TS U3600 ( .A0(Data_array_SWR[48]), .A1(n2954), .B0(
Data_array_SWR[52]), .B1(n3016), .Y(n2956) );
NAND2X2TS U3601 ( .A(n2956), .B(n2955), .Y(n3116) );
INVX2TS U3602 ( .A(n3116), .Y(n3062) );
AOI22X1TS U3603 ( .A0(Data_array_SWR[40]), .A1(n2947), .B0(
Data_array_SWR[32]), .B1(n2957), .Y(n2958) );
OAI2BB1X1TS U3604 ( .A0N(Data_array_SWR[36]), .A1N(n2642), .B0(n2958), .Y(
n2959) );
AOI21X2TS U3605 ( .A0(Data_array_SWR[44]), .A1(n2960), .B0(n2959), .Y(n3128)
);
OAI22X1TS U3606 ( .A0(n3062), .A1(n3012), .B0(n3128), .B1(n2961), .Y(n2962)
);
NOR2X1TS U3607 ( .A(n2963), .B(n2962), .Y(n3157) );
OAI222X1TS U3608 ( .A0(n3223), .A1(n3156), .B0(n3212), .B1(n3157), .C0(n3700), .C1(n3219), .Y(n1156) );
AO22XLTS U3609 ( .A0(n3148), .A1(Data_Y[6]), .B0(n3271), .B1(intDY_EWSW[6]),
.Y(n1812) );
AO22XLTS U3610 ( .A0(n2980), .A1(DMP_EXP_EWSW[15]), .B0(n3114), .B1(
DMP_SHT1_EWSW[15]), .Y(n1564) );
INVX2TS U3611 ( .A(n2939), .Y(n3175) );
CLKBUFX3TS U3612 ( .A(n3147), .Y(n3235) );
AO22XLTS U3613 ( .A0(n3175), .A1(intDX_EWSW[6]), .B0(n3235), .B1(Data_X[6]),
.Y(n1877) );
AO22XLTS U3614 ( .A0(n3234), .A1(intDY_EWSW[46]), .B0(n3235), .B1(Data_Y[46]), .Y(n1772) );
NOR2X2TS U3615 ( .A(n3686), .B(n3878), .Y(n3332) );
INVX2TS U3616 ( .A(n3584), .Y(n3653) );
AOI21X1TS U3617 ( .A0(n3654), .A1(n3858), .B0(n3653), .Y(n2964) );
INVX2TS U3618 ( .A(Shift_reg_FLAGS_7[2]), .Y(n3590) );
AO22XLTS U3619 ( .A0(n3343), .A1(n2964), .B0(n3622), .B1(ADD_OVRFLW_NRM),
.Y(n1277) );
CLKBUFX3TS U3620 ( .A(n3147), .Y(n3233) );
AO22XLTS U3621 ( .A0(n3234), .A1(intDY_EWSW[43]), .B0(n3233), .B1(Data_Y[43]), .Y(n1775) );
INVX2TS U3622 ( .A(n3174), .Y(n3193) );
AO22XLTS U3623 ( .A0(n3193), .A1(intDY_EWSW[35]), .B0(n3233), .B1(Data_Y[35]), .Y(n1783) );
AO22XLTS U3624 ( .A0(n4087), .A1(DMP_SHT1_EWSW[23]), .B0(n2981), .B1(
DMP_SHT2_EWSW[23]), .Y(n1539) );
NOR2XLTS U3625 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(
inst_FSM_INPUT_ENABLE_state_reg[1]), .Y(n2965) );
AOI32X4TS U3626 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
inst_FSM_INPUT_ENABLE_state_reg[0]), .A2(
inst_FSM_INPUT_ENABLE_state_reg[2]), .B0(n2965), .B1(n3841), .Y(n3325)
);
INVX2TS U3627 ( .A(n3325), .Y(n3323) );
AO22XLTS U3628 ( .A0(n3325), .A1(busy), .B0(n3323), .B1(Shift_reg_FLAGS_7[3]), .Y(n1887) );
AO22XLTS U3629 ( .A0(n3098), .A1(DMP_SHT1_EWSW[15]), .B0(n3097), .B1(
DMP_SHT2_EWSW[15]), .Y(n1563) );
INVX2TS U3630 ( .A(n2966), .Y(n2976) );
INVX2TS U3631 ( .A(n2498), .Y(n3212) );
CLKBUFX3TS U3632 ( .A(n3147), .Y(n3170) );
AO22XLTS U3633 ( .A0(n3170), .A1(Data_X[54]), .B0(n3175), .B1(intDX_EWSW[54]), .Y(n1829) );
INVX2TS U3634 ( .A(n2499), .Y(n3209) );
INVX2TS U3635 ( .A(n2967), .Y(n2974) );
AO22XLTS U3636 ( .A0(n3323), .A1(Shift_reg_FLAGS_7_6), .B0(n3325), .B1(n2968), .Y(n1890) );
INVX2TS U3637 ( .A(n3171), .Y(n3172) );
AO22XLTS U3638 ( .A0(n3171), .A1(Data_Y[18]), .B0(n3172), .B1(intDY_EWSW[18]), .Y(n1800) );
AO22XLTS U3639 ( .A0(n3237), .A1(intDY_EWSW[59]), .B0(n3236), .B1(Data_Y[59]), .Y(n1759) );
AO22XLTS U3640 ( .A0(n2980), .A1(DMP_EXP_EWSW[16]), .B0(n3114), .B1(
DMP_SHT1_EWSW[16]), .Y(n1561) );
INVX2TS U3641 ( .A(n2969), .Y(n2972) );
AO22XLTS U3642 ( .A0(n3234), .A1(intDY_EWSW[41]), .B0(n3184), .B1(Data_Y[41]), .Y(n1777) );
AO22XLTS U3643 ( .A0(n3173), .A1(Data_X[41]), .B0(n3271), .B1(intDX_EWSW[41]), .Y(n1842) );
INVX2TS U3644 ( .A(n2970), .Y(n2978) );
OAI222X1TS U3645 ( .A0(n3209), .A1(n2978), .B0(n3221), .B1(n2977), .C0(n3673), .C1(n3219), .Y(n1110) );
MX2X1TS U3646 ( .A(DMP_exp_NRM2_EW[7]), .B(DMP_exp_NRM_EW[7]), .S0(n2041),
.Y(n1414) );
AO22XLTS U3647 ( .A0(n2980), .A1(DMP_EXP_EWSW[17]), .B0(n3114), .B1(
DMP_SHT1_EWSW[17]), .Y(n1558) );
OAI222X1TS U3648 ( .A0(n3223), .A1(n2979), .B0(n2436), .B1(n1978), .C0(n3674), .C1(n3219), .Y(n1104) );
MX2X1TS U3649 ( .A(DMP_exp_NRM2_EW[10]), .B(DMP_exp_NRM_EW[10]), .S0(n2042),
.Y(n1399) );
AO22XLTS U3650 ( .A0(n4087), .A1(DMP_SHT1_EWSW[17]), .B0(n3097), .B1(
DMP_SHT2_EWSW[17]), .Y(n1557) );
AO22XLTS U3651 ( .A0(n3193), .A1(intDY_EWSW[33]), .B0(n3197), .B1(Data_Y[33]), .Y(n1785) );
AO22XLTS U3652 ( .A0(n2980), .A1(DMP_EXP_EWSW[23]), .B0(n3309), .B1(
DMP_SHT1_EWSW[23]), .Y(n1540) );
AO22XLTS U3653 ( .A0(n2980), .A1(DMP_EXP_EWSW[18]), .B0(n3114), .B1(
DMP_SHT1_EWSW[18]), .Y(n1555) );
INVX2TS U3654 ( .A(n2939), .Y(n3239) );
CLKBUFX3TS U3655 ( .A(n3147), .Y(n3196) );
AO22XLTS U3656 ( .A0(n3239), .A1(intDX_EWSW[23]), .B0(n3196), .B1(Data_X[23]), .Y(n1860) );
AO22XLTS U3657 ( .A0(n2980), .A1(DMP_EXP_EWSW[19]), .B0(n3114), .B1(
DMP_SHT1_EWSW[19]), .Y(n1552) );
MX2X1TS U3658 ( .A(DMP_exp_NRM2_EW[9]), .B(DMP_exp_NRM_EW[9]), .S0(n2039),
.Y(n1404) );
AO22XLTS U3659 ( .A0(n3098), .A1(DMP_SHT1_EWSW[11]), .B0(n3097), .B1(
DMP_SHT2_EWSW[11]), .Y(n1575) );
INVX2TS U3660 ( .A(n3174), .Y(n3232) );
CLKBUFX3TS U3661 ( .A(n3147), .Y(n3194) );
AO22XLTS U3662 ( .A0(n3232), .A1(intDY_EWSW[31]), .B0(n3194), .B1(Data_Y[31]), .Y(n1787) );
AO22XLTS U3663 ( .A0(n2980), .A1(DMP_EXP_EWSW[22]), .B0(n3309), .B1(
DMP_SHT1_EWSW[22]), .Y(n1543) );
AO22XLTS U3664 ( .A0(n4087), .A1(DMP_SHT1_EWSW[19]), .B0(n2981), .B1(
DMP_SHT2_EWSW[19]), .Y(n1551) );
AO22XLTS U3665 ( .A0(n2980), .A1(DMP_EXP_EWSW[20]), .B0(n3309), .B1(
DMP_SHT1_EWSW[20]), .Y(n1549) );
AO22XLTS U3666 ( .A0(n4087), .A1(DMP_SHT1_EWSW[21]), .B0(n2981), .B1(
DMP_SHT2_EWSW[21]), .Y(n1545) );
AO22XLTS U3667 ( .A0(n2980), .A1(DMP_EXP_EWSW[21]), .B0(n3309), .B1(
DMP_SHT1_EWSW[21]), .Y(n1546) );
INVX2TS U3668 ( .A(n2939), .Y(n3198) );
AO22XLTS U3669 ( .A0(n3198), .A1(intDY_EWSW[25]), .B0(n3184), .B1(Data_Y[25]), .Y(n1793) );
MX2X1TS U3670 ( .A(DMP_exp_NRM2_EW[8]), .B(DMP_exp_NRM_EW[8]), .S0(n2040),
.Y(n1409) );
AO22XLTS U3671 ( .A0(n3193), .A1(intDY_EWSW[30]), .B0(n3233), .B1(Data_Y[30]), .Y(n1788) );
AO22XLTS U3672 ( .A0(exp_rslt_NRM2_EW1[10]), .A1(n3039), .B0(
final_result_ieee[62]), .B1(n3324), .Y(n1676) );
AO22XLTS U3673 ( .A0(n3272), .A1(Data_Y[62]), .B0(n3172), .B1(intDY_EWSW[62]), .Y(n1756) );
CLKBUFX3TS U3674 ( .A(n3313), .Y(n3306) );
AO22XLTS U3675 ( .A0(n3316), .A1(DMP_SHT1_EWSW[38]), .B0(n3306), .B1(
DMP_SHT2_EWSW[38]), .Y(n1494) );
AO22XLTS U3676 ( .A0(n3170), .A1(Data_Y[58]), .B0(n3172), .B1(intDY_EWSW[58]), .Y(n1760) );
AO22XLTS U3677 ( .A0(n3300), .A1(DMP_SHT1_EWSW[32]), .B0(n3315), .B1(
DMP_SHT2_EWSW[32]), .Y(n1512) );
AO22XLTS U3678 ( .A0(n3300), .A1(DMP_SHT1_EWSW[30]), .B0(n3315), .B1(
DMP_SHT2_EWSW[30]), .Y(n1518) );
AO22XLTS U3679 ( .A0(n3316), .A1(DMP_SHT1_EWSW[40]), .B0(n3306), .B1(
DMP_SHT2_EWSW[40]), .Y(n1488) );
AO22XLTS U3680 ( .A0(n3300), .A1(DMP_SHT1_EWSW[28]), .B0(n3315), .B1(
DMP_SHT2_EWSW[28]), .Y(n1524) );
AO22XLTS U3681 ( .A0(busy), .A1(DMP_SHT1_EWSW[26]), .B0(n2981), .B1(
DMP_SHT2_EWSW[26]), .Y(n1530) );
AO22XLTS U3682 ( .A0(busy), .A1(DMP_SHT1_EWSW[24]), .B0(n2981), .B1(
DMP_SHT2_EWSW[24]), .Y(n1536) );
AO22XLTS U3683 ( .A0(n3316), .A1(DMP_SHT1_EWSW[42]), .B0(n3306), .B1(
DMP_SHT2_EWSW[42]), .Y(n1482) );
AO22XLTS U3684 ( .A0(n4087), .A1(DMP_SHT1_EWSW[22]), .B0(n2981), .B1(
DMP_SHT2_EWSW[22]), .Y(n1542) );
AO22XLTS U3685 ( .A0(n3316), .A1(DMP_SHT1_EWSW[44]), .B0(n3306), .B1(
DMP_SHT2_EWSW[44]), .Y(n1476) );
AO22XLTS U3686 ( .A0(n4087), .A1(DMP_SHT1_EWSW[20]), .B0(n2981), .B1(
DMP_SHT2_EWSW[20]), .Y(n1548) );
AO22XLTS U3687 ( .A0(n4087), .A1(DMP_SHT1_EWSW[18]), .B0(n2981), .B1(
DMP_SHT2_EWSW[18]), .Y(n1554) );
AO22XLTS U3688 ( .A0(n3098), .A1(DMP_SHT1_EWSW[16]), .B0(n3097), .B1(
DMP_SHT2_EWSW[16]), .Y(n1560) );
INVX2TS U3689 ( .A(n3254), .Y(n3314) );
AO22XLTS U3690 ( .A0(n3314), .A1(DMP_SHT1_EWSW[46]), .B0(n3306), .B1(
DMP_SHT2_EWSW[46]), .Y(n1470) );
AO22XLTS U3691 ( .A0(n3098), .A1(DMP_SHT1_EWSW[14]), .B0(n3097), .B1(
DMP_SHT2_EWSW[14]), .Y(n1566) );
AO22XLTS U3692 ( .A0(n3314), .A1(DMP_SHT1_EWSW[48]), .B0(n3313), .B1(
DMP_SHT2_EWSW[48]), .Y(n1464) );
AO22XLTS U3693 ( .A0(n3098), .A1(DMP_SHT1_EWSW[12]), .B0(n3097), .B1(
DMP_SHT2_EWSW[12]), .Y(n1572) );
AO22XLTS U3694 ( .A0(n3098), .A1(DMP_SHT1_EWSW[10]), .B0(n3097), .B1(
DMP_SHT2_EWSW[10]), .Y(n1578) );
AO22XLTS U3695 ( .A0(n3300), .A1(DMP_SHT1_EWSW[50]), .B0(n3313), .B1(
DMP_SHT2_EWSW[50]), .Y(n1458) );
AO22XLTS U3696 ( .A0(n3272), .A1(Data_X[61]), .B0(n3271), .B1(intDX_EWSW[61]), .Y(n1822) );
AO22XLTS U3697 ( .A0(n3098), .A1(DMP_SHT1_EWSW[8]), .B0(n3097), .B1(
DMP_SHT2_EWSW[8]), .Y(n1584) );
AO22XLTS U3698 ( .A0(busy), .A1(DMP_SHT1_EWSW[6]), .B0(n3854), .B1(
DMP_SHT2_EWSW[6]), .Y(n1590) );
AO22XLTS U3699 ( .A0(n3314), .A1(DMP_SHT1_EWSW[51]), .B0(n3313), .B1(
DMP_SHT2_EWSW[51]), .Y(n1455) );
AO22XLTS U3700 ( .A0(busy), .A1(DMP_SHT1_EWSW[4]), .B0(n3854), .B1(
DMP_SHT2_EWSW[4]), .Y(n1596) );
AO22XLTS U3701 ( .A0(n3170), .A1(Data_Y[60]), .B0(n3172), .B1(intDY_EWSW[60]), .Y(n1758) );
INVX2TS U3702 ( .A(n3301), .Y(n3288) );
INVX2TS U3703 ( .A(Shift_reg_FLAGS_7_5), .Y(n3298) );
CLKBUFX3TS U3704 ( .A(n3298), .Y(n3287) );
AO22XLTS U3705 ( .A0(n3288), .A1(DmP_EXP_EWSW[25]), .B0(n3287), .B1(
DmP_mant_SHT1_SW[25]), .Y(n1347) );
AO22XLTS U3706 ( .A0(busy), .A1(DMP_SHT1_EWSW[2]), .B0(n3854), .B1(
DMP_SHT2_EWSW[2]), .Y(n1602) );
AO22XLTS U3707 ( .A0(busy), .A1(DMP_SHT1_EWSW[0]), .B0(n3254), .B1(
DMP_SHT2_EWSW[0]), .Y(n1608) );
AO22XLTS U3708 ( .A0(n3295), .A1(OP_FLAG_SHT1), .B0(n3299), .B1(OP_FLAG_SHT2), .Y(n1279) );
INVX2TS U3709 ( .A(n3318), .Y(n3039) );
AOI22X1TS U3710 ( .A0(Data_array_SWR[15]), .A1(n1967), .B0(
Data_array_SWR[27]), .B1(n1962), .Y(n2986) );
AOI22X1TS U3711 ( .A0(Data_array_SWR[23]), .A1(n1966), .B0(
Data_array_SWR[19]), .B1(n1964), .Y(n2985) );
AOI22X1TS U3712 ( .A0(n1947), .A1(n2983), .B0(n1959), .B1(n2982), .Y(n2984)
);
NAND4XLTS U3713 ( .A(n2986), .B(n2985), .C(n2984), .D(n1981), .Y(n3055) );
AOI22X1TS U3714 ( .A0(n3111), .A1(n3054), .B0(n3746), .B1(n3055), .Y(n2987)
);
NAND2X2TS U3715 ( .A(left_right_SHT2), .B(n2997), .Y(n3052) );
NAND2X1TS U3716 ( .A(n2987), .B(n3052), .Y(n3151) );
AO22XLTS U3717 ( .A0(final_result_ieee[13]), .A1(n3107), .B0(n1972), .B1(
n3151), .Y(n1185) );
AO21XLTS U3718 ( .A0(OP_FLAG_EXP), .A1(n3679), .B0(n2988), .Y(n1612) );
INVX2TS U3719 ( .A(n3301), .Y(n3285) );
CLKBUFX3TS U3720 ( .A(n3296), .Y(n3078) );
AO22XLTS U3721 ( .A0(n3285), .A1(DMP_EXP_EWSW[0]), .B0(n3078), .B1(
DMP_SHT1_EWSW[0]), .Y(n1609) );
AO22XLTS U3722 ( .A0(n3285), .A1(DMP_EXP_EWSW[1]), .B0(n3078), .B1(
DMP_SHT1_EWSW[1]), .Y(n1606) );
AO22XLTS U3723 ( .A0(busy), .A1(DMP_SHT1_EWSW[1]), .B0(n3254), .B1(
DMP_SHT2_EWSW[1]), .Y(n1605) );
AO22XLTS U3724 ( .A0(n3272), .A1(Data_X[33]), .B0(n3271), .B1(intDX_EWSW[33]), .Y(n1850) );
AO22XLTS U3725 ( .A0(n3300), .A1(DMP_SHT1_EWSW[34]), .B0(n3315), .B1(
DMP_SHT2_EWSW[34]), .Y(n1506) );
OA21XLTS U3726 ( .A0(n2037), .A1(overflow_flag), .B0(n3327), .Y(n1287) );
AO22XLTS U3727 ( .A0(n3285), .A1(DMP_EXP_EWSW[2]), .B0(n3078), .B1(
DMP_SHT1_EWSW[2]), .Y(n1603) );
AO22XLTS U3728 ( .A0(n3285), .A1(DMP_EXP_EWSW[3]), .B0(n3078), .B1(
DMP_SHT1_EWSW[3]), .Y(n1600) );
AOI22X1TS U3729 ( .A0(Data_array_SWR[44]), .A1(n3015), .B0(
Data_array_SWR[36]), .B1(n2957), .Y(n2990) );
AOI22X1TS U3730 ( .A0(Data_array_SWR[48]), .A1(n3017), .B0(
Data_array_SWR[40]), .B1(n3016), .Y(n2989) );
NAND2X2TS U3731 ( .A(n2990), .B(n2989), .Y(n3090) );
AOI22X1TS U3732 ( .A0(Data_array_SWR[12]), .A1(n1966), .B0(Data_array_SWR[4]), .B1(n1968), .Y(n2992) );
AOI22X1TS U3733 ( .A0(Data_array_SWR[16]), .A1(n1962), .B0(Data_array_SWR[8]), .B1(n1964), .Y(n2991) );
OAI211XLTS U3734 ( .A0(n3012), .A1(n3092), .B0(n2992), .C0(n2991), .Y(n2993)
);
AOI21X1TS U3735 ( .A0(n1960), .A1(n3090), .B0(n2993), .Y(n3000) );
AOI22X1TS U3736 ( .A0(Data_array_SWR[28]), .A1(n2947), .B0(
Data_array_SWR[20]), .B1(n3014), .Y(n2996) );
AOI22X1TS U3737 ( .A0(Data_array_SWR[32]), .A1(n3017), .B0(
Data_array_SWR[24]), .B1(n2994), .Y(n2995) );
NAND2X1TS U3738 ( .A(n2996), .B(n2995), .Y(n3094) );
AOI22X1TS U3739 ( .A0(n1953), .A1(n3089), .B0(n3117), .B1(n3094), .Y(n2998)
);
NAND2X2TS U3740 ( .A(n2997), .B(n1958), .Y(n3056) );
OAI211X1TS U3741 ( .A0(n3000), .A1(n1958), .B0(n2998), .C0(n3056), .Y(n3146)
);
AO22XLTS U3742 ( .A0(n3130), .A1(n3146), .B0(final_result_ieee[48]), .B1(
n3136), .Y(n1162) );
AO22XLTS U3743 ( .A0(n3272), .A1(Data_Y[1]), .B0(n3271), .B1(intDY_EWSW[1]),
.Y(n1817) );
AOI22X1TS U3744 ( .A0(n3111), .A1(n3089), .B0(n3119), .B1(n3094), .Y(n2999)
);
OAI211X1TS U3745 ( .A0(left_right_SHT2), .A1(n3000), .B0(n2999), .C0(n3052),
.Y(n3242) );
AO22XLTS U3746 ( .A0(n1972), .A1(n3242), .B0(final_result_ieee[2]), .B1(
n3136), .Y(n1163) );
AOI22X1TS U3747 ( .A0(Data_array_SWR[13]), .A1(n1966), .B0(Data_array_SWR[5]), .B1(n1968), .Y(n3002) );
AOI22X1TS U3748 ( .A0(Data_array_SWR[17]), .A1(n1962), .B0(Data_array_SWR[9]), .B1(n1964), .Y(n3001) );
OAI211XLTS U3749 ( .A0(n3012), .A1(n3102), .B0(n3002), .C0(n3001), .Y(n3003)
);
AOI21X1TS U3750 ( .A0(n1960), .A1(n3099), .B0(n3003), .Y(n3006) );
AOI22X1TS U3751 ( .A0(n1953), .A1(n3100), .B0(n3117), .B1(n3104), .Y(n3004)
);
OAI211X1TS U3752 ( .A0(n3006), .A1(n3746), .B0(n3004), .C0(n3056), .Y(n3155)
);
AO22XLTS U3753 ( .A0(n3039), .A1(n3155), .B0(final_result_ieee[47]), .B1(
n3745), .Y(n1164) );
AO22XLTS U3754 ( .A0(busy), .A1(DMP_SHT1_EWSW[3]), .B0(n3854), .B1(
DMP_SHT2_EWSW[3]), .Y(n1599) );
AOI22X1TS U3755 ( .A0(n3111), .A1(n3100), .B0(n3119), .B1(n3104), .Y(n3005)
);
OAI211X1TS U3756 ( .A0(left_right_SHT2), .A1(n3006), .B0(n3005), .C0(n3052),
.Y(n3149) );
AO22XLTS U3757 ( .A0(n1972), .A1(n3149), .B0(final_result_ieee[3]), .B1(
n3136), .Y(n1165) );
AO22XLTS U3758 ( .A0(n3171), .A1(Data_Y[15]), .B0(n3251), .B1(intDY_EWSW[15]), .Y(n1803) );
AOI22X1TS U3759 ( .A0(Data_array_SWR[46]), .A1(n3015), .B0(
Data_array_SWR[38]), .B1(n2804), .Y(n3009) );
AOI22X1TS U3760 ( .A0(Data_array_SWR[50]), .A1(n3007), .B0(
Data_array_SWR[42]), .B1(n3016), .Y(n3008) );
NAND2X2TS U3761 ( .A(n3009), .B(n3008), .Y(n3118) );
AOI22X1TS U3762 ( .A0(Data_array_SWR[14]), .A1(n1966), .B0(Data_array_SWR[6]), .B1(n1968), .Y(n3011) );
AOI22X1TS U3763 ( .A0(Data_array_SWR[18]), .A1(n1962), .B0(
Data_array_SWR[10]), .B1(n1964), .Y(n3010) );
OAI211XLTS U3764 ( .A0(n3012), .A1(n3123), .B0(n3011), .C0(n3010), .Y(n3013)
);
AOI21X1TS U3765 ( .A0(n1960), .A1(n3118), .B0(n3013), .Y(n3022) );
AOI22X1TS U3766 ( .A0(Data_array_SWR[30]), .A1(n2947), .B0(
Data_array_SWR[22]), .B1(n2957), .Y(n3019) );
AOI22X1TS U3767 ( .A0(Data_array_SWR[34]), .A1(n3017), .B0(
Data_array_SWR[26]), .B1(n3016), .Y(n3018) );
NAND2X1TS U3768 ( .A(n3019), .B(n3018), .Y(n3125) );
AOI22X1TS U3769 ( .A0(n1953), .A1(n3116), .B0(n3117), .B1(n3125), .Y(n3020)
);
OAI211X1TS U3770 ( .A0(n3022), .A1(n3746), .B0(n3020), .C0(n3056), .Y(n3144)
);
AO22XLTS U3771 ( .A0(n3039), .A1(n3144), .B0(final_result_ieee[46]), .B1(
n3136), .Y(n1166) );
AO22XLTS U3772 ( .A0(n3115), .A1(DMP_EXP_EWSW[4]), .B0(n3078), .B1(
DMP_SHT1_EWSW[4]), .Y(n1597) );
AOI22X1TS U3773 ( .A0(n3111), .A1(n3116), .B0(n3119), .B1(n3125), .Y(n3021)
);
OAI211X1TS U3774 ( .A0(left_right_SHT2), .A1(n3022), .B0(n3021), .C0(n3052),
.Y(n3244) );
CLKBUFX3TS U3775 ( .A(n3023), .Y(n3129) );
AO22XLTS U3776 ( .A0(n1972), .A1(n3244), .B0(final_result_ieee[4]), .B1(
n3129), .Y(n1167) );
AO22XLTS U3777 ( .A0(n3115), .A1(DMP_EXP_EWSW[5]), .B0(n3078), .B1(
DMP_SHT1_EWSW[5]), .Y(n1594) );
AOI22X1TS U3778 ( .A0(Data_array_SWR[12]), .A1(n1967), .B0(
Data_array_SWR[24]), .B1(n1962), .Y(n3028) );
AOI22X1TS U3779 ( .A0(Data_array_SWR[20]), .A1(n1966), .B0(
Data_array_SWR[16]), .B1(n1964), .Y(n3027) );
AOI22X1TS U3780 ( .A0(n1947), .A1(n3025), .B0(n1959), .B1(n3024), .Y(n3026)
);
NAND4XLTS U3781 ( .A(n3028), .B(n3027), .C(n3026), .D(n1981), .Y(n3030) );
AOI22X1TS U3782 ( .A0(left_right_SHT2), .A1(n3030), .B0(n1954), .B1(n3031),
.Y(n3029) );
NAND2X1TS U3783 ( .A(n3029), .B(n3056), .Y(n3183) );
AO22XLTS U3784 ( .A0(n3039), .A1(n3183), .B0(final_result_ieee[40]), .B1(
n3129), .Y(n1178) );
AO22XLTS U3785 ( .A0(n3272), .A1(Data_Y[17]), .B0(n3251), .B1(intDY_EWSW[17]), .Y(n1801) );
AOI22X1TS U3786 ( .A0(n3111), .A1(n3031), .B0(n3746), .B1(n3030), .Y(n3032)
);
NAND2X1TS U3787 ( .A(n3032), .B(n3052), .Y(n3160) );
AO22XLTS U3788 ( .A0(n1972), .A1(n3160), .B0(final_result_ieee[10]), .B1(
n3129), .Y(n1179) );
AOI22X1TS U3789 ( .A0(Data_array_SWR[13]), .A1(n1967), .B0(
Data_array_SWR[25]), .B1(n1962), .Y(n3037) );
AOI22X1TS U3790 ( .A0(Data_array_SWR[21]), .A1(n1966), .B0(
Data_array_SWR[17]), .B1(n1964), .Y(n3036) );
AOI22X1TS U3791 ( .A0(n1947), .A1(n3034), .B0(n1959), .B1(n3033), .Y(n3035)
);
NAND4XLTS U3792 ( .A(n3037), .B(n3036), .C(n3035), .D(n1981), .Y(n3040) );
AOI22X1TS U3793 ( .A0(n1957), .A1(n3040), .B0(n1954), .B1(n3041), .Y(n3038)
);
NAND2X1TS U3794 ( .A(n3038), .B(n3056), .Y(n3189) );
AO22XLTS U3795 ( .A0(n3039), .A1(n3189), .B0(final_result_ieee[39]), .B1(
n3129), .Y(n1180) );
AOI22X1TS U3796 ( .A0(n3111), .A1(n3041), .B0(n3746), .B1(n3040), .Y(n3042)
);
NAND2X1TS U3797 ( .A(n3042), .B(n3052), .Y(n3150) );
AO22XLTS U3798 ( .A0(n1972), .A1(n3150), .B0(final_result_ieee[11]), .B1(
n3129), .Y(n1181) );
AO22XLTS U3799 ( .A0(busy), .A1(DMP_SHT1_EWSW[5]), .B0(n3854), .B1(
DMP_SHT2_EWSW[5]), .Y(n1593) );
AO22XLTS U3800 ( .A0(n3170), .A1(Data_Y[49]), .B0(n3172), .B1(intDY_EWSW[49]), .Y(n1769) );
AO22XLTS U3801 ( .A0(n3115), .A1(DMP_EXP_EWSW[6]), .B0(n3078), .B1(
DMP_SHT1_EWSW[6]), .Y(n1591) );
AOI22X1TS U3802 ( .A0(Data_array_SWR[14]), .A1(n1967), .B0(
Data_array_SWR[26]), .B1(n1962), .Y(n3048) );
AOI22X1TS U3803 ( .A0(Data_array_SWR[22]), .A1(n1966), .B0(
Data_array_SWR[18]), .B1(n1964), .Y(n3047) );
AOI22X1TS U3804 ( .A0(n1947), .A1(n3044), .B0(n1960), .B1(n3043), .Y(n3046)
);
NAND4XLTS U3805 ( .A(n3048), .B(n3047), .C(n3046), .D(n1981), .Y(n3050) );
AOI22X1TS U3806 ( .A0(n1957), .A1(n3050), .B0(n1954), .B1(n3051), .Y(n3049)
);
NAND2X1TS U3807 ( .A(n3049), .B(n3056), .Y(n3182) );
AO22XLTS U3808 ( .A0(n3039), .A1(n3182), .B0(final_result_ieee[38]), .B1(
n3107), .Y(n1182) );
AOI22X1TS U3809 ( .A0(n2033), .A1(n3051), .B0(n3746), .B1(n3050), .Y(n3053)
);
NAND2X1TS U3810 ( .A(n3053), .B(n3052), .Y(n3138) );
AO22XLTS U3811 ( .A0(n1972), .A1(n3138), .B0(final_result_ieee[12]), .B1(
n3107), .Y(n1183) );
AO22XLTS U3812 ( .A0(n3115), .A1(DMP_EXP_EWSW[7]), .B0(n3078), .B1(
DMP_SHT1_EWSW[7]), .Y(n1588) );
AOI22X1TS U3813 ( .A0(n1957), .A1(n3055), .B0(n1954), .B1(n3054), .Y(n3057)
);
NAND2X1TS U3814 ( .A(n3057), .B(n3056), .Y(n3188) );
AO22XLTS U3815 ( .A0(n3039), .A1(n3188), .B0(final_result_ieee[37]), .B1(
n3129), .Y(n1184) );
AO22XLTS U3816 ( .A0(n3174), .A1(Data_Y[52]), .B0(n3251), .B1(intDY_EWSW[52]), .Y(n1766) );
INVX2TS U3817 ( .A(n3119), .Y(n3080) );
OAI21XLTS U3818 ( .A0(n3080), .A1(n3123), .B0(n1971), .Y(n3060) );
NAND2X2TS U3819 ( .A(left_right_SHT2), .B(n1959), .Y(n3109) );
INVX2TS U3820 ( .A(n3117), .Y(n3079) );
OAI22X1TS U3821 ( .A0(n3062), .A1(n3109), .B0(n3128), .B1(n3079), .Y(n3059)
);
AOI211X1TS U3822 ( .A0(n1953), .A1(n3118), .B0(n3060), .C0(n3059), .Y(n3061)
);
OAI21X1TS U3823 ( .A0(n3066), .A1(n3127), .B0(n3061), .Y(n3181) );
AO22XLTS U3824 ( .A0(n1972), .A1(n3181), .B0(final_result_ieee[36]), .B1(
n3107), .Y(n1186) );
AO22XLTS U3825 ( .A0(n3195), .A1(intDY_EWSW[7]), .B0(n3194), .B1(Data_Y[7]),
.Y(n1811) );
INVX2TS U3826 ( .A(n1953), .Y(n3113) );
OAI22X1TS U3827 ( .A0(n3062), .A1(n3122), .B0(n3128), .B1(n3080), .Y(n3063)
);
AOI211X1TS U3828 ( .A0(n3111), .A1(n3118), .B0(n3064), .C0(n3063), .Y(n3065)
);
OAI21X1TS U3829 ( .A0(n3066), .A1(n3113), .B0(n3065), .Y(n3139) );
AO22XLTS U3830 ( .A0(n3039), .A1(n3139), .B0(final_result_ieee[14]), .B1(
n3129), .Y(n1187) );
AO22XLTS U3831 ( .A0(n3098), .A1(DMP_SHT1_EWSW[7]), .B0(n3254), .B1(
DMP_SHT2_EWSW[7]), .Y(n1587) );
OAI22X1TS U3832 ( .A0(n3070), .A1(n3109), .B0(n3106), .B1(n3079), .Y(n3067)
);
AOI211X1TS U3833 ( .A0(n1953), .A1(n3099), .B0(n3068), .C0(n3067), .Y(n3069)
);
OAI21X1TS U3834 ( .A0(n3074), .A1(n3127), .B0(n3069), .Y(n3186) );
AO22XLTS U3835 ( .A0(n1972), .A1(n3186), .B0(final_result_ieee[35]), .B1(
n3107), .Y(n1188) );
AO22XLTS U3836 ( .A0(n3272), .A1(Data_Y[56]), .B0(n3172), .B1(intDY_EWSW[56]), .Y(n1762) );
OAI21XLTS U3837 ( .A0(n3079), .A1(n3102), .B0(n3121), .Y(n3072) );
OAI22X1TS U3838 ( .A0(n3070), .A1(n3122), .B0(n3106), .B1(n3080), .Y(n3071)
);
AOI211X1TS U3839 ( .A0(n3111), .A1(n3099), .B0(n3072), .C0(n3071), .Y(n3073)
);
OAI21X1TS U3840 ( .A0(n3074), .A1(n3113), .B0(n3073), .Y(n3152) );
AO22XLTS U3841 ( .A0(n3039), .A1(n3152), .B0(final_result_ieee[15]), .B1(
n3107), .Y(n1189) );
OAI21XLTS U3842 ( .A0(n3080), .A1(n3092), .B0(n1971), .Y(n3076) );
OAI22X1TS U3843 ( .A0(n3081), .A1(n3109), .B0(n3096), .B1(n3079), .Y(n3075)
);
OAI21X1TS U3844 ( .A0(n3085), .A1(n3127), .B0(n3077), .Y(n3180) );
AO22XLTS U3845 ( .A0(n3130), .A1(n3180), .B0(final_result_ieee[34]), .B1(
n3129), .Y(n1190) );
AO22XLTS U3846 ( .A0(n3115), .A1(DMP_EXP_EWSW[8]), .B0(n3078), .B1(
DMP_SHT1_EWSW[8]), .Y(n1585) );
AO22XLTS U3847 ( .A0(n3115), .A1(DMP_EXP_EWSW[9]), .B0(n3078), .B1(
DMP_SHT1_EWSW[9]), .Y(n1582) );
OAI21XLTS U3848 ( .A0(n3079), .A1(n3092), .B0(n3121), .Y(n3083) );
OAI22X1TS U3849 ( .A0(n3081), .A1(n3122), .B0(n3096), .B1(n3080), .Y(n3082)
);
AOI211X1TS U3850 ( .A0(n3111), .A1(n3090), .B0(n3083), .C0(n3082), .Y(n3084)
);
OAI21X1TS U3851 ( .A0(n3085), .A1(n3113), .B0(n3084), .Y(n3140) );
AO22XLTS U3852 ( .A0(n3130), .A1(n3140), .B0(final_result_ieee[16]), .B1(
n3136), .Y(n1191) );
AO22XLTS U3853 ( .A0(n3272), .A1(Data_X[26]), .B0(n3271), .B1(intDX_EWSW[26]), .Y(n1857) );
AOI22X1TS U3854 ( .A0(n3119), .A1(n3089), .B0(n3117), .B1(n3090), .Y(n3086)
);
OAI211XLTS U3855 ( .A0(n3092), .A1(n3109), .B0(n1971), .C0(n3086), .Y(n3087)
);
AOI21X1TS U3856 ( .A0(n2033), .A1(n3094), .B0(n3087), .Y(n3088) );
OAI21X1TS U3857 ( .A0(n3096), .A1(n3113), .B0(n3088), .Y(n3179) );
AO22XLTS U3858 ( .A0(n3130), .A1(n3179), .B0(final_result_ieee[32]), .B1(
n3107), .Y(n1194) );
AOI22X1TS U3859 ( .A0(n3119), .A1(n3090), .B0(n3117), .B1(n3089), .Y(n3091)
);
OAI211XLTS U3860 ( .A0(n3092), .A1(n3122), .B0(n3121), .C0(n3091), .Y(n3093)
);
AOI21X1TS U3861 ( .A0(n1954), .A1(n3094), .B0(n3093), .Y(n3095) );
OAI21X1TS U3862 ( .A0(n3096), .A1(n3127), .B0(n3095), .Y(n3141) );
AO22XLTS U3863 ( .A0(n3130), .A1(n3141), .B0(final_result_ieee[18]), .B1(
n3107), .Y(n1195) );
AO22XLTS U3864 ( .A0(n3098), .A1(DMP_SHT1_EWSW[9]), .B0(n3097), .B1(
DMP_SHT2_EWSW[9]), .Y(n1581) );
AOI22X1TS U3865 ( .A0(n3119), .A1(n3100), .B0(n3117), .B1(n3099), .Y(n3101)
);
OAI211XLTS U3866 ( .A0(n3102), .A1(n3109), .B0(n1971), .C0(n3101), .Y(n3103)
);
AOI21X1TS U3867 ( .A0(n2033), .A1(n3104), .B0(n3103), .Y(n3105) );
OAI21X1TS U3868 ( .A0(n3106), .A1(n3113), .B0(n3105), .Y(n3185) );
AO22XLTS U3869 ( .A0(n3130), .A1(n3185), .B0(final_result_ieee[31]), .B1(
n3107), .Y(n1196) );
AO22XLTS U3870 ( .A0(n3170), .A1(Data_X[46]), .B0(n3251), .B1(intDX_EWSW[46]), .Y(n1837) );
AOI22X1TS U3871 ( .A0(n3119), .A1(n3116), .B0(n3117), .B1(n3118), .Y(n3108)
);
OAI211XLTS U3872 ( .A0(n3123), .A1(n3109), .B0(n1971), .C0(n3108), .Y(n3110)
);
AOI21X1TS U3873 ( .A0(n2033), .A1(n3125), .B0(n3110), .Y(n3112) );
OAI21X1TS U3874 ( .A0(n3128), .A1(n3113), .B0(n3112), .Y(n3143) );
AO22XLTS U3875 ( .A0(n3130), .A1(n3143), .B0(final_result_ieee[30]), .B1(
n3129), .Y(n1198) );
AO22XLTS U3876 ( .A0(n3115), .A1(DMP_EXP_EWSW[10]), .B0(n3114), .B1(
DMP_SHT1_EWSW[10]), .Y(n1579) );
AO22XLTS U3877 ( .A0(n3115), .A1(DMP_EXP_EWSW[11]), .B0(n3114), .B1(
DMP_SHT1_EWSW[11]), .Y(n1576) );
AOI22X1TS U3878 ( .A0(n3119), .A1(n3118), .B0(n3117), .B1(n3116), .Y(n3120)
);
OAI211XLTS U3879 ( .A0(n3123), .A1(n3122), .B0(n3121), .C0(n3120), .Y(n3124)
);
AOI21X1TS U3880 ( .A0(n1954), .A1(n3125), .B0(n3124), .Y(n3126) );
OAI21X1TS U3881 ( .A0(n3128), .A1(n3127), .B0(n3126), .Y(n3142) );
AO22XLTS U3882 ( .A0(n3130), .A1(n3142), .B0(final_result_ieee[20]), .B1(
n3129), .Y(n1199) );
AO22XLTS U3883 ( .A0(n3170), .A1(Data_Y[0]), .B0(n3271), .B1(intDY_EWSW[0]),
.Y(n1818) );
AOI22X1TS U3884 ( .A0(n1947), .A1(n1983), .B0(n2036), .B1(n3131), .Y(n3135)
);
NAND2X1TS U3885 ( .A(n3135), .B(n3134), .Y(n3154) );
AO22XLTS U3886 ( .A0(n3039), .A1(n3154), .B0(final_result_ieee[25]), .B1(
n3136), .Y(n1208) );
CLKBUFX3TS U3887 ( .A(n3225), .Y(n3246) );
INVX2TS U3888 ( .A(n3145), .Y(n3245) );
AO22XLTS U3889 ( .A0(n3246), .A1(DmP_mant_SFG_SWR[14]), .B0(n3245), .B1(
n3138), .Y(n1142) );
CLKBUFX2TS U3890 ( .A(n3145), .Y(n3177) );
INVX2TS U3891 ( .A(n3177), .Y(n3249) );
CLKBUFX3TS U3892 ( .A(n3145), .Y(n3252) );
AO22XLTS U3893 ( .A0(n3249), .A1(DMP_SHT2_EWSW[17]), .B0(n3252), .B1(
DMP_SFG[17]), .Y(n1556) );
AO22XLTS U3894 ( .A0(n3246), .A1(DmP_mant_SFG_SWR[16]), .B0(n3245), .B1(
n3139), .Y(n1140) );
CLKBUFX3TS U3895 ( .A(n3145), .Y(n3187) );
INVX2TS U3896 ( .A(n3164), .Y(n3228) );
AO22XLTS U3897 ( .A0(n3187), .A1(DmP_mant_SFG_SWR[18]), .B0(n3228), .B1(
n3140), .Y(n1138) );
INVX2TS U3898 ( .A(n3145), .Y(n3226) );
AO22XLTS U3899 ( .A0(n3187), .A1(DmP_mant_SFG_SWR[20]), .B0(n3226), .B1(
n3141), .Y(n1136) );
INVX2TS U3900 ( .A(n3177), .Y(n3243) );
AO22XLTS U3901 ( .A0(n3243), .A1(DMP_SHT2_EWSW[19]), .B0(n3252), .B1(
DMP_SFG[19]), .Y(n1550) );
INVX2TS U3902 ( .A(n3177), .Y(n3256) );
AO22XLTS U3903 ( .A0(n3187), .A1(DmP_mant_SFG_SWR[22]), .B0(n3256), .B1(
n3142), .Y(n1134) );
AO22XLTS U3904 ( .A0(n3187), .A1(DmP_mant_SFG_SWR[32]), .B0(n3226), .B1(
n3143), .Y(n1124) );
INVX2TS U3905 ( .A(n3164), .Y(n3224) );
AO22XLTS U3906 ( .A0(n3145), .A1(DmP_mant_SFG_SWR[48]), .B0(n3224), .B1(
n3144), .Y(n1108) );
INVX2TS U3907 ( .A(n3177), .Y(n3257) );
AO22XLTS U3908 ( .A0(n3257), .A1(DMP_SHT2_EWSW[21]), .B0(n3252), .B1(
DMP_SFG[21]), .Y(n1544) );
AO22XLTS U3909 ( .A0(n3164), .A1(DmP_mant_SFG_SWR[50]), .B0(n3224), .B1(
n3146), .Y(n1106) );
AO22XLTS U3910 ( .A0(n3243), .A1(DMP_SHT2_EWSW[23]), .B0(n3252), .B1(
DMP_SFG[23]), .Y(n1538) );
CLKBUFX3TS U3911 ( .A(n3147), .Y(n3229) );
AO22XLTS U3912 ( .A0(n3239), .A1(intDX_EWSW[10]), .B0(n3229), .B1(Data_X[10]), .Y(n1873) );
AO22XLTS U3913 ( .A0(n3243), .A1(DMP_SHT2_EWSW[25]), .B0(n3250), .B1(
DMP_SFG[25]), .Y(n1532) );
AO22XLTS U3914 ( .A0(n3237), .A1(intDY_EWSW[48]), .B0(n3236), .B1(Data_Y[48]), .Y(n1770) );
AO22XLTS U3915 ( .A0(n3305), .A1(DMP_SHT2_EWSW[29]), .B0(n3255), .B1(
DMP_SFG[29]), .Y(n1520) );
CLKBUFX3TS U3916 ( .A(n3250), .Y(n3304) );
AO22XLTS U3917 ( .A0(n3249), .A1(DMP_SHT2_EWSW[31]), .B0(n3304), .B1(
DMP_SFG[31]), .Y(n1514) );
AO22XLTS U3918 ( .A0(n3195), .A1(intDY_EWSW[12]), .B0(n3194), .B1(Data_Y[12]), .Y(n1806) );
AO22XLTS U3919 ( .A0(n3175), .A1(intDX_EWSW[16]), .B0(n3235), .B1(Data_X[16]), .Y(n1867) );
AO22XLTS U3920 ( .A0(n3198), .A1(intDY_EWSW[19]), .B0(n3184), .B1(Data_Y[19]), .Y(n1799) );
AO22XLTS U3921 ( .A0(n3243), .A1(DMP_SHT2_EWSW[33]), .B0(n3304), .B1(
DMP_SFG[33]), .Y(n1508) );
AO22XLTS U3922 ( .A0(n3193), .A1(intDY_EWSW[36]), .B0(n3197), .B1(Data_Y[36]), .Y(n1782) );
AO22XLTS U3923 ( .A0(n3243), .A1(DMP_SHT2_EWSW[35]), .B0(n3252), .B1(
DMP_SFG[35]), .Y(n1502) );
INVX2TS U3924 ( .A(n3174), .Y(n3241) );
CLKBUFX3TS U3925 ( .A(n3148), .Y(n3240) );
AO22XLTS U3926 ( .A0(n3241), .A1(intDX_EWSW[48]), .B0(n3240), .B1(Data_X[48]), .Y(n1835) );
AO22XLTS U3927 ( .A0(n3241), .A1(intDX_EWSW[47]), .B0(n3240), .B1(Data_X[47]), .Y(n1836) );
AO22XLTS U3928 ( .A0(n3249), .A1(DMP_SHT2_EWSW[37]), .B0(n3304), .B1(
DMP_SFG[37]), .Y(n1496) );
AO22XLTS U3929 ( .A0(n3137), .A1(DmP_mant_SFG_SWR[5]), .B0(n3256), .B1(n3149), .Y(n1151) );
AO22XLTS U3930 ( .A0(n3246), .A1(DmP_mant_SFG_SWR[13]), .B0(n3226), .B1(
n3150), .Y(n1143) );
AO22XLTS U3931 ( .A0(n3246), .A1(DmP_mant_SFG_SWR[15]), .B0(n3226), .B1(
n3151), .Y(n1141) );
AO22XLTS U3932 ( .A0(n3243), .A1(DMP_SHT2_EWSW[39]), .B0(n3250), .B1(
DMP_SFG[39]), .Y(n1490) );
AO22XLTS U3933 ( .A0(n3246), .A1(DmP_mant_SFG_SWR[17]), .B0(n3245), .B1(
n3152), .Y(n1139) );
AO22XLTS U3934 ( .A0(n3187), .A1(DmP_mant_SFG_SWR[21]), .B0(n3228), .B1(
n3153), .Y(n1135) );
AO22XLTS U3935 ( .A0(n3187), .A1(DmP_mant_SFG_SWR[27]), .B0(n3228), .B1(
n3154), .Y(n1129) );
AO22XLTS U3936 ( .A0(n3257), .A1(DMP_SHT2_EWSW[41]), .B0(n3225), .B1(
DMP_SFG[41]), .Y(n1484) );
AO22XLTS U3937 ( .A0(n3177), .A1(DmP_mant_SFG_SWR[49]), .B0(n3224), .B1(
n3155), .Y(n1107) );
AO22XLTS U3938 ( .A0(n3175), .A1(intDX_EWSW[9]), .B0(n3231), .B1(Data_X[9]),
.Y(n1874) );
AO22XLTS U3939 ( .A0(n3241), .A1(intDX_EWSW[37]), .B0(n3240), .B1(Data_X[37]), .Y(n1846) );
AO22XLTS U3940 ( .A0(n3256), .A1(DMP_SHT2_EWSW[43]), .B0(n3227), .B1(
DMP_SFG[43]), .Y(n1478) );
AO22XLTS U3941 ( .A0(n3198), .A1(intDY_EWSW[14]), .B0(n3194), .B1(Data_Y[14]), .Y(n1804) );
AO22XLTS U3942 ( .A0(n3232), .A1(intDX_EWSW[58]), .B0(n3231), .B1(Data_X[58]), .Y(n1825) );
AO22XLTS U3943 ( .A0(n3249), .A1(DMP_SHT2_EWSW[45]), .B0(n3190), .B1(
DMP_SFG[45]), .Y(n1472) );
AO22XLTS U3944 ( .A0(n3249), .A1(DMP_SHT2_EWSW[47]), .B0(n3227), .B1(
DMP_SFG[47]), .Y(n1466) );
AO22XLTS U3945 ( .A0(n3239), .A1(intDX_EWSW[4]), .B0(n3235), .B1(Data_X[4]),
.Y(n1879) );
AO22XLTS U3946 ( .A0(n3241), .A1(intDX_EWSW[30]), .B0(n3196), .B1(Data_X[30]), .Y(n1853) );
AO22XLTS U3947 ( .A0(n3249), .A1(DMP_SHT2_EWSW[49]), .B0(n3255), .B1(
DMP_SFG[49]), .Y(n1460) );
AO22XLTS U3948 ( .A0(n3193), .A1(intDY_EWSW[27]), .B0(n3184), .B1(Data_Y[27]), .Y(n1791) );
AO22XLTS U3949 ( .A0(n3193), .A1(intDY_EWSW[37]), .B0(n3233), .B1(Data_Y[37]), .Y(n1781) );
AO22XLTS U3950 ( .A0(n3198), .A1(intDY_EWSW[13]), .B0(n3184), .B1(Data_Y[13]), .Y(n1805) );
INVX2TS U3951 ( .A(n3158), .Y(n3319) );
NAND2X1TS U3952 ( .A(n3319), .B(n3159), .Y(n1892) );
AO22XLTS U3953 ( .A0(n3246), .A1(DmP_mant_SFG_SWR[12]), .B0(n3245), .B1(
n3160), .Y(n1144) );
AO22XLTS U3954 ( .A0(n3170), .A1(Data_X[11]), .B0(n3172), .B1(intDX_EWSW[11]), .Y(n1872) );
AO22XLTS U3955 ( .A0(n3170), .A1(Data_X[25]), .B0(n3251), .B1(intDX_EWSW[25]), .Y(n1858) );
INVX2TS U3956 ( .A(n2939), .Y(n3230) );
AO22XLTS U3957 ( .A0(n3230), .A1(intDX_EWSW[3]), .B0(n3235), .B1(Data_X[3]),
.Y(n1880) );
AO22XLTS U3958 ( .A0(n3230), .A1(intDX_EWSW[7]), .B0(n3235), .B1(Data_X[7]),
.Y(n1876) );
AO22XLTS U3959 ( .A0(n3175), .A1(intDX_EWSW[14]), .B0(n3229), .B1(Data_X[14]), .Y(n1869) );
AO22XLTS U3960 ( .A0(n3173), .A1(Data_X[59]), .B0(n3175), .B1(intDX_EWSW[59]), .Y(n1824) );
AO22XLTS U3961 ( .A0(n3175), .A1(intDX_EWSW[22]), .B0(n3196), .B1(Data_X[22]), .Y(n1861) );
AO22XLTS U3962 ( .A0(n3195), .A1(intDY_EWSW[2]), .B0(n3197), .B1(Data_Y[2]),
.Y(n1816) );
AO22XLTS U3963 ( .A0(n3195), .A1(intDY_EWSW[9]), .B0(n3194), .B1(Data_Y[9]),
.Y(n1809) );
CLKBUFX2TS U3964 ( .A(n3903), .Y(n3476) );
NOR2XLTS U3965 ( .A(n3165), .B(n3476), .Y(n3162) );
AOI21X1TS U3966 ( .A0(n3686), .A1(n3878), .B0(n3332), .Y(n3161) );
XNOR2X1TS U3967 ( .A(n3162), .B(n3161), .Y(n3163) );
AOI2BB2XLTS U3968 ( .B0(n3343), .B1(n3163), .A0N(Raw_mant_NRM_SWR[2]), .A1N(
Shift_reg_FLAGS_7[2]), .Y(n1267) );
AO22XLTS U3969 ( .A0(n3237), .A1(intDY_EWSW[50]), .B0(n3236), .B1(Data_Y[50]), .Y(n1768) );
AO22XLTS U3970 ( .A0(n3193), .A1(intDY_EWSW[34]), .B0(n3233), .B1(Data_Y[34]), .Y(n1784) );
INVX2TS U3971 ( .A(n3164), .Y(n3238) );
AO22XLTS U3972 ( .A0(n3164), .A1(DMP_SFG[0]), .B0(n3238), .B1(
DMP_SHT2_EWSW[0]), .Y(n1607) );
AO22XLTS U3973 ( .A0(n3173), .A1(Data_X[32]), .B0(n3251), .B1(intDX_EWSW[32]), .Y(n1851) );
AO22XLTS U3974 ( .A0(n3232), .A1(intDX_EWSW[53]), .B0(n3231), .B1(Data_X[53]), .Y(n1830) );
AO22XLTS U3975 ( .A0(n3198), .A1(intDY_EWSW[21]), .B0(n3184), .B1(Data_Y[21]), .Y(n1797) );
AO22XLTS U3976 ( .A0(n3239), .A1(intDX_EWSW[8]), .B0(n3229), .B1(Data_X[8]),
.Y(n1875) );
AO22XLTS U3977 ( .A0(n3175), .A1(intDX_EWSW[12]), .B0(n3229), .B1(Data_X[12]), .Y(n1871) );
AO22XLTS U3978 ( .A0(n3239), .A1(intDX_EWSW[28]), .B0(n3196), .B1(Data_X[28]), .Y(n1855) );
AO22XLTS U3979 ( .A0(n3230), .A1(intDX_EWSW[34]), .B0(n3196), .B1(Data_X[34]), .Y(n1849) );
AO22XLTS U3980 ( .A0(n3170), .A1(Data_X[40]), .B0(n3251), .B1(intDX_EWSW[40]), .Y(n1843) );
AO22XLTS U3981 ( .A0(n3241), .A1(intDX_EWSW[42]), .B0(n3240), .B1(Data_X[42]), .Y(n1841) );
AO22XLTS U3982 ( .A0(n3241), .A1(intDX_EWSW[50]), .B0(n3240), .B1(Data_X[50]), .Y(n1833) );
AO22XLTS U3983 ( .A0(n3195), .A1(intDY_EWSW[4]), .B0(n3194), .B1(Data_Y[4]),
.Y(n1814) );
NOR2X1TS U3984 ( .A(DMP_SFG[5]), .B(n3766), .Y(n3356) );
NAND2X1TS U3985 ( .A(DmP_mant_SFG_SWR[6]), .B(n3718), .Y(n3352) );
NOR2X1TS U3986 ( .A(DMP_SFG[3]), .B(n3842), .Y(n3344) );
NAND2X1TS U3987 ( .A(DmP_mant_SFG_SWR[4]), .B(n3717), .Y(n3339) );
NOR2X1TS U3988 ( .A(DMP_SFG[1]), .B(n3765), .Y(n3331) );
OAI2BB2X1TS U3989 ( .B0(n3333), .B1(n3331), .A0N(n3765), .A1N(DMP_SFG[1]),
.Y(n3338) );
AOI22X1TS U3990 ( .A0(DMP_SFG[2]), .A1(n3808), .B0(n3339), .B1(n3338), .Y(
n3346) );
OAI2BB2X1TS U3991 ( .B0(n3344), .B1(n3346), .A0N(n3842), .A1N(DMP_SFG[3]),
.Y(n3351) );
AOI22X1TS U3992 ( .A0(DMP_SFG[4]), .A1(n3809), .B0(n3352), .B1(n3351), .Y(
n3358) );
OAI2BB2X1TS U3993 ( .B0(n3356), .B1(n3358), .A0N(n3766), .A1N(DMP_SFG[5]),
.Y(n3362) );
AOI22X1TS U3994 ( .A0(n3675), .A1(n3362), .B0(n3166), .B1(n3584), .Y(n3168)
);
NAND2X1TS U3995 ( .A(DmP_mant_SFG_SWR[8]), .B(n3781), .Y(n3363) );
XNOR2X1TS U3996 ( .A(n3168), .B(n3167), .Y(n3169) );
INVX2TS U3997 ( .A(n3629), .Y(n3278) );
AOI2BB2XLTS U3998 ( .B0(n3343), .B1(n3169), .A0N(Raw_mant_NRM_SWR[8]), .A1N(
n3278), .Y(n1261) );
AO22XLTS U3999 ( .A0(n3195), .A1(intDY_EWSW[8]), .B0(n3194), .B1(Data_Y[8]),
.Y(n1810) );
AO22XLTS U4000 ( .A0(n3193), .A1(intDY_EWSW[28]), .B0(n3197), .B1(Data_Y[28]), .Y(n1790) );
AO22XLTS U4001 ( .A0(n3234), .A1(intDY_EWSW[38]), .B0(n3197), .B1(Data_Y[38]), .Y(n1780) );
AO22XLTS U4002 ( .A0(n3234), .A1(intDY_EWSW[45]), .B0(n3197), .B1(Data_Y[45]), .Y(n1773) );
AO22XLTS U4003 ( .A0(n3170), .A1(Data_X[43]), .B0(n3271), .B1(intDX_EWSW[43]), .Y(n1840) );
AO22XLTS U4004 ( .A0(n3171), .A1(Data_X[35]), .B0(n3172), .B1(intDX_EWSW[35]), .Y(n1848) );
AO22XLTS U4005 ( .A0(n3234), .A1(intDY_EWSW[42]), .B0(n3233), .B1(Data_Y[42]), .Y(n1776) );
AO22XLTS U4006 ( .A0(n3237), .A1(intDY_EWSW[61]), .B0(n3236), .B1(Data_Y[61]), .Y(n1757) );
AO22XLTS U4007 ( .A0(n3230), .A1(intDX_EWSW[31]), .B0(n3196), .B1(Data_X[31]), .Y(n1852) );
AO22XLTS U4008 ( .A0(n3173), .A1(Data_X[51]), .B0(n3172), .B1(intDX_EWSW[51]), .Y(n1832) );
AO22XLTS U4009 ( .A0(n3239), .A1(intDX_EWSW[36]), .B0(n3196), .B1(Data_X[36]), .Y(n1847) );
AO22XLTS U4010 ( .A0(n3241), .A1(intDX_EWSW[44]), .B0(n3240), .B1(Data_X[44]), .Y(n1839) );
AO22XLTS U4011 ( .A0(n3232), .A1(intDX_EWSW[57]), .B0(n3231), .B1(Data_X[57]), .Y(n1826) );
AO22XLTS U4012 ( .A0(n3174), .A1(Data_Y[23]), .B0(n3251), .B1(intDY_EWSW[23]), .Y(n1795) );
AO22XLTS U4013 ( .A0(n3175), .A1(intDX_EWSW[20]), .B0(n3229), .B1(Data_X[20]), .Y(n1863) );
AO22XLTS U4014 ( .A0(n3230), .A1(intDX_EWSW[29]), .B0(n3196), .B1(Data_X[29]), .Y(n1854) );
AO22XLTS U4015 ( .A0(n3239), .A1(intDX_EWSW[39]), .B0(n3240), .B1(Data_X[39]), .Y(n1844) );
AO22XLTS U4016 ( .A0(n3198), .A1(intDY_EWSW[20]), .B0(n3229), .B1(Data_Y[20]), .Y(n1798) );
AO22XLTS U4017 ( .A0(n3198), .A1(intDY_EWSW[22]), .B0(n3184), .B1(Data_Y[22]), .Y(n1796) );
AO22XLTS U4018 ( .A0(n3234), .A1(intDY_EWSW[44]), .B0(n3233), .B1(Data_Y[44]), .Y(n1774) );
AO22XLTS U4019 ( .A0(n3323), .A1(n3278), .B0(n3325), .B1(
Shift_reg_FLAGS_7[3]), .Y(n1886) );
AO22XLTS U4020 ( .A0(n3198), .A1(intDY_EWSW[16]), .B0(n3184), .B1(Data_Y[16]), .Y(n1802) );
AO22XLTS U4021 ( .A0(n3232), .A1(intDX_EWSW[27]), .B0(n3196), .B1(Data_X[27]), .Y(n1856) );
AO22XLTS U4022 ( .A0(n3239), .A1(intDX_EWSW[13]), .B0(n3235), .B1(Data_X[13]), .Y(n1870) );
AO22XLTS U4023 ( .A0(n3175), .A1(intDX_EWSW[18]), .B0(n3235), .B1(Data_X[18]), .Y(n1865) );
AO22XLTS U4024 ( .A0(n3237), .A1(intDX_EWSW[0]), .B0(n3236), .B1(Data_X[0]),
.Y(n1883) );
AO22XLTS U4025 ( .A0(n3230), .A1(intDX_EWSW[5]), .B0(n3229), .B1(Data_X[5]),
.Y(n1878) );
AO22XLTS U4026 ( .A0(n3198), .A1(intDY_EWSW[26]), .B0(n3197), .B1(Data_Y[26]), .Y(n1792) );
INVX2TS U4027 ( .A(n3176), .Y(n3205) );
AO22XLTS U4028 ( .A0(n3225), .A1(DMP_SFG[2]), .B0(n3224), .B1(
DMP_SHT2_EWSW[2]), .Y(n1601) );
AO22XLTS U4029 ( .A0(n3227), .A1(DMP_SFG[4]), .B0(n3224), .B1(
DMP_SHT2_EWSW[4]), .Y(n1595) );
AO22XLTS U4030 ( .A0(n3227), .A1(DMP_SFG[10]), .B0(n3256), .B1(
DMP_SHT2_EWSW[10]), .Y(n1577) );
AO22XLTS U4031 ( .A0(n3164), .A1(DMP_SFG[12]), .B0(n3256), .B1(
DMP_SHT2_EWSW[12]), .Y(n1571) );
AO22XLTS U4032 ( .A0(n3190), .A1(DMP_SFG[14]), .B0(n3226), .B1(
DMP_SHT2_EWSW[14]), .Y(n1565) );
AO22XLTS U4033 ( .A0(n3225), .A1(DMP_SFG[16]), .B0(n3228), .B1(
DMP_SHT2_EWSW[16]), .Y(n1559) );
AO22XLTS U4034 ( .A0(n3225), .A1(DMP_SFG[18]), .B0(n3238), .B1(
DMP_SHT2_EWSW[18]), .Y(n1553) );
AO22XLTS U4035 ( .A0(n3227), .A1(DMP_SFG[20]), .B0(n3245), .B1(
DMP_SHT2_EWSW[20]), .Y(n1547) );
AO22XLTS U4036 ( .A0(n3227), .A1(DMP_SFG[30]), .B0(n3245), .B1(
DMP_SHT2_EWSW[30]), .Y(n1517) );
AO22XLTS U4037 ( .A0(n3255), .A1(DMP_SFG[46]), .B0(n3228), .B1(
DMP_SHT2_EWSW[46]), .Y(n1469) );
INVX2TS U4038 ( .A(n3177), .Y(n3178) );
AO22XLTS U4039 ( .A0(n3225), .A1(DMP_SFG[48]), .B0(n3178), .B1(
DMP_SHT2_EWSW[48]), .Y(n1463) );
AO22XLTS U4040 ( .A0(n3246), .A1(n3451), .B0(n3238), .B1(OP_FLAG_SHT2), .Y(
n1278) );
AO22XLTS U4041 ( .A0(n3195), .A1(intDY_EWSW[10]), .B0(n3194), .B1(Data_Y[10]), .Y(n1808) );
AO22XLTS U4042 ( .A0(n3187), .A1(DmP_mant_SFG_SWR[34]), .B0(n3226), .B1(
n3179), .Y(n1122) );
AO22XLTS U4043 ( .A0(n3187), .A1(DmP_mant_SFG_SWR[36]), .B0(n3226), .B1(
n3180), .Y(n1120) );
AO22XLTS U4044 ( .A0(n3190), .A1(DmP_mant_SFG_SWR[38]), .B0(n3226), .B1(
n3181), .Y(n1118) );
AO22XLTS U4045 ( .A0(n3190), .A1(DmP_mant_SFG_SWR[40]), .B0(n3226), .B1(
n3182), .Y(n1116) );
AO22XLTS U4046 ( .A0(n3190), .A1(DmP_mant_SFG_SWR[42]), .B0(n3224), .B1(
n3183), .Y(n1114) );
AO22XLTS U4047 ( .A0(n3195), .A1(intDY_EWSW[3]), .B0(n3194), .B1(Data_Y[3]),
.Y(n1815) );
AO22XLTS U4048 ( .A0(n3234), .A1(intDY_EWSW[39]), .B0(n3184), .B1(Data_Y[39]), .Y(n1779) );
AO22XLTS U4049 ( .A0(n3232), .A1(intDX_EWSW[55]), .B0(n3231), .B1(Data_X[55]), .Y(n1828) );
AO22XLTS U4050 ( .A0(n3187), .A1(DmP_mant_SFG_SWR[33]), .B0(n3228), .B1(
n3185), .Y(n1123) );
AO22XLTS U4051 ( .A0(n3187), .A1(DmP_mant_SFG_SWR[37]), .B0(n3228), .B1(
n3186), .Y(n1119) );
AO22XLTS U4052 ( .A0(n3190), .A1(DmP_mant_SFG_SWR[39]), .B0(n3224), .B1(
n3188), .Y(n1117) );
AO22XLTS U4053 ( .A0(n3190), .A1(DmP_mant_SFG_SWR[41]), .B0(n3224), .B1(
n3189), .Y(n1115) );
AO22XLTS U4054 ( .A0(n3232), .A1(intDX_EWSW[62]), .B0(n3231), .B1(Data_X[62]), .Y(n1821) );
AO22XLTS U4055 ( .A0(n3230), .A1(intDX_EWSW[2]), .B0(n3229), .B1(Data_X[2]),
.Y(n1881) );
AO22XLTS U4056 ( .A0(n3193), .A1(intDY_EWSW[32]), .B0(n3233), .B1(Data_Y[32]), .Y(n1786) );
AO22XLTS U4057 ( .A0(n3193), .A1(intDY_EWSW[29]), .B0(n3197), .B1(Data_Y[29]), .Y(n1789) );
AO22XLTS U4058 ( .A0(n3195), .A1(intDY_EWSW[11]), .B0(n3194), .B1(Data_Y[11]), .Y(n1807) );
AO22XLTS U4059 ( .A0(n3257), .A1(DMP_SHT2_EWSW[27]), .B0(n3250), .B1(
DMP_SFG[27]), .Y(n1526) );
AO22XLTS U4060 ( .A0(n3239), .A1(intDX_EWSW[21]), .B0(n3196), .B1(Data_X[21]), .Y(n1862) );
AO22XLTS U4061 ( .A0(n3198), .A1(intDY_EWSW[24]), .B0(n3197), .B1(Data_Y[24]), .Y(n1794) );
AO22XLTS U4062 ( .A0(n3237), .A1(intDY_EWSW[54]), .B0(n3233), .B1(Data_Y[54]), .Y(n1764) );
INVX2TS U4063 ( .A(n3199), .Y(n3220) );
INVX2TS U4064 ( .A(n3200), .Y(n3218) );
INVX2TS U4065 ( .A(n3201), .Y(n3215) );
INVX2TS U4066 ( .A(n3203), .Y(n3213) );
INVX2TS U4067 ( .A(n3206), .Y(n3210) );
INVX2TS U4068 ( .A(n3207), .Y(n3208) );
OAI222X1TS U4069 ( .A0(n3202), .A1(n3215), .B0(n1975), .B1(n3214), .C0(n3775), .C1(n3305), .Y(n1111) );
OAI222X1TS U4070 ( .A0(n3209), .A1(n3218), .B0(n3212), .B1(n3217), .C0(n3776), .C1(n3216), .Y(n1109) );
OAI222X1TS U4071 ( .A0(n3223), .A1(n3222), .B0(n3221), .B1(n3220), .C0(n3777), .C1(n3219), .Y(n1105) );
AO22XLTS U4072 ( .A0(n3232), .A1(intDX_EWSW[52]), .B0(n3231), .B1(Data_X[52]), .Y(n1831) );
AO22XLTS U4073 ( .A0(n3232), .A1(intDX_EWSW[56]), .B0(n3231), .B1(Data_X[56]), .Y(n1827) );
AO22XLTS U4074 ( .A0(n3145), .A1(DMP_SFG[6]), .B0(n3224), .B1(
DMP_SHT2_EWSW[6]), .Y(n1589) );
AO22XLTS U4075 ( .A0(n3225), .A1(DMP_SFG[8]), .B0(n3224), .B1(
DMP_SHT2_EWSW[8]), .Y(n1583) );
AO22XLTS U4076 ( .A0(n3164), .A1(DMP_SFG[22]), .B0(n3238), .B1(
DMP_SHT2_EWSW[22]), .Y(n1541) );
AO22XLTS U4077 ( .A0(n3227), .A1(DMP_SFG[24]), .B0(n3245), .B1(
DMP_SHT2_EWSW[24]), .Y(n1535) );
AO22XLTS U4078 ( .A0(n3225), .A1(DMP_SFG[26]), .B0(n3238), .B1(
DMP_SHT2_EWSW[26]), .Y(n1529) );
AO22XLTS U4079 ( .A0(n3225), .A1(DMP_SFG[28]), .B0(n3238), .B1(
DMP_SHT2_EWSW[28]), .Y(n1523) );
AO22XLTS U4080 ( .A0(n3250), .A1(DMP_SFG[32]), .B0(n3228), .B1(
DMP_SHT2_EWSW[32]), .Y(n1511) );
AO22XLTS U4081 ( .A0(n3243), .A1(DMP_SHT2_EWSW[1]), .B0(n3255), .B1(
DMP_SFG[1]), .Y(n1604) );
AO22XLTS U4082 ( .A0(n3227), .A1(DMP_SFG[34]), .B0(n3226), .B1(
DMP_SHT2_EWSW[34]), .Y(n1505) );
AO22XLTS U4083 ( .A0(n3255), .A1(DMP_SFG[36]), .B0(n3228), .B1(
DMP_SHT2_EWSW[36]), .Y(n1499) );
AO22XLTS U4084 ( .A0(n3225), .A1(DMP_SFG[38]), .B0(n3245), .B1(
DMP_SHT2_EWSW[38]), .Y(n1493) );
AO22XLTS U4085 ( .A0(n3256), .A1(DMP_SHT2_EWSW[3]), .B0(n3255), .B1(
DMP_SFG[3]), .Y(n1598) );
AO22XLTS U4086 ( .A0(n3250), .A1(DMP_SFG[40]), .B0(n3238), .B1(
DMP_SHT2_EWSW[40]), .Y(n1487) );
AO22XLTS U4087 ( .A0(n3227), .A1(DMP_SFG[42]), .B0(n3238), .B1(
DMP_SHT2_EWSW[42]), .Y(n1481) );
AO22XLTS U4088 ( .A0(n3145), .A1(DMP_SFG[44]), .B0(n3238), .B1(
DMP_SHT2_EWSW[44]), .Y(n1475) );
AO22XLTS U4089 ( .A0(n3243), .A1(DMP_SHT2_EWSW[5]), .B0(n3255), .B1(
DMP_SFG[5]), .Y(n1592) );
AO22XLTS U4090 ( .A0(n3164), .A1(DMP_SFG[50]), .B0(n3228), .B1(
DMP_SHT2_EWSW[50]), .Y(n1457) );
AO22XLTS U4091 ( .A0(n3230), .A1(intDX_EWSW[1]), .B0(n3235), .B1(Data_X[1]),
.Y(n1882) );
AO22XLTS U4092 ( .A0(n3230), .A1(intDX_EWSW[15]), .B0(n3229), .B1(Data_X[15]), .Y(n1868) );
AO22XLTS U4093 ( .A0(n3243), .A1(DMP_SHT2_EWSW[7]), .B0(n3252), .B1(
DMP_SFG[7]), .Y(n1586) );
AO22XLTS U4094 ( .A0(n3230), .A1(intDX_EWSW[17]), .B0(n3229), .B1(Data_X[17]), .Y(n1866) );
AO22XLTS U4095 ( .A0(n3241), .A1(intDX_EWSW[49]), .B0(n3240), .B1(Data_X[49]), .Y(n1834) );
AO22XLTS U4096 ( .A0(n3232), .A1(intDX_EWSW[60]), .B0(n3231), .B1(Data_X[60]), .Y(n1823) );
AO22XLTS U4097 ( .A0(n3249), .A1(DMP_SHT2_EWSW[9]), .B0(n3252), .B1(
DMP_SFG[9]), .Y(n1580) );
AO22XLTS U4098 ( .A0(n3234), .A1(intDY_EWSW[47]), .B0(n3233), .B1(Data_Y[47]), .Y(n1771) );
AO22XLTS U4099 ( .A0(n3241), .A1(intDX_EWSW[19]), .B0(n3235), .B1(Data_X[19]), .Y(n1864) );
AO22XLTS U4100 ( .A0(n3237), .A1(intDY_EWSW[57]), .B0(n3236), .B1(Data_Y[57]), .Y(n1761) );
AO22XLTS U4101 ( .A0(n3256), .A1(DMP_SHT2_EWSW[11]), .B0(n3255), .B1(
DMP_SFG[11]), .Y(n1574) );
AO22XLTS U4102 ( .A0(n3246), .A1(DMP_SFG[51]), .B0(n3238), .B1(
DMP_SHT2_EWSW[51]), .Y(n1454) );
AO22XLTS U4103 ( .A0(n3249), .A1(DMP_SHT2_EWSW[13]), .B0(n3252), .B1(
DMP_SFG[13]), .Y(n1568) );
AO22XLTS U4104 ( .A0(n3239), .A1(intDX_EWSW[38]), .B0(n3240), .B1(Data_X[38]), .Y(n1845) );
AO22XLTS U4105 ( .A0(n3241), .A1(intDX_EWSW[45]), .B0(n3240), .B1(Data_X[45]), .Y(n1838) );
AO22XLTS U4106 ( .A0(n3246), .A1(DmP_mant_SFG_SWR[4]), .B0(n3245), .B1(n3242), .Y(n1152) );
AO22XLTS U4107 ( .A0(n3243), .A1(DMP_SHT2_EWSW[15]), .B0(n3252), .B1(
DMP_SFG[15]), .Y(n1562) );
AO22XLTS U4108 ( .A0(n3246), .A1(DmP_mant_SFG_SWR[6]), .B0(n3245), .B1(n3244), .Y(n1150) );
AO22XLTS U4109 ( .A0(n3248), .A1(DmP_EXP_EWSW[33]), .B0(n3912), .B1(
DmP_mant_SHT1_SW[33]), .Y(n1331) );
AO22XLTS U4110 ( .A0(n3248), .A1(DmP_EXP_EWSW[34]), .B0(n3303), .B1(
DmP_mant_SHT1_SW[34]), .Y(n1329) );
AO22XLTS U4111 ( .A0(n3248), .A1(DmP_EXP_EWSW[35]), .B0(n3298), .B1(
DmP_mant_SHT1_SW[35]), .Y(n1327) );
AO21XLTS U4112 ( .A0(LZD_output_NRM2_EW[0]), .A1(n3749), .B0(n3247), .Y(
n1210) );
AO22XLTS U4113 ( .A0(n3248), .A1(DmP_EXP_EWSW[36]), .B0(n3912), .B1(
DmP_mant_SHT1_SW[36]), .Y(n1325) );
AO22XLTS U4114 ( .A0(n3343), .A1(SIGN_FLAG_SFG), .B0(n3629), .B1(
SIGN_FLAG_NRM), .Y(n1272) );
AO22XLTS U4115 ( .A0(n3249), .A1(SIGN_FLAG_SHT2), .B0(n3250), .B1(
SIGN_FLAG_SFG), .Y(n1273) );
AO22XLTS U4116 ( .A0(n3248), .A1(DmP_EXP_EWSW[37]), .B0(n3912), .B1(
DmP_mant_SHT1_SW[37]), .Y(n1323) );
AO22XLTS U4117 ( .A0(n3295), .A1(SIGN_FLAG_SHT1), .B0(n3299), .B1(
SIGN_FLAG_SHT2), .Y(n1274) );
AO22XLTS U4118 ( .A0(n3248), .A1(DmP_EXP_EWSW[38]), .B0(n3297), .B1(
DmP_mant_SHT1_SW[38]), .Y(n1321) );
CLKBUFX3TS U4119 ( .A(n3298), .Y(n3311) );
AO22XLTS U4120 ( .A0(Shift_reg_FLAGS_7_5), .A1(SIGN_FLAG_EXP), .B0(n3311),
.B1(SIGN_FLAG_SHT1), .Y(n1275) );
AO22XLTS U4121 ( .A0(Shift_reg_FLAGS_7_5), .A1(OP_FLAG_EXP), .B0(n3301),
.B1(OP_FLAG_SHT1), .Y(n1280) );
AO22XLTS U4122 ( .A0(n2042), .A1(ZERO_FLAG_NRM), .B0(n2345), .B1(
ZERO_FLAG_SHT1SHT2), .Y(n1282) );
AO22XLTS U4123 ( .A0(n3343), .A1(ZERO_FLAG_SFG), .B0(n3913), .B1(
ZERO_FLAG_NRM), .Y(n1283) );
INVX2TS U4124 ( .A(n3297), .Y(n3253) );
AO22XLTS U4125 ( .A0(n3253), .A1(DmP_EXP_EWSW[41]), .B0(n3302), .B1(
DmP_mant_SHT1_SW[41]), .Y(n1315) );
AO22XLTS U4126 ( .A0(n3249), .A1(ZERO_FLAG_SHT2), .B0(n3250), .B1(
ZERO_FLAG_SFG), .Y(n1284) );
AO22XLTS U4127 ( .A0(n3295), .A1(ZERO_FLAG_SHT1), .B0(n3299), .B1(
ZERO_FLAG_SHT2), .Y(n1285) );
AO22XLTS U4128 ( .A0(n3253), .A1(DmP_EXP_EWSW[42]), .B0(n3298), .B1(
DmP_mant_SHT1_SW[42]), .Y(n1313) );
AO22XLTS U4129 ( .A0(Shift_reg_FLAGS_7_5), .A1(ZERO_FLAG_EXP), .B0(n3301),
.B1(ZERO_FLAG_SHT1), .Y(n1286) );
AO22XLTS U4130 ( .A0(n3253), .A1(DmP_EXP_EWSW[43]), .B0(n3296), .B1(
DmP_mant_SHT1_SW[43]), .Y(n1311) );
AO22XLTS U4131 ( .A0(n3257), .A1(DMP_SHT2_EWSW[62]), .B0(n3255), .B1(
DMP_SFG[62]), .Y(n1401) );
AO22XLTS U4132 ( .A0(n3253), .A1(DmP_EXP_EWSW[44]), .B0(n3303), .B1(
DmP_mant_SHT1_SW[44]), .Y(n1309) );
AO22XLTS U4133 ( .A0(n3295), .A1(DMP_SHT1_EWSW[62]), .B0(n3299), .B1(
DMP_SHT2_EWSW[62]), .Y(n1402) );
AO22XLTS U4134 ( .A0(n3253), .A1(DmP_EXP_EWSW[45]), .B0(n3298), .B1(
DmP_mant_SHT1_SW[45]), .Y(n1307) );
INVX2TS U4135 ( .A(n3301), .Y(n3273) );
CLKBUFX3TS U4136 ( .A(n3298), .Y(n3277) );
AO22XLTS U4137 ( .A0(n3273), .A1(DMP_EXP_EWSW[62]), .B0(n3277), .B1(
DMP_SHT1_EWSW[62]), .Y(n1403) );
AO22XLTS U4138 ( .A0(n3256), .A1(DMP_SHT2_EWSW[61]), .B0(n3250), .B1(
DMP_SFG[61]), .Y(n1406) );
AO22XLTS U4139 ( .A0(n3253), .A1(DmP_EXP_EWSW[46]), .B0(n3321), .B1(
DmP_mant_SHT1_SW[46]), .Y(n1305) );
AO22XLTS U4140 ( .A0(n3272), .A1(Data_Y[63]), .B0(n3251), .B1(intDY_EWSW[63]), .Y(n1755) );
AO22XLTS U4141 ( .A0(n3253), .A1(DmP_EXP_EWSW[47]), .B0(n3301), .B1(
DmP_mant_SHT1_SW[47]), .Y(n1303) );
AO22XLTS U4142 ( .A0(n3273), .A1(DMP_EXP_EWSW[61]), .B0(n3277), .B1(
DMP_SHT1_EWSW[61]), .Y(n1408) );
AO22XLTS U4143 ( .A0(n3257), .A1(DMP_SHT2_EWSW[60]), .B0(n3304), .B1(
DMP_SFG[60]), .Y(n1411) );
AO22XLTS U4144 ( .A0(n3253), .A1(DmP_EXP_EWSW[48]), .B0(n3302), .B1(
DmP_mant_SHT1_SW[48]), .Y(n1301) );
AO22XLTS U4145 ( .A0(n3295), .A1(DMP_SHT1_EWSW[60]), .B0(n3299), .B1(
DMP_SHT2_EWSW[60]), .Y(n1412) );
AO22XLTS U4146 ( .A0(n3253), .A1(DmP_EXP_EWSW[49]), .B0(n3321), .B1(
DmP_mant_SHT1_SW[49]), .Y(n1299) );
AO22XLTS U4147 ( .A0(n3273), .A1(DMP_EXP_EWSW[60]), .B0(n3277), .B1(
DMP_SHT1_EWSW[60]), .Y(n1413) );
AO22XLTS U4148 ( .A0(n3257), .A1(DMP_SHT2_EWSW[59]), .B0(n3252), .B1(
DMP_SFG[59]), .Y(n1416) );
AO22XLTS U4149 ( .A0(n3253), .A1(DmP_EXP_EWSW[50]), .B0(n3301), .B1(
DmP_mant_SHT1_SW[50]), .Y(n1297) );
AO22XLTS U4150 ( .A0(n3295), .A1(DMP_SHT1_EWSW[59]), .B0(n3299), .B1(
DMP_SHT2_EWSW[59]), .Y(n1417) );
AO22XLTS U4151 ( .A0(n3273), .A1(DMP_EXP_EWSW[59]), .B0(n3277), .B1(
DMP_SHT1_EWSW[59]), .Y(n1418) );
AO22XLTS U4152 ( .A0(n3257), .A1(DMP_SHT2_EWSW[58]), .B0(n3304), .B1(
DMP_SFG[58]), .Y(n1421) );
AO22XLTS U4153 ( .A0(n3295), .A1(DMP_SHT1_EWSW[58]), .B0(n3299), .B1(
DMP_SHT2_EWSW[58]), .Y(n1422) );
AO22XLTS U4154 ( .A0(n3273), .A1(DMP_EXP_EWSW[58]), .B0(n3311), .B1(
DMP_SHT1_EWSW[58]), .Y(n1423) );
AO22XLTS U4155 ( .A0(n3257), .A1(DMP_SHT2_EWSW[57]), .B0(n3304), .B1(
DMP_SFG[57]), .Y(n1426) );
AO22XLTS U4156 ( .A0(n3295), .A1(DMP_SHT1_EWSW[57]), .B0(n3254), .B1(
DMP_SHT2_EWSW[57]), .Y(n1427) );
AO22XLTS U4157 ( .A0(n3273), .A1(DMP_EXP_EWSW[57]), .B0(n3311), .B1(
DMP_SHT1_EWSW[57]), .Y(n1428) );
AO22XLTS U4158 ( .A0(n3256), .A1(DMP_SHT2_EWSW[56]), .B0(n3304), .B1(
DMP_SFG[56]), .Y(n1431) );
AO22XLTS U4159 ( .A0(n3314), .A1(DMP_SHT1_EWSW[56]), .B0(n3854), .B1(
DMP_SHT2_EWSW[56]), .Y(n1432) );
AO22XLTS U4160 ( .A0(n3273), .A1(DMP_EXP_EWSW[56]), .B0(n3311), .B1(
DMP_SHT1_EWSW[56]), .Y(n1433) );
AO22XLTS U4161 ( .A0(n3257), .A1(DMP_SHT2_EWSW[55]), .B0(n3304), .B1(
DMP_SFG[55]), .Y(n1436) );
AO22XLTS U4162 ( .A0(n3314), .A1(DMP_SHT1_EWSW[55]), .B0(n3854), .B1(
DMP_SHT2_EWSW[55]), .Y(n1437) );
AO22XLTS U4163 ( .A0(n3273), .A1(DMP_EXP_EWSW[55]), .B0(n3311), .B1(
DMP_SHT1_EWSW[55]), .Y(n1438) );
AO22XLTS U4164 ( .A0(n3256), .A1(DMP_SHT2_EWSW[54]), .B0(n3255), .B1(
DMP_SFG[54]), .Y(n1441) );
AO22XLTS U4165 ( .A0(n3314), .A1(DMP_SHT1_EWSW[54]), .B0(n3313), .B1(
DMP_SHT2_EWSW[54]), .Y(n1442) );
AO22XLTS U4166 ( .A0(n3273), .A1(DMP_EXP_EWSW[54]), .B0(n3311), .B1(
DMP_SHT1_EWSW[54]), .Y(n1443) );
AO22XLTS U4167 ( .A0(n3257), .A1(DMP_SHT2_EWSW[53]), .B0(n3304), .B1(
DMP_SFG[53]), .Y(n1446) );
NAND2X1TS U4168 ( .A(DmP_EXP_EWSW[52]), .B(n3892), .Y(n3274) );
NAND2X1TS U4169 ( .A(DmP_EXP_EWSW[53]), .B(n3893), .Y(n3260) );
XNOR2X1TS U4170 ( .A(n3274), .B(n3258), .Y(n3259) );
AO22XLTS U4171 ( .A0(n3285), .A1(n3259), .B0(n3303), .B1(
Shift_amount_SHT1_EWR[1]), .Y(n1691) );
NOR2X1TS U4172 ( .A(n3837), .B(DMP_EXP_EWSW[54]), .Y(n3263) );
AOI22X1TS U4173 ( .A0(DMP_EXP_EWSW[53]), .A1(n3743), .B0(n3274), .B1(n3260),
.Y(n3265) );
OAI2BB2X1TS U4174 ( .B0(n3263), .B1(n3265), .A0N(n3837), .A1N(
DMP_EXP_EWSW[54]), .Y(n3267) );
NAND2X1TS U4175 ( .A(DmP_EXP_EWSW[55]), .B(n3832), .Y(n3268) );
OAI21XLTS U4176 ( .A0(DmP_EXP_EWSW[55]), .A1(n3832), .B0(n3268), .Y(n3261)
);
XNOR2X1TS U4177 ( .A(n3267), .B(n3261), .Y(n3262) );
AO22XLTS U4178 ( .A0(n3285), .A1(n3262), .B0(n3303), .B1(
Shift_amount_SHT1_EWR[3]), .Y(n1689) );
AOI21X1TS U4179 ( .A0(DMP_EXP_EWSW[54]), .A1(n3837), .B0(n3263), .Y(n3264)
);
XNOR2X1TS U4180 ( .A(n3265), .B(n3264), .Y(n3266) );
AO22XLTS U4181 ( .A0(n3285), .A1(n3266), .B0(n3303), .B1(
Shift_amount_SHT1_EWR[2]), .Y(n1690) );
AOI22X1TS U4182 ( .A0(DMP_EXP_EWSW[55]), .A1(n3857), .B0(n3268), .B1(n3267),
.Y(n3280) );
NOR2X1TS U4183 ( .A(n3838), .B(DMP_EXP_EWSW[56]), .Y(n3281) );
AOI21X1TS U4184 ( .A0(DMP_EXP_EWSW[56]), .A1(n3838), .B0(n3281), .Y(n3269)
);
XNOR2X1TS U4185 ( .A(n3280), .B(n3269), .Y(n3270) );
AO22XLTS U4186 ( .A0(n3285), .A1(n3270), .B0(n3303), .B1(
Shift_amount_SHT1_EWR[4]), .Y(n1688) );
AO22XLTS U4187 ( .A0(n3272), .A1(add_subt), .B0(n3271), .B1(intAS), .Y(n1819) );
AO22XLTS U4188 ( .A0(n3273), .A1(DmP_EXP_EWSW[0]), .B0(n3277), .B1(
DmP_mant_SHT1_SW[0]), .Y(n1397) );
OAI21XLTS U4189 ( .A0(DmP_EXP_EWSW[52]), .A1(n3892), .B0(n3274), .Y(n3275)
);
AO22XLTS U4190 ( .A0(n3285), .A1(n3275), .B0(n3296), .B1(
Shift_amount_SHT1_EWR[0]), .Y(n1692) );
MX2X1TS U4191 ( .A(LZD_output_NRM2_EW[1]), .B(n3276), .S0(n2041), .Y(n1212)
);
INVX2TS U4192 ( .A(n3321), .Y(n3279) );
AO22XLTS U4193 ( .A0(n3279), .A1(DmP_EXP_EWSW[1]), .B0(n3277), .B1(
DmP_mant_SHT1_SW[1]), .Y(n1395) );
AO22XLTS U4194 ( .A0(n3343), .A1(DMP_SFG[62]), .B0(n3622), .B1(
DMP_exp_NRM_EW[10]), .Y(n1400) );
AO22XLTS U4195 ( .A0(n3279), .A1(DmP_EXP_EWSW[2]), .B0(n3277), .B1(
DmP_mant_SHT1_SW[2]), .Y(n1393) );
AO22XLTS U4196 ( .A0(Shift_reg_FLAGS_7[2]), .A1(DMP_SFG[61]), .B0(n3913),
.B1(DMP_exp_NRM_EW[9]), .Y(n1405) );
AO22XLTS U4197 ( .A0(n3343), .A1(DMP_SFG[60]), .B0(n3622), .B1(
DMP_exp_NRM_EW[8]), .Y(n1410) );
AO22XLTS U4198 ( .A0(n3279), .A1(DmP_EXP_EWSW[3]), .B0(n3277), .B1(
DmP_mant_SHT1_SW[3]), .Y(n1391) );
AO22XLTS U4199 ( .A0(Shift_reg_FLAGS_7[2]), .A1(DMP_SFG[59]), .B0(n3913),
.B1(DMP_exp_NRM_EW[7]), .Y(n1415) );
AO22XLTS U4200 ( .A0(n3279), .A1(DmP_EXP_EWSW[4]), .B0(n3277), .B1(
DmP_mant_SHT1_SW[4]), .Y(n1389) );
AO22XLTS U4201 ( .A0(Shift_reg_FLAGS_7[2]), .A1(DMP_SFG[58]), .B0(n3622),
.B1(DMP_exp_NRM_EW[6]), .Y(n1420) );
AO22XLTS U4202 ( .A0(Shift_reg_FLAGS_7[2]), .A1(DMP_SFG[57]), .B0(n3590),
.B1(DMP_exp_NRM_EW[5]), .Y(n1425) );
AO22XLTS U4203 ( .A0(n3279), .A1(DmP_EXP_EWSW[5]), .B0(n3277), .B1(
DmP_mant_SHT1_SW[5]), .Y(n1387) );
AO22XLTS U4204 ( .A0(Shift_reg_FLAGS_7[2]), .A1(DMP_SFG[56]), .B0(n3590),
.B1(DMP_exp_NRM_EW[4]), .Y(n1430) );
AO22XLTS U4205 ( .A0(n3279), .A1(DmP_EXP_EWSW[6]), .B0(n3912), .B1(
DmP_mant_SHT1_SW[6]), .Y(n1385) );
AO22XLTS U4206 ( .A0(n3278), .A1(DMP_SFG[55]), .B0(n3622), .B1(
DMP_exp_NRM_EW[3]), .Y(n1435) );
AO22XLTS U4207 ( .A0(n3279), .A1(DmP_EXP_EWSW[7]), .B0(n3912), .B1(
DmP_mant_SHT1_SW[7]), .Y(n1383) );
AO22XLTS U4208 ( .A0(Shift_reg_FLAGS_7[2]), .A1(DMP_SFG[54]), .B0(n3590),
.B1(DMP_exp_NRM_EW[2]), .Y(n1440) );
AO22XLTS U4209 ( .A0(Shift_reg_FLAGS_7[2]), .A1(DMP_SFG[53]), .B0(n3622),
.B1(DMP_exp_NRM_EW[1]), .Y(n1445) );
AO22XLTS U4210 ( .A0(n3279), .A1(DmP_EXP_EWSW[8]), .B0(n3297), .B1(
DmP_mant_SHT1_SW[8]), .Y(n1381) );
AO22XLTS U4211 ( .A0(n3278), .A1(DMP_SFG[52]), .B0(n3622), .B1(
DMP_exp_NRM_EW[0]), .Y(n1450) );
AO22XLTS U4212 ( .A0(n3279), .A1(DmP_EXP_EWSW[9]), .B0(n3302), .B1(
DmP_mant_SHT1_SW[9]), .Y(n1379) );
AO22XLTS U4213 ( .A0(Shift_reg_FLAGS_7_5), .A1(DmP_EXP_EWSW[51]), .B0(n3301),
.B1(DmP_mant_SHT1_SW[51]), .Y(n1295) );
AO22XLTS U4214 ( .A0(n3288), .A1(DmP_EXP_EWSW[24]), .B0(n3287), .B1(
DmP_mant_SHT1_SW[24]), .Y(n1349) );
AO22XLTS U4215 ( .A0(n3279), .A1(DmP_EXP_EWSW[10]), .B0(n3302), .B1(
DmP_mant_SHT1_SW[10]), .Y(n1377) );
INVX2TS U4216 ( .A(n3296), .Y(n3286) );
AO22XLTS U4217 ( .A0(n3286), .A1(DmP_EXP_EWSW[11]), .B0(n3302), .B1(
DmP_mant_SHT1_SW[11]), .Y(n1375) );
AO22XLTS U4218 ( .A0(n3286), .A1(DmP_EXP_EWSW[12]), .B0(n3297), .B1(
DmP_mant_SHT1_SW[12]), .Y(n1373) );
AO22XLTS U4219 ( .A0(n3286), .A1(DmP_EXP_EWSW[13]), .B0(n3296), .B1(
DmP_mant_SHT1_SW[13]), .Y(n1371) );
AOI2BB2XLTS U4220 ( .B0(DMP_EXP_EWSW[57]), .B1(DmP_EXP_EWSW[57]), .A0N(
DmP_EXP_EWSW[57]), .A1N(DMP_EXP_EWSW[57]), .Y(n3283) );
OAI2BB2XLTS U4221 ( .B0(n3281), .B1(n3280), .A0N(n3838), .A1N(
DMP_EXP_EWSW[56]), .Y(n3282) );
XNOR2X1TS U4222 ( .A(n3283), .B(n3282), .Y(n3284) );
AO22XLTS U4223 ( .A0(n3285), .A1(n3284), .B0(n3303), .B1(
Shift_amount_SHT1_EWR[5]), .Y(n1687) );
AO22XLTS U4224 ( .A0(n2039), .A1(SIGN_FLAG_NRM), .B0(n2038), .B1(
SIGN_FLAG_SHT1SHT2), .Y(n1271) );
AO22XLTS U4225 ( .A0(n3286), .A1(DmP_EXP_EWSW[14]), .B0(n3912), .B1(
DmP_mant_SHT1_SW[14]), .Y(n1369) );
AO22XLTS U4226 ( .A0(n3286), .A1(DmP_EXP_EWSW[15]), .B0(n3298), .B1(
DmP_mant_SHT1_SW[15]), .Y(n1367) );
AO22XLTS U4227 ( .A0(n3286), .A1(DmP_EXP_EWSW[16]), .B0(n3287), .B1(
DmP_mant_SHT1_SW[16]), .Y(n1365) );
AO22XLTS U4228 ( .A0(n3286), .A1(DmP_EXP_EWSW[17]), .B0(n3287), .B1(
DmP_mant_SHT1_SW[17]), .Y(n1363) );
AO22XLTS U4229 ( .A0(n3286), .A1(DmP_EXP_EWSW[18]), .B0(n3287), .B1(
DmP_mant_SHT1_SW[18]), .Y(n1361) );
AO22XLTS U4230 ( .A0(n3286), .A1(DmP_EXP_EWSW[19]), .B0(n3287), .B1(
DmP_mant_SHT1_SW[19]), .Y(n1359) );
AO22XLTS U4231 ( .A0(n3286), .A1(DmP_EXP_EWSW[20]), .B0(n3287), .B1(
DmP_mant_SHT1_SW[20]), .Y(n1357) );
AO22XLTS U4232 ( .A0(n3288), .A1(DmP_EXP_EWSW[21]), .B0(n3287), .B1(
DmP_mant_SHT1_SW[21]), .Y(n1355) );
AO22XLTS U4233 ( .A0(n3288), .A1(DmP_EXP_EWSW[22]), .B0(n3287), .B1(
DmP_mant_SHT1_SW[22]), .Y(n1353) );
AO22XLTS U4234 ( .A0(n3288), .A1(DmP_EXP_EWSW[23]), .B0(n3287), .B1(
DmP_mant_SHT1_SW[23]), .Y(n1351) );
AO22XLTS U4235 ( .A0(n3288), .A1(DmP_EXP_EWSW[26]), .B0(n3298), .B1(
DmP_mant_SHT1_SW[26]), .Y(n1345) );
AO22XLTS U4236 ( .A0(n3288), .A1(DmP_EXP_EWSW[27]), .B0(n3298), .B1(
DmP_mant_SHT1_SW[27]), .Y(n1343) );
AO22XLTS U4237 ( .A0(n3288), .A1(DmP_EXP_EWSW[28]), .B0(n3912), .B1(
DmP_mant_SHT1_SW[28]), .Y(n1341) );
AO22XLTS U4238 ( .A0(n3288), .A1(DmP_EXP_EWSW[29]), .B0(n3297), .B1(
DmP_mant_SHT1_SW[29]), .Y(n1339) );
AO22XLTS U4239 ( .A0(n3288), .A1(DmP_EXP_EWSW[30]), .B0(n3321), .B1(
DmP_mant_SHT1_SW[30]), .Y(n1337) );
NOR2BX1TS U4240 ( .AN(LZD_output_NRM2_EW[4]), .B(ADD_OVRFLW_NRM2), .Y(n3289)
);
XOR2X1TS U4241 ( .A(n1895), .B(n3289), .Y(DP_OP_15J180_122_2221_n18) );
NOR2BX1TS U4242 ( .AN(LZD_output_NRM2_EW[5]), .B(ADD_OVRFLW_NRM2), .Y(n3290)
);
XOR2X1TS U4243 ( .A(n1895), .B(n3290), .Y(DP_OP_15J180_122_2221_n17) );
NOR2BX1TS U4244 ( .AN(LZD_output_NRM2_EW[1]), .B(ADD_OVRFLW_NRM2), .Y(n3291)
);
XOR2X1TS U4245 ( .A(n1895), .B(n3291), .Y(DP_OP_15J180_122_2221_n21) );
NOR2BX1TS U4246 ( .AN(LZD_output_NRM2_EW[2]), .B(ADD_OVRFLW_NRM2), .Y(n3292)
);
XOR2X1TS U4247 ( .A(n1895), .B(n3292), .Y(DP_OP_15J180_122_2221_n20) );
NOR2BX1TS U4248 ( .AN(LZD_output_NRM2_EW[3]), .B(ADD_OVRFLW_NRM2), .Y(n3293)
);
XOR2X1TS U4249 ( .A(n1895), .B(n3293), .Y(DP_OP_15J180_122_2221_n19) );
OR2X1TS U4250 ( .A(ADD_OVRFLW_NRM2), .B(LZD_output_NRM2_EW[0]), .Y(n3294) );
XOR2X1TS U4251 ( .A(n1895), .B(n3294), .Y(DP_OP_15J180_122_2221_n22) );
AO22XLTS U4252 ( .A0(n3295), .A1(DMP_SHT1_EWSW[61]), .B0(n3299), .B1(
DMP_SHT2_EWSW[61]), .Y(n1407) );
MX2X1TS U4253 ( .A(DMP_exp_NRM2_EW[2]), .B(DMP_exp_NRM_EW[2]), .S0(n2042),
.Y(n1439) );
INVX2TS U4254 ( .A(n3302), .Y(n3312) );
CLKBUFX3TS U4255 ( .A(n3296), .Y(n3307) );
AO22XLTS U4256 ( .A0(n3312), .A1(DMP_EXP_EWSW[44]), .B0(n3307), .B1(
DMP_SHT1_EWSW[44]), .Y(n1477) );
INVX2TS U4257 ( .A(n3321), .Y(n3308) );
AO22XLTS U4258 ( .A0(n3308), .A1(DMP_EXP_EWSW[34]), .B0(n3296), .B1(
DMP_SHT1_EWSW[34]), .Y(n1507) );
AO22XLTS U4259 ( .A0(n3312), .A1(DMP_EXP_EWSW[45]), .B0(n3307), .B1(
DMP_SHT1_EWSW[45]), .Y(n1474) );
AO22XLTS U4260 ( .A0(n3316), .A1(DMP_SHT1_EWSW[43]), .B0(n3306), .B1(
DMP_SHT2_EWSW[43]), .Y(n1479) );
AO22XLTS U4261 ( .A0(n3310), .A1(DMP_EXP_EWSW[33]), .B0(n3297), .B1(
DMP_SHT1_EWSW[33]), .Y(n1510) );
AO22XLTS U4262 ( .A0(n3316), .A1(DMP_SHT1_EWSW[45]), .B0(n3306), .B1(
DMP_SHT2_EWSW[45]), .Y(n1473) );
AO22XLTS U4263 ( .A0(n3312), .A1(DMP_EXP_EWSW[46]), .B0(n3307), .B1(
DMP_SHT1_EWSW[46]), .Y(n1471) );
AO22XLTS U4264 ( .A0(n3310), .A1(DMP_EXP_EWSW[32]), .B0(n3298), .B1(
DMP_SHT1_EWSW[32]), .Y(n1513) );
AO22XLTS U4265 ( .A0(n3308), .A1(DMP_EXP_EWSW[35]), .B0(n3303), .B1(
DMP_SHT1_EWSW[35]), .Y(n1504) );
AO22XLTS U4266 ( .A0(n3308), .A1(DMP_EXP_EWSW[43]), .B0(n3307), .B1(
DMP_SHT1_EWSW[43]), .Y(n1480) );
AO22XLTS U4267 ( .A0(n3300), .A1(DMP_SHT1_EWSW[31]), .B0(n3315), .B1(
DMP_SHT2_EWSW[31]), .Y(n1515) );
AO22XLTS U4268 ( .A0(n3312), .A1(DMP_EXP_EWSW[47]), .B0(n3307), .B1(
DMP_SHT1_EWSW[47]), .Y(n1468) );
MX2X1TS U4269 ( .A(DMP_exp_NRM2_EW[3]), .B(DMP_exp_NRM_EW[3]), .S0(n2039),
.Y(n1434) );
AO22XLTS U4270 ( .A0(n3314), .A1(DMP_SHT1_EWSW[47]), .B0(n3306), .B1(
DMP_SHT2_EWSW[47]), .Y(n1467) );
AO22XLTS U4271 ( .A0(n3308), .A1(DMP_EXP_EWSW[42]), .B0(n3307), .B1(
DMP_SHT1_EWSW[42]), .Y(n1483) );
MX2X1TS U4272 ( .A(DMP_exp_NRM2_EW[1]), .B(DMP_exp_NRM_EW[1]), .S0(n2040),
.Y(n1444) );
AO22XLTS U4273 ( .A0(n3310), .A1(DMP_EXP_EWSW[31]), .B0(n3912), .B1(
DMP_SHT1_EWSW[31]), .Y(n1516) );
AO22XLTS U4274 ( .A0(n3312), .A1(DMP_EXP_EWSW[48]), .B0(n3307), .B1(
DMP_SHT1_EWSW[48]), .Y(n1465) );
AO22XLTS U4275 ( .A0(n3300), .A1(DMP_SHT1_EWSW[35]), .B0(n3315), .B1(
DMP_SHT2_EWSW[35]), .Y(n1503) );
AO22XLTS U4276 ( .A0(n3316), .A1(DMP_SHT1_EWSW[41]), .B0(n3306), .B1(
DMP_SHT2_EWSW[41]), .Y(n1485) );
AO22XLTS U4277 ( .A0(n3312), .A1(DMP_EXP_EWSW[49]), .B0(n3307), .B1(
DMP_SHT1_EWSW[49]), .Y(n1462) );
AO22XLTS U4278 ( .A0(n3310), .A1(DMP_EXP_EWSW[30]), .B0(n3912), .B1(
DMP_SHT1_EWSW[30]), .Y(n1519) );
AO22XLTS U4279 ( .A0(n3300), .A1(DMP_SHT1_EWSW[33]), .B0(n3315), .B1(
DMP_SHT2_EWSW[33]), .Y(n1509) );
AO22XLTS U4280 ( .A0(n3314), .A1(DMP_SHT1_EWSW[49]), .B0(n3299), .B1(
DMP_SHT2_EWSW[49]), .Y(n1461) );
AO22XLTS U4281 ( .A0(n3300), .A1(DMP_SHT1_EWSW[29]), .B0(n3315), .B1(
DMP_SHT2_EWSW[29]), .Y(n1521) );
AO22XLTS U4282 ( .A0(n3308), .A1(DMP_EXP_EWSW[36]), .B0(n3321), .B1(
DMP_SHT1_EWSW[36]), .Y(n1501) );
MX2X1TS U4283 ( .A(DMP_exp_NRM2_EW[4]), .B(DMP_exp_NRM_EW[4]), .S0(n2041),
.Y(n1429) );
AO22XLTS U4284 ( .A0(n3312), .A1(DMP_EXP_EWSW[50]), .B0(n3311), .B1(
DMP_SHT1_EWSW[50]), .Y(n1459) );
AO22XLTS U4285 ( .A0(n3308), .A1(DMP_EXP_EWSW[41]), .B0(n3307), .B1(
DMP_SHT1_EWSW[41]), .Y(n1486) );
AO22XLTS U4286 ( .A0(n3308), .A1(DMP_EXP_EWSW[38]), .B0(n3321), .B1(
DMP_SHT1_EWSW[38]), .Y(n1495) );
AO22XLTS U4287 ( .A0(n3310), .A1(DMP_EXP_EWSW[29]), .B0(n3309), .B1(
DMP_SHT1_EWSW[29]), .Y(n1522) );
AO22XLTS U4288 ( .A0(n3312), .A1(DMP_EXP_EWSW[52]), .B0(n3311), .B1(
DMP_SHT1_EWSW[52]), .Y(n1453) );
AO22XLTS U4289 ( .A0(n3308), .A1(DMP_EXP_EWSW[39]), .B0(n3303), .B1(
DMP_SHT1_EWSW[39]), .Y(n1492) );
AO22XLTS U4290 ( .A0(n3312), .A1(DMP_EXP_EWSW[51]), .B0(n3311), .B1(
DMP_SHT1_EWSW[51]), .Y(n1456) );
AO22XLTS U4291 ( .A0(n3305), .A1(DMP_SHT2_EWSW[52]), .B0(n3304), .B1(
DMP_SFG[52]), .Y(n1451) );
AO22XLTS U4292 ( .A0(n3310), .A1(DMP_EXP_EWSW[27]), .B0(n3309), .B1(
DMP_SHT1_EWSW[27]), .Y(n1528) );
AO22XLTS U4293 ( .A0(n3310), .A1(DMP_EXP_EWSW[28]), .B0(n3309), .B1(
DMP_SHT1_EWSW[28]), .Y(n1525) );
AO22XLTS U4294 ( .A0(n3316), .A1(DMP_SHT1_EWSW[39]), .B0(n3306), .B1(
DMP_SHT2_EWSW[39]), .Y(n1491) );
AO22XLTS U4295 ( .A0(n3308), .A1(DMP_EXP_EWSW[40]), .B0(n3307), .B1(
DMP_SHT1_EWSW[40]), .Y(n1489) );
AO22XLTS U4296 ( .A0(n3308), .A1(DMP_EXP_EWSW[37]), .B0(n3321), .B1(
DMP_SHT1_EWSW[37]), .Y(n1498) );
AO22XLTS U4297 ( .A0(n3310), .A1(DMP_EXP_EWSW[26]), .B0(n3309), .B1(
DMP_SHT1_EWSW[26]), .Y(n1531) );
AO22XLTS U4298 ( .A0(n3314), .A1(DMP_SHT1_EWSW[52]), .B0(n3313), .B1(
DMP_SHT2_EWSW[52]), .Y(n1452) );
AO22XLTS U4299 ( .A0(n3312), .A1(DMP_EXP_EWSW[53]), .B0(n3311), .B1(
DMP_SHT1_EWSW[53]), .Y(n1448) );
AO22XLTS U4300 ( .A0(n3314), .A1(DMP_SHT1_EWSW[53]), .B0(n3313), .B1(
DMP_SHT2_EWSW[53]), .Y(n1447) );
MX2X1TS U4301 ( .A(DMP_exp_NRM2_EW[5]), .B(DMP_exp_NRM_EW[5]), .S0(n2042),
.Y(n1424) );
MX2X1TS U4302 ( .A(DMP_exp_NRM2_EW[0]), .B(DMP_exp_NRM_EW[0]), .S0(n2039),
.Y(n1449) );
AO22XLTS U4303 ( .A0(n3316), .A1(DMP_SHT1_EWSW[37]), .B0(n3315), .B1(
DMP_SHT2_EWSW[37]), .Y(n1497) );
OAI21XLTS U4304 ( .A0(n2039), .A1(n1895), .B0(n3317), .Y(n1276) );
OA22X1TS U4305 ( .A0(exp_rslt_NRM2_EW1[0]), .A1(n1973), .B0(
Shift_reg_FLAGS_7[0]), .B1(final_result_ieee[52]), .Y(n1686) );
OA22X1TS U4306 ( .A0(exp_rslt_NRM2_EW1[1]), .A1(n3318), .B0(
Shift_reg_FLAGS_7[0]), .B1(final_result_ieee[53]), .Y(n1685) );
OA22X1TS U4307 ( .A0(exp_rslt_NRM2_EW1[2]), .A1(n1973), .B0(
Shift_reg_FLAGS_7[0]), .B1(final_result_ieee[54]), .Y(n1684) );
OA22X1TS U4308 ( .A0(exp_rslt_NRM2_EW1[3]), .A1(n3318), .B0(
Shift_reg_FLAGS_7[0]), .B1(final_result_ieee[55]), .Y(n1683) );
OA22X1TS U4309 ( .A0(exp_rslt_NRM2_EW1[4]), .A1(n1973), .B0(
Shift_reg_FLAGS_7[0]), .B1(final_result_ieee[56]), .Y(n1682) );
OA22X1TS U4310 ( .A0(exp_rslt_NRM2_EW1[5]), .A1(n3318), .B0(n2037), .B1(
final_result_ieee[57]), .Y(n1681) );
OA22X1TS U4311 ( .A0(exp_rslt_NRM2_EW1[6]), .A1(n1973), .B0(n2037), .B1(
final_result_ieee[58]), .Y(n1680) );
OA22X1TS U4312 ( .A0(exp_rslt_NRM2_EW1[7]), .A1(n3318), .B0(n2037), .B1(
final_result_ieee[59]), .Y(n1679) );
OA22X1TS U4313 ( .A0(exp_rslt_NRM2_EW1[8]), .A1(n1973), .B0(n2037), .B1(
final_result_ieee[60]), .Y(n1678) );
OA22X1TS U4314 ( .A0(exp_rslt_NRM2_EW1[9]), .A1(n1973), .B0(n2037), .B1(
final_result_ieee[61]), .Y(n1677) );
AOI22X1TS U4315 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
inst_FSM_INPUT_ENABLE_state_reg[0]), .B0(n3319), .B1(n3684), .Y(
inst_FSM_INPUT_ENABLE_state_next_1_) );
AOI22X1TS U4316 ( .A0(n3325), .A1(n3320), .B0(n3321), .B1(n3323), .Y(n1889)
);
AOI22X1TS U4317 ( .A0(n3325), .A1(n3302), .B0(n3854), .B1(n3323), .Y(n1888)
);
INVX2TS U4318 ( .A(Shift_reg_FLAGS_7[2]), .Y(n3504) );
AOI22X1TS U4319 ( .A0(n3325), .A1(n3649), .B0(n3322), .B1(n3323), .Y(n1885)
);
AOI22X1TS U4320 ( .A0(n3325), .A1(n3749), .B0(n3324), .B1(n3323), .Y(n1884)
);
NOR2XLTS U4321 ( .A(n3326), .B(SIGN_FLAG_SHT1SHT2), .Y(n3328) );
OAI2BB2XLTS U4322 ( .B0(n3328), .B1(n3327), .A0N(final_result_ieee[63]),
.A1N(n3745), .Y(n1270) );
CLKBUFX3TS U4323 ( .A(n3590), .Y(n3379) );
AOI22X1TS U4324 ( .A0(n3399), .A1(n3700), .B0(n3867), .B1(n3379), .Y(n1269)
);
CLKBUFX3TS U4325 ( .A(n3584), .Y(n3657) );
NOR2XLTS U4326 ( .A(n3657), .B(n3700), .Y(n3329) );
OAI32X1TS U4327 ( .A0(n3916), .A1(n3657), .A2(n3700), .B0(
DmP_mant_SFG_SWR[1]), .B1(n3329), .Y(n3330) );
AOI22X1TS U4328 ( .A0(n3343), .A1(n3330), .B0(n3669), .B1(n3379), .Y(n1268)
);
AOI21X1TS U4329 ( .A0(DMP_SFG[1]), .A1(n3765), .B0(n3331), .Y(n3335) );
AOI22X1TS U4330 ( .A0(n3675), .A1(n3333), .B0(n3332), .B1(n3476), .Y(n3334)
);
XNOR2X1TS U4331 ( .A(n3335), .B(n3334), .Y(n3336) );
AOI22X1TS U4332 ( .A0(n3343), .A1(n3336), .B0(n3829), .B1(n3379), .Y(n1266)
);
AOI22X1TS U4333 ( .A0(n3451), .A1(n3338), .B0(n3337), .B1(n3476), .Y(n3341)
);
XNOR2X1TS U4334 ( .A(n3341), .B(n3340), .Y(n3342) );
AOI22X1TS U4335 ( .A0(n3343), .A1(n3342), .B0(n3856), .B1(n3379), .Y(n1265)
);
AOI21X1TS U4336 ( .A0(DMP_SFG[3]), .A1(n3842), .B0(n3344), .Y(n3348) );
AOI22X1TS U4337 ( .A0(n3675), .A1(n3346), .B0(n3345), .B1(n3476), .Y(n3347)
);
XNOR2X1TS U4338 ( .A(n3348), .B(n3347), .Y(n3349) );
AOI22X1TS U4339 ( .A0(n3399), .A1(n3349), .B0(n3711), .B1(n3379), .Y(n1264)
);
AOI22X1TS U4340 ( .A0(n3675), .A1(n3351), .B0(n3350), .B1(n3476), .Y(n3354)
);
OAI21XLTS U4341 ( .A0(DmP_mant_SFG_SWR[6]), .A1(n3718), .B0(n3352), .Y(n3353) );
XNOR2X1TS U4342 ( .A(n3354), .B(n3353), .Y(n3355) );
AOI22X1TS U4343 ( .A0(n3399), .A1(n3355), .B0(n3828), .B1(n3379), .Y(n1263)
);
AOI21X1TS U4344 ( .A0(DMP_SFG[5]), .A1(n3766), .B0(n3356), .Y(n3360) );
AOI22X1TS U4345 ( .A0(n3675), .A1(n3358), .B0(n3357), .B1(n3903), .Y(n3359)
);
XNOR2X1TS U4346 ( .A(n3360), .B(n3359), .Y(n3361) );
AOI22X1TS U4347 ( .A0(n3399), .A1(n3361), .B0(n3830), .B1(n3379), .Y(n1262)
);
NOR2X1TS U4348 ( .A(DMP_SFG[7]), .B(n3767), .Y(n3369) );
AOI21X1TS U4349 ( .A0(DMP_SFG[7]), .A1(n3767), .B0(n3369), .Y(n3366) );
AOI22X1TS U4350 ( .A0(DMP_SFG[6]), .A1(n3691), .B0(n3363), .B1(n3362), .Y(
n3368) );
AOI22X1TS U4351 ( .A0(n3675), .A1(n3368), .B0(n3364), .B1(n3903), .Y(n3365)
);
XNOR2X1TS U4352 ( .A(n3366), .B(n3365), .Y(n3367) );
AOI22X1TS U4353 ( .A0(n3399), .A1(n3367), .B0(n3712), .B1(n3379), .Y(n1260)
);
OAI2BB2X1TS U4354 ( .B0(n3369), .B1(n3368), .A0N(n3767), .A1N(DMP_SFG[7]),
.Y(n3374) );
AOI22X1TS U4355 ( .A0(n3675), .A1(n3374), .B0(n3370), .B1(n3584), .Y(n3372)
);
NAND2X1TS U4356 ( .A(DmP_mant_SFG_SWR[10]), .B(n3782), .Y(n3375) );
OAI21XLTS U4357 ( .A0(DmP_mant_SFG_SWR[10]), .A1(n3782), .B0(n3375), .Y(
n3371) );
XNOR2X1TS U4358 ( .A(n3372), .B(n3371), .Y(n3373) );
AOI22X1TS U4359 ( .A0(n3399), .A1(n3373), .B0(n3866), .B1(n3379), .Y(n1259)
);
NOR2X1TS U4360 ( .A(DMP_SFG[9]), .B(n3768), .Y(n3382) );
AOI21X1TS U4361 ( .A0(DMP_SFG[9]), .A1(n3768), .B0(n3382), .Y(n3378) );
AOI22X1TS U4362 ( .A0(DMP_SFG[8]), .A1(n3692), .B0(n3375), .B1(n3374), .Y(
n3381) );
AOI22X1TS U4363 ( .A0(n3675), .A1(n3381), .B0(n3376), .B1(n3584), .Y(n3377)
);
XNOR2X1TS U4364 ( .A(n3378), .B(n3377), .Y(n3380) );
AOI22X1TS U4365 ( .A0(n3399), .A1(n3380), .B0(n3864), .B1(n3379), .Y(n1258)
);
OAI2BB2X1TS U4366 ( .B0(n3382), .B1(n3381), .A0N(n3768), .A1N(DMP_SFG[9]),
.Y(n3387) );
AOI22X1TS U4367 ( .A0(n3675), .A1(n3387), .B0(n3383), .B1(n3903), .Y(n3385)
);
NAND2X1TS U4368 ( .A(DmP_mant_SFG_SWR[12]), .B(n3719), .Y(n3388) );
OAI21XLTS U4369 ( .A0(DmP_mant_SFG_SWR[12]), .A1(n3719), .B0(n3388), .Y(
n3384) );
XNOR2X1TS U4370 ( .A(n3385), .B(n3384), .Y(n3386) );
CLKBUFX3TS U4371 ( .A(n3590), .Y(n3659) );
AOI22X1TS U4372 ( .A0(n3399), .A1(n3386), .B0(n3703), .B1(n3659), .Y(n1257)
);
NOR2X1TS U4373 ( .A(DMP_SFG[11]), .B(n3843), .Y(n3394) );
AOI21X1TS U4374 ( .A0(DMP_SFG[11]), .A1(n3843), .B0(n3394), .Y(n3391) );
AOI22X1TS U4375 ( .A0(DMP_SFG[10]), .A1(n3810), .B0(n3388), .B1(n3387), .Y(
n3393) );
AOI22X1TS U4376 ( .A0(n3653), .A1(n3393), .B0(n3389), .B1(n3903), .Y(n3390)
);
XNOR2X1TS U4377 ( .A(n3391), .B(n3390), .Y(n3392) );
AOI22X1TS U4378 ( .A0(n3399), .A1(n3392), .B0(n3821), .B1(n3659), .Y(n1256)
);
INVX2TS U4379 ( .A(n3903), .Y(n3451) );
OAI2BB2X1TS U4380 ( .B0(n3394), .B1(n3393), .A0N(n3843), .A1N(DMP_SFG[11]),
.Y(n3400) );
AOI22X1TS U4381 ( .A0(n3451), .A1(n3400), .B0(n3395), .B1(n3903), .Y(n3397)
);
NAND2X1TS U4382 ( .A(DmP_mant_SFG_SWR[14]), .B(n3720), .Y(n3401) );
OAI21XLTS U4383 ( .A0(DmP_mant_SFG_SWR[14]), .A1(n3720), .B0(n3401), .Y(
n3396) );
XNOR2X1TS U4384 ( .A(n3397), .B(n3396), .Y(n3398) );
AOI22X1TS U4385 ( .A0(n3399), .A1(n3398), .B0(n3827), .B1(n3659), .Y(n1255)
);
NOR2X1TS U4386 ( .A(DMP_SFG[13]), .B(n3844), .Y(n3407) );
AOI21X1TS U4387 ( .A0(DMP_SFG[13]), .A1(n3844), .B0(n3407), .Y(n3404) );
AOI22X1TS U4388 ( .A0(DMP_SFG[12]), .A1(n3811), .B0(n3401), .B1(n3400), .Y(
n3406) );
AOI22X1TS U4389 ( .A0(n3653), .A1(n3406), .B0(n3402), .B1(n3584), .Y(n3403)
);
XNOR2X1TS U4390 ( .A(n3404), .B(n3403), .Y(n3405) );
AOI22X1TS U4391 ( .A0(n3661), .A1(n3405), .B0(n3822), .B1(n3659), .Y(n1254)
);
OAI2BB2X1TS U4392 ( .B0(n3407), .B1(n3406), .A0N(n3844), .A1N(DMP_SFG[13]),
.Y(n3412) );
AOI22X1TS U4393 ( .A0(n3451), .A1(n3412), .B0(n3408), .B1(n3476), .Y(n3410)
);
NAND2X1TS U4394 ( .A(DmP_mant_SFG_SWR[16]), .B(n3721), .Y(n3413) );
OAI21XLTS U4395 ( .A0(DmP_mant_SFG_SWR[16]), .A1(n3721), .B0(n3413), .Y(
n3409) );
XNOR2X1TS U4396 ( .A(n3410), .B(n3409), .Y(n3411) );
AOI22X1TS U4397 ( .A0(n3661), .A1(n3411), .B0(n3682), .B1(n3659), .Y(n1253)
);
NOR2X1TS U4398 ( .A(DMP_SFG[15]), .B(n3845), .Y(n3419) );
AOI21X1TS U4399 ( .A0(DMP_SFG[15]), .A1(n3845), .B0(n3419), .Y(n3416) );
AOI22X1TS U4400 ( .A0(DMP_SFG[14]), .A1(n3812), .B0(n3413), .B1(n3412), .Y(
n3418) );
CLKBUFX3TS U4401 ( .A(n3903), .Y(n3469) );
AOI22X1TS U4402 ( .A0(n3653), .A1(n3418), .B0(n3414), .B1(n3469), .Y(n3415)
);
XNOR2X1TS U4403 ( .A(n3416), .B(n3415), .Y(n3417) );
AOI22X1TS U4404 ( .A0(n3661), .A1(n3417), .B0(n3868), .B1(n3659), .Y(n1252)
);
OAI2BB2X1TS U4405 ( .B0(n3419), .B1(n3418), .A0N(n3845), .A1N(DMP_SFG[15]),
.Y(n3424) );
AOI22X1TS U4406 ( .A0(n3451), .A1(n3424), .B0(n3420), .B1(n3469), .Y(n3422)
);
NAND2X1TS U4407 ( .A(DmP_mant_SFG_SWR[18]), .B(n3722), .Y(n3425) );
OAI21XLTS U4408 ( .A0(DmP_mant_SFG_SWR[18]), .A1(n3722), .B0(n3425), .Y(
n3421) );
XNOR2X1TS U4409 ( .A(n3422), .B(n3421), .Y(n3423) );
AOI22X1TS U4410 ( .A0(n3661), .A1(n3423), .B0(n3869), .B1(n3659), .Y(n1251)
);
NOR2X1TS U4411 ( .A(DMP_SFG[17]), .B(n3769), .Y(n3431) );
AOI21X1TS U4412 ( .A0(DMP_SFG[17]), .A1(n3769), .B0(n3431), .Y(n3428) );
AOI22X1TS U4413 ( .A0(DMP_SFG[16]), .A1(n3813), .B0(n3425), .B1(n3424), .Y(
n3430) );
AOI22X1TS U4414 ( .A0(n3653), .A1(n3430), .B0(n3426), .B1(n3469), .Y(n3427)
);
XNOR2X1TS U4415 ( .A(n3428), .B(n3427), .Y(n3429) );
AOI22X1TS U4416 ( .A0(n3661), .A1(n3429), .B0(n3683), .B1(n3659), .Y(n1250)
);
OAI2BB2X1TS U4417 ( .B0(n3431), .B1(n3430), .A0N(n3769), .A1N(DMP_SFG[17]),
.Y(n3436) );
AOI22X1TS U4418 ( .A0(n3451), .A1(n3436), .B0(n3432), .B1(n3469), .Y(n3434)
);
NAND2X1TS U4419 ( .A(DmP_mant_SFG_SWR[20]), .B(n3723), .Y(n3437) );
OAI21XLTS U4420 ( .A0(DmP_mant_SFG_SWR[20]), .A1(n3723), .B0(n3437), .Y(
n3433) );
XNOR2X1TS U4421 ( .A(n3434), .B(n3433), .Y(n3435) );
AOI22X1TS U4422 ( .A0(n3661), .A1(n3435), .B0(n3670), .B1(n3659), .Y(n1249)
);
NOR2X1TS U4423 ( .A(DMP_SFG[19]), .B(n3846), .Y(n3443) );
AOI21X1TS U4424 ( .A0(DMP_SFG[19]), .A1(n3846), .B0(n3443), .Y(n3440) );
AOI22X1TS U4425 ( .A0(DMP_SFG[18]), .A1(n3814), .B0(n3437), .B1(n3436), .Y(
n3442) );
AOI22X1TS U4426 ( .A0(n3653), .A1(n3442), .B0(n3438), .B1(n3469), .Y(n3439)
);
XNOR2X1TS U4427 ( .A(n3440), .B(n3439), .Y(n3441) );
AOI22X1TS U4428 ( .A0(n3661), .A1(n3441), .B0(n3754), .B1(n3504), .Y(n1248)
);
OAI2BB2X1TS U4429 ( .B0(n3443), .B1(n3442), .A0N(n3846), .A1N(DMP_SFG[19]),
.Y(n3448) );
AOI22X1TS U4430 ( .A0(n3451), .A1(n3448), .B0(n3444), .B1(n3469), .Y(n3446)
);
NAND2X1TS U4431 ( .A(DmP_mant_SFG_SWR[22]), .B(n3724), .Y(n3449) );
OAI21XLTS U4432 ( .A0(DmP_mant_SFG_SWR[22]), .A1(n3724), .B0(n3449), .Y(
n3445) );
XNOR2X1TS U4433 ( .A(n3446), .B(n3445), .Y(n3447) );
AOI22X1TS U4434 ( .A0(n3661), .A1(n3447), .B0(n3831), .B1(n3504), .Y(n1247)
);
NOR2X1TS U4435 ( .A(DMP_SFG[21]), .B(n3770), .Y(n3456) );
AOI21X1TS U4436 ( .A0(DMP_SFG[21]), .A1(n3770), .B0(n3456), .Y(n3453) );
AOI22X1TS U4437 ( .A0(DMP_SFG[20]), .A1(n3815), .B0(n3449), .B1(n3448), .Y(
n3455) );
AOI22X1TS U4438 ( .A0(n3653), .A1(n3455), .B0(n3450), .B1(n3469), .Y(n3452)
);
XNOR2X1TS U4439 ( .A(n3453), .B(n3452), .Y(n3454) );
AOI22X1TS U4440 ( .A0(n3661), .A1(n3454), .B0(n3707), .B1(n3504), .Y(n1246)
);
OAI2BB2X1TS U4441 ( .B0(n3456), .B1(n3455), .A0N(n3770), .A1N(DMP_SFG[21]),
.Y(n3461) );
AOI22X1TS U4442 ( .A0(n3572), .A1(n3461), .B0(n3457), .B1(n3469), .Y(n3459)
);
NAND2X1TS U4443 ( .A(DmP_mant_SFG_SWR[24]), .B(n3783), .Y(n3462) );
XNOR2X1TS U4444 ( .A(n3459), .B(n3458), .Y(n3460) );
AOI22X1TS U4445 ( .A0(n3518), .A1(n3460), .B0(n3826), .B1(n3504), .Y(n1245)
);
NOR2X1TS U4446 ( .A(DMP_SFG[23]), .B(n3771), .Y(n3468) );
AOI21X1TS U4447 ( .A0(DMP_SFG[23]), .A1(n3771), .B0(n3468), .Y(n3465) );
AOI22X1TS U4448 ( .A0(DMP_SFG[22]), .A1(n3693), .B0(n3462), .B1(n3461), .Y(
n3467) );
AOI22X1TS U4449 ( .A0(n3572), .A1(n3467), .B0(n3463), .B1(n3469), .Y(n3464)
);
XNOR2X1TS U4450 ( .A(n3465), .B(n3464), .Y(n3466) );
AOI22X1TS U4451 ( .A0(n3518), .A1(n3466), .B0(n3756), .B1(n3913), .Y(n1244)
);
OAI2BB2X1TS U4452 ( .B0(n3468), .B1(n3467), .A0N(n3771), .A1N(DMP_SFG[23]),
.Y(n3474) );
AOI22X1TS U4453 ( .A0(n3572), .A1(n3474), .B0(n3470), .B1(n3469), .Y(n3472)
);
NAND2X1TS U4454 ( .A(DmP_mant_SFG_SWR[26]), .B(n3784), .Y(n3475) );
XNOR2X1TS U4455 ( .A(n3472), .B(n3471), .Y(n3473) );
AOI22X1TS U4456 ( .A0(n3518), .A1(n3473), .B0(n3865), .B1(n3504), .Y(n1243)
);
NOR2X1TS U4457 ( .A(DMP_SFG[25]), .B(n3847), .Y(n3482) );
AOI21X1TS U4458 ( .A0(DMP_SFG[25]), .A1(n3847), .B0(n3482), .Y(n3479) );
AOI22X1TS U4459 ( .A0(DMP_SFG[24]), .A1(n3694), .B0(n3475), .B1(n3474), .Y(
n3481) );
CLKBUFX3TS U4460 ( .A(n3476), .Y(n3557) );
AOI22X1TS U4461 ( .A0(n3572), .A1(n3481), .B0(n3477), .B1(n3557), .Y(n3478)
);
XNOR2X1TS U4462 ( .A(n3479), .B(n3478), .Y(n3480) );
AOI22X1TS U4463 ( .A0(n3518), .A1(n3480), .B0(n3914), .B1(n3913), .Y(n1242)
);
OAI2BB2X1TS U4464 ( .B0(n3482), .B1(n3481), .A0N(n3847), .A1N(DMP_SFG[25]),
.Y(n3487) );
AOI22X1TS U4465 ( .A0(n3572), .A1(n3487), .B0(n3483), .B1(n3557), .Y(n3485)
);
NAND2X1TS U4466 ( .A(DmP_mant_SFG_SWR[28]), .B(n3785), .Y(n3488) );
OAI21XLTS U4467 ( .A0(DmP_mant_SFG_SWR[28]), .A1(n3785), .B0(n3488), .Y(
n3484) );
XNOR2X1TS U4468 ( .A(n3485), .B(n3484), .Y(n3486) );
AOI22X1TS U4469 ( .A0(n3518), .A1(n3486), .B0(n3762), .B1(n3504), .Y(n1241)
);
NOR2X1TS U4470 ( .A(DMP_SFG[27]), .B(n3772), .Y(n3494) );
AOI21X1TS U4471 ( .A0(DMP_SFG[27]), .A1(n3772), .B0(n3494), .Y(n3491) );
AOI22X1TS U4472 ( .A0(DMP_SFG[26]), .A1(n3695), .B0(n3488), .B1(n3487), .Y(
n3493) );
AOI22X1TS U4473 ( .A0(n3572), .A1(n3493), .B0(n3489), .B1(n3557), .Y(n3490)
);
XNOR2X1TS U4474 ( .A(n3491), .B(n3490), .Y(n3492) );
AOI22X1TS U4475 ( .A0(n3518), .A1(n3492), .B0(n3688), .B1(n3913), .Y(n1240)
);
OAI2BB2X1TS U4476 ( .B0(n3494), .B1(n3493), .A0N(n3772), .A1N(DMP_SFG[27]),
.Y(n3499) );
AOI22X1TS U4477 ( .A0(n3572), .A1(n3499), .B0(n3495), .B1(n3557), .Y(n3497)
);
NAND2X1TS U4478 ( .A(DmP_mant_SFG_SWR[30]), .B(n3786), .Y(n3500) );
XNOR2X1TS U4479 ( .A(n3497), .B(n3496), .Y(n3498) );
AOI22X1TS U4480 ( .A0(n3518), .A1(n3498), .B0(n3750), .B1(n3504), .Y(n1239)
);
NOR2X1TS U4481 ( .A(DMP_SFG[29]), .B(n3773), .Y(n3507) );
AOI21X1TS U4482 ( .A0(DMP_SFG[29]), .A1(n3773), .B0(n3507), .Y(n3503) );
AOI22X1TS U4483 ( .A0(DMP_SFG[28]), .A1(n3696), .B0(n3500), .B1(n3499), .Y(
n3506) );
AOI22X1TS U4484 ( .A0(n3572), .A1(n3506), .B0(n3501), .B1(n3557), .Y(n3502)
);
XNOR2X1TS U4485 ( .A(n3503), .B(n3502), .Y(n3505) );
CLKBUFX3TS U4486 ( .A(n3504), .Y(n3561) );
AOI22X1TS U4487 ( .A0(n3518), .A1(n3505), .B0(n3820), .B1(n3561), .Y(n1238)
);
OAI2BB2X1TS U4488 ( .B0(n3507), .B1(n3506), .A0N(n3773), .A1N(DMP_SFG[29]),
.Y(n3512) );
AOI22X1TS U4489 ( .A0(n3572), .A1(n3512), .B0(n3508), .B1(n3557), .Y(n3510)
);
NAND2X1TS U4490 ( .A(DmP_mant_SFG_SWR[32]), .B(n3725), .Y(n3513) );
OAI21XLTS U4491 ( .A0(DmP_mant_SFG_SWR[32]), .A1(n3725), .B0(n3513), .Y(
n3509) );
XNOR2X1TS U4492 ( .A(n3510), .B(n3509), .Y(n3511) );
AOI22X1TS U4493 ( .A0(n3518), .A1(n3511), .B0(n3819), .B1(n3561), .Y(n1237)
);
NOR2X1TS U4494 ( .A(DMP_SFG[31]), .B(n3738), .Y(n3520) );
AOI21X1TS U4495 ( .A0(DMP_SFG[31]), .A1(n3738), .B0(n3520), .Y(n3516) );
AOI22X1TS U4496 ( .A0(DMP_SFG[30]), .A1(n3816), .B0(n3513), .B1(n3512), .Y(
n3519) );
AOI22X1TS U4497 ( .A0(n3579), .A1(n3519), .B0(n3514), .B1(n3557), .Y(n3515)
);
XNOR2X1TS U4498 ( .A(n3516), .B(n3515), .Y(n3517) );
AOI22X1TS U4499 ( .A0(n3518), .A1(n3517), .B0(n3751), .B1(n3561), .Y(n1236)
);
OAI2BB2X1TS U4500 ( .B0(n3520), .B1(n3519), .A0N(n3738), .A1N(DMP_SFG[31]),
.Y(n3525) );
AOI22X1TS U4501 ( .A0(n3579), .A1(n3525), .B0(n3521), .B1(n3557), .Y(n3523)
);
NAND2X1TS U4502 ( .A(DmP_mant_SFG_SWR[34]), .B(n3787), .Y(n3526) );
OAI21XLTS U4503 ( .A0(DmP_mant_SFG_SWR[34]), .A1(n3787), .B0(n3526), .Y(
n3522) );
XNOR2X1TS U4504 ( .A(n3523), .B(n3522), .Y(n3524) );
AOI22X1TS U4505 ( .A0(n3583), .A1(n3524), .B0(n3702), .B1(n3561), .Y(n1235)
);
NOR2X1TS U4506 ( .A(DMP_SFG[33]), .B(n3716), .Y(n3532) );
AOI21X1TS U4507 ( .A0(DMP_SFG[33]), .A1(n3716), .B0(n3532), .Y(n3529) );
AOI22X1TS U4508 ( .A0(DMP_SFG[32]), .A1(n3729), .B0(n3526), .B1(n3525), .Y(
n3531) );
AOI22X1TS U4509 ( .A0(n3579), .A1(n3531), .B0(n3527), .B1(n3557), .Y(n3528)
);
XNOR2X1TS U4510 ( .A(n3529), .B(n3528), .Y(n3530) );
AOI22X1TS U4511 ( .A0(n3583), .A1(n3530), .B0(n3699), .B1(n3561), .Y(n1234)
);
OAI2BB2X1TS U4512 ( .B0(n3532), .B1(n3531), .A0N(n3716), .A1N(DMP_SFG[33]),
.Y(n3537) );
CLKBUFX3TS U4513 ( .A(n3584), .Y(n3600) );
AOI22X1TS U4514 ( .A0(n3579), .A1(n3537), .B0(n3533), .B1(n3600), .Y(n3535)
);
NAND2X1TS U4515 ( .A(DmP_mant_SFG_SWR[36]), .B(n3788), .Y(n3538) );
OAI21XLTS U4516 ( .A0(DmP_mant_SFG_SWR[36]), .A1(n3788), .B0(n3538), .Y(
n3534) );
XNOR2X1TS U4517 ( .A(n3535), .B(n3534), .Y(n3536) );
AOI22X1TS U4518 ( .A0(n3583), .A1(n3536), .B0(n3805), .B1(n3561), .Y(n1233)
);
NOR2X1TS U4519 ( .A(DMP_SFG[35]), .B(n3739), .Y(n3544) );
AOI21X1TS U4520 ( .A0(DMP_SFG[35]), .A1(n3739), .B0(n3544), .Y(n3541) );
AOI22X1TS U4521 ( .A0(DMP_SFG[34]), .A1(n3730), .B0(n3538), .B1(n3537), .Y(
n3543) );
AOI22X1TS U4522 ( .A0(n3579), .A1(n3543), .B0(n3539), .B1(n3600), .Y(n3540)
);
XNOR2X1TS U4523 ( .A(n3541), .B(n3540), .Y(n3542) );
AOI22X1TS U4524 ( .A0(n3583), .A1(n3542), .B0(n3755), .B1(n3561), .Y(n1232)
);
OAI2BB2X1TS U4525 ( .B0(n3544), .B1(n3543), .A0N(n3739), .A1N(DMP_SFG[35]),
.Y(n3549) );
AOI22X1TS U4526 ( .A0(n3579), .A1(n3549), .B0(n3545), .B1(n3600), .Y(n3547)
);
NAND2X1TS U4527 ( .A(DmP_mant_SFG_SWR[38]), .B(n3789), .Y(n3550) );
OAI21XLTS U4528 ( .A0(DmP_mant_SFG_SWR[38]), .A1(n3789), .B0(n3550), .Y(
n3546) );
XNOR2X1TS U4529 ( .A(n3547), .B(n3546), .Y(n3548) );
AOI22X1TS U4530 ( .A0(n3583), .A1(n3548), .B0(n3685), .B1(n3561), .Y(n1231)
);
NOR2X1TS U4531 ( .A(DMP_SFG[37]), .B(n3740), .Y(n3556) );
AOI21X1TS U4532 ( .A0(DMP_SFG[37]), .A1(n3740), .B0(n3556), .Y(n3553) );
AOI22X1TS U4533 ( .A0(DMP_SFG[36]), .A1(n3731), .B0(n3550), .B1(n3549), .Y(
n3555) );
AOI22X1TS U4534 ( .A0(n3579), .A1(n3555), .B0(n3551), .B1(n3600), .Y(n3552)
);
XNOR2X1TS U4535 ( .A(n3553), .B(n3552), .Y(n3554) );
AOI22X1TS U4536 ( .A0(n3583), .A1(n3554), .B0(n3825), .B1(n3561), .Y(n1230)
);
OAI2BB2X1TS U4537 ( .B0(n3556), .B1(n3555), .A0N(n3740), .A1N(DMP_SFG[37]),
.Y(n3563) );
AOI22X1TS U4538 ( .A0(n3579), .A1(n3563), .B0(n3558), .B1(n3557), .Y(n3560)
);
NAND2X1TS U4539 ( .A(DmP_mant_SFG_SWR[40]), .B(n3790), .Y(n3564) );
OAI21XLTS U4540 ( .A0(DmP_mant_SFG_SWR[40]), .A1(n3790), .B0(n3564), .Y(
n3559) );
XNOR2X1TS U4541 ( .A(n3560), .B(n3559), .Y(n3562) );
AOI22X1TS U4542 ( .A0(n3583), .A1(n3562), .B0(n3690), .B1(n3561), .Y(n1229)
);
NOR2X1TS U4543 ( .A(DMP_SFG[39]), .B(n3741), .Y(n3570) );
AOI21X1TS U4544 ( .A0(DMP_SFG[39]), .A1(n3741), .B0(n3570), .Y(n3567) );
AOI22X1TS U4545 ( .A0(DMP_SFG[38]), .A1(n3732), .B0(n3564), .B1(n3563), .Y(
n3569) );
AOI22X1TS U4546 ( .A0(n3579), .A1(n3569), .B0(n3565), .B1(n3600), .Y(n3566)
);
XNOR2X1TS U4547 ( .A(n3567), .B(n3566), .Y(n3568) );
AOI22X1TS U4548 ( .A0(n3583), .A1(n3568), .B0(n3698), .B1(n3590), .Y(n1228)
);
OAI2BB2X1TS U4549 ( .B0(n3570), .B1(n3569), .A0N(n3741), .A1N(DMP_SFG[39]),
.Y(n3576) );
AOI22X1TS U4550 ( .A0(n3572), .A1(n3576), .B0(n3571), .B1(n3600), .Y(n3574)
);
NAND2X1TS U4551 ( .A(DmP_mant_SFG_SWR[42]), .B(n3791), .Y(n3577) );
XNOR2X1TS U4552 ( .A(n3574), .B(n3573), .Y(n3575) );
AOI22X1TS U4553 ( .A0(n3583), .A1(n3575), .B0(n3803), .B1(n3590), .Y(n1227)
);
NOR2X1TS U4554 ( .A(DMP_SFG[41]), .B(n3774), .Y(n3586) );
AOI21X1TS U4555 ( .A0(DMP_SFG[41]), .A1(n3774), .B0(n3586), .Y(n3581) );
AOI22X1TS U4556 ( .A0(DMP_SFG[40]), .A1(n3733), .B0(n3577), .B1(n3576), .Y(
n3585) );
AOI22X1TS U4557 ( .A0(n3579), .A1(n3585), .B0(n3578), .B1(n3600), .Y(n3580)
);
XNOR2X1TS U4558 ( .A(n3581), .B(n3580), .Y(n3582) );
AOI22X1TS U4559 ( .A0(n3583), .A1(n3582), .B0(n3747), .B1(n3913), .Y(n1226)
);
OAI2BB2X1TS U4560 ( .B0(n3586), .B1(n3585), .A0N(n3774), .A1N(DMP_SFG[41]),
.Y(n3592) );
AOI22X1TS U4561 ( .A0(n3646), .A1(n3592), .B0(n3587), .B1(n3600), .Y(n3589)
);
NAND2X1TS U4562 ( .A(DmP_mant_SFG_SWR[44]), .B(n3792), .Y(n3593) );
OAI21XLTS U4563 ( .A0(DmP_mant_SFG_SWR[44]), .A1(n3792), .B0(n3593), .Y(
n3588) );
XNOR2X1TS U4564 ( .A(n3589), .B(n3588), .Y(n3591) );
AOI22X1TS U4565 ( .A0(n3651), .A1(n3591), .B0(n3705), .B1(n3590), .Y(n1225)
);
NOR2X1TS U4566 ( .A(DMP_SFG[43]), .B(n3775), .Y(n3599) );
AOI21X1TS U4567 ( .A0(DMP_SFG[43]), .A1(n3775), .B0(n3599), .Y(n3596) );
AOI22X1TS U4568 ( .A0(DMP_SFG[42]), .A1(n3697), .B0(n3593), .B1(n3592), .Y(
n3598) );
AOI22X1TS U4569 ( .A0(n3646), .A1(n3598), .B0(n3594), .B1(n3600), .Y(n3595)
);
XNOR2X1TS U4570 ( .A(n3596), .B(n3595), .Y(n3597) );
AOI22X1TS U4571 ( .A0(n3651), .A1(n3597), .B0(n3704), .B1(n3913), .Y(n1224)
);
OAI2BB2X1TS U4572 ( .B0(n3599), .B1(n3598), .A0N(n3775), .A1N(DMP_SFG[43]),
.Y(n3605) );
AOI22X1TS U4573 ( .A0(n3646), .A1(n3605), .B0(n3601), .B1(n3600), .Y(n3603)
);
NAND2X1TS U4574 ( .A(DmP_mant_SFG_SWR[46]), .B(n3793), .Y(n3606) );
XNOR2X1TS U4575 ( .A(n3603), .B(n3602), .Y(n3604) );
AOI22X1TS U4576 ( .A0(n3651), .A1(n3604), .B0(n3759), .B1(n3913), .Y(n1223)
);
NOR2X1TS U4577 ( .A(DMP_SFG[45]), .B(n3776), .Y(n3612) );
AOI21X1TS U4578 ( .A0(DMP_SFG[45]), .A1(n3776), .B0(n3612), .Y(n3609) );
AOI22X1TS U4579 ( .A0(DMP_SFG[44]), .A1(n3673), .B0(n3606), .B1(n3605), .Y(
n3611) );
AOI22X1TS U4580 ( .A0(n3646), .A1(n3611), .B0(n3607), .B1(n3657), .Y(n3608)
);
XNOR2X1TS U4581 ( .A(n3609), .B(n3608), .Y(n3610) );
AOI22X1TS U4582 ( .A0(n3651), .A1(n3610), .B0(n3677), .B1(n3629), .Y(n1222)
);
OAI2BB2X1TS U4583 ( .B0(n3612), .B1(n3611), .A0N(n3776), .A1N(DMP_SFG[45]),
.Y(n3617) );
AOI22X1TS U4584 ( .A0(n3646), .A1(n3617), .B0(n3613), .B1(n3657), .Y(n3615)
);
NAND2X1TS U4585 ( .A(DmP_mant_SFG_SWR[48]), .B(n3726), .Y(n3618) );
OAI21XLTS U4586 ( .A0(DmP_mant_SFG_SWR[48]), .A1(n3726), .B0(n3618), .Y(
n3614) );
XNOR2X1TS U4587 ( .A(n3615), .B(n3614), .Y(n3616) );
AOI22X1TS U4588 ( .A0(n3651), .A1(n3616), .B0(n3778), .B1(n3649), .Y(n1221)
);
NOR2X1TS U4589 ( .A(DMP_SFG[47]), .B(n3848), .Y(n3625) );
AOI21X1TS U4590 ( .A0(DMP_SFG[47]), .A1(n3848), .B0(n3625), .Y(n3621) );
AOI22X1TS U4591 ( .A0(DMP_SFG[46]), .A1(n3817), .B0(n3618), .B1(n3617), .Y(
n3624) );
AOI22X1TS U4592 ( .A0(n3646), .A1(n3624), .B0(n3619), .B1(n3657), .Y(n3620)
);
XNOR2X1TS U4593 ( .A(n3621), .B(n3620), .Y(n3623) );
AOI22X1TS U4594 ( .A0(n3651), .A1(n3623), .B0(n3708), .B1(n3622), .Y(n1220)
);
OAI2BB2X1TS U4595 ( .B0(n3625), .B1(n3624), .A0N(n3848), .A1N(DMP_SFG[47]),
.Y(n3631) );
AOI22X1TS U4596 ( .A0(n3646), .A1(n3631), .B0(n3626), .B1(n3657), .Y(n3628)
);
NAND2X1TS U4597 ( .A(DmP_mant_SFG_SWR[50]), .B(n3727), .Y(n3632) );
OAI21XLTS U4598 ( .A0(DmP_mant_SFG_SWR[50]), .A1(n3727), .B0(n3632), .Y(
n3627) );
XNOR2X1TS U4599 ( .A(n3628), .B(n3627), .Y(n3630) );
AOI22X1TS U4600 ( .A0(n3651), .A1(n3630), .B0(n3761), .B1(n3629), .Y(n1219)
);
NOR2X1TS U4601 ( .A(DMP_SFG[49]), .B(n3777), .Y(n3638) );
AOI21X1TS U4602 ( .A0(DMP_SFG[49]), .A1(n3777), .B0(n3638), .Y(n3635) );
AOI22X1TS U4603 ( .A0(DMP_SFG[48]), .A1(n3818), .B0(n3632), .B1(n3631), .Y(
n3637) );
AOI22X1TS U4604 ( .A0(n3646), .A1(n3637), .B0(n3633), .B1(n3657), .Y(n3634)
);
XNOR2X1TS U4605 ( .A(n3635), .B(n3634), .Y(n3636) );
AOI22X1TS U4606 ( .A0(n3651), .A1(n3636), .B0(n3676), .B1(n3649), .Y(n1218)
);
OAI2BB2X1TS U4607 ( .B0(n3638), .B1(n3637), .A0N(n3777), .A1N(DMP_SFG[49]),
.Y(n3643) );
AOI22X1TS U4608 ( .A0(n3646), .A1(n3643), .B0(n3639), .B1(n3657), .Y(n3641)
);
NAND2X1TS U4609 ( .A(DmP_mant_SFG_SWR[52]), .B(n3794), .Y(n3644) );
OAI21XLTS U4610 ( .A0(DmP_mant_SFG_SWR[52]), .A1(n3794), .B0(n3644), .Y(
n3640) );
XNOR2X1TS U4611 ( .A(n3641), .B(n3640), .Y(n3642) );
AOI22X1TS U4612 ( .A0(n3651), .A1(n3642), .B0(n3760), .B1(n3649), .Y(n1217)
);
NOR2X1TS U4613 ( .A(DmP_mant_SFG_SWR[53]), .B(n3804), .Y(n3656) );
AOI21X1TS U4614 ( .A0(DmP_mant_SFG_SWR[53]), .A1(n3804), .B0(n3656), .Y(
n3648) );
AOI22X1TS U4615 ( .A0(DMP_SFG[50]), .A1(n3674), .B0(n3644), .B1(n3643), .Y(
n3652) );
AOI22X1TS U4616 ( .A0(n3646), .A1(n3652), .B0(n3645), .B1(n3657), .Y(n3647)
);
XNOR2X1TS U4617 ( .A(n3648), .B(n3647), .Y(n3650) );
AOI22X1TS U4618 ( .A0(n3651), .A1(n3650), .B0(n3855), .B1(n3649), .Y(n1216)
);
AOI21X1TS U4619 ( .A0(DmP_mant_SFG_SWR[53]), .A1(n3804), .B0(n3652), .Y(
n3655) );
OAI32X1TS U4620 ( .A0(n3657), .A1(n3656), .A2(n3655), .B0(n3654), .B1(n3451),
.Y(n3658) );
XOR2X1TS U4621 ( .A(DmP_mant_SFG_SWR[54]), .B(n3658), .Y(n3660) );
AOI22X1TS U4622 ( .A0(n3661), .A1(n3660), .B0(n3735), .B1(n3659), .Y(n1215)
);
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_ASIC_fpu_syn_constraints_noclk.tcl_syn.sdf");
endmodule
|
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_system_CPU_test_bench (
// inputs:
A_bstatus_reg,
A_cmp_result,
A_ctrl_exception,
A_ctrl_ld_non_bypass,
A_dst_regnum,
A_en,
A_estatus_reg,
A_ienable_reg,
A_ipending_reg,
A_iw,
A_mem_byte_en,
A_op_hbreak,
A_op_intr,
A_pcb,
A_st_data,
A_status_reg,
A_valid,
A_wr_data_unfiltered,
A_wr_dst_reg,
E_add_br_to_taken_history_unfiltered,
E_logic_result,
E_valid,
M_bht_ptr_unfiltered,
M_bht_wr_data_unfiltered,
M_bht_wr_en_unfiltered,
M_mem_baddr,
M_target_pcb,
M_valid,
W_dst_regnum,
W_iw,
W_iw_op,
W_iw_opx,
W_pcb,
W_valid,
W_vinst,
W_wr_dst_reg,
clk,
d_address,
d_byteenable,
d_read,
d_write,
i_address,
i_read,
i_readdatavalid,
reset_n,
// outputs:
A_wr_data_filtered,
E_add_br_to_taken_history_filtered,
E_src1_eq_src2,
M_bht_ptr_filtered,
M_bht_wr_data_filtered,
M_bht_wr_en_filtered,
test_has_ended
)
;
output [ 31: 0] A_wr_data_filtered;
output E_add_br_to_taken_history_filtered;
output E_src1_eq_src2;
output [ 7: 0] M_bht_ptr_filtered;
output [ 1: 0] M_bht_wr_data_filtered;
output M_bht_wr_en_filtered;
output test_has_ended;
input [ 31: 0] A_bstatus_reg;
input A_cmp_result;
input A_ctrl_exception;
input A_ctrl_ld_non_bypass;
input [ 4: 0] A_dst_regnum;
input A_en;
input [ 31: 0] A_estatus_reg;
input [ 31: 0] A_ienable_reg;
input [ 31: 0] A_ipending_reg;
input [ 31: 0] A_iw;
input [ 3: 0] A_mem_byte_en;
input A_op_hbreak;
input A_op_intr;
input [ 27: 0] A_pcb;
input [ 31: 0] A_st_data;
input [ 31: 0] A_status_reg;
input A_valid;
input [ 31: 0] A_wr_data_unfiltered;
input A_wr_dst_reg;
input E_add_br_to_taken_history_unfiltered;
input [ 31: 0] E_logic_result;
input E_valid;
input [ 7: 0] M_bht_ptr_unfiltered;
input [ 1: 0] M_bht_wr_data_unfiltered;
input M_bht_wr_en_unfiltered;
input [ 27: 0] M_mem_baddr;
input [ 27: 0] M_target_pcb;
input M_valid;
input [ 4: 0] W_dst_regnum;
input [ 31: 0] W_iw;
input [ 5: 0] W_iw_op;
input [ 5: 0] W_iw_opx;
input [ 27: 0] W_pcb;
input W_valid;
input [ 55: 0] W_vinst;
input W_wr_dst_reg;
input clk;
input [ 27: 0] d_address;
input [ 3: 0] d_byteenable;
input d_read;
input d_write;
input [ 27: 0] i_address;
input i_read;
input i_readdatavalid;
input reset_n;
reg [ 27: 0] A_mem_baddr;
reg [ 27: 0] A_target_pcb;
wire [ 31: 0] A_wr_data_filtered;
wire A_wr_data_unfiltered_0_is_x;
wire A_wr_data_unfiltered_10_is_x;
wire A_wr_data_unfiltered_11_is_x;
wire A_wr_data_unfiltered_12_is_x;
wire A_wr_data_unfiltered_13_is_x;
wire A_wr_data_unfiltered_14_is_x;
wire A_wr_data_unfiltered_15_is_x;
wire A_wr_data_unfiltered_16_is_x;
wire A_wr_data_unfiltered_17_is_x;
wire A_wr_data_unfiltered_18_is_x;
wire A_wr_data_unfiltered_19_is_x;
wire A_wr_data_unfiltered_1_is_x;
wire A_wr_data_unfiltered_20_is_x;
wire A_wr_data_unfiltered_21_is_x;
wire A_wr_data_unfiltered_22_is_x;
wire A_wr_data_unfiltered_23_is_x;
wire A_wr_data_unfiltered_24_is_x;
wire A_wr_data_unfiltered_25_is_x;
wire A_wr_data_unfiltered_26_is_x;
wire A_wr_data_unfiltered_27_is_x;
wire A_wr_data_unfiltered_28_is_x;
wire A_wr_data_unfiltered_29_is_x;
wire A_wr_data_unfiltered_2_is_x;
wire A_wr_data_unfiltered_30_is_x;
wire A_wr_data_unfiltered_31_is_x;
wire A_wr_data_unfiltered_3_is_x;
wire A_wr_data_unfiltered_4_is_x;
wire A_wr_data_unfiltered_5_is_x;
wire A_wr_data_unfiltered_6_is_x;
wire A_wr_data_unfiltered_7_is_x;
wire A_wr_data_unfiltered_8_is_x;
wire A_wr_data_unfiltered_9_is_x;
wire E_add_br_to_taken_history_filtered;
wire E_src1_eq_src2;
wire [ 7: 0] M_bht_ptr_filtered;
wire [ 1: 0] M_bht_wr_data_filtered;
wire M_bht_wr_en_filtered;
wire W_op_add;
wire W_op_addi;
wire W_op_and;
wire W_op_andhi;
wire W_op_andi;
wire W_op_beq;
wire W_op_bge;
wire W_op_bgeu;
wire W_op_blt;
wire W_op_bltu;
wire W_op_bne;
wire W_op_br;
wire W_op_break;
wire W_op_bret;
wire W_op_call;
wire W_op_callr;
wire W_op_cmpeq;
wire W_op_cmpeqi;
wire W_op_cmpge;
wire W_op_cmpgei;
wire W_op_cmpgeu;
wire W_op_cmpgeui;
wire W_op_cmplt;
wire W_op_cmplti;
wire W_op_cmpltu;
wire W_op_cmpltui;
wire W_op_cmpne;
wire W_op_cmpnei;
wire W_op_crst;
wire W_op_custom;
wire W_op_div;
wire W_op_divu;
wire W_op_eret;
wire W_op_flushd;
wire W_op_flushda;
wire W_op_flushi;
wire W_op_flushp;
wire W_op_hbreak;
wire W_op_initd;
wire W_op_initda;
wire W_op_initi;
wire W_op_intr;
wire W_op_jmp;
wire W_op_jmpi;
wire W_op_ldb;
wire W_op_ldbio;
wire W_op_ldbu;
wire W_op_ldbuio;
wire W_op_ldh;
wire W_op_ldhio;
wire W_op_ldhu;
wire W_op_ldhuio;
wire W_op_ldl;
wire W_op_ldw;
wire W_op_ldwio;
wire W_op_mul;
wire W_op_muli;
wire W_op_mulxss;
wire W_op_mulxsu;
wire W_op_mulxuu;
wire W_op_nextpc;
wire W_op_nor;
wire W_op_opx;
wire W_op_or;
wire W_op_orhi;
wire W_op_ori;
wire W_op_rdctl;
wire W_op_rdprs;
wire W_op_ret;
wire W_op_rol;
wire W_op_roli;
wire W_op_ror;
wire W_op_rsv02;
wire W_op_rsv09;
wire W_op_rsv10;
wire W_op_rsv17;
wire W_op_rsv18;
wire W_op_rsv25;
wire W_op_rsv26;
wire W_op_rsv33;
wire W_op_rsv34;
wire W_op_rsv41;
wire W_op_rsv42;
wire W_op_rsv49;
wire W_op_rsv57;
wire W_op_rsv61;
wire W_op_rsv62;
wire W_op_rsv63;
wire W_op_rsvx00;
wire W_op_rsvx10;
wire W_op_rsvx15;
wire W_op_rsvx17;
wire W_op_rsvx21;
wire W_op_rsvx25;
wire W_op_rsvx33;
wire W_op_rsvx34;
wire W_op_rsvx35;
wire W_op_rsvx42;
wire W_op_rsvx43;
wire W_op_rsvx44;
wire W_op_rsvx47;
wire W_op_rsvx50;
wire W_op_rsvx51;
wire W_op_rsvx55;
wire W_op_rsvx56;
wire W_op_rsvx60;
wire W_op_rsvx63;
wire W_op_sll;
wire W_op_slli;
wire W_op_sra;
wire W_op_srai;
wire W_op_srl;
wire W_op_srli;
wire W_op_stb;
wire W_op_stbio;
wire W_op_stc;
wire W_op_sth;
wire W_op_sthio;
wire W_op_stw;
wire W_op_stwio;
wire W_op_sub;
wire W_op_sync;
wire W_op_trap;
wire W_op_wrctl;
wire W_op_wrprs;
wire W_op_xor;
wire W_op_xorhi;
wire W_op_xori;
wire test_has_ended;
assign W_op_call = W_iw_op == 0;
assign W_op_jmpi = W_iw_op == 1;
assign W_op_ldbu = W_iw_op == 3;
assign W_op_addi = W_iw_op == 4;
assign W_op_stb = W_iw_op == 5;
assign W_op_br = W_iw_op == 6;
assign W_op_ldb = W_iw_op == 7;
assign W_op_cmpgei = W_iw_op == 8;
assign W_op_ldhu = W_iw_op == 11;
assign W_op_andi = W_iw_op == 12;
assign W_op_sth = W_iw_op == 13;
assign W_op_bge = W_iw_op == 14;
assign W_op_ldh = W_iw_op == 15;
assign W_op_cmplti = W_iw_op == 16;
assign W_op_initda = W_iw_op == 19;
assign W_op_ori = W_iw_op == 20;
assign W_op_stw = W_iw_op == 21;
assign W_op_blt = W_iw_op == 22;
assign W_op_ldw = W_iw_op == 23;
assign W_op_cmpnei = W_iw_op == 24;
assign W_op_flushda = W_iw_op == 27;
assign W_op_xori = W_iw_op == 28;
assign W_op_stc = W_iw_op == 29;
assign W_op_bne = W_iw_op == 30;
assign W_op_ldl = W_iw_op == 31;
assign W_op_cmpeqi = W_iw_op == 32;
assign W_op_ldbuio = W_iw_op == 35;
assign W_op_muli = W_iw_op == 36;
assign W_op_stbio = W_iw_op == 37;
assign W_op_beq = W_iw_op == 38;
assign W_op_ldbio = W_iw_op == 39;
assign W_op_cmpgeui = W_iw_op == 40;
assign W_op_ldhuio = W_iw_op == 43;
assign W_op_andhi = W_iw_op == 44;
assign W_op_sthio = W_iw_op == 45;
assign W_op_bgeu = W_iw_op == 46;
assign W_op_ldhio = W_iw_op == 47;
assign W_op_cmpltui = W_iw_op == 48;
assign W_op_initd = W_iw_op == 51;
assign W_op_orhi = W_iw_op == 52;
assign W_op_stwio = W_iw_op == 53;
assign W_op_bltu = W_iw_op == 54;
assign W_op_ldwio = W_iw_op == 55;
assign W_op_rdprs = W_iw_op == 56;
assign W_op_flushd = W_iw_op == 59;
assign W_op_xorhi = W_iw_op == 60;
assign W_op_rsv02 = W_iw_op == 2;
assign W_op_rsv09 = W_iw_op == 9;
assign W_op_rsv10 = W_iw_op == 10;
assign W_op_rsv17 = W_iw_op == 17;
assign W_op_rsv18 = W_iw_op == 18;
assign W_op_rsv25 = W_iw_op == 25;
assign W_op_rsv26 = W_iw_op == 26;
assign W_op_rsv33 = W_iw_op == 33;
assign W_op_rsv34 = W_iw_op == 34;
assign W_op_rsv41 = W_iw_op == 41;
assign W_op_rsv42 = W_iw_op == 42;
assign W_op_rsv49 = W_iw_op == 49;
assign W_op_rsv57 = W_iw_op == 57;
assign W_op_rsv61 = W_iw_op == 61;
assign W_op_rsv62 = W_iw_op == 62;
assign W_op_rsv63 = W_iw_op == 63;
assign W_op_eret = W_op_opx & (W_iw_opx == 1);
assign W_op_roli = W_op_opx & (W_iw_opx == 2);
assign W_op_rol = W_op_opx & (W_iw_opx == 3);
assign W_op_flushp = W_op_opx & (W_iw_opx == 4);
assign W_op_ret = W_op_opx & (W_iw_opx == 5);
assign W_op_nor = W_op_opx & (W_iw_opx == 6);
assign W_op_mulxuu = W_op_opx & (W_iw_opx == 7);
assign W_op_cmpge = W_op_opx & (W_iw_opx == 8);
assign W_op_bret = W_op_opx & (W_iw_opx == 9);
assign W_op_ror = W_op_opx & (W_iw_opx == 11);
assign W_op_flushi = W_op_opx & (W_iw_opx == 12);
assign W_op_jmp = W_op_opx & (W_iw_opx == 13);
assign W_op_and = W_op_opx & (W_iw_opx == 14);
assign W_op_cmplt = W_op_opx & (W_iw_opx == 16);
assign W_op_slli = W_op_opx & (W_iw_opx == 18);
assign W_op_sll = W_op_opx & (W_iw_opx == 19);
assign W_op_wrprs = W_op_opx & (W_iw_opx == 20);
assign W_op_or = W_op_opx & (W_iw_opx == 22);
assign W_op_mulxsu = W_op_opx & (W_iw_opx == 23);
assign W_op_cmpne = W_op_opx & (W_iw_opx == 24);
assign W_op_srli = W_op_opx & (W_iw_opx == 26);
assign W_op_srl = W_op_opx & (W_iw_opx == 27);
assign W_op_nextpc = W_op_opx & (W_iw_opx == 28);
assign W_op_callr = W_op_opx & (W_iw_opx == 29);
assign W_op_xor = W_op_opx & (W_iw_opx == 30);
assign W_op_mulxss = W_op_opx & (W_iw_opx == 31);
assign W_op_cmpeq = W_op_opx & (W_iw_opx == 32);
assign W_op_divu = W_op_opx & (W_iw_opx == 36);
assign W_op_div = W_op_opx & (W_iw_opx == 37);
assign W_op_rdctl = W_op_opx & (W_iw_opx == 38);
assign W_op_mul = W_op_opx & (W_iw_opx == 39);
assign W_op_cmpgeu = W_op_opx & (W_iw_opx == 40);
assign W_op_initi = W_op_opx & (W_iw_opx == 41);
assign W_op_trap = W_op_opx & (W_iw_opx == 45);
assign W_op_wrctl = W_op_opx & (W_iw_opx == 46);
assign W_op_cmpltu = W_op_opx & (W_iw_opx == 48);
assign W_op_add = W_op_opx & (W_iw_opx == 49);
assign W_op_break = W_op_opx & (W_iw_opx == 52);
assign W_op_hbreak = W_op_opx & (W_iw_opx == 53);
assign W_op_sync = W_op_opx & (W_iw_opx == 54);
assign W_op_sub = W_op_opx & (W_iw_opx == 57);
assign W_op_srai = W_op_opx & (W_iw_opx == 58);
assign W_op_sra = W_op_opx & (W_iw_opx == 59);
assign W_op_intr = W_op_opx & (W_iw_opx == 61);
assign W_op_crst = W_op_opx & (W_iw_opx == 62);
assign W_op_rsvx00 = W_op_opx & (W_iw_opx == 0);
assign W_op_rsvx10 = W_op_opx & (W_iw_opx == 10);
assign W_op_rsvx15 = W_op_opx & (W_iw_opx == 15);
assign W_op_rsvx17 = W_op_opx & (W_iw_opx == 17);
assign W_op_rsvx21 = W_op_opx & (W_iw_opx == 21);
assign W_op_rsvx25 = W_op_opx & (W_iw_opx == 25);
assign W_op_rsvx33 = W_op_opx & (W_iw_opx == 33);
assign W_op_rsvx34 = W_op_opx & (W_iw_opx == 34);
assign W_op_rsvx35 = W_op_opx & (W_iw_opx == 35);
assign W_op_rsvx42 = W_op_opx & (W_iw_opx == 42);
assign W_op_rsvx43 = W_op_opx & (W_iw_opx == 43);
assign W_op_rsvx44 = W_op_opx & (W_iw_opx == 44);
assign W_op_rsvx47 = W_op_opx & (W_iw_opx == 47);
assign W_op_rsvx50 = W_op_opx & (W_iw_opx == 50);
assign W_op_rsvx51 = W_op_opx & (W_iw_opx == 51);
assign W_op_rsvx55 = W_op_opx & (W_iw_opx == 55);
assign W_op_rsvx56 = W_op_opx & (W_iw_opx == 56);
assign W_op_rsvx60 = W_op_opx & (W_iw_opx == 60);
assign W_op_rsvx63 = W_op_opx & (W_iw_opx == 63);
assign W_op_opx = W_iw_op == 58;
assign W_op_custom = W_iw_op == 50;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
A_target_pcb <= 0;
else if (A_en)
A_target_pcb <= M_target_pcb;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
A_mem_baddr <= 0;
else if (A_en)
A_mem_baddr <= M_mem_baddr;
end
assign E_src1_eq_src2 = E_logic_result == 0;
//Propagating 'X' data bits
assign E_add_br_to_taken_history_filtered = E_add_br_to_taken_history_unfiltered;
//Propagating 'X' data bits
assign M_bht_wr_en_filtered = M_bht_wr_en_unfiltered;
//Propagating 'X' data bits
assign M_bht_wr_data_filtered = M_bht_wr_data_unfiltered;
//Propagating 'X' data bits
assign M_bht_ptr_filtered = M_bht_ptr_unfiltered;
assign test_has_ended = 1'b0;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//Clearing 'X' data bits
assign A_wr_data_unfiltered_0_is_x = ^(A_wr_data_unfiltered[0]) === 1'bx;
assign A_wr_data_filtered[0] = (A_wr_data_unfiltered_0_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[0];
assign A_wr_data_unfiltered_1_is_x = ^(A_wr_data_unfiltered[1]) === 1'bx;
assign A_wr_data_filtered[1] = (A_wr_data_unfiltered_1_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[1];
assign A_wr_data_unfiltered_2_is_x = ^(A_wr_data_unfiltered[2]) === 1'bx;
assign A_wr_data_filtered[2] = (A_wr_data_unfiltered_2_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[2];
assign A_wr_data_unfiltered_3_is_x = ^(A_wr_data_unfiltered[3]) === 1'bx;
assign A_wr_data_filtered[3] = (A_wr_data_unfiltered_3_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[3];
assign A_wr_data_unfiltered_4_is_x = ^(A_wr_data_unfiltered[4]) === 1'bx;
assign A_wr_data_filtered[4] = (A_wr_data_unfiltered_4_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[4];
assign A_wr_data_unfiltered_5_is_x = ^(A_wr_data_unfiltered[5]) === 1'bx;
assign A_wr_data_filtered[5] = (A_wr_data_unfiltered_5_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[5];
assign A_wr_data_unfiltered_6_is_x = ^(A_wr_data_unfiltered[6]) === 1'bx;
assign A_wr_data_filtered[6] = (A_wr_data_unfiltered_6_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[6];
assign A_wr_data_unfiltered_7_is_x = ^(A_wr_data_unfiltered[7]) === 1'bx;
assign A_wr_data_filtered[7] = (A_wr_data_unfiltered_7_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[7];
assign A_wr_data_unfiltered_8_is_x = ^(A_wr_data_unfiltered[8]) === 1'bx;
assign A_wr_data_filtered[8] = (A_wr_data_unfiltered_8_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[8];
assign A_wr_data_unfiltered_9_is_x = ^(A_wr_data_unfiltered[9]) === 1'bx;
assign A_wr_data_filtered[9] = (A_wr_data_unfiltered_9_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[9];
assign A_wr_data_unfiltered_10_is_x = ^(A_wr_data_unfiltered[10]) === 1'bx;
assign A_wr_data_filtered[10] = (A_wr_data_unfiltered_10_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[10];
assign A_wr_data_unfiltered_11_is_x = ^(A_wr_data_unfiltered[11]) === 1'bx;
assign A_wr_data_filtered[11] = (A_wr_data_unfiltered_11_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[11];
assign A_wr_data_unfiltered_12_is_x = ^(A_wr_data_unfiltered[12]) === 1'bx;
assign A_wr_data_filtered[12] = (A_wr_data_unfiltered_12_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[12];
assign A_wr_data_unfiltered_13_is_x = ^(A_wr_data_unfiltered[13]) === 1'bx;
assign A_wr_data_filtered[13] = (A_wr_data_unfiltered_13_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[13];
assign A_wr_data_unfiltered_14_is_x = ^(A_wr_data_unfiltered[14]) === 1'bx;
assign A_wr_data_filtered[14] = (A_wr_data_unfiltered_14_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[14];
assign A_wr_data_unfiltered_15_is_x = ^(A_wr_data_unfiltered[15]) === 1'bx;
assign A_wr_data_filtered[15] = (A_wr_data_unfiltered_15_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[15];
assign A_wr_data_unfiltered_16_is_x = ^(A_wr_data_unfiltered[16]) === 1'bx;
assign A_wr_data_filtered[16] = (A_wr_data_unfiltered_16_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[16];
assign A_wr_data_unfiltered_17_is_x = ^(A_wr_data_unfiltered[17]) === 1'bx;
assign A_wr_data_filtered[17] = (A_wr_data_unfiltered_17_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[17];
assign A_wr_data_unfiltered_18_is_x = ^(A_wr_data_unfiltered[18]) === 1'bx;
assign A_wr_data_filtered[18] = (A_wr_data_unfiltered_18_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[18];
assign A_wr_data_unfiltered_19_is_x = ^(A_wr_data_unfiltered[19]) === 1'bx;
assign A_wr_data_filtered[19] = (A_wr_data_unfiltered_19_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[19];
assign A_wr_data_unfiltered_20_is_x = ^(A_wr_data_unfiltered[20]) === 1'bx;
assign A_wr_data_filtered[20] = (A_wr_data_unfiltered_20_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[20];
assign A_wr_data_unfiltered_21_is_x = ^(A_wr_data_unfiltered[21]) === 1'bx;
assign A_wr_data_filtered[21] = (A_wr_data_unfiltered_21_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[21];
assign A_wr_data_unfiltered_22_is_x = ^(A_wr_data_unfiltered[22]) === 1'bx;
assign A_wr_data_filtered[22] = (A_wr_data_unfiltered_22_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[22];
assign A_wr_data_unfiltered_23_is_x = ^(A_wr_data_unfiltered[23]) === 1'bx;
assign A_wr_data_filtered[23] = (A_wr_data_unfiltered_23_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[23];
assign A_wr_data_unfiltered_24_is_x = ^(A_wr_data_unfiltered[24]) === 1'bx;
assign A_wr_data_filtered[24] = (A_wr_data_unfiltered_24_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[24];
assign A_wr_data_unfiltered_25_is_x = ^(A_wr_data_unfiltered[25]) === 1'bx;
assign A_wr_data_filtered[25] = (A_wr_data_unfiltered_25_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[25];
assign A_wr_data_unfiltered_26_is_x = ^(A_wr_data_unfiltered[26]) === 1'bx;
assign A_wr_data_filtered[26] = (A_wr_data_unfiltered_26_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[26];
assign A_wr_data_unfiltered_27_is_x = ^(A_wr_data_unfiltered[27]) === 1'bx;
assign A_wr_data_filtered[27] = (A_wr_data_unfiltered_27_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[27];
assign A_wr_data_unfiltered_28_is_x = ^(A_wr_data_unfiltered[28]) === 1'bx;
assign A_wr_data_filtered[28] = (A_wr_data_unfiltered_28_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[28];
assign A_wr_data_unfiltered_29_is_x = ^(A_wr_data_unfiltered[29]) === 1'bx;
assign A_wr_data_filtered[29] = (A_wr_data_unfiltered_29_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[29];
assign A_wr_data_unfiltered_30_is_x = ^(A_wr_data_unfiltered[30]) === 1'bx;
assign A_wr_data_filtered[30] = (A_wr_data_unfiltered_30_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[30];
assign A_wr_data_unfiltered_31_is_x = ^(A_wr_data_unfiltered[31]) === 1'bx;
assign A_wr_data_filtered[31] = (A_wr_data_unfiltered_31_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[31];
always @(posedge clk)
begin
if (reset_n)
if (^(W_wr_dst_reg) === 1'bx)
begin
$write("%0d ns: ERROR: nios_system_CPU_test_bench/W_wr_dst_reg is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_wr_dst_reg)
if (^(W_dst_regnum) === 1'bx)
begin
$write("%0d ns: ERROR: nios_system_CPU_test_bench/W_dst_regnum is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(W_valid) === 1'bx)
begin
$write("%0d ns: ERROR: nios_system_CPU_test_bench/W_valid is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_valid)
if (^(W_pcb) === 1'bx)
begin
$write("%0d ns: ERROR: nios_system_CPU_test_bench/W_pcb is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_valid)
if (^(W_iw) === 1'bx)
begin
$write("%0d ns: ERROR: nios_system_CPU_test_bench/W_iw is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(A_en) === 1'bx)
begin
$write("%0d ns: ERROR: nios_system_CPU_test_bench/A_en is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(E_valid) === 1'bx)
begin
$write("%0d ns: ERROR: nios_system_CPU_test_bench/E_valid is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(M_valid) === 1'bx)
begin
$write("%0d ns: ERROR: nios_system_CPU_test_bench/M_valid is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(A_valid) === 1'bx)
begin
$write("%0d ns: ERROR: nios_system_CPU_test_bench/A_valid is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (A_valid & A_en & A_wr_dst_reg)
if (^(A_wr_data_unfiltered) === 1'bx)
begin
$write("%0d ns: WARNING: nios_system_CPU_test_bench/A_wr_data_unfiltered is 'x'\n", $time);
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(A_status_reg) === 1'bx)
begin
$write("%0d ns: ERROR: nios_system_CPU_test_bench/A_status_reg is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(A_estatus_reg) === 1'bx)
begin
$write("%0d ns: ERROR: nios_system_CPU_test_bench/A_estatus_reg is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(A_bstatus_reg) === 1'bx)
begin
$write("%0d ns: ERROR: nios_system_CPU_test_bench/A_bstatus_reg is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(i_read) === 1'bx)
begin
$write("%0d ns: ERROR: nios_system_CPU_test_bench/i_read is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (i_read)
if (^(i_address) === 1'bx)
begin
$write("%0d ns: ERROR: nios_system_CPU_test_bench/i_address is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(i_readdatavalid) === 1'bx)
begin
$write("%0d ns: ERROR: nios_system_CPU_test_bench/i_readdatavalid is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(d_write) === 1'bx)
begin
$write("%0d ns: ERROR: nios_system_CPU_test_bench/d_write is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (d_write)
if (^(d_byteenable) === 1'bx)
begin
$write("%0d ns: ERROR: nios_system_CPU_test_bench/d_byteenable is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (d_write | d_read)
if (^(d_address) === 1'bx)
begin
$write("%0d ns: ERROR: nios_system_CPU_test_bench/d_address is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(d_read) === 1'bx)
begin
$write("%0d ns: ERROR: nios_system_CPU_test_bench/d_read is 'x'\n", $time);
$stop;
end
end
reg [31:0] trace_handle; // for $fopen
initial
begin
trace_handle = $fopen("nios_system_CPU.tr");
$fwrite(trace_handle, "version 3\nnumThreads 1\n");
end
always @(posedge clk)
begin
if ((~reset_n || (A_valid & A_en)) && ~test_has_ended)
$fwrite(trace_handle, "%0d ns: %0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h\n", $time, ~reset_n, A_pcb, 0, A_op_intr, A_op_hbreak, A_iw, ~(A_op_intr | A_op_hbreak), A_wr_dst_reg, A_dst_regnum, 0, A_wr_data_filtered, A_mem_baddr, A_st_data, A_mem_byte_en, A_cmp_result, A_target_pcb, A_status_reg, A_estatus_reg, A_bstatus_reg, A_ienable_reg, A_ipending_reg, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, A_ctrl_exception ? 1 : 0, 0, 0, 0, 0);
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
//
// assign A_wr_data_filtered = A_wr_data_unfiltered;
//
//synthesis read_comments_as_HDL off
endmodule
|
// MBT 11/9/2014
//
// Synchronous 1-port ram.
// Only one read or one write may be done per cycle.
`define bsg_mem_1rw_sync_mask_write_bit_macro(bits,words) \
if (els_p == words && width_p == bits) \
begin: macro \
saed90_``bits``x``words``_1P_bit mem \
(.CE1 (clk_lo) \
,.WEB1 (~w_i) \
,.OEB1 (1'b0) \
,.CSB1 (~v_i) \
,.A1 (addr_i) \
,.I1 (data_i) \
,.O1 (data_o) \
,.WBM1 (w_mask_i) \
); \
end
module bsg_mem_1rw_sync_mask_write_bit #(parameter `BSG_INV_PARAM(width_p)
, parameter `BSG_INV_PARAM(els_p)
, parameter addr_width_lp=`BSG_SAFE_CLOG2(els_p)
, parameter enable_clock_gating_p=1'b0
)
(input clk_i
, input reset_i
, input v_i
, input w_i
, input [addr_width_lp-1:0] addr_i
, input [width_p-1:0] data_i
, input [width_p-1:0] w_mask_i
, output [width_p-1:0] data_o
);
wire clk_lo;
bsg_clkgate_optional icg
(.clk_i( clk_i )
,.en_i( v_i )
,.bypass_i( ~enable_clock_gating_p )
,.gated_clock_o( clk_lo )
);
// TODO: ADD ANY NEW RAM CONFIGURATIONS HERE
`bsg_mem_1rw_sync_mask_write_bit_macro (736, 64) else
`bsg_mem_1rw_sync_mask_write_bit_macro ( 96, 64) else
// Hack fo 7 bit ram to use 8 bit ram
if (els_p == 64 && width_p == 7)
begin: macro
logic [7:0] data_lo;
saed90_8x64_1P_bit mem
(.CE1 (clk_lo)
,.WEB1 (~w_i)
,.OEB1 (1'b0)
,.CSB1 (~v_i)
,.A1 (addr_i)
,.I1 ({1'b0, data_i})
,.O1 (data_lo)
,.WBM1 ({1'b0, w_mask_i})
);
assign data_o = data_lo[6:0];
end
else
// no hardened version found
begin: notmacro
bsg_mem_1rw_sync_mask_write_bit_synth
#(.width_p(width_p)
,.els_p(els_p)
) synth
(.clk_i (clk_lo)
,.reset_i
,.data_i
,.addr_i
,.v_i
,.w_mask_i
,.w_i
,.data_o
);
end // block: notmacro
// synopsys translate_off
always_ff @(posedge clk_lo)
if (v_i === 1)
assert ((reset_i === 'X) || (reset_i === 1'b1) || (addr_i < els_p))
else $error("Invalid address %x to %m of size %x (reset_i = %b, v_i = %b, clk_lo=%b)\n", addr_i, els_p, reset_i, v_i, clk_lo);
initial
begin
$display("## %L: instantiating width_p=%d, els_p=%d (%m)",width_p,els_p);
end
// synopsys translate_on
endmodule
`BSG_ABSTRACT_MODULE(bsg_mem_1rw_sync_mask_write_bit)
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_pll.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
//
// Unit Name: bw_pll (phase-locked loop)
// Block Name: PLL
//
//-----------------------------------------------------------------------------
`include "sys.h"
`define DEFAULT_JMHZ 200
`define DEFAULT_JDIV 31
`define OSC_DLY 10
`define PLL_START_UP_DLY 50000
//`define SLOW_CLK_MULT 256
`define SLOW_PLL_WIDTH 100000
`define RAW_CLK_OUTPUT_DLY 300
`define PHASE_LOCK_THRESHOLD 5 // num of matches to detect for 'phase lock'
`define FREQ_STEP_COUNT 3 // ref-clocks spent to step from slow to target freq
`define VCO_OUT_DLY 50 // ps dly vco_reg->vco_out (to guarantee fb dly is non-zero)
`define FEEDBACK_DLY_MAX 10000 // ps dly pll_clk_out->feedback
module bw_pll (
// Inputs:
pll_sys_clk , // Differential System Clock Inputs
pll_bypass , // 0: PLL Output, 1: Bypass Clock
pll_arst_l , // PLL Asynchronous Reset, active low
l2clk , // Feedback Clock from l2clk Grid
pll_clamp_fltr , // Multiplexed Pin. Default=0
pll_div1 , // Frequency Divider 1 : Input Reference, cnt=div1+1
// For Niagara div1=0, => divide by 1
pll_div2 , // Frequency Divider 2 : Feedback Clock , cnt=div2+1
// Program div2 to desired VCO frequency.
// Ex. sys_clk=200MHz, div2=7, vco=1.6GHz, clk_out=1.6GHz
pll_div3 , // Frequency Divider 3 : Clocktree Drive, cnt=div3+1
// For Niagara div3=0, => divide by 1
vdd_pll , // Vdd for PLL
pll_char_in , // Characterization In. Default=0
testmode , // PLL Test Mode. Default=0
vreg_seldb_l , // Default=0
// Outputs:
pll_raw_clk_out , // Raw Clock Output from Differential Reciever
pll_vco_out , // VCO Output
pll_clk_out , // PLL Clock Output to CTU Digital
pll_clk_out_l , // PLL Clock Output to CTU Digital, Invert of cktree_drv
pll_char_out // Characterization Output to IO
);
input [1:0] pll_sys_clk;
input pll_bypass;
input pll_arst_l;
input l2clk;
input pll_clamp_fltr;
input [5:0] pll_div1;
input [5:0] pll_div2;
input [5:0] pll_div3;
input vdd_pll;
input pll_char_in;
input testmode;
input vreg_seldb_l;
output pll_raw_clk_out;
output pll_vco_out;
output pll_clk_out;
output pll_clk_out_l;
output [1:0] pll_char_out;
//synopsys translate_off
wire [4:0] jdiv ; // driven by env. meaningful range is 4 to 24
reg [7:0] jmhz ; // computed here, to be used by env
integer ref_clk_last_edge ;
integer ref_clk_this_edge ;
integer ref_clk_width ;
reg ref_clk_vld ;
reg slow_ext_clk_reg ;
reg fast_ext_clk_reg ;
integer fast_ext_clk_jdiv;
integer fast_ext_clk_width;
reg fast_int_clk_reg ;
integer fast_int_clk_jdiv ;
integer fast_int_clk_width ;
integer fast_int_clk_residue ;
reg osc_reg0;
reg osc_reg1;
reg osc_reg2;
reg osc_reg3;
reg osc_out;
integer osc_dly0;
integer osc_dly1;
integer osc_dly2;
integer osc_dly3;
reg osc_dly0_set;
reg osc_dly1_set;
reg osc_dly2_set;
reg osc_dly3_set;
reg vco_reg;
reg vco_off;
wire vco_out;
integer freq_step_ctr;
wire freq_locked ;
reg phase_locked;
reg edge_locked;
integer phase_match_ctr;
integer sync_errors;
wire ref_clk = pll_sys_clk[0] ;
wire feedback = l2clk ;
integer beg_time, end_time ;
wire pll_clk_free ;
wire pll_lock = freq_locked && phase_locked &&
(phase_match_ctr>`PHASE_LOCK_THRESHOLD) &&
(sync_errors==0) ;
reg pll_raw_clk_reg ;
// PLL Characterization Ports
assign pll_char_out[0] = pll_char_in; // Like this to check connections
assign pll_char_out[1] = ~pll_char_in; // Like this to check connections
// PLL Bypass Mux
assign pll_clk_out = pll_bypass ? pll_sys_clk[0] : vco_out ;
assign pll_clk_out_l = ~pll_clk_out;
assign pll_clk_free = pll_bypass ? fast_ext_clk_reg : osc_out ;
assign pll_vco_out = vco_out;
assign pll_raw_clk_out = pll_raw_clk_reg ;
initial pll_raw_clk_reg = 1'b0 ;
always @(pll_sys_clk[0]) begin
#(`RAW_CLK_OUTPUT_DLY)
pll_raw_clk_reg = pll_sys_clk[0];
end
//assign #(`RAW_CLK_OUTPUT_DLY) pll_raw_clk_out = pll_sys_clk[0];
// slow_ext_clk is a free running clock whose frequency is specified by
// plusarg. This signal is not used internally, but is expected to be
// tapped externally to drive reference clk
initial begin
if (! $value$plusargs("jmhz=%d", jmhz)) jmhz = `DEFAULT_JMHZ ;
ref_clk_width = 1000000/(2*jmhz) ; // ps
slow_ext_clk_reg = 1'b0 ;
forever begin
#(ref_clk_width) slow_ext_clk_reg = ~slow_ext_clk_reg ;
end
end
// fast_ext_clk is a free running multiple of slow_ext_clk.
// It is generated such that exactly 'jdiv' periods of it fit within each
// of the high or the low windows of slow_ext_clk.
// 'jdiv' is a dynamic value which can be driven by the environment at any
// time, but its value is sampled on every rising edge of slow_ext_clock.
// Since the period of slow_ext_clk may not divisible by jdiv, the low
// period of fast_ext_clk just before an edge of slow_ext_clk is stretched
// if necessary, so that an edge of slow_ext_clk is always coincident with
// a rising edge of fast_ext_clk.
// Note that this signal is not used internally. It is expected to be
// tapped externally to drive vera interface.
initial begin
fast_ext_clk_jdiv = `DEFAULT_JDIV ;
forever begin
@(jdiv) @(negedge slow_ext_clk_reg) #1
fast_ext_clk_jdiv = jdiv ;
end
end
initial begin
fast_ext_clk_reg = 1'b0 ;
forever begin
@(slow_ext_clk_reg)
fast_ext_clk_reg = 1'b1 ;
fast_ext_clk_width = ref_clk_width/(2*fast_ext_clk_jdiv) ;
repeat ((2*fast_ext_clk_jdiv)-1)
#(fast_ext_clk_width) fast_ext_clk_reg = ~fast_ext_clk_reg ;
end
end
// ref_clk is expected to be driven externally such that its shape exactly
// matches that of ext_slow_clk (adding a delay is acceptable).
// The following logic continuously measures period of ref_clk by comparing
// its width to the expected value.
initial begin
ref_clk_vld = 1'b0 ;
@(posedge ref_clk) ref_clk_last_edge = $time ;
@(negedge ref_clk) ref_clk_this_edge = $time ;
forever begin
@(ref_clk)
ref_clk_last_edge = ref_clk_this_edge ;
ref_clk_this_edge = $time ;
if ((ref_clk_this_edge-ref_clk_last_edge) == ref_clk_width)
ref_clk_vld = 1'b1 ;
else
ref_clk_vld = 1'b0 ;
end
end
// fast_int_clk is similar to fast_ext_clk except that it is synchronized
// to ref_clk. It runs at twice the steady state frequency of PLL.
initial begin
fast_int_clk_jdiv = `DEFAULT_JDIV ;
forever begin
@(jdiv) @(negedge ref_clk) #1
fast_int_clk_jdiv = jdiv ;
end
end
initial begin
fast_int_clk_reg = 1'b0 ;
#1
forever begin
@(ref_clk)
fast_int_clk_reg = 1'b1 ;
fast_int_clk_width = ref_clk_width/(2*fast_int_clk_jdiv) ;
fast_int_clk_residue= ref_clk_width%(2*fast_int_clk_jdiv) ;
repeat ((2*fast_int_clk_jdiv)-1)
#(fast_int_clk_width) fast_int_clk_reg = ~fast_int_clk_reg ;
end
end
// osc_out is the same as fast_int_clk, with a dyamic amount of delay
// added in. The delay is set to zero at assertion of pll_arst, and
// then programmed by locking logic. The purpose of this is to fine
// tune the edge of the final pll_clk_out.
// Because the needed delay can be more than fast_int_clk period, it
// is injected in four smaller chunks.
initial begin
osc_reg0 = 0;
osc_reg1 = 0;
osc_reg2 = 0;
osc_reg3 = 0;
osc_out = 0;
osc_dly0 = 0;
osc_dly1 = 0;
osc_dly2 = 0;
osc_dly3 = 0;
osc_dly0_set = 0;
osc_dly1_set = 0;
osc_dly2_set = 0;
osc_dly3_set = 0;
end
always @(negedge pll_arst_l) begin
osc_dly0 = 0;
osc_dly1 = 0;
osc_dly2 = 0;
osc_dly3 = 0;
osc_dly0_set = 0;
osc_dly1_set = 0;
osc_dly2_set = 0;
osc_dly3_set = 0;
end
always @(posedge fast_int_clk_reg) begin
#(osc_dly0) osc_reg0 = 1'b1;
end
always @(negedge fast_int_clk_reg) begin
#(osc_dly0) osc_reg0 = 1'b0;
end
always @(posedge osc_reg0) begin
#(osc_dly1) osc_reg1 = 1'b1;
end
always @(negedge osc_reg0) begin
#(osc_dly1) osc_reg1 = 1'b0;
end
always @(posedge osc_reg1) begin
#(osc_dly2) osc_reg2 = 1'b1;
end
always @(negedge osc_reg1) begin
#(osc_dly2) osc_reg2 = 1'b0;
end
always @(posedge osc_reg2) begin
#(osc_dly3) osc_reg3 = 1'b1;
end
always @(negedge osc_reg2) begin
#(osc_dly3) osc_reg3 = 1'b0;
end
always @(posedge osc_reg3) begin
#(`OSC_DLY) osc_out = 1'b1;
end
always @(negedge osc_reg3) begin
#(`OSC_DLY) osc_out = 1'b0;
end
// freq_step_ctr is used to the divide osc_out to produce pll_clk_out.
// The value of counter is dynamic. On deassertion of pll_arst_l, the
// counter counts down towards zero, resulting in a continuously
// speeding up pll_clk_out. When freq_step_ctr reaches zero, pll is
// producing its target frequency, and 'frequency is locked'.
// Note that freq_step_ctr loaded on assertion of pll_arst_l. This is
// to turn off freq_locked signal.
reg vco_pump_up ;
initial begin
freq_step_ctr = `FREQ_STEP_COUNT;
vco_pump_up = 1'b1 ;
#1
forever begin
@(pll_arst_l)
if ( pll_arst_l===0 ) begin
freq_step_ctr <= `FREQ_STEP_COUNT;
vco_pump_up = 1'b0 ;
end
else if ( pll_arst_l === 1 ) begin
#(`PLL_START_UP_DLY);
if( pll_arst_l === 1 ) // could be deasserted while waiting
vco_pump_up = 1'b1 ;
end
end
end
always @(posedge ref_clk) begin
if ( (freq_step_ctr>0) && (vco_pump_up==1'b1) )
freq_step_ctr <= freq_step_ctr-1;
end
assign freq_locked = (freq_step_ctr===0) ;
// vco_reg: is same as osc_out, subject to division by freq_step_ctr.
// -while pll_arst_l is asserted, vco_reg is low
// -after pll_arst_l is deasserted, vco_reg steps up to target
// frequency
initial begin
vco_reg = 1'b0;
vco_off = 1'b0;
end
always begin
if (pll_arst_l === 1'b0) begin
vco_reg = 1'b0;
vco_off = 1'b1;
@(posedge pll_arst_l) ;
vco_off = 0;
end
else if (vco_pump_up === 1'b0) begin
@(posedge vco_pump_up or negedge pll_arst_l) ;
end
else begin
repeat (freq_step_ctr+1) @(posedge osc_out) ;
vco_reg = ~vco_reg ;
end
end
// vco_out: This is vco_reg subject to shut off by phase locking logic
// as described below
assign vco_out = vco_reg & ~vco_off;
// phase_locking: this logic starts after frequency is locked.
// There are two components:
// -gross adjustement: the loop periodically shuts off pll output.
// This 'stretch' of pll_clk_out causes a stretch on feedback, and
// the edge of feedback gets closer to ref_clk. The proccess
// continues until feedback is within one PLL period of ref_clk.
// -fine adjustment: when feedback is within one PLL period of
// ref_clk, the delay between them is measured, and the value is
// injected in the osc_out path. This is done is four steps.
initial begin
phase_locked = 0;
edge_locked = 0;
end
always begin
if (pll_bypass===1'b1) begin
@(negedge pll_bypass);
end
else if (pll_arst_l===1'b0) begin
phase_locked = 0;
edge_locked = 0;
@(posedge pll_arst_l);
end
else if (freq_locked===1'b0) begin
@(posedge freq_locked)
#(`FEEDBACK_DLY_MAX) ;
end
else if (phase_locked===1'b0) begin
@(posedge feedback) beg_time = $time ;
@(posedge ref_clk) end_time = $time ;
if ((end_time-beg_time)<(4*fast_int_clk_width+fast_int_clk_residue)) begin
phase_locked= 1'b1 ;
end
else begin
// skip 1st osc pulse after next edge of ref_clk
@(ref_clk)
@(negedge vco_reg)
#1 // just past the edge
vco_off <= 1'b1;
@(vco_reg)
@(vco_reg)
#1 // just past the edge
vco_off <= 1'b0;
#(`FEEDBACK_DLY_MAX) ;
end
end
else if (edge_locked===1'b1) begin
@(negedge pll_arst_l) ;
end
else if ( osc_dly0_set === 1'b0 ) begin
osc_dly0 = (end_time-beg_time)/4;
osc_dly0_set = 1'b1 ;
#(`FEEDBACK_DLY_MAX) ;
end
else if ( osc_dly1_set === 1'b0 ) begin
osc_dly1 = (end_time-beg_time)/4;
osc_dly1_set = 1'b1 ;
#(`FEEDBACK_DLY_MAX) ;
end
else if ( osc_dly2_set === 1'b0 ) begin
osc_dly2 = (end_time-beg_time)/4;
osc_dly2_set = 1'b1 ;
#(`FEEDBACK_DLY_MAX) ;
end
else if ( osc_dly3_set === 1'b0 ) begin
osc_dly3 = (end_time-beg_time) - (osc_dly0+osc_dly1+osc_dly2) ;
osc_dly3_set = 1'b1 ;
#(`FEEDBACK_DLY_MAX) ;
end
else begin
edge_locked = 1;
end
end // always begin
//always @(negedge pll_arst_l) begin
// vco_off = 1;
// phase_locked = 0;
// @(posedge pll_arst_l)
// vco_off = 0;
// if (pll_bypass==1'b0) begin
// @(posedge freq_locked)
// #(`FEEDBACK_DLY_MAX) ;
// while (phase_locked==0) begin
// @(posedge feedback) beg_time = $time ;
// @(posedge ref_clk) end_time = $time ;
// if ((end_time-beg_time)>(4*fast_int_clk_width+fast_int_clk_residue)) begin
// // skip 1st osc pulse after next edge of ref_clk
// @(ref_clk)
// @(negedge vco_reg)
// #1 // just past the edge
// vco_off <= 1'b1;
// @(vco_reg)
// @(vco_reg)
// #1 // just past the edge
// vco_off <= 1'b0;
// #(`FEEDBACK_DLY_MAX) ;
// end
// else begin
// osc_dly0 = (end_time-beg_time)/4;
// #(`FEEDBACK_DLY_MAX) ;
// osc_dly1 = osc_dly0 ;
// #(`FEEDBACK_DLY_MAX) ;
// osc_dly2 = osc_dly0 ;
// #(`FEEDBACK_DLY_MAX) ;
// osc_dly3 = (end_time-beg_time) - (3*osc_dly0) ;
// #(`FEEDBACK_DLY_MAX) ;
// phase_locked = 1;
// end
// end // while (phase_locked==0)
// end // if (pll_bypass==1'b1)
//end
// phase match tracking: The following logic continuously compares the
// ref_clk and feedback, and keeps track of consecutive matches.
// 'pll_lock' requires the count to reach a certain threshold.
// Mismatch after pll_lock is considered an error.
initial begin
phase_match_ctr = 0;
sync_errors = 0;
end
always @(negedge pll_arst_l) begin
phase_match_ctr = 0;
sync_errors = 0;
end
always @(posedge ref_clk or posedge feedback) begin
#1 // to go past both edges, when they occur in coincidence
if ( ref_clk==feedback ) begin
phase_match_ctr <= phase_match_ctr+1;
end
else begin
// phase mismatch after pll-lock is recorded as error
if (pll_lock==1) sync_errors <= sync_errors+1;
phase_match_ctr <= 0;
end
end // always @ (ref_clk or feedback)
///////////////////////////////////////////////////////////////////
// error checkers for signals that should not be changing
// #10 delay allows for initialization at time 1 by environment
///////////////////////////////////////////////////////////////////
initial begin
#10 if ( vreg_seldb_l !== 1'b0 )
`ifdef MODELSIM
$display("bw_pll", "%m vreg_seldb_l not low at t=1\n" );
`else
$error("bw_pll", "%m vreg_seldb_l not low at t=1\n" );
`endif
forever begin @ ( vreg_seldb_l )
`ifdef MODELSIM
$display("bw_pll", "%m vreg_seldb_l changing during sim\n" );
`else
$error("bw_pll", "%m vreg_seldb_l changing during sim\n" );
`endif
end
end
initial begin
#10 if ( pll_clamp_fltr !== 1'b0 )
`ifdef MODELSIM
$display("bw_pll", "%m pll_clamp_fltr not low at t=1\n" );
`else
$error("bw_pll", "%m pll_clamp_fltr not low at t=1\n" );
`endif
forever begin @ ( pll_clamp_fltr )
`ifdef MODELSIM
$display("bw_pll", "%m pll_clamp_fltr changing during sim\n" );
`else
$error("bw_pll", "%m pll_clamp_fltr changing during sim\n" );
`endif
end
end
// initial begin
// #10 if ( testmode !== 1'b0 )
// $error("bw_pll", "%m testmode not low at t=1\n" );
//
// forever begin @ ( testmode )
// $error("bw_pll", "%m testmode changing during sim\n" );
// end
// end
initial begin
#10 if ( pll_div1 !== 6'b000000 )
`ifdef MODELSIM
$display("bw_pll", "%m pll_div1 not low at t=1\n" );
`else
$error("bw_pll", "%m pll_div1 not low at t=1\n" );
`endif
forever begin @ ( pll_div1 )
`ifdef MODELSIM
$display("bw_pll", "%m pll_div1 changing during sim\n" );
`else
$error("bw_pll", "%m pll_div1 changing during sim\n" );
`endif
end
end
initial begin
#10 if ( pll_div2 !== 6'b000000 )
`ifdef MODELSIM
$display("bw_pll", "%m pll_div2 not low at t=1\n" );
`else
$error("bw_pll", "%m pll_div2 not low at t=1\n" );
`endif
forever begin @ ( pll_div2 )
`ifdef MODELSIM
$display("bw_pll", "%m pll_div2 changing during sim\n" );
`else
$error("bw_pll", "%m pll_div2 changing during sim\n" );
`endif
end
end
initial begin
#10 if ( pll_div3 !== 6'b000000 )
`ifdef MODELSIM
$display("bw_pll", "%m pll_div3 not low at t=1\n" );
`else
$error("bw_pll", "%m pll_div3 not low at t=1\n" );
`endif
forever begin @ ( pll_div3 )
`ifdef MODELSIM
$display("bw_pll", "%m pll_div3 changing during sim\n" );
`else
$error("bw_pll", "%m pll_div3 changing during sim\n" );
`endif
end
end
//synopsys translate_on
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O21A_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__O21A_PP_BLACKBOX_V
/**
* o21a: 2-input OR into first input of 2-input AND.
*
* X = ((A1 | A2) & B1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__o21a (
X ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__O21A_PP_BLACKBOX_V
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:07:01 03/24/2015
// Design Name: hcsr04
// Module Name: /home/michael/Projects/mojo/ultrasonic-fountain/hcsr04_test.v
// Project Name: Mojo-Base
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: hcsr04
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module hcsr04_test;
// Inputs
reg rst;
reg clk;
reg measure;
reg echo;
// Outputs
wire [15:0] ticks;
wire valid;
wire trigger;
wire clk_10us;
clk_divider #(.DIV(500)) clk_10usmodule(
.rst(rst),
.clk(clk),
.div_clk(clk_10us)
);
// Instantiate the Unit Under Test (UUT)
hcsr04 #(
.TRIGGER_DURATION(1),
.MAX_COUNT(3800)
) uut (
.rst(rst),
.clk(clk),
.tclk(clk_10us),
.measure(measure),
.echo(echo),
.ticks(ticks),
.valid(valid),
.trigger(trigger)
);
initial begin
// Initialize Inputs
rst = 0;
clk = 0;
measure = 0;
echo = 0;
clk = 1'b0;
rst = 1'b1;
repeat(4) #10 clk = ~clk;
rst = 1'b0;
forever #10 clk = ~clk; // generate a clock
end
initial begin
measure = 0; // initial value
@(negedge rst); // wait for reset
measure = 1;
repeat(5000) @(posedge clk); //wait for trigger to finish, 10us
echo = 1;
repeat(100000) @(posedge clk); //echo for 10ms
echo = 0;
repeat (100000) @(posedge clk);
$finish;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__OR2_PP_SYMBOL_V
`define SKY130_FD_SC_HVL__OR2_PP_SYMBOL_V
/**
* or2: 2-input OR.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__or2 (
//# {{data|Data Signals}}
input A ,
input B ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__OR2_PP_SYMBOL_V
|
// system_mm_interconnect_1.v
// This file was auto-generated from altera_mm_interconnect_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 14.0 200 at 2015.05.05.08:40:20
`timescale 1 ps / 1 ps
module system_mm_interconnect_1 (
input wire acl_iface_kernel_clk_clk, // acl_iface_kernel_clk.clk
input wire cra_root_reset_reset_bridge_in_reset_reset, // cra_root_reset_reset_bridge_in_reset.reset
input wire [29:0] acl_iface_kernel_cra_address, // acl_iface_kernel_cra.address
output wire acl_iface_kernel_cra_waitrequest, // .waitrequest
input wire [0:0] acl_iface_kernel_cra_burstcount, // .burstcount
input wire [7:0] acl_iface_kernel_cra_byteenable, // .byteenable
input wire acl_iface_kernel_cra_read, // .read
output wire [63:0] acl_iface_kernel_cra_readdata, // .readdata
output wire acl_iface_kernel_cra_readdatavalid, // .readdatavalid
input wire acl_iface_kernel_cra_write, // .write
input wire [63:0] acl_iface_kernel_cra_writedata, // .writedata
input wire acl_iface_kernel_cra_debugaccess, // .debugaccess
output wire [3:0] cra_root_cra_slave_address, // cra_root_cra_slave.address
output wire cra_root_cra_slave_write, // .write
output wire cra_root_cra_slave_read, // .read
input wire [63:0] cra_root_cra_slave_readdata, // .readdata
output wire [63:0] cra_root_cra_slave_writedata, // .writedata
output wire [7:0] cra_root_cra_slave_byteenable, // .byteenable
input wire cra_root_cra_slave_readdatavalid, // .readdatavalid
input wire cra_root_cra_slave_waitrequest // .waitrequest
);
wire acl_iface_kernel_cra_translator_avalon_universal_master_0_waitrequest; // cra_root_cra_slave_translator:uav_waitrequest -> acl_iface_kernel_cra_translator:uav_waitrequest
wire [3:0] acl_iface_kernel_cra_translator_avalon_universal_master_0_burstcount; // acl_iface_kernel_cra_translator:uav_burstcount -> cra_root_cra_slave_translator:uav_burstcount
wire [63:0] acl_iface_kernel_cra_translator_avalon_universal_master_0_writedata; // acl_iface_kernel_cra_translator:uav_writedata -> cra_root_cra_slave_translator:uav_writedata
wire [29:0] acl_iface_kernel_cra_translator_avalon_universal_master_0_address; // acl_iface_kernel_cra_translator:uav_address -> cra_root_cra_slave_translator:uav_address
wire acl_iface_kernel_cra_translator_avalon_universal_master_0_lock; // acl_iface_kernel_cra_translator:uav_lock -> cra_root_cra_slave_translator:uav_lock
wire acl_iface_kernel_cra_translator_avalon_universal_master_0_write; // acl_iface_kernel_cra_translator:uav_write -> cra_root_cra_slave_translator:uav_write
wire acl_iface_kernel_cra_translator_avalon_universal_master_0_read; // acl_iface_kernel_cra_translator:uav_read -> cra_root_cra_slave_translator:uav_read
wire [63:0] acl_iface_kernel_cra_translator_avalon_universal_master_0_readdata; // cra_root_cra_slave_translator:uav_readdata -> acl_iface_kernel_cra_translator:uav_readdata
wire acl_iface_kernel_cra_translator_avalon_universal_master_0_debugaccess; // acl_iface_kernel_cra_translator:uav_debugaccess -> cra_root_cra_slave_translator:uav_debugaccess
wire [7:0] acl_iface_kernel_cra_translator_avalon_universal_master_0_byteenable; // acl_iface_kernel_cra_translator:uav_byteenable -> cra_root_cra_slave_translator:uav_byteenable
wire acl_iface_kernel_cra_translator_avalon_universal_master_0_readdatavalid; // cra_root_cra_slave_translator:uav_readdatavalid -> acl_iface_kernel_cra_translator:uav_readdatavalid
altera_merlin_master_translator #(
.AV_ADDRESS_W (30),
.AV_DATA_W (64),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (8),
.UAV_ADDRESS_W (30),
.UAV_BURSTCOUNT_W (4),
.USE_READ (1),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (1),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (8),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (0)
) acl_iface_kernel_cra_translator (
.clk (acl_iface_kernel_clk_clk), // clk.clk
.reset (cra_root_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (acl_iface_kernel_cra_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (acl_iface_kernel_cra_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (acl_iface_kernel_cra_translator_avalon_universal_master_0_read), // .read
.uav_write (acl_iface_kernel_cra_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (acl_iface_kernel_cra_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (acl_iface_kernel_cra_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (acl_iface_kernel_cra_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (acl_iface_kernel_cra_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (acl_iface_kernel_cra_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (acl_iface_kernel_cra_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (acl_iface_kernel_cra_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (acl_iface_kernel_cra_address), // avalon_anti_master_0.address
.av_waitrequest (acl_iface_kernel_cra_waitrequest), // .waitrequest
.av_burstcount (acl_iface_kernel_cra_burstcount), // .burstcount
.av_byteenable (acl_iface_kernel_cra_byteenable), // .byteenable
.av_read (acl_iface_kernel_cra_read), // .read
.av_readdata (acl_iface_kernel_cra_readdata), // .readdata
.av_readdatavalid (acl_iface_kernel_cra_readdatavalid), // .readdatavalid
.av_write (acl_iface_kernel_cra_write), // .write
.av_writedata (acl_iface_kernel_cra_writedata), // .writedata
.av_debugaccess (acl_iface_kernel_cra_debugaccess), // .debugaccess
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_lock (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponserequest (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponserequest (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (4),
.AV_DATA_W (64),
.UAV_DATA_W (64),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (8),
.UAV_BYTEENABLE_W (8),
.UAV_ADDRESS_W (30),
.UAV_BURSTCOUNT_W (4),
.AV_READLATENCY (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (8),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) cra_root_cra_slave_translator (
.clk (acl_iface_kernel_clk_clk), // clk.clk
.reset (cra_root_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (acl_iface_kernel_cra_translator_avalon_universal_master_0_address), // avalon_universal_slave_0.address
.uav_burstcount (acl_iface_kernel_cra_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (acl_iface_kernel_cra_translator_avalon_universal_master_0_read), // .read
.uav_write (acl_iface_kernel_cra_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (acl_iface_kernel_cra_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (acl_iface_kernel_cra_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (acl_iface_kernel_cra_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (acl_iface_kernel_cra_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (acl_iface_kernel_cra_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (acl_iface_kernel_cra_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (acl_iface_kernel_cra_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (cra_root_cra_slave_address), // avalon_anti_slave_0.address
.av_write (cra_root_cra_slave_write), // .write
.av_read (cra_root_cra_slave_read), // .read
.av_readdata (cra_root_cra_slave_readdata), // .readdata
.av_writedata (cra_root_cra_slave_writedata), // .writedata
.av_byteenable (cra_root_cra_slave_byteenable), // .byteenable
.av_readdatavalid (cra_root_cra_slave_readdatavalid), // .readdatavalid
.av_waitrequest (cra_root_cra_slave_waitrequest), // .waitrequest
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
module user_logic (
dac_clk_in_p,
dac_clk_in_n,
dac_clk_out_p,
dac_clk_out_n,
dac_data_out_a_p,
dac_data_out_a_n,
dac_data_out_b_p,
dac_data_out_b_n,
vdma_clk,
vdma_valid,
vdma_data,
vdma_ready,
up_status,
vdma_dbg_data,
vdma_dbg_trigger,
dac_div3_clk,
dac_dbg_data,
dac_dbg_trigger,
delay_clk,
Bus2IP_Clk,
Bus2IP_Resetn,
Bus2IP_Data,
Bus2IP_BE,
Bus2IP_RdCE,
Bus2IP_WrCE,
IP2Bus_Data,
IP2Bus_RdAck,
IP2Bus_WrAck,
IP2Bus_Error);
parameter C_NUM_REG = 32;
parameter C_SLV_DWIDTH = 32;
input dac_clk_in_p;
input dac_clk_in_n;
output dac_clk_out_p;
output dac_clk_out_n;
output [13:0] dac_data_out_a_p;
output [13:0] dac_data_out_a_n;
output [13:0] dac_data_out_b_p;
output [13:0] dac_data_out_b_n;
input vdma_clk;
input vdma_valid;
input [63:0] vdma_data;
output vdma_ready;
output [ 7:0] up_status;
output [198:0] vdma_dbg_data;
output [ 7:0] vdma_dbg_trigger;
output dac_div3_clk;
output [292:0] dac_dbg_data;
output [ 7:0] dac_dbg_trigger;
input delay_clk;
input Bus2IP_Clk;
input Bus2IP_Resetn;
input [31:0] Bus2IP_Data;
input [ 3:0] Bus2IP_BE;
input [31:0] Bus2IP_RdCE;
input [31:0] Bus2IP_WrCE;
output [31:0] IP2Bus_Data;
output IP2Bus_RdAck;
output IP2Bus_WrAck;
output IP2Bus_Error;
reg up_sel;
reg up_rwn;
reg [ 4:0] up_addr;
reg [31:0] up_wdata;
reg IP2Bus_RdAck;
reg IP2Bus_WrAck;
reg [31:0] IP2Bus_Data;
reg IP2Bus_Error;
wire [31:0] up_rwce_s;
wire [31:0] up_rdata_s;
wire up_ack_s;
assign up_rwce_s = (Bus2IP_RdCE == 0) ? Bus2IP_WrCE : Bus2IP_RdCE;
always @(negedge Bus2IP_Resetn or posedge Bus2IP_Clk) begin
if (Bus2IP_Resetn == 0) begin
up_sel <= 'd0;
up_rwn <= 'd0;
up_addr <= 'd0;
up_wdata <= 'd0;
end else begin
up_sel <= (up_rwce_s == 0) ? 1'b0 : 1'b1;
up_rwn <= (Bus2IP_RdCE == 0) ? 1'b0 : 1'b1;
case (up_rwce_s)
32'h80000000: up_addr <= 5'h00;
32'h40000000: up_addr <= 5'h01;
32'h20000000: up_addr <= 5'h02;
32'h10000000: up_addr <= 5'h03;
32'h08000000: up_addr <= 5'h04;
32'h04000000: up_addr <= 5'h05;
32'h02000000: up_addr <= 5'h06;
32'h01000000: up_addr <= 5'h07;
32'h00800000: up_addr <= 5'h08;
32'h00400000: up_addr <= 5'h09;
32'h00200000: up_addr <= 5'h0a;
32'h00100000: up_addr <= 5'h0b;
32'h00080000: up_addr <= 5'h0c;
32'h00040000: up_addr <= 5'h0d;
32'h00020000: up_addr <= 5'h0e;
32'h00010000: up_addr <= 5'h0f;
32'h00008000: up_addr <= 5'h10;
32'h00004000: up_addr <= 5'h11;
32'h00002000: up_addr <= 5'h12;
32'h00001000: up_addr <= 5'h13;
32'h00000800: up_addr <= 5'h14;
32'h00000400: up_addr <= 5'h15;
32'h00000200: up_addr <= 5'h16;
32'h00000100: up_addr <= 5'h17;
32'h00000080: up_addr <= 5'h18;
32'h00000040: up_addr <= 5'h19;
32'h00000020: up_addr <= 5'h1a;
32'h00000010: up_addr <= 5'h1b;
32'h00000008: up_addr <= 5'h1c;
32'h00000004: up_addr <= 5'h1d;
32'h00000002: up_addr <= 5'h1e;
32'h00000001: up_addr <= 5'h1f;
default: up_addr <= 5'h1f;
endcase
up_wdata <= Bus2IP_Data;
end
end
always @(negedge Bus2IP_Resetn or posedge Bus2IP_Clk) begin
if (Bus2IP_Resetn == 0) begin
IP2Bus_RdAck <= 'd0;
IP2Bus_WrAck <= 'd0;
IP2Bus_Data <= 'd0;
IP2Bus_Error <= 'd0;
end else begin
IP2Bus_RdAck <= (Bus2IP_RdCE == 0) ? 1'b0 : up_ack_s;
IP2Bus_WrAck <= (Bus2IP_WrCE == 0) ? 1'b0 : up_ack_s;
IP2Bus_Data <= up_rdata_s;
IP2Bus_Error <= 'd0;
end
end
cf_dac_1c_2p i_dac_1c_2p (
.dac_clk_in_p (dac_clk_in_p),
.dac_clk_in_n (dac_clk_in_n),
.dac_clk_out_p (dac_clk_out_p),
.dac_clk_out_n (dac_clk_out_n),
.dac_data_out_a_p (dac_data_out_a_p),
.dac_data_out_a_n (dac_data_out_a_n),
.dac_data_out_b_p (dac_data_out_b_p),
.dac_data_out_b_n (dac_data_out_b_n),
.vdma_clk (vdma_clk),
.vdma_valid (vdma_valid),
.vdma_data (vdma_data),
.vdma_ready (vdma_ready),
.up_rstn (Bus2IP_Resetn),
.up_clk (Bus2IP_Clk),
.up_sel (up_sel),
.up_rwn (up_rwn),
.up_addr (up_addr),
.up_wdata (up_wdata),
.up_rdata (up_rdata_s),
.up_ack (up_ack_s),
.up_status (up_status),
.vdma_dbg_data (vdma_dbg_data),
.vdma_dbg_trigger (vdma_dbg_trigger),
.dac_div3_clk (dac_div3_clk),
.dac_dbg_data (dac_dbg_data),
.dac_dbg_trigger (dac_dbg_trigger),
.delay_clk (delay_clk));
endmodule
// ***************************************************************************
// ***************************************************************************
|
//`#start header` -- edit after this line, do not edit this line
// ========================================
// Copyright 2013 David Turnbull AE9RB
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
// ========================================
`include "cypress.v"
//`#end` -- edit above this line, do not edit this line
// Generated on 03/11/2013 at 13:09
// Component: FracN
module FracN (
input clk
);
//`#start body` -- edit after this line, do not edit this line
// Special thanks to Michael Hightower KF6SJ for showing me how
// to create a Fractional-N Sigma Delta Modulator in the PSoC.
// This version is simpified to reduce PLA usage.
// A more complete implementation is available from:
// http://www.simplecircuits.com/SimpleSDR.html
wire [7:0] fHigh;
wire [7:0] fLow;
wire [13:0] frac = {fHigh [5:0], fLow [7:0]};
reg [13:0] acc1;
reg [13:0] acc2;
wire [14:0] adder1 = acc1 + frac;
wire [14:0] adder2 = acc2 + acc1;
reg minus1;
reg [6:0] pOut;
cy_psoc3_control #(.cy_init_value (8'h3D), .cy_force_order(`TRUE))
FRAC_HI ( .control(fHigh));
cy_psoc3_control #(.cy_init_value (8'hF4), .cy_force_order(`TRUE))
FRAC_LO ( .control(fLow));
cy_psoc3_status #(.cy_md_select(8'h00), .cy_force_order(`TRUE))
PLL_P ( .status( {1'b0, pOut} ));
always @(posedge clk)
begin
acc1 <= adder1 [13:0];
acc2 <= adder2 [13:0];
minus1 <= adder2 [14];
pOut <= 8'h13 + {6'b0, adder1 [14]} + {6'b0, adder2 [14]} + {7{minus1}};
end
//`#end` -- edit above this line, do not edit this line
endmodule
//`#start footer` -- edit after this line, do not edit this line
//`#end` -- edit above this line, do not edit this line
|
module lca_processor(clk,reset);
input clk,reset;
wire [15:0] new_IR_multi, pr2_IR ,pr3_IR ,pr4_IR, pr5_IR, fromPipe2_PCim, fromPipe2_970, fromPipe3RFOut,
fromPipe3PCInc, fromPipe4_Aluout, fromPipe5Mem, to_pr1_PC, to_pr1_IR, to_pr1_PCInc, pr1_PC,
to_pr2_PCImmInc, pr1_PCInc, pr1_IR, to_pr2_SImm6, to_pr2_Imm970, pr2_PCInc, pr2_PC, pr2_PCImmInc,
pr2_SImm6, pr2_Imm970, writeData, regValue1, regValue2, writeR7Data, pr3_Imm970s, pr3_PCImmInc,
pr3_PCInc, pr3_RFOut1, pr3_RFOut2, pr3_SImm6, ALUOut, RAFromPipeInc, RAOut, pr4_ALUOut, pr5_ALUOut,
pr5_MemData, pr4_PCImmInc, pr4_Imm970s, pr5_Imm970s, pr5_PCInc, pr4_PCInc, pr4_RFOut1, pr4_RFOut2,
pr4_RAOut, MemData, pr5_PCImmInc;
wire [5:0] mem_wb_op,ex_mem_op,regread_ex_op;
wire [2:0] to_pr2_rA1, to_pr2_rA2, to_pr2_WriteAdd, to_pr2_MregWB, pr2_rA1, pr2_rA2, pr2_WriteAdd, pr5_WriteAdd,
pr3_WriteAdd, pr4_WriteAdd;
wire [1:0] to_pr2_Mr7WB, pr2_Mr7WB, pr3_RegWriteSelect, pr3_R7WriteSelect, CCRWriteValue, pr5_CCR, CCR, pr4_CCR,
pr4_RegWriteSelect, pr4_R7WriteSelect, pr5_RegWriteSelect, pr5_R7WriteSelect;
wire IR_load_mux, equalValue, pc_write, to_pr1_first_multiple, pr1_first_multiple, flush_if_id,
to_pr2_Memdata, to_pr2_Mex1, to_pr2_Mex2, to_pr2_WriteMem, to_pr2_alu_ctrl, to_pr2_MmemR,
to_pr2_MmemW, pr2_Mex1, pr2_Mex2, pr2_Mmemdata, pr2_MmemR, pr2_MmemW, pr2_MregWB, pr2_first_multiple,
pr2_WriteMem, pr2_alu_ctrl, flush_id_reg, pr5_WriteRF, pr5_WriteR7, flush_reg_ex, pr3_alu_ctrl,
pr3_WriteRF, pr3_WriteMem, pr3_Equ, pr3_Mmemdata, pr3_MmemR, pr3_MmemW, pr3_first_multiple, pr3_Mex1,
pr3_Mex2, CCRWrite, pr5_CCR_Write, r7_write, rf_write, pr4_CCRWrite, pr4_rf_write, pr4_r7_write,
pr4_WriteMem, pr4_MmemR, pr4_MmemW, pr4_Mmemdata;
assign mem_wb_op = {pr5_IR[15:12],pr5_IR[1:0]};
assign ex_mem_op = {pr4_IR[15:12],pr4_IR[1:0]};
assign regread_ex_op = {pr3_IR[15:12],pr3_IR[1:0]};
fetch stage1(.IR_load_mux(IR_load_mux),.new_IR_multi(new_IR_multi), .equ(equalValue), .pr2_IR(pr2_IR) ,
.pr3_IR(pr3_IR) , .pr4_IR(pr4_IR), .pr5_IR(pr5_IR), .fromPipe2_PCim(fromPipe2_PCim),
.fromPipe2_970(fromPipe2_970), .fromPipe3RFOut(fromPipe3RFOut), .fromPipe3PCInc(fromPipe3PCInc),
.fromPipe4_Aluout(fromPipe4_Aluout), .fromPipe5Mem(fromPipe5Mem), .PCWrite(pc_write),
.PCOut(to_pr1_PC), .IROut(to_pr1_IR), .incPCOut(to_pr1_PCInc), .clk(clk), .reset(reset));
pipeline_reg1 p1(.clk(clk), .reset(reset), .toPCInc(to_pr1_PCInc), .toPC(to_pr1_PC), .toIR(to_pr1_IR),
.PCInc(pr1_PCInc), .PC(pr1_PC), .IR(pr1_IR), .tofirst_multiple(to_pr1_first_multiple),
.first_multiple(pr1_first_multiple),.flush(flush_if_id));
decode stage2(.MmemData(to_pr2_Memdata), .fromPipe1PC(pr1_PC), .IR(pr1_IR), .PC_Imm(to_pr2_PCImmInc),
.rA1(to_pr2_rA1), .rA2(to_pr2_rA2), .wA(to_pr2_WriteAdd), .Sext_Imm6(to_pr2_SImm6),
.Imm970(to_pr2_Imm970), .Mex1(to_pr2_Mex1), .Mex2(to_pr2_Mex2), .wMem(to_pr2_WriteMem),
.alu_ctrl(to_pr2_alu_ctrl), .MregWB(to_pr2_MregWB), .MmemR(to_pr2_MmemR), .MmemW(to_pr2_MmemW),
.Mr7WB(to_pr2_Mr7WB));
pipeline_reg2 p2(.clk(clk), .reset(reset),.toMex1(to_pr2_Mex1),.Mex1(pr2_Mex1),.toMex2(to_pr2_Mex2),
.Mex2(pr2_Mex2),.toMmemData(to_pr2_Memdata),.MmemData(pr2_Mmemdata),.toMmemR(to_pr2_MmemR),
.MmemR(pr2_MmemR),.toMmemW(to_pr2_MmemW),.MmemW(pr2_MmemW),.toMregWB(to_pr2_MregWB),
.MregWB(pr2_MregWB), .toMr7WB(to_pr2_Mr7WB), .Mr7WB(pr2_Mr7WB), .toPCInc(pr1_PCInc),
.PCInc(pr2_PCInc), .toPC(pr1_PC), .PC(pr2_PC), .toIR(pr1_IR),.IR(pr2_IR),
.tofirst_multiple(pr1_first_multiple), .first_multiple(pr2_first_multiple),
.toPCImmInc(to_pr2_PCImmInc), .PCImmInc(pr2_PCImmInc), .toWriteMem(to_pr2_WriteMem),
.WriteMem(pr2_WriteMem), .torA1(to_pr2_rA1), .rA1(pr2_rA1), .torA2(to_pr2_rA2),.rA2(pr2_rA2),
.toWriteAdd(to_pr2_WriteAdd), .WriteAdd(pr2_WriteAdd), .toSImm6(to_pr2_SImm6),.SImm6(pr2_SImm6),
.toImm970s(to_pr2_Imm970),.Imm970s(pr2_Imm970),.toalu_ctrl(to_pr2_alu_ctrl),
.alu_ctrl(pr2_alu_ctrl), .flush(flush_id_reg));
//from wb
reg_read stage3(.in(writeData),.readAdd1(pr2_rA1),.readAdd2(pr2_rA2),.regValue1(regValue1),.regValue2(regValue2),
.equalValue(equalValue), .write(pr5_WriteRF), .writeAdd(pr5_WriteAdd), .writeR7(pr5_WriteR7),
.inR7(writeR7Data), .clk(clk), .reset(reset));
pipeline_reg3 p3(.flush(flush_reg_ex),.clk(clk),.reset(reset),.toalu_ctrl(pr2_alu_ctrl),.alu_ctrl(pr3_alu_ctrl),
.toImm970s(pr2_Imm970),.toPCImmInc(pr2_PCImmInc),.toPCInc(pr2_PCInc),.toWriteAdd(pr2_WriteAdd),
.toRegWriteSelect(pr2_MregWB),.toR7WriteSelect(pr2_Mr7WB),.toWriteMem(pr2_WriteMem),
.toRFOut1(regValue1),.toRFOut2(regValue2),.toEqu(equalValue),.toSImm6(pr2_SImm6),.toIR(pr2_IR),
.Imm970s(pr3_Imm970s), .PCImmInc(pr3_PCImmInc), .PCInc(pr3_PCInc),
.WriteAdd(pr3_WriteAdd), .RegWriteSelect(pr3_RegWriteSelect),
.R7WriteSelect(pr3_R7WriteSelect),.WriteMem(pr3_WriteMem),.RFOut1(pr3_RFOut1),.RFOut2(pr3_RFOut2),
.Equ(pr3_Equ), .SImm6(pr3_SImm6), .IR(pr3_IR),.MemdataSelectInput(pr3_Mmemdata),
.toMemdataSelectInput(pr2_Mmemdata), .RAMemSelectInput(pr3_MmemR),.toRAMemSelectInput(pr2_MmemR),
.WAMemSelectInput(pr3_MmemW),.toWAMemSelectInput(pr2_MmemW),.tofirst_multiple(pr2_first_multiple),
.first_multiple(pr3_first_multiple),.Mex1(pr3_Mex1), .toMex1(pr2_Mex1), .Mex2(pr3_Mex2),
.toMex2(pr2_Mex2));
//
execute stage4(.clk(clk), .reset(reset), .ALUOut(ALUOut), .ALUOp(pr3_alu_ctrl),.fromPlusOneMem(RAFromPipeInc),
.fromRFOut1(pr3_RFOut1), .fromRFOut2(pr3_RFOut2), .RASelectInput(pr3_first_multiple),
.CCRWrite(CCRWrite), .CCR_Write_from_wb(pr5_CCR_Write),.CCRWriteValue(CCRWriteValue),
.CCRWriteValue_from_wb(pr5_CCR), .fromSImm6(pr3_SImm6), .ExMux1Select(pr3_Mex1),
.ExMux2Select(pr3_Mex2), .RAOut(RAOut), .CCR(CCR), .IR(pr3_IR), .SignalA(pr4_ALUOut),
.SignalB(pr5_ALUOut), .SignalC(pr5_MemData), .SignalG(pr4_PCImmInc), .SignalI(pr4_Imm970s),
.SignalJ(pr5_Imm970s), .SignalK(pr5_PCInc), .SignalX(pr4_CCR), .SignalY(pr5_CCR),
.mem_wb_op(mem_wb_op), .mem_wb_regA(pr5_IR[11:9]),.mem_wb_regB(pr5_IR[8:6]),
.mem_wb_regC(pr5_IR[5:3]), .ex_mem_op(ex_mem_op),.ex_mem_regA(pr4_IR[11:9]),
.ex_mem_regB(pr4_IR[8:6]),.ex_mem_regC(pr4_IR[5:3]),.regread_ex_op(regread_ex_op),
.regread_ex_regA(pr3_IR[11:9]),.regread_ex_regB(pr3_IR[8:6]),.regread_ex_regC(pr3_IR[5:3]),
.ex_mem_CCR_write(pr4_CCRWrite),.r7(r7_write),.rf(rf_write));
pipeline_reg4 pr4(.clk(clk), .reset(reset), .toCCR(CCR), .toCCRWrite(CCRWrite), .toWriteRF(rf_write),
.toImm970s(pr3_Imm970s), .toPCImmInc(pr3_PCImmInc), .toALUOut(ALUOut), .toPCInc(pr3_PCInc),
.toWriteAdd(pr3_WriteAdd), .toWriteR7(r7_write), .toRegWriteSelect(pr3_RegWriteSelect),
.toR7WriteSelect(pr3_R7WriteSelect), .toWriteMem(pr3_WriteMem), .toRFOut1(pr3_RFOut1),
.toRFOut2(pr3_RFOut2), .toRAOut(RAOut), .CCR(pr4_CCR), .CCRWrite(pr4_CCRWrite),
.WriteRF(pr4_rf_write), .Imm970s(pr4_Imm970s), .PCImmInc(pr4_PCImmInc), .ALUOut(pr4_ALUOut),
.PCInc(pr4_PCInc), .WriteAdd(pr4_WriteAdd), .WriteR7(pr4_r7_write),
.RegWriteSelect(pr4_RegWriteSelect), .R7WriteSelect(pr4_R7WriteSelect),.WriteMem(pr4_WriteMem),
.RFOut1(pr4_RFOut1), .RFOut2(pr4_RFOut2), .RAOut(pr4_RAOut), .toIR(pr3_IR), .IR(pr4_IR),
.RAMemSelectInput(pr4_MmemR),.toRAMemSelectInput(pr3_MmemR), .WAMemSelectInput(pr4_MmemW),
.toWAMemSelectInput(pr3_MmemW),.MemdataSelectInput(pr4_Mmemdata),
.toMemdataSelectInput(pr3_Mmemdata));
mem_access stage5(.IRfrompipe4(pr4_IR), .IRfrompipe5(pr5_IR), .RAFromPipe(pr4_RAOut), .ALUOut(pr4_ALUOut),
.RAMemSelectInput(pr4_MmemR), .WAMemSelectInput(pr4_MmemW), .MemData(MemData),
.DataInSelect(pr4_Mmemdata), .WriteMem(pr4_WriteMem), .RAFromPipeInc(RAFromPipeInc),
.SignalC(pr5_MemData),.Rfout1(pr4_RFOut1),.Rfout2(pr4_RFOut2),.mem_wb_CCR_write(pr5_CCR_Write),
.ex_mem_CCR_write(pr4_CCRWrite));
pipeline_reg5 pr5(.clk(clk),.reset(reset),.toCCR(pr4_CCR),.toCCRWrite(pr4_CCRWrite),.toMemData(MemData),
.toWriteRF(pr4_rf_write),.toImm970s(pr4_Imm970s),.toPCImmInc(pr4_PCImmInc),.toALUOut(pr4_ALUOut),
.toPCInc(pr4_PCInc),.toWriteAdd(pr4_WriteAdd), .toWriteR7(pr4_r7_write),
.toRegWriteSelect(pr4_RegWriteSelect),.toR7WriteSelect(pr4_R7WriteSelect),.CCR(pr5_CCR),
.CCRWrite(pr5_CCR_Write), .MemData(pr5_MemData), .WriteRF(pr5_WriteRF), .Imm970s(pr5_Imm970s),
.PCImmInc(pr5_PCImmInc), .ALUOut(pr5_ALUOut), .PCInc(pr5_PCInc),.WriteAdd(pr5_WriteAdd),
.WriteR7(pr5_WriteR7), .RegWriteSelect(pr5_RegWriteSelect),.R7WriteSelect(pr5_R7WriteSelect),
.toIR(pr4_IR), .IR(pr5_IR));
write_back stage6(.clk(clk), .reset(clk), .Imm970(pr5_Imm970s), .MemData(pr5_MemData), .PCImmInc(pr5_PCImmInc), .ALUOut(pr5_ALUOut), .PCInc(pr5_PCInc)
, .regSelect(pr5_RegWriteSelect), .r7Select(pr5_R7WriteSelect), .writeData(writeData), .writeR7Data(writeData));
hazard_detection hdu(.IR_load_mux(IR_load_mux),.new_IR_multi(new_IR_multi),.first_multiple(to_pr1_first_multiple),.clk(clk),.flush_reg_ex(flush_reg_ex),
.flush_id_reg(flush_id_reg), .flush_if_id(flush_if_id) ,.pr1_IR(pr1_IR), .pr1_pc(pr1_PC), .pr2_IR(pr2_IR), .pr2_pc(pr2_IR),.pr3_IR(pr3_IR), .pr4_IR(pr4_IR)
, .pc_write(pc_write),.equ(pr3_Equ));
endmodule
//pipeline register modules
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
// Date : Mon Apr 03 17:46:36 2017
// Host : LAPTOP-IQ9G3D1I running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/Users/andrewandre/Documents/GitHub/axiplasma/hdl/projects/VC707/bd/mig_wrap/ip/mig_wrap_mig_7series_0_0/mig_wrap_mig_7series_0_0_stub.v
// Design : mig_wrap_mig_7series_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7vx485tffg1761-2
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
module mig_wrap_mig_7series_0_0(ddr3_dq, ddr3_dqs_n, ddr3_dqs_p, ddr3_addr,
ddr3_ba, ddr3_ras_n, ddr3_cas_n, ddr3_we_n, ddr3_reset_n, ddr3_ck_p, ddr3_ck_n, ddr3_cke,
ddr3_cs_n, ddr3_dm, ddr3_odt, sys_clk_p, sys_clk_n, ui_clk, ui_clk_sync_rst, ui_addn_clk_0,
ui_addn_clk_1, ui_addn_clk_2, ui_addn_clk_3, ui_addn_clk_4, mmcm_locked, aresetn,
app_sr_active, app_ref_ack, app_zq_ack, s_axi_awid, s_axi_awaddr, s_axi_awlen, s_axi_awsize,
s_axi_awburst, s_axi_awlock, s_axi_awcache, s_axi_awprot, s_axi_awqos, s_axi_awvalid,
s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wlast, s_axi_wvalid, s_axi_wready,
s_axi_bready, s_axi_bid, s_axi_bresp, s_axi_bvalid, s_axi_arid, s_axi_araddr, s_axi_arlen,
s_axi_arsize, s_axi_arburst, s_axi_arlock, s_axi_arcache, s_axi_arprot, s_axi_arqos,
s_axi_arvalid, s_axi_arready, s_axi_rready, s_axi_rid, s_axi_rdata, s_axi_rresp, s_axi_rlast,
s_axi_rvalid, init_calib_complete, device_temp, sys_rst)
/* synthesis syn_black_box black_box_pad_pin="ddr3_dq[63:0],ddr3_dqs_n[7:0],ddr3_dqs_p[7:0],ddr3_addr[13:0],ddr3_ba[2:0],ddr3_ras_n,ddr3_cas_n,ddr3_we_n,ddr3_reset_n,ddr3_ck_p[0:0],ddr3_ck_n[0:0],ddr3_cke[0:0],ddr3_cs_n[0:0],ddr3_dm[7:0],ddr3_odt[0:0],sys_clk_p,sys_clk_n,ui_clk,ui_clk_sync_rst,ui_addn_clk_0,ui_addn_clk_1,ui_addn_clk_2,ui_addn_clk_3,ui_addn_clk_4,mmcm_locked,aresetn,app_sr_active,app_ref_ack,app_zq_ack,s_axi_awid[3:0],s_axi_awaddr[29:0],s_axi_awlen[7:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[0:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awqos[3:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[511:0],s_axi_wstrb[63:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bready,s_axi_bid[3:0],s_axi_bresp[1:0],s_axi_bvalid,s_axi_arid[3:0],s_axi_araddr[29:0],s_axi_arlen[7:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[0:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arqos[3:0],s_axi_arvalid,s_axi_arready,s_axi_rready,s_axi_rid[3:0],s_axi_rdata[511:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,init_calib_complete,device_temp[11:0],sys_rst" */;
inout [63:0]ddr3_dq;
inout [7:0]ddr3_dqs_n;
inout [7:0]ddr3_dqs_p;
output [13:0]ddr3_addr;
output [2:0]ddr3_ba;
output ddr3_ras_n;
output ddr3_cas_n;
output ddr3_we_n;
output ddr3_reset_n;
output [0:0]ddr3_ck_p;
output [0:0]ddr3_ck_n;
output [0:0]ddr3_cke;
output [0:0]ddr3_cs_n;
output [7:0]ddr3_dm;
output [0:0]ddr3_odt;
input sys_clk_p;
input sys_clk_n;
output ui_clk;
output ui_clk_sync_rst;
output ui_addn_clk_0;
output ui_addn_clk_1;
output ui_addn_clk_2;
output ui_addn_clk_3;
output ui_addn_clk_4;
output mmcm_locked;
input aresetn;
output app_sr_active;
output app_ref_ack;
output app_zq_ack;
input [3:0]s_axi_awid;
input [29:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [0:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awqos;
input s_axi_awvalid;
output s_axi_awready;
input [511:0]s_axi_wdata;
input [63:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
input s_axi_bready;
output [3:0]s_axi_bid;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input [3:0]s_axi_arid;
input [29:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [0:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arqos;
input s_axi_arvalid;
output s_axi_arready;
input s_axi_rready;
output [3:0]s_axi_rid;
output [511:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
output init_calib_complete;
output [11:0]device_temp;
input sys_rst;
endmodule
|
/*
* blockram_spool.v - Spools data to the processor from block ram
*
* Used to spool data to/from the SD Card buffer. Expects the block ram to be 8-bit
* Only one clock domain allowed
*
* Registers:
*
* 0 - Set/Get A(low)
* 1 - Set/Get A(high)
* 8 - Read/Write Data
* 15 - Operation Request/Status
* Bit 0 - Initiate Read Process / Read Processor Ready for spool
* Bit 1 - Initiate Write Process / Write Processor Ready for spool
* Bit 7 - Terminate read/write
*
* Part of the CPC2 project: http://intelligenttoasters.blog
*
* Copyright (C)2017 [email protected]
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, you can find a copy here:
* https://www.gnu.org/licenses/gpl-3.0.en.html
*
*/
`timescale 1ns/1ns
`default_nettype none
module blockram_spool (
// System signals
input wire clk_i,
input wire areset_i,
// Blockram Interface
output reg [15:0] address_o,
output reg [7:0] data_o,
input wire [7:0] q_i,
output reg wren_o,
// CPC Interface
input wire [3:0] A_i,
input wire [7:0] D_i,
output reg [7:0] D_o,
input wire rd_i,
input wire wr_i
);
parameter IDLE = 4'd0,
PRE_READ = 4'd1, READ_READY = 4'd2, READ_CAPTURE = 4'd4, WAIT_READ = 4'd5,
WRITE_WAIT = 4'd6, WRITE_NEXT = 4'd7;
// Wire definitions ===========================================================================
wire rd_sig, wr_sig, abort_sig;
wire read_trigger, write_trigger;
// Registers ==================================================================================
reg [15:0] A;
reg cpu_rd, cpu_wr, fsm_rd, fsm_wr, cpu_abort, fsm_abort;
reg [3:0] state;
reg [7:0] rd_buffer;
// Assignments ================================================================================
assign rd_sig = (cpu_rd != fsm_rd);
assign wr_sig = (cpu_wr != fsm_wr);
assign abort_sig = (cpu_abort != fsm_abort);
assign read_trigger = (A_i == 4'd8) && rd_i;
assign write_trigger = (A_i == 4'd8) && wr_i;
// Module connections =========================================================================
// Simulation branches and control ============================================================
// Core logic ================================================================================
always @(posedge clk_i or posedge areset_i)
if( areset_i )
begin
D_o <= 8'd0;
cpu_rd <= 1'b0;
cpu_wr <= 1'b0;
cpu_abort <= 1'b0;
end else if( rd_i | wr_i ) begin // Only do something if signalled
case(A_i)
4'd0: begin
if( wr_i ) A[7:0] <= D_i; else D_o <= A[7:0];
end
4'd1: begin
if( wr_i ) A[15:8] <= D_i; else D_o <= A[15:8];
end
4'd8: begin
if( rd_i ) D_o <= rd_buffer;
end
4'd15: begin
if( wr_i ) begin
if( D_i[0] ) if( ~rd_sig) cpu_rd <= ~cpu_rd;
if( D_i[1] ) if( ~wr_sig) cpu_wr <= ~cpu_wr;
if( D_i[7] ) if( ~abort_sig ) cpu_abort <= ~cpu_abort;
end else begin
D_o <= {8'b0};
end
end
endcase
end
// FSM to read/write block ram
always @(posedge clk_i or posedge areset_i)
if( areset_i )
begin
fsm_rd <= 1'b0;
fsm_wr <= 1'b0;
fsm_abort <= 1'b0;
address_o <= 16'd0;
data_o <= 8'd0;
wren_o <= 1'b0;
state <= IDLE;
end else begin
case( state )
// Waiting for instructions
IDLE: begin
address_o <= A;
if( rd_sig )
begin
fsm_rd <= ~fsm_rd;
state <= PRE_READ;
end else if( wr_sig )
begin
data_o <= D_i; // Capture first case
fsm_wr <= ~fsm_wr;
state <= WRITE_WAIT;
end
end
// Read states
PRE_READ: begin
state <= READ_READY;
end
READ_READY: begin
address_o <= address_o + 1'b1;
state <= READ_CAPTURE;
end
READ_CAPTURE: begin
rd_buffer <= q_i;
state <= WAIT_READ;
end
WAIT_READ: begin
if( abort_sig )
begin
state <= IDLE;
fsm_abort <= ~fsm_abort;
end else
if( (A_i == 4'd8) && rd_i ) state <= READ_READY;
end
// Write states
WRITE_WAIT: begin
if( abort_sig )
begin
state <= IDLE;
fsm_abort <= ~fsm_abort;
end else
if( write_trigger ) begin
wren_o <= 1'b1;
state <= WRITE_NEXT;
end
data_o <= D_i;
end
WRITE_NEXT: begin
address_o <= address_o + 1'b1;
wren_o <= 1'b0;
state <= WRITE_WAIT;
end
endcase
end
endmodule
|
// file: clk_wiz_0.v
//
// (c) Copyright 2008 - 2015 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// CLK_OUT1___250.000______0.000______50.0_______93.990_____89.971
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
//----------------------------------------------------------------------------
// __primary_____________200____________0.010
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "clk_wiz_0,clk_wiz_v5_1,{component_name=clk_wiz_0,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=PLL,num_out_clk=1,clkin1_period=5.0,clkin2_period=10.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
module clk_wiz_0
(
// Clock in ports
input clk_in1_p,
input clk_in1_n,
// Clock out ports
output clk_out1,
// Status and control signals
input reset,
output locked
);
clk_wiz_0_clk_wiz inst
(
// Clock in ports
.clk_in1_p(clk_in1_p),
.clk_in1_n(clk_in1_n),
// Clock out ports
.clk_out1(clk_out1),
// Status and control signals
.reset(reset),
.locked(locked)
);
endmodule
|
//Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2016.1 (lin64) Build 1538259 Fri Apr 8 15:45:23 MDT 2016
//Date : Mon Jun 6 23:44:13 2016
//Host : edinburgh running 64-bit Ubuntu 15.04
//Command : generate_target opl3_cpu_wrapper.bd
//Design : opl3_cpu_wrapper
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module opl3_cpu_wrapper
(DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb,
ac_mclk,
ac_mute_n,
clk125,
i2s_sclk,
i2s_sd,
i2s_ws,
iic_0_scl_io,
iic_0_sda_io,
led);
inout [14:0]DDR_addr;
inout [2:0]DDR_ba;
inout DDR_cas_n;
inout DDR_ck_n;
inout DDR_ck_p;
inout DDR_cke;
inout DDR_cs_n;
inout [3:0]DDR_dm;
inout [31:0]DDR_dq;
inout [3:0]DDR_dqs_n;
inout [3:0]DDR_dqs_p;
inout DDR_odt;
inout DDR_ras_n;
inout DDR_reset_n;
inout DDR_we_n;
inout FIXED_IO_ddr_vrn;
inout FIXED_IO_ddr_vrp;
inout [53:0]FIXED_IO_mio;
inout FIXED_IO_ps_clk;
inout FIXED_IO_ps_porb;
inout FIXED_IO_ps_srstb;
output ac_mclk;
output ac_mute_n;
input clk125;
output i2s_sclk;
output i2s_sd;
output i2s_ws;
inout iic_0_scl_io;
inout iic_0_sda_io;
output [3:0]led;
wire [14:0]DDR_addr;
wire [2:0]DDR_ba;
wire DDR_cas_n;
wire DDR_ck_n;
wire DDR_ck_p;
wire DDR_cke;
wire DDR_cs_n;
wire [3:0]DDR_dm;
wire [31:0]DDR_dq;
wire [3:0]DDR_dqs_n;
wire [3:0]DDR_dqs_p;
wire DDR_odt;
wire DDR_ras_n;
wire DDR_reset_n;
wire DDR_we_n;
wire FIXED_IO_ddr_vrn;
wire FIXED_IO_ddr_vrp;
wire [53:0]FIXED_IO_mio;
wire FIXED_IO_ps_clk;
wire FIXED_IO_ps_porb;
wire FIXED_IO_ps_srstb;
wire ac_mclk;
wire ac_mute_n;
wire clk125;
wire i2s_sclk;
wire i2s_sd;
wire i2s_ws;
wire iic_0_scl_i;
wire iic_0_scl_io;
wire iic_0_scl_o;
wire iic_0_scl_t;
wire iic_0_sda_i;
wire iic_0_sda_io;
wire iic_0_sda_o;
wire iic_0_sda_t;
wire [3:0]led;
IOBUF iic_0_scl_iobuf
(.I(iic_0_scl_o),
.IO(iic_0_scl_io),
.O(iic_0_scl_i),
.T(iic_0_scl_t));
IOBUF iic_0_sda_iobuf
(.I(iic_0_sda_o),
.IO(iic_0_sda_io),
.O(iic_0_sda_i),
.T(iic_0_sda_t));
opl3_cpu opl3_cpu_i
(.DDR_addr(DDR_addr),
.DDR_ba(DDR_ba),
.DDR_cas_n(DDR_cas_n),
.DDR_ck_n(DDR_ck_n),
.DDR_ck_p(DDR_ck_p),
.DDR_cke(DDR_cke),
.DDR_cs_n(DDR_cs_n),
.DDR_dm(DDR_dm),
.DDR_dq(DDR_dq),
.DDR_dqs_n(DDR_dqs_n),
.DDR_dqs_p(DDR_dqs_p),
.DDR_odt(DDR_odt),
.DDR_ras_n(DDR_ras_n),
.DDR_reset_n(DDR_reset_n),
.DDR_we_n(DDR_we_n),
.FIXED_IO_ddr_vrn(FIXED_IO_ddr_vrn),
.FIXED_IO_ddr_vrp(FIXED_IO_ddr_vrp),
.FIXED_IO_mio(FIXED_IO_mio),
.FIXED_IO_ps_clk(FIXED_IO_ps_clk),
.FIXED_IO_ps_porb(FIXED_IO_ps_porb),
.FIXED_IO_ps_srstb(FIXED_IO_ps_srstb),
.IIC_0_scl_i(iic_0_scl_i),
.IIC_0_scl_o(iic_0_scl_o),
.IIC_0_scl_t(iic_0_scl_t),
.IIC_0_sda_i(iic_0_sda_i),
.IIC_0_sda_o(iic_0_sda_o),
.IIC_0_sda_t(iic_0_sda_t),
.ac_mclk(ac_mclk),
.ac_mute_n(ac_mute_n),
.clk125(clk125),
.i2s_sclk(i2s_sclk),
.i2s_sd(i2s_sd),
.i2s_ws(i2s_ws),
.led(led));
endmodule
|
/* Copyright (C) 2015-2016 by John Cronin
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
// SPI interface
module spi(clk, clk_div, data_in, data_out, send_data, data_ready, spi_sclk, spi_mosi, spi_miso, mode);
input clk;
input [31:0] clk_div;
output [7:0] data_in;
input [7:0] data_out;
input send_data;
output data_ready;
output spi_sclk;
output spi_mosi;
input spi_miso;
input [1:0] mode;
reg [7:0] xmit_state = 8'hff; // rests at 0xff, counts 7 through 0 during transmission (bytes sent msb first)
reg [7:0] next_xmit_state = 8'h00;
reg spi_sclk = 0;
reg [31:0] cd = 32'd0;
reg [7:0] data_in = 8'd0;
reg spi_mosi = 0;
reg latch_buf = 0;
assign data_ready = &xmit_state;
always @(posedge clk)
begin
begin
cd = cd + 32'd2;
if(cd >= clk_div) begin
if(~&xmit_state) begin
// Clock has ticked whilst sending
// state decrements on low in modes 0/1, on high in modes 2/3
if(spi_sclk & mode[1])
xmit_state = xmit_state - 8'h01;
else if(~spi_sclk & ~mode[1])
xmit_state = xmit_state - 8'h01;
// some modes (0 and 2) don't shift the current state but the next state
next_xmit_state = xmit_state - 8'h1;
if(&next_xmit_state)
next_xmit_state = 8'h0;
spi_sclk = ~spi_sclk;
// if xmit_state has reached 0xff, set clk to CPOL
if(&xmit_state)
spi_sclk = mode[1];
else begin
// else transfer some data
// modes 0 and 2 latch before shifting, therefore we need to buffer the data recived
// so it doesn't overwrite what we're about to shift out
// if clock has gone positive, latch in modes 0 and 3, shift in 1 and 2
// if negative, latch in 1/2, shift in 0/3
if(spi_sclk)
case(mode)
2'd0:
latch_buf = spi_miso;
2'd1:
spi_mosi = data_out[xmit_state[2:0]];
2'd2:
begin
spi_mosi = data_out[next_xmit_state[2:0]];
data_in[xmit_state[2:0]] = latch_buf;
end
2'd3:
data_in[xmit_state[2:0]] = spi_miso;
endcase
else
case(mode)
2'd0:
begin
spi_mosi = data_out[next_xmit_state[2:0]];
data_in[xmit_state[2:0]] = latch_buf;
end
2'd1:
data_in[xmit_state[2:0]] = spi_miso;
2'd2:
latch_buf = spi_miso;
2'd3:
spi_mosi = data_out[xmit_state[2:0]];
endcase
end
end
// reset clk counter
cd = 32'd0;
end
end
if(&xmit_state)
spi_sclk = mode[1];
if(send_data & &xmit_state)
begin
xmit_state = 8'd8;
spi_mosi = ~mode[1] & data_out[7]; // shift the first byte out before clock starts cycling in modes 0 + 2
end
end
endmodule
|
`timescale 1 ns / 100 ps
module tube_ula_testbench();
// Inputs
reg DACK;
reg [2:0] HA;
reg HCS;
reg [7:0] HDIN;
wire HO2;
reg HO2early;
reg HRST;
reg HRW;
reg [2:0] PA;
reg PCS;
reg [7:0] PDIN;
reg PNRDS;
reg PNWDS;
wire PNRDSgated;
wire PNWDSgated;
// Outputs
wire DRQ;
wire [7:0] HDOUT;
wire HDOE;
wire HIRQ;
wire [7:0] PDOUT;
wire PDOE;
wire PIRQ;
wire PNMI;
wire PRST;
task host_write;
input [2:0] addr;
input [7:0] data;
begin
@ (negedge HO2);
HA = addr;
HDIN = data;
HRW = 0;
HCS = 0;
@ (negedge HO2);
HCS = 1;
HA = 3'bXXX;
HDIN = 8'bXXXXXXXX;
HRW = 1;
end
endtask
task host_read;
input [2:0] addr;
input [7:0] expected_mask;
input [7:0] expected_data;
begin
@ (negedge HO2);
HA = addr;
HRW = 1;
HCS = 0;
@ (posedge HO2);
if ((HDOUT & expected_mask) != expected_data)
$display("%0dns: host addr %0d data error detected; expected_mask = %b; expected_data = %b; actual_data = %b", $time, HA, expected_mask, expected_data, HDOUT);
@ (negedge HO2);
HCS = 1;
HA = 3'bXXX;
HRW = 1;
end
endtask
task para_write;
input [2:0] addr;
input [7:0] data;
begin
@ (negedge HO2);
PA = addr;
PDIN = data;
PNWDS = 0;
PCS = 0;
@ (negedge HO2);
PCS = 1;
PA = 3'bXXX;
PDIN = 8'bXXXXXXXX;
PNWDS = 1;
end
endtask
task para_read;
input [2:0] addr;
input [7:0] expected_mask;
input [7:0] expected_data;
begin
@ (negedge HO2);
PA = addr;
PNRDS = 0;
PCS = 0;
@ (posedge HO2);
if ((PDOUT & expected_mask) != expected_data)
$display("%0dns: para addr %0d data error detected; expected_mask = %b; expected_data = %b; actual_data = %b", $time, PA, expected_mask, expected_data, PDOUT);
@ (negedge HO2);
PCS = 1;
PA = 3'bXXX;
PNRDS = 1;
end
endtask
task delay;
input integer n;
begin
repeat (n)
begin
@ (negedge HO2);
end
end
endtask
task test_host_to_para_fifo;
input [2:0] status;
input [2:0] fifo;
input integer num;
begin
$display("%0dns: Testing host to para status=%0d, fifo=%0d, num=%0d", $time, status, fifo, num);
// Initial FIFO state should be empty
// Bit 7 is Available, Bit 6 is not full
host_read(status, 8'b11000000, 8'b01000000);
para_read(status, 8'b11000000, 8'b01000000);
for (i = 0; i < num; i = i + 1)
begin
host_write(fifo, 170 + i); // write to host
end
// Intermediate FIFO state should be full
host_read(status, 8'b11000000, 8'b00000000);
para_read(status, 8'b11000000, 8'b11000000);
for (i = 0; i < num; i = i + 1)
begin
para_read(fifo, 8'b11111111, 170 + i); // read from para
end
// Initial FIFO state should be empty
host_read(status, 8'b11000000, 8'b01000000);
para_read(status, 8'b11000000, 8'b01000000);
end
endtask
task test_para_to_host_fifo;
input [2:0] status;
input [2:0] fifo;
input integer num;
begin
$display("%0dns: Testing para to host status=%0d, fifo=%0d, num=%0d", $time, status, fifo, num);
// Initial FIFO state should be empty
// Bit 7 is Available, Bit 6 is not full
para_read(status, 8'b11000000, 8'b01000000);
host_read(status, 8'b11000000, 8'b01000000);
for (i = 0; i < num; i = i + 1)
begin
para_write(fifo, 170 + i); // write to para
end
// Intermediate FIFO state should be full
para_read(status, 8'b11000000, 8'b00000000);
host_read(status, 8'b11000000, 8'b11000000);
for (i = 0; i < num; i = i + 1)
begin
host_read(fifo, 8'b11111111, 170 + i); // read from host
end
// Initial FIFO state should be empty
para_read(status, 8'b11000000, 8'b01000000);
host_read(status, 8'b11000000, 8'b01000000);
end
endtask
// Instantaiate gate level design
tube_ula U1 (
// Inputs
.DACK(DACK),
.HA2(HA[2]),
.HA1(HA[1]),
.HA0(HA[0]),
.HCS(HCS),
.HD7IN(HDIN[7]),
.HD6IN(HDIN[6]),
.HD5IN(HDIN[5]),
.HD4IN(HDIN[4]),
.HD3IN(HDIN[3]),
.HD2IN(HDIN[2]),
.HD1IN(HDIN[1]),
.HD0IN(HDIN[0]),
.HO2(HO2early),
.HRST(HRST),
.HRW(HRW),
.PA2(PA[2]),
.PA1(PA[1]),
.PA0(PA[0]),
.PCS(PCS),
.PD7IN(PDIN[7]),
.PD6IN(PDIN[6]),
.PD5IN(PDIN[5]),
.PD4IN(PDIN[4]),
.PD3IN(PDIN[3]),
.PD2IN(PDIN[2]),
.PD1IN(PDIN[1]),
.PD0IN(PDIN[0]),
.PNRDS(PNRDSgated),
.PNWDS(PNWDSgated),
// Outputs
.DRQ(DRQ),
.HD7OUT(HDOUT[7]),
.HD6OUT(HDOUT[6]),
.HD5OUT(HDOUT[5]),
.HD4OUT(HDOUT[4]),
.HD3OUT(HDOUT[3]),
.HD2OUT(HDOUT[2]),
.HD1OUT(HDOUT[1]),
.HD0OUT(HDOUT[0]),
.HDOE(HDOE),
.HIRQ(HIRQ),
.PD7OUT(PDOUT[7]),
.PD6OUT(PDOUT[6]),
.PD5OUT(PDOUT[5]),
.PD4OUT(PDOUT[4]),
.PD3OUT(PDOUT[3]),
.PD2OUT(PDOUT[2]),
.PD1OUT(PDOUT[1]),
.PD0OUT(PDOUT[0]),
.PDOE(PDOE),
.PIRQ(PIRQ),
.PNMI(PNMI),
.PRST(PRST)
);
integer i;
initial
begin
DACK = 1;
HA = 3'bXXX;
HCS = 1;
HDIN = 8'bXXXXXXXX;
HO2early = 0;
HRST = 1;
HRW = 1;
PA = 3'bXXX;
PCS = 1;
PDIN = 8'bXXXXXXXX;
PNRDS = 1;
PNWDS = 1;
// Synchronously assert HRST for 50 clocks
@ (negedge HO2);
HRST = 0;
repeat (50)
begin
@ (negedge HO2);
end
HRST = 1;
delay(10);
// Take PRST high, low, high
host_write(3'b000, 8'b00100000);
host_write(3'b000, 8'b10100000);
host_write(3'b000, 8'b00100000);
host_read(3'b000, 0, 0);
delay(10);
// Get rid of X's from address pointers
delay(10);
// De-Assert soft reset (up until this point it will be X)
host_write(3'b000, 8'b01000000);
delay(10);
// Assert soft reset for atleast 24 clocks to flush the 24 byte FIFO
host_write(3'b000, 8'b11000000);
delay(50);
// De-Assert soft reset
host_write(3'b000, 8'b01000000);
delay(10);
// Disable all interrupts
host_write(3'b000, 8'b00001111);
// Set two byte mode for register 3
host_write(3'b000, 8'b10100000);
// Check the control bits are as expected
host_read(3'b000, 8'b00111111, 8'b00100000);
// Read the junk byte out of register 3
host_read(3'b101, 0, 0);
para_read(3'b101, 0, 0);
para_read(3'b101, 0, 0);
delay(10);
// Test Host To Para
// Test Register 1
test_host_to_para_fifo(3'b000, 3'b001, 1);
delay(10);
// Test Register 2
test_host_to_para_fifo(3'b010, 3'b011, 1);
delay(10);
// Test Register 3
test_host_to_para_fifo(3'b100, 3'b101, 2);
delay(10);
// Test Register 4
test_host_to_para_fifo(3'b110, 3'b111, 1);
delay(10);
// Test Para to Host
// Test Register 1
test_para_to_host_fifo(3'b000, 3'b001, 24);
delay(10);
// Test Register 2
test_para_to_host_fifo(3'b010, 3'b011, 1);
delay(10);
// Test Register 3
test_para_to_host_fifo(3'b100, 3'b101, 2);
delay(10);
// Test Register 4
test_para_to_host_fifo(3'b110, 3'b111, 1);
delay(10);
end
always
begin
#500 HO2early = ~HO2early;
end
assign #250 HO2 = HO2early;
assign PNRDSgated = PNRDS | ~HO2early;
assign PNWDSgated = PNWDS | ~HO2early;
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// or1200_monitor.v ////
//// ////
//// OR1200 processor monitor module ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, [email protected] ////
//// - Julius Baxter, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009, 2010 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
`include "timescale.v"
`include "or1200_defines.v"
`include "or1200_monitor_defines.v"
`include "test-defines.v"
module or1200_monitor;
integer fexe;
integer finsn;
reg [23:0] ref;
`ifdef OR1200_MONITOR_SPRS
integer fspr;
`endif
integer fgeneral;
`ifdef OR1200_MONITOR_LOOKUP
integer flookup;
`endif
integer r3;
integer insns;
//
// Initialization
//
initial begin
ref = 0;
`ifdef OR1200_MONITOR_EXEC_STATE
fexe = $fopen({"../out/",`TEST_NAME_STRING,"-executed.log"});
`endif
`ifdef OR1200_MONITOR_EXEC_LOG_DISASSEMBLY
finsn = fexe;
`endif
$timeformat (-9, 2, " ns", 12);
`ifdef OR1200_MONITOR_SPRS
fspr = $fopen({"../out/",`TEST_NAME_STRING,"-sprs.log"});
`endif
fgeneral = $fopen({"../out/",`TEST_NAME_STRING,"-general.log"});
`ifdef OR1200_MONITOR_LOOKUP
flookup = $fopen({"../out/",`TEST_NAME_STRING,"-lookup.log"});
`endif
insns = 0;
end
//
// Get GPR
//
task get_gpr;
input [4:0] gpr_no;
output [31:0] gpr;
integer j;
begin
`ifdef OR1200_RFRAM_GENERIC
for(j = 0; j < 32; j = j + 1) begin
gpr[j] = `OR1200_TOP.`CPU_cpu.`CPU_rf.rf_a.mem[gpr_no*32+j];
end
`else
//gpr = `OR1200_TOP.`CPU_cpu.`CPU_rf.rf_a.mem[gpr_no];
gpr = `OR1200_TOP.`CPU_cpu.`CPU_rf.rf_a.get_gpr(gpr_no);
`endif
end
endtask
//
// Write state of the OR1200 registers into a file
//
// Limitation: only a small subset of register file RAMs
// are supported
//
task display_arch_state;
reg [5:0] i;
reg [31:0] r;
integer j;
begin
`ifdef OR1200_MONITOR_EXEC_STATE
ref = ref + 1;
`ifdef OR1200_MONITOR_LOOKUP
$fdisplay(flookup, "Instruction %d: %t", insns, $time);
`endif
$fwrite(fexe, "\nEXECUTED(%d): %h: %h", insns,
`OR1200_TOP.`CPU_cpu.`CPU_except.wb_pc,
`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn);
`ifdef OR1200_MONITOR_EXEC_LOG_DISASSEMBLY
$fwrite(fexe,"\t");
// Decode the instruction, print it out
or1200_print_op(`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn);
`endif
for(i = 0; i < 32; i = i + 1) begin
if (i % 4 == 0)
$fdisplay(fexe);
get_gpr(i, r);
$fwrite(fexe, "GPR%d: %h ", i, r);
end
$fdisplay(fexe);
r = `OR1200_TOP.`CPU_cpu.`CPU_sprs.sr;
$fwrite(fexe, "SR : %h ", r);
r = `OR1200_TOP.`CPU_cpu.`CPU_sprs.epcr;
$fwrite(fexe, "EPCR0: %h ", r);
r = `OR1200_TOP.`CPU_cpu.`CPU_sprs.eear;
$fwrite(fexe, "EEAR0: %h ", r);
r = `OR1200_TOP.`CPU_cpu.`CPU_sprs.esr;
$fdisplay(fexe, "ESR0 : %h", r);
`endif // `ifdef OR1200_MONITOR_EXEC_STATE
`ifdef OR1200_DISPLAY_EXECUTED
ref = ref + 1;
`ifdef OR1200_MONITOR_LOOKUP
$fdisplay(flookup, "Instruction %d: %t", insns, $time);
`endif
$fwrite(fexe, "\nEXECUTED(%d): %h: %h", insns, `OR1200_TOP.`CPU_cpu.`CPU_except.wb_pc, `OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn);
`endif
insns = insns + 1;
end
endtask // display_arch_state
/* Keep a trace buffer of the last lot of instructions and addresses
* "executed",as read from the writeback stage, and cause a $finish if we hit
* an instruction that is invalid, such as all zeros.
* Currently, only breaks on an all zero instruction, but should probably be
* made to break for anything with an X in it too. And of course ideally this
* shouldn't be needed - but is handy if someone changes something and stops
* the test continuing forever.
*/
integer num_nul_inst;
initial num_nul_inst = 0;
task monitor_for_crash;
`define OR1200_MONITOR_CRASH_TRACE_SIZE 32
//Trace buffer of 32 instructions
reg [31:0] insn_trace [0:`OR1200_MONITOR_CRASH_TRACE_SIZE-1];
//Trace buffer of the addresses of those instructions
reg [31:0] addr_trace [0:`OR1200_MONITOR_CRASH_TRACE_SIZE-1];
integer i;
begin
if (`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn == 32'h00000000)
num_nul_inst = num_nul_inst + 1;
else
num_nul_inst = 0; // Reset it
if (num_nul_inst == 1000) // Sat a loop a bit too long...
begin
$fdisplay(fgeneral, "ERROR - no instruction at PC %h",
`OR1200_TOP.`CPU_cpu.`CPU_except.wb_pc);
$fdisplay(fgeneral, "Crash trace: Last %d instructions: ",
`OR1200_MONITOR_CRASH_TRACE_SIZE);
$fdisplay(fgeneral, "PC\t\tINSTR");
for(i=`OR1200_MONITOR_CRASH_TRACE_SIZE-1;i>=0;i=i-1) begin
$fdisplay(fgeneral, "%h\t%h",addr_trace[i], insn_trace[i]);
end
$display("*");
$display("* or1200_monitor : OR1200 crash detected (suspected CPU PC corruption)");
$display("*");
#100 $finish;
end
else
begin
for(i=`OR1200_MONITOR_CRASH_TRACE_SIZE-1;i>0;i=i-1) begin
insn_trace[i] = insn_trace[i-1];
addr_trace[i] = addr_trace[i-1];
end
insn_trace[0] = `OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn;
addr_trace[0] = `OR1200_TOP.`CPU_cpu.`CPU_except.wb_pc;
end
end
endtask // monitor_for_crash
//
// Write state of the OR1200 registers into a file; version for exception
//
task display_arch_state_except;
reg [5:0] i;
reg [31:0] r;
integer j;
begin
`ifdef OR1200_MONITOR_EXEC_STATE
ref = ref + 1;
`ifdef OR1200_MONITOR_LOOKUP
$fdisplay(flookup, "Instruction %d: %t", insns, $time);
`endif
$fwrite(fexe, "\nEXECUTED(%d): %h: %h (exception)", insns, `OR1200_TOP.`CPU_cpu.`CPU_except.ex_pc, `OR1200_TOP.`CPU_cpu.`CPU_ctrl.ex_insn);
for(i = 0; i < 32; i = i + 1) begin
if (i % 4 == 0)
$fdisplay(fexe);
get_gpr(i, r);
$fwrite(fexe, "GPR%d: %h ", i, r);
end
$fdisplay(fexe);
r = `OR1200_TOP.`CPU_cpu.`CPU_sprs.sr;
$fwrite(fexe, "SR : %h ", r);
r = `OR1200_TOP.`CPU_cpu.`CPU_sprs.epcr;
$fwrite(fexe, "EPCR0: %h ", r);
r = `OR1200_TOP.`CPU_cpu.`CPU_sprs.eear;
$fwrite(fexe, "EEAR0: %h ", r);
r = `OR1200_TOP.`CPU_cpu.`CPU_sprs.esr;
$fdisplay(fexe, "ESR0 : %h", r);
insns = insns + 1;
`endif // `ifdef OR1200_MONITOR_EXEC_STATE
`ifdef OR1200_DISPLAY_EXECUTED
ref = ref + 1;
`ifdef OR1200_MONITOR_LOOKUP
$fdisplay(flookup, "Instruction %d: %t", insns, $time);
`endif
$fwrite(fexe, "\nEXECUTED(%d): %h: %h (exception)", insns,
`OR1200_TOP.`CPU_cpu.`CPU_except.ex_pc,
`OR1200_TOP.`CPU_cpu.`CPU_ctrl.ex_insn);
insns = insns + 1;
`endif
end
endtask
integer iwb_progress;
reg [31:0] iwb_progress_addr;
//
// WISHBONE bus checker
//
always @(posedge `OR1200_TOP.iwb_clk_i)
if (`OR1200_TOP.iwb_rst_i) begin
iwb_progress = 0;
iwb_progress_addr = `OR1200_TOP.iwb_adr_o;
end
else begin
if (`OR1200_TOP.iwb_cyc_o && (iwb_progress != 2)) begin
iwb_progress = 1;
end
if (`OR1200_TOP.iwb_stb_o) begin
if (iwb_progress >= 1) begin
if (iwb_progress == 1)
iwb_progress_addr = `OR1200_TOP.iwb_adr_o;
iwb_progress = 2;
end
else begin
$fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.iwb_stb_o raised without `OR1200_TOP.iwb_cyc_o, at %t\n", $time);
#100 $finish;
end
end
if (`OR1200_TOP.iwb_ack_i & `OR1200_TOP.iwb_err_i) begin
$fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.iwb_ack_i and `OR1200_TOP.iwb_err_i raised at the same time, at %t\n", $time);
end
if ((iwb_progress == 2) && (iwb_progress_addr != `OR1200_TOP.iwb_adr_o)) begin
$fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.iwb_adr_o changed while waiting for `OR1200_TOP.iwb_err_i/`OR1200_TOP.iwb_ack_i, at %t\n", $time);
#100 $finish;
end
if (`OR1200_TOP.iwb_ack_i | `OR1200_TOP.iwb_err_i)
if (iwb_progress == 2) begin
iwb_progress = 0;
iwb_progress_addr = `OR1200_TOP.iwb_adr_o;
end
else begin
$fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.iwb_ack_i/`OR1200_TOP.iwb_err_i raised without `OR1200_TOP.iwb_cyc_i/`OR1200_TOP.iwb_stb_i, at %t\n", $time);
#100 $finish;
end
if ((iwb_progress == 2) && !`OR1200_TOP.iwb_stb_o) begin
$fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.iwb_stb_o lowered without `OR1200_TOP.iwb_err_i/`OR1200_TOP.iwb_ack_i, at %t\n", $time);
#100 $finish;
end
end
integer dwb_progress;
reg [31:0] dwb_progress_addr;
//
// WISHBONE bus checker
//
always @(posedge `OR1200_TOP.dwb_clk_i)
if (`OR1200_TOP.dwb_rst_i)
dwb_progress = 0;
else begin
if (`OR1200_TOP.dwb_cyc_o && (dwb_progress != 2))
dwb_progress = 1;
if (`OR1200_TOP.dwb_stb_o)
if (dwb_progress >= 1) begin
if (dwb_progress == 1)
dwb_progress_addr = `OR1200_TOP.dwb_adr_o;
dwb_progress = 2;
end
else begin
$fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.dwb_stb_o raised without `OR1200_TOP.dwb_cyc_o, at %t\n", $time);
#100 $finish;
end
if (`OR1200_TOP.dwb_ack_i & `OR1200_TOP.dwb_err_i) begin
$fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.dwb_ack_i and `OR1200_TOP.dwb_err_i raised at the same time, at %t\n", $time);
end
if ((dwb_progress == 2) && (dwb_progress_addr != `OR1200_TOP.dwb_adr_o)) begin
$fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.dwb_adr_o changed while waiting for `OR1200_TOP.dwb_err_i/`OR1200_TOP.dwb_ack_i, at %t\n", $time);
#100 $finish;
end
if (`OR1200_TOP.dwb_ack_i | `OR1200_TOP.dwb_err_i)
if (dwb_progress == 2) begin
dwb_progress = 0;
dwb_progress_addr = `OR1200_TOP.dwb_adr_o;
end
else begin
$fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.dwb_ack_i/`OR1200_TOP.dwb_err_i raised without `OR1200_TOP.dwb_cyc_i/`OR1200_TOP.dwb_stb_i, at %t\n", $time);
#100 $finish;
end
if ((dwb_progress == 2) && !`OR1200_TOP.dwb_stb_o) begin
$fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.dwb_stb_o lowered without `OR1200_TOP.dwb_err_i/`OR1200_TOP.dwb_ack_i, at %t\n", $time);
#100 $finish;
end
end
// Softpatch - check for assertion violations
reg [31:0] sp_assertions_violated_reg_prev;
reg [31:0] sp_checker_3_counter_prev;
reg [31:0] sp_insn_counter_prev;
initial begin
sp_assertions_violated_reg_prev = 0;
sp_checker_3_counter_prev = 0;
sp_insn_counter_prev = 1;
end
always @(posedge `CPU_CORE_CLK)
if(`OR1200_TOP.`CPU_cpu.sp_assertion_violated)
if(sp_assertions_violated_reg_prev != `OR1200_TOP.`CPU_cpu.bia.checkersFired_reg)begin
if((`OR1200_TOP.`CPU_cpu.bia.checkersFired_reg & 32'hfffffff7) != 32'h0)
$display("Assertions violated at %t: %h\n", $time, `OR1200_TOP.`CPU_cpu.bia.checkersFired_reg);
sp_assertions_violated_reg_prev <= `OR1200_TOP.`CPU_cpu.bia.checkersFired_reg;
end
always @(posedge `CPU_CORE_CLK)begin
sp_insn_counter_prev <= `OR1200_TOP.`CPU_cpu.bia.insn_counter;
if(`OR1200_TOP.`CPU_cpu.bia.insn_counter == 32'h0 && `OR1200_TOP.`CPU_cpu.bia.insn_counter != sp_insn_counter_prev)
$display("Instruction counter rolled over at %t\n", $time);
end
always @(posedge `CPU_CORE_CLK)
if(sp_checker_3_counter_prev != `OR1200_TOP.`CPU_cpu.bia.checker_3_counter)begin
$display("False positive %d at 0x%h\n", `OR1200_TOP.`CPU_cpu.bia.checker_3_counter, `OR1200_TOP.`CPU_cpu.bia.insn_counter);
sp_checker_3_counter_prev <= `OR1200_TOP.`CPU_cpu.bia.checker_3_counter;
end
//
// Hooks for:
// - displaying registers
// - end of simulation
// - access to SPRs
//
always @(posedge `CPU_CORE_CLK)
if (!`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_freeze) begin
// #2;
if (((`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn[31:26] != `OR1200_OR32_NOP)
| !`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn[16])
& !(`OR1200_TOP.`CPU_cpu.`CPU_except.except_flushpipe &
`OR1200_TOP.`CPU_cpu.`CPU_except.ex_dslot))
begin
display_arch_state;
monitor_for_crash;
end
else
if (`OR1200_TOP.`CPU_cpu.`CPU_except.except_flushpipe)
display_arch_state_except;
// small hack to stop simulation (l.nop 1):
if (`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn == 32'h1500_0001) begin
get_gpr(3, r3);
$fdisplay(fgeneral, "%t: l.nop exit (%h)", $time, r3);
`ifdef OR1200_MONITOR_VERBOSE_NOPS
// Note that the 'expect' scripts in or1ksim's test suite look for strings
// like "exit(1)", therefore something like "exit( 1)" would fail.
$display("exit(%0d)",r3);
`endif
$finish;
end
// debug if test (l.nop 10)
if (`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn == 32'h1500_000a) begin
$fdisplay(fgeneral, "%t: l.nop dbg_if_test", $time);
end
// simulation reports (l.nop 2)
if (`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn == 32'h1500_0002) begin
get_gpr(3, r3);
$fdisplay(fgeneral, "%t: l.nop report (0x%h)", $time, r3);
`ifdef OR1200_MONITOR_VERBOSE_NOPS
// Note that the 'expect' scripts in or1ksim's test suite look for strings
// like "report(0x7ffffffe);", therefore something like "report (0x7ffffffe);"
// (note the extra space character) would fail.
$display("report(0x%h);", r3);
`endif
end
// simulation printfs (l.nop 3)
if (`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn == 32'h1500_0003) begin
get_gpr(3, r3);
$fdisplay(fgeneral, "%t: l.nop printf (%h)", $time, r3);
end
if (`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn == 32'h1500_0004) begin
// simulation putc (l.nop 4)
get_gpr(3, r3);
$write("%c", r3);
$fdisplay(fgeneral, "%t: l.nop putc (%c)", $time, r3);
end
`ifdef OR1200_MONITOR_SPRS
if (`OR1200_TOP.`CPU_cpu.`CPU_sprs.spr_we)
$fdisplay(fspr, "%t: Write to SPR : [%h] <- %h", $time,
`OR1200_TOP.`CPU_cpu.`CPU_sprs.spr_addr,
`OR1200_TOP.`CPU_cpu.`CPU_sprs.spr_dat_o);
if ((|`OR1200_TOP.`CPU_cpu.`CPU_sprs.spr_cs) &
!`OR1200_TOP.`CPU_cpu.`CPU_sprs.spr_we)
$fdisplay(fspr, "%t: Read from SPR: [%h] -> %h", $time,
`OR1200_TOP.`CPU_cpu.`CPU_sprs.spr_addr,
`OR1200_TOP.`CPU_cpu.`CPU_sprs.to_wbmux);
`endif
end
`ifdef RAM_WB
`define RAM_WB_TOP `DUT_TOP.ram_wb0.ram_wb_b3_0
task get_insn_from_wb_ram;
input [31:0] addr;
output [31:0] insn;
begin
insn = `RAM_WB_TOP.get_mem32(addr[31:2]);
end
endtask // get_insn_from_wb_ram
`endif
`ifdef VERSATILE_SDRAM
`define SDRAM_TOP `TB_TOP.sdram0
// Bit selects to define the bank
// 32 MB part with 4 banks
`define SDRAM_BANK_SEL_BITS 24:23
`define SDRAM_WORD_SEL_TOP_BIT 22
// Gets instruction word from correct bank
task get_insn_from_sdram;
input [31:0] addr;
output [31:0] insn;
reg [`SDRAM_WORD_SEL_TOP_BIT-1:0] word_addr;
begin
word_addr = addr[`SDRAM_WORD_SEL_TOP_BIT:2];
if (addr[`SDRAM_BANK_SEL_BITS] == 2'b00)
begin
//$display("%t: get_insn_from_sdram bank0, word 0x%h, (%h and %h in SDRAM)", $time, word_addr, `SDRAM_TOP.Bank0[{word_addr,1'b0}], `SDRAM_TOP.Bank0[{word_addr,1'b1}]);
insn[15:0] = `SDRAM_TOP.Bank0[{word_addr,1'b1}];
insn[31:16] = `SDRAM_TOP.Bank0[{word_addr,1'b0}];
end
end
endtask // get_insn_from_sdram
`endif // `ifdef VERSATILE_SDRAM
`ifdef XILINX_DDR2
`define DDR2_TOP `TB_TOP.gen_cs[0]
// Gets instruction word from correct bank
task get_insn_from_xilinx_ddr2;
input [31:0] addr;
output [31:0] insn;
reg [16*8-1:0] ddr2_array_line0,ddr2_array_line1,ddr2_array_line2,
ddr2_array_line3;
integer word_in_line_num;
begin
// Get our 4 128-bit chunks (8 half-words in each!! Confused yet?),
// 16 words total
`DDR2_TOP.gen[0].u_mem0.memory_read(addr[28:27],addr[26:13],{addr[12:6],3'd0},ddr2_array_line0);
`DDR2_TOP.gen[1].u_mem0.memory_read(addr[28:27],addr[26:13],{addr[12:6],3'd0},ddr2_array_line1);
`DDR2_TOP.gen[2].u_mem0.memory_read(addr[28:27],addr[26:13],{addr[12:6],3'd0},ddr2_array_line2);
`DDR2_TOP.gen[3].u_mem0.memory_read(addr[28:27],addr[26:13],{addr[12:6],3'd0},ddr2_array_line3);
case (addr[5:2])
4'h0:
begin
insn[15:0] = ddr2_array_line0[15:0];
insn[31:16] = ddr2_array_line1[15:0];
end
4'h1:
begin
insn[15:0] = ddr2_array_line2[15:0];
insn[31:16] = ddr2_array_line3[15:0];
end
4'h2:
begin
insn[15:0] = ddr2_array_line0[31:16];
insn[31:16] = ddr2_array_line1[31:16];
end
4'h3:
begin
insn[15:0] = ddr2_array_line2[31:16];
insn[31:16] = ddr2_array_line3[31:16];
end
4'h4:
begin
insn[15:0] = ddr2_array_line0[47:32];
insn[31:16] = ddr2_array_line1[47:32];
end
4'h5:
begin
insn[15:0] = ddr2_array_line2[47:32];
insn[31:16] = ddr2_array_line3[47:32];
end
4'h6:
begin
insn[15:0] = ddr2_array_line0[63:48];
insn[31:16] = ddr2_array_line1[63:48];
end
4'h7:
begin
insn[15:0] = ddr2_array_line2[63:48];
insn[31:16] = ddr2_array_line3[63:48];
end
4'h8:
begin
insn[15:0] = ddr2_array_line0[79:64];
insn[31:16] = ddr2_array_line1[79:64];
end
4'h9:
begin
insn[15:0] = ddr2_array_line2[79:64];
insn[31:16] = ddr2_array_line3[79:64];
end
4'ha:
begin
insn[15:0] = ddr2_array_line0[95:80];
insn[31:16] = ddr2_array_line1[95:80];
end
4'hb:
begin
insn[15:0] = ddr2_array_line2[95:80];
insn[31:16] = ddr2_array_line3[95:80];
end
4'hc:
begin
insn[15:0] = ddr2_array_line0[111:96];
insn[31:16] = ddr2_array_line1[111:96];
end
4'hd:
begin
insn[15:0] = ddr2_array_line2[111:96];
insn[31:16] = ddr2_array_line3[111:96];
end
4'he:
begin
insn[15:0] = ddr2_array_line0[127:112];
insn[31:16] = ddr2_array_line1[127:112];
end
4'hf:
begin
insn[15:0] = ddr2_array_line2[127:112];
insn[31:16] = ddr2_array_line3[127:112];
end
endcase // case (addr[5:2])
end
endtask // get_insn_from_xilinx_ddr2
`endif
task get_insn_from_memory;
input [31:0] id_pc;
output [31:0] insn;
begin
// do a decode of which server we should look in
case (id_pc[31:28])
`ifdef VERSATILE_SDRAM
4'h0:
get_insn_from_sdram(id_pc, insn);
`endif
`ifdef XILINX_DDR2
4'h0:
get_insn_from_xilinx_ddr2(id_pc, insn);
`endif
`ifdef RAM_WB
4'h0:
get_insn_from_wb_ram(id_pc, insn);
`endif
4'hf:
// Flash isn't stored in a memory, it's an FSM so just skip/ignore
insn = `OR1200_TOP.`CPU_cpu.`CPU_ctrl.id_insn;
default:
begin
$fdisplay(fgeneral, "%t: Unknown memory server for address 0x%h", $time,id_pc);
insn = 32'hxxxxxxxx; // Unknown server
end
endcase // case (id_pc[31:28])
end
endtask // get_insn_from_memory
//
// Look in the iMMU TLB MR for this address' page, if MMUs are on and enabled
//
task check_for_immu_entry;
input [31:0] pc;
output [31:0] physical_pc;
output mmu_tlb_miss;
integer w,x;
reg [31:`OR1200_IMMU_PS] pc_vpn;
reg [`OR1200_ITLBTRW-1:0] itlb_tr;
reg [`OR1200_ITLBMRW-1:0] itlb_mr;
integer tlb_index;
reg mmu_en;
begin
mmu_tlb_miss = 0;
`ifdef OR1200_NO_IMMU
physical_pc = pc;
`else
mmu_en = `OR1200_TOP.`CPU_immu_top.immu_en;
// If MMU is enabled
if (mmu_en)
begin
// Look in the iTLB for mapping - get virtual page number
pc_vpn = pc[31:`OR1200_IMMU_PS];
tlb_index = pc[`OR1200_ITLB_INDX];
// Look at the ITLB match register
itlb_mr = `OR1200_TOP.`CPU_immu_top.`CPU_immu_tlb.itlb_mr_ram.mem[tlb_index];
// Get the translate register here too, in case there's an error, we print it
itlb_tr = `OR1200_TOP.`CPU_immu_top.`CPU_immu_tlb.itlb_tr_ram.mem[tlb_index];
if ((itlb_mr[`OR1200_ITLBMR_V_BITS] === 1'b1) & (itlb_mr[`OR1200_ITLBMRW-1:1] === pc[`OR1200_ITLB_TAG]))
begin
// Page number in match register matches page number of virtual PC, so get the physical
// address from the translate memory
// Now pull the physical page number out of the tranlsate register (it's after bottom 3 bits)
physical_pc = {itlb_tr[`OR1200_ITLBTRW-1:`OR1200_ITLBTRW-(32-`OR1200_IMMU_PS)],pc[`OR1200_IMMU_PS-1:0]};
//$display("check_for_immu_entry: found match for virtual PC 0x%h in entry %d of iMMU, mr = 0x%x tr = 0x%x, phys. PC = 0x%h", pc, pc[`OR1200_ITLB_INDX], itlb_mr, itlb_tr, physical_pc);
end // if ((itlb_mr[`OR1200_ITLBMR_V_BITS]) & (itlb_mr[`OR1200_ITLBMRW-1:1] == pc[`OR1200_ITLB_TAG]))
else
begin
// Wait a couple of clocks, see if we're doing a miss
@(posedge `CPU_CORE_CLK);
@(posedge `CPU_CORE_CLK);
if (!(`OR1200_TOP.`CPU_immu_top.miss)) // MMU should indicate miss
begin
$display("%t: check_for_immu_entry - ERROR - no match found for virtual PC 0x%h in entry %d of iMMU, mr = 0x%x tr = 0x%x, and no miss generated",
$time, pc, pc[`OR1200_ITLB_INDX], itlb_mr, itlb_tr);
#100;
$finish;
end
else
begin
mmu_tlb_miss = 1; // Started a miss, so ignore this instruction
end
end // else: !if((itlb_mr[`OR1200_ITLBMR_V_BITS]) & (itlb_mr[`OR1200_ITLBMRW-1:1] == pc[`OR1200_ITLB_TAG]))
end // if (`OR1200_TOP.`CPU_immu_top.immu_en === 1'b1)
else
physical_pc = pc;
`endif // !`ifdef OR1200_NO_IMMU
end
endtask // check_for_immu_entry
/*
Instruction memory coherence checking.
For new instruction executed in the pipeline - ensure it matches
what is in the main program memory. Perform MMU translations if
it is enabled.
*/
reg [31:0] mem_word;
reg [31:0] last_addr = 0;
reg [31:0] last_mem_word;
reg [31:0] physical_pc;
reg tlb_miss;
`ifdef MEM_COHERENCE_CHECK
`define MEM_COHERENCE_TRIGGER (`OR1200_TOP.`CPU_cpu.`CPU_ctrl.id_void === 1'b0)
`define INSN_TO_CHECK `OR1200_TOP.`CPU_cpu.`CPU_ctrl.id_insn
`define PC_TO_CHECK `OR1200_TOP.`CPU_cpu.`CPU_except.id_pc
// Check instruction in decode stage is what is in the RAM
always @(posedge `CPU_CORE_CLK)
begin
if (`MEM_COHERENCE_TRIGGER)
begin
check_for_immu_entry(`PC_TO_CHECK, physical_pc, tlb_miss);
// Check if it's a new PC - will also get triggered if the
// instruction has changed since we last checked it
if (((physical_pc !== last_addr) ||
(last_mem_word != `INSN_TO_CHECK)) & !tlb_miss)
begin
// Decode stage not void, check instruction
// get PC
get_insn_from_memory(physical_pc, mem_word);
if (mem_word !== `INSN_TO_CHECK)
begin
$fdisplay(fgeneral, "%t: Instruction mismatch for PC 0x%h (phys. 0x%h) - memory had 0x%h, CPU had 0x%h",
$time, `PC_TO_CHECK, physical_pc, mem_word,
`INSN_TO_CHECK);
$display("%t: Instruction mismatch for PC 0x%h (phys. 0x%h) - memory had 0x%h, CPU had 0x%h",
$time, `PC_TO_CHECK, physical_pc, mem_word,
`INSN_TO_CHECK);
#200;
$finish;
end
last_addr = physical_pc;
last_mem_word = mem_word;
end // if (((physical_pc !== last_addr) || (last_mem_word != `INSN_TO_CHECK))...
end // if (`MEM_COHERENCE_TRIGGER)
end // always @ (posedge `CPU_CORE_CLK)
`endif // `ifdef MEM_COHERENCE_CHECK
// Trigger on each instruction that gets into writeback stage properly
reg exception_coming1, exception_coming2, exception_here;
reg will_jump, jumping, jump_dslot, jumped;
reg rfe, except_during_rfe;
reg dslot_expt;
// Maintain a copy of GPRS for previous instruction
reg [31:0] current_gprs [0:31];
reg [31:0] current_epcr, current_eear, current_esr, current_sr;
reg [31:0] previous_gprs [0:31];
reg [31:0] previous_epcr;
reg [31:0] previous_eear;
reg [31:0] previous_esr;
reg [31:0] previous_sr;
task update_current_gprs;
integer j;
begin
for(j=0;j<32;j=j+1)
begin
get_gpr(j,current_gprs[j]);
end
current_sr = `OR1200_TOP.`CPU_cpu.`CPU_sprs.sr ;
current_esr = `OR1200_TOP.`CPU_cpu.`CPU_sprs.epcr ;
current_epcr = `OR1200_TOP.`CPU_cpu.`CPU_sprs.epcr ;
current_eear = `OR1200_TOP.`CPU_cpu.`CPU_sprs.eear ;
end
endtask
task update_previous_gprs;
integer j;
begin
for(j=0;j<32;j=j+1)
begin
previous_gprs[j] = current_gprs[j];
end
previous_sr = current_sr;
previous_esr = current_esr;
previous_epcr = current_epcr;
previous_eear = current_eear;
end
endtask // update_previous_gprs
// Maintain a list of addresses we expect the processor to execute
// Whenever we hit a branch or jump or rfe we add to this list - when we
// execute it then we remove it from the list.
reg [31:0] expected_addresses [0:31];
reg expected_addresses_waiting [0:31]; // List indicating if address is waiting
reg duplicate_expected_addresses_waiting [0:31]; // List indicating if a waiting address will be cleared by the single return
integer expected_address_num;
// Initialise things on reset
always @(`OR1200_TOP.iwb_rst_i)
begin
for (expected_address_num=0;expected_address_num<32;expected_address_num=expected_address_num+1)
begin
expected_addresses_waiting[expected_address_num] = 0;
duplicate_expected_addresses_waiting[expected_address_num] = 0;
end
expected_address_num = 0;
end
task add_expected_address;
input [31:0] expected_pc;
begin
if (expected_address_num == 31)
begin
$display("%t: Too many branches not reached",$time);
#100;
$finish;
end
if (expected_addresses_waiting[expected_address_num])
begin
$display("%t: expected_addresses tracker bugged out. expected_address_num = %0d",$time,expected_address_num);
#100;
$finish;
end
else
begin
`ifdef OR1200_MONITOR_JUMPTRACK_DEBUG_OUTPUT
// Debugging output...
$display("%t: Adding address 0x%h to expected list index %0d",$time, expected_pc,expected_address_num);
`endif
// Put the expected PC in the list, increase the index
expected_addresses[expected_address_num] = expected_pc;
expected_addresses_waiting[expected_address_num] = 1;
expected_address_num = expected_address_num + 1;
end // else: !if(expected_addresses_waiting[expected_address_num])
end
endtask // add_address_to_expect
// Use this in the case that there's an execption after a jump, in which
// case we'll have two entries when we finally jump back (the one the
// original jump put in, and the one put in by the l.rfe or l.jr/ when
// returning outside of exception handler), so mark this one as OK for
// removing the duplicate of
task mark_duplicate_expected_address;
begin
// This will always be done on the first instruction of an exception
// that has occured after a delay slot instruction, so
// expected_address_num will be one past the entry for the one we will
// get a duplicate return call for
duplicate_expected_addresses_waiting[expected_address_num-1] = 1;
end
endtask // mark_duplicate_expected_address
task check_expected_address;
input [31:0] pc;
input expecting_hit;
integer i,j;
reg hit;
reg duplicates;
begin
hit = 0;
//$display("%t: check_expected_addr 0x%h, index %0d",
// $time,pc, expected_address_num);
if (expected_address_num > 0)
begin
// First check the last jump we did
if (expected_addresses[expected_address_num-1] == pc)
begin
// Jump address hit
// Debugging printout:
`ifdef OR1200_MONITOR_JUMPTRACK_DEBUG_OUTPUT
$display("%t: PC address 0x%h was in expected list, index %0d",$time, pc,expected_address_num-1);
`endif
expected_address_num = expected_address_num-1;
expected_addresses_waiting[expected_address_num] = 0;
hit = 1;
end
else
begin
// Check through the list
for(i=0;i<expected_address_num;i=i+1)
begin
if (expected_addresses[i] == pc)
begin
// Jump address hit
// Debugging printout:
`ifdef OR1200_MONITOR_JUMPTRACK_DEBUG_OUTPUT
$display("%t: PC address 0x%h was in expected list, index %0d",$time, pc,i);
`endif
for(j=i;j<expected_address_num;j=j+1)
begin
// Pull all of the ones above us down one
expected_addresses_waiting[j]
= expected_addresses_waiting[j+1];
expected_addresses[j]
= expected_addresses[j+1];
duplicate_expected_addresses_waiting[j]
= duplicate_expected_addresses_waiting[j+1];
end
expected_address_num = expected_address_num-1;
hit = 1;
// quit out. only allow 1 hit
i = expected_address_num;
end
end
end // else: !if(expected_addresses[expected_ad...
end // if (expected_address_num > 0)
// Check for duplicates this way because of the way we've declared
// the array...
duplicates=0;
for(i=0;i<32;i=i+1)
duplicates = duplicates | duplicate_expected_addresses_waiting[i];
if (hit & duplicates)
begin
// If we got a hit, check for duplicates we're also meant to clear
`ifdef OR1200_MONITOR_JUMPTRACK_DEBUG_OUTPUT
$display;
`endif
for(i=0;i<expected_address_num;i=i+1)
begin
if(duplicate_expected_addresses_waiting[i] &
expected_addresses_waiting[i] &
expected_addresses[i] == pc)
begin
// Found a duplicate call address, clear it
duplicate_expected_addresses_waiting[i] = 0;
expected_addresses_waiting[i] = 0;
// Now reorder the list - pull all the ones above us
// down by one
for(j=i;j<expected_address_num;j=j+1)
begin
expected_addresses_waiting[j] = expected_addresses_waiting[j+1];
expected_addresses[j] = expected_addresses[j+1];
duplicate_expected_addresses_waiting[j] = duplicate_expected_addresses_waiting[j+1];
end
expected_address_num = expected_address_num - 1;
end
end // for (i=0;i<expected_address_num;i=i+1)
end // if (hit & duplicates)
if (expecting_hit & !hit)
begin
// Expected this address to be one we're supposed to jump to, but it wasn't!
$display("%t: Failed to find current PC, 0x%h, in expected PCs for branches/jumps",$time,pc);
#100;
$finish;
end
end
endtask // check_expected_address
// Task to assert value of GPR
task assert_gpr_val;
input [5:0] regnum;
input [31:0] assert_value;
input [31:0] pc;
reg [31:0] reg_val;
begin
get_gpr(regnum, reg_val);
if (reg_val !== assert_value)
begin
$display("%t: Assert r%0d value (0x%h) = 0x%h failed. pc=0x%h",
$time, regnum, reg_val, assert_value,pc);
#100;
$finish;
end
end
endtask // assert_gpr_val
// Task to assert something is true
task assert_this;
input assert_result;
input [31:0] pc;
begin
if (!assert_result)
begin
$display("%t: Assert failed for instruction at pc=0x%h",
$time , pc);
#100;
$finish;
end
end
endtask // assert_gpr_val
// The jumping variable doesn't get updated until we do the proper check of
// the current instruction reaching the writeback stage. We need to know
// earlier, eg. in the exception checking part, if this instruction will
// jump. We do that with this task.
task check_for_jump;
input [31:0] insn;
reg [5:0] opcode;
reg flag;
begin
opcode = insn[`OR1K_OPCODE_POS];
// Use the flag from the previous instruction, as the decision
// is made in the execute stage not in te writeback stage,
// which is where we're getting our instructions.
flag = previous_sr[`OR1200_SR_F];
case (opcode)
`OR1200_OR32_J,
`OR1200_OR32_JR,
`OR1200_OR32_JAL,
`OR1200_OR32_JALR:
will_jump = 1;
`OR1200_OR32_BNF:
will_jump = !flag;
`OR1200_OR32_BF:
will_jump = flag;
default:
will_jump = 0;
endcase // case (opcode)
end
endtask // check_for_jump
// Detect exceptions from the processor here
reg [13:0] except_trig_r;
reg exception_coming;
always @(posedge `CPU_CORE_CLK)
if (`OR1200_TOP.iwb_rst_i)
begin
except_trig_r = 0;
exception_coming = 0;
except_during_rfe = 0;
end
else if ((|`OR1200_TOP.`CPU_cpu.`CPU_except.except_trig) && !exception_coming)
begin
exception_coming = 1;
except_trig_r = `OR1200_TOP.`CPU_cpu.`CPU_except.except_trig;
except_during_rfe = rfe;
end
task check_incoming_exceptions;
begin
// Exception timing - depends on the trigger.
// Appears to be:
// tick timer - dslot - 1 instruction delay, else 2
// tlb lookasides - 1 instruction for both
casex (except_trig_r)
13'b1_xxxx_xxxx_xxxx: begin
//except_type <= #1 `OR1200_EXCEPT_TICK;
exception_here = exception_coming2;
exception_coming2 = jump_dslot ? exception_coming: exception_coming1 ;
exception_coming1 = jump_dslot ? 0 : exception_coming;
end
13'b0_1xxx_xxxx_xxxx: begin
//except_type <= #1 `OR1200_EXCEPT_INT;
#1;
end
13'b0_01xx_xxxx_xxxx: begin
//except_type <= #1 `OR1200_EXCEPT_ITLBMISS;
exception_here = exception_coming2;
exception_coming2 = jump_dslot ? exception_coming : exception_coming1 ;
exception_coming1 = jump_dslot ? 0 : exception_coming;
end
13'b0_001x_xxxx_xxxx: begin
//except_type <= #1 `OR1200_EXCEPT_IPF;
exception_here = exception_coming2;
exception_coming2 = jump_dslot ? exception_coming : exception_coming1 ;
exception_coming1 = jump_dslot ? 0 : exception_coming;
end
13'b0_0001_xxxx_xxxx: begin
//except_type <= #1 `OR1200_EXCEPT_BUSERR;
exception_here = exception_coming;
exception_coming2 = 0;
exception_coming1 = 0;
end
13'b0_0000_1xxx_xxxx: begin
//except_type <= #1 `OR1200_EXCEPT_ILLEGAL;
if (will_jump)
begin
// Writeback stage instruction will jump, and we have an
// illegal instruction in the decode/execute stage, which is
// the delay slot, so indicate the exception is coming...
exception_here = exception_coming2;
exception_coming2 = exception_coming;
exception_coming1 = 0;
end
else
begin
exception_here = jump_dslot ?
exception_coming2 : exception_coming;
exception_coming2 = jump_dslot ? exception_coming : 0;
exception_coming1 = 0;
end
end
13'b0_0000_01xx_xxxx: begin
//except_type <= #1 `OR1200_EXCEPT_ALIGN;
if(will_jump)
begin
exception_here = exception_coming2;
exception_coming2 = exception_coming;
exception_coming1 = 0;
end
else
begin
exception_here = (rfe) ? exception_coming : exception_coming2;
exception_coming2 = (rfe) ? 0 : exception_coming;
exception_coming1 = 0;
end
end
13'b0_0000_001x_xxxx: begin
//except_type <= #1 `OR1200_EXCEPT_DTLBMISS;
// Looks like except_trig goes high here after we check the
// instruction before the itlb miss after a delay slot, so we
// miss the dslot variable (it gets propegated before we call
// this task) so we use the jumped variable here to see if we
// are an exception after a delay slot
//exception_here = (jumped | rfe) ? exception_coming : exception_coming2 ;
//exception_coming2 = (jumped | rfe) ? 0 : exception_coming;
exception_here = (jumped | rfe) ? exception_coming : exception_coming2 ;
exception_coming2 = (jumped | rfe) ? 0 : exception_coming;
exception_coming1 = 0;
end
13'b0_0000_0001_xxxx: begin
//except_type <= #1 `OR1200_EXCEPT_DPF;
if (jumped) begin // Jumped onto illegal instruction
exception_here = exception_coming ;
exception_coming2 = 0;
exception_coming1 = 0;
end
else begin
exception_here = exception_coming2;
exception_coming2 = exception_coming;
exception_coming1 = 0;
end
end
13'b0_0000_0000_1xxx: begin // Data Bus Error
//except_type <= #1 `OR1200_EXCEPT_BUSERR;
exception_here = exception_coming2 ;
exception_coming2 = exception_coming;
exception_coming1 = 0;
end
13'b0_0000_0000_01xx: begin
//except_type <= #1 `OR1200_EXCEPT_RANGE;
#1;
end
13'b0_0000_0000_001x: begin
// trap
#1;
end
13'b0_0000_0000_0001: begin
//except_type <= #1 `OR1200_EXCEPT_SYSCALL;
exception_here = exception_coming2;
exception_coming2 = jumped ? exception_coming: exception_coming1 ;
exception_coming1 = jumped ? 0 : exception_coming;
end
endcase // casex (except_trig_r)
exception_coming = 0;
except_during_rfe = 0;
end
endtask // check_incoming_exceptions
/////////////////////////////////////////////////////////////////////////
// Execution tracking task
/////////////////////////////////////////////////////////////////////////
`ifdef OR1200_SYSTEM_CHECKER
always @(posedge `CPU_CORE_CLK)
begin
if (`OR1200_TOP.iwb_rst_i)
begin
exception_coming1 = 0;exception_coming2 = 0;exception_here= 0;
jumping = 0; jump_dslot = 0; jumped = 0;
rfe = 0;
end
if (!`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_freeze) begin
//#2 ;
// If instruction isn't a l.nop with bit 16 set (implementation's
// filler instruction in pipeline), and do not have an exception
// signaled with a dslot instruction in the execute stage
if (((`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn[`OR1K_OPCODE_POS] !=
`OR1200_OR32_NOP) || !`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn[16])
&& !(`OR1200_TOP.`CPU_cpu.`CPU_except.except_flushpipe &&
`OR1200_TOP.`CPU_cpu.`CPU_except.ex_dslot)) // and not except start
begin
// Propegate jump-tracking variables
// If was exception in delay slot, we didn't actually jump
// so don't set jumped in this case.
jumped = exception_here ? 0 : jump_dslot;
jump_dslot = jumping;
jumping = 0;
rfe = 0;
// Now, check if current instruction will jump/branch, this is
// needed by the exception checking code, sets will_jump=1
check_for_jump(`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn);
// Now check if it's an exception this instruction
check_incoming_exceptions;
// Case where we just went to an exception after a jump, so we
// mark the address we were meant to jump to as a place which will
// have duplicate return entries in the expected address list
if (exception_here & (jumped | jump_dslot))
begin
$display("%t: marked as jump address with exception (dup)"
,$time);
mark_duplicate_expected_address;
end
or1200_check_execution(`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn,
`OR1200_TOP.`CPU_cpu.`CPU_except.wb_pc,
exception_here);
//$write("%t: pc:0x%h\t",$time,
// `OR1200_TOP.`CPU_cpu.`CPU_except.wb_pc);
// Decode the instruction, print it out
//or1200_print_op(`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn);
//$write("\t exc:%0h dsl:%0h\n",exception_here,jump_dslot);
end
end // if (!`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_freeze)
end // always @ (posedge `CPU_CORE_CLK)
`endif
task or1200_check_execution;
input [31:0] insn;
input [31:0] pc;
input exception;
reg [5:0] opcode;
reg [25:0] j_imm;
reg [25:0] br_imm;
reg [4:0] rD_num, rA_num, rB_num;
reg [31:0] rD_val, rA_val, rB_val;
reg [15:0] imm_16bit;
reg [15:0] mtspr_imm;
reg [3:0] alu_op;
reg [1:0] shrot_op;
reg [5:0] shroti_imm;
reg [5:0] sf_op;
reg [5:0] xsync_op;
reg flag;
reg [31:0] br_j_ea; // Branch/jump effective address
begin
// Instruction opcode
opcode = insn[`OR1K_OPCODE_POS];
// Immediates for jump or branch instructions
j_imm = insn[`OR1K_J_BR_IMM_POS];
br_imm = insn[`OR1K_J_BR_IMM_POS];
// Register numbers (D, A and B)
rD_num = insn[`OR1K_RD_POS];
rA_num = insn[`OR1K_RA_POS];
rB_num = insn[`OR1K_RB_POS];
// Bottom 16 bits when used as immediates in various instructions
imm_16bit = insn[15:0];
// 16-bit immediate for mtspr instructions
mtspr_imm = {insn[25:21],insn[10:0]};
// ALU op for ALU instructions
alu_op = insn[`OR1K_ALU_OP_POS];
// Shift-rotate op for SHROT ALU instructions
shrot_op = insn[`OR1K_SHROT_OP_POS];
shroti_imm = insn[`OR1K_SHROTI_IMM_POS];
// Set flag op
sf_op = insn[`OR1K_SF_OP];
// Xsync/syscall/trap opcode
xsync_op = insn[`OR1K_XSYNC_OP_POS];
// Use the flag from the previous instruction, as the decision
// is made in the execute stage not in te writeback stage,
// which is where we're getting our instructions.
flag = previous_sr[`OR1200_SR_F];
update_current_gprs;
// Check MSbit of the immediate, sign extend if set
br_j_ea = j_imm[25] ? pc + {4'hf,j_imm,2'b00} :
pc + {4'h0,j_imm,2'b00};
if (exception)
begin
$display("%t: exception - at 0x%x",$time, pc);
// get epcr, put it in the addresses we expect to jump
// back to
// Maybe DON'T do this. Because maybe in linux things we
// interrupt out of, we don't want to execute them again?
//add_expected_address(current_epcr);
end
check_expected_address(pc, (jumped & !exception));
rfe = 0;
case (opcode)
`OR1200_OR32_J:
begin
//
// PC < - exts(Immediate < < 2) + JumpInsnAddr
//
//The immediate value is shifted left two bits, sign-extended
// to program counter width, and then added to the address of
// the jump instruction. The result is the effective address
// of the jump. The program unconditionally jumps to EA with
// a delay of one instruction.
add_expected_address(br_j_ea);
jumping = 1;
end
`OR1200_OR32_JAL:
begin
//
//PC < - exts(Immediate < < 2) + JumpInsnAddr
//LR < - DelayInsnAddr + 4
//
// Link reg is r9, check it is PC+8
//
add_expected_address(br_j_ea);
assert_gpr_val(9, pc+8, pc);
jumping = 1; //
end
`OR1200_OR32_BNF:
begin
//EA < - exts(Immediate < < 2) + BranchInsnAddr
//PC < - EA if SR[F] cleared
if (!flag)
begin
add_expected_address(br_j_ea);
jumping = 1;
end
end
`OR1200_OR32_BF:
begin
//EA < - exts(Immediate < < 2) + BranchInsnAddr
//PC < - EA if SR[F] set
if (flag)
begin
add_expected_address(br_j_ea);
jumping = 1;
end
end
`OR1200_OR32_RFE:
begin
add_expected_address(current_epcr);
// jumping variable keeps track of jumps/branches with delay
// slot - there is none for l.rfe
rfe = 1;
end
`OR1200_OR32_JR:
begin
//PC < - rB
get_gpr(rB_num, rB_val);
add_expected_address(rB_val);
jumping = 1;
end
`OR1200_OR32_JALR:
begin
//PC < - rB
//LR < - DelayInsnAddr + 4
get_gpr(rB_num, rB_val);
add_expected_address(rB_val);
assert_gpr_val(9, pc+8, pc);
jumping = 1;
end
/*
`OR1200_OR32_LWZ,
`OR1200_OR32_LBZ,
`OR1200_OR32_LBS,
`OR1200_OR32_LHZ,
`OR1200_OR32_LHS,
`OR1200_OR32_SW,
`OR1200_OR32_SB,
`OR1200_OR32_SH:
begin
// Should result in databus access if data cache disabled
$display("%t: lsu instruction",$time);
end
`OR1200_OR32_MFSPR,
`OR1200_OR32_MTSPR:
begin
// Confirm RF values end up in the correct SPR
$display("%t: mxspr",$time);
end
`OR1200_OR32_MOVHI,
`OR1200_OR32_ADDI,
`OR1200_OR32_ADDIC,
`OR1200_OR32_ANDI,
`OR1200_OR32_ORI,
`OR1200_OR32_XORI,
`OR1200_OR32_MULI,
`OR1200_OR32_ALU:
begin
// Double check operations done on RF and immediate values
$display("%t: ALU op",$time);
end
`OR1200_OR32_SH_ROTI:
begin
// Rotate according to immediate - maybe should be in ALU ops
$display("%t: rotate op",$time);
end
`OR1200_OR32_SFXXI,
`OR1200_OR32_SFXX:
begin
// Set flag - do the check oursevles, check flag
$display("%t: set flag op",$time);
end
`OR1200_OR32_MACI,
`OR1200_OR32_MACMSB:
begin
// Either, multiply signed and accumulate, l.mac
// or multiply signed and subtract, l.msb
$display("%t: MAC op",$time);
end
*/
/*default:
begin
$display("%t: Unknown opcode 0x%h at pc 0x%x\n",
$time,opcode, pc);
end
*/
endcase // case (opcode)
update_previous_gprs;
end
endtask // or1200_check_execution
/////////////////////////////////////////////////////////////////////////
// Instruction decode task
/////////////////////////////////////////////////////////////////////////
task or1200_print_op;
input [31:0] insn;
reg [5:0] opcode;
reg [25:0] j_imm;
reg [25:0] br_imm;
reg [4:0] rD_num, rA_num, rB_num;
reg [31:0] rA_val, rB_val;
reg [15:0] imm_16bit;
reg [10:0] imm_split16bit;
reg [3:0] alu_op;
reg [1:0] shrot_op;
reg [5:0] shroti_imm;
reg [5:0] sf_op;
reg [5:0] xsync_op;
begin
// Instruction opcode
opcode = insn[`OR1K_OPCODE_POS];
// Immediates for jump or branch instructions
j_imm = insn[`OR1K_J_BR_IMM_POS];
br_imm = insn[`OR1K_J_BR_IMM_POS];
// Register numbers (D, A and B)
rD_num = insn[`OR1K_RD_POS];
rA_num = insn[`OR1K_RA_POS];
rB_num = insn[`OR1K_RB_POS];
// Bottom 16 bits when used as immediates in various instructions
imm_16bit = insn[15:0];
// Bottom 11 bits used as immediates for l.sX instructions
// Split 16-bit immediate for l.mtspr/l.sX instructions
imm_split16bit = {insn[25:21],insn[10:0]};
// ALU op for ALU instructions
alu_op = insn[`OR1K_ALU_OP_POS];
// Shift-rotate op for SHROT ALU instructions
shrot_op = insn[`OR1K_SHROT_OP_POS];
shroti_imm = insn[`OR1K_SHROTI_IMM_POS];
// Set flag op
sf_op = insn[`OR1K_SF_OP];
// Xsync/syscall/trap opcode
xsync_op = insn[`OR1K_XSYNC_OP_POS];
case (opcode)
`OR1200_OR32_J:
begin
$fwrite(finsn,"l.j 0x%h", {j_imm,2'b00});
end
`OR1200_OR32_JAL:
begin
$fwrite(finsn,"l.jal 0x%h", {j_imm,2'b00});
end
`OR1200_OR32_BNF:
begin
$fwrite(finsn,"l.bnf 0x%h", {br_imm,2'b00});
end
`OR1200_OR32_BF:
begin
$fwrite(finsn,"l.bf 0x%h", {br_imm,2'b00});
end
`OR1200_OR32_RFE:
begin
$fwrite(finsn,"l.rfe");
end
`OR1200_OR32_JR:
begin
$fwrite(finsn,"l.jr r%0d",rB_num);
end
`OR1200_OR32_JALR:
begin
$fwrite(finsn,"l.jalr r%0d",rB_num);
end
`OR1200_OR32_LWZ:
begin
$fwrite(finsn,"l.lwz r%0d,0x%0h(r%0d)",rD_num,imm_16bit,rA_num);
end
`OR1200_OR32_LBZ:
begin
$fwrite(finsn,"l.lbz r%0d,0x%0h(r%0d)",rD_num,imm_16bit,rA_num);
end
`OR1200_OR32_LBS:
begin
$fwrite(finsn,"l.lbs r%0d,0x%0h(r%0d)",rD_num,imm_16bit,rA_num);
end
`OR1200_OR32_LHZ:
begin
$fwrite(finsn,"l.lhz r%0d,0x%0h(r%0d)",rD_num,imm_16bit,rA_num);
end
`OR1200_OR32_LHS:
begin
$fwrite(finsn,"l.lhs r%0d,0x%0h(r%0d)",rD_num,imm_16bit,rA_num);
end
`OR1200_OR32_SW:
begin
$fwrite(finsn,"l.sw 0x%0h(r%0d),r%0d",imm_split16bit,rA_num,rB_num);
end
`OR1200_OR32_SB:
begin
$fwrite(finsn,"l.sb 0x%0h(r%0d),r%0d",imm_split16bit,rA_num,rB_num);
end
`OR1200_OR32_SH:
begin
$fwrite(finsn,"l.sh 0x%0h(r%0d),r%0d",imm_split16bit,rA_num,rB_num);
end
`OR1200_OR32_MFSPR:
begin
$fwrite(finsn,"l.mfspr r%0d,r%0d,0x%h",rD_num,rA_num,imm_16bit,);
end
`OR1200_OR32_MTSPR:
begin
$fwrite(finsn,"l.mtspr r%0d,r%0d,0x%h",rA_num,rB_num,imm_split16bit);
end
`OR1200_OR32_MOVHI:
begin
if (!insn[16])
$fwrite(finsn,"l.movhi r%0d,0x%h",rD_num,imm_16bit);
else
$fwrite(finsn,"l.macrc r%0d",rD_num);
end
`OR1200_OR32_ADDI:
begin
$fwrite(finsn,"l.addi r%0d,r%0d,0x%h",rD_num,rA_num,imm_16bit);
end
`OR1200_OR32_ADDIC:
begin
$fwrite(finsn,"l.addic r%0d,r%0d,0x%h",rD_num,rA_num,imm_16bit);
end
`OR1200_OR32_ANDI:
begin
$fwrite(finsn,"l.andi r%0d,r%0d,0x%h",rD_num,rA_num,imm_16bit);
end
`OR1200_OR32_ORI:
begin
$fwrite(finsn,"l.ori r%0d,r%0d,0x%h",rD_num,rA_num,imm_16bit);
end
`OR1200_OR32_XORI:
begin
$fwrite(finsn,"l.xori r%0d,r%0d,0x%h",rD_num,rA_num,imm_16bit);
end
`OR1200_OR32_MULI:
begin
$fwrite(finsn,"l.muli r%0d,r%0d,0x%h",rD_num,rA_num,imm_16bit);
end
`OR1200_OR32_ALU:
begin
case(alu_op)
`OR1200_ALUOP_ADD:
$fwrite(finsn,"l.add ");
`OR1200_ALUOP_ADDC:
$fwrite(finsn,"l.addc ");
`OR1200_ALUOP_SUB:
$fwrite(finsn,"l.sub ");
`OR1200_ALUOP_AND:
$fwrite(finsn,"l.and ");
`OR1200_ALUOP_OR:
$fwrite(finsn,"l.or ");
`OR1200_ALUOP_XOR:
$fwrite(finsn,"l.xor ");
`OR1200_ALUOP_MUL:
$fwrite(finsn,"l.mul ");
`OR1200_ALUOP_SHROT:
begin
case(shrot_op)
`OR1200_SHROTOP_SLL:
$fwrite(finsn,"l.sll ");
`OR1200_SHROTOP_SRL:
$fwrite(finsn,"l.srl ");
`OR1200_SHROTOP_SRA:
$fwrite(finsn,"l.sra ");
`OR1200_SHROTOP_ROR:
$fwrite(finsn,"l.ror ");
endcase // case (shrot_op)
end
`OR1200_ALUOP_DIV:
$fwrite(finsn,"l.div ");
`OR1200_ALUOP_DIVU:
$fwrite(finsn,"l.divu ");
`OR1200_ALUOP_CMOV:
$fwrite(finsn,"l.cmov ");
endcase // case (alu_op)
$fwrite(finsn,"r%0d,r%0d,r%0d",rD_num,rA_num,rB_num);
end
`OR1200_OR32_SH_ROTI:
begin
case(shrot_op)
`OR1200_SHROTOP_SLL:
$fwrite(finsn,"l.slli ");
`OR1200_SHROTOP_SRL:
$fwrite(finsn,"l.srli ");
`OR1200_SHROTOP_SRA:
$fwrite(finsn,"l.srai ");
`OR1200_SHROTOP_ROR:
$fwrite(finsn,"l.rori ");
endcase // case (shrot_op)
$fwrite(finsn,"r%0d,r%0d,0x%h",rD_num,rA_num,shroti_imm);
end
`OR1200_OR32_SFXXI:
begin
case(sf_op[2:0])
`OR1200_COP_SFEQ:
$fwrite(finsn,"l.sfeqi ");
`OR1200_COP_SFNE:
$fwrite(finsn,"l.sfnei ");
`OR1200_COP_SFGT:
begin
if (sf_op[`OR1200_SIGNED_COMPARE])
$fwrite(finsn,"l.sfgtsi ");
else
$fwrite(finsn,"l.sfgtui ");
end
`OR1200_COP_SFGE:
begin
if (sf_op[`OR1200_SIGNED_COMPARE])
$fwrite(finsn,"l.sfgesi ");
else
$fwrite(finsn,"l.sfgeui ");
end
`OR1200_COP_SFLT:
begin
if (sf_op[`OR1200_SIGNED_COMPARE])
$fwrite(finsn,"l.sfltsi ");
else
$fwrite(finsn,"l.sfltui ");
end
`OR1200_COP_SFLE:
begin
if (sf_op[`OR1200_SIGNED_COMPARE])
$fwrite(finsn,"l.sflesi ");
else
$fwrite(finsn,"l.sfleui ");
end
endcase // case (sf_op[2:0])
$fwrite(finsn,"r%0d,0x%h",rA_num, imm_16bit);
end // case: `OR1200_OR32_SFXXI
`OR1200_OR32_SFXX:
begin
case(sf_op[2:0])
`OR1200_COP_SFEQ:
$fwrite(finsn,"l.sfeq ");
`OR1200_COP_SFNE:
$fwrite(finsn,"l.sfne ");
`OR1200_COP_SFGT:
begin
if (sf_op[`OR1200_SIGNED_COMPARE])
$fwrite(finsn,"l.sfgts ");
else
$fwrite(finsn,"l.sfgtu ");
end
`OR1200_COP_SFGE:
begin
if (sf_op[`OR1200_SIGNED_COMPARE])
$fwrite(finsn,"l.sfges ");
else
$fwrite(finsn,"l.sfgeu ");
end
`OR1200_COP_SFLT:
begin
if (sf_op[`OR1200_SIGNED_COMPARE])
$fwrite(finsn,"l.sflts ");
else
$fwrite(finsn,"l.sfltu ");
end
`OR1200_COP_SFLE:
begin
if (sf_op[`OR1200_SIGNED_COMPARE])
$fwrite(finsn,"l.sfles ");
else
$fwrite(finsn,"l.sfleu ");
end
endcase // case (sf_op[2:0])
$fwrite(finsn,"r%0d,r%0d",rA_num, rB_num);
end
`OR1200_OR32_MACI:
begin
$fwrite(finsn,"l.maci r%0d,0x%h",rA_num,imm_16bit);
end
`OR1200_OR32_MACMSB:
begin
if(insn[3:0] == 4'h1)
$fwrite(finsn,"l.mac ");
else if(insn[3:0] == 4'h2)
$fwrite(finsn,"l.msb ");
$fwrite(finsn,"r%0d,r%0d",rA_num,rB_num);
end
`OR1200_OR32_NOP:
begin
$fwrite(finsn,"l.nop 0x%0h",imm_16bit);
end
`OR1200_OR32_XSYNC:
begin
case (xsync_op)
5'd0:
$fwrite(finsn,"l.sys 0x%h",imm_16bit);
5'd8:
$fwrite(finsn,"l.trap 0x%h",imm_16bit);
5'd16:
$fwrite(finsn,"l.msync");
5'd20:
$fwrite(finsn,"l.psync");
5'd24:
$fwrite(finsn,"l.csync");
default:
begin
$display("%t: Instruction with opcode 0x%h has bad specific type information: 0x%h",$time,opcode,insn);
$fwrite(finsn,"%t: Instruction with opcode 0x%h has has bad specific type information: 0x%h",$time,opcode,insn);
end
endcase // case (xsync_op)
end
default:
begin
$display("%t: Unknown opcode 0x%h",$time,opcode);
$fwrite(finsn,"%t: Unknown opcode 0x%h",$time,opcode);
end
endcase // case (opcode)
end
endtask // or1200_print_op
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__XNOR3_PP_SYMBOL_V
`define SKY130_FD_SC_MS__XNOR3_PP_SYMBOL_V
/**
* xnor3: 3-input exclusive NOR.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__xnor3 (
//# {{data|Data Signals}}
input A ,
input B ,
input C ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__XNOR3_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__AND2_2_V
`define SKY130_FD_SC_MS__AND2_2_V
/**
* and2: 2-input AND.
*
* Verilog wrapper for and2 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__and2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__and2_2 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__and2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__and2_2 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__and2 base (
.X(X),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__AND2_2_V
|
`include "instr_decode_defines.vh"
module instr_decoder (
input [31:0] instr,
input [31:0] pc_in ,
output use_rsj ,
output use_rsk ,
output use_rsd ,
output [1:0] rsd_lockout ,
output [`ALU_FUNCT_W-1:0] alu_funct ,
output alu_sel_a ,
output alu_sel_b ,
output [31:0] alu_immed_a ,
output [31:0] alu_immed_b ,
output [`BR_FUNCT_W-1:0] br_funct ,
output br_sel_a ,
output [31:0] br_immed_a ,
output [31:0] br_immed_b ,
output [`MEM_FUNCT_W-1:0] mem_funct
);
//To decode the instruciton this module will create a packed array for each
//opcode and then select and unpack that array to drive the outputs
localparam PK_REG_W = (1 + 1 + 1 + 1);
localparam PK_ALU_W = (`ALU_FUNCT_W + 1 + 1 + 32 + 32);
localparam PK_BR_W = (`BR_FUNCT_W + 1 + 32 + 32);
localparam PK_MEM_W = (`MEM_FUNCT_W);
//TODO these are wrong
localparam PK_ILLEGAL_OFFSET = PK_REG_OFFSET + PK_REG_W;
localparam PK_REG_OFFSET = PK_ALU_OFFSET + PK_ALU_W;
localparam PK_ALU_OFFSET = PK_BR_OFFSET + PK_BR_W;
localparam PK_BR_OFFSET = PK_MEM_OFFSET + PK_MEM_W;
localparam PK_MEM_OFFSET = 0;
localparam PK_DATA_W = 1 + PK_REG_W + PK_ALU_W + PK_BR_W + PK_MEM_W;
localparam OPCODE_IMM = 7'b0010011;
localparam OPCODE_LUI = 7'b0110111;
localparam OPCODE_AUIPC = 7'b0010111;
localparam OPCODE_OP = 7'b0110011;
localparam OPCODE_JAL = 7'b1101111;
localparam OPCODE_JALR = 7'b1100111;
localparam OPCODE_BRANCH = 7'b1100011;
localparam OPCODE_LOAD = 7'b0000011;
localparam OPCODE_STORE = 7'b0100011;
localparam OPCODE_MISC_MEM = 7'b0001111;
localparam OPCODE_SYSTEM = 7'b1110011;
//Functions
//ALU
localparam INSTR_ADD = 10'b0000000000;
localparam INSTR_SUB = 10'b0100000000;
localparam INSTR_OR = 10'b0000000110;
localparam INSTR_XOR = 10'b0000000100;
localparam INSTR_AND = 10'b0000000111;
localparam INSTR_SLT = 10'b0000000010;
localparam INSTR_SLTU = 10'b0000000011;
localparam INSTR_SLL = 10'b0000000001;
localparam INSTR_SRL = 10'b0000000101;
localparam INSTR_SRA = 10'b0100000101;
//MEM
localparam INSTR_LB = 3'b000;
localparam INSTR_LH = 3'b001;
localparam INSTR_LW = 3'b010;
localparam INSTR_LBU = 3'b100;
localparam INSTR_LHU = 3'b101;
localparam INSTR_SB = 3'b000;
localparam INSTR_SH = 3'b001;
localparam INSTR_SW = 3'b010;
//Branch
localparam INSTR_BEQ = 3'b000;
localparam INSTR_BNE = 3'b001;
localparam INSTR_BLT = 3'b100;
localparam INSTR_BGE = 3'b101;
localparam INSTR_BLTU = 3'b110;
localparam INSTR_BGEU = 3'b111;
//JALR
localparam INSTR_JALR = 3'b000;
wire [PK_REG_W-1:0] reg_imm ;
wire [PK_REG_W-1:0] reg_op ;
wire [PK_REG_W-1:0] reg_br ;
wire [PK_REG_W-1:0] reg_jal ;
wire [PK_REG_W-1:0] reg_jalr ;
wire [PK_REG_W-1:0] reg_auipc;
wire [PK_REG_W-1:0] reg_lui ;
wire [PK_REG_W-1:0] reg_load ;
wire [PK_REG_W-1:0] reg_store;
//ALU
wire [PK_ALU_W-1:0] alu_imm ;
wire [PK_ALU_W-1:0] alu_op ;
wire [PK_ALU_W-1:0] alu_br ;
wire [PK_ALU_W-1:0] alu_jal ;
wire [PK_ALU_W-1:0] alu_jalr ;
wire [PK_ALU_W-1:0] alu_auipc;
wire [PK_ALU_W-1:0] alu_lui ;
wire [PK_ALU_W-1:0] alu_load ;
wire [PK_ALU_W-1:0] alu_store;
//Branch
wire [PK_BR_W-1:0] br_imm ;
wire [PK_BR_W-1:0] br_op ;
wire [PK_BR_W-1:0] br_br ;
wire [PK_BR_W-1:0] br_jal ;
wire [PK_BR_W-1:0] br_jalr ;
wire [PK_BR_W-1:0] br_auipc ;
wire [PK_BR_W-1:0] br_lui ;
wire [PK_BR_W-1:0] br_load ;
wire [PK_BR_W-1:0] br_store ;
//Memory
wire [PK_MEM_W-1:0] mem_imm ;
wire [PK_MEM_W-1:0] mem_op ;
wire [PK_MEM_W-1:0] mem_br ;
wire [PK_MEM_W-1:0] mem_jal ;
wire [PK_MEM_W-1:0] mem_jalr ;
wire [PK_MEM_W-1:0] mem_lui ;
wire [PK_MEM_W-1:0] mem_load ;
wire [PK_MEM_W-1:0] mem_store;
//Illegal instruction decoded
wire illegal_imm ;
wire illegal_op ;
wire illegal_br ;
wire illegal_jal ;
wire illegal_jalr ;
wire illegal_lui ;
wire illegal_load ;
wire illegal_store;
wire [PK_DATA_W-1:0] decoded_packed_imm ;
wire [PK_DATA_W-1:0] decoded_packed_lui ;
wire [PK_DATA_W-1:0] decoded_packed_auipc;
wire [PK_DATA_W-1:0] decoded_packed_op ;
wire [PK_DATA_W-1:0] decoded_packed_jal ;
wire [PK_DATA_W-1:0] decoded_packed_jalr ;
wire [PK_DATA_W-1:0] decoded_packed_br ;
wire [PK_DATA_W-1:0] decoded_packed_load ;
wire [PK_DATA_W-1:0] decoded_packed_store;
reg [PK_DATA_W-1:0] decoded_packed;
reg [`ALU_FUNCT_W-1:0] alu_funct3_imm;
wire [`ALU_FUNCT_W-1:0] alu_funct_imm;
reg [`ALU_FUNCT_W-1:0] alu_funct_op;
reg [`BR_FUNCT_W-1 :0] br_funct_branch;
reg [`MEM_FUNCT_W-1:0] mem_funct_load;
reg [`MEM_FUNCT_W-1:0] mem_funct_store;
wire illegal_instruction;
wire [PK_REG_W-1:0] reg_unpk;
wire [PK_ALU_W-1:0] alu_unpk;
wire [PK_BR_W-1:0] br_unpk ;
wire [PK_MEM_W-1:0] mem_unpk;
wire sign;
wire [6:0] funct7;
wire [2:0] funct3;
wire [6:0] opcode;
wire [9:0] funct10;
wire [31:0] i_im;
wire [31:0] s_im;
wire [31:0] b_im;
wire [31:0] u_im;
wire [31:0] j_im;
assign sign = instr[31];
assign funct7 = instr[31:25];
assign funct3 = instr[14:12];
assign opcode = instr[6:0];
assign funct10 = {funct7, funct3};
assign i_im = {{20{sign}}, instr[30:20]};
assign s_im = {{20{sign}}, instr[30:25], instr[11:7]};
assign b_im = {{19{sign}}, instr[7], instr[30:25], instr[11:8], 1'b0};
assign u_im = {sign, instr[30:12], 12'b0};
assign j_im = {{11{sign}}, instr[19:12], instr[20], instr[30:21], 1'b0};
//Packed data is packed {MEM, BR, ALU, REG};
// Valids Lockout on RSD
//Register settings rsj rsk rsd rsd
assign reg_imm = {1'b1, 1'b0, 1'b1, `ALU_LOCKOUT };
assign reg_op = {1'b1, 1'b1, 1'b1, `ALU_LOCKOUT };
assign reg_br = {1'b1, 1'b1, 1'b0, `NO_LOCKOUT };
assign reg_jal = {1'b0, 1'b0, 1'b1, `ALU_LOCKOUT };
assign reg_jalr = {1'b1, 1'b0, 1'b1, `ALU_LOCKOUT };
assign reg_auipc = {1'b0, 1'b0, 1'b1, `ALU_LOCKOUT };
assign reg_lui = {1'b0, 1'b0, 1'b1, `ALU_LOCKOUT };
assign reg_load = {1'b1, 1'b0, 1'b1, `LOAD_LOCKOUT};
assign reg_store = {1'b1, 1'b1, 1'b0, `NO_LOCKOUT };
//ALU alu_funct sel_a sel_b immed_a immed_b
assign alu_imm = {alu_funct_imm, `SEL_REG, `SEL_IM, 32'b0, i_im};
assign alu_op = {alu_funct_op, `SEL_REG, `SEL_REG, 32'b0, 32'b0};
assign alu_br = {`ALU_NOP, `SEL_IM, `SEL_IM, 32'b0, 32'b0};
assign alu_jal = {`ALU_ADD, `SEL_IM, `SEL_IM, pc_in, 32'h4};
assign alu_jalr = {`ALU_ADD, `SEL_IM, `SEL_IM, pc_in, 32'h4};
assign alu_auipc = {`ALU_ADD, `SEL_IM, `SEL_IM, pc_in, u_im};
assign alu_lui = {`ALU_ADD, `SEL_IM, `SEL_IM, 32'b0, u_im};
assign alu_load = {`ALU_ADD, `SEL_REG, `SEL_IM, 32'b0, i_im};
assign alu_store = {`ALU_ADD, `SEL_REG, `SEL_IM, 32'b0, s_im};
//Branch br_funct sel_a im_a im_b
assign br_imm = {`BR_NOP, `SEL_IM, 32'b0, 32'b0};
assign br_op = {`BR_NOP, `SEL_IM, 32'b0, 32'b0};
assign br_br = {br_funct_branch, `SEL_IM, pc_in, b_im};
assign br_jal = {`BR_JUMP, `SEL_IM, pc_in, j_im};
assign br_jalr = {`BR_JUMP, `SEL_REG, 32'b0, j_im};
assign br_auipc = {`BR_NOP, `SEL_IM, 32'b0, 32'b0};
assign br_lui = {`BR_NOP, `SEL_IM, 32'b0, 32'b0};
assign br_load = {`BR_NOP, `SEL_IM, 32'b0, 32'b0};
assign br_store = {`BR_NOP, `SEL_IM, 32'b0, 32'b0};
//Memory
assign mem_imm = `MEM_NOP;
assign mem_op = `MEM_NOP;
assign mem_br = `MEM_NOP;
assign mem_jal = `MEM_NOP;
assign mem_jalr = `MEM_NOP;
assign mem_lui = `MEM_NOP;
assign mem_load = mem_funct_load;
assign mem_store = mem_funct_store;
//Decode IMM
always @ (*) begin
case (funct3)
INSTR_ADD : alu_funct3_imm = `ALU_ADD ;
INSTR_OR : alu_funct3_imm = `ALU_OR ;
INSTR_XOR : alu_funct3_imm = `ALU_XOR ;
INSTR_AND : alu_funct3_imm = `ALU_AND ;
INSTR_SLT : alu_funct3_imm = `ALU_SLT ;
INSTR_SLTU: alu_funct3_imm = `ALU_SLTU;
INSTR_SLL : alu_funct3_imm = `ALU_SLL ;
INSTR_SRL : alu_funct3_imm = `ALU_SRL ;
default : alu_funct3_imm = `ALU_NOP ;
endcase
end
assign illegal_imm = (alu_funct3_imm == `ALU_NOP) ? 1'b1 : 1'b0;
//Decode OP
always @ (*) begin
case (funct10)
INSTR_ADD : alu_funct_op = `ALU_ADD ;
INSTR_SUB : alu_funct_op = `ALU_SUB ;
INSTR_OR : alu_funct_op = `ALU_OR ;
INSTR_XOR : alu_funct_op = `ALU_XOR ;
INSTR_AND : alu_funct_op = `ALU_AND ;
INSTR_SLT : alu_funct_op = `ALU_SLT ;
INSTR_SLTU: alu_funct_op = `ALU_SLTU;
INSTR_SLL : alu_funct_op = `ALU_SLL ;
INSTR_SRL : alu_funct_op = `ALU_SRL ;
INSTR_SRA : alu_funct_op = `ALU_SRA ;
default : alu_funct_op = `ALU_NOP ;
endcase
end
assign illegal_op = (alu_funct_op == `ALU_NOP) ? 1'b1 : 1'b0;
//Special case handle SRA Immediate as immediate field is overloaded
assign alu_funct_imm = (alu_funct_op == `ALU_SRA) ? alu_funct_op : alu_funct3_imm;
//Decode branch
always @ (*) begin
case (funct3)
INSTR_BEQ : br_funct_branch = `BR_BEQ;
INSTR_BNE : br_funct_branch = `BR_BNE;
INSTR_BLT : br_funct_branch = `BR_BLT;
INSTR_BGE : br_funct_branch = `BR_BGE;
INSTR_BLTU : br_funct_branch = `BR_BLTU;
INSTR_BGEU : br_funct_branch = `BR_BGEU;
default : br_funct_branch = `BR_NOP;
endcase
end
assign illegal_br = (br_funct_branch == `BR_NOP) ? 1'b1 : 1'b0;
//Decode JALR
assign illegal_jalr = (funct3 != INSTR_JALR) ? 1'b1 : 1'b0;
//These cannot be illegal for now
assign illegal_jal = 1'b0;
assign illegal_auipc = 1'b0;
assign illegal_lui = 1'b0;
//Decode LOAD
always @ (*) begin
case (funct3)
INSTR_LB : mem_funct_load = `MEM_LB;
INSTR_LH : mem_funct_load = `MEM_LH;
INSTR_LW : mem_funct_load = `MEM_LW;
INSTR_LBU: mem_funct_load = `MEM_LBU;
INSTR_LHU: mem_funct_load = `MEM_LHU;
default : mem_funct_load = `MEM_NOP;
endcase
end
assign illegal_load = (mem_funct_load == `MEM_NOP) ? 1'b1 : 1'b0;
always @ (*) begin
case (funct3)
INSTR_SB : mem_funct_store = `MEM_SB;
INSTR_SH : mem_funct_store = `MEM_SH;
INSTR_SW : mem_funct_store = `MEM_SW;
default : mem_funct_store = `MEM_NOP;
endcase
end
assign illegal_store = (mem_funct_store == `MEM_NOP) ? 1'b1 : 1'b0;
assign decoded_packed_imm = {illegal_imm, reg_imm, alu_imm, br_imm, mem_imm };
assign decoded_packed_lui = {illegal_lui, reg_lui, alu_lui, br_lui, mem_lui };
assign decoded_packed_auipc = {illegal_auipc, reg_auipc, alu_auipc, br_auipc, mem_auipc };
assign decoded_packed_op = {illegal_op, reg_op, alu_op, br_op, mem_op };
assign decoded_packed_jal = {illegal_jal, reg_jal, alu_jal, br_jal, mem_jal };
assign decoded_packed_jalr = {illegal_jalr, reg_jalr, alu_jalr, br_jalr, mem_jalr };
assign decoded_packed_br = {illegal_br, reg_br, alu_br, br_br, mem_br };
assign decoded_packed_load = {illegal_load, reg_load, alu_load, br_load, mem_load };
assign decoded_packed_store = {illegal_store, reg_store, alu_store, br_store, mem_store };
always @ (*) begin
case (opcode)
OPCODE_IMM : decoded_packed = decoded_packed_imm;
OPCODE_LUI : decoded_packed = decoded_packed_lui;
OPCODE_AUIPC : decoded_packed = decoded_packed_auipc;
OPCODE_OP : decoded_packed = decoded_packed_op;
OPCODE_JAL : decoded_packed = decoded_packed_jal;
OPCODE_JALR : decoded_packed = decoded_packed_jalr;
OPCODE_BRANCH: decoded_packed = decoded_packed_br;
OPCODE_LOAD : decoded_packed = decoded_packed_load;
OPCODE_STORE : decoded_packed = decoded_packed_store;
default : decoded_packed = {1'b1, {PK_DATA_W-1{1'b0}}};
endcase
end
//unpack and assign outputs
assign illegal_instruction = decoded_packed[ILLEGAL_OFFSET];
assign reg_unpk = decoded_packed[(PK_REG_W-1)+PK_REG_OFFSET:PK_REG_OFFSET];
assign alu_unpk = decoded_packed[(PK_ALU_W-1)+PK_ALU_OFFSET:PK_ALU_OFFSET];
assign br_unpk = decoded_packed[(PK_BR_W -1)+PK_BR_OFFSET :PK_BR_OFFSET];
assign mem_unpk = decoded_packed[(PK_MEM_W-1)+PK_MEM_OFFSET:PK_MEM_OFFSET];
//Register settings rsj rsk rsd rsd
assign use_rsj = reg_unpk[4];
assign use_rsk = reg_unpk[3];
assign use_rsd = reg_unpk[2];
assign rsd_lockout = reg_unpk[1:0];
//ALU alu_funct sel_a sel_b immed_a immed_b
assign alu_funct = alu_unpk[75:66];
assign alu_sel_a = alu_unpk[65];
assign alu_sel_b = alu_unpk[64];
assign alu_immed_a = alu_unpk[63:32];
assign alu_immed_b = alu_unpk[31:0];
//Branch br_funct sel_a immed_a immed_b
assign br_funct = br_unpk[71:65];
assign br_sel_a = br_unpk[64];
assign br_immed_a = br_unpk[63:32];
assign br_immed_b = br_unpk[31:0];
//MEM
assign mem_funct = mem_unpk[7:0];
endmodule
|
//
// fixed for 9.1 jan 21 2010 cruben
//
`include "timescale.v"
`include "i2c_master_defines.v"
module i2c_opencores
(
wb_clk_i, wb_rst_i, wb_adr_i, wb_dat_i, wb_dat_o,
wb_we_i, wb_stb_i, /*wb_cyc_i,*/ wb_ack_o, wb_inta_o,
scl_pad_io, sda_pad_io
);
// Common bus signals
input wb_clk_i; // WISHBONE clock
input wb_rst_i; // WISHBONE reset
// Slave signals
input [2:0] wb_adr_i; // WISHBONE address input
input [7:0] wb_dat_i; // WISHBONE data input
output [7:0] wb_dat_o; // WISHBONE data output
input wb_we_i; // WISHBONE write enable input
input wb_stb_i; // WISHBONE strobe input
//input wb_cyc_i; // WISHBONE cycle input
output wb_ack_o; // WISHBONE acknowledge output
output wb_inta_o; // WISHBONE interrupt output
// I2C signals
inout scl_pad_io; // I2C clock io
inout sda_pad_io; // I2C data io
wire wb_cyc_i; // WISHBONE cycle input
// Wire tri-state scl/sda
wire scl_pad_i;
wire scl_pad_o;
wire scl_pad_io;
wire scl_padoen_o;
assign wb_cyc_i = wb_stb_i;
assign scl_pad_i = scl_pad_io;
assign scl_pad_io = scl_padoen_o ? 1'bZ : scl_pad_o;
wire sda_pad_i;
wire sda_pad_o;
wire sda_pad_io;
wire sda_padoen_o;
assign sda_pad_i = sda_pad_io;
assign sda_pad_io = sda_padoen_o ? 1'bZ : sda_pad_o;
// Avalon doesn't have an asynchronous reset
// set it to be inactive and just use synchronous reset
// reset level is a parameter, 0 is the default (active-low reset)
wire arst_i;
assign arst_i = 1'b1;
// Connect the top level I2C core
i2c_master_top i2c_master_top_inst
(
.wb_clk_i(wb_clk_i), .wb_rst_i(wb_rst_i), .arst_i(arst_i),
.wb_adr_i(wb_adr_i), .wb_dat_i(wb_dat_i), .wb_dat_o(wb_dat_o),
.wb_we_i(wb_we_i), .wb_stb_i(wb_stb_i), .wb_cyc_i(wb_cyc_i),
.wb_ack_o(wb_ack_o), .wb_inta_o(wb_inta_o),
.scl_pad_i(scl_pad_i), .scl_pad_o(scl_pad_o), .scl_padoen_o(scl_padoen_o),
.sda_pad_i(sda_pad_i), .sda_pad_o(sda_pad_o), .sda_padoen_o(sda_padoen_o)
);
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_ad9361_tx (
// dac interface
dac_clk,
dac_valid,
dac_data,
dac_r1_mode,
adc_data,
// delay interface
up_dld,
up_dwdata,
up_drdata,
delay_clk,
delay_rst,
delay_locked,
// master/slave
dac_sync_in,
dac_sync_out,
// dma interface
dac_enable_i0,
dac_valid_i0,
dac_data_i0,
dac_enable_q0,
dac_valid_q0,
dac_data_q0,
dac_enable_i1,
dac_valid_i1,
dac_data_i1,
dac_enable_q1,
dac_valid_q1,
dac_data_q1,
dac_dovf,
dac_dunf,
// gpio
up_dac_gpio_in,
up_dac_gpio_out,
// processor interface
up_rstn,
up_clk,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_rack);
// parameters
parameter DP_DISABLE = 0;
parameter PCORE_ID = 0;
// dac interface
input dac_clk;
output dac_valid;
output [47:0] dac_data;
output dac_r1_mode;
input [47:0] adc_data;
// delay interface
output [ 7:0] up_dld;
output [39:0] up_dwdata;
input [39:0] up_drdata;
input delay_clk;
output delay_rst;
input delay_locked;
// master/slave
input dac_sync_in;
output dac_sync_out;
// dma interface
output dac_enable_i0;
output dac_valid_i0;
input [15:0] dac_data_i0;
output dac_enable_q0;
output dac_valid_q0;
input [15:0] dac_data_q0;
output dac_enable_i1;
output dac_valid_i1;
input [15:0] dac_data_i1;
output dac_enable_q1;
output dac_valid_q1;
input [15:0] dac_data_q1;
input dac_dovf;
input dac_dunf;
// gpio
input [31:0] up_dac_gpio_in;
output [31:0] up_dac_gpio_out;
// processor interface
input up_rstn;
input up_clk;
input up_wreq;
input [13:0] up_waddr;
input [31:0] up_wdata;
output up_wack;
input up_rreq;
input [13:0] up_raddr;
output [31:0] up_rdata;
output up_rack;
// internal registers
reg dac_data_sync = 'd0;
reg [ 7:0] dac_rate_cnt = 'd0;
reg dac_valid = 'd0;
reg dac_valid_i0 = 'd0;
reg dac_valid_q0 = 'd0;
reg dac_valid_i1 = 'd0;
reg dac_valid_q1 = 'd0;
reg [31:0] up_rdata = 'd0;
reg up_rack = 'd0;
reg up_wack = 'd0;
// internal clock and resets
wire dac_rst;
// internal signals
wire dac_data_sync_s;
wire dac_dds_format_s;
wire [ 7:0] dac_datarate_s;
wire [47:0] dac_data_int_s;
wire [31:0] up_rdata_s[0:5];
wire up_rack_s[0:5];
wire up_wack_s[0:5];
// master/slave
assign dac_data_sync_s = (PCORE_ID == 0) ? dac_sync_out : dac_sync_in;
always @(posedge dac_clk) begin
dac_data_sync <= dac_data_sync_s;
end
// rate counters and data sync signals
always @(posedge dac_clk) begin
if ((dac_data_sync == 1'b1) || (dac_rate_cnt == 8'd0)) begin
dac_rate_cnt <= dac_datarate_s;
end else begin
dac_rate_cnt <= dac_rate_cnt - 1'b1;
end
end
// dma interface
always @(posedge dac_clk) begin
dac_valid <= (dac_rate_cnt == 8'd0) ? 1'b1 : 1'b0;
dac_valid_i0 <= dac_valid;
dac_valid_q0 <= dac_valid;
dac_valid_i1 <= dac_valid & ~dac_r1_mode;
dac_valid_q1 <= dac_valid & ~dac_r1_mode;
end
// processor read interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_rdata <= 'd0;
up_rack <= 'd0;
up_wack <= 'd0;
end else begin
up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2] |
up_rdata_s[3] | up_rdata_s[4] | up_rdata_s[5];
up_rack <= up_rack_s[0] | up_rack_s[1] | up_rack_s[2] |
up_rack_s[3] | up_rack_s[4] | up_rack_s[5];
up_wack <= up_wack_s[0] | up_wack_s[1] | up_wack_s[2] |
up_wack_s[3] | up_wack_s[4] | up_wack_s[5];
end
end
// dac channel
axi_ad9361_tx_channel #(
.CHID (0),
.IQSEL (0),
.DP_DISABLE (DP_DISABLE))
i_tx_channel_0 (
.dac_clk (dac_clk),
.dac_rst (dac_rst),
.dac_valid (dac_valid),
.dma_data (dac_data_i0),
.adc_data (adc_data[11:0]),
.dac_data (dac_data[11:0]),
.dac_data_out (dac_data_int_s[11:0]),
.dac_data_in (dac_data_int_s[23:12]),
.dac_enable (dac_enable_i0),
.dac_data_sync (dac_data_sync),
.dac_dds_format (dac_dds_format_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack_s[0]),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata_s[0]),
.up_rack (up_rack_s[0]));
// dac channel
axi_ad9361_tx_channel #(
.CHID (1),
.IQSEL (1),
.DP_DISABLE (DP_DISABLE))
i_tx_channel_1 (
.dac_clk (dac_clk),
.dac_rst (dac_rst),
.dac_valid (dac_valid),
.dma_data (dac_data_q0),
.adc_data (adc_data[23:12]),
.dac_data (dac_data[23:12]),
.dac_data_out (dac_data_int_s[23:12]),
.dac_data_in (dac_data_int_s[11:0]),
.dac_enable (dac_enable_q0),
.dac_data_sync (dac_data_sync),
.dac_dds_format (dac_dds_format_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack_s[1]),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata_s[1]),
.up_rack (up_rack_s[1]));
// dac channel
axi_ad9361_tx_channel #(
.CHID (2),
.IQSEL (0),
.DP_DISABLE (DP_DISABLE))
i_tx_channel_2 (
.dac_clk (dac_clk),
.dac_rst (dac_rst),
.dac_valid (dac_valid),
.dma_data (dac_data_i1),
.adc_data (adc_data[35:24]),
.dac_data (dac_data[35:24]),
.dac_data_out (dac_data_int_s[35:24]),
.dac_data_in (dac_data_int_s[47:36]),
.dac_enable (dac_enable_i1),
.dac_data_sync (dac_data_sync),
.dac_dds_format (dac_dds_format_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack_s[2]),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata_s[2]),
.up_rack (up_rack_s[2]));
// dac channel
axi_ad9361_tx_channel #(
.CHID (3),
.IQSEL (1),
.DP_DISABLE (DP_DISABLE))
i_tx_channel_3 (
.dac_clk (dac_clk),
.dac_rst (dac_rst),
.dac_valid (dac_valid),
.dma_data (dac_data_q1),
.adc_data (adc_data[47:36]),
.dac_data (dac_data[47:36]),
.dac_data_out (dac_data_int_s[47:36]),
.dac_data_in (dac_data_int_s[35:24]),
.dac_enable (dac_enable_q1),
.dac_data_sync (dac_data_sync),
.dac_dds_format (dac_dds_format_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack_s[3]),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata_s[3]),
.up_rack (up_rack_s[3]));
// dac common processor interface
up_dac_common #(.PCORE_ID (PCORE_ID)) i_up_dac_common (
.mmcm_rst (),
.dac_clk (dac_clk),
.dac_rst (dac_rst),
.dac_sync (dac_sync_out),
.dac_frame (),
.dac_par_type (),
.dac_par_enb (),
.dac_r1_mode (dac_r1_mode),
.dac_datafmt (dac_dds_format_s),
.dac_datarate (dac_datarate_s),
.dac_status (1'b1),
.dac_status_ovf (dac_dovf),
.dac_status_unf (dac_dunf),
.dac_clk_ratio (32'd1),
.up_drp_sel (),
.up_drp_wr (),
.up_drp_addr (),
.up_drp_wdata (),
.up_drp_rdata (16'd0),
.up_drp_ready (1'd0),
.up_drp_locked (1'd1),
.up_usr_chanmax (),
.dac_usr_chanmax (8'd3),
.up_dac_gpio_in (up_dac_gpio_in),
.up_dac_gpio_out (up_dac_gpio_out),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack_s[4]),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata_s[4]),
.up_rack (up_rack_s[4]));
// dac delay control
up_delay_cntrl #(.IO_WIDTH(8), .IO_BASEADDR(6'h12)) i_delay_cntrl (
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_locked (delay_locked),
.up_dld (up_dld),
.up_dwdata (up_dwdata),
.up_drdata (up_drdata),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack_s[5]),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata_s[5]),
.up_rack (up_rack_s[5]));
endmodule
// ***************************************************************************
// ***************************************************************************
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O2BB2A_4_V
`define SKY130_FD_SC_LS__O2BB2A_4_V
/**
* o2bb2a: 2-input NAND and 2-input OR into 2-input AND.
*
* X = (!(A1 & A2) & (B1 | B2))
*
* Verilog wrapper for o2bb2a with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__o2bb2a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o2bb2a_4 (
X ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__o2bb2a base (
.X(X),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o2bb2a_4 (
X ,
A1_N,
A2_N,
B1 ,
B2
);
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__o2bb2a base (
.X(X),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__O2BB2A_4_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NOR4BB_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__NOR4BB_BEHAVIORAL_PP_V
/**
* nor4bb: 4-input NOR, first two inputs inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__nor4bb (
VPWR,
VGND,
Y ,
A ,
B ,
C_N ,
D_N
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A ;
input B ;
input C_N ;
input D_N ;
// Local signals
wire DN nor0_out ;
wire and0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , A, B );
and and0 (and0_out_Y , nor0_out, C_N, D_N );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, and0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__NOR4BB_BEHAVIORAL_PP_V
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: sparc_exu_alulogic.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
//
// Module Name: sparc_exu_alulogic
// Description: This block implements and, or, xor, xnor, nand, nor
// and pass_rs2_data. And, or, Xor and pass are muxed together
// and then xored with an inversion signal to create
// xnor, nand and nor. Both inputs are buffered before being
// used and the rs2_data signal is buffered again before going
// to the mux.
*/
module sparc_exu_alulogic (/*AUTOARG*/
// Outputs
logic_out,
// Inputs
rs1_data, rs2_data, isand, isor, isxor, pass_rs2_data, inv_logic,
ifu_exu_sethi_inst_e
);
input [63:0] rs1_data; // 1st input operand
input [63:0] rs2_data; // 2nd input operand
input isand;
input isor;
input isxor;
input pass_rs2_data;
input inv_logic;
input ifu_exu_sethi_inst_e; // zero out top half of rs2 on mov
output [63:0] logic_out; // output of logic block
wire [63:0] rs1_data_bf1; // buffered rs1_data
wire [63:0] rs2_data_bf1; // buffered rs2_data
wire [63:0] mov_data;
wire [63:0] result_and; // rs1_data & rs2_data
wire [63:0] result_or; // rs1_data | rs2_data
wire [63:0] result_xor; // rs1_data ^ rs2_data
wire [63:0] rs2_xor_invert; // output of mux between various results
// mux between various results
mux4ds #(64) logic_mux(.dout(logic_out[63:0]),
.in0(result_and[63:0]),
.in1(result_or[63:0]),
.in2(result_xor[63:0]),
.in3(mov_data[63:0]),
.sel0(isand),
.sel1(isor),
.sel2(isxor),
.sel3(pass_rs2_data));
// buffer inputs
dp_buffer #(64) rs1_data_buf(.dout(rs1_data_bf1[63:0]), .in(rs1_data[63:0]));
dp_buffer #(64) rs2_data_buf(.dout(rs2_data_bf1[63:0]), .in(rs2_data[63:0]));
// zero out top of rs2 for sethi_inst
assign mov_data[63:32] = rs2_data_bf1[63:32] & {32{~ifu_exu_sethi_inst_e}};
dp_buffer #(32) rs2_data_buf2(.dout(mov_data[31:0]), .in(rs2_data_bf1[31:0]));
// invert input2 for andn, orn, xnor
assign rs2_xor_invert[63:0] = rs2_data_bf1[63:0] ^ {64{inv_logic}};
// do boolean ops
assign result_and = rs1_data_bf1 & rs2_xor_invert;
assign result_or = rs1_data_bf1 | rs2_xor_invert;
assign result_xor = rs1_data_bf1 ^ rs2_xor_invert;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A2BB2O_PP_SYMBOL_V
`define SKY130_FD_SC_LP__A2BB2O_PP_SYMBOL_V
/**
* a2bb2o: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input OR.
*
* X = ((!A1 & !A2) | (B1 & B2))
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__a2bb2o (
//# {{data|Data Signals}}
input A1_N,
input A2_N,
input B1 ,
input B2 ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__A2BB2O_PP_SYMBOL_V
|
module demo2_text (
input wire clk,
input wire [10:0] PIXEL_H, PIXEL_V,
output reg [2:0] PIXEL
);
// signal declaration
wire [10:0] rom_addr;
reg [6:0] char_addr;
reg [3:0] row_addr;
reg [2:0] bit_addr;
wire [7:0] font_word;
wire font_bit;
wire text_on;
// instantiate font ROM
font_rom font_unit
(.clk(clk), .addr(rom_addr), .data(font_word));
// Location on the screen of this tile.
reg [10:0] tile_v_start = 8'd10;
reg [10:0] tile_h_start = 8'd200;
wire [10:0] tile_v_end;
wire [10:0] tile_h_end;
assign tile_v_end = tile_v_start + (8'd15 << 2);
assign tile_h_end = tile_h_start + (8'd7 << 2);
// Check we are within the part of the screen that holds the character tile.
assign text_on = (PIXEL_H >= tile_h_start && PIXEL_H <= tile_h_end && PIXEL_V >= tile_v_start && PIXEL_V <= tile_v_end);
// Mux for font ROM addresses and rgb
always @* begin
PIXEL = 3'b000;
if (text_on) begin
char_addr = 7'h30; // 0
row_addr = (PIXEL_V - tile_v_start) >> 2;
bit_addr = (PIXEL_H - tile_h_start) >> 2;
if (font_bit)
PIXEL = 3'b111;
end else begin
char_addr = 0;
row_addr = 0;
bit_addr = 0;
end
end
// Build the rom address of the current pixel.
assign rom_addr = {char_addr, row_addr};
// Get the on/off value of the bit at the current pixel from the rom.
assign font_bit = font_word[~bit_addr];
endmodule
|
(************************************************************************)
(* * The Coq Proof Assistant / The Coq Development Team *)
(* v * INRIA, CNRS and contributors - Copyright 1999-2019 *)
(* <O___,, * (see CREDITS file for the list of authors) *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(* * (see LICENSE file for the text of the license) *)
(************************************************************************)
Require Import Morphisms BinInt ZDivEucl.
Local Open Scope Z_scope.
(** * Definitions of division for binary integers, Euclid convention. *)
(** In this convention, the remainder is always positive.
For other conventions, see [Z.div] and [Z.quot] in file [BinIntDef].
To avoid collision with the other divisions, we place this one
under a module.
*)
Module ZEuclid.
Definition modulo a b := Z.modulo a (Z.abs b).
Definition div a b := (Z.sgn b) * (Z.div a (Z.abs b)).
Instance mod_wd : Proper (eq==>eq==>eq) modulo.
Proof. congruence. Qed.
Instance div_wd : Proper (eq==>eq==>eq) div.
Proof. congruence. Qed.
Theorem div_mod a b : b<>0 -> a = b*(div a b) + modulo a b.
Proof.
intros Hb. unfold div, modulo.
rewrite Z.mul_assoc. rewrite Z.sgn_abs. apply Z.div_mod.
now destruct b.
Qed.
Lemma mod_always_pos a b : b<>0 -> 0 <= modulo a b < Z.abs b.
Proof.
intros Hb. unfold modulo.
apply Z.mod_pos_bound.
destruct b; compute; trivial. now destruct Hb.
Qed.
Lemma mod_bound_pos a b : 0<=a -> 0<b -> 0 <= modulo a b < b.
Proof.
intros _ Hb. rewrite <- (Z.abs_eq b) at 3 by Z.order.
apply mod_always_pos. Z.order.
Qed.
Include ZEuclidProp Z Z Z.
End ZEuclid.
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__TAP_BEHAVIORAL_V
`define SKY130_FD_SC_HD__TAP_BEHAVIORAL_V
/**
* tap: Tap cell with no tap connections (no contacts on metal1).
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__tap ();
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__TAP_BEHAVIORAL_V
|
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module sysid_0 (
// inputs:
address,
clock,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input address;
input clock;
input reset_n;
wire [ 31: 0] readdata;
//control_slave, which is an e_avalon_slave
assign readdata = address ? 1419253882 : 0;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A221OI_BEHAVIORAL_V
`define SKY130_FD_SC_HD__A221OI_BEHAVIORAL_V
/**
* a221oi: 2-input AND into first two inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__a221oi (
Y ,
A1,
A2,
B1,
B2,
C1
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out ;
wire and1_out ;
wire nor0_out_Y;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
and and1 (and1_out , A1, A2 );
nor nor0 (nor0_out_Y, and0_out, C1, and1_out);
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__A221OI_BEHAVIORAL_V
|
//wb_artemis_ddr3.v
/*
Distributed under the MIT license.
Copyright (c) 2015 Dave McCoy ([email protected])
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/*
Set the Vendor ID (Hexidecimal 64-bit Number)
SDB_VENDOR_ID:0x800000000000C594
Set the Device ID (Hexcidecimal 32-bit Number)
SDB_DEVICE_ID:0x00000000
Set the version of the Core XX.XXX.XXX Example: 01.000.000
SDB_CORE_VERSION:00.000.001
Set the Device Name: 19 UNICODE characters
SDB_NAME:wb_artemis_ddr3
Set the class of the device (16 bits) Set as 0
SDB_ABI_CLASS:0
Set the ABI Major Version: (8-bits)
SDB_ABI_VERSION_MAJOR:0x06
Set the ABI Minor Version (8-bits)
SDB_ABI_VERSION_MINOR:0x03
Set the Module URL (63 Unicode Characters)
SDB_MODULE_URL:http://www.example.com
Set the date of module YYYY/MM/DD
SDB_DATE:2015/03/11
Device is executable (True/False)
SDB_EXECUTABLE:True
Device is readable (True/False)
SDB_READABLE:True
Device is writeable (True/False)
SDB_WRITEABLE:True
Device Size: Number of Registers
SDB_SIZE:0x8000000
*/
`timescale 1 ns/1 ps
module wb_artemis_ddr3 (
input clk,
input rst,
//DDR3 Control Signals
output ddr3_cmd_clk,
output ddr3_cmd_en,
output [2:0] ddr3_cmd_instr,
output [5:0] ddr3_cmd_bl,
output [29:0] ddr3_cmd_byte_addr,
input ddr3_cmd_empty,
input ddr3_cmd_full,
output ddr3_wr_clk,
output ddr3_wr_en,
output [3:0] ddr3_wr_mask,
output [31:0] ddr3_wr_data,
input ddr3_wr_full,
input ddr3_wr_empty,
input [6:0] ddr3_wr_count,
input ddr3_wr_underrun,
input ddr3_wr_error,
output ddr3_rd_clk,
output ddr3_rd_en,
input [31:0] ddr3_rd_data,
input ddr3_rd_full,
input ddr3_rd_empty,
input [6:0] ddr3_rd_count,
input ddr3_rd_overflow,
input ddr3_rd_error,
//Wishbone Bus Signals
input i_wbs_we,
input i_wbs_cyc,
input [3:0] i_wbs_sel,
input [31:0] i_wbs_dat,
input i_wbs_stb,
output reg o_wbs_ack,
output reg [31:0] o_wbs_dat,
input [31:0] i_wbs_adr,
//This interrupt can be controlled from this module or a submodule
output reg o_wbs_int
//output o_wbs_int
);
//Local Parameters
//Registers/Wires
reg write_en;
reg read_en;
wire [27:0] ddr3_cmd_word_addr;
reg if_write_strobe;
wire [1:0] if_write_ready;
reg [1:0] if_write_activate;
wire [23:0] if_write_fifo_size;
wire if_starved;
reg of_read_strobe;
wire of_read_ready;
reg of_read_activate;
wire [23:0] of_read_size;
wire [31:0] of_read_data;
reg [23:0] write_count;
reg [23:0] read_count;
//Submodules
ddr3_controller dc(
.clk (clk ),
.rst (rst ),
.write_address (i_wbs_adr[27:0] ),
.write_en (write_en ),
.read_address (i_wbs_adr[27:0] ),
.read_en (read_en ),
.if_write_strobe (if_write_strobe ),
.if_write_data (i_wbs_dat ),
//.if_write_data (32'h01234567 ),
.if_write_ready (if_write_ready ),
.if_write_activate (if_write_activate ),
.if_write_fifo_size (if_write_fifo_size ),
.if_starved (if_starved ),
.of_read_strobe (of_read_strobe ),
.of_read_ready (of_read_ready ),
.of_read_activate (of_read_activate ),
.of_read_size (of_read_size ),
.of_read_data (of_read_data ),
.cmd_en (ddr3_cmd_en ),
.cmd_instr (ddr3_cmd_instr ),
.cmd_bl (ddr3_cmd_bl ),
.cmd_word_addr (ddr3_cmd_word_addr ),
.cmd_empty (ddr3_cmd_empty ),
.cmd_full (ddr3_cmd_full ),
.wr_en (ddr3_wr_en ),
.wr_mask (ddr3_wr_mask ),
.wr_data (ddr3_wr_data ),
.wr_full (ddr3_wr_full ),
.wr_empty (ddr3_wr_empty ),
.wr_count (ddr3_wr_count ),
.wr_underrun (ddr3_wr_underrun ),
.wr_error (ddr3_wr_error ),
.rd_en (ddr3_rd_en ),
.rd_data (ddr3_rd_data ),
.rd_full (ddr3_rd_full ),
.rd_empty (ddr3_rd_empty ),
.rd_count (ddr3_rd_count ),
.rd_overflow (ddr3_rd_overflow ),
.rd_error (ddr3_rd_error )
);
//Asynchronous Logic
assign ddr3_cmd_clk = clk;
assign ddr3_wr_clk = clk;
assign ddr3_rd_clk = clk;
assign ddr3_cmd_byte_addr = {ddr3_cmd_word_addr, 2'b0};
//Synchronous Logic
always @ (posedge clk) begin
if (rst) begin
o_wbs_dat <= 32'h0;
o_wbs_ack <= 0;
o_wbs_int <= 0;
write_en <= 0;
read_en <= 0;
if_write_strobe <= 0;
if_write_activate <= 0;
of_read_strobe <= 0;
of_read_activate <= 0;
write_count <= 0;
read_count <= 0;
end
else begin
//Deasserts Strobes
if_write_strobe <= 0;
of_read_strobe <= 0;
//Get a Ping Pong FIFO Writer
if ((if_write_ready > 0) && (if_write_activate == 0)) begin
write_count <= 0;
if (if_write_ready[0]) begin
if_write_activate[0] <= 1;
end
else begin
if_write_activate[1] <= 1;
end
end
//Get the Ping Pong FIFO Reader
if (of_read_ready && !of_read_activate) begin
read_count <= 0;
of_read_activate <= 1;
end
//when the master acks our ack, then put our ack down
if (o_wbs_ack && ~i_wbs_stb)begin
o_wbs_ack <= 0;
end
//A transaction has starting
if (i_wbs_cyc) begin
if (i_wbs_we) begin
write_en <= 1;
end
else begin
read_en <= 1;
end
end
else begin
write_en <= 0;
read_en <= 0;
//A transaction has ended
//Close any FIFO that is open
if_write_activate <= 0;
of_read_activate <= 0;
end
if ((if_write_activate > 0) && (write_count > 0)&& (if_write_ready > 0)) begin
//Other side is idle, give it something to do
if_write_activate <= 0;
end
//Strobe
else if (i_wbs_stb && i_wbs_cyc && !o_wbs_ack) begin
//master is requesting something
if (write_en) begin
//write request
if (if_write_activate > 0) begin
if (write_count < if_write_fifo_size) begin
if_write_strobe <= 1;
o_wbs_ack <= 1;
write_count <= write_count + 24'h1;
end
else begin
if_write_activate <= 0;
end
end
end
else begin
//read request
if (of_read_activate) begin
if (read_count < of_read_size) begin
read_count <= read_count + 1;
o_wbs_dat <= of_read_data;
o_wbs_ack <= 1;
of_read_strobe <= 1;
end
else begin
of_read_activate <= 0;
end
end
end
end
end
end
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_jesd_gt (
// physical interface
ref_clk_q,
ref_clk_c,
rx_data_p,
rx_data_n,
rx_sync,
rx_sysref,
rx_ext_sysref,
tx_data_p,
tx_data_n,
tx_sync,
tx_sysref,
tx_ext_sysref,
// core interface
rx_rst,
rx_jesd_rst,
rx_clk_g,
rx_clk,
rx_data,
rx_sof,
rx_gt_charisk,
rx_gt_disperr,
rx_gt_notintable,
rx_gt_data,
rx_rst_done,
rx_ip_comma_align,
rx_ip_sync,
rx_ip_sof,
rx_ip_data,
tx_rst,
tx_jesd_rst,
tx_clk_g,
tx_clk,
tx_data,
tx_gt_charisk,
tx_gt_data,
tx_rst_done,
tx_ip_sync,
tx_ip_sof,
tx_ip_data,
// axi - clock & reset
axi_aclk,
axi_aresetn,
// axi-lite (slave)
s_axi_awvalid,
s_axi_awaddr,
s_axi_awready,
s_axi_wvalid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wready,
s_axi_bvalid,
s_axi_bresp,
s_axi_bready,
s_axi_arvalid,
s_axi_araddr,
s_axi_arready,
s_axi_rvalid,
s_axi_rdata,
s_axi_rresp,
s_axi_rready,
// axi (master)
m_axi_awvalid,
m_axi_awaddr,
m_axi_awprot,
m_axi_awready,
m_axi_wvalid,
m_axi_wdata,
m_axi_wstrb,
m_axi_wready,
m_axi_bvalid,
m_axi_bresp,
m_axi_bready,
m_axi_arvalid,
m_axi_araddr,
m_axi_arprot,
m_axi_arready,
m_axi_rvalid,
m_axi_rdata,
m_axi_rresp,
m_axi_rready);
parameter PCORE_ID = 0;
parameter PCORE_DEVICE_TYPE = 0;
parameter PCORE_NUM_OF_TX_LANES = 4;
parameter PCORE_NUM_OF_RX_LANES = 4;
parameter PCORE_QPLL_REFCLK_DIV = 1;
parameter PCORE_QPLL_CFG = 27'h0680181;
parameter PCORE_QPLL_FBDIV_RATIO = 1'b1;
parameter PCORE_QPLL_FBDIV = 10'b0000110000;
parameter PCORE_CPLL_FBDIV = 2;
parameter PCORE_RX_OUT_DIV = 1;
parameter PCORE_TX_OUT_DIV = 1;
parameter PCORE_RX_CLK25_DIV = 20;
parameter PCORE_TX_CLK25_DIV = 20;
parameter PCORE_PMA_RSV = 32'h001E7080;
parameter PCORE_RX_CDR_CFG = 72'h0b000023ff10400020;
parameter PCORE_TX_LANE_SEL_0 = 0;
parameter PCORE_TX_LANE_SEL_1 = 1;
parameter PCORE_TX_LANE_SEL_2 = 2;
parameter PCORE_TX_LANE_SEL_3 = 3;
parameter PCORE_TX_LANE_SEL_4 = 4;
parameter PCORE_TX_LANE_SEL_5 = 5;
parameter PCORE_TX_LANE_SEL_6 = 6;
parameter PCORE_TX_LANE_SEL_7 = 7;
parameter PCORE_TX_LANE_SEL_8 = 8;
localparam PCORE_NUM_OF_LANES = (PCORE_NUM_OF_TX_LANES > PCORE_NUM_OF_RX_LANES) ?
PCORE_NUM_OF_TX_LANES : PCORE_NUM_OF_RX_LANES;
// physical interface
input ref_clk_q;
input ref_clk_c;
input [((PCORE_NUM_OF_RX_LANES* 1)-1):0] rx_data_p;
input [((PCORE_NUM_OF_RX_LANES* 1)-1):0] rx_data_n;
output rx_sync;
output rx_sysref;
input rx_ext_sysref;
output [((PCORE_NUM_OF_TX_LANES* 1)-1):0] tx_data_p;
output [((PCORE_NUM_OF_TX_LANES* 1)-1):0] tx_data_n;
input tx_sync;
output tx_sysref;
input tx_ext_sysref;
// core interface
output rx_rst;
output rx_jesd_rst;
output rx_clk_g;
input rx_clk;
output [((PCORE_NUM_OF_RX_LANES*32)-1):0] rx_data;
output [((PCORE_NUM_OF_RX_LANES* 1)-1):0] rx_sof;
output [((PCORE_NUM_OF_RX_LANES* 4)-1):0] rx_gt_charisk;
output [((PCORE_NUM_OF_RX_LANES* 4)-1):0] rx_gt_disperr;
output [((PCORE_NUM_OF_RX_LANES* 4)-1):0] rx_gt_notintable;
output [((PCORE_NUM_OF_RX_LANES*32)-1):0] rx_gt_data;
output rx_rst_done;
input rx_ip_comma_align;
input rx_ip_sync;
input [ 3:0] rx_ip_sof;
input [((PCORE_NUM_OF_RX_LANES*32)-1):0] rx_ip_data;
output tx_rst;
output tx_jesd_rst;
output tx_clk_g;
input tx_clk;
input [((PCORE_NUM_OF_TX_LANES*32)-1):0] tx_data;
input [((PCORE_NUM_OF_TX_LANES* 4)-1):0] tx_gt_charisk;
input [((PCORE_NUM_OF_TX_LANES*32)-1):0] tx_gt_data;
output tx_rst_done;
output tx_ip_sync;
input [ 3:0] tx_ip_sof;
output [((PCORE_NUM_OF_TX_LANES*32)-1):0] tx_ip_data;
input axi_aclk;
input axi_aresetn;
// axi interface
input s_axi_awvalid;
input [ 31:0] s_axi_awaddr;
output s_axi_awready;
input s_axi_wvalid;
input [ 31:0] s_axi_wdata;
input [ 3:0] s_axi_wstrb;
output s_axi_wready;
output s_axi_bvalid;
output [ 1:0] s_axi_bresp;
input s_axi_bready;
input s_axi_arvalid;
input [ 31:0] s_axi_araddr;
output s_axi_arready;
output s_axi_rvalid;
output [ 31:0] s_axi_rdata;
output [ 1:0] s_axi_rresp;
input s_axi_rready;
// master interface
output m_axi_awvalid;
output [ 31:0] m_axi_awaddr;
output [ 2:0] m_axi_awprot;
input m_axi_awready;
output m_axi_wvalid;
output [ 31:0] m_axi_wdata;
output [ 3:0] m_axi_wstrb;
input m_axi_wready;
input m_axi_bvalid;
input [ 1:0] m_axi_bresp;
output m_axi_bready;
output m_axi_arvalid;
output [ 31:0] m_axi_araddr;
output [ 2:0] m_axi_arprot;
input m_axi_arready;
input m_axi_rvalid;
input [ 31:0] m_axi_rdata;
input [ 1:0] m_axi_rresp;
output m_axi_rready;
// reset and clocks
wire gt_pll_rst;
wire gt_rx_rst;
wire gt_tx_rst;
wire qpll_clk_0;
wire qpll_ref_clk_0;
wire qpll_clk_1;
wire qpll_ref_clk_1;
wire [ 7:0] qpll_clk;
wire [ 7:0] qpll_ref_clk;
wire [((PCORE_NUM_OF_LANES* 1)-1):0] rx_out_clk;
wire [((PCORE_NUM_OF_LANES* 1)-1):0] tx_out_clk;
wire up_rstn;
wire up_clk;
wire up_drp_rst;
// internal signals
wire [ 8:0] up_status_extn_s;
wire [ 8:0] rx_rst_done_extn_s;
wire [ 8:0] rx_pll_locked_extn_s;
wire [ 8:0] tx_rst_done_extn_s;
wire [ 8:0] tx_pll_locked_extn_s;
wire [((PCORE_NUM_OF_LANES* 1)-1):0] rx_mon_trigger_s;
wire [((PCORE_NUM_OF_LANES*50)-1):0] rx_mon_data_s;
wire [ 15:0] up_drp_rdata_gt_s[15:0];
wire up_drp_ready_gt_s[15:0];
wire [ 7:0] up_drp_rxrate_gt_s[15:0];
wire [((PCORE_NUM_OF_LANES* 1)-1):0] rx_data_p_s;
wire [((PCORE_NUM_OF_LANES* 1)-1):0] rx_data_n_s;
wire [((PCORE_NUM_OF_LANES*32)-1):0] rx_data_s;
wire [((PCORE_NUM_OF_LANES* 1)-1):0] rx_sof_s;
wire [((PCORE_NUM_OF_LANES* 4)-1):0] rx_gt_charisk_s;
wire [((PCORE_NUM_OF_LANES* 4)-1):0] rx_gt_disperr_s;
wire [((PCORE_NUM_OF_LANES* 4)-1):0] rx_gt_notintable_s;
wire [((PCORE_NUM_OF_LANES*32)-1):0] rx_gt_data_s;
wire [((PCORE_NUM_OF_LANES* 4)-1):0] rx_ilas_f_s;
wire [((PCORE_NUM_OF_LANES* 4)-1):0] rx_ilas_q_s;
wire [((PCORE_NUM_OF_LANES* 4)-1):0] rx_ilas_a_s;
wire [((PCORE_NUM_OF_LANES* 4)-1):0] rx_ilas_r_s;
wire [((PCORE_NUM_OF_LANES* 4)-1):0] rx_cgs_k_s;
wire [((PCORE_NUM_OF_LANES*32)-1):0] rx_ip_data_s;
wire [((PCORE_NUM_OF_LANES* 1)-1):0] tx_data_p_s;
wire [((PCORE_NUM_OF_LANES* 1)-1):0] tx_data_n_s;
wire [((PCORE_NUM_OF_LANES* 4)-1):0] tx_gt_charisk_s;
wire [((PCORE_NUM_OF_LANES*32)-1):0] tx_gt_data_s;
wire [287:0] tx_gt_data_extn_zero_s;
wire [ 35:0] tx_gt_charisk_extn_zero_s;
wire [287:0] tx_gt_data_extn_s;
wire [ 35:0] tx_gt_charisk_extn_s;
wire [287:0] tx_gt_data_mux_s;
wire [ 35:0] tx_gt_charisk_mux_s;
wire qpll_locked_0_s;
wire qpll_locked_1_s;
wire [ 7:0] qpll_locked_s;
wire [((PCORE_NUM_OF_LANES* 1)-1):0] rx_rst_done_s;
wire [((PCORE_NUM_OF_LANES* 1)-1):0] rx_pll_locked_s;
wire [((PCORE_NUM_OF_LANES* 1)-1):0] tx_rst_done_s;
wire [((PCORE_NUM_OF_LANES* 1)-1):0] tx_pll_locked_s;
wire up_lpm_dfe_n_s;
wire up_cpll_pd_s;
wire [ 1:0] up_rx_sys_clk_sel_s;
wire [ 2:0] up_rx_out_clk_sel_s;
wire [ 1:0] up_tx_sys_clk_sel_s;
wire [ 2:0] up_tx_out_clk_sel_s;
wire up_drp_sel_s;
wire up_drp_wr_s;
wire [ 11:0] up_drp_addr_s;
wire [ 15:0] up_drp_wdata_s;
wire [ 15:0] up_drp_rdata_s;
wire up_drp_ready_s;
wire [ 7:0] up_drp_lanesel_s;
wire [ 7:0] up_drp_rxrate_s;
wire up_es_drp_sel_s;
wire up_es_drp_wr_s;
wire [ 11:0] up_es_drp_addr_s;
wire [ 15:0] up_es_drp_wdata_s;
wire [ 15:0] up_es_drp_rdata_s;
wire up_es_drp_ready_s;
wire up_es_start_s;
wire up_es_stop_s;
wire up_es_init_s;
wire up_es_lpm_dfe_n_s;
wire [ 15:0] up_es_sdata0_s;
wire [ 15:0] up_es_sdata1_s;
wire [ 15:0] up_es_sdata2_s;
wire [ 15:0] up_es_sdata3_s;
wire [ 15:0] up_es_sdata4_s;
wire [ 15:0] up_es_qdata0_s;
wire [ 15:0] up_es_qdata1_s;
wire [ 15:0] up_es_qdata2_s;
wire [ 15:0] up_es_qdata3_s;
wire [ 15:0] up_es_qdata4_s;
wire [ 4:0] up_es_prescale_s;
wire [ 11:0] up_es_hoffset_min_s;
wire [ 11:0] up_es_hoffset_max_s;
wire [ 11:0] up_es_hoffset_step_s;
wire [ 7:0] up_es_voffset_min_s;
wire [ 7:0] up_es_voffset_max_s;
wire [ 7:0] up_es_voffset_step_s;
wire [ 1:0] up_es_voffset_range_s;
wire [ 31:0] up_es_start_addr_s;
wire up_es_dmaerr_s;
wire up_es_status_s;
wire up_wreq_s;
wire [ 13:0] up_waddr_s;
wire [ 31:0] up_wdata_s;
wire up_wack_s;
wire up_rreq_s;
wire [ 13:0] up_raddr_s;
wire [ 31:0] up_rdata_s;
wire up_rack_s;
// debug interface
assign rx_mon_data = {rx_sync, rx_sysref, rx_ip_sof, rx_ip_data, rx_mon_data_s[((PCORE_NUM_OF_RX_LANES*50)-1):0]};
assign rx_mon_trigger = {rx_sync, rx_sysref, rx_mon_trigger_s[((PCORE_NUM_OF_RX_LANES* 1)-1):0]};
assign tx_mon_data = {tx_sync, tx_sysref, tx_ip_sof, tx_gt_charisk, tx_gt_data};
assign tx_mon_trigger = {tx_sync, tx_sysref, tx_ip_sof};
// signal name changes
assign up_rstn = axi_aresetn;
assign up_clk = axi_aclk;
// drp is simply over-defined to avoid errors with singluar entries
assign up_status_extn_s = 9'hff;
assign rx_rst_done_extn_s = {up_status_extn_s[8:PCORE_NUM_OF_LANES], rx_rst_done_s};
assign rx_pll_locked_extn_s = {up_status_extn_s[8:PCORE_NUM_OF_LANES], rx_pll_locked_s};
assign tx_rst_done_extn_s = {up_status_extn_s[8:PCORE_NUM_OF_LANES], tx_rst_done_s};
assign tx_pll_locked_extn_s = {up_status_extn_s[8:PCORE_NUM_OF_LANES], tx_pll_locked_s};
assign up_drp_rdata_s = up_drp_rdata_gt_s[15] | up_drp_rdata_gt_s[14] |
up_drp_rdata_gt_s[13] | up_drp_rdata_gt_s[12] |
up_drp_rdata_gt_s[11] | up_drp_rdata_gt_s[10] |
up_drp_rdata_gt_s[ 9] | up_drp_rdata_gt_s[ 8] |
up_drp_rdata_gt_s[ 7] | up_drp_rdata_gt_s[ 6] |
up_drp_rdata_gt_s[ 5] | up_drp_rdata_gt_s[ 4] |
up_drp_rdata_gt_s[ 3] | up_drp_rdata_gt_s[ 2] |
up_drp_rdata_gt_s[ 1] | up_drp_rdata_gt_s[ 0];
assign up_drp_ready_s = up_drp_ready_gt_s[15] | up_drp_ready_gt_s[14] |
up_drp_ready_gt_s[13] | up_drp_ready_gt_s[12] |
up_drp_ready_gt_s[11] | up_drp_ready_gt_s[10] |
up_drp_ready_gt_s[ 9] | up_drp_ready_gt_s[ 8] |
up_drp_ready_gt_s[ 7] | up_drp_ready_gt_s[ 6] |
up_drp_ready_gt_s[ 5] | up_drp_ready_gt_s[ 4] |
up_drp_ready_gt_s[ 3] | up_drp_ready_gt_s[ 2] |
up_drp_ready_gt_s[ 1] | up_drp_ready_gt_s[ 0];
assign up_drp_rxrate_s = up_drp_rxrate_gt_s[15] | up_drp_rxrate_gt_s[14] |
up_drp_rxrate_gt_s[13] | up_drp_rxrate_gt_s[12] |
up_drp_rxrate_gt_s[11] | up_drp_rxrate_gt_s[10] |
up_drp_rxrate_gt_s[ 9] | up_drp_rxrate_gt_s[ 8] |
up_drp_rxrate_gt_s[ 7] | up_drp_rxrate_gt_s[ 6] |
up_drp_rxrate_gt_s[ 5] | up_drp_rxrate_gt_s[ 4] |
up_drp_rxrate_gt_s[ 3] | up_drp_rxrate_gt_s[ 2] |
up_drp_rxrate_gt_s[ 1] | up_drp_rxrate_gt_s[ 0];
// asymmetric widths -- receive
assign rx_data = rx_data_s[((PCORE_NUM_OF_RX_LANES*32)-1):0];
assign rx_sof = rx_sof_s[((PCORE_NUM_OF_RX_LANES* 1)-1):0];
assign rx_gt_charisk = rx_gt_charisk_s[((PCORE_NUM_OF_RX_LANES* 4)-1):0];
assign rx_gt_disperr = rx_gt_disperr_s[((PCORE_NUM_OF_RX_LANES* 4)-1):0];
assign rx_gt_notintable = rx_gt_notintable_s[((PCORE_NUM_OF_RX_LANES* 4)-1):0];
assign rx_gt_data = rx_gt_data_s[((PCORE_NUM_OF_RX_LANES*32)-1):0];
generate
if (PCORE_NUM_OF_LANES == PCORE_NUM_OF_RX_LANES) begin
assign rx_data_p_s = rx_data_p;
assign rx_data_n_s = rx_data_n;
assign rx_ip_data_s = rx_ip_data;
end else begin
assign rx_data_p_s[((PCORE_NUM_OF_LANES* 1)-1):(PCORE_NUM_OF_RX_LANES* 1)] = 'd0;
assign rx_data_n_s[((PCORE_NUM_OF_LANES* 1)-1):(PCORE_NUM_OF_RX_LANES* 1)] = 'd0;
assign rx_ip_data_s[((PCORE_NUM_OF_LANES*32)-1):(PCORE_NUM_OF_RX_LANES*32)] = 'd0;
assign rx_data_p_s[((PCORE_NUM_OF_RX_LANES* 1)-1):0] = rx_data_p;
assign rx_data_n_s[((PCORE_NUM_OF_RX_LANES* 1)-1):0] = rx_data_n;
assign rx_ip_data_s[((PCORE_NUM_OF_RX_LANES*32)-1):0] = rx_ip_data;
end
endgenerate
// asymmetric widths -- transmit
assign tx_data_p = tx_data_p_s[((PCORE_NUM_OF_TX_LANES* 1)-1):0];
assign tx_data_n = tx_data_n_s[((PCORE_NUM_OF_TX_LANES* 1)-1):0];
generate
if (PCORE_NUM_OF_LANES == PCORE_NUM_OF_TX_LANES) begin
assign tx_gt_charisk_s = tx_gt_charisk;
assign tx_gt_data_s = tx_gt_data;
end else begin
assign tx_gt_charisk_s[((PCORE_NUM_OF_LANES* 4)-1):(PCORE_NUM_OF_TX_LANES* 4)] = 'd0;
assign tx_gt_data_s[((PCORE_NUM_OF_LANES*32)-1):(PCORE_NUM_OF_TX_LANES*32)] = 'd0;
assign tx_gt_charisk_s[((PCORE_NUM_OF_TX_LANES* 4)-1):0] = tx_gt_charisk;
assign tx_gt_data_s[((PCORE_NUM_OF_TX_LANES*32)-1):0] = tx_gt_data;
end
endgenerate
// transmit data interleave -- since transceivers are shared, lane assignments may not match pin assignments
assign tx_ip_data = tx_data;
assign tx_gt_data_extn_zero_s = 288'd0;
assign tx_gt_charisk_extn_zero_s = 36'd0;
assign tx_gt_data_extn_s = {tx_gt_data_extn_zero_s[(((9-PCORE_NUM_OF_LANES)*32)-1):0], tx_gt_data_s};
assign tx_gt_charisk_extn_s = {tx_gt_charisk_extn_zero_s[(((9-PCORE_NUM_OF_LANES)*4)-1):0], tx_gt_charisk_s};
assign tx_gt_data_mux_s[((8*32)+31):(8*32)] = tx_gt_data_extn_s[((PCORE_TX_LANE_SEL_8*32)+31):(PCORE_TX_LANE_SEL_8*32)];
assign tx_gt_data_mux_s[((7*32)+31):(7*32)] = tx_gt_data_extn_s[((PCORE_TX_LANE_SEL_7*32)+31):(PCORE_TX_LANE_SEL_7*32)];
assign tx_gt_data_mux_s[((6*32)+31):(6*32)] = tx_gt_data_extn_s[((PCORE_TX_LANE_SEL_6*32)+31):(PCORE_TX_LANE_SEL_6*32)];
assign tx_gt_data_mux_s[((5*32)+31):(5*32)] = tx_gt_data_extn_s[((PCORE_TX_LANE_SEL_5*32)+31):(PCORE_TX_LANE_SEL_5*32)];
assign tx_gt_data_mux_s[((4*32)+31):(4*32)] = tx_gt_data_extn_s[((PCORE_TX_LANE_SEL_4*32)+31):(PCORE_TX_LANE_SEL_4*32)];
assign tx_gt_data_mux_s[((3*32)+31):(3*32)] = tx_gt_data_extn_s[((PCORE_TX_LANE_SEL_3*32)+31):(PCORE_TX_LANE_SEL_3*32)];
assign tx_gt_data_mux_s[((2*32)+31):(2*32)] = tx_gt_data_extn_s[((PCORE_TX_LANE_SEL_2*32)+31):(PCORE_TX_LANE_SEL_2*32)];
assign tx_gt_data_mux_s[((1*32)+31):(1*32)] = tx_gt_data_extn_s[((PCORE_TX_LANE_SEL_1*32)+31):(PCORE_TX_LANE_SEL_1*32)];
assign tx_gt_data_mux_s[((0*32)+31):(0*32)] = tx_gt_data_extn_s[((PCORE_TX_LANE_SEL_0*32)+31):(PCORE_TX_LANE_SEL_0*32)];
assign tx_gt_charisk_mux_s[((8*4)+3):(8*4)] = tx_gt_charisk_extn_s[((PCORE_TX_LANE_SEL_8*4)+3):(PCORE_TX_LANE_SEL_8*4)];
assign tx_gt_charisk_mux_s[((7*4)+3):(7*4)] = tx_gt_charisk_extn_s[((PCORE_TX_LANE_SEL_7*4)+3):(PCORE_TX_LANE_SEL_7*4)];
assign tx_gt_charisk_mux_s[((6*4)+3):(6*4)] = tx_gt_charisk_extn_s[((PCORE_TX_LANE_SEL_6*4)+3):(PCORE_TX_LANE_SEL_6*4)];
assign tx_gt_charisk_mux_s[((5*4)+3):(5*4)] = tx_gt_charisk_extn_s[((PCORE_TX_LANE_SEL_5*4)+3):(PCORE_TX_LANE_SEL_5*4)];
assign tx_gt_charisk_mux_s[((4*4)+3):(4*4)] = tx_gt_charisk_extn_s[((PCORE_TX_LANE_SEL_4*4)+3):(PCORE_TX_LANE_SEL_4*4)];
assign tx_gt_charisk_mux_s[((3*4)+3):(3*4)] = tx_gt_charisk_extn_s[((PCORE_TX_LANE_SEL_3*4)+3):(PCORE_TX_LANE_SEL_3*4)];
assign tx_gt_charisk_mux_s[((2*4)+3):(2*4)] = tx_gt_charisk_extn_s[((PCORE_TX_LANE_SEL_2*4)+3):(PCORE_TX_LANE_SEL_2*4)];
assign tx_gt_charisk_mux_s[((1*4)+3):(1*4)] = tx_gt_charisk_extn_s[((PCORE_TX_LANE_SEL_1*4)+3):(PCORE_TX_LANE_SEL_1*4)];
assign tx_gt_charisk_mux_s[((0*4)+3):(0*4)] = tx_gt_charisk_extn_s[((PCORE_TX_LANE_SEL_0*4)+3):(PCORE_TX_LANE_SEL_0*4)];
// clock buffers
generate
if (PCORE_DEVICE_TYPE == 0) begin
BUFG i_bufg_rx_clk (
.I (rx_out_clk[0]),
.O (rx_clk_g));
end
if (PCORE_DEVICE_TYPE == 0) begin
BUFG i_bufg_tx_clk (
.I (tx_out_clk[0]),
.O (tx_clk_g));
end
if (PCORE_DEVICE_TYPE == 1) begin
BUFG_GT i_bufg_rx_clk (
.I (rx_out_clk[0]),
.O (rx_clk_g));
end
if (PCORE_DEVICE_TYPE == 1) begin
BUFG_GT i_bufg_tx_clk (
.I (tx_out_clk[0]),
.O (tx_clk_g));
end
endgenerate
// transceivers
assign qpll_clk = {{4{qpll_clk_1}}, {4{qpll_clk_0}}};
assign qpll_ref_clk = {{4{qpll_ref_clk_1}}, {4{qpll_ref_clk_0}}};
assign qpll_locked_s = {{4{qpll_locked_1_s}}, {4{qpll_locked_0_s}}};
ad_gt_common_1 #(
.DRP_ID (14),
.GTH_GTX_N (PCORE_DEVICE_TYPE),
.QPLL_REFCLK_DIV (PCORE_QPLL_REFCLK_DIV),
.QPLL_CFG (PCORE_QPLL_CFG),
.QPLL_FBDIV_RATIO (PCORE_QPLL_FBDIV_RATIO),
.QPLL_FBDIV (PCORE_QPLL_FBDIV))
i_gt_common_1 (
.rst (gt_pll_rst),
.ref_clk (ref_clk_q),
.qpll_clk (qpll_clk_0),
.qpll_ref_clk (qpll_ref_clk_0),
.qpll_locked (qpll_locked_0_s),
.up_clk (up_clk),
.up_drp_sel (up_drp_sel_s),
.up_drp_addr (up_drp_addr_s),
.up_drp_wr (up_drp_wr_s),
.up_drp_wdata (up_drp_wdata_s),
.up_drp_rdata (up_drp_rdata_gt_s[14]),
.up_drp_ready (up_drp_ready_gt_s[14]),
.up_drp_lanesel (up_drp_lanesel_s),
.up_drp_rxrate (up_drp_rxrate_gt_s[14]));
ad_gt_common_1 #(
.DRP_ID (15),
.GTH_GTX_N (PCORE_DEVICE_TYPE),
.QPLL_REFCLK_DIV (PCORE_QPLL_REFCLK_DIV),
.QPLL_CFG (PCORE_QPLL_CFG),
.QPLL_FBDIV_RATIO (PCORE_QPLL_FBDIV_RATIO),
.QPLL_FBDIV (PCORE_QPLL_FBDIV))
i_gt_common_2 (
.rst (gt_pll_rst),
.ref_clk (ref_clk_q),
.qpll_clk (qpll_clk_1),
.qpll_ref_clk (qpll_ref_clk_1),
.qpll_locked (qpll_locked_1_s),
.up_clk (up_clk),
.up_drp_sel (up_drp_sel_s),
.up_drp_addr (up_drp_addr_s),
.up_drp_wr (up_drp_wr_s),
.up_drp_wdata (up_drp_wdata_s),
.up_drp_rdata (up_drp_rdata_gt_s[15]),
.up_drp_ready (up_drp_ready_gt_s[15]),
.up_drp_lanesel (up_drp_lanesel_s),
.up_drp_rxrate (up_drp_rxrate_gt_s[15]));
genvar n;
generate
for (n = PCORE_NUM_OF_LANES; n < 14; n = n + 1) begin: g_unused_1
assign up_drp_rdata_gt_s[n] = 'd0;
assign up_drp_ready_gt_s[n] = 'd0;
assign up_drp_rxrate_gt_s[n] = 'd0;
end
for (n = 0; n < PCORE_NUM_OF_LANES; n = n + 1) begin: g_lane_1
ad_jesd_align i_jesd_align (
.rx_clk (rx_clk),
.rx_ip_sof (rx_ip_sof),
.rx_ip_data (rx_ip_data_s[n*32+31:n*32]),
.rx_sof (rx_sof_s[n]),
.rx_data (rx_data_s[n*32+31:n*32]));
ad_gt_channel_1 #(
.DRP_ID (n),
.GTH_GTX_N (PCORE_DEVICE_TYPE),
.CPLL_FBDIV (PCORE_CPLL_FBDIV),
.RX_OUT_DIV (PCORE_RX_OUT_DIV),
.TX_OUT_DIV (PCORE_TX_OUT_DIV),
.RX_CLK25_DIV (PCORE_RX_CLK25_DIV),
.TX_CLK25_DIV (PCORE_TX_CLK25_DIV),
.PMA_RSV (PCORE_PMA_RSV),
.RX_CDR_CFG (PCORE_RX_CDR_CFG))
i_gt_channel_1 (
.ref_clk (ref_clk_c),
.lpm_dfe_n (up_lpm_dfe_n_s),
.cpll_pd (up_cpll_pd_s),
.cpll_rst (gt_pll_rst),
.qpll_clk (qpll_clk[n]),
.qpll_ref_clk (qpll_ref_clk[n]),
.qpll_locked (qpll_locked_s[n]),
.rx_rst (gt_rx_rst),
.rx_p (rx_data_p_s[n]),
.rx_n (rx_data_n_s[n]),
.rx_sys_clk_sel (up_rx_sys_clk_sel_s),
.rx_out_clk_sel (up_rx_out_clk_sel_s),
.rx_out_clk (rx_out_clk[n]),
.rx_rst_done (rx_rst_done_s[n]),
.rx_pll_locked (rx_pll_locked_s[n]),
.rx_clk (rx_clk),
.rx_charisk (rx_gt_charisk_s[n*4+3:n*4]),
.rx_disperr (rx_gt_disperr_s[n*4+3:n*4]),
.rx_notintable (rx_gt_notintable_s[n*4+3:n*4]),
.rx_data (rx_gt_data_s[n*32+31:n*32]),
.rx_comma_align_enb (rx_ip_comma_align),
.rx_ilas_f (rx_ilas_f_s[n*4+3:n*4]),
.rx_ilas_q (rx_ilas_q_s[n*4+3:n*4]),
.rx_ilas_a (rx_ilas_a_s[n*4+3:n*4]),
.rx_ilas_r (rx_ilas_r_s[n*4+3:n*4]),
.rx_cgs_k (rx_cgs_k_s[n*4+3:n*4]),
.tx_rst (gt_tx_rst),
.tx_p (tx_data_p_s[n]),
.tx_n (tx_data_n_s[n]),
.tx_sys_clk_sel (up_tx_sys_clk_sel_s),
.tx_out_clk_sel (up_tx_out_clk_sel_s),
.tx_out_clk (tx_out_clk[n]),
.tx_rst_done (tx_rst_done_s[n]),
.tx_pll_locked (tx_pll_locked_s[n]),
.tx_clk (tx_clk),
.tx_charisk (tx_gt_charisk_mux_s[n*4+3:n*4]),
.tx_data (tx_gt_data_mux_s[n*32+31:n*32]),
.up_clk (up_clk),
.up_drp_sel (up_drp_sel_s),
.up_drp_addr (up_drp_addr_s),
.up_drp_wr (up_drp_wr_s),
.up_drp_wdata (up_drp_wdata_s),
.up_drp_rdata (up_drp_rdata_gt_s[n]),
.up_drp_ready (up_drp_ready_gt_s[n]),
.up_drp_lanesel (up_drp_lanesel_s),
.up_drp_rxrate (up_drp_rxrate_gt_s[n]));
end
endgenerate
// eye scan
ad_gt_es #(.GTH_GTX_N(PCORE_DEVICE_TYPE)) i_gt_es (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_es_drp_sel (up_es_drp_sel_s),
.up_es_drp_wr (up_es_drp_wr_s),
.up_es_drp_addr (up_es_drp_addr_s),
.up_es_drp_wdata (up_es_drp_wdata_s),
.up_es_drp_rdata (up_es_drp_rdata_s),
.up_es_drp_ready (up_es_drp_ready_s),
.axi_awvalid (m_axi_awvalid),
.axi_awaddr (m_axi_awaddr),
.axi_awprot (m_axi_awprot),
.axi_awready (m_axi_awready),
.axi_wvalid (m_axi_wvalid),
.axi_wdata (m_axi_wdata),
.axi_wstrb (m_axi_wstrb),
.axi_wready (m_axi_wready),
.axi_bvalid (m_axi_bvalid),
.axi_bresp (m_axi_bresp),
.axi_bready (m_axi_bready),
.axi_arvalid (m_axi_arvalid),
.axi_araddr (m_axi_araddr),
.axi_arprot (m_axi_arprot),
.axi_arready (m_axi_arready),
.axi_rvalid (m_axi_rvalid),
.axi_rdata (m_axi_rdata),
.axi_rresp (m_axi_rresp),
.axi_rready (m_axi_rready),
.up_lpm_dfe_n (up_lpm_dfe_n_s),
.up_es_start (up_es_start_s),
.up_es_stop (up_es_stop_s),
.up_es_init (up_es_init_s),
.up_es_sdata0 (up_es_sdata0_s),
.up_es_sdata1 (up_es_sdata1_s),
.up_es_sdata2 (up_es_sdata2_s),
.up_es_sdata3 (up_es_sdata3_s),
.up_es_sdata4 (up_es_sdata4_s),
.up_es_qdata0 (up_es_qdata0_s),
.up_es_qdata1 (up_es_qdata1_s),
.up_es_qdata2 (up_es_qdata2_s),
.up_es_qdata3 (up_es_qdata3_s),
.up_es_qdata4 (up_es_qdata4_s),
.up_es_prescale (up_es_prescale_s),
.up_es_hoffset_min (up_es_hoffset_min_s),
.up_es_hoffset_max (up_es_hoffset_max_s),
.up_es_hoffset_step (up_es_hoffset_step_s),
.up_es_voffset_min (up_es_voffset_min_s),
.up_es_voffset_max (up_es_voffset_max_s),
.up_es_voffset_step (up_es_voffset_step_s),
.up_es_voffset_range (up_es_voffset_range_s),
.up_es_start_addr (up_es_start_addr_s),
.up_es_dmaerr (up_es_dmaerr_s),
.up_es_status (up_es_status_s));
// processor
up_gt #(.PCORE_ID(PCORE_ID), .PCORE_DEVICE_TYPE(PCORE_DEVICE_TYPE)) i_up_gt (
.gt_pll_rst (gt_pll_rst),
.gt_rx_rst (gt_rx_rst),
.gt_tx_rst (gt_tx_rst),
.up_lpm_dfe_n (up_lpm_dfe_n_s),
.up_cpll_pd (up_cpll_pd_s),
.up_rx_sys_clk_sel (up_rx_sys_clk_sel_s),
.up_rx_out_clk_sel (up_rx_out_clk_sel_s),
.up_tx_sys_clk_sel (up_tx_sys_clk_sel_s),
.up_tx_out_clk_sel (up_tx_out_clk_sel_s),
.rx_clk (rx_clk),
.rx_rst (rx_rst),
.rx_jesd_rst (rx_jesd_rst),
.rx_ext_sysref (rx_ext_sysref),
.rx_sysref (rx_sysref),
.rx_ip_sync (rx_ip_sync),
.rx_sync (rx_sync),
.rx_rst_done (rx_rst_done_extn_s[7:0]),
.rx_pll_locked (rx_pll_locked_extn_s[7:0]),
.rx_error (1'd0),
.rx_rst_done_up (rx_rst_done),
.tx_clk (tx_clk),
.tx_rst (tx_rst),
.tx_jesd_rst (tx_jesd_rst),
.tx_ext_sysref (tx_ext_sysref),
.tx_sysref (tx_sysref),
.tx_sync (tx_sync),
.tx_ip_sync (tx_ip_sync),
.tx_rst_done (tx_rst_done_extn_s[7:0]),
.tx_pll_locked (tx_pll_locked_extn_s[7:0]),
.tx_error (1'd0),
.tx_rst_done_up (tx_rst_done),
.up_drp_sel (up_drp_sel_s),
.up_drp_wr (up_drp_wr_s),
.up_drp_addr (up_drp_addr_s),
.up_drp_wdata (up_drp_wdata_s),
.up_drp_rdata (up_drp_rdata_s),
.up_drp_ready (up_drp_ready_s),
.up_drp_lanesel (up_drp_lanesel_s),
.up_drp_rxrate (up_drp_rxrate_s),
.up_es_drp_sel (up_es_drp_sel_s),
.up_es_drp_wr (up_es_drp_wr_s),
.up_es_drp_addr (up_es_drp_addr_s),
.up_es_drp_wdata (up_es_drp_wdata_s),
.up_es_drp_rdata (up_es_drp_rdata_s),
.up_es_drp_ready (up_es_drp_ready_s),
.up_es_start (up_es_start_s),
.up_es_stop (up_es_stop_s),
.up_es_init (up_es_init_s),
.up_es_prescale (up_es_prescale_s),
.up_es_voffset_range (up_es_voffset_range_s),
.up_es_voffset_step (up_es_voffset_step_s),
.up_es_voffset_max (up_es_voffset_max_s),
.up_es_voffset_min (up_es_voffset_min_s),
.up_es_hoffset_max (up_es_hoffset_max_s),
.up_es_hoffset_min (up_es_hoffset_min_s),
.up_es_hoffset_step (up_es_hoffset_step_s),
.up_es_start_addr (up_es_start_addr_s),
.up_es_sdata0 (up_es_sdata0_s),
.up_es_sdata1 (up_es_sdata1_s),
.up_es_sdata2 (up_es_sdata2_s),
.up_es_sdata3 (up_es_sdata3_s),
.up_es_sdata4 (up_es_sdata4_s),
.up_es_qdata0 (up_es_qdata0_s),
.up_es_qdata1 (up_es_qdata1_s),
.up_es_qdata2 (up_es_qdata2_s),
.up_es_qdata3 (up_es_qdata3_s),
.up_es_qdata4 (up_es_qdata4_s),
.up_es_dmaerr (up_es_dmaerr_s),
.up_es_status (up_es_status_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s),
.up_rack (up_rack_s));
// axi interface
up_axi i_up_axi (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_axi_awvalid (s_axi_awvalid),
.up_axi_awaddr (s_axi_awaddr),
.up_axi_awready (s_axi_awready),
.up_axi_wvalid (s_axi_wvalid),
.up_axi_wdata (s_axi_wdata),
.up_axi_wstrb (s_axi_wstrb),
.up_axi_wready (s_axi_wready),
.up_axi_bvalid (s_axi_bvalid),
.up_axi_bresp (s_axi_bresp),
.up_axi_bready (s_axi_bready),
.up_axi_arvalid (s_axi_arvalid),
.up_axi_araddr (s_axi_araddr),
.up_axi_arready (s_axi_arready),
.up_axi_rvalid (s_axi_rvalid),
.up_axi_rresp (s_axi_rresp),
.up_axi_rdata (s_axi_rdata),
.up_axi_rready (s_axi_rready),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s),
.up_rack (up_rack_s));
endmodule
// ***************************************************************************
// ***************************************************************************
|
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module SoC_onchip_memory2_0 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
)
;
parameter INIT_FILE = "SoC_onchip_memory2_0.hex";
output [ 31: 0] readdata;
input [ 14: 0] address;
input [ 3: 0] byteenable;
input chipselect;
input clk;
input clken;
input reset;
input reset_req;
input write;
input [ 31: 0] writedata;
wire clocken0;
wire [ 31: 0] readdata;
wire wren;
assign wren = chipselect & write;
assign clocken0 = clken & ~reset_req;
altsyncram the_altsyncram
(
.address_a (address),
.byteena_a (byteenable),
.clock0 (clk),
.clocken0 (clocken0),
.data_a (writedata),
.q_a (readdata),
.wren_a (wren)
);
defparam the_altsyncram.byte_size = 8,
the_altsyncram.init_file = INIT_FILE,
the_altsyncram.lpm_type = "altsyncram",
the_altsyncram.maximum_depth = 32768,
the_altsyncram.numwords_a = 32768,
the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.width_a = 32,
the_altsyncram.width_byteena_a = 4,
the_altsyncram.widthad_a = 15;
//s1, which is an e_avalon_slave
//s2, which is an e_avalon_slave
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NOR2B_1_V
`define SKY130_FD_SC_HDLL__NOR2B_1_V
/**
* nor2b: 2-input NOR, first input inverted.
*
* Y = !(A | B | C | !D)
*
* Verilog wrapper for nor2b with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__nor2b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__nor2b_1 (
Y ,
A ,
B_N ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__nor2b base (
.Y(Y),
.A(A),
.B_N(B_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__nor2b_1 (
Y ,
A ,
B_N
);
output Y ;
input A ;
input B_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__nor2b base (
.Y(Y),
.A(A),
.B_N(B_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NOR2B_1_V
|
//
// Generated by Bluespec Compiler, version 2011.03.beta1 (build 23381, 2011-03-08)
//
// On Fri May 6 07:43:57 EDT 2011
//
//
// Ports:
// Name I/O size props
// RDY_usr_sw O 1 const
// led O 8 reg
// RDY_led O 1 const
// debug O 32 reg
// RDY_debug O 1 const
// p200clk O 1
// CLK_GATE_p200clk O 1 const
// p200rst O 1
// sys0_clk I 1
// sys0_rstn I 1
// usr_sw_i I 8 reg
// EN_usr_sw I 1
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
module mkFTop_kc705(sys0_clk,
sys0_rstn,
usr_sw_i,
EN_usr_sw,
RDY_usr_sw,
led,
RDY_led,
debug,
RDY_debug,
p200clk,
CLK_GATE_p200clk,
p200rst);
input sys0_clk;
input sys0_rstn;
// action method usr_sw
input [7 : 0] usr_sw_i;
input EN_usr_sw;
output RDY_usr_sw;
// value method led
output [7 : 0] led;
output RDY_led;
// value method debug
output [31 : 0] debug;
output RDY_debug;
// oscillator and gates for output clock p200clk
output p200clk;
output CLK_GATE_p200clk;
// output resets
output p200rst;
// signals for module outputs
wire [31 : 0] debug;
wire [7 : 0] led;
wire CLK_GATE_p200clk, RDY_debug, RDY_led, RDY_usr_sw, p200clk, p200rst;
// register freeCnt
reg [31 : 0] freeCnt;
wire [31 : 0] freeCnt$D_IN;
wire freeCnt$EN;
// register swReg
reg [7 : 0] swReg;
wire [7 : 0] swReg$D_IN;
wire swReg$EN;
// oscillator and gates for output clock p200clk
assign p200clk = sys0_clk ;
assign CLK_GATE_p200clk = 1'd1 ;
// output resets
assign p200rst = sys0_rstn ;
// action method usr_sw
assign RDY_usr_sw = 1'd1 ;
// value method led
assign led = swReg ;
assign RDY_led = 1'd1 ;
// value method debug
assign debug = freeCnt ;
assign RDY_debug = 1'd1 ;
// register freeCnt
assign freeCnt$D_IN = freeCnt + 32'd1 ;
assign freeCnt$EN = 1'd1 ;
// register swReg
assign swReg$D_IN = usr_sw_i ;
assign swReg$EN = EN_usr_sw ;
// handling of inlined registers
always@(posedge sys0_clk)
begin
if (!sys0_rstn)
begin
freeCnt <= `BSV_ASSIGNMENT_DELAY 32'd0;
swReg <= `BSV_ASSIGNMENT_DELAY 8'd0;
end
else
begin
if (freeCnt$EN) freeCnt <= `BSV_ASSIGNMENT_DELAY freeCnt$D_IN;
if (swReg$EN) swReg <= `BSV_ASSIGNMENT_DELAY swReg$D_IN;
end
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
freeCnt = 32'hAAAAAAAA;
swReg = 8'hAA;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
endmodule // mkFTop_kc705
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__OR4B_4_V
`define SKY130_FD_SC_HD__OR4B_4_V
/**
* or4b: 4-input OR, first input inverted.
*
* Verilog wrapper for or4b with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__or4b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__or4b_4 (
X ,
A ,
B ,
C ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__or4b base (
.X(X),
.A(A),
.B(B),
.C(C),
.D_N(D_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__or4b_4 (
X ,
A ,
B ,
C ,
D_N
);
output X ;
input A ;
input B ;
input C ;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__or4b base (
.X(X),
.A(A),
.B(B),
.C(C),
.D_N(D_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__OR4B_4_V
|
//--------------------------------------------------------------------------------
// clockman.vhd
//
// Author: Michael "Mr. Sump" Poppitz
//
// Details: http://www.sump.org/projects/analyzer/
//
// This is only a wrapper for Xilinx' DCM component so it doesn't
// have to go in the main code and can be replaced more easily.
//
// Creates 100Mhz core clk0 from 50Mhz input reference clock.
//
//--------------------------------------------------------------------------------
//
// 12/29/2010 - Verilog Version created by Ian Davis - mygizmos.org
//
`timescale 1ns/100ps
module pll_wrapper (clkin, clk0);
input clkin; // clock input
output clk0; // double clock rate output
parameter TRUE = 1'b1;
parameter FALSE = 1'b0;
wire clkin;
wire clk0;
wire clkfb;
wire clkfbbuf;
// DCM: Digital Clock Manager Circuit for Virtex-II/II-Pro and Spartan-3/3E
// Xilinx HDL Language Template version 8.1i
DCM DCM_baseClock (
.CLKIN(clkin), // Clock input (from IBUFG, BUFG or DCM)
.PSCLK(1'b 0), // Dynamic phase adjust clock input
.PSEN(1'b 0), // Dynamic phase adjust enable input
.PSINCDEC(1'b 0), // Dynamic phase adjust increment/decrement
.RST(1'b 0), // DCM asynchronous reset input
.CLK2X(clk0),
.CLK0(clkfb),
.CLKFB(clkfbbuf));
// synthesis attribute declarations
/* synopsys attribute
DESKEW_ADJUST "SYSTEM_SYNCHRONOUS"
DLL_FREQUENCY_MODE "LOW"
DUTY_CYCLE_CORRECTION "TRUE"
STARTUP_WAIT "TRUE"
*/
BUFG BUFG_clkfb(.I(clkfb), .O(clkfbbuf));
endmodule
|
// ****************************************************************************
// Copyright : NUDT.
// ============================================================================
// FILE NAME : SGMII_RX.v
// CREATE DATE : 2013-12-03
// AUTHOR : ZengQiang
// AUTHOR'S EMAIL : [email protected]
// AUTHOR'S TEL :
// ============================================================================
// RELEASE HISTORY -------------------------------------------------------
// VERSION DATE AUTHOR DESCRIPTION
// 1.0 2013-12-03 ZengQiang Original Verison
// ============================================================================
// KEYWORDS : N/A
// ----------------------------------------------------------------------------
// PURPOSE : MAC core output 8bit pkt format transform 134bit pkt format
// ----------------------------------------------------------------------------
// ============================================================================
// REUSE ISSUES
// Reset Strategy : Async clear,active high
// Clock Domains : ff_rx_clk
// Critical TiminG : N/A
// Instantiations : N/A
// Synthesizable : N/A
// Others : N/A
// ****************************************************************************
module SGMII_RX1
(reset,
ff_rx_clk,
ff_rx_rdy,
ff_rx_data,
ff_rx_sop,
ff_rx_eop,
rx_err,
rx_err_stat,
rx_frm_type,
ff_rx_dsav,
ff_rx_dval,
ff_rx_a_full,
ff_rx_a_empty,
pkt_receive_add,
pkt_discard_add,
out_pkt_wrreq,
out_pkt,
out_pkt_almostfull,
out_valid_wrreq,
out_valid
);
input reset;
input ff_rx_clk;
output ff_rx_rdy;
input [7:0] ff_rx_data;
input ff_rx_sop;
input ff_rx_eop;
input [5:0] rx_err;
input [17:0] rx_err_stat;
input [3:0] rx_frm_type;
input ff_rx_dsav;
input ff_rx_dval;
input ff_rx_a_full;
input ff_rx_a_empty;
output pkt_receive_add;
output pkt_discard_add;
output out_pkt_wrreq;
output [133:0] out_pkt;
input out_pkt_almostfull;
output out_valid_wrreq;
output out_valid;
reg ff_rx_rdy;
reg pkt_receive_add;
reg pkt_discard_add;
reg out_pkt_wrreq;
reg [133:0] out_pkt;
reg out_valid_wrreq;
reg out_valid;
reg [4:0]current_state;
parameter //idle_s = 5'b00000,
transmit_byte0_s = 5'b00001,
transmit_byte1_s = 5'b00010,
transmit_byte2_s = 5'b00011,
transmit_byte3_s = 5'b00100,
transmit_byte4_s = 5'b00101,
transmit_byte5_s = 5'b00110,
transmit_byte6_s = 5'b00111,
transmit_byte7_s = 5'b01000,
transmit_byte8_s = 5'b01001,
transmit_byte9_s = 5'b01010,
transmit_byte10_s = 5'b01011,
transmit_byte11_s = 5'b01100,
transmit_byte12_s = 5'b01101,
transmit_byte13_s = 5'b01110,
transmit_byte14_s = 5'b01111,
transmit_byte15_s = 5'b10000,
discard_s = 5'b10001;
always@(posedge ff_rx_clk or negedge reset)
if(!reset) begin
ff_rx_rdy <= 1'b0;
out_pkt_wrreq <= 1'b0;
out_pkt <= 134'b0;
out_valid_wrreq <= 1'b0;
out_valid <= 1'b0;
pkt_receive_add <= 1'b0;
pkt_discard_add <= 1'b0;
current_state <= transmit_byte0_s;
end
else begin
ff_rx_rdy <= 1'b1;
case(current_state)
transmit_byte0_s: begin
out_valid_wrreq <= 1'b0;
out_valid <= 1'b0;
out_pkt_wrreq <= 1'b0;
if(ff_rx_dval == 1'b1) begin//data valid
out_pkt[127:120] <= ff_rx_data;
if(ff_rx_sop == 1'b1) begin //pkt head
if(!out_pkt_almostfull) begin//FIFO can receive a 1518B pkt
out_pkt[133:132] <= 2'b01;
pkt_receive_add <= 1'b1;
current_state <= transmit_byte1_s;
end
else begin
pkt_discard_add <= 1'b1;
current_state <= discard_s;
end
end
else if(ff_rx_eop == 1'b1) begin//pkt tail
out_pkt[133:132] <= 2'b10;
out_pkt[131:128] <= 4'b1111;
out_pkt_wrreq <= 1'b1;
if(rx_err == 6'b0) begin//pkt error
out_valid_wrreq <= 1'b1;
out_valid <= 1'b1;
end
else begin
out_valid_wrreq <= 1'b1;
out_valid <= 1'b0;
end
current_state <= transmit_byte0_s;
end
else begin
out_pkt[133:132] <= 2'b11;
current_state <= transmit_byte1_s;
end
end
else begin
current_state <= transmit_byte0_s;
end
end
transmit_byte1_s: begin
out_pkt_wrreq <= 1'b0;
pkt_receive_add <= 1'b0;
if(ff_rx_dval == 1'b1) begin//data valid
out_pkt[119:112] <= ff_rx_data;
if(ff_rx_eop == 1'b1) begin//pkt head
out_pkt[133:132] <= 2'b10;
out_pkt[131:128] <= 4'b1110;
out_pkt_wrreq <= 1'b1;
if(rx_err == 6'b0) begin//pkt error
out_valid_wrreq <= 1'b1;
out_valid <= 1'b1;
end
else begin
out_valid_wrreq <= 1'b1;
out_valid <= 1'b0;
end
current_state <= transmit_byte0_s;
end
else begin
//out_pkt[133:132] <= 2'b11;
current_state <= transmit_byte2_s;
end
end
else begin
current_state <= transmit_byte1_s;
end
end
transmit_byte2_s: begin
out_pkt_wrreq <= 1'b0;
if(ff_rx_dval == 1'b1) begin
out_pkt[111:104] <= ff_rx_data;
if(ff_rx_eop == 1'b1) begin
out_pkt[133:132] <= 2'b10;
out_pkt[131:128] <= 4'b1101;
out_pkt_wrreq <= 1'b1;
if(rx_err == 6'b0) begin
out_valid_wrreq <= 1'b1;
out_valid <= 1'b1;
end
else begin
out_valid_wrreq <= 1'b1;
out_valid <= 1'b0;
end
current_state <= transmit_byte0_s;
end
else begin
//out_pkt[133:132] <= 2'b11;
current_state <= transmit_byte3_s;
end
end
else begin
current_state <= transmit_byte2_s;
end
end
transmit_byte3_s: begin
out_pkt_wrreq <= 1'b0;
if(ff_rx_dval == 1'b1) begin
out_pkt[103:96] <= ff_rx_data;
if(ff_rx_eop == 1'b1) begin
out_pkt[133:132] <= 2'b10;
out_pkt[131:128] <= 4'b1100;
out_pkt_wrreq <= 1'b1;
if(rx_err == 6'b0) begin
out_valid_wrreq <= 1'b1;
out_valid <= 1'b1;
end
else begin
out_valid_wrreq <= 1'b1;
out_valid <= 1'b0;
end
current_state <= transmit_byte0_s;
end
else begin
//out_pkt[133:132] <= 2'b11;
current_state <= transmit_byte4_s;
end
end
else begin
current_state <= transmit_byte3_s;
end
end
transmit_byte4_s: begin
out_pkt_wrreq <= 1'b0;
if(ff_rx_dval == 1'b1) begin
out_pkt[95:88] <= ff_rx_data;
if(ff_rx_eop == 1'b1) begin
out_pkt[133:132] <= 2'b10;
out_pkt[131:128] <= 4'b1011;
out_pkt_wrreq <= 1'b1;
if(rx_err == 6'b0) begin
out_valid_wrreq <= 1'b1;
out_valid <= 1'b1;
end
else begin
out_valid_wrreq <= 1'b1;
out_valid <= 1'b0;
end
current_state <= transmit_byte0_s;
end
else begin
//out_pkt[133:132] <= 2'b11;
current_state <= transmit_byte5_s;
end
end
else begin
current_state <= transmit_byte4_s;
end
end
transmit_byte5_s: begin
out_pkt_wrreq <= 1'b0;
if(ff_rx_dval == 1'b1) begin
out_pkt[87:80] <= ff_rx_data;
if(ff_rx_eop == 1'b1) begin
out_pkt[133:132] <= 2'b10;
out_pkt[131:128] <= 4'b1010;
out_pkt_wrreq <= 1'b1;
if(rx_err == 6'b0) begin
out_valid_wrreq <= 1'b1;
out_valid <= 1'b1;
end
else begin
out_valid_wrreq <= 1'b1;
out_valid <= 1'b0;
end
current_state <= transmit_byte0_s;
end
else begin
//out_pkt[133:132] <= 2'b11;
current_state <= transmit_byte6_s;
end
end
else begin
current_state <= transmit_byte5_s;
end
end
transmit_byte6_s: begin
out_pkt_wrreq <= 1'b0;
if(ff_rx_dval == 1'b1) begin
out_pkt[79:72] <= ff_rx_data;
if(ff_rx_eop == 1'b1) begin
out_pkt[133:132] <= 2'b10;
out_pkt[131:128] <= 4'b1001;
out_pkt_wrreq <= 1'b1;
if(rx_err == 6'b0) begin
out_valid_wrreq <= 1'b1;
out_valid <= 1'b1;
end
else begin
out_valid_wrreq <= 1'b1;
out_valid <= 1'b0;
end
current_state <= transmit_byte0_s;
end
else begin
//out_pkt[133:132] <= 2'b11;
current_state <= transmit_byte7_s;
end
end
else begin
current_state <= transmit_byte6_s;
end
end
transmit_byte7_s: begin
out_pkt_wrreq <= 1'b0;
if(ff_rx_dval == 1'b1) begin
out_pkt[71:64] <= ff_rx_data;
if(ff_rx_eop == 1'b1) begin
out_pkt[133:132] <= 2'b10;
out_pkt[131:128] <= 4'b1000;
out_pkt_wrreq <= 1'b1;
if(rx_err == 6'b0) begin
out_valid_wrreq <= 1'b1;
out_valid <= 1'b1;
end
else begin
out_valid_wrreq <= 1'b1;
out_valid <= 1'b0;
end
current_state <= transmit_byte0_s;
end
else begin
//out_pkt[133:132] <= 2'b11;
current_state <= transmit_byte8_s;
end
end
else begin
current_state <= transmit_byte7_s;
end
end
transmit_byte8_s: begin
out_pkt_wrreq <= 1'b0;
if(ff_rx_dval == 1'b1) begin
out_pkt[63:56] <= ff_rx_data;
if(ff_rx_eop == 1'b1) begin
out_pkt[133:132] <= 2'b10;
out_pkt[131:128] <= 4'b0111;
out_pkt_wrreq <= 1'b1;
if(rx_err == 6'b0) begin
out_valid_wrreq <= 1'b1;
out_valid <= 1'b1;
end
else begin
out_valid_wrreq <= 1'b1;
out_valid <= 1'b0;
end
current_state <= transmit_byte0_s;
end
else begin
//out_pkt[133:132] <= 2'b11;
current_state <= transmit_byte9_s;
end
end
else begin
current_state <= transmit_byte8_s;
end
end
transmit_byte9_s: begin
out_pkt_wrreq <= 1'b0;
if(ff_rx_dval == 1'b1) begin
out_pkt[55:48] <= ff_rx_data;
if(ff_rx_eop == 1'b1) begin
out_pkt[133:132] <= 2'b10;
out_pkt[131:128] <= 4'b0110;
out_pkt_wrreq <= 1'b1;
if(rx_err == 6'b0) begin
out_valid_wrreq <= 1'b1;
out_valid <= 1'b1;
end
else begin
out_valid_wrreq <= 1'b1;
out_valid <= 1'b0;
end
current_state <= transmit_byte0_s;
end
else begin
//out_pkt[133:132] <= 2'b11;
current_state <= transmit_byte10_s;
end
end
else begin
current_state <= transmit_byte9_s;
end
end
transmit_byte10_s: begin
out_pkt_wrreq <= 1'b0;
if(ff_rx_dval == 1'b1) begin
out_pkt[47:40] <= ff_rx_data;
if(ff_rx_eop == 1'b1) begin
out_pkt[133:132] <= 2'b10;
out_pkt[131:128] <= 4'b0101;
out_pkt_wrreq <= 1'b1;
if(rx_err == 6'b0) begin
out_valid_wrreq <= 1'b1;
out_valid <= 1'b1;
end
else begin
out_valid_wrreq <= 1'b1;
out_valid <= 1'b0;
end
current_state <= transmit_byte0_s;
end
else begin
//out_pkt[133:132] <= 2'b11;
current_state <= transmit_byte11_s;
end
end
else begin
current_state <= transmit_byte10_s;
end
end
transmit_byte11_s: begin
out_pkt_wrreq <= 1'b0;
if(ff_rx_dval == 1'b1) begin
out_pkt[39:32] <= ff_rx_data;
if(ff_rx_eop == 1'b1) begin
out_pkt[133:132] <= 2'b10;
out_pkt[131:128] <= 4'b0100;
out_pkt_wrreq <= 1'b1;
if(rx_err == 6'b0) begin
out_valid_wrreq <= 1'b1;
out_valid <= 1'b1;
end
else begin
out_valid_wrreq <= 1'b1;
out_valid <= 1'b0;
end
current_state <= transmit_byte0_s;
end
else begin
//out_pkt[133:132] <= 2'b11;
current_state <= transmit_byte12_s;
end
end
else begin
current_state <= transmit_byte11_s;
end
end
transmit_byte12_s: begin
out_pkt_wrreq <= 1'b0;
if(ff_rx_dval == 1'b1) begin
out_pkt[31:24] <= ff_rx_data;
if(ff_rx_eop == 1'b1) begin
out_pkt[133:132] <= 2'b10;
out_pkt[131:128] <= 4'b0011;
out_pkt_wrreq <= 1'b1;
if(rx_err == 6'b0) begin
out_valid_wrreq <= 1'b1;
out_valid <= 1'b1;
end
else begin
out_valid_wrreq <= 1'b1;
out_valid <= 1'b0;
end
current_state <= transmit_byte0_s;
end
else begin
//out_pkt[133:132] <= 2'b11;
current_state <= transmit_byte13_s;
end
end
else begin
current_state <= transmit_byte12_s;
end
end
transmit_byte13_s: begin
out_pkt_wrreq <= 1'b0;
if(ff_rx_dval == 1'b1) begin
out_pkt[23:16] <= ff_rx_data;
if(ff_rx_eop == 1'b1) begin
out_pkt[133:132] <= 2'b10;
out_pkt[131:128] <= 4'b0010;
out_pkt_wrreq <= 1'b1;
if(rx_err == 6'b0) begin
out_valid_wrreq <= 1'b1;
out_valid <= 1'b1;
end
else begin
out_valid_wrreq <= 1'b1;
out_valid <= 1'b0;
end
current_state <= transmit_byte0_s;
end
else begin
//out_pkt[133:132] <= 2'b11;
current_state <= transmit_byte14_s;
end
end
else begin
current_state <= transmit_byte13_s;
end
end
transmit_byte14_s: begin
out_pkt_wrreq <= 1'b0;
if(ff_rx_dval == 1'b1) begin
out_pkt[15:8] <= ff_rx_data;
if(ff_rx_eop == 1'b1) begin
out_pkt[133:132] <= 2'b10;
out_pkt[131:128] <= 4'b0001;
out_pkt_wrreq <= 1'b1;
if(rx_err == 6'b0) begin
out_valid_wrreq <= 1'b1;
out_valid <= 1'b1;
end
else begin
out_valid_wrreq <= 1'b1;
out_valid <= 1'b0;
end
current_state <= transmit_byte0_s;
end
else begin
//out_pkt[133:132] <= 2'b11;
current_state <= transmit_byte15_s;
end
end
else begin
current_state <= transmit_byte14_s;
end
end
transmit_byte15_s: begin
if(ff_rx_dval == 1'b1) begin
out_pkt_wrreq <= 1'b1;
out_pkt[7:0] <= ff_rx_data;
if(ff_rx_eop == 1'b1) begin
out_pkt[133:132] <= 2'b10;
out_pkt[131:128] <= 4'b0000;
out_pkt_wrreq <= 1'b1;
if(rx_err == 6'b0) begin
out_valid_wrreq <= 1'b1;
out_valid <= 1'b1;
end
else begin
out_valid_wrreq <= 1'b1;
out_valid <= 1'b0;
end
current_state <= transmit_byte0_s;
end
else begin
//out_pkt[133:132] <= 2'b11;
current_state <= transmit_byte0_s;
end
end
else begin
current_state <= transmit_byte15_s;
end
end
discard_s:begin
out_pkt_wrreq <= 1'b0;
pkt_discard_add <= 1'b0;
if((ff_rx_dval == 1'b1)&&(ff_rx_eop == 1'b1))begin
current_state <= transmit_byte0_s;
end
else begin
current_state <= discard_s;
end
end
endcase
end
endmodule
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
// Date : Tue Oct 17 15:20:13 2017
// Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
// Command : write_verilog -force -mode synth_stub -rename_top led_controller_design_auto_pc_0 -prefix
// led_controller_design_auto_pc_0_ led_controller_design_auto_pc_0_stub.v
// Design : led_controller_design_auto_pc_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "axi_protocol_converter_v2_1_14_axi_protocol_converter,Vivado 2017.3" *)
module led_controller_design_auto_pc_0(aclk, aresetn, s_axi_awid, s_axi_awaddr,
s_axi_awlen, s_axi_awsize, s_axi_awburst, s_axi_awlock, s_axi_awcache, s_axi_awprot,
s_axi_awqos, s_axi_awvalid, s_axi_awready, s_axi_wid, s_axi_wdata, s_axi_wstrb, s_axi_wlast,
s_axi_wvalid, s_axi_wready, s_axi_bid, s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_arid,
s_axi_araddr, s_axi_arlen, s_axi_arsize, s_axi_arburst, s_axi_arlock, s_axi_arcache,
s_axi_arprot, s_axi_arqos, s_axi_arvalid, s_axi_arready, s_axi_rid, s_axi_rdata, s_axi_rresp,
s_axi_rlast, s_axi_rvalid, s_axi_rready, m_axi_awaddr, m_axi_awprot, m_axi_awvalid,
m_axi_awready, m_axi_wdata, m_axi_wstrb, m_axi_wvalid, m_axi_wready, m_axi_bresp,
m_axi_bvalid, m_axi_bready, m_axi_araddr, m_axi_arprot, m_axi_arvalid, m_axi_arready,
m_axi_rdata, m_axi_rresp, m_axi_rvalid, m_axi_rready)
/* synthesis syn_black_box black_box_pad_pin="aclk,aresetn,s_axi_awid[11:0],s_axi_awaddr[31:0],s_axi_awlen[3:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[1:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awqos[3:0],s_axi_awvalid,s_axi_awready,s_axi_wid[11:0],s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bid[11:0],s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_arid[11:0],s_axi_araddr[31:0],s_axi_arlen[3:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[1:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arqos[3:0],s_axi_arvalid,s_axi_arready,s_axi_rid[11:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_awaddr[31:0],m_axi_awprot[2:0],m_axi_awvalid,m_axi_awready,m_axi_wdata[31:0],m_axi_wstrb[3:0],m_axi_wvalid,m_axi_wready,m_axi_bresp[1:0],m_axi_bvalid,m_axi_bready,m_axi_araddr[31:0],m_axi_arprot[2:0],m_axi_arvalid,m_axi_arready,m_axi_rdata[31:0],m_axi_rresp[1:0],m_axi_rvalid,m_axi_rready" */;
input aclk;
input aresetn;
input [11:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [3:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [1:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awqos;
input s_axi_awvalid;
output s_axi_awready;
input [11:0]s_axi_wid;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [11:0]s_axi_bid;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [11:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [3:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [1:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arqos;
input s_axi_arvalid;
output s_axi_arready;
output [11:0]s_axi_rid;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
output [31:0]m_axi_awaddr;
output [2:0]m_axi_awprot;
output m_axi_awvalid;
input m_axi_awready;
output [31:0]m_axi_wdata;
output [3:0]m_axi_wstrb;
output m_axi_wvalid;
input m_axi_wready;
input [1:0]m_axi_bresp;
input m_axi_bvalid;
output m_axi_bready;
output [31:0]m_axi_araddr;
output [2:0]m_axi_arprot;
output m_axi_arvalid;
input m_axi_arready;
input [31:0]m_axi_rdata;
input [1:0]m_axi_rresp;
input m_axi_rvalid;
output m_axi_rready;
endmodule
|
`timescale 1 ns / 1 ps
module pwm_v1_0 #
(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Parameters of Axi Slave Bus Interface S00_AXI
parameter integer C_S00_AXI_DATA_WIDTH = 32,
parameter integer C_S00_AXI_ADDR_WIDTH = 4
)
(
// Users to add ports here
output wire pwm_out,
// User ports ends
// Do not modify the ports beyond this line
// Ports of Axi Slave Bus Interface S00_AXI
input wire s00_axi_aclk,
input wire s00_axi_aresetn,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_awaddr,
input wire [2 : 0] s00_axi_awprot,
input wire s00_axi_awvalid,
output wire s00_axi_awready,
input wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_wdata,
input wire [(C_S00_AXI_DATA_WIDTH/8)-1 : 0] s00_axi_wstrb,
input wire s00_axi_wvalid,
output wire s00_axi_wready,
output wire [1 : 0] s00_axi_bresp,
output wire s00_axi_bvalid,
input wire s00_axi_bready,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_araddr,
input wire [2 : 0] s00_axi_arprot,
input wire s00_axi_arvalid,
output wire s00_axi_arready,
output wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_rdata,
output wire [1 : 0] s00_axi_rresp,
output wire s00_axi_rvalid,
input wire s00_axi_rready
);
// Instantiation of Axi Bus Interface S00_AXI
pwm_v1_0_S00_AXI # (
.C_S_AXI_DATA_WIDTH(C_S00_AXI_DATA_WIDTH),
.C_S_AXI_ADDR_WIDTH(C_S00_AXI_ADDR_WIDTH)
) pwm_v1_0_S00_AXI_inst (
.pwm_out(pwm_out),
.S_AXI_ACLK(s00_axi_aclk),
.S_AXI_ARESETN(s00_axi_aresetn),
.S_AXI_AWADDR(s00_axi_awaddr),
.S_AXI_AWPROT(s00_axi_awprot),
.S_AXI_AWVALID(s00_axi_awvalid),
.S_AXI_AWREADY(s00_axi_awready),
.S_AXI_WDATA(s00_axi_wdata),
.S_AXI_WSTRB(s00_axi_wstrb),
.S_AXI_WVALID(s00_axi_wvalid),
.S_AXI_WREADY(s00_axi_wready),
.S_AXI_BRESP(s00_axi_bresp),
.S_AXI_BVALID(s00_axi_bvalid),
.S_AXI_BREADY(s00_axi_bready),
.S_AXI_ARADDR(s00_axi_araddr),
.S_AXI_ARPROT(s00_axi_arprot),
.S_AXI_ARVALID(s00_axi_arvalid),
.S_AXI_ARREADY(s00_axi_arready),
.S_AXI_RDATA(s00_axi_rdata),
.S_AXI_RRESP(s00_axi_rresp),
.S_AXI_RVALID(s00_axi_rvalid),
.S_AXI_RREADY(s00_axi_rready)
);
// Add user logic here
// User logic ends
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2017 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [15:0] in = crc[15:0];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire out; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.out (out),
// Inputs
.in (in[15:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {63'h0, out};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= '0;
end
else if (cyc<10) begin
sum <= '0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h162c58b1635b8d6e
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (/*AUTOARG*/
// Outputs
out,
// Inputs
in
);
input [15:0] in;
output reg out;
// TODO this should flatten into a reduction OR
always_comb begin
out = 0;
for (int i=0; i<16; i=i+1) begin
if (in[i]) begin
out = 1;
end
end
end
endmodule
|
`timescale 1ns / 1ps
module ftl_top(
reset,clk,clk_83X2M,clk_83M,clk_83M_reverse,phy_init_done,
pcie_data_rec_fifo_out,pcie_data_rec_fifo_out_en,pcie_command_rec_fifo_out,pcie_command_rec_fifo_empty_or_not,
pcie_command_rec_fifo_out_en,pcie_data_send_fifo_in,pcie_data_send_fifo_in_en,pcie_data_send_fifo_out_prog_full,
pcie_command_send_fifo_full_or_not,pcie_command_send_fifo_in,pcie_command_send_fifo_in_en,
//dram
dram_ready,rd_data_valid,data_from_dram,
dram_en,dram_read_or_write,addr_to_dram,data_to_dram,dram_data_mask,
data_to_dram_en,data_to_dram_end,data_to_dram_ready,initial_dram_done,
//flash_controller
nand0Cle,nand0Ale,nand0Clk_We_n,nand0Wr_Re_n,nand0Wp_n,nand0Ce_n,nand0Rb_n,nand0DQX,nand0DQS,
nand1Cle,nand1Ale,nand1Clk_We_n,nand1Wr_Re_n,nand1Wp_n,nand1Ce_n,nand1Rb_n,nand1DQX,nand1DQS,
nand2Cle,nand2Ale,nand2Clk_We_n,nand2Wr_Re_n,nand2Wp_n,nand2Ce_n,nand2Rb_n,nand2DQX,nand2DQS,
nand3Cle,nand3Ale,nand3Clk_We_n,nand3Wr_Re_n,nand3Wp_n,nand3Ce_n,nand3Rb_n,nand3DQX,nand3DQS,
nand4Cle,nand4Ale,nand4Clk_We_n,nand4Wr_Re_n,nand4Wp_n,nand4Ce_n,nand4Rb_n,nand4DQX,nand4DQS,
nand5Cle,nand5Ale,nand5Clk_We_n,nand5Wr_Re_n,nand5Wp_n,nand5Ce_n,nand5Rb_n,nand5DQX,nand5DQS,
nand6Cle,nand6Ale,nand6Clk_We_n,nand6Wr_Re_n,nand6Wp_n,nand6Ce_n,nand6Rb_n,nand6DQX,nand6DQS,
nand7Cle,nand7Ale,nand7Clk_We_n,nand7Wr_Re_n,nand7Wp_n,nand7Ce_n,nand7Rb_n,nand7DQX,nand7DQS
);
`include"ftl_define.v"
input reset;
input clk;
input clk_83X2M;
input clk_83M;
input clk_83M_reverse;
input phy_init_done;
/***************Instantiate the IDELAYCTRL primitive ***********/
// IDELAYCTRL: IDELAY Tap Delay Value Control
// Virtex-6
// Xilinx HDL Libraries Guide, version 12.4
(* IODELAY_GROUP = "iodelay_delayDQS" *) // Specifies group name for associated IODELAYs and IDELAYCTRL
IDELAYCTRL IDELAYCTRL_inst (
.RDY(), // 1-bit Indicates the validity of the reference clock input, REFCLK. When REFCLK
// disappears (i.e., REFCLK is held High or Low for one clock period or more), the RDY
// signal is deasserted.
.REFCLK(clk), // 1-bit Provides a voltage bias, independent of process, voltage, and temperature
// variations, to the tap-delay lines in the IOBs. The frequency of REFCLK must be 200
// MHz to guarantee the tap-delay value specified in the applicable data sheet.
.RST(reset) // 1-bit Resets the IDELAYCTRL circuitry. The RST signal is an active-high asynchronous
// reset. To reset the IDELAYCTRL, assert it High for at least 50 ns.
);
// End of IDELAYCTRL_inst instantiation
//pcie_data_rec_fifo
input [DRAM_IO_WIDTH-1:0]pcie_data_rec_fifo_out; // output [255 : 0] dout
output pcie_data_rec_fifo_out_en; // input rd_en
wire pcie_data_rec_fifo_out_en; // input rd_en
//pcie_command_rec_fifo
input [COMMAND_WIDTH-1:0]pcie_command_rec_fifo_out; // output [127 : 0] dout
input pcie_command_rec_fifo_empty_or_not; // output empty
output pcie_command_rec_fifo_out_en; // input rd_en
wire pcie_command_rec_fifo_out_en; // input rd_en
//pcie_data_send_fifo
input pcie_data_send_fifo_out_prog_full;
output [DRAM_IO_WIDTH-1:0]pcie_data_send_fifo_in;
output pcie_data_send_fifo_in_en;
wire [DRAM_IO_WIDTH-1:0]pcie_data_send_fifo_in;
wire pcie_data_send_fifo_in_en;
//pcie_command_send_fifo
input pcie_command_send_fifo_full_or_not;
output [COMMAND_WIDTH-1:0]pcie_command_send_fifo_in;
output pcie_command_send_fifo_in_en;
wire [COMMAND_WIDTH-1:0]pcie_command_send_fifo_in;
wire pcie_command_send_fifo_in_en;
//dram
input dram_ready;
input rd_data_valid;
input [DRAM_IO_WIDTH-1:0]data_from_dram;
input data_to_dram_ready;
output data_to_dram_en;
output data_to_dram_end;
output dram_en;
output dram_read_or_write;
output [DRAM_ADDR_WIDTH-1:0]addr_to_dram;
output [DRAM_IO_WIDTH-1:0]data_to_dram;
output [DRAM_MASK_WIDTH-1:0]dram_data_mask;
output initial_dram_done;
reg dram_en;
reg dram_read_or_write;
reg [DRAM_ADDR_WIDTH-1:0]addr_to_dram;
reg [DRAM_IO_WIDTH-1:0]data_to_dram;
reg [DRAM_MASK_WIDTH-1:0]dram_data_mask;
reg data_to_dram_en;
reg data_to_dram_end;
wire cache_dram_en;
wire cache_dram_read_or_write;
wire [DRAM_ADDR_WIDTH-1:0]cache_addr_to_dram;
wire [DRAM_IO_WIDTH-1:0]cache_data_to_dram;
wire [DRAM_MASK_WIDTH-1:0]cache_dram_data_mask;
wire cache_data_to_dram_en;
wire cache_data_to_dram_end;
wire io_dram_en;
wire io_dram_read_or_write;
wire [DRAM_ADDR_WIDTH-1:0]io_addr_to_dram;
wire [DRAM_IO_WIDTH-1:0]io_data_to_dram;
wire [DRAM_MASK_WIDTH-1:0]io_dram_data_mask;
wire io_data_to_dram_en;
wire io_data_to_dram_end;
wire gc_dram_en;
wire gc_dram_read_or_write;
wire [DRAM_ADDR_WIDTH-1:0]gc_addr_to_dram;
wire [DRAM_IO_WIDTH-1:0]gc_data_to_dram;
wire [DRAM_MASK_WIDTH-1:0]gc_dram_data_mask;
wire gc_data_to_dram_en;
wire gc_data_to_dram_end;
wire check_dram_en;
wire check_dram_read_or_write;
wire [DRAM_ADDR_WIDTH-1:0]check_addr_to_dram;
wire [DRAM_IO_WIDTH-1:0]check_data_to_dram;
wire [DRAM_MASK_WIDTH-1:0]check_dram_data_mask;
wire check_data_to_dram_en;
wire check_data_to_dram_end;
wire test_dram_en;
wire test_dram_read_or_write;
wire [DRAM_ADDR_WIDTH-1:0]test_addr_to_dram;
wire [DRAM_IO_WIDTH-1:0]test_data_to_dram;
wire [DRAM_MASK_WIDTH-1:0]test_dram_data_mask;
wire test_dram_data_to_dram_en;
wire test_dram_data_to_dram_end;
wire backup_dram_en;
wire backup_dram_read_or_write;
wire [DRAM_ADDR_WIDTH-1:0]backup_addr_to_dram;
wire [DRAM_IO_WIDTH-1:0]backup_data_to_dram;
wire [DRAM_MASK_WIDTH-1:0]backup_dram_data_mask;
wire backup_data_to_dram_en;
wire backup_data_to_dram_end;
//dram arbitrator
//dram arbitrator input
wire cache_dram_request;
wire cache_release_dram;
wire io_dram_request;
wire io_release_dram;
wire gc_dram_request;
wire gc_release_dram;
wire check_dram_request;
wire check_release_dram;
wire test_dram_request;
wire test_release_dram;
wire backup_dram_request;
wire backup_release_dram;
//dram arbitrator output
wire cache_dram_permit;
wire io_dram_permit;
wire gc_dram_permit;
wire check_dram_permit;
wire test_dram_permit;
wire backup_dram_permit;
//ssd_command_fifo
wire [COMMAND_WIDTH-1:0]ssd_command_fifo_in; // input [127 : 0] din
wire ssd_command_fifo_in_en; // input wr_en
wire ssd_command_fifo_out_en; // input rd_en
wire [COMMAND_WIDTH-1:0]ssd_command_fifo_out; // output [127: 0] dout
wire ssd_command_fifo_full; // output full
wire ssd_command_fifo_empty_or_not;// output empty
//gc_command_fifo
wire [GC_COMMAND_WIDTH-1:0]gc_command_fifo_in; // input [28 : 0] din
wire gc_command_fifo_in_en;// input wr_en
wire gc_command_fifo_out_en; // input rd_en
wire [GC_COMMAND_WIDTH-1:0]gc_command_fifo_out; // output [28 : 0] dout
wire gc_command_fifo_empty_or_not; // output empty
wire gc_command_fifo_prog_full; // output prog_full
//controller_command_fifo
wire [COMMAND_WIDTH-1:0]controller_command_fifo_in; // input [127 : 0] din
wire [7:0]controller_command_fifo_in_en; // input wr_en
//wire controller_command_fifo_out_en[0:7]; // input rd_en
//wire [COMMAND_WIDTH-1:0]controller_command_fifo_out[0:7]; // output [127 : 0] dout
//wire controller_command_fifo_full[0:7];
//wire controller_command_fifo_empty_or_not[0:7]; // output empty
//write_data_fifo
wire [DRAM_IO_WIDTH-1:0]write_data_fifo_in; // input [255 : 0] din
wire [7:0]write_data_fifo_in_en; // input wr_en
//wire write_fifo_out_en[0:7]; // input rd_en
//wire [FLASH_IO_WIDTH*4-1:0]data_from_ftl[0:7]; // output [31 : 0] dout
//wire write_data_fifo_prog_full[0:7];
//wire write_data_fifo_full[0:7];
//read_data_fifo
//wire [FLASH_IO_WIDTH*4-1:0]data_to_ftl[0:7]; // input [31 : 0] din
//wire read_fifo_in_en[0:7]; // input wr_en
//wire read_data_fifo_prog_full[0:7]; // output prog_full
//wire read_data_fifo_full [0:7];
wire read_data_fifo_out_en[0:7]; // input rd_en
wire [DRAM_IO_WIDTH-1:0]read_data_fifo_out[0:7]; // output [255 : 0] dout
//gc_fifo
//wire [FLASH_IO_WIDTH*4-1:0]data_to_gc_fifo[0:7]; // input [31 : 0] din
//wire gc_fifo_in_en[0:7]; // input wr_en
//wire gc_fifo_out_en[0:7]; // input rd_en
//wire [FLASH_IO_WIDTH*4-1:0]data_from_gc_fifo[0:7]; // output [31 : 0] dout
//wire GC_fifo_full[0:7];
//finish_command_fifo
wire [COMMAND_WIDTH-1:0]finish_command_fifo8_in; // input [127 : 0] din
wire finish_command_fifo8_in_en;
//wire [COMMAND_WIDTH-1:0]finish_command_fifo_in[0:7]; // input [127 : 0] din
//wire finish_command_fifo_in_en[0:7]; // input wr_en
wire finish_command_fifo_out_en[0:8]; // input rd_en
wire [COMMAND_WIDTH-1:0]finish_command_fifo_out[0:8]; // output [127 : 0] dout
wire finish_command_fifo_full[0:8];
wire finish_command_fifo_empty_or_not[0:8]; // output empty
//flash_controller
//input
//wire read_page_en[0:7];
//wire write_page_en[0:7];
//wire erase_block_en[0:7];
//wire read_ready[0:7];
//wire [FLASH_IO_WIDTH*4-1:0]data_from_host[0:7];
//wire [21:0]addr[0:7];
//output
//wire [FLASH_IO_WIDTH*4-1:0]data_from_flash_o[0:7];
//wire controller_rb_l[0:7];
//wire data_from_flash_en[0:7];
//wire data_to_flash_en[0:7];
wire dram_backup_en;
wire [5:0] state_check;
//wire [4:0] state_gc;
wire [4:0] state_io;
//wire [3:0] initial_dram_state;
wire [7:0] idle_flag;
wire all_idle_flag;
assign all_idle_flag = idle_flag[0] & idle_flag[1] & idle_flag[2] & idle_flag[3] & idle_flag[4] & idle_flag[5] & idle_flag[6] & idle_flag[7];
wire [7:0] Cmd_Available;
wire all_Cmd_Available_flag;
assign all_Cmd_Available_flag = Cmd_Available[0] & Cmd_Available[1] & Cmd_Available[2] & Cmd_Available[3] & Cmd_Available[4] & Cmd_Available[5] & Cmd_Available[6] & Cmd_Available[7];
wire [COMMAND_WIDTH-1:0]checkcache_ssd_command_fifo_in; // input [127 : 0] din
wire checkcache_ssd_command_fifo_in_en; // input wr_en
wire [COMMAND_WIDTH-1:0]backup_ssd_command_fifo_in; // input [127 : 0] din
wire backup_ssd_command_fifo_in_en; // input wr_en
wire [COMMAND_WIDTH-1:0]io_controller_command_fifo_in; // input [127 : 0] din
wire [7:0]io_controller_command_fifo_in_en; // input wr_en
wire [COMMAND_WIDTH-1:0]backup_controller_command_fifo_in; // input [127 : 0] din
wire [7:0]backup_controller_command_fifo_in_en; // input wr_en
wire [DRAM_IO_WIDTH-1:0]io_write_data_fifo_in; // input [255 : 0] din
wire [7:0]io_write_data_fifo_in_en; // input wr_en
wire [DRAM_IO_WIDTH-1:0]backup_write_data_fifo_in; // input [255 : 0] din
wire [7:0]backup_write_data_fifo_in_en; // input wr_en
wire backup_or_checkcache;
wire backup_or_io;
wire initial_dram_done;
wire init_dram_done;
wire register_ready;
wire [7:0] initialdram_controller_command_fifo_in_en;
wire [COMMAND_WIDTH-1:0] initialdram_controller_command_fifo_in;
//wire [16:0]flash_left_capacity;//512GB flash217η
wire [127:0] free_block_fifo_tails;
wire [127:0] free_block_fifo_heads;
//GC
wire [18:0]left_capacity;//512GB flashæç7次æ¹ä¸ªå
//wire [16:0]flash_left_capacity;//512GB flash217η
wire [127:0] free_block_fifo_tails_initial;
wire [127:0] free_block_fifo_heads_initial;
//GC
wire [18:0]left_capacity_initial;//512GB flashæç7次æ¹ä¸ªå
//wire [16:0]flash_left_capacity;//512GB flash217η
wire [127:0] free_block_fifo_tails_io;
wire [127:0] free_block_fifo_heads_io;
//GC
wire [18:0]left_capacity_io;//512GB flashæç7次æ¹ä¸ªå
assign ssd_command_fifo_in=(backup_or_checkcache)?backup_ssd_command_fifo_in:checkcache_ssd_command_fifo_in;
assign ssd_command_fifo_in_en=(backup_or_checkcache)?backup_ssd_command_fifo_in_en:checkcache_ssd_command_fifo_in_en;
assign controller_command_fifo_in=(initial_dram_done)?((backup_or_io)?backup_controller_command_fifo_in:io_controller_command_fifo_in):initialdram_controller_command_fifo_in;
assign controller_command_fifo_in_en=(initial_dram_done)?((backup_or_io)?backup_controller_command_fifo_in_en:io_controller_command_fifo_in_en):initialdram_controller_command_fifo_in_en;
assign write_data_fifo_in=(backup_or_io)?backup_write_data_fifo_in:io_write_data_fifo_in;
assign write_data_fifo_in_en=(backup_or_io)?backup_write_data_fifo_in_en:io_write_data_fifo_in_en;
assign left_capacity_io= register_ready? left_capacity_initial :19'bz;
assign free_block_fifo_heads_io= register_ready? free_block_fifo_heads_initial : 128'bz;
assign free_block_fifo_tails_io= register_ready? free_block_fifo_tails_initial : 128'bz;
assign left_capacity= left_capacity_io ;
assign free_block_fifo_heads= free_block_fifo_heads_io;
assign free_block_fifo_tails= free_block_fifo_tails_io;
output nand0Cle;
output nand0Ale;
output nand0Clk_We_n;
output nand0Wr_Re_n;
output nand0Wp_n;
output [7:0] nand0Ce_n;
input [7:0] nand0Rb_n;
inout [FLASH_IO_WIDTH-1:0] nand0DQX;
inout nand0DQS;
output nand1Cle;
output nand1Ale;
output nand1Clk_We_n;
output nand1Wr_Re_n;
output nand1Wp_n;
output [7:0] nand1Ce_n;
input [7:0] nand1Rb_n;
inout [FLASH_IO_WIDTH-1:0] nand1DQX;
inout nand1DQS;
output nand2Cle;
output nand2Ale;
output nand2Clk_We_n;
output nand2Wr_Re_n;
output nand2Wp_n;
output [7:0] nand2Ce_n;
input [7:0] nand2Rb_n;
inout [FLASH_IO_WIDTH-1:0] nand2DQX;
inout nand2DQS;
output nand3Cle;
output nand3Ale;
output nand3Clk_We_n;
output nand3Wr_Re_n;
output nand3Wp_n;
output [7:0] nand3Ce_n;
input [7:0] nand3Rb_n;
inout [FLASH_IO_WIDTH-1:0] nand3DQX;
inout nand3DQS;
output nand4Cle;
output nand4Ale;
output nand4Clk_We_n;
output nand4Wr_Re_n;
output nand4Wp_n;
output [7:0] nand4Ce_n;
input [7:0] nand4Rb_n;
inout [FLASH_IO_WIDTH-1:0] nand4DQX;
inout nand4DQS;
output nand5Cle;
output nand5Ale;
output nand5Clk_We_n;
output nand5Wr_Re_n;
output nand5Wp_n;
output [7:0] nand5Ce_n;
input [7:0] nand5Rb_n;
inout [FLASH_IO_WIDTH-1:0] nand5DQX;
inout nand5DQS;
output nand6Cle;
output nand6Ale;
output nand6Clk_We_n;
output nand6Wr_Re_n;
output nand6Wp_n;
output [7:0] nand6Ce_n;
input [7:0] nand6Rb_n;
inout [FLASH_IO_WIDTH-1:0] nand6DQX;
inout nand6DQS;
output nand7Cle;
output nand7Ale;
output nand7Clk_We_n;
output nand7Wr_Re_n;
output nand7Wp_n;
output [7:0] nand7Ce_n;
input [7:0] nand7Rb_n;
inout [FLASH_IO_WIDTH-1:0] nand7DQX;
inout nand7DQS;
always @(*)
begin
case({cache_dram_permit,io_dram_permit,gc_dram_permit,check_dram_permit,test_dram_permit,backup_dram_permit})
6'b100000:
begin
dram_en = cache_dram_en;
dram_read_or_write = cache_dram_read_or_write;
addr_to_dram = cache_addr_to_dram;
data_to_dram = cache_data_to_dram;
dram_data_mask = cache_dram_data_mask;
data_to_dram_en = cache_data_to_dram_en;
data_to_dram_end = cache_data_to_dram_end;
end
6'b010000:
begin
dram_en = io_dram_en;
dram_read_or_write = io_dram_read_or_write;
addr_to_dram = io_addr_to_dram;
data_to_dram = io_data_to_dram;
dram_data_mask = io_dram_data_mask;
data_to_dram_en = io_data_to_dram_en;
data_to_dram_end = io_data_to_dram_end;
end
6'b001000:
begin
dram_en = gc_dram_en;
dram_read_or_write = gc_dram_read_or_write;
addr_to_dram = gc_addr_to_dram;
data_to_dram = gc_data_to_dram;
dram_data_mask = gc_dram_data_mask;
data_to_dram_en = gc_data_to_dram_en;
data_to_dram_end = gc_data_to_dram_end;
end
6'b000100:
begin
dram_en = check_dram_en;
dram_read_or_write = check_dram_read_or_write;
addr_to_dram = check_addr_to_dram;
data_to_dram = check_data_to_dram;
dram_data_mask = check_dram_data_mask;
data_to_dram_en = check_data_to_dram_en;
data_to_dram_end = check_data_to_dram_end;
end
6'b000010:
begin
dram_en = test_dram_en;
dram_read_or_write = test_dram_read_or_write;
addr_to_dram = test_addr_to_dram;
data_to_dram = test_data_to_dram;
dram_data_mask = test_dram_data_mask;
data_to_dram_en = test_dram_data_to_dram_en;
data_to_dram_end = test_dram_data_to_dram_end;
end
6'b000001:
begin
dram_en = backup_dram_en;
dram_read_or_write = backup_dram_read_or_write;
addr_to_dram = backup_addr_to_dram;
data_to_dram = backup_data_to_dram;
dram_data_mask = backup_dram_data_mask;
data_to_dram_en = backup_data_to_dram_en;
data_to_dram_end = backup_data_to_dram_end;
end
default:
begin
dram_en = cache_dram_en;
dram_read_or_write = cache_dram_read_or_write;
addr_to_dram = cache_addr_to_dram;
data_to_dram = cache_data_to_dram;
dram_data_mask = cache_dram_data_mask;
data_to_dram_en = cache_data_to_dram_en;
data_to_dram_end = cache_data_to_dram_end;
end
endcase
end
arbitrator arbitrator_instance(
.reset(!reset),
.clk(clk),
.request0(cache_dram_request),
.release0(cache_release_dram),
.request1(io_dram_request),
.release1(io_release_dram),
.request2(1'b0),
.release2(gc_release_dram),
.request3(check_dram_request),
.release3(check_release_dram),
.request4(test_dram_request),
.release4(test_release_dram),
.request5(backup_dram_request),
.release5(backup_release_dram),
.permit0(cache_dram_permit),
.permit1(io_dram_permit),
.permit2(gc_dram_permit),
.permit3(check_dram_permit),
.permit4(test_dram_permit),
.permit5(backup_dram_permit)
//.state(state_arbitrator)
);
dram_test dram_test_instance(
.reset(!reset),
.clk(clk),
.phy_init_done(phy_init_done),
.dram_ready_i(dram_ready),
.rd_data_valid_i(rd_data_valid),
.data_from_dram_i(data_from_dram),
.dram_permit_i(test_dram_permit),
.dram_request_o(test_dram_request),
.release_dram_o(test_release_dram),
.dram_en_o(test_dram_en),
.dram_rd_wr_o(test_dram_read_or_write),
.data_to_dram_en(test_dram_data_to_dram_en),
.data_to_dram_end(test_dram_data_to_dram_end),
.data_to_dram_ready(data_to_dram_ready),
.addr_to_dram_o(test_addr_to_dram),
.data_to_dram_o(test_data_to_dram),
.dram_data_mask_o(test_dram_data_mask),
//.state(state_test),
.init_dram_done(init_dram_done)
);
initial_dram initial_dram_inst (
.reset(!reset),
.clk(clk),
.trigger_initial_dram(init_dram_done),
.all_Cmd_Available_flag(all_Cmd_Available_flag),
.controller_command_fifo_in(initialdram_controller_command_fifo_in),
.controller_command_fifo_in_en(initialdram_controller_command_fifo_in_en)
);
check_cache check_cache_instance(
//input
.reset(!reset),
.clk(clk),
.initial_dram_done(initial_dram_done),
//pcie_command_fifo
.pcie_cmd_rec_fifo_empty_i(pcie_command_rec_fifo_empty_or_not),
.pcie_cmd_rec_fifo_i(pcie_command_rec_fifo_out),
.pcie_cmd_rec_fifo_en_o(pcie_command_rec_fifo_out_en),
//pcie_data_fifo
.pcie_data_rec_fifo_en_o(pcie_data_rec_fifo_out_en),
.pcie_data_rec_fifo_i(pcie_data_rec_fifo_out),
//dram
.data_from_dram_i(data_from_dram),
.dram_ready_i(dram_ready),
.rd_data_valid_i(rd_data_valid),
.addr_to_dram_o(cache_addr_to_dram),
.data_to_dram_o(cache_data_to_dram),
.dram_data_mask_o(cache_dram_data_mask),
.dram_en_o(cache_dram_en),
.dram_rd_wr_o(cache_dram_read_or_write),
.data_to_dram_en(cache_data_to_dram_en),
.data_to_dram_end(cache_data_to_dram_end),
.data_to_dram_ready(data_to_dram_ready),
//arbitrator
.dram_permit_i(cache_dram_permit),
.dram_request_o(cache_dram_request),
.release_dram_o(cache_release_dram),
//ssd_command_fifo
.ssd_cmd_fifo_full_i(ssd_command_fifo_full),
.ssd_cmd_fifo_en_o(checkcache_ssd_command_fifo_in_en),
.ssd_cmd_fifo_in_o(checkcache_ssd_command_fifo_in),
//finish_command_fifo8
.finish_cmd_fifo8_full_i(finish_command_fifo_full[8]),
.finish_cmd_fifo8_in_o(finish_command_fifo8_in),
.finish_cmd_fifo8_en_o(finish_command_fifo8_in_en),
//debug
//.state(state_cache),
//.step(cache_step),
.dram_backup_en(dram_backup_en)
);
ssd_command_fifo ssd_command_fifo_instance (//depth 1024
.clk(clk), // input clk
.rst(reset), // input rst
.din(ssd_command_fifo_in), // input [127 : 0] din
.wr_en(ssd_command_fifo_in_en), // input wr_en
.rd_en(ssd_command_fifo_out_en), // input rd_en
.dout(ssd_command_fifo_out), // output [127: 0] dout
.full(ssd_command_fifo_full), // output full
.empty(ssd_command_fifo_empty_or_not), // output empty
.data_count() // output [6 : 0] data_count
);
controller_command_fifo finish_command_fifo8 (//write_depth 128
.clk(clk), // input clk
.rst(reset), // input rst
.din(finish_command_fifo8_in), // input [127 : 0] din
.wr_en(finish_command_fifo8_in_en), // input wr_en
.rd_en(finish_command_fifo_out_en[8]), // input rd_en
.dout(finish_command_fifo_out[8]), // output [127 : 0] dout
.full(finish_command_fifo_full[8]), // output full
.empty(finish_command_fifo_empty_or_not[8]), // output empty
.data_count() // output [4 : 0] data_count
);
/* GC gc_instance(
.clk(clk),
.reset(!reset),
.left_capacity(left_capacity), //need input
.data_from_dram(data_from_dram),
.dram_ready(dram_ready),
.rd_data_valid(rd_data_valid),
.dram_permit(gc_dram_permit),
.gc_command_fifo_prog_full(gc_command_fifo_prog_full),
.dram_en(gc_dram_en),
.dram_read_or_write(gc_dram_read_or_write),
.addr_to_dram(gc_addr_to_dram),
.data_to_dram(gc_data_to_dram),
.dram_data_mask(gc_dram_data_mask),
.data_to_dram_en(gc_data_to_dram_en),
.data_to_dram_end(gc_data_to_dram_end),
.data_to_dram_ready(data_to_dram_ready),
.release_dram(gc_release_dram),
.dram_request(gc_dram_request),
.gc_command_fifo_in(gc_command_fifo_in),
.gc_command_fifo_in_en(gc_command_fifo_in_en)
//.state(state_gc)
);*/
/* gc_command_fifo gc_command_fifo_instance (//fifo depth 1024
.clk(clk), // input clk
.rst(reset), // input rst
.din(gc_command_fifo_in), // input [28 : 0] din
.wr_en(gc_command_fifo_in_en), // input wr_en
.rd_en(gc_command_fifo_out_en), // input rd_en
.dout(gc_command_fifo_out), // output [28 : 0] dout
.full(), // output full
.empty(gc_command_fifo_empty_or_not), // output empty
.data_count(), // output [10 : 0] data_count
.prog_full(gc_command_fifo_prog_full) // output prog_full
);*/
io_schedule io_schedule_instance(
.reset(!reset),
.clk(clk),
.ssd_command_fifo_empty_or_not(ssd_command_fifo_empty_or_not),
.ssd_command_fifo_out(ssd_command_fifo_out),
.dram_permit(io_dram_permit),
.data_from_dram(data_from_dram),
.dram_ready(dram_ready),
.rd_data_valid(rd_data_valid),
.gc_command_fifo_out(gc_command_fifo_out),
.gc_command_fifo_empty_or_not(1),
//.write_data_fifo0_prog_full(!Cmd_Available[0]),
//.command_fifo0_full(!Cmd_Available[0]),
//.write_data_fifo1_prog_full(!Cmd_Available[1]),
//.command_fifo1_full(!Cmd_Available[1]),
//.write_data_fifo2_prog_full(!Cmd_Available[2]),
//.command_fifo2_full(!Cmd_Available[2]),
//.write_data_fifo3_prog_full(!Cmd_Available[3]),
//.command_fifo3_full(!Cmd_Available[3]),
//.write_data_fifo4_prog_full(!Cmd_Available[4]),
//.command_fifo4_full(!Cmd_Available[4]),
//.write_data_fifo5_prog_full(!Cmd_Available[5]),
//.command_fifo5_full(!Cmd_Available[5]),
//.write_data_fifo6_prog_full(!Cmd_Available[6]),
//.command_fifo6_full(!Cmd_Available[6]),
//.write_data_fifo7_prog_full(!Cmd_Available[7]),
//.command_fifo7_full(!Cmd_Available[7]),
.command_available(Cmd_Available),
.ssd_command_fifo_out_en(ssd_command_fifo_out_en),
.controller_command_fifo_in(io_controller_command_fifo_in),
.controller_command_fifo_in_en(io_controller_command_fifo_in_en),
.write_data_fifo_in(io_write_data_fifo_in),
.write_data_fifo_in_en(io_write_data_fifo_in_en),
.dram_request(io_dram_request),
.release_dram(io_release_dram),
.addr_to_dram(io_addr_to_dram),
.data_to_dram(io_data_to_dram),
.dram_data_mask(io_dram_data_mask),
.dram_en(io_dram_en),
.dram_read_or_write(io_dram_read_or_write),
.data_to_dram_en(io_data_to_dram_en),
.data_to_dram_end(io_data_to_dram_end),
.data_to_dram_ready(data_to_dram_ready),
.gc_command_fifo_out_en(gc_command_fifo_out_en),
.flash_left_capacity(left_capacity_io),
.free_block_fifo_heads(free_block_fifo_heads_io),
.free_block_fifo_tails(free_block_fifo_tails_io),
.register_ready(register_ready),
.state(state_io)
//.state_addr(state_addr)
);
//channel 0
Dynamic_Controller flash_controller_instance0 (
.clk_200M(clk), //??????????czg
.rst_n(!reset), //????????????czg
.clk_83X2M(clk_83X2M), //????????czg
.clk_83M(clk_83M),
.clk_83M_reverse(clk_83M_reverse),
//Ports with Host
.Cmd_In_En(controller_command_fifo_in_en[0]),
.Cmd_In(controller_command_fifo_in),
.Finished_Cmd_Out_En(finish_command_fifo_out_en[0]),
.Data_In_En(write_data_fifo_in_en[0]),
.Data_In(write_data_fifo_in),
.Cmd_Available(Cmd_Available[0]), //czg??????
.Finished_Cmd_FIFO_Empty(finish_command_fifo_empty_or_not[0]),
.Finished_Cmd_Out(finish_command_fifo_out[0]),
.ControllerIdle(idle_flag[0]),
.Data_2_host_en(read_data_fifo_out_en[0]),
.Data_2_host(read_data_fifo_out[0]),
//.Data_Out_En(read_data_fifo_out_en[0]),
//.Data_Out(read_data_fifo_out[0]),
// .Post_Data_Empty(), //use for check
//.Post_Data_Full(), //use for check
// .Post_Data_Valid(), //use for check
//Ports with Chips
.Cle(nand0Cle),
.Ale(nand0Ale),
.Clk_We_n(nand0Clk_We_n),
.Wr_Re_n(nand0Wr_Re_n),
.Wp_n(nand0Wp_n),
.Ce_n(nand0Ce_n),
.Rb_n(nand0Rb_n),
.DQX(nand0DQX),
.DQS(nand0DQS)
);
//channel 1
Dynamic_Controller flash_controller_instance1 (
.clk_200M(clk), //??????????czg
.rst_n(!reset), //????????????czg
.clk_83X2M(clk_83X2M), //????????czg
.clk_83M(clk_83M),
.clk_83M_reverse(clk_83M_reverse),
.Cmd_In_En(controller_command_fifo_in_en[1]),
.Cmd_In(controller_command_fifo_in),
.Finished_Cmd_Out_En(finish_command_fifo_out_en[1]),
.Data_In_En(write_data_fifo_in_en[1]),
.Data_In(write_data_fifo_in),
.Cmd_Available(Cmd_Available[1]), //czg??????
.Finished_Cmd_FIFO_Empty(finish_command_fifo_empty_or_not[1]),
.Finished_Cmd_Out(finish_command_fifo_out[1]),
.ControllerIdle(idle_flag[1]),
.Data_2_host_en(read_data_fifo_out_en[1]),
.Data_2_host(read_data_fifo_out[1]),
//.Post_Data_Empty(), //use for check
//.Post_Data_Full(), //use for check
//.Post_Data_Valid(), //use for check
.Cle(nand1Cle),
.Ale(nand1Ale),
.Clk_We_n(nand1Clk_We_n),
.Wr_Re_n(nand1Wr_Re_n),
.Wp_n(nand1Wp_n),
.Ce_n(nand1Ce_n),
.Rb_n(nand1Rb_n),
.DQX(nand1DQX),
.DQS(nand1DQS)
);
//channel 2
Dynamic_Controller flash_controller_instance2 (
.clk_200M(clk), //??????????czg
.rst_n(!reset), //????????????czg
.clk_83X2M(clk_83X2M), //????????czg
.clk_83M(clk_83M),
.clk_83M_reverse(clk_83M_reverse),
.Cmd_In_En(controller_command_fifo_in_en[2]),
.Cmd_In(controller_command_fifo_in),
.Finished_Cmd_Out_En(finish_command_fifo_out_en[2]),
.Data_In_En(write_data_fifo_in_en[2]),
.Data_In(write_data_fifo_in),
.Cmd_Available(Cmd_Available[2]), //czg??????
.Finished_Cmd_FIFO_Empty(finish_command_fifo_empty_or_not[2]),
.Finished_Cmd_Out(finish_command_fifo_out[2]),
.ControllerIdle(idle_flag[2]),
.Data_2_host_en(read_data_fifo_out_en[2]),
.Data_2_host(read_data_fifo_out[2]),
//.Post_Data_Empty(), //use for check
//.Post_Data_Full(), //use for check
//.Post_Data_Valid(), //use for check
.Cle(nand2Cle),
.Ale(nand2Ale),
.Clk_We_n(nand2Clk_We_n),
.Wr_Re_n(nand2Wr_Re_n),
.Wp_n(nand2Wp_n),
.Ce_n(nand2Ce_n),
.Rb_n(nand2Rb_n),
.DQX(nand2DQX),
.DQS(nand2DQS)
);
//channel 3
Dynamic_Controller flash_controller_instance3 (
.clk_200M(clk), //??????????czg
.rst_n(!reset), //????????????czg
.clk_83X2M(clk_83X2M), //????????czg
.clk_83M(clk_83M),
.clk_83M_reverse(clk_83M_reverse),
.Cmd_In_En(controller_command_fifo_in_en[3]),
.Cmd_In(controller_command_fifo_in),
.Finished_Cmd_Out_En(finish_command_fifo_out_en[3]),
.Data_In_En(write_data_fifo_in_en[3]),
.Data_In(write_data_fifo_in),
.ControllerIdle(idle_flag[3]),
.Cmd_Available(Cmd_Available[3]), //czg??????
.Finished_Cmd_FIFO_Empty(finish_command_fifo_empty_or_not[3]),
.Finished_Cmd_Out(finish_command_fifo_out[3]),
.Data_2_host_en(read_data_fifo_out_en[3]),
.Data_2_host(read_data_fifo_out[3]),
//.Post_Data_Empty(), //use for check
// .Post_Data_Full(), //use for check
//.Post_Data_Valid(), //use for check
.Cle(nand3Cle),
.Ale(nand3Ale),
.Clk_We_n(nand3Clk_We_n),
.Wr_Re_n(nand3Wr_Re_n),
.Wp_n(nand3Wp_n),
.Ce_n(nand3Ce_n),
.Rb_n(nand3Rb_n),
.DQX(nand3DQX),
.DQS(nand3DQS)
);
//channel 4
Dynamic_Controller flash_controller_instance4 (
.clk_200M(clk), //??????????czg
.rst_n(!reset), //????????????czg
.clk_83X2M(clk_83X2M), //????????czg
.clk_83M(clk_83M),
.clk_83M_reverse(clk_83M_reverse),
.Cmd_In_En(controller_command_fifo_in_en[4]),
.Cmd_In(controller_command_fifo_in),
.Finished_Cmd_Out_En(finish_command_fifo_out_en[4]),
.Data_In_En(write_data_fifo_in_en[4]),
.Data_In(write_data_fifo_in),
.ControllerIdle(idle_flag[4]),
.Cmd_Available(Cmd_Available[4]), //czg??????
.Finished_Cmd_FIFO_Empty(finish_command_fifo_empty_or_not[4]),
.Finished_Cmd_Out(finish_command_fifo_out[4]),
.Data_2_host_en(read_data_fifo_out_en[4]),
.Data_2_host(read_data_fifo_out[4]),
//.Post_Data_Empty(), //use for check
//.Post_Data_Full(), //use for check
//.Post_Data_Valid(), //use for check
.Cle(nand4Cle),
.Ale(nand4Ale),
.Clk_We_n(nand4Clk_We_n),
.Wr_Re_n(nand4Wr_Re_n),
.Wp_n(nand4Wp_n),
.Ce_n(nand4Ce_n),
.Rb_n(nand4Rb_n),
.DQX(nand4DQX),
.DQS(nand4DQS)
);
//channel 5
Dynamic_Controller flash_controller_instance5 (
.clk_200M(clk), //??????????czg
.rst_n(!reset), //????????????czg
.clk_83X2M(clk_83X2M), //????????czg
.clk_83M(clk_83M),
.clk_83M_reverse(clk_83M_reverse),
.Cmd_In_En(controller_command_fifo_in_en[5]),
.Cmd_In(controller_command_fifo_in),
.Finished_Cmd_Out_En(finish_command_fifo_out_en[5]),
.Data_In_En(write_data_fifo_in_en[5]),
.Data_In(write_data_fifo_in),
.ControllerIdle(idle_flag[5]),
.Cmd_Available(Cmd_Available[5]), //czg??????
.Finished_Cmd_FIFO_Empty(finish_command_fifo_empty_or_not[5]),
.Finished_Cmd_Out(finish_command_fifo_out[5]),
.Data_2_host_en(read_data_fifo_out_en[5]),
.Data_2_host(read_data_fifo_out[5]),
//.Post_Data_Empty(), //use for check
//.Post_Data_Full(), //use for check
//.Post_Data_Valid(), //use for check
.Cle(nand5Cle),
.Ale(nand5Ale),
.Clk_We_n(nand5Clk_We_n),
.Wr_Re_n(nand5Wr_Re_n),
.Wp_n(nand5Wp_n),
.Ce_n(nand5Ce_n),
.Rb_n(nand5Rb_n),
.DQX(nand5DQX),
.DQS(nand5DQS)
);
//channel 6
Dynamic_Controller flash_controller_instance6 (
.clk_200M(clk), //??????????czg
.rst_n(!reset), //????????????czg
.clk_83X2M(clk_83X2M), //????????czg
.clk_83M(clk_83M),
.clk_83M_reverse(clk_83M_reverse),
.Cmd_In_En(controller_command_fifo_in_en[6]),
.Cmd_In(controller_command_fifo_in),
.Finished_Cmd_Out_En(finish_command_fifo_out_en[6]),
.Data_In_En(write_data_fifo_in_en[6]),
.Data_In(write_data_fifo_in),
.ControllerIdle(idle_flag[6]),
.Cmd_Available(Cmd_Available[6]), //czg??????
.Finished_Cmd_FIFO_Empty(finish_command_fifo_empty_or_not[6]),
.Finished_Cmd_Out(finish_command_fifo_out[6]),
.Data_2_host_en(read_data_fifo_out_en[6]),
.Data_2_host(read_data_fifo_out[6]),
//.Post_Data_Empty(), //use for check
//.Post_Data_Full(), //use for check
//.Post_Data_Valid(), //use for check
.Cle(nand6Cle),
.Ale(nand6Ale),
.Clk_We_n(nand6Clk_We_n),
.Wr_Re_n(nand6Wr_Re_n),
.Wp_n(nand6Wp_n),
.Ce_n(nand6Ce_n),
.Rb_n(nand6Rb_n),
.DQX(nand6DQX),
.DQS(nand6DQS)
);
//channel 7
Dynamic_Controller flash_controller_instance7 (
.clk_200M(clk), //??????????czg
.rst_n(!reset), //????????????czg
.clk_83X2M(clk_83X2M), //????????czg
.clk_83M(clk_83M),
.clk_83M_reverse(clk_83M_reverse),
.Cmd_In_En(controller_command_fifo_in_en[7]),
.Cmd_In(controller_command_fifo_in),
.Finished_Cmd_Out_En(finish_command_fifo_out_en[7]),
.Data_In_En(write_data_fifo_in_en[7]),
.Data_In(write_data_fifo_in),
.ControllerIdle(idle_flag[7]),
.Cmd_Available(Cmd_Available[7]), //czg??????
.Finished_Cmd_FIFO_Empty(finish_command_fifo_empty_or_not[7]),
.Finished_Cmd_Out(finish_command_fifo_out[7]),
.Data_2_host_en(read_data_fifo_out_en[7]),
.Data_2_host(read_data_fifo_out[7]),
//.Post_Data_Empty(), //use for check
//.Post_Data_Full(), //use for check
//.Post_Data_Valid(), //use for check
.Cle(nand7Cle),
.Ale(nand7Ale),
.Clk_We_n(nand7Clk_We_n),
.Wr_Re_n(nand7Wr_Re_n),
.Wp_n(nand7Wp_n),
.Ce_n(nand7Ce_n),
.Rb_n(nand7Rb_n),
.DQX(nand7DQX),
.DQS(nand7DQS)
);
check_command_fifo check_command_fifo_instance(
//input
.reset(!reset),
.clk(clk),
//.init_dram_done(init_dram_done),
.all_controller_command_fifo_empty(all_idle_flag),
.finish_command_fifo0_empty_or_not(finish_command_fifo_empty_or_not[0]),
.finish_command_fifo1_empty_or_not(finish_command_fifo_empty_or_not[1]),
.finish_command_fifo2_empty_or_not(finish_command_fifo_empty_or_not[2]),
.finish_command_fifo3_empty_or_not(finish_command_fifo_empty_or_not[3]),
.finish_command_fifo4_empty_or_not(finish_command_fifo_empty_or_not[4]),
.finish_command_fifo5_empty_or_not(finish_command_fifo_empty_or_not[5]),
.finish_command_fifo6_empty_or_not(finish_command_fifo_empty_or_not[6]),
.finish_command_fifo7_empty_or_not(finish_command_fifo_empty_or_not[7]),
.finish_command_fifo8_empty_or_not(finish_command_fifo_empty_or_not[8]),
.finish_command_fifo0_out(finish_command_fifo_out[0]),
.finish_command_fifo1_out(finish_command_fifo_out[1]),
.finish_command_fifo2_out(finish_command_fifo_out[2]),
.finish_command_fifo3_out(finish_command_fifo_out[3]),
.finish_command_fifo4_out(finish_command_fifo_out[4]),
.finish_command_fifo5_out(finish_command_fifo_out[5]),
.finish_command_fifo6_out(finish_command_fifo_out[6]),
.finish_command_fifo7_out(finish_command_fifo_out[7]),
.finish_command_fifo8_out(finish_command_fifo_out[8]),
.read_data_fifo0_out(read_data_fifo_out[0]),
.read_data_fifo1_out(read_data_fifo_out[1]),
.read_data_fifo2_out(read_data_fifo_out[2]),
.read_data_fifo3_out(read_data_fifo_out[3]),
.read_data_fifo4_out(read_data_fifo_out[4]),
.read_data_fifo5_out(read_data_fifo_out[5]),
.read_data_fifo6_out(read_data_fifo_out[6]),
.read_data_fifo7_out(read_data_fifo_out[7]),
.data_from_dram(data_from_dram),
.dram_ready(dram_ready),
.rd_data_valid(rd_data_valid),
.dram_permit(check_dram_permit),
.pcie_data_send_fifo_out_prog_full(pcie_data_send_fifo_out_prog_full),
.pcie_command_send_fifo_full_or_not(pcie_command_send_fifo_full_or_not),
//output
.finish_command_fifo0_out_en(finish_command_fifo_out_en[0]),
.finish_command_fifo1_out_en(finish_command_fifo_out_en[1]),
.finish_command_fifo2_out_en(finish_command_fifo_out_en[2]),
.finish_command_fifo3_out_en(finish_command_fifo_out_en[3]),
.finish_command_fifo4_out_en(finish_command_fifo_out_en[4]),
.finish_command_fifo5_out_en(finish_command_fifo_out_en[5]),
.finish_command_fifo6_out_en(finish_command_fifo_out_en[6]),
.finish_command_fifo7_out_en(finish_command_fifo_out_en[7]),
.finish_command_fifo8_out_en(finish_command_fifo_out_en[8]),
.read_data_fifo0_out_en(read_data_fifo_out_en[0]),
.read_data_fifo1_out_en(read_data_fifo_out_en[1]),
.read_data_fifo2_out_en(read_data_fifo_out_en[2]),
.read_data_fifo3_out_en(read_data_fifo_out_en[3]),
.read_data_fifo4_out_en(read_data_fifo_out_en[4]),
.read_data_fifo5_out_en(read_data_fifo_out_en[5]),
.read_data_fifo6_out_en(read_data_fifo_out_en[6]),
.read_data_fifo7_out_en(read_data_fifo_out_en[7]),
.dram_request(check_dram_request),
.release_dram(check_release_dram),
.addr_to_dram_o(check_addr_to_dram),
.data_to_dram(check_data_to_dram),
.dram_data_mask(check_dram_data_mask),
.dram_en_o(check_dram_en),
.dram_read_or_write(check_dram_read_or_write),
.data_to_dram_en(check_data_to_dram_en),
.data_to_dram_end(check_data_to_dram_end),
.data_to_dram_ready(data_to_dram_ready),
.pcie_data_send_fifo_in(pcie_data_send_fifo_in),
.pcie_data_send_fifo_in_en(pcie_data_send_fifo_in_en),
.pcie_command_send_fifo_in(pcie_command_send_fifo_in),
.pcie_command_send_fifo_in_en(pcie_command_send_fifo_in_en),
.left_capacity_final(left_capacity_initial),//512GB flashæç9次æ¹ä¸ªå
.free_block_fifo_tails(free_block_fifo_tails_initial),
.free_block_fifo_heads(free_block_fifo_heads_initial),
.register_ready(register_ready),
.initial_dram_done(initial_dram_done),
.state(state_check)
);
backup backup_instance(
.reset(!reset),
.clk(clk),
.dram_backup_en(1'b0),
.backup_op(),
.fifo_enpty_flag(!all_idle_flag),
.state_check(state_check),
.dram_permit(backup_dram_permit),
.data_from_dram(data_from_dram),
.dram_ready(dram_ready),
.rd_data_valid(rd_data_valid),
.left_capacity_final(left_capacity),
.free_block_fifo_heads(free_block_fifo_heads),
.free_block_fifo_tails(free_block_fifo_tails),
.ssd_command_fifo_full(ssd_command_fifo_full),
.controller_command_fifo_full_or_not(!all_Cmd_Available_flag),
.write_data_fifo_prog_full(!all_Cmd_Available_flag),//8 bit
.write_data_fifo_full(!all_Cmd_Available_flag),
.dram_request(backup_dram_request),
.release_dram(backup_release_dram),
.addr_to_dram(backup_addr_to_dram),
.data_to_dram(backup_data_to_dram),
.dram_data_mask(backup_dram_data_mask),
.dram_en(backup_dram_en),
.dram_read_or_write(backup_dram_read_or_write),
.ssd_command_fifo_in(backup_ssd_command_fifo_in),
.ssd_command_fifo_in_en(backup_ssd_command_fifo_in_en),
.controller_command_fifo_in_en(backup_controller_command_fifo_in_en),
.controller_command_fifo_in(backup_controller_command_fifo_in),
.write_data_fifo_in(backup_write_data_fifo_in),
.write_data_fifo_in_en(backup_write_data_fifo_in_en),//8 bit
.backup_or_checkcache(backup_or_checkcache),
.backup_or_io(backup_or_io)
);
endmodule
|
//======================================================================
//
// fltcpu_regfile.v
// ----------------
// This file contains the implementation of all API registers. This
// includes program counter (PC) and status registers.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2015 Secworks Sweden AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module fltcpu_regfile(
// Clock and reset.
input wire clk,
input wire reset_n,
// Main operands.
input wire [4 : 0] src0_addr,
output wire [31 : 0] src0_data,
input wire [4 : 0] src1_addr,
output wire [31 : 0] src1_data,
input wire dst_we,
input wire [4 : 0] dst_addr,
input wire [31 : 0] dst_wr_data,
output wire [31 : 0] dst_rd_data,
// Flags.
output wire zero_flag,
// Program counter.
input wire inc,
input wire ret,
output wire [31 : 0] pc
);
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
localparam BOOT_VECTOR = 32'h00000000;
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
reg [31 : 0] gp_reg [0 : 27];
reg gp_we;
reg zero_reg;
reg zero_we;
reg eq_reg;
reg eq_we;
reg carry_reg;
reg carry_we;
reg [31 : 0] return_reg;
reg return_we;
reg [31 : 0] ret_reg [0 : 15];
reg [31 : 0] ret_new;
reg ret_we;
reg [03 : 0] ret_ptr_reg;
reg [03 : 0] ret_ptr_new;
reg ret_ptr_we;
reg [31 : 0] pc_reg;
reg [31 : 0] pc_new;
reg pc_we;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
reg [31 : 0] tmp_src0_data;
reg [31 : 0] tmp_src1_data;
reg [31 : 0] tmp_dst_rd_data;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign src0_data = tmp_src0_data;
assign src1_data = tmp_src1_data;
assign dst_rd_data = tmp_dst_rd_data;
assign pc = pc_reg;
//----------------------------------------------------------------
// reg_update
// Update functionality for all registers in the core.
// All registers are positive edge triggered with asynchronous
// active low reset.
//----------------------------------------------------------------
always @ (posedge clk or negedge reset_n)
begin : reg_update
integer i;
if (!reset_n)
begin
for (i = 0 ; i < 28 ; i = i + 1)
gp_reg[i] <= 32'h0;
for (i = 0 ; i < 16 ; i = i + 1)
ret_reg[i] <= 32'h0;
ret_ptr_reg <= 4'h0;
pc_reg <= BOOT_VECTOR;
end
else
begin
if (gp_we)
gp_reg[dst_addr] <= dst_wr_data;
if (pc_we)
pc_reg <= pc_new;
if (ret_we)
ret_reg[ret_ptr_reg] <= ret_new;
if (ret_ptr_we)
ret_ptr_reg <= ret_ptr_new;
end
end // reg_update
//----------------------------------------------------------------
// read_src0
//
// Combinational read of operand source 0.
//----------------------------------------------------------------
always @*
begin : read_src0
if (src0_addr == 0)
tmp_src0_data = 32'h0;
if (0 < src0_addr < 29)
tmp_src0_data = gp_reg[(src0_addr - 1)];
else if (src0_addr == 29)
tmp_src0_data = {carry_reg, eq_reg, zero_reg};
else if (src0_addr == 30)
tmp_src0_data = ret_reg[ret_ptr_reg];
else if (src0_addr == 31)
tmp_src0_data = pc_reg;
end // read_src0
//----------------------------------------------------------------
// read_src1
//
// Combinational read of operand source 1.
//----------------------------------------------------------------
always @*
begin : read_src1
if (src1_addr == 0)
tmp_src1_data = 32'h0;
if (0 < src1_addr < 29)
tmp_src1_data = gp_reg[(src1_addr - 1)];
else if (src1_addr == 29)
tmp_src1_data = {carry_reg, eq_reg, zero_reg};
else if (src1_addr == 30)
tmp_src1_data = ret_reg[ret_ptr_reg];
else if (src1_addr == 31)
tmp_src1_data = pc_reg;
end // read_src1
//----------------------------------------------------------------
// read_dst
//
// Combinational read of operand dst.
//----------------------------------------------------------------
always @*
begin : read_dst
if (dst_addr == 0)
tmp_dst_rd_data = 32'h0;
if (0 < dst_addr < 29)
tmp_dst_rd_data = gp_reg[(src1_addr - 1)];
else if (dst_addr == 29)
tmp_dst_rd_data = {carry_reg, eq_reg, zero_reg};
else if (dst_addr == 30)
tmp_dst_rd_data = ret_reg[ret_ptr_reg];
else if (dst_addr == 31)
tmp_dst_rd_data = pc_reg;
end // read_dst
//----------------------------------------------------------------
// update_ctrl
//
// Update logic for the registers including the return register
// and the program counter. The update supports direct writes to
// the PC (i.e. jumps), return and simple increments.
//----------------------------------------------------------------
always @*
begin : pc_update
return_we = 0;
gp_we = 0;
pc_new = 32'h0;
pc_we = 0;
ret_ptr_new = 32'h0;
ret_ptr_we = 0;
if (dst_we && (dst_addr < 30))
gp_we = 1;
if (dst_we && (dst_addr == 30))
begin
ret_new = dst_wr_data;
ret_we = 1;
end
if (dst_we && (dst_addr == 31))
begin
ret_new = pc_reg;
ret_we = 1;
ret_ptr_new = ret_ptr_reg + 1;
ret_ptr_we = 1;
pc_new = dst_wr_data;
pc_we = 1;
end
else if (ret)
begin
ret_ptr_new = ret_ptr_reg - 1;
ret_ptr_we = 1;
pc_new = ret_reg[ret_ptr_reg];
pc_we = 1;
end
else if (inc)
begin
pc_new = pc_reg + 1;
pc_we = 1;
end
end // update_ctrl
endmodule // fltcpu_regfile
//======================================================================
// EOF fltcpu_regfile.v
//======================================================================
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2015.2
// Copyright (C) 2015 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module fir_hw_smpl_V_ram (addr0, ce0, d0, we0, q0, clk);
parameter DWIDTH = 18;
parameter AWIDTH = 7;
parameter MEM_SIZE = 128;
input[AWIDTH-1:0] addr0;
input ce0;
input[DWIDTH-1:0] d0;
input we0;
output reg[DWIDTH-1:0] q0;
input clk;
(* ram_style = "block" *)reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
initial begin
$readmemh("./fir_hw_smpl_V_ram.dat", ram);
end
always @(posedge clk)
begin
if (ce0)
begin
if (we0)
begin
ram[addr0] <= d0;
q0 <= d0;
end
else
q0 <= ram[addr0];
end
end
endmodule
`timescale 1 ns / 1 ps
module fir_hw_smpl_V(
reset,
clk,
address0,
ce0,
we0,
d0,
q0);
parameter DataWidth = 32'd18;
parameter AddressRange = 32'd128;
parameter AddressWidth = 32'd7;
input reset;
input clk;
input[AddressWidth - 1:0] address0;
input ce0;
input we0;
input[DataWidth - 1:0] d0;
output[DataWidth - 1:0] q0;
fir_hw_smpl_V_ram fir_hw_smpl_V_ram_U(
.clk( clk ),
.addr0( address0 ),
.ce0( ce0 ),
.d0( d0 ),
.we0( we0 ),
.q0( q0 ));
endmodule
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