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/*
* spi_regs.v
* State machine which handles reading and writing from the test registers.
* Currently, the test bus width is hardcoded as 37 bits wide, generalize
* later.
* Autogenerated code from the register .csv definition file.
*/
module spi_reg(
// Register read signals
o_dco_rd, o_dcycle_cal_0_rd, o_dcycle_cal_1_rd, o_dlc_rd,
o_dlc_f2p_rd, o_dlc_iir_0_rd, o_dlc_iir_1_rd, o_dlc_iir_2_rd,
o_dlc_iir_3_rd, o_dlc_pi_rd, o_dlc_qnc_rd, o_fdelta_cal_0_rd,
o_fdelta_cal_1_rd, o_fdelta_lms_0_rd, o_fdelta_lms_1_rd,
o_rfdc_0_rd, o_rfdc_1_rd, o_rfdc_state_0_rd, o_rfdc_state_1_rd,
// Register write signals
o_dco_wr, o_dcycle_cal_0_wr, o_dcycle_cal_1_wr, o_dlc_wr,
o_dlc_f2p_wr, o_dlc_iir_0_wr, o_dlc_iir_1_wr, o_dlc_iir_2_wr,
o_dlc_iir_3_wr, o_dlc_pi_wr, o_dlc_qnc_wr, o_fdelta_cal_0_wr,
o_fdelta_cal_1_wr, o_fdelta_lms_0_wr, o_fdelta_lms_1_wr,
o_rfdc_0_wr, o_rfdc_1_wr, o_rfdc_state_0_wr, o_rfdc_state_1_wr,
// Inouts
vio_data_regs, io_success, vio_tbus,
// Inputs
i_rstb, i_clk_ext_osc, i_spi_active, vi_data_rx, i_rx_valid,
vi_byte_num);
// This global variable defines the number of registers
localparam NUM_REGS = 19;
// Global reset
input i_rstb;
// State machine clock
input i_clk_ext_osc;
// SPI interface
input i_spi_active;
input [7:0] vi_data_rx;
input i_rx_valid;
input [2:0] vi_byte_num;
inout [7:0] vio_data_regs;
// Test bus
inout io_success;
inout [36:0] vio_tbus;
// Register read and write controls
output o_dco_rd;
output o_dcycle_cal_0_rd;
output o_dcycle_cal_1_rd;
output o_dlc_rd;
output o_dlc_f2p_rd;
output o_dlc_iir_0_rd;
output o_dlc_iir_1_rd;
output o_dlc_iir_2_rd;
output o_dlc_iir_3_rd;
output o_dlc_pi_rd;
output o_dlc_qnc_rd;
output o_fdelta_cal_0_rd;
output o_fdelta_cal_1_rd;
output o_fdelta_lms_0_rd;
output o_fdelta_lms_1_rd;
output o_rfdc_0_rd;
output o_rfdc_1_rd;
output o_rfdc_state_0_rd;
output o_rfdc_state_1_rd;
output o_dco_wr;
output o_dcycle_cal_0_wr;
output o_dcycle_cal_1_wr;
output o_dlc_wr;
output o_dlc_f2p_wr;
output o_dlc_iir_0_wr;
output o_dlc_iir_1_wr;
output o_dlc_iir_2_wr;
output o_dlc_iir_3_wr;
output o_dlc_pi_wr;
output o_dlc_qnc_wr;
output o_fdelta_cal_0_wr;
output o_fdelta_cal_1_wr;
output o_fdelta_lms_0_wr;
output o_fdelta_lms_1_wr;
output o_rfdc_0_wr;
output o_rfdc_1_wr;
output o_rfdc_state_0_wr;
output o_rfdc_state_1_wr;
/*
* These vectors define the data mask for the test bus reads
*/
reg [7:0] rv_addr;
reg [36:0] rv_rd_mask;
always @( * ) begin
case ( rv_addr )
0 : rv_rd_mask = {{7{1'b0}},{30{1'b1}}};
1 : rv_rd_mask = {{12{1'b0}},{25{1'b1}}};
2 : rv_rd_mask = {37{1'b1}};
3 : rv_rd_mask = {{17{1'b0}},{20{1'b1}}};
4 : rv_rd_mask = {{9{1'b0}},{28{1'b1}}};
5 : rv_rd_mask = {{7{1'b0}},{30{1'b1}}};
6 : rv_rd_mask = {{12{1'b0}},{25{1'b1}}};
7 : rv_rd_mask = {37{1'b1}};
8 : rv_rd_mask = {{17{1'b0}},{20{1'b1}}};
9 : rv_rd_mask = {{9{1'b0}},{28{1'b1}}};
10 : rv_rd_mask = {{17{1'b0}},{20{1'b1}}};
11 : rv_rd_mask = {{4{1'b0}},{33{1'b1}}};
12 : rv_rd_mask = {{15{1'b0}},{22{1'b1}}};
13 : rv_rd_mask = {{15{1'b0}},{22{1'b1}}};
14 : rv_rd_mask = {{15{1'b0}},{22{1'b1}}};
15 : rv_rd_mask = {{15{1'b0}},{22{1'b1}}};
16 : rv_rd_mask = {{3{1'b0}},{34{1'b1}}};
17 : rv_rd_mask = {{15{1'b0}},{22{1'b1}}};
18 : rv_rd_mask = {{28{1'b0}},{9{1'b1}}};
default : rv_rd_mask = {NUM_REGS{1'b0}};
endcase // case ( rv_addr )
end
/*
* These vectors define the number of bytes transmitted for the
* corresponding register. In the MSB register, unused bits are 0
* due to the data coming in the test bus being masked off.
*/
reg [NUM_REGS-1:0] rv_num_rd_bytes;
always @( * ) begin
case ( rv_addr )
0 : rv_num_rd_bytes = 4; // rfdc_state_0
1 : rv_num_rd_bytes = 4; // fdelta_cal_0
2 : rv_num_rd_bytes = 5; // fdelta_lms_0
3 : rv_num_rd_bytes = 3; // dcycle_cal_0
4 : rv_num_rd_bytes = 4; // rfdc_0
5 : rv_num_rd_bytes = 4; // rfdc_state_1
6 : rv_num_rd_bytes = 4; // fdelta_cal_1
7 : rv_num_rd_bytes = 5; // fdelta_lms_1
8 : rv_num_rd_bytes = 3; // dcycle_cal_1
9 : rv_num_rd_bytes = 4; // rfdc_1
10 : rv_num_rd_bytes = 3; // dlc_f2p
11 : rv_num_rd_bytes = 5; // dlc_qnc
12 : rv_num_rd_bytes = 3; // dlc_iir_0
13 : rv_num_rd_bytes = 3; // dlc_iir_1
14 : rv_num_rd_bytes = 3; // dlc_iir_2
15 : rv_num_rd_bytes = 3; // dlc_iir_3
16 : rv_num_rd_bytes = 5; // dlc_pi
17 : rv_num_rd_bytes = 3; // dlc
18 : rv_num_rd_bytes = 2; // dco
default : rv_num_rd_bytes = 0;
endcase // case ( rv_addr )
end
/*
* This register groups all the _rd wires into a single bus, such that
* rv_rd_bus[n] corresponds to the _rd wire associated with the register
* at address n.
*/
reg [NUM_REGS-1:0] rv_rd_tbus;
assign o_rfdc_state_0_rd = rv_rd_tbus[0];
assign o_fdelta_cal_0_rd = rv_rd_tbus[1];
assign o_fdelta_lms_0_rd = rv_rd_tbus[2];
assign o_dcycle_cal_0_rd = rv_rd_tbus[3];
assign o_rfdc_0_rd = rv_rd_tbus[4];
assign o_rfdc_state_1_rd = rv_rd_tbus[5];
assign o_fdelta_cal_1_rd = rv_rd_tbus[6];
assign o_fdelta_lms_1_rd = rv_rd_tbus[7];
assign o_dcycle_cal_1_rd = rv_rd_tbus[8];
assign o_rfdc_1_rd = rv_rd_tbus[9];
assign o_dlc_f2p_rd = rv_rd_tbus[10];
assign o_dlc_qnc_rd = rv_rd_tbus[11];
assign o_dlc_iir_0_rd = rv_rd_tbus[12];
assign o_dlc_iir_1_rd = rv_rd_tbus[13];
assign o_dlc_iir_2_rd = rv_rd_tbus[14];
assign o_dlc_iir_3_rd = rv_rd_tbus[15];
assign o_dlc_pi_rd = rv_rd_tbus[16];
assign o_dlc_rd = rv_rd_tbus[17];
assign o_dco_rd = rv_rd_tbus[18];
/*
* This does the same for the _wr wires
*/
reg [NUM_REGS-1:0] rv_wr_tbus;
assign o_rfdc_state_0_wr = rv_wr_tbus[0];
assign o_fdelta_cal_0_wr = rv_wr_tbus[1];
assign o_fdelta_lms_0_wr = rv_wr_tbus[2];
assign o_dcycle_cal_0_wr = rv_wr_tbus[3];
assign o_rfdc_0_wr = rv_wr_tbus[4];
assign o_rfdc_state_1_wr = rv_wr_tbus[5];
assign o_fdelta_cal_1_wr = rv_wr_tbus[6];
assign o_fdelta_lms_1_wr = rv_wr_tbus[7];
assign o_dcycle_cal_1_wr = rv_wr_tbus[8];
assign o_rfdc_1_wr = rv_wr_tbus[9];
assign o_dlc_f2p_wr = rv_wr_tbus[10];
assign o_dlc_qnc_wr = rv_wr_tbus[11];
assign o_dlc_iir_0_wr = rv_wr_tbus[12];
assign o_dlc_iir_1_wr = rv_wr_tbus[13];
assign o_dlc_iir_2_wr = rv_wr_tbus[14];
assign o_dlc_iir_3_wr = rv_wr_tbus[15];
assign o_dlc_pi_wr = rv_wr_tbus[16];
assign o_dlc_wr = rv_wr_tbus[17];
assign o_dco_wr = rv_wr_tbus[18];
/*
* Local reset
*/
wire active = i_rstb && i_spi_active;
/*
* This state machine simply captures the opcode on the arrival
* of the first (0th) byte, and enables the oscillator
*/
reg r_read_tbus;
reg r_write_tbus;
reg r_clamp_success;
always @( posedge i_rx_valid or negedge active ) begin : opcode_fsm
if ( !active ) begin
r_read_tbus <= 0;
r_write_tbus <= 0;
r_clamp_success <= 1;
end else begin
if ( 0 == vi_byte_num ) begin
if ( 128 == vi_data_rx ) begin
r_write_tbus <= 1;
r_clamp_success <= 0;
end
if ( 192 == vi_data_rx ) begin
r_read_tbus <= 1;
r_clamp_success <= 0;
end
end
end
end // block: opcode_fsm
assign io_success = r_clamp_success ? 1'b0 : 1'bz;
/*
* This state machine captures the address arriving on byte 1 regardless
* of whether the register interface is active or not.
*/
always @( posedge i_rx_valid or negedge active ) begin : address_fsm
if ( !active ) begin
rv_addr <= 0;
end else begin
if ( 1 == vi_byte_num )
rv_addr <= vi_data_rx;
end
end
/*
* This state machine handles register reads. When the address is loaded,
* ena_reg_read triggers the state machine clocked by the internal oscillator
* The data which is read from the test bus is then serialized out one
* byte at a time, from the LSB chunk to the MSB chunk.
* The shadow byte is initialized to an invalid value (7) which makes
* the output mux drive a 0.
*/
reg [2:0] rv_shadow_byte;
reg [7:0] rv_reg2spi;
reg r_ena_reg_read;
always @( posedge i_rx_valid or negedge active ) begin : read_fsm
if ( !active ) begin
rv_shadow_byte <= 7;
r_ena_reg_read <= 0;
end else begin
if (( 1 == vi_byte_num ) && r_read_tbus )
r_ena_reg_read <= 1;
if ( rv_num_rd_bytes >= vi_byte_num )
rv_shadow_byte <= vi_byte_num - 1;
else
rv_shadow_byte <= 7;
end
end
// The byte of the shadow register is addressed by the byte number
reg [36:0] rv_read_shadow;
always @( * ) begin
case ( rv_shadow_byte )
0 : rv_reg2spi = rv_read_shadow[7:0];
1 : rv_reg2spi = rv_read_shadow[15:8];
2 : rv_reg2spi = rv_read_shadow[23:16];
3 : rv_reg2spi = rv_read_shadow[31:24];
4 : rv_reg2spi = {3'b000,rv_read_shadow[36:32]};
default : rv_reg2spi = 0;
endcase // case ( rv_shadow_byte )
end
/*
* This state machine handles parallelizing the byte-widge chunks coming
* from the SPI into the full 37 bit test bus vector. When the parallel
* shadow bus is loaded, ena_reg_write is raised which initiates the state
* machine clocked by the internal oscillator.
*/
reg [36:0] rv_write_shadow;
reg r_ena_reg_write;
reg r_ser2par_done;
always @( posedge i_rx_valid or negedge active ) begin : write_fsm
if ( ! active ) begin
r_ena_reg_write <= 0;
r_ser2par_done <= 0;
rv_write_shadow <= 0;
end else begin
if ( !r_ser2par_done ) begin
// Serialize the data while the byte number is within the register size
if ( 2 == vi_byte_num )
rv_write_shadow[7:0] <= vi_data_rx;
if ( 3 == vi_byte_num )
rv_write_shadow[15:8] <= vi_data_rx;
if ( 4 == vi_byte_num )
rv_write_shadow[23:16] <= vi_data_rx;
if ( 5 == vi_byte_num )
rv_write_shadow[31:24] <= vi_data_rx;
if ( 6 == vi_byte_num )
rv_write_shadow[36:32] <= vi_data_rx[4:0];
if ( rv_num_rd_bytes < vi_byte_num ) begin
// When enough bytes are loaded, stop loading data
r_ser2par_done <= 1;
r_ena_reg_write <= r_write_tbus;
end
end
end
end
/*
* This state machine is clocked on the external oscillator. It
* sends the appropriate _rd signal, waits for the success line to go
* high, then latches the data on the test bus to the shadow register
*/
reg [1:0] rv_rd_state;
localparam READ_IDLE = 0;
localparam READ_WAIT = 1;
localparam READ_DONE = 2;
always @( posedge i_clk_ext_osc or negedge active ) begin
if ( !active ) begin
rv_read_shadow <= 0;
rv_rd_tbus <= 0;
rv_rd_state <= READ_IDLE;
end else begin
if (( READ_IDLE == rv_rd_state ) && r_ena_reg_read ) begin
// A read was just initiated, and we need to send the right _rd
rv_rd_tbus[rv_addr] <= 1;
rv_rd_state <= READ_WAIT;
end
if (( READ_WAIT == rv_rd_state ) && io_success ) begin
// The read had been initiated, and now data has appeared on the bus
rv_read_shadow <= vio_tbus & rv_rd_mask;
rv_rd_tbus <= 0;
rv_rd_state <= READ_DONE;
end
if ( READ_DONE == rv_rd_state ) begin
// Wait here forever until SPI goes inactive again
rv_rd_tbus <= 0;
rv_rd_state <= READ_DONE;
end
end
end
/*
* This state machine handles writing data to the register interface
*/
reg [1:0] rv_wr_state;
localparam WRITE_IDLE = 0;
localparam WRITE_WAIT = 1;
localparam WRITE_DONE = 2;
always @( posedge i_clk_ext_osc or negedge active ) begin
if ( !active ) begin
rv_wr_tbus <= 0;
rv_wr_state <= WRITE_IDLE;
end else begin
if (( WRITE_IDLE == rv_wr_state ) && r_ena_reg_write ) begin
// A write was just initiated, now send the right _wr and wait
rv_wr_tbus[rv_addr] <= 1;
rv_wr_state <= WRITE_WAIT;
end
if (( WRITE_WAIT == rv_wr_state ) && io_success ) begin
// The success signal indicates the data on vio_tbus was latched in
rv_wr_tbus <= 0;
rv_wr_state <= WRITE_DONE;
end
if ( WRITE_DONE == rv_wr_state ) begin
// Stay here until bus resets
rv_wr_tbus <= 0;
rv_wr_state <= WRITE_DONE;
end
end
end
/*
* Tristate bus driver: drive the test bus when in register write mode,
* otherwise leave it floating.
*/
assign vio_tbus = r_write_tbus ? rv_write_shadow : 37'bz;
/*
* Tristate bus driver: only drive data back to SPI when we are in
* register read mode, otherwise float bus.
*/
assign vio_data_regs = r_read_tbus ? rv_reg2spi : 8'bz;
endmodule // spi_regs
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
module tb (
input wire FCLK_IN,
//full speed
inout wire [7:0] BUS_DATA,
input wire [15:0] ADD,
input wire RD_B,
input wire WR_B,
//high speed
inout wire [7:0] FD,
input wire FREAD,
input wire FSTROBE,
input wire FMODE
);
wire [19:0] SRAM_A;
wire SRAM_BHE_B;
wire SRAM_BLE_B;
wire SRAM_CE1_B;
wire SRAM_OE_B;
wire SRAM_WE_B;
// Bidirs
wire [15:0] SRAM_IO;
wire SR_IN;
wire GLOBAL_SR_CLK;
wire GLOBAL_CTR_LD;
wire GLOBAL_DAC_LD;
wire PIXEL_SR_CLK;
wire INJECT;
// Instantiate the Unit Under Test (UUT)
pixel uut (
.FCLK_IN(FCLK_IN),
.BUS_DATA(BUS_DATA),
.ADD(ADD),
.RD_B(RD_B),
.WR_B(WR_B),
.FD(FD),
.FREAD(FREAD),
.FSTROBE(FSTROBE),
.FMODE(FMODE),
.DEBUG_D(),
.LED1(),
.LED2(),
.LED3(),
.LED4(),
.LED5(),
.SRAM_A(SRAM_A),
.SRAM_IO(SRAM_IO),
.SRAM_BHE_B(SRAM_BHE_B),
.SRAM_BLE_B(SRAM_BLE_B),
.SRAM_CE1_B(SRAM_CE1_B),
.SRAM_OE_B(SRAM_OE_B),
.SRAM_WE_B(SRAM_WE_B),
.SR_IN(SR_IN),
.GLOBAL_SR_CLK(GLOBAL_SR_CLK),
.GLOBAL_CTR_LD(GLOBAL_CTR_LD),
.GLOBAL_DAC_LD(GLOBAL_DAC_LD),
.PIXEL_SR_CLK(PIXEL_SR_CLK),
.PIXEL_SR_OUT(SR_IN), // loop SR_IN to SR_OUT for testing
.HIT_OR(INJECT), // loop INJECT to HIT_OR for testing
.INJECT(INJECT)
);
/// SRAM Model
reg [15:0] sram [1048576-1:0];
always@(negedge SRAM_WE_B)
sram[SRAM_A] <= SRAM_IO;
assign SRAM_IO = !SRAM_OE_B ? sram[SRAM_A] : 16'hzzzz;
initial begin
$dumpfile("pixel.vcd");
$dumpvars(0);
end
endmodule
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2012 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file orlink_wtl_fifo.v when simulating
// the core, orlink_wtl_fifo. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module orlink_wtl_fifo(
rst,
wr_clk,
rd_clk,
din,
wr_en,
rd_en,
dout,
full,
empty
);
input rst;
input wr_clk;
input rd_clk;
input [31 : 0] din;
input wr_en;
input rd_en;
output [7 : 0] dout;
output full;
output empty;
// synthesis translate_off
FIFO_GENERATOR_V8_2 #(
.C_ADD_NGC_CONSTRAINT(0),
.C_APPLICATION_TYPE_AXIS(0),
.C_APPLICATION_TYPE_RACH(0),
.C_APPLICATION_TYPE_RDCH(0),
.C_APPLICATION_TYPE_WACH(0),
.C_APPLICATION_TYPE_WDCH(0),
.C_APPLICATION_TYPE_WRCH(0),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_AXI_DATA_WIDTH(64),
.C_AXI_ID_WIDTH(4),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_TYPE(0),
.C_AXI_WUSER_WIDTH(1),
.C_AXIS_TDATA_WIDTH(64),
.C_AXIS_TDEST_WIDTH(4),
.C_AXIS_TID_WIDTH(8),
.C_AXIS_TKEEP_WIDTH(4),
.C_AXIS_TSTRB_WIDTH(4),
.C_AXIS_TUSER_WIDTH(4),
.C_AXIS_TYPE(0),
.C_COMMON_CLOCK(0),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(8),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH(32),
.C_DIN_WIDTH_AXIS(1),
.C_DIN_WIDTH_RACH(32),
.C_DIN_WIDTH_RDCH(64),
.C_DIN_WIDTH_WACH(32),
.C_DIN_WIDTH_WDCH(64),
.C_DIN_WIDTH_WRCH(2),
.C_DOUT_RST_VAL("0"),
.C_DOUT_WIDTH(8),
.C_ENABLE_RLOCS(0),
.C_ENABLE_RST_SYNC(1),
.C_ERROR_INJECTION_TYPE(0),
.C_ERROR_INJECTION_TYPE_AXIS(0),
.C_ERROR_INJECTION_TYPE_RACH(0),
.C_ERROR_INJECTION_TYPE_RDCH(0),
.C_ERROR_INJECTION_TYPE_WACH(0),
.C_ERROR_INJECTION_TYPE_WDCH(0),
.C_ERROR_INJECTION_TYPE_WRCH(0),
.C_FAMILY("spartan6"),
.C_FULL_FLAGS_RST_VAL(1),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(0),
.C_HAS_AXI_ARUSER(0),
.C_HAS_AXI_AWUSER(0),
.C_HAS_AXI_BUSER(0),
.C_HAS_AXI_RD_CHANNEL(0),
.C_HAS_AXI_RUSER(0),
.C_HAS_AXI_WR_CHANNEL(0),
.C_HAS_AXI_WUSER(0),
.C_HAS_AXIS_TDATA(0),
.C_HAS_AXIS_TDEST(0),
.C_HAS_AXIS_TID(0),
.C_HAS_AXIS_TKEEP(0),
.C_HAS_AXIS_TLAST(0),
.C_HAS_AXIS_TREADY(1),
.C_HAS_AXIS_TSTRB(0),
.C_HAS_AXIS_TUSER(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_DATA_COUNTS_AXIS(0),
.C_HAS_DATA_COUNTS_RACH(0),
.C_HAS_DATA_COUNTS_RDCH(0),
.C_HAS_DATA_COUNTS_WACH(0),
.C_HAS_DATA_COUNTS_WDCH(0),
.C_HAS_DATA_COUNTS_WRCH(0),
.C_HAS_INT_CLK(0),
.C_HAS_MASTER_CE(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_PROG_FLAGS_AXIS(0),
.C_HAS_PROG_FLAGS_RACH(0),
.C_HAS_PROG_FLAGS_RDCH(0),
.C_HAS_PROG_FLAGS_WACH(0),
.C_HAS_PROG_FLAGS_WDCH(0),
.C_HAS_PROG_FLAGS_WRCH(0),
.C_HAS_RD_DATA_COUNT(0),
.C_HAS_RD_RST(0),
.C_HAS_RST(1),
.C_HAS_SLAVE_CE(0),
.C_HAS_SRST(0),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(0),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(2),
.C_IMPLEMENTATION_TYPE_AXIS(1),
.C_IMPLEMENTATION_TYPE_RACH(1),
.C_IMPLEMENTATION_TYPE_RDCH(1),
.C_IMPLEMENTATION_TYPE_WACH(1),
.C_IMPLEMENTATION_TYPE_WDCH(1),
.C_IMPLEMENTATION_TYPE_WRCH(1),
.C_INIT_WR_PNTR_VAL(0),
.C_INTERFACE_TYPE(0),
.C_MEMORY_TYPE(1),
.C_MIF_FILE_NAME("BlankString"),
.C_MSGON_VAL(1),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(1),
.C_PRELOAD_REGS(0),
.C_PRIM_FIFO_TYPE("512x36"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(2),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(3),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_EMPTY_TYPE_AXIS(5),
.C_PROG_EMPTY_TYPE_RACH(5),
.C_PROG_EMPTY_TYPE_RDCH(5),
.C_PROG_EMPTY_TYPE_WACH(5),
.C_PROG_EMPTY_TYPE_WDCH(5),
.C_PROG_EMPTY_TYPE_WRCH(5),
.C_PROG_FULL_THRESH_ASSERT_VAL(253),
.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023),
.C_PROG_FULL_THRESH_NEGATE_VAL(252),
.C_PROG_FULL_TYPE(0),
.C_PROG_FULL_TYPE_AXIS(5),
.C_PROG_FULL_TYPE_RACH(5),
.C_PROG_FULL_TYPE_RDCH(5),
.C_PROG_FULL_TYPE_WACH(5),
.C_PROG_FULL_TYPE_WDCH(5),
.C_PROG_FULL_TYPE_WRCH(5),
.C_RACH_TYPE(0),
.C_RD_DATA_COUNT_WIDTH(10),
.C_RD_DEPTH(1024),
.C_RD_FREQ(1),
.C_RD_PNTR_WIDTH(10),
.C_RDCH_TYPE(0),
.C_REG_SLICE_MODE_AXIS(0),
.C_REG_SLICE_MODE_RACH(0),
.C_REG_SLICE_MODE_RDCH(0),
.C_REG_SLICE_MODE_WACH(0),
.C_REG_SLICE_MODE_WDCH(0),
.C_REG_SLICE_MODE_WRCH(0),
.C_UNDERFLOW_LOW(0),
.C_USE_COMMON_OVERFLOW(0),
.C_USE_COMMON_UNDERFLOW(0),
.C_USE_DEFAULT_SETTINGS(0),
.C_USE_DOUT_RST(1),
.C_USE_ECC(0),
.C_USE_ECC_AXIS(0),
.C_USE_ECC_RACH(0),
.C_USE_ECC_RDCH(0),
.C_USE_ECC_WACH(0),
.C_USE_ECC_WDCH(0),
.C_USE_ECC_WRCH(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(0),
.C_VALID_LOW(0),
.C_WACH_TYPE(0),
.C_WDCH_TYPE(0),
.C_WR_ACK_LOW(0),
.C_WR_DATA_COUNT_WIDTH(8),
.C_WR_DEPTH(256),
.C_WR_DEPTH_AXIS(1024),
.C_WR_DEPTH_RACH(16),
.C_WR_DEPTH_RDCH(1024),
.C_WR_DEPTH_WACH(16),
.C_WR_DEPTH_WDCH(1024),
.C_WR_DEPTH_WRCH(16),
.C_WR_FREQ(1),
.C_WR_PNTR_WIDTH(8),
.C_WR_PNTR_WIDTH_AXIS(10),
.C_WR_PNTR_WIDTH_RACH(4),
.C_WR_PNTR_WIDTH_RDCH(10),
.C_WR_PNTR_WIDTH_WACH(4),
.C_WR_PNTR_WIDTH_WDCH(10),
.C_WR_PNTR_WIDTH_WRCH(4),
.C_WR_RESPONSE_LATENCY(1),
.C_WRCH_TYPE(0)
)
inst (
.RST(rst),
.WR_CLK(wr_clk),
.RD_CLK(rd_clk),
.DIN(din),
.WR_EN(wr_en),
.RD_EN(rd_en),
.DOUT(dout),
.FULL(full),
.EMPTY(empty),
.BACKUP(),
.BACKUP_MARKER(),
.CLK(),
.SRST(),
.WR_RST(),
.RD_RST(),
.PROG_EMPTY_THRESH(),
.PROG_EMPTY_THRESH_ASSERT(),
.PROG_EMPTY_THRESH_NEGATE(),
.PROG_FULL_THRESH(),
.PROG_FULL_THRESH_ASSERT(),
.PROG_FULL_THRESH_NEGATE(),
.INT_CLK(),
.INJECTDBITERR(),
.INJECTSBITERR(),
.ALMOST_FULL(),
.WR_ACK(),
.OVERFLOW(),
.ALMOST_EMPTY(),
.VALID(),
.UNDERFLOW(),
.DATA_COUNT(),
.RD_DATA_COUNT(),
.WR_DATA_COUNT(),
.PROG_FULL(),
.PROG_EMPTY(),
.SBITERR(),
.DBITERR(),
.M_ACLK(),
.S_ACLK(),
.S_ARESETN(),
.M_ACLK_EN(),
.S_ACLK_EN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWLOCK(),
.S_AXI_AWCACHE(),
.S_AXI_AWPROT(),
.S_AXI_AWQOS(),
.S_AXI_AWREGION(),
.S_AXI_AWUSER(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WID(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WUSER(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BUSER(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.M_AXI_AWID(),
.M_AXI_AWADDR(),
.M_AXI_AWLEN(),
.M_AXI_AWSIZE(),
.M_AXI_AWBURST(),
.M_AXI_AWLOCK(),
.M_AXI_AWCACHE(),
.M_AXI_AWPROT(),
.M_AXI_AWQOS(),
.M_AXI_AWREGION(),
.M_AXI_AWUSER(),
.M_AXI_AWVALID(),
.M_AXI_AWREADY(),
.M_AXI_WID(),
.M_AXI_WDATA(),
.M_AXI_WSTRB(),
.M_AXI_WLAST(),
.M_AXI_WUSER(),
.M_AXI_WVALID(),
.M_AXI_WREADY(),
.M_AXI_BID(),
.M_AXI_BRESP(),
.M_AXI_BUSER(),
.M_AXI_BVALID(),
.M_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARLOCK(),
.S_AXI_ARCACHE(),
.S_AXI_ARPROT(),
.S_AXI_ARQOS(),
.S_AXI_ARREGION(),
.S_AXI_ARUSER(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RUSER(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.M_AXI_ARID(),
.M_AXI_ARADDR(),
.M_AXI_ARLEN(),
.M_AXI_ARSIZE(),
.M_AXI_ARBURST(),
.M_AXI_ARLOCK(),
.M_AXI_ARCACHE(),
.M_AXI_ARPROT(),
.M_AXI_ARQOS(),
.M_AXI_ARREGION(),
.M_AXI_ARUSER(),
.M_AXI_ARVALID(),
.M_AXI_ARREADY(),
.M_AXI_RID(),
.M_AXI_RDATA(),
.M_AXI_RRESP(),
.M_AXI_RLAST(),
.M_AXI_RUSER(),
.M_AXI_RVALID(),
.M_AXI_RREADY(),
.S_AXIS_TVALID(),
.S_AXIS_TREADY(),
.S_AXIS_TDATA(),
.S_AXIS_TSTRB(),
.S_AXIS_TKEEP(),
.S_AXIS_TLAST(),
.S_AXIS_TID(),
.S_AXIS_TDEST(),
.S_AXIS_TUSER(),
.M_AXIS_TVALID(),
.M_AXIS_TREADY(),
.M_AXIS_TDATA(),
.M_AXIS_TSTRB(),
.M_AXIS_TKEEP(),
.M_AXIS_TLAST(),
.M_AXIS_TID(),
.M_AXIS_TDEST(),
.M_AXIS_TUSER(),
.AXI_AW_INJECTSBITERR(),
.AXI_AW_INJECTDBITERR(),
.AXI_AW_PROG_FULL_THRESH(),
.AXI_AW_PROG_EMPTY_THRESH(),
.AXI_AW_DATA_COUNT(),
.AXI_AW_WR_DATA_COUNT(),
.AXI_AW_RD_DATA_COUNT(),
.AXI_AW_SBITERR(),
.AXI_AW_DBITERR(),
.AXI_AW_OVERFLOW(),
.AXI_AW_UNDERFLOW(),
.AXI_W_INJECTSBITERR(),
.AXI_W_INJECTDBITERR(),
.AXI_W_PROG_FULL_THRESH(),
.AXI_W_PROG_EMPTY_THRESH(),
.AXI_W_DATA_COUNT(),
.AXI_W_WR_DATA_COUNT(),
.AXI_W_RD_DATA_COUNT(),
.AXI_W_SBITERR(),
.AXI_W_DBITERR(),
.AXI_W_OVERFLOW(),
.AXI_W_UNDERFLOW(),
.AXI_B_INJECTSBITERR(),
.AXI_B_INJECTDBITERR(),
.AXI_B_PROG_FULL_THRESH(),
.AXI_B_PROG_EMPTY_THRESH(),
.AXI_B_DATA_COUNT(),
.AXI_B_WR_DATA_COUNT(),
.AXI_B_RD_DATA_COUNT(),
.AXI_B_SBITERR(),
.AXI_B_DBITERR(),
.AXI_B_OVERFLOW(),
.AXI_B_UNDERFLOW(),
.AXI_AR_INJECTSBITERR(),
.AXI_AR_INJECTDBITERR(),
.AXI_AR_PROG_FULL_THRESH(),
.AXI_AR_PROG_EMPTY_THRESH(),
.AXI_AR_DATA_COUNT(),
.AXI_AR_WR_DATA_COUNT(),
.AXI_AR_RD_DATA_COUNT(),
.AXI_AR_SBITERR(),
.AXI_AR_DBITERR(),
.AXI_AR_OVERFLOW(),
.AXI_AR_UNDERFLOW(),
.AXI_R_INJECTSBITERR(),
.AXI_R_INJECTDBITERR(),
.AXI_R_PROG_FULL_THRESH(),
.AXI_R_PROG_EMPTY_THRESH(),
.AXI_R_DATA_COUNT(),
.AXI_R_WR_DATA_COUNT(),
.AXI_R_RD_DATA_COUNT(),
.AXI_R_SBITERR(),
.AXI_R_DBITERR(),
.AXI_R_OVERFLOW(),
.AXI_R_UNDERFLOW(),
.AXIS_INJECTSBITERR(),
.AXIS_INJECTDBITERR(),
.AXIS_PROG_FULL_THRESH(),
.AXIS_PROG_EMPTY_THRESH(),
.AXIS_DATA_COUNT(),
.AXIS_WR_DATA_COUNT(),
.AXIS_RD_DATA_COUNT(),
.AXIS_SBITERR(),
.AXIS_DBITERR(),
.AXIS_OVERFLOW(),
.AXIS_UNDERFLOW()
);
// synthesis translate_on
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DLRTP_PP_BLACKBOX_V
`define SKY130_FD_SC_HVL__DLRTP_PP_BLACKBOX_V
/**
* dlrtp: Delay latch, inverted reset, non-inverted enable,
* single output.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__dlrtp (
Q ,
RESET_B,
D ,
GATE ,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input RESET_B;
input D ;
input GATE ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DLRTP_PP_BLACKBOX_V
|
`timescale 1ns / 1ps
`include "cache_defines.vh"
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:39:36 03/01/2015
// Design Name: cache
// Module Name: D:/Modelsim Projects/Xilinx/cache_implementation/top_tb.v
// Project Name: cache_implementation
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: cache
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module cacheblock1_tb;
parameter TAG_WIDTH = 8; // width of the tag
parameter DATA_WIDTH = 16; // width of the data
parameter ENTRIES_WIDTH = 64; // # of entries
parameter OPCODE_WIDTH = 2; // width of opcode
parameter LINE_WIDTH = TAG_WIDTH+DATA_WIDTH+OPCODE_WIDTH; // length of the input vector
// Inputs
reg [LINE_WIDTH-1:0]vector_in;
reg clk;
reg enable;
reg [TAG_WIDTH-1:0]tag_count;
reg [DATA_WIDTH-1:0]data_test;
// Outputs
wire [DATA_WIDTH-1:0]data_out;
wire [DATA_WIDTH-1:0]data_out_miss;
wire [TAG_WIDTH-1:0]tag_out_miss;
wire hit_miss_out;
// Instantiate the Unit Under Test (UUT)
cache #(TAG_WIDTH,DATA_WIDTH,ENTRIES_WIDTH) cacheblock1 (
.data_out(data_out),
.data_out_miss(data_out_miss),
.tag_out_miss(tag_out_miss),
.hit_miss_out(hit_miss_out),
.vector_in(vector_in),
.clk(clk),
.enable(enable)
);
initial begin
// Initialize Inputs
// data_in = 0;
clk = 0;
enable = 0;
// Wait 100 ns for global reset to finish
// Fill up cache
tag_count = {TAG_WIDTH{1'b0}};
data_test = {DATA_WIDTH{1'b1}};
// This loop fills up the cache
repeat(ENTRIES_WIDTH)begin: bench1
#2 vector_in = {`WRITE,tag_count,data_test}; // write to a new tag entry every time
// #2 vector_in = {2'b01,tag_count,data_test}; // read such tag entry
tag_count = tag_count + 8'b1;
data_test = data_test + 16'b1;
end // end repeat loop
// This loop reads all the data that has been written in the cache previously
#2 tag_count = {TAG_WIDTH{1'b0}};
#2 data_test = {DATA_WIDTH{1'b1}};
repeat(ENTRIES_WIDTH)begin: bench2
#2 vector_in = {`READ,tag_count,data_test}; // write to a new tag entry every time
// #2 vector_in = {`READ,8'b111,data_test}; // read a new tag entry every time
// #2 vector_in = {`READ,8'b1010,data_test}; // read a new tag entry every time
// #2 vector_in = {`READ,8'b1111,data_test}; // read a new tag entry every time
// #2 vector_in = {2'b01,tag_count,data_test}; // read such tag entry
tag_count = tag_count + 1'b1;
data_test = data_test + 1'b1;
end // end repeat loop
#2 vector_in = 26'b10_11111111_0001000100010001; // write to a different tag entry
#2 vector_in = 26'b01_11111111_0001000100010001; // read the above tag entry
#2 vector_in = 26'b01_00001111_0001000100010001; // read the above tag entry
repeat(4)begin: bench3
#2 vector_in = {`READ,8'b00001010,data_test}; // read same tag entry every time
// #2 vector_in = {2'b01,tag_count,data_test}; // read such tag entry
end // end repeat loop
#2 vector_in = 26'b00_00110001_0000000000000001; // flashes entire cache
// reads entire cache to confirm that has been flashed
tag_count = {TAG_WIDTH{1'b0}};
data_test = {DATA_WIDTH{1'b1}};
repeat(8)begin: bench4
#2 vector_in = {`READ,tag_count,data_test}; // read a new tag entry every time
// #2 vector_in = {2'b01,tag_count,data_test}; // read such tag entry
tag_count = tag_count + 1'b1;
data_test = data_test + 1'b1;
end // end repeat loop
end
always begin
#1 clk = ~clk; // Toggle clock every 1 ticks
end
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_7x_v1_11_0_pcie_7x.v
// Version : 1.11
//
// Description: Solution wrapper for Virtex7 Hard Block for PCI Express
//
//
//
//--------------------------------------------------------------------------------
`ifndef PCIE_2LM
`timescale 1ps/1ps
module pcie_7x_v1_11_0_pcie_7x # (
// PCIE_2_1 params
parameter [11:0] AER_BASE_PTR = 12'h140,
parameter AER_CAP_ECRC_CHECK_CAPABLE = "FALSE",
parameter AER_CAP_ECRC_GEN_CAPABLE = "FALSE",
parameter [15:0] AER_CAP_ID = 16'h0001,
parameter AER_CAP_MULTIHEADER = "FALSE",
parameter [11:0] AER_CAP_NEXTPTR = 12'h178,
parameter AER_CAP_ON = "FALSE",
parameter [23:0] AER_CAP_OPTIONAL_ERR_SUPPORT = 24'h000000,
parameter AER_CAP_PERMIT_ROOTERR_UPDATE = "TRUE",
parameter [3:0] AER_CAP_VERSION = 4'h1,
parameter ALLOW_X8_GEN2 = "FALSE",
parameter [31:0] BAR0 = 32'hFFFFFF00,
parameter [31:0] BAR1 = 32'hFFFF0000,
parameter [31:0] BAR2 = 32'hFFFF000C,
parameter [31:0] BAR3 = 32'hFFFFFFFF,
parameter [31:0] BAR4 = 32'h00000000,
parameter [31:0] BAR5 = 32'h00000000,
parameter [7:0] CAPABILITIES_PTR = 8'h40,
parameter [31:0] CARDBUS_CIS_POINTER = 32'h00000000,
parameter CFG_ECRC_ERR_CPLSTAT = 0,
parameter [23:0] CLASS_CODE = 24'h000000,
parameter CMD_INTX_IMPLEMENTED = "TRUE",
parameter CPL_TIMEOUT_DISABLE_SUPPORTED = "FALSE",
parameter [3:0] CPL_TIMEOUT_RANGES_SUPPORTED = 4'h0,
parameter [6:0] CRM_MODULE_RSTS = 7'h00,
parameter C_DATA_WIDTH = 64,
parameter REM_WIDTH = (C_DATA_WIDTH == 128) ? 2 : 1,
parameter KEEP_WIDTH = C_DATA_WIDTH / 8,
parameter DEV_CAP2_ARI_FORWARDING_SUPPORTED = "FALSE",
parameter DEV_CAP2_ATOMICOP32_COMPLETER_SUPPORTED = "FALSE",
parameter DEV_CAP2_ATOMICOP64_COMPLETER_SUPPORTED = "FALSE",
parameter DEV_CAP2_ATOMICOP_ROUTING_SUPPORTED = "FALSE",
parameter DEV_CAP2_CAS128_COMPLETER_SUPPORTED = "FALSE",
parameter DEV_CAP2_ENDEND_TLP_PREFIX_SUPPORTED = "FALSE",
parameter DEV_CAP2_EXTENDED_FMT_FIELD_SUPPORTED = "FALSE",
parameter DEV_CAP2_LTR_MECHANISM_SUPPORTED = "FALSE",
parameter [1:0] DEV_CAP2_MAX_ENDEND_TLP_PREFIXES = 2'h0,
parameter DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING = "FALSE",
parameter [1:0] DEV_CAP2_TPH_COMPLETER_SUPPORTED = 2'h0,
parameter DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE = "TRUE",
parameter DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE = "TRUE",
parameter integer DEV_CAP_ENDPOINT_L0S_LATENCY = 0,
parameter integer DEV_CAP_ENDPOINT_L1_LATENCY = 0,
parameter DEV_CAP_EXT_TAG_SUPPORTED = "TRUE",
parameter DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE = "FALSE",
parameter integer DEV_CAP_MAX_PAYLOAD_SUPPORTED = 2,
parameter integer DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT = 0,
parameter DEV_CAP_ROLE_BASED_ERROR = "TRUE",
parameter integer DEV_CAP_RSVD_14_12 = 0,
parameter integer DEV_CAP_RSVD_17_16 = 0,
parameter integer DEV_CAP_RSVD_31_29 = 0,
parameter DEV_CONTROL_AUX_POWER_SUPPORTED = "FALSE",
parameter DEV_CONTROL_EXT_TAG_DEFAULT = "FALSE",
parameter DISABLE_ASPM_L1_TIMER = "FALSE",
parameter DISABLE_BAR_FILTERING = "FALSE",
parameter DISABLE_ERR_MSG = "FALSE",
parameter DISABLE_ID_CHECK = "FALSE",
parameter DISABLE_LANE_REVERSAL = "FALSE",
parameter DISABLE_LOCKED_FILTER = "FALSE",
parameter DISABLE_PPM_FILTER = "FALSE",
parameter DISABLE_RX_POISONED_RESP = "FALSE",
parameter DISABLE_RX_TC_FILTER = "FALSE",
parameter DISABLE_SCRAMBLING = "FALSE",
parameter [7:0] DNSTREAM_LINK_NUM = 8'h00,
parameter [11:0] DSN_BASE_PTR = 12'h100,
parameter [15:0] DSN_CAP_ID = 16'h0003,
parameter [11:0] DSN_CAP_NEXTPTR = 12'h10C,
parameter DSN_CAP_ON = "TRUE",
parameter [3:0] DSN_CAP_VERSION = 4'h1,
parameter [10:0] ENABLE_MSG_ROUTE = 11'h000,
parameter ENABLE_RX_TD_ECRC_TRIM = "FALSE",
parameter ENDEND_TLP_PREFIX_FORWARDING_SUPPORTED = "FALSE",
parameter ENTER_RVRY_EI_L0 = "TRUE",
parameter EXIT_LOOPBACK_ON_EI = "TRUE",
parameter [31:0] EXPANSION_ROM = 32'hFFFFF001,
parameter [5:0] EXT_CFG_CAP_PTR = 6'h3F,
parameter [9:0] EXT_CFG_XP_CAP_PTR = 10'h3FF,
parameter [7:0] HEADER_TYPE = 8'h00,
parameter [4:0] INFER_EI = 5'h00,
parameter [7:0] INTERRUPT_PIN = 8'h01,
parameter INTERRUPT_STAT_AUTO = "TRUE",
parameter IS_SWITCH = "FALSE",
parameter [9:0] LAST_CONFIG_DWORD = 10'h3FF,
parameter LINK_CAP_ASPM_OPTIONALITY = "TRUE",
parameter integer LINK_CAP_ASPM_SUPPORT = 1,
parameter LINK_CAP_CLOCK_POWER_MANAGEMENT = "FALSE",
parameter LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP = "FALSE",
parameter integer LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 = 7,
parameter integer LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 = 7,
parameter integer LINK_CAP_L0S_EXIT_LATENCY_GEN1 = 7,
parameter integer LINK_CAP_L0S_EXIT_LATENCY_GEN2 = 7,
parameter integer LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 = 7,
parameter integer LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 = 7,
parameter integer LINK_CAP_L1_EXIT_LATENCY_GEN1 = 7,
parameter integer LINK_CAP_L1_EXIT_LATENCY_GEN2 = 7,
parameter LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP = "FALSE",
parameter [3:0] LINK_CAP_MAX_LINK_SPEED = 4'h1,
parameter [5:0] LINK_CAP_MAX_LINK_WIDTH = 6'h08,
parameter integer LINK_CAP_RSVD_23 = 0,
parameter LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE = "FALSE",
parameter integer LINK_CONTROL_RCB = 0,
parameter LINK_CTRL2_DEEMPHASIS = "FALSE",
parameter LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE = "FALSE",
parameter [3:0] LINK_CTRL2_TARGET_LINK_SPEED = 4'h2,
parameter LINK_STATUS_SLOT_CLOCK_CONFIG = "TRUE",
parameter [14:0] LL_ACK_TIMEOUT = 15'h0000,
parameter LL_ACK_TIMEOUT_EN = "FALSE",
parameter integer LL_ACK_TIMEOUT_FUNC = 0,
parameter [14:0] LL_REPLAY_TIMEOUT = 15'h0000,
parameter LL_REPLAY_TIMEOUT_EN = "FALSE",
parameter integer LL_REPLAY_TIMEOUT_FUNC = 0,
parameter [5:0] LTSSM_MAX_LINK_WIDTH = 6'h01,
parameter MPS_FORCE = "FALSE",
parameter [7:0] MSIX_BASE_PTR = 8'h9C,
parameter [7:0] MSIX_CAP_ID = 8'h11,
parameter [7:0] MSIX_CAP_NEXTPTR = 8'h00,
parameter MSIX_CAP_ON = "FALSE",
parameter integer MSIX_CAP_PBA_BIR = 0,
parameter [28:0] MSIX_CAP_PBA_OFFSET = 29'h00000050,
parameter integer MSIX_CAP_TABLE_BIR = 0,
parameter [28:0] MSIX_CAP_TABLE_OFFSET = 29'h00000040,
parameter [10:0] MSIX_CAP_TABLE_SIZE = 11'h000,
parameter [7:0] MSI_BASE_PTR = 8'h48,
parameter MSI_CAP_64_BIT_ADDR_CAPABLE = "TRUE",
parameter [7:0] MSI_CAP_ID = 8'h05,
parameter integer MSI_CAP_MULTIMSGCAP = 0,
parameter integer MSI_CAP_MULTIMSG_EXTENSION = 0,
parameter [7:0] MSI_CAP_NEXTPTR = 8'h60,
parameter MSI_CAP_ON = "FALSE",
parameter MSI_CAP_PER_VECTOR_MASKING_CAPABLE = "TRUE",
parameter integer N_FTS_COMCLK_GEN1 = 255,
parameter integer N_FTS_COMCLK_GEN2 = 255,
parameter integer N_FTS_GEN1 = 255,
parameter integer N_FTS_GEN2 = 255,
parameter [7:0] PCIE_BASE_PTR = 8'h60,
parameter [7:0] PCIE_CAP_CAPABILITY_ID = 8'h10,
parameter [3:0] PCIE_CAP_CAPABILITY_VERSION = 4'h2,
parameter [3:0] PCIE_CAP_DEVICE_PORT_TYPE = 4'h0,
parameter [7:0] PCIE_CAP_NEXTPTR = 8'h9C,
parameter PCIE_CAP_ON = "TRUE",
parameter integer PCIE_CAP_RSVD_15_14 = 0,
parameter PCIE_CAP_SLOT_IMPLEMENTED = "FALSE",
parameter integer PCIE_REVISION = 2,
parameter integer PL_AUTO_CONFIG = 0,
parameter PL_FAST_TRAIN = "FALSE",
parameter [14:0] PM_ASPML0S_TIMEOUT = 15'h0000,
parameter PM_ASPML0S_TIMEOUT_EN = "FALSE",
parameter integer PM_ASPML0S_TIMEOUT_FUNC = 0,
parameter PM_ASPM_FASTEXIT = "FALSE",
parameter [7:0] PM_BASE_PTR = 8'h40,
parameter integer PM_CAP_AUXCURRENT = 0,
parameter PM_CAP_D1SUPPORT = "TRUE",
parameter PM_CAP_D2SUPPORT = "TRUE",
parameter PM_CAP_DSI = "FALSE",
parameter [7:0] PM_CAP_ID = 8'h01,
parameter [7:0] PM_CAP_NEXTPTR = 8'h48,
parameter PM_CAP_ON = "TRUE",
parameter [4:0] PM_CAP_PMESUPPORT = 5'h0F,
parameter PM_CAP_PME_CLOCK = "FALSE",
parameter integer PM_CAP_RSVD_04 = 0,
parameter integer PM_CAP_VERSION = 3,
parameter PM_CSR_B2B3 = "FALSE",
parameter PM_CSR_BPCCEN = "FALSE",
parameter PM_CSR_NOSOFTRST = "TRUE",
parameter [7:0] PM_DATA0 = 8'h01,
parameter [7:0] PM_DATA1 = 8'h01,
parameter [7:0] PM_DATA2 = 8'h01,
parameter [7:0] PM_DATA3 = 8'h01,
parameter [7:0] PM_DATA4 = 8'h01,
parameter [7:0] PM_DATA5 = 8'h01,
parameter [7:0] PM_DATA6 = 8'h01,
parameter [7:0] PM_DATA7 = 8'h01,
parameter [1:0] PM_DATA_SCALE0 = 2'h1,
parameter [1:0] PM_DATA_SCALE1 = 2'h1,
parameter [1:0] PM_DATA_SCALE2 = 2'h1,
parameter [1:0] PM_DATA_SCALE3 = 2'h1,
parameter [1:0] PM_DATA_SCALE4 = 2'h1,
parameter [1:0] PM_DATA_SCALE5 = 2'h1,
parameter [1:0] PM_DATA_SCALE6 = 2'h1,
parameter [1:0] PM_DATA_SCALE7 = 2'h1,
parameter PM_MF = "FALSE",
parameter [11:0] RBAR_BASE_PTR = 12'h178,
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR0 = 5'h00,
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR1 = 5'h00,
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR2 = 5'h00,
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR3 = 5'h00,
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR4 = 5'h00,
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR5 = 5'h00,
parameter [15:0] RBAR_CAP_ID = 16'h0015,
parameter [2:0] RBAR_CAP_INDEX0 = 3'h0,
parameter [2:0] RBAR_CAP_INDEX1 = 3'h0,
parameter [2:0] RBAR_CAP_INDEX2 = 3'h0,
parameter [2:0] RBAR_CAP_INDEX3 = 3'h0,
parameter [2:0] RBAR_CAP_INDEX4 = 3'h0,
parameter [2:0] RBAR_CAP_INDEX5 = 3'h0,
parameter [11:0] RBAR_CAP_NEXTPTR = 12'h000,
parameter RBAR_CAP_ON = "FALSE",
parameter [31:0] RBAR_CAP_SUP0 = 32'h00000000,
parameter [31:0] RBAR_CAP_SUP1 = 32'h00000000,
parameter [31:0] RBAR_CAP_SUP2 = 32'h00000000,
parameter [31:0] RBAR_CAP_SUP3 = 32'h00000000,
parameter [31:0] RBAR_CAP_SUP4 = 32'h00000000,
parameter [31:0] RBAR_CAP_SUP5 = 32'h00000000,
parameter [3:0] RBAR_CAP_VERSION = 4'h1,
parameter [2:0] RBAR_NUM = 3'h1,
parameter integer RECRC_CHK = 0,
parameter RECRC_CHK_TRIM = "FALSE",
parameter ROOT_CAP_CRS_SW_VISIBILITY = "FALSE",
parameter [1:0] RP_AUTO_SPD = 2'h1,
parameter [4:0] RP_AUTO_SPD_LOOPCNT = 5'h1f,
parameter SELECT_DLL_IF = "FALSE",
parameter SIM_VERSION = "1.0",
parameter SLOT_CAP_ATT_BUTTON_PRESENT = "FALSE",
parameter SLOT_CAP_ATT_INDICATOR_PRESENT = "FALSE",
parameter SLOT_CAP_ELEC_INTERLOCK_PRESENT = "FALSE",
parameter SLOT_CAP_HOTPLUG_CAPABLE = "FALSE",
parameter SLOT_CAP_HOTPLUG_SURPRISE = "FALSE",
parameter SLOT_CAP_MRL_SENSOR_PRESENT = "FALSE",
parameter SLOT_CAP_NO_CMD_COMPLETED_SUPPORT = "FALSE",
parameter [12:0] SLOT_CAP_PHYSICAL_SLOT_NUM = 13'h0000,
parameter SLOT_CAP_POWER_CONTROLLER_PRESENT = "FALSE",
parameter SLOT_CAP_POWER_INDICATOR_PRESENT = "FALSE",
parameter integer SLOT_CAP_SLOT_POWER_LIMIT_SCALE = 0,
parameter [7:0] SLOT_CAP_SLOT_POWER_LIMIT_VALUE = 8'h00,
parameter integer SPARE_BIT0 = 0,
parameter integer SPARE_BIT1 = 0,
parameter integer SPARE_BIT2 = 0,
parameter integer SPARE_BIT3 = 0,
parameter integer SPARE_BIT4 = 0,
parameter integer SPARE_BIT5 = 0,
parameter integer SPARE_BIT6 = 0,
parameter integer SPARE_BIT7 = 0,
parameter integer SPARE_BIT8 = 0,
parameter [7:0] SPARE_BYTE0 = 8'h00,
parameter [7:0] SPARE_BYTE1 = 8'h00,
parameter [7:0] SPARE_BYTE2 = 8'h00,
parameter [7:0] SPARE_BYTE3 = 8'h00,
parameter [31:0] SPARE_WORD0 = 32'h00000000,
parameter [31:0] SPARE_WORD1 = 32'h00000000,
parameter [31:0] SPARE_WORD2 = 32'h00000000,
parameter [31:0] SPARE_WORD3 = 32'h00000000,
parameter SSL_MESSAGE_AUTO = "FALSE",
parameter TECRC_EP_INV = "FALSE",
parameter TL_RBYPASS = "FALSE",
parameter integer TL_RX_RAM_RADDR_LATENCY = 0,
parameter integer TL_RX_RAM_RDATA_LATENCY = 2,
parameter integer TL_RX_RAM_WRITE_LATENCY = 0,
parameter TL_TFC_DISABLE = "FALSE",
parameter TL_TX_CHECKS_DISABLE = "FALSE",
parameter integer TL_TX_RAM_RADDR_LATENCY = 0,
parameter integer TL_TX_RAM_RDATA_LATENCY = 2,
parameter integer TL_TX_RAM_WRITE_LATENCY = 0,
parameter TRN_DW = "FALSE",
parameter TRN_NP_FC = "FALSE",
parameter UPCONFIG_CAPABLE = "TRUE",
parameter UPSTREAM_FACING = "TRUE",
parameter UR_ATOMIC = "TRUE",
parameter UR_CFG1 = "TRUE",
parameter UR_INV_REQ = "TRUE",
parameter UR_PRS_RESPONSE = "TRUE",
parameter USER_CLK2_DIV2 = "FALSE",
parameter integer USER_CLK_FREQ = 3,
parameter USE_RID_PINS = "FALSE",
parameter VC0_CPL_INFINITE = "TRUE",
parameter [12:0] VC0_RX_RAM_LIMIT = 13'h03FF,
parameter integer VC0_TOTAL_CREDITS_CD = 127,
parameter integer VC0_TOTAL_CREDITS_CH = 31,
parameter integer VC0_TOTAL_CREDITS_NPD = 24,
parameter integer VC0_TOTAL_CREDITS_NPH = 12,
parameter integer VC0_TOTAL_CREDITS_PD = 288,
parameter integer VC0_TOTAL_CREDITS_PH = 32,
parameter integer VC0_TX_LASTPACKET = 31,
parameter [11:0] VC_BASE_PTR = 12'h10C,
parameter [15:0] VC_CAP_ID = 16'h0002,
parameter [11:0] VC_CAP_NEXTPTR = 12'h000,
parameter VC_CAP_ON = "FALSE",
parameter VC_CAP_REJECT_SNOOP_TRANSACTIONS = "FALSE",
parameter [3:0] VC_CAP_VERSION = 4'h1,
parameter [11:0] VSEC_BASE_PTR = 12'h128,
parameter [15:0] VSEC_CAP_HDR_ID = 16'h1234,
parameter [11:0] VSEC_CAP_HDR_LENGTH = 12'h018,
parameter [3:0] VSEC_CAP_HDR_REVISION = 4'h1,
parameter [15:0] VSEC_CAP_ID = 16'h000B,
parameter VSEC_CAP_IS_LINK_VISIBLE = "TRUE",
parameter [11:0] VSEC_CAP_NEXTPTR = 12'h140,
parameter VSEC_CAP_ON = "FALSE",
parameter [3:0] VSEC_CAP_VERSION = 4'h1
)
(
input wire [C_DATA_WIDTH-1:0] trn_td,
input wire [REM_WIDTH-1:0] trn_trem,
input wire trn_tsof,
input wire trn_teof,
input wire trn_tsrc_rdy,
input wire trn_tsrc_dsc,
input wire trn_terrfwd,
input wire trn_tecrc_gen,
input wire trn_tstr,
input wire trn_tcfg_gnt,
input wire trn_rdst_rdy,
input wire trn_rnp_req,
input wire trn_rfcp_ret,
input wire trn_rnp_ok,
input wire [2:0] trn_fc_sel,
input wire [31:0] trn_tdllp_data,
input wire trn_tdllp_src_rdy,
input wire ll2_tlp_rcv,
input wire ll2_send_enter_l1,
input wire ll2_send_enter_l23,
input wire ll2_send_as_req_l1,
input wire ll2_send_pm_ack,
input wire [4:0] pl2_directed_lstate,
input wire ll2_suspend_now,
input wire tl2_ppm_suspend_req,
input wire tl2_aspm_suspend_credit_check,
input wire [1:0] pl_directed_link_change,
input wire [1:0] pl_directed_link_width,
input wire pl_directed_link_speed,
input wire pl_directed_link_auton,
input wire pl_upstream_prefer_deemph,
input wire pl_downstream_deemph_source,
input wire pl_directed_ltssm_new_vld,
input wire [5:0] pl_directed_ltssm_new,
input wire pl_directed_ltssm_stall,
input wire [1:0] pipe_rx0_char_is_k,
input wire [1:0] pipe_rx1_char_is_k,
input wire [1:0] pipe_rx2_char_is_k,
input wire [1:0] pipe_rx3_char_is_k,
input wire [1:0] pipe_rx4_char_is_k,
input wire [1:0] pipe_rx5_char_is_k,
input wire [1:0] pipe_rx6_char_is_k,
input wire [1:0] pipe_rx7_char_is_k,
input wire pipe_rx0_valid,
input wire pipe_rx1_valid,
input wire pipe_rx2_valid,
input wire pipe_rx3_valid,
input wire pipe_rx4_valid,
input wire pipe_rx5_valid,
input wire pipe_rx6_valid,
input wire pipe_rx7_valid,
input wire [15:0] pipe_rx0_data,
input wire [15:0] pipe_rx1_data,
input wire [15:0] pipe_rx2_data,
input wire [15:0] pipe_rx3_data,
input wire [15:0] pipe_rx4_data,
input wire [15:0] pipe_rx5_data,
input wire [15:0] pipe_rx6_data,
input wire [15:0] pipe_rx7_data,
input wire pipe_rx0_chanisaligned,
input wire pipe_rx1_chanisaligned,
input wire pipe_rx2_chanisaligned,
input wire pipe_rx3_chanisaligned,
input wire pipe_rx4_chanisaligned,
input wire pipe_rx5_chanisaligned,
input wire pipe_rx6_chanisaligned,
input wire pipe_rx7_chanisaligned,
input wire [2:0] pipe_rx0_status,
input wire [2:0] pipe_rx1_status,
input wire [2:0] pipe_rx2_status,
input wire [2:0] pipe_rx3_status,
input wire [2:0] pipe_rx4_status,
input wire [2:0] pipe_rx5_status,
input wire [2:0] pipe_rx6_status,
input wire [2:0] pipe_rx7_status,
input wire pipe_rx0_phy_status,
input wire pipe_rx1_phy_status,
input wire pipe_rx2_phy_status,
input wire pipe_rx3_phy_status,
input wire pipe_rx4_phy_status,
input wire pipe_rx5_phy_status,
input wire pipe_rx6_phy_status,
input wire pipe_rx7_phy_status,
input wire pipe_rx0_elec_idle,
input wire pipe_rx1_elec_idle,
input wire pipe_rx2_elec_idle,
input wire pipe_rx3_elec_idle,
input wire pipe_rx4_elec_idle,
input wire pipe_rx5_elec_idle,
input wire pipe_rx6_elec_idle,
input wire pipe_rx7_elec_idle,
input wire pipe_clk,
input wire user_clk,
input wire user_clk2,
input wire user_clk_prebuf,
input wire user_clk_prebuf_en,
`ifdef B_TESTMODE
input wire scanmode_n,
input wire scanenable_n,
input wire edt_clk,
input wire edt_bypass,
input wire edt_update,
input wire edt_configuration,
input wire edt_single_bypass_chain,
input wire edt_channels_in1,
input wire edt_channels_in2,
input wire edt_channels_in3,
input wire edt_channels_in4,
input wire edt_channels_in5,
input wire edt_channels_in6,
input wire edt_channels_in7,
input wire edt_channels_in8,
input wire pmv_enable_n,
input wire [2:0] pmv_select,
input wire [1:0] pmv_divide,
`endif
input wire sys_rst_n,
input wire cm_rst_n,
input wire cm_sticky_rst_n,
input wire func_lvl_rst_n,
input wire tl_rst_n,
input wire dl_rst_n,
input wire pl_rst_n,
input wire pl_transmit_hot_rst,
// input wire cfg_reset,
// input wire gwe,
// input wire grestore,
// input wire ghigh,
input wire [31:0] cfg_mgmt_di,
input wire [3:0] cfg_mgmt_byte_en_n,
input wire [9:0] cfg_mgmt_dwaddr,
input wire cfg_mgmt_wr_rw1c_as_rw_n,
input wire cfg_mgmt_wr_readonly_n,
input wire cfg_mgmt_wr_en_n,
input wire cfg_mgmt_rd_en_n,
input wire cfg_err_malformed_n,
input wire cfg_err_cor_n,
input wire cfg_err_ur_n,
input wire cfg_err_ecrc_n,
input wire cfg_err_cpl_timeout_n,
input wire cfg_err_cpl_abort_n,
input wire cfg_err_cpl_unexpect_n,
input wire cfg_err_poisoned_n,
input wire cfg_err_acs_n,
input wire cfg_err_atomic_egress_blocked_n,
input wire cfg_err_mc_blocked_n,
input wire cfg_err_internal_uncor_n,
input wire cfg_err_internal_cor_n,
input wire cfg_err_posted_n,
input wire cfg_err_locked_n,
input wire cfg_err_norecovery_n,
input wire [127:0] cfg_err_aer_headerlog,
input wire [47:0] cfg_err_tlp_cpl_header,
input wire cfg_interrupt_n,
input wire [7:0] cfg_interrupt_di,
input wire cfg_interrupt_assert_n,
input wire cfg_interrupt_stat_n,
input wire [7:0] cfg_ds_bus_number,
input wire [4:0] cfg_ds_device_number,
input wire [2:0] cfg_ds_function_number,
input wire [7:0] cfg_port_number,
input wire cfg_pm_halt_aspm_l0s_n,
input wire cfg_pm_halt_aspm_l1_n,
input wire cfg_pm_force_state_en_n,
input wire [1:0] cfg_pm_force_state,
input wire cfg_pm_wake_n,
input wire cfg_pm_turnoff_ok_n,
input wire cfg_pm_send_pme_to_n,
input wire [4:0] cfg_pciecap_interrupt_msgnum,
input wire cfg_trn_pending_n,
input wire [2:0] cfg_force_mps,
input wire cfg_force_common_clock_off,
input wire cfg_force_extended_sync_on,
input wire [63:0] cfg_dsn,
input wire [4:0] cfg_aer_interrupt_msgnum,
input wire [15:0] cfg_dev_id,
input wire [15:0] cfg_vend_id,
input wire [7:0] cfg_rev_id,
input wire [15:0] cfg_subsys_id,
input wire [15:0] cfg_subsys_vend_id,
input wire drp_clk,
input wire drp_en,
input wire drp_we,
input wire [8:0] drp_addr,
input wire [15:0] drp_di,
input wire [1:0] dbg_mode,
input wire dbg_sub_mode,
input wire [2:0] pl_dbg_mode,
output wire trn_clk,
output wire trn_tdst_rdy,
output wire trn_terr_drop,
output wire [5:0] trn_tbuf_av,
output wire trn_tcfg_req,
output wire [C_DATA_WIDTH-1:0] trn_rd,
output wire [REM_WIDTH-1:0] trn_rrem,
output wire trn_rsof,
output wire trn_reof,
output wire trn_rsrc_rdy,
output wire trn_rsrc_dsc,
output wire trn_recrc_err,
output wire trn_rerrfwd,
output wire [7:0] trn_rbar_hit,
output wire trn_lnk_up,
output wire [7:0] trn_fc_ph,
output wire [11:0] trn_fc_pd,
output wire [7:0] trn_fc_nph,
output wire [11:0] trn_fc_npd,
output wire [7:0] trn_fc_cplh,
output wire [11:0] trn_fc_cpld,
output wire trn_tdllp_dst_rdy,
output wire [63:0] trn_rdllp_data,
output wire [1:0] trn_rdllp_src_rdy,
output wire ll2_tfc_init1_seq,
output wire ll2_tfc_init2_seq,
output wire pl2_suspend_ok,
output wire pl2_recovery,
output wire pl2_rx_elec_idle,
output wire [1:0] pl2_rx_pm_state,
output wire pl2_l0_req,
output wire ll2_suspend_ok,
output wire ll2_tx_idle,
output wire [4:0] ll2_link_status,
output wire tl2_ppm_suspend_ok,
output wire tl2_aspm_suspend_req,
output wire tl2_aspm_suspend_credit_check_ok,
output wire pl2_link_up,
output wire pl2_receiver_err,
output wire ll2_receiver_err,
output wire ll2_protocol_err,
output wire ll2_bad_tlp_err,
output wire ll2_bad_dllp_err,
output wire ll2_replay_ro_err,
output wire ll2_replay_to_err,
output wire [63:0] tl2_err_hdr,
output wire tl2_err_malformed,
output wire tl2_err_rxoverflow,
output wire tl2_err_fcpe,
output wire pl_sel_lnk_rate,
output wire [1:0] pl_sel_lnk_width,
output wire [5:0] pl_ltssm_state,
output wire [1:0] pl_lane_reversal_mode,
output wire pl_phy_lnk_up_n,
output wire [2:0] pl_tx_pm_state,
output wire [1:0] pl_rx_pm_state,
output wire pl_link_upcfg_cap,
output wire pl_link_gen2_cap,
output wire pl_link_partner_gen2_supported,
output wire [2:0] pl_initial_link_width,
output wire pl_directed_change_done,
output wire pipe_tx_rcvr_det,
output wire pipe_tx_reset,
output wire pipe_tx_rate,
output wire pipe_tx_deemph,
output wire [2:0] pipe_tx_margin,
output wire pipe_rx0_polarity,
output wire pipe_rx1_polarity,
output wire pipe_rx2_polarity,
output wire pipe_rx3_polarity,
output wire pipe_rx4_polarity,
output wire pipe_rx5_polarity,
output wire pipe_rx6_polarity,
output wire pipe_rx7_polarity,
output wire pipe_tx0_compliance,
output wire pipe_tx1_compliance,
output wire pipe_tx2_compliance,
output wire pipe_tx3_compliance,
output wire pipe_tx4_compliance,
output wire pipe_tx5_compliance,
output wire pipe_tx6_compliance,
output wire pipe_tx7_compliance,
output wire [1:0] pipe_tx0_char_is_k,
output wire [1:0] pipe_tx1_char_is_k,
output wire [1:0] pipe_tx2_char_is_k,
output wire [1:0] pipe_tx3_char_is_k,
output wire [1:0] pipe_tx4_char_is_k,
output wire [1:0] pipe_tx5_char_is_k,
output wire [1:0] pipe_tx6_char_is_k,
output wire [1:0] pipe_tx7_char_is_k,
output wire [15:0] pipe_tx0_data,
output wire [15:0] pipe_tx1_data,
output wire [15:0] pipe_tx2_data,
output wire [15:0] pipe_tx3_data,
output wire [15:0] pipe_tx4_data,
output wire [15:0] pipe_tx5_data,
output wire [15:0] pipe_tx6_data,
output wire [15:0] pipe_tx7_data,
output wire pipe_tx0_elec_idle,
output wire pipe_tx1_elec_idle,
output wire pipe_tx2_elec_idle,
output wire pipe_tx3_elec_idle,
output wire pipe_tx4_elec_idle,
output wire pipe_tx5_elec_idle,
output wire pipe_tx6_elec_idle,
output wire pipe_tx7_elec_idle,
output wire [1:0] pipe_tx0_powerdown,
output wire [1:0] pipe_tx1_powerdown,
output wire [1:0] pipe_tx2_powerdown,
output wire [1:0] pipe_tx3_powerdown,
output wire [1:0] pipe_tx4_powerdown,
output wire [1:0] pipe_tx5_powerdown,
output wire [1:0] pipe_tx6_powerdown,
output wire [1:0] pipe_tx7_powerdown,
`ifdef B_TESTMODE
output wire pmv_out,
`endif
output wire user_rst_n,
output wire pl_received_hot_rst,
output wire received_func_lvl_rst_n,
output wire lnk_clk_en,
output wire [31:0] cfg_mgmt_do,
output wire cfg_mgmt_rd_wr_done_n,
output wire cfg_err_aer_headerlog_set_n,
output wire cfg_err_cpl_rdy_n,
output wire cfg_interrupt_rdy_n,
output wire [2:0] cfg_interrupt_mmenable,
output wire cfg_interrupt_msienable,
output wire [7:0] cfg_interrupt_do,
output wire cfg_interrupt_msixenable,
output wire cfg_interrupt_msixfm,
output wire cfg_msg_received,
output wire [15:0] cfg_msg_data,
output wire cfg_msg_received_err_cor,
output wire cfg_msg_received_err_non_fatal,
output wire cfg_msg_received_err_fatal,
output wire cfg_msg_received_assert_int_a,
output wire cfg_msg_received_deassert_int_a,
output wire cfg_msg_received_assert_int_b,
output wire cfg_msg_received_deassert_int_b,
output wire cfg_msg_received_assert_int_c,
output wire cfg_msg_received_deassert_int_c,
output wire cfg_msg_received_assert_int_d,
output wire cfg_msg_received_deassert_int_d,
output wire cfg_msg_received_pm_pme,
output wire cfg_msg_received_pme_to_ack,
output wire cfg_msg_received_pme_to,
output wire cfg_msg_received_setslotpowerlimit,
output wire cfg_msg_received_unlock,
output wire cfg_msg_received_pm_as_nak,
output wire [2:0] cfg_pcie_link_state,
output wire cfg_pm_rcv_as_req_l1_n,
output wire cfg_pm_rcv_enter_l1_n,
output wire cfg_pm_rcv_enter_l23_n,
output wire cfg_pm_rcv_req_ack_n,
output wire [1:0] cfg_pmcsr_powerstate,
output wire cfg_pmcsr_pme_en,
output wire cfg_pmcsr_pme_status,
output wire cfg_transaction,
output wire cfg_transaction_type,
output wire [6:0] cfg_transaction_addr,
output wire cfg_command_io_enable,
output wire cfg_command_mem_enable,
output wire cfg_command_bus_master_enable,
output wire cfg_command_interrupt_disable,
output wire cfg_command_serr_en,
output wire cfg_bridge_serr_en,
output wire cfg_dev_status_corr_err_detected,
output wire cfg_dev_status_non_fatal_err_detected,
output wire cfg_dev_status_fatal_err_detected,
output wire cfg_dev_status_ur_detected,
output wire cfg_dev_control_corr_err_reporting_en,
output wire cfg_dev_control_non_fatal_reporting_en,
output wire cfg_dev_control_fatal_err_reporting_en,
output wire cfg_dev_control_ur_err_reporting_en,
output wire cfg_dev_control_enable_ro,
output wire [2:0] cfg_dev_control_max_payload,
output wire cfg_dev_control_ext_tag_en,
output wire cfg_dev_control_phantom_en,
output wire cfg_dev_control_aux_power_en,
output wire cfg_dev_control_no_snoop_en,
output wire [2:0] cfg_dev_control_max_read_req,
output wire [1:0] cfg_link_status_current_speed,
output wire [3:0] cfg_link_status_negotiated_width,
output wire cfg_link_status_link_training,
output wire cfg_link_status_dll_active,
output wire cfg_link_status_bandwidth_status,
output wire cfg_link_status_auto_bandwidth_status,
output wire [1:0] cfg_link_control_aspm_control,
output wire cfg_link_control_rcb,
output wire cfg_link_control_link_disable,
output wire cfg_link_control_retrain_link,
output wire cfg_link_control_common_clock,
output wire cfg_link_control_extended_sync,
output wire cfg_link_control_clock_pm_en,
output wire cfg_link_control_hw_auto_width_dis,
output wire cfg_link_control_bandwidth_int_en,
output wire cfg_link_control_auto_bandwidth_int_en,
output wire [3:0] cfg_dev_control2_cpl_timeout_val,
output wire cfg_dev_control2_cpl_timeout_dis,
output wire cfg_dev_control2_ari_forward_en,
output wire cfg_dev_control2_atomic_requester_en,
output wire cfg_dev_control2_atomic_egress_block,
output wire cfg_dev_control2_ido_req_en,
output wire cfg_dev_control2_ido_cpl_en,
output wire cfg_dev_control2_ltr_en,
output wire cfg_dev_control2_tlp_prefix_block,
output wire cfg_slot_control_electromech_il_ctl_pulse,
output wire cfg_root_control_syserr_corr_err_en,
output wire cfg_root_control_syserr_non_fatal_err_en,
output wire cfg_root_control_syserr_fatal_err_en,
output wire cfg_root_control_pme_int_en,
output wire cfg_aer_ecrc_check_en,
output wire cfg_aer_ecrc_gen_en,
output wire cfg_aer_rooterr_corr_err_reporting_en,
output wire cfg_aer_rooterr_non_fatal_err_reporting_en,
output wire cfg_aer_rooterr_fatal_err_reporting_en,
output wire cfg_aer_rooterr_corr_err_received,
output wire cfg_aer_rooterr_non_fatal_err_received,
output wire cfg_aer_rooterr_fatal_err_received,
output wire [6:0] cfg_vc_tcvc_map,
output wire drp_rdy,
output wire [15:0] drp_do,
output wire [63:0] dbg_vec_a,
output wire [63:0] dbg_vec_b,
output wire [11:0] dbg_vec_c,
output wire dbg_sclr_a,
output wire dbg_sclr_b,
output wire dbg_sclr_c,
output wire dbg_sclr_d,
output wire dbg_sclr_e,
output wire dbg_sclr_f,
output wire dbg_sclr_g,
output wire dbg_sclr_h,
output wire dbg_sclr_i,
output wire dbg_sclr_j,
output wire dbg_sclr_k,
output wire [11:0] pl_dbg_vec
// output wire [18:0] xil_unconn_out
);
localparam TCQ = 1;
wire [3:0] trn_tdst_rdy_bus;
wire [(127-C_DATA_WIDTH):0] trn_rd_wire;
wire trn_rrem_wire;
// Assignments to outputs
assign trn_clk = user_clk2;
assign trn_tdst_rdy = trn_tdst_rdy_bus[0];
//----------------------------------------------------------------------//
// BRAM //
//----------------------------------------------------------------------//
// transmit bram interface
wire mim_tx_wen;
wire [12:0] mim_tx_waddr;
wire [68:0] mim_tx_wdata;
wire mim_tx_ren;
wire mim_tx_rce;
wire [12:0] mim_tx_raddr;
wire [68:0] mim_tx_rdata;
wire [2:0] unused_mim_tx_rdata;
// receive bram interface
wire mim_rx_wen;
wire [12:0] mim_rx_waddr;
wire [67:0] mim_rx_wdata;
wire mim_rx_ren;
wire mim_rx_rce;
wire [12:0] mim_rx_raddr;
wire [67:0] mim_rx_rdata;
wire [3:0] unused_mim_rx_rdata;
pcie_7x_v1_11_0_pcie_bram_top_7x #(
.LINK_CAP_MAX_LINK_SPEED ( LINK_CAP_MAX_LINK_SPEED ),
.LINK_CAP_MAX_LINK_WIDTH ( LINK_CAP_MAX_LINK_WIDTH ),
.DEV_CAP_MAX_PAYLOAD_SUPPORTED ( DEV_CAP_MAX_PAYLOAD_SUPPORTED ),
.VC0_TX_LASTPACKET ( VC0_TX_LASTPACKET ),
.TL_TX_RAM_RADDR_LATENCY ( TL_TX_RAM_RADDR_LATENCY ),
.TL_TX_RAM_RDATA_LATENCY ( TL_TX_RAM_RDATA_LATENCY ),
.TL_TX_RAM_WRITE_LATENCY ( TL_TX_RAM_WRITE_LATENCY ),
.VC0_RX_RAM_LIMIT ( VC0_RX_RAM_LIMIT ),
.TL_RX_RAM_RADDR_LATENCY ( TL_RX_RAM_RADDR_LATENCY ),
.TL_RX_RAM_RDATA_LATENCY ( TL_RX_RAM_RDATA_LATENCY ),
.TL_RX_RAM_WRITE_LATENCY ( TL_RX_RAM_WRITE_LATENCY )
) pcie_bram_top (
.user_clk_i ( user_clk ),
.reset_i ( 1'b0 ),
.mim_tx_waddr ( mim_tx_waddr ),
.mim_tx_wen ( mim_tx_wen ),
.mim_tx_ren ( mim_tx_ren ),
.mim_tx_rce ( 1'b1 ),
.mim_tx_wdata ( {3'b0, mim_tx_wdata} ),
.mim_tx_raddr ( mim_tx_raddr ),
.mim_tx_rdata ( {unused_mim_tx_rdata, mim_tx_rdata} ),
.mim_rx_waddr ( mim_rx_waddr ),
.mim_rx_wen ( mim_rx_wen ),
.mim_rx_ren ( mim_rx_ren ),
.mim_rx_rce ( 1'b1 ),
.mim_rx_wdata ( {4'b0, mim_rx_wdata} ),
.mim_rx_raddr ( mim_rx_raddr ),
.mim_rx_rdata ( {unused_mim_rx_rdata, mim_rx_rdata} )
);
//-------------------------------------------------------
// Virtex7 PCI Express Block Module
//-------------------------------------------------------
PCIE_2_1 #( // Verilog-2001
.AER_BASE_PTR ( AER_BASE_PTR ),
.AER_CAP_ECRC_CHECK_CAPABLE ( AER_CAP_ECRC_CHECK_CAPABLE ),
.AER_CAP_ECRC_GEN_CAPABLE ( AER_CAP_ECRC_GEN_CAPABLE ),
.AER_CAP_ID ( AER_CAP_ID ),
.AER_CAP_MULTIHEADER ( AER_CAP_MULTIHEADER ),
.AER_CAP_NEXTPTR ( AER_CAP_NEXTPTR ),
.AER_CAP_ON ( AER_CAP_ON ),
.AER_CAP_OPTIONAL_ERR_SUPPORT ( AER_CAP_OPTIONAL_ERR_SUPPORT ),
.AER_CAP_PERMIT_ROOTERR_UPDATE ( AER_CAP_PERMIT_ROOTERR_UPDATE ),
.AER_CAP_VERSION ( AER_CAP_VERSION ),
.ALLOW_X8_GEN2 ( ALLOW_X8_GEN2 ),
.BAR0 ( BAR0 ),
.BAR1 ( BAR1 ),
.BAR2 ( BAR2 ),
.BAR3 ( BAR3 ),
.BAR4 ( BAR4 ),
.BAR5 ( BAR5 ),
.CAPABILITIES_PTR ( CAPABILITIES_PTR ),
.CARDBUS_CIS_POINTER ( CARDBUS_CIS_POINTER ),
.CFG_ECRC_ERR_CPLSTAT ( CFG_ECRC_ERR_CPLSTAT ),
.CLASS_CODE ( CLASS_CODE ),
.CMD_INTX_IMPLEMENTED ( CMD_INTX_IMPLEMENTED ),
.CPL_TIMEOUT_DISABLE_SUPPORTED ( CPL_TIMEOUT_DISABLE_SUPPORTED ),
.CPL_TIMEOUT_RANGES_SUPPORTED ( CPL_TIMEOUT_RANGES_SUPPORTED ),
.CRM_MODULE_RSTS ( CRM_MODULE_RSTS ),
.DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE ( DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE ),
.DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE ( DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE ),
.DEV_CAP_ENDPOINT_L0S_LATENCY ( DEV_CAP_ENDPOINT_L0S_LATENCY ),
.DEV_CAP_ENDPOINT_L1_LATENCY ( DEV_CAP_ENDPOINT_L1_LATENCY ),
.DEV_CAP_EXT_TAG_SUPPORTED ( DEV_CAP_EXT_TAG_SUPPORTED ),
.DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE ( DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE ),
.DEV_CAP_MAX_PAYLOAD_SUPPORTED ( DEV_CAP_MAX_PAYLOAD_SUPPORTED ),
.DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT ( DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT ),
.DEV_CAP_ROLE_BASED_ERROR ( DEV_CAP_ROLE_BASED_ERROR ),
.DEV_CAP_RSVD_14_12 ( DEV_CAP_RSVD_14_12 ),
.DEV_CAP_RSVD_17_16 ( DEV_CAP_RSVD_17_16 ),
.DEV_CAP_RSVD_31_29 ( DEV_CAP_RSVD_31_29 ),
.DEV_CAP2_ARI_FORWARDING_SUPPORTED ( DEV_CAP2_ARI_FORWARDING_SUPPORTED ),
.DEV_CAP2_ATOMICOP_ROUTING_SUPPORTED ( DEV_CAP2_ATOMICOP_ROUTING_SUPPORTED ),
.DEV_CAP2_ATOMICOP32_COMPLETER_SUPPORTED ( DEV_CAP2_ATOMICOP32_COMPLETER_SUPPORTED ),
.DEV_CAP2_ATOMICOP64_COMPLETER_SUPPORTED ( DEV_CAP2_ATOMICOP64_COMPLETER_SUPPORTED ),
.DEV_CAP2_CAS128_COMPLETER_SUPPORTED ( DEV_CAP2_CAS128_COMPLETER_SUPPORTED ),
.DEV_CAP2_ENDEND_TLP_PREFIX_SUPPORTED ( DEV_CAP2_ENDEND_TLP_PREFIX_SUPPORTED ),
.DEV_CAP2_EXTENDED_FMT_FIELD_SUPPORTED ( DEV_CAP2_EXTENDED_FMT_FIELD_SUPPORTED ),
.DEV_CAP2_LTR_MECHANISM_SUPPORTED ( DEV_CAP2_LTR_MECHANISM_SUPPORTED ),
.DEV_CAP2_MAX_ENDEND_TLP_PREFIXES ( DEV_CAP2_MAX_ENDEND_TLP_PREFIXES ),
.DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING ( DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING ),
.DEV_CAP2_TPH_COMPLETER_SUPPORTED ( DEV_CAP2_TPH_COMPLETER_SUPPORTED ),
.DEV_CONTROL_AUX_POWER_SUPPORTED ( DEV_CONTROL_AUX_POWER_SUPPORTED ),
.DEV_CONTROL_EXT_TAG_DEFAULT ( DEV_CONTROL_EXT_TAG_DEFAULT ),
.DISABLE_ASPM_L1_TIMER ( DISABLE_ASPM_L1_TIMER ),
.DISABLE_BAR_FILTERING ( DISABLE_BAR_FILTERING ),
.DISABLE_ERR_MSG ( DISABLE_ERR_MSG ),
.DISABLE_ID_CHECK ( DISABLE_ID_CHECK ),
.DISABLE_LANE_REVERSAL ( DISABLE_LANE_REVERSAL ),
.DISABLE_LOCKED_FILTER ( DISABLE_LOCKED_FILTER ),
.DISABLE_PPM_FILTER ( DISABLE_PPM_FILTER ),
.DISABLE_RX_POISONED_RESP ( DISABLE_RX_POISONED_RESP ),
.DISABLE_RX_TC_FILTER ( DISABLE_RX_TC_FILTER ),
.DISABLE_SCRAMBLING ( DISABLE_SCRAMBLING ),
.DNSTREAM_LINK_NUM ( DNSTREAM_LINK_NUM ),
.DSN_BASE_PTR ( DSN_BASE_PTR ),
.DSN_CAP_ID ( DSN_CAP_ID ),
.DSN_CAP_NEXTPTR ( DSN_CAP_NEXTPTR ),
.DSN_CAP_ON ( DSN_CAP_ON ),
.DSN_CAP_VERSION ( DSN_CAP_VERSION ),
.ENABLE_MSG_ROUTE ( ENABLE_MSG_ROUTE ),
.ENABLE_RX_TD_ECRC_TRIM ( ENABLE_RX_TD_ECRC_TRIM ),
.ENDEND_TLP_PREFIX_FORWARDING_SUPPORTED ( ENDEND_TLP_PREFIX_FORWARDING_SUPPORTED ),
.ENTER_RVRY_EI_L0 ( ENTER_RVRY_EI_L0 ),
.EXIT_LOOPBACK_ON_EI ( EXIT_LOOPBACK_ON_EI ),
.EXPANSION_ROM ( EXPANSION_ROM ),
.EXT_CFG_CAP_PTR ( EXT_CFG_CAP_PTR ),
.EXT_CFG_XP_CAP_PTR ( EXT_CFG_XP_CAP_PTR ),
.HEADER_TYPE ( HEADER_TYPE ),
.INFER_EI ( INFER_EI ),
.INTERRUPT_PIN ( INTERRUPT_PIN ),
.INTERRUPT_STAT_AUTO ( INTERRUPT_STAT_AUTO ),
.IS_SWITCH ( IS_SWITCH ),
.LAST_CONFIG_DWORD ( LAST_CONFIG_DWORD ),
.LINK_CAP_ASPM_OPTIONALITY ( LINK_CAP_ASPM_OPTIONALITY ),
.LINK_CAP_ASPM_SUPPORT ( LINK_CAP_ASPM_SUPPORT ),
.LINK_CAP_CLOCK_POWER_MANAGEMENT ( LINK_CAP_CLOCK_POWER_MANAGEMENT ),
.LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP ( LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP ),
.LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP ( LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP ),
.LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 ( LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 ),
.LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 ( LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 ),
.LINK_CAP_L0S_EXIT_LATENCY_GEN1 ( LINK_CAP_L0S_EXIT_LATENCY_GEN1 ),
.LINK_CAP_L0S_EXIT_LATENCY_GEN2 ( LINK_CAP_L0S_EXIT_LATENCY_GEN2 ),
.LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 ( LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 ),
.LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 ( LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 ),
.LINK_CAP_L1_EXIT_LATENCY_GEN1 ( LINK_CAP_L1_EXIT_LATENCY_GEN1 ),
.LINK_CAP_L1_EXIT_LATENCY_GEN2 ( LINK_CAP_L1_EXIT_LATENCY_GEN2 ),
.LINK_CAP_MAX_LINK_SPEED ( LINK_CAP_MAX_LINK_SPEED ),
.LINK_CAP_MAX_LINK_WIDTH ( LINK_CAP_MAX_LINK_WIDTH ),
.LINK_CAP_RSVD_23 ( LINK_CAP_RSVD_23 ),
.LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE ( LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE ),
.LINK_CONTROL_RCB ( LINK_CONTROL_RCB ),
.LINK_CTRL2_DEEMPHASIS ( LINK_CTRL2_DEEMPHASIS ),
.LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE ( LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE ),
.LINK_CTRL2_TARGET_LINK_SPEED ( LINK_CTRL2_TARGET_LINK_SPEED ),
.LINK_STATUS_SLOT_CLOCK_CONFIG ( LINK_STATUS_SLOT_CLOCK_CONFIG ),
.LL_ACK_TIMEOUT ( LL_ACK_TIMEOUT ),
.LL_ACK_TIMEOUT_EN ( LL_ACK_TIMEOUT_EN ),
.LL_ACK_TIMEOUT_FUNC ( LL_ACK_TIMEOUT_FUNC ),
.LL_REPLAY_TIMEOUT ( LL_REPLAY_TIMEOUT ),
.LL_REPLAY_TIMEOUT_EN ( LL_REPLAY_TIMEOUT_EN ),
.LL_REPLAY_TIMEOUT_FUNC ( LL_REPLAY_TIMEOUT_FUNC ),
.LTSSM_MAX_LINK_WIDTH ( LTSSM_MAX_LINK_WIDTH ),
.MPS_FORCE ( MPS_FORCE ),
.MSI_BASE_PTR ( MSI_BASE_PTR ),
.MSI_CAP_ID ( MSI_CAP_ID ),
.MSI_CAP_MULTIMSG_EXTENSION ( MSI_CAP_MULTIMSG_EXTENSION ),
.MSI_CAP_MULTIMSGCAP ( MSI_CAP_MULTIMSGCAP ),
.MSI_CAP_NEXTPTR ( MSI_CAP_NEXTPTR ),
.MSI_CAP_ON ( MSI_CAP_ON ),
.MSI_CAP_PER_VECTOR_MASKING_CAPABLE ( MSI_CAP_PER_VECTOR_MASKING_CAPABLE ),
.MSI_CAP_64_BIT_ADDR_CAPABLE ( MSI_CAP_64_BIT_ADDR_CAPABLE ),
.MSIX_BASE_PTR ( MSIX_BASE_PTR ),
.MSIX_CAP_ID ( MSIX_CAP_ID ),
.MSIX_CAP_NEXTPTR ( MSIX_CAP_NEXTPTR ),
.MSIX_CAP_ON ( MSIX_CAP_ON ),
.MSIX_CAP_PBA_BIR ( MSIX_CAP_PBA_BIR ),
.MSIX_CAP_PBA_OFFSET ( MSIX_CAP_PBA_OFFSET ),
.MSIX_CAP_TABLE_BIR ( MSIX_CAP_TABLE_BIR ),
.MSIX_CAP_TABLE_OFFSET ( MSIX_CAP_TABLE_OFFSET ),
.MSIX_CAP_TABLE_SIZE ( MSIX_CAP_TABLE_SIZE ),
.N_FTS_COMCLK_GEN1 ( N_FTS_COMCLK_GEN1 ),
.N_FTS_COMCLK_GEN2 ( N_FTS_COMCLK_GEN2 ),
.N_FTS_GEN1 ( N_FTS_GEN1 ),
.N_FTS_GEN2 ( N_FTS_GEN2 ),
.PCIE_BASE_PTR ( PCIE_BASE_PTR ),
.PCIE_CAP_CAPABILITY_ID ( PCIE_CAP_CAPABILITY_ID ),
.PCIE_CAP_CAPABILITY_VERSION ( PCIE_CAP_CAPABILITY_VERSION ),
.PCIE_CAP_DEVICE_PORT_TYPE ( PCIE_CAP_DEVICE_PORT_TYPE ),
.PCIE_CAP_NEXTPTR ( PCIE_CAP_NEXTPTR ),
.PCIE_CAP_ON ( PCIE_CAP_ON ),
.PCIE_CAP_RSVD_15_14 ( PCIE_CAP_RSVD_15_14 ),
.PCIE_CAP_SLOT_IMPLEMENTED ( PCIE_CAP_SLOT_IMPLEMENTED ),
.PCIE_REVISION ( PCIE_REVISION ),
.PL_AUTO_CONFIG ( PL_AUTO_CONFIG ),
.PL_FAST_TRAIN ( PL_FAST_TRAIN ),
.PM_ASPML0S_TIMEOUT ( PM_ASPML0S_TIMEOUT ),
.PM_ASPML0S_TIMEOUT_EN ( PM_ASPML0S_TIMEOUT_EN ),
.PM_ASPML0S_TIMEOUT_FUNC ( PM_ASPML0S_TIMEOUT_FUNC ),
.PM_ASPM_FASTEXIT ( PM_ASPM_FASTEXIT ),
.PM_BASE_PTR ( PM_BASE_PTR ),
.PM_CAP_AUXCURRENT ( PM_CAP_AUXCURRENT ),
.PM_CAP_DSI ( PM_CAP_DSI ),
.PM_CAP_D1SUPPORT ( PM_CAP_D1SUPPORT ),
.PM_CAP_D2SUPPORT ( PM_CAP_D2SUPPORT ),
.PM_CAP_ID ( PM_CAP_ID ),
.PM_CAP_NEXTPTR ( PM_CAP_NEXTPTR ),
.PM_CAP_ON ( PM_CAP_ON ),
.PM_CAP_PME_CLOCK ( PM_CAP_PME_CLOCK ),
.PM_CAP_PMESUPPORT ( PM_CAP_PMESUPPORT ),
.PM_CAP_RSVD_04 ( PM_CAP_RSVD_04 ),
.PM_CAP_VERSION ( PM_CAP_VERSION ),
.PM_CSR_BPCCEN ( PM_CSR_BPCCEN ),
.PM_CSR_B2B3 ( PM_CSR_B2B3 ),
.PM_CSR_NOSOFTRST ( PM_CSR_NOSOFTRST ),
.PM_DATA_SCALE0 ( PM_DATA_SCALE0 ),
.PM_DATA_SCALE1 ( PM_DATA_SCALE1 ),
.PM_DATA_SCALE2 ( PM_DATA_SCALE2 ),
.PM_DATA_SCALE3 ( PM_DATA_SCALE3 ),
.PM_DATA_SCALE4 ( PM_DATA_SCALE4 ),
.PM_DATA_SCALE5 ( PM_DATA_SCALE5 ),
.PM_DATA_SCALE6 ( PM_DATA_SCALE6 ),
.PM_DATA_SCALE7 ( PM_DATA_SCALE7 ),
.PM_DATA0 ( PM_DATA0 ),
.PM_DATA1 ( PM_DATA1 ),
.PM_DATA2 ( PM_DATA2 ),
.PM_DATA3 ( PM_DATA3 ),
.PM_DATA4 ( PM_DATA4 ),
.PM_DATA5 ( PM_DATA5 ),
.PM_DATA6 ( PM_DATA6 ),
.PM_DATA7 ( PM_DATA7 ),
.PM_MF ( PM_MF ),
.RBAR_BASE_PTR ( RBAR_BASE_PTR ),
.RBAR_CAP_CONTROL_ENCODEDBAR0 ( RBAR_CAP_CONTROL_ENCODEDBAR0 ),
.RBAR_CAP_CONTROL_ENCODEDBAR1 ( RBAR_CAP_CONTROL_ENCODEDBAR1 ),
.RBAR_CAP_CONTROL_ENCODEDBAR2 ( RBAR_CAP_CONTROL_ENCODEDBAR2 ),
.RBAR_CAP_CONTROL_ENCODEDBAR3 ( RBAR_CAP_CONTROL_ENCODEDBAR3 ),
.RBAR_CAP_CONTROL_ENCODEDBAR4 ( RBAR_CAP_CONTROL_ENCODEDBAR4 ),
.RBAR_CAP_CONTROL_ENCODEDBAR5 ( RBAR_CAP_CONTROL_ENCODEDBAR5 ),
.RBAR_CAP_ID ( RBAR_CAP_ID ),
.RBAR_CAP_INDEX0 ( RBAR_CAP_INDEX0 ),
.RBAR_CAP_INDEX1 ( RBAR_CAP_INDEX1 ),
.RBAR_CAP_INDEX2 ( RBAR_CAP_INDEX2 ),
.RBAR_CAP_INDEX3 ( RBAR_CAP_INDEX3 ),
.RBAR_CAP_INDEX4 ( RBAR_CAP_INDEX4 ),
.RBAR_CAP_INDEX5 ( RBAR_CAP_INDEX5 ),
.RBAR_CAP_NEXTPTR ( RBAR_CAP_NEXTPTR ),
.RBAR_CAP_ON ( RBAR_CAP_ON ),
.RBAR_CAP_SUP0 ( RBAR_CAP_SUP0 ),
.RBAR_CAP_SUP1 ( RBAR_CAP_SUP1 ),
.RBAR_CAP_SUP2 ( RBAR_CAP_SUP2 ),
.RBAR_CAP_SUP3 ( RBAR_CAP_SUP3 ),
.RBAR_CAP_SUP4 ( RBAR_CAP_SUP4 ),
.RBAR_CAP_SUP5 ( RBAR_CAP_SUP5 ),
.RBAR_CAP_VERSION ( RBAR_CAP_VERSION ),
.RBAR_NUM ( RBAR_NUM ),
.RECRC_CHK ( RECRC_CHK ),
.RECRC_CHK_TRIM ( RECRC_CHK_TRIM ),
.ROOT_CAP_CRS_SW_VISIBILITY ( ROOT_CAP_CRS_SW_VISIBILITY ),
.RP_AUTO_SPD ( RP_AUTO_SPD ),
.RP_AUTO_SPD_LOOPCNT ( RP_AUTO_SPD_LOOPCNT ),
.SELECT_DLL_IF ( SELECT_DLL_IF ),
.SLOT_CAP_ATT_BUTTON_PRESENT ( SLOT_CAP_ATT_BUTTON_PRESENT ),
.SLOT_CAP_ATT_INDICATOR_PRESENT ( SLOT_CAP_ATT_INDICATOR_PRESENT ),
.SLOT_CAP_ELEC_INTERLOCK_PRESENT ( SLOT_CAP_ELEC_INTERLOCK_PRESENT ),
.SLOT_CAP_HOTPLUG_CAPABLE ( SLOT_CAP_HOTPLUG_CAPABLE ),
.SLOT_CAP_HOTPLUG_SURPRISE ( SLOT_CAP_HOTPLUG_SURPRISE ),
.SLOT_CAP_MRL_SENSOR_PRESENT ( SLOT_CAP_MRL_SENSOR_PRESENT ),
.SLOT_CAP_NO_CMD_COMPLETED_SUPPORT ( SLOT_CAP_NO_CMD_COMPLETED_SUPPORT ),
.SLOT_CAP_PHYSICAL_SLOT_NUM ( SLOT_CAP_PHYSICAL_SLOT_NUM ),
.SLOT_CAP_POWER_CONTROLLER_PRESENT ( SLOT_CAP_POWER_CONTROLLER_PRESENT ),
.SLOT_CAP_POWER_INDICATOR_PRESENT ( SLOT_CAP_POWER_INDICATOR_PRESENT ),
.SLOT_CAP_SLOT_POWER_LIMIT_SCALE ( SLOT_CAP_SLOT_POWER_LIMIT_SCALE ),
.SLOT_CAP_SLOT_POWER_LIMIT_VALUE ( SLOT_CAP_SLOT_POWER_LIMIT_VALUE ),
.SPARE_BIT0 ( SPARE_BIT0 ),
.SPARE_BIT1 ( SPARE_BIT1 ),
.SPARE_BIT2 ( SPARE_BIT2 ),
.SPARE_BIT3 ( SPARE_BIT3 ),
.SPARE_BIT4 ( SPARE_BIT4 ),
.SPARE_BIT5 ( SPARE_BIT5 ),
.SPARE_BIT6 ( SPARE_BIT6 ),
.SPARE_BIT7 ( SPARE_BIT7 ),
.SPARE_BIT8 ( SPARE_BIT8 ),
.SPARE_BYTE0 ( SPARE_BYTE0 ),
.SPARE_BYTE1 ( SPARE_BYTE1 ),
.SPARE_BYTE2 ( SPARE_BYTE2 ),
.SPARE_BYTE3 ( SPARE_BYTE3 ),
.SPARE_WORD0 ( SPARE_WORD0 ),
.SPARE_WORD1 ( SPARE_WORD1 ),
.SPARE_WORD2 ( SPARE_WORD2 ),
.SPARE_WORD3 ( SPARE_WORD3 ),
.SSL_MESSAGE_AUTO ( SSL_MESSAGE_AUTO ),
.TECRC_EP_INV ( TECRC_EP_INV ),
.TL_RBYPASS ( TL_RBYPASS ),
.TL_RX_RAM_RADDR_LATENCY ( TL_RX_RAM_RADDR_LATENCY ),
.TL_RX_RAM_RDATA_LATENCY ( TL_RX_RAM_RDATA_LATENCY ),
.TL_RX_RAM_WRITE_LATENCY ( TL_RX_RAM_WRITE_LATENCY ),
.TL_TFC_DISABLE ( TL_TFC_DISABLE ),
.TL_TX_CHECKS_DISABLE ( TL_TX_CHECKS_DISABLE ),
.TL_TX_RAM_RADDR_LATENCY ( TL_TX_RAM_RADDR_LATENCY ),
.TL_TX_RAM_RDATA_LATENCY ( TL_TX_RAM_RDATA_LATENCY ),
.TL_TX_RAM_WRITE_LATENCY ( TL_TX_RAM_WRITE_LATENCY ),
.TRN_DW ( TRN_DW ),
.TRN_NP_FC ( TRN_NP_FC ),
.UPCONFIG_CAPABLE ( UPCONFIG_CAPABLE ),
.UPSTREAM_FACING ( UPSTREAM_FACING ),
.UR_ATOMIC ( UR_ATOMIC ),
.UR_CFG1 ( UR_CFG1 ),
.UR_INV_REQ ( UR_INV_REQ ),
.UR_PRS_RESPONSE ( UR_PRS_RESPONSE ),
.USE_RID_PINS ( USE_RID_PINS ),
.USER_CLK_FREQ ( USER_CLK_FREQ ),
.USER_CLK2_DIV2 ( USER_CLK2_DIV2 ),
.VC_BASE_PTR ( VC_BASE_PTR ),
.VC_CAP_ID ( VC_CAP_ID ),
.VC_CAP_NEXTPTR ( VC_CAP_NEXTPTR ),
.VC_CAP_ON ( VC_CAP_ON ),
.VC_CAP_REJECT_SNOOP_TRANSACTIONS ( VC_CAP_REJECT_SNOOP_TRANSACTIONS ),
.VC_CAP_VERSION ( VC_CAP_VERSION ),
.VC0_CPL_INFINITE ( VC0_CPL_INFINITE ),
.VC0_RX_RAM_LIMIT ( VC0_RX_RAM_LIMIT ),
.VC0_TOTAL_CREDITS_CD ( VC0_TOTAL_CREDITS_CD ),
.VC0_TOTAL_CREDITS_CH ( VC0_TOTAL_CREDITS_CH ),
.VC0_TOTAL_CREDITS_NPD ( VC0_TOTAL_CREDITS_NPD ),
.VC0_TOTAL_CREDITS_NPH ( VC0_TOTAL_CREDITS_NPH ),
.VC0_TOTAL_CREDITS_PD ( VC0_TOTAL_CREDITS_PD ),
.VC0_TOTAL_CREDITS_PH ( VC0_TOTAL_CREDITS_PH ),
.VC0_TX_LASTPACKET ( VC0_TX_LASTPACKET ),
.VSEC_BASE_PTR ( VSEC_BASE_PTR ),
.VSEC_CAP_HDR_ID ( VSEC_CAP_HDR_ID ),
.VSEC_CAP_HDR_REVISION ( VSEC_CAP_HDR_REVISION ),
.VSEC_CAP_ID ( VSEC_CAP_ID ),
.VSEC_CAP_IS_LINK_VISIBLE ( VSEC_CAP_IS_LINK_VISIBLE ),
.VSEC_CAP_NEXTPTR ( VSEC_CAP_NEXTPTR ),
.VSEC_CAP_ON ( VSEC_CAP_ON ),
.VSEC_CAP_VERSION ( VSEC_CAP_VERSION )
`ifdef B_TESTMODE
,
.TEST_MODE_PIN_CHAR ( TEST_MODE_PIN_CHAR )
`endif
)
pcie_block_i (
.TRNTD ({ {(128-C_DATA_WIDTH){1'b0}} ,trn_td} ),
.TRNTREM ({ {(2-REM_WIDTH){1'b0}} ,trn_trem} ),
.TRNTSOF (trn_tsof ),
.TRNTEOF (trn_teof ),
.TRNTSRCRDY (trn_tsrc_rdy ),
.TRNTSRCDSC (trn_tsrc_dsc ),
.TRNTERRFWD (trn_terrfwd ),
.TRNTECRCGEN (trn_tecrc_gen ),
.TRNTSTR (trn_tstr ),
.TRNTCFGGNT (trn_tcfg_gnt ),
.TRNRDSTRDY (trn_rdst_rdy ),
.TRNRNPREQ (trn_rnp_req ),
.TRNRFCPRET (trn_rfcp_ret ),
.TRNRNPOK (trn_rnp_ok ),
.TRNFCSEL (trn_fc_sel ),
.MIMTXRDATA (mim_tx_rdata ),
.MIMRXRDATA (mim_rx_rdata ),
.TRNTDLLPDATA (trn_tdllp_data ),
.TRNTDLLPSRCRDY (trn_tdllp_src_rdy ),
.LL2TLPRCV (ll2_tlp_rcv ),
.LL2SENDENTERL1 (ll2_send_enter_l1 ),
.LL2SENDENTERL23 (ll2_send_enter_l23 ),
.LL2SENDASREQL1 (ll2_send_as_req_l1 ),
.LL2SENDPMACK (ll2_send_pm_ack ),
.PL2DIRECTEDLSTATE (pl2_directed_lstate ),
.LL2SUSPENDNOW (ll2_suspend_now ),
.TL2PPMSUSPENDREQ (tl2_ppm_suspend_req ),
.TL2ASPMSUSPENDCREDITCHECK (tl2_aspm_suspend_credit_check ),
.PLDIRECTEDLINKCHANGE (pl_directed_link_change ),
.PLDIRECTEDLINKWIDTH (pl_directed_link_width ),
.PLDIRECTEDLINKSPEED (pl_directed_link_speed ),
.PLDIRECTEDLINKAUTON (pl_directed_link_auton ),
.PLUPSTREAMPREFERDEEMPH (pl_upstream_prefer_deemph ),
.PLDOWNSTREAMDEEMPHSOURCE (pl_downstream_deemph_source ),
.PLDIRECTEDLTSSMNEW (pl_directed_ltssm_new ),
.PLDIRECTEDLTSSMNEWVLD (pl_directed_ltssm_new_vld ),
.PLDIRECTEDLTSSMSTALL (pl_directed_ltssm_stall ),
.PIPERX0CHARISK (pipe_rx0_char_is_k ),
.PIPERX1CHARISK (pipe_rx1_char_is_k ),
.PIPERX2CHARISK (pipe_rx2_char_is_k ),
.PIPERX3CHARISK (pipe_rx3_char_is_k ),
.PIPERX4CHARISK (pipe_rx4_char_is_k ),
.PIPERX5CHARISK (pipe_rx5_char_is_k ),
.PIPERX6CHARISK (pipe_rx6_char_is_k ),
.PIPERX7CHARISK (pipe_rx7_char_is_k ),
.PIPERX0VALID (pipe_rx0_valid ),
.PIPERX1VALID (pipe_rx1_valid ),
.PIPERX2VALID (pipe_rx2_valid ),
.PIPERX3VALID (pipe_rx3_valid ),
.PIPERX4VALID (pipe_rx4_valid ),
.PIPERX5VALID (pipe_rx5_valid ),
.PIPERX6VALID (pipe_rx6_valid ),
.PIPERX7VALID (pipe_rx7_valid ),
.PIPERX0DATA (pipe_rx0_data ),
.PIPERX1DATA (pipe_rx1_data ),
.PIPERX2DATA (pipe_rx2_data ),
.PIPERX3DATA (pipe_rx3_data ),
.PIPERX4DATA (pipe_rx4_data ),
.PIPERX5DATA (pipe_rx5_data ),
.PIPERX6DATA (pipe_rx6_data ),
.PIPERX7DATA (pipe_rx7_data ),
.PIPERX0CHANISALIGNED (pipe_rx0_chanisaligned ),
.PIPERX1CHANISALIGNED (pipe_rx1_chanisaligned ),
.PIPERX2CHANISALIGNED (pipe_rx2_chanisaligned ),
.PIPERX3CHANISALIGNED (pipe_rx3_chanisaligned ),
.PIPERX4CHANISALIGNED (pipe_rx4_chanisaligned ),
.PIPERX5CHANISALIGNED (pipe_rx5_chanisaligned ),
.PIPERX6CHANISALIGNED (pipe_rx6_chanisaligned ),
.PIPERX7CHANISALIGNED (pipe_rx7_chanisaligned ),
.PIPERX0STATUS (pipe_rx0_status ),
.PIPERX1STATUS (pipe_rx1_status ),
.PIPERX2STATUS (pipe_rx2_status ),
.PIPERX3STATUS (pipe_rx3_status ),
.PIPERX4STATUS (pipe_rx4_status ),
.PIPERX5STATUS (pipe_rx5_status ),
.PIPERX6STATUS (pipe_rx6_status ),
.PIPERX7STATUS (pipe_rx7_status ),
.PIPERX0PHYSTATUS (pipe_rx0_phy_status ),
.PIPERX1PHYSTATUS (pipe_rx1_phy_status ),
.PIPERX2PHYSTATUS (pipe_rx2_phy_status ),
.PIPERX3PHYSTATUS (pipe_rx3_phy_status ),
.PIPERX4PHYSTATUS (pipe_rx4_phy_status ),
.PIPERX5PHYSTATUS (pipe_rx5_phy_status ),
.PIPERX6PHYSTATUS (pipe_rx6_phy_status ),
.PIPERX7PHYSTATUS (pipe_rx7_phy_status ),
.PIPERX0ELECIDLE (pipe_rx0_elec_idle ),
.PIPERX1ELECIDLE (pipe_rx1_elec_idle ),
.PIPERX2ELECIDLE (pipe_rx2_elec_idle ),
.PIPERX3ELECIDLE (pipe_rx3_elec_idle ),
.PIPERX4ELECIDLE (pipe_rx4_elec_idle ),
.PIPERX5ELECIDLE (pipe_rx5_elec_idle ),
.PIPERX6ELECIDLE (pipe_rx6_elec_idle ),
.PIPERX7ELECIDLE (pipe_rx7_elec_idle ),
.PIPECLK (pipe_clk ),
.USERCLK (user_clk ),
.USERCLK2 (user_clk2 ),
`ifdef VALIDATION
.USERCLKPREBUF (user_clk_prebuf ),
.USERCLKPREBUFEN (user_clk_prebuf_en ),
`endif
`ifdef B_TESTMODE
.USERCLKPREBUF (user_clk_prebuf ),
.USERCLKPREBUFEN (user_clk_prebuf_en ),
.SCANMODEN (scanmode_n ),
.SCANENABLEN (scanenable_n ),
.EDTCLK (edt_clk ),
.EDTUPDATE (edt_update ),
.EDTBYPASS (edt_bypass ),
.EDTCONFIGURATION (edt_configuration ),
.EDTSINGLEBYPASSCHAIN (edt_single_bypass_chain ),
.EDTCHANNELSIN1 (edt_channels_in1 ),
.EDTCHANNELSIN2 (edt_channels_in2 ),
.EDTCHANNELSIN3 (edt_channels_in3 ),
.EDTCHANNELSIN4 (edt_channels_in4 ),
.EDTCHANNELSIN5 (edt_channels_in5 ),
.EDTCHANNELSIN6 (edt_channels_in6 ),
.EDTCHANNELSIN7 (edt_channels_in7 ),
.EDTCHANNELSIN8 (edt_channels_in8 ),
.PMVENABLEN (pmv_enable_n ),
.PMVSELECT (pmv_select ),
.PMVDIVIDE (pmv_divide ),
`endif
//`ifdef SECUREIP
// .GSR (gsr ),
//`endif
.SYSRSTN (sys_rst_n ),
.CMRSTN (cm_rst_n ),
.CMSTICKYRSTN (cm_sticky_rst_n ),
.FUNCLVLRSTN (func_lvl_rst_n ),
.TLRSTN (tl_rst_n ),
.DLRSTN (dl_rst_n ),
.PLRSTN (pl_rst_n ),
.PLTRANSMITHOTRST (pl_transmit_hot_rst ),
// Global pins not on Holistic model
//.CFGRESET (cfg_reset ),
//.GWE (gwe ),
//.GRESTORE (grestore ),
//.GHIGHB (ghigh_b ),
.CFGMGMTDI (cfg_mgmt_di ),
.CFGMGMTBYTEENN (cfg_mgmt_byte_en_n ),
.CFGMGMTDWADDR (cfg_mgmt_dwaddr ),
.CFGMGMTWRRW1CASRWN (cfg_mgmt_wr_rw1c_as_rw_n ),
.CFGMGMTWRREADONLYN (cfg_mgmt_wr_readonly_n ),
.CFGMGMTWRENN (cfg_mgmt_wr_en_n ),
.CFGMGMTRDENN (cfg_mgmt_rd_en_n ),
.CFGERRMALFORMEDN (cfg_err_malformed_n ),
.CFGERRCORN (cfg_err_cor_n ),
.CFGERRURN (cfg_err_ur_n ),
.CFGERRECRCN (cfg_err_ecrc_n ),
.CFGERRCPLTIMEOUTN (cfg_err_cpl_timeout_n ),
.CFGERRCPLABORTN (cfg_err_cpl_abort_n ),
.CFGERRCPLUNEXPECTN (cfg_err_cpl_unexpect_n ),
.CFGERRPOISONEDN (cfg_err_poisoned_n ),
.CFGERRACSN (cfg_err_acs_n ),
.CFGERRATOMICEGRESSBLOCKEDN (cfg_err_atomic_egress_blocked_n ),
.CFGERRMCBLOCKEDN (cfg_err_mc_blocked_n ),
.CFGERRINTERNALUNCORN (cfg_err_internal_uncor_n ),
.CFGERRINTERNALCORN (cfg_err_internal_cor_n ),
.CFGERRPOSTEDN (cfg_err_posted_n ),
.CFGERRLOCKEDN (cfg_err_locked_n ),
.CFGERRNORECOVERYN (cfg_err_norecovery_n ),
.CFGERRAERHEADERLOG (cfg_err_aer_headerlog ),
.CFGERRTLPCPLHEADER (cfg_err_tlp_cpl_header ),
.CFGINTERRUPTN (cfg_interrupt_n ),
.CFGINTERRUPTDI (cfg_interrupt_di ),
.CFGINTERRUPTASSERTN (cfg_interrupt_assert_n ),
.CFGINTERRUPTSTATN (cfg_interrupt_stat_n ),
.CFGDSBUSNUMBER (cfg_ds_bus_number ),
.CFGDSDEVICENUMBER (cfg_ds_device_number ),
.CFGDSFUNCTIONNUMBER (cfg_ds_function_number ),
.CFGPORTNUMBER (cfg_port_number ),
.CFGPMHALTASPML0SN (cfg_pm_halt_aspm_l0s_n ),
.CFGPMHALTASPML1N (cfg_pm_halt_aspm_l1_n ),
.CFGPMFORCESTATEENN (cfg_pm_force_state_en_n ),
.CFGPMFORCESTATE (cfg_pm_force_state ),
.CFGPMWAKEN (cfg_pm_wake_n ),
.CFGPMTURNOFFOKN (cfg_pm_turnoff_ok_n ),
.CFGPMSENDPMETON (cfg_pm_send_pme_to_n ),
.CFGPCIECAPINTERRUPTMSGNUM (cfg_pciecap_interrupt_msgnum ),
.CFGTRNPENDINGN (cfg_trn_pending_n ),
.CFGFORCEMPS (cfg_force_mps ),
.CFGFORCECOMMONCLOCKOFF (cfg_force_common_clock_off ),
.CFGFORCEEXTENDEDSYNCON (cfg_force_extended_sync_on ),
.CFGDSN (cfg_dsn ),
.CFGDEVID (cfg_dev_id ),
.CFGVENDID (cfg_vend_id ),
.CFGREVID (cfg_rev_id ),
.CFGSUBSYSID (cfg_subsys_id ),
.CFGSUBSYSVENDID (cfg_subsys_vend_id ),
.CFGAERINTERRUPTMSGNUM (cfg_aer_interrupt_msgnum ),
.DRPCLK (drp_clk ),
.DRPEN (drp_en ),
.DRPWE (drp_we ),
.DRPADDR (drp_addr ),
.DRPDI (drp_di ),
//.DRPREADPORT0 (drp_read_port_0 ),
//.DRPREADPORT1 (drp_read_port_1 ),
//.DRPREADPORT2 (drp_read_port_2 ),
//.DRPREADPORT3 (drp_read_port_3 ),
//.DRPREADPORT4 (drp_read_port_4 ),
//.DRPREADPORT5 (drp_read_port_5 ),
//.DRPREADPORT6 (drp_read_port_6 ),
//.DRPREADPORT7 (drp_read_port_7 ),
//.DRPREADPORT8 (drp_read_port_8 ),
//.DRPREADPORT9 (drp_read_port_9 ),
//.DRPREADPORT10 (drp_read_port_10 ),
//.DRPREADPORT11 (drp_read_port_11 ),
//.DRPREADPORT12 (drp_read_port_12 ),
.DBGMODE (dbg_mode ),
.DBGSUBMODE (dbg_sub_mode ),
.PLDBGMODE (pl_dbg_mode ),
.TRNTDSTRDY (trn_tdst_rdy_bus ),
.TRNTERRDROP (trn_terr_drop ),
.TRNTBUFAV (trn_tbuf_av ),
.TRNTCFGREQ (trn_tcfg_req ),
.TRNRD ({trn_rd_wire,trn_rd} ),
.TRNRREM ({trn_rrem_wire,trn_rrem} ),
.TRNRSOF (trn_rsof ),
.TRNREOF (trn_reof ),
.TRNRSRCRDY (trn_rsrc_rdy ),
.TRNRSRCDSC (trn_rsrc_dsc ),
.TRNRECRCERR (trn_recrc_err ),
.TRNRERRFWD (trn_rerrfwd ),
.TRNRBARHIT (trn_rbar_hit ),
.TRNLNKUP (trn_lnk_up ),
.TRNFCPH (trn_fc_ph ),
.TRNFCPD (trn_fc_pd ),
.TRNFCNPH (trn_fc_nph ),
.TRNFCNPD (trn_fc_npd ),
.TRNFCCPLH (trn_fc_cplh ),
.TRNFCCPLD (trn_fc_cpld ),
.MIMTXWDATA (mim_tx_wdata ),
.MIMTXWADDR (mim_tx_waddr ),
.MIMTXWEN (mim_tx_wen ),
.MIMTXRADDR (mim_tx_raddr ),
.MIMTXREN (mim_tx_ren ),
.MIMRXWDATA (mim_rx_wdata ),
.MIMRXWADDR (mim_rx_waddr ),
.MIMRXWEN (mim_rx_wen ),
.MIMRXRADDR (mim_rx_raddr ),
.MIMRXREN (mim_rx_ren ),
.TRNTDLLPDSTRDY (trn_tdllp_dst_rdy ),
.TRNRDLLPDATA (trn_rdllp_data ),
.TRNRDLLPSRCRDY (trn_rdllp_src_rdy ),
.LL2TFCINIT1SEQ (ll2_tfc_init1_seq ),
.LL2TFCINIT2SEQ (ll2_tfc_init2_seq ),
.PL2SUSPENDOK (pl2_suspend_ok ),
.PL2RECOVERY (pl2_recovery ),
.PL2RXELECIDLE (pl2_rx_elec_idle ),
.PL2RXPMSTATE (pl2_rx_pm_state ),
.PL2L0REQ (pl2_l0_req ),
.LL2SUSPENDOK (ll2_suspend_ok ),
.LL2TXIDLE (ll2_tx_idle ),
.LL2LINKSTATUS (ll2_link_status ),
.TL2PPMSUSPENDOK (tl2_ppm_suspend_ok ),
.TL2ASPMSUSPENDREQ (tl2_aspm_suspend_req ),
.TL2ASPMSUSPENDCREDITCHECKOK (tl2_aspm_suspend_credit_check_ok ),
.PL2LINKUP (pl2_link_up ),
.PL2RECEIVERERR (pl2_receiver_err ),
.LL2RECEIVERERR (ll2_receiver_err ),
.LL2PROTOCOLERR (ll2_protocol_err ),
.LL2BADTLPERR (ll2_bad_tlp_err ),
.LL2BADDLLPERR (ll2_bad_dllp_err ),
.LL2REPLAYROERR (ll2_replay_ro_err ),
.LL2REPLAYTOERR (ll2_replay_to_err ),
.TL2ERRHDR (tl2_err_hdr ),
.TL2ERRMALFORMED (tl2_err_malformed ),
.TL2ERRRXOVERFLOW (tl2_err_rxoverflow ),
.TL2ERRFCPE (tl2_err_fcpe ),
.PLSELLNKRATE (pl_sel_lnk_rate ),
.PLSELLNKWIDTH (pl_sel_lnk_width ),
.PLLTSSMSTATE (pl_ltssm_state ),
.PLLANEREVERSALMODE (pl_lane_reversal_mode ),
.PLPHYLNKUPN (pl_phy_lnk_up_n ),
.PLTXPMSTATE (pl_tx_pm_state ),
.PLRXPMSTATE (pl_rx_pm_state ),
.PLLINKUPCFGCAP (pl_link_upcfg_cap ),
.PLLINKGEN2CAP (pl_link_gen2_cap ),
.PLLINKPARTNERGEN2SUPPORTED (pl_link_partner_gen2_supported ),
.PLINITIALLINKWIDTH (pl_initial_link_width ),
.PLDIRECTEDCHANGEDONE (pl_directed_change_done ),
.PIPETXRCVRDET (pipe_tx_rcvr_det ),
.PIPETXRESET (pipe_tx_reset ),
.PIPETXRATE (pipe_tx_rate ),
.PIPETXDEEMPH (pipe_tx_deemph ),
.PIPETXMARGIN (pipe_tx_margin ),
.PIPERX0POLARITY (pipe_rx0_polarity ),
.PIPERX1POLARITY (pipe_rx1_polarity ),
.PIPERX2POLARITY (pipe_rx2_polarity ),
.PIPERX3POLARITY (pipe_rx3_polarity ),
.PIPERX4POLARITY (pipe_rx4_polarity ),
.PIPERX5POLARITY (pipe_rx5_polarity ),
.PIPERX6POLARITY (pipe_rx6_polarity ),
.PIPERX7POLARITY (pipe_rx7_polarity ),
.PIPETX0COMPLIANCE (pipe_tx0_compliance ),
.PIPETX1COMPLIANCE (pipe_tx1_compliance ),
.PIPETX2COMPLIANCE (pipe_tx2_compliance ),
.PIPETX3COMPLIANCE (pipe_tx3_compliance ),
.PIPETX4COMPLIANCE (pipe_tx4_compliance ),
.PIPETX5COMPLIANCE (pipe_tx5_compliance ),
.PIPETX6COMPLIANCE (pipe_tx6_compliance ),
.PIPETX7COMPLIANCE (pipe_tx7_compliance ),
.PIPETX0CHARISK (pipe_tx0_char_is_k ),
.PIPETX1CHARISK (pipe_tx1_char_is_k ),
.PIPETX2CHARISK (pipe_tx2_char_is_k ),
.PIPETX3CHARISK (pipe_tx3_char_is_k ),
.PIPETX4CHARISK (pipe_tx4_char_is_k ),
.PIPETX5CHARISK (pipe_tx5_char_is_k ),
.PIPETX6CHARISK (pipe_tx6_char_is_k ),
.PIPETX7CHARISK (pipe_tx7_char_is_k ),
.PIPETX0DATA (pipe_tx0_data ),
.PIPETX1DATA (pipe_tx1_data ),
.PIPETX2DATA (pipe_tx2_data ),
.PIPETX3DATA (pipe_tx3_data ),
.PIPETX4DATA (pipe_tx4_data ),
.PIPETX5DATA (pipe_tx5_data ),
.PIPETX6DATA (pipe_tx6_data ),
.PIPETX7DATA (pipe_tx7_data ),
.PIPETX0ELECIDLE (pipe_tx0_elec_idle ),
.PIPETX1ELECIDLE (pipe_tx1_elec_idle ),
.PIPETX2ELECIDLE (pipe_tx2_elec_idle ),
.PIPETX3ELECIDLE (pipe_tx3_elec_idle ),
.PIPETX4ELECIDLE (pipe_tx4_elec_idle ),
.PIPETX5ELECIDLE (pipe_tx5_elec_idle ),
.PIPETX6ELECIDLE (pipe_tx6_elec_idle ),
.PIPETX7ELECIDLE (pipe_tx7_elec_idle ),
.PIPETX0POWERDOWN (pipe_tx0_powerdown ),
.PIPETX1POWERDOWN (pipe_tx1_powerdown ),
.PIPETX2POWERDOWN (pipe_tx2_powerdown ),
.PIPETX3POWERDOWN (pipe_tx3_powerdown ),
.PIPETX4POWERDOWN (pipe_tx4_powerdown ),
.PIPETX5POWERDOWN (pipe_tx5_powerdown ),
.PIPETX6POWERDOWN (pipe_tx6_powerdown ),
.PIPETX7POWERDOWN (pipe_tx7_powerdown ),
`ifdef B_TESTMODE
.PMVOUT (pmv_out ),
.SCANOUT (scanout ),
`endif
.USERRSTN (user_rst_n ),
.PLRECEIVEDHOTRST (pl_received_hot_rst ),
.RECEIVEDFUNCLVLRSTN (received_func_lvl_rst_n ),
.LNKCLKEN (lnk_clk_en ),
.CFGMGMTDO (cfg_mgmt_do ),
.CFGMGMTRDWRDONEN (cfg_mgmt_rd_wr_done_n ),
.CFGERRAERHEADERLOGSETN (cfg_err_aer_headerlog_set_n ),
.CFGERRCPLRDYN (cfg_err_cpl_rdy_n ),
.CFGINTERRUPTRDYN (cfg_interrupt_rdy_n ),
.CFGINTERRUPTMMENABLE (cfg_interrupt_mmenable ),
.CFGINTERRUPTMSIENABLE (cfg_interrupt_msienable ),
.CFGINTERRUPTDO (cfg_interrupt_do ),
.CFGINTERRUPTMSIXENABLE (cfg_interrupt_msixenable ),
.CFGINTERRUPTMSIXFM (cfg_interrupt_msixfm ),
.CFGMSGRECEIVED (cfg_msg_received ),
.CFGMSGDATA (cfg_msg_data ),
.CFGMSGRECEIVEDERRCOR (cfg_msg_received_err_cor ),
.CFGMSGRECEIVEDERRNONFATAL (cfg_msg_received_err_non_fatal ),
.CFGMSGRECEIVEDERRFATAL (cfg_msg_received_err_fatal ),
.CFGMSGRECEIVEDASSERTINTA (cfg_msg_received_assert_int_a ),
.CFGMSGRECEIVEDDEASSERTINTA (cfg_msg_received_deassert_int_a ),
.CFGMSGRECEIVEDASSERTINTB (cfg_msg_received_assert_int_b ),
.CFGMSGRECEIVEDDEASSERTINTB (cfg_msg_received_deassert_int_b ),
.CFGMSGRECEIVEDASSERTINTC (cfg_msg_received_assert_int_c ),
.CFGMSGRECEIVEDDEASSERTINTC (cfg_msg_received_deassert_int_c ),
.CFGMSGRECEIVEDASSERTINTD (cfg_msg_received_assert_int_d ),
.CFGMSGRECEIVEDDEASSERTINTD (cfg_msg_received_deassert_int_d ),
.CFGMSGRECEIVEDPMPME (cfg_msg_received_pm_pme ),
.CFGMSGRECEIVEDPMETOACK (cfg_msg_received_pme_to_ack ),
.CFGMSGRECEIVEDPMETO (cfg_msg_received_pme_to ),
.CFGMSGRECEIVEDSETSLOTPOWERLIMIT (cfg_msg_received_setslotpowerlimit ),
.CFGMSGRECEIVEDUNLOCK (cfg_msg_received_unlock ),
.CFGMSGRECEIVEDPMASNAK (cfg_msg_received_pm_as_nak ),
.CFGPCIELINKSTATE (cfg_pcie_link_state ),
.CFGPMRCVASREQL1N (cfg_pm_rcv_as_req_l1_n ),
.CFGPMRCVREQACKN (cfg_pm_rcv_req_ack_n ),
.CFGPMRCVENTERL1N (cfg_pm_rcv_enter_l1_n ),
.CFGPMRCVENTERL23N (cfg_pm_rcv_enter_l23_n ),
.CFGPMCSRPOWERSTATE (cfg_pmcsr_powerstate ),
.CFGPMCSRPMEEN (cfg_pmcsr_pme_en ),
.CFGPMCSRPMESTATUS (cfg_pmcsr_pme_status ),
.CFGTRANSACTION (cfg_transaction ),
.CFGTRANSACTIONTYPE (cfg_transaction_type ),
.CFGTRANSACTIONADDR (cfg_transaction_addr ),
.CFGCOMMANDIOENABLE (cfg_command_io_enable ),
.CFGCOMMANDMEMENABLE (cfg_command_mem_enable ),
.CFGCOMMANDBUSMASTERENABLE (cfg_command_bus_master_enable ),
.CFGCOMMANDINTERRUPTDISABLE (cfg_command_interrupt_disable ),
.CFGCOMMANDSERREN (cfg_command_serr_en ),
.CFGBRIDGESERREN (cfg_bridge_serr_en ),
.CFGDEVSTATUSCORRERRDETECTED (cfg_dev_status_corr_err_detected ),
.CFGDEVSTATUSNONFATALERRDETECTED (cfg_dev_status_non_fatal_err_detected ),
.CFGDEVSTATUSFATALERRDETECTED (cfg_dev_status_fatal_err_detected ),
.CFGDEVSTATUSURDETECTED (cfg_dev_status_ur_detected ),
.CFGDEVCONTROLCORRERRREPORTINGEN (cfg_dev_control_corr_err_reporting_en ),
.CFGDEVCONTROLNONFATALREPORTINGEN (cfg_dev_control_non_fatal_reporting_en ),
.CFGDEVCONTROLFATALERRREPORTINGEN (cfg_dev_control_fatal_err_reporting_en ),
.CFGDEVCONTROLURERRREPORTINGEN (cfg_dev_control_ur_err_reporting_en ),
.CFGDEVCONTROLENABLERO (cfg_dev_control_enable_ro ),
.CFGDEVCONTROLMAXPAYLOAD (cfg_dev_control_max_payload ),
.CFGDEVCONTROLEXTTAGEN (cfg_dev_control_ext_tag_en ),
.CFGDEVCONTROLPHANTOMEN (cfg_dev_control_phantom_en ),
.CFGDEVCONTROLAUXPOWEREN (cfg_dev_control_aux_power_en ),
.CFGDEVCONTROLNOSNOOPEN (cfg_dev_control_no_snoop_en ),
.CFGDEVCONTROLMAXREADREQ (cfg_dev_control_max_read_req ),
.CFGLINKSTATUSCURRENTSPEED (cfg_link_status_current_speed ),
.CFGLINKSTATUSNEGOTIATEDWIDTH (cfg_link_status_negotiated_width ),
.CFGLINKSTATUSLINKTRAINING (cfg_link_status_link_training ),
.CFGLINKSTATUSDLLACTIVE (cfg_link_status_dll_active ),
.CFGLINKSTATUSBANDWIDTHSTATUS (cfg_link_status_bandwidth_status ),
.CFGLINKSTATUSAUTOBANDWIDTHSTATUS (cfg_link_status_auto_bandwidth_status ),
.CFGLINKCONTROLASPMCONTROL (cfg_link_control_aspm_control ),
.CFGLINKCONTROLRCB (cfg_link_control_rcb ),
.CFGLINKCONTROLLINKDISABLE (cfg_link_control_link_disable ),
.CFGLINKCONTROLRETRAINLINK (cfg_link_control_retrain_link ),
.CFGLINKCONTROLCOMMONCLOCK (cfg_link_control_common_clock ),
.CFGLINKCONTROLEXTENDEDSYNC (cfg_link_control_extended_sync ),
.CFGLINKCONTROLCLOCKPMEN (cfg_link_control_clock_pm_en ),
.CFGLINKCONTROLHWAUTOWIDTHDIS (cfg_link_control_hw_auto_width_dis ),
.CFGLINKCONTROLBANDWIDTHINTEN (cfg_link_control_bandwidth_int_en ),
.CFGLINKCONTROLAUTOBANDWIDTHINTEN (cfg_link_control_auto_bandwidth_int_en ),
.CFGDEVCONTROL2CPLTIMEOUTVAL (cfg_dev_control2_cpl_timeout_val ),
.CFGDEVCONTROL2CPLTIMEOUTDIS (cfg_dev_control2_cpl_timeout_dis ),
.CFGDEVCONTROL2ARIFORWARDEN (cfg_dev_control2_ari_forward_en ),
.CFGDEVCONTROL2ATOMICREQUESTEREN (cfg_dev_control2_atomic_requester_en ),
.CFGDEVCONTROL2ATOMICEGRESSBLOCK (cfg_dev_control2_atomic_egress_block ),
.CFGDEVCONTROL2IDOREQEN (cfg_dev_control2_ido_req_en ),
.CFGDEVCONTROL2IDOCPLEN (cfg_dev_control2_ido_cpl_en ),
.CFGDEVCONTROL2LTREN (cfg_dev_control2_ltr_en ),
.CFGDEVCONTROL2TLPPREFIXBLOCK (cfg_dev_control2_tlp_prefix_block ),
.CFGSLOTCONTROLELECTROMECHILCTLPULSE (cfg_slot_control_electromech_il_ctl_pulse ),
.CFGROOTCONTROLSYSERRCORRERREN (cfg_root_control_syserr_corr_err_en ),
.CFGROOTCONTROLSYSERRNONFATALERREN (cfg_root_control_syserr_non_fatal_err_en ),
.CFGROOTCONTROLSYSERRFATALERREN (cfg_root_control_syserr_fatal_err_en ),
.CFGROOTCONTROLPMEINTEN (cfg_root_control_pme_int_en ),
.CFGAERECRCCHECKEN (cfg_aer_ecrc_check_en ),
.CFGAERECRCGENEN (cfg_aer_ecrc_gen_en ),
.CFGAERROOTERRCORRERRREPORTINGEN (cfg_aer_rooterr_corr_err_reporting_en ),
.CFGAERROOTERRNONFATALERRREPORTINGEN (cfg_aer_rooterr_non_fatal_err_reporting_en ),
.CFGAERROOTERRFATALERRREPORTINGEN (cfg_aer_rooterr_fatal_err_reporting_en ),
.CFGAERROOTERRCORRERRRECEIVED (cfg_aer_rooterr_corr_err_received ),
.CFGAERROOTERRNONFATALERRRECEIVED (cfg_aer_rooterr_non_fatal_err_received ),
.CFGAERROOTERRFATALERRRECEIVED (cfg_aer_rooterr_fatal_err_received ),
.CFGVCTCVCMAP (cfg_vc_tcvc_map ),
.DRPRDY (drp_rdy ),
.DRPDO (drp_do ),
//.DRPWRITEEN (drp_write_en ),
//.DRPWRITEPORT0 (drp_write_port_0 ),
//.DRPWRITEPORT1 (drp_write_port_1 ),
//.DRPWRITEPORT2 (drp_write_port_2 ),
//.DRPWRITEPORT3 (drp_write_port_3 ),
//.DRPWRITEPORT4 (drp_write_port_4 ),
//.DRPWRITEPORT5 (drp_write_port_5 ),
//.DRPWRITEPORT6 (drp_write_port_6 ),
//.DRPWRITEPORT7 (drp_write_port_7 ),
//.DRPWRITEPORT8 (drp_write_port_8 ),
//.DRPWRITEPORT9 (drp_write_port_9 ),
//.DRPWRITEPORT10 (drp_write_port_10 ),
//.DRPWRITEPORT11 (drp_write_port_11 ),
//.DRPWRITEPORT12 (drp_write_port_12 ),
//.DRPREADADDR (drp_read_addr ),
.DBGVECA (dbg_vec_a ),
.DBGVECB (dbg_vec_b ),
.DBGVECC (dbg_vec_c ),
.DBGSCLRA (dbg_sclr_a ),
.DBGSCLRB (dbg_sclr_b ),
.DBGSCLRC (dbg_sclr_c ),
.DBGSCLRD (dbg_sclr_d ),
.DBGSCLRE (dbg_sclr_e ),
.DBGSCLRF (dbg_sclr_f ),
.DBGSCLRG (dbg_sclr_g ),
.DBGSCLRH (dbg_sclr_h ),
.DBGSCLRI (dbg_sclr_i ),
.DBGSCLRJ (dbg_sclr_j ),
.DBGSCLRK (dbg_sclr_k ),
.PLDBGVEC (pl_dbg_vec )
//.XILUNCONNOUT (xil_unconn_out )
);
endmodule
`endif // PCIE_2LM
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2014 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2014.3
// \ \ Description : Xilinx Unified Simulation Library Component
// / / Static Dual Port Synchronous RAM 256-Deep by 1-Wide
// /___/ /\ Filename : RAM256X1D.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
// 07/02/12 - Initial version, from RAM128X1D
// 10/22/14 - Added #1 to $finish (CR 808642).
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module RAM256X1D #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter [255:0] INIT = 256'h0,
parameter [0:0] IS_WCLK_INVERTED = 1'b0
) (
output DPO,
output SPO,
input [7:0] A,
input D,
input [7:0] DPRA,
input WCLK,
input WE
);
// define constants
localparam MODULE_NAME = "RAM256X1D";
reg trig_attr = 1'b0;
`ifdef XIL_ATTR_TEST
reg attr_test = 1'b1;
`else
reg attr_test = 1'b0;
`endif
reg attr_err = 1'b0;
wire IS_WCLK_INVERTED_BIN;
wire D_in;
wire WCLK_in;
wire WE_in;
wire [7:0] A_in;
wire [7:0] DPRA_in;
assign IS_WCLK_INVERTED_BIN = IS_WCLK_INVERTED;
`ifdef XIL_TIMING
wire D_dly;
wire WCLK_dly;
wire WE_dly;
wire [7:0] A_dly;
reg notifier;
wire sh_clk_en_p;
wire sh_clk_en_n;
wire sh_we_clk_en_p;
wire sh_we_clk_en_n;
assign A_in = A_dly;
assign D_in = D_dly;
assign WCLK_in = WCLK_dly ^ IS_WCLK_INVERTED_BIN;
assign WE_in = (WE === 1'bz) || WE_dly; // rv 1
`else
assign A_in = A;
assign D_in = D;
assign WCLK_in = WCLK ^ IS_WCLK_INVERTED_BIN;
assign WE_in = (WE === 1'bz) || WE; // rv 1
`endif
assign DPRA_in = DPRA;
reg [255:0] mem;
initial
mem = INIT;
assign DPO = mem[DPRA_in];
assign SPO = mem[A_in];
always @(posedge WCLK_in)
if (WE_in == 1'b1) mem[A_in] <= #100 D_in;
`ifdef XIL_TIMING
always @(notifier) mem[A_in] <= 1'bx;
assign sh_clk_en_p = ~IS_WCLK_INVERTED_BIN;
assign sh_clk_en_n = IS_WCLK_INVERTED_BIN;
assign sh_we_clk_en_p = WE_in && ~IS_WCLK_INVERTED_BIN;
assign sh_we_clk_en_n = WE_in && IS_WCLK_INVERTED_BIN;
specify
(WCLK => DPO) = (0:0:0, 0:0:0);
(WCLK => SPO) = (0:0:0, 0:0:0);
(A[0] => SPO) = (0:0:0, 0:0:0);
(A[1] => SPO) = (0:0:0, 0:0:0);
(A[2] => SPO) = (0:0:0, 0:0:0);
(A[3] => SPO) = (0:0:0, 0:0:0);
(A[4] => SPO) = (0:0:0, 0:0:0);
(A[5] => SPO) = (0:0:0, 0:0:0);
(A[6] => SPO) = (0:0:0, 0:0:0);
(A[7] => SPO) = (0:0:0, 0:0:0);
(DPRA[0] => DPO) = (0:0:0, 0:0:0);
(DPRA[1] => DPO) = (0:0:0, 0:0:0);
(DPRA[2] => DPO) = (0:0:0, 0:0:0);
(DPRA[3] => DPO) = (0:0:0, 0:0:0);
(DPRA[4] => DPO) = (0:0:0, 0:0:0);
(DPRA[5] => DPO) = (0:0:0, 0:0:0);
(DPRA[6] => DPO) = (0:0:0, 0:0:0);
(DPRA[7] => DPO) = (0:0:0, 0:0:0);
$period (negedge WCLK &&& WE, 0:0:0, notifier);
$period (posedge WCLK &&& WE, 0:0:0, notifier);
$setuphold (negedge WCLK, negedge A[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[0]);
$setuphold (negedge WCLK, negedge A[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[1]);
$setuphold (negedge WCLK, negedge A[2], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[2]);
$setuphold (negedge WCLK, negedge A[3], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[3]);
$setuphold (negedge WCLK, negedge A[4], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[4]);
$setuphold (negedge WCLK, negedge A[5], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[5]);
$setuphold (negedge WCLK, negedge A[6], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[6]);
$setuphold (negedge WCLK, negedge A[7], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[7]);
$setuphold (negedge WCLK, negedge D, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,D_dly);
$setuphold (negedge WCLK, negedge WE, 0:0:0, 0:0:0, notifier,sh_clk_en_n,sh_clk_en_n,WCLK_dly,WE_dly);
$setuphold (negedge WCLK, posedge A[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[0]);
$setuphold (negedge WCLK, posedge A[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[1]);
$setuphold (negedge WCLK, posedge A[2], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[2]);
$setuphold (negedge WCLK, posedge A[3], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[3]);
$setuphold (negedge WCLK, posedge A[4], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[4]);
$setuphold (negedge WCLK, posedge A[5], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[5]);
$setuphold (negedge WCLK, posedge A[6], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[6]);
$setuphold (negedge WCLK, posedge A[7], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[7]);
$setuphold (negedge WCLK, posedge D, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,D_dly);
$setuphold (negedge WCLK, posedge WE, 0:0:0, 0:0:0, notifier,sh_clk_en_n,sh_clk_en_n,WCLK_dly,WE_dly);
$setuphold (posedge WCLK, negedge A[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[0]);
$setuphold (posedge WCLK, negedge A[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[1]);
$setuphold (posedge WCLK, negedge A[2], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[2]);
$setuphold (posedge WCLK, negedge A[3], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[3]);
$setuphold (posedge WCLK, negedge A[4], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[4]);
$setuphold (posedge WCLK, negedge A[5], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[5]);
$setuphold (posedge WCLK, negedge A[6], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[6]);
$setuphold (posedge WCLK, negedge A[7], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[7]);
$setuphold (posedge WCLK, negedge D, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,D_dly);
$setuphold (posedge WCLK, negedge WE, 0:0:0, 0:0:0, notifier,sh_clk_en_p,sh_clk_en_p,WCLK_dly,WE_dly);
$setuphold (posedge WCLK, posedge A[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[0]);
$setuphold (posedge WCLK, posedge A[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[1]);
$setuphold (posedge WCLK, posedge A[2], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[2]);
$setuphold (posedge WCLK, posedge A[3], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[3]);
$setuphold (posedge WCLK, posedge A[4], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[4]);
$setuphold (posedge WCLK, posedge A[5], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[5]);
$setuphold (posedge WCLK, posedge A[6], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[6]);
$setuphold (posedge WCLK, posedge A[7], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[7]);
$setuphold (posedge WCLK, posedge D, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,D_dly);
$setuphold (posedge WCLK, posedge WE, 0:0:0, 0:0:0, notifier,sh_clk_en_p,sh_clk_en_p,WCLK_dly,WE_dly);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
// Date : Fri Sep 22 23:00:32 2017
// Host : DarkCube running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zqynq_lab_1_design_axi_gpio_0_1_sim_netlist.v
// Design : zqynq_lab_1_design_axi_gpio_0_1
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_GPIO_Core
(D,
gpio_io_o,
GPIO_xferAck_i,
gpio_xferAck_Reg,
ip2bus_rdack_i,
ip2bus_wrack_i_D1_reg,
gpio_io_t,
bus2ip_rnw_i_reg,
s_axi_aclk,
SS,
bus2ip_rnw,
bus2ip_cs,
E,
\MEM_DECODE_GEN[0].cs_out_i_reg[0] ,
rst_reg);
output [7:0]D;
output [7:0]gpio_io_o;
output GPIO_xferAck_i;
output gpio_xferAck_Reg;
output ip2bus_rdack_i;
output ip2bus_wrack_i_D1_reg;
output [7:0]gpio_io_t;
input bus2ip_rnw_i_reg;
input s_axi_aclk;
input [0:0]SS;
input bus2ip_rnw;
input bus2ip_cs;
input [0:0]E;
input [7:0]\MEM_DECODE_GEN[0].cs_out_i_reg[0] ;
input [0:0]rst_reg;
wire [7:0]D;
wire [0:0]E;
wire GPIO_xferAck_i;
wire [7:0]\MEM_DECODE_GEN[0].cs_out_i_reg[0] ;
wire [0:0]SS;
wire bus2ip_cs;
wire bus2ip_rnw;
wire bus2ip_rnw_i_reg;
wire [7:0]gpio_io_o;
wire [7:0]gpio_io_t;
wire gpio_xferAck_Reg;
wire iGPIO_xferAck;
wire ip2bus_rdack_i;
wire ip2bus_wrack_i_D1_reg;
wire [0:0]rst_reg;
wire s_axi_aclk;
FDRE \Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_o[7]),
.Q(D[7]),
.R(bus2ip_rnw_i_reg));
FDRE \Not_Dual.ALLOUT_ND.READ_REG_GEN[1].GPIO_DBus_i_reg[25]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_o[6]),
.Q(D[6]),
.R(bus2ip_rnw_i_reg));
FDRE \Not_Dual.ALLOUT_ND.READ_REG_GEN[2].GPIO_DBus_i_reg[26]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_o[5]),
.Q(D[5]),
.R(bus2ip_rnw_i_reg));
FDRE \Not_Dual.ALLOUT_ND.READ_REG_GEN[3].GPIO_DBus_i_reg[27]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_o[4]),
.Q(D[4]),
.R(bus2ip_rnw_i_reg));
FDRE \Not_Dual.ALLOUT_ND.READ_REG_GEN[4].GPIO_DBus_i_reg[28]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_o[3]),
.Q(D[3]),
.R(bus2ip_rnw_i_reg));
FDRE \Not_Dual.ALLOUT_ND.READ_REG_GEN[5].GPIO_DBus_i_reg[29]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_o[2]),
.Q(D[2]),
.R(bus2ip_rnw_i_reg));
FDRE \Not_Dual.ALLOUT_ND.READ_REG_GEN[6].GPIO_DBus_i_reg[30]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_o[1]),
.Q(D[1]),
.R(bus2ip_rnw_i_reg));
FDRE \Not_Dual.ALLOUT_ND.READ_REG_GEN[7].GPIO_DBus_i_reg[31]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_o[0]),
.Q(D[0]),
.R(bus2ip_rnw_i_reg));
FDRE #(
.INIT(1'b0))
\Not_Dual.gpio_Data_Out_reg[0]
(.C(s_axi_aclk),
.CE(E),
.D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [7]),
.Q(gpio_io_o[7]),
.R(SS));
FDRE #(
.INIT(1'b0))
\Not_Dual.gpio_Data_Out_reg[1]
(.C(s_axi_aclk),
.CE(E),
.D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [6]),
.Q(gpio_io_o[6]),
.R(SS));
FDRE #(
.INIT(1'b0))
\Not_Dual.gpio_Data_Out_reg[2]
(.C(s_axi_aclk),
.CE(E),
.D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [5]),
.Q(gpio_io_o[5]),
.R(SS));
FDRE #(
.INIT(1'b0))
\Not_Dual.gpio_Data_Out_reg[3]
(.C(s_axi_aclk),
.CE(E),
.D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [4]),
.Q(gpio_io_o[4]),
.R(SS));
FDRE #(
.INIT(1'b0))
\Not_Dual.gpio_Data_Out_reg[4]
(.C(s_axi_aclk),
.CE(E),
.D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [3]),
.Q(gpio_io_o[3]),
.R(SS));
FDRE #(
.INIT(1'b0))
\Not_Dual.gpio_Data_Out_reg[5]
(.C(s_axi_aclk),
.CE(E),
.D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [2]),
.Q(gpio_io_o[2]),
.R(SS));
FDRE #(
.INIT(1'b0))
\Not_Dual.gpio_Data_Out_reg[6]
(.C(s_axi_aclk),
.CE(E),
.D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [1]),
.Q(gpio_io_o[1]),
.R(SS));
FDRE #(
.INIT(1'b0))
\Not_Dual.gpio_Data_Out_reg[7]
(.C(s_axi_aclk),
.CE(E),
.D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [0]),
.Q(gpio_io_o[0]),
.R(SS));
FDSE #(
.INIT(1'b1))
\Not_Dual.gpio_OE_reg[0]
(.C(s_axi_aclk),
.CE(rst_reg),
.D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [7]),
.Q(gpio_io_t[7]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Not_Dual.gpio_OE_reg[1]
(.C(s_axi_aclk),
.CE(rst_reg),
.D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [6]),
.Q(gpio_io_t[6]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Not_Dual.gpio_OE_reg[2]
(.C(s_axi_aclk),
.CE(rst_reg),
.D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [5]),
.Q(gpio_io_t[5]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Not_Dual.gpio_OE_reg[3]
(.C(s_axi_aclk),
.CE(rst_reg),
.D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [4]),
.Q(gpio_io_t[4]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Not_Dual.gpio_OE_reg[4]
(.C(s_axi_aclk),
.CE(rst_reg),
.D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [3]),
.Q(gpio_io_t[3]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Not_Dual.gpio_OE_reg[5]
(.C(s_axi_aclk),
.CE(rst_reg),
.D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [2]),
.Q(gpio_io_t[2]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Not_Dual.gpio_OE_reg[6]
(.C(s_axi_aclk),
.CE(rst_reg),
.D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [1]),
.Q(gpio_io_t[1]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Not_Dual.gpio_OE_reg[7]
(.C(s_axi_aclk),
.CE(rst_reg),
.D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [0]),
.Q(gpio_io_t[0]),
.S(SS));
FDRE gpio_xferAck_Reg_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(GPIO_xferAck_i),
.Q(gpio_xferAck_Reg),
.R(SS));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT3 #(
.INIT(8'h02))
iGPIO_xferAck_i_1
(.I0(bus2ip_cs),
.I1(gpio_xferAck_Reg),
.I2(GPIO_xferAck_i),
.O(iGPIO_xferAck));
FDRE iGPIO_xferAck_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(iGPIO_xferAck),
.Q(GPIO_xferAck_i),
.R(SS));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT2 #(
.INIT(4'h8))
ip2bus_rdack_i_D1_i_1
(.I0(GPIO_xferAck_i),
.I1(bus2ip_rnw),
.O(ip2bus_rdack_i));
LUT2 #(
.INIT(4'h2))
ip2bus_wrack_i_D1_i_1
(.I0(GPIO_xferAck_i),
.I1(bus2ip_rnw),
.O(ip2bus_wrack_i_D1_reg));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder
(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ,
E,
\Not_Dual.gpio_OE_reg[0] ,
s_axi_arready,
s_axi_wready,
D,
\Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24] ,
s_axi_aclk,
rst_reg,
Q,
bus2ip_rnw_i_reg,
ip2bus_rdack_i_D1,
is_read,
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] ,
ip2bus_wrack_i_D1,
is_write_reg,
s_axi_wdata,
start2_reg,
s_axi_aresetn,
gpio_xferAck_Reg,
GPIO_xferAck_i);
output \MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ;
output [0:0]E;
output [0:0]\Not_Dual.gpio_OE_reg[0] ;
output s_axi_arready;
output s_axi_wready;
output [7:0]D;
output \Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24] ;
input s_axi_aclk;
input rst_reg;
input [2:0]Q;
input bus2ip_rnw_i_reg;
input ip2bus_rdack_i_D1;
input is_read;
input [3:0]\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] ;
input ip2bus_wrack_i_D1;
input is_write_reg;
input [15:0]s_axi_wdata;
input start2_reg;
input s_axi_aresetn;
input gpio_xferAck_Reg;
input GPIO_xferAck_i;
wire [7:0]D;
wire [0:0]E;
wire GPIO_xferAck_i;
wire [3:0]\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] ;
wire \MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0 ;
wire \MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ;
wire \Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24] ;
wire [0:0]\Not_Dual.gpio_OE_reg[0] ;
wire [2:0]Q;
wire bus2ip_rnw_i_reg;
wire gpio_xferAck_Reg;
wire ip2bus_rdack_i_D1;
wire ip2bus_wrack_i_D1;
wire is_read;
wire is_write_reg;
wire rst_reg;
wire s_axi_aclk;
wire s_axi_aresetn;
wire s_axi_arready;
wire [15:0]s_axi_wdata;
wire s_axi_wready;
wire start2_reg;
LUT5 #(
.INIT(32'h000000E0))
\MEM_DECODE_GEN[0].cs_out_i[0]_i_1
(.I0(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I1(start2_reg),
.I2(s_axi_aresetn),
.I3(s_axi_arready),
.I4(s_axi_wready),
.O(\MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0 ));
FDRE \MEM_DECODE_GEN[0].cs_out_i_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0 ),
.Q(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.R(1'b0));
LUT4 #(
.INIT(16'hFFF7))
\Not_Dual.ALLOUT_ND.READ_REG_GEN[7].GPIO_DBus_i[31]_i_1
(.I0(bus2ip_rnw_i_reg),
.I1(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I2(gpio_xferAck_Reg),
.I3(GPIO_xferAck_i),
.O(\Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24] ));
LUT6 #(
.INIT(64'hAAAAAAAAAAABAAAA))
\Not_Dual.gpio_Data_Out[0]_i_1
(.I0(rst_reg),
.I1(Q[1]),
.I2(bus2ip_rnw_i_reg),
.I3(Q[0]),
.I4(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I5(Q[2]),
.O(E));
LUT4 #(
.INIT(16'hFB08))
\Not_Dual.gpio_Data_Out[0]_i_2
(.I0(s_axi_wdata[7]),
.I1(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I2(Q[1]),
.I3(s_axi_wdata[15]),
.O(D[7]));
LUT4 #(
.INIT(16'hFB08))
\Not_Dual.gpio_Data_Out[1]_i_1
(.I0(s_axi_wdata[6]),
.I1(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I2(Q[1]),
.I3(s_axi_wdata[14]),
.O(D[6]));
LUT4 #(
.INIT(16'hFB08))
\Not_Dual.gpio_Data_Out[2]_i_1
(.I0(s_axi_wdata[5]),
.I1(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I2(Q[1]),
.I3(s_axi_wdata[13]),
.O(D[5]));
LUT4 #(
.INIT(16'hFB08))
\Not_Dual.gpio_Data_Out[3]_i_1
(.I0(s_axi_wdata[4]),
.I1(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I2(Q[1]),
.I3(s_axi_wdata[12]),
.O(D[4]));
LUT4 #(
.INIT(16'hFB08))
\Not_Dual.gpio_Data_Out[4]_i_1
(.I0(s_axi_wdata[3]),
.I1(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I2(Q[1]),
.I3(s_axi_wdata[11]),
.O(D[3]));
LUT4 #(
.INIT(16'hFB08))
\Not_Dual.gpio_Data_Out[5]_i_1
(.I0(s_axi_wdata[2]),
.I1(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I2(Q[1]),
.I3(s_axi_wdata[10]),
.O(D[2]));
LUT4 #(
.INIT(16'hFB08))
\Not_Dual.gpio_Data_Out[6]_i_1
(.I0(s_axi_wdata[1]),
.I1(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I2(Q[1]),
.I3(s_axi_wdata[9]),
.O(D[1]));
LUT4 #(
.INIT(16'hFB08))
\Not_Dual.gpio_Data_Out[7]_i_1
(.I0(s_axi_wdata[0]),
.I1(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I2(Q[1]),
.I3(s_axi_wdata[8]),
.O(D[0]));
LUT6 #(
.INIT(64'hAAAAAAAAAAAEAAAA))
\Not_Dual.gpio_OE[0]_i_1
(.I0(rst_reg),
.I1(Q[0]),
.I2(Q[1]),
.I3(bus2ip_rnw_i_reg),
.I4(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I5(Q[2]),
.O(\Not_Dual.gpio_OE_reg[0] ));
LUT6 #(
.INIT(64'hAAAAAAAAAAAEAAAA))
s_axi_arready_INST_0
(.I0(ip2bus_rdack_i_D1),
.I1(is_read),
.I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [2]),
.I3(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [1]),
.I4(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [3]),
.I5(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [0]),
.O(s_axi_arready));
LUT6 #(
.INIT(64'hAAAAAAAAAAAEAAAA))
s_axi_wready_INST_0
(.I0(ip2bus_wrack_i_D1),
.I1(is_write_reg),
.I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [2]),
.I3(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [1]),
.I4(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [3]),
.I5(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [0]),
.O(s_axi_wready));
endmodule
(* C_ALL_INPUTS = "0" *) (* C_ALL_INPUTS_2 = "0" *) (* C_ALL_OUTPUTS = "1" *)
(* C_ALL_OUTPUTS_2 = "0" *) (* C_DOUT_DEFAULT = "0" *) (* C_DOUT_DEFAULT_2 = "0" *)
(* C_FAMILY = "zynq" *) (* C_GPIO2_WIDTH = "32" *) (* C_GPIO_WIDTH = "8" *)
(* C_INTERRUPT_PRESENT = "0" *) (* C_IS_DUAL = "0" *) (* C_S_AXI_ADDR_WIDTH = "9" *)
(* C_S_AXI_DATA_WIDTH = "32" *) (* C_TRI_DEFAULT = "-1" *) (* C_TRI_DEFAULT_2 = "-1" *)
(* downgradeipidentifiedwarnings = "yes" *) (* ip_group = "LOGICORE" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio
(s_axi_aclk,
s_axi_aresetn,
s_axi_awaddr,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rvalid,
s_axi_rready,
ip2intc_irpt,
gpio_io_i,
gpio_io_o,
gpio_io_t,
gpio2_io_i,
gpio2_io_o,
gpio2_io_t);
(* max_fanout = "10000" *) (* sigis = "Clk" *) input s_axi_aclk;
(* max_fanout = "10000" *) (* sigis = "Rst" *) input s_axi_aresetn;
input [8:0]s_axi_awaddr;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wvalid;
output s_axi_wready;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [8:0]s_axi_araddr;
input s_axi_arvalid;
output s_axi_arready;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rvalid;
input s_axi_rready;
(* sigis = "INTR_LEVEL_HIGH" *) output ip2intc_irpt;
input [7:0]gpio_io_i;
output [7:0]gpio_io_o;
output [7:0]gpio_io_t;
input [31:0]gpio2_io_i;
output [31:0]gpio2_io_o;
output [31:0]gpio2_io_t;
wire \<const0> ;
wire \<const1> ;
wire AXI_LITE_IPIF_I_n_17;
wire AXI_LITE_IPIF_I_n_6;
wire AXI_LITE_IPIF_I_n_7;
wire [0:7]DBus_Reg;
wire GPIO_xferAck_i;
wire bus2ip_cs;
wire bus2ip_reset;
wire bus2ip_rnw;
wire gpio_core_1_n_19;
wire [7:0]gpio_io_o;
wire [7:0]gpio_io_t;
wire gpio_xferAck_Reg;
wire [24:31]ip2bus_data;
wire [24:31]ip2bus_data_i_D1;
wire ip2bus_rdack_i;
wire ip2bus_rdack_i_D1;
wire ip2bus_wrack_i_D1;
(* MAX_FANOUT = "10000" *) (* RTL_MAX_FANOUT = "found" *) (* sigis = "Clk" *) wire s_axi_aclk;
wire [8:0]s_axi_araddr;
(* MAX_FANOUT = "10000" *) (* RTL_MAX_FANOUT = "found" *) (* sigis = "Rst" *) wire s_axi_aresetn;
wire s_axi_arready;
wire s_axi_arvalid;
wire [8:0]s_axi_awaddr;
wire s_axi_awvalid;
wire s_axi_bready;
wire s_axi_bvalid;
wire [7:0]\^s_axi_rdata ;
wire s_axi_rready;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire s_axi_wready;
wire s_axi_wvalid;
assign gpio2_io_o[31] = \<const0> ;
assign gpio2_io_o[30] = \<const0> ;
assign gpio2_io_o[29] = \<const0> ;
assign gpio2_io_o[28] = \<const0> ;
assign gpio2_io_o[27] = \<const0> ;
assign gpio2_io_o[26] = \<const0> ;
assign gpio2_io_o[25] = \<const0> ;
assign gpio2_io_o[24] = \<const0> ;
assign gpio2_io_o[23] = \<const0> ;
assign gpio2_io_o[22] = \<const0> ;
assign gpio2_io_o[21] = \<const0> ;
assign gpio2_io_o[20] = \<const0> ;
assign gpio2_io_o[19] = \<const0> ;
assign gpio2_io_o[18] = \<const0> ;
assign gpio2_io_o[17] = \<const0> ;
assign gpio2_io_o[16] = \<const0> ;
assign gpio2_io_o[15] = \<const0> ;
assign gpio2_io_o[14] = \<const0> ;
assign gpio2_io_o[13] = \<const0> ;
assign gpio2_io_o[12] = \<const0> ;
assign gpio2_io_o[11] = \<const0> ;
assign gpio2_io_o[10] = \<const0> ;
assign gpio2_io_o[9] = \<const0> ;
assign gpio2_io_o[8] = \<const0> ;
assign gpio2_io_o[7] = \<const0> ;
assign gpio2_io_o[6] = \<const0> ;
assign gpio2_io_o[5] = \<const0> ;
assign gpio2_io_o[4] = \<const0> ;
assign gpio2_io_o[3] = \<const0> ;
assign gpio2_io_o[2] = \<const0> ;
assign gpio2_io_o[1] = \<const0> ;
assign gpio2_io_o[0] = \<const0> ;
assign gpio2_io_t[31] = \<const1> ;
assign gpio2_io_t[30] = \<const1> ;
assign gpio2_io_t[29] = \<const1> ;
assign gpio2_io_t[28] = \<const1> ;
assign gpio2_io_t[27] = \<const1> ;
assign gpio2_io_t[26] = \<const1> ;
assign gpio2_io_t[25] = \<const1> ;
assign gpio2_io_t[24] = \<const1> ;
assign gpio2_io_t[23] = \<const1> ;
assign gpio2_io_t[22] = \<const1> ;
assign gpio2_io_t[21] = \<const1> ;
assign gpio2_io_t[20] = \<const1> ;
assign gpio2_io_t[19] = \<const1> ;
assign gpio2_io_t[18] = \<const1> ;
assign gpio2_io_t[17] = \<const1> ;
assign gpio2_io_t[16] = \<const1> ;
assign gpio2_io_t[15] = \<const1> ;
assign gpio2_io_t[14] = \<const1> ;
assign gpio2_io_t[13] = \<const1> ;
assign gpio2_io_t[12] = \<const1> ;
assign gpio2_io_t[11] = \<const1> ;
assign gpio2_io_t[10] = \<const1> ;
assign gpio2_io_t[9] = \<const1> ;
assign gpio2_io_t[8] = \<const1> ;
assign gpio2_io_t[7] = \<const1> ;
assign gpio2_io_t[6] = \<const1> ;
assign gpio2_io_t[5] = \<const1> ;
assign gpio2_io_t[4] = \<const1> ;
assign gpio2_io_t[3] = \<const1> ;
assign gpio2_io_t[2] = \<const1> ;
assign gpio2_io_t[1] = \<const1> ;
assign gpio2_io_t[0] = \<const1> ;
assign ip2intc_irpt = \<const0> ;
assign s_axi_awready = s_axi_wready;
assign s_axi_bresp[1] = \<const0> ;
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_rdata[31] = \<const0> ;
assign s_axi_rdata[30] = \<const0> ;
assign s_axi_rdata[29] = \<const0> ;
assign s_axi_rdata[28] = \<const0> ;
assign s_axi_rdata[27] = \<const0> ;
assign s_axi_rdata[26] = \<const0> ;
assign s_axi_rdata[25] = \<const0> ;
assign s_axi_rdata[24] = \<const0> ;
assign s_axi_rdata[23] = \<const0> ;
assign s_axi_rdata[22] = \<const0> ;
assign s_axi_rdata[21] = \<const0> ;
assign s_axi_rdata[20] = \<const0> ;
assign s_axi_rdata[19] = \<const0> ;
assign s_axi_rdata[18] = \<const0> ;
assign s_axi_rdata[17] = \<const0> ;
assign s_axi_rdata[16] = \<const0> ;
assign s_axi_rdata[15] = \<const0> ;
assign s_axi_rdata[14] = \<const0> ;
assign s_axi_rdata[13] = \<const0> ;
assign s_axi_rdata[12] = \<const0> ;
assign s_axi_rdata[11] = \<const0> ;
assign s_axi_rdata[10] = \<const0> ;
assign s_axi_rdata[9] = \<const0> ;
assign s_axi_rdata[8] = \<const0> ;
assign s_axi_rdata[7:0] = \^s_axi_rdata [7:0];
assign s_axi_rresp[1] = \<const0> ;
assign s_axi_rresp[0] = \<const0> ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif AXI_LITE_IPIF_I
(.D({DBus_Reg[0],DBus_Reg[1],DBus_Reg[2],DBus_Reg[3],DBus_Reg[4],DBus_Reg[5],DBus_Reg[6],DBus_Reg[7]}),
.E(AXI_LITE_IPIF_I_n_6),
.GPIO_xferAck_i(GPIO_xferAck_i),
.\Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24] (AXI_LITE_IPIF_I_n_17),
.\Not_Dual.gpio_OE_reg[0] (AXI_LITE_IPIF_I_n_7),
.Q({ip2bus_data_i_D1[24],ip2bus_data_i_D1[25],ip2bus_data_i_D1[26],ip2bus_data_i_D1[27],ip2bus_data_i_D1[28],ip2bus_data_i_D1[29],ip2bus_data_i_D1[30],ip2bus_data_i_D1[31]}),
.bus2ip_cs(bus2ip_cs),
.bus2ip_reset(bus2ip_reset),
.bus2ip_rnw(bus2ip_rnw),
.gpio_xferAck_Reg(gpio_xferAck_Reg),
.ip2bus_rdack_i_D1(ip2bus_rdack_i_D1),
.ip2bus_wrack_i_D1(ip2bus_wrack_i_D1),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr({s_axi_araddr[8],s_axi_araddr[3:2]}),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr({s_axi_awaddr[8],s_axi_awaddr[3:2]}),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(\^s_axi_rdata ),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata({s_axi_wdata[31:24],s_axi_wdata[7:0]}),
.s_axi_wready(s_axi_wready),
.s_axi_wvalid(s_axi_wvalid));
GND GND
(.G(\<const0> ));
VCC VCC
(.P(\<const1> ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_GPIO_Core gpio_core_1
(.D({ip2bus_data[24],ip2bus_data[25],ip2bus_data[26],ip2bus_data[27],ip2bus_data[28],ip2bus_data[29],ip2bus_data[30],ip2bus_data[31]}),
.E(AXI_LITE_IPIF_I_n_6),
.GPIO_xferAck_i(GPIO_xferAck_i),
.\MEM_DECODE_GEN[0].cs_out_i_reg[0] ({DBus_Reg[0],DBus_Reg[1],DBus_Reg[2],DBus_Reg[3],DBus_Reg[4],DBus_Reg[5],DBus_Reg[6],DBus_Reg[7]}),
.SS(bus2ip_reset),
.bus2ip_cs(bus2ip_cs),
.bus2ip_rnw(bus2ip_rnw),
.bus2ip_rnw_i_reg(AXI_LITE_IPIF_I_n_17),
.gpio_io_o(gpio_io_o),
.gpio_io_t(gpio_io_t),
.gpio_xferAck_Reg(gpio_xferAck_Reg),
.ip2bus_rdack_i(ip2bus_rdack_i),
.ip2bus_wrack_i_D1_reg(gpio_core_1_n_19),
.rst_reg(AXI_LITE_IPIF_I_n_7),
.s_axi_aclk(s_axi_aclk));
FDRE \ip2bus_data_i_D1_reg[24]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_data[24]),
.Q(ip2bus_data_i_D1[24]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[25]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_data[25]),
.Q(ip2bus_data_i_D1[25]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[26]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_data[26]),
.Q(ip2bus_data_i_D1[26]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[27]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_data[27]),
.Q(ip2bus_data_i_D1[27]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[28]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_data[28]),
.Q(ip2bus_data_i_D1[28]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[29]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_data[29]),
.Q(ip2bus_data_i_D1[29]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[30]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_data[30]),
.Q(ip2bus_data_i_D1[30]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[31]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_data[31]),
.Q(ip2bus_data_i_D1[31]),
.R(bus2ip_reset));
FDRE ip2bus_rdack_i_D1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_rdack_i),
.Q(ip2bus_rdack_i_D1),
.R(bus2ip_reset));
FDRE ip2bus_wrack_i_D1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_core_1_n_19),
.Q(ip2bus_wrack_i_D1),
.R(bus2ip_reset));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif
(bus2ip_reset,
bus2ip_rnw,
bus2ip_cs,
s_axi_rvalid,
s_axi_bvalid,
s_axi_arready,
E,
\Not_Dual.gpio_OE_reg[0] ,
s_axi_wready,
D,
\Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24] ,
s_axi_rdata,
s_axi_aclk,
s_axi_arvalid,
s_axi_awvalid,
s_axi_wvalid,
s_axi_araddr,
s_axi_awaddr,
s_axi_aresetn,
s_axi_rready,
s_axi_bready,
ip2bus_rdack_i_D1,
ip2bus_wrack_i_D1,
s_axi_wdata,
gpio_xferAck_Reg,
GPIO_xferAck_i,
Q);
output bus2ip_reset;
output bus2ip_rnw;
output bus2ip_cs;
output s_axi_rvalid;
output s_axi_bvalid;
output s_axi_arready;
output [0:0]E;
output [0:0]\Not_Dual.gpio_OE_reg[0] ;
output s_axi_wready;
output [7:0]D;
output \Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24] ;
output [7:0]s_axi_rdata;
input s_axi_aclk;
input s_axi_arvalid;
input s_axi_awvalid;
input s_axi_wvalid;
input [2:0]s_axi_araddr;
input [2:0]s_axi_awaddr;
input s_axi_aresetn;
input s_axi_rready;
input s_axi_bready;
input ip2bus_rdack_i_D1;
input ip2bus_wrack_i_D1;
input [15:0]s_axi_wdata;
input gpio_xferAck_Reg;
input GPIO_xferAck_i;
input [7:0]Q;
wire [7:0]D;
wire [0:0]E;
wire GPIO_xferAck_i;
wire \Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24] ;
wire [0:0]\Not_Dual.gpio_OE_reg[0] ;
wire [7:0]Q;
wire bus2ip_cs;
wire bus2ip_reset;
wire bus2ip_rnw;
wire gpio_xferAck_Reg;
wire ip2bus_rdack_i_D1;
wire ip2bus_wrack_i_D1;
wire s_axi_aclk;
wire [2:0]s_axi_araddr;
wire s_axi_aresetn;
wire s_axi_arready;
wire s_axi_arvalid;
wire [2:0]s_axi_awaddr;
wire s_axi_awvalid;
wire s_axi_bready;
wire s_axi_bvalid;
wire [7:0]s_axi_rdata;
wire s_axi_rready;
wire s_axi_rvalid;
wire [15:0]s_axi_wdata;
wire s_axi_wready;
wire s_axi_wvalid;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment I_SLAVE_ATTACHMENT
(.D(D),
.E(E),
.GPIO_xferAck_i(GPIO_xferAck_i),
.\MEM_DECODE_GEN[0].cs_out_i_reg[0] (bus2ip_cs),
.\Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24] (\Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24] ),
.\Not_Dual.gpio_Data_Out_reg[0] (bus2ip_rnw),
.\Not_Dual.gpio_OE_reg[0] (\Not_Dual.gpio_OE_reg[0] ),
.Q(Q),
.SR(bus2ip_reset),
.gpio_xferAck_Reg(gpio_xferAck_Reg),
.ip2bus_rdack_i_D1(ip2bus_rdack_i_D1),
.ip2bus_wrack_i_D1(ip2bus_wrack_i_D1),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr(s_axi_araddr),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wready(s_axi_wready),
.s_axi_wvalid(s_axi_wvalid));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment
(SR,
\Not_Dual.gpio_Data_Out_reg[0] ,
\MEM_DECODE_GEN[0].cs_out_i_reg[0] ,
s_axi_rvalid,
s_axi_bvalid,
s_axi_arready,
E,
\Not_Dual.gpio_OE_reg[0] ,
s_axi_wready,
D,
\Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24] ,
s_axi_rdata,
s_axi_aclk,
s_axi_arvalid,
s_axi_awvalid,
s_axi_wvalid,
s_axi_araddr,
s_axi_awaddr,
s_axi_aresetn,
s_axi_rready,
s_axi_bready,
ip2bus_rdack_i_D1,
ip2bus_wrack_i_D1,
s_axi_wdata,
gpio_xferAck_Reg,
GPIO_xferAck_i,
Q);
output SR;
output \Not_Dual.gpio_Data_Out_reg[0] ;
output \MEM_DECODE_GEN[0].cs_out_i_reg[0] ;
output s_axi_rvalid;
output s_axi_bvalid;
output s_axi_arready;
output [0:0]E;
output [0:0]\Not_Dual.gpio_OE_reg[0] ;
output s_axi_wready;
output [7:0]D;
output \Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24] ;
output [7:0]s_axi_rdata;
input s_axi_aclk;
input s_axi_arvalid;
input s_axi_awvalid;
input s_axi_wvalid;
input [2:0]s_axi_araddr;
input [2:0]s_axi_awaddr;
input s_axi_aresetn;
input s_axi_rready;
input s_axi_bready;
input ip2bus_rdack_i_D1;
input ip2bus_wrack_i_D1;
input [15:0]s_axi_wdata;
input gpio_xferAck_Reg;
input GPIO_xferAck_i;
input [7:0]Q;
wire [7:0]D;
wire [0:0]E;
wire GPIO_xferAck_i;
wire [3:0]\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 ;
wire \MEM_DECODE_GEN[0].cs_out_i_reg[0] ;
wire \Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24] ;
wire \Not_Dual.gpio_Data_Out_reg[0] ;
wire [0:0]\Not_Dual.gpio_OE_reg[0] ;
wire [7:0]Q;
wire SR;
wire [0:6]bus2ip_addr;
wire \bus2ip_addr_i[2]_i_1_n_0 ;
wire \bus2ip_addr_i[3]_i_1_n_0 ;
wire \bus2ip_addr_i[8]_i_1_n_0 ;
wire \bus2ip_addr_i[8]_i_2_n_0 ;
wire bus2ip_rnw_i06_out;
wire clear;
wire gpio_xferAck_Reg;
wire ip2bus_rdack_i_D1;
wire ip2bus_wrack_i_D1;
wire is_read;
wire is_read_i_1_n_0;
wire is_write;
wire is_write_i_1_n_0;
wire is_write_reg_n_0;
wire [1:0]p_0_out;
wire p_1_in;
wire [3:0]plusOp;
wire s_axi_aclk;
wire [2:0]s_axi_araddr;
wire s_axi_aresetn;
wire s_axi_arready;
wire s_axi_arvalid;
wire [2:0]s_axi_awaddr;
wire s_axi_awvalid;
wire s_axi_bready;
wire s_axi_bvalid;
wire s_axi_bvalid_i_i_1_n_0;
wire [7:0]s_axi_rdata;
wire \s_axi_rdata_i[7]_i_1_n_0 ;
wire s_axi_rready;
wire s_axi_rvalid;
wire s_axi_rvalid_i_i_1_n_0;
wire [15:0]s_axi_wdata;
wire s_axi_wready;
wire s_axi_wvalid;
wire start2;
wire start2_i_1_n_0;
wire [1:0]state;
wire state1__2;
wire \state[1]_i_3_n_0 ;
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT1 #(
.INIT(2'h1))
\INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.O(plusOp[0]));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT2 #(
.INIT(4'h6))
\INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
.O(plusOp[1]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT3 #(
.INIT(8'h78))
\INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
.I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]),
.O(plusOp[2]));
LUT2 #(
.INIT(4'h9))
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1
(.I0(state[0]),
.I1(state[1]),
.O(clear));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'h7F80))
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
.I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]),
.I3(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [3]),
.O(plusOp[3]));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(plusOp[0]),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.R(clear));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(plusOp[1]),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
.R(clear));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[2]
(.C(s_axi_aclk),
.CE(1'b1),
.D(plusOp[2]),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]),
.R(clear));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]
(.C(s_axi_aclk),
.CE(1'b1),
.D(plusOp[3]),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [3]),
.R(clear));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder I_DECODER
(.D(D),
.E(E),
.GPIO_xferAck_i(GPIO_xferAck_i),
.\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] (\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 ),
.\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 (\MEM_DECODE_GEN[0].cs_out_i_reg[0] ),
.\Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24] (\Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24] ),
.\Not_Dual.gpio_OE_reg[0] (\Not_Dual.gpio_OE_reg[0] ),
.Q({bus2ip_addr[0],bus2ip_addr[5],bus2ip_addr[6]}),
.bus2ip_rnw_i_reg(\Not_Dual.gpio_Data_Out_reg[0] ),
.gpio_xferAck_Reg(gpio_xferAck_Reg),
.ip2bus_rdack_i_D1(ip2bus_rdack_i_D1),
.ip2bus_wrack_i_D1(ip2bus_wrack_i_D1),
.is_read(is_read),
.is_write_reg(is_write_reg_n_0),
.rst_reg(SR),
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arready(s_axi_arready),
.s_axi_wdata(s_axi_wdata),
.s_axi_wready(s_axi_wready),
.start2_reg(start2));
LUT5 #(
.INIT(32'hCCCACCCC))
\bus2ip_addr_i[2]_i_1
(.I0(s_axi_araddr[0]),
.I1(s_axi_awaddr[0]),
.I2(state[0]),
.I3(state[1]),
.I4(s_axi_arvalid),
.O(\bus2ip_addr_i[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'hCCCACCCC))
\bus2ip_addr_i[3]_i_1
(.I0(s_axi_araddr[1]),
.I1(s_axi_awaddr[1]),
.I2(state[0]),
.I3(state[1]),
.I4(s_axi_arvalid),
.O(\bus2ip_addr_i[3]_i_1_n_0 ));
LUT5 #(
.INIT(32'h000000EA))
\bus2ip_addr_i[8]_i_1
(.I0(s_axi_arvalid),
.I1(s_axi_awvalid),
.I2(s_axi_wvalid),
.I3(state[1]),
.I4(state[0]),
.O(\bus2ip_addr_i[8]_i_1_n_0 ));
LUT5 #(
.INIT(32'hCCCACCCC))
\bus2ip_addr_i[8]_i_2
(.I0(s_axi_araddr[2]),
.I1(s_axi_awaddr[2]),
.I2(state[0]),
.I3(state[1]),
.I4(s_axi_arvalid),
.O(\bus2ip_addr_i[8]_i_2_n_0 ));
FDRE \bus2ip_addr_i_reg[2]
(.C(s_axi_aclk),
.CE(\bus2ip_addr_i[8]_i_1_n_0 ),
.D(\bus2ip_addr_i[2]_i_1_n_0 ),
.Q(bus2ip_addr[6]),
.R(SR));
FDRE \bus2ip_addr_i_reg[3]
(.C(s_axi_aclk),
.CE(\bus2ip_addr_i[8]_i_1_n_0 ),
.D(\bus2ip_addr_i[3]_i_1_n_0 ),
.Q(bus2ip_addr[5]),
.R(SR));
FDRE \bus2ip_addr_i_reg[8]
(.C(s_axi_aclk),
.CE(\bus2ip_addr_i[8]_i_1_n_0 ),
.D(\bus2ip_addr_i[8]_i_2_n_0 ),
.Q(bus2ip_addr[0]),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT3 #(
.INIT(8'h10))
bus2ip_rnw_i_i_1
(.I0(state[0]),
.I1(state[1]),
.I2(s_axi_arvalid),
.O(bus2ip_rnw_i06_out));
FDRE bus2ip_rnw_i_reg
(.C(s_axi_aclk),
.CE(\bus2ip_addr_i[8]_i_1_n_0 ),
.D(bus2ip_rnw_i06_out),
.Q(\Not_Dual.gpio_Data_Out_reg[0] ),
.R(SR));
LUT5 #(
.INIT(32'h3FFA000A))
is_read_i_1
(.I0(s_axi_arvalid),
.I1(state1__2),
.I2(state[0]),
.I3(state[1]),
.I4(is_read),
.O(is_read_i_1_n_0));
FDRE is_read_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(is_read_i_1_n_0),
.Q(is_read),
.R(SR));
LUT6 #(
.INIT(64'h0040FFFF00400000))
is_write_i_1
(.I0(s_axi_arvalid),
.I1(s_axi_awvalid),
.I2(s_axi_wvalid),
.I3(state[1]),
.I4(is_write),
.I5(is_write_reg_n_0),
.O(is_write_i_1_n_0));
LUT6 #(
.INIT(64'hF88800000000FFFF))
is_write_i_2
(.I0(s_axi_rvalid),
.I1(s_axi_rready),
.I2(s_axi_bvalid),
.I3(s_axi_bready),
.I4(state[0]),
.I5(state[1]),
.O(is_write));
FDRE is_write_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(is_write_i_1_n_0),
.Q(is_write_reg_n_0),
.R(SR));
LUT1 #(
.INIT(2'h1))
rst_i_1
(.I0(s_axi_aresetn),
.O(p_1_in));
FDRE rst_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(p_1_in),
.Q(SR),
.R(1'b0));
LUT5 #(
.INIT(32'h08FF0808))
s_axi_bvalid_i_i_1
(.I0(s_axi_wready),
.I1(state[1]),
.I2(state[0]),
.I3(s_axi_bready),
.I4(s_axi_bvalid),
.O(s_axi_bvalid_i_i_1_n_0));
FDRE #(
.INIT(1'b0))
s_axi_bvalid_i_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_axi_bvalid_i_i_1_n_0),
.Q(s_axi_bvalid),
.R(SR));
LUT2 #(
.INIT(4'h2))
\s_axi_rdata_i[7]_i_1
(.I0(state[0]),
.I1(state[1]),
.O(\s_axi_rdata_i[7]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[0]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[7]_i_1_n_0 ),
.D(Q[0]),
.Q(s_axi_rdata[0]),
.R(SR));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[1]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[7]_i_1_n_0 ),
.D(Q[1]),
.Q(s_axi_rdata[1]),
.R(SR));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[2]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[7]_i_1_n_0 ),
.D(Q[2]),
.Q(s_axi_rdata[2]),
.R(SR));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[3]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[7]_i_1_n_0 ),
.D(Q[3]),
.Q(s_axi_rdata[3]),
.R(SR));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[4]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[7]_i_1_n_0 ),
.D(Q[4]),
.Q(s_axi_rdata[4]),
.R(SR));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[5]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[7]_i_1_n_0 ),
.D(Q[5]),
.Q(s_axi_rdata[5]),
.R(SR));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[6]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[7]_i_1_n_0 ),
.D(Q[6]),
.Q(s_axi_rdata[6]),
.R(SR));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[7]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[7]_i_1_n_0 ),
.D(Q[7]),
.Q(s_axi_rdata[7]),
.R(SR));
LUT5 #(
.INIT(32'h08FF0808))
s_axi_rvalid_i_i_1
(.I0(s_axi_arready),
.I1(state[0]),
.I2(state[1]),
.I3(s_axi_rready),
.I4(s_axi_rvalid),
.O(s_axi_rvalid_i_i_1_n_0));
FDRE #(
.INIT(1'b0))
s_axi_rvalid_i_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_axi_rvalid_i_i_1_n_0),
.Q(s_axi_rvalid),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'h000000F8))
start2_i_1
(.I0(s_axi_awvalid),
.I1(s_axi_wvalid),
.I2(s_axi_arvalid),
.I3(state[1]),
.I4(state[0]),
.O(start2_i_1_n_0));
FDRE start2_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(start2_i_1_n_0),
.Q(start2),
.R(SR));
LUT5 #(
.INIT(32'h77FC44FC))
\state[0]_i_1
(.I0(state1__2),
.I1(state[0]),
.I2(s_axi_arvalid),
.I3(state[1]),
.I4(s_axi_wready),
.O(p_0_out[0]));
LUT5 #(
.INIT(32'h5FFC50FC))
\state[1]_i_1
(.I0(state1__2),
.I1(\state[1]_i_3_n_0 ),
.I2(state[1]),
.I3(state[0]),
.I4(s_axi_arready),
.O(p_0_out[1]));
LUT4 #(
.INIT(16'hF888))
\state[1]_i_2
(.I0(s_axi_bready),
.I1(s_axi_bvalid),
.I2(s_axi_rready),
.I3(s_axi_rvalid),
.O(state1__2));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT3 #(
.INIT(8'h08))
\state[1]_i_3
(.I0(s_axi_wvalid),
.I1(s_axi_awvalid),
.I2(s_axi_arvalid),
.O(\state[1]_i_3_n_0 ));
FDRE \state_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(p_0_out[0]),
.Q(state[0]),
.R(SR));
FDRE \state_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(p_0_out[1]),
.Q(state[1]),
.R(SR));
endmodule
(* CHECK_LICENSE_TYPE = "zqynq_lab_1_design_axi_gpio_0_1,axi_gpio,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "axi_gpio,Vivado 2017.2" *)
(* NotValidForBitStream *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
(s_axi_aclk,
s_axi_aresetn,
s_axi_awaddr,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rvalid,
s_axi_rready,
gpio_io_o);
(* x_interface_info = "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK" *) input s_axi_aclk;
(* x_interface_info = "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST" *) input s_axi_aresetn;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *) input [8:0]s_axi_awaddr;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *) input s_axi_awvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *) output s_axi_awready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *) input [31:0]s_axi_wdata;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *) input [3:0]s_axi_wstrb;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *) input s_axi_wvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *) output s_axi_wready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *) output [1:0]s_axi_bresp;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *) output s_axi_bvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *) input s_axi_bready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *) input [8:0]s_axi_araddr;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *) input s_axi_arvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *) output s_axi_arready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *) output [31:0]s_axi_rdata;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *) output [1:0]s_axi_rresp;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *) output s_axi_rvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *) input s_axi_rready;
(* x_interface_info = "xilinx.com:interface:gpio:1.0 GPIO TRI_O" *) output [7:0]gpio_io_o;
wire [7:0]gpio_io_o;
wire s_axi_aclk;
wire [8:0]s_axi_araddr;
wire s_axi_aresetn;
wire s_axi_arready;
wire s_axi_arvalid;
wire [8:0]s_axi_awaddr;
wire s_axi_awready;
wire s_axi_awvalid;
wire s_axi_bready;
wire [1:0]s_axi_bresp;
wire s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire s_axi_rready;
wire [1:0]s_axi_rresp;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire s_axi_wready;
wire [3:0]s_axi_wstrb;
wire s_axi_wvalid;
wire NLW_U0_ip2intc_irpt_UNCONNECTED;
wire [31:0]NLW_U0_gpio2_io_o_UNCONNECTED;
wire [31:0]NLW_U0_gpio2_io_t_UNCONNECTED;
wire [7:0]NLW_U0_gpio_io_t_UNCONNECTED;
(* C_ALL_INPUTS = "0" *)
(* C_ALL_INPUTS_2 = "0" *)
(* C_ALL_OUTPUTS = "1" *)
(* C_ALL_OUTPUTS_2 = "0" *)
(* C_DOUT_DEFAULT = "0" *)
(* C_DOUT_DEFAULT_2 = "0" *)
(* C_FAMILY = "zynq" *)
(* C_GPIO2_WIDTH = "32" *)
(* C_GPIO_WIDTH = "8" *)
(* C_INTERRUPT_PRESENT = "0" *)
(* C_IS_DUAL = "0" *)
(* C_S_AXI_ADDR_WIDTH = "9" *)
(* C_S_AXI_DATA_WIDTH = "32" *)
(* C_TRI_DEFAULT = "-1" *)
(* C_TRI_DEFAULT_2 = "-1" *)
(* downgradeipidentifiedwarnings = "yes" *)
(* ip_group = "LOGICORE" *)
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio U0
(.gpio2_io_i({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.gpio2_io_o(NLW_U0_gpio2_io_o_UNCONNECTED[31:0]),
.gpio2_io_t(NLW_U0_gpio2_io_t_UNCONNECTED[31:0]),
.gpio_io_i({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.gpio_io_o(gpio_io_o),
.gpio_io_t(NLW_U0_gpio_io_t_UNCONNECTED[7:0]),
.ip2intc_irpt(NLW_U0_ip2intc_irpt_UNCONNECTED),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr(s_axi_araddr),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awready(s_axi_awready),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(s_axi_bresp),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(s_axi_rresp),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wready(s_axi_wready),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wvalid(s_axi_wvalid));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Tecnológico de Costa Rica
// Engineer: Juan José Rojas Salazar
//
// Create Date: 30.07.2016 10:22:05
// Design Name:
// Module Name: V_NORM_FLOAT_TO_FIXED
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
//////////////////////////////////////////////////////////////////////////////////
module V_NORM_FLOAT_TO_FIXED(
//INPUTS
input wire CLK, //system clock
input wire [31:0] F, //VALOR BINARIO EN COMA FLOTANTE
input wire RST_FF, //system reset
input wire Begin_FSM_FF, //INICIA LA CONVERSION
//OUTṔUTS
output wire ACK_FF,//INDICA QUE LA CONVERSION FUE REALIZADA
output wire [31:0] RESULT // RESULTADO FINAL
);
wire Exp_out;
wire [7:0] Exp;
wire EN_REG1;
wire EN_REG2;
wire RST;
wire LOAD;
wire MS_1;
wire EN_MS_1;
wire MS_1_reg;
FSM_Convert_Float_To_Fixed FSM_CONVERT_FLOAT_FIXED(
.CLK(CLK), //system clock
.RST_FF(RST_FF), //system reset
.Exp_out(Exp_out),
.Begin_FSM_FF(Begin_FSM_FF), //inicia la maquina de estados
.Exp(Exp),
.EN_REG1(EN_REG1),
.LOAD(LOAD),
.MS_1(MS_1),
.ACK_FF(ACK_FF),
.EN_MS_1(EN_MS_1),
.EN_REG2(EN_REG2),
.RST(RST)
);
FF_D #(.P(1)) REG_MS_1V(
.CLK(CLK), //RELOJ DEL SISTEMA
.RST(RST), //RESET
.EN(EN_MS_1), //ENABLE
.D(MS_1), //ENTRADA
.Q(MS_1_reg) //SALIDA
);
Convert_Float_To_Fixed_V CONVERT_FLOAT_FIXED_V(
.CLK(CLK),
.FLOAT(F),
.EN_REG1(EN_REG1),
.LOAD(LOAD),
.MS_1(MS_1_reg),
.Exp_out(Exp_out),
.FIXED(RESULT),
.Exp(Exp),
.EN_REG2(EN_REG2),
.RST(RST)
);
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Rose-Hulman Institute of Technology
// Tom D'Agostino
// ECE398 CAN Controller Design
//
// Create Date: 23:00 03/26/2015
// Module Name: main
// Project Name: CAN_Controller
// Target Devices: Nexys 3 running a Xilinx Spartan6 XC6LX16-CS324
// Description: Implements the CAN Bus protocol.
//////////////////////////////////////////////////////////////////////////////////
module Main(
output CAN_TX,
input CAN_RX,
input RESET,
input CLOCK_SIGNAL_IN,
input send_data,
input[7:0] transmit_data
);
wire[63:0] tx_data;
wire txing;
assign tx_data = {8{transmit_data}};
//Device address, arbitrarily chosen
parameter address = 11'h25, rxing = 1'b1;
//Clock Generator (100MHz in, 400MHz out)
Clock_gen clock_block(CLOCK_SIGNAL_IN,clk);
//Baud Clk Generator(currently set for baud of 500kHz)
BaudGen baud_calc(clk,RESET,baud_clk);
//Tx Block
//can_tx tx_block(CAN_TX,CAN_RX,address,clk,baud_clk,RESET,tx_data,send_data);
tx_container tx_can(CAN_TX,txing,CAN_RX,rxing,address,clk,baud_clk,RESET,tx_data,send_data);
//rx_container rx_can(rx_data,rxing,txing,CAN_RX,clk,baud_clk,RESET);
//Rx goes here
endmodule
|
//-----------------------------------------------------------------------------
//
// Jonathan Westhues, April 2006
//-----------------------------------------------------------------------------
module hi_reader(
ck_1356meg,
pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
adc_d, adc_clk,
ssp_frame, ssp_din, ssp_dout, ssp_clk,
dbg,
subcarrier_frequency, minor_mode
);
input ck_1356meg;
output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
input [7:0] adc_d;
output adc_clk;
input ssp_dout;
output ssp_frame, ssp_din, ssp_clk;
output dbg;
input [1:0] subcarrier_frequency;
input [3:0] minor_mode;
assign adc_clk = ck_1356meg; // sample frequency is 13,56 MHz
// When we're a reader, we just need to do the BPSK demod; but when we're an
// eavesdropper, we also need to pick out the commands sent by the reader,
// using AM. Do this the same way that we do it for the simulated tag.
reg after_hysteresis, after_hysteresis_prev, after_hysteresis_prev_prev;
reg [11:0] has_been_low_for;
always @(negedge adc_clk)
begin
if (& adc_d[7:0]) after_hysteresis <= 1'b1;
else if (~(| adc_d[7:0])) after_hysteresis <= 1'b0;
if (after_hysteresis)
begin
has_been_low_for <= 12'd0;
end
else
begin
if (has_been_low_for == 12'd4095)
begin
has_been_low_for <= 12'd0;
after_hysteresis <= 1'b1;
end
else
has_been_low_for <= has_been_low_for + 1;
end
end
// Let us report a correlation every 64 samples. I.e.
// one Q/I pair after 4 subcarrier cycles for the 848kHz subcarrier,
// one Q/I pair after 2 subcarrier cycles for the 424kHz subcarriers,
// one Q/I pair for each subcarrier cyle for the 212kHz subcarrier.
// We need a 6-bit counter for the timing.
reg [5:0] corr_i_cnt;
always @(negedge adc_clk)
begin
corr_i_cnt <= corr_i_cnt + 1;
end
// A couple of registers in which to accumulate the correlations. From the 64 samples
// we would add at most 32 times the difference between unmodulated and modulated signal. It should
// be safe to assume that a tag will not be able to modulate the carrier signal by more than 25%.
// 32 * 255 * 0,25 = 2040, which can be held in 11 bits. Add 1 bit for sign.
// Temporary we might need more bits. For the 212kHz subcarrier we could possible add 32 times the
// maximum signal value before a first subtraction would occur. 32 * 255 = 8160 can be held in 13 bits.
// Add one bit for sign -> need 14 bit registers but final result will fit into 12 bits.
reg signed [13:0] corr_i_accum;
reg signed [13:0] corr_q_accum;
// we will report maximum 8 significant bits
reg signed [7:0] corr_i_out;
reg signed [7:0] corr_q_out;
// the amplitude of the subcarrier is sqrt(ci^2 + cq^2).
// approximate by amplitude = max(|ci|,|cq|) + 1/2*min(|ci|,|cq|)
reg [13:0] corr_amplitude, abs_ci, abs_cq, max_ci_cq;
reg [12:0] min_ci_cq_2; // min_ci_cq / 2
always @(*)
begin
if (corr_i_accum[13] == 1'b0)
abs_ci <= corr_i_accum;
else
abs_ci <= -corr_i_accum;
if (corr_q_accum[13] == 1'b0)
abs_cq <= corr_q_accum;
else
abs_cq <= -corr_q_accum;
if (abs_ci > abs_cq)
begin
max_ci_cq <= abs_ci;
min_ci_cq_2 <= abs_cq / 2;
end
else
begin
max_ci_cq <= abs_cq;
min_ci_cq_2 <= abs_ci / 2;
end
corr_amplitude <= max_ci_cq + min_ci_cq_2;
end
// The subcarrier reference signals
reg subcarrier_I;
reg subcarrier_Q;
always @(*)
begin
if (subcarrier_frequency == `FPGA_HF_READER_SUBCARRIER_848_KHZ)
begin
subcarrier_I = ~corr_i_cnt[3];
subcarrier_Q = ~(corr_i_cnt[3] ^ corr_i_cnt[2]);
end
else if (subcarrier_frequency == `FPGA_HF_READER_SUBCARRIER_212_KHZ)
begin
subcarrier_I = ~corr_i_cnt[5];
subcarrier_Q = ~(corr_i_cnt[5] ^ corr_i_cnt[4]);
end
else
begin // 424 kHz
subcarrier_I = ~corr_i_cnt[4];
subcarrier_Q = ~(corr_i_cnt[4] ^ corr_i_cnt[3]);
end
end
// ADC data appears on the rising edge, so sample it on the falling edge
always @(negedge adc_clk)
begin
// These are the correlators: we correlate against in-phase and quadrature
// versions of our reference signal, and keep the (signed) results or the
// resulting amplitude to send out later over the SSP.
if (corr_i_cnt == 6'd0)
begin
if (minor_mode == `FPGA_HF_READER_MODE_SNIFF_AMPLITUDE)
begin
// send amplitude plus 2 bits reader signal
corr_i_out <= corr_amplitude[13:6];
corr_q_out <= {corr_amplitude[5:0], after_hysteresis_prev_prev, after_hysteresis_prev};
end
else if (minor_mode == `FPGA_HF_READER_MODE_SNIFF_IQ)
begin
// Send 7 most significant bits of in phase tag signal (signed), plus 1 bit reader signal
if (corr_i_accum[13:11] == 3'b000 || corr_i_accum[13:11] == 3'b111)
corr_i_out <= {corr_i_accum[11:5], after_hysteresis_prev_prev};
else // truncate to maximum value
if (corr_i_accum[13] == 1'b0)
corr_i_out <= {7'b0111111, after_hysteresis_prev_prev};
else
corr_i_out <= {7'b1000000, after_hysteresis_prev_prev};
// Send 7 most significant bits of quadrature phase tag signal (signed), plus 1 bit reader signal
if (corr_q_accum[13:11] == 3'b000 || corr_q_accum[13:11] == 3'b111)
corr_q_out <= {corr_q_accum[11:5], after_hysteresis_prev};
else // truncate to maximum value
if (corr_q_accum[13] == 1'b0)
corr_q_out <= {7'b0111111, after_hysteresis_prev};
else
corr_q_out <= {7'b1000000, after_hysteresis_prev};
end
else if (minor_mode == `FPGA_HF_READER_MODE_RECEIVE_AMPLITUDE)
begin
// send amplitude
corr_i_out <= {2'b00, corr_amplitude[13:8]};
corr_q_out <= corr_amplitude[7:0];
end
else if (minor_mode == `FPGA_HF_READER_MODE_RECEIVE_IQ)
begin
// Send 8 bits of in phase tag signal
if (corr_i_accum[13:11] == 3'b000 || corr_i_accum[13:11] == 3'b111)
corr_i_out <= corr_i_accum[11:4];
else // truncate to maximum value
if (corr_i_accum[13] == 1'b0)
corr_i_out <= 8'b01111111;
else
corr_i_out <= 8'b10000000;
// Send 8 bits of quadrature phase tag signal
if (corr_q_accum[13:11] == 3'b000 || corr_q_accum[13:11] == 3'b111)
corr_q_out <= corr_q_accum[11:4];
else // truncate to maximum value
if (corr_q_accum[13] == 1'b0)
corr_q_out <= 8'b01111111;
else
corr_q_out <= 8'b10000000;
end
// for each Q/I pair report two reader signal samples when sniffing. Store the 1st.
after_hysteresis_prev_prev <= after_hysteresis;
// Initialize next correlation.
// Both I and Q reference signals are high when corr_i_nct == 0. Therefore need to accumulate.
corr_i_accum <= $signed({1'b0, adc_d});
corr_q_accum <= $signed({1'b0, adc_d});
end
else
begin
if (subcarrier_I)
corr_i_accum <= corr_i_accum + $signed({1'b0, adc_d});
else
corr_i_accum <= corr_i_accum - $signed({1'b0, adc_d});
if (subcarrier_Q)
corr_q_accum <= corr_q_accum + $signed({1'b0, adc_d});
else
corr_q_accum <= corr_q_accum - $signed({1'b0, adc_d});
end
// for each Q/I pair report two reader signal samples when sniffing. Store the 2nd.
if (corr_i_cnt == 6'd32)
after_hysteresis_prev <= after_hysteresis;
// Then the result from last time is serialized and send out to the ARM.
// We get one report each cycle, and each report is 16 bits, so the
// ssp_clk should be the adc_clk divided by 64/16 = 4.
// ssp_clk frequency = 13,56MHz / 4 = 3.39MHz
if (corr_i_cnt[1:0] == 2'b00)
begin
// Don't shift if we just loaded new data, obviously.
if (corr_i_cnt != 6'd0)
begin
corr_i_out[7:0] <= {corr_i_out[6:0], corr_q_out[7]};
corr_q_out[7:1] <= corr_q_out[6:0];
end
end
end
// ssp clock and frame signal for communication to and from ARM
// _____ _____ _____ _
// ssp_clk | |_____| |_____| |_____|
// _____
// ssp_frame ___| |____________________________
// ___________ ___________ ___________ _
// ssp_d_in X___________X___________X___________X_
//
// corr_i_cnt 0 1 2 3 4 5 6 7 8 9 10 11 12 ...
//
reg ssp_clk;
reg ssp_frame;
always @(negedge adc_clk)
begin
if (corr_i_cnt[1:0] == 2'b00)
ssp_clk <= 1'b1;
if (corr_i_cnt[1:0] == 2'b10)
ssp_clk <= 1'b0;
// set ssp_frame signal for corr_i_cnt = 1..3
// (send one frame with 16 Bits)
if (corr_i_cnt == 6'd1)
ssp_frame <= 1'b1;
if (corr_i_cnt == 6'd3)
ssp_frame <= 1'b0;
end
assign ssp_din = corr_i_out[7];
// a jamming signal
reg jam_signal;
reg [3:0] jam_counter;
always @(negedge adc_clk)
begin
if (corr_i_cnt == 6'd0)
begin
jam_counter <= jam_counter + 1;
jam_signal <= jam_counter[1] ^ jam_counter[3];
end
end
// Antenna drivers
reg pwr_hi, pwr_oe4;
always @(*)
begin
if (minor_mode == `FPGA_HF_READER_MODE_SEND_SHALLOW_MOD)
begin
pwr_hi = ck_1356meg;
pwr_oe4 = ssp_dout;
end
else if (minor_mode == `FPGA_HF_READER_MODE_SEND_FULL_MOD)
begin
pwr_hi = ck_1356meg & ~ssp_dout;
pwr_oe4 = 1'b0;
end
else if (minor_mode == `FPGA_HF_READER_MODE_SEND_JAM)
begin
pwr_hi = ck_1356meg & jam_signal;
pwr_oe4 = 1'b0;
end
else if (minor_mode == `FPGA_HF_READER_MODE_SNIFF_IQ
|| minor_mode == `FPGA_HF_READER_MODE_SNIFF_AMPLITUDE
|| minor_mode == `FPGA_HF_READER_MODE_SNIFF_PHASE)
begin // all off
pwr_hi = 1'b0;
pwr_oe4 = 1'b0;
end
else // receiving from tag
begin
pwr_hi = ck_1356meg;
pwr_oe4 = 1'b0;
end
end
// always on
assign pwr_oe1 = 1'b0;
assign pwr_oe3 = 1'b0;
// Unused.
assign pwr_lo = 1'b0;
assign pwr_oe2 = 1'b0;
// Debug Output
assign dbg = corr_i_cnt[3];
endmodule
|
/**
* testbench.v
*
* mul_32 test
*
*/
module testbench();
localparam width_p = 32;
localparam ring_width_p = width_p*2;
localparam rom_addr_width_p = 32;
logic clk;
logic reset;
bsg_nonsynth_clock_gen #(
.cycle_time_p(10)
) clock_gen (
.o(clk)
);
bsg_nonsynth_reset_gen #(
.reset_cycles_lo_p(4)
,.reset_cycles_hi_p(4)
) reset_gen (
.clk_i(clk)
,.async_reset_o(reset)
);
logic v_li;
logic [width_p-1:0] a_li;
logic [width_p-1:0] b_li;
logic ready_lo;
logic v_lo;
logic yumi_li;
logic [width_p-1:0] z_lo;
logic unimplemented;
logic invalid;
logic overflow;
logic underflow;
bsg_fpu_mul #(
.e_p(8)
,.m_p(23)
) dut (
.clk_i(clk)
,.reset_i(reset)
,.en_i(1'b1)
,.v_i(v_li)
,.a_i(a_li)
,.b_i(b_li)
,.ready_o(ready_lo)
,.v_o(v_lo)
,.z_o(z_lo)
,.unimplemented_o(unimplemented)
,.invalid_o(invalid)
,.overflow_o(overflow)
,.underflow_o(underflow)
,.yumi_i(yumi_li)
);
logic [ring_width_p-1:0] tr_data_li;
logic tr_ready_lo;
logic tr_v_lo;
logic [ring_width_p-1:0] tr_data_lo;
logic tr_yumi_li;
logic [rom_addr_width_p-1:0] rom_addr;
logic [ring_width_p+4-1:0] rom_data;
logic done_lo;
bsg_fsb_node_trace_replay #(
.ring_width_p(ring_width_p)
,.rom_addr_width_p(rom_addr_width_p)
) tr (
.clk_i(clk)
,.reset_i(reset)
,.en_i(1'b1)
,.v_i(v_lo)
,.data_i(tr_data_li)
,.ready_o(tr_ready_lo)
,.v_o(v_li)
,.data_o(tr_data_lo)
,.yumi_i(tr_yumi_li)
,.rom_addr_o(rom_addr)
,.rom_data_i(rom_data)
,.done_o(done_lo)
,.error_o()
);
bsg_fpu_trace_rom #(
.width_p(ring_width_p+4)
,.addr_width_p(rom_addr_width_p)
) rom (
.addr_i(rom_addr)
,.data_o(rom_data)
);
assign yumi_li = v_lo & tr_ready_lo;
assign tr_yumi_li = v_li & ready_lo;
assign {sub_li, a_li, b_li} = tr_data_lo;
assign tr_data_li = {
{ring_width_p-width_p-4{1'b0}},
unimplemented,
invalid,
overflow,
underflow,
z_lo
};
initial begin
wait(done_lo);
$finish;
end
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:17:38 02/18/2017
// Design Name: bin2sevenSeg
// Module Name: /home/aaron/Git Repos/CSE311/lab3/bin2sevenSeg_tb.v
// Project Name: lab3
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: bin2sevenSeg
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module bin2sevenSeg_tb;
// Inputs
reg clk;
reg [13:0] d_in;
// Outputs
wire [15:0] fullOutput;
wire [3:0] segA;
wire [3:0] segB;
wire [3:0] segC;
wire [3:0] segD;
wire [13:0] d_out;
// Instantiate the Unit Under Test (UUT)
bin2sevenSeg uut (
.clk(clk),
.d_in(d_in),
.fullOutput(fullOutput),
.segA(segA),
.segB(segB),
.segC(segC),
.segD(segD),
.d_out(d_out)
);
initial begin
// Initialize Inputs
clk = 0;
d_in = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
d_in = 4'd11;
end
endmodule
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module FIFO_image_filter_img_3_rows_V_shiftReg (
clk,
data,
ce,
a,
q);
parameter DATA_WIDTH = 32'd12;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd3;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg[DATA_WIDTH-1:0] SRL_SIG [0:DEPTH-1];
integer i;
always @ (posedge clk)
begin
if (ce)
begin
for (i=0;i<DEPTH-1;i=i+1)
SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
module FIFO_image_filter_img_3_rows_V (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd12;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd3;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output[DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input[DATA_WIDTH - 1:0] if_din;
wire[ADDR_WIDTH - 1:0] shiftReg_addr ;
wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
reg[ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH+1){1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @ (posedge clk) begin
if (reset == 1'b1)
begin
mOutPtr <= ~{ADDR_WIDTH+1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr -1;
if (mOutPtr == 0)
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr +1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH-2)
internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
FIFO_image_filter_img_3_rows_V_shiftReg
#(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH))
U_FIFO_image_filter_img_3_rows_V_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q));
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DLXTP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HVL__DLXTP_BEHAVIORAL_PP_V
/**
* dlxtp: Delay latch, non-inverted enable, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v"
`include "../../models/udp_dlatch_p_pp_pg_n/sky130_fd_sc_hvl__udp_dlatch_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hvl__dlxtp (
Q ,
D ,
GATE,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
input D ;
input GATE;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
reg notifier ;
wire buf_Q ;
wire GATE_delayed;
wire D_delayed ;
wire buf0_out_Q ;
// Name Output Other arguments
sky130_fd_sc_hvl__udp_dlatch$P_pp$PG$N dlatch0 (buf_Q , D_delayed, GATE_delayed, notifier, VPWR, VGND);
buf buf0 (buf0_out_Q, buf_Q );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (Q , buf0_out_Q, VPWR, VGND );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DLXTP_BEHAVIORAL_PP_V
|
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: P.20131013
// \ \ Application: netgen
// / / Filename: Amul.v
// /___/ /\ Timestamp: Sun Apr 30 23:51:48 2017
// \ \ / \
// \___\/\___\
//
// Command : -w -sim -ofmt verilog /home/rohith/Image-Watermarking/ipcore_dir/tmp/_cg/Amul.ngc /home/rohith/Image-Watermarking/ipcore_dir/tmp/_cg/Amul.v
// Device : 3s500efg320-5
// Input file : /home/rohith/Image-Watermarking/ipcore_dir/tmp/_cg/Amul.ngc
// Output file : /home/rohith/Image-Watermarking/ipcore_dir/tmp/_cg/Amul.v
// # of Modules : 1
// Design Name : Amul
// Xilinx : /opt/14.7/ISE_DS/ISE/
//
// Purpose:
// This verilog netlist is a verification model and uses simulation
// primitives which may not represent the true implementation of the
// device, however the netlist is functionally correct and should not
// be modified. This file cannot be synthesized and should only be used
// with supported simulation tools.
//
// Reference:
// Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6
//
////////////////////////////////////////////////////////////////////////////////
`timescale 1 ns/1 ps
module Amul (
clk, p, a
)/* synthesis syn_black_box syn_noprune=1 */;
input clk;
output [7 : 0] p;
input [7 : 0] a;
// synthesis translate_off
wire \blk00000001/sig0000002f ;
wire \blk00000001/sig0000002e ;
wire \blk00000001/sig0000002d ;
wire \blk00000001/sig0000002c ;
wire \blk00000001/sig0000002b ;
wire \blk00000001/sig0000002a ;
wire \blk00000001/sig00000029 ;
wire \blk00000001/sig00000028 ;
wire \blk00000001/sig00000027 ;
wire \blk00000001/sig00000026 ;
wire \blk00000001/sig00000025 ;
wire \blk00000001/sig00000024 ;
wire \blk00000001/sig00000023 ;
wire \blk00000001/sig00000022 ;
wire \blk00000001/sig00000021 ;
wire \blk00000001/sig00000020 ;
wire \blk00000001/sig0000001f ;
wire \blk00000001/sig0000001e ;
wire \blk00000001/sig0000001d ;
wire \blk00000001/sig0000001c ;
wire \blk00000001/sig0000001b ;
wire \blk00000001/sig0000001a ;
wire \blk00000001/sig00000019 ;
wire \blk00000001/sig00000018 ;
wire \blk00000001/sig00000017 ;
wire \blk00000001/sig00000016 ;
wire \blk00000001/sig00000015 ;
wire \blk00000001/sig00000014 ;
wire \blk00000001/sig00000013 ;
wire \blk00000001/sig00000012 ;
wire \blk00000001/sig00000011 ;
wire \blk00000001/sig00000010 ;
wire \blk00000001/sig0000000f ;
wire \blk00000001/sig0000000e ;
wire \blk00000001/sig0000000d ;
wire \blk00000001/sig0000000c ;
wire \blk00000001/sig0000000b ;
wire \blk00000001/sig0000000a ;
LUT1 #(
.INIT ( 2'h2 ))
\blk00000001/blk0000002f (
.I0(\blk00000001/sig0000002c ),
.O(\blk00000001/sig00000017 )
);
LUT1 #(
.INIT ( 2'h2 ))
\blk00000001/blk0000002e (
.I0(\blk00000001/sig0000002d ),
.O(\blk00000001/sig00000019 )
);
LUT1 #(
.INIT ( 2'h2 ))
\blk00000001/blk0000002d (
.I0(\blk00000001/sig0000002e ),
.O(\blk00000001/sig0000001b )
);
RAM16X1S #(
.INIT ( 16'h07C0 ))
\blk00000001/blk0000002c (
.A0(a[0]),
.A1(a[1]),
.A2(a[2]),
.A3(a[3]),
.D(\blk00000001/sig0000000a ),
.WCLK(clk),
.WE(\blk00000001/sig0000000a ),
.O(\blk00000001/sig0000000e )
);
RAM16X1S #(
.INIT ( 16'hC738 ))
\blk00000001/blk0000002b (
.A0(a[0]),
.A1(a[1]),
.A2(a[2]),
.A3(a[3]),
.D(\blk00000001/sig0000000a ),
.WCLK(clk),
.WE(\blk00000001/sig0000000a ),
.O(\blk00000001/sig0000000d )
);
RAM16X1S #(
.INIT ( 16'hF800 ))
\blk00000001/blk0000002a (
.A0(a[0]),
.A1(a[1]),
.A2(a[2]),
.A3(a[3]),
.D(\blk00000001/sig0000000a ),
.WCLK(clk),
.WE(\blk00000001/sig0000000a ),
.O(\blk00000001/sig0000000f )
);
RAM16X1S #(
.INIT ( 16'hB4B4 ))
\blk00000001/blk00000029 (
.A0(a[0]),
.A1(a[1]),
.A2(a[2]),
.A3(a[3]),
.D(\blk00000001/sig0000000a ),
.WCLK(clk),
.WE(\blk00000001/sig0000000a ),
.O(\blk00000001/sig0000000c )
);
FDRE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000028 (
.C(clk),
.CE(\blk00000001/sig0000000b ),
.D(\blk00000001/sig0000000f ),
.R(\blk00000001/sig0000000a ),
.Q(\blk00000001/sig00000013 )
);
FDRE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000027 (
.C(clk),
.CE(\blk00000001/sig0000000b ),
.D(\blk00000001/sig0000000e ),
.R(\blk00000001/sig0000000a ),
.Q(\blk00000001/sig00000012 )
);
FDRE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000026 (
.C(clk),
.CE(\blk00000001/sig0000000b ),
.D(\blk00000001/sig0000000d ),
.R(\blk00000001/sig0000000a ),
.Q(\blk00000001/sig00000011 )
);
FDRE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000025 (
.C(clk),
.CE(\blk00000001/sig0000000b ),
.D(\blk00000001/sig0000000c ),
.R(\blk00000001/sig0000000a ),
.Q(\blk00000001/sig00000010 )
);
RAM16X1S #(
.INIT ( 16'h07C0 ))
\blk00000001/blk00000024 (
.A0(a[4]),
.A1(a[5]),
.A2(a[6]),
.A3(a[7]),
.D(\blk00000001/sig0000000a ),
.WCLK(clk),
.WE(\blk00000001/sig0000000a ),
.O(\blk00000001/sig00000028 )
);
RAM16X1S #(
.INIT ( 16'hC738 ))
\blk00000001/blk00000023 (
.A0(a[4]),
.A1(a[5]),
.A2(a[6]),
.A3(a[7]),
.D(\blk00000001/sig0000000a ),
.WCLK(clk),
.WE(\blk00000001/sig0000000a ),
.O(\blk00000001/sig00000027 )
);
RAM16X1S #(
.INIT ( 16'hF800 ))
\blk00000001/blk00000022 (
.A0(a[4]),
.A1(a[5]),
.A2(a[6]),
.A3(a[7]),
.D(\blk00000001/sig0000000a ),
.WCLK(clk),
.WE(\blk00000001/sig0000000a ),
.O(\blk00000001/sig00000029 )
);
RAM16X1S #(
.INIT ( 16'h6666 ))
\blk00000001/blk00000021 (
.A0(a[4]),
.A1(a[5]),
.A2(a[6]),
.A3(a[7]),
.D(\blk00000001/sig0000000a ),
.WCLK(clk),
.WE(\blk00000001/sig0000000a ),
.O(\blk00000001/sig00000025 )
);
RAM16X1S #(
.INIT ( 16'hAAAA ))
\blk00000001/blk00000020 (
.A0(a[4]),
.A1(a[5]),
.A2(a[6]),
.A3(a[7]),
.D(\blk00000001/sig0000000a ),
.WCLK(clk),
.WE(\blk00000001/sig0000000a ),
.O(\blk00000001/sig00000024 )
);
RAM16X1S #(
.INIT ( 16'hB4B4 ))
\blk00000001/blk0000001f (
.A0(a[4]),
.A1(a[5]),
.A2(a[6]),
.A3(a[7]),
.D(\blk00000001/sig0000000a ),
.WCLK(clk),
.WE(\blk00000001/sig0000000a ),
.O(\blk00000001/sig00000026 )
);
FDRE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000001e (
.C(clk),
.CE(\blk00000001/sig0000000b ),
.D(\blk00000001/sig00000029 ),
.R(\blk00000001/sig0000000a ),
.Q(\blk00000001/sig0000002f )
);
FDRE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000001d (
.C(clk),
.CE(\blk00000001/sig0000000b ),
.D(\blk00000001/sig00000028 ),
.R(\blk00000001/sig0000000a ),
.Q(\blk00000001/sig0000002e )
);
FDRE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000001c (
.C(clk),
.CE(\blk00000001/sig0000000b ),
.D(\blk00000001/sig00000027 ),
.R(\blk00000001/sig0000000a ),
.Q(\blk00000001/sig0000002d )
);
FDRE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000001b (
.C(clk),
.CE(\blk00000001/sig0000000b ),
.D(\blk00000001/sig00000026 ),
.R(\blk00000001/sig0000000a ),
.Q(\blk00000001/sig0000002c )
);
FDRE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000001a (
.C(clk),
.CE(\blk00000001/sig0000000b ),
.D(\blk00000001/sig00000025 ),
.R(\blk00000001/sig0000000a ),
.Q(\blk00000001/sig0000002b )
);
FDRE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000019 (
.C(clk),
.CE(\blk00000001/sig0000000b ),
.D(\blk00000001/sig00000024 ),
.R(\blk00000001/sig0000000a ),
.Q(\blk00000001/sig0000002a )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000018 (
.C(clk),
.D(\blk00000001/sig00000010 ),
.Q(p[0])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000017 (
.C(clk),
.D(\blk00000001/sig00000011 ),
.Q(p[1])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000016 (
.C(clk),
.D(\blk00000001/sig0000001e ),
.Q(p[2])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000015 (
.C(clk),
.D(\blk00000001/sig0000001f ),
.Q(p[3])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000014 (
.C(clk),
.D(\blk00000001/sig00000020 ),
.Q(p[4])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000013 (
.C(clk),
.D(\blk00000001/sig00000021 ),
.Q(p[5])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000012 (
.C(clk),
.D(\blk00000001/sig00000022 ),
.Q(p[6])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000011 (
.C(clk),
.D(\blk00000001/sig00000023 ),
.Q(p[7])
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000010 (
.I0(\blk00000001/sig00000012 ),
.I1(\blk00000001/sig0000002a ),
.O(\blk00000001/sig0000001c )
);
MUXCY \blk00000001/blk0000000f (
.CI(\blk00000001/sig0000000a ),
.DI(\blk00000001/sig00000012 ),
.S(\blk00000001/sig0000001c ),
.O(\blk00000001/sig00000014 )
);
XORCY \blk00000001/blk0000000e (
.CI(\blk00000001/sig0000000a ),
.LI(\blk00000001/sig0000001c ),
.O(\blk00000001/sig0000001e )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000000d (
.I0(\blk00000001/sig00000013 ),
.I1(\blk00000001/sig0000002b ),
.O(\blk00000001/sig0000001d )
);
MUXCY \blk00000001/blk0000000c (
.CI(\blk00000001/sig00000014 ),
.DI(\blk00000001/sig00000013 ),
.S(\blk00000001/sig0000001d ),
.O(\blk00000001/sig00000015 )
);
XORCY \blk00000001/blk0000000b (
.CI(\blk00000001/sig00000014 ),
.LI(\blk00000001/sig0000001d ),
.O(\blk00000001/sig0000001f )
);
MUXCY \blk00000001/blk0000000a (
.CI(\blk00000001/sig00000015 ),
.DI(\blk00000001/sig0000000a ),
.S(\blk00000001/sig00000017 ),
.O(\blk00000001/sig00000016 )
);
XORCY \blk00000001/blk00000009 (
.CI(\blk00000001/sig00000015 ),
.LI(\blk00000001/sig00000017 ),
.O(\blk00000001/sig00000020 )
);
MUXCY \blk00000001/blk00000008 (
.CI(\blk00000001/sig00000016 ),
.DI(\blk00000001/sig0000000a ),
.S(\blk00000001/sig00000019 ),
.O(\blk00000001/sig00000018 )
);
XORCY \blk00000001/blk00000007 (
.CI(\blk00000001/sig00000016 ),
.LI(\blk00000001/sig00000019 ),
.O(\blk00000001/sig00000021 )
);
MUXCY \blk00000001/blk00000006 (
.CI(\blk00000001/sig00000018 ),
.DI(\blk00000001/sig0000000a ),
.S(\blk00000001/sig0000001b ),
.O(\blk00000001/sig0000001a )
);
XORCY \blk00000001/blk00000005 (
.CI(\blk00000001/sig00000018 ),
.LI(\blk00000001/sig0000001b ),
.O(\blk00000001/sig00000022 )
);
XORCY \blk00000001/blk00000004 (
.CI(\blk00000001/sig0000001a ),
.LI(\blk00000001/sig0000002f ),
.O(\blk00000001/sig00000023 )
);
VCC \blk00000001/blk00000003 (
.P(\blk00000001/sig0000000b )
);
GND \blk00000001/blk00000002 (
.G(\blk00000001/sig0000000a )
);
// synthesis translate_on
endmodule
// synthesis translate_off
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
// synthesis translate_on
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Wed May 31 03:26:46 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// C:/ZyboIP/examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ip/system_vga_buffer_1_0/system_vga_buffer_1_0_sim_netlist.v
// Design : system_vga_buffer_1_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "system_vga_buffer_1_0,vga_buffer,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "vga_buffer,Vivado 2016.4" *)
(* NotValidForBitStream *)
module system_vga_buffer_1_0
(clk_w,
clk_r,
wen,
x_addr_w,
y_addr_w,
x_addr_r,
y_addr_r,
data_w,
data_r);
(* x_interface_info = "xilinx.com:signal:clock:1.0 clk CLK" *) input clk_w;
input clk_r;
input wen;
input [9:0]x_addr_w;
input [9:0]y_addr_w;
input [9:0]x_addr_r;
input [9:0]y_addr_r;
input [23:0]data_w;
output [23:0]data_r;
wire clk_r;
wire clk_w;
wire [23:0]data_r;
wire [23:0]data_w;
wire wen;
wire [9:0]x_addr_r;
wire [9:0]x_addr_w;
system_vga_buffer_1_0_vga_buffer U0
(.clk_r(clk_r),
.clk_w(clk_w),
.data_r(data_r),
.data_w(data_w),
.wen(wen),
.x_addr_r(x_addr_r),
.x_addr_w(x_addr_w));
endmodule
(* ORIG_REF_NAME = "vga_buffer" *)
module system_vga_buffer_1_0_vga_buffer
(data_r,
clk_w,
clk_r,
wen,
data_w,
x_addr_w,
x_addr_r);
output [23:0]data_r;
input clk_w;
input clk_r;
input wen;
input [23:0]data_w;
input [9:0]x_addr_w;
input [9:0]x_addr_r;
wire [9:0]addr_r;
wire [9:0]addr_w;
wire [9:0]c_addr_r;
wire [9:0]c_addr_w;
wire clk_r;
wire clk_w;
wire [23:0]data_r;
wire [23:0]data_w;
wire wen;
wire [9:0]x_addr_r;
wire [9:0]x_addr_w;
wire NLW_data_reg_CASCADEOUTA_UNCONNECTED;
wire NLW_data_reg_CASCADEOUTB_UNCONNECTED;
wire NLW_data_reg_DBITERR_UNCONNECTED;
wire NLW_data_reg_INJECTDBITERR_UNCONNECTED;
wire NLW_data_reg_INJECTSBITERR_UNCONNECTED;
wire NLW_data_reg_SBITERR_UNCONNECTED;
wire [31:0]NLW_data_reg_DOADO_UNCONNECTED;
wire [31:24]NLW_data_reg_DOBDO_UNCONNECTED;
wire [3:0]NLW_data_reg_DOPADOP_UNCONNECTED;
wire [3:0]NLW_data_reg_DOPBDOP_UNCONNECTED;
wire [7:0]NLW_data_reg_ECCPARITY_UNCONNECTED;
wire [8:0]NLW_data_reg_RDADDRECC_UNCONNECTED;
FDRE \addr_r_reg[0]
(.C(clk_r),
.CE(1'b1),
.D(c_addr_r[0]),
.Q(addr_r[0]),
.R(1'b0));
FDRE \addr_r_reg[1]
(.C(clk_r),
.CE(1'b1),
.D(c_addr_r[1]),
.Q(addr_r[1]),
.R(1'b0));
FDRE \addr_r_reg[2]
(.C(clk_r),
.CE(1'b1),
.D(c_addr_r[2]),
.Q(addr_r[2]),
.R(1'b0));
FDRE \addr_r_reg[3]
(.C(clk_r),
.CE(1'b1),
.D(c_addr_r[3]),
.Q(addr_r[3]),
.R(1'b0));
FDRE \addr_r_reg[4]
(.C(clk_r),
.CE(1'b1),
.D(c_addr_r[4]),
.Q(addr_r[4]),
.R(1'b0));
FDRE \addr_r_reg[5]
(.C(clk_r),
.CE(1'b1),
.D(c_addr_r[5]),
.Q(addr_r[5]),
.R(1'b0));
FDRE \addr_r_reg[6]
(.C(clk_r),
.CE(1'b1),
.D(c_addr_r[6]),
.Q(addr_r[6]),
.R(1'b0));
FDRE \addr_r_reg[7]
(.C(clk_r),
.CE(1'b1),
.D(c_addr_r[7]),
.Q(addr_r[7]),
.R(1'b0));
FDRE \addr_r_reg[8]
(.C(clk_r),
.CE(1'b1),
.D(c_addr_r[8]),
.Q(addr_r[8]),
.R(1'b0));
FDRE \addr_r_reg[9]
(.C(clk_r),
.CE(1'b1),
.D(c_addr_r[9]),
.Q(addr_r[9]),
.R(1'b0));
FDRE \addr_w_reg[0]
(.C(clk_w),
.CE(wen),
.D(c_addr_w[0]),
.Q(addr_w[0]),
.R(1'b0));
FDRE \addr_w_reg[1]
(.C(clk_w),
.CE(wen),
.D(c_addr_w[1]),
.Q(addr_w[1]),
.R(1'b0));
FDRE \addr_w_reg[2]
(.C(clk_w),
.CE(wen),
.D(c_addr_w[2]),
.Q(addr_w[2]),
.R(1'b0));
FDRE \addr_w_reg[3]
(.C(clk_w),
.CE(wen),
.D(c_addr_w[3]),
.Q(addr_w[3]),
.R(1'b0));
FDRE \addr_w_reg[4]
(.C(clk_w),
.CE(wen),
.D(c_addr_w[4]),
.Q(addr_w[4]),
.R(1'b0));
FDRE \addr_w_reg[5]
(.C(clk_w),
.CE(wen),
.D(c_addr_w[5]),
.Q(addr_w[5]),
.R(1'b0));
FDRE \addr_w_reg[6]
(.C(clk_w),
.CE(wen),
.D(c_addr_w[6]),
.Q(addr_w[6]),
.R(1'b0));
FDRE \addr_w_reg[7]
(.C(clk_w),
.CE(wen),
.D(c_addr_w[7]),
.Q(addr_w[7]),
.R(1'b0));
FDRE \addr_w_reg[8]
(.C(clk_w),
.CE(wen),
.D(c_addr_w[8]),
.Q(addr_w[8]),
.R(1'b0));
FDRE \addr_w_reg[9]
(.C(clk_w),
.CE(wen),
.D(c_addr_w[9]),
.Q(addr_w[9]),
.R(1'b0));
FDRE \c_addr_r_reg[0]
(.C(clk_r),
.CE(1'b1),
.D(x_addr_r[0]),
.Q(c_addr_r[0]),
.R(1'b0));
FDRE \c_addr_r_reg[1]
(.C(clk_r),
.CE(1'b1),
.D(x_addr_r[1]),
.Q(c_addr_r[1]),
.R(1'b0));
FDRE \c_addr_r_reg[2]
(.C(clk_r),
.CE(1'b1),
.D(x_addr_r[2]),
.Q(c_addr_r[2]),
.R(1'b0));
FDRE \c_addr_r_reg[3]
(.C(clk_r),
.CE(1'b1),
.D(x_addr_r[3]),
.Q(c_addr_r[3]),
.R(1'b0));
FDRE \c_addr_r_reg[4]
(.C(clk_r),
.CE(1'b1),
.D(x_addr_r[4]),
.Q(c_addr_r[4]),
.R(1'b0));
FDRE \c_addr_r_reg[5]
(.C(clk_r),
.CE(1'b1),
.D(x_addr_r[5]),
.Q(c_addr_r[5]),
.R(1'b0));
FDRE \c_addr_r_reg[6]
(.C(clk_r),
.CE(1'b1),
.D(x_addr_r[6]),
.Q(c_addr_r[6]),
.R(1'b0));
FDRE \c_addr_r_reg[7]
(.C(clk_r),
.CE(1'b1),
.D(x_addr_r[7]),
.Q(c_addr_r[7]),
.R(1'b0));
FDRE \c_addr_r_reg[8]
(.C(clk_r),
.CE(1'b1),
.D(x_addr_r[8]),
.Q(c_addr_r[8]),
.R(1'b0));
FDRE \c_addr_r_reg[9]
(.C(clk_r),
.CE(1'b1),
.D(x_addr_r[9]),
.Q(c_addr_r[9]),
.R(1'b0));
FDRE \c_addr_w_reg[0]
(.C(clk_w),
.CE(wen),
.D(x_addr_w[0]),
.Q(c_addr_w[0]),
.R(1'b0));
FDRE \c_addr_w_reg[1]
(.C(clk_w),
.CE(wen),
.D(x_addr_w[1]),
.Q(c_addr_w[1]),
.R(1'b0));
FDRE \c_addr_w_reg[2]
(.C(clk_w),
.CE(wen),
.D(x_addr_w[2]),
.Q(c_addr_w[2]),
.R(1'b0));
FDRE \c_addr_w_reg[3]
(.C(clk_w),
.CE(wen),
.D(x_addr_w[3]),
.Q(c_addr_w[3]),
.R(1'b0));
FDRE \c_addr_w_reg[4]
(.C(clk_w),
.CE(wen),
.D(x_addr_w[4]),
.Q(c_addr_w[4]),
.R(1'b0));
FDRE \c_addr_w_reg[5]
(.C(clk_w),
.CE(wen),
.D(x_addr_w[5]),
.Q(c_addr_w[5]),
.R(1'b0));
FDRE \c_addr_w_reg[6]
(.C(clk_w),
.CE(wen),
.D(x_addr_w[6]),
.Q(c_addr_w[6]),
.R(1'b0));
FDRE \c_addr_w_reg[7]
(.C(clk_w),
.CE(wen),
.D(x_addr_w[7]),
.Q(c_addr_w[7]),
.R(1'b0));
FDRE \c_addr_w_reg[8]
(.C(clk_w),
.CE(wen),
.D(x_addr_w[8]),
.Q(c_addr_w[8]),
.R(1'b0));
FDRE \c_addr_w_reg[9]
(.C(clk_w),
.CE(wen),
.D(x_addr_w[9]),
.Q(c_addr_w[9]),
.R(1'b0));
(* CLOCK_DOMAINS = "INDEPENDENT" *)
(* \MEM.PORTA.DATA_BIT_LAYOUT = "p0_d24" *)
(* \MEM.PORTB.DATA_BIT_LAYOUT = "p0_d24" *)
(* METHODOLOGY_DRC_VIOS = "{SYNTH-6 {cell *THIS*}}" *)
(* RTL_RAM_BITS = "24576" *)
(* RTL_RAM_NAME = "data" *)
(* bram_addr_begin = "0" *)
(* bram_addr_end = "1023" *)
(* bram_slice_begin = "0" *)
(* bram_slice_end = "23" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(36),
.RSTREG_PRIORITY_A("RSTREG"),
.RSTREG_PRIORITY_B("RSTREG"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("NO_CHANGE"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(36),
.WRITE_WIDTH_B(36))
data_reg
(.ADDRARDADDR({1'b1,addr_w,1'b1,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,addr_r,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b1),
.CASCADEINB(1'b1),
.CASCADEOUTA(NLW_data_reg_CASCADEOUTA_UNCONNECTED),
.CASCADEOUTB(NLW_data_reg_CASCADEOUTB_UNCONNECTED),
.CLKARDCLK(clk_w),
.CLKBWRCLK(clk_r),
.DBITERR(NLW_data_reg_DBITERR_UNCONNECTED),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,data_w}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(NLW_data_reg_DOADO_UNCONNECTED[31:0]),
.DOBDO({NLW_data_reg_DOBDO_UNCONNECTED[31:24],data_r}),
.DOPADOP(NLW_data_reg_DOPADOP_UNCONNECTED[3:0]),
.DOPBDOP(NLW_data_reg_DOPBDOP_UNCONNECTED[3:0]),
.ECCPARITY(NLW_data_reg_ECCPARITY_UNCONNECTED[7:0]),
.ENARDEN(wen),
.ENBWREN(1'b1),
.INJECTDBITERR(NLW_data_reg_INJECTDBITERR_UNCONNECTED),
.INJECTSBITERR(NLW_data_reg_INJECTSBITERR_UNCONNECTED),
.RDADDRECC(NLW_data_reg_RDADDRECC_UNCONNECTED[8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(NLW_data_reg_SBITERR_UNCONNECTED),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O211A_TB_V
`define SKY130_FD_SC_HS__O211A_TB_V
/**
* o211a: 2-input OR into first input of 3-input AND.
*
* X = ((A1 | A2) & B1 & C1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__o211a.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg C1;
reg VPWR;
reg VGND;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
C1 = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 C1 = 1'b0;
#100 VGND = 1'b0;
#120 VPWR = 1'b0;
#140 A1 = 1'b1;
#160 A2 = 1'b1;
#180 B1 = 1'b1;
#200 C1 = 1'b1;
#220 VGND = 1'b1;
#240 VPWR = 1'b1;
#260 A1 = 1'b0;
#280 A2 = 1'b0;
#300 B1 = 1'b0;
#320 C1 = 1'b0;
#340 VGND = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VGND = 1'b1;
#420 C1 = 1'b1;
#440 B1 = 1'b1;
#460 A2 = 1'b1;
#480 A1 = 1'b1;
#500 VPWR = 1'bx;
#520 VGND = 1'bx;
#540 C1 = 1'bx;
#560 B1 = 1'bx;
#580 A2 = 1'bx;
#600 A1 = 1'bx;
end
sky130_fd_sc_hs__o211a dut (.A1(A1), .A2(A2), .B1(B1), .C1(C1), .VPWR(VPWR), .VGND(VGND), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__O211A_TB_V
|
module transmit_test_model (
//input
input clk_100M ,
input reset_n ,
//output
output [7:0] Line_Num ,
output [1:0] Focus_Num,
output Pr_Gate ,
output RX_Gate ,
output End_Gate ,
output Envelop
);
//wire
wire Focus_Num_Pre ;
//reg
reg [31:0] Line_Period ;
reg [31:0] Envelop_Counter ;
reg [31:0] Pulse_Counter ;
reg Pr_Gate_reg ;
reg RX_Gate_reg ;
reg End_Gate_reg ;
reg [1:0] Focus_Num_reg ;
reg Envelop_reg ;
always @(posedge End_Gate_reg)
begin //next foucus
Focus_Num_reg <= Focus_Num_Pre;
end
always @(posedge Pr_Gate_reg)
begin
case(Focus_Num_reg[1:0])
2'b00: //
Line_Period<=32'd12000; //120us
2'b01:
Line_Period<=32'd12000; //120us
2'b10:
Line_Period<=32'd29000; //290us
2'b11:
Line_Period<=32'd29000; //290us
endcase
end
always @(posedge clk_100M or posedge Envelop)
begin
if(Envelop)
begin
Pulse_Counter <= 32'd0;
end
else begin
if(Pulse_Counter < 32'd3000) //30us
begin
Pulse_Counter <= Pulse_Counter + 1'b1;
Pr_Gate_reg <= 1'b1;
RX_Gate_reg <= 1'b0;
End_Gate_reg <= 1'b0;
end
else if(Pulse_Counter < 32'd3250) //2.5us?
begin
Pulse_Counter <= Pulse_Counter + 1'b1;
Pr_Gate_reg <= 1'b0;
RX_Gate_reg <= 1'b1;
End_Gate_reg <= 1'b0;
end
else if(Pulse_Counter < Line_Period)
begin
Pulse_Counter <= Pulse_Counter + 1'b1;
Pr_Gate_reg <= 1'b0;
RX_Gate_reg <= 1'b0;
End_Gate_reg <= 1'b0;
end
else if(Pulse_Counter < (Line_Period + 8'd80)) //0.8us
begin
Pulse_Counter <= Pulse_Counter + 1'b1;
Pr_Gate_reg <= 1'b0;
RX_Gate_reg <= 1'b0;
End_Gate_reg <= 1'b1;
end
else begin
if(Focus_Num_Pre >2'b00)
Pulse_Counter <= 32'd0;
else
Pulse_Counter <= 32'd65536;
Pr_Gate_reg <= 1'b0;
RX_Gate_reg <= 1'b0;
End_Gate_reg <= 1'b0;
end
end
end
always@ (posedge clk_100M or negedge reset_n )
begin
if (!reset_n)
begin
Envelop_reg <= 0 ;
Envelop_Counter <= 0 ;
end
else if (Envelop_Counter < (Line_Period + 8'd90))
begin
Envelop_Counter <= Envelop_Counter + 1'b1;
Envelop_reg <= 1'b0 ;
end
else if (Envelop_Counter >= (Line_Period + 8'd90)&&Envelop_Counter <(Line_Period + 8'd95))
begin
Envelop_Counter <= Envelop_Counter + 1'b1;
Envelop_reg <= 1'b1 ;
end
else
begin
Envelop_reg <= 0 ;
Envelop_Counter <= 0 ;
end
end
cc3200_test_model cc3200_test_model (
//input
.clk_in (clk_100M) ,
.reset_n (reset_n) ,
.RX_Gate (RX_Gate_reg),
.Envelop (Envelop_reg),
//output
.line_num (Line_Num) ,
.focus_num (Focus_Num_Pre)
);
assign Pr_Gate = Pr_Gate_reg ;
assign RX_Gate = RX_Gate_reg ;
assign End_Gate = End_Gate_reg ;
assign Focus_Num = Focus_Num_reg;
assign Envelop = Envelop_reg ;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2016/06/11 11:25:26
// Design Name:
// Module Name: lab5_2_1_tb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module lab5_2_1_tb(
);
reg [1:0] ain;
reg clk,reset;
wire yout;
lab5_2_1 dut(ain,clk,reset,yout);
initial
begin
for(clk = 0;clk >= 0;clk = clk + 1)
begin
#5;
end
end
initial
begin
ain = 0;reset = 1;
#20 reset = 0;
#20 ain = 3;
#10 ain = 2;
#10 ain = 0;
#20 ain = 2;
#10 ain = 0;
#10 ain = 3;
#10 ain = 0;
#10 ain = 1;
#10 ain = 0;
#10 ain = 2;
#10 ain = 3;
#10 ain = 0;
#10 reset = 1;
#10 reset = 0;
#10 ain = 2;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__OR3B_2_V
`define SKY130_FD_SC_HS__OR3B_2_V
/**
* or3b: 3-input OR, first input inverted.
*
* Verilog wrapper for or3b with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__or3b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__or3b_2 (
X ,
A ,
B ,
C_N ,
VPWR,
VGND
);
output X ;
input A ;
input B ;
input C_N ;
input VPWR;
input VGND;
sky130_fd_sc_hs__or3b base (
.X(X),
.A(A),
.B(B),
.C_N(C_N),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__or3b_2 (
X ,
A ,
B ,
C_N
);
output X ;
input A ;
input B ;
input C_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__or3b base (
.X(X),
.A(A),
.B(B),
.C_N(C_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__OR3B_2_V
|
`timescale 1ns/1ns
module Score_tb();
reg RESET;
reg [11:0] SCORE;
wire [6:0] DISP_SU;
wire [6:0] DISP_SD;
wire [6:0] DISP_SC;
wire [6:0] DISP_SM;
Score sc_tb(
.RESET(RESET),
.SCORE(SCORE),
.DISP_SU(DISP_SU),
.DISP_SD(DISP_SD),
.DISP_SC(DISP_SC),
.DISP_SM(DISP_SM)
);
initial begin
RESET=0;
SCORE=0;
$display("==================================//\\\\==================================");
$display("| Testbench Modulo Score |");
$display("==================================\\\\//==================================");
$display("\tTEMPO: %0t // SCORE = 0\n", $time);
#5 RESET=1;
#10 RESET=0;
$display("\tTEMPO: %0t // RESET foi ativado por 10ns\n", $time);
#5 SCORE=9;
#1 $display("\tTEMPO: %0t // SCORE alterado para %d\n\t\tDISP_SM = %b,\n\t\tDISP_SC = %b,\n\t\tDISP_SD = %b,\n\t\tDISP_SU = %b\n", $time, SCORE, DISP_SM, DISP_SC, DISP_SD, DISP_SU);
#10 SCORE=56;
#1 $display("\tTEMPO: %0t // SCORE alterado para %d\n\t\tDISP_SM = %b,\n\t\tDISP_SC = %b,\n\t\tDISP_SD = %b,\n\t\tDISP_SU = %b\n", $time, SCORE, DISP_SM, DISP_SC, DISP_SD, DISP_SU);
#10 SCORE=703;
#1 $display("\tTEMPO: %0t // SCORE alterado para %d\n\t\tDISP_SM = %b,\n\t\tDISP_SC = %b,\n\t\tDISP_SD = %b,\n\t\tDISP_SU = %b\n", $time, SCORE, DISP_SM, DISP_SC, DISP_SD, DISP_SU);
#10 SCORE=2590;
#1 $display("\tTEMPO: %0t // SCORE alterado para %d\n\t\tDISP_SM = %b,\n\t\tDISP_SC = %b,\n\t\tDISP_SD = %b,\n\t\tDISP_SU = %b\n", $time, SCORE, DISP_SM, DISP_SC, DISP_SD, DISP_SU);
#10 SCORE=4095;
#1 $display("\tTEMPO: %0t // SCORE alterado para %d\n\t\tDISP_SM = %b,\n\t\tDISP_SC = %b,\n\t\tDISP_SD = %b,\n\t\tDISP_SU = %b\n", $time, SCORE, DISP_SM, DISP_SC, DISP_SD, DISP_SU);
#10
$display("==================================//\\\\==================================");
$display("| Fim do Testbench |");
$display("==================================\\\\//==================================");
$stop;
end
endmodule
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Nov 13 14:14:55 2016
/////////////////////////////////////////////////////////////
module FPU_Multiplication_Function_W32_EW8_SW23 ( clk, rst, beg_FSM, ack_FSM,
Data_MX, Data_MY, round_mode, overflow_flag, underflow_flag, ready,
final_result_ieee );
input [31:0] Data_MX;
input [31:0] Data_MY;
input [1:0] round_mode;
output [31:0] final_result_ieee;
input clk, rst, beg_FSM, ack_FSM;
output overflow_flag, underflow_flag, ready;
wire zero_flag, FSM_add_overflow_flag, FSM_selector_A, FSM_selector_C,
FSM_selector_B_1_, Exp_module_Overflow_flag_A,
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N11,
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N10,
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N9,
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N8,
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N7,
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N6,
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N5,
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N4,
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N3,
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N2,
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N1,
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N0,
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N13,
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N12,
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N11,
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N10,
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N9,
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N8,
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N8,
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N7,
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N6,
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N5,
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N4,
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N3,
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N1,
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N0,
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N11,
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N10,
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N9,
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N8,
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N7,
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N6,
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N5,
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N4,
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N3,
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N2,
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N1,
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N0,
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N11,
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N10,
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N9,
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N8,
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N7,
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N6,
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N5,
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N4,
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N3,
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N2,
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N1,
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N11,
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N10,
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N9,
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N8,
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N7,
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N6,
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N5,
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N4,
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N3,
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N2,
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N1,
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N0,
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N11,
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N10,
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N9,
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N8,
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N7,
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N6,
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N5,
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N4,
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N3,
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N2,
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N1,
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N0,
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N13,
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N12,
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N11,
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N10,
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N9,
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N8,
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N7,
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N6,
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N5,
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N4,
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N3,
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N2,
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N1,
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N0,
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N13,
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N12,
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N11,
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N10,
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N9,
n167, n169, n170, n171, n172, n173, n174, n175, n176, n177, n178,
n179, n180, n181, n182, n183, n184, n185, n186, n187, n188, n189,
n190, n191, n192, n193, n194, n195, n196, n197, n198, n199, n200,
n201, n202, n203, n209, n214, n215, n216, n217, n218, n219, n220,
n221, n222, n223, n224, n225, n228, n229, n230, n231, n232, n233,
n234, n235, n236, n237, n238, n239, n240, n241, n242, n243, n244,
n245, n246, n247, n248, n249, n250, n251, n262, n263, n264, n265,
n266, n267, n268, n269, n270, n271, n273, n274, n275, n276, n277,
n278, n279, n280, n281, n282, n283, n284, n285, n286, n287, n288,
n289, n290, n291, n292, n293, n294, n295, n296, n297, n298, n299,
n300, n301, n302, n303, n304, n305, n306, n307, n308, n310, n311,
n312, n313, n314, n315, n316, n317, n318, n319, n320, n321, n322,
n323, n324, n325, n326, n327, n328, n329, n330, n331, n332, n333,
n334, n335, n336, n337, n338, n339, n340, n341, n343, n344, n345,
n346, n347, n348, n349, n350, n351, n352, n353, n354, n355, n356,
n357, n358, n359, n360, n361, n362, n363, n364, n365, n366, n367,
n368, n369, n370, n371, n372, n373, n374, n375, n376, n377, n379,
add_x_19_n320, add_x_19_n282, add_x_19_n272, add_x_19_n271,
add_x_19_n268, add_x_19_n265, add_x_19_n257, add_x_19_n252,
add_x_19_n251, add_x_19_n247, add_x_19_n246, add_x_19_n244,
add_x_19_n238, add_x_19_n237, add_x_19_n236, add_x_19_n114,
add_x_19_n106, add_x_19_n104, add_x_19_n95, add_x_19_n94,
add_x_19_n85, add_x_19_n76, add_x_19_n75, add_x_19_n68, add_x_19_n57,
add_x_19_n47, add_x_19_n40, add_x_19_n39, add_x_19_n26, add_x_19_n24,
add_x_19_n23, add_x_19_n22, add_x_19_n21, add_x_19_n20,
DP_OP_156J21_125_3370_n408, DP_OP_156J21_125_3370_n360,
DP_OP_156J21_125_3370_n299, DP_OP_156J21_125_3370_n208,
DP_OP_156J21_125_3370_n205, DP_OP_156J21_125_3370_n204,
DP_OP_156J21_125_3370_n201, DP_OP_156J21_125_3370_n200,
DP_OP_156J21_125_3370_n197, DP_OP_156J21_125_3370_n174,
DP_OP_156J21_125_3370_n173, DP_OP_156J21_125_3370_n168,
DP_OP_156J21_125_3370_n164, DP_OP_156J21_125_3370_n92,
DP_OP_156J21_125_3370_n91, DP_OP_156J21_125_3370_n85,
DP_OP_156J21_125_3370_n84, DP_OP_156J21_125_3370_n83,
DP_OP_156J21_125_3370_n82, DP_OP_156J21_125_3370_n80,
DP_OP_156J21_125_3370_n73, DP_OP_156J21_125_3370_n71,
DP_OP_156J21_125_3370_n70, DP_OP_156J21_125_3370_n66,
DP_OP_156J21_125_3370_n65, DP_OP_156J21_125_3370_n61,
DP_OP_156J21_125_3370_n52, DP_OP_156J21_125_3370_n45,
DP_OP_156J21_125_3370_n36, DP_OP_156J21_125_3370_n33,
DP_OP_156J21_125_3370_n11, DP_OP_156J21_125_3370_n10,
DP_OP_156J21_125_3370_n2, DP_OP_159J21_128_5719_n300,
DP_OP_159J21_128_5719_n294, DP_OP_159J21_128_5719_n262,
DP_OP_159J21_128_5719_n259, DP_OP_159J21_128_5719_n256,
DP_OP_159J21_128_5719_n255, DP_OP_159J21_128_5719_n249,
DP_OP_159J21_128_5719_n248, DP_OP_159J21_128_5719_n246,
DP_OP_159J21_128_5719_n229, DP_OP_154J21_123_2814_n148,
DP_OP_154J21_123_2814_n147, DP_OP_154J21_123_2814_n146,
DP_OP_154J21_123_2814_n144, DP_OP_154J21_123_2814_n136,
DP_OP_154J21_123_2814_n135, DP_OP_154J21_123_2814_n133,
DP_OP_154J21_123_2814_n131, DP_OP_154J21_123_2814_n130,
DP_OP_154J21_123_2814_n129, DP_OP_154J21_123_2814_n128,
DP_OP_154J21_123_2814_n127, DP_OP_154J21_123_2814_n126,
DP_OP_154J21_123_2814_n125, DP_OP_154J21_123_2814_n124,
DP_OP_154J21_123_2814_n123, DP_OP_154J21_123_2814_n122,
DP_OP_154J21_123_2814_n121, DP_OP_154J21_123_2814_n120,
DP_OP_154J21_123_2814_n119, DP_OP_154J21_123_2814_n97,
DP_OP_154J21_123_2814_n94, DP_OP_154J21_123_2814_n93,
DP_OP_154J21_123_2814_n92, DP_OP_154J21_123_2814_n91,
DP_OP_154J21_123_2814_n90, DP_OP_154J21_123_2814_n87,
DP_OP_154J21_123_2814_n84, mult_x_59_a_5_, mult_x_59_a_4_,
mult_x_59_a_3_, mult_x_59_a_0_, mult_x_59_b_5_, mult_x_59_b_4_,
mult_x_59_b_3_, mult_x_59_b_0_, mult_x_59_n64, mult_x_59_n59,
mult_x_59_n58, mult_x_59_n53, mult_x_59_n49, mult_x_59_n48,
mult_x_59_n40, mult_x_59_n37, mult_x_59_n36, mult_x_59_n33,
mult_x_59_n31, mult_x_59_n30, mult_x_59_n29, mult_x_59_n28,
mult_x_59_n27, mult_x_59_n26, mult_x_59_n25, mult_x_59_n24,
mult_x_59_n23, mult_x_59_n22, mult_x_59_n21, mult_x_59_n20,
mult_x_59_n19, mult_x_59_n18, mult_x_59_n17, mult_x_59_n16,
mult_x_59_n15, mult_x_59_n14, mult_x_59_n13, mult_x_59_n8,
mult_x_58_a_5_, mult_x_58_a_4_, mult_x_58_a_0_, mult_x_58_b_5_,
mult_x_58_b_4_, mult_x_58_b_3_, mult_x_58_b_0_, mult_x_58_n64,
mult_x_58_n59, mult_x_58_n58, mult_x_58_n54, mult_x_58_n53,
mult_x_58_n49, mult_x_58_n48, mult_x_58_n43, mult_x_58_n41,
mult_x_58_n40, mult_x_58_n37, mult_x_58_n36, mult_x_58_n33,
mult_x_58_n31, mult_x_58_n30, mult_x_58_n29, mult_x_58_n28,
mult_x_58_n27, mult_x_58_n26, mult_x_58_n25, mult_x_58_n24,
mult_x_58_n23, mult_x_58_n22, mult_x_58_n21, mult_x_58_n20,
mult_x_58_n19, mult_x_58_n18, mult_x_58_n17, mult_x_58_n16,
mult_x_58_n15, mult_x_58_n14, mult_x_58_n13, mult_x_58_n9,
mult_x_57_a_5_, mult_x_57_a_4_, mult_x_57_a_3_, mult_x_57_a_0_,
mult_x_57_b_5_, mult_x_57_b_4_, mult_x_57_b_3_, mult_x_57_b_1_,
mult_x_57_b_0_, mult_x_57_n71, mult_x_57_n69, mult_x_57_n58,
mult_x_57_n55, mult_x_57_n49, mult_x_57_n48, mult_x_57_n45,
mult_x_57_n43, mult_x_57_n41, mult_x_57_n40, mult_x_57_n38,
mult_x_57_n37, mult_x_57_n36, mult_x_57_n35, mult_x_57_n34,
mult_x_57_n32, mult_x_57_n31, mult_x_57_n25, mult_x_57_n24,
mult_x_57_n10, mult_x_56_n75, mult_x_56_n63, mult_x_56_n58,
mult_x_56_n57, mult_x_56_n53, mult_x_56_n52, mult_x_56_n51,
mult_x_56_n50, mult_x_56_n48, mult_x_56_n47, mult_x_56_n43,
mult_x_56_n41, mult_x_56_n40, mult_x_56_n37, mult_x_56_n36,
mult_x_56_n33, mult_x_56_n31, mult_x_56_n30, mult_x_56_n29,
mult_x_56_n28, mult_x_56_n27, mult_x_56_n26, mult_x_56_n25,
mult_x_56_n24, mult_x_56_n23, mult_x_56_n22, mult_x_56_n21,
mult_x_56_n20, mult_x_56_n19, mult_x_56_n18, mult_x_56_n17,
mult_x_56_n16, mult_x_56_n15, mult_x_56_n14, mult_x_56_n13,
mult_x_56_n9, DP_OP_157J21_126_5719_n298, DP_OP_157J21_126_5719_n293,
DP_OP_157J21_126_5719_n261, DP_OP_157J21_126_5719_n258,
DP_OP_157J21_126_5719_n255, DP_OP_157J21_126_5719_n254,
DP_OP_157J21_126_5719_n248, DP_OP_157J21_126_5719_n246,
DP_OP_157J21_126_5719_n229, DP_OP_155J21_124_2814_net275302,
DP_OP_155J21_124_2814_net275301, DP_OP_155J21_124_2814_net274901,
DP_OP_155J21_124_2814_n147, DP_OP_155J21_124_2814_n146,
DP_OP_155J21_124_2814_n145, DP_OP_155J21_124_2814_n144,
DP_OP_155J21_124_2814_n135, DP_OP_155J21_124_2814_n134,
DP_OP_155J21_124_2814_n133, DP_OP_155J21_124_2814_n129,
DP_OP_155J21_124_2814_n128, DP_OP_155J21_124_2814_n127,
DP_OP_155J21_124_2814_n126, DP_OP_155J21_124_2814_n125,
DP_OP_155J21_124_2814_n124, DP_OP_155J21_124_2814_n123,
DP_OP_155J21_124_2814_n122, DP_OP_155J21_124_2814_n121,
DP_OP_155J21_124_2814_n120, DP_OP_155J21_124_2814_n119,
DP_OP_155J21_124_2814_n118, DP_OP_155J21_124_2814_n117,
DP_OP_155J21_124_2814_n97, DP_OP_155J21_124_2814_n94,
DP_OP_155J21_124_2814_n93, DP_OP_155J21_124_2814_n92,
DP_OP_155J21_124_2814_n91, DP_OP_155J21_124_2814_n90,
DP_OP_155J21_124_2814_n88, DP_OP_155J21_124_2814_n87,
DP_OP_155J21_124_2814_n84, DP_OP_155J21_124_2814_n78,
DP_OP_158J21_127_356_n1057, DP_OP_158J21_127_356_n1056,
DP_OP_158J21_127_356_n1053, DP_OP_158J21_127_356_n1050,
DP_OP_158J21_127_356_n1049, DP_OP_158J21_127_356_n1048,
DP_OP_158J21_127_356_n1047, DP_OP_158J21_127_356_n1046,
DP_OP_158J21_127_356_n1045, DP_OP_158J21_127_356_n1044,
DP_OP_158J21_127_356_n1043, DP_OP_158J21_127_356_n1035,
DP_OP_158J21_127_356_n1033, DP_OP_158J21_127_356_n986,
DP_OP_158J21_127_356_n931, DP_OP_158J21_127_356_n895,
DP_OP_158J21_127_356_n894, DP_OP_158J21_127_356_n859,
DP_OP_158J21_127_356_n707, DP_OP_158J21_127_356_n699,
DP_OP_158J21_127_356_n693, DP_OP_158J21_127_356_n692,
DP_OP_158J21_127_356_n690, DP_OP_158J21_127_356_n685,
DP_OP_158J21_127_356_n681, DP_OP_158J21_127_356_n656,
DP_OP_158J21_127_356_n655, DP_OP_158J21_127_356_n654,
DP_OP_158J21_127_356_n653, DP_OP_158J21_127_356_n652,
DP_OP_158J21_127_356_n651, DP_OP_158J21_127_356_n648,
DP_OP_158J21_127_356_n647, DP_OP_158J21_127_356_n646,
DP_OP_158J21_127_356_n645, DP_OP_158J21_127_356_n644,
DP_OP_158J21_127_356_n643, DP_OP_158J21_127_356_n642,
DP_OP_158J21_127_356_n617, DP_OP_158J21_127_356_n615,
DP_OP_158J21_127_356_n614, DP_OP_158J21_127_356_n612,
DP_OP_158J21_127_356_n609, DP_OP_158J21_127_356_n608,
DP_OP_158J21_127_356_n607, DP_OP_158J21_127_356_n599,
DP_OP_158J21_127_356_n411, DP_OP_158J21_127_356_n405,
DP_OP_158J21_127_356_n400, DP_OP_158J21_127_356_n399,
DP_OP_158J21_127_356_n398, DP_OP_158J21_127_356_n397,
DP_OP_158J21_127_356_n388, DP_OP_158J21_127_356_n381,
DP_OP_158J21_127_356_n319, DP_OP_158J21_127_356_n318,
DP_OP_158J21_127_356_n317, DP_OP_158J21_127_356_n314,
DP_OP_158J21_127_356_n312, DP_OP_158J21_127_356_n307,
DP_OP_158J21_127_356_n297, DP_OP_158J21_127_356_n71,
DP_OP_158J21_127_356_n70, DP_OP_158J21_127_356_n63,
DP_OP_158J21_127_356_n62, DP_OP_158J21_127_356_n56,
DP_OP_158J21_127_356_n53, DP_OP_158J21_127_356_n51,
DP_OP_158J21_127_356_n46, DP_OP_158J21_127_356_n44,
DP_OP_158J21_127_356_n38, DP_OP_158J21_127_356_n37,
DP_OP_158J21_127_356_n33, DP_OP_158J21_127_356_n7,
DP_OP_158J21_127_356_n6, DP_OP_158J21_127_356_n5,
DP_OP_158J21_127_356_n4, DP_OP_158J21_127_356_n3,
DP_OP_158J21_127_356_n2, DP_OP_153J21_122_3500_n244,
DP_OP_153J21_122_3500_n243, DP_OP_153J21_122_3500_n195,
DP_OP_153J21_122_3500_n194, DP_OP_153J21_122_3500_n169,
DP_OP_153J21_122_3500_n167, DP_OP_153J21_122_3500_n166,
DP_OP_153J21_122_3500_n127, net286882, net286886, net286911,
net286912, net286913, net286914, net287241, net287247, net287248,
net287451, net287455, net287459, net287462, net287489, net287491,
net287493, net287494, net287495, net287496, net287583, net287633,
net287641, net287652, net287906, net287909, net287910, net288223,
net288224, net288229, net288230, net288236, net288237, net288241,
net288242, net288243, net288247, net288249, net288590, net288595,
net288689, net288731, net288736, net288740, net288745, net288747,
net288757, net288758, net288759, net288763, net288767, net288775,
net288777, net288778, net288781, net288788, net288798, net288802,
net288803, net288806, net288809, net288812, net288813, net288814,
net288815, net288817, net288831, net288832, net288833, net288834,
net288841, net288845, net288847, net290401, net290403, net290404,
net290443, net290453, net291299, net291323, net291361, net291370,
net291396, net291787, net291835, net291904, net291907, net291929,
net291949, net291956, net291992, net292232, net292233, net292476,
net292709, net292731, net292765, net293003, net292178, net288862,
net291594, net287972, net287971, net288858, net287974, net287973,
net292234, net292023, net290827, net288826, net288821, net288819,
net288818, net292367, net292370, net292005, net291953, net291951,
net291950, net288853, net288852, net288824, net288820, net288808,
net293451, net292376, net288828, net288748, net292175, net290421,
net288684, net288678, net288677, mult_x_57_n59, mult_x_57_n53,
mult_x_57_n30, mult_x_57_n29, mult_x_57_n28, mult_x_57_n27,
mult_x_57_n26, mult_x_57_n23, mult_x_57_n22, mult_x_57_n21,
mult_x_57_n20, mult_x_57_n19, mult_x_57_n18, mult_x_57_n17,
mult_x_57_n16, mult_x_57_n15, mult_x_57_n14, mult_x_57_n13, net292780,
net292333, net292332, net292173, net292172, net288594, net288592,
net293459, net290442, net287916, net287250, net287246, net287244,
net293204, net292372, net288756, net288750, net288749, net288742,
net288739, net288738, net288248, net291330, net290615, net290399,
net288235, net288221, net287249, net291630, n401, n402, n403, n404,
n405, n406, n407, n408, n409, n410, n411, n412, n416, n417, n418,
n420, n421, n422, n423, n424, n425, n426, n427, n428, n429, n430,
n431, n432, n433, n435, n436, n437, n438, n439, n440, n441, n442,
n443, n444, n445, n446, n447, n448, n449, n450, n451, n452, n453,
n454, n455, n456, n457, n458, n459, n460, n461, n462, n463, n464,
n465, n466, n467, n468, n469, n470, n471, n472, n473, n474, n475,
n476, n477, n478, n479, n481, n482, n483, n484, n485, n486, n487,
n488, n489, n490, n491, n492, n493, n494, n495, n496, n497, n498,
n499, n500, n501, n502, n503, n504, n505, n506, n507, n508, n509,
n510, n511, n512, n513, n514, n515, n516, n517, n518, n519, n520,
n521, n522, n523, n524, n525, n526, n527, n528, n529, n530, n531,
n532, n533, n534, n535, n536, n537, n538, n539, n540, n541, n542,
n543, n544, n545, n546, n547, n548, n549, n550, n551, n552, n553,
n554, n555, n556, n557, n558, n559, n560, n561, n562, n563, n564,
n565, n566, n567, n568, n569, n570, n571, n572, n573, n574, n575,
n576, n577, n578, n579, n580, n581, n582, n583, n584, n585, n586,
n587, n588, n589, n590, n591, n592, n593, n594, n595, n596, n597,
n598, n599, n600, n601, n602, n603, n604, n605, n606, n607, n608,
n609, n610, n611, n612, n613, n614, n615, n616, n617, n618, n619,
n620, n621, n622, n623, n624, n625, n626, n627, n628, n629, n630,
n631, n632, n633, n634, n635, n636, n637, n638, n639, n640, n641,
n642, n643, n644, n645, n646, n647, n648, n649, n650, n651, n652,
n653, n654, n655, n656, n657, n658, n659, n660, n661, n662, n663,
n664, n665, n666, n667, n668, n669, n670, n671, n672, n673, n674,
n675, n676, n677, n678, n679, n680, n681, n682, n683, n684, n685,
n686, n687, n688, n689, n690, n691, n692, n693, n694, n695, n696,
n697, n698, n699, n700, n701, n702, n703, n704, n705, n706, n707,
n708, n709, n710, n711, n712, n713, n714, n715, n716, n717, n718,
n719, n720, n721, n722, n723, n724, n725, n726, n727, n728, n729,
n730, n731, n732, n733, n734, n735, n736, n737, n738, n739, n740,
n741, n742, n743, n744, n745, n746, n747, n748, n749, n750, n751,
n752, n753, n754, n755, n756, n757, n758, n759, n760, n761, n762,
n763, n764, n765, n766, n767, n768, n769, n770, n771, n772, n774,
n775, n776, n777, n778, n779, n780, n781, n782, n783, n784, n785,
n786, n787, n788, n789, n790, n791, n792, n793, n794, n795, n796,
n797, n798, n799, n800, n801, n802, n803, n804, n805, n806, n807,
n808, n809, n810, n811, n812, n813, n814, n815, n816, n817, n818,
n819, n820, n821, n822, n823, n824, n825, n826, n827, n828, n829,
n830, n831, n832, n833, n834, n835, n836, n837, n838, n839, n840,
n841, n842, n843, n844, n845, n846, n847, n848, n849, n850, n851,
n852, n853, n854, n855, n856, n857, n858, n859, n860, n861, n862,
n863, n864, n865, n866, n867, n868, n869, n870, n871, n872, n873,
n874, n875, n876, n877, n878, n879, n880, n881, n882, n883, n884,
n885, n886, n887, n888, n889, n890, n891, n892, n893, n894, n895,
n896, n897, n898, n899, n900, n901, n902, n903, n904, n905, n906,
n907, n908, n909, n910, n911, n912, n913, n914, n915, n916, n917,
n918, n919, n920, n921, n922, n923, n924, n925, n926, n927, n928,
n929, n930, n931, n932, n933, n934, n935, n936, n937, n938, n939,
n940, n941, n942, n943, n944, n945, n946, n947, n948, n949, n950,
n951, n952, n953, n954, n955, n956, n957, n958, n959, n960, n961,
n962, n963, n964, n965, n966, n967, n968, n969, n970, n971, n972,
n973, n974, n975, n976, n977, n978, n979, n980, n981, n982, n983,
n984, n985, n986, n987, n988, n989, n990, n991, n992, n993, n994,
n995, n996, n997, n998, n999, n1000, n1001, n1002, n1003, n1004,
n1005, n1006, n1007, n1008, n1009, n1010, n1011, n1012, n1013, n1014,
n1015, n1016, n1017, n1018, n1019, n1020, n1021, n1022, n1023, n1024,
n1025, n1026, n1027, n1028, n1029, n1030, n1031, n1032, n1033, n1034,
n1035, n1036, n1037, n1038, n1039, n1040, n1041, n1042, n1043, n1044,
n1045, n1046, n1047, n1048, n1049, n1050, n1051, n1052, n1053, n1054,
n1055, n1056, n1057, n1058, n1059, n1060, n1061, n1062, n1063, n1064,
n1065, n1066, n1067, n1068, n1069, n1070, n1071, n1072, n1073, n1074,
n1075, n1076, n1077, n1078, n1079, n1080, n1081, n1082, n1083, n1084,
n1085, n1086, n1087, n1088, n1089, n1090, n1091, n1092, n1093, n1094,
n1095, n1096, n1097, n1098, n1099, n1100, n1101, n1102, n1103, n1104,
n1105, n1106, n1107, n1108, n1109, n1110, n1111, n1112, n1113, n1114,
n1115, n1116, n1117, n1118, n1119, n1120, n1121, n1122, n1123, n1124,
n1125, n1126, n1127, n1128, n1129, n1130, n1131, n1132, n1133, n1134,
n1135, n1136, n1137, n1138, n1139, n1140, n1141, n1142, n1143, n1144,
n1145, n1146, n1147, n1148, n1149, n1150, n1151, n1152, n1153, n1154,
n1155, n1156, n1157, n1158, n1159, n1160, n1161, n1162, n1163, n1164,
n1165, n1166, n1167, n1168, n1169, n1170, n1171, n1172, n1173, n1174,
n1175, n1176, n1177, n1178, n1179, n1180, n1181, n1182, n1183, n1184,
n1185, n1186, n1187, n1188, n1189, n1190, n1191, n1192, n1193, n1194,
n1195, n1196, n1197, n1198, n1199, n1200, n1201, n1202, n1203, n1204,
n1205, n1206, n1207, n1208, n1209, n1210, n1211, n1212, n1213, n1214,
n1215, n1216, n1217, n1218, n1219, n1220, n1221, n1222, n1223, n1224,
n1225, n1226, n1227, n1228, n1229, n1230, n1231, n1232, n1233, n1234,
n1235, n1236, n1237, n1238, n1239, n1240, n1241, n1242, n1243, n1244,
n1245, n1246, n1247, n1248, n1249, n1250, n1251, n1252, n1253, n1254,
n1255, n1256, n1257, n1258, n1259, n1260, n1261, n1262, n1263, n1264,
n1265, n1266, n1267, n1268, n1269, n1270, n1271, n1272, n1273, n1274,
n1275, n1276, n1277, n1278, n1279, n1280, n1281, n1282, n1283, n1284,
n1285, n1286, n1287, n1288, n1289, n1290, n1291, n1292, n1293, n1294,
n1295, n1296, n1297, n1298, n1299, n1300, n1301, n1302, n1303, n1304,
n1305, n1306, n1307, n1308, n1309, n1310, n1311, n1312, n1313, n1314,
n1315, n1316, n1317, n1318, n1319, n1320, n1321, n1322, n1323, n1324,
n1325, n1326, n1327, n1328, n1329, n1330, n1331, n1332, n1333, n1334,
n1335, n1336, n1337, n1338, n1339, n1340, n1341, n1342, n1343, n1344,
n1345, n1346, n1347, n1348, n1349, n1350, n1351, n1352, n1353, n1354,
n1355, n1356, n1357, n1358, n1359, n1360, n1361, n1362, n1363, n1364,
n1365, n1366, n1367, n1368, n1369, n1370, n1371, n1372, n1373, n1374,
n1375, n1376, n1377, n1378, n1379, n1380, n1381, n1382, n1383, n1384,
n1385, n1386, n1387, n1388, n1389, n1390, n1391, n1392, n1393, n1394,
n1395, n1396, n1397, n1398, n1399, n1400, n1401, n1402, n1403, n1404,
n1405, n1406, n1407, n1408, n1409, n1410, n1411, n1412, n1413, n1414,
n1415, n1416, n1417, n1418, n1419, n1420, n1421, n1422, n1423, n1424,
n1425, n1426, n1427, n1428, n1429, n1430, n1431, n1432, n1433, n1434,
n1435, n1436, n1437, n1438, n1439, n1440, n1441, n1442, n1443, n1444,
n1445, n1446, n1447, n1449, n1450, n1451, n1452, n1453, n1454, n1455,
n1456, n1457, n1458, n1459, n1460, n1461, n1462, n1463, n1464, n1465,
n1466, n1467, n1468, n1469, n1470, n1471, n1472, n1473, n1474, n1475,
n1476, n1477, n1478, n1479, n1480, n1481, n1482, n1483, n1484, n1485,
n1486, n1487, n1488, n1489, n1490, n1491, n1492, n1493, n1494, n1495,
n1496, n1497, n1498, n1499, n1500, n1501, n1502, n1503, n1504, n1505,
n1506, n1507, n1508, n1509, n1510, n1511, n1512, n1513, n1514, n1515,
n1516, n1517, n1518, n1519, n1520, n1521, n1522, n1523, n1524, n1525,
n1526, n1527, n1528, n1529, n1530, n1531, n1532, n1533, n1534, n1535,
n1536, n1537, n1538, n1539, n1540, n1541, n1542, n1543, n1544, n1545,
n1546, n1547, n1548, n1549, n1550, n1551, n1552, n1553, n1554, n1555,
n1556, n1557, n1558, n1559, n1560, n1561, n1562, n1563, n1564, n1565,
n1566, n1567, n1568, n1569, n1570, n1571, n1572, n1573, n1574, n1575,
n1576, n1577, n1578, n1579, n1580, n1581, n1582, n1583, n1584, n1585,
n1586, n1587, n1588, n1589, n1590, n1591, n1592, n1593, n1594, n1595,
n1596, n1597, n1598, n1599, n1600, n1601, n1602, n1603, n1604, n1605,
n1606, n1607, n1608, n1609, n1610, n1611, n1612, n1613, n1614, n1615,
n1616, n1617, n1618, n1619, n1620, n1621, n1622, n1623, n1624, n1625,
n1626, n1627, n1628, n1629, n1630, n1631, n1632, n1633, n1634, n1635,
n1636, n1637, n1638, n1639, n1640, n1641, n1642, n1643, n1644, n1645,
n1646, n1647, n1648, n1649, n1650, n1651, n1652, n1653, n1654, n1655,
n1656, n1657, n1658, n1659, n1660, n1661, n1662, n1663, n1664, n1665,
n1666, n1667, n1668, n1669, n1670, n1671, n1672, n1673, n1674, n1675,
n1676, n1677, n1678, n1679, n1680, n1681, n1682, n1683, n1684, n1685,
n1686, n1687, n1688, n1689, n1690, n1691, n1692, n1693, n1694, n1695,
n1696, n1697, n1698, n1699, n1700, n1701, n1702, n1703, n1704, n1705,
n1706, n1707, n1708, n1709, n1710, n1711, n1712, n1713, n1714, n1715,
n1716, n1717, n1718, n1719, n1720, n1721, n1722, n1723, n1724, n1725,
n1726, n1727, n1728, n1729, n1730, n1731, n1732, n1733, n1734, n1735,
n1736, n1737, n1738, n1739, n1740, n1741, n1742, n1743, n1744, n1745,
n1746, n1747, n1748, n1749, n1750, n1751, n1752, n1753, n1754, n1755,
n1756, n1757, n1758, n1759, n1760, n1761, n1762, n1763, n1764, n1765,
n1766, n1767, n1768, n1769, n1770, n1771, n1772, n1773, n1774, n1775,
n1776, n1777, n1778, n1779, n1780, n1781, n1782, n1783, n1784, n1785,
n1786, n1787, n1788, n1789, n1790, n1791, n1792, n1793, n1794, n1795,
n1796, n1797, n1798, n1799, n1800, n1801, n1802, n1803, n1804, n1805,
n1806, n1807, n1808, n1809, n1810, n1811, n1812, n1813, n1814, n1815,
n1816, n1817, n1818, n1819, n1820, n1821, n1822, n1823, n1824, n1825,
n1826, n1827, n1828, n1829, n1830, n1831, n1832, n1833, n1834, n1835,
n1836, n1837, n1838, n1839, n1840, n1841, n1842, n1843, n1844, n1845,
n1846, n1847, n1848, n1849, n1850, n1851, n1852, n1853, n1854, n1855,
n1856, n1857, n1858, n1859, n1860, n1861, n1862, n1863, n1864, n1865,
n1866, n1867, n1868, n1869, n1870, n1871, n1872, n1873, n1874, n1875,
n1876, n1877, n1878, n1879, n1880, n1881, n1882, n1883, n1884, n1885,
n1886, n1887, n1888, n1889, n1890, n1891, n1892, n1893, n1894, n1895,
n1896, n1897, n1898, n1899, n1900, n1901, n1902, n1903, n1904, n1905,
n1906, n1907, n1908, n1909, n1910, n1911, n1912, n1913, n1914, n1915,
n1916, n1917, n1918, n1919, n1920, n1921, n1922, n1923, n1924, n1925,
n1926, n1927, n1928, n1929, n1930, n1931, n1932, n1933, n1934, n1935,
n1936, n1937, n1938, n1939, n1940, n1941, n1942, n1943, n1944, n1945,
n1946, n1947, n1948, n1949, n1950, n1951, n1952, n1953, n1954, n1955,
n1956, n1957, n1958, n1959, n1960, n1961, n1962, n1963, n1964, n1965,
n1966, n1967, n1968, n1969, n1970, n1971, n1972, n1973, n1974, n1975,
n1976, n1977, n1978, n1979, n1980, n1981, n1982, n1983, n1984, n1985,
n1986, n1987, n1988, n1989, n1990, n1991, n1992, n1993, n1994, n1995,
n1996, n1997, n1998, n1999, n2000, n2001, n2002, n2003, n2004, n2005,
n2006, n2007, n2008, n2009, n2010, n2011, n2012, n2013, n2014, n2015,
n2016, n2017, n2018, n2019, n2020, n2021, n2022, n2023, n2024, n2025,
n2026, n2027, n2028, n2029, n2030, n2031, n2032, n2033, n2034, n2035,
n2036, n2037, n2038, n2039, n2040, n2041, n2042, n2043, n2044, n2045,
n2046, n2047, n2048, n2049, n2050, n2051, n2052, n2053, n2054, n2055,
n2056, n2057, n2058, n2059, n2060, n2061, n2062, n2063, n2064, n2065,
n2066, n2067, n2068, n2069, n2070, n2071, n2072, n2073, n2074, n2075,
n2076, n2077, n2078, n2079, n2080, n2081, n2082, n2083, n2084, n2085,
n2086, n2087, n2088, n2089, n2090, n2091, n2092, n2093, n2094, n2095,
n2096, n2097, n2098, n2099, n2100, n2101, n2102, n2103, n2104, n2105,
n2106, n2107, n2108, n2109, n2110, n2111, n2112, n2113, n2114, n2115,
n2116, n2117, n2118, n2119, n2120, n2121, n2122, n2123, n2124, n2125,
n2126, n2127, n2128, n2129, n2130, n2131, n2132, n2133, n2134, n2135,
n2136, n2137, n2138, n2139, n2140, n2141, n2142, n2143, n2144, n2145,
n2146, n2147, n2148, n2149, n2150, n2151, n2152, n2153, n2154, n2155,
n2156, n2157, n2158, n2159, n2160, n2161, n2162, n2163, n2164, n2165,
n2166, n2167, n2168, n2169, n2170, n2171, n2172, n2173, n2174, n2175,
n2176, n2177, n2178, n2179, n2180, n2181, n2182, n2183, n2184, n2185,
n2186, n2187, n2188, n2189, n2190, n2191, n2192, n2193, n2194, n2195,
n2196, n2197, n2198, n2199, n2200, n2201, n2202, n2203, n2204, n2205,
n2206, n2207, n2208, n2209, n2210, n2211, n2212, n2213, n2214, n2215,
n2216, n2217, n2218, n2219, n2220, n2221, n2222, n2223, n2224, n2225,
n2226, n2227, n2228, n2229, n2230, n2231, n2232, n2233, n2234, n2235,
n2236, n2237, n2238, n2239, n2240, n2241, n2242, n2243, n2244, n2245,
n2246, n2247, n2248, n2249, n2250, n2251, n2252, n2253, n2254, n2255,
n2256, n2257, n2258, n2259, n2260, n2261, n2262, n2263, n2264, n2265,
n2266, n2267, n2268, n2269, n2270, n2271, n2272, n2273, n2274, n2275,
n2276, n2277, n2278, n2279, n2280, n2281, n2282, n2283, n2284, n2285,
n2286, n2287, n2288, n2289, n2290, n2291, n2292, n2293, n2294, n2295,
n2296, n2297, n2298, n2299, n2300, n2301, n2302, n2303, n2304, n2305,
n2306, n2307, n2308, n2309, n2310, n2311, n2312, n2313, n2314, n2315,
n2316, n2317, n2318, n2319, n2320, n2321, n2322, n2323, n2324, n2325,
n2326, n2327, n2328, n2329, n2330, n2331, n2332, n2333, n2334, n2335,
n2336, n2337, n2338, n2339, n2340, n2341, n2342, n2343, n2344, n2345,
n2346, n2347, n2348, n2349, n2350, n2351, n2352, n2353, n2354, n2355,
n2356, n2357, n2358, n2359, n2360, n2361, n2362, n2363, n2364, n2365,
n2366, n2367, n2368, n2369, n2370, n2371, n2372, n2373, n2374, n2375,
n2376, n2377, n2378, n2379, n2380, n2381, n2382, n2383, n2384, n2385,
n2386, n2387, n2388, n2389, n2390, n2391, n2392, n2393, n2394, n2395,
n2396, n2397, n2398, n2399, n2400, n2401, n2402, n2403, n2404, n2405,
n2406, n2407, n2408, n2409, n2410, n2411, n2412, n2413, n2414, n2415,
n2416, n2417, n2418, n2419, n2420, n2421, n2422, n2423, n2424, n2425,
n2426, n2427, n2428, n2429, n2430, n2431, n2432, n2433, n2434, n2435,
n2436, n2437, n2438, n2439, n2440, n2441, n2442, n2443, n2444, n2445,
n2446, n2447, n2448, n2449, n2450, n2451, n2452, n2453, n2454, n2455,
n2456, n2457, n2458, n2459, n2460, n2461, n2462, n2463, n2464, n2465,
n2466, n2467, n2468, n2469, n2470, n2471, n2472, n2473, n2474, n2475,
n2476, n2477, n2478, n2479, n2480, n2481, n2482, n2483, n2484, n2485,
n2486, n2487, n2488, n2489, n2490, n2491, n2492, n2493, n2494, n2495,
n2496, n2497, n2498, n2499, n2500, n2501, n2502, n2503, n2504, n2505,
n2506, n2507, n2508, n2509, n2510, n2511, n2512, n2513, n2514, n2515,
n2516, n2517, n2518, n2519, n2520, n2521, n2522, n2523, n2524, n2525,
n2526, n2527, n2528, n2529, n2530, n2531, n2532, n2533, n2534, n2535,
n2536, n2537, n2538, n2539, n2540, n2541, n2542, n2543, n2544, n2545,
n2546, n2547, n2548, n2549, n2550, n2551, n2552, n2553, n2554, n2555,
n2556, n2557, n2558, n2559, n2560, n2561, n2562, n2563, n2564, n2565,
n2566, n2567, n2568, n2569, n2570, n2571, n2572, n2573, n2574, n2575,
n2576, n2577, n2578, n2579, n2580, n2581, n2582, n2583, n2584, n2585,
n2586, n2587, n2588, n2589, n2590, n2591, n2592, n2593, n2594, n2595,
n2596, n2597, n2598, n2599, n2600, n2601, n2602, n2603, n2604, n2605,
n2606, n2607, n2608, n2609, n2610, n2611, n2612, n2613, n2614, n2615,
n2616, n2617, n2618, n2619, n2620, n2621, n2622, n2623, n2624, n2625,
n2626, n2627, n2628, n2629, n2630, n2631, n2632, n2633, n2634, n2635,
n2636, n2637, n2638, n2639, n2640, n2641, n2642, n2643, n2644, n2645,
n2646, n2647, n2648, n2649, n2650, n2651, n2652, n2653, n2654, n2655,
n2656, n2657, n2658, n2659, n2660, n2661, n2662, n2663, n2664, n2665,
n2666, n2667, n2668, n2669, n2670, n2671, n2672, n2673, n2674, n2675,
n2676, n2677, n2678, n2679, n2680, n2681, n2682, n2683, n2684, n2685,
n2686, n2687, n2688, n2689, n2690, n2691, n2692, n2693, n2694, n2695,
n2696, n2697, n2698, n2699, n2700, n2701, n2702, n2703, n2704, n2705,
n2706, n2707, n2708, n2709, n2710, n2711, n2712, n2713, n2714, n2715,
n2716, n2717, n2718, n2719, n2720, n2721, n2722, n2723, n2724, n2725,
n2726, n2727, n2728, n2729, n2730, n2731, n2732, n2733, n2734, n2735,
n2736, n2737, n2738, n2739, n2740, n2741, n2742, n2743, n2744, n2745,
n2746, n2747, n2748, n2749, n2750, n2751, n2752, n2753, n2754, n2755,
n2756, n2757, n2758, n2759, n2760, n2761, n2762, n2763, n2764, n2765,
n2766, n2767, n2768, n2769, n2770, n2771, n2772, n2773, n2774, n2775,
n2776, n2777, n2778, n2779, n2780, n2781, n2782, n2783, n2784, n2785,
n2786, n2787, n2788, n2789, n2790, n2791, n2792, n2793, n2794, n2795,
n2796, n2797, n2798, n2799, n2800, n2801, n2802, n2803, n2804, n2805,
n2806, n2807, n2808, n2809, n2810, n2811, n2812, n2813, n2814, n2815,
n2816, n2817, n2818, n2819, n2820, n2821, n2822, n2823, n2824, n2825,
n2826, n2827, n2828, n2829, n2830, n2831, n2832, n2833, n2834, n2835,
n2836, n2837, n2838, n2839, n2840, n2841, n2842, n2843, n2844, n2845,
n2846, n2847, n2848, n2849, n2850, n2851, n2852, n2853, n2854, n2855,
n2856, n2857, n2858, n2859, n2860, n2861, n2862, n2863, n2864, n2865,
n2866, n2867, n2868, n2869, n2870, n2871, n2872, n2873, n2874, n2875,
n2876, n2877, n2878, n2879, n2880, n2881, n2882, n2883, n2884, n2885,
n2886, n2887, n2888, n2889, n2890, n2891, n2892, n2893, n2894, n2895,
n2896, n2897, n2898, n2899, n2900, n2901, n2902, n2903, n2904, n2905,
n2906, n2907, n2908, n2909, n2910, n2911, n2912, n2913, n2914, n2915,
n2916, n2917, n2918, n2919, n2920, n2921, n2922, n2923, n2924, n2925,
n2926, n2927, n2928, n2929, n2930, n2931, n2932, n2933, n2934, n2935,
n2936, n2937, n2938, n2939, n2940, n2941, n2942, n2943, n2944, n2945,
n2946, n2947, n2948, n2949, n2950, n2951, n2952, n2953, n2954, n2955,
n2956, n2957, n2958, n2959, n2960, n2961, n2962, n2963, n2964, n2965,
n2966, n2967, n2968, n2969, n2970, n2971, n2972, n2973, n2974, n2975,
n2976, n2977, n2978, n2979, n2980, n2981, n2982, n2983, n2984, n2985,
n2986, n2987, n2988, n2989, n2990, n2991, n2992, n2993, n2994, n2995,
n2996, n2997, n2998, n2999, n3000, n3001, n3002, n3003, n3004, n3005,
n3006, n3007, n3008, n3009, n3010, n3011, n3012, n3013, n3014, n3015,
n3016, n3017, n3018, n3019, n3020, n3021, n3022, n3023, n3024, n3025,
n3026, n3027, n3028, n3029, n3030, n3031, n3032, n3033, n3034, n3035,
n3036, n3037, n3038, n3039, n3040, n3041, n3042, n3043, n3044, n3045,
n3046, n3047, n3048, n3049, n3050, n3051, n3052, n3053, n3054, n3055,
n3056, n3057, n3058, n3059, n3060, n3061, n3062, n3063, n3064, n3065,
n3066, n3067, n3068, n3069, n3070, n3071, n3072, n3073, n3074, n3075,
n3076, n3077, n3078, n3079, n3080, n3081, n3082, n3083, n3084, n3085,
n3086, n3087, n3088, n3089, n3090, n3091, n3092, n3093, n3094, n3095,
n3096, n3097, n3098, n3099, n3100, n3101, n3102, n3103, n3104, n3105,
n3106, n3107, n3108, n3109, n3110, n3111, n3112, n3113, n3114, n3115,
n3116, n3117, n3118, n3119, n3120, n3121, n3122, n3123, n3124, n3125,
n3126, n3127, n3128, n3129, n3130, n3131, n3132, n3133, n3134, n3135,
n3136, n3137, n3138, n3139, n3140, n3141, n3142, n3143, n3144, n3145,
n3146, n3147, n3148, n3149, n3150, n3151, n3152, n3153, n3154, n3155,
n3156, n3157, n3158, n3159, n3160, n3161, n3162, n3163, n3164, n3165,
n3166, n3167, n3168, n3169, n3170, n3171, n3172, n3173, n3174, n3175,
n3176, n3177, n3178, n3179, n3180, n3181, n3182, n3183, n3184, n3185,
n3186, n3187, n3188, n3189, n3190, n3191, n3192, n3193, n3194, n3195,
n3196, n3197, n3198, n3199, n3200, n3201, n3202, n3203, n3204, n3205,
n3206, n3207, n3208, n3209, n3210, n3211, n3212, n3213, n3214, n3215,
n3216, n3217, n3218, n3219, n3220, n3221, n3222, n3223, n3224, n3225,
n3226, n3227, n3228, n3229, n3230, n3231, n3232, n3233, n3234, n3235,
n3236, n3237, n3238, n3239, n3240, n3241, n3242, n3243, n3244, n3245,
n3246, n3247, n3248, n3249, n3250, n3251, n3252, n3253, n3254, n3255,
n3256, n3257, n3258, n3259, n3260, n3261, n3262, n3263, n3264, n3265,
n3266, n3267, n3268, n3269, n3270, n3271, n3272, n3273, n3274, n3275,
n3276, n3277, n3278, n3279, n3280, n3281, n3282, n3283, n3284, n3285,
n3286, n3287, n3288, n3289, n3290, n3291, n3292, n3293, n3294, n3295,
n3296, n3297, n3298, n3299, n3300, n3301, n3302, n3303, n3304, n3305,
n3306, n3307, n3308, n3309, n3310, n3311, n3312, n3313, n3314, n3315,
n3316, n3317, n3318, n3319, n3320, n3321, n3322, n3323, n3324, n3325,
n3326, n3327, n3328, n3329, n3330, n3331, n3332, n3333, n3334, n3335,
n3336, n3337, n3338, n3339, n3340, n3341, n3342, n3343, n3344, n3345,
n3346, n3347, n3348, n3349, n3350, n3351, n3352, n3353, n3354, n3355,
n3356, n3357, n3358, n3359, n3360, n3361, n3362, n3363, n3364, n3365,
n3366, n3367, n3368, n3369, n3370, n3371, n3372, n3373, n3374, n3375,
n3376, n3377, n3378, n3379, n3380, n3381, n3382, n3383, n3384, n3385,
n3386, n3387, n3388, n3389, n3390, n3391, n3392, n3393, n3394, n3395,
n3396, n3397, n3398, n3399, n3400, n3401, n3402, n3403, n3404, n3405,
n3406, n3407, n3408, n3409, n3410, n3411, n3412, n3413, n3414, n3415,
n3416, n3417, n3418, n3419, n3420, n3421, n3422, n3423, n3424, n3425,
n3426, n3427, n3428, n3429, n3430, n3431, n3432, n3433, n3434, n3435,
n3436, n3437, n3438, n3439, n3440, n3441, n3442, n3443, n3444, n3445,
n3446, n3447, n3448, n3449, n3450, n3451, n3452, n3453, n3454, n3455,
n3456, n3457, n3458, n3459, n3460, n3461, n3462, n3463, n3464, n3465,
n3466, n3467, n3468, n3469, n3470, n3471, n3472, n3473, n3474, n3475,
n3476, n3477, n3478, n3479, n3480, n3481, n3482, n3483, n3484, n3485,
n3486, n3487, n3488, n3489, n3490, n3491, n3492, n3493, n3494, n3495,
n3496, n3497, n3498, n3499, n3500, n3501, n3502, n3503, n3504, n3505,
n3506, n3507, n3508, n3509, n3510, n3511, n3512, n3513, n3514, n3515,
n3516, n3517, n3518, n3519, n3520, n3521, n3522, n3523, n3524, n3525,
n3526, n3527, n3528, n3529, n3530, n3531, n3532, n3533, n3534, n3535,
n3536, n3537, n3538, n3539, n3540, n3541, n3542, n3543, n3544, n3545,
n3546, n3547, n3548, n3549, n3550, n3551, n3552, n3553, n3554, n3555,
n3556, n3557, n3558, n3559, n3560, n3561, n3562, n3563, n3564, n3565,
n3566, n3567, n3568, n3569, n3570, n3571, n3572, n3573, n3574, n3575,
n3576, n3577, n3578, n3579, n3580, n3581, n3582, n3583, n3584, n3585,
n3586, n3587, n3588, n3589, n3590, n3591, n3592, n3593, n3594, n3595,
n3596, n3597, n3598, n3599, n3600, n3601, n3602, n3603, n3604, n3605,
n3606, n3607, n3608, n3609, n3610, n3611, n3612, n3613, n3614, n3615,
n3616, n3617, n3618, n3619, n3620, n3621, n3622, n3623, n3624, n3625,
n3626, n3627, n3628, n3629, n3630, n3631, n3632, n3633, n3634, n3635,
n3636, n3637, n3638, n3639, n3640, n3641, n3642, n3643, n3644, n3645,
n3646, n3647, n3648, n3649, n3650, n3651, n3652, n3653, n3654, n3655,
n3656, n3657, n3658, n3659, n3660, n3661, n3662, n3663, n3664, n3665,
n3666, n3667, n3668, n3669, n3670, n3671, n3672, n3673, n3674, n3675,
n3676, n3677, n3678, n3679, n3680, n3681, n3682, n3683, n3684, n3685,
n3686, n3687, n3688, n3689, n3690, n3691, n3692, n3693, n3694, n3695,
n3696, n3697, n3698, n3699, n3700, n3701, n3702, n3703, n3704, n3705,
n3706, n3707, n3708, n3709, n3710, n3711, n3712, n3713, n3714, n3715,
n3716, n3717, n3718, n3719, n3720, n3721, n3722, n3723, n3724, n3725,
n3726, n3727, n3728, n3729, n3730, n3731, n3732, n3733, n3734, n3735,
n3736, n3737, n3738, n3739, n3740, n3741, n3742, n3743, n3744, n3745,
n3746, n3747, n3748, n3749, n3750, n3751, n3752, n3753, n3754, n3755,
n3756, n3757, n3758, n3759, n3760, n3761, n3762, n3763, n3764, n3765,
n3766, n3767, n3768, n3769, n3770, n3771, n3772, n3773, n3774, n3775,
n3776, n3777, n3778, n3779, n3780, n3781, n3782, n3783, n3784, n3785,
n3786, n3787, n3788, n3789, n3790, n3791, n3792, n3793, n3794, n3795,
n3796, n3797, n3798, n3799, n3800, n3801, n3802, n3803, n3804, n3805,
n3806, n3807, n3808, n3809, n3810, n3811, n3812, n3813, n3814, n3815,
n3816, n3817, n3818, n3819, n3820, n3821, n3822, n3823, n3824, n3825,
n3826, n3827, n3828, n3829, n3830, n3831, n3832, n3833, n3834, n3835,
n3836, n3837, n3838, n3839, n3840, n3841, n3842, n3843, n3844, n3845,
n3846, n3847, n3848, n3849, n3850, n3851, n3852, n3853, n3854, n3855,
n3856, n3857, n3858, n3859, n3860, n3861, n3862, n3863, n3864, n3865,
n3866, n3867, n3868, n3869, n3870, n3871, n3872, n3873, n3874, n3875,
n3876, n3877, n3878, n3879, n3880, n3881, n3882, n3883, n3884, n3885,
n3886, n3887, n3888, n3889, n3890, n3891, n3892, n3893, n3894, n3895,
n3896, n3897, n3898, n3899, n3900, n3901, n3902, n3903, n3904, n3905,
n3906, n3907, n3908, n3909, n3910, n3911, n3912, n3913, n3914, n3915,
n3916, n3917, n3918, n3919, n3920, n3921, n3922, n3923, n3924, n3925,
n3926, n3927, n3928, n3929, n3930, n3931, n3932, n3933, n3934, n3935,
n3936, n3937, n3938, n3939, n3940, n3941, n3942, n3943, n3944, n3945,
n3946, n3947, n3948, n3949, n3950, n3951, n3952, n3953, n3954, n3955,
n3956, n3957, n3958, n3959, n3960, n3961, n3962, n3963, n3964, n3965,
n3966, n3967, n3968, n3969, n3970, n3971, n3972, n3973, n3974, n3975,
n3976, n3977, n3978, n3979, n3980, n3981, n3982, n3983, n3984, n3985,
n3986, n3987, n3988, n3989, n3990, n3991, n3992, n3993, n3994, n3995,
n3996, n3997, n3998, n3999, n4000, n4001, n4002, n4003, n4004, n4005,
n4006, n4007, n4008, n4009, n4010, n4011, n4012, n4013, n4014, n4015,
n4017, n4018, n4020, n4026, n4027, n4028, n4029, n4030, n4031, n4032,
n4033, n4034, n4035, n4036, n4037, n4038, n4039, n4040, n4041, n4042,
n4043, n4044, n4045, n4046, n4047, n4048, n4049, n4050, n4051, n4052,
n4053, n4054, n4055, n4056, n4057, n4058, n4059, n4060, n4061, n4062,
n4063, n4064, n4065, n4066, n4067, n4068, n4069, n4070, n4071, n4072,
n4073, n4074, n4075, n4076, n4077, n4078, n4079, n4080, n4081, n4082,
n4083, n4084, n4085, n4086, n4087, n4088, n4089, n4090, n4091, n4092,
n4093, n4094, n4095, n4096, n4097, n4098, n4099, n4100, n4101, n4102,
n4103, n4104, n4105, n4106, n4107, n4108, n4109, n4110, n4111, n4112,
n4113, n4114, n4115, n4116, n4117, n4118, n4119, n4120, n4121, n4122,
n4123, n4124, n4125, n4126, n4127, n4128, n4129, n4130, n4131, n4132,
n4133, n4134, n4135, n4136, n4137, n4138, n4139, n4140, n4141, n4142,
n4143, n4144, n4145, n4146, n4147, n4148, n4149, n4150, n4151, n4152,
n4153, n4154, n4155, n4156, n4157, n4158, n4159, n4160, n4161, n4162,
n4163, n4164, n4165, n4166, n4167, n4168, n4169, n4170, n4171, n4172,
n4173, n4174, n4175, n4176, n4177, n4178, n4179, n4180, n4181, n4182,
n4183, n4184, n4185, n4186, n4187, n4188, n4189, n4190, n4191, n4192,
n4193, n4194, n4195, n4196, n4197, n4198, n4199, n4200, n4201, n4202,
n4203, n4204, n4205, n4206, n4207, n4208, n4209, n4210, n4211, n4212,
n4213, n4214, n4215, n4216, n4217, n4218, n4219, n4220, n4221, n4222,
n4223, n4224, n4225, n4226, n4227, n4228, n4229, n4230, n4231, n4232,
n4233, n4234, n4235, n4236, n4237, n4238, n4239, n4240, n4241, n4242,
n4243, n4244, n4245, n4246, n4247, n4248, n4249, n4250, n4251, n4252,
n4253, n4254, n4255, n4256, n4257, n4258, n4259, n4260, n4261, n4262,
n4263, n4264, n4265, n4266, n4267, n4268, n4269, n4270, n4271, n4272,
n4273, n4274, n4275, n4276, n4277, n4278, n4279, n4280, n4281, n4282,
n4283, n4284, n4285, n4286, n4287, n4288, n4289, n4290, n4291, n4292,
n4293, n4294, n4295, n4296, n4297, n4298, n4299, n4300, n4301, n4302,
n4303, n4304, n4305, n4306, n4307, n4308, n4309, n4310, n4311, n4312,
n4313, n4314, n4315, n4316, n4317, n4318, n4319, n4320, n4321, n4322,
n4323, n4324, n4325, n4326, n4327, n4328, n4330, n4331, n4332, n4333,
n4334, n4335, n4336, n4337, n4338, n4339, n4340, n4341, n4342, n4343,
n4344, n4345, n4346, n4347, n4349, n4350, n4351, n4352, n4353, n4354,
n4355, n4356, n4357, n4358, n4359, n4360, n4361, n4362, n4363, n4364,
n4365, n4366, n4367, n4368, n4369, n4370, n4371, n4372, n4373, n4374,
n4375, n4376, n4377, n4378, n4379, n4380, n4381, n4382, n4383, n4384,
n4385, n4386, n4387, n4388, n4389, n4390, n4391, n4392, n4393, n4394,
n4395, n4396, n4397, n4398, n4399, n4400, n4401, n4402, n4403, n4404,
n4405, n4406, n4407, n4408, n4409, n4410, n4411, n4412, n4413, n4414,
n4415, n4416, n4417, n4418, n4419, n4420, n4421, n4422, n4423, n4424,
n4425, n4426, n4427, n4428, n4429, n4430, n4431, n4432, n4433, n4434,
n4435, n4436, n4437, n4438, n4439, n4440, n4441, n4442, n4443, n4444,
n4445, n4446, n4447, n4448, n4449, n4450, n4451, n4452, n4453, n4454,
n4455, n4456, n4457, n4458, n4459, n4460, n4461, n4462, n4463, n4464,
n4465, n4466, n4467, n4468, n4469, n4470, n4471, n4472, n4473, n4474,
n4475, n4476, n4477, n4478, n4479, n4480, n4481, n4482, n4483, n4484,
n4485, n4486, n4487, n4488, n4489, n4490, n4491, n4492, n4493, n4494,
n4495, n4496, n4497, n4498, n4499, n4500, n4501, n4502, n4503, n4504,
n4505, n4506, n4507, n4508, n4509, n4510, n4511, n4512, n4513, n4514,
n4515, n4516, n4517, n4518, n4519, n4520, n4521, n4522, n4523, n4524,
n4525, n4526, n4527, n4528, n4529, n4530, n4531, n4532, n4533, n4534,
n4535, n4536, n4537, n4538, n4539, n4540, n4541, n4542, n4543, n4544,
n4545, n4546, n4547, n4548, n4549, n4550, n4551, n4552, n4553, n4554,
n4555, n4556, n4557, n4558, n4559, n4560, n4561, n4562, n4563, n4564,
n4565, n4566, n4567, n4568, n4569, n4570, n4571, n4572, n4573, n4574,
n4575, n4576, n4577, n4578, n4579, n4580, n4581, n4582, n4583, n4584,
n4585, n4586, n4587, n4589;
wire [16:0] P_Sgf;
wire [31:0] Op_MX;
wire [31:0] Op_MY;
wire [7:0] exp_oper_result;
wire [23:0] Add_result;
wire [22:0] Sgf_normalized_result;
wire [3:1] FS_Module_state_reg;
wire [8:4] Exp_module_Data_S;
wire [19:0] Sgf_operation_Result;
wire [15:13] Sgf_operation_EVEN1_S_B;
wire [5:0] Sgf_operation_EVEN1_result_B_adder;
wire [5:0] Sgf_operation_EVEN1_result_A_adder;
wire [23:0] Sgf_operation_EVEN1_Q_left;
wire [13:8] Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle;
wire [11:6] Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right;
wire [11:0] Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left;
wire [8:3] Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle;
wire [13:0] Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right;
wire [11:0] Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left;
wire [13:9] Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle;
wire [11:6] Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right;
wire [11:0] Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left;
DFFRX4TS FS_Module_state_reg_reg_1_ ( .D(n377), .CK(clk), .RN(n4442), .Q(
FS_Module_state_reg[1]), .QN(n4488) );
DFFRX4TS FS_Module_state_reg_reg_2_ ( .D(n376), .CK(clk), .RN(n4442), .Q(
FS_Module_state_reg[2]), .QN(n4393) );
DFFRX4TS FS_Module_state_reg_reg_3_ ( .D(n379), .CK(clk), .RN(n4442), .Q(
FS_Module_state_reg[3]), .QN(n4386) );
DFFRX4TS Sel_A_Q_reg_0_ ( .D(n375), .CK(clk), .RN(n1132), .Q(FSM_selector_A),
.QN(n4385) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_30_ ( .D(n374), .CK(clk), .RN(
n4440), .Q(Op_MX[30]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_29_ ( .D(n373), .CK(clk), .RN(
n4441), .Q(Op_MX[29]) );
DFFRX4TS R_1156 ( .D(n366), .CK(clk), .RN(n4106), .Q(Op_MX[22]) );
DFFRX4TS R_1052 ( .D(n365), .CK(clk), .RN(n1107), .Q(Op_MX[21]) );
DFFRX4TS R_677 ( .D(n364), .CK(clk), .RN(n1109), .Q(Op_MX[20]) );
DFFRX4TS R_633 ( .D(n363), .CK(clk), .RN(n1107), .Q(Op_MX[19]) );
DFFRX4TS R_792 ( .D(n362), .CK(clk), .RN(n1104), .Q(Op_MX[18]) );
DFFRX4TS R_455 ( .D(n361), .CK(clk), .RN(n1107), .Q(Op_MX[17]), .QN(n1852)
);
DFFRX4TS R_669 ( .D(n360), .CK(clk), .RN(n1110), .Q(Op_MX[16]) );
DFFRX4TS R_547 ( .D(n359), .CK(clk), .RN(n1107), .Q(Op_MX[15]) );
DFFRX4TS R_557 ( .D(n358), .CK(clk), .RN(n4542), .Q(Op_MX[14]) );
DFFRX4TS R_503 ( .D(n357), .CK(clk), .RN(n1102), .Q(Op_MX[13]) );
DFFRX4TS R_512 ( .D(n356), .CK(clk), .RN(n4542), .Q(Op_MX[12]) );
DFFRX4TS R_1470 ( .D(n355), .CK(clk), .RN(n1103), .Q(Op_MX[11]) );
DFFRX4TS R_1155 ( .D(n354), .CK(clk), .RN(n4543), .Q(Op_MX[10]) );
DFFRX4TS R_1051 ( .D(n353), .CK(clk), .RN(n1129), .Q(Op_MX[9]) );
DFFRX4TS R_731 ( .D(n352), .CK(clk), .RN(n1101), .Q(Op_MX[8]) );
DFFRX4TS R_617 ( .D(n351), .CK(clk), .RN(n1102), .Q(Op_MX[7]) );
DFFRX4TS R_624 ( .D(n350), .CK(clk), .RN(n1103), .Q(Op_MX[6]) );
DFFRX4TS R_1087 ( .D(n349), .CK(clk), .RN(n1101), .Q(Op_MX[5]) );
DFFRX4TS R_1016 ( .D(n348), .CK(clk), .RN(n1103), .Q(Op_MX[4]) );
DFFRX4TS R_1047 ( .D(n347), .CK(clk), .RN(n4539), .Q(Op_MX[3]) );
DFFRX4TS R_1081 ( .D(n346), .CK(clk), .RN(n4539), .Q(Op_MX[2]) );
DFFRX4TS R_1092 ( .D(n345), .CK(clk), .RN(n4539), .Q(Op_MX[1]) );
DFFRX4TS R_1068 ( .D(n344), .CK(clk), .RN(n4539), .Q(Op_MX[0]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_31_ ( .D(n343), .CK(clk), .RN(
n4539), .Q(Op_MX[31]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_16_ ( .D(n290), .CK(clk), .RN(n4540),
.Q(Add_result[16]), .QN(n4423) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_8_ ( .D(n298), .CK(clk), .RN(n4540),
.Q(Add_result[8]), .QN(n4424) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_7_ ( .D(n299), .CK(clk), .RN(n4541),
.Q(Add_result[7]), .QN(n4430) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_6_ ( .D(n300), .CK(clk), .RN(n4541),
.Q(Add_result[6]), .QN(n4431) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_5_ ( .D(n301), .CK(clk), .RN(n4541),
.Q(Add_result[5]), .QN(n4432) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_3_ ( .D(n303), .CK(clk), .RN(n4541),
.Q(Add_result[3]), .QN(n4433) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_2_ ( .D(n304), .CK(clk), .RN(n4541),
.Q(Add_result[2]), .QN(n4429) );
DFFRXLTS Adder_M_Add_overflow_Result_Q_reg_0_ ( .D(n282), .CK(clk), .RN(
n4541), .Q(FSM_add_overflow_flag) );
DFFRX4TS R_831 ( .D(n334), .CK(clk), .RN(n1108), .Q(Op_MY[22]), .QN(n1063)
);
DFFRX2TS R_1574 ( .D(n1040), .CK(clk), .RN(n4447), .Q(Op_MY[20]) );
DFFRX4TS R_680 ( .D(n328), .CK(clk), .RN(n4447), .Q(Op_MY[16]), .QN(n1064)
);
DFFRX4TS R_822 ( .D(n322), .CK(clk), .RN(n4589), .Q(Op_MY[10]) );
DFFRX4TS R_1294 ( .D(n316), .CK(clk), .RN(n1102), .Q(Op_MY[4]) );
DFFRX1TS Zero_Result_Detect_Zero_Info_Mult_Q_reg_0_ ( .D(n311), .CK(clk),
.RN(n4106), .Q(zero_flag), .QN(n4418) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_0_ ( .D(n280), .CK(clk), .RN(n4101),
.Q(exp_oper_result[0]), .QN(n4421) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_2_ ( .D(n278), .CK(clk), .RN(n1100),
.Q(exp_oper_result[2]), .QN(n4422) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_3_ ( .D(n277), .CK(clk), .RN(n4191),
.Q(exp_oper_result[3]), .QN(n4420) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_16_ ( .D(n231), .CK(clk), .RN(
n4538), .Q(P_Sgf[16]) );
DFFRX2TS Sgf_operation_EVEN1_finalreg_Q_reg_15_ ( .D(n230), .CK(clk), .RN(
n4537), .Q(P_Sgf[15]) );
DFFRX2TS Sgf_operation_EVEN1_finalreg_Q_reg_14_ ( .D(n229), .CK(clk), .RN(
n1125), .Q(P_Sgf[14]) );
DFFRX2TS Sgf_operation_EVEN1_finalreg_Q_reg_13_ ( .D(n228), .CK(clk), .RN(
n4538), .Q(P_Sgf[13]) );
DFFRX2TS Sgf_operation_EVEN1_finalreg_Q_reg_12_ ( .D(n4394), .CK(clk), .RN(
n4535), .Q(P_Sgf[12]) );
DFFRX2TS Sgf_operation_EVEN1_finalreg_Q_reg_11_ ( .D(n4412), .CK(clk), .RN(
n4537), .Q(P_Sgf[11]) );
DFFRX2TS Sgf_operation_EVEN1_finalreg_Q_reg_10_ ( .D(n225), .CK(clk), .RN(
n1125), .Q(P_Sgf[10]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_0_ ( .D(n215), .CK(clk), .RN(
n4536), .Q(P_Sgf[0]), .QN(n4419) );
DFFRX4TS final_result_ieee_Module_Final_Result_IEEE_Q_reg_21_ ( .D(n169),
.CK(clk), .RN(n1130), .Q(final_result_ieee[21]) );
DFFRX4TS final_result_ieee_Module_Final_Result_IEEE_Q_reg_22_ ( .D(n167),
.CK(clk), .RN(n1131), .Q(final_result_ieee[22]) );
DFFHQX4TS Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_Data_S_o_reg_3_ (
.D(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N3), .CK(clk), .Q(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[3]) );
DFFHQX4TS Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_Data_S_o_reg_4_ (
.D(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N4), .CK(clk), .Q(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[4]) );
DFFHQX4TS Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_Data_S_o_reg_5_ (
.D(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N5), .CK(clk), .Q(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[5]) );
DFFHQX4TS Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_Data_S_o_reg_7_ (
.D(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N7), .CK(clk), .Q(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[7]) );
DFFHQX4TS R_507 ( .D(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N2),
.CK(clk), .Q(Sgf_operation_Result[2]) );
DFFHQX4TS R_1432 ( .D(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N0),
.CK(clk), .Q(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[0]) );
DFFHQX8TS Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_Data_S_o_reg_1_ (
.D(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N1),
.CK(clk), .Q(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[1]) );
DFFHQX4TS R_1102 ( .D(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N4),
.CK(clk), .Q(Sgf_operation_Result[4]) );
DFFHQX4TS R_692 ( .D(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N3),
.CK(clk), .Q(Sgf_operation_EVEN1_Q_left[3]) );
DFFHQX4TS R_694 ( .D(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N2),
.CK(clk), .Q(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[2]) );
DFFHQX8TS R_1422 ( .D(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N8),
.CK(clk), .Q(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[8]) );
DFFHQX4TS R_728 ( .D(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N2),
.CK(clk), .Q(Sgf_operation_EVEN1_Q_left[2]) );
DFFSX1TS R_2 ( .D(n4565), .CK(clk), .SN(n4446), .Q(n4532) );
DFFSX1TS R_5 ( .D(n4573), .CK(clk), .SN(n4445), .Q(n4531) );
DFFSX1TS R_8 ( .D(n4569), .CK(clk), .SN(n4446), .Q(n4530) );
DFFSX1TS R_11 ( .D(n4548), .CK(clk), .SN(n4446), .QN(n1052) );
DFFSX1TS R_14 ( .D(n4547), .CK(clk), .SN(n1092), .Q(n4529) );
DFFSX1TS R_17 ( .D(n4545), .CK(clk), .SN(n1092), .QN(n938) );
DFFSX1TS R_20 ( .D(n4561), .CK(clk), .SN(n4446), .Q(n4528) );
DFFSX1TS R_23 ( .D(n4560), .CK(clk), .SN(n4446), .Q(n4527) );
DFFSX1TS R_26 ( .D(n4556), .CK(clk), .SN(n4446), .Q(n4526) );
DFFSX1TS R_29 ( .D(n4552), .CK(clk), .SN(n4537), .Q(n4525) );
DFFSX1TS R_32 ( .D(n4580), .CK(clk), .SN(n1093), .Q(n4524) );
DFFRXLTS R_34 ( .D(n251), .CK(clk), .RN(n4445), .Q(n4523) );
DFFRXLTS R_37 ( .D(n249), .CK(clk), .RN(n4443), .Q(n4522) );
DFFRXLTS R_40 ( .D(n248), .CK(clk), .RN(n4443), .Q(n4521) );
DFFRXLTS R_43 ( .D(n250), .CK(clk), .RN(n4445), .Q(n4520) );
DFFRXLTS R_46 ( .D(n243), .CK(clk), .RN(n4443), .Q(n4519) );
DFFRXLTS R_71 ( .D(n244), .CK(clk), .RN(n4443), .Q(n4518) );
DFFRXLTS R_74 ( .D(n246), .CK(clk), .RN(n4443), .Q(n4517) );
DFFRXLTS R_77 ( .D(n245), .CK(clk), .RN(n4444), .Q(n4516) );
DFFRXLTS R_80 ( .D(n247), .CK(clk), .RN(n4444), .Q(n4515) );
DFFRXLTS R_198 ( .D(n242), .CK(clk), .RN(n4444), .Q(n4514) );
DFFRXLTS R_330 ( .D(n241), .CK(clk), .RN(n4444), .Q(n4513) );
DFFRXLTS R_393 ( .D(n240), .CK(clk), .RN(n4443), .Q(n4512) );
DFFRXLTS R_450 ( .D(n239), .CK(clk), .RN(n4536), .Q(n4511) );
DFFRX4TS R_542 ( .D(DP_OP_158J21_127_356_n986), .CK(clk), .RN(n1100), .QN(
n1837) );
DFFHQX4TS R_723 ( .D(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N3),
.CK(clk), .Q(Sgf_operation_Result[3]) );
DFFHQX4TS R_886 ( .D(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N5),
.CK(clk), .Q(Sgf_operation_Result[5]) );
DFFRX4TS R_1151 ( .D(n4503), .CK(clk), .RN(n4542), .Q(
Sgf_operation_EVEN1_result_A_adder[1]) );
DFFRX4TS R_1161 ( .D(DP_OP_158J21_127_356_n1057), .CK(clk), .RN(n1101), .Q(
Sgf_operation_EVEN1_result_A_adder[3]) );
DFFRX4TS R_1235 ( .D(n4500), .CK(clk), .RN(n1103), .Q(
Sgf_operation_EVEN1_result_B_adder[4]) );
DFFRX4TS R_1264 ( .D(n4499), .CK(clk), .RN(n4440), .Q(
Sgf_operation_EVEN1_result_B_adder[2]) );
DFFRX4TS R_1266 ( .D(n4498), .CK(clk), .RN(n4440), .Q(
Sgf_operation_EVEN1_result_B_adder[1]) );
DFFRX4TS R_1283 ( .D(n4497), .CK(clk), .RN(n1100), .Q(
Sgf_operation_EVEN1_result_A_adder[0]) );
DFFRX4TS R_1452 ( .D(n4496), .CK(clk), .RN(n1100), .Q(
Sgf_operation_EVEN1_result_A_adder[2]) );
DFFRX4TS R_1473 ( .D(n4495), .CK(clk), .RN(n1100), .Q(
Sgf_operation_EVEN1_result_A_adder[4]) );
DFFSX4TS R_1652 ( .D(n4582), .CK(clk), .SN(n1093), .Q(n4490) );
DFFSX4TS R_1651 ( .D(n4489), .CK(clk), .SN(n1092), .Q(n4491) );
DFFSX4TS R_1650 ( .D(n4581), .CK(clk), .SN(n1092), .Q(n4492) );
DFFRX4TS R_1696 ( .D(n4484), .CK(clk), .RN(n1129), .Q(
Sgf_operation_EVEN1_result_B_adder[0]) );
DFFRX4TS R_1712 ( .D(n4480), .CK(clk), .RN(n4447), .QN(n881) );
DFFRX4TS R_1710 ( .D(n4481), .CK(clk), .RN(n4447), .Q(
Sgf_operation_EVEN1_result_B_adder[5]) );
DFFHQX4TS R_895 ( .D(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N4),
.CK(clk), .Q(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[4]) );
DFFHQX4TS R_509 ( .D(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N1),
.CK(clk), .Q(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[1]) );
DFFHQX4TS R_708 ( .D(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N3),
.CK(clk), .Q(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[3]) );
DFFHQX4TS R_698 ( .D(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N2),
.CK(clk), .Q(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[2]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_1_ ( .D(n189),
.CK(clk), .RN(n1105), .Q(final_result_ieee[1]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_2_ ( .D(n188),
.CK(clk), .RN(n1105), .Q(final_result_ieee[2]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_3_ ( .D(n187),
.CK(clk), .RN(n1105), .Q(final_result_ieee[3]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_4_ ( .D(n186),
.CK(clk), .RN(n1105), .Q(final_result_ieee[4]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_5_ ( .D(n185),
.CK(clk), .RN(n1105), .Q(final_result_ieee[5]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_6_ ( .D(n184),
.CK(clk), .RN(n1105), .Q(final_result_ieee[6]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_7_ ( .D(n183),
.CK(clk), .RN(n1105), .Q(final_result_ieee[7]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_8_ ( .D(n182),
.CK(clk), .RN(n1105), .Q(final_result_ieee[8]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_9_ ( .D(n181),
.CK(clk), .RN(n1104), .Q(final_result_ieee[9]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_10_ ( .D(n180),
.CK(clk), .RN(n1104), .Q(final_result_ieee[10]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_11_ ( .D(n179),
.CK(clk), .RN(n4543), .Q(final_result_ieee[11]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_12_ ( .D(n178),
.CK(clk), .RN(n4541), .Q(final_result_ieee[12]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_13_ ( .D(n177),
.CK(clk), .RN(n4219), .Q(final_result_ieee[13]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_14_ ( .D(n176),
.CK(clk), .RN(n4162), .Q(final_result_ieee[14]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_15_ ( .D(n175),
.CK(clk), .RN(n4543), .Q(final_result_ieee[15]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_16_ ( .D(n174),
.CK(clk), .RN(n4104), .Q(final_result_ieee[16]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_17_ ( .D(n173),
.CK(clk), .RN(n4162), .Q(final_result_ieee[17]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_18_ ( .D(n172),
.CK(clk), .RN(n4541), .Q(final_result_ieee[18]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_19_ ( .D(n171),
.CK(clk), .RN(n4447), .Q(final_result_ieee[19]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_20_ ( .D(n170),
.CK(clk), .RN(n1102), .Q(final_result_ieee[20]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_23_ ( .D(n270),
.CK(clk), .RN(n4191), .Q(final_result_ieee[23]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_24_ ( .D(n269),
.CK(clk), .RN(n4543), .Q(final_result_ieee[24]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_25_ ( .D(n268),
.CK(clk), .RN(n4541), .Q(final_result_ieee[25]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_26_ ( .D(n267),
.CK(clk), .RN(n4541), .Q(final_result_ieee[26]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_27_ ( .D(n266),
.CK(clk), .RN(n4191), .Q(final_result_ieee[27]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_28_ ( .D(n265),
.CK(clk), .RN(n3521), .Q(final_result_ieee[28]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_29_ ( .D(n264),
.CK(clk), .RN(n1102), .Q(final_result_ieee[29]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_30_ ( .D(n263),
.CK(clk), .RN(n1105), .Q(final_result_ieee[30]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_0_ ( .D(n190),
.CK(clk), .RN(n4543), .Q(final_result_ieee[0]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_5_ ( .D(n220), .CK(clk), .RN(
n4536), .Q(P_Sgf[5]), .QN(n4439) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_4_ ( .D(n219), .CK(clk), .RN(
n4536), .Q(P_Sgf[4]), .QN(n4438) );
DFFSX1TS R_1095 ( .D(Sgf_operation_Result[19]), .CK(clk), .SN(n4538), .Q(
n4505) );
DFFSX1TS R_1183 ( .D(Sgf_operation_Result[17]), .CK(clk), .SN(n4535), .Q(
n4502) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_2_ ( .D(n217), .CK(clk), .RN(
n4536), .Q(P_Sgf[2]), .QN(n4436) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_3_ ( .D(n218), .CK(clk), .RN(
n4536), .Q(P_Sgf[3]), .QN(n4437) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_1_ ( .D(n216), .CK(clk), .RN(
n4536), .Q(P_Sgf[1]), .QN(n4435) );
DFFRXLTS R_1759 ( .D(n307), .CK(clk), .RN(n4252), .Q(n4460) );
DFFRXLTS R_1096 ( .D(n234), .CK(clk), .RN(n1093), .Q(n4504) );
DFFRXLTS R_1184 ( .D(n232), .CK(clk), .RN(n4537), .Q(n4501) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_31_ ( .D(n310), .CK(clk), .RN(
n4440), .Q(Op_MY[31]) );
DFFHQX4TS R_1521 ( .D(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N0),
.CK(clk), .Q(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[0]) );
DFFRXLTS R_1811 ( .D(n281), .CK(clk), .RN(n4101), .Q(n4454) );
DFFRXLTS R_1820 ( .D(n274), .CK(clk), .RN(n4219), .Q(n4448) );
DFFSX2TS R_1536 ( .D(n4587), .CK(clk), .SN(n1102), .Q(n4493) );
DFFSX2TS R_1724 ( .D(n4559), .CK(clk), .SN(n4252), .Q(n4476) );
DFFSX2TS R_1733 ( .D(n4564), .CK(clk), .SN(n1111), .Q(n4467) );
DFFSX1TS R_1735 ( .D(n4562), .CK(clk), .SN(n1112), .Q(n4465) );
DFFSX1TS R_1720 ( .D(n4575), .CK(clk), .SN(n1112), .Q(n4478) );
DFFSX2TS R_1666 ( .D(n4579), .CK(clk), .SN(n1112), .Q(n4487) );
DFFSX2TS R_1753 ( .D(n4568), .CK(clk), .SN(n1111), .Q(n4464) );
DFFRX2TS R_1549 ( .D(n327), .CK(clk), .RN(n4447), .Q(Op_MY[15]) );
DFFRX2TS R_1569 ( .D(n1121), .CK(clk), .RN(n1103), .Q(Op_MY[8]) );
DFFRX2TS R_1509 ( .D(n1098), .CK(clk), .RN(n1102), .Q(Op_MY[7]) );
DFFRX2TS R_1491 ( .D(n318), .CK(clk), .RN(n4543), .Q(Op_MY[6]) );
DFFSX1TS R_1755 ( .D(n4566), .CK(clk), .SN(n1111), .Q(n4462) );
DFFSX1TS R_1768 ( .D(n4570), .CK(clk), .SN(n1111), .Q(n4456) );
DFFRX2TS R_1543 ( .D(n1099), .CK(clk), .RN(n4542), .Q(Op_MY[9]) );
DFFRX2TS R_1544 ( .D(n315), .CK(clk), .RN(n4542), .Q(Op_MY[3]) );
DFFHQX1TS R_1607 ( .D(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N10),
.CK(clk), .Q(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[10]) );
DFFRXLTS R_1814 ( .D(n275), .CK(clk), .RN(n1129), .Q(n4452) );
DFFRXLTS R_1817 ( .D(n276), .CK(clk), .RN(n4219), .Q(n4450) );
DFFHQX4TS R_688 ( .D(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N4),
.CK(clk), .Q(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[4]) );
DFFQX1TS R_1205 ( .D(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N6),
.CK(clk), .Q(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[6]) );
DFFSX2TS R_1702 ( .D(n4583), .CK(clk), .SN(n4252), .Q(n4483) );
DFFQX1TS R_1646 ( .D(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N8),
.CK(clk), .Q(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[8]) );
DFFHQX4TS Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_Data_S_o_reg_10_ (
.D(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N10),
.CK(clk), .Q(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[10]) );
DFFHQX4TS Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_Data_S_o_reg_13_ (
.D(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N13),
.CK(clk), .Q(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[13]) );
DFFHQX4TS R_752 ( .D(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N1),
.CK(clk), .Q(Sgf_operation_Result[1]) );
DFFHQX2TS R_1630 ( .D(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N9),
.CK(clk), .Q(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[9]) );
DFFHQX4TS R_1217 ( .D(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N6),
.CK(clk), .Q(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[6]) );
DFFHQX4TS R_706 ( .D(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N0),
.CK(clk), .Q(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[0]) );
DFFHQX4TS R_690 ( .D(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N1),
.CK(clk), .Q(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[1]) );
DFFHQX4TS R_704 ( .D(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N4),
.CK(clk), .Q(Sgf_operation_EVEN1_Q_left[4]) );
DFFHQX4TS R_1196 ( .D(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N7),
.CK(clk), .Q(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[7]) );
DFFHQX4TS R_117 ( .D(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N0),
.CK(clk), .Q(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[0]) );
DFFHQX4TS R_1257 ( .D(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N0),
.CK(clk), .Q(Sgf_operation_EVEN1_Q_left[0]) );
DFFHQX4TS Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_8_ (
.D(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N8),
.CK(clk), .Q(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[8]) );
DFFHQX4TS Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_9_ (
.D(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N9),
.CK(clk), .Q(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[9]) );
DFFHQX4TS Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_3_ (
.D(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N3),
.CK(clk), .Q(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[3]) );
DFFHQX4TS Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_4_ (
.D(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N4),
.CK(clk), .Q(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[4]) );
DFFHQX4TS Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_5_ (
.D(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N5),
.CK(clk), .Q(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[5]) );
DFFHQX4TS Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_6_ (
.D(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N6),
.CK(clk), .Q(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[6]) );
DFFHQX4TS Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_7_ (
.D(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N7),
.CK(clk), .Q(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[7]) );
DFFHQX4TS Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_8_ (
.D(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N8),
.CK(clk), .Q(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[8]) );
DFFHQX4TS Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_9_ (
.D(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N9),
.CK(clk), .Q(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[9]) );
DFFHQX4TS Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_10_ (
.D(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N10),
.CK(clk), .Q(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[10]) );
DFFHQX4TS Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_Data_S_o_reg_3_ (
.D(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N3),
.CK(clk), .Q(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[3]) );
DFFHQX4TS Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_Data_S_o_reg_4_ (
.D(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N4),
.CK(clk), .Q(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[4]) );
DFFHQX4TS Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_Data_S_o_reg_5_ (
.D(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N5),
.CK(clk), .Q(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[5]) );
DFFHQX4TS Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_Data_S_o_reg_6_ (
.D(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N6),
.CK(clk), .Q(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[6]) );
DFFHQX4TS Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_Data_S_o_reg_8_ (
.D(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N8),
.CK(clk), .Q(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[8]) );
DFFHQX4TS Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_Data_S_o_reg_9_ (
.D(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N9),
.CK(clk), .Q(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[9]) );
DFFHQX4TS Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_Data_S_o_reg_8_ (
.D(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N8), .CK(clk), .Q(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[8]) );
DFFHQX4TS Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_Data_S_o_reg_9_ (
.D(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N9), .CK(clk), .Q(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[9]) );
DFFHQX4TS R_1363 ( .D(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N8),
.CK(clk), .Q(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[8]) );
DFFHQX4TS Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_11_ (
.D(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N11), .CK(clk), .Q(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[11]) );
DFFHQX4TS R_1126 ( .D(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N5),
.CK(clk), .Q(Sgf_operation_EVEN1_Q_left[5]) );
DFFHQX4TS R_1644 ( .D(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N9),
.CK(clk), .Q(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[9]) );
DFFHQX4TS Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_Data_S_o_reg_7_ (
.D(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N7),
.CK(clk), .Q(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[7]) );
DFFHQX4TS R_1351 ( .D(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N7),
.CK(clk), .Q(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[7]) );
DFFQX1TS R_1420 ( .D(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N1),
.CK(clk), .Q(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[1]) );
DFFQX4TS R_875 ( .D(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N5),
.CK(clk), .Q(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[5]) );
DFFHQX4TS R_973 ( .D(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N6),
.CK(clk), .Q(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[6]) );
DFFQX4TS R_1424 ( .D(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N8),
.CK(clk), .Q(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[8]) );
DFFSX1TS add_x_19_R_1340 ( .D(add_x_19_n23), .CK(clk), .SN(n4442), .Q(n4366)
);
DFFSX1TS add_x_19_R_1343 ( .D(add_x_19_n257), .CK(clk), .SN(n1094), .Q(n4367) );
DFFSX1TS add_x_19_R_1339 ( .D(add_x_19_n268), .CK(clk), .SN(n4537), .Q(n4365) );
DFFSX2TS add_x_19_R_1438 ( .D(Sgf_operation_EVEN1_Q_left[1]), .CK(clk), .SN(
n4382), .Q(n4370) );
DFFSX1TS add_x_19_R_1594 ( .D(add_x_19_n247), .CK(clk), .SN(n1125), .Q(n4375) );
DFFSX1TS add_x_19_R_1561 ( .D(add_x_19_n251), .CK(clk), .SN(n450), .Q(n4371)
);
DFFSX1TS add_x_19_R_1344 ( .D(add_x_19_n22), .CK(clk), .SN(n4538), .Q(n4368)
);
DFFSX1TS add_x_19_R_1331 ( .D(add_x_19_n21), .CK(clk), .SN(n4384), .Q(n4364)
);
DFFRXLTS add_x_19_R_1299 ( .D(add_x_19_n24), .CK(clk), .RN(n4384), .Q(n4363)
);
DFFRX4TS add_x_19_R_1804 ( .D(add_x_19_n26), .CK(clk), .RN(n4535), .Q(n4379)
);
DFFRXLTS add_x_19_R_899_RW_0 ( .D(add_x_19_n236), .CK(clk), .RN(n1094), .Q(
n4361) );
DFFRXLTS add_x_19_R_898_RW_0 ( .D(add_x_19_n320), .CK(clk), .RN(n4380), .Q(
n4360) );
DFFSX1TS add_x_19_R_1689 ( .D(add_x_19_n320), .CK(clk), .SN(n4383), .Q(n4376) );
DFFRX4TS add_x_19_R_1562 ( .D(add_x_19_n252), .CK(clk), .RN(n4384), .Q(n4372) );
DFFRXLTS add_x_19_R_598_RW_0 ( .D(add_x_19_n244), .CK(clk), .RN(n4537), .Q(
n4358) );
DFFSX1TS add_x_19_R_854 ( .D(add_x_19_n20), .CK(clk), .SN(n4538), .Q(n4359)
);
DFFSX1TS add_x_19_R_434 ( .D(add_x_19_n272), .CK(clk), .SN(n450), .Q(n4356)
);
DFFSX1TS add_x_19_R_69 ( .D(Sgf_operation_EVEN1_Q_left[23]), .CK(clk), .SN(
n4384), .Q(n4355) );
DFFSX1TS add_x_19_R_67 ( .D(n2015), .CK(clk), .SN(n4381), .Q(n4354) );
DFFSX1TS add_x_19_R_65 ( .D(n3621), .CK(clk), .SN(n1092), .Q(n4353) );
DFFSX1TS add_x_19_R_63 ( .D(add_x_19_n68), .CK(clk), .SN(n4381), .Q(n4352)
);
DFFSX1TS add_x_19_R_55 ( .D(n3601), .CK(clk), .SN(n4381), .QN(n937) );
DFFSX1TS add_x_19_R_53 ( .D(n866), .CK(clk), .SN(n4381), .QN(n939) );
DFFSX1TS add_x_19_R_51 ( .D(add_x_19_n95), .CK(clk), .SN(n4381), .Q(n4349)
);
DFFRXLTS add_x_19_R_49 ( .D(add_x_19_n106), .CK(clk), .RN(n450), .QN(n416)
);
DFFSX2TS DP_OP_156J21_125_3370_R_1599 ( .D(DP_OP_156J21_125_3370_n201), .CK(
clk), .SN(n450), .Q(n4335) );
DFFSX2TS DP_OP_156J21_125_3370_R_1600 ( .D(DP_OP_156J21_125_3370_n204), .CK(
clk), .SN(n450), .Q(n4336) );
DFFHQX4TS DP_OP_156J21_125_3370_R_1433 ( .D(n4331), .CK(clk), .Q(
DP_OP_156J21_125_3370_n164) );
DFFHQX4TS DP_OP_156J21_125_3370_R_1436 ( .D(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N0),
.CK(clk), .Q(DP_OP_156J21_125_3370_n408) );
DFFHQX4TS DP_OP_156J21_125_3370_R_1434 ( .D(n4125), .CK(clk), .Q(
DP_OP_156J21_125_3370_n299) );
DFFSX1TS DP_OP_156J21_125_3370_R_1228 ( .D(DP_OP_156J21_125_3370_n85), .CK(
clk), .SN(n4346), .Q(n4328) );
DFFRX2TS DP_OP_156J21_125_3370_R_1773 ( .D(DP_OP_156J21_125_3370_n91), .CK(
clk), .RN(n4537), .Q(n4340) );
DFFRXLTS DP_OP_156J21_125_3370_R_1611 ( .D(DP_OP_156J21_125_3370_n83), .CK(
clk), .RN(n1125), .Q(n4337) );
DFFSX1TS DP_OP_156J21_125_3370_R_1779 ( .D(DP_OP_156J21_125_3370_n174), .CK(
clk), .SN(n4445), .Q(n4342) );
DFFSX1TS DP_OP_156J21_125_3370_R_1533 ( .D(DP_OP_156J21_125_3370_n168), .CK(
clk), .SN(n4347), .Q(n4334) );
DFFSX4TS DP_OP_156J21_125_3370_R_1187 ( .D(DP_OP_156J21_125_3370_n11), .CK(
clk), .SN(n4444), .Q(n4327) );
DFFRX2TS DP_OP_156J21_125_3370_R_1024 ( .D(DP_OP_156J21_125_3370_n10), .CK(
clk), .RN(n4535), .Q(n4326) );
DFFRXLTS DP_OP_156J21_125_3370_R_716 ( .D(DP_OP_156J21_125_3370_n2), .CK(clk), .RN(n4347), .Q(n4325) );
DFFSX4TS DP_OP_159J21_128_5719_R_1748 ( .D(n4315), .CK(clk), .SN(n4323), .Q(
DP_OP_159J21_128_5719_n248), .QN(n4324) );
DFFSX4TS DP_OP_159J21_128_5719_R_1686 ( .D(n4317), .CK(clk), .SN(n4543), .Q(
DP_OP_159J21_128_5719_n256) );
DFFSX4TS DP_OP_159J21_128_5719_R_1687 ( .D(n4321), .CK(clk), .SN(n4543), .Q(
DP_OP_159J21_128_5719_n229) );
DFFSX4TS DP_OP_159J21_128_5719_R_1617 ( .D(n4318), .CK(clk), .SN(n4323), .Q(
DP_OP_159J21_128_5719_n249) );
DFFSX4TS DP_OP_159J21_128_5719_R_1626 ( .D(n4314), .CK(clk), .SN(n4323), .Q(
DP_OP_159J21_128_5719_n259) );
DFFSX4TS DP_OP_159J21_128_5719_R_1627 ( .D(n4313), .CK(clk), .SN(n4323), .Q(
DP_OP_159J21_128_5719_n262) );
DFFRX4TS DP_OP_159J21_128_5719_R_1494 ( .D(n318), .CK(clk), .RN(n4323), .Q(
DP_OP_159J21_128_5719_n294) );
DFFRX4TS DP_OP_159J21_128_5719_R_1495 ( .D(n312), .CK(clk), .RN(n4323), .Q(
DP_OP_159J21_128_5719_n300) );
DFFHQX4TS DP_OP_154J21_123_2814_R_1649 ( .D(n4308), .CK(clk), .Q(
DP_OP_154J21_123_2814_n120) );
DFFHQX4TS DP_OP_154J21_123_2814_R_1386 ( .D(n4297), .CK(clk), .Q(
DP_OP_154J21_123_2814_n121) );
DFFHQX4TS DP_OP_154J21_123_2814_R_1567 ( .D(n4302), .CK(clk), .Q(
DP_OP_154J21_123_2814_n92) );
DFFHQX4TS DP_OP_154J21_123_2814_R_1645 ( .D(n4306), .CK(clk), .Q(
DP_OP_154J21_123_2814_n135) );
DFFHQX4TS DP_OP_154J21_123_2814_R_1423 ( .D(n4301), .CK(clk), .Q(
DP_OP_154J21_123_2814_n148) );
DFFHQX4TS DP_OP_154J21_123_2814_R_1648 ( .D(n4307), .CK(clk), .Q(
DP_OP_154J21_123_2814_n119) );
DFFHQX4TS DP_OP_154J21_123_2814_R_1757 ( .D(n4311), .CK(clk), .Q(
DP_OP_154J21_123_2814_n146) );
DFFHQX4TS DP_OP_154J21_123_2814_R_1706 ( .D(n4310), .CK(clk), .Q(
DP_OP_154J21_123_2814_n133) );
DFFHQX8TS DP_OP_154J21_123_2814_R_1699 ( .D(n4309), .CK(clk), .Q(
DP_OP_154J21_123_2814_n84) );
DFFHQX4TS DP_OP_154J21_123_2814_R_1631 ( .D(n4305), .CK(clk), .Q(
DP_OP_154J21_123_2814_n147) );
DFFHQX4TS DP_OP_154J21_123_2814_R_1602 ( .D(n4300), .CK(clk), .Q(
DP_OP_154J21_123_2814_n131) );
DFFHQX4TS DP_OP_154J21_123_2814_R_1565 ( .D(n4299), .CK(clk), .Q(
DP_OP_154J21_123_2814_n91) );
DFFHQX8TS DP_OP_154J21_123_2814_R_1387 ( .D(n4298), .CK(clk), .Q(
DP_OP_154J21_123_2814_n122) );
DFFHQX4TS DP_OP_154J21_123_2814_R_1365 ( .D(n4312), .CK(clk), .Q(
DP_OP_154J21_123_2814_n94) );
DFFHQX4TS DP_OP_154J21_123_2814_R_1366 ( .D(n4291), .CK(clk), .Q(
DP_OP_154J21_123_2814_n144) );
DFFHQX4TS DP_OP_154J21_123_2814_R_1364 ( .D(n4295), .CK(clk), .Q(
DP_OP_154J21_123_2814_n136) );
DFFHQX4TS DP_OP_154J21_123_2814_R_1332 ( .D(n4294), .CK(clk), .Q(
DP_OP_154J21_123_2814_n97) );
DFFHQX8TS DP_OP_154J21_123_2814_R_1260 ( .D(n4293), .CK(clk), .Q(
DP_OP_154J21_123_2814_n124) );
DFFHQX4TS DP_OP_154J21_123_2814_R_1697 ( .D(n4290), .CK(clk), .Q(
DP_OP_154J21_123_2814_n128) );
DFFHQX8TS DP_OP_154J21_123_2814_R_1226 ( .D(n4289), .CK(clk), .Q(
DP_OP_154J21_123_2814_n127) );
DFFHQX8TS DP_OP_154J21_123_2814_R_1191 ( .D(n4287), .CK(clk), .Q(
DP_OP_154J21_123_2814_n125) );
DFFHQX8TS DP_OP_154J21_123_2814_R_1192 ( .D(n4288), .CK(clk), .Q(
DP_OP_154J21_123_2814_n126) );
DFFHQX4TS DP_OP_154J21_123_2814_R_1698 ( .D(n4285), .CK(clk), .Q(
DP_OP_154J21_123_2814_n129) );
DFFHQX4TS DP_OP_154J21_123_2814_R_1601 ( .D(n4286), .CK(clk), .Q(
DP_OP_154J21_123_2814_n130) );
DFFRXLTS mult_x_59_R_1635 ( .D(n4282), .CK(clk), .RN(n4284), .Q(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N3),
.QN(n1841) );
DFFRXLTS mult_x_59_R_1216 ( .D(n4269), .CK(clk), .RN(n4542), .Q(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N2),
.QN(n1842) );
DFFRXLTS mult_x_59_R_970 ( .D(n356), .CK(clk), .RN(n4283), .Q(mult_x_59_a_0_) );
DFFRXLTS mult_x_59_R_1395 ( .D(n4278), .CK(clk), .RN(n4284), .Q(
mult_x_59_n29) );
DFFRXLTS mult_x_59_R_1394 ( .D(n4277), .CK(clk), .RN(n4284), .Q(
mult_x_59_n28) );
DFFRXLTS mult_x_59_R_1393 ( .D(n4276), .CK(clk), .RN(n4284), .Q(
mult_x_59_n30) );
CMPR42X2TS mult_x_59_U16 ( .A(mult_x_59_n33), .B(mult_x_59_n31), .C(
mult_x_59_n27), .D(mult_x_59_n25), .ICI(mult_x_59_n28), .S(
mult_x_59_n23), .ICO(mult_x_59_n21), .CO(mult_x_59_n22) );
CMPR42X2TS mult_x_59_U19 ( .A(n4268), .B(n4262), .C(n4266), .D(n4261), .ICI(
n4273), .S(n4276), .ICO(n4277), .CO(n4278) );
DFFRX2TS mult_x_59_R_1371 ( .D(n4275), .CK(clk), .RN(n4284), .Q(
mult_x_59_n25) );
DFFRXLTS mult_x_59_R_1370 ( .D(n4274), .CK(clk), .RN(n4284), .Q(
mult_x_59_n24) );
CMPR42X2TS mult_x_59_U14 ( .A(mult_x_59_n59), .B(mult_x_59_n26), .C(
mult_x_59_n24), .D(mult_x_59_n20), .ICI(mult_x_59_n21), .S(
mult_x_59_n18), .ICO(mult_x_59_n16), .CO(mult_x_59_n17) );
DFFRX2TS mult_x_59_R_1286 ( .D(n4271), .CK(clk), .RN(n4283), .Q(
mult_x_59_n27) );
DFFRX2TS mult_x_59_R_1106 ( .D(n359), .CK(clk), .RN(n1107), .Q(
mult_x_59_a_3_) );
DFFRXLTS mult_x_59_R_1033 ( .D(n4267), .CK(clk), .RN(n4283), .Q(
mult_x_59_n36) );
CMPR42X2TS mult_x_59_U22 ( .A(n4255), .B(n4256), .C(n4257), .D(n4258), .ICI(
n4263), .S(n4265), .ICO(n4266), .CO(n4267) );
CMPR42X1TS mult_x_59_U13 ( .A(mult_x_59_n58), .B(mult_x_59_n48), .C(
mult_x_59_n53), .D(mult_x_59_n19), .ICI(mult_x_59_n16), .S(
mult_x_59_n15), .ICO(mult_x_59_n13), .CO(mult_x_59_n14) );
DFFRXLTS mult_x_58_R_1146 ( .D(n4232), .CK(clk), .RN(n4253), .Q(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N1),
.QN(n1843) );
DFFRXLTS mult_x_58_R_948 ( .D(n350), .CK(clk), .RN(n4252), .Q(mult_x_58_a_0_) );
DFFRXLTS mult_x_58_R_1784 ( .D(n1099), .CK(clk), .RN(n4254), .Q(
mult_x_58_b_3_) );
DFFRXLTS mult_x_58_R_1786 ( .D(n4251), .CK(clk), .RN(n4254), .Q(
mult_x_58_n54) );
DFFRXLTS mult_x_58_R_1532 ( .D(n4250), .CK(clk), .RN(n4254), .Q(
mult_x_58_n29) );
DFFRXLTS mult_x_58_R_1531 ( .D(n4249), .CK(clk), .RN(n4254), .Q(
mult_x_58_n28) );
DFFRXLTS mult_x_58_R_1530 ( .D(n4248), .CK(clk), .RN(n4254), .Q(
mult_x_58_n30) );
CMPR42X2TS mult_x_58_U16 ( .A(mult_x_58_n33), .B(mult_x_58_n31), .C(
mult_x_58_n27), .D(mult_x_58_n25), .ICI(mult_x_58_n28), .S(
mult_x_58_n23), .ICO(mult_x_58_n21), .CO(mult_x_58_n22) );
CMPR42X2TS mult_x_58_U19 ( .A(n4231), .B(n4229), .C(n4236), .D(n4228), .ICI(
n4241), .S(n4248), .ICO(n4249), .CO(n4250) );
DFFRX1TS mult_x_58_R_1528 ( .D(n355), .CK(clk), .RN(n1101), .Q(
mult_x_58_a_5_) );
DFFRX1TS mult_x_58_R_1529 ( .D(n4247), .CK(clk), .RN(n4191), .Q(
mult_x_58_n49) );
DFFRX1TS mult_x_58_R_1455 ( .D(n323), .CK(clk), .RN(n4589), .Q(
mult_x_58_b_5_) );
DFFRX1TS mult_x_58_R_1456 ( .D(n4246), .CK(clk), .RN(n4589), .Q(
mult_x_58_n64) );
DFFRXLTS mult_x_58_R_1373 ( .D(n4245), .CK(clk), .RN(n4254), .Q(
mult_x_58_n25) );
DFFRXLTS mult_x_58_R_1372 ( .D(n4244), .CK(clk), .RN(n4254), .Q(
mult_x_58_n24) );
DFFRX1TS mult_x_58_R_1328 ( .D(n4240), .CK(clk), .RN(n4254), .Q(
mult_x_58_n31) );
DFFRXLTS mult_x_58_R_1287 ( .D(n4238), .CK(clk), .RN(n4253), .Q(
mult_x_58_n26) );
DFFRXLTS mult_x_58_R_1164 ( .D(n4237), .CK(clk), .RN(n4253), .Q(
mult_x_58_n36) );
DFFRXLTS mult_x_58_R_1162 ( .D(n4235), .CK(clk), .RN(n4253), .Q(
mult_x_58_n37) );
CMPR42X2TS mult_x_58_U22 ( .A(n4222), .B(n4223), .C(n4224), .D(n4225), .ICI(
n4230), .S(n4235), .ICO(n4236), .CO(n4237) );
DFFRXLTS mult_x_58_R_1153 ( .D(n4233), .CK(clk), .RN(n4253), .Q(
mult_x_58_n40) );
DFFRX1TS mult_x_58_R_1065 ( .D(n4227), .CK(clk), .RN(n4253), .Q(
mult_x_58_n33) );
DFFRX4TS mult_x_58_R_1045 ( .D(n4226), .CK(clk), .RN(n4252), .Q(
mult_x_58_n43) );
CMPR42X1TS mult_x_58_U13 ( .A(mult_x_58_n58), .B(mult_x_58_n48), .C(
mult_x_58_n53), .D(mult_x_58_n19), .ICI(mult_x_58_n16), .S(
mult_x_58_n15), .ICO(mult_x_58_n13), .CO(mult_x_58_n14) );
DFFRXLTS mult_x_57_R_1313 ( .D(n344), .CK(clk), .RN(n4220), .Q(
mult_x_57_a_0_) );
DFFRXLTS mult_x_57_R_1642 ( .D(n312), .CK(clk), .RN(n1108), .Q(
mult_x_57_b_0_) );
DFFRXLTS mult_x_57_R_1765 ( .D(n4218), .CK(clk), .RN(n4221), .Q(
mult_x_57_n25) );
DFFRXLTS mult_x_57_R_1764 ( .D(n4217), .CK(clk), .RN(n4221), .Q(
mult_x_57_n24) );
DFFRXLTS mult_x_57_R_1701 ( .D(n4216), .CK(clk), .RN(n4221), .Q(
mult_x_57_n41) );
DFFRXLTS mult_x_57_R_1700 ( .D(n4215), .CK(clk), .RN(n4221), .Q(
mult_x_57_n40) );
DFFRXLTS mult_x_57_R_1675 ( .D(n4212), .CK(clk), .RN(n4221), .Q(
mult_x_57_n32) );
DFFRXLTS mult_x_57_R_1674 ( .D(n4211), .CK(clk), .RN(n4221), .Q(
mult_x_57_n31) );
DFFRXLTS mult_x_57_R_1619 ( .D(n4206), .CK(clk), .RN(n4221), .Q(
mult_x_57_n37) );
CMPR42X2TS mult_x_57_U22 ( .A(n4196), .B(n4195), .C(n4194), .D(n4201), .ICI(
n4204), .S(n4206), .ICO(n4207), .CO(n4208) );
DFFRX1TS mult_x_57_R_1590 ( .D(n4203), .CK(clk), .RN(n4220), .Q(
mult_x_57_n38) );
DFFRXLTS mult_x_57_R_1515 ( .D(n4202), .CK(clk), .RN(n4220), .Q(
mult_x_57_n43) );
DFFRXLTS mult_x_57_R_1377 ( .D(n4198), .CK(clk), .RN(n4220), .Q(
mult_x_57_n34) );
DFFRXLTS mult_x_56_R_1520 ( .D(n4178), .CK(clk), .RN(n4192), .Q(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N2),
.QN(n1844) );
DFFRXLTS mult_x_56_R_1678 ( .D(n362), .CK(clk), .RN(n4192), .Q(mult_x_56_n75) );
DFFRX1TS mult_x_56_R_1806 ( .D(n4190), .CK(clk), .RN(n4192), .Q(
mult_x_56_n27) );
DFFRXLTS mult_x_56_R_1805 ( .D(n4189), .CK(clk), .RN(n4192), .Q(
mult_x_56_n26) );
CMPR42X2TS mult_x_56_U17 ( .A(mult_x_56_n33), .B(mult_x_56_n27), .C(
mult_x_56_n31), .D(mult_x_56_n25), .ICI(mult_x_56_n28), .S(
mult_x_56_n23), .ICO(mult_x_56_n21), .CO(mult_x_56_n22) );
DFFRXLTS mult_x_56_R_1788 ( .D(n4187), .CK(clk), .RN(n1129), .Q(
mult_x_56_n28) );
DFFRXLTS mult_x_56_R_1787 ( .D(n4186), .CK(clk), .RN(n1109), .Q(
mult_x_56_n30) );
DFFRXLTS mult_x_56_R_1789 ( .D(n4188), .CK(clk), .RN(n1129), .Q(
mult_x_56_n29) );
DFFRXLTS mult_x_56_R_1783 ( .D(n4185), .CK(clk), .RN(n1107), .Q(
mult_x_56_n53) );
DFFRX1TS mult_x_56_R_1679 ( .D(n4183), .CK(clk), .RN(n4192), .Q(
mult_x_56_n33) );
DFFRXLTS mult_x_56_R_1615 ( .D(n4181), .CK(clk), .RN(n1107), .Q(
mult_x_56_n31) );
DFFRXLTS mult_x_56_R_1581 ( .D(n4180), .CK(clk), .RN(n1109), .Q(
mult_x_56_n25) );
DFFRXLTS mult_x_56_R_1580 ( .D(n4179), .CK(clk), .RN(n1109), .Q(
mult_x_56_n24) );
DFFRX2TS mult_x_56_R_1441 ( .D(n364), .CK(clk), .RN(n4192), .Q(mult_x_56_n63) );
DFFRX1TS mult_x_56_R_1380 ( .D(n365), .CK(clk), .RN(n4192), .Q(mult_x_56_n57) );
DFFRX1TS mult_x_56_R_1379 ( .D(n1040), .CK(clk), .RN(n4192), .Q(
mult_x_56_n48) );
DFFRXLTS mult_x_56_R_1325 ( .D(n4175), .CK(clk), .RN(n1109), .Q(
mult_x_56_n36) );
DFFRXLTS mult_x_56_R_1323 ( .D(n4173), .CK(clk), .RN(n1129), .Q(
mult_x_56_n37) );
DFFRX4TS mult_x_56_R_1182 ( .D(n4170), .CK(clk), .RN(n4191), .Q(
mult_x_56_n43) );
DFFRX4TS mult_x_56_R_1170 ( .D(n4168), .CK(clk), .RN(n4191), .Q(
mult_x_56_n41) );
DFFRXLTS mult_x_56_R_1169 ( .D(n4167), .CK(clk), .RN(n4191), .Q(
mult_x_56_n40) );
DFFSX4TS DP_OP_157J21_126_5719_R_1771 ( .D(n4161), .CK(clk), .SN(n4162), .Q(
DP_OP_157J21_126_5719_n229) );
DFFSX4TS DP_OP_157J21_126_5719_R_1769 ( .D(n4155), .CK(clk), .SN(n4162), .Q(
DP_OP_157J21_126_5719_n254) );
DFFSX4TS DP_OP_157J21_126_5719_R_1622 ( .D(n4153), .CK(clk), .SN(n4162), .Q(
DP_OP_157J21_126_5719_n258) );
DFFSX4TS DP_OP_157J21_126_5719_R_1623 ( .D(n4152), .CK(clk), .SN(n4162), .Q(
DP_OP_157J21_126_5719_n261) );
DFFRX4TS DP_OP_157J21_126_5719_R_1499 ( .D(n412), .CK(clk), .RN(n4162), .Q(
DP_OP_157J21_126_5719_n293) );
DFFRX4TS DP_OP_157J21_126_5719_R_1500 ( .D(n324), .CK(clk), .RN(n4162), .Q(
DP_OP_157J21_126_5719_n298) );
DFFHQX2TS DP_OP_155J21_124_2814_R_1743 ( .D(n4148), .CK(clk), .Q(
DP_OP_155J21_124_2814_n133) );
DFFHQX4TS DP_OP_155J21_124_2814_R_1357 ( .D(n4139), .CK(clk), .Q(
DP_OP_155J21_124_2814_n122) );
DFFHQX4TS DP_OP_155J21_124_2814_R_1207 ( .D(n4132), .CK(clk), .Q(
DP_OP_155J21_124_2814_n123) );
DFFHQX4TS DP_OP_155J21_124_2814_R_1103 ( .D(n4130), .CK(clk), .Q(
DP_OP_155J21_124_2814_n125) );
DFFHQX4TS DP_OP_155J21_124_2814_R_1763 ( .D(n4149), .CK(clk), .Q(
DP_OP_155J21_124_2814_n78) );
DFFHQX4TS DP_OP_155J21_124_2814_R_1346 ( .D(n4137), .CK(clk), .Q(
DP_OP_155J21_124_2814_n120) );
DFFHQX4TS DP_OP_155J21_124_2814_R_1356 ( .D(n4138), .CK(clk), .Q(
DP_OP_155J21_124_2814_n121) );
DFFHQX4TS DP_OP_155J21_124_2814_R_1778 ( .D(DP_OP_155J21_124_2814_net275302),
.CK(clk), .Q(DP_OP_155J21_124_2814_n118) );
DFFHQX4TS DP_OP_155J21_124_2814_R_1345 ( .D(n4136), .CK(clk), .Q(
DP_OP_155J21_124_2814_n119) );
DFFHQX4TS DP_OP_155J21_124_2814_R_1208 ( .D(n4133), .CK(clk), .Q(
DP_OP_155J21_124_2814_n124) );
DFFHQX4TS DP_OP_155J21_124_2814_R_1586 ( .D(n4134), .CK(clk), .Q(
DP_OP_155J21_124_2814_n93) );
DFFHQX4TS DP_OP_155J21_124_2814_R_1761 ( .D(n4131), .CK(clk), .Q(
DP_OP_155J21_124_2814_n126) );
DFFHQX4TS DP_OP_155J21_124_2814_R_1762 ( .D(n4126), .CK(clk), .Q(
DP_OP_155J21_124_2814_n127) );
DFFHQX4TS DP_OP_155J21_124_2814_R_1587 ( .D(n4135), .CK(clk), .Q(
DP_OP_155J21_124_2814_n92) );
DFFHQX4TS DP_OP_155J21_124_2814_R_1723 ( .D(n4147), .CK(clk), .Q(
DP_OP_155J21_124_2814_n134) );
DFFHQX4TS DP_OP_155J21_124_2814_R_1539 ( .D(DP_OP_155J21_124_2814_net274901),
.CK(clk), .Q(DP_OP_155J21_124_2814_n135) );
DFFHQX4TS DP_OP_155J21_124_2814_R_1791 ( .D(n4150), .CK(clk), .Q(
DP_OP_155J21_124_2814_n145) );
DFFHQX4TS DP_OP_155J21_124_2814_R_1633 ( .D(n4146), .CK(clk), .Q(
DP_OP_155J21_124_2814_n147) );
DFFHQX4TS DP_OP_155J21_124_2814_R_1608 ( .D(n4145), .CK(clk), .Q(
DP_OP_155J21_124_2814_n146) );
DFFHQX4TS DP_OP_155J21_124_2814_R_1585 ( .D(n4141), .CK(clk), .Q(
DP_OP_155J21_124_2814_n91) );
DFFHQX8TS DP_OP_155J21_124_2814_R_1383 ( .D(n4140), .CK(clk), .Q(
DP_OP_155J21_124_2814_n88) );
DFFHQX4TS DP_OP_155J21_124_2814_R_1254 ( .D(n4129), .CK(clk), .Q(
DP_OP_155J21_124_2814_n97) );
DFFHQX4TS DP_OP_155J21_124_2814_R_1267 ( .D(n4151), .CK(clk), .Q(
DP_OP_155J21_124_2814_n94) );
DFFHQX4TS DP_OP_155J21_124_2814_R_1555 ( .D(n4127), .CK(clk), .Q(
DP_OP_155J21_124_2814_n128) );
DFFHQX4TS DP_OP_155J21_124_2814_R_1556 ( .D(n4124), .CK(clk), .Q(
DP_OP_155J21_124_2814_n129) );
DFFHQX2TS DP_OP_158J21_127_356_R_1776 ( .D(DP_OP_158J21_127_356_n7), .CK(clk), .Q(n4096) );
DFFQX1TS DP_OP_158J21_127_356_R_802 ( .D(DP_OP_158J21_127_356_n33), .CK(clk),
.Q(n4048) );
DFFHQX4TS DP_OP_158J21_127_356_R_1807 ( .D(DP_OP_158J21_127_356_n56), .CK(
clk), .Q(n4098) );
DFFHQX4TS DP_OP_158J21_127_356_R_1752 ( .D(DP_OP_158J21_127_356_n63), .CK(
clk), .Q(n4095) );
DFFHQX4TS DP_OP_158J21_127_356_R_1501 ( .D(DP_OP_158J21_127_356_n44), .CK(
clk), .Q(n4074) );
DFFSX2TS DP_OP_158J21_127_356_R_1641 ( .D(n4081), .CK(clk), .SN(n4106), .Q(
DP_OP_158J21_127_356_n690) );
DFFSX2TS DP_OP_158J21_127_356_R_1655 ( .D(n4056), .CK(clk), .SN(n4105), .Q(
DP_OP_158J21_127_356_n400) );
DFFSX2TS DP_OP_158J21_127_356_R_1638 ( .D(n4057), .CK(clk), .SN(n4106), .QN(
n4121) );
DFFHQX2TS DP_OP_158J21_127_356_R_722 ( .D(DP_OP_158J21_127_356_n4), .CK(clk),
.Q(n4040) );
DFFHQX4TS DP_OP_158J21_127_356_R_755 ( .D(DP_OP_158J21_127_356_n3), .CK(clk),
.Q(n4042) );
DFFHQX4TS DP_OP_158J21_127_356_R_775 ( .D(n4109), .CK(clk), .Q(n4046) );
DFFRX4TS DP_OP_158J21_127_356_R_1707 ( .D(n4060), .CK(clk), .RN(n4104), .Q(
DP_OP_158J21_127_356_n642) );
DFFRX4TS DP_OP_158J21_127_356_R_1693 ( .D(n4032), .CK(clk), .RN(n4103), .Q(
DP_OP_158J21_127_356_n297) );
DFFRX4TS DP_OP_158J21_127_356_R_1695 ( .D(n4484), .CK(clk), .RN(n4104), .Q(
DP_OP_158J21_127_356_n1048) );
DFFSX2TS DP_OP_158J21_127_356_R_1692 ( .D(n4086), .CK(clk), .SN(n4102), .Q(
DP_OP_158J21_127_356_n307) );
DFFRX4TS DP_OP_158J21_127_356_R_1691 ( .D(n4033), .CK(clk), .RN(n4103), .Q(
DP_OP_158J21_127_356_n648) );
DFFSX4TS DP_OP_158J21_127_356_R_1673 ( .D(n4085), .CK(clk), .SN(n4101), .Q(
DP_OP_158J21_127_356_n617) );
DFFSX4TS DP_OP_158J21_127_356_R_1665 ( .D(n4084), .CK(clk), .SN(n4105), .Q(
DP_OP_158J21_127_356_n381), .QN(n4122) );
DFFSX4TS DP_OP_158J21_127_356_R_1659 ( .D(n4054), .CK(clk), .SN(n4104), .Q(
DP_OP_158J21_127_356_n643) );
DFFSX2TS DP_OP_158J21_127_356_R_1662 ( .D(n4083), .CK(clk), .SN(n4104), .Q(
DP_OP_158J21_127_356_n317) );
DFFSX4TS DP_OP_158J21_127_356_R_1653 ( .D(n4058), .CK(clk), .SN(n4105), .Q(
DP_OP_158J21_127_356_n405), .QN(n882) );
DFFRX1TS DP_OP_158J21_127_356_R_1656 ( .D(n4082), .CK(clk), .RN(n4191), .Q(
DP_OP_158J21_127_356_n398) );
DFFSX2TS DP_OP_158J21_127_356_R_1639 ( .D(n4075), .CK(clk), .SN(n4106), .Q(
DP_OP_158J21_127_356_n681) );
DFFHQX4TS DP_OP_158J21_127_356_R_1524 ( .D(DP_OP_158J21_127_356_n37), .CK(
clk), .Q(n4077) );
DFFSX4TS DP_OP_158J21_127_356_R_1471 ( .D(n4071), .CK(clk), .SN(n4106), .Q(
DP_OP_158J21_127_356_n652) );
DFFSX4TS DP_OP_158J21_127_356_R_1406 ( .D(n4065), .CK(clk), .SN(n4101), .Q(
DP_OP_158J21_127_356_n615) );
DFFSX2TS DP_OP_158J21_127_356_R_1401 ( .D(n4061), .CK(clk), .SN(n4589), .Q(
DP_OP_158J21_127_356_n699) );
DFFSX2TS DP_OP_158J21_127_356_R_1385 ( .D(n4062), .CK(clk), .SN(n4589), .Q(
DP_OP_158J21_127_356_n895) );
DFFSX4TS DP_OP_158J21_127_356_R_1350 ( .D(n4059), .CK(clk), .SN(n4101), .Q(
DP_OP_158J21_127_356_n614) );
DFFSX2TS DP_OP_158J21_127_356_R_1262 ( .D(n4055), .CK(clk), .SN(n4101), .Q(
DP_OP_158J21_127_356_n318) );
DFFRX4TS DP_OP_158J21_127_356_R_1115 ( .D(n4107), .CK(clk), .RN(n4106), .Q(
DP_OP_158J21_127_356_n931) );
DFFSX4TS DP_OP_158J21_127_356_R_1077 ( .D(n4041), .CK(clk), .SN(n1100), .Q(
DP_OP_158J21_127_356_n894) );
DFFHQX4TS DP_OP_153J21_122_3500_R_1489 ( .D(n4027), .CK(clk), .Q(
DP_OP_153J21_122_3500_n169) );
DFFHQX4TS DP_OP_153J21_122_3500_R_1564 ( .D(n4030), .CK(clk), .Q(
DP_OP_153J21_122_3500_n167) );
DFFHQX4TS DP_OP_153J21_122_3500_R_1685 ( .D(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N0),
.CK(clk), .Q(DP_OP_153J21_122_3500_n243) );
DFFHQX4TS DP_OP_153J21_122_3500_R_1683 ( .D(n4028), .CK(clk), .Q(
DP_OP_153J21_122_3500_n195) );
DFFHQX4TS DP_OP_153J21_122_3500_R_1490 ( .D(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N1),
.CK(clk), .Q(DP_OP_153J21_122_3500_n244) );
DFFHQX4TS DP_OP_153J21_122_3500_R_1488 ( .D(n4026), .CK(clk), .Q(
DP_OP_153J21_122_3500_n194) );
DFFSX4TS DP_OP_158J21_127_356_R_1654 ( .D(n4070), .CK(clk), .SN(n1132), .Q(
DP_OP_158J21_127_356_n399) );
DFFRX4TS DP_OP_158J21_127_356_R_1157 ( .D(n4051), .CK(clk), .RN(n1107), .Q(
DP_OP_158J21_127_356_n653) );
DFFRX4TS DP_OP_158J21_127_356_R_1483 ( .D(n334), .CK(clk), .RN(n4103), .Q(
DP_OP_158J21_127_356_n1035), .QN(n1839) );
DFFRX4TS DP_OP_158J21_127_356_R_1671 ( .D(n1099), .CK(clk), .RN(n4102), .Q(
DP_OP_158J21_127_356_n1045) );
DFFRX2TS DP_OP_158J21_127_356_R_1451 ( .D(n4496), .CK(clk), .RN(n1100), .Q(
DP_OP_158J21_127_356_n1056) );
DFFRX4TS DP_OP_158J21_127_356_R_1690 ( .D(n4498), .CK(clk), .RN(n4103), .Q(
DP_OP_158J21_127_356_n1049) );
DFFRX2TS DP_OP_158J21_127_356_R_1718 ( .D(n4091), .CK(clk), .RN(n1112), .Q(
DP_OP_158J21_127_356_n651) );
DFFRX2TS DP_OP_158J21_127_356_R_1449 ( .D(n4050), .CK(clk), .RN(n1105), .Q(
DP_OP_158J21_127_356_n656) );
DFFRX4TS DP_OP_157J21_126_5719_R_1738 ( .D(n4159), .CK(clk), .RN(n1108), .Q(
DP_OP_157J21_126_5719_n246) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_23_ ( .D(n335), .CK(clk), .RN(
n1108), .Q(Op_MY[23]) );
DFFRX4TS DP_OP_158J21_127_356_R_1660 ( .D(n4036), .CK(clk), .RN(n4102), .Q(
DP_OP_158J21_127_356_n644) );
DFFRX4TS DP_OP_158J21_127_356_R_1636 ( .D(n4064), .CK(clk), .RN(n1131), .Q(
DP_OP_158J21_127_356_n693), .QN(n4117) );
DFFRX4TS DP_OP_158J21_127_356_R_1661 ( .D(n4037), .CK(clk), .RN(n4102), .Q(
DP_OP_158J21_127_356_n645) );
DFFRX2TS DP_OP_158J21_127_356_R_1664 ( .D(n4049), .CK(clk), .RN(n1109), .Q(
DP_OP_158J21_127_356_n655) );
DFFRX4TS DP_OP_159J21_128_5719_R_1749 ( .D(n4322), .CK(clk), .RN(n4323), .Q(
DP_OP_159J21_128_5719_n246) );
DFFRX2TS Barrel_Shifter_module_Output_Reg_Q_reg_0_ ( .D(n191), .CK(clk),
.RN(n1102), .Q(Sgf_normalized_result[0]) );
DFFHQX4TS DP_OP_158J21_127_356_R_1525 ( .D(DP_OP_158J21_127_356_n38), .CK(
clk), .Q(n4078) );
DFFRX4TS DP_OP_158J21_127_356_R_1713 ( .D(n4111), .CK(clk), .RN(n3631), .Q(
DP_OP_158J21_127_356_n411), .QN(n420) );
DFFRX4TS DP_OP_158J21_127_356_R_1709 ( .D(n4481), .CK(clk), .RN(n4104), .Q(
DP_OP_158J21_127_356_n1053) );
DFFHQX4TS DP_OP_158J21_127_356_R_1751 ( .D(DP_OP_158J21_127_356_n62), .CK(
clk), .Q(n4094) );
DFFRX2TS DP_OP_158J21_127_356_R_1663 ( .D(n4052), .CK(clk), .RN(n1110), .Q(
DP_OP_158J21_127_356_n654) );
DFFRX4TS DP_OP_158J21_127_356_R_1800 ( .D(n4097), .CK(clk), .RN(n3631), .Q(
DP_OP_158J21_127_356_n692), .QN(n4112) );
DFFRX4TS DP_OP_158J21_127_356_R_1711 ( .D(n4480), .CK(clk), .RN(n4104), .Q(
DP_OP_158J21_127_356_n312) );
DFFRXLTS R_927 ( .D(n238), .CK(clk), .RN(n4442), .Q(n4508) );
DFFRHQX2TS R_1435 ( .D(DP_OP_156J21_125_3370_n360), .CK(clk), .RN(1'b1), .Q(
Sgf_operation_Result[0]) );
DFFRHQX2TS Adder_M_Add_Subt_Result_Q_reg_0_ ( .D(n306), .CK(clk), .RN(n1132),
.Q(Add_result[0]) );
DFFRHQX2TS final_result_ieee_Module_Final_Result_IEEE_Q_reg_31_ ( .D(n262),
.CK(clk), .RN(n1130), .Q(final_result_ieee[31]) );
DFFRHQX2TS Adder_M_Add_Subt_Result_Q_reg_23_ ( .D(n283), .CK(clk), .RN(n1131), .Q(Add_result[23]) );
DFFSHQX4TS Operands_load_reg_YMRegister_Q_reg_30_ ( .D(n1840), .CK(clk),
.SN(n1132), .Q(n4409) );
DFFHQX8TS Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_Data_S_o_reg_10_ (
.D(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N10),
.CK(clk), .Q(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[10]) );
DFFSX4TS R_1727 ( .D(n4555), .CK(clk), .SN(n4441), .Q(n4473) );
DFFSX4TS R_1730 ( .D(n4551), .CK(clk), .SN(n4441), .Q(n4470) );
DFFSX4TS R_1668 ( .D(n4577), .CK(clk), .SN(n1112), .Q(n4485) );
DFFSX4TS add_x_19_R_1803 ( .D(add_x_19_n282), .CK(clk), .SN(n4538), .Q(n4378) );
DFFSX4TS R_1535 ( .D(n4586), .CK(clk), .SN(n1103), .Q(n4494) );
DFFSX4TS R_1725 ( .D(n4558), .CK(clk), .SN(n4105), .Q(n4475) );
DFFSX4TS R_1731 ( .D(n4550), .CK(clk), .SN(n4105), .Q(n4469) );
DFFSX4TS DP_OP_156J21_125_3370_R_1426 ( .D(n1081), .CK(clk), .SN(n4346), .Q(
n4330) );
DFFSX4TS R_1754 ( .D(n4567), .CK(clk), .SN(n1112), .Q(n4463) );
DFFSX4TS DP_OP_156J21_125_3370_R_1462 ( .D(DP_OP_156J21_125_3370_n83), .CK(
clk), .SN(n1092), .Q(n4332) );
DFFSX4TS DP_OP_156J21_125_3370_R_1315 ( .D(DP_OP_156J21_125_3370_n84), .CK(
clk), .SN(n4346), .QN(n421) );
DFFSX4TS DP_OP_156J21_125_3370_R_1658 ( .D(DP_OP_156J21_125_3370_n200), .CK(
clk), .SN(n450), .Q(n4339) );
DFFRHQX2TS Exp_module_Oflow_A_m_Q_reg_0_ ( .D(n271), .CK(clk), .RN(n1130),
.Q(Exp_module_Overflow_flag_A) );
DFFRHQX4TS DP_OP_158J21_127_356_R_1799_IP ( .D(n4020), .CK(clk), .RN(n1130),
.Q(n4113) );
DFFSX1TS Barrel_Shifter_module_Output_Reg_Q_reg_22_ ( .D(n901), .CK(clk),
.SN(n1132), .Q(n4413), .QN(Sgf_normalized_result[22]) );
DFFRHQX4TS DP_OP_158J21_127_356_R_1374 ( .D(n323), .CK(clk), .RN(n1131), .Q(
DP_OP_158J21_127_356_n1047) );
DFFSHQX4TS DP_OP_158J21_127_356_R_1714 ( .D(n4067), .CK(clk), .SN(n1130),
.Q(DP_OP_158J21_127_356_n397) );
DFFRHQX4TS DP_OP_158J21_127_356_R_1400_IP ( .D(n4018), .CK(clk), .RN(n1132),
.Q(n4116) );
DFFHQX1TS DP_OP_158J21_127_356_R_766 ( .D(DP_OP_158J21_127_356_n5), .CK(clk),
.Q(n4043) );
DFFRX4TS DP_OP_158J21_127_356_R_1614 ( .D(n4080), .CK(clk), .RN(n4102), .Q(
DP_OP_158J21_127_356_n612) );
DFFRX4TS mult_x_57_R_1643 ( .D(n4209), .CK(clk), .RN(n4101), .Q(
mult_x_57_n69) );
DFFRX4TS mult_x_57_R_1681 ( .D(n4213), .CK(clk), .RN(n1103), .Q(
mult_x_57_n10) );
DFFRX4TS mult_x_59_R_951 ( .D(n360), .CK(clk), .RN(n4283), .Q(mult_x_59_a_4_) );
DFFRX4TS Barrel_Shifter_module_Output_Reg_Q_reg_2_ ( .D(n193), .CK(clk),
.RN(n1112), .Q(Sgf_normalized_result[2]) );
DFFRX4TS DP_OP_158J21_127_356_R_1613 ( .D(n1098), .CK(clk), .RN(n4103), .Q(
DP_OP_158J21_127_356_n1043) );
DFFRX4TS DP_OP_158J21_127_356_R_1475 ( .D(n4035), .CK(clk), .RN(n4103), .Q(
DP_OP_158J21_127_356_n647) );
DFFRX4TS Barrel_Shifter_module_Output_Reg_Q_reg_4_ ( .D(n195), .CK(clk),
.RN(n1104), .Q(Sgf_normalized_result[4]), .QN(n4434) );
DFFRX4TS Barrel_Shifter_module_Output_Reg_Q_reg_8_ ( .D(n199), .CK(clk),
.RN(n1104), .Q(Sgf_normalized_result[8]), .QN(n4417) );
DFFRX4TS mult_x_57_R_1165 ( .D(n1116), .CK(clk), .RN(n4219), .Q(
mult_x_57_b_1_) );
DFFRX4TS mult_x_57_R_1540 ( .D(n316), .CK(clk), .RN(n4220), .Q(
mult_x_57_b_4_) );
DFFRX4TS DP_OP_158J21_127_356_R_1482 ( .D(n322), .CK(clk), .RN(n4102), .Q(
DP_OP_158J21_127_356_n1046), .QN(n4115) );
DFFRX4TS mult_x_59_R_1175 ( .D(n327), .CK(clk), .RN(n4283), .Q(
mult_x_59_b_3_) );
DFFRX4TS mult_x_58_R_1154 ( .D(n4234), .CK(clk), .RN(n4253), .Q(
mult_x_58_n41) );
DFFRX4TS Sel_B_Q_reg_1_ ( .D(n308), .CK(clk), .RN(n1111), .Q(
FSM_selector_B_1_), .QN(n895) );
DFFRX4TS DP_OP_158J21_127_356_R_1408 ( .D(n4066), .CK(clk), .RN(n1130), .Q(
Sgf_operation_EVEN1_result_A_adder[5]), .QN(n876) );
DFFRX4TS mult_x_59_R_959 ( .D(n4260), .CK(clk), .RN(n4283), .Q(mult_x_59_n33) );
DFFRX4TS mult_x_59_R_1326 ( .D(n4272), .CK(clk), .RN(n4284), .Q(
mult_x_59_n31) );
DFFRX4TS mult_x_58_R_1242 ( .D(n322), .CK(clk), .RN(n4253), .Q(
mult_x_58_b_4_) );
DFFRX4TS DP_OP_158J21_127_356_R_473 ( .D(n4034), .CK(clk), .RN(n4102), .Q(
DP_OP_158J21_127_356_n646) );
DFFRX4TS mult_x_59_R_1527 ( .D(n4280), .CK(clk), .RN(n1101), .Q(
mult_x_59_n49) );
DFFHQX8TS Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_10_ (
.D(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N10),
.CK(clk), .Q(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[10]) );
DFFRX4TS DP_OP_158J21_127_356_R_1612 ( .D(n1123), .CK(clk), .RN(n4102), .Q(
DP_OP_158J21_127_356_n599) );
DFFSX4TS DP_OP_158J21_127_356_R_1582 ( .D(n4063), .CK(clk), .SN(n4589), .Q(
DP_OP_158J21_127_356_n685), .QN(n4110) );
DFFSX4TS DP_OP_158J21_127_356_R_1431 ( .D(n4068), .CK(clk), .SN(n4102), .Q(
DP_OP_158J21_127_356_n609), .QN(n899) );
DFFRX4TS Barrel_Shifter_module_Output_Reg_Q_reg_10_ ( .D(n201), .CK(clk),
.RN(n1110), .Q(Sgf_normalized_result[10]), .QN(n4416) );
DFFRX4TS Barrel_Shifter_module_Output_Reg_Q_reg_3_ ( .D(n194), .CK(clk),
.RN(n1104), .Q(Sgf_normalized_result[3]), .QN(n4411) );
DFFHQX4TS DP_OP_158J21_127_356_R_1745 ( .D(DP_OP_158J21_127_356_n53), .CK(
clk), .Q(n4092) );
DFFHQX4TS DP_OP_158J21_127_356_R_1746 ( .D(n1772), .CK(clk), .Q(n4093) );
DFFRX4TS mult_x_57_R_1596 ( .D(n317), .CK(clk), .RN(n4220), .Q(
mult_x_57_b_5_) );
DFFRX4TS mult_x_57_R_1413 ( .D(n315), .CK(clk), .RN(n4220), .Q(
mult_x_57_b_3_) );
DFFRX4TS mult_x_59_R_1012 ( .D(n4264), .CK(clk), .RN(n4283), .Q(
mult_x_59_n40) );
DFFRX4TS mult_x_59_R_1031 ( .D(n4265), .CK(clk), .RN(n4283), .Q(
mult_x_59_n37) );
DFFRX4TS mult_x_57_R_1669 ( .D(n349), .CK(clk), .RN(n1100), .Q(
mult_x_57_a_5_) );
DFFRHQX4TS Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_Data_S_o_reg_6_ (
.D(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N6), .CK(clk), .RN(1'b1), .Q(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[6])
);
DFFHQX8TS Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_12_ (
.D(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N12),
.CK(clk), .Q(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[12]) );
DFFHQX8TS DP_OP_155J21_124_2814_R_1588 ( .D(n4143), .CK(clk), .Q(
DP_OP_155J21_124_2814_n90) );
DFFRX4TS DP_OP_158J21_127_356_R_1637 ( .D(n4079), .CK(clk), .RN(n1131), .QN(
n424) );
DFFSX4TS DP_OP_159J21_128_5719_R_1747 ( .D(n4316), .CK(clk), .SN(n4323), .Q(
DP_OP_159J21_128_5719_n255) );
DFFRX4TS DP_OP_158J21_127_356_R_1430 ( .D(n1040), .CK(clk), .RN(n4103), .Q(
DP_OP_158J21_127_356_n1033), .QN(n900) );
DFFSX4TS DP_OP_158J21_127_356_R_1450 ( .D(n4069), .CK(clk), .SN(n4589), .Q(
DP_OP_158J21_127_356_n388), .QN(n4118) );
DFFSX4TS DP_OP_157J21_126_5719_R_1737 ( .D(n4156), .CK(clk), .SN(n1109), .Q(
DP_OP_157J21_126_5719_n248) );
DFFRX4TS add_x_19_R_1795 ( .D(Sgf_operation_EVEN1_Q_left[1]), .CK(clk), .RN(
n1094), .Q(n4377) );
DFFRX2TS mult_x_57_R_1479 ( .D(n4200), .CK(clk), .RN(n4220), .Q(
mult_x_57_n45) );
DFFHQX8TS DP_OP_154J21_123_2814_R_1603 ( .D(n4304), .CK(clk), .Q(
DP_OP_154J21_123_2814_n87) );
DFFRX4TS DP_OP_158J21_127_356_R_1477 ( .D(n4072), .CK(clk), .RN(n4103), .Q(
DP_OP_158J21_127_356_n314) );
DFFHQX8TS Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_Data_S_o_reg_11_ (
.D(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N11),
.CK(clk), .Q(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[11]) );
DFFRX2TS mult_x_59_R_1634 ( .D(n4281), .CK(clk), .RN(n4284), .Q(mult_x_59_n8) );
DFFRX4TS mult_x_59_R_1239 ( .D(n328), .CK(clk), .RN(n4283), .Q(
mult_x_59_b_4_) );
DFFRX4TS mult_x_57_R_1213 ( .D(n348), .CK(clk), .RN(n4219), .Q(
mult_x_57_a_4_) );
DFFSX4TS DP_OP_156J21_125_3370_R_1793 ( .D(DP_OP_156J21_125_3370_n208), .CK(
clk), .SN(n4445), .Q(n4344) );
DFFRX2TS mult_x_58_R_1341 ( .D(n4242), .CK(clk), .RN(n4254), .Q(mult_x_58_n9) );
DFFSX4TS DP_OP_158J21_127_356_R_1484 ( .D(n4073), .CK(clk), .SN(n4101), .Q(
DP_OP_158J21_127_356_n608) );
DFFQX4TS R_1194 ( .D(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N7),
.CK(clk), .Q(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[7]) );
DFFHQX8TS DP_OP_154J21_123_2814_R_1568 ( .D(n4303), .CK(clk), .Q(
DP_OP_154J21_123_2814_n90) );
DFFSX4TS DP_OP_158J21_127_356_R_1798 ( .D(n4090), .CK(clk), .SN(n1130), .Q(
DP_OP_158J21_127_356_n707), .QN(n425) );
DFFSX4TS DP_OP_156J21_125_3370_R_1792 ( .D(DP_OP_156J21_125_3370_n205), .CK(
clk), .SN(n4382), .Q(n4343) );
DFFRX4TS mult_x_57_R_1361 ( .D(n347), .CK(clk), .RN(n4252), .Q(
mult_x_57_a_3_) );
DFFHQX8TS Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_Data_S_o_reg_12_ (
.D(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N12),
.CK(clk), .Q(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[12]) );
DFFHQX4TS DP_OP_155J21_124_2814_R_1595 ( .D(n4144), .CK(clk), .Q(
DP_OP_155J21_124_2814_n87) );
DFFSX4TS R_1704 ( .D(n4534), .CK(clk), .SN(n1132), .Q(n4482) );
DFFRX2TS DP_OP_156J21_125_3370_R_1774 ( .D(DP_OP_156J21_125_3370_n92), .CK(
clk), .RN(n4443), .Q(n4341) );
DFFHQX4TS DP_OP_155J21_124_2814_R_1557 ( .D(n4142), .CK(clk), .Q(
DP_OP_155J21_124_2814_n84) );
DFFRX4TS DP_OP_158J21_127_356_R_1429 ( .D(n1121), .CK(clk), .RN(n4103), .Q(
DP_OP_158J21_127_356_n1044) );
DFFRX4TS DP_OP_158J21_127_356_R_1476 ( .D(n4499), .CK(clk), .RN(n4103), .Q(
DP_OP_158J21_127_356_n1050) );
DFFHQX4TS Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_13_ (
.D(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N13), .CK(clk), .Q(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[13]) );
DFFSHQX8TS DP_OP_158J21_127_356_R_1672_IP ( .D(n1095), .CK(clk), .SN(n1131),
.Q(n4017) );
DFFRX2TS Sel_C_Q_reg_0_ ( .D(n214), .CK(clk), .RN(n1131), .Q(FSM_selector_C),
.QN(n4395) );
DFFRX4TS Barrel_Shifter_module_Output_Reg_Q_reg_18_ ( .D(n209), .CK(clk),
.RN(n1110), .Q(Sgf_normalized_result[18]), .QN(n4415) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_8_ ( .D(n223), .CK(clk), .RN(
n1125), .Q(P_Sgf[8]) );
DFFRX4TS R_1492 ( .D(n312), .CK(clk), .RN(n4252), .Q(Op_MY[0]), .QN(n879) );
DFFRX4TS mult_x_57_R_1682 ( .D(n4214), .CK(clk), .RN(n4219), .Q(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N1),
.QN(n940) );
DFFRX4TS mult_x_59_R_894 ( .D(n4259), .CK(clk), .RN(n4106), .Q(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N1),
.QN(n941) );
DFFRX4TS Adder_M_Add_Subt_Result_Q_reg_18_ ( .D(n288), .CK(clk), .RN(n4539),
.Q(Add_result[18]), .QN(n4399) );
DFFRX4TS Adder_M_Add_Subt_Result_Q_reg_11_ ( .D(n295), .CK(clk), .RN(n4540),
.Q(Add_result[11]), .QN(n4406) );
DFFRX4TS Adder_M_Add_Subt_Result_Q_reg_10_ ( .D(n296), .CK(clk), .RN(n4540),
.Q(Add_result[10]), .QN(n4407) );
DFFRX1TS R_1504 ( .D(n1123), .CK(clk), .RN(n4589), .Q(Op_MY[19]) );
DFFRX4TS Exp_module_exp_result_m_Q_reg_1_ ( .D(n279), .CK(clk), .RN(n4219),
.Q(exp_oper_result[1]), .QN(n1851) );
DFFRX4TS Adder_M_Add_Subt_Result_Q_reg_22_ ( .D(n284), .CK(clk), .RN(n4539),
.Q(Add_result[22]), .QN(n4396) );
DFFRX4TS Adder_M_Add_Subt_Result_Q_reg_19_ ( .D(n287), .CK(clk), .RN(n4539),
.Q(Add_result[19]), .QN(n4403) );
DFFHQX8TS Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_10_ (
.D(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N10), .CK(clk), .Q(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[10]) );
DFFRHQX2TS DP_OP_159J21_128_5719_R_1628 ( .D(n4319), .CK(clk), .RN(n4323),
.Q(net292709) );
DFFRHQX2TS mult_x_57_R_1376 ( .D(n4197), .CK(clk), .RN(n4220), .Q(net292731)
);
DFFRHQX2TS mult_x_57_R_1598 ( .D(n4205), .CK(clk), .RN(n4221), .Q(net292765)
);
DFFRHQX2TS DP_OP_158J21_127_356_R_1708 ( .D(n4088), .CK(clk), .RN(n4104),
.Q(n1072) );
DFFSX4TS DP_OP_157J21_126_5719_R_1770 ( .D(n4160), .CK(clk), .SN(n1109), .Q(
DP_OP_157J21_126_5719_n255) );
DFFRHQX8TS R_1289 ( .D(n317), .CK(clk), .RN(n4543), .Q(n1065) );
DFFRHQX2TS mult_x_56_R_1440 ( .D(n334), .CK(clk), .RN(n1108), .Q(n1053) );
DFFHQX8TS Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_12_ (
.D(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N12), .CK(clk), .Q(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[12]) );
DFFHQX8TS Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_11_ (
.D(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N11), .CK(clk), .Q(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[11]) );
DFFRHQX8TS R_1232 ( .D(n323), .CK(clk), .RN(n4447), .Q(n1050) );
DFFSX2TS add_x_19_R_57 ( .D(add_x_19_n76), .CK(clk), .SN(n4381), .Q(n4350)
);
DFFSX4TS DP_OP_158J21_127_356_R_1694 ( .D(n4087), .CK(clk), .SN(n4104), .Q(
DP_OP_158J21_127_356_n319) );
DFFRHQX2TS mult_x_58_R_1109 ( .D(n353), .CK(clk), .RN(n4253), .Q(n1045) );
DFFSX4TS DP_OP_156J21_125_3370_R_1657 ( .D(DP_OP_156J21_125_3370_n197), .CK(
clk), .SN(n450), .Q(n4338) );
DFFSX1TS DP_OP_156J21_125_3370_R_1801 ( .D(DP_OP_156J21_125_3370_n173), .CK(
clk), .SN(n4346), .Q(n4345) );
DFFQX2TS R_1756 ( .D(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N10),
.CK(clk), .Q(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[10]) );
DFFRX1TS R_1505 ( .D(n1087), .CK(clk), .RN(n4447), .Q(Op_MY[13]), .QN(n933)
);
DFFRX1TS R_1510 ( .D(n1116), .CK(clk), .RN(n4440), .Q(Op_MY[1]), .QN(n932)
);
DFFRX1TS R_1497 ( .D(n324), .CK(clk), .RN(n4447), .Q(Op_MY[12]), .QN(n931)
);
DFFHQX2TS R_877 ( .D(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N5),
.CK(clk), .Q(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[5]) );
DFFRX1TS R_1570 ( .D(n1038), .CK(clk), .RN(n4440), .Q(Op_MY[2]), .QN(n927)
);
DFFRX4TS mult_x_56_R_1144 ( .D(n4166), .CK(clk), .RN(n4191), .Q(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N1),
.QN(n1845) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_24_ ( .D(n336), .CK(clk), .RN(
n1129), .Q(Op_MY[24]), .QN(n4392) );
DFFSHQX4TS DP_OP_157J21_126_5719_R_1736 ( .D(n4154), .CK(clk), .SN(n1110),
.Q(n1071) );
DFFQX2TS R_1300 ( .D(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N7),
.CK(clk), .Q(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[7]) );
DFFQX4TS R_1705 ( .D(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N11),
.CK(clk), .Q(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[11]) );
DFFRX2TS Sgf_operation_EVEN1_finalreg_Q_reg_7_ ( .D(n222), .CK(clk), .RN(
n4536), .Q(P_Sgf[7]) );
DFFRX4TS mult_x_56_R_1781 ( .D(n366), .CK(clk), .RN(n4191), .Q(mult_x_56_n51) );
DFFRX2TS Sgf_operation_EVEN1_finalreg_Q_reg_6_ ( .D(n221), .CK(clk), .RN(
n4536), .Q(P_Sgf[6]) );
CMPR42X1TS mult_x_57_U13 ( .A(mult_x_57_n58), .B(mult_x_57_n48), .C(
mult_x_57_n53), .D(mult_x_57_n19), .ICI(mult_x_57_n16), .S(
mult_x_57_n15), .ICO(mult_x_57_n13), .CO(mult_x_57_n14) );
CMPR42X2TS mult_x_57_U14 ( .A(mult_x_57_n59), .B(mult_x_57_n26), .C(
mult_x_57_n24), .D(mult_x_57_n20), .ICI(mult_x_57_n21), .S(
mult_x_57_n18), .ICO(mult_x_57_n16), .CO(mult_x_57_n17) );
CMPR42X2TS mult_x_57_U19 ( .A(mult_x_57_n71), .B(mult_x_57_n38), .C(
mult_x_57_n35), .D(mult_x_57_n34), .ICI(mult_x_57_n32), .S(
mult_x_57_n30), .ICO(mult_x_57_n28), .CO(mult_x_57_n29) );
DFFRXLTS R_848 ( .D(n235), .CK(clk), .RN(n4442), .Q(n4510) );
DFFRXLTS R_924 ( .D(n236), .CK(clk), .RN(n4442), .Q(n4509) );
DFFRXLTS R_934 ( .D(n237), .CK(clk), .RN(n4442), .Q(n4507) );
DFFRXLTS R_1073 ( .D(n233), .CK(clk), .RN(n4538), .Q(n4506) );
DFFHQX4TS DP_OP_154J21_123_2814_R_1259 ( .D(n4292), .CK(clk), .Q(
DP_OP_154J21_123_2814_n123) );
DFFSX2TS R_1758 ( .D(n4546), .CK(clk), .SN(n4105), .Q(n4461) );
DFFSRHQX4TS R_1575 ( .D(n1086), .CK(clk), .SN(1'b1), .RN(n1130), .Q(
Op_MY[14]) );
DFFSRHQX4TS mult_x_59_R_1526 ( .D(n361), .CK(clk), .SN(1'b1), .RN(n1131),
.Q(mult_x_59_a_5_) );
DFFHQX4TS DP_OP_158J21_127_356_R_1523 ( .D(DP_OP_158J21_127_356_n71), .CK(
clk), .Q(n4076) );
DFFHQX4TS DP_OP_153J21_122_3500_R_1684 ( .D(n4031), .CK(clk), .Q(
DP_OP_153J21_122_3500_n127) );
DFFHQX4TS Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_13_ (
.D(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N13),
.CK(clk), .Q(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[13]) );
DFFHQX4TS Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_11_ (
.D(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N11),
.CK(clk), .Q(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[11]) );
DFFHQX4TS DP_OP_155J21_124_2814_R_1268 ( .D(n4125), .CK(clk), .Q(
DP_OP_155J21_124_2814_n144) );
DFFSX4TS DP_OP_158J21_127_356_R_1715 ( .D(n4089), .CK(clk), .SN(n4105), .QN(
n889) );
DFFRX4TS R_1822 ( .D(n831), .CK(clk), .RN(n4323), .Q(n858) );
DFFSX2TS R_1831 ( .D(add_x_19_n271), .CK(clk), .SN(n4535), .Q(n826) );
DFFSX2TS R_1832 ( .D(n1091), .CK(clk), .SN(n4538), .Q(n825) );
DFFSX2TS R_1833 ( .D(n4584), .CK(clk), .SN(n3631), .Q(n824) );
DFFSX2TS R_1834 ( .D(n440), .CK(clk), .SN(n4444), .Q(n823) );
DFFSX4TS R_1835 ( .D(n1623), .CK(clk), .SN(n4383), .Q(n822) );
DFFHQX8TS R_1836 ( .D(DP_OP_158J21_127_356_n70), .CK(clk), .Q(n821) );
DFFSX2TS R_1837 ( .D(DP_OP_156J21_125_3370_n52), .CK(clk), .SN(n4347), .Q(
n820) );
DFFSX4TS R_1838 ( .D(DP_OP_156J21_125_3370_n66), .CK(clk), .SN(n1092), .Q(
n819) );
DFFSX2TS R_1839 ( .D(n1850), .CK(clk), .SN(n1093), .Q(n818), .QN(n817) );
DFFSX2TS R_1840 ( .D(Sgf_operation_EVEN1_Q_left[3]), .CK(clk), .SN(n4382),
.Q(n816) );
DFFSX2TS R_1841 ( .D(Sgf_operation_EVEN1_Q_left[2]), .CK(clk), .SN(n4382),
.Q(n815) );
DFFSX2TS R_1842 ( .D(Sgf_operation_EVEN1_Q_left[4]), .CK(clk), .SN(n1093),
.Q(n814) );
DFFSX2TS R_1843 ( .D(Sgf_operation_EVEN1_Q_left[5]), .CK(clk), .SN(n4536),
.Q(n813) );
DFFRX2TS R_1844 ( .D(add_x_19_n75), .CK(clk), .RN(n4384), .Q(n812), .QN(n422) );
DFFRX2TS R_1845 ( .D(add_x_19_n57), .CK(clk), .RN(n4384), .Q(n811) );
DFFSX2TS R_1846 ( .D(add_x_19_n85), .CK(clk), .SN(n4381), .Q(n810), .QN(n809) );
DFFRX2TS R_1847 ( .D(add_x_19_n104), .CK(clk), .RN(n450), .Q(n808) );
DFFSX2TS R_1848 ( .D(Sgf_operation_EVEN1_Q_left[9]), .CK(clk), .SN(n4381),
.Q(n807) );
DFFSX2TS R_1849 ( .D(Sgf_operation_EVEN1_Q_left[10]), .CK(clk), .SN(n4380),
.Q(n806) );
DFFRX2TS R_1850 ( .D(DP_OP_156J21_125_3370_n82), .CK(clk), .RN(n4535), .Q(
n805) );
DFFSX2TS R_1851 ( .D(DP_OP_156J21_125_3370_n65), .CK(clk), .SN(n1094), .Q(
n804), .QN(n803) );
DFFRX2TS R_1852 ( .D(add_x_19_n39), .CK(clk), .RN(n4384), .Q(n802), .QN(n418) );
DFFSX2TS R_1853 ( .D(Sgf_operation_EVEN1_S_B[15]), .CK(clk), .SN(n4382), .Q(
n801) );
DFFSX2TS R_1854 ( .D(DP_OP_156J21_125_3370_n61), .CK(clk), .SN(n4346), .Q(
n800) );
DFFSX2TS R_1855 ( .D(n1633), .CK(clk), .SN(n4346), .Q(n799) );
DFFSX2TS R_1856 ( .D(n2313), .CK(clk), .SN(n4381), .Q(n798) );
DFFSX2TS R_1857 ( .D(DP_OP_156J21_125_3370_n45), .CK(clk), .SN(n4347), .Q(
n797) );
DFFSX4TS R_1858 ( .D(DP_OP_156J21_125_3370_n70), .CK(clk), .SN(n4445), .Q(
n796) );
DFFSX2TS R_1859 ( .D(Sgf_operation_EVEN1_Q_left[12]), .CK(clk), .SN(n4380),
.Q(n795) );
DFFSX2TS R_1860 ( .D(Sgf_operation_EVEN1_S_B[14]), .CK(clk), .SN(n1093), .Q(
n794) );
DFFSX2TS R_1862 ( .D(DP_OP_156J21_125_3370_n36), .CK(clk), .SN(n4347), .Q(
n792) );
DFFRX2TS R_1863 ( .D(n3623), .CK(clk), .RN(n4384), .Q(n791) );
DFFSX2TS R_1864 ( .D(Sgf_operation_EVEN1_Q_left[8]), .CK(clk), .SN(n4380),
.Q(n790) );
DFFSX2TS R_1865 ( .D(Sgf_operation_EVEN1_Q_left[7]), .CK(clk), .SN(n4380),
.Q(n789) );
DFFRX2TS R_1867 ( .D(add_x_19_n114), .CK(clk), .RN(n4381), .Q(n787) );
DFFSX2TS R_1868 ( .D(n1846), .CK(clk), .SN(n1092), .Q(n786) );
DFFRX2TS R_1869 ( .D(add_x_19_n94), .CK(clk), .RN(n450), .Q(n785), .QN(n784)
);
DFFRX2TS R_1870 ( .D(add_x_19_n47), .CK(clk), .RN(n4384), .Q(n783) );
DFFSX2TS R_1871 ( .D(DP_OP_156J21_125_3370_n33), .CK(clk), .SN(n4347), .QN(
n782) );
DFFSX2TS R_1872 ( .D(DP_OP_156J21_125_3370_n80), .CK(clk), .SN(n4346), .Q(
n781) );
DFFSX4TS DP_OP_157J21_126_5719_R_1625 ( .D(n4158), .CK(clk), .SN(n4162), .Q(
n859) );
DFFHQX8TS Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_Data_S_o_reg_11_ (
.D(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N11),
.CK(clk), .Q(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[11]) );
DFFRHQX4TS DP_OP_157J21_126_5719_R_1624 ( .D(n4157), .CK(clk), .RN(n4162),
.Q(n1084) );
DFFHQX8TS DP_OP_155J21_124_2814_R_1777 ( .D(DP_OP_155J21_124_2814_net275301),
.CK(clk), .Q(DP_OP_155J21_124_2814_n117) );
DFFSX4TS DP_OP_158J21_127_356_R_1405 ( .D(n4053), .CK(clk), .SN(n4104), .Q(
DP_OP_158J21_127_356_n607) );
CMPR42X2TS mult_x_58_U14 ( .A(mult_x_58_n59), .B(mult_x_58_n26), .C(
mult_x_58_n24), .D(mult_x_58_n20), .ICI(mult_x_58_n21), .S(
mult_x_58_n18), .ICO(mult_x_58_n16), .CO(mult_x_58_n17) );
CMPR42X2TS mult_x_56_U15 ( .A(mult_x_56_n58), .B(mult_x_56_n26), .C(
mult_x_56_n20), .D(mult_x_56_n24), .ICI(mult_x_56_n21), .S(
mult_x_56_n18), .ICO(mult_x_56_n16), .CO(mult_x_56_n17) );
DFFSX1TS R_1767 ( .D(n4571), .CK(clk), .SN(n1111), .Q(n4457) );
DFFSX4TS R_1829 ( .D(n1091), .CK(clk), .SN(n4346), .Q(n830), .QN(n829) );
DFFSX4TS R_1830 ( .D(n1850), .CK(clk), .SN(n4445), .Q(n828), .QN(n827) );
DFFRX4TS R_1496 ( .D(n412), .CK(clk), .RN(n4589), .Q(Op_MY[18]) );
DFFRX2TS mult_x_57_R_1620 ( .D(n4207), .CK(clk), .RN(n4221), .Q(
mult_x_57_n35) );
DFFRX4TS mult_x_59_R_1453 ( .D(n329), .CK(clk), .RN(n4284), .Q(
mult_x_59_b_5_) );
DFFRX4TS mult_x_58_R_1785 ( .D(n354), .CK(clk), .RN(n4252), .Q(
mult_x_58_a_4_) );
DFFRX4TS mult_x_56_R_1519 ( .D(n4177), .CK(clk), .RN(n4192), .Q(mult_x_56_n9) );
DFFRX4TS add_x_19_R_1358 ( .D(add_x_19_n237), .CK(clk), .RN(n4346), .Q(n4369) );
DFFSX4TS R_1866 ( .D(Sgf_operation_EVEN1_S_B[13]), .CK(clk), .SN(n4383), .Q(
n788) );
DFFSX4TS R_1861 ( .D(n4585), .CK(clk), .SN(n4219), .Q(n793) );
DFFHQX2TS DP_OP_155J21_124_2814_R_993 ( .D(n4128), .CK(clk), .Q(n4123) );
DFFHQX2TS DP_OP_154J21_123_2814_R_1566 ( .D(n4296), .CK(clk), .Q(
DP_OP_154J21_123_2814_n93) );
DFFSX2TS DP_OP_156J21_125_3370_R_1463 ( .D(DP_OP_156J21_125_3370_n71), .CK(
clk), .SN(n4346), .Q(n4333) );
DFFQX2TS R_1722 ( .D(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N10),
.CK(clk), .Q(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[10]) );
DFFQX2TS R_1538 ( .D(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N9),
.CK(clk), .Q(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[9]) );
DFFHQX4TS R_654 ( .D(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N1),
.CK(clk), .Q(Sgf_operation_EVEN1_Q_left[1]) );
DFFHQX2TS R_1485 ( .D(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N2),
.CK(clk), .Q(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[2]) );
DFFQX1TS R_1742 ( .D(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N11),
.CK(clk), .Q(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[11]) );
DFFHQX1TS DP_OP_158J21_127_356_R_1809 ( .D(DP_OP_158J21_127_356_n51), .CK(
clk), .Q(n4100) );
DFFHQX1TS DP_OP_158J21_127_356_R_1808 ( .D(DP_OP_158J21_127_356_n46), .CK(
clk), .Q(n4099) );
DFFQX4TS DP_OP_153J21_122_3500_R_1563 ( .D(n4029), .CK(clk), .Q(
DP_OP_153J21_122_3500_n166) );
DFFHQX1TS DP_OP_158J21_127_356_R_768 ( .D(DP_OP_158J21_127_356_n6), .CK(clk),
.Q(n4044) );
DFFSX1TS DP_OP_156J21_125_3370_R_1802 ( .D(DP_OP_156J21_125_3370_n73), .CK(
clk), .SN(n1094), .QN(n878) );
DFFSX1TS add_x_19_R_1041 ( .D(add_x_19_n238), .CK(clk), .SN(n4382), .Q(n4362) );
DFFX2TS R_713 ( .D(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N3),
.CK(clk), .Q(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[3]), .QN(
n4544) );
DFFRX2TS R_969 ( .D(n329), .CK(clk), .RN(n4447), .Q(Op_MY[17]), .QN(n1836)
);
DFFQX1TS DP_OP_158J21_127_356_R_801 ( .D(n4119), .CK(clk), .Q(n4047) );
DFFRHQX2TS DP_OP_158J21_127_356_R_1640_IP ( .D(n885), .CK(clk), .RN(n1132),
.Q(n4120) );
DFFQX1TS R_1085 ( .D(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N6),
.CK(clk), .Q(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[6]) );
DFFSX1TS add_x_19_R_1592 ( .D(add_x_19_n265), .CK(clk), .SN(n4537), .Q(n4373) );
DFFSX1TS add_x_19_R_1593 ( .D(add_x_19_n246), .CK(clk), .SN(n4538), .Q(n4374) );
DFFHQX1TS DP_OP_158J21_127_356_R_572 ( .D(DP_OP_158J21_127_356_n2), .CK(clk),
.Q(n4039) );
DFFRX2TS DP_OP_158J21_127_356_R_1717 ( .D(n355), .CK(clk), .RN(n1108), .Q(
DP_OP_158J21_127_356_n859), .QN(n4114) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_26_ ( .D(n338), .CK(clk), .RN(
n1129), .Q(Op_MY[26]), .QN(n4390) );
DFFSX1TS add_x_19_R_482 ( .D(Sgf_operation_EVEN1_Q_left[13]), .CK(clk), .SN(
n4380), .QN(n930) );
DFFRXLTS add_x_19_R_567 ( .D(Sgf_operation_EVEN1_Q_left[13]), .CK(clk), .RN(
n4384), .Q(n4357) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_29_ ( .D(n341), .CK(clk), .RN(
n1108), .Q(Op_MY[29]), .QN(n4387) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_25_ ( .D(n337), .CK(clk), .RN(
n1109), .Q(Op_MY[25]), .QN(n4391) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_27_ ( .D(n339), .CK(clk), .RN(
n1109), .Q(Op_MY[27]), .QN(n4389) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_28_ ( .D(n340), .CK(clk), .RN(
n1129), .Q(Op_MY[28]), .QN(n4388) );
DFFHQX1TS DP_OP_158J21_127_356_R_774 ( .D(n4108), .CK(clk), .Q(n4045) );
DFFSX1TS R_1813 ( .D(Exp_module_Data_S[5]), .CK(clk), .SN(n4441), .Q(n4453)
);
DFFSX1TS R_1816 ( .D(Exp_module_Data_S[4]), .CK(clk), .SN(n4252), .Q(n4451)
);
DFFSX1TS R_1819 ( .D(Exp_module_Data_S[6]), .CK(clk), .SN(n3631), .Q(n4449)
);
DFFQX2TS R_1632 ( .D(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N9),
.CK(clk), .Q(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[9]) );
DFFQX1TS DP_OP_158J21_127_356_R_570 ( .D(n3369), .CK(clk), .Q(n4038) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_25_ ( .D(n369), .CK(clk), .RN(
n4440), .Q(Op_MX[25]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_24_ ( .D(n368), .CK(clk), .RN(
n4441), .Q(Op_MX[24]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_27_ ( .D(n371), .CK(clk), .RN(
n4441), .Q(Op_MX[27]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_26_ ( .D(n370), .CK(clk), .RN(
n4440), .Q(Op_MX[26]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_23_ ( .D(n367), .CK(clk), .RN(
n4106), .Q(Op_MX[23]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_28_ ( .D(n372), .CK(clk), .RN(
n4441), .Q(Op_MX[28]) );
DFFRX2TS mult_x_57_R_1214 ( .D(n4193), .CK(clk), .RN(n4219), .Q(
mult_x_57_n55) );
DFFSX1TS R_1810 ( .D(Exp_module_Data_S[8]), .CK(clk), .SN(n4101), .Q(n4455)
);
DFFRX2TS mult_x_57_R_1458 ( .D(n4199), .CK(clk), .RN(n4220), .Q(
mult_x_57_n71) );
DFFRX1TS mult_x_57_R_1621 ( .D(n4208), .CK(clk), .RN(n4221), .Q(
mult_x_57_n36) );
DFFSX2TS R_1766 ( .D(n4572), .CK(clk), .SN(n1111), .Q(n4458) );
DFFSX2TS R_1719 ( .D(n4576), .CK(clk), .SN(n1112), .Q(n4479) );
DFFSX1TS R_1726 ( .D(n4557), .CK(clk), .SN(n4105), .Q(n4474) );
DFFSX1TS R_1729 ( .D(n4553), .CK(clk), .SN(n4105), .Q(n4471) );
DFFSX1TS R_1734 ( .D(n4563), .CK(clk), .SN(n1111), .Q(n4466) );
DFFSX1TS R_1732 ( .D(n4549), .CK(clk), .SN(n3631), .Q(n4468) );
DFFSX1TS R_1721 ( .D(n4574), .CK(clk), .SN(n1111), .Q(n4477) );
DFFRX2TS mult_x_57_R_1670 ( .D(n4210), .CK(clk), .RN(n1100), .Q(
mult_x_57_n49) );
DFFSX2TS R_1667 ( .D(n4578), .CK(clk), .SN(n1112), .Q(n4486) );
DFFSX1TS R_1728 ( .D(n4554), .CK(clk), .SN(n4102), .Q(n4472) );
DFFQX1TS R_1459 ( .D(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N2),
.CK(clk), .Q(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[2]) );
DFFRX2TS Barrel_Shifter_module_Output_Reg_Q_reg_1_ ( .D(n192), .CK(clk),
.RN(n1110), .Q(Sgf_normalized_result[1]) );
DFFRX2TS Barrel_Shifter_module_Output_Reg_Q_reg_9_ ( .D(n200), .CK(clk),
.RN(n1110), .Q(Sgf_normalized_result[9]), .QN(n4427) );
DFFRX2TS Barrel_Shifter_module_Output_Reg_Q_reg_7_ ( .D(n198), .CK(clk),
.RN(n1104), .Q(Sgf_normalized_result[7]), .QN(n4426) );
DFFRX2TS Barrel_Shifter_module_Output_Reg_Q_reg_6_ ( .D(n197), .CK(clk),
.RN(n1104), .Q(Sgf_normalized_result[6]), .QN(n4425) );
DFFSX1TS add_x_19_R_61 ( .D(add_x_19_n40), .CK(clk), .SN(n1094), .Q(n4351),
.QN(n935) );
DFFRX2TS Barrel_Shifter_module_Output_Reg_Q_reg_11_ ( .D(n202), .CK(clk),
.RN(n1110), .Q(Sgf_normalized_result[11]), .QN(n4428) );
DFFRX2TS Barrel_Shifter_module_Output_Reg_Q_reg_12_ ( .D(n203), .CK(clk),
.RN(n1110), .Q(Sgf_normalized_result[12]), .QN(n4414) );
DFFRX2TS Barrel_Shifter_module_Output_Reg_Q_reg_5_ ( .D(n196), .CK(clk),
.RN(n1104), .Q(Sgf_normalized_result[5]), .QN(n4410) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_7_ ( .D(n273), .CK(clk), .RN(n4101),
.Q(exp_oper_result[7]), .QN(n1838) );
DFFRX2TS mult_x_59_R_1454 ( .D(n4279), .CK(clk), .RN(n4284), .Q(
mult_x_59_n64) );
DFFRX1TS mult_x_58_R_1288 ( .D(n4239), .CK(clk), .RN(n4253), .Q(
mult_x_58_n27) );
DFFSRHQX2TS Sgf_operation_EVEN1_finalreg_Q_reg_9_ ( .D(n224), .CK(clk), .SN(
1'b1), .RN(n1092), .Q(P_Sgf[9]) );
DFFRXLTS mult_x_58_R_1020 ( .D(n318), .CK(clk), .RN(n4252), .Q(
mult_x_58_b_0_) );
DFFRX1TS mult_x_59_R_1285 ( .D(n4270), .CK(clk), .RN(n4283), .Q(
mult_x_59_n26) );
DFFSX2TS add_x_19_R_1688 ( .D(add_x_19_n244), .CK(clk), .SN(n4383), .Q(n1847), .QN(n1848) );
DFFSX1TS R_1760 ( .D(n4533), .CK(clk), .SN(n4441), .Q(n4459) );
DFFRX2TS R_1548 ( .D(n1097), .CK(clk), .RN(n1108), .Q(Op_MY[21]) );
DFFQX1TS R_1790 ( .D(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N11),
.CK(clk), .Q(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[11]) );
DFFRXLTS mult_x_56_R_1677 ( .D(n412), .CK(clk), .RN(n4192), .Q(mult_x_56_n50) );
DFFSRHQX2TS mult_x_56_R_1782 ( .D(n1097), .CK(clk), .SN(1'b1), .RN(n1131),
.Q(mult_x_56_n47) );
DFFSX2TS R_35 ( .D(n3910), .CK(clk), .SN(n4535), .QN(n936) );
DFFRXLTS mult_x_59_R_872 ( .D(n324), .CK(clk), .RN(n4106), .Q(mult_x_59_b_0_) );
DFFRHQX2TS Adder_M_Add_Subt_Result_Q_reg_4_ ( .D(n302), .CK(clk), .RN(n1130),
.Q(Add_result[4]) );
DFFSRHQX2TS Adder_M_Add_Subt_Result_Q_reg_1_ ( .D(n305), .CK(clk), .SN(1'b1),
.RN(n1132), .Q(Add_result[1]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_9_ ( .D(n297), .CK(clk), .RN(n4540),
.Q(Add_result[9]), .QN(n4408) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_12_ ( .D(n294), .CK(clk), .RN(n4540),
.Q(Add_result[12]), .QN(n4405) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_13_ ( .D(n293), .CK(clk), .RN(n4540),
.Q(Add_result[13]), .QN(n4404) );
DFFRX2TS mult_x_58_R_1342 ( .D(n4243), .CK(clk), .RN(n4254), .Q(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N2),
.QN(n934) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_15_ ( .D(n291), .CK(clk), .RN(n4540),
.Q(Add_result[15]), .QN(n4401) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_14_ ( .D(n292), .CK(clk), .RN(n4540),
.Q(Add_result[14]), .QN(n4402) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_17_ ( .D(n289), .CK(clk), .RN(n4540),
.Q(Add_result[17]), .QN(n4400) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_21_ ( .D(n285), .CK(clk), .RN(n4539),
.Q(Add_result[21]), .QN(n4397) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_20_ ( .D(n286), .CK(clk), .RN(n4539),
.Q(Add_result[20]), .QN(n4398) );
AO22X1TS U405 ( .A0(n3904), .A1(Sgf_normalized_result[0]), .B0(
final_result_ieee[0]), .B1(n3905), .Y(n190) );
NAND2X2TS U406 ( .A(n3915), .B(n3921), .Y(n4574) );
AOI21X2TS U407 ( .A0(n4111), .A1(n3275), .B0(n3274), .Y(n4089) );
NAND2X2TS U408 ( .A(n3915), .B(n3922), .Y(n4549) );
NAND2X1TS U409 ( .A(n1481), .B(n3230), .Y(n3231) );
INVX2TS U410 ( .A(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N8),
.Y(net288677) );
NAND2BX2TS U411 ( .AN(n3226), .B(n3227), .Y(n1479) );
NAND2X1TS U412 ( .A(n3800), .B(n242), .Y(n3715) );
INVX2TS U413 ( .A(n3874), .Y(n3900) );
CLKAND2X2TS U414 ( .A(n315), .B(n345), .Y(n4194) );
INVX2TS U415 ( .A(DP_OP_158J21_127_356_n33), .Y(n3342) );
AND2X2TS U416 ( .A(n1038), .B(n346), .Y(n4195) );
AND2X2TS U417 ( .A(n1099), .B(n350), .Y(n3509) );
OR2X4TS U418 ( .A(n3311), .B(n3310), .Y(n4119) );
AND2X2TS U419 ( .A(n1120), .B(n351), .Y(n3510) );
NAND2X2TS U420 ( .A(n3354), .B(n3353), .Y(n3357) );
AND2X2TS U421 ( .A(n322), .B(n351), .Y(n4231) );
INVX2TS U422 ( .A(net291594), .Y(n456) );
CLKAND2X2TS U423 ( .A(n412), .B(n364), .Y(n3450) );
NAND2X1TS U424 ( .A(n3850), .B(n246), .Y(n3758) );
AOI2BB2X1TS U425 ( .B0(n3932), .B1(n241), .A0N(n1126), .A1N(n4429), .Y(n3719) );
NOR2X1TS U426 ( .A(n3843), .B(FS_Module_state_reg[2]), .Y(n689) );
AND2X2TS U427 ( .A(n1096), .B(n364), .Y(n4176) );
NAND2X1TS U428 ( .A(n1695), .B(n2610), .Y(n2611) );
INVX2TS U429 ( .A(add_x_19_n265), .Y(n2443) );
CLKAND2X2TS U430 ( .A(n334), .B(n364), .Y(n3460) );
NOR2X4TS U431 ( .A(n3791), .B(n691), .Y(n690) );
NAND2X1TS U432 ( .A(n2993), .B(n2992), .Y(n2994) );
AND2X2TS U433 ( .A(n1040), .B(n363), .Y(n3459) );
CLKAND2X2TS U434 ( .A(n1038), .B(n345), .Y(n3486) );
AND2X2TS U435 ( .A(n1116), .B(n344), .Y(n3495) );
INVX3TS U436 ( .A(n3874), .Y(n3902) );
NAND2XLTS U437 ( .A(n1091), .B(Exp_module_Overflow_flag_A), .Y(n1386) );
NAND2X1TS U438 ( .A(n440), .B(P_Sgf[16]), .Y(n1787) );
CLKBUFX3TS U439 ( .A(n3874), .Y(n3870) );
INVX4TS U440 ( .A(DP_OP_158J21_127_356_n46), .Y(n1671) );
NAND2XLTS U441 ( .A(n3296), .B(n3295), .Y(n3297) );
NAND2X6TS U442 ( .A(n432), .B(n1621), .Y(n1620) );
NAND2X2TS U443 ( .A(n2836), .B(n1443), .Y(n3615) );
CLKBUFX3TS U444 ( .A(n3840), .Y(n4014) );
NOR2BX1TS U445 ( .AN(n1901), .B(n1830), .Y(n1829) );
NAND2X6TS U446 ( .A(n1544), .B(n3022), .Y(n3028) );
NOR2X4TS U447 ( .A(n1806), .B(n1391), .Y(n1805) );
NAND3X6TS U448 ( .A(n1570), .B(n3026), .C(n1569), .Y(
DP_OP_158J21_127_356_n70) );
NAND2XLTS U449 ( .A(n3210), .B(n3209), .Y(n3211) );
AOI21X2TS U450 ( .A0(n3372), .A1(n3371), .B0(n1765), .Y(n1339) );
CLKAND2X2TS U451 ( .A(n2983), .B(n3439), .Y(n1075) );
NOR2X2TS U452 ( .A(n887), .B(n3356), .Y(n1752) );
NAND2X2TS U453 ( .A(n3438), .B(n3442), .Y(n3443) );
CLKXOR2X2TS U454 ( .A(net288731), .B(n2508), .Y(n1293) );
NOR2BX1TS U455 ( .AN(n2647), .B(n1416), .Y(n1415) );
NAND2X4TS U456 ( .A(n432), .B(n3032), .Y(n1718) );
XOR2X1TS U457 ( .A(n3584), .B(n3583), .Y(n1532) );
XOR2X2TS U458 ( .A(net288689), .B(n2522), .Y(n470) );
XOR2X2TS U459 ( .A(net288590), .B(n2578), .Y(n1552) );
INVX2TS U460 ( .A(n3444), .Y(n1704) );
NOR2X1TS U461 ( .A(n1127), .B(n4399), .Y(n1416) );
INVX6TS U462 ( .A(n1433), .Y(n1621) );
INVX2TS U463 ( .A(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N5),
.Y(net288731) );
NOR2X1TS U464 ( .A(n1127), .B(n4396), .Y(n1830) );
INVX2TS U465 ( .A(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N7),
.Y(net288590) );
INVX2TS U466 ( .A(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N7),
.Y(n3001) );
INVX2TS U467 ( .A(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N5),
.Y(n2508) );
NAND2X1TS U468 ( .A(n4011), .B(n3838), .Y(n3839) );
INVX3TS U469 ( .A(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N8),
.Y(net288678) );
INVX2TS U470 ( .A(n1813), .Y(n1681) );
INVX2TS U471 ( .A(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N6),
.Y(n2522) );
NAND2X6TS U472 ( .A(n2866), .B(n2865), .Y(n1356) );
INVX3TS U473 ( .A(n1539), .Y(n2605) );
INVX4TS U474 ( .A(n868), .Y(n3618) );
INVX4TS U475 ( .A(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N6),
.Y(n3578) );
AND2X2TS U476 ( .A(n326), .B(n357), .Y(n3532) );
INVX2TS U477 ( .A(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N6),
.Y(n3577) );
INVX2TS U478 ( .A(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N7),
.Y(n3002) );
AND2X2TS U479 ( .A(n1116), .B(n345), .Y(n3491) );
INVX12TS U480 ( .A(n677), .Y(n3228) );
INVX6TS U481 ( .A(n3374), .Y(n3386) );
AND2X2TS U482 ( .A(n319), .B(n350), .Y(n3513) );
CLKAND2X2TS U483 ( .A(n323), .B(n350), .Y(n3498) );
NOR2X4TS U484 ( .A(n1734), .B(n1392), .Y(n1391) );
INVX2TS U485 ( .A(n2990), .Y(n1763) );
NAND2X1TS U486 ( .A(n3289), .B(n3291), .Y(n3290) );
CLKAND2X2TS U487 ( .A(n1113), .B(n358), .Y(n3534) );
NAND2X6TS U488 ( .A(add_x_19_n76), .B(add_x_19_n68), .Y(n3623) );
NAND2X4TS U489 ( .A(n3010), .B(n3009), .Y(n3032) );
OR2X4TS U490 ( .A(n3626), .B(n915), .Y(n1789) );
NAND2X1TS U491 ( .A(n3396), .B(n3395), .Y(n3397) );
OAI2BB1X1TS U492 ( .A0N(n449), .A1N(n659), .B0(n2459), .Y(n658) );
NOR2X6TS U493 ( .A(n1777), .B(n2243), .Y(n3607) );
INVX4TS U494 ( .A(n1020), .Y(add_x_19_n95) );
NAND2X2TS U495 ( .A(n4497), .B(n3326), .Y(n4056) );
NAND2X2TS U496 ( .A(n364), .B(n352), .Y(n4061) );
OR2X4TS U497 ( .A(n1113), .B(n1085), .Y(n3324) );
NAND2XLTS U498 ( .A(n1530), .B(n3635), .Y(n691) );
NAND2X4TS U499 ( .A(n2990), .B(n2989), .Y(n1653) );
INVX2TS U500 ( .A(n3045), .Y(n1814) );
NAND2XLTS U501 ( .A(n3827), .B(n3825), .Y(n2085) );
NAND2BXLTS U502 ( .AN(n1379), .B(net287489), .Y(n1377) );
AND2X4TS U503 ( .A(n1085), .B(n347), .Y(n3489) );
NOR2X6TS U504 ( .A(n622), .B(n621), .Y(net290399) );
BUFX3TS U505 ( .A(n607), .Y(n484) );
NAND2X2TS U506 ( .A(n2843), .B(n2842), .Y(n2844) );
NAND3X6TS U507 ( .A(n1756), .B(n2989), .C(n2986), .Y(n1652) );
XOR2X1TS U508 ( .A(net287489), .B(n3400), .Y(n1380) );
NAND3X6TS U509 ( .A(n1756), .B(n1784), .C(n2986), .Y(n1783) );
NOR2X2TS U510 ( .A(n3204), .B(n3208), .Y(n3201) );
AOI22X1TS U511 ( .A0(n3913), .A1(Add_result[19]), .B0(
Sgf_normalized_result[18]), .B1(n4533), .Y(n2647) );
CMPR32X2TS U512 ( .A(n1053), .B(mult_x_56_n51), .C(mult_x_56_n13), .CO(n3473), .S(n3468) );
INVX6TS U513 ( .A(net287249), .Y(n622) );
NAND2X1TS U514 ( .A(n3043), .B(n3042), .Y(net287248) );
NAND2X1TS U515 ( .A(n2982), .B(n2981), .Y(n3439) );
INVX6TS U516 ( .A(n2860), .Y(n2989) );
INVX6TS U517 ( .A(n3023), .Y(n1689) );
INVX2TS U518 ( .A(n3204), .Y(n3218) );
BUFX3TS U519 ( .A(n3034), .Y(n1519) );
AO22X2TS U520 ( .A0(n2744), .A1(n1722), .B0(n2745), .B1(n2746), .Y(n2752) );
NAND2X6TS U521 ( .A(n2815), .B(n2814), .Y(n3022) );
NAND2X1TS U522 ( .A(n3199), .B(n3198), .Y(n3209) );
NAND2BX1TS U523 ( .AN(n829), .B(n4522), .Y(n660) );
NAND2X1TS U524 ( .A(n3391), .B(n3390), .Y(n3392) );
INVX3TS U525 ( .A(n3437), .Y(n2984) );
INVX8TS U526 ( .A(n1316), .Y(n1038) );
INVX8TS U527 ( .A(n495), .Y(n1717) );
INVX12TS U528 ( .A(n1217), .Y(n1568) );
OR2X2TS U529 ( .A(n3799), .B(FSM_selector_C), .Y(n3667) );
INVX2TS U530 ( .A(n3441), .Y(n2977) );
NOR2X6TS U531 ( .A(n3221), .B(n3226), .Y(n3213) );
NOR2X4TS U532 ( .A(n3626), .B(n3627), .Y(n2608) );
INVX4TS U533 ( .A(n1095), .Y(n1096) );
OAI21X2TS U534 ( .A0(n3294), .A1(n3291), .B0(n3295), .Y(n3329) );
NAND2X6TS U535 ( .A(n982), .B(n2223), .Y(n3610) );
NOR2X6TS U536 ( .A(n2860), .B(n2991), .Y(n1784) );
NOR2X6TS U537 ( .A(n513), .B(net287250), .Y(net290403) );
INVX6TS U538 ( .A(n3874), .Y(n3905) );
NAND2X4TS U539 ( .A(n1813), .B(n607), .Y(n3000) );
INVX2TS U540 ( .A(net287973), .Y(net290615) );
NAND2X1TS U541 ( .A(n2853), .B(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[7]), .Y(n731) );
INVX8TS U542 ( .A(n3620), .Y(n3621) );
AOI21X1TS U543 ( .A0(n3828), .A1(n3827), .B0(n3826), .Y(n1389) );
AOI21X2TS U544 ( .A0(n2090), .A1(n2072), .B0(n2076), .Y(n1270) );
AOI21X2TS U545 ( .A0(n2090), .A1(n2056), .B0(n2055), .Y(n1271) );
NAND2X4TS U546 ( .A(n2741), .B(n2740), .Y(n2987) );
OR2X6TS U547 ( .A(n1539), .B(n1778), .Y(n868) );
INVX2TS U548 ( .A(n1299), .Y(n1298) );
INVX2TS U549 ( .A(n3285), .Y(n3256) );
NOR2X6TS U550 ( .A(n2741), .B(n2740), .Y(n2860) );
NOR2X6TS U551 ( .A(n2971), .B(n1068), .Y(n3444) );
NAND2X2TS U552 ( .A(n2976), .B(n2975), .Y(n3441) );
NOR2X6TS U553 ( .A(n3195), .B(n3194), .Y(n3221) );
NOR2X6TS U554 ( .A(n2743), .B(n2742), .Y(n2991) );
AND2X2TS U555 ( .A(mult_x_57_b_5_), .B(mult_x_57_a_5_), .Y(n3400) );
NOR2X1TS U556 ( .A(n436), .B(n1367), .Y(n2749) );
OR2X4TS U557 ( .A(n3037), .B(n891), .Y(n2610) );
NOR2X4TS U558 ( .A(n3192), .B(n3193), .Y(n3226) );
INVX4TS U559 ( .A(n2015), .Y(n3603) );
INVX8TS U560 ( .A(n1318), .Y(n1087) );
NAND2X1TS U561 ( .A(n2059), .B(n2058), .Y(n2060) );
CLKAND2X2TS U562 ( .A(mult_x_59_a_5_), .B(mult_x_59_b_4_), .Y(n3550) );
INVX2TS U563 ( .A(underflow_flag), .Y(n4587) );
NAND2X1TS U564 ( .A(n3739), .B(n3737), .Y(n3730) );
NOR2X4TS U565 ( .A(n2736), .B(n2737), .Y(n3356) );
NAND2X1TS U566 ( .A(n362), .B(n350), .Y(n4041) );
OR2X2TS U567 ( .A(n2853), .B(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[7]), .Y(n1077) );
NAND2X1TS U568 ( .A(n2450), .B(n2460), .Y(n2451) );
CLKBUFX2TS U569 ( .A(n3846), .Y(n1530) );
BUFX8TS U570 ( .A(n3012), .Y(n759) );
OR2X2TS U571 ( .A(n3830), .B(n2084), .Y(n3827) );
NAND2X4TS U572 ( .A(n3157), .B(n3156), .Y(n3230) );
NAND2X1TS U573 ( .A(n2456), .B(n2455), .Y(n2457) );
NAND2X1TS U574 ( .A(n894), .B(n2074), .Y(n2054) );
NAND2X1TS U575 ( .A(n3754), .B(n3753), .Y(n3755) );
NAND2XLTS U576 ( .A(n2070), .B(n2073), .Y(n2071) );
NAND2X4TS U577 ( .A(n1683), .B(n1682), .Y(n2540) );
NAND2X2TS U578 ( .A(n361), .B(n349), .Y(n3295) );
INVX2TS U579 ( .A(n2506), .Y(n2495) );
OR2X4TS U580 ( .A(n411), .B(n1115), .Y(n3396) );
NOR2X4TS U581 ( .A(n653), .B(n1506), .Y(n652) );
CLKAND2X2TS U582 ( .A(n3853), .B(n3919), .Y(n1273) );
NAND2X6TS U583 ( .A(n623), .B(n1813), .Y(n629) );
NAND2X4TS U584 ( .A(n2738), .B(n2739), .Y(n2996) );
NAND2X6TS U585 ( .A(n1513), .B(n1527), .Y(n2317) );
AOI21X2TS U586 ( .A0(n2065), .A1(n2090), .B0(n2064), .Y(n1272) );
INVX8TS U587 ( .A(n3608), .Y(n1776) );
NAND2X2TS U588 ( .A(n1893), .B(n3793), .Y(n1895) );
INVX1TS U589 ( .A(n2057), .Y(n2059) );
NOR2X1TS U590 ( .A(n935), .B(n817), .Y(n952) );
BUFX6TS U591 ( .A(n330), .Y(n411) );
AND2X6TS U592 ( .A(n2220), .B(n2221), .Y(n915) );
INVX6TS U593 ( .A(n2995), .Y(n1366) );
OR2X2TS U594 ( .A(n1117), .B(n951), .Y(n950) );
NAND2X6TS U595 ( .A(n3037), .B(n891), .Y(n1695) );
INVX6TS U596 ( .A(net287974), .Y(n438) );
CLKINVX6TS U597 ( .A(n1442), .Y(n627) );
NAND2X2TS U598 ( .A(n412), .B(n1115), .Y(n3395) );
CLKAND2X2TS U599 ( .A(mult_x_57_a_5_), .B(mult_x_57_b_4_), .Y(net287493) );
CLKAND2X2TS U600 ( .A(mult_x_57_b_5_), .B(mult_x_57_a_4_), .Y(net287494) );
NAND2X6TS U601 ( .A(n1020), .B(n1684), .Y(n1683) );
CLKINVX6TS U602 ( .A(n3234), .Y(n672) );
NAND2X6TS U603 ( .A(n1725), .B(n1505), .Y(n973) );
OR2X4TS U604 ( .A(n2078), .B(n2079), .Y(n897) );
NAND2XLTS U605 ( .A(n2585), .B(n2584), .Y(n2586) );
NOR2X2TS U606 ( .A(n3306), .B(n437), .Y(n3350) );
CLKINVX6TS U607 ( .A(n3370), .Y(n1765) );
NAND2X2TS U608 ( .A(n3736), .B(n3739), .Y(n3741) );
NOR2X2TS U609 ( .A(n3786), .B(n791), .Y(n3785) );
NAND2X4TS U610 ( .A(n430), .B(n1579), .Y(n616) );
NAND3X2TS U611 ( .A(n539), .B(n3793), .C(n435), .Y(n537) );
NAND2X2TS U612 ( .A(n3793), .B(n3788), .Y(n3790) );
NAND2X1TS U613 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[5]),
.B(n2859), .Y(n1553) );
NOR2X4TS U614 ( .A(n535), .B(n549), .Y(n548) );
INVX6TS U615 ( .A(n3384), .Y(n507) );
BUFX6TS U616 ( .A(n1816), .Y(n1506) );
CMPR32X2TS U617 ( .A(n3191), .B(n3190), .C(n3189), .CO(n3199), .S(n3196) );
NAND2X4TS U618 ( .A(n3155), .B(n3154), .Y(n3234) );
INVX3TS U619 ( .A(n3155), .Y(n676) );
CLKMX2X2TS U620 ( .A(Op_MX[30]), .B(exp_oper_result[7]), .S0(FSM_selector_A),
.Y(n2081) );
AO21X1TS U621 ( .A0(n2716), .A1(n461), .B0(n2715), .Y(n2729) );
NAND2X1TS U622 ( .A(n2017), .B(n1998), .Y(n1997) );
CLKAND2X2TS U623 ( .A(mult_x_57_a_5_), .B(mult_x_57_b_3_), .Y(mult_x_57_n48)
);
INVX8TS U624 ( .A(n3033), .Y(n1777) );
INVX2TS U625 ( .A(n3154), .Y(n678) );
NOR2X1TS U626 ( .A(n1520), .B(n1852), .Y(n2981) );
CLKBUFX2TS U627 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[3]),
.Y(n1523) );
NAND2X2TS U628 ( .A(n2783), .B(n2782), .Y(n3379) );
INVX2TS U629 ( .A(n2453), .Y(n3754) );
NAND2XLTS U630 ( .A(Sgf_normalized_result[3]), .B(Sgf_normalized_result[2]),
.Y(n3808) );
NAND2XLTS U631 ( .A(n2536), .B(n2535), .Y(n2537) );
NOR2X2TS U632 ( .A(n1262), .B(n437), .Y(n3352) );
NAND2X6TS U633 ( .A(n2936), .B(n2935), .Y(n1435) );
OAI21X1TS U634 ( .A0(n2594), .A1(n2580), .B0(n2579), .Y(n2581) );
NOR2X4TS U635 ( .A(n1343), .B(n1133), .Y(n1342) );
NAND2X1TS U636 ( .A(Sgf_normalized_result[18]), .B(n4001), .Y(n3816) );
NAND2X4TS U637 ( .A(n1664), .B(n1663), .Y(n1477) );
NOR2X4TS U638 ( .A(n762), .B(n783), .Y(n1892) );
NOR2X6TS U639 ( .A(n912), .B(n3145), .Y(n3240) );
NAND2XLTS U640 ( .A(n880), .B(n2598), .Y(n2599) );
AND2X2TS U641 ( .A(n1149), .B(n1707), .Y(n1079) );
NAND2X6TS U642 ( .A(n2785), .B(n2784), .Y(n3370) );
NOR2X2TS U643 ( .A(n1564), .B(n3185), .Y(n3190) );
OAI22X1TS U644 ( .A0(n2360), .A1(n1118), .B0(n2364), .B1(n3305), .Y(n2367)
);
OAI2BB1X2TS U645 ( .A0N(n2003), .A1N(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[3]), .B0(n2002), .Y(
n1936) );
ADDFX2TS U646 ( .A(n2436), .B(n2435), .CI(n2434), .CO(n2643), .S(n2432) );
NOR2X2TS U647 ( .A(n3912), .B(n4395), .Y(n1896) );
NAND2X2TS U648 ( .A(n993), .B(n928), .Y(n1004) );
NAND2X2TS U649 ( .A(n423), .B(n873), .Y(n2461) );
CLKINVX2TS U650 ( .A(n435), .Y(n549) );
NOR2X4TS U651 ( .A(n1637), .B(n540), .Y(n539) );
NOR2X2TS U652 ( .A(n448), .B(n808), .Y(n3787) );
NOR3X6TS U653 ( .A(n535), .B(n3786), .C(n1117), .Y(n527) );
CMPR32X2TS U654 ( .A(mult_x_58_n37), .B(mult_x_58_n40), .C(n3417), .CO(n2520), .S(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N4) );
OR2X6TS U655 ( .A(n2693), .B(n2692), .Y(n3336) );
INVX2TS U656 ( .A(n1785), .Y(n2440) );
NOR3X1TS U657 ( .A(n4409), .B(FSM_selector_B_1_), .C(n3851), .Y(n2080) );
INVX2TS U658 ( .A(n2011), .Y(n1686) );
OAI2BB1X2TS U659 ( .A0N(n518), .A1N(n517), .B0(n2717), .Y(n516) );
NAND2X1TS U660 ( .A(n2515), .B(n1163), .Y(n1715) );
INVX12TS U661 ( .A(n1641), .Y(n3793) );
INVX4TS U662 ( .A(n2645), .Y(n448) );
OR2X4TS U663 ( .A(n1559), .B(n2302), .Y(n909) );
OAI22X2TS U664 ( .A0(n417), .A1(n2668), .B0(n2747), .B1(n511), .Y(n2700) );
NAND2X2TS U665 ( .A(n2240), .B(n2238), .Y(n2172) );
NAND2X6TS U666 ( .A(n1438), .B(n569), .Y(n1424) );
NAND2X2TS U667 ( .A(n1809), .B(n1808), .Y(n3039) );
INVX8TS U668 ( .A(n1195), .Y(n1193) );
INVX1TS U669 ( .A(n2400), .Y(n1348) );
INVX4TS U670 ( .A(n762), .Y(n444) );
BUFX3TS U671 ( .A(n2399), .Y(n1133) );
NAND2X2TS U672 ( .A(n991), .B(n990), .Y(n989) );
OAI22X2TS U673 ( .A0(n2790), .A1(n1042), .B0(n2765), .B1(n1543), .Y(n2784)
);
NAND2XLTS U674 ( .A(n2598), .B(n2426), .Y(n2427) );
NOR2X2TS U675 ( .A(n2095), .B(n2097), .Y(n2044) );
NAND2X6TS U676 ( .A(n1540), .B(n3580), .Y(n1536) );
INVX2TS U677 ( .A(n1001), .Y(n1343) );
CLKINVX3TS U678 ( .A(n3242), .Y(n3145) );
CLKINVX6TS U679 ( .A(n535), .Y(n1663) );
NOR2X4TS U680 ( .A(n3786), .B(n802), .Y(n2387) );
NAND2X6TS U681 ( .A(n1232), .B(n2531), .Y(n1231) );
OAI22X2TS U682 ( .A0(n2788), .A1(n1543), .B0(n2372), .B1(n1042), .Y(n2808)
);
OAI21X2TS U683 ( .A0(n2594), .A1(n2593), .B0(n2592), .Y(n2595) );
XNOR2X2TS U684 ( .A(n2137), .B(n2136), .Y(n2222) );
OAI22X2TS U685 ( .A0(n2723), .A1(n417), .B0(n2730), .B1(n2747), .Y(n2733) );
CLKXOR2X2TS U686 ( .A(n2194), .B(n2193), .Y(n2217) );
INVX6TS U687 ( .A(n435), .Y(n1117) );
BUFX4TS U688 ( .A(n447), .Y(n1215) );
OAI2BB1X2TS U689 ( .A0N(n3141), .A1N(n3142), .B0(n668), .Y(n3148) );
CLKINVX6TS U690 ( .A(n1376), .Y(n708) );
AND2X2TS U691 ( .A(n2518), .B(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[10]), .Y(n2402) );
NAND2X4TS U692 ( .A(n326), .B(n314), .Y(n3278) );
NAND2X1TS U693 ( .A(n1507), .B(n2185), .Y(n2186) );
NAND2X4TS U694 ( .A(n1290), .B(n2040), .Y(n2094) );
NAND2X2TS U695 ( .A(n2685), .B(n2686), .Y(n3263) );
NAND2X4TS U696 ( .A(n1559), .B(n2302), .Y(n2613) );
NOR2X1TS U697 ( .A(n2384), .B(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[9]), .Y(n990) );
OAI22X2TS U698 ( .A0(n2730), .A1(n417), .B0(n2747), .B1(n436), .Y(n2748) );
ADDHX1TS U699 ( .A(mult_x_57_n55), .B(n841), .CO(mult_x_57_n26), .S(
mult_x_57_n27) );
NOR2X2TS U700 ( .A(n1383), .B(n2960), .Y(n2970) );
AND2X4TS U701 ( .A(n2445), .B(n2450), .Y(n423) );
ADDFHX2TS U702 ( .A(n3151), .B(n3150), .CI(n3149), .CO(n3118), .S(n3152) );
CLKAND2X2TS U703 ( .A(n2510), .B(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[10]), .Y(n928) );
NOR2X6TS U704 ( .A(n326), .B(n314), .Y(n3276) );
INVX2TS U705 ( .A(n2389), .Y(n1351) );
INVX6TS U706 ( .A(n1612), .Y(n1634) );
NAND2BX2TS U707 ( .AN(n861), .B(n2945), .Y(n1403) );
ADDFHX2TS U708 ( .A(n2807), .B(n2806), .CI(n2805), .CO(n3017), .S(n2811) );
ADDFHX2TS U709 ( .A(n2703), .B(n2702), .CI(n2701), .CO(n2709), .S(n2698) );
NAND2BX1TS U710 ( .AN(net290453), .B(n1812), .Y(n1808) );
CLKINVX2TS U711 ( .A(n1812), .Y(n1810) );
NOR2X1TS U712 ( .A(n3185), .B(n3106), .Y(n3151) );
CLKINVX6TS U713 ( .A(n1501), .Y(n2048) );
NAND2X6TS U714 ( .A(n2549), .B(n2552), .Y(n1611) );
OR2X4TS U715 ( .A(n2686), .B(n2685), .Y(n1849) );
NOR2X1TS U716 ( .A(n3185), .B(n3158), .Y(n3167) );
INVX2TS U717 ( .A(FSM_add_overflow_flag), .Y(n3820) );
INVX3TS U718 ( .A(n1460), .Y(n2389) );
OAI22X2TS U719 ( .A0(n2707), .A1(n2716), .B0(n461), .B1(n2714), .Y(n2712) );
CLKAND2X2TS U720 ( .A(n1140), .B(n496), .Y(n2763) );
NOR2BX2TS U721 ( .AN(n3069), .B(n436), .Y(n2703) );
NAND2X4TS U722 ( .A(n1166), .B(n1254), .Y(n1253) );
BUFX3TS U723 ( .A(n2195), .Y(n1697) );
OAI22X2TS U724 ( .A0(n512), .A1(n884), .B0(n474), .B1(n2659), .Y(n2670) );
NOR2X4TS U725 ( .A(n2778), .B(n2777), .Y(n3054) );
NOR2X4TS U726 ( .A(n2998), .B(n809), .Y(n1427) );
MX2X1TS U727 ( .A(Op_MX[26]), .B(exp_oper_result[3]), .S0(FSM_selector_A),
.Y(n2047) );
MX2X1TS U728 ( .A(Op_MX[23]), .B(exp_oper_result[0]), .S0(FSM_selector_A),
.Y(n2039) );
NOR2X2TS U729 ( .A(n1564), .B(n3108), .Y(n3165) );
XNOR2X2TS U730 ( .A(n2719), .B(n2721), .Y(n2711) );
XNOR2X2TS U731 ( .A(n2704), .B(n2721), .Y(n2668) );
NAND2XLTS U732 ( .A(n2623), .B(n2622), .Y(n2624) );
XOR2X2TS U733 ( .A(n2731), .B(n436), .Y(n2723) );
INVX4TS U734 ( .A(n2449), .Y(n2450) );
NAND2X6TS U735 ( .A(n906), .B(n870), .Y(n1456) );
CLKXOR2X2TS U736 ( .A(n2425), .B(n4038), .Y(n2516) );
NOR2BX2TS U737 ( .AN(n2207), .B(n2184), .Y(n1613) );
OAI22X2TS U738 ( .A0(n1340), .A1(n2902), .B0(n1383), .B1(n2909), .Y(n2887)
);
NAND2X2TS U739 ( .A(n2626), .B(n2625), .Y(n2627) );
NAND2X2TS U740 ( .A(n1223), .B(n1222), .Y(n1227) );
NAND2BX2TS U741 ( .AN(n2945), .B(n861), .Y(n1402) );
NAND2X4TS U742 ( .A(n604), .B(n3561), .Y(n1583) );
INVX8TS U743 ( .A(n3779), .Y(n435) );
CLKINVX6TS U744 ( .A(n1816), .Y(n638) );
XOR2X2TS U745 ( .A(n2718), .B(n520), .Y(n519) );
NOR2X2TS U746 ( .A(n2560), .B(n754), .Y(n2561) );
AND3X4TS U747 ( .A(n1631), .B(n2619), .C(n1630), .Y(n921) );
OAI22X4TS U748 ( .A0(net291370), .A1(net288229), .B0(net292476), .B1(
net287910), .Y(n2829) );
NOR2X2TS U749 ( .A(n1564), .B(n3247), .Y(n3122) );
INVX6TS U750 ( .A(Sgf_operation_EVEN1_Q_left[12]), .Y(n2571) );
BUFX6TS U751 ( .A(n2549), .Y(n723) );
INVX6TS U752 ( .A(n1514), .Y(n1488) );
INVX2TS U753 ( .A(n2198), .Y(n1819) );
OR2X6TS U754 ( .A(n3078), .B(n3077), .Y(n3094) );
INVX4TS U755 ( .A(n1166), .Y(n2173) );
NAND2BX1TS U756 ( .AN(n2620), .B(n1357), .Y(n1630) );
NAND3X1TS U757 ( .A(n1626), .B(n2618), .C(n2567), .Y(n1631) );
NAND2X6TS U758 ( .A(n1486), .B(n1639), .Y(n1485) );
INVX8TS U759 ( .A(n1088), .Y(n1090) );
NAND2X6TS U760 ( .A(n443), .B(n595), .Y(n1574) );
INVX2TS U761 ( .A(n2271), .Y(n1554) );
BUFX8TS U762 ( .A(n2597), .Y(n1163) );
NAND2X2TS U763 ( .A(n2915), .B(n2914), .Y(n3561) );
NOR2X2TS U764 ( .A(n1564), .B(n3107), .Y(n3103) );
INVX4TS U765 ( .A(n2735), .Y(n2718) );
CLKINVX6TS U766 ( .A(n3091), .Y(n3092) );
BUFX16TS U767 ( .A(n3304), .Y(n1118) );
NAND2X6TS U768 ( .A(n666), .B(n664), .Y(n870) );
NAND2X4TS U769 ( .A(n1487), .B(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[7]), .Y(n2551) );
AND2X4TS U770 ( .A(n3736), .B(n1885), .Y(n873) );
NOR2X6TS U771 ( .A(n2681), .B(n2680), .Y(n3046) );
INVX4TS U772 ( .A(n2770), .Y(n1672) );
OAI21X1TS U773 ( .A0(FSM_selector_B_1_), .A1(n4389), .B0(n2066), .Y(n2046)
);
NAND3X4TS U774 ( .A(n1563), .B(n2332), .C(n1561), .Y(n1567) );
NAND2X2TS U775 ( .A(n2314), .B(n2315), .Y(n974) );
NAND2X2TS U776 ( .A(n1234), .B(n2176), .Y(n1233) );
NAND2X4TS U777 ( .A(n2681), .B(n2680), .Y(n3047) );
XNOR2X2TS U778 ( .A(n3071), .B(n442), .Y(n2359) );
BUFX6TS U779 ( .A(n1221), .Y(n1220) );
INVX2TS U780 ( .A(n2620), .Y(n2567) );
OR2X6TS U781 ( .A(n2915), .B(n2914), .Y(n1371) );
NOR2BX2TS U782 ( .AN(n3069), .B(n461), .Y(n2680) );
OR2X6TS U783 ( .A(n2454), .B(n3753), .Y(n662) );
INVX2TS U784 ( .A(n682), .Y(n681) );
OR2X2TS U785 ( .A(n2948), .B(n2947), .Y(n1049) );
OR2X6TS U786 ( .A(n2492), .B(n2491), .Y(n916) );
OR2X2TS U787 ( .A(n2899), .B(n1668), .Y(n1048) );
NAND2X4TS U788 ( .A(n2419), .B(n2418), .Y(n2579) );
INVX2TS U789 ( .A(Data_MY[0]), .Y(n1321) );
BUFX16TS U790 ( .A(n2334), .Y(n2757) );
INVX6TS U791 ( .A(n3070), .Y(n1042) );
INVX2TS U792 ( .A(n2344), .Y(n1561) );
INVX6TS U793 ( .A(n2557), .Y(n1799) );
CLKINVX6TS U794 ( .A(n1853), .Y(n3843) );
OAI22X2TS U795 ( .A0(net291370), .A1(net287496), .B0(net292476), .B1(
net288781), .Y(n2478) );
NAND2X6TS U796 ( .A(net291951), .B(net291950), .Y(net291953) );
INVX2TS U797 ( .A(n2017), .Y(n960) );
NAND2X2TS U798 ( .A(n2423), .B(n2422), .Y(n2598) );
NAND2X4TS U799 ( .A(n1887), .B(n806), .Y(n2460) );
BUFX12TS U800 ( .A(n1167), .Y(n1166) );
NAND2X6TS U801 ( .A(n1409), .B(n1407), .Y(n1408) );
INVX2TS U802 ( .A(Data_MY[12]), .Y(n1320) );
INVX12TS U803 ( .A(n1563), .Y(n1564) );
NAND2X6TS U804 ( .A(n2526), .B(n2417), .Y(n2590) );
NAND2X2TS U805 ( .A(n2421), .B(n2420), .Y(n2584) );
INVX12TS U806 ( .A(n2721), .Y(n436) );
INVX2TS U807 ( .A(Data_MY[2]), .Y(n1323) );
INVX2TS U808 ( .A(Data_MY[1]), .Y(n1327) );
INVX2TS U809 ( .A(Data_MY[14]), .Y(n1325) );
INVX2TS U810 ( .A(Data_MY[13]), .Y(n1326) );
NAND2X2TS U811 ( .A(n663), .B(n807), .Y(n2455) );
BUFX8TS U812 ( .A(n1520), .Y(n1383) );
CLKXOR2X4TS U813 ( .A(n2341), .B(n2342), .Y(n2343) );
NAND2X2TS U814 ( .A(n2016), .B(n1144), .Y(n963) );
OR2X4TS U815 ( .A(net288241), .B(net288747), .Y(net291950) );
CLKINVX6TS U816 ( .A(n1667), .Y(n1409) );
INVX8TS U817 ( .A(n1657), .Y(n2716) );
NAND2X4TS U818 ( .A(n1590), .B(n3068), .Y(n884) );
NAND2X4TS U819 ( .A(n4115), .B(n2651), .Y(n2721) );
NOR2X6TS U820 ( .A(n2580), .B(n2583), .Y(n2589) );
INVX4TS U821 ( .A(Sgf_operation_EVEN1_Q_left[9]), .Y(n2288) );
INVX6TS U822 ( .A(n2527), .Y(n2526) );
NAND2X2TS U823 ( .A(n1083), .B(n1629), .Y(n1828) );
NAND2X4TS U824 ( .A(net288775), .B(n2490), .Y(n3406) );
BUFX16TS U825 ( .A(net288241), .Y(net292476) );
NAND2X4TS U826 ( .A(n667), .B(n3699), .Y(n3726) );
NOR2X2TS U827 ( .A(n3177), .B(n3247), .Y(n3126) );
INVX4TS U828 ( .A(n2238), .Y(n1187) );
NOR2X2TS U829 ( .A(n3178), .B(n3246), .Y(n3125) );
NAND2X6TS U830 ( .A(n746), .B(n745), .Y(n728) );
CLKAND2X2TS U831 ( .A(n2657), .B(n4114), .Y(n892) );
OR2X4TS U832 ( .A(n2423), .B(n2422), .Y(n880) );
INVX12TS U833 ( .A(n588), .Y(n2747) );
BUFX4TS U834 ( .A(n3698), .Y(n1531) );
NAND2X2TS U835 ( .A(n2923), .B(n478), .Y(n713) );
CLKINVX2TS U836 ( .A(Sgf_operation_EVEN1_Q_left[8]), .Y(n2235) );
NAND2X4TS U837 ( .A(n726), .B(n748), .Y(n725) );
NAND2X2TS U838 ( .A(n2332), .B(n2345), .Y(n1483) );
INVX4TS U839 ( .A(n2793), .Y(n1452) );
OR2X4TS U840 ( .A(net291956), .B(net288242), .Y(net291951) );
NAND2X2TS U841 ( .A(n2213), .B(n2212), .Y(n2214) );
NAND2X2TS U842 ( .A(n1657), .B(n2706), .Y(n1219) );
XNOR2X2TS U843 ( .A(n3069), .B(n2706), .Y(n2682) );
BUFX8TS U844 ( .A(net291396), .Y(net292372) );
INVX8TS U845 ( .A(n2678), .Y(n441) );
INVX2TS U846 ( .A(n1944), .Y(n2213) );
OR2X6TS U847 ( .A(n1932), .B(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[2]), .Y(n2626) );
NOR2X1TS U848 ( .A(n3102), .B(n3107), .Y(n3086) );
INVX6TS U849 ( .A(Sgf_operation_EVEN1_result_B_adder[5]), .Y(n3185) );
INVX12TS U850 ( .A(n1690), .Y(n2793) );
INVX2TS U851 ( .A(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[6]), .Y(
n2396) );
INVX6TS U852 ( .A(n3070), .Y(n1041) );
OR2X2TS U853 ( .A(DP_OP_158J21_127_356_n1053), .B(DP_OP_158J21_127_356_n312),
.Y(n2328) );
INVX4TS U854 ( .A(n1648), .Y(n1647) );
NOR2X4TS U855 ( .A(n1883), .B(n786), .Y(n3729) );
NOR2X6TS U856 ( .A(n2418), .B(n2419), .Y(n2580) );
INVX3TS U857 ( .A(n747), .Y(n745) );
NOR2X2TS U858 ( .A(n3108), .B(n3106), .Y(n3083) );
NOR2X6TS U859 ( .A(FS_Module_state_reg[2]), .B(FS_Module_state_reg[3]), .Y(
n1330) );
INVX6TS U860 ( .A(net288858), .Y(net288230) );
INVX4TS U861 ( .A(n1587), .Y(n3068) );
OR2X2TS U862 ( .A(n2413), .B(n2412), .Y(n2423) );
INVX2TS U863 ( .A(n2535), .Y(n1440) );
NAND2X2TS U864 ( .A(n1882), .B(n813), .Y(n3699) );
INVX6TS U865 ( .A(n835), .Y(net287910) );
OR2X2TS U866 ( .A(n1449), .B(n2344), .Y(n922) );
NAND2X6TS U867 ( .A(n1144), .B(n1998), .Y(n2527) );
NOR2X6TS U868 ( .A(n754), .B(n427), .Y(n753) );
OAI22X2TS U869 ( .A0(n1307), .A1(n2902), .B0(n2948), .B1(n2909), .Y(n2916)
);
NAND2BX2TS U870 ( .AN(n2344), .B(n2346), .Y(n1263) );
NOR2X6TS U871 ( .A(n744), .B(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[13]), .Y(n746) );
INVX6TS U872 ( .A(n3366), .Y(n442) );
NOR2X2TS U873 ( .A(n2715), .B(n3069), .Y(n1659) );
AND2X4TS U874 ( .A(n877), .B(n2622), .Y(n865) );
NAND2X4TS U875 ( .A(n715), .B(n712), .Y(n711) );
INVX16TS U876 ( .A(n1449), .Y(n2332) );
INVX4TS U877 ( .A(n1268), .Y(n749) );
OR2X6TS U878 ( .A(n1141), .B(Op_MX[17]), .Y(n1083) );
INVX2TS U879 ( .A(n1691), .Y(n2803) );
BUFX3TS U880 ( .A(n4325), .Y(n1835) );
AND2X6TS U881 ( .A(n1836), .B(n2870), .Y(n1363) );
NOR2X6TS U882 ( .A(n2024), .B(n2023), .Y(n2530) );
INVX2TS U883 ( .A(n2923), .Y(n712) );
NAND2X2TS U884 ( .A(n1992), .B(n1991), .Y(n2622) );
OR2X6TS U885 ( .A(n1119), .B(n1852), .Y(n1629) );
NAND2X4TS U886 ( .A(n1017), .B(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[3]), .Y(n2198) );
NOR2X4TS U887 ( .A(n424), .B(n500), .Y(n2658) );
NAND2X1TS U888 ( .A(n1878), .B(n797), .Y(n1879) );
INVX4TS U889 ( .A(n1158), .Y(n2003) );
NAND2X4TS U890 ( .A(n1721), .B(n1720), .Y(n1998) );
NOR2X6TS U891 ( .A(n2252), .B(n2253), .Y(n2251) );
NAND2X6TS U892 ( .A(n1801), .B(n1800), .Y(n2260) );
XOR2X2TS U893 ( .A(net288788), .B(n632), .Y(n631) );
NAND2X2TS U894 ( .A(n2157), .B(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[6]), .Y(n2175) );
NOR2X4TS U895 ( .A(n2620), .B(n2621), .Y(n1627) );
NOR2X6TS U896 ( .A(n737), .B(n1268), .Y(n744) );
NAND2X2TS U897 ( .A(n1754), .B(n612), .Y(n593) );
NAND2BX2TS U898 ( .AN(n2248), .B(n2247), .Y(n2249) );
NAND2X2TS U899 ( .A(n2232), .B(n2231), .Y(n2234) );
NAND2X2TS U900 ( .A(n2284), .B(n2283), .Y(n2285) );
OAI22X2TS U901 ( .A0(n481), .A1(n3567), .B0(n2908), .B1(n1307), .Y(n2912) );
NAND2X2TS U902 ( .A(n2398), .B(n2397), .Y(n2395) );
NAND3X6TS U903 ( .A(n743), .B(n742), .C(n2397), .Y(n747) );
CLKAND2X2TS U904 ( .A(n1872), .B(n800), .Y(n1032) );
NAND2X1TS U905 ( .A(n2134), .B(n2133), .Y(n2144) );
NAND2X4TS U906 ( .A(n558), .B(n2398), .Y(n1268) );
INVX2TS U907 ( .A(n1871), .Y(n1872) );
NAND2X4TS U908 ( .A(n1986), .B(n1985), .Y(n2303) );
INVX2TS U909 ( .A(DP_OP_158J21_127_356_n1047), .Y(n2651) );
NAND2X4TS U910 ( .A(n1990), .B(n1989), .Y(n2619) );
INVX2TS U911 ( .A(n1996), .Y(n1721) );
BUFX3TS U912 ( .A(n2292), .Y(n1525) );
NOR2X6TS U913 ( .A(n1989), .B(n1990), .Y(n2620) );
INVX6TS U914 ( .A(n4490), .Y(n1288) );
CLKINVX2TS U915 ( .A(n1995), .Y(n1720) );
NOR2X6TS U916 ( .A(n2001), .B(n2000), .Y(n2018) );
NOR2X2TS U917 ( .A(n2128), .B(n2127), .Y(n2143) );
NAND2X1TS U918 ( .A(n4334), .B(n792), .Y(n1864) );
NAND2X2TS U919 ( .A(n1019), .B(n2245), .Y(n2246) );
INVX6TS U920 ( .A(n2868), .Y(n2967) );
NAND2X6TS U921 ( .A(n863), .B(n4118), .Y(n1786) );
INVX4TS U922 ( .A(n1654), .Y(n2706) );
NAND2X4TS U923 ( .A(n763), .B(n542), .Y(n534) );
INVX2TS U924 ( .A(Sgf_operation_EVEN1_Q_left[7]), .Y(n999) );
INVX8TS U925 ( .A(n2948), .Y(n483) );
INVX8TS U926 ( .A(n1925), .Y(n2560) );
AND2X4TS U927 ( .A(n1515), .B(n1907), .Y(n2256) );
INVX3TS U928 ( .A(n558), .Y(n615) );
NAND3X4TS U929 ( .A(DP_OP_158J21_127_356_n1056), .B(
DP_OP_158J21_127_356_n656), .C(n4122), .Y(n1211) );
OAI22X2TS U930 ( .A0(net292376), .A1(net287496), .B0(net291396), .B1(
net288781), .Y(net288775) );
NAND2X6TS U931 ( .A(n2208), .B(n1507), .Y(n1698) );
NAND2X6TS U932 ( .A(n407), .B(n1465), .Y(n1034) );
INVX4TS U933 ( .A(n1754), .Y(n610) );
NAND2X2TS U934 ( .A(n4342), .B(n781), .Y(n1867) );
INVX4TS U935 ( .A(n2176), .Y(n1770) );
NAND2X1TS U936 ( .A(n2355), .B(DP_OP_158J21_127_356_n400), .Y(n2356) );
INVX2TS U937 ( .A(n612), .Y(n609) );
NOR2X6TS U938 ( .A(n801), .B(n816), .Y(n3679) );
CLKINVX2TS U939 ( .A(n2346), .Y(n1566) );
INVX2TS U940 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[11]), .Y(
n2408) );
BUFX16TS U941 ( .A(net292233), .Y(net293204) );
CLKINVX6TS U942 ( .A(net288852), .Y(net288242) );
NAND2X4TS U943 ( .A(DP_OP_158J21_127_356_n654), .B(DP_OP_158J21_127_356_n655), .Y(n2329) );
INVX8TS U944 ( .A(net288862), .Y(net288243) );
NAND2X6TS U945 ( .A(n1497), .B(n1495), .Y(n1345) );
INVX6TS U946 ( .A(n2867), .Y(n2961) );
OR2X4TS U947 ( .A(n2392), .B(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[12]), .Y(n2398) );
INVX6TS U948 ( .A(n1496), .Y(n1346) );
INVX4TS U949 ( .A(net288832), .Y(net288745) );
NOR2X6TS U950 ( .A(DP_OP_158J21_127_356_n388), .B(DP_OP_158J21_127_356_n381),
.Y(n1210) );
NOR2X4TS U951 ( .A(n1453), .B(n1865), .Y(n1429) );
NAND2X4TS U952 ( .A(DP_OP_153J21_122_3500_n166), .B(n1984), .Y(n2275) );
BUFX12TS U953 ( .A(n764), .Y(n680) );
NAND3X4TS U954 ( .A(n1016), .B(n1015), .C(n910), .Y(n1013) );
NOR2X6TS U955 ( .A(n2115), .B(n1280), .Y(n2181) );
NAND2X2TS U956 ( .A(n717), .B(n2008), .Y(n1618) );
NAND2X4TS U957 ( .A(n1575), .B(n2391), .Y(n750) );
CLKINVX6TS U958 ( .A(n2875), .Y(n2908) );
NAND2X6TS U959 ( .A(n429), .B(n867), .Y(n1580) );
INVX8TS U960 ( .A(n2872), .Y(n2946) );
CLKINVX6TS U961 ( .A(Sgf_operation_Result[4]), .Y(n3872) );
INVX4TS U962 ( .A(Sgf_operation_Result[5]), .Y(n2139) );
INVX2TS U963 ( .A(n4116), .Y(n2654) );
OAI2BB1X2TS U964 ( .A0N(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[8]),
.A1N(n1709), .B0(n1999), .Y(n1708) );
INVX2TS U965 ( .A(n4112), .Y(n1160) );
NAND2X2TS U966 ( .A(n2121), .B(n2122), .Y(n2191) );
INVX4TS U967 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[9]), .Y(
n2021) );
BUFX16TS U968 ( .A(net291929), .Y(net291956) );
NAND2X4TS U969 ( .A(n1954), .B(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[11]), .Y(n2296) );
CLKINVX2TS U970 ( .A(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[11]),
.Y(n1907) );
INVX6TS U971 ( .A(n2877), .Y(n2947) );
NAND2X6TS U972 ( .A(n429), .B(n1576), .Y(n1575) );
CLKINVX2TS U973 ( .A(net287496), .Y(n648) );
BUFX2TS U974 ( .A(n2163), .Y(n1499) );
NAND2X1TS U975 ( .A(n896), .B(n2178), .Y(n2155) );
AND2X4TS U976 ( .A(n900), .B(n457), .Y(n1260) );
CLKINVX2TS U977 ( .A(n2203), .Y(n2115) );
NOR2X6TS U978 ( .A(n2469), .B(net288845), .Y(n1769) );
XOR2X2TS U979 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[8]),
.B(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[8]), .Y(n1710) );
NAND2X6TS U980 ( .A(n1465), .B(n407), .Y(n1464) );
CLKINVX2TS U981 ( .A(n2468), .Y(n1815) );
NAND2X2TS U982 ( .A(n2467), .B(n2468), .Y(n1304) );
INVX16TS U983 ( .A(n482), .Y(n2948) );
INVX2TS U984 ( .A(n2469), .Y(n2467) );
INVX6TS U985 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[4]), .Y(
n1976) );
INVX6TS U986 ( .A(n2470), .Y(n2477) );
INVX8TS U987 ( .A(n838), .Y(net291396) );
INVX2TS U988 ( .A(n2165), .Y(n1185) );
NOR2X4TS U989 ( .A(n764), .B(n1877), .Y(n1431) );
INVX8TS U990 ( .A(n491), .Y(n1688) );
INVX2TS U991 ( .A(n2121), .Y(n1278) );
AND2X6TS U992 ( .A(n1921), .B(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[8]), .Y(n1922) );
CLKINVX2TS U993 ( .A(DP_OP_158J21_127_356_n1044), .Y(n457) );
NAND2X6TS U994 ( .A(n603), .B(n1489), .Y(n602) );
NAND2X2TS U995 ( .A(n1050), .B(n1065), .Y(n2468) );
INVX2TS U996 ( .A(n1018), .Y(n564) );
INVX6TS U997 ( .A(n2471), .Y(n2488) );
NAND2X4TS U998 ( .A(n1700), .B(n1699), .Y(n1507) );
INVX2TS U999 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[8]), .Y(
n1999) );
NOR2X6TS U1000 ( .A(n1954), .B(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[11]), .Y(n2295) );
OR2X2TS U1001 ( .A(n918), .B(n2153), .Y(n987) );
INVX4TS U1002 ( .A(n1679), .Y(n490) );
INVX2TS U1003 ( .A(n2178), .Y(n1008) );
NOR2X6TS U1004 ( .A(n1607), .B(n601), .Y(n600) );
CLKBUFX2TS U1005 ( .A(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[10]),
.Y(n405) );
CLKINVX2TS U1006 ( .A(n2119), .Y(n1276) );
INVX4TS U1007 ( .A(n1625), .Y(n972) );
INVX8TS U1008 ( .A(net288833), .Y(net288798) );
NAND2X4TS U1009 ( .A(n1913), .B(n1927), .Y(n1679) );
OR2X4TS U1010 ( .A(n2154), .B(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[12]), .Y(n896) );
NAND2X6TS U1011 ( .A(n1287), .B(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[1]), .Y(n2226) );
NAND2X2TS U1012 ( .A(n2154), .B(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[12]), .Y(n2178) );
INVX2TS U1013 ( .A(n1489), .Y(n601) );
NOR2X4TS U1014 ( .A(n1050), .B(n1065), .Y(n2469) );
NAND2X2TS U1015 ( .A(n4324), .B(DP_OP_159J21_128_5719_n249), .Y(n619) );
INVX8TS U1016 ( .A(n1624), .Y(n971) );
NOR2X4TS U1017 ( .A(n4339), .B(n4338), .Y(n1877) );
INVX2TS U1018 ( .A(n1929), .Y(n1913) );
CLKINVX6TS U1019 ( .A(Sgf_operation_Result[3]), .Y(n2126) );
CLKINVX6TS U1020 ( .A(Sgf_operation_Result[1]), .Y(n2116) );
INVX8TS U1021 ( .A(n2159), .Y(n1624) );
INVX2TS U1022 ( .A(DP_OP_156J21_125_3370_n164), .Y(n1283) );
CLKINVX6TS U1023 ( .A(DP_OP_157J21_126_5719_n258), .Y(n729) );
NOR2BX2TS U1024 ( .AN(n875), .B(n929), .Y(n1599) );
INVX4TS U1025 ( .A(n981), .Y(n565) );
NAND2X2TS U1026 ( .A(n955), .B(DP_OP_157J21_126_5719_n248), .Y(n1302) );
NAND2BX2TS U1027 ( .AN(n1958), .B(n1961), .Y(n1807) );
NOR2X6TS U1028 ( .A(n1181), .B(n918), .Y(n1176) );
NOR2X4TS U1029 ( .A(n2153), .B(n2152), .Y(n1181) );
INVX4TS U1030 ( .A(n1926), .Y(n1680) );
NOR2X6TS U1031 ( .A(n2153), .B(n2150), .Y(n1182) );
NAND2X6TS U1032 ( .A(n1920), .B(n1200), .Y(n760) );
NAND2X4TS U1033 ( .A(n1066), .B(n1959), .Y(n1504) );
INVX6TS U1034 ( .A(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[11]), .Y(
n2393) );
INVX6TS U1035 ( .A(DP_OP_154J21_123_2814_n90), .Y(n1919) );
INVX3TS U1036 ( .A(n1962), .Y(n1956) );
AOI21X2TS U1037 ( .A0(n1703), .A1(DP_OP_155J21_124_2814_n90), .B0(n1702),
.Y(n1701) );
NAND2X2TS U1038 ( .A(n1951), .B(n966), .Y(n947) );
NAND2X6TS U1039 ( .A(Op_MY[10]), .B(Op_MY[4]), .Y(net288845) );
OR2X4TS U1040 ( .A(DP_OP_155J21_124_2814_n118), .B(
DP_OP_155J21_124_2814_n119), .Y(n875) );
INVX12TS U1041 ( .A(n504), .Y(n717) );
NAND2X4TS U1042 ( .A(n1964), .B(DP_OP_155J21_124_2814_n117), .Y(n1970) );
INVX2TS U1043 ( .A(n1960), .Y(n1172) );
NAND2X4TS U1044 ( .A(DP_OP_155J21_124_2814_n120), .B(
DP_OP_155J21_124_2814_n121), .Y(n1960) );
NAND2X6TS U1045 ( .A(DP_OP_155J21_124_2814_n128), .B(
DP_OP_155J21_124_2814_n129), .Y(n1951) );
NAND2X6TS U1046 ( .A(n1162), .B(n4123), .Y(n1942) );
NAND2X6TS U1047 ( .A(DP_OP_155J21_124_2814_n126), .B(
DP_OP_155J21_124_2814_n127), .Y(n1948) );
NOR2X4TS U1048 ( .A(n1929), .B(n1928), .Y(n1467) );
INVX6TS U1049 ( .A(DP_OP_154J21_123_2814_n126), .Y(n702) );
NAND2X6TS U1050 ( .A(DP_OP_154J21_123_2814_n128), .B(
DP_OP_154J21_123_2814_n129), .Y(n1920) );
INVX8TS U1051 ( .A(DP_OP_154J21_123_2814_n127), .Y(n701) );
INVX8TS U1052 ( .A(DP_OP_154J21_123_2814_n87), .Y(n1603) );
INVX4TS U1053 ( .A(DP_OP_155J21_124_2814_n92), .Y(n1397) );
NAND2X4TS U1054 ( .A(n1024), .B(n3357), .Y(n4109) );
BUFX20TS U1055 ( .A(n1141), .Y(n1054) );
NAND2X4TS U1056 ( .A(n3723), .B(n3722), .Y(n3724) );
OAI21X2TS U1057 ( .A0(FSM_selector_B_1_), .A1(n4387), .B0(n2066), .Y(n2067)
);
OAI21X2TS U1058 ( .A0(FSM_selector_B_1_), .A1(n4388), .B0(n2066), .Y(n2051)
);
OAI21X2TS U1059 ( .A0(FSM_selector_B_1_), .A1(n4391), .B0(n2066), .Y(n2036)
);
ADDFHX4TS U1060 ( .A(n3502), .B(n3501), .CI(n3500), .CO(n4242), .S(n4243) );
ADDHX4TS U1061 ( .A(n3514), .B(n3513), .CO(n3502), .S(n4232) );
XNOR2X4TS U1062 ( .A(n3683), .B(n3682), .Y(n3684) );
OAI21X2TS U1063 ( .A0(n826), .A1(n3678), .B0(n3677), .Y(n3683) );
NOR2X4TS U1064 ( .A(n4131), .B(n4126), .Y(n4149) );
INVX4TS U1065 ( .A(n3623), .Y(n3625) );
XNOR2X4TS U1066 ( .A(n3756), .B(n3755), .Y(n3757) );
NAND2X2TS U1067 ( .A(n3852), .B(n3851), .Y(n4583) );
XNOR2X4TS U1068 ( .A(n3588), .B(n3587), .Y(n3590) );
BUFX20TS U1069 ( .A(n2444), .Y(n3779) );
INVX4TS U1070 ( .A(n3054), .Y(n3056) );
INVX4TS U1071 ( .A(n3624), .Y(add_x_19_n47) );
OR2X8TS U1072 ( .A(n3354), .B(n3353), .Y(n3358) );
OAI21X4TS U1073 ( .A0(n3236), .A1(n3233), .B0(n3234), .Y(n3232) );
INVX6TS U1074 ( .A(n3229), .Y(n3236) );
AOI21X4TS U1075 ( .A0(n822), .A1(n4340), .B0(n4341), .Y(n1866) );
INVX8TS U1076 ( .A(n3729), .Y(n3739) );
INVX6TS U1077 ( .A(n2490), .Y(n1300) );
ADDFHX4TS U1078 ( .A(n1099), .B(n1097), .CI(n3249), .CO(n4034), .S(n4035) );
OAI21X4TS U1079 ( .A0(n3081), .A1(n3080), .B0(n3079), .Y(n3093) );
NOR2X4TS U1080 ( .A(n3051), .B(n3050), .Y(n3081) );
NOR2BX4TS U1081 ( .AN(n496), .B(n1089), .Y(n2777) );
BUFX20TS U1082 ( .A(n3071), .Y(n496) );
NAND2X4TS U1083 ( .A(n794), .B(n815), .Y(n3690) );
XOR2X4TS U1084 ( .A(n3386), .B(n3385), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N5)
);
CLKINVX6TS U1085 ( .A(n1356), .Y(DP_OP_156J21_125_3370_n92) );
NAND2X4TS U1086 ( .A(n3358), .B(n3357), .Y(DP_OP_158J21_127_356_n2) );
NAND4X6TS U1087 ( .A(n1211), .B(n1209), .C(n1208), .D(n2329), .Y(n1212) );
NOR2X8TS U1088 ( .A(n2087), .B(n2057), .Y(n2072) );
NAND2X4TS U1089 ( .A(DP_OP_156J21_125_3370_n91), .B(n1356), .Y(
DP_OP_156J21_125_3370_n11) );
NAND2X4TS U1090 ( .A(n3771), .B(n3770), .Y(n3772) );
OR2X8TS U1091 ( .A(n3008), .B(n886), .Y(n3770) );
ADDHX4TS U1092 ( .A(n3518), .B(n3517), .CO(n4225), .S(n4226) );
AND2X4TS U1093 ( .A(n316), .B(n344), .Y(n4196) );
NAND3X6TS U1094 ( .A(n4479), .B(n4478), .C(n4477), .Y(n3968) );
NAND2X4TS U1095 ( .A(n1738), .B(n3312), .Y(n1332) );
OR2X8TS U1096 ( .A(n1329), .B(n1328), .Y(n4585) );
XNOR2X4TS U1097 ( .A(n973), .B(n2576), .Y(Sgf_operation_EVEN1_S_B[13]) );
NAND2BX4TS U1098 ( .AN(n3445), .B(n625), .Y(n3446) );
NAND2X8TS U1099 ( .A(n625), .B(n3445), .Y(n1370) );
NAND2X4TS U1100 ( .A(n4119), .B(n3342), .Y(DP_OP_158J21_127_356_n3) );
NOR2X6TS U1101 ( .A(n1863), .B(n1429), .Y(n1428) );
NAND2X8TS U1102 ( .A(n1430), .B(n905), .Y(n1863) );
NAND2X4TS U1103 ( .A(add_x_19_n95), .B(n2015), .Y(n3604) );
ADDHX4TS U1104 ( .A(n3540), .B(n3539), .CO(n4262), .S(n4263) );
NAND2X8TS U1105 ( .A(n2077), .B(n897), .Y(n3829) );
NOR2X8TS U1106 ( .A(n503), .B(n3623), .Y(n3624) );
NAND2X6TS U1107 ( .A(n3621), .B(n866), .Y(n503) );
NAND2X2TS U1108 ( .A(n768), .B(n3929), .Y(n1831) );
NAND2X8TS U1109 ( .A(n1457), .B(n4525), .Y(n3924) );
NAND2X4TS U1110 ( .A(n3078), .B(n3077), .Y(n3091) );
AND2X8TS U1111 ( .A(n903), .B(n1803), .Y(n532) );
NAND3X4TS U1112 ( .A(n3793), .B(n3792), .C(n435), .Y(n1803) );
NAND2X8TS U1113 ( .A(n3791), .B(n1757), .Y(n3852) );
CLKINVX6TS U1114 ( .A(n3778), .Y(n476) );
NAND2X8TS U1115 ( .A(n1550), .B(n1548), .Y(n250) );
NAND2X6TS U1116 ( .A(n2466), .B(n829), .Y(n1550) );
XNOR2X4TS U1117 ( .A(n669), .B(n3142), .Y(n3143) );
CMPR22X2TS U1118 ( .A(n3121), .B(n3120), .CO(n3111), .S(n3142) );
XNOR2X4TS U1119 ( .A(n3373), .B(n3372), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N5)
);
XNOR2X4TS U1120 ( .A(n3746), .B(n3745), .Y(n3747) );
OAI21X4TS U1121 ( .A0(n3779), .A1(n3741), .B0(n3740), .Y(n3746) );
BUFX20TS U1122 ( .A(n319), .Y(n1098) );
INVX12TS U1123 ( .A(Sgf_operation_EVEN1_result_A_adder[0]), .Y(n3246) );
OR2X4TS U1124 ( .A(n4495), .B(n355), .Y(n4091) );
NAND2X8TS U1125 ( .A(n1353), .B(n4528), .Y(n3926) );
NAND2X8TS U1126 ( .A(n1741), .B(n1739), .Y(n1738) );
NAND3X8TS U1127 ( .A(n3253), .B(n1322), .C(n1319), .Y(n1741) );
OAI21X2TS U1128 ( .A0(FSM_selector_B_1_), .A1(n4392), .B0(n2066), .Y(n2035)
);
NAND3X4TS U1129 ( .A(n3768), .B(n3767), .C(n3766), .Y(n202) );
NAND2X8TS U1130 ( .A(n530), .B(n529), .Y(n528) );
OR2X8TS U1131 ( .A(n362), .B(n350), .Y(n4107) );
AND2X4TS U1132 ( .A(n322), .B(n350), .Y(n4222) );
NAND3X8TS U1133 ( .A(n770), .B(n769), .C(n948), .Y(n768) );
NAND3X4TS U1134 ( .A(n767), .B(n1895), .C(n952), .Y(n769) );
NAND2X8TS U1135 ( .A(n528), .B(n4532), .Y(n3928) );
BUFX12TS U1136 ( .A(n2509), .Y(n1291) );
INVX8TS U1137 ( .A(n3607), .Y(n2244) );
ADDFHX4TS U1138 ( .A(n3124), .B(n3123), .CI(n3122), .CO(n3114), .S(n3147) );
NOR2X2TS U1139 ( .A(n876), .B(n3107), .Y(n3123) );
NOR2X2TS U1140 ( .A(n881), .B(n3246), .Y(n3124) );
NAND2X8TS U1141 ( .A(n499), .B(n3335), .Y(n3374) );
INVX6TS U1142 ( .A(n3293), .Y(n3332) );
OAI21X2TS U1143 ( .A0(n3293), .A1(n3292), .B0(n3291), .Y(n3298) );
NAND2X8TS U1144 ( .A(n1804), .B(n532), .Y(n531) );
INVX6TS U1145 ( .A(n2832), .Y(n2220) );
ADDFHX2TS U1146 ( .A(n3167), .B(n3166), .CI(n3165), .CO(n3179), .S(n3170) );
NOR2X2TS U1147 ( .A(n876), .B(n3185), .Y(n3187) );
AND2X4TS U1148 ( .A(n334), .B(n362), .Y(n4163) );
NAND2X8TS U1149 ( .A(n1116), .B(n325), .Y(n3315) );
INVX8TS U1150 ( .A(n1318), .Y(n325) );
INVX16TS U1151 ( .A(n1317), .Y(n1116) );
NAND2X4TS U1152 ( .A(n1638), .B(n3776), .Y(n2999) );
INVX12TS U1153 ( .A(n3776), .Y(n1486) );
NAND3X6TS U1154 ( .A(n1195), .B(n1194), .C(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[9]), .Y(n1191) );
ADDHX4TS U1155 ( .A(n2671), .B(n2670), .CO(n2699), .S(n2672) );
NAND2X8TS U1156 ( .A(n1036), .B(n1037), .Y(n2671) );
NAND2X8TS U1157 ( .A(n763), .B(n1431), .Y(n1865) );
NOR2X8TS U1158 ( .A(n794), .B(n815), .Y(n3673) );
NAND2X8TS U1159 ( .A(n662), .B(n2455), .Y(n2446) );
AND2X4TS U1160 ( .A(n1115), .B(n353), .Y(n3517) );
CLKINVX6TS U1161 ( .A(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N11),
.Y(n4150) );
NAND2X4TS U1162 ( .A(n3793), .B(n1638), .Y(n3778) );
CLKINVX12TS U1163 ( .A(n1159), .Y(n406) );
ADDFHX4TS U1164 ( .A(mult_x_59_n15), .B(mult_x_59_n17), .CI(n3548), .CO(
n3551), .S(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N8)
);
ADDFHX4TS U1165 ( .A(mult_x_59_n18), .B(mult_x_59_n22), .CI(n3547), .CO(
n3548), .S(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N7)
);
ADDFHX2TS U1166 ( .A(n3130), .B(n3129), .CI(n3128), .CO(n3150), .S(n3138) );
AND2X4TS U1167 ( .A(n1085), .B(n348), .Y(n3487) );
AND2X4TS U1168 ( .A(n4119), .B(n3358), .Y(n4108) );
OAI21X2TS U1169 ( .A0(n3228), .A1(n3203), .B0(n3202), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N13)
);
CLKINVX6TS U1170 ( .A(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N11),
.Y(n4148) );
ADDFHX4TS U1171 ( .A(n3139), .B(n3138), .CI(n3137), .CO(n3146), .S(n3144) );
NAND3X4TS U1172 ( .A(n1419), .B(n1417), .C(n1415), .Y(n209) );
ADDFHX4TS U1173 ( .A(n2700), .B(n2699), .CI(n2698), .CO(n2736), .S(n2697) );
ADDFHX4TS U1174 ( .A(n3454), .B(n3453), .CI(n3452), .CO(n4181), .S(n4182) );
ADDHX4TS U1175 ( .A(n3470), .B(n3469), .CO(n4171), .S(n4172) );
AND2X8TS U1176 ( .A(n1115), .B(n354), .Y(n3515) );
XNOR2X4TS U1177 ( .A(n3298), .B(n3297), .Y(n4066) );
NAND2X8TS U1178 ( .A(n477), .B(n4531), .Y(n3921) );
NAND2X4TS U1179 ( .A(n3783), .B(n828), .Y(n477) );
NAND2X8TS U1180 ( .A(n765), .B(n792), .Y(n1645) );
XOR2X4TS U1181 ( .A(n1635), .B(n1154), .Y(n1069) );
INVX6TS U1182 ( .A(Sgf_operation_EVEN1_Q_left[10]), .Y(n2300) );
NAND2X6TS U1183 ( .A(n526), .B(n525), .Y(n524) );
NAND2BX2TS U1184 ( .AN(n2837), .B(n2838), .Y(n1856) );
CLKINVX6TS U1185 ( .A(n2549), .Y(n1582) );
NAND2X4TS U1186 ( .A(n3341), .B(n431), .Y(DP_OP_158J21_127_356_n4) );
NAND2X6TS U1187 ( .A(n1378), .B(n1377), .Y(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N11)
);
ADDFHX4TS U1188 ( .A(n3532), .B(n3531), .CI(n3530), .CO(n4264), .S(n3538) );
AND2X4TS U1189 ( .A(n334), .B(n363), .Y(n3453) );
AND2X4TS U1190 ( .A(n1096), .B(n363), .Y(n4165) );
AND2X4TS U1191 ( .A(mult_x_59_b_5_), .B(mult_x_59_a_3_), .Y(mult_x_59_n58)
);
AND2X4TS U1192 ( .A(mult_x_59_b_4_), .B(mult_x_59_a_3_), .Y(mult_x_59_n59)
);
NAND2X8TS U1193 ( .A(n1420), .B(n4526), .Y(n3775) );
NAND3X6TS U1194 ( .A(n902), .B(n1477), .C(n1476), .Y(n1475) );
NAND2X8TS U1195 ( .A(n2646), .B(n547), .Y(n1476) );
ADDHX4TS U1196 ( .A(n3475), .B(n3474), .CO(n4169), .S(n4170) );
AND2X8TS U1197 ( .A(n1122), .B(n364), .Y(n3475) );
NAND2X4TS U1198 ( .A(n3581), .B(n3580), .Y(n3582) );
NAND2X6TS U1199 ( .A(n3581), .B(n1583), .Y(n1540) );
NOR2X6TS U1200 ( .A(n3153), .B(n3152), .Y(n3237) );
MX2X6TS U1201 ( .A(Data_MY[8]), .B(Op_MY[8]), .S0(net287583), .Y(n320) );
INVX6TS U1202 ( .A(n2252), .Y(n2254) );
ADDFHX2TS U1203 ( .A(n352), .B(n364), .CI(n3270), .CO(n3265), .S(n3273) );
AND2X4TS U1204 ( .A(n1039), .B(n364), .Y(n4164) );
NAND3X6TS U1205 ( .A(n780), .B(n595), .C(n443), .Y(n1154) );
NAND2X2TS U1206 ( .A(n873), .B(n2445), .Y(n2448) );
NAND2X4TS U1207 ( .A(n1874), .B(n534), .Y(n1662) );
NAND2X4TS U1208 ( .A(n2050), .B(n2049), .Y(n2058) );
NAND2X6TS U1209 ( .A(n547), .B(n2387), .Y(n685) );
ADDFHX4TS U1210 ( .A(mult_x_56_n18), .B(mult_x_56_n22), .CI(n3463), .CO(
n3471), .S(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N7) );
CLKINVX6TS U1211 ( .A(n3795), .Y(n466) );
NAND2X4TS U1212 ( .A(n3793), .B(n2644), .Y(n3795) );
ADDFX2TS U1213 ( .A(mult_x_56_n23), .B(mult_x_56_n29), .CI(n3466), .CO(n3463), .S(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N6) );
ADDFX2TS U1214 ( .A(mult_x_56_n30), .B(mult_x_56_n36), .CI(n3464), .CO(n3466), .S(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N5) );
BUFX12TS U1215 ( .A(n1454), .Y(n546) );
NAND3X6TS U1216 ( .A(n1058), .B(n1057), .C(n1059), .Y(n4297) );
CMPR22X2TS U1217 ( .A(n3560), .B(n3559), .CO(n4270), .S(n4271) );
AND2X4TS U1218 ( .A(n316), .B(n345), .Y(n4199) );
INVX6TS U1219 ( .A(n1744), .Y(n1443) );
CLKINVX6TS U1220 ( .A(DP_OP_157J21_126_5719_n261), .Y(n771) );
NAND2X8TS U1221 ( .A(n1758), .B(n4524), .Y(n3791) );
ADDFX2TS U1222 ( .A(mult_x_56_n37), .B(mult_x_56_n40), .CI(n3465), .CO(n3464), .S(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N4) );
ADDFHX4TS U1223 ( .A(mult_x_56_n41), .B(mult_x_56_n43), .CI(mult_x_56_n9),
.CO(n3465), .S(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N3) );
BUFX20TS U1224 ( .A(n1641), .Y(n535) );
INVX8TS U1225 ( .A(n1197), .Y(n1559) );
NAND2X6TS U1226 ( .A(n1601), .B(n2176), .Y(n1600) );
NAND2X8TS U1227 ( .A(n1085), .B(n1113), .Y(n3323) );
BUFX16TS U1228 ( .A(n324), .Y(n1113) );
BUFX16TS U1229 ( .A(n312), .Y(n1085) );
NAND2X4TS U1230 ( .A(n3620), .B(n1077), .Y(n732) );
ADDFHX2TS U1231 ( .A(n3451), .B(n3450), .CI(n3449), .CO(n4177), .S(n4178) );
CLKINVX12TS U1232 ( .A(n1873), .Y(n1874) );
CLKINVX6TS U1233 ( .A(add_x_19_n238), .Y(add_x_19_n236) );
BUFX20TS U1234 ( .A(net291904), .Y(net287633) );
ADDHX4TS U1235 ( .A(n2691), .B(n2690), .CO(n2692), .S(n2686) );
NAND2X8TS U1236 ( .A(n1658), .B(n1219), .Y(n2691) );
NAND2X4TS U1237 ( .A(n1689), .B(n3022), .Y(n2816) );
AND2X4TS U1238 ( .A(n2242), .B(n2511), .Y(n883) );
INVX4TS U1239 ( .A(n2840), .Y(n3773) );
INVX6TS U1240 ( .A(DP_OP_156J21_125_3370_n168), .Y(DP_OP_156J21_125_3370_n33) );
ADDFHX4TS U1241 ( .A(n1120), .B(n1039), .CI(n3248), .CO(n3249), .S(n4033) );
INVX6TS U1242 ( .A(n1580), .Y(n1577) );
OAI22X2TS U1243 ( .A0(n2711), .A1(n2747), .B0(n511), .B1(n417), .Y(n2710) );
OAI22X2TS U1244 ( .A0(n2711), .A1(n417), .B0(n2723), .B1(n2747), .Y(n2726)
);
INVX12TS U1245 ( .A(n2007), .Y(n1933) );
INVX16TS U1246 ( .A(n1910), .Y(n1205) );
NOR2X4TS U1247 ( .A(n2007), .B(n1067), .Y(n736) );
NOR2X4TS U1248 ( .A(n546), .B(n1585), .Y(n568) );
NAND3X4TS U1249 ( .A(n2548), .B(n1509), .C(n447), .Y(n780) );
AOI21X4TS U1250 ( .A0(n547), .A1(n907), .B0(n1898), .Y(n1899) );
INVX8TS U1251 ( .A(n1140), .Y(n3304) );
BUFX20TS U1252 ( .A(net291904), .Y(net287641) );
INVX16TS U1253 ( .A(n1114), .Y(n1115) );
NAND3X6TS U1254 ( .A(n739), .B(n741), .C(n738), .Y(n404) );
BUFX8TS U1255 ( .A(net286913), .Y(net286914) );
BUFX12TS U1256 ( .A(n716), .Y(n478) );
CMPR22X2TS U1257 ( .A(n3520), .B(n3519), .CO(n4238), .S(n4239) );
BUFX20TS U1258 ( .A(n562), .Y(n558) );
NAND3X4TS U1259 ( .A(n864), .B(n871), .C(n1167), .Y(n1005) );
INVX4TS U1260 ( .A(DP_OP_158J21_127_356_n70), .Y(DP_OP_158J21_127_356_n71)
);
NOR2X4TS U1261 ( .A(n3025), .B(n3023), .Y(n1571) );
OR2X8TS U1262 ( .A(n3025), .B(n3022), .Y(n1569) );
NOR2X4TS U1263 ( .A(n1611), .B(n2601), .Y(n501) );
NAND2X8TS U1264 ( .A(n573), .B(n483), .Y(n572) );
NAND2X8TS U1265 ( .A(n1904), .B(n1205), .Y(n1434) );
BUFX20TS U1266 ( .A(n1382), .Y(n1340) );
NAND2X8TS U1267 ( .A(n1241), .B(n2284), .Y(n1240) );
AND2X4TS U1268 ( .A(n349), .B(n1038), .Y(n4210) );
BUFX20TS U1269 ( .A(n2948), .Y(n481) );
BUFX20TS U1270 ( .A(n1546), .Y(n1307) );
NAND2X4TS U1271 ( .A(n510), .B(net287974), .Y(n509) );
NAND3X4TS U1272 ( .A(n719), .B(n2398), .C(n1577), .Y(n743) );
INVX8TS U1273 ( .A(n719), .Y(n1492) );
NAND2X6TS U1274 ( .A(n719), .B(n867), .Y(n599) );
CLKBUFX2TS U1275 ( .A(net287909), .Y(n401) );
NAND2X8TS U1276 ( .A(net292332), .B(n475), .Y(net292333) );
BUFX6TS U1277 ( .A(net291630), .Y(n410) );
NAND2X8TS U1278 ( .A(n1717), .B(n1755), .Y(n1716) );
NAND2X8TS U1279 ( .A(n979), .B(n1333), .Y(n978) );
XOR2X4TS U1280 ( .A(n403), .B(n2565), .Y(n2570) );
ADDFHX2TS U1281 ( .A(n2735), .B(n2734), .CI(n2733), .CO(n2744), .S(n2727) );
CLKINVX12TS U1282 ( .A(n718), .Y(n1067) );
NAND2X8TS U1283 ( .A(n1306), .B(n1814), .Y(DP_OP_156J21_125_3370_n168) );
OAI2BB1X4TS U1284 ( .A0N(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[12]), .A1N(n2566),
.B0(n402), .Y(n2630) );
OAI21X1TS U1285 ( .A0(n2566), .A1(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[12]), .B0(n2565),
.Y(n402) );
XOR2X4TS U1286 ( .A(n2566), .B(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[12]), .Y(n403) );
XOR2X4TS U1287 ( .A(n404), .B(n774), .Y(Sgf_operation_EVEN1_Q_left[23]) );
AOI21X4TS U1288 ( .A0(n3214), .A1(n3218), .B0(n3205), .Y(n3206) );
OAI21X4TS U1289 ( .A0(n3227), .A1(n3221), .B0(n3222), .Y(n3214) );
NAND2X8TS U1290 ( .A(n406), .B(n1754), .Y(n611) );
BUFX6TS U1291 ( .A(n1018), .Y(n407) );
ADDFHX4TS U1292 ( .A(mult_x_57_n10), .B(mult_x_57_n69), .CI(mult_x_57_n45),
.CO(n844), .S(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N2)
);
BUFX16TS U1293 ( .A(n1837), .Y(n408) );
OAI21X2TS U1294 ( .A0(net287241), .A1(net293003), .B0(net290443), .Y(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N13) );
INVX4TS U1295 ( .A(n1762), .Y(n2349) );
NAND2X4TS U1296 ( .A(n1266), .B(n1267), .Y(n1349) );
NAND2X4TS U1297 ( .A(n1930), .B(n1680), .Y(n494) );
NAND2X6TS U1298 ( .A(net292023), .B(net292005), .Y(n852) );
ADDFHX4TS U1299 ( .A(n2022), .B(n2021), .CI(n2020), .CO(n2023), .S(n2001) );
XNOR2X4TS U1300 ( .A(n4096), .B(n821), .Y(n2020) );
NOR2X4TS U1301 ( .A(n3600), .B(n3599), .Y(DP_OP_156J21_125_3370_n82) );
NAND2BX2TS U1302 ( .AN(n3599), .B(n2835), .Y(DP_OP_156J21_125_3370_n10) );
AND2X6TS U1303 ( .A(n2010), .B(n2009), .Y(n1576) );
NAND2X2TS U1304 ( .A(net291299), .B(net288852), .Y(net290453) );
NOR2X4TS U1305 ( .A(n1438), .B(n1612), .Y(n502) );
ADDHX4TS U1306 ( .A(n2766), .B(n2767), .CO(n2762), .S(n2780) );
NAND2BX4TS U1307 ( .AN(net292178), .B(net288862), .Y(net292023) );
NAND2X8TS U1308 ( .A(n1504), .B(n1503), .Y(n1502) );
INVX8TS U1309 ( .A(n583), .Y(n409) );
INVX16TS U1310 ( .A(n635), .Y(n583) );
INVX12TS U1311 ( .A(n521), .Y(n635) );
ADDFHX4TS U1312 ( .A(mult_x_58_n41), .B(mult_x_58_n43), .CI(mult_x_58_n9),
.CO(n3417), .S(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N3)
);
ADDFX2TS U1313 ( .A(mult_x_58_n23), .B(mult_x_58_n29), .CI(n2523), .CO(n2577), .S(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N6) );
ADDFX2TS U1314 ( .A(mult_x_58_n30), .B(mult_x_58_n36), .CI(n2520), .CO(n2523), .S(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N5) );
ACHCINX2TS U1315 ( .CIN(n587), .A(n2578), .B(net288590), .CO(n4136) );
NOR2X4TS U1316 ( .A(n2031), .B(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[5]), .Y(n2174) );
NAND2X6TS U1317 ( .A(n2031), .B(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[5]), .Y(n2176) );
NOR2X6TS U1318 ( .A(net288738), .B(net288739), .Y(net287973) );
NAND2X8TS U1319 ( .A(n1932), .B(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[2]), .Y(n2625) );
NAND2X4TS U1320 ( .A(n869), .B(n1267), .Y(n1422) );
BUFX12TS U1321 ( .A(n330), .Y(n412) );
MX2X4TS U1322 ( .A(Data_MY[18]), .B(Op_MY[18]), .S0(net287652), .Y(n330) );
MX2X6TS U1323 ( .A(n3732), .B(n4516), .S0(n830), .Y(n245) );
MX2X4TS U1324 ( .A(n3684), .B(n4514), .S0(n830), .Y(n242) );
MX2X6TS U1325 ( .A(n3708), .B(n4519), .S0(n830), .Y(n243) );
INVX2TS U1326 ( .A(n1084), .Y(n1295) );
NAND2X4TS U1327 ( .A(n1083), .B(n1629), .Y(n1061) );
INVX2TS U1328 ( .A(n4017), .Y(n2662) );
OR2X6TS U1329 ( .A(n2621), .B(n2619), .Y(n877) );
NAND3X4TS U1330 ( .A(n1007), .B(n1006), .C(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[13]), .Y(n1011) );
INVX2TS U1331 ( .A(n2879), .Y(n1080) );
INVX2TS U1332 ( .A(n3743), .Y(n665) );
NOR2X4TS U1333 ( .A(n1637), .B(n787), .Y(n3792) );
NAND2X2TS U1334 ( .A(n960), .B(n963), .Y(n957) );
AND2X4TS U1335 ( .A(n1581), .B(n2552), .Y(n426) );
NAND2X1TS U1336 ( .A(n3183), .B(n3184), .Y(n692) );
NAND2X1TS U1337 ( .A(Sgf_normalized_result[10]), .B(
Sgf_normalized_result[11]), .Y(n3812) );
CLKXOR2X2TS U1338 ( .A(n2569), .B(n2568), .Y(n2617) );
OAI22X2TS U1339 ( .A0(net293204), .A1(net288781), .B0(net291396), .B1(
net287496), .Y(net288777) );
INVX4TS U1340 ( .A(n2507), .Y(n653) );
NOR2X1TS U1341 ( .A(n1564), .B(n881), .Y(n3198) );
INVX4TS U1342 ( .A(n2202), .Y(n3005) );
INVX8TS U1343 ( .A(n447), .Y(n1438) );
NAND2X4TS U1344 ( .A(n1886), .B(n790), .Y(n3753) );
OR2X6TS U1345 ( .A(n1952), .B(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[9]), .Y(n2281) );
NAND2X1TS U1346 ( .A(n3823), .B(n2106), .Y(n2107) );
AND2X2TS U1347 ( .A(n1087), .B(n357), .Y(n3528) );
INVX2TS U1348 ( .A(n3714), .Y(n3800) );
NAND2X2TS U1349 ( .A(n3256), .B(n3284), .Y(n3257) );
AOI2BB2X2TS U1350 ( .B0(n3932), .B1(n3931), .A0N(n3930), .A1N(n4402), .Y(
n4575) );
NAND2X8TS U1351 ( .A(n2747), .B(n2652), .Y(n417) );
INVX6TS U1352 ( .A(n1262), .Y(n2794) );
INVX4TS U1353 ( .A(n734), .Y(n1469) );
INVX2TS U1354 ( .A(n3071), .Y(n498) );
AND2X8TS U1355 ( .A(n2556), .B(n1925), .Y(n427) );
NOR2X6TS U1356 ( .A(n967), .B(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[0]), .Y(n2557) );
AND3X6TS U1357 ( .A(n717), .B(n1933), .C(n867), .Y(n428) );
OR2X8TS U1358 ( .A(n2014), .B(n2013), .Y(n429) );
AND2X8TS U1359 ( .A(n1726), .B(n2602), .Y(n430) );
NAND3X4TS U1360 ( .A(n725), .B(n727), .C(n728), .Y(n1487) );
NAND2X4TS U1361 ( .A(n2850), .B(n2849), .Y(n431) );
OR2X8TS U1362 ( .A(n3010), .B(n3009), .Y(n432) );
OR2X8TS U1363 ( .A(n2501), .B(n2500), .Y(n433) );
BUFX6TS U1364 ( .A(n2616), .Y(n1235) );
NAND2BX1TS U1365 ( .AN(net287972), .B(net287971), .Y(net291594) );
NOR2X4TS U1366 ( .A(n2340), .B(n2339), .Y(n2342) );
XOR2X2TS U1367 ( .A(DP_OP_158J21_127_356_n644), .B(DP_OP_158J21_127_356_n646), .Y(n2339) );
INVX12TS U1368 ( .A(n581), .Y(n578) );
NAND2X8TS U1369 ( .A(DP_OP_159J21_128_5719_n246), .B(net292709), .Y(
net291835) );
NAND2X8TS U1370 ( .A(n578), .B(n577), .Y(n580) );
NAND2X4TS U1371 ( .A(n1968), .B(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[1]), .Y(n2207) );
AND2X4TS U1372 ( .A(net288862), .B(net291299), .Y(n634) );
NAND2X4TS U1373 ( .A(n2400), .B(n1001), .Y(n1490) );
NAND2X6TS U1374 ( .A(n1776), .B(n868), .Y(n1518) );
NAND2X4TS U1375 ( .A(n2864), .B(n2863), .Y(DP_OP_156J21_125_3370_n80) );
NAND2X2TS U1376 ( .A(n868), .B(n3619), .Y(add_x_19_n23) );
MX2X2TS U1377 ( .A(n3774), .B(P_Sgf[14]), .S0(n1091), .Y(n229) );
MX2X2TS U1378 ( .A(n3725), .B(P_Sgf[13]), .S0(n440), .Y(n228) );
XNOR2X2TS U1379 ( .A(n3376), .B(n3377), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N6)
);
NOR2X4TS U1380 ( .A(n527), .B(n444), .Y(n526) );
NAND2X4TS U1381 ( .A(n444), .B(n418), .Y(n684) );
BUFX8TS U1382 ( .A(n1442), .Y(n625) );
NAND2X2TS U1383 ( .A(n3915), .B(n248), .Y(n2458) );
INVX12TS U1384 ( .A(n1246), .Y(n2242) );
INVX3TS U1385 ( .A(n3259), .Y(n2781) );
INVX2TS U1386 ( .A(n460), .Y(n3337) );
NOR2X2TS U1387 ( .A(n4290), .B(n4285), .Y(n4309) );
XNOR2X2TS U1388 ( .A(n3409), .B(n3408), .Y(n3424) );
NAND2X2TS U1389 ( .A(n3597), .B(n4317), .Y(n4321) );
INVX2TS U1390 ( .A(n2784), .Y(n1767) );
NAND2X6TS U1391 ( .A(n2002), .B(n2626), .Y(n2390) );
MX2X2TS U1392 ( .A(n3805), .B(exp_oper_result[3]), .S0(n4584), .Y(n277) );
NAND2X2TS U1393 ( .A(n3336), .B(n3335), .Y(n3338) );
NAND3X1TS U1394 ( .A(n3671), .B(n3670), .C(n3669), .Y(n192) );
NAND2X6TS U1395 ( .A(n2695), .B(n2694), .Y(n3384) );
MX2X2TS U1396 ( .A(n3806), .B(exp_oper_result[2]), .S0(n4584), .Y(n278) );
INVX2TS U1397 ( .A(n3406), .Y(n1297) );
OAI21X1TS U1398 ( .A0(n2268), .A1(n1091), .B0(n1305), .Y(n223) );
INVX2TS U1399 ( .A(n4300), .Y(n1412) );
NAND2X2TS U1400 ( .A(n2142), .B(n2169), .Y(n2149) );
XOR2X2TS U1401 ( .A(n2105), .B(n926), .Y(n3919) );
INVX4TS U1402 ( .A(n1117), .Y(n687) );
NAND2X1TS U1403 ( .A(n1091), .B(P_Sgf[8]), .Y(n1305) );
INVX8TS U1404 ( .A(n449), .Y(n1127) );
INVX8TS U1405 ( .A(n3667), .Y(n3927) );
NAND2X4TS U1406 ( .A(n498), .B(n442), .Y(n1222) );
NAND2X2TS U1407 ( .A(n3653), .B(n4395), .Y(n214) );
INVX6TS U1408 ( .A(n1850), .Y(n1091) );
INVX8TS U1409 ( .A(n3709), .Y(n3873) );
INVX8TS U1410 ( .A(n1850), .Y(n440) );
AND2X6TS U1411 ( .A(n2070), .B(n894), .Y(n913) );
INVX6TS U1412 ( .A(n1128), .Y(n1129) );
BUFX8TS U1413 ( .A(n3904), .Y(n3875) );
BUFX8TS U1414 ( .A(n3904), .Y(n3903) );
NAND3X1TS U1415 ( .A(n4534), .B(n4585), .C(FSM_selector_B_1_), .Y(n2388) );
XOR2X2TS U1416 ( .A(n3053), .B(n3080), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N2)
);
MX2X2TS U1417 ( .A(n3983), .B(Add_result[16]), .S0(n4014), .Y(n290) );
INVX3TS U1418 ( .A(n461), .Y(n1660) );
INVX4TS U1419 ( .A(n2280), .Y(n1334) );
BUFX12TS U1420 ( .A(n3840), .Y(n4534) );
BUFX8TS U1421 ( .A(n1655), .Y(n461) );
NOR2BX2TS U1422 ( .AN(n3069), .B(n474), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N0)
);
NOR2X2TS U1423 ( .A(net287495), .B(net287496), .Y(n3433) );
NAND2X2TS U1424 ( .A(n4010), .B(n3833), .Y(n3995) );
INVX3TS U1425 ( .A(n4010), .Y(n3989) );
NAND2X6TS U1426 ( .A(n892), .B(n1368), .Y(n2722) );
NAND2X2TS U1427 ( .A(n1589), .B(n3068), .Y(n1588) );
CLKINVX2TS U1428 ( .A(net287489), .Y(net291787) );
NOR2X6TS U1429 ( .A(n3848), .B(n3820), .Y(n2837) );
NAND2X4TS U1430 ( .A(n1277), .B(n1276), .Y(n2189) );
INVX4TS U1431 ( .A(n2961), .Y(n573) );
CLKINVX2TS U1432 ( .A(n3862), .Y(overflow_flag) );
INVX8TS U1433 ( .A(n1562), .Y(n1563) );
INVX3TS U1434 ( .A(net288781), .Y(n582) );
NAND2X4TS U1435 ( .A(n2348), .B(n2351), .Y(n2337) );
INVX3TS U1436 ( .A(n2120), .Y(n1277) );
INVX2TS U1437 ( .A(n3947), .Y(n3942) );
NAND2X6TS U1438 ( .A(n702), .B(n701), .Y(n734) );
INVX12TS U1439 ( .A(n442), .Y(n437) );
NAND2X4TS U1440 ( .A(DP_OP_158J21_127_356_n318), .B(n2336), .Y(n2348) );
NAND2X2TS U1441 ( .A(n1707), .B(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[8]), .Y(n1706) );
INVX2TS U1442 ( .A(DP_OP_158J21_127_356_n397), .Y(n1674) );
NAND2X4TS U1443 ( .A(Sgf_normalized_result[5]), .B(Sgf_normalized_result[4]),
.Y(n3947) );
INVX3TS U1444 ( .A(DP_OP_158J21_127_356_n692), .Y(n500) );
NOR2X8TS U1445 ( .A(FS_Module_state_reg[2]), .B(n4386), .Y(n3855) );
INVX4TS U1446 ( .A(DP_OP_154J21_123_2814_n91), .Y(n1918) );
INVX2TS U1447 ( .A(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[2]), .Y(
n1699) );
NAND2X2TS U1448 ( .A(n3624), .B(add_x_19_n40), .Y(add_x_19_n39) );
INVX4TS U1449 ( .A(n1633), .Y(DP_OP_156J21_125_3370_n174) );
NOR2X4TS U1450 ( .A(n690), .B(n689), .Y(n4489) );
NAND2X6TS U1451 ( .A(n1821), .B(n915), .Y(n1164) );
NAND2X2TS U1452 ( .A(n3924), .B(n3850), .Y(n4553) );
INVX8TS U1453 ( .A(n2614), .Y(n3606) );
BUFX8TS U1454 ( .A(n1894), .Y(n767) );
NAND2X2TS U1455 ( .A(n2458), .B(n657), .Y(n201) );
INVX4TS U1456 ( .A(n3438), .Y(n730) );
NOR2X4TS U1457 ( .A(n949), .B(n938), .Y(n948) );
OR2X4TS U1458 ( .A(n992), .B(n989), .Y(n911) );
NAND2X4TS U1459 ( .A(n3358), .B(DP_OP_158J21_127_356_n33), .Y(n1024) );
NAND2X4TS U1460 ( .A(n1686), .B(n1685), .Y(n1684) );
BUFX3TS U1461 ( .A(n597), .Y(n596) );
NAND2X4TS U1462 ( .A(n570), .B(n2625), .Y(n1937) );
INVX6TS U1463 ( .A(n983), .Y(n1779) );
NAND3X4TS U1464 ( .A(n3793), .B(n2387), .C(n687), .Y(n686) );
INVX6TS U1465 ( .A(n2242), .Y(n995) );
INVX2TS U1466 ( .A(n4067), .Y(n3274) );
NAND3X6TS U1467 ( .A(n961), .B(n958), .C(n957), .Y(n2011) );
NAND2X2TS U1468 ( .A(n3379), .B(n3380), .Y(n3382) );
INVX2TS U1469 ( .A(n2991), .Y(n2993) );
NOR2X2TS U1470 ( .A(n2833), .B(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[0]), .Y(n1676) );
INVX4TS U1471 ( .A(n3878), .Y(n2299) );
NOR2X4TS U1472 ( .A(n1298), .B(n1297), .Y(n3419) );
NAND2X4TS U1473 ( .A(n2450), .B(n467), .Y(n698) );
INVX2TS U1474 ( .A(n3356), .Y(n1743) );
NAND2X4TS U1475 ( .A(n956), .B(n963), .Y(n961) );
NOR2BX2TS U1476 ( .AN(n1412), .B(n4286), .Y(n4304) );
NAND2X4TS U1477 ( .A(n1891), .B(n4357), .Y(n3780) );
INVX2TS U1478 ( .A(n4056), .Y(n3275) );
NAND2X4TS U1479 ( .A(n962), .B(n959), .Y(n958) );
NAND2X6TS U1480 ( .A(n1511), .B(n1510), .Y(n2964) );
NAND2X2TS U1481 ( .A(n1480), .B(n3234), .Y(n3235) );
XOR2X4TS U1482 ( .A(n3317), .B(n3323), .Y(n4498) );
NAND2X4TS U1483 ( .A(n516), .B(n515), .Y(n2728) );
NAND2X4TS U1484 ( .A(n605), .B(n1371), .Y(n604) );
NAND2X4TS U1485 ( .A(n1849), .B(n459), .Y(n458) );
INVX12TS U1486 ( .A(n3714), .Y(n3850) );
NAND2X4TS U1487 ( .A(n1010), .B(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[13]), .Y(n1012) );
NAND2X2TS U1488 ( .A(n3448), .B(n4160), .Y(n4161) );
INVX4TS U1489 ( .A(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N1),
.Y(n4026) );
NAND2X2TS U1490 ( .A(n3842), .B(n3860), .Y(n4582) );
CMPR22X2TS U1491 ( .A(n3544), .B(n3543), .CO(n4260), .S(n4261) );
NOR2X2TS U1492 ( .A(n3294), .B(n3292), .Y(n3327) );
NAND2X2TS U1493 ( .A(n1371), .B(n3561), .Y(n3563) );
AND2X2TS U1494 ( .A(n312), .B(n345), .Y(n3496) );
NAND2X4TS U1495 ( .A(n693), .B(n692), .Y(n3197) );
INVX4TS U1496 ( .A(n3156), .Y(n679) );
INVX8TS U1497 ( .A(n3915), .Y(n3714) );
INVX12TS U1498 ( .A(n1190), .Y(n1239) );
NAND2X4TS U1499 ( .A(n454), .B(n453), .Y(n2481) );
NAND2X4TS U1500 ( .A(n2246), .B(n1341), .Y(n2250) );
INVX4TS U1501 ( .A(n3388), .Y(n3312) );
NAND2X6TS U1502 ( .A(n1647), .B(n1835), .Y(n1646) );
INVX2TS U1503 ( .A(n2070), .Y(n1385) );
NAND2X4TS U1504 ( .A(n1885), .B(n3726), .Y(n666) );
INVX8TS U1505 ( .A(n3667), .Y(n3929) );
INVX6TS U1506 ( .A(n3930), .Y(n449) );
INVX8TS U1507 ( .A(n1711), .Y(n2594) );
INVX8TS U1508 ( .A(n3667), .Y(n3932) );
MX2X2TS U1509 ( .A(n3837), .B(Add_result[23]), .S0(n3986), .Y(n283) );
INVX12TS U1510 ( .A(n1095), .Y(n1097) );
INVX8TS U1511 ( .A(net288241), .Y(n649) );
NAND2X2TS U1512 ( .A(n2546), .B(n2579), .Y(n2547) );
NAND2X6TS U1513 ( .A(n1177), .B(n1176), .Y(n1471) );
NAND2X4TS U1514 ( .A(n2678), .B(n1588), .Y(n2735) );
INVX3TS U1515 ( .A(n1317), .Y(n313) );
NOR2X4TS U1516 ( .A(n3858), .B(FSM_selector_C), .Y(n1897) );
INVX8TS U1517 ( .A(n2207), .Y(n439) );
OR2X8TS U1518 ( .A(n3799), .B(n4395), .Y(n3709) );
NAND2X4TS U1519 ( .A(n750), .B(n2398), .Y(n742) );
INVX6TS U1520 ( .A(n1316), .Y(n314) );
NOR2X4TS U1521 ( .A(n960), .B(n963), .Y(n959) );
NAND2X4TS U1522 ( .A(n606), .B(n3569), .Y(n3594) );
NAND2X4TS U1523 ( .A(n1660), .B(n1659), .Y(n1658) );
INVX6TS U1524 ( .A(n4589), .Y(n1128) );
INVX2TS U1525 ( .A(n3184), .Y(n694) );
NAND2X4TS U1526 ( .A(n2281), .B(n1334), .Y(n1705) );
INVX12TS U1527 ( .A(n1088), .Y(n1089) );
NAND2X6TS U1528 ( .A(n1863), .B(n782), .Y(n1648) );
NAND2X2TS U1529 ( .A(n3052), .B(n3079), .Y(n3053) );
CLKMX2X3TS U1530 ( .A(Data_MX[23]), .B(Op_MX[23]), .S0(net286911), .Y(n367)
);
CMPR32X2TS U1531 ( .A(n3176), .B(n3175), .C(n3174), .CO(n3184), .S(n3173) );
BUFX16TS U1532 ( .A(n1668), .Y(n721) );
CLKMX2X3TS U1533 ( .A(Data_MY[29]), .B(Op_MY[29]), .S0(net286911), .Y(n341)
);
NAND2X6TS U1534 ( .A(n2151), .B(n1182), .Y(n2177) );
MX2X4TS U1535 ( .A(n1323), .B(n927), .S0(net287652), .Y(n1316) );
NAND2X4TS U1536 ( .A(n1884), .B(n789), .Y(n3743) );
MX2X6TS U1537 ( .A(Data_MY[17]), .B(Op_MY[17]), .S0(net286914), .Y(n329) );
INVX4TS U1538 ( .A(net288809), .Y(n577) );
NAND2X2TS U1539 ( .A(n2025), .B(n2529), .Y(n2026) );
INVX4TS U1540 ( .A(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N6),
.Y(net288689) );
MX2X4TS U1541 ( .A(Data_MY[21]), .B(Op_MY[21]), .S0(net287652), .Y(n333) );
MX2X4TS U1542 ( .A(n1327), .B(n932), .S0(net287652), .Y(n1317) );
INVX2TS U1543 ( .A(net288775), .Y(net291992) );
NOR2X4TS U1544 ( .A(n3089), .B(n3088), .Y(n3135) );
INVX6TS U1545 ( .A(n1922), .Y(n1341) );
INVX4TS U1546 ( .A(n1865), .Y(n766) );
NAND2X4TS U1547 ( .A(n1447), .B(n2273), .Y(n1446) );
INVX8TS U1548 ( .A(n589), .Y(n2731) );
INVX2TS U1549 ( .A(n3632), .Y(n3334) );
BUFX12TS U1550 ( .A(n3856), .Y(n1124) );
BUFX12TS U1551 ( .A(n3856), .Y(n3830) );
NAND2X4TS U1552 ( .A(n2837), .B(FS_Module_state_reg[1]), .Y(n2839) );
NAND2X6TS U1553 ( .A(n1530), .B(n3855), .Y(n3840) );
NOR2X4TS U1554 ( .A(n656), .B(n654), .Y(n1870) );
NAND2BX2TS U1555 ( .AN(n3843), .B(n4488), .Y(n3632) );
INVX6TS U1556 ( .A(n3940), .Y(n3984) );
ADDFHX2TS U1557 ( .A(n3133), .B(n3132), .CI(n3131), .CO(n3137), .S(n3089) );
AND2X8TS U1558 ( .A(n3855), .B(n3654), .Y(n3874) );
NAND2X4TS U1559 ( .A(n1947), .B(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[8]), .Y(n2231) );
NAND2X4TS U1560 ( .A(n1873), .B(n1431), .Y(n1430) );
CLKINVX2TS U1561 ( .A(n3965), .Y(n3958) );
INVX2TS U1562 ( .A(n2205), .Y(n1281) );
NAND2X4TS U1563 ( .A(n2332), .B(n1566), .Y(n1565) );
NAND2X6TS U1564 ( .A(n854), .B(net288845), .Y(n468) );
NOR2X4TS U1565 ( .A(n1882), .B(n813), .Y(n3698) );
NAND2X2TS U1566 ( .A(n2114), .B(n2113), .Y(n2203) );
NOR2X4TS U1567 ( .A(n2134), .B(n2133), .Y(n2146) );
NAND2X4TS U1568 ( .A(n1883), .B(n786), .Y(n3737) );
NAND2X4TS U1569 ( .A(n1708), .B(n1706), .Y(n2000) );
INVX8TS U1570 ( .A(n1904), .Y(n1470) );
INVX3TS U1571 ( .A(n2122), .Y(n1279) );
MX2X2TS U1572 ( .A(n3762), .B(n4508), .S0(n823), .Y(n238) );
NOR2X4TS U1573 ( .A(n3999), .B(n3816), .Y(n4010) );
NAND2X4TS U1574 ( .A(n1918), .B(DP_OP_154J21_123_2814_n92), .Y(n1361) );
NOR2X4TS U1575 ( .A(n2384), .B(n2383), .Y(n2510) );
INVX2TS U1576 ( .A(n2384), .Y(n1586) );
INVX6TS U1577 ( .A(net288847), .Y(n854) );
NOR2X4TS U1578 ( .A(n420), .B(n1674), .Y(n1673) );
MX2X2TS U1579 ( .A(Op_MX[27]), .B(n276), .S0(FSM_selector_A), .Y(n2049) );
NAND2X4TS U1580 ( .A(n1750), .B(DP_OP_158J21_127_356_n615), .Y(n2661) );
NAND2X4TS U1581 ( .A(n425), .B(n2654), .Y(n1751) );
INVX2TS U1582 ( .A(n3400), .Y(n1379) );
INVX8TS U1583 ( .A(n2878), .Y(n3567) );
NOR2X2TS U1584 ( .A(n3809), .B(n4410), .Y(n3811) );
INVX2TS U1585 ( .A(n3988), .Y(n4012) );
NOR2X4TS U1586 ( .A(n3158), .B(n3247), .Y(n3084) );
INVX2TS U1587 ( .A(n4001), .Y(n4002) );
NOR2X2TS U1588 ( .A(n876), .B(n3247), .Y(n3140) );
NOR3X1TS U1589 ( .A(Op_MX[0]), .B(Op_MX[23]), .C(Op_MX[25]), .Y(n3880) );
BUFX4TS U1590 ( .A(Op_MY[10]), .Y(n1157) );
NAND2X4TS U1591 ( .A(DP_OP_158J21_127_356_n1043), .B(
DP_OP_158J21_127_356_n599), .Y(n1750) );
NAND3X4TS U1592 ( .A(n4473), .B(n4472), .C(n4471), .Y(n3988) );
NAND3X4TS U1593 ( .A(n4464), .B(n4463), .C(n4462), .Y(n4005) );
INVX6TS U1594 ( .A(n796), .Y(n555) );
NOR2X4TS U1595 ( .A(DP_OP_158J21_127_356_n612), .B(DP_OP_158J21_127_356_n599), .Y(n1591) );
NAND3X4TS U1596 ( .A(n4487), .B(n4486), .C(n4485), .Y(n3954) );
OR2X2TS U1597 ( .A(n4351), .B(n817), .Y(n951) );
INVX6TS U1598 ( .A(Sgf_operation_Result[2]), .Y(n2118) );
NAND2X2TS U1599 ( .A(DP_OP_156J21_125_3370_n299), .B(
DP_OP_156J21_125_3370_n408), .Y(n2210) );
INVX3TS U1600 ( .A(Sgf_operation_EVEN1_Q_left[0]), .Y(n1282) );
NAND2X6TS U1601 ( .A(n1064), .B(n1063), .Y(n1062) );
CMPR22X2TS U1602 ( .A(Op_MX[18]), .B(Op_MX[12]), .CO(n2875), .S(n2878) );
INVX6TS U1603 ( .A(DP_OP_153J21_122_3500_n244), .Y(n1286) );
INVX6TS U1604 ( .A(DP_OP_153J21_122_3500_n194), .Y(n1285) );
AND2X4TS U1605 ( .A(mult_x_59_b_3_), .B(mult_x_59_a_4_), .Y(n3556) );
INVX2TS U1606 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[0]), .Y(
n1678) );
INVX2TS U1607 ( .A(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[4]), .Y(
n1461) );
INVX2TS U1608 ( .A(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[7]), .Y(
n724) );
NAND2X4TS U1609 ( .A(DP_OP_156J21_125_3370_n205), .B(
DP_OP_156J21_125_3370_n208), .Y(DP_OP_156J21_125_3370_n61) );
NAND2X4TS U1610 ( .A(n551), .B(n3045), .Y(DP_OP_156J21_125_3370_n36) );
NAND2X4TS U1611 ( .A(DP_OP_156J21_125_3370_n197), .B(
DP_OP_156J21_125_3370_n200), .Y(DP_OP_156J21_125_3370_n45) );
INVX4TS U1612 ( .A(add_x_19_n272), .Y(add_x_19_n271) );
NAND2X6TS U1613 ( .A(n732), .B(n731), .Y(n2855) );
NAND2X6TS U1614 ( .A(n1716), .B(n1433), .Y(n1719) );
NAND2X6TS U1615 ( .A(n1825), .B(n2607), .Y(n1820) );
NAND2X2TS U1616 ( .A(n3611), .B(n3610), .Y(add_x_19_n26) );
NAND2X2TS U1617 ( .A(n3606), .B(n3616), .Y(add_x_19_n22) );
NAND2X4TS U1618 ( .A(n3852), .B(n2388), .Y(n308) );
NAND2X2TS U1619 ( .A(n3928), .B(n3915), .Y(n4566) );
NAND2X2TS U1620 ( .A(n3804), .B(n3928), .Y(n4565) );
NAND2X2TS U1621 ( .A(n3910), .B(n3924), .Y(n4552) );
NAND2X6TS U1622 ( .A(n709), .B(n708), .Y(n707) );
NAND2X2TS U1623 ( .A(n3804), .B(n3775), .Y(n4556) );
NAND2X2TS U1624 ( .A(n3926), .B(n3850), .Y(n4562) );
NAND2X2TS U1625 ( .A(n3799), .B(n3798), .Y(n4546) );
INVX8TS U1626 ( .A(add_x_19_n237), .Y(add_x_19_n320) );
NAND2X2TS U1627 ( .A(n3800), .B(n3775), .Y(n4557) );
MX2X2TS U1628 ( .A(n2846), .B(P_Sgf[15]), .S0(n440), .Y(n230) );
NAND2X6TS U1629 ( .A(n3030), .B(n3029), .Y(n3616) );
INVX4TS U1630 ( .A(n1069), .Y(add_x_19_n76) );
NAND2X2TS U1631 ( .A(n3804), .B(n768), .Y(n4545) );
NAND2X6TS U1632 ( .A(n2376), .B(Sgf_operation_EVEN1_Q_left[0]), .Y(
add_x_19_n238) );
NAND2X4TS U1633 ( .A(n1458), .B(n828), .Y(n1457) );
NAND2X6TS U1634 ( .A(n1474), .B(n828), .Y(n1418) );
INVX6TS U1635 ( .A(n2856), .Y(n3030) );
NOR2X6TS U1636 ( .A(n2495), .B(n652), .Y(n651) );
NAND2X4TS U1637 ( .A(n1354), .B(n828), .Y(n1353) );
NAND2X4TS U1638 ( .A(n1759), .B(n828), .Y(n1758) );
NAND3X6TS U1639 ( .A(n1753), .B(n1653), .C(n1652), .Y(n1651) );
NAND2X6TS U1640 ( .A(n567), .B(n936), .Y(n566) );
INVX8TS U1641 ( .A(n1568), .Y(n1218) );
NAND2X6TS U1642 ( .A(n569), .B(n2390), .Y(n1423) );
NAND2X4TS U1643 ( .A(n3438), .B(n2984), .Y(n592) );
INVX12TS U1644 ( .A(n1153), .Y(n443) );
INVX8TS U1645 ( .A(n1733), .Y(n1734) );
INVX8TS U1646 ( .A(n1472), .Y(n1255) );
INVX4TS U1647 ( .A(n1665), .Y(n2646) );
NAND2X6TS U1648 ( .A(n898), .B(n974), .Y(n1593) );
INVX6TS U1649 ( .A(net287916), .Y(n621) );
NOR2X4TS U1650 ( .A(n4481), .B(n4060), .Y(n3399) );
NAND2X6TS U1651 ( .A(n994), .B(n2511), .Y(n1472) );
AND2X2TS U1652 ( .A(n2984), .B(n3441), .Y(n919) );
INVX12TS U1653 ( .A(n1611), .Y(n445) );
NAND2X6TS U1654 ( .A(n2511), .B(n995), .Y(n991) );
XOR2X2TS U1655 ( .A(n1149), .B(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[8]), .Y(n1148) );
INVX4TS U1656 ( .A(n4053), .Y(n3325) );
NAND3X2TS U1657 ( .A(n3765), .B(n3764), .C(n3763), .Y(n200) );
INVX8TS U1658 ( .A(n2380), .Y(n446) );
NAND2X6TS U1659 ( .A(n2644), .B(n784), .Y(n1665) );
NAND2X6TS U1660 ( .A(n2512), .B(n2242), .Y(n994) );
NAND2X6TS U1661 ( .A(n460), .B(n3336), .Y(n499) );
NAND3X6TS U1662 ( .A(n3418), .B(n1299), .C(n3406), .Y(n1206) );
NAND2X6TS U1663 ( .A(n2940), .B(n2939), .Y(n1442) );
AND2X2TS U1664 ( .A(n3368), .B(n3367), .Y(n3369) );
AND3X8TS U1665 ( .A(n699), .B(n2460), .C(n698), .Y(n697) );
BUFX20TS U1666 ( .A(n752), .Y(n447) );
NAND2X6TS U1667 ( .A(n1555), .B(n1554), .Y(n2379) );
NAND2X4TS U1668 ( .A(n1332), .B(n3387), .Y(n1331) );
NAND3X6TS U1669 ( .A(n914), .B(n1745), .C(n1151), .Y(n1150) );
NAND2X6TS U1670 ( .A(n757), .B(n2260), .Y(n755) );
ADDFHX2TS U1671 ( .A(n3566), .B(n3565), .CI(n3564), .CO(n4287), .S(n4288) );
NAND2X6TS U1672 ( .A(n458), .B(n3263), .Y(n460) );
NAND2X6TS U1673 ( .A(n486), .B(n757), .Y(n756) );
NAND2X4TS U1674 ( .A(n2481), .B(n452), .Y(n643) );
INVX12TS U1675 ( .A(n485), .Y(n1813) );
INVX8TS U1676 ( .A(n607), .Y(n626) );
ADDFHX2TS U1677 ( .A(n3352), .B(n3351), .CI(n3350), .CO(n3359), .S(n3344) );
XOR2X2TS U1678 ( .A(n3563), .B(n3562), .Y(n3566) );
NAND2X2TS U1679 ( .A(n3218), .B(n3217), .Y(n3219) );
NAND2X6TS U1680 ( .A(n2944), .B(n1402), .Y(n1404) );
MXI2X2TS U1681 ( .A(n3854), .B(n1851), .S0(n4584), .Y(n279) );
NAND2X2TS U1682 ( .A(n2175), .B(n1175), .Y(n2158) );
NAND3X6TS U1683 ( .A(n674), .B(n1481), .C(n1480), .Y(n673) );
NOR2X2TS U1684 ( .A(n3428), .B(n3430), .Y(n4144) );
INVX2TS U1685 ( .A(n4320), .Y(n831) );
NAND2X6TS U1686 ( .A(n1770), .B(n1175), .Y(n1003) );
NAND2X6TS U1687 ( .A(n1890), .B(n795), .Y(n3776) );
AO21X2TS U1688 ( .A0(n3329), .A1(n4107), .B0(n3328), .Y(n3330) );
NAND2X6TS U1689 ( .A(n776), .B(n775), .Y(n2944) );
CLKMX2X2TS U1690 ( .A(n3879), .B(P_Sgf[9]), .S0(n440), .Y(n224) );
NAND2X2TS U1691 ( .A(n3056), .B(n3055), .Y(n3057) );
NAND2X4TS U1692 ( .A(n2199), .B(n2198), .Y(n2200) );
OR2X4TS U1693 ( .A(n645), .B(n2482), .Y(n452) );
INVX8TS U1694 ( .A(n2195), .Y(n944) );
NAND3X4TS U1695 ( .A(n1030), .B(n1029), .C(n3753), .Y(n1028) );
AND2X6TS U1696 ( .A(n1924), .B(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[1]), .Y(n754) );
ADDFHX2TS U1697 ( .A(n3499), .B(n3498), .CI(n3497), .CO(n4240), .S(n4241) );
NAND2X6TS U1698 ( .A(n2597), .B(n1998), .Y(n962) );
NAND2X6TS U1699 ( .A(n1481), .B(n672), .Y(n671) );
NAND2X6TS U1700 ( .A(n1188), .B(n3877), .Y(n2240) );
NAND2X4TS U1701 ( .A(n2168), .B(n2167), .Y(n2238) );
NAND2X2TS U1702 ( .A(n3239), .B(n3238), .Y(n3241) );
INVX2TS U1703 ( .A(n1902), .Y(n4018) );
NAND2X4TS U1704 ( .A(n1372), .B(n3585), .Y(n605) );
ADDHX1TS U1705 ( .A(n3488), .B(n3487), .CO(n4203), .S(n4204) );
CMPR22X2TS U1706 ( .A(n3558), .B(n3557), .CO(n4258), .S(n3537) );
ADDHX1TS U1707 ( .A(n3496), .B(n3495), .CO(n4213), .S(n4214) );
NAND2X6TS U1708 ( .A(n747), .B(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[13]), .Y(n727) );
XNOR2X2TS U1709 ( .A(n1845), .B(n3571), .Y(n3572) );
NAND2X2TS U1710 ( .A(n3593), .B(n3592), .Y(n3595) );
INVX3TS U1711 ( .A(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N10),
.Y(n4311) );
NOR2X4TS U1712 ( .A(n3278), .B(n3279), .Y(n1740) );
NAND2X6TS U1713 ( .A(n1507), .B(n439), .Y(n1247) );
AND2X2TS U1714 ( .A(n361), .B(n1087), .Y(n3559) );
AND2X4TS U1715 ( .A(n3063), .B(n1748), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N1)
);
NAND2X2TS U1716 ( .A(n3412), .B(n3411), .Y(n3413) );
AND2X2TS U1717 ( .A(n1038), .B(n348), .Y(n4193) );
AND2X2TS U1718 ( .A(n312), .B(n346), .Y(n4209) );
BUFX12TS U1719 ( .A(n321), .Y(n1099) );
AND2X2TS U1720 ( .A(n361), .B(n326), .Y(n4280) );
BUFX8TS U1721 ( .A(n320), .Y(n1121) );
AND2X2TS U1722 ( .A(n329), .B(n358), .Y(n4279) );
CLKMX2X2TS U1723 ( .A(n3877), .B(P_Sgf[7]), .S0(n440), .Y(n222) );
CLKMX2X3TS U1724 ( .A(n3876), .B(P_Sgf[6]), .S0(n440), .Y(n221) );
INVX4TS U1725 ( .A(n2087), .Y(n2056) );
NAND2X2TS U1726 ( .A(n329), .B(n317), .Y(n3390) );
INVX6TS U1727 ( .A(n3157), .Y(n675) );
AOI22X1TS U1728 ( .A0(n3866), .A1(Add_result[21]), .B0(n3988), .B1(n4533),
.Y(n4555) );
AOI22X1TS U1729 ( .A0(n3866), .A1(Add_result[18]), .B0(n4006), .B1(n4533),
.Y(n4564) );
INVX4TS U1730 ( .A(n1078), .Y(n584) );
NAND2BX2TS U1731 ( .AN(n2746), .B(n1723), .Y(n1722) );
INVX4TS U1732 ( .A(n2168), .Y(n1188) );
NOR2BX2TS U1733 ( .AN(n496), .B(n1042), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N0)
);
INVX4TS U1734 ( .A(n2092), .Y(n2096) );
BUFX12TS U1735 ( .A(n3362), .Y(n1560) );
NAND2X2TS U1736 ( .A(n412), .B(n1113), .Y(n4152) );
INVX6TS U1737 ( .A(n3709), .Y(n3913) );
MX2X2TS U1738 ( .A(n3998), .B(Add_result[22]), .S0(n4534), .Y(n284) );
AO22X2TS U1739 ( .A0(n3875), .A1(n4005), .B0(final_result_ieee[16]), .B1(
n3905), .Y(n174) );
AO22X2TS U1740 ( .A0(n3875), .A1(n3961), .B0(final_result_ieee[15]), .B1(
n3905), .Y(n175) );
MX2X2TS U1741 ( .A(n3841), .B(Add_result[18]), .S0(n4014), .Y(n288) );
AO22X2TS U1742 ( .A0(n3875), .A1(n3968), .B0(final_result_ieee[14]), .B1(
n3902), .Y(n176) );
AO22X2TS U1743 ( .A0(n3875), .A1(n3954), .B0(final_result_ieee[13]), .B1(
n3902), .Y(n177) );
NAND2X4TS U1744 ( .A(n3061), .B(n3062), .Y(n1748) );
AO22X2TS U1745 ( .A0(n3875), .A1(Sgf_normalized_result[12]), .B0(
final_result_ieee[12]), .B1(n3902), .Y(n178) );
MX2X2TS U1746 ( .A(n4015), .B(Add_result[20]), .S0(n4014), .Y(n286) );
INVX6TS U1747 ( .A(n478), .Y(n715) );
AO22X2TS U1748 ( .A0(n3875), .A1(Sgf_normalized_result[11]), .B0(
final_result_ieee[11]), .B1(n3902), .Y(n179) );
AO22X2TS U1749 ( .A0(n3903), .A1(Sgf_normalized_result[10]), .B0(
final_result_ieee[10]), .B1(n3902), .Y(n180) );
AO22X2TS U1750 ( .A0(n3903), .A1(Sgf_normalized_result[9]), .B0(
final_result_ieee[9]), .B1(n3902), .Y(n181) );
AO22X2TS U1751 ( .A0(n3903), .A1(Sgf_normalized_result[1]), .B0(
final_result_ieee[1]), .B1(n3900), .Y(n189) );
AOI2BB2X1TS U1752 ( .B0(n3871), .B1(n1838), .A0N(n3870), .A1N(
final_result_ieee[30]), .Y(n263) );
MX2X2TS U1753 ( .A(n4004), .B(Add_result[19]), .S0(n4014), .Y(n287) );
AO22X2TS U1754 ( .A0(n3903), .A1(Sgf_normalized_result[8]), .B0(
final_result_ieee[8]), .B1(n3902), .Y(n182) );
AO22X2TS U1755 ( .A0(n3903), .A1(Sgf_normalized_result[7]), .B0(
final_result_ieee[7]), .B1(n3902), .Y(n183) );
AO22X2TS U1756 ( .A0(n3903), .A1(Sgf_normalized_result[2]), .B0(
final_result_ieee[2]), .B1(n3900), .Y(n188) );
AO22X2TS U1757 ( .A0(n3903), .A1(Sgf_normalized_result[3]), .B0(
final_result_ieee[3]), .B1(n3900), .Y(n187) );
NAND2X6TS U1758 ( .A(n1401), .B(n779), .Y(n778) );
AO22X2TS U1759 ( .A0(n3903), .A1(Sgf_normalized_result[4]), .B0(
final_result_ieee[4]), .B1(n3900), .Y(n186) );
AO22X2TS U1760 ( .A0(n3903), .A1(Sgf_normalized_result[6]), .B0(
final_result_ieee[6]), .B1(n3902), .Y(n184) );
AO22X2TS U1761 ( .A0(n3903), .A1(Sgf_normalized_result[5]), .B0(
final_result_ieee[5]), .B1(n3900), .Y(n185) );
AO22X2TS U1762 ( .A0(n3875), .A1(n4006), .B0(final_result_ieee[17]), .B1(
n3902), .Y(n173) );
AOI2BB2X1TS U1763 ( .B0(n3871), .B1(n1851), .A0N(n3870), .A1N(
final_result_ieee[24]), .Y(n269) );
MX2X2TS U1764 ( .A(n4009), .B(Add_result[17]), .S0(n4014), .Y(n289) );
AO22X2TS U1765 ( .A0(n3871), .A1(n3991), .B0(final_result_ieee[21]), .B1(
n3905), .Y(n169) );
NAND2X6TS U1766 ( .A(n1471), .B(n896), .Y(n1016) );
MX2X2TS U1767 ( .A(n3994), .B(Add_result[21]), .S0(n4014), .Y(n285) );
MX2X2TS U1768 ( .A(n3964), .B(Add_result[15]), .S0(n4014), .Y(n291) );
INVX12TS U1769 ( .A(n1315), .Y(n326) );
OR2X6TS U1770 ( .A(n2053), .B(n2052), .Y(n894) );
OR2X6TS U1771 ( .A(n2069), .B(n2068), .Y(n2070) );
CLKMX2X2TS U1772 ( .A(n3920), .B(Add_result[1]), .S0(n4534), .Y(n305) );
NAND2X6TS U1773 ( .A(n541), .B(n819), .Y(n561) );
INVX8TS U1774 ( .A(n332), .Y(n1040) );
INVX8TS U1775 ( .A(n1728), .Y(n2252) );
MX2X2TS U1776 ( .A(n3957), .B(Add_result[13]), .S0(n3986), .Y(n293) );
NAND2X4TS U1777 ( .A(n328), .B(n316), .Y(n3387) );
INVX8TS U1778 ( .A(n1792), .Y(n492) );
OR2X4TS U1779 ( .A(n606), .B(n3569), .Y(n3570) );
MX2X2TS U1780 ( .A(n3977), .B(Add_result[12]), .S0(n3986), .Y(n294) );
MX2X2TS U1781 ( .A(n3974), .B(Add_result[11]), .S0(n3986), .Y(n295) );
NAND2X6TS U1782 ( .A(n953), .B(n1907), .Y(n1908) );
INVX2TS U1783 ( .A(n3183), .Y(n695) );
MX2X2TS U1784 ( .A(n3971), .B(Add_result[14]), .S0(n3986), .Y(n292) );
MX2X2TS U1785 ( .A(n3981), .B(Add_result[10]), .S0(n3986), .Y(n296) );
INVX8TS U1786 ( .A(n1492), .Y(n1491) );
MX2X2TS U1787 ( .A(n3987), .B(Add_result[9]), .S0(n3986), .Y(n297) );
AND2X4TS U1788 ( .A(n3427), .B(n3426), .Y(n3432) );
NAND2X1TS U1789 ( .A(n3860), .B(n3636), .Y(n376) );
NAND2X6TS U1790 ( .A(n1274), .B(n2124), .Y(n2148) );
INVX6TS U1791 ( .A(n2177), .Y(n1009) );
NAND2X6TS U1792 ( .A(n880), .B(n2589), .Y(n2514) );
NAND2X6TS U1793 ( .A(n1441), .B(n1439), .Y(n1711) );
INVX4TS U1794 ( .A(n2636), .Y(n2436) );
MX2X2TS U1795 ( .A(n3664), .B(n4512), .S0(n825), .Y(n240) );
MX2X2TS U1796 ( .A(n3666), .B(n4511), .S0(n825), .Y(n239) );
NAND2X6TS U1797 ( .A(n1856), .B(FS_Module_state_reg[1]), .Y(n3799) );
NOR2X8TS U1798 ( .A(n3905), .B(n3655), .Y(n3904) );
NAND2X2TS U1799 ( .A(n3577), .B(n3578), .Y(n1059) );
BUFX8TS U1800 ( .A(n2789), .Y(n1543) );
MX2X4TS U1801 ( .A(n1325), .B(n1324), .S0(net286914), .Y(n1315) );
BUFX12TS U1802 ( .A(n3840), .Y(n3986) );
BUFX8TS U1803 ( .A(n3912), .Y(n4533) );
INVX4TS U1804 ( .A(n1607), .Y(n598) );
MX2X4TS U1805 ( .A(n1326), .B(n933), .S0(net286914), .Y(n1318) );
NOR2X2TS U1806 ( .A(n3651), .B(n3650), .Y(n3849) );
CLKMX2X2TS U1807 ( .A(Data_MX[27]), .B(Op_MX[27]), .S0(net286912), .Y(n371)
);
NAND2X4TS U1808 ( .A(net287455), .B(n3425), .Y(n3426) );
CLKMX2X2TS U1809 ( .A(Data_MX[28]), .B(Op_MX[28]), .S0(net286912), .Y(n372)
);
NAND2X1TS U1810 ( .A(n4585), .B(n4385), .Y(n375) );
NAND2X4TS U1811 ( .A(n2273), .B(n977), .Y(n979) );
NAND2X6TS U1812 ( .A(n2266), .B(n1155), .Y(n1528) );
NOR2X4TS U1813 ( .A(n2039), .B(n3830), .Y(n2102) );
BUFX8TS U1814 ( .A(n2882), .Y(n862) );
ADDFHX2TS U1815 ( .A(n3164), .B(n3163), .CI(n3162), .CO(n3180), .S(n3160) );
AND2X2TS U1816 ( .A(n1530), .B(n3635), .Y(n1757) );
INVX8TS U1817 ( .A(n2803), .Y(n1088) );
NOR2X2TS U1818 ( .A(n3995), .B(n4413), .Y(n3834) );
NAND2X6TS U1819 ( .A(n1362), .B(n2111), .Y(n1360) );
NAND2X6TS U1820 ( .A(n1445), .B(n2226), .Y(n2274) );
NAND3X6TS U1821 ( .A(n2226), .B(n1445), .C(n1447), .Y(n977) );
NAND2X4TS U1822 ( .A(n2192), .B(n2189), .Y(n1275) );
NAND2X4TS U1823 ( .A(n1357), .B(n1627), .Y(n964) );
NOR2X6TS U1824 ( .A(n3940), .B(n3815), .Y(n4011) );
XNOR2X2TS U1825 ( .A(n2206), .B(n2205), .Y(n2216) );
INVX1TS U1826 ( .A(n3848), .Y(n3652) );
INVX2TS U1827 ( .A(n2516), .Y(n2426) );
INVX2TS U1828 ( .A(n3473), .Y(n1136) );
INVX12TS U1829 ( .A(n497), .Y(n3071) );
NAND2X6TS U1830 ( .A(n1279), .B(n1278), .Y(n2192) );
INVX12TS U1831 ( .A(n1656), .Y(n3069) );
NAND2X4TS U1832 ( .A(n1333), .B(n2275), .Y(n2276) );
INVX12TS U1833 ( .A(n1749), .Y(n2678) );
INVX12TS U1834 ( .A(n1470), .Y(n735) );
BUFX8TS U1835 ( .A(net291929), .Y(net292376) );
NOR3X1TS U1836 ( .A(n4488), .B(FS_Module_state_reg[2]), .C(n3843), .Y(n3844)
);
NAND2X4TS U1837 ( .A(n2416), .B(n2415), .Y(n2535) );
NOR2X1TS U1838 ( .A(n3966), .B(n3965), .Y(n3967) );
AND2X2TS U1839 ( .A(n3074), .B(n3080), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N1)
);
BUFX8TS U1840 ( .A(n3068), .Y(n474) );
NAND2X4TS U1841 ( .A(n2661), .B(DP_OP_158J21_127_356_n609), .Y(n1258) );
NAND2X4TS U1842 ( .A(n554), .B(n805), .Y(n544) );
NOR2X4TS U1843 ( .A(n1119), .B(n2909), .Y(n3569) );
NAND2X6TS U1844 ( .A(n1995), .B(n1996), .Y(n2017) );
BUFX12TS U1845 ( .A(n2319), .Y(n3070) );
NOR2X6TS U1846 ( .A(n1467), .B(n1466), .Y(n1022) );
NAND2X4TS U1847 ( .A(n4587), .B(n3862), .Y(n3655) );
CLKMX2X2TS U1848 ( .A(round_mode[1]), .B(round_mode[0]), .S0(n3861), .Y(
n3650) );
INVX2TS U1849 ( .A(n1640), .Y(n540) );
NOR2X4TS U1850 ( .A(n281), .B(Exp_module_Overflow_flag_A), .Y(n3862) );
AOI21X2TS U1851 ( .A0(n2424), .A1(n4047), .B0(n4048), .Y(n2414) );
INVX6TS U1852 ( .A(net288834), .Y(net288781) );
NOR2X2TS U1853 ( .A(n3247), .B(n3246), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N0)
);
INVX8TS U1854 ( .A(net288831), .Y(net287496) );
INVX4TS U1855 ( .A(n3656), .Y(n3687) );
INVX2TS U1856 ( .A(n2393), .Y(n774) );
NAND2X2TS U1857 ( .A(n3988), .B(n3991), .Y(n3832) );
INVX2TS U1858 ( .A(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N0),
.Y(n3574) );
NAND2X2TS U1859 ( .A(Sgf_normalized_result[12]), .B(n3954), .Y(n3965) );
NAND2BX2TS U1860 ( .AN(n1314), .B(DP_OP_158J21_127_356_n699), .Y(n1313) );
INVX2TS U1861 ( .A(n1549), .Y(n1548) );
INVX1TS U1862 ( .A(n1330), .Y(n1328) );
NAND2X6TS U1863 ( .A(n594), .B(DP_OP_158J21_127_356_n690), .Y(n612) );
INVX2TS U1864 ( .A(n1538), .Y(n1537) );
ADDFHX2TS U1865 ( .A(mult_x_59_n49), .B(mult_x_59_n64), .CI(n3556), .CO(
mult_x_59_n19), .S(mult_x_59_n20) );
NOR2X4TS U1866 ( .A(n1337), .B(DP_OP_158J21_127_356_n314), .Y(n1336) );
NOR2X2TS U1867 ( .A(n3809), .B(n3947), .Y(n3810) );
NAND2X4TS U1868 ( .A(n421), .B(n822), .Y(n655) );
INVX2TS U1869 ( .A(n3978), .Y(n3979) );
INVX2TS U1870 ( .A(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N0),
.Y(n3434) );
CLKBUFX3TS U1871 ( .A(n4445), .Y(n450) );
AND2X2TS U1872 ( .A(n1053), .B(mult_x_56_n51), .Y(mult_x_56_n52) );
INVX6TS U1873 ( .A(DP_OP_153J21_122_3500_n169), .Y(n1287) );
INVX8TS U1874 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[1]),
.Y(n1980) );
NOR2X4TS U1875 ( .A(n799), .B(n4328), .Y(n656) );
INVX2TS U1876 ( .A(n827), .Y(n529) );
NAND2X6TS U1877 ( .A(DP_OP_154J21_123_2814_n122), .B(
DP_OP_154J21_123_2814_n123), .Y(n1928) );
NAND2X6TS U1878 ( .A(DP_OP_158J21_127_356_n614), .B(
DP_OP_158J21_127_356_n617), .Y(n2660) );
NOR2X4TS U1879 ( .A(DP_OP_158J21_127_356_n1046), .B(
DP_OP_158J21_127_356_n1035), .Y(n2648) );
INVX2TS U1880 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[8]),
.Y(n1709) );
AND2X2TS U1881 ( .A(mult_x_59_b_4_), .B(mult_x_59_a_4_), .Y(mult_x_59_n53)
);
AND2X4TS U1882 ( .A(DP_OP_158J21_127_356_n690), .B(n4110), .Y(n1693) );
NAND3X4TS U1883 ( .A(n4458), .B(n4457), .C(n4456), .Y(n3961) );
INVX4TS U1884 ( .A(n1071), .Y(n955) );
AND2X2TS U1885 ( .A(mult_x_59_b_0_), .B(mult_x_59_a_0_), .Y(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N0)
);
NAND2X6TS U1886 ( .A(DP_OP_154J21_123_2814_n97), .B(
DP_OP_154J21_123_2814_n94), .Y(n1021) );
INVX2TS U1887 ( .A(n4409), .Y(n3890) );
AND2X2TS U1888 ( .A(mult_x_56_n50), .B(mult_x_56_n75), .Y(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N0) );
AND2X2TS U1889 ( .A(mult_x_57_b_4_), .B(mult_x_57_a_4_), .Y(mult_x_57_n53)
);
CLKMX2X4TS U1890 ( .A(n4449), .B(n4448), .S0(n824), .Y(n274) );
AND2X2TS U1891 ( .A(mult_x_57_b_3_), .B(mult_x_57_a_4_), .Y(n840) );
CLKMX2X4TS U1892 ( .A(n4453), .B(n4452), .S0(n824), .Y(n275) );
AND2X2TS U1893 ( .A(mult_x_58_b_0_), .B(mult_x_58_a_0_), .Y(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N0)
);
NAND3X4TS U1894 ( .A(n4467), .B(n4466), .C(n4465), .Y(n4006) );
CLKMX2X4TS U1895 ( .A(n4451), .B(n4450), .S0(n824), .Y(n276) );
NAND3X4TS U1896 ( .A(n4476), .B(n4475), .C(n4474), .Y(n4001) );
NAND3X4TS U1897 ( .A(n4470), .B(n4469), .C(n4468), .Y(n3991) );
MX2X2TS U1898 ( .A(n4461), .B(n4460), .S0(n4459), .Y(n307) );
NOR2X2TS U1899 ( .A(Sgf_normalized_result[1]), .B(Sgf_normalized_result[0]),
.Y(n3933) );
NAND2X2TS U1900 ( .A(Sgf_normalized_result[6]), .B(Sgf_normalized_result[7]),
.Y(n3809) );
NAND2X2TS U1901 ( .A(Sgf_normalized_result[8]), .B(Sgf_normalized_result[9]),
.Y(n3978) );
INVX8TS U1902 ( .A(Sgf_operation_EVEN1_result_B_adder[4]), .Y(n3178) );
NAND2X4TS U1903 ( .A(DP_OP_158J21_127_356_n894), .B(
DP_OP_158J21_127_356_n931), .Y(n1595) );
INVX6TS U1904 ( .A(DP_OP_153J21_122_3500_n127), .Y(n1309) );
CLKBUFX2TS U1905 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[6]),
.Y(n2858) );
NAND2X4TS U1906 ( .A(DP_OP_158J21_127_356_n647), .B(
DP_OP_158J21_127_356_n1050), .Y(n2336) );
NAND2X6TS U1907 ( .A(DP_OP_158J21_127_356_n652), .B(
DP_OP_158J21_127_356_n653), .Y(n2346) );
NAND2X8TS U1908 ( .A(net292172), .B(n410), .Y(net292173) );
NAND2X8TS U1909 ( .A(n451), .B(n2506), .Y(n639) );
NAND2X8TS U1910 ( .A(n2507), .B(n638), .Y(n451) );
NAND2X2TS U1911 ( .A(n2485), .B(n2486), .Y(n453) );
OAI21X4TS U1912 ( .A0(n2485), .A1(n2486), .B0(n2484), .Y(n454) );
XOR2X4TS U1913 ( .A(n455), .B(n2484), .Y(n2490) );
XOR2X4TS U1914 ( .A(n2485), .B(n2486), .Y(n455) );
XOR2X4TS U1915 ( .A(net292333), .B(net292173), .Y(net290421) );
NOR2X8TS U1916 ( .A(net288684), .B(net288595), .Y(n465) );
NAND2X8TS U1917 ( .A(n2355), .B(DP_OP_158J21_127_356_n411), .Y(n2324) );
CLKINVX12TS U1918 ( .A(DP_OP_158J21_127_356_n399), .Y(n2355) );
NAND3X6TS U1919 ( .A(n1634), .B(n445), .C(n1215), .Y(n1793) );
XOR2X4TS U1920 ( .A(n509), .B(n456), .Y(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N10) );
NAND2X8TS U1921 ( .A(net288756), .B(net288757), .Y(n475) );
OAI21X4TS U1922 ( .A0(n3046), .A1(n1748), .B0(n3047), .Y(n459) );
XNOR2X4TS U1923 ( .A(n1259), .B(n1258), .Y(n1655) );
NAND2X8TS U1924 ( .A(net288684), .B(n475), .Y(n463) );
NOR2X8TS U1925 ( .A(net288756), .B(net288757), .Y(net288684) );
NAND2X8TS U1926 ( .A(n463), .B(n462), .Y(net292370) );
NAND2X8TS U1927 ( .A(n475), .B(net291630), .Y(n462) );
NAND2X8TS U1928 ( .A(net288758), .B(net288759), .Y(net291630) );
NAND2X4TS U1929 ( .A(n464), .B(net290615), .Y(n510) );
OAI2BB1X4TS U1930 ( .A0N(net287249), .A1N(n464), .B0(net288235), .Y(
net288221) );
OAI2BB1X4TS U1931 ( .A0N(net290399), .A1N(n464), .B0(net290401), .Y(
net291323) );
NAND2X8TS U1932 ( .A(net292370), .B(net292367), .Y(n464) );
NAND2X8TS U1933 ( .A(n465), .B(n641), .Y(net292367) );
OAI2BB1X4TS U1934 ( .A0N(n435), .A1N(n466), .B0(n3794), .Y(n3796) );
BUFX6TS U1935 ( .A(n2446), .Y(n467) );
INVX8TS U1936 ( .A(net287972), .Y(n514) );
NOR4X2TS U1937 ( .A(n235), .B(n233), .C(n234), .D(n232), .Y(n3645) );
NAND3X2TS U1938 ( .A(n3849), .B(n3652), .C(n4488), .Y(n3653) );
OAI22X2TS U1939 ( .A0(n3649), .A1(n3648), .B0(round_mode[0]), .B1(
round_mode[1]), .Y(n3651) );
OAI21X4TS U1940 ( .A0(n2524), .A1(n1523), .B0(n1547), .Y(n1393) );
NAND2X8TS U1941 ( .A(n468), .B(n853), .Y(n855) );
OAI2BB1X4TS U1942 ( .A0N(n2522), .A1N(n471), .B0(n469), .Y(n4138) );
OAI21X4TS U1943 ( .A0(n471), .A1(n2522), .B0(net288689), .Y(n469) );
XOR2X4TS U1944 ( .A(n471), .B(n470), .Y(n4139) );
XOR2X4TS U1945 ( .A(n651), .B(n650), .Y(n471) );
NAND2X8TS U1946 ( .A(n1001), .B(n1460), .Y(n1794) );
NOR2X8TS U1947 ( .A(n1931), .B(DP_OP_154J21_123_2814_n119), .Y(n2007) );
XOR2X4TS U1948 ( .A(n472), .B(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[10]), .Y(n1146) );
OAI2BB1X4TS U1949 ( .A0N(n2518), .A1N(n1437), .B0(n1145), .Y(n472) );
NAND2X8TS U1950 ( .A(n557), .B(n1022), .Y(n556) );
XOR2X4TS U1951 ( .A(net288824), .B(n473), .Y(net288812) );
XOR2X4TS U1952 ( .A(net291949), .B(net291953), .Y(n473) );
NOR2X6TS U1953 ( .A(net288778), .B(net288229), .Y(net288821) );
NAND2X8TS U1954 ( .A(n1933), .B(n717), .Y(n981) );
INVX16TS U1955 ( .A(n1794), .Y(n2548) );
OR2X8TS U1956 ( .A(n2936), .B(n2935), .Y(n3576) );
BUFX20TS U1957 ( .A(n721), .Y(n720) );
XOR2X2TS U1958 ( .A(n2505), .B(n620), .Y(n2502) );
OAI2BB1X4TS U1959 ( .A0N(n435), .A1N(n476), .B0(n3777), .Y(n3782) );
XOR2X4TS U1960 ( .A(n2923), .B(n716), .Y(n479) );
OAI22X4TS U1961 ( .A0(n2948), .A1(n2908), .B0(n3567), .B1(n1668), .Y(n716)
);
XOR2X4TS U1962 ( .A(n2922), .B(n479), .Y(n2915) );
XNOR2X4TS U1963 ( .A(n1303), .B(n1302), .Y(n482) );
OAI22X4TS U1964 ( .A0(n1307), .A1(n2960), .B0(n2946), .B1(n481), .Y(n2893)
);
OAI22X4TS U1965 ( .A0(n721), .A1(n2946), .B0(n481), .B1(n2960), .Y(n2880) );
XOR2X4TS U1966 ( .A(n3000), .B(n1070), .Y(n1798) );
AND2X8TS U1967 ( .A(n1352), .B(n1435), .Y(n1070) );
NAND2X8TS U1968 ( .A(n1536), .B(n3576), .Y(n1352) );
NAND2X8TS U1969 ( .A(n2938), .B(n2937), .Y(n607) );
NOR2X6TS U1970 ( .A(n2938), .B(n2937), .Y(n485) );
NOR2X2TS U1971 ( .A(n486), .B(n2260), .Y(n2262) );
NAND2X1TS U1972 ( .A(n486), .B(n1799), .Y(n2558) );
NOR2X8TS U1973 ( .A(n1727), .B(n2256), .Y(n486) );
NAND2X8TS U1974 ( .A(n488), .B(n487), .Y(n1904) );
CLKINVX12TS U1975 ( .A(DP_OP_154J21_123_2814_n124), .Y(n487) );
CLKINVX12TS U1976 ( .A(DP_OP_154J21_123_2814_n125), .Y(n488) );
NAND3X8TS U1977 ( .A(n493), .B(n1605), .C(n489), .Y(n1925) );
NAND2X8TS U1978 ( .A(n1688), .B(n1679), .Y(n489) );
NAND3X8TS U1979 ( .A(n492), .B(n491), .C(n490), .Y(n1605) );
NAND3X8TS U1980 ( .A(n1551), .B(n1602), .C(n1680), .Y(n491) );
AOI21X4TS U1981 ( .A0(n1792), .A1(n1679), .B0(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[1]), .Y(n493) );
NAND2X8TS U1982 ( .A(n494), .B(n1928), .Y(n1792) );
OAI21X4TS U1983 ( .A0(n597), .A1(n1374), .B0(n2985), .Y(n1733) );
NAND2X4TS U1984 ( .A(n1044), .B(n2973), .Y(n2985) );
NOR2X8TS U1985 ( .A(n2973), .B(n2974), .Y(n1374) );
NAND2X6TS U1986 ( .A(n2972), .B(n2971), .Y(n597) );
OAI22X4TS U1987 ( .A0(n1307), .A1(n2947), .B0(n481), .B1(n2899), .Y(n2919)
);
OAI22X4TS U1988 ( .A0(n721), .A1(Op_MX[17]), .B0(n481), .B1(n1852), .Y(n2958) );
OAI22X4TS U1989 ( .A0(n720), .A1(n2909), .B0(n2948), .B1(n2902), .Y(n2925)
);
NOR2X4TS U1990 ( .A(n1621), .B(n495), .Y(n1432) );
NOR2X8TS U1991 ( .A(n2632), .B(n2631), .Y(n495) );
OR2X8TS U1992 ( .A(n1214), .B(n405), .Y(n1728) );
XOR2X4TS U1993 ( .A(n1602), .B(n758), .Y(n1214) );
XOR2X4TS U1994 ( .A(n2356), .B(n882), .Y(n497) );
AOI21X4TS U1995 ( .A0(n882), .A1(n2658), .B0(n4120), .Y(n2656) );
OAI21X4TS U1996 ( .A0(n1574), .A1(n502), .B0(n501), .Y(n1579) );
NAND2X8TS U1997 ( .A(n1509), .B(n2548), .Y(n1612) );
NAND2X8TS U1998 ( .A(n2548), .B(n1267), .Y(n595) );
NAND2X8TS U1999 ( .A(n617), .B(n616), .Y(n3620) );
CLKINVX6TS U2000 ( .A(n3614), .Y(add_x_19_n68) );
NAND3X8TS U2001 ( .A(n707), .B(n703), .C(n705), .Y(n3614) );
XOR2X4TS U2002 ( .A(n1524), .B(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[8]), .Y(n866) );
NAND3X8TS U2003 ( .A(n1793), .B(n1795), .C(n2588), .Y(n1524) );
NOR2X8TS U2004 ( .A(n1934), .B(n1935), .Y(n504) );
OAI22X4TS U2005 ( .A0(n2659), .A1(n884), .B0(n441), .B1(n474), .Y(n2702) );
NOR2X8TS U2006 ( .A(n1645), .B(n1835), .Y(n1644) );
NAND2X8TS U2007 ( .A(n1648), .B(n1644), .Y(n1643) );
INVX4TS U2008 ( .A(n3214), .Y(n3215) );
NOR2X8TS U2009 ( .A(DP_OP_159J21_128_5719_n259), .B(n858), .Y(n642) );
BUFX6TS U2010 ( .A(n1756), .Y(n505) );
NAND3X8TS U2011 ( .A(n508), .B(n506), .C(n3375), .Y(n1756) );
NAND2X6TS U2012 ( .A(n507), .B(n624), .Y(n506) );
NAND3X8TS U2013 ( .A(n3374), .B(n624), .C(n1584), .Y(n508) );
OR2X8TS U2014 ( .A(n2695), .B(n2694), .Y(n1584) );
OR2X8TS U2015 ( .A(n2697), .B(n2696), .Y(n624) );
NAND2X4TS U2016 ( .A(n2693), .B(n2692), .Y(n3335) );
AOI21X4TS U2017 ( .A0(n882), .A1(DP_OP_158J21_127_356_n692), .B0(
DP_OP_158J21_127_356_n693), .Y(n2653) );
OAI22X4TS U2018 ( .A0(n2684), .A1(n474), .B0(n2677), .B1(n884), .Y(n2681) );
XOR2X4TS U2019 ( .A(n1023), .B(n2678), .Y(n2684) );
XOR2X4TS U2020 ( .A(n1023), .B(n2721), .Y(n511) );
OAI22X4TS U2021 ( .A0(n2683), .A1(n884), .B0(n512), .B1(n474), .Y(n2688) );
XOR2X4TS U2022 ( .A(n2731), .B(n441), .Y(n512) );
NAND2X8TS U2023 ( .A(n513), .B(net287971), .Y(net291330) );
NAND2X8TS U2024 ( .A(n438), .B(n514), .Y(n513) );
NAND2X1TS U2025 ( .A(n2718), .B(n520), .Y(n515) );
INVX2TS U2026 ( .A(n520), .Y(n517) );
INVX2TS U2027 ( .A(n2718), .Y(n518) );
XOR2X4TS U2028 ( .A(n2717), .B(n519), .Y(n2724) );
NOR2X4TS U2029 ( .A(n1023), .B(n436), .Y(n520) );
XNOR2X4TS U2030 ( .A(n522), .B(n1304), .Y(n521) );
OAI21X4TS U2031 ( .A0(net288841), .A1(net288847), .B0(net288845), .Y(n522)
);
NAND2X2TS U2032 ( .A(n523), .B(n798), .Y(n2463) );
NOR2X8TS U2033 ( .A(n523), .B(n798), .Y(n2462) );
XOR2X4TS U2034 ( .A(n1880), .B(n1879), .Y(n523) );
NOR2X8TS U2035 ( .A(n4344), .B(n4343), .Y(n1871) );
XOR2X4TS U2036 ( .A(n524), .B(n4350), .Y(n1827) );
NAND2X4TS U2037 ( .A(n547), .B(n1426), .Y(n525) );
XOR2X4TS U2038 ( .A(n531), .B(n416), .Y(n530) );
INVX16TS U2039 ( .A(n533), .Y(n542) );
AND2X8TS U2040 ( .A(n543), .B(n544), .Y(n533) );
NAND2X8TS U2041 ( .A(n2645), .B(n810), .Y(n762) );
NAND3BX4TS U2042 ( .AN(n448), .B(n810), .C(n422), .Y(n536) );
NAND2X8TS U2043 ( .A(n906), .B(n873), .Y(n1641) );
AND3X8TS U2044 ( .A(n538), .B(n537), .C(n536), .Y(n1459) );
NAND2X4TS U2045 ( .A(n547), .B(n539), .Y(n538) );
NAND2X8TS U2046 ( .A(n542), .B(n803), .Y(n541) );
AOI21X4TS U2047 ( .A0(n4332), .A1(n796), .B0(n4333), .Y(n543) );
NAND2BX4TS U2048 ( .AN(n3784), .B(n545), .Y(n1636) );
OAI21X4TS U2049 ( .A0(n548), .A1(n547), .B0(n3785), .Y(n545) );
BUFX20TS U2050 ( .A(n1454), .Y(n547) );
NAND2X8TS U2051 ( .A(n1455), .B(n1456), .Y(n1454) );
NOR2X2TS U2052 ( .A(n550), .B(n3044), .Y(DP_OP_156J21_125_3370_n65) );
XOR2X4TS U2053 ( .A(n3035), .B(n1609), .Y(n550) );
NAND2X4TS U2054 ( .A(n550), .B(n3044), .Y(DP_OP_156J21_125_3370_n66) );
INVX6TS U2055 ( .A(n1306), .Y(n551) );
AND2X8TS U2056 ( .A(n553), .B(n552), .Y(n1306) );
NAND2X4TS U2057 ( .A(n759), .B(n1744), .Y(n552) );
OAI21X4TS U2058 ( .A0(n759), .A1(n1744), .B0(n3011), .Y(n553) );
INVX12TS U2059 ( .A(n542), .Y(n1453) );
NOR2X8TS U2060 ( .A(n555), .B(n4330), .Y(n554) );
INVX8TS U2061 ( .A(n556), .Y(n560) );
NAND2X8TS U2062 ( .A(n1930), .B(n1468), .Y(n557) );
INVX16TS U2063 ( .A(n751), .Y(n1602) );
NAND2X8TS U2064 ( .A(n560), .B(n559), .Y(n562) );
NAND3X8TS U2065 ( .A(n1602), .B(n1551), .C(n1468), .Y(n559) );
INVX12TS U2066 ( .A(n733), .Y(n1551) );
NAND2X8TS U2067 ( .A(n1434), .B(n1909), .Y(n1930) );
NAND3X8TS U2068 ( .A(n432), .B(n1717), .C(n1755), .Y(n1622) );
XOR2X4TS U2069 ( .A(n561), .B(n1032), .Y(n663) );
NAND2X8TS U2070 ( .A(n563), .B(n2008), .Y(n719) );
NAND2X4TS U2071 ( .A(n1934), .B(n1935), .Y(n2008) );
NAND2X8TS U2072 ( .A(n1067), .B(n717), .Y(n563) );
NAND3X8TS U2073 ( .A(n1493), .B(n1492), .C(n564), .Y(n1462) );
NAND2X8TS U2074 ( .A(n1489), .B(n867), .Y(n1018) );
INVX12TS U2075 ( .A(n1576), .Y(n1489) );
NAND2X8TS U2076 ( .A(n565), .B(n558), .Y(n1493) );
NAND2X8TS U2077 ( .A(n566), .B(n1537), .Y(n251) );
XOR2X4TS U2078 ( .A(n568), .B(n2999), .Y(n567) );
NOR2X8TS U2079 ( .A(n869), .B(n1267), .Y(n569) );
NAND2X8TS U2080 ( .A(n752), .B(n2626), .Y(n570) );
NAND3X8TS U2081 ( .A(n753), .B(n756), .C(n755), .Y(n752) );
OAI21X4TS U2082 ( .A0(DP_OP_157J21_126_5719_n254), .A1(n1295), .B0(
DP_OP_157J21_126_5719_n255), .Y(n1303) );
XOR2X4TS U2083 ( .A(n1667), .B(n571), .Y(n1666) );
INVX12TS U2084 ( .A(n571), .Y(n1407) );
NAND2X8TS U2085 ( .A(n1369), .B(n572), .Y(n571) );
NAND2X8TS U2086 ( .A(n575), .B(n574), .Y(n581) );
OR2X8TS U2087 ( .A(net287909), .B(net287496), .Y(n574) );
NAND2X8TS U2088 ( .A(n583), .B(n582), .Y(n575) );
XOR2X4TS U2089 ( .A(n576), .B(n2472), .Y(n2496) );
XOR2X4TS U2090 ( .A(n581), .B(net288809), .Y(n576) );
OAI2BB1X4TS U2091 ( .A0N(n2472), .A1N(n580), .B0(n579), .Y(net288817) );
NAND2X2TS U2092 ( .A(net288809), .B(n581), .Y(n579) );
OAI21X4TS U2093 ( .A0(n2880), .A1(n778), .B0(n584), .Y(n776) );
XOR2X4TS U2094 ( .A(n777), .B(n1078), .Y(n2890) );
CLKINVX12TS U2095 ( .A(n1062), .Y(n1414) );
NOR2X8TS U2096 ( .A(n585), .B(DP_OP_157J21_126_5719_n246), .Y(n2871) );
NOR2X8TS U2097 ( .A(DP_OP_157J21_126_5719_n254), .B(n954), .Y(n585) );
XOR2X4TS U2098 ( .A(n586), .B(Op_MY[17]), .Y(n1382) );
OAI21X4TS U2099 ( .A0(n2871), .A1(n1414), .B0(n2870), .Y(n586) );
NOR2X8TS U2100 ( .A(n3444), .B(n1374), .Y(n3438) );
XNOR2X4TS U2101 ( .A(n587), .B(n1552), .Y(n4137) );
XOR2X4TS U2102 ( .A(net288592), .B(n641), .Y(n587) );
XNOR2X4TS U2103 ( .A(n2649), .B(n2650), .Y(n588) );
XNOR2X4TS U2104 ( .A(n2656), .B(DP_OP_158J21_127_356_n859), .Y(n589) );
XOR2X4TS U2105 ( .A(n590), .B(n1075), .Y(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N12)
);
OAI21X4TS U2106 ( .A0(n1735), .A1(n592), .B0(n591), .Y(n590) );
AOI21X4TS U2107 ( .A0(n1733), .A1(n2984), .B0(n2977), .Y(n591) );
NAND2X8TS U2108 ( .A(n1134), .B(n1370), .Y(n1735) );
NAND2X8TS U2109 ( .A(n629), .B(n628), .Y(n1134) );
OR2X8TS U2110 ( .A(n4117), .B(DP_OP_158J21_127_356_n685), .Y(n594) );
AND2X8TS U2111 ( .A(n4121), .B(DP_OP_158J21_127_356_n681), .Y(n1754) );
NAND2X8TS U2112 ( .A(n443), .B(n595), .Y(n1035) );
NAND2X2TS U2113 ( .A(n1704), .B(n596), .Y(n1736) );
OAI21X4TS U2114 ( .A0(n860), .A1(n3444), .B0(n596), .Y(n1152) );
NAND4X8TS U2115 ( .A(n1496), .B(n1494), .C(n1497), .D(n1495), .Y(n1001) );
OR2X8TS U2116 ( .A(n599), .B(n598), .Y(n1497) );
NAND3X8TS U2117 ( .A(n600), .B(n599), .C(n603), .Y(n1495) );
NAND2X8TS U2118 ( .A(n602), .B(n1607), .Y(n1496) );
NAND2X8TS U2119 ( .A(n428), .B(n558), .Y(n603) );
INVX2TS U2120 ( .A(n605), .Y(n3562) );
OAI22X4TS U2121 ( .A0(n1054), .A1(n3567), .B0(n1119), .B1(n2908), .Y(n606)
);
OAI21X4TS U2122 ( .A0(n1070), .A1(n1681), .B0(n484), .Y(n3447) );
INVX12TS U2123 ( .A(n2720), .Y(n2719) );
NAND3X8TS U2124 ( .A(n608), .B(n593), .C(n611), .Y(n2720) );
NAND3X6TS U2125 ( .A(n610), .B(n1159), .C(n609), .Y(n608) );
XOR2X4TS U2126 ( .A(n613), .B(n2395), .Y(n2401) );
OAI21X4TS U2127 ( .A0(n737), .A1(n615), .B0(n614), .Y(n613) );
AOI21X4TS U2128 ( .A0(n1577), .A1(n719), .B0(n750), .Y(n614) );
XOR2X4TS U2129 ( .A(n3620), .B(n1578), .Y(n2603) );
OAI2BB1X4TS U2130 ( .A0N(n1726), .A1N(n1579), .B0(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[9]), .Y(n617) );
XOR2X4TS U2131 ( .A(n619), .B(n618), .Y(net291929) );
OAI21X4TS U2132 ( .A0(DP_OP_159J21_128_5719_n255), .A1(n839), .B0(
DP_OP_159J21_128_5719_n256), .Y(n618) );
INVX6TS U2133 ( .A(net292709), .Y(n839) );
AND2X8TS U2134 ( .A(n2505), .B(n620), .Y(n2820) );
OAI22X4TS U2135 ( .A0(net291956), .A1(net288229), .B0(net292372), .B1(
net287910), .Y(n620) );
NOR2X8TS U2136 ( .A(net287973), .B(net287972), .Y(net287249) );
NOR2X8TS U2137 ( .A(net288236), .B(net288237), .Y(net287972) );
NAND2X8TS U2138 ( .A(n1352), .B(n1435), .Y(n623) );
NAND2XLTS U2139 ( .A(n3375), .B(n624), .Y(n3376) );
NAND2X8TS U2140 ( .A(n1134), .B(n1370), .Y(n860) );
NOR2X4TS U2141 ( .A(n2940), .B(n2939), .Y(n3445) );
NOR2X8TS U2142 ( .A(n627), .B(n626), .Y(n628) );
OAI2BB1X4TS U2143 ( .A0N(net288788), .A1N(n2483), .B0(n630), .Y(n2499) );
OAI21X4TS U2144 ( .A0(n2483), .A1(net288788), .B0(n632), .Y(n630) );
XOR2X4TS U2145 ( .A(n631), .B(n2483), .Y(n2491) );
OAI22X4TS U2146 ( .A0(net291956), .A1(n2488), .B0(net291396), .B1(n2477),
.Y(n632) );
XOR2X4TS U2147 ( .A(n2653), .B(n1693), .Y(n1023) );
INVX12TS U2148 ( .A(n633), .Y(n1812) );
AOI2BB1X4TS U2149 ( .A0N(n635), .A1N(net288230), .B0(n634), .Y(n633) );
NAND2X8TS U2150 ( .A(n637), .B(n636), .Y(net291299) );
NOR2X8TS U2151 ( .A(n1769), .B(n1815), .Y(n636) );
NAND2X8TS U2152 ( .A(net291361), .B(n853), .Y(n637) );
NAND2X4TS U2153 ( .A(n2494), .B(n2493), .Y(n2506) );
NAND2X8TS U2154 ( .A(n1206), .B(n916), .Y(n1816) );
OR2X8TS U2155 ( .A(n2494), .B(n2493), .Y(n2507) );
NAND2X8TS U2156 ( .A(n433), .B(n639), .Y(n640) );
NAND2X8TS U2157 ( .A(n640), .B(n2521), .Y(n641) );
NAND2X8TS U2158 ( .A(n641), .B(net288594), .Y(net292172) );
NAND2X4TS U2159 ( .A(n2501), .B(n2500), .Y(n2521) );
XOR2X4TS U2160 ( .A(n642), .B(DP_OP_159J21_128_5719_n262), .Y(net292178) );
NOR2X8TS U2161 ( .A(net288758), .B(net288759), .Y(net288595) );
OAI2BB1X4TS U2162 ( .A0N(n2482), .A1N(n645), .B0(n643), .Y(n2498) );
XOR2X4TS U2163 ( .A(n2481), .B(n644), .Y(n2492) );
XOR2X4TS U2164 ( .A(n2482), .B(n645), .Y(n644) );
NAND2X8TS U2165 ( .A(n647), .B(n646), .Y(n645) );
OR2X8TS U2166 ( .A(net291956), .B(net288781), .Y(n646) );
NAND2X8TS U2167 ( .A(n649), .B(n648), .Y(n647) );
NAND2X8TS U2168 ( .A(n2521), .B(n433), .Y(n650) );
OAI21X4TS U2169 ( .A0(n799), .A1(n655), .B0(n781), .Y(n654) );
AOI21X4TS U2170 ( .A0(n249), .A1(n3932), .B0(n658), .Y(n657) );
INVX2TS U2171 ( .A(n4407), .Y(n659) );
OAI21X4TS U2172 ( .A0(n661), .A1(n830), .B0(n660), .Y(n249) );
XOR2X4TS U2173 ( .A(n2452), .B(n2451), .Y(n661) );
AOI21X4TS U2174 ( .A0(n2445), .A1(n870), .B0(n467), .Y(n2447) );
NOR2X8TS U2175 ( .A(n663), .B(n807), .Y(n2454) );
AOI2BB1X4TS U2176 ( .A0N(n3742), .A1N(n3737), .B0(n665), .Y(n664) );
OR2X8TS U2177 ( .A(n3698), .B(n3705), .Y(n667) );
NOR2X8TS U2178 ( .A(n3742), .B(n3729), .Y(n1885) );
NOR2X8TS U2179 ( .A(n1884), .B(n789), .Y(n3742) );
NOR2X1TS U2180 ( .A(n1837), .B(n3102), .Y(n3121) );
OAI21X2TS U2181 ( .A0(n3142), .A1(n3141), .B0(n3140), .Y(n668) );
XOR2X1TS U2182 ( .A(n3140), .B(n670), .Y(n669) );
INVX2TS U2183 ( .A(n3141), .Y(n670) );
NAND3X8TS U2184 ( .A(n673), .B(n3230), .C(n671), .Y(n677) );
NAND2X8TS U2185 ( .A(n676), .B(n678), .Y(n1480) );
NAND2X8TS U2186 ( .A(n675), .B(n679), .Y(n1481) );
OAI21X4TS U2187 ( .A0(n3240), .A1(n3237), .B0(n3238), .Y(n674) );
OAI21X2TS U2188 ( .A0(n3237), .A1(n3240), .B0(n3238), .Y(n3229) );
INVX2TS U2189 ( .A(n1480), .Y(n3233) );
NOR2X4TS U2190 ( .A(net288847), .B(n2469), .Y(net291361) );
NOR2BX4TS U2191 ( .AN(n763), .B(n680), .Y(n1876) );
NOR2X8TS U2192 ( .A(n4335), .B(n4336), .Y(n764) );
NOR2X8TS U2193 ( .A(n1871), .B(n804), .Y(n763) );
NOR2BX4TS U2194 ( .AN(n3101), .B(n681), .Y(n3163) );
XOR2X4TS U2195 ( .A(n3101), .B(n682), .Y(n3099) );
NOR2X8TS U2196 ( .A(n408), .B(n3177), .Y(n682) );
XOR2X4TS U2197 ( .A(n683), .B(n4355), .Y(n1759) );
NAND3X6TS U2198 ( .A(n686), .B(n685), .C(n684), .Y(n683) );
XOR2X4TS U2199 ( .A(n542), .B(n688), .Y(n1886) );
AND2X8TS U2200 ( .A(n803), .B(n819), .Y(n688) );
OAI2BB1X4TS U2201 ( .A0N(n695), .A1N(n694), .B0(n3182), .Y(n693) );
XOR2X4TS U2202 ( .A(n3182), .B(n696), .Y(n3194) );
XOR2X4TS U2203 ( .A(n3183), .B(n3184), .Y(n696) );
OAI21X4TS U2204 ( .A0(n2461), .A1(n3779), .B0(n697), .Y(n2465) );
NAND2X4TS U2205 ( .A(n423), .B(n870), .Y(n699) );
NAND2X4TS U2206 ( .A(n2553), .B(n700), .Y(DP_OP_156J21_125_3370_n73) );
NOR2X8TS U2207 ( .A(n2553), .B(n700), .Y(n3598) );
XOR2X4TS U2208 ( .A(n1517), .B(n3036), .Y(n700) );
NAND3X6TS U2209 ( .A(n706), .B(n1376), .C(n710), .Y(n705) );
NAND2X8TS U2210 ( .A(n1574), .B(n723), .Y(n710) );
AND2X8TS U2211 ( .A(n2550), .B(n1514), .Y(n706) );
NAND2X8TS U2212 ( .A(n704), .B(n708), .Y(n703) );
CLKINVX12TS U2213 ( .A(n706), .Y(n704) );
CLKINVX6TS U2214 ( .A(n710), .Y(n709) );
XOR2X4TS U2215 ( .A(n736), .B(n562), .Y(n1932) );
NAND2X8TS U2216 ( .A(n2922), .B(n711), .Y(n714) );
NAND2X8TS U2217 ( .A(n714), .B(n713), .Y(n2932) );
NAND2X8TS U2218 ( .A(n1931), .B(DP_OP_154J21_123_2814_n119), .Y(n718) );
XNOR2X4TS U2219 ( .A(n1296), .B(n2871), .Y(n1668) );
OR2X8TS U2220 ( .A(n1580), .B(n981), .Y(n737) );
NAND2X8TS U2221 ( .A(n2401), .B(n2396), .Y(n2549) );
NAND3X8TS U2222 ( .A(n722), .B(n728), .C(n725), .Y(n2552) );
AND2X8TS U2223 ( .A(n727), .B(n724), .Y(n722) );
AND2X8TS U2224 ( .A(n749), .B(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[13]), .Y(n726) );
NAND2X4TS U2225 ( .A(n729), .B(n859), .Y(n772) );
OAI21X4TS U2226 ( .A0(n1735), .A1(n730), .B0(n1734), .Y(n1541) );
NAND2X4TS U2227 ( .A(DP_OP_156J21_125_3370_n201), .B(
DP_OP_156J21_125_3370_n204), .Y(DP_OP_156J21_125_3370_n52) );
NAND2X8TS U2228 ( .A(n735), .B(n734), .Y(n733) );
INVX12TS U2229 ( .A(n2390), .Y(n1509) );
NAND2X8TS U2230 ( .A(n723), .B(n1514), .Y(n1635) );
OR2X8TS U2231 ( .A(n2401), .B(n2396), .Y(n1514) );
NOR2X8TS U2232 ( .A(n1929), .B(n1926), .Y(n1468) );
NOR2X8TS U2233 ( .A(DP_OP_154J21_123_2814_n123), .B(
DP_OP_154J21_123_2814_n122), .Y(n1926) );
NOR2X8TS U2234 ( .A(DP_OP_154J21_123_2814_n120), .B(
DP_OP_154J21_123_2814_n121), .Y(n1929) );
XOR2X4TS U2235 ( .A(n3579), .B(n1056), .Y(n4298) );
XOR2X4TS U2236 ( .A(n1073), .B(n1797), .Y(n4308) );
NAND3X8TS U2237 ( .A(n445), .B(n1035), .C(n2402), .Y(n738) );
NAND2X8TS U2238 ( .A(n1437), .B(n2402), .Y(n739) );
NAND2X8TS U2239 ( .A(n740), .B(n2551), .Y(n1437) );
NAND2X8TS U2240 ( .A(n1488), .B(n2552), .Y(n740) );
NAND4X8TS U2241 ( .A(n1634), .B(n445), .C(n1215), .D(n2402), .Y(n741) );
INVX2TS U2242 ( .A(n737), .Y(n748) );
NOR2X8TS U2243 ( .A(n1410), .B(n1411), .Y(n751) );
AND2X8TS U2244 ( .A(n967), .B(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[0]), .Y(n2556) );
NOR2X8TS U2245 ( .A(n2560), .B(n2557), .Y(n757) );
NAND2X8TS U2246 ( .A(n1214), .B(n405), .Y(n953) );
NOR2X8TS U2247 ( .A(n1205), .B(n1469), .Y(n758) );
OAI21X4TS U2248 ( .A0(n1146), .A1(n1079), .B0(n1147), .Y(n3012) );
NOR2X8TS U2249 ( .A(n1923), .B(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[9]), .Y(n2248) );
XNOR2X4TS U2250 ( .A(n761), .B(n760), .Y(n1923) );
INVX12TS U2251 ( .A(DP_OP_154J21_123_2814_n84), .Y(n1200) );
OAI21X4TS U2252 ( .A0(n1919), .A1(DP_OP_154J21_123_2814_n87), .B0(n1265),
.Y(n761) );
NAND2X8TS U2253 ( .A(DP_OP_154J21_123_2814_n130), .B(
DP_OP_154J21_123_2814_n131), .Y(n1265) );
NOR2X2TS U2254 ( .A(n762), .B(n811), .Y(n1898) );
NOR2X2TS U2255 ( .A(n762), .B(n791), .Y(n3784) );
NAND3X6TS U2256 ( .A(n766), .B(n782), .C(n542), .Y(n765) );
AOI2BB2X4TS U2257 ( .B0(n925), .B1(n767), .A0N(n1894), .A1N(n951), .Y(n770)
);
XOR2X4TS U2258 ( .A(n772), .B(n771), .Y(n1264) );
NAND2X2TS U2259 ( .A(n778), .B(n2880), .Y(n775) );
XNOR2X4TS U2260 ( .A(n778), .B(n2880), .Y(n777) );
NAND2X4TS U2261 ( .A(n862), .B(n1061), .Y(n779) );
NOR2X8TS U2262 ( .A(n1890), .B(n795), .Y(n2998) );
XOR2X2TS U2263 ( .A(n3582), .B(n1583), .Y(n1533) );
XNOR2X2TS U2264 ( .A(n1533), .B(n1532), .Y(n4293) );
NAND2X4TS U2265 ( .A(n2658), .B(n882), .Y(n1368) );
NAND3X4TS U2266 ( .A(n1622), .B(n1620), .C(n3032), .Y(n1623) );
OAI21X4TS U2267 ( .A0(n3443), .A1(n1732), .B0(n1805), .Y(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N13)
);
NOR2X4TS U2268 ( .A(n1633), .B(n3598), .Y(DP_OP_156J21_125_3370_n70) );
OR2X4TS U2269 ( .A(n448), .B(n787), .Y(n903) );
NAND2X2TS U2270 ( .A(n788), .B(n4377), .Y(n3660) );
NOR2X6TS U2271 ( .A(n788), .B(n4370), .Y(n3659) );
NOR2X4TS U2272 ( .A(n1886), .B(n790), .Y(n2453) );
NOR2X6TS U2273 ( .A(n1887), .B(n806), .Y(n2449) );
NOR2X4TS U2274 ( .A(n1637), .B(n808), .Y(n3788) );
NOR2BX2TS U2275 ( .AN(n810), .B(n812), .Y(n1640) );
NOR2BX1TS U2276 ( .AN(n810), .B(n811), .Y(n1649) );
NOR2X2TS U2277 ( .A(n1881), .B(n814), .Y(n3704) );
NAND2X2TS U2278 ( .A(n1881), .B(n814), .Y(n3705) );
OAI2BB1X2TS U2279 ( .A0N(n821), .A1N(n4074), .B0(n4100), .Y(n1747) );
CLKMX2X2TS U2280 ( .A(n4505), .B(n4504), .S0(n823), .Y(n234) );
CLKMX2X2TS U2281 ( .A(n3640), .B(n4507), .S0(n823), .Y(n237) );
CLKMX2X2TS U2282 ( .A(n3639), .B(n4506), .S0(n823), .Y(n233) );
MX2X4TS U2283 ( .A(n4455), .B(n4454), .S0(n824), .Y(n281) );
CLKMX2X2TS U2284 ( .A(n3638), .B(n4510), .S0(n825), .Y(n235) );
CLKMX2X2TS U2285 ( .A(n3641), .B(n4509), .S0(n825), .Y(n236) );
CLKMX2X2TS U2286 ( .A(n4502), .B(n4501), .S0(n825), .Y(n232) );
XOR2X2TS U2287 ( .A(n826), .B(n4363), .Y(n3638) );
NAND2X2TS U2288 ( .A(net290615), .B(net287974), .Y(net288736) );
OR2X8TS U2289 ( .A(n1135), .B(n889), .Y(n863) );
OAI22X4TS U2290 ( .A0(n2790), .A1(n1543), .B0(n2788), .B1(n1042), .Y(n2812)
);
NOR2X4TS U2291 ( .A(n2489), .B(net288777), .Y(n3410) );
XOR2X4TS U2292 ( .A(n3413), .B(n3426), .Y(n3429) );
OAI21X2TS U2293 ( .A0(n3441), .A1(n3440), .B0(n3439), .Y(n1806) );
NOR2X4TS U2294 ( .A(n3440), .B(n3437), .Y(n3442) );
OAI21X4TS U2295 ( .A0(n768), .A1(FSM_selector_C), .B0(n1526), .Y(n3798) );
XOR2X4TS U2296 ( .A(n1541), .B(n919), .Y(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N11)
);
INVX8TS U2297 ( .A(n1244), .Y(n2151) );
INVX6TS U2298 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[6]), .Y(
n1979) );
NAND2X2TS U2299 ( .A(net288832), .B(net288826), .Y(net292232) );
CLKINVX6TS U2300 ( .A(n962), .Y(n956) );
INVX2TS U2301 ( .A(n1590), .Y(n1589) );
NAND2X4TS U2302 ( .A(n2024), .B(n2023), .Y(n2529) );
INVX12TS U2303 ( .A(n1212), .Y(n1773) );
INVX2TS U2304 ( .A(n2174), .Y(n1031) );
NAND2X4TS U2305 ( .A(n864), .B(n2512), .Y(n1002) );
INVX8TS U2306 ( .A(n2385), .Y(n1254) );
INVX4TS U2307 ( .A(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[9]), .Y(
n2383) );
NAND2X6TS U2308 ( .A(n1413), .B(n2003), .Y(n2006) );
INVX4TS U2309 ( .A(n2625), .Y(n2004) );
INVX8TS U2310 ( .A(n1425), .Y(n2400) );
NAND2X6TS U2311 ( .A(n1539), .B(n1778), .Y(n3619) );
NAND2X2TS U2312 ( .A(n870), .B(n3754), .Y(n1030) );
NAND3X2TS U2313 ( .A(n435), .B(n3754), .C(n873), .Y(n1029) );
NAND2X4TS U2314 ( .A(n2226), .B(n2225), .Y(n2227) );
NAND2X4TS U2315 ( .A(net288858), .B(net288826), .Y(net292005) );
INVX2TS U2316 ( .A(n2328), .Y(n1225) );
INVX4TS U2317 ( .A(DP_OP_155J21_124_2814_n117), .Y(n1256) );
INVX2TS U2318 ( .A(n2314), .Y(n976) );
NAND3X4TS U2319 ( .A(n854), .B(net288845), .C(net288841), .Y(n856) );
NAND2X4TS U2320 ( .A(n2597), .B(n2526), .Y(n1232) );
NAND3X6TS U2321 ( .A(n888), .B(n1168), .C(n2027), .Y(n1076) );
INVX6TS U2322 ( .A(n1482), .Y(n1545) );
INVX2TS U2323 ( .A(n2379), .Y(n1558) );
NOR2X1TS U2324 ( .A(n876), .B(n408), .Y(n3166) );
NOR2X2TS U2325 ( .A(n2146), .B(n2143), .Y(n1284) );
NOR2X4TS U2326 ( .A(n2141), .B(n2140), .Y(n2171) );
INVX4TS U2327 ( .A(n2184), .Y(n2208) );
NAND2X2TS U2328 ( .A(n2027), .B(n1261), .Y(n1974) );
INVX2TS U2329 ( .A(n2028), .Y(n1261) );
NOR2X4TS U2330 ( .A(n2976), .B(n2975), .Y(n3437) );
INVX4TS U2331 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[5]), .Y(
n1522) );
INVX2TS U2332 ( .A(n3825), .Y(n3826) );
NAND2X2TS U2333 ( .A(n2072), .B(n913), .Y(n2078) );
INVX8TS U2334 ( .A(net288595), .Y(net288594) );
INVX12TS U2335 ( .A(n1142), .Y(n1119) );
NAND2X4TS U2336 ( .A(n3315), .B(n3323), .Y(n1319) );
NOR2X4TS U2337 ( .A(n1665), .B(n1117), .Y(n1664) );
INVX12TS U2338 ( .A(Sgf_operation_EVEN1_result_B_adder[1]), .Y(n3107) );
ADDFHX2TS U2339 ( .A(n2710), .B(n2709), .CI(n2708), .CO(n2739), .S(n2737) );
NOR2X2TS U2340 ( .A(FSM_selector_B_1_), .B(Op_MY[23]), .Y(n2037) );
INVX12TS U2341 ( .A(net291907), .Y(net291904) );
CLKINVX6TS U2342 ( .A(net286913), .Y(net291907) );
INVX2TS U2343 ( .A(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[11]),
.Y(n1201) );
NAND3X6TS U2344 ( .A(n1005), .B(n1004), .C(n1002), .Y(n1202) );
NAND2X4TS U2345 ( .A(net288223), .B(net288224), .Y(net287246) );
INVX2TS U2346 ( .A(Op_MY[14]), .Y(n1324) );
ADDFHX2TS U2347 ( .A(n3345), .B(n3344), .CI(n3343), .CO(n3354), .S(n3310) );
NOR2X4TS U2348 ( .A(n2385), .B(n2386), .Y(n1183) );
NAND3X4TS U2349 ( .A(n447), .B(n869), .C(n1509), .Y(n1421) );
CLKINVX6TS U2350 ( .A(n1437), .Y(n2588) );
NAND2X4TS U2351 ( .A(n1035), .B(n445), .Y(n1795) );
NAND2X4TS U2352 ( .A(n2552), .B(n2551), .Y(n1376) );
NAND2X6TS U2353 ( .A(n1143), .B(n1765), .Y(n1572) );
NAND3X6TS U2354 ( .A(n793), .B(n4483), .C(n4482), .Y(n3851) );
NAND2X4TS U2355 ( .A(n360), .B(n348), .Y(n3291) );
NOR2X4TS U2356 ( .A(n358), .B(n346), .Y(n3318) );
NAND2X6TS U2357 ( .A(n3635), .B(n1853), .Y(n2838) );
AOI22X1TS U2358 ( .A0(n3866), .A1(Add_result[12]), .B0(
Sgf_normalized_result[11]), .B1(n4533), .Y(n3768) );
AOI22X1TS U2359 ( .A0(n3913), .A1(Add_result[10]), .B0(
Sgf_normalized_result[9]), .B1(n3912), .Y(n3765) );
AOI2BB2X2TS U2360 ( .B0(n3927), .B1(n248), .A0N(n1127), .A1N(n4408), .Y(
n3764) );
NAND2X4TS U2361 ( .A(n3923), .B(n3915), .Y(n1832) );
INVX6TS U2362 ( .A(n1156), .Y(n2267) );
NOR2X4TS U2363 ( .A(n1958), .B(n1962), .Y(n1174) );
INVX2TS U2364 ( .A(DP_OP_153J21_122_3500_n167), .Y(n969) );
INVX6TS U2365 ( .A(n1983), .Y(n970) );
INVX2TS U2366 ( .A(n1447), .Y(n968) );
INVX6TS U2367 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[5]),
.Y(n1977) );
NOR2X2TS U2368 ( .A(n3178), .B(n3158), .Y(n3101) );
CLKINVX6TS U2369 ( .A(n1016), .Y(n1010) );
NAND3X4TS U2370 ( .A(n1959), .B(n1066), .C(n1617), .Y(n1616) );
INVX2TS U2371 ( .A(n1958), .Y(n1617) );
AND2X4TS U2372 ( .A(n1973), .B(n2152), .Y(n1790) );
CLKINVX3TS U2373 ( .A(n2325), .Y(n1138) );
NAND2X2TS U2374 ( .A(n955), .B(n1084), .Y(n954) );
NAND2X4TS U2375 ( .A(n1632), .B(n1973), .Y(n985) );
NAND2X2TS U2376 ( .A(n1210), .B(n889), .Y(n1208) );
OAI22X2TS U2377 ( .A0(net291956), .A1(net288798), .B0(net291396), .B1(
net288745), .Y(net288803) );
NOR2X2TS U2378 ( .A(n3108), .B(n3177), .Y(n3096) );
NAND2X4TS U2379 ( .A(n1221), .B(n1224), .Y(n1223) );
NOR2X2TS U2380 ( .A(n437), .B(n1225), .Y(n1224) );
INVX2TS U2381 ( .A(n4113), .Y(n1314) );
INVX8TS U2382 ( .A(n1774), .Y(n2768) );
NAND2X4TS U2383 ( .A(n4118), .B(n2330), .Y(n1775) );
NAND2X4TS U2384 ( .A(n2625), .B(n4544), .Y(n1413) );
INVX2TS U2385 ( .A(n2833), .Y(n1675) );
INVX4TS U2386 ( .A(n2272), .Y(n1555) );
INVX6TS U2387 ( .A(n2705), .Y(n2704) );
INVX2TS U2388 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[2]), .Y(
n1685) );
NAND2X2TS U2389 ( .A(n2011), .B(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[2]), .Y(n1682) );
NAND2X6TS U2390 ( .A(n2492), .B(n2491), .Y(n3418) );
NAND2X4TS U2391 ( .A(n991), .B(n1586), .Y(n988) );
NOR2X4TS U2392 ( .A(n2512), .B(n993), .Y(n992) );
NAND4X2TS U2393 ( .A(n2548), .B(n447), .C(n2549), .D(n1509), .Y(n2550) );
NAND2X2TS U2394 ( .A(n1670), .B(n2963), .Y(n1510) );
NOR2X4TS U2395 ( .A(n327), .B(n315), .Y(n3279) );
INVX2TS U2396 ( .A(n3786), .Y(n1426) );
NOR2X4TS U2397 ( .A(n1895), .B(n950), .Y(n949) );
NOR2X4TS U2398 ( .A(net290403), .B(net290404), .Y(net290401) );
OAI21X2TS U2399 ( .A0(net287971), .A1(net287250), .B0(net287246), .Y(
net290404) );
OAI21X2TS U2400 ( .A0(net287247), .A1(net287246), .B0(net287248), .Y(
net290442) );
INVX2TS U2401 ( .A(n3442), .Y(n1392) );
NAND3X4TS U2402 ( .A(n1253), .B(n2384), .C(n1255), .Y(n1252) );
NOR2X6TS U2403 ( .A(n1250), .B(n1249), .Y(n1248) );
NAND2X6TS U2404 ( .A(n1375), .B(n1553), .Y(n3034) );
INVX2TS U2405 ( .A(n2745), .Y(n1723) );
INVX2TS U2406 ( .A(n2722), .Y(n1367) );
NAND2X4TS U2407 ( .A(n1784), .B(n2990), .Y(n1781) );
INVX4TS U2408 ( .A(n2525), .Y(n2542) );
INVX2TS U2409 ( .A(n2988), .Y(n1753) );
INVX4TS U2410 ( .A(n2610), .Y(n1823) );
NAND2X6TS U2411 ( .A(n2112), .B(n1917), .Y(n1362) );
NAND2X4TS U2412 ( .A(n3144), .B(n3143), .Y(n3242) );
NAND2X4TS U2413 ( .A(n3089), .B(n3088), .Y(n3134) );
CLKAND2X2TS U2414 ( .A(mult_x_58_b_5_), .B(mult_x_58_a_4_), .Y(n3401) );
INVX12TS U2415 ( .A(n1695), .Y(n2609) );
OAI21X2TS U2416 ( .A0(n3673), .A1(n3686), .B0(n3690), .Y(n3675) );
INVX2TS U2417 ( .A(n2102), .Y(n2104) );
INVX2TS U2418 ( .A(n3991), .Y(n3992) );
NAND2X4TS U2419 ( .A(n3775), .B(n3929), .Y(n1419) );
XOR3X2TS U2420 ( .A(n3429), .B(net287451), .C(n934), .Y(n3428) );
NOR2X1TS U2421 ( .A(n4028), .B(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N0),
.Y(n4031) );
AOI2BB2X2TS U2422 ( .B0(n3932), .B1(n242), .A0N(n1127), .A1N(n4433), .Y(
n3696) );
NOR2X2TS U2423 ( .A(n365), .B(n353), .Y(n4063) );
ADDFHX2TS U2424 ( .A(n3524), .B(n3523), .CI(n3522), .CO(n4272), .S(n4273) );
AOI2BB2X2TS U2425 ( .B0(n3927), .B1(n246), .A0N(n3930), .A1N(n4430), .Y(
n3749) );
AOI2BB2X2TS U2426 ( .B0(n3927), .B1(n244), .A0N(n1127), .A1N(n4432), .Y(
n3711) );
AOI22X1TS U2427 ( .A0(n3866), .A1(Add_result[9]), .B0(
Sgf_normalized_result[8]), .B1(n3912), .Y(n3760) );
AOI2BB2X2TS U2428 ( .B0(n3929), .B1(n245), .A0N(n1127), .A1N(n4431), .Y(
n3734) );
INVX2TS U2429 ( .A(n1315), .Y(n1086) );
AOI2BB2X2TS U2430 ( .B0(n3932), .B1(n3923), .A0N(n1127), .A1N(n4397), .Y(
n4550) );
NAND2BX1TS U2431 ( .AN(Add_result[23]), .B(FSM_selector_C), .Y(n1526) );
ADDFHX2TS U2432 ( .A(n354), .B(n366), .CI(DP_OP_158J21_127_356_n1057), .CO(
n4051), .S(n4052) );
ACHCINX2TS U2433 ( .CIN(n1533), .A(n3584), .B(n3583), .CO(n4292) );
NAND3X4TS U2434 ( .A(n1350), .B(n1349), .C(n1348), .Y(n1347) );
NAND2X2TS U2435 ( .A(n3605), .B(add_x_19_n95), .Y(add_x_19_n94) );
AND2X4TS U2436 ( .A(n2112), .B(n2110), .Y(n1846) );
NAND2X4TS U2437 ( .A(add_x_19_n246), .B(n1478), .Y(add_x_19_n244) );
CLKINVX6TS U2438 ( .A(n3616), .Y(n3031) );
XOR2X2TS U2439 ( .A(n1339), .B(n1338), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N6)
);
NAND2X2TS U2440 ( .A(n3931), .B(n3850), .Y(n4570) );
AOI22X1TS U2441 ( .A0(n3873), .A1(Add_result[20]), .B0(n4001), .B1(n4533),
.Y(n4559) );
INVX2TS U2442 ( .A(n3654), .Y(n1329) );
INVX2TS U2443 ( .A(n3626), .Y(n3807) );
NOR2BX1TS U2444 ( .AN(n4520), .B(n829), .Y(n1549) );
INVX2TS U2445 ( .A(n1026), .Y(n1025) );
NOR2BX1TS U2446 ( .AN(n4521), .B(n829), .Y(n1026) );
NOR2BX1TS U2447 ( .AN(n4523), .B(n936), .Y(n1538) );
INVX2TS U2448 ( .A(rst), .Y(n1094) );
NAND2X2TS U2449 ( .A(n3804), .B(n3922), .Y(n4548) );
INVX3TS U2450 ( .A(n1128), .Y(n1131) );
INVX3TS U2451 ( .A(n1128), .Y(n1130) );
BUFX3TS U2452 ( .A(n1094), .Y(n4536) );
CLKBUFX3TS U2453 ( .A(n1093), .Y(n4535) );
CLKBUFX2TS U2454 ( .A(n1093), .Y(n1125) );
BUFX3TS U2455 ( .A(n3631), .Y(n4191) );
INVX3TS U2456 ( .A(n1106), .Y(n1100) );
NAND2X1TS U2457 ( .A(n4011), .B(n3819), .Y(n3821) );
CLKINVX3TS U2458 ( .A(n1128), .Y(n1132) );
NAND2X4TS U2459 ( .A(net288594), .B(net291630), .Y(net288592) );
XOR2X4TS U2460 ( .A(net288221), .B(net293459), .Y(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N11) );
INVX2TS U2461 ( .A(net291330), .Y(net288235) );
NAND2X2TS U2462 ( .A(net287249), .B(net287244), .Y(net287241) );
AOI21X4TS U2463 ( .A0(net291330), .A1(net287244), .B0(net290442), .Y(
net290443) );
AND2X4TS U2464 ( .A(net292367), .B(net292370), .Y(net293003) );
ADDFHX4TS U2465 ( .A(n832), .B(net288740), .CI(net288742), .CO(net288739),
.S(net288756) );
NAND2X6TS U2466 ( .A(net288738), .B(net288739), .Y(net287974) );
ADDFHX4TS U2467 ( .A(net288748), .B(net288749), .CI(net288750), .CO(
net288248), .S(net288742) );
ADDFHX4TS U2468 ( .A(net288247), .B(net288248), .CI(net288249), .CO(
net288236), .S(net288738) );
OAI2BB1X4TS U2469 ( .A0N(net291953), .A1N(net288824), .B0(n837), .Y(
net288750) );
OAI21X4TS U2470 ( .A0(net288824), .A1(net291953), .B0(net291949), .Y(n837)
);
ADDFHX4TS U2471 ( .A(net288828), .B(net293451), .CI(n834), .CO(net288749),
.S(n833) );
ADDFHX4TS U2472 ( .A(net288815), .B(n833), .CI(net288817), .CO(n832), .S(
net288814) );
OAI22X4TS U2473 ( .A0(net292372), .A1(net288229), .B0(net293204), .B1(
net287910), .Y(n834) );
ADDHX4TS U2474 ( .A(Op_MX[5]), .B(Op_MX[11]), .CO(n835), .S(n836) );
INVX12TS U2475 ( .A(n836), .Y(net288229) );
OAI22X4TS U2476 ( .A0(net288745), .A1(net293204), .B0(net291396), .B1(
net288798), .Y(net288788) );
OAI22X4TS U2477 ( .A0(net293204), .A1(net287496), .B0(net288781), .B1(
net287495), .Y(net287455) );
BUFX20TS U2478 ( .A(net292178), .Y(net292233) );
OAI22X4TS U2479 ( .A0(net291956), .A1(net288747), .B0(net288242), .B1(
net292372), .Y(net288809) );
XOR2X4TS U2480 ( .A(n839), .B(DP_OP_159J21_128_5719_n229), .Y(n838) );
AND2X2TS U2481 ( .A(net287916), .B(net287246), .Y(net293459) );
INVX4TS U2482 ( .A(net287250), .Y(net287916) );
NOR2X8TS U2483 ( .A(net288223), .B(net288224), .Y(net287250) );
NOR2X4TS U2484 ( .A(net287250), .B(net287247), .Y(net287244) );
XOR2X4TS U2485 ( .A(net292173), .B(net292333), .Y(net292780) );
ACHCINX4TS U2486 ( .CIN(net292780), .A(net288678), .B(net288677), .CO(
DP_OP_155J21_124_2814_net275301) );
INVX3TS U2487 ( .A(net288684), .Y(net292332) );
XOR2X4TS U2488 ( .A(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N8),
.B(net288678), .Y(net292175) );
ADDFHX4TS U2489 ( .A(mult_x_57_n15), .B(mult_x_57_n17), .CI(n846), .CO(n843),
.S(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N8)
);
ADDFHX4TS U2490 ( .A(mult_x_57_n14), .B(n842), .CI(n843), .CO(net287491),
.S(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N9)
);
ADDFHX4TS U2491 ( .A(mult_x_57_n18), .B(mult_x_57_n22), .CI(n847), .CO(n846),
.S(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N7)
);
ADDFHX4TS U2492 ( .A(mult_x_57_n23), .B(mult_x_57_n29), .CI(n848), .CO(n847),
.S(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N6)
);
ADDFHX4TS U2493 ( .A(mult_x_57_n30), .B(mult_x_57_n36), .CI(n849), .CO(n848),
.S(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N5)
);
CMPR32X2TS U2494 ( .A(mult_x_57_n37), .B(mult_x_57_n40), .C(n845), .CO(n849),
.S(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N4)
);
INVX2TS U2495 ( .A(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N4),
.Y(net287462) );
CMPR32X2TS U2496 ( .A(mult_x_57_n41), .B(mult_x_57_n43), .C(n844), .CO(n845),
.S(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N3)
);
INVX2TS U2497 ( .A(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N3),
.Y(net287459) );
INVX2TS U2498 ( .A(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N2),
.Y(net287451) );
CMPR42X2TS U2499 ( .A(net292731), .B(mult_x_57_n31), .C(mult_x_57_n27), .D(
mult_x_57_n25), .ICI(mult_x_57_n28), .S(mult_x_57_n23), .ICO(
mult_x_57_n21), .CO(mult_x_57_n22) );
AND2X4TS U2500 ( .A(mult_x_57_a_5_), .B(mult_x_57_b_1_), .Y(n841) );
ADDFX2TS U2501 ( .A(mult_x_57_n49), .B(net292765), .CI(n840), .CO(
mult_x_57_n19), .S(mult_x_57_n20) );
AND2X2TS U2502 ( .A(mult_x_57_b_4_), .B(mult_x_57_a_3_), .Y(mult_x_57_n59)
);
CMPR32X2TS U2503 ( .A(net287493), .B(net287494), .C(mult_x_57_n13), .CO(
net287489), .S(n842) );
XOR2X4TS U2504 ( .A(net290421), .B(net292175), .Y(
DP_OP_155J21_124_2814_net275302) );
AND2X4TS U2505 ( .A(net288834), .B(net291299), .Y(net293451) );
OAI22X4TS U2506 ( .A0(net292376), .A1(net288243), .B0(net288230), .B1(
net291396), .Y(net288828) );
OAI22X2TS U2507 ( .A0(n409), .A1(net288745), .B0(net287909), .B1(net288798),
.Y(net288748) );
INVX12TS U2508 ( .A(net288853), .Y(net288747) );
ADDHX4TS U2509 ( .A(Op_MX[3]), .B(Op_MX[9]), .CO(net288852), .S(net288853)
);
INVX16TS U2510 ( .A(n857), .Y(net288241) );
NAND2X8TS U2511 ( .A(n855), .B(n856), .Y(n857) );
INVX8TS U2512 ( .A(net288841), .Y(n853) );
ADDFHX4TS U2513 ( .A(net288818), .B(net288819), .CI(net288820), .CO(
net288824), .S(net288808) );
ADDFHX4TS U2514 ( .A(net288808), .B(n851), .CI(net288806), .CO(net288813),
.S(net288767) );
ADDHX4TS U2515 ( .A(net288821), .B(n852), .CO(net288820), .S(n850) );
ADDFHX4TS U2516 ( .A(n850), .B(net288802), .CI(net288803), .CO(n851), .S(
net288763) );
INVX12TS U2517 ( .A(net292234), .Y(net288826) );
INVX12TS U2518 ( .A(net288826), .Y(net287495) );
INVX12TS U2519 ( .A(net288826), .Y(net288778) );
NAND2BX4TS U2520 ( .AN(net290827), .B(DP_OP_159J21_128_5719_n262), .Y(
net292234) );
NOR2X8TS U2521 ( .A(DP_OP_159J21_128_5719_n300), .B(
DP_OP_159J21_128_5719_n294), .Y(net290827) );
OAI22X4TS U2522 ( .A0(net291396), .A1(net288243), .B0(net292233), .B1(
net288230), .Y(net288819) );
OAI22X4TS U2523 ( .A0(net292233), .A1(net288229), .B0(net287910), .B1(
net288778), .Y(net288818) );
ADDHX4TS U2524 ( .A(Op_MX[4]), .B(Op_MX[10]), .CO(net288858), .S(net288862)
);
NAND2X4TS U2525 ( .A(net288237), .B(net288236), .Y(net287971) );
MX2X6TS U2526 ( .A(Data_MX[4]), .B(Op_MX[4]), .S0(net287633), .Y(n348) );
NOR4X1TS U2527 ( .A(Op_MX[6]), .B(Op_MX[4]), .C(Op_MX[12]), .D(Op_MX[5]),
.Y(net286882) );
MX2X6TS U2528 ( .A(Data_MX[10]), .B(Op_MX[10]), .S0(net287633), .Y(n354) );
NOR4X1TS U2529 ( .A(Op_MX[8]), .B(Op_MX[9]), .C(Op_MX[21]), .D(Op_MX[10]),
.Y(net286886) );
ADDFHX4TS U2530 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[1]),
.B(n2834), .CI(add_x_19_n106), .CO(n2831), .S(n3003) );
XOR2X4TS U2531 ( .A(n447), .B(n2627), .Y(n1216) );
NAND3X4TS U2532 ( .A(n1351), .B(n447), .C(n1509), .Y(n1350) );
AOI2BB2X4TS U2533 ( .B0(n2879), .B1(n1408), .A0N(n1407), .A1N(n1409), .Y(
n861) );
ADDFHX4TS U2534 ( .A(n2918), .B(n2917), .CI(n2916), .CO(n2934), .S(n2914) );
AND3X6TS U2535 ( .A(n3805), .B(n3806), .C(n1273), .Y(n917) );
OAI21X2TS U2536 ( .A0(FSM_selector_B_1_), .A1(n4390), .B0(n2066), .Y(n2045)
);
AND2X8TS U2537 ( .A(n2242), .B(n928), .Y(n864) );
INVX2TS U2538 ( .A(n1106), .Y(n1112) );
BUFX3TS U2539 ( .A(n1131), .Y(n4543) );
INVX2TS U2540 ( .A(n2076), .Y(n2063) );
MXI2X4TS U2541 ( .A(Data_MY[19]), .B(Op_MY[19]), .S0(net287652), .Y(n331) );
INVX2TS U2542 ( .A(n3601), .Y(add_x_19_n114) );
OR2X8TS U2543 ( .A(n2010), .B(n2009), .Y(n867) );
AND2X8TS U2544 ( .A(n1425), .B(n1460), .Y(n869) );
INVX6TS U2545 ( .A(n318), .Y(n1114) );
AND2X8TS U2546 ( .A(n1175), .B(n1031), .Y(n871) );
AND2X8TS U2547 ( .A(n1565), .B(n2345), .Y(n872) );
AND2X4TS U2548 ( .A(n1713), .B(n2021), .Y(n874) );
INVX8TS U2549 ( .A(n333), .Y(n1095) );
INVX6TS U2550 ( .A(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[8]), .Y(
n2384) );
INVX2TS U2551 ( .A(n1584), .Y(n3383) );
AO21X4TS U2552 ( .A0(n4064), .A1(n4079), .B0(n1903), .Y(n885) );
INVX4TS U2553 ( .A(n3279), .Y(n3253) );
CLKXOR2X2TS U2554 ( .A(n2190), .B(n2183), .Y(n886) );
AND2X8TS U2555 ( .A(n2737), .B(n2736), .Y(n887) );
CLKXOR2X4TS U2556 ( .A(n2165), .B(n2166), .Y(n3877) );
OR2X8TS U2557 ( .A(n2028), .B(n2198), .Y(n888) );
XNOR2X4TS U2558 ( .A(n1336), .B(n2351), .Y(n890) );
NAND2X4TS U2559 ( .A(n429), .B(n2391), .Y(n1607) );
CLKXOR2X2TS U2560 ( .A(n2172), .B(n2239), .Y(n891) );
INVX4TS U2561 ( .A(n2150), .Y(n1973) );
AND2X2TS U2562 ( .A(n2464), .B(n2463), .Y(n893) );
NOR2X6TS U2563 ( .A(n1986), .B(n1985), .Y(n2292) );
INVX2TS U2564 ( .A(n1546), .Y(n1301) );
INVX4TS U2565 ( .A(n2174), .Y(n1234) );
AO21X4TS U2566 ( .A0(n2313), .A1(n976), .B0(n975), .Y(n898) );
INVX4TS U2567 ( .A(n2018), .Y(n1144) );
AND3X8TS U2568 ( .A(n1832), .B(n1831), .C(n1829), .Y(n901) );
OR2X4TS U2569 ( .A(n448), .B(n785), .Y(n902) );
AND2X4TS U2570 ( .A(n1180), .B(n896), .Y(n904) );
OA21X4TS U2571 ( .A0(n1877), .A1(n820), .B0(n797), .Y(n905) );
AND2X8TS U2572 ( .A(n2445), .B(n1889), .Y(n906) );
NAND2X6TS U2573 ( .A(n2179), .B(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[7]), .Y(n2511) );
INVX6TS U2574 ( .A(n2511), .Y(n993) );
AND2X8TS U2575 ( .A(n2644), .B(n1649), .Y(n907) );
AND2X2TS U2576 ( .A(net287906), .B(net287248), .Y(n908) );
AND2X2TS U2577 ( .A(n2178), .B(n1014), .Y(n910) );
AND2X8TS U2578 ( .A(n3243), .B(n3244), .Y(n912) );
OR2X4TS U2579 ( .A(n2594), .B(n2514), .Y(n914) );
NAND2X4TS U2580 ( .A(n1983), .B(DP_OP_153J21_122_3500_n167), .Y(n2273) );
NAND2X4TS U2581 ( .A(DP_OP_154J21_123_2814_n121), .B(
DP_OP_154J21_123_2814_n120), .Y(n1927) );
INVX2TS U2582 ( .A(n1927), .Y(n1466) );
AND2X4TS U2583 ( .A(n2030), .B(n2029), .Y(n918) );
NAND2X4TS U2584 ( .A(n2272), .B(n2271), .Y(n2378) );
INVX2TS U2585 ( .A(n1698), .Y(n2196) );
AND2X4TS U2586 ( .A(n2379), .B(n2378), .Y(n920) );
AND2X8TS U2587 ( .A(n1269), .B(n3822), .Y(n923) );
AND2X4TS U2588 ( .A(n1949), .B(n1948), .Y(n924) );
AND2X2TS U2589 ( .A(n1117), .B(n952), .Y(n925) );
INVX2TS U2590 ( .A(n1055), .Y(n2963) );
XNOR2X2TS U2591 ( .A(n3856), .B(n2038), .Y(n926) );
INVX4TS U2592 ( .A(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[5]), .Y(
n1494) );
AND2X4TS U2593 ( .A(DP_OP_155J21_124_2814_n118), .B(
DP_OP_155J21_124_2814_n119), .Y(n929) );
INVX2TS U2594 ( .A(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[13]),
.Y(n1014) );
INVX4TS U2595 ( .A(DP_OP_156J21_125_3370_n360), .Y(n4125) );
INVX2TS U2596 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[8]), .Y(
n1707) );
INVX2TS U2597 ( .A(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[9]), .Y(
n2602) );
INVX2TS U2598 ( .A(rst), .Y(n1093) );
INVX2TS U2599 ( .A(rst), .Y(n1092) );
BUFX3TS U2600 ( .A(n4105), .Y(n4106) );
CLKINVX3TS U2601 ( .A(n1128), .Y(n1105) );
CLKINVX3TS U2602 ( .A(n1128), .Y(n1104) );
CLKINVX3TS U2603 ( .A(n1106), .Y(n1110) );
INVX2TS U2604 ( .A(n1106), .Y(n1107) );
CLKINVX3TS U2605 ( .A(n1128), .Y(n1109) );
INVX2TS U2606 ( .A(n1106), .Y(n1108) );
BUFX3TS U2607 ( .A(n4441), .Y(n4542) );
INVX2TS U2608 ( .A(n1128), .Y(n1103) );
INVX2TS U2609 ( .A(n1106), .Y(n1102) );
INVX2TS U2610 ( .A(n1128), .Y(n1101) );
INVX2TS U2611 ( .A(n4542), .Y(n1106) );
NAND2X8TS U2612 ( .A(n943), .B(n942), .Y(n1168) );
NOR2X8TS U2613 ( .A(n2028), .B(n2197), .Y(n942) );
NOR2X8TS U2614 ( .A(n1017), .B(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[3]), .Y(n2197) );
XOR2X4TS U2615 ( .A(n1967), .B(n1966), .Y(n1017) );
NOR2X8TS U2616 ( .A(n1165), .B(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[4]), .Y(n2028) );
OAI21X4TS U2617 ( .A0(n1236), .A1(n1698), .B0(n944), .Y(n943) );
NAND2X8TS U2618 ( .A(n1247), .B(n2185), .Y(n2195) );
NOR2X8TS U2619 ( .A(n946), .B(n945), .Y(n1236) );
OAI21X4TS U2620 ( .A0(n1944), .A1(n2296), .B0(n2212), .Y(n945) );
NOR2X8TS U2621 ( .A(n1556), .B(n1557), .Y(n946) );
NAND2X8TS U2622 ( .A(n2283), .B(n2281), .Y(n1238) );
XOR2X4TS U2623 ( .A(n1701), .B(n947), .Y(n1952) );
OR2X8TS U2624 ( .A(n1953), .B(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[10]), .Y(n2283) );
XOR2X4TS U2625 ( .A(n980), .B(n924), .Y(n1953) );
NAND3X8TS U2626 ( .A(n1598), .B(n1597), .C(n1951), .Y(n980) );
NOR2X8TS U2627 ( .A(n2462), .B(n2449), .Y(n1889) );
NOR2X8TS U2628 ( .A(n2454), .B(n2453), .Y(n2445) );
INVX12TS U2629 ( .A(n953), .Y(n2253) );
AND2X8TS U2630 ( .A(n3008), .B(n886), .Y(n3769) );
XNOR2X4TS U2631 ( .A(n2187), .B(n2186), .Y(n3008) );
NAND2X8TS U2632 ( .A(n2632), .B(n2631), .Y(n1433) );
NAND3X8TS U2633 ( .A(n965), .B(n964), .C(n865), .Y(n2597) );
NAND3X4TS U2634 ( .A(n2618), .B(n1627), .C(n1626), .Y(n965) );
NAND2X8TS U2635 ( .A(n1527), .B(n2613), .Y(n1592) );
NAND2X8TS U2636 ( .A(n1082), .B(n1593), .Y(n1527) );
NAND3X8TS U2637 ( .A(n966), .B(n1703), .C(DP_OP_155J21_124_2814_n90), .Y(
n1598) );
NAND2X8TS U2638 ( .A(n966), .B(n1702), .Y(n1597) );
INVX12TS U2639 ( .A(DP_OP_155J21_124_2814_n84), .Y(n966) );
XOR2X4TS U2640 ( .A(n1912), .B(n1911), .Y(n967) );
OAI21X4TS U2641 ( .A0(n2274), .A1(n968), .B0(n2273), .Y(n2277) );
NAND2X8TS U2642 ( .A(n970), .B(n969), .Y(n1447) );
NAND3X8TS U2643 ( .A(n972), .B(n971), .C(n2225), .Y(n1445) );
NAND2X8TS U2644 ( .A(n1980), .B(DP_OP_153J21_122_3500_n169), .Y(n2225) );
NAND2X4TS U2645 ( .A(add_x_19_n320), .B(add_x_19_n238), .Y(add_x_19_n20) );
NAND2X8TS U2646 ( .A(n973), .B(n2575), .Y(n1498) );
XNOR2X4TS U2647 ( .A(n2258), .B(n2259), .Y(n2315) );
INVX2TS U2648 ( .A(n2312), .Y(n975) );
NAND2X8TS U2649 ( .A(n978), .B(n2275), .Y(n1626) );
OR2X8TS U2650 ( .A(n1984), .B(DP_OP_153J21_122_3500_n166), .Y(n1333) );
AOI21X4TS U2651 ( .A0(n980), .A1(n1949), .B0(n1938), .Y(n1941) );
NAND3X4TS U2652 ( .A(n1174), .B(n1959), .C(n980), .Y(n1173) );
BUFX12TS U2653 ( .A(n2525), .Y(n982) );
XNOR2X4TS U2654 ( .A(n1600), .B(n2158), .Y(n2525) );
NAND3X8TS U2655 ( .A(n446), .B(n2379), .C(n983), .Y(n1199) );
NAND2X8TS U2656 ( .A(n1196), .B(n2263), .Y(n983) );
XNOR2X4TS U2657 ( .A(n1779), .B(n920), .Y(n1778) );
XNOR2X4TS U2658 ( .A(n984), .B(n987), .Y(n2031) );
NAND3X6TS U2659 ( .A(n986), .B(n985), .C(n2152), .Y(n984) );
NAND2X6TS U2660 ( .A(n1243), .B(n1180), .Y(n986) );
OR2X4TS U2661 ( .A(n992), .B(n988), .Y(n1194) );
INVX6TS U2662 ( .A(n996), .Y(Sgf_operation_EVEN1_Q_left[7]) );
XNOR2X4TS U2663 ( .A(n2229), .B(n997), .Y(n2168) );
XOR2X4TS U2664 ( .A(Sgf_operation_EVEN1_Q_left[7]), .B(n2230), .Y(n997) );
XNOR2X4TS U2665 ( .A(n1000), .B(n1359), .Y(n996) );
OAI2BB1X4TS U2666 ( .A0N(n2230), .A1N(n2229), .B0(n998), .Y(n2269) );
OAI21X4TS U2667 ( .A0(n2229), .A1(n2230), .B0(n999), .Y(n998) );
XOR2X4TS U2668 ( .A(n2111), .B(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[7]), .Y(n1000) );
INVX2TS U2669 ( .A(n3598), .Y(DP_OP_156J21_125_3370_n173) );
NAND2X4TS U2670 ( .A(n2014), .B(n2013), .Y(n2391) );
OAI22X4TS U2671 ( .A0(net293204), .A1(net288242), .B0(net291396), .B1(
net288747), .Y(net288802) );
NOR2X8TS U2672 ( .A(n1972), .B(n1971), .Y(n2150) );
NOR2X8TS U2673 ( .A(n2030), .B(n2029), .Y(n2153) );
NAND2X8TS U2674 ( .A(n1003), .B(n2175), .Y(n2512) );
NAND3X8TS U2675 ( .A(n888), .B(n2027), .C(n1168), .Y(n1167) );
NAND2X4TS U2676 ( .A(n1009), .B(n904), .Y(n1015) );
OR2X8TS U2677 ( .A(n904), .B(n1008), .Y(n1006) );
OR2X8TS U2678 ( .A(n1009), .B(n1008), .Y(n1007) );
NOR2X8TS U2679 ( .A(n2179), .B(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[7]), .Y(n1246) );
NAND3X8TS U2680 ( .A(n1013), .B(n1012), .C(n1011), .Y(n2179) );
NAND2X8TS U2681 ( .A(n1491), .B(n407), .Y(n1463) );
NAND3X8TS U2682 ( .A(n1019), .B(n1534), .C(n2245), .Y(n1731) );
XNOR2X2TS U2683 ( .A(n2224), .B(n1019), .Y(Sgf_operation_EVEN1_Q_left[8]) );
NAND2X8TS U2684 ( .A(n1360), .B(n1358), .Y(n1019) );
XOR2X4TS U2685 ( .A(n1020), .B(n1687), .Y(n2830) );
NAND4X8TS U2686 ( .A(n1424), .B(n1423), .C(n1421), .D(n1422), .Y(n1020) );
NOR2X8TS U2687 ( .A(DP_OP_155J21_124_2814_n122), .B(
DP_OP_155J21_124_2814_n123), .Y(n1958) );
NAND2X8TS U2688 ( .A(n2109), .B(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[6]), .Y(n2112) );
XNOR2X4TS U2689 ( .A(n1021), .B(DP_OP_154J21_123_2814_n144), .Y(n2109) );
NAND2BX4TS U2690 ( .AN(n878), .B(n4345), .Y(n1869) );
OAI22X4TS U2691 ( .A0(n884), .A1(n2684), .B0(n2683), .B1(n474), .Y(n2685) );
XNOR2X4TS U2692 ( .A(n2719), .B(n2678), .Y(n2683) );
AND2X8TS U2693 ( .A(n3310), .B(n3311), .Y(DP_OP_158J21_127_356_n33) );
OAI21X4TS U2694 ( .A0(n1027), .A1(n830), .B0(n1025), .Y(n248) );
XOR2X4TS U2695 ( .A(n1028), .B(n2457), .Y(n1027) );
AOI21X4TS U2696 ( .A0(n1167), .A1(n871), .B0(n2512), .Y(n2180) );
OR2X8TS U2697 ( .A(n2157), .B(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[6]), .Y(n1175) );
NOR2X4TS U2698 ( .A(n1237), .B(n1240), .Y(n1033) );
NOR2X4TS U2699 ( .A(n1237), .B(n1240), .Y(n1557) );
NOR2X8TS U2700 ( .A(n1239), .B(n1238), .Y(n1237) );
INVX8TS U2701 ( .A(n2606), .Y(n1826) );
AOI21X2TS U2702 ( .A0(n1626), .A1(n2618), .B0(n1357), .Y(n2569) );
INVX8TS U2703 ( .A(n1493), .Y(n1465) );
OAI22X4TS U2704 ( .A0(n2801), .A1(n1090), .B0(n2795), .B1(n2802), .Y(n2805)
);
INVX6TS U2705 ( .A(n1137), .Y(n1785) );
NAND2X6TS U2706 ( .A(n1963), .B(n1174), .Y(n1169) );
INVX8TS U2707 ( .A(n2112), .Y(n1359) );
OAI22X4TS U2708 ( .A0(n2442), .A1(n1220), .B0(n3346), .B1(n2331), .Y(n2438)
);
NOR2X6TS U2709 ( .A(n2202), .B(n2217), .Y(n2841) );
NAND2X4TS U2710 ( .A(n2417), .B(n2528), .Y(n1441) );
NAND2X4TS U2711 ( .A(n1158), .B(n4544), .Y(n2002) );
OR2X4TS U2712 ( .A(n2655), .B(n2747), .Y(n1036) );
OR2X4TS U2713 ( .A(n417), .B(n436), .Y(n1037) );
MXI2X4TS U2714 ( .A(Data_MY[20]), .B(Op_MY[20]), .S0(net287652), .Y(n332) );
INVX2TS U2715 ( .A(n332), .Y(n1039) );
INVX12TS U2716 ( .A(n2563), .Y(n1513) );
NAND2X2TS U2717 ( .A(n801), .B(n816), .Y(n3680) );
XNOR2X2TS U2718 ( .A(n1189), .B(DP_OP_155J21_124_2814_n144), .Y(n1043) );
BUFX20TS U2719 ( .A(n1264), .Y(n1141) );
NAND2X2TS U2720 ( .A(n2911), .B(n2910), .Y(n3592) );
NAND2X2TS U2721 ( .A(n2615), .B(n2575), .Y(n2576) );
NAND2X4TS U2722 ( .A(n546), .B(n3792), .Y(n1804) );
NOR2X6TS U2723 ( .A(DP_OP_155J21_124_2814_n78), .B(n1943), .Y(n1959) );
INVX6TS U2724 ( .A(n1964), .Y(n1257) );
AOI21X2TS U2725 ( .A0(n2260), .A1(n1799), .B0(n2556), .Y(n2559) );
XOR2X4TS U2726 ( .A(n1046), .B(n1626), .Y(n2311) );
AND2X4TS U2727 ( .A(n1074), .B(n2303), .Y(n1046) );
OAI21X1TS U2728 ( .A0(n3046), .A1(n1748), .B0(n3047), .Y(n1047) );
NAND3X4TS U2729 ( .A(n1598), .B(n1597), .C(n1951), .Y(n1066) );
XNOR2X4TS U2730 ( .A(n2209), .B(n1613), .Y(n2616) );
AOI21X4TS U2731 ( .A0(n1163), .A1(n2596), .B0(n2595), .Y(n2600) );
ADDHX4TS U2732 ( .A(Op_MX[14]), .B(Op_MX[20]), .CO(n2877), .S(n2876) );
ADDHX4TS U2733 ( .A(n2476), .B(n2475), .CO(n2482), .S(n2485) );
NAND2X6TS U2734 ( .A(n1834), .B(n818), .Y(n1833) );
INVX8TS U2735 ( .A(n2998), .Y(n1638) );
OR2X4TS U2736 ( .A(n1700), .B(n1699), .Y(n2185) );
INVX3TS U2737 ( .A(n1180), .Y(n1179) );
NAND2X4TS U2738 ( .A(n2507), .B(n2506), .Y(n1207) );
NAND2X4TS U2739 ( .A(n1048), .B(n1049), .Y(n2892) );
ADDFHX4TS U2740 ( .A(n2893), .B(n2892), .CI(n2891), .CO(n2885), .S(n2930) );
OAI22X2TS U2741 ( .A0(n1340), .A1(n3567), .B0(n720), .B1(n2908), .Y(n2924)
);
NAND2BX2TS U2742 ( .AN(n1149), .B(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[8]), .Y(n1147) );
NAND2X4TS U2743 ( .A(n2515), .B(n1163), .Y(n1151) );
AOI2BB2X2TS U2744 ( .B0(n880), .B1(n2591), .A0N(n2514), .A1N(n2594), .Y(
n1714) );
AOI21X2TS U2745 ( .A0(n2591), .A1(n880), .B0(n2513), .Y(n1745) );
CLKINVX6TS U2746 ( .A(n1963), .Y(n1503) );
ADDFHX4TS U2747 ( .A(n2370), .B(n2369), .CI(n2368), .CO(n2361), .S(n3015) );
ADDFHX4TS U2748 ( .A(n2926), .B(n2925), .CI(n2924), .CO(n2931), .S(n2927) );
ADDFHX4TS U2749 ( .A(n2763), .B(n2764), .CI(n2762), .CO(n2796), .S(n2783) );
NAND2X6TS U2750 ( .A(n3021), .B(n1689), .Y(n1544) );
NAND2X6TS U2751 ( .A(n3021), .B(n1571), .Y(n1570) );
NAND2X4TS U2752 ( .A(n2848), .B(n2847), .Y(n3339) );
OAI22X2TS U2753 ( .A0(n3347), .A1(n3346), .B0(n437), .B1(n1221), .Y(n3361)
);
INVX6TS U2754 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[7]), .Y(
n1994) );
AO21X4TS U2755 ( .A0(n1051), .A1(n818), .B0(n1052), .Y(n3922) );
XNOR2X4TS U2756 ( .A(n1636), .B(n939), .Y(n1051) );
NOR2X6TS U2757 ( .A(n1244), .B(n2150), .Y(n1243) );
NAND2X4TS U2758 ( .A(n2778), .B(n2777), .Y(n3055) );
OAI22X2TS U2759 ( .A0(n2804), .A1(n2802), .B0(n1090), .B1(n1451), .Y(n2373)
);
OAI22X4TS U2760 ( .A0(n2360), .A1(n3305), .B0(n2441), .B1(n1118), .Y(n2437)
);
NOR2X6TS U2761 ( .A(n2384), .B(n2385), .Y(n2377) );
INVX2TS U2762 ( .A(n1670), .Y(n1512) );
OA22X2TS U2763 ( .A0(n1382), .A1(n2960), .B0(n1520), .B1(n2946), .Y(n1055)
);
ADDFHX4TS U2764 ( .A(n2822), .B(n2821), .CI(n2820), .CO(n2828), .S(n2823) );
NAND2X2TS U2765 ( .A(n3804), .B(n3926), .Y(n4561) );
XOR2X4TS U2766 ( .A(n2465), .B(n893), .Y(n2466) );
AND2X6TS U2767 ( .A(n3576), .B(n1435), .Y(n1060) );
XOR2X1TS U2768 ( .A(n3578), .B(n3577), .Y(n1056) );
NAND2X4TS U2769 ( .A(n3578), .B(n3579), .Y(n1057) );
NAND2X4TS U2770 ( .A(n3577), .B(n3579), .Y(n1058) );
XOR2X4TS U2771 ( .A(n1536), .B(n1060), .Y(n3579) );
NAND2X4TS U2772 ( .A(n2394), .B(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[12]), .Y(n2397) );
NAND2X4TS U2773 ( .A(DP_OP_155J21_124_2814_n123), .B(
DP_OP_155J21_124_2814_n122), .Y(n1961) );
NAND2X4TS U2774 ( .A(n3334), .B(n1330), .Y(n4589) );
BUFX12TS U2775 ( .A(net286913), .Y(net287652) );
OR2X8TS U2776 ( .A(n1947), .B(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[8]), .Y(n2232) );
NAND2X4TS U2777 ( .A(n1210), .B(n1135), .Y(n1209) );
XNOR2X4TS U2778 ( .A(n1137), .B(n437), .Y(n2331) );
NAND4X4TS U2779 ( .A(n917), .B(Exp_module_Data_S[6]), .C(
Exp_module_Data_S[4]), .D(Exp_module_Data_S[5]), .Y(n1269) );
BUFX20TS U2780 ( .A(n2323), .Y(n2774) );
INVX12TS U2781 ( .A(n2774), .Y(n2775) );
NAND2BX4TS U2782 ( .AN(n496), .B(n2774), .Y(n2776) );
NOR2X4TS U2783 ( .A(n1624), .B(n1625), .Y(n2228) );
NAND2X4TS U2784 ( .A(n1437), .B(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[8]), .Y(n1726) );
NAND2X4TS U2785 ( .A(n1972), .B(n1971), .Y(n2152) );
ADDFHX2TS U2786 ( .A(n2956), .B(n2955), .CI(n2954), .CO(n1044), .S(n1068) );
ADDFHX2TS U2787 ( .A(n2943), .B(n2942), .CI(n2941), .CO(n2956), .S(n2953) );
INVX6TS U2788 ( .A(n1547), .Y(n2032) );
ADDHX4TS U2789 ( .A(Op_MX[16]), .B(Op_MX[22]), .CO(n2868), .S(n2867) );
INVX4TS U2790 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[3]),
.Y(n1981) );
ADDFHX2TS U2791 ( .A(n2509), .B(n2508), .CI(net288731), .S(n4128) );
NAND2X4TS U2792 ( .A(n3586), .B(n3587), .Y(n1372) );
BUFX20TS U2793 ( .A(n635), .Y(net291370) );
ADDFHX4TS U2794 ( .A(n2480), .B(n2479), .CI(n2478), .CO(n2497), .S(n2493) );
NOR2X6TS U2795 ( .A(n2235), .B(n2236), .Y(n2264) );
BUFX20TS U2796 ( .A(n1242), .Y(n1180) );
XOR2X4TS U2797 ( .A(n3000), .B(n1070), .Y(n1073) );
INVX4TS U2798 ( .A(n2292), .Y(n1074) );
OAI22X2TS U2799 ( .A0(n2354), .A1(n2802), .B0(n1089), .B1(n1452), .Y(n2434)
);
CLKINVX6TS U2800 ( .A(n2247), .Y(n1730) );
AOI2BB2X4TS U2801 ( .B0(n3929), .B1(n3921), .A0N(n3930), .A1N(n4404), .Y(
n4578) );
NAND2X2TS U2802 ( .A(n3804), .B(n3921), .Y(n4573) );
INVX8TS U2803 ( .A(n1204), .Y(n2341) );
NOR2X2TS U2804 ( .A(n408), .B(n3106), .Y(n3127) );
XNOR2X4TS U2805 ( .A(n3232), .B(n3231), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N8)
);
INVX6TS U2806 ( .A(n1515), .Y(n2257) );
NOR2X8TS U2807 ( .A(n2850), .B(n2849), .Y(n3340) );
AOI2BB2X2TS U2808 ( .B0(n3929), .B1(n3928), .A0N(n3930), .A1N(n4401), .Y(
n4571) );
NOR2X4TS U2809 ( .A(n1438), .B(n1612), .Y(n1436) );
OAI22X2TS U2810 ( .A0(n409), .A1(net288242), .B0(net287909), .B1(net288747),
.Y(n2825) );
NAND2X6TS U2811 ( .A(Op_MY[22]), .B(Op_MY[16]), .Y(n2870) );
NAND2X2TS U2812 ( .A(n3804), .B(n3931), .Y(n4569) );
ADDFHX4TS U2813 ( .A(n2921), .B(n2920), .CI(n2919), .CO(n2894), .S(n2933) );
OA22X4TS U2814 ( .A0(n1340), .A1(n2899), .B0(n721), .B1(n2947), .Y(n1078) );
XNOR2X4TS U2815 ( .A(n3796), .B(n937), .Y(n3797) );
ADDFHX2TS U2816 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[13]),
.B(n2617), .CI(n2616), .CO(n3007), .S(n2628) );
NOR2X4TS U2817 ( .A(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[6]),
.B(n1043), .Y(n1184) );
NAND2X4TS U2818 ( .A(n3213), .B(n3218), .Y(n3207) );
XNOR2X4TS U2819 ( .A(n1666), .B(n1080), .Y(n2886) );
ADDHX4TS U2820 ( .A(n2907), .B(n2906), .CO(n2903), .S(n2911) );
AND3X8TS U2821 ( .A(n1622), .B(n1620), .C(n3032), .Y(n1081) );
ADDFHX4TS U2822 ( .A(n2572), .B(n2571), .CI(n2570), .S(n1082) );
ADDFHX4TS U2823 ( .A(n2503), .B(n2504), .CI(n2502), .CO(net288247), .S(
net288740) );
ADDFHX2TS U2824 ( .A(n2970), .B(n2969), .CI(n2968), .CO(n2978), .S(n2965) );
OAI22X4TS U2825 ( .A0(n2669), .A1(n2716), .B0(n2707), .B1(n461), .Y(n2701)
);
NOR2X6TS U2826 ( .A(DP_OP_158J21_127_356_n46), .B(n3340), .Y(n2852) );
OR2X4TS U2827 ( .A(n1546), .B(n2967), .Y(n1369) );
AND2X4TS U2828 ( .A(n326), .B(n358), .Y(n4256) );
AND2X2TS U2829 ( .A(n326), .B(n356), .Y(n3529) );
AND2X4TS U2830 ( .A(n326), .B(n359), .Y(n3524) );
AND2X4TS U2831 ( .A(n1087), .B(n358), .Y(n3558) );
AND2X4TS U2832 ( .A(n1087), .B(n359), .Y(n3540) );
OAI22X2TS U2833 ( .A0(n2765), .A1(n1042), .B0(n2769), .B1(n1543), .Y(n2782)
);
INVX2TS U2834 ( .A(n1106), .Y(n1111) );
NOR3X1TS U2835 ( .A(Op_MY[17]), .B(Op_MY[25]), .C(Op_MY[23]), .Y(n3891) );
AO22X2TS U2836 ( .A0(n3875), .A1(n3988), .B0(final_result_ieee[20]), .B1(
n3905), .Y(n170) );
MXI2X2TS U2837 ( .A(n3822), .B(n1838), .S0(n4584), .Y(n273) );
MXI2X4TS U2838 ( .A(n1320), .B(n931), .S0(net286914), .Y(n324) );
NOR2X8TS U2839 ( .A(n313), .B(n325), .Y(n3314) );
NOR2X4TS U2840 ( .A(n1117), .B(n535), .Y(n1585) );
NOR2X6TS U2841 ( .A(n3568), .B(n2946), .Y(n2898) );
NOR2X4TS U2842 ( .A(n1119), .B(n2899), .Y(n2907) );
INVX6TS U2843 ( .A(n1142), .Y(n3568) );
OAI22X4TS U2844 ( .A0(net288241), .A1(net288229), .B0(net291956), .B1(
net287910), .Y(n2822) );
OAI22X4TS U2845 ( .A0(net292476), .A1(n2488), .B0(net291956), .B1(n2477),
.Y(n2479) );
OAI22X2TS U2846 ( .A0(n635), .A1(net288747), .B0(net288241), .B1(net288242),
.Y(n2503) );
BUFX8TS U2847 ( .A(n320), .Y(n1120) );
BUFX20TS U2848 ( .A(net291904), .Y(net287583) );
INVX4TS U2849 ( .A(n331), .Y(n1122) );
INVX8TS U2850 ( .A(n331), .Y(n1123) );
AND2X4TS U2851 ( .A(n1122), .B(n365), .Y(n3470) );
XOR2X4TS U2852 ( .A(n1124), .B(n2080), .Y(n2082) );
XOR2X4TS U2853 ( .A(n1124), .B(n2067), .Y(n2069) );
NOR2BX4TS U2854 ( .AN(n496), .B(n437), .Y(n2370) );
NAND2BX4TS U2855 ( .AN(n3071), .B(n2793), .Y(n2760) );
NAND2BX2TS U2856 ( .AN(n3071), .B(n2757), .Y(n2758) );
INVX4TS U2857 ( .A(n449), .Y(n1126) );
AOI2BB2X2TS U2858 ( .B0(n3927), .B1(n243), .A0N(n1126), .A1N(n3713), .Y(
n3716) );
AOI2BB2X2TS U2859 ( .B0(n3927), .B1(n240), .A0N(n1126), .A1N(n3668), .Y(
n3670) );
AOI2BB2X1TS U2860 ( .B0(n3927), .B1(n239), .A0N(n1126), .A1N(n3914), .Y(
n3917) );
NAND2X8TS U2861 ( .A(n3799), .B(n1896), .Y(n3930) );
AOI22X2TS U2862 ( .A0(n3873), .A1(Add_result[11]), .B0(
Sgf_normalized_result[10]), .B1(n4533), .Y(n2459) );
AOI22X2TS U2863 ( .A0(n3913), .A1(Add_result[13]), .B0(
Sgf_normalized_result[12]), .B1(n4533), .Y(n3803) );
NOR4X2TS U2864 ( .A(Op_MY[29]), .B(Op_MY[8]), .C(Op_MY[19]), .D(n3890), .Y(
n3892) );
ADDFHX2TS U2865 ( .A(n2688), .B(n2689), .CI(n2687), .CO(n2694), .S(n2693) );
NOR4X2TS U2866 ( .A(Op_MY[16]), .B(Op_MY[15]), .C(Op_MY[1]), .D(Op_MY[0]),
.Y(n3888) );
NOR4X2TS U2867 ( .A(n1157), .B(Op_MY[7]), .C(Op_MY[21]), .D(Op_MY[9]), .Y(
n3893) );
AO22X2TS U2868 ( .A0(n3875), .A1(n4001), .B0(final_result_ieee[19]), .B1(
n3905), .Y(n171) );
AO22X2TS U2869 ( .A0(n3875), .A1(Sgf_normalized_result[18]), .B0(
final_result_ieee[18]), .B1(n3905), .Y(n172) );
NAND2X8TS U2870 ( .A(n1766), .B(n3379), .Y(n3372) );
NOR2X4TS U2871 ( .A(n2783), .B(n2782), .Y(n3378) );
INVX8TS U2872 ( .A(n1335), .Y(n2351) );
OAI21X4TS U2873 ( .A0(n1033), .A1(n2295), .B0(n2296), .Y(n2215) );
NAND2X6TS U2874 ( .A(n2233), .B(n2232), .Y(n1161) );
MX2X6TS U2875 ( .A(n3694), .B(n4513), .S0(n830), .Y(n241) );
AOI21X2TS U2876 ( .A0(n3687), .A1(n3672), .B0(n3674), .Y(n3688) );
NAND2BX4TS U2877 ( .AN(n3025), .B(n3026), .Y(n3027) );
NAND2X4TS U2878 ( .A(n3020), .B(n3019), .Y(n3026) );
NOR2X8TS U2879 ( .A(n3020), .B(n3019), .Y(n3025) );
NOR2X8TS U2880 ( .A(n2324), .B(DP_OP_158J21_127_356_n405), .Y(n1135) );
XOR2X4TS U2881 ( .A(n3472), .B(n1136), .Y(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N10)
);
XNOR2X4TS U2882 ( .A(n1139), .B(n1138), .Y(n1137) );
NAND2X8TS U2883 ( .A(n1786), .B(n2330), .Y(n1139) );
XNOR2X4TS U2884 ( .A(n2338), .B(n2337), .Y(n1140) );
OAI22X4TS U2885 ( .A0(n1141), .A1(n2899), .B0(n2947), .B1(n3568), .Y(n2897)
);
OA21X4TS U2886 ( .A0(DP_OP_157J21_126_5719_n293), .A1(
DP_OP_157J21_126_5719_n298), .B0(DP_OP_157J21_126_5719_n261), .Y(n1142) );
INVX12TS U2887 ( .A(n2876), .Y(n2899) );
NOR2X4TS U2888 ( .A(DP_OP_158J21_127_356_n645), .B(DP_OP_158J21_127_356_n646), .Y(n2335) );
NAND3X8TS U2889 ( .A(n1143), .B(n3372), .C(n3371), .Y(n1573) );
NAND2X1TS U2890 ( .A(n1143), .B(n3355), .Y(n1338) );
INVX12TS U2891 ( .A(n1473), .Y(n1143) );
OAI21X4TS U2892 ( .A0(n1035), .A1(n1436), .B0(n426), .Y(n1145) );
INVX4TS U2893 ( .A(n1146), .Y(n3622) );
XNOR2X4TS U2894 ( .A(n3622), .B(n1148), .Y(n2854) );
XOR2X4TS U2895 ( .A(n1150), .B(n2516), .Y(n1149) );
NOR2X8TS U2896 ( .A(n2514), .B(n2590), .Y(n2515) );
XOR2X4TS U2897 ( .A(n1152), .B(n1694), .Y(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N10)
);
NAND2X8TS U2898 ( .A(n1490), .B(n1610), .Y(n1153) );
XOR2X4TS U2899 ( .A(n1154), .B(n1635), .Y(n3612) );
NAND2X8TS U2900 ( .A(n1156), .B(n1999), .Y(n1155) );
NAND2X8TS U2901 ( .A(n1542), .B(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[7]), .Y(n1156) );
ADDFHX4TS U2902 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[9]),
.B(n2279), .CI(n2278), .CO(n2293), .S(n2289) );
NAND2X6TS U2903 ( .A(n2004), .B(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[3]), .Y(n2005) );
XNOR2X4TS U2904 ( .A(n1619), .B(n1618), .Y(n1158) );
NOR2X6TS U2905 ( .A(n1520), .B(n2908), .Y(n2879) );
NAND3X8TS U2906 ( .A(n882), .B(n1160), .C(n4110), .Y(n1159) );
INVX4TS U2907 ( .A(Sgf_operation_EVEN1_Q_left[13]), .Y(n2629) );
NAND2X4TS U2908 ( .A(n2559), .B(n2558), .Y(n2562) );
NAND2X8TS U2909 ( .A(n1161), .B(n2231), .Y(n1190) );
NAND3X8TS U2910 ( .A(n1464), .B(n1462), .C(n1463), .Y(n1381) );
INVX8TS U2911 ( .A(n3627), .Y(n1821) );
AOI2BB2X4TS U2912 ( .B0(n3932), .B1(n3922), .A0N(n3930), .A1N(n4398), .Y(
n4554) );
OAI2BB2X4TS U2913 ( .B0(n1141), .B1(n2960), .A0N(n2872), .A1N(n1301), .Y(
n2921) );
INVX8TS U2914 ( .A(n1229), .Y(n1547) );
INVX8TS U2915 ( .A(n1216), .Y(n3601) );
BUFX6TS U2916 ( .A(DP_OP_155J21_124_2814_n125), .Y(n1162) );
NAND2X8TS U2917 ( .A(n2377), .B(n1166), .Y(n1195) );
NAND3X8TS U2918 ( .A(n1169), .B(n1173), .C(n1171), .Y(n1242) );
NAND2X4TS U2919 ( .A(n2236), .B(n2235), .Y(n2263) );
NOR2X8TS U2920 ( .A(n2291), .B(n2290), .Y(n2380) );
INVX8TS U2921 ( .A(n1239), .Y(n2282) );
NAND2X8TS U2922 ( .A(n1164), .B(n3628), .Y(n2607) );
NAND2X4TS U2923 ( .A(n1165), .B(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[4]), .Y(n2027) );
XNOR2X4TS U2924 ( .A(n1737), .B(n1790), .Y(n1165) );
NAND2X8TS U2925 ( .A(n1170), .B(n1942), .Y(n1963) );
OR2X8TS U2926 ( .A(n1943), .B(n1948), .Y(n1170) );
NOR2X8TS U2927 ( .A(DP_OP_155J21_124_2814_n125), .B(
DP_OP_155J21_124_2814_n124), .Y(n1943) );
AOI2BB1X4TS U2928 ( .A0N(n1961), .A1N(n1962), .B0(n1172), .Y(n1171) );
NOR2X8TS U2929 ( .A(DP_OP_155J21_124_2814_n121), .B(
DP_OP_155J21_124_2814_n120), .Y(n1962) );
NOR2X6TS U2930 ( .A(n1178), .B(n1471), .Y(n2156) );
NAND2X8TS U2931 ( .A(n1632), .B(n1182), .Y(n1177) );
NOR2X8TS U2932 ( .A(n2177), .B(n1179), .Y(n1178) );
NAND2X8TS U2933 ( .A(n1245), .B(n1970), .Y(n1632) );
AOI22X4TS U2934 ( .A0(n1183), .A1(n1166), .B0(n1472), .B1(n2510), .Y(n1791)
);
NAND2X8TS U2935 ( .A(n871), .B(n2242), .Y(n2385) );
NOR2X8TS U2936 ( .A(n1185), .B(n1184), .Y(n3876) );
NAND2X8TS U2937 ( .A(n1186), .B(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[6]), .Y(n2165) );
XNOR2X4TS U2938 ( .A(n1189), .B(DP_OP_155J21_124_2814_n144), .Y(n1186) );
NOR2X8TS U2939 ( .A(n2614), .B(n3617), .Y(add_x_19_n246) );
NOR2X8TS U2940 ( .A(n2836), .B(n1443), .Y(n3617) );
XOR2X4TS U2941 ( .A(n2564), .B(n1203), .Y(n2836) );
NOR2X8TS U2942 ( .A(n3029), .B(n3030), .Y(n2614) );
XNOR2X4TS U2943 ( .A(n2382), .B(n1310), .Y(n3029) );
AOI21X4TS U2944 ( .A0(n2239), .A1(n2240), .B0(n1187), .Y(n2265) );
OAI21X4TS U2945 ( .A0(n2170), .A1(n2171), .B0(n2169), .Y(n2239) );
NAND2X8TS U2946 ( .A(DP_OP_155J21_124_2814_n94), .B(
DP_OP_155J21_124_2814_n97), .Y(n1189) );
NOR2X8TS U2947 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[0]),
.B(DP_OP_153J21_122_3500_n127), .Y(n1625) );
NAND2X8TS U2948 ( .A(DP_OP_153J21_122_3500_n195), .B(
DP_OP_153J21_122_3500_n243), .Y(n2159) );
NAND3X8TS U2949 ( .A(n1192), .B(n1191), .C(n911), .Y(n1539) );
NAND2X8TS U2950 ( .A(n1193), .B(n2383), .Y(n1192) );
OR2X8TS U2951 ( .A(n2265), .B(n2264), .Y(n1196) );
NAND3X8TS U2952 ( .A(n1513), .B(n2564), .C(n909), .Y(n1725) );
XNOR2X4TS U2953 ( .A(n1802), .B(n2312), .Y(n1197) );
NAND3X8TS U2954 ( .A(n1199), .B(n2381), .C(n1198), .Y(n2564) );
OR2X8TS U2955 ( .A(n2380), .B(n2378), .Y(n1198) );
NOR2X8TS U2956 ( .A(n2316), .B(n1593), .Y(n2563) );
XOR2X4TS U2957 ( .A(n1202), .B(n1201), .Y(n1744) );
XOR2X4TS U2958 ( .A(n1559), .B(n2302), .Y(n1203) );
NAND2X4TS U2959 ( .A(n2291), .B(n2290), .Y(n2381) );
XOR2X4TS U2960 ( .A(DP_OP_158J21_127_356_n1053), .B(
DP_OP_158J21_127_356_n642), .Y(n1204) );
OAI21X4TS U2961 ( .A0(net288798), .A1(net292233), .B0(net292232), .Y(n2475)
);
XOR2X4TS U2962 ( .A(n1207), .B(n1506), .Y(n2509) );
OAI22X1TS U2963 ( .A0(n2633), .A1(n1221), .B0(n2442), .B1(n3346), .Y(n2638)
);
OAI22X1TS U2964 ( .A0(n2633), .A1(n3346), .B0(n3302), .B1(n1221), .Y(n3301)
);
OAI22X1TS U2965 ( .A0(n3347), .A1(n1221), .B0(n3302), .B1(n3346), .Y(n3345)
);
NAND2X8TS U2966 ( .A(n1221), .B(n2328), .Y(n3346) );
INVX16TS U2967 ( .A(n1226), .Y(n1221) );
NAND2X4TS U2968 ( .A(n1568), .B(n3339), .Y(DP_OP_158J21_127_356_n6) );
AND2X8TS U2969 ( .A(DP_OP_158J21_127_356_n53), .B(n1671), .Y(
DP_OP_158J21_127_356_n44) );
NAND2X4TS U2970 ( .A(n2852), .B(DP_OP_158J21_127_356_n53), .Y(
DP_OP_158J21_127_356_n37) );
NOR2X8TS U2971 ( .A(n1218), .B(n2817), .Y(DP_OP_158J21_127_356_n53) );
NAND2X4TS U2972 ( .A(DP_OP_158J21_127_356_n1056), .B(
DP_OP_158J21_127_356_n656), .Y(n2330) );
INVX12TS U2973 ( .A(n1213), .Y(n1546) );
XOR2X4TS U2974 ( .A(n1295), .B(DP_OP_157J21_126_5719_n229), .Y(n1213) );
NAND2X4TS U2975 ( .A(n2696), .B(n2697), .Y(n3375) );
NOR2X8TS U2976 ( .A(n2847), .B(n2848), .Y(n1217) );
XNOR2X4TS U2977 ( .A(n2706), .B(n2722), .Y(n2714) );
XOR2X4TS U2978 ( .A(n1023), .B(n2706), .Y(n2675) );
XOR2X4TS U2979 ( .A(n2731), .B(n2715), .Y(n2707) );
XOR2X4TS U2980 ( .A(n2719), .B(n2715), .Y(n2669) );
INVX12TS U2981 ( .A(n2706), .Y(n2715) );
AND2X8TS U2982 ( .A(n1228), .B(n1227), .Y(n2368) );
XOR2X4TS U2983 ( .A(n1228), .B(n1227), .Y(n2809) );
OAI22X4TS U2984 ( .A0(n2359), .A1(n3346), .B0(n2358), .B1(n1221), .Y(n1228)
);
XNOR2X4TS U2985 ( .A(n442), .B(n2770), .Y(n2358) );
XOR2X4TS U2986 ( .A(DP_OP_158J21_127_356_n398), .B(n1673), .Y(n2770) );
XNOR2X4TS U2987 ( .A(n2327), .B(n1072), .Y(n1226) );
XOR2X4TS U2988 ( .A(n2660), .B(DP_OP_158J21_127_356_n608), .Y(n1654) );
XOR2X4TS U2989 ( .A(n1547), .B(n1230), .Y(n2539) );
XOR2X4TS U2990 ( .A(n2524), .B(n1523), .Y(n1230) );
XNOR2X4TS U2991 ( .A(n1231), .B(n2026), .Y(n2524) );
XNOR2X4TS U2992 ( .A(n1076), .B(n1233), .Y(n1229) );
INVX12TS U2993 ( .A(n1236), .Y(n2209) );
NAND2X8TS U2994 ( .A(n2283), .B(n2280), .Y(n1241) );
AOI21X4TS U2995 ( .A0(add_x_19_n265), .A1(n3606), .B0(n3031), .Y(
add_x_19_n252) );
NAND2X8TS U2996 ( .A(n1518), .B(n3619), .Y(add_x_19_n265) );
NAND2X8TS U2997 ( .A(n1965), .B(n875), .Y(n1244) );
NAND2X8TS U2998 ( .A(n1965), .B(n929), .Y(n1245) );
NAND2X8TS U2999 ( .A(n1257), .B(n1256), .Y(n1965) );
NAND2X8TS U3000 ( .A(n1777), .B(n2243), .Y(n3608) );
NAND2X8TS U3001 ( .A(n1248), .B(n1252), .Y(n3033) );
NOR2X8TS U3002 ( .A(n1255), .B(n2384), .Y(n1249) );
NOR2X8TS U3003 ( .A(n2173), .B(n1251), .Y(n1250) );
NAND2X8TS U3004 ( .A(n1254), .B(n1586), .Y(n1251) );
XOR2X4TS U3005 ( .A(n1260), .B(n2663), .Y(n1259) );
XOR2X4TS U3006 ( .A(DP_OP_158J21_127_356_n1045), .B(n2662), .Y(n2663) );
XNOR2X4TS U3007 ( .A(n1773), .B(n1263), .Y(n1262) );
NAND2X4TS U3008 ( .A(n2202), .B(n2217), .Y(n2842) );
OAI21X4TS U3009 ( .A0(n1265), .A1(DP_OP_154J21_123_2814_n84), .B0(n1920),
.Y(n1410) );
NAND2X2TS U3010 ( .A(n1265), .B(n1603), .Y(n1914) );
INVX2TS U3011 ( .A(n2389), .Y(n1266) );
NAND2X8TS U3012 ( .A(n2005), .B(n2006), .Y(n1267) );
NAND2BX4TS U3013 ( .AN(Exp_module_Data_S[8]), .B(n923), .Y(n4586) );
XOR2X4TS U3014 ( .A(n3829), .B(n2107), .Y(n3822) );
XOR2X4TS U3015 ( .A(n1270), .B(n2054), .Y(Exp_module_Data_S[5]) );
XOR2X4TS U3016 ( .A(n1271), .B(n2060), .Y(Exp_module_Data_S[4]) );
XOR2X4TS U3017 ( .A(n1272), .B(n2071), .Y(Exp_module_Data_S[6]) );
XOR2X4TS U3018 ( .A(n2093), .B(n2096), .Y(n3853) );
XOR2X4TS U3019 ( .A(n2086), .B(n2085), .Y(Exp_module_Data_S[8]) );
AOI21X4TS U3020 ( .A0(n1284), .A1(n2148), .B0(n2147), .Y(n2170) );
OR2X8TS U3021 ( .A(n2181), .B(n1275), .Y(n1274) );
NOR2BX4TS U3022 ( .AN(n2204), .B(n1281), .Y(n1280) );
OAI2BB1X4TS U3023 ( .A0N(n1283), .A1N(n1282), .B0(n2210), .Y(n2205) );
NAND2X8TS U3024 ( .A(n1286), .B(n1285), .Y(n1983) );
NOR2X8TS U3025 ( .A(n2838), .B(FS_Module_state_reg[1]), .Y(n3856) );
NAND2X8TS U3026 ( .A(n1289), .B(n1288), .Y(n1853) );
NAND2X8TS U3027 ( .A(n4492), .B(n4491), .Y(n1289) );
NOR2X8TS U3028 ( .A(n4393), .B(FS_Module_state_reg[3]), .Y(n3635) );
NOR2X8TS U3029 ( .A(n1290), .B(n2040), .Y(n2095) );
XOR2X4TS U3030 ( .A(n3830), .B(n2035), .Y(n1290) );
OAI2BB1X4TS U3031 ( .A0N(n2508), .A1N(n1291), .B0(n1292), .Y(n4132) );
OAI21X4TS U3032 ( .A0(n1291), .A1(n2508), .B0(net288731), .Y(n1292) );
XOR2X4TS U3033 ( .A(n1291), .B(n1293), .Y(n4133) );
AND2X8TS U3034 ( .A(n2487), .B(n1294), .Y(n2484) );
XOR2X4TS U3035 ( .A(n2487), .B(n1294), .Y(n2489) );
OAI22X4TS U3036 ( .A0(n2488), .A1(net292233), .B0(n2477), .B1(net288778),
.Y(n1294) );
NAND2X8TS U3037 ( .A(n2870), .B(n1062), .Y(n1296) );
NAND2X8TS U3038 ( .A(n3407), .B(n3408), .Y(n1299) );
OAI21X4TS U3039 ( .A0(n3410), .A1(n3426), .B0(n3411), .Y(n3408) );
NAND2X8TS U3040 ( .A(n1300), .B(net291992), .Y(n3407) );
OAI22X4TS U3041 ( .A0(n2948), .A1(Op_MX[17]), .B0(n1852), .B1(n1546), .Y(
n2950) );
INVX16TS U3042 ( .A(net291299), .Y(net287909) );
XOR2X4TS U3043 ( .A(n1508), .B(n2234), .Y(n2268) );
OAI22X4TS U3044 ( .A0(n1054), .A1(n2947), .B0(n1546), .B1(n2899), .Y(n2918)
);
OAI22X4TS U3045 ( .A0(n1054), .A1(n2908), .B0(n1307), .B1(n3567), .Y(n2910)
);
XOR2X4TS U3046 ( .A(Sgf_operation_EVEN1_Q_left[23]), .B(n1712), .Y(n3011) );
OAI22X4TS U3047 ( .A0(net288241), .A1(net288745), .B0(n635), .B1(net288798),
.Y(net291949) );
XOR2X4TS U3048 ( .A(n1308), .B(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[0]), .Y(n1542) );
NAND2X8TS U3049 ( .A(n2159), .B(n1309), .Y(n1308) );
XOR2X4TS U3050 ( .A(n1791), .B(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[10]), .Y(n2856) );
OAI21X4TS U3051 ( .A0(n1779), .A1(n1558), .B0(n2378), .Y(n1310) );
OAI22X4TS U3052 ( .A0(n2716), .A1(n2682), .B0(n461), .B1(n1311), .Y(n2690)
);
OAI22X4TS U3053 ( .A0(n2716), .A1(n1311), .B0(n2675), .B1(n461), .Y(n2687)
);
XOR2X4TS U3054 ( .A(n2704), .B(n2715), .Y(n1311) );
XOR2X4TS U3055 ( .A(n1313), .B(n1312), .Y(n2705) );
OAI21X4TS U3056 ( .A0(DP_OP_158J21_127_356_n707), .A1(
DP_OP_158J21_127_356_n405), .B0(n2654), .Y(n1312) );
MXI2X8TS U3057 ( .A(n1321), .B(n879), .S0(net287652), .Y(n312) );
AOI21X4TS U3058 ( .A0(n3315), .A1(n3314), .B0(n3276), .Y(n1322) );
NAND2X8TS U3059 ( .A(n3846), .B(n1330), .Y(net286913) );
OR2X8TS U3060 ( .A(n4500), .B(n323), .Y(n4060) );
XNOR2X4TS U3061 ( .A(n1738), .B(n3313), .Y(n4500) );
XNOR2X4TS U3062 ( .A(n1331), .B(n3392), .Y(n4481) );
XNOR2X4TS U3063 ( .A(n2793), .B(n3071), .Y(n1692) );
XNOR2X4TS U3064 ( .A(n3362), .B(n2793), .Y(n2354) );
AND2X8TS U3065 ( .A(n1952), .B(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[9]), .Y(n2280) );
XOR2X4TS U3066 ( .A(DP_OP_158J21_127_356_n645), .B(DP_OP_158J21_127_356_n646), .Y(n1335) );
XOR2X4TS U3067 ( .A(DP_OP_158J21_127_356_n1050), .B(
DP_OP_158J21_127_356_n648), .Y(n1337) );
NAND2X8TS U3068 ( .A(n2245), .B(n1341), .Y(n2224) );
XOR2X4TS U3069 ( .A(n1347), .B(n1342), .Y(n2015) );
NOR2X8TS U3070 ( .A(n1344), .B(n1494), .Y(n2399) );
NOR2X8TS U3071 ( .A(n1346), .B(n1345), .Y(n1344) );
NAND4X8TS U3072 ( .A(n1034), .B(n1461), .C(n1463), .D(n1462), .Y(n1460) );
OAI22X2TS U3073 ( .A0(n721), .A1(n2961), .B0(n2948), .B1(n2967), .Y(n2943)
);
XOR2X4TS U3074 ( .A(n1355), .B(n4349), .Y(n1354) );
OAI21X4TS U3075 ( .A0(n1117), .A1(n3790), .B0(n3789), .Y(n1355) );
OAI21X4TS U3076 ( .A0(n3599), .A1(n1356), .B0(n2835), .Y(
DP_OP_156J21_125_3370_n83) );
OAI21X4TS U3077 ( .A0(n2305), .A1(n2303), .B0(n2306), .Y(n1357) );
OAI22X4TS U3078 ( .A0(net291396), .A1(n2488), .B0(n2477), .B1(net292233),
.Y(n2486) );
NAND2X8TS U3079 ( .A(n1359), .B(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[7]), .Y(n1358) );
XOR2X4TS U3080 ( .A(n1361), .B(DP_OP_154J21_123_2814_n93), .Y(n2111) );
OAI21X4TS U3081 ( .A0(n1414), .A1(n2871), .B0(n1363), .Y(n1384) );
NOR2X8TS U3082 ( .A(Op_MY[4]), .B(Op_MY[10]), .Y(net288847) );
NOR2X8TS U3083 ( .A(n1365), .B(n1364), .Y(net288841) );
NOR2X8TS U3084 ( .A(DP_OP_159J21_128_5719_n248), .B(
DP_OP_159J21_128_5719_n256), .Y(n1364) );
NAND2X8TS U3085 ( .A(net291835), .B(DP_OP_159J21_128_5719_n249), .Y(n1365)
);
NAND2X8TS U3086 ( .A(n1366), .B(n887), .Y(n1764) );
OAI21X4TS U3087 ( .A0(n3591), .A1(n3594), .B0(n3592), .Y(n3587) );
OR2X8TS U3088 ( .A(n2913), .B(n2912), .Y(n3586) );
OR2X8TS U3089 ( .A(n2928), .B(n2927), .Y(n3581) );
NOR2X2TS U3090 ( .A(n1373), .B(n1374), .Y(n1694) );
INVX2TS U3091 ( .A(n2985), .Y(n1373) );
OAI2BB1X4TS U3092 ( .A0N(n1522), .A1N(n1521), .B0(n3614), .Y(n1375) );
OAI2BB1X4TS U3093 ( .A0N(n1379), .A1N(net291787), .B0(net287491), .Y(n1378)
);
XOR2X4TS U3094 ( .A(net287491), .B(n1380), .Y(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N10)
);
NAND2X8TS U3095 ( .A(n1381), .B(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[4]), .Y(n1425) );
INVX12TS U3096 ( .A(n1384), .Y(n1520) );
OAI22X4TS U3097 ( .A0(n1383), .A1(n2899), .B0(n2947), .B1(n1340), .Y(n2945)
);
OAI21X4TS U3098 ( .A0(n1385), .A1(n2074), .B0(n2073), .Y(n2075) );
NAND2X8TS U3099 ( .A(n3851), .B(n895), .Y(n2066) );
OAI21X4TS U3100 ( .A0(n1387), .A1(n440), .B0(n1386), .Y(n271) );
XOR2X4TS U3101 ( .A(n1388), .B(n3831), .Y(n1387) );
OAI21X4TS U3102 ( .A0(n1390), .A1(n3824), .B0(n1389), .Y(n1388) );
INVX2TS U3103 ( .A(n3829), .Y(n1390) );
OAI2BB1X4TS U3104 ( .A0N(n1523), .A1N(n2524), .B0(n1393), .Y(n2543) );
NOR2X8TS U3105 ( .A(n1400), .B(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[7]), .Y(n2162) );
NAND3X8TS U3106 ( .A(n1396), .B(n1395), .C(n1394), .Y(n1400) );
NAND2X8TS U3107 ( .A(n1397), .B(n1398), .Y(n1394) );
NAND3X4TS U3108 ( .A(n1946), .B(DP_OP_155J21_124_2814_n92), .C(
DP_OP_155J21_124_2814_n93), .Y(n1395) );
NAND2X6TS U3109 ( .A(n1399), .B(n1398), .Y(n1396) );
INVX8TS U3110 ( .A(DP_OP_155J21_124_2814_n93), .Y(n1398) );
INVX6TS U3111 ( .A(n1946), .Y(n1399) );
OAI21X4TS U3112 ( .A0(n2162), .A1(n2165), .B0(n2163), .Y(n2233) );
NAND2X4TS U3113 ( .A(n1400), .B(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[7]), .Y(n2163) );
OAI21X4TS U3114 ( .A0(n862), .A1(n1061), .B0(n2881), .Y(n1401) );
NAND2X8TS U3115 ( .A(n1404), .B(n1403), .Y(n2955) );
XNOR2X4TS U3116 ( .A(n2944), .B(n1405), .Y(n2951) );
XOR2X4TS U3117 ( .A(n2945), .B(n1406), .Y(n1405) );
AOI2BB2X4TS U3118 ( .B0(n2879), .B1(n1408), .A0N(n1407), .A1N(n1409), .Y(
n1406) );
AND3X8TS U3119 ( .A(n1603), .B(n1200), .C(DP_OP_154J21_123_2814_n90), .Y(
n1411) );
NAND2X8TS U3120 ( .A(n3925), .B(n3915), .Y(n1417) );
NAND2X8TS U3121 ( .A(n1418), .B(n4527), .Y(n3925) );
NAND2X8TS U3122 ( .A(n1827), .B(n828), .Y(n1420) );
NAND2X8TS U3123 ( .A(n1427), .B(n1639), .Y(n3786) );
XNOR2X4TS U3124 ( .A(n1428), .B(n1864), .Y(n1535) );
XOR2X4TS U3125 ( .A(n1755), .B(n1432), .Y(Sgf_operation_EVEN1_S_B[14]) );
NOR2BX4TS U3126 ( .AN(n1235), .B(n2216), .Y(n3721) );
NAND2BX4TS U3127 ( .AN(n1235), .B(n2216), .Y(n3722) );
XNOR2X4TS U3128 ( .A(n1545), .B(n2757), .Y(n2360) );
XNOR2X4TS U3129 ( .A(n1545), .B(n2774), .Y(n2790) );
XNOR2X4TS U3130 ( .A(n1545), .B(n2793), .Y(n2804) );
AOI2BB1X4TS U3131 ( .A0N(n2534), .A1N(n2529), .B0(n1440), .Y(n1439) );
OAI21X4TS U3132 ( .A0(n2018), .A1(n2017), .B0(n2016), .Y(n2528) );
XNOR2X4TS U3133 ( .A(n1710), .B(n1999), .Y(n1996) );
NOR2X8TS U3134 ( .A(n2534), .B(n2530), .Y(n2417) );
NOR2X8TS U3135 ( .A(n2416), .B(n2415), .Y(n2534) );
INVX12TS U3136 ( .A(Sgf_operation_EVEN1_result_A_adder[4]), .Y(n3177) );
INVX12TS U3137 ( .A(Sgf_operation_EVEN1_result_B_adder[2]), .Y(n3108) );
NAND2X8TS U3138 ( .A(n3193), .B(n3192), .Y(n3227) );
XOR2X4TS U3139 ( .A(n1444), .B(n2547), .Y(n2859) );
AOI21X4TS U3140 ( .A0(n2545), .A1(n1163), .B0(n1711), .Y(n1444) );
XOR2X4TS U3141 ( .A(n2274), .B(n1446), .Y(n2279) );
INVX2TS U3142 ( .A(n1772), .Y(DP_OP_158J21_127_356_n56) );
AOI21X4TS U3143 ( .A0(n1772), .A1(n2852), .B0(n2851), .Y(
DP_OP_158J21_127_356_n38) );
NAND2X8TS U3144 ( .A(n1771), .B(n3339), .Y(n1772) );
NOR2X8TS U3145 ( .A(DP_OP_158J21_127_356_n651), .B(
Sgf_operation_EVEN1_result_A_adder[5]), .Y(n1449) );
INVX12TS U3146 ( .A(n1450), .Y(DP_OP_158J21_127_356_n63) );
NAND2X1TS U3147 ( .A(DP_OP_158J21_127_356_n62), .B(n1450), .Y(
DP_OP_158J21_127_356_n7) );
NAND2X8TS U3148 ( .A(n2819), .B(n2818), .Y(n1450) );
INVX3TS U3149 ( .A(DP_OP_156J21_125_3370_n83), .Y(DP_OP_156J21_125_3370_n85)
);
OAI22X4TS U3150 ( .A0(n2802), .A1(n1451), .B0(n2354), .B1(n1090), .Y(n2362)
);
XOR2X4TS U3151 ( .A(n3348), .B(n1452), .Y(n1451) );
INVX2TS U3152 ( .A(DP_OP_155J21_124_2814_n90), .Y(n1950) );
AOI21X4TS U3153 ( .A0(n2446), .A1(n1889), .B0(n1888), .Y(n1455) );
XNOR2X4TS U3154 ( .A(n1459), .B(n4352), .Y(n1458) );
XNOR2X4TS U3155 ( .A(n2262), .B(n2261), .Y(Sgf_operation_EVEN1_Q_left[12])
);
AOI21X4TS U3156 ( .A0(n1551), .A1(n1602), .B0(n1930), .Y(n1912) );
NOR2X8TS U3157 ( .A(n2800), .B(n2799), .Y(n1473) );
NAND2X8TS U3158 ( .A(n1768), .B(n1767), .Y(n3371) );
NOR2X8TS U3159 ( .A(n2554), .B(n2555), .Y(DP_OP_158J21_127_356_n46) );
XOR2X4TS U3160 ( .A(n1475), .B(n4354), .Y(n1474) );
NAND2X2TS U3161 ( .A(n1478), .B(n3606), .Y(add_x_19_n251) );
OAI2BB1X4TS U3162 ( .A0N(n1478), .A1N(add_x_19_n272), .B0(n2443), .Y(
add_x_19_n257) );
NOR2X8TS U3163 ( .A(n3618), .B(n3607), .Y(n1478) );
XOR2X4TS U3164 ( .A(n3228), .B(n1479), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N9)
);
XNOR2X4TS U3165 ( .A(n1545), .B(n442), .Y(n2633) );
XOR2X4TS U3166 ( .A(n1484), .B(n1483), .Y(n1482) );
OAI21X4TS U3167 ( .A0(n1773), .A1(n2344), .B0(n2346), .Y(n1484) );
NAND2X8TS U3168 ( .A(n3780), .B(n1485), .Y(n2645) );
INVX12TS U3169 ( .A(Sgf_operation_EVEN1_result_B_adder[0]), .Y(n3247) );
INVX12TS U3170 ( .A(Sgf_operation_EVEN1_result_A_adder[3]), .Y(n3158) );
NAND2X8TS U3171 ( .A(n1498), .B(n2615), .Y(n1755) );
XNOR2X4TS U3172 ( .A(n1500), .B(n3011), .Y(DP_OP_156J21_125_3370_n197) );
XNOR2X4TS U3173 ( .A(n3012), .B(n1744), .Y(n1500) );
NOR2X4TS U3174 ( .A(net288778), .B(net288747), .Y(n2476) );
XNOR2X4TS U3175 ( .A(n3830), .B(n2045), .Y(n1501) );
XNOR2X4TS U3176 ( .A(n1502), .B(n1807), .Y(n1955) );
NAND2X8TS U3177 ( .A(n1592), .B(n1513), .Y(n1505) );
OAI22X4TS U3178 ( .A0(net292476), .A1(net288243), .B0(net291956), .B1(
net288230), .Y(n2504) );
ADDHX4TS U3179 ( .A(Op_MX[15]), .B(Op_MX[21]), .CO(n2873), .S(n2872) );
NAND2X2TS U3180 ( .A(n1965), .B(n1970), .Y(n1966) );
OAI21X4TS U3181 ( .A0(n3228), .A1(n3207), .B0(n3206), .Y(n3212) );
OR2X8TS U3182 ( .A(n1944), .B(n2295), .Y(n1556) );
NOR2BX4TS U3183 ( .AN(n2350), .B(n1762), .Y(n1761) );
OR2X8TS U3184 ( .A(n890), .B(n1691), .Y(n2802) );
CLKBUFX2TS U3185 ( .A(n2233), .Y(n1508) );
INVX4TS U3186 ( .A(n3876), .Y(n2160) );
OAI2BB1X4TS U3187 ( .A0N(n909), .A1N(n2564), .B0(n2613), .Y(n2318) );
NAND2X8TS U3188 ( .A(DP_OP_154J21_123_2814_n126), .B(
DP_OP_154J21_123_2814_n127), .Y(n1910) );
OAI2BB1X4TS U3189 ( .A0N(n1512), .A1N(n1055), .B0(n2962), .Y(n1511) );
XOR2X4TS U3190 ( .A(n1677), .B(n3601), .Y(n3006) );
NAND2X4TS U3191 ( .A(n1955), .B(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[0]), .Y(n2212) );
NOR2X8TS U3192 ( .A(n1992), .B(n1991), .Y(n2621) );
NAND2X4TS U3193 ( .A(n1606), .B(n1605), .Y(n1924) );
XNOR2X4TS U3194 ( .A(n1906), .B(n1905), .Y(n1515) );
OAI2BB1X2TS U3195 ( .A0N(n3037), .A1N(n3038), .B0(n1516), .Y(n3044) );
OAI21X2TS U3196 ( .A0(n3037), .A1(n3038), .B0(n3036), .Y(n1516) );
XOR2X4TS U3197 ( .A(n3038), .B(n3037), .Y(n1517) );
OAI21X4TS U3198 ( .A0(n3598), .A1(DP_OP_156J21_125_3370_n80), .B0(
DP_OP_156J21_125_3370_n73), .Y(DP_OP_156J21_125_3370_n71) );
NOR2X8TS U3199 ( .A(n1955), .B(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[0]), .Y(n1944) );
OR2X8TS U3200 ( .A(n2574), .B(n2573), .Y(n2575) );
NAND2X4TS U3201 ( .A(n1234), .B(n1076), .Y(n1601) );
CLKXOR2X4TS U3202 ( .A(n2241), .B(n2265), .Y(n2243) );
ADDFHX4TS U3203 ( .A(n2905), .B(n2904), .CI(n2903), .CO(n2922), .S(n2913) );
INVX8TS U3204 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[3]), .Y(
n1982) );
NOR2X4TS U3205 ( .A(n3769), .B(n2841), .Y(n2219) );
INVX2TS U3206 ( .A(n2859), .Y(n1521) );
XNOR2X4TS U3207 ( .A(n1524), .B(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[8]), .Y(n3613) );
OAI22X4TS U3208 ( .A0(n1141), .A1(n2909), .B0(n1119), .B1(n2902), .Y(n2906)
);
OAI22X4TS U3209 ( .A0(n2331), .A1(n1220), .B0(n3346), .B1(n2357), .Y(n2352)
);
INVX8TS U3210 ( .A(n1535), .Y(n1890) );
ADDFHX4TS U3211 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[10]),
.B(n2294), .CI(n2293), .CO(n2310), .S(n2301) );
OAI2BB1X4TS U3212 ( .A0N(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[8]), .A1N(n2267),
.B0(n1528), .Y(n2278) );
XNOR2X2TS U3213 ( .A(n1529), .B(n2266), .Y(n2270) );
XNOR2X4TS U3214 ( .A(n2267), .B(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[8]), .Y(n1529) );
OAI21X2TS U3215 ( .A0(n2146), .A1(n2145), .B0(n2144), .Y(n2147) );
XNOR2X4TS U3216 ( .A(n1614), .B(n1957), .Y(n1968) );
INVX8TS U3217 ( .A(n2248), .Y(n1534) );
INVX8TS U3218 ( .A(n2079), .Y(n2090) );
NAND2X2TS U3219 ( .A(n2307), .B(n2306), .Y(n2308) );
NOR2X8TS U3220 ( .A(n1988), .B(n1987), .Y(n2305) );
INVX4TS U3221 ( .A(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N10),
.Y(n4145) );
OAI22X4TS U3222 ( .A0(n3346), .A1(n2358), .B0(n2357), .B1(n1221), .Y(n2369)
);
ADDFHX4TS U3223 ( .A(mult_x_58_n18), .B(mult_x_58_n22), .CI(n2577), .CO(
n3403), .S(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N7)
);
AOI21X2TS U3224 ( .A0(n3214), .A1(n3201), .B0(n3200), .Y(n3202) );
XOR2X4TS U3225 ( .A(n1937), .B(n1936), .Y(add_x_19_n106) );
XOR2X4TS U3226 ( .A(n1628), .B(n2881), .Y(n2895) );
AOI21X4TS U3227 ( .A0(n1738), .A1(n3394), .B0(n3393), .Y(n3398) );
OAI22X4TS U3228 ( .A0(n3305), .A1(n2792), .B0(n1118), .B1(n2791), .Y(n2806)
);
OAI22X4TS U3229 ( .A0(n3305), .A1(n2791), .B0(n1118), .B1(n2371), .Y(n2810)
);
INVX12TS U3230 ( .A(n1594), .Y(n3348) );
ADDFHX4TS U3231 ( .A(mult_x_59_n14), .B(n3552), .CI(n3551), .CO(n3553), .S(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N9)
);
CMPR22X2TS U3232 ( .A(n2950), .B(n2949), .CO(n2957), .S(n2942) );
NAND2X4TS U3233 ( .A(n3672), .B(n1858), .Y(n1860) );
OAI21X4TS U3234 ( .A0(n3656), .A1(n1860), .B0(n1859), .Y(n1861) );
XNOR2X4TS U3235 ( .A(n3220), .B(n3219), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N11)
);
OAI21X4TS U3236 ( .A0(n3779), .A1(n3704), .B0(n3705), .Y(n3702) );
NAND2X6TS U3237 ( .A(n1908), .B(n2257), .Y(n1801) );
NAND3X8TS U3238 ( .A(n1825), .B(n1826), .C(n2608), .Y(n1824) );
NOR2X8TS U3239 ( .A(n2609), .B(n3609), .Y(n1825) );
AOI2BB2X4TS U3240 ( .B0(n251), .B1(n3932), .A0N(n3930), .A1N(n4405), .Y(
n3802) );
INVX12TS U3241 ( .A(n1696), .Y(n3037) );
OAI2BB1X4TS U3242 ( .A0N(n2244), .A1N(add_x_19_n272), .B0(n3608), .Y(
add_x_19_n268) );
NAND2X2TS U3243 ( .A(n1939), .B(n1942), .Y(n1940) );
AOI2BB1X4TS U3244 ( .A0N(n4099), .A1N(n4098), .B0(n1747), .Y(n1746) );
NAND2X4TS U3245 ( .A(n3153), .B(n3152), .Y(n3238) );
OAI22X4TS U3246 ( .A0(n1340), .A1(n2909), .B0(n720), .B1(n2902), .Y(n2896)
);
NOR2X2TS U3247 ( .A(n2590), .B(n2593), .Y(n2596) );
OAI21X4TS U3248 ( .A0(n3228), .A1(n3226), .B0(n3227), .Y(n3225) );
XOR2X4TS U3249 ( .A(n1542), .B(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[7]), .Y(n2230) );
INVX2TS U3250 ( .A(n2315), .Y(n2313) );
NAND2X2TS U3251 ( .A(n446), .B(n2381), .Y(n2382) );
AOI21X4TS U3252 ( .A0(n1602), .A1(n734), .B0(n1205), .Y(n1906) );
INVX4TS U3253 ( .A(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N10),
.Y(n4147) );
AOI21X4TS U3254 ( .A0(n546), .A1(n2644), .B0(n2645), .Y(n3794) );
XNOR2X4TS U3255 ( .A(n2320), .B(DP_OP_158J21_127_356_n607), .Y(n2319) );
XOR2X4TS U3256 ( .A(DP_OP_158J21_127_356_n1048), .B(
DP_OP_158J21_127_356_n297), .Y(n2320) );
ADDFHX2TS U3257 ( .A(n3424), .B(n3423), .CI(net287459), .CO(n4126), .S(n4127) );
NAND2X4TS U3258 ( .A(n3406), .B(n3407), .Y(n3409) );
AOI21X4TS U3259 ( .A0(n3829), .A1(n3823), .B0(n3828), .Y(n2086) );
NOR2X2TS U3260 ( .A(n2664), .B(n2663), .Y(n2665) );
NAND2X4TS U3261 ( .A(n2430), .B(n2429), .Y(DP_OP_156J21_125_3370_n2) );
OAI22X2TS U3262 ( .A0(n635), .A1(n2477), .B0(net287909), .B1(n2488), .Y(
net288815) );
OAI21X4TS U3263 ( .A0(n3779), .A1(n3752), .B0(n3751), .Y(n3756) );
NOR2X2TS U3264 ( .A(n1520), .B(n2947), .Y(n2959) );
OAI2BB1X4TS U3265 ( .A0N(n2986), .A1N(n1756), .B0(n1763), .Y(n2862) );
OAI22X4TS U3266 ( .A0(n874), .A1(Sgf_operation_EVEN1_Q_left[23]), .B0(n1713),
.B1(n2021), .Y(n2519) );
AOI2BB2X4TS U3267 ( .B0(n3929), .B1(n247), .A0N(n1127), .A1N(n4424), .Y(
n3759) );
XOR2X4TS U3268 ( .A(net291323), .B(n908), .Y(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N12) );
AOI21X4TS U3269 ( .A0(n546), .A1(n1638), .B0(n1486), .Y(n3777) );
OAI21X4TS U3270 ( .A0(n3779), .A1(n2448), .B0(n2447), .Y(n2452) );
AOI2BB2X4TS U3271 ( .B0(n250), .B1(n3932), .A0N(n1127), .A1N(n4406), .Y(
n3767) );
INVX8TS U3272 ( .A(DP_OP_155J21_124_2814_n91), .Y(n1946) );
OAI22X4TS U3273 ( .A0(n2802), .A1(n2761), .B0(n2759), .B1(n1090), .Y(n2764)
);
INVX6TS U3274 ( .A(n2785), .Y(n1768) );
OAI21X4TS U3275 ( .A0(n2097), .A1(n2094), .B0(n2098), .Y(n2043) );
OAI21X4TS U3276 ( .A0(n3228), .A1(n3216), .B0(n3215), .Y(n3220) );
XOR2X4TS U3277 ( .A(n3034), .B(n3033), .Y(n1609) );
NAND2X4TS U3278 ( .A(n2574), .B(n2573), .Y(n2615) );
OAI22X4TS U3279 ( .A0(n1773), .A1(n1567), .B0(n872), .B1(n1564), .Y(n3362)
);
XNOR2X4TS U3280 ( .A(DP_OP_158J21_127_356_n895), .B(n1595), .Y(n1562) );
NOR2X8TS U3281 ( .A(n2815), .B(n2814), .Y(n3023) );
NAND3X8TS U3282 ( .A(n1573), .B(n1572), .C(n3355), .Y(n3021) );
XOR2X4TS U3283 ( .A(n2853), .B(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[7]), .Y(n1578) );
NOR2X8TS U3284 ( .A(n1582), .B(n2517), .Y(n1581) );
NOR2X8TS U3285 ( .A(n2863), .B(n2864), .Y(n1633) );
OAI22X4TS U3286 ( .A0(n1141), .A1(n2967), .B0(n1546), .B1(n2961), .Y(n2882)
);
OAI21X4TS U3287 ( .A0(n819), .A1(n1871), .B0(n800), .Y(n1873) );
XOR2X4TS U3288 ( .A(n1591), .B(DP_OP_158J21_127_356_n609), .Y(n1590) );
XNOR2X4TS U3289 ( .A(DP_OP_158J21_127_356_n607), .B(
DP_OP_158J21_127_356_n612), .Y(n1587) );
NAND2X8TS U3290 ( .A(n1568), .B(DP_OP_158J21_127_356_n63), .Y(n1771) );
XNOR2X4TS U3291 ( .A(n1596), .B(n1563), .Y(n1594) );
OAI21X4TS U3292 ( .A0(n1773), .A1(n922), .B0(n872), .Y(n1596) );
XNOR2X4TS U3293 ( .A(n1242), .B(n1599), .Y(n1700) );
XOR2X4TS U3294 ( .A(n3614), .B(n1604), .Y(n3036) );
XOR2X4TS U3295 ( .A(n2859), .B(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[5]), .Y(n1604) );
OAI21X4TS U3296 ( .A0(n1688), .A1(n1792), .B0(n1679), .Y(n1606) );
OAI2BB1X4TS U3297 ( .A0N(n1519), .A1N(n3035), .B0(n1608), .Y(
DP_OP_156J21_125_3370_n208) );
OAI21X4TS U3298 ( .A0(n1519), .A1(n3035), .B0(n3033), .Y(n1608) );
INVX8TS U3299 ( .A(n2399), .Y(n1610) );
NAND3X6TS U3300 ( .A(n1616), .B(n1615), .C(n1961), .Y(n1614) );
NAND2BX4TS U3301 ( .AN(n1958), .B(n1963), .Y(n1615) );
AOI21X4TS U3302 ( .A0(n562), .A1(n1933), .B0(n1067), .Y(n1619) );
XOR2X4TS U3303 ( .A(n1828), .B(n2882), .Y(n1628) );
NOR2X8TS U3304 ( .A(n2305), .B(n1525), .Y(n2618) );
CLKINVX12TS U3305 ( .A(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[10]),
.Y(n2012) );
OAI22X4TS U3306 ( .A0(net288778), .A1(net288242), .B0(net288747), .B1(
net292233), .Y(n2473) );
NAND4X8TS U3307 ( .A(n1643), .B(n1642), .C(n930), .D(n1646), .Y(n1639) );
NAND3X4TS U3308 ( .A(n1643), .B(n1642), .C(n1646), .Y(n1891) );
INVX12TS U3309 ( .A(n1637), .Y(n2644) );
NAND2X8TS U3310 ( .A(n1638), .B(n1639), .Y(n1637) );
NAND2X4TS U3311 ( .A(n1645), .B(n1835), .Y(n1642) );
OAI2BB1X4TS U3312 ( .A0N(n1663), .A1N(n1650), .B0(n1899), .Y(n1900) );
AND2X8TS U3313 ( .A(n907), .B(n435), .Y(n1650) );
XNOR2X4TS U3314 ( .A(n1651), .B(n2994), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N10)
);
NAND2X8TS U3315 ( .A(n1764), .B(n2996), .Y(n2990) );
XNOR2X4TS U3316 ( .A(n1751), .B(DP_OP_158J21_127_356_n405), .Y(n1656) );
AND2X8TS U3317 ( .A(n1655), .B(n2666), .Y(n1657) );
XNOR2X4TS U3318 ( .A(n1662), .B(n1661), .Y(n1887) );
NAND2BX4TS U3319 ( .AN(n680), .B(n820), .Y(n1661) );
OAI22X4TS U3320 ( .A0(n1546), .A1(Op_MX[17]), .B0(n1852), .B1(n1141), .Y(
n1667) );
XOR2X4TS U3321 ( .A(n1669), .B(n2962), .Y(n2954) );
XOR2X4TS U3322 ( .A(n1670), .B(n2963), .Y(n1669) );
OAI22X4TS U3323 ( .A0(n1340), .A1(n2961), .B0(n2967), .B1(n720), .Y(n1670)
);
NOR2X8TS U3324 ( .A(n2819), .B(n2818), .Y(n2817) );
NOR2X8TS U3325 ( .A(n437), .B(n1672), .Y(n2636) );
OAI22X4TS U3326 ( .A0(n3601), .A1(n1676), .B0(n1678), .B1(n1675), .Y(n3004)
);
XOR2X4TS U3327 ( .A(n2833), .B(n1678), .Y(n1677) );
XOR2X4TS U3328 ( .A(n2011), .B(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[2]), .Y(n1687) );
INVX2TS U3329 ( .A(n3021), .Y(n3024) );
OAI22X4TS U3330 ( .A0(n2802), .A1(n1692), .B0(n2761), .B1(n1089), .Y(n2766)
);
XNOR2X4TS U3331 ( .A(n2793), .B(n2770), .Y(n2761) );
XOR2X4TS U3332 ( .A(n2351), .B(n2348), .Y(n1690) );
XOR2X4TS U3333 ( .A(n1761), .B(n1760), .Y(n1691) );
XNOR2X4TS U3334 ( .A(n2180), .B(n883), .Y(n1696) );
INVX12TS U3335 ( .A(DP_OP_155J21_124_2814_n88), .Y(n1702) );
INVX12TS U3336 ( .A(DP_OP_155J21_124_2814_n87), .Y(n1703) );
XOR2X4TS U3337 ( .A(n1239), .B(n1705), .Y(n3879) );
XOR2X4TS U3338 ( .A(n1742), .B(n2997), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N8)
);
XOR2X4TS U3339 ( .A(n1713), .B(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[9]), .Y(n1712) );
NAND3BX4TS U3340 ( .AN(n2427), .B(n1715), .C(n1714), .Y(n1713) );
XNOR2X4TS U3341 ( .A(n1719), .B(n1718), .Y(Sgf_operation_EVEN1_S_B[15]) );
XOR2X4TS U3342 ( .A(n2744), .B(n1724), .Y(n2742) );
XOR2X4TS U3343 ( .A(n2746), .B(n2745), .Y(n1724) );
NAND2X8TS U3344 ( .A(n2255), .B(n1728), .Y(n1727) );
NAND2X8TS U3345 ( .A(n1731), .B(n1729), .Y(n2255) );
AOI21X4TS U3346 ( .A0(n1922), .A1(n1534), .B0(n1730), .Y(n1729) );
BUFX12TS U3347 ( .A(n860), .Y(n1732) );
XOR2X4TS U3348 ( .A(n1732), .B(n1736), .Y(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N9)
);
AOI21X4TS U3349 ( .A0(n1180), .A1(n2151), .B0(n1632), .Y(n1737) );
OAI21X4TS U3350 ( .A0(n2460), .A1(n2462), .B0(n2463), .Y(n1888) );
AOI21X4TS U3351 ( .A0(n1454), .A1(n1893), .B0(n1892), .Y(n1894) );
OAI21X4TS U3352 ( .A0(n2841), .A1(n3770), .B0(n2842), .Y(n2218) );
XNOR2X4TS U3353 ( .A(n3447), .B(n3446), .Y(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N8)
);
XNOR2X4TS U3354 ( .A(n2678), .B(n2722), .Y(n2659) );
OAI21X4TS U3355 ( .A0(n3314), .A1(n3323), .B0(n3315), .Y(n3280) );
NOR2BX4TS U3356 ( .AN(n3277), .B(n1740), .Y(n1739) );
AOI21X4TS U3357 ( .A0(n1756), .A1(n1743), .B0(n887), .Y(n1742) );
OAI21X4TS U3358 ( .A0(n2579), .A1(n2583), .B0(n2584), .Y(n2591) );
XNOR2X4TS U3359 ( .A(n2410), .B(n2411), .Y(n2419) );
XOR2X4TS U3360 ( .A(n1746), .B(n4040), .Y(n2410) );
XOR2X4TS U3361 ( .A(n505), .B(n1752), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N7)
);
XOR2X4TS U3362 ( .A(n3049), .B(n1748), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N2)
);
OR2X4TS U3363 ( .A(n3069), .B(n441), .Y(n2679) );
XNOR2X4TS U3364 ( .A(n2661), .B(n899), .Y(n1749) );
NOR2X8TS U3365 ( .A(n2995), .B(n3356), .Y(n2986) );
XNOR2X4TS U3366 ( .A(DP_OP_158J21_127_356_n307), .B(
DP_OP_158J21_127_356_n314), .Y(n1760) );
OAI2BB1X4TS U3367 ( .A0N(DP_OP_158J21_127_356_n1048), .A1N(
DP_OP_158J21_127_356_n297), .B0(DP_OP_158J21_127_356_n319), .Y(n2350)
);
XOR2X4TS U3368 ( .A(DP_OP_158J21_127_356_n1049), .B(
DP_OP_158J21_127_356_n648), .Y(n1762) );
NOR2X8TS U3369 ( .A(n2738), .B(n2739), .Y(n2995) );
OR2X8TS U3370 ( .A(n3378), .B(n3381), .Y(n1766) );
AOI21X4TS U3371 ( .A0(n3261), .A1(n3260), .B0(n2781), .Y(n3381) );
OAI22X4TS U3372 ( .A0(n1141), .A1(n2946), .B0(n1119), .B1(n2960), .Y(n2900)
);
INVX12TS U3373 ( .A(n2873), .Y(n2960) );
XOR2X4TS U3374 ( .A(n1775), .B(n863), .Y(n1774) );
XNOR2X4TS U3375 ( .A(n1780), .B(n2755), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N11)
);
NAND3X6TS U3376 ( .A(n1781), .B(n1782), .C(n1783), .Y(n1780) );
OA21X4TS U3377 ( .A0(n2991), .A1(n2987), .B0(n2992), .Y(n1782) );
OAI21X4TS U3378 ( .A0(n1788), .A1(n440), .B0(n1787), .Y(n231) );
XOR2X4TS U3379 ( .A(n1826), .B(n1789), .Y(n1788) );
OAI2BB1X4TS U3380 ( .A0N(n3002), .A1N(n1073), .B0(n1796), .Y(n4307) );
OAI21X4TS U3381 ( .A0(n1798), .A1(n3002), .B0(n3001), .Y(n1796) );
XOR2X4TS U3382 ( .A(n3002), .B(n3001), .Y(n1797) );
OAI22X4TS U3383 ( .A0(n2902), .A1(n1141), .B0(n2909), .B1(n1546), .Y(n2905)
);
INVX12TS U3384 ( .A(n2874), .Y(n2909) );
NAND2X8TS U3385 ( .A(n2253), .B(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[11]), .Y(n1800) );
XOR2X4TS U3386 ( .A(n2315), .B(n2314), .Y(n1802) );
OAI2BB1X4TS U3387 ( .A0N(n1810), .A1N(net290453), .B0(n2829), .Y(n1809) );
XOR2X4TS U3388 ( .A(n1811), .B(n2829), .Y(n2827) );
XNOR2X4TS U3389 ( .A(n1812), .B(net290453), .Y(n1811) );
NOR2BX4TS U3390 ( .AN(net291299), .B(net288745), .Y(n2821) );
XOR2X4TS U3391 ( .A(n1817), .B(n1974), .Y(n2832) );
OAI21X4TS U3392 ( .A0(n944), .A1(n2197), .B0(n1818), .Y(n1817) );
AOI21X4TS U3393 ( .A0(n1969), .A1(n2209), .B0(n1819), .Y(n1818) );
AOI21X4TS U3394 ( .A0(n1180), .A1(n875), .B0(n929), .Y(n1967) );
NAND3X8TS U3395 ( .A(n1824), .B(n1822), .C(n1820), .Y(add_x_19_n272) );
AOI2BB1X4TS U3396 ( .A0N(n3610), .A1N(n2609), .B0(n1823), .Y(n1822) );
NOR2X8TS U3397 ( .A(n2032), .B(n2222), .Y(n3627) );
NOR2X8TS U3398 ( .A(n2220), .B(n2221), .Y(n3626) );
NOR2X8TS U3399 ( .A(n982), .B(n2223), .Y(n3609) );
NAND2X8TS U3400 ( .A(n1833), .B(n4529), .Y(n3923) );
XOR2X4TS U3401 ( .A(n1900), .B(n4353), .Y(n1834) );
AOI21X4TS U3402 ( .A0(n4373), .A1(n4374), .B0(n4375), .Y(n3656) );
CMPR22X2TS U3403 ( .A(n3490), .B(n3489), .CO(n4201), .S(n4202) );
AND2X4TS U3404 ( .A(n1116), .B(n346), .Y(n3490) );
XOR2X4TS U3405 ( .A(n3773), .B(n3772), .Y(n3774) );
NAND2X4TS U3406 ( .A(n2913), .B(n2912), .Y(n3585) );
ADDHX4TS U3407 ( .A(n2884), .B(n2883), .CO(n2881), .S(n2920) );
NOR2X4TS U3408 ( .A(n3568), .B(Op_MX[17]), .Y(n2884) );
ADDFHX4TS U3409 ( .A(mult_x_56_n15), .B(mult_x_56_n17), .CI(n3471), .CO(
n3467), .S(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N8) );
ADDHX4TS U3410 ( .A(n3516), .B(n3515), .CO(n4229), .S(n4230) );
NOR2X2TS U3411 ( .A(n1040), .B(n326), .Y(n4155) );
XNOR2X1TS U3412 ( .A(n1121), .B(n1040), .Y(n4068) );
NAND2X6TS U3413 ( .A(n2555), .B(n2554), .Y(DP_OP_158J21_127_356_n51) );
AND2X4TS U3414 ( .A(n1120), .B(n352), .Y(n4223) );
AOI21X4TS U3415 ( .A0(n3288), .A1(n3287), .B0(n3286), .Y(n3293) );
INVX6TS U3416 ( .A(n3288), .Y(n3322) );
XOR2X2TS U3417 ( .A(n4035), .B(n4499), .Y(n4072) );
ADDFHX2TS U3418 ( .A(n3060), .B(n3059), .CI(n3058), .CO(n4029), .S(n4030) );
AND2X4TS U3419 ( .A(n1098), .B(n352), .Y(n3518) );
ADDFHX2TS U3420 ( .A(n2640), .B(n2639), .CI(n2638), .CO(n3299), .S(n2641) );
OAI21X2TS U3421 ( .A0(n4058), .A1(n4070), .B0(n4056), .Y(n4082) );
XOR2X4TS U3422 ( .A(n3724), .B(n3908), .Y(n3725) );
ADDFHX2TS U3423 ( .A(n3590), .B(n1841), .CI(n3589), .CO(n4289), .S(n4290) );
CMPR22X2TS U3424 ( .A(n3542), .B(n3541), .CO(n3535), .S(n4259) );
NOR2X2TS U3425 ( .A(n4050), .B(n4496), .Y(n4069) );
ADDFHX2TS U3426 ( .A(n353), .B(n365), .CI(n3265), .CO(n4049), .S(n4050) );
XNOR2X4TS U3427 ( .A(n2101), .B(n2100), .Y(n3806) );
NOR2X4TS U3428 ( .A(n3685), .B(n3673), .Y(n3676) );
INVX3TS U3429 ( .A(n3672), .Y(n3685) );
CMPR22X2TS U3430 ( .A(Op_MX[13]), .B(Op_MX[19]), .CO(n2869), .S(n2874) );
AOI21X2TS U3431 ( .A0(n3726), .A1(n3739), .B0(n3738), .Y(n3740) );
AOI21X4TS U3432 ( .A0(n547), .A1(n3788), .B0(n3787), .Y(n3789) );
XOR2X4TS U3433 ( .A(n3630), .B(n3629), .Y(Sgf_operation_Result[17]) );
MX2X6TS U3434 ( .A(Data_MX[5]), .B(Op_MX[5]), .S0(net287633), .Y(n349) );
MX2X6TS U3435 ( .A(Data_MX[17]), .B(Op_MX[17]), .S0(net287641), .Y(n361) );
INVX6TS U3436 ( .A(n3600), .Y(DP_OP_156J21_125_3370_n91) );
NAND2X4TS U3437 ( .A(n363), .B(n351), .Y(n1902) );
AND2X4TS U3438 ( .A(n1098), .B(n351), .Y(n3506) );
AND2X4TS U3439 ( .A(n323), .B(n351), .Y(n3504) );
AND2X4TS U3440 ( .A(n1115), .B(n351), .Y(n3514) );
AND2X4TS U3441 ( .A(n321), .B(n351), .Y(n4224) );
CMPR22X2TS U3442 ( .A(n351), .B(n363), .CO(n3270), .S(n3326) );
OAI21X2TS U3443 ( .A0(n3617), .A1(n3616), .B0(n3615), .Y(add_x_19_n247) );
XNOR2X4TS U3444 ( .A(n2845), .B(n2844), .Y(n2846) );
OAI21X4TS U3445 ( .A0(n3773), .A1(n3769), .B0(n3770), .Y(n2845) );
CMPR22X2TS U3446 ( .A(n3456), .B(n3455), .CO(n3457), .S(n3449) );
AND2X4TS U3447 ( .A(n1040), .B(n362), .Y(n3456) );
CMPR22X2TS U3448 ( .A(n3507), .B(n3506), .CO(n3508), .S(n3500) );
AND2X4TS U3449 ( .A(n1120), .B(n350), .Y(n3507) );
AND2X4TS U3450 ( .A(n411), .B(n363), .Y(n3477) );
AND2X4TS U3451 ( .A(n411), .B(n365), .Y(n3474) );
AND2X4TS U3452 ( .A(n366), .B(n411), .Y(n3469) );
ADDHX1TS U3453 ( .A(n411), .B(n362), .CO(n4183), .S(n4184) );
ADDHX4TS U3454 ( .A(Op_MX[1]), .B(Op_MX[7]), .CO(n2470), .S(n2471) );
ADDFHX4TS U3455 ( .A(n3538), .B(n3537), .CI(n3536), .CO(n4281), .S(n4282) );
AOI21X4TS U3456 ( .A0(n3674), .A1(n1858), .B0(n1857), .Y(n1859) );
OAI21X2TS U3457 ( .A0(n3679), .A1(n3690), .B0(n3680), .Y(n1857) );
ADDFHX2TS U3458 ( .A(n3087), .B(n3086), .CI(n3085), .CO(n3088), .S(n3078) );
ADDFHX4TS U3459 ( .A(n2810), .B(n2809), .CI(n2808), .CO(n3014), .S(n3016) );
NOR2X6TS U3460 ( .A(Sgf_operation_EVEN1_Q_left[0]), .B(n2376), .Y(
add_x_19_n237) );
NAND2X4TS U3461 ( .A(n3804), .B(n3925), .Y(n4560) );
AOI2BB2X2TS U3462 ( .B0(n3927), .B1(n3925), .A0N(n1127), .A1N(n4400), .Y(
n4563) );
MX2X6TS U3463 ( .A(Data_MY[5]), .B(n1065), .S0(net287583), .Y(n317) );
AOI21X4TS U3464 ( .A0(n2255), .A1(n2254), .B0(n2253), .Y(n2259) );
XOR2X4TS U3465 ( .A(n2046), .B(n1124), .Y(n2050) );
AND2X4TS U3466 ( .A(n361), .B(n1113), .Y(n3543) );
AND2X4TS U3467 ( .A(n1113), .B(n359), .Y(n3557) );
AND2X4TS U3468 ( .A(n1113), .B(n360), .Y(n3539) );
AND2X4TS U3469 ( .A(n1113), .B(n357), .Y(n3542) );
ADDHX1TS U3470 ( .A(n1123), .B(n363), .CO(n4189), .S(n4190) );
AND2X4TS U3471 ( .A(n1123), .B(n362), .Y(n3476) );
AND2X4TS U3472 ( .A(n366), .B(n1123), .Y(n3454) );
AND2X4TS U3473 ( .A(n1123), .B(n363), .Y(n3455) );
ADDFHX2TS U3474 ( .A(n3361), .B(n3360), .CI(n3359), .CO(n3368), .S(n3353) );
AND2X4TS U3475 ( .A(n1053), .B(mult_x_56_n57), .Y(mult_x_56_n58) );
AND2X4TS U3476 ( .A(n1087), .B(n360), .Y(n3544) );
AND2X4TS U3477 ( .A(n1087), .B(n356), .Y(n3541) );
AND2X4TS U3478 ( .A(n319), .B(n353), .Y(n3516) );
NOR2X4TS U3479 ( .A(n3388), .B(n3389), .Y(n3394) );
NOR2X6TS U3480 ( .A(n329), .B(n317), .Y(n3389) );
NOR2X4TS U3481 ( .A(n1564), .B(n408), .Y(n3174) );
ADDFHX4TS U3482 ( .A(mult_x_58_n15), .B(mult_x_58_n17), .CI(n3403), .CO(
n3404), .S(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N8)
);
XOR2X1TS U3483 ( .A(n1123), .B(n1098), .Y(n4080) );
OAI21X2TS U3484 ( .A0(n2063), .A1(n2062), .B0(n2074), .Y(n2064) );
NOR2X4TS U3485 ( .A(n1564), .B(n3178), .Y(n3186) );
NOR2X4TS U3486 ( .A(n3102), .B(n3247), .Y(n3075) );
NOR2X4TS U3487 ( .A(n3197), .B(n3196), .Y(n3204) );
AND2X4TS U3488 ( .A(n317), .B(n345), .Y(n3482) );
NAND2X4TS U3489 ( .A(n357), .B(n345), .Y(n3267) );
OAI21X2TS U3490 ( .A0(n3851), .A1(n2037), .B0(n2066), .Y(n2038) );
ADDFHX2TS U3491 ( .A(mult_x_56_n48), .B(mult_x_56_n63), .CI(mult_x_56_n53),
.CO(mult_x_56_n19), .S(mult_x_56_n20) );
NOR2X4TS U3492 ( .A(n3107), .B(n3106), .Y(n3076) );
NOR2X4TS U3493 ( .A(net287495), .B(net288798), .Y(n2487) );
OAI21X2TS U3494 ( .A0(n2096), .A1(n2095), .B0(n2094), .Y(n2101) );
ADDFHX2TS U3495 ( .A(n3181), .B(n3180), .CI(n3179), .CO(n3182), .S(n3171) );
NAND2X4TS U3496 ( .A(n1923), .B(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[9]), .Y(n2247) );
ADDFHX4TS U3497 ( .A(n2439), .B(n2438), .CI(n2437), .CO(n2642), .S(n2433) );
XOR2X4TS U3498 ( .A(net293003), .B(net288736), .Y(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N9)
);
OAI22X4TS U3499 ( .A0(n2802), .A1(n1452), .B0(n1089), .B1(n2760), .Y(n2767)
);
NOR2X2TS U3500 ( .A(n3965), .B(n3813), .Y(n3814) );
OAI21X2TS U3501 ( .A0(n3285), .A1(n3319), .B0(n3284), .Y(n3286) );
NAND2X4TS U3502 ( .A(n358), .B(n346), .Y(n3319) );
OAI21X4TS U3503 ( .A0(add_x_19_n282), .A1(n3609), .B0(n3610), .Y(n2612) );
ADDFHX2TS U3504 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[4]),
.B(n3872), .CI(n2132), .CO(n2133), .S(n2128) );
AOI21X4TS U3505 ( .A0(n3935), .A1(n3811), .B0(n3810), .Y(n3940) );
OAI21X2TS U3506 ( .A0(n3933), .A1(n4411), .B0(n3808), .Y(n3935) );
NOR2X4TS U3507 ( .A(n2048), .B(n2047), .Y(n2087) );
OAI21X4TS U3508 ( .A0(n3386), .A1(n3383), .B0(n3384), .Y(n3377) );
XNOR2X2TS U3509 ( .A(n4495), .B(n355), .Y(n4071) );
NAND2X2TS U3510 ( .A(n2489), .B(net288777), .Y(n3411) );
XNOR2X4TS U3511 ( .A(n4500), .B(n323), .Y(n4054) );
OR2X8TS U3512 ( .A(n2428), .B(n2408), .Y(n2430) );
ADDHX4TS U3513 ( .A(n2898), .B(n2897), .CO(n2923), .S(n2904) );
OAI21X2TS U3514 ( .A0(n4054), .A1(n4036), .B0(n4037), .Y(n4083) );
ADDFHX2TS U3515 ( .A(n322), .B(n334), .CI(DP_OP_158J21_127_356_n986), .CO(
n4036), .S(n4037) );
OAI22X2TS U3516 ( .A0(n1340), .A1(n2908), .B0(n1383), .B1(n3567), .Y(n2891)
);
XNOR2X4TS U3517 ( .A(n3348), .B(n442), .Y(n3302) );
OAI2BB1X4TS U3518 ( .A0N(n828), .A1N(n3797), .B0(n4530), .Y(n3931) );
NAND2X2TS U3519 ( .A(n3586), .B(n3585), .Y(n3588) );
ADDFHX4TS U3520 ( .A(n3100), .B(n3099), .CI(n3098), .CO(n3161), .S(n3115) );
CMPR22X2TS U3521 ( .A(n3097), .B(n3096), .CO(n3100), .S(n3112) );
NAND2X6TS U3522 ( .A(n3065), .B(n3064), .Y(n3066) );
OAI22X4TS U3523 ( .A0(n2776), .A1(n1042), .B0(n2775), .B1(n1543), .Y(n3064)
);
CMPR22X2TS U3524 ( .A(n319), .B(n1122), .CO(n3248), .S(n4032) );
NAND2X4TS U3525 ( .A(DP_OP_158J21_127_356_n643), .B(
DP_OP_158J21_127_356_n644), .Y(n2326) );
CMPR22X2TS U3526 ( .A(n3529), .B(n3528), .CO(n3530), .S(n3533) );
ADDFHX4TS U3527 ( .A(n2404), .B(n2405), .CI(n2406), .CO(n2415), .S(n2024) );
XOR2X4TS U3528 ( .A(n2562), .B(n2561), .Y(Sgf_operation_EVEN1_Q_left[13]) );
OAI21X4TS U3529 ( .A0(n3136), .A1(n3135), .B0(n3134), .Y(n3244) );
ADDHX4TS U3530 ( .A(n2787), .B(n2786), .CO(n2813), .S(n2797) );
OAI22X4TS U3531 ( .A0(n2795), .A1(n1090), .B0(n2802), .B1(n2759), .Y(n2787)
);
NOR2X8TS U3532 ( .A(n3704), .B(n1531), .Y(n3736) );
NOR2X4TS U3533 ( .A(n361), .B(n349), .Y(n3294) );
NAND3X2TS U3534 ( .A(n3697), .B(n3696), .C(n3695), .Y(n194) );
NAND2X4TS U3535 ( .A(n1703), .B(DP_OP_155J21_124_2814_n88), .Y(n1945) );
XOR2X4TS U3536 ( .A(n3241), .B(n3240), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N6)
);
NOR2X4TS U3537 ( .A(net287495), .B(net288243), .Y(n2474) );
NOR2X4TS U3538 ( .A(n3043), .B(n3042), .Y(net287247) );
ADDFHX2TS U3539 ( .A(n3041), .B(n3040), .CI(n3039), .CO(n3043), .S(net288224) );
OAI21X4TS U3540 ( .A0(n3266), .A1(n3271), .B0(n3267), .Y(n3288) );
NAND2X6TS U3541 ( .A(n356), .B(n344), .Y(n3271) );
NOR2X4TS U3542 ( .A(n357), .B(n345), .Y(n3266) );
OAI22X2TS U3543 ( .A0(n1340), .A1(n2967), .B0(n1383), .B1(n2961), .Y(n2969)
);
ADDFHX2TS U3544 ( .A(n3113), .B(n3112), .CI(n3111), .CO(n3116), .S(n3149) );
XNOR2X2TS U3545 ( .A(n2678), .B(n3069), .Y(n2676) );
ADDFHX4TS U3546 ( .A(n2362), .B(n2363), .CI(n2361), .CO(n2431), .S(n2366) );
XNOR2X4TS U3547 ( .A(n442), .B(n1560), .Y(n3347) );
CMPR22X2TS U3548 ( .A(n3512), .B(n3511), .CO(n4227), .S(n4228) );
AND2X4TS U3549 ( .A(n1098), .B(n354), .Y(n3512) );
NOR2X2TS U3550 ( .A(n2061), .B(n2062), .Y(n2065) );
ADDFHX4TS U3551 ( .A(n2812), .B(n2813), .CI(n2811), .CO(n2814), .S(n2800) );
NAND2X4TS U3552 ( .A(n2120), .B(n2119), .Y(n2182) );
ADDFHX4TS U3553 ( .A(n2118), .B(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[2]), .CI(n2117),
.CO(n2121), .S(n2120) );
NOR2X4TS U3554 ( .A(n2982), .B(n2981), .Y(n3440) );
ADDFHX4TS U3555 ( .A(n2636), .B(n2635), .CI(n2634), .CO(n3308), .S(n2640) );
NOR2X8TS U3556 ( .A(n2440), .B(n437), .Y(n2635) );
ADDHX4TS U3557 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[10]),
.B(n2519), .CO(n2428), .S(n3045) );
ADDFHX4TS U3558 ( .A(n3555), .B(n3554), .CI(n3553), .CO(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N11),
.S(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N10)
);
ADDFHX4TS U3559 ( .A(n3015), .B(n3014), .CI(n3013), .CO(n2818), .S(n3020) );
ADDFHX4TS U3560 ( .A(n3422), .B(n3421), .CI(net287462), .CO(n4130), .S(n4131) );
INVX4TS U3561 ( .A(n3906), .Y(n2572) );
OAI21X2TS U3562 ( .A0(n3389), .A1(n3387), .B0(n3390), .Y(n3393) );
ADDFHX4TS U3563 ( .A(n3416), .B(n3415), .CI(n3414), .CO(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N11),
.S(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N10)
);
ADDFHX4TS U3564 ( .A(mult_x_58_n14), .B(n3405), .CI(n3404), .CO(n3414), .S(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N9)
);
XNOR2X4TS U3565 ( .A(n3731), .B(n3730), .Y(n3732) );
OAI21X2TS U3566 ( .A0(n3779), .A1(n3728), .B0(n3727), .Y(n3731) );
MX2X6TS U3567 ( .A(n3757), .B(n4515), .S0(n830), .Y(n247) );
MX2X6TS U3568 ( .A(n3747), .B(n4517), .S0(n830), .Y(n246) );
MX2X6TS U3569 ( .A(n3703), .B(n4518), .S0(n830), .Y(n244) );
INVX6TS U3570 ( .A(n2817), .Y(DP_OP_158J21_127_356_n62) );
OAI22X2TS U3571 ( .A0(net291370), .A1(net288243), .B0(net292476), .B1(
net288230), .Y(n2824) );
NAND2X2TS U3572 ( .A(n3608), .B(n2244), .Y(add_x_19_n24) );
AOI21X4TS U3573 ( .A0(n2076), .A1(n913), .B0(n2075), .Y(n2077) );
ADDFHX2TS U3574 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[3]),
.B(n2126), .CI(n2125), .CO(n2127), .S(n2122) );
NOR2X4TS U3575 ( .A(n1698), .B(n2197), .Y(n1969) );
INVX4TS U3576 ( .A(n2197), .Y(n2199) );
XNOR2X4TS U3577 ( .A(n822), .B(n4327), .Y(n1881) );
XNOR2X4TS U3578 ( .A(n2722), .B(n2721), .Y(n2730) );
XOR2X4TS U3579 ( .A(n3830), .B(n2051), .Y(n2053) );
AOI21X4TS U3580 ( .A0(n1876), .A1(n542), .B0(n1875), .Y(n1880) );
OAI21X4TS U3581 ( .A0(n1874), .A1(n680), .B0(n820), .Y(n1875) );
NOR2X4TS U3582 ( .A(n1119), .B(n2961), .Y(n2901) );
OAI22X2TS U3583 ( .A0(net291370), .A1(n2488), .B0(net292476), .B1(n2477),
.Y(net288806) );
ADDFHX2TS U3584 ( .A(n2825), .B(n2824), .CI(n2823), .CO(n2826), .S(net288249) );
ADDFHX4TS U3585 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[6]),
.B(n2161), .CI(n2160), .CO(n2229), .S(n2141) );
ADDFHX2TS U3586 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[5]),
.B(n2139), .CI(n2138), .CO(n2161), .S(n2134) );
AOI21X4TS U3587 ( .A0(n2044), .A1(n2092), .B0(n2043), .Y(n2079) );
OAI21X4TS U3588 ( .A0(n926), .A1(n2102), .B0(n2103), .Y(n2092) );
OAI22X2TS U3589 ( .A0(n2372), .A1(n1543), .B0(n2775), .B1(n1042), .Y(n2375)
);
OAI22X4TS U3590 ( .A0(n2769), .A1(n1042), .B0(n2771), .B1(n1543), .Y(n2779)
);
OAI22X4TS U3591 ( .A0(n2771), .A1(n1042), .B0(n2773), .B1(n2789), .Y(n2778)
);
AO21X4TS U3592 ( .A0(n2789), .A1(n1041), .B0(n2775), .Y(n2353) );
ADDFHX4TS U3593 ( .A(n3161), .B(n3160), .CI(n3159), .CO(n3172), .S(n3168) );
NAND2X4TS U3594 ( .A(n2297), .B(n2296), .Y(n2298) );
NAND2X4TS U3595 ( .A(DP_OP_154J21_123_2814_n124), .B(
DP_OP_154J21_123_2814_n125), .Y(n1909) );
ADDFHX4TS U3596 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[4]),
.B(n2544), .CI(n3612), .CO(n3038), .S(n2541) );
AO21X4TS U3597 ( .A0(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[11]),
.A1(n2257), .B0(n2256), .Y(n2258) );
NOR2X4TS U3598 ( .A(n4369), .B(n3659), .Y(n3672) );
NOR2X2TS U3599 ( .A(n1837), .B(n3158), .Y(n3097) );
NOR4X2TS U3600 ( .A(Op_MY[2]), .B(Op_MY[4]), .C(Op_MY[3]), .D(n1065), .Y(
n3887) );
ADDFHX2TS U3601 ( .A(mult_x_58_n49), .B(mult_x_58_n64), .CI(mult_x_58_n54),
.CO(mult_x_58_n19), .S(mult_x_58_n20) );
NOR2X4TS U3602 ( .A(n2911), .B(n2910), .Y(n3591) );
XOR2X4TS U3603 ( .A(n2538), .B(n2537), .Y(n2544) );
ADDFHX4TS U3604 ( .A(mult_x_56_n14), .B(n3468), .CI(n3467), .CO(n3472), .S(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N9) );
ADDFHX4TS U3605 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[4]),
.B(n1976), .CI(n1975), .CO(n1987), .S(n1986) );
ADDFHX2TS U3606 ( .A(n2959), .B(n2958), .CI(n2957), .CO(n2966), .S(n2962) );
AOI21X4TS U3607 ( .A0(n3332), .A1(n3331), .B0(n3330), .Y(n4058) );
OAI22X2TS U3608 ( .A0(n2804), .A1(n1090), .B0(n2802), .B1(n2801), .Y(n3018)
);
AO21X4TS U3609 ( .A0(n2802), .A1(n1089), .B0(n1452), .Y(n2634) );
NOR2X4TS U3610 ( .A(n3199), .B(n3198), .Y(n3208) );
XNOR2X4TS U3611 ( .A(n3348), .B(n2757), .Y(n2441) );
NAND3X2TS U3612 ( .A(n3750), .B(n3749), .C(n3748), .Y(n198) );
XOR2X4TS U3613 ( .A(n2414), .B(n4039), .Y(n2422) );
ADDFHX4TS U3614 ( .A(n2672), .B(n2673), .CI(n2674), .CO(n2696), .S(n2695) );
OAI22X4TS U3615 ( .A0(n2773), .A1(n1042), .B0(n2772), .B1(n1543), .Y(n3065)
);
XNOR2X4TS U3616 ( .A(n2774), .B(n496), .Y(n2772) );
ADDFHX4TS U3617 ( .A(n3148), .B(n3147), .CI(n3146), .CO(n3154), .S(n3153) );
ADDFHX4TS U3618 ( .A(n2729), .B(n2728), .CI(n2727), .CO(n2743), .S(n2741) );
ADDFHX4TS U3619 ( .A(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[9]),
.B(DP_OP_154J21_123_2814_n147), .CI(DP_OP_154J21_123_2814_n135), .CO(
n2009), .S(n1934) );
OAI21X4TS U3620 ( .A0(n3252), .A1(n3276), .B0(n3278), .Y(n3255) );
INVX6TS U3621 ( .A(n3280), .Y(n3252) );
XNOR2X4TS U3622 ( .A(n2794), .B(n442), .Y(n2442) );
AOI21X2TS U3623 ( .A0(n2190), .A1(n2189), .B0(n2188), .Y(n2194) );
NAND2X4TS U3624 ( .A(n2042), .B(n2041), .Y(n2098) );
ADDFHX2TS U3625 ( .A(n2980), .B(n2979), .CI(n2978), .CO(n2982), .S(n2975) );
XNOR2X4TS U3626 ( .A(n2768), .B(n442), .Y(n2357) );
XNOR2X4TS U3627 ( .A(n2774), .B(n2768), .Y(n2771) );
XOR2X4TS U3628 ( .A(n2255), .B(n2251), .Y(Sgf_operation_EVEN1_Q_left[10]) );
ADDFHX4TS U3629 ( .A(n2726), .B(n2725), .CI(n2724), .CO(n2740), .S(n2738) );
ADDFHX2TS U3630 ( .A(n2713), .B(n2718), .CI(n2712), .CO(n2725), .S(n2708) );
OR2X8TS U3631 ( .A(n3144), .B(n3143), .Y(n3243) );
OAI22X2TS U3632 ( .A0(n2637), .A1(n3305), .B0(n1118), .B1(n3303), .Y(n3307)
);
OAI22X2TS U3633 ( .A0(n3305), .A1(n2756), .B0(n1118), .B1(n2792), .Y(n2798)
);
OAI22X2TS U3634 ( .A0(n3305), .A1(n3303), .B0(n1118), .B1(n2758), .Y(n2786)
);
OAI22X2TS U3635 ( .A0(n2364), .A1(n1118), .B0(n3305), .B1(n2371), .Y(n2374)
);
AO21X4TS U3636 ( .A0(n3305), .A1(n1118), .B0(n3303), .Y(n3351) );
OR2X8TS U3637 ( .A(n2411), .B(n2410), .Y(n2420) );
NAND2X4TS U3638 ( .A(n1953), .B(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[10]), .Y(n2284) );
INVX6TS U3639 ( .A(DP_OP_155J21_124_2814_n78), .Y(n1949) );
INVX12TS U3640 ( .A(Sgf_operation_EVEN1_result_A_adder[1]), .Y(n3106) );
AOI2BB2X2TS U3641 ( .B0(n3929), .B1(n3924), .A0N(n3930), .A1N(n4403), .Y(
n4558) );
ADDFHX4TS U3642 ( .A(n3301), .B(n3300), .CI(n3299), .CO(n3311), .S(n2850) );
OAI22X2TS U3643 ( .A0(net288241), .A1(net288798), .B0(net291956), .B1(
net288745), .Y(n2472) );
XNOR2X4TS U3644 ( .A(n3399), .B(n4480), .Y(n4088) );
XOR2X4TS U3645 ( .A(n3398), .B(n3397), .Y(n4480) );
NOR2X6TS U3646 ( .A(n2865), .B(n2866), .Y(n3600) );
ADDFHX4TS U3647 ( .A(n3018), .B(n3017), .CI(n3016), .CO(n3019), .S(n2815) );
NAND2X4TS U3648 ( .A(n2001), .B(n2000), .Y(n2016) );
XNOR2X4TS U3649 ( .A(n3258), .B(n3257), .Y(DP_OP_158J21_127_356_n1057) );
OAI21X4TS U3650 ( .A0(n3322), .A1(n3318), .B0(n3319), .Y(n3258) );
XNOR2X4TS U3651 ( .A(n3212), .B(n3211), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N12)
);
ADDFHX4TS U3652 ( .A(n2436), .B(n2353), .CI(n2352), .CO(n2439), .S(n2363) );
ADDFHX2TS U3653 ( .A(n2375), .B(n2374), .CI(n2373), .CO(n2365), .S(n3013) );
XOR2X4TS U3654 ( .A(n2309), .B(n2308), .Y(n2566) );
NAND2X4TS U3655 ( .A(Sgf_operation_EVEN1_result_A_adder[5]), .B(
DP_OP_158J21_127_356_n651), .Y(n2345) );
XNOR2X4TS U3656 ( .A(n2276), .B(n2277), .Y(n2294) );
NOR2X2TS U3657 ( .A(n3158), .B(n3107), .Y(n3110) );
XOR2X4TS U3658 ( .A(n3782), .B(n3781), .Y(n3783) );
ADDFHX4TS U3659 ( .A(n2270), .B(n2268), .CI(n2269), .CO(n2271), .S(n2236) );
AOI2BB2X2TS U3660 ( .B0(n3927), .B1(n3926), .A0N(n3930), .A1N(n4423), .Y(
n4567) );
AOI21X4TS U3661 ( .A0(n1738), .A1(n3283), .B0(n3282), .Y(n4053) );
AO21X4TS U3662 ( .A0(n3393), .A1(n3396), .B0(n3281), .Y(n3282) );
NOR2X2TS U3663 ( .A(n3108), .B(n3102), .Y(n3109) );
INVX12TS U3664 ( .A(Sgf_operation_EVEN1_result_A_adder[2]), .Y(n3102) );
ADDFHX2TS U3665 ( .A(n3510), .B(n3509), .CI(n3508), .CO(n4233), .S(n4234) );
ADDFHX4TS U3666 ( .A(n2931), .B(n2930), .CI(n2929), .CO(n2937), .S(n2936) );
NAND2X8TS U3667 ( .A(n1041), .B(n2322), .Y(n2789) );
XNOR2X4TS U3668 ( .A(n1785), .B(n2774), .Y(n2769) );
INVX8TS U3669 ( .A(n2869), .Y(n2902) );
ADDFHX4TS U3670 ( .A(n2827), .B(n2828), .CI(n2826), .CO(net288223), .S(
net288237) );
ADDFHX2TS U3671 ( .A(n3125), .B(n3126), .CI(n3127), .CO(n3139), .S(n3131) );
XNOR2X2TS U3672 ( .A(n2774), .B(n2794), .Y(n2765) );
XOR2X4TS U3673 ( .A(n2201), .B(n2200), .Y(n2202) );
ADDFHX4TS U3674 ( .A(n2890), .B(n2889), .CI(n2888), .CO(n2939), .S(n2938) );
XNOR2X4TS U3675 ( .A(n2349), .B(n2350), .Y(n2323) );
XOR2X4TS U3676 ( .A(n2665), .B(DP_OP_158J21_127_356_n608), .Y(n2666) );
NAND3X4TS U3677 ( .A(n3803), .B(n3802), .C(n3801), .Y(n203) );
NAND2X4TS U3678 ( .A(n2164), .B(n1499), .Y(n2166) );
ADDFHX4TS U3679 ( .A(n1977), .B(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[5]), .CI(n1522),
.CO(n1989), .S(n1988) );
NOR2X8TS U3680 ( .A(n2042), .B(n2041), .Y(n2097) );
ADDFHX4TS U3681 ( .A(n3119), .B(n3118), .CI(n3117), .CO(n3156), .S(n3155) );
ADDFHX4TS U3682 ( .A(n3114), .B(n3115), .CI(n3116), .CO(n3169), .S(n3117) );
XNOR2X4TS U3683 ( .A(n3255), .B(n3254), .Y(DP_OP_158J21_127_356_n986) );
XNOR2X4TS U3684 ( .A(n3225), .B(n3224), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N10)
);
OAI22X2TS U3685 ( .A0(n2675), .A1(n2716), .B0(n2669), .B1(n461), .Y(n2673)
);
NAND2X8TS U3686 ( .A(n3304), .B(n2343), .Y(n3305) );
ADDFHX4TS U3687 ( .A(n2966), .B(n2964), .CI(n2965), .CO(n2976), .S(n2973) );
ADDFHX4TS U3688 ( .A(n2630), .B(n2629), .CI(n2628), .CO(n2631), .S(n2574) );
XNOR2X4TS U3689 ( .A(n2333), .B(n2341), .Y(n2334) );
NAND2X4TS U3690 ( .A(DP_OP_158J21_127_356_n317), .B(n2326), .Y(n2333) );
NOR2X4TS U3691 ( .A(n1520), .B(n2902), .Y(n2949) );
AOI21X4TS U3692 ( .A0(n3094), .A1(n3093), .B0(n3092), .Y(n3136) );
XNOR2X4TS U3693 ( .A(n1785), .B(n2793), .Y(n2795) );
ADDFHX4TS U3694 ( .A(n2643), .B(n2642), .CI(n2641), .CO(n2849), .S(n2554) );
ADDFHX4TS U3695 ( .A(n2433), .B(n2432), .CI(n2431), .CO(n2555), .S(n2847) );
NAND2X8TS U3696 ( .A(n1916), .B(n1915), .Y(n2245) );
INVX6TS U3697 ( .A(n1921), .Y(n1916) );
XOR2X4TS U3698 ( .A(n3419), .B(n3420), .Y(n3422) );
NAND2X4TS U3699 ( .A(n916), .B(n3418), .Y(n3420) );
XNOR2X4TS U3700 ( .A(n2413), .B(n2412), .Y(n2421) );
XNOR2X4TS U3701 ( .A(n2424), .B(n4042), .Y(n2412) );
XNOR2X4TS U3702 ( .A(n2704), .B(n2678), .Y(n2677) );
ADDFHX4TS U3703 ( .A(n3170), .B(n3169), .CI(n3168), .CO(n3192), .S(n3157) );
NAND3X2TS U3704 ( .A(n3712), .B(n3711), .C(n3710), .Y(n196) );
ADDFHX4TS U3705 ( .A(n2543), .B(n2542), .CI(n2541), .CO(n2553), .S(n2864) );
ADDFHX4TS U3706 ( .A(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[11]),
.B(DP_OP_154J21_123_2814_n133), .CI(n2393), .CO(n2392), .S(n2014) );
NOR2X4TS U3707 ( .A(net287909), .B(n2477), .Y(n2505) );
XOR2X4TS U3708 ( .A(n1914), .B(n1919), .Y(n1921) );
AOI21X4TS U3709 ( .A0(n2192), .A1(n2188), .B0(n2123), .Y(n2124) );
NAND3X2TS U3710 ( .A(n3760), .B(n3759), .C(n3758), .Y(n199) );
XNOR2X4TS U3711 ( .A(n2794), .B(n2757), .Y(n2364) );
NAND3X2TS U3712 ( .A(n3717), .B(n3716), .C(n3715), .Y(n195) );
XNOR2X4TS U3713 ( .A(n2794), .B(n2793), .Y(n2801) );
XNOR2X4TS U3714 ( .A(n2340), .B(n2335), .Y(n2338) );
XOR2X4TS U3715 ( .A(DP_OP_158J21_127_356_n643), .B(DP_OP_158J21_127_356_n644), .Y(n2340) );
AOI21X4TS U3716 ( .A0(n4356), .A1(n1862), .B0(n1861), .Y(n2444) );
NOR2X2TS U3717 ( .A(n4358), .B(n1860), .Y(n1862) );
XOR2X4TS U3718 ( .A(n2349), .B(n2321), .Y(n2322) );
NOR2X4TS U3719 ( .A(n2320), .B(DP_OP_158J21_127_356_n297), .Y(n2321) );
OAI21X2TS U3720 ( .A0(n2131), .A1(n2143), .B0(n2145), .Y(n2137) );
ADDFHX4TS U3721 ( .A(n2953), .B(n2952), .CI(n2951), .CO(n2971), .S(n2940) );
ADDFHX4TS U3722 ( .A(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[11]),
.B(DP_OP_155J21_124_2814_n145), .CI(DP_OP_155J21_124_2814_n133), .CO(
n2154), .S(n2030) );
ADDFHX4TS U3723 ( .A(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[10]),
.B(DP_OP_155J21_124_2814_n146), .CI(DP_OP_155J21_124_2814_n134), .CO(
n2029), .S(n1972) );
XNOR2X4TS U3724 ( .A(n3348), .B(n2774), .Y(n2788) );
ADDFHX4TS U3725 ( .A(n2540), .B(n3603), .CI(n2539), .CO(n2863), .S(n2033) );
OAI21X4TS U3726 ( .A0(n3721), .A1(n3908), .B0(n3722), .Y(n2840) );
XNOR2X4TS U3727 ( .A(n2768), .B(n2793), .Y(n2759) );
NAND3X2TS U3728 ( .A(n3720), .B(n3719), .C(n3718), .Y(n193) );
XOR2X4TS U3729 ( .A(n2587), .B(n2586), .Y(n2857) );
AOI21X2TS U3730 ( .A0(n1163), .A1(n2582), .B0(n2581), .Y(n2587) );
NAND2X4TS U3731 ( .A(n2927), .B(n2928), .Y(n3580) );
ADDFHX4TS U3732 ( .A(n2832), .B(n2831), .CI(n2830), .CO(n2034), .S(n2866) );
ADDFHX4TS U3733 ( .A(n3008), .B(n3007), .CI(n3006), .CO(n3009), .S(n2632) );
NAND2X4TS U3734 ( .A(n2333), .B(n2341), .Y(n2327) );
INVX6TS U3735 ( .A(n3901), .Y(n2314) );
XOR2X4TS U3736 ( .A(n1033), .B(n2298), .Y(n3901) );
NAND2X4TS U3737 ( .A(n1988), .B(n1987), .Y(n2306) );
OAI21X4TS U3738 ( .A0(n2057), .A1(n2088), .B0(n2058), .Y(n2076) );
NAND2X4TS U3739 ( .A(n2048), .B(n2047), .Y(n2088) );
NOR2X6TS U3740 ( .A(n2050), .B(n2049), .Y(n2057) );
NOR2X8TS U3741 ( .A(DP_OP_158J21_127_356_n652), .B(DP_OP_158J21_127_356_n653), .Y(n2344) );
ADDFHX4TS U3742 ( .A(n3173), .B(n3172), .CI(n3171), .CO(n3195), .S(n3193) );
OAI21X4TS U3743 ( .A0(n3659), .A1(n4362), .B0(n3660), .Y(n3674) );
XNOR2X4TS U3744 ( .A(n2774), .B(n2770), .Y(n2773) );
ADDFHX4TS U3745 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[7]),
.B(n1994), .CI(n1993), .CO(n1995), .S(n1992) );
OR2X4TS U3746 ( .A(n2780), .B(n2779), .Y(n3260) );
NAND2X2TS U3747 ( .A(n2780), .B(n2779), .Y(n3259) );
ADDFHX4TS U3748 ( .A(n2367), .B(n2366), .CI(n2365), .CO(n2848), .S(n2819) );
XNOR2X4TS U3749 ( .A(n2250), .B(n2249), .Y(Sgf_operation_EVEN1_Q_left[9]) );
XOR2X4TS U3750 ( .A(n1866), .B(n4326), .Y(n1882) );
XOR2X4TS U3751 ( .A(n1868), .B(n1867), .Y(n1883) );
NOR2X4TS U3752 ( .A(n3673), .B(n3679), .Y(n1858) );
XNOR2X4TS U3753 ( .A(n2757), .B(n2770), .Y(n2792) );
XNOR2X4TS U3754 ( .A(n2768), .B(n2757), .Y(n2791) );
XOR2X4TS U3755 ( .A(n2286), .B(n2285), .Y(n3878) );
AOI21X4TS U3756 ( .A0(n2282), .A1(n2281), .B0(n2280), .Y(n2286) );
NAND3X2TS U3757 ( .A(n3735), .B(n3734), .C(n3733), .Y(n197) );
XOR2X4TS U3758 ( .A(n921), .B(n2624), .Y(n2833) );
ADDFHX4TS U3759 ( .A(net288812), .B(net288813), .CI(net288814), .CO(
net288757), .S(net288758) );
OAI22X2TS U3760 ( .A0(n2441), .A1(n3305), .B0(n2637), .B1(n1118), .Y(n2639)
);
XNOR2X4TS U3761 ( .A(n1560), .B(n2757), .Y(n2637) );
MXI2X1TS U3762 ( .A(Data_MY[30]), .B(n3890), .S0(net286911), .Y(n1840) );
NAND2X8TS U3763 ( .A(n2839), .B(n2838), .Y(n1850) );
NOR2BX1TS U3764 ( .AN(n3069), .B(n2747), .Y(n2689) );
INVX2TS U3765 ( .A(Add_result[1]), .Y(n3668) );
INVX2TS U3766 ( .A(n4129), .Y(n3435) );
INVX2TS U3767 ( .A(n4294), .Y(n3575) );
NAND2X2TS U3768 ( .A(n3800), .B(n250), .Y(n3801) );
INVX2TS U3769 ( .A(n3333), .Y(n4020) );
CLKBUFX3TS U3770 ( .A(n1094), .Y(n4537) );
CLKBUFX3TS U3771 ( .A(n1125), .Y(n4445) );
NOR2X8TS U3773 ( .A(n1853), .B(FS_Module_state_reg[1]), .Y(n3846) );
MX2X6TS U3774 ( .A(Data_MX[19]), .B(Op_MX[19]), .S0(net287641), .Y(n363) );
MX2X6TS U3775 ( .A(Data_MX[7]), .B(Op_MX[7]), .S0(net287633), .Y(n351) );
NAND2X4TS U3777 ( .A(n3855), .B(n1853), .Y(n3848) );
INVX2TS U3778 ( .A(n3635), .Y(n1854) );
NAND2X4TS U3779 ( .A(n3848), .B(n1854), .Y(n1855) );
NAND2X6TS U3780 ( .A(n1855), .B(FS_Module_state_reg[1]), .Y(n3912) );
AOI22X1TS U3781 ( .A0(n3873), .A1(Add_result[23]), .B0(
Sgf_normalized_result[22]), .B1(n4533), .Y(n1901) );
NOR2X4TS U3782 ( .A(n3786), .B(n783), .Y(n1893) );
AOI21X2TS U3783 ( .A0(n822), .A1(n805), .B0(n4337), .Y(n1868) );
XOR2X4TS U3784 ( .A(n1870), .B(n1869), .Y(n1884) );
INVX2TS U3785 ( .A(n1877), .Y(n1878) );
BUFX12TS U3786 ( .A(n3912), .Y(n3858) );
AND2X8TS U3787 ( .A(n3799), .B(n1897), .Y(n3915) );
MX2X6TS U3788 ( .A(Data_MX[20]), .B(Op_MX[20]), .S0(net287641), .Y(n364) );
MX2X6TS U3789 ( .A(Data_MX[8]), .B(Op_MX[8]), .S0(net287633), .Y(n352) );
NOR2X4TS U3790 ( .A(n364), .B(n352), .Y(n3333) );
OAI21X2TS U3791 ( .A0(n3333), .A1(n1902), .B0(n4061), .Y(n4064) );
MX2X6TS U3792 ( .A(Data_MX[21]), .B(Op_MX[21]), .S0(net287641), .Y(n365) );
MX2X6TS U3793 ( .A(Data_MX[9]), .B(Op_MX[9]), .S0(net287633), .Y(n353) );
MX2X6TS U3794 ( .A(Data_MX[22]), .B(Op_MX[22]), .S0(net287641), .Y(n366) );
NOR2X4TS U3795 ( .A(n366), .B(n354), .Y(n4057) );
NOR2X2TS U3796 ( .A(n4063), .B(n4057), .Y(n4079) );
NAND2X2TS U3797 ( .A(n365), .B(n353), .Y(n4081) );
NAND2X2TS U3798 ( .A(n366), .B(n354), .Y(n4075) );
OAI21X1TS U3799 ( .A0(n4057), .A1(n4081), .B0(n4075), .Y(n1903) );
BUFX6TS U3801 ( .A(net286913), .Y(net286911) );
NAND2X2TS U3806 ( .A(n735), .B(n1909), .Y(n1905) );
NAND2X2TS U3807 ( .A(n1680), .B(n1928), .Y(n1911) );
INVX2TS U3808 ( .A(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[8]), .Y(
n1915) );
INVX2TS U3809 ( .A(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[7]), .Y(
n1917) );
ADDFHX4TS U3810 ( .A(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[8]),
.B(DP_OP_154J21_123_2814_n136), .CI(DP_OP_154J21_123_2814_n148), .CO(
n1935), .S(n1931) );
INVX2TS U3811 ( .A(n1948), .Y(n1938) );
INVX2TS U3812 ( .A(n1943), .Y(n1939) );
XOR2X4TS U3813 ( .A(n1941), .B(n1940), .Y(n1954) );
XOR2X4TS U3814 ( .A(n1950), .B(n1945), .Y(n1947) );
NAND2X1TS U3815 ( .A(n1956), .B(n1960), .Y(n1957) );
NOR2X4TS U3816 ( .A(n1968), .B(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[1]), .Y(n2184) );
ADDFHX4TS U3817 ( .A(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[9]),
.B(DP_OP_155J21_124_2814_n147), .CI(DP_OP_155J21_124_2814_n135), .CO(
n1971), .S(n1964) );
INVX2TS U3818 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[4]),
.Y(n1975) );
INVX2TS U3819 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[6]),
.Y(n1978) );
INVX2TS U3820 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[7]),
.Y(n1993) );
ADDFHX4TS U3821 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[6]),
.B(n1979), .CI(n1978), .CO(n1991), .S(n1990) );
ADDFHX4TS U3822 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[3]),
.B(n1982), .CI(n1981), .CO(n1985), .S(n1984) );
XNOR2X2TS U3823 ( .A(n2597), .B(n1997), .Y(n2834) );
INVX2TS U3824 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[9]),
.Y(n2022) );
ADDFHX4TS U3825 ( .A(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[10]),
.B(DP_OP_154J21_123_2814_n146), .CI(n2012), .CO(n2013), .S(n2010) );
AOI21X4TS U3826 ( .A0(n821), .A1(n4094), .B0(n4095), .Y(n2019) );
XOR2X4TS U3827 ( .A(n2019), .B(n4044), .Y(n2406) );
INVX2TS U3828 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[10]),
.Y(n2405) );
INVX2TS U3829 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[10]),
.Y(n2404) );
INVX2TS U3830 ( .A(n2530), .Y(n2025) );
NOR2X8TS U3831 ( .A(n2033), .B(n2034), .Y(n3599) );
NAND2X4TS U3832 ( .A(n2034), .B(n2033), .Y(n2835) );
CLKMX2X2TS U3833 ( .A(Op_MX[24]), .B(exp_oper_result[1]), .S0(FSM_selector_A), .Y(n2040) );
XOR2X4TS U3834 ( .A(n1124), .B(n2036), .Y(n2042) );
CLKMX2X2TS U3835 ( .A(Op_MX[25]), .B(exp_oper_result[2]), .S0(FSM_selector_A), .Y(n2041) );
NAND2X2TS U3836 ( .A(n2039), .B(n3830), .Y(n2103) );
INVX2TS U3837 ( .A(n2072), .Y(n2061) );
CLKMX2X2TS U3838 ( .A(Op_MX[28]), .B(n275), .S0(FSM_selector_A), .Y(n2052)
);
NAND2X2TS U3839 ( .A(n2053), .B(n2052), .Y(n2074) );
INVX2TS U3840 ( .A(n2088), .Y(n2055) );
INVX2TS U3841 ( .A(n894), .Y(n2062) );
CLKMX2X2TS U3842 ( .A(Op_MX[29]), .B(n274), .S0(FSM_selector_A), .Y(n2068)
);
NAND2X2TS U3843 ( .A(n2069), .B(n2068), .Y(n2073) );
OR2X2TS U3844 ( .A(n2082), .B(n2081), .Y(n3823) );
NAND2X2TS U3845 ( .A(n2082), .B(n2081), .Y(n2106) );
INVX2TS U3846 ( .A(n2106), .Y(n3828) );
INVX2TS U3847 ( .A(n281), .Y(n2083) );
NOR2X2TS U3848 ( .A(n4385), .B(n2083), .Y(n2084) );
NAND2X2TS U3849 ( .A(n1124), .B(n2084), .Y(n3825) );
NAND2X1TS U3850 ( .A(n2056), .B(n2088), .Y(n2089) );
XNOR2X4TS U3851 ( .A(n2090), .B(n2089), .Y(n3805) );
INVX2TS U3852 ( .A(n2095), .Y(n2091) );
NAND2X1TS U3853 ( .A(n2091), .B(n2094), .Y(n2093) );
INVX2TS U3854 ( .A(n2097), .Y(n2099) );
NAND2X1TS U3855 ( .A(n2099), .B(n2098), .Y(n2100) );
NAND2X1TS U3856 ( .A(n2104), .B(n2103), .Y(n2105) );
INVX2TS U3857 ( .A(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[6]), .Y(
n2108) );
NAND2BX1TS U3858 ( .AN(n2109), .B(n2108), .Y(n2110) );
XNOR2X4TS U3859 ( .A(n2116), .B(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[1]), .Y(n2114) );
INVX2TS U3860 ( .A(Sgf_operation_EVEN1_Q_left[1]), .Y(n2113) );
OR2X2TS U3861 ( .A(n2114), .B(n2113), .Y(n2204) );
INVX2TS U3862 ( .A(Sgf_operation_EVEN1_Q_left[2]), .Y(n2117) );
OR2X2TS U3863 ( .A(n2116), .B(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[1]), .Y(n2119) );
INVX2TS U3864 ( .A(Sgf_operation_EVEN1_Q_left[3]), .Y(n2125) );
INVX2TS U3865 ( .A(n2182), .Y(n2188) );
INVX2TS U3866 ( .A(n2191), .Y(n2123) );
INVX2TS U3867 ( .A(n2148), .Y(n2131) );
INVX2TS U3868 ( .A(Sgf_operation_EVEN1_Q_left[4]), .Y(n2132) );
INVX2TS U3869 ( .A(n2143), .Y(n2129) );
NAND2X2TS U3870 ( .A(n2128), .B(n2127), .Y(n2145) );
NAND2X1TS U3871 ( .A(n2129), .B(n2145), .Y(n2130) );
CLKXOR2X2TS U3872 ( .A(n2131), .B(n2130), .Y(n2221) );
INVX2TS U3873 ( .A(Sgf_operation_EVEN1_Q_left[5]), .Y(n2138) );
INVX2TS U3874 ( .A(n2146), .Y(n2135) );
NAND2X1TS U3875 ( .A(n2135), .B(n2144), .Y(n2136) );
INVX2TS U3876 ( .A(n1846), .Y(n2140) );
INVX2TS U3877 ( .A(n2171), .Y(n2142) );
NAND2X2TS U3878 ( .A(n2141), .B(n2140), .Y(n2169) );
CLKXOR2X2TS U3879 ( .A(n2149), .B(n2170), .Y(n2223) );
XOR2X4TS U3880 ( .A(n2156), .B(n2155), .Y(n2157) );
INVX2TS U3881 ( .A(n2162), .Y(n2164) );
INVX2TS U3882 ( .A(n3877), .Y(n2167) );
INVX2TS U3883 ( .A(n2181), .Y(n2190) );
NAND2X1TS U3884 ( .A(n2189), .B(n2182), .Y(n2183) );
AOI21X4TS U3885 ( .A0(n2209), .A1(n2208), .B0(n439), .Y(n2187) );
NAND2X1TS U3886 ( .A(n2192), .B(n2191), .Y(n2193) );
AOI21X4TS U3887 ( .A0(n2209), .A1(n2196), .B0(n1697), .Y(n2201) );
NAND2X1TS U3888 ( .A(n2204), .B(n2203), .Y(n2206) );
NAND2X1TS U3889 ( .A(n1283), .B(n2210), .Y(n2211) );
XNOR2X1TS U3890 ( .A(n2211), .B(n1282), .Y(n3907) );
XNOR2X4TS U3891 ( .A(n2215), .B(n2214), .Y(n3906) );
NAND2X2TS U3892 ( .A(n3907), .B(n3906), .Y(n3908) );
AOI21X4TS U3893 ( .A0(n2840), .A1(n2219), .B0(n2218), .Y(n2606) );
NAND2X2TS U3894 ( .A(n2222), .B(n2032), .Y(n3628) );
XOR2X4TS U3895 ( .A(n2227), .B(n2228), .Y(n2266) );
INVX2TS U3896 ( .A(n2264), .Y(n2237) );
NAND2X4TS U3897 ( .A(n2237), .B(n2263), .Y(n2241) );
NOR2X2TS U3898 ( .A(n2557), .B(n2556), .Y(n2261) );
INVX2TS U3899 ( .A(n3879), .Y(n2287) );
ADDFHX4TS U3900 ( .A(n2289), .B(n2288), .CI(n2287), .CO(n2290), .S(n2272) );
INVX2TS U3901 ( .A(n2295), .Y(n2297) );
ADDFHX4TS U3902 ( .A(n2301), .B(n2299), .CI(n2300), .CO(n2302), .S(n2291) );
INVX2TS U3903 ( .A(n2303), .Y(n2304) );
AOI21X4TS U3904 ( .A0(n1626), .A1(n1074), .B0(n2304), .Y(n2309) );
INVX2TS U3905 ( .A(n2305), .Y(n2307) );
ADDFHX4TS U3906 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[11]),
.B(n2311), .CI(n2310), .CO(n2565), .S(n2312) );
XNOR2X4TS U3907 ( .A(n2318), .B(n2317), .Y(n2376) );
NAND2X4TS U3908 ( .A(DP_OP_158J21_127_356_n312), .B(
DP_OP_158J21_127_356_n642), .Y(n3366) );
NAND2X2TS U3909 ( .A(n4122), .B(n2329), .Y(n2325) );
INVX2TS U3910 ( .A(n2768), .Y(n2347) );
NOR2X2TS U3911 ( .A(n2347), .B(n437), .Y(n2435) );
XNOR2X4TS U3912 ( .A(n3362), .B(n2774), .Y(n2372) );
XNOR2X4TS U3913 ( .A(n1785), .B(n2757), .Y(n2371) );
INVX2TS U3914 ( .A(n2510), .Y(n2386) );
NOR2X4TS U3915 ( .A(n4488), .B(n1853), .Y(n3654) );
CMPR32X2TS U3916 ( .A(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[11]),
.B(n2393), .C(DP_OP_154J21_123_2814_n133), .CO(n2394) );
NAND2X2TS U3917 ( .A(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[9]),
.B(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[8]), .Y(n2517) );
INVX2TS U3918 ( .A(n2517), .Y(n2518) );
AOI21X4TS U3919 ( .A0(n821), .A1(n4092), .B0(n4093), .Y(n2403) );
XOR2X4TS U3920 ( .A(n2403), .B(n4043), .Y(n2409) );
INVX2TS U3921 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[11]),
.Y(n2407) );
INVX2TS U3922 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[12]),
.Y(n2411) );
ADDFHX4TS U3923 ( .A(n2409), .B(n2408), .CI(n2407), .CO(n2418), .S(n2416) );
INVX2TS U3924 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[13]),
.Y(n2413) );
OAI21X4TS U3925 ( .A0(n4076), .A1(n4077), .B0(n4078), .Y(n2424) );
NOR2X6TS U3926 ( .A(n2421), .B(n2420), .Y(n2583) );
AOI21X1TS U3927 ( .A0(n2424), .A1(n4045), .B0(n4046), .Y(n2425) );
NAND2X2TS U3928 ( .A(n2428), .B(n2408), .Y(n2429) );
INVX2TS U3929 ( .A(n2454), .Y(n2456) );
INVX2TS U3930 ( .A(n2462), .Y(n2464) );
CMPR22X2TS U3931 ( .A(Op_MX[2]), .B(Op_MX[8]), .CO(net288832), .S(net288833)
);
ADDHX4TS U3932 ( .A(Op_MX[6]), .B(Op_MX[0]), .CO(net288834), .S(net288831)
);
CMPR22X2TS U3933 ( .A(n2474), .B(n2473), .CO(n2480), .S(n2483) );
NOR2X2TS U3934 ( .A(net288778), .B(n2488), .Y(n3425) );
ADDFHX4TS U3935 ( .A(n2497), .B(n2496), .CI(net288767), .CO(net288759), .S(
n2501) );
ADDFHX4TS U3936 ( .A(n2499), .B(net288763), .CI(n2498), .CO(n2500), .S(n2494) );
INVX2TS U3937 ( .A(n2598), .Y(n2513) );
NOR2X1TS U3938 ( .A(n2527), .B(n2530), .Y(n2533) );
INVX2TS U3939 ( .A(n2528), .Y(n2531) );
OAI21X2TS U3940 ( .A0(n2531), .A1(n2530), .B0(n2529), .Y(n2532) );
AOI21X2TS U3941 ( .A0(n1163), .A1(n2533), .B0(n2532), .Y(n2538) );
INVX2TS U3942 ( .A(n2534), .Y(n2536) );
INVX2TS U3943 ( .A(n2590), .Y(n2545) );
INVX2TS U3944 ( .A(n2580), .Y(n2546) );
NAND2X4TS U3945 ( .A(n1671), .B(DP_OP_158J21_127_356_n51), .Y(
DP_OP_158J21_127_356_n5) );
NAND2X1TS U3946 ( .A(n2567), .B(n2619), .Y(n2568) );
ADDFHX4TS U3947 ( .A(n2572), .B(n2571), .CI(n2570), .CO(n2573), .S(n2316) );
INVX2TS U3948 ( .A(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N7),
.Y(n2578) );
NOR2X1TS U3949 ( .A(n2590), .B(n2580), .Y(n2582) );
INVX2TS U3950 ( .A(n2583), .Y(n2585) );
INVX2TS U3951 ( .A(n2589), .Y(n2593) );
INVX2TS U3952 ( .A(n2591), .Y(n2592) );
XOR2X4TS U3953 ( .A(n2600), .B(n2599), .Y(n2853) );
INVX2TS U3954 ( .A(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[8]), .Y(
n2601) );
ADDFHX4TS U3955 ( .A(n2605), .B(n2604), .CI(n2603), .CO(
DP_OP_156J21_125_3370_n204), .S(DP_OP_156J21_125_3370_n205) );
AOI21X4TS U3956 ( .A0(n1826), .A1(n2608), .B0(n2607), .Y(add_x_19_n282) );
XNOR2X4TS U3957 ( .A(n2612), .B(n2611), .Y(Sgf_operation_Result[19]) );
INVX2TS U3958 ( .A(n2621), .Y(n2623) );
INVX2TS U3959 ( .A(n3352), .Y(n3309) );
INVX2TS U3960 ( .A(n2757), .Y(n3303) );
NAND2X2TS U3961 ( .A(DP_OP_158J21_127_356_n608), .B(n2660), .Y(n2650) );
XNOR2X4TS U3962 ( .A(n2648), .B(n2651), .Y(n2649) );
OR2X2TS U3963 ( .A(n1839), .B(n2651), .Y(n2652) );
NAND2BX1TS U3964 ( .AN(n3069), .B(n2721), .Y(n2655) );
INVX2TS U3965 ( .A(n4120), .Y(n2657) );
XOR2X1TS U3966 ( .A(DP_OP_158J21_127_356_n1033), .B(n2662), .Y(n2664) );
XNOR2X1TS U3967 ( .A(n3069), .B(n2721), .Y(n2667) );
OAI22X1TS U3968 ( .A0(n2668), .A1(n2747), .B0(n2667), .B1(n417), .Y(n2674)
);
OAI22X2TS U3969 ( .A0(n2677), .A1(n474), .B0(n2676), .B1(n884), .Y(n3062) );
OAI22X2TS U3970 ( .A0(n2679), .A1(n474), .B0(n441), .B1(n884), .Y(n3061) );
NOR2X1TS U3971 ( .A(n436), .B(n2705), .Y(n2713) );
OAI22X2TS U3972 ( .A0(n2716), .A1(n2714), .B0(n461), .B1(n2715), .Y(n2717)
);
NOR2X1TS U3973 ( .A(n2720), .B(n436), .Y(n2734) );
INVX2TS U3974 ( .A(n2748), .Y(n2746) );
INVX2TS U3975 ( .A(n2731), .Y(n2732) );
NOR2X2TS U3976 ( .A(n2732), .B(n436), .Y(n2745) );
NAND2X2TS U3977 ( .A(n2743), .B(n2742), .Y(n2992) );
AO21X1TS U3978 ( .A0(n417), .A1(n2747), .B0(n436), .Y(n2750) );
XOR3X2TS U3979 ( .A(n2750), .B(n2749), .C(n2748), .Y(n2751) );
OR2X2TS U3980 ( .A(n2752), .B(n2751), .Y(n2754) );
NAND2X1TS U3981 ( .A(n2752), .B(n2751), .Y(n2753) );
NAND2X2TS U3982 ( .A(n2754), .B(n2753), .Y(n2755) );
XNOR2X1TS U3983 ( .A(n2757), .B(n3071), .Y(n2756) );
OAI21X4TS U3984 ( .A0(n3054), .A1(n3066), .B0(n3055), .Y(n3261) );
NOR2BX2TS U3985 ( .AN(n496), .B(n1220), .Y(n2807) );
ADDFHX4TS U3986 ( .A(n2798), .B(n2797), .CI(n2796), .CO(n2799), .S(n2785) );
NAND2X4TS U3987 ( .A(n2800), .B(n2799), .Y(n3355) );
XOR2X4TS U3988 ( .A(n3024), .B(n2816), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N7)
);
NOR2X1TS U3989 ( .A(n401), .B(net288230), .Y(n3041) );
OAI22X1TS U3990 ( .A0(net291370), .A1(net287910), .B0(net287909), .B1(
net288229), .Y(n3040) );
NAND2BX2TS U3991 ( .AN(n3617), .B(n3615), .Y(add_x_19_n21) );
INVX2TS U3992 ( .A(n2841), .Y(n2843) );
OAI21X4TS U3993 ( .A0(n3340), .A1(DP_OP_158J21_127_356_n51), .B0(n431), .Y(
n2851) );
ADDFHX4TS U3994 ( .A(n2856), .B(n2855), .CI(n2854), .CO(
DP_OP_156J21_125_3370_n200), .S(DP_OP_156J21_125_3370_n201) );
ADDFHX4TS U3995 ( .A(n2858), .B(n2857), .CI(n3613), .CO(n2604), .S(n3035) );
NAND2X2TS U3996 ( .A(n2989), .B(n2987), .Y(n2861) );
XNOR2X4TS U3997 ( .A(n2862), .B(n2861), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N9)
);
OAI22X1TS U3998 ( .A0(n1382), .A1(n2946), .B0(n721), .B1(n2960), .Y(n2941)
);
OAI22X4TS U3999 ( .A0(n1141), .A1(n2961), .B0(n1119), .B1(n2967), .Y(n2883)
);
ADDFHX4TS U4000 ( .A(n2887), .B(n2886), .CI(n2885), .CO(n2952), .S(n2888) );
ADDFHX4TS U4001 ( .A(n2896), .B(n2894), .CI(n2895), .CO(n2889), .S(n2929) );
CMPR22X2TS U4002 ( .A(n2901), .B(n2900), .CO(n2926), .S(n2917) );
ADDFHX4TS U4003 ( .A(n2934), .B(n2933), .CI(n2932), .CO(n2935), .S(n2928) );
ADDFHX4TS U4004 ( .A(n2956), .B(n2955), .CI(n2954), .CO(n2974), .S(n2972) );
OAI22X1TS U4005 ( .A0(n1340), .A1(Op_MX[17]), .B0(n720), .B1(n1852), .Y(
n2968) );
NOR2X1TS U4006 ( .A(n1520), .B(n2967), .Y(n2980) );
OAI22X1TS U4007 ( .A0(n1340), .A1(n1852), .B0(n1520), .B1(Op_MX[17]), .Y(
n2979) );
INVX2TS U4008 ( .A(n3440), .Y(n2983) );
INVX2TS U4009 ( .A(n2987), .Y(n2988) );
NAND2X1TS U4010 ( .A(n1366), .B(n2996), .Y(n2997) );
ADDFHX4TS U4011 ( .A(n3005), .B(n3004), .CI(n3003), .CO(n2865), .S(n3010) );
XNOR2X4TS U4012 ( .A(n3028), .B(n3027), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N8)
);
NOR2X1TS U4013 ( .A(n401), .B(net287910), .Y(n3042) );
INVX2TS U4014 ( .A(net287247), .Y(net287906) );
INVX2TS U4015 ( .A(n3046), .Y(n3048) );
NAND2X2TS U4016 ( .A(n3048), .B(n3047), .Y(n3049) );
NOR2X2TS U4017 ( .A(n3108), .B(n3246), .Y(n3050) );
INVX2TS U4018 ( .A(n3081), .Y(n3052) );
NAND2X2TS U4019 ( .A(n3051), .B(n3050), .Y(n3079) );
NOR2X2TS U4020 ( .A(n3107), .B(n3246), .Y(n3073) );
NOR2X2TS U4021 ( .A(n3106), .B(n3247), .Y(n3072) );
NAND2X2TS U4022 ( .A(n3073), .B(n3072), .Y(n3080) );
XOR2X1TS U4023 ( .A(n3057), .B(n3066), .Y(n3060) );
INVX2TS U4024 ( .A(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N2),
.Y(n3059) );
INVX2TS U4025 ( .A(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N2),
.Y(n3058) );
OR2X2TS U4026 ( .A(n3062), .B(n3061), .Y(n3063) );
OR2X2TS U4027 ( .A(n3065), .B(n3064), .Y(n3067) );
AND2X4TS U4028 ( .A(n3067), .B(n3066), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N1)
);
XNOR2X1TS U4029 ( .A(n4026), .B(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N1),
.Y(n4027) );
INVX2TS U4030 ( .A(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N0),
.Y(n4028) );
OR2X2TS U4031 ( .A(n3073), .B(n3072), .Y(n3074) );
NOR2X1TS U4032 ( .A(n1837), .B(n3246), .Y(n3087) );
ADDHX1TS U4033 ( .A(n3076), .B(n3075), .CO(n3085), .S(n3051) );
NAND2X1TS U4034 ( .A(n3094), .B(n3091), .Y(n3082) );
XNOR2X1TS U4035 ( .A(n3082), .B(n3093), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N3)
);
ADDHX1TS U4036 ( .A(n3084), .B(n3083), .CO(n3132), .S(n3077) );
INVX2TS U4037 ( .A(n3135), .Y(n3090) );
NAND2X1TS U4038 ( .A(n3090), .B(n3134), .Y(n3095) );
XOR2X1TS U4039 ( .A(n3095), .B(n3136), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N4)
);
NOR2X1TS U4040 ( .A(n3178), .B(n3102), .Y(n3113) );
NOR2X1TS U4041 ( .A(n3178), .B(n3106), .Y(n3120) );
NOR2X1TS U4042 ( .A(n3185), .B(n3102), .Y(n3098) );
NOR2X1TS U4043 ( .A(n3178), .B(n3177), .Y(n3164) );
NOR2X1TS U4044 ( .A(n881), .B(n3102), .Y(n3162) );
NOR2X1TS U4045 ( .A(n881), .B(n3106), .Y(n3105) );
NOR2X1TS U4046 ( .A(n876), .B(n3108), .Y(n3104) );
CMPR32X2TS U4047 ( .A(n3105), .B(n3104), .C(n3103), .CO(n3159), .S(n3119) );
NOR2X1TS U4048 ( .A(n3177), .B(n3107), .Y(n3130) );
NOR2X1TS U4049 ( .A(n3108), .B(n3158), .Y(n3129) );
ADDHX1TS U4050 ( .A(n3110), .B(n3109), .CO(n3128), .S(n3133) );
NOR2X2TS U4051 ( .A(n3185), .B(n3246), .Y(n3141) );
NOR2X1TS U4052 ( .A(n881), .B(n3158), .Y(n3176) );
NOR2X1TS U4053 ( .A(n876), .B(n3178), .Y(n3175) );
NOR2X1TS U4054 ( .A(n3185), .B(n3177), .Y(n3181) );
NOR2X1TS U4055 ( .A(n881), .B(n3177), .Y(n3188) );
NOR2X1TS U4056 ( .A(n876), .B(n881), .Y(n3191) );
CMPR32X2TS U4057 ( .A(n3188), .B(n3187), .C(n3186), .CO(n3189), .S(n3183) );
NAND2X1TS U4058 ( .A(n3213), .B(n3201), .Y(n3203) );
NAND2X2TS U4059 ( .A(n3194), .B(n3195), .Y(n3222) );
NAND2X2TS U4060 ( .A(n3197), .B(n3196), .Y(n3217) );
OAI21X1TS U4061 ( .A0(n3217), .A1(n3208), .B0(n3209), .Y(n3200) );
INVX2TS U4062 ( .A(n3217), .Y(n3205) );
INVX2TS U4063 ( .A(n3208), .Y(n3210) );
INVX2TS U4064 ( .A(n3213), .Y(n3216) );
INVX2TS U4065 ( .A(n3221), .Y(n3223) );
NAND2X1TS U4066 ( .A(n3223), .B(n3222), .Y(n3224) );
XOR2X1TS U4067 ( .A(n3236), .B(n3235), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N7)
);
INVX2TS U4068 ( .A(n3237), .Y(n3239) );
NAND2X2TS U4069 ( .A(n3243), .B(n3242), .Y(n3245) );
XNOR2X1TS U4070 ( .A(n3245), .B(n3244), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N5)
);
MX2X6TS U4071 ( .A(Data_MY[7]), .B(Op_MY[7]), .S0(net287583), .Y(n319) );
MX2X6TS U4072 ( .A(Data_MY[9]), .B(Op_MY[9]), .S0(net287583), .Y(n321) );
INVX2TS U4073 ( .A(n3276), .Y(n3250) );
NAND2X2TS U4074 ( .A(n3250), .B(n3278), .Y(n3251) );
XOR2X4TS U4075 ( .A(n3252), .B(n3251), .Y(n4499) );
MX2X6TS U4076 ( .A(Data_MY[10]), .B(n1157), .S0(net287583), .Y(n322) );
MX2X6TS U4077 ( .A(Data_MY[22]), .B(Op_MY[22]), .S0(net287652), .Y(n334) );
MX2X6TS U4078 ( .A(Data_MY[15]), .B(Op_MY[15]), .S0(net286914), .Y(n327) );
MX2X6TS U4079 ( .A(Data_MY[3]), .B(Op_MY[3]), .S0(net287652), .Y(n315) );
NAND2X2TS U4080 ( .A(n327), .B(n315), .Y(n3277) );
NAND2X2TS U4081 ( .A(n3253), .B(n3277), .Y(n3254) );
MX2X6TS U4082 ( .A(Data_MX[13]), .B(Op_MX[13]), .S0(net287583), .Y(n357) );
MX2X6TS U4083 ( .A(Data_MX[1]), .B(Op_MX[1]), .S0(net287641), .Y(n345) );
MX2X6TS U4084 ( .A(Data_MX[12]), .B(Op_MX[12]), .S0(net287583), .Y(n356) );
MX2X6TS U4085 ( .A(Data_MX[0]), .B(Op_MX[0]), .S0(net287641), .Y(n344) );
MX2X6TS U4086 ( .A(Data_MX[14]), .B(Op_MX[14]), .S0(net287583), .Y(n358) );
MX2X6TS U4087 ( .A(Data_MX[2]), .B(Op_MX[2]), .S0(net287633), .Y(n346) );
MX2X6TS U4088 ( .A(Data_MX[15]), .B(Op_MX[15]), .S0(net287641), .Y(n359) );
MX2X6TS U4089 ( .A(Data_MX[3]), .B(Op_MX[3]), .S0(net287633), .Y(n347) );
NOR2X4TS U4090 ( .A(n359), .B(n347), .Y(n3285) );
NAND2X2TS U4091 ( .A(n359), .B(n347), .Y(n3284) );
NAND2X1TS U4092 ( .A(n3260), .B(n3259), .Y(n3262) );
XNOR2X1TS U4093 ( .A(n3262), .B(n3261), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N3)
);
NAND2X1TS U4094 ( .A(n1849), .B(n3263), .Y(n3264) );
XNOR2X1TS U4095 ( .A(n3264), .B(n1047), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N3)
);
INVX2TS U4096 ( .A(n3266), .Y(n3268) );
NAND2X2TS U4097 ( .A(n3268), .B(n3267), .Y(n3269) );
XOR2X4TS U4098 ( .A(n3269), .B(n3271), .Y(n4503) );
OR2X4TS U4099 ( .A(n4503), .B(n3273), .Y(n4111) );
OR2X2TS U4100 ( .A(n356), .B(n344), .Y(n3272) );
AND2X4TS U4101 ( .A(n3272), .B(n3271), .Y(n4497) );
NAND2X2TS U4102 ( .A(n4503), .B(n3273), .Y(n4067) );
MX2X6TS U4103 ( .A(Data_MY[16]), .B(Op_MY[16]), .S0(net286914), .Y(n328) );
MX2X6TS U4104 ( .A(Data_MY[4]), .B(Op_MY[4]), .S0(net287652), .Y(n316) );
MX2X6TS U4105 ( .A(Data_MY[6]), .B(Op_MY[6]), .S0(net287583), .Y(n318) );
NOR2X4TS U4106 ( .A(n328), .B(n316), .Y(n3388) );
AND2X2TS U4107 ( .A(n3394), .B(n3396), .Y(n3283) );
INVX2TS U4108 ( .A(n3395), .Y(n3281) );
MX2X6TS U4109 ( .A(Data_MX[18]), .B(Op_MX[18]), .S0(net287641), .Y(n362) );
MX2X6TS U4110 ( .A(Data_MX[6]), .B(Op_MX[6]), .S0(net287633), .Y(n350) );
MX2X6TS U4111 ( .A(Data_MX[16]), .B(Op_MX[16]), .S0(net287641), .Y(n360) );
NOR2X2TS U4112 ( .A(n3318), .B(n3285), .Y(n3287) );
NOR2X4TS U4113 ( .A(n360), .B(n348), .Y(n3292) );
AOI21X1TS U4114 ( .A0(n3332), .A1(n3327), .B0(n3329), .Y(n4062) );
NAND2X1TS U4115 ( .A(n1099), .B(n1097), .Y(n4085) );
XNOR2X1TS U4116 ( .A(n322), .B(n334), .Y(n4073) );
INVX2TS U4117 ( .A(n3292), .Y(n3289) );
XNOR2X4TS U4118 ( .A(n3332), .B(n3290), .Y(n4495) );
MX2X6TS U4119 ( .A(Data_MX[11]), .B(Op_MX[11]), .S0(net287633), .Y(n355) );
INVX2TS U4120 ( .A(n3294), .Y(n3296) );
INVX2TS U4121 ( .A(n1545), .Y(n3306) );
ADDFHX4TS U4122 ( .A(n3309), .B(n3308), .CI(n3307), .CO(n3343), .S(n3300) );
NAND2X2TS U4123 ( .A(n3312), .B(n3387), .Y(n3313) );
INVX2TS U4124 ( .A(n3314), .Y(n3316) );
NAND2X2TS U4125 ( .A(n3316), .B(n3315), .Y(n3317) );
OAI21X1TS U4126 ( .A0(n4035), .A1(n4499), .B0(n4498), .Y(n4055) );
NOR2X2TS U4127 ( .A(n4052), .B(n4049), .Y(n4084) );
INVX2TS U4128 ( .A(n3318), .Y(n3320) );
NAND2X2TS U4129 ( .A(n3320), .B(n3319), .Y(n3321) );
CLKXOR2X2TS U4130 ( .A(n3322), .B(n3321), .Y(n4496) );
OAI21X1TS U4131 ( .A0(n1123), .A1(n1098), .B0(n3325), .Y(n4065) );
AND2X4TS U4132 ( .A(n3324), .B(n3323), .Y(n4484) );
OAI21X1TS U4133 ( .A0(n4484), .A1(n4032), .B0(n3325), .Y(n4087) );
NOR2X2TS U4134 ( .A(n4497), .B(n3326), .Y(n4070) );
AND2X2TS U4135 ( .A(n3327), .B(n4107), .Y(n3331) );
INVX2TS U4136 ( .A(n4041), .Y(n3328) );
NOR2X2TS U4137 ( .A(n363), .B(n351), .Y(n4090) );
NOR2X1TS U4138 ( .A(n4090), .B(n3333), .Y(n4097) );
OAI21X1TS U4139 ( .A0(n1099), .A1(n1097), .B0(n1121), .Y(n4059) );
BUFX3TS U4140 ( .A(n1130), .Y(n4441) );
CLKBUFX3TS U4141 ( .A(n4441), .Y(n3631) );
CLKBUFX3TS U4142 ( .A(n1101), .Y(n4105) );
MX2X6TS U4143 ( .A(Data_MY[11]), .B(n1050), .S0(net287583), .Y(n323) );
XOR2X1TS U4144 ( .A(n3338), .B(n3337), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N4)
);
INVX4TS U4145 ( .A(n3340), .Y(n3341) );
INVX2TS U4146 ( .A(n3348), .Y(n3349) );
NOR2X2TS U4147 ( .A(n3349), .B(n437), .Y(n3364) );
INVX2TS U4148 ( .A(n3364), .Y(n3360) );
INVX2TS U4149 ( .A(n1560), .Y(n3363) );
NOR2X1TS U4150 ( .A(n3363), .B(n3366), .Y(n3365) );
XOR3X2TS U4151 ( .A(n3366), .B(n3365), .C(n3364), .Y(n3367) );
NAND2X2TS U4152 ( .A(n3371), .B(n3370), .Y(n3373) );
INVX2TS U4153 ( .A(n3378), .Y(n3380) );
XOR2X1TS U4154 ( .A(n3382), .B(n3381), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N4)
);
NAND2X2TS U4155 ( .A(n1584), .B(n3384), .Y(n3385) );
INVX2TS U4156 ( .A(n3389), .Y(n3391) );
NOR2X2TS U4157 ( .A(n4498), .B(n4033), .Y(n4086) );
CLKBUFX3TS U4158 ( .A(n1100), .Y(n3521) );
BUFX3TS U4159 ( .A(n3521), .Y(n4102) );
BUFX3TS U4160 ( .A(n4542), .Y(n4104) );
BUFX3TS U4161 ( .A(n3521), .Y(n4103) );
BUFX3TS U4162 ( .A(n3521), .Y(n4101) );
NAND2X2TS U4163 ( .A(n3434), .B(n3433), .Y(n4129) );
AND2X2TS U4164 ( .A(mult_x_58_a_5_), .B(mult_x_58_b_4_), .Y(n3402) );
AND2X2TS U4165 ( .A(mult_x_58_b_5_), .B(mult_x_58_a_5_), .Y(n3415) );
CMPR32X2TS U4166 ( .A(n3402), .B(n3401), .C(mult_x_58_n13), .CO(n3416), .S(
n3405) );
INVX2TS U4167 ( .A(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N9),
.Y(n4146) );
INVX2TS U4168 ( .A(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N3),
.Y(n3423) );
INVX2TS U4169 ( .A(n3410), .Y(n3412) );
NOR2X2TS U4170 ( .A(n4127), .B(n4124), .Y(n4142) );
AND2X4TS U4171 ( .A(mult_x_57_b_0_), .B(mult_x_57_a_0_), .Y(
DP_OP_156J21_125_3370_n360) );
INVX2TS U4172 ( .A(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N9),
.Y(DP_OP_155J21_124_2814_net274901) );
INVX2TS U4173 ( .A(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N4),
.Y(n3421) );
OR2X2TS U4174 ( .A(net287455), .B(n3425), .Y(n3427) );
OR2X2TS U4175 ( .A(n1843), .B(n3432), .Y(n3430) );
CMPR32X2TS U4176 ( .A(n3429), .B(n934), .C(net287451), .CO(n4124), .S(n3431)
);
NAND2X2TS U4177 ( .A(n3431), .B(n3430), .Y(n4140) );
XNOR2X1TS U4178 ( .A(n1843), .B(n3432), .Y(n3436) );
NOR2X2TS U4179 ( .A(n3436), .B(n940), .Y(n4141) );
OR2X4TS U4180 ( .A(n3434), .B(n3433), .Y(n4151) );
AOI21X1TS U4181 ( .A0(n4151), .A1(n4125), .B0(n3435), .Y(n4134) );
NAND2X2TS U4182 ( .A(n3436), .B(n940), .Y(n4135) );
OAI21X1TS U4183 ( .A0(n4141), .A1(n4134), .B0(n4135), .Y(n4143) );
NOR2X2TS U4184 ( .A(n1123), .B(n1087), .Y(n4153) );
NAND2X2TS U4185 ( .A(n1123), .B(n1087), .Y(n4158) );
OAI21X1TS U4186 ( .A0(n4153), .A1(n4152), .B0(n4158), .Y(n4157) );
NOR2X2TS U4187 ( .A(n1097), .B(n327), .Y(n4154) );
NAND2X4TS U4188 ( .A(n1040), .B(n326), .Y(n4160) );
NAND2X2TS U4189 ( .A(n1097), .B(n327), .Y(n4156) );
OAI21X1TS U4190 ( .A0(n4154), .A1(n4160), .B0(n4156), .Y(n4159) );
BUFX3TS U4191 ( .A(n3631), .Y(n4162) );
INVX2TS U4192 ( .A(n4155), .Y(n3448) );
AND2X2TS U4193 ( .A(n366), .B(n1097), .Y(n4185) );
AND2X2TS U4194 ( .A(n1040), .B(n365), .Y(n3452) );
AND2X2TS U4195 ( .A(n1096), .B(n362), .Y(n3458) );
CMPR32X2TS U4196 ( .A(n3459), .B(n3458), .C(n3457), .CO(n4167), .S(n4168) );
AND2X2TS U4197 ( .A(n1097), .B(n365), .Y(n3462) );
AND2X2TS U4198 ( .A(n366), .B(n1040), .Y(n3461) );
CMPR32X2TS U4199 ( .A(n3462), .B(n3461), .C(n3460), .CO(n4179), .S(n4180) );
OR2X2TS U4200 ( .A(n3473), .B(n3472), .Y(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N11)
);
ADDHX1TS U4201 ( .A(n3477), .B(n3476), .CO(n3451), .S(n4166) );
BUFX3TS U4202 ( .A(n4440), .Y(n4192) );
AND2X2TS U4203 ( .A(mult_x_57_b_5_), .B(mult_x_57_a_3_), .Y(mult_x_57_n58)
);
AND2X2TS U4204 ( .A(n1038), .B(n347), .Y(n3480) );
AND2X2TS U4205 ( .A(n317), .B(n344), .Y(n3479) );
AND2X2TS U4206 ( .A(n315), .B(n346), .Y(n3478) );
CMPR32X2TS U4207 ( .A(n3480), .B(n3479), .C(n3478), .CO(n4211), .S(n4212) );
AND2X2TS U4208 ( .A(n315), .B(n347), .Y(n3483) );
AND2X2TS U4209 ( .A(n316), .B(n346), .Y(n3481) );
CMPR32X2TS U4210 ( .A(n3483), .B(n3482), .C(n3481), .CO(n4217), .S(n4218) );
AND2X2TS U4211 ( .A(n315), .B(n344), .Y(n3485) );
AND2X2TS U4212 ( .A(n1038), .B(n344), .Y(n3492) );
CMPR32X2TS U4213 ( .A(n3486), .B(n3485), .C(n3484), .CO(n4215), .S(n4216) );
AND2X2TS U4214 ( .A(n317), .B(n346), .Y(n4205) );
AND2X2TS U4215 ( .A(n1116), .B(n347), .Y(n3488) );
ADDHX1TS U4216 ( .A(n3492), .B(n3491), .CO(n3484), .S(n4200) );
AND2X2TS U4217 ( .A(n1116), .B(n348), .Y(n3494) );
AND2X2TS U4218 ( .A(n349), .B(n312), .Y(n3493) );
ADDHX1TS U4219 ( .A(n3494), .B(n3493), .CO(n4197), .S(n4198) );
BUFX3TS U4220 ( .A(n3521), .Y(n4220) );
CLKBUFX3TS U4221 ( .A(n3521), .Y(n4219) );
BUFX3TS U4222 ( .A(n3521), .Y(n4221) );
AND2X2TS U4223 ( .A(n1099), .B(n354), .Y(n4251) );
AND2X2TS U4224 ( .A(n1120), .B(n353), .Y(n3499) );
AND2X2TS U4225 ( .A(n321), .B(n352), .Y(n3497) );
AND2X2TS U4226 ( .A(n318), .B(n352), .Y(n3501) );
AND2X2TS U4227 ( .A(n321), .B(n353), .Y(n3505) );
AND2X2TS U4228 ( .A(n322), .B(n352), .Y(n3503) );
CMPR32X2TS U4229 ( .A(n3505), .B(n3504), .C(n3503), .CO(n4244), .S(n4245) );
AND2X2TS U4230 ( .A(mult_x_58_b_5_), .B(n1045), .Y(mult_x_58_n58) );
AND2X2TS U4231 ( .A(n355), .B(n1121), .Y(n4247) );
AND2X2TS U4232 ( .A(mult_x_58_a_5_), .B(mult_x_58_b_3_), .Y(mult_x_58_n48)
);
AND2X2TS U4233 ( .A(mult_x_58_b_4_), .B(mult_x_58_a_4_), .Y(mult_x_58_n53)
);
AND2X2TS U4234 ( .A(n323), .B(n352), .Y(n4246) );
AND2X2TS U4235 ( .A(n355), .B(n1115), .Y(n3511) );
AND2X2TS U4236 ( .A(mult_x_58_b_4_), .B(n1045), .Y(mult_x_58_n59) );
AND2X2TS U4237 ( .A(n1120), .B(n354), .Y(n3520) );
AND2X2TS U4238 ( .A(n355), .B(n1098), .Y(n3519) );
BUFX3TS U4239 ( .A(n3521), .Y(n4254) );
BUFX3TS U4240 ( .A(n3521), .Y(n4253) );
BUFX3TS U4241 ( .A(n3521), .Y(n4252) );
AND2X2TS U4242 ( .A(n327), .B(n357), .Y(n4257) );
AND2X2TS U4243 ( .A(n328), .B(n357), .Y(n4268) );
AND2X2TS U4244 ( .A(n329), .B(n356), .Y(n3523) );
AND2X2TS U4245 ( .A(n327), .B(n358), .Y(n3522) );
AND2X2TS U4246 ( .A(n327), .B(n359), .Y(n3527) );
AND2X2TS U4247 ( .A(n329), .B(n357), .Y(n3526) );
AND2X2TS U4248 ( .A(n328), .B(n358), .Y(n3525) );
CMPR32X2TS U4249 ( .A(n3527), .B(n3526), .C(n3525), .CO(n4274), .S(n4275) );
AND2X2TS U4250 ( .A(mult_x_59_a_5_), .B(mult_x_59_b_3_), .Y(mult_x_59_n48)
);
AND2X2TS U4251 ( .A(n328), .B(n356), .Y(n4255) );
AND2X2TS U4252 ( .A(n327), .B(n356), .Y(n3531) );
CMPR32X2TS U4253 ( .A(n3535), .B(n3534), .C(n3533), .CO(n3536), .S(n4269) );
CMPR32X2TS U4254 ( .A(mult_x_59_n37), .B(mult_x_59_n40), .C(mult_x_59_n8),
.CO(n3545), .S(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N4)
);
CMPR32X2TS U4255 ( .A(mult_x_59_n30), .B(mult_x_59_n36), .C(n3545), .CO(
n3546), .S(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N5)
);
CMPR32X2TS U4256 ( .A(mult_x_59_n23), .B(mult_x_59_n29), .C(n3546), .CO(
n3547), .S(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N6)
);
AND2X2TS U4257 ( .A(mult_x_59_b_5_), .B(mult_x_59_a_4_), .Y(n3549) );
CMPR32X2TS U4258 ( .A(n3550), .B(n3549), .C(mult_x_59_n13), .CO(n3555), .S(
n3552) );
AND2X2TS U4259 ( .A(mult_x_59_b_5_), .B(mult_x_59_a_5_), .Y(n3554) );
AND2X2TS U4260 ( .A(n326), .B(n360), .Y(n3560) );
BUFX3TS U4261 ( .A(n4543), .Y(n4283) );
BUFX3TS U4262 ( .A(n3631), .Y(n4284) );
INVX2TS U4263 ( .A(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N4),
.Y(n3565) );
INVX2TS U4264 ( .A(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N4),
.Y(n3564) );
NOR2X4TS U4265 ( .A(n1119), .B(n3567), .Y(n3573) );
NAND2X2TS U4266 ( .A(n3574), .B(n3573), .Y(n4294) );
INVX2TS U4267 ( .A(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N11),
.Y(n4310) );
INVX2TS U4268 ( .A(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N9),
.Y(n4305) );
INVX2TS U4269 ( .A(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N8),
.Y(n4301) );
AND2X4TS U4270 ( .A(n3570), .B(n3594), .Y(n3571) );
OR2X4TS U4271 ( .A(n1845), .B(n3571), .Y(n4300) );
NAND2X2TS U4272 ( .A(n3572), .B(n941), .Y(n4302) );
NOR2X2TS U4273 ( .A(n3572), .B(n941), .Y(n4299) );
OR2X4TS U4274 ( .A(n3574), .B(n3573), .Y(n4312) );
INVX2TS U4275 ( .A(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N0),
.Y(n4291) );
AOI21X1TS U4276 ( .A0(n4312), .A1(n4291), .B0(n3575), .Y(n4296) );
OAI21X1TS U4277 ( .A0(n4299), .A1(n4296), .B0(n4302), .Y(n4303) );
INVX2TS U4278 ( .A(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N5),
.Y(n3584) );
INVX2TS U4279 ( .A(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N5),
.Y(n3583) );
INVX2TS U4280 ( .A(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N3),
.Y(n3589) );
INVX2TS U4281 ( .A(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N9),
.Y(n4306) );
INVX2TS U4282 ( .A(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N8),
.Y(n4295) );
INVX2TS U4283 ( .A(n3591), .Y(n3593) );
XOR2X1TS U4284 ( .A(n3595), .B(n3594), .Y(n3596) );
CMPR32X2TS U4285 ( .A(n3596), .B(n1844), .C(n1842), .CO(n4285), .S(n4286) );
NAND2X2TS U4286 ( .A(n1121), .B(n1038), .Y(n4317) );
NOR2X4TS U4287 ( .A(n1121), .B(n1038), .Y(n4316) );
INVX2TS U4288 ( .A(n4316), .Y(n3597) );
NAND2X1TS U4289 ( .A(n1099), .B(n315), .Y(n4318) );
NOR2X2TS U4290 ( .A(n1098), .B(n1116), .Y(n4314) );
NAND2X4TS U4291 ( .A(n1098), .B(n1116), .Y(n4320) );
NAND2X2TS U4292 ( .A(n318), .B(n312), .Y(n4313) );
OAI21X1TS U4293 ( .A0(n4314), .A1(n4313), .B0(n4320), .Y(n4319) );
NOR2X2TS U4294 ( .A(n1099), .B(n315), .Y(n4315) );
NOR2X1TS U4295 ( .A(n4316), .B(n4315), .Y(n4322) );
BUFX3TS U4296 ( .A(n4542), .Y(n4323) );
NOR2X1TS U4297 ( .A(n4125), .B(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N0),
.Y(n4331) );
BUFX3TS U4298 ( .A(n4535), .Y(n4442) );
CLKBUFX2TS U4299 ( .A(n4442), .Y(n4347) );
INVX2TS U4300 ( .A(DP_OP_156J21_125_3370_n82), .Y(DP_OP_156J21_125_3370_n84)
);
CLKBUFX3TS U4301 ( .A(n4537), .Y(n4443) );
CLKBUFX3TS U4302 ( .A(n1093), .Y(n4538) );
CLKBUFX3TS U4303 ( .A(n4443), .Y(n4346) );
INVX2TS U4304 ( .A(add_x_19_n106), .Y(n3602) );
NAND2X4TS U4305 ( .A(n3601), .B(n3602), .Y(add_x_19_n104) );
NOR2X2TS U4306 ( .A(add_x_19_n104), .B(n3604), .Y(add_x_19_n85) );
INVX2TS U4307 ( .A(add_x_19_n104), .Y(n3605) );
CLKBUFX2TS U4308 ( .A(n4443), .Y(n4382) );
CLKBUFX2TS U4309 ( .A(n4382), .Y(n4383) );
BUFX3TS U4310 ( .A(n4442), .Y(n4384) );
CLKBUFX3TS U4311 ( .A(n4445), .Y(n4381) );
INVX2TS U4312 ( .A(n3609), .Y(n3611) );
NAND2X2TS U4313 ( .A(n3625), .B(n866), .Y(add_x_19_n57) );
INVX2TS U4314 ( .A(n3622), .Y(add_x_19_n40) );
AOI21X4TS U4315 ( .A0(n1826), .A1(n3807), .B0(n915), .Y(n3630) );
NAND2X2TS U4316 ( .A(n1821), .B(n3628), .Y(n3629) );
INVX2TS U4317 ( .A(add_x_19_n76), .Y(add_x_19_n75) );
CLKBUFX2TS U4318 ( .A(n4445), .Y(n4380) );
CLKBUFX2TS U4319 ( .A(n4535), .Y(n4446) );
BUFX3TS U4320 ( .A(n1103), .Y(n4541) );
BUFX3TS U4321 ( .A(n1132), .Y(n4440) );
BUFX3TS U4322 ( .A(n4542), .Y(n4539) );
BUFX3TS U4323 ( .A(n1101), .Y(n4540) );
BUFX3TS U4324 ( .A(n4440), .Y(n4447) );
CLKBUFX2TS U4325 ( .A(n4538), .Y(n4444) );
NAND2X1TS U4326 ( .A(FS_Module_state_reg[2]), .B(FS_Module_state_reg[3]),
.Y(n3845) );
NOR2X2TS U4327 ( .A(n3632), .B(n3845), .Y(ready) );
INVX2TS U4328 ( .A(ack_FSM), .Y(n3633) );
NAND2X2TS U4329 ( .A(ready), .B(n3633), .Y(n3860) );
NOR2XLTS U4330 ( .A(n1853), .B(FS_Module_state_reg[2]), .Y(n3634) );
MXI2X1TS U4331 ( .A(n3635), .B(n3634), .S0(FS_Module_state_reg[1]), .Y(n3636) );
INVX2TS U4332 ( .A(Sgf_operation_Result[0]), .Y(n3637) );
INVX8TS U4333 ( .A(n1850), .Y(n3910) );
MXI2X1TS U4334 ( .A(n3637), .B(n4419), .S0(n1091), .Y(n215) );
XOR2X1TS U4335 ( .A(n4378), .B(n4379), .Y(n3639) );
XNOR2X1TS U4336 ( .A(n4367), .B(n4368), .Y(n3640) );
XNOR2X1TS U4337 ( .A(n4365), .B(n4366), .Y(n3641) );
NOR4X1TS U4338 ( .A(P_Sgf[16]), .B(P_Sgf[14]), .C(P_Sgf[15]), .D(P_Sgf[13]),
.Y(n3644) );
NOR4X1TS U4339 ( .A(P_Sgf[12]), .B(P_Sgf[11]), .C(P_Sgf[10]), .D(P_Sgf[9]),
.Y(n3643) );
NOR3X1TS U4340 ( .A(n237), .B(n236), .C(P_Sgf[0]), .Y(n3642) );
NAND4X1TS U4341 ( .A(n3645), .B(n3644), .C(n3643), .D(n3642), .Y(n3649) );
NOR4X1TS U4342 ( .A(P_Sgf[8]), .B(P_Sgf[7]), .C(P_Sgf[6]), .D(P_Sgf[5]), .Y(
n3647) );
NOR4X1TS U4343 ( .A(P_Sgf[1]), .B(P_Sgf[2]), .C(P_Sgf[3]), .D(P_Sgf[4]), .Y(
n3646) );
NAND2X1TS U4344 ( .A(n3647), .B(n3646), .Y(n3648) );
XNOR2X1TS U4345 ( .A(Op_MX[31]), .B(Op_MY[31]), .Y(n3861) );
MXI2X2TS U4346 ( .A(n4494), .B(n4493), .S0(n793), .Y(underflow_flag) );
BUFX8TS U4347 ( .A(n3904), .Y(n3871) );
AO22X2TS U4348 ( .A0(n3871), .A1(Sgf_normalized_result[22]), .B0(
final_result_ieee[22]), .B1(n3905), .Y(n167) );
NAND2X1TS U4349 ( .A(n1848), .B(n4376), .Y(n3658) );
AOI21X1TS U4350 ( .A0(n3687), .A1(n4360), .B0(n4361), .Y(n3657) );
OAI21X1TS U4351 ( .A0(n826), .A1(n3658), .B0(n3657), .Y(n3663) );
INVX2TS U4352 ( .A(n3659), .Y(n3661) );
NAND2X1TS U4353 ( .A(n3661), .B(n3660), .Y(n3662) );
XNOR2X1TS U4354 ( .A(n3663), .B(n3662), .Y(n3664) );
OAI21X1TS U4355 ( .A0(n826), .A1(n1847), .B0(n3656), .Y(n3665) );
XNOR2X1TS U4356 ( .A(n3665), .B(n4359), .Y(n3666) );
AOI22X1TS U4357 ( .A0(n3873), .A1(Add_result[2]), .B0(
Sgf_normalized_result[1]), .B1(n3858), .Y(n3671) );
NAND2X1TS U4358 ( .A(n3850), .B(n239), .Y(n3669) );
INVX2TS U4359 ( .A(n3673), .Y(n3691) );
NAND2X1TS U4360 ( .A(n3676), .B(n1848), .Y(n3678) );
INVX2TS U4361 ( .A(n3674), .Y(n3686) );
AOI21X1TS U4362 ( .A0(n3687), .A1(n3676), .B0(n3675), .Y(n3677) );
INVX2TS U4363 ( .A(n3679), .Y(n3681) );
NAND2X1TS U4364 ( .A(n3681), .B(n3680), .Y(n3682) );
NAND2X1TS U4365 ( .A(n1848), .B(n3672), .Y(n3689) );
OAI21X1TS U4366 ( .A0(n826), .A1(n3689), .B0(n3688), .Y(n3693) );
NAND2X1TS U4367 ( .A(n3691), .B(n3690), .Y(n3692) );
XNOR2X1TS U4368 ( .A(n3693), .B(n3692), .Y(n3694) );
AOI22X1TS U4369 ( .A0(n3913), .A1(Add_result[4]), .B0(
Sgf_normalized_result[3]), .B1(n3858), .Y(n3697) );
NAND2X1TS U4370 ( .A(n3850), .B(n241), .Y(n3695) );
INVX2TS U4371 ( .A(n1531), .Y(n3700) );
NAND2X1TS U4372 ( .A(n3700), .B(n3699), .Y(n3701) );
XNOR2X1TS U4373 ( .A(n3702), .B(n3701), .Y(n3703) );
INVX2TS U4374 ( .A(n3704), .Y(n3706) );
NAND2X1TS U4375 ( .A(n3706), .B(n3705), .Y(n3707) );
XOR2X1TS U4376 ( .A(n3779), .B(n3707), .Y(n3708) );
INVX6TS U4377 ( .A(n3709), .Y(n3866) );
AOI22X1TS U4378 ( .A0(n3866), .A1(Add_result[6]), .B0(
Sgf_normalized_result[5]), .B1(n3858), .Y(n3712) );
NAND2X1TS U4379 ( .A(n3850), .B(n243), .Y(n3710) );
AOI22X1TS U4380 ( .A0(n3873), .A1(Add_result[5]), .B0(
Sgf_normalized_result[4]), .B1(n3858), .Y(n3717) );
INVX2TS U4381 ( .A(Add_result[4]), .Y(n3713) );
AOI22X1TS U4382 ( .A0(n3866), .A1(Add_result[3]), .B0(
Sgf_normalized_result[2]), .B1(n3858), .Y(n3720) );
NAND2X1TS U4383 ( .A(n3850), .B(n240), .Y(n3718) );
INVX2TS U4384 ( .A(n3721), .Y(n3723) );
INVX2TS U4385 ( .A(n3736), .Y(n3728) );
INVX2TS U4386 ( .A(n3726), .Y(n3727) );
AOI22X1TS U4387 ( .A0(n3913), .A1(Add_result[7]), .B0(
Sgf_normalized_result[6]), .B1(n3858), .Y(n3735) );
NAND2X2TS U4388 ( .A(n3850), .B(n244), .Y(n3733) );
INVX2TS U4389 ( .A(n3737), .Y(n3738) );
INVX2TS U4390 ( .A(n3742), .Y(n3744) );
NAND2X1TS U4391 ( .A(n3744), .B(n3743), .Y(n3745) );
AOI22X1TS U4392 ( .A0(n3873), .A1(Add_result[8]), .B0(
Sgf_normalized_result[7]), .B1(n3858), .Y(n3750) );
NAND2X1TS U4393 ( .A(n3915), .B(n245), .Y(n3748) );
INVX2TS U4394 ( .A(n873), .Y(n3752) );
INVX2TS U4395 ( .A(n870), .Y(n3751) );
OAI21X1TS U4396 ( .A0(n826), .A1(n4371), .B0(n4372), .Y(n3761) );
XNOR2X1TS U4397 ( .A(n3761), .B(n4364), .Y(n3762) );
NAND2X2TS U4398 ( .A(n3915), .B(n247), .Y(n3763) );
NAND2X2TS U4399 ( .A(n3800), .B(n249), .Y(n3766) );
INVX2TS U4400 ( .A(n3769), .Y(n3771) );
INVX12TS U4401 ( .A(n1850), .Y(n3804) );
AND2X2TS U4402 ( .A(n1639), .B(n3780), .Y(n3781) );
NAND2X1TS U4403 ( .A(n3923), .B(n3910), .Y(n4547) );
NAND2X1TS U4404 ( .A(n3804), .B(n3791), .Y(n4580) );
AND2X8TS U4405 ( .A(n3804), .B(n4585), .Y(n4584) );
NOR2X2TS U4406 ( .A(n3978), .B(n3812), .Y(n3975) );
NAND2X1TS U4407 ( .A(n3968), .B(n3961), .Y(n3813) );
NAND2X2TS U4408 ( .A(n3975), .B(n3814), .Y(n3815) );
NAND2X2TS U4409 ( .A(n4005), .B(n4006), .Y(n3999) );
NAND2X1TS U4410 ( .A(Sgf_normalized_result[22]), .B(n307), .Y(n3817) );
NOR2X1TS U4411 ( .A(n3832), .B(n3817), .Y(n3818) );
AND2X2TS U4412 ( .A(n4010), .B(n3818), .Y(n3819) );
MXI2X2TS U4413 ( .A(n3821), .B(n3820), .S0(n4534), .Y(n282) );
NAND2X1TS U4414 ( .A(n3823), .B(n3827), .Y(n3824) );
INVX2TS U4415 ( .A(n1124), .Y(n3831) );
INVX2TS U4416 ( .A(n3832), .Y(n3833) );
NAND2X1TS U4417 ( .A(n4011), .B(n3834), .Y(n3836) );
INVX2TS U4418 ( .A(n307), .Y(n3835) );
XOR2X1TS U4419 ( .A(n3836), .B(n3835), .Y(n3837) );
INVX2TS U4420 ( .A(n3999), .Y(n3838) );
XOR2X1TS U4421 ( .A(n3839), .B(n4415), .Y(n3841) );
OR2X4TS U4422 ( .A(n1129), .B(beg_FSM), .Y(n3842) );
AOI21X1TS U4423 ( .A0(n1530), .A1(n3845), .B0(n3844), .Y(n3847) );
OAI21X1TS U4424 ( .A0(n3849), .A1(n3848), .B0(n3847), .Y(n377) );
NAND2X2TS U4425 ( .A(n3850), .B(n251), .Y(n4577) );
INVX2TS U4426 ( .A(n3853), .Y(n3854) );
NAND2X1TS U4427 ( .A(n3830), .B(n4418), .Y(n4581) );
CLKINVX1TS U4428 ( .A(n3855), .Y(n3859) );
NAND2X1TS U4429 ( .A(n3856), .B(zero_flag), .Y(n3857) );
NAND4X1TS U4430 ( .A(n3860), .B(n3859), .C(n3858), .D(n3857), .Y(n379) );
NAND2X1TS U4431 ( .A(n3861), .B(n4587), .Y(n3863) );
NAND2X1TS U4432 ( .A(n3863), .B(n3862), .Y(n3865) );
INVX2TS U4433 ( .A(final_result_ieee[31]), .Y(n3864) );
MXI2X1TS U4434 ( .A(n3865), .B(n3864), .S0(n3905), .Y(n262) );
CLKMX2X2TS U4435 ( .A(Data_MY[24]), .B(Op_MY[24]), .S0(net286914), .Y(n336)
);
CLKMX2X2TS U4436 ( .A(Data_MY[31]), .B(Op_MY[31]), .S0(net286914), .Y(n310)
);
CLKMX2X2TS U4437 ( .A(Data_MY[23]), .B(Op_MY[23]), .S0(net286914), .Y(n335)
);
CLKMX2X3TS U4438 ( .A(Data_MY[25]), .B(Op_MY[25]), .S0(net286911), .Y(n337)
);
CLKMX2X3TS U4439 ( .A(Data_MY[28]), .B(Op_MY[28]), .S0(net286911), .Y(n340)
);
CLKMX2X3TS U4440 ( .A(Data_MY[27]), .B(Op_MY[27]), .S0(net286911), .Y(n339)
);
CLKMX2X3TS U4441 ( .A(Data_MY[26]), .B(Op_MY[26]), .S0(net286911), .Y(n338)
);
CLKMX2X2TS U4442 ( .A(Data_MX[31]), .B(Op_MX[31]), .S0(net286914), .Y(n343)
);
CLKBUFX3TS U4443 ( .A(net286913), .Y(net286912) );
CLKMX2X2TS U4444 ( .A(Data_MX[29]), .B(Op_MX[29]), .S0(net286912), .Y(n373)
);
CLKMX2X2TS U4445 ( .A(Data_MX[30]), .B(Op_MX[30]), .S0(net286912), .Y(n374)
);
CLKMX2X2TS U4446 ( .A(Data_MX[25]), .B(Op_MX[25]), .S0(net286911), .Y(n369)
);
CLKMX2X3TS U4447 ( .A(Data_MX[24]), .B(Op_MX[24]), .S0(net286911), .Y(n368)
);
CLKMX2X2TS U4448 ( .A(Data_MX[26]), .B(Op_MX[26]), .S0(net286911), .Y(n370)
);
MXI2X1TS U4449 ( .A(n2118), .B(n4436), .S0(n3910), .Y(n217) );
MXI2X1TS U4450 ( .A(n2116), .B(n4435), .S0(n3910), .Y(n216) );
AOI22X1TS U4451 ( .A0(n3913), .A1(Add_result[16]), .B0(n3961), .B1(n3858),
.Y(n4572) );
AOI22X1TS U4452 ( .A0(n3913), .A1(Add_result[22]), .B0(n3991), .B1(n4533),
.Y(n4551) );
AOI22X1TS U4453 ( .A0(n3866), .A1(Add_result[15]), .B0(n3968), .B1(n3912),
.Y(n4576) );
AOI2BB2X1TS U4454 ( .B0(n3871), .B1(n4420), .A0N(n3870), .A1N(
final_result_ieee[26]), .Y(n267) );
INVX2TS U4455 ( .A(n275), .Y(n3867) );
AOI2BB2X1TS U4456 ( .B0(n3871), .B1(n3867), .A0N(n3870), .A1N(
final_result_ieee[28]), .Y(n265) );
INVX2TS U4457 ( .A(n274), .Y(n3868) );
AOI2BB2X1TS U4458 ( .B0(n3871), .B1(n3868), .A0N(n3870), .A1N(
final_result_ieee[29]), .Y(n264) );
AOI2BB2X1TS U4459 ( .B0(n3871), .B1(n4422), .A0N(n3870), .A1N(
final_result_ieee[25]), .Y(n268) );
AOI2BB2X1TS U4460 ( .B0(n3871), .B1(n4421), .A0N(n3870), .A1N(
final_result_ieee[23]), .Y(n270) );
INVX2TS U4461 ( .A(n276), .Y(n3869) );
AOI2BB2X1TS U4462 ( .B0(n3871), .B1(n3869), .A0N(n3870), .A1N(
final_result_ieee[27]), .Y(n266) );
MXI2X1TS U4463 ( .A(n2139), .B(n4439), .S0(n3910), .Y(n220) );
MXI2X1TS U4464 ( .A(n2126), .B(n4437), .S0(n3910), .Y(n218) );
MXI2X1TS U4465 ( .A(n3872), .B(n4438), .S0(n3910), .Y(n219) );
AOI22X1TS U4466 ( .A0(n3873), .A1(Add_result[14]), .B0(n3954), .B1(n3912),
.Y(n4579) );
AOI22X1TS U4467 ( .A0(n3873), .A1(Add_result[17]), .B0(n4005), .B1(n3912),
.Y(n4568) );
CLKMX2X2TS U4468 ( .A(n3878), .B(P_Sgf[10]), .S0(n440), .Y(n225) );
NOR4X1TS U4469 ( .A(Op_MX[24]), .B(Op_MX[27]), .C(Op_MX[26]), .D(Op_MX[28]),
.Y(n3882) );
NOR4X1TS U4470 ( .A(Op_MX[29]), .B(Op_MX[19]), .C(Op_MX[17]), .D(Op_MX[30]),
.Y(n3881) );
NAND4X1TS U4471 ( .A(n3882), .B(net286886), .C(n3881), .D(n3880), .Y(n3898)
);
NOR4X1TS U4472 ( .A(Op_MX[13]), .B(Op_MX[18]), .C(Op_MX[14]), .D(Op_MX[15]),
.Y(n3885) );
NOR4X1TS U4473 ( .A(Op_MX[1]), .B(Op_MX[2]), .C(Op_MX[3]), .D(Op_MX[16]),
.Y(n3884) );
NOR4X1TS U4474 ( .A(Op_MX[7]), .B(Op_MX[20]), .C(Op_MX[22]), .D(Op_MX[11]),
.Y(n3883) );
NAND4X1TS U4475 ( .A(n3885), .B(n3884), .C(net286882), .D(n3883), .Y(n3897)
);
NOR4X1TS U4476 ( .A(Op_MY[13]), .B(Op_MY[12]), .C(Op_MY[6]), .D(Op_MY[14]),
.Y(n3889) );
NOR4X1TS U4477 ( .A(Op_MY[20]), .B(Op_MY[22]), .C(Op_MY[18]), .D(n1050), .Y(
n3886) );
NAND4X1TS U4478 ( .A(n3889), .B(n3888), .C(n3887), .D(n3886), .Y(n3896) );
NOR4X1TS U4479 ( .A(Op_MY[24]), .B(Op_MY[28]), .C(Op_MY[27]), .D(Op_MY[26]),
.Y(n3894) );
NAND4X1TS U4480 ( .A(n3894), .B(n3893), .C(n3892), .D(n3891), .Y(n3895) );
OAI22X1TS U4481 ( .A0(n3898), .A1(n3897), .B0(n3896), .B1(n3895), .Y(n3899)
);
CLKMX2X2TS U4482 ( .A(n3899), .B(zero_flag), .S0(n4585), .Y(n311) );
CLKMX2X2TS U4483 ( .A(n3901), .B(P_Sgf[11]), .S0(n3910), .Y(n4412) );
INVX2TS U4484 ( .A(Add_result[0]), .Y(n3914) );
MXI2X1TS U4485 ( .A(Sgf_normalized_result[0]), .B(n3914), .S0(n4534), .Y(
n306) );
OR2X2TS U4486 ( .A(n3907), .B(n3906), .Y(n3909) );
AND2X2TS U4487 ( .A(n3909), .B(n3908), .Y(n3911) );
CLKMX2X2TS U4488 ( .A(n3911), .B(P_Sgf[12]), .S0(n3910), .Y(n4394) );
AOI22X1TS U4489 ( .A0(n3913), .A1(Add_result[1]), .B0(
Sgf_normalized_result[0]), .B1(n3912), .Y(n3918) );
NAND2X1TS U4490 ( .A(n3915), .B(n238), .Y(n3916) );
NAND3X1TS U4491 ( .A(n3918), .B(n3917), .C(n3916), .Y(n191) );
CLKMX2X2TS U4492 ( .A(n3919), .B(exp_oper_result[0]), .S0(n4584), .Y(n280)
);
XNOR2X1TS U4493 ( .A(Sgf_normalized_result[1]), .B(Sgf_normalized_result[0]),
.Y(n3920) );
INVX2TS U4494 ( .A(n3933), .Y(n3937) );
XNOR2X1TS U4495 ( .A(n3937), .B(Sgf_normalized_result[2]), .Y(n3934) );
CLKMX2X2TS U4496 ( .A(n3934), .B(Add_result[2]), .S0(n4534), .Y(n304) );
INVX2TS U4497 ( .A(n3935), .Y(n3950) );
XOR2X1TS U4498 ( .A(n3950), .B(Sgf_normalized_result[4]), .Y(n3936) );
CLKMX2X2TS U4499 ( .A(n3936), .B(Add_result[4]), .S0(n4534), .Y(n302) );
NOR2X1TS U4500 ( .A(n3937), .B(Sgf_normalized_result[2]), .Y(n3938) );
XOR2X1TS U4501 ( .A(n3938), .B(n4411), .Y(n3939) );
CLKMX2X2TS U4502 ( .A(n3939), .B(Add_result[3]), .S0(n4534), .Y(n303) );
XNOR2X1TS U4503 ( .A(n3984), .B(n4417), .Y(n3941) );
CLKMX2X2TS U4504 ( .A(n3941), .B(Add_result[8]), .S0(n3986), .Y(n298) );
NAND2X1TS U4505 ( .A(Sgf_normalized_result[5]), .B(Sgf_normalized_result[6]),
.Y(n3944) );
NAND2X1TS U4506 ( .A(n3942), .B(Sgf_normalized_result[6]), .Y(n3943) );
OAI21X1TS U4507 ( .A0(n3950), .A1(n3944), .B0(n3943), .Y(n3945) );
XNOR2X1TS U4508 ( .A(n3945), .B(n4426), .Y(n3946) );
CLKMX2X2TS U4509 ( .A(n3946), .B(Add_result[7]), .S0(n3986), .Y(n299) );
OAI21X1TS U4510 ( .A0(n3950), .A1(n4410), .B0(n3947), .Y(n3948) );
XNOR2X1TS U4511 ( .A(n3948), .B(n4425), .Y(n3949) );
CLKMX2X2TS U4512 ( .A(n3949), .B(Add_result[6]), .S0(n3986), .Y(n300) );
NAND2X1TS U4513 ( .A(n3950), .B(n4434), .Y(n3951) );
XNOR2X1TS U4514 ( .A(n3951), .B(n4410), .Y(n3952) );
CLKMX2X2TS U4515 ( .A(n3952), .B(Add_result[5]), .S0(n4534), .Y(n301) );
INVX2TS U4516 ( .A(n3975), .Y(n3966) );
NOR2X1TS U4517 ( .A(n3966), .B(n4414), .Y(n3953) );
NAND2X1TS U4518 ( .A(n3984), .B(n3953), .Y(n3956) );
INVX2TS U4519 ( .A(n3954), .Y(n3955) );
XOR2X1TS U4520 ( .A(n3956), .B(n3955), .Y(n3957) );
NAND2X1TS U4521 ( .A(n3958), .B(n3968), .Y(n3959) );
NOR2X1TS U4522 ( .A(n3966), .B(n3959), .Y(n3960) );
NAND2X1TS U4523 ( .A(n3984), .B(n3960), .Y(n3963) );
INVX2TS U4524 ( .A(n3961), .Y(n3962) );
XOR2X1TS U4525 ( .A(n3963), .B(n3962), .Y(n3964) );
NAND2X1TS U4526 ( .A(n3984), .B(n3967), .Y(n3970) );
INVX2TS U4527 ( .A(n3968), .Y(n3969) );
XOR2X1TS U4528 ( .A(n3970), .B(n3969), .Y(n3971) );
NOR2X1TS U4529 ( .A(n3978), .B(n4416), .Y(n3972) );
NAND2X1TS U4530 ( .A(n3984), .B(n3972), .Y(n3973) );
XOR2X1TS U4531 ( .A(n3973), .B(n4428), .Y(n3974) );
NAND2X1TS U4532 ( .A(n3984), .B(n3975), .Y(n3976) );
XOR2X1TS U4533 ( .A(n3976), .B(n4414), .Y(n3977) );
NAND2X1TS U4534 ( .A(n3984), .B(n3979), .Y(n3980) );
XOR2X1TS U4535 ( .A(n3980), .B(n4416), .Y(n3981) );
INVX2TS U4536 ( .A(n4005), .Y(n3982) );
XNOR2X1TS U4537 ( .A(n4011), .B(n3982), .Y(n3983) );
NAND2X1TS U4538 ( .A(n3984), .B(Sgf_normalized_result[8]), .Y(n3985) );
XOR2X1TS U4539 ( .A(n3985), .B(n4427), .Y(n3987) );
NOR2X1TS U4540 ( .A(n3989), .B(n4012), .Y(n3990) );
NAND2X1TS U4541 ( .A(n4011), .B(n3990), .Y(n3993) );
XOR2X1TS U4542 ( .A(n3993), .B(n3992), .Y(n3994) );
INVX2TS U4543 ( .A(n3995), .Y(n3996) );
NAND2X1TS U4544 ( .A(n4011), .B(n3996), .Y(n3997) );
XOR2X1TS U4545 ( .A(n3997), .B(n4413), .Y(n3998) );
NOR2X1TS U4546 ( .A(n3999), .B(n4415), .Y(n4000) );
NAND2X1TS U4547 ( .A(n4011), .B(n4000), .Y(n4003) );
XOR2X1TS U4548 ( .A(n4003), .B(n4002), .Y(n4004) );
NAND2X1TS U4549 ( .A(n4011), .B(n4005), .Y(n4008) );
INVX2TS U4550 ( .A(n4006), .Y(n4007) );
XOR2X1TS U4551 ( .A(n4008), .B(n4007), .Y(n4009) );
NAND2X1TS U4552 ( .A(n4011), .B(n4010), .Y(n4013) );
XOR2X1TS U4553 ( .A(n4013), .B(n4012), .Y(n4015) );
CMPR42X2TS U4554 ( .A(n4163), .B(n4164), .C(n4165), .D(n4169), .ICI(n4172),
.S(n4173), .ICO(n4174), .CO(n4175) );
CMPR42X2TS U4555 ( .A(n4176), .B(n4171), .C(n4174), .D(n4184), .ICI(n4182),
.S(n4186), .ICO(n4187), .CO(n4188) );
CMPR42X1TS U4556 ( .A(mult_x_56_n57), .B(mult_x_56_n47), .C(mult_x_56_n52),
.D(mult_x_56_n19), .ICI(mult_x_56_n16), .S(mult_x_56_n15), .ICO(
mult_x_56_n13), .CO(mult_x_56_n14) );
initial $sdf_annotate("FPU_Multiplication_Function_ASIC_fpu_syn_constraints_clk1.tcl_RKOA_2STAGE_syn.sdf");
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module up_pmod (
pmod_clk,
pmod_rst,
pmod_signal_freq,
// bus interface
up_rstn,
up_clk,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_rack);
// parameters
localparam PCORE_VERSION = 32'h00010001;
parameter ID = 0;
input pmod_clk;
output pmod_rst;
input [31:0] pmod_signal_freq;
// bus interface
input up_rstn;
input up_clk;
input up_wreq;
input [13:0] up_waddr;
input [31:0] up_wdata;
output up_wack;
input up_rreq;
input [13:0] up_raddr;
output [31:0] up_rdata;
output up_rack;
// internal registers
reg up_wack = 'd0;
reg [31:0] up_scratch = 'd0;
reg up_resetn = 'd0;
reg up_rack = 'd0;
reg [31:0] up_rdata = 'd0;
// internal signals
wire [31:0] up_pmod_signal_freq_s;
wire up_wreq_s;
wire up_rreq_s;
// decode block select
assign up_wreq_s = (up_waddr[13:8] == 6'h00) ? up_wreq : 1'b0;
assign up_rreq_s = (up_raddr[13:8] == 6'h00) ? up_rreq : 1'b0;
assign up_preset_s = ~up_resetn;
// processor write interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_wack <= 'd0;
up_scratch <= 'd0;
up_resetn <= 'd0;
end else begin
up_wack <= up_wreq_s;
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h02)) begin
up_scratch <= up_wdata;
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h10)) begin
up_resetn <= up_wdata[0];
end
end
end
// processor read interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_rack <= 'd0;
up_rdata <= 'd0;
end else begin
up_rack <= up_rreq_s;
if (up_rreq_s == 1'b1) begin
case (up_raddr[7:0])
8'h00: up_rdata <= PCORE_VERSION;
8'h01: up_rdata <= ID;
8'h02: up_rdata <= up_scratch;
8'h03: up_rdata <= up_pmod_signal_freq_s;
8'h10: up_rdata <= up_resetn;
default: up_rdata <= 0;
endcase
end else begin
up_rdata <= 32'd0;
end
end
end
// resets
ad_rst i_adc_rst_reg (.preset(up_preset_s), .clk(pmod_clk), .rst(pmod_rst));
// adc control & status
up_xfer_status #(.DATA_WIDTH(32)) i_pmod_xfer_status (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_data_status (up_pmod_signal_freq_s),
.d_rst (pmod_rst),
.d_clk (pmod_clk),
.d_data_status (pmod_signal_freq));
endmodule
// ***************************************************************************
// ***************************************************************************
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A222O_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__A222O_PP_BLACKBOX_V
/**
* a222o: 2-input AND into all inputs of 3-input OR.
*
* X = ((A1 & A2) | (B1 & B2) | (C1 & C2))
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__a222o (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
C2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input C2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__A222O_PP_BLACKBOX_V
|
//
// Conformal-LEC Version 15.20-d227 ( 10-Mar-2016) ( 64 bit executable)
//
module top ( n0 , n1 , n2 , n3 , n4 , n5 , n6 , n7 , n8 , n9 , n10 , n11 , n12 , n13 , n14 , n15 , n16 , n17 , n18 , n19 , n20 , n21 , n22 , n23 , n24 , n25 , n26 , n27 , n28 , n29 , n30 , n31 , n32 , n33 , n34 , n35 , n36 , n37 , n38 , n39 , n40 , n41 , n42 , n43 , n44 , n45 , n46 , n47 , n48 , n49 , n50 , n51 , n52 , n53 , n54 , n55 , n56 , n57 , n58 );
input n0 , n1 , n2 , n3 , n4 , n5 , n6 , n7 , n8 , n9 , n10 , n11 , n12 , n13 , n14 , n15 , n16 , n17 , n18 , n19 , n20 , n21 , n22 , n23 , n24 , n25 , n26 , n27 , n28 , n29 , n30 , n31 , n32 , n33 , n34 , n35 , n36 , n37 , n38 , n39 , n40 , n41 , n42 ;
output n43 , n44 , n45 , n46 , n47 , n48 , n49 , n50 , n51 , n52 , n53 , n54 , n55 , n56 , n57 , n58 ;
wire n118 , n119 , n120 , n121 , n122 , n123 , n124 , n125 , n126 ,
n127 , n128 , n129 , n130 , n131 , n132 , n133 , n134 , n135 , n136 ,
n137 , n138 , n139 , n140 , n141 , n142 , n143 , n144 , n145 , n146 ,
n147 , n148 , n149 , n150 , n151 , n152 , n153 , n154 , n155 , n156 ,
n157 , n158 , n159 , n160 , n161 , n162 , n163 , n164 , n165 , n166 ,
n167 , n168 , n169 , n170 , n171 , n172 , n173 , n174 , n175 , n176 ,
n177 , n178 , n179 , n180 , n181 , n182 , n183 , n184 , n185 , n186 ,
n187 , n188 , n189 , n190 , n191 , n192 , n193 , n194 , n195 , n196 ,
n197 , n198 , n199 , n200 , n201 , n202 , n203 , n204 , n205 , n206 ,
n207 , n208 , n209 , n210 , n211 , n212 , n213 , n214 , n215 , n216 ,
n217 , n218 , n219 , n220 , n221 , n222 , n223 , n224 , n225 , n226 ,
n227 , n228 , n229 , n230 , n231 , n232 , n233 , n234 , n235 , n236 ,
n237 , n238 , n239 , n240 , n241 , n242 , n243 , n244 , n245 , n246 ,
n247 , n248 , n249 , n250 , n251 , n252 , n253 , n254 , n255 , n256 ,
n257 , n258 , n259 , n260 , n261 , n262 , n263 , n264 , n265 , n266 ,
n267 , n268 , n269 , n270 , n271 , n272 , n273 , n274 , n275 , n276 ,
n277 , n278 , n279 , n280 , n281 , n282 , n283 , n284 , n285 , n286 ,
n287 , n288 , n289 , n290 , n291 , n292 , n293 , n294 , n295 , n296 ,
n297 , n298 , n299 , n300 , n301 , n302 , n303 , n304 , n305 , n306 ,
n307 , n308 , n309 , n310 , n311 , n312 , n313 , n314 , n315 , n316 ,
n317 , n318 , n319 , n320 , n321 , n322 , n323 , n324 , n325 , n326 ,
n327 , n328 , n329 , n330 , n331 , n332 , n333 , n334 , n335 , n336 ,
n337 , n338 , n339 , n340 , n341 , n342 , n343 , n344 , n345 , n346 ,
n347 , n348 , n349 , n350 , n351 , n352 , n353 , n354 , n355 , n356 ,
n357 , n358 , n359 , n360 , n361 , n362 , n363 , n364 , n365 , n366 ,
n367 , n368 , n369 , n370 , n371 , n372 , n373 , n374 , n375 , n376 ,
n377 , n378 , n379 , n380 , n381 , n382 , n383 , n384 , n385 , n386 ,
n387 , n388 , n389 , n390 , n391 , n392 , n393 , n394 , n395 , n396 ,
n397 , n398 , n399 , n400 , n401 , n402 , n403 , n404 , n405 , n406 ,
n407 , n408 , n409 , n410 , n411 , n412 , n413 , n414 , n415 , n416 ,
n417 , n418 , n419 , n420 , n421 , n422 , n423 , n424 , n425 , n426 ,
n427 , n428 , n429 , n430 , n431 , n432 , n433 , n434 , n435 , n436 ,
n437 , n438 , n439 , n440 , n441 , n442 , n443 , n444 , n445 , n446 ,
n447 , n448 , n449 , n450 , n451 , n452 , n453 , n454 , n455 , n456 ,
n457 , n458 ;
buf ( n47 , n402 );
buf ( n51 , n405 );
buf ( n55 , n408 );
buf ( n49 , n412 );
buf ( n50 , n416 );
buf ( n52 , n420 );
buf ( n46 , n424 );
buf ( n53 , n428 );
buf ( n48 , n432 );
buf ( n57 , n436 );
buf ( n45 , n440 );
buf ( n58 , n444 );
buf ( n56 , n448 );
buf ( n44 , n452 );
buf ( n54 , n455 );
buf ( n43 , n458 );
buf ( n120 , n32 );
buf ( n121 , n27 );
buf ( n122 , n34 );
buf ( n123 , n9 );
buf ( n124 , n37 );
buf ( n125 , n13 );
buf ( n126 , n42 );
buf ( n127 , n12 );
buf ( n128 , n41 );
buf ( n129 , n33 );
buf ( n130 , n15 );
buf ( n131 , n38 );
buf ( n132 , n28 );
buf ( n133 , n1 );
buf ( n134 , n24 );
buf ( n135 , n2 );
buf ( n136 , n23 );
buf ( n137 , n4 );
buf ( n138 , n22 );
buf ( n139 , n11 );
buf ( n140 , n10 );
buf ( n141 , n29 );
buf ( n142 , n3 );
buf ( n143 , n18 );
buf ( n144 , n14 );
buf ( n145 , n36 );
buf ( n146 , n17 );
buf ( n147 , n30 );
buf ( n148 , n35 );
buf ( n149 , n0 );
buf ( n150 , n7 );
buf ( n151 , n31 );
buf ( n152 , n20 );
buf ( n153 , n8 );
buf ( n154 , n21 );
buf ( n155 , n39 );
buf ( n156 , n5 );
buf ( n157 , n19 );
buf ( n158 , n16 );
buf ( n159 , n6 );
buf ( n160 , n25 );
buf ( n161 , n40 );
buf ( n162 , n26 );
buf ( n163 , n120 );
buf ( n164 , n136 );
not ( n165 , n164 );
xor ( n166 , n163 , n165 );
buf ( n167 , n121 );
buf ( n168 , n137 );
not ( n169 , n168 );
and ( n170 , n167 , n169 );
buf ( n171 , n122 );
buf ( n172 , n138 );
not ( n173 , n172 );
and ( n174 , n171 , n173 );
buf ( n175 , n123 );
buf ( n176 , n139 );
not ( n177 , n176 );
and ( n178 , n175 , n177 );
buf ( n179 , n124 );
buf ( n180 , n140 );
not ( n181 , n180 );
and ( n182 , n179 , n181 );
buf ( n183 , n125 );
buf ( n184 , n141 );
not ( n185 , n184 );
and ( n186 , n183 , n185 );
buf ( n187 , n126 );
buf ( n188 , n142 );
not ( n189 , n188 );
and ( n190 , n187 , n189 );
buf ( n191 , n127 );
buf ( n192 , n143 );
not ( n193 , n192 );
and ( n194 , n191 , n193 );
buf ( n195 , n128 );
buf ( n196 , n144 );
not ( n197 , n196 );
and ( n198 , n195 , n197 );
buf ( n199 , n129 );
buf ( n200 , n145 );
not ( n201 , n200 );
and ( n202 , n199 , n201 );
buf ( n203 , n130 );
buf ( n204 , n146 );
not ( n205 , n204 );
and ( n206 , n203 , n205 );
buf ( n207 , n131 );
buf ( n208 , n147 );
not ( n209 , n208 );
and ( n210 , n207 , n209 );
buf ( n211 , n132 );
buf ( n212 , n148 );
not ( n213 , n212 );
and ( n214 , n211 , n213 );
buf ( n215 , n133 );
buf ( n216 , n149 );
not ( n217 , n216 );
and ( n218 , n215 , n217 );
buf ( n219 , n134 );
buf ( n220 , n150 );
not ( n221 , n220 );
and ( n222 , n219 , n221 );
buf ( n223 , n135 );
buf ( n224 , n151 );
not ( n225 , n224 );
or ( n226 , n223 , n225 );
and ( n227 , n221 , n226 );
and ( n228 , n219 , n226 );
or ( n229 , n222 , n227 , n228 );
and ( n230 , n217 , n229 );
and ( n231 , n215 , n229 );
or ( n232 , n218 , n230 , n231 );
and ( n233 , n213 , n232 );
and ( n234 , n211 , n232 );
or ( n235 , n214 , n233 , n234 );
and ( n236 , n209 , n235 );
and ( n237 , n207 , n235 );
or ( n238 , n210 , n236 , n237 );
and ( n239 , n205 , n238 );
and ( n240 , n203 , n238 );
or ( n241 , n206 , n239 , n240 );
and ( n242 , n201 , n241 );
and ( n243 , n199 , n241 );
or ( n244 , n202 , n242 , n243 );
and ( n245 , n197 , n244 );
and ( n246 , n195 , n244 );
or ( n247 , n198 , n245 , n246 );
and ( n248 , n193 , n247 );
and ( n249 , n191 , n247 );
or ( n250 , n194 , n248 , n249 );
and ( n251 , n189 , n250 );
and ( n252 , n187 , n250 );
or ( n253 , n190 , n251 , n252 );
and ( n254 , n185 , n253 );
and ( n255 , n183 , n253 );
or ( n256 , n186 , n254 , n255 );
and ( n257 , n181 , n256 );
and ( n258 , n179 , n256 );
or ( n259 , n182 , n257 , n258 );
and ( n260 , n177 , n259 );
and ( n261 , n175 , n259 );
or ( n262 , n178 , n260 , n261 );
and ( n263 , n173 , n262 );
and ( n264 , n171 , n262 );
or ( n265 , n174 , n263 , n264 );
and ( n266 , n169 , n265 );
and ( n267 , n167 , n265 );
or ( n268 , n170 , n266 , n267 );
xor ( n269 , n166 , n268 );
buf ( n270 , n269 );
buf ( n271 , n270 );
xor ( n272 , n167 , n169 );
xor ( n273 , n272 , n265 );
buf ( n274 , n273 );
buf ( n275 , n274 );
xor ( n276 , n171 , n173 );
xor ( n277 , n276 , n262 );
buf ( n278 , n277 );
buf ( n279 , n278 );
xor ( n280 , n175 , n177 );
xor ( n281 , n280 , n259 );
buf ( n282 , n281 );
buf ( n283 , n282 );
not ( n284 , n152 );
buf ( n285 , n284 );
and ( n286 , n283 , n285 );
xor ( n287 , n179 , n181 );
xor ( n288 , n287 , n256 );
buf ( n289 , n288 );
buf ( n290 , n289 );
not ( n291 , n153 );
buf ( n292 , n291 );
and ( n293 , n290 , n292 );
xor ( n294 , n183 , n185 );
xor ( n295 , n294 , n253 );
buf ( n296 , n295 );
buf ( n297 , n296 );
not ( n298 , n154 );
buf ( n299 , n298 );
and ( n300 , n297 , n299 );
xor ( n301 , n187 , n189 );
xor ( n302 , n301 , n250 );
buf ( n303 , n302 );
buf ( n304 , n303 );
not ( n305 , n155 );
buf ( n306 , n305 );
and ( n307 , n304 , n306 );
xor ( n308 , n191 , n193 );
xor ( n309 , n308 , n247 );
buf ( n310 , n309 );
buf ( n311 , n310 );
not ( n312 , n156 );
buf ( n313 , n312 );
and ( n314 , n311 , n313 );
xor ( n315 , n195 , n197 );
xor ( n316 , n315 , n244 );
buf ( n317 , n316 );
buf ( n318 , n317 );
not ( n319 , n157 );
buf ( n320 , n319 );
and ( n321 , n318 , n320 );
xor ( n322 , n199 , n201 );
xor ( n323 , n322 , n241 );
buf ( n324 , n323 );
buf ( n325 , n324 );
not ( n326 , n158 );
buf ( n327 , n326 );
and ( n328 , n325 , n327 );
xor ( n329 , n203 , n205 );
xor ( n330 , n329 , n238 );
buf ( n331 , n330 );
buf ( n332 , n331 );
not ( n333 , n159 );
buf ( n334 , n333 );
and ( n335 , n332 , n334 );
xor ( n336 , n207 , n209 );
xor ( n337 , n336 , n235 );
buf ( n338 , n337 );
buf ( n339 , n338 );
not ( n340 , n160 );
buf ( n341 , n340 );
and ( n342 , n339 , n341 );
xor ( n343 , n211 , n213 );
xor ( n344 , n343 , n232 );
buf ( n345 , n344 );
buf ( n346 , n345 );
not ( n347 , n161 );
buf ( n348 , n347 );
and ( n349 , n346 , n348 );
xor ( n350 , n215 , n217 );
xor ( n351 , n350 , n229 );
buf ( n352 , n351 );
buf ( n353 , n352 );
not ( n354 , n162 );
buf ( n355 , n354 );
and ( n356 , n353 , n355 );
xor ( n357 , n219 , n221 );
xor ( n358 , n357 , n226 );
buf ( n359 , n358 );
buf ( n360 , n359 );
xor ( n361 , n223 , n224 );
buf ( n362 , n361 );
buf ( n363 , n362 );
or ( n364 , n360 , n363 );
and ( n365 , n355 , n364 );
and ( n366 , n353 , n364 );
or ( n367 , n356 , n365 , n366 );
and ( n368 , n348 , n367 );
and ( n369 , n346 , n367 );
or ( n370 , n349 , n368 , n369 );
and ( n371 , n341 , n370 );
and ( n372 , n339 , n370 );
or ( n373 , n342 , n371 , n372 );
and ( n374 , n334 , n373 );
and ( n375 , n332 , n373 );
or ( n376 , n335 , n374 , n375 );
and ( n377 , n327 , n376 );
and ( n378 , n325 , n376 );
or ( n379 , n328 , n377 , n378 );
and ( n380 , n320 , n379 );
and ( n381 , n318 , n379 );
or ( n382 , n321 , n380 , n381 );
and ( n383 , n313 , n382 );
and ( n384 , n311 , n382 );
or ( n385 , n314 , n383 , n384 );
and ( n386 , n306 , n385 );
and ( n387 , n304 , n385 );
or ( n388 , n307 , n386 , n387 );
and ( n389 , n299 , n388 );
and ( n390 , n297 , n388 );
or ( n391 , n300 , n389 , n390 );
and ( n392 , n292 , n391 );
and ( n393 , n290 , n391 );
or ( n394 , n293 , n392 , n393 );
and ( n395 , n285 , n394 );
and ( n396 , n283 , n394 );
or ( n397 , n286 , n395 , n396 );
and ( n398 , n279 , n397 );
and ( n399 , n275 , n398 );
xor ( n400 , n271 , n399 );
buf ( n401 , n400 );
buf ( n402 , n401 );
xor ( n403 , n275 , n398 );
buf ( n404 , n403 );
buf ( n405 , n404 );
xor ( n406 , n279 , n397 );
buf ( n407 , n406 );
buf ( n408 , n407 );
xor ( n409 , n283 , n285 );
xor ( n410 , n409 , n394 );
buf ( n411 , n410 );
buf ( n412 , n411 );
xor ( n413 , n290 , n292 );
xor ( n414 , n413 , n391 );
buf ( n415 , n414 );
buf ( n416 , n415 );
xor ( n417 , n297 , n299 );
xor ( n418 , n417 , n388 );
buf ( n419 , n418 );
buf ( n420 , n419 );
xor ( n421 , n304 , n306 );
xor ( n422 , n421 , n385 );
buf ( n423 , n422 );
buf ( n424 , n423 );
xor ( n425 , n311 , n313 );
xor ( n426 , n425 , n382 );
buf ( n427 , n426 );
buf ( n428 , n427 );
xor ( n429 , n318 , n320 );
xor ( n430 , n429 , n379 );
buf ( n431 , n430 );
buf ( n432 , n431 );
xor ( n433 , n325 , n327 );
xor ( n434 , n433 , n376 );
buf ( n435 , n434 );
buf ( n436 , n435 );
xor ( n437 , n332 , n334 );
xor ( n438 , n437 , n373 );
buf ( n439 , n438 );
buf ( n440 , n439 );
xor ( n441 , n339 , n341 );
xor ( n442 , n441 , n370 );
buf ( n443 , n442 );
buf ( n444 , n443 );
xor ( n445 , n346 , n348 );
xor ( n446 , n445 , n367 );
buf ( n447 , n446 );
buf ( n448 , n447 );
xor ( n449 , n353 , n355 );
xor ( n450 , n449 , n364 );
buf ( n451 , n450 );
buf ( n452 , n451 );
xnor ( n453 , n360 , n363 );
buf ( n454 , n453 );
buf ( n455 , n454 );
not ( n456 , n363 );
buf ( n457 , n456 );
buf ( n458 , n457 );
endmodule
|
/***********************************************
Module Name: CORDIC
Feature: CORDIC algorithm
An example for the GEM Projects
Coder: Garfield
Organization: xxxx Group, Department of Architecture
------------------------------------------------------
Input ports: clk: System clock
Reset_n: System reset
opernd: input number to be calculated
Output Ports: results: results of operation
------------------------------------------------------
History:
06-21-2016: First Version by Garfield
06-21-2016: Verified by CORDIC_Test
***********************************************/
`define ORDER 12
// CORDIC order by simulation
`define WIDTH 15
//CORDIC ports bit width by simulatation
`define K 14'h26DD
module CORDIC
#(parameter MODE = 1)
//CORDIC Mode
(
CLK,
RESET_n,
operand,
results
);
localparam PORT_WIDTH = (MODE == 3) ? (7 + `WIDTH) : ( (MODE == 2) ? (2 + `WIDTH) :(`WIDTH));
localparam IN_WIDTH = 2 * PORT_WIDTH;
localparam OUT_WIDTH = 2 * PORT_WIDTH;
localparam ONE = 15'd16384;
input CLK;
input RESET_n;
input signed[(IN_WIDTH - 1) : 0] operand;
output signed[(OUT_WIDTH - 1) : 0] results;
wire[(PORT_WIDTH-1):0] x[(`ORDER+1):0];
wire[(PORT_WIDTH-1):0] y[(`ORDER+1):0];
wire[(PORT_WIDTH-1):0] z[(`ORDER+1):0];
//middle signals
generate
begin
case(MODE)
1:
begin
assign x[0] = `K;
assign y[0] = 14'h0;
assign z[0] = operand[PORT_WIDTH -1 : 0];
end
2:
begin
assign x[0] = ONE;
assign y[0] = operand[PORT_WIDTH -1 : 0];
assign z[0] = 14'h0;
end
3:
begin
assign x[0] = operand[PORT_WIDTH -1 : 0];
assign y[0] = operand[2*PORT_WIDTH -1 : PORT_WIDTH];
assign z[0] = 14'h0;
end
default:
begin
assign x[0] = `K;
assign y[0] = 14'h0;
assign z[0] = operand[PORT_WIDTH -1 : 0];
end
endcase
end
endgenerate
generate
begin
case(MODE)
1:
begin
assign results = {x[13], y[13]};
end
2:
begin
assign results = {{(PORT_WIDTH){1'b0}}, z[13]};
end
3:
begin
assign results = {{(PORT_WIDTH){1'b0}}, x[13]};
end
default:
begin
assign results = {x[13], y[13]};
end
endcase
end
endgenerate
//CORDIC pipeline
//Connection to the modules
CORDIC_elemet #(.ADDRESS_WIDTH(PORT_WIDTH-1), .VALUE_WIDTH(PORT_WIDTH-1), .e_k(14'h3243), .ORDER(0), .MODE(MODE) )
CE0 ( .CLK(CLK), .RESET_n(RESET_n),
.x_k(x[0]), .y_k(y[0]), .z_k(z[0]),
.x_k1(x[1]), .y_k1(y[1]), .z_k1(z[1]) );
CORDIC_elemet #(.ADDRESS_WIDTH(PORT_WIDTH-1), .VALUE_WIDTH(PORT_WIDTH-1), .e_k(14'h1DAC), .ORDER(1), .MODE(MODE) )
CE1 ( .CLK(CLK), .RESET_n(RESET_n),
.x_k(x[1]), .y_k(y[1]), .z_k(z[1]),
.x_k1(x[2]), .y_k1(y[2]), .z_k1(z[2]) );
CORDIC_elemet #(.ADDRESS_WIDTH(PORT_WIDTH-1), .VALUE_WIDTH(PORT_WIDTH-1), .e_k(14'h0FAD), .ORDER(2), .MODE(MODE) )
CE2 ( .CLK(CLK), .RESET_n(RESET_n),
.x_k(x[2]), .y_k(y[2]), .z_k(z[2]),
.x_k1(x[3]), .y_k1(y[3]), .z_k1(z[3]) );
CORDIC_elemet #(.ADDRESS_WIDTH(PORT_WIDTH-1), .VALUE_WIDTH(PORT_WIDTH-1), .e_k(14'h07F5), .ORDER(3) , .MODE(MODE) )
CE3 ( .CLK(CLK), .RESET_n(RESET_n),
.x_k(x[3]), .y_k(y[3]), .z_k(z[3]),
.x_k1(x[4]), .y_k1(y[4]), .z_k1(z[4]) );
CORDIC_elemet #(.ADDRESS_WIDTH(PORT_WIDTH-1), .VALUE_WIDTH(PORT_WIDTH-1), .e_k(14'h03FE), .ORDER(4) , .MODE(MODE) )
CE4 ( .CLK(CLK), .RESET_n(RESET_n),
.x_k(x[4]), .y_k(y[4]), .z_k(z[4]),
.x_k1(x[5]), .y_k1(y[5]), .z_k1(z[5]) );
CORDIC_elemet #(.ADDRESS_WIDTH(PORT_WIDTH-1), .VALUE_WIDTH(PORT_WIDTH-1), .e_k(14'h01FF), .ORDER(5) , .MODE(MODE) )
CE5 ( .CLK(CLK), .RESET_n(RESET_n),
.x_k(x[5]), .y_k(y[5]), .z_k(z[5]),
.x_k1(x[6]), .y_k1(y[6]), .z_k1(z[6]) );
CORDIC_elemet #(.ADDRESS_WIDTH(PORT_WIDTH-1), .VALUE_WIDTH(PORT_WIDTH-1), .e_k(14'h00FF), .ORDER(6) , .MODE(MODE) )
CE6 ( .CLK(CLK), .RESET_n(RESET_n),
.x_k(x[6]), .y_k(y[6]), .z_k(z[6]),
.x_k1(x[7]), .y_k1(y[7]), .z_k1(z[7]) );
CORDIC_elemet #(.ADDRESS_WIDTH(PORT_WIDTH-1), .VALUE_WIDTH(PORT_WIDTH-1), .e_k(14'h007F), .ORDER(7) , .MODE(MODE) )
CE7 ( .CLK(CLK), .RESET_n(RESET_n),
.x_k(x[7]), .y_k(y[7]), .z_k(z[7]),
.x_k1(x[8]), .y_k1(y[8]), .z_k1(z[8]) );
CORDIC_elemet #(.ADDRESS_WIDTH(PORT_WIDTH-1), .VALUE_WIDTH(PORT_WIDTH-1), .e_k(14'h003F), .ORDER(8) , .MODE(MODE) )
CE8 ( .CLK(CLK), .RESET_n(RESET_n),
.x_k(x[8]), .y_k(y[8]), .z_k(z[8]),
.x_k1(x[9]), .y_k1(y[9]), .z_k1(z[9]) );
CORDIC_elemet #(.ADDRESS_WIDTH(PORT_WIDTH-1), .VALUE_WIDTH(PORT_WIDTH-1), .e_k(14'h001F), .ORDER(9) , .MODE(MODE) )
CE9 ( .CLK(CLK), .RESET_n(RESET_n),
.x_k(x[9]), .y_k(y[9]), .z_k(z[9]),
.x_k1(x[10]), .y_k1(y[10]), .z_k1(z[10]) );
CORDIC_elemet #(.ADDRESS_WIDTH(PORT_WIDTH-1), .VALUE_WIDTH(PORT_WIDTH-1), .e_k(14'h000F), .ORDER(10) , .MODE(MODE) )
CE10 ( .CLK(CLK), .RESET_n(RESET_n),
.x_k(x[10]), .y_k(y[10]), .z_k(z[10]),
.x_k1(x[11]), .y_k1(y[11]), .z_k1(z[11]) );
CORDIC_elemet #(.ADDRESS_WIDTH(PORT_WIDTH-1), .VALUE_WIDTH(PORT_WIDTH-1), .e_k(14'h0007), .ORDER(11) , .MODE(MODE) )
CE11 ( .CLK(CLK), .RESET_n(RESET_n),
.x_k(x[11]), .y_k(y[11]), .z_k(z[11]),
.x_k1(x[12]), .y_k1(y[12]), .z_k1(z[12]) );
CORDIC_elemet #(.ADDRESS_WIDTH(PORT_WIDTH-1), .VALUE_WIDTH(PORT_WIDTH-1), .e_k(14'h0003), .ORDER(12) , .MODE(MODE) )
CE12 ( .CLK(CLK), .RESET_n(RESET_n),
.x_k(x[12]), .y_k(y[12]), .z_k(z[12]),
.x_k1(x[13]), .y_k1(y[13]), .z_k1(z[13]) );
endmodule
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2016.2
// Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
(* CORE_GENERATION_INFO="sp,hls_ip_2016_2,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=1,HLS_INPUT_PART=xc7vx690tffg1927-2,HLS_INPUT_CLOCK=25.000000,HLS_INPUT_ARCH=pipeline,HLS_SYN_CLOCK=23.000000,HLS_SYN_LAT=10,HLS_SYN_TPT=1,HLS_SYN_MEM=0,HLS_SYN_DSP=39,HLS_SYN_FF=113669,HLS_SYN_LUT=576347}" *)
module sp (
ap_clk,
ap_rst,
q_0_0_0_V,
q_0_0_1_V,
q_0_1_0_V,
q_0_1_1_V,
q_0_2_0_V,
q_0_2_1_V,
q_0_3_0_V,
q_0_3_1_V,
q_0_4_0_V,
q_0_4_1_V,
q_0_5_0_V,
q_0_5_1_V,
q_0_6_0_V,
q_0_6_1_V,
q_0_7_0_V,
q_0_7_1_V,
q_0_8_0_V,
q_0_8_1_V,
q_1_0_0_V,
q_1_0_1_V,
q_1_1_0_V,
q_1_1_1_V,
q_1_2_0_V,
q_1_2_1_V,
q_1_3_0_V,
q_1_3_1_V,
q_1_4_0_V,
q_1_4_1_V,
q_1_5_0_V,
q_1_5_1_V,
q_1_6_0_V,
q_1_6_1_V,
q_1_7_0_V,
q_1_7_1_V,
q_1_8_0_V,
q_1_8_1_V,
q_2_0_0_V,
q_2_0_1_V,
q_2_1_0_V,
q_2_1_1_V,
q_2_2_0_V,
q_2_2_1_V,
q_2_3_0_V,
q_2_3_1_V,
q_2_4_0_V,
q_2_4_1_V,
q_2_5_0_V,
q_2_5_1_V,
q_2_6_0_V,
q_2_6_1_V,
q_2_7_0_V,
q_2_7_1_V,
q_2_8_0_V,
q_2_8_1_V,
q_3_0_0_V,
q_3_0_1_V,
q_3_1_0_V,
q_3_1_1_V,
q_3_2_0_V,
q_3_2_1_V,
q_3_3_0_V,
q_3_3_1_V,
q_3_4_0_V,
q_3_4_1_V,
q_3_5_0_V,
q_3_5_1_V,
q_3_6_0_V,
q_3_6_1_V,
q_3_7_0_V,
q_3_7_1_V,
q_3_8_0_V,
q_3_8_1_V,
q_4_0_0_V,
q_4_0_1_V,
q_4_1_0_V,
q_4_1_1_V,
q_4_2_0_V,
q_4_2_1_V,
q_4_3_0_V,
q_4_3_1_V,
q_4_4_0_V,
q_4_4_1_V,
q_4_5_0_V,
q_4_5_1_V,
q_4_6_0_V,
q_4_6_1_V,
q_4_7_0_V,
q_4_7_1_V,
q_4_8_0_V,
q_4_8_1_V,
wg_0_0_0_V,
wg_0_0_1_V,
wg_0_1_0_V,
wg_0_1_1_V,
wg_0_2_0_V,
wg_0_2_1_V,
wg_0_3_0_V,
wg_0_3_1_V,
wg_0_4_0_V,
wg_0_4_1_V,
wg_0_5_0_V,
wg_0_5_1_V,
wg_0_6_0_V,
wg_0_6_1_V,
wg_0_7_0_V,
wg_0_7_1_V,
wg_0_8_0_V,
wg_0_8_1_V,
wg_1_0_0_V,
wg_1_0_1_V,
wg_1_1_0_V,
wg_1_1_1_V,
wg_1_2_0_V,
wg_1_2_1_V,
wg_1_3_0_V,
wg_1_3_1_V,
wg_1_4_0_V,
wg_1_4_1_V,
wg_1_5_0_V,
wg_1_5_1_V,
wg_1_6_0_V,
wg_1_6_1_V,
wg_1_7_0_V,
wg_1_7_1_V,
wg_1_8_0_V,
wg_1_8_1_V,
wg_2_0_0_V,
wg_2_0_1_V,
wg_2_1_0_V,
wg_2_1_1_V,
wg_2_2_0_V,
wg_2_2_1_V,
wg_2_3_0_V,
wg_2_3_1_V,
wg_2_4_0_V,
wg_2_4_1_V,
wg_2_5_0_V,
wg_2_5_1_V,
wg_2_6_0_V,
wg_2_6_1_V,
wg_2_7_0_V,
wg_2_7_1_V,
wg_2_8_0_V,
wg_2_8_1_V,
wg_3_0_0_V,
wg_3_0_1_V,
wg_3_1_0_V,
wg_3_1_1_V,
wg_3_2_0_V,
wg_3_2_1_V,
wg_3_3_0_V,
wg_3_3_1_V,
wg_3_4_0_V,
wg_3_4_1_V,
wg_3_5_0_V,
wg_3_5_1_V,
wg_3_6_0_V,
wg_3_6_1_V,
wg_3_7_0_V,
wg_3_7_1_V,
wg_3_8_0_V,
wg_3_8_1_V,
wg_4_0_0_V,
wg_4_0_1_V,
wg_4_1_0_V,
wg_4_1_1_V,
wg_4_2_0_V,
wg_4_2_1_V,
wg_4_3_0_V,
wg_4_3_1_V,
wg_4_4_0_V,
wg_4_4_1_V,
wg_4_5_0_V,
wg_4_5_1_V,
wg_4_6_0_V,
wg_4_6_1_V,
wg_4_7_0_V,
wg_4_7_1_V,
wg_4_8_0_V,
wg_4_8_1_V,
hstr_0_0_0_V,
hstr_0_0_1_V,
hstr_0_1_0_V,
hstr_0_1_1_V,
hstr_0_2_0_V,
hstr_0_2_1_V,
hstr_0_3_0_V,
hstr_0_3_1_V,
hstr_0_4_0_V,
hstr_0_4_1_V,
hstr_0_5_0_V,
hstr_0_5_1_V,
hstr_0_6_0_V,
hstr_0_6_1_V,
hstr_0_7_0_V,
hstr_0_7_1_V,
hstr_0_8_0_V,
hstr_0_8_1_V,
hstr_1_0_0_V,
hstr_1_0_1_V,
hstr_1_1_0_V,
hstr_1_1_1_V,
hstr_1_2_0_V,
hstr_1_2_1_V,
hstr_1_3_0_V,
hstr_1_3_1_V,
hstr_1_4_0_V,
hstr_1_4_1_V,
hstr_1_5_0_V,
hstr_1_5_1_V,
hstr_1_6_0_V,
hstr_1_6_1_V,
hstr_1_7_0_V,
hstr_1_7_1_V,
hstr_1_8_0_V,
hstr_1_8_1_V,
hstr_2_0_0_V,
hstr_2_0_1_V,
hstr_2_1_0_V,
hstr_2_1_1_V,
hstr_2_2_0_V,
hstr_2_2_1_V,
hstr_2_3_0_V,
hstr_2_3_1_V,
hstr_2_4_0_V,
hstr_2_4_1_V,
hstr_2_5_0_V,
hstr_2_5_1_V,
hstr_2_6_0_V,
hstr_2_6_1_V,
hstr_2_7_0_V,
hstr_2_7_1_V,
hstr_2_8_0_V,
hstr_2_8_1_V,
hstr_3_0_0_V,
hstr_3_0_1_V,
hstr_3_1_0_V,
hstr_3_1_1_V,
hstr_3_2_0_V,
hstr_3_2_1_V,
hstr_3_3_0_V,
hstr_3_3_1_V,
hstr_3_4_0_V,
hstr_3_4_1_V,
hstr_3_5_0_V,
hstr_3_5_1_V,
hstr_3_6_0_V,
hstr_3_6_1_V,
hstr_3_7_0_V,
hstr_3_7_1_V,
hstr_3_8_0_V,
hstr_3_8_1_V,
hstr_4_0_0_V,
hstr_4_0_1_V,
hstr_4_1_0_V,
hstr_4_1_1_V,
hstr_4_2_0_V,
hstr_4_2_1_V,
hstr_4_3_0_V,
hstr_4_3_1_V,
hstr_4_4_0_V,
hstr_4_4_1_V,
hstr_4_5_0_V,
hstr_4_5_1_V,
hstr_4_6_0_V,
hstr_4_6_1_V,
hstr_4_7_0_V,
hstr_4_7_1_V,
hstr_4_8_0_V,
hstr_4_8_1_V,
cpat_0_0_0_V,
cpat_0_0_1_V,
cpat_0_1_0_V,
cpat_0_1_1_V,
cpat_0_2_0_V,
cpat_0_2_1_V,
cpat_0_3_0_V,
cpat_0_3_1_V,
cpat_0_4_0_V,
cpat_0_4_1_V,
cpat_0_5_0_V,
cpat_0_5_1_V,
cpat_0_6_0_V,
cpat_0_6_1_V,
cpat_0_7_0_V,
cpat_0_7_1_V,
cpat_0_8_0_V,
cpat_0_8_1_V,
cpat_1_0_0_V,
cpat_1_0_1_V,
cpat_1_1_0_V,
cpat_1_1_1_V,
cpat_1_2_0_V,
cpat_1_2_1_V,
cpat_1_3_0_V,
cpat_1_3_1_V,
cpat_1_4_0_V,
cpat_1_4_1_V,
cpat_1_5_0_V,
cpat_1_5_1_V,
cpat_1_6_0_V,
cpat_1_6_1_V,
cpat_1_7_0_V,
cpat_1_7_1_V,
cpat_1_8_0_V,
cpat_1_8_1_V,
cpat_2_0_0_V,
cpat_2_0_1_V,
cpat_2_1_0_V,
cpat_2_1_1_V,
cpat_2_2_0_V,
cpat_2_2_1_V,
cpat_2_3_0_V,
cpat_2_3_1_V,
cpat_2_4_0_V,
cpat_2_4_1_V,
cpat_2_5_0_V,
cpat_2_5_1_V,
cpat_2_6_0_V,
cpat_2_6_1_V,
cpat_2_7_0_V,
cpat_2_7_1_V,
cpat_2_8_0_V,
cpat_2_8_1_V,
cpat_3_0_0_V,
cpat_3_0_1_V,
cpat_3_1_0_V,
cpat_3_1_1_V,
cpat_3_2_0_V,
cpat_3_2_1_V,
cpat_3_3_0_V,
cpat_3_3_1_V,
cpat_3_4_0_V,
cpat_3_4_1_V,
cpat_3_5_0_V,
cpat_3_5_1_V,
cpat_3_6_0_V,
cpat_3_6_1_V,
cpat_3_7_0_V,
cpat_3_7_1_V,
cpat_3_8_0_V,
cpat_3_8_1_V,
cpat_4_0_0_V,
cpat_4_0_1_V,
cpat_4_1_0_V,
cpat_4_1_1_V,
cpat_4_2_0_V,
cpat_4_2_1_V,
cpat_4_3_0_V,
cpat_4_3_1_V,
cpat_4_4_0_V,
cpat_4_4_1_V,
cpat_4_5_0_V,
cpat_4_5_1_V,
cpat_4_6_0_V,
cpat_4_6_1_V,
cpat_4_7_0_V,
cpat_4_7_1_V,
cpat_4_8_0_V,
cpat_4_8_1_V,
pcs_cs_0_V,
pcs_cs_1_V,
pcs_cs_2_V,
pcs_cs_3_V,
pcs_cs_4_V,
pps_cs_V_address0,
pps_cs_V_ce0,
pps_cs_V_we0,
pps_cs_V_d0,
pps_cs_V_q0,
pps_cs_V_address1,
pps_cs_V_ce1,
pps_cs_V_we1,
pps_cs_V_d1,
pps_cs_V_q1,
sel_V,
addr_V,
r_in_V,
r_out_V,
we_V,
ph_V_address0,
ph_V_ce0,
ph_V_we0,
ph_V_d0,
ph_V_q0,
ph_V_address1,
ph_V_ce1,
ph_V_we1,
ph_V_d1,
ph_V_q1,
th11_V_address0,
th11_V_ce0,
th11_V_we0,
th11_V_d0,
th11_V_q0,
th11_V_address1,
th11_V_ce1,
th11_V_we1,
th11_V_d1,
th11_V_q1,
th_V_address0,
th_V_ce0,
th_V_we0,
th_V_d0,
th_V_q0,
th_V_address1,
th_V_ce1,
th_V_we1,
th_V_d1,
th_V_q1,
vl_V_address0,
vl_V_ce0,
vl_V_we0,
vl_V_d0,
vl_V_q0,
vl_V_address1,
vl_V_ce1,
vl_V_we1,
vl_V_d1,
vl_V_q1,
phzvl_V_address0,
phzvl_V_ce0,
phzvl_V_we0,
phzvl_V_d0,
phzvl_V_q0,
phzvl_V_address1,
phzvl_V_ce1,
phzvl_V_we1,
phzvl_V_d1,
phzvl_V_q1,
me11a_V_address0,
me11a_V_ce0,
me11a_V_we0,
me11a_V_d0,
me11a_V_q0,
me11a_V_address1,
me11a_V_ce1,
me11a_V_we1,
me11a_V_d1,
me11a_V_q1,
cpatr_V_address0,
cpatr_V_ce0,
cpatr_V_we0,
cpatr_V_d0,
cpatr_V_q0,
cpatr_V_address1,
cpatr_V_ce1,
cpatr_V_we1,
cpatr_V_d1,
cpatr_V_q1,
ph_hit_V_address0,
ph_hit_V_ce0,
ph_hit_V_we0,
ph_hit_V_d0,
ph_hit_V_q0,
ph_hit_V_address1,
ph_hit_V_ce1,
ph_hit_V_we1,
ph_hit_V_d1,
ph_hit_V_q1,
th_hit_V_address0,
th_hit_V_ce0,
th_hit_V_we0,
th_hit_V_d0,
th_hit_V_q0,
th_hit_V_address1,
th_hit_V_ce1,
th_hit_V_we1,
th_hit_V_d1,
th_hit_V_q1,
ph_zone_0_0_V,
ph_zone_0_0_V_ap_vld,
ph_zone_0_1_V,
ph_zone_0_1_V_ap_vld,
ph_zone_0_2_V,
ph_zone_0_2_V_ap_vld,
ph_zone_0_3_V,
ph_zone_0_3_V_ap_vld,
ph_zone_0_4_V,
ph_zone_0_4_V_ap_vld,
ph_zone_1_0_V,
ph_zone_1_0_V_ap_vld,
ph_zone_1_1_V,
ph_zone_1_1_V_ap_vld,
ph_zone_1_2_V,
ph_zone_1_2_V_ap_vld,
ph_zone_1_3_V,
ph_zone_1_3_V_ap_vld,
ph_zone_1_4_V,
ph_zone_1_4_V_ap_vld,
ph_zone_2_0_V,
ph_zone_2_0_V_ap_vld,
ph_zone_2_1_V,
ph_zone_2_1_V_ap_vld,
ph_zone_2_2_V,
ph_zone_2_2_V_ap_vld,
ph_zone_2_3_V,
ph_zone_2_3_V_ap_vld,
ph_zone_2_4_V,
ph_zone_2_4_V_ap_vld,
ph_zone_3_0_V,
ph_zone_3_0_V_ap_vld,
ph_zone_3_1_V,
ph_zone_3_1_V_ap_vld,
ph_zone_3_2_V,
ph_zone_3_2_V_ap_vld,
ph_zone_3_3_V,
ph_zone_3_3_V_ap_vld,
ph_zone_3_4_V,
ph_zone_3_4_V_ap_vld,
ph_ext_0_0_V,
ph_ext_0_0_V_ap_vld,
ph_ext_0_1_V,
ph_ext_0_1_V_ap_vld,
ph_ext_0_2_V,
ph_ext_0_2_V_ap_vld,
ph_ext_0_3_V,
ph_ext_0_3_V_ap_vld,
ph_ext_0_4_V,
ph_ext_0_4_V_ap_vld,
ph_ext_1_0_V,
ph_ext_1_0_V_ap_vld,
ph_ext_1_1_V,
ph_ext_1_1_V_ap_vld,
ph_ext_1_2_V,
ph_ext_1_2_V_ap_vld,
ph_ext_1_3_V,
ph_ext_1_3_V_ap_vld,
ph_ext_1_4_V,
ph_ext_1_4_V_ap_vld,
ph_ext_2_0_V,
ph_ext_2_0_V_ap_vld,
ph_ext_2_1_V,
ph_ext_2_1_V_ap_vld,
ph_ext_2_2_V,
ph_ext_2_2_V_ap_vld,
ph_ext_2_3_V,
ph_ext_2_3_V_ap_vld,
ph_ext_2_4_V,
ph_ext_2_4_V_ap_vld,
ph_ext_3_0_V,
ph_ext_3_0_V_ap_vld,
ph_ext_3_1_V,
ph_ext_3_1_V_ap_vld,
ph_ext_3_2_V,
ph_ext_3_2_V_ap_vld,
ph_ext_3_3_V,
ph_ext_3_3_V_ap_vld,
ph_ext_3_4_V,
ph_ext_3_4_V_ap_vld,
ph_rank_V_address0,
ph_rank_V_ce0,
ph_rank_V_we0,
ph_rank_V_d0,
ph_rank_V_q0,
ph_rank_V_address1,
ph_rank_V_ce1,
ph_rank_V_we1,
ph_rank_V_d1,
ph_rank_V_q1,
ph_num_0_0_V,
ph_num_0_0_V_ap_vld,
ph_num_0_1_V,
ph_num_0_1_V_ap_vld,
ph_num_0_2_V,
ph_num_0_2_V_ap_vld,
ph_num_1_0_V,
ph_num_1_0_V_ap_vld,
ph_num_1_1_V,
ph_num_1_1_V_ap_vld,
ph_num_1_2_V,
ph_num_1_2_V_ap_vld,
ph_num_2_0_V,
ph_num_2_0_V_ap_vld,
ph_num_2_1_V,
ph_num_2_1_V_ap_vld,
ph_num_2_2_V,
ph_num_2_2_V_ap_vld,
ph_num_3_0_V,
ph_num_3_0_V_ap_vld,
ph_num_3_1_V,
ph_num_3_1_V_ap_vld,
ph_num_3_2_V,
ph_num_3_2_V_ap_vld,
ph_q_0_0_V,
ph_q_0_0_V_ap_vld,
ph_q_0_1_V,
ph_q_0_1_V_ap_vld,
ph_q_0_2_V,
ph_q_0_2_V_ap_vld,
ph_q_1_0_V,
ph_q_1_0_V_ap_vld,
ph_q_1_1_V,
ph_q_1_1_V_ap_vld,
ph_q_1_2_V,
ph_q_1_2_V_ap_vld,
ph_q_2_0_V,
ph_q_2_0_V_ap_vld,
ph_q_2_1_V,
ph_q_2_1_V_ap_vld,
ph_q_2_2_V,
ph_q_2_2_V_ap_vld,
ph_q_3_0_V,
ph_q_3_0_V_ap_vld,
ph_q_3_1_V,
ph_q_3_1_V_ap_vld,
ph_q_3_2_V,
ph_q_3_2_V_ap_vld,
vi_V_address0,
vi_V_ce0,
vi_V_we0,
vi_V_d0,
vi_V_q0,
vi_V_address1,
vi_V_ce1,
vi_V_we1,
vi_V_d1,
vi_V_q1,
hi_V_address0,
hi_V_ce0,
hi_V_we0,
hi_V_d0,
hi_V_q0,
hi_V_address1,
hi_V_ce1,
hi_V_we1,
hi_V_d1,
hi_V_q1,
ci_V_address0,
ci_V_ce0,
ci_V_we0,
ci_V_d0,
ci_V_q0,
ci_V_address1,
ci_V_ce1,
ci_V_we1,
ci_V_d1,
ci_V_q1,
si_V_address0,
si_V_ce0,
si_V_we0,
si_V_d0,
si_V_q0,
si_V_address1,
si_V_ce1,
si_V_we1,
si_V_d1,
si_V_q1,
ph_match_V_address0,
ph_match_V_ce0,
ph_match_V_we0,
ph_match_V_d0,
ph_match_V_q0,
ph_match_V_address1,
ph_match_V_ce1,
ph_match_V_we1,
ph_match_V_d1,
ph_match_V_q1,
th_match_V_address0,
th_match_V_ce0,
th_match_V_we0,
th_match_V_d0,
th_match_V_q0,
th_match_V_address1,
th_match_V_ce1,
th_match_V_we1,
th_match_V_d1,
th_match_V_q1,
th_match11_V_address0,
th_match11_V_ce0,
th_match11_V_we0,
th_match11_V_d0,
th_match11_V_q0,
th_match11_V_address1,
th_match11_V_ce1,
th_match11_V_we1,
th_match11_V_d1,
th_match11_V_q1,
cpat_match_V_address0,
cpat_match_V_ce0,
cpat_match_V_we0,
cpat_match_V_d0,
cpat_match_V_q0,
cpat_match_V_address1,
cpat_match_V_ce1,
cpat_match_V_we1,
cpat_match_V_d1,
cpat_match_V_q1,
ph_qr_V_address0,
ph_qr_V_ce0,
ph_qr_V_we0,
ph_qr_V_d0,
ph_qr_V_q0,
ph_qr_V_address1,
ph_qr_V_ce1,
ph_qr_V_we1,
ph_qr_V_d1,
ph_qr_V_q1,
phi_V_address0,
phi_V_ce0,
phi_V_we0,
phi_V_d0,
phi_V_q0,
phi_V_address1,
phi_V_ce1,
phi_V_we1,
phi_V_d1,
phi_V_q1,
theta_V_address0,
theta_V_ce0,
theta_V_we0,
theta_V_d0,
theta_V_q0,
theta_V_address1,
theta_V_ce1,
theta_V_we1,
theta_V_d1,
theta_V_q1,
cpattern_V_address0,
cpattern_V_ce0,
cpattern_V_we0,
cpattern_V_d0,
cpattern_V_q0,
cpattern_V_address1,
cpattern_V_ce1,
cpattern_V_we1,
cpattern_V_d1,
cpattern_V_q1,
delta_ph_V_address0,
delta_ph_V_ce0,
delta_ph_V_we0,
delta_ph_V_d0,
delta_ph_V_q0,
delta_ph_V_address1,
delta_ph_V_ce1,
delta_ph_V_we1,
delta_ph_V_d1,
delta_ph_V_q1,
delta_th_V_address0,
delta_th_V_ce0,
delta_th_V_we0,
delta_th_V_d0,
delta_th_V_q0,
delta_th_V_address1,
delta_th_V_ce1,
delta_th_V_we1,
delta_th_V_d1,
delta_th_V_q1,
sign_ph_V_address0,
sign_ph_V_ce0,
sign_ph_V_we0,
sign_ph_V_d0,
sign_ph_V_q0,
sign_ph_V_address1,
sign_ph_V_ce1,
sign_ph_V_we1,
sign_ph_V_d1,
sign_ph_V_q1,
sign_th_V_address0,
sign_th_V_ce0,
sign_th_V_we0,
sign_th_V_d0,
sign_th_V_q0,
sign_th_V_address1,
sign_th_V_ce1,
sign_th_V_we1,
sign_th_V_d1,
sign_th_V_q1,
rank_V_address0,
rank_V_ce0,
rank_V_we0,
rank_V_d0,
rank_V_q0,
rank_V_address1,
rank_V_ce1,
rank_V_we1,
rank_V_d1,
rank_V_q1,
vir_V_address0,
vir_V_ce0,
vir_V_we0,
vir_V_d0,
vir_V_q0,
vir_V_address1,
vir_V_ce1,
vir_V_we1,
vir_V_d1,
vir_V_q1,
hir_V_address0,
hir_V_ce0,
hir_V_we0,
hir_V_d0,
hir_V_q0,
hir_V_address1,
hir_V_ce1,
hir_V_we1,
hir_V_d1,
hir_V_q1,
cir_V_address0,
cir_V_ce0,
cir_V_we0,
cir_V_d0,
cir_V_q0,
cir_V_address1,
cir_V_ce1,
cir_V_we1,
cir_V_d1,
cir_V_q1,
sir_V_address0,
sir_V_ce0,
sir_V_we0,
sir_V_d0,
sir_V_q0,
sir_V_address1,
sir_V_ce1,
sir_V_we1,
sir_V_d1,
sir_V_q1,
bt_phi_0_V,
bt_phi_0_V_ap_vld,
bt_phi_1_V,
bt_phi_1_V_ap_vld,
bt_phi_2_V,
bt_phi_2_V_ap_vld,
bt_theta_0_V,
bt_theta_0_V_ap_vld,
bt_theta_1_V,
bt_theta_1_V_ap_vld,
bt_theta_2_V,
bt_theta_2_V_ap_vld,
bt_cpattern_0_0_V,
bt_cpattern_0_0_V_ap_vld,
bt_cpattern_0_1_V,
bt_cpattern_0_1_V_ap_vld,
bt_cpattern_0_2_V,
bt_cpattern_0_2_V_ap_vld,
bt_cpattern_0_3_V,
bt_cpattern_0_3_V_ap_vld,
bt_cpattern_1_0_V,
bt_cpattern_1_0_V_ap_vld,
bt_cpattern_1_1_V,
bt_cpattern_1_1_V_ap_vld,
bt_cpattern_1_2_V,
bt_cpattern_1_2_V_ap_vld,
bt_cpattern_1_3_V,
bt_cpattern_1_3_V_ap_vld,
bt_cpattern_2_0_V,
bt_cpattern_2_0_V_ap_vld,
bt_cpattern_2_1_V,
bt_cpattern_2_1_V_ap_vld,
bt_cpattern_2_2_V,
bt_cpattern_2_2_V_ap_vld,
bt_cpattern_2_3_V,
bt_cpattern_2_3_V_ap_vld,
bt_delta_ph_0_0_V,
bt_delta_ph_0_0_V_ap_vld,
bt_delta_ph_0_1_V,
bt_delta_ph_0_1_V_ap_vld,
bt_delta_ph_0_2_V,
bt_delta_ph_0_2_V_ap_vld,
bt_delta_ph_0_3_V,
bt_delta_ph_0_3_V_ap_vld,
bt_delta_ph_0_4_V,
bt_delta_ph_0_4_V_ap_vld,
bt_delta_ph_0_5_V,
bt_delta_ph_0_5_V_ap_vld,
bt_delta_ph_1_0_V,
bt_delta_ph_1_0_V_ap_vld,
bt_delta_ph_1_1_V,
bt_delta_ph_1_1_V_ap_vld,
bt_delta_ph_1_2_V,
bt_delta_ph_1_2_V_ap_vld,
bt_delta_ph_1_3_V,
bt_delta_ph_1_3_V_ap_vld,
bt_delta_ph_1_4_V,
bt_delta_ph_1_4_V_ap_vld,
bt_delta_ph_1_5_V,
bt_delta_ph_1_5_V_ap_vld,
bt_delta_ph_2_0_V,
bt_delta_ph_2_0_V_ap_vld,
bt_delta_ph_2_1_V,
bt_delta_ph_2_1_V_ap_vld,
bt_delta_ph_2_2_V,
bt_delta_ph_2_2_V_ap_vld,
bt_delta_ph_2_3_V,
bt_delta_ph_2_3_V_ap_vld,
bt_delta_ph_2_4_V,
bt_delta_ph_2_4_V_ap_vld,
bt_delta_ph_2_5_V,
bt_delta_ph_2_5_V_ap_vld,
bt_delta_th_0_0_V,
bt_delta_th_0_0_V_ap_vld,
bt_delta_th_0_1_V,
bt_delta_th_0_1_V_ap_vld,
bt_delta_th_0_2_V,
bt_delta_th_0_2_V_ap_vld,
bt_delta_th_0_3_V,
bt_delta_th_0_3_V_ap_vld,
bt_delta_th_0_4_V,
bt_delta_th_0_4_V_ap_vld,
bt_delta_th_0_5_V,
bt_delta_th_0_5_V_ap_vld,
bt_delta_th_1_0_V,
bt_delta_th_1_0_V_ap_vld,
bt_delta_th_1_1_V,
bt_delta_th_1_1_V_ap_vld,
bt_delta_th_1_2_V,
bt_delta_th_1_2_V_ap_vld,
bt_delta_th_1_3_V,
bt_delta_th_1_3_V_ap_vld,
bt_delta_th_1_4_V,
bt_delta_th_1_4_V_ap_vld,
bt_delta_th_1_5_V,
bt_delta_th_1_5_V_ap_vld,
bt_delta_th_2_0_V,
bt_delta_th_2_0_V_ap_vld,
bt_delta_th_2_1_V,
bt_delta_th_2_1_V_ap_vld,
bt_delta_th_2_2_V,
bt_delta_th_2_2_V_ap_vld,
bt_delta_th_2_3_V,
bt_delta_th_2_3_V_ap_vld,
bt_delta_th_2_4_V,
bt_delta_th_2_4_V_ap_vld,
bt_delta_th_2_5_V,
bt_delta_th_2_5_V_ap_vld,
bt_sign_ph_0_V,
bt_sign_ph_0_V_ap_vld,
bt_sign_ph_1_V,
bt_sign_ph_1_V_ap_vld,
bt_sign_ph_2_V,
bt_sign_ph_2_V_ap_vld,
bt_sign_th_0_V,
bt_sign_th_0_V_ap_vld,
bt_sign_th_1_V,
bt_sign_th_1_V_ap_vld,
bt_sign_th_2_V,
bt_sign_th_2_V_ap_vld,
bt_rank_0_V,
bt_rank_0_V_ap_vld,
bt_rank_1_V,
bt_rank_1_V_ap_vld,
bt_rank_2_V,
bt_rank_2_V_ap_vld,
bt_vi_0_0_V,
bt_vi_0_0_V_ap_vld,
bt_vi_0_1_V,
bt_vi_0_1_V_ap_vld,
bt_vi_0_2_V,
bt_vi_0_2_V_ap_vld,
bt_vi_0_3_V,
bt_vi_0_3_V_ap_vld,
bt_vi_0_4_V,
bt_vi_0_4_V_ap_vld,
bt_vi_1_0_V,
bt_vi_1_0_V_ap_vld,
bt_vi_1_1_V,
bt_vi_1_1_V_ap_vld,
bt_vi_1_2_V,
bt_vi_1_2_V_ap_vld,
bt_vi_1_3_V,
bt_vi_1_3_V_ap_vld,
bt_vi_1_4_V,
bt_vi_1_4_V_ap_vld,
bt_vi_2_0_V,
bt_vi_2_0_V_ap_vld,
bt_vi_2_1_V,
bt_vi_2_1_V_ap_vld,
bt_vi_2_2_V,
bt_vi_2_2_V_ap_vld,
bt_vi_2_3_V,
bt_vi_2_3_V_ap_vld,
bt_vi_2_4_V,
bt_vi_2_4_V_ap_vld,
bt_hi_0_0_V,
bt_hi_0_0_V_ap_vld,
bt_hi_0_1_V,
bt_hi_0_1_V_ap_vld,
bt_hi_0_2_V,
bt_hi_0_2_V_ap_vld,
bt_hi_0_3_V,
bt_hi_0_3_V_ap_vld,
bt_hi_0_4_V,
bt_hi_0_4_V_ap_vld,
bt_hi_1_0_V,
bt_hi_1_0_V_ap_vld,
bt_hi_1_1_V,
bt_hi_1_1_V_ap_vld,
bt_hi_1_2_V,
bt_hi_1_2_V_ap_vld,
bt_hi_1_3_V,
bt_hi_1_3_V_ap_vld,
bt_hi_1_4_V,
bt_hi_1_4_V_ap_vld,
bt_hi_2_0_V,
bt_hi_2_0_V_ap_vld,
bt_hi_2_1_V,
bt_hi_2_1_V_ap_vld,
bt_hi_2_2_V,
bt_hi_2_2_V_ap_vld,
bt_hi_2_3_V,
bt_hi_2_3_V_ap_vld,
bt_hi_2_4_V,
bt_hi_2_4_V_ap_vld,
bt_ci_0_0_V,
bt_ci_0_0_V_ap_vld,
bt_ci_0_1_V,
bt_ci_0_1_V_ap_vld,
bt_ci_0_2_V,
bt_ci_0_2_V_ap_vld,
bt_ci_0_3_V,
bt_ci_0_3_V_ap_vld,
bt_ci_0_4_V,
bt_ci_0_4_V_ap_vld,
bt_ci_1_0_V,
bt_ci_1_0_V_ap_vld,
bt_ci_1_1_V,
bt_ci_1_1_V_ap_vld,
bt_ci_1_2_V,
bt_ci_1_2_V_ap_vld,
bt_ci_1_3_V,
bt_ci_1_3_V_ap_vld,
bt_ci_1_4_V,
bt_ci_1_4_V_ap_vld,
bt_ci_2_0_V,
bt_ci_2_0_V_ap_vld,
bt_ci_2_1_V,
bt_ci_2_1_V_ap_vld,
bt_ci_2_2_V,
bt_ci_2_2_V_ap_vld,
bt_ci_2_3_V,
bt_ci_2_3_V_ap_vld,
bt_ci_2_4_V,
bt_ci_2_4_V_ap_vld,
bt_si_0_V,
bt_si_0_V_ap_vld,
bt_si_1_V,
bt_si_1_V_ap_vld,
bt_si_2_V,
bt_si_2_V_ap_vld,
ptlut_addr_0_V,
ptlut_addr_0_V_ap_vld,
ptlut_addr_1_V,
ptlut_addr_1_V_ap_vld,
ptlut_addr_2_V,
ptlut_addr_2_V_ap_vld,
ptlut_cs_0_V,
ptlut_cs_0_V_ap_vld,
ptlut_cs_1_V,
ptlut_cs_1_V_ap_vld,
ptlut_cs_2_V,
ptlut_cs_2_V_ap_vld,
ptlut_addr_val_V,
ptlut_addr_val_V_ap_vld,
gmt_phi_0_V,
gmt_phi_0_V_ap_vld,
gmt_phi_1_V,
gmt_phi_1_V_ap_vld,
gmt_phi_2_V,
gmt_phi_2_V_ap_vld,
gmt_eta_0_V,
gmt_eta_0_V_ap_vld,
gmt_eta_1_V,
gmt_eta_1_V_ap_vld,
gmt_eta_2_V,
gmt_eta_2_V_ap_vld,
gmt_qlt_0_V,
gmt_qlt_0_V_ap_vld,
gmt_qlt_1_V,
gmt_qlt_1_V_ap_vld,
gmt_qlt_2_V,
gmt_qlt_2_V_ap_vld,
gmt_crg_V,
gmt_crg_V_ap_vld,
endcap_V,
sector_V,
lat_test_V,
print_flag_V,
ph_num_0_0_V_ap_lwr,
ph_num_0_1_V_ap_lwr,
ph_num_0_2_V_ap_lwr,
ph_num_1_0_V_ap_lwr,
ph_num_1_1_V_ap_lwr,
ph_num_1_2_V_ap_lwr,
ph_num_2_0_V_ap_lwr,
ph_num_2_1_V_ap_lwr,
ph_num_2_2_V_ap_lwr,
ph_num_3_0_V_ap_lwr,
ph_num_3_1_V_ap_lwr,
ph_num_3_2_V_ap_lwr,
ph_q_0_0_V_ap_lwr,
ph_q_0_1_V_ap_lwr,
ph_q_0_2_V_ap_lwr,
ph_q_1_0_V_ap_lwr,
ph_q_1_1_V_ap_lwr,
ph_q_1_2_V_ap_lwr,
ph_q_2_0_V_ap_lwr,
ph_q_2_1_V_ap_lwr,
ph_q_2_2_V_ap_lwr,
ph_q_3_0_V_ap_lwr,
ph_q_3_1_V_ap_lwr,
ph_q_3_2_V_ap_lwr
);
parameter ap_ST_pp0_stg0_fsm_0 = 1'b1;
parameter ap_const_lv32_0 = 32'b00000000000000000000000000000000;
parameter ap_const_lv3_0 = 3'b000;
parameter ap_const_lv12_0 = 12'b000000000000;
parameter ap_const_lv6_0 = 6'b000000;
parameter ap_const_lv4_0 = 4'b0000;
parameter ap_const_lv2_0 = 2'b00;
parameter ap_const_lv5_0 = 5'b00000;
parameter ap_const_lv7_0 = 7'b0000000;
parameter ap_const_lv44_0 = 44'b00000000000000000000000000000000000000000000;
parameter ap_const_lv64_0 = 64'b0000000000000000000000000000000000000000000000000000000000000000;
parameter ap_const_lv9_0 = 9'b000000000;
parameter ap_const_lv8_0 = 8'b00000000;
input ap_clk;
input ap_rst;
input [3:0] q_0_0_0_V;
input [3:0] q_0_0_1_V;
input [3:0] q_0_1_0_V;
input [3:0] q_0_1_1_V;
input [3:0] q_0_2_0_V;
input [3:0] q_0_2_1_V;
input [3:0] q_0_3_0_V;
input [3:0] q_0_3_1_V;
input [3:0] q_0_4_0_V;
input [3:0] q_0_4_1_V;
input [3:0] q_0_5_0_V;
input [3:0] q_0_5_1_V;
input [3:0] q_0_6_0_V;
input [3:0] q_0_6_1_V;
input [3:0] q_0_7_0_V;
input [3:0] q_0_7_1_V;
input [3:0] q_0_8_0_V;
input [3:0] q_0_8_1_V;
input [3:0] q_1_0_0_V;
input [3:0] q_1_0_1_V;
input [3:0] q_1_1_0_V;
input [3:0] q_1_1_1_V;
input [3:0] q_1_2_0_V;
input [3:0] q_1_2_1_V;
input [3:0] q_1_3_0_V;
input [3:0] q_1_3_1_V;
input [3:0] q_1_4_0_V;
input [3:0] q_1_4_1_V;
input [3:0] q_1_5_0_V;
input [3:0] q_1_5_1_V;
input [3:0] q_1_6_0_V;
input [3:0] q_1_6_1_V;
input [3:0] q_1_7_0_V;
input [3:0] q_1_7_1_V;
input [3:0] q_1_8_0_V;
input [3:0] q_1_8_1_V;
input [3:0] q_2_0_0_V;
input [3:0] q_2_0_1_V;
input [3:0] q_2_1_0_V;
input [3:0] q_2_1_1_V;
input [3:0] q_2_2_0_V;
input [3:0] q_2_2_1_V;
input [3:0] q_2_3_0_V;
input [3:0] q_2_3_1_V;
input [3:0] q_2_4_0_V;
input [3:0] q_2_4_1_V;
input [3:0] q_2_5_0_V;
input [3:0] q_2_5_1_V;
input [3:0] q_2_6_0_V;
input [3:0] q_2_6_1_V;
input [3:0] q_2_7_0_V;
input [3:0] q_2_7_1_V;
input [3:0] q_2_8_0_V;
input [3:0] q_2_8_1_V;
input [3:0] q_3_0_0_V;
input [3:0] q_3_0_1_V;
input [3:0] q_3_1_0_V;
input [3:0] q_3_1_1_V;
input [3:0] q_3_2_0_V;
input [3:0] q_3_2_1_V;
input [3:0] q_3_3_0_V;
input [3:0] q_3_3_1_V;
input [3:0] q_3_4_0_V;
input [3:0] q_3_4_1_V;
input [3:0] q_3_5_0_V;
input [3:0] q_3_5_1_V;
input [3:0] q_3_6_0_V;
input [3:0] q_3_6_1_V;
input [3:0] q_3_7_0_V;
input [3:0] q_3_7_1_V;
input [3:0] q_3_8_0_V;
input [3:0] q_3_8_1_V;
input [3:0] q_4_0_0_V;
input [3:0] q_4_0_1_V;
input [3:0] q_4_1_0_V;
input [3:0] q_4_1_1_V;
input [3:0] q_4_2_0_V;
input [3:0] q_4_2_1_V;
input [3:0] q_4_3_0_V;
input [3:0] q_4_3_1_V;
input [3:0] q_4_4_0_V;
input [3:0] q_4_4_1_V;
input [3:0] q_4_5_0_V;
input [3:0] q_4_5_1_V;
input [3:0] q_4_6_0_V;
input [3:0] q_4_6_1_V;
input [3:0] q_4_7_0_V;
input [3:0] q_4_7_1_V;
input [3:0] q_4_8_0_V;
input [3:0] q_4_8_1_V;
input [6:0] wg_0_0_0_V;
input [6:0] wg_0_0_1_V;
input [6:0] wg_0_1_0_V;
input [6:0] wg_0_1_1_V;
input [6:0] wg_0_2_0_V;
input [6:0] wg_0_2_1_V;
input [6:0] wg_0_3_0_V;
input [6:0] wg_0_3_1_V;
input [6:0] wg_0_4_0_V;
input [6:0] wg_0_4_1_V;
input [6:0] wg_0_5_0_V;
input [6:0] wg_0_5_1_V;
input [6:0] wg_0_6_0_V;
input [6:0] wg_0_6_1_V;
input [6:0] wg_0_7_0_V;
input [6:0] wg_0_7_1_V;
input [6:0] wg_0_8_0_V;
input [6:0] wg_0_8_1_V;
input [6:0] wg_1_0_0_V;
input [6:0] wg_1_0_1_V;
input [6:0] wg_1_1_0_V;
input [6:0] wg_1_1_1_V;
input [6:0] wg_1_2_0_V;
input [6:0] wg_1_2_1_V;
input [6:0] wg_1_3_0_V;
input [6:0] wg_1_3_1_V;
input [6:0] wg_1_4_0_V;
input [6:0] wg_1_4_1_V;
input [6:0] wg_1_5_0_V;
input [6:0] wg_1_5_1_V;
input [6:0] wg_1_6_0_V;
input [6:0] wg_1_6_1_V;
input [6:0] wg_1_7_0_V;
input [6:0] wg_1_7_1_V;
input [6:0] wg_1_8_0_V;
input [6:0] wg_1_8_1_V;
input [6:0] wg_2_0_0_V;
input [6:0] wg_2_0_1_V;
input [6:0] wg_2_1_0_V;
input [6:0] wg_2_1_1_V;
input [6:0] wg_2_2_0_V;
input [6:0] wg_2_2_1_V;
input [6:0] wg_2_3_0_V;
input [6:0] wg_2_3_1_V;
input [6:0] wg_2_4_0_V;
input [6:0] wg_2_4_1_V;
input [6:0] wg_2_5_0_V;
input [6:0] wg_2_5_1_V;
input [6:0] wg_2_6_0_V;
input [6:0] wg_2_6_1_V;
input [6:0] wg_2_7_0_V;
input [6:0] wg_2_7_1_V;
input [6:0] wg_2_8_0_V;
input [6:0] wg_2_8_1_V;
input [6:0] wg_3_0_0_V;
input [6:0] wg_3_0_1_V;
input [6:0] wg_3_1_0_V;
input [6:0] wg_3_1_1_V;
input [6:0] wg_3_2_0_V;
input [6:0] wg_3_2_1_V;
input [6:0] wg_3_3_0_V;
input [6:0] wg_3_3_1_V;
input [6:0] wg_3_4_0_V;
input [6:0] wg_3_4_1_V;
input [6:0] wg_3_5_0_V;
input [6:0] wg_3_5_1_V;
input [6:0] wg_3_6_0_V;
input [6:0] wg_3_6_1_V;
input [6:0] wg_3_7_0_V;
input [6:0] wg_3_7_1_V;
input [6:0] wg_3_8_0_V;
input [6:0] wg_3_8_1_V;
input [6:0] wg_4_0_0_V;
input [6:0] wg_4_0_1_V;
input [6:0] wg_4_1_0_V;
input [6:0] wg_4_1_1_V;
input [6:0] wg_4_2_0_V;
input [6:0] wg_4_2_1_V;
input [6:0] wg_4_3_0_V;
input [6:0] wg_4_3_1_V;
input [6:0] wg_4_4_0_V;
input [6:0] wg_4_4_1_V;
input [6:0] wg_4_5_0_V;
input [6:0] wg_4_5_1_V;
input [6:0] wg_4_6_0_V;
input [6:0] wg_4_6_1_V;
input [6:0] wg_4_7_0_V;
input [6:0] wg_4_7_1_V;
input [6:0] wg_4_8_0_V;
input [6:0] wg_4_8_1_V;
input [7:0] hstr_0_0_0_V;
input [7:0] hstr_0_0_1_V;
input [7:0] hstr_0_1_0_V;
input [7:0] hstr_0_1_1_V;
input [7:0] hstr_0_2_0_V;
input [7:0] hstr_0_2_1_V;
input [7:0] hstr_0_3_0_V;
input [7:0] hstr_0_3_1_V;
input [7:0] hstr_0_4_0_V;
input [7:0] hstr_0_4_1_V;
input [7:0] hstr_0_5_0_V;
input [7:0] hstr_0_5_1_V;
input [7:0] hstr_0_6_0_V;
input [7:0] hstr_0_6_1_V;
input [7:0] hstr_0_7_0_V;
input [7:0] hstr_0_7_1_V;
input [7:0] hstr_0_8_0_V;
input [7:0] hstr_0_8_1_V;
input [7:0] hstr_1_0_0_V;
input [7:0] hstr_1_0_1_V;
input [7:0] hstr_1_1_0_V;
input [7:0] hstr_1_1_1_V;
input [7:0] hstr_1_2_0_V;
input [7:0] hstr_1_2_1_V;
input [7:0] hstr_1_3_0_V;
input [7:0] hstr_1_3_1_V;
input [7:0] hstr_1_4_0_V;
input [7:0] hstr_1_4_1_V;
input [7:0] hstr_1_5_0_V;
input [7:0] hstr_1_5_1_V;
input [7:0] hstr_1_6_0_V;
input [7:0] hstr_1_6_1_V;
input [7:0] hstr_1_7_0_V;
input [7:0] hstr_1_7_1_V;
input [7:0] hstr_1_8_0_V;
input [7:0] hstr_1_8_1_V;
input [7:0] hstr_2_0_0_V;
input [7:0] hstr_2_0_1_V;
input [7:0] hstr_2_1_0_V;
input [7:0] hstr_2_1_1_V;
input [7:0] hstr_2_2_0_V;
input [7:0] hstr_2_2_1_V;
input [7:0] hstr_2_3_0_V;
input [7:0] hstr_2_3_1_V;
input [7:0] hstr_2_4_0_V;
input [7:0] hstr_2_4_1_V;
input [7:0] hstr_2_5_0_V;
input [7:0] hstr_2_5_1_V;
input [7:0] hstr_2_6_0_V;
input [7:0] hstr_2_6_1_V;
input [7:0] hstr_2_7_0_V;
input [7:0] hstr_2_7_1_V;
input [7:0] hstr_2_8_0_V;
input [7:0] hstr_2_8_1_V;
input [7:0] hstr_3_0_0_V;
input [7:0] hstr_3_0_1_V;
input [7:0] hstr_3_1_0_V;
input [7:0] hstr_3_1_1_V;
input [7:0] hstr_3_2_0_V;
input [7:0] hstr_3_2_1_V;
input [7:0] hstr_3_3_0_V;
input [7:0] hstr_3_3_1_V;
input [7:0] hstr_3_4_0_V;
input [7:0] hstr_3_4_1_V;
input [7:0] hstr_3_5_0_V;
input [7:0] hstr_3_5_1_V;
input [7:0] hstr_3_6_0_V;
input [7:0] hstr_3_6_1_V;
input [7:0] hstr_3_7_0_V;
input [7:0] hstr_3_7_1_V;
input [7:0] hstr_3_8_0_V;
input [7:0] hstr_3_8_1_V;
input [7:0] hstr_4_0_0_V;
input [7:0] hstr_4_0_1_V;
input [7:0] hstr_4_1_0_V;
input [7:0] hstr_4_1_1_V;
input [7:0] hstr_4_2_0_V;
input [7:0] hstr_4_2_1_V;
input [7:0] hstr_4_3_0_V;
input [7:0] hstr_4_3_1_V;
input [7:0] hstr_4_4_0_V;
input [7:0] hstr_4_4_1_V;
input [7:0] hstr_4_5_0_V;
input [7:0] hstr_4_5_1_V;
input [7:0] hstr_4_6_0_V;
input [7:0] hstr_4_6_1_V;
input [7:0] hstr_4_7_0_V;
input [7:0] hstr_4_7_1_V;
input [7:0] hstr_4_8_0_V;
input [7:0] hstr_4_8_1_V;
input [3:0] cpat_0_0_0_V;
input [3:0] cpat_0_0_1_V;
input [3:0] cpat_0_1_0_V;
input [3:0] cpat_0_1_1_V;
input [3:0] cpat_0_2_0_V;
input [3:0] cpat_0_2_1_V;
input [3:0] cpat_0_3_0_V;
input [3:0] cpat_0_3_1_V;
input [3:0] cpat_0_4_0_V;
input [3:0] cpat_0_4_1_V;
input [3:0] cpat_0_5_0_V;
input [3:0] cpat_0_5_1_V;
input [3:0] cpat_0_6_0_V;
input [3:0] cpat_0_6_1_V;
input [3:0] cpat_0_7_0_V;
input [3:0] cpat_0_7_1_V;
input [3:0] cpat_0_8_0_V;
input [3:0] cpat_0_8_1_V;
input [3:0] cpat_1_0_0_V;
input [3:0] cpat_1_0_1_V;
input [3:0] cpat_1_1_0_V;
input [3:0] cpat_1_1_1_V;
input [3:0] cpat_1_2_0_V;
input [3:0] cpat_1_2_1_V;
input [3:0] cpat_1_3_0_V;
input [3:0] cpat_1_3_1_V;
input [3:0] cpat_1_4_0_V;
input [3:0] cpat_1_4_1_V;
input [3:0] cpat_1_5_0_V;
input [3:0] cpat_1_5_1_V;
input [3:0] cpat_1_6_0_V;
input [3:0] cpat_1_6_1_V;
input [3:0] cpat_1_7_0_V;
input [3:0] cpat_1_7_1_V;
input [3:0] cpat_1_8_0_V;
input [3:0] cpat_1_8_1_V;
input [3:0] cpat_2_0_0_V;
input [3:0] cpat_2_0_1_V;
input [3:0] cpat_2_1_0_V;
input [3:0] cpat_2_1_1_V;
input [3:0] cpat_2_2_0_V;
input [3:0] cpat_2_2_1_V;
input [3:0] cpat_2_3_0_V;
input [3:0] cpat_2_3_1_V;
input [3:0] cpat_2_4_0_V;
input [3:0] cpat_2_4_1_V;
input [3:0] cpat_2_5_0_V;
input [3:0] cpat_2_5_1_V;
input [3:0] cpat_2_6_0_V;
input [3:0] cpat_2_6_1_V;
input [3:0] cpat_2_7_0_V;
input [3:0] cpat_2_7_1_V;
input [3:0] cpat_2_8_0_V;
input [3:0] cpat_2_8_1_V;
input [3:0] cpat_3_0_0_V;
input [3:0] cpat_3_0_1_V;
input [3:0] cpat_3_1_0_V;
input [3:0] cpat_3_1_1_V;
input [3:0] cpat_3_2_0_V;
input [3:0] cpat_3_2_1_V;
input [3:0] cpat_3_3_0_V;
input [3:0] cpat_3_3_1_V;
input [3:0] cpat_3_4_0_V;
input [3:0] cpat_3_4_1_V;
input [3:0] cpat_3_5_0_V;
input [3:0] cpat_3_5_1_V;
input [3:0] cpat_3_6_0_V;
input [3:0] cpat_3_6_1_V;
input [3:0] cpat_3_7_0_V;
input [3:0] cpat_3_7_1_V;
input [3:0] cpat_3_8_0_V;
input [3:0] cpat_3_8_1_V;
input [3:0] cpat_4_0_0_V;
input [3:0] cpat_4_0_1_V;
input [3:0] cpat_4_1_0_V;
input [3:0] cpat_4_1_1_V;
input [3:0] cpat_4_2_0_V;
input [3:0] cpat_4_2_1_V;
input [3:0] cpat_4_3_0_V;
input [3:0] cpat_4_3_1_V;
input [3:0] cpat_4_4_0_V;
input [3:0] cpat_4_4_1_V;
input [3:0] cpat_4_5_0_V;
input [3:0] cpat_4_5_1_V;
input [3:0] cpat_4_6_0_V;
input [3:0] cpat_4_6_1_V;
input [3:0] cpat_4_7_0_V;
input [3:0] cpat_4_7_1_V;
input [3:0] cpat_4_8_0_V;
input [3:0] cpat_4_8_1_V;
input [8:0] pcs_cs_0_V;
input [8:0] pcs_cs_1_V;
input [8:0] pcs_cs_2_V;
input [8:0] pcs_cs_3_V;
input [8:0] pcs_cs_4_V;
output [1:0] pps_cs_V_address0;
output pps_cs_V_ce0;
output pps_cs_V_we0;
output [4:0] pps_cs_V_d0;
input [4:0] pps_cs_V_q0;
output [1:0] pps_cs_V_address1;
output pps_cs_V_ce1;
output pps_cs_V_we1;
output [4:0] pps_cs_V_d1;
input [4:0] pps_cs_V_q1;
input [2:0] sel_V;
input [6:0] addr_V;
input [11:0] r_in_V;
input [11:0] r_out_V;
input [0:0] we_V;
output [6:0] ph_V_address0;
output ph_V_ce0;
output ph_V_we0;
output [11:0] ph_V_d0;
input [11:0] ph_V_q0;
output [6:0] ph_V_address1;
output ph_V_ce1;
output ph_V_we1;
output [11:0] ph_V_d1;
input [11:0] ph_V_q1;
output [4:0] th11_V_address0;
output th11_V_ce0;
output th11_V_we0;
output [6:0] th11_V_d0;
input [6:0] th11_V_q0;
output [4:0] th11_V_address1;
output th11_V_ce1;
output th11_V_we1;
output [6:0] th11_V_d1;
input [6:0] th11_V_q1;
output [6:0] th_V_address0;
output th_V_ce0;
output th_V_we0;
output [6:0] th_V_d0;
input [6:0] th_V_q0;
output [6:0] th_V_address1;
output th_V_ce1;
output th_V_we1;
output [6:0] th_V_d1;
input [6:0] th_V_q1;
output [5:0] vl_V_address0;
output vl_V_ce0;
output vl_V_we0;
output [1:0] vl_V_d0;
input [1:0] vl_V_q0;
output [5:0] vl_V_address1;
output vl_V_ce1;
output vl_V_we1;
output [1:0] vl_V_d1;
input [1:0] vl_V_q1;
output [5:0] phzvl_V_address0;
output phzvl_V_ce0;
output phzvl_V_we0;
output [2:0] phzvl_V_d0;
input [2:0] phzvl_V_q0;
output [5:0] phzvl_V_address1;
output phzvl_V_ce1;
output phzvl_V_we1;
output [2:0] phzvl_V_d1;
input [2:0] phzvl_V_q1;
output [2:0] me11a_V_address0;
output me11a_V_ce0;
output me11a_V_we0;
output [1:0] me11a_V_d0;
input [1:0] me11a_V_q0;
output [2:0] me11a_V_address1;
output me11a_V_ce1;
output me11a_V_we1;
output [1:0] me11a_V_d1;
input [1:0] me11a_V_q1;
output [6:0] cpatr_V_address0;
output cpatr_V_ce0;
output cpatr_V_we0;
output [3:0] cpatr_V_d0;
input [3:0] cpatr_V_q0;
output [6:0] cpatr_V_address1;
output cpatr_V_ce1;
output cpatr_V_we1;
output [3:0] cpatr_V_d1;
input [3:0] cpatr_V_q1;
output [5:0] ph_hit_V_address0;
output ph_hit_V_ce0;
output ph_hit_V_we0;
output [43:0] ph_hit_V_d0;
input [43:0] ph_hit_V_q0;
output [5:0] ph_hit_V_address1;
output ph_hit_V_ce1;
output ph_hit_V_we1;
output [43:0] ph_hit_V_d1;
input [43:0] ph_hit_V_q1;
output [5:0] th_hit_V_address0;
output th_hit_V_ce0;
output th_hit_V_we0;
output [63:0] th_hit_V_d0;
input [63:0] th_hit_V_q0;
output [5:0] th_hit_V_address1;
output th_hit_V_ce1;
output th_hit_V_we1;
output [63:0] th_hit_V_d1;
input [63:0] th_hit_V_q1;
output [121:0] ph_zone_0_0_V;
output ph_zone_0_0_V_ap_vld;
output [121:0] ph_zone_0_1_V;
output ph_zone_0_1_V_ap_vld;
output [121:0] ph_zone_0_2_V;
output ph_zone_0_2_V_ap_vld;
output [121:0] ph_zone_0_3_V;
output ph_zone_0_3_V_ap_vld;
output [121:0] ph_zone_0_4_V;
output ph_zone_0_4_V_ap_vld;
output [121:0] ph_zone_1_0_V;
output ph_zone_1_0_V_ap_vld;
output [121:0] ph_zone_1_1_V;
output ph_zone_1_1_V_ap_vld;
output [121:0] ph_zone_1_2_V;
output ph_zone_1_2_V_ap_vld;
output [121:0] ph_zone_1_3_V;
output ph_zone_1_3_V_ap_vld;
output [121:0] ph_zone_1_4_V;
output ph_zone_1_4_V_ap_vld;
output [121:0] ph_zone_2_0_V;
output ph_zone_2_0_V_ap_vld;
output [121:0] ph_zone_2_1_V;
output ph_zone_2_1_V_ap_vld;
output [121:0] ph_zone_2_2_V;
output ph_zone_2_2_V_ap_vld;
output [121:0] ph_zone_2_3_V;
output ph_zone_2_3_V_ap_vld;
output [121:0] ph_zone_2_4_V;
output ph_zone_2_4_V_ap_vld;
output [121:0] ph_zone_3_0_V;
output ph_zone_3_0_V_ap_vld;
output [121:0] ph_zone_3_1_V;
output ph_zone_3_1_V_ap_vld;
output [121:0] ph_zone_3_2_V;
output ph_zone_3_2_V_ap_vld;
output [121:0] ph_zone_3_3_V;
output ph_zone_3_3_V_ap_vld;
output [121:0] ph_zone_3_4_V;
output ph_zone_3_4_V_ap_vld;
output [121:0] ph_ext_0_0_V;
output ph_ext_0_0_V_ap_vld;
output [121:0] ph_ext_0_1_V;
output ph_ext_0_1_V_ap_vld;
output [121:0] ph_ext_0_2_V;
output ph_ext_0_2_V_ap_vld;
output [121:0] ph_ext_0_3_V;
output ph_ext_0_3_V_ap_vld;
output [121:0] ph_ext_0_4_V;
output ph_ext_0_4_V_ap_vld;
output [121:0] ph_ext_1_0_V;
output ph_ext_1_0_V_ap_vld;
output [121:0] ph_ext_1_1_V;
output ph_ext_1_1_V_ap_vld;
output [121:0] ph_ext_1_2_V;
output ph_ext_1_2_V_ap_vld;
output [121:0] ph_ext_1_3_V;
output ph_ext_1_3_V_ap_vld;
output [121:0] ph_ext_1_4_V;
output ph_ext_1_4_V_ap_vld;
output [121:0] ph_ext_2_0_V;
output ph_ext_2_0_V_ap_vld;
output [121:0] ph_ext_2_1_V;
output ph_ext_2_1_V_ap_vld;
output [121:0] ph_ext_2_2_V;
output ph_ext_2_2_V_ap_vld;
output [121:0] ph_ext_2_3_V;
output ph_ext_2_3_V_ap_vld;
output [121:0] ph_ext_2_4_V;
output ph_ext_2_4_V_ap_vld;
output [121:0] ph_ext_3_0_V;
output ph_ext_3_0_V_ap_vld;
output [121:0] ph_ext_3_1_V;
output ph_ext_3_1_V_ap_vld;
output [121:0] ph_ext_3_2_V;
output ph_ext_3_2_V_ap_vld;
output [121:0] ph_ext_3_3_V;
output ph_ext_3_3_V_ap_vld;
output [121:0] ph_ext_3_4_V;
output ph_ext_3_4_V_ap_vld;
output [8:0] ph_rank_V_address0;
output ph_rank_V_ce0;
output ph_rank_V_we0;
output [5:0] ph_rank_V_d0;
input [5:0] ph_rank_V_q0;
output [8:0] ph_rank_V_address1;
output ph_rank_V_ce1;
output ph_rank_V_we1;
output [5:0] ph_rank_V_d1;
input [5:0] ph_rank_V_q1;
output [6:0] ph_num_0_0_V;
output ph_num_0_0_V_ap_vld;
output [6:0] ph_num_0_1_V;
output ph_num_0_1_V_ap_vld;
output [6:0] ph_num_0_2_V;
output ph_num_0_2_V_ap_vld;
output [6:0] ph_num_1_0_V;
output ph_num_1_0_V_ap_vld;
output [6:0] ph_num_1_1_V;
output ph_num_1_1_V_ap_vld;
output [6:0] ph_num_1_2_V;
output ph_num_1_2_V_ap_vld;
output [6:0] ph_num_2_0_V;
output ph_num_2_0_V_ap_vld;
output [6:0] ph_num_2_1_V;
output ph_num_2_1_V_ap_vld;
output [6:0] ph_num_2_2_V;
output ph_num_2_2_V_ap_vld;
output [6:0] ph_num_3_0_V;
output ph_num_3_0_V_ap_vld;
output [6:0] ph_num_3_1_V;
output ph_num_3_1_V_ap_vld;
output [6:0] ph_num_3_2_V;
output ph_num_3_2_V_ap_vld;
output [5:0] ph_q_0_0_V;
output ph_q_0_0_V_ap_vld;
output [5:0] ph_q_0_1_V;
output ph_q_0_1_V_ap_vld;
output [5:0] ph_q_0_2_V;
output ph_q_0_2_V_ap_vld;
output [5:0] ph_q_1_0_V;
output ph_q_1_0_V_ap_vld;
output [5:0] ph_q_1_1_V;
output ph_q_1_1_V_ap_vld;
output [5:0] ph_q_1_2_V;
output ph_q_1_2_V_ap_vld;
output [5:0] ph_q_2_0_V;
output ph_q_2_0_V_ap_vld;
output [5:0] ph_q_2_1_V;
output ph_q_2_1_V_ap_vld;
output [5:0] ph_q_2_2_V;
output ph_q_2_2_V_ap_vld;
output [5:0] ph_q_3_0_V;
output ph_q_3_0_V_ap_vld;
output [5:0] ph_q_3_1_V;
output ph_q_3_1_V_ap_vld;
output [5:0] ph_q_3_2_V;
output ph_q_3_2_V_ap_vld;
output [5:0] vi_V_address0;
output vi_V_ce0;
output vi_V_we0;
output [1:0] vi_V_d0;
input [1:0] vi_V_q0;
output [5:0] vi_V_address1;
output vi_V_ce1;
output vi_V_we1;
output [1:0] vi_V_d1;
input [1:0] vi_V_q1;
output [5:0] hi_V_address0;
output hi_V_ce0;
output hi_V_we0;
output [1:0] hi_V_d0;
input [1:0] hi_V_q0;
output [5:0] hi_V_address1;
output hi_V_ce1;
output hi_V_we1;
output [1:0] hi_V_d1;
input [1:0] hi_V_q1;
output [5:0] ci_V_address0;
output ci_V_ce0;
output ci_V_we0;
output [2:0] ci_V_d0;
input [2:0] ci_V_q0;
output [5:0] ci_V_address1;
output ci_V_ce1;
output ci_V_we1;
output [2:0] ci_V_d1;
input [2:0] ci_V_q1;
output [3:0] si_V_address0;
output si_V_ce0;
output si_V_we0;
output [3:0] si_V_d0;
input [3:0] si_V_q0;
output [3:0] si_V_address1;
output si_V_ce1;
output si_V_we1;
output [3:0] si_V_d1;
input [3:0] si_V_q1;
output [5:0] ph_match_V_address0;
output ph_match_V_ce0;
output ph_match_V_we0;
output [11:0] ph_match_V_d0;
input [11:0] ph_match_V_q0;
output [5:0] ph_match_V_address1;
output ph_match_V_ce1;
output ph_match_V_we1;
output [11:0] ph_match_V_d1;
input [11:0] ph_match_V_q1;
output [7:0] th_match_V_address0;
output th_match_V_ce0;
output th_match_V_we0;
output [6:0] th_match_V_d0;
input [6:0] th_match_V_q0;
output [7:0] th_match_V_address1;
output th_match_V_ce1;
output th_match_V_we1;
output [6:0] th_match_V_d1;
input [6:0] th_match_V_q1;
output [4:0] th_match11_V_address0;
output th_match11_V_ce0;
output th_match11_V_we0;
output [6:0] th_match11_V_d0;
input [6:0] th_match11_V_q0;
output [4:0] th_match11_V_address1;
output th_match11_V_ce1;
output th_match11_V_we1;
output [6:0] th_match11_V_d1;
input [6:0] th_match11_V_q1;
output [5:0] cpat_match_V_address0;
output cpat_match_V_ce0;
output cpat_match_V_we0;
output [3:0] cpat_match_V_d0;
input [3:0] cpat_match_V_q0;
output [5:0] cpat_match_V_address1;
output cpat_match_V_ce1;
output cpat_match_V_we1;
output [3:0] cpat_match_V_d1;
input [3:0] cpat_match_V_q1;
output [3:0] ph_qr_V_address0;
output ph_qr_V_ce0;
output ph_qr_V_we0;
output [5:0] ph_qr_V_d0;
input [5:0] ph_qr_V_q0;
output [3:0] ph_qr_V_address1;
output ph_qr_V_ce1;
output ph_qr_V_we1;
output [5:0] ph_qr_V_d1;
input [5:0] ph_qr_V_q1;
output [3:0] phi_V_address0;
output phi_V_ce0;
output phi_V_we0;
output [11:0] phi_V_d0;
input [11:0] phi_V_q0;
output [3:0] phi_V_address1;
output phi_V_ce1;
output phi_V_we1;
output [11:0] phi_V_d1;
input [11:0] phi_V_q1;
output [3:0] theta_V_address0;
output theta_V_ce0;
output theta_V_we0;
output [6:0] theta_V_d0;
input [6:0] theta_V_q0;
output [3:0] theta_V_address1;
output theta_V_ce1;
output theta_V_we1;
output [6:0] theta_V_d1;
input [6:0] theta_V_q1;
output [5:0] cpattern_V_address0;
output cpattern_V_ce0;
output cpattern_V_we0;
output [3:0] cpattern_V_d0;
input [3:0] cpattern_V_q0;
output [5:0] cpattern_V_address1;
output cpattern_V_ce1;
output cpattern_V_we1;
output [3:0] cpattern_V_d1;
input [3:0] cpattern_V_q1;
output [6:0] delta_ph_V_address0;
output delta_ph_V_ce0;
output delta_ph_V_we0;
output [11:0] delta_ph_V_d0;
input [11:0] delta_ph_V_q0;
output [6:0] delta_ph_V_address1;
output delta_ph_V_ce1;
output delta_ph_V_we1;
output [11:0] delta_ph_V_d1;
input [11:0] delta_ph_V_q1;
output [6:0] delta_th_V_address0;
output delta_th_V_ce0;
output delta_th_V_we0;
output [6:0] delta_th_V_d0;
input [6:0] delta_th_V_q0;
output [6:0] delta_th_V_address1;
output delta_th_V_ce1;
output delta_th_V_we1;
output [6:0] delta_th_V_d1;
input [6:0] delta_th_V_q1;
output [3:0] sign_ph_V_address0;
output sign_ph_V_ce0;
output sign_ph_V_we0;
output [5:0] sign_ph_V_d0;
input [5:0] sign_ph_V_q0;
output [3:0] sign_ph_V_address1;
output sign_ph_V_ce1;
output sign_ph_V_we1;
output [5:0] sign_ph_V_d1;
input [5:0] sign_ph_V_q1;
output [3:0] sign_th_V_address0;
output sign_th_V_ce0;
output sign_th_V_we0;
output [5:0] sign_th_V_d0;
input [5:0] sign_th_V_q0;
output [3:0] sign_th_V_address1;
output sign_th_V_ce1;
output sign_th_V_we1;
output [5:0] sign_th_V_d1;
input [5:0] sign_th_V_q1;
output [3:0] rank_V_address0;
output rank_V_ce0;
output rank_V_we0;
output [6:0] rank_V_d0;
input [6:0] rank_V_q0;
output [3:0] rank_V_address1;
output rank_V_ce1;
output rank_V_we1;
output [6:0] rank_V_d1;
input [6:0] rank_V_q1;
output [5:0] vir_V_address0;
output vir_V_ce0;
output vir_V_we0;
output [1:0] vir_V_d0;
input [1:0] vir_V_q0;
output [5:0] vir_V_address1;
output vir_V_ce1;
output vir_V_we1;
output [1:0] vir_V_d1;
input [1:0] vir_V_q1;
output [5:0] hir_V_address0;
output hir_V_ce0;
output hir_V_we0;
output [1:0] hir_V_d0;
input [1:0] hir_V_q0;
output [5:0] hir_V_address1;
output hir_V_ce1;
output hir_V_we1;
output [1:0] hir_V_d1;
input [1:0] hir_V_q1;
output [5:0] cir_V_address0;
output cir_V_ce0;
output cir_V_we0;
output [2:0] cir_V_d0;
input [2:0] cir_V_q0;
output [5:0] cir_V_address1;
output cir_V_ce1;
output cir_V_we1;
output [2:0] cir_V_d1;
input [2:0] cir_V_q1;
output [3:0] sir_V_address0;
output sir_V_ce0;
output sir_V_we0;
output [3:0] sir_V_d0;
input [3:0] sir_V_q0;
output [3:0] sir_V_address1;
output sir_V_ce1;
output sir_V_we1;
output [3:0] sir_V_d1;
input [3:0] sir_V_q1;
output [11:0] bt_phi_0_V;
output bt_phi_0_V_ap_vld;
output [11:0] bt_phi_1_V;
output bt_phi_1_V_ap_vld;
output [11:0] bt_phi_2_V;
output bt_phi_2_V_ap_vld;
output [6:0] bt_theta_0_V;
output bt_theta_0_V_ap_vld;
output [6:0] bt_theta_1_V;
output bt_theta_1_V_ap_vld;
output [6:0] bt_theta_2_V;
output bt_theta_2_V_ap_vld;
output [3:0] bt_cpattern_0_0_V;
output bt_cpattern_0_0_V_ap_vld;
output [3:0] bt_cpattern_0_1_V;
output bt_cpattern_0_1_V_ap_vld;
output [3:0] bt_cpattern_0_2_V;
output bt_cpattern_0_2_V_ap_vld;
output [3:0] bt_cpattern_0_3_V;
output bt_cpattern_0_3_V_ap_vld;
output [3:0] bt_cpattern_1_0_V;
output bt_cpattern_1_0_V_ap_vld;
output [3:0] bt_cpattern_1_1_V;
output bt_cpattern_1_1_V_ap_vld;
output [3:0] bt_cpattern_1_2_V;
output bt_cpattern_1_2_V_ap_vld;
output [3:0] bt_cpattern_1_3_V;
output bt_cpattern_1_3_V_ap_vld;
output [3:0] bt_cpattern_2_0_V;
output bt_cpattern_2_0_V_ap_vld;
output [3:0] bt_cpattern_2_1_V;
output bt_cpattern_2_1_V_ap_vld;
output [3:0] bt_cpattern_2_2_V;
output bt_cpattern_2_2_V_ap_vld;
output [3:0] bt_cpattern_2_3_V;
output bt_cpattern_2_3_V_ap_vld;
output [11:0] bt_delta_ph_0_0_V;
output bt_delta_ph_0_0_V_ap_vld;
output [11:0] bt_delta_ph_0_1_V;
output bt_delta_ph_0_1_V_ap_vld;
output [11:0] bt_delta_ph_0_2_V;
output bt_delta_ph_0_2_V_ap_vld;
output [11:0] bt_delta_ph_0_3_V;
output bt_delta_ph_0_3_V_ap_vld;
output [11:0] bt_delta_ph_0_4_V;
output bt_delta_ph_0_4_V_ap_vld;
output [11:0] bt_delta_ph_0_5_V;
output bt_delta_ph_0_5_V_ap_vld;
output [11:0] bt_delta_ph_1_0_V;
output bt_delta_ph_1_0_V_ap_vld;
output [11:0] bt_delta_ph_1_1_V;
output bt_delta_ph_1_1_V_ap_vld;
output [11:0] bt_delta_ph_1_2_V;
output bt_delta_ph_1_2_V_ap_vld;
output [11:0] bt_delta_ph_1_3_V;
output bt_delta_ph_1_3_V_ap_vld;
output [11:0] bt_delta_ph_1_4_V;
output bt_delta_ph_1_4_V_ap_vld;
output [11:0] bt_delta_ph_1_5_V;
output bt_delta_ph_1_5_V_ap_vld;
output [11:0] bt_delta_ph_2_0_V;
output bt_delta_ph_2_0_V_ap_vld;
output [11:0] bt_delta_ph_2_1_V;
output bt_delta_ph_2_1_V_ap_vld;
output [11:0] bt_delta_ph_2_2_V;
output bt_delta_ph_2_2_V_ap_vld;
output [11:0] bt_delta_ph_2_3_V;
output bt_delta_ph_2_3_V_ap_vld;
output [11:0] bt_delta_ph_2_4_V;
output bt_delta_ph_2_4_V_ap_vld;
output [11:0] bt_delta_ph_2_5_V;
output bt_delta_ph_2_5_V_ap_vld;
output [6:0] bt_delta_th_0_0_V;
output bt_delta_th_0_0_V_ap_vld;
output [6:0] bt_delta_th_0_1_V;
output bt_delta_th_0_1_V_ap_vld;
output [6:0] bt_delta_th_0_2_V;
output bt_delta_th_0_2_V_ap_vld;
output [6:0] bt_delta_th_0_3_V;
output bt_delta_th_0_3_V_ap_vld;
output [6:0] bt_delta_th_0_4_V;
output bt_delta_th_0_4_V_ap_vld;
output [6:0] bt_delta_th_0_5_V;
output bt_delta_th_0_5_V_ap_vld;
output [6:0] bt_delta_th_1_0_V;
output bt_delta_th_1_0_V_ap_vld;
output [6:0] bt_delta_th_1_1_V;
output bt_delta_th_1_1_V_ap_vld;
output [6:0] bt_delta_th_1_2_V;
output bt_delta_th_1_2_V_ap_vld;
output [6:0] bt_delta_th_1_3_V;
output bt_delta_th_1_3_V_ap_vld;
output [6:0] bt_delta_th_1_4_V;
output bt_delta_th_1_4_V_ap_vld;
output [6:0] bt_delta_th_1_5_V;
output bt_delta_th_1_5_V_ap_vld;
output [6:0] bt_delta_th_2_0_V;
output bt_delta_th_2_0_V_ap_vld;
output [6:0] bt_delta_th_2_1_V;
output bt_delta_th_2_1_V_ap_vld;
output [6:0] bt_delta_th_2_2_V;
output bt_delta_th_2_2_V_ap_vld;
output [6:0] bt_delta_th_2_3_V;
output bt_delta_th_2_3_V_ap_vld;
output [6:0] bt_delta_th_2_4_V;
output bt_delta_th_2_4_V_ap_vld;
output [6:0] bt_delta_th_2_5_V;
output bt_delta_th_2_5_V_ap_vld;
output [5:0] bt_sign_ph_0_V;
output bt_sign_ph_0_V_ap_vld;
output [5:0] bt_sign_ph_1_V;
output bt_sign_ph_1_V_ap_vld;
output [5:0] bt_sign_ph_2_V;
output bt_sign_ph_2_V_ap_vld;
output [5:0] bt_sign_th_0_V;
output bt_sign_th_0_V_ap_vld;
output [5:0] bt_sign_th_1_V;
output bt_sign_th_1_V_ap_vld;
output [5:0] bt_sign_th_2_V;
output bt_sign_th_2_V_ap_vld;
output [6:0] bt_rank_0_V;
output bt_rank_0_V_ap_vld;
output [6:0] bt_rank_1_V;
output bt_rank_1_V_ap_vld;
output [6:0] bt_rank_2_V;
output bt_rank_2_V_ap_vld;
output [1:0] bt_vi_0_0_V;
output bt_vi_0_0_V_ap_vld;
output [1:0] bt_vi_0_1_V;
output bt_vi_0_1_V_ap_vld;
output [1:0] bt_vi_0_2_V;
output bt_vi_0_2_V_ap_vld;
output [1:0] bt_vi_0_3_V;
output bt_vi_0_3_V_ap_vld;
output [1:0] bt_vi_0_4_V;
output bt_vi_0_4_V_ap_vld;
output [1:0] bt_vi_1_0_V;
output bt_vi_1_0_V_ap_vld;
output [1:0] bt_vi_1_1_V;
output bt_vi_1_1_V_ap_vld;
output [1:0] bt_vi_1_2_V;
output bt_vi_1_2_V_ap_vld;
output [1:0] bt_vi_1_3_V;
output bt_vi_1_3_V_ap_vld;
output [1:0] bt_vi_1_4_V;
output bt_vi_1_4_V_ap_vld;
output [1:0] bt_vi_2_0_V;
output bt_vi_2_0_V_ap_vld;
output [1:0] bt_vi_2_1_V;
output bt_vi_2_1_V_ap_vld;
output [1:0] bt_vi_2_2_V;
output bt_vi_2_2_V_ap_vld;
output [1:0] bt_vi_2_3_V;
output bt_vi_2_3_V_ap_vld;
output [1:0] bt_vi_2_4_V;
output bt_vi_2_4_V_ap_vld;
output [1:0] bt_hi_0_0_V;
output bt_hi_0_0_V_ap_vld;
output [1:0] bt_hi_0_1_V;
output bt_hi_0_1_V_ap_vld;
output [1:0] bt_hi_0_2_V;
output bt_hi_0_2_V_ap_vld;
output [1:0] bt_hi_0_3_V;
output bt_hi_0_3_V_ap_vld;
output [1:0] bt_hi_0_4_V;
output bt_hi_0_4_V_ap_vld;
output [1:0] bt_hi_1_0_V;
output bt_hi_1_0_V_ap_vld;
output [1:0] bt_hi_1_1_V;
output bt_hi_1_1_V_ap_vld;
output [1:0] bt_hi_1_2_V;
output bt_hi_1_2_V_ap_vld;
output [1:0] bt_hi_1_3_V;
output bt_hi_1_3_V_ap_vld;
output [1:0] bt_hi_1_4_V;
output bt_hi_1_4_V_ap_vld;
output [1:0] bt_hi_2_0_V;
output bt_hi_2_0_V_ap_vld;
output [1:0] bt_hi_2_1_V;
output bt_hi_2_1_V_ap_vld;
output [1:0] bt_hi_2_2_V;
output bt_hi_2_2_V_ap_vld;
output [1:0] bt_hi_2_3_V;
output bt_hi_2_3_V_ap_vld;
output [1:0] bt_hi_2_4_V;
output bt_hi_2_4_V_ap_vld;
output [3:0] bt_ci_0_0_V;
output bt_ci_0_0_V_ap_vld;
output [3:0] bt_ci_0_1_V;
output bt_ci_0_1_V_ap_vld;
output [3:0] bt_ci_0_2_V;
output bt_ci_0_2_V_ap_vld;
output [3:0] bt_ci_0_3_V;
output bt_ci_0_3_V_ap_vld;
output [3:0] bt_ci_0_4_V;
output bt_ci_0_4_V_ap_vld;
output [3:0] bt_ci_1_0_V;
output bt_ci_1_0_V_ap_vld;
output [3:0] bt_ci_1_1_V;
output bt_ci_1_1_V_ap_vld;
output [3:0] bt_ci_1_2_V;
output bt_ci_1_2_V_ap_vld;
output [3:0] bt_ci_1_3_V;
output bt_ci_1_3_V_ap_vld;
output [3:0] bt_ci_1_4_V;
output bt_ci_1_4_V_ap_vld;
output [3:0] bt_ci_2_0_V;
output bt_ci_2_0_V_ap_vld;
output [3:0] bt_ci_2_1_V;
output bt_ci_2_1_V_ap_vld;
output [3:0] bt_ci_2_2_V;
output bt_ci_2_2_V_ap_vld;
output [3:0] bt_ci_2_3_V;
output bt_ci_2_3_V_ap_vld;
output [3:0] bt_ci_2_4_V;
output bt_ci_2_4_V_ap_vld;
output [4:0] bt_si_0_V;
output bt_si_0_V_ap_vld;
output [4:0] bt_si_1_V;
output bt_si_1_V_ap_vld;
output [4:0] bt_si_2_V;
output bt_si_2_V_ap_vld;
output [29:0] ptlut_addr_0_V;
output ptlut_addr_0_V_ap_vld;
output [29:0] ptlut_addr_1_V;
output ptlut_addr_1_V_ap_vld;
output [29:0] ptlut_addr_2_V;
output ptlut_addr_2_V_ap_vld;
output [31:0] ptlut_cs_0_V;
output ptlut_cs_0_V_ap_vld;
output [31:0] ptlut_cs_1_V;
output ptlut_cs_1_V_ap_vld;
output [31:0] ptlut_cs_2_V;
output ptlut_cs_2_V_ap_vld;
output [2:0] ptlut_addr_val_V;
output ptlut_addr_val_V_ap_vld;
output [7:0] gmt_phi_0_V;
output gmt_phi_0_V_ap_vld;
output [7:0] gmt_phi_1_V;
output gmt_phi_1_V_ap_vld;
output [7:0] gmt_phi_2_V;
output gmt_phi_2_V_ap_vld;
output [8:0] gmt_eta_0_V;
output gmt_eta_0_V_ap_vld;
output [8:0] gmt_eta_1_V;
output gmt_eta_1_V_ap_vld;
output [8:0] gmt_eta_2_V;
output gmt_eta_2_V_ap_vld;
output [3:0] gmt_qlt_0_V;
output gmt_qlt_0_V_ap_vld;
output [3:0] gmt_qlt_1_V;
output gmt_qlt_1_V_ap_vld;
output [3:0] gmt_qlt_2_V;
output gmt_qlt_2_V_ap_vld;
output [2:0] gmt_crg_V;
output gmt_crg_V_ap_vld;
input [0:0] endcap_V;
input [2:0] sector_V;
input [0:0] lat_test_V;
input [0:0] print_flag_V;
output ph_num_0_0_V_ap_lwr;
output ph_num_0_1_V_ap_lwr;
output ph_num_0_2_V_ap_lwr;
output ph_num_1_0_V_ap_lwr;
output ph_num_1_1_V_ap_lwr;
output ph_num_1_2_V_ap_lwr;
output ph_num_2_0_V_ap_lwr;
output ph_num_2_1_V_ap_lwr;
output ph_num_2_2_V_ap_lwr;
output ph_num_3_0_V_ap_lwr;
output ph_num_3_1_V_ap_lwr;
output ph_num_3_2_V_ap_lwr;
output ph_q_0_0_V_ap_lwr;
output ph_q_0_1_V_ap_lwr;
output ph_q_0_2_V_ap_lwr;
output ph_q_1_0_V_ap_lwr;
output ph_q_1_1_V_ap_lwr;
output ph_q_1_2_V_ap_lwr;
output ph_q_2_0_V_ap_lwr;
output ph_q_2_1_V_ap_lwr;
output ph_q_2_2_V_ap_lwr;
output ph_q_3_0_V_ap_lwr;
output ph_q_3_1_V_ap_lwr;
output ph_q_3_2_V_ap_lwr;
reg ph_zone_0_0_V_ap_vld;
reg ph_zone_0_1_V_ap_vld;
reg ph_zone_0_2_V_ap_vld;
reg ph_zone_0_3_V_ap_vld;
reg ph_zone_0_4_V_ap_vld;
reg ph_zone_1_0_V_ap_vld;
reg ph_zone_1_1_V_ap_vld;
reg ph_zone_1_2_V_ap_vld;
reg ph_zone_1_3_V_ap_vld;
reg ph_zone_1_4_V_ap_vld;
reg ph_zone_2_0_V_ap_vld;
reg ph_zone_2_1_V_ap_vld;
reg ph_zone_2_2_V_ap_vld;
reg ph_zone_2_3_V_ap_vld;
reg ph_zone_2_4_V_ap_vld;
reg ph_zone_3_0_V_ap_vld;
reg ph_zone_3_1_V_ap_vld;
reg ph_zone_3_2_V_ap_vld;
reg ph_zone_3_3_V_ap_vld;
reg ph_zone_3_4_V_ap_vld;
reg ph_ext_0_0_V_ap_vld;
reg ph_ext_0_1_V_ap_vld;
reg ph_ext_0_2_V_ap_vld;
reg ph_ext_0_3_V_ap_vld;
reg ph_ext_0_4_V_ap_vld;
reg ph_ext_1_0_V_ap_vld;
reg ph_ext_1_1_V_ap_vld;
reg ph_ext_1_2_V_ap_vld;
reg ph_ext_1_3_V_ap_vld;
reg ph_ext_1_4_V_ap_vld;
reg ph_ext_2_0_V_ap_vld;
reg ph_ext_2_1_V_ap_vld;
reg ph_ext_2_2_V_ap_vld;
reg ph_ext_2_3_V_ap_vld;
reg ph_ext_2_4_V_ap_vld;
reg ph_ext_3_0_V_ap_vld;
reg ph_ext_3_1_V_ap_vld;
reg ph_ext_3_2_V_ap_vld;
reg ph_ext_3_3_V_ap_vld;
reg ph_ext_3_4_V_ap_vld;
reg ph_num_0_0_V_ap_vld;
reg ph_num_0_1_V_ap_vld;
reg ph_num_0_2_V_ap_vld;
reg ph_num_1_0_V_ap_vld;
reg ph_num_1_1_V_ap_vld;
reg ph_num_1_2_V_ap_vld;
reg ph_num_2_0_V_ap_vld;
reg ph_num_2_1_V_ap_vld;
reg ph_num_2_2_V_ap_vld;
reg ph_num_3_0_V_ap_vld;
reg ph_num_3_1_V_ap_vld;
reg ph_num_3_2_V_ap_vld;
reg ph_q_0_0_V_ap_vld;
reg ph_q_0_1_V_ap_vld;
reg ph_q_0_2_V_ap_vld;
reg ph_q_1_0_V_ap_vld;
reg ph_q_1_1_V_ap_vld;
reg ph_q_1_2_V_ap_vld;
reg ph_q_2_0_V_ap_vld;
reg ph_q_2_1_V_ap_vld;
reg ph_q_2_2_V_ap_vld;
reg ph_q_3_0_V_ap_vld;
reg ph_q_3_1_V_ap_vld;
reg ph_q_3_2_V_ap_vld;
reg bt_phi_0_V_ap_vld;
reg bt_phi_1_V_ap_vld;
reg bt_phi_2_V_ap_vld;
reg bt_theta_0_V_ap_vld;
reg bt_theta_1_V_ap_vld;
reg bt_theta_2_V_ap_vld;
reg bt_cpattern_0_0_V_ap_vld;
reg bt_cpattern_0_1_V_ap_vld;
reg bt_cpattern_0_2_V_ap_vld;
reg bt_cpattern_0_3_V_ap_vld;
reg bt_cpattern_1_0_V_ap_vld;
reg bt_cpattern_1_1_V_ap_vld;
reg bt_cpattern_1_2_V_ap_vld;
reg bt_cpattern_1_3_V_ap_vld;
reg bt_cpattern_2_0_V_ap_vld;
reg bt_cpattern_2_1_V_ap_vld;
reg bt_cpattern_2_2_V_ap_vld;
reg bt_cpattern_2_3_V_ap_vld;
reg bt_delta_ph_0_0_V_ap_vld;
reg bt_delta_ph_0_1_V_ap_vld;
reg bt_delta_ph_0_2_V_ap_vld;
reg bt_delta_ph_0_3_V_ap_vld;
reg bt_delta_ph_0_4_V_ap_vld;
reg bt_delta_ph_0_5_V_ap_vld;
reg bt_delta_ph_1_0_V_ap_vld;
reg bt_delta_ph_1_1_V_ap_vld;
reg bt_delta_ph_1_2_V_ap_vld;
reg bt_delta_ph_1_3_V_ap_vld;
reg bt_delta_ph_1_4_V_ap_vld;
reg bt_delta_ph_1_5_V_ap_vld;
reg bt_delta_ph_2_0_V_ap_vld;
reg bt_delta_ph_2_1_V_ap_vld;
reg bt_delta_ph_2_2_V_ap_vld;
reg bt_delta_ph_2_3_V_ap_vld;
reg bt_delta_ph_2_4_V_ap_vld;
reg bt_delta_ph_2_5_V_ap_vld;
reg bt_delta_th_0_0_V_ap_vld;
reg bt_delta_th_0_1_V_ap_vld;
reg bt_delta_th_0_2_V_ap_vld;
reg bt_delta_th_0_3_V_ap_vld;
reg bt_delta_th_0_4_V_ap_vld;
reg bt_delta_th_0_5_V_ap_vld;
reg bt_delta_th_1_0_V_ap_vld;
reg bt_delta_th_1_1_V_ap_vld;
reg bt_delta_th_1_2_V_ap_vld;
reg bt_delta_th_1_3_V_ap_vld;
reg bt_delta_th_1_4_V_ap_vld;
reg bt_delta_th_1_5_V_ap_vld;
reg bt_delta_th_2_0_V_ap_vld;
reg bt_delta_th_2_1_V_ap_vld;
reg bt_delta_th_2_2_V_ap_vld;
reg bt_delta_th_2_3_V_ap_vld;
reg bt_delta_th_2_4_V_ap_vld;
reg bt_delta_th_2_5_V_ap_vld;
reg bt_sign_ph_0_V_ap_vld;
reg bt_sign_ph_1_V_ap_vld;
reg bt_sign_ph_2_V_ap_vld;
reg bt_sign_th_0_V_ap_vld;
reg bt_sign_th_1_V_ap_vld;
reg bt_sign_th_2_V_ap_vld;
reg bt_rank_0_V_ap_vld;
reg bt_rank_1_V_ap_vld;
reg bt_rank_2_V_ap_vld;
reg bt_vi_0_0_V_ap_vld;
reg bt_vi_0_1_V_ap_vld;
reg bt_vi_0_2_V_ap_vld;
reg bt_vi_0_3_V_ap_vld;
reg bt_vi_0_4_V_ap_vld;
reg bt_vi_1_0_V_ap_vld;
reg bt_vi_1_1_V_ap_vld;
reg bt_vi_1_2_V_ap_vld;
reg bt_vi_1_3_V_ap_vld;
reg bt_vi_1_4_V_ap_vld;
reg bt_vi_2_0_V_ap_vld;
reg bt_vi_2_1_V_ap_vld;
reg bt_vi_2_2_V_ap_vld;
reg bt_vi_2_3_V_ap_vld;
reg bt_vi_2_4_V_ap_vld;
reg bt_hi_0_0_V_ap_vld;
reg bt_hi_0_1_V_ap_vld;
reg bt_hi_0_2_V_ap_vld;
reg bt_hi_0_3_V_ap_vld;
reg bt_hi_0_4_V_ap_vld;
reg bt_hi_1_0_V_ap_vld;
reg bt_hi_1_1_V_ap_vld;
reg bt_hi_1_2_V_ap_vld;
reg bt_hi_1_3_V_ap_vld;
reg bt_hi_1_4_V_ap_vld;
reg bt_hi_2_0_V_ap_vld;
reg bt_hi_2_1_V_ap_vld;
reg bt_hi_2_2_V_ap_vld;
reg bt_hi_2_3_V_ap_vld;
reg bt_hi_2_4_V_ap_vld;
reg bt_ci_0_0_V_ap_vld;
reg bt_ci_0_1_V_ap_vld;
reg bt_ci_0_2_V_ap_vld;
reg bt_ci_0_3_V_ap_vld;
reg bt_ci_0_4_V_ap_vld;
reg bt_ci_1_0_V_ap_vld;
reg bt_ci_1_1_V_ap_vld;
reg bt_ci_1_2_V_ap_vld;
reg bt_ci_1_3_V_ap_vld;
reg bt_ci_1_4_V_ap_vld;
reg bt_ci_2_0_V_ap_vld;
reg bt_ci_2_1_V_ap_vld;
reg bt_ci_2_2_V_ap_vld;
reg bt_ci_2_3_V_ap_vld;
reg bt_ci_2_4_V_ap_vld;
reg bt_si_0_V_ap_vld;
reg bt_si_1_V_ap_vld;
reg bt_si_2_V_ap_vld;
reg ptlut_addr_0_V_ap_vld;
reg ptlut_addr_1_V_ap_vld;
reg ptlut_addr_2_V_ap_vld;
reg ptlut_cs_0_V_ap_vld;
reg ptlut_cs_1_V_ap_vld;
reg ptlut_cs_2_V_ap_vld;
reg ptlut_addr_val_V_ap_vld;
reg gmt_phi_0_V_ap_vld;
reg gmt_phi_1_V_ap_vld;
reg gmt_phi_2_V_ap_vld;
reg gmt_eta_0_V_ap_vld;
reg gmt_eta_1_V_ap_vld;
reg gmt_eta_2_V_ap_vld;
reg gmt_qlt_0_V_ap_vld;
reg gmt_qlt_1_V_ap_vld;
reg gmt_qlt_2_V_ap_vld;
reg gmt_crg_V_ap_vld;
reg ph_num_0_0_V_ap_lwr;
reg ph_num_0_1_V_ap_lwr;
reg ph_num_0_2_V_ap_lwr;
reg ph_num_1_0_V_ap_lwr;
reg ph_num_1_1_V_ap_lwr;
reg ph_num_1_2_V_ap_lwr;
reg ph_num_2_0_V_ap_lwr;
reg ph_num_2_1_V_ap_lwr;
reg ph_num_2_2_V_ap_lwr;
reg ph_num_3_0_V_ap_lwr;
reg ph_num_3_1_V_ap_lwr;
reg ph_num_3_2_V_ap_lwr;
reg ph_q_0_0_V_ap_lwr;
reg ph_q_0_1_V_ap_lwr;
reg ph_q_0_2_V_ap_lwr;
reg ph_q_1_0_V_ap_lwr;
reg ph_q_1_1_V_ap_lwr;
reg ph_q_1_2_V_ap_lwr;
reg ph_q_2_0_V_ap_lwr;
reg ph_q_2_1_V_ap_lwr;
reg ph_q_2_2_V_ap_lwr;
reg ph_q_3_0_V_ap_lwr;
reg ph_q_3_1_V_ap_lwr;
reg ph_q_3_2_V_ap_lwr;
reg ap_reg_ppiten_pp0_it4;
reg ap_reg_ppiten_pp0_it1;
reg ap_reg_ppiten_pp0_it2;
reg ap_reg_ppiten_pp0_it3;
reg ap_reg_ppiten_pp0_it5;
reg ap_reg_ppiten_pp0_it6;
reg ap_reg_ppiten_pp0_it7;
reg ap_reg_ppiten_pp0_it8;
reg ap_reg_ppiten_pp0_it9;
reg ap_reg_ppiten_pp0_it10;
(* fsm_encoding = "none" *) reg [0:0] ap_CS_fsm;
reg ap_sig_cseq_ST_pp0_stg0_fsm_0;
reg ap_sig_1237;
reg [2:0] phzvl_t_0_3_V_reg_61488;
reg [2:0] phzvl_t_0_4_V_reg_61493;
reg [2:0] phzvl_t_0_5_V_reg_61498;
reg [2:0] phzvl_t_1_3_V_reg_61503;
reg [2:0] phzvl_t_1_4_V_reg_61508;
reg [2:0] phzvl_t_1_5_V_reg_61513;
reg [2:0] phzvl_t_2_0_V_reg_61518;
reg [2:0] phzvl_t_2_1_V_reg_61523;
reg [2:0] phzvl_t_2_2_V_reg_61528;
reg [2:0] phzvl_t_2_3_V_reg_61533;
reg [2:0] phzvl_t_2_4_V_reg_61538;
reg [2:0] phzvl_t_2_5_V_reg_61543;
reg [2:0] phzvl_t_2_6_V_reg_61548;
reg [2:0] phzvl_t_2_7_V_reg_61553;
reg [2:0] phzvl_t_2_8_V_reg_61558;
reg [2:0] phzvl_t_3_0_V_reg_61563;
reg [2:0] phzvl_t_3_1_V_reg_61568;
reg [2:0] phzvl_t_3_2_V_reg_61573;
reg [2:0] phzvl_t_3_3_V_reg_61578;
reg [2:0] phzvl_t_3_4_V_reg_61583;
reg [2:0] phzvl_t_3_5_V_reg_61588;
reg [2:0] phzvl_t_3_6_V_reg_61593;
reg [2:0] phzvl_t_3_7_V_reg_61598;
reg [2:0] phzvl_t_3_8_V_reg_61603;
reg [2:0] phzvl_t_4_0_V_reg_61608;
reg [2:0] phzvl_t_4_1_V_reg_61613;
reg [2:0] phzvl_t_4_2_V_reg_61618;
reg [2:0] phzvl_t_4_3_V_reg_61623;
reg [2:0] phzvl_t_4_4_V_reg_61628;
reg [2:0] phzvl_t_4_5_V_reg_61633;
reg [2:0] phzvl_t_4_6_V_reg_61638;
reg [2:0] phzvl_t_4_7_V_reg_61643;
reg [2:0] phzvl_t_4_8_V_reg_61648;
reg [43:0] ph_hit_t_0_3_V_reg_61653;
reg [43:0] ph_hit_t_0_4_V_reg_61658;
reg [43:0] ph_hit_t_0_5_V_reg_61663;
reg [43:0] ph_hit_t_0_6_V_reg_61668;
reg [43:0] ph_hit_t_0_7_V_reg_61673;
reg [43:0] ph_hit_t_0_8_V_reg_61678;
reg [43:0] ph_hit_t_1_3_V_reg_61683;
reg [43:0] ph_hit_t_1_4_V_reg_61688;
reg [43:0] ph_hit_t_1_5_V_reg_61693;
reg [43:0] ph_hit_t_1_6_V_reg_61698;
reg [43:0] ph_hit_t_1_7_V_reg_61703;
reg [43:0] ph_hit_t_1_8_V_reg_61708;
reg [43:0] ph_hit_t_2_0_V_reg_61713;
reg [43:0] ph_hit_t_2_1_V_reg_61718;
reg [43:0] ph_hit_t_2_2_V_reg_61723;
reg [43:0] ph_hit_t_2_3_V_reg_61728;
reg [43:0] ph_hit_t_2_4_V_reg_61733;
reg [43:0] ph_hit_t_2_5_V_reg_61738;
reg [43:0] ph_hit_t_2_6_V_reg_61743;
reg [43:0] ph_hit_t_2_7_V_reg_61748;
reg [43:0] ph_hit_t_2_8_V_reg_61753;
reg [43:0] ph_hit_t_3_0_V_reg_61758;
reg [43:0] ph_hit_t_3_1_V_reg_61763;
reg [43:0] ph_hit_t_3_2_V_reg_61768;
reg [43:0] ph_hit_t_3_3_V_reg_61773;
reg [43:0] ph_hit_t_3_4_V_reg_61778;
reg [43:0] ph_hit_t_3_5_V_reg_61783;
reg [43:0] ph_hit_t_3_6_V_reg_61788;
reg [43:0] ph_hit_t_3_7_V_reg_61793;
reg [43:0] ph_hit_t_3_8_V_reg_61798;
reg [43:0] ph_hit_t_4_0_V_reg_61803;
reg [43:0] ph_hit_t_4_1_V_reg_61808;
reg [43:0] ph_hit_t_4_2_V_reg_61813;
reg [43:0] ph_hit_t_4_3_V_reg_61818;
reg [43:0] ph_hit_t_4_4_V_reg_61823;
reg [43:0] ph_hit_t_4_5_V_reg_61828;
reg [43:0] ph_hit_t_4_6_V_reg_61833;
reg [43:0] ph_hit_t_4_7_V_reg_61838;
reg [43:0] ph_hit_t_4_8_V_reg_61843;
reg [2:0] phzvl_t_0_0_V_reg_61848;
reg [2:0] phzvl_t_0_1_V_reg_61853;
reg [2:0] phzvl_t_0_2_V_reg_61858;
reg [2:0] phzvl_t_1_0_V_reg_61863;
reg [2:0] phzvl_t_1_1_V_reg_61868;
reg [2:0] phzvl_t_1_2_V_reg_61873;
reg [43:0] ph_hit_t_0_0_V_reg_61878;
reg [43:0] ph_hit_t_0_1_V_reg_61883;
reg [43:0] ph_hit_t_0_2_V_reg_61888;
reg [43:0] ph_hit_t_1_0_V_reg_61893;
reg [43:0] ph_hit_t_1_1_V_reg_61898;
reg [43:0] ph_hit_t_1_2_V_reg_61903;
reg [121:0] ph_zone_t_0_1_V_1_reg_61908;
reg [121:0] ph_zone_t_0_2_V_1_reg_61913;
reg [121:0] ph_zone_t_0_3_V_1_reg_61918;
reg [121:0] ph_zone_t_0_4_V_1_reg_61923;
reg [121:0] ph_zone_t_1_1_V_1_reg_61928;
reg [121:0] ph_zone_t_1_2_V_1_reg_61933;
reg [121:0] ph_zone_t_1_3_V_1_reg_61938;
reg [121:0] ph_zone_t_1_4_V_1_reg_61943;
reg [121:0] ph_zone_t_2_1_V_1_reg_61948;
reg [121:0] ph_zone_t_2_2_V_1_reg_61953;
reg [121:0] ph_zone_t_2_3_V_1_reg_61958;
reg [121:0] ph_zone_t_2_4_V_1_reg_61963;
reg [121:0] ph_zone_t_3_1_V_1_reg_61968;
reg [121:0] ph_zone_t_3_2_V_1_reg_61973;
reg [121:0] ph_zone_t_3_3_V_1_reg_61978;
reg [11:0] phd_1_2_1_1_V_reg_61983;
reg [11:0] ap_reg_ppstg_phd_1_2_1_1_V_reg_61983_pp0_iter4;
reg [11:0] phd_1_3_1_1_V_reg_61988;
reg [11:0] ap_reg_ppstg_phd_1_3_1_1_V_reg_61988_pp0_iter4;
reg [11:0] phd_1_4_1_1_V_reg_61993;
reg [11:0] ap_reg_ppstg_phd_1_4_1_1_V_reg_61993_pp0_iter4;
reg [11:0] phd_2_0_1_1_V_reg_61998;
reg [11:0] ap_reg_ppstg_phd_2_0_1_1_V_reg_61998_pp0_iter4;
reg [11:0] phd_2_0_4_1_V_reg_62003;
reg [11:0] ap_reg_ppstg_phd_2_0_4_1_V_reg_62003_pp0_iter4;
reg [11:0] phd_2_0_7_1_V_reg_62008;
reg [11:0] ap_reg_ppstg_phd_2_0_7_1_V_reg_62008_pp0_iter4;
reg [11:0] phd_2_2_4_1_V_reg_62013;
reg [11:0] ap_reg_ppstg_phd_2_2_4_1_V_reg_62013_pp0_iter4;
reg [11:0] phd_2_3_4_1_V_reg_62018;
reg [11:0] ap_reg_ppstg_phd_2_3_4_1_V_reg_62018_pp0_iter4;
reg [11:0] phd_2_4_4_1_V_reg_62023;
reg [11:0] ap_reg_ppstg_phd_2_4_4_1_V_reg_62023_pp0_iter4;
reg [6:0] th11d_2_0_1_0_V_reg_62028;
reg [6:0] ap_reg_ppstg_th11d_2_0_1_0_V_reg_62028_pp0_iter4;
reg [6:0] th11d_2_0_1_1_V_reg_62033;
reg [6:0] ap_reg_ppstg_th11d_2_0_1_1_V_reg_62033_pp0_iter4;
reg [6:0] th11d_2_0_1_2_V_reg_62038;
reg [6:0] ap_reg_ppstg_th11d_2_0_1_2_V_reg_62038_pp0_iter4;
reg [6:0] th11d_2_0_1_3_V_reg_62043;
reg [6:0] ap_reg_ppstg_th11d_2_0_1_3_V_reg_62043_pp0_iter4;
reg [6:0] thd_1_2_1_0_V_reg_62048;
reg [6:0] ap_reg_ppstg_thd_1_2_1_0_V_reg_62048_pp0_iter4;
reg [6:0] thd_1_2_1_1_V_reg_62053;
reg [6:0] ap_reg_ppstg_thd_1_2_1_1_V_reg_62053_pp0_iter4;
reg [6:0] thd_1_3_1_0_V_reg_62058;
reg [6:0] ap_reg_ppstg_thd_1_3_1_0_V_reg_62058_pp0_iter4;
reg [6:0] thd_1_3_1_1_V_reg_62063;
reg [6:0] ap_reg_ppstg_thd_1_3_1_1_V_reg_62063_pp0_iter4;
reg [6:0] thd_1_4_1_0_V_reg_62068;
reg [6:0] ap_reg_ppstg_thd_1_4_1_0_V_reg_62068_pp0_iter4;
reg [6:0] thd_1_4_1_1_V_reg_62073;
reg [6:0] ap_reg_ppstg_thd_1_4_1_1_V_reg_62073_pp0_iter4;
reg [6:0] thd_2_0_4_0_V_reg_62078;
reg [6:0] ap_reg_ppstg_thd_2_0_4_0_V_reg_62078_pp0_iter4;
reg [6:0] thd_2_0_4_1_V_reg_62083;
reg [6:0] ap_reg_ppstg_thd_2_0_4_1_V_reg_62083_pp0_iter4;
reg [6:0] thd_2_0_7_0_V_reg_62088;
reg [6:0] ap_reg_ppstg_thd_2_0_7_0_V_reg_62088_pp0_iter4;
reg [6:0] thd_2_0_7_1_V_reg_62093;
reg [6:0] ap_reg_ppstg_thd_2_0_7_1_V_reg_62093_pp0_iter4;
reg [6:0] thd_2_2_4_0_V_reg_62098;
reg [6:0] ap_reg_ppstg_thd_2_2_4_0_V_reg_62098_pp0_iter4;
reg [6:0] thd_2_2_4_1_V_reg_62103;
reg [6:0] ap_reg_ppstg_thd_2_2_4_1_V_reg_62103_pp0_iter4;
reg [6:0] thd_2_3_4_0_V_reg_62108;
reg [6:0] ap_reg_ppstg_thd_2_3_4_0_V_reg_62108_pp0_iter4;
reg [6:0] thd_2_3_4_1_V_reg_62113;
reg [6:0] ap_reg_ppstg_thd_2_3_4_1_V_reg_62113_pp0_iter4;
reg [6:0] thd_2_4_4_0_V_reg_62118;
reg [6:0] ap_reg_ppstg_thd_2_4_4_0_V_reg_62118_pp0_iter4;
reg [6:0] thd_2_4_4_1_V_reg_62123;
reg [6:0] ap_reg_ppstg_thd_2_4_4_1_V_reg_62123_pp0_iter4;
reg [3:0] cpatd_1_2_1_1_V_reg_62128;
reg [3:0] ap_reg_ppstg_cpatd_1_2_1_1_V_reg_62128_pp0_iter4;
reg [3:0] cpatd_1_3_1_1_V_reg_62133;
reg [3:0] ap_reg_ppstg_cpatd_1_3_1_1_V_reg_62133_pp0_iter4;
reg [3:0] cpatd_1_4_1_1_V_reg_62138;
reg [3:0] ap_reg_ppstg_cpatd_1_4_1_1_V_reg_62138_pp0_iter4;
reg [3:0] cpatd_2_0_1_1_V_reg_62143;
reg [3:0] ap_reg_ppstg_cpatd_2_0_1_1_V_reg_62143_pp0_iter4;
reg [3:0] cpatd_2_0_4_1_V_reg_62148;
reg [3:0] ap_reg_ppstg_cpatd_2_0_4_1_V_reg_62148_pp0_iter4;
reg [3:0] cpatd_2_0_7_1_V_reg_62153;
reg [3:0] ap_reg_ppstg_cpatd_2_0_7_1_V_reg_62153_pp0_iter4;
reg [3:0] cpatd_2_2_4_1_V_reg_62158;
reg [3:0] ap_reg_ppstg_cpatd_2_2_4_1_V_reg_62158_pp0_iter4;
reg [3:0] cpatd_2_3_4_1_V_reg_62163;
reg [3:0] ap_reg_ppstg_cpatd_2_3_4_1_V_reg_62163_pp0_iter4;
reg [3:0] cpatd_2_4_4_1_V_reg_62168;
reg [3:0] ap_reg_ppstg_cpatd_2_4_4_1_V_reg_62168_pp0_iter4;
reg [3:0] patt_ph_si_0_0_V_reg_62173;
reg [3:0] ap_reg_ppstg_patt_ph_si_0_0_V_reg_62173_pp0_iter6;
reg [3:0] patt_ph_si_0_1_V_reg_62178;
reg [3:0] ap_reg_ppstg_patt_ph_si_0_1_V_reg_62178_pp0_iter6;
reg [3:0] patt_ph_si_0_2_V_reg_62183;
reg [3:0] ap_reg_ppstg_patt_ph_si_0_2_V_reg_62183_pp0_iter6;
reg [3:0] patt_ph_si_1_0_V_reg_62188;
reg [3:0] ap_reg_ppstg_patt_ph_si_1_0_V_reg_62188_pp0_iter6;
reg [3:0] patt_ph_si_1_1_V_reg_62193;
reg [3:0] ap_reg_ppstg_patt_ph_si_1_1_V_reg_62193_pp0_iter6;
reg [3:0] patt_ph_si_1_2_V_reg_62198;
reg [3:0] ap_reg_ppstg_patt_ph_si_1_2_V_reg_62198_pp0_iter6;
reg [3:0] patt_ph_si_2_0_V_reg_62203;
reg [3:0] ap_reg_ppstg_patt_ph_si_2_0_V_reg_62203_pp0_iter6;
reg [3:0] patt_ph_si_2_1_V_reg_62208;
reg [3:0] ap_reg_ppstg_patt_ph_si_2_1_V_reg_62208_pp0_iter6;
reg [3:0] patt_ph_si_2_2_V_reg_62213;
reg [3:0] ap_reg_ppstg_patt_ph_si_2_2_V_reg_62213_pp0_iter6;
reg [3:0] patt_ph_si_3_0_V_reg_62218;
reg [3:0] ap_reg_ppstg_patt_ph_si_3_0_V_reg_62218_pp0_iter6;
reg [3:0] patt_ph_si_3_1_V_reg_62223;
reg [3:0] ap_reg_ppstg_patt_ph_si_3_1_V_reg_62223_pp0_iter6;
reg [3:0] patt_ph_si_3_2_V_reg_62228;
reg [3:0] ap_reg_ppstg_patt_ph_si_3_2_V_reg_62228_pp0_iter6;
reg [11:0] ph_match_t_0_0_0_V_reg_62233;
reg [11:0] ph_match_t_0_0_1_V_reg_62238;
reg [11:0] ph_match_t_0_0_2_V_reg_62243;
reg [11:0] ph_match_t_0_0_3_V_reg_62248;
reg [11:0] ph_match_t_0_1_0_V_reg_62253;
reg [11:0] ph_match_t_0_1_1_V_reg_62258;
reg [11:0] ph_match_t_0_1_2_V_reg_62263;
reg [11:0] ph_match_t_0_1_3_V_reg_62268;
reg [11:0] ph_match_t_0_2_0_V_reg_62273;
reg [11:0] ph_match_t_0_2_1_V_reg_62278;
reg [11:0] ph_match_t_0_2_2_V_reg_62283;
reg [11:0] ph_match_t_0_2_3_V_reg_62288;
reg [11:0] ph_match_t_1_0_0_V_reg_62293;
reg [11:0] ph_match_t_1_0_1_V_reg_62298;
reg [11:0] ph_match_t_1_0_2_V_reg_62303;
reg [11:0] ph_match_t_1_0_3_V_reg_62308;
reg [11:0] ph_match_t_1_1_0_V_reg_62313;
reg [11:0] ph_match_t_1_1_1_V_reg_62318;
reg [11:0] ph_match_t_1_1_2_V_reg_62323;
reg [11:0] ph_match_t_1_1_3_V_reg_62328;
reg [11:0] ph_match_t_1_2_0_V_reg_62333;
reg [11:0] ph_match_t_1_2_1_V_reg_62338;
reg [11:0] ph_match_t_1_2_2_V_reg_62343;
reg [11:0] ph_match_t_1_2_3_V_reg_62348;
reg [11:0] ph_match_t_2_0_0_V_reg_62353;
reg [11:0] ph_match_t_2_0_1_V_reg_62358;
reg [11:0] ph_match_t_2_0_2_V_reg_62363;
reg [11:0] ph_match_t_2_0_3_V_reg_62368;
reg [11:0] ph_match_t_2_1_0_V_reg_62373;
reg [11:0] ph_match_t_2_1_1_V_reg_62378;
reg [11:0] ph_match_t_2_1_2_V_reg_62383;
reg [11:0] ph_match_t_2_1_3_V_reg_62388;
reg [11:0] ph_match_t_2_2_0_V_reg_62393;
reg [11:0] ph_match_t_2_2_1_V_reg_62398;
reg [11:0] ph_match_t_2_2_2_V_reg_62403;
reg [11:0] ph_match_t_2_2_3_V_reg_62408;
reg [11:0] ph_match_t_3_0_0_V_reg_62413;
reg [11:0] ph_match_t_3_0_1_V_reg_62418;
reg [11:0] ph_match_t_3_0_2_V_reg_62423;
reg [11:0] ph_match_t_3_0_3_V_reg_62428;
reg [11:0] ph_match_t_3_1_0_V_reg_62433;
reg [11:0] ph_match_t_3_1_1_V_reg_62438;
reg [11:0] ph_match_t_3_1_2_V_reg_62443;
reg [11:0] ph_match_t_3_1_3_V_reg_62448;
reg [11:0] ph_match_t_3_2_0_V_reg_62453;
reg [11:0] ph_match_t_3_2_1_V_reg_62458;
reg [11:0] ph_match_t_3_2_2_V_reg_62463;
reg [11:0] ph_match_t_3_2_3_V_reg_62468;
reg [3:0] cpat_match_t_0_0_0_V_reg_62473;
reg [3:0] cpat_match_t_0_0_1_V_reg_62478;
reg [3:0] cpat_match_t_0_0_2_V_reg_62483;
reg [3:0] cpat_match_t_0_0_3_V_reg_62488;
reg [3:0] cpat_match_t_0_1_0_V_reg_62493;
reg [3:0] cpat_match_t_0_1_1_V_reg_62498;
reg [3:0] cpat_match_t_0_1_2_V_reg_62503;
reg [3:0] cpat_match_t_0_1_3_V_reg_62508;
reg [3:0] cpat_match_t_0_2_0_V_reg_62513;
reg [3:0] cpat_match_t_0_2_1_V_reg_62518;
reg [3:0] cpat_match_t_0_2_2_V_reg_62523;
reg [3:0] cpat_match_t_0_2_3_V_reg_62528;
reg [3:0] cpat_match_t_1_0_0_V_reg_62533;
reg [3:0] cpat_match_t_1_0_1_V_reg_62538;
reg [3:0] cpat_match_t_1_0_2_V_reg_62543;
reg [3:0] cpat_match_t_1_0_3_V_reg_62548;
reg [3:0] cpat_match_t_1_1_0_V_reg_62553;
reg [3:0] cpat_match_t_1_1_1_V_reg_62558;
reg [3:0] cpat_match_t_1_1_2_V_reg_62563;
reg [3:0] cpat_match_t_1_1_3_V_reg_62568;
reg [3:0] cpat_match_t_1_2_0_V_reg_62573;
reg [3:0] cpat_match_t_1_2_1_V_reg_62578;
reg [3:0] cpat_match_t_1_2_2_V_reg_62583;
reg [3:0] cpat_match_t_1_2_3_V_reg_62588;
reg [3:0] cpat_match_t_2_0_0_V_reg_62593;
reg [3:0] cpat_match_t_2_0_1_V_reg_62598;
reg [3:0] cpat_match_t_2_0_2_V_reg_62603;
reg [3:0] cpat_match_t_2_0_3_V_reg_62608;
reg [3:0] cpat_match_t_2_1_0_V_reg_62613;
reg [3:0] cpat_match_t_2_1_1_V_reg_62618;
reg [3:0] cpat_match_t_2_1_2_V_reg_62623;
reg [3:0] cpat_match_t_2_1_3_V_reg_62628;
reg [3:0] cpat_match_t_2_2_0_V_reg_62633;
reg [3:0] cpat_match_t_2_2_1_V_reg_62638;
reg [3:0] cpat_match_t_2_2_2_V_reg_62643;
reg [3:0] cpat_match_t_2_2_3_V_reg_62648;
reg [3:0] cpat_match_t_3_0_0_V_reg_62653;
reg [3:0] cpat_match_t_3_0_1_V_reg_62658;
reg [3:0] cpat_match_t_3_0_2_V_reg_62663;
reg [3:0] cpat_match_t_3_0_3_V_reg_62668;
reg [3:0] cpat_match_t_3_1_0_V_reg_62673;
reg [3:0] cpat_match_t_3_1_1_V_reg_62678;
reg [3:0] cpat_match_t_3_1_2_V_reg_62683;
reg [3:0] cpat_match_t_3_1_3_V_reg_62688;
reg [3:0] cpat_match_t_3_2_0_V_reg_62693;
reg [3:0] cpat_match_t_3_2_1_V_reg_62698;
reg [3:0] cpat_match_t_3_2_2_V_reg_62703;
reg [3:0] cpat_match_t_3_2_3_V_reg_62708;
reg [6:0] th_match_t1_0_0_1_0_V_reg_62713;
reg [6:0] th_match_t1_0_0_1_1_V_reg_62718;
reg [6:0] th_match_t1_0_0_2_0_V_reg_62723;
reg [6:0] th_match_t1_0_0_2_1_V_reg_62728;
reg [6:0] th_match_t1_0_0_3_0_V_reg_62733;
reg [6:0] th_match_t1_0_0_3_1_V_reg_62738;
reg [6:0] th_match_t1_0_1_1_0_V_reg_62743;
reg [6:0] th_match_t1_0_1_1_1_V_reg_62748;
reg [6:0] th_match_t1_0_1_2_0_V_reg_62753;
reg [6:0] th_match_t1_0_1_2_1_V_reg_62758;
reg [6:0] th_match_t1_0_1_3_0_V_reg_62763;
reg [6:0] th_match_t1_0_1_3_1_V_reg_62768;
reg [6:0] th_match_t1_0_2_1_0_V_reg_62773;
reg [6:0] th_match_t1_0_2_1_1_V_reg_62778;
reg [6:0] th_match_t1_0_2_2_0_V_reg_62783;
reg [6:0] th_match_t1_0_2_2_1_V_reg_62788;
reg [6:0] th_match_t1_0_2_3_0_V_reg_62793;
reg [6:0] th_match_t1_0_2_3_1_V_reg_62798;
reg [6:0] th_match_t1_1_0_1_0_V_reg_62803;
reg [6:0] th_match_t1_1_0_1_1_V_reg_62808;
reg [6:0] th_match_t1_1_0_2_0_V_reg_62813;
reg [6:0] th_match_t1_1_0_2_1_V_reg_62818;
reg [6:0] th_match_t1_1_0_3_0_V_reg_62823;
reg [6:0] th_match_t1_1_0_3_1_V_reg_62828;
reg [6:0] th_match_t1_1_1_1_0_V_reg_62833;
reg [6:0] th_match_t1_1_1_1_1_V_reg_62838;
reg [6:0] th_match_t1_1_1_2_0_V_reg_62843;
reg [6:0] th_match_t1_1_1_2_1_V_reg_62848;
reg [6:0] th_match_t1_1_1_3_0_V_reg_62853;
reg [6:0] th_match_t1_1_1_3_1_V_reg_62858;
reg [6:0] th_match_t1_1_2_1_0_V_reg_62863;
reg [6:0] th_match_t1_1_2_1_1_V_reg_62868;
reg [6:0] th_match_t1_1_2_2_0_V_reg_62873;
reg [6:0] th_match_t1_1_2_2_1_V_reg_62878;
reg [6:0] th_match_t1_1_2_3_0_V_reg_62883;
reg [6:0] th_match_t1_1_2_3_1_V_reg_62888;
reg [6:0] th_match_t1_2_0_0_0_V_reg_62893;
reg [6:0] th_match_t1_2_0_0_1_V_reg_62898;
reg [6:0] th_match_t1_2_0_1_0_V_reg_62903;
reg [6:0] th_match_t1_2_0_1_1_V_reg_62908;
reg [6:0] th_match_t1_2_0_2_0_V_reg_62913;
reg [6:0] th_match_t1_2_0_2_1_V_reg_62918;
reg [6:0] th_match_t1_2_0_3_0_V_reg_62923;
reg [6:0] th_match_t1_2_0_3_1_V_reg_62928;
reg [6:0] th_match_t1_2_1_0_0_V_reg_62933;
reg [6:0] th_match_t1_2_1_0_1_V_reg_62938;
reg [6:0] th_match_t1_2_1_1_0_V_reg_62943;
reg [6:0] th_match_t1_2_1_1_1_V_reg_62948;
reg [6:0] th_match_t1_2_1_2_0_V_reg_62953;
reg [6:0] th_match_t1_2_1_2_1_V_reg_62958;
reg [6:0] th_match_t1_2_1_3_0_V_reg_62963;
reg [6:0] th_match_t1_2_1_3_1_V_reg_62968;
reg [6:0] th_match_t1_2_2_0_0_V_reg_62973;
reg [6:0] th_match_t1_2_2_0_1_V_reg_62978;
reg [6:0] th_match_t1_2_2_1_0_V_reg_62983;
reg [6:0] th_match_t1_2_2_1_1_V_reg_62988;
reg [6:0] th_match_t1_2_2_2_0_V_reg_62993;
reg [6:0] th_match_t1_2_2_2_1_V_reg_62998;
reg [6:0] th_match_t1_2_2_3_0_V_reg_63003;
reg [6:0] th_match_t1_2_2_3_1_V_reg_63008;
reg [6:0] th_match_t1_3_0_0_0_V_reg_63013;
reg [6:0] th_match_t1_3_0_0_1_V_reg_63018;
reg [6:0] th_match_t1_3_0_1_0_V_reg_63023;
reg [6:0] th_match_t1_3_0_1_1_V_reg_63028;
reg [6:0] th_match_t1_3_0_2_0_V_reg_63033;
reg [6:0] th_match_t1_3_0_2_1_V_reg_63038;
reg [6:0] th_match_t1_3_0_3_0_V_reg_63043;
reg [6:0] th_match_t1_3_0_3_1_V_reg_63048;
reg [6:0] th_match_t1_3_1_0_0_V_reg_63053;
reg [6:0] th_match_t1_3_1_0_1_V_reg_63058;
reg [6:0] th_match_t1_3_1_1_0_V_reg_63063;
reg [6:0] th_match_t1_3_1_1_1_V_reg_63068;
reg [6:0] th_match_t1_3_1_2_0_V_reg_63073;
reg [6:0] th_match_t1_3_1_2_1_V_reg_63078;
reg [6:0] th_match_t1_3_1_3_0_V_reg_63083;
reg [6:0] th_match_t1_3_1_3_1_V_reg_63088;
reg [6:0] th_match_t1_3_2_0_0_V_reg_63093;
reg [6:0] th_match_t1_3_2_0_1_V_reg_63098;
reg [6:0] th_match_t1_3_2_1_0_V_reg_63103;
reg [6:0] th_match_t1_3_2_1_1_V_reg_63108;
reg [6:0] th_match_t1_3_2_2_0_V_reg_63113;
reg [6:0] th_match_t1_3_2_2_1_V_reg_63118;
reg [6:0] th_match_t1_3_2_3_0_V_reg_63123;
reg [6:0] th_match_t1_3_2_3_1_V_reg_63128;
reg [6:0] th_match11_t_0_0_0_V_reg_63133;
reg [6:0] th_match11_t_0_0_1_V_reg_63138;
reg [6:0] th_match11_t_0_0_2_V_reg_63143;
reg [6:0] th_match11_t_0_0_3_V_reg_63148;
reg [6:0] th_match11_t_0_1_0_V_reg_63153;
reg [6:0] th_match11_t_0_1_1_V_reg_63158;
reg [6:0] th_match11_t_0_1_2_V_reg_63163;
reg [6:0] th_match11_t_0_1_3_V_reg_63168;
reg [6:0] th_match11_t_0_2_0_V_reg_63173;
reg [6:0] th_match11_t_0_2_1_V_reg_63178;
reg [6:0] th_match11_t_0_2_2_V_reg_63183;
reg [6:0] th_match11_t_0_2_3_V_reg_63188;
reg [6:0] th_match11_t_1_0_0_V_reg_63193;
reg [6:0] th_match11_t_1_0_1_V_reg_63198;
reg [6:0] th_match11_t_1_0_2_V_reg_63203;
reg [6:0] th_match11_t_1_0_3_V_reg_63208;
reg [6:0] th_match11_t_1_1_0_V_reg_63213;
reg [6:0] th_match11_t_1_1_1_V_reg_63218;
reg [6:0] th_match11_t_1_1_2_V_reg_63223;
reg [6:0] th_match11_t_1_1_3_V_reg_63228;
reg [6:0] th_match11_t_1_2_0_V_reg_63233;
reg [6:0] th_match11_t_1_2_1_V_reg_63238;
reg [6:0] th_match11_t_1_2_2_V_reg_63243;
reg [6:0] th_match11_t_1_2_3_V_reg_63248;
reg [11:0] phi_t_0_0_V_reg_63253;
reg [11:0] phi_t_0_1_V_reg_63258;
reg [11:0] phi_t_0_2_V_reg_63263;
reg [11:0] phi_t_1_0_V_reg_63268;
reg [11:0] phi_t_1_1_V_reg_63273;
reg [11:0] phi_t_1_2_V_reg_63278;
reg [11:0] phi_t_2_0_V_reg_63283;
reg [11:0] phi_t_2_1_V_reg_63288;
reg [11:0] phi_t_2_2_V_reg_63293;
reg [11:0] phi_t_3_0_V_reg_63298;
reg [11:0] phi_t_3_1_V_reg_63303;
reg [11:0] phi_t_3_2_V_reg_63308;
reg [6:0] theta_t_0_0_V_reg_63313;
reg [6:0] theta_t_0_1_V_reg_63318;
reg [6:0] theta_t_0_2_V_reg_63323;
reg [6:0] theta_t_1_0_V_reg_63328;
reg [6:0] theta_t_1_1_V_reg_63333;
reg [6:0] theta_t_1_2_V_reg_63338;
reg [6:0] theta_t_2_0_V_reg_63343;
reg [6:0] theta_t_2_1_V_reg_63348;
reg [6:0] theta_t_2_2_V_reg_63353;
reg [6:0] theta_t_3_0_V_reg_63358;
reg [6:0] theta_t_3_1_V_reg_63363;
reg [6:0] theta_t_3_2_V_reg_63368;
reg [5:0] sign_ph_t_0_0_V_reg_63373;
reg [5:0] sign_ph_t_0_1_V_reg_63378;
reg [5:0] sign_ph_t_0_2_V_reg_63383;
reg [5:0] sign_ph_t_1_0_V_reg_63388;
reg [5:0] sign_ph_t_1_1_V_reg_63393;
reg [5:0] sign_ph_t_1_2_V_reg_63398;
reg [5:0] sign_ph_t_2_0_V_reg_63403;
reg [5:0] sign_ph_t_2_1_V_reg_63408;
reg [5:0] sign_ph_t_2_2_V_reg_63413;
reg [5:0] sign_ph_t_3_0_V_reg_63418;
reg [5:0] sign_ph_t_3_1_V_reg_63423;
reg [5:0] sign_ph_t_3_2_V_reg_63428;
reg [5:0] sign_th_t_0_0_V_reg_63433;
reg [5:0] sign_th_t_0_1_V_reg_63438;
reg [5:0] sign_th_t_0_2_V_reg_63443;
reg [5:0] sign_th_t_1_0_V_reg_63448;
reg [5:0] sign_th_t_1_1_V_reg_63453;
reg [5:0] sign_th_t_1_2_V_reg_63458;
reg [5:0] sign_th_t_2_0_V_reg_63463;
reg [5:0] sign_th_t_2_1_V_reg_63468;
reg [5:0] sign_th_t_2_2_V_reg_63473;
reg [5:0] sign_th_t_3_0_V_reg_63478;
reg [5:0] sign_th_t_3_1_V_reg_63483;
reg [5:0] sign_th_t_3_2_V_reg_63488;
reg [6:0] rank_t_0_0_V_reg_63493;
reg [6:0] rank_t_0_1_V_reg_63498;
reg [6:0] rank_t_0_2_V_reg_63503;
reg [6:0] rank_t_1_0_V_reg_63508;
reg [6:0] rank_t_1_1_V_reg_63513;
reg [6:0] rank_t_1_2_V_reg_63518;
reg [6:0] rank_t_2_0_V_reg_63523;
reg [6:0] rank_t_2_1_V_reg_63528;
reg [6:0] rank_t_2_2_V_reg_63533;
reg [6:0] rank_t_3_0_V_reg_63538;
reg [6:0] rank_t_3_1_V_reg_63543;
reg [6:0] rank_t_3_2_V_reg_63548;
reg [3:0] cpattern_t_0_0_0_V_reg_63553;
reg [3:0] cpattern_t_0_0_1_V_reg_63558;
reg [3:0] cpattern_t_0_0_2_V_reg_63563;
reg [3:0] cpattern_t_0_0_3_V_reg_63568;
reg [3:0] cpattern_t_0_1_0_V_reg_63573;
reg [3:0] cpattern_t_0_1_1_V_reg_63578;
reg [3:0] cpattern_t_0_1_2_V_reg_63583;
reg [3:0] cpattern_t_0_1_3_V_reg_63588;
reg [3:0] cpattern_t_0_2_0_V_reg_63593;
reg [3:0] cpattern_t_0_2_1_V_reg_63598;
reg [3:0] cpattern_t_0_2_2_V_reg_63603;
reg [3:0] cpattern_t_0_2_3_V_reg_63608;
reg [3:0] cpattern_t_1_0_0_V_reg_63613;
reg [3:0] cpattern_t_1_0_1_V_reg_63618;
reg [3:0] cpattern_t_1_0_2_V_reg_63623;
reg [3:0] cpattern_t_1_0_3_V_reg_63628;
reg [3:0] cpattern_t_1_1_0_V_reg_63633;
reg [3:0] cpattern_t_1_1_1_V_reg_63638;
reg [3:0] cpattern_t_1_1_2_V_reg_63643;
reg [3:0] cpattern_t_1_1_3_V_reg_63648;
reg [3:0] cpattern_t_1_2_0_V_reg_63653;
reg [3:0] cpattern_t_1_2_1_V_reg_63658;
reg [3:0] cpattern_t_1_2_2_V_reg_63663;
reg [3:0] cpattern_t_1_2_3_V_reg_63668;
reg [3:0] cpattern_t_2_0_0_V_reg_63673;
reg [3:0] cpattern_t_2_0_1_V_reg_63678;
reg [3:0] cpattern_t_2_0_2_V_reg_63683;
reg [3:0] cpattern_t_2_0_3_V_reg_63688;
reg [3:0] cpattern_t_2_1_0_V_reg_63693;
reg [3:0] cpattern_t_2_1_1_V_reg_63698;
reg [3:0] cpattern_t_2_1_2_V_reg_63703;
reg [3:0] cpattern_t_2_1_3_V_reg_63708;
reg [3:0] cpattern_t_2_2_0_V_reg_63713;
reg [3:0] cpattern_t_2_2_1_V_reg_63718;
reg [3:0] cpattern_t_2_2_2_V_reg_63723;
reg [3:0] cpattern_t_2_2_3_V_reg_63728;
reg [3:0] cpattern_t_3_0_0_V_reg_63733;
reg [3:0] cpattern_t_3_0_1_V_reg_63738;
reg [3:0] cpattern_t_3_0_2_V_reg_63743;
reg [3:0] cpattern_t_3_0_3_V_reg_63748;
reg [3:0] cpattern_t_3_1_0_V_reg_63753;
reg [3:0] cpattern_t_3_1_1_V_reg_63758;
reg [3:0] cpattern_t_3_1_2_V_reg_63763;
reg [3:0] cpattern_t_3_1_3_V_reg_63768;
reg [3:0] cpattern_t_3_2_0_V_reg_63773;
reg [3:0] cpattern_t_3_2_1_V_reg_63778;
reg [3:0] cpattern_t_3_2_2_V_reg_63783;
reg [3:0] cpattern_t_3_2_3_V_reg_63788;
reg [11:0] delta_ph_t_0_0_0_V_reg_63793;
reg [11:0] delta_ph_t_0_0_1_V_reg_63798;
reg [11:0] delta_ph_t_0_0_2_V_reg_63803;
reg [11:0] delta_ph_t_0_0_3_V_reg_63808;
reg [11:0] delta_ph_t_0_0_4_V_reg_63813;
reg [11:0] delta_ph_t_0_0_5_V_reg_63818;
reg [11:0] delta_ph_t_0_1_0_V_reg_63823;
reg [11:0] delta_ph_t_0_1_1_V_reg_63828;
reg [11:0] delta_ph_t_0_1_2_V_reg_63833;
reg [11:0] delta_ph_t_0_1_3_V_reg_63838;
reg [11:0] delta_ph_t_0_1_4_V_reg_63843;
reg [11:0] delta_ph_t_0_1_5_V_reg_63848;
reg [11:0] delta_ph_t_0_2_0_V_reg_63853;
reg [11:0] delta_ph_t_0_2_1_V_reg_63858;
reg [11:0] delta_ph_t_0_2_2_V_reg_63863;
reg [11:0] delta_ph_t_0_2_3_V_reg_63868;
reg [11:0] delta_ph_t_0_2_4_V_reg_63873;
reg [11:0] delta_ph_t_0_2_5_V_reg_63878;
reg [11:0] delta_ph_t_1_0_0_V_reg_63883;
reg [11:0] delta_ph_t_1_0_1_V_reg_63888;
reg [11:0] delta_ph_t_1_0_2_V_reg_63893;
reg [11:0] delta_ph_t_1_0_3_V_reg_63898;
reg [11:0] delta_ph_t_1_0_4_V_reg_63903;
reg [11:0] delta_ph_t_1_0_5_V_reg_63908;
reg [11:0] delta_ph_t_1_1_0_V_reg_63913;
reg [11:0] delta_ph_t_1_1_1_V_reg_63918;
reg [11:0] delta_ph_t_1_1_2_V_reg_63923;
reg [11:0] delta_ph_t_1_1_3_V_reg_63928;
reg [11:0] delta_ph_t_1_1_4_V_reg_63933;
reg [11:0] delta_ph_t_1_1_5_V_reg_63938;
reg [11:0] delta_ph_t_1_2_0_V_reg_63943;
reg [11:0] delta_ph_t_1_2_1_V_reg_63948;
reg [11:0] delta_ph_t_1_2_2_V_reg_63953;
reg [11:0] delta_ph_t_1_2_3_V_reg_63958;
reg [11:0] delta_ph_t_1_2_4_V_reg_63963;
reg [11:0] delta_ph_t_1_2_5_V_reg_63968;
reg [11:0] delta_ph_t_2_0_0_V_reg_63973;
reg [11:0] delta_ph_t_2_0_1_V_reg_63978;
reg [11:0] delta_ph_t_2_0_2_V_reg_63983;
reg [11:0] delta_ph_t_2_0_3_V_reg_63988;
reg [11:0] delta_ph_t_2_0_4_V_reg_63993;
reg [11:0] delta_ph_t_2_0_5_V_reg_63998;
reg [11:0] delta_ph_t_2_1_0_V_reg_64003;
reg [11:0] delta_ph_t_2_1_1_V_reg_64008;
reg [11:0] delta_ph_t_2_1_2_V_reg_64013;
reg [11:0] delta_ph_t_2_1_3_V_reg_64018;
reg [11:0] delta_ph_t_2_1_4_V_reg_64023;
reg [11:0] delta_ph_t_2_1_5_V_reg_64028;
reg [11:0] delta_ph_t_2_2_0_V_reg_64033;
reg [11:0] delta_ph_t_2_2_1_V_reg_64038;
reg [11:0] delta_ph_t_2_2_2_V_reg_64043;
reg [11:0] delta_ph_t_2_2_3_V_reg_64048;
reg [11:0] delta_ph_t_2_2_4_V_reg_64053;
reg [11:0] delta_ph_t_2_2_5_V_reg_64058;
reg [11:0] delta_ph_t_3_0_0_V_reg_64063;
reg [11:0] delta_ph_t_3_0_1_V_reg_64068;
reg [11:0] delta_ph_t_3_0_2_V_reg_64073;
reg [11:0] delta_ph_t_3_0_3_V_reg_64078;
reg [11:0] delta_ph_t_3_0_4_V_reg_64083;
reg [11:0] delta_ph_t_3_0_5_V_reg_64088;
reg [11:0] delta_ph_t_3_1_0_V_reg_64093;
reg [11:0] delta_ph_t_3_1_1_V_reg_64098;
reg [11:0] delta_ph_t_3_1_2_V_reg_64103;
reg [11:0] delta_ph_t_3_1_3_V_reg_64108;
reg [11:0] delta_ph_t_3_1_4_V_reg_64113;
reg [11:0] delta_ph_t_3_1_5_V_reg_64118;
reg [11:0] delta_ph_t_3_2_0_V_reg_64123;
reg [11:0] delta_ph_t_3_2_1_V_reg_64128;
reg [11:0] delta_ph_t_3_2_2_V_reg_64133;
reg [11:0] delta_ph_t_3_2_3_V_reg_64138;
reg [11:0] delta_ph_t_3_2_4_V_reg_64143;
reg [11:0] delta_ph_t_3_2_5_V_reg_64148;
reg [6:0] delta_th_t_0_0_0_V_reg_64153;
reg [6:0] delta_th_t_0_0_1_V_reg_64158;
reg [6:0] delta_th_t_0_0_2_V_reg_64163;
reg [6:0] delta_th_t_0_0_3_V_reg_64168;
reg [6:0] delta_th_t_0_0_4_V_reg_64173;
reg [6:0] delta_th_t_0_0_5_V_reg_64178;
reg [6:0] delta_th_t_0_1_0_V_reg_64183;
reg [6:0] delta_th_t_0_1_1_V_reg_64188;
reg [6:0] delta_th_t_0_1_2_V_reg_64193;
reg [6:0] delta_th_t_0_1_3_V_reg_64198;
reg [6:0] delta_th_t_0_1_4_V_reg_64203;
reg [6:0] delta_th_t_0_1_5_V_reg_64208;
reg [6:0] delta_th_t_0_2_0_V_reg_64213;
reg [6:0] delta_th_t_0_2_1_V_reg_64218;
reg [6:0] delta_th_t_0_2_2_V_reg_64223;
reg [6:0] delta_th_t_0_2_3_V_reg_64228;
reg [6:0] delta_th_t_0_2_4_V_reg_64233;
reg [6:0] delta_th_t_0_2_5_V_reg_64238;
reg [6:0] delta_th_t_1_0_0_V_reg_64243;
reg [6:0] delta_th_t_1_0_1_V_reg_64248;
reg [6:0] delta_th_t_1_0_2_V_reg_64253;
reg [6:0] delta_th_t_1_0_3_V_reg_64258;
reg [6:0] delta_th_t_1_0_4_V_reg_64263;
reg [6:0] delta_th_t_1_0_5_V_reg_64268;
reg [6:0] delta_th_t_1_1_0_V_reg_64273;
reg [6:0] delta_th_t_1_1_1_V_reg_64278;
reg [6:0] delta_th_t_1_1_2_V_reg_64283;
reg [6:0] delta_th_t_1_1_3_V_reg_64288;
reg [6:0] delta_th_t_1_1_4_V_reg_64293;
reg [6:0] delta_th_t_1_1_5_V_reg_64298;
reg [6:0] delta_th_t_1_2_0_V_reg_64303;
reg [6:0] delta_th_t_1_2_1_V_reg_64308;
reg [6:0] delta_th_t_1_2_2_V_reg_64313;
reg [6:0] delta_th_t_1_2_3_V_reg_64318;
reg [6:0] delta_th_t_1_2_4_V_reg_64323;
reg [6:0] delta_th_t_1_2_5_V_reg_64328;
reg [6:0] delta_th_t_2_0_0_V_reg_64333;
reg [6:0] delta_th_t_2_0_1_V_reg_64338;
reg [6:0] delta_th_t_2_0_2_V_reg_64343;
reg [6:0] delta_th_t_2_0_3_V_reg_64348;
reg [6:0] delta_th_t_2_0_4_V_reg_64353;
reg [6:0] delta_th_t_2_0_5_V_reg_64358;
reg [6:0] delta_th_t_2_1_0_V_reg_64363;
reg [6:0] delta_th_t_2_1_1_V_reg_64368;
reg [6:0] delta_th_t_2_1_2_V_reg_64373;
reg [6:0] delta_th_t_2_1_3_V_reg_64378;
reg [6:0] delta_th_t_2_1_4_V_reg_64383;
reg [6:0] delta_th_t_2_1_5_V_reg_64388;
reg [6:0] delta_th_t_2_2_0_V_reg_64393;
reg [6:0] delta_th_t_2_2_1_V_reg_64398;
reg [6:0] delta_th_t_2_2_2_V_reg_64403;
reg [6:0] delta_th_t_2_2_3_V_reg_64408;
reg [6:0] delta_th_t_2_2_4_V_reg_64413;
reg [6:0] delta_th_t_2_2_5_V_reg_64418;
reg [6:0] delta_th_t_3_0_0_V_reg_64423;
reg [6:0] delta_th_t_3_0_1_V_reg_64428;
reg [6:0] delta_th_t_3_0_2_V_reg_64433;
reg [6:0] delta_th_t_3_0_3_V_reg_64438;
reg [6:0] delta_th_t_3_0_4_V_reg_64443;
reg [6:0] delta_th_t_3_0_5_V_reg_64448;
reg [6:0] delta_th_t_3_1_0_V_reg_64453;
reg [6:0] delta_th_t_3_1_1_V_reg_64458;
reg [6:0] delta_th_t_3_1_2_V_reg_64463;
reg [6:0] delta_th_t_3_1_3_V_reg_64468;
reg [6:0] delta_th_t_3_1_4_V_reg_64473;
reg [6:0] delta_th_t_3_1_5_V_reg_64478;
reg [6:0] delta_th_t_3_2_0_V_reg_64483;
reg [6:0] delta_th_t_3_2_1_V_reg_64488;
reg [6:0] delta_th_t_3_2_2_V_reg_64493;
reg [6:0] delta_th_t_3_2_3_V_reg_64498;
reg [6:0] delta_th_t_3_2_4_V_reg_64503;
reg [6:0] delta_th_t_3_2_5_V_reg_64508;
reg [11:0] bt_phi_t_0_V_reg_64513;
reg [11:0] bt_phi_t_1_V_reg_64519;
reg [11:0] bt_phi_t_2_V_reg_64525;
reg [6:0] bt_theta_t_0_V_reg_64531;
reg [6:0] bt_theta_t_1_V_reg_64537;
reg [6:0] bt_theta_t_2_V_reg_64543;
reg [3:0] bt_cpattern_t_0_0_V_reg_64549;
reg [3:0] bt_cpattern_t_0_1_V_reg_64555;
reg [3:0] bt_cpattern_t_0_2_V_reg_64561;
reg [3:0] bt_cpattern_t_0_3_V_reg_64567;
reg [3:0] bt_cpattern_t_1_0_V_reg_64573;
reg [3:0] bt_cpattern_t_1_1_V_reg_64579;
reg [3:0] bt_cpattern_t_1_2_V_reg_64585;
reg [3:0] bt_cpattern_t_1_3_V_reg_64591;
reg [3:0] bt_cpattern_t_2_0_V_reg_64597;
reg [3:0] bt_cpattern_t_2_1_V_reg_64603;
reg [3:0] bt_cpattern_t_2_2_V_reg_64609;
reg [3:0] bt_cpattern_t_2_3_V_reg_64615;
reg [11:0] bt_delta_ph_t_0_0_V_reg_64621;
reg [11:0] bt_delta_ph_t_0_1_V_reg_64627;
reg [11:0] bt_delta_ph_t_0_2_V_reg_64633;
reg [11:0] bt_delta_ph_t_0_3_V_reg_64639;
reg [11:0] bt_delta_ph_t_0_4_V_reg_64645;
reg [11:0] bt_delta_ph_t_0_5_V_reg_64651;
reg [11:0] bt_delta_ph_t_1_0_V_reg_64657;
reg [11:0] bt_delta_ph_t_1_1_V_reg_64663;
reg [11:0] bt_delta_ph_t_1_2_V_reg_64669;
reg [11:0] bt_delta_ph_t_1_3_V_reg_64675;
reg [11:0] bt_delta_ph_t_1_4_V_reg_64681;
reg [11:0] bt_delta_ph_t_1_5_V_reg_64687;
reg [11:0] bt_delta_ph_t_2_0_V_reg_64693;
reg [11:0] bt_delta_ph_t_2_1_V_reg_64699;
reg [11:0] bt_delta_ph_t_2_2_V_reg_64705;
reg [11:0] bt_delta_ph_t_2_3_V_reg_64711;
reg [11:0] bt_delta_ph_t_2_4_V_reg_64717;
reg [11:0] bt_delta_ph_t_2_5_V_reg_64723;
reg [6:0] bt_delta_th_t_0_0_V_reg_64729;
reg [6:0] bt_delta_th_t_0_1_V_reg_64735;
reg [6:0] bt_delta_th_t_0_2_V_reg_64741;
reg [6:0] bt_delta_th_t_0_3_V_reg_64747;
reg [6:0] bt_delta_th_t_0_4_V_reg_64753;
reg [6:0] bt_delta_th_t_0_5_V_reg_64759;
reg [6:0] bt_delta_th_t_1_0_V_reg_64765;
reg [6:0] bt_delta_th_t_1_1_V_reg_64771;
reg [6:0] bt_delta_th_t_1_2_V_reg_64777;
reg [6:0] bt_delta_th_t_1_3_V_reg_64783;
reg [6:0] bt_delta_th_t_1_4_V_reg_64789;
reg [6:0] bt_delta_th_t_1_5_V_reg_64795;
reg [6:0] bt_delta_th_t_2_0_V_reg_64801;
reg [6:0] bt_delta_th_t_2_1_V_reg_64807;
reg [6:0] bt_delta_th_t_2_2_V_reg_64813;
reg [6:0] bt_delta_th_t_2_3_V_reg_64819;
reg [6:0] bt_delta_th_t_2_4_V_reg_64825;
reg [6:0] bt_delta_th_t_2_5_V_reg_64831;
reg [5:0] bt_sign_ph_t_0_V_reg_64837;
reg [5:0] bt_sign_ph_t_1_V_reg_64843;
reg [5:0] bt_sign_ph_t_2_V_reg_64849;
reg [5:0] bt_sign_th_t_0_V_reg_64855;
reg [5:0] bt_sign_th_t_1_V_reg_64861;
reg [5:0] bt_sign_th_t_2_V_reg_64867;
reg [6:0] bt_rank_t_0_V_reg_64873;
reg [6:0] bt_rank_t_1_V_reg_64879;
reg [6:0] bt_rank_t_2_V_reg_64885;
reg [1:0] bt_vi_t_0_0_V_reg_64891;
reg [1:0] bt_vi_t_0_1_V_reg_64897;
reg [1:0] bt_vi_t_0_2_V_reg_64902;
reg [1:0] bt_vi_t_0_3_V_reg_64907;
reg [1:0] bt_vi_t_0_4_V_reg_64912;
reg [1:0] bt_vi_t_1_0_V_reg_64917;
reg [1:0] bt_vi_t_1_1_V_reg_64923;
reg [1:0] bt_vi_t_1_2_V_reg_64928;
reg [1:0] bt_vi_t_1_3_V_reg_64933;
reg [1:0] bt_vi_t_1_4_V_reg_64938;
reg [1:0] bt_vi_t_2_0_V_reg_64943;
reg [1:0] bt_vi_t_2_1_V_reg_64949;
reg [1:0] bt_vi_t_2_2_V_reg_64954;
reg [1:0] bt_vi_t_2_3_V_reg_64959;
reg [1:0] bt_vi_t_2_4_V_reg_64964;
reg [1:0] bt_hi_t_0_0_V_reg_64969;
reg [1:0] bt_hi_t_0_1_V_reg_64974;
reg [1:0] bt_hi_t_0_2_V_reg_64979;
reg [1:0] bt_hi_t_0_3_V_reg_64984;
reg [1:0] bt_hi_t_0_4_V_reg_64989;
reg [1:0] bt_hi_t_1_0_V_reg_64994;
reg [1:0] bt_hi_t_1_1_V_reg_64999;
reg [1:0] bt_hi_t_1_2_V_reg_65004;
reg [1:0] bt_hi_t_1_3_V_reg_65009;
reg [1:0] bt_hi_t_1_4_V_reg_65014;
reg [1:0] bt_hi_t_2_0_V_reg_65019;
reg [1:0] bt_hi_t_2_1_V_reg_65024;
reg [1:0] bt_hi_t_2_2_V_reg_65029;
reg [1:0] bt_hi_t_2_3_V_reg_65034;
reg [1:0] bt_hi_t_2_4_V_reg_65039;
reg [3:0] bt_ci_t_0_0_V_reg_65044;
reg [3:0] bt_ci_t_0_1_V_reg_65050;
reg [3:0] bt_ci_t_0_2_V_reg_65056;
reg [3:0] bt_ci_t_0_3_V_reg_65062;
reg [3:0] bt_ci_t_0_4_V_reg_65068;
reg [3:0] bt_ci_t_1_0_V_reg_65074;
reg [3:0] bt_ci_t_1_1_V_reg_65080;
reg [3:0] bt_ci_t_1_2_V_reg_65086;
reg [3:0] bt_ci_t_1_3_V_reg_65092;
reg [3:0] bt_ci_t_1_4_V_reg_65098;
reg [3:0] bt_ci_t_2_0_V_reg_65104;
reg [3:0] bt_ci_t_2_1_V_reg_65110;
reg [3:0] bt_ci_t_2_2_V_reg_65116;
reg [3:0] bt_ci_t_2_3_V_reg_65122;
reg [3:0] bt_ci_t_2_4_V_reg_65128;
reg [4:0] bt_si_t_0_V_reg_65134;
reg [4:0] bt_si_t_1_V_reg_65139;
reg [4:0] bt_si_t_2_V_reg_65144;
wire grp_sp_ph_pattern_sector_fu_28574_ap_start;
wire grp_sp_ph_pattern_sector_fu_28574_ap_done;
wire grp_sp_ph_pattern_sector_fu_28574_ap_idle;
wire grp_sp_ph_pattern_sector_fu_28574_ap_ready;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_0;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_1;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_2;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_3;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_4;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_5;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_6;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_7;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_8;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_9;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_10;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_11;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_12;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_13;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_14;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_15;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_16;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_17;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_18;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_19;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_20;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_21;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_22;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_23;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_24;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_25;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_26;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_27;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_28;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_29;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_30;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_31;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_32;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_33;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_34;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_35;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_36;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_37;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_38;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_39;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_40;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_41;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_42;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_43;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_44;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_45;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_46;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_47;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_48;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_49;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_50;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_51;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_52;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_53;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_54;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_55;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_56;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_57;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_58;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_59;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_60;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_61;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_62;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_63;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_64;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_65;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_66;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_67;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_68;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_69;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_70;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_71;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_72;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_73;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_74;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_75;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_76;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_77;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_78;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_79;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_80;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_81;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_82;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_83;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_84;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_85;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_86;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_87;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_88;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_89;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_90;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_91;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_92;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_93;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_94;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_95;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_96;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_97;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_98;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_99;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_100;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_101;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_102;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_103;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_104;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_105;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_106;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_107;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_108;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_109;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_110;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_111;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_112;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_113;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_114;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_115;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_116;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_117;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_118;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_119;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_120;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_121;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_122;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_123;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_124;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_125;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_126;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_127;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_128;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_129;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_130;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_131;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_132;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_133;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_134;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_135;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_136;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_137;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_138;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_139;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_140;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_141;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_142;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_143;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_144;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_145;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_146;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_147;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_148;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_149;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_150;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_151;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_152;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_153;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_154;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_155;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_156;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_157;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_158;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_159;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_160;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_161;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_162;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_163;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_164;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_165;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_166;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_167;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_168;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_169;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_170;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_171;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_172;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_173;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_174;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_175;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_176;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_177;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_178;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_179;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_180;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_181;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_182;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_183;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_184;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_185;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_186;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_187;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_188;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_189;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_190;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_191;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_192;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_193;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_194;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_195;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_196;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_197;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_198;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_199;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_200;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_201;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_202;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_203;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_204;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_205;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_206;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_207;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_208;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_209;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_210;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_211;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_212;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_213;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_214;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_215;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_216;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_217;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_218;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_219;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_220;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_221;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_222;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_223;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_224;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_225;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_226;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_227;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_228;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_229;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_230;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_231;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_232;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_233;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_234;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_235;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_236;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_237;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_238;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_239;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_240;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_241;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_242;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_243;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_244;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_245;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_246;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_247;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_248;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_249;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_250;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_251;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_252;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_253;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_254;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_255;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_256;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_257;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_258;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_259;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_260;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_261;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_262;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_263;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_264;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_265;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_266;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_267;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_268;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_269;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_270;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_271;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_272;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_273;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_274;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_275;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_276;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_277;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_278;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_279;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_280;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_281;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_282;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_283;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_284;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_285;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_286;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_287;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_288;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_289;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_290;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_291;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_292;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_293;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_294;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_295;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_296;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_297;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_298;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_299;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_300;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_301;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_302;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_303;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_304;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_305;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_306;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_307;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_308;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_309;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_310;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_311;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_312;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_313;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_314;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_315;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_316;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_317;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_318;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_319;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_320;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_321;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_322;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_323;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_324;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_325;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_326;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_327;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_328;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_329;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_330;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_331;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_332;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_333;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_334;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_335;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_336;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_337;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_338;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_339;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_340;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_341;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_342;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_343;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_344;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_345;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_346;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_347;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_348;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_349;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_350;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_351;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_352;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_353;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_354;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_355;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_356;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_357;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_358;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_359;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_360;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_361;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_362;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_363;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_364;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_365;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_366;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_367;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_368;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_369;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_370;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_371;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_372;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_373;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_374;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_375;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_376;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_377;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_378;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_379;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_380;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_381;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_382;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_383;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_384;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_385;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_386;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_387;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_388;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_389;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_390;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_391;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_392;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_393;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_394;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_395;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_396;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_397;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_398;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_399;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_400;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_401;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_402;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_403;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_404;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_405;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_406;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_407;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_408;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_409;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_410;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_411;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_412;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_413;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_414;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_415;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_416;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_417;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_418;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_419;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_420;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_421;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_422;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_423;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_424;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_425;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_426;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_427;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_428;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_429;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_430;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_431;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_432;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_433;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_434;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_435;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_436;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_437;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_438;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_439;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_440;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_441;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_442;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_443;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_444;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_445;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_446;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_447;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_448;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_449;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_450;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_451;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_452;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_453;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_454;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_455;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_456;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_457;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_458;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_459;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_460;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_461;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_462;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_463;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_464;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_465;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_466;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_467;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_468;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_469;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_470;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_471;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_472;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_473;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_474;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_475;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_476;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_477;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_478;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_479;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_480;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_481;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_482;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_483;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_484;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_485;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_486;
wire [5:0] grp_sp_ph_pattern_sector_fu_28574_ap_return_487;
reg call_ret4_sp_prim_conv_sector_fu_37378_ap_start;
wire call_ret4_sp_prim_conv_sector_fu_37378_ap_done;
wire call_ret4_sp_prim_conv_sector_fu_37378_ap_idle;
wire call_ret4_sp_prim_conv_sector_fu_37378_ap_ready;
wire [2:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_0;
wire [2:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_1;
wire [2:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_2;
wire [2:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_3;
wire [2:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_4;
wire [2:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_5;
wire [2:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_6;
wire [2:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_7;
wire [2:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_8;
wire [2:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_9;
wire [2:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_10;
wire [2:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_11;
wire [2:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_12;
wire [2:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_13;
wire [2:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_14;
wire [2:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_15;
wire [2:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_16;
wire [2:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_17;
wire [2:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_18;
wire [2:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_19;
wire [2:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_20;
wire [2:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_21;
wire [2:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_22;
wire [2:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_23;
wire [2:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_24;
wire [2:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_25;
wire [2:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_26;
wire [2:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_27;
wire [2:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_28;
wire [2:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_29;
wire [2:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_30;
wire [2:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_31;
wire [2:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_32;
wire [43:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_33;
wire [43:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_34;
wire [43:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_35;
wire [43:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_36;
wire [43:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_37;
wire [43:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_38;
wire [43:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_39;
wire [43:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_40;
wire [43:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_41;
wire [43:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_42;
wire [43:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_43;
wire [43:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_44;
wire [43:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_45;
wire [43:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_46;
wire [43:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_47;
wire [43:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_48;
wire [43:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_49;
wire [43:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_50;
wire [43:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_51;
wire [43:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_52;
wire [43:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_53;
wire [43:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_54;
wire [43:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_55;
wire [43:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_56;
wire [43:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_57;
wire [43:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_58;
wire [43:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_59;
wire [43:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_60;
wire [43:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_61;
wire [43:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_62;
wire [43:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_63;
wire [43:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_64;
wire [43:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_65;
wire [43:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_66;
wire [43:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_67;
wire [43:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_68;
wire [43:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_69;
wire [43:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_70;
wire [43:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_71;
wire [2:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_72;
wire [2:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_73;
wire [2:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_74;
wire [2:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_75;
wire [2:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_76;
wire [2:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_77;
wire [43:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_78;
wire [43:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_79;
wire [43:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_80;
wire [43:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_81;
wire [43:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_82;
wire [43:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_83;
wire [11:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_84;
wire [11:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_85;
wire [11:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_86;
wire [11:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_87;
wire [11:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_88;
wire [11:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_89;
wire [11:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_90;
wire [11:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_91;
wire [11:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_92;
wire [11:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_93;
wire [11:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_94;
wire [11:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_95;
wire [11:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_96;
wire [11:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_97;
wire [11:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_98;
wire [11:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_99;
wire [11:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_100;
wire [11:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_101;
wire [11:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_102;
wire [11:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_103;
wire [11:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_104;
wire [11:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_105;
wire [11:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_106;
wire [11:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_107;
wire [11:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_108;
wire [11:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_109;
wire [11:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_110;
wire [11:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_111;
wire [11:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_112;
wire [11:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_113;
wire [11:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_114;
wire [11:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_115;
wire [11:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_116;
wire [11:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_117;
wire [11:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_118;
wire [11:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_119;
wire [11:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_120;
wire [11:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_121;
wire [11:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_122;
wire [11:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_123;
wire [11:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_124;
wire [11:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_125;
wire [11:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_126;
wire [11:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_127;
wire [11:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_128;
wire [11:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_129;
wire [11:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_130;
wire [11:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_131;
wire [11:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_132;
wire [11:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_133;
wire [11:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_134;
wire [11:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_135;
wire [11:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_136;
wire [11:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_137;
wire [11:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_138;
wire [11:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_139;
wire [11:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_140;
wire [11:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_141;
wire [11:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_142;
wire [11:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_143;
wire [11:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_144;
wire [11:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_145;
wire [11:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_146;
wire [11:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_147;
wire [11:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_148;
wire [11:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_149;
wire [11:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_150;
wire [11:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_151;
wire [11:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_152;
wire [11:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_153;
wire [11:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_154;
wire [11:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_155;
wire [11:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_156;
wire [11:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_157;
wire [11:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_158;
wire [11:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_159;
wire [11:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_160;
wire [11:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_161;
wire [11:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_162;
wire [11:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_163;
wire [11:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_164;
wire [11:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_165;
wire [11:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_166;
wire [11:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_167;
wire [11:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_168;
wire [11:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_169;
wire [11:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_170;
wire [11:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_171;
wire [11:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_172;
wire [11:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_173;
wire [3:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_174;
wire [3:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_175;
wire [3:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_176;
wire [3:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_177;
wire [3:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_178;
wire [3:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_179;
wire [3:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_180;
wire [3:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_181;
wire [3:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_182;
wire [3:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_183;
wire [3:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_184;
wire [3:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_185;
wire [3:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_186;
wire [3:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_187;
wire [3:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_188;
wire [3:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_189;
wire [3:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_190;
wire [3:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_191;
wire [3:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_192;
wire [3:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_193;
wire [3:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_194;
wire [3:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_195;
wire [3:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_196;
wire [3:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_197;
wire [3:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_198;
wire [3:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_199;
wire [3:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_200;
wire [3:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_201;
wire [3:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_202;
wire [3:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_203;
wire [3:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_204;
wire [3:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_205;
wire [3:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_206;
wire [3:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_207;
wire [3:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_208;
wire [3:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_209;
wire [3:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_210;
wire [3:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_211;
wire [3:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_212;
wire [3:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_213;
wire [3:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_214;
wire [3:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_215;
wire [3:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_216;
wire [3:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_217;
wire [3:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_218;
wire [3:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_219;
wire [3:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_220;
wire [3:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_221;
wire [3:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_222;
wire [3:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_223;
wire [3:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_224;
wire [3:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_225;
wire [3:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_226;
wire [3:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_227;
wire [3:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_228;
wire [3:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_229;
wire [3:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_230;
wire [3:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_231;
wire [3:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_232;
wire [3:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_233;
wire [3:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_234;
wire [3:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_235;
wire [3:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_236;
wire [3:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_237;
wire [3:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_238;
wire [3:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_239;
wire [3:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_240;
wire [3:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_241;
wire [3:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_242;
wire [3:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_243;
wire [3:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_244;
wire [3:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_245;
wire [3:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_246;
wire [3:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_247;
wire [3:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_248;
wire [3:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_249;
wire [3:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_250;
wire [3:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_251;
wire [3:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_252;
wire [3:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_253;
wire [3:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_254;
wire [3:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_255;
wire [3:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_256;
wire [3:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_257;
wire [3:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_258;
wire [3:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_259;
wire [3:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_260;
wire [3:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_261;
wire [3:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_262;
wire [3:0] call_ret4_sp_prim_conv_sector_fu_37378_ap_return_263;
wire [11:0] grp_sp_best_tracks_fu_51719_ap_return_0;
wire [11:0] grp_sp_best_tracks_fu_51719_ap_return_1;
wire [11:0] grp_sp_best_tracks_fu_51719_ap_return_2;
wire [6:0] grp_sp_best_tracks_fu_51719_ap_return_3;
wire [6:0] grp_sp_best_tracks_fu_51719_ap_return_4;
wire [6:0] grp_sp_best_tracks_fu_51719_ap_return_5;
wire [3:0] grp_sp_best_tracks_fu_51719_ap_return_6;
wire [3:0] grp_sp_best_tracks_fu_51719_ap_return_7;
wire [3:0] grp_sp_best_tracks_fu_51719_ap_return_8;
wire [3:0] grp_sp_best_tracks_fu_51719_ap_return_9;
wire [3:0] grp_sp_best_tracks_fu_51719_ap_return_10;
wire [3:0] grp_sp_best_tracks_fu_51719_ap_return_11;
wire [3:0] grp_sp_best_tracks_fu_51719_ap_return_12;
wire [3:0] grp_sp_best_tracks_fu_51719_ap_return_13;
wire [3:0] grp_sp_best_tracks_fu_51719_ap_return_14;
wire [3:0] grp_sp_best_tracks_fu_51719_ap_return_15;
wire [3:0] grp_sp_best_tracks_fu_51719_ap_return_16;
wire [3:0] grp_sp_best_tracks_fu_51719_ap_return_17;
wire [11:0] grp_sp_best_tracks_fu_51719_ap_return_18;
wire [11:0] grp_sp_best_tracks_fu_51719_ap_return_19;
wire [11:0] grp_sp_best_tracks_fu_51719_ap_return_20;
wire [11:0] grp_sp_best_tracks_fu_51719_ap_return_21;
wire [11:0] grp_sp_best_tracks_fu_51719_ap_return_22;
wire [11:0] grp_sp_best_tracks_fu_51719_ap_return_23;
wire [11:0] grp_sp_best_tracks_fu_51719_ap_return_24;
wire [11:0] grp_sp_best_tracks_fu_51719_ap_return_25;
wire [11:0] grp_sp_best_tracks_fu_51719_ap_return_26;
wire [11:0] grp_sp_best_tracks_fu_51719_ap_return_27;
wire [11:0] grp_sp_best_tracks_fu_51719_ap_return_28;
wire [11:0] grp_sp_best_tracks_fu_51719_ap_return_29;
wire [11:0] grp_sp_best_tracks_fu_51719_ap_return_30;
wire [11:0] grp_sp_best_tracks_fu_51719_ap_return_31;
wire [11:0] grp_sp_best_tracks_fu_51719_ap_return_32;
wire [11:0] grp_sp_best_tracks_fu_51719_ap_return_33;
wire [11:0] grp_sp_best_tracks_fu_51719_ap_return_34;
wire [11:0] grp_sp_best_tracks_fu_51719_ap_return_35;
wire [6:0] grp_sp_best_tracks_fu_51719_ap_return_36;
wire [6:0] grp_sp_best_tracks_fu_51719_ap_return_37;
wire [6:0] grp_sp_best_tracks_fu_51719_ap_return_38;
wire [6:0] grp_sp_best_tracks_fu_51719_ap_return_39;
wire [6:0] grp_sp_best_tracks_fu_51719_ap_return_40;
wire [6:0] grp_sp_best_tracks_fu_51719_ap_return_41;
wire [6:0] grp_sp_best_tracks_fu_51719_ap_return_42;
wire [6:0] grp_sp_best_tracks_fu_51719_ap_return_43;
wire [6:0] grp_sp_best_tracks_fu_51719_ap_return_44;
wire [6:0] grp_sp_best_tracks_fu_51719_ap_return_45;
wire [6:0] grp_sp_best_tracks_fu_51719_ap_return_46;
wire [6:0] grp_sp_best_tracks_fu_51719_ap_return_47;
wire [6:0] grp_sp_best_tracks_fu_51719_ap_return_48;
wire [6:0] grp_sp_best_tracks_fu_51719_ap_return_49;
wire [6:0] grp_sp_best_tracks_fu_51719_ap_return_50;
wire [6:0] grp_sp_best_tracks_fu_51719_ap_return_51;
wire [6:0] grp_sp_best_tracks_fu_51719_ap_return_52;
wire [6:0] grp_sp_best_tracks_fu_51719_ap_return_53;
wire [5:0] grp_sp_best_tracks_fu_51719_ap_return_54;
wire [5:0] grp_sp_best_tracks_fu_51719_ap_return_55;
wire [5:0] grp_sp_best_tracks_fu_51719_ap_return_56;
wire [5:0] grp_sp_best_tracks_fu_51719_ap_return_57;
wire [5:0] grp_sp_best_tracks_fu_51719_ap_return_58;
wire [5:0] grp_sp_best_tracks_fu_51719_ap_return_59;
wire [6:0] grp_sp_best_tracks_fu_51719_ap_return_60;
wire [6:0] grp_sp_best_tracks_fu_51719_ap_return_61;
wire [6:0] grp_sp_best_tracks_fu_51719_ap_return_62;
wire [1:0] grp_sp_best_tracks_fu_51719_ap_return_63;
wire [1:0] grp_sp_best_tracks_fu_51719_ap_return_64;
wire [1:0] grp_sp_best_tracks_fu_51719_ap_return_65;
wire [1:0] grp_sp_best_tracks_fu_51719_ap_return_66;
wire [1:0] grp_sp_best_tracks_fu_51719_ap_return_67;
wire [1:0] grp_sp_best_tracks_fu_51719_ap_return_68;
wire [1:0] grp_sp_best_tracks_fu_51719_ap_return_69;
wire [1:0] grp_sp_best_tracks_fu_51719_ap_return_70;
wire [1:0] grp_sp_best_tracks_fu_51719_ap_return_71;
wire [1:0] grp_sp_best_tracks_fu_51719_ap_return_72;
wire [1:0] grp_sp_best_tracks_fu_51719_ap_return_73;
wire [1:0] grp_sp_best_tracks_fu_51719_ap_return_74;
wire [1:0] grp_sp_best_tracks_fu_51719_ap_return_75;
wire [1:0] grp_sp_best_tracks_fu_51719_ap_return_76;
wire [1:0] grp_sp_best_tracks_fu_51719_ap_return_77;
wire [1:0] grp_sp_best_tracks_fu_51719_ap_return_78;
wire [1:0] grp_sp_best_tracks_fu_51719_ap_return_79;
wire [1:0] grp_sp_best_tracks_fu_51719_ap_return_80;
wire [1:0] grp_sp_best_tracks_fu_51719_ap_return_81;
wire [1:0] grp_sp_best_tracks_fu_51719_ap_return_82;
wire [1:0] grp_sp_best_tracks_fu_51719_ap_return_83;
wire [1:0] grp_sp_best_tracks_fu_51719_ap_return_84;
wire [1:0] grp_sp_best_tracks_fu_51719_ap_return_85;
wire [1:0] grp_sp_best_tracks_fu_51719_ap_return_86;
wire [1:0] grp_sp_best_tracks_fu_51719_ap_return_87;
wire [1:0] grp_sp_best_tracks_fu_51719_ap_return_88;
wire [1:0] grp_sp_best_tracks_fu_51719_ap_return_89;
wire [1:0] grp_sp_best_tracks_fu_51719_ap_return_90;
wire [1:0] grp_sp_best_tracks_fu_51719_ap_return_91;
wire [1:0] grp_sp_best_tracks_fu_51719_ap_return_92;
wire [3:0] grp_sp_best_tracks_fu_51719_ap_return_93;
wire [3:0] grp_sp_best_tracks_fu_51719_ap_return_94;
wire [3:0] grp_sp_best_tracks_fu_51719_ap_return_95;
wire [3:0] grp_sp_best_tracks_fu_51719_ap_return_96;
wire [3:0] grp_sp_best_tracks_fu_51719_ap_return_97;
wire [3:0] grp_sp_best_tracks_fu_51719_ap_return_98;
wire [3:0] grp_sp_best_tracks_fu_51719_ap_return_99;
wire [3:0] grp_sp_best_tracks_fu_51719_ap_return_100;
wire [3:0] grp_sp_best_tracks_fu_51719_ap_return_101;
wire [3:0] grp_sp_best_tracks_fu_51719_ap_return_102;
wire [3:0] grp_sp_best_tracks_fu_51719_ap_return_103;
wire [3:0] grp_sp_best_tracks_fu_51719_ap_return_104;
wire [3:0] grp_sp_best_tracks_fu_51719_ap_return_105;
wire [3:0] grp_sp_best_tracks_fu_51719_ap_return_106;
wire [3:0] grp_sp_best_tracks_fu_51719_ap_return_107;
wire [4:0] grp_sp_best_tracks_fu_51719_ap_return_108;
wire [4:0] grp_sp_best_tracks_fu_51719_ap_return_109;
wire [4:0] grp_sp_best_tracks_fu_51719_ap_return_110;
wire [11:0] call_ret_sp_deltas_sector_fu_51987_ap_return_0;
wire [11:0] call_ret_sp_deltas_sector_fu_51987_ap_return_1;
wire [11:0] call_ret_sp_deltas_sector_fu_51987_ap_return_2;
wire [11:0] call_ret_sp_deltas_sector_fu_51987_ap_return_3;
wire [11:0] call_ret_sp_deltas_sector_fu_51987_ap_return_4;
wire [11:0] call_ret_sp_deltas_sector_fu_51987_ap_return_5;
wire [11:0] call_ret_sp_deltas_sector_fu_51987_ap_return_6;
wire [11:0] call_ret_sp_deltas_sector_fu_51987_ap_return_7;
wire [11:0] call_ret_sp_deltas_sector_fu_51987_ap_return_8;
wire [11:0] call_ret_sp_deltas_sector_fu_51987_ap_return_9;
wire [11:0] call_ret_sp_deltas_sector_fu_51987_ap_return_10;
wire [11:0] call_ret_sp_deltas_sector_fu_51987_ap_return_11;
wire [6:0] call_ret_sp_deltas_sector_fu_51987_ap_return_12;
wire [6:0] call_ret_sp_deltas_sector_fu_51987_ap_return_13;
wire [6:0] call_ret_sp_deltas_sector_fu_51987_ap_return_14;
wire [6:0] call_ret_sp_deltas_sector_fu_51987_ap_return_15;
wire [6:0] call_ret_sp_deltas_sector_fu_51987_ap_return_16;
wire [6:0] call_ret_sp_deltas_sector_fu_51987_ap_return_17;
wire [6:0] call_ret_sp_deltas_sector_fu_51987_ap_return_18;
wire [6:0] call_ret_sp_deltas_sector_fu_51987_ap_return_19;
wire [6:0] call_ret_sp_deltas_sector_fu_51987_ap_return_20;
wire [6:0] call_ret_sp_deltas_sector_fu_51987_ap_return_21;
wire [6:0] call_ret_sp_deltas_sector_fu_51987_ap_return_22;
wire [6:0] call_ret_sp_deltas_sector_fu_51987_ap_return_23;
wire [5:0] call_ret_sp_deltas_sector_fu_51987_ap_return_24;
wire [5:0] call_ret_sp_deltas_sector_fu_51987_ap_return_25;
wire [5:0] call_ret_sp_deltas_sector_fu_51987_ap_return_26;
wire [5:0] call_ret_sp_deltas_sector_fu_51987_ap_return_27;
wire [5:0] call_ret_sp_deltas_sector_fu_51987_ap_return_28;
wire [5:0] call_ret_sp_deltas_sector_fu_51987_ap_return_29;
wire [5:0] call_ret_sp_deltas_sector_fu_51987_ap_return_30;
wire [5:0] call_ret_sp_deltas_sector_fu_51987_ap_return_31;
wire [5:0] call_ret_sp_deltas_sector_fu_51987_ap_return_32;
wire [5:0] call_ret_sp_deltas_sector_fu_51987_ap_return_33;
wire [5:0] call_ret_sp_deltas_sector_fu_51987_ap_return_34;
wire [5:0] call_ret_sp_deltas_sector_fu_51987_ap_return_35;
wire [5:0] call_ret_sp_deltas_sector_fu_51987_ap_return_36;
wire [5:0] call_ret_sp_deltas_sector_fu_51987_ap_return_37;
wire [5:0] call_ret_sp_deltas_sector_fu_51987_ap_return_38;
wire [5:0] call_ret_sp_deltas_sector_fu_51987_ap_return_39;
wire [5:0] call_ret_sp_deltas_sector_fu_51987_ap_return_40;
wire [5:0] call_ret_sp_deltas_sector_fu_51987_ap_return_41;
wire [5:0] call_ret_sp_deltas_sector_fu_51987_ap_return_42;
wire [5:0] call_ret_sp_deltas_sector_fu_51987_ap_return_43;
wire [5:0] call_ret_sp_deltas_sector_fu_51987_ap_return_44;
wire [5:0] call_ret_sp_deltas_sector_fu_51987_ap_return_45;
wire [5:0] call_ret_sp_deltas_sector_fu_51987_ap_return_46;
wire [5:0] call_ret_sp_deltas_sector_fu_51987_ap_return_47;
wire [6:0] call_ret_sp_deltas_sector_fu_51987_ap_return_48;
wire [6:0] call_ret_sp_deltas_sector_fu_51987_ap_return_49;
wire [6:0] call_ret_sp_deltas_sector_fu_51987_ap_return_50;
wire [6:0] call_ret_sp_deltas_sector_fu_51987_ap_return_51;
wire [6:0] call_ret_sp_deltas_sector_fu_51987_ap_return_52;
wire [6:0] call_ret_sp_deltas_sector_fu_51987_ap_return_53;
wire [6:0] call_ret_sp_deltas_sector_fu_51987_ap_return_54;
wire [6:0] call_ret_sp_deltas_sector_fu_51987_ap_return_55;
wire [6:0] call_ret_sp_deltas_sector_fu_51987_ap_return_56;
wire [6:0] call_ret_sp_deltas_sector_fu_51987_ap_return_57;
wire [6:0] call_ret_sp_deltas_sector_fu_51987_ap_return_58;
wire [6:0] call_ret_sp_deltas_sector_fu_51987_ap_return_59;
wire [3:0] call_ret_sp_deltas_sector_fu_51987_ap_return_60;
wire [3:0] call_ret_sp_deltas_sector_fu_51987_ap_return_61;
wire [3:0] call_ret_sp_deltas_sector_fu_51987_ap_return_62;
wire [3:0] call_ret_sp_deltas_sector_fu_51987_ap_return_63;
wire [3:0] call_ret_sp_deltas_sector_fu_51987_ap_return_64;
wire [3:0] call_ret_sp_deltas_sector_fu_51987_ap_return_65;
wire [3:0] call_ret_sp_deltas_sector_fu_51987_ap_return_66;
wire [3:0] call_ret_sp_deltas_sector_fu_51987_ap_return_67;
wire [3:0] call_ret_sp_deltas_sector_fu_51987_ap_return_68;
wire [3:0] call_ret_sp_deltas_sector_fu_51987_ap_return_69;
wire [3:0] call_ret_sp_deltas_sector_fu_51987_ap_return_70;
wire [3:0] call_ret_sp_deltas_sector_fu_51987_ap_return_71;
wire [3:0] call_ret_sp_deltas_sector_fu_51987_ap_return_72;
wire [3:0] call_ret_sp_deltas_sector_fu_51987_ap_return_73;
wire [3:0] call_ret_sp_deltas_sector_fu_51987_ap_return_74;
wire [3:0] call_ret_sp_deltas_sector_fu_51987_ap_return_75;
wire [3:0] call_ret_sp_deltas_sector_fu_51987_ap_return_76;
wire [3:0] call_ret_sp_deltas_sector_fu_51987_ap_return_77;
wire [3:0] call_ret_sp_deltas_sector_fu_51987_ap_return_78;
wire [3:0] call_ret_sp_deltas_sector_fu_51987_ap_return_79;
wire [3:0] call_ret_sp_deltas_sector_fu_51987_ap_return_80;
wire [3:0] call_ret_sp_deltas_sector_fu_51987_ap_return_81;
wire [3:0] call_ret_sp_deltas_sector_fu_51987_ap_return_82;
wire [3:0] call_ret_sp_deltas_sector_fu_51987_ap_return_83;
wire [3:0] call_ret_sp_deltas_sector_fu_51987_ap_return_84;
wire [3:0] call_ret_sp_deltas_sector_fu_51987_ap_return_85;
wire [3:0] call_ret_sp_deltas_sector_fu_51987_ap_return_86;
wire [3:0] call_ret_sp_deltas_sector_fu_51987_ap_return_87;
wire [3:0] call_ret_sp_deltas_sector_fu_51987_ap_return_88;
wire [3:0] call_ret_sp_deltas_sector_fu_51987_ap_return_89;
wire [3:0] call_ret_sp_deltas_sector_fu_51987_ap_return_90;
wire [3:0] call_ret_sp_deltas_sector_fu_51987_ap_return_91;
wire [3:0] call_ret_sp_deltas_sector_fu_51987_ap_return_92;
wire [3:0] call_ret_sp_deltas_sector_fu_51987_ap_return_93;
wire [3:0] call_ret_sp_deltas_sector_fu_51987_ap_return_94;
wire [3:0] call_ret_sp_deltas_sector_fu_51987_ap_return_95;
wire [3:0] call_ret_sp_deltas_sector_fu_51987_ap_return_96;
wire [3:0] call_ret_sp_deltas_sector_fu_51987_ap_return_97;
wire [3:0] call_ret_sp_deltas_sector_fu_51987_ap_return_98;
wire [3:0] call_ret_sp_deltas_sector_fu_51987_ap_return_99;
wire [3:0] call_ret_sp_deltas_sector_fu_51987_ap_return_100;
wire [3:0] call_ret_sp_deltas_sector_fu_51987_ap_return_101;
wire [3:0] call_ret_sp_deltas_sector_fu_51987_ap_return_102;
wire [3:0] call_ret_sp_deltas_sector_fu_51987_ap_return_103;
wire [3:0] call_ret_sp_deltas_sector_fu_51987_ap_return_104;
wire [3:0] call_ret_sp_deltas_sector_fu_51987_ap_return_105;
wire [3:0] call_ret_sp_deltas_sector_fu_51987_ap_return_106;
wire [3:0] call_ret_sp_deltas_sector_fu_51987_ap_return_107;
wire [11:0] call_ret_sp_deltas_sector_fu_51987_ap_return_108;
wire [11:0] call_ret_sp_deltas_sector_fu_51987_ap_return_109;
wire [11:0] call_ret_sp_deltas_sector_fu_51987_ap_return_110;
wire [11:0] call_ret_sp_deltas_sector_fu_51987_ap_return_111;
wire [11:0] call_ret_sp_deltas_sector_fu_51987_ap_return_112;
wire [11:0] call_ret_sp_deltas_sector_fu_51987_ap_return_113;
wire [11:0] call_ret_sp_deltas_sector_fu_51987_ap_return_114;
wire [11:0] call_ret_sp_deltas_sector_fu_51987_ap_return_115;
wire [11:0] call_ret_sp_deltas_sector_fu_51987_ap_return_116;
wire [11:0] call_ret_sp_deltas_sector_fu_51987_ap_return_117;
wire [11:0] call_ret_sp_deltas_sector_fu_51987_ap_return_118;
wire [11:0] call_ret_sp_deltas_sector_fu_51987_ap_return_119;
wire [11:0] call_ret_sp_deltas_sector_fu_51987_ap_return_120;
wire [11:0] call_ret_sp_deltas_sector_fu_51987_ap_return_121;
wire [11:0] call_ret_sp_deltas_sector_fu_51987_ap_return_122;
wire [11:0] call_ret_sp_deltas_sector_fu_51987_ap_return_123;
wire [11:0] call_ret_sp_deltas_sector_fu_51987_ap_return_124;
wire [11:0] call_ret_sp_deltas_sector_fu_51987_ap_return_125;
wire [11:0] call_ret_sp_deltas_sector_fu_51987_ap_return_126;
wire [11:0] call_ret_sp_deltas_sector_fu_51987_ap_return_127;
wire [11:0] call_ret_sp_deltas_sector_fu_51987_ap_return_128;
wire [11:0] call_ret_sp_deltas_sector_fu_51987_ap_return_129;
wire [11:0] call_ret_sp_deltas_sector_fu_51987_ap_return_130;
wire [11:0] call_ret_sp_deltas_sector_fu_51987_ap_return_131;
wire [11:0] call_ret_sp_deltas_sector_fu_51987_ap_return_132;
wire [11:0] call_ret_sp_deltas_sector_fu_51987_ap_return_133;
wire [11:0] call_ret_sp_deltas_sector_fu_51987_ap_return_134;
wire [11:0] call_ret_sp_deltas_sector_fu_51987_ap_return_135;
wire [11:0] call_ret_sp_deltas_sector_fu_51987_ap_return_136;
wire [11:0] call_ret_sp_deltas_sector_fu_51987_ap_return_137;
wire [11:0] call_ret_sp_deltas_sector_fu_51987_ap_return_138;
wire [11:0] call_ret_sp_deltas_sector_fu_51987_ap_return_139;
wire [11:0] call_ret_sp_deltas_sector_fu_51987_ap_return_140;
wire [11:0] call_ret_sp_deltas_sector_fu_51987_ap_return_141;
wire [11:0] call_ret_sp_deltas_sector_fu_51987_ap_return_142;
wire [11:0] call_ret_sp_deltas_sector_fu_51987_ap_return_143;
wire [11:0] call_ret_sp_deltas_sector_fu_51987_ap_return_144;
wire [11:0] call_ret_sp_deltas_sector_fu_51987_ap_return_145;
wire [11:0] call_ret_sp_deltas_sector_fu_51987_ap_return_146;
wire [11:0] call_ret_sp_deltas_sector_fu_51987_ap_return_147;
wire [11:0] call_ret_sp_deltas_sector_fu_51987_ap_return_148;
wire [11:0] call_ret_sp_deltas_sector_fu_51987_ap_return_149;
wire [11:0] call_ret_sp_deltas_sector_fu_51987_ap_return_150;
wire [11:0] call_ret_sp_deltas_sector_fu_51987_ap_return_151;
wire [11:0] call_ret_sp_deltas_sector_fu_51987_ap_return_152;
wire [11:0] call_ret_sp_deltas_sector_fu_51987_ap_return_153;
wire [11:0] call_ret_sp_deltas_sector_fu_51987_ap_return_154;
wire [11:0] call_ret_sp_deltas_sector_fu_51987_ap_return_155;
wire [11:0] call_ret_sp_deltas_sector_fu_51987_ap_return_156;
wire [11:0] call_ret_sp_deltas_sector_fu_51987_ap_return_157;
wire [11:0] call_ret_sp_deltas_sector_fu_51987_ap_return_158;
wire [11:0] call_ret_sp_deltas_sector_fu_51987_ap_return_159;
wire [11:0] call_ret_sp_deltas_sector_fu_51987_ap_return_160;
wire [11:0] call_ret_sp_deltas_sector_fu_51987_ap_return_161;
wire [11:0] call_ret_sp_deltas_sector_fu_51987_ap_return_162;
wire [11:0] call_ret_sp_deltas_sector_fu_51987_ap_return_163;
wire [11:0] call_ret_sp_deltas_sector_fu_51987_ap_return_164;
wire [11:0] call_ret_sp_deltas_sector_fu_51987_ap_return_165;
wire [11:0] call_ret_sp_deltas_sector_fu_51987_ap_return_166;
wire [11:0] call_ret_sp_deltas_sector_fu_51987_ap_return_167;
wire [11:0] call_ret_sp_deltas_sector_fu_51987_ap_return_168;
wire [11:0] call_ret_sp_deltas_sector_fu_51987_ap_return_169;
wire [11:0] call_ret_sp_deltas_sector_fu_51987_ap_return_170;
wire [11:0] call_ret_sp_deltas_sector_fu_51987_ap_return_171;
wire [11:0] call_ret_sp_deltas_sector_fu_51987_ap_return_172;
wire [11:0] call_ret_sp_deltas_sector_fu_51987_ap_return_173;
wire [11:0] call_ret_sp_deltas_sector_fu_51987_ap_return_174;
wire [11:0] call_ret_sp_deltas_sector_fu_51987_ap_return_175;
wire [11:0] call_ret_sp_deltas_sector_fu_51987_ap_return_176;
wire [11:0] call_ret_sp_deltas_sector_fu_51987_ap_return_177;
wire [11:0] call_ret_sp_deltas_sector_fu_51987_ap_return_178;
wire [11:0] call_ret_sp_deltas_sector_fu_51987_ap_return_179;
wire [6:0] call_ret_sp_deltas_sector_fu_51987_ap_return_180;
wire [6:0] call_ret_sp_deltas_sector_fu_51987_ap_return_181;
wire [6:0] call_ret_sp_deltas_sector_fu_51987_ap_return_182;
wire [6:0] call_ret_sp_deltas_sector_fu_51987_ap_return_183;
wire [6:0] call_ret_sp_deltas_sector_fu_51987_ap_return_184;
wire [6:0] call_ret_sp_deltas_sector_fu_51987_ap_return_185;
wire [6:0] call_ret_sp_deltas_sector_fu_51987_ap_return_186;
wire [6:0] call_ret_sp_deltas_sector_fu_51987_ap_return_187;
wire [6:0] call_ret_sp_deltas_sector_fu_51987_ap_return_188;
wire [6:0] call_ret_sp_deltas_sector_fu_51987_ap_return_189;
wire [6:0] call_ret_sp_deltas_sector_fu_51987_ap_return_190;
wire [6:0] call_ret_sp_deltas_sector_fu_51987_ap_return_191;
wire [6:0] call_ret_sp_deltas_sector_fu_51987_ap_return_192;
wire [6:0] call_ret_sp_deltas_sector_fu_51987_ap_return_193;
wire [6:0] call_ret_sp_deltas_sector_fu_51987_ap_return_194;
wire [6:0] call_ret_sp_deltas_sector_fu_51987_ap_return_195;
wire [6:0] call_ret_sp_deltas_sector_fu_51987_ap_return_196;
wire [6:0] call_ret_sp_deltas_sector_fu_51987_ap_return_197;
wire [6:0] call_ret_sp_deltas_sector_fu_51987_ap_return_198;
wire [6:0] call_ret_sp_deltas_sector_fu_51987_ap_return_199;
wire [6:0] call_ret_sp_deltas_sector_fu_51987_ap_return_200;
wire [6:0] call_ret_sp_deltas_sector_fu_51987_ap_return_201;
wire [6:0] call_ret_sp_deltas_sector_fu_51987_ap_return_202;
wire [6:0] call_ret_sp_deltas_sector_fu_51987_ap_return_203;
wire [6:0] call_ret_sp_deltas_sector_fu_51987_ap_return_204;
wire [6:0] call_ret_sp_deltas_sector_fu_51987_ap_return_205;
wire [6:0] call_ret_sp_deltas_sector_fu_51987_ap_return_206;
wire [6:0] call_ret_sp_deltas_sector_fu_51987_ap_return_207;
wire [6:0] call_ret_sp_deltas_sector_fu_51987_ap_return_208;
wire [6:0] call_ret_sp_deltas_sector_fu_51987_ap_return_209;
wire [6:0] call_ret_sp_deltas_sector_fu_51987_ap_return_210;
wire [6:0] call_ret_sp_deltas_sector_fu_51987_ap_return_211;
wire [6:0] call_ret_sp_deltas_sector_fu_51987_ap_return_212;
wire [6:0] call_ret_sp_deltas_sector_fu_51987_ap_return_213;
wire [6:0] call_ret_sp_deltas_sector_fu_51987_ap_return_214;
wire [6:0] call_ret_sp_deltas_sector_fu_51987_ap_return_215;
wire [6:0] call_ret_sp_deltas_sector_fu_51987_ap_return_216;
wire [6:0] call_ret_sp_deltas_sector_fu_51987_ap_return_217;
wire [6:0] call_ret_sp_deltas_sector_fu_51987_ap_return_218;
wire [6:0] call_ret_sp_deltas_sector_fu_51987_ap_return_219;
wire [6:0] call_ret_sp_deltas_sector_fu_51987_ap_return_220;
wire [6:0] call_ret_sp_deltas_sector_fu_51987_ap_return_221;
wire [6:0] call_ret_sp_deltas_sector_fu_51987_ap_return_222;
wire [6:0] call_ret_sp_deltas_sector_fu_51987_ap_return_223;
wire [6:0] call_ret_sp_deltas_sector_fu_51987_ap_return_224;
wire [6:0] call_ret_sp_deltas_sector_fu_51987_ap_return_225;
wire [6:0] call_ret_sp_deltas_sector_fu_51987_ap_return_226;
wire [6:0] call_ret_sp_deltas_sector_fu_51987_ap_return_227;
wire [6:0] call_ret_sp_deltas_sector_fu_51987_ap_return_228;
wire [6:0] call_ret_sp_deltas_sector_fu_51987_ap_return_229;
wire [6:0] call_ret_sp_deltas_sector_fu_51987_ap_return_230;
wire [6:0] call_ret_sp_deltas_sector_fu_51987_ap_return_231;
wire [6:0] call_ret_sp_deltas_sector_fu_51987_ap_return_232;
wire [6:0] call_ret_sp_deltas_sector_fu_51987_ap_return_233;
wire [6:0] call_ret_sp_deltas_sector_fu_51987_ap_return_234;
wire [6:0] call_ret_sp_deltas_sector_fu_51987_ap_return_235;
wire [6:0] call_ret_sp_deltas_sector_fu_51987_ap_return_236;
wire [6:0] call_ret_sp_deltas_sector_fu_51987_ap_return_237;
wire [6:0] call_ret_sp_deltas_sector_fu_51987_ap_return_238;
wire [6:0] call_ret_sp_deltas_sector_fu_51987_ap_return_239;
wire [6:0] call_ret_sp_deltas_sector_fu_51987_ap_return_240;
wire [6:0] call_ret_sp_deltas_sector_fu_51987_ap_return_241;
wire [6:0] call_ret_sp_deltas_sector_fu_51987_ap_return_242;
wire [6:0] call_ret_sp_deltas_sector_fu_51987_ap_return_243;
wire [6:0] call_ret_sp_deltas_sector_fu_51987_ap_return_244;
wire [6:0] call_ret_sp_deltas_sector_fu_51987_ap_return_245;
wire [6:0] call_ret_sp_deltas_sector_fu_51987_ap_return_246;
wire [6:0] call_ret_sp_deltas_sector_fu_51987_ap_return_247;
wire [6:0] call_ret_sp_deltas_sector_fu_51987_ap_return_248;
wire [6:0] call_ret_sp_deltas_sector_fu_51987_ap_return_249;
wire [6:0] call_ret_sp_deltas_sector_fu_51987_ap_return_250;
wire [6:0] call_ret_sp_deltas_sector_fu_51987_ap_return_251;
wire [6:0] grp_sp_sort_sector_fu_52195_ap_return_0;
wire [6:0] grp_sp_sort_sector_fu_52195_ap_return_1;
wire [6:0] grp_sp_sort_sector_fu_52195_ap_return_2;
wire [6:0] grp_sp_sort_sector_fu_52195_ap_return_3;
wire [6:0] grp_sp_sort_sector_fu_52195_ap_return_4;
wire [6:0] grp_sp_sort_sector_fu_52195_ap_return_5;
wire [6:0] grp_sp_sort_sector_fu_52195_ap_return_6;
wire [6:0] grp_sp_sort_sector_fu_52195_ap_return_7;
wire [6:0] grp_sp_sort_sector_fu_52195_ap_return_8;
wire [6:0] grp_sp_sort_sector_fu_52195_ap_return_9;
wire [6:0] grp_sp_sort_sector_fu_52195_ap_return_10;
wire [6:0] grp_sp_sort_sector_fu_52195_ap_return_11;
wire [5:0] grp_sp_sort_sector_fu_52195_ap_return_12;
wire [5:0] grp_sp_sort_sector_fu_52195_ap_return_13;
wire [5:0] grp_sp_sort_sector_fu_52195_ap_return_14;
wire [5:0] grp_sp_sort_sector_fu_52195_ap_return_15;
wire [5:0] grp_sp_sort_sector_fu_52195_ap_return_16;
wire [5:0] grp_sp_sort_sector_fu_52195_ap_return_17;
wire [5:0] grp_sp_sort_sector_fu_52195_ap_return_18;
wire [5:0] grp_sp_sort_sector_fu_52195_ap_return_19;
wire [5:0] grp_sp_sort_sector_fu_52195_ap_return_20;
wire [5:0] grp_sp_sort_sector_fu_52195_ap_return_21;
wire [5:0] grp_sp_sort_sector_fu_52195_ap_return_22;
wire [5:0] grp_sp_sort_sector_fu_52195_ap_return_23;
wire [121:0] call_ret6_sp_zones_fu_52687_ap_return_0;
wire [121:0] call_ret6_sp_zones_fu_52687_ap_return_1;
wire [121:0] call_ret6_sp_zones_fu_52687_ap_return_2;
wire [121:0] call_ret6_sp_zones_fu_52687_ap_return_3;
wire [121:0] call_ret6_sp_zones_fu_52687_ap_return_4;
wire [121:0] call_ret6_sp_zones_fu_52687_ap_return_5;
wire [121:0] call_ret6_sp_zones_fu_52687_ap_return_6;
wire [121:0] call_ret6_sp_zones_fu_52687_ap_return_7;
wire [121:0] call_ret6_sp_zones_fu_52687_ap_return_8;
wire [121:0] call_ret6_sp_zones_fu_52687_ap_return_9;
wire [121:0] call_ret6_sp_zones_fu_52687_ap_return_10;
wire [121:0] call_ret6_sp_zones_fu_52687_ap_return_11;
wire [121:0] call_ret6_sp_zones_fu_52687_ap_return_12;
wire [121:0] call_ret6_sp_zones_fu_52687_ap_return_13;
wire [121:0] call_ret6_sp_zones_fu_52687_ap_return_14;
reg grp_sp_co_ord_delay_fu_52775_ap_start;
wire grp_sp_co_ord_delay_fu_52775_ap_done;
wire grp_sp_co_ord_delay_fu_52775_ap_idle;
wire grp_sp_co_ord_delay_fu_52775_ap_ready;
wire [11:0] grp_sp_co_ord_delay_fu_52775_ap_return_0;
wire [11:0] grp_sp_co_ord_delay_fu_52775_ap_return_1;
wire [11:0] grp_sp_co_ord_delay_fu_52775_ap_return_2;
wire [11:0] grp_sp_co_ord_delay_fu_52775_ap_return_3;
wire [11:0] grp_sp_co_ord_delay_fu_52775_ap_return_4;
wire [11:0] grp_sp_co_ord_delay_fu_52775_ap_return_5;
wire [11:0] grp_sp_co_ord_delay_fu_52775_ap_return_6;
wire [11:0] grp_sp_co_ord_delay_fu_52775_ap_return_7;
wire [11:0] grp_sp_co_ord_delay_fu_52775_ap_return_8;
wire [6:0] grp_sp_co_ord_delay_fu_52775_ap_return_9;
wire [6:0] grp_sp_co_ord_delay_fu_52775_ap_return_10;
wire [6:0] grp_sp_co_ord_delay_fu_52775_ap_return_11;
wire [6:0] grp_sp_co_ord_delay_fu_52775_ap_return_12;
wire [6:0] grp_sp_co_ord_delay_fu_52775_ap_return_13;
wire [6:0] grp_sp_co_ord_delay_fu_52775_ap_return_14;
wire [6:0] grp_sp_co_ord_delay_fu_52775_ap_return_15;
wire [6:0] grp_sp_co_ord_delay_fu_52775_ap_return_16;
wire [6:0] grp_sp_co_ord_delay_fu_52775_ap_return_17;
wire [6:0] grp_sp_co_ord_delay_fu_52775_ap_return_18;
wire [6:0] grp_sp_co_ord_delay_fu_52775_ap_return_19;
wire [6:0] grp_sp_co_ord_delay_fu_52775_ap_return_20;
wire [6:0] grp_sp_co_ord_delay_fu_52775_ap_return_21;
wire [6:0] grp_sp_co_ord_delay_fu_52775_ap_return_22;
wire [6:0] grp_sp_co_ord_delay_fu_52775_ap_return_23;
wire [6:0] grp_sp_co_ord_delay_fu_52775_ap_return_24;
wire [6:0] grp_sp_co_ord_delay_fu_52775_ap_return_25;
wire [6:0] grp_sp_co_ord_delay_fu_52775_ap_return_26;
wire [6:0] grp_sp_co_ord_delay_fu_52775_ap_return_27;
wire [6:0] grp_sp_co_ord_delay_fu_52775_ap_return_28;
wire [3:0] grp_sp_co_ord_delay_fu_52775_ap_return_29;
wire [3:0] grp_sp_co_ord_delay_fu_52775_ap_return_30;
wire [3:0] grp_sp_co_ord_delay_fu_52775_ap_return_31;
wire [3:0] grp_sp_co_ord_delay_fu_52775_ap_return_32;
wire [3:0] grp_sp_co_ord_delay_fu_52775_ap_return_33;
wire [3:0] grp_sp_co_ord_delay_fu_52775_ap_return_34;
wire [3:0] grp_sp_co_ord_delay_fu_52775_ap_return_35;
wire [3:0] grp_sp_co_ord_delay_fu_52775_ap_return_36;
wire [3:0] grp_sp_co_ord_delay_fu_52775_ap_return_37;
wire call_ret7_sp_extend_sector_fu_54039_ap_start;
wire call_ret7_sp_extend_sector_fu_54039_ap_done;
wire call_ret7_sp_extend_sector_fu_54039_ap_idle;
wire call_ret7_sp_extend_sector_fu_54039_ap_ready;
wire [121:0] call_ret7_sp_extend_sector_fu_54039_ap_return_0;
wire [121:0] call_ret7_sp_extend_sector_fu_54039_ap_return_1;
wire [121:0] call_ret7_sp_extend_sector_fu_54039_ap_return_2;
wire [121:0] call_ret7_sp_extend_sector_fu_54039_ap_return_3;
wire [121:0] call_ret7_sp_extend_sector_fu_54039_ap_return_4;
wire [121:0] call_ret7_sp_extend_sector_fu_54039_ap_return_5;
wire [121:0] call_ret7_sp_extend_sector_fu_54039_ap_return_6;
wire [121:0] call_ret7_sp_extend_sector_fu_54039_ap_return_7;
wire [121:0] call_ret7_sp_extend_sector_fu_54039_ap_return_8;
wire [121:0] call_ret7_sp_extend_sector_fu_54039_ap_return_9;
wire [121:0] call_ret7_sp_extend_sector_fu_54039_ap_return_10;
wire [121:0] call_ret7_sp_extend_sector_fu_54039_ap_return_11;
wire [121:0] call_ret7_sp_extend_sector_fu_54039_ap_return_12;
wire [121:0] call_ret7_sp_extend_sector_fu_54039_ap_return_13;
wire [121:0] call_ret7_sp_extend_sector_fu_54039_ap_return_14;
wire [121:0] call_ret7_sp_extend_sector_fu_54039_ap_return_15;
wire [121:0] call_ret7_sp_extend_sector_fu_54039_ap_return_16;
wire [121:0] call_ret7_sp_extend_sector_fu_54039_ap_return_17;
wire [121:0] call_ret7_sp_extend_sector_fu_54039_ap_return_18;
wire [121:0] call_ret7_sp_extend_sector_fu_54039_ap_return_19;
wire [2:0] grp_sp_ptlut_address_fu_54138_ap_return_0;
wire [2:0] grp_sp_ptlut_address_fu_54138_ap_return_1;
wire [31:0] grp_sp_ptlut_address_fu_54138_ap_return_2;
wire [31:0] grp_sp_ptlut_address_fu_54138_ap_return_3;
wire [31:0] grp_sp_ptlut_address_fu_54138_ap_return_4;
wire [7:0] grp_sp_ptlut_address_fu_54138_ap_return_5;
wire [7:0] grp_sp_ptlut_address_fu_54138_ap_return_6;
wire [7:0] grp_sp_ptlut_address_fu_54138_ap_return_7;
wire [3:0] grp_sp_ptlut_address_fu_54138_ap_return_8;
wire [3:0] grp_sp_ptlut_address_fu_54138_ap_return_9;
wire [3:0] grp_sp_ptlut_address_fu_54138_ap_return_10;
wire [29:0] grp_sp_ptlut_address_fu_54138_ap_return_11;
wire [29:0] grp_sp_ptlut_address_fu_54138_ap_return_12;
wire [29:0] grp_sp_ptlut_address_fu_54138_ap_return_13;
wire [8:0] grp_sp_ptlut_address_fu_54138_ap_return_14;
wire [8:0] grp_sp_ptlut_address_fu_54138_ap_return_15;
wire [8:0] grp_sp_ptlut_address_fu_54138_ap_return_16;
wire [3:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_0;
wire [3:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_1;
wire [3:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_2;
wire [3:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_3;
wire [3:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_4;
wire [3:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_5;
wire [3:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_6;
wire [3:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_7;
wire [3:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_8;
wire [3:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_9;
wire [3:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_10;
wire [3:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_11;
wire [11:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_12;
wire [11:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_13;
wire [11:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_14;
wire [11:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_15;
wire [11:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_16;
wire [11:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_17;
wire [11:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_18;
wire [11:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_19;
wire [11:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_20;
wire [11:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_21;
wire [11:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_22;
wire [11:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_23;
wire [11:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_24;
wire [11:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_25;
wire [11:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_26;
wire [11:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_27;
wire [11:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_28;
wire [11:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_29;
wire [11:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_30;
wire [11:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_31;
wire [11:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_32;
wire [11:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_33;
wire [11:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_34;
wire [11:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_35;
wire [11:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_36;
wire [11:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_37;
wire [11:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_38;
wire [11:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_39;
wire [11:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_40;
wire [11:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_41;
wire [11:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_42;
wire [11:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_43;
wire [11:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_44;
wire [11:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_45;
wire [11:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_46;
wire [11:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_47;
wire [11:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_48;
wire [11:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_49;
wire [11:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_50;
wire [11:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_51;
wire [11:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_52;
wire [11:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_53;
wire [11:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_54;
wire [11:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_55;
wire [11:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_56;
wire [11:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_57;
wire [11:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_58;
wire [11:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_59;
wire [3:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_60;
wire [3:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_61;
wire [3:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_62;
wire [3:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_63;
wire [3:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_64;
wire [3:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_65;
wire [3:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_66;
wire [3:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_67;
wire [3:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_68;
wire [3:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_69;
wire [3:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_70;
wire [3:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_71;
wire [3:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_72;
wire [3:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_73;
wire [3:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_74;
wire [3:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_75;
wire [3:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_76;
wire [3:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_77;
wire [3:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_78;
wire [3:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_79;
wire [3:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_80;
wire [3:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_81;
wire [3:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_82;
wire [3:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_83;
wire [3:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_84;
wire [3:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_85;
wire [3:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_86;
wire [3:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_87;
wire [3:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_88;
wire [3:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_89;
wire [3:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_90;
wire [3:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_91;
wire [3:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_92;
wire [3:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_93;
wire [3:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_94;
wire [3:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_95;
wire [3:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_96;
wire [3:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_97;
wire [3:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_98;
wire [3:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_99;
wire [3:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_100;
wire [3:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_101;
wire [3:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_102;
wire [3:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_103;
wire [3:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_104;
wire [3:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_105;
wire [3:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_106;
wire [3:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_107;
wire [6:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_108;
wire [6:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_109;
wire [6:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_110;
wire [6:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_111;
wire [6:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_112;
wire [6:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_113;
wire [6:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_114;
wire [6:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_115;
wire [6:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_116;
wire [6:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_117;
wire [6:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_118;
wire [6:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_119;
wire [6:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_120;
wire [6:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_121;
wire [6:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_122;
wire [6:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_123;
wire [6:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_124;
wire [6:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_125;
wire [6:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_126;
wire [6:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_127;
wire [6:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_128;
wire [6:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_129;
wire [6:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_130;
wire [6:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_131;
wire [6:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_132;
wire [6:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_133;
wire [6:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_134;
wire [6:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_135;
wire [6:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_136;
wire [6:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_137;
wire [6:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_138;
wire [6:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_139;
wire [6:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_140;
wire [6:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_141;
wire [6:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_142;
wire [6:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_143;
wire [6:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_144;
wire [6:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_145;
wire [6:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_146;
wire [6:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_147;
wire [6:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_148;
wire [6:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_149;
wire [6:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_150;
wire [6:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_151;
wire [6:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_152;
wire [6:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_153;
wire [6:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_154;
wire [6:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_155;
wire [6:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_156;
wire [6:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_157;
wire [6:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_158;
wire [6:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_159;
wire [6:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_160;
wire [6:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_161;
wire [6:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_162;
wire [6:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_163;
wire [6:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_164;
wire [6:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_165;
wire [6:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_166;
wire [6:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_167;
wire [6:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_168;
wire [6:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_169;
wire [6:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_170;
wire [6:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_171;
wire [6:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_172;
wire [6:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_173;
wire [6:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_174;
wire [6:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_175;
wire [6:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_176;
wire [6:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_177;
wire [6:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_178;
wire [6:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_179;
wire [6:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_180;
wire [6:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_181;
wire [6:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_182;
wire [6:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_183;
wire [6:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_184;
wire [6:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_185;
wire [6:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_186;
wire [6:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_187;
wire [6:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_188;
wire [6:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_189;
wire [6:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_190;
wire [6:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_191;
wire [6:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_192;
wire [6:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_193;
wire [6:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_194;
wire [6:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_195;
wire [6:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_196;
wire [6:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_197;
wire [6:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_198;
wire [6:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_199;
wire [6:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_200;
wire [6:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_201;
wire [6:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_202;
wire [6:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_203;
wire [6:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_204;
wire [6:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_205;
wire [6:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_206;
wire [6:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_207;
wire [6:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_208;
wire [6:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_209;
wire [6:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_210;
wire [6:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_211;
wire [6:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_212;
wire [6:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_213;
wire [6:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_214;
wire [6:0] call_ret1_sp_match_ph_seg_fu_54225_ap_return_215;
reg ap_reg_grp_sp_ph_pattern_sector_fu_28574_ap_start;
wire ap_reg_call_ret4_sp_prim_conv_sector_fu_37378_ap_start;
reg [0:0] ap_NS_fsm;
reg ap_sig_call_ret4_sp_prim_conv_sector_fu_37378_ap_start;
wire [1:0] tmp_146_fu_54267_p1;
wire ap_reg_grp_sp_co_ord_delay_fu_52775_ap_start;
reg ap_sig_grp_sp_co_ord_delay_fu_52775_ap_start;
reg ap_reg_call_ret7_sp_extend_sector_fu_54039_ap_start;
wire [0:0] ph_zone_t_0_0_V_fu_24838;
reg [121:0] ph_zone_t_0_1_V_fu_24842;
reg [121:0] ph_zone_t_0_2_V_fu_24846;
reg [121:0] ph_zone_t_0_3_V_fu_24850;
reg [121:0] ph_zone_t_0_4_V_fu_24854;
wire [0:0] ph_zone_t_1_0_V_fu_24858;
reg [121:0] ph_zone_t_1_1_V_fu_24862;
reg [121:0] ph_zone_t_1_2_V_fu_24866;
reg [121:0] ph_zone_t_1_3_V_fu_24870;
reg [121:0] ph_zone_t_1_4_V_fu_24874;
wire [0:0] ph_zone_t_2_0_V_fu_24878;
reg [121:0] ph_zone_t_2_1_V_fu_24882;
reg [121:0] ph_zone_t_2_2_V_fu_24886;
reg [121:0] ph_zone_t_2_3_V_fu_24890;
reg [121:0] ph_zone_t_2_4_V_fu_24894;
wire [0:0] ph_zone_t_3_0_V_fu_24898;
reg [121:0] ph_zone_t_3_1_V_fu_24902;
reg [121:0] ph_zone_t_3_2_V_fu_24906;
reg [121:0] ph_zone_t_3_3_V_fu_24910;
wire [0:0] ph_zone_t_3_4_V_fu_24914;
reg [121:0] ph_ext_t_0_0_V_fu_24918;
reg [121:0] ph_ext_t_0_1_V_fu_24922;
reg [121:0] ph_ext_t_0_2_V_fu_24926;
reg [121:0] ph_ext_t_0_3_V_fu_24930;
reg [121:0] ph_ext_t_0_4_V_fu_24934;
reg [121:0] ph_ext_t_1_0_V_fu_24938;
reg [121:0] ph_ext_t_1_1_V_fu_24942;
reg [121:0] ph_ext_t_1_2_V_fu_24946;
reg [121:0] ph_ext_t_1_3_V_fu_24950;
reg [121:0] ph_ext_t_1_4_V_fu_24954;
reg [121:0] ph_ext_t_2_0_V_fu_24958;
reg [121:0] ph_ext_t_2_1_V_fu_24962;
reg [121:0] ph_ext_t_2_2_V_fu_24966;
reg [121:0] ph_ext_t_2_3_V_fu_24970;
reg [121:0] ph_ext_t_2_4_V_fu_24974;
reg [121:0] ph_ext_t_3_0_V_fu_24978;
reg [121:0] ph_ext_t_3_1_V_fu_24982;
reg [121:0] ph_ext_t_3_2_V_fu_24986;
reg [121:0] ph_ext_t_3_3_V_fu_24990;
reg [121:0] ph_ext_t_3_4_V_fu_24994;
wire [121:0] extLd_fu_61061_p1;
wire [121:0] extLd1_fu_61105_p1;
wire [121:0] extLd2_fu_61149_p1;
wire [121:0] extLd3_fu_61193_p1;
wire [121:0] extLd4_fu_61229_p1;
wire ap_sig_pprstidle_pp0;
// power-on initialization
initial begin
#0 ap_reg_ppiten_pp0_it4 = 1'b0;
#0 ap_reg_ppiten_pp0_it1 = 1'b0;
#0 ap_reg_ppiten_pp0_it2 = 1'b0;
#0 ap_reg_ppiten_pp0_it3 = 1'b0;
#0 ap_reg_ppiten_pp0_it5 = 1'b0;
#0 ap_reg_ppiten_pp0_it6 = 1'b0;
#0 ap_reg_ppiten_pp0_it7 = 1'b0;
#0 ap_reg_ppiten_pp0_it8 = 1'b0;
#0 ap_reg_ppiten_pp0_it9 = 1'b0;
#0 ap_reg_ppiten_pp0_it10 = 1'b0;
#0 ap_CS_fsm = 1'b1;
#0 ap_reg_grp_sp_ph_pattern_sector_fu_28574_ap_start = 1'b0;
#0 ap_reg_call_ret7_sp_extend_sector_fu_54039_ap_start = 1'b0;
end
sp_ph_pattern_sector grp_sp_ph_pattern_sector_fu_28574(
.ap_clk(ap_clk),
.ap_rst(ap_rst),
.ap_start(grp_sp_ph_pattern_sector_fu_28574_ap_start),
.ap_done(grp_sp_ph_pattern_sector_fu_28574_ap_done),
.ap_idle(grp_sp_ph_pattern_sector_fu_28574_ap_idle),
.ap_ready(grp_sp_ph_pattern_sector_fu_28574_ap_ready),
.st_0_1_V_read(call_ret7_sp_extend_sector_fu_54039_ap_return_1),
.st_0_2_V_read(call_ret7_sp_extend_sector_fu_54039_ap_return_2),
.st_0_3_V_read(call_ret7_sp_extend_sector_fu_54039_ap_return_3),
.st_0_4_V_read(call_ret7_sp_extend_sector_fu_54039_ap_return_4),
.st_1_1_V_read(call_ret7_sp_extend_sector_fu_54039_ap_return_6),
.st_1_2_V_read(call_ret7_sp_extend_sector_fu_54039_ap_return_7),
.st_1_3_V_read(call_ret7_sp_extend_sector_fu_54039_ap_return_8),
.st_1_4_V_read(call_ret7_sp_extend_sector_fu_54039_ap_return_9),
.st_2_1_V_read(call_ret7_sp_extend_sector_fu_54039_ap_return_11),
.st_2_2_V_read(call_ret7_sp_extend_sector_fu_54039_ap_return_12),
.st_2_3_V_read(call_ret7_sp_extend_sector_fu_54039_ap_return_13),
.st_2_4_V_read(call_ret7_sp_extend_sector_fu_54039_ap_return_14),
.st_3_1_V_read(call_ret7_sp_extend_sector_fu_54039_ap_return_16),
.st_3_2_V_read(call_ret7_sp_extend_sector_fu_54039_ap_return_17),
.st_3_3_V_read(call_ret7_sp_extend_sector_fu_54039_ap_return_18),
.st_3_4_V_read(call_ret7_sp_extend_sector_fu_54039_ap_return_19),
.ap_return_0(grp_sp_ph_pattern_sector_fu_28574_ap_return_0),
.ap_return_1(grp_sp_ph_pattern_sector_fu_28574_ap_return_1),
.ap_return_2(grp_sp_ph_pattern_sector_fu_28574_ap_return_2),
.ap_return_3(grp_sp_ph_pattern_sector_fu_28574_ap_return_3),
.ap_return_4(grp_sp_ph_pattern_sector_fu_28574_ap_return_4),
.ap_return_5(grp_sp_ph_pattern_sector_fu_28574_ap_return_5),
.ap_return_6(grp_sp_ph_pattern_sector_fu_28574_ap_return_6),
.ap_return_7(grp_sp_ph_pattern_sector_fu_28574_ap_return_7),
.ap_return_8(grp_sp_ph_pattern_sector_fu_28574_ap_return_8),
.ap_return_9(grp_sp_ph_pattern_sector_fu_28574_ap_return_9),
.ap_return_10(grp_sp_ph_pattern_sector_fu_28574_ap_return_10),
.ap_return_11(grp_sp_ph_pattern_sector_fu_28574_ap_return_11),
.ap_return_12(grp_sp_ph_pattern_sector_fu_28574_ap_return_12),
.ap_return_13(grp_sp_ph_pattern_sector_fu_28574_ap_return_13),
.ap_return_14(grp_sp_ph_pattern_sector_fu_28574_ap_return_14),
.ap_return_15(grp_sp_ph_pattern_sector_fu_28574_ap_return_15),
.ap_return_16(grp_sp_ph_pattern_sector_fu_28574_ap_return_16),
.ap_return_17(grp_sp_ph_pattern_sector_fu_28574_ap_return_17),
.ap_return_18(grp_sp_ph_pattern_sector_fu_28574_ap_return_18),
.ap_return_19(grp_sp_ph_pattern_sector_fu_28574_ap_return_19),
.ap_return_20(grp_sp_ph_pattern_sector_fu_28574_ap_return_20),
.ap_return_21(grp_sp_ph_pattern_sector_fu_28574_ap_return_21),
.ap_return_22(grp_sp_ph_pattern_sector_fu_28574_ap_return_22),
.ap_return_23(grp_sp_ph_pattern_sector_fu_28574_ap_return_23),
.ap_return_24(grp_sp_ph_pattern_sector_fu_28574_ap_return_24),
.ap_return_25(grp_sp_ph_pattern_sector_fu_28574_ap_return_25),
.ap_return_26(grp_sp_ph_pattern_sector_fu_28574_ap_return_26),
.ap_return_27(grp_sp_ph_pattern_sector_fu_28574_ap_return_27),
.ap_return_28(grp_sp_ph_pattern_sector_fu_28574_ap_return_28),
.ap_return_29(grp_sp_ph_pattern_sector_fu_28574_ap_return_29),
.ap_return_30(grp_sp_ph_pattern_sector_fu_28574_ap_return_30),
.ap_return_31(grp_sp_ph_pattern_sector_fu_28574_ap_return_31),
.ap_return_32(grp_sp_ph_pattern_sector_fu_28574_ap_return_32),
.ap_return_33(grp_sp_ph_pattern_sector_fu_28574_ap_return_33),
.ap_return_34(grp_sp_ph_pattern_sector_fu_28574_ap_return_34),
.ap_return_35(grp_sp_ph_pattern_sector_fu_28574_ap_return_35),
.ap_return_36(grp_sp_ph_pattern_sector_fu_28574_ap_return_36),
.ap_return_37(grp_sp_ph_pattern_sector_fu_28574_ap_return_37),
.ap_return_38(grp_sp_ph_pattern_sector_fu_28574_ap_return_38),
.ap_return_39(grp_sp_ph_pattern_sector_fu_28574_ap_return_39),
.ap_return_40(grp_sp_ph_pattern_sector_fu_28574_ap_return_40),
.ap_return_41(grp_sp_ph_pattern_sector_fu_28574_ap_return_41),
.ap_return_42(grp_sp_ph_pattern_sector_fu_28574_ap_return_42),
.ap_return_43(grp_sp_ph_pattern_sector_fu_28574_ap_return_43),
.ap_return_44(grp_sp_ph_pattern_sector_fu_28574_ap_return_44),
.ap_return_45(grp_sp_ph_pattern_sector_fu_28574_ap_return_45),
.ap_return_46(grp_sp_ph_pattern_sector_fu_28574_ap_return_46),
.ap_return_47(grp_sp_ph_pattern_sector_fu_28574_ap_return_47),
.ap_return_48(grp_sp_ph_pattern_sector_fu_28574_ap_return_48),
.ap_return_49(grp_sp_ph_pattern_sector_fu_28574_ap_return_49),
.ap_return_50(grp_sp_ph_pattern_sector_fu_28574_ap_return_50),
.ap_return_51(grp_sp_ph_pattern_sector_fu_28574_ap_return_51),
.ap_return_52(grp_sp_ph_pattern_sector_fu_28574_ap_return_52),
.ap_return_53(grp_sp_ph_pattern_sector_fu_28574_ap_return_53),
.ap_return_54(grp_sp_ph_pattern_sector_fu_28574_ap_return_54),
.ap_return_55(grp_sp_ph_pattern_sector_fu_28574_ap_return_55),
.ap_return_56(grp_sp_ph_pattern_sector_fu_28574_ap_return_56),
.ap_return_57(grp_sp_ph_pattern_sector_fu_28574_ap_return_57),
.ap_return_58(grp_sp_ph_pattern_sector_fu_28574_ap_return_58),
.ap_return_59(grp_sp_ph_pattern_sector_fu_28574_ap_return_59),
.ap_return_60(grp_sp_ph_pattern_sector_fu_28574_ap_return_60),
.ap_return_61(grp_sp_ph_pattern_sector_fu_28574_ap_return_61),
.ap_return_62(grp_sp_ph_pattern_sector_fu_28574_ap_return_62),
.ap_return_63(grp_sp_ph_pattern_sector_fu_28574_ap_return_63),
.ap_return_64(grp_sp_ph_pattern_sector_fu_28574_ap_return_64),
.ap_return_65(grp_sp_ph_pattern_sector_fu_28574_ap_return_65),
.ap_return_66(grp_sp_ph_pattern_sector_fu_28574_ap_return_66),
.ap_return_67(grp_sp_ph_pattern_sector_fu_28574_ap_return_67),
.ap_return_68(grp_sp_ph_pattern_sector_fu_28574_ap_return_68),
.ap_return_69(grp_sp_ph_pattern_sector_fu_28574_ap_return_69),
.ap_return_70(grp_sp_ph_pattern_sector_fu_28574_ap_return_70),
.ap_return_71(grp_sp_ph_pattern_sector_fu_28574_ap_return_71),
.ap_return_72(grp_sp_ph_pattern_sector_fu_28574_ap_return_72),
.ap_return_73(grp_sp_ph_pattern_sector_fu_28574_ap_return_73),
.ap_return_74(grp_sp_ph_pattern_sector_fu_28574_ap_return_74),
.ap_return_75(grp_sp_ph_pattern_sector_fu_28574_ap_return_75),
.ap_return_76(grp_sp_ph_pattern_sector_fu_28574_ap_return_76),
.ap_return_77(grp_sp_ph_pattern_sector_fu_28574_ap_return_77),
.ap_return_78(grp_sp_ph_pattern_sector_fu_28574_ap_return_78),
.ap_return_79(grp_sp_ph_pattern_sector_fu_28574_ap_return_79),
.ap_return_80(grp_sp_ph_pattern_sector_fu_28574_ap_return_80),
.ap_return_81(grp_sp_ph_pattern_sector_fu_28574_ap_return_81),
.ap_return_82(grp_sp_ph_pattern_sector_fu_28574_ap_return_82),
.ap_return_83(grp_sp_ph_pattern_sector_fu_28574_ap_return_83),
.ap_return_84(grp_sp_ph_pattern_sector_fu_28574_ap_return_84),
.ap_return_85(grp_sp_ph_pattern_sector_fu_28574_ap_return_85),
.ap_return_86(grp_sp_ph_pattern_sector_fu_28574_ap_return_86),
.ap_return_87(grp_sp_ph_pattern_sector_fu_28574_ap_return_87),
.ap_return_88(grp_sp_ph_pattern_sector_fu_28574_ap_return_88),
.ap_return_89(grp_sp_ph_pattern_sector_fu_28574_ap_return_89),
.ap_return_90(grp_sp_ph_pattern_sector_fu_28574_ap_return_90),
.ap_return_91(grp_sp_ph_pattern_sector_fu_28574_ap_return_91),
.ap_return_92(grp_sp_ph_pattern_sector_fu_28574_ap_return_92),
.ap_return_93(grp_sp_ph_pattern_sector_fu_28574_ap_return_93),
.ap_return_94(grp_sp_ph_pattern_sector_fu_28574_ap_return_94),
.ap_return_95(grp_sp_ph_pattern_sector_fu_28574_ap_return_95),
.ap_return_96(grp_sp_ph_pattern_sector_fu_28574_ap_return_96),
.ap_return_97(grp_sp_ph_pattern_sector_fu_28574_ap_return_97),
.ap_return_98(grp_sp_ph_pattern_sector_fu_28574_ap_return_98),
.ap_return_99(grp_sp_ph_pattern_sector_fu_28574_ap_return_99),
.ap_return_100(grp_sp_ph_pattern_sector_fu_28574_ap_return_100),
.ap_return_101(grp_sp_ph_pattern_sector_fu_28574_ap_return_101),
.ap_return_102(grp_sp_ph_pattern_sector_fu_28574_ap_return_102),
.ap_return_103(grp_sp_ph_pattern_sector_fu_28574_ap_return_103),
.ap_return_104(grp_sp_ph_pattern_sector_fu_28574_ap_return_104),
.ap_return_105(grp_sp_ph_pattern_sector_fu_28574_ap_return_105),
.ap_return_106(grp_sp_ph_pattern_sector_fu_28574_ap_return_106),
.ap_return_107(grp_sp_ph_pattern_sector_fu_28574_ap_return_107),
.ap_return_108(grp_sp_ph_pattern_sector_fu_28574_ap_return_108),
.ap_return_109(grp_sp_ph_pattern_sector_fu_28574_ap_return_109),
.ap_return_110(grp_sp_ph_pattern_sector_fu_28574_ap_return_110),
.ap_return_111(grp_sp_ph_pattern_sector_fu_28574_ap_return_111),
.ap_return_112(grp_sp_ph_pattern_sector_fu_28574_ap_return_112),
.ap_return_113(grp_sp_ph_pattern_sector_fu_28574_ap_return_113),
.ap_return_114(grp_sp_ph_pattern_sector_fu_28574_ap_return_114),
.ap_return_115(grp_sp_ph_pattern_sector_fu_28574_ap_return_115),
.ap_return_116(grp_sp_ph_pattern_sector_fu_28574_ap_return_116),
.ap_return_117(grp_sp_ph_pattern_sector_fu_28574_ap_return_117),
.ap_return_118(grp_sp_ph_pattern_sector_fu_28574_ap_return_118),
.ap_return_119(grp_sp_ph_pattern_sector_fu_28574_ap_return_119),
.ap_return_120(grp_sp_ph_pattern_sector_fu_28574_ap_return_120),
.ap_return_121(grp_sp_ph_pattern_sector_fu_28574_ap_return_121),
.ap_return_122(grp_sp_ph_pattern_sector_fu_28574_ap_return_122),
.ap_return_123(grp_sp_ph_pattern_sector_fu_28574_ap_return_123),
.ap_return_124(grp_sp_ph_pattern_sector_fu_28574_ap_return_124),
.ap_return_125(grp_sp_ph_pattern_sector_fu_28574_ap_return_125),
.ap_return_126(grp_sp_ph_pattern_sector_fu_28574_ap_return_126),
.ap_return_127(grp_sp_ph_pattern_sector_fu_28574_ap_return_127),
.ap_return_128(grp_sp_ph_pattern_sector_fu_28574_ap_return_128),
.ap_return_129(grp_sp_ph_pattern_sector_fu_28574_ap_return_129),
.ap_return_130(grp_sp_ph_pattern_sector_fu_28574_ap_return_130),
.ap_return_131(grp_sp_ph_pattern_sector_fu_28574_ap_return_131),
.ap_return_132(grp_sp_ph_pattern_sector_fu_28574_ap_return_132),
.ap_return_133(grp_sp_ph_pattern_sector_fu_28574_ap_return_133),
.ap_return_134(grp_sp_ph_pattern_sector_fu_28574_ap_return_134),
.ap_return_135(grp_sp_ph_pattern_sector_fu_28574_ap_return_135),
.ap_return_136(grp_sp_ph_pattern_sector_fu_28574_ap_return_136),
.ap_return_137(grp_sp_ph_pattern_sector_fu_28574_ap_return_137),
.ap_return_138(grp_sp_ph_pattern_sector_fu_28574_ap_return_138),
.ap_return_139(grp_sp_ph_pattern_sector_fu_28574_ap_return_139),
.ap_return_140(grp_sp_ph_pattern_sector_fu_28574_ap_return_140),
.ap_return_141(grp_sp_ph_pattern_sector_fu_28574_ap_return_141),
.ap_return_142(grp_sp_ph_pattern_sector_fu_28574_ap_return_142),
.ap_return_143(grp_sp_ph_pattern_sector_fu_28574_ap_return_143),
.ap_return_144(grp_sp_ph_pattern_sector_fu_28574_ap_return_144),
.ap_return_145(grp_sp_ph_pattern_sector_fu_28574_ap_return_145),
.ap_return_146(grp_sp_ph_pattern_sector_fu_28574_ap_return_146),
.ap_return_147(grp_sp_ph_pattern_sector_fu_28574_ap_return_147),
.ap_return_148(grp_sp_ph_pattern_sector_fu_28574_ap_return_148),
.ap_return_149(grp_sp_ph_pattern_sector_fu_28574_ap_return_149),
.ap_return_150(grp_sp_ph_pattern_sector_fu_28574_ap_return_150),
.ap_return_151(grp_sp_ph_pattern_sector_fu_28574_ap_return_151),
.ap_return_152(grp_sp_ph_pattern_sector_fu_28574_ap_return_152),
.ap_return_153(grp_sp_ph_pattern_sector_fu_28574_ap_return_153),
.ap_return_154(grp_sp_ph_pattern_sector_fu_28574_ap_return_154),
.ap_return_155(grp_sp_ph_pattern_sector_fu_28574_ap_return_155),
.ap_return_156(grp_sp_ph_pattern_sector_fu_28574_ap_return_156),
.ap_return_157(grp_sp_ph_pattern_sector_fu_28574_ap_return_157),
.ap_return_158(grp_sp_ph_pattern_sector_fu_28574_ap_return_158),
.ap_return_159(grp_sp_ph_pattern_sector_fu_28574_ap_return_159),
.ap_return_160(grp_sp_ph_pattern_sector_fu_28574_ap_return_160),
.ap_return_161(grp_sp_ph_pattern_sector_fu_28574_ap_return_161),
.ap_return_162(grp_sp_ph_pattern_sector_fu_28574_ap_return_162),
.ap_return_163(grp_sp_ph_pattern_sector_fu_28574_ap_return_163),
.ap_return_164(grp_sp_ph_pattern_sector_fu_28574_ap_return_164),
.ap_return_165(grp_sp_ph_pattern_sector_fu_28574_ap_return_165),
.ap_return_166(grp_sp_ph_pattern_sector_fu_28574_ap_return_166),
.ap_return_167(grp_sp_ph_pattern_sector_fu_28574_ap_return_167),
.ap_return_168(grp_sp_ph_pattern_sector_fu_28574_ap_return_168),
.ap_return_169(grp_sp_ph_pattern_sector_fu_28574_ap_return_169),
.ap_return_170(grp_sp_ph_pattern_sector_fu_28574_ap_return_170),
.ap_return_171(grp_sp_ph_pattern_sector_fu_28574_ap_return_171),
.ap_return_172(grp_sp_ph_pattern_sector_fu_28574_ap_return_172),
.ap_return_173(grp_sp_ph_pattern_sector_fu_28574_ap_return_173),
.ap_return_174(grp_sp_ph_pattern_sector_fu_28574_ap_return_174),
.ap_return_175(grp_sp_ph_pattern_sector_fu_28574_ap_return_175),
.ap_return_176(grp_sp_ph_pattern_sector_fu_28574_ap_return_176),
.ap_return_177(grp_sp_ph_pattern_sector_fu_28574_ap_return_177),
.ap_return_178(grp_sp_ph_pattern_sector_fu_28574_ap_return_178),
.ap_return_179(grp_sp_ph_pattern_sector_fu_28574_ap_return_179),
.ap_return_180(grp_sp_ph_pattern_sector_fu_28574_ap_return_180),
.ap_return_181(grp_sp_ph_pattern_sector_fu_28574_ap_return_181),
.ap_return_182(grp_sp_ph_pattern_sector_fu_28574_ap_return_182),
.ap_return_183(grp_sp_ph_pattern_sector_fu_28574_ap_return_183),
.ap_return_184(grp_sp_ph_pattern_sector_fu_28574_ap_return_184),
.ap_return_185(grp_sp_ph_pattern_sector_fu_28574_ap_return_185),
.ap_return_186(grp_sp_ph_pattern_sector_fu_28574_ap_return_186),
.ap_return_187(grp_sp_ph_pattern_sector_fu_28574_ap_return_187),
.ap_return_188(grp_sp_ph_pattern_sector_fu_28574_ap_return_188),
.ap_return_189(grp_sp_ph_pattern_sector_fu_28574_ap_return_189),
.ap_return_190(grp_sp_ph_pattern_sector_fu_28574_ap_return_190),
.ap_return_191(grp_sp_ph_pattern_sector_fu_28574_ap_return_191),
.ap_return_192(grp_sp_ph_pattern_sector_fu_28574_ap_return_192),
.ap_return_193(grp_sp_ph_pattern_sector_fu_28574_ap_return_193),
.ap_return_194(grp_sp_ph_pattern_sector_fu_28574_ap_return_194),
.ap_return_195(grp_sp_ph_pattern_sector_fu_28574_ap_return_195),
.ap_return_196(grp_sp_ph_pattern_sector_fu_28574_ap_return_196),
.ap_return_197(grp_sp_ph_pattern_sector_fu_28574_ap_return_197),
.ap_return_198(grp_sp_ph_pattern_sector_fu_28574_ap_return_198),
.ap_return_199(grp_sp_ph_pattern_sector_fu_28574_ap_return_199),
.ap_return_200(grp_sp_ph_pattern_sector_fu_28574_ap_return_200),
.ap_return_201(grp_sp_ph_pattern_sector_fu_28574_ap_return_201),
.ap_return_202(grp_sp_ph_pattern_sector_fu_28574_ap_return_202),
.ap_return_203(grp_sp_ph_pattern_sector_fu_28574_ap_return_203),
.ap_return_204(grp_sp_ph_pattern_sector_fu_28574_ap_return_204),
.ap_return_205(grp_sp_ph_pattern_sector_fu_28574_ap_return_205),
.ap_return_206(grp_sp_ph_pattern_sector_fu_28574_ap_return_206),
.ap_return_207(grp_sp_ph_pattern_sector_fu_28574_ap_return_207),
.ap_return_208(grp_sp_ph_pattern_sector_fu_28574_ap_return_208),
.ap_return_209(grp_sp_ph_pattern_sector_fu_28574_ap_return_209),
.ap_return_210(grp_sp_ph_pattern_sector_fu_28574_ap_return_210),
.ap_return_211(grp_sp_ph_pattern_sector_fu_28574_ap_return_211),
.ap_return_212(grp_sp_ph_pattern_sector_fu_28574_ap_return_212),
.ap_return_213(grp_sp_ph_pattern_sector_fu_28574_ap_return_213),
.ap_return_214(grp_sp_ph_pattern_sector_fu_28574_ap_return_214),
.ap_return_215(grp_sp_ph_pattern_sector_fu_28574_ap_return_215),
.ap_return_216(grp_sp_ph_pattern_sector_fu_28574_ap_return_216),
.ap_return_217(grp_sp_ph_pattern_sector_fu_28574_ap_return_217),
.ap_return_218(grp_sp_ph_pattern_sector_fu_28574_ap_return_218),
.ap_return_219(grp_sp_ph_pattern_sector_fu_28574_ap_return_219),
.ap_return_220(grp_sp_ph_pattern_sector_fu_28574_ap_return_220),
.ap_return_221(grp_sp_ph_pattern_sector_fu_28574_ap_return_221),
.ap_return_222(grp_sp_ph_pattern_sector_fu_28574_ap_return_222),
.ap_return_223(grp_sp_ph_pattern_sector_fu_28574_ap_return_223),
.ap_return_224(grp_sp_ph_pattern_sector_fu_28574_ap_return_224),
.ap_return_225(grp_sp_ph_pattern_sector_fu_28574_ap_return_225),
.ap_return_226(grp_sp_ph_pattern_sector_fu_28574_ap_return_226),
.ap_return_227(grp_sp_ph_pattern_sector_fu_28574_ap_return_227),
.ap_return_228(grp_sp_ph_pattern_sector_fu_28574_ap_return_228),
.ap_return_229(grp_sp_ph_pattern_sector_fu_28574_ap_return_229),
.ap_return_230(grp_sp_ph_pattern_sector_fu_28574_ap_return_230),
.ap_return_231(grp_sp_ph_pattern_sector_fu_28574_ap_return_231),
.ap_return_232(grp_sp_ph_pattern_sector_fu_28574_ap_return_232),
.ap_return_233(grp_sp_ph_pattern_sector_fu_28574_ap_return_233),
.ap_return_234(grp_sp_ph_pattern_sector_fu_28574_ap_return_234),
.ap_return_235(grp_sp_ph_pattern_sector_fu_28574_ap_return_235),
.ap_return_236(grp_sp_ph_pattern_sector_fu_28574_ap_return_236),
.ap_return_237(grp_sp_ph_pattern_sector_fu_28574_ap_return_237),
.ap_return_238(grp_sp_ph_pattern_sector_fu_28574_ap_return_238),
.ap_return_239(grp_sp_ph_pattern_sector_fu_28574_ap_return_239),
.ap_return_240(grp_sp_ph_pattern_sector_fu_28574_ap_return_240),
.ap_return_241(grp_sp_ph_pattern_sector_fu_28574_ap_return_241),
.ap_return_242(grp_sp_ph_pattern_sector_fu_28574_ap_return_242),
.ap_return_243(grp_sp_ph_pattern_sector_fu_28574_ap_return_243),
.ap_return_244(grp_sp_ph_pattern_sector_fu_28574_ap_return_244),
.ap_return_245(grp_sp_ph_pattern_sector_fu_28574_ap_return_245),
.ap_return_246(grp_sp_ph_pattern_sector_fu_28574_ap_return_246),
.ap_return_247(grp_sp_ph_pattern_sector_fu_28574_ap_return_247),
.ap_return_248(grp_sp_ph_pattern_sector_fu_28574_ap_return_248),
.ap_return_249(grp_sp_ph_pattern_sector_fu_28574_ap_return_249),
.ap_return_250(grp_sp_ph_pattern_sector_fu_28574_ap_return_250),
.ap_return_251(grp_sp_ph_pattern_sector_fu_28574_ap_return_251),
.ap_return_252(grp_sp_ph_pattern_sector_fu_28574_ap_return_252),
.ap_return_253(grp_sp_ph_pattern_sector_fu_28574_ap_return_253),
.ap_return_254(grp_sp_ph_pattern_sector_fu_28574_ap_return_254),
.ap_return_255(grp_sp_ph_pattern_sector_fu_28574_ap_return_255),
.ap_return_256(grp_sp_ph_pattern_sector_fu_28574_ap_return_256),
.ap_return_257(grp_sp_ph_pattern_sector_fu_28574_ap_return_257),
.ap_return_258(grp_sp_ph_pattern_sector_fu_28574_ap_return_258),
.ap_return_259(grp_sp_ph_pattern_sector_fu_28574_ap_return_259),
.ap_return_260(grp_sp_ph_pattern_sector_fu_28574_ap_return_260),
.ap_return_261(grp_sp_ph_pattern_sector_fu_28574_ap_return_261),
.ap_return_262(grp_sp_ph_pattern_sector_fu_28574_ap_return_262),
.ap_return_263(grp_sp_ph_pattern_sector_fu_28574_ap_return_263),
.ap_return_264(grp_sp_ph_pattern_sector_fu_28574_ap_return_264),
.ap_return_265(grp_sp_ph_pattern_sector_fu_28574_ap_return_265),
.ap_return_266(grp_sp_ph_pattern_sector_fu_28574_ap_return_266),
.ap_return_267(grp_sp_ph_pattern_sector_fu_28574_ap_return_267),
.ap_return_268(grp_sp_ph_pattern_sector_fu_28574_ap_return_268),
.ap_return_269(grp_sp_ph_pattern_sector_fu_28574_ap_return_269),
.ap_return_270(grp_sp_ph_pattern_sector_fu_28574_ap_return_270),
.ap_return_271(grp_sp_ph_pattern_sector_fu_28574_ap_return_271),
.ap_return_272(grp_sp_ph_pattern_sector_fu_28574_ap_return_272),
.ap_return_273(grp_sp_ph_pattern_sector_fu_28574_ap_return_273),
.ap_return_274(grp_sp_ph_pattern_sector_fu_28574_ap_return_274),
.ap_return_275(grp_sp_ph_pattern_sector_fu_28574_ap_return_275),
.ap_return_276(grp_sp_ph_pattern_sector_fu_28574_ap_return_276),
.ap_return_277(grp_sp_ph_pattern_sector_fu_28574_ap_return_277),
.ap_return_278(grp_sp_ph_pattern_sector_fu_28574_ap_return_278),
.ap_return_279(grp_sp_ph_pattern_sector_fu_28574_ap_return_279),
.ap_return_280(grp_sp_ph_pattern_sector_fu_28574_ap_return_280),
.ap_return_281(grp_sp_ph_pattern_sector_fu_28574_ap_return_281),
.ap_return_282(grp_sp_ph_pattern_sector_fu_28574_ap_return_282),
.ap_return_283(grp_sp_ph_pattern_sector_fu_28574_ap_return_283),
.ap_return_284(grp_sp_ph_pattern_sector_fu_28574_ap_return_284),
.ap_return_285(grp_sp_ph_pattern_sector_fu_28574_ap_return_285),
.ap_return_286(grp_sp_ph_pattern_sector_fu_28574_ap_return_286),
.ap_return_287(grp_sp_ph_pattern_sector_fu_28574_ap_return_287),
.ap_return_288(grp_sp_ph_pattern_sector_fu_28574_ap_return_288),
.ap_return_289(grp_sp_ph_pattern_sector_fu_28574_ap_return_289),
.ap_return_290(grp_sp_ph_pattern_sector_fu_28574_ap_return_290),
.ap_return_291(grp_sp_ph_pattern_sector_fu_28574_ap_return_291),
.ap_return_292(grp_sp_ph_pattern_sector_fu_28574_ap_return_292),
.ap_return_293(grp_sp_ph_pattern_sector_fu_28574_ap_return_293),
.ap_return_294(grp_sp_ph_pattern_sector_fu_28574_ap_return_294),
.ap_return_295(grp_sp_ph_pattern_sector_fu_28574_ap_return_295),
.ap_return_296(grp_sp_ph_pattern_sector_fu_28574_ap_return_296),
.ap_return_297(grp_sp_ph_pattern_sector_fu_28574_ap_return_297),
.ap_return_298(grp_sp_ph_pattern_sector_fu_28574_ap_return_298),
.ap_return_299(grp_sp_ph_pattern_sector_fu_28574_ap_return_299),
.ap_return_300(grp_sp_ph_pattern_sector_fu_28574_ap_return_300),
.ap_return_301(grp_sp_ph_pattern_sector_fu_28574_ap_return_301),
.ap_return_302(grp_sp_ph_pattern_sector_fu_28574_ap_return_302),
.ap_return_303(grp_sp_ph_pattern_sector_fu_28574_ap_return_303),
.ap_return_304(grp_sp_ph_pattern_sector_fu_28574_ap_return_304),
.ap_return_305(grp_sp_ph_pattern_sector_fu_28574_ap_return_305),
.ap_return_306(grp_sp_ph_pattern_sector_fu_28574_ap_return_306),
.ap_return_307(grp_sp_ph_pattern_sector_fu_28574_ap_return_307),
.ap_return_308(grp_sp_ph_pattern_sector_fu_28574_ap_return_308),
.ap_return_309(grp_sp_ph_pattern_sector_fu_28574_ap_return_309),
.ap_return_310(grp_sp_ph_pattern_sector_fu_28574_ap_return_310),
.ap_return_311(grp_sp_ph_pattern_sector_fu_28574_ap_return_311),
.ap_return_312(grp_sp_ph_pattern_sector_fu_28574_ap_return_312),
.ap_return_313(grp_sp_ph_pattern_sector_fu_28574_ap_return_313),
.ap_return_314(grp_sp_ph_pattern_sector_fu_28574_ap_return_314),
.ap_return_315(grp_sp_ph_pattern_sector_fu_28574_ap_return_315),
.ap_return_316(grp_sp_ph_pattern_sector_fu_28574_ap_return_316),
.ap_return_317(grp_sp_ph_pattern_sector_fu_28574_ap_return_317),
.ap_return_318(grp_sp_ph_pattern_sector_fu_28574_ap_return_318),
.ap_return_319(grp_sp_ph_pattern_sector_fu_28574_ap_return_319),
.ap_return_320(grp_sp_ph_pattern_sector_fu_28574_ap_return_320),
.ap_return_321(grp_sp_ph_pattern_sector_fu_28574_ap_return_321),
.ap_return_322(grp_sp_ph_pattern_sector_fu_28574_ap_return_322),
.ap_return_323(grp_sp_ph_pattern_sector_fu_28574_ap_return_323),
.ap_return_324(grp_sp_ph_pattern_sector_fu_28574_ap_return_324),
.ap_return_325(grp_sp_ph_pattern_sector_fu_28574_ap_return_325),
.ap_return_326(grp_sp_ph_pattern_sector_fu_28574_ap_return_326),
.ap_return_327(grp_sp_ph_pattern_sector_fu_28574_ap_return_327),
.ap_return_328(grp_sp_ph_pattern_sector_fu_28574_ap_return_328),
.ap_return_329(grp_sp_ph_pattern_sector_fu_28574_ap_return_329),
.ap_return_330(grp_sp_ph_pattern_sector_fu_28574_ap_return_330),
.ap_return_331(grp_sp_ph_pattern_sector_fu_28574_ap_return_331),
.ap_return_332(grp_sp_ph_pattern_sector_fu_28574_ap_return_332),
.ap_return_333(grp_sp_ph_pattern_sector_fu_28574_ap_return_333),
.ap_return_334(grp_sp_ph_pattern_sector_fu_28574_ap_return_334),
.ap_return_335(grp_sp_ph_pattern_sector_fu_28574_ap_return_335),
.ap_return_336(grp_sp_ph_pattern_sector_fu_28574_ap_return_336),
.ap_return_337(grp_sp_ph_pattern_sector_fu_28574_ap_return_337),
.ap_return_338(grp_sp_ph_pattern_sector_fu_28574_ap_return_338),
.ap_return_339(grp_sp_ph_pattern_sector_fu_28574_ap_return_339),
.ap_return_340(grp_sp_ph_pattern_sector_fu_28574_ap_return_340),
.ap_return_341(grp_sp_ph_pattern_sector_fu_28574_ap_return_341),
.ap_return_342(grp_sp_ph_pattern_sector_fu_28574_ap_return_342),
.ap_return_343(grp_sp_ph_pattern_sector_fu_28574_ap_return_343),
.ap_return_344(grp_sp_ph_pattern_sector_fu_28574_ap_return_344),
.ap_return_345(grp_sp_ph_pattern_sector_fu_28574_ap_return_345),
.ap_return_346(grp_sp_ph_pattern_sector_fu_28574_ap_return_346),
.ap_return_347(grp_sp_ph_pattern_sector_fu_28574_ap_return_347),
.ap_return_348(grp_sp_ph_pattern_sector_fu_28574_ap_return_348),
.ap_return_349(grp_sp_ph_pattern_sector_fu_28574_ap_return_349),
.ap_return_350(grp_sp_ph_pattern_sector_fu_28574_ap_return_350),
.ap_return_351(grp_sp_ph_pattern_sector_fu_28574_ap_return_351),
.ap_return_352(grp_sp_ph_pattern_sector_fu_28574_ap_return_352),
.ap_return_353(grp_sp_ph_pattern_sector_fu_28574_ap_return_353),
.ap_return_354(grp_sp_ph_pattern_sector_fu_28574_ap_return_354),
.ap_return_355(grp_sp_ph_pattern_sector_fu_28574_ap_return_355),
.ap_return_356(grp_sp_ph_pattern_sector_fu_28574_ap_return_356),
.ap_return_357(grp_sp_ph_pattern_sector_fu_28574_ap_return_357),
.ap_return_358(grp_sp_ph_pattern_sector_fu_28574_ap_return_358),
.ap_return_359(grp_sp_ph_pattern_sector_fu_28574_ap_return_359),
.ap_return_360(grp_sp_ph_pattern_sector_fu_28574_ap_return_360),
.ap_return_361(grp_sp_ph_pattern_sector_fu_28574_ap_return_361),
.ap_return_362(grp_sp_ph_pattern_sector_fu_28574_ap_return_362),
.ap_return_363(grp_sp_ph_pattern_sector_fu_28574_ap_return_363),
.ap_return_364(grp_sp_ph_pattern_sector_fu_28574_ap_return_364),
.ap_return_365(grp_sp_ph_pattern_sector_fu_28574_ap_return_365),
.ap_return_366(grp_sp_ph_pattern_sector_fu_28574_ap_return_366),
.ap_return_367(grp_sp_ph_pattern_sector_fu_28574_ap_return_367),
.ap_return_368(grp_sp_ph_pattern_sector_fu_28574_ap_return_368),
.ap_return_369(grp_sp_ph_pattern_sector_fu_28574_ap_return_369),
.ap_return_370(grp_sp_ph_pattern_sector_fu_28574_ap_return_370),
.ap_return_371(grp_sp_ph_pattern_sector_fu_28574_ap_return_371),
.ap_return_372(grp_sp_ph_pattern_sector_fu_28574_ap_return_372),
.ap_return_373(grp_sp_ph_pattern_sector_fu_28574_ap_return_373),
.ap_return_374(grp_sp_ph_pattern_sector_fu_28574_ap_return_374),
.ap_return_375(grp_sp_ph_pattern_sector_fu_28574_ap_return_375),
.ap_return_376(grp_sp_ph_pattern_sector_fu_28574_ap_return_376),
.ap_return_377(grp_sp_ph_pattern_sector_fu_28574_ap_return_377),
.ap_return_378(grp_sp_ph_pattern_sector_fu_28574_ap_return_378),
.ap_return_379(grp_sp_ph_pattern_sector_fu_28574_ap_return_379),
.ap_return_380(grp_sp_ph_pattern_sector_fu_28574_ap_return_380),
.ap_return_381(grp_sp_ph_pattern_sector_fu_28574_ap_return_381),
.ap_return_382(grp_sp_ph_pattern_sector_fu_28574_ap_return_382),
.ap_return_383(grp_sp_ph_pattern_sector_fu_28574_ap_return_383),
.ap_return_384(grp_sp_ph_pattern_sector_fu_28574_ap_return_384),
.ap_return_385(grp_sp_ph_pattern_sector_fu_28574_ap_return_385),
.ap_return_386(grp_sp_ph_pattern_sector_fu_28574_ap_return_386),
.ap_return_387(grp_sp_ph_pattern_sector_fu_28574_ap_return_387),
.ap_return_388(grp_sp_ph_pattern_sector_fu_28574_ap_return_388),
.ap_return_389(grp_sp_ph_pattern_sector_fu_28574_ap_return_389),
.ap_return_390(grp_sp_ph_pattern_sector_fu_28574_ap_return_390),
.ap_return_391(grp_sp_ph_pattern_sector_fu_28574_ap_return_391),
.ap_return_392(grp_sp_ph_pattern_sector_fu_28574_ap_return_392),
.ap_return_393(grp_sp_ph_pattern_sector_fu_28574_ap_return_393),
.ap_return_394(grp_sp_ph_pattern_sector_fu_28574_ap_return_394),
.ap_return_395(grp_sp_ph_pattern_sector_fu_28574_ap_return_395),
.ap_return_396(grp_sp_ph_pattern_sector_fu_28574_ap_return_396),
.ap_return_397(grp_sp_ph_pattern_sector_fu_28574_ap_return_397),
.ap_return_398(grp_sp_ph_pattern_sector_fu_28574_ap_return_398),
.ap_return_399(grp_sp_ph_pattern_sector_fu_28574_ap_return_399),
.ap_return_400(grp_sp_ph_pattern_sector_fu_28574_ap_return_400),
.ap_return_401(grp_sp_ph_pattern_sector_fu_28574_ap_return_401),
.ap_return_402(grp_sp_ph_pattern_sector_fu_28574_ap_return_402),
.ap_return_403(grp_sp_ph_pattern_sector_fu_28574_ap_return_403),
.ap_return_404(grp_sp_ph_pattern_sector_fu_28574_ap_return_404),
.ap_return_405(grp_sp_ph_pattern_sector_fu_28574_ap_return_405),
.ap_return_406(grp_sp_ph_pattern_sector_fu_28574_ap_return_406),
.ap_return_407(grp_sp_ph_pattern_sector_fu_28574_ap_return_407),
.ap_return_408(grp_sp_ph_pattern_sector_fu_28574_ap_return_408),
.ap_return_409(grp_sp_ph_pattern_sector_fu_28574_ap_return_409),
.ap_return_410(grp_sp_ph_pattern_sector_fu_28574_ap_return_410),
.ap_return_411(grp_sp_ph_pattern_sector_fu_28574_ap_return_411),
.ap_return_412(grp_sp_ph_pattern_sector_fu_28574_ap_return_412),
.ap_return_413(grp_sp_ph_pattern_sector_fu_28574_ap_return_413),
.ap_return_414(grp_sp_ph_pattern_sector_fu_28574_ap_return_414),
.ap_return_415(grp_sp_ph_pattern_sector_fu_28574_ap_return_415),
.ap_return_416(grp_sp_ph_pattern_sector_fu_28574_ap_return_416),
.ap_return_417(grp_sp_ph_pattern_sector_fu_28574_ap_return_417),
.ap_return_418(grp_sp_ph_pattern_sector_fu_28574_ap_return_418),
.ap_return_419(grp_sp_ph_pattern_sector_fu_28574_ap_return_419),
.ap_return_420(grp_sp_ph_pattern_sector_fu_28574_ap_return_420),
.ap_return_421(grp_sp_ph_pattern_sector_fu_28574_ap_return_421),
.ap_return_422(grp_sp_ph_pattern_sector_fu_28574_ap_return_422),
.ap_return_423(grp_sp_ph_pattern_sector_fu_28574_ap_return_423),
.ap_return_424(grp_sp_ph_pattern_sector_fu_28574_ap_return_424),
.ap_return_425(grp_sp_ph_pattern_sector_fu_28574_ap_return_425),
.ap_return_426(grp_sp_ph_pattern_sector_fu_28574_ap_return_426),
.ap_return_427(grp_sp_ph_pattern_sector_fu_28574_ap_return_427),
.ap_return_428(grp_sp_ph_pattern_sector_fu_28574_ap_return_428),
.ap_return_429(grp_sp_ph_pattern_sector_fu_28574_ap_return_429),
.ap_return_430(grp_sp_ph_pattern_sector_fu_28574_ap_return_430),
.ap_return_431(grp_sp_ph_pattern_sector_fu_28574_ap_return_431),
.ap_return_432(grp_sp_ph_pattern_sector_fu_28574_ap_return_432),
.ap_return_433(grp_sp_ph_pattern_sector_fu_28574_ap_return_433),
.ap_return_434(grp_sp_ph_pattern_sector_fu_28574_ap_return_434),
.ap_return_435(grp_sp_ph_pattern_sector_fu_28574_ap_return_435),
.ap_return_436(grp_sp_ph_pattern_sector_fu_28574_ap_return_436),
.ap_return_437(grp_sp_ph_pattern_sector_fu_28574_ap_return_437),
.ap_return_438(grp_sp_ph_pattern_sector_fu_28574_ap_return_438),
.ap_return_439(grp_sp_ph_pattern_sector_fu_28574_ap_return_439),
.ap_return_440(grp_sp_ph_pattern_sector_fu_28574_ap_return_440),
.ap_return_441(grp_sp_ph_pattern_sector_fu_28574_ap_return_441),
.ap_return_442(grp_sp_ph_pattern_sector_fu_28574_ap_return_442),
.ap_return_443(grp_sp_ph_pattern_sector_fu_28574_ap_return_443),
.ap_return_444(grp_sp_ph_pattern_sector_fu_28574_ap_return_444),
.ap_return_445(grp_sp_ph_pattern_sector_fu_28574_ap_return_445),
.ap_return_446(grp_sp_ph_pattern_sector_fu_28574_ap_return_446),
.ap_return_447(grp_sp_ph_pattern_sector_fu_28574_ap_return_447),
.ap_return_448(grp_sp_ph_pattern_sector_fu_28574_ap_return_448),
.ap_return_449(grp_sp_ph_pattern_sector_fu_28574_ap_return_449),
.ap_return_450(grp_sp_ph_pattern_sector_fu_28574_ap_return_450),
.ap_return_451(grp_sp_ph_pattern_sector_fu_28574_ap_return_451),
.ap_return_452(grp_sp_ph_pattern_sector_fu_28574_ap_return_452),
.ap_return_453(grp_sp_ph_pattern_sector_fu_28574_ap_return_453),
.ap_return_454(grp_sp_ph_pattern_sector_fu_28574_ap_return_454),
.ap_return_455(grp_sp_ph_pattern_sector_fu_28574_ap_return_455),
.ap_return_456(grp_sp_ph_pattern_sector_fu_28574_ap_return_456),
.ap_return_457(grp_sp_ph_pattern_sector_fu_28574_ap_return_457),
.ap_return_458(grp_sp_ph_pattern_sector_fu_28574_ap_return_458),
.ap_return_459(grp_sp_ph_pattern_sector_fu_28574_ap_return_459),
.ap_return_460(grp_sp_ph_pattern_sector_fu_28574_ap_return_460),
.ap_return_461(grp_sp_ph_pattern_sector_fu_28574_ap_return_461),
.ap_return_462(grp_sp_ph_pattern_sector_fu_28574_ap_return_462),
.ap_return_463(grp_sp_ph_pattern_sector_fu_28574_ap_return_463),
.ap_return_464(grp_sp_ph_pattern_sector_fu_28574_ap_return_464),
.ap_return_465(grp_sp_ph_pattern_sector_fu_28574_ap_return_465),
.ap_return_466(grp_sp_ph_pattern_sector_fu_28574_ap_return_466),
.ap_return_467(grp_sp_ph_pattern_sector_fu_28574_ap_return_467),
.ap_return_468(grp_sp_ph_pattern_sector_fu_28574_ap_return_468),
.ap_return_469(grp_sp_ph_pattern_sector_fu_28574_ap_return_469),
.ap_return_470(grp_sp_ph_pattern_sector_fu_28574_ap_return_470),
.ap_return_471(grp_sp_ph_pattern_sector_fu_28574_ap_return_471),
.ap_return_472(grp_sp_ph_pattern_sector_fu_28574_ap_return_472),
.ap_return_473(grp_sp_ph_pattern_sector_fu_28574_ap_return_473),
.ap_return_474(grp_sp_ph_pattern_sector_fu_28574_ap_return_474),
.ap_return_475(grp_sp_ph_pattern_sector_fu_28574_ap_return_475),
.ap_return_476(grp_sp_ph_pattern_sector_fu_28574_ap_return_476),
.ap_return_477(grp_sp_ph_pattern_sector_fu_28574_ap_return_477),
.ap_return_478(grp_sp_ph_pattern_sector_fu_28574_ap_return_478),
.ap_return_479(grp_sp_ph_pattern_sector_fu_28574_ap_return_479),
.ap_return_480(grp_sp_ph_pattern_sector_fu_28574_ap_return_480),
.ap_return_481(grp_sp_ph_pattern_sector_fu_28574_ap_return_481),
.ap_return_482(grp_sp_ph_pattern_sector_fu_28574_ap_return_482),
.ap_return_483(grp_sp_ph_pattern_sector_fu_28574_ap_return_483),
.ap_return_484(grp_sp_ph_pattern_sector_fu_28574_ap_return_484),
.ap_return_485(grp_sp_ph_pattern_sector_fu_28574_ap_return_485),
.ap_return_486(grp_sp_ph_pattern_sector_fu_28574_ap_return_486),
.ap_return_487(grp_sp_ph_pattern_sector_fu_28574_ap_return_487)
);
sp_prim_conv_sector call_ret4_sp_prim_conv_sector_fu_37378(
.ap_clk(ap_clk),
.ap_rst(ap_rst),
.ap_start(call_ret4_sp_prim_conv_sector_fu_37378_ap_start),
.ap_done(call_ret4_sp_prim_conv_sector_fu_37378_ap_done),
.ap_idle(call_ret4_sp_prim_conv_sector_fu_37378_ap_idle),
.ap_ready(call_ret4_sp_prim_conv_sector_fu_37378_ap_ready),
.q_0_0_0_V_read(q_0_0_0_V),
.q_0_0_1_V_read(q_0_0_1_V),
.q_0_1_0_V_read(q_0_1_0_V),
.q_0_1_1_V_read(q_0_1_1_V),
.q_0_2_0_V_read(q_0_2_0_V),
.q_0_2_1_V_read(q_0_2_1_V),
.q_0_3_0_V_read(q_0_3_0_V),
.q_0_3_1_V_read(q_0_3_1_V),
.q_0_4_0_V_read(q_0_4_0_V),
.q_0_4_1_V_read(q_0_4_1_V),
.q_0_5_0_V_read(q_0_5_0_V),
.q_0_5_1_V_read(q_0_5_1_V),
.q_0_6_0_V_read(q_0_6_0_V),
.q_0_6_1_V_read(q_0_6_1_V),
.q_0_7_0_V_read(q_0_7_0_V),
.q_0_7_1_V_read(q_0_7_1_V),
.q_0_8_0_V_read(q_0_8_0_V),
.q_0_8_1_V_read(q_0_8_1_V),
.q_1_0_0_V_read(q_1_0_0_V),
.q_1_0_1_V_read(q_1_0_1_V),
.q_1_1_0_V_read(q_1_1_0_V),
.q_1_1_1_V_read(q_1_1_1_V),
.q_1_2_0_V_read(q_1_2_0_V),
.q_1_2_1_V_read(q_1_2_1_V),
.q_1_3_0_V_read(q_1_3_0_V),
.q_1_3_1_V_read(q_1_3_1_V),
.q_1_4_0_V_read(q_1_4_0_V),
.q_1_4_1_V_read(q_1_4_1_V),
.q_1_5_0_V_read(q_1_5_0_V),
.q_1_5_1_V_read(q_1_5_1_V),
.q_1_6_0_V_read(q_1_6_0_V),
.q_1_6_1_V_read(q_1_6_1_V),
.q_1_7_0_V_read(q_1_7_0_V),
.q_1_7_1_V_read(q_1_7_1_V),
.q_1_8_0_V_read(q_1_8_0_V),
.q_1_8_1_V_read(q_1_8_1_V),
.q_2_0_0_V_read(q_2_0_0_V),
.q_2_0_1_V_read(q_2_0_1_V),
.q_2_1_0_V_read(q_2_1_0_V),
.q_2_1_1_V_read(q_2_1_1_V),
.q_2_2_0_V_read(q_2_2_0_V),
.q_2_2_1_V_read(q_2_2_1_V),
.q_2_3_0_V_read(q_2_3_0_V),
.q_2_3_1_V_read(q_2_3_1_V),
.q_2_4_0_V_read(q_2_4_0_V),
.q_2_4_1_V_read(q_2_4_1_V),
.q_2_5_0_V_read(q_2_5_0_V),
.q_2_5_1_V_read(q_2_5_1_V),
.q_2_6_0_V_read(q_2_6_0_V),
.q_2_6_1_V_read(q_2_6_1_V),
.q_2_7_0_V_read(q_2_7_0_V),
.q_2_7_1_V_read(q_2_7_1_V),
.q_2_8_0_V_read(q_2_8_0_V),
.q_2_8_1_V_read(q_2_8_1_V),
.q_3_0_0_V_read(q_3_0_0_V),
.q_3_0_1_V_read(q_3_0_1_V),
.q_3_1_0_V_read(q_3_1_0_V),
.q_3_1_1_V_read(q_3_1_1_V),
.q_3_2_0_V_read(q_3_2_0_V),
.q_3_2_1_V_read(q_3_2_1_V),
.q_3_3_0_V_read(q_3_3_0_V),
.q_3_3_1_V_read(q_3_3_1_V),
.q_3_4_0_V_read(q_3_4_0_V),
.q_3_4_1_V_read(q_3_4_1_V),
.q_3_5_0_V_read(q_3_5_0_V),
.q_3_5_1_V_read(q_3_5_1_V),
.q_3_6_0_V_read(q_3_6_0_V),
.q_3_6_1_V_read(q_3_6_1_V),
.q_3_7_0_V_read(q_3_7_0_V),
.q_3_7_1_V_read(q_3_7_1_V),
.q_3_8_0_V_read(q_3_8_0_V),
.q_3_8_1_V_read(q_3_8_1_V),
.q_4_0_0_V_read(q_4_0_0_V),
.q_4_0_1_V_read(q_4_0_1_V),
.q_4_1_0_V_read(q_4_1_0_V),
.q_4_1_1_V_read(q_4_1_1_V),
.q_4_2_0_V_read(q_4_2_0_V),
.q_4_2_1_V_read(q_4_2_1_V),
.q_4_3_0_V_read(q_4_3_0_V),
.q_4_3_1_V_read(q_4_3_1_V),
.q_4_4_0_V_read(q_4_4_0_V),
.q_4_4_1_V_read(q_4_4_1_V),
.q_4_5_0_V_read(q_4_5_0_V),
.q_4_5_1_V_read(q_4_5_1_V),
.q_4_6_0_V_read(q_4_6_0_V),
.q_4_6_1_V_read(q_4_6_1_V),
.q_4_7_0_V_read(q_4_7_0_V),
.q_4_7_1_V_read(q_4_7_1_V),
.q_4_8_0_V_read(q_4_8_0_V),
.q_4_8_1_V_read(q_4_8_1_V),
.wg_0_0_0_V_read(wg_0_0_0_V),
.wg_0_0_1_V_read(wg_0_0_1_V),
.wg_0_1_0_V_read(wg_0_1_0_V),
.wg_0_1_1_V_read(wg_0_1_1_V),
.wg_0_2_0_V_read(wg_0_2_0_V),
.wg_0_2_1_V_read(wg_0_2_1_V),
.wg_0_3_0_V_read(wg_0_3_0_V),
.wg_0_3_1_V_read(wg_0_3_1_V),
.wg_0_4_0_V_read(wg_0_4_0_V),
.wg_0_4_1_V_read(wg_0_4_1_V),
.wg_0_5_0_V_read(wg_0_5_0_V),
.wg_0_5_1_V_read(wg_0_5_1_V),
.wg_0_6_0_V_read(wg_0_6_0_V),
.wg_0_6_1_V_read(wg_0_6_1_V),
.wg_0_7_0_V_read(wg_0_7_0_V),
.wg_0_7_1_V_read(wg_0_7_1_V),
.wg_0_8_0_V_read(wg_0_8_0_V),
.wg_0_8_1_V_read(wg_0_8_1_V),
.wg_1_0_0_V_read(wg_1_0_0_V),
.wg_1_0_1_V_read(wg_1_0_1_V),
.wg_1_1_0_V_read(wg_1_1_0_V),
.wg_1_1_1_V_read(wg_1_1_1_V),
.wg_1_2_0_V_read(wg_1_2_0_V),
.wg_1_2_1_V_read(wg_1_2_1_V),
.wg_1_3_0_V_read(wg_1_3_0_V),
.wg_1_3_1_V_read(wg_1_3_1_V),
.wg_1_4_0_V_read(wg_1_4_0_V),
.wg_1_4_1_V_read(wg_1_4_1_V),
.wg_1_5_0_V_read(wg_1_5_0_V),
.wg_1_5_1_V_read(wg_1_5_1_V),
.wg_1_6_0_V_read(wg_1_6_0_V),
.wg_1_6_1_V_read(wg_1_6_1_V),
.wg_1_7_0_V_read(wg_1_7_0_V),
.wg_1_7_1_V_read(wg_1_7_1_V),
.wg_1_8_0_V_read(wg_1_8_0_V),
.wg_1_8_1_V_read(wg_1_8_1_V),
.wg_2_0_0_V_read(wg_2_0_0_V),
.wg_2_0_1_V_read(wg_2_0_1_V),
.wg_2_1_0_V_read(wg_2_1_0_V),
.wg_2_1_1_V_read(wg_2_1_1_V),
.wg_2_2_0_V_read(wg_2_2_0_V),
.wg_2_2_1_V_read(wg_2_2_1_V),
.wg_2_3_0_V_read(wg_2_3_0_V),
.wg_2_3_1_V_read(wg_2_3_1_V),
.wg_2_4_0_V_read(wg_2_4_0_V),
.wg_2_4_1_V_read(wg_2_4_1_V),
.wg_2_5_0_V_read(wg_2_5_0_V),
.wg_2_5_1_V_read(wg_2_5_1_V),
.wg_2_6_0_V_read(wg_2_6_0_V),
.wg_2_6_1_V_read(wg_2_6_1_V),
.wg_2_7_0_V_read(wg_2_7_0_V),
.wg_2_7_1_V_read(wg_2_7_1_V),
.wg_2_8_0_V_read(wg_2_8_0_V),
.wg_2_8_1_V_read(wg_2_8_1_V),
.wg_3_0_0_V_read(wg_3_0_0_V),
.wg_3_0_1_V_read(wg_3_0_1_V),
.wg_3_1_0_V_read(wg_3_1_0_V),
.wg_3_1_1_V_read(wg_3_1_1_V),
.wg_3_2_0_V_read(wg_3_2_0_V),
.wg_3_2_1_V_read(wg_3_2_1_V),
.wg_3_3_0_V_read(wg_3_3_0_V),
.wg_3_3_1_V_read(wg_3_3_1_V),
.wg_3_4_0_V_read(wg_3_4_0_V),
.wg_3_4_1_V_read(wg_3_4_1_V),
.wg_3_5_0_V_read(wg_3_5_0_V),
.wg_3_5_1_V_read(wg_3_5_1_V),
.wg_3_6_0_V_read(wg_3_6_0_V),
.wg_3_6_1_V_read(wg_3_6_1_V),
.wg_3_7_0_V_read(wg_3_7_0_V),
.wg_3_7_1_V_read(wg_3_7_1_V),
.wg_3_8_0_V_read(wg_3_8_0_V),
.wg_3_8_1_V_read(wg_3_8_1_V),
.wg_4_0_0_V_read(wg_4_0_0_V),
.wg_4_0_1_V_read(wg_4_0_1_V),
.wg_4_1_0_V_read(wg_4_1_0_V),
.wg_4_1_1_V_read(wg_4_1_1_V),
.wg_4_2_0_V_read(wg_4_2_0_V),
.wg_4_2_1_V_read(wg_4_2_1_V),
.wg_4_3_0_V_read(wg_4_3_0_V),
.wg_4_3_1_V_read(wg_4_3_1_V),
.wg_4_4_0_V_read(wg_4_4_0_V),
.wg_4_4_1_V_read(wg_4_4_1_V),
.wg_4_5_0_V_read(wg_4_5_0_V),
.wg_4_5_1_V_read(wg_4_5_1_V),
.wg_4_6_0_V_read(wg_4_6_0_V),
.wg_4_6_1_V_read(wg_4_6_1_V),
.wg_4_7_0_V_read(wg_4_7_0_V),
.wg_4_7_1_V_read(wg_4_7_1_V),
.wg_4_8_0_V_read(wg_4_8_0_V),
.wg_4_8_1_V_read(wg_4_8_1_V),
.hstr_0_0_0_V_read(hstr_0_0_0_V),
.hstr_0_0_1_V_read(hstr_0_0_1_V),
.hstr_0_1_0_V_read(hstr_0_1_0_V),
.hstr_0_1_1_V_read(hstr_0_1_1_V),
.hstr_0_2_0_V_read(hstr_0_2_0_V),
.hstr_0_2_1_V_read(hstr_0_2_1_V),
.hstr_0_3_0_V_read(hstr_0_3_0_V),
.hstr_0_3_1_V_read(hstr_0_3_1_V),
.hstr_0_4_0_V_read(hstr_0_4_0_V),
.hstr_0_4_1_V_read(hstr_0_4_1_V),
.hstr_0_5_0_V_read(hstr_0_5_0_V),
.hstr_0_5_1_V_read(hstr_0_5_1_V),
.hstr_0_6_0_V_read(hstr_0_6_0_V),
.hstr_0_6_1_V_read(hstr_0_6_1_V),
.hstr_0_7_0_V_read(hstr_0_7_0_V),
.hstr_0_7_1_V_read(hstr_0_7_1_V),
.hstr_0_8_0_V_read(hstr_0_8_0_V),
.hstr_0_8_1_V_read(hstr_0_8_1_V),
.hstr_1_0_0_V_read(hstr_1_0_0_V),
.hstr_1_0_1_V_read(hstr_1_0_1_V),
.hstr_1_1_0_V_read(hstr_1_1_0_V),
.hstr_1_1_1_V_read(hstr_1_1_1_V),
.hstr_1_2_0_V_read(hstr_1_2_0_V),
.hstr_1_2_1_V_read(hstr_1_2_1_V),
.hstr_1_3_0_V_read(hstr_1_3_0_V),
.hstr_1_3_1_V_read(hstr_1_3_1_V),
.hstr_1_4_0_V_read(hstr_1_4_0_V),
.hstr_1_4_1_V_read(hstr_1_4_1_V),
.hstr_1_5_0_V_read(hstr_1_5_0_V),
.hstr_1_5_1_V_read(hstr_1_5_1_V),
.hstr_1_6_0_V_read(hstr_1_6_0_V),
.hstr_1_6_1_V_read(hstr_1_6_1_V),
.hstr_1_7_0_V_read(hstr_1_7_0_V),
.hstr_1_7_1_V_read(hstr_1_7_1_V),
.hstr_1_8_0_V_read(hstr_1_8_0_V),
.hstr_1_8_1_V_read(hstr_1_8_1_V),
.hstr_2_0_0_V_read(hstr_2_0_0_V),
.hstr_2_0_1_V_read(hstr_2_0_1_V),
.hstr_2_1_0_V_read(hstr_2_1_0_V),
.hstr_2_1_1_V_read(hstr_2_1_1_V),
.hstr_2_2_0_V_read(hstr_2_2_0_V),
.hstr_2_2_1_V_read(hstr_2_2_1_V),
.hstr_2_3_0_V_read(hstr_2_3_0_V),
.hstr_2_3_1_V_read(hstr_2_3_1_V),
.hstr_2_4_0_V_read(hstr_2_4_0_V),
.hstr_2_4_1_V_read(hstr_2_4_1_V),
.hstr_2_5_0_V_read(hstr_2_5_0_V),
.hstr_2_5_1_V_read(hstr_2_5_1_V),
.hstr_2_6_0_V_read(hstr_2_6_0_V),
.hstr_2_6_1_V_read(hstr_2_6_1_V),
.hstr_2_7_0_V_read(hstr_2_7_0_V),
.hstr_2_7_1_V_read(hstr_2_7_1_V),
.hstr_2_8_0_V_read(hstr_2_8_0_V),
.hstr_2_8_1_V_read(hstr_2_8_1_V),
.hstr_3_0_0_V_read(hstr_3_0_0_V),
.hstr_3_0_1_V_read(hstr_3_0_1_V),
.hstr_3_1_0_V_read(hstr_3_1_0_V),
.hstr_3_1_1_V_read(hstr_3_1_1_V),
.hstr_3_2_0_V_read(hstr_3_2_0_V),
.hstr_3_2_1_V_read(hstr_3_2_1_V),
.hstr_3_3_0_V_read(hstr_3_3_0_V),
.hstr_3_3_1_V_read(hstr_3_3_1_V),
.hstr_3_4_0_V_read(hstr_3_4_0_V),
.hstr_3_4_1_V_read(hstr_3_4_1_V),
.hstr_3_5_0_V_read(hstr_3_5_0_V),
.hstr_3_5_1_V_read(hstr_3_5_1_V),
.hstr_3_6_0_V_read(hstr_3_6_0_V),
.hstr_3_6_1_V_read(hstr_3_6_1_V),
.hstr_3_7_0_V_read(hstr_3_7_0_V),
.hstr_3_7_1_V_read(hstr_3_7_1_V),
.hstr_3_8_0_V_read(hstr_3_8_0_V),
.hstr_3_8_1_V_read(hstr_3_8_1_V),
.hstr_4_0_0_V_read(hstr_4_0_0_V),
.hstr_4_0_1_V_read(hstr_4_0_1_V),
.hstr_4_1_0_V_read(hstr_4_1_0_V),
.hstr_4_1_1_V_read(hstr_4_1_1_V),
.hstr_4_2_0_V_read(hstr_4_2_0_V),
.hstr_4_2_1_V_read(hstr_4_2_1_V),
.hstr_4_3_0_V_read(hstr_4_3_0_V),
.hstr_4_3_1_V_read(hstr_4_3_1_V),
.hstr_4_4_0_V_read(hstr_4_4_0_V),
.hstr_4_4_1_V_read(hstr_4_4_1_V),
.hstr_4_5_0_V_read(hstr_4_5_0_V),
.hstr_4_5_1_V_read(hstr_4_5_1_V),
.hstr_4_6_0_V_read(hstr_4_6_0_V),
.hstr_4_6_1_V_read(hstr_4_6_1_V),
.hstr_4_7_0_V_read(hstr_4_7_0_V),
.hstr_4_7_1_V_read(hstr_4_7_1_V),
.hstr_4_8_0_V_read(hstr_4_8_0_V),
.hstr_4_8_1_V_read(hstr_4_8_1_V),
.cpat_0_0_0_V_read(cpat_0_0_0_V),
.cpat_0_0_1_V_read(cpat_0_0_1_V),
.cpat_0_1_0_V_read(cpat_0_1_0_V),
.cpat_0_1_1_V_read(cpat_0_1_1_V),
.cpat_0_2_0_V_read(cpat_0_2_0_V),
.cpat_0_2_1_V_read(cpat_0_2_1_V),
.cpat_0_3_0_V_read(cpat_0_3_0_V),
.cpat_0_3_1_V_read(cpat_0_3_1_V),
.cpat_0_4_0_V_read(cpat_0_4_0_V),
.cpat_0_4_1_V_read(cpat_0_4_1_V),
.cpat_0_5_0_V_read(cpat_0_5_0_V),
.cpat_0_5_1_V_read(cpat_0_5_1_V),
.cpat_0_6_0_V_read(cpat_0_6_0_V),
.cpat_0_6_1_V_read(cpat_0_6_1_V),
.cpat_0_7_0_V_read(cpat_0_7_0_V),
.cpat_0_7_1_V_read(cpat_0_7_1_V),
.cpat_0_8_0_V_read(cpat_0_8_0_V),
.cpat_0_8_1_V_read(cpat_0_8_1_V),
.cpat_1_0_0_V_read(cpat_1_0_0_V),
.cpat_1_0_1_V_read(cpat_1_0_1_V),
.cpat_1_1_0_V_read(cpat_1_1_0_V),
.cpat_1_1_1_V_read(cpat_1_1_1_V),
.cpat_1_2_0_V_read(cpat_1_2_0_V),
.cpat_1_2_1_V_read(cpat_1_2_1_V),
.cpat_1_3_0_V_read(cpat_1_3_0_V),
.cpat_1_3_1_V_read(cpat_1_3_1_V),
.cpat_1_4_0_V_read(cpat_1_4_0_V),
.cpat_1_4_1_V_read(cpat_1_4_1_V),
.cpat_1_5_0_V_read(cpat_1_5_0_V),
.cpat_1_5_1_V_read(cpat_1_5_1_V),
.cpat_1_6_0_V_read(cpat_1_6_0_V),
.cpat_1_6_1_V_read(cpat_1_6_1_V),
.cpat_1_7_0_V_read(cpat_1_7_0_V),
.cpat_1_7_1_V_read(cpat_1_7_1_V),
.cpat_1_8_0_V_read(cpat_1_8_0_V),
.cpat_1_8_1_V_read(cpat_1_8_1_V),
.cpat_2_0_0_V_read(cpat_2_0_0_V),
.cpat_2_0_1_V_read(cpat_2_0_1_V),
.cpat_2_1_0_V_read(cpat_2_1_0_V),
.cpat_2_1_1_V_read(cpat_2_1_1_V),
.cpat_2_2_0_V_read(cpat_2_2_0_V),
.cpat_2_2_1_V_read(cpat_2_2_1_V),
.cpat_2_3_0_V_read(cpat_2_3_0_V),
.cpat_2_3_1_V_read(cpat_2_3_1_V),
.cpat_2_4_0_V_read(cpat_2_4_0_V),
.cpat_2_4_1_V_read(cpat_2_4_1_V),
.cpat_2_5_0_V_read(cpat_2_5_0_V),
.cpat_2_5_1_V_read(cpat_2_5_1_V),
.cpat_2_6_0_V_read(cpat_2_6_0_V),
.cpat_2_6_1_V_read(cpat_2_6_1_V),
.cpat_2_7_0_V_read(cpat_2_7_0_V),
.cpat_2_7_1_V_read(cpat_2_7_1_V),
.cpat_2_8_0_V_read(cpat_2_8_0_V),
.cpat_2_8_1_V_read(cpat_2_8_1_V),
.cpat_3_0_0_V_read(cpat_3_0_0_V),
.cpat_3_0_1_V_read(cpat_3_0_1_V),
.cpat_3_1_0_V_read(cpat_3_1_0_V),
.cpat_3_1_1_V_read(cpat_3_1_1_V),
.cpat_3_2_0_V_read(cpat_3_2_0_V),
.cpat_3_2_1_V_read(cpat_3_2_1_V),
.cpat_3_3_0_V_read(cpat_3_3_0_V),
.cpat_3_3_1_V_read(cpat_3_3_1_V),
.cpat_3_4_0_V_read(cpat_3_4_0_V),
.cpat_3_4_1_V_read(cpat_3_4_1_V),
.cpat_3_5_0_V_read(cpat_3_5_0_V),
.cpat_3_5_1_V_read(cpat_3_5_1_V),
.cpat_3_6_0_V_read(cpat_3_6_0_V),
.cpat_3_6_1_V_read(cpat_3_6_1_V),
.cpat_3_7_0_V_read(cpat_3_7_0_V),
.cpat_3_7_1_V_read(cpat_3_7_1_V),
.cpat_3_8_0_V_read(cpat_3_8_0_V),
.cpat_3_8_1_V_read(cpat_3_8_1_V),
.cpat_4_0_0_V_read(cpat_4_0_0_V),
.cpat_4_0_1_V_read(cpat_4_0_1_V),
.cpat_4_1_0_V_read(cpat_4_1_0_V),
.cpat_4_1_1_V_read(cpat_4_1_1_V),
.cpat_4_2_0_V_read(cpat_4_2_0_V),
.cpat_4_2_1_V_read(cpat_4_2_1_V),
.cpat_4_3_0_V_read(cpat_4_3_0_V),
.cpat_4_3_1_V_read(cpat_4_3_1_V),
.cpat_4_4_0_V_read(cpat_4_4_0_V),
.cpat_4_4_1_V_read(cpat_4_4_1_V),
.cpat_4_5_0_V_read(cpat_4_5_0_V),
.cpat_4_5_1_V_read(cpat_4_5_1_V),
.cpat_4_6_0_V_read(cpat_4_6_0_V),
.cpat_4_6_1_V_read(cpat_4_6_1_V),
.cpat_4_7_0_V_read(cpat_4_7_0_V),
.cpat_4_7_1_V_read(cpat_4_7_1_V),
.cpat_4_8_0_V_read(cpat_4_8_0_V),
.cpat_4_8_1_V_read(cpat_4_8_1_V),
.sel_V(tmp_146_fu_54267_p1),
.addr_V(addr_V),
.r_in_V(r_in_V),
.we_V(we_V),
.endcap_V(endcap_V),
.lat_test_V(lat_test_V),
.cs_0_V_read(pcs_cs_0_V),
.cs_1_V_read(pcs_cs_1_V),
.cs_2_V_read(pcs_cs_2_V),
.cs_3_V_read(pcs_cs_3_V),
.cs_4_V_read(pcs_cs_4_V),
.ap_return_0(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_0),
.ap_return_1(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_1),
.ap_return_2(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_2),
.ap_return_3(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_3),
.ap_return_4(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_4),
.ap_return_5(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_5),
.ap_return_6(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_6),
.ap_return_7(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_7),
.ap_return_8(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_8),
.ap_return_9(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_9),
.ap_return_10(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_10),
.ap_return_11(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_11),
.ap_return_12(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_12),
.ap_return_13(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_13),
.ap_return_14(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_14),
.ap_return_15(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_15),
.ap_return_16(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_16),
.ap_return_17(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_17),
.ap_return_18(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_18),
.ap_return_19(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_19),
.ap_return_20(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_20),
.ap_return_21(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_21),
.ap_return_22(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_22),
.ap_return_23(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_23),
.ap_return_24(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_24),
.ap_return_25(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_25),
.ap_return_26(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_26),
.ap_return_27(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_27),
.ap_return_28(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_28),
.ap_return_29(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_29),
.ap_return_30(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_30),
.ap_return_31(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_31),
.ap_return_32(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_32),
.ap_return_33(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_33),
.ap_return_34(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_34),
.ap_return_35(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_35),
.ap_return_36(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_36),
.ap_return_37(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_37),
.ap_return_38(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_38),
.ap_return_39(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_39),
.ap_return_40(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_40),
.ap_return_41(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_41),
.ap_return_42(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_42),
.ap_return_43(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_43),
.ap_return_44(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_44),
.ap_return_45(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_45),
.ap_return_46(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_46),
.ap_return_47(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_47),
.ap_return_48(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_48),
.ap_return_49(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_49),
.ap_return_50(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_50),
.ap_return_51(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_51),
.ap_return_52(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_52),
.ap_return_53(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_53),
.ap_return_54(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_54),
.ap_return_55(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_55),
.ap_return_56(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_56),
.ap_return_57(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_57),
.ap_return_58(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_58),
.ap_return_59(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_59),
.ap_return_60(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_60),
.ap_return_61(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_61),
.ap_return_62(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_62),
.ap_return_63(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_63),
.ap_return_64(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_64),
.ap_return_65(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_65),
.ap_return_66(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_66),
.ap_return_67(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_67),
.ap_return_68(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_68),
.ap_return_69(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_69),
.ap_return_70(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_70),
.ap_return_71(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_71),
.ap_return_72(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_72),
.ap_return_73(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_73),
.ap_return_74(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_74),
.ap_return_75(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_75),
.ap_return_76(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_76),
.ap_return_77(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_77),
.ap_return_78(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_78),
.ap_return_79(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_79),
.ap_return_80(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_80),
.ap_return_81(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_81),
.ap_return_82(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_82),
.ap_return_83(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_83),
.ap_return_84(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_84),
.ap_return_85(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_85),
.ap_return_86(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_86),
.ap_return_87(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_87),
.ap_return_88(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_88),
.ap_return_89(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_89),
.ap_return_90(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_90),
.ap_return_91(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_91),
.ap_return_92(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_92),
.ap_return_93(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_93),
.ap_return_94(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_94),
.ap_return_95(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_95),
.ap_return_96(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_96),
.ap_return_97(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_97),
.ap_return_98(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_98),
.ap_return_99(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_99),
.ap_return_100(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_100),
.ap_return_101(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_101),
.ap_return_102(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_102),
.ap_return_103(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_103),
.ap_return_104(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_104),
.ap_return_105(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_105),
.ap_return_106(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_106),
.ap_return_107(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_107),
.ap_return_108(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_108),
.ap_return_109(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_109),
.ap_return_110(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_110),
.ap_return_111(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_111),
.ap_return_112(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_112),
.ap_return_113(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_113),
.ap_return_114(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_114),
.ap_return_115(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_115),
.ap_return_116(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_116),
.ap_return_117(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_117),
.ap_return_118(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_118),
.ap_return_119(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_119),
.ap_return_120(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_120),
.ap_return_121(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_121),
.ap_return_122(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_122),
.ap_return_123(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_123),
.ap_return_124(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_124),
.ap_return_125(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_125),
.ap_return_126(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_126),
.ap_return_127(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_127),
.ap_return_128(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_128),
.ap_return_129(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_129),
.ap_return_130(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_130),
.ap_return_131(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_131),
.ap_return_132(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_132),
.ap_return_133(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_133),
.ap_return_134(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_134),
.ap_return_135(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_135),
.ap_return_136(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_136),
.ap_return_137(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_137),
.ap_return_138(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_138),
.ap_return_139(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_139),
.ap_return_140(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_140),
.ap_return_141(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_141),
.ap_return_142(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_142),
.ap_return_143(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_143),
.ap_return_144(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_144),
.ap_return_145(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_145),
.ap_return_146(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_146),
.ap_return_147(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_147),
.ap_return_148(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_148),
.ap_return_149(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_149),
.ap_return_150(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_150),
.ap_return_151(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_151),
.ap_return_152(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_152),
.ap_return_153(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_153),
.ap_return_154(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_154),
.ap_return_155(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_155),
.ap_return_156(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_156),
.ap_return_157(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_157),
.ap_return_158(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_158),
.ap_return_159(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_159),
.ap_return_160(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_160),
.ap_return_161(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_161),
.ap_return_162(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_162),
.ap_return_163(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_163),
.ap_return_164(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_164),
.ap_return_165(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_165),
.ap_return_166(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_166),
.ap_return_167(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_167),
.ap_return_168(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_168),
.ap_return_169(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_169),
.ap_return_170(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_170),
.ap_return_171(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_171),
.ap_return_172(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_172),
.ap_return_173(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_173),
.ap_return_174(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_174),
.ap_return_175(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_175),
.ap_return_176(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_176),
.ap_return_177(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_177),
.ap_return_178(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_178),
.ap_return_179(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_179),
.ap_return_180(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_180),
.ap_return_181(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_181),
.ap_return_182(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_182),
.ap_return_183(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_183),
.ap_return_184(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_184),
.ap_return_185(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_185),
.ap_return_186(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_186),
.ap_return_187(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_187),
.ap_return_188(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_188),
.ap_return_189(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_189),
.ap_return_190(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_190),
.ap_return_191(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_191),
.ap_return_192(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_192),
.ap_return_193(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_193),
.ap_return_194(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_194),
.ap_return_195(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_195),
.ap_return_196(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_196),
.ap_return_197(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_197),
.ap_return_198(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_198),
.ap_return_199(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_199),
.ap_return_200(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_200),
.ap_return_201(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_201),
.ap_return_202(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_202),
.ap_return_203(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_203),
.ap_return_204(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_204),
.ap_return_205(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_205),
.ap_return_206(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_206),
.ap_return_207(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_207),
.ap_return_208(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_208),
.ap_return_209(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_209),
.ap_return_210(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_210),
.ap_return_211(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_211),
.ap_return_212(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_212),
.ap_return_213(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_213),
.ap_return_214(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_214),
.ap_return_215(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_215),
.ap_return_216(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_216),
.ap_return_217(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_217),
.ap_return_218(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_218),
.ap_return_219(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_219),
.ap_return_220(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_220),
.ap_return_221(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_221),
.ap_return_222(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_222),
.ap_return_223(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_223),
.ap_return_224(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_224),
.ap_return_225(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_225),
.ap_return_226(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_226),
.ap_return_227(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_227),
.ap_return_228(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_228),
.ap_return_229(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_229),
.ap_return_230(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_230),
.ap_return_231(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_231),
.ap_return_232(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_232),
.ap_return_233(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_233),
.ap_return_234(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_234),
.ap_return_235(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_235),
.ap_return_236(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_236),
.ap_return_237(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_237),
.ap_return_238(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_238),
.ap_return_239(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_239),
.ap_return_240(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_240),
.ap_return_241(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_241),
.ap_return_242(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_242),
.ap_return_243(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_243),
.ap_return_244(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_244),
.ap_return_245(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_245),
.ap_return_246(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_246),
.ap_return_247(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_247),
.ap_return_248(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_248),
.ap_return_249(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_249),
.ap_return_250(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_250),
.ap_return_251(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_251),
.ap_return_252(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_252),
.ap_return_253(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_253),
.ap_return_254(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_254),
.ap_return_255(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_255),
.ap_return_256(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_256),
.ap_return_257(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_257),
.ap_return_258(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_258),
.ap_return_259(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_259),
.ap_return_260(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_260),
.ap_return_261(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_261),
.ap_return_262(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_262),
.ap_return_263(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_263)
);
sp_best_tracks grp_sp_best_tracks_fu_51719(
.ap_clk(ap_clk),
.ap_rst(ap_rst),
.phi_0_0_V_read(phi_t_0_0_V_reg_63253),
.phi_0_1_V_read(phi_t_0_1_V_reg_63258),
.phi_0_2_V_read(phi_t_0_2_V_reg_63263),
.phi_1_0_V_read(phi_t_1_0_V_reg_63268),
.phi_1_1_V_read(phi_t_1_1_V_reg_63273),
.phi_1_2_V_read(phi_t_1_2_V_reg_63278),
.phi_2_0_V_read(phi_t_2_0_V_reg_63283),
.phi_2_1_V_read(phi_t_2_1_V_reg_63288),
.phi_2_2_V_read(phi_t_2_2_V_reg_63293),
.phi_3_0_V_read(phi_t_3_0_V_reg_63298),
.phi_3_1_V_read(phi_t_3_1_V_reg_63303),
.phi_3_2_V_read(phi_t_3_2_V_reg_63308),
.theta_0_0_V_read(theta_t_0_0_V_reg_63313),
.theta_0_1_V_read(theta_t_0_1_V_reg_63318),
.theta_0_2_V_read(theta_t_0_2_V_reg_63323),
.theta_1_0_V_read(theta_t_1_0_V_reg_63328),
.theta_1_1_V_read(theta_t_1_1_V_reg_63333),
.theta_1_2_V_read(theta_t_1_2_V_reg_63338),
.theta_2_0_V_read(theta_t_2_0_V_reg_63343),
.theta_2_1_V_read(theta_t_2_1_V_reg_63348),
.theta_2_2_V_read(theta_t_2_2_V_reg_63353),
.theta_3_0_V_read(theta_t_3_0_V_reg_63358),
.theta_3_1_V_read(theta_t_3_1_V_reg_63363),
.theta_3_2_V_read(theta_t_3_2_V_reg_63368),
.cpattern_0_0_0_V_read(cpattern_t_0_0_0_V_reg_63553),
.cpattern_0_0_1_V_read(cpattern_t_0_0_1_V_reg_63558),
.cpattern_0_0_2_V_read(cpattern_t_0_0_2_V_reg_63563),
.cpattern_0_0_3_V_read(cpattern_t_0_0_3_V_reg_63568),
.cpattern_0_1_0_V_read(cpattern_t_0_1_0_V_reg_63573),
.cpattern_0_1_1_V_read(cpattern_t_0_1_1_V_reg_63578),
.cpattern_0_1_2_V_read(cpattern_t_0_1_2_V_reg_63583),
.cpattern_0_1_3_V_read(cpattern_t_0_1_3_V_reg_63588),
.cpattern_0_2_0_V_read(cpattern_t_0_2_0_V_reg_63593),
.cpattern_0_2_1_V_read(cpattern_t_0_2_1_V_reg_63598),
.cpattern_0_2_2_V_read(cpattern_t_0_2_2_V_reg_63603),
.cpattern_0_2_3_V_read(cpattern_t_0_2_3_V_reg_63608),
.cpattern_1_0_0_V_read(cpattern_t_1_0_0_V_reg_63613),
.cpattern_1_0_1_V_read(cpattern_t_1_0_1_V_reg_63618),
.cpattern_1_0_2_V_read(cpattern_t_1_0_2_V_reg_63623),
.cpattern_1_0_3_V_read(cpattern_t_1_0_3_V_reg_63628),
.cpattern_1_1_0_V_read(cpattern_t_1_1_0_V_reg_63633),
.cpattern_1_1_1_V_read(cpattern_t_1_1_1_V_reg_63638),
.cpattern_1_1_2_V_read(cpattern_t_1_1_2_V_reg_63643),
.cpattern_1_1_3_V_read(cpattern_t_1_1_3_V_reg_63648),
.cpattern_1_2_0_V_read(cpattern_t_1_2_0_V_reg_63653),
.cpattern_1_2_1_V_read(cpattern_t_1_2_1_V_reg_63658),
.cpattern_1_2_2_V_read(cpattern_t_1_2_2_V_reg_63663),
.cpattern_1_2_3_V_read(cpattern_t_1_2_3_V_reg_63668),
.cpattern_2_0_0_V_read(cpattern_t_2_0_0_V_reg_63673),
.cpattern_2_0_1_V_read(cpattern_t_2_0_1_V_reg_63678),
.cpattern_2_0_2_V_read(cpattern_t_2_0_2_V_reg_63683),
.cpattern_2_0_3_V_read(cpattern_t_2_0_3_V_reg_63688),
.cpattern_2_1_0_V_read(cpattern_t_2_1_0_V_reg_63693),
.cpattern_2_1_1_V_read(cpattern_t_2_1_1_V_reg_63698),
.cpattern_2_1_2_V_read(cpattern_t_2_1_2_V_reg_63703),
.cpattern_2_1_3_V_read(cpattern_t_2_1_3_V_reg_63708),
.cpattern_2_2_0_V_read(cpattern_t_2_2_0_V_reg_63713),
.cpattern_2_2_1_V_read(cpattern_t_2_2_1_V_reg_63718),
.cpattern_2_2_2_V_read(cpattern_t_2_2_2_V_reg_63723),
.cpattern_2_2_3_V_read(cpattern_t_2_2_3_V_reg_63728),
.cpattern_3_0_0_V_read(cpattern_t_3_0_0_V_reg_63733),
.cpattern_3_0_1_V_read(cpattern_t_3_0_1_V_reg_63738),
.cpattern_3_0_2_V_read(cpattern_t_3_0_2_V_reg_63743),
.cpattern_3_0_3_V_read(cpattern_t_3_0_3_V_reg_63748),
.cpattern_3_1_0_V_read(cpattern_t_3_1_0_V_reg_63753),
.cpattern_3_1_1_V_read(cpattern_t_3_1_1_V_reg_63758),
.cpattern_3_1_2_V_read(cpattern_t_3_1_2_V_reg_63763),
.cpattern_3_1_3_V_read(cpattern_t_3_1_3_V_reg_63768),
.cpattern_3_2_0_V_read(cpattern_t_3_2_0_V_reg_63773),
.cpattern_3_2_1_V_read(cpattern_t_3_2_1_V_reg_63778),
.cpattern_3_2_2_V_read(cpattern_t_3_2_2_V_reg_63783),
.cpattern_3_2_3_V_read(cpattern_t_3_2_3_V_reg_63788),
.delta_ph_0_0_0_V_read(delta_ph_t_0_0_0_V_reg_63793),
.delta_ph_0_0_1_V_read(delta_ph_t_0_0_1_V_reg_63798),
.delta_ph_0_0_2_V_read(delta_ph_t_0_0_2_V_reg_63803),
.delta_ph_0_0_3_V_read(delta_ph_t_0_0_3_V_reg_63808),
.delta_ph_0_0_4_V_read(delta_ph_t_0_0_4_V_reg_63813),
.delta_ph_0_0_5_V_read(delta_ph_t_0_0_5_V_reg_63818),
.delta_ph_0_1_0_V_read(delta_ph_t_0_1_0_V_reg_63823),
.delta_ph_0_1_1_V_read(delta_ph_t_0_1_1_V_reg_63828),
.delta_ph_0_1_2_V_read(delta_ph_t_0_1_2_V_reg_63833),
.delta_ph_0_1_3_V_read(delta_ph_t_0_1_3_V_reg_63838),
.delta_ph_0_1_4_V_read(delta_ph_t_0_1_4_V_reg_63843),
.delta_ph_0_1_5_V_read(delta_ph_t_0_1_5_V_reg_63848),
.delta_ph_0_2_0_V_read(delta_ph_t_0_2_0_V_reg_63853),
.delta_ph_0_2_1_V_read(delta_ph_t_0_2_1_V_reg_63858),
.delta_ph_0_2_2_V_read(delta_ph_t_0_2_2_V_reg_63863),
.delta_ph_0_2_3_V_read(delta_ph_t_0_2_3_V_reg_63868),
.delta_ph_0_2_4_V_read(delta_ph_t_0_2_4_V_reg_63873),
.delta_ph_0_2_5_V_read(delta_ph_t_0_2_5_V_reg_63878),
.delta_ph_1_0_0_V_read(delta_ph_t_1_0_0_V_reg_63883),
.delta_ph_1_0_1_V_read(delta_ph_t_1_0_1_V_reg_63888),
.delta_ph_1_0_2_V_read(delta_ph_t_1_0_2_V_reg_63893),
.delta_ph_1_0_3_V_read(delta_ph_t_1_0_3_V_reg_63898),
.delta_ph_1_0_4_V_read(delta_ph_t_1_0_4_V_reg_63903),
.delta_ph_1_0_5_V_read(delta_ph_t_1_0_5_V_reg_63908),
.delta_ph_1_1_0_V_read(delta_ph_t_1_1_0_V_reg_63913),
.delta_ph_1_1_1_V_read(delta_ph_t_1_1_1_V_reg_63918),
.delta_ph_1_1_2_V_read(delta_ph_t_1_1_2_V_reg_63923),
.delta_ph_1_1_3_V_read(delta_ph_t_1_1_3_V_reg_63928),
.delta_ph_1_1_4_V_read(delta_ph_t_1_1_4_V_reg_63933),
.delta_ph_1_1_5_V_read(delta_ph_t_1_1_5_V_reg_63938),
.delta_ph_1_2_0_V_read(delta_ph_t_1_2_0_V_reg_63943),
.delta_ph_1_2_1_V_read(delta_ph_t_1_2_1_V_reg_63948),
.delta_ph_1_2_2_V_read(delta_ph_t_1_2_2_V_reg_63953),
.delta_ph_1_2_3_V_read(delta_ph_t_1_2_3_V_reg_63958),
.delta_ph_1_2_4_V_read(delta_ph_t_1_2_4_V_reg_63963),
.delta_ph_1_2_5_V_read(delta_ph_t_1_2_5_V_reg_63968),
.delta_ph_2_0_0_V_read(delta_ph_t_2_0_0_V_reg_63973),
.delta_ph_2_0_1_V_read(delta_ph_t_2_0_1_V_reg_63978),
.delta_ph_2_0_2_V_read(delta_ph_t_2_0_2_V_reg_63983),
.delta_ph_2_0_3_V_read(delta_ph_t_2_0_3_V_reg_63988),
.delta_ph_2_0_4_V_read(delta_ph_t_2_0_4_V_reg_63993),
.delta_ph_2_0_5_V_read(delta_ph_t_2_0_5_V_reg_63998),
.delta_ph_2_1_0_V_read(delta_ph_t_2_1_0_V_reg_64003),
.delta_ph_2_1_1_V_read(delta_ph_t_2_1_1_V_reg_64008),
.delta_ph_2_1_2_V_read(delta_ph_t_2_1_2_V_reg_64013),
.delta_ph_2_1_3_V_read(delta_ph_t_2_1_3_V_reg_64018),
.delta_ph_2_1_4_V_read(delta_ph_t_2_1_4_V_reg_64023),
.delta_ph_2_1_5_V_read(delta_ph_t_2_1_5_V_reg_64028),
.delta_ph_2_2_0_V_read(delta_ph_t_2_2_0_V_reg_64033),
.delta_ph_2_2_1_V_read(delta_ph_t_2_2_1_V_reg_64038),
.delta_ph_2_2_2_V_read(delta_ph_t_2_2_2_V_reg_64043),
.delta_ph_2_2_3_V_read(delta_ph_t_2_2_3_V_reg_64048),
.delta_ph_2_2_4_V_read(delta_ph_t_2_2_4_V_reg_64053),
.delta_ph_2_2_5_V_read(delta_ph_t_2_2_5_V_reg_64058),
.delta_ph_3_0_0_V_read(delta_ph_t_3_0_0_V_reg_64063),
.delta_ph_3_0_1_V_read(delta_ph_t_3_0_1_V_reg_64068),
.delta_ph_3_0_2_V_read(delta_ph_t_3_0_2_V_reg_64073),
.delta_ph_3_0_3_V_read(delta_ph_t_3_0_3_V_reg_64078),
.delta_ph_3_0_4_V_read(delta_ph_t_3_0_4_V_reg_64083),
.delta_ph_3_0_5_V_read(delta_ph_t_3_0_5_V_reg_64088),
.delta_ph_3_1_0_V_read(delta_ph_t_3_1_0_V_reg_64093),
.delta_ph_3_1_1_V_read(delta_ph_t_3_1_1_V_reg_64098),
.delta_ph_3_1_2_V_read(delta_ph_t_3_1_2_V_reg_64103),
.delta_ph_3_1_3_V_read(delta_ph_t_3_1_3_V_reg_64108),
.delta_ph_3_1_4_V_read(delta_ph_t_3_1_4_V_reg_64113),
.delta_ph_3_1_5_V_read(delta_ph_t_3_1_5_V_reg_64118),
.delta_ph_3_2_0_V_read(delta_ph_t_3_2_0_V_reg_64123),
.delta_ph_3_2_1_V_read(delta_ph_t_3_2_1_V_reg_64128),
.delta_ph_3_2_2_V_read(delta_ph_t_3_2_2_V_reg_64133),
.delta_ph_3_2_3_V_read(delta_ph_t_3_2_3_V_reg_64138),
.delta_ph_3_2_4_V_read(delta_ph_t_3_2_4_V_reg_64143),
.delta_ph_3_2_5_V_read(delta_ph_t_3_2_5_V_reg_64148),
.delta_th_0_0_0_V_read(delta_th_t_0_0_0_V_reg_64153),
.delta_th_0_0_1_V_read(delta_th_t_0_0_1_V_reg_64158),
.delta_th_0_0_2_V_read(delta_th_t_0_0_2_V_reg_64163),
.delta_th_0_0_3_V_read(delta_th_t_0_0_3_V_reg_64168),
.delta_th_0_0_4_V_read(delta_th_t_0_0_4_V_reg_64173),
.delta_th_0_0_5_V_read(delta_th_t_0_0_5_V_reg_64178),
.delta_th_0_1_0_V_read(delta_th_t_0_1_0_V_reg_64183),
.delta_th_0_1_1_V_read(delta_th_t_0_1_1_V_reg_64188),
.delta_th_0_1_2_V_read(delta_th_t_0_1_2_V_reg_64193),
.delta_th_0_1_3_V_read(delta_th_t_0_1_3_V_reg_64198),
.delta_th_0_1_4_V_read(delta_th_t_0_1_4_V_reg_64203),
.delta_th_0_1_5_V_read(delta_th_t_0_1_5_V_reg_64208),
.delta_th_0_2_0_V_read(delta_th_t_0_2_0_V_reg_64213),
.delta_th_0_2_1_V_read(delta_th_t_0_2_1_V_reg_64218),
.delta_th_0_2_2_V_read(delta_th_t_0_2_2_V_reg_64223),
.delta_th_0_2_3_V_read(delta_th_t_0_2_3_V_reg_64228),
.delta_th_0_2_4_V_read(delta_th_t_0_2_4_V_reg_64233),
.delta_th_0_2_5_V_read(delta_th_t_0_2_5_V_reg_64238),
.delta_th_1_0_0_V_read(delta_th_t_1_0_0_V_reg_64243),
.delta_th_1_0_1_V_read(delta_th_t_1_0_1_V_reg_64248),
.delta_th_1_0_2_V_read(delta_th_t_1_0_2_V_reg_64253),
.delta_th_1_0_3_V_read(delta_th_t_1_0_3_V_reg_64258),
.delta_th_1_0_4_V_read(delta_th_t_1_0_4_V_reg_64263),
.delta_th_1_0_5_V_read(delta_th_t_1_0_5_V_reg_64268),
.delta_th_1_1_0_V_read(delta_th_t_1_1_0_V_reg_64273),
.delta_th_1_1_1_V_read(delta_th_t_1_1_1_V_reg_64278),
.delta_th_1_1_2_V_read(delta_th_t_1_1_2_V_reg_64283),
.delta_th_1_1_3_V_read(delta_th_t_1_1_3_V_reg_64288),
.delta_th_1_1_4_V_read(delta_th_t_1_1_4_V_reg_64293),
.delta_th_1_1_5_V_read(delta_th_t_1_1_5_V_reg_64298),
.delta_th_1_2_0_V_read(delta_th_t_1_2_0_V_reg_64303),
.delta_th_1_2_1_V_read(delta_th_t_1_2_1_V_reg_64308),
.delta_th_1_2_2_V_read(delta_th_t_1_2_2_V_reg_64313),
.delta_th_1_2_3_V_read(delta_th_t_1_2_3_V_reg_64318),
.delta_th_1_2_4_V_read(delta_th_t_1_2_4_V_reg_64323),
.delta_th_1_2_5_V_read(delta_th_t_1_2_5_V_reg_64328),
.delta_th_2_0_0_V_read(delta_th_t_2_0_0_V_reg_64333),
.delta_th_2_0_1_V_read(delta_th_t_2_0_1_V_reg_64338),
.delta_th_2_0_2_V_read(delta_th_t_2_0_2_V_reg_64343),
.delta_th_2_0_3_V_read(delta_th_t_2_0_3_V_reg_64348),
.delta_th_2_0_4_V_read(delta_th_t_2_0_4_V_reg_64353),
.delta_th_2_0_5_V_read(delta_th_t_2_0_5_V_reg_64358),
.delta_th_2_1_0_V_read(delta_th_t_2_1_0_V_reg_64363),
.delta_th_2_1_1_V_read(delta_th_t_2_1_1_V_reg_64368),
.delta_th_2_1_2_V_read(delta_th_t_2_1_2_V_reg_64373),
.delta_th_2_1_3_V_read(delta_th_t_2_1_3_V_reg_64378),
.delta_th_2_1_4_V_read(delta_th_t_2_1_4_V_reg_64383),
.delta_th_2_1_5_V_read(delta_th_t_2_1_5_V_reg_64388),
.delta_th_2_2_0_V_read(delta_th_t_2_2_0_V_reg_64393),
.delta_th_2_2_1_V_read(delta_th_t_2_2_1_V_reg_64398),
.delta_th_2_2_2_V_read(delta_th_t_2_2_2_V_reg_64403),
.delta_th_2_2_3_V_read(delta_th_t_2_2_3_V_reg_64408),
.delta_th_2_2_4_V_read(delta_th_t_2_2_4_V_reg_64413),
.delta_th_2_2_5_V_read(delta_th_t_2_2_5_V_reg_64418),
.delta_th_3_0_0_V_read(delta_th_t_3_0_0_V_reg_64423),
.delta_th_3_0_1_V_read(delta_th_t_3_0_1_V_reg_64428),
.delta_th_3_0_2_V_read(delta_th_t_3_0_2_V_reg_64433),
.delta_th_3_0_3_V_read(delta_th_t_3_0_3_V_reg_64438),
.delta_th_3_0_4_V_read(delta_th_t_3_0_4_V_reg_64443),
.delta_th_3_0_5_V_read(delta_th_t_3_0_5_V_reg_64448),
.delta_th_3_1_0_V_read(delta_th_t_3_1_0_V_reg_64453),
.delta_th_3_1_1_V_read(delta_th_t_3_1_1_V_reg_64458),
.delta_th_3_1_2_V_read(delta_th_t_3_1_2_V_reg_64463),
.delta_th_3_1_3_V_read(delta_th_t_3_1_3_V_reg_64468),
.delta_th_3_1_4_V_read(delta_th_t_3_1_4_V_reg_64473),
.delta_th_3_1_5_V_read(delta_th_t_3_1_5_V_reg_64478),
.delta_th_3_2_0_V_read(delta_th_t_3_2_0_V_reg_64483),
.delta_th_3_2_1_V_read(delta_th_t_3_2_1_V_reg_64488),
.delta_th_3_2_2_V_read(delta_th_t_3_2_2_V_reg_64493),
.delta_th_3_2_3_V_read(delta_th_t_3_2_3_V_reg_64498),
.delta_th_3_2_4_V_read(delta_th_t_3_2_4_V_reg_64503),
.delta_th_3_2_5_V_read(delta_th_t_3_2_5_V_reg_64508),
.sign_ph_0_0_V_read(sign_ph_t_0_0_V_reg_63373),
.sign_ph_0_1_V_read(sign_ph_t_0_1_V_reg_63378),
.sign_ph_0_2_V_read(sign_ph_t_0_2_V_reg_63383),
.sign_ph_1_0_V_read(sign_ph_t_1_0_V_reg_63388),
.sign_ph_1_1_V_read(sign_ph_t_1_1_V_reg_63393),
.sign_ph_1_2_V_read(sign_ph_t_1_2_V_reg_63398),
.sign_ph_2_0_V_read(sign_ph_t_2_0_V_reg_63403),
.sign_ph_2_1_V_read(sign_ph_t_2_1_V_reg_63408),
.sign_ph_2_2_V_read(sign_ph_t_2_2_V_reg_63413),
.sign_ph_3_0_V_read(sign_ph_t_3_0_V_reg_63418),
.sign_ph_3_1_V_read(sign_ph_t_3_1_V_reg_63423),
.sign_ph_3_2_V_read(sign_ph_t_3_2_V_reg_63428),
.sign_th_0_0_V_read(sign_th_t_0_0_V_reg_63433),
.sign_th_0_1_V_read(sign_th_t_0_1_V_reg_63438),
.sign_th_0_2_V_read(sign_th_t_0_2_V_reg_63443),
.sign_th_1_0_V_read(sign_th_t_1_0_V_reg_63448),
.sign_th_1_1_V_read(sign_th_t_1_1_V_reg_63453),
.sign_th_1_2_V_read(sign_th_t_1_2_V_reg_63458),
.sign_th_2_0_V_read(sign_th_t_2_0_V_reg_63463),
.sign_th_2_1_V_read(sign_th_t_2_1_V_reg_63468),
.sign_th_2_2_V_read(sign_th_t_2_2_V_reg_63473),
.sign_th_3_0_V_read(sign_th_t_3_0_V_reg_63478),
.sign_th_3_1_V_read(sign_th_t_3_1_V_reg_63483),
.sign_th_3_2_V_read(sign_th_t_3_2_V_reg_63488),
.rank_0_0_V_read(rank_t_0_0_V_reg_63493),
.rank_0_1_V_read(rank_t_0_1_V_reg_63498),
.rank_0_2_V_read(rank_t_0_2_V_reg_63503),
.rank_1_0_V_read(rank_t_1_0_V_reg_63508),
.rank_1_1_V_read(rank_t_1_1_V_reg_63513),
.rank_1_2_V_read(rank_t_1_2_V_reg_63518),
.rank_2_0_V_read(rank_t_2_0_V_reg_63523),
.rank_2_1_V_read(rank_t_2_1_V_reg_63528),
.rank_2_2_V_read(rank_t_2_2_V_reg_63533),
.rank_3_0_V_read(rank_t_3_0_V_reg_63538),
.rank_3_1_V_read(rank_t_3_1_V_reg_63543),
.rank_3_2_V_read(rank_t_3_2_V_reg_63548),
.si_0_0_V_read(ap_reg_ppstg_patt_ph_si_0_0_V_reg_62173_pp0_iter6),
.si_0_1_V_read(ap_reg_ppstg_patt_ph_si_0_1_V_reg_62178_pp0_iter6),
.si_0_2_V_read(ap_reg_ppstg_patt_ph_si_0_2_V_reg_62183_pp0_iter6),
.si_1_0_V_read(ap_reg_ppstg_patt_ph_si_1_0_V_reg_62188_pp0_iter6),
.si_1_1_V_read(ap_reg_ppstg_patt_ph_si_1_1_V_reg_62193_pp0_iter6),
.si_1_2_V_read(ap_reg_ppstg_patt_ph_si_1_2_V_reg_62198_pp0_iter6),
.si_2_0_V_read(ap_reg_ppstg_patt_ph_si_2_0_V_reg_62203_pp0_iter6),
.si_2_1_V_read(ap_reg_ppstg_patt_ph_si_2_1_V_reg_62208_pp0_iter6),
.si_2_2_V_read(ap_reg_ppstg_patt_ph_si_2_2_V_reg_62213_pp0_iter6),
.si_3_0_V_read(ap_reg_ppstg_patt_ph_si_3_0_V_reg_62218_pp0_iter6),
.si_3_1_V_read(ap_reg_ppstg_patt_ph_si_3_1_V_reg_62223_pp0_iter6),
.si_3_2_V_read(ap_reg_ppstg_patt_ph_si_3_2_V_reg_62228_pp0_iter6),
.ap_return_0(grp_sp_best_tracks_fu_51719_ap_return_0),
.ap_return_1(grp_sp_best_tracks_fu_51719_ap_return_1),
.ap_return_2(grp_sp_best_tracks_fu_51719_ap_return_2),
.ap_return_3(grp_sp_best_tracks_fu_51719_ap_return_3),
.ap_return_4(grp_sp_best_tracks_fu_51719_ap_return_4),
.ap_return_5(grp_sp_best_tracks_fu_51719_ap_return_5),
.ap_return_6(grp_sp_best_tracks_fu_51719_ap_return_6),
.ap_return_7(grp_sp_best_tracks_fu_51719_ap_return_7),
.ap_return_8(grp_sp_best_tracks_fu_51719_ap_return_8),
.ap_return_9(grp_sp_best_tracks_fu_51719_ap_return_9),
.ap_return_10(grp_sp_best_tracks_fu_51719_ap_return_10),
.ap_return_11(grp_sp_best_tracks_fu_51719_ap_return_11),
.ap_return_12(grp_sp_best_tracks_fu_51719_ap_return_12),
.ap_return_13(grp_sp_best_tracks_fu_51719_ap_return_13),
.ap_return_14(grp_sp_best_tracks_fu_51719_ap_return_14),
.ap_return_15(grp_sp_best_tracks_fu_51719_ap_return_15),
.ap_return_16(grp_sp_best_tracks_fu_51719_ap_return_16),
.ap_return_17(grp_sp_best_tracks_fu_51719_ap_return_17),
.ap_return_18(grp_sp_best_tracks_fu_51719_ap_return_18),
.ap_return_19(grp_sp_best_tracks_fu_51719_ap_return_19),
.ap_return_20(grp_sp_best_tracks_fu_51719_ap_return_20),
.ap_return_21(grp_sp_best_tracks_fu_51719_ap_return_21),
.ap_return_22(grp_sp_best_tracks_fu_51719_ap_return_22),
.ap_return_23(grp_sp_best_tracks_fu_51719_ap_return_23),
.ap_return_24(grp_sp_best_tracks_fu_51719_ap_return_24),
.ap_return_25(grp_sp_best_tracks_fu_51719_ap_return_25),
.ap_return_26(grp_sp_best_tracks_fu_51719_ap_return_26),
.ap_return_27(grp_sp_best_tracks_fu_51719_ap_return_27),
.ap_return_28(grp_sp_best_tracks_fu_51719_ap_return_28),
.ap_return_29(grp_sp_best_tracks_fu_51719_ap_return_29),
.ap_return_30(grp_sp_best_tracks_fu_51719_ap_return_30),
.ap_return_31(grp_sp_best_tracks_fu_51719_ap_return_31),
.ap_return_32(grp_sp_best_tracks_fu_51719_ap_return_32),
.ap_return_33(grp_sp_best_tracks_fu_51719_ap_return_33),
.ap_return_34(grp_sp_best_tracks_fu_51719_ap_return_34),
.ap_return_35(grp_sp_best_tracks_fu_51719_ap_return_35),
.ap_return_36(grp_sp_best_tracks_fu_51719_ap_return_36),
.ap_return_37(grp_sp_best_tracks_fu_51719_ap_return_37),
.ap_return_38(grp_sp_best_tracks_fu_51719_ap_return_38),
.ap_return_39(grp_sp_best_tracks_fu_51719_ap_return_39),
.ap_return_40(grp_sp_best_tracks_fu_51719_ap_return_40),
.ap_return_41(grp_sp_best_tracks_fu_51719_ap_return_41),
.ap_return_42(grp_sp_best_tracks_fu_51719_ap_return_42),
.ap_return_43(grp_sp_best_tracks_fu_51719_ap_return_43),
.ap_return_44(grp_sp_best_tracks_fu_51719_ap_return_44),
.ap_return_45(grp_sp_best_tracks_fu_51719_ap_return_45),
.ap_return_46(grp_sp_best_tracks_fu_51719_ap_return_46),
.ap_return_47(grp_sp_best_tracks_fu_51719_ap_return_47),
.ap_return_48(grp_sp_best_tracks_fu_51719_ap_return_48),
.ap_return_49(grp_sp_best_tracks_fu_51719_ap_return_49),
.ap_return_50(grp_sp_best_tracks_fu_51719_ap_return_50),
.ap_return_51(grp_sp_best_tracks_fu_51719_ap_return_51),
.ap_return_52(grp_sp_best_tracks_fu_51719_ap_return_52),
.ap_return_53(grp_sp_best_tracks_fu_51719_ap_return_53),
.ap_return_54(grp_sp_best_tracks_fu_51719_ap_return_54),
.ap_return_55(grp_sp_best_tracks_fu_51719_ap_return_55),
.ap_return_56(grp_sp_best_tracks_fu_51719_ap_return_56),
.ap_return_57(grp_sp_best_tracks_fu_51719_ap_return_57),
.ap_return_58(grp_sp_best_tracks_fu_51719_ap_return_58),
.ap_return_59(grp_sp_best_tracks_fu_51719_ap_return_59),
.ap_return_60(grp_sp_best_tracks_fu_51719_ap_return_60),
.ap_return_61(grp_sp_best_tracks_fu_51719_ap_return_61),
.ap_return_62(grp_sp_best_tracks_fu_51719_ap_return_62),
.ap_return_63(grp_sp_best_tracks_fu_51719_ap_return_63),
.ap_return_64(grp_sp_best_tracks_fu_51719_ap_return_64),
.ap_return_65(grp_sp_best_tracks_fu_51719_ap_return_65),
.ap_return_66(grp_sp_best_tracks_fu_51719_ap_return_66),
.ap_return_67(grp_sp_best_tracks_fu_51719_ap_return_67),
.ap_return_68(grp_sp_best_tracks_fu_51719_ap_return_68),
.ap_return_69(grp_sp_best_tracks_fu_51719_ap_return_69),
.ap_return_70(grp_sp_best_tracks_fu_51719_ap_return_70),
.ap_return_71(grp_sp_best_tracks_fu_51719_ap_return_71),
.ap_return_72(grp_sp_best_tracks_fu_51719_ap_return_72),
.ap_return_73(grp_sp_best_tracks_fu_51719_ap_return_73),
.ap_return_74(grp_sp_best_tracks_fu_51719_ap_return_74),
.ap_return_75(grp_sp_best_tracks_fu_51719_ap_return_75),
.ap_return_76(grp_sp_best_tracks_fu_51719_ap_return_76),
.ap_return_77(grp_sp_best_tracks_fu_51719_ap_return_77),
.ap_return_78(grp_sp_best_tracks_fu_51719_ap_return_78),
.ap_return_79(grp_sp_best_tracks_fu_51719_ap_return_79),
.ap_return_80(grp_sp_best_tracks_fu_51719_ap_return_80),
.ap_return_81(grp_sp_best_tracks_fu_51719_ap_return_81),
.ap_return_82(grp_sp_best_tracks_fu_51719_ap_return_82),
.ap_return_83(grp_sp_best_tracks_fu_51719_ap_return_83),
.ap_return_84(grp_sp_best_tracks_fu_51719_ap_return_84),
.ap_return_85(grp_sp_best_tracks_fu_51719_ap_return_85),
.ap_return_86(grp_sp_best_tracks_fu_51719_ap_return_86),
.ap_return_87(grp_sp_best_tracks_fu_51719_ap_return_87),
.ap_return_88(grp_sp_best_tracks_fu_51719_ap_return_88),
.ap_return_89(grp_sp_best_tracks_fu_51719_ap_return_89),
.ap_return_90(grp_sp_best_tracks_fu_51719_ap_return_90),
.ap_return_91(grp_sp_best_tracks_fu_51719_ap_return_91),
.ap_return_92(grp_sp_best_tracks_fu_51719_ap_return_92),
.ap_return_93(grp_sp_best_tracks_fu_51719_ap_return_93),
.ap_return_94(grp_sp_best_tracks_fu_51719_ap_return_94),
.ap_return_95(grp_sp_best_tracks_fu_51719_ap_return_95),
.ap_return_96(grp_sp_best_tracks_fu_51719_ap_return_96),
.ap_return_97(grp_sp_best_tracks_fu_51719_ap_return_97),
.ap_return_98(grp_sp_best_tracks_fu_51719_ap_return_98),
.ap_return_99(grp_sp_best_tracks_fu_51719_ap_return_99),
.ap_return_100(grp_sp_best_tracks_fu_51719_ap_return_100),
.ap_return_101(grp_sp_best_tracks_fu_51719_ap_return_101),
.ap_return_102(grp_sp_best_tracks_fu_51719_ap_return_102),
.ap_return_103(grp_sp_best_tracks_fu_51719_ap_return_103),
.ap_return_104(grp_sp_best_tracks_fu_51719_ap_return_104),
.ap_return_105(grp_sp_best_tracks_fu_51719_ap_return_105),
.ap_return_106(grp_sp_best_tracks_fu_51719_ap_return_106),
.ap_return_107(grp_sp_best_tracks_fu_51719_ap_return_107),
.ap_return_108(grp_sp_best_tracks_fu_51719_ap_return_108),
.ap_return_109(grp_sp_best_tracks_fu_51719_ap_return_109),
.ap_return_110(grp_sp_best_tracks_fu_51719_ap_return_110)
);
sp_deltas_sector call_ret_sp_deltas_sector_fu_51987(
.ph_match_0_0_0_V_read(ph_match_t_0_0_0_V_reg_62233),
.ph_match_0_0_1_V_read(ph_match_t_0_0_1_V_reg_62238),
.ph_match_0_0_2_V_read(ph_match_t_0_0_2_V_reg_62243),
.ph_match_0_0_3_V_read(ph_match_t_0_0_3_V_reg_62248),
.ph_match_0_1_0_V_read(ph_match_t_0_1_0_V_reg_62253),
.ph_match_0_1_1_V_read(ph_match_t_0_1_1_V_reg_62258),
.ph_match_0_1_2_V_read(ph_match_t_0_1_2_V_reg_62263),
.ph_match_0_1_3_V_read(ph_match_t_0_1_3_V_reg_62268),
.ph_match_0_2_0_V_read(ph_match_t_0_2_0_V_reg_62273),
.ph_match_0_2_1_V_read(ph_match_t_0_2_1_V_reg_62278),
.ph_match_0_2_2_V_read(ph_match_t_0_2_2_V_reg_62283),
.ph_match_0_2_3_V_read(ph_match_t_0_2_3_V_reg_62288),
.ph_match_1_0_0_V_read(ph_match_t_1_0_0_V_reg_62293),
.ph_match_1_0_1_V_read(ph_match_t_1_0_1_V_reg_62298),
.ph_match_1_0_2_V_read(ph_match_t_1_0_2_V_reg_62303),
.ph_match_1_0_3_V_read(ph_match_t_1_0_3_V_reg_62308),
.ph_match_1_1_0_V_read(ph_match_t_1_1_0_V_reg_62313),
.ph_match_1_1_1_V_read(ph_match_t_1_1_1_V_reg_62318),
.ph_match_1_1_2_V_read(ph_match_t_1_1_2_V_reg_62323),
.ph_match_1_1_3_V_read(ph_match_t_1_1_3_V_reg_62328),
.ph_match_1_2_0_V_read(ph_match_t_1_2_0_V_reg_62333),
.ph_match_1_2_1_V_read(ph_match_t_1_2_1_V_reg_62338),
.ph_match_1_2_2_V_read(ph_match_t_1_2_2_V_reg_62343),
.ph_match_1_2_3_V_read(ph_match_t_1_2_3_V_reg_62348),
.ph_match_2_0_0_V_read(ph_match_t_2_0_0_V_reg_62353),
.ph_match_2_0_1_V_read(ph_match_t_2_0_1_V_reg_62358),
.ph_match_2_0_2_V_read(ph_match_t_2_0_2_V_reg_62363),
.ph_match_2_0_3_V_read(ph_match_t_2_0_3_V_reg_62368),
.ph_match_2_1_0_V_read(ph_match_t_2_1_0_V_reg_62373),
.ph_match_2_1_1_V_read(ph_match_t_2_1_1_V_reg_62378),
.ph_match_2_1_2_V_read(ph_match_t_2_1_2_V_reg_62383),
.ph_match_2_1_3_V_read(ph_match_t_2_1_3_V_reg_62388),
.ph_match_2_2_0_V_read(ph_match_t_2_2_0_V_reg_62393),
.ph_match_2_2_1_V_read(ph_match_t_2_2_1_V_reg_62398),
.ph_match_2_2_2_V_read(ph_match_t_2_2_2_V_reg_62403),
.ph_match_2_2_3_V_read(ph_match_t_2_2_3_V_reg_62408),
.ph_match_3_0_0_V_read(ph_match_t_3_0_0_V_reg_62413),
.ph_match_3_0_1_V_read(ph_match_t_3_0_1_V_reg_62418),
.ph_match_3_0_2_V_read(ph_match_t_3_0_2_V_reg_62423),
.ph_match_3_0_3_V_read(ph_match_t_3_0_3_V_reg_62428),
.ph_match_3_1_0_V_read(ph_match_t_3_1_0_V_reg_62433),
.ph_match_3_1_1_V_read(ph_match_t_3_1_1_V_reg_62438),
.ph_match_3_1_2_V_read(ph_match_t_3_1_2_V_reg_62443),
.ph_match_3_1_3_V_read(ph_match_t_3_1_3_V_reg_62448),
.ph_match_3_2_0_V_read(ph_match_t_3_2_0_V_reg_62453),
.ph_match_3_2_1_V_read(ph_match_t_3_2_1_V_reg_62458),
.ph_match_3_2_2_V_read(ph_match_t_3_2_2_V_reg_62463),
.ph_match_3_2_3_V_read(ph_match_t_3_2_3_V_reg_62468),
.th_match_0_0_1_0_V_read(th_match_t1_0_0_1_0_V_reg_62713),
.th_match_0_0_1_1_V_read(th_match_t1_0_0_1_1_V_reg_62718),
.th_match_0_0_2_0_V_read(th_match_t1_0_0_2_0_V_reg_62723),
.th_match_0_0_2_1_V_read(th_match_t1_0_0_2_1_V_reg_62728),
.th_match_0_0_3_0_V_read(th_match_t1_0_0_3_0_V_reg_62733),
.th_match_0_0_3_1_V_read(th_match_t1_0_0_3_1_V_reg_62738),
.th_match_0_1_1_0_V_read(th_match_t1_0_1_1_0_V_reg_62743),
.th_match_0_1_1_1_V_read(th_match_t1_0_1_1_1_V_reg_62748),
.th_match_0_1_2_0_V_read(th_match_t1_0_1_2_0_V_reg_62753),
.th_match_0_1_2_1_V_read(th_match_t1_0_1_2_1_V_reg_62758),
.th_match_0_1_3_0_V_read(th_match_t1_0_1_3_0_V_reg_62763),
.th_match_0_1_3_1_V_read(th_match_t1_0_1_3_1_V_reg_62768),
.th_match_0_2_1_0_V_read(th_match_t1_0_2_1_0_V_reg_62773),
.th_match_0_2_1_1_V_read(th_match_t1_0_2_1_1_V_reg_62778),
.th_match_0_2_2_0_V_read(th_match_t1_0_2_2_0_V_reg_62783),
.th_match_0_2_2_1_V_read(th_match_t1_0_2_2_1_V_reg_62788),
.th_match_0_2_3_0_V_read(th_match_t1_0_2_3_0_V_reg_62793),
.th_match_0_2_3_1_V_read(th_match_t1_0_2_3_1_V_reg_62798),
.th_match_1_0_1_0_V_read(th_match_t1_1_0_1_0_V_reg_62803),
.th_match_1_0_1_1_V_read(th_match_t1_1_0_1_1_V_reg_62808),
.th_match_1_0_2_0_V_read(th_match_t1_1_0_2_0_V_reg_62813),
.th_match_1_0_2_1_V_read(th_match_t1_1_0_2_1_V_reg_62818),
.th_match_1_0_3_0_V_read(th_match_t1_1_0_3_0_V_reg_62823),
.th_match_1_0_3_1_V_read(th_match_t1_1_0_3_1_V_reg_62828),
.th_match_1_1_1_0_V_read(th_match_t1_1_1_1_0_V_reg_62833),
.th_match_1_1_1_1_V_read(th_match_t1_1_1_1_1_V_reg_62838),
.th_match_1_1_2_0_V_read(th_match_t1_1_1_2_0_V_reg_62843),
.th_match_1_1_2_1_V_read(th_match_t1_1_1_2_1_V_reg_62848),
.th_match_1_1_3_0_V_read(th_match_t1_1_1_3_0_V_reg_62853),
.th_match_1_1_3_1_V_read(th_match_t1_1_1_3_1_V_reg_62858),
.th_match_1_2_1_0_V_read(th_match_t1_1_2_1_0_V_reg_62863),
.th_match_1_2_1_1_V_read(th_match_t1_1_2_1_1_V_reg_62868),
.th_match_1_2_2_0_V_read(th_match_t1_1_2_2_0_V_reg_62873),
.th_match_1_2_2_1_V_read(th_match_t1_1_2_2_1_V_reg_62878),
.th_match_1_2_3_0_V_read(th_match_t1_1_2_3_0_V_reg_62883),
.th_match_1_2_3_1_V_read(th_match_t1_1_2_3_1_V_reg_62888),
.th_match_2_0_0_0_V_read(th_match_t1_2_0_0_0_V_reg_62893),
.th_match_2_0_0_1_V_read(th_match_t1_2_0_0_1_V_reg_62898),
.th_match_2_0_1_0_V_read(th_match_t1_2_0_1_0_V_reg_62903),
.th_match_2_0_1_1_V_read(th_match_t1_2_0_1_1_V_reg_62908),
.th_match_2_0_2_0_V_read(th_match_t1_2_0_2_0_V_reg_62913),
.th_match_2_0_2_1_V_read(th_match_t1_2_0_2_1_V_reg_62918),
.th_match_2_0_3_0_V_read(th_match_t1_2_0_3_0_V_reg_62923),
.th_match_2_0_3_1_V_read(th_match_t1_2_0_3_1_V_reg_62928),
.th_match_2_1_0_0_V_read(th_match_t1_2_1_0_0_V_reg_62933),
.th_match_2_1_0_1_V_read(th_match_t1_2_1_0_1_V_reg_62938),
.th_match_2_1_1_0_V_read(th_match_t1_2_1_1_0_V_reg_62943),
.th_match_2_1_1_1_V_read(th_match_t1_2_1_1_1_V_reg_62948),
.th_match_2_1_2_0_V_read(th_match_t1_2_1_2_0_V_reg_62953),
.th_match_2_1_2_1_V_read(th_match_t1_2_1_2_1_V_reg_62958),
.th_match_2_1_3_0_V_read(th_match_t1_2_1_3_0_V_reg_62963),
.th_match_2_1_3_1_V_read(th_match_t1_2_1_3_1_V_reg_62968),
.th_match_2_2_0_0_V_read(th_match_t1_2_2_0_0_V_reg_62973),
.th_match_2_2_0_1_V_read(th_match_t1_2_2_0_1_V_reg_62978),
.th_match_2_2_1_0_V_read(th_match_t1_2_2_1_0_V_reg_62983),
.th_match_2_2_1_1_V_read(th_match_t1_2_2_1_1_V_reg_62988),
.th_match_2_2_2_0_V_read(th_match_t1_2_2_2_0_V_reg_62993),
.th_match_2_2_2_1_V_read(th_match_t1_2_2_2_1_V_reg_62998),
.th_match_2_2_3_0_V_read(th_match_t1_2_2_3_0_V_reg_63003),
.th_match_2_2_3_1_V_read(th_match_t1_2_2_3_1_V_reg_63008),
.th_match_3_0_0_0_V_read(th_match_t1_3_0_0_0_V_reg_63013),
.th_match_3_0_0_1_V_read(th_match_t1_3_0_0_1_V_reg_63018),
.th_match_3_0_1_0_V_read(th_match_t1_3_0_1_0_V_reg_63023),
.th_match_3_0_1_1_V_read(th_match_t1_3_0_1_1_V_reg_63028),
.th_match_3_0_2_0_V_read(th_match_t1_3_0_2_0_V_reg_63033),
.th_match_3_0_2_1_V_read(th_match_t1_3_0_2_1_V_reg_63038),
.th_match_3_0_3_0_V_read(th_match_t1_3_0_3_0_V_reg_63043),
.th_match_3_0_3_1_V_read(th_match_t1_3_0_3_1_V_reg_63048),
.th_match_3_1_0_0_V_read(th_match_t1_3_1_0_0_V_reg_63053),
.th_match_3_1_0_1_V_read(th_match_t1_3_1_0_1_V_reg_63058),
.th_match_3_1_1_0_V_read(th_match_t1_3_1_1_0_V_reg_63063),
.th_match_3_1_1_1_V_read(th_match_t1_3_1_1_1_V_reg_63068),
.th_match_3_1_2_0_V_read(th_match_t1_3_1_2_0_V_reg_63073),
.th_match_3_1_2_1_V_read(th_match_t1_3_1_2_1_V_reg_63078),
.th_match_3_1_3_0_V_read(th_match_t1_3_1_3_0_V_reg_63083),
.th_match_3_1_3_1_V_read(th_match_t1_3_1_3_1_V_reg_63088),
.th_match_3_2_0_0_V_read(th_match_t1_3_2_0_0_V_reg_63093),
.th_match_3_2_0_1_V_read(th_match_t1_3_2_0_1_V_reg_63098),
.th_match_3_2_1_0_V_read(th_match_t1_3_2_1_0_V_reg_63103),
.th_match_3_2_1_1_V_read(th_match_t1_3_2_1_1_V_reg_63108),
.th_match_3_2_2_0_V_read(th_match_t1_3_2_2_0_V_reg_63113),
.th_match_3_2_2_1_V_read(th_match_t1_3_2_2_1_V_reg_63118),
.th_match_3_2_3_0_V_read(th_match_t1_3_2_3_0_V_reg_63123),
.th_match_3_2_3_1_V_read(th_match_t1_3_2_3_1_V_reg_63128),
.th_match11_0_0_0_V_read(th_match11_t_0_0_0_V_reg_63133),
.th_match11_0_0_1_V_read(th_match11_t_0_0_1_V_reg_63138),
.th_match11_0_0_2_V_read(th_match11_t_0_0_2_V_reg_63143),
.th_match11_0_0_3_V_read(th_match11_t_0_0_3_V_reg_63148),
.th_match11_0_1_0_V_read(th_match11_t_0_1_0_V_reg_63153),
.th_match11_0_1_1_V_read(th_match11_t_0_1_1_V_reg_63158),
.th_match11_0_1_2_V_read(th_match11_t_0_1_2_V_reg_63163),
.th_match11_0_1_3_V_read(th_match11_t_0_1_3_V_reg_63168),
.th_match11_0_2_0_V_read(th_match11_t_0_2_0_V_reg_63173),
.th_match11_0_2_1_V_read(th_match11_t_0_2_1_V_reg_63178),
.th_match11_0_2_2_V_read(th_match11_t_0_2_2_V_reg_63183),
.th_match11_0_2_3_V_read(th_match11_t_0_2_3_V_reg_63188),
.th_match11_1_0_0_V_read(th_match11_t_1_0_0_V_reg_63193),
.th_match11_1_0_1_V_read(th_match11_t_1_0_1_V_reg_63198),
.th_match11_1_0_2_V_read(th_match11_t_1_0_2_V_reg_63203),
.th_match11_1_0_3_V_read(th_match11_t_1_0_3_V_reg_63208),
.th_match11_1_1_0_V_read(th_match11_t_1_1_0_V_reg_63213),
.th_match11_1_1_1_V_read(th_match11_t_1_1_1_V_reg_63218),
.th_match11_1_1_2_V_read(th_match11_t_1_1_2_V_reg_63223),
.th_match11_1_1_3_V_read(th_match11_t_1_1_3_V_reg_63228),
.th_match11_1_2_0_V_read(th_match11_t_1_2_0_V_reg_63233),
.th_match11_1_2_1_V_read(th_match11_t_1_2_1_V_reg_63238),
.th_match11_1_2_2_V_read(th_match11_t_1_2_2_V_reg_63243),
.th_match11_1_2_3_V_read(th_match11_t_1_2_3_V_reg_63248),
.cpat_match_0_0_0_V_read(cpat_match_t_0_0_0_V_reg_62473),
.cpat_match_0_0_1_V_read(cpat_match_t_0_0_1_V_reg_62478),
.cpat_match_0_0_2_V_read(cpat_match_t_0_0_2_V_reg_62483),
.cpat_match_0_0_3_V_read(cpat_match_t_0_0_3_V_reg_62488),
.cpat_match_0_1_0_V_read(cpat_match_t_0_1_0_V_reg_62493),
.cpat_match_0_1_1_V_read(cpat_match_t_0_1_1_V_reg_62498),
.cpat_match_0_1_2_V_read(cpat_match_t_0_1_2_V_reg_62503),
.cpat_match_0_1_3_V_read(cpat_match_t_0_1_3_V_reg_62508),
.cpat_match_0_2_0_V_read(cpat_match_t_0_2_0_V_reg_62513),
.cpat_match_0_2_1_V_read(cpat_match_t_0_2_1_V_reg_62518),
.cpat_match_0_2_2_V_read(cpat_match_t_0_2_2_V_reg_62523),
.cpat_match_0_2_3_V_read(cpat_match_t_0_2_3_V_reg_62528),
.cpat_match_1_0_0_V_read(cpat_match_t_1_0_0_V_reg_62533),
.cpat_match_1_0_1_V_read(cpat_match_t_1_0_1_V_reg_62538),
.cpat_match_1_0_2_V_read(cpat_match_t_1_0_2_V_reg_62543),
.cpat_match_1_0_3_V_read(cpat_match_t_1_0_3_V_reg_62548),
.cpat_match_1_1_0_V_read(cpat_match_t_1_1_0_V_reg_62553),
.cpat_match_1_1_1_V_read(cpat_match_t_1_1_1_V_reg_62558),
.cpat_match_1_1_2_V_read(cpat_match_t_1_1_2_V_reg_62563),
.cpat_match_1_1_3_V_read(cpat_match_t_1_1_3_V_reg_62568),
.cpat_match_1_2_0_V_read(cpat_match_t_1_2_0_V_reg_62573),
.cpat_match_1_2_1_V_read(cpat_match_t_1_2_1_V_reg_62578),
.cpat_match_1_2_2_V_read(cpat_match_t_1_2_2_V_reg_62583),
.cpat_match_1_2_3_V_read(cpat_match_t_1_2_3_V_reg_62588),
.cpat_match_2_0_0_V_read(cpat_match_t_2_0_0_V_reg_62593),
.cpat_match_2_0_1_V_read(cpat_match_t_2_0_1_V_reg_62598),
.cpat_match_2_0_2_V_read(cpat_match_t_2_0_2_V_reg_62603),
.cpat_match_2_0_3_V_read(cpat_match_t_2_0_3_V_reg_62608),
.cpat_match_2_1_0_V_read(cpat_match_t_2_1_0_V_reg_62613),
.cpat_match_2_1_1_V_read(cpat_match_t_2_1_1_V_reg_62618),
.cpat_match_2_1_2_V_read(cpat_match_t_2_1_2_V_reg_62623),
.cpat_match_2_1_3_V_read(cpat_match_t_2_1_3_V_reg_62628),
.cpat_match_2_2_0_V_read(cpat_match_t_2_2_0_V_reg_62633),
.cpat_match_2_2_1_V_read(cpat_match_t_2_2_1_V_reg_62638),
.cpat_match_2_2_2_V_read(cpat_match_t_2_2_2_V_reg_62643),
.cpat_match_2_2_3_V_read(cpat_match_t_2_2_3_V_reg_62648),
.cpat_match_3_0_0_V_read(cpat_match_t_3_0_0_V_reg_62653),
.cpat_match_3_0_1_V_read(cpat_match_t_3_0_1_V_reg_62658),
.cpat_match_3_0_2_V_read(cpat_match_t_3_0_2_V_reg_62663),
.cpat_match_3_0_3_V_read(cpat_match_t_3_0_3_V_reg_62668),
.cpat_match_3_1_0_V_read(cpat_match_t_3_1_0_V_reg_62673),
.cpat_match_3_1_1_V_read(cpat_match_t_3_1_1_V_reg_62678),
.cpat_match_3_1_2_V_read(cpat_match_t_3_1_2_V_reg_62683),
.cpat_match_3_1_3_V_read(cpat_match_t_3_1_3_V_reg_62688),
.cpat_match_3_2_0_V_read(cpat_match_t_3_2_0_V_reg_62693),
.cpat_match_3_2_1_V_read(cpat_match_t_3_2_1_V_reg_62698),
.cpat_match_3_2_2_V_read(cpat_match_t_3_2_2_V_reg_62703),
.cpat_match_3_2_3_V_read(cpat_match_t_3_2_3_V_reg_62708),
.ap_return_0(call_ret_sp_deltas_sector_fu_51987_ap_return_0),
.ap_return_1(call_ret_sp_deltas_sector_fu_51987_ap_return_1),
.ap_return_2(call_ret_sp_deltas_sector_fu_51987_ap_return_2),
.ap_return_3(call_ret_sp_deltas_sector_fu_51987_ap_return_3),
.ap_return_4(call_ret_sp_deltas_sector_fu_51987_ap_return_4),
.ap_return_5(call_ret_sp_deltas_sector_fu_51987_ap_return_5),
.ap_return_6(call_ret_sp_deltas_sector_fu_51987_ap_return_6),
.ap_return_7(call_ret_sp_deltas_sector_fu_51987_ap_return_7),
.ap_return_8(call_ret_sp_deltas_sector_fu_51987_ap_return_8),
.ap_return_9(call_ret_sp_deltas_sector_fu_51987_ap_return_9),
.ap_return_10(call_ret_sp_deltas_sector_fu_51987_ap_return_10),
.ap_return_11(call_ret_sp_deltas_sector_fu_51987_ap_return_11),
.ap_return_12(call_ret_sp_deltas_sector_fu_51987_ap_return_12),
.ap_return_13(call_ret_sp_deltas_sector_fu_51987_ap_return_13),
.ap_return_14(call_ret_sp_deltas_sector_fu_51987_ap_return_14),
.ap_return_15(call_ret_sp_deltas_sector_fu_51987_ap_return_15),
.ap_return_16(call_ret_sp_deltas_sector_fu_51987_ap_return_16),
.ap_return_17(call_ret_sp_deltas_sector_fu_51987_ap_return_17),
.ap_return_18(call_ret_sp_deltas_sector_fu_51987_ap_return_18),
.ap_return_19(call_ret_sp_deltas_sector_fu_51987_ap_return_19),
.ap_return_20(call_ret_sp_deltas_sector_fu_51987_ap_return_20),
.ap_return_21(call_ret_sp_deltas_sector_fu_51987_ap_return_21),
.ap_return_22(call_ret_sp_deltas_sector_fu_51987_ap_return_22),
.ap_return_23(call_ret_sp_deltas_sector_fu_51987_ap_return_23),
.ap_return_24(call_ret_sp_deltas_sector_fu_51987_ap_return_24),
.ap_return_25(call_ret_sp_deltas_sector_fu_51987_ap_return_25),
.ap_return_26(call_ret_sp_deltas_sector_fu_51987_ap_return_26),
.ap_return_27(call_ret_sp_deltas_sector_fu_51987_ap_return_27),
.ap_return_28(call_ret_sp_deltas_sector_fu_51987_ap_return_28),
.ap_return_29(call_ret_sp_deltas_sector_fu_51987_ap_return_29),
.ap_return_30(call_ret_sp_deltas_sector_fu_51987_ap_return_30),
.ap_return_31(call_ret_sp_deltas_sector_fu_51987_ap_return_31),
.ap_return_32(call_ret_sp_deltas_sector_fu_51987_ap_return_32),
.ap_return_33(call_ret_sp_deltas_sector_fu_51987_ap_return_33),
.ap_return_34(call_ret_sp_deltas_sector_fu_51987_ap_return_34),
.ap_return_35(call_ret_sp_deltas_sector_fu_51987_ap_return_35),
.ap_return_36(call_ret_sp_deltas_sector_fu_51987_ap_return_36),
.ap_return_37(call_ret_sp_deltas_sector_fu_51987_ap_return_37),
.ap_return_38(call_ret_sp_deltas_sector_fu_51987_ap_return_38),
.ap_return_39(call_ret_sp_deltas_sector_fu_51987_ap_return_39),
.ap_return_40(call_ret_sp_deltas_sector_fu_51987_ap_return_40),
.ap_return_41(call_ret_sp_deltas_sector_fu_51987_ap_return_41),
.ap_return_42(call_ret_sp_deltas_sector_fu_51987_ap_return_42),
.ap_return_43(call_ret_sp_deltas_sector_fu_51987_ap_return_43),
.ap_return_44(call_ret_sp_deltas_sector_fu_51987_ap_return_44),
.ap_return_45(call_ret_sp_deltas_sector_fu_51987_ap_return_45),
.ap_return_46(call_ret_sp_deltas_sector_fu_51987_ap_return_46),
.ap_return_47(call_ret_sp_deltas_sector_fu_51987_ap_return_47),
.ap_return_48(call_ret_sp_deltas_sector_fu_51987_ap_return_48),
.ap_return_49(call_ret_sp_deltas_sector_fu_51987_ap_return_49),
.ap_return_50(call_ret_sp_deltas_sector_fu_51987_ap_return_50),
.ap_return_51(call_ret_sp_deltas_sector_fu_51987_ap_return_51),
.ap_return_52(call_ret_sp_deltas_sector_fu_51987_ap_return_52),
.ap_return_53(call_ret_sp_deltas_sector_fu_51987_ap_return_53),
.ap_return_54(call_ret_sp_deltas_sector_fu_51987_ap_return_54),
.ap_return_55(call_ret_sp_deltas_sector_fu_51987_ap_return_55),
.ap_return_56(call_ret_sp_deltas_sector_fu_51987_ap_return_56),
.ap_return_57(call_ret_sp_deltas_sector_fu_51987_ap_return_57),
.ap_return_58(call_ret_sp_deltas_sector_fu_51987_ap_return_58),
.ap_return_59(call_ret_sp_deltas_sector_fu_51987_ap_return_59),
.ap_return_60(call_ret_sp_deltas_sector_fu_51987_ap_return_60),
.ap_return_61(call_ret_sp_deltas_sector_fu_51987_ap_return_61),
.ap_return_62(call_ret_sp_deltas_sector_fu_51987_ap_return_62),
.ap_return_63(call_ret_sp_deltas_sector_fu_51987_ap_return_63),
.ap_return_64(call_ret_sp_deltas_sector_fu_51987_ap_return_64),
.ap_return_65(call_ret_sp_deltas_sector_fu_51987_ap_return_65),
.ap_return_66(call_ret_sp_deltas_sector_fu_51987_ap_return_66),
.ap_return_67(call_ret_sp_deltas_sector_fu_51987_ap_return_67),
.ap_return_68(call_ret_sp_deltas_sector_fu_51987_ap_return_68),
.ap_return_69(call_ret_sp_deltas_sector_fu_51987_ap_return_69),
.ap_return_70(call_ret_sp_deltas_sector_fu_51987_ap_return_70),
.ap_return_71(call_ret_sp_deltas_sector_fu_51987_ap_return_71),
.ap_return_72(call_ret_sp_deltas_sector_fu_51987_ap_return_72),
.ap_return_73(call_ret_sp_deltas_sector_fu_51987_ap_return_73),
.ap_return_74(call_ret_sp_deltas_sector_fu_51987_ap_return_74),
.ap_return_75(call_ret_sp_deltas_sector_fu_51987_ap_return_75),
.ap_return_76(call_ret_sp_deltas_sector_fu_51987_ap_return_76),
.ap_return_77(call_ret_sp_deltas_sector_fu_51987_ap_return_77),
.ap_return_78(call_ret_sp_deltas_sector_fu_51987_ap_return_78),
.ap_return_79(call_ret_sp_deltas_sector_fu_51987_ap_return_79),
.ap_return_80(call_ret_sp_deltas_sector_fu_51987_ap_return_80),
.ap_return_81(call_ret_sp_deltas_sector_fu_51987_ap_return_81),
.ap_return_82(call_ret_sp_deltas_sector_fu_51987_ap_return_82),
.ap_return_83(call_ret_sp_deltas_sector_fu_51987_ap_return_83),
.ap_return_84(call_ret_sp_deltas_sector_fu_51987_ap_return_84),
.ap_return_85(call_ret_sp_deltas_sector_fu_51987_ap_return_85),
.ap_return_86(call_ret_sp_deltas_sector_fu_51987_ap_return_86),
.ap_return_87(call_ret_sp_deltas_sector_fu_51987_ap_return_87),
.ap_return_88(call_ret_sp_deltas_sector_fu_51987_ap_return_88),
.ap_return_89(call_ret_sp_deltas_sector_fu_51987_ap_return_89),
.ap_return_90(call_ret_sp_deltas_sector_fu_51987_ap_return_90),
.ap_return_91(call_ret_sp_deltas_sector_fu_51987_ap_return_91),
.ap_return_92(call_ret_sp_deltas_sector_fu_51987_ap_return_92),
.ap_return_93(call_ret_sp_deltas_sector_fu_51987_ap_return_93),
.ap_return_94(call_ret_sp_deltas_sector_fu_51987_ap_return_94),
.ap_return_95(call_ret_sp_deltas_sector_fu_51987_ap_return_95),
.ap_return_96(call_ret_sp_deltas_sector_fu_51987_ap_return_96),
.ap_return_97(call_ret_sp_deltas_sector_fu_51987_ap_return_97),
.ap_return_98(call_ret_sp_deltas_sector_fu_51987_ap_return_98),
.ap_return_99(call_ret_sp_deltas_sector_fu_51987_ap_return_99),
.ap_return_100(call_ret_sp_deltas_sector_fu_51987_ap_return_100),
.ap_return_101(call_ret_sp_deltas_sector_fu_51987_ap_return_101),
.ap_return_102(call_ret_sp_deltas_sector_fu_51987_ap_return_102),
.ap_return_103(call_ret_sp_deltas_sector_fu_51987_ap_return_103),
.ap_return_104(call_ret_sp_deltas_sector_fu_51987_ap_return_104),
.ap_return_105(call_ret_sp_deltas_sector_fu_51987_ap_return_105),
.ap_return_106(call_ret_sp_deltas_sector_fu_51987_ap_return_106),
.ap_return_107(call_ret_sp_deltas_sector_fu_51987_ap_return_107),
.ap_return_108(call_ret_sp_deltas_sector_fu_51987_ap_return_108),
.ap_return_109(call_ret_sp_deltas_sector_fu_51987_ap_return_109),
.ap_return_110(call_ret_sp_deltas_sector_fu_51987_ap_return_110),
.ap_return_111(call_ret_sp_deltas_sector_fu_51987_ap_return_111),
.ap_return_112(call_ret_sp_deltas_sector_fu_51987_ap_return_112),
.ap_return_113(call_ret_sp_deltas_sector_fu_51987_ap_return_113),
.ap_return_114(call_ret_sp_deltas_sector_fu_51987_ap_return_114),
.ap_return_115(call_ret_sp_deltas_sector_fu_51987_ap_return_115),
.ap_return_116(call_ret_sp_deltas_sector_fu_51987_ap_return_116),
.ap_return_117(call_ret_sp_deltas_sector_fu_51987_ap_return_117),
.ap_return_118(call_ret_sp_deltas_sector_fu_51987_ap_return_118),
.ap_return_119(call_ret_sp_deltas_sector_fu_51987_ap_return_119),
.ap_return_120(call_ret_sp_deltas_sector_fu_51987_ap_return_120),
.ap_return_121(call_ret_sp_deltas_sector_fu_51987_ap_return_121),
.ap_return_122(call_ret_sp_deltas_sector_fu_51987_ap_return_122),
.ap_return_123(call_ret_sp_deltas_sector_fu_51987_ap_return_123),
.ap_return_124(call_ret_sp_deltas_sector_fu_51987_ap_return_124),
.ap_return_125(call_ret_sp_deltas_sector_fu_51987_ap_return_125),
.ap_return_126(call_ret_sp_deltas_sector_fu_51987_ap_return_126),
.ap_return_127(call_ret_sp_deltas_sector_fu_51987_ap_return_127),
.ap_return_128(call_ret_sp_deltas_sector_fu_51987_ap_return_128),
.ap_return_129(call_ret_sp_deltas_sector_fu_51987_ap_return_129),
.ap_return_130(call_ret_sp_deltas_sector_fu_51987_ap_return_130),
.ap_return_131(call_ret_sp_deltas_sector_fu_51987_ap_return_131),
.ap_return_132(call_ret_sp_deltas_sector_fu_51987_ap_return_132),
.ap_return_133(call_ret_sp_deltas_sector_fu_51987_ap_return_133),
.ap_return_134(call_ret_sp_deltas_sector_fu_51987_ap_return_134),
.ap_return_135(call_ret_sp_deltas_sector_fu_51987_ap_return_135),
.ap_return_136(call_ret_sp_deltas_sector_fu_51987_ap_return_136),
.ap_return_137(call_ret_sp_deltas_sector_fu_51987_ap_return_137),
.ap_return_138(call_ret_sp_deltas_sector_fu_51987_ap_return_138),
.ap_return_139(call_ret_sp_deltas_sector_fu_51987_ap_return_139),
.ap_return_140(call_ret_sp_deltas_sector_fu_51987_ap_return_140),
.ap_return_141(call_ret_sp_deltas_sector_fu_51987_ap_return_141),
.ap_return_142(call_ret_sp_deltas_sector_fu_51987_ap_return_142),
.ap_return_143(call_ret_sp_deltas_sector_fu_51987_ap_return_143),
.ap_return_144(call_ret_sp_deltas_sector_fu_51987_ap_return_144),
.ap_return_145(call_ret_sp_deltas_sector_fu_51987_ap_return_145),
.ap_return_146(call_ret_sp_deltas_sector_fu_51987_ap_return_146),
.ap_return_147(call_ret_sp_deltas_sector_fu_51987_ap_return_147),
.ap_return_148(call_ret_sp_deltas_sector_fu_51987_ap_return_148),
.ap_return_149(call_ret_sp_deltas_sector_fu_51987_ap_return_149),
.ap_return_150(call_ret_sp_deltas_sector_fu_51987_ap_return_150),
.ap_return_151(call_ret_sp_deltas_sector_fu_51987_ap_return_151),
.ap_return_152(call_ret_sp_deltas_sector_fu_51987_ap_return_152),
.ap_return_153(call_ret_sp_deltas_sector_fu_51987_ap_return_153),
.ap_return_154(call_ret_sp_deltas_sector_fu_51987_ap_return_154),
.ap_return_155(call_ret_sp_deltas_sector_fu_51987_ap_return_155),
.ap_return_156(call_ret_sp_deltas_sector_fu_51987_ap_return_156),
.ap_return_157(call_ret_sp_deltas_sector_fu_51987_ap_return_157),
.ap_return_158(call_ret_sp_deltas_sector_fu_51987_ap_return_158),
.ap_return_159(call_ret_sp_deltas_sector_fu_51987_ap_return_159),
.ap_return_160(call_ret_sp_deltas_sector_fu_51987_ap_return_160),
.ap_return_161(call_ret_sp_deltas_sector_fu_51987_ap_return_161),
.ap_return_162(call_ret_sp_deltas_sector_fu_51987_ap_return_162),
.ap_return_163(call_ret_sp_deltas_sector_fu_51987_ap_return_163),
.ap_return_164(call_ret_sp_deltas_sector_fu_51987_ap_return_164),
.ap_return_165(call_ret_sp_deltas_sector_fu_51987_ap_return_165),
.ap_return_166(call_ret_sp_deltas_sector_fu_51987_ap_return_166),
.ap_return_167(call_ret_sp_deltas_sector_fu_51987_ap_return_167),
.ap_return_168(call_ret_sp_deltas_sector_fu_51987_ap_return_168),
.ap_return_169(call_ret_sp_deltas_sector_fu_51987_ap_return_169),
.ap_return_170(call_ret_sp_deltas_sector_fu_51987_ap_return_170),
.ap_return_171(call_ret_sp_deltas_sector_fu_51987_ap_return_171),
.ap_return_172(call_ret_sp_deltas_sector_fu_51987_ap_return_172),
.ap_return_173(call_ret_sp_deltas_sector_fu_51987_ap_return_173),
.ap_return_174(call_ret_sp_deltas_sector_fu_51987_ap_return_174),
.ap_return_175(call_ret_sp_deltas_sector_fu_51987_ap_return_175),
.ap_return_176(call_ret_sp_deltas_sector_fu_51987_ap_return_176),
.ap_return_177(call_ret_sp_deltas_sector_fu_51987_ap_return_177),
.ap_return_178(call_ret_sp_deltas_sector_fu_51987_ap_return_178),
.ap_return_179(call_ret_sp_deltas_sector_fu_51987_ap_return_179),
.ap_return_180(call_ret_sp_deltas_sector_fu_51987_ap_return_180),
.ap_return_181(call_ret_sp_deltas_sector_fu_51987_ap_return_181),
.ap_return_182(call_ret_sp_deltas_sector_fu_51987_ap_return_182),
.ap_return_183(call_ret_sp_deltas_sector_fu_51987_ap_return_183),
.ap_return_184(call_ret_sp_deltas_sector_fu_51987_ap_return_184),
.ap_return_185(call_ret_sp_deltas_sector_fu_51987_ap_return_185),
.ap_return_186(call_ret_sp_deltas_sector_fu_51987_ap_return_186),
.ap_return_187(call_ret_sp_deltas_sector_fu_51987_ap_return_187),
.ap_return_188(call_ret_sp_deltas_sector_fu_51987_ap_return_188),
.ap_return_189(call_ret_sp_deltas_sector_fu_51987_ap_return_189),
.ap_return_190(call_ret_sp_deltas_sector_fu_51987_ap_return_190),
.ap_return_191(call_ret_sp_deltas_sector_fu_51987_ap_return_191),
.ap_return_192(call_ret_sp_deltas_sector_fu_51987_ap_return_192),
.ap_return_193(call_ret_sp_deltas_sector_fu_51987_ap_return_193),
.ap_return_194(call_ret_sp_deltas_sector_fu_51987_ap_return_194),
.ap_return_195(call_ret_sp_deltas_sector_fu_51987_ap_return_195),
.ap_return_196(call_ret_sp_deltas_sector_fu_51987_ap_return_196),
.ap_return_197(call_ret_sp_deltas_sector_fu_51987_ap_return_197),
.ap_return_198(call_ret_sp_deltas_sector_fu_51987_ap_return_198),
.ap_return_199(call_ret_sp_deltas_sector_fu_51987_ap_return_199),
.ap_return_200(call_ret_sp_deltas_sector_fu_51987_ap_return_200),
.ap_return_201(call_ret_sp_deltas_sector_fu_51987_ap_return_201),
.ap_return_202(call_ret_sp_deltas_sector_fu_51987_ap_return_202),
.ap_return_203(call_ret_sp_deltas_sector_fu_51987_ap_return_203),
.ap_return_204(call_ret_sp_deltas_sector_fu_51987_ap_return_204),
.ap_return_205(call_ret_sp_deltas_sector_fu_51987_ap_return_205),
.ap_return_206(call_ret_sp_deltas_sector_fu_51987_ap_return_206),
.ap_return_207(call_ret_sp_deltas_sector_fu_51987_ap_return_207),
.ap_return_208(call_ret_sp_deltas_sector_fu_51987_ap_return_208),
.ap_return_209(call_ret_sp_deltas_sector_fu_51987_ap_return_209),
.ap_return_210(call_ret_sp_deltas_sector_fu_51987_ap_return_210),
.ap_return_211(call_ret_sp_deltas_sector_fu_51987_ap_return_211),
.ap_return_212(call_ret_sp_deltas_sector_fu_51987_ap_return_212),
.ap_return_213(call_ret_sp_deltas_sector_fu_51987_ap_return_213),
.ap_return_214(call_ret_sp_deltas_sector_fu_51987_ap_return_214),
.ap_return_215(call_ret_sp_deltas_sector_fu_51987_ap_return_215),
.ap_return_216(call_ret_sp_deltas_sector_fu_51987_ap_return_216),
.ap_return_217(call_ret_sp_deltas_sector_fu_51987_ap_return_217),
.ap_return_218(call_ret_sp_deltas_sector_fu_51987_ap_return_218),
.ap_return_219(call_ret_sp_deltas_sector_fu_51987_ap_return_219),
.ap_return_220(call_ret_sp_deltas_sector_fu_51987_ap_return_220),
.ap_return_221(call_ret_sp_deltas_sector_fu_51987_ap_return_221),
.ap_return_222(call_ret_sp_deltas_sector_fu_51987_ap_return_222),
.ap_return_223(call_ret_sp_deltas_sector_fu_51987_ap_return_223),
.ap_return_224(call_ret_sp_deltas_sector_fu_51987_ap_return_224),
.ap_return_225(call_ret_sp_deltas_sector_fu_51987_ap_return_225),
.ap_return_226(call_ret_sp_deltas_sector_fu_51987_ap_return_226),
.ap_return_227(call_ret_sp_deltas_sector_fu_51987_ap_return_227),
.ap_return_228(call_ret_sp_deltas_sector_fu_51987_ap_return_228),
.ap_return_229(call_ret_sp_deltas_sector_fu_51987_ap_return_229),
.ap_return_230(call_ret_sp_deltas_sector_fu_51987_ap_return_230),
.ap_return_231(call_ret_sp_deltas_sector_fu_51987_ap_return_231),
.ap_return_232(call_ret_sp_deltas_sector_fu_51987_ap_return_232),
.ap_return_233(call_ret_sp_deltas_sector_fu_51987_ap_return_233),
.ap_return_234(call_ret_sp_deltas_sector_fu_51987_ap_return_234),
.ap_return_235(call_ret_sp_deltas_sector_fu_51987_ap_return_235),
.ap_return_236(call_ret_sp_deltas_sector_fu_51987_ap_return_236),
.ap_return_237(call_ret_sp_deltas_sector_fu_51987_ap_return_237),
.ap_return_238(call_ret_sp_deltas_sector_fu_51987_ap_return_238),
.ap_return_239(call_ret_sp_deltas_sector_fu_51987_ap_return_239),
.ap_return_240(call_ret_sp_deltas_sector_fu_51987_ap_return_240),
.ap_return_241(call_ret_sp_deltas_sector_fu_51987_ap_return_241),
.ap_return_242(call_ret_sp_deltas_sector_fu_51987_ap_return_242),
.ap_return_243(call_ret_sp_deltas_sector_fu_51987_ap_return_243),
.ap_return_244(call_ret_sp_deltas_sector_fu_51987_ap_return_244),
.ap_return_245(call_ret_sp_deltas_sector_fu_51987_ap_return_245),
.ap_return_246(call_ret_sp_deltas_sector_fu_51987_ap_return_246),
.ap_return_247(call_ret_sp_deltas_sector_fu_51987_ap_return_247),
.ap_return_248(call_ret_sp_deltas_sector_fu_51987_ap_return_248),
.ap_return_249(call_ret_sp_deltas_sector_fu_51987_ap_return_249),
.ap_return_250(call_ret_sp_deltas_sector_fu_51987_ap_return_250),
.ap_return_251(call_ret_sp_deltas_sector_fu_51987_ap_return_251)
);
sp_sort_sector grp_sp_sort_sector_fu_52195(
.ap_clk(ap_clk),
.ap_rst(ap_rst),
.ph_rank_0_0_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_0),
.ph_rank_0_1_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_1),
.ph_rank_0_2_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_2),
.ph_rank_0_3_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_3),
.ph_rank_0_4_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_4),
.ph_rank_0_5_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_5),
.ph_rank_0_6_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_6),
.ph_rank_0_7_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_7),
.ph_rank_0_8_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_8),
.ph_rank_0_9_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_9),
.ph_rank_0_10_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_10),
.ph_rank_0_11_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_11),
.ph_rank_0_12_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_12),
.ph_rank_0_13_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_13),
.ph_rank_0_14_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_14),
.ph_rank_0_15_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_15),
.ph_rank_0_16_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_16),
.ph_rank_0_17_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_17),
.ph_rank_0_18_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_18),
.ph_rank_0_19_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_19),
.ph_rank_0_20_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_20),
.ph_rank_0_21_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_21),
.ph_rank_0_22_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_22),
.ph_rank_0_23_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_23),
.ph_rank_0_24_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_24),
.ph_rank_0_25_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_25),
.ph_rank_0_26_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_26),
.ph_rank_0_27_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_27),
.ph_rank_0_28_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_28),
.ph_rank_0_29_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_29),
.ph_rank_0_30_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_30),
.ph_rank_0_31_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_31),
.ph_rank_0_32_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_32),
.ph_rank_0_33_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_33),
.ph_rank_0_34_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_34),
.ph_rank_0_35_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_35),
.ph_rank_0_36_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_36),
.ph_rank_0_37_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_37),
.ph_rank_0_38_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_38),
.ph_rank_0_39_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_39),
.ph_rank_0_40_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_40),
.ph_rank_0_41_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_41),
.ph_rank_0_42_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_42),
.ph_rank_0_43_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_43),
.ph_rank_0_44_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_44),
.ph_rank_0_45_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_45),
.ph_rank_0_46_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_46),
.ph_rank_0_47_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_47),
.ph_rank_0_48_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_48),
.ph_rank_0_49_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_49),
.ph_rank_0_50_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_50),
.ph_rank_0_51_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_51),
.ph_rank_0_52_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_52),
.ph_rank_0_53_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_53),
.ph_rank_0_54_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_54),
.ph_rank_0_55_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_55),
.ph_rank_0_56_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_56),
.ph_rank_0_57_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_57),
.ph_rank_0_58_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_58),
.ph_rank_0_59_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_59),
.ph_rank_0_60_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_60),
.ph_rank_0_61_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_61),
.ph_rank_0_62_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_62),
.ph_rank_0_63_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_63),
.ph_rank_0_64_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_64),
.ph_rank_0_65_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_65),
.ph_rank_0_66_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_66),
.ph_rank_0_67_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_67),
.ph_rank_0_68_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_68),
.ph_rank_0_69_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_69),
.ph_rank_0_70_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_70),
.ph_rank_0_71_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_71),
.ph_rank_0_72_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_72),
.ph_rank_0_73_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_73),
.ph_rank_0_74_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_74),
.ph_rank_0_75_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_75),
.ph_rank_0_76_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_76),
.ph_rank_0_77_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_77),
.ph_rank_0_78_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_78),
.ph_rank_0_79_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_79),
.ph_rank_0_80_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_80),
.ph_rank_0_81_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_81),
.ph_rank_0_82_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_82),
.ph_rank_0_83_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_83),
.ph_rank_0_84_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_84),
.ph_rank_0_85_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_85),
.ph_rank_0_86_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_86),
.ph_rank_0_87_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_87),
.ph_rank_0_88_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_88),
.ph_rank_0_89_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_89),
.ph_rank_0_90_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_90),
.ph_rank_0_91_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_91),
.ph_rank_0_92_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_92),
.ph_rank_0_93_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_93),
.ph_rank_0_94_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_94),
.ph_rank_0_95_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_95),
.ph_rank_0_96_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_96),
.ph_rank_0_97_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_97),
.ph_rank_0_98_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_98),
.ph_rank_0_99_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_99),
.ph_rank_0_100_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_100),
.ph_rank_0_101_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_101),
.ph_rank_0_102_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_102),
.ph_rank_0_103_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_103),
.ph_rank_0_104_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_104),
.ph_rank_0_105_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_105),
.ph_rank_0_106_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_106),
.ph_rank_0_107_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_107),
.ph_rank_0_108_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_108),
.ph_rank_0_109_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_109),
.ph_rank_0_110_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_110),
.ph_rank_0_111_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_111),
.ph_rank_0_112_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_112),
.ph_rank_0_113_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_113),
.ph_rank_0_114_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_114),
.ph_rank_0_115_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_115),
.ph_rank_0_116_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_116),
.ph_rank_0_117_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_117),
.ph_rank_0_118_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_118),
.ph_rank_0_119_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_119),
.ph_rank_0_120_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_120),
.ph_rank_0_121_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_121),
.ph_rank_1_0_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_122),
.ph_rank_1_1_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_123),
.ph_rank_1_2_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_124),
.ph_rank_1_3_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_125),
.ph_rank_1_4_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_126),
.ph_rank_1_5_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_127),
.ph_rank_1_6_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_128),
.ph_rank_1_7_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_129),
.ph_rank_1_8_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_130),
.ph_rank_1_9_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_131),
.ph_rank_1_10_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_132),
.ph_rank_1_11_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_133),
.ph_rank_1_12_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_134),
.ph_rank_1_13_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_135),
.ph_rank_1_14_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_136),
.ph_rank_1_15_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_137),
.ph_rank_1_16_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_138),
.ph_rank_1_17_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_139),
.ph_rank_1_18_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_140),
.ph_rank_1_19_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_141),
.ph_rank_1_20_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_142),
.ph_rank_1_21_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_143),
.ph_rank_1_22_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_144),
.ph_rank_1_23_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_145),
.ph_rank_1_24_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_146),
.ph_rank_1_25_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_147),
.ph_rank_1_26_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_148),
.ph_rank_1_27_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_149),
.ph_rank_1_28_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_150),
.ph_rank_1_29_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_151),
.ph_rank_1_30_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_152),
.ph_rank_1_31_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_153),
.ph_rank_1_32_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_154),
.ph_rank_1_33_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_155),
.ph_rank_1_34_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_156),
.ph_rank_1_35_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_157),
.ph_rank_1_36_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_158),
.ph_rank_1_37_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_159),
.ph_rank_1_38_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_160),
.ph_rank_1_39_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_161),
.ph_rank_1_40_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_162),
.ph_rank_1_41_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_163),
.ph_rank_1_42_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_164),
.ph_rank_1_43_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_165),
.ph_rank_1_44_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_166),
.ph_rank_1_45_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_167),
.ph_rank_1_46_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_168),
.ph_rank_1_47_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_169),
.ph_rank_1_48_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_170),
.ph_rank_1_49_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_171),
.ph_rank_1_50_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_172),
.ph_rank_1_51_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_173),
.ph_rank_1_52_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_174),
.ph_rank_1_53_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_175),
.ph_rank_1_54_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_176),
.ph_rank_1_55_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_177),
.ph_rank_1_56_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_178),
.ph_rank_1_57_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_179),
.ph_rank_1_58_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_180),
.ph_rank_1_59_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_181),
.ph_rank_1_60_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_182),
.ph_rank_1_61_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_183),
.ph_rank_1_62_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_184),
.ph_rank_1_63_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_185),
.ph_rank_1_64_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_186),
.ph_rank_1_65_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_187),
.ph_rank_1_66_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_188),
.ph_rank_1_67_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_189),
.ph_rank_1_68_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_190),
.ph_rank_1_69_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_191),
.ph_rank_1_70_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_192),
.ph_rank_1_71_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_193),
.ph_rank_1_72_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_194),
.ph_rank_1_73_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_195),
.ph_rank_1_74_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_196),
.ph_rank_1_75_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_197),
.ph_rank_1_76_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_198),
.ph_rank_1_77_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_199),
.ph_rank_1_78_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_200),
.ph_rank_1_79_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_201),
.ph_rank_1_80_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_202),
.ph_rank_1_81_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_203),
.ph_rank_1_82_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_204),
.ph_rank_1_83_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_205),
.ph_rank_1_84_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_206),
.ph_rank_1_85_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_207),
.ph_rank_1_86_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_208),
.ph_rank_1_87_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_209),
.ph_rank_1_88_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_210),
.ph_rank_1_89_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_211),
.ph_rank_1_90_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_212),
.ph_rank_1_91_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_213),
.ph_rank_1_92_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_214),
.ph_rank_1_93_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_215),
.ph_rank_1_94_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_216),
.ph_rank_1_95_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_217),
.ph_rank_1_96_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_218),
.ph_rank_1_97_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_219),
.ph_rank_1_98_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_220),
.ph_rank_1_99_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_221),
.ph_rank_1_100_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_222),
.ph_rank_1_101_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_223),
.ph_rank_1_102_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_224),
.ph_rank_1_103_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_225),
.ph_rank_1_104_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_226),
.ph_rank_1_105_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_227),
.ph_rank_1_106_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_228),
.ph_rank_1_107_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_229),
.ph_rank_1_108_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_230),
.ph_rank_1_109_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_231),
.ph_rank_1_110_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_232),
.ph_rank_1_111_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_233),
.ph_rank_1_112_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_234),
.ph_rank_1_113_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_235),
.ph_rank_1_114_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_236),
.ph_rank_1_115_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_237),
.ph_rank_1_116_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_238),
.ph_rank_1_117_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_239),
.ph_rank_1_118_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_240),
.ph_rank_1_119_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_241),
.ph_rank_1_120_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_242),
.ph_rank_1_121_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_243),
.ph_rank_2_0_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_244),
.ph_rank_2_1_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_245),
.ph_rank_2_2_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_246),
.ph_rank_2_3_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_247),
.ph_rank_2_4_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_248),
.ph_rank_2_5_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_249),
.ph_rank_2_6_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_250),
.ph_rank_2_7_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_251),
.ph_rank_2_8_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_252),
.ph_rank_2_9_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_253),
.ph_rank_2_10_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_254),
.ph_rank_2_11_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_255),
.ph_rank_2_12_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_256),
.ph_rank_2_13_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_257),
.ph_rank_2_14_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_258),
.ph_rank_2_15_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_259),
.ph_rank_2_16_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_260),
.ph_rank_2_17_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_261),
.ph_rank_2_18_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_262),
.ph_rank_2_19_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_263),
.ph_rank_2_20_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_264),
.ph_rank_2_21_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_265),
.ph_rank_2_22_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_266),
.ph_rank_2_23_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_267),
.ph_rank_2_24_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_268),
.ph_rank_2_25_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_269),
.ph_rank_2_26_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_270),
.ph_rank_2_27_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_271),
.ph_rank_2_28_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_272),
.ph_rank_2_29_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_273),
.ph_rank_2_30_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_274),
.ph_rank_2_31_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_275),
.ph_rank_2_32_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_276),
.ph_rank_2_33_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_277),
.ph_rank_2_34_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_278),
.ph_rank_2_35_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_279),
.ph_rank_2_36_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_280),
.ph_rank_2_37_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_281),
.ph_rank_2_38_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_282),
.ph_rank_2_39_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_283),
.ph_rank_2_40_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_284),
.ph_rank_2_41_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_285),
.ph_rank_2_42_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_286),
.ph_rank_2_43_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_287),
.ph_rank_2_44_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_288),
.ph_rank_2_45_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_289),
.ph_rank_2_46_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_290),
.ph_rank_2_47_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_291),
.ph_rank_2_48_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_292),
.ph_rank_2_49_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_293),
.ph_rank_2_50_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_294),
.ph_rank_2_51_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_295),
.ph_rank_2_52_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_296),
.ph_rank_2_53_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_297),
.ph_rank_2_54_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_298),
.ph_rank_2_55_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_299),
.ph_rank_2_56_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_300),
.ph_rank_2_57_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_301),
.ph_rank_2_58_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_302),
.ph_rank_2_59_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_303),
.ph_rank_2_60_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_304),
.ph_rank_2_61_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_305),
.ph_rank_2_62_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_306),
.ph_rank_2_63_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_307),
.ph_rank_2_64_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_308),
.ph_rank_2_65_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_309),
.ph_rank_2_66_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_310),
.ph_rank_2_67_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_311),
.ph_rank_2_68_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_312),
.ph_rank_2_69_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_313),
.ph_rank_2_70_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_314),
.ph_rank_2_71_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_315),
.ph_rank_2_72_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_316),
.ph_rank_2_73_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_317),
.ph_rank_2_74_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_318),
.ph_rank_2_75_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_319),
.ph_rank_2_76_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_320),
.ph_rank_2_77_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_321),
.ph_rank_2_78_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_322),
.ph_rank_2_79_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_323),
.ph_rank_2_80_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_324),
.ph_rank_2_81_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_325),
.ph_rank_2_82_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_326),
.ph_rank_2_83_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_327),
.ph_rank_2_84_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_328),
.ph_rank_2_85_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_329),
.ph_rank_2_86_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_330),
.ph_rank_2_87_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_331),
.ph_rank_2_88_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_332),
.ph_rank_2_89_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_333),
.ph_rank_2_90_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_334),
.ph_rank_2_91_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_335),
.ph_rank_2_92_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_336),
.ph_rank_2_93_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_337),
.ph_rank_2_94_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_338),
.ph_rank_2_95_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_339),
.ph_rank_2_96_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_340),
.ph_rank_2_97_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_341),
.ph_rank_2_98_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_342),
.ph_rank_2_99_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_343),
.ph_rank_2_100_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_344),
.ph_rank_2_101_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_345),
.ph_rank_2_102_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_346),
.ph_rank_2_103_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_347),
.ph_rank_2_104_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_348),
.ph_rank_2_105_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_349),
.ph_rank_2_106_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_350),
.ph_rank_2_107_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_351),
.ph_rank_2_108_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_352),
.ph_rank_2_109_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_353),
.ph_rank_2_110_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_354),
.ph_rank_2_111_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_355),
.ph_rank_2_112_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_356),
.ph_rank_2_113_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_357),
.ph_rank_2_114_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_358),
.ph_rank_2_115_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_359),
.ph_rank_2_116_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_360),
.ph_rank_2_117_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_361),
.ph_rank_2_118_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_362),
.ph_rank_2_119_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_363),
.ph_rank_2_120_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_364),
.ph_rank_2_121_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_365),
.ph_rank_3_0_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_366),
.ph_rank_3_1_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_367),
.ph_rank_3_2_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_368),
.ph_rank_3_3_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_369),
.ph_rank_3_4_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_370),
.ph_rank_3_5_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_371),
.ph_rank_3_6_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_372),
.ph_rank_3_7_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_373),
.ph_rank_3_8_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_374),
.ph_rank_3_9_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_375),
.ph_rank_3_10_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_376),
.ph_rank_3_11_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_377),
.ph_rank_3_12_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_378),
.ph_rank_3_13_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_379),
.ph_rank_3_14_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_380),
.ph_rank_3_15_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_381),
.ph_rank_3_16_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_382),
.ph_rank_3_17_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_383),
.ph_rank_3_18_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_384),
.ph_rank_3_19_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_385),
.ph_rank_3_20_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_386),
.ph_rank_3_21_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_387),
.ph_rank_3_22_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_388),
.ph_rank_3_23_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_389),
.ph_rank_3_24_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_390),
.ph_rank_3_25_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_391),
.ph_rank_3_26_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_392),
.ph_rank_3_27_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_393),
.ph_rank_3_28_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_394),
.ph_rank_3_29_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_395),
.ph_rank_3_30_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_396),
.ph_rank_3_31_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_397),
.ph_rank_3_32_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_398),
.ph_rank_3_33_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_399),
.ph_rank_3_34_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_400),
.ph_rank_3_35_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_401),
.ph_rank_3_36_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_402),
.ph_rank_3_37_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_403),
.ph_rank_3_38_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_404),
.ph_rank_3_39_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_405),
.ph_rank_3_40_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_406),
.ph_rank_3_41_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_407),
.ph_rank_3_42_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_408),
.ph_rank_3_43_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_409),
.ph_rank_3_44_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_410),
.ph_rank_3_45_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_411),
.ph_rank_3_46_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_412),
.ph_rank_3_47_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_413),
.ph_rank_3_48_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_414),
.ph_rank_3_49_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_415),
.ph_rank_3_50_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_416),
.ph_rank_3_51_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_417),
.ph_rank_3_52_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_418),
.ph_rank_3_53_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_419),
.ph_rank_3_54_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_420),
.ph_rank_3_55_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_421),
.ph_rank_3_56_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_422),
.ph_rank_3_57_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_423),
.ph_rank_3_58_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_424),
.ph_rank_3_59_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_425),
.ph_rank_3_60_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_426),
.ph_rank_3_61_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_427),
.ph_rank_3_62_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_428),
.ph_rank_3_63_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_429),
.ph_rank_3_64_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_430),
.ph_rank_3_65_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_431),
.ph_rank_3_66_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_432),
.ph_rank_3_67_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_433),
.ph_rank_3_68_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_434),
.ph_rank_3_69_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_435),
.ph_rank_3_70_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_436),
.ph_rank_3_71_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_437),
.ph_rank_3_72_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_438),
.ph_rank_3_73_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_439),
.ph_rank_3_74_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_440),
.ph_rank_3_75_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_441),
.ph_rank_3_76_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_442),
.ph_rank_3_77_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_443),
.ph_rank_3_78_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_444),
.ph_rank_3_79_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_445),
.ph_rank_3_80_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_446),
.ph_rank_3_81_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_447),
.ph_rank_3_82_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_448),
.ph_rank_3_83_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_449),
.ph_rank_3_84_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_450),
.ph_rank_3_85_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_451),
.ph_rank_3_86_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_452),
.ph_rank_3_87_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_453),
.ph_rank_3_88_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_454),
.ph_rank_3_89_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_455),
.ph_rank_3_90_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_456),
.ph_rank_3_91_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_457),
.ph_rank_3_92_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_458),
.ph_rank_3_93_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_459),
.ph_rank_3_94_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_460),
.ph_rank_3_95_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_461),
.ph_rank_3_96_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_462),
.ph_rank_3_97_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_463),
.ph_rank_3_98_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_464),
.ph_rank_3_99_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_465),
.ph_rank_3_100_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_466),
.ph_rank_3_101_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_467),
.ph_rank_3_102_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_468),
.ph_rank_3_103_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_469),
.ph_rank_3_104_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_470),
.ph_rank_3_105_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_471),
.ph_rank_3_106_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_472),
.ph_rank_3_107_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_473),
.ph_rank_3_108_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_474),
.ph_rank_3_109_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_475),
.ph_rank_3_110_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_476),
.ph_rank_3_111_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_477),
.ph_rank_3_112_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_478),
.ph_rank_3_113_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_479),
.ph_rank_3_114_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_480),
.ph_rank_3_115_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_481),
.ph_rank_3_116_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_482),
.ph_rank_3_117_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_483),
.ph_rank_3_118_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_484),
.ph_rank_3_119_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_485),
.ph_rank_3_120_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_486),
.ph_rank_3_121_V_read(grp_sp_ph_pattern_sector_fu_28574_ap_return_487),
.ap_return_0(grp_sp_sort_sector_fu_52195_ap_return_0),
.ap_return_1(grp_sp_sort_sector_fu_52195_ap_return_1),
.ap_return_2(grp_sp_sort_sector_fu_52195_ap_return_2),
.ap_return_3(grp_sp_sort_sector_fu_52195_ap_return_3),
.ap_return_4(grp_sp_sort_sector_fu_52195_ap_return_4),
.ap_return_5(grp_sp_sort_sector_fu_52195_ap_return_5),
.ap_return_6(grp_sp_sort_sector_fu_52195_ap_return_6),
.ap_return_7(grp_sp_sort_sector_fu_52195_ap_return_7),
.ap_return_8(grp_sp_sort_sector_fu_52195_ap_return_8),
.ap_return_9(grp_sp_sort_sector_fu_52195_ap_return_9),
.ap_return_10(grp_sp_sort_sector_fu_52195_ap_return_10),
.ap_return_11(grp_sp_sort_sector_fu_52195_ap_return_11),
.ap_return_12(grp_sp_sort_sector_fu_52195_ap_return_12),
.ap_return_13(grp_sp_sort_sector_fu_52195_ap_return_13),
.ap_return_14(grp_sp_sort_sector_fu_52195_ap_return_14),
.ap_return_15(grp_sp_sort_sector_fu_52195_ap_return_15),
.ap_return_16(grp_sp_sort_sector_fu_52195_ap_return_16),
.ap_return_17(grp_sp_sort_sector_fu_52195_ap_return_17),
.ap_return_18(grp_sp_sort_sector_fu_52195_ap_return_18),
.ap_return_19(grp_sp_sort_sector_fu_52195_ap_return_19),
.ap_return_20(grp_sp_sort_sector_fu_52195_ap_return_20),
.ap_return_21(grp_sp_sort_sector_fu_52195_ap_return_21),
.ap_return_22(grp_sp_sort_sector_fu_52195_ap_return_22),
.ap_return_23(grp_sp_sort_sector_fu_52195_ap_return_23)
);
sp_zones call_ret6_sp_zones_fu_52687(
.phzvl_in_0_0_V_read(phzvl_t_0_0_V_reg_61848),
.phzvl_in_0_1_V_read(phzvl_t_0_1_V_reg_61853),
.phzvl_in_0_2_V_read(phzvl_t_0_2_V_reg_61858),
.phzvl_in_0_3_V_read(phzvl_t_0_3_V_reg_61488),
.phzvl_in_0_4_V_read(phzvl_t_0_4_V_reg_61493),
.phzvl_in_0_5_V_read(phzvl_t_0_5_V_reg_61498),
.phzvl_in_1_0_V_read(phzvl_t_1_0_V_reg_61863),
.phzvl_in_1_1_V_read(phzvl_t_1_1_V_reg_61868),
.phzvl_in_1_2_V_read(phzvl_t_1_2_V_reg_61873),
.phzvl_in_1_3_V_read(phzvl_t_1_3_V_reg_61503),
.phzvl_in_1_4_V_read(phzvl_t_1_4_V_reg_61508),
.phzvl_in_1_5_V_read(phzvl_t_1_5_V_reg_61513),
.phzvl_in_2_0_V_read(phzvl_t_2_0_V_reg_61518),
.phzvl_in_2_1_V_read(phzvl_t_2_1_V_reg_61523),
.phzvl_in_2_2_V_read(phzvl_t_2_2_V_reg_61528),
.phzvl_in_2_3_V_read(phzvl_t_2_3_V_reg_61533),
.phzvl_in_2_4_V_read(phzvl_t_2_4_V_reg_61538),
.phzvl_in_2_5_V_read(phzvl_t_2_5_V_reg_61543),
.phzvl_in_2_6_V_read(phzvl_t_2_6_V_reg_61548),
.phzvl_in_2_7_V_read(phzvl_t_2_7_V_reg_61553),
.phzvl_in_2_8_V_read(phzvl_t_2_8_V_reg_61558),
.phzvl_in_3_0_V_read(phzvl_t_3_0_V_reg_61563),
.phzvl_in_3_1_V_read(phzvl_t_3_1_V_reg_61568),
.phzvl_in_3_2_V_read(phzvl_t_3_2_V_reg_61573),
.phzvl_in_3_3_V_read(phzvl_t_3_3_V_reg_61578),
.phzvl_in_3_4_V_read(phzvl_t_3_4_V_reg_61583),
.phzvl_in_3_5_V_read(phzvl_t_3_5_V_reg_61588),
.phzvl_in_3_6_V_read(phzvl_t_3_6_V_reg_61593),
.phzvl_in_3_7_V_read(phzvl_t_3_7_V_reg_61598),
.phzvl_in_3_8_V_read(phzvl_t_3_8_V_reg_61603),
.phzvl_in_4_0_V_read(phzvl_t_4_0_V_reg_61608),
.phzvl_in_4_1_V_read(phzvl_t_4_1_V_reg_61613),
.phzvl_in_4_2_V_read(phzvl_t_4_2_V_reg_61618),
.phzvl_in_4_3_V_read(phzvl_t_4_3_V_reg_61623),
.phzvl_in_4_4_V_read(phzvl_t_4_4_V_reg_61628),
.phzvl_in_4_5_V_read(phzvl_t_4_5_V_reg_61633),
.phzvl_in_4_6_V_read(phzvl_t_4_6_V_reg_61638),
.phzvl_in_4_7_V_read(phzvl_t_4_7_V_reg_61643),
.phzvl_in_4_8_V_read(phzvl_t_4_8_V_reg_61648),
.ph_hit_in_0_0_V_read(ph_hit_t_0_0_V_reg_61878),
.ph_hit_in_0_1_V_read(ph_hit_t_0_1_V_reg_61883),
.ph_hit_in_0_2_V_read(ph_hit_t_0_2_V_reg_61888),
.ph_hit_in_0_3_V_read(ph_hit_t_0_3_V_reg_61653),
.ph_hit_in_0_4_V_read(ph_hit_t_0_4_V_reg_61658),
.ph_hit_in_0_5_V_read(ph_hit_t_0_5_V_reg_61663),
.ph_hit_in_0_6_V_read(ph_hit_t_0_6_V_reg_61668),
.ph_hit_in_0_7_V_read(ph_hit_t_0_7_V_reg_61673),
.ph_hit_in_0_8_V_read(ph_hit_t_0_8_V_reg_61678),
.ph_hit_in_1_0_V_read(ph_hit_t_1_0_V_reg_61893),
.ph_hit_in_1_1_V_read(ph_hit_t_1_1_V_reg_61898),
.ph_hit_in_1_2_V_read(ph_hit_t_1_2_V_reg_61903),
.ph_hit_in_1_3_V_read(ph_hit_t_1_3_V_reg_61683),
.ph_hit_in_1_4_V_read(ph_hit_t_1_4_V_reg_61688),
.ph_hit_in_1_5_V_read(ph_hit_t_1_5_V_reg_61693),
.ph_hit_in_1_6_V_read(ph_hit_t_1_6_V_reg_61698),
.ph_hit_in_1_7_V_read(ph_hit_t_1_7_V_reg_61703),
.ph_hit_in_1_8_V_read(ph_hit_t_1_8_V_reg_61708),
.ph_hit_in_2_0_V_read(ph_hit_t_2_0_V_reg_61713),
.ph_hit_in_2_1_V_read(ph_hit_t_2_1_V_reg_61718),
.ph_hit_in_2_2_V_read(ph_hit_t_2_2_V_reg_61723),
.ph_hit_in_2_3_V_read(ph_hit_t_2_3_V_reg_61728),
.ph_hit_in_2_4_V_read(ph_hit_t_2_4_V_reg_61733),
.ph_hit_in_2_5_V_read(ph_hit_t_2_5_V_reg_61738),
.ph_hit_in_2_6_V_read(ph_hit_t_2_6_V_reg_61743),
.ph_hit_in_2_7_V_read(ph_hit_t_2_7_V_reg_61748),
.ph_hit_in_2_8_V_read(ph_hit_t_2_8_V_reg_61753),
.ph_hit_in_3_0_V_read(ph_hit_t_3_0_V_reg_61758),
.ph_hit_in_3_1_V_read(ph_hit_t_3_1_V_reg_61763),
.ph_hit_in_3_2_V_read(ph_hit_t_3_2_V_reg_61768),
.ph_hit_in_3_3_V_read(ph_hit_t_3_3_V_reg_61773),
.ph_hit_in_3_4_V_read(ph_hit_t_3_4_V_reg_61778),
.ph_hit_in_3_5_V_read(ph_hit_t_3_5_V_reg_61783),
.ph_hit_in_3_6_V_read(ph_hit_t_3_6_V_reg_61788),
.ph_hit_in_3_7_V_read(ph_hit_t_3_7_V_reg_61793),
.ph_hit_in_3_8_V_read(ph_hit_t_3_8_V_reg_61798),
.ph_hit_in_4_0_V_read(ph_hit_t_4_0_V_reg_61803),
.ph_hit_in_4_1_V_read(ph_hit_t_4_1_V_reg_61808),
.ph_hit_in_4_2_V_read(ph_hit_t_4_2_V_reg_61813),
.ph_hit_in_4_3_V_read(ph_hit_t_4_3_V_reg_61818),
.ph_hit_in_4_4_V_read(ph_hit_t_4_4_V_reg_61823),
.ph_hit_in_4_5_V_read(ph_hit_t_4_5_V_reg_61828),
.ph_hit_in_4_6_V_read(ph_hit_t_4_6_V_reg_61833),
.ph_hit_in_4_7_V_read(ph_hit_t_4_7_V_reg_61838),
.ph_hit_in_4_8_V_read(ph_hit_t_4_8_V_reg_61843),
.ap_return_0(call_ret6_sp_zones_fu_52687_ap_return_0),
.ap_return_1(call_ret6_sp_zones_fu_52687_ap_return_1),
.ap_return_2(call_ret6_sp_zones_fu_52687_ap_return_2),
.ap_return_3(call_ret6_sp_zones_fu_52687_ap_return_3),
.ap_return_4(call_ret6_sp_zones_fu_52687_ap_return_4),
.ap_return_5(call_ret6_sp_zones_fu_52687_ap_return_5),
.ap_return_6(call_ret6_sp_zones_fu_52687_ap_return_6),
.ap_return_7(call_ret6_sp_zones_fu_52687_ap_return_7),
.ap_return_8(call_ret6_sp_zones_fu_52687_ap_return_8),
.ap_return_9(call_ret6_sp_zones_fu_52687_ap_return_9),
.ap_return_10(call_ret6_sp_zones_fu_52687_ap_return_10),
.ap_return_11(call_ret6_sp_zones_fu_52687_ap_return_11),
.ap_return_12(call_ret6_sp_zones_fu_52687_ap_return_12),
.ap_return_13(call_ret6_sp_zones_fu_52687_ap_return_13),
.ap_return_14(call_ret6_sp_zones_fu_52687_ap_return_14)
);
sp_co_ord_delay grp_sp_co_ord_delay_fu_52775(
.ap_clk(ap_clk),
.ap_rst(ap_rst),
.ap_start(grp_sp_co_ord_delay_fu_52775_ap_start),
.ap_done(grp_sp_co_ord_delay_fu_52775_ap_done),
.ap_idle(grp_sp_co_ord_delay_fu_52775_ap_idle),
.ap_ready(grp_sp_co_ord_delay_fu_52775_ap_ready),
.phi_0_0_0_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_84),
.phi_0_0_1_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_85),
.phi_0_1_0_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_86),
.phi_0_1_1_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_87),
.phi_0_2_0_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_88),
.phi_0_2_1_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_89),
.phi_0_3_0_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_90),
.phi_0_3_1_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_91),
.phi_0_4_0_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_92),
.phi_0_4_1_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_93),
.phi_0_5_0_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_94),
.phi_0_5_1_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_95),
.phi_0_6_0_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_96),
.phi_0_6_1_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_97),
.phi_0_7_0_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_98),
.phi_0_7_1_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_99),
.phi_0_8_0_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_100),
.phi_0_8_1_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_101),
.phi_1_0_0_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_102),
.phi_1_0_1_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_103),
.phi_1_1_0_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_104),
.phi_1_1_1_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_105),
.phi_1_2_0_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_106),
.phi_1_2_1_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_107),
.phi_1_3_0_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_108),
.phi_1_3_1_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_109),
.phi_1_4_0_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_110),
.phi_1_4_1_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_111),
.phi_1_5_0_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_112),
.phi_1_5_1_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_113),
.phi_1_6_0_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_114),
.phi_1_6_1_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_115),
.phi_1_7_0_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_116),
.phi_1_7_1_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_117),
.phi_1_8_0_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_118),
.phi_1_8_1_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_119),
.phi_2_0_0_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_120),
.phi_2_0_1_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_121),
.phi_2_1_0_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_122),
.phi_2_1_1_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_123),
.phi_2_2_0_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_124),
.phi_2_2_1_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_125),
.phi_2_3_0_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_126),
.phi_2_3_1_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_127),
.phi_2_4_0_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_128),
.phi_2_4_1_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_129),
.phi_2_5_0_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_130),
.phi_2_5_1_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_131),
.phi_2_6_0_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_132),
.phi_2_6_1_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_133),
.phi_2_7_0_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_134),
.phi_2_7_1_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_135),
.phi_2_8_0_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_136),
.phi_2_8_1_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_137),
.phi_3_0_0_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_138),
.phi_3_0_1_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_139),
.phi_3_1_0_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_140),
.phi_3_1_1_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_141),
.phi_3_2_0_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_142),
.phi_3_2_1_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_143),
.phi_3_3_0_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_144),
.phi_3_3_1_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_145),
.phi_3_4_0_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_146),
.phi_3_4_1_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_147),
.phi_3_5_0_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_148),
.phi_3_5_1_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_149),
.phi_3_6_0_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_150),
.phi_3_6_1_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_151),
.phi_3_7_0_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_152),
.phi_3_7_1_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_153),
.phi_3_8_0_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_154),
.phi_3_8_1_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_155),
.phi_4_0_0_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_156),
.phi_4_0_1_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_157),
.phi_4_1_0_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_158),
.phi_4_1_1_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_159),
.phi_4_2_0_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_160),
.phi_4_2_1_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_161),
.phi_4_3_0_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_162),
.phi_4_3_1_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_163),
.phi_4_4_0_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_164),
.phi_4_4_1_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_165),
.phi_4_5_0_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_166),
.phi_4_5_1_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_167),
.phi_4_6_0_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_168),
.phi_4_6_1_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_169),
.phi_4_7_0_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_170),
.phi_4_7_1_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_171),
.phi_4_8_0_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_172),
.phi_4_8_1_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_173),
.cpati_0_0_0_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_174),
.cpati_0_0_1_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_175),
.cpati_0_1_0_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_176),
.cpati_0_1_1_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_177),
.cpati_0_2_0_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_178),
.cpati_0_2_1_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_179),
.cpati_0_3_0_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_180),
.cpati_0_3_1_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_181),
.cpati_0_4_0_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_182),
.cpati_0_4_1_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_183),
.cpati_0_5_0_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_184),
.cpati_0_5_1_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_185),
.cpati_0_6_0_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_186),
.cpati_0_6_1_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_187),
.cpati_0_7_0_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_188),
.cpati_0_7_1_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_189),
.cpati_0_8_0_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_190),
.cpati_0_8_1_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_191),
.cpati_1_0_0_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_192),
.cpati_1_0_1_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_193),
.cpati_1_1_0_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_194),
.cpati_1_1_1_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_195),
.cpati_1_2_0_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_196),
.cpati_1_2_1_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_197),
.cpati_1_3_0_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_198),
.cpati_1_3_1_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_199),
.cpati_1_4_0_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_200),
.cpati_1_4_1_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_201),
.cpati_1_5_0_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_202),
.cpati_1_5_1_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_203),
.cpati_1_6_0_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_204),
.cpati_1_6_1_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_205),
.cpati_1_7_0_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_206),
.cpati_1_7_1_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_207),
.cpati_1_8_0_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_208),
.cpati_1_8_1_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_209),
.cpati_2_0_0_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_210),
.cpati_2_0_1_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_211),
.cpati_2_1_0_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_212),
.cpati_2_1_1_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_213),
.cpati_2_2_0_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_214),
.cpati_2_2_1_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_215),
.cpati_2_3_0_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_216),
.cpati_2_3_1_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_217),
.cpati_2_4_0_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_218),
.cpati_2_4_1_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_219),
.cpati_2_5_0_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_220),
.cpati_2_5_1_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_221),
.cpati_2_6_0_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_222),
.cpati_2_6_1_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_223),
.cpati_2_7_0_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_224),
.cpati_2_7_1_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_225),
.cpati_2_8_0_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_226),
.cpati_2_8_1_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_227),
.cpati_3_0_0_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_228),
.cpati_3_0_1_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_229),
.cpati_3_1_0_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_230),
.cpati_3_1_1_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_231),
.cpati_3_2_0_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_232),
.cpati_3_2_1_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_233),
.cpati_3_3_0_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_234),
.cpati_3_3_1_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_235),
.cpati_3_4_0_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_236),
.cpati_3_4_1_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_237),
.cpati_3_5_0_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_238),
.cpati_3_5_1_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_239),
.cpati_3_6_0_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_240),
.cpati_3_6_1_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_241),
.cpati_3_7_0_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_242),
.cpati_3_7_1_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_243),
.cpati_3_8_0_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_244),
.cpati_3_8_1_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_245),
.cpati_4_0_0_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_246),
.cpati_4_0_1_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_247),
.cpati_4_1_0_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_248),
.cpati_4_1_1_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_249),
.cpati_4_2_0_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_250),
.cpati_4_2_1_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_251),
.cpati_4_3_0_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_252),
.cpati_4_3_1_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_253),
.cpati_4_4_0_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_254),
.cpati_4_4_1_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_255),
.cpati_4_5_0_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_256),
.cpati_4_5_1_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_257),
.cpati_4_6_0_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_258),
.cpati_4_6_1_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_259),
.cpati_4_7_0_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_260),
.cpati_4_7_1_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_261),
.cpati_4_8_0_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_262),
.cpati_4_8_1_V_read(call_ret4_sp_prim_conv_sector_fu_37378_ap_return_263),
.ap_return_0(grp_sp_co_ord_delay_fu_52775_ap_return_0),
.ap_return_1(grp_sp_co_ord_delay_fu_52775_ap_return_1),
.ap_return_2(grp_sp_co_ord_delay_fu_52775_ap_return_2),
.ap_return_3(grp_sp_co_ord_delay_fu_52775_ap_return_3),
.ap_return_4(grp_sp_co_ord_delay_fu_52775_ap_return_4),
.ap_return_5(grp_sp_co_ord_delay_fu_52775_ap_return_5),
.ap_return_6(grp_sp_co_ord_delay_fu_52775_ap_return_6),
.ap_return_7(grp_sp_co_ord_delay_fu_52775_ap_return_7),
.ap_return_8(grp_sp_co_ord_delay_fu_52775_ap_return_8),
.ap_return_9(grp_sp_co_ord_delay_fu_52775_ap_return_9),
.ap_return_10(grp_sp_co_ord_delay_fu_52775_ap_return_10),
.ap_return_11(grp_sp_co_ord_delay_fu_52775_ap_return_11),
.ap_return_12(grp_sp_co_ord_delay_fu_52775_ap_return_12),
.ap_return_13(grp_sp_co_ord_delay_fu_52775_ap_return_13),
.ap_return_14(grp_sp_co_ord_delay_fu_52775_ap_return_14),
.ap_return_15(grp_sp_co_ord_delay_fu_52775_ap_return_15),
.ap_return_16(grp_sp_co_ord_delay_fu_52775_ap_return_16),
.ap_return_17(grp_sp_co_ord_delay_fu_52775_ap_return_17),
.ap_return_18(grp_sp_co_ord_delay_fu_52775_ap_return_18),
.ap_return_19(grp_sp_co_ord_delay_fu_52775_ap_return_19),
.ap_return_20(grp_sp_co_ord_delay_fu_52775_ap_return_20),
.ap_return_21(grp_sp_co_ord_delay_fu_52775_ap_return_21),
.ap_return_22(grp_sp_co_ord_delay_fu_52775_ap_return_22),
.ap_return_23(grp_sp_co_ord_delay_fu_52775_ap_return_23),
.ap_return_24(grp_sp_co_ord_delay_fu_52775_ap_return_24),
.ap_return_25(grp_sp_co_ord_delay_fu_52775_ap_return_25),
.ap_return_26(grp_sp_co_ord_delay_fu_52775_ap_return_26),
.ap_return_27(grp_sp_co_ord_delay_fu_52775_ap_return_27),
.ap_return_28(grp_sp_co_ord_delay_fu_52775_ap_return_28),
.ap_return_29(grp_sp_co_ord_delay_fu_52775_ap_return_29),
.ap_return_30(grp_sp_co_ord_delay_fu_52775_ap_return_30),
.ap_return_31(grp_sp_co_ord_delay_fu_52775_ap_return_31),
.ap_return_32(grp_sp_co_ord_delay_fu_52775_ap_return_32),
.ap_return_33(grp_sp_co_ord_delay_fu_52775_ap_return_33),
.ap_return_34(grp_sp_co_ord_delay_fu_52775_ap_return_34),
.ap_return_35(grp_sp_co_ord_delay_fu_52775_ap_return_35),
.ap_return_36(grp_sp_co_ord_delay_fu_52775_ap_return_36),
.ap_return_37(grp_sp_co_ord_delay_fu_52775_ap_return_37)
);
sp_extend_sector call_ret7_sp_extend_sector_fu_54039(
.ap_clk(ap_clk),
.ap_rst(ap_rst),
.ap_start(call_ret7_sp_extend_sector_fu_54039_ap_start),
.ap_done(call_ret7_sp_extend_sector_fu_54039_ap_done),
.ap_idle(call_ret7_sp_extend_sector_fu_54039_ap_idle),
.ap_ready(call_ret7_sp_extend_sector_fu_54039_ap_ready),
.inp_0_1_V_read(ph_zone_t_0_1_V_1_reg_61908),
.inp_0_2_V_read(ph_zone_t_0_2_V_1_reg_61913),
.inp_0_3_V_read(ph_zone_t_0_3_V_1_reg_61918),
.inp_0_4_V_read(ph_zone_t_0_4_V_1_reg_61923),
.inp_1_1_V_read(ph_zone_t_1_1_V_1_reg_61928),
.inp_1_2_V_read(ph_zone_t_1_2_V_1_reg_61933),
.inp_1_3_V_read(ph_zone_t_1_3_V_1_reg_61938),
.inp_1_4_V_read(ph_zone_t_1_4_V_1_reg_61943),
.inp_2_1_V_read(ph_zone_t_2_1_V_1_reg_61948),
.inp_2_2_V_read(ph_zone_t_2_2_V_1_reg_61953),
.inp_2_3_V_read(ph_zone_t_2_3_V_1_reg_61958),
.inp_2_4_V_read(ph_zone_t_2_4_V_1_reg_61963),
.inp_3_1_V_read(ph_zone_t_3_1_V_1_reg_61968),
.inp_3_2_V_read(ph_zone_t_3_2_V_1_reg_61973),
.inp_3_3_V_read(ph_zone_t_3_3_V_1_reg_61978),
.ap_return_0(call_ret7_sp_extend_sector_fu_54039_ap_return_0),
.ap_return_1(call_ret7_sp_extend_sector_fu_54039_ap_return_1),
.ap_return_2(call_ret7_sp_extend_sector_fu_54039_ap_return_2),
.ap_return_3(call_ret7_sp_extend_sector_fu_54039_ap_return_3),
.ap_return_4(call_ret7_sp_extend_sector_fu_54039_ap_return_4),
.ap_return_5(call_ret7_sp_extend_sector_fu_54039_ap_return_5),
.ap_return_6(call_ret7_sp_extend_sector_fu_54039_ap_return_6),
.ap_return_7(call_ret7_sp_extend_sector_fu_54039_ap_return_7),
.ap_return_8(call_ret7_sp_extend_sector_fu_54039_ap_return_8),
.ap_return_9(call_ret7_sp_extend_sector_fu_54039_ap_return_9),
.ap_return_10(call_ret7_sp_extend_sector_fu_54039_ap_return_10),
.ap_return_11(call_ret7_sp_extend_sector_fu_54039_ap_return_11),
.ap_return_12(call_ret7_sp_extend_sector_fu_54039_ap_return_12),
.ap_return_13(call_ret7_sp_extend_sector_fu_54039_ap_return_13),
.ap_return_14(call_ret7_sp_extend_sector_fu_54039_ap_return_14),
.ap_return_15(call_ret7_sp_extend_sector_fu_54039_ap_return_15),
.ap_return_16(call_ret7_sp_extend_sector_fu_54039_ap_return_16),
.ap_return_17(call_ret7_sp_extend_sector_fu_54039_ap_return_17),
.ap_return_18(call_ret7_sp_extend_sector_fu_54039_ap_return_18),
.ap_return_19(call_ret7_sp_extend_sector_fu_54039_ap_return_19)
);
sp_ptlut_address grp_sp_ptlut_address_fu_54138(
.ap_clk(ap_clk),
.ap_rst(ap_rst),
.bt_phi_i_0_V_read(grp_sp_best_tracks_fu_51719_ap_return_0),
.bt_phi_i_1_V_read(grp_sp_best_tracks_fu_51719_ap_return_1),
.bt_phi_i_2_V_read(grp_sp_best_tracks_fu_51719_ap_return_2),
.bt_theta_i_0_V_read(grp_sp_best_tracks_fu_51719_ap_return_3),
.bt_theta_i_1_V_read(grp_sp_best_tracks_fu_51719_ap_return_4),
.bt_theta_i_2_V_read(grp_sp_best_tracks_fu_51719_ap_return_5),
.bt_cpattern_0_0_V_read(grp_sp_best_tracks_fu_51719_ap_return_6),
.bt_cpattern_0_1_V_read(grp_sp_best_tracks_fu_51719_ap_return_7),
.bt_cpattern_0_2_V_read(grp_sp_best_tracks_fu_51719_ap_return_8),
.bt_cpattern_0_3_V_read(grp_sp_best_tracks_fu_51719_ap_return_9),
.bt_cpattern_1_0_V_read(grp_sp_best_tracks_fu_51719_ap_return_10),
.bt_cpattern_1_1_V_read(grp_sp_best_tracks_fu_51719_ap_return_11),
.bt_cpattern_1_2_V_read(grp_sp_best_tracks_fu_51719_ap_return_12),
.bt_cpattern_1_3_V_read(grp_sp_best_tracks_fu_51719_ap_return_13),
.bt_cpattern_2_0_V_read(grp_sp_best_tracks_fu_51719_ap_return_14),
.bt_cpattern_2_1_V_read(grp_sp_best_tracks_fu_51719_ap_return_15),
.bt_cpattern_2_2_V_read(grp_sp_best_tracks_fu_51719_ap_return_16),
.bt_cpattern_2_3_V_read(grp_sp_best_tracks_fu_51719_ap_return_17),
.bt_delta_ph_0_0_V_read(grp_sp_best_tracks_fu_51719_ap_return_18),
.bt_delta_ph_0_1_V_read(grp_sp_best_tracks_fu_51719_ap_return_19),
.bt_delta_ph_0_2_V_read(grp_sp_best_tracks_fu_51719_ap_return_20),
.bt_delta_ph_0_3_V_read(grp_sp_best_tracks_fu_51719_ap_return_21),
.bt_delta_ph_0_4_V_read(grp_sp_best_tracks_fu_51719_ap_return_22),
.bt_delta_ph_0_5_V_read(grp_sp_best_tracks_fu_51719_ap_return_23),
.bt_delta_ph_1_0_V_read(grp_sp_best_tracks_fu_51719_ap_return_24),
.bt_delta_ph_1_1_V_read(grp_sp_best_tracks_fu_51719_ap_return_25),
.bt_delta_ph_1_2_V_read(grp_sp_best_tracks_fu_51719_ap_return_26),
.bt_delta_ph_1_3_V_read(grp_sp_best_tracks_fu_51719_ap_return_27),
.bt_delta_ph_1_4_V_read(grp_sp_best_tracks_fu_51719_ap_return_28),
.bt_delta_ph_1_5_V_read(grp_sp_best_tracks_fu_51719_ap_return_29),
.bt_delta_ph_2_0_V_read(grp_sp_best_tracks_fu_51719_ap_return_30),
.bt_delta_ph_2_1_V_read(grp_sp_best_tracks_fu_51719_ap_return_31),
.bt_delta_ph_2_2_V_read(grp_sp_best_tracks_fu_51719_ap_return_32),
.bt_delta_ph_2_3_V_read(grp_sp_best_tracks_fu_51719_ap_return_33),
.bt_delta_ph_2_4_V_read(grp_sp_best_tracks_fu_51719_ap_return_34),
.bt_delta_ph_2_5_V_read(grp_sp_best_tracks_fu_51719_ap_return_35),
.bt_delta_th_0_0_V_read(grp_sp_best_tracks_fu_51719_ap_return_36),
.bt_delta_th_0_1_V_read(grp_sp_best_tracks_fu_51719_ap_return_37),
.bt_delta_th_0_2_V_read(grp_sp_best_tracks_fu_51719_ap_return_38),
.bt_delta_th_0_3_V_read(grp_sp_best_tracks_fu_51719_ap_return_39),
.bt_delta_th_0_4_V_read(grp_sp_best_tracks_fu_51719_ap_return_40),
.bt_delta_th_0_5_V_read(grp_sp_best_tracks_fu_51719_ap_return_41),
.bt_delta_th_1_0_V_read(grp_sp_best_tracks_fu_51719_ap_return_42),
.bt_delta_th_1_1_V_read(grp_sp_best_tracks_fu_51719_ap_return_43),
.bt_delta_th_1_2_V_read(grp_sp_best_tracks_fu_51719_ap_return_44),
.bt_delta_th_1_3_V_read(grp_sp_best_tracks_fu_51719_ap_return_45),
.bt_delta_th_1_4_V_read(grp_sp_best_tracks_fu_51719_ap_return_46),
.bt_delta_th_1_5_V_read(grp_sp_best_tracks_fu_51719_ap_return_47),
.bt_delta_th_2_0_V_read(grp_sp_best_tracks_fu_51719_ap_return_48),
.bt_delta_th_2_1_V_read(grp_sp_best_tracks_fu_51719_ap_return_49),
.bt_delta_th_2_2_V_read(grp_sp_best_tracks_fu_51719_ap_return_50),
.bt_delta_th_2_3_V_read(grp_sp_best_tracks_fu_51719_ap_return_51),
.bt_delta_th_2_4_V_read(grp_sp_best_tracks_fu_51719_ap_return_52),
.bt_delta_th_2_5_V_read(grp_sp_best_tracks_fu_51719_ap_return_53),
.bt_sign_ph_0_V_read(grp_sp_best_tracks_fu_51719_ap_return_54),
.bt_sign_ph_1_V_read(grp_sp_best_tracks_fu_51719_ap_return_55),
.bt_sign_ph_2_V_read(grp_sp_best_tracks_fu_51719_ap_return_56),
.bt_sign_th_0_V_read(grp_sp_best_tracks_fu_51719_ap_return_57),
.bt_sign_th_1_V_read(grp_sp_best_tracks_fu_51719_ap_return_58),
.bt_sign_th_2_V_read(grp_sp_best_tracks_fu_51719_ap_return_59),
.bt_rank_i_0_V_read(grp_sp_best_tracks_fu_51719_ap_return_60),
.bt_rank_i_1_V_read(grp_sp_best_tracks_fu_51719_ap_return_61),
.bt_rank_i_2_V_read(grp_sp_best_tracks_fu_51719_ap_return_62),
.bt_vi_0_0_V_read(grp_sp_best_tracks_fu_51719_ap_return_63),
.bt_vi_1_0_V_read(grp_sp_best_tracks_fu_51719_ap_return_68),
.bt_vi_2_0_V_read(grp_sp_best_tracks_fu_51719_ap_return_73),
.bt_ci_0_0_V_read(grp_sp_best_tracks_fu_51719_ap_return_93),
.bt_ci_0_1_V_read(grp_sp_best_tracks_fu_51719_ap_return_94),
.bt_ci_0_2_V_read(grp_sp_best_tracks_fu_51719_ap_return_95),
.bt_ci_0_3_V_read(grp_sp_best_tracks_fu_51719_ap_return_96),
.bt_ci_0_4_V_read(grp_sp_best_tracks_fu_51719_ap_return_97),
.bt_ci_1_0_V_read(grp_sp_best_tracks_fu_51719_ap_return_98),
.bt_ci_1_1_V_read(grp_sp_best_tracks_fu_51719_ap_return_99),
.bt_ci_1_2_V_read(grp_sp_best_tracks_fu_51719_ap_return_100),
.bt_ci_1_3_V_read(grp_sp_best_tracks_fu_51719_ap_return_101),
.bt_ci_1_4_V_read(grp_sp_best_tracks_fu_51719_ap_return_102),
.bt_ci_2_0_V_read(grp_sp_best_tracks_fu_51719_ap_return_103),
.bt_ci_2_1_V_read(grp_sp_best_tracks_fu_51719_ap_return_104),
.bt_ci_2_2_V_read(grp_sp_best_tracks_fu_51719_ap_return_105),
.bt_ci_2_3_V_read(grp_sp_best_tracks_fu_51719_ap_return_106),
.bt_ci_2_4_V_read(grp_sp_best_tracks_fu_51719_ap_return_107),
.sector_V(sector_V),
.endcap_V(endcap_V),
.ap_return_0(grp_sp_ptlut_address_fu_54138_ap_return_0),
.ap_return_1(grp_sp_ptlut_address_fu_54138_ap_return_1),
.ap_return_2(grp_sp_ptlut_address_fu_54138_ap_return_2),
.ap_return_3(grp_sp_ptlut_address_fu_54138_ap_return_3),
.ap_return_4(grp_sp_ptlut_address_fu_54138_ap_return_4),
.ap_return_5(grp_sp_ptlut_address_fu_54138_ap_return_5),
.ap_return_6(grp_sp_ptlut_address_fu_54138_ap_return_6),
.ap_return_7(grp_sp_ptlut_address_fu_54138_ap_return_7),
.ap_return_8(grp_sp_ptlut_address_fu_54138_ap_return_8),
.ap_return_9(grp_sp_ptlut_address_fu_54138_ap_return_9),
.ap_return_10(grp_sp_ptlut_address_fu_54138_ap_return_10),
.ap_return_11(grp_sp_ptlut_address_fu_54138_ap_return_11),
.ap_return_12(grp_sp_ptlut_address_fu_54138_ap_return_12),
.ap_return_13(grp_sp_ptlut_address_fu_54138_ap_return_13),
.ap_return_14(grp_sp_ptlut_address_fu_54138_ap_return_14),
.ap_return_15(grp_sp_ptlut_address_fu_54138_ap_return_15),
.ap_return_16(grp_sp_ptlut_address_fu_54138_ap_return_16)
);
sp_match_ph_seg call_ret1_sp_match_ph_seg_fu_54225(
.ph_1_2_1_1_V_read(ap_reg_ppstg_phd_1_2_1_1_V_reg_61983_pp0_iter4),
.ph_1_3_1_1_V_read(ap_reg_ppstg_phd_1_3_1_1_V_reg_61988_pp0_iter4),
.ph_1_4_1_1_V_read(ap_reg_ppstg_phd_1_4_1_1_V_reg_61993_pp0_iter4),
.ph_2_0_1_1_V_read(ap_reg_ppstg_phd_2_0_1_1_V_reg_61998_pp0_iter4),
.ph_2_0_4_1_V_read(ap_reg_ppstg_phd_2_0_4_1_V_reg_62003_pp0_iter4),
.ph_2_0_7_1_V_read(ap_reg_ppstg_phd_2_0_7_1_V_reg_62008_pp0_iter4),
.ph_2_2_4_1_V_read(ap_reg_ppstg_phd_2_2_4_1_V_reg_62013_pp0_iter4),
.ph_2_3_4_1_V_read(ap_reg_ppstg_phd_2_3_4_1_V_reg_62018_pp0_iter4),
.ph_2_4_4_1_V_read(ap_reg_ppstg_phd_2_4_4_1_V_reg_62023_pp0_iter4),
.th11_2_0_1_0_V_read(ap_reg_ppstg_th11d_2_0_1_0_V_reg_62028_pp0_iter4),
.th11_2_0_1_1_V_read(ap_reg_ppstg_th11d_2_0_1_1_V_reg_62033_pp0_iter4),
.th11_2_0_1_2_V_read(ap_reg_ppstg_th11d_2_0_1_2_V_reg_62038_pp0_iter4),
.th11_2_0_1_3_V_read(ap_reg_ppstg_th11d_2_0_1_3_V_reg_62043_pp0_iter4),
.th_1_2_1_0_V_read(ap_reg_ppstg_thd_1_2_1_0_V_reg_62048_pp0_iter4),
.th_1_2_1_1_V_read(ap_reg_ppstg_thd_1_2_1_1_V_reg_62053_pp0_iter4),
.th_1_3_1_0_V_read(ap_reg_ppstg_thd_1_3_1_0_V_reg_62058_pp0_iter4),
.th_1_3_1_1_V_read(ap_reg_ppstg_thd_1_3_1_1_V_reg_62063_pp0_iter4),
.th_1_4_1_0_V_read(ap_reg_ppstg_thd_1_4_1_0_V_reg_62068_pp0_iter4),
.th_1_4_1_1_V_read(ap_reg_ppstg_thd_1_4_1_1_V_reg_62073_pp0_iter4),
.th_2_0_4_0_V_read(ap_reg_ppstg_thd_2_0_4_0_V_reg_62078_pp0_iter4),
.th_2_0_4_1_V_read(ap_reg_ppstg_thd_2_0_4_1_V_reg_62083_pp0_iter4),
.th_2_0_7_0_V_read(ap_reg_ppstg_thd_2_0_7_0_V_reg_62088_pp0_iter4),
.th_2_0_7_1_V_read(ap_reg_ppstg_thd_2_0_7_1_V_reg_62093_pp0_iter4),
.th_2_2_4_0_V_read(ap_reg_ppstg_thd_2_2_4_0_V_reg_62098_pp0_iter4),
.th_2_2_4_1_V_read(ap_reg_ppstg_thd_2_2_4_1_V_reg_62103_pp0_iter4),
.th_2_3_4_0_V_read(ap_reg_ppstg_thd_2_3_4_0_V_reg_62108_pp0_iter4),
.th_2_3_4_1_V_read(ap_reg_ppstg_thd_2_3_4_1_V_reg_62113_pp0_iter4),
.th_2_4_4_0_V_read(ap_reg_ppstg_thd_2_4_4_0_V_reg_62118_pp0_iter4),
.th_2_4_4_1_V_read(ap_reg_ppstg_thd_2_4_4_1_V_reg_62123_pp0_iter4),
.cpat_1_2_1_1_V_read(ap_reg_ppstg_cpatd_1_2_1_1_V_reg_62128_pp0_iter4),
.cpat_1_3_1_1_V_read(ap_reg_ppstg_cpatd_1_3_1_1_V_reg_62133_pp0_iter4),
.cpat_1_4_1_1_V_read(ap_reg_ppstg_cpatd_1_4_1_1_V_reg_62138_pp0_iter4),
.cpat_2_0_1_1_V_read(ap_reg_ppstg_cpatd_2_0_1_1_V_reg_62143_pp0_iter4),
.cpat_2_0_4_1_V_read(ap_reg_ppstg_cpatd_2_0_4_1_V_reg_62148_pp0_iter4),
.cpat_2_0_7_1_V_read(ap_reg_ppstg_cpatd_2_0_7_1_V_reg_62153_pp0_iter4),
.cpat_2_2_4_1_V_read(ap_reg_ppstg_cpatd_2_2_4_1_V_reg_62158_pp0_iter4),
.cpat_2_3_4_1_V_read(ap_reg_ppstg_cpatd_2_3_4_1_V_reg_62163_pp0_iter4),
.cpat_2_4_4_1_V_read(ap_reg_ppstg_cpatd_2_4_4_1_V_reg_62168_pp0_iter4),
.ap_return_0(call_ret1_sp_match_ph_seg_fu_54225_ap_return_0),
.ap_return_1(call_ret1_sp_match_ph_seg_fu_54225_ap_return_1),
.ap_return_2(call_ret1_sp_match_ph_seg_fu_54225_ap_return_2),
.ap_return_3(call_ret1_sp_match_ph_seg_fu_54225_ap_return_3),
.ap_return_4(call_ret1_sp_match_ph_seg_fu_54225_ap_return_4),
.ap_return_5(call_ret1_sp_match_ph_seg_fu_54225_ap_return_5),
.ap_return_6(call_ret1_sp_match_ph_seg_fu_54225_ap_return_6),
.ap_return_7(call_ret1_sp_match_ph_seg_fu_54225_ap_return_7),
.ap_return_8(call_ret1_sp_match_ph_seg_fu_54225_ap_return_8),
.ap_return_9(call_ret1_sp_match_ph_seg_fu_54225_ap_return_9),
.ap_return_10(call_ret1_sp_match_ph_seg_fu_54225_ap_return_10),
.ap_return_11(call_ret1_sp_match_ph_seg_fu_54225_ap_return_11),
.ap_return_12(call_ret1_sp_match_ph_seg_fu_54225_ap_return_12),
.ap_return_13(call_ret1_sp_match_ph_seg_fu_54225_ap_return_13),
.ap_return_14(call_ret1_sp_match_ph_seg_fu_54225_ap_return_14),
.ap_return_15(call_ret1_sp_match_ph_seg_fu_54225_ap_return_15),
.ap_return_16(call_ret1_sp_match_ph_seg_fu_54225_ap_return_16),
.ap_return_17(call_ret1_sp_match_ph_seg_fu_54225_ap_return_17),
.ap_return_18(call_ret1_sp_match_ph_seg_fu_54225_ap_return_18),
.ap_return_19(call_ret1_sp_match_ph_seg_fu_54225_ap_return_19),
.ap_return_20(call_ret1_sp_match_ph_seg_fu_54225_ap_return_20),
.ap_return_21(call_ret1_sp_match_ph_seg_fu_54225_ap_return_21),
.ap_return_22(call_ret1_sp_match_ph_seg_fu_54225_ap_return_22),
.ap_return_23(call_ret1_sp_match_ph_seg_fu_54225_ap_return_23),
.ap_return_24(call_ret1_sp_match_ph_seg_fu_54225_ap_return_24),
.ap_return_25(call_ret1_sp_match_ph_seg_fu_54225_ap_return_25),
.ap_return_26(call_ret1_sp_match_ph_seg_fu_54225_ap_return_26),
.ap_return_27(call_ret1_sp_match_ph_seg_fu_54225_ap_return_27),
.ap_return_28(call_ret1_sp_match_ph_seg_fu_54225_ap_return_28),
.ap_return_29(call_ret1_sp_match_ph_seg_fu_54225_ap_return_29),
.ap_return_30(call_ret1_sp_match_ph_seg_fu_54225_ap_return_30),
.ap_return_31(call_ret1_sp_match_ph_seg_fu_54225_ap_return_31),
.ap_return_32(call_ret1_sp_match_ph_seg_fu_54225_ap_return_32),
.ap_return_33(call_ret1_sp_match_ph_seg_fu_54225_ap_return_33),
.ap_return_34(call_ret1_sp_match_ph_seg_fu_54225_ap_return_34),
.ap_return_35(call_ret1_sp_match_ph_seg_fu_54225_ap_return_35),
.ap_return_36(call_ret1_sp_match_ph_seg_fu_54225_ap_return_36),
.ap_return_37(call_ret1_sp_match_ph_seg_fu_54225_ap_return_37),
.ap_return_38(call_ret1_sp_match_ph_seg_fu_54225_ap_return_38),
.ap_return_39(call_ret1_sp_match_ph_seg_fu_54225_ap_return_39),
.ap_return_40(call_ret1_sp_match_ph_seg_fu_54225_ap_return_40),
.ap_return_41(call_ret1_sp_match_ph_seg_fu_54225_ap_return_41),
.ap_return_42(call_ret1_sp_match_ph_seg_fu_54225_ap_return_42),
.ap_return_43(call_ret1_sp_match_ph_seg_fu_54225_ap_return_43),
.ap_return_44(call_ret1_sp_match_ph_seg_fu_54225_ap_return_44),
.ap_return_45(call_ret1_sp_match_ph_seg_fu_54225_ap_return_45),
.ap_return_46(call_ret1_sp_match_ph_seg_fu_54225_ap_return_46),
.ap_return_47(call_ret1_sp_match_ph_seg_fu_54225_ap_return_47),
.ap_return_48(call_ret1_sp_match_ph_seg_fu_54225_ap_return_48),
.ap_return_49(call_ret1_sp_match_ph_seg_fu_54225_ap_return_49),
.ap_return_50(call_ret1_sp_match_ph_seg_fu_54225_ap_return_50),
.ap_return_51(call_ret1_sp_match_ph_seg_fu_54225_ap_return_51),
.ap_return_52(call_ret1_sp_match_ph_seg_fu_54225_ap_return_52),
.ap_return_53(call_ret1_sp_match_ph_seg_fu_54225_ap_return_53),
.ap_return_54(call_ret1_sp_match_ph_seg_fu_54225_ap_return_54),
.ap_return_55(call_ret1_sp_match_ph_seg_fu_54225_ap_return_55),
.ap_return_56(call_ret1_sp_match_ph_seg_fu_54225_ap_return_56),
.ap_return_57(call_ret1_sp_match_ph_seg_fu_54225_ap_return_57),
.ap_return_58(call_ret1_sp_match_ph_seg_fu_54225_ap_return_58),
.ap_return_59(call_ret1_sp_match_ph_seg_fu_54225_ap_return_59),
.ap_return_60(call_ret1_sp_match_ph_seg_fu_54225_ap_return_60),
.ap_return_61(call_ret1_sp_match_ph_seg_fu_54225_ap_return_61),
.ap_return_62(call_ret1_sp_match_ph_seg_fu_54225_ap_return_62),
.ap_return_63(call_ret1_sp_match_ph_seg_fu_54225_ap_return_63),
.ap_return_64(call_ret1_sp_match_ph_seg_fu_54225_ap_return_64),
.ap_return_65(call_ret1_sp_match_ph_seg_fu_54225_ap_return_65),
.ap_return_66(call_ret1_sp_match_ph_seg_fu_54225_ap_return_66),
.ap_return_67(call_ret1_sp_match_ph_seg_fu_54225_ap_return_67),
.ap_return_68(call_ret1_sp_match_ph_seg_fu_54225_ap_return_68),
.ap_return_69(call_ret1_sp_match_ph_seg_fu_54225_ap_return_69),
.ap_return_70(call_ret1_sp_match_ph_seg_fu_54225_ap_return_70),
.ap_return_71(call_ret1_sp_match_ph_seg_fu_54225_ap_return_71),
.ap_return_72(call_ret1_sp_match_ph_seg_fu_54225_ap_return_72),
.ap_return_73(call_ret1_sp_match_ph_seg_fu_54225_ap_return_73),
.ap_return_74(call_ret1_sp_match_ph_seg_fu_54225_ap_return_74),
.ap_return_75(call_ret1_sp_match_ph_seg_fu_54225_ap_return_75),
.ap_return_76(call_ret1_sp_match_ph_seg_fu_54225_ap_return_76),
.ap_return_77(call_ret1_sp_match_ph_seg_fu_54225_ap_return_77),
.ap_return_78(call_ret1_sp_match_ph_seg_fu_54225_ap_return_78),
.ap_return_79(call_ret1_sp_match_ph_seg_fu_54225_ap_return_79),
.ap_return_80(call_ret1_sp_match_ph_seg_fu_54225_ap_return_80),
.ap_return_81(call_ret1_sp_match_ph_seg_fu_54225_ap_return_81),
.ap_return_82(call_ret1_sp_match_ph_seg_fu_54225_ap_return_82),
.ap_return_83(call_ret1_sp_match_ph_seg_fu_54225_ap_return_83),
.ap_return_84(call_ret1_sp_match_ph_seg_fu_54225_ap_return_84),
.ap_return_85(call_ret1_sp_match_ph_seg_fu_54225_ap_return_85),
.ap_return_86(call_ret1_sp_match_ph_seg_fu_54225_ap_return_86),
.ap_return_87(call_ret1_sp_match_ph_seg_fu_54225_ap_return_87),
.ap_return_88(call_ret1_sp_match_ph_seg_fu_54225_ap_return_88),
.ap_return_89(call_ret1_sp_match_ph_seg_fu_54225_ap_return_89),
.ap_return_90(call_ret1_sp_match_ph_seg_fu_54225_ap_return_90),
.ap_return_91(call_ret1_sp_match_ph_seg_fu_54225_ap_return_91),
.ap_return_92(call_ret1_sp_match_ph_seg_fu_54225_ap_return_92),
.ap_return_93(call_ret1_sp_match_ph_seg_fu_54225_ap_return_93),
.ap_return_94(call_ret1_sp_match_ph_seg_fu_54225_ap_return_94),
.ap_return_95(call_ret1_sp_match_ph_seg_fu_54225_ap_return_95),
.ap_return_96(call_ret1_sp_match_ph_seg_fu_54225_ap_return_96),
.ap_return_97(call_ret1_sp_match_ph_seg_fu_54225_ap_return_97),
.ap_return_98(call_ret1_sp_match_ph_seg_fu_54225_ap_return_98),
.ap_return_99(call_ret1_sp_match_ph_seg_fu_54225_ap_return_99),
.ap_return_100(call_ret1_sp_match_ph_seg_fu_54225_ap_return_100),
.ap_return_101(call_ret1_sp_match_ph_seg_fu_54225_ap_return_101),
.ap_return_102(call_ret1_sp_match_ph_seg_fu_54225_ap_return_102),
.ap_return_103(call_ret1_sp_match_ph_seg_fu_54225_ap_return_103),
.ap_return_104(call_ret1_sp_match_ph_seg_fu_54225_ap_return_104),
.ap_return_105(call_ret1_sp_match_ph_seg_fu_54225_ap_return_105),
.ap_return_106(call_ret1_sp_match_ph_seg_fu_54225_ap_return_106),
.ap_return_107(call_ret1_sp_match_ph_seg_fu_54225_ap_return_107),
.ap_return_108(call_ret1_sp_match_ph_seg_fu_54225_ap_return_108),
.ap_return_109(call_ret1_sp_match_ph_seg_fu_54225_ap_return_109),
.ap_return_110(call_ret1_sp_match_ph_seg_fu_54225_ap_return_110),
.ap_return_111(call_ret1_sp_match_ph_seg_fu_54225_ap_return_111),
.ap_return_112(call_ret1_sp_match_ph_seg_fu_54225_ap_return_112),
.ap_return_113(call_ret1_sp_match_ph_seg_fu_54225_ap_return_113),
.ap_return_114(call_ret1_sp_match_ph_seg_fu_54225_ap_return_114),
.ap_return_115(call_ret1_sp_match_ph_seg_fu_54225_ap_return_115),
.ap_return_116(call_ret1_sp_match_ph_seg_fu_54225_ap_return_116),
.ap_return_117(call_ret1_sp_match_ph_seg_fu_54225_ap_return_117),
.ap_return_118(call_ret1_sp_match_ph_seg_fu_54225_ap_return_118),
.ap_return_119(call_ret1_sp_match_ph_seg_fu_54225_ap_return_119),
.ap_return_120(call_ret1_sp_match_ph_seg_fu_54225_ap_return_120),
.ap_return_121(call_ret1_sp_match_ph_seg_fu_54225_ap_return_121),
.ap_return_122(call_ret1_sp_match_ph_seg_fu_54225_ap_return_122),
.ap_return_123(call_ret1_sp_match_ph_seg_fu_54225_ap_return_123),
.ap_return_124(call_ret1_sp_match_ph_seg_fu_54225_ap_return_124),
.ap_return_125(call_ret1_sp_match_ph_seg_fu_54225_ap_return_125),
.ap_return_126(call_ret1_sp_match_ph_seg_fu_54225_ap_return_126),
.ap_return_127(call_ret1_sp_match_ph_seg_fu_54225_ap_return_127),
.ap_return_128(call_ret1_sp_match_ph_seg_fu_54225_ap_return_128),
.ap_return_129(call_ret1_sp_match_ph_seg_fu_54225_ap_return_129),
.ap_return_130(call_ret1_sp_match_ph_seg_fu_54225_ap_return_130),
.ap_return_131(call_ret1_sp_match_ph_seg_fu_54225_ap_return_131),
.ap_return_132(call_ret1_sp_match_ph_seg_fu_54225_ap_return_132),
.ap_return_133(call_ret1_sp_match_ph_seg_fu_54225_ap_return_133),
.ap_return_134(call_ret1_sp_match_ph_seg_fu_54225_ap_return_134),
.ap_return_135(call_ret1_sp_match_ph_seg_fu_54225_ap_return_135),
.ap_return_136(call_ret1_sp_match_ph_seg_fu_54225_ap_return_136),
.ap_return_137(call_ret1_sp_match_ph_seg_fu_54225_ap_return_137),
.ap_return_138(call_ret1_sp_match_ph_seg_fu_54225_ap_return_138),
.ap_return_139(call_ret1_sp_match_ph_seg_fu_54225_ap_return_139),
.ap_return_140(call_ret1_sp_match_ph_seg_fu_54225_ap_return_140),
.ap_return_141(call_ret1_sp_match_ph_seg_fu_54225_ap_return_141),
.ap_return_142(call_ret1_sp_match_ph_seg_fu_54225_ap_return_142),
.ap_return_143(call_ret1_sp_match_ph_seg_fu_54225_ap_return_143),
.ap_return_144(call_ret1_sp_match_ph_seg_fu_54225_ap_return_144),
.ap_return_145(call_ret1_sp_match_ph_seg_fu_54225_ap_return_145),
.ap_return_146(call_ret1_sp_match_ph_seg_fu_54225_ap_return_146),
.ap_return_147(call_ret1_sp_match_ph_seg_fu_54225_ap_return_147),
.ap_return_148(call_ret1_sp_match_ph_seg_fu_54225_ap_return_148),
.ap_return_149(call_ret1_sp_match_ph_seg_fu_54225_ap_return_149),
.ap_return_150(call_ret1_sp_match_ph_seg_fu_54225_ap_return_150),
.ap_return_151(call_ret1_sp_match_ph_seg_fu_54225_ap_return_151),
.ap_return_152(call_ret1_sp_match_ph_seg_fu_54225_ap_return_152),
.ap_return_153(call_ret1_sp_match_ph_seg_fu_54225_ap_return_153),
.ap_return_154(call_ret1_sp_match_ph_seg_fu_54225_ap_return_154),
.ap_return_155(call_ret1_sp_match_ph_seg_fu_54225_ap_return_155),
.ap_return_156(call_ret1_sp_match_ph_seg_fu_54225_ap_return_156),
.ap_return_157(call_ret1_sp_match_ph_seg_fu_54225_ap_return_157),
.ap_return_158(call_ret1_sp_match_ph_seg_fu_54225_ap_return_158),
.ap_return_159(call_ret1_sp_match_ph_seg_fu_54225_ap_return_159),
.ap_return_160(call_ret1_sp_match_ph_seg_fu_54225_ap_return_160),
.ap_return_161(call_ret1_sp_match_ph_seg_fu_54225_ap_return_161),
.ap_return_162(call_ret1_sp_match_ph_seg_fu_54225_ap_return_162),
.ap_return_163(call_ret1_sp_match_ph_seg_fu_54225_ap_return_163),
.ap_return_164(call_ret1_sp_match_ph_seg_fu_54225_ap_return_164),
.ap_return_165(call_ret1_sp_match_ph_seg_fu_54225_ap_return_165),
.ap_return_166(call_ret1_sp_match_ph_seg_fu_54225_ap_return_166),
.ap_return_167(call_ret1_sp_match_ph_seg_fu_54225_ap_return_167),
.ap_return_168(call_ret1_sp_match_ph_seg_fu_54225_ap_return_168),
.ap_return_169(call_ret1_sp_match_ph_seg_fu_54225_ap_return_169),
.ap_return_170(call_ret1_sp_match_ph_seg_fu_54225_ap_return_170),
.ap_return_171(call_ret1_sp_match_ph_seg_fu_54225_ap_return_171),
.ap_return_172(call_ret1_sp_match_ph_seg_fu_54225_ap_return_172),
.ap_return_173(call_ret1_sp_match_ph_seg_fu_54225_ap_return_173),
.ap_return_174(call_ret1_sp_match_ph_seg_fu_54225_ap_return_174),
.ap_return_175(call_ret1_sp_match_ph_seg_fu_54225_ap_return_175),
.ap_return_176(call_ret1_sp_match_ph_seg_fu_54225_ap_return_176),
.ap_return_177(call_ret1_sp_match_ph_seg_fu_54225_ap_return_177),
.ap_return_178(call_ret1_sp_match_ph_seg_fu_54225_ap_return_178),
.ap_return_179(call_ret1_sp_match_ph_seg_fu_54225_ap_return_179),
.ap_return_180(call_ret1_sp_match_ph_seg_fu_54225_ap_return_180),
.ap_return_181(call_ret1_sp_match_ph_seg_fu_54225_ap_return_181),
.ap_return_182(call_ret1_sp_match_ph_seg_fu_54225_ap_return_182),
.ap_return_183(call_ret1_sp_match_ph_seg_fu_54225_ap_return_183),
.ap_return_184(call_ret1_sp_match_ph_seg_fu_54225_ap_return_184),
.ap_return_185(call_ret1_sp_match_ph_seg_fu_54225_ap_return_185),
.ap_return_186(call_ret1_sp_match_ph_seg_fu_54225_ap_return_186),
.ap_return_187(call_ret1_sp_match_ph_seg_fu_54225_ap_return_187),
.ap_return_188(call_ret1_sp_match_ph_seg_fu_54225_ap_return_188),
.ap_return_189(call_ret1_sp_match_ph_seg_fu_54225_ap_return_189),
.ap_return_190(call_ret1_sp_match_ph_seg_fu_54225_ap_return_190),
.ap_return_191(call_ret1_sp_match_ph_seg_fu_54225_ap_return_191),
.ap_return_192(call_ret1_sp_match_ph_seg_fu_54225_ap_return_192),
.ap_return_193(call_ret1_sp_match_ph_seg_fu_54225_ap_return_193),
.ap_return_194(call_ret1_sp_match_ph_seg_fu_54225_ap_return_194),
.ap_return_195(call_ret1_sp_match_ph_seg_fu_54225_ap_return_195),
.ap_return_196(call_ret1_sp_match_ph_seg_fu_54225_ap_return_196),
.ap_return_197(call_ret1_sp_match_ph_seg_fu_54225_ap_return_197),
.ap_return_198(call_ret1_sp_match_ph_seg_fu_54225_ap_return_198),
.ap_return_199(call_ret1_sp_match_ph_seg_fu_54225_ap_return_199),
.ap_return_200(call_ret1_sp_match_ph_seg_fu_54225_ap_return_200),
.ap_return_201(call_ret1_sp_match_ph_seg_fu_54225_ap_return_201),
.ap_return_202(call_ret1_sp_match_ph_seg_fu_54225_ap_return_202),
.ap_return_203(call_ret1_sp_match_ph_seg_fu_54225_ap_return_203),
.ap_return_204(call_ret1_sp_match_ph_seg_fu_54225_ap_return_204),
.ap_return_205(call_ret1_sp_match_ph_seg_fu_54225_ap_return_205),
.ap_return_206(call_ret1_sp_match_ph_seg_fu_54225_ap_return_206),
.ap_return_207(call_ret1_sp_match_ph_seg_fu_54225_ap_return_207),
.ap_return_208(call_ret1_sp_match_ph_seg_fu_54225_ap_return_208),
.ap_return_209(call_ret1_sp_match_ph_seg_fu_54225_ap_return_209),
.ap_return_210(call_ret1_sp_match_ph_seg_fu_54225_ap_return_210),
.ap_return_211(call_ret1_sp_match_ph_seg_fu_54225_ap_return_211),
.ap_return_212(call_ret1_sp_match_ph_seg_fu_54225_ap_return_212),
.ap_return_213(call_ret1_sp_match_ph_seg_fu_54225_ap_return_213),
.ap_return_214(call_ret1_sp_match_ph_seg_fu_54225_ap_return_214),
.ap_return_215(call_ret1_sp_match_ph_seg_fu_54225_ap_return_215)
);
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_pp0_stg0_fsm_0;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_reg_call_ret7_sp_extend_sector_fu_54039_ap_start <= 1'b0;
end else begin
if (((1'b1 == ap_reg_ppiten_pp0_it1) & (1'b1 == ap_sig_cseq_ST_pp0_stg0_fsm_0))) begin
ap_reg_call_ret7_sp_extend_sector_fu_54039_ap_start <= 1'b1;
end else if ((1'b1 == call_ret7_sp_extend_sector_fu_54039_ap_ready)) begin
ap_reg_call_ret7_sp_extend_sector_fu_54039_ap_start <= 1'b0;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_reg_grp_sp_ph_pattern_sector_fu_28574_ap_start <= 1'b0;
end else begin
if (((1'b1 == ap_reg_ppiten_pp0_it1) & (1'b1 == ap_sig_cseq_ST_pp0_stg0_fsm_0))) begin
ap_reg_grp_sp_ph_pattern_sector_fu_28574_ap_start <= 1'b1;
end else if ((1'b1 == grp_sp_ph_pattern_sector_fu_28574_ap_ready)) begin
ap_reg_grp_sp_ph_pattern_sector_fu_28574_ap_start <= 1'b0;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it1 <= 1'b0;
end else begin
if ((1'b1 == ap_sig_cseq_ST_pp0_stg0_fsm_0)) begin
ap_reg_ppiten_pp0_it1 <= 1'b1;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it10 <= 1'b0;
end else begin
ap_reg_ppiten_pp0_it10 <= ap_reg_ppiten_pp0_it9;
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it2 <= 1'b0;
end else begin
ap_reg_ppiten_pp0_it2 <= ap_reg_ppiten_pp0_it1;
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it3 <= 1'b0;
end else begin
ap_reg_ppiten_pp0_it3 <= ap_reg_ppiten_pp0_it2;
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it4 <= 1'b0;
end else begin
ap_reg_ppiten_pp0_it4 <= ap_reg_ppiten_pp0_it3;
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it5 <= 1'b0;
end else begin
ap_reg_ppiten_pp0_it5 <= ap_reg_ppiten_pp0_it4;
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it6 <= 1'b0;
end else begin
ap_reg_ppiten_pp0_it6 <= ap_reg_ppiten_pp0_it5;
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it7 <= 1'b0;
end else begin
ap_reg_ppiten_pp0_it7 <= ap_reg_ppiten_pp0_it6;
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it8 <= 1'b0;
end else begin
ap_reg_ppiten_pp0_it8 <= ap_reg_ppiten_pp0_it7;
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it9 <= 1'b0;
end else begin
ap_reg_ppiten_pp0_it9 <= ap_reg_ppiten_pp0_it8;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == 1'b1)) begin
ap_reg_ppstg_cpatd_1_2_1_1_V_reg_62128_pp0_iter4 <= cpatd_1_2_1_1_V_reg_62128;
ap_reg_ppstg_cpatd_1_3_1_1_V_reg_62133_pp0_iter4 <= cpatd_1_3_1_1_V_reg_62133;
ap_reg_ppstg_cpatd_1_4_1_1_V_reg_62138_pp0_iter4 <= cpatd_1_4_1_1_V_reg_62138;
ap_reg_ppstg_cpatd_2_0_1_1_V_reg_62143_pp0_iter4 <= cpatd_2_0_1_1_V_reg_62143;
ap_reg_ppstg_cpatd_2_0_4_1_V_reg_62148_pp0_iter4 <= cpatd_2_0_4_1_V_reg_62148;
ap_reg_ppstg_cpatd_2_0_7_1_V_reg_62153_pp0_iter4 <= cpatd_2_0_7_1_V_reg_62153;
ap_reg_ppstg_cpatd_2_2_4_1_V_reg_62158_pp0_iter4 <= cpatd_2_2_4_1_V_reg_62158;
ap_reg_ppstg_cpatd_2_3_4_1_V_reg_62163_pp0_iter4 <= cpatd_2_3_4_1_V_reg_62163;
ap_reg_ppstg_cpatd_2_4_4_1_V_reg_62168_pp0_iter4 <= cpatd_2_4_4_1_V_reg_62168;
ap_reg_ppstg_patt_ph_si_0_0_V_reg_62173_pp0_iter6 <= patt_ph_si_0_0_V_reg_62173;
ap_reg_ppstg_patt_ph_si_0_1_V_reg_62178_pp0_iter6 <= patt_ph_si_0_1_V_reg_62178;
ap_reg_ppstg_patt_ph_si_0_2_V_reg_62183_pp0_iter6 <= patt_ph_si_0_2_V_reg_62183;
ap_reg_ppstg_patt_ph_si_1_0_V_reg_62188_pp0_iter6 <= patt_ph_si_1_0_V_reg_62188;
ap_reg_ppstg_patt_ph_si_1_1_V_reg_62193_pp0_iter6 <= patt_ph_si_1_1_V_reg_62193;
ap_reg_ppstg_patt_ph_si_1_2_V_reg_62198_pp0_iter6 <= patt_ph_si_1_2_V_reg_62198;
ap_reg_ppstg_patt_ph_si_2_0_V_reg_62203_pp0_iter6 <= patt_ph_si_2_0_V_reg_62203;
ap_reg_ppstg_patt_ph_si_2_1_V_reg_62208_pp0_iter6 <= patt_ph_si_2_1_V_reg_62208;
ap_reg_ppstg_patt_ph_si_2_2_V_reg_62213_pp0_iter6 <= patt_ph_si_2_2_V_reg_62213;
ap_reg_ppstg_patt_ph_si_3_0_V_reg_62218_pp0_iter6 <= patt_ph_si_3_0_V_reg_62218;
ap_reg_ppstg_patt_ph_si_3_1_V_reg_62223_pp0_iter6 <= patt_ph_si_3_1_V_reg_62223;
ap_reg_ppstg_patt_ph_si_3_2_V_reg_62228_pp0_iter6 <= patt_ph_si_3_2_V_reg_62228;
ap_reg_ppstg_phd_1_2_1_1_V_reg_61983_pp0_iter4 <= phd_1_2_1_1_V_reg_61983;
ap_reg_ppstg_phd_1_3_1_1_V_reg_61988_pp0_iter4 <= phd_1_3_1_1_V_reg_61988;
ap_reg_ppstg_phd_1_4_1_1_V_reg_61993_pp0_iter4 <= phd_1_4_1_1_V_reg_61993;
ap_reg_ppstg_phd_2_0_1_1_V_reg_61998_pp0_iter4 <= phd_2_0_1_1_V_reg_61998;
ap_reg_ppstg_phd_2_0_4_1_V_reg_62003_pp0_iter4 <= phd_2_0_4_1_V_reg_62003;
ap_reg_ppstg_phd_2_0_7_1_V_reg_62008_pp0_iter4 <= phd_2_0_7_1_V_reg_62008;
ap_reg_ppstg_phd_2_2_4_1_V_reg_62013_pp0_iter4 <= phd_2_2_4_1_V_reg_62013;
ap_reg_ppstg_phd_2_3_4_1_V_reg_62018_pp0_iter4 <= phd_2_3_4_1_V_reg_62018;
ap_reg_ppstg_phd_2_4_4_1_V_reg_62023_pp0_iter4 <= phd_2_4_4_1_V_reg_62023;
ap_reg_ppstg_th11d_2_0_1_0_V_reg_62028_pp0_iter4 <= th11d_2_0_1_0_V_reg_62028;
ap_reg_ppstg_th11d_2_0_1_1_V_reg_62033_pp0_iter4 <= th11d_2_0_1_1_V_reg_62033;
ap_reg_ppstg_th11d_2_0_1_2_V_reg_62038_pp0_iter4 <= th11d_2_0_1_2_V_reg_62038;
ap_reg_ppstg_th11d_2_0_1_3_V_reg_62043_pp0_iter4 <= th11d_2_0_1_3_V_reg_62043;
ap_reg_ppstg_thd_1_2_1_0_V_reg_62048_pp0_iter4 <= thd_1_2_1_0_V_reg_62048;
ap_reg_ppstg_thd_1_2_1_1_V_reg_62053_pp0_iter4 <= thd_1_2_1_1_V_reg_62053;
ap_reg_ppstg_thd_1_3_1_0_V_reg_62058_pp0_iter4 <= thd_1_3_1_0_V_reg_62058;
ap_reg_ppstg_thd_1_3_1_1_V_reg_62063_pp0_iter4 <= thd_1_3_1_1_V_reg_62063;
ap_reg_ppstg_thd_1_4_1_0_V_reg_62068_pp0_iter4 <= thd_1_4_1_0_V_reg_62068;
ap_reg_ppstg_thd_1_4_1_1_V_reg_62073_pp0_iter4 <= thd_1_4_1_1_V_reg_62073;
ap_reg_ppstg_thd_2_0_4_0_V_reg_62078_pp0_iter4 <= thd_2_0_4_0_V_reg_62078;
ap_reg_ppstg_thd_2_0_4_1_V_reg_62083_pp0_iter4 <= thd_2_0_4_1_V_reg_62083;
ap_reg_ppstg_thd_2_0_7_0_V_reg_62088_pp0_iter4 <= thd_2_0_7_0_V_reg_62088;
ap_reg_ppstg_thd_2_0_7_1_V_reg_62093_pp0_iter4 <= thd_2_0_7_1_V_reg_62093;
ap_reg_ppstg_thd_2_2_4_0_V_reg_62098_pp0_iter4 <= thd_2_2_4_0_V_reg_62098;
ap_reg_ppstg_thd_2_2_4_1_V_reg_62103_pp0_iter4 <= thd_2_2_4_1_V_reg_62103;
ap_reg_ppstg_thd_2_3_4_0_V_reg_62108_pp0_iter4 <= thd_2_3_4_0_V_reg_62108;
ap_reg_ppstg_thd_2_3_4_1_V_reg_62113_pp0_iter4 <= thd_2_3_4_1_V_reg_62113;
ap_reg_ppstg_thd_2_4_4_0_V_reg_62118_pp0_iter4 <= thd_2_4_4_0_V_reg_62118;
ap_reg_ppstg_thd_2_4_4_1_V_reg_62123_pp0_iter4 <= thd_2_4_4_1_V_reg_62123;
bt_ci_t_0_0_V_reg_65044 <= grp_sp_best_tracks_fu_51719_ap_return_93;
bt_ci_t_0_1_V_reg_65050 <= grp_sp_best_tracks_fu_51719_ap_return_94;
bt_ci_t_0_2_V_reg_65056 <= grp_sp_best_tracks_fu_51719_ap_return_95;
bt_ci_t_0_3_V_reg_65062 <= grp_sp_best_tracks_fu_51719_ap_return_96;
bt_ci_t_0_4_V_reg_65068 <= grp_sp_best_tracks_fu_51719_ap_return_97;
bt_ci_t_1_0_V_reg_65074 <= grp_sp_best_tracks_fu_51719_ap_return_98;
bt_ci_t_1_1_V_reg_65080 <= grp_sp_best_tracks_fu_51719_ap_return_99;
bt_ci_t_1_2_V_reg_65086 <= grp_sp_best_tracks_fu_51719_ap_return_100;
bt_ci_t_1_3_V_reg_65092 <= grp_sp_best_tracks_fu_51719_ap_return_101;
bt_ci_t_1_4_V_reg_65098 <= grp_sp_best_tracks_fu_51719_ap_return_102;
bt_ci_t_2_0_V_reg_65104 <= grp_sp_best_tracks_fu_51719_ap_return_103;
bt_ci_t_2_1_V_reg_65110 <= grp_sp_best_tracks_fu_51719_ap_return_104;
bt_ci_t_2_2_V_reg_65116 <= grp_sp_best_tracks_fu_51719_ap_return_105;
bt_ci_t_2_3_V_reg_65122 <= grp_sp_best_tracks_fu_51719_ap_return_106;
bt_ci_t_2_4_V_reg_65128 <= grp_sp_best_tracks_fu_51719_ap_return_107;
bt_cpattern_t_0_0_V_reg_64549 <= grp_sp_best_tracks_fu_51719_ap_return_6;
bt_cpattern_t_0_1_V_reg_64555 <= grp_sp_best_tracks_fu_51719_ap_return_7;
bt_cpattern_t_0_2_V_reg_64561 <= grp_sp_best_tracks_fu_51719_ap_return_8;
bt_cpattern_t_0_3_V_reg_64567 <= grp_sp_best_tracks_fu_51719_ap_return_9;
bt_cpattern_t_1_0_V_reg_64573 <= grp_sp_best_tracks_fu_51719_ap_return_10;
bt_cpattern_t_1_1_V_reg_64579 <= grp_sp_best_tracks_fu_51719_ap_return_11;
bt_cpattern_t_1_2_V_reg_64585 <= grp_sp_best_tracks_fu_51719_ap_return_12;
bt_cpattern_t_1_3_V_reg_64591 <= grp_sp_best_tracks_fu_51719_ap_return_13;
bt_cpattern_t_2_0_V_reg_64597 <= grp_sp_best_tracks_fu_51719_ap_return_14;
bt_cpattern_t_2_1_V_reg_64603 <= grp_sp_best_tracks_fu_51719_ap_return_15;
bt_cpattern_t_2_2_V_reg_64609 <= grp_sp_best_tracks_fu_51719_ap_return_16;
bt_cpattern_t_2_3_V_reg_64615 <= grp_sp_best_tracks_fu_51719_ap_return_17;
bt_delta_ph_t_0_0_V_reg_64621 <= grp_sp_best_tracks_fu_51719_ap_return_18;
bt_delta_ph_t_0_1_V_reg_64627 <= grp_sp_best_tracks_fu_51719_ap_return_19;
bt_delta_ph_t_0_2_V_reg_64633 <= grp_sp_best_tracks_fu_51719_ap_return_20;
bt_delta_ph_t_0_3_V_reg_64639 <= grp_sp_best_tracks_fu_51719_ap_return_21;
bt_delta_ph_t_0_4_V_reg_64645 <= grp_sp_best_tracks_fu_51719_ap_return_22;
bt_delta_ph_t_0_5_V_reg_64651 <= grp_sp_best_tracks_fu_51719_ap_return_23;
bt_delta_ph_t_1_0_V_reg_64657 <= grp_sp_best_tracks_fu_51719_ap_return_24;
bt_delta_ph_t_1_1_V_reg_64663 <= grp_sp_best_tracks_fu_51719_ap_return_25;
bt_delta_ph_t_1_2_V_reg_64669 <= grp_sp_best_tracks_fu_51719_ap_return_26;
bt_delta_ph_t_1_3_V_reg_64675 <= grp_sp_best_tracks_fu_51719_ap_return_27;
bt_delta_ph_t_1_4_V_reg_64681 <= grp_sp_best_tracks_fu_51719_ap_return_28;
bt_delta_ph_t_1_5_V_reg_64687 <= grp_sp_best_tracks_fu_51719_ap_return_29;
bt_delta_ph_t_2_0_V_reg_64693 <= grp_sp_best_tracks_fu_51719_ap_return_30;
bt_delta_ph_t_2_1_V_reg_64699 <= grp_sp_best_tracks_fu_51719_ap_return_31;
bt_delta_ph_t_2_2_V_reg_64705 <= grp_sp_best_tracks_fu_51719_ap_return_32;
bt_delta_ph_t_2_3_V_reg_64711 <= grp_sp_best_tracks_fu_51719_ap_return_33;
bt_delta_ph_t_2_4_V_reg_64717 <= grp_sp_best_tracks_fu_51719_ap_return_34;
bt_delta_ph_t_2_5_V_reg_64723 <= grp_sp_best_tracks_fu_51719_ap_return_35;
bt_delta_th_t_0_0_V_reg_64729 <= grp_sp_best_tracks_fu_51719_ap_return_36;
bt_delta_th_t_0_1_V_reg_64735 <= grp_sp_best_tracks_fu_51719_ap_return_37;
bt_delta_th_t_0_2_V_reg_64741 <= grp_sp_best_tracks_fu_51719_ap_return_38;
bt_delta_th_t_0_3_V_reg_64747 <= grp_sp_best_tracks_fu_51719_ap_return_39;
bt_delta_th_t_0_4_V_reg_64753 <= grp_sp_best_tracks_fu_51719_ap_return_40;
bt_delta_th_t_0_5_V_reg_64759 <= grp_sp_best_tracks_fu_51719_ap_return_41;
bt_delta_th_t_1_0_V_reg_64765 <= grp_sp_best_tracks_fu_51719_ap_return_42;
bt_delta_th_t_1_1_V_reg_64771 <= grp_sp_best_tracks_fu_51719_ap_return_43;
bt_delta_th_t_1_2_V_reg_64777 <= grp_sp_best_tracks_fu_51719_ap_return_44;
bt_delta_th_t_1_3_V_reg_64783 <= grp_sp_best_tracks_fu_51719_ap_return_45;
bt_delta_th_t_1_4_V_reg_64789 <= grp_sp_best_tracks_fu_51719_ap_return_46;
bt_delta_th_t_1_5_V_reg_64795 <= grp_sp_best_tracks_fu_51719_ap_return_47;
bt_delta_th_t_2_0_V_reg_64801 <= grp_sp_best_tracks_fu_51719_ap_return_48;
bt_delta_th_t_2_1_V_reg_64807 <= grp_sp_best_tracks_fu_51719_ap_return_49;
bt_delta_th_t_2_2_V_reg_64813 <= grp_sp_best_tracks_fu_51719_ap_return_50;
bt_delta_th_t_2_3_V_reg_64819 <= grp_sp_best_tracks_fu_51719_ap_return_51;
bt_delta_th_t_2_4_V_reg_64825 <= grp_sp_best_tracks_fu_51719_ap_return_52;
bt_delta_th_t_2_5_V_reg_64831 <= grp_sp_best_tracks_fu_51719_ap_return_53;
bt_hi_t_0_0_V_reg_64969 <= grp_sp_best_tracks_fu_51719_ap_return_78;
bt_hi_t_0_1_V_reg_64974 <= grp_sp_best_tracks_fu_51719_ap_return_79;
bt_hi_t_0_2_V_reg_64979 <= grp_sp_best_tracks_fu_51719_ap_return_80;
bt_hi_t_0_3_V_reg_64984 <= grp_sp_best_tracks_fu_51719_ap_return_81;
bt_hi_t_0_4_V_reg_64989 <= grp_sp_best_tracks_fu_51719_ap_return_82;
bt_hi_t_1_0_V_reg_64994 <= grp_sp_best_tracks_fu_51719_ap_return_83;
bt_hi_t_1_1_V_reg_64999 <= grp_sp_best_tracks_fu_51719_ap_return_84;
bt_hi_t_1_2_V_reg_65004 <= grp_sp_best_tracks_fu_51719_ap_return_85;
bt_hi_t_1_3_V_reg_65009 <= grp_sp_best_tracks_fu_51719_ap_return_86;
bt_hi_t_1_4_V_reg_65014 <= grp_sp_best_tracks_fu_51719_ap_return_87;
bt_hi_t_2_0_V_reg_65019 <= grp_sp_best_tracks_fu_51719_ap_return_88;
bt_hi_t_2_1_V_reg_65024 <= grp_sp_best_tracks_fu_51719_ap_return_89;
bt_hi_t_2_2_V_reg_65029 <= grp_sp_best_tracks_fu_51719_ap_return_90;
bt_hi_t_2_3_V_reg_65034 <= grp_sp_best_tracks_fu_51719_ap_return_91;
bt_hi_t_2_4_V_reg_65039 <= grp_sp_best_tracks_fu_51719_ap_return_92;
bt_phi_t_0_V_reg_64513 <= grp_sp_best_tracks_fu_51719_ap_return_0;
bt_phi_t_1_V_reg_64519 <= grp_sp_best_tracks_fu_51719_ap_return_1;
bt_phi_t_2_V_reg_64525 <= grp_sp_best_tracks_fu_51719_ap_return_2;
bt_rank_t_0_V_reg_64873 <= grp_sp_best_tracks_fu_51719_ap_return_60;
bt_rank_t_1_V_reg_64879 <= grp_sp_best_tracks_fu_51719_ap_return_61;
bt_rank_t_2_V_reg_64885 <= grp_sp_best_tracks_fu_51719_ap_return_62;
bt_si_t_0_V_reg_65134 <= grp_sp_best_tracks_fu_51719_ap_return_108;
bt_si_t_1_V_reg_65139 <= grp_sp_best_tracks_fu_51719_ap_return_109;
bt_si_t_2_V_reg_65144 <= grp_sp_best_tracks_fu_51719_ap_return_110;
bt_sign_ph_t_0_V_reg_64837 <= grp_sp_best_tracks_fu_51719_ap_return_54;
bt_sign_ph_t_1_V_reg_64843 <= grp_sp_best_tracks_fu_51719_ap_return_55;
bt_sign_ph_t_2_V_reg_64849 <= grp_sp_best_tracks_fu_51719_ap_return_56;
bt_sign_th_t_0_V_reg_64855 <= grp_sp_best_tracks_fu_51719_ap_return_57;
bt_sign_th_t_1_V_reg_64861 <= grp_sp_best_tracks_fu_51719_ap_return_58;
bt_sign_th_t_2_V_reg_64867 <= grp_sp_best_tracks_fu_51719_ap_return_59;
bt_theta_t_0_V_reg_64531 <= grp_sp_best_tracks_fu_51719_ap_return_3;
bt_theta_t_1_V_reg_64537 <= grp_sp_best_tracks_fu_51719_ap_return_4;
bt_theta_t_2_V_reg_64543 <= grp_sp_best_tracks_fu_51719_ap_return_5;
bt_vi_t_0_0_V_reg_64891 <= grp_sp_best_tracks_fu_51719_ap_return_63;
bt_vi_t_0_1_V_reg_64897 <= grp_sp_best_tracks_fu_51719_ap_return_64;
bt_vi_t_0_2_V_reg_64902 <= grp_sp_best_tracks_fu_51719_ap_return_65;
bt_vi_t_0_3_V_reg_64907 <= grp_sp_best_tracks_fu_51719_ap_return_66;
bt_vi_t_0_4_V_reg_64912 <= grp_sp_best_tracks_fu_51719_ap_return_67;
bt_vi_t_1_0_V_reg_64917 <= grp_sp_best_tracks_fu_51719_ap_return_68;
bt_vi_t_1_1_V_reg_64923 <= grp_sp_best_tracks_fu_51719_ap_return_69;
bt_vi_t_1_2_V_reg_64928 <= grp_sp_best_tracks_fu_51719_ap_return_70;
bt_vi_t_1_3_V_reg_64933 <= grp_sp_best_tracks_fu_51719_ap_return_71;
bt_vi_t_1_4_V_reg_64938 <= grp_sp_best_tracks_fu_51719_ap_return_72;
bt_vi_t_2_0_V_reg_64943 <= grp_sp_best_tracks_fu_51719_ap_return_73;
bt_vi_t_2_1_V_reg_64949 <= grp_sp_best_tracks_fu_51719_ap_return_74;
bt_vi_t_2_2_V_reg_64954 <= grp_sp_best_tracks_fu_51719_ap_return_75;
bt_vi_t_2_3_V_reg_64959 <= grp_sp_best_tracks_fu_51719_ap_return_76;
bt_vi_t_2_4_V_reg_64964 <= grp_sp_best_tracks_fu_51719_ap_return_77;
cpat_match_t_0_0_0_V_reg_62473 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_60;
cpat_match_t_0_0_1_V_reg_62478 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_61;
cpat_match_t_0_0_2_V_reg_62483 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_62;
cpat_match_t_0_0_3_V_reg_62488 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_63;
cpat_match_t_0_1_0_V_reg_62493 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_64;
cpat_match_t_0_1_1_V_reg_62498 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_65;
cpat_match_t_0_1_2_V_reg_62503 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_66;
cpat_match_t_0_1_3_V_reg_62508 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_67;
cpat_match_t_0_2_0_V_reg_62513 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_68;
cpat_match_t_0_2_1_V_reg_62518 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_69;
cpat_match_t_0_2_2_V_reg_62523 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_70;
cpat_match_t_0_2_3_V_reg_62528 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_71;
cpat_match_t_1_0_0_V_reg_62533 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_72;
cpat_match_t_1_0_1_V_reg_62538 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_73;
cpat_match_t_1_0_2_V_reg_62543 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_74;
cpat_match_t_1_0_3_V_reg_62548 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_75;
cpat_match_t_1_1_0_V_reg_62553 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_76;
cpat_match_t_1_1_1_V_reg_62558 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_77;
cpat_match_t_1_1_2_V_reg_62563 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_78;
cpat_match_t_1_1_3_V_reg_62568 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_79;
cpat_match_t_1_2_0_V_reg_62573 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_80;
cpat_match_t_1_2_1_V_reg_62578 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_81;
cpat_match_t_1_2_2_V_reg_62583 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_82;
cpat_match_t_1_2_3_V_reg_62588 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_83;
cpat_match_t_2_0_0_V_reg_62593 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_84;
cpat_match_t_2_0_1_V_reg_62598 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_85;
cpat_match_t_2_0_2_V_reg_62603 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_86;
cpat_match_t_2_0_3_V_reg_62608 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_87;
cpat_match_t_2_1_0_V_reg_62613 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_88;
cpat_match_t_2_1_1_V_reg_62618 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_89;
cpat_match_t_2_1_2_V_reg_62623 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_90;
cpat_match_t_2_1_3_V_reg_62628 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_91;
cpat_match_t_2_2_0_V_reg_62633 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_92;
cpat_match_t_2_2_1_V_reg_62638 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_93;
cpat_match_t_2_2_2_V_reg_62643 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_94;
cpat_match_t_2_2_3_V_reg_62648 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_95;
cpat_match_t_3_0_0_V_reg_62653 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_96;
cpat_match_t_3_0_1_V_reg_62658 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_97;
cpat_match_t_3_0_2_V_reg_62663 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_98;
cpat_match_t_3_0_3_V_reg_62668 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_99;
cpat_match_t_3_1_0_V_reg_62673 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_100;
cpat_match_t_3_1_1_V_reg_62678 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_101;
cpat_match_t_3_1_2_V_reg_62683 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_102;
cpat_match_t_3_1_3_V_reg_62688 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_103;
cpat_match_t_3_2_0_V_reg_62693 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_104;
cpat_match_t_3_2_1_V_reg_62698 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_105;
cpat_match_t_3_2_2_V_reg_62703 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_106;
cpat_match_t_3_2_3_V_reg_62708 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_107;
cpatd_1_2_1_1_V_reg_62128 <= grp_sp_co_ord_delay_fu_52775_ap_return_29;
cpatd_1_3_1_1_V_reg_62133 <= grp_sp_co_ord_delay_fu_52775_ap_return_30;
cpatd_1_4_1_1_V_reg_62138 <= grp_sp_co_ord_delay_fu_52775_ap_return_31;
cpatd_2_0_1_1_V_reg_62143 <= grp_sp_co_ord_delay_fu_52775_ap_return_32;
cpatd_2_0_4_1_V_reg_62148 <= grp_sp_co_ord_delay_fu_52775_ap_return_33;
cpatd_2_0_7_1_V_reg_62153 <= grp_sp_co_ord_delay_fu_52775_ap_return_34;
cpatd_2_2_4_1_V_reg_62158 <= grp_sp_co_ord_delay_fu_52775_ap_return_35;
cpatd_2_3_4_1_V_reg_62163 <= grp_sp_co_ord_delay_fu_52775_ap_return_36;
cpatd_2_4_4_1_V_reg_62168 <= grp_sp_co_ord_delay_fu_52775_ap_return_37;
cpattern_t_0_0_0_V_reg_63553 <= call_ret_sp_deltas_sector_fu_51987_ap_return_60;
cpattern_t_0_0_1_V_reg_63558 <= call_ret_sp_deltas_sector_fu_51987_ap_return_61;
cpattern_t_0_0_2_V_reg_63563 <= call_ret_sp_deltas_sector_fu_51987_ap_return_62;
cpattern_t_0_0_3_V_reg_63568 <= call_ret_sp_deltas_sector_fu_51987_ap_return_63;
cpattern_t_0_1_0_V_reg_63573 <= call_ret_sp_deltas_sector_fu_51987_ap_return_64;
cpattern_t_0_1_1_V_reg_63578 <= call_ret_sp_deltas_sector_fu_51987_ap_return_65;
cpattern_t_0_1_2_V_reg_63583 <= call_ret_sp_deltas_sector_fu_51987_ap_return_66;
cpattern_t_0_1_3_V_reg_63588 <= call_ret_sp_deltas_sector_fu_51987_ap_return_67;
cpattern_t_0_2_0_V_reg_63593 <= call_ret_sp_deltas_sector_fu_51987_ap_return_68;
cpattern_t_0_2_1_V_reg_63598 <= call_ret_sp_deltas_sector_fu_51987_ap_return_69;
cpattern_t_0_2_2_V_reg_63603 <= call_ret_sp_deltas_sector_fu_51987_ap_return_70;
cpattern_t_0_2_3_V_reg_63608 <= call_ret_sp_deltas_sector_fu_51987_ap_return_71;
cpattern_t_1_0_0_V_reg_63613 <= call_ret_sp_deltas_sector_fu_51987_ap_return_72;
cpattern_t_1_0_1_V_reg_63618 <= call_ret_sp_deltas_sector_fu_51987_ap_return_73;
cpattern_t_1_0_2_V_reg_63623 <= call_ret_sp_deltas_sector_fu_51987_ap_return_74;
cpattern_t_1_0_3_V_reg_63628 <= call_ret_sp_deltas_sector_fu_51987_ap_return_75;
cpattern_t_1_1_0_V_reg_63633 <= call_ret_sp_deltas_sector_fu_51987_ap_return_76;
cpattern_t_1_1_1_V_reg_63638 <= call_ret_sp_deltas_sector_fu_51987_ap_return_77;
cpattern_t_1_1_2_V_reg_63643 <= call_ret_sp_deltas_sector_fu_51987_ap_return_78;
cpattern_t_1_1_3_V_reg_63648 <= call_ret_sp_deltas_sector_fu_51987_ap_return_79;
cpattern_t_1_2_0_V_reg_63653 <= call_ret_sp_deltas_sector_fu_51987_ap_return_80;
cpattern_t_1_2_1_V_reg_63658 <= call_ret_sp_deltas_sector_fu_51987_ap_return_81;
cpattern_t_1_2_2_V_reg_63663 <= call_ret_sp_deltas_sector_fu_51987_ap_return_82;
cpattern_t_1_2_3_V_reg_63668 <= call_ret_sp_deltas_sector_fu_51987_ap_return_83;
cpattern_t_2_0_0_V_reg_63673 <= call_ret_sp_deltas_sector_fu_51987_ap_return_84;
cpattern_t_2_0_1_V_reg_63678 <= call_ret_sp_deltas_sector_fu_51987_ap_return_85;
cpattern_t_2_0_2_V_reg_63683 <= call_ret_sp_deltas_sector_fu_51987_ap_return_86;
cpattern_t_2_0_3_V_reg_63688 <= call_ret_sp_deltas_sector_fu_51987_ap_return_87;
cpattern_t_2_1_0_V_reg_63693 <= call_ret_sp_deltas_sector_fu_51987_ap_return_88;
cpattern_t_2_1_1_V_reg_63698 <= call_ret_sp_deltas_sector_fu_51987_ap_return_89;
cpattern_t_2_1_2_V_reg_63703 <= call_ret_sp_deltas_sector_fu_51987_ap_return_90;
cpattern_t_2_1_3_V_reg_63708 <= call_ret_sp_deltas_sector_fu_51987_ap_return_91;
cpattern_t_2_2_0_V_reg_63713 <= call_ret_sp_deltas_sector_fu_51987_ap_return_92;
cpattern_t_2_2_1_V_reg_63718 <= call_ret_sp_deltas_sector_fu_51987_ap_return_93;
cpattern_t_2_2_2_V_reg_63723 <= call_ret_sp_deltas_sector_fu_51987_ap_return_94;
cpattern_t_2_2_3_V_reg_63728 <= call_ret_sp_deltas_sector_fu_51987_ap_return_95;
cpattern_t_3_0_0_V_reg_63733 <= call_ret_sp_deltas_sector_fu_51987_ap_return_96;
cpattern_t_3_0_1_V_reg_63738 <= call_ret_sp_deltas_sector_fu_51987_ap_return_97;
cpattern_t_3_0_2_V_reg_63743 <= call_ret_sp_deltas_sector_fu_51987_ap_return_98;
cpattern_t_3_0_3_V_reg_63748 <= call_ret_sp_deltas_sector_fu_51987_ap_return_99;
cpattern_t_3_1_0_V_reg_63753 <= call_ret_sp_deltas_sector_fu_51987_ap_return_100;
cpattern_t_3_1_1_V_reg_63758 <= call_ret_sp_deltas_sector_fu_51987_ap_return_101;
cpattern_t_3_1_2_V_reg_63763 <= call_ret_sp_deltas_sector_fu_51987_ap_return_102;
cpattern_t_3_1_3_V_reg_63768 <= call_ret_sp_deltas_sector_fu_51987_ap_return_103;
cpattern_t_3_2_0_V_reg_63773 <= call_ret_sp_deltas_sector_fu_51987_ap_return_104;
cpattern_t_3_2_1_V_reg_63778 <= call_ret_sp_deltas_sector_fu_51987_ap_return_105;
cpattern_t_3_2_2_V_reg_63783 <= call_ret_sp_deltas_sector_fu_51987_ap_return_106;
cpattern_t_3_2_3_V_reg_63788 <= call_ret_sp_deltas_sector_fu_51987_ap_return_107;
delta_ph_t_0_0_0_V_reg_63793 <= call_ret_sp_deltas_sector_fu_51987_ap_return_108;
delta_ph_t_0_0_1_V_reg_63798 <= call_ret_sp_deltas_sector_fu_51987_ap_return_109;
delta_ph_t_0_0_2_V_reg_63803 <= call_ret_sp_deltas_sector_fu_51987_ap_return_110;
delta_ph_t_0_0_3_V_reg_63808 <= call_ret_sp_deltas_sector_fu_51987_ap_return_111;
delta_ph_t_0_0_4_V_reg_63813 <= call_ret_sp_deltas_sector_fu_51987_ap_return_112;
delta_ph_t_0_0_5_V_reg_63818 <= call_ret_sp_deltas_sector_fu_51987_ap_return_113;
delta_ph_t_0_1_0_V_reg_63823 <= call_ret_sp_deltas_sector_fu_51987_ap_return_114;
delta_ph_t_0_1_1_V_reg_63828 <= call_ret_sp_deltas_sector_fu_51987_ap_return_115;
delta_ph_t_0_1_2_V_reg_63833 <= call_ret_sp_deltas_sector_fu_51987_ap_return_116;
delta_ph_t_0_1_3_V_reg_63838 <= call_ret_sp_deltas_sector_fu_51987_ap_return_117;
delta_ph_t_0_1_4_V_reg_63843 <= call_ret_sp_deltas_sector_fu_51987_ap_return_118;
delta_ph_t_0_1_5_V_reg_63848 <= call_ret_sp_deltas_sector_fu_51987_ap_return_119;
delta_ph_t_0_2_0_V_reg_63853 <= call_ret_sp_deltas_sector_fu_51987_ap_return_120;
delta_ph_t_0_2_1_V_reg_63858 <= call_ret_sp_deltas_sector_fu_51987_ap_return_121;
delta_ph_t_0_2_2_V_reg_63863 <= call_ret_sp_deltas_sector_fu_51987_ap_return_122;
delta_ph_t_0_2_3_V_reg_63868 <= call_ret_sp_deltas_sector_fu_51987_ap_return_123;
delta_ph_t_0_2_4_V_reg_63873 <= call_ret_sp_deltas_sector_fu_51987_ap_return_124;
delta_ph_t_0_2_5_V_reg_63878 <= call_ret_sp_deltas_sector_fu_51987_ap_return_125;
delta_ph_t_1_0_0_V_reg_63883 <= call_ret_sp_deltas_sector_fu_51987_ap_return_126;
delta_ph_t_1_0_1_V_reg_63888 <= call_ret_sp_deltas_sector_fu_51987_ap_return_127;
delta_ph_t_1_0_2_V_reg_63893 <= call_ret_sp_deltas_sector_fu_51987_ap_return_128;
delta_ph_t_1_0_3_V_reg_63898 <= call_ret_sp_deltas_sector_fu_51987_ap_return_129;
delta_ph_t_1_0_4_V_reg_63903 <= call_ret_sp_deltas_sector_fu_51987_ap_return_130;
delta_ph_t_1_0_5_V_reg_63908 <= call_ret_sp_deltas_sector_fu_51987_ap_return_131;
delta_ph_t_1_1_0_V_reg_63913 <= call_ret_sp_deltas_sector_fu_51987_ap_return_132;
delta_ph_t_1_1_1_V_reg_63918 <= call_ret_sp_deltas_sector_fu_51987_ap_return_133;
delta_ph_t_1_1_2_V_reg_63923 <= call_ret_sp_deltas_sector_fu_51987_ap_return_134;
delta_ph_t_1_1_3_V_reg_63928 <= call_ret_sp_deltas_sector_fu_51987_ap_return_135;
delta_ph_t_1_1_4_V_reg_63933 <= call_ret_sp_deltas_sector_fu_51987_ap_return_136;
delta_ph_t_1_1_5_V_reg_63938 <= call_ret_sp_deltas_sector_fu_51987_ap_return_137;
delta_ph_t_1_2_0_V_reg_63943 <= call_ret_sp_deltas_sector_fu_51987_ap_return_138;
delta_ph_t_1_2_1_V_reg_63948 <= call_ret_sp_deltas_sector_fu_51987_ap_return_139;
delta_ph_t_1_2_2_V_reg_63953 <= call_ret_sp_deltas_sector_fu_51987_ap_return_140;
delta_ph_t_1_2_3_V_reg_63958 <= call_ret_sp_deltas_sector_fu_51987_ap_return_141;
delta_ph_t_1_2_4_V_reg_63963 <= call_ret_sp_deltas_sector_fu_51987_ap_return_142;
delta_ph_t_1_2_5_V_reg_63968 <= call_ret_sp_deltas_sector_fu_51987_ap_return_143;
delta_ph_t_2_0_0_V_reg_63973 <= call_ret_sp_deltas_sector_fu_51987_ap_return_144;
delta_ph_t_2_0_1_V_reg_63978 <= call_ret_sp_deltas_sector_fu_51987_ap_return_145;
delta_ph_t_2_0_2_V_reg_63983 <= call_ret_sp_deltas_sector_fu_51987_ap_return_146;
delta_ph_t_2_0_3_V_reg_63988 <= call_ret_sp_deltas_sector_fu_51987_ap_return_147;
delta_ph_t_2_0_4_V_reg_63993 <= call_ret_sp_deltas_sector_fu_51987_ap_return_148;
delta_ph_t_2_0_5_V_reg_63998 <= call_ret_sp_deltas_sector_fu_51987_ap_return_149;
delta_ph_t_2_1_0_V_reg_64003 <= call_ret_sp_deltas_sector_fu_51987_ap_return_150;
delta_ph_t_2_1_1_V_reg_64008 <= call_ret_sp_deltas_sector_fu_51987_ap_return_151;
delta_ph_t_2_1_2_V_reg_64013 <= call_ret_sp_deltas_sector_fu_51987_ap_return_152;
delta_ph_t_2_1_3_V_reg_64018 <= call_ret_sp_deltas_sector_fu_51987_ap_return_153;
delta_ph_t_2_1_4_V_reg_64023 <= call_ret_sp_deltas_sector_fu_51987_ap_return_154;
delta_ph_t_2_1_5_V_reg_64028 <= call_ret_sp_deltas_sector_fu_51987_ap_return_155;
delta_ph_t_2_2_0_V_reg_64033 <= call_ret_sp_deltas_sector_fu_51987_ap_return_156;
delta_ph_t_2_2_1_V_reg_64038 <= call_ret_sp_deltas_sector_fu_51987_ap_return_157;
delta_ph_t_2_2_2_V_reg_64043 <= call_ret_sp_deltas_sector_fu_51987_ap_return_158;
delta_ph_t_2_2_3_V_reg_64048 <= call_ret_sp_deltas_sector_fu_51987_ap_return_159;
delta_ph_t_2_2_4_V_reg_64053 <= call_ret_sp_deltas_sector_fu_51987_ap_return_160;
delta_ph_t_2_2_5_V_reg_64058 <= call_ret_sp_deltas_sector_fu_51987_ap_return_161;
delta_ph_t_3_0_0_V_reg_64063 <= call_ret_sp_deltas_sector_fu_51987_ap_return_162;
delta_ph_t_3_0_1_V_reg_64068 <= call_ret_sp_deltas_sector_fu_51987_ap_return_163;
delta_ph_t_3_0_2_V_reg_64073 <= call_ret_sp_deltas_sector_fu_51987_ap_return_164;
delta_ph_t_3_0_3_V_reg_64078 <= call_ret_sp_deltas_sector_fu_51987_ap_return_165;
delta_ph_t_3_0_4_V_reg_64083 <= call_ret_sp_deltas_sector_fu_51987_ap_return_166;
delta_ph_t_3_0_5_V_reg_64088 <= call_ret_sp_deltas_sector_fu_51987_ap_return_167;
delta_ph_t_3_1_0_V_reg_64093 <= call_ret_sp_deltas_sector_fu_51987_ap_return_168;
delta_ph_t_3_1_1_V_reg_64098 <= call_ret_sp_deltas_sector_fu_51987_ap_return_169;
delta_ph_t_3_1_2_V_reg_64103 <= call_ret_sp_deltas_sector_fu_51987_ap_return_170;
delta_ph_t_3_1_3_V_reg_64108 <= call_ret_sp_deltas_sector_fu_51987_ap_return_171;
delta_ph_t_3_1_4_V_reg_64113 <= call_ret_sp_deltas_sector_fu_51987_ap_return_172;
delta_ph_t_3_1_5_V_reg_64118 <= call_ret_sp_deltas_sector_fu_51987_ap_return_173;
delta_ph_t_3_2_0_V_reg_64123 <= call_ret_sp_deltas_sector_fu_51987_ap_return_174;
delta_ph_t_3_2_1_V_reg_64128 <= call_ret_sp_deltas_sector_fu_51987_ap_return_175;
delta_ph_t_3_2_2_V_reg_64133 <= call_ret_sp_deltas_sector_fu_51987_ap_return_176;
delta_ph_t_3_2_3_V_reg_64138 <= call_ret_sp_deltas_sector_fu_51987_ap_return_177;
delta_ph_t_3_2_4_V_reg_64143 <= call_ret_sp_deltas_sector_fu_51987_ap_return_178;
delta_ph_t_3_2_5_V_reg_64148 <= call_ret_sp_deltas_sector_fu_51987_ap_return_179;
delta_th_t_0_0_0_V_reg_64153 <= call_ret_sp_deltas_sector_fu_51987_ap_return_180;
delta_th_t_0_0_1_V_reg_64158 <= call_ret_sp_deltas_sector_fu_51987_ap_return_181;
delta_th_t_0_0_2_V_reg_64163 <= call_ret_sp_deltas_sector_fu_51987_ap_return_182;
delta_th_t_0_0_3_V_reg_64168 <= call_ret_sp_deltas_sector_fu_51987_ap_return_183;
delta_th_t_0_0_4_V_reg_64173 <= call_ret_sp_deltas_sector_fu_51987_ap_return_184;
delta_th_t_0_0_5_V_reg_64178 <= call_ret_sp_deltas_sector_fu_51987_ap_return_185;
delta_th_t_0_1_0_V_reg_64183 <= call_ret_sp_deltas_sector_fu_51987_ap_return_186;
delta_th_t_0_1_1_V_reg_64188 <= call_ret_sp_deltas_sector_fu_51987_ap_return_187;
delta_th_t_0_1_2_V_reg_64193 <= call_ret_sp_deltas_sector_fu_51987_ap_return_188;
delta_th_t_0_1_3_V_reg_64198 <= call_ret_sp_deltas_sector_fu_51987_ap_return_189;
delta_th_t_0_1_4_V_reg_64203 <= call_ret_sp_deltas_sector_fu_51987_ap_return_190;
delta_th_t_0_1_5_V_reg_64208 <= call_ret_sp_deltas_sector_fu_51987_ap_return_191;
delta_th_t_0_2_0_V_reg_64213 <= call_ret_sp_deltas_sector_fu_51987_ap_return_192;
delta_th_t_0_2_1_V_reg_64218 <= call_ret_sp_deltas_sector_fu_51987_ap_return_193;
delta_th_t_0_2_2_V_reg_64223 <= call_ret_sp_deltas_sector_fu_51987_ap_return_194;
delta_th_t_0_2_3_V_reg_64228 <= call_ret_sp_deltas_sector_fu_51987_ap_return_195;
delta_th_t_0_2_4_V_reg_64233 <= call_ret_sp_deltas_sector_fu_51987_ap_return_196;
delta_th_t_0_2_5_V_reg_64238 <= call_ret_sp_deltas_sector_fu_51987_ap_return_197;
delta_th_t_1_0_0_V_reg_64243 <= call_ret_sp_deltas_sector_fu_51987_ap_return_198;
delta_th_t_1_0_1_V_reg_64248 <= call_ret_sp_deltas_sector_fu_51987_ap_return_199;
delta_th_t_1_0_2_V_reg_64253 <= call_ret_sp_deltas_sector_fu_51987_ap_return_200;
delta_th_t_1_0_3_V_reg_64258 <= call_ret_sp_deltas_sector_fu_51987_ap_return_201;
delta_th_t_1_0_4_V_reg_64263 <= call_ret_sp_deltas_sector_fu_51987_ap_return_202;
delta_th_t_1_0_5_V_reg_64268 <= call_ret_sp_deltas_sector_fu_51987_ap_return_203;
delta_th_t_1_1_0_V_reg_64273 <= call_ret_sp_deltas_sector_fu_51987_ap_return_204;
delta_th_t_1_1_1_V_reg_64278 <= call_ret_sp_deltas_sector_fu_51987_ap_return_205;
delta_th_t_1_1_2_V_reg_64283 <= call_ret_sp_deltas_sector_fu_51987_ap_return_206;
delta_th_t_1_1_3_V_reg_64288 <= call_ret_sp_deltas_sector_fu_51987_ap_return_207;
delta_th_t_1_1_4_V_reg_64293 <= call_ret_sp_deltas_sector_fu_51987_ap_return_208;
delta_th_t_1_1_5_V_reg_64298 <= call_ret_sp_deltas_sector_fu_51987_ap_return_209;
delta_th_t_1_2_0_V_reg_64303 <= call_ret_sp_deltas_sector_fu_51987_ap_return_210;
delta_th_t_1_2_1_V_reg_64308 <= call_ret_sp_deltas_sector_fu_51987_ap_return_211;
delta_th_t_1_2_2_V_reg_64313 <= call_ret_sp_deltas_sector_fu_51987_ap_return_212;
delta_th_t_1_2_3_V_reg_64318 <= call_ret_sp_deltas_sector_fu_51987_ap_return_213;
delta_th_t_1_2_4_V_reg_64323 <= call_ret_sp_deltas_sector_fu_51987_ap_return_214;
delta_th_t_1_2_5_V_reg_64328 <= call_ret_sp_deltas_sector_fu_51987_ap_return_215;
delta_th_t_2_0_0_V_reg_64333 <= call_ret_sp_deltas_sector_fu_51987_ap_return_216;
delta_th_t_2_0_1_V_reg_64338 <= call_ret_sp_deltas_sector_fu_51987_ap_return_217;
delta_th_t_2_0_2_V_reg_64343 <= call_ret_sp_deltas_sector_fu_51987_ap_return_218;
delta_th_t_2_0_3_V_reg_64348 <= call_ret_sp_deltas_sector_fu_51987_ap_return_219;
delta_th_t_2_0_4_V_reg_64353 <= call_ret_sp_deltas_sector_fu_51987_ap_return_220;
delta_th_t_2_0_5_V_reg_64358 <= call_ret_sp_deltas_sector_fu_51987_ap_return_221;
delta_th_t_2_1_0_V_reg_64363 <= call_ret_sp_deltas_sector_fu_51987_ap_return_222;
delta_th_t_2_1_1_V_reg_64368 <= call_ret_sp_deltas_sector_fu_51987_ap_return_223;
delta_th_t_2_1_2_V_reg_64373 <= call_ret_sp_deltas_sector_fu_51987_ap_return_224;
delta_th_t_2_1_3_V_reg_64378 <= call_ret_sp_deltas_sector_fu_51987_ap_return_225;
delta_th_t_2_1_4_V_reg_64383 <= call_ret_sp_deltas_sector_fu_51987_ap_return_226;
delta_th_t_2_1_5_V_reg_64388 <= call_ret_sp_deltas_sector_fu_51987_ap_return_227;
delta_th_t_2_2_0_V_reg_64393 <= call_ret_sp_deltas_sector_fu_51987_ap_return_228;
delta_th_t_2_2_1_V_reg_64398 <= call_ret_sp_deltas_sector_fu_51987_ap_return_229;
delta_th_t_2_2_2_V_reg_64403 <= call_ret_sp_deltas_sector_fu_51987_ap_return_230;
delta_th_t_2_2_3_V_reg_64408 <= call_ret_sp_deltas_sector_fu_51987_ap_return_231;
delta_th_t_2_2_4_V_reg_64413 <= call_ret_sp_deltas_sector_fu_51987_ap_return_232;
delta_th_t_2_2_5_V_reg_64418 <= call_ret_sp_deltas_sector_fu_51987_ap_return_233;
delta_th_t_3_0_0_V_reg_64423 <= call_ret_sp_deltas_sector_fu_51987_ap_return_234;
delta_th_t_3_0_1_V_reg_64428 <= call_ret_sp_deltas_sector_fu_51987_ap_return_235;
delta_th_t_3_0_2_V_reg_64433 <= call_ret_sp_deltas_sector_fu_51987_ap_return_236;
delta_th_t_3_0_3_V_reg_64438 <= call_ret_sp_deltas_sector_fu_51987_ap_return_237;
delta_th_t_3_0_4_V_reg_64443 <= call_ret_sp_deltas_sector_fu_51987_ap_return_238;
delta_th_t_3_0_5_V_reg_64448 <= call_ret_sp_deltas_sector_fu_51987_ap_return_239;
delta_th_t_3_1_0_V_reg_64453 <= call_ret_sp_deltas_sector_fu_51987_ap_return_240;
delta_th_t_3_1_1_V_reg_64458 <= call_ret_sp_deltas_sector_fu_51987_ap_return_241;
delta_th_t_3_1_2_V_reg_64463 <= call_ret_sp_deltas_sector_fu_51987_ap_return_242;
delta_th_t_3_1_3_V_reg_64468 <= call_ret_sp_deltas_sector_fu_51987_ap_return_243;
delta_th_t_3_1_4_V_reg_64473 <= call_ret_sp_deltas_sector_fu_51987_ap_return_244;
delta_th_t_3_1_5_V_reg_64478 <= call_ret_sp_deltas_sector_fu_51987_ap_return_245;
delta_th_t_3_2_0_V_reg_64483 <= call_ret_sp_deltas_sector_fu_51987_ap_return_246;
delta_th_t_3_2_1_V_reg_64488 <= call_ret_sp_deltas_sector_fu_51987_ap_return_247;
delta_th_t_3_2_2_V_reg_64493 <= call_ret_sp_deltas_sector_fu_51987_ap_return_248;
delta_th_t_3_2_3_V_reg_64498 <= call_ret_sp_deltas_sector_fu_51987_ap_return_249;
delta_th_t_3_2_4_V_reg_64503 <= call_ret_sp_deltas_sector_fu_51987_ap_return_250;
delta_th_t_3_2_5_V_reg_64508 <= call_ret_sp_deltas_sector_fu_51987_ap_return_251;
patt_ph_si_0_0_V_reg_62173 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_0;
patt_ph_si_0_1_V_reg_62178 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_1;
patt_ph_si_0_2_V_reg_62183 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_2;
patt_ph_si_1_0_V_reg_62188 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_3;
patt_ph_si_1_1_V_reg_62193 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_4;
patt_ph_si_1_2_V_reg_62198 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_5;
patt_ph_si_2_0_V_reg_62203 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_6;
patt_ph_si_2_1_V_reg_62208 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_7;
patt_ph_si_2_2_V_reg_62213 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_8;
patt_ph_si_3_0_V_reg_62218 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_9;
patt_ph_si_3_1_V_reg_62223 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_10;
patt_ph_si_3_2_V_reg_62228 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_11;
ph_match_t_0_0_0_V_reg_62233 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_12;
ph_match_t_0_0_1_V_reg_62238 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_13;
ph_match_t_0_0_2_V_reg_62243 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_14;
ph_match_t_0_0_3_V_reg_62248 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_15;
ph_match_t_0_1_0_V_reg_62253 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_16;
ph_match_t_0_1_1_V_reg_62258 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_17;
ph_match_t_0_1_2_V_reg_62263 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_18;
ph_match_t_0_1_3_V_reg_62268 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_19;
ph_match_t_0_2_0_V_reg_62273 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_20;
ph_match_t_0_2_1_V_reg_62278 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_21;
ph_match_t_0_2_2_V_reg_62283 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_22;
ph_match_t_0_2_3_V_reg_62288 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_23;
ph_match_t_1_0_0_V_reg_62293 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_24;
ph_match_t_1_0_1_V_reg_62298 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_25;
ph_match_t_1_0_2_V_reg_62303 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_26;
ph_match_t_1_0_3_V_reg_62308 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_27;
ph_match_t_1_1_0_V_reg_62313 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_28;
ph_match_t_1_1_1_V_reg_62318 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_29;
ph_match_t_1_1_2_V_reg_62323 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_30;
ph_match_t_1_1_3_V_reg_62328 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_31;
ph_match_t_1_2_0_V_reg_62333 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_32;
ph_match_t_1_2_1_V_reg_62338 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_33;
ph_match_t_1_2_2_V_reg_62343 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_34;
ph_match_t_1_2_3_V_reg_62348 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_35;
ph_match_t_2_0_0_V_reg_62353 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_36;
ph_match_t_2_0_1_V_reg_62358 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_37;
ph_match_t_2_0_2_V_reg_62363 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_38;
ph_match_t_2_0_3_V_reg_62368 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_39;
ph_match_t_2_1_0_V_reg_62373 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_40;
ph_match_t_2_1_1_V_reg_62378 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_41;
ph_match_t_2_1_2_V_reg_62383 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_42;
ph_match_t_2_1_3_V_reg_62388 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_43;
ph_match_t_2_2_0_V_reg_62393 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_44;
ph_match_t_2_2_1_V_reg_62398 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_45;
ph_match_t_2_2_2_V_reg_62403 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_46;
ph_match_t_2_2_3_V_reg_62408 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_47;
ph_match_t_3_0_0_V_reg_62413 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_48;
ph_match_t_3_0_1_V_reg_62418 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_49;
ph_match_t_3_0_2_V_reg_62423 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_50;
ph_match_t_3_0_3_V_reg_62428 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_51;
ph_match_t_3_1_0_V_reg_62433 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_52;
ph_match_t_3_1_1_V_reg_62438 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_53;
ph_match_t_3_1_2_V_reg_62443 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_54;
ph_match_t_3_1_3_V_reg_62448 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_55;
ph_match_t_3_2_0_V_reg_62453 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_56;
ph_match_t_3_2_1_V_reg_62458 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_57;
ph_match_t_3_2_2_V_reg_62463 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_58;
ph_match_t_3_2_3_V_reg_62468 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_59;
phd_1_2_1_1_V_reg_61983 <= grp_sp_co_ord_delay_fu_52775_ap_return_0;
phd_1_3_1_1_V_reg_61988 <= grp_sp_co_ord_delay_fu_52775_ap_return_1;
phd_1_4_1_1_V_reg_61993 <= grp_sp_co_ord_delay_fu_52775_ap_return_2;
phd_2_0_1_1_V_reg_61998 <= grp_sp_co_ord_delay_fu_52775_ap_return_3;
phd_2_0_4_1_V_reg_62003 <= grp_sp_co_ord_delay_fu_52775_ap_return_4;
phd_2_0_7_1_V_reg_62008 <= grp_sp_co_ord_delay_fu_52775_ap_return_5;
phd_2_2_4_1_V_reg_62013 <= grp_sp_co_ord_delay_fu_52775_ap_return_6;
phd_2_3_4_1_V_reg_62018 <= grp_sp_co_ord_delay_fu_52775_ap_return_7;
phd_2_4_4_1_V_reg_62023 <= grp_sp_co_ord_delay_fu_52775_ap_return_8;
phi_t_0_0_V_reg_63253 <= call_ret_sp_deltas_sector_fu_51987_ap_return_0;
phi_t_0_1_V_reg_63258 <= call_ret_sp_deltas_sector_fu_51987_ap_return_1;
phi_t_0_2_V_reg_63263 <= call_ret_sp_deltas_sector_fu_51987_ap_return_2;
phi_t_1_0_V_reg_63268 <= call_ret_sp_deltas_sector_fu_51987_ap_return_3;
phi_t_1_1_V_reg_63273 <= call_ret_sp_deltas_sector_fu_51987_ap_return_4;
phi_t_1_2_V_reg_63278 <= call_ret_sp_deltas_sector_fu_51987_ap_return_5;
phi_t_2_0_V_reg_63283 <= call_ret_sp_deltas_sector_fu_51987_ap_return_6;
phi_t_2_1_V_reg_63288 <= call_ret_sp_deltas_sector_fu_51987_ap_return_7;
phi_t_2_2_V_reg_63293 <= call_ret_sp_deltas_sector_fu_51987_ap_return_8;
phi_t_3_0_V_reg_63298 <= call_ret_sp_deltas_sector_fu_51987_ap_return_9;
phi_t_3_1_V_reg_63303 <= call_ret_sp_deltas_sector_fu_51987_ap_return_10;
phi_t_3_2_V_reg_63308 <= call_ret_sp_deltas_sector_fu_51987_ap_return_11;
rank_t_0_0_V_reg_63493 <= call_ret_sp_deltas_sector_fu_51987_ap_return_48;
rank_t_0_1_V_reg_63498 <= call_ret_sp_deltas_sector_fu_51987_ap_return_49;
rank_t_0_2_V_reg_63503 <= call_ret_sp_deltas_sector_fu_51987_ap_return_50;
rank_t_1_0_V_reg_63508 <= call_ret_sp_deltas_sector_fu_51987_ap_return_51;
rank_t_1_1_V_reg_63513 <= call_ret_sp_deltas_sector_fu_51987_ap_return_52;
rank_t_1_2_V_reg_63518 <= call_ret_sp_deltas_sector_fu_51987_ap_return_53;
rank_t_2_0_V_reg_63523 <= call_ret_sp_deltas_sector_fu_51987_ap_return_54;
rank_t_2_1_V_reg_63528 <= call_ret_sp_deltas_sector_fu_51987_ap_return_55;
rank_t_2_2_V_reg_63533 <= call_ret_sp_deltas_sector_fu_51987_ap_return_56;
rank_t_3_0_V_reg_63538 <= call_ret_sp_deltas_sector_fu_51987_ap_return_57;
rank_t_3_1_V_reg_63543 <= call_ret_sp_deltas_sector_fu_51987_ap_return_58;
rank_t_3_2_V_reg_63548 <= call_ret_sp_deltas_sector_fu_51987_ap_return_59;
sign_ph_t_0_0_V_reg_63373 <= call_ret_sp_deltas_sector_fu_51987_ap_return_24;
sign_ph_t_0_1_V_reg_63378 <= call_ret_sp_deltas_sector_fu_51987_ap_return_25;
sign_ph_t_0_2_V_reg_63383 <= call_ret_sp_deltas_sector_fu_51987_ap_return_26;
sign_ph_t_1_0_V_reg_63388 <= call_ret_sp_deltas_sector_fu_51987_ap_return_27;
sign_ph_t_1_1_V_reg_63393 <= call_ret_sp_deltas_sector_fu_51987_ap_return_28;
sign_ph_t_1_2_V_reg_63398 <= call_ret_sp_deltas_sector_fu_51987_ap_return_29;
sign_ph_t_2_0_V_reg_63403 <= call_ret_sp_deltas_sector_fu_51987_ap_return_30;
sign_ph_t_2_1_V_reg_63408 <= call_ret_sp_deltas_sector_fu_51987_ap_return_31;
sign_ph_t_2_2_V_reg_63413 <= call_ret_sp_deltas_sector_fu_51987_ap_return_32;
sign_ph_t_3_0_V_reg_63418 <= call_ret_sp_deltas_sector_fu_51987_ap_return_33;
sign_ph_t_3_1_V_reg_63423 <= call_ret_sp_deltas_sector_fu_51987_ap_return_34;
sign_ph_t_3_2_V_reg_63428 <= call_ret_sp_deltas_sector_fu_51987_ap_return_35;
sign_th_t_0_0_V_reg_63433 <= call_ret_sp_deltas_sector_fu_51987_ap_return_36;
sign_th_t_0_1_V_reg_63438 <= call_ret_sp_deltas_sector_fu_51987_ap_return_37;
sign_th_t_0_2_V_reg_63443 <= call_ret_sp_deltas_sector_fu_51987_ap_return_38;
sign_th_t_1_0_V_reg_63448 <= call_ret_sp_deltas_sector_fu_51987_ap_return_39;
sign_th_t_1_1_V_reg_63453 <= call_ret_sp_deltas_sector_fu_51987_ap_return_40;
sign_th_t_1_2_V_reg_63458 <= call_ret_sp_deltas_sector_fu_51987_ap_return_41;
sign_th_t_2_0_V_reg_63463 <= call_ret_sp_deltas_sector_fu_51987_ap_return_42;
sign_th_t_2_1_V_reg_63468 <= call_ret_sp_deltas_sector_fu_51987_ap_return_43;
sign_th_t_2_2_V_reg_63473 <= call_ret_sp_deltas_sector_fu_51987_ap_return_44;
sign_th_t_3_0_V_reg_63478 <= call_ret_sp_deltas_sector_fu_51987_ap_return_45;
sign_th_t_3_1_V_reg_63483 <= call_ret_sp_deltas_sector_fu_51987_ap_return_46;
sign_th_t_3_2_V_reg_63488 <= call_ret_sp_deltas_sector_fu_51987_ap_return_47;
th11d_2_0_1_0_V_reg_62028 <= grp_sp_co_ord_delay_fu_52775_ap_return_9;
th11d_2_0_1_1_V_reg_62033 <= grp_sp_co_ord_delay_fu_52775_ap_return_10;
th11d_2_0_1_2_V_reg_62038 <= grp_sp_co_ord_delay_fu_52775_ap_return_11;
th11d_2_0_1_3_V_reg_62043 <= grp_sp_co_ord_delay_fu_52775_ap_return_12;
th_match11_t_0_0_0_V_reg_63133 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_192;
th_match11_t_0_0_1_V_reg_63138 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_193;
th_match11_t_0_0_2_V_reg_63143 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_194;
th_match11_t_0_0_3_V_reg_63148 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_195;
th_match11_t_0_1_0_V_reg_63153 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_196;
th_match11_t_0_1_1_V_reg_63158 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_197;
th_match11_t_0_1_2_V_reg_63163 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_198;
th_match11_t_0_1_3_V_reg_63168 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_199;
th_match11_t_0_2_0_V_reg_63173 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_200;
th_match11_t_0_2_1_V_reg_63178 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_201;
th_match11_t_0_2_2_V_reg_63183 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_202;
th_match11_t_0_2_3_V_reg_63188 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_203;
th_match11_t_1_0_0_V_reg_63193 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_204;
th_match11_t_1_0_1_V_reg_63198 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_205;
th_match11_t_1_0_2_V_reg_63203 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_206;
th_match11_t_1_0_3_V_reg_63208 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_207;
th_match11_t_1_1_0_V_reg_63213 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_208;
th_match11_t_1_1_1_V_reg_63218 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_209;
th_match11_t_1_1_2_V_reg_63223 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_210;
th_match11_t_1_1_3_V_reg_63228 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_211;
th_match11_t_1_2_0_V_reg_63233 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_212;
th_match11_t_1_2_1_V_reg_63238 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_213;
th_match11_t_1_2_2_V_reg_63243 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_214;
th_match11_t_1_2_3_V_reg_63248 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_215;
th_match_t1_0_0_1_0_V_reg_62713 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_108;
th_match_t1_0_0_1_1_V_reg_62718 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_109;
th_match_t1_0_0_2_0_V_reg_62723 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_110;
th_match_t1_0_0_2_1_V_reg_62728 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_111;
th_match_t1_0_0_3_0_V_reg_62733 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_112;
th_match_t1_0_0_3_1_V_reg_62738 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_113;
th_match_t1_0_1_1_0_V_reg_62743 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_114;
th_match_t1_0_1_1_1_V_reg_62748 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_115;
th_match_t1_0_1_2_0_V_reg_62753 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_116;
th_match_t1_0_1_2_1_V_reg_62758 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_117;
th_match_t1_0_1_3_0_V_reg_62763 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_118;
th_match_t1_0_1_3_1_V_reg_62768 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_119;
th_match_t1_0_2_1_0_V_reg_62773 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_120;
th_match_t1_0_2_1_1_V_reg_62778 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_121;
th_match_t1_0_2_2_0_V_reg_62783 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_122;
th_match_t1_0_2_2_1_V_reg_62788 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_123;
th_match_t1_0_2_3_0_V_reg_62793 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_124;
th_match_t1_0_2_3_1_V_reg_62798 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_125;
th_match_t1_1_0_1_0_V_reg_62803 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_126;
th_match_t1_1_0_1_1_V_reg_62808 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_127;
th_match_t1_1_0_2_0_V_reg_62813 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_128;
th_match_t1_1_0_2_1_V_reg_62818 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_129;
th_match_t1_1_0_3_0_V_reg_62823 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_130;
th_match_t1_1_0_3_1_V_reg_62828 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_131;
th_match_t1_1_1_1_0_V_reg_62833 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_132;
th_match_t1_1_1_1_1_V_reg_62838 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_133;
th_match_t1_1_1_2_0_V_reg_62843 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_134;
th_match_t1_1_1_2_1_V_reg_62848 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_135;
th_match_t1_1_1_3_0_V_reg_62853 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_136;
th_match_t1_1_1_3_1_V_reg_62858 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_137;
th_match_t1_1_2_1_0_V_reg_62863 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_138;
th_match_t1_1_2_1_1_V_reg_62868 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_139;
th_match_t1_1_2_2_0_V_reg_62873 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_140;
th_match_t1_1_2_2_1_V_reg_62878 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_141;
th_match_t1_1_2_3_0_V_reg_62883 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_142;
th_match_t1_1_2_3_1_V_reg_62888 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_143;
th_match_t1_2_0_0_0_V_reg_62893 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_144;
th_match_t1_2_0_0_1_V_reg_62898 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_145;
th_match_t1_2_0_1_0_V_reg_62903 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_146;
th_match_t1_2_0_1_1_V_reg_62908 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_147;
th_match_t1_2_0_2_0_V_reg_62913 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_148;
th_match_t1_2_0_2_1_V_reg_62918 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_149;
th_match_t1_2_0_3_0_V_reg_62923 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_150;
th_match_t1_2_0_3_1_V_reg_62928 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_151;
th_match_t1_2_1_0_0_V_reg_62933 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_152;
th_match_t1_2_1_0_1_V_reg_62938 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_153;
th_match_t1_2_1_1_0_V_reg_62943 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_154;
th_match_t1_2_1_1_1_V_reg_62948 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_155;
th_match_t1_2_1_2_0_V_reg_62953 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_156;
th_match_t1_2_1_2_1_V_reg_62958 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_157;
th_match_t1_2_1_3_0_V_reg_62963 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_158;
th_match_t1_2_1_3_1_V_reg_62968 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_159;
th_match_t1_2_2_0_0_V_reg_62973 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_160;
th_match_t1_2_2_0_1_V_reg_62978 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_161;
th_match_t1_2_2_1_0_V_reg_62983 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_162;
th_match_t1_2_2_1_1_V_reg_62988 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_163;
th_match_t1_2_2_2_0_V_reg_62993 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_164;
th_match_t1_2_2_2_1_V_reg_62998 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_165;
th_match_t1_2_2_3_0_V_reg_63003 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_166;
th_match_t1_2_2_3_1_V_reg_63008 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_167;
th_match_t1_3_0_0_0_V_reg_63013 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_168;
th_match_t1_3_0_0_1_V_reg_63018 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_169;
th_match_t1_3_0_1_0_V_reg_63023 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_170;
th_match_t1_3_0_1_1_V_reg_63028 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_171;
th_match_t1_3_0_2_0_V_reg_63033 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_172;
th_match_t1_3_0_2_1_V_reg_63038 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_173;
th_match_t1_3_0_3_0_V_reg_63043 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_174;
th_match_t1_3_0_3_1_V_reg_63048 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_175;
th_match_t1_3_1_0_0_V_reg_63053 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_176;
th_match_t1_3_1_0_1_V_reg_63058 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_177;
th_match_t1_3_1_1_0_V_reg_63063 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_178;
th_match_t1_3_1_1_1_V_reg_63068 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_179;
th_match_t1_3_1_2_0_V_reg_63073 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_180;
th_match_t1_3_1_2_1_V_reg_63078 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_181;
th_match_t1_3_1_3_0_V_reg_63083 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_182;
th_match_t1_3_1_3_1_V_reg_63088 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_183;
th_match_t1_3_2_0_0_V_reg_63093 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_184;
th_match_t1_3_2_0_1_V_reg_63098 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_185;
th_match_t1_3_2_1_0_V_reg_63103 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_186;
th_match_t1_3_2_1_1_V_reg_63108 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_187;
th_match_t1_3_2_2_0_V_reg_63113 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_188;
th_match_t1_3_2_2_1_V_reg_63118 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_189;
th_match_t1_3_2_3_0_V_reg_63123 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_190;
th_match_t1_3_2_3_1_V_reg_63128 <= call_ret1_sp_match_ph_seg_fu_54225_ap_return_191;
thd_1_2_1_0_V_reg_62048 <= grp_sp_co_ord_delay_fu_52775_ap_return_13;
thd_1_2_1_1_V_reg_62053 <= grp_sp_co_ord_delay_fu_52775_ap_return_14;
thd_1_3_1_0_V_reg_62058 <= grp_sp_co_ord_delay_fu_52775_ap_return_15;
thd_1_3_1_1_V_reg_62063 <= grp_sp_co_ord_delay_fu_52775_ap_return_16;
thd_1_4_1_0_V_reg_62068 <= grp_sp_co_ord_delay_fu_52775_ap_return_17;
thd_1_4_1_1_V_reg_62073 <= grp_sp_co_ord_delay_fu_52775_ap_return_18;
thd_2_0_4_0_V_reg_62078 <= grp_sp_co_ord_delay_fu_52775_ap_return_19;
thd_2_0_4_1_V_reg_62083 <= grp_sp_co_ord_delay_fu_52775_ap_return_20;
thd_2_0_7_0_V_reg_62088 <= grp_sp_co_ord_delay_fu_52775_ap_return_21;
thd_2_0_7_1_V_reg_62093 <= grp_sp_co_ord_delay_fu_52775_ap_return_22;
thd_2_2_4_0_V_reg_62098 <= grp_sp_co_ord_delay_fu_52775_ap_return_23;
thd_2_2_4_1_V_reg_62103 <= grp_sp_co_ord_delay_fu_52775_ap_return_24;
thd_2_3_4_0_V_reg_62108 <= grp_sp_co_ord_delay_fu_52775_ap_return_25;
thd_2_3_4_1_V_reg_62113 <= grp_sp_co_ord_delay_fu_52775_ap_return_26;
thd_2_4_4_0_V_reg_62118 <= grp_sp_co_ord_delay_fu_52775_ap_return_27;
thd_2_4_4_1_V_reg_62123 <= grp_sp_co_ord_delay_fu_52775_ap_return_28;
theta_t_0_0_V_reg_63313 <= call_ret_sp_deltas_sector_fu_51987_ap_return_12;
theta_t_0_1_V_reg_63318 <= call_ret_sp_deltas_sector_fu_51987_ap_return_13;
theta_t_0_2_V_reg_63323 <= call_ret_sp_deltas_sector_fu_51987_ap_return_14;
theta_t_1_0_V_reg_63328 <= call_ret_sp_deltas_sector_fu_51987_ap_return_15;
theta_t_1_1_V_reg_63333 <= call_ret_sp_deltas_sector_fu_51987_ap_return_16;
theta_t_1_2_V_reg_63338 <= call_ret_sp_deltas_sector_fu_51987_ap_return_17;
theta_t_2_0_V_reg_63343 <= call_ret_sp_deltas_sector_fu_51987_ap_return_18;
theta_t_2_1_V_reg_63348 <= call_ret_sp_deltas_sector_fu_51987_ap_return_19;
theta_t_2_2_V_reg_63353 <= call_ret_sp_deltas_sector_fu_51987_ap_return_20;
theta_t_3_0_V_reg_63358 <= call_ret_sp_deltas_sector_fu_51987_ap_return_21;
theta_t_3_1_V_reg_63363 <= call_ret_sp_deltas_sector_fu_51987_ap_return_22;
theta_t_3_2_V_reg_63368 <= call_ret_sp_deltas_sector_fu_51987_ap_return_23;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == ap_reg_ppiten_pp0_it2)) begin
ph_ext_t_0_0_V_fu_24918 <= call_ret7_sp_extend_sector_fu_54039_ap_return_0;
ph_ext_t_0_1_V_fu_24922 <= call_ret7_sp_extend_sector_fu_54039_ap_return_1;
ph_ext_t_0_2_V_fu_24926 <= call_ret7_sp_extend_sector_fu_54039_ap_return_2;
ph_ext_t_0_3_V_fu_24930 <= call_ret7_sp_extend_sector_fu_54039_ap_return_3;
ph_ext_t_0_4_V_fu_24934 <= call_ret7_sp_extend_sector_fu_54039_ap_return_4;
ph_ext_t_1_0_V_fu_24938 <= call_ret7_sp_extend_sector_fu_54039_ap_return_5;
ph_ext_t_1_1_V_fu_24942 <= call_ret7_sp_extend_sector_fu_54039_ap_return_6;
ph_ext_t_1_2_V_fu_24946 <= call_ret7_sp_extend_sector_fu_54039_ap_return_7;
ph_ext_t_1_3_V_fu_24950 <= call_ret7_sp_extend_sector_fu_54039_ap_return_8;
ph_ext_t_1_4_V_fu_24954 <= call_ret7_sp_extend_sector_fu_54039_ap_return_9;
ph_ext_t_2_0_V_fu_24958 <= call_ret7_sp_extend_sector_fu_54039_ap_return_10;
ph_ext_t_2_1_V_fu_24962 <= call_ret7_sp_extend_sector_fu_54039_ap_return_11;
ph_ext_t_2_2_V_fu_24966 <= call_ret7_sp_extend_sector_fu_54039_ap_return_12;
ph_ext_t_2_3_V_fu_24970 <= call_ret7_sp_extend_sector_fu_54039_ap_return_13;
ph_ext_t_2_4_V_fu_24974 <= call_ret7_sp_extend_sector_fu_54039_ap_return_14;
ph_ext_t_3_0_V_fu_24978 <= call_ret7_sp_extend_sector_fu_54039_ap_return_15;
ph_ext_t_3_1_V_fu_24982 <= call_ret7_sp_extend_sector_fu_54039_ap_return_16;
ph_ext_t_3_2_V_fu_24986 <= call_ret7_sp_extend_sector_fu_54039_ap_return_17;
ph_ext_t_3_3_V_fu_24990 <= call_ret7_sp_extend_sector_fu_54039_ap_return_18;
ph_ext_t_3_4_V_fu_24994 <= call_ret7_sp_extend_sector_fu_54039_ap_return_19;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == ap_sig_cseq_ST_pp0_stg0_fsm_0)) begin
ph_hit_t_0_0_V_reg_61878 <= call_ret4_sp_prim_conv_sector_fu_37378_ap_return_78;
ph_hit_t_0_1_V_reg_61883 <= call_ret4_sp_prim_conv_sector_fu_37378_ap_return_79;
ph_hit_t_0_2_V_reg_61888 <= call_ret4_sp_prim_conv_sector_fu_37378_ap_return_80;
ph_hit_t_0_3_V_reg_61653 <= call_ret4_sp_prim_conv_sector_fu_37378_ap_return_33;
ph_hit_t_0_4_V_reg_61658 <= call_ret4_sp_prim_conv_sector_fu_37378_ap_return_34;
ph_hit_t_0_5_V_reg_61663 <= call_ret4_sp_prim_conv_sector_fu_37378_ap_return_35;
ph_hit_t_0_6_V_reg_61668 <= call_ret4_sp_prim_conv_sector_fu_37378_ap_return_36;
ph_hit_t_0_7_V_reg_61673 <= call_ret4_sp_prim_conv_sector_fu_37378_ap_return_37;
ph_hit_t_0_8_V_reg_61678 <= call_ret4_sp_prim_conv_sector_fu_37378_ap_return_38;
ph_hit_t_1_0_V_reg_61893 <= call_ret4_sp_prim_conv_sector_fu_37378_ap_return_81;
ph_hit_t_1_1_V_reg_61898 <= call_ret4_sp_prim_conv_sector_fu_37378_ap_return_82;
ph_hit_t_1_2_V_reg_61903 <= call_ret4_sp_prim_conv_sector_fu_37378_ap_return_83;
ph_hit_t_1_3_V_reg_61683 <= call_ret4_sp_prim_conv_sector_fu_37378_ap_return_39;
ph_hit_t_1_4_V_reg_61688 <= call_ret4_sp_prim_conv_sector_fu_37378_ap_return_40;
ph_hit_t_1_5_V_reg_61693 <= call_ret4_sp_prim_conv_sector_fu_37378_ap_return_41;
ph_hit_t_1_6_V_reg_61698 <= call_ret4_sp_prim_conv_sector_fu_37378_ap_return_42;
ph_hit_t_1_7_V_reg_61703 <= call_ret4_sp_prim_conv_sector_fu_37378_ap_return_43;
ph_hit_t_1_8_V_reg_61708 <= call_ret4_sp_prim_conv_sector_fu_37378_ap_return_44;
ph_hit_t_2_0_V_reg_61713 <= call_ret4_sp_prim_conv_sector_fu_37378_ap_return_45;
ph_hit_t_2_1_V_reg_61718 <= call_ret4_sp_prim_conv_sector_fu_37378_ap_return_46;
ph_hit_t_2_2_V_reg_61723 <= call_ret4_sp_prim_conv_sector_fu_37378_ap_return_47;
ph_hit_t_2_3_V_reg_61728 <= call_ret4_sp_prim_conv_sector_fu_37378_ap_return_48;
ph_hit_t_2_4_V_reg_61733 <= call_ret4_sp_prim_conv_sector_fu_37378_ap_return_49;
ph_hit_t_2_5_V_reg_61738 <= call_ret4_sp_prim_conv_sector_fu_37378_ap_return_50;
ph_hit_t_2_6_V_reg_61743 <= call_ret4_sp_prim_conv_sector_fu_37378_ap_return_51;
ph_hit_t_2_7_V_reg_61748 <= call_ret4_sp_prim_conv_sector_fu_37378_ap_return_52;
ph_hit_t_2_8_V_reg_61753 <= call_ret4_sp_prim_conv_sector_fu_37378_ap_return_53;
ph_hit_t_3_0_V_reg_61758 <= call_ret4_sp_prim_conv_sector_fu_37378_ap_return_54;
ph_hit_t_3_1_V_reg_61763 <= call_ret4_sp_prim_conv_sector_fu_37378_ap_return_55;
ph_hit_t_3_2_V_reg_61768 <= call_ret4_sp_prim_conv_sector_fu_37378_ap_return_56;
ph_hit_t_3_3_V_reg_61773 <= call_ret4_sp_prim_conv_sector_fu_37378_ap_return_57;
ph_hit_t_3_4_V_reg_61778 <= call_ret4_sp_prim_conv_sector_fu_37378_ap_return_58;
ph_hit_t_3_5_V_reg_61783 <= call_ret4_sp_prim_conv_sector_fu_37378_ap_return_59;
ph_hit_t_3_6_V_reg_61788 <= call_ret4_sp_prim_conv_sector_fu_37378_ap_return_60;
ph_hit_t_3_7_V_reg_61793 <= call_ret4_sp_prim_conv_sector_fu_37378_ap_return_61;
ph_hit_t_3_8_V_reg_61798 <= call_ret4_sp_prim_conv_sector_fu_37378_ap_return_62;
ph_hit_t_4_0_V_reg_61803 <= call_ret4_sp_prim_conv_sector_fu_37378_ap_return_63;
ph_hit_t_4_1_V_reg_61808 <= call_ret4_sp_prim_conv_sector_fu_37378_ap_return_64;
ph_hit_t_4_2_V_reg_61813 <= call_ret4_sp_prim_conv_sector_fu_37378_ap_return_65;
ph_hit_t_4_3_V_reg_61818 <= call_ret4_sp_prim_conv_sector_fu_37378_ap_return_66;
ph_hit_t_4_4_V_reg_61823 <= call_ret4_sp_prim_conv_sector_fu_37378_ap_return_67;
ph_hit_t_4_5_V_reg_61828 <= call_ret4_sp_prim_conv_sector_fu_37378_ap_return_68;
ph_hit_t_4_6_V_reg_61833 <= call_ret4_sp_prim_conv_sector_fu_37378_ap_return_69;
ph_hit_t_4_7_V_reg_61838 <= call_ret4_sp_prim_conv_sector_fu_37378_ap_return_70;
ph_hit_t_4_8_V_reg_61843 <= call_ret4_sp_prim_conv_sector_fu_37378_ap_return_71;
ph_zone_t_0_1_V_1_reg_61908 <= call_ret6_sp_zones_fu_52687_ap_return_0;
ph_zone_t_0_2_V_1_reg_61913 <= call_ret6_sp_zones_fu_52687_ap_return_1;
ph_zone_t_0_3_V_1_reg_61918 <= call_ret6_sp_zones_fu_52687_ap_return_2;
ph_zone_t_0_4_V_1_reg_61923 <= call_ret6_sp_zones_fu_52687_ap_return_3;
ph_zone_t_1_1_V_1_reg_61928 <= call_ret6_sp_zones_fu_52687_ap_return_4;
ph_zone_t_1_2_V_1_reg_61933 <= call_ret6_sp_zones_fu_52687_ap_return_5;
ph_zone_t_1_3_V_1_reg_61938 <= call_ret6_sp_zones_fu_52687_ap_return_6;
ph_zone_t_1_4_V_1_reg_61943 <= call_ret6_sp_zones_fu_52687_ap_return_7;
ph_zone_t_2_1_V_1_reg_61948 <= call_ret6_sp_zones_fu_52687_ap_return_8;
ph_zone_t_2_2_V_1_reg_61953 <= call_ret6_sp_zones_fu_52687_ap_return_9;
ph_zone_t_2_3_V_1_reg_61958 <= call_ret6_sp_zones_fu_52687_ap_return_10;
ph_zone_t_2_4_V_1_reg_61963 <= call_ret6_sp_zones_fu_52687_ap_return_11;
ph_zone_t_3_1_V_1_reg_61968 <= call_ret6_sp_zones_fu_52687_ap_return_12;
ph_zone_t_3_2_V_1_reg_61973 <= call_ret6_sp_zones_fu_52687_ap_return_13;
ph_zone_t_3_3_V_1_reg_61978 <= call_ret6_sp_zones_fu_52687_ap_return_14;
phzvl_t_0_0_V_reg_61848 <= call_ret4_sp_prim_conv_sector_fu_37378_ap_return_72;
phzvl_t_0_1_V_reg_61853 <= call_ret4_sp_prim_conv_sector_fu_37378_ap_return_73;
phzvl_t_0_2_V_reg_61858 <= call_ret4_sp_prim_conv_sector_fu_37378_ap_return_74;
phzvl_t_0_3_V_reg_61488 <= call_ret4_sp_prim_conv_sector_fu_37378_ap_return_0;
phzvl_t_0_4_V_reg_61493 <= call_ret4_sp_prim_conv_sector_fu_37378_ap_return_1;
phzvl_t_0_5_V_reg_61498 <= call_ret4_sp_prim_conv_sector_fu_37378_ap_return_2;
phzvl_t_1_0_V_reg_61863 <= call_ret4_sp_prim_conv_sector_fu_37378_ap_return_75;
phzvl_t_1_1_V_reg_61868 <= call_ret4_sp_prim_conv_sector_fu_37378_ap_return_76;
phzvl_t_1_2_V_reg_61873 <= call_ret4_sp_prim_conv_sector_fu_37378_ap_return_77;
phzvl_t_1_3_V_reg_61503 <= call_ret4_sp_prim_conv_sector_fu_37378_ap_return_3;
phzvl_t_1_4_V_reg_61508 <= call_ret4_sp_prim_conv_sector_fu_37378_ap_return_4;
phzvl_t_1_5_V_reg_61513 <= call_ret4_sp_prim_conv_sector_fu_37378_ap_return_5;
phzvl_t_2_0_V_reg_61518 <= call_ret4_sp_prim_conv_sector_fu_37378_ap_return_6;
phzvl_t_2_1_V_reg_61523 <= call_ret4_sp_prim_conv_sector_fu_37378_ap_return_7;
phzvl_t_2_2_V_reg_61528 <= call_ret4_sp_prim_conv_sector_fu_37378_ap_return_8;
phzvl_t_2_3_V_reg_61533 <= call_ret4_sp_prim_conv_sector_fu_37378_ap_return_9;
phzvl_t_2_4_V_reg_61538 <= call_ret4_sp_prim_conv_sector_fu_37378_ap_return_10;
phzvl_t_2_5_V_reg_61543 <= call_ret4_sp_prim_conv_sector_fu_37378_ap_return_11;
phzvl_t_2_6_V_reg_61548 <= call_ret4_sp_prim_conv_sector_fu_37378_ap_return_12;
phzvl_t_2_7_V_reg_61553 <= call_ret4_sp_prim_conv_sector_fu_37378_ap_return_13;
phzvl_t_2_8_V_reg_61558 <= call_ret4_sp_prim_conv_sector_fu_37378_ap_return_14;
phzvl_t_3_0_V_reg_61563 <= call_ret4_sp_prim_conv_sector_fu_37378_ap_return_15;
phzvl_t_3_1_V_reg_61568 <= call_ret4_sp_prim_conv_sector_fu_37378_ap_return_16;
phzvl_t_3_2_V_reg_61573 <= call_ret4_sp_prim_conv_sector_fu_37378_ap_return_17;
phzvl_t_3_3_V_reg_61578 <= call_ret4_sp_prim_conv_sector_fu_37378_ap_return_18;
phzvl_t_3_4_V_reg_61583 <= call_ret4_sp_prim_conv_sector_fu_37378_ap_return_19;
phzvl_t_3_5_V_reg_61588 <= call_ret4_sp_prim_conv_sector_fu_37378_ap_return_20;
phzvl_t_3_6_V_reg_61593 <= call_ret4_sp_prim_conv_sector_fu_37378_ap_return_21;
phzvl_t_3_7_V_reg_61598 <= call_ret4_sp_prim_conv_sector_fu_37378_ap_return_22;
phzvl_t_3_8_V_reg_61603 <= call_ret4_sp_prim_conv_sector_fu_37378_ap_return_23;
phzvl_t_4_0_V_reg_61608 <= call_ret4_sp_prim_conv_sector_fu_37378_ap_return_24;
phzvl_t_4_1_V_reg_61613 <= call_ret4_sp_prim_conv_sector_fu_37378_ap_return_25;
phzvl_t_4_2_V_reg_61618 <= call_ret4_sp_prim_conv_sector_fu_37378_ap_return_26;
phzvl_t_4_3_V_reg_61623 <= call_ret4_sp_prim_conv_sector_fu_37378_ap_return_27;
phzvl_t_4_4_V_reg_61628 <= call_ret4_sp_prim_conv_sector_fu_37378_ap_return_28;
phzvl_t_4_5_V_reg_61633 <= call_ret4_sp_prim_conv_sector_fu_37378_ap_return_29;
phzvl_t_4_6_V_reg_61638 <= call_ret4_sp_prim_conv_sector_fu_37378_ap_return_30;
phzvl_t_4_7_V_reg_61643 <= call_ret4_sp_prim_conv_sector_fu_37378_ap_return_31;
phzvl_t_4_8_V_reg_61648 <= call_ret4_sp_prim_conv_sector_fu_37378_ap_return_32;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_reg_ppiten_pp0_it1) & (1'b1 == ap_sig_cseq_ST_pp0_stg0_fsm_0))) begin
ph_zone_t_0_1_V_fu_24842 <= call_ret6_sp_zones_fu_52687_ap_return_0;
ph_zone_t_0_2_V_fu_24846 <= call_ret6_sp_zones_fu_52687_ap_return_1;
ph_zone_t_0_3_V_fu_24850 <= call_ret6_sp_zones_fu_52687_ap_return_2;
ph_zone_t_0_4_V_fu_24854 <= call_ret6_sp_zones_fu_52687_ap_return_3;
ph_zone_t_1_1_V_fu_24862 <= call_ret6_sp_zones_fu_52687_ap_return_4;
ph_zone_t_1_2_V_fu_24866 <= call_ret6_sp_zones_fu_52687_ap_return_5;
ph_zone_t_1_3_V_fu_24870 <= call_ret6_sp_zones_fu_52687_ap_return_6;
ph_zone_t_1_4_V_fu_24874 <= call_ret6_sp_zones_fu_52687_ap_return_7;
ph_zone_t_2_1_V_fu_24882 <= call_ret6_sp_zones_fu_52687_ap_return_8;
ph_zone_t_2_2_V_fu_24886 <= call_ret6_sp_zones_fu_52687_ap_return_9;
ph_zone_t_2_3_V_fu_24890 <= call_ret6_sp_zones_fu_52687_ap_return_10;
ph_zone_t_2_4_V_fu_24894 <= call_ret6_sp_zones_fu_52687_ap_return_11;
ph_zone_t_3_1_V_fu_24902 <= call_ret6_sp_zones_fu_52687_ap_return_12;
ph_zone_t_3_2_V_fu_24906 <= call_ret6_sp_zones_fu_52687_ap_return_13;
ph_zone_t_3_3_V_fu_24910 <= call_ret6_sp_zones_fu_52687_ap_return_14;
end
end
always @ (*) begin
if (((1'b1 == 1'b1) & (1'b1 == ap_sig_cseq_ST_pp0_stg0_fsm_0))) begin
ap_sig_call_ret4_sp_prim_conv_sector_fu_37378_ap_start = 1'b1;
end else begin
ap_sig_call_ret4_sp_prim_conv_sector_fu_37378_ap_start = 1'b0;
end
end
always @ (*) begin
if (ap_sig_1237) begin
ap_sig_cseq_ST_pp0_stg0_fsm_0 = 1'b1;
end else begin
ap_sig_cseq_ST_pp0_stg0_fsm_0 = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == 1'b1) & (1'b1 == ap_sig_cseq_ST_pp0_stg0_fsm_0))) begin
ap_sig_grp_sp_co_ord_delay_fu_52775_ap_start = 1'b1;
end else begin
ap_sig_grp_sp_co_ord_delay_fu_52775_ap_start = 1'b0;
end
end
assign ap_sig_pprstidle_pp0 = 1'b0;
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
bt_ci_0_0_V_ap_vld = 1'b1;
end else begin
bt_ci_0_0_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
bt_ci_0_1_V_ap_vld = 1'b1;
end else begin
bt_ci_0_1_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
bt_ci_0_2_V_ap_vld = 1'b1;
end else begin
bt_ci_0_2_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
bt_ci_0_3_V_ap_vld = 1'b1;
end else begin
bt_ci_0_3_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
bt_ci_0_4_V_ap_vld = 1'b1;
end else begin
bt_ci_0_4_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
bt_ci_1_0_V_ap_vld = 1'b1;
end else begin
bt_ci_1_0_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
bt_ci_1_1_V_ap_vld = 1'b1;
end else begin
bt_ci_1_1_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
bt_ci_1_2_V_ap_vld = 1'b1;
end else begin
bt_ci_1_2_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
bt_ci_1_3_V_ap_vld = 1'b1;
end else begin
bt_ci_1_3_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
bt_ci_1_4_V_ap_vld = 1'b1;
end else begin
bt_ci_1_4_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
bt_ci_2_0_V_ap_vld = 1'b1;
end else begin
bt_ci_2_0_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
bt_ci_2_1_V_ap_vld = 1'b1;
end else begin
bt_ci_2_1_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
bt_ci_2_2_V_ap_vld = 1'b1;
end else begin
bt_ci_2_2_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
bt_ci_2_3_V_ap_vld = 1'b1;
end else begin
bt_ci_2_3_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
bt_ci_2_4_V_ap_vld = 1'b1;
end else begin
bt_ci_2_4_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
bt_cpattern_0_0_V_ap_vld = 1'b1;
end else begin
bt_cpattern_0_0_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
bt_cpattern_0_1_V_ap_vld = 1'b1;
end else begin
bt_cpattern_0_1_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
bt_cpattern_0_2_V_ap_vld = 1'b1;
end else begin
bt_cpattern_0_2_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
bt_cpattern_0_3_V_ap_vld = 1'b1;
end else begin
bt_cpattern_0_3_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
bt_cpattern_1_0_V_ap_vld = 1'b1;
end else begin
bt_cpattern_1_0_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
bt_cpattern_1_1_V_ap_vld = 1'b1;
end else begin
bt_cpattern_1_1_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
bt_cpattern_1_2_V_ap_vld = 1'b1;
end else begin
bt_cpattern_1_2_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
bt_cpattern_1_3_V_ap_vld = 1'b1;
end else begin
bt_cpattern_1_3_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
bt_cpattern_2_0_V_ap_vld = 1'b1;
end else begin
bt_cpattern_2_0_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
bt_cpattern_2_1_V_ap_vld = 1'b1;
end else begin
bt_cpattern_2_1_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
bt_cpattern_2_2_V_ap_vld = 1'b1;
end else begin
bt_cpattern_2_2_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
bt_cpattern_2_3_V_ap_vld = 1'b1;
end else begin
bt_cpattern_2_3_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
bt_delta_ph_0_0_V_ap_vld = 1'b1;
end else begin
bt_delta_ph_0_0_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
bt_delta_ph_0_1_V_ap_vld = 1'b1;
end else begin
bt_delta_ph_0_1_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
bt_delta_ph_0_2_V_ap_vld = 1'b1;
end else begin
bt_delta_ph_0_2_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
bt_delta_ph_0_3_V_ap_vld = 1'b1;
end else begin
bt_delta_ph_0_3_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
bt_delta_ph_0_4_V_ap_vld = 1'b1;
end else begin
bt_delta_ph_0_4_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
bt_delta_ph_0_5_V_ap_vld = 1'b1;
end else begin
bt_delta_ph_0_5_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
bt_delta_ph_1_0_V_ap_vld = 1'b1;
end else begin
bt_delta_ph_1_0_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
bt_delta_ph_1_1_V_ap_vld = 1'b1;
end else begin
bt_delta_ph_1_1_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
bt_delta_ph_1_2_V_ap_vld = 1'b1;
end else begin
bt_delta_ph_1_2_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
bt_delta_ph_1_3_V_ap_vld = 1'b1;
end else begin
bt_delta_ph_1_3_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
bt_delta_ph_1_4_V_ap_vld = 1'b1;
end else begin
bt_delta_ph_1_4_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
bt_delta_ph_1_5_V_ap_vld = 1'b1;
end else begin
bt_delta_ph_1_5_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
bt_delta_ph_2_0_V_ap_vld = 1'b1;
end else begin
bt_delta_ph_2_0_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
bt_delta_ph_2_1_V_ap_vld = 1'b1;
end else begin
bt_delta_ph_2_1_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
bt_delta_ph_2_2_V_ap_vld = 1'b1;
end else begin
bt_delta_ph_2_2_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
bt_delta_ph_2_3_V_ap_vld = 1'b1;
end else begin
bt_delta_ph_2_3_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
bt_delta_ph_2_4_V_ap_vld = 1'b1;
end else begin
bt_delta_ph_2_4_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
bt_delta_ph_2_5_V_ap_vld = 1'b1;
end else begin
bt_delta_ph_2_5_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
bt_delta_th_0_0_V_ap_vld = 1'b1;
end else begin
bt_delta_th_0_0_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
bt_delta_th_0_1_V_ap_vld = 1'b1;
end else begin
bt_delta_th_0_1_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
bt_delta_th_0_2_V_ap_vld = 1'b1;
end else begin
bt_delta_th_0_2_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
bt_delta_th_0_3_V_ap_vld = 1'b1;
end else begin
bt_delta_th_0_3_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
bt_delta_th_0_4_V_ap_vld = 1'b1;
end else begin
bt_delta_th_0_4_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
bt_delta_th_0_5_V_ap_vld = 1'b1;
end else begin
bt_delta_th_0_5_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
bt_delta_th_1_0_V_ap_vld = 1'b1;
end else begin
bt_delta_th_1_0_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
bt_delta_th_1_1_V_ap_vld = 1'b1;
end else begin
bt_delta_th_1_1_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
bt_delta_th_1_2_V_ap_vld = 1'b1;
end else begin
bt_delta_th_1_2_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
bt_delta_th_1_3_V_ap_vld = 1'b1;
end else begin
bt_delta_th_1_3_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
bt_delta_th_1_4_V_ap_vld = 1'b1;
end else begin
bt_delta_th_1_4_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
bt_delta_th_1_5_V_ap_vld = 1'b1;
end else begin
bt_delta_th_1_5_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
bt_delta_th_2_0_V_ap_vld = 1'b1;
end else begin
bt_delta_th_2_0_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
bt_delta_th_2_1_V_ap_vld = 1'b1;
end else begin
bt_delta_th_2_1_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
bt_delta_th_2_2_V_ap_vld = 1'b1;
end else begin
bt_delta_th_2_2_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
bt_delta_th_2_3_V_ap_vld = 1'b1;
end else begin
bt_delta_th_2_3_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
bt_delta_th_2_4_V_ap_vld = 1'b1;
end else begin
bt_delta_th_2_4_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
bt_delta_th_2_5_V_ap_vld = 1'b1;
end else begin
bt_delta_th_2_5_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
bt_hi_0_0_V_ap_vld = 1'b1;
end else begin
bt_hi_0_0_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
bt_hi_0_1_V_ap_vld = 1'b1;
end else begin
bt_hi_0_1_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
bt_hi_0_2_V_ap_vld = 1'b1;
end else begin
bt_hi_0_2_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
bt_hi_0_3_V_ap_vld = 1'b1;
end else begin
bt_hi_0_3_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
bt_hi_0_4_V_ap_vld = 1'b1;
end else begin
bt_hi_0_4_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
bt_hi_1_0_V_ap_vld = 1'b1;
end else begin
bt_hi_1_0_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
bt_hi_1_1_V_ap_vld = 1'b1;
end else begin
bt_hi_1_1_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
bt_hi_1_2_V_ap_vld = 1'b1;
end else begin
bt_hi_1_2_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
bt_hi_1_3_V_ap_vld = 1'b1;
end else begin
bt_hi_1_3_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
bt_hi_1_4_V_ap_vld = 1'b1;
end else begin
bt_hi_1_4_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
bt_hi_2_0_V_ap_vld = 1'b1;
end else begin
bt_hi_2_0_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
bt_hi_2_1_V_ap_vld = 1'b1;
end else begin
bt_hi_2_1_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
bt_hi_2_2_V_ap_vld = 1'b1;
end else begin
bt_hi_2_2_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
bt_hi_2_3_V_ap_vld = 1'b1;
end else begin
bt_hi_2_3_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
bt_hi_2_4_V_ap_vld = 1'b1;
end else begin
bt_hi_2_4_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
bt_phi_0_V_ap_vld = 1'b1;
end else begin
bt_phi_0_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
bt_phi_1_V_ap_vld = 1'b1;
end else begin
bt_phi_1_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
bt_phi_2_V_ap_vld = 1'b1;
end else begin
bt_phi_2_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
bt_rank_0_V_ap_vld = 1'b1;
end else begin
bt_rank_0_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
bt_rank_1_V_ap_vld = 1'b1;
end else begin
bt_rank_1_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
bt_rank_2_V_ap_vld = 1'b1;
end else begin
bt_rank_2_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
bt_si_0_V_ap_vld = 1'b1;
end else begin
bt_si_0_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
bt_si_1_V_ap_vld = 1'b1;
end else begin
bt_si_1_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
bt_si_2_V_ap_vld = 1'b1;
end else begin
bt_si_2_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
bt_sign_ph_0_V_ap_vld = 1'b1;
end else begin
bt_sign_ph_0_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
bt_sign_ph_1_V_ap_vld = 1'b1;
end else begin
bt_sign_ph_1_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
bt_sign_ph_2_V_ap_vld = 1'b1;
end else begin
bt_sign_ph_2_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
bt_sign_th_0_V_ap_vld = 1'b1;
end else begin
bt_sign_th_0_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
bt_sign_th_1_V_ap_vld = 1'b1;
end else begin
bt_sign_th_1_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
bt_sign_th_2_V_ap_vld = 1'b1;
end else begin
bt_sign_th_2_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
bt_theta_0_V_ap_vld = 1'b1;
end else begin
bt_theta_0_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
bt_theta_1_V_ap_vld = 1'b1;
end else begin
bt_theta_1_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
bt_theta_2_V_ap_vld = 1'b1;
end else begin
bt_theta_2_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
bt_vi_0_0_V_ap_vld = 1'b1;
end else begin
bt_vi_0_0_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
bt_vi_0_1_V_ap_vld = 1'b1;
end else begin
bt_vi_0_1_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
bt_vi_0_2_V_ap_vld = 1'b1;
end else begin
bt_vi_0_2_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
bt_vi_0_3_V_ap_vld = 1'b1;
end else begin
bt_vi_0_3_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
bt_vi_0_4_V_ap_vld = 1'b1;
end else begin
bt_vi_0_4_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
bt_vi_1_0_V_ap_vld = 1'b1;
end else begin
bt_vi_1_0_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
bt_vi_1_1_V_ap_vld = 1'b1;
end else begin
bt_vi_1_1_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
bt_vi_1_2_V_ap_vld = 1'b1;
end else begin
bt_vi_1_2_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
bt_vi_1_3_V_ap_vld = 1'b1;
end else begin
bt_vi_1_3_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
bt_vi_1_4_V_ap_vld = 1'b1;
end else begin
bt_vi_1_4_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
bt_vi_2_0_V_ap_vld = 1'b1;
end else begin
bt_vi_2_0_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
bt_vi_2_1_V_ap_vld = 1'b1;
end else begin
bt_vi_2_1_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
bt_vi_2_2_V_ap_vld = 1'b1;
end else begin
bt_vi_2_2_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
bt_vi_2_3_V_ap_vld = 1'b1;
end else begin
bt_vi_2_3_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
bt_vi_2_4_V_ap_vld = 1'b1;
end else begin
bt_vi_2_4_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_sig_call_ret4_sp_prim_conv_sector_fu_37378_ap_start)) begin
call_ret4_sp_prim_conv_sector_fu_37378_ap_start = ap_sig_call_ret4_sp_prim_conv_sector_fu_37378_ap_start;
end else begin
call_ret4_sp_prim_conv_sector_fu_37378_ap_start = ap_reg_call_ret4_sp_prim_conv_sector_fu_37378_ap_start;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
gmt_crg_V_ap_vld = 1'b1;
end else begin
gmt_crg_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
gmt_eta_0_V_ap_vld = 1'b1;
end else begin
gmt_eta_0_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
gmt_eta_1_V_ap_vld = 1'b1;
end else begin
gmt_eta_1_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
gmt_eta_2_V_ap_vld = 1'b1;
end else begin
gmt_eta_2_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
gmt_phi_0_V_ap_vld = 1'b1;
end else begin
gmt_phi_0_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
gmt_phi_1_V_ap_vld = 1'b1;
end else begin
gmt_phi_1_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
gmt_phi_2_V_ap_vld = 1'b1;
end else begin
gmt_phi_2_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
gmt_qlt_0_V_ap_vld = 1'b1;
end else begin
gmt_qlt_0_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
gmt_qlt_1_V_ap_vld = 1'b1;
end else begin
gmt_qlt_1_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
gmt_qlt_2_V_ap_vld = 1'b1;
end else begin
gmt_qlt_2_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_sig_grp_sp_co_ord_delay_fu_52775_ap_start)) begin
grp_sp_co_ord_delay_fu_52775_ap_start = ap_sig_grp_sp_co_ord_delay_fu_52775_ap_start;
end else begin
grp_sp_co_ord_delay_fu_52775_ap_start = ap_reg_grp_sp_co_ord_delay_fu_52775_ap_start;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
ph_ext_0_0_V_ap_vld = 1'b1;
end else begin
ph_ext_0_0_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
ph_ext_0_1_V_ap_vld = 1'b1;
end else begin
ph_ext_0_1_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
ph_ext_0_2_V_ap_vld = 1'b1;
end else begin
ph_ext_0_2_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
ph_ext_0_3_V_ap_vld = 1'b1;
end else begin
ph_ext_0_3_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
ph_ext_0_4_V_ap_vld = 1'b1;
end else begin
ph_ext_0_4_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
ph_ext_1_0_V_ap_vld = 1'b1;
end else begin
ph_ext_1_0_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
ph_ext_1_1_V_ap_vld = 1'b1;
end else begin
ph_ext_1_1_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
ph_ext_1_2_V_ap_vld = 1'b1;
end else begin
ph_ext_1_2_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
ph_ext_1_3_V_ap_vld = 1'b1;
end else begin
ph_ext_1_3_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
ph_ext_1_4_V_ap_vld = 1'b1;
end else begin
ph_ext_1_4_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
ph_ext_2_0_V_ap_vld = 1'b1;
end else begin
ph_ext_2_0_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
ph_ext_2_1_V_ap_vld = 1'b1;
end else begin
ph_ext_2_1_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
ph_ext_2_2_V_ap_vld = 1'b1;
end else begin
ph_ext_2_2_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
ph_ext_2_3_V_ap_vld = 1'b1;
end else begin
ph_ext_2_3_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
ph_ext_2_4_V_ap_vld = 1'b1;
end else begin
ph_ext_2_4_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
ph_ext_3_0_V_ap_vld = 1'b1;
end else begin
ph_ext_3_0_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
ph_ext_3_1_V_ap_vld = 1'b1;
end else begin
ph_ext_3_1_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
ph_ext_3_2_V_ap_vld = 1'b1;
end else begin
ph_ext_3_2_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
ph_ext_3_3_V_ap_vld = 1'b1;
end else begin
ph_ext_3_3_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
ph_ext_3_4_V_ap_vld = 1'b1;
end else begin
ph_ext_3_4_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it4)) begin
ph_num_0_0_V_ap_lwr = 1'b1;
end else begin
ph_num_0_0_V_ap_lwr = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it4)) begin
ph_num_0_0_V_ap_vld = 1'b1;
end else begin
ph_num_0_0_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it4)) begin
ph_num_0_1_V_ap_lwr = 1'b1;
end else begin
ph_num_0_1_V_ap_lwr = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it4)) begin
ph_num_0_1_V_ap_vld = 1'b1;
end else begin
ph_num_0_1_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it4)) begin
ph_num_0_2_V_ap_lwr = 1'b1;
end else begin
ph_num_0_2_V_ap_lwr = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it4)) begin
ph_num_0_2_V_ap_vld = 1'b1;
end else begin
ph_num_0_2_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it4)) begin
ph_num_1_0_V_ap_lwr = 1'b1;
end else begin
ph_num_1_0_V_ap_lwr = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it4)) begin
ph_num_1_0_V_ap_vld = 1'b1;
end else begin
ph_num_1_0_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it4)) begin
ph_num_1_1_V_ap_lwr = 1'b1;
end else begin
ph_num_1_1_V_ap_lwr = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it4)) begin
ph_num_1_1_V_ap_vld = 1'b1;
end else begin
ph_num_1_1_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it4)) begin
ph_num_1_2_V_ap_lwr = 1'b1;
end else begin
ph_num_1_2_V_ap_lwr = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it4)) begin
ph_num_1_2_V_ap_vld = 1'b1;
end else begin
ph_num_1_2_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it4)) begin
ph_num_2_0_V_ap_lwr = 1'b1;
end else begin
ph_num_2_0_V_ap_lwr = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it4)) begin
ph_num_2_0_V_ap_vld = 1'b1;
end else begin
ph_num_2_0_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it4)) begin
ph_num_2_1_V_ap_lwr = 1'b1;
end else begin
ph_num_2_1_V_ap_lwr = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it4)) begin
ph_num_2_1_V_ap_vld = 1'b1;
end else begin
ph_num_2_1_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it4)) begin
ph_num_2_2_V_ap_lwr = 1'b1;
end else begin
ph_num_2_2_V_ap_lwr = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it4)) begin
ph_num_2_2_V_ap_vld = 1'b1;
end else begin
ph_num_2_2_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it4)) begin
ph_num_3_0_V_ap_lwr = 1'b1;
end else begin
ph_num_3_0_V_ap_lwr = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it4)) begin
ph_num_3_0_V_ap_vld = 1'b1;
end else begin
ph_num_3_0_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it4)) begin
ph_num_3_1_V_ap_lwr = 1'b1;
end else begin
ph_num_3_1_V_ap_lwr = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it4)) begin
ph_num_3_1_V_ap_vld = 1'b1;
end else begin
ph_num_3_1_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it4)) begin
ph_num_3_2_V_ap_lwr = 1'b1;
end else begin
ph_num_3_2_V_ap_lwr = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it4)) begin
ph_num_3_2_V_ap_vld = 1'b1;
end else begin
ph_num_3_2_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it4)) begin
ph_q_0_0_V_ap_lwr = 1'b1;
end else begin
ph_q_0_0_V_ap_lwr = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it4)) begin
ph_q_0_0_V_ap_vld = 1'b1;
end else begin
ph_q_0_0_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it4)) begin
ph_q_0_1_V_ap_lwr = 1'b1;
end else begin
ph_q_0_1_V_ap_lwr = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it4)) begin
ph_q_0_1_V_ap_vld = 1'b1;
end else begin
ph_q_0_1_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it4)) begin
ph_q_0_2_V_ap_lwr = 1'b1;
end else begin
ph_q_0_2_V_ap_lwr = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it4)) begin
ph_q_0_2_V_ap_vld = 1'b1;
end else begin
ph_q_0_2_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it4)) begin
ph_q_1_0_V_ap_lwr = 1'b1;
end else begin
ph_q_1_0_V_ap_lwr = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it4)) begin
ph_q_1_0_V_ap_vld = 1'b1;
end else begin
ph_q_1_0_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it4)) begin
ph_q_1_1_V_ap_lwr = 1'b1;
end else begin
ph_q_1_1_V_ap_lwr = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it4)) begin
ph_q_1_1_V_ap_vld = 1'b1;
end else begin
ph_q_1_1_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it4)) begin
ph_q_1_2_V_ap_lwr = 1'b1;
end else begin
ph_q_1_2_V_ap_lwr = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it4)) begin
ph_q_1_2_V_ap_vld = 1'b1;
end else begin
ph_q_1_2_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it4)) begin
ph_q_2_0_V_ap_lwr = 1'b1;
end else begin
ph_q_2_0_V_ap_lwr = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it4)) begin
ph_q_2_0_V_ap_vld = 1'b1;
end else begin
ph_q_2_0_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it4)) begin
ph_q_2_1_V_ap_lwr = 1'b1;
end else begin
ph_q_2_1_V_ap_lwr = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it4)) begin
ph_q_2_1_V_ap_vld = 1'b1;
end else begin
ph_q_2_1_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it4)) begin
ph_q_2_2_V_ap_lwr = 1'b1;
end else begin
ph_q_2_2_V_ap_lwr = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it4)) begin
ph_q_2_2_V_ap_vld = 1'b1;
end else begin
ph_q_2_2_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it4)) begin
ph_q_3_0_V_ap_lwr = 1'b1;
end else begin
ph_q_3_0_V_ap_lwr = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it4)) begin
ph_q_3_0_V_ap_vld = 1'b1;
end else begin
ph_q_3_0_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it4)) begin
ph_q_3_1_V_ap_lwr = 1'b1;
end else begin
ph_q_3_1_V_ap_lwr = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it4)) begin
ph_q_3_1_V_ap_vld = 1'b1;
end else begin
ph_q_3_1_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it4)) begin
ph_q_3_2_V_ap_lwr = 1'b1;
end else begin
ph_q_3_2_V_ap_lwr = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it4)) begin
ph_q_3_2_V_ap_vld = 1'b1;
end else begin
ph_q_3_2_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
ph_zone_0_0_V_ap_vld = 1'b1;
end else begin
ph_zone_0_0_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
ph_zone_0_1_V_ap_vld = 1'b1;
end else begin
ph_zone_0_1_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
ph_zone_0_2_V_ap_vld = 1'b1;
end else begin
ph_zone_0_2_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
ph_zone_0_3_V_ap_vld = 1'b1;
end else begin
ph_zone_0_3_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
ph_zone_0_4_V_ap_vld = 1'b1;
end else begin
ph_zone_0_4_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
ph_zone_1_0_V_ap_vld = 1'b1;
end else begin
ph_zone_1_0_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
ph_zone_1_1_V_ap_vld = 1'b1;
end else begin
ph_zone_1_1_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
ph_zone_1_2_V_ap_vld = 1'b1;
end else begin
ph_zone_1_2_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
ph_zone_1_3_V_ap_vld = 1'b1;
end else begin
ph_zone_1_3_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
ph_zone_1_4_V_ap_vld = 1'b1;
end else begin
ph_zone_1_4_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
ph_zone_2_0_V_ap_vld = 1'b1;
end else begin
ph_zone_2_0_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
ph_zone_2_1_V_ap_vld = 1'b1;
end else begin
ph_zone_2_1_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
ph_zone_2_2_V_ap_vld = 1'b1;
end else begin
ph_zone_2_2_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
ph_zone_2_3_V_ap_vld = 1'b1;
end else begin
ph_zone_2_3_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
ph_zone_2_4_V_ap_vld = 1'b1;
end else begin
ph_zone_2_4_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
ph_zone_3_0_V_ap_vld = 1'b1;
end else begin
ph_zone_3_0_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
ph_zone_3_1_V_ap_vld = 1'b1;
end else begin
ph_zone_3_1_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
ph_zone_3_2_V_ap_vld = 1'b1;
end else begin
ph_zone_3_2_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
ph_zone_3_3_V_ap_vld = 1'b1;
end else begin
ph_zone_3_3_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
ph_zone_3_4_V_ap_vld = 1'b1;
end else begin
ph_zone_3_4_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
ptlut_addr_0_V_ap_vld = 1'b1;
end else begin
ptlut_addr_0_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
ptlut_addr_1_V_ap_vld = 1'b1;
end else begin
ptlut_addr_1_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
ptlut_addr_2_V_ap_vld = 1'b1;
end else begin
ptlut_addr_2_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
ptlut_addr_val_V_ap_vld = 1'b1;
end else begin
ptlut_addr_val_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
ptlut_cs_0_V_ap_vld = 1'b1;
end else begin
ptlut_cs_0_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
ptlut_cs_1_V_ap_vld = 1'b1;
end else begin
ptlut_cs_1_V_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_reg_ppiten_pp0_it10)) begin
ptlut_cs_2_V_ap_vld = 1'b1;
end else begin
ptlut_cs_2_V_ap_vld = 1'b0;
end
end
always @ (*) begin
case (ap_CS_fsm)
ap_ST_pp0_stg0_fsm_0 : begin
ap_NS_fsm = ap_ST_pp0_stg0_fsm_0;
end
default : begin
ap_NS_fsm = 'bx;
end
endcase
end
assign ap_reg_call_ret4_sp_prim_conv_sector_fu_37378_ap_start = 1'b0;
assign ap_reg_grp_sp_co_ord_delay_fu_52775_ap_start = 1'b0;
always @ (*) begin
ap_sig_1237 = (ap_CS_fsm[ap_const_lv32_0] == 1'b1);
end
assign bt_ci_0_0_V = bt_ci_t_0_0_V_reg_65044;
assign bt_ci_0_1_V = bt_ci_t_0_1_V_reg_65050;
assign bt_ci_0_2_V = bt_ci_t_0_2_V_reg_65056;
assign bt_ci_0_3_V = bt_ci_t_0_3_V_reg_65062;
assign bt_ci_0_4_V = bt_ci_t_0_4_V_reg_65068;
assign bt_ci_1_0_V = bt_ci_t_1_0_V_reg_65074;
assign bt_ci_1_1_V = bt_ci_t_1_1_V_reg_65080;
assign bt_ci_1_2_V = bt_ci_t_1_2_V_reg_65086;
assign bt_ci_1_3_V = bt_ci_t_1_3_V_reg_65092;
assign bt_ci_1_4_V = bt_ci_t_1_4_V_reg_65098;
assign bt_ci_2_0_V = bt_ci_t_2_0_V_reg_65104;
assign bt_ci_2_1_V = bt_ci_t_2_1_V_reg_65110;
assign bt_ci_2_2_V = bt_ci_t_2_2_V_reg_65116;
assign bt_ci_2_3_V = bt_ci_t_2_3_V_reg_65122;
assign bt_ci_2_4_V = bt_ci_t_2_4_V_reg_65128;
assign bt_cpattern_0_0_V = bt_cpattern_t_0_0_V_reg_64549;
assign bt_cpattern_0_1_V = bt_cpattern_t_0_1_V_reg_64555;
assign bt_cpattern_0_2_V = bt_cpattern_t_0_2_V_reg_64561;
assign bt_cpattern_0_3_V = bt_cpattern_t_0_3_V_reg_64567;
assign bt_cpattern_1_0_V = bt_cpattern_t_1_0_V_reg_64573;
assign bt_cpattern_1_1_V = bt_cpattern_t_1_1_V_reg_64579;
assign bt_cpattern_1_2_V = bt_cpattern_t_1_2_V_reg_64585;
assign bt_cpattern_1_3_V = bt_cpattern_t_1_3_V_reg_64591;
assign bt_cpattern_2_0_V = bt_cpattern_t_2_0_V_reg_64597;
assign bt_cpattern_2_1_V = bt_cpattern_t_2_1_V_reg_64603;
assign bt_cpattern_2_2_V = bt_cpattern_t_2_2_V_reg_64609;
assign bt_cpattern_2_3_V = bt_cpattern_t_2_3_V_reg_64615;
assign bt_delta_ph_0_0_V = bt_delta_ph_t_0_0_V_reg_64621;
assign bt_delta_ph_0_1_V = bt_delta_ph_t_0_1_V_reg_64627;
assign bt_delta_ph_0_2_V = bt_delta_ph_t_0_2_V_reg_64633;
assign bt_delta_ph_0_3_V = bt_delta_ph_t_0_3_V_reg_64639;
assign bt_delta_ph_0_4_V = bt_delta_ph_t_0_4_V_reg_64645;
assign bt_delta_ph_0_5_V = bt_delta_ph_t_0_5_V_reg_64651;
assign bt_delta_ph_1_0_V = bt_delta_ph_t_1_0_V_reg_64657;
assign bt_delta_ph_1_1_V = bt_delta_ph_t_1_1_V_reg_64663;
assign bt_delta_ph_1_2_V = bt_delta_ph_t_1_2_V_reg_64669;
assign bt_delta_ph_1_3_V = bt_delta_ph_t_1_3_V_reg_64675;
assign bt_delta_ph_1_4_V = bt_delta_ph_t_1_4_V_reg_64681;
assign bt_delta_ph_1_5_V = bt_delta_ph_t_1_5_V_reg_64687;
assign bt_delta_ph_2_0_V = bt_delta_ph_t_2_0_V_reg_64693;
assign bt_delta_ph_2_1_V = bt_delta_ph_t_2_1_V_reg_64699;
assign bt_delta_ph_2_2_V = bt_delta_ph_t_2_2_V_reg_64705;
assign bt_delta_ph_2_3_V = bt_delta_ph_t_2_3_V_reg_64711;
assign bt_delta_ph_2_4_V = bt_delta_ph_t_2_4_V_reg_64717;
assign bt_delta_ph_2_5_V = bt_delta_ph_t_2_5_V_reg_64723;
assign bt_delta_th_0_0_V = bt_delta_th_t_0_0_V_reg_64729;
assign bt_delta_th_0_1_V = bt_delta_th_t_0_1_V_reg_64735;
assign bt_delta_th_0_2_V = bt_delta_th_t_0_2_V_reg_64741;
assign bt_delta_th_0_3_V = bt_delta_th_t_0_3_V_reg_64747;
assign bt_delta_th_0_4_V = bt_delta_th_t_0_4_V_reg_64753;
assign bt_delta_th_0_5_V = bt_delta_th_t_0_5_V_reg_64759;
assign bt_delta_th_1_0_V = bt_delta_th_t_1_0_V_reg_64765;
assign bt_delta_th_1_1_V = bt_delta_th_t_1_1_V_reg_64771;
assign bt_delta_th_1_2_V = bt_delta_th_t_1_2_V_reg_64777;
assign bt_delta_th_1_3_V = bt_delta_th_t_1_3_V_reg_64783;
assign bt_delta_th_1_4_V = bt_delta_th_t_1_4_V_reg_64789;
assign bt_delta_th_1_5_V = bt_delta_th_t_1_5_V_reg_64795;
assign bt_delta_th_2_0_V = bt_delta_th_t_2_0_V_reg_64801;
assign bt_delta_th_2_1_V = bt_delta_th_t_2_1_V_reg_64807;
assign bt_delta_th_2_2_V = bt_delta_th_t_2_2_V_reg_64813;
assign bt_delta_th_2_3_V = bt_delta_th_t_2_3_V_reg_64819;
assign bt_delta_th_2_4_V = bt_delta_th_t_2_4_V_reg_64825;
assign bt_delta_th_2_5_V = bt_delta_th_t_2_5_V_reg_64831;
assign bt_hi_0_0_V = bt_hi_t_0_0_V_reg_64969;
assign bt_hi_0_1_V = bt_hi_t_0_1_V_reg_64974;
assign bt_hi_0_2_V = bt_hi_t_0_2_V_reg_64979;
assign bt_hi_0_3_V = bt_hi_t_0_3_V_reg_64984;
assign bt_hi_0_4_V = bt_hi_t_0_4_V_reg_64989;
assign bt_hi_1_0_V = bt_hi_t_1_0_V_reg_64994;
assign bt_hi_1_1_V = bt_hi_t_1_1_V_reg_64999;
assign bt_hi_1_2_V = bt_hi_t_1_2_V_reg_65004;
assign bt_hi_1_3_V = bt_hi_t_1_3_V_reg_65009;
assign bt_hi_1_4_V = bt_hi_t_1_4_V_reg_65014;
assign bt_hi_2_0_V = bt_hi_t_2_0_V_reg_65019;
assign bt_hi_2_1_V = bt_hi_t_2_1_V_reg_65024;
assign bt_hi_2_2_V = bt_hi_t_2_2_V_reg_65029;
assign bt_hi_2_3_V = bt_hi_t_2_3_V_reg_65034;
assign bt_hi_2_4_V = bt_hi_t_2_4_V_reg_65039;
assign bt_phi_0_V = bt_phi_t_0_V_reg_64513;
assign bt_phi_1_V = bt_phi_t_1_V_reg_64519;
assign bt_phi_2_V = bt_phi_t_2_V_reg_64525;
assign bt_rank_0_V = bt_rank_t_0_V_reg_64873;
assign bt_rank_1_V = bt_rank_t_1_V_reg_64879;
assign bt_rank_2_V = bt_rank_t_2_V_reg_64885;
assign bt_si_0_V = bt_si_t_0_V_reg_65134;
assign bt_si_1_V = bt_si_t_1_V_reg_65139;
assign bt_si_2_V = bt_si_t_2_V_reg_65144;
assign bt_sign_ph_0_V = bt_sign_ph_t_0_V_reg_64837;
assign bt_sign_ph_1_V = bt_sign_ph_t_1_V_reg_64843;
assign bt_sign_ph_2_V = bt_sign_ph_t_2_V_reg_64849;
assign bt_sign_th_0_V = bt_sign_th_t_0_V_reg_64855;
assign bt_sign_th_1_V = bt_sign_th_t_1_V_reg_64861;
assign bt_sign_th_2_V = bt_sign_th_t_2_V_reg_64867;
assign bt_theta_0_V = bt_theta_t_0_V_reg_64531;
assign bt_theta_1_V = bt_theta_t_1_V_reg_64537;
assign bt_theta_2_V = bt_theta_t_2_V_reg_64543;
assign bt_vi_0_0_V = bt_vi_t_0_0_V_reg_64891;
assign bt_vi_0_1_V = bt_vi_t_0_1_V_reg_64897;
assign bt_vi_0_2_V = bt_vi_t_0_2_V_reg_64902;
assign bt_vi_0_3_V = bt_vi_t_0_3_V_reg_64907;
assign bt_vi_0_4_V = bt_vi_t_0_4_V_reg_64912;
assign bt_vi_1_0_V = bt_vi_t_1_0_V_reg_64917;
assign bt_vi_1_1_V = bt_vi_t_1_1_V_reg_64923;
assign bt_vi_1_2_V = bt_vi_t_1_2_V_reg_64928;
assign bt_vi_1_3_V = bt_vi_t_1_3_V_reg_64933;
assign bt_vi_1_4_V = bt_vi_t_1_4_V_reg_64938;
assign bt_vi_2_0_V = bt_vi_t_2_0_V_reg_64943;
assign bt_vi_2_1_V = bt_vi_t_2_1_V_reg_64949;
assign bt_vi_2_2_V = bt_vi_t_2_2_V_reg_64954;
assign bt_vi_2_3_V = bt_vi_t_2_3_V_reg_64959;
assign bt_vi_2_4_V = bt_vi_t_2_4_V_reg_64964;
assign call_ret7_sp_extend_sector_fu_54039_ap_start = ap_reg_call_ret7_sp_extend_sector_fu_54039_ap_start;
assign ci_V_address0 = ap_const_lv6_0;
assign ci_V_address1 = ap_const_lv6_0;
assign ci_V_ce0 = 1'b0;
assign ci_V_ce1 = 1'b0;
assign ci_V_d0 = ap_const_lv3_0;
assign ci_V_d1 = ap_const_lv3_0;
assign ci_V_we0 = 1'b0;
assign ci_V_we1 = 1'b0;
assign cir_V_address0 = ap_const_lv6_0;
assign cir_V_address1 = ap_const_lv6_0;
assign cir_V_ce0 = 1'b0;
assign cir_V_ce1 = 1'b0;
assign cir_V_d0 = ap_const_lv3_0;
assign cir_V_d1 = ap_const_lv3_0;
assign cir_V_we0 = 1'b0;
assign cir_V_we1 = 1'b0;
assign cpat_match_V_address0 = ap_const_lv6_0;
assign cpat_match_V_address1 = ap_const_lv6_0;
assign cpat_match_V_ce0 = 1'b0;
assign cpat_match_V_ce1 = 1'b0;
assign cpat_match_V_d0 = ap_const_lv4_0;
assign cpat_match_V_d1 = ap_const_lv4_0;
assign cpat_match_V_we0 = 1'b0;
assign cpat_match_V_we1 = 1'b0;
assign cpatr_V_address0 = ap_const_lv7_0;
assign cpatr_V_address1 = ap_const_lv7_0;
assign cpatr_V_ce0 = 1'b0;
assign cpatr_V_ce1 = 1'b0;
assign cpatr_V_d0 = ap_const_lv4_0;
assign cpatr_V_d1 = ap_const_lv4_0;
assign cpatr_V_we0 = 1'b0;
assign cpatr_V_we1 = 1'b0;
assign cpattern_V_address0 = ap_const_lv6_0;
assign cpattern_V_address1 = ap_const_lv6_0;
assign cpattern_V_ce0 = 1'b0;
assign cpattern_V_ce1 = 1'b0;
assign cpattern_V_d0 = ap_const_lv4_0;
assign cpattern_V_d1 = ap_const_lv4_0;
assign cpattern_V_we0 = 1'b0;
assign cpattern_V_we1 = 1'b0;
assign delta_ph_V_address0 = ap_const_lv7_0;
assign delta_ph_V_address1 = ap_const_lv7_0;
assign delta_ph_V_ce0 = 1'b0;
assign delta_ph_V_ce1 = 1'b0;
assign delta_ph_V_d0 = ap_const_lv12_0;
assign delta_ph_V_d1 = ap_const_lv12_0;
assign delta_ph_V_we0 = 1'b0;
assign delta_ph_V_we1 = 1'b0;
assign delta_th_V_address0 = ap_const_lv7_0;
assign delta_th_V_address1 = ap_const_lv7_0;
assign delta_th_V_ce0 = 1'b0;
assign delta_th_V_ce1 = 1'b0;
assign delta_th_V_d0 = ap_const_lv7_0;
assign delta_th_V_d1 = ap_const_lv7_0;
assign delta_th_V_we0 = 1'b0;
assign delta_th_V_we1 = 1'b0;
assign extLd1_fu_61105_p1 = ph_zone_t_1_0_V_fu_24858;
assign extLd2_fu_61149_p1 = ph_zone_t_2_0_V_fu_24878;
assign extLd3_fu_61193_p1 = ph_zone_t_3_0_V_fu_24898;
assign extLd4_fu_61229_p1 = ph_zone_t_3_4_V_fu_24914;
assign extLd_fu_61061_p1 = ph_zone_t_0_0_V_fu_24838;
assign gmt_crg_V = grp_sp_ptlut_address_fu_54138_ap_return_1;
assign gmt_eta_0_V = grp_sp_ptlut_address_fu_54138_ap_return_14;
assign gmt_eta_1_V = grp_sp_ptlut_address_fu_54138_ap_return_15;
assign gmt_eta_2_V = grp_sp_ptlut_address_fu_54138_ap_return_16;
assign gmt_phi_0_V = grp_sp_ptlut_address_fu_54138_ap_return_5;
assign gmt_phi_1_V = grp_sp_ptlut_address_fu_54138_ap_return_6;
assign gmt_phi_2_V = grp_sp_ptlut_address_fu_54138_ap_return_7;
assign gmt_qlt_0_V = grp_sp_ptlut_address_fu_54138_ap_return_8;
assign gmt_qlt_1_V = grp_sp_ptlut_address_fu_54138_ap_return_9;
assign gmt_qlt_2_V = grp_sp_ptlut_address_fu_54138_ap_return_10;
assign grp_sp_ph_pattern_sector_fu_28574_ap_start = ap_reg_grp_sp_ph_pattern_sector_fu_28574_ap_start;
assign hi_V_address0 = ap_const_lv6_0;
assign hi_V_address1 = ap_const_lv6_0;
assign hi_V_ce0 = 1'b0;
assign hi_V_ce1 = 1'b0;
assign hi_V_d0 = ap_const_lv2_0;
assign hi_V_d1 = ap_const_lv2_0;
assign hi_V_we0 = 1'b0;
assign hi_V_we1 = 1'b0;
assign hir_V_address0 = ap_const_lv6_0;
assign hir_V_address1 = ap_const_lv6_0;
assign hir_V_ce0 = 1'b0;
assign hir_V_ce1 = 1'b0;
assign hir_V_d0 = ap_const_lv2_0;
assign hir_V_d1 = ap_const_lv2_0;
assign hir_V_we0 = 1'b0;
assign hir_V_we1 = 1'b0;
assign me11a_V_address0 = ap_const_lv3_0;
assign me11a_V_address1 = ap_const_lv3_0;
assign me11a_V_ce0 = 1'b0;
assign me11a_V_ce1 = 1'b0;
assign me11a_V_d0 = ap_const_lv2_0;
assign me11a_V_d1 = ap_const_lv2_0;
assign me11a_V_we0 = 1'b0;
assign me11a_V_we1 = 1'b0;
assign ph_V_address0 = ap_const_lv7_0;
assign ph_V_address1 = ap_const_lv7_0;
assign ph_V_ce0 = 1'b0;
assign ph_V_ce1 = 1'b0;
assign ph_V_d0 = ap_const_lv12_0;
assign ph_V_d1 = ap_const_lv12_0;
assign ph_V_we0 = 1'b0;
assign ph_V_we1 = 1'b0;
assign ph_ext_0_0_V = ph_ext_t_0_0_V_fu_24918;
assign ph_ext_0_1_V = ph_ext_t_0_1_V_fu_24922;
assign ph_ext_0_2_V = ph_ext_t_0_2_V_fu_24926;
assign ph_ext_0_3_V = ph_ext_t_0_3_V_fu_24930;
assign ph_ext_0_4_V = ph_ext_t_0_4_V_fu_24934;
assign ph_ext_1_0_V = ph_ext_t_1_0_V_fu_24938;
assign ph_ext_1_1_V = ph_ext_t_1_1_V_fu_24942;
assign ph_ext_1_2_V = ph_ext_t_1_2_V_fu_24946;
assign ph_ext_1_3_V = ph_ext_t_1_3_V_fu_24950;
assign ph_ext_1_4_V = ph_ext_t_1_4_V_fu_24954;
assign ph_ext_2_0_V = ph_ext_t_2_0_V_fu_24958;
assign ph_ext_2_1_V = ph_ext_t_2_1_V_fu_24962;
assign ph_ext_2_2_V = ph_ext_t_2_2_V_fu_24966;
assign ph_ext_2_3_V = ph_ext_t_2_3_V_fu_24970;
assign ph_ext_2_4_V = ph_ext_t_2_4_V_fu_24974;
assign ph_ext_3_0_V = ph_ext_t_3_0_V_fu_24978;
assign ph_ext_3_1_V = ph_ext_t_3_1_V_fu_24982;
assign ph_ext_3_2_V = ph_ext_t_3_2_V_fu_24986;
assign ph_ext_3_3_V = ph_ext_t_3_3_V_fu_24990;
assign ph_ext_3_4_V = ph_ext_t_3_4_V_fu_24994;
assign ph_hit_V_address0 = ap_const_lv6_0;
assign ph_hit_V_address1 = ap_const_lv6_0;
assign ph_hit_V_ce0 = 1'b0;
assign ph_hit_V_ce1 = 1'b0;
assign ph_hit_V_d0 = ap_const_lv44_0;
assign ph_hit_V_d1 = ap_const_lv44_0;
assign ph_hit_V_we0 = 1'b0;
assign ph_hit_V_we1 = 1'b0;
assign ph_match_V_address0 = ap_const_lv6_0;
assign ph_match_V_address1 = ap_const_lv6_0;
assign ph_match_V_ce0 = 1'b0;
assign ph_match_V_ce1 = 1'b0;
assign ph_match_V_d0 = ap_const_lv12_0;
assign ph_match_V_d1 = ap_const_lv12_0;
assign ph_match_V_we0 = 1'b0;
assign ph_match_V_we1 = 1'b0;
assign ph_num_0_0_V = grp_sp_sort_sector_fu_52195_ap_return_0;
assign ph_num_0_1_V = grp_sp_sort_sector_fu_52195_ap_return_1;
assign ph_num_0_2_V = grp_sp_sort_sector_fu_52195_ap_return_2;
assign ph_num_1_0_V = grp_sp_sort_sector_fu_52195_ap_return_3;
assign ph_num_1_1_V = grp_sp_sort_sector_fu_52195_ap_return_4;
assign ph_num_1_2_V = grp_sp_sort_sector_fu_52195_ap_return_5;
assign ph_num_2_0_V = grp_sp_sort_sector_fu_52195_ap_return_6;
assign ph_num_2_1_V = grp_sp_sort_sector_fu_52195_ap_return_7;
assign ph_num_2_2_V = grp_sp_sort_sector_fu_52195_ap_return_8;
assign ph_num_3_0_V = grp_sp_sort_sector_fu_52195_ap_return_9;
assign ph_num_3_1_V = grp_sp_sort_sector_fu_52195_ap_return_10;
assign ph_num_3_2_V = grp_sp_sort_sector_fu_52195_ap_return_11;
assign ph_q_0_0_V = grp_sp_sort_sector_fu_52195_ap_return_12;
assign ph_q_0_1_V = grp_sp_sort_sector_fu_52195_ap_return_13;
assign ph_q_0_2_V = grp_sp_sort_sector_fu_52195_ap_return_14;
assign ph_q_1_0_V = grp_sp_sort_sector_fu_52195_ap_return_15;
assign ph_q_1_1_V = grp_sp_sort_sector_fu_52195_ap_return_16;
assign ph_q_1_2_V = grp_sp_sort_sector_fu_52195_ap_return_17;
assign ph_q_2_0_V = grp_sp_sort_sector_fu_52195_ap_return_18;
assign ph_q_2_1_V = grp_sp_sort_sector_fu_52195_ap_return_19;
assign ph_q_2_2_V = grp_sp_sort_sector_fu_52195_ap_return_20;
assign ph_q_3_0_V = grp_sp_sort_sector_fu_52195_ap_return_21;
assign ph_q_3_1_V = grp_sp_sort_sector_fu_52195_ap_return_22;
assign ph_q_3_2_V = grp_sp_sort_sector_fu_52195_ap_return_23;
assign ph_qr_V_address0 = ap_const_lv4_0;
assign ph_qr_V_address1 = ap_const_lv4_0;
assign ph_qr_V_ce0 = 1'b0;
assign ph_qr_V_ce1 = 1'b0;
assign ph_qr_V_d0 = ap_const_lv6_0;
assign ph_qr_V_d1 = ap_const_lv6_0;
assign ph_qr_V_we0 = 1'b0;
assign ph_qr_V_we1 = 1'b0;
assign ph_rank_V_address0 = ap_const_lv9_0;
assign ph_rank_V_address1 = ap_const_lv9_0;
assign ph_rank_V_ce0 = 1'b0;
assign ph_rank_V_ce1 = 1'b0;
assign ph_rank_V_d0 = ap_const_lv6_0;
assign ph_rank_V_d1 = ap_const_lv6_0;
assign ph_rank_V_we0 = 1'b0;
assign ph_rank_V_we1 = 1'b0;
assign ph_zone_0_0_V = extLd_fu_61061_p1;
assign ph_zone_0_1_V = ph_zone_t_0_1_V_fu_24842;
assign ph_zone_0_2_V = ph_zone_t_0_2_V_fu_24846;
assign ph_zone_0_3_V = ph_zone_t_0_3_V_fu_24850;
assign ph_zone_0_4_V = ph_zone_t_0_4_V_fu_24854;
assign ph_zone_1_0_V = extLd1_fu_61105_p1;
assign ph_zone_1_1_V = ph_zone_t_1_1_V_fu_24862;
assign ph_zone_1_2_V = ph_zone_t_1_2_V_fu_24866;
assign ph_zone_1_3_V = ph_zone_t_1_3_V_fu_24870;
assign ph_zone_1_4_V = ph_zone_t_1_4_V_fu_24874;
assign ph_zone_2_0_V = extLd2_fu_61149_p1;
assign ph_zone_2_1_V = ph_zone_t_2_1_V_fu_24882;
assign ph_zone_2_2_V = ph_zone_t_2_2_V_fu_24886;
assign ph_zone_2_3_V = ph_zone_t_2_3_V_fu_24890;
assign ph_zone_2_4_V = ph_zone_t_2_4_V_fu_24894;
assign ph_zone_3_0_V = extLd3_fu_61193_p1;
assign ph_zone_3_1_V = ph_zone_t_3_1_V_fu_24902;
assign ph_zone_3_2_V = ph_zone_t_3_2_V_fu_24906;
assign ph_zone_3_3_V = ph_zone_t_3_3_V_fu_24910;
assign ph_zone_3_4_V = extLd4_fu_61229_p1;
assign ph_zone_t_0_0_V_fu_24838 = 1'b0;
assign ph_zone_t_1_0_V_fu_24858 = 1'b0;
assign ph_zone_t_2_0_V_fu_24878 = 1'b0;
assign ph_zone_t_3_0_V_fu_24898 = 1'b0;
assign ph_zone_t_3_4_V_fu_24914 = 1'b0;
assign phi_V_address0 = ap_const_lv4_0;
assign phi_V_address1 = ap_const_lv4_0;
assign phi_V_ce0 = 1'b0;
assign phi_V_ce1 = 1'b0;
assign phi_V_d0 = ap_const_lv12_0;
assign phi_V_d1 = ap_const_lv12_0;
assign phi_V_we0 = 1'b0;
assign phi_V_we1 = 1'b0;
assign phzvl_V_address0 = ap_const_lv6_0;
assign phzvl_V_address1 = ap_const_lv6_0;
assign phzvl_V_ce0 = 1'b0;
assign phzvl_V_ce1 = 1'b0;
assign phzvl_V_d0 = ap_const_lv3_0;
assign phzvl_V_d1 = ap_const_lv3_0;
assign phzvl_V_we0 = 1'b0;
assign phzvl_V_we1 = 1'b0;
assign pps_cs_V_address0 = ap_const_lv2_0;
assign pps_cs_V_address1 = ap_const_lv2_0;
assign pps_cs_V_ce0 = 1'b0;
assign pps_cs_V_ce1 = 1'b0;
assign pps_cs_V_d0 = ap_const_lv5_0;
assign pps_cs_V_d1 = ap_const_lv5_0;
assign pps_cs_V_we0 = 1'b0;
assign pps_cs_V_we1 = 1'b0;
assign ptlut_addr_0_V = grp_sp_ptlut_address_fu_54138_ap_return_11;
assign ptlut_addr_1_V = grp_sp_ptlut_address_fu_54138_ap_return_12;
assign ptlut_addr_2_V = grp_sp_ptlut_address_fu_54138_ap_return_13;
assign ptlut_addr_val_V = grp_sp_ptlut_address_fu_54138_ap_return_0;
assign ptlut_cs_0_V = grp_sp_ptlut_address_fu_54138_ap_return_2;
assign ptlut_cs_1_V = grp_sp_ptlut_address_fu_54138_ap_return_3;
assign ptlut_cs_2_V = grp_sp_ptlut_address_fu_54138_ap_return_4;
assign rank_V_address0 = ap_const_lv4_0;
assign rank_V_address1 = ap_const_lv4_0;
assign rank_V_ce0 = 1'b0;
assign rank_V_ce1 = 1'b0;
assign rank_V_d0 = ap_const_lv7_0;
assign rank_V_d1 = ap_const_lv7_0;
assign rank_V_we0 = 1'b0;
assign rank_V_we1 = 1'b0;
assign si_V_address0 = ap_const_lv4_0;
assign si_V_address1 = ap_const_lv4_0;
assign si_V_ce0 = 1'b0;
assign si_V_ce1 = 1'b0;
assign si_V_d0 = ap_const_lv4_0;
assign si_V_d1 = ap_const_lv4_0;
assign si_V_we0 = 1'b0;
assign si_V_we1 = 1'b0;
assign sign_ph_V_address0 = ap_const_lv4_0;
assign sign_ph_V_address1 = ap_const_lv4_0;
assign sign_ph_V_ce0 = 1'b0;
assign sign_ph_V_ce1 = 1'b0;
assign sign_ph_V_d0 = ap_const_lv6_0;
assign sign_ph_V_d1 = ap_const_lv6_0;
assign sign_ph_V_we0 = 1'b0;
assign sign_ph_V_we1 = 1'b0;
assign sign_th_V_address0 = ap_const_lv4_0;
assign sign_th_V_address1 = ap_const_lv4_0;
assign sign_th_V_ce0 = 1'b0;
assign sign_th_V_ce1 = 1'b0;
assign sign_th_V_d0 = ap_const_lv6_0;
assign sign_th_V_d1 = ap_const_lv6_0;
assign sign_th_V_we0 = 1'b0;
assign sign_th_V_we1 = 1'b0;
assign sir_V_address0 = ap_const_lv4_0;
assign sir_V_address1 = ap_const_lv4_0;
assign sir_V_ce0 = 1'b0;
assign sir_V_ce1 = 1'b0;
assign sir_V_d0 = ap_const_lv4_0;
assign sir_V_d1 = ap_const_lv4_0;
assign sir_V_we0 = 1'b0;
assign sir_V_we1 = 1'b0;
assign th11_V_address0 = ap_const_lv5_0;
assign th11_V_address1 = ap_const_lv5_0;
assign th11_V_ce0 = 1'b0;
assign th11_V_ce1 = 1'b0;
assign th11_V_d0 = ap_const_lv7_0;
assign th11_V_d1 = ap_const_lv7_0;
assign th11_V_we0 = 1'b0;
assign th11_V_we1 = 1'b0;
assign th_V_address0 = ap_const_lv7_0;
assign th_V_address1 = ap_const_lv7_0;
assign th_V_ce0 = 1'b0;
assign th_V_ce1 = 1'b0;
assign th_V_d0 = ap_const_lv7_0;
assign th_V_d1 = ap_const_lv7_0;
assign th_V_we0 = 1'b0;
assign th_V_we1 = 1'b0;
assign th_hit_V_address0 = ap_const_lv6_0;
assign th_hit_V_address1 = ap_const_lv6_0;
assign th_hit_V_ce0 = 1'b0;
assign th_hit_V_ce1 = 1'b0;
assign th_hit_V_d0 = ap_const_lv64_0;
assign th_hit_V_d1 = ap_const_lv64_0;
assign th_hit_V_we0 = 1'b0;
assign th_hit_V_we1 = 1'b0;
assign th_match11_V_address0 = ap_const_lv5_0;
assign th_match11_V_address1 = ap_const_lv5_0;
assign th_match11_V_ce0 = 1'b0;
assign th_match11_V_ce1 = 1'b0;
assign th_match11_V_d0 = ap_const_lv7_0;
assign th_match11_V_d1 = ap_const_lv7_0;
assign th_match11_V_we0 = 1'b0;
assign th_match11_V_we1 = 1'b0;
assign th_match_V_address0 = ap_const_lv8_0;
assign th_match_V_address1 = ap_const_lv8_0;
assign th_match_V_ce0 = 1'b0;
assign th_match_V_ce1 = 1'b0;
assign th_match_V_d0 = ap_const_lv7_0;
assign th_match_V_d1 = ap_const_lv7_0;
assign th_match_V_we0 = 1'b0;
assign th_match_V_we1 = 1'b0;
assign theta_V_address0 = ap_const_lv4_0;
assign theta_V_address1 = ap_const_lv4_0;
assign theta_V_ce0 = 1'b0;
assign theta_V_ce1 = 1'b0;
assign theta_V_d0 = ap_const_lv7_0;
assign theta_V_d1 = ap_const_lv7_0;
assign theta_V_we0 = 1'b0;
assign theta_V_we1 = 1'b0;
assign tmp_146_fu_54267_p1 = sel_V[1:0];
assign vi_V_address0 = ap_const_lv6_0;
assign vi_V_address1 = ap_const_lv6_0;
assign vi_V_ce0 = 1'b0;
assign vi_V_ce1 = 1'b0;
assign vi_V_d0 = ap_const_lv2_0;
assign vi_V_d1 = ap_const_lv2_0;
assign vi_V_we0 = 1'b0;
assign vi_V_we1 = 1'b0;
assign vir_V_address0 = ap_const_lv6_0;
assign vir_V_address1 = ap_const_lv6_0;
assign vir_V_ce0 = 1'b0;
assign vir_V_ce1 = 1'b0;
assign vir_V_d0 = ap_const_lv2_0;
assign vir_V_d1 = ap_const_lv2_0;
assign vir_V_we0 = 1'b0;
assign vir_V_we1 = 1'b0;
assign vl_V_address0 = ap_const_lv6_0;
assign vl_V_address1 = ap_const_lv6_0;
assign vl_V_ce0 = 1'b0;
assign vl_V_ce1 = 1'b0;
assign vl_V_d0 = ap_const_lv2_0;
assign vl_V_d1 = ap_const_lv2_0;
assign vl_V_we0 = 1'b0;
assign vl_V_we1 = 1'b0;
endmodule //sp
|
// Generated by DDR3 High Performance Controller 10.0 [Altera, IP Toolbench 1.3.0 Build 262]
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
// Copyright (C) 1991-2011 Altera Corporation
// Any megafunction design, and related net list (encrypted or decrypted),
// support information, device programming or simulation file, and any other
// associated documentation or information provided by Altera or a partner
// under Altera's Megafunction Partnership Program may be used only to
// program PLD devices (but not masked PLD devices) from Altera. Any other
// use of such megafunction design, net list, support information, device
// programming or simulation file, or any other related documentation or
// information is prohibited for any other purpose, including, but not
// limited to modification, reverse engineering, de-compiling, or use with
// any other silicon devices, unless such use is explicitly licensed under
// a separate agreement with Altera or a megafunction partner. Title to
// the intellectual property, including patents, copyrights, trademarks,
// trade secrets, or maskworks, embodied in any such megafunction design,
// net list, support information, device programming or simulation file, or
// any other related documentation or information provided by Altera or a
// megafunction partner, remains with Altera, the megafunction partner, or
// their respective licensors. No other licenses, including any licenses
// needed under any third party's intellectual property, are provided herein.
module ddr3_int (
local_address,
local_write_req,
local_read_req,
local_burstbegin,
local_wdata,
local_be,
local_size,
global_reset_n,
pll_ref_clk,
soft_reset_n,
local_ready,
local_rdata,
local_rdata_valid,
reset_request_n,
mem_odt,
mem_cs_n,
mem_cke,
mem_addr,
mem_ba,
mem_ras_n,
mem_cas_n,
mem_we_n,
mem_dm,
local_refresh_ack,
local_wdata_req,
local_init_done,
reset_phy_clk_n,
mem_reset_n,
dll_reference_clk,
dqs_delay_ctrl_export,
phy_clk,
aux_full_rate_clk,
aux_half_rate_clk,
mem_clk,
mem_clk_n,
mem_dq,
mem_dqs,
mem_dqsn);
input [24:0] local_address;
input local_write_req;
input local_read_req;
input local_burstbegin;
input [127:0] local_wdata;
input [15:0] local_be;
input [5:0] local_size;
input global_reset_n;
input pll_ref_clk;
input soft_reset_n;
output local_ready;
output [127:0] local_rdata;
output local_rdata_valid;
output reset_request_n;
output [0:0] mem_odt;
output [0:0] mem_cs_n;
output [0:0] mem_cke;
output [13:0] mem_addr;
output [2:0] mem_ba;
output mem_ras_n;
output mem_cas_n;
output mem_we_n;
output [3:0] mem_dm;
output local_refresh_ack;
output local_wdata_req;
output local_init_done;
output reset_phy_clk_n;
output mem_reset_n;
output dll_reference_clk;
output [5:0] dqs_delay_ctrl_export;
output phy_clk;
output aux_full_rate_clk;
output aux_half_rate_clk;
inout [0:0] mem_clk;
inout [0:0] mem_clk_n;
inout [31:0] mem_dq;
inout [3:0] mem_dqs;
inout [3:0] mem_dqsn;
endmodule
|
/*
* Copyright 2013-2016 Colin Weltin-Wu ([email protected])
* UC San Diego Integrated Signal Processing Group
*
* Licensed under GNU General Public License 3.0 or later.
* Some rights reserved. See LICENSE.
*
* reg_slice.v
*
* General purpose register bank. For correct operation, this block requires
* a running clock on i_clk at all times.
*
* i_ena high defines "normal mode", and the data on vi_regs appears at
* vo_regs on each rising edge of i_clk. The vio_tbus is tristated.
*
* In normal mode, the signals i_step and i_wr are ignored. Bringing i_rd
* high will cause a sample of the data in the register to appear on vio_tbus.
* This sample will be taken on the next rising edge if i_clk after i_rd
* goes high. As long as i_rd is held high, the data which was initially
* sampled will continue to appear on vio_tbus. One period after data appears
* on vio_tbus, the signal o_success will go high, indicating that vio_tbus
* can be read. This will stay high for 1.5-2 periods after i_rd goes low.
*
* i_ena low defines "test mode". In this mode, the register clock is
* synchronously disabled, and the register will retain the last value.
* In test mode, i_rd behaves the same as in normal mode. If i_wr goes
* high, the value on vio_tbus (driven externally) will be latched into
* the register 1-1.5 periods after i_wr goes high. 2-2.5 periods after
* i_wr goes high, o_success will go high, indicating the data was latched.
* This will stay high 2.5-3 periods after i_wr goes low.
*
* In test mode, i_step can also be used to allow the register to receive
* a single rising edge. The register will latch vi_regs identically to
* normal operation, hence this is a method to single-step the clock.
* o_success has a similar behavior where it goes high 1.5-2 periods after
* i_step goes high, indicating that the register was cycled.
*
* It is important that only one of the signals i_rd, i_wr, and i_step are
* active at a time. Having more than one active at a time causes bus
* contention and is undefined. it is also important to have AT LEAST 6
* periods between when one signal becomes inactive and another becomes
* active.
*
*/
module reg_slice (/*AUTOARG*/
// Outputs
vo_regs,
// Inouts
io_success, vio_tbus,
// Inputs
i_clk, i_rstb, i_ena, vi_regs, i_step, i_rd, i_wr
);
parameter DWIDTH = 16; // Register size
input i_clk; // Master clock
input i_rstb; // Master reset
input i_ena; // Asynchronous enable signal
input [DWIDTH-1:0] vi_regs; // Data to register
output [DWIDTH-1:0] vo_regs; // Data in register
input i_step; // Manually step the clock
input i_rd; // Put register data on test bus
input i_wr; // Load data on test bus into register
inout io_success; // Indicates a successful transaction
inout [DWIDTH-1:0] vio_tbus;
// Synchronize the ena, rd, wr and step signals
wire ena_sync, rd_sync, wr_sync, step_sync;
negedge_sync ena_synchro(.i_clk(i_clk), .i_async(i_ena),
.o_sync(ena_sync));
negedge_sync rd_synchro(.i_clk(i_clk), .i_async(i_rd),
.o_sync(rd_sync));
negedge_sync wr_synchro(.i_clk(i_clk), .i_async(i_wr),
.o_sync(wr_sync));
negedge_sync step_synchro(.i_clk(i_clk), .i_async(i_step),
.o_sync(step_sync));
/*
* Generate the clock to the main register. When enabled, this clock
* is simply i_clk. When the register is disabled, the register is
* clocked by clk_pulse, which is either the write or step clock.
*/
wire clk_pulse;
wire clk_regs = ena_sync ? i_clk : clk_pulse;
reg r_wr_prev, r_wr_pprev, r_step_prev;
wire clk_pulse_wr, clk_pulse_step;
always @( posedge i_clk or negedge i_rstb ) begin : main_clk_reg
if ( !i_rstb ) begin
r_wr_prev <= 0;
r_wr_pprev <= 0;
r_step_prev <= 0;
end
else begin
r_wr_prev <= wr_sync;
r_wr_pprev <= r_wr_prev;
r_step_prev <= step_sync;
end
end // block: main_clk_reg
assign clk_pulse_wr = r_wr_prev && !r_wr_pprev;
assign clk_pulse_step = step_sync && !r_step_prev;
assign clk_pulse = wr_sync ? clk_pulse_wr : clk_pulse_step;
/*
* Generate clock to load the shadow register. This is a pulse which
* rises on the falling edge of i_clk, and lasts half an i_clk period.
* This is to ensure that there is no race condition between the Q output
* of the main register (changes on the rising edge of i_clk).
*/
reg r_rd_prev;
wire clk_pulse_rd;
always @( posedge i_clk or negedge i_rstb ) begin : shadow_clk_reg
if ( !i_rstb )
r_rd_prev <= 0;
else
r_rd_prev <= rd_sync;
end
assign clk_pulse_rd = rd_sync && !r_rd_prev;
reg [DWIDTH-1:0] rv_shadow;
always @( posedge clk_pulse_rd or negedge i_rstb ) begin : shadow_reg
if ( !i_rstb )
rv_shadow <= 0;
else
rv_shadow <= vo_regs;
end
assign vio_tbus = (rd_sync && i_rd) ? rv_shadow : {DWIDTH{1'bz}};
/*
* Main register file. Input is v_regs_pre, which is multiplexed from
* either the normal input when enabled, or the test bus when disabled.
*/
reg [DWIDTH-1:0] vo_regs;
wire [DWIDTH-1:0] v_regs_pre;
assign v_regs_pre = ( !ena_sync && wr_sync ) ? vio_tbus : vi_regs;
always @( posedge clk_regs or negedge i_rstb ) begin : main_reg
if ( !i_rstb )
vo_regs <= 0;
else
vo_regs <= v_regs_pre;
end
/*
* Generate the handshaking signal back to the register interface state
* machine, indicating that the current action (rd, wr, step) completed
*/
wire pre_io_success = r_rd_prev || ( !ena_sync && r_wr_pprev );
assign io_success = ( i_rd || i_wr ) ? pre_io_success : 1'bz;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: RIT
// Engineer: Cody Cziesler and Nick Desaulniers
//
// Create Date: 11:50:14 04/07/2011
// Design Name: write_back
// Module Name: write_back
// Project Name: omicon
// Target Devices: Xilinx Spartan-3E
// Tool versions:
// Description: The write back stage of the pipelined cpu
//
// Revision 0.01 - File Created
// Revision 1.00 - Complete, untested
// Revision 2.00 - Renamed outputs for ID (CRC)
// Revision 3.00 - Tested (CRC)
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module write_back(
input [15:0] m_alu_result,
input [15:0] m_dm_dout,
input [2:0] m_reg_waddr,
input cu_reg_data_loc,
input cu_reg_load,
output [15:0] wb_reg_wdata,
output wb_reg_wea,
output [2:0] wb_reg_waddr
);
// Mux for getting data from memory or the ALU
// if( cu_reg_data_loc )
// wb_reg_din <= m_dm_dout;
// else
// wb_reg_din <= m_alu_result;
assign wb_reg_wdata = cu_reg_data_loc ? m_dm_dout : m_alu_result;
assign wb_reg_wea = cu_reg_load;
assign wb_reg_waddr = m_reg_waddr;
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_dmac_burst_memory #(
parameter DATA_WIDTH_SRC = 64,
parameter DATA_WIDTH_DEST = 64,
parameter ID_WIDTH = 3,
parameter MAX_BYTES_PER_BURST = 128,
parameter ASYNC_CLK = 1,
parameter BYTES_PER_BEAT_WIDTH_SRC = $clog2(DATA_WIDTH_SRC/8),
parameter BYTES_PER_BURST_WIDTH = $clog2(MAX_BYTES_PER_BURST),
parameter ENABLE_DIAGNOSTICS_IF = 0
) (
input src_clk,
input src_reset,
input src_data_valid,
input [DATA_WIDTH_SRC-1:0] src_data,
input src_data_last,
input [BYTES_PER_BEAT_WIDTH_SRC-1:0] src_data_valid_bytes,
input src_data_partial_burst,
output [ID_WIDTH-1:0] src_data_request_id,
input dest_clk,
input dest_reset,
output dest_data_valid,
input dest_data_ready,
output [DATA_WIDTH_DEST-1:0] dest_data,
output dest_data_last,
output [BYTES_PER_BURST_WIDTH-1:0] dest_burst_info_length,
output dest_burst_info_partial,
output [ID_WIDTH-1:0] dest_burst_info_id,
output reg dest_burst_info_write = 1'b0,
output [ID_WIDTH-1:0] dest_request_id,
input [ID_WIDTH-1:0] dest_data_request_id,
output [ID_WIDTH-1:0] dest_data_response_id,
// Diagnostics interface
output [7:0] dest_diag_level_bursts
);
localparam DATA_WIDTH = DATA_WIDTH_SRC > DATA_WIDTH_DEST ?
DATA_WIDTH_SRC : DATA_WIDTH_DEST;
/* A burst can have up to 256 beats */
localparam BURST_LEN = MAX_BYTES_PER_BURST / (DATA_WIDTH / 8);
localparam BURST_LEN_WIDTH = BURST_LEN > 128 ? 8 :
BURST_LEN > 64 ? 7 :
BURST_LEN > 32 ? 6 :
BURST_LEN > 16 ? 5 :
BURST_LEN > 8 ? 4 :
BURST_LEN > 4 ? 3 :
BURST_LEN > 2 ? 2 : 1;
localparam ADDRESS_WIDTH = BURST_LEN_WIDTH + ID_WIDTH - 1;
localparam AUX_FIFO_SIZE = 2**(ID_WIDTH-1);
localparam DEST_SRC_RATIO = DATA_WIDTH_DEST/DATA_WIDTH_SRC;
localparam DEST_SRC_RATIO_WIDTH = DEST_SRC_RATIO > 64 ? 7 :
DEST_SRC_RATIO > 32 ? 6 :
DEST_SRC_RATIO > 16 ? 5 :
DEST_SRC_RATIO > 8 ? 4 :
DEST_SRC_RATIO > 4 ? 3 :
DEST_SRC_RATIO > 2 ? 2 :
DEST_SRC_RATIO > 1 ? 1 : 0;
/*
* The burst memory is separated into 2**(ID_WIDTH-1) segments. Each segment can
* hold up to BURST_LEN beats. The addresses that are used to access the memory
* are split into two parts. The MSBs index the segment and the LSBs index a
* beat in a specific segment.
*
* src_id and dest_id are used to index the segment of the burst memory on the
* write and read side respectively. The IDs are 1 bit wider than the address of
* the burst memory. So we can't use them directly as an index into the burst
* memory. Since the IDs are gray counted we also can't just leave out the MSB
* like with a binary counter. But XOR-ing the two MSBs of a gray counter gives
* us a gray counter of 1 bit less. Use this to generate the segment index.
* These addresses are captured in the src_id_reduced and dest_id_reduced
* signals.
*
* src_beat_counter and dest_beat_counter are used to index the beat on the
* write and read side respectively. They will be incremented for each beat that
* is written/read. Note that the beat counters are not reset to 0 on the last
* beat of a burst. This means the first beat of a burst might not be stored at
* offset 0 in the segment memory. But this is OK since the beat counter
* increments modulo the segment size and both the write and read side agree on
* the order.
*/
reg [ID_WIDTH-1:0] src_id_next;
reg [ID_WIDTH-1:0] src_id = 'h0;
reg src_id_reduced_msb = 1'b0;
reg [BURST_LEN_WIDTH-1:0] src_beat_counter = 'h00;
reg [ID_WIDTH-1:0] dest_id_next = 'h0;
reg dest_id_reduced_msb_next = 1'b0;
reg dest_id_reduced_msb = 1'b0;
reg [ID_WIDTH-1:0] dest_id = 'h0;
reg [BURST_LEN_WIDTH-1:0] dest_beat_counter = 'h00;
wire [BURST_LEN_WIDTH-1:0] dest_burst_len;
reg dest_valid = 1'b0;
reg dest_mem_data_valid = 1'b0;
reg dest_mem_data_last = 1'b0;
reg [BYTES_PER_BURST_WIDTH+1-1:0] burst_len_mem[0:AUX_FIFO_SIZE-1];
wire [BYTES_PER_BURST_WIDTH+1-1:0] src_burst_len_data;
reg [BYTES_PER_BURST_WIDTH+1-1:0] dest_burst_len_data = 'h00;
wire src_beat;
wire src_last_beat;
wire [ID_WIDTH-1:0] src_dest_id;
wire [ADDRESS_WIDTH-1:0] src_waddr;
wire [ID_WIDTH-2:0] src_id_reduced;
wire src_mem_data_valid;
wire src_mem_data_last;
wire [DATA_WIDTH-1:0] src_mem_data;
wire dest_beat;
wire dest_last_beat;
wire dest_last;
wire [ID_WIDTH-1:0] dest_src_id;
wire [ADDRESS_WIDTH-1:0] dest_raddr;
wire [ID_WIDTH-2:0] dest_id_reduced_next;
wire [ID_WIDTH-1:0] dest_id_next_inc;
wire [ID_WIDTH-2:0] dest_id_reduced;
wire dest_burst_valid;
wire dest_burst_ready;
wire dest_ready;
wire [DATA_WIDTH-1:0] dest_mem_data;
wire dest_mem_data_ready;
`include "inc_id.vh"
generate if (ID_WIDTH >= 3) begin
assign src_id_reduced = {src_id_reduced_msb,src_id[ID_WIDTH-3:0]};
assign dest_id_reduced_next = {dest_id_reduced_msb_next,dest_id_next[ID_WIDTH-3:0]};
assign dest_id_reduced = {dest_id_reduced_msb,dest_id[ID_WIDTH-3:0]};
end else begin
assign src_id_reduced = src_id_reduced_msb;
assign dest_id_reduced_next = dest_id_reduced_msb_next;
assign dest_id_reduced = dest_id_reduced_msb;
end endgenerate
assign src_beat = src_mem_data_valid;
assign src_last_beat = src_beat & src_mem_data_last;
assign src_waddr = {src_id_reduced,src_beat_counter};
assign src_data_request_id = src_dest_id;
always @(*) begin
if (src_last_beat == 1'b1) begin
src_id_next <= inc_id(src_id);
end else begin
src_id_next <= src_id;
end
end
always @(posedge src_clk) begin
if (src_reset == 1'b1) begin
src_id <= 'h00;
src_id_reduced_msb <= 1'b0;
end else begin
src_id <= src_id_next;
src_id_reduced_msb <= ^src_id_next[ID_WIDTH-1-:2];
end
end
always @(posedge src_clk) begin
if (src_reset == 1'b1) begin
src_beat_counter <= 'h00;
end else if (src_beat == 1'b1) begin
src_beat_counter <= src_beat_counter + 1'b1;
end
end
always @(posedge src_clk) begin
if (src_last_beat == 1'b1) begin
burst_len_mem[src_id_reduced] <= src_burst_len_data;
end
end
assign dest_ready = ~dest_mem_data_valid | dest_mem_data_ready;
assign dest_last = dest_beat_counter == dest_burst_len;
assign dest_beat = dest_valid & dest_ready;
assign dest_last_beat = dest_last & dest_beat;
assign dest_raddr = {dest_id_reduced,dest_beat_counter};
assign dest_burst_valid = dest_data_request_id != dest_id_next;
assign dest_burst_ready = ~dest_valid | dest_last_beat;
/*
* The data valid signal for the destination side is asserted if there are one
* or more pending bursts. It is de-asserted if there are no more pending burst
* and it is the last beat of the current burst
*/
always @(posedge dest_clk) begin
if (dest_reset == 1'b1) begin
dest_valid <= 1'b0;
end else if (dest_burst_valid == 1'b1) begin
dest_valid <= 1'b1;
end else if (dest_last_beat == 1'b1) begin
dest_valid <= 1'b0;
end
end
/*
* The output register of the memory creates a extra clock cycle of latency on
* the data path. We need to handle this more the handshaking signals. If data
* is available in the memory it will be available one clock cycle later in the
* output register.
*/
always @(posedge dest_clk) begin
if (dest_reset == 1'b1) begin
dest_mem_data_valid <= 1'b0;
end else if (dest_valid == 1'b1) begin
dest_mem_data_valid <= 1'b1;
end else if (dest_mem_data_ready == 1'b1) begin
dest_mem_data_valid <= 1'b0;
end
end
/*
* This clears dest_data_last after the last beat. Strictly speaking this is not
* necessary if this followed AXI handshaking rules since dest_data_last would
* be qualified by dest_data_valid and it is OK to retain the previous value of
* dest_data_last when dest_data_valid is not asserted. But clearing the signal
* here doesn't cost much and can simplify some of the more congested
* combinatorical logic further up the pipeline since we can assume that
* fifo_last == 1'b1 implies fifo_valid == 1'b1.
*/
always @(posedge dest_clk) begin
if (dest_reset == 1'b1) begin
dest_mem_data_last <= 1'b0;
end else if (dest_beat == 1'b1) begin
dest_mem_data_last <= dest_last;
end else if (dest_mem_data_ready == 1'b1) begin
dest_mem_data_last <= 1'b0;
end
end
assign dest_id_next_inc = inc_id(dest_id_next);
always @(posedge dest_clk) begin
if (dest_reset == 1'b1) begin
dest_id_next <= 'h00;
dest_id_reduced_msb_next <= 1'b0;
end else if (dest_burst_valid == 1'b1 && dest_burst_ready == 1'b1) begin
dest_id_next <= dest_id_next_inc;
dest_id_reduced_msb_next <= ^dest_id_next_inc[ID_WIDTH-1-:2];
end
end
always @(posedge dest_clk) begin
if (dest_burst_valid == 1'b1 && dest_burst_ready == 1'b1) begin
dest_burst_len_data <= burst_len_mem[dest_id_reduced_next];
end
end
always @(posedge dest_clk) begin
if (dest_burst_ready == 1'b1) begin
dest_id <= dest_id_next;
dest_id_reduced_msb <= dest_id_reduced_msb_next;
end
end
always @(posedge dest_clk) begin
if (dest_reset == 1'b1) begin
dest_beat_counter <= 'h00;
end else if (dest_beat == 1'b1) begin
dest_beat_counter <= dest_beat_counter + 1'b1;
end
end
assign dest_burst_info_length = dest_burst_len_data[BYTES_PER_BURST_WIDTH-1:0];
assign dest_burst_info_partial = dest_burst_len_data[BYTES_PER_BURST_WIDTH];
assign dest_burst_info_id = dest_id;
always @(posedge dest_clk) begin
dest_burst_info_write <= (dest_burst_valid == 1'b1 && dest_burst_ready == 1'b1);
end
// If destination is wider track the number of source beats in a destination
// beat in case the stream is not destination width aligned.
generate if (DATA_WIDTH_SRC < DATA_WIDTH_DEST) begin
reg [DEST_SRC_RATIO_WIDTH-1:0] src_num_beats = {DEST_SRC_RATIO_WIDTH{1'b1}};
reg [BYTES_PER_BEAT_WIDTH_SRC-1:0] src_data_valid_bytes_d = 'h00;
reg src_data_partial_burst_d = 'h0;
// This counter will hold the number of source beat in a destination beat
// minus one
always @(posedge src_clk) begin
if (src_mem_data_last == 1'b1 && src_mem_data_valid == 1'b1) begin
if (src_data_valid) begin
src_num_beats <= {DEST_SRC_RATIO_WIDTH{1'b0}};
end else begin
src_num_beats <= {DEST_SRC_RATIO_WIDTH{1'b1}};
end
end else if (src_data_valid) begin
src_num_beats <= src_num_beats + 1'b1;
end
end
// Compensate the delay through the resize block
always @(posedge src_clk) begin
if (src_data_valid == 1'b1) begin
src_data_valid_bytes_d <= src_data_valid_bytes;
src_data_partial_burst_d <= src_data_partial_burst;
end
end
assign src_burst_len_data = {src_data_partial_burst_d,
src_beat_counter,
src_num_beats,
src_data_valid_bytes_d};
end else begin
assign src_burst_len_data = {src_data_partial_burst,
src_beat_counter,
src_data_valid_bytes};
end
endgenerate
assign dest_burst_len = dest_burst_len_data[BYTES_PER_BURST_WIDTH-1 -: BURST_LEN_WIDTH];
axi_dmac_resize_src #(
.DATA_WIDTH_SRC (DATA_WIDTH_SRC),
.DATA_WIDTH_MEM (DATA_WIDTH)
) i_resize_src (
.clk (src_clk),
.reset (src_reset),
.src_data_valid (src_data_valid),
.src_data (src_data),
.src_data_last (src_data_last),
.mem_data_valid (src_mem_data_valid),
.mem_data (src_mem_data),
.mem_data_last (src_mem_data_last)
);
ad_mem #(
.DATA_WIDTH (DATA_WIDTH),
.ADDRESS_WIDTH (ADDRESS_WIDTH)
) i_mem (
.clka (src_clk),
.wea (src_beat),
.addra (src_waddr),
.dina (src_mem_data),
.clkb (dest_clk),
.reb (dest_beat),
.addrb (dest_raddr),
.doutb (dest_mem_data)
);
axi_dmac_resize_dest #(
.DATA_WIDTH_DEST (DATA_WIDTH_DEST),
.DATA_WIDTH_MEM (DATA_WIDTH)
) i_resize_dest (
.clk (dest_clk),
.reset (dest_reset),
.mem_data_valid (dest_mem_data_valid),
.mem_data_ready (dest_mem_data_ready),
.mem_data (dest_mem_data),
.mem_data_last (dest_mem_data_last),
.dest_data_valid (dest_data_valid),
.dest_data_ready (dest_data_ready),
.dest_data (dest_data),
.dest_data_last (dest_data_last)
);
sync_bits #(
.NUM_OF_BITS (ID_WIDTH),
.ASYNC_CLK (ASYNC_CLK)
) i_dest_sync_id (
.in (src_id),
.out_clk (dest_clk),
.out_resetn (1'b1),
.out (dest_src_id)
);
sync_bits #(
.NUM_OF_BITS (ID_WIDTH),
.ASYNC_CLK (ASYNC_CLK)
) i_src_sync_id (
.in (dest_id),
.out_clk (src_clk),
.out_resetn (1'b1),
.out (src_dest_id)
);
assign dest_request_id = dest_src_id;
assign dest_data_response_id = dest_id;
generate if (ENABLE_DIAGNOSTICS_IF == 1) begin
reg [ID_WIDTH-1:0] _dest_diag_level_bursts = 'h0;
// calculate buffer fullness in bursts
always @(posedge dest_clk) begin
if (dest_reset == 1'b1) begin
_dest_diag_level_bursts <= 'h0;
end else begin
_dest_diag_level_bursts <= g2b(dest_src_id) - g2b(dest_id);
end
end
assign dest_diag_level_bursts = {{{8-ID_WIDTH}{1'b0}},_dest_diag_level_bursts};
end else begin
assign dest_diag_level_bursts = 'h0;
end
endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A2111O_2_V
`define SKY130_FD_SC_HD__A2111O_2_V
/**
* a2111o: 2-input AND into first input of 4-input OR.
*
* X = ((A1 & A2) | B1 | C1 | D1)
*
* Verilog wrapper for a2111o with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__a2111o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a2111o_2 (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a2111o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a2111o_2 (
X ,
A1,
A2,
B1,
C1,
D1
);
output X ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a2111o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__A2111O_2_V
|
//-----------------------------------------------------------------------------
//-- Baudrate generator
//-- It generates a square signal, with a frequency for communicating at the
//-- given baudrate
//-- The output is set to 1 only during one clock cycle. The rest of the
// time is 0
//-- Once enabled, the pulse is generated just in the middle of the period
//-- This is necessary for the implementation of the receptor
//------------------------------------------------------------------------------
//-- (c) Juan Gonzalez (obijuan)
//-----------------------------------------------------------------------------
//-- GPL license
//-----------------------------------------------------------------------------
`include "baudgen.vh"
//------------------------------------------------------------------------------
//-- baudgen module
//--
//-- INPUTS:
//-- -clk: System clock (12 MHZ in the iceStick board)
//-- -clk_ena: clock enable:
//-- 1. Normal working: The squeare signal is generated
//-- 0: stoped. Output always 0
//-- OUTPUTS:
//-- - clk_out: Output signal. Pulse width: 1 clock cycle.
//-- Output not registered
//-- It tells the uart_rx when to sample the next bit
//-- __ __
//-- _____| |________________________________________| |_____________________
//-- | -> <- 1 clock cycle |
//-- <------- Period ------------------------>
//--
//------------------------------------------------------------------------------
module baudgen_rx #(
parameter BAUDRATE = `B115200 //-- Default baudrate
)(
input wire clk, //-- System clock
input wire clk_ena, //-- Clock enable
output wire clk_out //-- Bitrate Clock output
);
//-- Number of bits needed for storing the baudrate divisor
localparam N = $clog2(BAUDRATE);
//-- Value for generating the pulse in the middle of the period
localparam M2 = (BAUDRATE >> 1);
//-- Counter for implementing the divisor (it is a BAUDRATE module counter)
//-- (when BAUDRATE is reached, it start again from 0)
reg [N-1:0] divcounter = 0;
//-- Contador módulo M
always @(posedge clk)
if (clk_ena)
//-- Normal working: counting. When the maximum count is reached, it starts from 0
divcounter <= (divcounter == BAUDRATE - 1) ? 0 : divcounter + 1;
else
//-- Counter fixed to its maximum value
//-- When it is resumed it start from 0
divcounter <= BAUDRATE - 1;
//-- The output is 1 when the counter is in the middle of the period, if clk_ena is active
//-- It is 1 only for one system clock cycle
assign clk_out = (divcounter == M2) ? clk_ena : 0;
endmodule
|
/*******************************************************************************
* Module: simul_fifo
* Date:2014-04-06
* Author: Andrey Filippov
* Description: simple fifo for simulation
*
* Copyright (c) 2014 Elphel, Inc.
* simul_fifo.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* simul_fifo.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*******************************************************************************/
`timescale 1ns/1ps
module simul_fifo
#(
parameter integer WIDTH= 32, // total number of output bits
parameter integer DEPTH= 64, // maximal number of words in FIFO
// parameter OUT_DELAY = 3.5,
parameter integer FIFO_DEPTH=DEPTH+1
// parameter integer DATA_2DEPTH=(1<<DATA_DEPTH)-1
)(
input clk,
input reset,
input [WIDTH-1:0] data_in,
input load,
output input_ready,
output [WIDTH-1:0] data_out,
output valid,
input ready);
reg [WIDTH-1:0] fifo [0:FIFO_DEPTH-1];
integer in_address;
integer out_address;
integer count;
assign data_out= fifo[out_address];
assign valid= count!=0;
assign input_ready= count<DEPTH;
always @ (posedge clk or posedge reset) begin
if (reset) in_address <= 0;
else if (load) in_address <= (in_address==(FIFO_DEPTH-1))?0:in_address+1;
if (reset) out_address <= 0;
else if (valid && ready) out_address <= (out_address==(FIFO_DEPTH-1))?0:out_address+1;
if (reset) count <= 0;
else if (!(valid && ready) && load) count <= count+1;
else if (valid && ready && !load) count <= count-1;
end
always @ (posedge clk) begin
if (load) fifo[in_address] <= data_in;
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:48:14 10/06/2016
// Design Name:
// Module Name: mouse_ps2
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module mouse_ps2(
input wire clk, reset,
inout wire ps2d, ps2c,
output wire [9:0] mouse_x,
output wire [8:0] mouse_y,
//output wire [8:0] xm, ym,
output wire [2:0] btnm,
output reg m_done_tick
);
// constant declaration
localparam STRM=8'hf4; // stream command F4
// symbolic state declaration
localparam [2:0]
init1 = 3'b000,
init2 = 3'b001,
init3 = 3'b010,
packl = 3'b011,
pack2 = 3'b100,
pack3 = 3'b101,
done = 3'b110;
// signal declaration
reg [2:0] state_reg , state_next;
wire [7:0] rx_data;
reg wr_ps2;
wire rx_done_tick , tx_done_tick;
reg [8:0] x_reg, y_reg, x_next, y_next;
reg [2:0] btn_reg, btn_next;
// body
// instantiation
ps2_rxtx ps2_unit(
.clk(clk),
.reset(reset),
.wr_ps2(wr_ps2),
.din(STRM),
.dout(rx_data),
.ps2d(ps2d),
.ps2c(ps2c),
.rx_done_tick(rx_done_tick),
.tx_done_tick(tx_done_tick)
);
// body
// FSMD state and data registers
always @ (posedge clk , posedge reset)
begin
if (reset)
begin
state_reg <= init1;
x_reg <= 0;
y_reg <= 0;
btn_reg <= 0;
end
else
begin
state_reg <= state_next;
x_reg <= x_next;
y_reg <= y_next;
btn_reg <= btn_next;
end
end
// FSMD next-state logic
always @*
begin
state_next = state_reg;
wr_ps2 = 1'b0;
m_done_tick = 1'b0;
x_next = x_reg;
y_next = y_reg;
btn_next = btn_reg;
case(state_reg)
init1:
begin
wr_ps2 = 1'b1;
state_next = init2;
end
init2: // wait for send to complete
if (tx_done_tick)
state_next = init3;
init3: // wait for acknowledge packet
if (rx_done_tick)
state_next = packl;
packl: // wait for 1st data packet
if (rx_done_tick)
begin
state_next = pack2;
y_next [8] = rx_data[5];
x_next [8] = rx_data[4];
btn_next = rx_data[2:0];
end
pack2: //wait for 2nd data packet
if(rx_done_tick)
begin
state_next = pack3;
x_next [7:0] = rx_data;
end
pack3: //wait for 3rd data packet
if(rx_done_tick)
begin
state_next = done;
y_next [7:0] = rx_data;
end
done:
begin
m_done_tick = 1'b1;
state_next = packl;
end
endcase
end
// Mouse Controller
mouse_controller m_c(
.clk(clk),
.xm(xm),
.ym(ym),
.mouse_x(mouse_x),
.mouse_y(mouse_y)
);
//output
assign xm = x_reg;
assign ym = y_reg;
assign btnm = btn_reg;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NAND4_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__NAND4_PP_BLACKBOX_V
/**
* nand4: 4-input NAND.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__nand4 (
Y ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__NAND4_PP_BLACKBOX_V
|
(** * Equiv: Program Equivalence *)
Require Export Imp.
(** *** Some general advice for working on exercises:
- Most of the Coq proofs we ask you to do are similar to proofs
that we've provided. Before starting to work on the homework
problems, take the time to work through our proofs (both
informally, on paper, and in Coq) and make sure you understand
them in detail. This will save you a lot of time.
- The Coq proofs we're doing now are sufficiently complicated that
it is more or less impossible to complete them simply by random
experimentation or "following your nose." You need to start
with an idea about why the property is true and how the proof is
going to go. The best way to do this is to write out at least a
sketch of an informal proof on paper -- one that intuitively
convinces you of the truth of the theorem -- before starting to
work on the formal one. Alternately, grab a friend and try to
convince them that the theorem is true; then try to formalize
your explanation.
- Use automation to save work! Some of the proofs in this
chapter's exercises are pretty long if you try to write out all
the cases explicitly. *)
(* ####################################################### *)
(** * Behavioral Equivalence *)
(** In the last chapter, we investigated the correctness of a very
simple program transformation: the [optimize_0plus] function. The
programming language we were considering was the first version of
the language of arithmetic expressions -- with no variables -- so
in that setting it was very easy to define what it _means_ for a
program transformation to be correct: it should always yield a
program that evaluates to the same number as the original.
To go further and talk about the correctness of program
transformations in the full Imp language, we need to consider the
role of variables and state. *)
(* ####################################################### *)
(** ** Definitions *)
(** For [aexp]s and [bexp]s with variables, the definition we want is
clear. We say
that two [aexp]s or [bexp]s are _behaviorally equivalent_ if they
evaluate to the same result _in every state_. *)
Definition aequiv (a1 a2 : aexp) : Prop :=
forall (st:state),
aeval st a1 = aeval st a2.
Definition bequiv (b1 b2 : bexp) : Prop :=
forall (st:state),
beval st b1 = beval st b2.
(** For commands, the situation is a little more subtle. We can't
simply say "two commands are behaviorally equivalent if they
evaluate to the same ending state whenever they are started in the
same initial state," because some commands (in some starting
states) don't terminate in any final state at all! What we need
instead is this: two commands are behaviorally equivalent if, for
any given starting state, they either both diverge or both
terminate in the same final state. A compact way to express this
is "if the first one terminates in a particular state then so does
the second, and vice versa." *)
Definition cequiv (c1 c2 : com) : Prop :=
forall (st st' : state),
(c1 / st || st') <-> (c2 / st || st').
(** **** Exercise: 2 stars (equiv_classes) *)
(** Given the following programs, group together those that are
equivalent in [Imp]. For example, if you think programs (a)
through (h) are all equivalent to each other, but not to (i), your
answer should look like this: {a,b,c,d,e,f,g,h} {i}.
(a)
WHILE X > 0 DO
X ::= X + 1
END
(b)
IFB X = 0 THEN
X ::= X + 1;;
Y ::= 1
ELSE
Y ::= 0
FI;;
X ::= X - Y;;
Y ::= 0
(c)
SKIP
(d)
WHILE X <> 0 DO
X ::= X * Y + 1
END
(e)
Y ::= 0
(f)
Y ::= X + 1;;
WHILE X <> Y DO
Y ::= X + 1
END
(g)
WHILE TRUE DO
SKIP
END
(h)
WHILE X <> X DO
X ::= X + 1
END
(i)
WHILE X <> Y DO
X ::= Y + 1
END
(* FILL IN HERE *)
{a} {b} {d} {i}
diverge for all inputs
{f,g}
do nothing
{c,h}
[] *)
(* ####################################################### *)
(** ** Examples *)
(** Here are some simple examples of equivalences of arithmetic
and boolean expressions. *)
Theorem aequiv_example:
aequiv (AMinus (AId X) (AId X)) (ANum 0).
Proof.
intros st. simpl. omega.
Qed.
Theorem bequiv_example:
bequiv (BEq (AMinus (AId X) (AId X)) (ANum 0)) BTrue.
Proof.
intros st. unfold beval.
rewrite aequiv_example. reflexivity.
Qed.
(** For examples of command equivalence, let's start by looking at
some trivial program transformations involving [SKIP]: *)
Theorem skip_left: forall c,
cequiv
(SKIP;; c)
c.
Proof.
(* WORKED IN CLASS *)
intros c st st'.
split; intros H.
Case "->".
inversion H. subst.
inversion H2. subst.
assumption.
Case "<-".
apply E_Seq with st.
apply E_Skip.
assumption.
Qed.
(** **** Exercise: 2 stars (skip_right) *)
(** Prove that adding a SKIP after a command results in an equivalent
program *)
Theorem skip_right: forall c,
cequiv
(c;; SKIP)
c.
Proof.
intros c st st'. split; intros H.
Case "->".
inversion H. subst. inversion H5. subst. assumption.
Case "<-".
apply E_Seq with st'. apply H. apply E_Skip.
Qed.
(** [] *)
(** Similarly, here is a simple transformations that simplifies [IFB]
commands: *)
Theorem IFB_true_simple: forall c1 c2,
cequiv
(IFB BTrue THEN c1 ELSE c2 FI)
c1.
Proof.
intros c1 c2.
split; intros H.
Case "->".
inversion H; subst. assumption. inversion H5.
Case "<-".
apply E_IfTrue. reflexivity. assumption. Qed.
(** Of course, few programmers would be tempted to write a conditional
whose guard is literally [BTrue]. A more interesting case is when
the guard is _equivalent_ to true:
_Theorem_: If [b] is equivalent to [BTrue], then [IFB b THEN c1
ELSE c2 FI] is equivalent to [c1].
_Proof_:
- ([->]) We must show, for all [st] and [st'], that if [IFB b
THEN c1 ELSE c2 FI / st || st'] then [c1 / st || st'].
Proceed by cases on the rules that could possibly have been
used to show [IFB b THEN c1 ELSE c2 FI / st || st'], namely
[E_IfTrue] and [E_IfFalse].
- Suppose the final rule rule in the derivation of [IFB b THEN
c1 ELSE c2 FI / st || st'] was [E_IfTrue]. We then have, by
the premises of [E_IfTrue], that [c1 / st || st']. This is
exactly what we set out to prove.
- On the other hand, suppose the final rule in the derivation
of [IFB b THEN c1 ELSE c2 FI / st || st'] was [E_IfFalse].
We then know that [beval st b = false] and [c2 / st || st'].
Recall that [b] is equivalent to [BTrue], i.e. forall [st],
[beval st b = beval st BTrue]. In particular, this means
that [beval st b = true], since [beval st BTrue = true]. But
this is a contradiction, since [E_IfFalse] requires that
[beval st b = false]. Thus, the final rule could not have
been [E_IfFalse].
- ([<-]) We must show, for all [st] and [st'], that if [c1 / st
|| st'] then [IFB b THEN c1 ELSE c2 FI / st || st'].
Since [b] is equivalent to [BTrue], we know that [beval st b] =
[beval st BTrue] = [true]. Together with the assumption that
[c1 / st || st'], we can apply [E_IfTrue] to derive [IFB b THEN
c1 ELSE c2 FI / st || st']. []
Here is the formal version of this proof: *)
Theorem IFB_true: forall b c1 c2,
bequiv b BTrue ->
cequiv
(IFB b THEN c1 ELSE c2 FI)
c1.
Proof.
intros b c1 c2 Hb.
split; intros H.
Case "->".
inversion H; subst.
SCase "b evaluates to true".
assumption.
SCase "b evaluates to false (contradiction)".
rewrite Hb in H5.
inversion H5.
Case "<-".
apply E_IfTrue; try assumption.
rewrite Hb. reflexivity. Qed.
(** **** Exercise: 2 stars (IFB_false) *)
Theorem IFB_false: forall b c1 c2,
bequiv b BFalse ->
cequiv
(IFB b THEN c1 ELSE c2 FI)
c2.
Proof.
intros b c1 c2 Hb.
split; intros.
Case "->".
inversion H. subst. rewrite Hb in H5. inversion H5. assumption.
Case "<-".
apply E_IfFalse; try assumption. apply Hb.
Qed.
(** [] *)
(** **** Exercise: 3 stars (swap_if_branches) *)
(** Show that we can swap the branches of an IF by negating its
condition *)
Theorem swap_if_branches: forall b e1 e2,
cequiv
(IFB b THEN e1 ELSE e2 FI)
(IFB BNot b THEN e2 ELSE e1 FI).
Proof.
intros. split; intro H.
Case "->".
inversion H; subst.
SCase "true". apply E_IfFalse. simpl. rewrite H5. reflexivity. assumption.
SCase "false". apply E_IfTrue. simpl. rewrite H5. reflexivity. assumption.
Case "<-".
inversion H; subst.
SCase "false". apply E_IfFalse. simpl in H5. apply negb_true_iff in H5. assumption. assumption.
SCase "true". apply E_IfTrue. simpl in H5. apply negb_false_iff in H5. assumption. assumption.
Qed.
(** [] *)
(** For [WHILE] loops, we can give a similar pair of theorems. A loop
whose guard is equivalent to [BFalse] is equivalent to [SKIP],
while a loop whose guard is equivalent to [BTrue] is equivalent to
[WHILE BTrue DO SKIP END] (or any other non-terminating program).
The first of these facts is easy. *)
Theorem WHILE_false : forall b c,
bequiv b BFalse ->
cequiv
(WHILE b DO c END)
SKIP.
Proof.
intros b c Hb. split; intros H.
Case "->".
inversion H; subst.
SCase "E_WhileEnd".
apply E_Skip.
SCase "E_WhileLoop".
rewrite Hb in H2. inversion H2.
Case "<-".
inversion H; subst.
apply E_WhileEnd.
rewrite Hb.
reflexivity. Qed.
(** **** Exercise: 2 stars, advanced, optional (WHILE_false_informal) *)
(** Write an informal proof of [WHILE_false].
(* FILL IN HERE *)
[]
*)
(** To prove the second fact, we need an auxiliary lemma stating that
[WHILE] loops whose guards are equivalent to [BTrue] never
terminate:
_Lemma_: If [b] is equivalent to [BTrue], then it cannot be the
case that [(WHILE b DO c END) / st || st'].
_Proof_: Suppose that [(WHILE b DO c END) / st || st']. We show,
by induction on a derivation of [(WHILE b DO c END) / st || st'],
that this assumption leads to a contradiction.
- Suppose [(WHILE b DO c END) / st || st'] is proved using rule
[E_WhileEnd]. Then by assumption [beval st b = false]. But
this contradicts the assumption that [b] is equivalent to
[BTrue].
- Suppose [(WHILE b DO c END) / st || st'] is proved using rule
[E_WhileLoop]. Then we are given the induction hypothesis
that [(WHILE b DO c END) / st || st'] is contradictory, which
is exactly what we are trying to prove!
- Since these are the only rules that could have been used to
prove [(WHILE b DO c END) / st || st'], the other cases of
the induction are immediately contradictory. [] *)
Lemma WHILE_true_nonterm : forall b c st st',
bequiv b BTrue ->
~( (WHILE b DO c END) / st || st' ).
Proof.
(* WORKED IN CLASS *)
intros b c st st' Hb.
intros H.
remember (WHILE b DO c END) as cw eqn:Heqcw.
ceval_cases (induction H) Case;
(* Most rules don't apply, and we can rule them out
by inversion *)
inversion Heqcw; subst; clear Heqcw.
(* The two interesting cases are the ones for WHILE loops: *)
Case "E_WhileEnd". (* contradictory -- b is always true! *)
unfold bequiv in Hb.
(* [rewrite] is able to instantiate the quantifier in [st] *)
rewrite Hb in H. inversion H.
Case "E_WhileLoop". (* immediate from the IH *)
apply IHceval2. reflexivity. Qed.
(** **** Exercise: 2 stars, optional (WHILE_true_nonterm_informal) *)
(** Explain what the lemma [WHILE_true_nonterm] means in English.
(* FILL IN HERE *)
*)
(** [] *)
(** **** Exercise: 2 stars (WHILE_true) *)
(** Prove the following theorem. _Hint_: You'll want to use
[WHILE_true_nonterm] here. *)
Theorem WHILE_true: forall b c,
bequiv b BTrue ->
cequiv
(WHILE b DO c END)
(WHILE BTrue DO SKIP END).
Proof.
intros. split; intros;
apply WHILE_true_nonterm in H0; inversion H0; try assumption; try constructor.
Qed.
(** [] *)
Theorem loop_unrolling: forall b c,
cequiv
(WHILE b DO c END)
(IFB b THEN (c;; WHILE b DO c END) ELSE SKIP FI).
Proof.
(* WORKED IN CLASS *)
intros b c st st'.
split; intros Hce.
Case "->".
inversion Hce; subst.
SCase "loop doesn't run".
apply E_IfFalse. assumption. apply E_Skip.
SCase "loop runs".
apply E_IfTrue. assumption.
apply E_Seq with (st' := st'0). assumption. assumption.
Case "<-".
inversion Hce; subst.
SCase "loop runs".
inversion H5; subst.
apply E_WhileLoop with (st' := st'0).
assumption. assumption. assumption.
SCase "loop doesn't run".
inversion H5; subst. apply E_WhileEnd. assumption. Qed.
(** **** Exercise: 2 stars, optional (seq_assoc) *)
Theorem seq_assoc : forall c1 c2 c3,
cequiv ((c1;;c2);;c3) (c1;;(c2;;c3)).
Proof.
split; intros H.
Case "->". inversion H. subst. inversion H2. subst.
apply E_Seq with (c2:= c2;; c3) (st':=st'1). assumption.
apply E_Seq with (st':=st'0). assumption. assumption.
Case "<-". inversion H. subst. inversion H5. subst.
apply E_Seq with (st':=st'1).
apply E_Seq with (st':=st'0). assumption. assumption. assumption.
Qed.
(** [] *)
(** ** The Functional Equivalence Axiom *)
(** Finally, let's look at simple equivalences involving assignments.
For example, we might expect to be able to show that [X ::= AId X]
is equivalent to [SKIP]. However, when we try to show it, we get
stuck in an interesting way. *)
Theorem identity_assignment_first_try : forall (X:id),
cequiv (X ::= AId X) SKIP.
Proof.
intros. split; intro H.
Case "->".
inversion H; subst. simpl.
replace (update st X (st X)) with st.
constructor.
(* Stuck... *) Abort.
(** Here we're stuck. The goal looks reasonable, but in fact it is not
provable! If we look back at the set of lemmas we proved about
[update] in the last chapter, we can see that lemma [update_same]
almost does the job, but not quite: it says that the original and
updated states agree at all values, but this is not the same thing
as saying that they are [=] in Coq's sense! *)
(** What is going on here? Recall that our states are just
functions from identifiers to values. For Coq, functions are only
equal when their definitions are syntactically the same, modulo
simplification. (This is the only way we can legally apply the
[refl_equal] constructor of the inductively defined proposition
[eq]!) In practice, for functions built up by repeated uses of the
[update] operation, this means that two functions can be proven
equal only if they were constructed using the _same_ [update]
operations, applied in the same order. In the theorem above, the
sequence of updates on the first parameter [cequiv] is one longer
than for the second parameter, so it is no wonder that the
equality doesn't hold. *)
(** This problem is actually quite general. If we try to prove other
simple facts, such as
cequiv (X ::= X + 1;;
X ::= X + 1)
(X ::= X + 2)
or
cequiv (X ::= 1;; Y ::= 2)
(y ::= 2;; X ::= 1)
we'll get stuck in the same way: we'll have two functions that
behave the same way on all inputs, but cannot be proven to be [eq]
to each other.
The reasoning principle we would like to use in these situations
is called _functional extensionality_:
forall x, f x = g x
-------------------
f = g
Although this principle is not derivable in Coq's built-in logic,
it is safe to add it as an additional _axiom_. *)
Axiom functional_extensionality : forall {X Y: Type} {f g : X -> Y},
(forall (x: X), f x = g x) -> f = g.
(** It can be shown that adding this axiom doesn't introduce any
inconsistencies into Coq. (In this way, it is similar to adding
one of the classical logic axioms, such as [excluded_middle].) *)
(** With the benefit of this axiom we can prove our theorem. *)
Theorem identity_assignment : forall (X:id),
cequiv
(X ::= AId X)
SKIP.
Proof.
intros. split; intro H.
Case "->".
inversion H; subst. simpl.
replace (update st X (st X)) with st.
constructor.
apply functional_extensionality. intro.
rewrite update_same; reflexivity.
Case "<-".
inversion H; subst.
assert (st' = (update st' X (st' X))).
apply functional_extensionality. intro.
rewrite update_same; reflexivity.
rewrite H0 at 2.
constructor. reflexivity.
Qed.
(** **** Exercise: 2 stars (assign_aequiv) *)
Theorem assign_aequiv : forall X e,
aequiv (AId X) e ->
cequiv SKIP (X ::= e).
Proof.
intros. split; intro.
Case "->".
assert (st = update st X (aeval st e)).
apply functional_extensionality. intro. rewrite update_same. reflexivity. apply H.
assert (st = st'). inversion H0. reflexivity. rewrite H2 in H1. rewrite H1. rewrite <- H2.
apply E_Ass. reflexivity.
Case "<-". inversion H0. subst. assert (st = update st X (aeval st e)).
apply functional_extensionality. intro. rewrite update_same. reflexivity. apply H.
rewrite <- H1. apply E_Skip.
Qed.
(** [] *)
(* ####################################################### *)
(** * Properties of Behavioral Equivalence *)
(** We now turn to developing some of the properties of the program
equivalences we have defined. *)
(* ####################################################### *)
(** ** Behavioral Equivalence is an Equivalence *)
(** First, we verify that the equivalences on [aexps], [bexps], and
[com]s really are _equivalences_ -- i.e., that they are reflexive,
symmetric, and transitive. The proofs are all easy. *)
Lemma refl_aequiv : forall (a : aexp), aequiv a a.
Proof.
intros a st. reflexivity. Qed.
Lemma sym_aequiv : forall (a1 a2 : aexp),
aequiv a1 a2 -> aequiv a2 a1.
Proof.
intros a1 a2 H. intros st. symmetry. apply H. Qed.
Lemma trans_aequiv : forall (a1 a2 a3 : aexp),
aequiv a1 a2 -> aequiv a2 a3 -> aequiv a1 a3.
Proof.
unfold aequiv. intros a1 a2 a3 H12 H23 st.
rewrite (H12 st). rewrite (H23 st). reflexivity. Qed.
Lemma refl_bequiv : forall (b : bexp), bequiv b b.
Proof.
unfold bequiv. intros b st. reflexivity. Qed.
Lemma sym_bequiv : forall (b1 b2 : bexp),
bequiv b1 b2 -> bequiv b2 b1.
Proof.
unfold bequiv. intros b1 b2 H. intros st. symmetry. apply H. Qed.
Lemma trans_bequiv : forall (b1 b2 b3 : bexp),
bequiv b1 b2 -> bequiv b2 b3 -> bequiv b1 b3.
Proof.
unfold bequiv. intros b1 b2 b3 H12 H23 st.
rewrite (H12 st). rewrite (H23 st). reflexivity. Qed.
Lemma refl_cequiv : forall (c : com), cequiv c c.
Proof.
unfold cequiv. intros c st st'. apply iff_refl. Qed.
Lemma sym_cequiv : forall (c1 c2 : com),
cequiv c1 c2 -> cequiv c2 c1.
Proof.
unfold cequiv. intros c1 c2 H st st'.
assert (c1 / st || st' <-> c2 / st || st') as H'.
SCase "Proof of assertion". apply H.
apply iff_sym. assumption.
Qed.
Lemma iff_trans : forall (P1 P2 P3 : Prop),
(P1 <-> P2) -> (P2 <-> P3) -> (P1 <-> P3).
Proof.
intros P1 P2 P3 H12 H23.
inversion H12. inversion H23.
split; intros A.
apply H1. apply H. apply A.
apply H0. apply H2. apply A. Qed.
Lemma trans_cequiv : forall (c1 c2 c3 : com),
cequiv c1 c2 -> cequiv c2 c3 -> cequiv c1 c3.
Proof.
unfold cequiv. intros c1 c2 c3 H12 H23 st st'.
apply iff_trans with (c2 / st || st'). apply H12. apply H23. Qed.
(* ######################################################## *)
(** ** Behavioral Equivalence is a Congruence *)
(** Less obviously, behavioral equivalence is also a _congruence_.
That is, the equivalence of two subprograms implies the
equivalence of the larger programs in which they are embedded:
aequiv a1 a1'
-----------------------------
cequiv (i ::= a1) (i ::= a1')
cequiv c1 c1'
cequiv c2 c2'
------------------------
cequiv (c1;;c2) (c1';;c2')
...and so on.
(Note that we are using the inference rule notation here not as
part of a definition, but simply to write down some valid
implications in a readable format. We prove these implications
below.) *)
(** We will see a concrete example of why these congruence
properties are important in the following section (in the proof of
[fold_constants_com_sound]), but the main idea is that they allow
us to replace a small part of a large program with an equivalent
small part and know that the whole large programs are equivalent
_without_ doing an explicit proof about the non-varying parts --
i.e., the "proof burden" of a small change to a large program is
proportional to the size of the change, not the program. *)
Theorem CAss_congruence : forall i a1 a1',
aequiv a1 a1' ->
cequiv (CAss i a1) (CAss i a1').
Proof.
intros i a1 a2 Heqv st st'.
split; intros Hceval.
Case "->".
inversion Hceval. subst. apply E_Ass.
rewrite Heqv. reflexivity.
Case "<-".
inversion Hceval. subst. apply E_Ass.
rewrite Heqv. reflexivity. Qed.
(** The congruence property for loops is a little more interesting,
since it requires induction.
_Theorem_: Equivalence is a congruence for [WHILE] -- that is, if
[b1] is equivalent to [b1'] and [c1] is equivalent to [c1'], then
[WHILE b1 DO c1 END] is equivalent to [WHILE b1' DO c1' END].
_Proof_: Suppose [b1] is equivalent to [b1'] and [c1] is
equivalent to [c1']. We must show, for every [st] and [st'], that
[WHILE b1 DO c1 END / st || st'] iff [WHILE b1' DO c1' END / st
|| st']. We consider the two directions separately.
- ([->]) We show that [WHILE b1 DO c1 END / st || st'] implies
[WHILE b1' DO c1' END / st || st'], by induction on a
derivation of [WHILE b1 DO c1 END / st || st']. The only
nontrivial cases are when the final rule in the derivation is
[E_WhileEnd] or [E_WhileLoop].
- [E_WhileEnd]: In this case, the form of the rule gives us
[beval st b1 = false] and [st = st']. But then, since
[b1] and [b1'] are equivalent, we have [beval st b1' =
false], and [E-WhileEnd] applies, giving us [WHILE b1' DO
c1' END / st || st'], as required.
- [E_WhileLoop]: The form of the rule now gives us [beval st
b1 = true], with [c1 / st || st'0] and [WHILE b1 DO c1
END / st'0 || st'] for some state [st'0], with the
induction hypothesis [WHILE b1' DO c1' END / st'0 ||
st'].
Since [c1] and [c1'] are equivalent, we know that [c1' /
st || st'0]. And since [b1] and [b1'] are equivalent, we
have [beval st b1' = true]. Now [E-WhileLoop] applies,
giving us [WHILE b1' DO c1' END / st || st'], as
required.
- ([<-]) Similar. [] *)
Theorem CWhile_congruence : forall b1 b1' c1 c1',
bequiv b1 b1' -> cequiv c1 c1' ->
cequiv (WHILE b1 DO c1 END) (WHILE b1' DO c1' END).
Proof.
(* WORKED IN CLASS *)
unfold bequiv,cequiv.
intros b1 b1' c1 c1' Hb1e Hc1e st st'.
split; intros Hce.
Case "->".
remember (WHILE b1 DO c1 END) as cwhile eqn:Heqcwhile.
induction Hce; inversion Heqcwhile; subst.
SCase "E_WhileEnd".
apply E_WhileEnd. rewrite <- Hb1e. apply H.
SCase "E_WhileLoop".
apply E_WhileLoop with (st' := st').
SSCase "show loop runs". rewrite <- Hb1e. apply H.
SSCase "body execution".
apply (Hc1e st st'). apply Hce1.
SSCase "subsequent loop execution".
apply IHHce2. reflexivity.
Case "<-".
remember (WHILE b1' DO c1' END) as c'while eqn:Heqc'while.
induction Hce; inversion Heqc'while; subst.
SCase "E_WhileEnd".
apply E_WhileEnd. rewrite -> Hb1e. apply H.
SCase "E_WhileLoop".
apply E_WhileLoop with (st' := st').
SSCase "show loop runs". rewrite -> Hb1e. apply H.
SSCase "body execution".
apply (Hc1e st st'). apply Hce1.
SSCase "subsequent loop execution".
apply IHHce2. reflexivity. Qed.
(** **** Exercise: 3 stars, optional (CSeq_congruence) *)
Theorem CSeq_congruence : forall c1 c1' c2 c2',
cequiv c1 c1' -> cequiv c2 c2' ->
cequiv (c1;;c2) (c1';;c2').
Proof.
intros c1 c1' c2 c2' Hc1equiv Hc2equiv.
split.
Case "->".
intro H. inversion H. subst. apply Hc1equiv in H2. apply Hc2equiv in H5.
apply E_Seq with (st':=st'0). assumption. assumption.
Case "<-".
intro H. inversion H. subst. apply Hc1equiv in H2. apply Hc2equiv in H5.
apply E_Seq with (st':=st'0). assumption. assumption.
Qed.
(** [] *)
(** **** Exercise: 3 stars (CIf_congruence) *)
Theorem CIf_congruence : forall b b' c1 c1' c2 c2',
bequiv b b' -> cequiv c1 c1' -> cequiv c2 c2' ->
cequiv (IFB b THEN c1 ELSE c2 FI) (IFB b' THEN c1' ELSE c2' FI).
Proof.
intros. split.
Case "->". intro Hif. inversion Hif; subst.
SCase "true". unfold bequiv in H. rewrite H in H7. apply E_IfTrue. assumption. apply H0. assumption.
SCase "false". apply E_IfFalse. rewrite <- H. assumption. apply H1. assumption.
Case "<-". intro Hif. inversion Hif; subst.
SCase "true". apply E_IfTrue. rewrite H. assumption. apply H0. assumption.
SCase "false". apply E_IfFalse. rewrite H. assumption. apply H1. assumption.
Qed.
(** [] *)
(** For example, here are two equivalent programs and a proof of their
equivalence... *)
Example congruence_example:
cequiv
(* Program 1: *)
(X ::= ANum 0;;
IFB (BEq (AId X) (ANum 0))
THEN
Y ::= ANum 0
ELSE
Y ::= ANum 42
FI)
(* Program 2: *)
(X ::= ANum 0;;
IFB (BEq (AId X) (ANum 0))
THEN
Y ::= AMinus (AId X) (AId X) (* <--- changed here *)
ELSE
Y ::= ANum 42
FI).
Proof.
apply CSeq_congruence.
apply refl_cequiv.
apply CIf_congruence.
apply refl_bequiv.
apply CAss_congruence. unfold aequiv. simpl.
symmetry. apply minus_diag.
apply refl_cequiv.
Qed.
(* ####################################################### *)
(** * Case Study: Constant Folding *)
(** A _program transformation_ is a function that takes a program
as input and produces some variant of the program as its
output. Compiler optimizations such as constant folding are
a canonical example, but there are many others. *)
(* ####################################################### *)
(** ** Soundness of Program Transformations *)
(** A program transformation is _sound_ if it preserves the
behavior of the original program.
We can define a notion of soundness for translations of
[aexp]s, [bexp]s, and [com]s. *)
Definition atrans_sound (atrans : aexp -> aexp) : Prop :=
forall (a : aexp),
aequiv a (atrans a).
Definition btrans_sound (btrans : bexp -> bexp) : Prop :=
forall (b : bexp),
bequiv b (btrans b).
Definition ctrans_sound (ctrans : com -> com) : Prop :=
forall (c : com),
cequiv c (ctrans c).
(* ######################################################## *)
(** ** The Constant-Folding Transformation *)
(** An expression is _constant_ when it contains no variable
references.
Constant folding is an optimization that finds constant
expressions and replaces them by their values. *)
Fixpoint fold_constants_aexp (a : aexp) : aexp :=
match a with
| ANum n => ANum n
| AId i => AId i
| APlus a1 a2 =>
match (fold_constants_aexp a1, fold_constants_aexp a2) with
| (ANum n1, ANum n2) => ANum (n1 + n2)
| (a1', a2') => APlus a1' a2'
end
| AMinus a1 a2 =>
match (fold_constants_aexp a1, fold_constants_aexp a2) with
| (ANum n1, ANum n2) => ANum (n1 - n2)
| (a1', a2') => AMinus a1' a2'
end
| AMult a1 a2 =>
match (fold_constants_aexp a1, fold_constants_aexp a2) with
| (ANum n1, ANum n2) => ANum (n1 * n2)
| (a1', a2') => AMult a1' a2'
end
end.
Example fold_aexp_ex1 :
fold_constants_aexp
(AMult (APlus (ANum 1) (ANum 2)) (AId X))
= AMult (ANum 3) (AId X).
Proof. reflexivity. Qed.
(** Note that this version of constant folding doesn't eliminate
trivial additions, etc. -- we are focusing attention on a single
optimization for the sake of simplicity. It is not hard to
incorporate other ways of simplifying expressions; the definitions
and proofs just get longer. *)
Example fold_aexp_ex2 :
fold_constants_aexp
(AMinus (AId X) (APlus (AMult (ANum 0) (ANum 6)) (AId Y)))
= AMinus (AId X) (APlus (ANum 0) (AId Y)).
Proof. reflexivity. Qed.
(** Not only can we lift [fold_constants_aexp] to [bexp]s (in the
[BEq] and [BLe] cases), we can also find constant _boolean_
expressions and reduce them in-place. *)
Fixpoint fold_constants_bexp (b : bexp) : bexp :=
match b with
| BTrue => BTrue
| BFalse => BFalse
| BEq a1 a2 =>
match (fold_constants_aexp a1, fold_constants_aexp a2) with
| (ANum n1, ANum n2) => if beq_nat n1 n2 then BTrue else BFalse
| (a1', a2') => BEq a1' a2'
end
| BLe a1 a2 =>
match (fold_constants_aexp a1, fold_constants_aexp a2) with
| (ANum n1, ANum n2) => if ble_nat n1 n2 then BTrue else BFalse
| (a1', a2') => BLe a1' a2'
end
| BNot b1 =>
match (fold_constants_bexp b1) with
| BTrue => BFalse
| BFalse => BTrue
| b1' => BNot b1'
end
| BAnd b1 b2 =>
match (fold_constants_bexp b1, fold_constants_bexp b2) with
| (BTrue, BTrue) => BTrue
| (BTrue, BFalse) => BFalse
| (BFalse, BTrue) => BFalse
| (BFalse, BFalse) => BFalse
| (b1', b2') => BAnd b1' b2'
end
end.
Example fold_bexp_ex1 :
fold_constants_bexp (BAnd BTrue (BNot (BAnd BFalse BTrue)))
= BTrue.
Proof. reflexivity. Qed.
Example fold_bexp_ex2 :
fold_constants_bexp
(BAnd (BEq (AId X) (AId Y))
(BEq (ANum 0)
(AMinus (ANum 2) (APlus (ANum 1) (ANum 1)))))
= BAnd (BEq (AId X) (AId Y)) BTrue.
Proof. reflexivity. Qed.
(** To fold constants in a command, we apply the appropriate folding
functions on all embedded expressions. *)
Fixpoint fold_constants_com (c : com) : com :=
match c with
| SKIP =>
SKIP
| i ::= a =>
CAss i (fold_constants_aexp a)
| c1 ;; c2 =>
(fold_constants_com c1) ;; (fold_constants_com c2)
| IFB b THEN c1 ELSE c2 FI =>
match fold_constants_bexp b with
| BTrue => fold_constants_com c1
| BFalse => fold_constants_com c2
| b' => IFB b' THEN fold_constants_com c1
ELSE fold_constants_com c2 FI
end
| WHILE b DO c END =>
match fold_constants_bexp b with
| BTrue => WHILE BTrue DO SKIP END
| BFalse => SKIP
| b' => WHILE b' DO (fold_constants_com c) END
end
end.
Example fold_com_ex1 :
fold_constants_com
(* Original program: *)
(X ::= APlus (ANum 4) (ANum 5);;
Y ::= AMinus (AId X) (ANum 3);;
IFB BEq (AMinus (AId X) (AId Y)) (APlus (ANum 2) (ANum 4)) THEN
SKIP
ELSE
Y ::= ANum 0
FI;;
IFB BLe (ANum 0) (AMinus (ANum 4) (APlus (ANum 2) (ANum 1))) THEN
Y ::= ANum 0
ELSE
SKIP
FI;;
WHILE BEq (AId Y) (ANum 0) DO
X ::= APlus (AId X) (ANum 1)
END)
= (* After constant folding: *)
(X ::= ANum 9;;
Y ::= AMinus (AId X) (ANum 3);;
IFB BEq (AMinus (AId X) (AId Y)) (ANum 6) THEN
SKIP
ELSE
(Y ::= ANum 0)
FI;;
Y ::= ANum 0;;
WHILE BEq (AId Y) (ANum 0) DO
X ::= APlus (AId X) (ANum 1)
END).
Proof. reflexivity. Qed.
(* ################################################### *)
(** ** Soundness of Constant Folding *)
(** Now we need to show that what we've done is correct. *)
(** Here's the proof for arithmetic expressions: *)
Theorem fold_constants_aexp_sound :
atrans_sound fold_constants_aexp.
Proof.
unfold atrans_sound. intros a. unfold aequiv. intros st.
aexp_cases (induction a) Case; simpl;
(* ANum and AId follow immediately *)
try reflexivity;
(* APlus, AMinus, and AMult follow from the IH
and the observation that
aeval st (APlus a1 a2)
= ANum ((aeval st a1) + (aeval st a2))
= aeval st (ANum ((aeval st a1) + (aeval st a2)))
(and similarly for AMinus/minus and AMult/mult) *)
try (destruct (fold_constants_aexp a1);
destruct (fold_constants_aexp a2);
rewrite IHa1; rewrite IHa2; reflexivity). Qed.
(** **** Exercise: 3 stars, optional (fold_bexp_BEq_informal) *)
(** Here is an informal proof of the [BEq] case of the soundness
argument for boolean expression constant folding. Read it
carefully and compare it to the formal proof that follows. Then
fill in the [BLe] case of the formal proof (without looking at the
[BEq] case, if possible).
_Theorem_: The constant folding function for booleans,
[fold_constants_bexp], is sound.
_Proof_: We must show that [b] is equivalent to [fold_constants_bexp],
for all boolean expressions [b]. Proceed by induction on [b]. We
show just the case where [b] has the form [BEq a1 a2].
In this case, we must show
beval st (BEq a1 a2)
= beval st (fold_constants_bexp (BEq a1 a2)).
There are two cases to consider:
- First, suppose [fold_constants_aexp a1 = ANum n1] and
[fold_constants_aexp a2 = ANum n2] for some [n1] and [n2].
In this case, we have
fold_constants_bexp (BEq a1 a2)
= if beq_nat n1 n2 then BTrue else BFalse
and
beval st (BEq a1 a2)
= beq_nat (aeval st a1) (aeval st a2).
By the soundness of constant folding for arithmetic
expressions (Lemma [fold_constants_aexp_sound]), we know
aeval st a1
= aeval st (fold_constants_aexp a1)
= aeval st (ANum n1)
= n1
and
aeval st a2
= aeval st (fold_constants_aexp a2)
= aeval st (ANum n2)
= n2,
so
beval st (BEq a1 a2)
= beq_nat (aeval a1) (aeval a2)
= beq_nat n1 n2.
Also, it is easy to see (by considering the cases [n1 = n2] and
[n1 <> n2] separately) that
beval st (if beq_nat n1 n2 then BTrue else BFalse)
= if beq_nat n1 n2 then beval st BTrue else beval st BFalse
= if beq_nat n1 n2 then true else false
= beq_nat n1 n2.
So
beval st (BEq a1 a2)
= beq_nat n1 n2.
= beval st (if beq_nat n1 n2 then BTrue else BFalse),
]]
as required.
- Otherwise, one of [fold_constants_aexp a1] and
[fold_constants_aexp a2] is not a constant. In this case, we
must show
beval st (BEq a1 a2)
= beval st (BEq (fold_constants_aexp a1)
(fold_constants_aexp a2)),
which, by the definition of [beval], is the same as showing
beq_nat (aeval st a1) (aeval st a2)
= beq_nat (aeval st (fold_constants_aexp a1))
(aeval st (fold_constants_aexp a2)).
But the soundness of constant folding for arithmetic
expressions ([fold_constants_aexp_sound]) gives us
aeval st a1 = aeval st (fold_constants_aexp a1)
aeval st a2 = aeval st (fold_constants_aexp a2),
completing the case. []
*)
Theorem fold_constants_bexp_sound:
btrans_sound fold_constants_bexp.
Proof.
unfold btrans_sound. intros b. unfold bequiv. intros st.
bexp_cases (induction b) Case;
(* BTrue and BFalse are immediate *)
try reflexivity.
Case "BEq".
(* Doing induction when there are a lot of constructors makes
specifying variable names a chore, but Coq doesn't always
choose nice variable names. We can rename entries in the
context with the [rename] tactic: [rename a into a1] will
change [a] to [a1] in the current goal and context. *)
rename a into a1. rename a0 into a2. simpl.
remember (fold_constants_aexp a1) as a1' eqn:Heqa1'.
remember (fold_constants_aexp a2) as a2' eqn:Heqa2'.
replace (aeval st a1) with (aeval st a1') by
(subst a1'; rewrite <- fold_constants_aexp_sound; reflexivity).
replace (aeval st a2) with (aeval st a2') by
(subst a2'; rewrite <- fold_constants_aexp_sound; reflexivity).
destruct a1'; destruct a2'; try reflexivity.
(* The only interesting case is when both a1 and a2
become constants after folding *)
simpl. destruct (beq_nat n n0); reflexivity.
Case "BLe".
rename a into a1. rename a0 into a2. simpl.
remember (fold_constants_aexp a1) as a1' eqn:Heqa1'.
remember (fold_constants_aexp a2) as a2' eqn:Heqa2'.
replace (aeval st a1) with (aeval st a1') by
(subst a1'; rewrite <- fold_constants_aexp_sound; reflexivity).
replace (aeval st a2) with (aeval st a2') by
(subst a2'; rewrite <- fold_constants_aexp_sound; reflexivity).
destruct a1'; destruct a2'; try reflexivity.
simpl. destruct (ble_nat n n0); reflexivity.
Case "BNot".
simpl. remember (fold_constants_bexp b) as b' eqn:Heqb'.
rewrite IHb.
destruct b'; reflexivity.
Case "BAnd".
simpl.
remember (fold_constants_bexp b1) as b1' eqn:Heqb1'.
remember (fold_constants_bexp b2) as b2' eqn:Heqb2'.
rewrite IHb1. rewrite IHb2.
destruct b1'; destruct b2'; reflexivity. Qed.
(** [] *)
(** **** Exercise: 3 stars (fold_constants_com_sound) *)
(** Complete the [WHILE] case of the following proof. *)
Theorem fold_constants_com_sound :
ctrans_sound fold_constants_com.
Proof.
unfold ctrans_sound. intros c.
com_cases (induction c) Case; simpl.
Case "SKIP". apply refl_cequiv.
Case "::=". apply CAss_congruence. apply fold_constants_aexp_sound.
Case ";;". apply CSeq_congruence; assumption.
Case "IFB".
assert (bequiv b (fold_constants_bexp b)).
SCase "Pf of assertion". apply fold_constants_bexp_sound.
destruct (fold_constants_bexp b) eqn:Heqb;
(* If the optimization doesn't eliminate the if, then the result
is easy to prove from the IH and fold_constants_bexp_sound *)
try (apply CIf_congruence; assumption).
SCase "b always true".
apply trans_cequiv with c1; try assumption.
apply IFB_true; assumption.
SCase "b always false".
apply trans_cequiv with c2; try assumption.
apply IFB_false; assumption.
Case "WHILE".
assert (bequiv b (fold_constants_bexp b)). apply fold_constants_bexp_sound.
destruct (fold_constants_bexp b) eqn:Heqb;
(* most cases can be treated by congruence *)
try (apply CWhile_congruence; assumption; apply IHc).
(* const true and const false cases are special *)
SCase "b always true".
apply WHILE_true. assumption.
SCase "b always false".
apply WHILE_false. assumption.
Qed.
(** [] *)
(* ########################################################## *)
(** *** Soundness of (0 + n) Elimination, Redux *)
(** **** Exercise: 4 stars, advanced, optional (optimize_0plus) *)
(** Recall the definition [optimize_0plus] from Imp.v:
Fixpoint optimize_0plus (e:aexp) : aexp :=
match e with
| ANum n =>
ANum n
| APlus (ANum 0) e2 =>
optimize_0plus e2
| APlus e1 e2 =>
APlus (optimize_0plus e1) (optimize_0plus e2)
| AMinus e1 e2 =>
AMinus (optimize_0plus e1) (optimize_0plus e2)
| AMult e1 e2 =>
AMult (optimize_0plus e1) (optimize_0plus e2)
end.
Note that this function is defined over the old [aexp]s,
without states.
Write a new version of this function that accounts for variables,
and analogous ones for [bexp]s and commands:
optimize_0plus_aexp
optimize_0plus_bexp
optimize_0plus_com
Prove that these three functions are sound, as we did for
[fold_constants_*]. (Make sure you use the congruence lemmas in
the proof of [optimize_0plus_com] -- otherwise it will be _long_!)
Then define an optimizer on commands that first folds
constants (using [fold_constants_com]) and then eliminates [0 + n]
terms (using [optimize_0plus_com]).
- Give a meaningful example of this optimizer's output.
- Prove that the optimizer is sound. (This part should be _very_
easy.) *)
Fixpoint optimize_0plus (e:aexp) : aexp :=
match e with
| ANum n => ANum n
| AId id => AId id
| APlus (ANum 0) e => optimize_0plus e
| APlus e1 e2 => APlus (optimize_0plus e1) (optimize_0plus e2)
| AMinus e1 e2 => AMinus (optimize_0plus e1) (optimize_0plus e2)
| AMult e1 e2 => AMult (optimize_0plus e1) (optimize_0plus e2)
end.
Fixpoint optimize_0plus_b (b:bexp) : bexp :=
match b with
| BTrue => BTrue
| BFalse => BFalse
| BEq a1 a2 => BEq (optimize_0plus a1) (optimize_0plus a2)
| BLe a1 a2 => BLe (optimize_0plus a1) (optimize_0plus a2)
| BNot b1 => BNot (optimize_0plus_b b1)
| BAnd b1 b2 => BAnd (optimize_0plus_b b1) (optimize_0plus_b b2)
end.
Fixpoint optimize_0plus_com (c:com) : com :=
match c with
| SKIP => SKIP
| x ::= a1 => x ::= (optimize_0plus a1)
| c1 ;; c2 => optimize_0plus_com c1 ;; optimize_0plus_com c2
| IFB b THEN c1 ELSE c2 FI =>
IFB (optimize_0plus_b b) THEN (optimize_0plus_com c1) ELSE (optimize_0plus_com c2) FI
| WHILE b DO c END =>
WHILE (optimize_0plus_b b) DO (optimize_0plus_com c) END
end.
Theorem optimize_0plus_sound : atrans_sound optimize_0plus.
Proof.
unfold atrans_sound. unfold aequiv. intros. aexp_cases (induction a) Case;
try reflexivity.
Case "APlus".
destruct a1.
SCase "ANum".
try (destruct n).
SSCase "ANum 0". simpl. rewrite <- IHa2. reflexivity.
SSCase "ANum S n". simpl. rewrite <- IHa2. reflexivity.
SCase "AId".
simpl. rewrite <- IHa2. reflexivity.
SCase "APlus".
replace (optimize_0plus (APlus (APlus a1_1 a1_2) a2))
with (APlus (optimize_0plus (APlus a1_1 a1_2)) (optimize_0plus a2)) by reflexivity.
replace (aeval st (APlus (optimize_0plus (APlus a1_1 a1_2)) (optimize_0plus a2)))
with (aeval st (optimize_0plus (APlus a1_1 a1_2)) + aeval st (optimize_0plus a2)) by reflexivity.
rewrite <- IHa2. rewrite <- IHa1. reflexivity.
SCase "AMinus".
replace (optimize_0plus (APlus (AMinus a1_1 a1_2) a2))
with (APlus (optimize_0plus (AMinus a1_1 a1_2)) (optimize_0plus a2)) by reflexivity.
replace (aeval st (APlus (optimize_0plus (AMinus a1_1 a1_2)) (optimize_0plus a2)))
with (aeval st (optimize_0plus (AMinus a1_1 a1_2)) + aeval st (optimize_0plus a2)) by reflexivity.
rewrite <- IHa2. rewrite <- IHa1. reflexivity.
SCase "AMult".
replace (optimize_0plus (APlus (AMult a1_1 a1_2) a2))
with (APlus (optimize_0plus (AMult a1_1 a1_2)) (optimize_0plus a2)) by reflexivity.
replace (aeval st (APlus (optimize_0plus (AMult a1_1 a1_2)) (optimize_0plus a2)))
with (aeval st (optimize_0plus (AMult a1_1 a1_2)) + aeval st (optimize_0plus a2)) by reflexivity.
rewrite <- IHa2. rewrite <- IHa1. reflexivity.
simpl. try (rewrite <- IHa1). try (rewrite <- IHa2). reflexivity.
simpl. try (rewrite <- IHa1). try (rewrite <- IHa2). reflexivity.
Qed.
Theorem optimize_0plus_b_sound : btrans_sound optimize_0plus_b.
Proof.
unfold btrans_sound. unfold bequiv. intros.
bexp_cases (induction b) Case;
try reflexivity;
try (simpl; rewrite <- optimize_0plus_sound; rewrite <- optimize_0plus_sound; reflexivity).
Case "BNot". simpl. rewrite IHb. reflexivity.
Case "BAnd". simpl. rewrite <- IHb1. rewrite <- IHb2. reflexivity.
Qed.
Theorem optimize_0plus_com_sound : ctrans_sound optimize_0plus_com.
Proof.
unfold ctrans_sound. intro c.
com_cases (induction c) Case.
Case "SKIP". apply refl_cequiv.
Case "::=". apply CAss_congruence. apply optimize_0plus_sound.
Case ";;". apply CSeq_congruence; assumption.
Case "IFB". apply CIf_congruence; try (apply optimize_0plus_b_sound); assumption.
Case "WHILE". apply CWhile_congruence; try (apply optimize_0plus_b_sound); assumption.
Qed.
Definition optimize_combined (c:com) : com :=
optimize_0plus_com (fold_constants_com c).
Theorem optimize_combined_sound : ctrans_sound optimize_combined.
Proof.
unfold ctrans_sound. intros c. unfold optimize_combined.
apply trans_cequiv with (c2:=fold_constants_com c).
apply fold_constants_com_sound.
apply optimize_0plus_com_sound.
Qed.
(** [] *)
(* ####################################################### *)
(** * Proving That Programs Are _Not_ Equivalent *)
(** Suppose that [c1] is a command of the form [X ::= a1;; Y ::= a2]
and [c2] is the command [X ::= a1;; Y ::= a2'], where [a2'] is
formed by substituting [a1] for all occurrences of [X] in [a2].
For example, [c1] and [c2] might be:
c1 = (X ::= 42 + 53;;
Y ::= Y + X)
c2 = (X ::= 42 + 53;;
Y ::= Y + (42 + 53))
Clearly, this _particular_ [c1] and [c2] are equivalent. Is this
true in general? *)
(** We will see in a moment that it is not, but it is worthwhile
to pause, now, and see if you can find a counter-example on your
own. *)
(** Here, formally, is the function that substitutes an arithmetic
expression for each occurrence of a given variable in another
expression: *)
Fixpoint subst_aexp (i : id) (u : aexp) (a : aexp) : aexp :=
match a with
| ANum n => ANum n
| AId i' => if eq_id_dec i i' then u else AId i'
| APlus a1 a2 => APlus (subst_aexp i u a1) (subst_aexp i u a2)
| AMinus a1 a2 => AMinus (subst_aexp i u a1) (subst_aexp i u a2)
| AMult a1 a2 => AMult (subst_aexp i u a1) (subst_aexp i u a2)
end.
Example subst_aexp_ex :
subst_aexp X (APlus (ANum 42) (ANum 53)) (APlus (AId Y) (AId X)) =
(APlus (AId Y) (APlus (ANum 42) (ANum 53))).
Proof. reflexivity. Qed.
(** And here is the property we are interested in, expressing the
claim that commands [c1] and [c2] as described above are
always equivalent. *)
Definition subst_equiv_property := forall i1 i2 a1 a2,
cequiv (i1 ::= a1;; i2 ::= a2)
(i1 ::= a1;; i2 ::= subst_aexp i1 a1 a2).
(** Sadly, the property does _not_ always hold.
_Theorem_: It is not the case that, for all [i1], [i2], [a1],
and [a2],
cequiv (i1 ::= a1;; i2 ::= a2)
(i1 ::= a1;; i2 ::= subst_aexp i1 a1 a2).
]]
_Proof_: Suppose, for a contradiction, that for all [i1], [i2],
[a1], and [a2], we have
cequiv (i1 ::= a1;; i2 ::= a2)
(i1 ::= a1;; i2 ::= subst_aexp i1 a1 a2).
Consider the following program:
X ::= APlus (AId X) (ANum 1);; Y ::= AId X
Note that
(X ::= APlus (AId X) (ANum 1);; Y ::= AId X)
/ empty_state || st1,
where [st1 = { X |-> 1, Y |-> 1 }].
By our assumption, we know that
cequiv (X ::= APlus (AId X) (ANum 1);; Y ::= AId X)
(X ::= APlus (AId X) (ANum 1);; Y ::= APlus (AId X) (ANum 1))
so, by the definition of [cequiv], we have
(X ::= APlus (AId X) (ANum 1);; Y ::= APlus (AId X) (ANum 1))
/ empty_state || st1.
But we can also derive
(X ::= APlus (AId X) (ANum 1);; Y ::= APlus (AId X) (ANum 1))
/ empty_state || st2,
where [st2 = { X |-> 1, Y |-> 2 }]. Note that [st1 <> st2]; this
is a contradiction, since [ceval] is deterministic! [] *)
Theorem subst_inequiv :
~ subst_equiv_property.
Proof.
unfold subst_equiv_property.
intros Contra.
(* Here is the counterexample: assuming that [subst_equiv_property]
holds allows us to prove that these two programs are
equivalent... *)
remember (X ::= APlus (AId X) (ANum 1);;
Y ::= AId X)
as c1.
remember (X ::= APlus (AId X) (ANum 1);;
Y ::= APlus (AId X) (ANum 1))
as c2.
assert (cequiv c1 c2) by (subst; apply Contra).
(* ... allows us to show that the command [c2] can terminate
in two different final states:
st1 = {X |-> 1, Y |-> 1}
st2 = {X |-> 1, Y |-> 2}. *)
remember (update (update empty_state X 1) Y 1) as st1.
remember (update (update empty_state X 1) Y 2) as st2.
assert (H1: c1 / empty_state || st1);
assert (H2: c2 / empty_state || st2);
try (subst;
apply E_Seq with (st' := (update empty_state X 1));
apply E_Ass; reflexivity).
apply H in H1.
(* Finally, we use the fact that evaluation is deterministic
to obtain a contradiction. *)
assert (Hcontra: st1 = st2)
by (apply (ceval_deterministic c2 empty_state); assumption).
assert (Hcontra': st1 Y = st2 Y)
by (rewrite Hcontra; reflexivity).
subst. inversion Hcontra'. Qed.
(** **** Exercise: 4 stars, optional (better_subst_equiv) *)
(** The equivalence we had in mind above was not complete nonsense --
it was actually almost right. To make it correct, we just need to
exclude the case where the variable [X] occurs in the
right-hand-side of the first assignment statement. *)
Inductive var_not_used_in_aexp (X:id) : aexp -> Prop :=
| VNUNum: forall n, var_not_used_in_aexp X (ANum n)
| VNUId: forall Y, X <> Y -> var_not_used_in_aexp X (AId Y)
| VNUPlus: forall a1 a2,
var_not_used_in_aexp X a1 ->
var_not_used_in_aexp X a2 ->
var_not_used_in_aexp X (APlus a1 a2)
| VNUMinus: forall a1 a2,
var_not_used_in_aexp X a1 ->
var_not_used_in_aexp X a2 ->
var_not_used_in_aexp X (AMinus a1 a2)
| VNUMult: forall a1 a2,
var_not_used_in_aexp X a1 ->
var_not_used_in_aexp X a2 ->
var_not_used_in_aexp X (AMult a1 a2).
Lemma aeval_weakening : forall i st a ni,
var_not_used_in_aexp i a ->
aeval (update st i ni) a = aeval st a.
Proof.
intros. aexp_cases (induction a) Case.
Case "ANum". reflexivity.
Case "AId". inversion H. subst. simpl. apply update_neq. assumption.
(* other cases *)
inversion H. subst. simpl. rewrite IHa1. rewrite IHa2. reflexivity. assumption. assumption.
inversion H. subst. simpl. rewrite IHa1. rewrite IHa2. reflexivity. assumption. assumption.
inversion H. subst. simpl. rewrite IHa1. rewrite IHa2. reflexivity. assumption. assumption.
Qed.
(** Using [var_not_used_in_aexp], formalize and prove a correct verson
of [subst_equiv_property]. *)
Definition subst_equiv_property' := forall i1 i2 a1 a2,
var_not_used_in_aexp i1 a1 ->
cequiv (i1 ::= a1;; i2 ::= a2)
(i1 ::= a1;; i2 ::= subst_aexp i1 a1 a2).
(* Why does this hold? After the first assignment i1 is equal to (aeval st a1).
If i1 does not appear in a1, then the assignment of (aeval st a1) to i1 does not
change the value of (aeval st a1). Therefore, any occurence of a1 in a2 will
evaluate to the same value before and after the first assignment and will therefore
not change the value assigned to i2.
How can I show this?
1) var_not_used_in_aexp i1 a1 -> aeval st a1 = aeval (update st i1 n) a1
2) var_not_used_in_aexp i1 a1 -> st i1 = aeval st a1 -> aeval st a2 = aeval st (subst_aexp i1 a1 a2) (?)
3) induction over a2 (?) - maybe this is already taken care of by var_not_used_subst (?)
*)
Lemma var_not_used_aeval_const : forall i a st n,
var_not_used_in_aexp i a -> aeval st a = aeval (update st i n) a.
Proof.
intros. generalize dependent st. generalize dependent n. induction H; intros;
(* Nums *)
try reflexivity;
(* Ids *)
try (simpl; rewrite update_neq; try reflexivity; try assumption);
(* Recursive cases *)
try (simpl;
replace (aeval (update st i n) a1) with (aeval st a1) by (apply IHvar_not_used_in_aexp1);
replace (aeval (update st i n) a2) with (aeval st a2) by (apply IHvar_not_used_in_aexp2);
reflexivity).
Qed.
Lemma var_not_used_subst : forall st i1 a1 a2,
var_not_used_in_aexp i1 a1 -> st i1 = aeval st a1 -> aeval st a2 = aeval st (subst_aexp i1 a1 a2).
Proof.
intros. induction a2;
try reflexivity;
try (simpl; destruct (eq_id_dec i1 i); subst; try assumption; try reflexivity);
try (simpl; rewrite <- IHa2_1; rewrite <- IHa2_2; reflexivity).
Qed.
Theorem subst_equiv_sound : subst_equiv_property'.
Proof.
unfold subst_equiv_property'. intros i1 i2 a1 a2 H. split; intros.
Case "->".
apply E_Seq with (st':=update st i1 (aeval st a1)). apply E_Ass. reflexivity.
inversion H0. subst. inversion H6. subst. inversion H3. subst. apply E_Ass.
symmetry. apply var_not_used_subst. assumption.
rewrite <- var_not_used_aeval_const. rewrite update_eq. reflexivity. assumption.
Case "<-".
apply E_Seq with (st':=update st i1 (aeval st a1)). apply E_Ass. reflexivity.
inversion H0. subst. inversion H6. subst. inversion H3. subst. apply E_Ass.
apply var_not_used_subst. assumption.
rewrite <- var_not_used_aeval_const. rewrite update_eq. reflexivity. assumption.
Qed.
(** [] *)
(** **** Exercise: 3 stars, optional (inequiv_exercise) *)
(** Prove that an infinite loop is not equivalent to [SKIP] *)
Theorem inequiv_exercise:
~ cequiv (WHILE BTrue DO SKIP END) SKIP.
Proof. unfold not. intros Contra. unfold cequiv in Contra.
assert (H: forall st, SKIP / st || st) by (apply E_Skip).
assert (H1: SKIP / empty_state || empty_state) by (apply H). apply Contra in H1.
apply WHILE_true_nonterm in H1. inversion H1. apply refl_bequiv.
Qed.
(** [] *)
(** * Extended exercise: Non-deterministic Imp *)
(** As we have seen (in theorem [ceval_deterministic] in the Imp
chapter), Imp's evaluation relation is deterministic. However,
_non_-determinism is an important part of the definition of many
real programming languages. For example, in many imperative
languages (such as C and its relatives), the order in which
function arguments are evaluated is unspecified. The program
fragment
x = 0;;
f(++x, x)
might call [f] with arguments [(1, 0)] or [(1, 1)], depending how
the compiler chooses to order things. This can be a little
confusing for programmers, but it gives the compiler writer useful
freedom.
In this exercise, we will extend Imp with a simple
non-deterministic command and study how this change affects
program equivalence. The new command has the syntax [HAVOC X],
where [X] is an identifier. The effect of executing [HAVOC X] is
to assign an _arbitrary_ number to the variable [X],
non-deterministically. For example, after executing the program:
HAVOC Y;;
Z ::= Y * 2
the value of [Y] can be any number, while the value of [Z] is
twice that of [Y] (so [Z] is always even). Note that we are not
saying anything about the _probabilities_ of the outcomes -- just
that there are (infinitely) many different outcomes that can
possibly happen after executing this non-deterministic code.
In a sense a variable on which we do [HAVOC] roughly corresponds
to an unitialized variable in the C programming language. After
the [HAVOC] the variable holds a fixed but arbitrary number. Most
sources of nondeterminism in language definitions are there
precisely because programmers don't care which choice is made (and
so it is good to leave it open to the compiler to choose whichever
will run faster).
We call this new language _Himp_ (``Imp extended with [HAVOC]''). *)
Module Himp.
(** To formalize the language, we first add a clause to the definition of
commands. *)
Inductive com : Type :=
| CSkip : com
| CAss : id -> aexp -> com
| CSeq : com -> com -> com
| CIf : bexp -> com -> com -> com
| CWhile : bexp -> com -> com
| CHavoc : id -> com. (* <---- new *)
Tactic Notation "com_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "SKIP" | Case_aux c "::=" | Case_aux c ";;"
| Case_aux c "IFB" | Case_aux c "WHILE" | Case_aux c "HAVOC" ].
Notation "'SKIP'" :=
CSkip.
Notation "X '::=' a" :=
(CAss X a) (at level 60).
Notation "c1 ;; c2" :=
(CSeq c1 c2) (at level 80, right associativity).
Notation "'WHILE' b 'DO' c 'END'" :=
(CWhile b c) (at level 80, right associativity).
Notation "'IFB' e1 'THEN' e2 'ELSE' e3 'FI'" :=
(CIf e1 e2 e3) (at level 80, right associativity).
Notation "'HAVOC' l" := (CHavoc l) (at level 60).
(** **** Exercise: 2 stars (himp_ceval) *)
(** Now, we must extend the operational semantics. We have provided
a template for the [ceval] relation below, specifying the big-step
semantics. What rule(s) must be added to the definition of [ceval]
to formalize the behavior of the [HAVOC] command? *)
Reserved Notation "c1 '/' st '||' st'" (at level 40, st at level 39).
Inductive ceval : com -> state -> state -> Prop :=
| E_Skip : forall st : state, SKIP / st || st
| E_Ass : forall (st : state) (a1 : aexp) (n : nat) (X : id),
aeval st a1 = n -> (X ::= a1) / st || update st X n
| E_Seq : forall (c1 c2 : com) (st st' st'' : state),
c1 / st || st' -> c2 / st' || st'' -> (c1 ;; c2) / st || st''
| E_IfTrue : forall (st st' : state) (b1 : bexp) (c1 c2 : com),
beval st b1 = true ->
c1 / st || st' -> (IFB b1 THEN c1 ELSE c2 FI) / st || st'
| E_IfFalse : forall (st st' : state) (b1 : bexp) (c1 c2 : com),
beval st b1 = false ->
c2 / st || st' -> (IFB b1 THEN c1 ELSE c2 FI) / st || st'
| E_WhileEnd : forall (b1 : bexp) (st : state) (c1 : com),
beval st b1 = false -> (WHILE b1 DO c1 END) / st || st
| E_WhileLoop : forall (st st' st'' : state) (b1 : bexp) (c1 : com),
beval st b1 = true ->
c1 / st || st' ->
(WHILE b1 DO c1 END) / st' || st'' ->
(WHILE b1 DO c1 END) / st || st''
| E_Havoc : forall (st : state) (n:nat) (X : id),
(HAVOC X) / st || update st X n
(* FILL IN HERE *)
where "c1 '/' st '||' st'" := (ceval c1 st st').
Tactic Notation "ceval_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "E_Skip" | Case_aux c "E_Ass" | Case_aux c "E_Seq"
| Case_aux c "E_IfTrue" | Case_aux c "E_IfFalse"
| Case_aux c "E_WhileEnd" | Case_aux c "E_WhileLoop"
| Case_aux c "E_Havoc"
(* FILL IN HERE *)
].
(** As a sanity check, the following claims should be provable for
your definition: *)
Example havoc_example1 : (HAVOC X) / empty_state || update empty_state X 0.
Proof. constructor. Qed.
Example havoc_example2 :
(SKIP;; HAVOC Z) / empty_state || update empty_state Z 42.
Proof. apply E_Seq with (st':=empty_state). constructor. constructor. Qed.
(** [] *)
(** Finally, we repeat the definition of command equivalence from above: *)
Definition cequiv (c1 c2 : com) : Prop := forall st st' : state,
c1 / st || st' <-> c2 / st || st'.
(** This definition still makes perfect sense in the case of always
terminating programs, so let's apply it to prove some
non-deterministic programs equivalent or non-equivalent. *)
(** **** Exercise: 3 stars (havoc_swap) *)
(** Are the following two programs equivalent? *)
Definition pXY :=
HAVOC X;; HAVOC Y.
Definition pYX :=
HAVOC Y;; HAVOC X.
(** If you think they are equivalent, prove it. If you think they are
not, prove that. *)
Theorem pXY_cequiv_pYX :
cequiv pXY pYX \/ ~cequiv pXY pYX.
Proof.
left. unfold cequiv. unfold pXY. unfold pYX. split; intros.
Case "->". inversion H. subst. inversion H2. subst. inversion H5. subst.
apply E_Seq with (st':=update st Y n0). apply E_Havoc.
replace (update (update st X n) Y n0) with (update (update st Y n0) X n). apply E_Havoc.
apply functional_extensionality. intros. apply update_permute. intro Contra. inversion Contra.
Case "<-".
inversion H. subst. inversion H2. subst. inversion H5. subst.
apply E_Seq with (st':=update st X n0). apply E_Havoc.
replace (update (update st Y n) X n0) with (update (update st X n0) Y n). apply E_Havoc.
apply functional_extensionality. intros. apply update_permute. intro Contra. inversion Contra.
Qed.
(** **** Exercise: 4 stars, optional (havoc_copy) *)
(** Are the following two programs equivalent? *)
Definition ptwice :=
HAVOC X;; HAVOC Y.
Definition pcopy :=
HAVOC X;; Y ::= AId X.
(** If you think they are equivalent, then prove it. If you think they
are not, then prove that. (Hint: You may find the [assert] tactic
useful.) *)
Theorem ptwice_cequiv_pcopy :
cequiv ptwice pcopy \/ ~cequiv ptwice pcopy.
Proof.
right. intro Contra. unfold cequiv in Contra.
assert (H: ptwice / empty_state || update (update empty_state X 0) Y 1).
apply E_Seq with (st':=update empty_state X 0). apply E_Havoc. apply E_Havoc.
apply Contra in H. inversion H. subst. inversion H2. subst. inversion H5. subst.
simpl in H6. replace (update empty_state X n X) with n in H6 by reflexivity.
destruct n.
assert (update (update empty_state X 0) Y 1 Y = update (update empty_state X 0) Y 0 Y). rewrite H6. reflexivity.
rewrite update_eq in H0. rewrite update_eq in H0. inversion H0.
assert (update (update empty_state X (S n)) Y (S n) X = update (update empty_state X 0) Y 1 X). rewrite H6. reflexivity.
rewrite update_permute in H0. rewrite update_eq in H0. rewrite update_permute in H0. rewrite update_eq in H0. inversion H0.
intro. inversion H1. intro. inversion H1.
Qed.
(** The definition of program equivalence we are using here has some
subtle consequences on programs that may loop forever. What
[cequiv] says is that the set of possible _terminating_ outcomes
of two equivalent programs is the same. However, in a language
with non-determinism, like Himp, some programs always terminate,
some programs always diverge, and some programs can
non-deterministically terminate in some runs and diverge in
others. The final part of the following exercise illustrates this
phenomenon.
*)
(** **** Exercise: 5 stars, advanced (havoc_diverge) *)
(** Prove the following program equivalences and non-equivalences, and
try to understand why the [cequiv] definition has the behavior it
has on these examples. *)
Definition p1 : com :=
WHILE (BNot (BEq (AId X) (ANum 0))) DO
HAVOC Y;;
X ::= APlus (AId X) (ANum 1)
END.
Definition p2 : com :=
WHILE (BNot (BEq (AId X) (ANum 0))) DO
SKIP
END.
(* Why are the two equivalent? If X <> 0 in the beginning then
both loops diverge. This is because the first loop updates
X so that it will never be zero. If X = 0 then both loops
are equal to SKIP.
How can I prove this? I need to show that
bequiv cond BTrue and bequiv cond BFalse for the two cases.
For the first loop I probably need to show this by induction over
the current value of X in the state.
OK, what exactly do I want to show?
i) st X = 0 -> both loops are equiv to SKIP
ii) st X <> 0 -> beval st cond = BTrue -> c / st || st' -> beval st cond = BTrue
for both cs (loop bodies).
iii) ii -> both loops do not terminate (and are this equiv)
*)
Definition p1p2_loop_cond := (BNot (BEq (AId X) (ANum 0))).
Lemma p1p2_cond : forall st,
st X = 0 <-> beval st p1p2_loop_cond = false.
Proof.
intros. split.
Case "->". intros. simpl. rewrite H. reflexivity.
Case "<-". intro. inversion H. destruct (st X). reflexivity. simpl in H1. inversion H1.
Qed.
Definition p1_loop_body : com :=
(HAVOC Y;; X ::= APlus (AId X) (ANum 1)).
Lemma neq_zero_after_p1_body : forall st st',
p1_loop_body / st || st' -> st' X <> 0.
Proof.
intros. unfold p1_loop_body in H. inversion H. subst. inversion H5. subst. inversion H2. subst.
rewrite update_eq. simpl. destruct (update st Y n X); simpl; unfold not; intros; inversion H0.
Qed.
Lemma p1_cond_stays_true : forall st st',
p1_loop_body / st || st' -> beval st' p1p2_loop_cond = true.
Proof.
intros. unfold p1_loop_body in H. inversion H. subst. inversion H5. subst. inversion H2. subst.
unfold p1p2_loop_cond. simpl. rewrite update_eq. destruct (update st Y n X). reflexivity. reflexivity.
Qed.
Definition inf_loop : com := (WHILE BTrue DO SKIP END).
Lemma p1_nonterm : forall st st',
st X <> 0 -> ~ (p1 / st || st').
Proof.
unfold not. intros. unfold p1 in H0.
remember (WHILE BNot (BEq (AId X) (ANum 0))
DO HAVOC Y;; X ::= APlus (AId X) (ANum 1) END) as loop eqn:Hloop.
ceval_cases (induction H0) Case; try (inversion Hloop).
Case "E_WhileEnd". subst. simpl in H0. apply H. destruct (st X). reflexivity. simpl in H0. inversion H0.
Case "E_WhileLoop". subst. apply IHceval2. apply neq_zero_after_p1_body with (st:=st) (st':=st').
unfold p1_loop_body. apply H0_. reflexivity.
Qed.
Lemma p2_nonterm : forall st st',
st X <> 0 -> ~ (p2 / st || st').
Proof.
unfold not. intros. unfold p2 in H0.
remember (WHILE BNot (BEq (AId X) (ANum 0)) DO SKIP END) as loop eqn:Hloop.
ceval_cases (induction H0) Case; try (inversion Hloop).
Case "E_WhileEnd". subst. simpl in H0. apply H. destruct (st X). reflexivity. simpl in H0. inversion H0.
Case "E_WhileLoop". subst. apply IHceval2. inversion H0_. subst. assumption. reflexivity.
Qed.
Theorem p1_p2_equiv : cequiv p1 p2.
Proof.
unfold cequiv. intros.
assert ({st X = 0} + {st X <> 0}) by (apply eq_nat_dec). inversion H.
Case "st X = 0".
split.
SCase "->". intros. inversion H1.
unfold p2. apply E_WhileEnd. assumption.
simpl in H4. rewrite H0 in H4. inversion H4.
SCase "<-". intros. inversion H1.
unfold p1. apply E_WhileEnd. assumption.
simpl in H4. rewrite H0 in H4. inversion H4.
Case "st X <> 0".
split.
SCase "->". intros.
apply p1_nonterm with (st':=st') in H0. unfold not in H0. apply H0 in H1. inversion H1.
SCase "<-". intros. unfold p2 in H1. inversion H1. simpl in H6. subst.
destruct (st' X). contradiction H0. reflexivity. simpl in H6. inversion H6.
subst. apply p2_nonterm with (st':=st') in H0. unfold not in H0. fold p2 in H1. contradiction H0.
Qed.
Definition p3 : com :=
Z ::= ANum 1;;
WHILE (BNot (BEq (AId X) (ANum 0))) DO
HAVOC X;;
HAVOC Z
END.
Definition p4 : com :=
X ::= (ANum 0);;
Z ::= (ANum 1).
(* why are they not equivalent? If X <> 0 then X and Z hold arbitrary numbers
how to prove it?
*)
Theorem p3_p4_inequiv : ~ cequiv p3 p4.
Proof.
unfold not. unfold cequiv. intros.
remember (update empty_state X 1) as st.
remember (update (update (update st Z 1) X 0) Z 7) as st'.
assert (p3 / st || st'). unfold p3. apply E_Seq with (st':=update st Z 1). apply E_Ass. reflexivity.
apply E_WhileLoop with (st':=st'). simpl. rewrite Heqst. rewrite update_permute. rewrite update_eq.
reflexivity. unfold not. intro. inversion H0. apply E_Seq with (st':=update (update st Z 1) X 0).
apply E_Havoc. rewrite Heqst'. apply E_Havoc. apply E_WhileEnd. rewrite Heqst'. simpl. reflexivity.
apply H in H0. unfold p4 in H0. inversion H0. subst. inversion H6.
subst. simpl in H7. assert (update st'0 Z 1 Z = update (update (update (update empty_state X 1) Z 1) X 0) Z 7 Z).
rewrite H7. reflexivity. rewrite update_eq in H1. rewrite update_eq in H1. inversion H1.
Qed.
Definition p5 : com :=
WHILE (BNot (BEq (AId X) (ANum 1))) DO
HAVOC X
END.
Definition p6 : com :=
X ::= ANum 1.
(* why does this hold? p5 loops until X is 1, then exists.
how to prove it? induct on while expression.
*)
Theorem p5_p6_equiv : cequiv p5 p6.
Proof.
unfold cequiv. intros. unfold p5. unfold p6. split; intros.
Case "->". inversion H.
Admitted.
(** [] *)
End Himp.
(* ####################################################### *)
(** * Doing Without Extensionality (Optional) *)
(** Purists might object to using the [functional_extensionality]
axiom. In general, it can be quite dangerous to add axioms,
particularly several at once (as they may be mutually
inconsistent). In fact, [functional_extensionality] and
[excluded_middle] can both be assumed without any problems, but
some Coq users prefer to avoid such "heavyweight" general
techniques, and instead craft solutions for specific problems that
stay within Coq's standard logic.
For our particular problem here, rather than extending the
definition of equality to do what we want on functions
representing states, we could instead give an explicit notion of
_equivalence_ on states. For example: *)
Definition stequiv (st1 st2 : state) : Prop :=
forall (X:id), st1 X = st2 X.
Notation "st1 '~' st2" := (stequiv st1 st2) (at level 30).
(** It is easy to prove that [stequiv] is an _equivalence_ (i.e., it
is reflexive, symmetric, and transitive), so it partitions the set
of all states into equivalence classes. *)
(** **** Exercise: 1 star, optional (stequiv_refl) *)
Lemma stequiv_refl : forall (st : state),
st ~ st.
Proof.
intros. unfold stequiv. intro. reflexivity.
Qed.
(** [] *)
(** **** Exercise: 1 star, optional (stequiv_sym) *)
Lemma stequiv_sym : forall (st1 st2 : state),
st1 ~ st2 ->
st2 ~ st1.
Proof.
unfold stequiv. intros. symmetry. apply H.
Qed.
(** [] *)
(** **** Exercise: 1 star, optional (stequiv_trans) *)
Lemma stequiv_trans : forall (st1 st2 st3 : state),
st1 ~ st2 ->
st2 ~ st3 ->
st1 ~ st3.
Proof.
unfold stequiv. intros. rewrite H. rewrite H0. reflexivity.
Qed.
(** [] *)
(** Another useful fact... *)
(** **** Exercise: 1 star, optional (stequiv_update) *)
Lemma stequiv_update : forall (st1 st2 : state),
st1 ~ st2 ->
forall (X:id) (n:nat),
update st1 X n ~ update st2 X n.
Proof.
unfold stequiv. intros.
assert ({X=X0} + {X<>X0}) by (apply eq_id_dec).
inversion H0. rewrite H1. rewrite update_eq. rewrite update_eq. reflexivity.
rewrite update_neq. rewrite update_neq. apply H.
assert (st1 X0 = st2 X0) by (apply H). assumption. assumption.
Qed.
(** [] *)
(** It is then straightforward to show that [aeval] and [beval] behave
uniformly on all members of an equivalence class: *)
(** **** Exercise: 2 stars, optional (stequiv_aeval) *)
Lemma stequiv_aeval : forall (st1 st2 : state),
st1 ~ st2 ->
forall (a:aexp), aeval st1 a = aeval st2 a.
Proof.
intros. aexp_cases (induction a) Case;
try reflexivity;
try (simpl; apply H);
try (simpl; rewrite IHa1; rewrite IHa2; reflexivity).
Qed.
(** [] *)
(** **** Exercise: 2 stars, optional (stequiv_beval) *)
Lemma stequiv_beval : forall (st1 st2 : state),
st1 ~ st2 ->
forall (b:bexp), beval st1 b = beval st2 b.
Proof.
intros. bexp_cases (induction b) Case;
try reflexivity;
try (simpl;
replace (aeval st2 a) with (aeval st1 a) by (apply stequiv_aeval; assumption);
replace (aeval st2 a0) with (aeval st1 a0) by (apply stequiv_aeval; assumption);
reflexivity).
simpl. rewrite IHb. reflexivity.
simpl. rewrite IHb1. rewrite IHb2. reflexivity.
Qed.
(** [] *)
(** We can also characterize the behavior of [ceval] on equivalent
states (this result is a bit more complicated to write down
because [ceval] is a relation). *)
Lemma stequiv_ceval: forall (st1 st2 : state),
st1 ~ st2 ->
forall (c: com) (st1': state),
(c / st1 || st1') ->
exists st2' : state,
((c / st2 || st2') /\ st1' ~ st2').
Proof.
intros st1 st2 STEQV c st1' CEV1. generalize dependent st2.
induction CEV1; intros st2 STEQV.
Case "SKIP".
exists st2. split.
constructor.
assumption.
Case ":=".
exists (update st2 x n). split.
constructor. rewrite <- H. symmetry. apply stequiv_aeval.
assumption. apply stequiv_update. assumption.
Case ";".
destruct (IHCEV1_1 st2 STEQV) as [st2' [P1 EQV1]].
destruct (IHCEV1_2 st2' EQV1) as [st2'' [P2 EQV2]].
exists st2''. split.
apply E_Seq with st2'; assumption.
assumption.
Case "IfTrue".
destruct (IHCEV1 st2 STEQV) as [st2' [P EQV]].
exists st2'. split.
apply E_IfTrue. rewrite <- H. symmetry. apply stequiv_beval.
assumption. assumption. assumption.
Case "IfFalse".
destruct (IHCEV1 st2 STEQV) as [st2' [P EQV]].
exists st2'. split.
apply E_IfFalse. rewrite <- H. symmetry. apply stequiv_beval.
assumption. assumption. assumption.
Case "WhileEnd".
exists st2. split.
apply E_WhileEnd. rewrite <- H. symmetry. apply stequiv_beval.
assumption. assumption.
Case "WhileLoop".
destruct (IHCEV1_1 st2 STEQV) as [st2' [P1 EQV1]].
destruct (IHCEV1_2 st2' EQV1) as [st2'' [P2 EQV2]].
exists st2''. split.
apply E_WhileLoop with st2'. rewrite <- H. symmetry.
apply stequiv_beval. assumption. assumption. assumption.
assumption.
Qed.
(** Now we need to redefine [cequiv] to use [~] instead of [=]. It is
not completely trivial to do this in a way that keeps the
definition simple and symmetric, but here is one approach (thanks
to Andrew McCreight). We first define a looser variant of [||]
that "folds in" the notion of equivalence. *)
Reserved Notation "c1 '/' st '||'' st'" (at level 40, st at level 39).
Inductive ceval' : com -> state -> state -> Prop :=
| E_equiv : forall c st st' st'',
c / st || st' ->
st' ~ st'' ->
c / st ||' st''
where "c1 '/' st '||'' st'" := (ceval' c1 st st').
(** Now the revised definition of [cequiv'] looks familiar: *)
Definition cequiv' (c1 c2 : com) : Prop :=
forall (st st' : state),
(c1 / st ||' st') <-> (c2 / st ||' st').
(** A sanity check shows that the original notion of command
equivalence is at least as strong as this new one. (The converse
is not true, naturally.) *)
Lemma cequiv__cequiv' : forall (c1 c2: com),
cequiv c1 c2 -> cequiv' c1 c2.
Proof.
unfold cequiv, cequiv'; split; intros.
inversion H0 ; subst. apply E_equiv with st'0.
apply (H st st'0); assumption. assumption.
inversion H0 ; subst. apply E_equiv with st'0.
apply (H st st'0). assumption. assumption.
Qed.
(** **** Exercise: 2 stars, optional (identity_assignment') *)
(** Finally, here is our example once more... (You can complete the
proof.) *)
Example identity_assignment' :
cequiv' SKIP (X ::= AId X).
Proof.
unfold cequiv'. intros. split; intros.
Case "->".
inversion H; subst; clear H. inversion H0; subst.
apply E_equiv with (update st'0 X (st'0 X)).
constructor. reflexivity. apply stequiv_trans with st'0.
unfold stequiv. intros. apply update_same.
reflexivity. assumption.
Case "<-".
inversion H; subst. inversion H0; subst.
apply E_equiv with (st':=st). apply E_Skip.
(*apply stequiv_sym. apply *)
apply stequiv_trans with (update st X (aeval st (AId X))). simpl.
unfold stequiv. symmetry.
(* This is pretty close *)
Admitted.
(* FILL IN HERE *) Admitted.
(** [] *)
(** On the whole, this explicit equivalence approach is considerably
harder to work with than relying on functional
extensionality. (Coq does have an advanced mechanism called
"setoids" that makes working with equivalences somewhat easier, by
allowing them to be registered with the system so that standard
rewriting tactics work for them almost as well as for equalities.)
But it is worth knowing about, because it applies even in
situations where the equivalence in question is _not_ over
functions. For example, if we chose to represent state mappings
as binary search trees, we would need to use an explicit
equivalence of this kind. *)
(* ####################################################### *)
(** * Additional Exercises *)
(** **** Exercise: 4 stars, optional (for_while_equiv) *)
(** This exercise extends the optional [add_for_loop] exercise from
Imp.v, where you were asked to extend the language of commands
with C-style [for] loops. Prove that the command:
for (c1 ; b ; c2) {
c3
}
is equivalent to:
c1 ;
WHILE b DO
c3 ;
c2
END
*)
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 3 stars, optional (swap_noninterfering_assignments) *)
Theorem swap_noninterfering_assignments: forall l1 l2 a1 a2,
l1 <> l2 ->
var_not_used_in_aexp l1 a2 ->
var_not_used_in_aexp l2 a1 ->
cequiv
(l1 ::= a1;; l2 ::= a2)
(l2 ::= a2;; l1 ::= a1).
Proof.
(* Hint: You'll need [functional_extensionality] *)
(* FILL IN HERE *) Admitted.
(** [] *)
|
/******************************************************************************/
/* FPGA Sort for VC707 ArchLab. TOKYO TECH */
/* Version 2014-11-26 */
/******************************************************************************/
`default_nettype none
`include "define.v"
`include "core.v"
/******************************************************************************/
module top_sim;
reg CLK, RST;
wire CLK100M = CLK;
wire d_busy;
wire d_w;
wire [`DRAMW-1:0] d_din;
wire [`DRAMW-1:0] d_dout;
wire d_douten;
wire [1:0] d_req; // DRAM access request (read/write)
wire [31:0] d_initadr; // dram initial address for the access
wire [31:0] d_blocks; // the number of blocks per one access(read/write)
wire initdone;
wire sortdone;
initial begin CLK=0; forever #50 CLK=~CLK; end
initial begin RST=1; #400 RST=0; end
reg [31:0] cnt;
always @(posedge CLK) cnt <= (RST) ? 0 : cnt + 1;
reg [31:0] lcnt;
always @(posedge CLK) lcnt <= (RST) ? 0 : (c.last_phase && c.initdone) ? lcnt + 1 : lcnt;
reg [31:0] cnt0_0, cnt1_0, cnt2_0, cnt3_0, cnt4_0, cnt5_0, cnt6_0, cnt7_0, cnt8_0;
always @(posedge CLK) cnt0_0 <= (RST) ? 0 : (c.phase_a==0 && c.initdone) ? cnt0_0 + 1 : cnt0_0;
always @(posedge CLK) cnt1_0 <= (RST) ? 0 : (c.phase_a==1 && c.initdone) ? cnt1_0 + 1 : cnt1_0;
always @(posedge CLK) cnt2_0 <= (RST) ? 0 : (c.phase_a==2 && c.initdone) ? cnt2_0 + 1 : cnt2_0;
always @(posedge CLK) cnt3_0 <= (RST) ? 0 : (c.phase_a==3 && c.initdone) ? cnt3_0 + 1 : cnt3_0;
always @(posedge CLK) cnt4_0 <= (RST) ? 0 : (c.phase_a==4 && c.initdone) ? cnt4_0 + 1 : cnt4_0;
always @(posedge CLK) cnt5_0 <= (RST) ? 0 : (c.phase_a==5 && c.initdone) ? cnt5_0 + 1 : cnt5_0;
always @(posedge CLK) cnt6_0 <= (RST) ? 0 : (c.phase_a==6 && c.initdone) ? cnt6_0 + 1 : cnt6_0;
always @(posedge CLK) cnt7_0 <= (RST) ? 0 : (c.phase_a==7 && c.initdone) ? cnt7_0 + 1 : cnt7_0;
always @(posedge CLK) cnt8_0 <= (RST) ? 0 : (c.phase_a==8 && c.initdone) ? cnt8_0 + 1 : cnt8_0;
reg [31:0] cnt0_1, cnt1_1, cnt2_1, cnt3_1, cnt4_1, cnt5_1, cnt6_1, cnt7_1, cnt8_1;
always @(posedge CLK) cnt0_1 <= (RST) ? 0 : (c.phase_b==0 && c.initdone) ? cnt0_1 + 1 : cnt0_1;
always @(posedge CLK) cnt1_1 <= (RST) ? 0 : (c.phase_b==1 && c.initdone) ? cnt1_1 + 1 : cnt1_1;
always @(posedge CLK) cnt2_1 <= (RST) ? 0 : (c.phase_b==2 && c.initdone) ? cnt2_1 + 1 : cnt2_1;
always @(posedge CLK) cnt3_1 <= (RST) ? 0 : (c.phase_b==3 && c.initdone) ? cnt3_1 + 1 : cnt3_1;
always @(posedge CLK) cnt4_1 <= (RST) ? 0 : (c.phase_b==4 && c.initdone) ? cnt4_1 + 1 : cnt4_1;
always @(posedge CLK) cnt5_1 <= (RST) ? 0 : (c.phase_b==5 && c.initdone) ? cnt5_1 + 1 : cnt5_1;
always @(posedge CLK) cnt6_1 <= (RST) ? 0 : (c.phase_b==6 && c.initdone) ? cnt6_1 + 1 : cnt6_1;
always @(posedge CLK) cnt7_1 <= (RST) ? 0 : (c.phase_b==7 && c.initdone) ? cnt7_1 + 1 : cnt7_1;
always @(posedge CLK) cnt8_1 <= (RST) ? 0 : (c.phase_b==8 && c.initdone) ? cnt8_1 + 1 : cnt8_1;
generate
if (`INITTYPE=="reverse" || `INITTYPE=="sorted") begin
always @(posedge CLK) begin /// note
if (c.initdone) begin
$write("%d|%d|state(%d)", cnt[19:0], c.last_phase, c.state);
$write("|");
$write("P0%d(%d)|P1%d(%d)|P2%d(%d)|P3%d(%d)",
c.phase_a[2:0], c.pchange_a, c.phase_b[2:0], c.pchange_b,
c.phase_c[2:0], c.pchange_c, c.phase_d[2:0], c.pchange_d);
$write("|");
$write("|");
if (c.F01_deq0) $write("%d", c.F01_dot0); else $write(" ");
if (c.F01_deq1) $write("%d", c.F01_dot1); else $write(" ");
if (c.F01_deq2) $write("%d", c.F01_dot2); else $write(" ");
if (c.F01_deq3) $write("%d", c.F01_dot3); else $write(" ");
if (d.app_wdf_wren) $write(" |M%d %d ", d_din[63:32], d_din[31:0]);
$write("\n");
$fflush();
end
end
always @(posedge CLK) begin
if(c.sortdone) begin : simulation_finish
$write("\nIt takes %d cycles\n", cnt);
$write("last(%1d): %d cycles\n", `LAST_PHASE, lcnt);
$write("phase_a: %d %d cycles\n", cnt0_0, cnt0_1);
$write("phase_b: %d %d cycles\n", cnt1_0, cnt1_1);
$write("phase2: %d %d cycles\n", cnt2_0, cnt2_1);
$write("phase3: %d %d cycles\n", cnt3_0, cnt3_1);
$write("phase4: %d %d cycles\n", cnt4_0, cnt4_1);
$write("phase5: %d %d cycles\n", cnt5_0, cnt5_1);
$write("phase6: %d %d cycles\n", cnt6_0, cnt6_1);
$write("phase7: %d %d cycles\n", cnt7_0, cnt7_1);
$write("phase8: %d %d cycles\n", cnt8_0, cnt8_1);
$write("Sorting finished!\n");
$finish();
end
end
end else if (`INITTYPE == "xorshift") begin
integer fp;
initial begin
fp = $fopen("test.txt", "w");
end
always @(posedge CLK) begin /// note
if (c.last_phase && c.F01_deq0) begin
$write("%08x ", c.F01_dot0);
$fwrite(fp, "%08x ", c.F01_dot0);
$fflush();
end
if (c.sortdone) begin
$fclose(fp);
$finish();
end
end
end
endgenerate
/***** DRAM Controller & DRAM Instantiation *****/
/**********************************************************************************************/
DRAM d(CLK, RST, d_req, d_initadr, d_blocks, d_din, d_w, d_dout, d_douten, d_busy);
wire ERROR;
/***** Core Module Instantiation *****/
/**********************************************************************************************/
CORE c(CLK100M, RST, initdone, sortdone,
d_busy, d_din, d_w, d_dout, d_douten, d_req, d_initadr, d_blocks, ERROR);
endmodule
/**************************************************************************************************/
/**************************************************************************************************/
module DRAM (input wire CLK, //
input wire RST, //
input wire [1:0] D_REQ, // dram request, load or store
input wire [31:0] D_INITADR, // dram request, initial address
input wire [31:0] D_ELEM, // dram request, the number of elements
input wire [`DRAMW-1:0] D_DIN, //
output wire D_W, //
output reg [`DRAMW-1:0] D_DOUT, //
output reg D_DOUTEN, //
output wire D_BUSY); //
/******* DRAM ******************************************************/
localparam M_REQ = 0;
localparam M_WRITE = 1;
localparam M_READ = 2;
///////////////////////////////////////////////////////////////////////////////////
reg [`DDR3_CMD] app_cmd;
reg app_en;
wire [`DRAMW-1:0] app_wdf_data;
reg app_wdf_wren;
wire app_wdf_end = app_wdf_wren;
// outputs of u_dram
wire [`DRAMW-1:0] app_rd_data;
wire app_rd_data_end;
wire app_rd_data_valid=1; // in simulation, always ready !!
wire app_rdy = 1; // in simulation, always ready !!
wire app_wdf_rdy = 1; // in simulation, always ready !!
wire ui_clk = CLK;
reg [1:0] mode;
reg [`DRAMW-1:0] app_wdf_data_buf;
reg [31:0] caddr; // check address
reg [31:0] remain, remain2; //
reg [7:0] req_state; //
///////////////////////////////////////////////////////////////////////////////////
reg [`DRAMW-1:0] mem [`DRAM_SIZE-1:0];
reg [31:0] app_addr;
reg [31:0] dram_addr;
always @(posedge CLK) dram_addr <= app_addr;
always @(posedge CLK) begin /***** DRAM WRITE *****/
if (RST) begin end
else if(app_wdf_wren) mem[dram_addr[27:3]] <= app_wdf_data;
end
assign app_rd_data = mem[app_addr[27:3]];
assign app_wdf_data = D_DIN;
assign D_BUSY = (mode!=M_REQ); // DRAM busy
assign D_W = (mode==M_WRITE && app_rdy && app_wdf_rdy); // store one element
///// READ & WRITE PORT CONTROL (begin) ////////////////////////////////////////////
always @(posedge ui_clk) begin
if (RST) begin
mode <= M_REQ;
{app_addr, app_cmd, app_en, app_wdf_wren} <= 0;
{D_DOUT, D_DOUTEN} <= 0;
{caddr, remain, remain2, req_state} <= 0;
end else begin
case (mode)
///////////////////////////////////////////////////////////////// request
M_REQ: begin
D_DOUTEN <= 0;
if(D_REQ==`DRAM_REQ_WRITE) begin ///// WRITE or STORE request
app_cmd <= `DRAM_CMD_WRITE;
mode <= M_WRITE;
app_wdf_wren <= 0;
app_en <= 1;
app_addr <= D_INITADR; // param, initial address
remain <= D_ELEM; // the number of blocks to be written
end
else if(D_REQ==`DRAM_REQ_READ) begin ///// READ or LOAD request
app_cmd <= `DRAM_CMD_READ;
mode <= M_READ;
app_wdf_wren <= 0;
app_en <= 1;
app_addr <= D_INITADR; // param, initial address
remain <= D_ELEM; // param, the number of blocks to be read
remain2 <= D_ELEM; // param, the number of blocks to be read
end
else begin
app_wdf_wren <= 0;
app_en <= 0;
end
end
//////////////////////////////////////////////////////////////////// read
M_READ: begin
if (app_rdy) begin // read request is accepted.
app_addr <= (app_addr==`MEM_LAST_ADDR) ? 0 : app_addr + 8;
remain2 <= remain2 - 1;
if(remain2==1) app_en <= 0;
end
D_DOUTEN <= app_rd_data_valid; // dram data_out enable
if (app_rd_data_valid) begin
D_DOUT <= app_rd_data;
caddr <= (caddr==`MEM_LAST_ADDR) ? 0 : caddr + 8;
remain <= remain - 1;
if(remain==1) begin
mode <= M_REQ;
end
end
end
/////////////////////////////////////////////////////////////////// write
M_WRITE: begin
if (app_rdy && app_wdf_rdy) begin
// app_wdf_data <= D_DIN;
app_wdf_wren <= 1;
app_addr <= (app_addr==`MEM_LAST_ADDR) ? 0 : app_addr + 8;
remain <= remain - 1;
if(remain==1) begin
mode <= M_REQ;
app_en <= 0;
end
end
else app_wdf_wren <= 0;
end
endcase
end
end
///// READ & WRITE PORT CONTROL (end) //////////////////////////////////////
endmodule
/**************************************************************************************************/
`default_nettype wire
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
// Date : Tue Apr 18 23:18:54 2017
// Host : DESKTOP-I9J3TQJ running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ bram_1024_0_sim_netlist.v
// Design : bram_1024_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "bram_1024_0,blk_mem_gen_v8_3_5,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "blk_mem_gen_v8_3_5,Vivado 2016.4" *)
(* NotValidForBitStream *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
(clka,
ena,
wea,
addra,
dina,
douta);
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *) input clka;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA EN" *) input ena;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *) input [0:0]wea;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *) input [9:0]addra;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *) input [19:0]dina;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *) output [19:0]douta;
wire [9:0]addra;
wire clka;
wire [19:0]dina;
wire [19:0]douta;
wire ena;
wire [0:0]wea;
wire NLW_U0_dbiterr_UNCONNECTED;
wire NLW_U0_rsta_busy_UNCONNECTED;
wire NLW_U0_rstb_busy_UNCONNECTED;
wire NLW_U0_s_axi_arready_UNCONNECTED;
wire NLW_U0_s_axi_awready_UNCONNECTED;
wire NLW_U0_s_axi_bvalid_UNCONNECTED;
wire NLW_U0_s_axi_dbiterr_UNCONNECTED;
wire NLW_U0_s_axi_rlast_UNCONNECTED;
wire NLW_U0_s_axi_rvalid_UNCONNECTED;
wire NLW_U0_s_axi_sbiterr_UNCONNECTED;
wire NLW_U0_s_axi_wready_UNCONNECTED;
wire NLW_U0_sbiterr_UNCONNECTED;
wire [19:0]NLW_U0_doutb_UNCONNECTED;
wire [9:0]NLW_U0_rdaddrecc_UNCONNECTED;
wire [3:0]NLW_U0_s_axi_bid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED;
wire [9:0]NLW_U0_s_axi_rdaddrecc_UNCONNECTED;
wire [19:0]NLW_U0_s_axi_rdata_UNCONNECTED;
wire [3:0]NLW_U0_s_axi_rid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED;
(* C_ADDRA_WIDTH = "10" *)
(* C_ADDRB_WIDTH = "10" *)
(* C_ALGORITHM = "1" *)
(* C_AXI_ID_WIDTH = "4" *)
(* C_AXI_SLAVE_TYPE = "0" *)
(* C_AXI_TYPE = "1" *)
(* C_BYTE_SIZE = "9" *)
(* C_COMMON_CLK = "0" *)
(* C_COUNT_18K_BRAM = "0" *)
(* C_COUNT_36K_BRAM = "1" *)
(* C_CTRL_ECC_ALGO = "NONE" *)
(* C_DEFAULT_DATA = "0" *)
(* C_DISABLE_WARN_BHV_COLL = "0" *)
(* C_DISABLE_WARN_BHV_RANGE = "0" *)
(* C_ELABORATION_DIR = "./" *)
(* C_ENABLE_32BIT_ADDRESS = "0" *)
(* C_EN_DEEPSLEEP_PIN = "0" *)
(* C_EN_ECC_PIPE = "0" *)
(* C_EN_RDADDRA_CHG = "0" *)
(* C_EN_RDADDRB_CHG = "0" *)
(* C_EN_SAFETY_CKT = "0" *)
(* C_EN_SHUTDOWN_PIN = "0" *)
(* C_EN_SLEEP_PIN = "0" *)
(* C_EST_POWER_SUMMARY = "Estimated Power for IP : 2.74095 mW" *)
(* C_FAMILY = "zynq" *)
(* C_HAS_AXI_ID = "0" *)
(* C_HAS_ENA = "1" *)
(* C_HAS_ENB = "0" *)
(* C_HAS_INJECTERR = "0" *)
(* C_HAS_MEM_OUTPUT_REGS_A = "1" *)
(* C_HAS_MEM_OUTPUT_REGS_B = "0" *)
(* C_HAS_MUX_OUTPUT_REGS_A = "0" *)
(* C_HAS_MUX_OUTPUT_REGS_B = "0" *)
(* C_HAS_REGCEA = "0" *)
(* C_HAS_REGCEB = "0" *)
(* C_HAS_RSTA = "0" *)
(* C_HAS_RSTB = "0" *)
(* C_HAS_SOFTECC_INPUT_REGS_A = "0" *)
(* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *)
(* C_INITA_VAL = "0" *)
(* C_INITB_VAL = "0" *)
(* C_INIT_FILE = "bram_1024_0.mem" *)
(* C_INIT_FILE_NAME = "bram_1024_0.mif" *)
(* C_INTERFACE_TYPE = "0" *)
(* C_LOAD_INIT_FILE = "1" *)
(* C_MEM_TYPE = "0" *)
(* C_MUX_PIPELINE_STAGES = "0" *)
(* C_PRIM_TYPE = "1" *)
(* C_READ_DEPTH_A = "1024" *)
(* C_READ_DEPTH_B = "1024" *)
(* C_READ_WIDTH_A = "20" *)
(* C_READ_WIDTH_B = "20" *)
(* C_RSTRAM_A = "0" *)
(* C_RSTRAM_B = "0" *)
(* C_RST_PRIORITY_A = "CE" *)
(* C_RST_PRIORITY_B = "CE" *)
(* C_SIM_COLLISION_CHECK = "ALL" *)
(* C_USE_BRAM_BLOCK = "0" *)
(* C_USE_BYTE_WEA = "0" *)
(* C_USE_BYTE_WEB = "0" *)
(* C_USE_DEFAULT_DATA = "0" *)
(* C_USE_ECC = "0" *)
(* C_USE_SOFTECC = "0" *)
(* C_USE_URAM = "0" *)
(* C_WEA_WIDTH = "1" *)
(* C_WEB_WIDTH = "1" *)
(* C_WRITE_DEPTH_A = "1024" *)
(* C_WRITE_DEPTH_B = "1024" *)
(* C_WRITE_MODE_A = "WRITE_FIRST" *)
(* C_WRITE_MODE_B = "WRITE_FIRST" *)
(* C_WRITE_WIDTH_A = "20" *)
(* C_WRITE_WIDTH_B = "20" *)
(* C_XDEVICEFAMILY = "zynq" *)
(* downgradeipidentifiedwarnings = "yes" *)
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 U0
(.addra(addra),
.addrb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.clka(clka),
.clkb(1'b0),
.dbiterr(NLW_U0_dbiterr_UNCONNECTED),
.deepsleep(1'b0),
.dina(dina),
.dinb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.douta(douta),
.doutb(NLW_U0_doutb_UNCONNECTED[19:0]),
.eccpipece(1'b0),
.ena(ena),
.enb(1'b0),
.injectdbiterr(1'b0),
.injectsbiterr(1'b0),
.rdaddrecc(NLW_U0_rdaddrecc_UNCONNECTED[9:0]),
.regcea(1'b0),
.regceb(1'b0),
.rsta(1'b0),
.rsta_busy(NLW_U0_rsta_busy_UNCONNECTED),
.rstb(1'b0),
.rstb_busy(NLW_U0_rstb_busy_UNCONNECTED),
.s_aclk(1'b0),
.s_aresetn(1'b0),
.s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arburst({1'b0,1'b0}),
.s_axi_arid({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED),
.s_axi_arsize({1'b0,1'b0,1'b0}),
.s_axi_arvalid(1'b0),
.s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awburst({1'b0,1'b0}),
.s_axi_awid({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED),
.s_axi_awsize({1'b0,1'b0,1'b0}),
.s_axi_awvalid(1'b0),
.s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[3:0]),
.s_axi_bready(1'b0),
.s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]),
.s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED),
.s_axi_dbiterr(NLW_U0_s_axi_dbiterr_UNCONNECTED),
.s_axi_injectdbiterr(1'b0),
.s_axi_injectsbiterr(1'b0),
.s_axi_rdaddrecc(NLW_U0_s_axi_rdaddrecc_UNCONNECTED[9:0]),
.s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[19:0]),
.s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[3:0]),
.s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED),
.s_axi_rready(1'b0),
.s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]),
.s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED),
.s_axi_sbiterr(NLW_U0_s_axi_sbiterr_UNCONNECTED),
.s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wlast(1'b0),
.s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED),
.s_axi_wstrb(1'b0),
.s_axi_wvalid(1'b0),
.sbiterr(NLW_U0_sbiterr_UNCONNECTED),
.shutdown(1'b0),
.sleep(1'b0),
.wea(wea),
.web(1'b0));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr
(douta,
clka,
ena,
addra,
dina,
wea);
output [19:0]douta;
input clka;
input ena;
input [9:0]addra;
input [19:0]dina;
input [0:0]wea;
wire [9:0]addra;
wire clka;
wire [19:0]dina;
wire [19:0]douta;
wire ena;
wire [0:0]wea;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width \ramloop[0].ram.r
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.ena(ena),
.wea(wea));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width
(douta,
clka,
ena,
addra,
dina,
wea);
output [19:0]douta;
input clka;
input ena;
input [9:0]addra;
input [19:0]dina;
input [0:0]wea;
wire [9:0]addra;
wire clka;
wire [19:0]dina;
wire [19:0]douta;
wire ena;
wire [0:0]wea;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init \prim_init.ram
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.ena(ena),
.wea(wea));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init
(douta,
clka,
ena,
addra,
dina,
wea);
output [19:0]douta;
input clka;
input ena;
input [9:0]addra;
input [19:0]dina;
input [0:0]wea;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_21 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_22 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_23 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_29 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_30 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_31 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_37 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_38 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_39 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_45 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_46 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_47 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_85 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_86 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_87 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88 ;
wire [9:0]addra;
wire clka;
wire [19:0]dina;
wire [19:0]douta;
wire ena;
wire [0:0]wea;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(36),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(36),
.WRITE_WIDTH_B(36))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,dina[19:15],1'b0,1'b0,1'b0,dina[14:10],1'b0,1'b0,1'b0,dina[9:5],1'b0,1'b0,1'b0,dina[4:0]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_21 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_22 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_23 ,douta[19:15],\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_29 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_30 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_31 ,douta[14:10],\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_37 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_38 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_39 ,douta[9:5],\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_45 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_46 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_47 ,douta[4:0]}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_85 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_86 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_87 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88 }),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(ena),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({wea,wea,wea,wea}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top
(douta,
clka,
ena,
addra,
dina,
wea);
output [19:0]douta;
input clka;
input ena;
input [9:0]addra;
input [19:0]dina;
input [0:0]wea;
wire [9:0]addra;
wire clka;
wire [19:0]dina;
wire [19:0]douta;
wire ena;
wire [0:0]wea;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr \valid.cstr
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.ena(ena),
.wea(wea));
endmodule
(* C_ADDRA_WIDTH = "10" *) (* C_ADDRB_WIDTH = "10" *) (* C_ALGORITHM = "1" *)
(* C_AXI_ID_WIDTH = "4" *) (* C_AXI_SLAVE_TYPE = "0" *) (* C_AXI_TYPE = "1" *)
(* C_BYTE_SIZE = "9" *) (* C_COMMON_CLK = "0" *) (* C_COUNT_18K_BRAM = "0" *)
(* C_COUNT_36K_BRAM = "1" *) (* C_CTRL_ECC_ALGO = "NONE" *) (* C_DEFAULT_DATA = "0" *)
(* C_DISABLE_WARN_BHV_COLL = "0" *) (* C_DISABLE_WARN_BHV_RANGE = "0" *) (* C_ELABORATION_DIR = "./" *)
(* C_ENABLE_32BIT_ADDRESS = "0" *) (* C_EN_DEEPSLEEP_PIN = "0" *) (* C_EN_ECC_PIPE = "0" *)
(* C_EN_RDADDRA_CHG = "0" *) (* C_EN_RDADDRB_CHG = "0" *) (* C_EN_SAFETY_CKT = "0" *)
(* C_EN_SHUTDOWN_PIN = "0" *) (* C_EN_SLEEP_PIN = "0" *) (* C_EST_POWER_SUMMARY = "Estimated Power for IP : 2.74095 mW" *)
(* C_FAMILY = "zynq" *) (* C_HAS_AXI_ID = "0" *) (* C_HAS_ENA = "1" *)
(* C_HAS_ENB = "0" *) (* C_HAS_INJECTERR = "0" *) (* C_HAS_MEM_OUTPUT_REGS_A = "1" *)
(* C_HAS_MEM_OUTPUT_REGS_B = "0" *) (* C_HAS_MUX_OUTPUT_REGS_A = "0" *) (* C_HAS_MUX_OUTPUT_REGS_B = "0" *)
(* C_HAS_REGCEA = "0" *) (* C_HAS_REGCEB = "0" *) (* C_HAS_RSTA = "0" *)
(* C_HAS_RSTB = "0" *) (* C_HAS_SOFTECC_INPUT_REGS_A = "0" *) (* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *)
(* C_INITA_VAL = "0" *) (* C_INITB_VAL = "0" *) (* C_INIT_FILE = "bram_1024_0.mem" *)
(* C_INIT_FILE_NAME = "bram_1024_0.mif" *) (* C_INTERFACE_TYPE = "0" *) (* C_LOAD_INIT_FILE = "1" *)
(* C_MEM_TYPE = "0" *) (* C_MUX_PIPELINE_STAGES = "0" *) (* C_PRIM_TYPE = "1" *)
(* C_READ_DEPTH_A = "1024" *) (* C_READ_DEPTH_B = "1024" *) (* C_READ_WIDTH_A = "20" *)
(* C_READ_WIDTH_B = "20" *) (* C_RSTRAM_A = "0" *) (* C_RSTRAM_B = "0" *)
(* C_RST_PRIORITY_A = "CE" *) (* C_RST_PRIORITY_B = "CE" *) (* C_SIM_COLLISION_CHECK = "ALL" *)
(* C_USE_BRAM_BLOCK = "0" *) (* C_USE_BYTE_WEA = "0" *) (* C_USE_BYTE_WEB = "0" *)
(* C_USE_DEFAULT_DATA = "0" *) (* C_USE_ECC = "0" *) (* C_USE_SOFTECC = "0" *)
(* C_USE_URAM = "0" *) (* C_WEA_WIDTH = "1" *) (* C_WEB_WIDTH = "1" *)
(* C_WRITE_DEPTH_A = "1024" *) (* C_WRITE_DEPTH_B = "1024" *) (* C_WRITE_MODE_A = "WRITE_FIRST" *)
(* C_WRITE_MODE_B = "WRITE_FIRST" *) (* C_WRITE_WIDTH_A = "20" *) (* C_WRITE_WIDTH_B = "20" *)
(* C_XDEVICEFAMILY = "zynq" *) (* downgradeipidentifiedwarnings = "yes" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5
(clka,
rsta,
ena,
regcea,
wea,
addra,
dina,
douta,
clkb,
rstb,
enb,
regceb,
web,
addrb,
dinb,
doutb,
injectsbiterr,
injectdbiterr,
eccpipece,
sbiterr,
dbiterr,
rdaddrecc,
sleep,
deepsleep,
shutdown,
rsta_busy,
rstb_busy,
s_aclk,
s_aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
s_axi_injectsbiterr,
s_axi_injectdbiterr,
s_axi_sbiterr,
s_axi_dbiterr,
s_axi_rdaddrecc);
input clka;
input rsta;
input ena;
input regcea;
input [0:0]wea;
input [9:0]addra;
input [19:0]dina;
output [19:0]douta;
input clkb;
input rstb;
input enb;
input regceb;
input [0:0]web;
input [9:0]addrb;
input [19:0]dinb;
output [19:0]doutb;
input injectsbiterr;
input injectdbiterr;
input eccpipece;
output sbiterr;
output dbiterr;
output [9:0]rdaddrecc;
input sleep;
input deepsleep;
input shutdown;
output rsta_busy;
output rstb_busy;
input s_aclk;
input s_aresetn;
input [3:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input s_axi_awvalid;
output s_axi_awready;
input [19:0]s_axi_wdata;
input [0:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [3:0]s_axi_bid;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [3:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input s_axi_arvalid;
output s_axi_arready;
output [3:0]s_axi_rid;
output [19:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
input s_axi_injectsbiterr;
input s_axi_injectdbiterr;
output s_axi_sbiterr;
output s_axi_dbiterr;
output [9:0]s_axi_rdaddrecc;
wire \<const0> ;
wire [9:0]addra;
wire clka;
wire [19:0]dina;
wire [19:0]douta;
wire ena;
wire [0:0]wea;
assign dbiterr = \<const0> ;
assign doutb[19] = \<const0> ;
assign doutb[18] = \<const0> ;
assign doutb[17] = \<const0> ;
assign doutb[16] = \<const0> ;
assign doutb[15] = \<const0> ;
assign doutb[14] = \<const0> ;
assign doutb[13] = \<const0> ;
assign doutb[12] = \<const0> ;
assign doutb[11] = \<const0> ;
assign doutb[10] = \<const0> ;
assign doutb[9] = \<const0> ;
assign doutb[8] = \<const0> ;
assign doutb[7] = \<const0> ;
assign doutb[6] = \<const0> ;
assign doutb[5] = \<const0> ;
assign doutb[4] = \<const0> ;
assign doutb[3] = \<const0> ;
assign doutb[2] = \<const0> ;
assign doutb[1] = \<const0> ;
assign doutb[0] = \<const0> ;
assign rdaddrecc[9] = \<const0> ;
assign rdaddrecc[8] = \<const0> ;
assign rdaddrecc[7] = \<const0> ;
assign rdaddrecc[6] = \<const0> ;
assign rdaddrecc[5] = \<const0> ;
assign rdaddrecc[4] = \<const0> ;
assign rdaddrecc[3] = \<const0> ;
assign rdaddrecc[2] = \<const0> ;
assign rdaddrecc[1] = \<const0> ;
assign rdaddrecc[0] = \<const0> ;
assign rsta_busy = \<const0> ;
assign rstb_busy = \<const0> ;
assign s_axi_arready = \<const0> ;
assign s_axi_awready = \<const0> ;
assign s_axi_bid[3] = \<const0> ;
assign s_axi_bid[2] = \<const0> ;
assign s_axi_bid[1] = \<const0> ;
assign s_axi_bid[0] = \<const0> ;
assign s_axi_bresp[1] = \<const0> ;
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_bvalid = \<const0> ;
assign s_axi_dbiterr = \<const0> ;
assign s_axi_rdaddrecc[9] = \<const0> ;
assign s_axi_rdaddrecc[8] = \<const0> ;
assign s_axi_rdaddrecc[7] = \<const0> ;
assign s_axi_rdaddrecc[6] = \<const0> ;
assign s_axi_rdaddrecc[5] = \<const0> ;
assign s_axi_rdaddrecc[4] = \<const0> ;
assign s_axi_rdaddrecc[3] = \<const0> ;
assign s_axi_rdaddrecc[2] = \<const0> ;
assign s_axi_rdaddrecc[1] = \<const0> ;
assign s_axi_rdaddrecc[0] = \<const0> ;
assign s_axi_rdata[19] = \<const0> ;
assign s_axi_rdata[18] = \<const0> ;
assign s_axi_rdata[17] = \<const0> ;
assign s_axi_rdata[16] = \<const0> ;
assign s_axi_rdata[15] = \<const0> ;
assign s_axi_rdata[14] = \<const0> ;
assign s_axi_rdata[13] = \<const0> ;
assign s_axi_rdata[12] = \<const0> ;
assign s_axi_rdata[11] = \<const0> ;
assign s_axi_rdata[10] = \<const0> ;
assign s_axi_rdata[9] = \<const0> ;
assign s_axi_rdata[8] = \<const0> ;
assign s_axi_rdata[7] = \<const0> ;
assign s_axi_rdata[6] = \<const0> ;
assign s_axi_rdata[5] = \<const0> ;
assign s_axi_rdata[4] = \<const0> ;
assign s_axi_rdata[3] = \<const0> ;
assign s_axi_rdata[2] = \<const0> ;
assign s_axi_rdata[1] = \<const0> ;
assign s_axi_rdata[0] = \<const0> ;
assign s_axi_rid[3] = \<const0> ;
assign s_axi_rid[2] = \<const0> ;
assign s_axi_rid[1] = \<const0> ;
assign s_axi_rid[0] = \<const0> ;
assign s_axi_rlast = \<const0> ;
assign s_axi_rresp[1] = \<const0> ;
assign s_axi_rresp[0] = \<const0> ;
assign s_axi_rvalid = \<const0> ;
assign s_axi_sbiterr = \<const0> ;
assign s_axi_wready = \<const0> ;
assign sbiterr = \<const0> ;
GND GND
(.G(\<const0> ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5_synth inst_blk_mem_gen
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.ena(ena),
.wea(wea));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5_synth
(douta,
clka,
ena,
addra,
dina,
wea);
output [19:0]douta;
input clka;
input ena;
input [9:0]addra;
input [19:0]dina;
input [0:0]wea;
wire [9:0]addra;
wire clka;
wire [19:0]dina;
wire [19:0]douta;
wire ena;
wire [0:0]wea;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top \gnbram.gnativebmg.native_blk_mem_gen
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.ena(ena),
.wea(wea));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : PCIEBus_gt_wrapper.v
// Version : 1.11
//------------------------------------------------------------------------------
// Filename : gt_wrapper.v
// Description : GT Wrapper Module for 7 Series Transceiver
// Version : 19.0
//------------------------------------------------------------------------------
`timescale 1ns / 1ps
//---------- GT Wrapper --------------------------------------------------------
module PCIEBus_gt_wrapper #
(
parameter PCIE_SIM_MODE = "FALSE", // PCIe sim mode
parameter PCIE_SIM_SPEEDUP = "FALSE", // PCIe sim speedup
parameter PCIE_SIM_TX_EIDLE_DRIVE_LEVEL = "1", // PCIe sim TX electrical idle drive level
parameter PCIE_GT_DEVICE = "GTX", // PCIe GT device
parameter PCIE_USE_MODE = "3.0", // PCIe use mode
parameter PCIE_PLL_SEL = "CPLL", // PCIe PLL select for Gen1/Gen2
parameter PCIE_LPM_DFE = "LPM", // PCIe LPM or DFE mode for Gen1/Gen2 only
parameter PCIE_LPM_DFE_GEN3 = "DFE", // PCIe LPM or DFE mode for Gen3 only
parameter PCIE_ASYNC_EN = "FALSE", // PCIe async enable
parameter PCIE_TXBUF_EN = "FALSE", // PCIe TX buffer enable for Gen1/Gen2 only
parameter PCIE_TXSYNC_MODE = 0, // PCIe TX sync mode
parameter PCIE_RXSYNC_MODE = 0, // PCIe RX sync mode
parameter PCIE_CHAN_BOND = 0, // PCIe channel bonding mode
parameter PCIE_CHAN_BOND_EN = "TRUE", // PCIe channel bonding enable for Gen1/Gen2 only
parameter PCIE_LANE = 1, // PCIe number of lane
parameter PCIE_REFCLK_FREQ = 0, // PCIe reference clock frequency
parameter PCIE_TX_EIDLE_ASSERT_DELAY = 3'd4, // PCIe TX electrical idle assert delay
parameter PCIE_OOBCLK_MODE = 1, // PCIe OOB clock mode
parameter PCIE_DEBUG_MODE = 0 // PCIe debug mode
)
(
//---------- GT User Ports -----------------------------
input GT_MASTER,
input GT_GEN3,
input GT_RX_CONVERGE,
//---------- GT Clock Ports ----------------------------
input GT_GTREFCLK0,
input GT_QPLLCLK,
input GT_QPLLREFCLK,
input GT_TXUSRCLK,
input GT_RXUSRCLK,
input GT_TXUSRCLK2,
input GT_RXUSRCLK2,
input GT_OOBCLK,
input [ 1:0] GT_TXSYSCLKSEL,
input [ 1:0] GT_RXSYSCLKSEL,
output GT_TXOUTCLK,
output GT_RXOUTCLK,
output GT_CPLLLOCK,
output GT_RXCDRLOCK,
//---------- GT Reset Ports ----------------------------
input GT_CPLLPD,
input GT_CPLLRESET,
input GT_TXUSERRDY,
input GT_RXUSERRDY,
input GT_RESETOVRD,
input GT_GTTXRESET,
input GT_GTRXRESET,
input GT_TXPMARESET,
input GT_RXPMARESET,
input GT_RXCDRRESET,
input GT_RXCDRFREQRESET,
input GT_RXDFELPMRESET,
input GT_EYESCANRESET,
input GT_TXPCSRESET,
input GT_RXPCSRESET,
input GT_RXBUFRESET,
output GT_TXRESETDONE,
output GT_RXRESETDONE,
output GT_RXPMARESETDONE,
//---------- GT TX Data Ports --------------------------
input [31:0] GT_TXDATA,
input [ 3:0] GT_TXDATAK,
output GT_TXP,
output GT_TXN,
//---------- GT RX Data Ports --------------------------
input GT_RXN,
input GT_RXP,
output [31:0] GT_RXDATA,
output [ 3:0] GT_RXDATAK,
//---------- GT Command Ports --------------------------
input GT_TXDETECTRX,
input GT_TXELECIDLE,
input GT_TXCOMPLIANCE,
input GT_RXPOLARITY,
input [ 1:0] GT_TXPOWERDOWN,
input [ 1:0] GT_RXPOWERDOWN,
input [ 2:0] GT_TXRATE,
input [ 2:0] GT_RXRATE,
//---------- GT Electrical Command Ports ---------------
input [ 2:0] GT_TXMARGIN,
input GT_TXSWING,
input GT_TXDEEMPH,
input [ 4:0] GT_TXPRECURSOR,
input [ 6:0] GT_TXMAINCURSOR,
input [ 4:0] GT_TXPOSTCURSOR,
//---------- GT Status Ports ---------------------------
output GT_RXVALID,
output GT_PHYSTATUS,
output GT_RXELECIDLE,
output [ 2:0] GT_RXSTATUS,
output [ 2:0] GT_RXBUFSTATUS,
output GT_TXRATEDONE,
output GT_RXRATEDONE,
//---------- GT DRP Ports ------------------------------
input GT_DRPCLK,
input [ 8:0] GT_DRPADDR,
input GT_DRPEN,
input [15:0] GT_DRPDI,
input GT_DRPWE,
output [15:0] GT_DRPDO,
output GT_DRPRDY,
//---------- GT TX Sync Ports --------------------------
input GT_TXPHALIGN,
input GT_TXPHALIGNEN,
input GT_TXPHINIT,
input GT_TXDLYBYPASS,
input GT_TXDLYSRESET,
input GT_TXDLYEN,
output GT_TXDLYSRESETDONE,
output GT_TXPHINITDONE,
output GT_TXPHALIGNDONE,
input GT_TXPHDLYRESET,
input GT_TXSYNCMODE, // GTH
input GT_TXSYNCIN, // GTH
input GT_TXSYNCALLIN, // GTH
output GT_TXSYNCOUT, // GTH
output GT_TXSYNCDONE, // GTH
//---------- GT RX Sync Ports --------------------------
input GT_RXPHALIGN,
input GT_RXPHALIGNEN,
input GT_RXDLYBYPASS,
input GT_RXDLYSRESET,
input GT_RXDLYEN,
input GT_RXDDIEN,
output GT_RXDLYSRESETDONE,
output GT_RXPHALIGNDONE,
input GT_RXSYNCMODE, // GTH
input GT_RXSYNCIN, // GTH
input GT_RXSYNCALLIN, // GTH
output GT_RXSYNCOUT, // GTH
output GT_RXSYNCDONE, // GTH
//---------- GT Comma Alignment Ports ------------------
input GT_RXSLIDE,
output GT_RXCOMMADET,
output [ 3:0] GT_RXCHARISCOMMA,
output GT_RXBYTEISALIGNED,
output GT_RXBYTEREALIGN,
//---------- GT Channel Bonding Ports ------------------
input GT_RXCHBONDEN,
input [ 4:0] GT_RXCHBONDI,
input [ 2:0] GT_RXCHBONDLEVEL,
input GT_RXCHBONDMASTER,
input GT_RXCHBONDSLAVE,
output GT_RXCHANISALIGNED,
output [ 4:0] GT_RXCHBONDO,
//---------- GT PRBS/Loopback Ports --------------------
input [ 2:0] GT_TXPRBSSEL,
input [ 2:0] GT_RXPRBSSEL,
input GT_TXPRBSFORCEERR,
input GT_RXPRBSCNTRESET,
input [ 2:0] GT_LOOPBACK,
output GT_RXPRBSERR,
//---------- GT Debug Ports ----------------------------
output [14:0] GT_DMONITOROUT
);
//---------- Internal Signals --------------------------
wire [ 2:0] txoutclksel;
wire [ 2:0] rxoutclksel;
wire [63:0] rxdata;
wire [ 7:0] rxdatak;
wire [ 7:0] rxchariscomma;
wire rxlpmen;
wire [14:0] dmonitorout;
wire dmonitorclk;
//---------- Select CPLL and Clock Dividers ------------
localparam CPLL_REFCLK_DIV = 1;
localparam CPLL_FBDIV_45 = 5;
localparam CPLL_FBDIV = (PCIE_REFCLK_FREQ == 2) ? 2 :
(PCIE_REFCLK_FREQ == 1) ? 4 : 5;
localparam OUT_DIV = (PCIE_PLL_SEL == "QPLL") ? 4 : 2;
localparam CLK25_DIV = (PCIE_REFCLK_FREQ == 2) ? 10 :
(PCIE_REFCLK_FREQ == 1) ? 5 : 4;
//---------- Select IES vs. GES ------------------------
localparam CLKMUX_PD = ((PCIE_USE_MODE == "1.0") || (PCIE_USE_MODE == "1.1")) ? 1'd0 : 1'd1;
//---------- Select GTP CPLL configuration -------------
// PLL0/1_CFG[ 5:2] = CP1 : [ 8, 4, 2, 1] units
// PLL0/1_CFG[10:6] = CP2 : [16, 8, 4, 2, 1] units
// CP2/CP1 = 2 to 3
// (8/4=2) = 27'h01F0210 = 0000_0001_1111_0000_0010_0001_0000
// (9/3=3) = 27'h01F024C = 0000_0001_1111_0000_0010_0100_1100
// (8/3=2.67) = 27'h01F020C = 0000_0001_1111_0000_0010_0000_1100
// (7/3=2.33) = 27'h01F01CC = 0000_0001_1111_0000_0001_1100_1100
// (6/3=2) = 27'h01F018C = 0000_0001_1111_0000_0001_1000_1100
// (5/3=1.67) = 27'h01F014C = 0000_0001_1111_0000_0001_0100_1100
// (6/2=3) = 27'h01F0188 = 0000_0001_1111_0000_0001_1000_1000
//---------- Select GTX CPLL configuration -------------
// CPLL_CFG[ 5: 2] = CP1 : [ 8, 4, 2, 1] units
// CPLL_CFG[22:18] = CP2 : [16, 8, 4, 2, 1] units
// CP2/CP1 = 2 to 3
// (9/3=3) = 1010_0100_0000_0111_1100_1100
//------------------------------------------------------
localparam CPLL_CFG = ((PCIE_USE_MODE == "1.0") || (PCIE_USE_MODE == "1.1")) ? 24'hB407CC : 24'hA407CC;
//---------- Select TX XCLK ----------------------------
// TXOUT for TX Buffer Use
// TXUSR for TX Buffer Bypass
//------------------------------------------------------
localparam TX_XCLK_SEL = (PCIE_TXBUF_EN == "TRUE") ? "TXOUT" : "TXUSR";
//---------- Select TX Receiver Detection Configuration
localparam TX_RXDETECT_CFG = (PCIE_REFCLK_FREQ == 2) ? 14'd250 :
(PCIE_REFCLK_FREQ == 1) ? 14'd125 : 14'd100;
localparam TX_RXDETECT_REF = (((PCIE_USE_MODE == "1.0") || (PCIE_USE_MODE == "1.1")) && (PCIE_SIM_MODE == "FALSE")) ? 3'b000 : 3'b011;
//---------- Select PCS_RSVD_ATTR ----------------------
// [0]: 1 = enable latch when bypassing TX buffer, 0 = disable latch when using TX buffer
// [1]: 1 = enable manual TX sync, 0 = enable auto TX sync
// [2]: 1 = enable manual RX sync, 0 = enable auto RX sync
// [3]: 1 = select external clock for OOB 0 = select reference clock for OOB
// [6]: 1 = enable DMON 0 = disable DMON
// [7]: 1 = filter stale TX[P/N] data when exiting TX electrical idle
// [8]: 1 = power up OOB 0 = power down OOB
//------------------------------------------------------
localparam OOBCLK_SEL = (PCIE_OOBCLK_MODE == 0) ? 1'd0 : 1'd1; // GTX
localparam RXOOB_CLK_CFG = (PCIE_OOBCLK_MODE == 0) ? "PMA" : "FABRIC"; // GTH/GTP
localparam PCS_RSVD_ATTR = ((PCIE_USE_MODE == "1.0") && (PCIE_TXBUF_EN == "FALSE")) ? {44'h0000000001C, OOBCLK_SEL, 3'd1} :
((PCIE_USE_MODE == "1.0") && (PCIE_TXBUF_EN == "TRUE" )) ? {44'h0000000001C, OOBCLK_SEL, 3'd0} :
((PCIE_RXSYNC_MODE == 0) && (PCIE_TXSYNC_MODE == 0) && (PCIE_TXBUF_EN == "FALSE")) ? {44'h0000000001C, OOBCLK_SEL, 3'd7} :
((PCIE_RXSYNC_MODE == 0) && (PCIE_TXSYNC_MODE == 0) && (PCIE_TXBUF_EN == "TRUE" )) ? {44'h0000000001C, OOBCLK_SEL, 3'd6} :
((PCIE_RXSYNC_MODE == 0) && (PCIE_TXSYNC_MODE == 1) && (PCIE_TXBUF_EN == "FALSE")) ? {44'h0000000001C, OOBCLK_SEL, 3'd5} :
((PCIE_RXSYNC_MODE == 0) && (PCIE_TXSYNC_MODE == 1) && (PCIE_TXBUF_EN == "TRUE" )) ? {44'h0000000001C, OOBCLK_SEL, 3'd4} :
((PCIE_RXSYNC_MODE == 1) && (PCIE_TXSYNC_MODE == 0) && (PCIE_TXBUF_EN == "FALSE")) ? {44'h0000000001C, OOBCLK_SEL, 3'd3} :
((PCIE_RXSYNC_MODE == 1) && (PCIE_TXSYNC_MODE == 0) && (PCIE_TXBUF_EN == "TRUE" )) ? {44'h0000000001C, OOBCLK_SEL, 3'd2} :
((PCIE_RXSYNC_MODE == 1) && (PCIE_TXSYNC_MODE == 1) && (PCIE_TXBUF_EN == "FALSE")) ? {44'h0000000001C, OOBCLK_SEL, 3'd1} :
((PCIE_RXSYNC_MODE == 1) && (PCIE_TXSYNC_MODE == 1) && (PCIE_TXBUF_EN == "TRUE" )) ? {44'h0000000001C, OOBCLK_SEL, 3'd0} : {44'h0000000001C, OOBCLK_SEL, 3'd7};
//---------- Select RXCDR_CFG --------------------------
//---------- GTX Note ----------------------------------
// For GTX PCIe Gen1/Gen2 with 8B/10B, the following CDR setting may provide more margin
// Async 72'h03_8000_23FF_1040_0020
// Sync: 72'h03_0000_23FF_1040_0020
//------------------------------------------------------
localparam RXCDR_CFG_GTX = ((PCIE_USE_MODE == "1.0") || (PCIE_USE_MODE == "1.1")) ?
((PCIE_ASYNC_EN == "TRUE") ? 72'b0000_0010_0000_0111_1111_1110_0010_0000_0110_0000_0010_0001_0001_0000_0000000000010000
: 72'h11_07FE_4060_0104_0000): // IES setting
((PCIE_ASYNC_EN == "TRUE") ? 72'h03_8000_23FF_1020_0020 //
: 72'h03_0000_23FF_1020_0020); // optimized for GES silicon
localparam RXCDR_CFG_GTH = (PCIE_USE_MODE == "2.0") ?
((PCIE_ASYNC_EN == "TRUE") ? 83'h0_0011_07FE_4060_2104_1010
: 83'h0_0011_07FE_4060_0104_1010): // Optimized for IES silicon
((PCIE_ASYNC_EN == "TRUE") ? 83'h0_0020_07FE_2000_C208_8018
: 83'h0_0020_07FE_2000_C208_0018); // Optimized for 1.2 silicon
localparam RXCDR_CFG_GTP = ((PCIE_ASYNC_EN == "TRUE") ? 83'h0_0001_07FE_4060_2104_1010
: 83'h0_0001_07FE_4060_0104_1010); // Optimized for IES silicon
//---------- Select TX and RX Sync Mode ----------------
localparam TXSYNC_OVRD = (PCIE_TXSYNC_MODE == 1) ? 1'd0 : 1'd1;
localparam RXSYNC_OVRD = (PCIE_TXSYNC_MODE == 1) ? 1'd0 : 1'd1;
localparam TXSYNC_MULTILANE = (PCIE_LANE == 1) ? 1'd0 : 1'd1;
localparam RXSYNC_MULTILANE = (PCIE_LANE == 1) ? 1'd0 : 1'd1;
//---------- Select Clock Correction Min and Max Latency
// CLK_COR_MIN_LAT = Larger of (2 * RXCHBONDLEVEL + 13) or (CHAN_BOND_MAX_SKEW + 11)
// = 13 when PCIE_LANE = 1
// CLK_COR_MAX_LAT = CLK_COR_MIN_LAT + CLK_COR_SEQ_LEN + 1
// = CLK_COR_MIN_LAT + 2
//------------------------------------------------------
//---------- CLK_COR_MIN_LAT Look-up Table -------------
// Lane | One-Hop | Daisy-Chain | Binary-Tree
//------------------------------------------------------
// 0 | 13 | 13 | 13
// 1 | 15 to 18 | 15 to 18 | 15 to 18
// 2 | 15 to 18 | 17 to 18 | 15 to 18
// 3 | 15 to 18 | 19 | 17 to 18
// 4 | 15 to 18 | 21 | 17 to 18
// 5 | 15 to 18 | 23 | 19
// 6 | 15 to 18 | 25 | 19
// 7 | 15 to 18 | 27 | 21
//------------------------------------------------------
localparam CLK_COR_MIN_LAT = ((PCIE_LANE == 8) && (PCIE_CHAN_BOND != 0) && (PCIE_CHAN_BOND_EN == "TRUE")) ? ((PCIE_CHAN_BOND == 1) ? 27 : 21) :
((PCIE_LANE == 7) && (PCIE_CHAN_BOND != 0) && (PCIE_CHAN_BOND_EN == "TRUE")) ? ((PCIE_CHAN_BOND == 1) ? 25 : 19) :
((PCIE_LANE == 6) && (PCIE_CHAN_BOND != 0) && (PCIE_CHAN_BOND_EN == "TRUE")) ? ((PCIE_CHAN_BOND == 1) ? 23 : 19) :
((PCIE_LANE == 5) && (PCIE_CHAN_BOND != 0) && (PCIE_CHAN_BOND_EN == "TRUE")) ? ((PCIE_CHAN_BOND == 1) ? 21 : 18) :
((PCIE_LANE == 4) && (PCIE_CHAN_BOND != 0) && (PCIE_CHAN_BOND_EN == "TRUE")) ? ((PCIE_CHAN_BOND == 1) ? 19 : 18) :
((PCIE_LANE == 3) && (PCIE_CHAN_BOND != 0) && (PCIE_CHAN_BOND_EN == "TRUE")) ? ((PCIE_CHAN_BOND == 1) ? 18 : 18) :
((PCIE_LANE == 2) && (PCIE_CHAN_BOND != 0) && (PCIE_CHAN_BOND_EN == "TRUE")) ? ((PCIE_CHAN_BOND == 1) ? 18 : 18) :
((PCIE_LANE == 1) || (PCIE_CHAN_BOND_EN == "FALSE")) ? 13 : 18;
localparam CLK_COR_MAX_LAT = CLK_COR_MIN_LAT + 2;
//---------- Simulation Speedup ------------------------
//localparam CFOK_CFG_GTH = (PCIE_SIM_MODE == "TRUE") ? 42'h240_0004_0F80 : 42'h248_0004_0E80; // [8] : 1 = Skip CFOK
//localparam CFOK_CFG_GTP = (PCIE_SIM_MODE == "TRUE") ? 43'h000_0000_0000 : 43'h000_0000_0100; // [2] : 1 = Skip CFOK
//---------- Select [TX/RX]OUTCLK ----------------------
assign txoutclksel = GT_MASTER ? 3'd3 : 3'd0;
assign rxoutclksel = ((PCIE_DEBUG_MODE == 1) || ((PCIE_ASYNC_EN == "TRUE") && GT_MASTER)) ? 3'd2 : 3'd0;
//---------- Select DFE vs. LPM ------------------------
// Gen1/2 = Use LPM by default. Option to use DFE.
// Gen3 = Use DFE by default. Option to use LPM.
//------------------------------------------------------
assign rxlpmen = GT_GEN3 ? ((PCIE_LPM_DFE_GEN3 == "LPM") ? 1'd1 : 1'd0) : ((PCIE_LPM_DFE == "LPM") ? 1'd1 : 1'd0);
//---------- Generate DMONITOR Clock Buffer for Debug ------
generate if (PCIE_DEBUG_MODE == 1)
begin : dmonitorclk_i
//---------- DMONITOR CLK ------------------------------
BUFG dmonitorclk_i
(
//---------- Input ---------------------------------
.I (dmonitorout[7]),
//---------- Output --------------------------------
.O (dmonitorclk)
);
end
else
begin : dmonitorclk_i_disable
assign dmonitorclk = 1'd0;
end
endgenerate
//---------- Select GTX or GTH or GTP ------------------------------------------
// Notes : Attributes that are commented out always use the GT default settings
//------------------------------------------------------------------------------
generate if (PCIE_GT_DEVICE == "GTP")
begin : gtp_channel
//---------- GTP Channel Module --------------------------------------------
GTPE2_CHANNEL #
(
//---------- Simulation Attributes -------------------------------------
.SIM_RESET_SPEEDUP (PCIE_SIM_SPEEDUP), //
.SIM_RECEIVER_DETECT_PASS ("TRUE"), //
.SIM_TX_EIDLE_DRIVE_LEVEL (PCIE_SIM_TX_EIDLE_DRIVE_LEVEL), //
.SIM_VERSION (PCIE_USE_MODE), //
//---------- Clock Attributes ------------------------------------------
.TXOUT_DIV (OUT_DIV), //
.RXOUT_DIV (OUT_DIV), //
.TX_CLK25_DIV (CLK25_DIV), //
.RX_CLK25_DIV (CLK25_DIV), //
//.TX_CLKMUX_EN ( 1'b1), // GTP rename
//.RX_CLKMUX_EN ( 1'b1), // GTP rename
.TX_XCLK_SEL (TX_XCLK_SEL), // TXOUT = use TX buffer, TXUSR = bypass TX buffer
.RX_XCLK_SEL ("RXREC"), // RXREC = use RX buffer, RXUSR = bypass RX buffer
//.OUTREFCLK_SEL_INV ( 2'b11), //
//---------- Reset Attributes ------------------------------------------
.TXPCSRESET_TIME ( 5'b00001), //
.RXPCSRESET_TIME ( 5'b00001), //
.TXPMARESET_TIME ( 5'b00011), //
.RXPMARESET_TIME ( 5'b00011), // Optimized for sim
//.RXISCANRESET_TIME ( 5'b00001), //
//---------- TX Data Attributes ----------------------------------------
.TX_DATA_WIDTH (20), // 2-byte external datawidth for Gen1/Gen2
//---------- RX Data Attributes ----------------------------------------
.RX_DATA_WIDTH (20), // 2-byte external datawidth for Gen1/Gen2
//---------- Command Attributes ----------------------------------------
.TX_RXDETECT_CFG (TX_RXDETECT_CFG), //
.TX_RXDETECT_REF ( 3'b011), //
.RX_CM_SEL ( 2'd3), // 0 = AVTT, 1 = GND, 2 = Float, 3 = Programmable
.RX_CM_TRIM ( 4'b1010), // Select 800mV, Changed from 3 to 4-bits, optimized for IES
.TX_EIDLE_ASSERT_DELAY (PCIE_TX_EIDLE_ASSERT_DELAY), // Optimized for sim
.TX_EIDLE_DEASSERT_DELAY ( 3'b010), // Optimized for sim
//.PD_TRANS_TIME_FROM_P2 (12'h03C), //
.PD_TRANS_TIME_NONE_P2 ( 8'h09), //
//.PD_TRANS_TIME_TO_P2 ( 8'h64), //
//.TRANS_TIME_RATE ( 8'h0E), //
//---------- Electrical Command Attributes -----------------------------
.TX_DRIVE_MODE ("PIPE"), // Gen1/Gen2 = PIPE, Gen3 = PIPEGEN3
.TX_DEEMPH0 ( 5'b10100), // 6.0 dB
.TX_DEEMPH1 ( 5'b01011), // 3.5 dB
.TX_MARGIN_FULL_0 ( 7'b1001111), // 1000 mV
.TX_MARGIN_FULL_1 ( 7'b1001110), // 950 mV
.TX_MARGIN_FULL_2 ( 7'b1001101), // 900 mV
.TX_MARGIN_FULL_3 ( 7'b1001100), // 850 mV
.TX_MARGIN_FULL_4 ( 7'b1000011), // 400 mV
.TX_MARGIN_LOW_0 ( 7'b1000101), // 500 mV
.TX_MARGIN_LOW_1 ( 7'b1000110), // 450 mV
.TX_MARGIN_LOW_2 ( 7'b1000011), // 400 mV
.TX_MARGIN_LOW_3 ( 7'b1000010), // 350 mV
.TX_MARGIN_LOW_4 ( 7'b1000000), // 250 mV
.TX_MAINCURSOR_SEL ( 1'b0), //
.TX_PREDRIVER_MODE ( 1'b0), // GTP
//---------- Status Attributes -----------------------------------------
//.RX_SIG_VALID_DLY ( 4), // CHECK
//---------- DRP Attributes --------------------------------------------
//---------- PCS Attributes --------------------------------------------
.PCS_PCIE_EN ("TRUE"), // PCIe
.PCS_RSVD_ATTR (48'h0000_0000_0100), // [8] : 1 = OOB power-up
//---------- PMA Attributes -------------------------------------------
//.CLK_COMMON_SWING ( 1'b0), // GTP new
//.PMA_RSV (32'd0), //
.PMA_RSV2 (32'h00002040), // Optimized for GES
//.PMA_RSV3 ( 2'd0), //
//.PMA_RSV4 ( 4'd0), // Changed from 15 to 4-bits
//.PMA_RSV5 ( 1'd0), // Changed from 4 to 1-bit
//.PMA_RSV6 ( 1'd0), // GTP new
//.PMA_RSV7 ( 1'd0), // GTP new
.RX_BIAS_CFG (16'h0F33), // Optimized for IES
.TERM_RCAL_CFG (15'b100001000010000), // Optimized for IES
.TERM_RCAL_OVRD ( 3'b000), // Optimized for IES
//---------- TX PI ----------------------------------------------------
//.TXPI_CFG0 ( 2'd0), //
//.TXPI_CFG1 ( 2'd0), //
//.TXPI_CFG2 ( 2'd0), //
//.TXPI_CFG3 ( 1'd0), //
//.TXPI_CFG4 ( 1'd0), //
//.TXPI_CFG5 ( 3'd000), //
//.TXPI_GREY_SEL ( 1'd0), //
//.TXPI_INVSTROBE_SEL ( 1'd0), //
//.TXPI_PPMCLK_SEL ("TXUSRCLK2"), //
//.TXPI_PPM_CFG ( 8'd0), //
//.TXPI_SYNFREQ_PPM ( 3'd0), //
//---------- RX PI -----------------------------------------------------
.RXPI_CFG0 ( 3'd0), // Changed from 3 to 2-bits, Optimized for IES
.RXPI_CFG1 ( 1'd1), // Changed from 2 to 1-bits, Optimized for IES
.RXPI_CFG2 ( 1'd1), // Changed from 2 to 1-bits, Optimized for IES
//---------- CDR Attributes ---------------------------------------------
//.RXCDR_CFG (72'b0000_001000000_11111_11111_001000000_011_0000111_000_001000_010000_100000000000000), // CHECK
.RXCDR_CFG (RXCDR_CFG_GTP), // Optimized for IES
.RXCDR_LOCK_CFG ( 6'b010101), // [5:3] Window Refresh, [2:1] Window Size, [0] Enable Detection (sensitive lock = 6'b111001) CHECK
.RXCDR_HOLD_DURING_EIDLE ( 1'd1), // Hold RX CDR on electrical idle for Gen1/Gen2
.RXCDR_FR_RESET_ON_EIDLE ( 1'd0), // Reset RX CDR frequency on electrical idle for Gen3
.RXCDR_PH_RESET_ON_EIDLE ( 1'd0), // Reset RX CDR phase on electrical idle for Gen3
//.RXCDRFREQRESET_TIME ( 5'b00001), //
//.RXCDRPHRESET_TIME ( 5'b00001), //
//---------- LPM Attributes --------------------------------------------
//.RXLPMRESET_TIME ( 7'b0001111), // GTP new
//.RXLPM_BIAS_STARTUP_DISABLE ( 1'b0), // GTP new
.RXLPM_CFG ( 4'b0110), // GTP new, optimized for IES
//.RXLPM_CFG1 ( 1'b0), // GTP new
//.RXLPM_CM_CFG ( 1'b0), // GTP new
.RXLPM_GC_CFG ( 9'b111100010), // GTP new, optimized for IES
.RXLPM_GC_CFG2 ( 3'b001), // GTP new, optimized for IES
//.RXLPM_HF_CFG (14'b00001111110000), //
.RXLPM_HF_CFG2 ( 5'b01010), // GTP new
//.RXLPM_HF_CFG3 ( 4'b0000), // GTP new
.RXLPM_HOLD_DURING_EIDLE ( 1'b1), // GTP new
.RXLPM_INCM_CFG ( 1'b1), // GTP new, optimized for IES
.RXLPM_IPCM_CFG ( 1'b0), // GTP new, optimized for IES
//.RXLPM_LF_CFG (18'b000000001111110000), //
.RXLPM_LF_CFG2 ( 5'b01010), // GTP new, optimized for IES
.RXLPM_OSINT_CFG ( 3'b100), // GTP new, optimized for IES
//---------- OS Attributes ---------------------------------------------
.RX_OS_CFG (13'h0080), // CHECK
.RXOSCALRESET_TIME (5'b00011), // Optimized for IES
.RXOSCALRESET_TIMEOUT (5'b00000), // Disable timeout, Optimized for IES
//---------- Eye Scan Attributes ---------------------------------------
//.ES_CLK_PHASE_SEL ( 1'b0), //
//.ES_CONTROL ( 6'd0), //
//.ES_ERRDET_EN ("FALSE"), //
.ES_EYE_SCAN_EN ("TRUE"), //
//.ES_HORZ_OFFSET (12'd0), //
//.ES_PMA_CFG (10'd0), //
//.ES_PRESCALE ( 5'd0), //
//.ES_QUAL_MASK (80'd0), //
//.ES_QUALIFIER (80'd0), //
//.ES_SDATA_MASK (80'd0), //
//.ES_VERT_OFFSET ( 9'd0), //
//---------- TX Buffer Attributes --------------------------------------
.TXBUF_EN (PCIE_TXBUF_EN), //
.TXBUF_RESET_ON_RATE_CHANGE ("TRUE"), //
//---------- RX Buffer Attributes --------------------------------------
.RXBUF_EN ("TRUE"), //
//.RX_BUFFER_CFG ( 6'd0), //
.RX_DEFER_RESET_BUF_EN ("TRUE"), //
.RXBUF_ADDR_MODE ("FULL"), //
.RXBUF_EIDLE_HI_CNT ( 4'd4), // Optimized for sim
.RXBUF_EIDLE_LO_CNT ( 4'd0), // Optimized for sim
.RXBUF_RESET_ON_CB_CHANGE ("TRUE"), //
.RXBUF_RESET_ON_COMMAALIGN ("FALSE"), //
.RXBUF_RESET_ON_EIDLE ("TRUE"), // PCIe
.RXBUF_RESET_ON_RATE_CHANGE ("TRUE"), //
.RXBUF_THRESH_OVRD ("FALSE"), //
.RXBUF_THRESH_OVFLW (61), //
.RXBUF_THRESH_UNDFLW ( 4), //
//.RXBUFRESET_TIME ( 5'b00001), //
//---------- TX Sync Attributes ----------------------------------------
.TXPH_CFG (16'h0780), //
.TXPH_MONITOR_SEL ( 5'd0), //
.TXPHDLY_CFG (24'h084020), // [19] : 1 = full range, 0 = half range
.TXDLY_CFG (16'h001F), //
.TXDLY_LCFG ( 9'h030), //
.TXDLY_TAP_CFG (16'd0), //
.TXSYNC_OVRD (TXSYNC_OVRD), //
.TXSYNC_MULTILANE (TXSYNC_MULTILANE), //
.TXSYNC_SKIP_DA (1'b0), //
//---------- RX Sync Attributes ----------------------------------------
.RXPH_CFG (24'd0), //
.RXPH_MONITOR_SEL ( 5'd0), //
.RXPHDLY_CFG (24'h004020), // [19] : 1 = full range, 0 = half range
.RXDLY_CFG (16'h001F), //
.RXDLY_LCFG ( 9'h030), //
.RXDLY_TAP_CFG (16'd0), //
.RX_DDI_SEL ( 6'd0), //
.RXSYNC_OVRD (RXSYNC_OVRD), //
.RXSYNC_MULTILANE (RXSYNC_MULTILANE), //
.RXSYNC_SKIP_DA (1'b0), //
//---------- Comma Alignment Attributes --------------------------------
.ALIGN_COMMA_DOUBLE ("FALSE"), //
.ALIGN_COMMA_ENABLE (10'b1111111111), // PCIe
.ALIGN_COMMA_WORD ( 1), //
.ALIGN_MCOMMA_DET ("TRUE"), //
.ALIGN_MCOMMA_VALUE (10'b1010000011), //
.ALIGN_PCOMMA_DET ("TRUE"), //
.ALIGN_PCOMMA_VALUE (10'b0101111100), //
.DEC_MCOMMA_DETECT ("TRUE"), //
.DEC_PCOMMA_DETECT ("TRUE"), //
.DEC_VALID_COMMA_ONLY ("FALSE"), // PCIe
.SHOW_REALIGN_COMMA ("FALSE"), // PCIe
.RXSLIDE_AUTO_WAIT ( 7), //
.RXSLIDE_MODE ("PMA"), // PCIe
//---------- Channel Bonding Attributes --------------------------------
.CHAN_BOND_KEEP_ALIGN ("TRUE"), // PCIe
.CHAN_BOND_MAX_SKEW ( 7), //
.CHAN_BOND_SEQ_LEN ( 4), // PCIe
.CHAN_BOND_SEQ_1_ENABLE ( 4'b1111), //
.CHAN_BOND_SEQ_1_1 (10'b0001001010), // D10.2 (4A) - TS1
.CHAN_BOND_SEQ_1_2 (10'b0001001010), // D10.2 (4A) - TS1
.CHAN_BOND_SEQ_1_3 (10'b0001001010), // D10.2 (4A) - TS1
.CHAN_BOND_SEQ_1_4 (10'b0110111100), // K28.5 (BC) - COM
.CHAN_BOND_SEQ_2_USE ("TRUE"), // PCIe
.CHAN_BOND_SEQ_2_ENABLE (4'b1111), //
.CHAN_BOND_SEQ_2_1 (10'b0001000101), // D5.2 (45) - TS2
.CHAN_BOND_SEQ_2_2 (10'b0001000101), // D5.2 (45) - TS2
.CHAN_BOND_SEQ_2_3 (10'b0001000101), // D5.2 (45) - TS2
.CHAN_BOND_SEQ_2_4 (10'b0110111100), // K28.5 (BC) - COM
.FTS_DESKEW_SEQ_ENABLE ( 4'b1111), //
.FTS_LANE_DESKEW_EN ("TRUE"), // PCIe
.FTS_LANE_DESKEW_CFG ( 4'b1111), //
//---------- Clock Correction Attributes -------------------------------
.CBCC_DATA_SOURCE_SEL ("DECODED"), //
.CLK_CORRECT_USE ("TRUE"), //
.CLK_COR_KEEP_IDLE ("TRUE"), // PCIe
.CLK_COR_MAX_LAT (CLK_COR_MAX_LAT), //
.CLK_COR_MIN_LAT (CLK_COR_MIN_LAT), //
.CLK_COR_PRECEDENCE ("TRUE"), //
.CLK_COR_REPEAT_WAIT ( 0), //
.CLK_COR_SEQ_LEN ( 1), //
.CLK_COR_SEQ_1_ENABLE ( 4'b1111), //
.CLK_COR_SEQ_1_1 (10'b0100011100), // K28.0 (1C) - SKP
.CLK_COR_SEQ_1_2 (10'b0000000000), // Disabled
.CLK_COR_SEQ_1_3 (10'b0000000000), // Disabled
.CLK_COR_SEQ_1_4 (10'b0000000000), // Disabled
.CLK_COR_SEQ_2_ENABLE ( 4'b0000), // Disabled
.CLK_COR_SEQ_2_USE ("FALSE"), //
.CLK_COR_SEQ_2_1 (10'b0000000000), // Disabled
.CLK_COR_SEQ_2_2 (10'b0000000000), // Disabled
.CLK_COR_SEQ_2_3 (10'b0000000000), // Disabled
.CLK_COR_SEQ_2_4 (10'b0000000000), // Disabled
//---------- 8b10b Attributes ------------------------------------------
.RX_DISPERR_SEQ_MATCH ("TRUE"), //
//---------- 64b/66b & 64b/67b Attributes ------------------------------
.GEARBOX_MODE ( 3'd0), //
.TXGEARBOX_EN ("FALSE"), //
.RXGEARBOX_EN ("FALSE"), //
//---------- PRBS & Loopback Attributes ---------------------------------
.LOOPBACK_CFG ( 1'd0), // Enable latch when bypassing TX buffer, equivalent to GTX PCS_RSVD_ATTR[0]
.RXPRBS_ERR_LOOPBACK ( 1'd0), //
.TX_LOOPBACK_DRIVE_HIZ ("FALSE"), //
//---------- OOB & SATA Attributes --------------------------------------
.TXOOB_CFG ( 1'd1), // Filter stale TX data when exiting TX electrical idle, equivalent to GTX PCS_RSVD_ATTR[7]
//.RXOOB_CFG ( 7'b0000110), //
.RXOOB_CLK_CFG (RXOOB_CLK_CFG), //
//.SAS_MAX_COM (64), //
//.SAS_MIN_COM (36), //
//.SATA_BURST_SEQ_LEN ( 4'b1111), //
//.SATA_BURST_VAL ( 3'b100), //
//.SATA_PLL_CFG ("VCO_3000MHZ"), //
//.SATA_EIDLE_VAL ( 3'b100), //
//.SATA_MAX_BURST ( 8), //
//.SATA_MAX_INIT (21), //
//.SATA_MAX_WAKE ( 7), //
//.SATA_MIN_BURST ( 4), //
//.SATA_MIN_INIT (12), //
//.SATA_MIN_WAKE ( 4), //
//---------- MISC ------------------------------------------------------
.DMONITOR_CFG (24'h000B01), //
.RX_DEBUG_CFG (14'h0000), // Optimized for IES
//.TST_RSV (32'd0), //
//.UCODEER_CLR ( 1'd0) //
//---------- GTP -------------------------------------------------------
//.ACJTAG_DEBUG_MODE (1'd0), //
//.ACJTAG_MODE (1'd0), //
//.ACJTAG_RESET (1'd0), //
//.ADAPT_CFG0 (20'd0), //
.CFOK_CFG (43'h490_0004_0E80), // Changed from 42 to 43-bits, Optimized for IES
.CFOK_CFG2 ( 7'b010_0000), // Changed from 6 to 7-bits, Optimized for IES
.CFOK_CFG3 ( 7'b010_0000), // Changed from 6 to 7-bits, Optimized for IES
.CFOK_CFG4 ( 1'd0), // GTP new, Optimized for IES
.CFOK_CFG5 ( 2'd0), // GTP new, Optimized for IES
.CFOK_CFG6 ( 4'd0) // GTP new, Optimized for IES
)
gtpe2_channel_i
(
//---------- Clock -----------------------------------------------------
.PLL0CLK (GT_QPLLCLK), //
.PLL1CLK (1'd0), //
.PLL0REFCLK (GT_QPLLREFCLK), //
.PLL1REFCLK (1'd0), //
.TXUSRCLK (GT_TXUSRCLK), //
.RXUSRCLK (GT_RXUSRCLK), //
.TXUSRCLK2 (GT_TXUSRCLK2), //
.RXUSRCLK2 (GT_RXUSRCLK2), //
.TXSYSCLKSEL (GT_TXSYSCLKSEL), //
.RXSYSCLKSEL (GT_RXSYSCLKSEL), //
.TXOUTCLKSEL (txoutclksel), //
.RXOUTCLKSEL (rxoutclksel), //
.CLKRSVD0 (1'd0), //
.CLKRSVD1 (1'd0), //
.TXOUTCLK (GT_TXOUTCLK), //
.RXOUTCLK (GT_RXOUTCLK), //
.TXOUTCLKFABRIC (), //
.RXOUTCLKFABRIC (), //
.TXOUTCLKPCS (), //
.RXOUTCLKPCS (), //
.RXCDRLOCK (GT_RXCDRLOCK), //
//---------- Reset -----------------------------------------------------
.TXUSERRDY (GT_TXUSERRDY), //
.RXUSERRDY (GT_RXUSERRDY), //
.CFGRESET (1'd0), //
.GTRESETSEL (1'd0), //
.RESETOVRD (GT_RESETOVRD), //
.GTTXRESET (GT_GTTXRESET), //
.GTRXRESET (GT_GTRXRESET), //
.TXRESETDONE (GT_TXRESETDONE), //
.RXRESETDONE (GT_RXRESETDONE), //
//---------- TX Data ---------------------------------------------------
.TXDATA (GT_TXDATA), //
.TXCHARISK (GT_TXDATAK), //
.GTPTXP (GT_TXP), // GTP
.GTPTXN (GT_TXN), // GTP
//---------- RX Data ---------------------------------------------------
.GTPRXP (GT_RXP), // GTP
.GTPRXN (GT_RXN), // GTP
.RXDATA (rxdata[31:0]), //
.RXCHARISK (rxdatak[3:0]), //
//---------- Command ---------------------------------------------------
.TXDETECTRX (GT_TXDETECTRX), //
.TXPDELECIDLEMODE ( 1'd0), //
.RXELECIDLEMODE ( 2'd0), //
.TXELECIDLE (GT_TXELECIDLE), //
.TXCHARDISPMODE ({3'd0, GT_TXCOMPLIANCE}), // Changed from 8 to 4-bits
.TXCHARDISPVAL ( 4'd0), // Changed from 8 to 4-bits
.TXPOLARITY ( 1'd0), //
.RXPOLARITY (GT_RXPOLARITY), //
.TXPD (GT_TXPOWERDOWN), //
.RXPD (GT_RXPOWERDOWN), //
.TXRATE (GT_TXRATE), //
.RXRATE (GT_RXRATE), //
.TXRATEMODE (1'b0), //
.RXRATEMODE (1'b0), //
//---------- Electrical Command ----------------------------------------
.TXMARGIN (GT_TXMARGIN), //
.TXSWING (GT_TXSWING), //
.TXDEEMPH (GT_TXDEEMPH), //
.TXINHIBIT (1'd0), //
.TXBUFDIFFCTRL (3'b100), //
.TXDIFFCTRL (4'b1100), // Select 850mV
.TXPRECURSOR (GT_TXPRECURSOR), //
.TXPRECURSORINV (1'd0), //
.TXMAINCURSOR (GT_TXMAINCURSOR), //
.TXPOSTCURSOR (GT_TXPOSTCURSOR), //
.TXPOSTCURSORINV (1'd0), //
//---------- Status ----------------------------------------------------
.RXVALID (GT_RXVALID), //
.PHYSTATUS (GT_PHYSTATUS), //
.RXELECIDLE (GT_RXELECIDLE), //
.RXSTATUS (GT_RXSTATUS), //
.TXRATEDONE (GT_TXRATEDONE), //
.RXRATEDONE (GT_RXRATEDONE), //
//---------- DRP -------------------------------------------------------
.DRPCLK (GT_DRPCLK), //
.DRPADDR (GT_DRPADDR), //
.DRPEN (GT_DRPEN), //
.DRPDI (GT_DRPDI), //
.DRPWE (GT_DRPWE), //
.DRPDO (GT_DRPDO), //
.DRPRDY (GT_DRPRDY), //
//---------- PMA -------------------------------------------------------
.TXPMARESET (GT_TXPMARESET), //
.RXPMARESET (GT_RXPMARESET), //
.RXLPMRESET ( 1'd0), // GTP new
.RXLPMOSINTNTRLEN ( 1'd0), // GTP new
.RXLPMHFHOLD ( 1'd0), //
.RXLPMHFOVRDEN ( 1'd0), //
.RXLPMLFHOLD ( 1'd0), //
.RXLPMLFOVRDEN ( 1'd0), //
.PMARSVDIN0 ( 1'd0), // GTP new
.PMARSVDIN1 ( 1'd0), // GTP new
.PMARSVDIN2 ( 1'd0), // GTP new
.PMARSVDIN3 ( 1'd0), // GTP new
.PMARSVDIN4 ( 1'd0), // GTP new
.GTRSVD (16'd0), //
.PMARSVDOUT0 (), // GTP new
.PMARSVDOUT1 (), // GTP new
.DMONITOROUT (dmonitorout), // GTP 15-bits
//---------- PCS -------------------------------------------------------
.TXPCSRESET (GT_TXPCSRESET), //
.RXPCSRESET (GT_RXPCSRESET), //
.PCSRSVDIN (16'd0), // [0]: 1 = TXRATE async, [1]: 1 = RXRATE async
.PCSRSVDOUT (), //
//---------- CDR -------------------------------------------------------
.RXCDRRESET (GT_RXCDRRESET), //
.RXCDRRESETRSV (1'd0), //
.RXCDRFREQRESET (GT_RXCDRFREQRESET), //
.RXCDRHOLD (1'd0), //
.RXCDROVRDEN (1'd0), //
//---------- PI --------------------------------------------------------
.TXPIPPMEN (1'd0), //
.TXPIPPMOVRDEN (1'd0), //
.TXPIPPMPD (1'd0), //
.TXPIPPMSEL (1'd0), //
.TXPIPPMSTEPSIZE (5'd0), //
.TXPISOPD (1'd0), // GTP new
//---------- DFE -------------------------------------------------------
.RXDFEXYDEN (1'd0), //
//---------- OS --------------------------------------------------------
.RXOSHOLD (1'd0), // Optimized for IES
.RXOSOVRDEN (1'd0), // Optimized for IES
.RXOSINTEN (1'd1), // Optimized for IES
.RXOSINTHOLD (1'd0), // Optimized for IES
.RXOSINTNTRLEN (1'd0), // Optimized for IES
.RXOSINTOVRDEN (1'd0), // Optimized for IES
.RXOSINTPD (1'd0), // GTP new, Optimized for IES
.RXOSINTSTROBE (1'd0), // Optimized for IES
.RXOSINTTESTOVRDEN (1'd0), // Optimized for IES
.RXOSINTCFG (4'b0010), // Optimized for IES
.RXOSINTID0 (4'd0), // Optimized for IES
.RXOSINTDONE (), //
.RXOSINTSTARTED (), //
.RXOSINTSTROBEDONE (), //
.RXOSINTSTROBESTARTED (), //
//---------- Eye Scan --------------------------------------------------
.EYESCANRESET (GT_EYESCANRESET), //
.EYESCANMODE (1'd0), //
.EYESCANTRIGGER (1'd0), //
.EYESCANDATAERROR (), //
//---------- TX Buffer -------------------------------------------------
.TXBUFSTATUS (), //
//---------- RX Buffer -------------------------------------------------
.RXBUFRESET (GT_RXBUFRESET), //
.RXBUFSTATUS (GT_RXBUFSTATUS), //
//---------- TX Sync ---------------------------------------------------
.TXPHDLYRESET (GT_TXPHDLYRESET), //
.TXPHDLYTSTCLK (1'd0), //
.TXPHALIGN (GT_TXPHALIGN), //
.TXPHALIGNEN (GT_TXPHALIGNEN), //
.TXPHDLYPD (1'd0), //
.TXPHINIT (GT_TXPHINIT), //
.TXPHOVRDEN (1'd0), //
.TXDLYBYPASS (GT_TXDLYBYPASS), //
.TXDLYSRESET (GT_TXDLYSRESET), //
.TXDLYEN (GT_TXDLYEN), //
.TXDLYOVRDEN (1'd0), //
.TXDLYHOLD (1'd0), //
.TXDLYUPDOWN (1'd0), //
.TXPHALIGNDONE (GT_TXPHALIGNDONE), //
.TXPHINITDONE (GT_TXPHINITDONE), //
.TXDLYSRESETDONE (GT_TXDLYSRESETDONE), //
.TXSYNCMODE (GT_TXSYNCMODE), //
.TXSYNCIN (GT_TXSYNCIN), //
.TXSYNCALLIN (GT_TXSYNCALLIN), //
.TXSYNCDONE (GT_TXSYNCDONE), //
.TXSYNCOUT (GT_TXSYNCOUT), //
//---------- RX Sync ---------------------------------------------------
.RXPHDLYRESET (1'd0), //
.RXPHALIGN (GT_RXPHALIGN), //
.RXPHALIGNEN (GT_RXPHALIGNEN), //
.RXPHDLYPD (1'd0), //
.RXPHOVRDEN (1'd0), //
.RXDLYBYPASS (GT_RXDLYBYPASS), //
.RXDLYSRESET (GT_RXDLYSRESET), //
.RXDLYEN (GT_RXDLYEN), //
.RXDLYOVRDEN (1'd0), //
.RXDDIEN (GT_RXDDIEN), //
.RXPHALIGNDONE (GT_RXPHALIGNDONE), //
.RXPHMONITOR (), //
.RXPHSLIPMONITOR (), //
.RXDLYSRESETDONE (GT_RXDLYSRESETDONE), //
.RXSYNCMODE (GT_RXSYNCMODE), //
.RXSYNCIN (GT_RXSYNCIN), //
.RXSYNCALLIN (GT_RXSYNCALLIN), //
.RXSYNCDONE (GT_RXSYNCDONE), //
.RXSYNCOUT (GT_RXSYNCOUT), //
//---------- Comma Alignment -------------------------------------------
.RXCOMMADETEN (1'd1), //
.RXMCOMMAALIGNEN (1'd1), // No Gen3 support in GTP
.RXPCOMMAALIGNEN (1'd1), // No Gen3 support in GTP
.RXSLIDE (GT_RXSLIDE), //
.RXCOMMADET (GT_RXCOMMADET), //
.RXCHARISCOMMA (rxchariscomma[3:0]), //
.RXBYTEISALIGNED (GT_RXBYTEISALIGNED), //
.RXBYTEREALIGN (GT_RXBYTEREALIGN), //
//---------- Channel Bonding -------------------------------------------
.RXCHBONDEN (GT_RXCHBONDEN), //
.RXCHBONDI (GT_RXCHBONDI[3:0]), //
.RXCHBONDLEVEL (GT_RXCHBONDLEVEL), //
.RXCHBONDMASTER (GT_RXCHBONDMASTER), //
.RXCHBONDSLAVE (GT_RXCHBONDSLAVE), //
.RXCHANBONDSEQ (), //
.RXCHANISALIGNED (GT_RXCHANISALIGNED), //
.RXCHANREALIGN (), //
.RXCHBONDO (GT_RXCHBONDO[3:0]), //
//---------- Clock Correction -----------------------------------------
.RXCLKCORCNT (), //
//---------- 8b10b -----------------------------------------------------
.TX8B10BBYPASS (4'd0), //
.TX8B10BEN (1'b1), // No Gen3 support in GTP
.RX8B10BEN (1'b1), // No Gen3 support in GTP
.RXDISPERR (), //
.RXNOTINTABLE (), //
//---------- 64b/66b & 64b/67b -----------------------------------------
.TXHEADER (3'd0), //
.TXSEQUENCE (7'd0), //
.TXSTARTSEQ (1'd0), //
.RXGEARBOXSLIP (1'd0), //
.TXGEARBOXREADY (), //
.RXDATAVALID (), //
.RXHEADER (), //
.RXHEADERVALID (), //
.RXSTARTOFSEQ (), //
//---------- PRBS/Loopback ---------------------------------------------
.TXPRBSSEL (GT_TXPRBSSEL), //
.RXPRBSSEL (GT_RXPRBSSEL), //
.TXPRBSFORCEERR (GT_TXPRBSFORCEERR), //
.RXPRBSCNTRESET (GT_RXPRBSCNTRESET), //
.LOOPBACK (GT_LOOPBACK), //
.RXPRBSERR (GT_RXPRBSERR), //
//---------- OOB -------------------------------------------------------
.SIGVALIDCLK (GT_OOBCLK), // Optimized for debug
.TXCOMINIT (1'd0), //
.TXCOMSAS (1'd0), //
.TXCOMWAKE (1'd0), //
.RXOOBRESET (1'd0), //
.TXCOMFINISH (), //
.RXCOMINITDET (), //
.RXCOMSASDET (), //
.RXCOMWAKEDET (), //
//---------- MISC ------------------------------------------------------
.SETERRSTATUS ( 1'd0), //
.TXDIFFPD ( 1'd0), //
.TSTIN (20'hFFFFF), //
//---------- GTP -------------------------------------------------------
.RXADAPTSELTEST (14'd0), //
.DMONFIFORESET ( 1'd0), //
.DMONITORCLK (dmonitorclk), //
.RXOSCALRESET ( 1'd0), //
.RXPMARESETDONE (GT_RXPMARESETDONE), // GTP
.TXPMARESETDONE () //
);
assign GT_CPLLLOCK = 1'b0;
end
else if (PCIE_GT_DEVICE == "GTH")
begin : gth_channel
//---------- GTH Channel Module --------------------------------------------
GTHE2_CHANNEL #
(
//---------- Simulation Attributes -------------------------------------
.SIM_CPLLREFCLK_SEL (3'b001), //
.SIM_RESET_SPEEDUP (PCIE_SIM_SPEEDUP), //
.SIM_RECEIVER_DETECT_PASS ("TRUE"), //
.SIM_TX_EIDLE_DRIVE_LEVEL (PCIE_SIM_TX_EIDLE_DRIVE_LEVEL), //
.SIM_VERSION ("2.0"), //
//---------- Clock Attributes ------------------------------------------
.CPLL_REFCLK_DIV (CPLL_REFCLK_DIV), //
.CPLL_FBDIV_45 (CPLL_FBDIV_45), //
.CPLL_FBDIV (CPLL_FBDIV), //
.TXOUT_DIV (OUT_DIV), //
.RXOUT_DIV (OUT_DIV), //
.TX_CLK25_DIV (CLK25_DIV), //
.RX_CLK25_DIV (CLK25_DIV), //
.TX_CLKMUX_PD ( 1'b1), // GTH
.RX_CLKMUX_PD ( 1'b1), // GTH
.TX_XCLK_SEL (TX_XCLK_SEL), // TXOUT = use TX buffer, TXUSR = bypass TX buffer
.RX_XCLK_SEL ("RXREC"), // RXREC = use RX buffer, RXUSR = bypass RX buffer
.OUTREFCLK_SEL_INV ( 2'b11), //
.CPLL_CFG (29'h00A407CC), // Changed from 24 to 29-bits, Optimized for PCIe PLL BW
.CPLL_INIT_CFG (24'h00001E), // Optimized for IES
.CPLL_LOCK_CFG (16'h01E8), // Optimized for IES
//.USE_PCS_CLK_PHASE_SEL ( 1'd0) // GTH new
//---------- Reset Attributes ------------------------------------------
.TXPCSRESET_TIME (5'b00001), //
.RXPCSRESET_TIME (5'b00001), //
.TXPMARESET_TIME (5'b00011), //
.RXPMARESET_TIME (5'b00011), // Optimized for sim and for DRP
//.RXISCANRESET_TIME (5'b00001), //
//.RESET_POWERSAVE_DISABLE ( 1'd0), // GTH new
//---------- TX Data Attributes ----------------------------------------
.TX_DATA_WIDTH (20), // 2-byte external datawidth for Gen1/Gen2
.TX_INT_DATAWIDTH ( 0), // 2-byte internal datawidth for Gen1/Gen2
//---------- RX Data Attributes ----------------------------------------
.RX_DATA_WIDTH (20), // 2-byte external datawidth for Gen1/Gen2
.RX_INT_DATAWIDTH ( 0), // 2-byte internal datawidth for Gen1/Gen2
//---------- Command Attributes ----------------------------------------
.TX_RXDETECT_CFG (TX_RXDETECT_CFG), //
.TX_RXDETECT_PRECHARGE_TIME (17'h00001), // GTH new, Optimized for sim
.TX_RXDETECT_REF ( 3'b011), //
.RX_CM_SEL ( 2'b11), // 0 = AVTT, 1 = GND, 2 = Float, 3 = Programmable, optimized for silicon
.RX_CM_TRIM ( 4'b1010), // Select 800mV, Changed from 3 to 4-bits, optimized for silicon
.TX_EIDLE_ASSERT_DELAY (PCIE_TX_EIDLE_ASSERT_DELAY), // Optimized for sim (3'd4)
.TX_EIDLE_DEASSERT_DELAY ( 3'b100), // Optimized for sim
//.PD_TRANS_TIME_FROM_P2 (12'h03C), //
.PD_TRANS_TIME_NONE_P2 ( 8'h09), // Optimized for sim
//.PD_TRANS_TIME_TO_P2 ( 8'h64), //
//.TRANS_TIME_RATE ( 8'h0E), //
//---------- Electrical Command Attributes -----------------------------
.TX_DRIVE_MODE ("PIPE"), // Gen1/Gen2 = PIPE, Gen3 = PIPEGEN3
.TX_DEEMPH0 ( 6'b010100), // 6.0 dB, optimized for compliance, changed from 5 to 6-bits
.TX_DEEMPH1 ( 6'b001011), // 3.5 dB, optimized for compliance, changed from 5 to 6-bits
.TX_MARGIN_FULL_0 ( 7'b1001111), // 1000 mV
.TX_MARGIN_FULL_1 ( 7'b1001110), // 950 mV
.TX_MARGIN_FULL_2 ( 7'b1001101), // 900 mV
.TX_MARGIN_FULL_3 ( 7'b1001100), // 850 mV
.TX_MARGIN_FULL_4 ( 7'b1000011), // 400 mV
.TX_MARGIN_LOW_0 ( 7'b1000101), // 500 mV
.TX_MARGIN_LOW_1 ( 7'b1000110), // 450 mV
.TX_MARGIN_LOW_2 ( 7'b1000011), // 400 mV
.TX_MARGIN_LOW_3 ( 7'b1000010), // 350 mV
.TX_MARGIN_LOW_4 ( 7'b1000000), // 250 mV
.TX_MAINCURSOR_SEL ( 1'b0), //
.TX_QPI_STATUS_EN ( 1'b0), //
//---------- Status Attributes -----------------------------------------
.RX_SIG_VALID_DLY (4), // Optimized for sim
//---------- DRP Attributes --------------------------------------------
//---------- PCS Attributes --------------------------------------------
.PCS_PCIE_EN ("TRUE"), // PCIe
.PCS_RSVD_ATTR (48'h0000_0000_0140), // [8] : 1 = OOB power-up, [6] : 1 = DMON enable, Optimized for IES
//---------- PMA Attributes --------------------------------------------
.PMA_RSV (32'h00000080), // Optimized for IES
.PMA_RSV2 (32'h1C00000A), // Changed from 16 to 32-bits, Optimized for IES
//.PMA_RSV3 ( 2'h0), //
.PMA_RSV4 (15'h0008), // GTH new, Optimized for IES
//.PMA_RSV5 ( 4'h00), // GTH new
.RX_BIAS_CFG (24'h0C0010), // Changed from 12 to 24-bits, Optimized for IES
.TERM_RCAL_CFG (15'b100001000010000), // Changed from 5 to 15-bits, Optimized for IES
.TERM_RCAL_OVRD ( 3'b000), // Changed from 1 to 3-bits, Optimized for IES
//---------- TX PI -----------------------------------------------------
//.TXPI_CFG0 ( 2'd0), // GTH new
//.TXPI_CFG1 ( 2'd0), // GTH new
//.TXPI_CFG2 ( 2'd0), // GTH new
//.TXPI_CFG3 ( 1'd0), // GTH new
//.TXPI_CFG4 ( 1'd0), // GTH new
//.TXPI_CFG5 ( 3'b100), // GTH new
//.TXPI_GREY_SEL ( 1'd0), // GTH new
//.TXPI_INVSTROBE_SEL ( 1'd0), // GTH new
//.TXPI_PPMCLK_SEL ("TXUSRCLK2"), // GTH new
//.TXPI_PPM_CFG ( 8'd0), // GTH new
//.TXPI_SYNFREQ_PPM ( 3'd0), // GTH new
//---------- RX PI -----------------------------------------------------
.RXPI_CFG0 (2'b00), // GTH new
.RXPI_CFG1 (2'b11), // GTH new
.RXPI_CFG2 (2'b11), // GTH new
.RXPI_CFG3 (2'b11), // GTH new
.RXPI_CFG4 (1'b0), // GTH new
.RXPI_CFG5 (1'b0), // GTH new
.RXPI_CFG6 (3'b100), // GTH new
//---------- CDR Attributes --------------------------------------------
.RXCDR_CFG (RXCDR_CFG_GTH), //
//.RXCDR_CFG (83'h0_0011_07FE_4060_0104_1010), // A. Changed from 72 to 83-bits, optimized for IES div1 (Gen2), +/-000ppm, default, converted from GTX GES VnC,(2 Gen1)
//.RXCDR_CFG (83'h0_0011_07FE_4060_2104_1010), // B. Changed from 72 to 83-bits, optimized for IES div1 (Gen2), +/-300ppm, default, converted from GTX GES VnC,(2 Gen1)
//.RXCDR_CFG (83'h0_0011_07FE_2060_0104_1010), // C. Changed from 72 to 83-bits, optimized for IES div1 (Gen2), +/-000ppm, converted from GTX GES recommended, (3 Gen1)
//.RXCDR_CFG (83'h0_0011_07FE_2060_2104_1010), // D. Changed from 72 to 83-bits, optimized for IES div1 (Gen2), +/-300ppm, converted from GTX GES recommended, (3 Gen1)
//.RXCDR_CFG (83'h0_0001_07FE_1060_0110_1010), // E. Changed from 72 to 83-bits, optimized for IES div2 (Gen1), +/-000ppm, default, (3 Gen2)
//.RXCDR_CFG (83'h0_0001_07FE_1060_2110_1010), // F. Changed from 72 to 83-bits, optimized for IES div2 (Gen1), +/-300ppm, default, (3 Gen2)
//.RXCDR_CFG (83'h0_0011_07FE_1060_0110_1010), // G. Changed from 72 to 83-bits, optimized for IES div2 (Gen1), +/-000ppm, converted from GTX GES recommended, (3 Gen2)
//.RXCDR_CFG (83'h0_0011_07FE_1060_2110_1010), // H. Changed from 72 to 83-bits, optimized for IES div2 (Gen1), +/-300ppm, converted from GTX GES recommended, (2 Gen1)
.RXCDR_LOCK_CFG ( 6'b010101), // [5:3] Window Refresh, [2:1] Window Size, [0] Enable Detection (sensitive lock = 6'b111001)
.RXCDR_HOLD_DURING_EIDLE ( 1'd1), // Hold RX CDR on electrical idle for Gen1/Gen2
.RXCDR_FR_RESET_ON_EIDLE ( 1'd0), // Reset RX CDR frequency on electrical idle for Gen3
.RXCDR_PH_RESET_ON_EIDLE ( 1'd0), // Reset RX CDR phase on electrical idle for Gen3
//.RXCDRFREQRESET_TIME ( 5'b00001), // optimized for IES
//.RXCDRPHRESET_TIME ( 5'b00001), // optimized for IES
//---------- LPM Attributes --------------------------------------------
.RXLPM_HF_CFG (14'h0200), // Optimized for IES
.RXLPM_LF_CFG (18'h09000), // Changed from 14 to 18-bits, Optimized for IES
//---------- DFE Attributes --------------------------------------------
.RXDFELPMRESET_TIME ( 7'h0F), // Optimized for IES
.RX_DFE_AGC_CFG0 ( 2'h0), // GTH new, optimized for IES
.RX_DFE_AGC_CFG1 ( 3'h4), // GTH new, optimized for IES, DFE
.RX_DFE_AGC_CFG2 ( 4'h0), // GTH new, optimized for IES
.RX_DFE_AGC_OVRDEN ( 1'h1), // GTH new, optimized for IES
.RX_DFE_GAIN_CFG (23'h0020C0), // Optimized for IES
.RX_DFE_H2_CFG (12'h000), // Optimized for IES
.RX_DFE_H3_CFG (12'h040), // Optimized for IES
.RX_DFE_H4_CFG (11'h0E0), // Optimized for IES
.RX_DFE_H5_CFG (11'h0E0), // Optimized for IES
.RX_DFE_H6_CFG (11'h020), // GTH new, optimized for IES
.RX_DFE_H7_CFG (11'h020), // GTH new, optimized for IES
.RX_DFE_KL_CFG (33'h000000310), // Changed from 13 to 33-bits, optimized for IES
.RX_DFE_KL_LPM_KH_CFG0 ( 2'h2), // GTH new, optimized for IES, DFE
.RX_DFE_KL_LPM_KH_CFG1 ( 3'h2), // GTH new, optimized for IES
.RX_DFE_KL_LPM_KH_CFG2 ( 4'h2), // GTH new, optimized for IES
.RX_DFE_KL_LPM_KH_OVRDEN ( 1'h1), // GTH new, optimized for IES
.RX_DFE_KL_LPM_KL_CFG0 ( 2'h2), // GTH new, optimized for IES, DFE
.RX_DFE_KL_LPM_KL_CFG1 ( 3'h2), // GTH new, optimized for IES
.RX_DFE_KL_LPM_KL_CFG2 ( 4'h2), // GTH new, optimized for IES
.RX_DFE_KL_LPM_KL_OVRDEN ( 1'b1), // GTH new, optimized for IES
.RX_DFE_LPM_CFG (16'h0080), // Optimized for IES
.RX_DFELPM_CFG0 ( 4'h6), // GTH new, optimized for IES
.RX_DFELPM_CFG1 ( 4'h0), // GTH new, optimized for IES
.RX_DFELPM_KLKH_AGC_STUP_EN ( 1'h1), // GTH new, optimized for IES
.RX_DFE_LPM_HOLD_DURING_EIDLE ( 1'h1), // PCIe use mode
.RX_DFE_ST_CFG (54'h00_C100_000C_003F), // GTH new, optimized for IES
.RX_DFE_UT_CFG (17'h03800), // Optimized for IES
.RX_DFE_VP_CFG (17'h03AA3), // Optimized for IES
//---------- OS Attributes ---------------------------------------------
.RX_OS_CFG (13'h0080), // Optimized for IES
.A_RXOSCALRESET ( 1'd0), // GTH new, optimized for IES
.RXOSCALRESET_TIME ( 5'b00011), // GTH new, optimized for IES
.RXOSCALRESET_TIMEOUT ( 5'b00000), // GTH new, disable timeout, optimized for IES
//---------- Eye Scan Attributes ---------------------------------------
//.ES_CLK_PHASE_SEL ( 1'd0), // GTH new
//.ES_CONTROL ( 6'd0), //
//.ES_ERRDET_EN ("FALSE"), //
.ES_EYE_SCAN_EN ("TRUE"), // Optimized for IES
.ES_HORZ_OFFSET (12'h000), // Optimized for IES
//.ES_PMA_CFG (10'd0), //
//.ES_PRESCALE ( 5'd0), //
//.ES_QUAL_MASK (80'd0), //
//.ES_QUALIFIER (80'd0), //
//.ES_SDATA_MASK (80'd0), //
//.ES_VERT_OFFSET ( 9'd0), //
//---------- TX Buffer Attributes --------------------------------------
.TXBUF_EN (PCIE_TXBUF_EN), //
.TXBUF_RESET_ON_RATE_CHANGE ("TRUE"), //
//---------- RX Buffer Attributes --------------------------------------
.RXBUF_EN ("TRUE"), //
//.RX_BUFFER_CFG ( 6'd0), //
.RX_DEFER_RESET_BUF_EN ("TRUE"), //
.RXBUF_ADDR_MODE ("FULL"), //
.RXBUF_EIDLE_HI_CNT ( 4'd4), // Optimized for sim
.RXBUF_EIDLE_LO_CNT ( 4'd0), // Optimized for sim
.RXBUF_RESET_ON_CB_CHANGE ("TRUE"), //
.RXBUF_RESET_ON_COMMAALIGN ("FALSE"), //
.RXBUF_RESET_ON_EIDLE ("TRUE"), // PCIe
.RXBUF_RESET_ON_RATE_CHANGE ("TRUE"), //
.RXBUF_THRESH_OVRD ("FALSE"), //
.RXBUF_THRESH_OVFLW (61), //
.RXBUF_THRESH_UNDFLW ( 4), //
//.RXBUFRESET_TIME ( 5'b00001), //
//---------- TX Sync Attributes ----------------------------------------
//.TXPH_CFG (16'h0780), //
.TXPH_MONITOR_SEL ( 5'd0), //
//.TXPHDLY_CFG (24'h084020), // [19] : 1 = full range, 0 = half range
//.TXDLY_CFG (16'h001F), //
//.TXDLY_LCFG ( 9'h030), //
//.TXDLY_TAP_CFG (16'd0), //
.TXSYNC_OVRD (TXSYNC_OVRD), // GTH new
.TXSYNC_MULTILANE (TXSYNC_MULTILANE), // GTH new
.TXSYNC_SKIP_DA (1'b0), // GTH new
//---------- RX Sync Attributes ----------------------------------------
//.RXPH_CFG (24'd0), //
.RXPH_MONITOR_SEL ( 5'd0), //
.RXPHDLY_CFG (24'h004020), // [19] : 1 = full range, 0 = half range
//.RXDLY_CFG (16'h001F), //
//.RXDLY_LCFG ( 9'h030), //
//.RXDLY_TAP_CFG (16'd0), //
.RX_DDI_SEL ( 6'd0), //
.RXSYNC_OVRD (RXSYNC_OVRD), // GTH new
.RXSYNC_MULTILANE (RXSYNC_MULTILANE), // GTH new
.RXSYNC_SKIP_DA (1'b0), // GTH new
//---------- Comma Alignment Attributes --------------------------------
.ALIGN_COMMA_DOUBLE ("FALSE"), //
.ALIGN_COMMA_ENABLE (10'b1111111111), // PCIe
.ALIGN_COMMA_WORD ( 1), //
.ALIGN_MCOMMA_DET ("TRUE"), //
.ALIGN_MCOMMA_VALUE (10'b1010000011), //
.ALIGN_PCOMMA_DET ("TRUE"), //
.ALIGN_PCOMMA_VALUE (10'b0101111100), //
.DEC_MCOMMA_DETECT ("TRUE"), //
.DEC_PCOMMA_DETECT ("TRUE"), //
.DEC_VALID_COMMA_ONLY ("FALSE"), // PCIe
.SHOW_REALIGN_COMMA ("FALSE"), // PCIe
.RXSLIDE_AUTO_WAIT ( 7), //
.RXSLIDE_MODE ("PMA"), // PCIe
//---------- Channel Bonding Attributes --------------------------------
.CHAN_BOND_KEEP_ALIGN ("TRUE"), // PCIe
.CHAN_BOND_MAX_SKEW ( 7), //
.CHAN_BOND_SEQ_LEN ( 4), // PCIe
.CHAN_BOND_SEQ_1_ENABLE ( 4'b1111), //
.CHAN_BOND_SEQ_1_1 (10'b0001001010), // D10.2 (4A) - TS1
.CHAN_BOND_SEQ_1_2 (10'b0001001010), // D10.2 (4A) - TS1
.CHAN_BOND_SEQ_1_3 (10'b0001001010), // D10.2 (4A) - TS1
.CHAN_BOND_SEQ_1_4 (10'b0110111100), // K28.5 (BC) - COM
.CHAN_BOND_SEQ_2_USE ("TRUE"), // PCIe
.CHAN_BOND_SEQ_2_ENABLE ( 4'b1111), //
.CHAN_BOND_SEQ_2_1 (10'b0001000101), // D5.2 (45) - TS2
.CHAN_BOND_SEQ_2_2 (10'b0001000101), // D5.2 (45) - TS2
.CHAN_BOND_SEQ_2_3 (10'b0001000101), // D5.2 (45) - TS2
.CHAN_BOND_SEQ_2_4 (10'b0110111100), // K28.5 (BC) - COM
.FTS_DESKEW_SEQ_ENABLE ( 4'b1111), //
.FTS_LANE_DESKEW_EN ("TRUE"), // PCIe
.FTS_LANE_DESKEW_CFG ( 4'b1111), //
//---------- Clock Correction Attributes -------------------------------
.CBCC_DATA_SOURCE_SEL ("DECODED"), //
.CLK_CORRECT_USE ("TRUE"), //
.CLK_COR_KEEP_IDLE ("TRUE"), // PCIe
.CLK_COR_MAX_LAT (CLK_COR_MAX_LAT), //
.CLK_COR_MIN_LAT (CLK_COR_MIN_LAT), //
.CLK_COR_PRECEDENCE ("TRUE"), //
.CLK_COR_REPEAT_WAIT ( 0), //
.CLK_COR_SEQ_LEN ( 1), //
.CLK_COR_SEQ_1_ENABLE ( 4'b1111), //
.CLK_COR_SEQ_1_1 (10'b0100011100), // K28.0 (1C) - SKP
.CLK_COR_SEQ_1_2 (10'b0000000000), // Disabled
.CLK_COR_SEQ_1_3 (10'b0000000000), // Disabled
.CLK_COR_SEQ_1_4 (10'b0000000000), // Disabled
.CLK_COR_SEQ_2_ENABLE ( 4'b0000), // Disabled
.CLK_COR_SEQ_2_USE ("FALSE"), //
.CLK_COR_SEQ_2_1 (10'b0000000000), // Disabled
.CLK_COR_SEQ_2_2 (10'b0000000000), // Disabled
.CLK_COR_SEQ_2_3 (10'b0000000000), // Disabled
.CLK_COR_SEQ_2_4 (10'b0000000000), // Disabled
//---------- 8b10b Attributes ------------------------------------------
.RX_DISPERR_SEQ_MATCH ("TRUE"), //
//---------- 64b/66b & 64b/67b Attributes ------------------------------
.GEARBOX_MODE (3'd0), //
.TXGEARBOX_EN ("FALSE"), //
.RXGEARBOX_EN ("FALSE"), //
//---------- PRBS & Loopback Attributes --------------------------------
.LOOPBACK_CFG ( 1'd1), // GTH new, enable latch when bypassing TX buffer, equivalent to GTX PCS_RSVD_ATTR[0]
.RXPRBS_ERR_LOOPBACK ( 1'd0), //
.TX_LOOPBACK_DRIVE_HIZ ("FALSE"), //
//---------- OOB & SATA Attributes -------------------------------------
.TXOOB_CFG ( 1'd1), // GTH new, filter stale TX data when exiting TX electrical idle, equivalent to GTX PCS_RSVD_ATTR[7]
//.RXOOB_CFG ( 7'b0000110), //
.RXOOB_CLK_CFG (RXOOB_CLK_CFG), // GTH new
//.SAS_MAX_COM (64), //
//.SAS_MIN_COM (36), //
//.SATA_BURST_SEQ_LEN ( 4'b1111), //
//.SATA_BURST_VAL ( 3'b100), //
//.SATA_CPLL_CFG ("VCO_3000MHZ"), //
//.SATA_EIDLE_VAL ( 3'b100), //
//.SATA_MAX_BURST ( 8), //
//.SATA_MAX_INIT (21), //
//.SATA_MAX_WAKE ( 7), //
//.SATA_MIN_BURST ( 4), //
//.SATA_MIN_INIT (12), //
//.SATA_MIN_WAKE ( 4), //
//---------- MISC ------------------------------------------------------
.DMONITOR_CFG (24'h000AB1), // Optimized for debug; [7:4] : 1011 = AGC
//.DMONITOR_CFG (24'h000AB1), // Optimized for debug; [7:4] : 0000 = CDR FSM
.RX_DEBUG_CFG (14'b00000011000000), // Changed from 12 to 14-bits, optimized for IES
//.TST_RSV (32'd0), //
//.UCODEER_CLR ( 1'd0), //
//---------- GTH -------------------------------------------------------
//.ACJTAG_DEBUG_MODE ( 1'd0), // GTH new
//.ACJTAG_MODE ( 1'd0), // GTH new
//.ACJTAG_RESET ( 1'd0), // GTH new
.ADAPT_CFG0 (20'h00C10), // GTH new, optimized for IES
.CFOK_CFG (42'h248_0004_0E80), // GTH new, optimized for IES, [8] : 1 = Skip CFOK
.CFOK_CFG2 ( 6'b100000), // GTH new, optimized for IES
.CFOK_CFG3 ( 6'b100000) // GTH new, optimized for IES
)
gthe2_channel_i
(
//---------- Clock -----------------------------------------------------
.GTGREFCLK (1'd0), //
.GTREFCLK0 (GT_GTREFCLK0), //
.GTREFCLK1 (1'd0), //
.GTNORTHREFCLK0 (1'd0), //
.GTNORTHREFCLK1 (1'd0), //
.GTSOUTHREFCLK0 (1'd0), //
.GTSOUTHREFCLK1 (1'd0), //
.QPLLCLK (GT_QPLLCLK), //
.QPLLREFCLK (GT_QPLLREFCLK), //
.TXUSRCLK (GT_TXUSRCLK), //
.RXUSRCLK (GT_RXUSRCLK), //
.TXUSRCLK2 (GT_TXUSRCLK2), //
.RXUSRCLK2 (GT_RXUSRCLK2), //
.TXSYSCLKSEL (GT_TXSYSCLKSEL), //
.RXSYSCLKSEL (GT_RXSYSCLKSEL), //
.TXOUTCLKSEL (txoutclksel), //
.RXOUTCLKSEL (rxoutclksel), //
.CPLLREFCLKSEL (3'd1), //
.CPLLLOCKDETCLK (1'd0), //
.CPLLLOCKEN (1'd1), //
.CLKRSVD0 (1'd0), // GTH
.CLKRSVD1 (1'd0), // GTH
.TXOUTCLK (GT_TXOUTCLK), //
.RXOUTCLK (GT_RXOUTCLK), //
.TXOUTCLKFABRIC (), //
.RXOUTCLKFABRIC (), //
.TXOUTCLKPCS (), //
.RXOUTCLKPCS (), //
.CPLLLOCK (GT_CPLLLOCK), //
.CPLLREFCLKLOST (), //
.CPLLFBCLKLOST (), //
.RXCDRLOCK (GT_RXCDRLOCK), //
.GTREFCLKMONITOR (), //
//---------- Reset -----------------------------------------------------
.CPLLPD (GT_CPLLPD), //
.CPLLRESET (GT_CPLLRESET), //
.TXUSERRDY (GT_TXUSERRDY), //
.RXUSERRDY (GT_RXUSERRDY), //
.CFGRESET (1'd0), //
.GTRESETSEL (1'd0), //
.RESETOVRD (GT_RESETOVRD), //
.GTTXRESET (GT_GTTXRESET), //
.GTRXRESET (GT_GTRXRESET), //
.TXRESETDONE (GT_TXRESETDONE), //
.RXRESETDONE (GT_RXRESETDONE), //
//---------- TX Data ---------------------------------------------------
.TXDATA ({32'd0, GT_TXDATA}), //
.TXCHARISK ({ 4'd0, GT_TXDATAK}), //
.GTHTXP (GT_TXP), // GTH
.GTHTXN (GT_TXN), // GTH
//---------- RX Data ---------------------------------------------------
.GTHRXP (GT_RXP), // GTH
.GTHRXN (GT_RXN), // GTH
.RXDATA (rxdata), //
.RXCHARISK (rxdatak), //
//---------- Command ---------------------------------------------------
.TXDETECTRX (GT_TXDETECTRX), //
.TXPDELECIDLEMODE ( 1'd0), //
.RXELECIDLEMODE ( 2'd0), //
.TXELECIDLE (GT_TXELECIDLE), //
.TXCHARDISPMODE ({7'd0, GT_TXCOMPLIANCE}), //
.TXCHARDISPVAL ( 8'd0), //
.TXPOLARITY ( 1'd0), //
.RXPOLARITY (GT_RXPOLARITY), //
.TXPD (GT_TXPOWERDOWN), //
.RXPD (GT_RXPOWERDOWN), //
.TXRATE (GT_TXRATE), //
.RXRATE (GT_RXRATE), //
.TXRATEMODE (1'd0), // GTH
.RXRATEMODE (1'd0), // GTH
//---------- Electrical Command ----------------------------------------
.TXMARGIN (GT_TXMARGIN), //
.TXSWING (GT_TXSWING), //
.TXDEEMPH (GT_TXDEEMPH), //
.TXINHIBIT (1'd0), //
.TXBUFDIFFCTRL (3'b100), //
.TXDIFFCTRL (4'b1111), // Select 850mV
.TXPRECURSOR (GT_TXPRECURSOR), //
.TXPRECURSORINV (1'd0), //
.TXMAINCURSOR (GT_TXMAINCURSOR), //
.TXPOSTCURSOR (GT_TXPOSTCURSOR), //
.TXPOSTCURSORINV (1'd0), //
//---------- Status ----------------------------------------------------
.RXVALID (GT_RXVALID), //
.PHYSTATUS (GT_PHYSTATUS), //
.RXELECIDLE (GT_RXELECIDLE), //
.RXSTATUS (GT_RXSTATUS), //
.TXRATEDONE (GT_TXRATEDONE), //
.RXRATEDONE (GT_RXRATEDONE), //
//---------- DRP -------------------------------------------------------
.DRPCLK (GT_DRPCLK), //
.DRPADDR (GT_DRPADDR), //
.DRPEN (GT_DRPEN), //
.DRPDI (GT_DRPDI), //
.DRPWE (GT_DRPWE), //
.DRPDO (GT_DRPDO), //
.DRPRDY (GT_DRPRDY), //
//---------- PMA -------------------------------------------------------
.TXPMARESET (GT_TXPMARESET), //
.RXPMARESET (GT_RXPMARESET), //
.RXLPMEN (rxlpmen), // ***
.RXLPMHFHOLD (GT_RX_CONVERGE), // Set to 1 after convergence
.RXLPMHFOVRDEN ( 1'd0), //
.RXLPMLFHOLD (GT_RX_CONVERGE), // Set to 1 after convergence
.RXLPMLFKLOVRDEN ( 1'd0), //
.TXQPIBIASEN ( 1'd0), //
.TXQPISTRONGPDOWN ( 1'd0), //
.TXQPIWEAKPUP ( 1'd0), //
.RXQPIEN ( 1'd0), // Optimized for IES
.PMARSVDIN ( 5'd0), //
.GTRSVD (16'd0), //
.TXQPISENP (), //
.TXQPISENN (), //
.RXQPISENP (), //
.RXQPISENN (), //
.DMONITOROUT (dmonitorout), // GTH 15-bits.
//---------- PCS -------------------------------------------------------
.TXPCSRESET (GT_TXPCSRESET), //
.RXPCSRESET (GT_RXPCSRESET), //
.PCSRSVDIN (16'd0), // [0]: 1 = TXRATE async, [1]: 1 = RXRATE async
.PCSRSVDIN2 ( 5'd0), //
.PCSRSVDOUT (), //
//---------- CDR -------------------------------------------------------
.RXCDRRESET (GT_RXCDRRESET), //
.RXCDRRESETRSV (1'd0), //
.RXCDRFREQRESET (GT_RXCDRFREQRESET), //
.RXCDRHOLD (1'd0), //
.RXCDROVRDEN (1'd0), //
//---------- PI --------------------------------------------------------
.TXPIPPMEN (1'd0), // GTH new
.TXPIPPMOVRDEN (1'd0), // GTH new
.TXPIPPMPD (1'd0), // GTH new
.TXPIPPMSEL (1'd0), // GTH new
.TXPIPPMSTEPSIZE (5'd0), // GTH new
//---------- DFE -------------------------------------------------------
.RXDFELPMRESET (GT_RXDFELPMRESET), //
.RXDFEAGCTRL (5'b10000), // GTH new, optimized for IES
.RXDFECM1EN (1'd0), //
.RXDFEVSEN (1'd0), //
.RXDFETAP2HOLD (1'd0), //
.RXDFETAP2OVRDEN (1'd0), //
.RXDFETAP3HOLD (1'd0), //
.RXDFETAP3OVRDEN (1'd0), //
.RXDFETAP4HOLD (1'd0), //
.RXDFETAP4OVRDEN (1'd0), //
.RXDFETAP5HOLD (1'd0), //
.RXDFETAP5OVRDEN (1'd0), //
.RXDFETAP6HOLD (1'd0), // GTH new
.RXDFETAP6OVRDEN (1'd0), // GTH new
.RXDFETAP7HOLD (1'd0), // GTH new
.RXDFETAP7OVRDEN (1'd0), // GTH new
.RXDFEAGCHOLD (GT_RX_CONVERGE), // Set to 1 after convergence
.RXDFEAGCOVRDEN (rxlpmen), //
.RXDFELFHOLD (GT_RX_CONVERGE), // Set to 1 after convergence
.RXDFELFOVRDEN (1'd0), //
.RXDFEUTHOLD (1'd0), //
.RXDFEUTOVRDEN (1'd0), //
.RXDFEVPHOLD (1'd0), //
.RXDFEVPOVRDEN (1'd0), //
.RXDFEXYDEN (1'd1), // Optimized for IES
.RXMONITORSEL (2'd0), //
.RXDFESLIDETAP (5'd0), // GTH new
.RXDFESLIDETAPID (6'd0), // GTH new
.RXDFESLIDETAPHOLD (1'd0), // GTH new
.RXDFESLIDETAPOVRDEN (1'd0), // GTH new
.RXDFESLIDETAPADAPTEN (1'd0), // GTH new
.RXDFESLIDETAPINITOVRDEN (1'd0), // GTH new
.RXDFESLIDETAPONLYADAPTEN (1'd0), // GTH new
.RXDFESLIDETAPSTROBE (1'd0), // GTH new
.RXMONITOROUT (), //
.RXDFESLIDETAPSTARTED (), // GTH new
.RXDFESLIDETAPSTROBEDONE (), // GTH new
.RXDFESLIDETAPSTROBESTARTED (), // GTH new
.RXDFESTADAPTDONE (), // GTH new
//---------- OS --------------------------------------------------------
.RXOSHOLD (1'd0), // optimized for IES
.RXOSOVRDEN (1'd0), // optimized for IES
.RXOSINTEN (1'd1), // GTH new, optimized for IES
.RXOSINTHOLD (1'd0), // GTH new, optimized for IES
.RXOSINTNTRLEN (1'd0), // GTH new, optimized for IES
.RXOSINTOVRDEN (1'd0), // GTH new, optimized for IES
.RXOSINTSTROBE (1'd0), // GTH new, optimized for IES
.RXOSINTTESTOVRDEN (1'd0), // GTH new, optimized for IES
.RXOSINTCFG (4'b0110), // GTH new, optimized for IES
.RXOSINTID0 (4'b0000), // GTH new, optimized for IES
.RXOSCALRESET ( 1'd0), // GTH, optimized for IES
.RSOSINTDONE (), // GTH new
.RXOSINTSTARTED (), // GTH new
.RXOSINTSTROBEDONE (), // GTH new
.RXOSINTSTROBESTARTED (), // GTH new
//---------- Eye Scan --------------------------------------------------
.EYESCANRESET (GT_EYESCANRESET), //
.EYESCANMODE (1'd0), //
.EYESCANTRIGGER (1'd0), //
.EYESCANDATAERROR (), //
//---------- TX Buffer -------------------------------------------------
.TXBUFSTATUS (), //
//---------- RX Buffer -------------------------------------------------
.RXBUFRESET (GT_RXBUFRESET), //
.RXBUFSTATUS (GT_RXBUFSTATUS), //
//---------- TX Sync ---------------------------------------------------
.TXPHDLYRESET (GT_TXPHDLYRESET), //
.TXPHDLYTSTCLK (1'd0), //
.TXPHALIGN (GT_TXPHALIGN), //
.TXPHALIGNEN (GT_TXPHALIGNEN), //
.TXPHDLYPD (1'd0), //
.TXPHINIT (GT_TXPHINIT), //
.TXPHOVRDEN (1'd0), //
.TXDLYBYPASS (GT_TXDLYBYPASS), //
.TXDLYSRESET (GT_TXDLYSRESET), //
.TXDLYEN (GT_TXDLYEN), //
.TXDLYOVRDEN (1'd0), //
.TXDLYHOLD (1'd0), //
.TXDLYUPDOWN (1'd0), //
.TXPHALIGNDONE (GT_TXPHALIGNDONE), //
.TXPHINITDONE (GT_TXPHINITDONE), //
.TXDLYSRESETDONE (GT_TXDLYSRESETDONE), //
.TXSYNCMODE (GT_TXSYNCMODE), // GTH
.TXSYNCIN (GT_TXSYNCIN), // GTH
.TXSYNCALLIN (GT_TXSYNCALLIN), // GTH
.TXSYNCDONE (GT_TXSYNCDONE), // GTH
.TXSYNCOUT (GT_TXSYNCOUT), // GTH
//---------- RX Sync ---------------------------------------------------
.RXPHDLYRESET (1'd0), //
.RXPHALIGN (GT_RXPHALIGN), //
.RXPHALIGNEN (GT_RXPHALIGNEN), //
.RXPHDLYPD (1'd0), //
.RXPHOVRDEN (1'd0), //
.RXDLYBYPASS (GT_RXDLYBYPASS), //
.RXDLYSRESET (GT_RXDLYSRESET), //
.RXDLYEN (GT_RXDLYEN), //
.RXDLYOVRDEN (1'd0), //
.RXDDIEN (GT_RXDDIEN), //
.RXPHALIGNDONE (GT_RXPHALIGNDONE), //
.RXPHMONITOR (), //
.RXPHSLIPMONITOR (), //
.RXDLYSRESETDONE (GT_RXDLYSRESETDONE), //
.RXSYNCMODE (GT_RXSYNCMODE), // GTH
.RXSYNCIN (GT_RXSYNCIN), // GTH
.RXSYNCALLIN (GT_RXSYNCALLIN), // GTH
.RXSYNCDONE (GT_RXSYNCDONE), // GTH
.RXSYNCOUT (GT_RXSYNCOUT), // GTH
//---------- Comma Alignment -------------------------------------------
.RXCOMMADETEN ( 1'd1), //
.RXMCOMMAALIGNEN (!GT_GEN3), // 0 = disable comma alignment in Gen3
.RXPCOMMAALIGNEN (!GT_GEN3), // 0 = disable comma alignment in Gen3
.RXSLIDE ( GT_RXSLIDE), //
.RXCOMMADET (GT_RXCOMMADET), //
.RXCHARISCOMMA (rxchariscomma), //
.RXBYTEISALIGNED (GT_RXBYTEISALIGNED), //
.RXBYTEREALIGN (GT_RXBYTEREALIGN), //
//---------- Channel Bonding -------------------------------------------
.RXCHBONDEN (GT_RXCHBONDEN), //
.RXCHBONDI (GT_RXCHBONDI), //
.RXCHBONDLEVEL (GT_RXCHBONDLEVEL), //
.RXCHBONDMASTER (GT_RXCHBONDMASTER), //
.RXCHBONDSLAVE (GT_RXCHBONDSLAVE), //
.RXCHANBONDSEQ (), //
.RXCHANISALIGNED (GT_RXCHANISALIGNED), //
.RXCHANREALIGN (), //
.RXCHBONDO (GT_RXCHBONDO), //
//---------- Clock Correction -----------------------------------------
.RXCLKCORCNT (), //
//---------- 8b10b -----------------------------------------------------
.TX8B10BBYPASS (8'd0), //
.TX8B10BEN (!GT_GEN3), // 0 = disable TX 8b10b in Gen3
.RX8B10BEN (!GT_GEN3), // 0 = disable RX 8b10b in Gen3
.RXDISPERR (), //
.RXNOTINTABLE (), //
//---------- 64b/66b & 64b/67b -----------------------------------------
.TXHEADER (3'd0), //
.TXSEQUENCE (7'd0), //
.TXSTARTSEQ (1'd0), //
.RXGEARBOXSLIP (1'd0), //
.TXGEARBOXREADY (), //
.RXDATAVALID (), //
.RXHEADER (), //
.RXHEADERVALID (), //
.RXSTARTOFSEQ (), //
//---------- PRBS & Loopback -------------------------------------------
.TXPRBSSEL (GT_TXPRBSSEL), //
.RXPRBSSEL (GT_RXPRBSSEL), //
.TXPRBSFORCEERR (GT_TXPRBSFORCEERR), //
.RXPRBSCNTRESET (GT_RXPRBSCNTRESET), //
.LOOPBACK (GT_LOOPBACK), //
.RXPRBSERR (GT_RXPRBSERR), //
//---------- OOB -------------------------------------------------------
.SIGVALIDCLK (GT_OOBCLK), // GTH, optimized for debug
.TXCOMINIT (1'd0), //
.TXCOMSAS (1'd0), //
.TXCOMWAKE (1'd0), //
.RXOOBRESET (1'd0), //
.TXCOMFINISH (), //
.RXCOMINITDET (), //
.RXCOMSASDET (), //
.RXCOMWAKEDET (), //
//---------- MISC ------------------------------------------------------
.SETERRSTATUS ( 1'd0), //
.TXDIFFPD ( 1'd0), //
.TXPISOPD ( 1'd0), //
.TSTIN (20'hFFFFF), //
//---------- GTH -------------------------------------------------------
.RXADAPTSELTEST (14'd0), // GTH new
.DMONFIFORESET ( 1'd0), // GTH
.DMONITORCLK (dmonitorclk), // GTH, optimized for debug
//.DMONITORCLK (GT_DRPCLK), // GTH, optimized for debug
.RXPMARESETDONE (GT_RXPMARESETDONE), // GTH
.TXPMARESETDONE () // GTH
);
end
else
begin : gtx_channel
//---------- GTX Channel Module --------------------------------------------
GTXE2_CHANNEL #
(
//---------- Simulation Attributes -------------------------------------
.SIM_CPLLREFCLK_SEL (3'b001), //
.SIM_RESET_SPEEDUP (PCIE_SIM_SPEEDUP), //
.SIM_RECEIVER_DETECT_PASS ("TRUE"), //
.SIM_TX_EIDLE_DRIVE_LEVEL (PCIE_SIM_TX_EIDLE_DRIVE_LEVEL), //
.SIM_VERSION (PCIE_USE_MODE), //
//---------- Clock Attributes ------------------------------------------
.CPLL_REFCLK_DIV (CPLL_REFCLK_DIV), //
.CPLL_FBDIV_45 (CPLL_FBDIV_45), //
.CPLL_FBDIV (CPLL_FBDIV), //
.TXOUT_DIV (OUT_DIV), //
.RXOUT_DIV (OUT_DIV), //
.TX_CLK25_DIV (CLK25_DIV), //
.RX_CLK25_DIV (CLK25_DIV), //
.TX_CLKMUX_PD (CLKMUX_PD), // GTX
.RX_CLKMUX_PD (CLKMUX_PD), // GTX
.TX_XCLK_SEL (TX_XCLK_SEL), // TXOUT = use TX buffer, TXUSR = bypass TX buffer
.RX_XCLK_SEL ("RXREC"), // RXREC = use RX buffer, RXUSR = bypass RX buffer
.OUTREFCLK_SEL_INV ( 2'b11), //
.CPLL_CFG (CPLL_CFG), // Optimized for silicon
//.CPLL_INIT_CFG (24'h00001E), //
//.CPLL_LOCK_CFG (16'h01E8), //
//---------- Reset Attributes ------------------------------------------
.TXPCSRESET_TIME (5'b00001), //
.RXPCSRESET_TIME (5'b00001), //
.TXPMARESET_TIME (5'b00011), //
.RXPMARESET_TIME (5'b00011), // Optimized for sim and for DRP
//.RXISCANRESET_TIME (5'b00001), //
//---------- TX Data Attributes ----------------------------------------
.TX_DATA_WIDTH (20), // 2-byte external datawidth for Gen1/Gen2
.TX_INT_DATAWIDTH ( 0), // 2-byte internal datawidth for Gen1/Gen2
//---------- RX Data Attributes ----------------------------------------
.RX_DATA_WIDTH (20), // 2-byte external datawidth for Gen1/Gen2
.RX_INT_DATAWIDTH ( 0), // 2-byte internal datawidth for Gen1/Gen2
//---------- Command Attributes ----------------------------------------
.TX_RXDETECT_CFG (TX_RXDETECT_CFG), //
.TX_RXDETECT_REF (TX_RXDETECT_REF), //
.RX_CM_SEL ( 2'd3), // 0 = AVTT, 1 = GND, 2 = Float, 3 = Programmable
.RX_CM_TRIM ( 3'b010), // Select 800mV
.TX_EIDLE_ASSERT_DELAY (PCIE_TX_EIDLE_ASSERT_DELAY), // Optimized for sim (3'd4)
.TX_EIDLE_DEASSERT_DELAY ( 3'b100), // Optimized for sim
//.PD_TRANS_TIME_FROM_P2 (12'h03C), //
.PD_TRANS_TIME_NONE_P2 ( 8'h09), //
//.PD_TRANS_TIME_TO_P2 ( 8'h64), //
//.TRANS_TIME_RATE ( 8'h0E), //
//---------- Electrical Command Attributes -----------------------------
.TX_DRIVE_MODE ("PIPE"), // Gen1/Gen2 = PIPE, Gen3 = PIPEGEN3
.TX_DEEMPH0 ( 5'b10100), // 6.0 dB
.TX_DEEMPH1 ( 5'b01011), // 3.5 dB
.TX_MARGIN_FULL_0 ( 7'b1001111), // 1000 mV
.TX_MARGIN_FULL_1 ( 7'b1001110), // 950 mV
.TX_MARGIN_FULL_2 ( 7'b1001101), // 900 mV
.TX_MARGIN_FULL_3 ( 7'b1001100), // 850 mV
.TX_MARGIN_FULL_4 ( 7'b1000011), // 400 mV
.TX_MARGIN_LOW_0 ( 7'b1000101), // 500 mV
.TX_MARGIN_LOW_1 ( 7'b1000110), // 450 mV
.TX_MARGIN_LOW_2 ( 7'b1000011), // 400 mV
.TX_MARGIN_LOW_3 ( 7'b1000010), // 350 mV
.TX_MARGIN_LOW_4 ( 7'b1000000), // 250 mV
.TX_MAINCURSOR_SEL ( 1'b0), //
.TX_PREDRIVER_MODE ( 1'b0), // GTX
.TX_QPI_STATUS_EN ( 1'b0), //
//---------- Status Attributes -----------------------------------------
.RX_SIG_VALID_DLY (4), // Optimized for sim
//---------- DRP Attributes --------------------------------------------
//---------- PCS Attributes --------------------------------------------
.PCS_PCIE_EN ("TRUE"), // PCIe
.PCS_RSVD_ATTR (PCS_RSVD_ATTR), //
//---------- PMA Attributes --------------------------------------------
.PMA_RSV (32'h00018480), // Optimized for GES Gen1/Gen2
.PMA_RSV2 (16'h2070), // Optimized for silicon, [4] RX_CM_TRIM[4], [5] = 1 Enable Eye Scan
//.PMA_RSV3 ( 2'd0), //
//.PMA_RSV4 (32'd0), // GTX 3.0 new
.RX_BIAS_CFG (12'b000000000100), // Optimized for GES
//.TERM_RCAL_CFG ( 5'b10000), //
//.TERM_RCAL_OVRD ( 1'd0), //
//---------- CDR Attributes --------------------------------------------
.RXCDR_CFG (RXCDR_CFG_GTX), //
.RXCDR_LOCK_CFG ( 6'b010101), // [5:3] Window Refresh, [2:1] Window Size, [0] Enable Detection (sensitive lock = 6'b111001)
.RXCDR_HOLD_DURING_EIDLE ( 1'd1), // Hold RX CDR on electrical idle for Gen1/Gen2
.RXCDR_FR_RESET_ON_EIDLE ( 1'd0), // Reset RX CDR frequency on electrical idle for Gen3
.RXCDR_PH_RESET_ON_EIDLE ( 1'd0), // Reset RX CDR phase on electrical idle for Gen3
//.RXCDRFREQRESET_TIME ( 5'b00001), //
//.RXCDRPHRESET_TIME ( 5'b00001), //
//---------- LPM Attributes --------------------------------------------
.RXLPM_HF_CFG (14'h00F0), // Optimized for silicon
.RXLPM_LF_CFG (14'h00F0), // Optimized for silicon
//---------- DFE Attributes --------------------------------------------
//.RXDFELPMRESET_TIME ( 7'b0001111), //
.RX_DFE_GAIN_CFG (23'h020FEA), // Optimized for GES, IES = 23'h001F0A
.RX_DFE_H2_CFG (12'b000000000000), // Optimized for GES
.RX_DFE_H3_CFG (12'b000001000000), // Optimized for GES
.RX_DFE_H4_CFG (11'b00011110000), // Optimized for GES
.RX_DFE_H5_CFG (11'b00011100000), // Optimized for GES
.RX_DFE_KL_CFG (13'b0000011111110), // Optimized for GES
.RX_DFE_KL_CFG2 (32'h3290D86C), // Optimized for GES, GTX new, CTLE 3 3 5, default = 32'h3010D90C
.RX_DFE_LPM_CFG (16'h0954), // Optimized for GES
.RX_DFE_LPM_HOLD_DURING_EIDLE ( 1'd1), // Optimized for PCIe
.RX_DFE_UT_CFG (17'b10001111000000000), // Optimized for GES, IES = 17'h08F00
.RX_DFE_VP_CFG (17'b00011111100000011), // Optimized for GES
.RX_DFE_XYD_CFG (13'h0000), // Optimized for 4.0
//---------- OS Attributes ---------------------------------------------
.RX_OS_CFG (13'b0000010000000), // Optimized for GES
//---------- Eye Scan Attributes ---------------------------------------
//.ES_CONTROL ( 6'd0), //
//.ES_ERRDET_EN ("FALSE"), //
.ES_EYE_SCAN_EN ("TRUE"), //
.ES_HORZ_OFFSET (12'd0), //
//.ES_PMA_CFG (10'd0), //
//.ES_PRESCALE ( 5'd0), //
//.ES_QUAL_MASK (80'd0), //
//.ES_QUALIFIER (80'd0), //
//.ES_SDATA_MASK (80'd0), //
//.ES_VERT_OFFSET ( 9'd0), //
//---------- TX Buffer Attributes --------------------------------------
.TXBUF_EN (PCIE_TXBUF_EN), //
.TXBUF_RESET_ON_RATE_CHANGE ("TRUE"), //
//---------- RX Buffer Attributes --------------------------------------
.RXBUF_EN ("TRUE"), //
//.RX_BUFFER_CFG ( 6'd0), //
.RX_DEFER_RESET_BUF_EN ("TRUE"), //
.RXBUF_ADDR_MODE ("FULL"), //
.RXBUF_EIDLE_HI_CNT ( 4'd4), // Optimized for sim
.RXBUF_EIDLE_LO_CNT ( 4'd0), // Optimized for sim
.RXBUF_RESET_ON_CB_CHANGE ("TRUE"), //
.RXBUF_RESET_ON_COMMAALIGN ("FALSE"), //
.RXBUF_RESET_ON_EIDLE ("TRUE"), // PCIe
.RXBUF_RESET_ON_RATE_CHANGE ("TRUE"), //
.RXBUF_THRESH_OVRD ("FALSE"), //
.RXBUF_THRESH_OVFLW (61), //
.RXBUF_THRESH_UNDFLW ( 4), //
//.RXBUFRESET_TIME ( 5'b00001), //
//---------- TX Sync Attributes ----------------------------------------
//.TXPH_CFG (16'h0780), //
.TXPH_MONITOR_SEL ( 5'd0), //
//.TXPHDLY_CFG (24'h084020), //
//.TXDLY_CFG (16'h001F), //
//.TXDLY_LCFG ( 9'h030), //
//.TXDLY_TAP_CFG (16'd0), //
//---------- RX Sync Attributes ----------------------------------------
//.RXPH_CFG (24'd0), //
.RXPH_MONITOR_SEL ( 5'd0), //
.RXPHDLY_CFG (24'h004020), // Optimized for sim
//.RXDLY_CFG (16'h001F), //
//.RXDLY_LCFG ( 9'h030), //
//.RXDLY_TAP_CFG (16'd0), //
.RX_DDI_SEL ( 6'd0), //
//---------- Comma Alignment Attributes --------------------------------
.ALIGN_COMMA_DOUBLE ("FALSE"), //
.ALIGN_COMMA_ENABLE (10'b1111111111), // PCIe
.ALIGN_COMMA_WORD ( 1), //
.ALIGN_MCOMMA_DET ("TRUE"), //
.ALIGN_MCOMMA_VALUE (10'b1010000011), //
.ALIGN_PCOMMA_DET ("TRUE"), //
.ALIGN_PCOMMA_VALUE (10'b0101111100), //
.DEC_MCOMMA_DETECT ("TRUE"), //
.DEC_PCOMMA_DETECT ("TRUE"), //
.DEC_VALID_COMMA_ONLY ("FALSE"), // PCIe
.SHOW_REALIGN_COMMA ("FALSE"), // PCIe
.RXSLIDE_AUTO_WAIT ( 7), //
.RXSLIDE_MODE ("PMA"), // PCIe
//---------- Channel Bonding Attributes --------------------------------
.CHAN_BOND_KEEP_ALIGN ("TRUE"), // PCIe
.CHAN_BOND_MAX_SKEW ( 7), //
.CHAN_BOND_SEQ_LEN ( 4), // PCIe
.CHAN_BOND_SEQ_1_ENABLE ( 4'b1111), //
.CHAN_BOND_SEQ_1_1 (10'b0001001010), // D10.2 (4A) - TS1
.CHAN_BOND_SEQ_1_2 (10'b0001001010), // D10.2 (4A) - TS1
.CHAN_BOND_SEQ_1_3 (10'b0001001010), // D10.2 (4A) - TS1
.CHAN_BOND_SEQ_1_4 (10'b0110111100), // K28.5 (BC) - COM
.CHAN_BOND_SEQ_2_USE ("TRUE"), // PCIe
.CHAN_BOND_SEQ_2_ENABLE ( 4'b1111), //
.CHAN_BOND_SEQ_2_1 (10'b0001000101), // D5.2 (45) - TS2
.CHAN_BOND_SEQ_2_2 (10'b0001000101), // D5.2 (45) - TS2
.CHAN_BOND_SEQ_2_3 (10'b0001000101), // D5.2 (45) - TS2
.CHAN_BOND_SEQ_2_4 (10'b0110111100), // K28.5 (BC) - COM
.FTS_DESKEW_SEQ_ENABLE ( 4'b1111), //
.FTS_LANE_DESKEW_EN ("TRUE"), // PCIe
.FTS_LANE_DESKEW_CFG ( 4'b1111), //
//---------- Clock Correction Attributes -------------------------------
.CBCC_DATA_SOURCE_SEL ("DECODED"), //
.CLK_CORRECT_USE ("TRUE"), //
.CLK_COR_KEEP_IDLE ("TRUE"), // PCIe
.CLK_COR_MAX_LAT (CLK_COR_MAX_LAT), //
.CLK_COR_MIN_LAT (CLK_COR_MIN_LAT), //
.CLK_COR_PRECEDENCE ("TRUE"), //
.CLK_COR_REPEAT_WAIT ( 0), //
.CLK_COR_SEQ_LEN ( 1), //
.CLK_COR_SEQ_1_ENABLE ( 4'b1111), //
.CLK_COR_SEQ_1_1 (10'b0100011100), // K28.0 (1C) - SKP
.CLK_COR_SEQ_1_2 (10'b0000000000), // Disabled
.CLK_COR_SEQ_1_3 (10'b0000000000), // Disabled
.CLK_COR_SEQ_1_4 (10'b0000000000), // Disabled
.CLK_COR_SEQ_2_ENABLE ( 4'b0000), // Disabled
.CLK_COR_SEQ_2_USE ("FALSE"), //
.CLK_COR_SEQ_2_1 (10'b0000000000), // Disabled
.CLK_COR_SEQ_2_2 (10'b0000000000), // Disabled
.CLK_COR_SEQ_2_3 (10'b0000000000), // Disabled
.CLK_COR_SEQ_2_4 (10'b0000000000), // Disabled
//---------- 8b10b Attributes ------------------------------------------
.RX_DISPERR_SEQ_MATCH ("TRUE"), //
//---------- 64b/66b & 64b/67b Attributes ------------------------------
.GEARBOX_MODE (3'd0), //
.TXGEARBOX_EN ("FALSE"), //
.RXGEARBOX_EN ("FALSE"), //
//---------- PRBS & Loopback Attributes --------------------------------
.RXPRBS_ERR_LOOPBACK (1'd0), //
.TX_LOOPBACK_DRIVE_HIZ ("FALSE"), //
//---------- OOB & SATA Attributes -------------------------------------
//.RXOOB_CFG ( 7'b0000110), //
//.SAS_MAX_COM (64), //
//.SAS_MIN_COM (36), //
//.SATA_BURST_SEQ_LEN ( 4'b1111), //
//.SATA_BURST_VAL ( 3'b100), //
//.SATA_CPLL_CFG ("VCO_3000MHZ"), //
//.SATA_EIDLE_VAL ( 3'b100), //
//.SATA_MAX_BURST ( 8), //
//.SATA_MAX_INIT (21), //
//.SATA_MAX_WAKE ( 7), //
//.SATA_MIN_BURST ( 4), //
//.SATA_MIN_INIT (12), //
//.SATA_MIN_WAKE ( 4), //
//---------- MISC ------------------------------------------------------
.DMONITOR_CFG (24'h000B01), // Optimized for debug
.RX_DEBUG_CFG (12'd0) // Optimized for GES
//.TST_RSV (32'd0), //
//.UCODEER_CLR ( 1'd0) //
)
gtxe2_channel_i
(
//---------- Clock -----------------------------------------------------
.GTGREFCLK (1'd0), //
.GTREFCLK0 (GT_GTREFCLK0), //
.GTREFCLK1 (1'd0), //
.GTNORTHREFCLK0 (1'd0), //
.GTNORTHREFCLK1 (1'd0), //
.GTSOUTHREFCLK0 (1'd0), //
.GTSOUTHREFCLK1 (1'd0), //
.QPLLCLK (GT_QPLLCLK), //
.QPLLREFCLK (GT_QPLLREFCLK), //
.TXUSRCLK (GT_TXUSRCLK), //
.RXUSRCLK (GT_RXUSRCLK), //
.TXUSRCLK2 (GT_TXUSRCLK2), //
.RXUSRCLK2 (GT_RXUSRCLK2), //
.TXSYSCLKSEL (GT_TXSYSCLKSEL), //
.RXSYSCLKSEL (GT_RXSYSCLKSEL), //
.TXOUTCLKSEL (txoutclksel), //
.RXOUTCLKSEL (rxoutclksel), //
.CPLLREFCLKSEL (3'd1), //
.CPLLLOCKDETCLK (1'd0), //
.CPLLLOCKEN (1'd1), //
.CLKRSVD ({2'd0, dmonitorclk, GT_OOBCLK}), // Optimized for debug
.TXOUTCLK (GT_TXOUTCLK), //
.RXOUTCLK (GT_RXOUTCLK), //
.TXOUTCLKFABRIC (), //
.RXOUTCLKFABRIC (), //
.TXOUTCLKPCS (), //
.RXOUTCLKPCS (), //
.CPLLLOCK (GT_CPLLLOCK), //
.CPLLREFCLKLOST (), //
.CPLLFBCLKLOST (), //
.RXCDRLOCK (GT_RXCDRLOCK), //
.GTREFCLKMONITOR (), //
//---------- Reset -----------------------------------------------------
.CPLLPD (GT_CPLLPD), //
.CPLLRESET (GT_CPLLRESET), //
.TXUSERRDY (GT_TXUSERRDY), //
.RXUSERRDY (GT_RXUSERRDY), //
.CFGRESET (1'd0), //
.GTRESETSEL (1'd0), //
.RESETOVRD (GT_RESETOVRD), //
.GTTXRESET (GT_GTTXRESET), //
.GTRXRESET (GT_GTRXRESET), //
.TXRESETDONE (GT_TXRESETDONE), //
.RXRESETDONE (GT_RXRESETDONE), //
//---------- TX Data ---------------------------------------------------
.TXDATA ({32'd0, GT_TXDATA}), //
.TXCHARISK ({ 4'd0, GT_TXDATAK}), //
.GTXTXP (GT_TXP), // GTX
.GTXTXN (GT_TXN), // GTX
//---------- RX Data ---------------------------------------------------
.GTXRXP (GT_RXP), // GTX
.GTXRXN (GT_RXN), // GTX
.RXDATA (rxdata), //
.RXCHARISK (rxdatak), //
//---------- Command ---------------------------------------------------
.TXDETECTRX (GT_TXDETECTRX), //
.TXPDELECIDLEMODE ( 1'd0), //
.RXELECIDLEMODE ( 2'd0), //
.TXELECIDLE (GT_TXELECIDLE), //
.TXCHARDISPMODE ({7'd0, GT_TXCOMPLIANCE}), //
.TXCHARDISPVAL ( 8'd0), //
.TXPOLARITY ( 1'd0), //
.RXPOLARITY (GT_RXPOLARITY), //
.TXPD (GT_TXPOWERDOWN), //
.RXPD (GT_RXPOWERDOWN), //
.TXRATE (GT_TXRATE), //
.RXRATE (GT_RXRATE), //
//---------- Electrical Command ----------------------------------------
.TXMARGIN (GT_TXMARGIN), //
.TXSWING (GT_TXSWING), //
.TXDEEMPH (GT_TXDEEMPH), //
.TXINHIBIT (1'd0), //
.TXBUFDIFFCTRL (3'b100), //
.TXDIFFCTRL (4'b1100), //
.TXPRECURSOR (GT_TXPRECURSOR), //
.TXPRECURSORINV (1'd0), //
.TXMAINCURSOR (GT_TXMAINCURSOR), //
.TXPOSTCURSOR (GT_TXPOSTCURSOR), //
.TXPOSTCURSORINV (1'd0), //
//---------- Status ----------------------------------------------------
.RXVALID (GT_RXVALID), //
.PHYSTATUS (GT_PHYSTATUS), //
.RXELECIDLE (GT_RXELECIDLE), //
.RXSTATUS (GT_RXSTATUS), //
.TXRATEDONE (GT_TXRATEDONE), //
.RXRATEDONE (GT_RXRATEDONE), //
//---------- DRP -------------------------------------------------------
.DRPCLK (GT_DRPCLK), //
.DRPADDR (GT_DRPADDR), //
.DRPEN (GT_DRPEN), //
.DRPDI (GT_DRPDI), //
.DRPWE (GT_DRPWE), //
.DRPDO (GT_DRPDO), //
.DRPRDY (GT_DRPRDY), //
//---------- PMA -------------------------------------------------------
.TXPMARESET (GT_TXPMARESET), //
.RXPMARESET (GT_RXPMARESET), //
.RXLPMEN (rxlpmen), //
.RXLPMHFHOLD ( 1'd0), //
.RXLPMHFOVRDEN ( 1'd0), //
.RXLPMLFHOLD ( 1'd0), //
.RXLPMLFKLOVRDEN ( 1'd0), //
.TXQPIBIASEN ( 1'd0), //
.TXQPISTRONGPDOWN ( 1'd0), //
.TXQPIWEAKPUP ( 1'd0), //
.RXQPIEN ( 1'd0), //
.PMARSVDIN ( 5'd0), //
.PMARSVDIN2 ( 5'd0), // GTX
.GTRSVD (16'd0), //
.TXQPISENP (), //
.TXQPISENN (), //
.RXQPISENP (), //
.RXQPISENN (), //
.DMONITOROUT (dmonitorout[7:0]), // GTX 8-bits
//---------- PCS -------------------------------------------------------
.TXPCSRESET (GT_TXPCSRESET), //
.RXPCSRESET (GT_RXPCSRESET), //
.PCSRSVDIN (16'd0), // [0]: 1 = TXRATE async, [1]: 1 = RXRATE async
.PCSRSVDIN2 ( 5'd0), //
.PCSRSVDOUT (), //
//---------- CDR -------------------------------------------------------
.RXCDRRESET (GT_RXCDRRESET), //
.RXCDRRESETRSV (1'd0), //
.RXCDRFREQRESET (GT_RXCDRFREQRESET), //
.RXCDRHOLD (1'd0), //
.RXCDROVRDEN (1'd0), //
//---------- DFE -------------------------------------------------------
.RXDFELPMRESET (GT_RXDFELPMRESET), //
.RXDFECM1EN (1'd0), //
.RXDFEVSEN (1'd0), //
.RXDFETAP2HOLD (1'd0), //
.RXDFETAP2OVRDEN (1'd0), //
.RXDFETAP3HOLD (1'd0), //
.RXDFETAP3OVRDEN (1'd0), //
.RXDFETAP4HOLD (1'd0), //
.RXDFETAP4OVRDEN (1'd0), //
.RXDFETAP5HOLD (1'd0), //
.RXDFETAP5OVRDEN (1'd0), //
.RXDFEAGCHOLD (GT_RX_CONVERGE), // Optimized for GES, Set to 1 after convergence
.RXDFEAGCOVRDEN (1'd0), //
.RXDFELFHOLD (1'd0), //
.RXDFELFOVRDEN (1'd1), // Optimized for GES
.RXDFEUTHOLD (1'd0), //
.RXDFEUTOVRDEN (1'd0), //
.RXDFEVPHOLD (1'd0), //
.RXDFEVPOVRDEN (1'd0), //
.RXDFEXYDEN (1'd0), //
.RXDFEXYDHOLD (1'd0), // GTX
.RXDFEXYDOVRDEN (1'd0), // GTX
.RXMONITORSEL (2'd0), //
.RXMONITOROUT (), //
//---------- OS --------------------------------------------------------
.RXOSHOLD (1'd0), //
.RXOSOVRDEN (1'd0), //
//---------- Eye Scan --------------------------------------------------
.EYESCANRESET (GT_EYESCANRESET), //
.EYESCANMODE (1'd0), //
.EYESCANTRIGGER (1'd0), //
.EYESCANDATAERROR (), //
//---------- TX Buffer -------------------------------------------------
.TXBUFSTATUS (), //
//---------- RX Buffer -------------------------------------------------
.RXBUFRESET (GT_RXBUFRESET), //
.RXBUFSTATUS (GT_RXBUFSTATUS), //
//---------- TX Sync ---------------------------------------------------
.TXPHDLYRESET (1'd0), //
.TXPHDLYTSTCLK (1'd0), //
.TXPHALIGN (GT_TXPHALIGN), //
.TXPHALIGNEN (GT_TXPHALIGNEN), //
.TXPHDLYPD (1'd0), //
.TXPHINIT (GT_TXPHINIT), //
.TXPHOVRDEN (1'd0), //
.TXDLYBYPASS (GT_TXDLYBYPASS), //
.TXDLYSRESET (GT_TXDLYSRESET), //
.TXDLYEN (GT_TXDLYEN), //
.TXDLYOVRDEN (1'd0), //
.TXDLYHOLD (1'd0), //
.TXDLYUPDOWN (1'd0), //
.TXPHALIGNDONE (GT_TXPHALIGNDONE), //
.TXPHINITDONE (GT_TXPHINITDONE), //
.TXDLYSRESETDONE (GT_TXDLYSRESETDONE), //
//---------- RX Sync ---------------------------------------------------
.RXPHDLYRESET (1'd0), //
.RXPHALIGN (GT_RXPHALIGN), //
.RXPHALIGNEN (GT_RXPHALIGNEN), //
.RXPHDLYPD (1'd0), //
.RXPHOVRDEN (1'd0), //
.RXDLYBYPASS (GT_RXDLYBYPASS), //
.RXDLYSRESET (GT_RXDLYSRESET), //
.RXDLYEN (GT_RXDLYEN), //
.RXDLYOVRDEN (1'd0), //
.RXDDIEN (GT_RXDDIEN), //
.RXPHALIGNDONE (GT_RXPHALIGNDONE), //
.RXPHMONITOR (), //
.RXPHSLIPMONITOR (), //
.RXDLYSRESETDONE (GT_RXDLYSRESETDONE), //
//---------- Comma Alignment -------------------------------------------
.RXCOMMADETEN ( 1'd1), //
.RXMCOMMAALIGNEN (!GT_GEN3), // 0 = disable comma alignment in Gen3
.RXPCOMMAALIGNEN (!GT_GEN3), // 0 = disable comma alignment in Gen3
.RXSLIDE ( GT_RXSLIDE), //
.RXCOMMADET (GT_RXCOMMADET), //
.RXCHARISCOMMA (rxchariscomma), //
.RXBYTEISALIGNED (GT_RXBYTEISALIGNED), //
.RXBYTEREALIGN (GT_RXBYTEREALIGN), //
//---------- Channel Bonding -------------------------------------------
.RXCHBONDEN (GT_RXCHBONDEN), //
.RXCHBONDI (GT_RXCHBONDI), //
.RXCHBONDLEVEL (GT_RXCHBONDLEVEL), //
.RXCHBONDMASTER (GT_RXCHBONDMASTER), //
.RXCHBONDSLAVE (GT_RXCHBONDSLAVE), //
.RXCHANBONDSEQ (), //
.RXCHANISALIGNED (GT_RXCHANISALIGNED), //
.RXCHANREALIGN (), //
.RXCHBONDO (GT_RXCHBONDO), //
//---------- Clock Correction -----------------------------------------
.RXCLKCORCNT (), //
//---------- 8b10b -----------------------------------------------------
.TX8B10BBYPASS (8'd0), //
.TX8B10BEN (!GT_GEN3), // 0 = disable TX 8b10b in Gen3
.RX8B10BEN (!GT_GEN3), // 0 = disable RX 8b10b in Gen3
.RXDISPERR (), //
.RXNOTINTABLE (), //
//---------- 64b/66b & 64b/67b -----------------------------------------
.TXHEADER (3'd0), //
.TXSEQUENCE (7'd0), //
.TXSTARTSEQ (1'd0), //
.RXGEARBOXSLIP (1'd0), //
.TXGEARBOXREADY (), //
.RXDATAVALID (), //
.RXHEADER (), //
.RXHEADERVALID (), //
.RXSTARTOFSEQ (), //
//---------- PRBS/Loopback ---------------------------------------------
.TXPRBSSEL (GT_TXPRBSSEL), //
.RXPRBSSEL (GT_RXPRBSSEL), //
.TXPRBSFORCEERR (GT_TXPRBSFORCEERR), //
.RXPRBSCNTRESET (GT_RXPRBSCNTRESET), //
.LOOPBACK (GT_LOOPBACK), //
.RXPRBSERR (GT_RXPRBSERR), //
//---------- OOB -------------------------------------------------------
.TXCOMINIT (1'd0), //
.TXCOMSAS (1'd0), //
.TXCOMWAKE (1'd0), //
.RXOOBRESET (1'd0), //
.TXCOMFINISH (), //
.RXCOMINITDET (), //
.RXCOMSASDET (), //
.RXCOMWAKEDET (), //
//---------- MISC ------------------------------------------------------
.SETERRSTATUS ( 1'd0), //
.TXDIFFPD ( 1'd0), //
.TXPISOPD ( 1'd0), //
.TSTIN (20'hFFFFF), //
.TSTOUT () // GTX
);
//---------- Default -------------------------------------------------------
assign dmonitorout[14:8] = 7'd0; // GTH GTP
assign GT_TXSYNCOUT = 1'd0; // GTH GTP
assign GT_TXSYNCDONE = 1'd0; // GTH GTP
assign GT_RXSYNCOUT = 1'd0; // GTH GTP
assign GT_RXSYNCDONE = 1'd0; // GTH GTP
assign GT_RXPMARESETDONE = 1'd0; // GTH GTP
end
endgenerate
//---------- GT Wrapper Outputs ------------------------------------------------
assign GT_RXDATA = rxdata [31:0];
assign GT_RXDATAK = rxdatak[ 3:0];
assign GT_RXCHARISCOMMA = rxchariscomma[ 3:0];
assign GT_DMONITOROUT = dmonitorout;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A41OI_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__A41OI_PP_BLACKBOX_V
/**
* a41oi: 4-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3 & A4) | B1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__a41oi (
Y ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__A41OI_PP_BLACKBOX_V
|
// **********************************************************************
// $Header: /var/lib/cvs/dncvs/FPGA/dini/fifo/fifo_async_sel.v,v 1.12 2014/09/02 21:51:45 neal Exp $
// **********************************************************************
// $Log: fifo_async_sel.v,v $
// Revision 1.12 2014/09/02 21:51:45 neal
// Added an option to allow selectram FIFOs have quicker data output when empty.
//
// Revision 1.11 2014/05/19 16:57:00 neal
// Added a parameter to remove some safety logic to increase the clock rate.
//
// Revision 1.10 2014/05/07 22:16:55 neal
// Added a couple of parameters to generate X's in simulation.
//
// Revision 1.9 2013/01/23 21:22:29 claudiug
// removed timescale declaration from all fifo_ files
//
// Revision 1.8 2012/07/18 02:50:40 bpoladian
// Added separate generate blocks for async and sync selram to make constraints easier to write.
//
// Revision 1.7 2011/12/05 22:16:05 neal
// Fixed toe_interrupt.
// Reduced toe ram utilization.
// Allowed digitfinder to have some constant input ports (selectable by parameter).
// Changed some brams to be single bram with byte write enables.
// Allowed some FIFO ports to not be generated (xst warnings).
//
// Revision 1.6 2011/10/06 01:49:42 bpoladian
// Disable verilator tracing.
//
// Revision 1.5 2010/11/16 03:12:16 bpoladian
// Added read enable port for blockram.
//
// Revision 1.4 2010/05/17 23:34:55 bpoladian
// Updated include paths.
//
// Revision 1.3 2008/04/11 01:38:02 bpoladian
// Ran dos2unix. Removed comments on `else and `endif lines.
//
// Revision 1.2 2008/04/01 23:27:48 bpoladian
// Updated include paths to reflect change in directory structure.
//
// Revision 1.1 2007/08/01 22:19:42 jperry
// initial, copied from another place in cvs.
//
// Revision 1.4 2007/03/06 16:03:59 neal
// Made the fifo able to be synchronous to 1 clock domain to make it smaller and faster.
//
// Revision 1.3 2007/02/08 18:17:20 neal
// Made the files get through Silos compilation.
//
// Revision 1.2 2007/02/05 17:23:46 jperry
// changed module name to match file name.
//
// Revision 1.1 2007/02/05 17:11:30 jperry
// initial async FIFO files. Copied, modified from dn_fpgacode/FIFO. This may be cleaned up later.
//
// **********************************************************************
/*verilator tracing_off*/
`ifdef INCL_FIFO_ASYNC_SEL
`else
`define INCL_FIFO_ASYNC_SEL
`include "dini/fifo/fifo_addr.v"
`include "dini/fifo/infer_selectram.v"
module fifo_async_sel (
reset,
wr_clk,
wr_en,
wr_din,
wr_full,
wr_almostfull,
wr_full_count,
rd_clk,
rd_en,
rd_dout,
rd_empty,
rd_empty_count
);
// removed CNTR_W, because counters will be 1 bit more than addresses
parameter ADDR_W = 5; // number of bits wide for address, depth of the fifo is pow(2,ADDR_W)
parameter DATA_W = 32; // number of bits wide for data
parameter ALMOSTFULL_LIMIT = 4; // number of entries left before almost full goes active
parameter ONECLOCK = 0; // set to 1 to get rid of resync logic.
parameter GEN_RDCOUNT = 1;
parameter GEN_WRCOUNT = 1;
parameter GEN_WRALMOSTFULL = 1;
parameter SIM_EMPTY_X = 0; // simulate with 'bx for read data path when empty
parameter SIM_NOTRD_X = 0; // simulate with 'bx for read data path when not reading
parameter IGNORE_FULL_WR = 0; // set to 1 to allow WR to go through when FULL is asserted (breaks the FIFO, but allows much higher clock rates). WARNING: setting this parameter can make the FIFO misbehave
parameter IGNORE_EMPTY_RD = 0; // set to 1 to allow RD to go through when EMPTY is asserted (breaks the FIFO, but allows much higher clock rates). WARNING: setting this parameter can make the FIFO misbehave
parameter FAST_WR_TO_RD = 0; // set to 1 to allow RD the following clk after WR
input reset;
input wr_clk;
input wr_en;
input [DATA_W-1:0] wr_din;
output wr_full;
output wr_almostfull;
output [ADDR_W:0] wr_full_count;
input rd_clk;
input rd_en;
output [DATA_W-1:0] rd_dout;
output rd_empty;
output [ADDR_W:0] rd_empty_count;
wire wr_en_ram;
/**********************************************************************\
* *
* Address selection *
* *
\**********************************************************************/
wire [ADDR_W-1:0] rd_addr, wr_addr;
/**********************************************************************\
* *
* Instantiation of the address registers *
* *
\**********************************************************************/
fifo_addr i_fifo_addr
(
.wr_clk ( wr_clk ),
.wr_en ( wr_en ),
.wr_addr ( wr_addr ),
.wr_en_ram ( wr_en_ram ),
.wr_full ( wr_full ),
.wr_almost_full ( wr_almostfull ),
.wr_full_count ( wr_full_count ),
.rd_clk ( rd_clk ),
.rd_en ( rd_en ),
.rd_addr ( rd_addr ),
.rd_en_ram ( ), // selectram always outputs
.rd_empty ( rd_empty ),
.rd_empty_count(rd_empty_count),
//// Do we want separate resets for read/write clock domains?
.fifo_reset ( reset )
);
defparam i_fifo_addr.ADDR_W = ADDR_W;
defparam i_fifo_addr.ALMOSTFULL_LIMIT = ALMOSTFULL_LIMIT;
defparam i_fifo_addr.DELAY_READ = 0;
defparam i_fifo_addr.ONECLOCK = ONECLOCK;
defparam i_fifo_addr.GEN_RDCOUNT = GEN_RDCOUNT;
defparam i_fifo_addr.GEN_WRCOUNT = GEN_WRCOUNT;
defparam i_fifo_addr.GEN_WRALMOSTFULL = GEN_WRALMOSTFULL;
defparam i_fifo_addr.IGNORE_FULL_WR = IGNORE_FULL_WR;
defparam i_fifo_addr.IGNORE_EMPTY_RD = IGNORE_EMPTY_RD;
defparam i_fifo_addr.FAST_WR_TO_RD = FAST_WR_TO_RD;
/**********************************************************************\
* *
* Select RAM instantiation for FIFO. One address location per queue *
* is sacrificed from each channel for the overall speed of the *
* design. *
* *
\**********************************************************************/
// These two generate blocks are meant to use the same code but name the path differently
// so that the async FIFOs can be constrained easily
generate
if(ONECLOCK) begin : gen_sync
infer_selectram i_fifo_selram
(
.clk(wr_clk),
.we(wr_en_ram),
.d(wr_din[DATA_W-1:0]),
.waddr(wr_addr[ADDR_W-1:0]),
.o(rd_dout[DATA_W-1:0]),
.raddr(rd_addr[ADDR_W-1:0])
);
defparam i_fifo_selram.d_width = DATA_W;
defparam i_fifo_selram.addr_width = ADDR_W;
end else begin : gen_async
infer_selectram i_fifo_selram
(
.clk(wr_clk),
.we(wr_en_ram),
.d(wr_din[DATA_W-1:0]),
.waddr(wr_addr[ADDR_W-1:0]),
.o(rd_dout[DATA_W-1:0]),
.raddr(rd_addr[ADDR_W-1:0])
);
defparam i_fifo_selram.d_width = DATA_W;
defparam i_fifo_selram.addr_width = ADDR_W;
end
endgenerate
// synthesis translate_off
assign rd_dout = (SIM_EMPTY_X & rd_empty ? {DATA_W{1'bx}} : {DATA_W{1'bz}} ); // Drive 'x' on read data bus when empty in simulation.
assign rd_dout = (SIM_NOTRD_X & (~rd_en) ? {DATA_W{1'bx}} : {DATA_W{1'bz}} ); // Drive 'x' on read data bus when empty in simulation.
// synthesis translate_on
endmodule // fifo_async_sel
`endif
/*verilator tracing_on*/
|
module udi_udi_inst_pow (
input gclk ,
input gscanenable ,
input [31:0] in_rs ,
input [15:0] in_rt ,
output [31:0] out_rd ,
input udi_ctl_thr_wr ,
input [1:0] udi_ctl_sum_mode ,
input udi_ctl_res_sel
);
wire [31:0] mult_i_out ;
wire [31:0] mult_q_out ;
wire [31:0] mult_i_out_d ;
wire [31:0] mult_q_out_d ;
wire [31:0] threshold ;
wire [32:0] sum ;
wire [31:0] sum_out ;
wire [31:0] sum_out_d ;
wire comp_res ;
localparam CTL_SUM_MODE_NONE = 2'b00 ;
localparam CTL_SUM_MODE_SUM = 2'b01 ;
localparam CTL_SUM_MODE_SUMSHIFT = 2'b10 ;
localparam CTL_SUM_MODE_BYPASS = 2'b11 ;
assign sum = mult_i_out_d + mult_q_out_d ;
assign comp_res = (sum_out_d > threshold) ? 1'b1 : 1'b0 ;
assign out_rd = (udi_ctl_res_sel) ? {30'd0,comp_res} : sum_out_d ;
assign sum_out = (udi_ctl_sum_mode == CTL_SUM_MODE_SUM) ? sum[31:0] :
(udi_ctl_sum_mode == CTL_SUM_MODE_SUMSHIFT) ? sum[32:1] :
(udi_ctl_sum_mode == CTL_SUM_MODE_BYPASS) ? mult_i_out : 32'd0 ;
mvp_cregister_wide #(32) _udi_thr_31_0_(threshold, gscanenable, udi_ctl_thr_wr, gclk, in_rs);
mvp_register #(32) _udi_mul_1_31_0_(mult_i_out_d, gclk, mult_i_out);
mvp_register #(32) _udi_mul_2_31_0_(mult_q_out_d, gclk, mult_q_out);
mvp_register #(32) _udi_sum_out_31_0_(sum_out_d, gclk, sum_out);
mult_16_x_16_res_32 mult_16_x_16_res_32_u1(
.clk ( gclk ), //: IN STD_LOGIC;
.a ( in_rs[31:16] ), //: IN STD_LOGIC_VECTOR(15 DOWNTO 0);
.b ( in_rs[31:16] ), //: IN STD_LOGIC_VECTOR(15 DOWNTO 0);
.p ( mult_i_out ) //: OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
mult_16_x_16_res_32 mult_16_x_16_res_32_u2(
.clk ( gclk ), //: IN STD_LOGIC;
.a ( in_rt ), //: IN STD_LOGIC_VECTOR(15 DOWNTO 0);
.b ( in_rt ), //: IN STD_LOGIC_VECTOR(15 DOWNTO 0);
.p ( mult_q_out ) //: OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NOR2_TB_V
`define SKY130_FD_SC_HD__NOR2_TB_V
/**
* nor2: 2-input NOR.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__nor2.v"
module top();
// Inputs are registered
reg A;
reg B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A = 1'b1;
#160 B = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A = 1'b0;
#280 B = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 B = 1'b1;
#480 A = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 B = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_hd__nor2 dut (.A(A), .B(B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__NOR2_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O31AI_4_V
`define SKY130_FD_SC_MS__O31AI_4_V
/**
* o31ai: 3-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & B1)
*
* Verilog wrapper for o31ai with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__o31ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o31ai_4 (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__o31ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o31ai_4 (
Y ,
A1,
A2,
A3,
B1
);
output Y ;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__o31ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__O31AI_4_V
|
//# 35 inputs
//# 320 outputs
//# 1728 D-type flipflops
//# 3861 inverters
//# 12204 gates (4032 ANDs + 7020 NANDs + 1152 ORs + 0 NORs)
module dff (CK,Q,D);
input CK,D;
output Q;
wire NM,NCK;
trireg NQ,M;
nmos N7 (M,D,NCK);
not P3 (NM,M);
nmos N9 (NQ,NM,CK);
not P5 (Q,NQ);
not P1 (NCK,CK);
endmodule
module s35932(GND,VDD,CK,CRC_OUT_1_0,CRC_OUT_1_1,CRC_OUT_1_10,CRC_OUT_1_11,
CRC_OUT_1_12,CRC_OUT_1_13,CRC_OUT_1_14,CRC_OUT_1_15,CRC_OUT_1_16,CRC_OUT_1_17,
CRC_OUT_1_18,CRC_OUT_1_19,CRC_OUT_1_2,CRC_OUT_1_20,CRC_OUT_1_21,CRC_OUT_1_22,
CRC_OUT_1_23,CRC_OUT_1_24,CRC_OUT_1_25,CRC_OUT_1_26,CRC_OUT_1_27,
CRC_OUT_1_28,CRC_OUT_1_29,CRC_OUT_1_3,CRC_OUT_1_30,CRC_OUT_1_31,CRC_OUT_1_4,
CRC_OUT_1_5,CRC_OUT_1_6,CRC_OUT_1_7,CRC_OUT_1_8,CRC_OUT_1_9,CRC_OUT_2_0,
CRC_OUT_2_1,CRC_OUT_2_10,CRC_OUT_2_11,CRC_OUT_2_12,CRC_OUT_2_13,CRC_OUT_2_14,
CRC_OUT_2_15,CRC_OUT_2_16,CRC_OUT_2_17,CRC_OUT_2_18,CRC_OUT_2_19,CRC_OUT_2_2,
CRC_OUT_2_20,CRC_OUT_2_21,CRC_OUT_2_22,CRC_OUT_2_23,CRC_OUT_2_24,
CRC_OUT_2_25,CRC_OUT_2_26,CRC_OUT_2_27,CRC_OUT_2_28,CRC_OUT_2_29,CRC_OUT_2_3,
CRC_OUT_2_30,CRC_OUT_2_31,CRC_OUT_2_4,CRC_OUT_2_5,CRC_OUT_2_6,CRC_OUT_2_7,
CRC_OUT_2_8,CRC_OUT_2_9,CRC_OUT_3_0,CRC_OUT_3_1,CRC_OUT_3_10,CRC_OUT_3_11,
CRC_OUT_3_12,CRC_OUT_3_13,CRC_OUT_3_14,CRC_OUT_3_15,CRC_OUT_3_16,
CRC_OUT_3_17,CRC_OUT_3_18,CRC_OUT_3_19,CRC_OUT_3_2,CRC_OUT_3_20,CRC_OUT_3_21,
CRC_OUT_3_22,CRC_OUT_3_23,CRC_OUT_3_24,CRC_OUT_3_25,CRC_OUT_3_26,
CRC_OUT_3_27,CRC_OUT_3_28,CRC_OUT_3_29,CRC_OUT_3_3,CRC_OUT_3_30,CRC_OUT_3_31,
CRC_OUT_3_4,CRC_OUT_3_5,CRC_OUT_3_6,CRC_OUT_3_7,CRC_OUT_3_8,CRC_OUT_3_9,
CRC_OUT_4_0,CRC_OUT_4_1,CRC_OUT_4_10,CRC_OUT_4_11,CRC_OUT_4_12,CRC_OUT_4_13,
CRC_OUT_4_14,CRC_OUT_4_15,CRC_OUT_4_16,CRC_OUT_4_17,CRC_OUT_4_18,
CRC_OUT_4_19,CRC_OUT_4_2,CRC_OUT_4_20,CRC_OUT_4_21,CRC_OUT_4_22,CRC_OUT_4_23,
CRC_OUT_4_24,CRC_OUT_4_25,CRC_OUT_4_26,CRC_OUT_4_27,CRC_OUT_4_28,
CRC_OUT_4_29,CRC_OUT_4_3,CRC_OUT_4_30,CRC_OUT_4_31,CRC_OUT_4_4,CRC_OUT_4_5,
CRC_OUT_4_6,CRC_OUT_4_7,CRC_OUT_4_8,CRC_OUT_4_9,CRC_OUT_5_0,CRC_OUT_5_1,
CRC_OUT_5_10,CRC_OUT_5_11,CRC_OUT_5_12,CRC_OUT_5_13,CRC_OUT_5_14,
CRC_OUT_5_15,CRC_OUT_5_16,CRC_OUT_5_17,CRC_OUT_5_18,CRC_OUT_5_19,CRC_OUT_5_2,
CRC_OUT_5_20,CRC_OUT_5_21,CRC_OUT_5_22,CRC_OUT_5_23,CRC_OUT_5_24,
CRC_OUT_5_25,CRC_OUT_5_26,CRC_OUT_5_27,CRC_OUT_5_28,CRC_OUT_5_29,CRC_OUT_5_3,
CRC_OUT_5_30,CRC_OUT_5_31,CRC_OUT_5_4,CRC_OUT_5_5,CRC_OUT_5_6,CRC_OUT_5_7,
CRC_OUT_5_8,CRC_OUT_5_9,CRC_OUT_6_0,CRC_OUT_6_1,CRC_OUT_6_10,CRC_OUT_6_11,
CRC_OUT_6_12,CRC_OUT_6_13,CRC_OUT_6_14,CRC_OUT_6_15,CRC_OUT_6_16,
CRC_OUT_6_17,CRC_OUT_6_18,CRC_OUT_6_19,CRC_OUT_6_2,CRC_OUT_6_20,CRC_OUT_6_21,
CRC_OUT_6_22,CRC_OUT_6_23,CRC_OUT_6_24,CRC_OUT_6_25,CRC_OUT_6_26,
CRC_OUT_6_27,CRC_OUT_6_28,CRC_OUT_6_29,CRC_OUT_6_3,CRC_OUT_6_30,CRC_OUT_6_31,
CRC_OUT_6_4,CRC_OUT_6_5,CRC_OUT_6_6,CRC_OUT_6_7,CRC_OUT_6_8,CRC_OUT_6_9,
CRC_OUT_7_0,CRC_OUT_7_1,CRC_OUT_7_10,CRC_OUT_7_11,CRC_OUT_7_12,CRC_OUT_7_13,
CRC_OUT_7_14,CRC_OUT_7_15,CRC_OUT_7_16,CRC_OUT_7_17,CRC_OUT_7_18,
CRC_OUT_7_19,CRC_OUT_7_2,CRC_OUT_7_20,CRC_OUT_7_21,CRC_OUT_7_22,CRC_OUT_7_23,
CRC_OUT_7_24,CRC_OUT_7_25,CRC_OUT_7_26,CRC_OUT_7_27,CRC_OUT_7_28,
CRC_OUT_7_29,CRC_OUT_7_3,CRC_OUT_7_30,CRC_OUT_7_31,CRC_OUT_7_4,CRC_OUT_7_5,
CRC_OUT_7_6,CRC_OUT_7_7,CRC_OUT_7_8,CRC_OUT_7_9,CRC_OUT_8_0,CRC_OUT_8_1,
CRC_OUT_8_10,CRC_OUT_8_11,CRC_OUT_8_12,CRC_OUT_8_13,CRC_OUT_8_14,
CRC_OUT_8_15,CRC_OUT_8_16,CRC_OUT_8_17,CRC_OUT_8_18,CRC_OUT_8_19,CRC_OUT_8_2,
CRC_OUT_8_20,CRC_OUT_8_21,CRC_OUT_8_22,CRC_OUT_8_23,CRC_OUT_8_24,
CRC_OUT_8_25,CRC_OUT_8_26,CRC_OUT_8_27,CRC_OUT_8_28,CRC_OUT_8_29,CRC_OUT_8_3,
CRC_OUT_8_30,CRC_OUT_8_31,CRC_OUT_8_4,CRC_OUT_8_5,CRC_OUT_8_6,CRC_OUT_8_7,
CRC_OUT_8_8,CRC_OUT_8_9,CRC_OUT_9_0,CRC_OUT_9_1,CRC_OUT_9_10,CRC_OUT_9_11,
CRC_OUT_9_12,CRC_OUT_9_13,CRC_OUT_9_14,CRC_OUT_9_15,CRC_OUT_9_16,
CRC_OUT_9_17,CRC_OUT_9_18,CRC_OUT_9_19,CRC_OUT_9_2,CRC_OUT_9_20,CRC_OUT_9_21,
CRC_OUT_9_22,CRC_OUT_9_23,CRC_OUT_9_24,CRC_OUT_9_25,CRC_OUT_9_26,
CRC_OUT_9_27,CRC_OUT_9_28,CRC_OUT_9_29,CRC_OUT_9_3,CRC_OUT_9_30,CRC_OUT_9_31,
CRC_OUT_9_4,CRC_OUT_9_5,CRC_OUT_9_6,CRC_OUT_9_7,CRC_OUT_9_8,CRC_OUT_9_9,
DATA_0_0,DATA_0_1,DATA_0_10,DATA_0_11,DATA_0_12,DATA_0_13,DATA_0_14,
DATA_0_15,DATA_0_16,DATA_0_17,DATA_0_18,DATA_0_19,DATA_0_2,DATA_0_20,
DATA_0_21,DATA_0_22,DATA_0_23,DATA_0_24,DATA_0_25,DATA_0_26,DATA_0_27,
DATA_0_28,DATA_0_29,DATA_0_3,DATA_0_30,DATA_0_31,DATA_0_4,DATA_0_5,DATA_0_6,
DATA_0_7,DATA_0_8,DATA_0_9,DATA_9_0,DATA_9_1,DATA_9_10,DATA_9_11,DATA_9_12,
DATA_9_13,DATA_9_14,DATA_9_15,DATA_9_16,DATA_9_17,DATA_9_18,DATA_9_19,
DATA_9_2,DATA_9_20,DATA_9_21,DATA_9_22,DATA_9_23,DATA_9_24,DATA_9_25,
DATA_9_26,DATA_9_27,DATA_9_28,DATA_9_29,DATA_9_3,DATA_9_30,DATA_9_31,
DATA_9_4,DATA_9_5,DATA_9_6,DATA_9_7,DATA_9_8,DATA_9_9,RESET,TM0,TM1);
input GND,VDD,CK,DATA_0_31,DATA_0_30,DATA_0_29,DATA_0_28,DATA_0_27,DATA_0_26,
DATA_0_25,
DATA_0_24,DATA_0_23,DATA_0_22,DATA_0_21,DATA_0_20,DATA_0_19,DATA_0_18,
DATA_0_17,DATA_0_16,DATA_0_15,DATA_0_14,DATA_0_13,DATA_0_12,DATA_0_11,
DATA_0_10,DATA_0_9,DATA_0_8,DATA_0_7,DATA_0_6,DATA_0_5,DATA_0_4,DATA_0_3,
DATA_0_2,DATA_0_1,DATA_0_0,RESET,TM1,TM0;
output DATA_9_31,DATA_9_30,DATA_9_29,DATA_9_28,DATA_9_27,DATA_9_26,DATA_9_25,
DATA_9_24,DATA_9_23,DATA_9_22,DATA_9_21,DATA_9_20,DATA_9_19,DATA_9_18,
DATA_9_17,DATA_9_16,DATA_9_15,DATA_9_14,DATA_9_13,DATA_9_12,DATA_9_11,
DATA_9_10,DATA_9_9,DATA_9_8,DATA_9_7,DATA_9_6,DATA_9_5,DATA_9_4,DATA_9_3,
DATA_9_2,DATA_9_1,DATA_9_0,CRC_OUT_9_0,CRC_OUT_9_1,CRC_OUT_9_2,CRC_OUT_9_3,
CRC_OUT_9_4,CRC_OUT_9_5,CRC_OUT_9_6,CRC_OUT_9_7,CRC_OUT_9_8,CRC_OUT_9_9,
CRC_OUT_9_10,CRC_OUT_9_11,CRC_OUT_9_12,CRC_OUT_9_13,CRC_OUT_9_14,
CRC_OUT_9_15,CRC_OUT_9_16,CRC_OUT_9_17,CRC_OUT_9_18,CRC_OUT_9_19,
CRC_OUT_9_20,CRC_OUT_9_21,CRC_OUT_9_22,CRC_OUT_9_23,CRC_OUT_9_24,
CRC_OUT_9_25,CRC_OUT_9_26,CRC_OUT_9_27,CRC_OUT_9_28,CRC_OUT_9_29,
CRC_OUT_9_30,CRC_OUT_9_31,CRC_OUT_8_0,CRC_OUT_8_1,CRC_OUT_8_2,CRC_OUT_8_3,
CRC_OUT_8_4,CRC_OUT_8_5,CRC_OUT_8_6,CRC_OUT_8_7,CRC_OUT_8_8,CRC_OUT_8_9,
CRC_OUT_8_10,CRC_OUT_8_11,CRC_OUT_8_12,CRC_OUT_8_13,CRC_OUT_8_14,
CRC_OUT_8_15,CRC_OUT_8_16,CRC_OUT_8_17,CRC_OUT_8_18,CRC_OUT_8_19,
CRC_OUT_8_20,CRC_OUT_8_21,CRC_OUT_8_22,CRC_OUT_8_23,CRC_OUT_8_24,
CRC_OUT_8_25,CRC_OUT_8_26,CRC_OUT_8_27,CRC_OUT_8_28,CRC_OUT_8_29,
CRC_OUT_8_30,CRC_OUT_8_31,CRC_OUT_7_0,CRC_OUT_7_1,CRC_OUT_7_2,CRC_OUT_7_3,
CRC_OUT_7_4,CRC_OUT_7_5,CRC_OUT_7_6,CRC_OUT_7_7,CRC_OUT_7_8,CRC_OUT_7_9,
CRC_OUT_7_10,CRC_OUT_7_11,CRC_OUT_7_12,CRC_OUT_7_13,CRC_OUT_7_14,
CRC_OUT_7_15,CRC_OUT_7_16,CRC_OUT_7_17,CRC_OUT_7_18,CRC_OUT_7_19,
CRC_OUT_7_20,CRC_OUT_7_21,CRC_OUT_7_22,CRC_OUT_7_23,CRC_OUT_7_24,
CRC_OUT_7_25,CRC_OUT_7_26,CRC_OUT_7_27,CRC_OUT_7_28,CRC_OUT_7_29,
CRC_OUT_7_30,CRC_OUT_7_31,CRC_OUT_6_0,CRC_OUT_6_1,CRC_OUT_6_2,CRC_OUT_6_3,
CRC_OUT_6_4,CRC_OUT_6_5,CRC_OUT_6_6,CRC_OUT_6_7,CRC_OUT_6_8,CRC_OUT_6_9,
CRC_OUT_6_10,CRC_OUT_6_11,CRC_OUT_6_12,CRC_OUT_6_13,CRC_OUT_6_14,
CRC_OUT_6_15,CRC_OUT_6_16,CRC_OUT_6_17,CRC_OUT_6_18,CRC_OUT_6_19,
CRC_OUT_6_20,CRC_OUT_6_21,CRC_OUT_6_22,CRC_OUT_6_23,CRC_OUT_6_24,
CRC_OUT_6_25,CRC_OUT_6_26,CRC_OUT_6_27,CRC_OUT_6_28,CRC_OUT_6_29,
CRC_OUT_6_30,CRC_OUT_6_31,CRC_OUT_5_0,CRC_OUT_5_1,CRC_OUT_5_2,CRC_OUT_5_3,
CRC_OUT_5_4,CRC_OUT_5_5,CRC_OUT_5_6,CRC_OUT_5_7,CRC_OUT_5_8,CRC_OUT_5_9,
CRC_OUT_5_10,CRC_OUT_5_11,CRC_OUT_5_12,CRC_OUT_5_13,CRC_OUT_5_14,
CRC_OUT_5_15,CRC_OUT_5_16,CRC_OUT_5_17,CRC_OUT_5_18,CRC_OUT_5_19,
CRC_OUT_5_20,CRC_OUT_5_21,CRC_OUT_5_22,CRC_OUT_5_23,CRC_OUT_5_24,
CRC_OUT_5_25,CRC_OUT_5_26,CRC_OUT_5_27,CRC_OUT_5_28,CRC_OUT_5_29,
CRC_OUT_5_30,CRC_OUT_5_31,CRC_OUT_4_0,CRC_OUT_4_1,CRC_OUT_4_2,CRC_OUT_4_3,
CRC_OUT_4_4,CRC_OUT_4_5,CRC_OUT_4_6,CRC_OUT_4_7,CRC_OUT_4_8,CRC_OUT_4_9,
CRC_OUT_4_10,CRC_OUT_4_11,CRC_OUT_4_12,CRC_OUT_4_13,CRC_OUT_4_14,
CRC_OUT_4_15,CRC_OUT_4_16,CRC_OUT_4_17,CRC_OUT_4_18,CRC_OUT_4_19,
CRC_OUT_4_20,CRC_OUT_4_21,CRC_OUT_4_22,CRC_OUT_4_23,CRC_OUT_4_24,
CRC_OUT_4_25,CRC_OUT_4_26,CRC_OUT_4_27,CRC_OUT_4_28,CRC_OUT_4_29,
CRC_OUT_4_30,CRC_OUT_4_31,CRC_OUT_3_0,CRC_OUT_3_1,CRC_OUT_3_2,CRC_OUT_3_3,
CRC_OUT_3_4,CRC_OUT_3_5,CRC_OUT_3_6,CRC_OUT_3_7,CRC_OUT_3_8,CRC_OUT_3_9,
CRC_OUT_3_10,CRC_OUT_3_11,CRC_OUT_3_12,CRC_OUT_3_13,CRC_OUT_3_14,
CRC_OUT_3_15,CRC_OUT_3_16,CRC_OUT_3_17,CRC_OUT_3_18,CRC_OUT_3_19,
CRC_OUT_3_20,CRC_OUT_3_21,CRC_OUT_3_22,CRC_OUT_3_23,CRC_OUT_3_24,
CRC_OUT_3_25,CRC_OUT_3_26,CRC_OUT_3_27,CRC_OUT_3_28,CRC_OUT_3_29,
CRC_OUT_3_30,CRC_OUT_3_31,CRC_OUT_2_0,CRC_OUT_2_1,CRC_OUT_2_2,CRC_OUT_2_3,
CRC_OUT_2_4,CRC_OUT_2_5,CRC_OUT_2_6,CRC_OUT_2_7,CRC_OUT_2_8,CRC_OUT_2_9,
CRC_OUT_2_10,CRC_OUT_2_11,CRC_OUT_2_12,CRC_OUT_2_13,CRC_OUT_2_14,
CRC_OUT_2_15,CRC_OUT_2_16,CRC_OUT_2_17,CRC_OUT_2_18,CRC_OUT_2_19,
CRC_OUT_2_20,CRC_OUT_2_21,CRC_OUT_2_22,CRC_OUT_2_23,CRC_OUT_2_24,
CRC_OUT_2_25,CRC_OUT_2_26,CRC_OUT_2_27,CRC_OUT_2_28,CRC_OUT_2_29,
CRC_OUT_2_30,CRC_OUT_2_31,CRC_OUT_1_0,CRC_OUT_1_1,CRC_OUT_1_2,CRC_OUT_1_3,
CRC_OUT_1_4,CRC_OUT_1_5,CRC_OUT_1_6,CRC_OUT_1_7,CRC_OUT_1_8,CRC_OUT_1_9,
CRC_OUT_1_10,CRC_OUT_1_11,CRC_OUT_1_12,CRC_OUT_1_13,CRC_OUT_1_14,
CRC_OUT_1_15,CRC_OUT_1_16,CRC_OUT_1_17,CRC_OUT_1_18,CRC_OUT_1_19,
CRC_OUT_1_20,CRC_OUT_1_21,CRC_OUT_1_22,CRC_OUT_1_23,CRC_OUT_1_24,
CRC_OUT_1_25,CRC_OUT_1_26,CRC_OUT_1_27,CRC_OUT_1_28,CRC_OUT_1_29,
CRC_OUT_1_30,CRC_OUT_1_31;
wire WX485,WX484,WX487,WX486,WX489,WX488,WX491,WX490,WX493,WX492,WX495,WX494,
WX497,WX496,WX499,WX498,WX501,WX500,WX503,WX502,WX505,WX504,WX507,WX506,
WX509,WX508,WX511,WX510,WX513,WX512,WX515,WX514,WX517,WX516,WX519,WX518,
WX521,WX520,WX523,WX522,WX525,WX524,WX527,WX526,WX529,WX528,WX531,WX530,
WX533,WX532,WX535,WX534,WX537,WX536,WX539,WX538,WX541,WX540,WX543,WX542,
WX545,WX544,WX547,WX546,WX645,WX644,WX647,WX646,WX649,WX648,WX651,WX650,
WX653,WX652,WX655,WX654,WX657,WX656,WX659,WX658,WX661,WX660,WX663,WX662,
WX665,WX664,WX667,WX666,WX669,WX668,WX671,WX670,WX673,WX672,WX675,WX674,
WX677,WX676,WX679,WX678,WX681,WX680,WX683,WX682,WX685,WX684,WX687,WX686,
WX689,WX688,WX691,WX690,WX693,WX692,WX695,WX694,WX697,WX696,WX699,WX698,
WX701,WX700,WX703,WX702,WX705,WX704,WX707,WX706,WX709,WX708,WX711,WX710,
WX713,WX712,WX715,WX714,WX717,WX716,WX719,WX718,WX721,WX720,WX723,WX722,
WX725,WX724,WX727,WX726,WX729,WX728,WX731,WX730,WX733,WX732,WX735,WX734,
WX737,WX736,WX739,WX738,WX741,WX740,WX743,WX742,WX745,WX744,WX747,WX746,
WX749,WX748,WX751,WX750,WX753,WX752,WX755,WX754,WX757,WX756,WX759,WX758,
WX761,WX760,WX763,WX762,WX765,WX764,WX767,WX766,WX769,WX768,WX771,WX770,
WX773,WX772,WX775,WX774,WX777,WX776,WX779,WX778,WX781,WX780,WX783,WX782,
WX785,WX784,WX787,WX786,WX789,WX788,WX791,WX790,WX793,WX792,WX795,WX794,
WX797,WX796,WX799,WX798,WX801,WX800,WX803,WX802,WX805,WX804,WX807,WX806,
WX809,WX808,WX811,WX810,WX813,WX812,WX815,WX814,WX817,WX816,WX819,WX818,
WX821,WX820,WX823,WX822,WX825,WX824,WX827,WX826,WX829,WX828,WX831,WX830,
WX833,WX832,WX835,WX834,WX837,WX836,WX839,WX838,WX841,WX840,WX843,WX842,
WX845,WX844,WX847,WX846,WX849,WX848,WX851,WX850,WX853,WX852,WX855,WX854,
WX857,WX856,WX859,WX858,WX861,WX860,WX863,WX862,WX865,WX864,WX867,WX866,
WX869,WX868,WX871,WX870,WX873,WX872,WX875,WX874,WX877,WX876,WX879,WX878,
WX881,WX880,WX883,WX882,WX885,WX884,WX887,WX886,WX889,WX888,WX891,WX890,
WX893,WX892,WX895,WX894,WX897,WX896,WX899,WX898,WX1264,WX1266,WX1268,
WX1270,WX1272,WX1274,WX1276,WX1278,WX1280,WX1282,WX1284,WX1286,WX1288,
WX1290,WX1292,WX1294,WX1296,WX1298,WX1300,WX1302,WX1304,WX1306,WX1308,
WX1310,WX1312,WX1314,WX1316,WX1318,WX1320,WX1322,WX1324,WX1326,WX1778,
WX1777,WX1780,WX1779,WX1782,WX1781,WX1784,WX1783,WX1786,WX1785,WX1788,
WX1787,WX1790,WX1789,WX1792,WX1791,WX1794,WX1793,WX1796,WX1795,WX1798,
WX1797,WX1800,WX1799,WX1802,WX1801,WX1804,WX1803,WX1806,WX1805,WX1808,
WX1807,WX1810,WX1809,WX1812,WX1811,WX1814,WX1813,WX1816,WX1815,WX1818,
WX1817,WX1820,WX1819,WX1822,WX1821,WX1824,WX1823,WX1826,WX1825,WX1828,
WX1827,WX1830,WX1829,WX1832,WX1831,WX1834,WX1833,WX1836,WX1835,WX1838,
WX1837,WX1840,WX1839,WX1938,WX1937,WX1940,WX1939,WX1942,WX1941,WX1944,
WX1943,WX1946,WX1945,WX1948,WX1947,WX1950,WX1949,WX1952,WX1951,WX1954,
WX1953,WX1956,WX1955,WX1958,WX1957,WX1960,WX1959,WX1962,WX1961,WX1964,
WX1963,WX1966,WX1965,WX1968,WX1967,WX1970,WX1969,WX1972,WX1971,WX1974,
WX1973,WX1976,WX1975,WX1978,WX1977,WX1980,WX1979,WX1982,WX1981,WX1984,
WX1983,WX1986,WX1985,WX1988,WX1987,WX1990,WX1989,WX1992,WX1991,WX1994,
WX1993,WX1996,WX1995,WX1998,WX1997,WX2000,WX1999,WX2002,WX2001,WX2004,
WX2003,WX2006,WX2005,WX2008,WX2007,WX2010,WX2009,WX2012,WX2011,WX2014,
WX2013,WX2016,WX2015,WX2018,WX2017,WX2020,WX2019,WX2022,WX2021,WX2024,
WX2023,WX2026,WX2025,WX2028,WX2027,WX2030,WX2029,WX2032,WX2031,WX2034,
WX2033,WX2036,WX2035,WX2038,WX2037,WX2040,WX2039,WX2042,WX2041,WX2044,
WX2043,WX2046,WX2045,WX2048,WX2047,WX2050,WX2049,WX2052,WX2051,WX2054,
WX2053,WX2056,WX2055,WX2058,WX2057,WX2060,WX2059,WX2062,WX2061,WX2064,
WX2063,WX2066,WX2065,WX2068,WX2067,WX2070,WX2069,WX2072,WX2071,WX2074,
WX2073,WX2076,WX2075,WX2078,WX2077,WX2080,WX2079,WX2082,WX2081,WX2084,
WX2083,WX2086,WX2085,WX2088,WX2087,WX2090,WX2089,WX2092,WX2091,WX2094,
WX2093,WX2096,WX2095,WX2098,WX2097,WX2100,WX2099,WX2102,WX2101,WX2104,
WX2103,WX2106,WX2105,WX2108,WX2107,WX2110,WX2109,WX2112,WX2111,WX2114,
WX2113,WX2116,WX2115,WX2118,WX2117,WX2120,WX2119,WX2122,WX2121,WX2124,
WX2123,WX2126,WX2125,WX2128,WX2127,WX2130,WX2129,WX2132,WX2131,WX2134,
WX2133,WX2136,WX2135,WX2138,WX2137,WX2140,WX2139,WX2142,WX2141,WX2144,
WX2143,WX2146,WX2145,WX2148,WX2147,WX2150,WX2149,WX2152,WX2151,WX2154,
WX2153,WX2156,WX2155,WX2158,WX2157,WX2160,WX2159,WX2162,WX2161,WX2164,
WX2163,WX2166,WX2165,WX2168,WX2167,WX2170,WX2169,WX2172,WX2171,WX2174,
WX2173,WX2176,WX2175,WX2178,WX2177,WX2180,WX2179,WX2182,WX2181,WX2184,
WX2183,WX2186,WX2185,WX2188,WX2187,WX2190,WX2189,WX2192,WX2191,WX2557,
WX2559,WX2561,WX2563,WX2565,WX2567,WX2569,WX2571,WX2573,WX2575,WX2577,
WX2579,WX2581,WX2583,WX2585,WX2587,WX2589,WX2591,WX2593,WX2595,WX2597,
WX2599,WX2601,WX2603,WX2605,WX2607,WX2609,WX2611,WX2613,WX2615,WX2617,
WX2619,WX3071,WX3070,WX3073,WX3072,WX3075,WX3074,WX3077,WX3076,WX3079,
WX3078,WX3081,WX3080,WX3083,WX3082,WX3085,WX3084,WX3087,WX3086,WX3089,
WX3088,WX3091,WX3090,WX3093,WX3092,WX3095,WX3094,WX3097,WX3096,WX3099,
WX3098,WX3101,WX3100,WX3103,WX3102,WX3105,WX3104,WX3107,WX3106,WX3109,
WX3108,WX3111,WX3110,WX3113,WX3112,WX3115,WX3114,WX3117,WX3116,WX3119,
WX3118,WX3121,WX3120,WX3123,WX3122,WX3125,WX3124,WX3127,WX3126,WX3129,
WX3128,WX3131,WX3130,WX3133,WX3132,WX3231,WX3230,WX3233,WX3232,WX3235,
WX3234,WX3237,WX3236,WX3239,WX3238,WX3241,WX3240,WX3243,WX3242,WX3245,
WX3244,WX3247,WX3246,WX3249,WX3248,WX3251,WX3250,WX3253,WX3252,WX3255,
WX3254,WX3257,WX3256,WX3259,WX3258,WX3261,WX3260,WX3263,WX3262,WX3265,
WX3264,WX3267,WX3266,WX3269,WX3268,WX3271,WX3270,WX3273,WX3272,WX3275,
WX3274,WX3277,WX3276,WX3279,WX3278,WX3281,WX3280,WX3283,WX3282,WX3285,
WX3284,WX3287,WX3286,WX3289,WX3288,WX3291,WX3290,WX3293,WX3292,WX3295,
WX3294,WX3297,WX3296,WX3299,WX3298,WX3301,WX3300,WX3303,WX3302,WX3305,
WX3304,WX3307,WX3306,WX3309,WX3308,WX3311,WX3310,WX3313,WX3312,WX3315,
WX3314,WX3317,WX3316,WX3319,WX3318,WX3321,WX3320,WX3323,WX3322,WX3325,
WX3324,WX3327,WX3326,WX3329,WX3328,WX3331,WX3330,WX3333,WX3332,WX3335,
WX3334,WX3337,WX3336,WX3339,WX3338,WX3341,WX3340,WX3343,WX3342,WX3345,
WX3344,WX3347,WX3346,WX3349,WX3348,WX3351,WX3350,WX3353,WX3352,WX3355,
WX3354,WX3357,WX3356,WX3359,WX3358,WX3361,WX3360,WX3363,WX3362,WX3365,
WX3364,WX3367,WX3366,WX3369,WX3368,WX3371,WX3370,WX3373,WX3372,WX3375,
WX3374,WX3377,WX3376,WX3379,WX3378,WX3381,WX3380,WX3383,WX3382,WX3385,
WX3384,WX3387,WX3386,WX3389,WX3388,WX3391,WX3390,WX3393,WX3392,WX3395,
WX3394,WX3397,WX3396,WX3399,WX3398,WX3401,WX3400,WX3403,WX3402,WX3405,
WX3404,WX3407,WX3406,WX3409,WX3408,WX3411,WX3410,WX3413,WX3412,WX3415,
WX3414,WX3417,WX3416,WX3419,WX3418,WX3421,WX3420,WX3423,WX3422,WX3425,
WX3424,WX3427,WX3426,WX3429,WX3428,WX3431,WX3430,WX3433,WX3432,WX3435,
WX3434,WX3437,WX3436,WX3439,WX3438,WX3441,WX3440,WX3443,WX3442,WX3445,
WX3444,WX3447,WX3446,WX3449,WX3448,WX3451,WX3450,WX3453,WX3452,WX3455,
WX3454,WX3457,WX3456,WX3459,WX3458,WX3461,WX3460,WX3463,WX3462,WX3465,
WX3464,WX3467,WX3466,WX3469,WX3468,WX3471,WX3470,WX3473,WX3472,WX3475,
WX3474,WX3477,WX3476,WX3479,WX3478,WX3481,WX3480,WX3483,WX3482,WX3485,
WX3484,WX3850,WX3852,WX3854,WX3856,WX3858,WX3860,WX3862,WX3864,WX3866,
WX3868,WX3870,WX3872,WX3874,WX3876,WX3878,WX3880,WX3882,WX3884,WX3886,
WX3888,WX3890,WX3892,WX3894,WX3896,WX3898,WX3900,WX3902,WX3904,WX3906,
WX3908,WX3910,WX3912,WX4364,WX4363,WX4366,WX4365,WX4368,WX4367,WX4370,
WX4369,WX4372,WX4371,WX4374,WX4373,WX4376,WX4375,WX4378,WX4377,WX4380,
WX4379,WX4382,WX4381,WX4384,WX4383,WX4386,WX4385,WX4388,WX4387,WX4390,
WX4389,WX4392,WX4391,WX4394,WX4393,WX4396,WX4395,WX4398,WX4397,WX4400,
WX4399,WX4402,WX4401,WX4404,WX4403,WX4406,WX4405,WX4408,WX4407,WX4410,
WX4409,WX4412,WX4411,WX4414,WX4413,WX4416,WX4415,WX4418,WX4417,WX4420,
WX4419,WX4422,WX4421,WX4424,WX4423,WX4426,WX4425,WX4524,WX4523,WX4526,
WX4525,WX4528,WX4527,WX4530,WX4529,WX4532,WX4531,WX4534,WX4533,WX4536,
WX4535,WX4538,WX4537,WX4540,WX4539,WX4542,WX4541,WX4544,WX4543,WX4546,
WX4545,WX4548,WX4547,WX4550,WX4549,WX4552,WX4551,WX4554,WX4553,WX4556,
WX4555,WX4558,WX4557,WX4560,WX4559,WX4562,WX4561,WX4564,WX4563,WX4566,
WX4565,WX4568,WX4567,WX4570,WX4569,WX4572,WX4571,WX4574,WX4573,WX4576,
WX4575,WX4578,WX4577,WX4580,WX4579,WX4582,WX4581,WX4584,WX4583,WX4586,
WX4585,WX4588,WX4587,WX4590,WX4589,WX4592,WX4591,WX4594,WX4593,WX4596,
WX4595,WX4598,WX4597,WX4600,WX4599,WX4602,WX4601,WX4604,WX4603,WX4606,
WX4605,WX4608,WX4607,WX4610,WX4609,WX4612,WX4611,WX4614,WX4613,WX4616,
WX4615,WX4618,WX4617,WX4620,WX4619,WX4622,WX4621,WX4624,WX4623,WX4626,
WX4625,WX4628,WX4627,WX4630,WX4629,WX4632,WX4631,WX4634,WX4633,WX4636,
WX4635,WX4638,WX4637,WX4640,WX4639,WX4642,WX4641,WX4644,WX4643,WX4646,
WX4645,WX4648,WX4647,WX4650,WX4649,WX4652,WX4651,WX4654,WX4653,WX4656,
WX4655,WX4658,WX4657,WX4660,WX4659,WX4662,WX4661,WX4664,WX4663,WX4666,
WX4665,WX4668,WX4667,WX4670,WX4669,WX4672,WX4671,WX4674,WX4673,WX4676,
WX4675,WX4678,WX4677,WX4680,WX4679,WX4682,WX4681,WX4684,WX4683,WX4686,
WX4685,WX4688,WX4687,WX4690,WX4689,WX4692,WX4691,WX4694,WX4693,WX4696,
WX4695,WX4698,WX4697,WX4700,WX4699,WX4702,WX4701,WX4704,WX4703,WX4706,
WX4705,WX4708,WX4707,WX4710,WX4709,WX4712,WX4711,WX4714,WX4713,WX4716,
WX4715,WX4718,WX4717,WX4720,WX4719,WX4722,WX4721,WX4724,WX4723,WX4726,
WX4725,WX4728,WX4727,WX4730,WX4729,WX4732,WX4731,WX4734,WX4733,WX4736,
WX4735,WX4738,WX4737,WX4740,WX4739,WX4742,WX4741,WX4744,WX4743,WX4746,
WX4745,WX4748,WX4747,WX4750,WX4749,WX4752,WX4751,WX4754,WX4753,WX4756,
WX4755,WX4758,WX4757,WX4760,WX4759,WX4762,WX4761,WX4764,WX4763,WX4766,
WX4765,WX4768,WX4767,WX4770,WX4769,WX4772,WX4771,WX4774,WX4773,WX4776,
WX4775,WX4778,WX4777,WX5143,WX5145,WX5147,WX5149,WX5151,WX5153,WX5155,
WX5157,WX5159,WX5161,WX5163,WX5165,WX5167,WX5169,WX5171,WX5173,WX5175,
WX5177,WX5179,WX5181,WX5183,WX5185,WX5187,WX5189,WX5191,WX5193,WX5195,
WX5197,WX5199,WX5201,WX5203,WX5205,WX5657,WX5656,WX5659,WX5658,WX5661,
WX5660,WX5663,WX5662,WX5665,WX5664,WX5667,WX5666,WX5669,WX5668,WX5671,
WX5670,WX5673,WX5672,WX5675,WX5674,WX5677,WX5676,WX5679,WX5678,WX5681,
WX5680,WX5683,WX5682,WX5685,WX5684,WX5687,WX5686,WX5689,WX5688,WX5691,
WX5690,WX5693,WX5692,WX5695,WX5694,WX5697,WX5696,WX5699,WX5698,WX5701,
WX5700,WX5703,WX5702,WX5705,WX5704,WX5707,WX5706,WX5709,WX5708,WX5711,
WX5710,WX5713,WX5712,WX5715,WX5714,WX5717,WX5716,WX5719,WX5718,WX5817,
WX5816,WX5819,WX5818,WX5821,WX5820,WX5823,WX5822,WX5825,WX5824,WX5827,
WX5826,WX5829,WX5828,WX5831,WX5830,WX5833,WX5832,WX5835,WX5834,WX5837,
WX5836,WX5839,WX5838,WX5841,WX5840,WX5843,WX5842,WX5845,WX5844,WX5847,
WX5846,WX5849,WX5848,WX5851,WX5850,WX5853,WX5852,WX5855,WX5854,WX5857,
WX5856,WX5859,WX5858,WX5861,WX5860,WX5863,WX5862,WX5865,WX5864,WX5867,
WX5866,WX5869,WX5868,WX5871,WX5870,WX5873,WX5872,WX5875,WX5874,WX5877,
WX5876,WX5879,WX5878,WX5881,WX5880,WX5883,WX5882,WX5885,WX5884,WX5887,
WX5886,WX5889,WX5888,WX5891,WX5890,WX5893,WX5892,WX5895,WX5894,WX5897,
WX5896,WX5899,WX5898,WX5901,WX5900,WX5903,WX5902,WX5905,WX5904,WX5907,
WX5906,WX5909,WX5908,WX5911,WX5910,WX5913,WX5912,WX5915,WX5914,WX5917,
WX5916,WX5919,WX5918,WX5921,WX5920,WX5923,WX5922,WX5925,WX5924,WX5927,
WX5926,WX5929,WX5928,WX5931,WX5930,WX5933,WX5932,WX5935,WX5934,WX5937,
WX5936,WX5939,WX5938,WX5941,WX5940,WX5943,WX5942,WX5945,WX5944,WX5947,
WX5946,WX5949,WX5948,WX5951,WX5950,WX5953,WX5952,WX5955,WX5954,WX5957,
WX5956,WX5959,WX5958,WX5961,WX5960,WX5963,WX5962,WX5965,WX5964,WX5967,
WX5966,WX5969,WX5968,WX5971,WX5970,WX5973,WX5972,WX5975,WX5974,WX5977,
WX5976,WX5979,WX5978,WX5981,WX5980,WX5983,WX5982,WX5985,WX5984,WX5987,
WX5986,WX5989,WX5988,WX5991,WX5990,WX5993,WX5992,WX5995,WX5994,WX5997,
WX5996,WX5999,WX5998,WX6001,WX6000,WX6003,WX6002,WX6005,WX6004,WX6007,
WX6006,WX6009,WX6008,WX6011,WX6010,WX6013,WX6012,WX6015,WX6014,WX6017,
WX6016,WX6019,WX6018,WX6021,WX6020,WX6023,WX6022,WX6025,WX6024,WX6027,
WX6026,WX6029,WX6028,WX6031,WX6030,WX6033,WX6032,WX6035,WX6034,WX6037,
WX6036,WX6039,WX6038,WX6041,WX6040,WX6043,WX6042,WX6045,WX6044,WX6047,
WX6046,WX6049,WX6048,WX6051,WX6050,WX6053,WX6052,WX6055,WX6054,WX6057,
WX6056,WX6059,WX6058,WX6061,WX6060,WX6063,WX6062,WX6065,WX6064,WX6067,
WX6066,WX6069,WX6068,WX6071,WX6070,WX6436,WX6438,WX6440,WX6442,WX6444,
WX6446,WX6448,WX6450,WX6452,WX6454,WX6456,WX6458,WX6460,WX6462,WX6464,
WX6466,WX6468,WX6470,WX6472,WX6474,WX6476,WX6478,WX6480,WX6482,WX6484,
WX6486,WX6488,WX6490,WX6492,WX6494,WX6496,WX6498,WX6950,WX6949,WX6952,
WX6951,WX6954,WX6953,WX6956,WX6955,WX6958,WX6957,WX6960,WX6959,WX6962,
WX6961,WX6964,WX6963,WX6966,WX6965,WX6968,WX6967,WX6970,WX6969,WX6972,
WX6971,WX6974,WX6973,WX6976,WX6975,WX6978,WX6977,WX6980,WX6979,WX6982,
WX6981,WX6984,WX6983,WX6986,WX6985,WX6988,WX6987,WX6990,WX6989,WX6992,
WX6991,WX6994,WX6993,WX6996,WX6995,WX6998,WX6997,WX7000,WX6999,WX7002,
WX7001,WX7004,WX7003,WX7006,WX7005,WX7008,WX7007,WX7010,WX7009,WX7012,
WX7011,WX7110,WX7109,WX7112,WX7111,WX7114,WX7113,WX7116,WX7115,WX7118,
WX7117,WX7120,WX7119,WX7122,WX7121,WX7124,WX7123,WX7126,WX7125,WX7128,
WX7127,WX7130,WX7129,WX7132,WX7131,WX7134,WX7133,WX7136,WX7135,WX7138,
WX7137,WX7140,WX7139,WX7142,WX7141,WX7144,WX7143,WX7146,WX7145,WX7148,
WX7147,WX7150,WX7149,WX7152,WX7151,WX7154,WX7153,WX7156,WX7155,WX7158,
WX7157,WX7160,WX7159,WX7162,WX7161,WX7164,WX7163,WX7166,WX7165,WX7168,
WX7167,WX7170,WX7169,WX7172,WX7171,WX7174,WX7173,WX7176,WX7175,WX7178,
WX7177,WX7180,WX7179,WX7182,WX7181,WX7184,WX7183,WX7186,WX7185,WX7188,
WX7187,WX7190,WX7189,WX7192,WX7191,WX7194,WX7193,WX7196,WX7195,WX7198,
WX7197,WX7200,WX7199,WX7202,WX7201,WX7204,WX7203,WX7206,WX7205,WX7208,
WX7207,WX7210,WX7209,WX7212,WX7211,WX7214,WX7213,WX7216,WX7215,WX7218,
WX7217,WX7220,WX7219,WX7222,WX7221,WX7224,WX7223,WX7226,WX7225,WX7228,
WX7227,WX7230,WX7229,WX7232,WX7231,WX7234,WX7233,WX7236,WX7235,WX7238,
WX7237,WX7240,WX7239,WX7242,WX7241,WX7244,WX7243,WX7246,WX7245,WX7248,
WX7247,WX7250,WX7249,WX7252,WX7251,WX7254,WX7253,WX7256,WX7255,WX7258,
WX7257,WX7260,WX7259,WX7262,WX7261,WX7264,WX7263,WX7266,WX7265,WX7268,
WX7267,WX7270,WX7269,WX7272,WX7271,WX7274,WX7273,WX7276,WX7275,WX7278,
WX7277,WX7280,WX7279,WX7282,WX7281,WX7284,WX7283,WX7286,WX7285,WX7288,
WX7287,WX7290,WX7289,WX7292,WX7291,WX7294,WX7293,WX7296,WX7295,WX7298,
WX7297,WX7300,WX7299,WX7302,WX7301,WX7304,WX7303,WX7306,WX7305,WX7308,
WX7307,WX7310,WX7309,WX7312,WX7311,WX7314,WX7313,WX7316,WX7315,WX7318,
WX7317,WX7320,WX7319,WX7322,WX7321,WX7324,WX7323,WX7326,WX7325,WX7328,
WX7327,WX7330,WX7329,WX7332,WX7331,WX7334,WX7333,WX7336,WX7335,WX7338,
WX7337,WX7340,WX7339,WX7342,WX7341,WX7344,WX7343,WX7346,WX7345,WX7348,
WX7347,WX7350,WX7349,WX7352,WX7351,WX7354,WX7353,WX7356,WX7355,WX7358,
WX7357,WX7360,WX7359,WX7362,WX7361,WX7364,WX7363,WX7729,WX7731,WX7733,
WX7735,WX7737,WX7739,WX7741,WX7743,WX7745,WX7747,WX7749,WX7751,WX7753,
WX7755,WX7757,WX7759,WX7761,WX7763,WX7765,WX7767,WX7769,WX7771,WX7773,
WX7775,WX7777,WX7779,WX7781,WX7783,WX7785,WX7787,WX7789,WX7791,WX8243,
WX8242,WX8245,WX8244,WX8247,WX8246,WX8249,WX8248,WX8251,WX8250,WX8253,
WX8252,WX8255,WX8254,WX8257,WX8256,WX8259,WX8258,WX8261,WX8260,WX8263,
WX8262,WX8265,WX8264,WX8267,WX8266,WX8269,WX8268,WX8271,WX8270,WX8273,
WX8272,WX8275,WX8274,WX8277,WX8276,WX8279,WX8278,WX8281,WX8280,WX8283,
WX8282,WX8285,WX8284,WX8287,WX8286,WX8289,WX8288,WX8291,WX8290,WX8293,
WX8292,WX8295,WX8294,WX8297,WX8296,WX8299,WX8298,WX8301,WX8300,WX8303,
WX8302,WX8305,WX8304,WX8403,WX8402,WX8405,WX8404,WX8407,WX8406,WX8409,
WX8408,WX8411,WX8410,WX8413,WX8412,WX8415,WX8414,WX8417,WX8416,WX8419,
WX8418,WX8421,WX8420,WX8423,WX8422,WX8425,WX8424,WX8427,WX8426,WX8429,
WX8428,WX8431,WX8430,WX8433,WX8432,WX8435,WX8434,WX8437,WX8436,WX8439,
WX8438,WX8441,WX8440,WX8443,WX8442,WX8445,WX8444,WX8447,WX8446,WX8449,
WX8448,WX8451,WX8450,WX8453,WX8452,WX8455,WX8454,WX8457,WX8456,WX8459,
WX8458,WX8461,WX8460,WX8463,WX8462,WX8465,WX8464,WX8467,WX8466,WX8469,
WX8468,WX8471,WX8470,WX8473,WX8472,WX8475,WX8474,WX8477,WX8476,WX8479,
WX8478,WX8481,WX8480,WX8483,WX8482,WX8485,WX8484,WX8487,WX8486,WX8489,
WX8488,WX8491,WX8490,WX8493,WX8492,WX8495,WX8494,WX8497,WX8496,WX8499,
WX8498,WX8501,WX8500,WX8503,WX8502,WX8505,WX8504,WX8507,WX8506,WX8509,
WX8508,WX8511,WX8510,WX8513,WX8512,WX8515,WX8514,WX8517,WX8516,WX8519,
WX8518,WX8521,WX8520,WX8523,WX8522,WX8525,WX8524,WX8527,WX8526,WX8529,
WX8528,WX8531,WX8530,WX8533,WX8532,WX8535,WX8534,WX8537,WX8536,WX8539,
WX8538,WX8541,WX8540,WX8543,WX8542,WX8545,WX8544,WX8547,WX8546,WX8549,
WX8548,WX8551,WX8550,WX8553,WX8552,WX8555,WX8554,WX8557,WX8556,WX8559,
WX8558,WX8561,WX8560,WX8563,WX8562,WX8565,WX8564,WX8567,WX8566,WX8569,
WX8568,WX8571,WX8570,WX8573,WX8572,WX8575,WX8574,WX8577,WX8576,WX8579,
WX8578,WX8581,WX8580,WX8583,WX8582,WX8585,WX8584,WX8587,WX8586,WX8589,
WX8588,WX8591,WX8590,WX8593,WX8592,WX8595,WX8594,WX8597,WX8596,WX8599,
WX8598,WX8601,WX8600,WX8603,WX8602,WX8605,WX8604,WX8607,WX8606,WX8609,
WX8608,WX8611,WX8610,WX8613,WX8612,WX8615,WX8614,WX8617,WX8616,WX8619,
WX8618,WX8621,WX8620,WX8623,WX8622,WX8625,WX8624,WX8627,WX8626,WX8629,
WX8628,WX8631,WX8630,WX8633,WX8632,WX8635,WX8634,WX8637,WX8636,WX8639,
WX8638,WX8641,WX8640,WX8643,WX8642,WX8645,WX8644,WX8647,WX8646,WX8649,
WX8648,WX8651,WX8650,WX8653,WX8652,WX8655,WX8654,WX8657,WX8656,WX9022,
WX9024,WX9026,WX9028,WX9030,WX9032,WX9034,WX9036,WX9038,WX9040,WX9042,
WX9044,WX9046,WX9048,WX9050,WX9052,WX9054,WX9056,WX9058,WX9060,WX9062,
WX9064,WX9066,WX9068,WX9070,WX9072,WX9074,WX9076,WX9078,WX9080,WX9082,
WX9084,WX9536,WX9535,WX9538,WX9537,WX9540,WX9539,WX9542,WX9541,WX9544,
WX9543,WX9546,WX9545,WX9548,WX9547,WX9550,WX9549,WX9552,WX9551,WX9554,
WX9553,WX9556,WX9555,WX9558,WX9557,WX9560,WX9559,WX9562,WX9561,WX9564,
WX9563,WX9566,WX9565,WX9568,WX9567,WX9570,WX9569,WX9572,WX9571,WX9574,
WX9573,WX9576,WX9575,WX9578,WX9577,WX9580,WX9579,WX9582,WX9581,WX9584,
WX9583,WX9586,WX9585,WX9588,WX9587,WX9590,WX9589,WX9592,WX9591,WX9594,
WX9593,WX9596,WX9595,WX9598,WX9597,WX9696,WX9695,WX9698,WX9697,WX9700,
WX9699,WX9702,WX9701,WX9704,WX9703,WX9706,WX9705,WX9708,WX9707,WX9710,
WX9709,WX9712,WX9711,WX9714,WX9713,WX9716,WX9715,WX9718,WX9717,WX9720,
WX9719,WX9722,WX9721,WX9724,WX9723,WX9726,WX9725,WX9728,WX9727,WX9730,
WX9729,WX9732,WX9731,WX9734,WX9733,WX9736,WX9735,WX9738,WX9737,WX9740,
WX9739,WX9742,WX9741,WX9744,WX9743,WX9746,WX9745,WX9748,WX9747,WX9750,
WX9749,WX9752,WX9751,WX9754,WX9753,WX9756,WX9755,WX9758,WX9757,WX9760,
WX9759,WX9762,WX9761,WX9764,WX9763,WX9766,WX9765,WX9768,WX9767,WX9770,
WX9769,WX9772,WX9771,WX9774,WX9773,WX9776,WX9775,WX9778,WX9777,WX9780,
WX9779,WX9782,WX9781,WX9784,WX9783,WX9786,WX9785,WX9788,WX9787,WX9790,
WX9789,WX9792,WX9791,WX9794,WX9793,WX9796,WX9795,WX9798,WX9797,WX9800,
WX9799,WX9802,WX9801,WX9804,WX9803,WX9806,WX9805,WX9808,WX9807,WX9810,
WX9809,WX9812,WX9811,WX9814,WX9813,WX9816,WX9815,WX9818,WX9817,WX9820,
WX9819,WX9822,WX9821,WX9824,WX9823,WX9826,WX9825,WX9828,WX9827,WX9830,
WX9829,WX9832,WX9831,WX9834,WX9833,WX9836,WX9835,WX9838,WX9837,WX9840,
WX9839,WX9842,WX9841,WX9844,WX9843,WX9846,WX9845,WX9848,WX9847,WX9850,
WX9849,WX9852,WX9851,WX9854,WX9853,WX9856,WX9855,WX9858,WX9857,WX9860,
WX9859,WX9862,WX9861,WX9864,WX9863,WX9866,WX9865,WX9868,WX9867,WX9870,
WX9869,WX9872,WX9871,WX9874,WX9873,WX9876,WX9875,WX9878,WX9877,WX9880,
WX9879,WX9882,WX9881,WX9884,WX9883,WX9886,WX9885,WX9888,WX9887,WX9890,
WX9889,WX9892,WX9891,WX9894,WX9893,WX9896,WX9895,WX9898,WX9897,WX9900,
WX9899,WX9902,WX9901,WX9904,WX9903,WX9906,WX9905,WX9908,WX9907,WX9910,
WX9909,WX9912,WX9911,WX9914,WX9913,WX9916,WX9915,WX9918,WX9917,WX9920,
WX9919,WX9922,WX9921,WX9924,WX9923,WX9926,WX9925,WX9928,WX9927,WX9930,
WX9929,WX9932,WX9931,WX9934,WX9933,WX9936,WX9935,WX9938,WX9937,WX9940,
WX9939,WX9942,WX9941,WX9944,WX9943,WX9946,WX9945,WX9948,WX9947,WX9950,
WX9949,WX10315,WX10317,WX10319,WX10321,WX10323,WX10325,WX10327,WX10329,
WX10331,WX10333,WX10335,WX10337,WX10339,WX10341,WX10343,WX10345,WX10347,
WX10349,WX10351,WX10353,WX10355,WX10357,WX10359,WX10361,WX10363,WX10365,
WX10367,WX10369,WX10371,WX10373,WX10375,WX10377,WX10829,WX10828,WX10831,
WX10830,WX10833,WX10832,WX10835,WX10834,WX10837,WX10836,WX10839,WX10838,
WX10841,WX10840,WX10843,WX10842,WX10845,WX10844,WX10847,WX10846,WX10849,
WX10848,WX10851,WX10850,WX10853,WX10852,WX10855,WX10854,WX10857,WX10856,
WX10859,WX10858,WX10861,WX10860,WX10863,WX10862,WX10865,WX10864,WX10867,
WX10866,WX10869,WX10868,WX10871,WX10870,WX10873,WX10872,WX10875,WX10874,
WX10877,WX10876,WX10879,WX10878,WX10881,WX10880,WX10883,WX10882,WX10885,
WX10884,WX10887,WX10886,WX10889,WX10888,WX10891,WX10890,WX10989,WX10988,
WX10991,WX10990,WX10993,WX10992,WX10995,WX10994,WX10997,WX10996,WX10999,
WX10998,WX11001,WX11000,WX11003,WX11002,WX11005,WX11004,WX11007,WX11006,
WX11009,WX11008,WX11011,WX11010,WX11013,WX11012,WX11015,WX11014,WX11017,
WX11016,WX11019,WX11018,WX11021,WX11020,WX11023,WX11022,WX11025,WX11024,
WX11027,WX11026,WX11029,WX11028,WX11031,WX11030,WX11033,WX11032,WX11035,
WX11034,WX11037,WX11036,WX11039,WX11038,WX11041,WX11040,WX11043,WX11042,
WX11045,WX11044,WX11047,WX11046,WX11049,WX11048,WX11051,WX11050,WX11053,
WX11052,WX11055,WX11054,WX11057,WX11056,WX11059,WX11058,WX11061,WX11060,
WX11063,WX11062,WX11065,WX11064,WX11067,WX11066,WX11069,WX11068,WX11071,
WX11070,WX11073,WX11072,WX11075,WX11074,WX11077,WX11076,WX11079,WX11078,
WX11081,WX11080,WX11083,WX11082,WX11085,WX11084,WX11087,WX11086,WX11089,
WX11088,WX11091,WX11090,WX11093,WX11092,WX11095,WX11094,WX11097,WX11096,
WX11099,WX11098,WX11101,WX11100,WX11103,WX11102,WX11105,WX11104,WX11107,
WX11106,WX11109,WX11108,WX11111,WX11110,WX11113,WX11112,WX11115,WX11114,
WX11117,WX11116,WX11119,WX11118,WX11121,WX11120,WX11123,WX11122,WX11125,
WX11124,WX11127,WX11126,WX11129,WX11128,WX11131,WX11130,WX11133,WX11132,
WX11135,WX11134,WX11137,WX11136,WX11139,WX11138,WX11141,WX11140,WX11143,
WX11142,WX11145,WX11144,WX11147,WX11146,WX11149,WX11148,WX11151,WX11150,
WX11153,WX11152,WX11155,WX11154,WX11157,WX11156,WX11159,WX11158,WX11161,
WX11160,WX11163,WX11162,WX11165,WX11164,WX11167,WX11166,WX11169,WX11168,
WX11171,WX11170,WX11173,WX11172,WX11175,WX11174,WX11177,WX11176,WX11179,
WX11178,WX11181,WX11180,WX11183,WX11182,WX11185,WX11184,WX11187,WX11186,
WX11189,WX11188,WX11191,WX11190,WX11193,WX11192,WX11195,WX11194,WX11197,
WX11196,WX11199,WX11198,WX11201,WX11200,WX11203,WX11202,WX11205,WX11204,
WX11207,WX11206,WX11209,WX11208,WX11211,WX11210,WX11213,WX11212,WX11215,
WX11214,WX11217,WX11216,WX11219,WX11218,WX11221,WX11220,WX11223,WX11222,
WX11225,WX11224,WX11227,WX11226,WX11229,WX11228,WX11231,WX11230,WX11233,
WX11232,WX11235,WX11234,WX11237,WX11236,WX11239,WX11238,WX11241,WX11240,
WX11243,WX11242,WX11608,WX11610,WX11612,WX11614,WX11616,WX11618,WX11620,
WX11622,WX11624,WX11626,WX11628,WX11630,WX11632,WX11634,WX11636,WX11638,
WX11640,WX11642,WX11644,WX11646,WX11648,WX11650,WX11652,WX11654,WX11656,
WX11658,WX11660,WX11662,WX11664,WX11666,WX11668,WX11670,WX37,WX1003,WX41,
WX1004,WX45,WX47,WX38,WX48,WX51,WX55,WX59,WX61,WX52,WX62,WX65,WX69,WX73,
WX75,WX66,WX76,WX79,WX83,WX87,WX89,WX80,WX90,WX93,WX97,WX101,WX103,WX94,
WX104,WX107,WX111,WX115,WX117,WX108,WX118,WX121,WX125,WX129,WX131,WX122,
WX132,WX135,WX139,WX143,WX145,WX136,WX146,WX149,WX153,WX157,WX159,WX150,
WX160,WX163,WX167,WX171,WX173,WX164,WX174,WX177,WX181,WX185,WX187,WX178,
WX188,WX191,WX195,WX199,WX201,WX192,WX202,WX205,WX209,WX213,WX215,WX206,
WX216,WX219,WX223,WX227,WX229,WX220,WX230,WX233,WX237,WX241,WX243,WX234,
WX244,WX247,WX251,WX255,WX257,WX248,WX258,WX261,WX265,WX269,WX271,WX262,
WX272,WX275,WX279,WX283,WX285,WX276,WX286,WX289,WX293,WX297,WX299,WX290,
WX300,WX303,WX307,WX311,WX313,WX304,WX314,WX317,WX321,WX325,WX327,WX318,
WX328,WX331,WX335,WX339,WX341,WX332,WX342,WX345,WX349,WX353,WX355,WX346,
WX356,WX359,WX363,WX367,WX369,WX360,WX370,WX373,WX377,WX381,WX383,WX374,
WX384,WX387,WX391,WX395,WX397,WX388,WX398,WX401,WX405,WX409,WX411,WX402,
WX412,WX415,WX419,WX423,WX425,WX416,WX426,WX429,WX433,WX437,WX439,WX430,
WX440,WX443,WX447,WX451,WX453,WX444,WX454,WX457,WX461,WX465,WX467,WX458,
WX468,WX471,WX475,WX479,WX481,WX472,WX482,WX483,WX548,WX965,WX549,WX967,
WX550,WX969,WX551,WX971,WX552,WX973,WX553,WX975,WX554,WX977,WX555,WX979,
WX556,WX981,WX557,WX983,WX558,WX985,WX559,WX987,WX560,WX989,WX561,WX991,
WX562,WX993,WX563,WX995,WX564,WX933,WX565,WX935,WX566,WX937,WX567,WX939,
WX568,WX941,WX569,WX943,WX570,WX945,WX571,WX947,WX572,WX949,WX573,WX951,
WX574,WX953,WX575,WX955,WX576,WX957,WX577,WX959,WX578,WX961,WX579,WX963,
WX580,WX581,WX582,WX583,WX584,WX585,WX586,WX587,WX588,WX589,WX590,WX591,
WX592,WX593,WX594,WX595,WX596,WX597,WX598,WX599,WX600,WX601,WX602,WX603,
WX604,WX605,WX606,WX607,WX608,WX609,WX610,WX611,WX612,WX613,WX614,WX615,
WX616,WX617,WX618,WX619,WX620,WX621,WX622,WX623,WX624,WX625,WX626,WX627,
WX628,WX629,WX630,WX631,WX632,WX633,WX634,WX635,WX636,WX637,WX638,WX639,
WX640,WX641,WX642,WX643,WX932,WX916,WX934,WX917,WX936,WX918,WX938,WX919,
WX940,WX920,WX942,WX921,WX944,WX922,WX946,WX923,WX948,WX924,WX950,WX925,
WX952,WX926,WX954,WX927,WX956,WX928,WX958,WX929,WX960,WX930,WX962,WX931,
WX964,WX900,WX966,WX901,WX968,WX902,WX970,WX903,WX972,WX904,WX974,WX905,
WX976,WX906,WX978,WX907,WX980,WX908,WX982,WX909,WX984,WX910,WX986,WX911,
WX988,WX912,WX990,WX913,WX992,WX914,WX994,WX915,WX996,WX997,WX998,WX999,
WX1000,WX1001,WX1002,WX1005,WX1009,WX1011,WX1010,WX1016,WX1018,WX1017,
WX1023,WX1025,WX1024,WX1030,WX1032,WX1031,WX1037,WX1039,WX1038,WX1044,
WX1046,WX1045,WX1051,WX1053,WX1052,WX1058,WX1060,WX1059,WX1065,WX1067,
WX1066,WX1072,WX1074,WX1073,WX1079,WX1081,WX1080,WX1086,WX1088,WX1087,
WX1093,WX1095,WX1094,WX1100,WX1102,WX1101,WX1107,WX1109,WX1108,WX1114,
WX1116,WX1115,WX1121,WX1123,WX1122,WX1128,WX1130,WX1129,WX1135,WX1137,
WX1136,WX1142,WX1144,WX1143,WX1149,WX1151,WX1150,WX1156,WX1158,WX1157,
WX1163,WX1165,WX1164,WX1170,WX1172,WX1171,WX1177,WX1179,WX1178,WX1184,
WX1186,WX1185,WX1191,WX1193,WX1192,WX1198,WX1200,WX1199,WX1205,WX1207,
WX1206,WX1212,WX1214,WX1213,WX1219,WX1221,WX1220,WX1226,WX1228,WX1227,
WX1230,WX1263,WX1330,WX2296,WX1334,WX2297,WX1338,WX1340,WX1331,WX1341,
WX1344,WX1348,WX1352,WX1354,WX1345,WX1355,WX1358,WX1362,WX1366,WX1368,
WX1359,WX1369,WX1372,WX1376,WX1380,WX1382,WX1373,WX1383,WX1386,WX1390,
WX1394,WX1396,WX1387,WX1397,WX1400,WX1404,WX1408,WX1410,WX1401,WX1411,
WX1414,WX1418,WX1422,WX1424,WX1415,WX1425,WX1428,WX1432,WX1436,WX1438,
WX1429,WX1439,WX1442,WX1446,WX1450,WX1452,WX1443,WX1453,WX1456,WX1460,
WX1464,WX1466,WX1457,WX1467,WX1470,WX1474,WX1478,WX1480,WX1471,WX1481,
WX1484,WX1488,WX1492,WX1494,WX1485,WX1495,WX1498,WX1502,WX1506,WX1508,
WX1499,WX1509,WX1512,WX1516,WX1520,WX1522,WX1513,WX1523,WX1526,WX1530,
WX1534,WX1536,WX1527,WX1537,WX1540,WX1544,WX1548,WX1550,WX1541,WX1551,
WX1554,WX1558,WX1562,WX1564,WX1555,WX1565,WX1568,WX1572,WX1576,WX1578,
WX1569,WX1579,WX1582,WX1586,WX1590,WX1592,WX1583,WX1593,WX1596,WX1600,
WX1604,WX1606,WX1597,WX1607,WX1610,WX1614,WX1618,WX1620,WX1611,WX1621,
WX1624,WX1628,WX1632,WX1634,WX1625,WX1635,WX1638,WX1642,WX1646,WX1648,
WX1639,WX1649,WX1652,WX1656,WX1660,WX1662,WX1653,WX1663,WX1666,WX1670,
WX1674,WX1676,WX1667,WX1677,WX1680,WX1684,WX1688,WX1690,WX1681,WX1691,
WX1694,WX1698,WX1702,WX1704,WX1695,WX1705,WX1708,WX1712,WX1716,WX1718,
WX1709,WX1719,WX1722,WX1726,WX1730,WX1732,WX1723,WX1733,WX1736,WX1740,
WX1744,WX1746,WX1737,WX1747,WX1750,WX1754,WX1758,WX1760,WX1751,WX1761,
WX1764,WX1768,WX1772,WX1774,WX1765,WX1775,WX1776,WX1841,WX2258,WX1842,
WX2260,WX1843,WX2262,WX1844,WX2264,WX1845,WX2266,WX1846,WX2268,WX1847,
WX2270,WX1848,WX2272,WX1849,WX2274,WX1850,WX2276,WX1851,WX2278,WX1852,
WX2280,WX1853,WX2282,WX1854,WX2284,WX1855,WX2286,WX1856,WX2288,WX1857,
WX2226,WX1858,WX2228,WX1859,WX2230,WX1860,WX2232,WX1861,WX2234,WX1862,
WX2236,WX1863,WX2238,WX1864,WX2240,WX1865,WX2242,WX1866,WX2244,WX1867,
WX2246,WX1868,WX2248,WX1869,WX2250,WX1870,WX2252,WX1871,WX2254,WX1872,
WX2256,WX1873,WX1874,WX1875,WX1876,WX1877,WX1878,WX1879,WX1880,WX1881,
WX1882,WX1883,WX1884,WX1885,WX1886,WX1887,WX1888,WX1889,WX1890,WX1891,
WX1892,WX1893,WX1894,WX1895,WX1896,WX1897,WX1898,WX1899,WX1900,WX1901,
WX1902,WX1903,WX1904,WX1905,WX1906,WX1907,WX1908,WX1909,WX1910,WX1911,
WX1912,WX1913,WX1914,WX1915,WX1916,WX1917,WX1918,WX1919,WX1920,WX1921,
WX1922,WX1923,WX1924,WX1925,WX1926,WX1927,WX1928,WX1929,WX1930,WX1931,
WX1932,WX1933,WX1934,WX1935,WX1936,WX2225,WX2209,WX2227,WX2210,WX2229,
WX2211,WX2231,WX2212,WX2233,WX2213,WX2235,WX2214,WX2237,WX2215,WX2239,
WX2216,WX2241,WX2217,WX2243,WX2218,WX2245,WX2219,WX2247,WX2220,WX2249,
WX2221,WX2251,WX2222,WX2253,WX2223,WX2255,WX2224,WX2257,WX2193,WX2259,
WX2194,WX2261,WX2195,WX2263,WX2196,WX2265,WX2197,WX2267,WX2198,WX2269,
WX2199,WX2271,WX2200,WX2273,WX2201,WX2275,WX2202,WX2277,WX2203,WX2279,
WX2204,WX2281,WX2205,WX2283,WX2206,WX2285,WX2207,WX2287,WX2208,WX2289,
WX2290,WX2291,WX2292,WX2293,WX2294,WX2295,WX2298,WX2302,WX2304,WX2303,
WX2305,WX2309,WX2311,WX2310,WX2312,WX2316,WX2318,WX2317,WX2319,WX2323,
WX2325,WX2324,WX2326,WX2330,WX2332,WX2331,WX2333,WX2337,WX2339,WX2338,
WX2340,WX2344,WX2346,WX2345,WX2347,WX2351,WX2353,WX2352,WX2354,WX2358,
WX2360,WX2359,WX2361,WX2365,WX2367,WX2366,WX2368,WX2372,WX2374,WX2373,
WX2375,WX2379,WX2381,WX2380,WX2382,WX2386,WX2388,WX2387,WX2389,WX2393,
WX2395,WX2394,WX2396,WX2400,WX2402,WX2401,WX2403,WX2407,WX2409,WX2408,
WX2410,WX2414,WX2416,WX2415,WX2417,WX2421,WX2423,WX2422,WX2424,WX2428,
WX2430,WX2429,WX2431,WX2435,WX2437,WX2436,WX2438,WX2442,WX2444,WX2443,
WX2445,WX2449,WX2451,WX2450,WX2452,WX2456,WX2458,WX2457,WX2459,WX2463,
WX2465,WX2464,WX2466,WX2470,WX2472,WX2471,WX2473,WX2477,WX2479,WX2478,
WX2480,WX2484,WX2486,WX2485,WX2487,WX2491,WX2493,WX2492,WX2494,WX2498,
WX2500,WX2499,WX2501,WX2505,WX2507,WX2506,WX2508,WX2512,WX2514,WX2513,
WX2515,WX2519,WX2521,WX2520,WX2522,WX2523,WX2556,WX2623,WX3589,WX2627,
WX3590,WX2631,WX2633,WX2624,WX2634,WX2637,WX2641,WX2645,WX2647,WX2638,
WX2648,WX2651,WX2655,WX2659,WX2661,WX2652,WX2662,WX2665,WX2669,WX2673,
WX2675,WX2666,WX2676,WX2679,WX2683,WX2687,WX2689,WX2680,WX2690,WX2693,
WX2697,WX2701,WX2703,WX2694,WX2704,WX2707,WX2711,WX2715,WX2717,WX2708,
WX2718,WX2721,WX2725,WX2729,WX2731,WX2722,WX2732,WX2735,WX2739,WX2743,
WX2745,WX2736,WX2746,WX2749,WX2753,WX2757,WX2759,WX2750,WX2760,WX2763,
WX2767,WX2771,WX2773,WX2764,WX2774,WX2777,WX2781,WX2785,WX2787,WX2778,
WX2788,WX2791,WX2795,WX2799,WX2801,WX2792,WX2802,WX2805,WX2809,WX2813,
WX2815,WX2806,WX2816,WX2819,WX2823,WX2827,WX2829,WX2820,WX2830,WX2833,
WX2837,WX2841,WX2843,WX2834,WX2844,WX2847,WX2851,WX2855,WX2857,WX2848,
WX2858,WX2861,WX2865,WX2869,WX2871,WX2862,WX2872,WX2875,WX2879,WX2883,
WX2885,WX2876,WX2886,WX2889,WX2893,WX2897,WX2899,WX2890,WX2900,WX2903,
WX2907,WX2911,WX2913,WX2904,WX2914,WX2917,WX2921,WX2925,WX2927,WX2918,
WX2928,WX2931,WX2935,WX2939,WX2941,WX2932,WX2942,WX2945,WX2949,WX2953,
WX2955,WX2946,WX2956,WX2959,WX2963,WX2967,WX2969,WX2960,WX2970,WX2973,
WX2977,WX2981,WX2983,WX2974,WX2984,WX2987,WX2991,WX2995,WX2997,WX2988,
WX2998,WX3001,WX3005,WX3009,WX3011,WX3002,WX3012,WX3015,WX3019,WX3023,
WX3025,WX3016,WX3026,WX3029,WX3033,WX3037,WX3039,WX3030,WX3040,WX3043,
WX3047,WX3051,WX3053,WX3044,WX3054,WX3057,WX3061,WX3065,WX3067,WX3058,
WX3068,WX3069,WX3134,WX3551,WX3135,WX3553,WX3136,WX3555,WX3137,WX3557,
WX3138,WX3559,WX3139,WX3561,WX3140,WX3563,WX3141,WX3565,WX3142,WX3567,
WX3143,WX3569,WX3144,WX3571,WX3145,WX3573,WX3146,WX3575,WX3147,WX3577,
WX3148,WX3579,WX3149,WX3581,WX3150,WX3519,WX3151,WX3521,WX3152,WX3523,
WX3153,WX3525,WX3154,WX3527,WX3155,WX3529,WX3156,WX3531,WX3157,WX3533,
WX3158,WX3535,WX3159,WX3537,WX3160,WX3539,WX3161,WX3541,WX3162,WX3543,
WX3163,WX3545,WX3164,WX3547,WX3165,WX3549,WX3166,WX3167,WX3168,WX3169,
WX3170,WX3171,WX3172,WX3173,WX3174,WX3175,WX3176,WX3177,WX3178,WX3179,
WX3180,WX3181,WX3182,WX3183,WX3184,WX3185,WX3186,WX3187,WX3188,WX3189,
WX3190,WX3191,WX3192,WX3193,WX3194,WX3195,WX3196,WX3197,WX3198,WX3199,
WX3200,WX3201,WX3202,WX3203,WX3204,WX3205,WX3206,WX3207,WX3208,WX3209,
WX3210,WX3211,WX3212,WX3213,WX3214,WX3215,WX3216,WX3217,WX3218,WX3219,
WX3220,WX3221,WX3222,WX3223,WX3224,WX3225,WX3226,WX3227,WX3228,WX3229,
WX3518,WX3502,WX3520,WX3503,WX3522,WX3504,WX3524,WX3505,WX3526,WX3506,
WX3528,WX3507,WX3530,WX3508,WX3532,WX3509,WX3534,WX3510,WX3536,WX3511,
WX3538,WX3512,WX3540,WX3513,WX3542,WX3514,WX3544,WX3515,WX3546,WX3516,
WX3548,WX3517,WX3550,WX3486,WX3552,WX3487,WX3554,WX3488,WX3556,WX3489,
WX3558,WX3490,WX3560,WX3491,WX3562,WX3492,WX3564,WX3493,WX3566,WX3494,
WX3568,WX3495,WX3570,WX3496,WX3572,WX3497,WX3574,WX3498,WX3576,WX3499,
WX3578,WX3500,WX3580,WX3501,WX3582,WX3583,WX3584,WX3585,WX3586,WX3587,
WX3588,WX3591,WX3595,WX3597,WX3596,WX3598,WX3602,WX3604,WX3603,WX3605,
WX3609,WX3611,WX3610,WX3612,WX3616,WX3618,WX3617,WX3619,WX3623,WX3625,
WX3624,WX3626,WX3630,WX3632,WX3631,WX3633,WX3637,WX3639,WX3638,WX3640,
WX3644,WX3646,WX3645,WX3647,WX3651,WX3653,WX3652,WX3654,WX3658,WX3660,
WX3659,WX3661,WX3665,WX3667,WX3666,WX3668,WX3672,WX3674,WX3673,WX3675,
WX3679,WX3681,WX3680,WX3682,WX3686,WX3688,WX3687,WX3689,WX3693,WX3695,
WX3694,WX3696,WX3700,WX3702,WX3701,WX3703,WX3707,WX3709,WX3708,WX3710,
WX3714,WX3716,WX3715,WX3717,WX3721,WX3723,WX3722,WX3724,WX3728,WX3730,
WX3729,WX3731,WX3735,WX3737,WX3736,WX3738,WX3742,WX3744,WX3743,WX3745,
WX3749,WX3751,WX3750,WX3752,WX3756,WX3758,WX3757,WX3759,WX3763,WX3765,
WX3764,WX3766,WX3770,WX3772,WX3771,WX3773,WX3777,WX3779,WX3778,WX3780,
WX3784,WX3786,WX3785,WX3787,WX3791,WX3793,WX3792,WX3794,WX3798,WX3800,
WX3799,WX3801,WX3805,WX3807,WX3806,WX3808,WX3812,WX3814,WX3813,WX3815,
WX3816,WX3849,WX3916,WX4882,WX3920,WX4883,WX3924,WX3926,WX3917,WX3927,
WX3930,WX3934,WX3938,WX3940,WX3931,WX3941,WX3944,WX3948,WX3952,WX3954,
WX3945,WX3955,WX3958,WX3962,WX3966,WX3968,WX3959,WX3969,WX3972,WX3976,
WX3980,WX3982,WX3973,WX3983,WX3986,WX3990,WX3994,WX3996,WX3987,WX3997,
WX4000,WX4004,WX4008,WX4010,WX4001,WX4011,WX4014,WX4018,WX4022,WX4024,
WX4015,WX4025,WX4028,WX4032,WX4036,WX4038,WX4029,WX4039,WX4042,WX4046,
WX4050,WX4052,WX4043,WX4053,WX4056,WX4060,WX4064,WX4066,WX4057,WX4067,
WX4070,WX4074,WX4078,WX4080,WX4071,WX4081,WX4084,WX4088,WX4092,WX4094,
WX4085,WX4095,WX4098,WX4102,WX4106,WX4108,WX4099,WX4109,WX4112,WX4116,
WX4120,WX4122,WX4113,WX4123,WX4126,WX4130,WX4134,WX4136,WX4127,WX4137,
WX4140,WX4144,WX4148,WX4150,WX4141,WX4151,WX4154,WX4158,WX4162,WX4164,
WX4155,WX4165,WX4168,WX4172,WX4176,WX4178,WX4169,WX4179,WX4182,WX4186,
WX4190,WX4192,WX4183,WX4193,WX4196,WX4200,WX4204,WX4206,WX4197,WX4207,
WX4210,WX4214,WX4218,WX4220,WX4211,WX4221,WX4224,WX4228,WX4232,WX4234,
WX4225,WX4235,WX4238,WX4242,WX4246,WX4248,WX4239,WX4249,WX4252,WX4256,
WX4260,WX4262,WX4253,WX4263,WX4266,WX4270,WX4274,WX4276,WX4267,WX4277,
WX4280,WX4284,WX4288,WX4290,WX4281,WX4291,WX4294,WX4298,WX4302,WX4304,
WX4295,WX4305,WX4308,WX4312,WX4316,WX4318,WX4309,WX4319,WX4322,WX4326,
WX4330,WX4332,WX4323,WX4333,WX4336,WX4340,WX4344,WX4346,WX4337,WX4347,
WX4350,WX4354,WX4358,WX4360,WX4351,WX4361,WX4362,WX4427,WX4844,WX4428,
WX4846,WX4429,WX4848,WX4430,WX4850,WX4431,WX4852,WX4432,WX4854,WX4433,
WX4856,WX4434,WX4858,WX4435,WX4860,WX4436,WX4862,WX4437,WX4864,WX4438,
WX4866,WX4439,WX4868,WX4440,WX4870,WX4441,WX4872,WX4442,WX4874,WX4443,
WX4812,WX4444,WX4814,WX4445,WX4816,WX4446,WX4818,WX4447,WX4820,WX4448,
WX4822,WX4449,WX4824,WX4450,WX4826,WX4451,WX4828,WX4452,WX4830,WX4453,
WX4832,WX4454,WX4834,WX4455,WX4836,WX4456,WX4838,WX4457,WX4840,WX4458,
WX4842,WX4459,WX4460,WX4461,WX4462,WX4463,WX4464,WX4465,WX4466,WX4467,
WX4468,WX4469,WX4470,WX4471,WX4472,WX4473,WX4474,WX4475,WX4476,WX4477,
WX4478,WX4479,WX4480,WX4481,WX4482,WX4483,WX4484,WX4485,WX4486,WX4487,
WX4488,WX4489,WX4490,WX4491,WX4492,WX4493,WX4494,WX4495,WX4496,WX4497,
WX4498,WX4499,WX4500,WX4501,WX4502,WX4503,WX4504,WX4505,WX4506,WX4507,
WX4508,WX4509,WX4510,WX4511,WX4512,WX4513,WX4514,WX4515,WX4516,WX4517,
WX4518,WX4519,WX4520,WX4521,WX4522,WX4811,WX4795,WX4813,WX4796,WX4815,
WX4797,WX4817,WX4798,WX4819,WX4799,WX4821,WX4800,WX4823,WX4801,WX4825,
WX4802,WX4827,WX4803,WX4829,WX4804,WX4831,WX4805,WX4833,WX4806,WX4835,
WX4807,WX4837,WX4808,WX4839,WX4809,WX4841,WX4810,WX4843,WX4779,WX4845,
WX4780,WX4847,WX4781,WX4849,WX4782,WX4851,WX4783,WX4853,WX4784,WX4855,
WX4785,WX4857,WX4786,WX4859,WX4787,WX4861,WX4788,WX4863,WX4789,WX4865,
WX4790,WX4867,WX4791,WX4869,WX4792,WX4871,WX4793,WX4873,WX4794,WX4875,
WX4876,WX4877,WX4878,WX4879,WX4880,WX4881,WX4884,WX4888,WX4890,WX4889,
WX4891,WX4895,WX4897,WX4896,WX4898,WX4902,WX4904,WX4903,WX4905,WX4909,
WX4911,WX4910,WX4912,WX4916,WX4918,WX4917,WX4919,WX4923,WX4925,WX4924,
WX4926,WX4930,WX4932,WX4931,WX4933,WX4937,WX4939,WX4938,WX4940,WX4944,
WX4946,WX4945,WX4947,WX4951,WX4953,WX4952,WX4954,WX4958,WX4960,WX4959,
WX4961,WX4965,WX4967,WX4966,WX4968,WX4972,WX4974,WX4973,WX4975,WX4979,
WX4981,WX4980,WX4982,WX4986,WX4988,WX4987,WX4989,WX4993,WX4995,WX4994,
WX4996,WX5000,WX5002,WX5001,WX5003,WX5007,WX5009,WX5008,WX5010,WX5014,
WX5016,WX5015,WX5017,WX5021,WX5023,WX5022,WX5024,WX5028,WX5030,WX5029,
WX5031,WX5035,WX5037,WX5036,WX5038,WX5042,WX5044,WX5043,WX5045,WX5049,
WX5051,WX5050,WX5052,WX5056,WX5058,WX5057,WX5059,WX5063,WX5065,WX5064,
WX5066,WX5070,WX5072,WX5071,WX5073,WX5077,WX5079,WX5078,WX5080,WX5084,
WX5086,WX5085,WX5087,WX5091,WX5093,WX5092,WX5094,WX5098,WX5100,WX5099,
WX5101,WX5105,WX5107,WX5106,WX5108,WX5109,WX5142,WX5209,WX6175,WX5213,
WX6176,WX5217,WX5219,WX5210,WX5220,WX5223,WX5227,WX5231,WX5233,WX5224,
WX5234,WX5237,WX5241,WX5245,WX5247,WX5238,WX5248,WX5251,WX5255,WX5259,
WX5261,WX5252,WX5262,WX5265,WX5269,WX5273,WX5275,WX5266,WX5276,WX5279,
WX5283,WX5287,WX5289,WX5280,WX5290,WX5293,WX5297,WX5301,WX5303,WX5294,
WX5304,WX5307,WX5311,WX5315,WX5317,WX5308,WX5318,WX5321,WX5325,WX5329,
WX5331,WX5322,WX5332,WX5335,WX5339,WX5343,WX5345,WX5336,WX5346,WX5349,
WX5353,WX5357,WX5359,WX5350,WX5360,WX5363,WX5367,WX5371,WX5373,WX5364,
WX5374,WX5377,WX5381,WX5385,WX5387,WX5378,WX5388,WX5391,WX5395,WX5399,
WX5401,WX5392,WX5402,WX5405,WX5409,WX5413,WX5415,WX5406,WX5416,WX5419,
WX5423,WX5427,WX5429,WX5420,WX5430,WX5433,WX5437,WX5441,WX5443,WX5434,
WX5444,WX5447,WX5451,WX5455,WX5457,WX5448,WX5458,WX5461,WX5465,WX5469,
WX5471,WX5462,WX5472,WX5475,WX5479,WX5483,WX5485,WX5476,WX5486,WX5489,
WX5493,WX5497,WX5499,WX5490,WX5500,WX5503,WX5507,WX5511,WX5513,WX5504,
WX5514,WX5517,WX5521,WX5525,WX5527,WX5518,WX5528,WX5531,WX5535,WX5539,
WX5541,WX5532,WX5542,WX5545,WX5549,WX5553,WX5555,WX5546,WX5556,WX5559,
WX5563,WX5567,WX5569,WX5560,WX5570,WX5573,WX5577,WX5581,WX5583,WX5574,
WX5584,WX5587,WX5591,WX5595,WX5597,WX5588,WX5598,WX5601,WX5605,WX5609,
WX5611,WX5602,WX5612,WX5615,WX5619,WX5623,WX5625,WX5616,WX5626,WX5629,
WX5633,WX5637,WX5639,WX5630,WX5640,WX5643,WX5647,WX5651,WX5653,WX5644,
WX5654,WX5655,WX5720,WX6137,WX5721,WX6139,WX5722,WX6141,WX5723,WX6143,
WX5724,WX6145,WX5725,WX6147,WX5726,WX6149,WX5727,WX6151,WX5728,WX6153,
WX5729,WX6155,WX5730,WX6157,WX5731,WX6159,WX5732,WX6161,WX5733,WX6163,
WX5734,WX6165,WX5735,WX6167,WX5736,WX6105,WX5737,WX6107,WX5738,WX6109,
WX5739,WX6111,WX5740,WX6113,WX5741,WX6115,WX5742,WX6117,WX5743,WX6119,
WX5744,WX6121,WX5745,WX6123,WX5746,WX6125,WX5747,WX6127,WX5748,WX6129,
WX5749,WX6131,WX5750,WX6133,WX5751,WX6135,WX5752,WX5753,WX5754,WX5755,
WX5756,WX5757,WX5758,WX5759,WX5760,WX5761,WX5762,WX5763,WX5764,WX5765,
WX5766,WX5767,WX5768,WX5769,WX5770,WX5771,WX5772,WX5773,WX5774,WX5775,
WX5776,WX5777,WX5778,WX5779,WX5780,WX5781,WX5782,WX5783,WX5784,WX5785,
WX5786,WX5787,WX5788,WX5789,WX5790,WX5791,WX5792,WX5793,WX5794,WX5795,
WX5796,WX5797,WX5798,WX5799,WX5800,WX5801,WX5802,WX5803,WX5804,WX5805,
WX5806,WX5807,WX5808,WX5809,WX5810,WX5811,WX5812,WX5813,WX5814,WX5815,
WX6104,WX6088,WX6106,WX6089,WX6108,WX6090,WX6110,WX6091,WX6112,WX6092,
WX6114,WX6093,WX6116,WX6094,WX6118,WX6095,WX6120,WX6096,WX6122,WX6097,
WX6124,WX6098,WX6126,WX6099,WX6128,WX6100,WX6130,WX6101,WX6132,WX6102,
WX6134,WX6103,WX6136,WX6072,WX6138,WX6073,WX6140,WX6074,WX6142,WX6075,
WX6144,WX6076,WX6146,WX6077,WX6148,WX6078,WX6150,WX6079,WX6152,WX6080,
WX6154,WX6081,WX6156,WX6082,WX6158,WX6083,WX6160,WX6084,WX6162,WX6085,
WX6164,WX6086,WX6166,WX6087,WX6168,WX6169,WX6170,WX6171,WX6172,WX6173,
WX6174,WX6177,WX6181,WX6183,WX6182,WX6184,WX6188,WX6190,WX6189,WX6191,
WX6195,WX6197,WX6196,WX6198,WX6202,WX6204,WX6203,WX6205,WX6209,WX6211,
WX6210,WX6212,WX6216,WX6218,WX6217,WX6219,WX6223,WX6225,WX6224,WX6226,
WX6230,WX6232,WX6231,WX6233,WX6237,WX6239,WX6238,WX6240,WX6244,WX6246,
WX6245,WX6247,WX6251,WX6253,WX6252,WX6254,WX6258,WX6260,WX6259,WX6261,
WX6265,WX6267,WX6266,WX6268,WX6272,WX6274,WX6273,WX6275,WX6279,WX6281,
WX6280,WX6282,WX6286,WX6288,WX6287,WX6289,WX6293,WX6295,WX6294,WX6296,
WX6300,WX6302,WX6301,WX6303,WX6307,WX6309,WX6308,WX6310,WX6314,WX6316,
WX6315,WX6317,WX6321,WX6323,WX6322,WX6324,WX6328,WX6330,WX6329,WX6331,
WX6335,WX6337,WX6336,WX6338,WX6342,WX6344,WX6343,WX6345,WX6349,WX6351,
WX6350,WX6352,WX6356,WX6358,WX6357,WX6359,WX6363,WX6365,WX6364,WX6366,
WX6370,WX6372,WX6371,WX6373,WX6377,WX6379,WX6378,WX6380,WX6384,WX6386,
WX6385,WX6387,WX6391,WX6393,WX6392,WX6394,WX6398,WX6400,WX6399,WX6401,
WX6402,WX6435,WX6502,WX7468,WX6506,WX7469,WX6510,WX6512,WX6503,WX6513,
WX6516,WX6520,WX6524,WX6526,WX6517,WX6527,WX6530,WX6534,WX6538,WX6540,
WX6531,WX6541,WX6544,WX6548,WX6552,WX6554,WX6545,WX6555,WX6558,WX6562,
WX6566,WX6568,WX6559,WX6569,WX6572,WX6576,WX6580,WX6582,WX6573,WX6583,
WX6586,WX6590,WX6594,WX6596,WX6587,WX6597,WX6600,WX6604,WX6608,WX6610,
WX6601,WX6611,WX6614,WX6618,WX6622,WX6624,WX6615,WX6625,WX6628,WX6632,
WX6636,WX6638,WX6629,WX6639,WX6642,WX6646,WX6650,WX6652,WX6643,WX6653,
WX6656,WX6660,WX6664,WX6666,WX6657,WX6667,WX6670,WX6674,WX6678,WX6680,
WX6671,WX6681,WX6684,WX6688,WX6692,WX6694,WX6685,WX6695,WX6698,WX6702,
WX6706,WX6708,WX6699,WX6709,WX6712,WX6716,WX6720,WX6722,WX6713,WX6723,
WX6726,WX6730,WX6734,WX6736,WX6727,WX6737,WX6740,WX6744,WX6748,WX6750,
WX6741,WX6751,WX6754,WX6758,WX6762,WX6764,WX6755,WX6765,WX6768,WX6772,
WX6776,WX6778,WX6769,WX6779,WX6782,WX6786,WX6790,WX6792,WX6783,WX6793,
WX6796,WX6800,WX6804,WX6806,WX6797,WX6807,WX6810,WX6814,WX6818,WX6820,
WX6811,WX6821,WX6824,WX6828,WX6832,WX6834,WX6825,WX6835,WX6838,WX6842,
WX6846,WX6848,WX6839,WX6849,WX6852,WX6856,WX6860,WX6862,WX6853,WX6863,
WX6866,WX6870,WX6874,WX6876,WX6867,WX6877,WX6880,WX6884,WX6888,WX6890,
WX6881,WX6891,WX6894,WX6898,WX6902,WX6904,WX6895,WX6905,WX6908,WX6912,
WX6916,WX6918,WX6909,WX6919,WX6922,WX6926,WX6930,WX6932,WX6923,WX6933,
WX6936,WX6940,WX6944,WX6946,WX6937,WX6947,WX6948,WX7013,WX7430,WX7014,
WX7432,WX7015,WX7434,WX7016,WX7436,WX7017,WX7438,WX7018,WX7440,WX7019,
WX7442,WX7020,WX7444,WX7021,WX7446,WX7022,WX7448,WX7023,WX7450,WX7024,
WX7452,WX7025,WX7454,WX7026,WX7456,WX7027,WX7458,WX7028,WX7460,WX7029,
WX7398,WX7030,WX7400,WX7031,WX7402,WX7032,WX7404,WX7033,WX7406,WX7034,
WX7408,WX7035,WX7410,WX7036,WX7412,WX7037,WX7414,WX7038,WX7416,WX7039,
WX7418,WX7040,WX7420,WX7041,WX7422,WX7042,WX7424,WX7043,WX7426,WX7044,
WX7428,WX7045,WX7046,WX7047,WX7048,WX7049,WX7050,WX7051,WX7052,WX7053,
WX7054,WX7055,WX7056,WX7057,WX7058,WX7059,WX7060,WX7061,WX7062,WX7063,
WX7064,WX7065,WX7066,WX7067,WX7068,WX7069,WX7070,WX7071,WX7072,WX7073,
WX7074,WX7075,WX7076,WX7077,WX7078,WX7079,WX7080,WX7081,WX7082,WX7083,
WX7084,WX7085,WX7086,WX7087,WX7088,WX7089,WX7090,WX7091,WX7092,WX7093,
WX7094,WX7095,WX7096,WX7097,WX7098,WX7099,WX7100,WX7101,WX7102,WX7103,
WX7104,WX7105,WX7106,WX7107,WX7108,WX7397,WX7381,WX7399,WX7382,WX7401,
WX7383,WX7403,WX7384,WX7405,WX7385,WX7407,WX7386,WX7409,WX7387,WX7411,
WX7388,WX7413,WX7389,WX7415,WX7390,WX7417,WX7391,WX7419,WX7392,WX7421,
WX7393,WX7423,WX7394,WX7425,WX7395,WX7427,WX7396,WX7429,WX7365,WX7431,
WX7366,WX7433,WX7367,WX7435,WX7368,WX7437,WX7369,WX7439,WX7370,WX7441,
WX7371,WX7443,WX7372,WX7445,WX7373,WX7447,WX7374,WX7449,WX7375,WX7451,
WX7376,WX7453,WX7377,WX7455,WX7378,WX7457,WX7379,WX7459,WX7380,WX7461,
WX7462,WX7463,WX7464,WX7465,WX7466,WX7467,WX7470,WX7474,WX7476,WX7475,
WX7477,WX7481,WX7483,WX7482,WX7484,WX7488,WX7490,WX7489,WX7491,WX7495,
WX7497,WX7496,WX7498,WX7502,WX7504,WX7503,WX7505,WX7509,WX7511,WX7510,
WX7512,WX7516,WX7518,WX7517,WX7519,WX7523,WX7525,WX7524,WX7526,WX7530,
WX7532,WX7531,WX7533,WX7537,WX7539,WX7538,WX7540,WX7544,WX7546,WX7545,
WX7547,WX7551,WX7553,WX7552,WX7554,WX7558,WX7560,WX7559,WX7561,WX7565,
WX7567,WX7566,WX7568,WX7572,WX7574,WX7573,WX7575,WX7579,WX7581,WX7580,
WX7582,WX7586,WX7588,WX7587,WX7589,WX7593,WX7595,WX7594,WX7596,WX7600,
WX7602,WX7601,WX7603,WX7607,WX7609,WX7608,WX7610,WX7614,WX7616,WX7615,
WX7617,WX7621,WX7623,WX7622,WX7624,WX7628,WX7630,WX7629,WX7631,WX7635,
WX7637,WX7636,WX7638,WX7642,WX7644,WX7643,WX7645,WX7649,WX7651,WX7650,
WX7652,WX7656,WX7658,WX7657,WX7659,WX7663,WX7665,WX7664,WX7666,WX7670,
WX7672,WX7671,WX7673,WX7677,WX7679,WX7678,WX7680,WX7684,WX7686,WX7685,
WX7687,WX7691,WX7693,WX7692,WX7694,WX7695,WX7728,WX7795,WX8761,WX7799,
WX8762,WX7803,WX7805,WX7796,WX7806,WX7809,WX7813,WX7817,WX7819,WX7810,
WX7820,WX7823,WX7827,WX7831,WX7833,WX7824,WX7834,WX7837,WX7841,WX7845,
WX7847,WX7838,WX7848,WX7851,WX7855,WX7859,WX7861,WX7852,WX7862,WX7865,
WX7869,WX7873,WX7875,WX7866,WX7876,WX7879,WX7883,WX7887,WX7889,WX7880,
WX7890,WX7893,WX7897,WX7901,WX7903,WX7894,WX7904,WX7907,WX7911,WX7915,
WX7917,WX7908,WX7918,WX7921,WX7925,WX7929,WX7931,WX7922,WX7932,WX7935,
WX7939,WX7943,WX7945,WX7936,WX7946,WX7949,WX7953,WX7957,WX7959,WX7950,
WX7960,WX7963,WX7967,WX7971,WX7973,WX7964,WX7974,WX7977,WX7981,WX7985,
WX7987,WX7978,WX7988,WX7991,WX7995,WX7999,WX8001,WX7992,WX8002,WX8005,
WX8009,WX8013,WX8015,WX8006,WX8016,WX8019,WX8023,WX8027,WX8029,WX8020,
WX8030,WX8033,WX8037,WX8041,WX8043,WX8034,WX8044,WX8047,WX8051,WX8055,
WX8057,WX8048,WX8058,WX8061,WX8065,WX8069,WX8071,WX8062,WX8072,WX8075,
WX8079,WX8083,WX8085,WX8076,WX8086,WX8089,WX8093,WX8097,WX8099,WX8090,
WX8100,WX8103,WX8107,WX8111,WX8113,WX8104,WX8114,WX8117,WX8121,WX8125,
WX8127,WX8118,WX8128,WX8131,WX8135,WX8139,WX8141,WX8132,WX8142,WX8145,
WX8149,WX8153,WX8155,WX8146,WX8156,WX8159,WX8163,WX8167,WX8169,WX8160,
WX8170,WX8173,WX8177,WX8181,WX8183,WX8174,WX8184,WX8187,WX8191,WX8195,
WX8197,WX8188,WX8198,WX8201,WX8205,WX8209,WX8211,WX8202,WX8212,WX8215,
WX8219,WX8223,WX8225,WX8216,WX8226,WX8229,WX8233,WX8237,WX8239,WX8230,
WX8240,WX8241,WX8306,WX8723,WX8307,WX8725,WX8308,WX8727,WX8309,WX8729,
WX8310,WX8731,WX8311,WX8733,WX8312,WX8735,WX8313,WX8737,WX8314,WX8739,
WX8315,WX8741,WX8316,WX8743,WX8317,WX8745,WX8318,WX8747,WX8319,WX8749,
WX8320,WX8751,WX8321,WX8753,WX8322,WX8691,WX8323,WX8693,WX8324,WX8695,
WX8325,WX8697,WX8326,WX8699,WX8327,WX8701,WX8328,WX8703,WX8329,WX8705,
WX8330,WX8707,WX8331,WX8709,WX8332,WX8711,WX8333,WX8713,WX8334,WX8715,
WX8335,WX8717,WX8336,WX8719,WX8337,WX8721,WX8338,WX8339,WX8340,WX8341,
WX8342,WX8343,WX8344,WX8345,WX8346,WX8347,WX8348,WX8349,WX8350,WX8351,
WX8352,WX8353,WX8354,WX8355,WX8356,WX8357,WX8358,WX8359,WX8360,WX8361,
WX8362,WX8363,WX8364,WX8365,WX8366,WX8367,WX8368,WX8369,WX8370,WX8371,
WX8372,WX8373,WX8374,WX8375,WX8376,WX8377,WX8378,WX8379,WX8380,WX8381,
WX8382,WX8383,WX8384,WX8385,WX8386,WX8387,WX8388,WX8389,WX8390,WX8391,
WX8392,WX8393,WX8394,WX8395,WX8396,WX8397,WX8398,WX8399,WX8400,WX8401,
WX8690,WX8674,WX8692,WX8675,WX8694,WX8676,WX8696,WX8677,WX8698,WX8678,
WX8700,WX8679,WX8702,WX8680,WX8704,WX8681,WX8706,WX8682,WX8708,WX8683,
WX8710,WX8684,WX8712,WX8685,WX8714,WX8686,WX8716,WX8687,WX8718,WX8688,
WX8720,WX8689,WX8722,WX8658,WX8724,WX8659,WX8726,WX8660,WX8728,WX8661,
WX8730,WX8662,WX8732,WX8663,WX8734,WX8664,WX8736,WX8665,WX8738,WX8666,
WX8740,WX8667,WX8742,WX8668,WX8744,WX8669,WX8746,WX8670,WX8748,WX8671,
WX8750,WX8672,WX8752,WX8673,WX8754,WX8755,WX8756,WX8757,WX8758,WX8759,
WX8760,WX8763,WX8767,WX8769,WX8768,WX8770,WX8774,WX8776,WX8775,WX8777,
WX8781,WX8783,WX8782,WX8784,WX8788,WX8790,WX8789,WX8791,WX8795,WX8797,
WX8796,WX8798,WX8802,WX8804,WX8803,WX8805,WX8809,WX8811,WX8810,WX8812,
WX8816,WX8818,WX8817,WX8819,WX8823,WX8825,WX8824,WX8826,WX8830,WX8832,
WX8831,WX8833,WX8837,WX8839,WX8838,WX8840,WX8844,WX8846,WX8845,WX8847,
WX8851,WX8853,WX8852,WX8854,WX8858,WX8860,WX8859,WX8861,WX8865,WX8867,
WX8866,WX8868,WX8872,WX8874,WX8873,WX8875,WX8879,WX8881,WX8880,WX8882,
WX8886,WX8888,WX8887,WX8889,WX8893,WX8895,WX8894,WX8896,WX8900,WX8902,
WX8901,WX8903,WX8907,WX8909,WX8908,WX8910,WX8914,WX8916,WX8915,WX8917,
WX8921,WX8923,WX8922,WX8924,WX8928,WX8930,WX8929,WX8931,WX8935,WX8937,
WX8936,WX8938,WX8942,WX8944,WX8943,WX8945,WX8949,WX8951,WX8950,WX8952,
WX8956,WX8958,WX8957,WX8959,WX8963,WX8965,WX8964,WX8966,WX8970,WX8972,
WX8971,WX8973,WX8977,WX8979,WX8978,WX8980,WX8984,WX8986,WX8985,WX8987,
WX8988,WX9021,WX9088,WX10054,WX9092,WX10055,WX9096,WX9098,WX9089,WX9099,
WX9102,WX9106,WX9110,WX9112,WX9103,WX9113,WX9116,WX9120,WX9124,WX9126,
WX9117,WX9127,WX9130,WX9134,WX9138,WX9140,WX9131,WX9141,WX9144,WX9148,
WX9152,WX9154,WX9145,WX9155,WX9158,WX9162,WX9166,WX9168,WX9159,WX9169,
WX9172,WX9176,WX9180,WX9182,WX9173,WX9183,WX9186,WX9190,WX9194,WX9196,
WX9187,WX9197,WX9200,WX9204,WX9208,WX9210,WX9201,WX9211,WX9214,WX9218,
WX9222,WX9224,WX9215,WX9225,WX9228,WX9232,WX9236,WX9238,WX9229,WX9239,
WX9242,WX9246,WX9250,WX9252,WX9243,WX9253,WX9256,WX9260,WX9264,WX9266,
WX9257,WX9267,WX9270,WX9274,WX9278,WX9280,WX9271,WX9281,WX9284,WX9288,
WX9292,WX9294,WX9285,WX9295,WX9298,WX9302,WX9306,WX9308,WX9299,WX9309,
WX9312,WX9316,WX9320,WX9322,WX9313,WX9323,WX9326,WX9330,WX9334,WX9336,
WX9327,WX9337,WX9340,WX9344,WX9348,WX9350,WX9341,WX9351,WX9354,WX9358,
WX9362,WX9364,WX9355,WX9365,WX9368,WX9372,WX9376,WX9378,WX9369,WX9379,
WX9382,WX9386,WX9390,WX9392,WX9383,WX9393,WX9396,WX9400,WX9404,WX9406,
WX9397,WX9407,WX9410,WX9414,WX9418,WX9420,WX9411,WX9421,WX9424,WX9428,
WX9432,WX9434,WX9425,WX9435,WX9438,WX9442,WX9446,WX9448,WX9439,WX9449,
WX9452,WX9456,WX9460,WX9462,WX9453,WX9463,WX9466,WX9470,WX9474,WX9476,
WX9467,WX9477,WX9480,WX9484,WX9488,WX9490,WX9481,WX9491,WX9494,WX9498,
WX9502,WX9504,WX9495,WX9505,WX9508,WX9512,WX9516,WX9518,WX9509,WX9519,
WX9522,WX9526,WX9530,WX9532,WX9523,WX9533,WX9534,WX9599,WX10016,WX9600,
WX10018,WX9601,WX10020,WX9602,WX10022,WX9603,WX10024,WX9604,WX10026,WX9605,
WX10028,WX9606,WX10030,WX9607,WX10032,WX9608,WX10034,WX9609,WX10036,WX9610,
WX10038,WX9611,WX10040,WX9612,WX10042,WX9613,WX10044,WX9614,WX10046,WX9615,
WX9984,WX9616,WX9986,WX9617,WX9988,WX9618,WX9990,WX9619,WX9992,WX9620,
WX9994,WX9621,WX9996,WX9622,WX9998,WX9623,WX10000,WX9624,WX10002,WX9625,
WX10004,WX9626,WX10006,WX9627,WX10008,WX9628,WX10010,WX9629,WX10012,WX9630,
WX10014,WX9631,WX9632,WX9633,WX9634,WX9635,WX9636,WX9637,WX9638,WX9639,
WX9640,WX9641,WX9642,WX9643,WX9644,WX9645,WX9646,WX9647,WX9648,WX9649,
WX9650,WX9651,WX9652,WX9653,WX9654,WX9655,WX9656,WX9657,WX9658,WX9659,
WX9660,WX9661,WX9662,WX9663,WX9664,WX9665,WX9666,WX9667,WX9668,WX9669,
WX9670,WX9671,WX9672,WX9673,WX9674,WX9675,WX9676,WX9677,WX9678,WX9679,
WX9680,WX9681,WX9682,WX9683,WX9684,WX9685,WX9686,WX9687,WX9688,WX9689,
WX9690,WX9691,WX9692,WX9693,WX9694,WX9983,WX9967,WX9985,WX9968,WX9987,
WX9969,WX9989,WX9970,WX9991,WX9971,WX9993,WX9972,WX9995,WX9973,WX9997,
WX9974,WX9999,WX9975,WX10001,WX9976,WX10003,WX9977,WX10005,WX9978,WX10007,
WX9979,WX10009,WX9980,WX10011,WX9981,WX10013,WX9982,WX10015,WX9951,WX10017,
WX9952,WX10019,WX9953,WX10021,WX9954,WX10023,WX9955,WX10025,WX9956,WX10027,
WX9957,WX10029,WX9958,WX10031,WX9959,WX10033,WX9960,WX10035,WX9961,WX10037,
WX9962,WX10039,WX9963,WX10041,WX9964,WX10043,WX9965,WX10045,WX9966,WX10047,
WX10048,WX10049,WX10050,WX10051,WX10052,WX10053,WX10056,WX10060,WX10062,
WX10061,WX10063,WX10067,WX10069,WX10068,WX10070,WX10074,WX10076,WX10075,
WX10077,WX10081,WX10083,WX10082,WX10084,WX10088,WX10090,WX10089,WX10091,
WX10095,WX10097,WX10096,WX10098,WX10102,WX10104,WX10103,WX10105,WX10109,
WX10111,WX10110,WX10112,WX10116,WX10118,WX10117,WX10119,WX10123,WX10125,
WX10124,WX10126,WX10130,WX10132,WX10131,WX10133,WX10137,WX10139,WX10138,
WX10140,WX10144,WX10146,WX10145,WX10147,WX10151,WX10153,WX10152,WX10154,
WX10158,WX10160,WX10159,WX10161,WX10165,WX10167,WX10166,WX10168,WX10172,
WX10174,WX10173,WX10175,WX10179,WX10181,WX10180,WX10182,WX10186,WX10188,
WX10187,WX10189,WX10193,WX10195,WX10194,WX10196,WX10200,WX10202,WX10201,
WX10203,WX10207,WX10209,WX10208,WX10210,WX10214,WX10216,WX10215,WX10217,
WX10221,WX10223,WX10222,WX10224,WX10228,WX10230,WX10229,WX10231,WX10235,
WX10237,WX10236,WX10238,WX10242,WX10244,WX10243,WX10245,WX10249,WX10251,
WX10250,WX10252,WX10256,WX10258,WX10257,WX10259,WX10263,WX10265,WX10264,
WX10266,WX10270,WX10272,WX10271,WX10273,WX10277,WX10279,WX10278,WX10280,
WX10281,WX10314,WX10381,WX11347,WX10385,WX11348,WX10389,WX10391,WX10382,
WX10392,WX10395,WX10399,WX10403,WX10405,WX10396,WX10406,WX10409,WX10413,
WX10417,WX10419,WX10410,WX10420,WX10423,WX10427,WX10431,WX10433,WX10424,
WX10434,WX10437,WX10441,WX10445,WX10447,WX10438,WX10448,WX10451,WX10455,
WX10459,WX10461,WX10452,WX10462,WX10465,WX10469,WX10473,WX10475,WX10466,
WX10476,WX10479,WX10483,WX10487,WX10489,WX10480,WX10490,WX10493,WX10497,
WX10501,WX10503,WX10494,WX10504,WX10507,WX10511,WX10515,WX10517,WX10508,
WX10518,WX10521,WX10525,WX10529,WX10531,WX10522,WX10532,WX10535,WX10539,
WX10543,WX10545,WX10536,WX10546,WX10549,WX10553,WX10557,WX10559,WX10550,
WX10560,WX10563,WX10567,WX10571,WX10573,WX10564,WX10574,WX10577,WX10581,
WX10585,WX10587,WX10578,WX10588,WX10591,WX10595,WX10599,WX10601,WX10592,
WX10602,WX10605,WX10609,WX10613,WX10615,WX10606,WX10616,WX10619,WX10623,
WX10627,WX10629,WX10620,WX10630,WX10633,WX10637,WX10641,WX10643,WX10634,
WX10644,WX10647,WX10651,WX10655,WX10657,WX10648,WX10658,WX10661,WX10665,
WX10669,WX10671,WX10662,WX10672,WX10675,WX10679,WX10683,WX10685,WX10676,
WX10686,WX10689,WX10693,WX10697,WX10699,WX10690,WX10700,WX10703,WX10707,
WX10711,WX10713,WX10704,WX10714,WX10717,WX10721,WX10725,WX10727,WX10718,
WX10728,WX10731,WX10735,WX10739,WX10741,WX10732,WX10742,WX10745,WX10749,
WX10753,WX10755,WX10746,WX10756,WX10759,WX10763,WX10767,WX10769,WX10760,
WX10770,WX10773,WX10777,WX10781,WX10783,WX10774,WX10784,WX10787,WX10791,
WX10795,WX10797,WX10788,WX10798,WX10801,WX10805,WX10809,WX10811,WX10802,
WX10812,WX10815,WX10819,WX10823,WX10825,WX10816,WX10826,WX10827,WX10892,
WX11309,WX10893,WX11311,WX10894,WX11313,WX10895,WX11315,WX10896,WX11317,
WX10897,WX11319,WX10898,WX11321,WX10899,WX11323,WX10900,WX11325,WX10901,
WX11327,WX10902,WX11329,WX10903,WX11331,WX10904,WX11333,WX10905,WX11335,
WX10906,WX11337,WX10907,WX11339,WX10908,WX11277,WX10909,WX11279,WX10910,
WX11281,WX10911,WX11283,WX10912,WX11285,WX10913,WX11287,WX10914,WX11289,
WX10915,WX11291,WX10916,WX11293,WX10917,WX11295,WX10918,WX11297,WX10919,
WX11299,WX10920,WX11301,WX10921,WX11303,WX10922,WX11305,WX10923,WX11307,
WX10924,WX10925,WX10926,WX10927,WX10928,WX10929,WX10930,WX10931,WX10932,
WX10933,WX10934,WX10935,WX10936,WX10937,WX10938,WX10939,WX10940,WX10941,
WX10942,WX10943,WX10944,WX10945,WX10946,WX10947,WX10948,WX10949,WX10950,
WX10951,WX10952,WX10953,WX10954,WX10955,WX10956,WX10957,WX10958,WX10959,
WX10960,WX10961,WX10962,WX10963,WX10964,WX10965,WX10966,WX10967,WX10968,
WX10969,WX10970,WX10971,WX10972,WX10973,WX10974,WX10975,WX10976,WX10977,
WX10978,WX10979,WX10980,WX10981,WX10982,WX10983,WX10984,WX10985,WX10986,
WX10987,WX11276,WX11260,WX11278,WX11261,WX11280,WX11262,WX11282,WX11263,
WX11284,WX11264,WX11286,WX11265,WX11288,WX11266,WX11290,WX11267,WX11292,
WX11268,WX11294,WX11269,WX11296,WX11270,WX11298,WX11271,WX11300,WX11272,
WX11302,WX11273,WX11304,WX11274,WX11306,WX11275,WX11308,WX11244,WX11310,
WX11245,WX11312,WX11246,WX11314,WX11247,WX11316,WX11248,WX11318,WX11249,
WX11320,WX11250,WX11322,WX11251,WX11324,WX11252,WX11326,WX11253,WX11328,
WX11254,WX11330,WX11255,WX11332,WX11256,WX11334,WX11257,WX11336,WX11258,
WX11338,WX11259,WX11340,WX11341,WX11342,WX11343,WX11344,WX11345,WX11346,
WX11349,WX11353,WX11355,WX11354,WX11356,WX11360,WX11362,WX11361,WX11363,
WX11367,WX11369,WX11368,WX11370,WX11374,WX11376,WX11375,WX11377,WX11381,
WX11383,WX11382,WX11384,WX11388,WX11390,WX11389,WX11391,WX11395,WX11397,
WX11396,WX11398,WX11402,WX11404,WX11403,WX11405,WX11409,WX11411,WX11410,
WX11412,WX11416,WX11418,WX11417,WX11419,WX11423,WX11425,WX11424,WX11426,
WX11430,WX11432,WX11431,WX11433,WX11437,WX11439,WX11438,WX11440,WX11444,
WX11446,WX11445,WX11447,WX11451,WX11453,WX11452,WX11454,WX11458,WX11460,
WX11459,WX11461,WX11465,WX11467,WX11466,WX11468,WX11472,WX11474,WX11473,
WX11475,WX11479,WX11481,WX11480,WX11482,WX11486,WX11488,WX11487,WX11489,
WX11493,WX11495,WX11494,WX11496,WX11500,WX11502,WX11501,WX11503,WX11507,
WX11509,WX11508,WX11510,WX11514,WX11516,WX11515,WX11517,WX11521,WX11523,
WX11522,WX11524,WX11528,WX11530,WX11529,WX11531,WX11535,WX11537,WX11536,
WX11538,WX11542,WX11544,WX11543,WX11545,WX11549,WX11551,WX11550,WX11552,
WX11556,WX11558,WX11557,WX11559,WX11563,WX11565,WX11564,WX11566,WX11570,
WX11572,WX11571,WX11573,WX11574,WX11607,WX35,WX46,WX36,WX42,WX39,WX40,WX43,
WX44,WX49,WX60,WX50,WX56,WX53,WX54,WX57,WX58,WX63,WX74,WX64,WX70,WX67,WX68,
WX71,WX72,WX77,WX88,WX78,WX84,WX81,WX82,WX85,WX86,WX91,WX102,WX92,WX98,
WX95,WX96,WX99,WX100,WX105,WX116,WX106,WX112,WX109,WX110,WX113,WX114,WX119,
WX130,WX120,WX126,WX123,WX124,WX127,WX128,WX133,WX144,WX134,WX140,WX137,
WX138,WX141,WX142,WX147,WX158,WX148,WX154,WX151,WX152,WX155,WX156,WX161,
WX172,WX162,WX168,WX165,WX166,WX169,WX170,WX175,WX186,WX176,WX182,WX179,
WX180,WX183,WX184,WX189,WX200,WX190,WX196,WX193,WX194,WX197,WX198,WX203,
WX214,WX204,WX210,WX207,WX208,WX211,WX212,WX217,WX228,WX218,WX224,WX221,
WX222,WX225,WX226,WX231,WX242,WX232,WX238,WX235,WX236,WX239,WX240,WX245,
WX256,WX246,WX252,WX249,WX250,WX253,WX254,WX259,WX270,WX260,WX266,WX263,
WX264,WX267,WX268,WX273,WX284,WX274,WX280,WX277,WX278,WX281,WX282,WX287,
WX298,WX288,WX294,WX291,WX292,WX295,WX296,WX301,WX312,WX302,WX308,WX305,
WX306,WX309,WX310,WX315,WX326,WX316,WX322,WX319,WX320,WX323,WX324,WX329,
WX340,WX330,WX336,WX333,WX334,WX337,WX338,WX343,WX354,WX344,WX350,WX347,
WX348,WX351,WX352,WX357,WX368,WX358,WX364,WX361,WX362,WX365,WX366,WX371,
WX382,WX372,WX378,WX375,WX376,WX379,WX380,WX385,WX396,WX386,WX392,WX389,
WX390,WX393,WX394,WX399,WX410,WX400,WX406,WX403,WX404,WX407,WX408,WX413,
WX424,WX414,WX420,WX417,WX418,WX421,WX422,WX427,WX438,WX428,WX434,WX431,
WX432,WX435,WX436,WX441,WX452,WX442,WX448,WX445,WX446,WX449,WX450,WX455,
WX466,WX456,WX462,WX459,WX460,WX463,WX464,WX469,WX480,WX470,WX476,WX473,
WX474,WX477,WX478,WX1007,WX1006,WX1008,WX1014,WX1013,WX1015,WX1021,WX1020,
WX1022,WX1028,WX1027,WX1029,WX1035,WX1034,WX1036,WX1042,WX1041,WX1043,
WX1049,WX1048,WX1050,WX1056,WX1055,WX1057,WX1063,WX1062,WX1064,WX1070,
WX1069,WX1071,WX1077,WX1076,WX1078,WX1084,WX1083,WX1085,WX1091,WX1090,
WX1092,WX1098,WX1097,WX1099,WX1105,WX1104,WX1106,WX1112,WX1111,WX1113,
WX1119,WX1118,WX1120,WX1126,WX1125,WX1127,WX1133,WX1132,WX1134,WX1140,
WX1139,WX1141,WX1147,WX1146,WX1148,WX1154,WX1153,WX1155,WX1161,WX1160,
WX1162,WX1168,WX1167,WX1169,WX1175,WX1174,WX1176,WX1182,WX1181,WX1183,
WX1189,WX1188,WX1190,WX1196,WX1195,WX1197,WX1203,WX1202,WX1204,WX1210,
WX1209,WX1211,WX1217,WX1216,WX1218,WX1224,WX1223,WX1225,WX1234,WX1262,
WX1261,WX1260,WX1233,WX1259,WX1258,WX1257,WX1256,WX1255,WX1254,WX1232,
WX1253,WX1252,WX1251,WX1250,WX1231,WX1249,WX1248,WX1247,WX1246,WX1245,
WX1244,WX1243,WX1242,WX1241,WX1240,WX1239,WX1238,WX1237,WX1236,WX1235,
WX1328,WX1339,WX1329,WX1335,WX1332,WX1333,WX1336,WX1337,WX1342,WX1353,
WX1343,WX1349,WX1346,WX1347,WX1350,WX1351,WX1356,WX1367,WX1357,WX1363,
WX1360,WX1361,WX1364,WX1365,WX1370,WX1381,WX1371,WX1377,WX1374,WX1375,
WX1378,WX1379,WX1384,WX1395,WX1385,WX1391,WX1388,WX1389,WX1392,WX1393,
WX1398,WX1409,WX1399,WX1405,WX1402,WX1403,WX1406,WX1407,WX1412,WX1423,
WX1413,WX1419,WX1416,WX1417,WX1420,WX1421,WX1426,WX1437,WX1427,WX1433,
WX1430,WX1431,WX1434,WX1435,WX1440,WX1451,WX1441,WX1447,WX1444,WX1445,
WX1448,WX1449,WX1454,WX1465,WX1455,WX1461,WX1458,WX1459,WX1462,WX1463,
WX1468,WX1479,WX1469,WX1475,WX1472,WX1473,WX1476,WX1477,WX1482,WX1493,
WX1483,WX1489,WX1486,WX1487,WX1490,WX1491,WX1496,WX1507,WX1497,WX1503,
WX1500,WX1501,WX1504,WX1505,WX1510,WX1521,WX1511,WX1517,WX1514,WX1515,
WX1518,WX1519,WX1524,WX1535,WX1525,WX1531,WX1528,WX1529,WX1532,WX1533,
WX1538,WX1549,WX1539,WX1545,WX1542,WX1543,WX1546,WX1547,WX1552,WX1563,
WX1553,WX1559,WX1556,WX1557,WX1560,WX1561,WX1566,WX1577,WX1567,WX1573,
WX1570,WX1571,WX1574,WX1575,WX1580,WX1591,WX1581,WX1587,WX1584,WX1585,
WX1588,WX1589,WX1594,WX1605,WX1595,WX1601,WX1598,WX1599,WX1602,WX1603,
WX1608,WX1619,WX1609,WX1615,WX1612,WX1613,WX1616,WX1617,WX1622,WX1633,
WX1623,WX1629,WX1626,WX1627,WX1630,WX1631,WX1636,WX1647,WX1637,WX1643,
WX1640,WX1641,WX1644,WX1645,WX1650,WX1661,WX1651,WX1657,WX1654,WX1655,
WX1658,WX1659,WX1664,WX1675,WX1665,WX1671,WX1668,WX1669,WX1672,WX1673,
WX1678,WX1689,WX1679,WX1685,WX1682,WX1683,WX1686,WX1687,WX1692,WX1703,
WX1693,WX1699,WX1696,WX1697,WX1700,WX1701,WX1706,WX1717,WX1707,WX1713,
WX1710,WX1711,WX1714,WX1715,WX1720,WX1731,WX1721,WX1727,WX1724,WX1725,
WX1728,WX1729,WX1734,WX1745,WX1735,WX1741,WX1738,WX1739,WX1742,WX1743,
WX1748,WX1759,WX1749,WX1755,WX1752,WX1753,WX1756,WX1757,WX1762,WX1773,
WX1763,WX1769,WX1766,WX1767,WX1770,WX1771,WX2300,WX2299,WX2301,WX2307,
WX2306,WX2308,WX2314,WX2313,WX2315,WX2321,WX2320,WX2322,WX2328,WX2327,
WX2329,WX2335,WX2334,WX2336,WX2342,WX2341,WX2343,WX2349,WX2348,WX2350,
WX2356,WX2355,WX2357,WX2363,WX2362,WX2364,WX2370,WX2369,WX2371,WX2377,
WX2376,WX2378,WX2384,WX2383,WX2385,WX2391,WX2390,WX2392,WX2398,WX2397,
WX2399,WX2405,WX2404,WX2406,WX2412,WX2411,WX2413,WX2419,WX2418,WX2420,
WX2426,WX2425,WX2427,WX2433,WX2432,WX2434,WX2440,WX2439,WX2441,WX2447,
WX2446,WX2448,WX2454,WX2453,WX2455,WX2461,WX2460,WX2462,WX2468,WX2467,
WX2469,WX2475,WX2474,WX2476,WX2482,WX2481,WX2483,WX2489,WX2488,WX2490,
WX2496,WX2495,WX2497,WX2503,WX2502,WX2504,WX2510,WX2509,WX2511,WX2517,
WX2516,WX2518,WX2527,WX2555,WX2554,WX2553,WX2526,WX2552,WX2551,WX2550,
WX2549,WX2548,WX2547,WX2525,WX2546,WX2545,WX2544,WX2543,WX2524,WX2542,
WX2541,WX2540,WX2539,WX2538,WX2537,WX2536,WX2535,WX2534,WX2533,WX2532,
WX2531,WX2530,WX2529,WX2528,WX2621,WX2632,WX2622,WX2628,WX2625,WX2626,
WX2629,WX2630,WX2635,WX2646,WX2636,WX2642,WX2639,WX2640,WX2643,WX2644,
WX2649,WX2660,WX2650,WX2656,WX2653,WX2654,WX2657,WX2658,WX2663,WX2674,
WX2664,WX2670,WX2667,WX2668,WX2671,WX2672,WX2677,WX2688,WX2678,WX2684,
WX2681,WX2682,WX2685,WX2686,WX2691,WX2702,WX2692,WX2698,WX2695,WX2696,
WX2699,WX2700,WX2705,WX2716,WX2706,WX2712,WX2709,WX2710,WX2713,WX2714,
WX2719,WX2730,WX2720,WX2726,WX2723,WX2724,WX2727,WX2728,WX2733,WX2744,
WX2734,WX2740,WX2737,WX2738,WX2741,WX2742,WX2747,WX2758,WX2748,WX2754,
WX2751,WX2752,WX2755,WX2756,WX2761,WX2772,WX2762,WX2768,WX2765,WX2766,
WX2769,WX2770,WX2775,WX2786,WX2776,WX2782,WX2779,WX2780,WX2783,WX2784,
WX2789,WX2800,WX2790,WX2796,WX2793,WX2794,WX2797,WX2798,WX2803,WX2814,
WX2804,WX2810,WX2807,WX2808,WX2811,WX2812,WX2817,WX2828,WX2818,WX2824,
WX2821,WX2822,WX2825,WX2826,WX2831,WX2842,WX2832,WX2838,WX2835,WX2836,
WX2839,WX2840,WX2845,WX2856,WX2846,WX2852,WX2849,WX2850,WX2853,WX2854,
WX2859,WX2870,WX2860,WX2866,WX2863,WX2864,WX2867,WX2868,WX2873,WX2884,
WX2874,WX2880,WX2877,WX2878,WX2881,WX2882,WX2887,WX2898,WX2888,WX2894,
WX2891,WX2892,WX2895,WX2896,WX2901,WX2912,WX2902,WX2908,WX2905,WX2906,
WX2909,WX2910,WX2915,WX2926,WX2916,WX2922,WX2919,WX2920,WX2923,WX2924,
WX2929,WX2940,WX2930,WX2936,WX2933,WX2934,WX2937,WX2938,WX2943,WX2954,
WX2944,WX2950,WX2947,WX2948,WX2951,WX2952,WX2957,WX2968,WX2958,WX2964,
WX2961,WX2962,WX2965,WX2966,WX2971,WX2982,WX2972,WX2978,WX2975,WX2976,
WX2979,WX2980,WX2985,WX2996,WX2986,WX2992,WX2989,WX2990,WX2993,WX2994,
WX2999,WX3010,WX3000,WX3006,WX3003,WX3004,WX3007,WX3008,WX3013,WX3024,
WX3014,WX3020,WX3017,WX3018,WX3021,WX3022,WX3027,WX3038,WX3028,WX3034,
WX3031,WX3032,WX3035,WX3036,WX3041,WX3052,WX3042,WX3048,WX3045,WX3046,
WX3049,WX3050,WX3055,WX3066,WX3056,WX3062,WX3059,WX3060,WX3063,WX3064,
WX3593,WX3592,WX3594,WX3600,WX3599,WX3601,WX3607,WX3606,WX3608,WX3614,
WX3613,WX3615,WX3621,WX3620,WX3622,WX3628,WX3627,WX3629,WX3635,WX3634,
WX3636,WX3642,WX3641,WX3643,WX3649,WX3648,WX3650,WX3656,WX3655,WX3657,
WX3663,WX3662,WX3664,WX3670,WX3669,WX3671,WX3677,WX3676,WX3678,WX3684,
WX3683,WX3685,WX3691,WX3690,WX3692,WX3698,WX3697,WX3699,WX3705,WX3704,
WX3706,WX3712,WX3711,WX3713,WX3719,WX3718,WX3720,WX3726,WX3725,WX3727,
WX3733,WX3732,WX3734,WX3740,WX3739,WX3741,WX3747,WX3746,WX3748,WX3754,
WX3753,WX3755,WX3761,WX3760,WX3762,WX3768,WX3767,WX3769,WX3775,WX3774,
WX3776,WX3782,WX3781,WX3783,WX3789,WX3788,WX3790,WX3796,WX3795,WX3797,
WX3803,WX3802,WX3804,WX3810,WX3809,WX3811,WX3820,WX3848,WX3847,WX3846,
WX3819,WX3845,WX3844,WX3843,WX3842,WX3841,WX3840,WX3818,WX3839,WX3838,
WX3837,WX3836,WX3817,WX3835,WX3834,WX3833,WX3832,WX3831,WX3830,WX3829,
WX3828,WX3827,WX3826,WX3825,WX3824,WX3823,WX3822,WX3821,WX3914,WX3925,
WX3915,WX3921,WX3918,WX3919,WX3922,WX3923,WX3928,WX3939,WX3929,WX3935,
WX3932,WX3933,WX3936,WX3937,WX3942,WX3953,WX3943,WX3949,WX3946,WX3947,
WX3950,WX3951,WX3956,WX3967,WX3957,WX3963,WX3960,WX3961,WX3964,WX3965,
WX3970,WX3981,WX3971,WX3977,WX3974,WX3975,WX3978,WX3979,WX3984,WX3995,
WX3985,WX3991,WX3988,WX3989,WX3992,WX3993,WX3998,WX4009,WX3999,WX4005,
WX4002,WX4003,WX4006,WX4007,WX4012,WX4023,WX4013,WX4019,WX4016,WX4017,
WX4020,WX4021,WX4026,WX4037,WX4027,WX4033,WX4030,WX4031,WX4034,WX4035,
WX4040,WX4051,WX4041,WX4047,WX4044,WX4045,WX4048,WX4049,WX4054,WX4065,
WX4055,WX4061,WX4058,WX4059,WX4062,WX4063,WX4068,WX4079,WX4069,WX4075,
WX4072,WX4073,WX4076,WX4077,WX4082,WX4093,WX4083,WX4089,WX4086,WX4087,
WX4090,WX4091,WX4096,WX4107,WX4097,WX4103,WX4100,WX4101,WX4104,WX4105,
WX4110,WX4121,WX4111,WX4117,WX4114,WX4115,WX4118,WX4119,WX4124,WX4135,
WX4125,WX4131,WX4128,WX4129,WX4132,WX4133,WX4138,WX4149,WX4139,WX4145,
WX4142,WX4143,WX4146,WX4147,WX4152,WX4163,WX4153,WX4159,WX4156,WX4157,
WX4160,WX4161,WX4166,WX4177,WX4167,WX4173,WX4170,WX4171,WX4174,WX4175,
WX4180,WX4191,WX4181,WX4187,WX4184,WX4185,WX4188,WX4189,WX4194,WX4205,
WX4195,WX4201,WX4198,WX4199,WX4202,WX4203,WX4208,WX4219,WX4209,WX4215,
WX4212,WX4213,WX4216,WX4217,WX4222,WX4233,WX4223,WX4229,WX4226,WX4227,
WX4230,WX4231,WX4236,WX4247,WX4237,WX4243,WX4240,WX4241,WX4244,WX4245,
WX4250,WX4261,WX4251,WX4257,WX4254,WX4255,WX4258,WX4259,WX4264,WX4275,
WX4265,WX4271,WX4268,WX4269,WX4272,WX4273,WX4278,WX4289,WX4279,WX4285,
WX4282,WX4283,WX4286,WX4287,WX4292,WX4303,WX4293,WX4299,WX4296,WX4297,
WX4300,WX4301,WX4306,WX4317,WX4307,WX4313,WX4310,WX4311,WX4314,WX4315,
WX4320,WX4331,WX4321,WX4327,WX4324,WX4325,WX4328,WX4329,WX4334,WX4345,
WX4335,WX4341,WX4338,WX4339,WX4342,WX4343,WX4348,WX4359,WX4349,WX4355,
WX4352,WX4353,WX4356,WX4357,WX4886,WX4885,WX4887,WX4893,WX4892,WX4894,
WX4900,WX4899,WX4901,WX4907,WX4906,WX4908,WX4914,WX4913,WX4915,WX4921,
WX4920,WX4922,WX4928,WX4927,WX4929,WX4935,WX4934,WX4936,WX4942,WX4941,
WX4943,WX4949,WX4948,WX4950,WX4956,WX4955,WX4957,WX4963,WX4962,WX4964,
WX4970,WX4969,WX4971,WX4977,WX4976,WX4978,WX4984,WX4983,WX4985,WX4991,
WX4990,WX4992,WX4998,WX4997,WX4999,WX5005,WX5004,WX5006,WX5012,WX5011,
WX5013,WX5019,WX5018,WX5020,WX5026,WX5025,WX5027,WX5033,WX5032,WX5034,
WX5040,WX5039,WX5041,WX5047,WX5046,WX5048,WX5054,WX5053,WX5055,WX5061,
WX5060,WX5062,WX5068,WX5067,WX5069,WX5075,WX5074,WX5076,WX5082,WX5081,
WX5083,WX5089,WX5088,WX5090,WX5096,WX5095,WX5097,WX5103,WX5102,WX5104,
WX5113,WX5141,WX5140,WX5139,WX5112,WX5138,WX5137,WX5136,WX5135,WX5134,
WX5133,WX5111,WX5132,WX5131,WX5130,WX5129,WX5110,WX5128,WX5127,WX5126,
WX5125,WX5124,WX5123,WX5122,WX5121,WX5120,WX5119,WX5118,WX5117,WX5116,
WX5115,WX5114,WX5207,WX5218,WX5208,WX5214,WX5211,WX5212,WX5215,WX5216,
WX5221,WX5232,WX5222,WX5228,WX5225,WX5226,WX5229,WX5230,WX5235,WX5246,
WX5236,WX5242,WX5239,WX5240,WX5243,WX5244,WX5249,WX5260,WX5250,WX5256,
WX5253,WX5254,WX5257,WX5258,WX5263,WX5274,WX5264,WX5270,WX5267,WX5268,
WX5271,WX5272,WX5277,WX5288,WX5278,WX5284,WX5281,WX5282,WX5285,WX5286,
WX5291,WX5302,WX5292,WX5298,WX5295,WX5296,WX5299,WX5300,WX5305,WX5316,
WX5306,WX5312,WX5309,WX5310,WX5313,WX5314,WX5319,WX5330,WX5320,WX5326,
WX5323,WX5324,WX5327,WX5328,WX5333,WX5344,WX5334,WX5340,WX5337,WX5338,
WX5341,WX5342,WX5347,WX5358,WX5348,WX5354,WX5351,WX5352,WX5355,WX5356,
WX5361,WX5372,WX5362,WX5368,WX5365,WX5366,WX5369,WX5370,WX5375,WX5386,
WX5376,WX5382,WX5379,WX5380,WX5383,WX5384,WX5389,WX5400,WX5390,WX5396,
WX5393,WX5394,WX5397,WX5398,WX5403,WX5414,WX5404,WX5410,WX5407,WX5408,
WX5411,WX5412,WX5417,WX5428,WX5418,WX5424,WX5421,WX5422,WX5425,WX5426,
WX5431,WX5442,WX5432,WX5438,WX5435,WX5436,WX5439,WX5440,WX5445,WX5456,
WX5446,WX5452,WX5449,WX5450,WX5453,WX5454,WX5459,WX5470,WX5460,WX5466,
WX5463,WX5464,WX5467,WX5468,WX5473,WX5484,WX5474,WX5480,WX5477,WX5478,
WX5481,WX5482,WX5487,WX5498,WX5488,WX5494,WX5491,WX5492,WX5495,WX5496,
WX5501,WX5512,WX5502,WX5508,WX5505,WX5506,WX5509,WX5510,WX5515,WX5526,
WX5516,WX5522,WX5519,WX5520,WX5523,WX5524,WX5529,WX5540,WX5530,WX5536,
WX5533,WX5534,WX5537,WX5538,WX5543,WX5554,WX5544,WX5550,WX5547,WX5548,
WX5551,WX5552,WX5557,WX5568,WX5558,WX5564,WX5561,WX5562,WX5565,WX5566,
WX5571,WX5582,WX5572,WX5578,WX5575,WX5576,WX5579,WX5580,WX5585,WX5596,
WX5586,WX5592,WX5589,WX5590,WX5593,WX5594,WX5599,WX5610,WX5600,WX5606,
WX5603,WX5604,WX5607,WX5608,WX5613,WX5624,WX5614,WX5620,WX5617,WX5618,
WX5621,WX5622,WX5627,WX5638,WX5628,WX5634,WX5631,WX5632,WX5635,WX5636,
WX5641,WX5652,WX5642,WX5648,WX5645,WX5646,WX5649,WX5650,WX6179,WX6178,
WX6180,WX6186,WX6185,WX6187,WX6193,WX6192,WX6194,WX6200,WX6199,WX6201,
WX6207,WX6206,WX6208,WX6214,WX6213,WX6215,WX6221,WX6220,WX6222,WX6228,
WX6227,WX6229,WX6235,WX6234,WX6236,WX6242,WX6241,WX6243,WX6249,WX6248,
WX6250,WX6256,WX6255,WX6257,WX6263,WX6262,WX6264,WX6270,WX6269,WX6271,
WX6277,WX6276,WX6278,WX6284,WX6283,WX6285,WX6291,WX6290,WX6292,WX6298,
WX6297,WX6299,WX6305,WX6304,WX6306,WX6312,WX6311,WX6313,WX6319,WX6318,
WX6320,WX6326,WX6325,WX6327,WX6333,WX6332,WX6334,WX6340,WX6339,WX6341,
WX6347,WX6346,WX6348,WX6354,WX6353,WX6355,WX6361,WX6360,WX6362,WX6368,
WX6367,WX6369,WX6375,WX6374,WX6376,WX6382,WX6381,WX6383,WX6389,WX6388,
WX6390,WX6396,WX6395,WX6397,WX6406,WX6434,WX6433,WX6432,WX6405,WX6431,
WX6430,WX6429,WX6428,WX6427,WX6426,WX6404,WX6425,WX6424,WX6423,WX6422,
WX6403,WX6421,WX6420,WX6419,WX6418,WX6417,WX6416,WX6415,WX6414,WX6413,
WX6412,WX6411,WX6410,WX6409,WX6408,WX6407,WX6500,WX6511,WX6501,WX6507,
WX6504,WX6505,WX6508,WX6509,WX6514,WX6525,WX6515,WX6521,WX6518,WX6519,
WX6522,WX6523,WX6528,WX6539,WX6529,WX6535,WX6532,WX6533,WX6536,WX6537,
WX6542,WX6553,WX6543,WX6549,WX6546,WX6547,WX6550,WX6551,WX6556,WX6567,
WX6557,WX6563,WX6560,WX6561,WX6564,WX6565,WX6570,WX6581,WX6571,WX6577,
WX6574,WX6575,WX6578,WX6579,WX6584,WX6595,WX6585,WX6591,WX6588,WX6589,
WX6592,WX6593,WX6598,WX6609,WX6599,WX6605,WX6602,WX6603,WX6606,WX6607,
WX6612,WX6623,WX6613,WX6619,WX6616,WX6617,WX6620,WX6621,WX6626,WX6637,
WX6627,WX6633,WX6630,WX6631,WX6634,WX6635,WX6640,WX6651,WX6641,WX6647,
WX6644,WX6645,WX6648,WX6649,WX6654,WX6665,WX6655,WX6661,WX6658,WX6659,
WX6662,WX6663,WX6668,WX6679,WX6669,WX6675,WX6672,WX6673,WX6676,WX6677,
WX6682,WX6693,WX6683,WX6689,WX6686,WX6687,WX6690,WX6691,WX6696,WX6707,
WX6697,WX6703,WX6700,WX6701,WX6704,WX6705,WX6710,WX6721,WX6711,WX6717,
WX6714,WX6715,WX6718,WX6719,WX6724,WX6735,WX6725,WX6731,WX6728,WX6729,
WX6732,WX6733,WX6738,WX6749,WX6739,WX6745,WX6742,WX6743,WX6746,WX6747,
WX6752,WX6763,WX6753,WX6759,WX6756,WX6757,WX6760,WX6761,WX6766,WX6777,
WX6767,WX6773,WX6770,WX6771,WX6774,WX6775,WX6780,WX6791,WX6781,WX6787,
WX6784,WX6785,WX6788,WX6789,WX6794,WX6805,WX6795,WX6801,WX6798,WX6799,
WX6802,WX6803,WX6808,WX6819,WX6809,WX6815,WX6812,WX6813,WX6816,WX6817,
WX6822,WX6833,WX6823,WX6829,WX6826,WX6827,WX6830,WX6831,WX6836,WX6847,
WX6837,WX6843,WX6840,WX6841,WX6844,WX6845,WX6850,WX6861,WX6851,WX6857,
WX6854,WX6855,WX6858,WX6859,WX6864,WX6875,WX6865,WX6871,WX6868,WX6869,
WX6872,WX6873,WX6878,WX6889,WX6879,WX6885,WX6882,WX6883,WX6886,WX6887,
WX6892,WX6903,WX6893,WX6899,WX6896,WX6897,WX6900,WX6901,WX6906,WX6917,
WX6907,WX6913,WX6910,WX6911,WX6914,WX6915,WX6920,WX6931,WX6921,WX6927,
WX6924,WX6925,WX6928,WX6929,WX6934,WX6945,WX6935,WX6941,WX6938,WX6939,
WX6942,WX6943,WX7472,WX7471,WX7473,WX7479,WX7478,WX7480,WX7486,WX7485,
WX7487,WX7493,WX7492,WX7494,WX7500,WX7499,WX7501,WX7507,WX7506,WX7508,
WX7514,WX7513,WX7515,WX7521,WX7520,WX7522,WX7528,WX7527,WX7529,WX7535,
WX7534,WX7536,WX7542,WX7541,WX7543,WX7549,WX7548,WX7550,WX7556,WX7555,
WX7557,WX7563,WX7562,WX7564,WX7570,WX7569,WX7571,WX7577,WX7576,WX7578,
WX7584,WX7583,WX7585,WX7591,WX7590,WX7592,WX7598,WX7597,WX7599,WX7605,
WX7604,WX7606,WX7612,WX7611,WX7613,WX7619,WX7618,WX7620,WX7626,WX7625,
WX7627,WX7633,WX7632,WX7634,WX7640,WX7639,WX7641,WX7647,WX7646,WX7648,
WX7654,WX7653,WX7655,WX7661,WX7660,WX7662,WX7668,WX7667,WX7669,WX7675,
WX7674,WX7676,WX7682,WX7681,WX7683,WX7689,WX7688,WX7690,WX7699,WX7727,
WX7726,WX7725,WX7698,WX7724,WX7723,WX7722,WX7721,WX7720,WX7719,WX7697,
WX7718,WX7717,WX7716,WX7715,WX7696,WX7714,WX7713,WX7712,WX7711,WX7710,
WX7709,WX7708,WX7707,WX7706,WX7705,WX7704,WX7703,WX7702,WX7701,WX7700,
WX7793,WX7804,WX7794,WX7800,WX7797,WX7798,WX7801,WX7802,WX7807,WX7818,
WX7808,WX7814,WX7811,WX7812,WX7815,WX7816,WX7821,WX7832,WX7822,WX7828,
WX7825,WX7826,WX7829,WX7830,WX7835,WX7846,WX7836,WX7842,WX7839,WX7840,
WX7843,WX7844,WX7849,WX7860,WX7850,WX7856,WX7853,WX7854,WX7857,WX7858,
WX7863,WX7874,WX7864,WX7870,WX7867,WX7868,WX7871,WX7872,WX7877,WX7888,
WX7878,WX7884,WX7881,WX7882,WX7885,WX7886,WX7891,WX7902,WX7892,WX7898,
WX7895,WX7896,WX7899,WX7900,WX7905,WX7916,WX7906,WX7912,WX7909,WX7910,
WX7913,WX7914,WX7919,WX7930,WX7920,WX7926,WX7923,WX7924,WX7927,WX7928,
WX7933,WX7944,WX7934,WX7940,WX7937,WX7938,WX7941,WX7942,WX7947,WX7958,
WX7948,WX7954,WX7951,WX7952,WX7955,WX7956,WX7961,WX7972,WX7962,WX7968,
WX7965,WX7966,WX7969,WX7970,WX7975,WX7986,WX7976,WX7982,WX7979,WX7980,
WX7983,WX7984,WX7989,WX8000,WX7990,WX7996,WX7993,WX7994,WX7997,WX7998,
WX8003,WX8014,WX8004,WX8010,WX8007,WX8008,WX8011,WX8012,WX8017,WX8028,
WX8018,WX8024,WX8021,WX8022,WX8025,WX8026,WX8031,WX8042,WX8032,WX8038,
WX8035,WX8036,WX8039,WX8040,WX8045,WX8056,WX8046,WX8052,WX8049,WX8050,
WX8053,WX8054,WX8059,WX8070,WX8060,WX8066,WX8063,WX8064,WX8067,WX8068,
WX8073,WX8084,WX8074,WX8080,WX8077,WX8078,WX8081,WX8082,WX8087,WX8098,
WX8088,WX8094,WX8091,WX8092,WX8095,WX8096,WX8101,WX8112,WX8102,WX8108,
WX8105,WX8106,WX8109,WX8110,WX8115,WX8126,WX8116,WX8122,WX8119,WX8120,
WX8123,WX8124,WX8129,WX8140,WX8130,WX8136,WX8133,WX8134,WX8137,WX8138,
WX8143,WX8154,WX8144,WX8150,WX8147,WX8148,WX8151,WX8152,WX8157,WX8168,
WX8158,WX8164,WX8161,WX8162,WX8165,WX8166,WX8171,WX8182,WX8172,WX8178,
WX8175,WX8176,WX8179,WX8180,WX8185,WX8196,WX8186,WX8192,WX8189,WX8190,
WX8193,WX8194,WX8199,WX8210,WX8200,WX8206,WX8203,WX8204,WX8207,WX8208,
WX8213,WX8224,WX8214,WX8220,WX8217,WX8218,WX8221,WX8222,WX8227,WX8238,
WX8228,WX8234,WX8231,WX8232,WX8235,WX8236,WX8765,WX8764,WX8766,WX8772,
WX8771,WX8773,WX8779,WX8778,WX8780,WX8786,WX8785,WX8787,WX8793,WX8792,
WX8794,WX8800,WX8799,WX8801,WX8807,WX8806,WX8808,WX8814,WX8813,WX8815,
WX8821,WX8820,WX8822,WX8828,WX8827,WX8829,WX8835,WX8834,WX8836,WX8842,
WX8841,WX8843,WX8849,WX8848,WX8850,WX8856,WX8855,WX8857,WX8863,WX8862,
WX8864,WX8870,WX8869,WX8871,WX8877,WX8876,WX8878,WX8884,WX8883,WX8885,
WX8891,WX8890,WX8892,WX8898,WX8897,WX8899,WX8905,WX8904,WX8906,WX8912,
WX8911,WX8913,WX8919,WX8918,WX8920,WX8926,WX8925,WX8927,WX8933,WX8932,
WX8934,WX8940,WX8939,WX8941,WX8947,WX8946,WX8948,WX8954,WX8953,WX8955,
WX8961,WX8960,WX8962,WX8968,WX8967,WX8969,WX8975,WX8974,WX8976,WX8982,
WX8981,WX8983,WX8992,WX9020,WX9019,WX9018,WX8991,WX9017,WX9016,WX9015,
WX9014,WX9013,WX9012,WX8990,WX9011,WX9010,WX9009,WX9008,WX8989,WX9007,
WX9006,WX9005,WX9004,WX9003,WX9002,WX9001,WX9000,WX8999,WX8998,WX8997,
WX8996,WX8995,WX8994,WX8993,WX9086,WX9097,WX9087,WX9093,WX9090,WX9091,
WX9094,WX9095,WX9100,WX9111,WX9101,WX9107,WX9104,WX9105,WX9108,WX9109,
WX9114,WX9125,WX9115,WX9121,WX9118,WX9119,WX9122,WX9123,WX9128,WX9139,
WX9129,WX9135,WX9132,WX9133,WX9136,WX9137,WX9142,WX9153,WX9143,WX9149,
WX9146,WX9147,WX9150,WX9151,WX9156,WX9167,WX9157,WX9163,WX9160,WX9161,
WX9164,WX9165,WX9170,WX9181,WX9171,WX9177,WX9174,WX9175,WX9178,WX9179,
WX9184,WX9195,WX9185,WX9191,WX9188,WX9189,WX9192,WX9193,WX9198,WX9209,
WX9199,WX9205,WX9202,WX9203,WX9206,WX9207,WX9212,WX9223,WX9213,WX9219,
WX9216,WX9217,WX9220,WX9221,WX9226,WX9237,WX9227,WX9233,WX9230,WX9231,
WX9234,WX9235,WX9240,WX9251,WX9241,WX9247,WX9244,WX9245,WX9248,WX9249,
WX9254,WX9265,WX9255,WX9261,WX9258,WX9259,WX9262,WX9263,WX9268,WX9279,
WX9269,WX9275,WX9272,WX9273,WX9276,WX9277,WX9282,WX9293,WX9283,WX9289,
WX9286,WX9287,WX9290,WX9291,WX9296,WX9307,WX9297,WX9303,WX9300,WX9301,
WX9304,WX9305,WX9310,WX9321,WX9311,WX9317,WX9314,WX9315,WX9318,WX9319,
WX9324,WX9335,WX9325,WX9331,WX9328,WX9329,WX9332,WX9333,WX9338,WX9349,
WX9339,WX9345,WX9342,WX9343,WX9346,WX9347,WX9352,WX9363,WX9353,WX9359,
WX9356,WX9357,WX9360,WX9361,WX9366,WX9377,WX9367,WX9373,WX9370,WX9371,
WX9374,WX9375,WX9380,WX9391,WX9381,WX9387,WX9384,WX9385,WX9388,WX9389,
WX9394,WX9405,WX9395,WX9401,WX9398,WX9399,WX9402,WX9403,WX9408,WX9419,
WX9409,WX9415,WX9412,WX9413,WX9416,WX9417,WX9422,WX9433,WX9423,WX9429,
WX9426,WX9427,WX9430,WX9431,WX9436,WX9447,WX9437,WX9443,WX9440,WX9441,
WX9444,WX9445,WX9450,WX9461,WX9451,WX9457,WX9454,WX9455,WX9458,WX9459,
WX9464,WX9475,WX9465,WX9471,WX9468,WX9469,WX9472,WX9473,WX9478,WX9489,
WX9479,WX9485,WX9482,WX9483,WX9486,WX9487,WX9492,WX9503,WX9493,WX9499,
WX9496,WX9497,WX9500,WX9501,WX9506,WX9517,WX9507,WX9513,WX9510,WX9511,
WX9514,WX9515,WX9520,WX9531,WX9521,WX9527,WX9524,WX9525,WX9528,WX9529,
WX10058,WX10057,WX10059,WX10065,WX10064,WX10066,WX10072,WX10071,WX10073,
WX10079,WX10078,WX10080,WX10086,WX10085,WX10087,WX10093,WX10092,WX10094,
WX10100,WX10099,WX10101,WX10107,WX10106,WX10108,WX10114,WX10113,WX10115,
WX10121,WX10120,WX10122,WX10128,WX10127,WX10129,WX10135,WX10134,WX10136,
WX10142,WX10141,WX10143,WX10149,WX10148,WX10150,WX10156,WX10155,WX10157,
WX10163,WX10162,WX10164,WX10170,WX10169,WX10171,WX10177,WX10176,WX10178,
WX10184,WX10183,WX10185,WX10191,WX10190,WX10192,WX10198,WX10197,WX10199,
WX10205,WX10204,WX10206,WX10212,WX10211,WX10213,WX10219,WX10218,WX10220,
WX10226,WX10225,WX10227,WX10233,WX10232,WX10234,WX10240,WX10239,WX10241,
WX10247,WX10246,WX10248,WX10254,WX10253,WX10255,WX10261,WX10260,WX10262,
WX10268,WX10267,WX10269,WX10275,WX10274,WX10276,WX10285,WX10313,WX10312,
WX10311,WX10284,WX10310,WX10309,WX10308,WX10307,WX10306,WX10305,WX10283,
WX10304,WX10303,WX10302,WX10301,WX10282,WX10300,WX10299,WX10298,WX10297,
WX10296,WX10295,WX10294,WX10293,WX10292,WX10291,WX10290,WX10289,WX10288,
WX10287,WX10286,WX10379,WX10390,WX10380,WX10386,WX10383,WX10384,WX10387,
WX10388,WX10393,WX10404,WX10394,WX10400,WX10397,WX10398,WX10401,WX10402,
WX10407,WX10418,WX10408,WX10414,WX10411,WX10412,WX10415,WX10416,WX10421,
WX10432,WX10422,WX10428,WX10425,WX10426,WX10429,WX10430,WX10435,WX10446,
WX10436,WX10442,WX10439,WX10440,WX10443,WX10444,WX10449,WX10460,WX10450,
WX10456,WX10453,WX10454,WX10457,WX10458,WX10463,WX10474,WX10464,WX10470,
WX10467,WX10468,WX10471,WX10472,WX10477,WX10488,WX10478,WX10484,WX10481,
WX10482,WX10485,WX10486,WX10491,WX10502,WX10492,WX10498,WX10495,WX10496,
WX10499,WX10500,WX10505,WX10516,WX10506,WX10512,WX10509,WX10510,WX10513,
WX10514,WX10519,WX10530,WX10520,WX10526,WX10523,WX10524,WX10527,WX10528,
WX10533,WX10544,WX10534,WX10540,WX10537,WX10538,WX10541,WX10542,WX10547,
WX10558,WX10548,WX10554,WX10551,WX10552,WX10555,WX10556,WX10561,WX10572,
WX10562,WX10568,WX10565,WX10566,WX10569,WX10570,WX10575,WX10586,WX10576,
WX10582,WX10579,WX10580,WX10583,WX10584,WX10589,WX10600,WX10590,WX10596,
WX10593,WX10594,WX10597,WX10598,WX10603,WX10614,WX10604,WX10610,WX10607,
WX10608,WX10611,WX10612,WX10617,WX10628,WX10618,WX10624,WX10621,WX10622,
WX10625,WX10626,WX10631,WX10642,WX10632,WX10638,WX10635,WX10636,WX10639,
WX10640,WX10645,WX10656,WX10646,WX10652,WX10649,WX10650,WX10653,WX10654,
WX10659,WX10670,WX10660,WX10666,WX10663,WX10664,WX10667,WX10668,WX10673,
WX10684,WX10674,WX10680,WX10677,WX10678,WX10681,WX10682,WX10687,WX10698,
WX10688,WX10694,WX10691,WX10692,WX10695,WX10696,WX10701,WX10712,WX10702,
WX10708,WX10705,WX10706,WX10709,WX10710,WX10715,WX10726,WX10716,WX10722,
WX10719,WX10720,WX10723,WX10724,WX10729,WX10740,WX10730,WX10736,WX10733,
WX10734,WX10737,WX10738,WX10743,WX10754,WX10744,WX10750,WX10747,WX10748,
WX10751,WX10752,WX10757,WX10768,WX10758,WX10764,WX10761,WX10762,WX10765,
WX10766,WX10771,WX10782,WX10772,WX10778,WX10775,WX10776,WX10779,WX10780,
WX10785,WX10796,WX10786,WX10792,WX10789,WX10790,WX10793,WX10794,WX10799,
WX10810,WX10800,WX10806,WX10803,WX10804,WX10807,WX10808,WX10813,WX10824,
WX10814,WX10820,WX10817,WX10818,WX10821,WX10822,WX11351,WX11350,WX11352,
WX11358,WX11357,WX11359,WX11365,WX11364,WX11366,WX11372,WX11371,WX11373,
WX11379,WX11378,WX11380,WX11386,WX11385,WX11387,WX11393,WX11392,WX11394,
WX11400,WX11399,WX11401,WX11407,WX11406,WX11408,WX11414,WX11413,WX11415,
WX11421,WX11420,WX11422,WX11428,WX11427,WX11429,WX11435,WX11434,WX11436,
WX11442,WX11441,WX11443,WX11449,WX11448,WX11450,WX11456,WX11455,WX11457,
WX11463,WX11462,WX11464,WX11470,WX11469,WX11471,WX11477,WX11476,WX11478,
WX11484,WX11483,WX11485,WX11491,WX11490,WX11492,WX11498,WX11497,WX11499,
WX11505,WX11504,WX11506,WX11512,WX11511,WX11513,WX11519,WX11518,WX11520,
WX11526,WX11525,WX11527,WX11533,WX11532,WX11534,WX11540,WX11539,WX11541,
WX11547,WX11546,WX11548,WX11554,WX11553,WX11555,WX11561,WX11560,WX11562,
WX11568,WX11567,WX11569,WX11578,WX11606,WX11605,WX11604,WX11577,WX11603,
WX11602,WX11601,WX11600,WX11599,WX11598,WX11576,WX11597,WX11596,WX11595,
WX11594,WX11575,WX11593,WX11592,WX11591,WX11590,WX11589,WX11588,WX11587,
WX11586,WX11585,WX11584,WX11583,WX11582,WX11581,WX11580,WX11579,II1988,
II1989,II1990,II1987,II1995,II1996,II1997,II1986,II2003,II2004,II2005,
II2002,II2010,II2011,II2012,II2019,II2020,II2021,II2018,II2026,II2027,
II2028,II2017,II2034,II2035,II2036,II2033,II2041,II2042,II2043,II2050,
II2051,II2052,II2049,II2057,II2058,II2059,II2048,II2065,II2066,II2067,
II2064,II2072,II2073,II2074,II2081,II2082,II2083,II2080,II2088,II2089,
II2090,II2079,II2096,II2097,II2098,II2095,II2103,II2104,II2105,II2112,
II2113,II2114,II2111,II2119,II2120,II2121,II2110,II2127,II2128,II2129,
II2126,II2134,II2135,II2136,II2143,II2144,II2145,II2142,II2150,II2151,
II2152,II2141,II2158,II2159,II2160,II2157,II2165,II2166,II2167,II2174,
II2175,II2176,II2173,II2181,II2182,II2183,II2172,II2189,II2190,II2191,
II2188,II2196,II2197,II2198,II2205,II2206,II2207,II2204,II2212,II2213,
II2214,II2203,II2220,II2221,II2222,II2219,II2227,II2228,II2229,II2236,
II2237,II2238,II2235,II2243,II2244,II2245,II2234,II2251,II2252,II2253,
II2250,II2258,II2259,II2260,II2267,II2268,II2269,II2266,II2274,II2275,
II2276,II2265,II2282,II2283,II2284,II2281,II2289,II2290,II2291,II2298,
II2299,II2300,II2297,II2305,II2306,II2307,II2296,II2313,II2314,II2315,
II2312,II2320,II2321,II2322,II2329,II2330,II2331,II2328,II2336,II2337,
II2338,II2327,II2344,II2345,II2346,II2343,II2351,II2352,II2353,II2360,
II2361,II2362,II2359,II2367,II2368,II2369,II2358,II2375,II2376,II2377,
II2374,II2382,II2383,II2384,II2391,II2392,II2393,II2390,II2398,II2399,
II2400,II2389,II2406,II2407,II2408,II2405,II2413,II2414,II2415,II2422,
II2423,II2424,II2421,II2429,II2430,II2431,II2420,II2437,II2438,II2439,
II2436,II2444,II2445,II2446,II2453,II2454,II2455,II2452,II2460,II2461,
II2462,II2451,II2468,II2469,II2470,II2467,II2475,II2476,II2477,II2484,
II2485,II2486,II2483,II2491,II2492,II2493,II2482,II2499,II2500,II2501,
II2498,II2506,II2507,II2508,II2515,II2516,II2517,II2514,II2522,II2523,
II2524,II2513,II2530,II2531,II2532,II2529,II2537,II2538,II2539,II2546,
II2547,II2548,II2545,II2553,II2554,II2555,II2544,II2561,II2562,II2563,
II2560,II2568,II2569,II2570,II2577,II2578,II2579,II2576,II2584,II2585,
II2586,II2575,II2592,II2593,II2594,II2591,II2599,II2600,II2601,II2608,
II2609,II2610,II2607,II2615,II2616,II2617,II2606,II2623,II2624,II2625,
II2622,II2630,II2631,II2632,II2639,II2640,II2641,II2638,II2646,II2647,
II2648,II2637,II2654,II2655,II2656,II2653,II2661,II2662,II2663,II2670,
II2671,II2672,II2669,II2677,II2678,II2679,II2668,II2685,II2686,II2687,
II2684,II2692,II2693,II2694,II2701,II2702,II2703,II2700,II2708,II2709,
II2710,II2699,II2716,II2717,II2718,II2715,II2723,II2724,II2725,II2732,
II2733,II2734,II2731,II2739,II2740,II2741,II2730,II2747,II2748,II2749,
II2746,II2754,II2755,II2756,II2763,II2764,II2765,II2762,II2770,II2771,
II2772,II2761,II2778,II2779,II2780,II2777,II2785,II2786,II2787,II2794,
II2795,II2796,II2793,II2801,II2802,II2803,II2792,II2809,II2810,II2811,
II2808,II2816,II2817,II2818,II2825,II2826,II2827,II2824,II2832,II2833,
II2834,II2823,II2840,II2841,II2842,II2839,II2847,II2848,II2849,II2856,
II2857,II2858,II2855,II2863,II2864,II2865,II2854,II2871,II2872,II2873,
II2870,II2878,II2879,II2880,II2887,II2888,II2889,II2886,II2894,II2895,
II2896,II2885,II2902,II2903,II2904,II2901,II2909,II2910,II2911,II2918,
II2919,II2920,II2917,II2925,II2926,II2927,II2916,II2933,II2934,II2935,
II2932,II2940,II2941,II2942,II2949,II2950,II2951,II2948,II2956,II2957,
II2958,II2947,II2964,II2965,II2966,II2963,II2971,II2972,II2973,II3052,
II3053,II3054,II3065,II3066,II3067,II3078,II3079,II3080,II3091,II3092,
II3093,II3104,II3105,II3106,II3117,II3118,II3119,II3130,II3131,II3132,
II3143,II3144,II3145,II3156,II3157,II3158,II3169,II3170,II3171,II3182,
II3183,II3184,II3195,II3196,II3197,II3208,II3209,II3210,II3221,II3222,
II3223,II3234,II3235,II3236,II3247,II3248,II3249,II3260,II3261,II3262,
II3273,II3274,II3275,II3286,II3287,II3288,II3299,II3300,II3301,II3312,
II3313,II3314,II3325,II3326,II3327,II3338,II3339,II3340,II3351,II3352,
II3353,II3364,II3365,II3366,II3377,II3378,II3379,II3390,II3391,II3392,
II3403,II3404,II3405,II3416,II3417,II3418,II3429,II3430,II3431,II3442,
II3443,II3444,II3455,II3456,II3457,II3470,II3471,II3472,II3469,II3477,
II3478,II3479,II3485,II3486,II3487,II3484,II3492,II3493,II3494,II3500,
II3501,II3502,II3499,II3507,II3508,II3509,II3514,II3515,II3516,II3521,
II3522,II3523,II3528,II3529,II3530,II3535,II3536,II3537,II3542,II3543,
II3544,II3549,II3550,II3551,II3556,II3557,II3558,II3563,II3564,II3565,
II3570,II3571,II3572,II3577,II3578,II3579,II3584,II3585,II3586,II3591,
II3592,II3593,II3598,II3599,II3600,II3605,II3606,II3607,II3612,II3613,
II3614,II3619,II3620,II3621,II3626,II3627,II3628,II3633,II3634,II3635,
II3640,II3641,II3642,II3647,II3648,II3649,II3654,II3655,II3656,II3661,
II3662,II3663,II3668,II3669,II3670,II3675,II3676,II3677,II3682,II3683,
II3684,II3689,II3690,II3691,II3696,II3697,II3698,II3703,II3704,II3705,
II3710,II3711,II3712,II5993,II5994,II5995,II5992,II6000,II6001,II6002,
II5991,II6008,II6009,II6010,II6007,II6015,II6016,II6017,II6024,II6025,
II6026,II6023,II6031,II6032,II6033,II6022,II6039,II6040,II6041,II6038,
II6046,II6047,II6048,II6055,II6056,II6057,II6054,II6062,II6063,II6064,
II6053,II6070,II6071,II6072,II6069,II6077,II6078,II6079,II6086,II6087,
II6088,II6085,II6093,II6094,II6095,II6084,II6101,II6102,II6103,II6100,
II6108,II6109,II6110,II6117,II6118,II6119,II6116,II6124,II6125,II6126,
II6115,II6132,II6133,II6134,II6131,II6139,II6140,II6141,II6148,II6149,
II6150,II6147,II6155,II6156,II6157,II6146,II6163,II6164,II6165,II6162,
II6170,II6171,II6172,II6179,II6180,II6181,II6178,II6186,II6187,II6188,
II6177,II6194,II6195,II6196,II6193,II6201,II6202,II6203,II6210,II6211,
II6212,II6209,II6217,II6218,II6219,II6208,II6225,II6226,II6227,II6224,
II6232,II6233,II6234,II6241,II6242,II6243,II6240,II6248,II6249,II6250,
II6239,II6256,II6257,II6258,II6255,II6263,II6264,II6265,II6272,II6273,
II6274,II6271,II6279,II6280,II6281,II6270,II6287,II6288,II6289,II6286,
II6294,II6295,II6296,II6303,II6304,II6305,II6302,II6310,II6311,II6312,
II6301,II6318,II6319,II6320,II6317,II6325,II6326,II6327,II6334,II6335,
II6336,II6333,II6341,II6342,II6343,II6332,II6349,II6350,II6351,II6348,
II6356,II6357,II6358,II6365,II6366,II6367,II6364,II6372,II6373,II6374,
II6363,II6380,II6381,II6382,II6379,II6387,II6388,II6389,II6396,II6397,
II6398,II6395,II6403,II6404,II6405,II6394,II6411,II6412,II6413,II6410,
II6418,II6419,II6420,II6427,II6428,II6429,II6426,II6434,II6435,II6436,
II6425,II6442,II6443,II6444,II6441,II6449,II6450,II6451,II6458,II6459,
II6460,II6457,II6465,II6466,II6467,II6456,II6473,II6474,II6475,II6472,
II6480,II6481,II6482,II6489,II6490,II6491,II6488,II6496,II6497,II6498,
II6487,II6504,II6505,II6506,II6503,II6511,II6512,II6513,II6520,II6521,
II6522,II6519,II6527,II6528,II6529,II6518,II6535,II6536,II6537,II6534,
II6542,II6543,II6544,II6551,II6552,II6553,II6550,II6558,II6559,II6560,
II6549,II6566,II6567,II6568,II6565,II6573,II6574,II6575,II6582,II6583,
II6584,II6581,II6589,II6590,II6591,II6580,II6597,II6598,II6599,II6596,
II6604,II6605,II6606,II6613,II6614,II6615,II6612,II6620,II6621,II6622,
II6611,II6628,II6629,II6630,II6627,II6635,II6636,II6637,II6644,II6645,
II6646,II6643,II6651,II6652,II6653,II6642,II6659,II6660,II6661,II6658,
II6666,II6667,II6668,II6675,II6676,II6677,II6674,II6682,II6683,II6684,
II6673,II6690,II6691,II6692,II6689,II6697,II6698,II6699,II6706,II6707,
II6708,II6705,II6713,II6714,II6715,II6704,II6721,II6722,II6723,II6720,
II6728,II6729,II6730,II6737,II6738,II6739,II6736,II6744,II6745,II6746,
II6735,II6752,II6753,II6754,II6751,II6759,II6760,II6761,II6768,II6769,
II6770,II6767,II6775,II6776,II6777,II6766,II6783,II6784,II6785,II6782,
II6790,II6791,II6792,II6799,II6800,II6801,II6798,II6806,II6807,II6808,
II6797,II6814,II6815,II6816,II6813,II6821,II6822,II6823,II6830,II6831,
II6832,II6829,II6837,II6838,II6839,II6828,II6845,II6846,II6847,II6844,
II6852,II6853,II6854,II6861,II6862,II6863,II6860,II6868,II6869,II6870,
II6859,II6876,II6877,II6878,II6875,II6883,II6884,II6885,II6892,II6893,
II6894,II6891,II6899,II6900,II6901,II6890,II6907,II6908,II6909,II6906,
II6914,II6915,II6916,II6923,II6924,II6925,II6922,II6930,II6931,II6932,
II6921,II6938,II6939,II6940,II6937,II6945,II6946,II6947,II6954,II6955,
II6956,II6953,II6961,II6962,II6963,II6952,II6969,II6970,II6971,II6968,
II6976,II6977,II6978,II7057,II7058,II7059,II7070,II7071,II7072,II7083,
II7084,II7085,II7096,II7097,II7098,II7109,II7110,II7111,II7122,II7123,
II7124,II7135,II7136,II7137,II7148,II7149,II7150,II7161,II7162,II7163,
II7174,II7175,II7176,II7187,II7188,II7189,II7200,II7201,II7202,II7213,
II7214,II7215,II7226,II7227,II7228,II7239,II7240,II7241,II7252,II7253,
II7254,II7265,II7266,II7267,II7278,II7279,II7280,II7291,II7292,II7293,
II7304,II7305,II7306,II7317,II7318,II7319,II7330,II7331,II7332,II7343,
II7344,II7345,II7356,II7357,II7358,II7369,II7370,II7371,II7382,II7383,
II7384,II7395,II7396,II7397,II7408,II7409,II7410,II7421,II7422,II7423,
II7434,II7435,II7436,II7447,II7448,II7449,II7460,II7461,II7462,II7475,
II7476,II7477,II7474,II7482,II7483,II7484,II7490,II7491,II7492,II7489,
II7497,II7498,II7499,II7505,II7506,II7507,II7504,II7512,II7513,II7514,
II7519,II7520,II7521,II7526,II7527,II7528,II7533,II7534,II7535,II7540,
II7541,II7542,II7547,II7548,II7549,II7554,II7555,II7556,II7561,II7562,
II7563,II7568,II7569,II7570,II7575,II7576,II7577,II7582,II7583,II7584,
II7589,II7590,II7591,II7596,II7597,II7598,II7603,II7604,II7605,II7610,
II7611,II7612,II7617,II7618,II7619,II7624,II7625,II7626,II7631,II7632,
II7633,II7638,II7639,II7640,II7645,II7646,II7647,II7652,II7653,II7654,
II7659,II7660,II7661,II7666,II7667,II7668,II7673,II7674,II7675,II7680,
II7681,II7682,II7687,II7688,II7689,II7694,II7695,II7696,II7701,II7702,
II7703,II7708,II7709,II7710,II7715,II7716,II7717,II9998,II9999,II10000,
II9997,II10005,II10006,II10007,II9996,II10013,II10014,II10015,II10012,
II10020,II10021,II10022,II10029,II10030,II10031,II10028,II10036,II10037,
II10038,II10027,II10044,II10045,II10046,II10043,II10051,II10052,II10053,
II10060,II10061,II10062,II10059,II10067,II10068,II10069,II10058,II10075,
II10076,II10077,II10074,II10082,II10083,II10084,II10091,II10092,II10093,
II10090,II10098,II10099,II10100,II10089,II10106,II10107,II10108,II10105,
II10113,II10114,II10115,II10122,II10123,II10124,II10121,II10129,II10130,
II10131,II10120,II10137,II10138,II10139,II10136,II10144,II10145,II10146,
II10153,II10154,II10155,II10152,II10160,II10161,II10162,II10151,II10168,
II10169,II10170,II10167,II10175,II10176,II10177,II10184,II10185,II10186,
II10183,II10191,II10192,II10193,II10182,II10199,II10200,II10201,II10198,
II10206,II10207,II10208,II10215,II10216,II10217,II10214,II10222,II10223,
II10224,II10213,II10230,II10231,II10232,II10229,II10237,II10238,II10239,
II10246,II10247,II10248,II10245,II10253,II10254,II10255,II10244,II10261,
II10262,II10263,II10260,II10268,II10269,II10270,II10277,II10278,II10279,
II10276,II10284,II10285,II10286,II10275,II10292,II10293,II10294,II10291,
II10299,II10300,II10301,II10308,II10309,II10310,II10307,II10315,II10316,
II10317,II10306,II10323,II10324,II10325,II10322,II10330,II10331,II10332,
II10339,II10340,II10341,II10338,II10346,II10347,II10348,II10337,II10354,
II10355,II10356,II10353,II10361,II10362,II10363,II10370,II10371,II10372,
II10369,II10377,II10378,II10379,II10368,II10385,II10386,II10387,II10384,
II10392,II10393,II10394,II10401,II10402,II10403,II10400,II10408,II10409,
II10410,II10399,II10416,II10417,II10418,II10415,II10423,II10424,II10425,
II10432,II10433,II10434,II10431,II10439,II10440,II10441,II10430,II10447,
II10448,II10449,II10446,II10454,II10455,II10456,II10463,II10464,II10465,
II10462,II10470,II10471,II10472,II10461,II10478,II10479,II10480,II10477,
II10485,II10486,II10487,II10494,II10495,II10496,II10493,II10501,II10502,
II10503,II10492,II10509,II10510,II10511,II10508,II10516,II10517,II10518,
II10525,II10526,II10527,II10524,II10532,II10533,II10534,II10523,II10540,
II10541,II10542,II10539,II10547,II10548,II10549,II10556,II10557,II10558,
II10555,II10563,II10564,II10565,II10554,II10571,II10572,II10573,II10570,
II10578,II10579,II10580,II10587,II10588,II10589,II10586,II10594,II10595,
II10596,II10585,II10602,II10603,II10604,II10601,II10609,II10610,II10611,
II10618,II10619,II10620,II10617,II10625,II10626,II10627,II10616,II10633,
II10634,II10635,II10632,II10640,II10641,II10642,II10649,II10650,II10651,
II10648,II10656,II10657,II10658,II10647,II10664,II10665,II10666,II10663,
II10671,II10672,II10673,II10680,II10681,II10682,II10679,II10687,II10688,
II10689,II10678,II10695,II10696,II10697,II10694,II10702,II10703,II10704,
II10711,II10712,II10713,II10710,II10718,II10719,II10720,II10709,II10726,
II10727,II10728,II10725,II10733,II10734,II10735,II10742,II10743,II10744,
II10741,II10749,II10750,II10751,II10740,II10757,II10758,II10759,II10756,
II10764,II10765,II10766,II10773,II10774,II10775,II10772,II10780,II10781,
II10782,II10771,II10788,II10789,II10790,II10787,II10795,II10796,II10797,
II10804,II10805,II10806,II10803,II10811,II10812,II10813,II10802,II10819,
II10820,II10821,II10818,II10826,II10827,II10828,II10835,II10836,II10837,
II10834,II10842,II10843,II10844,II10833,II10850,II10851,II10852,II10849,
II10857,II10858,II10859,II10866,II10867,II10868,II10865,II10873,II10874,
II10875,II10864,II10881,II10882,II10883,II10880,II10888,II10889,II10890,
II10897,II10898,II10899,II10896,II10904,II10905,II10906,II10895,II10912,
II10913,II10914,II10911,II10919,II10920,II10921,II10928,II10929,II10930,
II10927,II10935,II10936,II10937,II10926,II10943,II10944,II10945,II10942,
II10950,II10951,II10952,II10959,II10960,II10961,II10958,II10966,II10967,
II10968,II10957,II10974,II10975,II10976,II10973,II10981,II10982,II10983,
II11062,II11063,II11064,II11075,II11076,II11077,II11088,II11089,II11090,
II11101,II11102,II11103,II11114,II11115,II11116,II11127,II11128,II11129,
II11140,II11141,II11142,II11153,II11154,II11155,II11166,II11167,II11168,
II11179,II11180,II11181,II11192,II11193,II11194,II11205,II11206,II11207,
II11218,II11219,II11220,II11231,II11232,II11233,II11244,II11245,II11246,
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II18402,II18403,II18404,II18411,II18412,II18413,II18410,II18418,II18419,
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II18885,II18874,II18891,II18892,II18893,II18890,II18898,II18899,II18900,
II18907,II18908,II18909,II18906,II18914,II18915,II18916,II18905,II18922,
II18923,II18924,II18921,II18929,II18930,II18931,II18938,II18939,II18940,
II18937,II18945,II18946,II18947,II18936,II18953,II18954,II18955,II18952,
II18960,II18961,II18962,II18969,II18970,II18971,II18968,II18976,II18977,
II18978,II18967,II18984,II18985,II18986,II18983,II18991,II18992,II18993,
II19072,II19073,II19074,II19085,II19086,II19087,II19098,II19099,II19100,
II19111,II19112,II19113,II19124,II19125,II19126,II19137,II19138,II19139,
II19150,II19151,II19152,II19163,II19164,II19165,II19176,II19177,II19178,
II19189,II19190,II19191,II19202,II19203,II19204,II19215,II19216,II19217,
II19228,II19229,II19230,II19241,II19242,II19243,II19254,II19255,II19256,
II19267,II19268,II19269,II19280,II19281,II19282,II19293,II19294,II19295,
II19306,II19307,II19308,II19319,II19320,II19321,II19332,II19333,II19334,
II19345,II19346,II19347,II19358,II19359,II19360,II19371,II19372,II19373,
II19384,II19385,II19386,II19397,II19398,II19399,II19410,II19411,II19412,
II19423,II19424,II19425,II19436,II19437,II19438,II19449,II19450,II19451,
II19462,II19463,II19464,II19475,II19476,II19477,II19490,II19491,II19492,
II19489,II19497,II19498,II19499,II19505,II19506,II19507,II19504,II19512,
II19513,II19514,II19520,II19521,II19522,II19519,II19527,II19528,II19529,
II19534,II19535,II19536,II19541,II19542,II19543,II19548,II19549,II19550,
II19555,II19556,II19557,II19562,II19563,II19564,II19569,II19570,II19571,
II19576,II19577,II19578,II19583,II19584,II19585,II19590,II19591,II19592,
II19597,II19598,II19599,II19604,II19605,II19606,II19611,II19612,II19613,
II19618,II19619,II19620,II19625,II19626,II19627,II19632,II19633,II19634,
II19639,II19640,II19641,II19646,II19647,II19648,II19653,II19654,II19655,
II19660,II19661,II19662,II19667,II19668,II19669,II19674,II19675,II19676,
II19681,II19682,II19683,II19688,II19689,II19690,II19695,II19696,II19697,
II19702,II19703,II19704,II19709,II19710,II19711,II19716,II19717,II19718,
II19723,II19724,II19725,II19730,II19731,II19732,II22013,II22014,II22015,
II22012,II22020,II22021,II22022,II22011,II22028,II22029,II22030,II22027,
II22035,II22036,II22037,II22044,II22045,II22046,II22043,II22051,II22052,
II22053,II22042,II22059,II22060,II22061,II22058,II22066,II22067,II22068,
II22075,II22076,II22077,II22074,II22082,II22083,II22084,II22073,II22090,
II22091,II22092,II22089,II22097,II22098,II22099,II22106,II22107,II22108,
II22105,II22113,II22114,II22115,II22104,II22121,II22122,II22123,II22120,
II22128,II22129,II22130,II22137,II22138,II22139,II22136,II22144,II22145,
II22146,II22135,II22152,II22153,II22154,II22151,II22159,II22160,II22161,
II22168,II22169,II22170,II22167,II22175,II22176,II22177,II22166,II22183,
II22184,II22185,II22182,II22190,II22191,II22192,II22199,II22200,II22201,
II22198,II22206,II22207,II22208,II22197,II22214,II22215,II22216,II22213,
II22221,II22222,II22223,II22230,II22231,II22232,II22229,II22237,II22238,
II22239,II22228,II22245,II22246,II22247,II22244,II22252,II22253,II22254,
II22261,II22262,II22263,II22260,II22268,II22269,II22270,II22259,II22276,
II22277,II22278,II22275,II22283,II22284,II22285,II22292,II22293,II22294,
II22291,II22299,II22300,II22301,II22290,II22307,II22308,II22309,II22306,
II22314,II22315,II22316,II22323,II22324,II22325,II22322,II22330,II22331,
II22332,II22321,II22338,II22339,II22340,II22337,II22345,II22346,II22347,
II22354,II22355,II22356,II22353,II22361,II22362,II22363,II22352,II22369,
II22370,II22371,II22368,II22376,II22377,II22378,II22385,II22386,II22387,
II22384,II22392,II22393,II22394,II22383,II22400,II22401,II22402,II22399,
II22407,II22408,II22409,II22416,II22417,II22418,II22415,II22423,II22424,
II22425,II22414,II22431,II22432,II22433,II22430,II22438,II22439,II22440,
II22447,II22448,II22449,II22446,II22454,II22455,II22456,II22445,II22462,
II22463,II22464,II22461,II22469,II22470,II22471,II22478,II22479,II22480,
II22477,II22485,II22486,II22487,II22476,II22493,II22494,II22495,II22492,
II22500,II22501,II22502,II22509,II22510,II22511,II22508,II22516,II22517,
II22518,II22507,II22524,II22525,II22526,II22523,II22531,II22532,II22533,
II22540,II22541,II22542,II22539,II22547,II22548,II22549,II22538,II22555,
II22556,II22557,II22554,II22562,II22563,II22564,II22571,II22572,II22573,
II22570,II22578,II22579,II22580,II22569,II22586,II22587,II22588,II22585,
II22593,II22594,II22595,II22602,II22603,II22604,II22601,II22609,II22610,
II22611,II22600,II22617,II22618,II22619,II22616,II22624,II22625,II22626,
II22633,II22634,II22635,II22632,II22640,II22641,II22642,II22631,II22648,
II22649,II22650,II22647,II22655,II22656,II22657,II22664,II22665,II22666,
II22663,II22671,II22672,II22673,II22662,II22679,II22680,II22681,II22678,
II22686,II22687,II22688,II22695,II22696,II22697,II22694,II22702,II22703,
II22704,II22693,II22710,II22711,II22712,II22709,II22717,II22718,II22719,
II22726,II22727,II22728,II22725,II22733,II22734,II22735,II22724,II22741,
II22742,II22743,II22740,II22748,II22749,II22750,II22757,II22758,II22759,
II22756,II22764,II22765,II22766,II22755,II22772,II22773,II22774,II22771,
II22779,II22780,II22781,II22788,II22789,II22790,II22787,II22795,II22796,
II22797,II22786,II22803,II22804,II22805,II22802,II22810,II22811,II22812,
II22819,II22820,II22821,II22818,II22826,II22827,II22828,II22817,II22834,
II22835,II22836,II22833,II22841,II22842,II22843,II22850,II22851,II22852,
II22849,II22857,II22858,II22859,II22848,II22865,II22866,II22867,II22864,
II22872,II22873,II22874,II22881,II22882,II22883,II22880,II22888,II22889,
II22890,II22879,II22896,II22897,II22898,II22895,II22903,II22904,II22905,
II22912,II22913,II22914,II22911,II22919,II22920,II22921,II22910,II22927,
II22928,II22929,II22926,II22934,II22935,II22936,II22943,II22944,II22945,
II22942,II22950,II22951,II22952,II22941,II22958,II22959,II22960,II22957,
II22965,II22966,II22967,II22974,II22975,II22976,II22973,II22981,II22982,
II22983,II22972,II22989,II22990,II22991,II22988,II22996,II22997,II22998,
II23077,II23078,II23079,II23090,II23091,II23092,II23103,II23104,II23105,
II23116,II23117,II23118,II23129,II23130,II23131,II23142,II23143,II23144,
II23155,II23156,II23157,II23168,II23169,II23170,II23181,II23182,II23183,
II23194,II23195,II23196,II23207,II23208,II23209,II23220,II23221,II23222,
II23233,II23234,II23235,II23246,II23247,II23248,II23259,II23260,II23261,
II23272,II23273,II23274,II23285,II23286,II23287,II23298,II23299,II23300,
II23311,II23312,II23313,II23324,II23325,II23326,II23337,II23338,II23339,
II23350,II23351,II23352,II23363,II23364,II23365,II23376,II23377,II23378,
II23389,II23390,II23391,II23402,II23403,II23404,II23415,II23416,II23417,
II23428,II23429,II23430,II23441,II23442,II23443,II23454,II23455,II23456,
II23467,II23468,II23469,II23480,II23481,II23482,II23495,II23496,II23497,
II23494,II23502,II23503,II23504,II23510,II23511,II23512,II23509,II23517,
II23518,II23519,II23525,II23526,II23527,II23524,II23532,II23533,II23534,
II23539,II23540,II23541,II23546,II23547,II23548,II23553,II23554,II23555,
II23560,II23561,II23562,II23567,II23568,II23569,II23574,II23575,II23576,
II23581,II23582,II23583,II23588,II23589,II23590,II23595,II23596,II23597,
II23602,II23603,II23604,II23609,II23610,II23611,II23616,II23617,II23618,
II23623,II23624,II23625,II23630,II23631,II23632,II23637,II23638,II23639,
II23644,II23645,II23646,II23651,II23652,II23653,II23658,II23659,II23660,
II23665,II23666,II23667,II23672,II23673,II23674,II23679,II23680,II23681,
II23686,II23687,II23688,II23693,II23694,II23695,II23700,II23701,II23702,
II23707,II23708,II23709,II23714,II23715,II23716,II23721,II23722,II23723,
II23728,II23729,II23730,II23735,II23736,II23737,II26018,II26019,II26020,
II26017,II26025,II26026,II26027,II26016,II26033,II26034,II26035,II26032,
II26040,II26041,II26042,II26049,II26050,II26051,II26048,II26056,II26057,
II26058,II26047,II26064,II26065,II26066,II26063,II26071,II26072,II26073,
II26080,II26081,II26082,II26079,II26087,II26088,II26089,II26078,II26095,
II26096,II26097,II26094,II26102,II26103,II26104,II26111,II26112,II26113,
II26110,II26118,II26119,II26120,II26109,II26126,II26127,II26128,II26125,
II26133,II26134,II26135,II26142,II26143,II26144,II26141,II26149,II26150,
II26151,II26140,II26157,II26158,II26159,II26156,II26164,II26165,II26166,
II26173,II26174,II26175,II26172,II26180,II26181,II26182,II26171,II26188,
II26189,II26190,II26187,II26195,II26196,II26197,II26204,II26205,II26206,
II26203,II26211,II26212,II26213,II26202,II26219,II26220,II26221,II26218,
II26226,II26227,II26228,II26235,II26236,II26237,II26234,II26242,II26243,
II26244,II26233,II26250,II26251,II26252,II26249,II26257,II26258,II26259,
II26266,II26267,II26268,II26265,II26273,II26274,II26275,II26264,II26281,
II26282,II26283,II26280,II26288,II26289,II26290,II26297,II26298,II26299,
II26296,II26304,II26305,II26306,II26295,II26312,II26313,II26314,II26311,
II26319,II26320,II26321,II26328,II26329,II26330,II26327,II26335,II26336,
II26337,II26326,II26343,II26344,II26345,II26342,II26350,II26351,II26352,
II26359,II26360,II26361,II26358,II26366,II26367,II26368,II26357,II26374,
II26375,II26376,II26373,II26381,II26382,II26383,II26390,II26391,II26392,
II26389,II26397,II26398,II26399,II26388,II26405,II26406,II26407,II26404,
II26412,II26413,II26414,II26421,II26422,II26423,II26420,II26428,II26429,
II26430,II26419,II26436,II26437,II26438,II26435,II26443,II26444,II26445,
II26452,II26453,II26454,II26451,II26459,II26460,II26461,II26450,II26467,
II26468,II26469,II26466,II26474,II26475,II26476,II26483,II26484,II26485,
II26482,II26490,II26491,II26492,II26481,II26498,II26499,II26500,II26497,
II26505,II26506,II26507,II26514,II26515,II26516,II26513,II26521,II26522,
II26523,II26512,II26529,II26530,II26531,II26528,II26536,II26537,II26538,
II26545,II26546,II26547,II26544,II26552,II26553,II26554,II26543,II26560,
II26561,II26562,II26559,II26567,II26568,II26569,II26576,II26577,II26578,
II26575,II26583,II26584,II26585,II26574,II26591,II26592,II26593,II26590,
II26598,II26599,II26600,II26607,II26608,II26609,II26606,II26614,II26615,
II26616,II26605,II26622,II26623,II26624,II26621,II26629,II26630,II26631,
II26638,II26639,II26640,II26637,II26645,II26646,II26647,II26636,II26653,
II26654,II26655,II26652,II26660,II26661,II26662,II26669,II26670,II26671,
II26668,II26676,II26677,II26678,II26667,II26684,II26685,II26686,II26683,
II26691,II26692,II26693,II26700,II26701,II26702,II26699,II26707,II26708,
II26709,II26698,II26715,II26716,II26717,II26714,II26722,II26723,II26724,
II26731,II26732,II26733,II26730,II26738,II26739,II26740,II26729,II26746,
II26747,II26748,II26745,II26753,II26754,II26755,II26762,II26763,II26764,
II26761,II26769,II26770,II26771,II26760,II26777,II26778,II26779,II26776,
II26784,II26785,II26786,II26793,II26794,II26795,II26792,II26800,II26801,
II26802,II26791,II26808,II26809,II26810,II26807,II26815,II26816,II26817,
II26824,II26825,II26826,II26823,II26831,II26832,II26833,II26822,II26839,
II26840,II26841,II26838,II26846,II26847,II26848,II26855,II26856,II26857,
II26854,II26862,II26863,II26864,II26853,II26870,II26871,II26872,II26869,
II26877,II26878,II26879,II26886,II26887,II26888,II26885,II26893,II26894,
II26895,II26884,II26901,II26902,II26903,II26900,II26908,II26909,II26910,
II26917,II26918,II26919,II26916,II26924,II26925,II26926,II26915,II26932,
II26933,II26934,II26931,II26939,II26940,II26941,II26948,II26949,II26950,
II26947,II26955,II26956,II26957,II26946,II26963,II26964,II26965,II26962,
II26970,II26971,II26972,II26979,II26980,II26981,II26978,II26986,II26987,
II26988,II26977,II26994,II26995,II26996,II26993,II27001,II27002,II27003,
II27082,II27083,II27084,II27095,II27096,II27097,II27108,II27109,II27110,
II27121,II27122,II27123,II27134,II27135,II27136,II27147,II27148,II27149,
II27160,II27161,II27162,II27173,II27174,II27175,II27186,II27187,II27188,
II27199,II27200,II27201,II27212,II27213,II27214,II27225,II27226,II27227,
II27238,II27239,II27240,II27251,II27252,II27253,II27264,II27265,II27266,
II27277,II27278,II27279,II27290,II27291,II27292,II27303,II27304,II27305,
II27316,II27317,II27318,II27329,II27330,II27331,II27342,II27343,II27344,
II27355,II27356,II27357,II27368,II27369,II27370,II27381,II27382,II27383,
II27394,II27395,II27396,II27407,II27408,II27409,II27420,II27421,II27422,
II27433,II27434,II27435,II27446,II27447,II27448,II27459,II27460,II27461,
II27472,II27473,II27474,II27485,II27486,II27487,II27500,II27501,II27502,
II27499,II27507,II27508,II27509,II27515,II27516,II27517,II27514,II27522,
II27523,II27524,II27530,II27531,II27532,II27529,II27537,II27538,II27539,
II27544,II27545,II27546,II27551,II27552,II27553,II27558,II27559,II27560,
II27565,II27566,II27567,II27572,II27573,II27574,II27579,II27580,II27581,
II27586,II27587,II27588,II27593,II27594,II27595,II27600,II27601,II27602,
II27607,II27608,II27609,II27614,II27615,II27616,II27621,II27622,II27623,
II27628,II27629,II27630,II27635,II27636,II27637,II27642,II27643,II27644,
II27649,II27650,II27651,II27656,II27657,II27658,II27663,II27664,II27665,
II27670,II27671,II27672,II27677,II27678,II27679,II27684,II27685,II27686,
II27691,II27692,II27693,II27698,II27699,II27700,II27705,II27706,II27707,
II27712,II27713,II27714,II27719,II27720,II27721,II27726,II27727,II27728,
II27733,II27734,II27735,II27740,II27741,II27742,II30023,II30024,II30025,
II30022,II30030,II30031,II30032,II30021,II30038,II30039,II30040,II30037,
II30045,II30046,II30047,II30054,II30055,II30056,II30053,II30061,II30062,
II30063,II30052,II30069,II30070,II30071,II30068,II30076,II30077,II30078,
II30085,II30086,II30087,II30084,II30092,II30093,II30094,II30083,II30100,
II30101,II30102,II30099,II30107,II30108,II30109,II30116,II30117,II30118,
II30115,II30123,II30124,II30125,II30114,II30131,II30132,II30133,II30130,
II30138,II30139,II30140,II30147,II30148,II30149,II30146,II30154,II30155,
II30156,II30145,II30162,II30163,II30164,II30161,II30169,II30170,II30171,
II30178,II30179,II30180,II30177,II30185,II30186,II30187,II30176,II30193,
II30194,II30195,II30192,II30200,II30201,II30202,II30209,II30210,II30211,
II30208,II30216,II30217,II30218,II30207,II30224,II30225,II30226,II30223,
II30231,II30232,II30233,II30240,II30241,II30242,II30239,II30247,II30248,
II30249,II30238,II30255,II30256,II30257,II30254,II30262,II30263,II30264,
II30271,II30272,II30273,II30270,II30278,II30279,II30280,II30269,II30286,
II30287,II30288,II30285,II30293,II30294,II30295,II30302,II30303,II30304,
II30301,II30309,II30310,II30311,II30300,II30317,II30318,II30319,II30316,
II30324,II30325,II30326,II30333,II30334,II30335,II30332,II30340,II30341,
II30342,II30331,II30348,II30349,II30350,II30347,II30355,II30356,II30357,
II30364,II30365,II30366,II30363,II30371,II30372,II30373,II30362,II30379,
II30380,II30381,II30378,II30386,II30387,II30388,II30395,II30396,II30397,
II30394,II30402,II30403,II30404,II30393,II30410,II30411,II30412,II30409,
II30417,II30418,II30419,II30426,II30427,II30428,II30425,II30433,II30434,
II30435,II30424,II30441,II30442,II30443,II30440,II30448,II30449,II30450,
II30457,II30458,II30459,II30456,II30464,II30465,II30466,II30455,II30472,
II30473,II30474,II30471,II30479,II30480,II30481,II30488,II30489,II30490,
II30487,II30495,II30496,II30497,II30486,II30503,II30504,II30505,II30502,
II30510,II30511,II30512,II30519,II30520,II30521,II30518,II30526,II30527,
II30528,II30517,II30534,II30535,II30536,II30533,II30541,II30542,II30543,
II30550,II30551,II30552,II30549,II30557,II30558,II30559,II30548,II30565,
II30566,II30567,II30564,II30572,II30573,II30574,II30581,II30582,II30583,
II30580,II30588,II30589,II30590,II30579,II30596,II30597,II30598,II30595,
II30603,II30604,II30605,II30612,II30613,II30614,II30611,II30619,II30620,
II30621,II30610,II30627,II30628,II30629,II30626,II30634,II30635,II30636,
II30643,II30644,II30645,II30642,II30650,II30651,II30652,II30641,II30658,
II30659,II30660,II30657,II30665,II30666,II30667,II30674,II30675,II30676,
II30673,II30681,II30682,II30683,II30672,II30689,II30690,II30691,II30688,
II30696,II30697,II30698,II30705,II30706,II30707,II30704,II30712,II30713,
II30714,II30703,II30720,II30721,II30722,II30719,II30727,II30728,II30729,
II30736,II30737,II30738,II30735,II30743,II30744,II30745,II30734,II30751,
II30752,II30753,II30750,II30758,II30759,II30760,II30767,II30768,II30769,
II30766,II30774,II30775,II30776,II30765,II30782,II30783,II30784,II30781,
II30789,II30790,II30791,II30798,II30799,II30800,II30797,II30805,II30806,
II30807,II30796,II30813,II30814,II30815,II30812,II30820,II30821,II30822,
II30829,II30830,II30831,II30828,II30836,II30837,II30838,II30827,II30844,
II30845,II30846,II30843,II30851,II30852,II30853,II30860,II30861,II30862,
II30859,II30867,II30868,II30869,II30858,II30875,II30876,II30877,II30874,
II30882,II30883,II30884,II30891,II30892,II30893,II30890,II30898,II30899,
II30900,II30889,II30906,II30907,II30908,II30905,II30913,II30914,II30915,
II30922,II30923,II30924,II30921,II30929,II30930,II30931,II30920,II30937,
II30938,II30939,II30936,II30944,II30945,II30946,II30953,II30954,II30955,
II30952,II30960,II30961,II30962,II30951,II30968,II30969,II30970,II30967,
II30975,II30976,II30977,II30984,II30985,II30986,II30983,II30991,II30992,
II30993,II30982,II30999,II31000,II31001,II30998,II31006,II31007,II31008,
II31087,II31088,II31089,II31100,II31101,II31102,II31113,II31114,II31115,
II31126,II31127,II31128,II31139,II31140,II31141,II31152,II31153,II31154,
II31165,II31166,II31167,II31178,II31179,II31180,II31191,II31192,II31193,
II31204,II31205,II31206,II31217,II31218,II31219,II31230,II31231,II31232,
II31243,II31244,II31245,II31256,II31257,II31258,II31269,II31270,II31271,
II31282,II31283,II31284,II31295,II31296,II31297,II31308,II31309,II31310,
II31321,II31322,II31323,II31334,II31335,II31336,II31347,II31348,II31349,
II31360,II31361,II31362,II31373,II31374,II31375,II31386,II31387,II31388,
II31399,II31400,II31401,II31412,II31413,II31414,II31425,II31426,II31427,
II31438,II31439,II31440,II31451,II31452,II31453,II31464,II31465,II31466,
II31477,II31478,II31479,II31490,II31491,II31492,II31505,II31506,II31507,
II31504,II31512,II31513,II31514,II31520,II31521,II31522,II31519,II31527,
II31528,II31529,II31535,II31536,II31537,II31534,II31542,II31543,II31544,
II31549,II31550,II31551,II31556,II31557,II31558,II31563,II31564,II31565,
II31570,II31571,II31572,II31577,II31578,II31579,II31584,II31585,II31586,
II31591,II31592,II31593,II31598,II31599,II31600,II31605,II31606,II31607,
II31612,II31613,II31614,II31619,II31620,II31621,II31626,II31627,II31628,
II31633,II31634,II31635,II31640,II31641,II31642,II31647,II31648,II31649,
II31654,II31655,II31656,II31661,II31662,II31663,II31668,II31669,II31670,
II31675,II31676,II31677,II31682,II31683,II31684,II31689,II31690,II31691,
II31696,II31697,II31698,II31703,II31704,II31705,II31710,II31711,II31712,
II31717,II31718,II31719,II31724,II31725,II31726,II31731,II31732,II31733,
II31738,II31739,II31740,II31745,II31746,II31747,II34028,II34029,II34030,
II34027,II34035,II34036,II34037,II34026,II34043,II34044,II34045,II34042,
II34050,II34051,II34052,II34059,II34060,II34061,II34058,II34066,II34067,
II34068,II34057,II34074,II34075,II34076,II34073,II34081,II34082,II34083,
II34090,II34091,II34092,II34089,II34097,II34098,II34099,II34088,II34105,
II34106,II34107,II34104,II34112,II34113,II34114,II34121,II34122,II34123,
II34120,II34128,II34129,II34130,II34119,II34136,II34137,II34138,II34135,
II34143,II34144,II34145,II34152,II34153,II34154,II34151,II34159,II34160,
II34161,II34150,II34167,II34168,II34169,II34166,II34174,II34175,II34176,
II34183,II34184,II34185,II34182,II34190,II34191,II34192,II34181,II34198,
II34199,II34200,II34197,II34205,II34206,II34207,II34214,II34215,II34216,
II34213,II34221,II34222,II34223,II34212,II34229,II34230,II34231,II34228,
II34236,II34237,II34238,II34245,II34246,II34247,II34244,II34252,II34253,
II34254,II34243,II34260,II34261,II34262,II34259,II34267,II34268,II34269,
II34276,II34277,II34278,II34275,II34283,II34284,II34285,II34274,II34291,
II34292,II34293,II34290,II34298,II34299,II34300,II34307,II34308,II34309,
II34306,II34314,II34315,II34316,II34305,II34322,II34323,II34324,II34321,
II34329,II34330,II34331,II34338,II34339,II34340,II34337,II34345,II34346,
II34347,II34336,II34353,II34354,II34355,II34352,II34360,II34361,II34362,
II34369,II34370,II34371,II34368,II34376,II34377,II34378,II34367,II34384,
II34385,II34386,II34383,II34391,II34392,II34393,II34400,II34401,II34402,
II34399,II34407,II34408,II34409,II34398,II34415,II34416,II34417,II34414,
II34422,II34423,II34424,II34431,II34432,II34433,II34430,II34438,II34439,
II34440,II34429,II34446,II34447,II34448,II34445,II34453,II34454,II34455,
II34462,II34463,II34464,II34461,II34469,II34470,II34471,II34460,II34477,
II34478,II34479,II34476,II34484,II34485,II34486,II34493,II34494,II34495,
II34492,II34500,II34501,II34502,II34491,II34508,II34509,II34510,II34507,
II34515,II34516,II34517,II34524,II34525,II34526,II34523,II34531,II34532,
II34533,II34522,II34539,II34540,II34541,II34538,II34546,II34547,II34548,
II34555,II34556,II34557,II34554,II34562,II34563,II34564,II34553,II34570,
II34571,II34572,II34569,II34577,II34578,II34579,II34586,II34587,II34588,
II34585,II34593,II34594,II34595,II34584,II34601,II34602,II34603,II34600,
II34608,II34609,II34610,II34617,II34618,II34619,II34616,II34624,II34625,
II34626,II34615,II34632,II34633,II34634,II34631,II34639,II34640,II34641,
II34648,II34649,II34650,II34647,II34655,II34656,II34657,II34646,II34663,
II34664,II34665,II34662,II34670,II34671,II34672,II34679,II34680,II34681,
II34678,II34686,II34687,II34688,II34677,II34694,II34695,II34696,II34693,
II34701,II34702,II34703,II34710,II34711,II34712,II34709,II34717,II34718,
II34719,II34708,II34725,II34726,II34727,II34724,II34732,II34733,II34734,
II34741,II34742,II34743,II34740,II34748,II34749,II34750,II34739,II34756,
II34757,II34758,II34755,II34763,II34764,II34765,II34772,II34773,II34774,
II34771,II34779,II34780,II34781,II34770,II34787,II34788,II34789,II34786,
II34794,II34795,II34796,II34803,II34804,II34805,II34802,II34810,II34811,
II34812,II34801,II34818,II34819,II34820,II34817,II34825,II34826,II34827,
II34834,II34835,II34836,II34833,II34841,II34842,II34843,II34832,II34849,
II34850,II34851,II34848,II34856,II34857,II34858,II34865,II34866,II34867,
II34864,II34872,II34873,II34874,II34863,II34880,II34881,II34882,II34879,
II34887,II34888,II34889,II34896,II34897,II34898,II34895,II34903,II34904,
II34905,II34894,II34911,II34912,II34913,II34910,II34918,II34919,II34920,
II34927,II34928,II34929,II34926,II34934,II34935,II34936,II34925,II34942,
II34943,II34944,II34941,II34949,II34950,II34951,II34958,II34959,II34960,
II34957,II34965,II34966,II34967,II34956,II34973,II34974,II34975,II34972,
II34980,II34981,II34982,II34989,II34990,II34991,II34988,II34996,II34997,
II34998,II34987,II35004,II35005,II35006,II35003,II35011,II35012,II35013,
II35092,II35093,II35094,II35105,II35106,II35107,II35118,II35119,II35120,
II35131,II35132,II35133,II35144,II35145,II35146,II35157,II35158,II35159,
II35170,II35171,II35172,II35183,II35184,II35185,II35196,II35197,II35198,
II35209,II35210,II35211,II35222,II35223,II35224,II35235,II35236,II35237,
II35248,II35249,II35250,II35261,II35262,II35263,II35274,II35275,II35276,
II35287,II35288,II35289,II35300,II35301,II35302,II35313,II35314,II35315,
II35326,II35327,II35328,II35339,II35340,II35341,II35352,II35353,II35354,
II35365,II35366,II35367,II35378,II35379,II35380,II35391,II35392,II35393,
II35404,II35405,II35406,II35417,II35418,II35419,II35430,II35431,II35432,
II35443,II35444,II35445,II35456,II35457,II35458,II35469,II35470,II35471,
II35482,II35483,II35484,II35495,II35496,II35497,II35510,II35511,II35512,
II35509,II35517,II35518,II35519,II35525,II35526,II35527,II35524,II35532,
II35533,II35534,II35540,II35541,II35542,II35539,II35547,II35548,II35549,
II35554,II35555,II35556,II35561,II35562,II35563,II35568,II35569,II35570,
II35575,II35576,II35577,II35582,II35583,II35584,II35589,II35590,II35591,
II35596,II35597,II35598,II35603,II35604,II35605,II35610,II35611,II35612,
II35617,II35618,II35619,II35624,II35625,II35626,II35631,II35632,II35633,
II35638,II35639,II35640,II35645,II35646,II35647,II35652,II35653,II35654,
II35659,II35660,II35661,II35666,II35667,II35668,II35673,II35674,II35675,
II35680,II35681,II35682,II35687,II35688,II35689,II35694,II35695,II35696,
II35701,II35702,II35703,II35708,II35709,II35710,II35715,II35716,II35717,
II35722,II35723,II35724,II35729,II35730,II35731,II35736,II35737,II35738,
II35743,II35744,II35745,II35750,II35751,II35752;
dff DFF_0(CK,WX485,WX484);
dff DFF_1(CK,WX487,WX486);
dff DFF_2(CK,WX489,WX488);
dff DFF_3(CK,WX491,WX490);
dff DFF_4(CK,WX493,WX492);
dff DFF_5(CK,WX495,WX494);
dff DFF_6(CK,WX497,WX496);
dff DFF_7(CK,WX499,WX498);
dff DFF_8(CK,WX501,WX500);
dff DFF_9(CK,WX503,WX502);
dff DFF_10(CK,WX505,WX504);
dff DFF_11(CK,WX507,WX506);
dff DFF_12(CK,WX509,WX508);
dff DFF_13(CK,WX511,WX510);
dff DFF_14(CK,WX513,WX512);
dff DFF_15(CK,WX515,WX514);
dff DFF_16(CK,WX517,WX516);
dff DFF_17(CK,WX519,WX518);
dff DFF_18(CK,WX521,WX520);
dff DFF_19(CK,WX523,WX522);
dff DFF_20(CK,WX525,WX524);
dff DFF_21(CK,WX527,WX526);
dff DFF_22(CK,WX529,WX528);
dff DFF_23(CK,WX531,WX530);
dff DFF_24(CK,WX533,WX532);
dff DFF_25(CK,WX535,WX534);
dff DFF_26(CK,WX537,WX536);
dff DFF_27(CK,WX539,WX538);
dff DFF_28(CK,WX541,WX540);
dff DFF_29(CK,WX543,WX542);
dff DFF_30(CK,WX545,WX544);
dff DFF_31(CK,WX547,WX546);
dff DFF_32(CK,WX645,WX644);
dff DFF_33(CK,WX647,WX646);
dff DFF_34(CK,WX649,WX648);
dff DFF_35(CK,WX651,WX650);
dff DFF_36(CK,WX653,WX652);
dff DFF_37(CK,WX655,WX654);
dff DFF_38(CK,WX657,WX656);
dff DFF_39(CK,WX659,WX658);
dff DFF_40(CK,WX661,WX660);
dff DFF_41(CK,WX663,WX662);
dff DFF_42(CK,WX665,WX664);
dff DFF_43(CK,WX667,WX666);
dff DFF_44(CK,WX669,WX668);
dff DFF_45(CK,WX671,WX670);
dff DFF_46(CK,WX673,WX672);
dff DFF_47(CK,WX675,WX674);
dff DFF_48(CK,WX677,WX676);
dff DFF_49(CK,WX679,WX678);
dff DFF_50(CK,WX681,WX680);
dff DFF_51(CK,WX683,WX682);
dff DFF_52(CK,WX685,WX684);
dff DFF_53(CK,WX687,WX686);
dff DFF_54(CK,WX689,WX688);
dff DFF_55(CK,WX691,WX690);
dff DFF_56(CK,WX693,WX692);
dff DFF_57(CK,WX695,WX694);
dff DFF_58(CK,WX697,WX696);
dff DFF_59(CK,WX699,WX698);
dff DFF_60(CK,WX701,WX700);
dff DFF_61(CK,WX703,WX702);
dff DFF_62(CK,WX705,WX704);
dff DFF_63(CK,WX707,WX706);
dff DFF_64(CK,WX709,WX708);
dff DFF_65(CK,WX711,WX710);
dff DFF_66(CK,WX713,WX712);
dff DFF_67(CK,WX715,WX714);
dff DFF_68(CK,WX717,WX716);
dff DFF_69(CK,WX719,WX718);
dff DFF_70(CK,WX721,WX720);
dff DFF_71(CK,WX723,WX722);
dff DFF_72(CK,WX725,WX724);
dff DFF_73(CK,WX727,WX726);
dff DFF_74(CK,WX729,WX728);
dff DFF_75(CK,WX731,WX730);
dff DFF_76(CK,WX733,WX732);
dff DFF_77(CK,WX735,WX734);
dff DFF_78(CK,WX737,WX736);
dff DFF_79(CK,WX739,WX738);
dff DFF_80(CK,WX741,WX740);
dff DFF_81(CK,WX743,WX742);
dff DFF_82(CK,WX745,WX744);
dff DFF_83(CK,WX747,WX746);
dff DFF_84(CK,WX749,WX748);
dff DFF_85(CK,WX751,WX750);
dff DFF_86(CK,WX753,WX752);
dff DFF_87(CK,WX755,WX754);
dff DFF_88(CK,WX757,WX756);
dff DFF_89(CK,WX759,WX758);
dff DFF_90(CK,WX761,WX760);
dff DFF_91(CK,WX763,WX762);
dff DFF_92(CK,WX765,WX764);
dff DFF_93(CK,WX767,WX766);
dff DFF_94(CK,WX769,WX768);
dff DFF_95(CK,WX771,WX770);
dff DFF_96(CK,WX773,WX772);
dff DFF_97(CK,WX775,WX774);
dff DFF_98(CK,WX777,WX776);
dff DFF_99(CK,WX779,WX778);
dff DFF_100(CK,WX781,WX780);
dff DFF_101(CK,WX783,WX782);
dff DFF_102(CK,WX785,WX784);
dff DFF_103(CK,WX787,WX786);
dff DFF_104(CK,WX789,WX788);
dff DFF_105(CK,WX791,WX790);
dff DFF_106(CK,WX793,WX792);
dff DFF_107(CK,WX795,WX794);
dff DFF_108(CK,WX797,WX796);
dff DFF_109(CK,WX799,WX798);
dff DFF_110(CK,WX801,WX800);
dff DFF_111(CK,WX803,WX802);
dff DFF_112(CK,WX805,WX804);
dff DFF_113(CK,WX807,WX806);
dff DFF_114(CK,WX809,WX808);
dff DFF_115(CK,WX811,WX810);
dff DFF_116(CK,WX813,WX812);
dff DFF_117(CK,WX815,WX814);
dff DFF_118(CK,WX817,WX816);
dff DFF_119(CK,WX819,WX818);
dff DFF_120(CK,WX821,WX820);
dff DFF_121(CK,WX823,WX822);
dff DFF_122(CK,WX825,WX824);
dff DFF_123(CK,WX827,WX826);
dff DFF_124(CK,WX829,WX828);
dff DFF_125(CK,WX831,WX830);
dff DFF_126(CK,WX833,WX832);
dff DFF_127(CK,WX835,WX834);
dff DFF_128(CK,WX837,WX836);
dff DFF_129(CK,WX839,WX838);
dff DFF_130(CK,WX841,WX840);
dff DFF_131(CK,WX843,WX842);
dff DFF_132(CK,WX845,WX844);
dff DFF_133(CK,WX847,WX846);
dff DFF_134(CK,WX849,WX848);
dff DFF_135(CK,WX851,WX850);
dff DFF_136(CK,WX853,WX852);
dff DFF_137(CK,WX855,WX854);
dff DFF_138(CK,WX857,WX856);
dff DFF_139(CK,WX859,WX858);
dff DFF_140(CK,WX861,WX860);
dff DFF_141(CK,WX863,WX862);
dff DFF_142(CK,WX865,WX864);
dff DFF_143(CK,WX867,WX866);
dff DFF_144(CK,WX869,WX868);
dff DFF_145(CK,WX871,WX870);
dff DFF_146(CK,WX873,WX872);
dff DFF_147(CK,WX875,WX874);
dff DFF_148(CK,WX877,WX876);
dff DFF_149(CK,WX879,WX878);
dff DFF_150(CK,WX881,WX880);
dff DFF_151(CK,WX883,WX882);
dff DFF_152(CK,WX885,WX884);
dff DFF_153(CK,WX887,WX886);
dff DFF_154(CK,WX889,WX888);
dff DFF_155(CK,WX891,WX890);
dff DFF_156(CK,WX893,WX892);
dff DFF_157(CK,WX895,WX894);
dff DFF_158(CK,WX897,WX896);
dff DFF_159(CK,WX899,WX898);
dff DFF_160(CK,CRC_OUT_9_0,WX1264);
dff DFF_161(CK,CRC_OUT_9_1,WX1266);
dff DFF_162(CK,CRC_OUT_9_2,WX1268);
dff DFF_163(CK,CRC_OUT_9_3,WX1270);
dff DFF_164(CK,CRC_OUT_9_4,WX1272);
dff DFF_165(CK,CRC_OUT_9_5,WX1274);
dff DFF_166(CK,CRC_OUT_9_6,WX1276);
dff DFF_167(CK,CRC_OUT_9_7,WX1278);
dff DFF_168(CK,CRC_OUT_9_8,WX1280);
dff DFF_169(CK,CRC_OUT_9_9,WX1282);
dff DFF_170(CK,CRC_OUT_9_10,WX1284);
dff DFF_171(CK,CRC_OUT_9_11,WX1286);
dff DFF_172(CK,CRC_OUT_9_12,WX1288);
dff DFF_173(CK,CRC_OUT_9_13,WX1290);
dff DFF_174(CK,CRC_OUT_9_14,WX1292);
dff DFF_175(CK,CRC_OUT_9_15,WX1294);
dff DFF_176(CK,CRC_OUT_9_16,WX1296);
dff DFF_177(CK,CRC_OUT_9_17,WX1298);
dff DFF_178(CK,CRC_OUT_9_18,WX1300);
dff DFF_179(CK,CRC_OUT_9_19,WX1302);
dff DFF_180(CK,CRC_OUT_9_20,WX1304);
dff DFF_181(CK,CRC_OUT_9_21,WX1306);
dff DFF_182(CK,CRC_OUT_9_22,WX1308);
dff DFF_183(CK,CRC_OUT_9_23,WX1310);
dff DFF_184(CK,CRC_OUT_9_24,WX1312);
dff DFF_185(CK,CRC_OUT_9_25,WX1314);
dff DFF_186(CK,CRC_OUT_9_26,WX1316);
dff DFF_187(CK,CRC_OUT_9_27,WX1318);
dff DFF_188(CK,CRC_OUT_9_28,WX1320);
dff DFF_189(CK,CRC_OUT_9_29,WX1322);
dff DFF_190(CK,CRC_OUT_9_30,WX1324);
dff DFF_191(CK,CRC_OUT_9_31,WX1326);
dff DFF_192(CK,WX1778,WX1777);
dff DFF_193(CK,WX1780,WX1779);
dff DFF_194(CK,WX1782,WX1781);
dff DFF_195(CK,WX1784,WX1783);
dff DFF_196(CK,WX1786,WX1785);
dff DFF_197(CK,WX1788,WX1787);
dff DFF_198(CK,WX1790,WX1789);
dff DFF_199(CK,WX1792,WX1791);
dff DFF_200(CK,WX1794,WX1793);
dff DFF_201(CK,WX1796,WX1795);
dff DFF_202(CK,WX1798,WX1797);
dff DFF_203(CK,WX1800,WX1799);
dff DFF_204(CK,WX1802,WX1801);
dff DFF_205(CK,WX1804,WX1803);
dff DFF_206(CK,WX1806,WX1805);
dff DFF_207(CK,WX1808,WX1807);
dff DFF_208(CK,WX1810,WX1809);
dff DFF_209(CK,WX1812,WX1811);
dff DFF_210(CK,WX1814,WX1813);
dff DFF_211(CK,WX1816,WX1815);
dff DFF_212(CK,WX1818,WX1817);
dff DFF_213(CK,WX1820,WX1819);
dff DFF_214(CK,WX1822,WX1821);
dff DFF_215(CK,WX1824,WX1823);
dff DFF_216(CK,WX1826,WX1825);
dff DFF_217(CK,WX1828,WX1827);
dff DFF_218(CK,WX1830,WX1829);
dff DFF_219(CK,WX1832,WX1831);
dff DFF_220(CK,WX1834,WX1833);
dff DFF_221(CK,WX1836,WX1835);
dff DFF_222(CK,WX1838,WX1837);
dff DFF_223(CK,WX1840,WX1839);
dff DFF_224(CK,WX1938,WX1937);
dff DFF_225(CK,WX1940,WX1939);
dff DFF_226(CK,WX1942,WX1941);
dff DFF_227(CK,WX1944,WX1943);
dff DFF_228(CK,WX1946,WX1945);
dff DFF_229(CK,WX1948,WX1947);
dff DFF_230(CK,WX1950,WX1949);
dff DFF_231(CK,WX1952,WX1951);
dff DFF_232(CK,WX1954,WX1953);
dff DFF_233(CK,WX1956,WX1955);
dff DFF_234(CK,WX1958,WX1957);
dff DFF_235(CK,WX1960,WX1959);
dff DFF_236(CK,WX1962,WX1961);
dff DFF_237(CK,WX1964,WX1963);
dff DFF_238(CK,WX1966,WX1965);
dff DFF_239(CK,WX1968,WX1967);
dff DFF_240(CK,WX1970,WX1969);
dff DFF_241(CK,WX1972,WX1971);
dff DFF_242(CK,WX1974,WX1973);
dff DFF_243(CK,WX1976,WX1975);
dff DFF_244(CK,WX1978,WX1977);
dff DFF_245(CK,WX1980,WX1979);
dff DFF_246(CK,WX1982,WX1981);
dff DFF_247(CK,WX1984,WX1983);
dff DFF_248(CK,WX1986,WX1985);
dff DFF_249(CK,WX1988,WX1987);
dff DFF_250(CK,WX1990,WX1989);
dff DFF_251(CK,WX1992,WX1991);
dff DFF_252(CK,WX1994,WX1993);
dff DFF_253(CK,WX1996,WX1995);
dff DFF_254(CK,WX1998,WX1997);
dff DFF_255(CK,WX2000,WX1999);
dff DFF_256(CK,WX2002,WX2001);
dff DFF_257(CK,WX2004,WX2003);
dff DFF_258(CK,WX2006,WX2005);
dff DFF_259(CK,WX2008,WX2007);
dff DFF_260(CK,WX2010,WX2009);
dff DFF_261(CK,WX2012,WX2011);
dff DFF_262(CK,WX2014,WX2013);
dff DFF_263(CK,WX2016,WX2015);
dff DFF_264(CK,WX2018,WX2017);
dff DFF_265(CK,WX2020,WX2019);
dff DFF_266(CK,WX2022,WX2021);
dff DFF_267(CK,WX2024,WX2023);
dff DFF_268(CK,WX2026,WX2025);
dff DFF_269(CK,WX2028,WX2027);
dff DFF_270(CK,WX2030,WX2029);
dff DFF_271(CK,WX2032,WX2031);
dff DFF_272(CK,WX2034,WX2033);
dff DFF_273(CK,WX2036,WX2035);
dff DFF_274(CK,WX2038,WX2037);
dff DFF_275(CK,WX2040,WX2039);
dff DFF_276(CK,WX2042,WX2041);
dff DFF_277(CK,WX2044,WX2043);
dff DFF_278(CK,WX2046,WX2045);
dff DFF_279(CK,WX2048,WX2047);
dff DFF_280(CK,WX2050,WX2049);
dff DFF_281(CK,WX2052,WX2051);
dff DFF_282(CK,WX2054,WX2053);
dff DFF_283(CK,WX2056,WX2055);
dff DFF_284(CK,WX2058,WX2057);
dff DFF_285(CK,WX2060,WX2059);
dff DFF_286(CK,WX2062,WX2061);
dff DFF_287(CK,WX2064,WX2063);
dff DFF_288(CK,WX2066,WX2065);
dff DFF_289(CK,WX2068,WX2067);
dff DFF_290(CK,WX2070,WX2069);
dff DFF_291(CK,WX2072,WX2071);
dff DFF_292(CK,WX2074,WX2073);
dff DFF_293(CK,WX2076,WX2075);
dff DFF_294(CK,WX2078,WX2077);
dff DFF_295(CK,WX2080,WX2079);
dff DFF_296(CK,WX2082,WX2081);
dff DFF_297(CK,WX2084,WX2083);
dff DFF_298(CK,WX2086,WX2085);
dff DFF_299(CK,WX2088,WX2087);
dff DFF_300(CK,WX2090,WX2089);
dff DFF_301(CK,WX2092,WX2091);
dff DFF_302(CK,WX2094,WX2093);
dff DFF_303(CK,WX2096,WX2095);
dff DFF_304(CK,WX2098,WX2097);
dff DFF_305(CK,WX2100,WX2099);
dff DFF_306(CK,WX2102,WX2101);
dff DFF_307(CK,WX2104,WX2103);
dff DFF_308(CK,WX2106,WX2105);
dff DFF_309(CK,WX2108,WX2107);
dff DFF_310(CK,WX2110,WX2109);
dff DFF_311(CK,WX2112,WX2111);
dff DFF_312(CK,WX2114,WX2113);
dff DFF_313(CK,WX2116,WX2115);
dff DFF_314(CK,WX2118,WX2117);
dff DFF_315(CK,WX2120,WX2119);
dff DFF_316(CK,WX2122,WX2121);
dff DFF_317(CK,WX2124,WX2123);
dff DFF_318(CK,WX2126,WX2125);
dff DFF_319(CK,WX2128,WX2127);
dff DFF_320(CK,WX2130,WX2129);
dff DFF_321(CK,WX2132,WX2131);
dff DFF_322(CK,WX2134,WX2133);
dff DFF_323(CK,WX2136,WX2135);
dff DFF_324(CK,WX2138,WX2137);
dff DFF_325(CK,WX2140,WX2139);
dff DFF_326(CK,WX2142,WX2141);
dff DFF_327(CK,WX2144,WX2143);
dff DFF_328(CK,WX2146,WX2145);
dff DFF_329(CK,WX2148,WX2147);
dff DFF_330(CK,WX2150,WX2149);
dff DFF_331(CK,WX2152,WX2151);
dff DFF_332(CK,WX2154,WX2153);
dff DFF_333(CK,WX2156,WX2155);
dff DFF_334(CK,WX2158,WX2157);
dff DFF_335(CK,WX2160,WX2159);
dff DFF_336(CK,WX2162,WX2161);
dff DFF_337(CK,WX2164,WX2163);
dff DFF_338(CK,WX2166,WX2165);
dff DFF_339(CK,WX2168,WX2167);
dff DFF_340(CK,WX2170,WX2169);
dff DFF_341(CK,WX2172,WX2171);
dff DFF_342(CK,WX2174,WX2173);
dff DFF_343(CK,WX2176,WX2175);
dff DFF_344(CK,WX2178,WX2177);
dff DFF_345(CK,WX2180,WX2179);
dff DFF_346(CK,WX2182,WX2181);
dff DFF_347(CK,WX2184,WX2183);
dff DFF_348(CK,WX2186,WX2185);
dff DFF_349(CK,WX2188,WX2187);
dff DFF_350(CK,WX2190,WX2189);
dff DFF_351(CK,WX2192,WX2191);
dff DFF_352(CK,CRC_OUT_8_0,WX2557);
dff DFF_353(CK,CRC_OUT_8_1,WX2559);
dff DFF_354(CK,CRC_OUT_8_2,WX2561);
dff DFF_355(CK,CRC_OUT_8_3,WX2563);
dff DFF_356(CK,CRC_OUT_8_4,WX2565);
dff DFF_357(CK,CRC_OUT_8_5,WX2567);
dff DFF_358(CK,CRC_OUT_8_6,WX2569);
dff DFF_359(CK,CRC_OUT_8_7,WX2571);
dff DFF_360(CK,CRC_OUT_8_8,WX2573);
dff DFF_361(CK,CRC_OUT_8_9,WX2575);
dff DFF_362(CK,CRC_OUT_8_10,WX2577);
dff DFF_363(CK,CRC_OUT_8_11,WX2579);
dff DFF_364(CK,CRC_OUT_8_12,WX2581);
dff DFF_365(CK,CRC_OUT_8_13,WX2583);
dff DFF_366(CK,CRC_OUT_8_14,WX2585);
dff DFF_367(CK,CRC_OUT_8_15,WX2587);
dff DFF_368(CK,CRC_OUT_8_16,WX2589);
dff DFF_369(CK,CRC_OUT_8_17,WX2591);
dff DFF_370(CK,CRC_OUT_8_18,WX2593);
dff DFF_371(CK,CRC_OUT_8_19,WX2595);
dff DFF_372(CK,CRC_OUT_8_20,WX2597);
dff DFF_373(CK,CRC_OUT_8_21,WX2599);
dff DFF_374(CK,CRC_OUT_8_22,WX2601);
dff DFF_375(CK,CRC_OUT_8_23,WX2603);
dff DFF_376(CK,CRC_OUT_8_24,WX2605);
dff DFF_377(CK,CRC_OUT_8_25,WX2607);
dff DFF_378(CK,CRC_OUT_8_26,WX2609);
dff DFF_379(CK,CRC_OUT_8_27,WX2611);
dff DFF_380(CK,CRC_OUT_8_28,WX2613);
dff DFF_381(CK,CRC_OUT_8_29,WX2615);
dff DFF_382(CK,CRC_OUT_8_30,WX2617);
dff DFF_383(CK,CRC_OUT_8_31,WX2619);
dff DFF_384(CK,WX3071,WX3070);
dff DFF_385(CK,WX3073,WX3072);
dff DFF_386(CK,WX3075,WX3074);
dff DFF_387(CK,WX3077,WX3076);
dff DFF_388(CK,WX3079,WX3078);
dff DFF_389(CK,WX3081,WX3080);
dff DFF_390(CK,WX3083,WX3082);
dff DFF_391(CK,WX3085,WX3084);
dff DFF_392(CK,WX3087,WX3086);
dff DFF_393(CK,WX3089,WX3088);
dff DFF_394(CK,WX3091,WX3090);
dff DFF_395(CK,WX3093,WX3092);
dff DFF_396(CK,WX3095,WX3094);
dff DFF_397(CK,WX3097,WX3096);
dff DFF_398(CK,WX3099,WX3098);
dff DFF_399(CK,WX3101,WX3100);
dff DFF_400(CK,WX3103,WX3102);
dff DFF_401(CK,WX3105,WX3104);
dff DFF_402(CK,WX3107,WX3106);
dff DFF_403(CK,WX3109,WX3108);
dff DFF_404(CK,WX3111,WX3110);
dff DFF_405(CK,WX3113,WX3112);
dff DFF_406(CK,WX3115,WX3114);
dff DFF_407(CK,WX3117,WX3116);
dff DFF_408(CK,WX3119,WX3118);
dff DFF_409(CK,WX3121,WX3120);
dff DFF_410(CK,WX3123,WX3122);
dff DFF_411(CK,WX3125,WX3124);
dff DFF_412(CK,WX3127,WX3126);
dff DFF_413(CK,WX3129,WX3128);
dff DFF_414(CK,WX3131,WX3130);
dff DFF_415(CK,WX3133,WX3132);
dff DFF_416(CK,WX3231,WX3230);
dff DFF_417(CK,WX3233,WX3232);
dff DFF_418(CK,WX3235,WX3234);
dff DFF_419(CK,WX3237,WX3236);
dff DFF_420(CK,WX3239,WX3238);
dff DFF_421(CK,WX3241,WX3240);
dff DFF_422(CK,WX3243,WX3242);
dff DFF_423(CK,WX3245,WX3244);
dff DFF_424(CK,WX3247,WX3246);
dff DFF_425(CK,WX3249,WX3248);
dff DFF_426(CK,WX3251,WX3250);
dff DFF_427(CK,WX3253,WX3252);
dff DFF_428(CK,WX3255,WX3254);
dff DFF_429(CK,WX3257,WX3256);
dff DFF_430(CK,WX3259,WX3258);
dff DFF_431(CK,WX3261,WX3260);
dff DFF_432(CK,WX3263,WX3262);
dff DFF_433(CK,WX3265,WX3264);
dff DFF_434(CK,WX3267,WX3266);
dff DFF_435(CK,WX3269,WX3268);
dff DFF_436(CK,WX3271,WX3270);
dff DFF_437(CK,WX3273,WX3272);
dff DFF_438(CK,WX3275,WX3274);
dff DFF_439(CK,WX3277,WX3276);
dff DFF_440(CK,WX3279,WX3278);
dff DFF_441(CK,WX3281,WX3280);
dff DFF_442(CK,WX3283,WX3282);
dff DFF_443(CK,WX3285,WX3284);
dff DFF_444(CK,WX3287,WX3286);
dff DFF_445(CK,WX3289,WX3288);
dff DFF_446(CK,WX3291,WX3290);
dff DFF_447(CK,WX3293,WX3292);
dff DFF_448(CK,WX3295,WX3294);
dff DFF_449(CK,WX3297,WX3296);
dff DFF_450(CK,WX3299,WX3298);
dff DFF_451(CK,WX3301,WX3300);
dff DFF_452(CK,WX3303,WX3302);
dff DFF_453(CK,WX3305,WX3304);
dff DFF_454(CK,WX3307,WX3306);
dff DFF_455(CK,WX3309,WX3308);
dff DFF_456(CK,WX3311,WX3310);
dff DFF_457(CK,WX3313,WX3312);
dff DFF_458(CK,WX3315,WX3314);
dff DFF_459(CK,WX3317,WX3316);
dff DFF_460(CK,WX3319,WX3318);
dff DFF_461(CK,WX3321,WX3320);
dff DFF_462(CK,WX3323,WX3322);
dff DFF_463(CK,WX3325,WX3324);
dff DFF_464(CK,WX3327,WX3326);
dff DFF_465(CK,WX3329,WX3328);
dff DFF_466(CK,WX3331,WX3330);
dff DFF_467(CK,WX3333,WX3332);
dff DFF_468(CK,WX3335,WX3334);
dff DFF_469(CK,WX3337,WX3336);
dff DFF_470(CK,WX3339,WX3338);
dff DFF_471(CK,WX3341,WX3340);
dff DFF_472(CK,WX3343,WX3342);
dff DFF_473(CK,WX3345,WX3344);
dff DFF_474(CK,WX3347,WX3346);
dff DFF_475(CK,WX3349,WX3348);
dff DFF_476(CK,WX3351,WX3350);
dff DFF_477(CK,WX3353,WX3352);
dff DFF_478(CK,WX3355,WX3354);
dff DFF_479(CK,WX3357,WX3356);
dff DFF_480(CK,WX3359,WX3358);
dff DFF_481(CK,WX3361,WX3360);
dff DFF_482(CK,WX3363,WX3362);
dff DFF_483(CK,WX3365,WX3364);
dff DFF_484(CK,WX3367,WX3366);
dff DFF_485(CK,WX3369,WX3368);
dff DFF_486(CK,WX3371,WX3370);
dff DFF_487(CK,WX3373,WX3372);
dff DFF_488(CK,WX3375,WX3374);
dff DFF_489(CK,WX3377,WX3376);
dff DFF_490(CK,WX3379,WX3378);
dff DFF_491(CK,WX3381,WX3380);
dff DFF_492(CK,WX3383,WX3382);
dff DFF_493(CK,WX3385,WX3384);
dff DFF_494(CK,WX3387,WX3386);
dff DFF_495(CK,WX3389,WX3388);
dff DFF_496(CK,WX3391,WX3390);
dff DFF_497(CK,WX3393,WX3392);
dff DFF_498(CK,WX3395,WX3394);
dff DFF_499(CK,WX3397,WX3396);
dff DFF_500(CK,WX3399,WX3398);
dff DFF_501(CK,WX3401,WX3400);
dff DFF_502(CK,WX3403,WX3402);
dff DFF_503(CK,WX3405,WX3404);
dff DFF_504(CK,WX3407,WX3406);
dff DFF_505(CK,WX3409,WX3408);
dff DFF_506(CK,WX3411,WX3410);
dff DFF_507(CK,WX3413,WX3412);
dff DFF_508(CK,WX3415,WX3414);
dff DFF_509(CK,WX3417,WX3416);
dff DFF_510(CK,WX3419,WX3418);
dff DFF_511(CK,WX3421,WX3420);
dff DFF_512(CK,WX3423,WX3422);
dff DFF_513(CK,WX3425,WX3424);
dff DFF_514(CK,WX3427,WX3426);
dff DFF_515(CK,WX3429,WX3428);
dff DFF_516(CK,WX3431,WX3430);
dff DFF_517(CK,WX3433,WX3432);
dff DFF_518(CK,WX3435,WX3434);
dff DFF_519(CK,WX3437,WX3436);
dff DFF_520(CK,WX3439,WX3438);
dff DFF_521(CK,WX3441,WX3440);
dff DFF_522(CK,WX3443,WX3442);
dff DFF_523(CK,WX3445,WX3444);
dff DFF_524(CK,WX3447,WX3446);
dff DFF_525(CK,WX3449,WX3448);
dff DFF_526(CK,WX3451,WX3450);
dff DFF_527(CK,WX3453,WX3452);
dff DFF_528(CK,WX3455,WX3454);
dff DFF_529(CK,WX3457,WX3456);
dff DFF_530(CK,WX3459,WX3458);
dff DFF_531(CK,WX3461,WX3460);
dff DFF_532(CK,WX3463,WX3462);
dff DFF_533(CK,WX3465,WX3464);
dff DFF_534(CK,WX3467,WX3466);
dff DFF_535(CK,WX3469,WX3468);
dff DFF_536(CK,WX3471,WX3470);
dff DFF_537(CK,WX3473,WX3472);
dff DFF_538(CK,WX3475,WX3474);
dff DFF_539(CK,WX3477,WX3476);
dff DFF_540(CK,WX3479,WX3478);
dff DFF_541(CK,WX3481,WX3480);
dff DFF_542(CK,WX3483,WX3482);
dff DFF_543(CK,WX3485,WX3484);
dff DFF_544(CK,CRC_OUT_7_0,WX3850);
dff DFF_545(CK,CRC_OUT_7_1,WX3852);
dff DFF_546(CK,CRC_OUT_7_2,WX3854);
dff DFF_547(CK,CRC_OUT_7_3,WX3856);
dff DFF_548(CK,CRC_OUT_7_4,WX3858);
dff DFF_549(CK,CRC_OUT_7_5,WX3860);
dff DFF_550(CK,CRC_OUT_7_6,WX3862);
dff DFF_551(CK,CRC_OUT_7_7,WX3864);
dff DFF_552(CK,CRC_OUT_7_8,WX3866);
dff DFF_553(CK,CRC_OUT_7_9,WX3868);
dff DFF_554(CK,CRC_OUT_7_10,WX3870);
dff DFF_555(CK,CRC_OUT_7_11,WX3872);
dff DFF_556(CK,CRC_OUT_7_12,WX3874);
dff DFF_557(CK,CRC_OUT_7_13,WX3876);
dff DFF_558(CK,CRC_OUT_7_14,WX3878);
dff DFF_559(CK,CRC_OUT_7_15,WX3880);
dff DFF_560(CK,CRC_OUT_7_16,WX3882);
dff DFF_561(CK,CRC_OUT_7_17,WX3884);
dff DFF_562(CK,CRC_OUT_7_18,WX3886);
dff DFF_563(CK,CRC_OUT_7_19,WX3888);
dff DFF_564(CK,CRC_OUT_7_20,WX3890);
dff DFF_565(CK,CRC_OUT_7_21,WX3892);
dff DFF_566(CK,CRC_OUT_7_22,WX3894);
dff DFF_567(CK,CRC_OUT_7_23,WX3896);
dff DFF_568(CK,CRC_OUT_7_24,WX3898);
dff DFF_569(CK,CRC_OUT_7_25,WX3900);
dff DFF_570(CK,CRC_OUT_7_26,WX3902);
dff DFF_571(CK,CRC_OUT_7_27,WX3904);
dff DFF_572(CK,CRC_OUT_7_28,WX3906);
dff DFF_573(CK,CRC_OUT_7_29,WX3908);
dff DFF_574(CK,CRC_OUT_7_30,WX3910);
dff DFF_575(CK,CRC_OUT_7_31,WX3912);
dff DFF_576(CK,WX4364,WX4363);
dff DFF_577(CK,WX4366,WX4365);
dff DFF_578(CK,WX4368,WX4367);
dff DFF_579(CK,WX4370,WX4369);
dff DFF_580(CK,WX4372,WX4371);
dff DFF_581(CK,WX4374,WX4373);
dff DFF_582(CK,WX4376,WX4375);
dff DFF_583(CK,WX4378,WX4377);
dff DFF_584(CK,WX4380,WX4379);
dff DFF_585(CK,WX4382,WX4381);
dff DFF_586(CK,WX4384,WX4383);
dff DFF_587(CK,WX4386,WX4385);
dff DFF_588(CK,WX4388,WX4387);
dff DFF_589(CK,WX4390,WX4389);
dff DFF_590(CK,WX4392,WX4391);
dff DFF_591(CK,WX4394,WX4393);
dff DFF_592(CK,WX4396,WX4395);
dff DFF_593(CK,WX4398,WX4397);
dff DFF_594(CK,WX4400,WX4399);
dff DFF_595(CK,WX4402,WX4401);
dff DFF_596(CK,WX4404,WX4403);
dff DFF_597(CK,WX4406,WX4405);
dff DFF_598(CK,WX4408,WX4407);
dff DFF_599(CK,WX4410,WX4409);
dff DFF_600(CK,WX4412,WX4411);
dff DFF_601(CK,WX4414,WX4413);
dff DFF_602(CK,WX4416,WX4415);
dff DFF_603(CK,WX4418,WX4417);
dff DFF_604(CK,WX4420,WX4419);
dff DFF_605(CK,WX4422,WX4421);
dff DFF_606(CK,WX4424,WX4423);
dff DFF_607(CK,WX4426,WX4425);
dff DFF_608(CK,WX4524,WX4523);
dff DFF_609(CK,WX4526,WX4525);
dff DFF_610(CK,WX4528,WX4527);
dff DFF_611(CK,WX4530,WX4529);
dff DFF_612(CK,WX4532,WX4531);
dff DFF_613(CK,WX4534,WX4533);
dff DFF_614(CK,WX4536,WX4535);
dff DFF_615(CK,WX4538,WX4537);
dff DFF_616(CK,WX4540,WX4539);
dff DFF_617(CK,WX4542,WX4541);
dff DFF_618(CK,WX4544,WX4543);
dff DFF_619(CK,WX4546,WX4545);
dff DFF_620(CK,WX4548,WX4547);
dff DFF_621(CK,WX4550,WX4549);
dff DFF_622(CK,WX4552,WX4551);
dff DFF_623(CK,WX4554,WX4553);
dff DFF_624(CK,WX4556,WX4555);
dff DFF_625(CK,WX4558,WX4557);
dff DFF_626(CK,WX4560,WX4559);
dff DFF_627(CK,WX4562,WX4561);
dff DFF_628(CK,WX4564,WX4563);
dff DFF_629(CK,WX4566,WX4565);
dff DFF_630(CK,WX4568,WX4567);
dff DFF_631(CK,WX4570,WX4569);
dff DFF_632(CK,WX4572,WX4571);
dff DFF_633(CK,WX4574,WX4573);
dff DFF_634(CK,WX4576,WX4575);
dff DFF_635(CK,WX4578,WX4577);
dff DFF_636(CK,WX4580,WX4579);
dff DFF_637(CK,WX4582,WX4581);
dff DFF_638(CK,WX4584,WX4583);
dff DFF_639(CK,WX4586,WX4585);
dff DFF_640(CK,WX4588,WX4587);
dff DFF_641(CK,WX4590,WX4589);
dff DFF_642(CK,WX4592,WX4591);
dff DFF_643(CK,WX4594,WX4593);
dff DFF_644(CK,WX4596,WX4595);
dff DFF_645(CK,WX4598,WX4597);
dff DFF_646(CK,WX4600,WX4599);
dff DFF_647(CK,WX4602,WX4601);
dff DFF_648(CK,WX4604,WX4603);
dff DFF_649(CK,WX4606,WX4605);
dff DFF_650(CK,WX4608,WX4607);
dff DFF_651(CK,WX4610,WX4609);
dff DFF_652(CK,WX4612,WX4611);
dff DFF_653(CK,WX4614,WX4613);
dff DFF_654(CK,WX4616,WX4615);
dff DFF_655(CK,WX4618,WX4617);
dff DFF_656(CK,WX4620,WX4619);
dff DFF_657(CK,WX4622,WX4621);
dff DFF_658(CK,WX4624,WX4623);
dff DFF_659(CK,WX4626,WX4625);
dff DFF_660(CK,WX4628,WX4627);
dff DFF_661(CK,WX4630,WX4629);
dff DFF_662(CK,WX4632,WX4631);
dff DFF_663(CK,WX4634,WX4633);
dff DFF_664(CK,WX4636,WX4635);
dff DFF_665(CK,WX4638,WX4637);
dff DFF_666(CK,WX4640,WX4639);
dff DFF_667(CK,WX4642,WX4641);
dff DFF_668(CK,WX4644,WX4643);
dff DFF_669(CK,WX4646,WX4645);
dff DFF_670(CK,WX4648,WX4647);
dff DFF_671(CK,WX4650,WX4649);
dff DFF_672(CK,WX4652,WX4651);
dff DFF_673(CK,WX4654,WX4653);
dff DFF_674(CK,WX4656,WX4655);
dff DFF_675(CK,WX4658,WX4657);
dff DFF_676(CK,WX4660,WX4659);
dff DFF_677(CK,WX4662,WX4661);
dff DFF_678(CK,WX4664,WX4663);
dff DFF_679(CK,WX4666,WX4665);
dff DFF_680(CK,WX4668,WX4667);
dff DFF_681(CK,WX4670,WX4669);
dff DFF_682(CK,WX4672,WX4671);
dff DFF_683(CK,WX4674,WX4673);
dff DFF_684(CK,WX4676,WX4675);
dff DFF_685(CK,WX4678,WX4677);
dff DFF_686(CK,WX4680,WX4679);
dff DFF_687(CK,WX4682,WX4681);
dff DFF_688(CK,WX4684,WX4683);
dff DFF_689(CK,WX4686,WX4685);
dff DFF_690(CK,WX4688,WX4687);
dff DFF_691(CK,WX4690,WX4689);
dff DFF_692(CK,WX4692,WX4691);
dff DFF_693(CK,WX4694,WX4693);
dff DFF_694(CK,WX4696,WX4695);
dff DFF_695(CK,WX4698,WX4697);
dff DFF_696(CK,WX4700,WX4699);
dff DFF_697(CK,WX4702,WX4701);
dff DFF_698(CK,WX4704,WX4703);
dff DFF_699(CK,WX4706,WX4705);
dff DFF_700(CK,WX4708,WX4707);
dff DFF_701(CK,WX4710,WX4709);
dff DFF_702(CK,WX4712,WX4711);
dff DFF_703(CK,WX4714,WX4713);
dff DFF_704(CK,WX4716,WX4715);
dff DFF_705(CK,WX4718,WX4717);
dff DFF_706(CK,WX4720,WX4719);
dff DFF_707(CK,WX4722,WX4721);
dff DFF_708(CK,WX4724,WX4723);
dff DFF_709(CK,WX4726,WX4725);
dff DFF_710(CK,WX4728,WX4727);
dff DFF_711(CK,WX4730,WX4729);
dff DFF_712(CK,WX4732,WX4731);
dff DFF_713(CK,WX4734,WX4733);
dff DFF_714(CK,WX4736,WX4735);
dff DFF_715(CK,WX4738,WX4737);
dff DFF_716(CK,WX4740,WX4739);
dff DFF_717(CK,WX4742,WX4741);
dff DFF_718(CK,WX4744,WX4743);
dff DFF_719(CK,WX4746,WX4745);
dff DFF_720(CK,WX4748,WX4747);
dff DFF_721(CK,WX4750,WX4749);
dff DFF_722(CK,WX4752,WX4751);
dff DFF_723(CK,WX4754,WX4753);
dff DFF_724(CK,WX4756,WX4755);
dff DFF_725(CK,WX4758,WX4757);
dff DFF_726(CK,WX4760,WX4759);
dff DFF_727(CK,WX4762,WX4761);
dff DFF_728(CK,WX4764,WX4763);
dff DFF_729(CK,WX4766,WX4765);
dff DFF_730(CK,WX4768,WX4767);
dff DFF_731(CK,WX4770,WX4769);
dff DFF_732(CK,WX4772,WX4771);
dff DFF_733(CK,WX4774,WX4773);
dff DFF_734(CK,WX4776,WX4775);
dff DFF_735(CK,WX4778,WX4777);
dff DFF_736(CK,CRC_OUT_6_0,WX5143);
dff DFF_737(CK,CRC_OUT_6_1,WX5145);
dff DFF_738(CK,CRC_OUT_6_2,WX5147);
dff DFF_739(CK,CRC_OUT_6_3,WX5149);
dff DFF_740(CK,CRC_OUT_6_4,WX5151);
dff DFF_741(CK,CRC_OUT_6_5,WX5153);
dff DFF_742(CK,CRC_OUT_6_6,WX5155);
dff DFF_743(CK,CRC_OUT_6_7,WX5157);
dff DFF_744(CK,CRC_OUT_6_8,WX5159);
dff DFF_745(CK,CRC_OUT_6_9,WX5161);
dff DFF_746(CK,CRC_OUT_6_10,WX5163);
dff DFF_747(CK,CRC_OUT_6_11,WX5165);
dff DFF_748(CK,CRC_OUT_6_12,WX5167);
dff DFF_749(CK,CRC_OUT_6_13,WX5169);
dff DFF_750(CK,CRC_OUT_6_14,WX5171);
dff DFF_751(CK,CRC_OUT_6_15,WX5173);
dff DFF_752(CK,CRC_OUT_6_16,WX5175);
dff DFF_753(CK,CRC_OUT_6_17,WX5177);
dff DFF_754(CK,CRC_OUT_6_18,WX5179);
dff DFF_755(CK,CRC_OUT_6_19,WX5181);
dff DFF_756(CK,CRC_OUT_6_20,WX5183);
dff DFF_757(CK,CRC_OUT_6_21,WX5185);
dff DFF_758(CK,CRC_OUT_6_22,WX5187);
dff DFF_759(CK,CRC_OUT_6_23,WX5189);
dff DFF_760(CK,CRC_OUT_6_24,WX5191);
dff DFF_761(CK,CRC_OUT_6_25,WX5193);
dff DFF_762(CK,CRC_OUT_6_26,WX5195);
dff DFF_763(CK,CRC_OUT_6_27,WX5197);
dff DFF_764(CK,CRC_OUT_6_28,WX5199);
dff DFF_765(CK,CRC_OUT_6_29,WX5201);
dff DFF_766(CK,CRC_OUT_6_30,WX5203);
dff DFF_767(CK,CRC_OUT_6_31,WX5205);
dff DFF_768(CK,WX5657,WX5656);
dff DFF_769(CK,WX5659,WX5658);
dff DFF_770(CK,WX5661,WX5660);
dff DFF_771(CK,WX5663,WX5662);
dff DFF_772(CK,WX5665,WX5664);
dff DFF_773(CK,WX5667,WX5666);
dff DFF_774(CK,WX5669,WX5668);
dff DFF_775(CK,WX5671,WX5670);
dff DFF_776(CK,WX5673,WX5672);
dff DFF_777(CK,WX5675,WX5674);
dff DFF_778(CK,WX5677,WX5676);
dff DFF_779(CK,WX5679,WX5678);
dff DFF_780(CK,WX5681,WX5680);
dff DFF_781(CK,WX5683,WX5682);
dff DFF_782(CK,WX5685,WX5684);
dff DFF_783(CK,WX5687,WX5686);
dff DFF_784(CK,WX5689,WX5688);
dff DFF_785(CK,WX5691,WX5690);
dff DFF_786(CK,WX5693,WX5692);
dff DFF_787(CK,WX5695,WX5694);
dff DFF_788(CK,WX5697,WX5696);
dff DFF_789(CK,WX5699,WX5698);
dff DFF_790(CK,WX5701,WX5700);
dff DFF_791(CK,WX5703,WX5702);
dff DFF_792(CK,WX5705,WX5704);
dff DFF_793(CK,WX5707,WX5706);
dff DFF_794(CK,WX5709,WX5708);
dff DFF_795(CK,WX5711,WX5710);
dff DFF_796(CK,WX5713,WX5712);
dff DFF_797(CK,WX5715,WX5714);
dff DFF_798(CK,WX5717,WX5716);
dff DFF_799(CK,WX5719,WX5718);
dff DFF_800(CK,WX5817,WX5816);
dff DFF_801(CK,WX5819,WX5818);
dff DFF_802(CK,WX5821,WX5820);
dff DFF_803(CK,WX5823,WX5822);
dff DFF_804(CK,WX5825,WX5824);
dff DFF_805(CK,WX5827,WX5826);
dff DFF_806(CK,WX5829,WX5828);
dff DFF_807(CK,WX5831,WX5830);
dff DFF_808(CK,WX5833,WX5832);
dff DFF_809(CK,WX5835,WX5834);
dff DFF_810(CK,WX5837,WX5836);
dff DFF_811(CK,WX5839,WX5838);
dff DFF_812(CK,WX5841,WX5840);
dff DFF_813(CK,WX5843,WX5842);
dff DFF_814(CK,WX5845,WX5844);
dff DFF_815(CK,WX5847,WX5846);
dff DFF_816(CK,WX5849,WX5848);
dff DFF_817(CK,WX5851,WX5850);
dff DFF_818(CK,WX5853,WX5852);
dff DFF_819(CK,WX5855,WX5854);
dff DFF_820(CK,WX5857,WX5856);
dff DFF_821(CK,WX5859,WX5858);
dff DFF_822(CK,WX5861,WX5860);
dff DFF_823(CK,WX5863,WX5862);
dff DFF_824(CK,WX5865,WX5864);
dff DFF_825(CK,WX5867,WX5866);
dff DFF_826(CK,WX5869,WX5868);
dff DFF_827(CK,WX5871,WX5870);
dff DFF_828(CK,WX5873,WX5872);
dff DFF_829(CK,WX5875,WX5874);
dff DFF_830(CK,WX5877,WX5876);
dff DFF_831(CK,WX5879,WX5878);
dff DFF_832(CK,WX5881,WX5880);
dff DFF_833(CK,WX5883,WX5882);
dff DFF_834(CK,WX5885,WX5884);
dff DFF_835(CK,WX5887,WX5886);
dff DFF_836(CK,WX5889,WX5888);
dff DFF_837(CK,WX5891,WX5890);
dff DFF_838(CK,WX5893,WX5892);
dff DFF_839(CK,WX5895,WX5894);
dff DFF_840(CK,WX5897,WX5896);
dff DFF_841(CK,WX5899,WX5898);
dff DFF_842(CK,WX5901,WX5900);
dff DFF_843(CK,WX5903,WX5902);
dff DFF_844(CK,WX5905,WX5904);
dff DFF_845(CK,WX5907,WX5906);
dff DFF_846(CK,WX5909,WX5908);
dff DFF_847(CK,WX5911,WX5910);
dff DFF_848(CK,WX5913,WX5912);
dff DFF_849(CK,WX5915,WX5914);
dff DFF_850(CK,WX5917,WX5916);
dff DFF_851(CK,WX5919,WX5918);
dff DFF_852(CK,WX5921,WX5920);
dff DFF_853(CK,WX5923,WX5922);
dff DFF_854(CK,WX5925,WX5924);
dff DFF_855(CK,WX5927,WX5926);
dff DFF_856(CK,WX5929,WX5928);
dff DFF_857(CK,WX5931,WX5930);
dff DFF_858(CK,WX5933,WX5932);
dff DFF_859(CK,WX5935,WX5934);
dff DFF_860(CK,WX5937,WX5936);
dff DFF_861(CK,WX5939,WX5938);
dff DFF_862(CK,WX5941,WX5940);
dff DFF_863(CK,WX5943,WX5942);
dff DFF_864(CK,WX5945,WX5944);
dff DFF_865(CK,WX5947,WX5946);
dff DFF_866(CK,WX5949,WX5948);
dff DFF_867(CK,WX5951,WX5950);
dff DFF_868(CK,WX5953,WX5952);
dff DFF_869(CK,WX5955,WX5954);
dff DFF_870(CK,WX5957,WX5956);
dff DFF_871(CK,WX5959,WX5958);
dff DFF_872(CK,WX5961,WX5960);
dff DFF_873(CK,WX5963,WX5962);
dff DFF_874(CK,WX5965,WX5964);
dff DFF_875(CK,WX5967,WX5966);
dff DFF_876(CK,WX5969,WX5968);
dff DFF_877(CK,WX5971,WX5970);
dff DFF_878(CK,WX5973,WX5972);
dff DFF_879(CK,WX5975,WX5974);
dff DFF_880(CK,WX5977,WX5976);
dff DFF_881(CK,WX5979,WX5978);
dff DFF_882(CK,WX5981,WX5980);
dff DFF_883(CK,WX5983,WX5982);
dff DFF_884(CK,WX5985,WX5984);
dff DFF_885(CK,WX5987,WX5986);
dff DFF_886(CK,WX5989,WX5988);
dff DFF_887(CK,WX5991,WX5990);
dff DFF_888(CK,WX5993,WX5992);
dff DFF_889(CK,WX5995,WX5994);
dff DFF_890(CK,WX5997,WX5996);
dff DFF_891(CK,WX5999,WX5998);
dff DFF_892(CK,WX6001,WX6000);
dff DFF_893(CK,WX6003,WX6002);
dff DFF_894(CK,WX6005,WX6004);
dff DFF_895(CK,WX6007,WX6006);
dff DFF_896(CK,WX6009,WX6008);
dff DFF_897(CK,WX6011,WX6010);
dff DFF_898(CK,WX6013,WX6012);
dff DFF_899(CK,WX6015,WX6014);
dff DFF_900(CK,WX6017,WX6016);
dff DFF_901(CK,WX6019,WX6018);
dff DFF_902(CK,WX6021,WX6020);
dff DFF_903(CK,WX6023,WX6022);
dff DFF_904(CK,WX6025,WX6024);
dff DFF_905(CK,WX6027,WX6026);
dff DFF_906(CK,WX6029,WX6028);
dff DFF_907(CK,WX6031,WX6030);
dff DFF_908(CK,WX6033,WX6032);
dff DFF_909(CK,WX6035,WX6034);
dff DFF_910(CK,WX6037,WX6036);
dff DFF_911(CK,WX6039,WX6038);
dff DFF_912(CK,WX6041,WX6040);
dff DFF_913(CK,WX6043,WX6042);
dff DFF_914(CK,WX6045,WX6044);
dff DFF_915(CK,WX6047,WX6046);
dff DFF_916(CK,WX6049,WX6048);
dff DFF_917(CK,WX6051,WX6050);
dff DFF_918(CK,WX6053,WX6052);
dff DFF_919(CK,WX6055,WX6054);
dff DFF_920(CK,WX6057,WX6056);
dff DFF_921(CK,WX6059,WX6058);
dff DFF_922(CK,WX6061,WX6060);
dff DFF_923(CK,WX6063,WX6062);
dff DFF_924(CK,WX6065,WX6064);
dff DFF_925(CK,WX6067,WX6066);
dff DFF_926(CK,WX6069,WX6068);
dff DFF_927(CK,WX6071,WX6070);
dff DFF_928(CK,CRC_OUT_5_0,WX6436);
dff DFF_929(CK,CRC_OUT_5_1,WX6438);
dff DFF_930(CK,CRC_OUT_5_2,WX6440);
dff DFF_931(CK,CRC_OUT_5_3,WX6442);
dff DFF_932(CK,CRC_OUT_5_4,WX6444);
dff DFF_933(CK,CRC_OUT_5_5,WX6446);
dff DFF_934(CK,CRC_OUT_5_6,WX6448);
dff DFF_935(CK,CRC_OUT_5_7,WX6450);
dff DFF_936(CK,CRC_OUT_5_8,WX6452);
dff DFF_937(CK,CRC_OUT_5_9,WX6454);
dff DFF_938(CK,CRC_OUT_5_10,WX6456);
dff DFF_939(CK,CRC_OUT_5_11,WX6458);
dff DFF_940(CK,CRC_OUT_5_12,WX6460);
dff DFF_941(CK,CRC_OUT_5_13,WX6462);
dff DFF_942(CK,CRC_OUT_5_14,WX6464);
dff DFF_943(CK,CRC_OUT_5_15,WX6466);
dff DFF_944(CK,CRC_OUT_5_16,WX6468);
dff DFF_945(CK,CRC_OUT_5_17,WX6470);
dff DFF_946(CK,CRC_OUT_5_18,WX6472);
dff DFF_947(CK,CRC_OUT_5_19,WX6474);
dff DFF_948(CK,CRC_OUT_5_20,WX6476);
dff DFF_949(CK,CRC_OUT_5_21,WX6478);
dff DFF_950(CK,CRC_OUT_5_22,WX6480);
dff DFF_951(CK,CRC_OUT_5_23,WX6482);
dff DFF_952(CK,CRC_OUT_5_24,WX6484);
dff DFF_953(CK,CRC_OUT_5_25,WX6486);
dff DFF_954(CK,CRC_OUT_5_26,WX6488);
dff DFF_955(CK,CRC_OUT_5_27,WX6490);
dff DFF_956(CK,CRC_OUT_5_28,WX6492);
dff DFF_957(CK,CRC_OUT_5_29,WX6494);
dff DFF_958(CK,CRC_OUT_5_30,WX6496);
dff DFF_959(CK,CRC_OUT_5_31,WX6498);
dff DFF_960(CK,WX6950,WX6949);
dff DFF_961(CK,WX6952,WX6951);
dff DFF_962(CK,WX6954,WX6953);
dff DFF_963(CK,WX6956,WX6955);
dff DFF_964(CK,WX6958,WX6957);
dff DFF_965(CK,WX6960,WX6959);
dff DFF_966(CK,WX6962,WX6961);
dff DFF_967(CK,WX6964,WX6963);
dff DFF_968(CK,WX6966,WX6965);
dff DFF_969(CK,WX6968,WX6967);
dff DFF_970(CK,WX6970,WX6969);
dff DFF_971(CK,WX6972,WX6971);
dff DFF_972(CK,WX6974,WX6973);
dff DFF_973(CK,WX6976,WX6975);
dff DFF_974(CK,WX6978,WX6977);
dff DFF_975(CK,WX6980,WX6979);
dff DFF_976(CK,WX6982,WX6981);
dff DFF_977(CK,WX6984,WX6983);
dff DFF_978(CK,WX6986,WX6985);
dff DFF_979(CK,WX6988,WX6987);
dff DFF_980(CK,WX6990,WX6989);
dff DFF_981(CK,WX6992,WX6991);
dff DFF_982(CK,WX6994,WX6993);
dff DFF_983(CK,WX6996,WX6995);
dff DFF_984(CK,WX6998,WX6997);
dff DFF_985(CK,WX7000,WX6999);
dff DFF_986(CK,WX7002,WX7001);
dff DFF_987(CK,WX7004,WX7003);
dff DFF_988(CK,WX7006,WX7005);
dff DFF_989(CK,WX7008,WX7007);
dff DFF_990(CK,WX7010,WX7009);
dff DFF_991(CK,WX7012,WX7011);
dff DFF_992(CK,WX7110,WX7109);
dff DFF_993(CK,WX7112,WX7111);
dff DFF_994(CK,WX7114,WX7113);
dff DFF_995(CK,WX7116,WX7115);
dff DFF_996(CK,WX7118,WX7117);
dff DFF_997(CK,WX7120,WX7119);
dff DFF_998(CK,WX7122,WX7121);
dff DFF_999(CK,WX7124,WX7123);
dff DFF_1000(CK,WX7126,WX7125);
dff DFF_1001(CK,WX7128,WX7127);
dff DFF_1002(CK,WX7130,WX7129);
dff DFF_1003(CK,WX7132,WX7131);
dff DFF_1004(CK,WX7134,WX7133);
dff DFF_1005(CK,WX7136,WX7135);
dff DFF_1006(CK,WX7138,WX7137);
dff DFF_1007(CK,WX7140,WX7139);
dff DFF_1008(CK,WX7142,WX7141);
dff DFF_1009(CK,WX7144,WX7143);
dff DFF_1010(CK,WX7146,WX7145);
dff DFF_1011(CK,WX7148,WX7147);
dff DFF_1012(CK,WX7150,WX7149);
dff DFF_1013(CK,WX7152,WX7151);
dff DFF_1014(CK,WX7154,WX7153);
dff DFF_1015(CK,WX7156,WX7155);
dff DFF_1016(CK,WX7158,WX7157);
dff DFF_1017(CK,WX7160,WX7159);
dff DFF_1018(CK,WX7162,WX7161);
dff DFF_1019(CK,WX7164,WX7163);
dff DFF_1020(CK,WX7166,WX7165);
dff DFF_1021(CK,WX7168,WX7167);
dff DFF_1022(CK,WX7170,WX7169);
dff DFF_1023(CK,WX7172,WX7171);
dff DFF_1024(CK,WX7174,WX7173);
dff DFF_1025(CK,WX7176,WX7175);
dff DFF_1026(CK,WX7178,WX7177);
dff DFF_1027(CK,WX7180,WX7179);
dff DFF_1028(CK,WX7182,WX7181);
dff DFF_1029(CK,WX7184,WX7183);
dff DFF_1030(CK,WX7186,WX7185);
dff DFF_1031(CK,WX7188,WX7187);
dff DFF_1032(CK,WX7190,WX7189);
dff DFF_1033(CK,WX7192,WX7191);
dff DFF_1034(CK,WX7194,WX7193);
dff DFF_1035(CK,WX7196,WX7195);
dff DFF_1036(CK,WX7198,WX7197);
dff DFF_1037(CK,WX7200,WX7199);
dff DFF_1038(CK,WX7202,WX7201);
dff DFF_1039(CK,WX7204,WX7203);
dff DFF_1040(CK,WX7206,WX7205);
dff DFF_1041(CK,WX7208,WX7207);
dff DFF_1042(CK,WX7210,WX7209);
dff DFF_1043(CK,WX7212,WX7211);
dff DFF_1044(CK,WX7214,WX7213);
dff DFF_1045(CK,WX7216,WX7215);
dff DFF_1046(CK,WX7218,WX7217);
dff DFF_1047(CK,WX7220,WX7219);
dff DFF_1048(CK,WX7222,WX7221);
dff DFF_1049(CK,WX7224,WX7223);
dff DFF_1050(CK,WX7226,WX7225);
dff DFF_1051(CK,WX7228,WX7227);
dff DFF_1052(CK,WX7230,WX7229);
dff DFF_1053(CK,WX7232,WX7231);
dff DFF_1054(CK,WX7234,WX7233);
dff DFF_1055(CK,WX7236,WX7235);
dff DFF_1056(CK,WX7238,WX7237);
dff DFF_1057(CK,WX7240,WX7239);
dff DFF_1058(CK,WX7242,WX7241);
dff DFF_1059(CK,WX7244,WX7243);
dff DFF_1060(CK,WX7246,WX7245);
dff DFF_1061(CK,WX7248,WX7247);
dff DFF_1062(CK,WX7250,WX7249);
dff DFF_1063(CK,WX7252,WX7251);
dff DFF_1064(CK,WX7254,WX7253);
dff DFF_1065(CK,WX7256,WX7255);
dff DFF_1066(CK,WX7258,WX7257);
dff DFF_1067(CK,WX7260,WX7259);
dff DFF_1068(CK,WX7262,WX7261);
dff DFF_1069(CK,WX7264,WX7263);
dff DFF_1070(CK,WX7266,WX7265);
dff DFF_1071(CK,WX7268,WX7267);
dff DFF_1072(CK,WX7270,WX7269);
dff DFF_1073(CK,WX7272,WX7271);
dff DFF_1074(CK,WX7274,WX7273);
dff DFF_1075(CK,WX7276,WX7275);
dff DFF_1076(CK,WX7278,WX7277);
dff DFF_1077(CK,WX7280,WX7279);
dff DFF_1078(CK,WX7282,WX7281);
dff DFF_1079(CK,WX7284,WX7283);
dff DFF_1080(CK,WX7286,WX7285);
dff DFF_1081(CK,WX7288,WX7287);
dff DFF_1082(CK,WX7290,WX7289);
dff DFF_1083(CK,WX7292,WX7291);
dff DFF_1084(CK,WX7294,WX7293);
dff DFF_1085(CK,WX7296,WX7295);
dff DFF_1086(CK,WX7298,WX7297);
dff DFF_1087(CK,WX7300,WX7299);
dff DFF_1088(CK,WX7302,WX7301);
dff DFF_1089(CK,WX7304,WX7303);
dff DFF_1090(CK,WX7306,WX7305);
dff DFF_1091(CK,WX7308,WX7307);
dff DFF_1092(CK,WX7310,WX7309);
dff DFF_1093(CK,WX7312,WX7311);
dff DFF_1094(CK,WX7314,WX7313);
dff DFF_1095(CK,WX7316,WX7315);
dff DFF_1096(CK,WX7318,WX7317);
dff DFF_1097(CK,WX7320,WX7319);
dff DFF_1098(CK,WX7322,WX7321);
dff DFF_1099(CK,WX7324,WX7323);
dff DFF_1100(CK,WX7326,WX7325);
dff DFF_1101(CK,WX7328,WX7327);
dff DFF_1102(CK,WX7330,WX7329);
dff DFF_1103(CK,WX7332,WX7331);
dff DFF_1104(CK,WX7334,WX7333);
dff DFF_1105(CK,WX7336,WX7335);
dff DFF_1106(CK,WX7338,WX7337);
dff DFF_1107(CK,WX7340,WX7339);
dff DFF_1108(CK,WX7342,WX7341);
dff DFF_1109(CK,WX7344,WX7343);
dff DFF_1110(CK,WX7346,WX7345);
dff DFF_1111(CK,WX7348,WX7347);
dff DFF_1112(CK,WX7350,WX7349);
dff DFF_1113(CK,WX7352,WX7351);
dff DFF_1114(CK,WX7354,WX7353);
dff DFF_1115(CK,WX7356,WX7355);
dff DFF_1116(CK,WX7358,WX7357);
dff DFF_1117(CK,WX7360,WX7359);
dff DFF_1118(CK,WX7362,WX7361);
dff DFF_1119(CK,WX7364,WX7363);
dff DFF_1120(CK,CRC_OUT_4_0,WX7729);
dff DFF_1121(CK,CRC_OUT_4_1,WX7731);
dff DFF_1122(CK,CRC_OUT_4_2,WX7733);
dff DFF_1123(CK,CRC_OUT_4_3,WX7735);
dff DFF_1124(CK,CRC_OUT_4_4,WX7737);
dff DFF_1125(CK,CRC_OUT_4_5,WX7739);
dff DFF_1126(CK,CRC_OUT_4_6,WX7741);
dff DFF_1127(CK,CRC_OUT_4_7,WX7743);
dff DFF_1128(CK,CRC_OUT_4_8,WX7745);
dff DFF_1129(CK,CRC_OUT_4_9,WX7747);
dff DFF_1130(CK,CRC_OUT_4_10,WX7749);
dff DFF_1131(CK,CRC_OUT_4_11,WX7751);
dff DFF_1132(CK,CRC_OUT_4_12,WX7753);
dff DFF_1133(CK,CRC_OUT_4_13,WX7755);
dff DFF_1134(CK,CRC_OUT_4_14,WX7757);
dff DFF_1135(CK,CRC_OUT_4_15,WX7759);
dff DFF_1136(CK,CRC_OUT_4_16,WX7761);
dff DFF_1137(CK,CRC_OUT_4_17,WX7763);
dff DFF_1138(CK,CRC_OUT_4_18,WX7765);
dff DFF_1139(CK,CRC_OUT_4_19,WX7767);
dff DFF_1140(CK,CRC_OUT_4_20,WX7769);
dff DFF_1141(CK,CRC_OUT_4_21,WX7771);
dff DFF_1142(CK,CRC_OUT_4_22,WX7773);
dff DFF_1143(CK,CRC_OUT_4_23,WX7775);
dff DFF_1144(CK,CRC_OUT_4_24,WX7777);
dff DFF_1145(CK,CRC_OUT_4_25,WX7779);
dff DFF_1146(CK,CRC_OUT_4_26,WX7781);
dff DFF_1147(CK,CRC_OUT_4_27,WX7783);
dff DFF_1148(CK,CRC_OUT_4_28,WX7785);
dff DFF_1149(CK,CRC_OUT_4_29,WX7787);
dff DFF_1150(CK,CRC_OUT_4_30,WX7789);
dff DFF_1151(CK,CRC_OUT_4_31,WX7791);
dff DFF_1152(CK,WX8243,WX8242);
dff DFF_1153(CK,WX8245,WX8244);
dff DFF_1154(CK,WX8247,WX8246);
dff DFF_1155(CK,WX8249,WX8248);
dff DFF_1156(CK,WX8251,WX8250);
dff DFF_1157(CK,WX8253,WX8252);
dff DFF_1158(CK,WX8255,WX8254);
dff DFF_1159(CK,WX8257,WX8256);
dff DFF_1160(CK,WX8259,WX8258);
dff DFF_1161(CK,WX8261,WX8260);
dff DFF_1162(CK,WX8263,WX8262);
dff DFF_1163(CK,WX8265,WX8264);
dff DFF_1164(CK,WX8267,WX8266);
dff DFF_1165(CK,WX8269,WX8268);
dff DFF_1166(CK,WX8271,WX8270);
dff DFF_1167(CK,WX8273,WX8272);
dff DFF_1168(CK,WX8275,WX8274);
dff DFF_1169(CK,WX8277,WX8276);
dff DFF_1170(CK,WX8279,WX8278);
dff DFF_1171(CK,WX8281,WX8280);
dff DFF_1172(CK,WX8283,WX8282);
dff DFF_1173(CK,WX8285,WX8284);
dff DFF_1174(CK,WX8287,WX8286);
dff DFF_1175(CK,WX8289,WX8288);
dff DFF_1176(CK,WX8291,WX8290);
dff DFF_1177(CK,WX8293,WX8292);
dff DFF_1178(CK,WX8295,WX8294);
dff DFF_1179(CK,WX8297,WX8296);
dff DFF_1180(CK,WX8299,WX8298);
dff DFF_1181(CK,WX8301,WX8300);
dff DFF_1182(CK,WX8303,WX8302);
dff DFF_1183(CK,WX8305,WX8304);
dff DFF_1184(CK,WX8403,WX8402);
dff DFF_1185(CK,WX8405,WX8404);
dff DFF_1186(CK,WX8407,WX8406);
dff DFF_1187(CK,WX8409,WX8408);
dff DFF_1188(CK,WX8411,WX8410);
dff DFF_1189(CK,WX8413,WX8412);
dff DFF_1190(CK,WX8415,WX8414);
dff DFF_1191(CK,WX8417,WX8416);
dff DFF_1192(CK,WX8419,WX8418);
dff DFF_1193(CK,WX8421,WX8420);
dff DFF_1194(CK,WX8423,WX8422);
dff DFF_1195(CK,WX8425,WX8424);
dff DFF_1196(CK,WX8427,WX8426);
dff DFF_1197(CK,WX8429,WX8428);
dff DFF_1198(CK,WX8431,WX8430);
dff DFF_1199(CK,WX8433,WX8432);
dff DFF_1200(CK,WX8435,WX8434);
dff DFF_1201(CK,WX8437,WX8436);
dff DFF_1202(CK,WX8439,WX8438);
dff DFF_1203(CK,WX8441,WX8440);
dff DFF_1204(CK,WX8443,WX8442);
dff DFF_1205(CK,WX8445,WX8444);
dff DFF_1206(CK,WX8447,WX8446);
dff DFF_1207(CK,WX8449,WX8448);
dff DFF_1208(CK,WX8451,WX8450);
dff DFF_1209(CK,WX8453,WX8452);
dff DFF_1210(CK,WX8455,WX8454);
dff DFF_1211(CK,WX8457,WX8456);
dff DFF_1212(CK,WX8459,WX8458);
dff DFF_1213(CK,WX8461,WX8460);
dff DFF_1214(CK,WX8463,WX8462);
dff DFF_1215(CK,WX8465,WX8464);
dff DFF_1216(CK,WX8467,WX8466);
dff DFF_1217(CK,WX8469,WX8468);
dff DFF_1218(CK,WX8471,WX8470);
dff DFF_1219(CK,WX8473,WX8472);
dff DFF_1220(CK,WX8475,WX8474);
dff DFF_1221(CK,WX8477,WX8476);
dff DFF_1222(CK,WX8479,WX8478);
dff DFF_1223(CK,WX8481,WX8480);
dff DFF_1224(CK,WX8483,WX8482);
dff DFF_1225(CK,WX8485,WX8484);
dff DFF_1226(CK,WX8487,WX8486);
dff DFF_1227(CK,WX8489,WX8488);
dff DFF_1228(CK,WX8491,WX8490);
dff DFF_1229(CK,WX8493,WX8492);
dff DFF_1230(CK,WX8495,WX8494);
dff DFF_1231(CK,WX8497,WX8496);
dff DFF_1232(CK,WX8499,WX8498);
dff DFF_1233(CK,WX8501,WX8500);
dff DFF_1234(CK,WX8503,WX8502);
dff DFF_1235(CK,WX8505,WX8504);
dff DFF_1236(CK,WX8507,WX8506);
dff DFF_1237(CK,WX8509,WX8508);
dff DFF_1238(CK,WX8511,WX8510);
dff DFF_1239(CK,WX8513,WX8512);
dff DFF_1240(CK,WX8515,WX8514);
dff DFF_1241(CK,WX8517,WX8516);
dff DFF_1242(CK,WX8519,WX8518);
dff DFF_1243(CK,WX8521,WX8520);
dff DFF_1244(CK,WX8523,WX8522);
dff DFF_1245(CK,WX8525,WX8524);
dff DFF_1246(CK,WX8527,WX8526);
dff DFF_1247(CK,WX8529,WX8528);
dff DFF_1248(CK,WX8531,WX8530);
dff DFF_1249(CK,WX8533,WX8532);
dff DFF_1250(CK,WX8535,WX8534);
dff DFF_1251(CK,WX8537,WX8536);
dff DFF_1252(CK,WX8539,WX8538);
dff DFF_1253(CK,WX8541,WX8540);
dff DFF_1254(CK,WX8543,WX8542);
dff DFF_1255(CK,WX8545,WX8544);
dff DFF_1256(CK,WX8547,WX8546);
dff DFF_1257(CK,WX8549,WX8548);
dff DFF_1258(CK,WX8551,WX8550);
dff DFF_1259(CK,WX8553,WX8552);
dff DFF_1260(CK,WX8555,WX8554);
dff DFF_1261(CK,WX8557,WX8556);
dff DFF_1262(CK,WX8559,WX8558);
dff DFF_1263(CK,WX8561,WX8560);
dff DFF_1264(CK,WX8563,WX8562);
dff DFF_1265(CK,WX8565,WX8564);
dff DFF_1266(CK,WX8567,WX8566);
dff DFF_1267(CK,WX8569,WX8568);
dff DFF_1268(CK,WX8571,WX8570);
dff DFF_1269(CK,WX8573,WX8572);
dff DFF_1270(CK,WX8575,WX8574);
dff DFF_1271(CK,WX8577,WX8576);
dff DFF_1272(CK,WX8579,WX8578);
dff DFF_1273(CK,WX8581,WX8580);
dff DFF_1274(CK,WX8583,WX8582);
dff DFF_1275(CK,WX8585,WX8584);
dff DFF_1276(CK,WX8587,WX8586);
dff DFF_1277(CK,WX8589,WX8588);
dff DFF_1278(CK,WX8591,WX8590);
dff DFF_1279(CK,WX8593,WX8592);
dff DFF_1280(CK,WX8595,WX8594);
dff DFF_1281(CK,WX8597,WX8596);
dff DFF_1282(CK,WX8599,WX8598);
dff DFF_1283(CK,WX8601,WX8600);
dff DFF_1284(CK,WX8603,WX8602);
dff DFF_1285(CK,WX8605,WX8604);
dff DFF_1286(CK,WX8607,WX8606);
dff DFF_1287(CK,WX8609,WX8608);
dff DFF_1288(CK,WX8611,WX8610);
dff DFF_1289(CK,WX8613,WX8612);
dff DFF_1290(CK,WX8615,WX8614);
dff DFF_1291(CK,WX8617,WX8616);
dff DFF_1292(CK,WX8619,WX8618);
dff DFF_1293(CK,WX8621,WX8620);
dff DFF_1294(CK,WX8623,WX8622);
dff DFF_1295(CK,WX8625,WX8624);
dff DFF_1296(CK,WX8627,WX8626);
dff DFF_1297(CK,WX8629,WX8628);
dff DFF_1298(CK,WX8631,WX8630);
dff DFF_1299(CK,WX8633,WX8632);
dff DFF_1300(CK,WX8635,WX8634);
dff DFF_1301(CK,WX8637,WX8636);
dff DFF_1302(CK,WX8639,WX8638);
dff DFF_1303(CK,WX8641,WX8640);
dff DFF_1304(CK,WX8643,WX8642);
dff DFF_1305(CK,WX8645,WX8644);
dff DFF_1306(CK,WX8647,WX8646);
dff DFF_1307(CK,WX8649,WX8648);
dff DFF_1308(CK,WX8651,WX8650);
dff DFF_1309(CK,WX8653,WX8652);
dff DFF_1310(CK,WX8655,WX8654);
dff DFF_1311(CK,WX8657,WX8656);
dff DFF_1312(CK,CRC_OUT_3_0,WX9022);
dff DFF_1313(CK,CRC_OUT_3_1,WX9024);
dff DFF_1314(CK,CRC_OUT_3_2,WX9026);
dff DFF_1315(CK,CRC_OUT_3_3,WX9028);
dff DFF_1316(CK,CRC_OUT_3_4,WX9030);
dff DFF_1317(CK,CRC_OUT_3_5,WX9032);
dff DFF_1318(CK,CRC_OUT_3_6,WX9034);
dff DFF_1319(CK,CRC_OUT_3_7,WX9036);
dff DFF_1320(CK,CRC_OUT_3_8,WX9038);
dff DFF_1321(CK,CRC_OUT_3_9,WX9040);
dff DFF_1322(CK,CRC_OUT_3_10,WX9042);
dff DFF_1323(CK,CRC_OUT_3_11,WX9044);
dff DFF_1324(CK,CRC_OUT_3_12,WX9046);
dff DFF_1325(CK,CRC_OUT_3_13,WX9048);
dff DFF_1326(CK,CRC_OUT_3_14,WX9050);
dff DFF_1327(CK,CRC_OUT_3_15,WX9052);
dff DFF_1328(CK,CRC_OUT_3_16,WX9054);
dff DFF_1329(CK,CRC_OUT_3_17,WX9056);
dff DFF_1330(CK,CRC_OUT_3_18,WX9058);
dff DFF_1331(CK,CRC_OUT_3_19,WX9060);
dff DFF_1332(CK,CRC_OUT_3_20,WX9062);
dff DFF_1333(CK,CRC_OUT_3_21,WX9064);
dff DFF_1334(CK,CRC_OUT_3_22,WX9066);
dff DFF_1335(CK,CRC_OUT_3_23,WX9068);
dff DFF_1336(CK,CRC_OUT_3_24,WX9070);
dff DFF_1337(CK,CRC_OUT_3_25,WX9072);
dff DFF_1338(CK,CRC_OUT_3_26,WX9074);
dff DFF_1339(CK,CRC_OUT_3_27,WX9076);
dff DFF_1340(CK,CRC_OUT_3_28,WX9078);
dff DFF_1341(CK,CRC_OUT_3_29,WX9080);
dff DFF_1342(CK,CRC_OUT_3_30,WX9082);
dff DFF_1343(CK,CRC_OUT_3_31,WX9084);
dff DFF_1344(CK,WX9536,WX9535);
dff DFF_1345(CK,WX9538,WX9537);
dff DFF_1346(CK,WX9540,WX9539);
dff DFF_1347(CK,WX9542,WX9541);
dff DFF_1348(CK,WX9544,WX9543);
dff DFF_1349(CK,WX9546,WX9545);
dff DFF_1350(CK,WX9548,WX9547);
dff DFF_1351(CK,WX9550,WX9549);
dff DFF_1352(CK,WX9552,WX9551);
dff DFF_1353(CK,WX9554,WX9553);
dff DFF_1354(CK,WX9556,WX9555);
dff DFF_1355(CK,WX9558,WX9557);
dff DFF_1356(CK,WX9560,WX9559);
dff DFF_1357(CK,WX9562,WX9561);
dff DFF_1358(CK,WX9564,WX9563);
dff DFF_1359(CK,WX9566,WX9565);
dff DFF_1360(CK,WX9568,WX9567);
dff DFF_1361(CK,WX9570,WX9569);
dff DFF_1362(CK,WX9572,WX9571);
dff DFF_1363(CK,WX9574,WX9573);
dff DFF_1364(CK,WX9576,WX9575);
dff DFF_1365(CK,WX9578,WX9577);
dff DFF_1366(CK,WX9580,WX9579);
dff DFF_1367(CK,WX9582,WX9581);
dff DFF_1368(CK,WX9584,WX9583);
dff DFF_1369(CK,WX9586,WX9585);
dff DFF_1370(CK,WX9588,WX9587);
dff DFF_1371(CK,WX9590,WX9589);
dff DFF_1372(CK,WX9592,WX9591);
dff DFF_1373(CK,WX9594,WX9593);
dff DFF_1374(CK,WX9596,WX9595);
dff DFF_1375(CK,WX9598,WX9597);
dff DFF_1376(CK,WX9696,WX9695);
dff DFF_1377(CK,WX9698,WX9697);
dff DFF_1378(CK,WX9700,WX9699);
dff DFF_1379(CK,WX9702,WX9701);
dff DFF_1380(CK,WX9704,WX9703);
dff DFF_1381(CK,WX9706,WX9705);
dff DFF_1382(CK,WX9708,WX9707);
dff DFF_1383(CK,WX9710,WX9709);
dff DFF_1384(CK,WX9712,WX9711);
dff DFF_1385(CK,WX9714,WX9713);
dff DFF_1386(CK,WX9716,WX9715);
dff DFF_1387(CK,WX9718,WX9717);
dff DFF_1388(CK,WX9720,WX9719);
dff DFF_1389(CK,WX9722,WX9721);
dff DFF_1390(CK,WX9724,WX9723);
dff DFF_1391(CK,WX9726,WX9725);
dff DFF_1392(CK,WX9728,WX9727);
dff DFF_1393(CK,WX9730,WX9729);
dff DFF_1394(CK,WX9732,WX9731);
dff DFF_1395(CK,WX9734,WX9733);
dff DFF_1396(CK,WX9736,WX9735);
dff DFF_1397(CK,WX9738,WX9737);
dff DFF_1398(CK,WX9740,WX9739);
dff DFF_1399(CK,WX9742,WX9741);
dff DFF_1400(CK,WX9744,WX9743);
dff DFF_1401(CK,WX9746,WX9745);
dff DFF_1402(CK,WX9748,WX9747);
dff DFF_1403(CK,WX9750,WX9749);
dff DFF_1404(CK,WX9752,WX9751);
dff DFF_1405(CK,WX9754,WX9753);
dff DFF_1406(CK,WX9756,WX9755);
dff DFF_1407(CK,WX9758,WX9757);
dff DFF_1408(CK,WX9760,WX9759);
dff DFF_1409(CK,WX9762,WX9761);
dff DFF_1410(CK,WX9764,WX9763);
dff DFF_1411(CK,WX9766,WX9765);
dff DFF_1412(CK,WX9768,WX9767);
dff DFF_1413(CK,WX9770,WX9769);
dff DFF_1414(CK,WX9772,WX9771);
dff DFF_1415(CK,WX9774,WX9773);
dff DFF_1416(CK,WX9776,WX9775);
dff DFF_1417(CK,WX9778,WX9777);
dff DFF_1418(CK,WX9780,WX9779);
dff DFF_1419(CK,WX9782,WX9781);
dff DFF_1420(CK,WX9784,WX9783);
dff DFF_1421(CK,WX9786,WX9785);
dff DFF_1422(CK,WX9788,WX9787);
dff DFF_1423(CK,WX9790,WX9789);
dff DFF_1424(CK,WX9792,WX9791);
dff DFF_1425(CK,WX9794,WX9793);
dff DFF_1426(CK,WX9796,WX9795);
dff DFF_1427(CK,WX9798,WX9797);
dff DFF_1428(CK,WX9800,WX9799);
dff DFF_1429(CK,WX9802,WX9801);
dff DFF_1430(CK,WX9804,WX9803);
dff DFF_1431(CK,WX9806,WX9805);
dff DFF_1432(CK,WX9808,WX9807);
dff DFF_1433(CK,WX9810,WX9809);
dff DFF_1434(CK,WX9812,WX9811);
dff DFF_1435(CK,WX9814,WX9813);
dff DFF_1436(CK,WX9816,WX9815);
dff DFF_1437(CK,WX9818,WX9817);
dff DFF_1438(CK,WX9820,WX9819);
dff DFF_1439(CK,WX9822,WX9821);
dff DFF_1440(CK,WX9824,WX9823);
dff DFF_1441(CK,WX9826,WX9825);
dff DFF_1442(CK,WX9828,WX9827);
dff DFF_1443(CK,WX9830,WX9829);
dff DFF_1444(CK,WX9832,WX9831);
dff DFF_1445(CK,WX9834,WX9833);
dff DFF_1446(CK,WX9836,WX9835);
dff DFF_1447(CK,WX9838,WX9837);
dff DFF_1448(CK,WX9840,WX9839);
dff DFF_1449(CK,WX9842,WX9841);
dff DFF_1450(CK,WX9844,WX9843);
dff DFF_1451(CK,WX9846,WX9845);
dff DFF_1452(CK,WX9848,WX9847);
dff DFF_1453(CK,WX9850,WX9849);
dff DFF_1454(CK,WX9852,WX9851);
dff DFF_1455(CK,WX9854,WX9853);
dff DFF_1456(CK,WX9856,WX9855);
dff DFF_1457(CK,WX9858,WX9857);
dff DFF_1458(CK,WX9860,WX9859);
dff DFF_1459(CK,WX9862,WX9861);
dff DFF_1460(CK,WX9864,WX9863);
dff DFF_1461(CK,WX9866,WX9865);
dff DFF_1462(CK,WX9868,WX9867);
dff DFF_1463(CK,WX9870,WX9869);
dff DFF_1464(CK,WX9872,WX9871);
dff DFF_1465(CK,WX9874,WX9873);
dff DFF_1466(CK,WX9876,WX9875);
dff DFF_1467(CK,WX9878,WX9877);
dff DFF_1468(CK,WX9880,WX9879);
dff DFF_1469(CK,WX9882,WX9881);
dff DFF_1470(CK,WX9884,WX9883);
dff DFF_1471(CK,WX9886,WX9885);
dff DFF_1472(CK,WX9888,WX9887);
dff DFF_1473(CK,WX9890,WX9889);
dff DFF_1474(CK,WX9892,WX9891);
dff DFF_1475(CK,WX9894,WX9893);
dff DFF_1476(CK,WX9896,WX9895);
dff DFF_1477(CK,WX9898,WX9897);
dff DFF_1478(CK,WX9900,WX9899);
dff DFF_1479(CK,WX9902,WX9901);
dff DFF_1480(CK,WX9904,WX9903);
dff DFF_1481(CK,WX9906,WX9905);
dff DFF_1482(CK,WX9908,WX9907);
dff DFF_1483(CK,WX9910,WX9909);
dff DFF_1484(CK,WX9912,WX9911);
dff DFF_1485(CK,WX9914,WX9913);
dff DFF_1486(CK,WX9916,WX9915);
dff DFF_1487(CK,WX9918,WX9917);
dff DFF_1488(CK,WX9920,WX9919);
dff DFF_1489(CK,WX9922,WX9921);
dff DFF_1490(CK,WX9924,WX9923);
dff DFF_1491(CK,WX9926,WX9925);
dff DFF_1492(CK,WX9928,WX9927);
dff DFF_1493(CK,WX9930,WX9929);
dff DFF_1494(CK,WX9932,WX9931);
dff DFF_1495(CK,WX9934,WX9933);
dff DFF_1496(CK,WX9936,WX9935);
dff DFF_1497(CK,WX9938,WX9937);
dff DFF_1498(CK,WX9940,WX9939);
dff DFF_1499(CK,WX9942,WX9941);
dff DFF_1500(CK,WX9944,WX9943);
dff DFF_1501(CK,WX9946,WX9945);
dff DFF_1502(CK,WX9948,WX9947);
dff DFF_1503(CK,WX9950,WX9949);
dff DFF_1504(CK,CRC_OUT_2_0,WX10315);
dff DFF_1505(CK,CRC_OUT_2_1,WX10317);
dff DFF_1506(CK,CRC_OUT_2_2,WX10319);
dff DFF_1507(CK,CRC_OUT_2_3,WX10321);
dff DFF_1508(CK,CRC_OUT_2_4,WX10323);
dff DFF_1509(CK,CRC_OUT_2_5,WX10325);
dff DFF_1510(CK,CRC_OUT_2_6,WX10327);
dff DFF_1511(CK,CRC_OUT_2_7,WX10329);
dff DFF_1512(CK,CRC_OUT_2_8,WX10331);
dff DFF_1513(CK,CRC_OUT_2_9,WX10333);
dff DFF_1514(CK,CRC_OUT_2_10,WX10335);
dff DFF_1515(CK,CRC_OUT_2_11,WX10337);
dff DFF_1516(CK,CRC_OUT_2_12,WX10339);
dff DFF_1517(CK,CRC_OUT_2_13,WX10341);
dff DFF_1518(CK,CRC_OUT_2_14,WX10343);
dff DFF_1519(CK,CRC_OUT_2_15,WX10345);
dff DFF_1520(CK,CRC_OUT_2_16,WX10347);
dff DFF_1521(CK,CRC_OUT_2_17,WX10349);
dff DFF_1522(CK,CRC_OUT_2_18,WX10351);
dff DFF_1523(CK,CRC_OUT_2_19,WX10353);
dff DFF_1524(CK,CRC_OUT_2_20,WX10355);
dff DFF_1525(CK,CRC_OUT_2_21,WX10357);
dff DFF_1526(CK,CRC_OUT_2_22,WX10359);
dff DFF_1527(CK,CRC_OUT_2_23,WX10361);
dff DFF_1528(CK,CRC_OUT_2_24,WX10363);
dff DFF_1529(CK,CRC_OUT_2_25,WX10365);
dff DFF_1530(CK,CRC_OUT_2_26,WX10367);
dff DFF_1531(CK,CRC_OUT_2_27,WX10369);
dff DFF_1532(CK,CRC_OUT_2_28,WX10371);
dff DFF_1533(CK,CRC_OUT_2_29,WX10373);
dff DFF_1534(CK,CRC_OUT_2_30,WX10375);
dff DFF_1535(CK,CRC_OUT_2_31,WX10377);
dff DFF_1536(CK,WX10829,WX10828);
dff DFF_1537(CK,WX10831,WX10830);
dff DFF_1538(CK,WX10833,WX10832);
dff DFF_1539(CK,WX10835,WX10834);
dff DFF_1540(CK,WX10837,WX10836);
dff DFF_1541(CK,WX10839,WX10838);
dff DFF_1542(CK,WX10841,WX10840);
dff DFF_1543(CK,WX10843,WX10842);
dff DFF_1544(CK,WX10845,WX10844);
dff DFF_1545(CK,WX10847,WX10846);
dff DFF_1546(CK,WX10849,WX10848);
dff DFF_1547(CK,WX10851,WX10850);
dff DFF_1548(CK,WX10853,WX10852);
dff DFF_1549(CK,WX10855,WX10854);
dff DFF_1550(CK,WX10857,WX10856);
dff DFF_1551(CK,WX10859,WX10858);
dff DFF_1552(CK,WX10861,WX10860);
dff DFF_1553(CK,WX10863,WX10862);
dff DFF_1554(CK,WX10865,WX10864);
dff DFF_1555(CK,WX10867,WX10866);
dff DFF_1556(CK,WX10869,WX10868);
dff DFF_1557(CK,WX10871,WX10870);
dff DFF_1558(CK,WX10873,WX10872);
dff DFF_1559(CK,WX10875,WX10874);
dff DFF_1560(CK,WX10877,WX10876);
dff DFF_1561(CK,WX10879,WX10878);
dff DFF_1562(CK,WX10881,WX10880);
dff DFF_1563(CK,WX10883,WX10882);
dff DFF_1564(CK,WX10885,WX10884);
dff DFF_1565(CK,WX10887,WX10886);
dff DFF_1566(CK,WX10889,WX10888);
dff DFF_1567(CK,WX10891,WX10890);
dff DFF_1568(CK,WX10989,WX10988);
dff DFF_1569(CK,WX10991,WX10990);
dff DFF_1570(CK,WX10993,WX10992);
dff DFF_1571(CK,WX10995,WX10994);
dff DFF_1572(CK,WX10997,WX10996);
dff DFF_1573(CK,WX10999,WX10998);
dff DFF_1574(CK,WX11001,WX11000);
dff DFF_1575(CK,WX11003,WX11002);
dff DFF_1576(CK,WX11005,WX11004);
dff DFF_1577(CK,WX11007,WX11006);
dff DFF_1578(CK,WX11009,WX11008);
dff DFF_1579(CK,WX11011,WX11010);
dff DFF_1580(CK,WX11013,WX11012);
dff DFF_1581(CK,WX11015,WX11014);
dff DFF_1582(CK,WX11017,WX11016);
dff DFF_1583(CK,WX11019,WX11018);
dff DFF_1584(CK,WX11021,WX11020);
dff DFF_1585(CK,WX11023,WX11022);
dff DFF_1586(CK,WX11025,WX11024);
dff DFF_1587(CK,WX11027,WX11026);
dff DFF_1588(CK,WX11029,WX11028);
dff DFF_1589(CK,WX11031,WX11030);
dff DFF_1590(CK,WX11033,WX11032);
dff DFF_1591(CK,WX11035,WX11034);
dff DFF_1592(CK,WX11037,WX11036);
dff DFF_1593(CK,WX11039,WX11038);
dff DFF_1594(CK,WX11041,WX11040);
dff DFF_1595(CK,WX11043,WX11042);
dff DFF_1596(CK,WX11045,WX11044);
dff DFF_1597(CK,WX11047,WX11046);
dff DFF_1598(CK,WX11049,WX11048);
dff DFF_1599(CK,WX11051,WX11050);
dff DFF_1600(CK,WX11053,WX11052);
dff DFF_1601(CK,WX11055,WX11054);
dff DFF_1602(CK,WX11057,WX11056);
dff DFF_1603(CK,WX11059,WX11058);
dff DFF_1604(CK,WX11061,WX11060);
dff DFF_1605(CK,WX11063,WX11062);
dff DFF_1606(CK,WX11065,WX11064);
dff DFF_1607(CK,WX11067,WX11066);
dff DFF_1608(CK,WX11069,WX11068);
dff DFF_1609(CK,WX11071,WX11070);
dff DFF_1610(CK,WX11073,WX11072);
dff DFF_1611(CK,WX11075,WX11074);
dff DFF_1612(CK,WX11077,WX11076);
dff DFF_1613(CK,WX11079,WX11078);
dff DFF_1614(CK,WX11081,WX11080);
dff DFF_1615(CK,WX11083,WX11082);
dff DFF_1616(CK,WX11085,WX11084);
dff DFF_1617(CK,WX11087,WX11086);
dff DFF_1618(CK,WX11089,WX11088);
dff DFF_1619(CK,WX11091,WX11090);
dff DFF_1620(CK,WX11093,WX11092);
dff DFF_1621(CK,WX11095,WX11094);
dff DFF_1622(CK,WX11097,WX11096);
dff DFF_1623(CK,WX11099,WX11098);
dff DFF_1624(CK,WX11101,WX11100);
dff DFF_1625(CK,WX11103,WX11102);
dff DFF_1626(CK,WX11105,WX11104);
dff DFF_1627(CK,WX11107,WX11106);
dff DFF_1628(CK,WX11109,WX11108);
dff DFF_1629(CK,WX11111,WX11110);
dff DFF_1630(CK,WX11113,WX11112);
dff DFF_1631(CK,WX11115,WX11114);
dff DFF_1632(CK,WX11117,WX11116);
dff DFF_1633(CK,WX11119,WX11118);
dff DFF_1634(CK,WX11121,WX11120);
dff DFF_1635(CK,WX11123,WX11122);
dff DFF_1636(CK,WX11125,WX11124);
dff DFF_1637(CK,WX11127,WX11126);
dff DFF_1638(CK,WX11129,WX11128);
dff DFF_1639(CK,WX11131,WX11130);
dff DFF_1640(CK,WX11133,WX11132);
dff DFF_1641(CK,WX11135,WX11134);
dff DFF_1642(CK,WX11137,WX11136);
dff DFF_1643(CK,WX11139,WX11138);
dff DFF_1644(CK,WX11141,WX11140);
dff DFF_1645(CK,WX11143,WX11142);
dff DFF_1646(CK,WX11145,WX11144);
dff DFF_1647(CK,WX11147,WX11146);
dff DFF_1648(CK,WX11149,WX11148);
dff DFF_1649(CK,WX11151,WX11150);
dff DFF_1650(CK,WX11153,WX11152);
dff DFF_1651(CK,WX11155,WX11154);
dff DFF_1652(CK,WX11157,WX11156);
dff DFF_1653(CK,WX11159,WX11158);
dff DFF_1654(CK,WX11161,WX11160);
dff DFF_1655(CK,WX11163,WX11162);
dff DFF_1656(CK,WX11165,WX11164);
dff DFF_1657(CK,WX11167,WX11166);
dff DFF_1658(CK,WX11169,WX11168);
dff DFF_1659(CK,WX11171,WX11170);
dff DFF_1660(CK,WX11173,WX11172);
dff DFF_1661(CK,WX11175,WX11174);
dff DFF_1662(CK,WX11177,WX11176);
dff DFF_1663(CK,WX11179,WX11178);
dff DFF_1664(CK,WX11181,WX11180);
dff DFF_1665(CK,WX11183,WX11182);
dff DFF_1666(CK,WX11185,WX11184);
dff DFF_1667(CK,WX11187,WX11186);
dff DFF_1668(CK,WX11189,WX11188);
dff DFF_1669(CK,WX11191,WX11190);
dff DFF_1670(CK,WX11193,WX11192);
dff DFF_1671(CK,WX11195,WX11194);
dff DFF_1672(CK,WX11197,WX11196);
dff DFF_1673(CK,WX11199,WX11198);
dff DFF_1674(CK,WX11201,WX11200);
dff DFF_1675(CK,WX11203,WX11202);
dff DFF_1676(CK,WX11205,WX11204);
dff DFF_1677(CK,WX11207,WX11206);
dff DFF_1678(CK,WX11209,WX11208);
dff DFF_1679(CK,WX11211,WX11210);
dff DFF_1680(CK,WX11213,WX11212);
dff DFF_1681(CK,WX11215,WX11214);
dff DFF_1682(CK,WX11217,WX11216);
dff DFF_1683(CK,WX11219,WX11218);
dff DFF_1684(CK,WX11221,WX11220);
dff DFF_1685(CK,WX11223,WX11222);
dff DFF_1686(CK,WX11225,WX11224);
dff DFF_1687(CK,WX11227,WX11226);
dff DFF_1688(CK,WX11229,WX11228);
dff DFF_1689(CK,WX11231,WX11230);
dff DFF_1690(CK,WX11233,WX11232);
dff DFF_1691(CK,WX11235,WX11234);
dff DFF_1692(CK,WX11237,WX11236);
dff DFF_1693(CK,WX11239,WX11238);
dff DFF_1694(CK,WX11241,WX11240);
dff DFF_1695(CK,WX11243,WX11242);
dff DFF_1696(CK,CRC_OUT_1_0,WX11608);
dff DFF_1697(CK,CRC_OUT_1_1,WX11610);
dff DFF_1698(CK,CRC_OUT_1_2,WX11612);
dff DFF_1699(CK,CRC_OUT_1_3,WX11614);
dff DFF_1700(CK,CRC_OUT_1_4,WX11616);
dff DFF_1701(CK,CRC_OUT_1_5,WX11618);
dff DFF_1702(CK,CRC_OUT_1_6,WX11620);
dff DFF_1703(CK,CRC_OUT_1_7,WX11622);
dff DFF_1704(CK,CRC_OUT_1_8,WX11624);
dff DFF_1705(CK,CRC_OUT_1_9,WX11626);
dff DFF_1706(CK,CRC_OUT_1_10,WX11628);
dff DFF_1707(CK,CRC_OUT_1_11,WX11630);
dff DFF_1708(CK,CRC_OUT_1_12,WX11632);
dff DFF_1709(CK,CRC_OUT_1_13,WX11634);
dff DFF_1710(CK,CRC_OUT_1_14,WX11636);
dff DFF_1711(CK,CRC_OUT_1_15,WX11638);
dff DFF_1712(CK,CRC_OUT_1_16,WX11640);
dff DFF_1713(CK,CRC_OUT_1_17,WX11642);
dff DFF_1714(CK,CRC_OUT_1_18,WX11644);
dff DFF_1715(CK,CRC_OUT_1_19,WX11646);
dff DFF_1716(CK,CRC_OUT_1_20,WX11648);
dff DFF_1717(CK,CRC_OUT_1_21,WX11650);
dff DFF_1718(CK,CRC_OUT_1_22,WX11652);
dff DFF_1719(CK,CRC_OUT_1_23,WX11654);
dff DFF_1720(CK,CRC_OUT_1_24,WX11656);
dff DFF_1721(CK,CRC_OUT_1_25,WX11658);
dff DFF_1722(CK,CRC_OUT_1_26,WX11660);
dff DFF_1723(CK,CRC_OUT_1_27,WX11662);
dff DFF_1724(CK,CRC_OUT_1_28,WX11664);
dff DFF_1725(CK,CRC_OUT_1_29,WX11666);
dff DFF_1726(CK,CRC_OUT_1_30,WX11668);
dff DFF_1727(CK,CRC_OUT_1_31,WX11670);
not NOT_0(WX37,WX1003);
not NOT_1(WX41,WX1004);
not NOT_2(WX45,WX1004);
not NOT_3(WX47,WX38);
not NOT_4(WX48,WX47);
not NOT_5(WX51,WX1003);
not NOT_6(WX55,WX1004);
not NOT_7(WX59,WX1004);
not NOT_8(WX61,WX52);
not NOT_9(WX62,WX61);
not NOT_10(WX65,WX1003);
not NOT_11(WX69,WX1004);
not NOT_12(WX73,WX1004);
not NOT_13(WX75,WX66);
not NOT_14(WX76,WX75);
not NOT_15(WX79,WX1003);
not NOT_16(WX83,WX1004);
not NOT_17(WX87,WX1004);
not NOT_18(WX89,WX80);
not NOT_19(WX90,WX89);
not NOT_20(WX93,WX1003);
not NOT_21(WX97,WX1004);
not NOT_22(WX101,WX1004);
not NOT_23(WX103,WX94);
not NOT_24(WX104,WX103);
not NOT_25(WX107,WX1003);
not NOT_26(WX111,WX1004);
not NOT_27(WX115,WX1004);
not NOT_28(WX117,WX108);
not NOT_29(WX118,WX117);
not NOT_30(WX121,WX1003);
not NOT_31(WX125,WX1004);
not NOT_32(WX129,WX1004);
not NOT_33(WX131,WX122);
not NOT_34(WX132,WX131);
not NOT_35(WX135,WX1003);
not NOT_36(WX139,WX1004);
not NOT_37(WX143,WX1004);
not NOT_38(WX145,WX136);
not NOT_39(WX146,WX145);
not NOT_40(WX149,WX1003);
not NOT_41(WX153,WX1004);
not NOT_42(WX157,WX1004);
not NOT_43(WX159,WX150);
not NOT_44(WX160,WX159);
not NOT_45(WX163,WX1003);
not NOT_46(WX167,WX1004);
not NOT_47(WX171,WX1004);
not NOT_48(WX173,WX164);
not NOT_49(WX174,WX173);
not NOT_50(WX177,WX1003);
not NOT_51(WX181,WX1004);
not NOT_52(WX185,WX1004);
not NOT_53(WX187,WX178);
not NOT_54(WX188,WX187);
not NOT_55(WX191,WX1003);
not NOT_56(WX195,WX1004);
not NOT_57(WX199,WX1004);
not NOT_58(WX201,WX192);
not NOT_59(WX202,WX201);
not NOT_60(WX205,WX1003);
not NOT_61(WX209,WX1004);
not NOT_62(WX213,WX1004);
not NOT_63(WX215,WX206);
not NOT_64(WX216,WX215);
not NOT_65(WX219,WX1003);
not NOT_66(WX223,WX1004);
not NOT_67(WX227,WX1004);
not NOT_68(WX229,WX220);
not NOT_69(WX230,WX229);
not NOT_70(WX233,WX1003);
not NOT_71(WX237,WX1004);
not NOT_72(WX241,WX1004);
not NOT_73(WX243,WX234);
not NOT_74(WX244,WX243);
not NOT_75(WX247,WX1003);
not NOT_76(WX251,WX1004);
not NOT_77(WX255,WX1004);
not NOT_78(WX257,WX248);
not NOT_79(WX258,WX257);
not NOT_80(WX261,WX1003);
not NOT_81(WX265,WX1004);
not NOT_82(WX269,WX1004);
not NOT_83(WX271,WX262);
not NOT_84(WX272,WX271);
not NOT_85(WX275,WX1003);
not NOT_86(WX279,WX1004);
not NOT_87(WX283,WX1004);
not NOT_88(WX285,WX276);
not NOT_89(WX286,WX285);
not NOT_90(WX289,WX1003);
not NOT_91(WX293,WX1004);
not NOT_92(WX297,WX1004);
not NOT_93(WX299,WX290);
not NOT_94(WX300,WX299);
not NOT_95(WX303,WX1003);
not NOT_96(WX307,WX1004);
not NOT_97(WX311,WX1004);
not NOT_98(WX313,WX304);
not NOT_99(WX314,WX313);
not NOT_100(WX317,WX1003);
not NOT_101(WX321,WX1004);
not NOT_102(WX325,WX1004);
not NOT_103(WX327,WX318);
not NOT_104(WX328,WX327);
not NOT_105(WX331,WX1003);
not NOT_106(WX335,WX1004);
not NOT_107(WX339,WX1004);
not NOT_108(WX341,WX332);
not NOT_109(WX342,WX341);
not NOT_110(WX345,WX1003);
not NOT_111(WX349,WX1004);
not NOT_112(WX353,WX1004);
not NOT_113(WX355,WX346);
not NOT_114(WX356,WX355);
not NOT_115(WX359,WX1003);
not NOT_116(WX363,WX1004);
not NOT_117(WX367,WX1004);
not NOT_118(WX369,WX360);
not NOT_119(WX370,WX369);
not NOT_120(WX373,WX1003);
not NOT_121(WX377,WX1004);
not NOT_122(WX381,WX1004);
not NOT_123(WX383,WX374);
not NOT_124(WX384,WX383);
not NOT_125(WX387,WX1003);
not NOT_126(WX391,WX1004);
not NOT_127(WX395,WX1004);
not NOT_128(WX397,WX388);
not NOT_129(WX398,WX397);
not NOT_130(WX401,WX1003);
not NOT_131(WX405,WX1004);
not NOT_132(WX409,WX1004);
not NOT_133(WX411,WX402);
not NOT_134(WX412,WX411);
not NOT_135(WX415,WX1003);
not NOT_136(WX419,WX1004);
not NOT_137(WX423,WX1004);
not NOT_138(WX425,WX416);
not NOT_139(WX426,WX425);
not NOT_140(WX429,WX1003);
not NOT_141(WX433,WX1004);
not NOT_142(WX437,WX1004);
not NOT_143(WX439,WX430);
not NOT_144(WX440,WX439);
not NOT_145(WX443,WX1003);
not NOT_146(WX447,WX1004);
not NOT_147(WX451,WX1004);
not NOT_148(WX453,WX444);
not NOT_149(WX454,WX453);
not NOT_150(WX457,WX1003);
not NOT_151(WX461,WX1004);
not NOT_152(WX465,WX1004);
not NOT_153(WX467,WX458);
not NOT_154(WX468,WX467);
not NOT_155(WX471,WX1003);
not NOT_156(WX475,WX1004);
not NOT_157(WX479,WX1004);
not NOT_158(WX481,WX472);
not NOT_159(WX482,WX481);
not NOT_160(WX483,WX485);
not NOT_161(WX548,WX965);
not NOT_162(WX549,WX967);
not NOT_163(WX550,WX969);
not NOT_164(WX551,WX971);
not NOT_165(WX552,WX973);
not NOT_166(WX553,WX975);
not NOT_167(WX554,WX977);
not NOT_168(WX555,WX979);
not NOT_169(WX556,WX981);
not NOT_170(WX557,WX983);
not NOT_171(WX558,WX985);
not NOT_172(WX559,WX987);
not NOT_173(WX560,WX989);
not NOT_174(WX561,WX991);
not NOT_175(WX562,WX993);
not NOT_176(WX563,WX995);
not NOT_177(WX564,WX933);
not NOT_178(WX565,WX935);
not NOT_179(WX566,WX937);
not NOT_180(WX567,WX939);
not NOT_181(WX568,WX941);
not NOT_182(WX569,WX943);
not NOT_183(WX570,WX945);
not NOT_184(WX571,WX947);
not NOT_185(WX572,WX949);
not NOT_186(WX573,WX951);
not NOT_187(WX574,WX953);
not NOT_188(WX575,WX955);
not NOT_189(WX576,WX957);
not NOT_190(WX577,WX959);
not NOT_191(WX578,WX961);
not NOT_192(WX579,WX963);
not NOT_193(WX580,WX548);
not NOT_194(WX581,WX549);
not NOT_195(WX582,WX550);
not NOT_196(WX583,WX551);
not NOT_197(WX584,WX552);
not NOT_198(WX585,WX553);
not NOT_199(WX586,WX554);
not NOT_200(WX587,WX555);
not NOT_201(WX588,WX556);
not NOT_202(WX589,WX557);
not NOT_203(WX590,WX558);
not NOT_204(WX591,WX559);
not NOT_205(WX592,WX560);
not NOT_206(WX593,WX561);
not NOT_207(WX594,WX562);
not NOT_208(WX595,WX563);
not NOT_209(WX596,WX564);
not NOT_210(WX597,WX565);
not NOT_211(WX598,WX566);
not NOT_212(WX599,WX567);
not NOT_213(WX600,WX568);
not NOT_214(WX601,WX569);
not NOT_215(WX602,WX570);
not NOT_216(WX603,WX571);
not NOT_217(WX604,WX572);
not NOT_218(WX605,WX573);
not NOT_219(WX606,WX574);
not NOT_220(WX607,WX575);
not NOT_221(WX608,WX576);
not NOT_222(WX609,WX577);
not NOT_223(WX610,WX578);
not NOT_224(WX611,WX579);
not NOT_225(WX612,WX837);
not NOT_226(WX613,WX839);
not NOT_227(WX614,WX841);
not NOT_228(WX615,WX843);
not NOT_229(WX616,WX845);
not NOT_230(WX617,WX847);
not NOT_231(WX618,WX849);
not NOT_232(WX619,WX851);
not NOT_233(WX620,WX853);
not NOT_234(WX621,WX855);
not NOT_235(WX622,WX857);
not NOT_236(WX623,WX859);
not NOT_237(WX624,WX861);
not NOT_238(WX625,WX863);
not NOT_239(WX626,WX865);
not NOT_240(WX627,WX867);
not NOT_241(WX628,WX869);
not NOT_242(WX629,WX871);
not NOT_243(WX630,WX873);
not NOT_244(WX631,WX875);
not NOT_245(WX632,WX877);
not NOT_246(WX633,WX879);
not NOT_247(WX634,WX881);
not NOT_248(WX635,WX883);
not NOT_249(WX636,WX885);
not NOT_250(WX637,WX887);
not NOT_251(WX638,WX889);
not NOT_252(WX639,WX891);
not NOT_253(WX640,WX893);
not NOT_254(WX641,WX895);
not NOT_255(WX642,WX897);
not NOT_256(WX643,WX899);
not NOT_257(WX932,WX916);
not NOT_258(WX933,WX932);
not NOT_259(WX934,WX917);
not NOT_260(WX935,WX934);
not NOT_261(WX936,WX918);
not NOT_262(WX937,WX936);
not NOT_263(WX938,WX919);
not NOT_264(WX939,WX938);
not NOT_265(WX940,WX920);
not NOT_266(WX941,WX940);
not NOT_267(WX942,WX921);
not NOT_268(WX943,WX942);
not NOT_269(WX944,WX922);
not NOT_270(WX945,WX944);
not NOT_271(WX946,WX923);
not NOT_272(WX947,WX946);
not NOT_273(WX948,WX924);
not NOT_274(WX949,WX948);
not NOT_275(WX950,WX925);
not NOT_276(WX951,WX950);
not NOT_277(WX952,WX926);
not NOT_278(WX953,WX952);
not NOT_279(WX954,WX927);
not NOT_280(WX955,WX954);
not NOT_281(WX956,WX928);
not NOT_282(WX957,WX956);
not NOT_283(WX958,WX929);
not NOT_284(WX959,WX958);
not NOT_285(WX960,WX930);
not NOT_286(WX961,WX960);
not NOT_287(WX962,WX931);
not NOT_288(WX963,WX962);
not NOT_289(WX964,WX900);
not NOT_290(WX965,WX964);
not NOT_291(WX966,WX901);
not NOT_292(WX967,WX966);
not NOT_293(WX968,WX902);
not NOT_294(WX969,WX968);
not NOT_295(WX970,WX903);
not NOT_296(WX971,WX970);
not NOT_297(WX972,WX904);
not NOT_298(WX973,WX972);
not NOT_299(WX974,WX905);
not NOT_300(WX975,WX974);
not NOT_301(WX976,WX906);
not NOT_302(WX977,WX976);
not NOT_303(WX978,WX907);
not NOT_304(WX979,WX978);
not NOT_305(WX980,WX908);
not NOT_306(WX981,WX980);
not NOT_307(WX982,WX909);
not NOT_308(WX983,WX982);
not NOT_309(WX984,WX910);
not NOT_310(WX985,WX984);
not NOT_311(WX986,WX911);
not NOT_312(WX987,WX986);
not NOT_313(WX988,WX912);
not NOT_314(WX989,WX988);
not NOT_315(WX990,WX913);
not NOT_316(WX991,WX990);
not NOT_317(WX992,WX914);
not NOT_318(WX993,WX992);
not NOT_319(WX994,WX915);
not NOT_320(WX995,WX994);
not NOT_321(WX996,TM0);
not NOT_322(WX997,TM0);
not NOT_323(WX998,TM0);
not NOT_324(WX999,TM1);
not NOT_325(WX1000,TM1);
not NOT_326(WX1001,WX1000);
not NOT_327(WX1002,WX998);
not NOT_328(WX1003,WX999);
not NOT_329(WX1004,WX997);
not NOT_330(WX1005,WX996);
not NOT_331(WX1009,WX1005);
not NOT_332(WX1011,WX1010);
not NOT_333(DATA_9_31,WX1011);
not NOT_334(WX1016,WX1005);
not NOT_335(WX1018,WX1017);
not NOT_336(DATA_9_30,WX1018);
not NOT_337(WX1023,WX1005);
not NOT_338(WX1025,WX1024);
not NOT_339(DATA_9_29,WX1025);
not NOT_340(WX1030,WX1005);
not NOT_341(WX1032,WX1031);
not NOT_342(DATA_9_28,WX1032);
not NOT_343(WX1037,WX1005);
not NOT_344(WX1039,WX1038);
not NOT_345(DATA_9_27,WX1039);
not NOT_346(WX1044,WX1005);
not NOT_347(WX1046,WX1045);
not NOT_348(DATA_9_26,WX1046);
not NOT_349(WX1051,WX1005);
not NOT_350(WX1053,WX1052);
not NOT_351(DATA_9_25,WX1053);
not NOT_352(WX1058,WX1005);
not NOT_353(WX1060,WX1059);
not NOT_354(DATA_9_24,WX1060);
not NOT_355(WX1065,WX1005);
not NOT_356(WX1067,WX1066);
not NOT_357(DATA_9_23,WX1067);
not NOT_358(WX1072,WX1005);
not NOT_359(WX1074,WX1073);
not NOT_360(DATA_9_22,WX1074);
not NOT_361(WX1079,WX1005);
not NOT_362(WX1081,WX1080);
not NOT_363(DATA_9_21,WX1081);
not NOT_364(WX1086,WX1005);
not NOT_365(WX1088,WX1087);
not NOT_366(DATA_9_20,WX1088);
not NOT_367(WX1093,WX1005);
not NOT_368(WX1095,WX1094);
not NOT_369(DATA_9_19,WX1095);
not NOT_370(WX1100,WX1005);
not NOT_371(WX1102,WX1101);
not NOT_372(DATA_9_18,WX1102);
not NOT_373(WX1107,WX1005);
not NOT_374(WX1109,WX1108);
not NOT_375(DATA_9_17,WX1109);
not NOT_376(WX1114,WX1005);
not NOT_377(WX1116,WX1115);
not NOT_378(DATA_9_16,WX1116);
not NOT_379(WX1121,WX1005);
not NOT_380(WX1123,WX1122);
not NOT_381(DATA_9_15,WX1123);
not NOT_382(WX1128,WX1005);
not NOT_383(WX1130,WX1129);
not NOT_384(DATA_9_14,WX1130);
not NOT_385(WX1135,WX1005);
not NOT_386(WX1137,WX1136);
not NOT_387(DATA_9_13,WX1137);
not NOT_388(WX1142,WX1005);
not NOT_389(WX1144,WX1143);
not NOT_390(DATA_9_12,WX1144);
not NOT_391(WX1149,WX1005);
not NOT_392(WX1151,WX1150);
not NOT_393(DATA_9_11,WX1151);
not NOT_394(WX1156,WX1005);
not NOT_395(WX1158,WX1157);
not NOT_396(DATA_9_10,WX1158);
not NOT_397(WX1163,WX1005);
not NOT_398(WX1165,WX1164);
not NOT_399(DATA_9_9,WX1165);
not NOT_400(WX1170,WX1005);
not NOT_401(WX1172,WX1171);
not NOT_402(DATA_9_8,WX1172);
not NOT_403(WX1177,WX1005);
not NOT_404(WX1179,WX1178);
not NOT_405(DATA_9_7,WX1179);
not NOT_406(WX1184,WX1005);
not NOT_407(WX1186,WX1185);
not NOT_408(DATA_9_6,WX1186);
not NOT_409(WX1191,WX1005);
not NOT_410(WX1193,WX1192);
not NOT_411(DATA_9_5,WX1193);
not NOT_412(WX1198,WX1005);
not NOT_413(WX1200,WX1199);
not NOT_414(DATA_9_4,WX1200);
not NOT_415(WX1205,WX1005);
not NOT_416(WX1207,WX1206);
not NOT_417(DATA_9_3,WX1207);
not NOT_418(WX1212,WX1005);
not NOT_419(WX1214,WX1213);
not NOT_420(DATA_9_2,WX1214);
not NOT_421(WX1219,WX1005);
not NOT_422(WX1221,WX1220);
not NOT_423(DATA_9_1,WX1221);
not NOT_424(WX1226,WX1005);
not NOT_425(WX1228,WX1227);
not NOT_426(DATA_9_0,WX1228);
not NOT_427(WX1230,RESET);
not NOT_428(WX1263,WX1230);
not NOT_429(WX1330,WX2296);
not NOT_430(WX1334,WX2297);
not NOT_431(WX1338,WX2297);
not NOT_432(WX1340,WX1331);
not NOT_433(WX1341,WX1340);
not NOT_434(WX1344,WX2296);
not NOT_435(WX1348,WX2297);
not NOT_436(WX1352,WX2297);
not NOT_437(WX1354,WX1345);
not NOT_438(WX1355,WX1354);
not NOT_439(WX1358,WX2296);
not NOT_440(WX1362,WX2297);
not NOT_441(WX1366,WX2297);
not NOT_442(WX1368,WX1359);
not NOT_443(WX1369,WX1368);
not NOT_444(WX1372,WX2296);
not NOT_445(WX1376,WX2297);
not NOT_446(WX1380,WX2297);
not NOT_447(WX1382,WX1373);
not NOT_448(WX1383,WX1382);
not NOT_449(WX1386,WX2296);
not NOT_450(WX1390,WX2297);
not NOT_451(WX1394,WX2297);
not NOT_452(WX1396,WX1387);
not NOT_453(WX1397,WX1396);
not NOT_454(WX1400,WX2296);
not NOT_455(WX1404,WX2297);
not NOT_456(WX1408,WX2297);
not NOT_457(WX1410,WX1401);
not NOT_458(WX1411,WX1410);
not NOT_459(WX1414,WX2296);
not NOT_460(WX1418,WX2297);
not NOT_461(WX1422,WX2297);
not NOT_462(WX1424,WX1415);
not NOT_463(WX1425,WX1424);
not NOT_464(WX1428,WX2296);
not NOT_465(WX1432,WX2297);
not NOT_466(WX1436,WX2297);
not NOT_467(WX1438,WX1429);
not NOT_468(WX1439,WX1438);
not NOT_469(WX1442,WX2296);
not NOT_470(WX1446,WX2297);
not NOT_471(WX1450,WX2297);
not NOT_472(WX1452,WX1443);
not NOT_473(WX1453,WX1452);
not NOT_474(WX1456,WX2296);
not NOT_475(WX1460,WX2297);
not NOT_476(WX1464,WX2297);
not NOT_477(WX1466,WX1457);
not NOT_478(WX1467,WX1466);
not NOT_479(WX1470,WX2296);
not NOT_480(WX1474,WX2297);
not NOT_481(WX1478,WX2297);
not NOT_482(WX1480,WX1471);
not NOT_483(WX1481,WX1480);
not NOT_484(WX1484,WX2296);
not NOT_485(WX1488,WX2297);
not NOT_486(WX1492,WX2297);
not NOT_487(WX1494,WX1485);
not NOT_488(WX1495,WX1494);
not NOT_489(WX1498,WX2296);
not NOT_490(WX1502,WX2297);
not NOT_491(WX1506,WX2297);
not NOT_492(WX1508,WX1499);
not NOT_493(WX1509,WX1508);
not NOT_494(WX1512,WX2296);
not NOT_495(WX1516,WX2297);
not NOT_496(WX1520,WX2297);
not NOT_497(WX1522,WX1513);
not NOT_498(WX1523,WX1522);
not NOT_499(WX1526,WX2296);
not NOT_500(WX1530,WX2297);
not NOT_501(WX1534,WX2297);
not NOT_502(WX1536,WX1527);
not NOT_503(WX1537,WX1536);
not NOT_504(WX1540,WX2296);
not NOT_505(WX1544,WX2297);
not NOT_506(WX1548,WX2297);
not NOT_507(WX1550,WX1541);
not NOT_508(WX1551,WX1550);
not NOT_509(WX1554,WX2296);
not NOT_510(WX1558,WX2297);
not NOT_511(WX1562,WX2297);
not NOT_512(WX1564,WX1555);
not NOT_513(WX1565,WX1564);
not NOT_514(WX1568,WX2296);
not NOT_515(WX1572,WX2297);
not NOT_516(WX1576,WX2297);
not NOT_517(WX1578,WX1569);
not NOT_518(WX1579,WX1578);
not NOT_519(WX1582,WX2296);
not NOT_520(WX1586,WX2297);
not NOT_521(WX1590,WX2297);
not NOT_522(WX1592,WX1583);
not NOT_523(WX1593,WX1592);
not NOT_524(WX1596,WX2296);
not NOT_525(WX1600,WX2297);
not NOT_526(WX1604,WX2297);
not NOT_527(WX1606,WX1597);
not NOT_528(WX1607,WX1606);
not NOT_529(WX1610,WX2296);
not NOT_530(WX1614,WX2297);
not NOT_531(WX1618,WX2297);
not NOT_532(WX1620,WX1611);
not NOT_533(WX1621,WX1620);
not NOT_534(WX1624,WX2296);
not NOT_535(WX1628,WX2297);
not NOT_536(WX1632,WX2297);
not NOT_537(WX1634,WX1625);
not NOT_538(WX1635,WX1634);
not NOT_539(WX1638,WX2296);
not NOT_540(WX1642,WX2297);
not NOT_541(WX1646,WX2297);
not NOT_542(WX1648,WX1639);
not NOT_543(WX1649,WX1648);
not NOT_544(WX1652,WX2296);
not NOT_545(WX1656,WX2297);
not NOT_546(WX1660,WX2297);
not NOT_547(WX1662,WX1653);
not NOT_548(WX1663,WX1662);
not NOT_549(WX1666,WX2296);
not NOT_550(WX1670,WX2297);
not NOT_551(WX1674,WX2297);
not NOT_552(WX1676,WX1667);
not NOT_553(WX1677,WX1676);
not NOT_554(WX1680,WX2296);
not NOT_555(WX1684,WX2297);
not NOT_556(WX1688,WX2297);
not NOT_557(WX1690,WX1681);
not NOT_558(WX1691,WX1690);
not NOT_559(WX1694,WX2296);
not NOT_560(WX1698,WX2297);
not NOT_561(WX1702,WX2297);
not NOT_562(WX1704,WX1695);
not NOT_563(WX1705,WX1704);
not NOT_564(WX1708,WX2296);
not NOT_565(WX1712,WX2297);
not NOT_566(WX1716,WX2297);
not NOT_567(WX1718,WX1709);
not NOT_568(WX1719,WX1718);
not NOT_569(WX1722,WX2296);
not NOT_570(WX1726,WX2297);
not NOT_571(WX1730,WX2297);
not NOT_572(WX1732,WX1723);
not NOT_573(WX1733,WX1732);
not NOT_574(WX1736,WX2296);
not NOT_575(WX1740,WX2297);
not NOT_576(WX1744,WX2297);
not NOT_577(WX1746,WX1737);
not NOT_578(WX1747,WX1746);
not NOT_579(WX1750,WX2296);
not NOT_580(WX1754,WX2297);
not NOT_581(WX1758,WX2297);
not NOT_582(WX1760,WX1751);
not NOT_583(WX1761,WX1760);
not NOT_584(WX1764,WX2296);
not NOT_585(WX1768,WX2297);
not NOT_586(WX1772,WX2297);
not NOT_587(WX1774,WX1765);
not NOT_588(WX1775,WX1774);
not NOT_589(WX1776,WX1778);
not NOT_590(WX1841,WX2258);
not NOT_591(WX1842,WX2260);
not NOT_592(WX1843,WX2262);
not NOT_593(WX1844,WX2264);
not NOT_594(WX1845,WX2266);
not NOT_595(WX1846,WX2268);
not NOT_596(WX1847,WX2270);
not NOT_597(WX1848,WX2272);
not NOT_598(WX1849,WX2274);
not NOT_599(WX1850,WX2276);
not NOT_600(WX1851,WX2278);
not NOT_601(WX1852,WX2280);
not NOT_602(WX1853,WX2282);
not NOT_603(WX1854,WX2284);
not NOT_604(WX1855,WX2286);
not NOT_605(WX1856,WX2288);
not NOT_606(WX1857,WX2226);
not NOT_607(WX1858,WX2228);
not NOT_608(WX1859,WX2230);
not NOT_609(WX1860,WX2232);
not NOT_610(WX1861,WX2234);
not NOT_611(WX1862,WX2236);
not NOT_612(WX1863,WX2238);
not NOT_613(WX1864,WX2240);
not NOT_614(WX1865,WX2242);
not NOT_615(WX1866,WX2244);
not NOT_616(WX1867,WX2246);
not NOT_617(WX1868,WX2248);
not NOT_618(WX1869,WX2250);
not NOT_619(WX1870,WX2252);
not NOT_620(WX1871,WX2254);
not NOT_621(WX1872,WX2256);
not NOT_622(WX1873,WX1841);
not NOT_623(WX1874,WX1842);
not NOT_624(WX1875,WX1843);
not NOT_625(WX1876,WX1844);
not NOT_626(WX1877,WX1845);
not NOT_627(WX1878,WX1846);
not NOT_628(WX1879,WX1847);
not NOT_629(WX1880,WX1848);
not NOT_630(WX1881,WX1849);
not NOT_631(WX1882,WX1850);
not NOT_632(WX1883,WX1851);
not NOT_633(WX1884,WX1852);
not NOT_634(WX1885,WX1853);
not NOT_635(WX1886,WX1854);
not NOT_636(WX1887,WX1855);
not NOT_637(WX1888,WX1856);
not NOT_638(WX1889,WX1857);
not NOT_639(WX1890,WX1858);
not NOT_640(WX1891,WX1859);
not NOT_641(WX1892,WX1860);
not NOT_642(WX1893,WX1861);
not NOT_643(WX1894,WX1862);
not NOT_644(WX1895,WX1863);
not NOT_645(WX1896,WX1864);
not NOT_646(WX1897,WX1865);
not NOT_647(WX1898,WX1866);
not NOT_648(WX1899,WX1867);
not NOT_649(WX1900,WX1868);
not NOT_650(WX1901,WX1869);
not NOT_651(WX1902,WX1870);
not NOT_652(WX1903,WX1871);
not NOT_653(WX1904,WX1872);
not NOT_654(WX1905,WX2130);
not NOT_655(WX1906,WX2132);
not NOT_656(WX1907,WX2134);
not NOT_657(WX1908,WX2136);
not NOT_658(WX1909,WX2138);
not NOT_659(WX1910,WX2140);
not NOT_660(WX1911,WX2142);
not NOT_661(WX1912,WX2144);
not NOT_662(WX1913,WX2146);
not NOT_663(WX1914,WX2148);
not NOT_664(WX1915,WX2150);
not NOT_665(WX1916,WX2152);
not NOT_666(WX1917,WX2154);
not NOT_667(WX1918,WX2156);
not NOT_668(WX1919,WX2158);
not NOT_669(WX1920,WX2160);
not NOT_670(WX1921,WX2162);
not NOT_671(WX1922,WX2164);
not NOT_672(WX1923,WX2166);
not NOT_673(WX1924,WX2168);
not NOT_674(WX1925,WX2170);
not NOT_675(WX1926,WX2172);
not NOT_676(WX1927,WX2174);
not NOT_677(WX1928,WX2176);
not NOT_678(WX1929,WX2178);
not NOT_679(WX1930,WX2180);
not NOT_680(WX1931,WX2182);
not NOT_681(WX1932,WX2184);
not NOT_682(WX1933,WX2186);
not NOT_683(WX1934,WX2188);
not NOT_684(WX1935,WX2190);
not NOT_685(WX1936,WX2192);
not NOT_686(WX2225,WX2209);
not NOT_687(WX2226,WX2225);
not NOT_688(WX2227,WX2210);
not NOT_689(WX2228,WX2227);
not NOT_690(WX2229,WX2211);
not NOT_691(WX2230,WX2229);
not NOT_692(WX2231,WX2212);
not NOT_693(WX2232,WX2231);
not NOT_694(WX2233,WX2213);
not NOT_695(WX2234,WX2233);
not NOT_696(WX2235,WX2214);
not NOT_697(WX2236,WX2235);
not NOT_698(WX2237,WX2215);
not NOT_699(WX2238,WX2237);
not NOT_700(WX2239,WX2216);
not NOT_701(WX2240,WX2239);
not NOT_702(WX2241,WX2217);
not NOT_703(WX2242,WX2241);
not NOT_704(WX2243,WX2218);
not NOT_705(WX2244,WX2243);
not NOT_706(WX2245,WX2219);
not NOT_707(WX2246,WX2245);
not NOT_708(WX2247,WX2220);
not NOT_709(WX2248,WX2247);
not NOT_710(WX2249,WX2221);
not NOT_711(WX2250,WX2249);
not NOT_712(WX2251,WX2222);
not NOT_713(WX2252,WX2251);
not NOT_714(WX2253,WX2223);
not NOT_715(WX2254,WX2253);
not NOT_716(WX2255,WX2224);
not NOT_717(WX2256,WX2255);
not NOT_718(WX2257,WX2193);
not NOT_719(WX2258,WX2257);
not NOT_720(WX2259,WX2194);
not NOT_721(WX2260,WX2259);
not NOT_722(WX2261,WX2195);
not NOT_723(WX2262,WX2261);
not NOT_724(WX2263,WX2196);
not NOT_725(WX2264,WX2263);
not NOT_726(WX2265,WX2197);
not NOT_727(WX2266,WX2265);
not NOT_728(WX2267,WX2198);
not NOT_729(WX2268,WX2267);
not NOT_730(WX2269,WX2199);
not NOT_731(WX2270,WX2269);
not NOT_732(WX2271,WX2200);
not NOT_733(WX2272,WX2271);
not NOT_734(WX2273,WX2201);
not NOT_735(WX2274,WX2273);
not NOT_736(WX2275,WX2202);
not NOT_737(WX2276,WX2275);
not NOT_738(WX2277,WX2203);
not NOT_739(WX2278,WX2277);
not NOT_740(WX2279,WX2204);
not NOT_741(WX2280,WX2279);
not NOT_742(WX2281,WX2205);
not NOT_743(WX2282,WX2281);
not NOT_744(WX2283,WX2206);
not NOT_745(WX2284,WX2283);
not NOT_746(WX2285,WX2207);
not NOT_747(WX2286,WX2285);
not NOT_748(WX2287,WX2208);
not NOT_749(WX2288,WX2287);
not NOT_750(WX2289,TM0);
not NOT_751(WX2290,TM0);
not NOT_752(WX2291,TM0);
not NOT_753(WX2292,TM1);
not NOT_754(WX2293,TM1);
not NOT_755(WX2294,WX2293);
not NOT_756(WX2295,WX2291);
not NOT_757(WX2296,WX2292);
not NOT_758(WX2297,WX2290);
not NOT_759(WX2298,WX2289);
not NOT_760(WX2302,WX2298);
not NOT_761(WX2304,WX2303);
not NOT_762(WX2305,WX2304);
not NOT_763(WX2309,WX2298);
not NOT_764(WX2311,WX2310);
not NOT_765(WX2312,WX2311);
not NOT_766(WX2316,WX2298);
not NOT_767(WX2318,WX2317);
not NOT_768(WX2319,WX2318);
not NOT_769(WX2323,WX2298);
not NOT_770(WX2325,WX2324);
not NOT_771(WX2326,WX2325);
not NOT_772(WX2330,WX2298);
not NOT_773(WX2332,WX2331);
not NOT_774(WX2333,WX2332);
not NOT_775(WX2337,WX2298);
not NOT_776(WX2339,WX2338);
not NOT_777(WX2340,WX2339);
not NOT_778(WX2344,WX2298);
not NOT_779(WX2346,WX2345);
not NOT_780(WX2347,WX2346);
not NOT_781(WX2351,WX2298);
not NOT_782(WX2353,WX2352);
not NOT_783(WX2354,WX2353);
not NOT_784(WX2358,WX2298);
not NOT_785(WX2360,WX2359);
not NOT_786(WX2361,WX2360);
not NOT_787(WX2365,WX2298);
not NOT_788(WX2367,WX2366);
not NOT_789(WX2368,WX2367);
not NOT_790(WX2372,WX2298);
not NOT_791(WX2374,WX2373);
not NOT_792(WX2375,WX2374);
not NOT_793(WX2379,WX2298);
not NOT_794(WX2381,WX2380);
not NOT_795(WX2382,WX2381);
not NOT_796(WX2386,WX2298);
not NOT_797(WX2388,WX2387);
not NOT_798(WX2389,WX2388);
not NOT_799(WX2393,WX2298);
not NOT_800(WX2395,WX2394);
not NOT_801(WX2396,WX2395);
not NOT_802(WX2400,WX2298);
not NOT_803(WX2402,WX2401);
not NOT_804(WX2403,WX2402);
not NOT_805(WX2407,WX2298);
not NOT_806(WX2409,WX2408);
not NOT_807(WX2410,WX2409);
not NOT_808(WX2414,WX2298);
not NOT_809(WX2416,WX2415);
not NOT_810(WX2417,WX2416);
not NOT_811(WX2421,WX2298);
not NOT_812(WX2423,WX2422);
not NOT_813(WX2424,WX2423);
not NOT_814(WX2428,WX2298);
not NOT_815(WX2430,WX2429);
not NOT_816(WX2431,WX2430);
not NOT_817(WX2435,WX2298);
not NOT_818(WX2437,WX2436);
not NOT_819(WX2438,WX2437);
not NOT_820(WX2442,WX2298);
not NOT_821(WX2444,WX2443);
not NOT_822(WX2445,WX2444);
not NOT_823(WX2449,WX2298);
not NOT_824(WX2451,WX2450);
not NOT_825(WX2452,WX2451);
not NOT_826(WX2456,WX2298);
not NOT_827(WX2458,WX2457);
not NOT_828(WX2459,WX2458);
not NOT_829(WX2463,WX2298);
not NOT_830(WX2465,WX2464);
not NOT_831(WX2466,WX2465);
not NOT_832(WX2470,WX2298);
not NOT_833(WX2472,WX2471);
not NOT_834(WX2473,WX2472);
not NOT_835(WX2477,WX2298);
not NOT_836(WX2479,WX2478);
not NOT_837(WX2480,WX2479);
not NOT_838(WX2484,WX2298);
not NOT_839(WX2486,WX2485);
not NOT_840(WX2487,WX2486);
not NOT_841(WX2491,WX2298);
not NOT_842(WX2493,WX2492);
not NOT_843(WX2494,WX2493);
not NOT_844(WX2498,WX2298);
not NOT_845(WX2500,WX2499);
not NOT_846(WX2501,WX2500);
not NOT_847(WX2505,WX2298);
not NOT_848(WX2507,WX2506);
not NOT_849(WX2508,WX2507);
not NOT_850(WX2512,WX2298);
not NOT_851(WX2514,WX2513);
not NOT_852(WX2515,WX2514);
not NOT_853(WX2519,WX2298);
not NOT_854(WX2521,WX2520);
not NOT_855(WX2522,WX2521);
not NOT_856(WX2523,RESET);
not NOT_857(WX2556,WX2523);
not NOT_858(WX2623,WX3589);
not NOT_859(WX2627,WX3590);
not NOT_860(WX2631,WX3590);
not NOT_861(WX2633,WX2624);
not NOT_862(WX2634,WX2633);
not NOT_863(WX2637,WX3589);
not NOT_864(WX2641,WX3590);
not NOT_865(WX2645,WX3590);
not NOT_866(WX2647,WX2638);
not NOT_867(WX2648,WX2647);
not NOT_868(WX2651,WX3589);
not NOT_869(WX2655,WX3590);
not NOT_870(WX2659,WX3590);
not NOT_871(WX2661,WX2652);
not NOT_872(WX2662,WX2661);
not NOT_873(WX2665,WX3589);
not NOT_874(WX2669,WX3590);
not NOT_875(WX2673,WX3590);
not NOT_876(WX2675,WX2666);
not NOT_877(WX2676,WX2675);
not NOT_878(WX2679,WX3589);
not NOT_879(WX2683,WX3590);
not NOT_880(WX2687,WX3590);
not NOT_881(WX2689,WX2680);
not NOT_882(WX2690,WX2689);
not NOT_883(WX2693,WX3589);
not NOT_884(WX2697,WX3590);
not NOT_885(WX2701,WX3590);
not NOT_886(WX2703,WX2694);
not NOT_887(WX2704,WX2703);
not NOT_888(WX2707,WX3589);
not NOT_889(WX2711,WX3590);
not NOT_890(WX2715,WX3590);
not NOT_891(WX2717,WX2708);
not NOT_892(WX2718,WX2717);
not NOT_893(WX2721,WX3589);
not NOT_894(WX2725,WX3590);
not NOT_895(WX2729,WX3590);
not NOT_896(WX2731,WX2722);
not NOT_897(WX2732,WX2731);
not NOT_898(WX2735,WX3589);
not NOT_899(WX2739,WX3590);
not NOT_900(WX2743,WX3590);
not NOT_901(WX2745,WX2736);
not NOT_902(WX2746,WX2745);
not NOT_903(WX2749,WX3589);
not NOT_904(WX2753,WX3590);
not NOT_905(WX2757,WX3590);
not NOT_906(WX2759,WX2750);
not NOT_907(WX2760,WX2759);
not NOT_908(WX2763,WX3589);
not NOT_909(WX2767,WX3590);
not NOT_910(WX2771,WX3590);
not NOT_911(WX2773,WX2764);
not NOT_912(WX2774,WX2773);
not NOT_913(WX2777,WX3589);
not NOT_914(WX2781,WX3590);
not NOT_915(WX2785,WX3590);
not NOT_916(WX2787,WX2778);
not NOT_917(WX2788,WX2787);
not NOT_918(WX2791,WX3589);
not NOT_919(WX2795,WX3590);
not NOT_920(WX2799,WX3590);
not NOT_921(WX2801,WX2792);
not NOT_922(WX2802,WX2801);
not NOT_923(WX2805,WX3589);
not NOT_924(WX2809,WX3590);
not NOT_925(WX2813,WX3590);
not NOT_926(WX2815,WX2806);
not NOT_927(WX2816,WX2815);
not NOT_928(WX2819,WX3589);
not NOT_929(WX2823,WX3590);
not NOT_930(WX2827,WX3590);
not NOT_931(WX2829,WX2820);
not NOT_932(WX2830,WX2829);
not NOT_933(WX2833,WX3589);
not NOT_934(WX2837,WX3590);
not NOT_935(WX2841,WX3590);
not NOT_936(WX2843,WX2834);
not NOT_937(WX2844,WX2843);
not NOT_938(WX2847,WX3589);
not NOT_939(WX2851,WX3590);
not NOT_940(WX2855,WX3590);
not NOT_941(WX2857,WX2848);
not NOT_942(WX2858,WX2857);
not NOT_943(WX2861,WX3589);
not NOT_944(WX2865,WX3590);
not NOT_945(WX2869,WX3590);
not NOT_946(WX2871,WX2862);
not NOT_947(WX2872,WX2871);
not NOT_948(WX2875,WX3589);
not NOT_949(WX2879,WX3590);
not NOT_950(WX2883,WX3590);
not NOT_951(WX2885,WX2876);
not NOT_952(WX2886,WX2885);
not NOT_953(WX2889,WX3589);
not NOT_954(WX2893,WX3590);
not NOT_955(WX2897,WX3590);
not NOT_956(WX2899,WX2890);
not NOT_957(WX2900,WX2899);
not NOT_958(WX2903,WX3589);
not NOT_959(WX2907,WX3590);
not NOT_960(WX2911,WX3590);
not NOT_961(WX2913,WX2904);
not NOT_962(WX2914,WX2913);
not NOT_963(WX2917,WX3589);
not NOT_964(WX2921,WX3590);
not NOT_965(WX2925,WX3590);
not NOT_966(WX2927,WX2918);
not NOT_967(WX2928,WX2927);
not NOT_968(WX2931,WX3589);
not NOT_969(WX2935,WX3590);
not NOT_970(WX2939,WX3590);
not NOT_971(WX2941,WX2932);
not NOT_972(WX2942,WX2941);
not NOT_973(WX2945,WX3589);
not NOT_974(WX2949,WX3590);
not NOT_975(WX2953,WX3590);
not NOT_976(WX2955,WX2946);
not NOT_977(WX2956,WX2955);
not NOT_978(WX2959,WX3589);
not NOT_979(WX2963,WX3590);
not NOT_980(WX2967,WX3590);
not NOT_981(WX2969,WX2960);
not NOT_982(WX2970,WX2969);
not NOT_983(WX2973,WX3589);
not NOT_984(WX2977,WX3590);
not NOT_985(WX2981,WX3590);
not NOT_986(WX2983,WX2974);
not NOT_987(WX2984,WX2983);
not NOT_988(WX2987,WX3589);
not NOT_989(WX2991,WX3590);
not NOT_990(WX2995,WX3590);
not NOT_991(WX2997,WX2988);
not NOT_992(WX2998,WX2997);
not NOT_993(WX3001,WX3589);
not NOT_994(WX3005,WX3590);
not NOT_995(WX3009,WX3590);
not NOT_996(WX3011,WX3002);
not NOT_997(WX3012,WX3011);
not NOT_998(WX3015,WX3589);
not NOT_999(WX3019,WX3590);
not NOT_1000(WX3023,WX3590);
not NOT_1001(WX3025,WX3016);
not NOT_1002(WX3026,WX3025);
not NOT_1003(WX3029,WX3589);
not NOT_1004(WX3033,WX3590);
not NOT_1005(WX3037,WX3590);
not NOT_1006(WX3039,WX3030);
not NOT_1007(WX3040,WX3039);
not NOT_1008(WX3043,WX3589);
not NOT_1009(WX3047,WX3590);
not NOT_1010(WX3051,WX3590);
not NOT_1011(WX3053,WX3044);
not NOT_1012(WX3054,WX3053);
not NOT_1013(WX3057,WX3589);
not NOT_1014(WX3061,WX3590);
not NOT_1015(WX3065,WX3590);
not NOT_1016(WX3067,WX3058);
not NOT_1017(WX3068,WX3067);
not NOT_1018(WX3069,WX3071);
not NOT_1019(WX3134,WX3551);
not NOT_1020(WX3135,WX3553);
not NOT_1021(WX3136,WX3555);
not NOT_1022(WX3137,WX3557);
not NOT_1023(WX3138,WX3559);
not NOT_1024(WX3139,WX3561);
not NOT_1025(WX3140,WX3563);
not NOT_1026(WX3141,WX3565);
not NOT_1027(WX3142,WX3567);
not NOT_1028(WX3143,WX3569);
not NOT_1029(WX3144,WX3571);
not NOT_1030(WX3145,WX3573);
not NOT_1031(WX3146,WX3575);
not NOT_1032(WX3147,WX3577);
not NOT_1033(WX3148,WX3579);
not NOT_1034(WX3149,WX3581);
not NOT_1035(WX3150,WX3519);
not NOT_1036(WX3151,WX3521);
not NOT_1037(WX3152,WX3523);
not NOT_1038(WX3153,WX3525);
not NOT_1039(WX3154,WX3527);
not NOT_1040(WX3155,WX3529);
not NOT_1041(WX3156,WX3531);
not NOT_1042(WX3157,WX3533);
not NOT_1043(WX3158,WX3535);
not NOT_1044(WX3159,WX3537);
not NOT_1045(WX3160,WX3539);
not NOT_1046(WX3161,WX3541);
not NOT_1047(WX3162,WX3543);
not NOT_1048(WX3163,WX3545);
not NOT_1049(WX3164,WX3547);
not NOT_1050(WX3165,WX3549);
not NOT_1051(WX3166,WX3134);
not NOT_1052(WX3167,WX3135);
not NOT_1053(WX3168,WX3136);
not NOT_1054(WX3169,WX3137);
not NOT_1055(WX3170,WX3138);
not NOT_1056(WX3171,WX3139);
not NOT_1057(WX3172,WX3140);
not NOT_1058(WX3173,WX3141);
not NOT_1059(WX3174,WX3142);
not NOT_1060(WX3175,WX3143);
not NOT_1061(WX3176,WX3144);
not NOT_1062(WX3177,WX3145);
not NOT_1063(WX3178,WX3146);
not NOT_1064(WX3179,WX3147);
not NOT_1065(WX3180,WX3148);
not NOT_1066(WX3181,WX3149);
not NOT_1067(WX3182,WX3150);
not NOT_1068(WX3183,WX3151);
not NOT_1069(WX3184,WX3152);
not NOT_1070(WX3185,WX3153);
not NOT_1071(WX3186,WX3154);
not NOT_1072(WX3187,WX3155);
not NOT_1073(WX3188,WX3156);
not NOT_1074(WX3189,WX3157);
not NOT_1075(WX3190,WX3158);
not NOT_1076(WX3191,WX3159);
not NOT_1077(WX3192,WX3160);
not NOT_1078(WX3193,WX3161);
not NOT_1079(WX3194,WX3162);
not NOT_1080(WX3195,WX3163);
not NOT_1081(WX3196,WX3164);
not NOT_1082(WX3197,WX3165);
not NOT_1083(WX3198,WX3423);
not NOT_1084(WX3199,WX3425);
not NOT_1085(WX3200,WX3427);
not NOT_1086(WX3201,WX3429);
not NOT_1087(WX3202,WX3431);
not NOT_1088(WX3203,WX3433);
not NOT_1089(WX3204,WX3435);
not NOT_1090(WX3205,WX3437);
not NOT_1091(WX3206,WX3439);
not NOT_1092(WX3207,WX3441);
not NOT_1093(WX3208,WX3443);
not NOT_1094(WX3209,WX3445);
not NOT_1095(WX3210,WX3447);
not NOT_1096(WX3211,WX3449);
not NOT_1097(WX3212,WX3451);
not NOT_1098(WX3213,WX3453);
not NOT_1099(WX3214,WX3455);
not NOT_1100(WX3215,WX3457);
not NOT_1101(WX3216,WX3459);
not NOT_1102(WX3217,WX3461);
not NOT_1103(WX3218,WX3463);
not NOT_1104(WX3219,WX3465);
not NOT_1105(WX3220,WX3467);
not NOT_1106(WX3221,WX3469);
not NOT_1107(WX3222,WX3471);
not NOT_1108(WX3223,WX3473);
not NOT_1109(WX3224,WX3475);
not NOT_1110(WX3225,WX3477);
not NOT_1111(WX3226,WX3479);
not NOT_1112(WX3227,WX3481);
not NOT_1113(WX3228,WX3483);
not NOT_1114(WX3229,WX3485);
not NOT_1115(WX3518,WX3502);
not NOT_1116(WX3519,WX3518);
not NOT_1117(WX3520,WX3503);
not NOT_1118(WX3521,WX3520);
not NOT_1119(WX3522,WX3504);
not NOT_1120(WX3523,WX3522);
not NOT_1121(WX3524,WX3505);
not NOT_1122(WX3525,WX3524);
not NOT_1123(WX3526,WX3506);
not NOT_1124(WX3527,WX3526);
not NOT_1125(WX3528,WX3507);
not NOT_1126(WX3529,WX3528);
not NOT_1127(WX3530,WX3508);
not NOT_1128(WX3531,WX3530);
not NOT_1129(WX3532,WX3509);
not NOT_1130(WX3533,WX3532);
not NOT_1131(WX3534,WX3510);
not NOT_1132(WX3535,WX3534);
not NOT_1133(WX3536,WX3511);
not NOT_1134(WX3537,WX3536);
not NOT_1135(WX3538,WX3512);
not NOT_1136(WX3539,WX3538);
not NOT_1137(WX3540,WX3513);
not NOT_1138(WX3541,WX3540);
not NOT_1139(WX3542,WX3514);
not NOT_1140(WX3543,WX3542);
not NOT_1141(WX3544,WX3515);
not NOT_1142(WX3545,WX3544);
not NOT_1143(WX3546,WX3516);
not NOT_1144(WX3547,WX3546);
not NOT_1145(WX3548,WX3517);
not NOT_1146(WX3549,WX3548);
not NOT_1147(WX3550,WX3486);
not NOT_1148(WX3551,WX3550);
not NOT_1149(WX3552,WX3487);
not NOT_1150(WX3553,WX3552);
not NOT_1151(WX3554,WX3488);
not NOT_1152(WX3555,WX3554);
not NOT_1153(WX3556,WX3489);
not NOT_1154(WX3557,WX3556);
not NOT_1155(WX3558,WX3490);
not NOT_1156(WX3559,WX3558);
not NOT_1157(WX3560,WX3491);
not NOT_1158(WX3561,WX3560);
not NOT_1159(WX3562,WX3492);
not NOT_1160(WX3563,WX3562);
not NOT_1161(WX3564,WX3493);
not NOT_1162(WX3565,WX3564);
not NOT_1163(WX3566,WX3494);
not NOT_1164(WX3567,WX3566);
not NOT_1165(WX3568,WX3495);
not NOT_1166(WX3569,WX3568);
not NOT_1167(WX3570,WX3496);
not NOT_1168(WX3571,WX3570);
not NOT_1169(WX3572,WX3497);
not NOT_1170(WX3573,WX3572);
not NOT_1171(WX3574,WX3498);
not NOT_1172(WX3575,WX3574);
not NOT_1173(WX3576,WX3499);
not NOT_1174(WX3577,WX3576);
not NOT_1175(WX3578,WX3500);
not NOT_1176(WX3579,WX3578);
not NOT_1177(WX3580,WX3501);
not NOT_1178(WX3581,WX3580);
not NOT_1179(WX3582,TM0);
not NOT_1180(WX3583,TM0);
not NOT_1181(WX3584,TM0);
not NOT_1182(WX3585,TM1);
not NOT_1183(WX3586,TM1);
not NOT_1184(WX3587,WX3586);
not NOT_1185(WX3588,WX3584);
not NOT_1186(WX3589,WX3585);
not NOT_1187(WX3590,WX3583);
not NOT_1188(WX3591,WX3582);
not NOT_1189(WX3595,WX3591);
not NOT_1190(WX3597,WX3596);
not NOT_1191(WX3598,WX3597);
not NOT_1192(WX3602,WX3591);
not NOT_1193(WX3604,WX3603);
not NOT_1194(WX3605,WX3604);
not NOT_1195(WX3609,WX3591);
not NOT_1196(WX3611,WX3610);
not NOT_1197(WX3612,WX3611);
not NOT_1198(WX3616,WX3591);
not NOT_1199(WX3618,WX3617);
not NOT_1200(WX3619,WX3618);
not NOT_1201(WX3623,WX3591);
not NOT_1202(WX3625,WX3624);
not NOT_1203(WX3626,WX3625);
not NOT_1204(WX3630,WX3591);
not NOT_1205(WX3632,WX3631);
not NOT_1206(WX3633,WX3632);
not NOT_1207(WX3637,WX3591);
not NOT_1208(WX3639,WX3638);
not NOT_1209(WX3640,WX3639);
not NOT_1210(WX3644,WX3591);
not NOT_1211(WX3646,WX3645);
not NOT_1212(WX3647,WX3646);
not NOT_1213(WX3651,WX3591);
not NOT_1214(WX3653,WX3652);
not NOT_1215(WX3654,WX3653);
not NOT_1216(WX3658,WX3591);
not NOT_1217(WX3660,WX3659);
not NOT_1218(WX3661,WX3660);
not NOT_1219(WX3665,WX3591);
not NOT_1220(WX3667,WX3666);
not NOT_1221(WX3668,WX3667);
not NOT_1222(WX3672,WX3591);
not NOT_1223(WX3674,WX3673);
not NOT_1224(WX3675,WX3674);
not NOT_1225(WX3679,WX3591);
not NOT_1226(WX3681,WX3680);
not NOT_1227(WX3682,WX3681);
not NOT_1228(WX3686,WX3591);
not NOT_1229(WX3688,WX3687);
not NOT_1230(WX3689,WX3688);
not NOT_1231(WX3693,WX3591);
not NOT_1232(WX3695,WX3694);
not NOT_1233(WX3696,WX3695);
not NOT_1234(WX3700,WX3591);
not NOT_1235(WX3702,WX3701);
not NOT_1236(WX3703,WX3702);
not NOT_1237(WX3707,WX3591);
not NOT_1238(WX3709,WX3708);
not NOT_1239(WX3710,WX3709);
not NOT_1240(WX3714,WX3591);
not NOT_1241(WX3716,WX3715);
not NOT_1242(WX3717,WX3716);
not NOT_1243(WX3721,WX3591);
not NOT_1244(WX3723,WX3722);
not NOT_1245(WX3724,WX3723);
not NOT_1246(WX3728,WX3591);
not NOT_1247(WX3730,WX3729);
not NOT_1248(WX3731,WX3730);
not NOT_1249(WX3735,WX3591);
not NOT_1250(WX3737,WX3736);
not NOT_1251(WX3738,WX3737);
not NOT_1252(WX3742,WX3591);
not NOT_1253(WX3744,WX3743);
not NOT_1254(WX3745,WX3744);
not NOT_1255(WX3749,WX3591);
not NOT_1256(WX3751,WX3750);
not NOT_1257(WX3752,WX3751);
not NOT_1258(WX3756,WX3591);
not NOT_1259(WX3758,WX3757);
not NOT_1260(WX3759,WX3758);
not NOT_1261(WX3763,WX3591);
not NOT_1262(WX3765,WX3764);
not NOT_1263(WX3766,WX3765);
not NOT_1264(WX3770,WX3591);
not NOT_1265(WX3772,WX3771);
not NOT_1266(WX3773,WX3772);
not NOT_1267(WX3777,WX3591);
not NOT_1268(WX3779,WX3778);
not NOT_1269(WX3780,WX3779);
not NOT_1270(WX3784,WX3591);
not NOT_1271(WX3786,WX3785);
not NOT_1272(WX3787,WX3786);
not NOT_1273(WX3791,WX3591);
not NOT_1274(WX3793,WX3792);
not NOT_1275(WX3794,WX3793);
not NOT_1276(WX3798,WX3591);
not NOT_1277(WX3800,WX3799);
not NOT_1278(WX3801,WX3800);
not NOT_1279(WX3805,WX3591);
not NOT_1280(WX3807,WX3806);
not NOT_1281(WX3808,WX3807);
not NOT_1282(WX3812,WX3591);
not NOT_1283(WX3814,WX3813);
not NOT_1284(WX3815,WX3814);
not NOT_1285(WX3816,RESET);
not NOT_1286(WX3849,WX3816);
not NOT_1287(WX3916,WX4882);
not NOT_1288(WX3920,WX4883);
not NOT_1289(WX3924,WX4883);
not NOT_1290(WX3926,WX3917);
not NOT_1291(WX3927,WX3926);
not NOT_1292(WX3930,WX4882);
not NOT_1293(WX3934,WX4883);
not NOT_1294(WX3938,WX4883);
not NOT_1295(WX3940,WX3931);
not NOT_1296(WX3941,WX3940);
not NOT_1297(WX3944,WX4882);
not NOT_1298(WX3948,WX4883);
not NOT_1299(WX3952,WX4883);
not NOT_1300(WX3954,WX3945);
not NOT_1301(WX3955,WX3954);
not NOT_1302(WX3958,WX4882);
not NOT_1303(WX3962,WX4883);
not NOT_1304(WX3966,WX4883);
not NOT_1305(WX3968,WX3959);
not NOT_1306(WX3969,WX3968);
not NOT_1307(WX3972,WX4882);
not NOT_1308(WX3976,WX4883);
not NOT_1309(WX3980,WX4883);
not NOT_1310(WX3982,WX3973);
not NOT_1311(WX3983,WX3982);
not NOT_1312(WX3986,WX4882);
not NOT_1313(WX3990,WX4883);
not NOT_1314(WX3994,WX4883);
not NOT_1315(WX3996,WX3987);
not NOT_1316(WX3997,WX3996);
not NOT_1317(WX4000,WX4882);
not NOT_1318(WX4004,WX4883);
not NOT_1319(WX4008,WX4883);
not NOT_1320(WX4010,WX4001);
not NOT_1321(WX4011,WX4010);
not NOT_1322(WX4014,WX4882);
not NOT_1323(WX4018,WX4883);
not NOT_1324(WX4022,WX4883);
not NOT_1325(WX4024,WX4015);
not NOT_1326(WX4025,WX4024);
not NOT_1327(WX4028,WX4882);
not NOT_1328(WX4032,WX4883);
not NOT_1329(WX4036,WX4883);
not NOT_1330(WX4038,WX4029);
not NOT_1331(WX4039,WX4038);
not NOT_1332(WX4042,WX4882);
not NOT_1333(WX4046,WX4883);
not NOT_1334(WX4050,WX4883);
not NOT_1335(WX4052,WX4043);
not NOT_1336(WX4053,WX4052);
not NOT_1337(WX4056,WX4882);
not NOT_1338(WX4060,WX4883);
not NOT_1339(WX4064,WX4883);
not NOT_1340(WX4066,WX4057);
not NOT_1341(WX4067,WX4066);
not NOT_1342(WX4070,WX4882);
not NOT_1343(WX4074,WX4883);
not NOT_1344(WX4078,WX4883);
not NOT_1345(WX4080,WX4071);
not NOT_1346(WX4081,WX4080);
not NOT_1347(WX4084,WX4882);
not NOT_1348(WX4088,WX4883);
not NOT_1349(WX4092,WX4883);
not NOT_1350(WX4094,WX4085);
not NOT_1351(WX4095,WX4094);
not NOT_1352(WX4098,WX4882);
not NOT_1353(WX4102,WX4883);
not NOT_1354(WX4106,WX4883);
not NOT_1355(WX4108,WX4099);
not NOT_1356(WX4109,WX4108);
not NOT_1357(WX4112,WX4882);
not NOT_1358(WX4116,WX4883);
not NOT_1359(WX4120,WX4883);
not NOT_1360(WX4122,WX4113);
not NOT_1361(WX4123,WX4122);
not NOT_1362(WX4126,WX4882);
not NOT_1363(WX4130,WX4883);
not NOT_1364(WX4134,WX4883);
not NOT_1365(WX4136,WX4127);
not NOT_1366(WX4137,WX4136);
not NOT_1367(WX4140,WX4882);
not NOT_1368(WX4144,WX4883);
not NOT_1369(WX4148,WX4883);
not NOT_1370(WX4150,WX4141);
not NOT_1371(WX4151,WX4150);
not NOT_1372(WX4154,WX4882);
not NOT_1373(WX4158,WX4883);
not NOT_1374(WX4162,WX4883);
not NOT_1375(WX4164,WX4155);
not NOT_1376(WX4165,WX4164);
not NOT_1377(WX4168,WX4882);
not NOT_1378(WX4172,WX4883);
not NOT_1379(WX4176,WX4883);
not NOT_1380(WX4178,WX4169);
not NOT_1381(WX4179,WX4178);
not NOT_1382(WX4182,WX4882);
not NOT_1383(WX4186,WX4883);
not NOT_1384(WX4190,WX4883);
not NOT_1385(WX4192,WX4183);
not NOT_1386(WX4193,WX4192);
not NOT_1387(WX4196,WX4882);
not NOT_1388(WX4200,WX4883);
not NOT_1389(WX4204,WX4883);
not NOT_1390(WX4206,WX4197);
not NOT_1391(WX4207,WX4206);
not NOT_1392(WX4210,WX4882);
not NOT_1393(WX4214,WX4883);
not NOT_1394(WX4218,WX4883);
not NOT_1395(WX4220,WX4211);
not NOT_1396(WX4221,WX4220);
not NOT_1397(WX4224,WX4882);
not NOT_1398(WX4228,WX4883);
not NOT_1399(WX4232,WX4883);
not NOT_1400(WX4234,WX4225);
not NOT_1401(WX4235,WX4234);
not NOT_1402(WX4238,WX4882);
not NOT_1403(WX4242,WX4883);
not NOT_1404(WX4246,WX4883);
not NOT_1405(WX4248,WX4239);
not NOT_1406(WX4249,WX4248);
not NOT_1407(WX4252,WX4882);
not NOT_1408(WX4256,WX4883);
not NOT_1409(WX4260,WX4883);
not NOT_1410(WX4262,WX4253);
not NOT_1411(WX4263,WX4262);
not NOT_1412(WX4266,WX4882);
not NOT_1413(WX4270,WX4883);
not NOT_1414(WX4274,WX4883);
not NOT_1415(WX4276,WX4267);
not NOT_1416(WX4277,WX4276);
not NOT_1417(WX4280,WX4882);
not NOT_1418(WX4284,WX4883);
not NOT_1419(WX4288,WX4883);
not NOT_1420(WX4290,WX4281);
not NOT_1421(WX4291,WX4290);
not NOT_1422(WX4294,WX4882);
not NOT_1423(WX4298,WX4883);
not NOT_1424(WX4302,WX4883);
not NOT_1425(WX4304,WX4295);
not NOT_1426(WX4305,WX4304);
not NOT_1427(WX4308,WX4882);
not NOT_1428(WX4312,WX4883);
not NOT_1429(WX4316,WX4883);
not NOT_1430(WX4318,WX4309);
not NOT_1431(WX4319,WX4318);
not NOT_1432(WX4322,WX4882);
not NOT_1433(WX4326,WX4883);
not NOT_1434(WX4330,WX4883);
not NOT_1435(WX4332,WX4323);
not NOT_1436(WX4333,WX4332);
not NOT_1437(WX4336,WX4882);
not NOT_1438(WX4340,WX4883);
not NOT_1439(WX4344,WX4883);
not NOT_1440(WX4346,WX4337);
not NOT_1441(WX4347,WX4346);
not NOT_1442(WX4350,WX4882);
not NOT_1443(WX4354,WX4883);
not NOT_1444(WX4358,WX4883);
not NOT_1445(WX4360,WX4351);
not NOT_1446(WX4361,WX4360);
not NOT_1447(WX4362,WX4364);
not NOT_1448(WX4427,WX4844);
not NOT_1449(WX4428,WX4846);
not NOT_1450(WX4429,WX4848);
not NOT_1451(WX4430,WX4850);
not NOT_1452(WX4431,WX4852);
not NOT_1453(WX4432,WX4854);
not NOT_1454(WX4433,WX4856);
not NOT_1455(WX4434,WX4858);
not NOT_1456(WX4435,WX4860);
not NOT_1457(WX4436,WX4862);
not NOT_1458(WX4437,WX4864);
not NOT_1459(WX4438,WX4866);
not NOT_1460(WX4439,WX4868);
not NOT_1461(WX4440,WX4870);
not NOT_1462(WX4441,WX4872);
not NOT_1463(WX4442,WX4874);
not NOT_1464(WX4443,WX4812);
not NOT_1465(WX4444,WX4814);
not NOT_1466(WX4445,WX4816);
not NOT_1467(WX4446,WX4818);
not NOT_1468(WX4447,WX4820);
not NOT_1469(WX4448,WX4822);
not NOT_1470(WX4449,WX4824);
not NOT_1471(WX4450,WX4826);
not NOT_1472(WX4451,WX4828);
not NOT_1473(WX4452,WX4830);
not NOT_1474(WX4453,WX4832);
not NOT_1475(WX4454,WX4834);
not NOT_1476(WX4455,WX4836);
not NOT_1477(WX4456,WX4838);
not NOT_1478(WX4457,WX4840);
not NOT_1479(WX4458,WX4842);
not NOT_1480(WX4459,WX4427);
not NOT_1481(WX4460,WX4428);
not NOT_1482(WX4461,WX4429);
not NOT_1483(WX4462,WX4430);
not NOT_1484(WX4463,WX4431);
not NOT_1485(WX4464,WX4432);
not NOT_1486(WX4465,WX4433);
not NOT_1487(WX4466,WX4434);
not NOT_1488(WX4467,WX4435);
not NOT_1489(WX4468,WX4436);
not NOT_1490(WX4469,WX4437);
not NOT_1491(WX4470,WX4438);
not NOT_1492(WX4471,WX4439);
not NOT_1493(WX4472,WX4440);
not NOT_1494(WX4473,WX4441);
not NOT_1495(WX4474,WX4442);
not NOT_1496(WX4475,WX4443);
not NOT_1497(WX4476,WX4444);
not NOT_1498(WX4477,WX4445);
not NOT_1499(WX4478,WX4446);
not NOT_1500(WX4479,WX4447);
not NOT_1501(WX4480,WX4448);
not NOT_1502(WX4481,WX4449);
not NOT_1503(WX4482,WX4450);
not NOT_1504(WX4483,WX4451);
not NOT_1505(WX4484,WX4452);
not NOT_1506(WX4485,WX4453);
not NOT_1507(WX4486,WX4454);
not NOT_1508(WX4487,WX4455);
not NOT_1509(WX4488,WX4456);
not NOT_1510(WX4489,WX4457);
not NOT_1511(WX4490,WX4458);
not NOT_1512(WX4491,WX4716);
not NOT_1513(WX4492,WX4718);
not NOT_1514(WX4493,WX4720);
not NOT_1515(WX4494,WX4722);
not NOT_1516(WX4495,WX4724);
not NOT_1517(WX4496,WX4726);
not NOT_1518(WX4497,WX4728);
not NOT_1519(WX4498,WX4730);
not NOT_1520(WX4499,WX4732);
not NOT_1521(WX4500,WX4734);
not NOT_1522(WX4501,WX4736);
not NOT_1523(WX4502,WX4738);
not NOT_1524(WX4503,WX4740);
not NOT_1525(WX4504,WX4742);
not NOT_1526(WX4505,WX4744);
not NOT_1527(WX4506,WX4746);
not NOT_1528(WX4507,WX4748);
not NOT_1529(WX4508,WX4750);
not NOT_1530(WX4509,WX4752);
not NOT_1531(WX4510,WX4754);
not NOT_1532(WX4511,WX4756);
not NOT_1533(WX4512,WX4758);
not NOT_1534(WX4513,WX4760);
not NOT_1535(WX4514,WX4762);
not NOT_1536(WX4515,WX4764);
not NOT_1537(WX4516,WX4766);
not NOT_1538(WX4517,WX4768);
not NOT_1539(WX4518,WX4770);
not NOT_1540(WX4519,WX4772);
not NOT_1541(WX4520,WX4774);
not NOT_1542(WX4521,WX4776);
not NOT_1543(WX4522,WX4778);
not NOT_1544(WX4811,WX4795);
not NOT_1545(WX4812,WX4811);
not NOT_1546(WX4813,WX4796);
not NOT_1547(WX4814,WX4813);
not NOT_1548(WX4815,WX4797);
not NOT_1549(WX4816,WX4815);
not NOT_1550(WX4817,WX4798);
not NOT_1551(WX4818,WX4817);
not NOT_1552(WX4819,WX4799);
not NOT_1553(WX4820,WX4819);
not NOT_1554(WX4821,WX4800);
not NOT_1555(WX4822,WX4821);
not NOT_1556(WX4823,WX4801);
not NOT_1557(WX4824,WX4823);
not NOT_1558(WX4825,WX4802);
not NOT_1559(WX4826,WX4825);
not NOT_1560(WX4827,WX4803);
not NOT_1561(WX4828,WX4827);
not NOT_1562(WX4829,WX4804);
not NOT_1563(WX4830,WX4829);
not NOT_1564(WX4831,WX4805);
not NOT_1565(WX4832,WX4831);
not NOT_1566(WX4833,WX4806);
not NOT_1567(WX4834,WX4833);
not NOT_1568(WX4835,WX4807);
not NOT_1569(WX4836,WX4835);
not NOT_1570(WX4837,WX4808);
not NOT_1571(WX4838,WX4837);
not NOT_1572(WX4839,WX4809);
not NOT_1573(WX4840,WX4839);
not NOT_1574(WX4841,WX4810);
not NOT_1575(WX4842,WX4841);
not NOT_1576(WX4843,WX4779);
not NOT_1577(WX4844,WX4843);
not NOT_1578(WX4845,WX4780);
not NOT_1579(WX4846,WX4845);
not NOT_1580(WX4847,WX4781);
not NOT_1581(WX4848,WX4847);
not NOT_1582(WX4849,WX4782);
not NOT_1583(WX4850,WX4849);
not NOT_1584(WX4851,WX4783);
not NOT_1585(WX4852,WX4851);
not NOT_1586(WX4853,WX4784);
not NOT_1587(WX4854,WX4853);
not NOT_1588(WX4855,WX4785);
not NOT_1589(WX4856,WX4855);
not NOT_1590(WX4857,WX4786);
not NOT_1591(WX4858,WX4857);
not NOT_1592(WX4859,WX4787);
not NOT_1593(WX4860,WX4859);
not NOT_1594(WX4861,WX4788);
not NOT_1595(WX4862,WX4861);
not NOT_1596(WX4863,WX4789);
not NOT_1597(WX4864,WX4863);
not NOT_1598(WX4865,WX4790);
not NOT_1599(WX4866,WX4865);
not NOT_1600(WX4867,WX4791);
not NOT_1601(WX4868,WX4867);
not NOT_1602(WX4869,WX4792);
not NOT_1603(WX4870,WX4869);
not NOT_1604(WX4871,WX4793);
not NOT_1605(WX4872,WX4871);
not NOT_1606(WX4873,WX4794);
not NOT_1607(WX4874,WX4873);
not NOT_1608(WX4875,TM0);
not NOT_1609(WX4876,TM0);
not NOT_1610(WX4877,TM0);
not NOT_1611(WX4878,TM1);
not NOT_1612(WX4879,TM1);
not NOT_1613(WX4880,WX4879);
not NOT_1614(WX4881,WX4877);
not NOT_1615(WX4882,WX4878);
not NOT_1616(WX4883,WX4876);
not NOT_1617(WX4884,WX4875);
not NOT_1618(WX4888,WX4884);
not NOT_1619(WX4890,WX4889);
not NOT_1620(WX4891,WX4890);
not NOT_1621(WX4895,WX4884);
not NOT_1622(WX4897,WX4896);
not NOT_1623(WX4898,WX4897);
not NOT_1624(WX4902,WX4884);
not NOT_1625(WX4904,WX4903);
not NOT_1626(WX4905,WX4904);
not NOT_1627(WX4909,WX4884);
not NOT_1628(WX4911,WX4910);
not NOT_1629(WX4912,WX4911);
not NOT_1630(WX4916,WX4884);
not NOT_1631(WX4918,WX4917);
not NOT_1632(WX4919,WX4918);
not NOT_1633(WX4923,WX4884);
not NOT_1634(WX4925,WX4924);
not NOT_1635(WX4926,WX4925);
not NOT_1636(WX4930,WX4884);
not NOT_1637(WX4932,WX4931);
not NOT_1638(WX4933,WX4932);
not NOT_1639(WX4937,WX4884);
not NOT_1640(WX4939,WX4938);
not NOT_1641(WX4940,WX4939);
not NOT_1642(WX4944,WX4884);
not NOT_1643(WX4946,WX4945);
not NOT_1644(WX4947,WX4946);
not NOT_1645(WX4951,WX4884);
not NOT_1646(WX4953,WX4952);
not NOT_1647(WX4954,WX4953);
not NOT_1648(WX4958,WX4884);
not NOT_1649(WX4960,WX4959);
not NOT_1650(WX4961,WX4960);
not NOT_1651(WX4965,WX4884);
not NOT_1652(WX4967,WX4966);
not NOT_1653(WX4968,WX4967);
not NOT_1654(WX4972,WX4884);
not NOT_1655(WX4974,WX4973);
not NOT_1656(WX4975,WX4974);
not NOT_1657(WX4979,WX4884);
not NOT_1658(WX4981,WX4980);
not NOT_1659(WX4982,WX4981);
not NOT_1660(WX4986,WX4884);
not NOT_1661(WX4988,WX4987);
not NOT_1662(WX4989,WX4988);
not NOT_1663(WX4993,WX4884);
not NOT_1664(WX4995,WX4994);
not NOT_1665(WX4996,WX4995);
not NOT_1666(WX5000,WX4884);
not NOT_1667(WX5002,WX5001);
not NOT_1668(WX5003,WX5002);
not NOT_1669(WX5007,WX4884);
not NOT_1670(WX5009,WX5008);
not NOT_1671(WX5010,WX5009);
not NOT_1672(WX5014,WX4884);
not NOT_1673(WX5016,WX5015);
not NOT_1674(WX5017,WX5016);
not NOT_1675(WX5021,WX4884);
not NOT_1676(WX5023,WX5022);
not NOT_1677(WX5024,WX5023);
not NOT_1678(WX5028,WX4884);
not NOT_1679(WX5030,WX5029);
not NOT_1680(WX5031,WX5030);
not NOT_1681(WX5035,WX4884);
not NOT_1682(WX5037,WX5036);
not NOT_1683(WX5038,WX5037);
not NOT_1684(WX5042,WX4884);
not NOT_1685(WX5044,WX5043);
not NOT_1686(WX5045,WX5044);
not NOT_1687(WX5049,WX4884);
not NOT_1688(WX5051,WX5050);
not NOT_1689(WX5052,WX5051);
not NOT_1690(WX5056,WX4884);
not NOT_1691(WX5058,WX5057);
not NOT_1692(WX5059,WX5058);
not NOT_1693(WX5063,WX4884);
not NOT_1694(WX5065,WX5064);
not NOT_1695(WX5066,WX5065);
not NOT_1696(WX5070,WX4884);
not NOT_1697(WX5072,WX5071);
not NOT_1698(WX5073,WX5072);
not NOT_1699(WX5077,WX4884);
not NOT_1700(WX5079,WX5078);
not NOT_1701(WX5080,WX5079);
not NOT_1702(WX5084,WX4884);
not NOT_1703(WX5086,WX5085);
not NOT_1704(WX5087,WX5086);
not NOT_1705(WX5091,WX4884);
not NOT_1706(WX5093,WX5092);
not NOT_1707(WX5094,WX5093);
not NOT_1708(WX5098,WX4884);
not NOT_1709(WX5100,WX5099);
not NOT_1710(WX5101,WX5100);
not NOT_1711(WX5105,WX4884);
not NOT_1712(WX5107,WX5106);
not NOT_1713(WX5108,WX5107);
not NOT_1714(WX5109,RESET);
not NOT_1715(WX5142,WX5109);
not NOT_1716(WX5209,WX6175);
not NOT_1717(WX5213,WX6176);
not NOT_1718(WX5217,WX6176);
not NOT_1719(WX5219,WX5210);
not NOT_1720(WX5220,WX5219);
not NOT_1721(WX5223,WX6175);
not NOT_1722(WX5227,WX6176);
not NOT_1723(WX5231,WX6176);
not NOT_1724(WX5233,WX5224);
not NOT_1725(WX5234,WX5233);
not NOT_1726(WX5237,WX6175);
not NOT_1727(WX5241,WX6176);
not NOT_1728(WX5245,WX6176);
not NOT_1729(WX5247,WX5238);
not NOT_1730(WX5248,WX5247);
not NOT_1731(WX5251,WX6175);
not NOT_1732(WX5255,WX6176);
not NOT_1733(WX5259,WX6176);
not NOT_1734(WX5261,WX5252);
not NOT_1735(WX5262,WX5261);
not NOT_1736(WX5265,WX6175);
not NOT_1737(WX5269,WX6176);
not NOT_1738(WX5273,WX6176);
not NOT_1739(WX5275,WX5266);
not NOT_1740(WX5276,WX5275);
not NOT_1741(WX5279,WX6175);
not NOT_1742(WX5283,WX6176);
not NOT_1743(WX5287,WX6176);
not NOT_1744(WX5289,WX5280);
not NOT_1745(WX5290,WX5289);
not NOT_1746(WX5293,WX6175);
not NOT_1747(WX5297,WX6176);
not NOT_1748(WX5301,WX6176);
not NOT_1749(WX5303,WX5294);
not NOT_1750(WX5304,WX5303);
not NOT_1751(WX5307,WX6175);
not NOT_1752(WX5311,WX6176);
not NOT_1753(WX5315,WX6176);
not NOT_1754(WX5317,WX5308);
not NOT_1755(WX5318,WX5317);
not NOT_1756(WX5321,WX6175);
not NOT_1757(WX5325,WX6176);
not NOT_1758(WX5329,WX6176);
not NOT_1759(WX5331,WX5322);
not NOT_1760(WX5332,WX5331);
not NOT_1761(WX5335,WX6175);
not NOT_1762(WX5339,WX6176);
not NOT_1763(WX5343,WX6176);
not NOT_1764(WX5345,WX5336);
not NOT_1765(WX5346,WX5345);
not NOT_1766(WX5349,WX6175);
not NOT_1767(WX5353,WX6176);
not NOT_1768(WX5357,WX6176);
not NOT_1769(WX5359,WX5350);
not NOT_1770(WX5360,WX5359);
not NOT_1771(WX5363,WX6175);
not NOT_1772(WX5367,WX6176);
not NOT_1773(WX5371,WX6176);
not NOT_1774(WX5373,WX5364);
not NOT_1775(WX5374,WX5373);
not NOT_1776(WX5377,WX6175);
not NOT_1777(WX5381,WX6176);
not NOT_1778(WX5385,WX6176);
not NOT_1779(WX5387,WX5378);
not NOT_1780(WX5388,WX5387);
not NOT_1781(WX5391,WX6175);
not NOT_1782(WX5395,WX6176);
not NOT_1783(WX5399,WX6176);
not NOT_1784(WX5401,WX5392);
not NOT_1785(WX5402,WX5401);
not NOT_1786(WX5405,WX6175);
not NOT_1787(WX5409,WX6176);
not NOT_1788(WX5413,WX6176);
not NOT_1789(WX5415,WX5406);
not NOT_1790(WX5416,WX5415);
not NOT_1791(WX5419,WX6175);
not NOT_1792(WX5423,WX6176);
not NOT_1793(WX5427,WX6176);
not NOT_1794(WX5429,WX5420);
not NOT_1795(WX5430,WX5429);
not NOT_1796(WX5433,WX6175);
not NOT_1797(WX5437,WX6176);
not NOT_1798(WX5441,WX6176);
not NOT_1799(WX5443,WX5434);
not NOT_1800(WX5444,WX5443);
not NOT_1801(WX5447,WX6175);
not NOT_1802(WX5451,WX6176);
not NOT_1803(WX5455,WX6176);
not NOT_1804(WX5457,WX5448);
not NOT_1805(WX5458,WX5457);
not NOT_1806(WX5461,WX6175);
not NOT_1807(WX5465,WX6176);
not NOT_1808(WX5469,WX6176);
not NOT_1809(WX5471,WX5462);
not NOT_1810(WX5472,WX5471);
not NOT_1811(WX5475,WX6175);
not NOT_1812(WX5479,WX6176);
not NOT_1813(WX5483,WX6176);
not NOT_1814(WX5485,WX5476);
not NOT_1815(WX5486,WX5485);
not NOT_1816(WX5489,WX6175);
not NOT_1817(WX5493,WX6176);
not NOT_1818(WX5497,WX6176);
not NOT_1819(WX5499,WX5490);
not NOT_1820(WX5500,WX5499);
not NOT_1821(WX5503,WX6175);
not NOT_1822(WX5507,WX6176);
not NOT_1823(WX5511,WX6176);
not NOT_1824(WX5513,WX5504);
not NOT_1825(WX5514,WX5513);
not NOT_1826(WX5517,WX6175);
not NOT_1827(WX5521,WX6176);
not NOT_1828(WX5525,WX6176);
not NOT_1829(WX5527,WX5518);
not NOT_1830(WX5528,WX5527);
not NOT_1831(WX5531,WX6175);
not NOT_1832(WX5535,WX6176);
not NOT_1833(WX5539,WX6176);
not NOT_1834(WX5541,WX5532);
not NOT_1835(WX5542,WX5541);
not NOT_1836(WX5545,WX6175);
not NOT_1837(WX5549,WX6176);
not NOT_1838(WX5553,WX6176);
not NOT_1839(WX5555,WX5546);
not NOT_1840(WX5556,WX5555);
not NOT_1841(WX5559,WX6175);
not NOT_1842(WX5563,WX6176);
not NOT_1843(WX5567,WX6176);
not NOT_1844(WX5569,WX5560);
not NOT_1845(WX5570,WX5569);
not NOT_1846(WX5573,WX6175);
not NOT_1847(WX5577,WX6176);
not NOT_1848(WX5581,WX6176);
not NOT_1849(WX5583,WX5574);
not NOT_1850(WX5584,WX5583);
not NOT_1851(WX5587,WX6175);
not NOT_1852(WX5591,WX6176);
not NOT_1853(WX5595,WX6176);
not NOT_1854(WX5597,WX5588);
not NOT_1855(WX5598,WX5597);
not NOT_1856(WX5601,WX6175);
not NOT_1857(WX5605,WX6176);
not NOT_1858(WX5609,WX6176);
not NOT_1859(WX5611,WX5602);
not NOT_1860(WX5612,WX5611);
not NOT_1861(WX5615,WX6175);
not NOT_1862(WX5619,WX6176);
not NOT_1863(WX5623,WX6176);
not NOT_1864(WX5625,WX5616);
not NOT_1865(WX5626,WX5625);
not NOT_1866(WX5629,WX6175);
not NOT_1867(WX5633,WX6176);
not NOT_1868(WX5637,WX6176);
not NOT_1869(WX5639,WX5630);
not NOT_1870(WX5640,WX5639);
not NOT_1871(WX5643,WX6175);
not NOT_1872(WX5647,WX6176);
not NOT_1873(WX5651,WX6176);
not NOT_1874(WX5653,WX5644);
not NOT_1875(WX5654,WX5653);
not NOT_1876(WX5655,WX5657);
not NOT_1877(WX5720,WX6137);
not NOT_1878(WX5721,WX6139);
not NOT_1879(WX5722,WX6141);
not NOT_1880(WX5723,WX6143);
not NOT_1881(WX5724,WX6145);
not NOT_1882(WX5725,WX6147);
not NOT_1883(WX5726,WX6149);
not NOT_1884(WX5727,WX6151);
not NOT_1885(WX5728,WX6153);
not NOT_1886(WX5729,WX6155);
not NOT_1887(WX5730,WX6157);
not NOT_1888(WX5731,WX6159);
not NOT_1889(WX5732,WX6161);
not NOT_1890(WX5733,WX6163);
not NOT_1891(WX5734,WX6165);
not NOT_1892(WX5735,WX6167);
not NOT_1893(WX5736,WX6105);
not NOT_1894(WX5737,WX6107);
not NOT_1895(WX5738,WX6109);
not NOT_1896(WX5739,WX6111);
not NOT_1897(WX5740,WX6113);
not NOT_1898(WX5741,WX6115);
not NOT_1899(WX5742,WX6117);
not NOT_1900(WX5743,WX6119);
not NOT_1901(WX5744,WX6121);
not NOT_1902(WX5745,WX6123);
not NOT_1903(WX5746,WX6125);
not NOT_1904(WX5747,WX6127);
not NOT_1905(WX5748,WX6129);
not NOT_1906(WX5749,WX6131);
not NOT_1907(WX5750,WX6133);
not NOT_1908(WX5751,WX6135);
not NOT_1909(WX5752,WX5720);
not NOT_1910(WX5753,WX5721);
not NOT_1911(WX5754,WX5722);
not NOT_1912(WX5755,WX5723);
not NOT_1913(WX5756,WX5724);
not NOT_1914(WX5757,WX5725);
not NOT_1915(WX5758,WX5726);
not NOT_1916(WX5759,WX5727);
not NOT_1917(WX5760,WX5728);
not NOT_1918(WX5761,WX5729);
not NOT_1919(WX5762,WX5730);
not NOT_1920(WX5763,WX5731);
not NOT_1921(WX5764,WX5732);
not NOT_1922(WX5765,WX5733);
not NOT_1923(WX5766,WX5734);
not NOT_1924(WX5767,WX5735);
not NOT_1925(WX5768,WX5736);
not NOT_1926(WX5769,WX5737);
not NOT_1927(WX5770,WX5738);
not NOT_1928(WX5771,WX5739);
not NOT_1929(WX5772,WX5740);
not NOT_1930(WX5773,WX5741);
not NOT_1931(WX5774,WX5742);
not NOT_1932(WX5775,WX5743);
not NOT_1933(WX5776,WX5744);
not NOT_1934(WX5777,WX5745);
not NOT_1935(WX5778,WX5746);
not NOT_1936(WX5779,WX5747);
not NOT_1937(WX5780,WX5748);
not NOT_1938(WX5781,WX5749);
not NOT_1939(WX5782,WX5750);
not NOT_1940(WX5783,WX5751);
not NOT_1941(WX5784,WX6009);
not NOT_1942(WX5785,WX6011);
not NOT_1943(WX5786,WX6013);
not NOT_1944(WX5787,WX6015);
not NOT_1945(WX5788,WX6017);
not NOT_1946(WX5789,WX6019);
not NOT_1947(WX5790,WX6021);
not NOT_1948(WX5791,WX6023);
not NOT_1949(WX5792,WX6025);
not NOT_1950(WX5793,WX6027);
not NOT_1951(WX5794,WX6029);
not NOT_1952(WX5795,WX6031);
not NOT_1953(WX5796,WX6033);
not NOT_1954(WX5797,WX6035);
not NOT_1955(WX5798,WX6037);
not NOT_1956(WX5799,WX6039);
not NOT_1957(WX5800,WX6041);
not NOT_1958(WX5801,WX6043);
not NOT_1959(WX5802,WX6045);
not NOT_1960(WX5803,WX6047);
not NOT_1961(WX5804,WX6049);
not NOT_1962(WX5805,WX6051);
not NOT_1963(WX5806,WX6053);
not NOT_1964(WX5807,WX6055);
not NOT_1965(WX5808,WX6057);
not NOT_1966(WX5809,WX6059);
not NOT_1967(WX5810,WX6061);
not NOT_1968(WX5811,WX6063);
not NOT_1969(WX5812,WX6065);
not NOT_1970(WX5813,WX6067);
not NOT_1971(WX5814,WX6069);
not NOT_1972(WX5815,WX6071);
not NOT_1973(WX6104,WX6088);
not NOT_1974(WX6105,WX6104);
not NOT_1975(WX6106,WX6089);
not NOT_1976(WX6107,WX6106);
not NOT_1977(WX6108,WX6090);
not NOT_1978(WX6109,WX6108);
not NOT_1979(WX6110,WX6091);
not NOT_1980(WX6111,WX6110);
not NOT_1981(WX6112,WX6092);
not NOT_1982(WX6113,WX6112);
not NOT_1983(WX6114,WX6093);
not NOT_1984(WX6115,WX6114);
not NOT_1985(WX6116,WX6094);
not NOT_1986(WX6117,WX6116);
not NOT_1987(WX6118,WX6095);
not NOT_1988(WX6119,WX6118);
not NOT_1989(WX6120,WX6096);
not NOT_1990(WX6121,WX6120);
not NOT_1991(WX6122,WX6097);
not NOT_1992(WX6123,WX6122);
not NOT_1993(WX6124,WX6098);
not NOT_1994(WX6125,WX6124);
not NOT_1995(WX6126,WX6099);
not NOT_1996(WX6127,WX6126);
not NOT_1997(WX6128,WX6100);
not NOT_1998(WX6129,WX6128);
not NOT_1999(WX6130,WX6101);
not NOT_2000(WX6131,WX6130);
not NOT_2001(WX6132,WX6102);
not NOT_2002(WX6133,WX6132);
not NOT_2003(WX6134,WX6103);
not NOT_2004(WX6135,WX6134);
not NOT_2005(WX6136,WX6072);
not NOT_2006(WX6137,WX6136);
not NOT_2007(WX6138,WX6073);
not NOT_2008(WX6139,WX6138);
not NOT_2009(WX6140,WX6074);
not NOT_2010(WX6141,WX6140);
not NOT_2011(WX6142,WX6075);
not NOT_2012(WX6143,WX6142);
not NOT_2013(WX6144,WX6076);
not NOT_2014(WX6145,WX6144);
not NOT_2015(WX6146,WX6077);
not NOT_2016(WX6147,WX6146);
not NOT_2017(WX6148,WX6078);
not NOT_2018(WX6149,WX6148);
not NOT_2019(WX6150,WX6079);
not NOT_2020(WX6151,WX6150);
not NOT_2021(WX6152,WX6080);
not NOT_2022(WX6153,WX6152);
not NOT_2023(WX6154,WX6081);
not NOT_2024(WX6155,WX6154);
not NOT_2025(WX6156,WX6082);
not NOT_2026(WX6157,WX6156);
not NOT_2027(WX6158,WX6083);
not NOT_2028(WX6159,WX6158);
not NOT_2029(WX6160,WX6084);
not NOT_2030(WX6161,WX6160);
not NOT_2031(WX6162,WX6085);
not NOT_2032(WX6163,WX6162);
not NOT_2033(WX6164,WX6086);
not NOT_2034(WX6165,WX6164);
not NOT_2035(WX6166,WX6087);
not NOT_2036(WX6167,WX6166);
not NOT_2037(WX6168,TM0);
not NOT_2038(WX6169,TM0);
not NOT_2039(WX6170,TM0);
not NOT_2040(WX6171,TM1);
not NOT_2041(WX6172,TM1);
not NOT_2042(WX6173,WX6172);
not NOT_2043(WX6174,WX6170);
not NOT_2044(WX6175,WX6171);
not NOT_2045(WX6176,WX6169);
not NOT_2046(WX6177,WX6168);
not NOT_2047(WX6181,WX6177);
not NOT_2048(WX6183,WX6182);
not NOT_2049(WX6184,WX6183);
not NOT_2050(WX6188,WX6177);
not NOT_2051(WX6190,WX6189);
not NOT_2052(WX6191,WX6190);
not NOT_2053(WX6195,WX6177);
not NOT_2054(WX6197,WX6196);
not NOT_2055(WX6198,WX6197);
not NOT_2056(WX6202,WX6177);
not NOT_2057(WX6204,WX6203);
not NOT_2058(WX6205,WX6204);
not NOT_2059(WX6209,WX6177);
not NOT_2060(WX6211,WX6210);
not NOT_2061(WX6212,WX6211);
not NOT_2062(WX6216,WX6177);
not NOT_2063(WX6218,WX6217);
not NOT_2064(WX6219,WX6218);
not NOT_2065(WX6223,WX6177);
not NOT_2066(WX6225,WX6224);
not NOT_2067(WX6226,WX6225);
not NOT_2068(WX6230,WX6177);
not NOT_2069(WX6232,WX6231);
not NOT_2070(WX6233,WX6232);
not NOT_2071(WX6237,WX6177);
not NOT_2072(WX6239,WX6238);
not NOT_2073(WX6240,WX6239);
not NOT_2074(WX6244,WX6177);
not NOT_2075(WX6246,WX6245);
not NOT_2076(WX6247,WX6246);
not NOT_2077(WX6251,WX6177);
not NOT_2078(WX6253,WX6252);
not NOT_2079(WX6254,WX6253);
not NOT_2080(WX6258,WX6177);
not NOT_2081(WX6260,WX6259);
not NOT_2082(WX6261,WX6260);
not NOT_2083(WX6265,WX6177);
not NOT_2084(WX6267,WX6266);
not NOT_2085(WX6268,WX6267);
not NOT_2086(WX6272,WX6177);
not NOT_2087(WX6274,WX6273);
not NOT_2088(WX6275,WX6274);
not NOT_2089(WX6279,WX6177);
not NOT_2090(WX6281,WX6280);
not NOT_2091(WX6282,WX6281);
not NOT_2092(WX6286,WX6177);
not NOT_2093(WX6288,WX6287);
not NOT_2094(WX6289,WX6288);
not NOT_2095(WX6293,WX6177);
not NOT_2096(WX6295,WX6294);
not NOT_2097(WX6296,WX6295);
not NOT_2098(WX6300,WX6177);
not NOT_2099(WX6302,WX6301);
not NOT_2100(WX6303,WX6302);
not NOT_2101(WX6307,WX6177);
not NOT_2102(WX6309,WX6308);
not NOT_2103(WX6310,WX6309);
not NOT_2104(WX6314,WX6177);
not NOT_2105(WX6316,WX6315);
not NOT_2106(WX6317,WX6316);
not NOT_2107(WX6321,WX6177);
not NOT_2108(WX6323,WX6322);
not NOT_2109(WX6324,WX6323);
not NOT_2110(WX6328,WX6177);
not NOT_2111(WX6330,WX6329);
not NOT_2112(WX6331,WX6330);
not NOT_2113(WX6335,WX6177);
not NOT_2114(WX6337,WX6336);
not NOT_2115(WX6338,WX6337);
not NOT_2116(WX6342,WX6177);
not NOT_2117(WX6344,WX6343);
not NOT_2118(WX6345,WX6344);
not NOT_2119(WX6349,WX6177);
not NOT_2120(WX6351,WX6350);
not NOT_2121(WX6352,WX6351);
not NOT_2122(WX6356,WX6177);
not NOT_2123(WX6358,WX6357);
not NOT_2124(WX6359,WX6358);
not NOT_2125(WX6363,WX6177);
not NOT_2126(WX6365,WX6364);
not NOT_2127(WX6366,WX6365);
not NOT_2128(WX6370,WX6177);
not NOT_2129(WX6372,WX6371);
not NOT_2130(WX6373,WX6372);
not NOT_2131(WX6377,WX6177);
not NOT_2132(WX6379,WX6378);
not NOT_2133(WX6380,WX6379);
not NOT_2134(WX6384,WX6177);
not NOT_2135(WX6386,WX6385);
not NOT_2136(WX6387,WX6386);
not NOT_2137(WX6391,WX6177);
not NOT_2138(WX6393,WX6392);
not NOT_2139(WX6394,WX6393);
not NOT_2140(WX6398,WX6177);
not NOT_2141(WX6400,WX6399);
not NOT_2142(WX6401,WX6400);
not NOT_2143(WX6402,RESET);
not NOT_2144(WX6435,WX6402);
not NOT_2145(WX6502,WX7468);
not NOT_2146(WX6506,WX7469);
not NOT_2147(WX6510,WX7469);
not NOT_2148(WX6512,WX6503);
not NOT_2149(WX6513,WX6512);
not NOT_2150(WX6516,WX7468);
not NOT_2151(WX6520,WX7469);
not NOT_2152(WX6524,WX7469);
not NOT_2153(WX6526,WX6517);
not NOT_2154(WX6527,WX6526);
not NOT_2155(WX6530,WX7468);
not NOT_2156(WX6534,WX7469);
not NOT_2157(WX6538,WX7469);
not NOT_2158(WX6540,WX6531);
not NOT_2159(WX6541,WX6540);
not NOT_2160(WX6544,WX7468);
not NOT_2161(WX6548,WX7469);
not NOT_2162(WX6552,WX7469);
not NOT_2163(WX6554,WX6545);
not NOT_2164(WX6555,WX6554);
not NOT_2165(WX6558,WX7468);
not NOT_2166(WX6562,WX7469);
not NOT_2167(WX6566,WX7469);
not NOT_2168(WX6568,WX6559);
not NOT_2169(WX6569,WX6568);
not NOT_2170(WX6572,WX7468);
not NOT_2171(WX6576,WX7469);
not NOT_2172(WX6580,WX7469);
not NOT_2173(WX6582,WX6573);
not NOT_2174(WX6583,WX6582);
not NOT_2175(WX6586,WX7468);
not NOT_2176(WX6590,WX7469);
not NOT_2177(WX6594,WX7469);
not NOT_2178(WX6596,WX6587);
not NOT_2179(WX6597,WX6596);
not NOT_2180(WX6600,WX7468);
not NOT_2181(WX6604,WX7469);
not NOT_2182(WX6608,WX7469);
not NOT_2183(WX6610,WX6601);
not NOT_2184(WX6611,WX6610);
not NOT_2185(WX6614,WX7468);
not NOT_2186(WX6618,WX7469);
not NOT_2187(WX6622,WX7469);
not NOT_2188(WX6624,WX6615);
not NOT_2189(WX6625,WX6624);
not NOT_2190(WX6628,WX7468);
not NOT_2191(WX6632,WX7469);
not NOT_2192(WX6636,WX7469);
not NOT_2193(WX6638,WX6629);
not NOT_2194(WX6639,WX6638);
not NOT_2195(WX6642,WX7468);
not NOT_2196(WX6646,WX7469);
not NOT_2197(WX6650,WX7469);
not NOT_2198(WX6652,WX6643);
not NOT_2199(WX6653,WX6652);
not NOT_2200(WX6656,WX7468);
not NOT_2201(WX6660,WX7469);
not NOT_2202(WX6664,WX7469);
not NOT_2203(WX6666,WX6657);
not NOT_2204(WX6667,WX6666);
not NOT_2205(WX6670,WX7468);
not NOT_2206(WX6674,WX7469);
not NOT_2207(WX6678,WX7469);
not NOT_2208(WX6680,WX6671);
not NOT_2209(WX6681,WX6680);
not NOT_2210(WX6684,WX7468);
not NOT_2211(WX6688,WX7469);
not NOT_2212(WX6692,WX7469);
not NOT_2213(WX6694,WX6685);
not NOT_2214(WX6695,WX6694);
not NOT_2215(WX6698,WX7468);
not NOT_2216(WX6702,WX7469);
not NOT_2217(WX6706,WX7469);
not NOT_2218(WX6708,WX6699);
not NOT_2219(WX6709,WX6708);
not NOT_2220(WX6712,WX7468);
not NOT_2221(WX6716,WX7469);
not NOT_2222(WX6720,WX7469);
not NOT_2223(WX6722,WX6713);
not NOT_2224(WX6723,WX6722);
not NOT_2225(WX6726,WX7468);
not NOT_2226(WX6730,WX7469);
not NOT_2227(WX6734,WX7469);
not NOT_2228(WX6736,WX6727);
not NOT_2229(WX6737,WX6736);
not NOT_2230(WX6740,WX7468);
not NOT_2231(WX6744,WX7469);
not NOT_2232(WX6748,WX7469);
not NOT_2233(WX6750,WX6741);
not NOT_2234(WX6751,WX6750);
not NOT_2235(WX6754,WX7468);
not NOT_2236(WX6758,WX7469);
not NOT_2237(WX6762,WX7469);
not NOT_2238(WX6764,WX6755);
not NOT_2239(WX6765,WX6764);
not NOT_2240(WX6768,WX7468);
not NOT_2241(WX6772,WX7469);
not NOT_2242(WX6776,WX7469);
not NOT_2243(WX6778,WX6769);
not NOT_2244(WX6779,WX6778);
not NOT_2245(WX6782,WX7468);
not NOT_2246(WX6786,WX7469);
not NOT_2247(WX6790,WX7469);
not NOT_2248(WX6792,WX6783);
not NOT_2249(WX6793,WX6792);
not NOT_2250(WX6796,WX7468);
not NOT_2251(WX6800,WX7469);
not NOT_2252(WX6804,WX7469);
not NOT_2253(WX6806,WX6797);
not NOT_2254(WX6807,WX6806);
not NOT_2255(WX6810,WX7468);
not NOT_2256(WX6814,WX7469);
not NOT_2257(WX6818,WX7469);
not NOT_2258(WX6820,WX6811);
not NOT_2259(WX6821,WX6820);
not NOT_2260(WX6824,WX7468);
not NOT_2261(WX6828,WX7469);
not NOT_2262(WX6832,WX7469);
not NOT_2263(WX6834,WX6825);
not NOT_2264(WX6835,WX6834);
not NOT_2265(WX6838,WX7468);
not NOT_2266(WX6842,WX7469);
not NOT_2267(WX6846,WX7469);
not NOT_2268(WX6848,WX6839);
not NOT_2269(WX6849,WX6848);
not NOT_2270(WX6852,WX7468);
not NOT_2271(WX6856,WX7469);
not NOT_2272(WX6860,WX7469);
not NOT_2273(WX6862,WX6853);
not NOT_2274(WX6863,WX6862);
not NOT_2275(WX6866,WX7468);
not NOT_2276(WX6870,WX7469);
not NOT_2277(WX6874,WX7469);
not NOT_2278(WX6876,WX6867);
not NOT_2279(WX6877,WX6876);
not NOT_2280(WX6880,WX7468);
not NOT_2281(WX6884,WX7469);
not NOT_2282(WX6888,WX7469);
not NOT_2283(WX6890,WX6881);
not NOT_2284(WX6891,WX6890);
not NOT_2285(WX6894,WX7468);
not NOT_2286(WX6898,WX7469);
not NOT_2287(WX6902,WX7469);
not NOT_2288(WX6904,WX6895);
not NOT_2289(WX6905,WX6904);
not NOT_2290(WX6908,WX7468);
not NOT_2291(WX6912,WX7469);
not NOT_2292(WX6916,WX7469);
not NOT_2293(WX6918,WX6909);
not NOT_2294(WX6919,WX6918);
not NOT_2295(WX6922,WX7468);
not NOT_2296(WX6926,WX7469);
not NOT_2297(WX6930,WX7469);
not NOT_2298(WX6932,WX6923);
not NOT_2299(WX6933,WX6932);
not NOT_2300(WX6936,WX7468);
not NOT_2301(WX6940,WX7469);
not NOT_2302(WX6944,WX7469);
not NOT_2303(WX6946,WX6937);
not NOT_2304(WX6947,WX6946);
not NOT_2305(WX6948,WX6950);
not NOT_2306(WX7013,WX7430);
not NOT_2307(WX7014,WX7432);
not NOT_2308(WX7015,WX7434);
not NOT_2309(WX7016,WX7436);
not NOT_2310(WX7017,WX7438);
not NOT_2311(WX7018,WX7440);
not NOT_2312(WX7019,WX7442);
not NOT_2313(WX7020,WX7444);
not NOT_2314(WX7021,WX7446);
not NOT_2315(WX7022,WX7448);
not NOT_2316(WX7023,WX7450);
not NOT_2317(WX7024,WX7452);
not NOT_2318(WX7025,WX7454);
not NOT_2319(WX7026,WX7456);
not NOT_2320(WX7027,WX7458);
not NOT_2321(WX7028,WX7460);
not NOT_2322(WX7029,WX7398);
not NOT_2323(WX7030,WX7400);
not NOT_2324(WX7031,WX7402);
not NOT_2325(WX7032,WX7404);
not NOT_2326(WX7033,WX7406);
not NOT_2327(WX7034,WX7408);
not NOT_2328(WX7035,WX7410);
not NOT_2329(WX7036,WX7412);
not NOT_2330(WX7037,WX7414);
not NOT_2331(WX7038,WX7416);
not NOT_2332(WX7039,WX7418);
not NOT_2333(WX7040,WX7420);
not NOT_2334(WX7041,WX7422);
not NOT_2335(WX7042,WX7424);
not NOT_2336(WX7043,WX7426);
not NOT_2337(WX7044,WX7428);
not NOT_2338(WX7045,WX7013);
not NOT_2339(WX7046,WX7014);
not NOT_2340(WX7047,WX7015);
not NOT_2341(WX7048,WX7016);
not NOT_2342(WX7049,WX7017);
not NOT_2343(WX7050,WX7018);
not NOT_2344(WX7051,WX7019);
not NOT_2345(WX7052,WX7020);
not NOT_2346(WX7053,WX7021);
not NOT_2347(WX7054,WX7022);
not NOT_2348(WX7055,WX7023);
not NOT_2349(WX7056,WX7024);
not NOT_2350(WX7057,WX7025);
not NOT_2351(WX7058,WX7026);
not NOT_2352(WX7059,WX7027);
not NOT_2353(WX7060,WX7028);
not NOT_2354(WX7061,WX7029);
not NOT_2355(WX7062,WX7030);
not NOT_2356(WX7063,WX7031);
not NOT_2357(WX7064,WX7032);
not NOT_2358(WX7065,WX7033);
not NOT_2359(WX7066,WX7034);
not NOT_2360(WX7067,WX7035);
not NOT_2361(WX7068,WX7036);
not NOT_2362(WX7069,WX7037);
not NOT_2363(WX7070,WX7038);
not NOT_2364(WX7071,WX7039);
not NOT_2365(WX7072,WX7040);
not NOT_2366(WX7073,WX7041);
not NOT_2367(WX7074,WX7042);
not NOT_2368(WX7075,WX7043);
not NOT_2369(WX7076,WX7044);
not NOT_2370(WX7077,WX7302);
not NOT_2371(WX7078,WX7304);
not NOT_2372(WX7079,WX7306);
not NOT_2373(WX7080,WX7308);
not NOT_2374(WX7081,WX7310);
not NOT_2375(WX7082,WX7312);
not NOT_2376(WX7083,WX7314);
not NOT_2377(WX7084,WX7316);
not NOT_2378(WX7085,WX7318);
not NOT_2379(WX7086,WX7320);
not NOT_2380(WX7087,WX7322);
not NOT_2381(WX7088,WX7324);
not NOT_2382(WX7089,WX7326);
not NOT_2383(WX7090,WX7328);
not NOT_2384(WX7091,WX7330);
not NOT_2385(WX7092,WX7332);
not NOT_2386(WX7093,WX7334);
not NOT_2387(WX7094,WX7336);
not NOT_2388(WX7095,WX7338);
not NOT_2389(WX7096,WX7340);
not NOT_2390(WX7097,WX7342);
not NOT_2391(WX7098,WX7344);
not NOT_2392(WX7099,WX7346);
not NOT_2393(WX7100,WX7348);
not NOT_2394(WX7101,WX7350);
not NOT_2395(WX7102,WX7352);
not NOT_2396(WX7103,WX7354);
not NOT_2397(WX7104,WX7356);
not NOT_2398(WX7105,WX7358);
not NOT_2399(WX7106,WX7360);
not NOT_2400(WX7107,WX7362);
not NOT_2401(WX7108,WX7364);
not NOT_2402(WX7397,WX7381);
not NOT_2403(WX7398,WX7397);
not NOT_2404(WX7399,WX7382);
not NOT_2405(WX7400,WX7399);
not NOT_2406(WX7401,WX7383);
not NOT_2407(WX7402,WX7401);
not NOT_2408(WX7403,WX7384);
not NOT_2409(WX7404,WX7403);
not NOT_2410(WX7405,WX7385);
not NOT_2411(WX7406,WX7405);
not NOT_2412(WX7407,WX7386);
not NOT_2413(WX7408,WX7407);
not NOT_2414(WX7409,WX7387);
not NOT_2415(WX7410,WX7409);
not NOT_2416(WX7411,WX7388);
not NOT_2417(WX7412,WX7411);
not NOT_2418(WX7413,WX7389);
not NOT_2419(WX7414,WX7413);
not NOT_2420(WX7415,WX7390);
not NOT_2421(WX7416,WX7415);
not NOT_2422(WX7417,WX7391);
not NOT_2423(WX7418,WX7417);
not NOT_2424(WX7419,WX7392);
not NOT_2425(WX7420,WX7419);
not NOT_2426(WX7421,WX7393);
not NOT_2427(WX7422,WX7421);
not NOT_2428(WX7423,WX7394);
not NOT_2429(WX7424,WX7423);
not NOT_2430(WX7425,WX7395);
not NOT_2431(WX7426,WX7425);
not NOT_2432(WX7427,WX7396);
not NOT_2433(WX7428,WX7427);
not NOT_2434(WX7429,WX7365);
not NOT_2435(WX7430,WX7429);
not NOT_2436(WX7431,WX7366);
not NOT_2437(WX7432,WX7431);
not NOT_2438(WX7433,WX7367);
not NOT_2439(WX7434,WX7433);
not NOT_2440(WX7435,WX7368);
not NOT_2441(WX7436,WX7435);
not NOT_2442(WX7437,WX7369);
not NOT_2443(WX7438,WX7437);
not NOT_2444(WX7439,WX7370);
not NOT_2445(WX7440,WX7439);
not NOT_2446(WX7441,WX7371);
not NOT_2447(WX7442,WX7441);
not NOT_2448(WX7443,WX7372);
not NOT_2449(WX7444,WX7443);
not NOT_2450(WX7445,WX7373);
not NOT_2451(WX7446,WX7445);
not NOT_2452(WX7447,WX7374);
not NOT_2453(WX7448,WX7447);
not NOT_2454(WX7449,WX7375);
not NOT_2455(WX7450,WX7449);
not NOT_2456(WX7451,WX7376);
not NOT_2457(WX7452,WX7451);
not NOT_2458(WX7453,WX7377);
not NOT_2459(WX7454,WX7453);
not NOT_2460(WX7455,WX7378);
not NOT_2461(WX7456,WX7455);
not NOT_2462(WX7457,WX7379);
not NOT_2463(WX7458,WX7457);
not NOT_2464(WX7459,WX7380);
not NOT_2465(WX7460,WX7459);
not NOT_2466(WX7461,TM0);
not NOT_2467(WX7462,TM0);
not NOT_2468(WX7463,TM0);
not NOT_2469(WX7464,TM1);
not NOT_2470(WX7465,TM1);
not NOT_2471(WX7466,WX7465);
not NOT_2472(WX7467,WX7463);
not NOT_2473(WX7468,WX7464);
not NOT_2474(WX7469,WX7462);
not NOT_2475(WX7470,WX7461);
not NOT_2476(WX7474,WX7470);
not NOT_2477(WX7476,WX7475);
not NOT_2478(WX7477,WX7476);
not NOT_2479(WX7481,WX7470);
not NOT_2480(WX7483,WX7482);
not NOT_2481(WX7484,WX7483);
not NOT_2482(WX7488,WX7470);
not NOT_2483(WX7490,WX7489);
not NOT_2484(WX7491,WX7490);
not NOT_2485(WX7495,WX7470);
not NOT_2486(WX7497,WX7496);
not NOT_2487(WX7498,WX7497);
not NOT_2488(WX7502,WX7470);
not NOT_2489(WX7504,WX7503);
not NOT_2490(WX7505,WX7504);
not NOT_2491(WX7509,WX7470);
not NOT_2492(WX7511,WX7510);
not NOT_2493(WX7512,WX7511);
not NOT_2494(WX7516,WX7470);
not NOT_2495(WX7518,WX7517);
not NOT_2496(WX7519,WX7518);
not NOT_2497(WX7523,WX7470);
not NOT_2498(WX7525,WX7524);
not NOT_2499(WX7526,WX7525);
not NOT_2500(WX7530,WX7470);
not NOT_2501(WX7532,WX7531);
not NOT_2502(WX7533,WX7532);
not NOT_2503(WX7537,WX7470);
not NOT_2504(WX7539,WX7538);
not NOT_2505(WX7540,WX7539);
not NOT_2506(WX7544,WX7470);
not NOT_2507(WX7546,WX7545);
not NOT_2508(WX7547,WX7546);
not NOT_2509(WX7551,WX7470);
not NOT_2510(WX7553,WX7552);
not NOT_2511(WX7554,WX7553);
not NOT_2512(WX7558,WX7470);
not NOT_2513(WX7560,WX7559);
not NOT_2514(WX7561,WX7560);
not NOT_2515(WX7565,WX7470);
not NOT_2516(WX7567,WX7566);
not NOT_2517(WX7568,WX7567);
not NOT_2518(WX7572,WX7470);
not NOT_2519(WX7574,WX7573);
not NOT_2520(WX7575,WX7574);
not NOT_2521(WX7579,WX7470);
not NOT_2522(WX7581,WX7580);
not NOT_2523(WX7582,WX7581);
not NOT_2524(WX7586,WX7470);
not NOT_2525(WX7588,WX7587);
not NOT_2526(WX7589,WX7588);
not NOT_2527(WX7593,WX7470);
not NOT_2528(WX7595,WX7594);
not NOT_2529(WX7596,WX7595);
not NOT_2530(WX7600,WX7470);
not NOT_2531(WX7602,WX7601);
not NOT_2532(WX7603,WX7602);
not NOT_2533(WX7607,WX7470);
not NOT_2534(WX7609,WX7608);
not NOT_2535(WX7610,WX7609);
not NOT_2536(WX7614,WX7470);
not NOT_2537(WX7616,WX7615);
not NOT_2538(WX7617,WX7616);
not NOT_2539(WX7621,WX7470);
not NOT_2540(WX7623,WX7622);
not NOT_2541(WX7624,WX7623);
not NOT_2542(WX7628,WX7470);
not NOT_2543(WX7630,WX7629);
not NOT_2544(WX7631,WX7630);
not NOT_2545(WX7635,WX7470);
not NOT_2546(WX7637,WX7636);
not NOT_2547(WX7638,WX7637);
not NOT_2548(WX7642,WX7470);
not NOT_2549(WX7644,WX7643);
not NOT_2550(WX7645,WX7644);
not NOT_2551(WX7649,WX7470);
not NOT_2552(WX7651,WX7650);
not NOT_2553(WX7652,WX7651);
not NOT_2554(WX7656,WX7470);
not NOT_2555(WX7658,WX7657);
not NOT_2556(WX7659,WX7658);
not NOT_2557(WX7663,WX7470);
not NOT_2558(WX7665,WX7664);
not NOT_2559(WX7666,WX7665);
not NOT_2560(WX7670,WX7470);
not NOT_2561(WX7672,WX7671);
not NOT_2562(WX7673,WX7672);
not NOT_2563(WX7677,WX7470);
not NOT_2564(WX7679,WX7678);
not NOT_2565(WX7680,WX7679);
not NOT_2566(WX7684,WX7470);
not NOT_2567(WX7686,WX7685);
not NOT_2568(WX7687,WX7686);
not NOT_2569(WX7691,WX7470);
not NOT_2570(WX7693,WX7692);
not NOT_2571(WX7694,WX7693);
not NOT_2572(WX7695,RESET);
not NOT_2573(WX7728,WX7695);
not NOT_2574(WX7795,WX8761);
not NOT_2575(WX7799,WX8762);
not NOT_2576(WX7803,WX8762);
not NOT_2577(WX7805,WX7796);
not NOT_2578(WX7806,WX7805);
not NOT_2579(WX7809,WX8761);
not NOT_2580(WX7813,WX8762);
not NOT_2581(WX7817,WX8762);
not NOT_2582(WX7819,WX7810);
not NOT_2583(WX7820,WX7819);
not NOT_2584(WX7823,WX8761);
not NOT_2585(WX7827,WX8762);
not NOT_2586(WX7831,WX8762);
not NOT_2587(WX7833,WX7824);
not NOT_2588(WX7834,WX7833);
not NOT_2589(WX7837,WX8761);
not NOT_2590(WX7841,WX8762);
not NOT_2591(WX7845,WX8762);
not NOT_2592(WX7847,WX7838);
not NOT_2593(WX7848,WX7847);
not NOT_2594(WX7851,WX8761);
not NOT_2595(WX7855,WX8762);
not NOT_2596(WX7859,WX8762);
not NOT_2597(WX7861,WX7852);
not NOT_2598(WX7862,WX7861);
not NOT_2599(WX7865,WX8761);
not NOT_2600(WX7869,WX8762);
not NOT_2601(WX7873,WX8762);
not NOT_2602(WX7875,WX7866);
not NOT_2603(WX7876,WX7875);
not NOT_2604(WX7879,WX8761);
not NOT_2605(WX7883,WX8762);
not NOT_2606(WX7887,WX8762);
not NOT_2607(WX7889,WX7880);
not NOT_2608(WX7890,WX7889);
not NOT_2609(WX7893,WX8761);
not NOT_2610(WX7897,WX8762);
not NOT_2611(WX7901,WX8762);
not NOT_2612(WX7903,WX7894);
not NOT_2613(WX7904,WX7903);
not NOT_2614(WX7907,WX8761);
not NOT_2615(WX7911,WX8762);
not NOT_2616(WX7915,WX8762);
not NOT_2617(WX7917,WX7908);
not NOT_2618(WX7918,WX7917);
not NOT_2619(WX7921,WX8761);
not NOT_2620(WX7925,WX8762);
not NOT_2621(WX7929,WX8762);
not NOT_2622(WX7931,WX7922);
not NOT_2623(WX7932,WX7931);
not NOT_2624(WX7935,WX8761);
not NOT_2625(WX7939,WX8762);
not NOT_2626(WX7943,WX8762);
not NOT_2627(WX7945,WX7936);
not NOT_2628(WX7946,WX7945);
not NOT_2629(WX7949,WX8761);
not NOT_2630(WX7953,WX8762);
not NOT_2631(WX7957,WX8762);
not NOT_2632(WX7959,WX7950);
not NOT_2633(WX7960,WX7959);
not NOT_2634(WX7963,WX8761);
not NOT_2635(WX7967,WX8762);
not NOT_2636(WX7971,WX8762);
not NOT_2637(WX7973,WX7964);
not NOT_2638(WX7974,WX7973);
not NOT_2639(WX7977,WX8761);
not NOT_2640(WX7981,WX8762);
not NOT_2641(WX7985,WX8762);
not NOT_2642(WX7987,WX7978);
not NOT_2643(WX7988,WX7987);
not NOT_2644(WX7991,WX8761);
not NOT_2645(WX7995,WX8762);
not NOT_2646(WX7999,WX8762);
not NOT_2647(WX8001,WX7992);
not NOT_2648(WX8002,WX8001);
not NOT_2649(WX8005,WX8761);
not NOT_2650(WX8009,WX8762);
not NOT_2651(WX8013,WX8762);
not NOT_2652(WX8015,WX8006);
not NOT_2653(WX8016,WX8015);
not NOT_2654(WX8019,WX8761);
not NOT_2655(WX8023,WX8762);
not NOT_2656(WX8027,WX8762);
not NOT_2657(WX8029,WX8020);
not NOT_2658(WX8030,WX8029);
not NOT_2659(WX8033,WX8761);
not NOT_2660(WX8037,WX8762);
not NOT_2661(WX8041,WX8762);
not NOT_2662(WX8043,WX8034);
not NOT_2663(WX8044,WX8043);
not NOT_2664(WX8047,WX8761);
not NOT_2665(WX8051,WX8762);
not NOT_2666(WX8055,WX8762);
not NOT_2667(WX8057,WX8048);
not NOT_2668(WX8058,WX8057);
not NOT_2669(WX8061,WX8761);
not NOT_2670(WX8065,WX8762);
not NOT_2671(WX8069,WX8762);
not NOT_2672(WX8071,WX8062);
not NOT_2673(WX8072,WX8071);
not NOT_2674(WX8075,WX8761);
not NOT_2675(WX8079,WX8762);
not NOT_2676(WX8083,WX8762);
not NOT_2677(WX8085,WX8076);
not NOT_2678(WX8086,WX8085);
not NOT_2679(WX8089,WX8761);
not NOT_2680(WX8093,WX8762);
not NOT_2681(WX8097,WX8762);
not NOT_2682(WX8099,WX8090);
not NOT_2683(WX8100,WX8099);
not NOT_2684(WX8103,WX8761);
not NOT_2685(WX8107,WX8762);
not NOT_2686(WX8111,WX8762);
not NOT_2687(WX8113,WX8104);
not NOT_2688(WX8114,WX8113);
not NOT_2689(WX8117,WX8761);
not NOT_2690(WX8121,WX8762);
not NOT_2691(WX8125,WX8762);
not NOT_2692(WX8127,WX8118);
not NOT_2693(WX8128,WX8127);
not NOT_2694(WX8131,WX8761);
not NOT_2695(WX8135,WX8762);
not NOT_2696(WX8139,WX8762);
not NOT_2697(WX8141,WX8132);
not NOT_2698(WX8142,WX8141);
not NOT_2699(WX8145,WX8761);
not NOT_2700(WX8149,WX8762);
not NOT_2701(WX8153,WX8762);
not NOT_2702(WX8155,WX8146);
not NOT_2703(WX8156,WX8155);
not NOT_2704(WX8159,WX8761);
not NOT_2705(WX8163,WX8762);
not NOT_2706(WX8167,WX8762);
not NOT_2707(WX8169,WX8160);
not NOT_2708(WX8170,WX8169);
not NOT_2709(WX8173,WX8761);
not NOT_2710(WX8177,WX8762);
not NOT_2711(WX8181,WX8762);
not NOT_2712(WX8183,WX8174);
not NOT_2713(WX8184,WX8183);
not NOT_2714(WX8187,WX8761);
not NOT_2715(WX8191,WX8762);
not NOT_2716(WX8195,WX8762);
not NOT_2717(WX8197,WX8188);
not NOT_2718(WX8198,WX8197);
not NOT_2719(WX8201,WX8761);
not NOT_2720(WX8205,WX8762);
not NOT_2721(WX8209,WX8762);
not NOT_2722(WX8211,WX8202);
not NOT_2723(WX8212,WX8211);
not NOT_2724(WX8215,WX8761);
not NOT_2725(WX8219,WX8762);
not NOT_2726(WX8223,WX8762);
not NOT_2727(WX8225,WX8216);
not NOT_2728(WX8226,WX8225);
not NOT_2729(WX8229,WX8761);
not NOT_2730(WX8233,WX8762);
not NOT_2731(WX8237,WX8762);
not NOT_2732(WX8239,WX8230);
not NOT_2733(WX8240,WX8239);
not NOT_2734(WX8241,WX8243);
not NOT_2735(WX8306,WX8723);
not NOT_2736(WX8307,WX8725);
not NOT_2737(WX8308,WX8727);
not NOT_2738(WX8309,WX8729);
not NOT_2739(WX8310,WX8731);
not NOT_2740(WX8311,WX8733);
not NOT_2741(WX8312,WX8735);
not NOT_2742(WX8313,WX8737);
not NOT_2743(WX8314,WX8739);
not NOT_2744(WX8315,WX8741);
not NOT_2745(WX8316,WX8743);
not NOT_2746(WX8317,WX8745);
not NOT_2747(WX8318,WX8747);
not NOT_2748(WX8319,WX8749);
not NOT_2749(WX8320,WX8751);
not NOT_2750(WX8321,WX8753);
not NOT_2751(WX8322,WX8691);
not NOT_2752(WX8323,WX8693);
not NOT_2753(WX8324,WX8695);
not NOT_2754(WX8325,WX8697);
not NOT_2755(WX8326,WX8699);
not NOT_2756(WX8327,WX8701);
not NOT_2757(WX8328,WX8703);
not NOT_2758(WX8329,WX8705);
not NOT_2759(WX8330,WX8707);
not NOT_2760(WX8331,WX8709);
not NOT_2761(WX8332,WX8711);
not NOT_2762(WX8333,WX8713);
not NOT_2763(WX8334,WX8715);
not NOT_2764(WX8335,WX8717);
not NOT_2765(WX8336,WX8719);
not NOT_2766(WX8337,WX8721);
not NOT_2767(WX8338,WX8306);
not NOT_2768(WX8339,WX8307);
not NOT_2769(WX8340,WX8308);
not NOT_2770(WX8341,WX8309);
not NOT_2771(WX8342,WX8310);
not NOT_2772(WX8343,WX8311);
not NOT_2773(WX8344,WX8312);
not NOT_2774(WX8345,WX8313);
not NOT_2775(WX8346,WX8314);
not NOT_2776(WX8347,WX8315);
not NOT_2777(WX8348,WX8316);
not NOT_2778(WX8349,WX8317);
not NOT_2779(WX8350,WX8318);
not NOT_2780(WX8351,WX8319);
not NOT_2781(WX8352,WX8320);
not NOT_2782(WX8353,WX8321);
not NOT_2783(WX8354,WX8322);
not NOT_2784(WX8355,WX8323);
not NOT_2785(WX8356,WX8324);
not NOT_2786(WX8357,WX8325);
not NOT_2787(WX8358,WX8326);
not NOT_2788(WX8359,WX8327);
not NOT_2789(WX8360,WX8328);
not NOT_2790(WX8361,WX8329);
not NOT_2791(WX8362,WX8330);
not NOT_2792(WX8363,WX8331);
not NOT_2793(WX8364,WX8332);
not NOT_2794(WX8365,WX8333);
not NOT_2795(WX8366,WX8334);
not NOT_2796(WX8367,WX8335);
not NOT_2797(WX8368,WX8336);
not NOT_2798(WX8369,WX8337);
not NOT_2799(WX8370,WX8595);
not NOT_2800(WX8371,WX8597);
not NOT_2801(WX8372,WX8599);
not NOT_2802(WX8373,WX8601);
not NOT_2803(WX8374,WX8603);
not NOT_2804(WX8375,WX8605);
not NOT_2805(WX8376,WX8607);
not NOT_2806(WX8377,WX8609);
not NOT_2807(WX8378,WX8611);
not NOT_2808(WX8379,WX8613);
not NOT_2809(WX8380,WX8615);
not NOT_2810(WX8381,WX8617);
not NOT_2811(WX8382,WX8619);
not NOT_2812(WX8383,WX8621);
not NOT_2813(WX8384,WX8623);
not NOT_2814(WX8385,WX8625);
not NOT_2815(WX8386,WX8627);
not NOT_2816(WX8387,WX8629);
not NOT_2817(WX8388,WX8631);
not NOT_2818(WX8389,WX8633);
not NOT_2819(WX8390,WX8635);
not NOT_2820(WX8391,WX8637);
not NOT_2821(WX8392,WX8639);
not NOT_2822(WX8393,WX8641);
not NOT_2823(WX8394,WX8643);
not NOT_2824(WX8395,WX8645);
not NOT_2825(WX8396,WX8647);
not NOT_2826(WX8397,WX8649);
not NOT_2827(WX8398,WX8651);
not NOT_2828(WX8399,WX8653);
not NOT_2829(WX8400,WX8655);
not NOT_2830(WX8401,WX8657);
not NOT_2831(WX8690,WX8674);
not NOT_2832(WX8691,WX8690);
not NOT_2833(WX8692,WX8675);
not NOT_2834(WX8693,WX8692);
not NOT_2835(WX8694,WX8676);
not NOT_2836(WX8695,WX8694);
not NOT_2837(WX8696,WX8677);
not NOT_2838(WX8697,WX8696);
not NOT_2839(WX8698,WX8678);
not NOT_2840(WX8699,WX8698);
not NOT_2841(WX8700,WX8679);
not NOT_2842(WX8701,WX8700);
not NOT_2843(WX8702,WX8680);
not NOT_2844(WX8703,WX8702);
not NOT_2845(WX8704,WX8681);
not NOT_2846(WX8705,WX8704);
not NOT_2847(WX8706,WX8682);
not NOT_2848(WX8707,WX8706);
not NOT_2849(WX8708,WX8683);
not NOT_2850(WX8709,WX8708);
not NOT_2851(WX8710,WX8684);
not NOT_2852(WX8711,WX8710);
not NOT_2853(WX8712,WX8685);
not NOT_2854(WX8713,WX8712);
not NOT_2855(WX8714,WX8686);
not NOT_2856(WX8715,WX8714);
not NOT_2857(WX8716,WX8687);
not NOT_2858(WX8717,WX8716);
not NOT_2859(WX8718,WX8688);
not NOT_2860(WX8719,WX8718);
not NOT_2861(WX8720,WX8689);
not NOT_2862(WX8721,WX8720);
not NOT_2863(WX8722,WX8658);
not NOT_2864(WX8723,WX8722);
not NOT_2865(WX8724,WX8659);
not NOT_2866(WX8725,WX8724);
not NOT_2867(WX8726,WX8660);
not NOT_2868(WX8727,WX8726);
not NOT_2869(WX8728,WX8661);
not NOT_2870(WX8729,WX8728);
not NOT_2871(WX8730,WX8662);
not NOT_2872(WX8731,WX8730);
not NOT_2873(WX8732,WX8663);
not NOT_2874(WX8733,WX8732);
not NOT_2875(WX8734,WX8664);
not NOT_2876(WX8735,WX8734);
not NOT_2877(WX8736,WX8665);
not NOT_2878(WX8737,WX8736);
not NOT_2879(WX8738,WX8666);
not NOT_2880(WX8739,WX8738);
not NOT_2881(WX8740,WX8667);
not NOT_2882(WX8741,WX8740);
not NOT_2883(WX8742,WX8668);
not NOT_2884(WX8743,WX8742);
not NOT_2885(WX8744,WX8669);
not NOT_2886(WX8745,WX8744);
not NOT_2887(WX8746,WX8670);
not NOT_2888(WX8747,WX8746);
not NOT_2889(WX8748,WX8671);
not NOT_2890(WX8749,WX8748);
not NOT_2891(WX8750,WX8672);
not NOT_2892(WX8751,WX8750);
not NOT_2893(WX8752,WX8673);
not NOT_2894(WX8753,WX8752);
not NOT_2895(WX8754,TM0);
not NOT_2896(WX8755,TM0);
not NOT_2897(WX8756,TM0);
not NOT_2898(WX8757,TM1);
not NOT_2899(WX8758,TM1);
not NOT_2900(WX8759,WX8758);
not NOT_2901(WX8760,WX8756);
not NOT_2902(WX8761,WX8757);
not NOT_2903(WX8762,WX8755);
not NOT_2904(WX8763,WX8754);
not NOT_2905(WX8767,WX8763);
not NOT_2906(WX8769,WX8768);
not NOT_2907(WX8770,WX8769);
not NOT_2908(WX8774,WX8763);
not NOT_2909(WX8776,WX8775);
not NOT_2910(WX8777,WX8776);
not NOT_2911(WX8781,WX8763);
not NOT_2912(WX8783,WX8782);
not NOT_2913(WX8784,WX8783);
not NOT_2914(WX8788,WX8763);
not NOT_2915(WX8790,WX8789);
not NOT_2916(WX8791,WX8790);
not NOT_2917(WX8795,WX8763);
not NOT_2918(WX8797,WX8796);
not NOT_2919(WX8798,WX8797);
not NOT_2920(WX8802,WX8763);
not NOT_2921(WX8804,WX8803);
not NOT_2922(WX8805,WX8804);
not NOT_2923(WX8809,WX8763);
not NOT_2924(WX8811,WX8810);
not NOT_2925(WX8812,WX8811);
not NOT_2926(WX8816,WX8763);
not NOT_2927(WX8818,WX8817);
not NOT_2928(WX8819,WX8818);
not NOT_2929(WX8823,WX8763);
not NOT_2930(WX8825,WX8824);
not NOT_2931(WX8826,WX8825);
not NOT_2932(WX8830,WX8763);
not NOT_2933(WX8832,WX8831);
not NOT_2934(WX8833,WX8832);
not NOT_2935(WX8837,WX8763);
not NOT_2936(WX8839,WX8838);
not NOT_2937(WX8840,WX8839);
not NOT_2938(WX8844,WX8763);
not NOT_2939(WX8846,WX8845);
not NOT_2940(WX8847,WX8846);
not NOT_2941(WX8851,WX8763);
not NOT_2942(WX8853,WX8852);
not NOT_2943(WX8854,WX8853);
not NOT_2944(WX8858,WX8763);
not NOT_2945(WX8860,WX8859);
not NOT_2946(WX8861,WX8860);
not NOT_2947(WX8865,WX8763);
not NOT_2948(WX8867,WX8866);
not NOT_2949(WX8868,WX8867);
not NOT_2950(WX8872,WX8763);
not NOT_2951(WX8874,WX8873);
not NOT_2952(WX8875,WX8874);
not NOT_2953(WX8879,WX8763);
not NOT_2954(WX8881,WX8880);
not NOT_2955(WX8882,WX8881);
not NOT_2956(WX8886,WX8763);
not NOT_2957(WX8888,WX8887);
not NOT_2958(WX8889,WX8888);
not NOT_2959(WX8893,WX8763);
not NOT_2960(WX8895,WX8894);
not NOT_2961(WX8896,WX8895);
not NOT_2962(WX8900,WX8763);
not NOT_2963(WX8902,WX8901);
not NOT_2964(WX8903,WX8902);
not NOT_2965(WX8907,WX8763);
not NOT_2966(WX8909,WX8908);
not NOT_2967(WX8910,WX8909);
not NOT_2968(WX8914,WX8763);
not NOT_2969(WX8916,WX8915);
not NOT_2970(WX8917,WX8916);
not NOT_2971(WX8921,WX8763);
not NOT_2972(WX8923,WX8922);
not NOT_2973(WX8924,WX8923);
not NOT_2974(WX8928,WX8763);
not NOT_2975(WX8930,WX8929);
not NOT_2976(WX8931,WX8930);
not NOT_2977(WX8935,WX8763);
not NOT_2978(WX8937,WX8936);
not NOT_2979(WX8938,WX8937);
not NOT_2980(WX8942,WX8763);
not NOT_2981(WX8944,WX8943);
not NOT_2982(WX8945,WX8944);
not NOT_2983(WX8949,WX8763);
not NOT_2984(WX8951,WX8950);
not NOT_2985(WX8952,WX8951);
not NOT_2986(WX8956,WX8763);
not NOT_2987(WX8958,WX8957);
not NOT_2988(WX8959,WX8958);
not NOT_2989(WX8963,WX8763);
not NOT_2990(WX8965,WX8964);
not NOT_2991(WX8966,WX8965);
not NOT_2992(WX8970,WX8763);
not NOT_2993(WX8972,WX8971);
not NOT_2994(WX8973,WX8972);
not NOT_2995(WX8977,WX8763);
not NOT_2996(WX8979,WX8978);
not NOT_2997(WX8980,WX8979);
not NOT_2998(WX8984,WX8763);
not NOT_2999(WX8986,WX8985);
not NOT_3000(WX8987,WX8986);
not NOT_3001(WX8988,RESET);
not NOT_3002(WX9021,WX8988);
not NOT_3003(WX9088,WX10054);
not NOT_3004(WX9092,WX10055);
not NOT_3005(WX9096,WX10055);
not NOT_3006(WX9098,WX9089);
not NOT_3007(WX9099,WX9098);
not NOT_3008(WX9102,WX10054);
not NOT_3009(WX9106,WX10055);
not NOT_3010(WX9110,WX10055);
not NOT_3011(WX9112,WX9103);
not NOT_3012(WX9113,WX9112);
not NOT_3013(WX9116,WX10054);
not NOT_3014(WX9120,WX10055);
not NOT_3015(WX9124,WX10055);
not NOT_3016(WX9126,WX9117);
not NOT_3017(WX9127,WX9126);
not NOT_3018(WX9130,WX10054);
not NOT_3019(WX9134,WX10055);
not NOT_3020(WX9138,WX10055);
not NOT_3021(WX9140,WX9131);
not NOT_3022(WX9141,WX9140);
not NOT_3023(WX9144,WX10054);
not NOT_3024(WX9148,WX10055);
not NOT_3025(WX9152,WX10055);
not NOT_3026(WX9154,WX9145);
not NOT_3027(WX9155,WX9154);
not NOT_3028(WX9158,WX10054);
not NOT_3029(WX9162,WX10055);
not NOT_3030(WX9166,WX10055);
not NOT_3031(WX9168,WX9159);
not NOT_3032(WX9169,WX9168);
not NOT_3033(WX9172,WX10054);
not NOT_3034(WX9176,WX10055);
not NOT_3035(WX9180,WX10055);
not NOT_3036(WX9182,WX9173);
not NOT_3037(WX9183,WX9182);
not NOT_3038(WX9186,WX10054);
not NOT_3039(WX9190,WX10055);
not NOT_3040(WX9194,WX10055);
not NOT_3041(WX9196,WX9187);
not NOT_3042(WX9197,WX9196);
not NOT_3043(WX9200,WX10054);
not NOT_3044(WX9204,WX10055);
not NOT_3045(WX9208,WX10055);
not NOT_3046(WX9210,WX9201);
not NOT_3047(WX9211,WX9210);
not NOT_3048(WX9214,WX10054);
not NOT_3049(WX9218,WX10055);
not NOT_3050(WX9222,WX10055);
not NOT_3051(WX9224,WX9215);
not NOT_3052(WX9225,WX9224);
not NOT_3053(WX9228,WX10054);
not NOT_3054(WX9232,WX10055);
not NOT_3055(WX9236,WX10055);
not NOT_3056(WX9238,WX9229);
not NOT_3057(WX9239,WX9238);
not NOT_3058(WX9242,WX10054);
not NOT_3059(WX9246,WX10055);
not NOT_3060(WX9250,WX10055);
not NOT_3061(WX9252,WX9243);
not NOT_3062(WX9253,WX9252);
not NOT_3063(WX9256,WX10054);
not NOT_3064(WX9260,WX10055);
not NOT_3065(WX9264,WX10055);
not NOT_3066(WX9266,WX9257);
not NOT_3067(WX9267,WX9266);
not NOT_3068(WX9270,WX10054);
not NOT_3069(WX9274,WX10055);
not NOT_3070(WX9278,WX10055);
not NOT_3071(WX9280,WX9271);
not NOT_3072(WX9281,WX9280);
not NOT_3073(WX9284,WX10054);
not NOT_3074(WX9288,WX10055);
not NOT_3075(WX9292,WX10055);
not NOT_3076(WX9294,WX9285);
not NOT_3077(WX9295,WX9294);
not NOT_3078(WX9298,WX10054);
not NOT_3079(WX9302,WX10055);
not NOT_3080(WX9306,WX10055);
not NOT_3081(WX9308,WX9299);
not NOT_3082(WX9309,WX9308);
not NOT_3083(WX9312,WX10054);
not NOT_3084(WX9316,WX10055);
not NOT_3085(WX9320,WX10055);
not NOT_3086(WX9322,WX9313);
not NOT_3087(WX9323,WX9322);
not NOT_3088(WX9326,WX10054);
not NOT_3089(WX9330,WX10055);
not NOT_3090(WX9334,WX10055);
not NOT_3091(WX9336,WX9327);
not NOT_3092(WX9337,WX9336);
not NOT_3093(WX9340,WX10054);
not NOT_3094(WX9344,WX10055);
not NOT_3095(WX9348,WX10055);
not NOT_3096(WX9350,WX9341);
not NOT_3097(WX9351,WX9350);
not NOT_3098(WX9354,WX10054);
not NOT_3099(WX9358,WX10055);
not NOT_3100(WX9362,WX10055);
not NOT_3101(WX9364,WX9355);
not NOT_3102(WX9365,WX9364);
not NOT_3103(WX9368,WX10054);
not NOT_3104(WX9372,WX10055);
not NOT_3105(WX9376,WX10055);
not NOT_3106(WX9378,WX9369);
not NOT_3107(WX9379,WX9378);
not NOT_3108(WX9382,WX10054);
not NOT_3109(WX9386,WX10055);
not NOT_3110(WX9390,WX10055);
not NOT_3111(WX9392,WX9383);
not NOT_3112(WX9393,WX9392);
not NOT_3113(WX9396,WX10054);
not NOT_3114(WX9400,WX10055);
not NOT_3115(WX9404,WX10055);
not NOT_3116(WX9406,WX9397);
not NOT_3117(WX9407,WX9406);
not NOT_3118(WX9410,WX10054);
not NOT_3119(WX9414,WX10055);
not NOT_3120(WX9418,WX10055);
not NOT_3121(WX9420,WX9411);
not NOT_3122(WX9421,WX9420);
not NOT_3123(WX9424,WX10054);
not NOT_3124(WX9428,WX10055);
not NOT_3125(WX9432,WX10055);
not NOT_3126(WX9434,WX9425);
not NOT_3127(WX9435,WX9434);
not NOT_3128(WX9438,WX10054);
not NOT_3129(WX9442,WX10055);
not NOT_3130(WX9446,WX10055);
not NOT_3131(WX9448,WX9439);
not NOT_3132(WX9449,WX9448);
not NOT_3133(WX9452,WX10054);
not NOT_3134(WX9456,WX10055);
not NOT_3135(WX9460,WX10055);
not NOT_3136(WX9462,WX9453);
not NOT_3137(WX9463,WX9462);
not NOT_3138(WX9466,WX10054);
not NOT_3139(WX9470,WX10055);
not NOT_3140(WX9474,WX10055);
not NOT_3141(WX9476,WX9467);
not NOT_3142(WX9477,WX9476);
not NOT_3143(WX9480,WX10054);
not NOT_3144(WX9484,WX10055);
not NOT_3145(WX9488,WX10055);
not NOT_3146(WX9490,WX9481);
not NOT_3147(WX9491,WX9490);
not NOT_3148(WX9494,WX10054);
not NOT_3149(WX9498,WX10055);
not NOT_3150(WX9502,WX10055);
not NOT_3151(WX9504,WX9495);
not NOT_3152(WX9505,WX9504);
not NOT_3153(WX9508,WX10054);
not NOT_3154(WX9512,WX10055);
not NOT_3155(WX9516,WX10055);
not NOT_3156(WX9518,WX9509);
not NOT_3157(WX9519,WX9518);
not NOT_3158(WX9522,WX10054);
not NOT_3159(WX9526,WX10055);
not NOT_3160(WX9530,WX10055);
not NOT_3161(WX9532,WX9523);
not NOT_3162(WX9533,WX9532);
not NOT_3163(WX9534,WX9536);
not NOT_3164(WX9599,WX10016);
not NOT_3165(WX9600,WX10018);
not NOT_3166(WX9601,WX10020);
not NOT_3167(WX9602,WX10022);
not NOT_3168(WX9603,WX10024);
not NOT_3169(WX9604,WX10026);
not NOT_3170(WX9605,WX10028);
not NOT_3171(WX9606,WX10030);
not NOT_3172(WX9607,WX10032);
not NOT_3173(WX9608,WX10034);
not NOT_3174(WX9609,WX10036);
not NOT_3175(WX9610,WX10038);
not NOT_3176(WX9611,WX10040);
not NOT_3177(WX9612,WX10042);
not NOT_3178(WX9613,WX10044);
not NOT_3179(WX9614,WX10046);
not NOT_3180(WX9615,WX9984);
not NOT_3181(WX9616,WX9986);
not NOT_3182(WX9617,WX9988);
not NOT_3183(WX9618,WX9990);
not NOT_3184(WX9619,WX9992);
not NOT_3185(WX9620,WX9994);
not NOT_3186(WX9621,WX9996);
not NOT_3187(WX9622,WX9998);
not NOT_3188(WX9623,WX10000);
not NOT_3189(WX9624,WX10002);
not NOT_3190(WX9625,WX10004);
not NOT_3191(WX9626,WX10006);
not NOT_3192(WX9627,WX10008);
not NOT_3193(WX9628,WX10010);
not NOT_3194(WX9629,WX10012);
not NOT_3195(WX9630,WX10014);
not NOT_3196(WX9631,WX9599);
not NOT_3197(WX9632,WX9600);
not NOT_3198(WX9633,WX9601);
not NOT_3199(WX9634,WX9602);
not NOT_3200(WX9635,WX9603);
not NOT_3201(WX9636,WX9604);
not NOT_3202(WX9637,WX9605);
not NOT_3203(WX9638,WX9606);
not NOT_3204(WX9639,WX9607);
not NOT_3205(WX9640,WX9608);
not NOT_3206(WX9641,WX9609);
not NOT_3207(WX9642,WX9610);
not NOT_3208(WX9643,WX9611);
not NOT_3209(WX9644,WX9612);
not NOT_3210(WX9645,WX9613);
not NOT_3211(WX9646,WX9614);
not NOT_3212(WX9647,WX9615);
not NOT_3213(WX9648,WX9616);
not NOT_3214(WX9649,WX9617);
not NOT_3215(WX9650,WX9618);
not NOT_3216(WX9651,WX9619);
not NOT_3217(WX9652,WX9620);
not NOT_3218(WX9653,WX9621);
not NOT_3219(WX9654,WX9622);
not NOT_3220(WX9655,WX9623);
not NOT_3221(WX9656,WX9624);
not NOT_3222(WX9657,WX9625);
not NOT_3223(WX9658,WX9626);
not NOT_3224(WX9659,WX9627);
not NOT_3225(WX9660,WX9628);
not NOT_3226(WX9661,WX9629);
not NOT_3227(WX9662,WX9630);
not NOT_3228(WX9663,WX9888);
not NOT_3229(WX9664,WX9890);
not NOT_3230(WX9665,WX9892);
not NOT_3231(WX9666,WX9894);
not NOT_3232(WX9667,WX9896);
not NOT_3233(WX9668,WX9898);
not NOT_3234(WX9669,WX9900);
not NOT_3235(WX9670,WX9902);
not NOT_3236(WX9671,WX9904);
not NOT_3237(WX9672,WX9906);
not NOT_3238(WX9673,WX9908);
not NOT_3239(WX9674,WX9910);
not NOT_3240(WX9675,WX9912);
not NOT_3241(WX9676,WX9914);
not NOT_3242(WX9677,WX9916);
not NOT_3243(WX9678,WX9918);
not NOT_3244(WX9679,WX9920);
not NOT_3245(WX9680,WX9922);
not NOT_3246(WX9681,WX9924);
not NOT_3247(WX9682,WX9926);
not NOT_3248(WX9683,WX9928);
not NOT_3249(WX9684,WX9930);
not NOT_3250(WX9685,WX9932);
not NOT_3251(WX9686,WX9934);
not NOT_3252(WX9687,WX9936);
not NOT_3253(WX9688,WX9938);
not NOT_3254(WX9689,WX9940);
not NOT_3255(WX9690,WX9942);
not NOT_3256(WX9691,WX9944);
not NOT_3257(WX9692,WX9946);
not NOT_3258(WX9693,WX9948);
not NOT_3259(WX9694,WX9950);
not NOT_3260(WX9983,WX9967);
not NOT_3261(WX9984,WX9983);
not NOT_3262(WX9985,WX9968);
not NOT_3263(WX9986,WX9985);
not NOT_3264(WX9987,WX9969);
not NOT_3265(WX9988,WX9987);
not NOT_3266(WX9989,WX9970);
not NOT_3267(WX9990,WX9989);
not NOT_3268(WX9991,WX9971);
not NOT_3269(WX9992,WX9991);
not NOT_3270(WX9993,WX9972);
not NOT_3271(WX9994,WX9993);
not NOT_3272(WX9995,WX9973);
not NOT_3273(WX9996,WX9995);
not NOT_3274(WX9997,WX9974);
not NOT_3275(WX9998,WX9997);
not NOT_3276(WX9999,WX9975);
not NOT_3277(WX10000,WX9999);
not NOT_3278(WX10001,WX9976);
not NOT_3279(WX10002,WX10001);
not NOT_3280(WX10003,WX9977);
not NOT_3281(WX10004,WX10003);
not NOT_3282(WX10005,WX9978);
not NOT_3283(WX10006,WX10005);
not NOT_3284(WX10007,WX9979);
not NOT_3285(WX10008,WX10007);
not NOT_3286(WX10009,WX9980);
not NOT_3287(WX10010,WX10009);
not NOT_3288(WX10011,WX9981);
not NOT_3289(WX10012,WX10011);
not NOT_3290(WX10013,WX9982);
not NOT_3291(WX10014,WX10013);
not NOT_3292(WX10015,WX9951);
not NOT_3293(WX10016,WX10015);
not NOT_3294(WX10017,WX9952);
not NOT_3295(WX10018,WX10017);
not NOT_3296(WX10019,WX9953);
not NOT_3297(WX10020,WX10019);
not NOT_3298(WX10021,WX9954);
not NOT_3299(WX10022,WX10021);
not NOT_3300(WX10023,WX9955);
not NOT_3301(WX10024,WX10023);
not NOT_3302(WX10025,WX9956);
not NOT_3303(WX10026,WX10025);
not NOT_3304(WX10027,WX9957);
not NOT_3305(WX10028,WX10027);
not NOT_3306(WX10029,WX9958);
not NOT_3307(WX10030,WX10029);
not NOT_3308(WX10031,WX9959);
not NOT_3309(WX10032,WX10031);
not NOT_3310(WX10033,WX9960);
not NOT_3311(WX10034,WX10033);
not NOT_3312(WX10035,WX9961);
not NOT_3313(WX10036,WX10035);
not NOT_3314(WX10037,WX9962);
not NOT_3315(WX10038,WX10037);
not NOT_3316(WX10039,WX9963);
not NOT_3317(WX10040,WX10039);
not NOT_3318(WX10041,WX9964);
not NOT_3319(WX10042,WX10041);
not NOT_3320(WX10043,WX9965);
not NOT_3321(WX10044,WX10043);
not NOT_3322(WX10045,WX9966);
not NOT_3323(WX10046,WX10045);
not NOT_3324(WX10047,TM0);
not NOT_3325(WX10048,TM0);
not NOT_3326(WX10049,TM0);
not NOT_3327(WX10050,TM1);
not NOT_3328(WX10051,TM1);
not NOT_3329(WX10052,WX10051);
not NOT_3330(WX10053,WX10049);
not NOT_3331(WX10054,WX10050);
not NOT_3332(WX10055,WX10048);
not NOT_3333(WX10056,WX10047);
not NOT_3334(WX10060,WX10056);
not NOT_3335(WX10062,WX10061);
not NOT_3336(WX10063,WX10062);
not NOT_3337(WX10067,WX10056);
not NOT_3338(WX10069,WX10068);
not NOT_3339(WX10070,WX10069);
not NOT_3340(WX10074,WX10056);
not NOT_3341(WX10076,WX10075);
not NOT_3342(WX10077,WX10076);
not NOT_3343(WX10081,WX10056);
not NOT_3344(WX10083,WX10082);
not NOT_3345(WX10084,WX10083);
not NOT_3346(WX10088,WX10056);
not NOT_3347(WX10090,WX10089);
not NOT_3348(WX10091,WX10090);
not NOT_3349(WX10095,WX10056);
not NOT_3350(WX10097,WX10096);
not NOT_3351(WX10098,WX10097);
not NOT_3352(WX10102,WX10056);
not NOT_3353(WX10104,WX10103);
not NOT_3354(WX10105,WX10104);
not NOT_3355(WX10109,WX10056);
not NOT_3356(WX10111,WX10110);
not NOT_3357(WX10112,WX10111);
not NOT_3358(WX10116,WX10056);
not NOT_3359(WX10118,WX10117);
not NOT_3360(WX10119,WX10118);
not NOT_3361(WX10123,WX10056);
not NOT_3362(WX10125,WX10124);
not NOT_3363(WX10126,WX10125);
not NOT_3364(WX10130,WX10056);
not NOT_3365(WX10132,WX10131);
not NOT_3366(WX10133,WX10132);
not NOT_3367(WX10137,WX10056);
not NOT_3368(WX10139,WX10138);
not NOT_3369(WX10140,WX10139);
not NOT_3370(WX10144,WX10056);
not NOT_3371(WX10146,WX10145);
not NOT_3372(WX10147,WX10146);
not NOT_3373(WX10151,WX10056);
not NOT_3374(WX10153,WX10152);
not NOT_3375(WX10154,WX10153);
not NOT_3376(WX10158,WX10056);
not NOT_3377(WX10160,WX10159);
not NOT_3378(WX10161,WX10160);
not NOT_3379(WX10165,WX10056);
not NOT_3380(WX10167,WX10166);
not NOT_3381(WX10168,WX10167);
not NOT_3382(WX10172,WX10056);
not NOT_3383(WX10174,WX10173);
not NOT_3384(WX10175,WX10174);
not NOT_3385(WX10179,WX10056);
not NOT_3386(WX10181,WX10180);
not NOT_3387(WX10182,WX10181);
not NOT_3388(WX10186,WX10056);
not NOT_3389(WX10188,WX10187);
not NOT_3390(WX10189,WX10188);
not NOT_3391(WX10193,WX10056);
not NOT_3392(WX10195,WX10194);
not NOT_3393(WX10196,WX10195);
not NOT_3394(WX10200,WX10056);
not NOT_3395(WX10202,WX10201);
not NOT_3396(WX10203,WX10202);
not NOT_3397(WX10207,WX10056);
not NOT_3398(WX10209,WX10208);
not NOT_3399(WX10210,WX10209);
not NOT_3400(WX10214,WX10056);
not NOT_3401(WX10216,WX10215);
not NOT_3402(WX10217,WX10216);
not NOT_3403(WX10221,WX10056);
not NOT_3404(WX10223,WX10222);
not NOT_3405(WX10224,WX10223);
not NOT_3406(WX10228,WX10056);
not NOT_3407(WX10230,WX10229);
not NOT_3408(WX10231,WX10230);
not NOT_3409(WX10235,WX10056);
not NOT_3410(WX10237,WX10236);
not NOT_3411(WX10238,WX10237);
not NOT_3412(WX10242,WX10056);
not NOT_3413(WX10244,WX10243);
not NOT_3414(WX10245,WX10244);
not NOT_3415(WX10249,WX10056);
not NOT_3416(WX10251,WX10250);
not NOT_3417(WX10252,WX10251);
not NOT_3418(WX10256,WX10056);
not NOT_3419(WX10258,WX10257);
not NOT_3420(WX10259,WX10258);
not NOT_3421(WX10263,WX10056);
not NOT_3422(WX10265,WX10264);
not NOT_3423(WX10266,WX10265);
not NOT_3424(WX10270,WX10056);
not NOT_3425(WX10272,WX10271);
not NOT_3426(WX10273,WX10272);
not NOT_3427(WX10277,WX10056);
not NOT_3428(WX10279,WX10278);
not NOT_3429(WX10280,WX10279);
not NOT_3430(WX10281,RESET);
not NOT_3431(WX10314,WX10281);
not NOT_3432(WX10381,WX11347);
not NOT_3433(WX10385,WX11348);
not NOT_3434(WX10389,WX11348);
not NOT_3435(WX10391,WX10382);
not NOT_3436(WX10392,WX10391);
not NOT_3437(WX10395,WX11347);
not NOT_3438(WX10399,WX11348);
not NOT_3439(WX10403,WX11348);
not NOT_3440(WX10405,WX10396);
not NOT_3441(WX10406,WX10405);
not NOT_3442(WX10409,WX11347);
not NOT_3443(WX10413,WX11348);
not NOT_3444(WX10417,WX11348);
not NOT_3445(WX10419,WX10410);
not NOT_3446(WX10420,WX10419);
not NOT_3447(WX10423,WX11347);
not NOT_3448(WX10427,WX11348);
not NOT_3449(WX10431,WX11348);
not NOT_3450(WX10433,WX10424);
not NOT_3451(WX10434,WX10433);
not NOT_3452(WX10437,WX11347);
not NOT_3453(WX10441,WX11348);
not NOT_3454(WX10445,WX11348);
not NOT_3455(WX10447,WX10438);
not NOT_3456(WX10448,WX10447);
not NOT_3457(WX10451,WX11347);
not NOT_3458(WX10455,WX11348);
not NOT_3459(WX10459,WX11348);
not NOT_3460(WX10461,WX10452);
not NOT_3461(WX10462,WX10461);
not NOT_3462(WX10465,WX11347);
not NOT_3463(WX10469,WX11348);
not NOT_3464(WX10473,WX11348);
not NOT_3465(WX10475,WX10466);
not NOT_3466(WX10476,WX10475);
not NOT_3467(WX10479,WX11347);
not NOT_3468(WX10483,WX11348);
not NOT_3469(WX10487,WX11348);
not NOT_3470(WX10489,WX10480);
not NOT_3471(WX10490,WX10489);
not NOT_3472(WX10493,WX11347);
not NOT_3473(WX10497,WX11348);
not NOT_3474(WX10501,WX11348);
not NOT_3475(WX10503,WX10494);
not NOT_3476(WX10504,WX10503);
not NOT_3477(WX10507,WX11347);
not NOT_3478(WX10511,WX11348);
not NOT_3479(WX10515,WX11348);
not NOT_3480(WX10517,WX10508);
not NOT_3481(WX10518,WX10517);
not NOT_3482(WX10521,WX11347);
not NOT_3483(WX10525,WX11348);
not NOT_3484(WX10529,WX11348);
not NOT_3485(WX10531,WX10522);
not NOT_3486(WX10532,WX10531);
not NOT_3487(WX10535,WX11347);
not NOT_3488(WX10539,WX11348);
not NOT_3489(WX10543,WX11348);
not NOT_3490(WX10545,WX10536);
not NOT_3491(WX10546,WX10545);
not NOT_3492(WX10549,WX11347);
not NOT_3493(WX10553,WX11348);
not NOT_3494(WX10557,WX11348);
not NOT_3495(WX10559,WX10550);
not NOT_3496(WX10560,WX10559);
not NOT_3497(WX10563,WX11347);
not NOT_3498(WX10567,WX11348);
not NOT_3499(WX10571,WX11348);
not NOT_3500(WX10573,WX10564);
not NOT_3501(WX10574,WX10573);
not NOT_3502(WX10577,WX11347);
not NOT_3503(WX10581,WX11348);
not NOT_3504(WX10585,WX11348);
not NOT_3505(WX10587,WX10578);
not NOT_3506(WX10588,WX10587);
not NOT_3507(WX10591,WX11347);
not NOT_3508(WX10595,WX11348);
not NOT_3509(WX10599,WX11348);
not NOT_3510(WX10601,WX10592);
not NOT_3511(WX10602,WX10601);
not NOT_3512(WX10605,WX11347);
not NOT_3513(WX10609,WX11348);
not NOT_3514(WX10613,WX11348);
not NOT_3515(WX10615,WX10606);
not NOT_3516(WX10616,WX10615);
not NOT_3517(WX10619,WX11347);
not NOT_3518(WX10623,WX11348);
not NOT_3519(WX10627,WX11348);
not NOT_3520(WX10629,WX10620);
not NOT_3521(WX10630,WX10629);
not NOT_3522(WX10633,WX11347);
not NOT_3523(WX10637,WX11348);
not NOT_3524(WX10641,WX11348);
not NOT_3525(WX10643,WX10634);
not NOT_3526(WX10644,WX10643);
not NOT_3527(WX10647,WX11347);
not NOT_3528(WX10651,WX11348);
not NOT_3529(WX10655,WX11348);
not NOT_3530(WX10657,WX10648);
not NOT_3531(WX10658,WX10657);
not NOT_3532(WX10661,WX11347);
not NOT_3533(WX10665,WX11348);
not NOT_3534(WX10669,WX11348);
not NOT_3535(WX10671,WX10662);
not NOT_3536(WX10672,WX10671);
not NOT_3537(WX10675,WX11347);
not NOT_3538(WX10679,WX11348);
not NOT_3539(WX10683,WX11348);
not NOT_3540(WX10685,WX10676);
not NOT_3541(WX10686,WX10685);
not NOT_3542(WX10689,WX11347);
not NOT_3543(WX10693,WX11348);
not NOT_3544(WX10697,WX11348);
not NOT_3545(WX10699,WX10690);
not NOT_3546(WX10700,WX10699);
not NOT_3547(WX10703,WX11347);
not NOT_3548(WX10707,WX11348);
not NOT_3549(WX10711,WX11348);
not NOT_3550(WX10713,WX10704);
not NOT_3551(WX10714,WX10713);
not NOT_3552(WX10717,WX11347);
not NOT_3553(WX10721,WX11348);
not NOT_3554(WX10725,WX11348);
not NOT_3555(WX10727,WX10718);
not NOT_3556(WX10728,WX10727);
not NOT_3557(WX10731,WX11347);
not NOT_3558(WX10735,WX11348);
not NOT_3559(WX10739,WX11348);
not NOT_3560(WX10741,WX10732);
not NOT_3561(WX10742,WX10741);
not NOT_3562(WX10745,WX11347);
not NOT_3563(WX10749,WX11348);
not NOT_3564(WX10753,WX11348);
not NOT_3565(WX10755,WX10746);
not NOT_3566(WX10756,WX10755);
not NOT_3567(WX10759,WX11347);
not NOT_3568(WX10763,WX11348);
not NOT_3569(WX10767,WX11348);
not NOT_3570(WX10769,WX10760);
not NOT_3571(WX10770,WX10769);
not NOT_3572(WX10773,WX11347);
not NOT_3573(WX10777,WX11348);
not NOT_3574(WX10781,WX11348);
not NOT_3575(WX10783,WX10774);
not NOT_3576(WX10784,WX10783);
not NOT_3577(WX10787,WX11347);
not NOT_3578(WX10791,WX11348);
not NOT_3579(WX10795,WX11348);
not NOT_3580(WX10797,WX10788);
not NOT_3581(WX10798,WX10797);
not NOT_3582(WX10801,WX11347);
not NOT_3583(WX10805,WX11348);
not NOT_3584(WX10809,WX11348);
not NOT_3585(WX10811,WX10802);
not NOT_3586(WX10812,WX10811);
not NOT_3587(WX10815,WX11347);
not NOT_3588(WX10819,WX11348);
not NOT_3589(WX10823,WX11348);
not NOT_3590(WX10825,WX10816);
not NOT_3591(WX10826,WX10825);
not NOT_3592(WX10827,WX10829);
not NOT_3593(WX10892,WX11309);
not NOT_3594(WX10893,WX11311);
not NOT_3595(WX10894,WX11313);
not NOT_3596(WX10895,WX11315);
not NOT_3597(WX10896,WX11317);
not NOT_3598(WX10897,WX11319);
not NOT_3599(WX10898,WX11321);
not NOT_3600(WX10899,WX11323);
not NOT_3601(WX10900,WX11325);
not NOT_3602(WX10901,WX11327);
not NOT_3603(WX10902,WX11329);
not NOT_3604(WX10903,WX11331);
not NOT_3605(WX10904,WX11333);
not NOT_3606(WX10905,WX11335);
not NOT_3607(WX10906,WX11337);
not NOT_3608(WX10907,WX11339);
not NOT_3609(WX10908,WX11277);
not NOT_3610(WX10909,WX11279);
not NOT_3611(WX10910,WX11281);
not NOT_3612(WX10911,WX11283);
not NOT_3613(WX10912,WX11285);
not NOT_3614(WX10913,WX11287);
not NOT_3615(WX10914,WX11289);
not NOT_3616(WX10915,WX11291);
not NOT_3617(WX10916,WX11293);
not NOT_3618(WX10917,WX11295);
not NOT_3619(WX10918,WX11297);
not NOT_3620(WX10919,WX11299);
not NOT_3621(WX10920,WX11301);
not NOT_3622(WX10921,WX11303);
not NOT_3623(WX10922,WX11305);
not NOT_3624(WX10923,WX11307);
not NOT_3625(WX10924,WX10892);
not NOT_3626(WX10925,WX10893);
not NOT_3627(WX10926,WX10894);
not NOT_3628(WX10927,WX10895);
not NOT_3629(WX10928,WX10896);
not NOT_3630(WX10929,WX10897);
not NOT_3631(WX10930,WX10898);
not NOT_3632(WX10931,WX10899);
not NOT_3633(WX10932,WX10900);
not NOT_3634(WX10933,WX10901);
not NOT_3635(WX10934,WX10902);
not NOT_3636(WX10935,WX10903);
not NOT_3637(WX10936,WX10904);
not NOT_3638(WX10937,WX10905);
not NOT_3639(WX10938,WX10906);
not NOT_3640(WX10939,WX10907);
not NOT_3641(WX10940,WX10908);
not NOT_3642(WX10941,WX10909);
not NOT_3643(WX10942,WX10910);
not NOT_3644(WX10943,WX10911);
not NOT_3645(WX10944,WX10912);
not NOT_3646(WX10945,WX10913);
not NOT_3647(WX10946,WX10914);
not NOT_3648(WX10947,WX10915);
not NOT_3649(WX10948,WX10916);
not NOT_3650(WX10949,WX10917);
not NOT_3651(WX10950,WX10918);
not NOT_3652(WX10951,WX10919);
not NOT_3653(WX10952,WX10920);
not NOT_3654(WX10953,WX10921);
not NOT_3655(WX10954,WX10922);
not NOT_3656(WX10955,WX10923);
not NOT_3657(WX10956,WX11181);
not NOT_3658(WX10957,WX11183);
not NOT_3659(WX10958,WX11185);
not NOT_3660(WX10959,WX11187);
not NOT_3661(WX10960,WX11189);
not NOT_3662(WX10961,WX11191);
not NOT_3663(WX10962,WX11193);
not NOT_3664(WX10963,WX11195);
not NOT_3665(WX10964,WX11197);
not NOT_3666(WX10965,WX11199);
not NOT_3667(WX10966,WX11201);
not NOT_3668(WX10967,WX11203);
not NOT_3669(WX10968,WX11205);
not NOT_3670(WX10969,WX11207);
not NOT_3671(WX10970,WX11209);
not NOT_3672(WX10971,WX11211);
not NOT_3673(WX10972,WX11213);
not NOT_3674(WX10973,WX11215);
not NOT_3675(WX10974,WX11217);
not NOT_3676(WX10975,WX11219);
not NOT_3677(WX10976,WX11221);
not NOT_3678(WX10977,WX11223);
not NOT_3679(WX10978,WX11225);
not NOT_3680(WX10979,WX11227);
not NOT_3681(WX10980,WX11229);
not NOT_3682(WX10981,WX11231);
not NOT_3683(WX10982,WX11233);
not NOT_3684(WX10983,WX11235);
not NOT_3685(WX10984,WX11237);
not NOT_3686(WX10985,WX11239);
not NOT_3687(WX10986,WX11241);
not NOT_3688(WX10987,WX11243);
not NOT_3689(WX11276,WX11260);
not NOT_3690(WX11277,WX11276);
not NOT_3691(WX11278,WX11261);
not NOT_3692(WX11279,WX11278);
not NOT_3693(WX11280,WX11262);
not NOT_3694(WX11281,WX11280);
not NOT_3695(WX11282,WX11263);
not NOT_3696(WX11283,WX11282);
not NOT_3697(WX11284,WX11264);
not NOT_3698(WX11285,WX11284);
not NOT_3699(WX11286,WX11265);
not NOT_3700(WX11287,WX11286);
not NOT_3701(WX11288,WX11266);
not NOT_3702(WX11289,WX11288);
not NOT_3703(WX11290,WX11267);
not NOT_3704(WX11291,WX11290);
not NOT_3705(WX11292,WX11268);
not NOT_3706(WX11293,WX11292);
not NOT_3707(WX11294,WX11269);
not NOT_3708(WX11295,WX11294);
not NOT_3709(WX11296,WX11270);
not NOT_3710(WX11297,WX11296);
not NOT_3711(WX11298,WX11271);
not NOT_3712(WX11299,WX11298);
not NOT_3713(WX11300,WX11272);
not NOT_3714(WX11301,WX11300);
not NOT_3715(WX11302,WX11273);
not NOT_3716(WX11303,WX11302);
not NOT_3717(WX11304,WX11274);
not NOT_3718(WX11305,WX11304);
not NOT_3719(WX11306,WX11275);
not NOT_3720(WX11307,WX11306);
not NOT_3721(WX11308,WX11244);
not NOT_3722(WX11309,WX11308);
not NOT_3723(WX11310,WX11245);
not NOT_3724(WX11311,WX11310);
not NOT_3725(WX11312,WX11246);
not NOT_3726(WX11313,WX11312);
not NOT_3727(WX11314,WX11247);
not NOT_3728(WX11315,WX11314);
not NOT_3729(WX11316,WX11248);
not NOT_3730(WX11317,WX11316);
not NOT_3731(WX11318,WX11249);
not NOT_3732(WX11319,WX11318);
not NOT_3733(WX11320,WX11250);
not NOT_3734(WX11321,WX11320);
not NOT_3735(WX11322,WX11251);
not NOT_3736(WX11323,WX11322);
not NOT_3737(WX11324,WX11252);
not NOT_3738(WX11325,WX11324);
not NOT_3739(WX11326,WX11253);
not NOT_3740(WX11327,WX11326);
not NOT_3741(WX11328,WX11254);
not NOT_3742(WX11329,WX11328);
not NOT_3743(WX11330,WX11255);
not NOT_3744(WX11331,WX11330);
not NOT_3745(WX11332,WX11256);
not NOT_3746(WX11333,WX11332);
not NOT_3747(WX11334,WX11257);
not NOT_3748(WX11335,WX11334);
not NOT_3749(WX11336,WX11258);
not NOT_3750(WX11337,WX11336);
not NOT_3751(WX11338,WX11259);
not NOT_3752(WX11339,WX11338);
not NOT_3753(WX11340,TM0);
not NOT_3754(WX11341,TM0);
not NOT_3755(WX11342,TM0);
not NOT_3756(WX11343,TM1);
not NOT_3757(WX11344,TM1);
not NOT_3758(WX11345,WX11344);
not NOT_3759(WX11346,WX11342);
not NOT_3760(WX11347,WX11343);
not NOT_3761(WX11348,WX11341);
not NOT_3762(WX11349,WX11340);
not NOT_3763(WX11353,WX11349);
not NOT_3764(WX11355,WX11354);
not NOT_3765(WX11356,WX11355);
not NOT_3766(WX11360,WX11349);
not NOT_3767(WX11362,WX11361);
not NOT_3768(WX11363,WX11362);
not NOT_3769(WX11367,WX11349);
not NOT_3770(WX11369,WX11368);
not NOT_3771(WX11370,WX11369);
not NOT_3772(WX11374,WX11349);
not NOT_3773(WX11376,WX11375);
not NOT_3774(WX11377,WX11376);
not NOT_3775(WX11381,WX11349);
not NOT_3776(WX11383,WX11382);
not NOT_3777(WX11384,WX11383);
not NOT_3778(WX11388,WX11349);
not NOT_3779(WX11390,WX11389);
not NOT_3780(WX11391,WX11390);
not NOT_3781(WX11395,WX11349);
not NOT_3782(WX11397,WX11396);
not NOT_3783(WX11398,WX11397);
not NOT_3784(WX11402,WX11349);
not NOT_3785(WX11404,WX11403);
not NOT_3786(WX11405,WX11404);
not NOT_3787(WX11409,WX11349);
not NOT_3788(WX11411,WX11410);
not NOT_3789(WX11412,WX11411);
not NOT_3790(WX11416,WX11349);
not NOT_3791(WX11418,WX11417);
not NOT_3792(WX11419,WX11418);
not NOT_3793(WX11423,WX11349);
not NOT_3794(WX11425,WX11424);
not NOT_3795(WX11426,WX11425);
not NOT_3796(WX11430,WX11349);
not NOT_3797(WX11432,WX11431);
not NOT_3798(WX11433,WX11432);
not NOT_3799(WX11437,WX11349);
not NOT_3800(WX11439,WX11438);
not NOT_3801(WX11440,WX11439);
not NOT_3802(WX11444,WX11349);
not NOT_3803(WX11446,WX11445);
not NOT_3804(WX11447,WX11446);
not NOT_3805(WX11451,WX11349);
not NOT_3806(WX11453,WX11452);
not NOT_3807(WX11454,WX11453);
not NOT_3808(WX11458,WX11349);
not NOT_3809(WX11460,WX11459);
not NOT_3810(WX11461,WX11460);
not NOT_3811(WX11465,WX11349);
not NOT_3812(WX11467,WX11466);
not NOT_3813(WX11468,WX11467);
not NOT_3814(WX11472,WX11349);
not NOT_3815(WX11474,WX11473);
not NOT_3816(WX11475,WX11474);
not NOT_3817(WX11479,WX11349);
not NOT_3818(WX11481,WX11480);
not NOT_3819(WX11482,WX11481);
not NOT_3820(WX11486,WX11349);
not NOT_3821(WX11488,WX11487);
not NOT_3822(WX11489,WX11488);
not NOT_3823(WX11493,WX11349);
not NOT_3824(WX11495,WX11494);
not NOT_3825(WX11496,WX11495);
not NOT_3826(WX11500,WX11349);
not NOT_3827(WX11502,WX11501);
not NOT_3828(WX11503,WX11502);
not NOT_3829(WX11507,WX11349);
not NOT_3830(WX11509,WX11508);
not NOT_3831(WX11510,WX11509);
not NOT_3832(WX11514,WX11349);
not NOT_3833(WX11516,WX11515);
not NOT_3834(WX11517,WX11516);
not NOT_3835(WX11521,WX11349);
not NOT_3836(WX11523,WX11522);
not NOT_3837(WX11524,WX11523);
not NOT_3838(WX11528,WX11349);
not NOT_3839(WX11530,WX11529);
not NOT_3840(WX11531,WX11530);
not NOT_3841(WX11535,WX11349);
not NOT_3842(WX11537,WX11536);
not NOT_3843(WX11538,WX11537);
not NOT_3844(WX11542,WX11349);
not NOT_3845(WX11544,WX11543);
not NOT_3846(WX11545,WX11544);
not NOT_3847(WX11549,WX11349);
not NOT_3848(WX11551,WX11550);
not NOT_3849(WX11552,WX11551);
not NOT_3850(WX11556,WX11349);
not NOT_3851(WX11558,WX11557);
not NOT_3852(WX11559,WX11558);
not NOT_3853(WX11563,WX11349);
not NOT_3854(WX11565,WX11564);
not NOT_3855(WX11566,WX11565);
not NOT_3856(WX11570,WX11349);
not NOT_3857(WX11572,WX11571);
not NOT_3858(WX11573,WX11572);
not NOT_3859(WX11574,RESET);
not NOT_3860(WX11607,WX11574);
and AND2_0(WX35,WX46,WX1003);
and AND2_1(WX36,WX42,WX37);
and AND2_2(WX39,CRC_OUT_9_31,WX1004);
and AND2_3(WX40,WX2305,WX41);
and AND2_4(WX43,WX485,WX1004);
and AND2_5(WX44,DATA_9_31,WX45);
and AND2_6(WX49,WX60,WX1003);
and AND2_7(WX50,WX56,WX51);
and AND2_8(WX53,CRC_OUT_9_30,WX1004);
and AND2_9(WX54,WX2312,WX55);
and AND2_10(WX57,WX487,WX1004);
and AND2_11(WX58,DATA_9_30,WX59);
and AND2_12(WX63,WX74,WX1003);
and AND2_13(WX64,WX70,WX65);
and AND2_14(WX67,CRC_OUT_9_29,WX1004);
and AND2_15(WX68,WX2319,WX69);
and AND2_16(WX71,WX489,WX1004);
and AND2_17(WX72,DATA_9_29,WX73);
and AND2_18(WX77,WX88,WX1003);
and AND2_19(WX78,WX84,WX79);
and AND2_20(WX81,CRC_OUT_9_28,WX1004);
and AND2_21(WX82,WX2326,WX83);
and AND2_22(WX85,WX491,WX1004);
and AND2_23(WX86,DATA_9_28,WX87);
and AND2_24(WX91,WX102,WX1003);
and AND2_25(WX92,WX98,WX93);
and AND2_26(WX95,CRC_OUT_9_27,WX1004);
and AND2_27(WX96,WX2333,WX97);
and AND2_28(WX99,WX493,WX1004);
and AND2_29(WX100,DATA_9_27,WX101);
and AND2_30(WX105,WX116,WX1003);
and AND2_31(WX106,WX112,WX107);
and AND2_32(WX109,CRC_OUT_9_26,WX1004);
and AND2_33(WX110,WX2340,WX111);
and AND2_34(WX113,WX495,WX1004);
and AND2_35(WX114,DATA_9_26,WX115);
and AND2_36(WX119,WX130,WX1003);
and AND2_37(WX120,WX126,WX121);
and AND2_38(WX123,CRC_OUT_9_25,WX1004);
and AND2_39(WX124,WX2347,WX125);
and AND2_40(WX127,WX497,WX1004);
and AND2_41(WX128,DATA_9_25,WX129);
and AND2_42(WX133,WX144,WX1003);
and AND2_43(WX134,WX140,WX135);
and AND2_44(WX137,CRC_OUT_9_24,WX1004);
and AND2_45(WX138,WX2354,WX139);
and AND2_46(WX141,WX499,WX1004);
and AND2_47(WX142,DATA_9_24,WX143);
and AND2_48(WX147,WX158,WX1003);
and AND2_49(WX148,WX154,WX149);
and AND2_50(WX151,CRC_OUT_9_23,WX1004);
and AND2_51(WX152,WX2361,WX153);
and AND2_52(WX155,WX501,WX1004);
and AND2_53(WX156,DATA_9_23,WX157);
and AND2_54(WX161,WX172,WX1003);
and AND2_55(WX162,WX168,WX163);
and AND2_56(WX165,CRC_OUT_9_22,WX1004);
and AND2_57(WX166,WX2368,WX167);
and AND2_58(WX169,WX503,WX1004);
and AND2_59(WX170,DATA_9_22,WX171);
and AND2_60(WX175,WX186,WX1003);
and AND2_61(WX176,WX182,WX177);
and AND2_62(WX179,CRC_OUT_9_21,WX1004);
and AND2_63(WX180,WX2375,WX181);
and AND2_64(WX183,WX505,WX1004);
and AND2_65(WX184,DATA_9_21,WX185);
and AND2_66(WX189,WX200,WX1003);
and AND2_67(WX190,WX196,WX191);
and AND2_68(WX193,CRC_OUT_9_20,WX1004);
and AND2_69(WX194,WX2382,WX195);
and AND2_70(WX197,WX507,WX1004);
and AND2_71(WX198,DATA_9_20,WX199);
and AND2_72(WX203,WX214,WX1003);
and AND2_73(WX204,WX210,WX205);
and AND2_74(WX207,CRC_OUT_9_19,WX1004);
and AND2_75(WX208,WX2389,WX209);
and AND2_76(WX211,WX509,WX1004);
and AND2_77(WX212,DATA_9_19,WX213);
and AND2_78(WX217,WX228,WX1003);
and AND2_79(WX218,WX224,WX219);
and AND2_80(WX221,CRC_OUT_9_18,WX1004);
and AND2_81(WX222,WX2396,WX223);
and AND2_82(WX225,WX511,WX1004);
and AND2_83(WX226,DATA_9_18,WX227);
and AND2_84(WX231,WX242,WX1003);
and AND2_85(WX232,WX238,WX233);
and AND2_86(WX235,CRC_OUT_9_17,WX1004);
and AND2_87(WX236,WX2403,WX237);
and AND2_88(WX239,WX513,WX1004);
and AND2_89(WX240,DATA_9_17,WX241);
and AND2_90(WX245,WX256,WX1003);
and AND2_91(WX246,WX252,WX247);
and AND2_92(WX249,CRC_OUT_9_16,WX1004);
and AND2_93(WX250,WX2410,WX251);
and AND2_94(WX253,WX515,WX1004);
and AND2_95(WX254,DATA_9_16,WX255);
and AND2_96(WX259,WX270,WX1003);
and AND2_97(WX260,WX266,WX261);
and AND2_98(WX263,CRC_OUT_9_15,WX1004);
and AND2_99(WX264,WX2417,WX265);
and AND2_100(WX267,WX517,WX1004);
and AND2_101(WX268,DATA_9_15,WX269);
and AND2_102(WX273,WX284,WX1003);
and AND2_103(WX274,WX280,WX275);
and AND2_104(WX277,CRC_OUT_9_14,WX1004);
and AND2_105(WX278,WX2424,WX279);
and AND2_106(WX281,WX519,WX1004);
and AND2_107(WX282,DATA_9_14,WX283);
and AND2_108(WX287,WX298,WX1003);
and AND2_109(WX288,WX294,WX289);
and AND2_110(WX291,CRC_OUT_9_13,WX1004);
and AND2_111(WX292,WX2431,WX293);
and AND2_112(WX295,WX521,WX1004);
and AND2_113(WX296,DATA_9_13,WX297);
and AND2_114(WX301,WX312,WX1003);
and AND2_115(WX302,WX308,WX303);
and AND2_116(WX305,CRC_OUT_9_12,WX1004);
and AND2_117(WX306,WX2438,WX307);
and AND2_118(WX309,WX523,WX1004);
and AND2_119(WX310,DATA_9_12,WX311);
and AND2_120(WX315,WX326,WX1003);
and AND2_121(WX316,WX322,WX317);
and AND2_122(WX319,CRC_OUT_9_11,WX1004);
and AND2_123(WX320,WX2445,WX321);
and AND2_124(WX323,WX525,WX1004);
and AND2_125(WX324,DATA_9_11,WX325);
and AND2_126(WX329,WX340,WX1003);
and AND2_127(WX330,WX336,WX331);
and AND2_128(WX333,CRC_OUT_9_10,WX1004);
and AND2_129(WX334,WX2452,WX335);
and AND2_130(WX337,WX527,WX1004);
and AND2_131(WX338,DATA_9_10,WX339);
and AND2_132(WX343,WX354,WX1003);
and AND2_133(WX344,WX350,WX345);
and AND2_134(WX347,CRC_OUT_9_9,WX1004);
and AND2_135(WX348,WX2459,WX349);
and AND2_136(WX351,WX529,WX1004);
and AND2_137(WX352,DATA_9_9,WX353);
and AND2_138(WX357,WX368,WX1003);
and AND2_139(WX358,WX364,WX359);
and AND2_140(WX361,CRC_OUT_9_8,WX1004);
and AND2_141(WX362,WX2466,WX363);
and AND2_142(WX365,WX531,WX1004);
and AND2_143(WX366,DATA_9_8,WX367);
and AND2_144(WX371,WX382,WX1003);
and AND2_145(WX372,WX378,WX373);
and AND2_146(WX375,CRC_OUT_9_7,WX1004);
and AND2_147(WX376,WX2473,WX377);
and AND2_148(WX379,WX533,WX1004);
and AND2_149(WX380,DATA_9_7,WX381);
and AND2_150(WX385,WX396,WX1003);
and AND2_151(WX386,WX392,WX387);
and AND2_152(WX389,CRC_OUT_9_6,WX1004);
and AND2_153(WX390,WX2480,WX391);
and AND2_154(WX393,WX535,WX1004);
and AND2_155(WX394,DATA_9_6,WX395);
and AND2_156(WX399,WX410,WX1003);
and AND2_157(WX400,WX406,WX401);
and AND2_158(WX403,CRC_OUT_9_5,WX1004);
and AND2_159(WX404,WX2487,WX405);
and AND2_160(WX407,WX537,WX1004);
and AND2_161(WX408,DATA_9_5,WX409);
and AND2_162(WX413,WX424,WX1003);
and AND2_163(WX414,WX420,WX415);
and AND2_164(WX417,CRC_OUT_9_4,WX1004);
and AND2_165(WX418,WX2494,WX419);
and AND2_166(WX421,WX539,WX1004);
and AND2_167(WX422,DATA_9_4,WX423);
and AND2_168(WX427,WX438,WX1003);
and AND2_169(WX428,WX434,WX429);
and AND2_170(WX431,CRC_OUT_9_3,WX1004);
and AND2_171(WX432,WX2501,WX433);
and AND2_172(WX435,WX541,WX1004);
and AND2_173(WX436,DATA_9_3,WX437);
and AND2_174(WX441,WX452,WX1003);
and AND2_175(WX442,WX448,WX443);
and AND2_176(WX445,CRC_OUT_9_2,WX1004);
and AND2_177(WX446,WX2508,WX447);
and AND2_178(WX449,WX543,WX1004);
and AND2_179(WX450,DATA_9_2,WX451);
and AND2_180(WX455,WX466,WX1003);
and AND2_181(WX456,WX462,WX457);
and AND2_182(WX459,CRC_OUT_9_1,WX1004);
and AND2_183(WX460,WX2515,WX461);
and AND2_184(WX463,WX545,WX1004);
and AND2_185(WX464,DATA_9_1,WX465);
and AND2_186(WX469,WX480,WX1003);
and AND2_187(WX470,WX476,WX471);
and AND2_188(WX473,CRC_OUT_9_0,WX1004);
and AND2_189(WX474,WX2522,WX475);
and AND2_190(WX477,WX547,WX1004);
and AND2_191(WX478,DATA_9_0,WX479);
and AND2_192(WX484,WX487,RESET);
and AND2_193(WX486,WX489,RESET);
and AND2_194(WX488,WX491,RESET);
and AND2_195(WX490,WX493,RESET);
and AND2_196(WX492,WX495,RESET);
and AND2_197(WX494,WX497,RESET);
and AND2_198(WX496,WX499,RESET);
and AND2_199(WX498,WX501,RESET);
and AND2_200(WX500,WX503,RESET);
and AND2_201(WX502,WX505,RESET);
and AND2_202(WX504,WX507,RESET);
and AND2_203(WX506,WX509,RESET);
and AND2_204(WX508,WX511,RESET);
and AND2_205(WX510,WX513,RESET);
and AND2_206(WX512,WX515,RESET);
and AND2_207(WX514,WX517,RESET);
and AND2_208(WX516,WX519,RESET);
and AND2_209(WX518,WX521,RESET);
and AND2_210(WX520,WX523,RESET);
and AND2_211(WX522,WX525,RESET);
and AND2_212(WX524,WX527,RESET);
and AND2_213(WX526,WX529,RESET);
and AND2_214(WX528,WX531,RESET);
and AND2_215(WX530,WX533,RESET);
and AND2_216(WX532,WX535,RESET);
and AND2_217(WX534,WX537,RESET);
and AND2_218(WX536,WX539,RESET);
and AND2_219(WX538,WX541,RESET);
and AND2_220(WX540,WX543,RESET);
and AND2_221(WX542,WX545,RESET);
and AND2_222(WX544,WX547,RESET);
and AND2_223(WX546,WX483,RESET);
and AND2_224(WX644,WX48,RESET);
and AND2_225(WX646,WX62,RESET);
and AND2_226(WX648,WX76,RESET);
and AND2_227(WX650,WX90,RESET);
and AND2_228(WX652,WX104,RESET);
and AND2_229(WX654,WX118,RESET);
and AND2_230(WX656,WX132,RESET);
and AND2_231(WX658,WX146,RESET);
and AND2_232(WX660,WX160,RESET);
and AND2_233(WX662,WX174,RESET);
and AND2_234(WX664,WX188,RESET);
and AND2_235(WX666,WX202,RESET);
and AND2_236(WX668,WX216,RESET);
and AND2_237(WX670,WX230,RESET);
and AND2_238(WX672,WX244,RESET);
and AND2_239(WX674,WX258,RESET);
and AND2_240(WX676,WX272,RESET);
and AND2_241(WX678,WX286,RESET);
and AND2_242(WX680,WX300,RESET);
and AND2_243(WX682,WX314,RESET);
and AND2_244(WX684,WX328,RESET);
and AND2_245(WX686,WX342,RESET);
and AND2_246(WX688,WX356,RESET);
and AND2_247(WX690,WX370,RESET);
and AND2_248(WX692,WX384,RESET);
and AND2_249(WX694,WX398,RESET);
and AND2_250(WX696,WX412,RESET);
and AND2_251(WX698,WX426,RESET);
and AND2_252(WX700,WX440,RESET);
and AND2_253(WX702,WX454,RESET);
and AND2_254(WX704,WX468,RESET);
and AND2_255(WX706,WX482,RESET);
and AND2_256(WX708,WX645,RESET);
and AND2_257(WX710,WX647,RESET);
and AND2_258(WX712,WX649,RESET);
and AND2_259(WX714,WX651,RESET);
and AND2_260(WX716,WX653,RESET);
and AND2_261(WX718,WX655,RESET);
and AND2_262(WX720,WX657,RESET);
and AND2_263(WX722,WX659,RESET);
and AND2_264(WX724,WX661,RESET);
and AND2_265(WX726,WX663,RESET);
and AND2_266(WX728,WX665,RESET);
and AND2_267(WX730,WX667,RESET);
and AND2_268(WX732,WX669,RESET);
and AND2_269(WX734,WX671,RESET);
and AND2_270(WX736,WX673,RESET);
and AND2_271(WX738,WX675,RESET);
and AND2_272(WX740,WX677,RESET);
and AND2_273(WX742,WX679,RESET);
and AND2_274(WX744,WX681,RESET);
and AND2_275(WX746,WX683,RESET);
and AND2_276(WX748,WX685,RESET);
and AND2_277(WX750,WX687,RESET);
and AND2_278(WX752,WX689,RESET);
and AND2_279(WX754,WX691,RESET);
and AND2_280(WX756,WX693,RESET);
and AND2_281(WX758,WX695,RESET);
and AND2_282(WX760,WX697,RESET);
and AND2_283(WX762,WX699,RESET);
and AND2_284(WX764,WX701,RESET);
and AND2_285(WX766,WX703,RESET);
and AND2_286(WX768,WX705,RESET);
and AND2_287(WX770,WX707,RESET);
and AND2_288(WX772,WX709,RESET);
and AND2_289(WX774,WX711,RESET);
and AND2_290(WX776,WX713,RESET);
and AND2_291(WX778,WX715,RESET);
and AND2_292(WX780,WX717,RESET);
and AND2_293(WX782,WX719,RESET);
and AND2_294(WX784,WX721,RESET);
and AND2_295(WX786,WX723,RESET);
and AND2_296(WX788,WX725,RESET);
and AND2_297(WX790,WX727,RESET);
and AND2_298(WX792,WX729,RESET);
and AND2_299(WX794,WX731,RESET);
and AND2_300(WX796,WX733,RESET);
and AND2_301(WX798,WX735,RESET);
and AND2_302(WX800,WX737,RESET);
and AND2_303(WX802,WX739,RESET);
and AND2_304(WX804,WX741,RESET);
and AND2_305(WX806,WX743,RESET);
and AND2_306(WX808,WX745,RESET);
and AND2_307(WX810,WX747,RESET);
and AND2_308(WX812,WX749,RESET);
and AND2_309(WX814,WX751,RESET);
and AND2_310(WX816,WX753,RESET);
and AND2_311(WX818,WX755,RESET);
and AND2_312(WX820,WX757,RESET);
and AND2_313(WX822,WX759,RESET);
and AND2_314(WX824,WX761,RESET);
and AND2_315(WX826,WX763,RESET);
and AND2_316(WX828,WX765,RESET);
and AND2_317(WX830,WX767,RESET);
and AND2_318(WX832,WX769,RESET);
and AND2_319(WX834,WX771,RESET);
and AND2_320(WX836,WX773,RESET);
and AND2_321(WX838,WX775,RESET);
and AND2_322(WX840,WX777,RESET);
and AND2_323(WX842,WX779,RESET);
and AND2_324(WX844,WX781,RESET);
and AND2_325(WX846,WX783,RESET);
and AND2_326(WX848,WX785,RESET);
and AND2_327(WX850,WX787,RESET);
and AND2_328(WX852,WX789,RESET);
and AND2_329(WX854,WX791,RESET);
and AND2_330(WX856,WX793,RESET);
and AND2_331(WX858,WX795,RESET);
and AND2_332(WX860,WX797,RESET);
and AND2_333(WX862,WX799,RESET);
and AND2_334(WX864,WX801,RESET);
and AND2_335(WX866,WX803,RESET);
and AND2_336(WX868,WX805,RESET);
and AND2_337(WX870,WX807,RESET);
and AND2_338(WX872,WX809,RESET);
and AND2_339(WX874,WX811,RESET);
and AND2_340(WX876,WX813,RESET);
and AND2_341(WX878,WX815,RESET);
and AND2_342(WX880,WX817,RESET);
and AND2_343(WX882,WX819,RESET);
and AND2_344(WX884,WX821,RESET);
and AND2_345(WX886,WX823,RESET);
and AND2_346(WX888,WX825,RESET);
and AND2_347(WX890,WX827,RESET);
and AND2_348(WX892,WX829,RESET);
and AND2_349(WX894,WX831,RESET);
and AND2_350(WX896,WX833,RESET);
and AND2_351(WX898,WX835,RESET);
and AND2_352(WX1007,WX1006,WX1005);
and AND2_353(WX1008,WX580,WX1009);
and AND2_354(WX1014,WX1013,WX1005);
and AND2_355(WX1015,WX581,WX1016);
and AND2_356(WX1021,WX1020,WX1005);
and AND2_357(WX1022,WX582,WX1023);
and AND2_358(WX1028,WX1027,WX1005);
and AND2_359(WX1029,WX583,WX1030);
and AND2_360(WX1035,WX1034,WX1005);
and AND2_361(WX1036,WX584,WX1037);
and AND2_362(WX1042,WX1041,WX1005);
and AND2_363(WX1043,WX585,WX1044);
and AND2_364(WX1049,WX1048,WX1005);
and AND2_365(WX1050,WX586,WX1051);
and AND2_366(WX1056,WX1055,WX1005);
and AND2_367(WX1057,WX587,WX1058);
and AND2_368(WX1063,WX1062,WX1005);
and AND2_369(WX1064,WX588,WX1065);
and AND2_370(WX1070,WX1069,WX1005);
and AND2_371(WX1071,WX589,WX1072);
and AND2_372(WX1077,WX1076,WX1005);
and AND2_373(WX1078,WX590,WX1079);
and AND2_374(WX1084,WX1083,WX1005);
and AND2_375(WX1085,WX591,WX1086);
and AND2_376(WX1091,WX1090,WX1005);
and AND2_377(WX1092,WX592,WX1093);
and AND2_378(WX1098,WX1097,WX1005);
and AND2_379(WX1099,WX593,WX1100);
and AND2_380(WX1105,WX1104,WX1005);
and AND2_381(WX1106,WX594,WX1107);
and AND2_382(WX1112,WX1111,WX1005);
and AND2_383(WX1113,WX595,WX1114);
and AND2_384(WX1119,WX1118,WX1005);
and AND2_385(WX1120,WX596,WX1121);
and AND2_386(WX1126,WX1125,WX1005);
and AND2_387(WX1127,WX597,WX1128);
and AND2_388(WX1133,WX1132,WX1005);
and AND2_389(WX1134,WX598,WX1135);
and AND2_390(WX1140,WX1139,WX1005);
and AND2_391(WX1141,WX599,WX1142);
and AND2_392(WX1147,WX1146,WX1005);
and AND2_393(WX1148,WX600,WX1149);
and AND2_394(WX1154,WX1153,WX1005);
and AND2_395(WX1155,WX601,WX1156);
and AND2_396(WX1161,WX1160,WX1005);
and AND2_397(WX1162,WX602,WX1163);
and AND2_398(WX1168,WX1167,WX1005);
and AND2_399(WX1169,WX603,WX1170);
and AND2_400(WX1175,WX1174,WX1005);
and AND2_401(WX1176,WX604,WX1177);
and AND2_402(WX1182,WX1181,WX1005);
and AND2_403(WX1183,WX605,WX1184);
and AND2_404(WX1189,WX1188,WX1005);
and AND2_405(WX1190,WX606,WX1191);
and AND2_406(WX1196,WX1195,WX1005);
and AND2_407(WX1197,WX607,WX1198);
and AND2_408(WX1203,WX1202,WX1005);
and AND2_409(WX1204,WX608,WX1205);
and AND2_410(WX1210,WX1209,WX1005);
and AND2_411(WX1211,WX609,WX1212);
and AND2_412(WX1217,WX1216,WX1005);
and AND2_413(WX1218,WX610,WX1219);
and AND2_414(WX1224,WX1223,WX1005);
and AND2_415(WX1225,WX611,WX1226);
and AND2_416(WX1264,WX1234,WX1263);
and AND2_417(WX1266,WX1262,WX1263);
and AND2_418(WX1268,WX1261,WX1263);
and AND2_419(WX1270,WX1260,WX1263);
and AND2_420(WX1272,WX1233,WX1263);
and AND2_421(WX1274,WX1259,WX1263);
and AND2_422(WX1276,WX1258,WX1263);
and AND2_423(WX1278,WX1257,WX1263);
and AND2_424(WX1280,WX1256,WX1263);
and AND2_425(WX1282,WX1255,WX1263);
and AND2_426(WX1284,WX1254,WX1263);
and AND2_427(WX1286,WX1232,WX1263);
and AND2_428(WX1288,WX1253,WX1263);
and AND2_429(WX1290,WX1252,WX1263);
and AND2_430(WX1292,WX1251,WX1263);
and AND2_431(WX1294,WX1250,WX1263);
and AND2_432(WX1296,WX1231,WX1263);
and AND2_433(WX1298,WX1249,WX1263);
and AND2_434(WX1300,WX1248,WX1263);
and AND2_435(WX1302,WX1247,WX1263);
and AND2_436(WX1304,WX1246,WX1263);
and AND2_437(WX1306,WX1245,WX1263);
and AND2_438(WX1308,WX1244,WX1263);
and AND2_439(WX1310,WX1243,WX1263);
and AND2_440(WX1312,WX1242,WX1263);
and AND2_441(WX1314,WX1241,WX1263);
and AND2_442(WX1316,WX1240,WX1263);
and AND2_443(WX1318,WX1239,WX1263);
and AND2_444(WX1320,WX1238,WX1263);
and AND2_445(WX1322,WX1237,WX1263);
and AND2_446(WX1324,WX1236,WX1263);
and AND2_447(WX1326,WX1235,WX1263);
and AND2_448(WX1328,WX1339,WX2296);
and AND2_449(WX1329,WX1335,WX1330);
and AND2_450(WX1332,CRC_OUT_8_31,WX2297);
and AND2_451(WX1333,WX3598,WX1334);
and AND2_452(WX1336,WX1778,WX2297);
and AND2_453(WX1337,WX2305,WX1338);
and AND2_454(WX1342,WX1353,WX2296);
and AND2_455(WX1343,WX1349,WX1344);
and AND2_456(WX1346,CRC_OUT_8_30,WX2297);
and AND2_457(WX1347,WX3605,WX1348);
and AND2_458(WX1350,WX1780,WX2297);
and AND2_459(WX1351,WX2312,WX1352);
and AND2_460(WX1356,WX1367,WX2296);
and AND2_461(WX1357,WX1363,WX1358);
and AND2_462(WX1360,CRC_OUT_8_29,WX2297);
and AND2_463(WX1361,WX3612,WX1362);
and AND2_464(WX1364,WX1782,WX2297);
and AND2_465(WX1365,WX2319,WX1366);
and AND2_466(WX1370,WX1381,WX2296);
and AND2_467(WX1371,WX1377,WX1372);
and AND2_468(WX1374,CRC_OUT_8_28,WX2297);
and AND2_469(WX1375,WX3619,WX1376);
and AND2_470(WX1378,WX1784,WX2297);
and AND2_471(WX1379,WX2326,WX1380);
and AND2_472(WX1384,WX1395,WX2296);
and AND2_473(WX1385,WX1391,WX1386);
and AND2_474(WX1388,CRC_OUT_8_27,WX2297);
and AND2_475(WX1389,WX3626,WX1390);
and AND2_476(WX1392,WX1786,WX2297);
and AND2_477(WX1393,WX2333,WX1394);
and AND2_478(WX1398,WX1409,WX2296);
and AND2_479(WX1399,WX1405,WX1400);
and AND2_480(WX1402,CRC_OUT_8_26,WX2297);
and AND2_481(WX1403,WX3633,WX1404);
and AND2_482(WX1406,WX1788,WX2297);
and AND2_483(WX1407,WX2340,WX1408);
and AND2_484(WX1412,WX1423,WX2296);
and AND2_485(WX1413,WX1419,WX1414);
and AND2_486(WX1416,CRC_OUT_8_25,WX2297);
and AND2_487(WX1417,WX3640,WX1418);
and AND2_488(WX1420,WX1790,WX2297);
and AND2_489(WX1421,WX2347,WX1422);
and AND2_490(WX1426,WX1437,WX2296);
and AND2_491(WX1427,WX1433,WX1428);
and AND2_492(WX1430,CRC_OUT_8_24,WX2297);
and AND2_493(WX1431,WX3647,WX1432);
and AND2_494(WX1434,WX1792,WX2297);
and AND2_495(WX1435,WX2354,WX1436);
and AND2_496(WX1440,WX1451,WX2296);
and AND2_497(WX1441,WX1447,WX1442);
and AND2_498(WX1444,CRC_OUT_8_23,WX2297);
and AND2_499(WX1445,WX3654,WX1446);
and AND2_500(WX1448,WX1794,WX2297);
and AND2_501(WX1449,WX2361,WX1450);
and AND2_502(WX1454,WX1465,WX2296);
and AND2_503(WX1455,WX1461,WX1456);
and AND2_504(WX1458,CRC_OUT_8_22,WX2297);
and AND2_505(WX1459,WX3661,WX1460);
and AND2_506(WX1462,WX1796,WX2297);
and AND2_507(WX1463,WX2368,WX1464);
and AND2_508(WX1468,WX1479,WX2296);
and AND2_509(WX1469,WX1475,WX1470);
and AND2_510(WX1472,CRC_OUT_8_21,WX2297);
and AND2_511(WX1473,WX3668,WX1474);
and AND2_512(WX1476,WX1798,WX2297);
and AND2_513(WX1477,WX2375,WX1478);
and AND2_514(WX1482,WX1493,WX2296);
and AND2_515(WX1483,WX1489,WX1484);
and AND2_516(WX1486,CRC_OUT_8_20,WX2297);
and AND2_517(WX1487,WX3675,WX1488);
and AND2_518(WX1490,WX1800,WX2297);
and AND2_519(WX1491,WX2382,WX1492);
and AND2_520(WX1496,WX1507,WX2296);
and AND2_521(WX1497,WX1503,WX1498);
and AND2_522(WX1500,CRC_OUT_8_19,WX2297);
and AND2_523(WX1501,WX3682,WX1502);
and AND2_524(WX1504,WX1802,WX2297);
and AND2_525(WX1505,WX2389,WX1506);
and AND2_526(WX1510,WX1521,WX2296);
and AND2_527(WX1511,WX1517,WX1512);
and AND2_528(WX1514,CRC_OUT_8_18,WX2297);
and AND2_529(WX1515,WX3689,WX1516);
and AND2_530(WX1518,WX1804,WX2297);
and AND2_531(WX1519,WX2396,WX1520);
and AND2_532(WX1524,WX1535,WX2296);
and AND2_533(WX1525,WX1531,WX1526);
and AND2_534(WX1528,CRC_OUT_8_17,WX2297);
and AND2_535(WX1529,WX3696,WX1530);
and AND2_536(WX1532,WX1806,WX2297);
and AND2_537(WX1533,WX2403,WX1534);
and AND2_538(WX1538,WX1549,WX2296);
and AND2_539(WX1539,WX1545,WX1540);
and AND2_540(WX1542,CRC_OUT_8_16,WX2297);
and AND2_541(WX1543,WX3703,WX1544);
and AND2_542(WX1546,WX1808,WX2297);
and AND2_543(WX1547,WX2410,WX1548);
and AND2_544(WX1552,WX1563,WX2296);
and AND2_545(WX1553,WX1559,WX1554);
and AND2_546(WX1556,CRC_OUT_8_15,WX2297);
and AND2_547(WX1557,WX3710,WX1558);
and AND2_548(WX1560,WX1810,WX2297);
and AND2_549(WX1561,WX2417,WX1562);
and AND2_550(WX1566,WX1577,WX2296);
and AND2_551(WX1567,WX1573,WX1568);
and AND2_552(WX1570,CRC_OUT_8_14,WX2297);
and AND2_553(WX1571,WX3717,WX1572);
and AND2_554(WX1574,WX1812,WX2297);
and AND2_555(WX1575,WX2424,WX1576);
and AND2_556(WX1580,WX1591,WX2296);
and AND2_557(WX1581,WX1587,WX1582);
and AND2_558(WX1584,CRC_OUT_8_13,WX2297);
and AND2_559(WX1585,WX3724,WX1586);
and AND2_560(WX1588,WX1814,WX2297);
and AND2_561(WX1589,WX2431,WX1590);
and AND2_562(WX1594,WX1605,WX2296);
and AND2_563(WX1595,WX1601,WX1596);
and AND2_564(WX1598,CRC_OUT_8_12,WX2297);
and AND2_565(WX1599,WX3731,WX1600);
and AND2_566(WX1602,WX1816,WX2297);
and AND2_567(WX1603,WX2438,WX1604);
and AND2_568(WX1608,WX1619,WX2296);
and AND2_569(WX1609,WX1615,WX1610);
and AND2_570(WX1612,CRC_OUT_8_11,WX2297);
and AND2_571(WX1613,WX3738,WX1614);
and AND2_572(WX1616,WX1818,WX2297);
and AND2_573(WX1617,WX2445,WX1618);
and AND2_574(WX1622,WX1633,WX2296);
and AND2_575(WX1623,WX1629,WX1624);
and AND2_576(WX1626,CRC_OUT_8_10,WX2297);
and AND2_577(WX1627,WX3745,WX1628);
and AND2_578(WX1630,WX1820,WX2297);
and AND2_579(WX1631,WX2452,WX1632);
and AND2_580(WX1636,WX1647,WX2296);
and AND2_581(WX1637,WX1643,WX1638);
and AND2_582(WX1640,CRC_OUT_8_9,WX2297);
and AND2_583(WX1641,WX3752,WX1642);
and AND2_584(WX1644,WX1822,WX2297);
and AND2_585(WX1645,WX2459,WX1646);
and AND2_586(WX1650,WX1661,WX2296);
and AND2_587(WX1651,WX1657,WX1652);
and AND2_588(WX1654,CRC_OUT_8_8,WX2297);
and AND2_589(WX1655,WX3759,WX1656);
and AND2_590(WX1658,WX1824,WX2297);
and AND2_591(WX1659,WX2466,WX1660);
and AND2_592(WX1664,WX1675,WX2296);
and AND2_593(WX1665,WX1671,WX1666);
and AND2_594(WX1668,CRC_OUT_8_7,WX2297);
and AND2_595(WX1669,WX3766,WX1670);
and AND2_596(WX1672,WX1826,WX2297);
and AND2_597(WX1673,WX2473,WX1674);
and AND2_598(WX1678,WX1689,WX2296);
and AND2_599(WX1679,WX1685,WX1680);
and AND2_600(WX1682,CRC_OUT_8_6,WX2297);
and AND2_601(WX1683,WX3773,WX1684);
and AND2_602(WX1686,WX1828,WX2297);
and AND2_603(WX1687,WX2480,WX1688);
and AND2_604(WX1692,WX1703,WX2296);
and AND2_605(WX1693,WX1699,WX1694);
and AND2_606(WX1696,CRC_OUT_8_5,WX2297);
and AND2_607(WX1697,WX3780,WX1698);
and AND2_608(WX1700,WX1830,WX2297);
and AND2_609(WX1701,WX2487,WX1702);
and AND2_610(WX1706,WX1717,WX2296);
and AND2_611(WX1707,WX1713,WX1708);
and AND2_612(WX1710,CRC_OUT_8_4,WX2297);
and AND2_613(WX1711,WX3787,WX1712);
and AND2_614(WX1714,WX1832,WX2297);
and AND2_615(WX1715,WX2494,WX1716);
and AND2_616(WX1720,WX1731,WX2296);
and AND2_617(WX1721,WX1727,WX1722);
and AND2_618(WX1724,CRC_OUT_8_3,WX2297);
and AND2_619(WX1725,WX3794,WX1726);
and AND2_620(WX1728,WX1834,WX2297);
and AND2_621(WX1729,WX2501,WX1730);
and AND2_622(WX1734,WX1745,WX2296);
and AND2_623(WX1735,WX1741,WX1736);
and AND2_624(WX1738,CRC_OUT_8_2,WX2297);
and AND2_625(WX1739,WX3801,WX1740);
and AND2_626(WX1742,WX1836,WX2297);
and AND2_627(WX1743,WX2508,WX1744);
and AND2_628(WX1748,WX1759,WX2296);
and AND2_629(WX1749,WX1755,WX1750);
and AND2_630(WX1752,CRC_OUT_8_1,WX2297);
and AND2_631(WX1753,WX3808,WX1754);
and AND2_632(WX1756,WX1838,WX2297);
and AND2_633(WX1757,WX2515,WX1758);
and AND2_634(WX1762,WX1773,WX2296);
and AND2_635(WX1763,WX1769,WX1764);
and AND2_636(WX1766,CRC_OUT_8_0,WX2297);
and AND2_637(WX1767,WX3815,WX1768);
and AND2_638(WX1770,WX1840,WX2297);
and AND2_639(WX1771,WX2522,WX1772);
and AND2_640(WX1777,WX1780,RESET);
and AND2_641(WX1779,WX1782,RESET);
and AND2_642(WX1781,WX1784,RESET);
and AND2_643(WX1783,WX1786,RESET);
and AND2_644(WX1785,WX1788,RESET);
and AND2_645(WX1787,WX1790,RESET);
and AND2_646(WX1789,WX1792,RESET);
and AND2_647(WX1791,WX1794,RESET);
and AND2_648(WX1793,WX1796,RESET);
and AND2_649(WX1795,WX1798,RESET);
and AND2_650(WX1797,WX1800,RESET);
and AND2_651(WX1799,WX1802,RESET);
and AND2_652(WX1801,WX1804,RESET);
and AND2_653(WX1803,WX1806,RESET);
and AND2_654(WX1805,WX1808,RESET);
and AND2_655(WX1807,WX1810,RESET);
and AND2_656(WX1809,WX1812,RESET);
and AND2_657(WX1811,WX1814,RESET);
and AND2_658(WX1813,WX1816,RESET);
and AND2_659(WX1815,WX1818,RESET);
and AND2_660(WX1817,WX1820,RESET);
and AND2_661(WX1819,WX1822,RESET);
and AND2_662(WX1821,WX1824,RESET);
and AND2_663(WX1823,WX1826,RESET);
and AND2_664(WX1825,WX1828,RESET);
and AND2_665(WX1827,WX1830,RESET);
and AND2_666(WX1829,WX1832,RESET);
and AND2_667(WX1831,WX1834,RESET);
and AND2_668(WX1833,WX1836,RESET);
and AND2_669(WX1835,WX1838,RESET);
and AND2_670(WX1837,WX1840,RESET);
and AND2_671(WX1839,WX1776,RESET);
and AND2_672(WX1937,WX1341,RESET);
and AND2_673(WX1939,WX1355,RESET);
and AND2_674(WX1941,WX1369,RESET);
and AND2_675(WX1943,WX1383,RESET);
and AND2_676(WX1945,WX1397,RESET);
and AND2_677(WX1947,WX1411,RESET);
and AND2_678(WX1949,WX1425,RESET);
and AND2_679(WX1951,WX1439,RESET);
and AND2_680(WX1953,WX1453,RESET);
and AND2_681(WX1955,WX1467,RESET);
and AND2_682(WX1957,WX1481,RESET);
and AND2_683(WX1959,WX1495,RESET);
and AND2_684(WX1961,WX1509,RESET);
and AND2_685(WX1963,WX1523,RESET);
and AND2_686(WX1965,WX1537,RESET);
and AND2_687(WX1967,WX1551,RESET);
and AND2_688(WX1969,WX1565,RESET);
and AND2_689(WX1971,WX1579,RESET);
and AND2_690(WX1973,WX1593,RESET);
and AND2_691(WX1975,WX1607,RESET);
and AND2_692(WX1977,WX1621,RESET);
and AND2_693(WX1979,WX1635,RESET);
and AND2_694(WX1981,WX1649,RESET);
and AND2_695(WX1983,WX1663,RESET);
and AND2_696(WX1985,WX1677,RESET);
and AND2_697(WX1987,WX1691,RESET);
and AND2_698(WX1989,WX1705,RESET);
and AND2_699(WX1991,WX1719,RESET);
and AND2_700(WX1993,WX1733,RESET);
and AND2_701(WX1995,WX1747,RESET);
and AND2_702(WX1997,WX1761,RESET);
and AND2_703(WX1999,WX1775,RESET);
and AND2_704(WX2001,WX1938,RESET);
and AND2_705(WX2003,WX1940,RESET);
and AND2_706(WX2005,WX1942,RESET);
and AND2_707(WX2007,WX1944,RESET);
and AND2_708(WX2009,WX1946,RESET);
and AND2_709(WX2011,WX1948,RESET);
and AND2_710(WX2013,WX1950,RESET);
and AND2_711(WX2015,WX1952,RESET);
and AND2_712(WX2017,WX1954,RESET);
and AND2_713(WX2019,WX1956,RESET);
and AND2_714(WX2021,WX1958,RESET);
and AND2_715(WX2023,WX1960,RESET);
and AND2_716(WX2025,WX1962,RESET);
and AND2_717(WX2027,WX1964,RESET);
and AND2_718(WX2029,WX1966,RESET);
and AND2_719(WX2031,WX1968,RESET);
and AND2_720(WX2033,WX1970,RESET);
and AND2_721(WX2035,WX1972,RESET);
and AND2_722(WX2037,WX1974,RESET);
and AND2_723(WX2039,WX1976,RESET);
and AND2_724(WX2041,WX1978,RESET);
and AND2_725(WX2043,WX1980,RESET);
and AND2_726(WX2045,WX1982,RESET);
and AND2_727(WX2047,WX1984,RESET);
and AND2_728(WX2049,WX1986,RESET);
and AND2_729(WX2051,WX1988,RESET);
and AND2_730(WX2053,WX1990,RESET);
and AND2_731(WX2055,WX1992,RESET);
and AND2_732(WX2057,WX1994,RESET);
and AND2_733(WX2059,WX1996,RESET);
and AND2_734(WX2061,WX1998,RESET);
and AND2_735(WX2063,WX2000,RESET);
and AND2_736(WX2065,WX2002,RESET);
and AND2_737(WX2067,WX2004,RESET);
and AND2_738(WX2069,WX2006,RESET);
and AND2_739(WX2071,WX2008,RESET);
and AND2_740(WX2073,WX2010,RESET);
and AND2_741(WX2075,WX2012,RESET);
and AND2_742(WX2077,WX2014,RESET);
and AND2_743(WX2079,WX2016,RESET);
and AND2_744(WX2081,WX2018,RESET);
and AND2_745(WX2083,WX2020,RESET);
and AND2_746(WX2085,WX2022,RESET);
and AND2_747(WX2087,WX2024,RESET);
and AND2_748(WX2089,WX2026,RESET);
and AND2_749(WX2091,WX2028,RESET);
and AND2_750(WX2093,WX2030,RESET);
and AND2_751(WX2095,WX2032,RESET);
and AND2_752(WX2097,WX2034,RESET);
and AND2_753(WX2099,WX2036,RESET);
and AND2_754(WX2101,WX2038,RESET);
and AND2_755(WX2103,WX2040,RESET);
and AND2_756(WX2105,WX2042,RESET);
and AND2_757(WX2107,WX2044,RESET);
and AND2_758(WX2109,WX2046,RESET);
and AND2_759(WX2111,WX2048,RESET);
and AND2_760(WX2113,WX2050,RESET);
and AND2_761(WX2115,WX2052,RESET);
and AND2_762(WX2117,WX2054,RESET);
and AND2_763(WX2119,WX2056,RESET);
and AND2_764(WX2121,WX2058,RESET);
and AND2_765(WX2123,WX2060,RESET);
and AND2_766(WX2125,WX2062,RESET);
and AND2_767(WX2127,WX2064,RESET);
and AND2_768(WX2129,WX2066,RESET);
and AND2_769(WX2131,WX2068,RESET);
and AND2_770(WX2133,WX2070,RESET);
and AND2_771(WX2135,WX2072,RESET);
and AND2_772(WX2137,WX2074,RESET);
and AND2_773(WX2139,WX2076,RESET);
and AND2_774(WX2141,WX2078,RESET);
and AND2_775(WX2143,WX2080,RESET);
and AND2_776(WX2145,WX2082,RESET);
and AND2_777(WX2147,WX2084,RESET);
and AND2_778(WX2149,WX2086,RESET);
and AND2_779(WX2151,WX2088,RESET);
and AND2_780(WX2153,WX2090,RESET);
and AND2_781(WX2155,WX2092,RESET);
and AND2_782(WX2157,WX2094,RESET);
and AND2_783(WX2159,WX2096,RESET);
and AND2_784(WX2161,WX2098,RESET);
and AND2_785(WX2163,WX2100,RESET);
and AND2_786(WX2165,WX2102,RESET);
and AND2_787(WX2167,WX2104,RESET);
and AND2_788(WX2169,WX2106,RESET);
and AND2_789(WX2171,WX2108,RESET);
and AND2_790(WX2173,WX2110,RESET);
and AND2_791(WX2175,WX2112,RESET);
and AND2_792(WX2177,WX2114,RESET);
and AND2_793(WX2179,WX2116,RESET);
and AND2_794(WX2181,WX2118,RESET);
and AND2_795(WX2183,WX2120,RESET);
and AND2_796(WX2185,WX2122,RESET);
and AND2_797(WX2187,WX2124,RESET);
and AND2_798(WX2189,WX2126,RESET);
and AND2_799(WX2191,WX2128,RESET);
and AND2_800(WX2300,WX2299,WX2298);
and AND2_801(WX2301,WX1873,WX2302);
and AND2_802(WX2307,WX2306,WX2298);
and AND2_803(WX2308,WX1874,WX2309);
and AND2_804(WX2314,WX2313,WX2298);
and AND2_805(WX2315,WX1875,WX2316);
and AND2_806(WX2321,WX2320,WX2298);
and AND2_807(WX2322,WX1876,WX2323);
and AND2_808(WX2328,WX2327,WX2298);
and AND2_809(WX2329,WX1877,WX2330);
and AND2_810(WX2335,WX2334,WX2298);
and AND2_811(WX2336,WX1878,WX2337);
and AND2_812(WX2342,WX2341,WX2298);
and AND2_813(WX2343,WX1879,WX2344);
and AND2_814(WX2349,WX2348,WX2298);
and AND2_815(WX2350,WX1880,WX2351);
and AND2_816(WX2356,WX2355,WX2298);
and AND2_817(WX2357,WX1881,WX2358);
and AND2_818(WX2363,WX2362,WX2298);
and AND2_819(WX2364,WX1882,WX2365);
and AND2_820(WX2370,WX2369,WX2298);
and AND2_821(WX2371,WX1883,WX2372);
and AND2_822(WX2377,WX2376,WX2298);
and AND2_823(WX2378,WX1884,WX2379);
and AND2_824(WX2384,WX2383,WX2298);
and AND2_825(WX2385,WX1885,WX2386);
and AND2_826(WX2391,WX2390,WX2298);
and AND2_827(WX2392,WX1886,WX2393);
and AND2_828(WX2398,WX2397,WX2298);
and AND2_829(WX2399,WX1887,WX2400);
and AND2_830(WX2405,WX2404,WX2298);
and AND2_831(WX2406,WX1888,WX2407);
and AND2_832(WX2412,WX2411,WX2298);
and AND2_833(WX2413,WX1889,WX2414);
and AND2_834(WX2419,WX2418,WX2298);
and AND2_835(WX2420,WX1890,WX2421);
and AND2_836(WX2426,WX2425,WX2298);
and AND2_837(WX2427,WX1891,WX2428);
and AND2_838(WX2433,WX2432,WX2298);
and AND2_839(WX2434,WX1892,WX2435);
and AND2_840(WX2440,WX2439,WX2298);
and AND2_841(WX2441,WX1893,WX2442);
and AND2_842(WX2447,WX2446,WX2298);
and AND2_843(WX2448,WX1894,WX2449);
and AND2_844(WX2454,WX2453,WX2298);
and AND2_845(WX2455,WX1895,WX2456);
and AND2_846(WX2461,WX2460,WX2298);
and AND2_847(WX2462,WX1896,WX2463);
and AND2_848(WX2468,WX2467,WX2298);
and AND2_849(WX2469,WX1897,WX2470);
and AND2_850(WX2475,WX2474,WX2298);
and AND2_851(WX2476,WX1898,WX2477);
and AND2_852(WX2482,WX2481,WX2298);
and AND2_853(WX2483,WX1899,WX2484);
and AND2_854(WX2489,WX2488,WX2298);
and AND2_855(WX2490,WX1900,WX2491);
and AND2_856(WX2496,WX2495,WX2298);
and AND2_857(WX2497,WX1901,WX2498);
and AND2_858(WX2503,WX2502,WX2298);
and AND2_859(WX2504,WX1902,WX2505);
and AND2_860(WX2510,WX2509,WX2298);
and AND2_861(WX2511,WX1903,WX2512);
and AND2_862(WX2517,WX2516,WX2298);
and AND2_863(WX2518,WX1904,WX2519);
and AND2_864(WX2557,WX2527,WX2556);
and AND2_865(WX2559,WX2555,WX2556);
and AND2_866(WX2561,WX2554,WX2556);
and AND2_867(WX2563,WX2553,WX2556);
and AND2_868(WX2565,WX2526,WX2556);
and AND2_869(WX2567,WX2552,WX2556);
and AND2_870(WX2569,WX2551,WX2556);
and AND2_871(WX2571,WX2550,WX2556);
and AND2_872(WX2573,WX2549,WX2556);
and AND2_873(WX2575,WX2548,WX2556);
and AND2_874(WX2577,WX2547,WX2556);
and AND2_875(WX2579,WX2525,WX2556);
and AND2_876(WX2581,WX2546,WX2556);
and AND2_877(WX2583,WX2545,WX2556);
and AND2_878(WX2585,WX2544,WX2556);
and AND2_879(WX2587,WX2543,WX2556);
and AND2_880(WX2589,WX2524,WX2556);
and AND2_881(WX2591,WX2542,WX2556);
and AND2_882(WX2593,WX2541,WX2556);
and AND2_883(WX2595,WX2540,WX2556);
and AND2_884(WX2597,WX2539,WX2556);
and AND2_885(WX2599,WX2538,WX2556);
and AND2_886(WX2601,WX2537,WX2556);
and AND2_887(WX2603,WX2536,WX2556);
and AND2_888(WX2605,WX2535,WX2556);
and AND2_889(WX2607,WX2534,WX2556);
and AND2_890(WX2609,WX2533,WX2556);
and AND2_891(WX2611,WX2532,WX2556);
and AND2_892(WX2613,WX2531,WX2556);
and AND2_893(WX2615,WX2530,WX2556);
and AND2_894(WX2617,WX2529,WX2556);
and AND2_895(WX2619,WX2528,WX2556);
and AND2_896(WX2621,WX2632,WX3589);
and AND2_897(WX2622,WX2628,WX2623);
and AND2_898(WX2625,CRC_OUT_7_31,WX3590);
and AND2_899(WX2626,WX4891,WX2627);
and AND2_900(WX2629,WX3071,WX3590);
and AND2_901(WX2630,WX3598,WX2631);
and AND2_902(WX2635,WX2646,WX3589);
and AND2_903(WX2636,WX2642,WX2637);
and AND2_904(WX2639,CRC_OUT_7_30,WX3590);
and AND2_905(WX2640,WX4898,WX2641);
and AND2_906(WX2643,WX3073,WX3590);
and AND2_907(WX2644,WX3605,WX2645);
and AND2_908(WX2649,WX2660,WX3589);
and AND2_909(WX2650,WX2656,WX2651);
and AND2_910(WX2653,CRC_OUT_7_29,WX3590);
and AND2_911(WX2654,WX4905,WX2655);
and AND2_912(WX2657,WX3075,WX3590);
and AND2_913(WX2658,WX3612,WX2659);
and AND2_914(WX2663,WX2674,WX3589);
and AND2_915(WX2664,WX2670,WX2665);
and AND2_916(WX2667,CRC_OUT_7_28,WX3590);
and AND2_917(WX2668,WX4912,WX2669);
and AND2_918(WX2671,WX3077,WX3590);
and AND2_919(WX2672,WX3619,WX2673);
and AND2_920(WX2677,WX2688,WX3589);
and AND2_921(WX2678,WX2684,WX2679);
and AND2_922(WX2681,CRC_OUT_7_27,WX3590);
and AND2_923(WX2682,WX4919,WX2683);
and AND2_924(WX2685,WX3079,WX3590);
and AND2_925(WX2686,WX3626,WX2687);
and AND2_926(WX2691,WX2702,WX3589);
and AND2_927(WX2692,WX2698,WX2693);
and AND2_928(WX2695,CRC_OUT_7_26,WX3590);
and AND2_929(WX2696,WX4926,WX2697);
and AND2_930(WX2699,WX3081,WX3590);
and AND2_931(WX2700,WX3633,WX2701);
and AND2_932(WX2705,WX2716,WX3589);
and AND2_933(WX2706,WX2712,WX2707);
and AND2_934(WX2709,CRC_OUT_7_25,WX3590);
and AND2_935(WX2710,WX4933,WX2711);
and AND2_936(WX2713,WX3083,WX3590);
and AND2_937(WX2714,WX3640,WX2715);
and AND2_938(WX2719,WX2730,WX3589);
and AND2_939(WX2720,WX2726,WX2721);
and AND2_940(WX2723,CRC_OUT_7_24,WX3590);
and AND2_941(WX2724,WX4940,WX2725);
and AND2_942(WX2727,WX3085,WX3590);
and AND2_943(WX2728,WX3647,WX2729);
and AND2_944(WX2733,WX2744,WX3589);
and AND2_945(WX2734,WX2740,WX2735);
and AND2_946(WX2737,CRC_OUT_7_23,WX3590);
and AND2_947(WX2738,WX4947,WX2739);
and AND2_948(WX2741,WX3087,WX3590);
and AND2_949(WX2742,WX3654,WX2743);
and AND2_950(WX2747,WX2758,WX3589);
and AND2_951(WX2748,WX2754,WX2749);
and AND2_952(WX2751,CRC_OUT_7_22,WX3590);
and AND2_953(WX2752,WX4954,WX2753);
and AND2_954(WX2755,WX3089,WX3590);
and AND2_955(WX2756,WX3661,WX2757);
and AND2_956(WX2761,WX2772,WX3589);
and AND2_957(WX2762,WX2768,WX2763);
and AND2_958(WX2765,CRC_OUT_7_21,WX3590);
and AND2_959(WX2766,WX4961,WX2767);
and AND2_960(WX2769,WX3091,WX3590);
and AND2_961(WX2770,WX3668,WX2771);
and AND2_962(WX2775,WX2786,WX3589);
and AND2_963(WX2776,WX2782,WX2777);
and AND2_964(WX2779,CRC_OUT_7_20,WX3590);
and AND2_965(WX2780,WX4968,WX2781);
and AND2_966(WX2783,WX3093,WX3590);
and AND2_967(WX2784,WX3675,WX2785);
and AND2_968(WX2789,WX2800,WX3589);
and AND2_969(WX2790,WX2796,WX2791);
and AND2_970(WX2793,CRC_OUT_7_19,WX3590);
and AND2_971(WX2794,WX4975,WX2795);
and AND2_972(WX2797,WX3095,WX3590);
and AND2_973(WX2798,WX3682,WX2799);
and AND2_974(WX2803,WX2814,WX3589);
and AND2_975(WX2804,WX2810,WX2805);
and AND2_976(WX2807,CRC_OUT_7_18,WX3590);
and AND2_977(WX2808,WX4982,WX2809);
and AND2_978(WX2811,WX3097,WX3590);
and AND2_979(WX2812,WX3689,WX2813);
and AND2_980(WX2817,WX2828,WX3589);
and AND2_981(WX2818,WX2824,WX2819);
and AND2_982(WX2821,CRC_OUT_7_17,WX3590);
and AND2_983(WX2822,WX4989,WX2823);
and AND2_984(WX2825,WX3099,WX3590);
and AND2_985(WX2826,WX3696,WX2827);
and AND2_986(WX2831,WX2842,WX3589);
and AND2_987(WX2832,WX2838,WX2833);
and AND2_988(WX2835,CRC_OUT_7_16,WX3590);
and AND2_989(WX2836,WX4996,WX2837);
and AND2_990(WX2839,WX3101,WX3590);
and AND2_991(WX2840,WX3703,WX2841);
and AND2_992(WX2845,WX2856,WX3589);
and AND2_993(WX2846,WX2852,WX2847);
and AND2_994(WX2849,CRC_OUT_7_15,WX3590);
and AND2_995(WX2850,WX5003,WX2851);
and AND2_996(WX2853,WX3103,WX3590);
and AND2_997(WX2854,WX3710,WX2855);
and AND2_998(WX2859,WX2870,WX3589);
and AND2_999(WX2860,WX2866,WX2861);
and AND2_1000(WX2863,CRC_OUT_7_14,WX3590);
and AND2_1001(WX2864,WX5010,WX2865);
and AND2_1002(WX2867,WX3105,WX3590);
and AND2_1003(WX2868,WX3717,WX2869);
and AND2_1004(WX2873,WX2884,WX3589);
and AND2_1005(WX2874,WX2880,WX2875);
and AND2_1006(WX2877,CRC_OUT_7_13,WX3590);
and AND2_1007(WX2878,WX5017,WX2879);
and AND2_1008(WX2881,WX3107,WX3590);
and AND2_1009(WX2882,WX3724,WX2883);
and AND2_1010(WX2887,WX2898,WX3589);
and AND2_1011(WX2888,WX2894,WX2889);
and AND2_1012(WX2891,CRC_OUT_7_12,WX3590);
and AND2_1013(WX2892,WX5024,WX2893);
and AND2_1014(WX2895,WX3109,WX3590);
and AND2_1015(WX2896,WX3731,WX2897);
and AND2_1016(WX2901,WX2912,WX3589);
and AND2_1017(WX2902,WX2908,WX2903);
and AND2_1018(WX2905,CRC_OUT_7_11,WX3590);
and AND2_1019(WX2906,WX5031,WX2907);
and AND2_1020(WX2909,WX3111,WX3590);
and AND2_1021(WX2910,WX3738,WX2911);
and AND2_1022(WX2915,WX2926,WX3589);
and AND2_1023(WX2916,WX2922,WX2917);
and AND2_1024(WX2919,CRC_OUT_7_10,WX3590);
and AND2_1025(WX2920,WX5038,WX2921);
and AND2_1026(WX2923,WX3113,WX3590);
and AND2_1027(WX2924,WX3745,WX2925);
and AND2_1028(WX2929,WX2940,WX3589);
and AND2_1029(WX2930,WX2936,WX2931);
and AND2_1030(WX2933,CRC_OUT_7_9,WX3590);
and AND2_1031(WX2934,WX5045,WX2935);
and AND2_1032(WX2937,WX3115,WX3590);
and AND2_1033(WX2938,WX3752,WX2939);
and AND2_1034(WX2943,WX2954,WX3589);
and AND2_1035(WX2944,WX2950,WX2945);
and AND2_1036(WX2947,CRC_OUT_7_8,WX3590);
and AND2_1037(WX2948,WX5052,WX2949);
and AND2_1038(WX2951,WX3117,WX3590);
and AND2_1039(WX2952,WX3759,WX2953);
and AND2_1040(WX2957,WX2968,WX3589);
and AND2_1041(WX2958,WX2964,WX2959);
and AND2_1042(WX2961,CRC_OUT_7_7,WX3590);
and AND2_1043(WX2962,WX5059,WX2963);
and AND2_1044(WX2965,WX3119,WX3590);
and AND2_1045(WX2966,WX3766,WX2967);
and AND2_1046(WX2971,WX2982,WX3589);
and AND2_1047(WX2972,WX2978,WX2973);
and AND2_1048(WX2975,CRC_OUT_7_6,WX3590);
and AND2_1049(WX2976,WX5066,WX2977);
and AND2_1050(WX2979,WX3121,WX3590);
and AND2_1051(WX2980,WX3773,WX2981);
and AND2_1052(WX2985,WX2996,WX3589);
and AND2_1053(WX2986,WX2992,WX2987);
and AND2_1054(WX2989,CRC_OUT_7_5,WX3590);
and AND2_1055(WX2990,WX5073,WX2991);
and AND2_1056(WX2993,WX3123,WX3590);
and AND2_1057(WX2994,WX3780,WX2995);
and AND2_1058(WX2999,WX3010,WX3589);
and AND2_1059(WX3000,WX3006,WX3001);
and AND2_1060(WX3003,CRC_OUT_7_4,WX3590);
and AND2_1061(WX3004,WX5080,WX3005);
and AND2_1062(WX3007,WX3125,WX3590);
and AND2_1063(WX3008,WX3787,WX3009);
and AND2_1064(WX3013,WX3024,WX3589);
and AND2_1065(WX3014,WX3020,WX3015);
and AND2_1066(WX3017,CRC_OUT_7_3,WX3590);
and AND2_1067(WX3018,WX5087,WX3019);
and AND2_1068(WX3021,WX3127,WX3590);
and AND2_1069(WX3022,WX3794,WX3023);
and AND2_1070(WX3027,WX3038,WX3589);
and AND2_1071(WX3028,WX3034,WX3029);
and AND2_1072(WX3031,CRC_OUT_7_2,WX3590);
and AND2_1073(WX3032,WX5094,WX3033);
and AND2_1074(WX3035,WX3129,WX3590);
and AND2_1075(WX3036,WX3801,WX3037);
and AND2_1076(WX3041,WX3052,WX3589);
and AND2_1077(WX3042,WX3048,WX3043);
and AND2_1078(WX3045,CRC_OUT_7_1,WX3590);
and AND2_1079(WX3046,WX5101,WX3047);
and AND2_1080(WX3049,WX3131,WX3590);
and AND2_1081(WX3050,WX3808,WX3051);
and AND2_1082(WX3055,WX3066,WX3589);
and AND2_1083(WX3056,WX3062,WX3057);
and AND2_1084(WX3059,CRC_OUT_7_0,WX3590);
and AND2_1085(WX3060,WX5108,WX3061);
and AND2_1086(WX3063,WX3133,WX3590);
and AND2_1087(WX3064,WX3815,WX3065);
and AND2_1088(WX3070,WX3073,RESET);
and AND2_1089(WX3072,WX3075,RESET);
and AND2_1090(WX3074,WX3077,RESET);
and AND2_1091(WX3076,WX3079,RESET);
and AND2_1092(WX3078,WX3081,RESET);
and AND2_1093(WX3080,WX3083,RESET);
and AND2_1094(WX3082,WX3085,RESET);
and AND2_1095(WX3084,WX3087,RESET);
and AND2_1096(WX3086,WX3089,RESET);
and AND2_1097(WX3088,WX3091,RESET);
and AND2_1098(WX3090,WX3093,RESET);
and AND2_1099(WX3092,WX3095,RESET);
and AND2_1100(WX3094,WX3097,RESET);
and AND2_1101(WX3096,WX3099,RESET);
and AND2_1102(WX3098,WX3101,RESET);
and AND2_1103(WX3100,WX3103,RESET);
and AND2_1104(WX3102,WX3105,RESET);
and AND2_1105(WX3104,WX3107,RESET);
and AND2_1106(WX3106,WX3109,RESET);
and AND2_1107(WX3108,WX3111,RESET);
and AND2_1108(WX3110,WX3113,RESET);
and AND2_1109(WX3112,WX3115,RESET);
and AND2_1110(WX3114,WX3117,RESET);
and AND2_1111(WX3116,WX3119,RESET);
and AND2_1112(WX3118,WX3121,RESET);
and AND2_1113(WX3120,WX3123,RESET);
and AND2_1114(WX3122,WX3125,RESET);
and AND2_1115(WX3124,WX3127,RESET);
and AND2_1116(WX3126,WX3129,RESET);
and AND2_1117(WX3128,WX3131,RESET);
and AND2_1118(WX3130,WX3133,RESET);
and AND2_1119(WX3132,WX3069,RESET);
and AND2_1120(WX3230,WX2634,RESET);
and AND2_1121(WX3232,WX2648,RESET);
and AND2_1122(WX3234,WX2662,RESET);
and AND2_1123(WX3236,WX2676,RESET);
and AND2_1124(WX3238,WX2690,RESET);
and AND2_1125(WX3240,WX2704,RESET);
and AND2_1126(WX3242,WX2718,RESET);
and AND2_1127(WX3244,WX2732,RESET);
and AND2_1128(WX3246,WX2746,RESET);
and AND2_1129(WX3248,WX2760,RESET);
and AND2_1130(WX3250,WX2774,RESET);
and AND2_1131(WX3252,WX2788,RESET);
and AND2_1132(WX3254,WX2802,RESET);
and AND2_1133(WX3256,WX2816,RESET);
and AND2_1134(WX3258,WX2830,RESET);
and AND2_1135(WX3260,WX2844,RESET);
and AND2_1136(WX3262,WX2858,RESET);
and AND2_1137(WX3264,WX2872,RESET);
and AND2_1138(WX3266,WX2886,RESET);
and AND2_1139(WX3268,WX2900,RESET);
and AND2_1140(WX3270,WX2914,RESET);
and AND2_1141(WX3272,WX2928,RESET);
and AND2_1142(WX3274,WX2942,RESET);
and AND2_1143(WX3276,WX2956,RESET);
and AND2_1144(WX3278,WX2970,RESET);
and AND2_1145(WX3280,WX2984,RESET);
and AND2_1146(WX3282,WX2998,RESET);
and AND2_1147(WX3284,WX3012,RESET);
and AND2_1148(WX3286,WX3026,RESET);
and AND2_1149(WX3288,WX3040,RESET);
and AND2_1150(WX3290,WX3054,RESET);
and AND2_1151(WX3292,WX3068,RESET);
and AND2_1152(WX3294,WX3231,RESET);
and AND2_1153(WX3296,WX3233,RESET);
and AND2_1154(WX3298,WX3235,RESET);
and AND2_1155(WX3300,WX3237,RESET);
and AND2_1156(WX3302,WX3239,RESET);
and AND2_1157(WX3304,WX3241,RESET);
and AND2_1158(WX3306,WX3243,RESET);
and AND2_1159(WX3308,WX3245,RESET);
and AND2_1160(WX3310,WX3247,RESET);
and AND2_1161(WX3312,WX3249,RESET);
and AND2_1162(WX3314,WX3251,RESET);
and AND2_1163(WX3316,WX3253,RESET);
and AND2_1164(WX3318,WX3255,RESET);
and AND2_1165(WX3320,WX3257,RESET);
and AND2_1166(WX3322,WX3259,RESET);
and AND2_1167(WX3324,WX3261,RESET);
and AND2_1168(WX3326,WX3263,RESET);
and AND2_1169(WX3328,WX3265,RESET);
and AND2_1170(WX3330,WX3267,RESET);
and AND2_1171(WX3332,WX3269,RESET);
and AND2_1172(WX3334,WX3271,RESET);
and AND2_1173(WX3336,WX3273,RESET);
and AND2_1174(WX3338,WX3275,RESET);
and AND2_1175(WX3340,WX3277,RESET);
and AND2_1176(WX3342,WX3279,RESET);
and AND2_1177(WX3344,WX3281,RESET);
and AND2_1178(WX3346,WX3283,RESET);
and AND2_1179(WX3348,WX3285,RESET);
and AND2_1180(WX3350,WX3287,RESET);
and AND2_1181(WX3352,WX3289,RESET);
and AND2_1182(WX3354,WX3291,RESET);
and AND2_1183(WX3356,WX3293,RESET);
and AND2_1184(WX3358,WX3295,RESET);
and AND2_1185(WX3360,WX3297,RESET);
and AND2_1186(WX3362,WX3299,RESET);
and AND2_1187(WX3364,WX3301,RESET);
and AND2_1188(WX3366,WX3303,RESET);
and AND2_1189(WX3368,WX3305,RESET);
and AND2_1190(WX3370,WX3307,RESET);
and AND2_1191(WX3372,WX3309,RESET);
and AND2_1192(WX3374,WX3311,RESET);
and AND2_1193(WX3376,WX3313,RESET);
and AND2_1194(WX3378,WX3315,RESET);
and AND2_1195(WX3380,WX3317,RESET);
and AND2_1196(WX3382,WX3319,RESET);
and AND2_1197(WX3384,WX3321,RESET);
and AND2_1198(WX3386,WX3323,RESET);
and AND2_1199(WX3388,WX3325,RESET);
and AND2_1200(WX3390,WX3327,RESET);
and AND2_1201(WX3392,WX3329,RESET);
and AND2_1202(WX3394,WX3331,RESET);
and AND2_1203(WX3396,WX3333,RESET);
and AND2_1204(WX3398,WX3335,RESET);
and AND2_1205(WX3400,WX3337,RESET);
and AND2_1206(WX3402,WX3339,RESET);
and AND2_1207(WX3404,WX3341,RESET);
and AND2_1208(WX3406,WX3343,RESET);
and AND2_1209(WX3408,WX3345,RESET);
and AND2_1210(WX3410,WX3347,RESET);
and AND2_1211(WX3412,WX3349,RESET);
and AND2_1212(WX3414,WX3351,RESET);
and AND2_1213(WX3416,WX3353,RESET);
and AND2_1214(WX3418,WX3355,RESET);
and AND2_1215(WX3420,WX3357,RESET);
and AND2_1216(WX3422,WX3359,RESET);
and AND2_1217(WX3424,WX3361,RESET);
and AND2_1218(WX3426,WX3363,RESET);
and AND2_1219(WX3428,WX3365,RESET);
and AND2_1220(WX3430,WX3367,RESET);
and AND2_1221(WX3432,WX3369,RESET);
and AND2_1222(WX3434,WX3371,RESET);
and AND2_1223(WX3436,WX3373,RESET);
and AND2_1224(WX3438,WX3375,RESET);
and AND2_1225(WX3440,WX3377,RESET);
and AND2_1226(WX3442,WX3379,RESET);
and AND2_1227(WX3444,WX3381,RESET);
and AND2_1228(WX3446,WX3383,RESET);
and AND2_1229(WX3448,WX3385,RESET);
and AND2_1230(WX3450,WX3387,RESET);
and AND2_1231(WX3452,WX3389,RESET);
and AND2_1232(WX3454,WX3391,RESET);
and AND2_1233(WX3456,WX3393,RESET);
and AND2_1234(WX3458,WX3395,RESET);
and AND2_1235(WX3460,WX3397,RESET);
and AND2_1236(WX3462,WX3399,RESET);
and AND2_1237(WX3464,WX3401,RESET);
and AND2_1238(WX3466,WX3403,RESET);
and AND2_1239(WX3468,WX3405,RESET);
and AND2_1240(WX3470,WX3407,RESET);
and AND2_1241(WX3472,WX3409,RESET);
and AND2_1242(WX3474,WX3411,RESET);
and AND2_1243(WX3476,WX3413,RESET);
and AND2_1244(WX3478,WX3415,RESET);
and AND2_1245(WX3480,WX3417,RESET);
and AND2_1246(WX3482,WX3419,RESET);
and AND2_1247(WX3484,WX3421,RESET);
and AND2_1248(WX3593,WX3592,WX3591);
and AND2_1249(WX3594,WX3166,WX3595);
and AND2_1250(WX3600,WX3599,WX3591);
and AND2_1251(WX3601,WX3167,WX3602);
and AND2_1252(WX3607,WX3606,WX3591);
and AND2_1253(WX3608,WX3168,WX3609);
and AND2_1254(WX3614,WX3613,WX3591);
and AND2_1255(WX3615,WX3169,WX3616);
and AND2_1256(WX3621,WX3620,WX3591);
and AND2_1257(WX3622,WX3170,WX3623);
and AND2_1258(WX3628,WX3627,WX3591);
and AND2_1259(WX3629,WX3171,WX3630);
and AND2_1260(WX3635,WX3634,WX3591);
and AND2_1261(WX3636,WX3172,WX3637);
and AND2_1262(WX3642,WX3641,WX3591);
and AND2_1263(WX3643,WX3173,WX3644);
and AND2_1264(WX3649,WX3648,WX3591);
and AND2_1265(WX3650,WX3174,WX3651);
and AND2_1266(WX3656,WX3655,WX3591);
and AND2_1267(WX3657,WX3175,WX3658);
and AND2_1268(WX3663,WX3662,WX3591);
and AND2_1269(WX3664,WX3176,WX3665);
and AND2_1270(WX3670,WX3669,WX3591);
and AND2_1271(WX3671,WX3177,WX3672);
and AND2_1272(WX3677,WX3676,WX3591);
and AND2_1273(WX3678,WX3178,WX3679);
and AND2_1274(WX3684,WX3683,WX3591);
and AND2_1275(WX3685,WX3179,WX3686);
and AND2_1276(WX3691,WX3690,WX3591);
and AND2_1277(WX3692,WX3180,WX3693);
and AND2_1278(WX3698,WX3697,WX3591);
and AND2_1279(WX3699,WX3181,WX3700);
and AND2_1280(WX3705,WX3704,WX3591);
and AND2_1281(WX3706,WX3182,WX3707);
and AND2_1282(WX3712,WX3711,WX3591);
and AND2_1283(WX3713,WX3183,WX3714);
and AND2_1284(WX3719,WX3718,WX3591);
and AND2_1285(WX3720,WX3184,WX3721);
and AND2_1286(WX3726,WX3725,WX3591);
and AND2_1287(WX3727,WX3185,WX3728);
and AND2_1288(WX3733,WX3732,WX3591);
and AND2_1289(WX3734,WX3186,WX3735);
and AND2_1290(WX3740,WX3739,WX3591);
and AND2_1291(WX3741,WX3187,WX3742);
and AND2_1292(WX3747,WX3746,WX3591);
and AND2_1293(WX3748,WX3188,WX3749);
and AND2_1294(WX3754,WX3753,WX3591);
and AND2_1295(WX3755,WX3189,WX3756);
and AND2_1296(WX3761,WX3760,WX3591);
and AND2_1297(WX3762,WX3190,WX3763);
and AND2_1298(WX3768,WX3767,WX3591);
and AND2_1299(WX3769,WX3191,WX3770);
and AND2_1300(WX3775,WX3774,WX3591);
and AND2_1301(WX3776,WX3192,WX3777);
and AND2_1302(WX3782,WX3781,WX3591);
and AND2_1303(WX3783,WX3193,WX3784);
and AND2_1304(WX3789,WX3788,WX3591);
and AND2_1305(WX3790,WX3194,WX3791);
and AND2_1306(WX3796,WX3795,WX3591);
and AND2_1307(WX3797,WX3195,WX3798);
and AND2_1308(WX3803,WX3802,WX3591);
and AND2_1309(WX3804,WX3196,WX3805);
and AND2_1310(WX3810,WX3809,WX3591);
and AND2_1311(WX3811,WX3197,WX3812);
and AND2_1312(WX3850,WX3820,WX3849);
and AND2_1313(WX3852,WX3848,WX3849);
and AND2_1314(WX3854,WX3847,WX3849);
and AND2_1315(WX3856,WX3846,WX3849);
and AND2_1316(WX3858,WX3819,WX3849);
and AND2_1317(WX3860,WX3845,WX3849);
and AND2_1318(WX3862,WX3844,WX3849);
and AND2_1319(WX3864,WX3843,WX3849);
and AND2_1320(WX3866,WX3842,WX3849);
and AND2_1321(WX3868,WX3841,WX3849);
and AND2_1322(WX3870,WX3840,WX3849);
and AND2_1323(WX3872,WX3818,WX3849);
and AND2_1324(WX3874,WX3839,WX3849);
and AND2_1325(WX3876,WX3838,WX3849);
and AND2_1326(WX3878,WX3837,WX3849);
and AND2_1327(WX3880,WX3836,WX3849);
and AND2_1328(WX3882,WX3817,WX3849);
and AND2_1329(WX3884,WX3835,WX3849);
and AND2_1330(WX3886,WX3834,WX3849);
and AND2_1331(WX3888,WX3833,WX3849);
and AND2_1332(WX3890,WX3832,WX3849);
and AND2_1333(WX3892,WX3831,WX3849);
and AND2_1334(WX3894,WX3830,WX3849);
and AND2_1335(WX3896,WX3829,WX3849);
and AND2_1336(WX3898,WX3828,WX3849);
and AND2_1337(WX3900,WX3827,WX3849);
and AND2_1338(WX3902,WX3826,WX3849);
and AND2_1339(WX3904,WX3825,WX3849);
and AND2_1340(WX3906,WX3824,WX3849);
and AND2_1341(WX3908,WX3823,WX3849);
and AND2_1342(WX3910,WX3822,WX3849);
and AND2_1343(WX3912,WX3821,WX3849);
and AND2_1344(WX3914,WX3925,WX4882);
and AND2_1345(WX3915,WX3921,WX3916);
and AND2_1346(WX3918,CRC_OUT_6_31,WX4883);
and AND2_1347(WX3919,WX6184,WX3920);
and AND2_1348(WX3922,WX4364,WX4883);
and AND2_1349(WX3923,WX4891,WX3924);
and AND2_1350(WX3928,WX3939,WX4882);
and AND2_1351(WX3929,WX3935,WX3930);
and AND2_1352(WX3932,CRC_OUT_6_30,WX4883);
and AND2_1353(WX3933,WX6191,WX3934);
and AND2_1354(WX3936,WX4366,WX4883);
and AND2_1355(WX3937,WX4898,WX3938);
and AND2_1356(WX3942,WX3953,WX4882);
and AND2_1357(WX3943,WX3949,WX3944);
and AND2_1358(WX3946,CRC_OUT_6_29,WX4883);
and AND2_1359(WX3947,WX6198,WX3948);
and AND2_1360(WX3950,WX4368,WX4883);
and AND2_1361(WX3951,WX4905,WX3952);
and AND2_1362(WX3956,WX3967,WX4882);
and AND2_1363(WX3957,WX3963,WX3958);
and AND2_1364(WX3960,CRC_OUT_6_28,WX4883);
and AND2_1365(WX3961,WX6205,WX3962);
and AND2_1366(WX3964,WX4370,WX4883);
and AND2_1367(WX3965,WX4912,WX3966);
and AND2_1368(WX3970,WX3981,WX4882);
and AND2_1369(WX3971,WX3977,WX3972);
and AND2_1370(WX3974,CRC_OUT_6_27,WX4883);
and AND2_1371(WX3975,WX6212,WX3976);
and AND2_1372(WX3978,WX4372,WX4883);
and AND2_1373(WX3979,WX4919,WX3980);
and AND2_1374(WX3984,WX3995,WX4882);
and AND2_1375(WX3985,WX3991,WX3986);
and AND2_1376(WX3988,CRC_OUT_6_26,WX4883);
and AND2_1377(WX3989,WX6219,WX3990);
and AND2_1378(WX3992,WX4374,WX4883);
and AND2_1379(WX3993,WX4926,WX3994);
and AND2_1380(WX3998,WX4009,WX4882);
and AND2_1381(WX3999,WX4005,WX4000);
and AND2_1382(WX4002,CRC_OUT_6_25,WX4883);
and AND2_1383(WX4003,WX6226,WX4004);
and AND2_1384(WX4006,WX4376,WX4883);
and AND2_1385(WX4007,WX4933,WX4008);
and AND2_1386(WX4012,WX4023,WX4882);
and AND2_1387(WX4013,WX4019,WX4014);
and AND2_1388(WX4016,CRC_OUT_6_24,WX4883);
and AND2_1389(WX4017,WX6233,WX4018);
and AND2_1390(WX4020,WX4378,WX4883);
and AND2_1391(WX4021,WX4940,WX4022);
and AND2_1392(WX4026,WX4037,WX4882);
and AND2_1393(WX4027,WX4033,WX4028);
and AND2_1394(WX4030,CRC_OUT_6_23,WX4883);
and AND2_1395(WX4031,WX6240,WX4032);
and AND2_1396(WX4034,WX4380,WX4883);
and AND2_1397(WX4035,WX4947,WX4036);
and AND2_1398(WX4040,WX4051,WX4882);
and AND2_1399(WX4041,WX4047,WX4042);
and AND2_1400(WX4044,CRC_OUT_6_22,WX4883);
and AND2_1401(WX4045,WX6247,WX4046);
and AND2_1402(WX4048,WX4382,WX4883);
and AND2_1403(WX4049,WX4954,WX4050);
and AND2_1404(WX4054,WX4065,WX4882);
and AND2_1405(WX4055,WX4061,WX4056);
and AND2_1406(WX4058,CRC_OUT_6_21,WX4883);
and AND2_1407(WX4059,WX6254,WX4060);
and AND2_1408(WX4062,WX4384,WX4883);
and AND2_1409(WX4063,WX4961,WX4064);
and AND2_1410(WX4068,WX4079,WX4882);
and AND2_1411(WX4069,WX4075,WX4070);
and AND2_1412(WX4072,CRC_OUT_6_20,WX4883);
and AND2_1413(WX4073,WX6261,WX4074);
and AND2_1414(WX4076,WX4386,WX4883);
and AND2_1415(WX4077,WX4968,WX4078);
and AND2_1416(WX4082,WX4093,WX4882);
and AND2_1417(WX4083,WX4089,WX4084);
and AND2_1418(WX4086,CRC_OUT_6_19,WX4883);
and AND2_1419(WX4087,WX6268,WX4088);
and AND2_1420(WX4090,WX4388,WX4883);
and AND2_1421(WX4091,WX4975,WX4092);
and AND2_1422(WX4096,WX4107,WX4882);
and AND2_1423(WX4097,WX4103,WX4098);
and AND2_1424(WX4100,CRC_OUT_6_18,WX4883);
and AND2_1425(WX4101,WX6275,WX4102);
and AND2_1426(WX4104,WX4390,WX4883);
and AND2_1427(WX4105,WX4982,WX4106);
and AND2_1428(WX4110,WX4121,WX4882);
and AND2_1429(WX4111,WX4117,WX4112);
and AND2_1430(WX4114,CRC_OUT_6_17,WX4883);
and AND2_1431(WX4115,WX6282,WX4116);
and AND2_1432(WX4118,WX4392,WX4883);
and AND2_1433(WX4119,WX4989,WX4120);
and AND2_1434(WX4124,WX4135,WX4882);
and AND2_1435(WX4125,WX4131,WX4126);
and AND2_1436(WX4128,CRC_OUT_6_16,WX4883);
and AND2_1437(WX4129,WX6289,WX4130);
and AND2_1438(WX4132,WX4394,WX4883);
and AND2_1439(WX4133,WX4996,WX4134);
and AND2_1440(WX4138,WX4149,WX4882);
and AND2_1441(WX4139,WX4145,WX4140);
and AND2_1442(WX4142,CRC_OUT_6_15,WX4883);
and AND2_1443(WX4143,WX6296,WX4144);
and AND2_1444(WX4146,WX4396,WX4883);
and AND2_1445(WX4147,WX5003,WX4148);
and AND2_1446(WX4152,WX4163,WX4882);
and AND2_1447(WX4153,WX4159,WX4154);
and AND2_1448(WX4156,CRC_OUT_6_14,WX4883);
and AND2_1449(WX4157,WX6303,WX4158);
and AND2_1450(WX4160,WX4398,WX4883);
and AND2_1451(WX4161,WX5010,WX4162);
and AND2_1452(WX4166,WX4177,WX4882);
and AND2_1453(WX4167,WX4173,WX4168);
and AND2_1454(WX4170,CRC_OUT_6_13,WX4883);
and AND2_1455(WX4171,WX6310,WX4172);
and AND2_1456(WX4174,WX4400,WX4883);
and AND2_1457(WX4175,WX5017,WX4176);
and AND2_1458(WX4180,WX4191,WX4882);
and AND2_1459(WX4181,WX4187,WX4182);
and AND2_1460(WX4184,CRC_OUT_6_12,WX4883);
and AND2_1461(WX4185,WX6317,WX4186);
and AND2_1462(WX4188,WX4402,WX4883);
and AND2_1463(WX4189,WX5024,WX4190);
and AND2_1464(WX4194,WX4205,WX4882);
and AND2_1465(WX4195,WX4201,WX4196);
and AND2_1466(WX4198,CRC_OUT_6_11,WX4883);
and AND2_1467(WX4199,WX6324,WX4200);
and AND2_1468(WX4202,WX4404,WX4883);
and AND2_1469(WX4203,WX5031,WX4204);
and AND2_1470(WX4208,WX4219,WX4882);
and AND2_1471(WX4209,WX4215,WX4210);
and AND2_1472(WX4212,CRC_OUT_6_10,WX4883);
and AND2_1473(WX4213,WX6331,WX4214);
and AND2_1474(WX4216,WX4406,WX4883);
and AND2_1475(WX4217,WX5038,WX4218);
and AND2_1476(WX4222,WX4233,WX4882);
and AND2_1477(WX4223,WX4229,WX4224);
and AND2_1478(WX4226,CRC_OUT_6_9,WX4883);
and AND2_1479(WX4227,WX6338,WX4228);
and AND2_1480(WX4230,WX4408,WX4883);
and AND2_1481(WX4231,WX5045,WX4232);
and AND2_1482(WX4236,WX4247,WX4882);
and AND2_1483(WX4237,WX4243,WX4238);
and AND2_1484(WX4240,CRC_OUT_6_8,WX4883);
and AND2_1485(WX4241,WX6345,WX4242);
and AND2_1486(WX4244,WX4410,WX4883);
and AND2_1487(WX4245,WX5052,WX4246);
and AND2_1488(WX4250,WX4261,WX4882);
and AND2_1489(WX4251,WX4257,WX4252);
and AND2_1490(WX4254,CRC_OUT_6_7,WX4883);
and AND2_1491(WX4255,WX6352,WX4256);
and AND2_1492(WX4258,WX4412,WX4883);
and AND2_1493(WX4259,WX5059,WX4260);
and AND2_1494(WX4264,WX4275,WX4882);
and AND2_1495(WX4265,WX4271,WX4266);
and AND2_1496(WX4268,CRC_OUT_6_6,WX4883);
and AND2_1497(WX4269,WX6359,WX4270);
and AND2_1498(WX4272,WX4414,WX4883);
and AND2_1499(WX4273,WX5066,WX4274);
and AND2_1500(WX4278,WX4289,WX4882);
and AND2_1501(WX4279,WX4285,WX4280);
and AND2_1502(WX4282,CRC_OUT_6_5,WX4883);
and AND2_1503(WX4283,WX6366,WX4284);
and AND2_1504(WX4286,WX4416,WX4883);
and AND2_1505(WX4287,WX5073,WX4288);
and AND2_1506(WX4292,WX4303,WX4882);
and AND2_1507(WX4293,WX4299,WX4294);
and AND2_1508(WX4296,CRC_OUT_6_4,WX4883);
and AND2_1509(WX4297,WX6373,WX4298);
and AND2_1510(WX4300,WX4418,WX4883);
and AND2_1511(WX4301,WX5080,WX4302);
and AND2_1512(WX4306,WX4317,WX4882);
and AND2_1513(WX4307,WX4313,WX4308);
and AND2_1514(WX4310,CRC_OUT_6_3,WX4883);
and AND2_1515(WX4311,WX6380,WX4312);
and AND2_1516(WX4314,WX4420,WX4883);
and AND2_1517(WX4315,WX5087,WX4316);
and AND2_1518(WX4320,WX4331,WX4882);
and AND2_1519(WX4321,WX4327,WX4322);
and AND2_1520(WX4324,CRC_OUT_6_2,WX4883);
and AND2_1521(WX4325,WX6387,WX4326);
and AND2_1522(WX4328,WX4422,WX4883);
and AND2_1523(WX4329,WX5094,WX4330);
and AND2_1524(WX4334,WX4345,WX4882);
and AND2_1525(WX4335,WX4341,WX4336);
and AND2_1526(WX4338,CRC_OUT_6_1,WX4883);
and AND2_1527(WX4339,WX6394,WX4340);
and AND2_1528(WX4342,WX4424,WX4883);
and AND2_1529(WX4343,WX5101,WX4344);
and AND2_1530(WX4348,WX4359,WX4882);
and AND2_1531(WX4349,WX4355,WX4350);
and AND2_1532(WX4352,CRC_OUT_6_0,WX4883);
and AND2_1533(WX4353,WX6401,WX4354);
and AND2_1534(WX4356,WX4426,WX4883);
and AND2_1535(WX4357,WX5108,WX4358);
and AND2_1536(WX4363,WX4366,RESET);
and AND2_1537(WX4365,WX4368,RESET);
and AND2_1538(WX4367,WX4370,RESET);
and AND2_1539(WX4369,WX4372,RESET);
and AND2_1540(WX4371,WX4374,RESET);
and AND2_1541(WX4373,WX4376,RESET);
and AND2_1542(WX4375,WX4378,RESET);
and AND2_1543(WX4377,WX4380,RESET);
and AND2_1544(WX4379,WX4382,RESET);
and AND2_1545(WX4381,WX4384,RESET);
and AND2_1546(WX4383,WX4386,RESET);
and AND2_1547(WX4385,WX4388,RESET);
and AND2_1548(WX4387,WX4390,RESET);
and AND2_1549(WX4389,WX4392,RESET);
and AND2_1550(WX4391,WX4394,RESET);
and AND2_1551(WX4393,WX4396,RESET);
and AND2_1552(WX4395,WX4398,RESET);
and AND2_1553(WX4397,WX4400,RESET);
and AND2_1554(WX4399,WX4402,RESET);
and AND2_1555(WX4401,WX4404,RESET);
and AND2_1556(WX4403,WX4406,RESET);
and AND2_1557(WX4405,WX4408,RESET);
and AND2_1558(WX4407,WX4410,RESET);
and AND2_1559(WX4409,WX4412,RESET);
and AND2_1560(WX4411,WX4414,RESET);
and AND2_1561(WX4413,WX4416,RESET);
and AND2_1562(WX4415,WX4418,RESET);
and AND2_1563(WX4417,WX4420,RESET);
and AND2_1564(WX4419,WX4422,RESET);
and AND2_1565(WX4421,WX4424,RESET);
and AND2_1566(WX4423,WX4426,RESET);
and AND2_1567(WX4425,WX4362,RESET);
and AND2_1568(WX4523,WX3927,RESET);
and AND2_1569(WX4525,WX3941,RESET);
and AND2_1570(WX4527,WX3955,RESET);
and AND2_1571(WX4529,WX3969,RESET);
and AND2_1572(WX4531,WX3983,RESET);
and AND2_1573(WX4533,WX3997,RESET);
and AND2_1574(WX4535,WX4011,RESET);
and AND2_1575(WX4537,WX4025,RESET);
and AND2_1576(WX4539,WX4039,RESET);
and AND2_1577(WX4541,WX4053,RESET);
and AND2_1578(WX4543,WX4067,RESET);
and AND2_1579(WX4545,WX4081,RESET);
and AND2_1580(WX4547,WX4095,RESET);
and AND2_1581(WX4549,WX4109,RESET);
and AND2_1582(WX4551,WX4123,RESET);
and AND2_1583(WX4553,WX4137,RESET);
and AND2_1584(WX4555,WX4151,RESET);
and AND2_1585(WX4557,WX4165,RESET);
and AND2_1586(WX4559,WX4179,RESET);
and AND2_1587(WX4561,WX4193,RESET);
and AND2_1588(WX4563,WX4207,RESET);
and AND2_1589(WX4565,WX4221,RESET);
and AND2_1590(WX4567,WX4235,RESET);
and AND2_1591(WX4569,WX4249,RESET);
and AND2_1592(WX4571,WX4263,RESET);
and AND2_1593(WX4573,WX4277,RESET);
and AND2_1594(WX4575,WX4291,RESET);
and AND2_1595(WX4577,WX4305,RESET);
and AND2_1596(WX4579,WX4319,RESET);
and AND2_1597(WX4581,WX4333,RESET);
and AND2_1598(WX4583,WX4347,RESET);
and AND2_1599(WX4585,WX4361,RESET);
and AND2_1600(WX4587,WX4524,RESET);
and AND2_1601(WX4589,WX4526,RESET);
and AND2_1602(WX4591,WX4528,RESET);
and AND2_1603(WX4593,WX4530,RESET);
and AND2_1604(WX4595,WX4532,RESET);
and AND2_1605(WX4597,WX4534,RESET);
and AND2_1606(WX4599,WX4536,RESET);
and AND2_1607(WX4601,WX4538,RESET);
and AND2_1608(WX4603,WX4540,RESET);
and AND2_1609(WX4605,WX4542,RESET);
and AND2_1610(WX4607,WX4544,RESET);
and AND2_1611(WX4609,WX4546,RESET);
and AND2_1612(WX4611,WX4548,RESET);
and AND2_1613(WX4613,WX4550,RESET);
and AND2_1614(WX4615,WX4552,RESET);
and AND2_1615(WX4617,WX4554,RESET);
and AND2_1616(WX4619,WX4556,RESET);
and AND2_1617(WX4621,WX4558,RESET);
and AND2_1618(WX4623,WX4560,RESET);
and AND2_1619(WX4625,WX4562,RESET);
and AND2_1620(WX4627,WX4564,RESET);
and AND2_1621(WX4629,WX4566,RESET);
and AND2_1622(WX4631,WX4568,RESET);
and AND2_1623(WX4633,WX4570,RESET);
and AND2_1624(WX4635,WX4572,RESET);
and AND2_1625(WX4637,WX4574,RESET);
and AND2_1626(WX4639,WX4576,RESET);
and AND2_1627(WX4641,WX4578,RESET);
and AND2_1628(WX4643,WX4580,RESET);
and AND2_1629(WX4645,WX4582,RESET);
and AND2_1630(WX4647,WX4584,RESET);
and AND2_1631(WX4649,WX4586,RESET);
and AND2_1632(WX4651,WX4588,RESET);
and AND2_1633(WX4653,WX4590,RESET);
and AND2_1634(WX4655,WX4592,RESET);
and AND2_1635(WX4657,WX4594,RESET);
and AND2_1636(WX4659,WX4596,RESET);
and AND2_1637(WX4661,WX4598,RESET);
and AND2_1638(WX4663,WX4600,RESET);
and AND2_1639(WX4665,WX4602,RESET);
and AND2_1640(WX4667,WX4604,RESET);
and AND2_1641(WX4669,WX4606,RESET);
and AND2_1642(WX4671,WX4608,RESET);
and AND2_1643(WX4673,WX4610,RESET);
and AND2_1644(WX4675,WX4612,RESET);
and AND2_1645(WX4677,WX4614,RESET);
and AND2_1646(WX4679,WX4616,RESET);
and AND2_1647(WX4681,WX4618,RESET);
and AND2_1648(WX4683,WX4620,RESET);
and AND2_1649(WX4685,WX4622,RESET);
and AND2_1650(WX4687,WX4624,RESET);
and AND2_1651(WX4689,WX4626,RESET);
and AND2_1652(WX4691,WX4628,RESET);
and AND2_1653(WX4693,WX4630,RESET);
and AND2_1654(WX4695,WX4632,RESET);
and AND2_1655(WX4697,WX4634,RESET);
and AND2_1656(WX4699,WX4636,RESET);
and AND2_1657(WX4701,WX4638,RESET);
and AND2_1658(WX4703,WX4640,RESET);
and AND2_1659(WX4705,WX4642,RESET);
and AND2_1660(WX4707,WX4644,RESET);
and AND2_1661(WX4709,WX4646,RESET);
and AND2_1662(WX4711,WX4648,RESET);
and AND2_1663(WX4713,WX4650,RESET);
and AND2_1664(WX4715,WX4652,RESET);
and AND2_1665(WX4717,WX4654,RESET);
and AND2_1666(WX4719,WX4656,RESET);
and AND2_1667(WX4721,WX4658,RESET);
and AND2_1668(WX4723,WX4660,RESET);
and AND2_1669(WX4725,WX4662,RESET);
and AND2_1670(WX4727,WX4664,RESET);
and AND2_1671(WX4729,WX4666,RESET);
and AND2_1672(WX4731,WX4668,RESET);
and AND2_1673(WX4733,WX4670,RESET);
and AND2_1674(WX4735,WX4672,RESET);
and AND2_1675(WX4737,WX4674,RESET);
and AND2_1676(WX4739,WX4676,RESET);
and AND2_1677(WX4741,WX4678,RESET);
and AND2_1678(WX4743,WX4680,RESET);
and AND2_1679(WX4745,WX4682,RESET);
and AND2_1680(WX4747,WX4684,RESET);
and AND2_1681(WX4749,WX4686,RESET);
and AND2_1682(WX4751,WX4688,RESET);
and AND2_1683(WX4753,WX4690,RESET);
and AND2_1684(WX4755,WX4692,RESET);
and AND2_1685(WX4757,WX4694,RESET);
and AND2_1686(WX4759,WX4696,RESET);
and AND2_1687(WX4761,WX4698,RESET);
and AND2_1688(WX4763,WX4700,RESET);
and AND2_1689(WX4765,WX4702,RESET);
and AND2_1690(WX4767,WX4704,RESET);
and AND2_1691(WX4769,WX4706,RESET);
and AND2_1692(WX4771,WX4708,RESET);
and AND2_1693(WX4773,WX4710,RESET);
and AND2_1694(WX4775,WX4712,RESET);
and AND2_1695(WX4777,WX4714,RESET);
and AND2_1696(WX4886,WX4885,WX4884);
and AND2_1697(WX4887,WX4459,WX4888);
and AND2_1698(WX4893,WX4892,WX4884);
and AND2_1699(WX4894,WX4460,WX4895);
and AND2_1700(WX4900,WX4899,WX4884);
and AND2_1701(WX4901,WX4461,WX4902);
and AND2_1702(WX4907,WX4906,WX4884);
and AND2_1703(WX4908,WX4462,WX4909);
and AND2_1704(WX4914,WX4913,WX4884);
and AND2_1705(WX4915,WX4463,WX4916);
and AND2_1706(WX4921,WX4920,WX4884);
and AND2_1707(WX4922,WX4464,WX4923);
and AND2_1708(WX4928,WX4927,WX4884);
and AND2_1709(WX4929,WX4465,WX4930);
and AND2_1710(WX4935,WX4934,WX4884);
and AND2_1711(WX4936,WX4466,WX4937);
and AND2_1712(WX4942,WX4941,WX4884);
and AND2_1713(WX4943,WX4467,WX4944);
and AND2_1714(WX4949,WX4948,WX4884);
and AND2_1715(WX4950,WX4468,WX4951);
and AND2_1716(WX4956,WX4955,WX4884);
and AND2_1717(WX4957,WX4469,WX4958);
and AND2_1718(WX4963,WX4962,WX4884);
and AND2_1719(WX4964,WX4470,WX4965);
and AND2_1720(WX4970,WX4969,WX4884);
and AND2_1721(WX4971,WX4471,WX4972);
and AND2_1722(WX4977,WX4976,WX4884);
and AND2_1723(WX4978,WX4472,WX4979);
and AND2_1724(WX4984,WX4983,WX4884);
and AND2_1725(WX4985,WX4473,WX4986);
and AND2_1726(WX4991,WX4990,WX4884);
and AND2_1727(WX4992,WX4474,WX4993);
and AND2_1728(WX4998,WX4997,WX4884);
and AND2_1729(WX4999,WX4475,WX5000);
and AND2_1730(WX5005,WX5004,WX4884);
and AND2_1731(WX5006,WX4476,WX5007);
and AND2_1732(WX5012,WX5011,WX4884);
and AND2_1733(WX5013,WX4477,WX5014);
and AND2_1734(WX5019,WX5018,WX4884);
and AND2_1735(WX5020,WX4478,WX5021);
and AND2_1736(WX5026,WX5025,WX4884);
and AND2_1737(WX5027,WX4479,WX5028);
and AND2_1738(WX5033,WX5032,WX4884);
and AND2_1739(WX5034,WX4480,WX5035);
and AND2_1740(WX5040,WX5039,WX4884);
and AND2_1741(WX5041,WX4481,WX5042);
and AND2_1742(WX5047,WX5046,WX4884);
and AND2_1743(WX5048,WX4482,WX5049);
and AND2_1744(WX5054,WX5053,WX4884);
and AND2_1745(WX5055,WX4483,WX5056);
and AND2_1746(WX5061,WX5060,WX4884);
and AND2_1747(WX5062,WX4484,WX5063);
and AND2_1748(WX5068,WX5067,WX4884);
and AND2_1749(WX5069,WX4485,WX5070);
and AND2_1750(WX5075,WX5074,WX4884);
and AND2_1751(WX5076,WX4486,WX5077);
and AND2_1752(WX5082,WX5081,WX4884);
and AND2_1753(WX5083,WX4487,WX5084);
and AND2_1754(WX5089,WX5088,WX4884);
and AND2_1755(WX5090,WX4488,WX5091);
and AND2_1756(WX5096,WX5095,WX4884);
and AND2_1757(WX5097,WX4489,WX5098);
and AND2_1758(WX5103,WX5102,WX4884);
and AND2_1759(WX5104,WX4490,WX5105);
and AND2_1760(WX5143,WX5113,WX5142);
and AND2_1761(WX5145,WX5141,WX5142);
and AND2_1762(WX5147,WX5140,WX5142);
and AND2_1763(WX5149,WX5139,WX5142);
and AND2_1764(WX5151,WX5112,WX5142);
and AND2_1765(WX5153,WX5138,WX5142);
and AND2_1766(WX5155,WX5137,WX5142);
and AND2_1767(WX5157,WX5136,WX5142);
and AND2_1768(WX5159,WX5135,WX5142);
and AND2_1769(WX5161,WX5134,WX5142);
and AND2_1770(WX5163,WX5133,WX5142);
and AND2_1771(WX5165,WX5111,WX5142);
and AND2_1772(WX5167,WX5132,WX5142);
and AND2_1773(WX5169,WX5131,WX5142);
and AND2_1774(WX5171,WX5130,WX5142);
and AND2_1775(WX5173,WX5129,WX5142);
and AND2_1776(WX5175,WX5110,WX5142);
and AND2_1777(WX5177,WX5128,WX5142);
and AND2_1778(WX5179,WX5127,WX5142);
and AND2_1779(WX5181,WX5126,WX5142);
and AND2_1780(WX5183,WX5125,WX5142);
and AND2_1781(WX5185,WX5124,WX5142);
and AND2_1782(WX5187,WX5123,WX5142);
and AND2_1783(WX5189,WX5122,WX5142);
and AND2_1784(WX5191,WX5121,WX5142);
and AND2_1785(WX5193,WX5120,WX5142);
and AND2_1786(WX5195,WX5119,WX5142);
and AND2_1787(WX5197,WX5118,WX5142);
and AND2_1788(WX5199,WX5117,WX5142);
and AND2_1789(WX5201,WX5116,WX5142);
and AND2_1790(WX5203,WX5115,WX5142);
and AND2_1791(WX5205,WX5114,WX5142);
and AND2_1792(WX5207,WX5218,WX6175);
and AND2_1793(WX5208,WX5214,WX5209);
and AND2_1794(WX5211,CRC_OUT_5_31,WX6176);
and AND2_1795(WX5212,WX7477,WX5213);
and AND2_1796(WX5215,WX5657,WX6176);
and AND2_1797(WX5216,WX6184,WX5217);
and AND2_1798(WX5221,WX5232,WX6175);
and AND2_1799(WX5222,WX5228,WX5223);
and AND2_1800(WX5225,CRC_OUT_5_30,WX6176);
and AND2_1801(WX5226,WX7484,WX5227);
and AND2_1802(WX5229,WX5659,WX6176);
and AND2_1803(WX5230,WX6191,WX5231);
and AND2_1804(WX5235,WX5246,WX6175);
and AND2_1805(WX5236,WX5242,WX5237);
and AND2_1806(WX5239,CRC_OUT_5_29,WX6176);
and AND2_1807(WX5240,WX7491,WX5241);
and AND2_1808(WX5243,WX5661,WX6176);
and AND2_1809(WX5244,WX6198,WX5245);
and AND2_1810(WX5249,WX5260,WX6175);
and AND2_1811(WX5250,WX5256,WX5251);
and AND2_1812(WX5253,CRC_OUT_5_28,WX6176);
and AND2_1813(WX5254,WX7498,WX5255);
and AND2_1814(WX5257,WX5663,WX6176);
and AND2_1815(WX5258,WX6205,WX5259);
and AND2_1816(WX5263,WX5274,WX6175);
and AND2_1817(WX5264,WX5270,WX5265);
and AND2_1818(WX5267,CRC_OUT_5_27,WX6176);
and AND2_1819(WX5268,WX7505,WX5269);
and AND2_1820(WX5271,WX5665,WX6176);
and AND2_1821(WX5272,WX6212,WX5273);
and AND2_1822(WX5277,WX5288,WX6175);
and AND2_1823(WX5278,WX5284,WX5279);
and AND2_1824(WX5281,CRC_OUT_5_26,WX6176);
and AND2_1825(WX5282,WX7512,WX5283);
and AND2_1826(WX5285,WX5667,WX6176);
and AND2_1827(WX5286,WX6219,WX5287);
and AND2_1828(WX5291,WX5302,WX6175);
and AND2_1829(WX5292,WX5298,WX5293);
and AND2_1830(WX5295,CRC_OUT_5_25,WX6176);
and AND2_1831(WX5296,WX7519,WX5297);
and AND2_1832(WX5299,WX5669,WX6176);
and AND2_1833(WX5300,WX6226,WX5301);
and AND2_1834(WX5305,WX5316,WX6175);
and AND2_1835(WX5306,WX5312,WX5307);
and AND2_1836(WX5309,CRC_OUT_5_24,WX6176);
and AND2_1837(WX5310,WX7526,WX5311);
and AND2_1838(WX5313,WX5671,WX6176);
and AND2_1839(WX5314,WX6233,WX5315);
and AND2_1840(WX5319,WX5330,WX6175);
and AND2_1841(WX5320,WX5326,WX5321);
and AND2_1842(WX5323,CRC_OUT_5_23,WX6176);
and AND2_1843(WX5324,WX7533,WX5325);
and AND2_1844(WX5327,WX5673,WX6176);
and AND2_1845(WX5328,WX6240,WX5329);
and AND2_1846(WX5333,WX5344,WX6175);
and AND2_1847(WX5334,WX5340,WX5335);
and AND2_1848(WX5337,CRC_OUT_5_22,WX6176);
and AND2_1849(WX5338,WX7540,WX5339);
and AND2_1850(WX5341,WX5675,WX6176);
and AND2_1851(WX5342,WX6247,WX5343);
and AND2_1852(WX5347,WX5358,WX6175);
and AND2_1853(WX5348,WX5354,WX5349);
and AND2_1854(WX5351,CRC_OUT_5_21,WX6176);
and AND2_1855(WX5352,WX7547,WX5353);
and AND2_1856(WX5355,WX5677,WX6176);
and AND2_1857(WX5356,WX6254,WX5357);
and AND2_1858(WX5361,WX5372,WX6175);
and AND2_1859(WX5362,WX5368,WX5363);
and AND2_1860(WX5365,CRC_OUT_5_20,WX6176);
and AND2_1861(WX5366,WX7554,WX5367);
and AND2_1862(WX5369,WX5679,WX6176);
and AND2_1863(WX5370,WX6261,WX5371);
and AND2_1864(WX5375,WX5386,WX6175);
and AND2_1865(WX5376,WX5382,WX5377);
and AND2_1866(WX5379,CRC_OUT_5_19,WX6176);
and AND2_1867(WX5380,WX7561,WX5381);
and AND2_1868(WX5383,WX5681,WX6176);
and AND2_1869(WX5384,WX6268,WX5385);
and AND2_1870(WX5389,WX5400,WX6175);
and AND2_1871(WX5390,WX5396,WX5391);
and AND2_1872(WX5393,CRC_OUT_5_18,WX6176);
and AND2_1873(WX5394,WX7568,WX5395);
and AND2_1874(WX5397,WX5683,WX6176);
and AND2_1875(WX5398,WX6275,WX5399);
and AND2_1876(WX5403,WX5414,WX6175);
and AND2_1877(WX5404,WX5410,WX5405);
and AND2_1878(WX5407,CRC_OUT_5_17,WX6176);
and AND2_1879(WX5408,WX7575,WX5409);
and AND2_1880(WX5411,WX5685,WX6176);
and AND2_1881(WX5412,WX6282,WX5413);
and AND2_1882(WX5417,WX5428,WX6175);
and AND2_1883(WX5418,WX5424,WX5419);
and AND2_1884(WX5421,CRC_OUT_5_16,WX6176);
and AND2_1885(WX5422,WX7582,WX5423);
and AND2_1886(WX5425,WX5687,WX6176);
and AND2_1887(WX5426,WX6289,WX5427);
and AND2_1888(WX5431,WX5442,WX6175);
and AND2_1889(WX5432,WX5438,WX5433);
and AND2_1890(WX5435,CRC_OUT_5_15,WX6176);
and AND2_1891(WX5436,WX7589,WX5437);
and AND2_1892(WX5439,WX5689,WX6176);
and AND2_1893(WX5440,WX6296,WX5441);
and AND2_1894(WX5445,WX5456,WX6175);
and AND2_1895(WX5446,WX5452,WX5447);
and AND2_1896(WX5449,CRC_OUT_5_14,WX6176);
and AND2_1897(WX5450,WX7596,WX5451);
and AND2_1898(WX5453,WX5691,WX6176);
and AND2_1899(WX5454,WX6303,WX5455);
and AND2_1900(WX5459,WX5470,WX6175);
and AND2_1901(WX5460,WX5466,WX5461);
and AND2_1902(WX5463,CRC_OUT_5_13,WX6176);
and AND2_1903(WX5464,WX7603,WX5465);
and AND2_1904(WX5467,WX5693,WX6176);
and AND2_1905(WX5468,WX6310,WX5469);
and AND2_1906(WX5473,WX5484,WX6175);
and AND2_1907(WX5474,WX5480,WX5475);
and AND2_1908(WX5477,CRC_OUT_5_12,WX6176);
and AND2_1909(WX5478,WX7610,WX5479);
and AND2_1910(WX5481,WX5695,WX6176);
and AND2_1911(WX5482,WX6317,WX5483);
and AND2_1912(WX5487,WX5498,WX6175);
and AND2_1913(WX5488,WX5494,WX5489);
and AND2_1914(WX5491,CRC_OUT_5_11,WX6176);
and AND2_1915(WX5492,WX7617,WX5493);
and AND2_1916(WX5495,WX5697,WX6176);
and AND2_1917(WX5496,WX6324,WX5497);
and AND2_1918(WX5501,WX5512,WX6175);
and AND2_1919(WX5502,WX5508,WX5503);
and AND2_1920(WX5505,CRC_OUT_5_10,WX6176);
and AND2_1921(WX5506,WX7624,WX5507);
and AND2_1922(WX5509,WX5699,WX6176);
and AND2_1923(WX5510,WX6331,WX5511);
and AND2_1924(WX5515,WX5526,WX6175);
and AND2_1925(WX5516,WX5522,WX5517);
and AND2_1926(WX5519,CRC_OUT_5_9,WX6176);
and AND2_1927(WX5520,WX7631,WX5521);
and AND2_1928(WX5523,WX5701,WX6176);
and AND2_1929(WX5524,WX6338,WX5525);
and AND2_1930(WX5529,WX5540,WX6175);
and AND2_1931(WX5530,WX5536,WX5531);
and AND2_1932(WX5533,CRC_OUT_5_8,WX6176);
and AND2_1933(WX5534,WX7638,WX5535);
and AND2_1934(WX5537,WX5703,WX6176);
and AND2_1935(WX5538,WX6345,WX5539);
and AND2_1936(WX5543,WX5554,WX6175);
and AND2_1937(WX5544,WX5550,WX5545);
and AND2_1938(WX5547,CRC_OUT_5_7,WX6176);
and AND2_1939(WX5548,WX7645,WX5549);
and AND2_1940(WX5551,WX5705,WX6176);
and AND2_1941(WX5552,WX6352,WX5553);
and AND2_1942(WX5557,WX5568,WX6175);
and AND2_1943(WX5558,WX5564,WX5559);
and AND2_1944(WX5561,CRC_OUT_5_6,WX6176);
and AND2_1945(WX5562,WX7652,WX5563);
and AND2_1946(WX5565,WX5707,WX6176);
and AND2_1947(WX5566,WX6359,WX5567);
and AND2_1948(WX5571,WX5582,WX6175);
and AND2_1949(WX5572,WX5578,WX5573);
and AND2_1950(WX5575,CRC_OUT_5_5,WX6176);
and AND2_1951(WX5576,WX7659,WX5577);
and AND2_1952(WX5579,WX5709,WX6176);
and AND2_1953(WX5580,WX6366,WX5581);
and AND2_1954(WX5585,WX5596,WX6175);
and AND2_1955(WX5586,WX5592,WX5587);
and AND2_1956(WX5589,CRC_OUT_5_4,WX6176);
and AND2_1957(WX5590,WX7666,WX5591);
and AND2_1958(WX5593,WX5711,WX6176);
and AND2_1959(WX5594,WX6373,WX5595);
and AND2_1960(WX5599,WX5610,WX6175);
and AND2_1961(WX5600,WX5606,WX5601);
and AND2_1962(WX5603,CRC_OUT_5_3,WX6176);
and AND2_1963(WX5604,WX7673,WX5605);
and AND2_1964(WX5607,WX5713,WX6176);
and AND2_1965(WX5608,WX6380,WX5609);
and AND2_1966(WX5613,WX5624,WX6175);
and AND2_1967(WX5614,WX5620,WX5615);
and AND2_1968(WX5617,CRC_OUT_5_2,WX6176);
and AND2_1969(WX5618,WX7680,WX5619);
and AND2_1970(WX5621,WX5715,WX6176);
and AND2_1971(WX5622,WX6387,WX5623);
and AND2_1972(WX5627,WX5638,WX6175);
and AND2_1973(WX5628,WX5634,WX5629);
and AND2_1974(WX5631,CRC_OUT_5_1,WX6176);
and AND2_1975(WX5632,WX7687,WX5633);
and AND2_1976(WX5635,WX5717,WX6176);
and AND2_1977(WX5636,WX6394,WX5637);
and AND2_1978(WX5641,WX5652,WX6175);
and AND2_1979(WX5642,WX5648,WX5643);
and AND2_1980(WX5645,CRC_OUT_5_0,WX6176);
and AND2_1981(WX5646,WX7694,WX5647);
and AND2_1982(WX5649,WX5719,WX6176);
and AND2_1983(WX5650,WX6401,WX5651);
and AND2_1984(WX5656,WX5659,RESET);
and AND2_1985(WX5658,WX5661,RESET);
and AND2_1986(WX5660,WX5663,RESET);
and AND2_1987(WX5662,WX5665,RESET);
and AND2_1988(WX5664,WX5667,RESET);
and AND2_1989(WX5666,WX5669,RESET);
and AND2_1990(WX5668,WX5671,RESET);
and AND2_1991(WX5670,WX5673,RESET);
and AND2_1992(WX5672,WX5675,RESET);
and AND2_1993(WX5674,WX5677,RESET);
and AND2_1994(WX5676,WX5679,RESET);
and AND2_1995(WX5678,WX5681,RESET);
and AND2_1996(WX5680,WX5683,RESET);
and AND2_1997(WX5682,WX5685,RESET);
and AND2_1998(WX5684,WX5687,RESET);
and AND2_1999(WX5686,WX5689,RESET);
and AND2_2000(WX5688,WX5691,RESET);
and AND2_2001(WX5690,WX5693,RESET);
and AND2_2002(WX5692,WX5695,RESET);
and AND2_2003(WX5694,WX5697,RESET);
and AND2_2004(WX5696,WX5699,RESET);
and AND2_2005(WX5698,WX5701,RESET);
and AND2_2006(WX5700,WX5703,RESET);
and AND2_2007(WX5702,WX5705,RESET);
and AND2_2008(WX5704,WX5707,RESET);
and AND2_2009(WX5706,WX5709,RESET);
and AND2_2010(WX5708,WX5711,RESET);
and AND2_2011(WX5710,WX5713,RESET);
and AND2_2012(WX5712,WX5715,RESET);
and AND2_2013(WX5714,WX5717,RESET);
and AND2_2014(WX5716,WX5719,RESET);
and AND2_2015(WX5718,WX5655,RESET);
and AND2_2016(WX5816,WX5220,RESET);
and AND2_2017(WX5818,WX5234,RESET);
and AND2_2018(WX5820,WX5248,RESET);
and AND2_2019(WX5822,WX5262,RESET);
and AND2_2020(WX5824,WX5276,RESET);
and AND2_2021(WX5826,WX5290,RESET);
and AND2_2022(WX5828,WX5304,RESET);
and AND2_2023(WX5830,WX5318,RESET);
and AND2_2024(WX5832,WX5332,RESET);
and AND2_2025(WX5834,WX5346,RESET);
and AND2_2026(WX5836,WX5360,RESET);
and AND2_2027(WX5838,WX5374,RESET);
and AND2_2028(WX5840,WX5388,RESET);
and AND2_2029(WX5842,WX5402,RESET);
and AND2_2030(WX5844,WX5416,RESET);
and AND2_2031(WX5846,WX5430,RESET);
and AND2_2032(WX5848,WX5444,RESET);
and AND2_2033(WX5850,WX5458,RESET);
and AND2_2034(WX5852,WX5472,RESET);
and AND2_2035(WX5854,WX5486,RESET);
and AND2_2036(WX5856,WX5500,RESET);
and AND2_2037(WX5858,WX5514,RESET);
and AND2_2038(WX5860,WX5528,RESET);
and AND2_2039(WX5862,WX5542,RESET);
and AND2_2040(WX5864,WX5556,RESET);
and AND2_2041(WX5866,WX5570,RESET);
and AND2_2042(WX5868,WX5584,RESET);
and AND2_2043(WX5870,WX5598,RESET);
and AND2_2044(WX5872,WX5612,RESET);
and AND2_2045(WX5874,WX5626,RESET);
and AND2_2046(WX5876,WX5640,RESET);
and AND2_2047(WX5878,WX5654,RESET);
and AND2_2048(WX5880,WX5817,RESET);
and AND2_2049(WX5882,WX5819,RESET);
and AND2_2050(WX5884,WX5821,RESET);
and AND2_2051(WX5886,WX5823,RESET);
and AND2_2052(WX5888,WX5825,RESET);
and AND2_2053(WX5890,WX5827,RESET);
and AND2_2054(WX5892,WX5829,RESET);
and AND2_2055(WX5894,WX5831,RESET);
and AND2_2056(WX5896,WX5833,RESET);
and AND2_2057(WX5898,WX5835,RESET);
and AND2_2058(WX5900,WX5837,RESET);
and AND2_2059(WX5902,WX5839,RESET);
and AND2_2060(WX5904,WX5841,RESET);
and AND2_2061(WX5906,WX5843,RESET);
and AND2_2062(WX5908,WX5845,RESET);
and AND2_2063(WX5910,WX5847,RESET);
and AND2_2064(WX5912,WX5849,RESET);
and AND2_2065(WX5914,WX5851,RESET);
and AND2_2066(WX5916,WX5853,RESET);
and AND2_2067(WX5918,WX5855,RESET);
and AND2_2068(WX5920,WX5857,RESET);
and AND2_2069(WX5922,WX5859,RESET);
and AND2_2070(WX5924,WX5861,RESET);
and AND2_2071(WX5926,WX5863,RESET);
and AND2_2072(WX5928,WX5865,RESET);
and AND2_2073(WX5930,WX5867,RESET);
and AND2_2074(WX5932,WX5869,RESET);
and AND2_2075(WX5934,WX5871,RESET);
and AND2_2076(WX5936,WX5873,RESET);
and AND2_2077(WX5938,WX5875,RESET);
and AND2_2078(WX5940,WX5877,RESET);
and AND2_2079(WX5942,WX5879,RESET);
and AND2_2080(WX5944,WX5881,RESET);
and AND2_2081(WX5946,WX5883,RESET);
and AND2_2082(WX5948,WX5885,RESET);
and AND2_2083(WX5950,WX5887,RESET);
and AND2_2084(WX5952,WX5889,RESET);
and AND2_2085(WX5954,WX5891,RESET);
and AND2_2086(WX5956,WX5893,RESET);
and AND2_2087(WX5958,WX5895,RESET);
and AND2_2088(WX5960,WX5897,RESET);
and AND2_2089(WX5962,WX5899,RESET);
and AND2_2090(WX5964,WX5901,RESET);
and AND2_2091(WX5966,WX5903,RESET);
and AND2_2092(WX5968,WX5905,RESET);
and AND2_2093(WX5970,WX5907,RESET);
and AND2_2094(WX5972,WX5909,RESET);
and AND2_2095(WX5974,WX5911,RESET);
and AND2_2096(WX5976,WX5913,RESET);
and AND2_2097(WX5978,WX5915,RESET);
and AND2_2098(WX5980,WX5917,RESET);
and AND2_2099(WX5982,WX5919,RESET);
and AND2_2100(WX5984,WX5921,RESET);
and AND2_2101(WX5986,WX5923,RESET);
and AND2_2102(WX5988,WX5925,RESET);
and AND2_2103(WX5990,WX5927,RESET);
and AND2_2104(WX5992,WX5929,RESET);
and AND2_2105(WX5994,WX5931,RESET);
and AND2_2106(WX5996,WX5933,RESET);
and AND2_2107(WX5998,WX5935,RESET);
and AND2_2108(WX6000,WX5937,RESET);
and AND2_2109(WX6002,WX5939,RESET);
and AND2_2110(WX6004,WX5941,RESET);
and AND2_2111(WX6006,WX5943,RESET);
and AND2_2112(WX6008,WX5945,RESET);
and AND2_2113(WX6010,WX5947,RESET);
and AND2_2114(WX6012,WX5949,RESET);
and AND2_2115(WX6014,WX5951,RESET);
and AND2_2116(WX6016,WX5953,RESET);
and AND2_2117(WX6018,WX5955,RESET);
and AND2_2118(WX6020,WX5957,RESET);
and AND2_2119(WX6022,WX5959,RESET);
and AND2_2120(WX6024,WX5961,RESET);
and AND2_2121(WX6026,WX5963,RESET);
and AND2_2122(WX6028,WX5965,RESET);
and AND2_2123(WX6030,WX5967,RESET);
and AND2_2124(WX6032,WX5969,RESET);
and AND2_2125(WX6034,WX5971,RESET);
and AND2_2126(WX6036,WX5973,RESET);
and AND2_2127(WX6038,WX5975,RESET);
and AND2_2128(WX6040,WX5977,RESET);
and AND2_2129(WX6042,WX5979,RESET);
and AND2_2130(WX6044,WX5981,RESET);
and AND2_2131(WX6046,WX5983,RESET);
and AND2_2132(WX6048,WX5985,RESET);
and AND2_2133(WX6050,WX5987,RESET);
and AND2_2134(WX6052,WX5989,RESET);
and AND2_2135(WX6054,WX5991,RESET);
and AND2_2136(WX6056,WX5993,RESET);
and AND2_2137(WX6058,WX5995,RESET);
and AND2_2138(WX6060,WX5997,RESET);
and AND2_2139(WX6062,WX5999,RESET);
and AND2_2140(WX6064,WX6001,RESET);
and AND2_2141(WX6066,WX6003,RESET);
and AND2_2142(WX6068,WX6005,RESET);
and AND2_2143(WX6070,WX6007,RESET);
and AND2_2144(WX6179,WX6178,WX6177);
and AND2_2145(WX6180,WX5752,WX6181);
and AND2_2146(WX6186,WX6185,WX6177);
and AND2_2147(WX6187,WX5753,WX6188);
and AND2_2148(WX6193,WX6192,WX6177);
and AND2_2149(WX6194,WX5754,WX6195);
and AND2_2150(WX6200,WX6199,WX6177);
and AND2_2151(WX6201,WX5755,WX6202);
and AND2_2152(WX6207,WX6206,WX6177);
and AND2_2153(WX6208,WX5756,WX6209);
and AND2_2154(WX6214,WX6213,WX6177);
and AND2_2155(WX6215,WX5757,WX6216);
and AND2_2156(WX6221,WX6220,WX6177);
and AND2_2157(WX6222,WX5758,WX6223);
and AND2_2158(WX6228,WX6227,WX6177);
and AND2_2159(WX6229,WX5759,WX6230);
and AND2_2160(WX6235,WX6234,WX6177);
and AND2_2161(WX6236,WX5760,WX6237);
and AND2_2162(WX6242,WX6241,WX6177);
and AND2_2163(WX6243,WX5761,WX6244);
and AND2_2164(WX6249,WX6248,WX6177);
and AND2_2165(WX6250,WX5762,WX6251);
and AND2_2166(WX6256,WX6255,WX6177);
and AND2_2167(WX6257,WX5763,WX6258);
and AND2_2168(WX6263,WX6262,WX6177);
and AND2_2169(WX6264,WX5764,WX6265);
and AND2_2170(WX6270,WX6269,WX6177);
and AND2_2171(WX6271,WX5765,WX6272);
and AND2_2172(WX6277,WX6276,WX6177);
and AND2_2173(WX6278,WX5766,WX6279);
and AND2_2174(WX6284,WX6283,WX6177);
and AND2_2175(WX6285,WX5767,WX6286);
and AND2_2176(WX6291,WX6290,WX6177);
and AND2_2177(WX6292,WX5768,WX6293);
and AND2_2178(WX6298,WX6297,WX6177);
and AND2_2179(WX6299,WX5769,WX6300);
and AND2_2180(WX6305,WX6304,WX6177);
and AND2_2181(WX6306,WX5770,WX6307);
and AND2_2182(WX6312,WX6311,WX6177);
and AND2_2183(WX6313,WX5771,WX6314);
and AND2_2184(WX6319,WX6318,WX6177);
and AND2_2185(WX6320,WX5772,WX6321);
and AND2_2186(WX6326,WX6325,WX6177);
and AND2_2187(WX6327,WX5773,WX6328);
and AND2_2188(WX6333,WX6332,WX6177);
and AND2_2189(WX6334,WX5774,WX6335);
and AND2_2190(WX6340,WX6339,WX6177);
and AND2_2191(WX6341,WX5775,WX6342);
and AND2_2192(WX6347,WX6346,WX6177);
and AND2_2193(WX6348,WX5776,WX6349);
and AND2_2194(WX6354,WX6353,WX6177);
and AND2_2195(WX6355,WX5777,WX6356);
and AND2_2196(WX6361,WX6360,WX6177);
and AND2_2197(WX6362,WX5778,WX6363);
and AND2_2198(WX6368,WX6367,WX6177);
and AND2_2199(WX6369,WX5779,WX6370);
and AND2_2200(WX6375,WX6374,WX6177);
and AND2_2201(WX6376,WX5780,WX6377);
and AND2_2202(WX6382,WX6381,WX6177);
and AND2_2203(WX6383,WX5781,WX6384);
and AND2_2204(WX6389,WX6388,WX6177);
and AND2_2205(WX6390,WX5782,WX6391);
and AND2_2206(WX6396,WX6395,WX6177);
and AND2_2207(WX6397,WX5783,WX6398);
and AND2_2208(WX6436,WX6406,WX6435);
and AND2_2209(WX6438,WX6434,WX6435);
and AND2_2210(WX6440,WX6433,WX6435);
and AND2_2211(WX6442,WX6432,WX6435);
and AND2_2212(WX6444,WX6405,WX6435);
and AND2_2213(WX6446,WX6431,WX6435);
and AND2_2214(WX6448,WX6430,WX6435);
and AND2_2215(WX6450,WX6429,WX6435);
and AND2_2216(WX6452,WX6428,WX6435);
and AND2_2217(WX6454,WX6427,WX6435);
and AND2_2218(WX6456,WX6426,WX6435);
and AND2_2219(WX6458,WX6404,WX6435);
and AND2_2220(WX6460,WX6425,WX6435);
and AND2_2221(WX6462,WX6424,WX6435);
and AND2_2222(WX6464,WX6423,WX6435);
and AND2_2223(WX6466,WX6422,WX6435);
and AND2_2224(WX6468,WX6403,WX6435);
and AND2_2225(WX6470,WX6421,WX6435);
and AND2_2226(WX6472,WX6420,WX6435);
and AND2_2227(WX6474,WX6419,WX6435);
and AND2_2228(WX6476,WX6418,WX6435);
and AND2_2229(WX6478,WX6417,WX6435);
and AND2_2230(WX6480,WX6416,WX6435);
and AND2_2231(WX6482,WX6415,WX6435);
and AND2_2232(WX6484,WX6414,WX6435);
and AND2_2233(WX6486,WX6413,WX6435);
and AND2_2234(WX6488,WX6412,WX6435);
and AND2_2235(WX6490,WX6411,WX6435);
and AND2_2236(WX6492,WX6410,WX6435);
and AND2_2237(WX6494,WX6409,WX6435);
and AND2_2238(WX6496,WX6408,WX6435);
and AND2_2239(WX6498,WX6407,WX6435);
and AND2_2240(WX6500,WX6511,WX7468);
and AND2_2241(WX6501,WX6507,WX6502);
and AND2_2242(WX6504,CRC_OUT_4_31,WX7469);
and AND2_2243(WX6505,WX8770,WX6506);
and AND2_2244(WX6508,WX6950,WX7469);
and AND2_2245(WX6509,WX7477,WX6510);
and AND2_2246(WX6514,WX6525,WX7468);
and AND2_2247(WX6515,WX6521,WX6516);
and AND2_2248(WX6518,CRC_OUT_4_30,WX7469);
and AND2_2249(WX6519,WX8777,WX6520);
and AND2_2250(WX6522,WX6952,WX7469);
and AND2_2251(WX6523,WX7484,WX6524);
and AND2_2252(WX6528,WX6539,WX7468);
and AND2_2253(WX6529,WX6535,WX6530);
and AND2_2254(WX6532,CRC_OUT_4_29,WX7469);
and AND2_2255(WX6533,WX8784,WX6534);
and AND2_2256(WX6536,WX6954,WX7469);
and AND2_2257(WX6537,WX7491,WX6538);
and AND2_2258(WX6542,WX6553,WX7468);
and AND2_2259(WX6543,WX6549,WX6544);
and AND2_2260(WX6546,CRC_OUT_4_28,WX7469);
and AND2_2261(WX6547,WX8791,WX6548);
and AND2_2262(WX6550,WX6956,WX7469);
and AND2_2263(WX6551,WX7498,WX6552);
and AND2_2264(WX6556,WX6567,WX7468);
and AND2_2265(WX6557,WX6563,WX6558);
and AND2_2266(WX6560,CRC_OUT_4_27,WX7469);
and AND2_2267(WX6561,WX8798,WX6562);
and AND2_2268(WX6564,WX6958,WX7469);
and AND2_2269(WX6565,WX7505,WX6566);
and AND2_2270(WX6570,WX6581,WX7468);
and AND2_2271(WX6571,WX6577,WX6572);
and AND2_2272(WX6574,CRC_OUT_4_26,WX7469);
and AND2_2273(WX6575,WX8805,WX6576);
and AND2_2274(WX6578,WX6960,WX7469);
and AND2_2275(WX6579,WX7512,WX6580);
and AND2_2276(WX6584,WX6595,WX7468);
and AND2_2277(WX6585,WX6591,WX6586);
and AND2_2278(WX6588,CRC_OUT_4_25,WX7469);
and AND2_2279(WX6589,WX8812,WX6590);
and AND2_2280(WX6592,WX6962,WX7469);
and AND2_2281(WX6593,WX7519,WX6594);
and AND2_2282(WX6598,WX6609,WX7468);
and AND2_2283(WX6599,WX6605,WX6600);
and AND2_2284(WX6602,CRC_OUT_4_24,WX7469);
and AND2_2285(WX6603,WX8819,WX6604);
and AND2_2286(WX6606,WX6964,WX7469);
and AND2_2287(WX6607,WX7526,WX6608);
and AND2_2288(WX6612,WX6623,WX7468);
and AND2_2289(WX6613,WX6619,WX6614);
and AND2_2290(WX6616,CRC_OUT_4_23,WX7469);
and AND2_2291(WX6617,WX8826,WX6618);
and AND2_2292(WX6620,WX6966,WX7469);
and AND2_2293(WX6621,WX7533,WX6622);
and AND2_2294(WX6626,WX6637,WX7468);
and AND2_2295(WX6627,WX6633,WX6628);
and AND2_2296(WX6630,CRC_OUT_4_22,WX7469);
and AND2_2297(WX6631,WX8833,WX6632);
and AND2_2298(WX6634,WX6968,WX7469);
and AND2_2299(WX6635,WX7540,WX6636);
and AND2_2300(WX6640,WX6651,WX7468);
and AND2_2301(WX6641,WX6647,WX6642);
and AND2_2302(WX6644,CRC_OUT_4_21,WX7469);
and AND2_2303(WX6645,WX8840,WX6646);
and AND2_2304(WX6648,WX6970,WX7469);
and AND2_2305(WX6649,WX7547,WX6650);
and AND2_2306(WX6654,WX6665,WX7468);
and AND2_2307(WX6655,WX6661,WX6656);
and AND2_2308(WX6658,CRC_OUT_4_20,WX7469);
and AND2_2309(WX6659,WX8847,WX6660);
and AND2_2310(WX6662,WX6972,WX7469);
and AND2_2311(WX6663,WX7554,WX6664);
and AND2_2312(WX6668,WX6679,WX7468);
and AND2_2313(WX6669,WX6675,WX6670);
and AND2_2314(WX6672,CRC_OUT_4_19,WX7469);
and AND2_2315(WX6673,WX8854,WX6674);
and AND2_2316(WX6676,WX6974,WX7469);
and AND2_2317(WX6677,WX7561,WX6678);
and AND2_2318(WX6682,WX6693,WX7468);
and AND2_2319(WX6683,WX6689,WX6684);
and AND2_2320(WX6686,CRC_OUT_4_18,WX7469);
and AND2_2321(WX6687,WX8861,WX6688);
and AND2_2322(WX6690,WX6976,WX7469);
and AND2_2323(WX6691,WX7568,WX6692);
and AND2_2324(WX6696,WX6707,WX7468);
and AND2_2325(WX6697,WX6703,WX6698);
and AND2_2326(WX6700,CRC_OUT_4_17,WX7469);
and AND2_2327(WX6701,WX8868,WX6702);
and AND2_2328(WX6704,WX6978,WX7469);
and AND2_2329(WX6705,WX7575,WX6706);
and AND2_2330(WX6710,WX6721,WX7468);
and AND2_2331(WX6711,WX6717,WX6712);
and AND2_2332(WX6714,CRC_OUT_4_16,WX7469);
and AND2_2333(WX6715,WX8875,WX6716);
and AND2_2334(WX6718,WX6980,WX7469);
and AND2_2335(WX6719,WX7582,WX6720);
and AND2_2336(WX6724,WX6735,WX7468);
and AND2_2337(WX6725,WX6731,WX6726);
and AND2_2338(WX6728,CRC_OUT_4_15,WX7469);
and AND2_2339(WX6729,WX8882,WX6730);
and AND2_2340(WX6732,WX6982,WX7469);
and AND2_2341(WX6733,WX7589,WX6734);
and AND2_2342(WX6738,WX6749,WX7468);
and AND2_2343(WX6739,WX6745,WX6740);
and AND2_2344(WX6742,CRC_OUT_4_14,WX7469);
and AND2_2345(WX6743,WX8889,WX6744);
and AND2_2346(WX6746,WX6984,WX7469);
and AND2_2347(WX6747,WX7596,WX6748);
and AND2_2348(WX6752,WX6763,WX7468);
and AND2_2349(WX6753,WX6759,WX6754);
and AND2_2350(WX6756,CRC_OUT_4_13,WX7469);
and AND2_2351(WX6757,WX8896,WX6758);
and AND2_2352(WX6760,WX6986,WX7469);
and AND2_2353(WX6761,WX7603,WX6762);
and AND2_2354(WX6766,WX6777,WX7468);
and AND2_2355(WX6767,WX6773,WX6768);
and AND2_2356(WX6770,CRC_OUT_4_12,WX7469);
and AND2_2357(WX6771,WX8903,WX6772);
and AND2_2358(WX6774,WX6988,WX7469);
and AND2_2359(WX6775,WX7610,WX6776);
and AND2_2360(WX6780,WX6791,WX7468);
and AND2_2361(WX6781,WX6787,WX6782);
and AND2_2362(WX6784,CRC_OUT_4_11,WX7469);
and AND2_2363(WX6785,WX8910,WX6786);
and AND2_2364(WX6788,WX6990,WX7469);
and AND2_2365(WX6789,WX7617,WX6790);
and AND2_2366(WX6794,WX6805,WX7468);
and AND2_2367(WX6795,WX6801,WX6796);
and AND2_2368(WX6798,CRC_OUT_4_10,WX7469);
and AND2_2369(WX6799,WX8917,WX6800);
and AND2_2370(WX6802,WX6992,WX7469);
and AND2_2371(WX6803,WX7624,WX6804);
and AND2_2372(WX6808,WX6819,WX7468);
and AND2_2373(WX6809,WX6815,WX6810);
and AND2_2374(WX6812,CRC_OUT_4_9,WX7469);
and AND2_2375(WX6813,WX8924,WX6814);
and AND2_2376(WX6816,WX6994,WX7469);
and AND2_2377(WX6817,WX7631,WX6818);
and AND2_2378(WX6822,WX6833,WX7468);
and AND2_2379(WX6823,WX6829,WX6824);
and AND2_2380(WX6826,CRC_OUT_4_8,WX7469);
and AND2_2381(WX6827,WX8931,WX6828);
and AND2_2382(WX6830,WX6996,WX7469);
and AND2_2383(WX6831,WX7638,WX6832);
and AND2_2384(WX6836,WX6847,WX7468);
and AND2_2385(WX6837,WX6843,WX6838);
and AND2_2386(WX6840,CRC_OUT_4_7,WX7469);
and AND2_2387(WX6841,WX8938,WX6842);
and AND2_2388(WX6844,WX6998,WX7469);
and AND2_2389(WX6845,WX7645,WX6846);
and AND2_2390(WX6850,WX6861,WX7468);
and AND2_2391(WX6851,WX6857,WX6852);
and AND2_2392(WX6854,CRC_OUT_4_6,WX7469);
and AND2_2393(WX6855,WX8945,WX6856);
and AND2_2394(WX6858,WX7000,WX7469);
and AND2_2395(WX6859,WX7652,WX6860);
and AND2_2396(WX6864,WX6875,WX7468);
and AND2_2397(WX6865,WX6871,WX6866);
and AND2_2398(WX6868,CRC_OUT_4_5,WX7469);
and AND2_2399(WX6869,WX8952,WX6870);
and AND2_2400(WX6872,WX7002,WX7469);
and AND2_2401(WX6873,WX7659,WX6874);
and AND2_2402(WX6878,WX6889,WX7468);
and AND2_2403(WX6879,WX6885,WX6880);
and AND2_2404(WX6882,CRC_OUT_4_4,WX7469);
and AND2_2405(WX6883,WX8959,WX6884);
and AND2_2406(WX6886,WX7004,WX7469);
and AND2_2407(WX6887,WX7666,WX6888);
and AND2_2408(WX6892,WX6903,WX7468);
and AND2_2409(WX6893,WX6899,WX6894);
and AND2_2410(WX6896,CRC_OUT_4_3,WX7469);
and AND2_2411(WX6897,WX8966,WX6898);
and AND2_2412(WX6900,WX7006,WX7469);
and AND2_2413(WX6901,WX7673,WX6902);
and AND2_2414(WX6906,WX6917,WX7468);
and AND2_2415(WX6907,WX6913,WX6908);
and AND2_2416(WX6910,CRC_OUT_4_2,WX7469);
and AND2_2417(WX6911,WX8973,WX6912);
and AND2_2418(WX6914,WX7008,WX7469);
and AND2_2419(WX6915,WX7680,WX6916);
and AND2_2420(WX6920,WX6931,WX7468);
and AND2_2421(WX6921,WX6927,WX6922);
and AND2_2422(WX6924,CRC_OUT_4_1,WX7469);
and AND2_2423(WX6925,WX8980,WX6926);
and AND2_2424(WX6928,WX7010,WX7469);
and AND2_2425(WX6929,WX7687,WX6930);
and AND2_2426(WX6934,WX6945,WX7468);
and AND2_2427(WX6935,WX6941,WX6936);
and AND2_2428(WX6938,CRC_OUT_4_0,WX7469);
and AND2_2429(WX6939,WX8987,WX6940);
and AND2_2430(WX6942,WX7012,WX7469);
and AND2_2431(WX6943,WX7694,WX6944);
and AND2_2432(WX6949,WX6952,RESET);
and AND2_2433(WX6951,WX6954,RESET);
and AND2_2434(WX6953,WX6956,RESET);
and AND2_2435(WX6955,WX6958,RESET);
and AND2_2436(WX6957,WX6960,RESET);
and AND2_2437(WX6959,WX6962,RESET);
and AND2_2438(WX6961,WX6964,RESET);
and AND2_2439(WX6963,WX6966,RESET);
and AND2_2440(WX6965,WX6968,RESET);
and AND2_2441(WX6967,WX6970,RESET);
and AND2_2442(WX6969,WX6972,RESET);
and AND2_2443(WX6971,WX6974,RESET);
and AND2_2444(WX6973,WX6976,RESET);
and AND2_2445(WX6975,WX6978,RESET);
and AND2_2446(WX6977,WX6980,RESET);
and AND2_2447(WX6979,WX6982,RESET);
and AND2_2448(WX6981,WX6984,RESET);
and AND2_2449(WX6983,WX6986,RESET);
and AND2_2450(WX6985,WX6988,RESET);
and AND2_2451(WX6987,WX6990,RESET);
and AND2_2452(WX6989,WX6992,RESET);
and AND2_2453(WX6991,WX6994,RESET);
and AND2_2454(WX6993,WX6996,RESET);
and AND2_2455(WX6995,WX6998,RESET);
and AND2_2456(WX6997,WX7000,RESET);
and AND2_2457(WX6999,WX7002,RESET);
and AND2_2458(WX7001,WX7004,RESET);
and AND2_2459(WX7003,WX7006,RESET);
and AND2_2460(WX7005,WX7008,RESET);
and AND2_2461(WX7007,WX7010,RESET);
and AND2_2462(WX7009,WX7012,RESET);
and AND2_2463(WX7011,WX6948,RESET);
and AND2_2464(WX7109,WX6513,RESET);
and AND2_2465(WX7111,WX6527,RESET);
and AND2_2466(WX7113,WX6541,RESET);
and AND2_2467(WX7115,WX6555,RESET);
and AND2_2468(WX7117,WX6569,RESET);
and AND2_2469(WX7119,WX6583,RESET);
and AND2_2470(WX7121,WX6597,RESET);
and AND2_2471(WX7123,WX6611,RESET);
and AND2_2472(WX7125,WX6625,RESET);
and AND2_2473(WX7127,WX6639,RESET);
and AND2_2474(WX7129,WX6653,RESET);
and AND2_2475(WX7131,WX6667,RESET);
and AND2_2476(WX7133,WX6681,RESET);
and AND2_2477(WX7135,WX6695,RESET);
and AND2_2478(WX7137,WX6709,RESET);
and AND2_2479(WX7139,WX6723,RESET);
and AND2_2480(WX7141,WX6737,RESET);
and AND2_2481(WX7143,WX6751,RESET);
and AND2_2482(WX7145,WX6765,RESET);
and AND2_2483(WX7147,WX6779,RESET);
and AND2_2484(WX7149,WX6793,RESET);
and AND2_2485(WX7151,WX6807,RESET);
and AND2_2486(WX7153,WX6821,RESET);
and AND2_2487(WX7155,WX6835,RESET);
and AND2_2488(WX7157,WX6849,RESET);
and AND2_2489(WX7159,WX6863,RESET);
and AND2_2490(WX7161,WX6877,RESET);
and AND2_2491(WX7163,WX6891,RESET);
and AND2_2492(WX7165,WX6905,RESET);
and AND2_2493(WX7167,WX6919,RESET);
and AND2_2494(WX7169,WX6933,RESET);
and AND2_2495(WX7171,WX6947,RESET);
and AND2_2496(WX7173,WX7110,RESET);
and AND2_2497(WX7175,WX7112,RESET);
and AND2_2498(WX7177,WX7114,RESET);
and AND2_2499(WX7179,WX7116,RESET);
and AND2_2500(WX7181,WX7118,RESET);
and AND2_2501(WX7183,WX7120,RESET);
and AND2_2502(WX7185,WX7122,RESET);
and AND2_2503(WX7187,WX7124,RESET);
and AND2_2504(WX7189,WX7126,RESET);
and AND2_2505(WX7191,WX7128,RESET);
and AND2_2506(WX7193,WX7130,RESET);
and AND2_2507(WX7195,WX7132,RESET);
and AND2_2508(WX7197,WX7134,RESET);
and AND2_2509(WX7199,WX7136,RESET);
and AND2_2510(WX7201,WX7138,RESET);
and AND2_2511(WX7203,WX7140,RESET);
and AND2_2512(WX7205,WX7142,RESET);
and AND2_2513(WX7207,WX7144,RESET);
and AND2_2514(WX7209,WX7146,RESET);
and AND2_2515(WX7211,WX7148,RESET);
and AND2_2516(WX7213,WX7150,RESET);
and AND2_2517(WX7215,WX7152,RESET);
and AND2_2518(WX7217,WX7154,RESET);
and AND2_2519(WX7219,WX7156,RESET);
and AND2_2520(WX7221,WX7158,RESET);
and AND2_2521(WX7223,WX7160,RESET);
and AND2_2522(WX7225,WX7162,RESET);
and AND2_2523(WX7227,WX7164,RESET);
and AND2_2524(WX7229,WX7166,RESET);
and AND2_2525(WX7231,WX7168,RESET);
and AND2_2526(WX7233,WX7170,RESET);
and AND2_2527(WX7235,WX7172,RESET);
and AND2_2528(WX7237,WX7174,RESET);
and AND2_2529(WX7239,WX7176,RESET);
and AND2_2530(WX7241,WX7178,RESET);
and AND2_2531(WX7243,WX7180,RESET);
and AND2_2532(WX7245,WX7182,RESET);
and AND2_2533(WX7247,WX7184,RESET);
and AND2_2534(WX7249,WX7186,RESET);
and AND2_2535(WX7251,WX7188,RESET);
and AND2_2536(WX7253,WX7190,RESET);
and AND2_2537(WX7255,WX7192,RESET);
and AND2_2538(WX7257,WX7194,RESET);
and AND2_2539(WX7259,WX7196,RESET);
and AND2_2540(WX7261,WX7198,RESET);
and AND2_2541(WX7263,WX7200,RESET);
and AND2_2542(WX7265,WX7202,RESET);
and AND2_2543(WX7267,WX7204,RESET);
and AND2_2544(WX7269,WX7206,RESET);
and AND2_2545(WX7271,WX7208,RESET);
and AND2_2546(WX7273,WX7210,RESET);
and AND2_2547(WX7275,WX7212,RESET);
and AND2_2548(WX7277,WX7214,RESET);
and AND2_2549(WX7279,WX7216,RESET);
and AND2_2550(WX7281,WX7218,RESET);
and AND2_2551(WX7283,WX7220,RESET);
and AND2_2552(WX7285,WX7222,RESET);
and AND2_2553(WX7287,WX7224,RESET);
and AND2_2554(WX7289,WX7226,RESET);
and AND2_2555(WX7291,WX7228,RESET);
and AND2_2556(WX7293,WX7230,RESET);
and AND2_2557(WX7295,WX7232,RESET);
and AND2_2558(WX7297,WX7234,RESET);
and AND2_2559(WX7299,WX7236,RESET);
and AND2_2560(WX7301,WX7238,RESET);
and AND2_2561(WX7303,WX7240,RESET);
and AND2_2562(WX7305,WX7242,RESET);
and AND2_2563(WX7307,WX7244,RESET);
and AND2_2564(WX7309,WX7246,RESET);
and AND2_2565(WX7311,WX7248,RESET);
and AND2_2566(WX7313,WX7250,RESET);
and AND2_2567(WX7315,WX7252,RESET);
and AND2_2568(WX7317,WX7254,RESET);
and AND2_2569(WX7319,WX7256,RESET);
and AND2_2570(WX7321,WX7258,RESET);
and AND2_2571(WX7323,WX7260,RESET);
and AND2_2572(WX7325,WX7262,RESET);
and AND2_2573(WX7327,WX7264,RESET);
and AND2_2574(WX7329,WX7266,RESET);
and AND2_2575(WX7331,WX7268,RESET);
and AND2_2576(WX7333,WX7270,RESET);
and AND2_2577(WX7335,WX7272,RESET);
and AND2_2578(WX7337,WX7274,RESET);
and AND2_2579(WX7339,WX7276,RESET);
and AND2_2580(WX7341,WX7278,RESET);
and AND2_2581(WX7343,WX7280,RESET);
and AND2_2582(WX7345,WX7282,RESET);
and AND2_2583(WX7347,WX7284,RESET);
and AND2_2584(WX7349,WX7286,RESET);
and AND2_2585(WX7351,WX7288,RESET);
and AND2_2586(WX7353,WX7290,RESET);
and AND2_2587(WX7355,WX7292,RESET);
and AND2_2588(WX7357,WX7294,RESET);
and AND2_2589(WX7359,WX7296,RESET);
and AND2_2590(WX7361,WX7298,RESET);
and AND2_2591(WX7363,WX7300,RESET);
and AND2_2592(WX7472,WX7471,WX7470);
and AND2_2593(WX7473,WX7045,WX7474);
and AND2_2594(WX7479,WX7478,WX7470);
and AND2_2595(WX7480,WX7046,WX7481);
and AND2_2596(WX7486,WX7485,WX7470);
and AND2_2597(WX7487,WX7047,WX7488);
and AND2_2598(WX7493,WX7492,WX7470);
and AND2_2599(WX7494,WX7048,WX7495);
and AND2_2600(WX7500,WX7499,WX7470);
and AND2_2601(WX7501,WX7049,WX7502);
and AND2_2602(WX7507,WX7506,WX7470);
and AND2_2603(WX7508,WX7050,WX7509);
and AND2_2604(WX7514,WX7513,WX7470);
and AND2_2605(WX7515,WX7051,WX7516);
and AND2_2606(WX7521,WX7520,WX7470);
and AND2_2607(WX7522,WX7052,WX7523);
and AND2_2608(WX7528,WX7527,WX7470);
and AND2_2609(WX7529,WX7053,WX7530);
and AND2_2610(WX7535,WX7534,WX7470);
and AND2_2611(WX7536,WX7054,WX7537);
and AND2_2612(WX7542,WX7541,WX7470);
and AND2_2613(WX7543,WX7055,WX7544);
and AND2_2614(WX7549,WX7548,WX7470);
and AND2_2615(WX7550,WX7056,WX7551);
and AND2_2616(WX7556,WX7555,WX7470);
and AND2_2617(WX7557,WX7057,WX7558);
and AND2_2618(WX7563,WX7562,WX7470);
and AND2_2619(WX7564,WX7058,WX7565);
and AND2_2620(WX7570,WX7569,WX7470);
and AND2_2621(WX7571,WX7059,WX7572);
and AND2_2622(WX7577,WX7576,WX7470);
and AND2_2623(WX7578,WX7060,WX7579);
and AND2_2624(WX7584,WX7583,WX7470);
and AND2_2625(WX7585,WX7061,WX7586);
and AND2_2626(WX7591,WX7590,WX7470);
and AND2_2627(WX7592,WX7062,WX7593);
and AND2_2628(WX7598,WX7597,WX7470);
and AND2_2629(WX7599,WX7063,WX7600);
and AND2_2630(WX7605,WX7604,WX7470);
and AND2_2631(WX7606,WX7064,WX7607);
and AND2_2632(WX7612,WX7611,WX7470);
and AND2_2633(WX7613,WX7065,WX7614);
and AND2_2634(WX7619,WX7618,WX7470);
and AND2_2635(WX7620,WX7066,WX7621);
and AND2_2636(WX7626,WX7625,WX7470);
and AND2_2637(WX7627,WX7067,WX7628);
and AND2_2638(WX7633,WX7632,WX7470);
and AND2_2639(WX7634,WX7068,WX7635);
and AND2_2640(WX7640,WX7639,WX7470);
and AND2_2641(WX7641,WX7069,WX7642);
and AND2_2642(WX7647,WX7646,WX7470);
and AND2_2643(WX7648,WX7070,WX7649);
and AND2_2644(WX7654,WX7653,WX7470);
and AND2_2645(WX7655,WX7071,WX7656);
and AND2_2646(WX7661,WX7660,WX7470);
and AND2_2647(WX7662,WX7072,WX7663);
and AND2_2648(WX7668,WX7667,WX7470);
and AND2_2649(WX7669,WX7073,WX7670);
and AND2_2650(WX7675,WX7674,WX7470);
and AND2_2651(WX7676,WX7074,WX7677);
and AND2_2652(WX7682,WX7681,WX7470);
and AND2_2653(WX7683,WX7075,WX7684);
and AND2_2654(WX7689,WX7688,WX7470);
and AND2_2655(WX7690,WX7076,WX7691);
and AND2_2656(WX7729,WX7699,WX7728);
and AND2_2657(WX7731,WX7727,WX7728);
and AND2_2658(WX7733,WX7726,WX7728);
and AND2_2659(WX7735,WX7725,WX7728);
and AND2_2660(WX7737,WX7698,WX7728);
and AND2_2661(WX7739,WX7724,WX7728);
and AND2_2662(WX7741,WX7723,WX7728);
and AND2_2663(WX7743,WX7722,WX7728);
and AND2_2664(WX7745,WX7721,WX7728);
and AND2_2665(WX7747,WX7720,WX7728);
and AND2_2666(WX7749,WX7719,WX7728);
and AND2_2667(WX7751,WX7697,WX7728);
and AND2_2668(WX7753,WX7718,WX7728);
and AND2_2669(WX7755,WX7717,WX7728);
and AND2_2670(WX7757,WX7716,WX7728);
and AND2_2671(WX7759,WX7715,WX7728);
and AND2_2672(WX7761,WX7696,WX7728);
and AND2_2673(WX7763,WX7714,WX7728);
and AND2_2674(WX7765,WX7713,WX7728);
and AND2_2675(WX7767,WX7712,WX7728);
and AND2_2676(WX7769,WX7711,WX7728);
and AND2_2677(WX7771,WX7710,WX7728);
and AND2_2678(WX7773,WX7709,WX7728);
and AND2_2679(WX7775,WX7708,WX7728);
and AND2_2680(WX7777,WX7707,WX7728);
and AND2_2681(WX7779,WX7706,WX7728);
and AND2_2682(WX7781,WX7705,WX7728);
and AND2_2683(WX7783,WX7704,WX7728);
and AND2_2684(WX7785,WX7703,WX7728);
and AND2_2685(WX7787,WX7702,WX7728);
and AND2_2686(WX7789,WX7701,WX7728);
and AND2_2687(WX7791,WX7700,WX7728);
and AND2_2688(WX7793,WX7804,WX8761);
and AND2_2689(WX7794,WX7800,WX7795);
and AND2_2690(WX7797,CRC_OUT_3_31,WX8762);
and AND2_2691(WX7798,WX10063,WX7799);
and AND2_2692(WX7801,WX8243,WX8762);
and AND2_2693(WX7802,WX8770,WX7803);
and AND2_2694(WX7807,WX7818,WX8761);
and AND2_2695(WX7808,WX7814,WX7809);
and AND2_2696(WX7811,CRC_OUT_3_30,WX8762);
and AND2_2697(WX7812,WX10070,WX7813);
and AND2_2698(WX7815,WX8245,WX8762);
and AND2_2699(WX7816,WX8777,WX7817);
and AND2_2700(WX7821,WX7832,WX8761);
and AND2_2701(WX7822,WX7828,WX7823);
and AND2_2702(WX7825,CRC_OUT_3_29,WX8762);
and AND2_2703(WX7826,WX10077,WX7827);
and AND2_2704(WX7829,WX8247,WX8762);
and AND2_2705(WX7830,WX8784,WX7831);
and AND2_2706(WX7835,WX7846,WX8761);
and AND2_2707(WX7836,WX7842,WX7837);
and AND2_2708(WX7839,CRC_OUT_3_28,WX8762);
and AND2_2709(WX7840,WX10084,WX7841);
and AND2_2710(WX7843,WX8249,WX8762);
and AND2_2711(WX7844,WX8791,WX7845);
and AND2_2712(WX7849,WX7860,WX8761);
and AND2_2713(WX7850,WX7856,WX7851);
and AND2_2714(WX7853,CRC_OUT_3_27,WX8762);
and AND2_2715(WX7854,WX10091,WX7855);
and AND2_2716(WX7857,WX8251,WX8762);
and AND2_2717(WX7858,WX8798,WX7859);
and AND2_2718(WX7863,WX7874,WX8761);
and AND2_2719(WX7864,WX7870,WX7865);
and AND2_2720(WX7867,CRC_OUT_3_26,WX8762);
and AND2_2721(WX7868,WX10098,WX7869);
and AND2_2722(WX7871,WX8253,WX8762);
and AND2_2723(WX7872,WX8805,WX7873);
and AND2_2724(WX7877,WX7888,WX8761);
and AND2_2725(WX7878,WX7884,WX7879);
and AND2_2726(WX7881,CRC_OUT_3_25,WX8762);
and AND2_2727(WX7882,WX10105,WX7883);
and AND2_2728(WX7885,WX8255,WX8762);
and AND2_2729(WX7886,WX8812,WX7887);
and AND2_2730(WX7891,WX7902,WX8761);
and AND2_2731(WX7892,WX7898,WX7893);
and AND2_2732(WX7895,CRC_OUT_3_24,WX8762);
and AND2_2733(WX7896,WX10112,WX7897);
and AND2_2734(WX7899,WX8257,WX8762);
and AND2_2735(WX7900,WX8819,WX7901);
and AND2_2736(WX7905,WX7916,WX8761);
and AND2_2737(WX7906,WX7912,WX7907);
and AND2_2738(WX7909,CRC_OUT_3_23,WX8762);
and AND2_2739(WX7910,WX10119,WX7911);
and AND2_2740(WX7913,WX8259,WX8762);
and AND2_2741(WX7914,WX8826,WX7915);
and AND2_2742(WX7919,WX7930,WX8761);
and AND2_2743(WX7920,WX7926,WX7921);
and AND2_2744(WX7923,CRC_OUT_3_22,WX8762);
and AND2_2745(WX7924,WX10126,WX7925);
and AND2_2746(WX7927,WX8261,WX8762);
and AND2_2747(WX7928,WX8833,WX7929);
and AND2_2748(WX7933,WX7944,WX8761);
and AND2_2749(WX7934,WX7940,WX7935);
and AND2_2750(WX7937,CRC_OUT_3_21,WX8762);
and AND2_2751(WX7938,WX10133,WX7939);
and AND2_2752(WX7941,WX8263,WX8762);
and AND2_2753(WX7942,WX8840,WX7943);
and AND2_2754(WX7947,WX7958,WX8761);
and AND2_2755(WX7948,WX7954,WX7949);
and AND2_2756(WX7951,CRC_OUT_3_20,WX8762);
and AND2_2757(WX7952,WX10140,WX7953);
and AND2_2758(WX7955,WX8265,WX8762);
and AND2_2759(WX7956,WX8847,WX7957);
and AND2_2760(WX7961,WX7972,WX8761);
and AND2_2761(WX7962,WX7968,WX7963);
and AND2_2762(WX7965,CRC_OUT_3_19,WX8762);
and AND2_2763(WX7966,WX10147,WX7967);
and AND2_2764(WX7969,WX8267,WX8762);
and AND2_2765(WX7970,WX8854,WX7971);
and AND2_2766(WX7975,WX7986,WX8761);
and AND2_2767(WX7976,WX7982,WX7977);
and AND2_2768(WX7979,CRC_OUT_3_18,WX8762);
and AND2_2769(WX7980,WX10154,WX7981);
and AND2_2770(WX7983,WX8269,WX8762);
and AND2_2771(WX7984,WX8861,WX7985);
and AND2_2772(WX7989,WX8000,WX8761);
and AND2_2773(WX7990,WX7996,WX7991);
and AND2_2774(WX7993,CRC_OUT_3_17,WX8762);
and AND2_2775(WX7994,WX10161,WX7995);
and AND2_2776(WX7997,WX8271,WX8762);
and AND2_2777(WX7998,WX8868,WX7999);
and AND2_2778(WX8003,WX8014,WX8761);
and AND2_2779(WX8004,WX8010,WX8005);
and AND2_2780(WX8007,CRC_OUT_3_16,WX8762);
and AND2_2781(WX8008,WX10168,WX8009);
and AND2_2782(WX8011,WX8273,WX8762);
and AND2_2783(WX8012,WX8875,WX8013);
and AND2_2784(WX8017,WX8028,WX8761);
and AND2_2785(WX8018,WX8024,WX8019);
and AND2_2786(WX8021,CRC_OUT_3_15,WX8762);
and AND2_2787(WX8022,WX10175,WX8023);
and AND2_2788(WX8025,WX8275,WX8762);
and AND2_2789(WX8026,WX8882,WX8027);
and AND2_2790(WX8031,WX8042,WX8761);
and AND2_2791(WX8032,WX8038,WX8033);
and AND2_2792(WX8035,CRC_OUT_3_14,WX8762);
and AND2_2793(WX8036,WX10182,WX8037);
and AND2_2794(WX8039,WX8277,WX8762);
and AND2_2795(WX8040,WX8889,WX8041);
and AND2_2796(WX8045,WX8056,WX8761);
and AND2_2797(WX8046,WX8052,WX8047);
and AND2_2798(WX8049,CRC_OUT_3_13,WX8762);
and AND2_2799(WX8050,WX10189,WX8051);
and AND2_2800(WX8053,WX8279,WX8762);
and AND2_2801(WX8054,WX8896,WX8055);
and AND2_2802(WX8059,WX8070,WX8761);
and AND2_2803(WX8060,WX8066,WX8061);
and AND2_2804(WX8063,CRC_OUT_3_12,WX8762);
and AND2_2805(WX8064,WX10196,WX8065);
and AND2_2806(WX8067,WX8281,WX8762);
and AND2_2807(WX8068,WX8903,WX8069);
and AND2_2808(WX8073,WX8084,WX8761);
and AND2_2809(WX8074,WX8080,WX8075);
and AND2_2810(WX8077,CRC_OUT_3_11,WX8762);
and AND2_2811(WX8078,WX10203,WX8079);
and AND2_2812(WX8081,WX8283,WX8762);
and AND2_2813(WX8082,WX8910,WX8083);
and AND2_2814(WX8087,WX8098,WX8761);
and AND2_2815(WX8088,WX8094,WX8089);
and AND2_2816(WX8091,CRC_OUT_3_10,WX8762);
and AND2_2817(WX8092,WX10210,WX8093);
and AND2_2818(WX8095,WX8285,WX8762);
and AND2_2819(WX8096,WX8917,WX8097);
and AND2_2820(WX8101,WX8112,WX8761);
and AND2_2821(WX8102,WX8108,WX8103);
and AND2_2822(WX8105,CRC_OUT_3_9,WX8762);
and AND2_2823(WX8106,WX10217,WX8107);
and AND2_2824(WX8109,WX8287,WX8762);
and AND2_2825(WX8110,WX8924,WX8111);
and AND2_2826(WX8115,WX8126,WX8761);
and AND2_2827(WX8116,WX8122,WX8117);
and AND2_2828(WX8119,CRC_OUT_3_8,WX8762);
and AND2_2829(WX8120,WX10224,WX8121);
and AND2_2830(WX8123,WX8289,WX8762);
and AND2_2831(WX8124,WX8931,WX8125);
and AND2_2832(WX8129,WX8140,WX8761);
and AND2_2833(WX8130,WX8136,WX8131);
and AND2_2834(WX8133,CRC_OUT_3_7,WX8762);
and AND2_2835(WX8134,WX10231,WX8135);
and AND2_2836(WX8137,WX8291,WX8762);
and AND2_2837(WX8138,WX8938,WX8139);
and AND2_2838(WX8143,WX8154,WX8761);
and AND2_2839(WX8144,WX8150,WX8145);
and AND2_2840(WX8147,CRC_OUT_3_6,WX8762);
and AND2_2841(WX8148,WX10238,WX8149);
and AND2_2842(WX8151,WX8293,WX8762);
and AND2_2843(WX8152,WX8945,WX8153);
and AND2_2844(WX8157,WX8168,WX8761);
and AND2_2845(WX8158,WX8164,WX8159);
and AND2_2846(WX8161,CRC_OUT_3_5,WX8762);
and AND2_2847(WX8162,WX10245,WX8163);
and AND2_2848(WX8165,WX8295,WX8762);
and AND2_2849(WX8166,WX8952,WX8167);
and AND2_2850(WX8171,WX8182,WX8761);
and AND2_2851(WX8172,WX8178,WX8173);
and AND2_2852(WX8175,CRC_OUT_3_4,WX8762);
and AND2_2853(WX8176,WX10252,WX8177);
and AND2_2854(WX8179,WX8297,WX8762);
and AND2_2855(WX8180,WX8959,WX8181);
and AND2_2856(WX8185,WX8196,WX8761);
and AND2_2857(WX8186,WX8192,WX8187);
and AND2_2858(WX8189,CRC_OUT_3_3,WX8762);
and AND2_2859(WX8190,WX10259,WX8191);
and AND2_2860(WX8193,WX8299,WX8762);
and AND2_2861(WX8194,WX8966,WX8195);
and AND2_2862(WX8199,WX8210,WX8761);
and AND2_2863(WX8200,WX8206,WX8201);
and AND2_2864(WX8203,CRC_OUT_3_2,WX8762);
and AND2_2865(WX8204,WX10266,WX8205);
and AND2_2866(WX8207,WX8301,WX8762);
and AND2_2867(WX8208,WX8973,WX8209);
and AND2_2868(WX8213,WX8224,WX8761);
and AND2_2869(WX8214,WX8220,WX8215);
and AND2_2870(WX8217,CRC_OUT_3_1,WX8762);
and AND2_2871(WX8218,WX10273,WX8219);
and AND2_2872(WX8221,WX8303,WX8762);
and AND2_2873(WX8222,WX8980,WX8223);
and AND2_2874(WX8227,WX8238,WX8761);
and AND2_2875(WX8228,WX8234,WX8229);
and AND2_2876(WX8231,CRC_OUT_3_0,WX8762);
and AND2_2877(WX8232,WX10280,WX8233);
and AND2_2878(WX8235,WX8305,WX8762);
and AND2_2879(WX8236,WX8987,WX8237);
and AND2_2880(WX8242,WX8245,RESET);
and AND2_2881(WX8244,WX8247,RESET);
and AND2_2882(WX8246,WX8249,RESET);
and AND2_2883(WX8248,WX8251,RESET);
and AND2_2884(WX8250,WX8253,RESET);
and AND2_2885(WX8252,WX8255,RESET);
and AND2_2886(WX8254,WX8257,RESET);
and AND2_2887(WX8256,WX8259,RESET);
and AND2_2888(WX8258,WX8261,RESET);
and AND2_2889(WX8260,WX8263,RESET);
and AND2_2890(WX8262,WX8265,RESET);
and AND2_2891(WX8264,WX8267,RESET);
and AND2_2892(WX8266,WX8269,RESET);
and AND2_2893(WX8268,WX8271,RESET);
and AND2_2894(WX8270,WX8273,RESET);
and AND2_2895(WX8272,WX8275,RESET);
and AND2_2896(WX8274,WX8277,RESET);
and AND2_2897(WX8276,WX8279,RESET);
and AND2_2898(WX8278,WX8281,RESET);
and AND2_2899(WX8280,WX8283,RESET);
and AND2_2900(WX8282,WX8285,RESET);
and AND2_2901(WX8284,WX8287,RESET);
and AND2_2902(WX8286,WX8289,RESET);
and AND2_2903(WX8288,WX8291,RESET);
and AND2_2904(WX8290,WX8293,RESET);
and AND2_2905(WX8292,WX8295,RESET);
and AND2_2906(WX8294,WX8297,RESET);
and AND2_2907(WX8296,WX8299,RESET);
and AND2_2908(WX8298,WX8301,RESET);
and AND2_2909(WX8300,WX8303,RESET);
and AND2_2910(WX8302,WX8305,RESET);
and AND2_2911(WX8304,WX8241,RESET);
and AND2_2912(WX8402,WX7806,RESET);
and AND2_2913(WX8404,WX7820,RESET);
and AND2_2914(WX8406,WX7834,RESET);
and AND2_2915(WX8408,WX7848,RESET);
and AND2_2916(WX8410,WX7862,RESET);
and AND2_2917(WX8412,WX7876,RESET);
and AND2_2918(WX8414,WX7890,RESET);
and AND2_2919(WX8416,WX7904,RESET);
and AND2_2920(WX8418,WX7918,RESET);
and AND2_2921(WX8420,WX7932,RESET);
and AND2_2922(WX8422,WX7946,RESET);
and AND2_2923(WX8424,WX7960,RESET);
and AND2_2924(WX8426,WX7974,RESET);
and AND2_2925(WX8428,WX7988,RESET);
and AND2_2926(WX8430,WX8002,RESET);
and AND2_2927(WX8432,WX8016,RESET);
and AND2_2928(WX8434,WX8030,RESET);
and AND2_2929(WX8436,WX8044,RESET);
and AND2_2930(WX8438,WX8058,RESET);
and AND2_2931(WX8440,WX8072,RESET);
and AND2_2932(WX8442,WX8086,RESET);
and AND2_2933(WX8444,WX8100,RESET);
and AND2_2934(WX8446,WX8114,RESET);
and AND2_2935(WX8448,WX8128,RESET);
and AND2_2936(WX8450,WX8142,RESET);
and AND2_2937(WX8452,WX8156,RESET);
and AND2_2938(WX8454,WX8170,RESET);
and AND2_2939(WX8456,WX8184,RESET);
and AND2_2940(WX8458,WX8198,RESET);
and AND2_2941(WX8460,WX8212,RESET);
and AND2_2942(WX8462,WX8226,RESET);
and AND2_2943(WX8464,WX8240,RESET);
and AND2_2944(WX8466,WX8403,RESET);
and AND2_2945(WX8468,WX8405,RESET);
and AND2_2946(WX8470,WX8407,RESET);
and AND2_2947(WX8472,WX8409,RESET);
and AND2_2948(WX8474,WX8411,RESET);
and AND2_2949(WX8476,WX8413,RESET);
and AND2_2950(WX8478,WX8415,RESET);
and AND2_2951(WX8480,WX8417,RESET);
and AND2_2952(WX8482,WX8419,RESET);
and AND2_2953(WX8484,WX8421,RESET);
and AND2_2954(WX8486,WX8423,RESET);
and AND2_2955(WX8488,WX8425,RESET);
and AND2_2956(WX8490,WX8427,RESET);
and AND2_2957(WX8492,WX8429,RESET);
and AND2_2958(WX8494,WX8431,RESET);
and AND2_2959(WX8496,WX8433,RESET);
and AND2_2960(WX8498,WX8435,RESET);
and AND2_2961(WX8500,WX8437,RESET);
and AND2_2962(WX8502,WX8439,RESET);
and AND2_2963(WX8504,WX8441,RESET);
and AND2_2964(WX8506,WX8443,RESET);
and AND2_2965(WX8508,WX8445,RESET);
and AND2_2966(WX8510,WX8447,RESET);
and AND2_2967(WX8512,WX8449,RESET);
and AND2_2968(WX8514,WX8451,RESET);
and AND2_2969(WX8516,WX8453,RESET);
and AND2_2970(WX8518,WX8455,RESET);
and AND2_2971(WX8520,WX8457,RESET);
and AND2_2972(WX8522,WX8459,RESET);
and AND2_2973(WX8524,WX8461,RESET);
and AND2_2974(WX8526,WX8463,RESET);
and AND2_2975(WX8528,WX8465,RESET);
and AND2_2976(WX8530,WX8467,RESET);
and AND2_2977(WX8532,WX8469,RESET);
and AND2_2978(WX8534,WX8471,RESET);
and AND2_2979(WX8536,WX8473,RESET);
and AND2_2980(WX8538,WX8475,RESET);
and AND2_2981(WX8540,WX8477,RESET);
and AND2_2982(WX8542,WX8479,RESET);
and AND2_2983(WX8544,WX8481,RESET);
and AND2_2984(WX8546,WX8483,RESET);
and AND2_2985(WX8548,WX8485,RESET);
and AND2_2986(WX8550,WX8487,RESET);
and AND2_2987(WX8552,WX8489,RESET);
and AND2_2988(WX8554,WX8491,RESET);
and AND2_2989(WX8556,WX8493,RESET);
and AND2_2990(WX8558,WX8495,RESET);
and AND2_2991(WX8560,WX8497,RESET);
and AND2_2992(WX8562,WX8499,RESET);
and AND2_2993(WX8564,WX8501,RESET);
and AND2_2994(WX8566,WX8503,RESET);
and AND2_2995(WX8568,WX8505,RESET);
and AND2_2996(WX8570,WX8507,RESET);
and AND2_2997(WX8572,WX8509,RESET);
and AND2_2998(WX8574,WX8511,RESET);
and AND2_2999(WX8576,WX8513,RESET);
and AND2_3000(WX8578,WX8515,RESET);
and AND2_3001(WX8580,WX8517,RESET);
and AND2_3002(WX8582,WX8519,RESET);
and AND2_3003(WX8584,WX8521,RESET);
and AND2_3004(WX8586,WX8523,RESET);
and AND2_3005(WX8588,WX8525,RESET);
and AND2_3006(WX8590,WX8527,RESET);
and AND2_3007(WX8592,WX8529,RESET);
and AND2_3008(WX8594,WX8531,RESET);
and AND2_3009(WX8596,WX8533,RESET);
and AND2_3010(WX8598,WX8535,RESET);
and AND2_3011(WX8600,WX8537,RESET);
and AND2_3012(WX8602,WX8539,RESET);
and AND2_3013(WX8604,WX8541,RESET);
and AND2_3014(WX8606,WX8543,RESET);
and AND2_3015(WX8608,WX8545,RESET);
and AND2_3016(WX8610,WX8547,RESET);
and AND2_3017(WX8612,WX8549,RESET);
and AND2_3018(WX8614,WX8551,RESET);
and AND2_3019(WX8616,WX8553,RESET);
and AND2_3020(WX8618,WX8555,RESET);
and AND2_3021(WX8620,WX8557,RESET);
and AND2_3022(WX8622,WX8559,RESET);
and AND2_3023(WX8624,WX8561,RESET);
and AND2_3024(WX8626,WX8563,RESET);
and AND2_3025(WX8628,WX8565,RESET);
and AND2_3026(WX8630,WX8567,RESET);
and AND2_3027(WX8632,WX8569,RESET);
and AND2_3028(WX8634,WX8571,RESET);
and AND2_3029(WX8636,WX8573,RESET);
and AND2_3030(WX8638,WX8575,RESET);
and AND2_3031(WX8640,WX8577,RESET);
and AND2_3032(WX8642,WX8579,RESET);
and AND2_3033(WX8644,WX8581,RESET);
and AND2_3034(WX8646,WX8583,RESET);
and AND2_3035(WX8648,WX8585,RESET);
and AND2_3036(WX8650,WX8587,RESET);
and AND2_3037(WX8652,WX8589,RESET);
and AND2_3038(WX8654,WX8591,RESET);
and AND2_3039(WX8656,WX8593,RESET);
and AND2_3040(WX8765,WX8764,WX8763);
and AND2_3041(WX8766,WX8338,WX8767);
and AND2_3042(WX8772,WX8771,WX8763);
and AND2_3043(WX8773,WX8339,WX8774);
and AND2_3044(WX8779,WX8778,WX8763);
and AND2_3045(WX8780,WX8340,WX8781);
and AND2_3046(WX8786,WX8785,WX8763);
and AND2_3047(WX8787,WX8341,WX8788);
and AND2_3048(WX8793,WX8792,WX8763);
and AND2_3049(WX8794,WX8342,WX8795);
and AND2_3050(WX8800,WX8799,WX8763);
and AND2_3051(WX8801,WX8343,WX8802);
and AND2_3052(WX8807,WX8806,WX8763);
and AND2_3053(WX8808,WX8344,WX8809);
and AND2_3054(WX8814,WX8813,WX8763);
and AND2_3055(WX8815,WX8345,WX8816);
and AND2_3056(WX8821,WX8820,WX8763);
and AND2_3057(WX8822,WX8346,WX8823);
and AND2_3058(WX8828,WX8827,WX8763);
and AND2_3059(WX8829,WX8347,WX8830);
and AND2_3060(WX8835,WX8834,WX8763);
and AND2_3061(WX8836,WX8348,WX8837);
and AND2_3062(WX8842,WX8841,WX8763);
and AND2_3063(WX8843,WX8349,WX8844);
and AND2_3064(WX8849,WX8848,WX8763);
and AND2_3065(WX8850,WX8350,WX8851);
and AND2_3066(WX8856,WX8855,WX8763);
and AND2_3067(WX8857,WX8351,WX8858);
and AND2_3068(WX8863,WX8862,WX8763);
and AND2_3069(WX8864,WX8352,WX8865);
and AND2_3070(WX8870,WX8869,WX8763);
and AND2_3071(WX8871,WX8353,WX8872);
and AND2_3072(WX8877,WX8876,WX8763);
and AND2_3073(WX8878,WX8354,WX8879);
and AND2_3074(WX8884,WX8883,WX8763);
and AND2_3075(WX8885,WX8355,WX8886);
and AND2_3076(WX8891,WX8890,WX8763);
and AND2_3077(WX8892,WX8356,WX8893);
and AND2_3078(WX8898,WX8897,WX8763);
and AND2_3079(WX8899,WX8357,WX8900);
and AND2_3080(WX8905,WX8904,WX8763);
and AND2_3081(WX8906,WX8358,WX8907);
and AND2_3082(WX8912,WX8911,WX8763);
and AND2_3083(WX8913,WX8359,WX8914);
and AND2_3084(WX8919,WX8918,WX8763);
and AND2_3085(WX8920,WX8360,WX8921);
and AND2_3086(WX8926,WX8925,WX8763);
and AND2_3087(WX8927,WX8361,WX8928);
and AND2_3088(WX8933,WX8932,WX8763);
and AND2_3089(WX8934,WX8362,WX8935);
and AND2_3090(WX8940,WX8939,WX8763);
and AND2_3091(WX8941,WX8363,WX8942);
and AND2_3092(WX8947,WX8946,WX8763);
and AND2_3093(WX8948,WX8364,WX8949);
and AND2_3094(WX8954,WX8953,WX8763);
and AND2_3095(WX8955,WX8365,WX8956);
and AND2_3096(WX8961,WX8960,WX8763);
and AND2_3097(WX8962,WX8366,WX8963);
and AND2_3098(WX8968,WX8967,WX8763);
and AND2_3099(WX8969,WX8367,WX8970);
and AND2_3100(WX8975,WX8974,WX8763);
and AND2_3101(WX8976,WX8368,WX8977);
and AND2_3102(WX8982,WX8981,WX8763);
and AND2_3103(WX8983,WX8369,WX8984);
and AND2_3104(WX9022,WX8992,WX9021);
and AND2_3105(WX9024,WX9020,WX9021);
and AND2_3106(WX9026,WX9019,WX9021);
and AND2_3107(WX9028,WX9018,WX9021);
and AND2_3108(WX9030,WX8991,WX9021);
and AND2_3109(WX9032,WX9017,WX9021);
and AND2_3110(WX9034,WX9016,WX9021);
and AND2_3111(WX9036,WX9015,WX9021);
and AND2_3112(WX9038,WX9014,WX9021);
and AND2_3113(WX9040,WX9013,WX9021);
and AND2_3114(WX9042,WX9012,WX9021);
and AND2_3115(WX9044,WX8990,WX9021);
and AND2_3116(WX9046,WX9011,WX9021);
and AND2_3117(WX9048,WX9010,WX9021);
and AND2_3118(WX9050,WX9009,WX9021);
and AND2_3119(WX9052,WX9008,WX9021);
and AND2_3120(WX9054,WX8989,WX9021);
and AND2_3121(WX9056,WX9007,WX9021);
and AND2_3122(WX9058,WX9006,WX9021);
and AND2_3123(WX9060,WX9005,WX9021);
and AND2_3124(WX9062,WX9004,WX9021);
and AND2_3125(WX9064,WX9003,WX9021);
and AND2_3126(WX9066,WX9002,WX9021);
and AND2_3127(WX9068,WX9001,WX9021);
and AND2_3128(WX9070,WX9000,WX9021);
and AND2_3129(WX9072,WX8999,WX9021);
and AND2_3130(WX9074,WX8998,WX9021);
and AND2_3131(WX9076,WX8997,WX9021);
and AND2_3132(WX9078,WX8996,WX9021);
and AND2_3133(WX9080,WX8995,WX9021);
and AND2_3134(WX9082,WX8994,WX9021);
and AND2_3135(WX9084,WX8993,WX9021);
and AND2_3136(WX9086,WX9097,WX10054);
and AND2_3137(WX9087,WX9093,WX9088);
and AND2_3138(WX9090,CRC_OUT_2_31,WX10055);
and AND2_3139(WX9091,WX11356,WX9092);
and AND2_3140(WX9094,WX9536,WX10055);
and AND2_3141(WX9095,WX10063,WX9096);
and AND2_3142(WX9100,WX9111,WX10054);
and AND2_3143(WX9101,WX9107,WX9102);
and AND2_3144(WX9104,CRC_OUT_2_30,WX10055);
and AND2_3145(WX9105,WX11363,WX9106);
and AND2_3146(WX9108,WX9538,WX10055);
and AND2_3147(WX9109,WX10070,WX9110);
and AND2_3148(WX9114,WX9125,WX10054);
and AND2_3149(WX9115,WX9121,WX9116);
and AND2_3150(WX9118,CRC_OUT_2_29,WX10055);
and AND2_3151(WX9119,WX11370,WX9120);
and AND2_3152(WX9122,WX9540,WX10055);
and AND2_3153(WX9123,WX10077,WX9124);
and AND2_3154(WX9128,WX9139,WX10054);
and AND2_3155(WX9129,WX9135,WX9130);
and AND2_3156(WX9132,CRC_OUT_2_28,WX10055);
and AND2_3157(WX9133,WX11377,WX9134);
and AND2_3158(WX9136,WX9542,WX10055);
and AND2_3159(WX9137,WX10084,WX9138);
and AND2_3160(WX9142,WX9153,WX10054);
and AND2_3161(WX9143,WX9149,WX9144);
and AND2_3162(WX9146,CRC_OUT_2_27,WX10055);
and AND2_3163(WX9147,WX11384,WX9148);
and AND2_3164(WX9150,WX9544,WX10055);
and AND2_3165(WX9151,WX10091,WX9152);
and AND2_3166(WX9156,WX9167,WX10054);
and AND2_3167(WX9157,WX9163,WX9158);
and AND2_3168(WX9160,CRC_OUT_2_26,WX10055);
and AND2_3169(WX9161,WX11391,WX9162);
and AND2_3170(WX9164,WX9546,WX10055);
and AND2_3171(WX9165,WX10098,WX9166);
and AND2_3172(WX9170,WX9181,WX10054);
and AND2_3173(WX9171,WX9177,WX9172);
and AND2_3174(WX9174,CRC_OUT_2_25,WX10055);
and AND2_3175(WX9175,WX11398,WX9176);
and AND2_3176(WX9178,WX9548,WX10055);
and AND2_3177(WX9179,WX10105,WX9180);
and AND2_3178(WX9184,WX9195,WX10054);
and AND2_3179(WX9185,WX9191,WX9186);
and AND2_3180(WX9188,CRC_OUT_2_24,WX10055);
and AND2_3181(WX9189,WX11405,WX9190);
and AND2_3182(WX9192,WX9550,WX10055);
and AND2_3183(WX9193,WX10112,WX9194);
and AND2_3184(WX9198,WX9209,WX10054);
and AND2_3185(WX9199,WX9205,WX9200);
and AND2_3186(WX9202,CRC_OUT_2_23,WX10055);
and AND2_3187(WX9203,WX11412,WX9204);
and AND2_3188(WX9206,WX9552,WX10055);
and AND2_3189(WX9207,WX10119,WX9208);
and AND2_3190(WX9212,WX9223,WX10054);
and AND2_3191(WX9213,WX9219,WX9214);
and AND2_3192(WX9216,CRC_OUT_2_22,WX10055);
and AND2_3193(WX9217,WX11419,WX9218);
and AND2_3194(WX9220,WX9554,WX10055);
and AND2_3195(WX9221,WX10126,WX9222);
and AND2_3196(WX9226,WX9237,WX10054);
and AND2_3197(WX9227,WX9233,WX9228);
and AND2_3198(WX9230,CRC_OUT_2_21,WX10055);
and AND2_3199(WX9231,WX11426,WX9232);
and AND2_3200(WX9234,WX9556,WX10055);
and AND2_3201(WX9235,WX10133,WX9236);
and AND2_3202(WX9240,WX9251,WX10054);
and AND2_3203(WX9241,WX9247,WX9242);
and AND2_3204(WX9244,CRC_OUT_2_20,WX10055);
and AND2_3205(WX9245,WX11433,WX9246);
and AND2_3206(WX9248,WX9558,WX10055);
and AND2_3207(WX9249,WX10140,WX9250);
and AND2_3208(WX9254,WX9265,WX10054);
and AND2_3209(WX9255,WX9261,WX9256);
and AND2_3210(WX9258,CRC_OUT_2_19,WX10055);
and AND2_3211(WX9259,WX11440,WX9260);
and AND2_3212(WX9262,WX9560,WX10055);
and AND2_3213(WX9263,WX10147,WX9264);
and AND2_3214(WX9268,WX9279,WX10054);
and AND2_3215(WX9269,WX9275,WX9270);
and AND2_3216(WX9272,CRC_OUT_2_18,WX10055);
and AND2_3217(WX9273,WX11447,WX9274);
and AND2_3218(WX9276,WX9562,WX10055);
and AND2_3219(WX9277,WX10154,WX9278);
and AND2_3220(WX9282,WX9293,WX10054);
and AND2_3221(WX9283,WX9289,WX9284);
and AND2_3222(WX9286,CRC_OUT_2_17,WX10055);
and AND2_3223(WX9287,WX11454,WX9288);
and AND2_3224(WX9290,WX9564,WX10055);
and AND2_3225(WX9291,WX10161,WX9292);
and AND2_3226(WX9296,WX9307,WX10054);
and AND2_3227(WX9297,WX9303,WX9298);
and AND2_3228(WX9300,CRC_OUT_2_16,WX10055);
and AND2_3229(WX9301,WX11461,WX9302);
and AND2_3230(WX9304,WX9566,WX10055);
and AND2_3231(WX9305,WX10168,WX9306);
and AND2_3232(WX9310,WX9321,WX10054);
and AND2_3233(WX9311,WX9317,WX9312);
and AND2_3234(WX9314,CRC_OUT_2_15,WX10055);
and AND2_3235(WX9315,WX11468,WX9316);
and AND2_3236(WX9318,WX9568,WX10055);
and AND2_3237(WX9319,WX10175,WX9320);
and AND2_3238(WX9324,WX9335,WX10054);
and AND2_3239(WX9325,WX9331,WX9326);
and AND2_3240(WX9328,CRC_OUT_2_14,WX10055);
and AND2_3241(WX9329,WX11475,WX9330);
and AND2_3242(WX9332,WX9570,WX10055);
and AND2_3243(WX9333,WX10182,WX9334);
and AND2_3244(WX9338,WX9349,WX10054);
and AND2_3245(WX9339,WX9345,WX9340);
and AND2_3246(WX9342,CRC_OUT_2_13,WX10055);
and AND2_3247(WX9343,WX11482,WX9344);
and AND2_3248(WX9346,WX9572,WX10055);
and AND2_3249(WX9347,WX10189,WX9348);
and AND2_3250(WX9352,WX9363,WX10054);
and AND2_3251(WX9353,WX9359,WX9354);
and AND2_3252(WX9356,CRC_OUT_2_12,WX10055);
and AND2_3253(WX9357,WX11489,WX9358);
and AND2_3254(WX9360,WX9574,WX10055);
and AND2_3255(WX9361,WX10196,WX9362);
and AND2_3256(WX9366,WX9377,WX10054);
and AND2_3257(WX9367,WX9373,WX9368);
and AND2_3258(WX9370,CRC_OUT_2_11,WX10055);
and AND2_3259(WX9371,WX11496,WX9372);
and AND2_3260(WX9374,WX9576,WX10055);
and AND2_3261(WX9375,WX10203,WX9376);
and AND2_3262(WX9380,WX9391,WX10054);
and AND2_3263(WX9381,WX9387,WX9382);
and AND2_3264(WX9384,CRC_OUT_2_10,WX10055);
and AND2_3265(WX9385,WX11503,WX9386);
and AND2_3266(WX9388,WX9578,WX10055);
and AND2_3267(WX9389,WX10210,WX9390);
and AND2_3268(WX9394,WX9405,WX10054);
and AND2_3269(WX9395,WX9401,WX9396);
and AND2_3270(WX9398,CRC_OUT_2_9,WX10055);
and AND2_3271(WX9399,WX11510,WX9400);
and AND2_3272(WX9402,WX9580,WX10055);
and AND2_3273(WX9403,WX10217,WX9404);
and AND2_3274(WX9408,WX9419,WX10054);
and AND2_3275(WX9409,WX9415,WX9410);
and AND2_3276(WX9412,CRC_OUT_2_8,WX10055);
and AND2_3277(WX9413,WX11517,WX9414);
and AND2_3278(WX9416,WX9582,WX10055);
and AND2_3279(WX9417,WX10224,WX9418);
and AND2_3280(WX9422,WX9433,WX10054);
and AND2_3281(WX9423,WX9429,WX9424);
and AND2_3282(WX9426,CRC_OUT_2_7,WX10055);
and AND2_3283(WX9427,WX11524,WX9428);
and AND2_3284(WX9430,WX9584,WX10055);
and AND2_3285(WX9431,WX10231,WX9432);
and AND2_3286(WX9436,WX9447,WX10054);
and AND2_3287(WX9437,WX9443,WX9438);
and AND2_3288(WX9440,CRC_OUT_2_6,WX10055);
and AND2_3289(WX9441,WX11531,WX9442);
and AND2_3290(WX9444,WX9586,WX10055);
and AND2_3291(WX9445,WX10238,WX9446);
and AND2_3292(WX9450,WX9461,WX10054);
and AND2_3293(WX9451,WX9457,WX9452);
and AND2_3294(WX9454,CRC_OUT_2_5,WX10055);
and AND2_3295(WX9455,WX11538,WX9456);
and AND2_3296(WX9458,WX9588,WX10055);
and AND2_3297(WX9459,WX10245,WX9460);
and AND2_3298(WX9464,WX9475,WX10054);
and AND2_3299(WX9465,WX9471,WX9466);
and AND2_3300(WX9468,CRC_OUT_2_4,WX10055);
and AND2_3301(WX9469,WX11545,WX9470);
and AND2_3302(WX9472,WX9590,WX10055);
and AND2_3303(WX9473,WX10252,WX9474);
and AND2_3304(WX9478,WX9489,WX10054);
and AND2_3305(WX9479,WX9485,WX9480);
and AND2_3306(WX9482,CRC_OUT_2_3,WX10055);
and AND2_3307(WX9483,WX11552,WX9484);
and AND2_3308(WX9486,WX9592,WX10055);
and AND2_3309(WX9487,WX10259,WX9488);
and AND2_3310(WX9492,WX9503,WX10054);
and AND2_3311(WX9493,WX9499,WX9494);
and AND2_3312(WX9496,CRC_OUT_2_2,WX10055);
and AND2_3313(WX9497,WX11559,WX9498);
and AND2_3314(WX9500,WX9594,WX10055);
and AND2_3315(WX9501,WX10266,WX9502);
and AND2_3316(WX9506,WX9517,WX10054);
and AND2_3317(WX9507,WX9513,WX9508);
and AND2_3318(WX9510,CRC_OUT_2_1,WX10055);
and AND2_3319(WX9511,WX11566,WX9512);
and AND2_3320(WX9514,WX9596,WX10055);
and AND2_3321(WX9515,WX10273,WX9516);
and AND2_3322(WX9520,WX9531,WX10054);
and AND2_3323(WX9521,WX9527,WX9522);
and AND2_3324(WX9524,CRC_OUT_2_0,WX10055);
and AND2_3325(WX9525,WX11573,WX9526);
and AND2_3326(WX9528,WX9598,WX10055);
and AND2_3327(WX9529,WX10280,WX9530);
and AND2_3328(WX9535,WX9538,RESET);
and AND2_3329(WX9537,WX9540,RESET);
and AND2_3330(WX9539,WX9542,RESET);
and AND2_3331(WX9541,WX9544,RESET);
and AND2_3332(WX9543,WX9546,RESET);
and AND2_3333(WX9545,WX9548,RESET);
and AND2_3334(WX9547,WX9550,RESET);
and AND2_3335(WX9549,WX9552,RESET);
and AND2_3336(WX9551,WX9554,RESET);
and AND2_3337(WX9553,WX9556,RESET);
and AND2_3338(WX9555,WX9558,RESET);
and AND2_3339(WX9557,WX9560,RESET);
and AND2_3340(WX9559,WX9562,RESET);
and AND2_3341(WX9561,WX9564,RESET);
and AND2_3342(WX9563,WX9566,RESET);
and AND2_3343(WX9565,WX9568,RESET);
and AND2_3344(WX9567,WX9570,RESET);
and AND2_3345(WX9569,WX9572,RESET);
and AND2_3346(WX9571,WX9574,RESET);
and AND2_3347(WX9573,WX9576,RESET);
and AND2_3348(WX9575,WX9578,RESET);
and AND2_3349(WX9577,WX9580,RESET);
and AND2_3350(WX9579,WX9582,RESET);
and AND2_3351(WX9581,WX9584,RESET);
and AND2_3352(WX9583,WX9586,RESET);
and AND2_3353(WX9585,WX9588,RESET);
and AND2_3354(WX9587,WX9590,RESET);
and AND2_3355(WX9589,WX9592,RESET);
and AND2_3356(WX9591,WX9594,RESET);
and AND2_3357(WX9593,WX9596,RESET);
and AND2_3358(WX9595,WX9598,RESET);
and AND2_3359(WX9597,WX9534,RESET);
and AND2_3360(WX9695,WX9099,RESET);
and AND2_3361(WX9697,WX9113,RESET);
and AND2_3362(WX9699,WX9127,RESET);
and AND2_3363(WX9701,WX9141,RESET);
and AND2_3364(WX9703,WX9155,RESET);
and AND2_3365(WX9705,WX9169,RESET);
and AND2_3366(WX9707,WX9183,RESET);
and AND2_3367(WX9709,WX9197,RESET);
and AND2_3368(WX9711,WX9211,RESET);
and AND2_3369(WX9713,WX9225,RESET);
and AND2_3370(WX9715,WX9239,RESET);
and AND2_3371(WX9717,WX9253,RESET);
and AND2_3372(WX9719,WX9267,RESET);
and AND2_3373(WX9721,WX9281,RESET);
and AND2_3374(WX9723,WX9295,RESET);
and AND2_3375(WX9725,WX9309,RESET);
and AND2_3376(WX9727,WX9323,RESET);
and AND2_3377(WX9729,WX9337,RESET);
and AND2_3378(WX9731,WX9351,RESET);
and AND2_3379(WX9733,WX9365,RESET);
and AND2_3380(WX9735,WX9379,RESET);
and AND2_3381(WX9737,WX9393,RESET);
and AND2_3382(WX9739,WX9407,RESET);
and AND2_3383(WX9741,WX9421,RESET);
and AND2_3384(WX9743,WX9435,RESET);
and AND2_3385(WX9745,WX9449,RESET);
and AND2_3386(WX9747,WX9463,RESET);
and AND2_3387(WX9749,WX9477,RESET);
and AND2_3388(WX9751,WX9491,RESET);
and AND2_3389(WX9753,WX9505,RESET);
and AND2_3390(WX9755,WX9519,RESET);
and AND2_3391(WX9757,WX9533,RESET);
and AND2_3392(WX9759,WX9696,RESET);
and AND2_3393(WX9761,WX9698,RESET);
and AND2_3394(WX9763,WX9700,RESET);
and AND2_3395(WX9765,WX9702,RESET);
and AND2_3396(WX9767,WX9704,RESET);
and AND2_3397(WX9769,WX9706,RESET);
and AND2_3398(WX9771,WX9708,RESET);
and AND2_3399(WX9773,WX9710,RESET);
and AND2_3400(WX9775,WX9712,RESET);
and AND2_3401(WX9777,WX9714,RESET);
and AND2_3402(WX9779,WX9716,RESET);
and AND2_3403(WX9781,WX9718,RESET);
and AND2_3404(WX9783,WX9720,RESET);
and AND2_3405(WX9785,WX9722,RESET);
and AND2_3406(WX9787,WX9724,RESET);
and AND2_3407(WX9789,WX9726,RESET);
and AND2_3408(WX9791,WX9728,RESET);
and AND2_3409(WX9793,WX9730,RESET);
and AND2_3410(WX9795,WX9732,RESET);
and AND2_3411(WX9797,WX9734,RESET);
and AND2_3412(WX9799,WX9736,RESET);
and AND2_3413(WX9801,WX9738,RESET);
and AND2_3414(WX9803,WX9740,RESET);
and AND2_3415(WX9805,WX9742,RESET);
and AND2_3416(WX9807,WX9744,RESET);
and AND2_3417(WX9809,WX9746,RESET);
and AND2_3418(WX9811,WX9748,RESET);
and AND2_3419(WX9813,WX9750,RESET);
and AND2_3420(WX9815,WX9752,RESET);
and AND2_3421(WX9817,WX9754,RESET);
and AND2_3422(WX9819,WX9756,RESET);
and AND2_3423(WX9821,WX9758,RESET);
and AND2_3424(WX9823,WX9760,RESET);
and AND2_3425(WX9825,WX9762,RESET);
and AND2_3426(WX9827,WX9764,RESET);
and AND2_3427(WX9829,WX9766,RESET);
and AND2_3428(WX9831,WX9768,RESET);
and AND2_3429(WX9833,WX9770,RESET);
and AND2_3430(WX9835,WX9772,RESET);
and AND2_3431(WX9837,WX9774,RESET);
and AND2_3432(WX9839,WX9776,RESET);
and AND2_3433(WX9841,WX9778,RESET);
and AND2_3434(WX9843,WX9780,RESET);
and AND2_3435(WX9845,WX9782,RESET);
and AND2_3436(WX9847,WX9784,RESET);
and AND2_3437(WX9849,WX9786,RESET);
and AND2_3438(WX9851,WX9788,RESET);
and AND2_3439(WX9853,WX9790,RESET);
and AND2_3440(WX9855,WX9792,RESET);
and AND2_3441(WX9857,WX9794,RESET);
and AND2_3442(WX9859,WX9796,RESET);
and AND2_3443(WX9861,WX9798,RESET);
and AND2_3444(WX9863,WX9800,RESET);
and AND2_3445(WX9865,WX9802,RESET);
and AND2_3446(WX9867,WX9804,RESET);
and AND2_3447(WX9869,WX9806,RESET);
and AND2_3448(WX9871,WX9808,RESET);
and AND2_3449(WX9873,WX9810,RESET);
and AND2_3450(WX9875,WX9812,RESET);
and AND2_3451(WX9877,WX9814,RESET);
and AND2_3452(WX9879,WX9816,RESET);
and AND2_3453(WX9881,WX9818,RESET);
and AND2_3454(WX9883,WX9820,RESET);
and AND2_3455(WX9885,WX9822,RESET);
and AND2_3456(WX9887,WX9824,RESET);
and AND2_3457(WX9889,WX9826,RESET);
and AND2_3458(WX9891,WX9828,RESET);
and AND2_3459(WX9893,WX9830,RESET);
and AND2_3460(WX9895,WX9832,RESET);
and AND2_3461(WX9897,WX9834,RESET);
and AND2_3462(WX9899,WX9836,RESET);
and AND2_3463(WX9901,WX9838,RESET);
and AND2_3464(WX9903,WX9840,RESET);
and AND2_3465(WX9905,WX9842,RESET);
and AND2_3466(WX9907,WX9844,RESET);
and AND2_3467(WX9909,WX9846,RESET);
and AND2_3468(WX9911,WX9848,RESET);
and AND2_3469(WX9913,WX9850,RESET);
and AND2_3470(WX9915,WX9852,RESET);
and AND2_3471(WX9917,WX9854,RESET);
and AND2_3472(WX9919,WX9856,RESET);
and AND2_3473(WX9921,WX9858,RESET);
and AND2_3474(WX9923,WX9860,RESET);
and AND2_3475(WX9925,WX9862,RESET);
and AND2_3476(WX9927,WX9864,RESET);
and AND2_3477(WX9929,WX9866,RESET);
and AND2_3478(WX9931,WX9868,RESET);
and AND2_3479(WX9933,WX9870,RESET);
and AND2_3480(WX9935,WX9872,RESET);
and AND2_3481(WX9937,WX9874,RESET);
and AND2_3482(WX9939,WX9876,RESET);
and AND2_3483(WX9941,WX9878,RESET);
and AND2_3484(WX9943,WX9880,RESET);
and AND2_3485(WX9945,WX9882,RESET);
and AND2_3486(WX9947,WX9884,RESET);
and AND2_3487(WX9949,WX9886,RESET);
and AND2_3488(WX10058,WX10057,WX10056);
and AND2_3489(WX10059,WX9631,WX10060);
and AND2_3490(WX10065,WX10064,WX10056);
and AND2_3491(WX10066,WX9632,WX10067);
and AND2_3492(WX10072,WX10071,WX10056);
and AND2_3493(WX10073,WX9633,WX10074);
and AND2_3494(WX10079,WX10078,WX10056);
and AND2_3495(WX10080,WX9634,WX10081);
and AND2_3496(WX10086,WX10085,WX10056);
and AND2_3497(WX10087,WX9635,WX10088);
and AND2_3498(WX10093,WX10092,WX10056);
and AND2_3499(WX10094,WX9636,WX10095);
and AND2_3500(WX10100,WX10099,WX10056);
and AND2_3501(WX10101,WX9637,WX10102);
and AND2_3502(WX10107,WX10106,WX10056);
and AND2_3503(WX10108,WX9638,WX10109);
and AND2_3504(WX10114,WX10113,WX10056);
and AND2_3505(WX10115,WX9639,WX10116);
and AND2_3506(WX10121,WX10120,WX10056);
and AND2_3507(WX10122,WX9640,WX10123);
and AND2_3508(WX10128,WX10127,WX10056);
and AND2_3509(WX10129,WX9641,WX10130);
and AND2_3510(WX10135,WX10134,WX10056);
and AND2_3511(WX10136,WX9642,WX10137);
and AND2_3512(WX10142,WX10141,WX10056);
and AND2_3513(WX10143,WX9643,WX10144);
and AND2_3514(WX10149,WX10148,WX10056);
and AND2_3515(WX10150,WX9644,WX10151);
and AND2_3516(WX10156,WX10155,WX10056);
and AND2_3517(WX10157,WX9645,WX10158);
and AND2_3518(WX10163,WX10162,WX10056);
and AND2_3519(WX10164,WX9646,WX10165);
and AND2_3520(WX10170,WX10169,WX10056);
and AND2_3521(WX10171,WX9647,WX10172);
and AND2_3522(WX10177,WX10176,WX10056);
and AND2_3523(WX10178,WX9648,WX10179);
and AND2_3524(WX10184,WX10183,WX10056);
and AND2_3525(WX10185,WX9649,WX10186);
and AND2_3526(WX10191,WX10190,WX10056);
and AND2_3527(WX10192,WX9650,WX10193);
and AND2_3528(WX10198,WX10197,WX10056);
and AND2_3529(WX10199,WX9651,WX10200);
and AND2_3530(WX10205,WX10204,WX10056);
and AND2_3531(WX10206,WX9652,WX10207);
and AND2_3532(WX10212,WX10211,WX10056);
and AND2_3533(WX10213,WX9653,WX10214);
and AND2_3534(WX10219,WX10218,WX10056);
and AND2_3535(WX10220,WX9654,WX10221);
and AND2_3536(WX10226,WX10225,WX10056);
and AND2_3537(WX10227,WX9655,WX10228);
and AND2_3538(WX10233,WX10232,WX10056);
and AND2_3539(WX10234,WX9656,WX10235);
and AND2_3540(WX10240,WX10239,WX10056);
and AND2_3541(WX10241,WX9657,WX10242);
and AND2_3542(WX10247,WX10246,WX10056);
and AND2_3543(WX10248,WX9658,WX10249);
and AND2_3544(WX10254,WX10253,WX10056);
and AND2_3545(WX10255,WX9659,WX10256);
and AND2_3546(WX10261,WX10260,WX10056);
and AND2_3547(WX10262,WX9660,WX10263);
and AND2_3548(WX10268,WX10267,WX10056);
and AND2_3549(WX10269,WX9661,WX10270);
and AND2_3550(WX10275,WX10274,WX10056);
and AND2_3551(WX10276,WX9662,WX10277);
and AND2_3552(WX10315,WX10285,WX10314);
and AND2_3553(WX10317,WX10313,WX10314);
and AND2_3554(WX10319,WX10312,WX10314);
and AND2_3555(WX10321,WX10311,WX10314);
and AND2_3556(WX10323,WX10284,WX10314);
and AND2_3557(WX10325,WX10310,WX10314);
and AND2_3558(WX10327,WX10309,WX10314);
and AND2_3559(WX10329,WX10308,WX10314);
and AND2_3560(WX10331,WX10307,WX10314);
and AND2_3561(WX10333,WX10306,WX10314);
and AND2_3562(WX10335,WX10305,WX10314);
and AND2_3563(WX10337,WX10283,WX10314);
and AND2_3564(WX10339,WX10304,WX10314);
and AND2_3565(WX10341,WX10303,WX10314);
and AND2_3566(WX10343,WX10302,WX10314);
and AND2_3567(WX10345,WX10301,WX10314);
and AND2_3568(WX10347,WX10282,WX10314);
and AND2_3569(WX10349,WX10300,WX10314);
and AND2_3570(WX10351,WX10299,WX10314);
and AND2_3571(WX10353,WX10298,WX10314);
and AND2_3572(WX10355,WX10297,WX10314);
and AND2_3573(WX10357,WX10296,WX10314);
and AND2_3574(WX10359,WX10295,WX10314);
and AND2_3575(WX10361,WX10294,WX10314);
and AND2_3576(WX10363,WX10293,WX10314);
and AND2_3577(WX10365,WX10292,WX10314);
and AND2_3578(WX10367,WX10291,WX10314);
and AND2_3579(WX10369,WX10290,WX10314);
and AND2_3580(WX10371,WX10289,WX10314);
and AND2_3581(WX10373,WX10288,WX10314);
and AND2_3582(WX10375,WX10287,WX10314);
and AND2_3583(WX10377,WX10286,WX10314);
and AND2_3584(WX10379,WX10390,WX11347);
and AND2_3585(WX10380,WX10386,WX10381);
and AND2_3586(WX10383,CRC_OUT_1_31,WX11348);
and AND2_3587(WX10384,DATA_0_31,WX10385);
and AND2_3588(WX10387,WX10829,WX11348);
and AND2_3589(WX10388,WX11356,WX10389);
and AND2_3590(WX10393,WX10404,WX11347);
and AND2_3591(WX10394,WX10400,WX10395);
and AND2_3592(WX10397,CRC_OUT_1_30,WX11348);
and AND2_3593(WX10398,DATA_0_30,WX10399);
and AND2_3594(WX10401,WX10831,WX11348);
and AND2_3595(WX10402,WX11363,WX10403);
and AND2_3596(WX10407,WX10418,WX11347);
and AND2_3597(WX10408,WX10414,WX10409);
and AND2_3598(WX10411,CRC_OUT_1_29,WX11348);
and AND2_3599(WX10412,DATA_0_29,WX10413);
and AND2_3600(WX10415,WX10833,WX11348);
and AND2_3601(WX10416,WX11370,WX10417);
and AND2_3602(WX10421,WX10432,WX11347);
and AND2_3603(WX10422,WX10428,WX10423);
and AND2_3604(WX10425,CRC_OUT_1_28,WX11348);
and AND2_3605(WX10426,DATA_0_28,WX10427);
and AND2_3606(WX10429,WX10835,WX11348);
and AND2_3607(WX10430,WX11377,WX10431);
and AND2_3608(WX10435,WX10446,WX11347);
and AND2_3609(WX10436,WX10442,WX10437);
and AND2_3610(WX10439,CRC_OUT_1_27,WX11348);
and AND2_3611(WX10440,DATA_0_27,WX10441);
and AND2_3612(WX10443,WX10837,WX11348);
and AND2_3613(WX10444,WX11384,WX10445);
and AND2_3614(WX10449,WX10460,WX11347);
and AND2_3615(WX10450,WX10456,WX10451);
and AND2_3616(WX10453,CRC_OUT_1_26,WX11348);
and AND2_3617(WX10454,DATA_0_26,WX10455);
and AND2_3618(WX10457,WX10839,WX11348);
and AND2_3619(WX10458,WX11391,WX10459);
and AND2_3620(WX10463,WX10474,WX11347);
and AND2_3621(WX10464,WX10470,WX10465);
and AND2_3622(WX10467,CRC_OUT_1_25,WX11348);
and AND2_3623(WX10468,DATA_0_25,WX10469);
and AND2_3624(WX10471,WX10841,WX11348);
and AND2_3625(WX10472,WX11398,WX10473);
and AND2_3626(WX10477,WX10488,WX11347);
and AND2_3627(WX10478,WX10484,WX10479);
and AND2_3628(WX10481,CRC_OUT_1_24,WX11348);
and AND2_3629(WX10482,DATA_0_24,WX10483);
and AND2_3630(WX10485,WX10843,WX11348);
and AND2_3631(WX10486,WX11405,WX10487);
and AND2_3632(WX10491,WX10502,WX11347);
and AND2_3633(WX10492,WX10498,WX10493);
and AND2_3634(WX10495,CRC_OUT_1_23,WX11348);
and AND2_3635(WX10496,DATA_0_23,WX10497);
and AND2_3636(WX10499,WX10845,WX11348);
and AND2_3637(WX10500,WX11412,WX10501);
and AND2_3638(WX10505,WX10516,WX11347);
and AND2_3639(WX10506,WX10512,WX10507);
and AND2_3640(WX10509,CRC_OUT_1_22,WX11348);
and AND2_3641(WX10510,DATA_0_22,WX10511);
and AND2_3642(WX10513,WX10847,WX11348);
and AND2_3643(WX10514,WX11419,WX10515);
and AND2_3644(WX10519,WX10530,WX11347);
and AND2_3645(WX10520,WX10526,WX10521);
and AND2_3646(WX10523,CRC_OUT_1_21,WX11348);
and AND2_3647(WX10524,DATA_0_21,WX10525);
and AND2_3648(WX10527,WX10849,WX11348);
and AND2_3649(WX10528,WX11426,WX10529);
and AND2_3650(WX10533,WX10544,WX11347);
and AND2_3651(WX10534,WX10540,WX10535);
and AND2_3652(WX10537,CRC_OUT_1_20,WX11348);
and AND2_3653(WX10538,DATA_0_20,WX10539);
and AND2_3654(WX10541,WX10851,WX11348);
and AND2_3655(WX10542,WX11433,WX10543);
and AND2_3656(WX10547,WX10558,WX11347);
and AND2_3657(WX10548,WX10554,WX10549);
and AND2_3658(WX10551,CRC_OUT_1_19,WX11348);
and AND2_3659(WX10552,DATA_0_19,WX10553);
and AND2_3660(WX10555,WX10853,WX11348);
and AND2_3661(WX10556,WX11440,WX10557);
and AND2_3662(WX10561,WX10572,WX11347);
and AND2_3663(WX10562,WX10568,WX10563);
and AND2_3664(WX10565,CRC_OUT_1_18,WX11348);
and AND2_3665(WX10566,DATA_0_18,WX10567);
and AND2_3666(WX10569,WX10855,WX11348);
and AND2_3667(WX10570,WX11447,WX10571);
and AND2_3668(WX10575,WX10586,WX11347);
and AND2_3669(WX10576,WX10582,WX10577);
and AND2_3670(WX10579,CRC_OUT_1_17,WX11348);
and AND2_3671(WX10580,DATA_0_17,WX10581);
and AND2_3672(WX10583,WX10857,WX11348);
and AND2_3673(WX10584,WX11454,WX10585);
and AND2_3674(WX10589,WX10600,WX11347);
and AND2_3675(WX10590,WX10596,WX10591);
and AND2_3676(WX10593,CRC_OUT_1_16,WX11348);
and AND2_3677(WX10594,DATA_0_16,WX10595);
and AND2_3678(WX10597,WX10859,WX11348);
and AND2_3679(WX10598,WX11461,WX10599);
and AND2_3680(WX10603,WX10614,WX11347);
and AND2_3681(WX10604,WX10610,WX10605);
and AND2_3682(WX10607,CRC_OUT_1_15,WX11348);
and AND2_3683(WX10608,DATA_0_15,WX10609);
and AND2_3684(WX10611,WX10861,WX11348);
and AND2_3685(WX10612,WX11468,WX10613);
and AND2_3686(WX10617,WX10628,WX11347);
and AND2_3687(WX10618,WX10624,WX10619);
and AND2_3688(WX10621,CRC_OUT_1_14,WX11348);
and AND2_3689(WX10622,DATA_0_14,WX10623);
and AND2_3690(WX10625,WX10863,WX11348);
and AND2_3691(WX10626,WX11475,WX10627);
and AND2_3692(WX10631,WX10642,WX11347);
and AND2_3693(WX10632,WX10638,WX10633);
and AND2_3694(WX10635,CRC_OUT_1_13,WX11348);
and AND2_3695(WX10636,DATA_0_13,WX10637);
and AND2_3696(WX10639,WX10865,WX11348);
and AND2_3697(WX10640,WX11482,WX10641);
and AND2_3698(WX10645,WX10656,WX11347);
and AND2_3699(WX10646,WX10652,WX10647);
and AND2_3700(WX10649,CRC_OUT_1_12,WX11348);
and AND2_3701(WX10650,DATA_0_12,WX10651);
and AND2_3702(WX10653,WX10867,WX11348);
and AND2_3703(WX10654,WX11489,WX10655);
and AND2_3704(WX10659,WX10670,WX11347);
and AND2_3705(WX10660,WX10666,WX10661);
and AND2_3706(WX10663,CRC_OUT_1_11,WX11348);
and AND2_3707(WX10664,DATA_0_11,WX10665);
and AND2_3708(WX10667,WX10869,WX11348);
and AND2_3709(WX10668,WX11496,WX10669);
and AND2_3710(WX10673,WX10684,WX11347);
and AND2_3711(WX10674,WX10680,WX10675);
and AND2_3712(WX10677,CRC_OUT_1_10,WX11348);
and AND2_3713(WX10678,DATA_0_10,WX10679);
and AND2_3714(WX10681,WX10871,WX11348);
and AND2_3715(WX10682,WX11503,WX10683);
and AND2_3716(WX10687,WX10698,WX11347);
and AND2_3717(WX10688,WX10694,WX10689);
and AND2_3718(WX10691,CRC_OUT_1_9,WX11348);
and AND2_3719(WX10692,DATA_0_9,WX10693);
and AND2_3720(WX10695,WX10873,WX11348);
and AND2_3721(WX10696,WX11510,WX10697);
and AND2_3722(WX10701,WX10712,WX11347);
and AND2_3723(WX10702,WX10708,WX10703);
and AND2_3724(WX10705,CRC_OUT_1_8,WX11348);
and AND2_3725(WX10706,DATA_0_8,WX10707);
and AND2_3726(WX10709,WX10875,WX11348);
and AND2_3727(WX10710,WX11517,WX10711);
and AND2_3728(WX10715,WX10726,WX11347);
and AND2_3729(WX10716,WX10722,WX10717);
and AND2_3730(WX10719,CRC_OUT_1_7,WX11348);
and AND2_3731(WX10720,DATA_0_7,WX10721);
and AND2_3732(WX10723,WX10877,WX11348);
and AND2_3733(WX10724,WX11524,WX10725);
and AND2_3734(WX10729,WX10740,WX11347);
and AND2_3735(WX10730,WX10736,WX10731);
and AND2_3736(WX10733,CRC_OUT_1_6,WX11348);
and AND2_3737(WX10734,DATA_0_6,WX10735);
and AND2_3738(WX10737,WX10879,WX11348);
and AND2_3739(WX10738,WX11531,WX10739);
and AND2_3740(WX10743,WX10754,WX11347);
and AND2_3741(WX10744,WX10750,WX10745);
and AND2_3742(WX10747,CRC_OUT_1_5,WX11348);
and AND2_3743(WX10748,DATA_0_5,WX10749);
and AND2_3744(WX10751,WX10881,WX11348);
and AND2_3745(WX10752,WX11538,WX10753);
and AND2_3746(WX10757,WX10768,WX11347);
and AND2_3747(WX10758,WX10764,WX10759);
and AND2_3748(WX10761,CRC_OUT_1_4,WX11348);
and AND2_3749(WX10762,DATA_0_4,WX10763);
and AND2_3750(WX10765,WX10883,WX11348);
and AND2_3751(WX10766,WX11545,WX10767);
and AND2_3752(WX10771,WX10782,WX11347);
and AND2_3753(WX10772,WX10778,WX10773);
and AND2_3754(WX10775,CRC_OUT_1_3,WX11348);
and AND2_3755(WX10776,DATA_0_3,WX10777);
and AND2_3756(WX10779,WX10885,WX11348);
and AND2_3757(WX10780,WX11552,WX10781);
and AND2_3758(WX10785,WX10796,WX11347);
and AND2_3759(WX10786,WX10792,WX10787);
and AND2_3760(WX10789,CRC_OUT_1_2,WX11348);
and AND2_3761(WX10790,DATA_0_2,WX10791);
and AND2_3762(WX10793,WX10887,WX11348);
and AND2_3763(WX10794,WX11559,WX10795);
and AND2_3764(WX10799,WX10810,WX11347);
and AND2_3765(WX10800,WX10806,WX10801);
and AND2_3766(WX10803,CRC_OUT_1_1,WX11348);
and AND2_3767(WX10804,DATA_0_1,WX10805);
and AND2_3768(WX10807,WX10889,WX11348);
and AND2_3769(WX10808,WX11566,WX10809);
and AND2_3770(WX10813,WX10824,WX11347);
and AND2_3771(WX10814,WX10820,WX10815);
and AND2_3772(WX10817,CRC_OUT_1_0,WX11348);
and AND2_3773(WX10818,DATA_0_0,WX10819);
and AND2_3774(WX10821,WX10891,WX11348);
and AND2_3775(WX10822,WX11573,WX10823);
and AND2_3776(WX10828,WX10831,RESET);
and AND2_3777(WX10830,WX10833,RESET);
and AND2_3778(WX10832,WX10835,RESET);
and AND2_3779(WX10834,WX10837,RESET);
and AND2_3780(WX10836,WX10839,RESET);
and AND2_3781(WX10838,WX10841,RESET);
and AND2_3782(WX10840,WX10843,RESET);
and AND2_3783(WX10842,WX10845,RESET);
and AND2_3784(WX10844,WX10847,RESET);
and AND2_3785(WX10846,WX10849,RESET);
and AND2_3786(WX10848,WX10851,RESET);
and AND2_3787(WX10850,WX10853,RESET);
and AND2_3788(WX10852,WX10855,RESET);
and AND2_3789(WX10854,WX10857,RESET);
and AND2_3790(WX10856,WX10859,RESET);
and AND2_3791(WX10858,WX10861,RESET);
and AND2_3792(WX10860,WX10863,RESET);
and AND2_3793(WX10862,WX10865,RESET);
and AND2_3794(WX10864,WX10867,RESET);
and AND2_3795(WX10866,WX10869,RESET);
and AND2_3796(WX10868,WX10871,RESET);
and AND2_3797(WX10870,WX10873,RESET);
and AND2_3798(WX10872,WX10875,RESET);
and AND2_3799(WX10874,WX10877,RESET);
and AND2_3800(WX10876,WX10879,RESET);
and AND2_3801(WX10878,WX10881,RESET);
and AND2_3802(WX10880,WX10883,RESET);
and AND2_3803(WX10882,WX10885,RESET);
and AND2_3804(WX10884,WX10887,RESET);
and AND2_3805(WX10886,WX10889,RESET);
and AND2_3806(WX10888,WX10891,RESET);
and AND2_3807(WX10890,WX10827,RESET);
and AND2_3808(WX10988,WX10392,RESET);
and AND2_3809(WX10990,WX10406,RESET);
and AND2_3810(WX10992,WX10420,RESET);
and AND2_3811(WX10994,WX10434,RESET);
and AND2_3812(WX10996,WX10448,RESET);
and AND2_3813(WX10998,WX10462,RESET);
and AND2_3814(WX11000,WX10476,RESET);
and AND2_3815(WX11002,WX10490,RESET);
and AND2_3816(WX11004,WX10504,RESET);
and AND2_3817(WX11006,WX10518,RESET);
and AND2_3818(WX11008,WX10532,RESET);
and AND2_3819(WX11010,WX10546,RESET);
and AND2_3820(WX11012,WX10560,RESET);
and AND2_3821(WX11014,WX10574,RESET);
and AND2_3822(WX11016,WX10588,RESET);
and AND2_3823(WX11018,WX10602,RESET);
and AND2_3824(WX11020,WX10616,RESET);
and AND2_3825(WX11022,WX10630,RESET);
and AND2_3826(WX11024,WX10644,RESET);
and AND2_3827(WX11026,WX10658,RESET);
and AND2_3828(WX11028,WX10672,RESET);
and AND2_3829(WX11030,WX10686,RESET);
and AND2_3830(WX11032,WX10700,RESET);
and AND2_3831(WX11034,WX10714,RESET);
and AND2_3832(WX11036,WX10728,RESET);
and AND2_3833(WX11038,WX10742,RESET);
and AND2_3834(WX11040,WX10756,RESET);
and AND2_3835(WX11042,WX10770,RESET);
and AND2_3836(WX11044,WX10784,RESET);
and AND2_3837(WX11046,WX10798,RESET);
and AND2_3838(WX11048,WX10812,RESET);
and AND2_3839(WX11050,WX10826,RESET);
and AND2_3840(WX11052,WX10989,RESET);
and AND2_3841(WX11054,WX10991,RESET);
and AND2_3842(WX11056,WX10993,RESET);
and AND2_3843(WX11058,WX10995,RESET);
and AND2_3844(WX11060,WX10997,RESET);
and AND2_3845(WX11062,WX10999,RESET);
and AND2_3846(WX11064,WX11001,RESET);
and AND2_3847(WX11066,WX11003,RESET);
and AND2_3848(WX11068,WX11005,RESET);
and AND2_3849(WX11070,WX11007,RESET);
and AND2_3850(WX11072,WX11009,RESET);
and AND2_3851(WX11074,WX11011,RESET);
and AND2_3852(WX11076,WX11013,RESET);
and AND2_3853(WX11078,WX11015,RESET);
and AND2_3854(WX11080,WX11017,RESET);
and AND2_3855(WX11082,WX11019,RESET);
and AND2_3856(WX11084,WX11021,RESET);
and AND2_3857(WX11086,WX11023,RESET);
and AND2_3858(WX11088,WX11025,RESET);
and AND2_3859(WX11090,WX11027,RESET);
and AND2_3860(WX11092,WX11029,RESET);
and AND2_3861(WX11094,WX11031,RESET);
and AND2_3862(WX11096,WX11033,RESET);
and AND2_3863(WX11098,WX11035,RESET);
and AND2_3864(WX11100,WX11037,RESET);
and AND2_3865(WX11102,WX11039,RESET);
and AND2_3866(WX11104,WX11041,RESET);
and AND2_3867(WX11106,WX11043,RESET);
and AND2_3868(WX11108,WX11045,RESET);
and AND2_3869(WX11110,WX11047,RESET);
and AND2_3870(WX11112,WX11049,RESET);
and AND2_3871(WX11114,WX11051,RESET);
and AND2_3872(WX11116,WX11053,RESET);
and AND2_3873(WX11118,WX11055,RESET);
and AND2_3874(WX11120,WX11057,RESET);
and AND2_3875(WX11122,WX11059,RESET);
and AND2_3876(WX11124,WX11061,RESET);
and AND2_3877(WX11126,WX11063,RESET);
and AND2_3878(WX11128,WX11065,RESET);
and AND2_3879(WX11130,WX11067,RESET);
and AND2_3880(WX11132,WX11069,RESET);
and AND2_3881(WX11134,WX11071,RESET);
and AND2_3882(WX11136,WX11073,RESET);
and AND2_3883(WX11138,WX11075,RESET);
and AND2_3884(WX11140,WX11077,RESET);
and AND2_3885(WX11142,WX11079,RESET);
and AND2_3886(WX11144,WX11081,RESET);
and AND2_3887(WX11146,WX11083,RESET);
and AND2_3888(WX11148,WX11085,RESET);
and AND2_3889(WX11150,WX11087,RESET);
and AND2_3890(WX11152,WX11089,RESET);
and AND2_3891(WX11154,WX11091,RESET);
and AND2_3892(WX11156,WX11093,RESET);
and AND2_3893(WX11158,WX11095,RESET);
and AND2_3894(WX11160,WX11097,RESET);
and AND2_3895(WX11162,WX11099,RESET);
and AND2_3896(WX11164,WX11101,RESET);
and AND2_3897(WX11166,WX11103,RESET);
and AND2_3898(WX11168,WX11105,RESET);
and AND2_3899(WX11170,WX11107,RESET);
and AND2_3900(WX11172,WX11109,RESET);
and AND2_3901(WX11174,WX11111,RESET);
and AND2_3902(WX11176,WX11113,RESET);
and AND2_3903(WX11178,WX11115,RESET);
and AND2_3904(WX11180,WX11117,RESET);
and AND2_3905(WX11182,WX11119,RESET);
and AND2_3906(WX11184,WX11121,RESET);
and AND2_3907(WX11186,WX11123,RESET);
and AND2_3908(WX11188,WX11125,RESET);
and AND2_3909(WX11190,WX11127,RESET);
and AND2_3910(WX11192,WX11129,RESET);
and AND2_3911(WX11194,WX11131,RESET);
and AND2_3912(WX11196,WX11133,RESET);
and AND2_3913(WX11198,WX11135,RESET);
and AND2_3914(WX11200,WX11137,RESET);
and AND2_3915(WX11202,WX11139,RESET);
and AND2_3916(WX11204,WX11141,RESET);
and AND2_3917(WX11206,WX11143,RESET);
and AND2_3918(WX11208,WX11145,RESET);
and AND2_3919(WX11210,WX11147,RESET);
and AND2_3920(WX11212,WX11149,RESET);
and AND2_3921(WX11214,WX11151,RESET);
and AND2_3922(WX11216,WX11153,RESET);
and AND2_3923(WX11218,WX11155,RESET);
and AND2_3924(WX11220,WX11157,RESET);
and AND2_3925(WX11222,WX11159,RESET);
and AND2_3926(WX11224,WX11161,RESET);
and AND2_3927(WX11226,WX11163,RESET);
and AND2_3928(WX11228,WX11165,RESET);
and AND2_3929(WX11230,WX11167,RESET);
and AND2_3930(WX11232,WX11169,RESET);
and AND2_3931(WX11234,WX11171,RESET);
and AND2_3932(WX11236,WX11173,RESET);
and AND2_3933(WX11238,WX11175,RESET);
and AND2_3934(WX11240,WX11177,RESET);
and AND2_3935(WX11242,WX11179,RESET);
and AND2_3936(WX11351,WX11350,WX11349);
and AND2_3937(WX11352,WX10924,WX11353);
and AND2_3938(WX11358,WX11357,WX11349);
and AND2_3939(WX11359,WX10925,WX11360);
and AND2_3940(WX11365,WX11364,WX11349);
and AND2_3941(WX11366,WX10926,WX11367);
and AND2_3942(WX11372,WX11371,WX11349);
and AND2_3943(WX11373,WX10927,WX11374);
and AND2_3944(WX11379,WX11378,WX11349);
and AND2_3945(WX11380,WX10928,WX11381);
and AND2_3946(WX11386,WX11385,WX11349);
and AND2_3947(WX11387,WX10929,WX11388);
and AND2_3948(WX11393,WX11392,WX11349);
and AND2_3949(WX11394,WX10930,WX11395);
and AND2_3950(WX11400,WX11399,WX11349);
and AND2_3951(WX11401,WX10931,WX11402);
and AND2_3952(WX11407,WX11406,WX11349);
and AND2_3953(WX11408,WX10932,WX11409);
and AND2_3954(WX11414,WX11413,WX11349);
and AND2_3955(WX11415,WX10933,WX11416);
and AND2_3956(WX11421,WX11420,WX11349);
and AND2_3957(WX11422,WX10934,WX11423);
and AND2_3958(WX11428,WX11427,WX11349);
and AND2_3959(WX11429,WX10935,WX11430);
and AND2_3960(WX11435,WX11434,WX11349);
and AND2_3961(WX11436,WX10936,WX11437);
and AND2_3962(WX11442,WX11441,WX11349);
and AND2_3963(WX11443,WX10937,WX11444);
and AND2_3964(WX11449,WX11448,WX11349);
and AND2_3965(WX11450,WX10938,WX11451);
and AND2_3966(WX11456,WX11455,WX11349);
and AND2_3967(WX11457,WX10939,WX11458);
and AND2_3968(WX11463,WX11462,WX11349);
and AND2_3969(WX11464,WX10940,WX11465);
and AND2_3970(WX11470,WX11469,WX11349);
and AND2_3971(WX11471,WX10941,WX11472);
and AND2_3972(WX11477,WX11476,WX11349);
and AND2_3973(WX11478,WX10942,WX11479);
and AND2_3974(WX11484,WX11483,WX11349);
and AND2_3975(WX11485,WX10943,WX11486);
and AND2_3976(WX11491,WX11490,WX11349);
and AND2_3977(WX11492,WX10944,WX11493);
and AND2_3978(WX11498,WX11497,WX11349);
and AND2_3979(WX11499,WX10945,WX11500);
and AND2_3980(WX11505,WX11504,WX11349);
and AND2_3981(WX11506,WX10946,WX11507);
and AND2_3982(WX11512,WX11511,WX11349);
and AND2_3983(WX11513,WX10947,WX11514);
and AND2_3984(WX11519,WX11518,WX11349);
and AND2_3985(WX11520,WX10948,WX11521);
and AND2_3986(WX11526,WX11525,WX11349);
and AND2_3987(WX11527,WX10949,WX11528);
and AND2_3988(WX11533,WX11532,WX11349);
and AND2_3989(WX11534,WX10950,WX11535);
and AND2_3990(WX11540,WX11539,WX11349);
and AND2_3991(WX11541,WX10951,WX11542);
and AND2_3992(WX11547,WX11546,WX11349);
and AND2_3993(WX11548,WX10952,WX11549);
and AND2_3994(WX11554,WX11553,WX11349);
and AND2_3995(WX11555,WX10953,WX11556);
and AND2_3996(WX11561,WX11560,WX11349);
and AND2_3997(WX11562,WX10954,WX11563);
and AND2_3998(WX11568,WX11567,WX11349);
and AND2_3999(WX11569,WX10955,WX11570);
and AND2_4000(WX11608,WX11578,WX11607);
and AND2_4001(WX11610,WX11606,WX11607);
and AND2_4002(WX11612,WX11605,WX11607);
and AND2_4003(WX11614,WX11604,WX11607);
and AND2_4004(WX11616,WX11577,WX11607);
and AND2_4005(WX11618,WX11603,WX11607);
and AND2_4006(WX11620,WX11602,WX11607);
and AND2_4007(WX11622,WX11601,WX11607);
and AND2_4008(WX11624,WX11600,WX11607);
and AND2_4009(WX11626,WX11599,WX11607);
and AND2_4010(WX11628,WX11598,WX11607);
and AND2_4011(WX11630,WX11576,WX11607);
and AND2_4012(WX11632,WX11597,WX11607);
and AND2_4013(WX11634,WX11596,WX11607);
and AND2_4014(WX11636,WX11595,WX11607);
and AND2_4015(WX11638,WX11594,WX11607);
and AND2_4016(WX11640,WX11575,WX11607);
and AND2_4017(WX11642,WX11593,WX11607);
and AND2_4018(WX11644,WX11592,WX11607);
and AND2_4019(WX11646,WX11591,WX11607);
and AND2_4020(WX11648,WX11590,WX11607);
and AND2_4021(WX11650,WX11589,WX11607);
and AND2_4022(WX11652,WX11588,WX11607);
and AND2_4023(WX11654,WX11587,WX11607);
and AND2_4024(WX11656,WX11586,WX11607);
and AND2_4025(WX11658,WX11585,WX11607);
and AND2_4026(WX11660,WX11584,WX11607);
and AND2_4027(WX11662,WX11583,WX11607);
and AND2_4028(WX11664,WX11582,WX11607);
and AND2_4029(WX11666,WX11581,WX11607);
and AND2_4030(WX11668,WX11580,WX11607);
and AND2_4031(WX11670,WX11579,WX11607);
or OR2_0(WX38,WX36,WX35);
or OR2_1(WX42,WX40,WX39);
or OR2_2(WX46,WX44,WX43);
or OR2_3(WX52,WX50,WX49);
or OR2_4(WX56,WX54,WX53);
or OR2_5(WX60,WX58,WX57);
or OR2_6(WX66,WX64,WX63);
or OR2_7(WX70,WX68,WX67);
or OR2_8(WX74,WX72,WX71);
or OR2_9(WX80,WX78,WX77);
or OR2_10(WX84,WX82,WX81);
or OR2_11(WX88,WX86,WX85);
or OR2_12(WX94,WX92,WX91);
or OR2_13(WX98,WX96,WX95);
or OR2_14(WX102,WX100,WX99);
or OR2_15(WX108,WX106,WX105);
or OR2_16(WX112,WX110,WX109);
or OR2_17(WX116,WX114,WX113);
or OR2_18(WX122,WX120,WX119);
or OR2_19(WX126,WX124,WX123);
or OR2_20(WX130,WX128,WX127);
or OR2_21(WX136,WX134,WX133);
or OR2_22(WX140,WX138,WX137);
or OR2_23(WX144,WX142,WX141);
or OR2_24(WX150,WX148,WX147);
or OR2_25(WX154,WX152,WX151);
or OR2_26(WX158,WX156,WX155);
or OR2_27(WX164,WX162,WX161);
or OR2_28(WX168,WX166,WX165);
or OR2_29(WX172,WX170,WX169);
or OR2_30(WX178,WX176,WX175);
or OR2_31(WX182,WX180,WX179);
or OR2_32(WX186,WX184,WX183);
or OR2_33(WX192,WX190,WX189);
or OR2_34(WX196,WX194,WX193);
or OR2_35(WX200,WX198,WX197);
or OR2_36(WX206,WX204,WX203);
or OR2_37(WX210,WX208,WX207);
or OR2_38(WX214,WX212,WX211);
or OR2_39(WX220,WX218,WX217);
or OR2_40(WX224,WX222,WX221);
or OR2_41(WX228,WX226,WX225);
or OR2_42(WX234,WX232,WX231);
or OR2_43(WX238,WX236,WX235);
or OR2_44(WX242,WX240,WX239);
or OR2_45(WX248,WX246,WX245);
or OR2_46(WX252,WX250,WX249);
or OR2_47(WX256,WX254,WX253);
or OR2_48(WX262,WX260,WX259);
or OR2_49(WX266,WX264,WX263);
or OR2_50(WX270,WX268,WX267);
or OR2_51(WX276,WX274,WX273);
or OR2_52(WX280,WX278,WX277);
or OR2_53(WX284,WX282,WX281);
or OR2_54(WX290,WX288,WX287);
or OR2_55(WX294,WX292,WX291);
or OR2_56(WX298,WX296,WX295);
or OR2_57(WX304,WX302,WX301);
or OR2_58(WX308,WX306,WX305);
or OR2_59(WX312,WX310,WX309);
or OR2_60(WX318,WX316,WX315);
or OR2_61(WX322,WX320,WX319);
or OR2_62(WX326,WX324,WX323);
or OR2_63(WX332,WX330,WX329);
or OR2_64(WX336,WX334,WX333);
or OR2_65(WX340,WX338,WX337);
or OR2_66(WX346,WX344,WX343);
or OR2_67(WX350,WX348,WX347);
or OR2_68(WX354,WX352,WX351);
or OR2_69(WX360,WX358,WX357);
or OR2_70(WX364,WX362,WX361);
or OR2_71(WX368,WX366,WX365);
or OR2_72(WX374,WX372,WX371);
or OR2_73(WX378,WX376,WX375);
or OR2_74(WX382,WX380,WX379);
or OR2_75(WX388,WX386,WX385);
or OR2_76(WX392,WX390,WX389);
or OR2_77(WX396,WX394,WX393);
or OR2_78(WX402,WX400,WX399);
or OR2_79(WX406,WX404,WX403);
or OR2_80(WX410,WX408,WX407);
or OR2_81(WX416,WX414,WX413);
or OR2_82(WX420,WX418,WX417);
or OR2_83(WX424,WX422,WX421);
or OR2_84(WX430,WX428,WX427);
or OR2_85(WX434,WX432,WX431);
or OR2_86(WX438,WX436,WX435);
or OR2_87(WX444,WX442,WX441);
or OR2_88(WX448,WX446,WX445);
or OR2_89(WX452,WX450,WX449);
or OR2_90(WX458,WX456,WX455);
or OR2_91(WX462,WX460,WX459);
or OR2_92(WX466,WX464,WX463);
or OR2_93(WX472,WX470,WX469);
or OR2_94(WX476,WX474,WX473);
or OR2_95(WX480,WX478,WX477);
or OR2_96(WX1010,WX1008,WX1007);
or OR2_97(WX1017,WX1015,WX1014);
or OR2_98(WX1024,WX1022,WX1021);
or OR2_99(WX1031,WX1029,WX1028);
or OR2_100(WX1038,WX1036,WX1035);
or OR2_101(WX1045,WX1043,WX1042);
or OR2_102(WX1052,WX1050,WX1049);
or OR2_103(WX1059,WX1057,WX1056);
or OR2_104(WX1066,WX1064,WX1063);
or OR2_105(WX1073,WX1071,WX1070);
or OR2_106(WX1080,WX1078,WX1077);
or OR2_107(WX1087,WX1085,WX1084);
or OR2_108(WX1094,WX1092,WX1091);
or OR2_109(WX1101,WX1099,WX1098);
or OR2_110(WX1108,WX1106,WX1105);
or OR2_111(WX1115,WX1113,WX1112);
or OR2_112(WX1122,WX1120,WX1119);
or OR2_113(WX1129,WX1127,WX1126);
or OR2_114(WX1136,WX1134,WX1133);
or OR2_115(WX1143,WX1141,WX1140);
or OR2_116(WX1150,WX1148,WX1147);
or OR2_117(WX1157,WX1155,WX1154);
or OR2_118(WX1164,WX1162,WX1161);
or OR2_119(WX1171,WX1169,WX1168);
or OR2_120(WX1178,WX1176,WX1175);
or OR2_121(WX1185,WX1183,WX1182);
or OR2_122(WX1192,WX1190,WX1189);
or OR2_123(WX1199,WX1197,WX1196);
or OR2_124(WX1206,WX1204,WX1203);
or OR2_125(WX1213,WX1211,WX1210);
or OR2_126(WX1220,WX1218,WX1217);
or OR2_127(WX1227,WX1225,WX1224);
or OR2_128(WX1331,WX1329,WX1328);
or OR2_129(WX1335,WX1333,WX1332);
or OR2_130(WX1339,WX1337,WX1336);
or OR2_131(WX1345,WX1343,WX1342);
or OR2_132(WX1349,WX1347,WX1346);
or OR2_133(WX1353,WX1351,WX1350);
or OR2_134(WX1359,WX1357,WX1356);
or OR2_135(WX1363,WX1361,WX1360);
or OR2_136(WX1367,WX1365,WX1364);
or OR2_137(WX1373,WX1371,WX1370);
or OR2_138(WX1377,WX1375,WX1374);
or OR2_139(WX1381,WX1379,WX1378);
or OR2_140(WX1387,WX1385,WX1384);
or OR2_141(WX1391,WX1389,WX1388);
or OR2_142(WX1395,WX1393,WX1392);
or OR2_143(WX1401,WX1399,WX1398);
or OR2_144(WX1405,WX1403,WX1402);
or OR2_145(WX1409,WX1407,WX1406);
or OR2_146(WX1415,WX1413,WX1412);
or OR2_147(WX1419,WX1417,WX1416);
or OR2_148(WX1423,WX1421,WX1420);
or OR2_149(WX1429,WX1427,WX1426);
or OR2_150(WX1433,WX1431,WX1430);
or OR2_151(WX1437,WX1435,WX1434);
or OR2_152(WX1443,WX1441,WX1440);
or OR2_153(WX1447,WX1445,WX1444);
or OR2_154(WX1451,WX1449,WX1448);
or OR2_155(WX1457,WX1455,WX1454);
or OR2_156(WX1461,WX1459,WX1458);
or OR2_157(WX1465,WX1463,WX1462);
or OR2_158(WX1471,WX1469,WX1468);
or OR2_159(WX1475,WX1473,WX1472);
or OR2_160(WX1479,WX1477,WX1476);
or OR2_161(WX1485,WX1483,WX1482);
or OR2_162(WX1489,WX1487,WX1486);
or OR2_163(WX1493,WX1491,WX1490);
or OR2_164(WX1499,WX1497,WX1496);
or OR2_165(WX1503,WX1501,WX1500);
or OR2_166(WX1507,WX1505,WX1504);
or OR2_167(WX1513,WX1511,WX1510);
or OR2_168(WX1517,WX1515,WX1514);
or OR2_169(WX1521,WX1519,WX1518);
or OR2_170(WX1527,WX1525,WX1524);
or OR2_171(WX1531,WX1529,WX1528);
or OR2_172(WX1535,WX1533,WX1532);
or OR2_173(WX1541,WX1539,WX1538);
or OR2_174(WX1545,WX1543,WX1542);
or OR2_175(WX1549,WX1547,WX1546);
or OR2_176(WX1555,WX1553,WX1552);
or OR2_177(WX1559,WX1557,WX1556);
or OR2_178(WX1563,WX1561,WX1560);
or OR2_179(WX1569,WX1567,WX1566);
or OR2_180(WX1573,WX1571,WX1570);
or OR2_181(WX1577,WX1575,WX1574);
or OR2_182(WX1583,WX1581,WX1580);
or OR2_183(WX1587,WX1585,WX1584);
or OR2_184(WX1591,WX1589,WX1588);
or OR2_185(WX1597,WX1595,WX1594);
or OR2_186(WX1601,WX1599,WX1598);
or OR2_187(WX1605,WX1603,WX1602);
or OR2_188(WX1611,WX1609,WX1608);
or OR2_189(WX1615,WX1613,WX1612);
or OR2_190(WX1619,WX1617,WX1616);
or OR2_191(WX1625,WX1623,WX1622);
or OR2_192(WX1629,WX1627,WX1626);
or OR2_193(WX1633,WX1631,WX1630);
or OR2_194(WX1639,WX1637,WX1636);
or OR2_195(WX1643,WX1641,WX1640);
or OR2_196(WX1647,WX1645,WX1644);
or OR2_197(WX1653,WX1651,WX1650);
or OR2_198(WX1657,WX1655,WX1654);
or OR2_199(WX1661,WX1659,WX1658);
or OR2_200(WX1667,WX1665,WX1664);
or OR2_201(WX1671,WX1669,WX1668);
or OR2_202(WX1675,WX1673,WX1672);
or OR2_203(WX1681,WX1679,WX1678);
or OR2_204(WX1685,WX1683,WX1682);
or OR2_205(WX1689,WX1687,WX1686);
or OR2_206(WX1695,WX1693,WX1692);
or OR2_207(WX1699,WX1697,WX1696);
or OR2_208(WX1703,WX1701,WX1700);
or OR2_209(WX1709,WX1707,WX1706);
or OR2_210(WX1713,WX1711,WX1710);
or OR2_211(WX1717,WX1715,WX1714);
or OR2_212(WX1723,WX1721,WX1720);
or OR2_213(WX1727,WX1725,WX1724);
or OR2_214(WX1731,WX1729,WX1728);
or OR2_215(WX1737,WX1735,WX1734);
or OR2_216(WX1741,WX1739,WX1738);
or OR2_217(WX1745,WX1743,WX1742);
or OR2_218(WX1751,WX1749,WX1748);
or OR2_219(WX1755,WX1753,WX1752);
or OR2_220(WX1759,WX1757,WX1756);
or OR2_221(WX1765,WX1763,WX1762);
or OR2_222(WX1769,WX1767,WX1766);
or OR2_223(WX1773,WX1771,WX1770);
or OR2_224(WX2303,WX2301,WX2300);
or OR2_225(WX2310,WX2308,WX2307);
or OR2_226(WX2317,WX2315,WX2314);
or OR2_227(WX2324,WX2322,WX2321);
or OR2_228(WX2331,WX2329,WX2328);
or OR2_229(WX2338,WX2336,WX2335);
or OR2_230(WX2345,WX2343,WX2342);
or OR2_231(WX2352,WX2350,WX2349);
or OR2_232(WX2359,WX2357,WX2356);
or OR2_233(WX2366,WX2364,WX2363);
or OR2_234(WX2373,WX2371,WX2370);
or OR2_235(WX2380,WX2378,WX2377);
or OR2_236(WX2387,WX2385,WX2384);
or OR2_237(WX2394,WX2392,WX2391);
or OR2_238(WX2401,WX2399,WX2398);
or OR2_239(WX2408,WX2406,WX2405);
or OR2_240(WX2415,WX2413,WX2412);
or OR2_241(WX2422,WX2420,WX2419);
or OR2_242(WX2429,WX2427,WX2426);
or OR2_243(WX2436,WX2434,WX2433);
or OR2_244(WX2443,WX2441,WX2440);
or OR2_245(WX2450,WX2448,WX2447);
or OR2_246(WX2457,WX2455,WX2454);
or OR2_247(WX2464,WX2462,WX2461);
or OR2_248(WX2471,WX2469,WX2468);
or OR2_249(WX2478,WX2476,WX2475);
or OR2_250(WX2485,WX2483,WX2482);
or OR2_251(WX2492,WX2490,WX2489);
or OR2_252(WX2499,WX2497,WX2496);
or OR2_253(WX2506,WX2504,WX2503);
or OR2_254(WX2513,WX2511,WX2510);
or OR2_255(WX2520,WX2518,WX2517);
or OR2_256(WX2624,WX2622,WX2621);
or OR2_257(WX2628,WX2626,WX2625);
or OR2_258(WX2632,WX2630,WX2629);
or OR2_259(WX2638,WX2636,WX2635);
or OR2_260(WX2642,WX2640,WX2639);
or OR2_261(WX2646,WX2644,WX2643);
or OR2_262(WX2652,WX2650,WX2649);
or OR2_263(WX2656,WX2654,WX2653);
or OR2_264(WX2660,WX2658,WX2657);
or OR2_265(WX2666,WX2664,WX2663);
or OR2_266(WX2670,WX2668,WX2667);
or OR2_267(WX2674,WX2672,WX2671);
or OR2_268(WX2680,WX2678,WX2677);
or OR2_269(WX2684,WX2682,WX2681);
or OR2_270(WX2688,WX2686,WX2685);
or OR2_271(WX2694,WX2692,WX2691);
or OR2_272(WX2698,WX2696,WX2695);
or OR2_273(WX2702,WX2700,WX2699);
or OR2_274(WX2708,WX2706,WX2705);
or OR2_275(WX2712,WX2710,WX2709);
or OR2_276(WX2716,WX2714,WX2713);
or OR2_277(WX2722,WX2720,WX2719);
or OR2_278(WX2726,WX2724,WX2723);
or OR2_279(WX2730,WX2728,WX2727);
or OR2_280(WX2736,WX2734,WX2733);
or OR2_281(WX2740,WX2738,WX2737);
or OR2_282(WX2744,WX2742,WX2741);
or OR2_283(WX2750,WX2748,WX2747);
or OR2_284(WX2754,WX2752,WX2751);
or OR2_285(WX2758,WX2756,WX2755);
or OR2_286(WX2764,WX2762,WX2761);
or OR2_287(WX2768,WX2766,WX2765);
or OR2_288(WX2772,WX2770,WX2769);
or OR2_289(WX2778,WX2776,WX2775);
or OR2_290(WX2782,WX2780,WX2779);
or OR2_291(WX2786,WX2784,WX2783);
or OR2_292(WX2792,WX2790,WX2789);
or OR2_293(WX2796,WX2794,WX2793);
or OR2_294(WX2800,WX2798,WX2797);
or OR2_295(WX2806,WX2804,WX2803);
or OR2_296(WX2810,WX2808,WX2807);
or OR2_297(WX2814,WX2812,WX2811);
or OR2_298(WX2820,WX2818,WX2817);
or OR2_299(WX2824,WX2822,WX2821);
or OR2_300(WX2828,WX2826,WX2825);
or OR2_301(WX2834,WX2832,WX2831);
or OR2_302(WX2838,WX2836,WX2835);
or OR2_303(WX2842,WX2840,WX2839);
or OR2_304(WX2848,WX2846,WX2845);
or OR2_305(WX2852,WX2850,WX2849);
or OR2_306(WX2856,WX2854,WX2853);
or OR2_307(WX2862,WX2860,WX2859);
or OR2_308(WX2866,WX2864,WX2863);
or OR2_309(WX2870,WX2868,WX2867);
or OR2_310(WX2876,WX2874,WX2873);
or OR2_311(WX2880,WX2878,WX2877);
or OR2_312(WX2884,WX2882,WX2881);
or OR2_313(WX2890,WX2888,WX2887);
or OR2_314(WX2894,WX2892,WX2891);
or OR2_315(WX2898,WX2896,WX2895);
or OR2_316(WX2904,WX2902,WX2901);
or OR2_317(WX2908,WX2906,WX2905);
or OR2_318(WX2912,WX2910,WX2909);
or OR2_319(WX2918,WX2916,WX2915);
or OR2_320(WX2922,WX2920,WX2919);
or OR2_321(WX2926,WX2924,WX2923);
or OR2_322(WX2932,WX2930,WX2929);
or OR2_323(WX2936,WX2934,WX2933);
or OR2_324(WX2940,WX2938,WX2937);
or OR2_325(WX2946,WX2944,WX2943);
or OR2_326(WX2950,WX2948,WX2947);
or OR2_327(WX2954,WX2952,WX2951);
or OR2_328(WX2960,WX2958,WX2957);
or OR2_329(WX2964,WX2962,WX2961);
or OR2_330(WX2968,WX2966,WX2965);
or OR2_331(WX2974,WX2972,WX2971);
or OR2_332(WX2978,WX2976,WX2975);
or OR2_333(WX2982,WX2980,WX2979);
or OR2_334(WX2988,WX2986,WX2985);
or OR2_335(WX2992,WX2990,WX2989);
or OR2_336(WX2996,WX2994,WX2993);
or OR2_337(WX3002,WX3000,WX2999);
or OR2_338(WX3006,WX3004,WX3003);
or OR2_339(WX3010,WX3008,WX3007);
or OR2_340(WX3016,WX3014,WX3013);
or OR2_341(WX3020,WX3018,WX3017);
or OR2_342(WX3024,WX3022,WX3021);
or OR2_343(WX3030,WX3028,WX3027);
or OR2_344(WX3034,WX3032,WX3031);
or OR2_345(WX3038,WX3036,WX3035);
or OR2_346(WX3044,WX3042,WX3041);
or OR2_347(WX3048,WX3046,WX3045);
or OR2_348(WX3052,WX3050,WX3049);
or OR2_349(WX3058,WX3056,WX3055);
or OR2_350(WX3062,WX3060,WX3059);
or OR2_351(WX3066,WX3064,WX3063);
or OR2_352(WX3596,WX3594,WX3593);
or OR2_353(WX3603,WX3601,WX3600);
or OR2_354(WX3610,WX3608,WX3607);
or OR2_355(WX3617,WX3615,WX3614);
or OR2_356(WX3624,WX3622,WX3621);
or OR2_357(WX3631,WX3629,WX3628);
or OR2_358(WX3638,WX3636,WX3635);
or OR2_359(WX3645,WX3643,WX3642);
or OR2_360(WX3652,WX3650,WX3649);
or OR2_361(WX3659,WX3657,WX3656);
or OR2_362(WX3666,WX3664,WX3663);
or OR2_363(WX3673,WX3671,WX3670);
or OR2_364(WX3680,WX3678,WX3677);
or OR2_365(WX3687,WX3685,WX3684);
or OR2_366(WX3694,WX3692,WX3691);
or OR2_367(WX3701,WX3699,WX3698);
or OR2_368(WX3708,WX3706,WX3705);
or OR2_369(WX3715,WX3713,WX3712);
or OR2_370(WX3722,WX3720,WX3719);
or OR2_371(WX3729,WX3727,WX3726);
or OR2_372(WX3736,WX3734,WX3733);
or OR2_373(WX3743,WX3741,WX3740);
or OR2_374(WX3750,WX3748,WX3747);
or OR2_375(WX3757,WX3755,WX3754);
or OR2_376(WX3764,WX3762,WX3761);
or OR2_377(WX3771,WX3769,WX3768);
or OR2_378(WX3778,WX3776,WX3775);
or OR2_379(WX3785,WX3783,WX3782);
or OR2_380(WX3792,WX3790,WX3789);
or OR2_381(WX3799,WX3797,WX3796);
or OR2_382(WX3806,WX3804,WX3803);
or OR2_383(WX3813,WX3811,WX3810);
or OR2_384(WX3917,WX3915,WX3914);
or OR2_385(WX3921,WX3919,WX3918);
or OR2_386(WX3925,WX3923,WX3922);
or OR2_387(WX3931,WX3929,WX3928);
or OR2_388(WX3935,WX3933,WX3932);
or OR2_389(WX3939,WX3937,WX3936);
or OR2_390(WX3945,WX3943,WX3942);
or OR2_391(WX3949,WX3947,WX3946);
or OR2_392(WX3953,WX3951,WX3950);
or OR2_393(WX3959,WX3957,WX3956);
or OR2_394(WX3963,WX3961,WX3960);
or OR2_395(WX3967,WX3965,WX3964);
or OR2_396(WX3973,WX3971,WX3970);
or OR2_397(WX3977,WX3975,WX3974);
or OR2_398(WX3981,WX3979,WX3978);
or OR2_399(WX3987,WX3985,WX3984);
or OR2_400(WX3991,WX3989,WX3988);
or OR2_401(WX3995,WX3993,WX3992);
or OR2_402(WX4001,WX3999,WX3998);
or OR2_403(WX4005,WX4003,WX4002);
or OR2_404(WX4009,WX4007,WX4006);
or OR2_405(WX4015,WX4013,WX4012);
or OR2_406(WX4019,WX4017,WX4016);
or OR2_407(WX4023,WX4021,WX4020);
or OR2_408(WX4029,WX4027,WX4026);
or OR2_409(WX4033,WX4031,WX4030);
or OR2_410(WX4037,WX4035,WX4034);
or OR2_411(WX4043,WX4041,WX4040);
or OR2_412(WX4047,WX4045,WX4044);
or OR2_413(WX4051,WX4049,WX4048);
or OR2_414(WX4057,WX4055,WX4054);
or OR2_415(WX4061,WX4059,WX4058);
or OR2_416(WX4065,WX4063,WX4062);
or OR2_417(WX4071,WX4069,WX4068);
or OR2_418(WX4075,WX4073,WX4072);
or OR2_419(WX4079,WX4077,WX4076);
or OR2_420(WX4085,WX4083,WX4082);
or OR2_421(WX4089,WX4087,WX4086);
or OR2_422(WX4093,WX4091,WX4090);
or OR2_423(WX4099,WX4097,WX4096);
or OR2_424(WX4103,WX4101,WX4100);
or OR2_425(WX4107,WX4105,WX4104);
or OR2_426(WX4113,WX4111,WX4110);
or OR2_427(WX4117,WX4115,WX4114);
or OR2_428(WX4121,WX4119,WX4118);
or OR2_429(WX4127,WX4125,WX4124);
or OR2_430(WX4131,WX4129,WX4128);
or OR2_431(WX4135,WX4133,WX4132);
or OR2_432(WX4141,WX4139,WX4138);
or OR2_433(WX4145,WX4143,WX4142);
or OR2_434(WX4149,WX4147,WX4146);
or OR2_435(WX4155,WX4153,WX4152);
or OR2_436(WX4159,WX4157,WX4156);
or OR2_437(WX4163,WX4161,WX4160);
or OR2_438(WX4169,WX4167,WX4166);
or OR2_439(WX4173,WX4171,WX4170);
or OR2_440(WX4177,WX4175,WX4174);
or OR2_441(WX4183,WX4181,WX4180);
or OR2_442(WX4187,WX4185,WX4184);
or OR2_443(WX4191,WX4189,WX4188);
or OR2_444(WX4197,WX4195,WX4194);
or OR2_445(WX4201,WX4199,WX4198);
or OR2_446(WX4205,WX4203,WX4202);
or OR2_447(WX4211,WX4209,WX4208);
or OR2_448(WX4215,WX4213,WX4212);
or OR2_449(WX4219,WX4217,WX4216);
or OR2_450(WX4225,WX4223,WX4222);
or OR2_451(WX4229,WX4227,WX4226);
or OR2_452(WX4233,WX4231,WX4230);
or OR2_453(WX4239,WX4237,WX4236);
or OR2_454(WX4243,WX4241,WX4240);
or OR2_455(WX4247,WX4245,WX4244);
or OR2_456(WX4253,WX4251,WX4250);
or OR2_457(WX4257,WX4255,WX4254);
or OR2_458(WX4261,WX4259,WX4258);
or OR2_459(WX4267,WX4265,WX4264);
or OR2_460(WX4271,WX4269,WX4268);
or OR2_461(WX4275,WX4273,WX4272);
or OR2_462(WX4281,WX4279,WX4278);
or OR2_463(WX4285,WX4283,WX4282);
or OR2_464(WX4289,WX4287,WX4286);
or OR2_465(WX4295,WX4293,WX4292);
or OR2_466(WX4299,WX4297,WX4296);
or OR2_467(WX4303,WX4301,WX4300);
or OR2_468(WX4309,WX4307,WX4306);
or OR2_469(WX4313,WX4311,WX4310);
or OR2_470(WX4317,WX4315,WX4314);
or OR2_471(WX4323,WX4321,WX4320);
or OR2_472(WX4327,WX4325,WX4324);
or OR2_473(WX4331,WX4329,WX4328);
or OR2_474(WX4337,WX4335,WX4334);
or OR2_475(WX4341,WX4339,WX4338);
or OR2_476(WX4345,WX4343,WX4342);
or OR2_477(WX4351,WX4349,WX4348);
or OR2_478(WX4355,WX4353,WX4352);
or OR2_479(WX4359,WX4357,WX4356);
or OR2_480(WX4889,WX4887,WX4886);
or OR2_481(WX4896,WX4894,WX4893);
or OR2_482(WX4903,WX4901,WX4900);
or OR2_483(WX4910,WX4908,WX4907);
or OR2_484(WX4917,WX4915,WX4914);
or OR2_485(WX4924,WX4922,WX4921);
or OR2_486(WX4931,WX4929,WX4928);
or OR2_487(WX4938,WX4936,WX4935);
or OR2_488(WX4945,WX4943,WX4942);
or OR2_489(WX4952,WX4950,WX4949);
or OR2_490(WX4959,WX4957,WX4956);
or OR2_491(WX4966,WX4964,WX4963);
or OR2_492(WX4973,WX4971,WX4970);
or OR2_493(WX4980,WX4978,WX4977);
or OR2_494(WX4987,WX4985,WX4984);
or OR2_495(WX4994,WX4992,WX4991);
or OR2_496(WX5001,WX4999,WX4998);
or OR2_497(WX5008,WX5006,WX5005);
or OR2_498(WX5015,WX5013,WX5012);
or OR2_499(WX5022,WX5020,WX5019);
or OR2_500(WX5029,WX5027,WX5026);
or OR2_501(WX5036,WX5034,WX5033);
or OR2_502(WX5043,WX5041,WX5040);
or OR2_503(WX5050,WX5048,WX5047);
or OR2_504(WX5057,WX5055,WX5054);
or OR2_505(WX5064,WX5062,WX5061);
or OR2_506(WX5071,WX5069,WX5068);
or OR2_507(WX5078,WX5076,WX5075);
or OR2_508(WX5085,WX5083,WX5082);
or OR2_509(WX5092,WX5090,WX5089);
or OR2_510(WX5099,WX5097,WX5096);
or OR2_511(WX5106,WX5104,WX5103);
or OR2_512(WX5210,WX5208,WX5207);
or OR2_513(WX5214,WX5212,WX5211);
or OR2_514(WX5218,WX5216,WX5215);
or OR2_515(WX5224,WX5222,WX5221);
or OR2_516(WX5228,WX5226,WX5225);
or OR2_517(WX5232,WX5230,WX5229);
or OR2_518(WX5238,WX5236,WX5235);
or OR2_519(WX5242,WX5240,WX5239);
or OR2_520(WX5246,WX5244,WX5243);
or OR2_521(WX5252,WX5250,WX5249);
or OR2_522(WX5256,WX5254,WX5253);
or OR2_523(WX5260,WX5258,WX5257);
or OR2_524(WX5266,WX5264,WX5263);
or OR2_525(WX5270,WX5268,WX5267);
or OR2_526(WX5274,WX5272,WX5271);
or OR2_527(WX5280,WX5278,WX5277);
or OR2_528(WX5284,WX5282,WX5281);
or OR2_529(WX5288,WX5286,WX5285);
or OR2_530(WX5294,WX5292,WX5291);
or OR2_531(WX5298,WX5296,WX5295);
or OR2_532(WX5302,WX5300,WX5299);
or OR2_533(WX5308,WX5306,WX5305);
or OR2_534(WX5312,WX5310,WX5309);
or OR2_535(WX5316,WX5314,WX5313);
or OR2_536(WX5322,WX5320,WX5319);
or OR2_537(WX5326,WX5324,WX5323);
or OR2_538(WX5330,WX5328,WX5327);
or OR2_539(WX5336,WX5334,WX5333);
or OR2_540(WX5340,WX5338,WX5337);
or OR2_541(WX5344,WX5342,WX5341);
or OR2_542(WX5350,WX5348,WX5347);
or OR2_543(WX5354,WX5352,WX5351);
or OR2_544(WX5358,WX5356,WX5355);
or OR2_545(WX5364,WX5362,WX5361);
or OR2_546(WX5368,WX5366,WX5365);
or OR2_547(WX5372,WX5370,WX5369);
or OR2_548(WX5378,WX5376,WX5375);
or OR2_549(WX5382,WX5380,WX5379);
or OR2_550(WX5386,WX5384,WX5383);
or OR2_551(WX5392,WX5390,WX5389);
or OR2_552(WX5396,WX5394,WX5393);
or OR2_553(WX5400,WX5398,WX5397);
or OR2_554(WX5406,WX5404,WX5403);
or OR2_555(WX5410,WX5408,WX5407);
or OR2_556(WX5414,WX5412,WX5411);
or OR2_557(WX5420,WX5418,WX5417);
or OR2_558(WX5424,WX5422,WX5421);
or OR2_559(WX5428,WX5426,WX5425);
or OR2_560(WX5434,WX5432,WX5431);
or OR2_561(WX5438,WX5436,WX5435);
or OR2_562(WX5442,WX5440,WX5439);
or OR2_563(WX5448,WX5446,WX5445);
or OR2_564(WX5452,WX5450,WX5449);
or OR2_565(WX5456,WX5454,WX5453);
or OR2_566(WX5462,WX5460,WX5459);
or OR2_567(WX5466,WX5464,WX5463);
or OR2_568(WX5470,WX5468,WX5467);
or OR2_569(WX5476,WX5474,WX5473);
or OR2_570(WX5480,WX5478,WX5477);
or OR2_571(WX5484,WX5482,WX5481);
or OR2_572(WX5490,WX5488,WX5487);
or OR2_573(WX5494,WX5492,WX5491);
or OR2_574(WX5498,WX5496,WX5495);
or OR2_575(WX5504,WX5502,WX5501);
or OR2_576(WX5508,WX5506,WX5505);
or OR2_577(WX5512,WX5510,WX5509);
or OR2_578(WX5518,WX5516,WX5515);
or OR2_579(WX5522,WX5520,WX5519);
or OR2_580(WX5526,WX5524,WX5523);
or OR2_581(WX5532,WX5530,WX5529);
or OR2_582(WX5536,WX5534,WX5533);
or OR2_583(WX5540,WX5538,WX5537);
or OR2_584(WX5546,WX5544,WX5543);
or OR2_585(WX5550,WX5548,WX5547);
or OR2_586(WX5554,WX5552,WX5551);
or OR2_587(WX5560,WX5558,WX5557);
or OR2_588(WX5564,WX5562,WX5561);
or OR2_589(WX5568,WX5566,WX5565);
or OR2_590(WX5574,WX5572,WX5571);
or OR2_591(WX5578,WX5576,WX5575);
or OR2_592(WX5582,WX5580,WX5579);
or OR2_593(WX5588,WX5586,WX5585);
or OR2_594(WX5592,WX5590,WX5589);
or OR2_595(WX5596,WX5594,WX5593);
or OR2_596(WX5602,WX5600,WX5599);
or OR2_597(WX5606,WX5604,WX5603);
or OR2_598(WX5610,WX5608,WX5607);
or OR2_599(WX5616,WX5614,WX5613);
or OR2_600(WX5620,WX5618,WX5617);
or OR2_601(WX5624,WX5622,WX5621);
or OR2_602(WX5630,WX5628,WX5627);
or OR2_603(WX5634,WX5632,WX5631);
or OR2_604(WX5638,WX5636,WX5635);
or OR2_605(WX5644,WX5642,WX5641);
or OR2_606(WX5648,WX5646,WX5645);
or OR2_607(WX5652,WX5650,WX5649);
or OR2_608(WX6182,WX6180,WX6179);
or OR2_609(WX6189,WX6187,WX6186);
or OR2_610(WX6196,WX6194,WX6193);
or OR2_611(WX6203,WX6201,WX6200);
or OR2_612(WX6210,WX6208,WX6207);
or OR2_613(WX6217,WX6215,WX6214);
or OR2_614(WX6224,WX6222,WX6221);
or OR2_615(WX6231,WX6229,WX6228);
or OR2_616(WX6238,WX6236,WX6235);
or OR2_617(WX6245,WX6243,WX6242);
or OR2_618(WX6252,WX6250,WX6249);
or OR2_619(WX6259,WX6257,WX6256);
or OR2_620(WX6266,WX6264,WX6263);
or OR2_621(WX6273,WX6271,WX6270);
or OR2_622(WX6280,WX6278,WX6277);
or OR2_623(WX6287,WX6285,WX6284);
or OR2_624(WX6294,WX6292,WX6291);
or OR2_625(WX6301,WX6299,WX6298);
or OR2_626(WX6308,WX6306,WX6305);
or OR2_627(WX6315,WX6313,WX6312);
or OR2_628(WX6322,WX6320,WX6319);
or OR2_629(WX6329,WX6327,WX6326);
or OR2_630(WX6336,WX6334,WX6333);
or OR2_631(WX6343,WX6341,WX6340);
or OR2_632(WX6350,WX6348,WX6347);
or OR2_633(WX6357,WX6355,WX6354);
or OR2_634(WX6364,WX6362,WX6361);
or OR2_635(WX6371,WX6369,WX6368);
or OR2_636(WX6378,WX6376,WX6375);
or OR2_637(WX6385,WX6383,WX6382);
or OR2_638(WX6392,WX6390,WX6389);
or OR2_639(WX6399,WX6397,WX6396);
or OR2_640(WX6503,WX6501,WX6500);
or OR2_641(WX6507,WX6505,WX6504);
or OR2_642(WX6511,WX6509,WX6508);
or OR2_643(WX6517,WX6515,WX6514);
or OR2_644(WX6521,WX6519,WX6518);
or OR2_645(WX6525,WX6523,WX6522);
or OR2_646(WX6531,WX6529,WX6528);
or OR2_647(WX6535,WX6533,WX6532);
or OR2_648(WX6539,WX6537,WX6536);
or OR2_649(WX6545,WX6543,WX6542);
or OR2_650(WX6549,WX6547,WX6546);
or OR2_651(WX6553,WX6551,WX6550);
or OR2_652(WX6559,WX6557,WX6556);
or OR2_653(WX6563,WX6561,WX6560);
or OR2_654(WX6567,WX6565,WX6564);
or OR2_655(WX6573,WX6571,WX6570);
or OR2_656(WX6577,WX6575,WX6574);
or OR2_657(WX6581,WX6579,WX6578);
or OR2_658(WX6587,WX6585,WX6584);
or OR2_659(WX6591,WX6589,WX6588);
or OR2_660(WX6595,WX6593,WX6592);
or OR2_661(WX6601,WX6599,WX6598);
or OR2_662(WX6605,WX6603,WX6602);
or OR2_663(WX6609,WX6607,WX6606);
or OR2_664(WX6615,WX6613,WX6612);
or OR2_665(WX6619,WX6617,WX6616);
or OR2_666(WX6623,WX6621,WX6620);
or OR2_667(WX6629,WX6627,WX6626);
or OR2_668(WX6633,WX6631,WX6630);
or OR2_669(WX6637,WX6635,WX6634);
or OR2_670(WX6643,WX6641,WX6640);
or OR2_671(WX6647,WX6645,WX6644);
or OR2_672(WX6651,WX6649,WX6648);
or OR2_673(WX6657,WX6655,WX6654);
or OR2_674(WX6661,WX6659,WX6658);
or OR2_675(WX6665,WX6663,WX6662);
or OR2_676(WX6671,WX6669,WX6668);
or OR2_677(WX6675,WX6673,WX6672);
or OR2_678(WX6679,WX6677,WX6676);
or OR2_679(WX6685,WX6683,WX6682);
or OR2_680(WX6689,WX6687,WX6686);
or OR2_681(WX6693,WX6691,WX6690);
or OR2_682(WX6699,WX6697,WX6696);
or OR2_683(WX6703,WX6701,WX6700);
or OR2_684(WX6707,WX6705,WX6704);
or OR2_685(WX6713,WX6711,WX6710);
or OR2_686(WX6717,WX6715,WX6714);
or OR2_687(WX6721,WX6719,WX6718);
or OR2_688(WX6727,WX6725,WX6724);
or OR2_689(WX6731,WX6729,WX6728);
or OR2_690(WX6735,WX6733,WX6732);
or OR2_691(WX6741,WX6739,WX6738);
or OR2_692(WX6745,WX6743,WX6742);
or OR2_693(WX6749,WX6747,WX6746);
or OR2_694(WX6755,WX6753,WX6752);
or OR2_695(WX6759,WX6757,WX6756);
or OR2_696(WX6763,WX6761,WX6760);
or OR2_697(WX6769,WX6767,WX6766);
or OR2_698(WX6773,WX6771,WX6770);
or OR2_699(WX6777,WX6775,WX6774);
or OR2_700(WX6783,WX6781,WX6780);
or OR2_701(WX6787,WX6785,WX6784);
or OR2_702(WX6791,WX6789,WX6788);
or OR2_703(WX6797,WX6795,WX6794);
or OR2_704(WX6801,WX6799,WX6798);
or OR2_705(WX6805,WX6803,WX6802);
or OR2_706(WX6811,WX6809,WX6808);
or OR2_707(WX6815,WX6813,WX6812);
or OR2_708(WX6819,WX6817,WX6816);
or OR2_709(WX6825,WX6823,WX6822);
or OR2_710(WX6829,WX6827,WX6826);
or OR2_711(WX6833,WX6831,WX6830);
or OR2_712(WX6839,WX6837,WX6836);
or OR2_713(WX6843,WX6841,WX6840);
or OR2_714(WX6847,WX6845,WX6844);
or OR2_715(WX6853,WX6851,WX6850);
or OR2_716(WX6857,WX6855,WX6854);
or OR2_717(WX6861,WX6859,WX6858);
or OR2_718(WX6867,WX6865,WX6864);
or OR2_719(WX6871,WX6869,WX6868);
or OR2_720(WX6875,WX6873,WX6872);
or OR2_721(WX6881,WX6879,WX6878);
or OR2_722(WX6885,WX6883,WX6882);
or OR2_723(WX6889,WX6887,WX6886);
or OR2_724(WX6895,WX6893,WX6892);
or OR2_725(WX6899,WX6897,WX6896);
or OR2_726(WX6903,WX6901,WX6900);
or OR2_727(WX6909,WX6907,WX6906);
or OR2_728(WX6913,WX6911,WX6910);
or OR2_729(WX6917,WX6915,WX6914);
or OR2_730(WX6923,WX6921,WX6920);
or OR2_731(WX6927,WX6925,WX6924);
or OR2_732(WX6931,WX6929,WX6928);
or OR2_733(WX6937,WX6935,WX6934);
or OR2_734(WX6941,WX6939,WX6938);
or OR2_735(WX6945,WX6943,WX6942);
or OR2_736(WX7475,WX7473,WX7472);
or OR2_737(WX7482,WX7480,WX7479);
or OR2_738(WX7489,WX7487,WX7486);
or OR2_739(WX7496,WX7494,WX7493);
or OR2_740(WX7503,WX7501,WX7500);
or OR2_741(WX7510,WX7508,WX7507);
or OR2_742(WX7517,WX7515,WX7514);
or OR2_743(WX7524,WX7522,WX7521);
or OR2_744(WX7531,WX7529,WX7528);
or OR2_745(WX7538,WX7536,WX7535);
or OR2_746(WX7545,WX7543,WX7542);
or OR2_747(WX7552,WX7550,WX7549);
or OR2_748(WX7559,WX7557,WX7556);
or OR2_749(WX7566,WX7564,WX7563);
or OR2_750(WX7573,WX7571,WX7570);
or OR2_751(WX7580,WX7578,WX7577);
or OR2_752(WX7587,WX7585,WX7584);
or OR2_753(WX7594,WX7592,WX7591);
or OR2_754(WX7601,WX7599,WX7598);
or OR2_755(WX7608,WX7606,WX7605);
or OR2_756(WX7615,WX7613,WX7612);
or OR2_757(WX7622,WX7620,WX7619);
or OR2_758(WX7629,WX7627,WX7626);
or OR2_759(WX7636,WX7634,WX7633);
or OR2_760(WX7643,WX7641,WX7640);
or OR2_761(WX7650,WX7648,WX7647);
or OR2_762(WX7657,WX7655,WX7654);
or OR2_763(WX7664,WX7662,WX7661);
or OR2_764(WX7671,WX7669,WX7668);
or OR2_765(WX7678,WX7676,WX7675);
or OR2_766(WX7685,WX7683,WX7682);
or OR2_767(WX7692,WX7690,WX7689);
or OR2_768(WX7796,WX7794,WX7793);
or OR2_769(WX7800,WX7798,WX7797);
or OR2_770(WX7804,WX7802,WX7801);
or OR2_771(WX7810,WX7808,WX7807);
or OR2_772(WX7814,WX7812,WX7811);
or OR2_773(WX7818,WX7816,WX7815);
or OR2_774(WX7824,WX7822,WX7821);
or OR2_775(WX7828,WX7826,WX7825);
or OR2_776(WX7832,WX7830,WX7829);
or OR2_777(WX7838,WX7836,WX7835);
or OR2_778(WX7842,WX7840,WX7839);
or OR2_779(WX7846,WX7844,WX7843);
or OR2_780(WX7852,WX7850,WX7849);
or OR2_781(WX7856,WX7854,WX7853);
or OR2_782(WX7860,WX7858,WX7857);
or OR2_783(WX7866,WX7864,WX7863);
or OR2_784(WX7870,WX7868,WX7867);
or OR2_785(WX7874,WX7872,WX7871);
or OR2_786(WX7880,WX7878,WX7877);
or OR2_787(WX7884,WX7882,WX7881);
or OR2_788(WX7888,WX7886,WX7885);
or OR2_789(WX7894,WX7892,WX7891);
or OR2_790(WX7898,WX7896,WX7895);
or OR2_791(WX7902,WX7900,WX7899);
or OR2_792(WX7908,WX7906,WX7905);
or OR2_793(WX7912,WX7910,WX7909);
or OR2_794(WX7916,WX7914,WX7913);
or OR2_795(WX7922,WX7920,WX7919);
or OR2_796(WX7926,WX7924,WX7923);
or OR2_797(WX7930,WX7928,WX7927);
or OR2_798(WX7936,WX7934,WX7933);
or OR2_799(WX7940,WX7938,WX7937);
or OR2_800(WX7944,WX7942,WX7941);
or OR2_801(WX7950,WX7948,WX7947);
or OR2_802(WX7954,WX7952,WX7951);
or OR2_803(WX7958,WX7956,WX7955);
or OR2_804(WX7964,WX7962,WX7961);
or OR2_805(WX7968,WX7966,WX7965);
or OR2_806(WX7972,WX7970,WX7969);
or OR2_807(WX7978,WX7976,WX7975);
or OR2_808(WX7982,WX7980,WX7979);
or OR2_809(WX7986,WX7984,WX7983);
or OR2_810(WX7992,WX7990,WX7989);
or OR2_811(WX7996,WX7994,WX7993);
or OR2_812(WX8000,WX7998,WX7997);
or OR2_813(WX8006,WX8004,WX8003);
or OR2_814(WX8010,WX8008,WX8007);
or OR2_815(WX8014,WX8012,WX8011);
or OR2_816(WX8020,WX8018,WX8017);
or OR2_817(WX8024,WX8022,WX8021);
or OR2_818(WX8028,WX8026,WX8025);
or OR2_819(WX8034,WX8032,WX8031);
or OR2_820(WX8038,WX8036,WX8035);
or OR2_821(WX8042,WX8040,WX8039);
or OR2_822(WX8048,WX8046,WX8045);
or OR2_823(WX8052,WX8050,WX8049);
or OR2_824(WX8056,WX8054,WX8053);
or OR2_825(WX8062,WX8060,WX8059);
or OR2_826(WX8066,WX8064,WX8063);
or OR2_827(WX8070,WX8068,WX8067);
or OR2_828(WX8076,WX8074,WX8073);
or OR2_829(WX8080,WX8078,WX8077);
or OR2_830(WX8084,WX8082,WX8081);
or OR2_831(WX8090,WX8088,WX8087);
or OR2_832(WX8094,WX8092,WX8091);
or OR2_833(WX8098,WX8096,WX8095);
or OR2_834(WX8104,WX8102,WX8101);
or OR2_835(WX8108,WX8106,WX8105);
or OR2_836(WX8112,WX8110,WX8109);
or OR2_837(WX8118,WX8116,WX8115);
or OR2_838(WX8122,WX8120,WX8119);
or OR2_839(WX8126,WX8124,WX8123);
or OR2_840(WX8132,WX8130,WX8129);
or OR2_841(WX8136,WX8134,WX8133);
or OR2_842(WX8140,WX8138,WX8137);
or OR2_843(WX8146,WX8144,WX8143);
or OR2_844(WX8150,WX8148,WX8147);
or OR2_845(WX8154,WX8152,WX8151);
or OR2_846(WX8160,WX8158,WX8157);
or OR2_847(WX8164,WX8162,WX8161);
or OR2_848(WX8168,WX8166,WX8165);
or OR2_849(WX8174,WX8172,WX8171);
or OR2_850(WX8178,WX8176,WX8175);
or OR2_851(WX8182,WX8180,WX8179);
or OR2_852(WX8188,WX8186,WX8185);
or OR2_853(WX8192,WX8190,WX8189);
or OR2_854(WX8196,WX8194,WX8193);
or OR2_855(WX8202,WX8200,WX8199);
or OR2_856(WX8206,WX8204,WX8203);
or OR2_857(WX8210,WX8208,WX8207);
or OR2_858(WX8216,WX8214,WX8213);
or OR2_859(WX8220,WX8218,WX8217);
or OR2_860(WX8224,WX8222,WX8221);
or OR2_861(WX8230,WX8228,WX8227);
or OR2_862(WX8234,WX8232,WX8231);
or OR2_863(WX8238,WX8236,WX8235);
or OR2_864(WX8768,WX8766,WX8765);
or OR2_865(WX8775,WX8773,WX8772);
or OR2_866(WX8782,WX8780,WX8779);
or OR2_867(WX8789,WX8787,WX8786);
or OR2_868(WX8796,WX8794,WX8793);
or OR2_869(WX8803,WX8801,WX8800);
or OR2_870(WX8810,WX8808,WX8807);
or OR2_871(WX8817,WX8815,WX8814);
or OR2_872(WX8824,WX8822,WX8821);
or OR2_873(WX8831,WX8829,WX8828);
or OR2_874(WX8838,WX8836,WX8835);
or OR2_875(WX8845,WX8843,WX8842);
or OR2_876(WX8852,WX8850,WX8849);
or OR2_877(WX8859,WX8857,WX8856);
or OR2_878(WX8866,WX8864,WX8863);
or OR2_879(WX8873,WX8871,WX8870);
or OR2_880(WX8880,WX8878,WX8877);
or OR2_881(WX8887,WX8885,WX8884);
or OR2_882(WX8894,WX8892,WX8891);
or OR2_883(WX8901,WX8899,WX8898);
or OR2_884(WX8908,WX8906,WX8905);
or OR2_885(WX8915,WX8913,WX8912);
or OR2_886(WX8922,WX8920,WX8919);
or OR2_887(WX8929,WX8927,WX8926);
or OR2_888(WX8936,WX8934,WX8933);
or OR2_889(WX8943,WX8941,WX8940);
or OR2_890(WX8950,WX8948,WX8947);
or OR2_891(WX8957,WX8955,WX8954);
or OR2_892(WX8964,WX8962,WX8961);
or OR2_893(WX8971,WX8969,WX8968);
or OR2_894(WX8978,WX8976,WX8975);
or OR2_895(WX8985,WX8983,WX8982);
or OR2_896(WX9089,WX9087,WX9086);
or OR2_897(WX9093,WX9091,WX9090);
or OR2_898(WX9097,WX9095,WX9094);
or OR2_899(WX9103,WX9101,WX9100);
or OR2_900(WX9107,WX9105,WX9104);
or OR2_901(WX9111,WX9109,WX9108);
or OR2_902(WX9117,WX9115,WX9114);
or OR2_903(WX9121,WX9119,WX9118);
or OR2_904(WX9125,WX9123,WX9122);
or OR2_905(WX9131,WX9129,WX9128);
or OR2_906(WX9135,WX9133,WX9132);
or OR2_907(WX9139,WX9137,WX9136);
or OR2_908(WX9145,WX9143,WX9142);
or OR2_909(WX9149,WX9147,WX9146);
or OR2_910(WX9153,WX9151,WX9150);
or OR2_911(WX9159,WX9157,WX9156);
or OR2_912(WX9163,WX9161,WX9160);
or OR2_913(WX9167,WX9165,WX9164);
or OR2_914(WX9173,WX9171,WX9170);
or OR2_915(WX9177,WX9175,WX9174);
or OR2_916(WX9181,WX9179,WX9178);
or OR2_917(WX9187,WX9185,WX9184);
or OR2_918(WX9191,WX9189,WX9188);
or OR2_919(WX9195,WX9193,WX9192);
or OR2_920(WX9201,WX9199,WX9198);
or OR2_921(WX9205,WX9203,WX9202);
or OR2_922(WX9209,WX9207,WX9206);
or OR2_923(WX9215,WX9213,WX9212);
or OR2_924(WX9219,WX9217,WX9216);
or OR2_925(WX9223,WX9221,WX9220);
or OR2_926(WX9229,WX9227,WX9226);
or OR2_927(WX9233,WX9231,WX9230);
or OR2_928(WX9237,WX9235,WX9234);
or OR2_929(WX9243,WX9241,WX9240);
or OR2_930(WX9247,WX9245,WX9244);
or OR2_931(WX9251,WX9249,WX9248);
or OR2_932(WX9257,WX9255,WX9254);
or OR2_933(WX9261,WX9259,WX9258);
or OR2_934(WX9265,WX9263,WX9262);
or OR2_935(WX9271,WX9269,WX9268);
or OR2_936(WX9275,WX9273,WX9272);
or OR2_937(WX9279,WX9277,WX9276);
or OR2_938(WX9285,WX9283,WX9282);
or OR2_939(WX9289,WX9287,WX9286);
or OR2_940(WX9293,WX9291,WX9290);
or OR2_941(WX9299,WX9297,WX9296);
or OR2_942(WX9303,WX9301,WX9300);
or OR2_943(WX9307,WX9305,WX9304);
or OR2_944(WX9313,WX9311,WX9310);
or OR2_945(WX9317,WX9315,WX9314);
or OR2_946(WX9321,WX9319,WX9318);
or OR2_947(WX9327,WX9325,WX9324);
or OR2_948(WX9331,WX9329,WX9328);
or OR2_949(WX9335,WX9333,WX9332);
or OR2_950(WX9341,WX9339,WX9338);
or OR2_951(WX9345,WX9343,WX9342);
or OR2_952(WX9349,WX9347,WX9346);
or OR2_953(WX9355,WX9353,WX9352);
or OR2_954(WX9359,WX9357,WX9356);
or OR2_955(WX9363,WX9361,WX9360);
or OR2_956(WX9369,WX9367,WX9366);
or OR2_957(WX9373,WX9371,WX9370);
or OR2_958(WX9377,WX9375,WX9374);
or OR2_959(WX9383,WX9381,WX9380);
or OR2_960(WX9387,WX9385,WX9384);
or OR2_961(WX9391,WX9389,WX9388);
or OR2_962(WX9397,WX9395,WX9394);
or OR2_963(WX9401,WX9399,WX9398);
or OR2_964(WX9405,WX9403,WX9402);
or OR2_965(WX9411,WX9409,WX9408);
or OR2_966(WX9415,WX9413,WX9412);
or OR2_967(WX9419,WX9417,WX9416);
or OR2_968(WX9425,WX9423,WX9422);
or OR2_969(WX9429,WX9427,WX9426);
or OR2_970(WX9433,WX9431,WX9430);
or OR2_971(WX9439,WX9437,WX9436);
or OR2_972(WX9443,WX9441,WX9440);
or OR2_973(WX9447,WX9445,WX9444);
or OR2_974(WX9453,WX9451,WX9450);
or OR2_975(WX9457,WX9455,WX9454);
or OR2_976(WX9461,WX9459,WX9458);
or OR2_977(WX9467,WX9465,WX9464);
or OR2_978(WX9471,WX9469,WX9468);
or OR2_979(WX9475,WX9473,WX9472);
or OR2_980(WX9481,WX9479,WX9478);
or OR2_981(WX9485,WX9483,WX9482);
or OR2_982(WX9489,WX9487,WX9486);
or OR2_983(WX9495,WX9493,WX9492);
or OR2_984(WX9499,WX9497,WX9496);
or OR2_985(WX9503,WX9501,WX9500);
or OR2_986(WX9509,WX9507,WX9506);
or OR2_987(WX9513,WX9511,WX9510);
or OR2_988(WX9517,WX9515,WX9514);
or OR2_989(WX9523,WX9521,WX9520);
or OR2_990(WX9527,WX9525,WX9524);
or OR2_991(WX9531,WX9529,WX9528);
or OR2_992(WX10061,WX10059,WX10058);
or OR2_993(WX10068,WX10066,WX10065);
or OR2_994(WX10075,WX10073,WX10072);
or OR2_995(WX10082,WX10080,WX10079);
or OR2_996(WX10089,WX10087,WX10086);
or OR2_997(WX10096,WX10094,WX10093);
or OR2_998(WX10103,WX10101,WX10100);
or OR2_999(WX10110,WX10108,WX10107);
or OR2_1000(WX10117,WX10115,WX10114);
or OR2_1001(WX10124,WX10122,WX10121);
or OR2_1002(WX10131,WX10129,WX10128);
or OR2_1003(WX10138,WX10136,WX10135);
or OR2_1004(WX10145,WX10143,WX10142);
or OR2_1005(WX10152,WX10150,WX10149);
or OR2_1006(WX10159,WX10157,WX10156);
or OR2_1007(WX10166,WX10164,WX10163);
or OR2_1008(WX10173,WX10171,WX10170);
or OR2_1009(WX10180,WX10178,WX10177);
or OR2_1010(WX10187,WX10185,WX10184);
or OR2_1011(WX10194,WX10192,WX10191);
or OR2_1012(WX10201,WX10199,WX10198);
or OR2_1013(WX10208,WX10206,WX10205);
or OR2_1014(WX10215,WX10213,WX10212);
or OR2_1015(WX10222,WX10220,WX10219);
or OR2_1016(WX10229,WX10227,WX10226);
or OR2_1017(WX10236,WX10234,WX10233);
or OR2_1018(WX10243,WX10241,WX10240);
or OR2_1019(WX10250,WX10248,WX10247);
or OR2_1020(WX10257,WX10255,WX10254);
or OR2_1021(WX10264,WX10262,WX10261);
or OR2_1022(WX10271,WX10269,WX10268);
or OR2_1023(WX10278,WX10276,WX10275);
or OR2_1024(WX10382,WX10380,WX10379);
or OR2_1025(WX10386,WX10384,WX10383);
or OR2_1026(WX10390,WX10388,WX10387);
or OR2_1027(WX10396,WX10394,WX10393);
or OR2_1028(WX10400,WX10398,WX10397);
or OR2_1029(WX10404,WX10402,WX10401);
or OR2_1030(WX10410,WX10408,WX10407);
or OR2_1031(WX10414,WX10412,WX10411);
or OR2_1032(WX10418,WX10416,WX10415);
or OR2_1033(WX10424,WX10422,WX10421);
or OR2_1034(WX10428,WX10426,WX10425);
or OR2_1035(WX10432,WX10430,WX10429);
or OR2_1036(WX10438,WX10436,WX10435);
or OR2_1037(WX10442,WX10440,WX10439);
or OR2_1038(WX10446,WX10444,WX10443);
or OR2_1039(WX10452,WX10450,WX10449);
or OR2_1040(WX10456,WX10454,WX10453);
or OR2_1041(WX10460,WX10458,WX10457);
or OR2_1042(WX10466,WX10464,WX10463);
or OR2_1043(WX10470,WX10468,WX10467);
or OR2_1044(WX10474,WX10472,WX10471);
or OR2_1045(WX10480,WX10478,WX10477);
or OR2_1046(WX10484,WX10482,WX10481);
or OR2_1047(WX10488,WX10486,WX10485);
or OR2_1048(WX10494,WX10492,WX10491);
or OR2_1049(WX10498,WX10496,WX10495);
or OR2_1050(WX10502,WX10500,WX10499);
or OR2_1051(WX10508,WX10506,WX10505);
or OR2_1052(WX10512,WX10510,WX10509);
or OR2_1053(WX10516,WX10514,WX10513);
or OR2_1054(WX10522,WX10520,WX10519);
or OR2_1055(WX10526,WX10524,WX10523);
or OR2_1056(WX10530,WX10528,WX10527);
or OR2_1057(WX10536,WX10534,WX10533);
or OR2_1058(WX10540,WX10538,WX10537);
or OR2_1059(WX10544,WX10542,WX10541);
or OR2_1060(WX10550,WX10548,WX10547);
or OR2_1061(WX10554,WX10552,WX10551);
or OR2_1062(WX10558,WX10556,WX10555);
or OR2_1063(WX10564,WX10562,WX10561);
or OR2_1064(WX10568,WX10566,WX10565);
or OR2_1065(WX10572,WX10570,WX10569);
or OR2_1066(WX10578,WX10576,WX10575);
or OR2_1067(WX10582,WX10580,WX10579);
or OR2_1068(WX10586,WX10584,WX10583);
or OR2_1069(WX10592,WX10590,WX10589);
or OR2_1070(WX10596,WX10594,WX10593);
or OR2_1071(WX10600,WX10598,WX10597);
or OR2_1072(WX10606,WX10604,WX10603);
or OR2_1073(WX10610,WX10608,WX10607);
or OR2_1074(WX10614,WX10612,WX10611);
or OR2_1075(WX10620,WX10618,WX10617);
or OR2_1076(WX10624,WX10622,WX10621);
or OR2_1077(WX10628,WX10626,WX10625);
or OR2_1078(WX10634,WX10632,WX10631);
or OR2_1079(WX10638,WX10636,WX10635);
or OR2_1080(WX10642,WX10640,WX10639);
or OR2_1081(WX10648,WX10646,WX10645);
or OR2_1082(WX10652,WX10650,WX10649);
or OR2_1083(WX10656,WX10654,WX10653);
or OR2_1084(WX10662,WX10660,WX10659);
or OR2_1085(WX10666,WX10664,WX10663);
or OR2_1086(WX10670,WX10668,WX10667);
or OR2_1087(WX10676,WX10674,WX10673);
or OR2_1088(WX10680,WX10678,WX10677);
or OR2_1089(WX10684,WX10682,WX10681);
or OR2_1090(WX10690,WX10688,WX10687);
or OR2_1091(WX10694,WX10692,WX10691);
or OR2_1092(WX10698,WX10696,WX10695);
or OR2_1093(WX10704,WX10702,WX10701);
or OR2_1094(WX10708,WX10706,WX10705);
or OR2_1095(WX10712,WX10710,WX10709);
or OR2_1096(WX10718,WX10716,WX10715);
or OR2_1097(WX10722,WX10720,WX10719);
or OR2_1098(WX10726,WX10724,WX10723);
or OR2_1099(WX10732,WX10730,WX10729);
or OR2_1100(WX10736,WX10734,WX10733);
or OR2_1101(WX10740,WX10738,WX10737);
or OR2_1102(WX10746,WX10744,WX10743);
or OR2_1103(WX10750,WX10748,WX10747);
or OR2_1104(WX10754,WX10752,WX10751);
or OR2_1105(WX10760,WX10758,WX10757);
or OR2_1106(WX10764,WX10762,WX10761);
or OR2_1107(WX10768,WX10766,WX10765);
or OR2_1108(WX10774,WX10772,WX10771);
or OR2_1109(WX10778,WX10776,WX10775);
or OR2_1110(WX10782,WX10780,WX10779);
or OR2_1111(WX10788,WX10786,WX10785);
or OR2_1112(WX10792,WX10790,WX10789);
or OR2_1113(WX10796,WX10794,WX10793);
or OR2_1114(WX10802,WX10800,WX10799);
or OR2_1115(WX10806,WX10804,WX10803);
or OR2_1116(WX10810,WX10808,WX10807);
or OR2_1117(WX10816,WX10814,WX10813);
or OR2_1118(WX10820,WX10818,WX10817);
or OR2_1119(WX10824,WX10822,WX10821);
or OR2_1120(WX11354,WX11352,WX11351);
or OR2_1121(WX11361,WX11359,WX11358);
or OR2_1122(WX11368,WX11366,WX11365);
or OR2_1123(WX11375,WX11373,WX11372);
or OR2_1124(WX11382,WX11380,WX11379);
or OR2_1125(WX11389,WX11387,WX11386);
or OR2_1126(WX11396,WX11394,WX11393);
or OR2_1127(WX11403,WX11401,WX11400);
or OR2_1128(WX11410,WX11408,WX11407);
or OR2_1129(WX11417,WX11415,WX11414);
or OR2_1130(WX11424,WX11422,WX11421);
or OR2_1131(WX11431,WX11429,WX11428);
or OR2_1132(WX11438,WX11436,WX11435);
or OR2_1133(WX11445,WX11443,WX11442);
or OR2_1134(WX11452,WX11450,WX11449);
or OR2_1135(WX11459,WX11457,WX11456);
or OR2_1136(WX11466,WX11464,WX11463);
or OR2_1137(WX11473,WX11471,WX11470);
or OR2_1138(WX11480,WX11478,WX11477);
or OR2_1139(WX11487,WX11485,WX11484);
or OR2_1140(WX11494,WX11492,WX11491);
or OR2_1141(WX11501,WX11499,WX11498);
or OR2_1142(WX11508,WX11506,WX11505);
or OR2_1143(WX11515,WX11513,WX11512);
or OR2_1144(WX11522,WX11520,WX11519);
or OR2_1145(WX11529,WX11527,WX11526);
or OR2_1146(WX11536,WX11534,WX11533);
or OR2_1147(WX11543,WX11541,WX11540);
or OR2_1148(WX11550,WX11548,WX11547);
or OR2_1149(WX11557,WX11555,WX11554);
or OR2_1150(WX11564,WX11562,WX11561);
or OR2_1151(WX11571,WX11569,WX11568);
nand NAND2_0(II1988,WX1001,WX645);
nand NAND2_1(II1989,WX1001,II1988);
nand NAND2_2(II1990,WX645,II1988);
nand NAND2_3(II1987,II1989,II1990);
nand NAND2_4(II1995,WX709,II1987);
nand NAND2_5(II1996,WX709,II1995);
nand NAND2_6(II1997,II1987,II1995);
nand NAND2_7(II1986,II1996,II1997);
nand NAND2_8(II2003,WX773,WX837);
nand NAND2_9(II2004,WX773,II2003);
nand NAND2_10(II2005,WX837,II2003);
nand NAND2_11(II2002,II2004,II2005);
nand NAND2_12(II2010,II1986,II2002);
nand NAND2_13(II2011,II1986,II2010);
nand NAND2_14(II2012,II2002,II2010);
nand NAND2_15(WX900,II2011,II2012);
nand NAND2_16(II2019,WX1001,WX647);
nand NAND2_17(II2020,WX1001,II2019);
nand NAND2_18(II2021,WX647,II2019);
nand NAND2_19(II2018,II2020,II2021);
nand NAND2_20(II2026,WX711,II2018);
nand NAND2_21(II2027,WX711,II2026);
nand NAND2_22(II2028,II2018,II2026);
nand NAND2_23(II2017,II2027,II2028);
nand NAND2_24(II2034,WX775,WX839);
nand NAND2_25(II2035,WX775,II2034);
nand NAND2_26(II2036,WX839,II2034);
nand NAND2_27(II2033,II2035,II2036);
nand NAND2_28(II2041,II2017,II2033);
nand NAND2_29(II2042,II2017,II2041);
nand NAND2_30(II2043,II2033,II2041);
nand NAND2_31(WX901,II2042,II2043);
nand NAND2_32(II2050,WX1001,WX649);
nand NAND2_33(II2051,WX1001,II2050);
nand NAND2_34(II2052,WX649,II2050);
nand NAND2_35(II2049,II2051,II2052);
nand NAND2_36(II2057,WX713,II2049);
nand NAND2_37(II2058,WX713,II2057);
nand NAND2_38(II2059,II2049,II2057);
nand NAND2_39(II2048,II2058,II2059);
nand NAND2_40(II2065,WX777,WX841);
nand NAND2_41(II2066,WX777,II2065);
nand NAND2_42(II2067,WX841,II2065);
nand NAND2_43(II2064,II2066,II2067);
nand NAND2_44(II2072,II2048,II2064);
nand NAND2_45(II2073,II2048,II2072);
nand NAND2_46(II2074,II2064,II2072);
nand NAND2_47(WX902,II2073,II2074);
nand NAND2_48(II2081,WX1001,WX651);
nand NAND2_49(II2082,WX1001,II2081);
nand NAND2_50(II2083,WX651,II2081);
nand NAND2_51(II2080,II2082,II2083);
nand NAND2_52(II2088,WX715,II2080);
nand NAND2_53(II2089,WX715,II2088);
nand NAND2_54(II2090,II2080,II2088);
nand NAND2_55(II2079,II2089,II2090);
nand NAND2_56(II2096,WX779,WX843);
nand NAND2_57(II2097,WX779,II2096);
nand NAND2_58(II2098,WX843,II2096);
nand NAND2_59(II2095,II2097,II2098);
nand NAND2_60(II2103,II2079,II2095);
nand NAND2_61(II2104,II2079,II2103);
nand NAND2_62(II2105,II2095,II2103);
nand NAND2_63(WX903,II2104,II2105);
nand NAND2_64(II2112,WX1001,WX653);
nand NAND2_65(II2113,WX1001,II2112);
nand NAND2_66(II2114,WX653,II2112);
nand NAND2_67(II2111,II2113,II2114);
nand NAND2_68(II2119,WX717,II2111);
nand NAND2_69(II2120,WX717,II2119);
nand NAND2_70(II2121,II2111,II2119);
nand NAND2_71(II2110,II2120,II2121);
nand NAND2_72(II2127,WX781,WX845);
nand NAND2_73(II2128,WX781,II2127);
nand NAND2_74(II2129,WX845,II2127);
nand NAND2_75(II2126,II2128,II2129);
nand NAND2_76(II2134,II2110,II2126);
nand NAND2_77(II2135,II2110,II2134);
nand NAND2_78(II2136,II2126,II2134);
nand NAND2_79(WX904,II2135,II2136);
nand NAND2_80(II2143,WX1001,WX655);
nand NAND2_81(II2144,WX1001,II2143);
nand NAND2_82(II2145,WX655,II2143);
nand NAND2_83(II2142,II2144,II2145);
nand NAND2_84(II2150,WX719,II2142);
nand NAND2_85(II2151,WX719,II2150);
nand NAND2_86(II2152,II2142,II2150);
nand NAND2_87(II2141,II2151,II2152);
nand NAND2_88(II2158,WX783,WX847);
nand NAND2_89(II2159,WX783,II2158);
nand NAND2_90(II2160,WX847,II2158);
nand NAND2_91(II2157,II2159,II2160);
nand NAND2_92(II2165,II2141,II2157);
nand NAND2_93(II2166,II2141,II2165);
nand NAND2_94(II2167,II2157,II2165);
nand NAND2_95(WX905,II2166,II2167);
nand NAND2_96(II2174,WX1001,WX657);
nand NAND2_97(II2175,WX1001,II2174);
nand NAND2_98(II2176,WX657,II2174);
nand NAND2_99(II2173,II2175,II2176);
nand NAND2_100(II2181,WX721,II2173);
nand NAND2_101(II2182,WX721,II2181);
nand NAND2_102(II2183,II2173,II2181);
nand NAND2_103(II2172,II2182,II2183);
nand NAND2_104(II2189,WX785,WX849);
nand NAND2_105(II2190,WX785,II2189);
nand NAND2_106(II2191,WX849,II2189);
nand NAND2_107(II2188,II2190,II2191);
nand NAND2_108(II2196,II2172,II2188);
nand NAND2_109(II2197,II2172,II2196);
nand NAND2_110(II2198,II2188,II2196);
nand NAND2_111(WX906,II2197,II2198);
nand NAND2_112(II2205,WX1001,WX659);
nand NAND2_113(II2206,WX1001,II2205);
nand NAND2_114(II2207,WX659,II2205);
nand NAND2_115(II2204,II2206,II2207);
nand NAND2_116(II2212,WX723,II2204);
nand NAND2_117(II2213,WX723,II2212);
nand NAND2_118(II2214,II2204,II2212);
nand NAND2_119(II2203,II2213,II2214);
nand NAND2_120(II2220,WX787,WX851);
nand NAND2_121(II2221,WX787,II2220);
nand NAND2_122(II2222,WX851,II2220);
nand NAND2_123(II2219,II2221,II2222);
nand NAND2_124(II2227,II2203,II2219);
nand NAND2_125(II2228,II2203,II2227);
nand NAND2_126(II2229,II2219,II2227);
nand NAND2_127(WX907,II2228,II2229);
nand NAND2_128(II2236,WX1001,WX661);
nand NAND2_129(II2237,WX1001,II2236);
nand NAND2_130(II2238,WX661,II2236);
nand NAND2_131(II2235,II2237,II2238);
nand NAND2_132(II2243,WX725,II2235);
nand NAND2_133(II2244,WX725,II2243);
nand NAND2_134(II2245,II2235,II2243);
nand NAND2_135(II2234,II2244,II2245);
nand NAND2_136(II2251,WX789,WX853);
nand NAND2_137(II2252,WX789,II2251);
nand NAND2_138(II2253,WX853,II2251);
nand NAND2_139(II2250,II2252,II2253);
nand NAND2_140(II2258,II2234,II2250);
nand NAND2_141(II2259,II2234,II2258);
nand NAND2_142(II2260,II2250,II2258);
nand NAND2_143(WX908,II2259,II2260);
nand NAND2_144(II2267,WX1001,WX663);
nand NAND2_145(II2268,WX1001,II2267);
nand NAND2_146(II2269,WX663,II2267);
nand NAND2_147(II2266,II2268,II2269);
nand NAND2_148(II2274,WX727,II2266);
nand NAND2_149(II2275,WX727,II2274);
nand NAND2_150(II2276,II2266,II2274);
nand NAND2_151(II2265,II2275,II2276);
nand NAND2_152(II2282,WX791,WX855);
nand NAND2_153(II2283,WX791,II2282);
nand NAND2_154(II2284,WX855,II2282);
nand NAND2_155(II2281,II2283,II2284);
nand NAND2_156(II2289,II2265,II2281);
nand NAND2_157(II2290,II2265,II2289);
nand NAND2_158(II2291,II2281,II2289);
nand NAND2_159(WX909,II2290,II2291);
nand NAND2_160(II2298,WX1001,WX665);
nand NAND2_161(II2299,WX1001,II2298);
nand NAND2_162(II2300,WX665,II2298);
nand NAND2_163(II2297,II2299,II2300);
nand NAND2_164(II2305,WX729,II2297);
nand NAND2_165(II2306,WX729,II2305);
nand NAND2_166(II2307,II2297,II2305);
nand NAND2_167(II2296,II2306,II2307);
nand NAND2_168(II2313,WX793,WX857);
nand NAND2_169(II2314,WX793,II2313);
nand NAND2_170(II2315,WX857,II2313);
nand NAND2_171(II2312,II2314,II2315);
nand NAND2_172(II2320,II2296,II2312);
nand NAND2_173(II2321,II2296,II2320);
nand NAND2_174(II2322,II2312,II2320);
nand NAND2_175(WX910,II2321,II2322);
nand NAND2_176(II2329,WX1001,WX667);
nand NAND2_177(II2330,WX1001,II2329);
nand NAND2_178(II2331,WX667,II2329);
nand NAND2_179(II2328,II2330,II2331);
nand NAND2_180(II2336,WX731,II2328);
nand NAND2_181(II2337,WX731,II2336);
nand NAND2_182(II2338,II2328,II2336);
nand NAND2_183(II2327,II2337,II2338);
nand NAND2_184(II2344,WX795,WX859);
nand NAND2_185(II2345,WX795,II2344);
nand NAND2_186(II2346,WX859,II2344);
nand NAND2_187(II2343,II2345,II2346);
nand NAND2_188(II2351,II2327,II2343);
nand NAND2_189(II2352,II2327,II2351);
nand NAND2_190(II2353,II2343,II2351);
nand NAND2_191(WX911,II2352,II2353);
nand NAND2_192(II2360,WX1001,WX669);
nand NAND2_193(II2361,WX1001,II2360);
nand NAND2_194(II2362,WX669,II2360);
nand NAND2_195(II2359,II2361,II2362);
nand NAND2_196(II2367,WX733,II2359);
nand NAND2_197(II2368,WX733,II2367);
nand NAND2_198(II2369,II2359,II2367);
nand NAND2_199(II2358,II2368,II2369);
nand NAND2_200(II2375,WX797,WX861);
nand NAND2_201(II2376,WX797,II2375);
nand NAND2_202(II2377,WX861,II2375);
nand NAND2_203(II2374,II2376,II2377);
nand NAND2_204(II2382,II2358,II2374);
nand NAND2_205(II2383,II2358,II2382);
nand NAND2_206(II2384,II2374,II2382);
nand NAND2_207(WX912,II2383,II2384);
nand NAND2_208(II2391,WX1001,WX671);
nand NAND2_209(II2392,WX1001,II2391);
nand NAND2_210(II2393,WX671,II2391);
nand NAND2_211(II2390,II2392,II2393);
nand NAND2_212(II2398,WX735,II2390);
nand NAND2_213(II2399,WX735,II2398);
nand NAND2_214(II2400,II2390,II2398);
nand NAND2_215(II2389,II2399,II2400);
nand NAND2_216(II2406,WX799,WX863);
nand NAND2_217(II2407,WX799,II2406);
nand NAND2_218(II2408,WX863,II2406);
nand NAND2_219(II2405,II2407,II2408);
nand NAND2_220(II2413,II2389,II2405);
nand NAND2_221(II2414,II2389,II2413);
nand NAND2_222(II2415,II2405,II2413);
nand NAND2_223(WX913,II2414,II2415);
nand NAND2_224(II2422,WX1001,WX673);
nand NAND2_225(II2423,WX1001,II2422);
nand NAND2_226(II2424,WX673,II2422);
nand NAND2_227(II2421,II2423,II2424);
nand NAND2_228(II2429,WX737,II2421);
nand NAND2_229(II2430,WX737,II2429);
nand NAND2_230(II2431,II2421,II2429);
nand NAND2_231(II2420,II2430,II2431);
nand NAND2_232(II2437,WX801,WX865);
nand NAND2_233(II2438,WX801,II2437);
nand NAND2_234(II2439,WX865,II2437);
nand NAND2_235(II2436,II2438,II2439);
nand NAND2_236(II2444,II2420,II2436);
nand NAND2_237(II2445,II2420,II2444);
nand NAND2_238(II2446,II2436,II2444);
nand NAND2_239(WX914,II2445,II2446);
nand NAND2_240(II2453,WX1001,WX675);
nand NAND2_241(II2454,WX1001,II2453);
nand NAND2_242(II2455,WX675,II2453);
nand NAND2_243(II2452,II2454,II2455);
nand NAND2_244(II2460,WX739,II2452);
nand NAND2_245(II2461,WX739,II2460);
nand NAND2_246(II2462,II2452,II2460);
nand NAND2_247(II2451,II2461,II2462);
nand NAND2_248(II2468,WX803,WX867);
nand NAND2_249(II2469,WX803,II2468);
nand NAND2_250(II2470,WX867,II2468);
nand NAND2_251(II2467,II2469,II2470);
nand NAND2_252(II2475,II2451,II2467);
nand NAND2_253(II2476,II2451,II2475);
nand NAND2_254(II2477,II2467,II2475);
nand NAND2_255(WX915,II2476,II2477);
nand NAND2_256(II2484,WX1002,WX677);
nand NAND2_257(II2485,WX1002,II2484);
nand NAND2_258(II2486,WX677,II2484);
nand NAND2_259(II2483,II2485,II2486);
nand NAND2_260(II2491,WX741,II2483);
nand NAND2_261(II2492,WX741,II2491);
nand NAND2_262(II2493,II2483,II2491);
nand NAND2_263(II2482,II2492,II2493);
nand NAND2_264(II2499,WX805,WX869);
nand NAND2_265(II2500,WX805,II2499);
nand NAND2_266(II2501,WX869,II2499);
nand NAND2_267(II2498,II2500,II2501);
nand NAND2_268(II2506,II2482,II2498);
nand NAND2_269(II2507,II2482,II2506);
nand NAND2_270(II2508,II2498,II2506);
nand NAND2_271(WX916,II2507,II2508);
nand NAND2_272(II2515,WX1002,WX679);
nand NAND2_273(II2516,WX1002,II2515);
nand NAND2_274(II2517,WX679,II2515);
nand NAND2_275(II2514,II2516,II2517);
nand NAND2_276(II2522,WX743,II2514);
nand NAND2_277(II2523,WX743,II2522);
nand NAND2_278(II2524,II2514,II2522);
nand NAND2_279(II2513,II2523,II2524);
nand NAND2_280(II2530,WX807,WX871);
nand NAND2_281(II2531,WX807,II2530);
nand NAND2_282(II2532,WX871,II2530);
nand NAND2_283(II2529,II2531,II2532);
nand NAND2_284(II2537,II2513,II2529);
nand NAND2_285(II2538,II2513,II2537);
nand NAND2_286(II2539,II2529,II2537);
nand NAND2_287(WX917,II2538,II2539);
nand NAND2_288(II2546,WX1002,WX681);
nand NAND2_289(II2547,WX1002,II2546);
nand NAND2_290(II2548,WX681,II2546);
nand NAND2_291(II2545,II2547,II2548);
nand NAND2_292(II2553,WX745,II2545);
nand NAND2_293(II2554,WX745,II2553);
nand NAND2_294(II2555,II2545,II2553);
nand NAND2_295(II2544,II2554,II2555);
nand NAND2_296(II2561,WX809,WX873);
nand NAND2_297(II2562,WX809,II2561);
nand NAND2_298(II2563,WX873,II2561);
nand NAND2_299(II2560,II2562,II2563);
nand NAND2_300(II2568,II2544,II2560);
nand NAND2_301(II2569,II2544,II2568);
nand NAND2_302(II2570,II2560,II2568);
nand NAND2_303(WX918,II2569,II2570);
nand NAND2_304(II2577,WX1002,WX683);
nand NAND2_305(II2578,WX1002,II2577);
nand NAND2_306(II2579,WX683,II2577);
nand NAND2_307(II2576,II2578,II2579);
nand NAND2_308(II2584,WX747,II2576);
nand NAND2_309(II2585,WX747,II2584);
nand NAND2_310(II2586,II2576,II2584);
nand NAND2_311(II2575,II2585,II2586);
nand NAND2_312(II2592,WX811,WX875);
nand NAND2_313(II2593,WX811,II2592);
nand NAND2_314(II2594,WX875,II2592);
nand NAND2_315(II2591,II2593,II2594);
nand NAND2_316(II2599,II2575,II2591);
nand NAND2_317(II2600,II2575,II2599);
nand NAND2_318(II2601,II2591,II2599);
nand NAND2_319(WX919,II2600,II2601);
nand NAND2_320(II2608,WX1002,WX685);
nand NAND2_321(II2609,WX1002,II2608);
nand NAND2_322(II2610,WX685,II2608);
nand NAND2_323(II2607,II2609,II2610);
nand NAND2_324(II2615,WX749,II2607);
nand NAND2_325(II2616,WX749,II2615);
nand NAND2_326(II2617,II2607,II2615);
nand NAND2_327(II2606,II2616,II2617);
nand NAND2_328(II2623,WX813,WX877);
nand NAND2_329(II2624,WX813,II2623);
nand NAND2_330(II2625,WX877,II2623);
nand NAND2_331(II2622,II2624,II2625);
nand NAND2_332(II2630,II2606,II2622);
nand NAND2_333(II2631,II2606,II2630);
nand NAND2_334(II2632,II2622,II2630);
nand NAND2_335(WX920,II2631,II2632);
nand NAND2_336(II2639,WX1002,WX687);
nand NAND2_337(II2640,WX1002,II2639);
nand NAND2_338(II2641,WX687,II2639);
nand NAND2_339(II2638,II2640,II2641);
nand NAND2_340(II2646,WX751,II2638);
nand NAND2_341(II2647,WX751,II2646);
nand NAND2_342(II2648,II2638,II2646);
nand NAND2_343(II2637,II2647,II2648);
nand NAND2_344(II2654,WX815,WX879);
nand NAND2_345(II2655,WX815,II2654);
nand NAND2_346(II2656,WX879,II2654);
nand NAND2_347(II2653,II2655,II2656);
nand NAND2_348(II2661,II2637,II2653);
nand NAND2_349(II2662,II2637,II2661);
nand NAND2_350(II2663,II2653,II2661);
nand NAND2_351(WX921,II2662,II2663);
nand NAND2_352(II2670,WX1002,WX689);
nand NAND2_353(II2671,WX1002,II2670);
nand NAND2_354(II2672,WX689,II2670);
nand NAND2_355(II2669,II2671,II2672);
nand NAND2_356(II2677,WX753,II2669);
nand NAND2_357(II2678,WX753,II2677);
nand NAND2_358(II2679,II2669,II2677);
nand NAND2_359(II2668,II2678,II2679);
nand NAND2_360(II2685,WX817,WX881);
nand NAND2_361(II2686,WX817,II2685);
nand NAND2_362(II2687,WX881,II2685);
nand NAND2_363(II2684,II2686,II2687);
nand NAND2_364(II2692,II2668,II2684);
nand NAND2_365(II2693,II2668,II2692);
nand NAND2_366(II2694,II2684,II2692);
nand NAND2_367(WX922,II2693,II2694);
nand NAND2_368(II2701,WX1002,WX691);
nand NAND2_369(II2702,WX1002,II2701);
nand NAND2_370(II2703,WX691,II2701);
nand NAND2_371(II2700,II2702,II2703);
nand NAND2_372(II2708,WX755,II2700);
nand NAND2_373(II2709,WX755,II2708);
nand NAND2_374(II2710,II2700,II2708);
nand NAND2_375(II2699,II2709,II2710);
nand NAND2_376(II2716,WX819,WX883);
nand NAND2_377(II2717,WX819,II2716);
nand NAND2_378(II2718,WX883,II2716);
nand NAND2_379(II2715,II2717,II2718);
nand NAND2_380(II2723,II2699,II2715);
nand NAND2_381(II2724,II2699,II2723);
nand NAND2_382(II2725,II2715,II2723);
nand NAND2_383(WX923,II2724,II2725);
nand NAND2_384(II2732,WX1002,WX693);
nand NAND2_385(II2733,WX1002,II2732);
nand NAND2_386(II2734,WX693,II2732);
nand NAND2_387(II2731,II2733,II2734);
nand NAND2_388(II2739,WX757,II2731);
nand NAND2_389(II2740,WX757,II2739);
nand NAND2_390(II2741,II2731,II2739);
nand NAND2_391(II2730,II2740,II2741);
nand NAND2_392(II2747,WX821,WX885);
nand NAND2_393(II2748,WX821,II2747);
nand NAND2_394(II2749,WX885,II2747);
nand NAND2_395(II2746,II2748,II2749);
nand NAND2_396(II2754,II2730,II2746);
nand NAND2_397(II2755,II2730,II2754);
nand NAND2_398(II2756,II2746,II2754);
nand NAND2_399(WX924,II2755,II2756);
nand NAND2_400(II2763,WX1002,WX695);
nand NAND2_401(II2764,WX1002,II2763);
nand NAND2_402(II2765,WX695,II2763);
nand NAND2_403(II2762,II2764,II2765);
nand NAND2_404(II2770,WX759,II2762);
nand NAND2_405(II2771,WX759,II2770);
nand NAND2_406(II2772,II2762,II2770);
nand NAND2_407(II2761,II2771,II2772);
nand NAND2_408(II2778,WX823,WX887);
nand NAND2_409(II2779,WX823,II2778);
nand NAND2_410(II2780,WX887,II2778);
nand NAND2_411(II2777,II2779,II2780);
nand NAND2_412(II2785,II2761,II2777);
nand NAND2_413(II2786,II2761,II2785);
nand NAND2_414(II2787,II2777,II2785);
nand NAND2_415(WX925,II2786,II2787);
nand NAND2_416(II2794,WX1002,WX697);
nand NAND2_417(II2795,WX1002,II2794);
nand NAND2_418(II2796,WX697,II2794);
nand NAND2_419(II2793,II2795,II2796);
nand NAND2_420(II2801,WX761,II2793);
nand NAND2_421(II2802,WX761,II2801);
nand NAND2_422(II2803,II2793,II2801);
nand NAND2_423(II2792,II2802,II2803);
nand NAND2_424(II2809,WX825,WX889);
nand NAND2_425(II2810,WX825,II2809);
nand NAND2_426(II2811,WX889,II2809);
nand NAND2_427(II2808,II2810,II2811);
nand NAND2_428(II2816,II2792,II2808);
nand NAND2_429(II2817,II2792,II2816);
nand NAND2_430(II2818,II2808,II2816);
nand NAND2_431(WX926,II2817,II2818);
nand NAND2_432(II2825,WX1002,WX699);
nand NAND2_433(II2826,WX1002,II2825);
nand NAND2_434(II2827,WX699,II2825);
nand NAND2_435(II2824,II2826,II2827);
nand NAND2_436(II2832,WX763,II2824);
nand NAND2_437(II2833,WX763,II2832);
nand NAND2_438(II2834,II2824,II2832);
nand NAND2_439(II2823,II2833,II2834);
nand NAND2_440(II2840,WX827,WX891);
nand NAND2_441(II2841,WX827,II2840);
nand NAND2_442(II2842,WX891,II2840);
nand NAND2_443(II2839,II2841,II2842);
nand NAND2_444(II2847,II2823,II2839);
nand NAND2_445(II2848,II2823,II2847);
nand NAND2_446(II2849,II2839,II2847);
nand NAND2_447(WX927,II2848,II2849);
nand NAND2_448(II2856,WX1002,WX701);
nand NAND2_449(II2857,WX1002,II2856);
nand NAND2_450(II2858,WX701,II2856);
nand NAND2_451(II2855,II2857,II2858);
nand NAND2_452(II2863,WX765,II2855);
nand NAND2_453(II2864,WX765,II2863);
nand NAND2_454(II2865,II2855,II2863);
nand NAND2_455(II2854,II2864,II2865);
nand NAND2_456(II2871,WX829,WX893);
nand NAND2_457(II2872,WX829,II2871);
nand NAND2_458(II2873,WX893,II2871);
nand NAND2_459(II2870,II2872,II2873);
nand NAND2_460(II2878,II2854,II2870);
nand NAND2_461(II2879,II2854,II2878);
nand NAND2_462(II2880,II2870,II2878);
nand NAND2_463(WX928,II2879,II2880);
nand NAND2_464(II2887,WX1002,WX703);
nand NAND2_465(II2888,WX1002,II2887);
nand NAND2_466(II2889,WX703,II2887);
nand NAND2_467(II2886,II2888,II2889);
nand NAND2_468(II2894,WX767,II2886);
nand NAND2_469(II2895,WX767,II2894);
nand NAND2_470(II2896,II2886,II2894);
nand NAND2_471(II2885,II2895,II2896);
nand NAND2_472(II2902,WX831,WX895);
nand NAND2_473(II2903,WX831,II2902);
nand NAND2_474(II2904,WX895,II2902);
nand NAND2_475(II2901,II2903,II2904);
nand NAND2_476(II2909,II2885,II2901);
nand NAND2_477(II2910,II2885,II2909);
nand NAND2_478(II2911,II2901,II2909);
nand NAND2_479(WX929,II2910,II2911);
nand NAND2_480(II2918,WX1002,WX705);
nand NAND2_481(II2919,WX1002,II2918);
nand NAND2_482(II2920,WX705,II2918);
nand NAND2_483(II2917,II2919,II2920);
nand NAND2_484(II2925,WX769,II2917);
nand NAND2_485(II2926,WX769,II2925);
nand NAND2_486(II2927,II2917,II2925);
nand NAND2_487(II2916,II2926,II2927);
nand NAND2_488(II2933,WX833,WX897);
nand NAND2_489(II2934,WX833,II2933);
nand NAND2_490(II2935,WX897,II2933);
nand NAND2_491(II2932,II2934,II2935);
nand NAND2_492(II2940,II2916,II2932);
nand NAND2_493(II2941,II2916,II2940);
nand NAND2_494(II2942,II2932,II2940);
nand NAND2_495(WX930,II2941,II2942);
nand NAND2_496(II2949,WX1002,WX707);
nand NAND2_497(II2950,WX1002,II2949);
nand NAND2_498(II2951,WX707,II2949);
nand NAND2_499(II2948,II2950,II2951);
nand NAND2_500(II2956,WX771,II2948);
nand NAND2_501(II2957,WX771,II2956);
nand NAND2_502(II2958,II2948,II2956);
nand NAND2_503(II2947,II2957,II2958);
nand NAND2_504(II2964,WX835,WX899);
nand NAND2_505(II2965,WX835,II2964);
nand NAND2_506(II2966,WX899,II2964);
nand NAND2_507(II2963,II2965,II2966);
nand NAND2_508(II2971,II2947,II2963);
nand NAND2_509(II2972,II2947,II2971);
nand NAND2_510(II2973,II2963,II2971);
nand NAND2_511(WX931,II2972,II2973);
nand NAND2_512(II3052,WX580,WX485);
nand NAND2_513(II3053,WX580,II3052);
nand NAND2_514(II3054,WX485,II3052);
nand NAND2_515(WX1006,II3053,II3054);
nand NAND2_516(II3065,WX581,WX487);
nand NAND2_517(II3066,WX581,II3065);
nand NAND2_518(II3067,WX487,II3065);
nand NAND2_519(WX1013,II3066,II3067);
nand NAND2_520(II3078,WX582,WX489);
nand NAND2_521(II3079,WX582,II3078);
nand NAND2_522(II3080,WX489,II3078);
nand NAND2_523(WX1020,II3079,II3080);
nand NAND2_524(II3091,WX583,WX491);
nand NAND2_525(II3092,WX583,II3091);
nand NAND2_526(II3093,WX491,II3091);
nand NAND2_527(WX1027,II3092,II3093);
nand NAND2_528(II3104,WX584,WX493);
nand NAND2_529(II3105,WX584,II3104);
nand NAND2_530(II3106,WX493,II3104);
nand NAND2_531(WX1034,II3105,II3106);
nand NAND2_532(II3117,WX585,WX495);
nand NAND2_533(II3118,WX585,II3117);
nand NAND2_534(II3119,WX495,II3117);
nand NAND2_535(WX1041,II3118,II3119);
nand NAND2_536(II3130,WX586,WX497);
nand NAND2_537(II3131,WX586,II3130);
nand NAND2_538(II3132,WX497,II3130);
nand NAND2_539(WX1048,II3131,II3132);
nand NAND2_540(II3143,WX587,WX499);
nand NAND2_541(II3144,WX587,II3143);
nand NAND2_542(II3145,WX499,II3143);
nand NAND2_543(WX1055,II3144,II3145);
nand NAND2_544(II3156,WX588,WX501);
nand NAND2_545(II3157,WX588,II3156);
nand NAND2_546(II3158,WX501,II3156);
nand NAND2_547(WX1062,II3157,II3158);
nand NAND2_548(II3169,WX589,WX503);
nand NAND2_549(II3170,WX589,II3169);
nand NAND2_550(II3171,WX503,II3169);
nand NAND2_551(WX1069,II3170,II3171);
nand NAND2_552(II3182,WX590,WX505);
nand NAND2_553(II3183,WX590,II3182);
nand NAND2_554(II3184,WX505,II3182);
nand NAND2_555(WX1076,II3183,II3184);
nand NAND2_556(II3195,WX591,WX507);
nand NAND2_557(II3196,WX591,II3195);
nand NAND2_558(II3197,WX507,II3195);
nand NAND2_559(WX1083,II3196,II3197);
nand NAND2_560(II3208,WX592,WX509);
nand NAND2_561(II3209,WX592,II3208);
nand NAND2_562(II3210,WX509,II3208);
nand NAND2_563(WX1090,II3209,II3210);
nand NAND2_564(II3221,WX593,WX511);
nand NAND2_565(II3222,WX593,II3221);
nand NAND2_566(II3223,WX511,II3221);
nand NAND2_567(WX1097,II3222,II3223);
nand NAND2_568(II3234,WX594,WX513);
nand NAND2_569(II3235,WX594,II3234);
nand NAND2_570(II3236,WX513,II3234);
nand NAND2_571(WX1104,II3235,II3236);
nand NAND2_572(II3247,WX595,WX515);
nand NAND2_573(II3248,WX595,II3247);
nand NAND2_574(II3249,WX515,II3247);
nand NAND2_575(WX1111,II3248,II3249);
nand NAND2_576(II3260,WX596,WX517);
nand NAND2_577(II3261,WX596,II3260);
nand NAND2_578(II3262,WX517,II3260);
nand NAND2_579(WX1118,II3261,II3262);
nand NAND2_580(II3273,WX597,WX519);
nand NAND2_581(II3274,WX597,II3273);
nand NAND2_582(II3275,WX519,II3273);
nand NAND2_583(WX1125,II3274,II3275);
nand NAND2_584(II3286,WX598,WX521);
nand NAND2_585(II3287,WX598,II3286);
nand NAND2_586(II3288,WX521,II3286);
nand NAND2_587(WX1132,II3287,II3288);
nand NAND2_588(II3299,WX599,WX523);
nand NAND2_589(II3300,WX599,II3299);
nand NAND2_590(II3301,WX523,II3299);
nand NAND2_591(WX1139,II3300,II3301);
nand NAND2_592(II3312,WX600,WX525);
nand NAND2_593(II3313,WX600,II3312);
nand NAND2_594(II3314,WX525,II3312);
nand NAND2_595(WX1146,II3313,II3314);
nand NAND2_596(II3325,WX601,WX527);
nand NAND2_597(II3326,WX601,II3325);
nand NAND2_598(II3327,WX527,II3325);
nand NAND2_599(WX1153,II3326,II3327);
nand NAND2_600(II3338,WX602,WX529);
nand NAND2_601(II3339,WX602,II3338);
nand NAND2_602(II3340,WX529,II3338);
nand NAND2_603(WX1160,II3339,II3340);
nand NAND2_604(II3351,WX603,WX531);
nand NAND2_605(II3352,WX603,II3351);
nand NAND2_606(II3353,WX531,II3351);
nand NAND2_607(WX1167,II3352,II3353);
nand NAND2_608(II3364,WX604,WX533);
nand NAND2_609(II3365,WX604,II3364);
nand NAND2_610(II3366,WX533,II3364);
nand NAND2_611(WX1174,II3365,II3366);
nand NAND2_612(II3377,WX605,WX535);
nand NAND2_613(II3378,WX605,II3377);
nand NAND2_614(II3379,WX535,II3377);
nand NAND2_615(WX1181,II3378,II3379);
nand NAND2_616(II3390,WX606,WX537);
nand NAND2_617(II3391,WX606,II3390);
nand NAND2_618(II3392,WX537,II3390);
nand NAND2_619(WX1188,II3391,II3392);
nand NAND2_620(II3403,WX607,WX539);
nand NAND2_621(II3404,WX607,II3403);
nand NAND2_622(II3405,WX539,II3403);
nand NAND2_623(WX1195,II3404,II3405);
nand NAND2_624(II3416,WX608,WX541);
nand NAND2_625(II3417,WX608,II3416);
nand NAND2_626(II3418,WX541,II3416);
nand NAND2_627(WX1202,II3417,II3418);
nand NAND2_628(II3429,WX609,WX543);
nand NAND2_629(II3430,WX609,II3429);
nand NAND2_630(II3431,WX543,II3429);
nand NAND2_631(WX1209,II3430,II3431);
nand NAND2_632(II3442,WX610,WX545);
nand NAND2_633(II3443,WX610,II3442);
nand NAND2_634(II3444,WX545,II3442);
nand NAND2_635(WX1216,II3443,II3444);
nand NAND2_636(II3455,WX611,WX547);
nand NAND2_637(II3456,WX611,II3455);
nand NAND2_638(II3457,WX547,II3455);
nand NAND2_639(WX1223,II3456,II3457);
nand NAND2_640(II3470,WX627,CRC_OUT_9_31);
nand NAND2_641(II3471,WX627,II3470);
nand NAND2_642(II3472,CRC_OUT_9_31,II3470);
nand NAND2_643(II3469,II3471,II3472);
nand NAND2_644(II3477,CRC_OUT_9_15,II3469);
nand NAND2_645(II3478,CRC_OUT_9_15,II3477);
nand NAND2_646(II3479,II3469,II3477);
nand NAND2_647(WX1231,II3478,II3479);
nand NAND2_648(II3485,WX632,CRC_OUT_9_31);
nand NAND2_649(II3486,WX632,II3485);
nand NAND2_650(II3487,CRC_OUT_9_31,II3485);
nand NAND2_651(II3484,II3486,II3487);
nand NAND2_652(II3492,CRC_OUT_9_10,II3484);
nand NAND2_653(II3493,CRC_OUT_9_10,II3492);
nand NAND2_654(II3494,II3484,II3492);
nand NAND2_655(WX1232,II3493,II3494);
nand NAND2_656(II3500,WX639,CRC_OUT_9_31);
nand NAND2_657(II3501,WX639,II3500);
nand NAND2_658(II3502,CRC_OUT_9_31,II3500);
nand NAND2_659(II3499,II3501,II3502);
nand NAND2_660(II3507,CRC_OUT_9_3,II3499);
nand NAND2_661(II3508,CRC_OUT_9_3,II3507);
nand NAND2_662(II3509,II3499,II3507);
nand NAND2_663(WX1233,II3508,II3509);
nand NAND2_664(II3514,WX643,CRC_OUT_9_31);
nand NAND2_665(II3515,WX643,II3514);
nand NAND2_666(II3516,CRC_OUT_9_31,II3514);
nand NAND2_667(WX1234,II3515,II3516);
nand NAND2_668(II3521,WX612,CRC_OUT_9_30);
nand NAND2_669(II3522,WX612,II3521);
nand NAND2_670(II3523,CRC_OUT_9_30,II3521);
nand NAND2_671(WX1235,II3522,II3523);
nand NAND2_672(II3528,WX613,CRC_OUT_9_29);
nand NAND2_673(II3529,WX613,II3528);
nand NAND2_674(II3530,CRC_OUT_9_29,II3528);
nand NAND2_675(WX1236,II3529,II3530);
nand NAND2_676(II3535,WX614,CRC_OUT_9_28);
nand NAND2_677(II3536,WX614,II3535);
nand NAND2_678(II3537,CRC_OUT_9_28,II3535);
nand NAND2_679(WX1237,II3536,II3537);
nand NAND2_680(II3542,WX615,CRC_OUT_9_27);
nand NAND2_681(II3543,WX615,II3542);
nand NAND2_682(II3544,CRC_OUT_9_27,II3542);
nand NAND2_683(WX1238,II3543,II3544);
nand NAND2_684(II3549,WX616,CRC_OUT_9_26);
nand NAND2_685(II3550,WX616,II3549);
nand NAND2_686(II3551,CRC_OUT_9_26,II3549);
nand NAND2_687(WX1239,II3550,II3551);
nand NAND2_688(II3556,WX617,CRC_OUT_9_25);
nand NAND2_689(II3557,WX617,II3556);
nand NAND2_690(II3558,CRC_OUT_9_25,II3556);
nand NAND2_691(WX1240,II3557,II3558);
nand NAND2_692(II3563,WX618,CRC_OUT_9_24);
nand NAND2_693(II3564,WX618,II3563);
nand NAND2_694(II3565,CRC_OUT_9_24,II3563);
nand NAND2_695(WX1241,II3564,II3565);
nand NAND2_696(II3570,WX619,CRC_OUT_9_23);
nand NAND2_697(II3571,WX619,II3570);
nand NAND2_698(II3572,CRC_OUT_9_23,II3570);
nand NAND2_699(WX1242,II3571,II3572);
nand NAND2_700(II3577,WX620,CRC_OUT_9_22);
nand NAND2_701(II3578,WX620,II3577);
nand NAND2_702(II3579,CRC_OUT_9_22,II3577);
nand NAND2_703(WX1243,II3578,II3579);
nand NAND2_704(II3584,WX621,CRC_OUT_9_21);
nand NAND2_705(II3585,WX621,II3584);
nand NAND2_706(II3586,CRC_OUT_9_21,II3584);
nand NAND2_707(WX1244,II3585,II3586);
nand NAND2_708(II3591,WX622,CRC_OUT_9_20);
nand NAND2_709(II3592,WX622,II3591);
nand NAND2_710(II3593,CRC_OUT_9_20,II3591);
nand NAND2_711(WX1245,II3592,II3593);
nand NAND2_712(II3598,WX623,CRC_OUT_9_19);
nand NAND2_713(II3599,WX623,II3598);
nand NAND2_714(II3600,CRC_OUT_9_19,II3598);
nand NAND2_715(WX1246,II3599,II3600);
nand NAND2_716(II3605,WX624,CRC_OUT_9_18);
nand NAND2_717(II3606,WX624,II3605);
nand NAND2_718(II3607,CRC_OUT_9_18,II3605);
nand NAND2_719(WX1247,II3606,II3607);
nand NAND2_720(II3612,WX625,CRC_OUT_9_17);
nand NAND2_721(II3613,WX625,II3612);
nand NAND2_722(II3614,CRC_OUT_9_17,II3612);
nand NAND2_723(WX1248,II3613,II3614);
nand NAND2_724(II3619,WX626,CRC_OUT_9_16);
nand NAND2_725(II3620,WX626,II3619);
nand NAND2_726(II3621,CRC_OUT_9_16,II3619);
nand NAND2_727(WX1249,II3620,II3621);
nand NAND2_728(II3626,WX628,CRC_OUT_9_14);
nand NAND2_729(II3627,WX628,II3626);
nand NAND2_730(II3628,CRC_OUT_9_14,II3626);
nand NAND2_731(WX1250,II3627,II3628);
nand NAND2_732(II3633,WX629,CRC_OUT_9_13);
nand NAND2_733(II3634,WX629,II3633);
nand NAND2_734(II3635,CRC_OUT_9_13,II3633);
nand NAND2_735(WX1251,II3634,II3635);
nand NAND2_736(II3640,WX630,CRC_OUT_9_12);
nand NAND2_737(II3641,WX630,II3640);
nand NAND2_738(II3642,CRC_OUT_9_12,II3640);
nand NAND2_739(WX1252,II3641,II3642);
nand NAND2_740(II3647,WX631,CRC_OUT_9_11);
nand NAND2_741(II3648,WX631,II3647);
nand NAND2_742(II3649,CRC_OUT_9_11,II3647);
nand NAND2_743(WX1253,II3648,II3649);
nand NAND2_744(II3654,WX633,CRC_OUT_9_9);
nand NAND2_745(II3655,WX633,II3654);
nand NAND2_746(II3656,CRC_OUT_9_9,II3654);
nand NAND2_747(WX1254,II3655,II3656);
nand NAND2_748(II3661,WX634,CRC_OUT_9_8);
nand NAND2_749(II3662,WX634,II3661);
nand NAND2_750(II3663,CRC_OUT_9_8,II3661);
nand NAND2_751(WX1255,II3662,II3663);
nand NAND2_752(II3668,WX635,CRC_OUT_9_7);
nand NAND2_753(II3669,WX635,II3668);
nand NAND2_754(II3670,CRC_OUT_9_7,II3668);
nand NAND2_755(WX1256,II3669,II3670);
nand NAND2_756(II3675,WX636,CRC_OUT_9_6);
nand NAND2_757(II3676,WX636,II3675);
nand NAND2_758(II3677,CRC_OUT_9_6,II3675);
nand NAND2_759(WX1257,II3676,II3677);
nand NAND2_760(II3682,WX637,CRC_OUT_9_5);
nand NAND2_761(II3683,WX637,II3682);
nand NAND2_762(II3684,CRC_OUT_9_5,II3682);
nand NAND2_763(WX1258,II3683,II3684);
nand NAND2_764(II3689,WX638,CRC_OUT_9_4);
nand NAND2_765(II3690,WX638,II3689);
nand NAND2_766(II3691,CRC_OUT_9_4,II3689);
nand NAND2_767(WX1259,II3690,II3691);
nand NAND2_768(II3696,WX640,CRC_OUT_9_2);
nand NAND2_769(II3697,WX640,II3696);
nand NAND2_770(II3698,CRC_OUT_9_2,II3696);
nand NAND2_771(WX1260,II3697,II3698);
nand NAND2_772(II3703,WX641,CRC_OUT_9_1);
nand NAND2_773(II3704,WX641,II3703);
nand NAND2_774(II3705,CRC_OUT_9_1,II3703);
nand NAND2_775(WX1261,II3704,II3705);
nand NAND2_776(II3710,WX642,CRC_OUT_9_0);
nand NAND2_777(II3711,WX642,II3710);
nand NAND2_778(II3712,CRC_OUT_9_0,II3710);
nand NAND2_779(WX1262,II3711,II3712);
nand NAND2_780(II5993,WX2294,WX1938);
nand NAND2_781(II5994,WX2294,II5993);
nand NAND2_782(II5995,WX1938,II5993);
nand NAND2_783(II5992,II5994,II5995);
nand NAND2_784(II6000,WX2002,II5992);
nand NAND2_785(II6001,WX2002,II6000);
nand NAND2_786(II6002,II5992,II6000);
nand NAND2_787(II5991,II6001,II6002);
nand NAND2_788(II6008,WX2066,WX2130);
nand NAND2_789(II6009,WX2066,II6008);
nand NAND2_790(II6010,WX2130,II6008);
nand NAND2_791(II6007,II6009,II6010);
nand NAND2_792(II6015,II5991,II6007);
nand NAND2_793(II6016,II5991,II6015);
nand NAND2_794(II6017,II6007,II6015);
nand NAND2_795(WX2193,II6016,II6017);
nand NAND2_796(II6024,WX2294,WX1940);
nand NAND2_797(II6025,WX2294,II6024);
nand NAND2_798(II6026,WX1940,II6024);
nand NAND2_799(II6023,II6025,II6026);
nand NAND2_800(II6031,WX2004,II6023);
nand NAND2_801(II6032,WX2004,II6031);
nand NAND2_802(II6033,II6023,II6031);
nand NAND2_803(II6022,II6032,II6033);
nand NAND2_804(II6039,WX2068,WX2132);
nand NAND2_805(II6040,WX2068,II6039);
nand NAND2_806(II6041,WX2132,II6039);
nand NAND2_807(II6038,II6040,II6041);
nand NAND2_808(II6046,II6022,II6038);
nand NAND2_809(II6047,II6022,II6046);
nand NAND2_810(II6048,II6038,II6046);
nand NAND2_811(WX2194,II6047,II6048);
nand NAND2_812(II6055,WX2294,WX1942);
nand NAND2_813(II6056,WX2294,II6055);
nand NAND2_814(II6057,WX1942,II6055);
nand NAND2_815(II6054,II6056,II6057);
nand NAND2_816(II6062,WX2006,II6054);
nand NAND2_817(II6063,WX2006,II6062);
nand NAND2_818(II6064,II6054,II6062);
nand NAND2_819(II6053,II6063,II6064);
nand NAND2_820(II6070,WX2070,WX2134);
nand NAND2_821(II6071,WX2070,II6070);
nand NAND2_822(II6072,WX2134,II6070);
nand NAND2_823(II6069,II6071,II6072);
nand NAND2_824(II6077,II6053,II6069);
nand NAND2_825(II6078,II6053,II6077);
nand NAND2_826(II6079,II6069,II6077);
nand NAND2_827(WX2195,II6078,II6079);
nand NAND2_828(II6086,WX2294,WX1944);
nand NAND2_829(II6087,WX2294,II6086);
nand NAND2_830(II6088,WX1944,II6086);
nand NAND2_831(II6085,II6087,II6088);
nand NAND2_832(II6093,WX2008,II6085);
nand NAND2_833(II6094,WX2008,II6093);
nand NAND2_834(II6095,II6085,II6093);
nand NAND2_835(II6084,II6094,II6095);
nand NAND2_836(II6101,WX2072,WX2136);
nand NAND2_837(II6102,WX2072,II6101);
nand NAND2_838(II6103,WX2136,II6101);
nand NAND2_839(II6100,II6102,II6103);
nand NAND2_840(II6108,II6084,II6100);
nand NAND2_841(II6109,II6084,II6108);
nand NAND2_842(II6110,II6100,II6108);
nand NAND2_843(WX2196,II6109,II6110);
nand NAND2_844(II6117,WX2294,WX1946);
nand NAND2_845(II6118,WX2294,II6117);
nand NAND2_846(II6119,WX1946,II6117);
nand NAND2_847(II6116,II6118,II6119);
nand NAND2_848(II6124,WX2010,II6116);
nand NAND2_849(II6125,WX2010,II6124);
nand NAND2_850(II6126,II6116,II6124);
nand NAND2_851(II6115,II6125,II6126);
nand NAND2_852(II6132,WX2074,WX2138);
nand NAND2_853(II6133,WX2074,II6132);
nand NAND2_854(II6134,WX2138,II6132);
nand NAND2_855(II6131,II6133,II6134);
nand NAND2_856(II6139,II6115,II6131);
nand NAND2_857(II6140,II6115,II6139);
nand NAND2_858(II6141,II6131,II6139);
nand NAND2_859(WX2197,II6140,II6141);
nand NAND2_860(II6148,WX2294,WX1948);
nand NAND2_861(II6149,WX2294,II6148);
nand NAND2_862(II6150,WX1948,II6148);
nand NAND2_863(II6147,II6149,II6150);
nand NAND2_864(II6155,WX2012,II6147);
nand NAND2_865(II6156,WX2012,II6155);
nand NAND2_866(II6157,II6147,II6155);
nand NAND2_867(II6146,II6156,II6157);
nand NAND2_868(II6163,WX2076,WX2140);
nand NAND2_869(II6164,WX2076,II6163);
nand NAND2_870(II6165,WX2140,II6163);
nand NAND2_871(II6162,II6164,II6165);
nand NAND2_872(II6170,II6146,II6162);
nand NAND2_873(II6171,II6146,II6170);
nand NAND2_874(II6172,II6162,II6170);
nand NAND2_875(WX2198,II6171,II6172);
nand NAND2_876(II6179,WX2294,WX1950);
nand NAND2_877(II6180,WX2294,II6179);
nand NAND2_878(II6181,WX1950,II6179);
nand NAND2_879(II6178,II6180,II6181);
nand NAND2_880(II6186,WX2014,II6178);
nand NAND2_881(II6187,WX2014,II6186);
nand NAND2_882(II6188,II6178,II6186);
nand NAND2_883(II6177,II6187,II6188);
nand NAND2_884(II6194,WX2078,WX2142);
nand NAND2_885(II6195,WX2078,II6194);
nand NAND2_886(II6196,WX2142,II6194);
nand NAND2_887(II6193,II6195,II6196);
nand NAND2_888(II6201,II6177,II6193);
nand NAND2_889(II6202,II6177,II6201);
nand NAND2_890(II6203,II6193,II6201);
nand NAND2_891(WX2199,II6202,II6203);
nand NAND2_892(II6210,WX2294,WX1952);
nand NAND2_893(II6211,WX2294,II6210);
nand NAND2_894(II6212,WX1952,II6210);
nand NAND2_895(II6209,II6211,II6212);
nand NAND2_896(II6217,WX2016,II6209);
nand NAND2_897(II6218,WX2016,II6217);
nand NAND2_898(II6219,II6209,II6217);
nand NAND2_899(II6208,II6218,II6219);
nand NAND2_900(II6225,WX2080,WX2144);
nand NAND2_901(II6226,WX2080,II6225);
nand NAND2_902(II6227,WX2144,II6225);
nand NAND2_903(II6224,II6226,II6227);
nand NAND2_904(II6232,II6208,II6224);
nand NAND2_905(II6233,II6208,II6232);
nand NAND2_906(II6234,II6224,II6232);
nand NAND2_907(WX2200,II6233,II6234);
nand NAND2_908(II6241,WX2294,WX1954);
nand NAND2_909(II6242,WX2294,II6241);
nand NAND2_910(II6243,WX1954,II6241);
nand NAND2_911(II6240,II6242,II6243);
nand NAND2_912(II6248,WX2018,II6240);
nand NAND2_913(II6249,WX2018,II6248);
nand NAND2_914(II6250,II6240,II6248);
nand NAND2_915(II6239,II6249,II6250);
nand NAND2_916(II6256,WX2082,WX2146);
nand NAND2_917(II6257,WX2082,II6256);
nand NAND2_918(II6258,WX2146,II6256);
nand NAND2_919(II6255,II6257,II6258);
nand NAND2_920(II6263,II6239,II6255);
nand NAND2_921(II6264,II6239,II6263);
nand NAND2_922(II6265,II6255,II6263);
nand NAND2_923(WX2201,II6264,II6265);
nand NAND2_924(II6272,WX2294,WX1956);
nand NAND2_925(II6273,WX2294,II6272);
nand NAND2_926(II6274,WX1956,II6272);
nand NAND2_927(II6271,II6273,II6274);
nand NAND2_928(II6279,WX2020,II6271);
nand NAND2_929(II6280,WX2020,II6279);
nand NAND2_930(II6281,II6271,II6279);
nand NAND2_931(II6270,II6280,II6281);
nand NAND2_932(II6287,WX2084,WX2148);
nand NAND2_933(II6288,WX2084,II6287);
nand NAND2_934(II6289,WX2148,II6287);
nand NAND2_935(II6286,II6288,II6289);
nand NAND2_936(II6294,II6270,II6286);
nand NAND2_937(II6295,II6270,II6294);
nand NAND2_938(II6296,II6286,II6294);
nand NAND2_939(WX2202,II6295,II6296);
nand NAND2_940(II6303,WX2294,WX1958);
nand NAND2_941(II6304,WX2294,II6303);
nand NAND2_942(II6305,WX1958,II6303);
nand NAND2_943(II6302,II6304,II6305);
nand NAND2_944(II6310,WX2022,II6302);
nand NAND2_945(II6311,WX2022,II6310);
nand NAND2_946(II6312,II6302,II6310);
nand NAND2_947(II6301,II6311,II6312);
nand NAND2_948(II6318,WX2086,WX2150);
nand NAND2_949(II6319,WX2086,II6318);
nand NAND2_950(II6320,WX2150,II6318);
nand NAND2_951(II6317,II6319,II6320);
nand NAND2_952(II6325,II6301,II6317);
nand NAND2_953(II6326,II6301,II6325);
nand NAND2_954(II6327,II6317,II6325);
nand NAND2_955(WX2203,II6326,II6327);
nand NAND2_956(II6334,WX2294,WX1960);
nand NAND2_957(II6335,WX2294,II6334);
nand NAND2_958(II6336,WX1960,II6334);
nand NAND2_959(II6333,II6335,II6336);
nand NAND2_960(II6341,WX2024,II6333);
nand NAND2_961(II6342,WX2024,II6341);
nand NAND2_962(II6343,II6333,II6341);
nand NAND2_963(II6332,II6342,II6343);
nand NAND2_964(II6349,WX2088,WX2152);
nand NAND2_965(II6350,WX2088,II6349);
nand NAND2_966(II6351,WX2152,II6349);
nand NAND2_967(II6348,II6350,II6351);
nand NAND2_968(II6356,II6332,II6348);
nand NAND2_969(II6357,II6332,II6356);
nand NAND2_970(II6358,II6348,II6356);
nand NAND2_971(WX2204,II6357,II6358);
nand NAND2_972(II6365,WX2294,WX1962);
nand NAND2_973(II6366,WX2294,II6365);
nand NAND2_974(II6367,WX1962,II6365);
nand NAND2_975(II6364,II6366,II6367);
nand NAND2_976(II6372,WX2026,II6364);
nand NAND2_977(II6373,WX2026,II6372);
nand NAND2_978(II6374,II6364,II6372);
nand NAND2_979(II6363,II6373,II6374);
nand NAND2_980(II6380,WX2090,WX2154);
nand NAND2_981(II6381,WX2090,II6380);
nand NAND2_982(II6382,WX2154,II6380);
nand NAND2_983(II6379,II6381,II6382);
nand NAND2_984(II6387,II6363,II6379);
nand NAND2_985(II6388,II6363,II6387);
nand NAND2_986(II6389,II6379,II6387);
nand NAND2_987(WX2205,II6388,II6389);
nand NAND2_988(II6396,WX2294,WX1964);
nand NAND2_989(II6397,WX2294,II6396);
nand NAND2_990(II6398,WX1964,II6396);
nand NAND2_991(II6395,II6397,II6398);
nand NAND2_992(II6403,WX2028,II6395);
nand NAND2_993(II6404,WX2028,II6403);
nand NAND2_994(II6405,II6395,II6403);
nand NAND2_995(II6394,II6404,II6405);
nand NAND2_996(II6411,WX2092,WX2156);
nand NAND2_997(II6412,WX2092,II6411);
nand NAND2_998(II6413,WX2156,II6411);
nand NAND2_999(II6410,II6412,II6413);
nand NAND2_1000(II6418,II6394,II6410);
nand NAND2_1001(II6419,II6394,II6418);
nand NAND2_1002(II6420,II6410,II6418);
nand NAND2_1003(WX2206,II6419,II6420);
nand NAND2_1004(II6427,WX2294,WX1966);
nand NAND2_1005(II6428,WX2294,II6427);
nand NAND2_1006(II6429,WX1966,II6427);
nand NAND2_1007(II6426,II6428,II6429);
nand NAND2_1008(II6434,WX2030,II6426);
nand NAND2_1009(II6435,WX2030,II6434);
nand NAND2_1010(II6436,II6426,II6434);
nand NAND2_1011(II6425,II6435,II6436);
nand NAND2_1012(II6442,WX2094,WX2158);
nand NAND2_1013(II6443,WX2094,II6442);
nand NAND2_1014(II6444,WX2158,II6442);
nand NAND2_1015(II6441,II6443,II6444);
nand NAND2_1016(II6449,II6425,II6441);
nand NAND2_1017(II6450,II6425,II6449);
nand NAND2_1018(II6451,II6441,II6449);
nand NAND2_1019(WX2207,II6450,II6451);
nand NAND2_1020(II6458,WX2294,WX1968);
nand NAND2_1021(II6459,WX2294,II6458);
nand NAND2_1022(II6460,WX1968,II6458);
nand NAND2_1023(II6457,II6459,II6460);
nand NAND2_1024(II6465,WX2032,II6457);
nand NAND2_1025(II6466,WX2032,II6465);
nand NAND2_1026(II6467,II6457,II6465);
nand NAND2_1027(II6456,II6466,II6467);
nand NAND2_1028(II6473,WX2096,WX2160);
nand NAND2_1029(II6474,WX2096,II6473);
nand NAND2_1030(II6475,WX2160,II6473);
nand NAND2_1031(II6472,II6474,II6475);
nand NAND2_1032(II6480,II6456,II6472);
nand NAND2_1033(II6481,II6456,II6480);
nand NAND2_1034(II6482,II6472,II6480);
nand NAND2_1035(WX2208,II6481,II6482);
nand NAND2_1036(II6489,WX2295,WX1970);
nand NAND2_1037(II6490,WX2295,II6489);
nand NAND2_1038(II6491,WX1970,II6489);
nand NAND2_1039(II6488,II6490,II6491);
nand NAND2_1040(II6496,WX2034,II6488);
nand NAND2_1041(II6497,WX2034,II6496);
nand NAND2_1042(II6498,II6488,II6496);
nand NAND2_1043(II6487,II6497,II6498);
nand NAND2_1044(II6504,WX2098,WX2162);
nand NAND2_1045(II6505,WX2098,II6504);
nand NAND2_1046(II6506,WX2162,II6504);
nand NAND2_1047(II6503,II6505,II6506);
nand NAND2_1048(II6511,II6487,II6503);
nand NAND2_1049(II6512,II6487,II6511);
nand NAND2_1050(II6513,II6503,II6511);
nand NAND2_1051(WX2209,II6512,II6513);
nand NAND2_1052(II6520,WX2295,WX1972);
nand NAND2_1053(II6521,WX2295,II6520);
nand NAND2_1054(II6522,WX1972,II6520);
nand NAND2_1055(II6519,II6521,II6522);
nand NAND2_1056(II6527,WX2036,II6519);
nand NAND2_1057(II6528,WX2036,II6527);
nand NAND2_1058(II6529,II6519,II6527);
nand NAND2_1059(II6518,II6528,II6529);
nand NAND2_1060(II6535,WX2100,WX2164);
nand NAND2_1061(II6536,WX2100,II6535);
nand NAND2_1062(II6537,WX2164,II6535);
nand NAND2_1063(II6534,II6536,II6537);
nand NAND2_1064(II6542,II6518,II6534);
nand NAND2_1065(II6543,II6518,II6542);
nand NAND2_1066(II6544,II6534,II6542);
nand NAND2_1067(WX2210,II6543,II6544);
nand NAND2_1068(II6551,WX2295,WX1974);
nand NAND2_1069(II6552,WX2295,II6551);
nand NAND2_1070(II6553,WX1974,II6551);
nand NAND2_1071(II6550,II6552,II6553);
nand NAND2_1072(II6558,WX2038,II6550);
nand NAND2_1073(II6559,WX2038,II6558);
nand NAND2_1074(II6560,II6550,II6558);
nand NAND2_1075(II6549,II6559,II6560);
nand NAND2_1076(II6566,WX2102,WX2166);
nand NAND2_1077(II6567,WX2102,II6566);
nand NAND2_1078(II6568,WX2166,II6566);
nand NAND2_1079(II6565,II6567,II6568);
nand NAND2_1080(II6573,II6549,II6565);
nand NAND2_1081(II6574,II6549,II6573);
nand NAND2_1082(II6575,II6565,II6573);
nand NAND2_1083(WX2211,II6574,II6575);
nand NAND2_1084(II6582,WX2295,WX1976);
nand NAND2_1085(II6583,WX2295,II6582);
nand NAND2_1086(II6584,WX1976,II6582);
nand NAND2_1087(II6581,II6583,II6584);
nand NAND2_1088(II6589,WX2040,II6581);
nand NAND2_1089(II6590,WX2040,II6589);
nand NAND2_1090(II6591,II6581,II6589);
nand NAND2_1091(II6580,II6590,II6591);
nand NAND2_1092(II6597,WX2104,WX2168);
nand NAND2_1093(II6598,WX2104,II6597);
nand NAND2_1094(II6599,WX2168,II6597);
nand NAND2_1095(II6596,II6598,II6599);
nand NAND2_1096(II6604,II6580,II6596);
nand NAND2_1097(II6605,II6580,II6604);
nand NAND2_1098(II6606,II6596,II6604);
nand NAND2_1099(WX2212,II6605,II6606);
nand NAND2_1100(II6613,WX2295,WX1978);
nand NAND2_1101(II6614,WX2295,II6613);
nand NAND2_1102(II6615,WX1978,II6613);
nand NAND2_1103(II6612,II6614,II6615);
nand NAND2_1104(II6620,WX2042,II6612);
nand NAND2_1105(II6621,WX2042,II6620);
nand NAND2_1106(II6622,II6612,II6620);
nand NAND2_1107(II6611,II6621,II6622);
nand NAND2_1108(II6628,WX2106,WX2170);
nand NAND2_1109(II6629,WX2106,II6628);
nand NAND2_1110(II6630,WX2170,II6628);
nand NAND2_1111(II6627,II6629,II6630);
nand NAND2_1112(II6635,II6611,II6627);
nand NAND2_1113(II6636,II6611,II6635);
nand NAND2_1114(II6637,II6627,II6635);
nand NAND2_1115(WX2213,II6636,II6637);
nand NAND2_1116(II6644,WX2295,WX1980);
nand NAND2_1117(II6645,WX2295,II6644);
nand NAND2_1118(II6646,WX1980,II6644);
nand NAND2_1119(II6643,II6645,II6646);
nand NAND2_1120(II6651,WX2044,II6643);
nand NAND2_1121(II6652,WX2044,II6651);
nand NAND2_1122(II6653,II6643,II6651);
nand NAND2_1123(II6642,II6652,II6653);
nand NAND2_1124(II6659,WX2108,WX2172);
nand NAND2_1125(II6660,WX2108,II6659);
nand NAND2_1126(II6661,WX2172,II6659);
nand NAND2_1127(II6658,II6660,II6661);
nand NAND2_1128(II6666,II6642,II6658);
nand NAND2_1129(II6667,II6642,II6666);
nand NAND2_1130(II6668,II6658,II6666);
nand NAND2_1131(WX2214,II6667,II6668);
nand NAND2_1132(II6675,WX2295,WX1982);
nand NAND2_1133(II6676,WX2295,II6675);
nand NAND2_1134(II6677,WX1982,II6675);
nand NAND2_1135(II6674,II6676,II6677);
nand NAND2_1136(II6682,WX2046,II6674);
nand NAND2_1137(II6683,WX2046,II6682);
nand NAND2_1138(II6684,II6674,II6682);
nand NAND2_1139(II6673,II6683,II6684);
nand NAND2_1140(II6690,WX2110,WX2174);
nand NAND2_1141(II6691,WX2110,II6690);
nand NAND2_1142(II6692,WX2174,II6690);
nand NAND2_1143(II6689,II6691,II6692);
nand NAND2_1144(II6697,II6673,II6689);
nand NAND2_1145(II6698,II6673,II6697);
nand NAND2_1146(II6699,II6689,II6697);
nand NAND2_1147(WX2215,II6698,II6699);
nand NAND2_1148(II6706,WX2295,WX1984);
nand NAND2_1149(II6707,WX2295,II6706);
nand NAND2_1150(II6708,WX1984,II6706);
nand NAND2_1151(II6705,II6707,II6708);
nand NAND2_1152(II6713,WX2048,II6705);
nand NAND2_1153(II6714,WX2048,II6713);
nand NAND2_1154(II6715,II6705,II6713);
nand NAND2_1155(II6704,II6714,II6715);
nand NAND2_1156(II6721,WX2112,WX2176);
nand NAND2_1157(II6722,WX2112,II6721);
nand NAND2_1158(II6723,WX2176,II6721);
nand NAND2_1159(II6720,II6722,II6723);
nand NAND2_1160(II6728,II6704,II6720);
nand NAND2_1161(II6729,II6704,II6728);
nand NAND2_1162(II6730,II6720,II6728);
nand NAND2_1163(WX2216,II6729,II6730);
nand NAND2_1164(II6737,WX2295,WX1986);
nand NAND2_1165(II6738,WX2295,II6737);
nand NAND2_1166(II6739,WX1986,II6737);
nand NAND2_1167(II6736,II6738,II6739);
nand NAND2_1168(II6744,WX2050,II6736);
nand NAND2_1169(II6745,WX2050,II6744);
nand NAND2_1170(II6746,II6736,II6744);
nand NAND2_1171(II6735,II6745,II6746);
nand NAND2_1172(II6752,WX2114,WX2178);
nand NAND2_1173(II6753,WX2114,II6752);
nand NAND2_1174(II6754,WX2178,II6752);
nand NAND2_1175(II6751,II6753,II6754);
nand NAND2_1176(II6759,II6735,II6751);
nand NAND2_1177(II6760,II6735,II6759);
nand NAND2_1178(II6761,II6751,II6759);
nand NAND2_1179(WX2217,II6760,II6761);
nand NAND2_1180(II6768,WX2295,WX1988);
nand NAND2_1181(II6769,WX2295,II6768);
nand NAND2_1182(II6770,WX1988,II6768);
nand NAND2_1183(II6767,II6769,II6770);
nand NAND2_1184(II6775,WX2052,II6767);
nand NAND2_1185(II6776,WX2052,II6775);
nand NAND2_1186(II6777,II6767,II6775);
nand NAND2_1187(II6766,II6776,II6777);
nand NAND2_1188(II6783,WX2116,WX2180);
nand NAND2_1189(II6784,WX2116,II6783);
nand NAND2_1190(II6785,WX2180,II6783);
nand NAND2_1191(II6782,II6784,II6785);
nand NAND2_1192(II6790,II6766,II6782);
nand NAND2_1193(II6791,II6766,II6790);
nand NAND2_1194(II6792,II6782,II6790);
nand NAND2_1195(WX2218,II6791,II6792);
nand NAND2_1196(II6799,WX2295,WX1990);
nand NAND2_1197(II6800,WX2295,II6799);
nand NAND2_1198(II6801,WX1990,II6799);
nand NAND2_1199(II6798,II6800,II6801);
nand NAND2_1200(II6806,WX2054,II6798);
nand NAND2_1201(II6807,WX2054,II6806);
nand NAND2_1202(II6808,II6798,II6806);
nand NAND2_1203(II6797,II6807,II6808);
nand NAND2_1204(II6814,WX2118,WX2182);
nand NAND2_1205(II6815,WX2118,II6814);
nand NAND2_1206(II6816,WX2182,II6814);
nand NAND2_1207(II6813,II6815,II6816);
nand NAND2_1208(II6821,II6797,II6813);
nand NAND2_1209(II6822,II6797,II6821);
nand NAND2_1210(II6823,II6813,II6821);
nand NAND2_1211(WX2219,II6822,II6823);
nand NAND2_1212(II6830,WX2295,WX1992);
nand NAND2_1213(II6831,WX2295,II6830);
nand NAND2_1214(II6832,WX1992,II6830);
nand NAND2_1215(II6829,II6831,II6832);
nand NAND2_1216(II6837,WX2056,II6829);
nand NAND2_1217(II6838,WX2056,II6837);
nand NAND2_1218(II6839,II6829,II6837);
nand NAND2_1219(II6828,II6838,II6839);
nand NAND2_1220(II6845,WX2120,WX2184);
nand NAND2_1221(II6846,WX2120,II6845);
nand NAND2_1222(II6847,WX2184,II6845);
nand NAND2_1223(II6844,II6846,II6847);
nand NAND2_1224(II6852,II6828,II6844);
nand NAND2_1225(II6853,II6828,II6852);
nand NAND2_1226(II6854,II6844,II6852);
nand NAND2_1227(WX2220,II6853,II6854);
nand NAND2_1228(II6861,WX2295,WX1994);
nand NAND2_1229(II6862,WX2295,II6861);
nand NAND2_1230(II6863,WX1994,II6861);
nand NAND2_1231(II6860,II6862,II6863);
nand NAND2_1232(II6868,WX2058,II6860);
nand NAND2_1233(II6869,WX2058,II6868);
nand NAND2_1234(II6870,II6860,II6868);
nand NAND2_1235(II6859,II6869,II6870);
nand NAND2_1236(II6876,WX2122,WX2186);
nand NAND2_1237(II6877,WX2122,II6876);
nand NAND2_1238(II6878,WX2186,II6876);
nand NAND2_1239(II6875,II6877,II6878);
nand NAND2_1240(II6883,II6859,II6875);
nand NAND2_1241(II6884,II6859,II6883);
nand NAND2_1242(II6885,II6875,II6883);
nand NAND2_1243(WX2221,II6884,II6885);
nand NAND2_1244(II6892,WX2295,WX1996);
nand NAND2_1245(II6893,WX2295,II6892);
nand NAND2_1246(II6894,WX1996,II6892);
nand NAND2_1247(II6891,II6893,II6894);
nand NAND2_1248(II6899,WX2060,II6891);
nand NAND2_1249(II6900,WX2060,II6899);
nand NAND2_1250(II6901,II6891,II6899);
nand NAND2_1251(II6890,II6900,II6901);
nand NAND2_1252(II6907,WX2124,WX2188);
nand NAND2_1253(II6908,WX2124,II6907);
nand NAND2_1254(II6909,WX2188,II6907);
nand NAND2_1255(II6906,II6908,II6909);
nand NAND2_1256(II6914,II6890,II6906);
nand NAND2_1257(II6915,II6890,II6914);
nand NAND2_1258(II6916,II6906,II6914);
nand NAND2_1259(WX2222,II6915,II6916);
nand NAND2_1260(II6923,WX2295,WX1998);
nand NAND2_1261(II6924,WX2295,II6923);
nand NAND2_1262(II6925,WX1998,II6923);
nand NAND2_1263(II6922,II6924,II6925);
nand NAND2_1264(II6930,WX2062,II6922);
nand NAND2_1265(II6931,WX2062,II6930);
nand NAND2_1266(II6932,II6922,II6930);
nand NAND2_1267(II6921,II6931,II6932);
nand NAND2_1268(II6938,WX2126,WX2190);
nand NAND2_1269(II6939,WX2126,II6938);
nand NAND2_1270(II6940,WX2190,II6938);
nand NAND2_1271(II6937,II6939,II6940);
nand NAND2_1272(II6945,II6921,II6937);
nand NAND2_1273(II6946,II6921,II6945);
nand NAND2_1274(II6947,II6937,II6945);
nand NAND2_1275(WX2223,II6946,II6947);
nand NAND2_1276(II6954,WX2295,WX2000);
nand NAND2_1277(II6955,WX2295,II6954);
nand NAND2_1278(II6956,WX2000,II6954);
nand NAND2_1279(II6953,II6955,II6956);
nand NAND2_1280(II6961,WX2064,II6953);
nand NAND2_1281(II6962,WX2064,II6961);
nand NAND2_1282(II6963,II6953,II6961);
nand NAND2_1283(II6952,II6962,II6963);
nand NAND2_1284(II6969,WX2128,WX2192);
nand NAND2_1285(II6970,WX2128,II6969);
nand NAND2_1286(II6971,WX2192,II6969);
nand NAND2_1287(II6968,II6970,II6971);
nand NAND2_1288(II6976,II6952,II6968);
nand NAND2_1289(II6977,II6952,II6976);
nand NAND2_1290(II6978,II6968,II6976);
nand NAND2_1291(WX2224,II6977,II6978);
nand NAND2_1292(II7057,WX1873,WX1778);
nand NAND2_1293(II7058,WX1873,II7057);
nand NAND2_1294(II7059,WX1778,II7057);
nand NAND2_1295(WX2299,II7058,II7059);
nand NAND2_1296(II7070,WX1874,WX1780);
nand NAND2_1297(II7071,WX1874,II7070);
nand NAND2_1298(II7072,WX1780,II7070);
nand NAND2_1299(WX2306,II7071,II7072);
nand NAND2_1300(II7083,WX1875,WX1782);
nand NAND2_1301(II7084,WX1875,II7083);
nand NAND2_1302(II7085,WX1782,II7083);
nand NAND2_1303(WX2313,II7084,II7085);
nand NAND2_1304(II7096,WX1876,WX1784);
nand NAND2_1305(II7097,WX1876,II7096);
nand NAND2_1306(II7098,WX1784,II7096);
nand NAND2_1307(WX2320,II7097,II7098);
nand NAND2_1308(II7109,WX1877,WX1786);
nand NAND2_1309(II7110,WX1877,II7109);
nand NAND2_1310(II7111,WX1786,II7109);
nand NAND2_1311(WX2327,II7110,II7111);
nand NAND2_1312(II7122,WX1878,WX1788);
nand NAND2_1313(II7123,WX1878,II7122);
nand NAND2_1314(II7124,WX1788,II7122);
nand NAND2_1315(WX2334,II7123,II7124);
nand NAND2_1316(II7135,WX1879,WX1790);
nand NAND2_1317(II7136,WX1879,II7135);
nand NAND2_1318(II7137,WX1790,II7135);
nand NAND2_1319(WX2341,II7136,II7137);
nand NAND2_1320(II7148,WX1880,WX1792);
nand NAND2_1321(II7149,WX1880,II7148);
nand NAND2_1322(II7150,WX1792,II7148);
nand NAND2_1323(WX2348,II7149,II7150);
nand NAND2_1324(II7161,WX1881,WX1794);
nand NAND2_1325(II7162,WX1881,II7161);
nand NAND2_1326(II7163,WX1794,II7161);
nand NAND2_1327(WX2355,II7162,II7163);
nand NAND2_1328(II7174,WX1882,WX1796);
nand NAND2_1329(II7175,WX1882,II7174);
nand NAND2_1330(II7176,WX1796,II7174);
nand NAND2_1331(WX2362,II7175,II7176);
nand NAND2_1332(II7187,WX1883,WX1798);
nand NAND2_1333(II7188,WX1883,II7187);
nand NAND2_1334(II7189,WX1798,II7187);
nand NAND2_1335(WX2369,II7188,II7189);
nand NAND2_1336(II7200,WX1884,WX1800);
nand NAND2_1337(II7201,WX1884,II7200);
nand NAND2_1338(II7202,WX1800,II7200);
nand NAND2_1339(WX2376,II7201,II7202);
nand NAND2_1340(II7213,WX1885,WX1802);
nand NAND2_1341(II7214,WX1885,II7213);
nand NAND2_1342(II7215,WX1802,II7213);
nand NAND2_1343(WX2383,II7214,II7215);
nand NAND2_1344(II7226,WX1886,WX1804);
nand NAND2_1345(II7227,WX1886,II7226);
nand NAND2_1346(II7228,WX1804,II7226);
nand NAND2_1347(WX2390,II7227,II7228);
nand NAND2_1348(II7239,WX1887,WX1806);
nand NAND2_1349(II7240,WX1887,II7239);
nand NAND2_1350(II7241,WX1806,II7239);
nand NAND2_1351(WX2397,II7240,II7241);
nand NAND2_1352(II7252,WX1888,WX1808);
nand NAND2_1353(II7253,WX1888,II7252);
nand NAND2_1354(II7254,WX1808,II7252);
nand NAND2_1355(WX2404,II7253,II7254);
nand NAND2_1356(II7265,WX1889,WX1810);
nand NAND2_1357(II7266,WX1889,II7265);
nand NAND2_1358(II7267,WX1810,II7265);
nand NAND2_1359(WX2411,II7266,II7267);
nand NAND2_1360(II7278,WX1890,WX1812);
nand NAND2_1361(II7279,WX1890,II7278);
nand NAND2_1362(II7280,WX1812,II7278);
nand NAND2_1363(WX2418,II7279,II7280);
nand NAND2_1364(II7291,WX1891,WX1814);
nand NAND2_1365(II7292,WX1891,II7291);
nand NAND2_1366(II7293,WX1814,II7291);
nand NAND2_1367(WX2425,II7292,II7293);
nand NAND2_1368(II7304,WX1892,WX1816);
nand NAND2_1369(II7305,WX1892,II7304);
nand NAND2_1370(II7306,WX1816,II7304);
nand NAND2_1371(WX2432,II7305,II7306);
nand NAND2_1372(II7317,WX1893,WX1818);
nand NAND2_1373(II7318,WX1893,II7317);
nand NAND2_1374(II7319,WX1818,II7317);
nand NAND2_1375(WX2439,II7318,II7319);
nand NAND2_1376(II7330,WX1894,WX1820);
nand NAND2_1377(II7331,WX1894,II7330);
nand NAND2_1378(II7332,WX1820,II7330);
nand NAND2_1379(WX2446,II7331,II7332);
nand NAND2_1380(II7343,WX1895,WX1822);
nand NAND2_1381(II7344,WX1895,II7343);
nand NAND2_1382(II7345,WX1822,II7343);
nand NAND2_1383(WX2453,II7344,II7345);
nand NAND2_1384(II7356,WX1896,WX1824);
nand NAND2_1385(II7357,WX1896,II7356);
nand NAND2_1386(II7358,WX1824,II7356);
nand NAND2_1387(WX2460,II7357,II7358);
nand NAND2_1388(II7369,WX1897,WX1826);
nand NAND2_1389(II7370,WX1897,II7369);
nand NAND2_1390(II7371,WX1826,II7369);
nand NAND2_1391(WX2467,II7370,II7371);
nand NAND2_1392(II7382,WX1898,WX1828);
nand NAND2_1393(II7383,WX1898,II7382);
nand NAND2_1394(II7384,WX1828,II7382);
nand NAND2_1395(WX2474,II7383,II7384);
nand NAND2_1396(II7395,WX1899,WX1830);
nand NAND2_1397(II7396,WX1899,II7395);
nand NAND2_1398(II7397,WX1830,II7395);
nand NAND2_1399(WX2481,II7396,II7397);
nand NAND2_1400(II7408,WX1900,WX1832);
nand NAND2_1401(II7409,WX1900,II7408);
nand NAND2_1402(II7410,WX1832,II7408);
nand NAND2_1403(WX2488,II7409,II7410);
nand NAND2_1404(II7421,WX1901,WX1834);
nand NAND2_1405(II7422,WX1901,II7421);
nand NAND2_1406(II7423,WX1834,II7421);
nand NAND2_1407(WX2495,II7422,II7423);
nand NAND2_1408(II7434,WX1902,WX1836);
nand NAND2_1409(II7435,WX1902,II7434);
nand NAND2_1410(II7436,WX1836,II7434);
nand NAND2_1411(WX2502,II7435,II7436);
nand NAND2_1412(II7447,WX1903,WX1838);
nand NAND2_1413(II7448,WX1903,II7447);
nand NAND2_1414(II7449,WX1838,II7447);
nand NAND2_1415(WX2509,II7448,II7449);
nand NAND2_1416(II7460,WX1904,WX1840);
nand NAND2_1417(II7461,WX1904,II7460);
nand NAND2_1418(II7462,WX1840,II7460);
nand NAND2_1419(WX2516,II7461,II7462);
nand NAND2_1420(II7475,WX1920,CRC_OUT_8_31);
nand NAND2_1421(II7476,WX1920,II7475);
nand NAND2_1422(II7477,CRC_OUT_8_31,II7475);
nand NAND2_1423(II7474,II7476,II7477);
nand NAND2_1424(II7482,CRC_OUT_8_15,II7474);
nand NAND2_1425(II7483,CRC_OUT_8_15,II7482);
nand NAND2_1426(II7484,II7474,II7482);
nand NAND2_1427(WX2524,II7483,II7484);
nand NAND2_1428(II7490,WX1925,CRC_OUT_8_31);
nand NAND2_1429(II7491,WX1925,II7490);
nand NAND2_1430(II7492,CRC_OUT_8_31,II7490);
nand NAND2_1431(II7489,II7491,II7492);
nand NAND2_1432(II7497,CRC_OUT_8_10,II7489);
nand NAND2_1433(II7498,CRC_OUT_8_10,II7497);
nand NAND2_1434(II7499,II7489,II7497);
nand NAND2_1435(WX2525,II7498,II7499);
nand NAND2_1436(II7505,WX1932,CRC_OUT_8_31);
nand NAND2_1437(II7506,WX1932,II7505);
nand NAND2_1438(II7507,CRC_OUT_8_31,II7505);
nand NAND2_1439(II7504,II7506,II7507);
nand NAND2_1440(II7512,CRC_OUT_8_3,II7504);
nand NAND2_1441(II7513,CRC_OUT_8_3,II7512);
nand NAND2_1442(II7514,II7504,II7512);
nand NAND2_1443(WX2526,II7513,II7514);
nand NAND2_1444(II7519,WX1936,CRC_OUT_8_31);
nand NAND2_1445(II7520,WX1936,II7519);
nand NAND2_1446(II7521,CRC_OUT_8_31,II7519);
nand NAND2_1447(WX2527,II7520,II7521);
nand NAND2_1448(II7526,WX1905,CRC_OUT_8_30);
nand NAND2_1449(II7527,WX1905,II7526);
nand NAND2_1450(II7528,CRC_OUT_8_30,II7526);
nand NAND2_1451(WX2528,II7527,II7528);
nand NAND2_1452(II7533,WX1906,CRC_OUT_8_29);
nand NAND2_1453(II7534,WX1906,II7533);
nand NAND2_1454(II7535,CRC_OUT_8_29,II7533);
nand NAND2_1455(WX2529,II7534,II7535);
nand NAND2_1456(II7540,WX1907,CRC_OUT_8_28);
nand NAND2_1457(II7541,WX1907,II7540);
nand NAND2_1458(II7542,CRC_OUT_8_28,II7540);
nand NAND2_1459(WX2530,II7541,II7542);
nand NAND2_1460(II7547,WX1908,CRC_OUT_8_27);
nand NAND2_1461(II7548,WX1908,II7547);
nand NAND2_1462(II7549,CRC_OUT_8_27,II7547);
nand NAND2_1463(WX2531,II7548,II7549);
nand NAND2_1464(II7554,WX1909,CRC_OUT_8_26);
nand NAND2_1465(II7555,WX1909,II7554);
nand NAND2_1466(II7556,CRC_OUT_8_26,II7554);
nand NAND2_1467(WX2532,II7555,II7556);
nand NAND2_1468(II7561,WX1910,CRC_OUT_8_25);
nand NAND2_1469(II7562,WX1910,II7561);
nand NAND2_1470(II7563,CRC_OUT_8_25,II7561);
nand NAND2_1471(WX2533,II7562,II7563);
nand NAND2_1472(II7568,WX1911,CRC_OUT_8_24);
nand NAND2_1473(II7569,WX1911,II7568);
nand NAND2_1474(II7570,CRC_OUT_8_24,II7568);
nand NAND2_1475(WX2534,II7569,II7570);
nand NAND2_1476(II7575,WX1912,CRC_OUT_8_23);
nand NAND2_1477(II7576,WX1912,II7575);
nand NAND2_1478(II7577,CRC_OUT_8_23,II7575);
nand NAND2_1479(WX2535,II7576,II7577);
nand NAND2_1480(II7582,WX1913,CRC_OUT_8_22);
nand NAND2_1481(II7583,WX1913,II7582);
nand NAND2_1482(II7584,CRC_OUT_8_22,II7582);
nand NAND2_1483(WX2536,II7583,II7584);
nand NAND2_1484(II7589,WX1914,CRC_OUT_8_21);
nand NAND2_1485(II7590,WX1914,II7589);
nand NAND2_1486(II7591,CRC_OUT_8_21,II7589);
nand NAND2_1487(WX2537,II7590,II7591);
nand NAND2_1488(II7596,WX1915,CRC_OUT_8_20);
nand NAND2_1489(II7597,WX1915,II7596);
nand NAND2_1490(II7598,CRC_OUT_8_20,II7596);
nand NAND2_1491(WX2538,II7597,II7598);
nand NAND2_1492(II7603,WX1916,CRC_OUT_8_19);
nand NAND2_1493(II7604,WX1916,II7603);
nand NAND2_1494(II7605,CRC_OUT_8_19,II7603);
nand NAND2_1495(WX2539,II7604,II7605);
nand NAND2_1496(II7610,WX1917,CRC_OUT_8_18);
nand NAND2_1497(II7611,WX1917,II7610);
nand NAND2_1498(II7612,CRC_OUT_8_18,II7610);
nand NAND2_1499(WX2540,II7611,II7612);
nand NAND2_1500(II7617,WX1918,CRC_OUT_8_17);
nand NAND2_1501(II7618,WX1918,II7617);
nand NAND2_1502(II7619,CRC_OUT_8_17,II7617);
nand NAND2_1503(WX2541,II7618,II7619);
nand NAND2_1504(II7624,WX1919,CRC_OUT_8_16);
nand NAND2_1505(II7625,WX1919,II7624);
nand NAND2_1506(II7626,CRC_OUT_8_16,II7624);
nand NAND2_1507(WX2542,II7625,II7626);
nand NAND2_1508(II7631,WX1921,CRC_OUT_8_14);
nand NAND2_1509(II7632,WX1921,II7631);
nand NAND2_1510(II7633,CRC_OUT_8_14,II7631);
nand NAND2_1511(WX2543,II7632,II7633);
nand NAND2_1512(II7638,WX1922,CRC_OUT_8_13);
nand NAND2_1513(II7639,WX1922,II7638);
nand NAND2_1514(II7640,CRC_OUT_8_13,II7638);
nand NAND2_1515(WX2544,II7639,II7640);
nand NAND2_1516(II7645,WX1923,CRC_OUT_8_12);
nand NAND2_1517(II7646,WX1923,II7645);
nand NAND2_1518(II7647,CRC_OUT_8_12,II7645);
nand NAND2_1519(WX2545,II7646,II7647);
nand NAND2_1520(II7652,WX1924,CRC_OUT_8_11);
nand NAND2_1521(II7653,WX1924,II7652);
nand NAND2_1522(II7654,CRC_OUT_8_11,II7652);
nand NAND2_1523(WX2546,II7653,II7654);
nand NAND2_1524(II7659,WX1926,CRC_OUT_8_9);
nand NAND2_1525(II7660,WX1926,II7659);
nand NAND2_1526(II7661,CRC_OUT_8_9,II7659);
nand NAND2_1527(WX2547,II7660,II7661);
nand NAND2_1528(II7666,WX1927,CRC_OUT_8_8);
nand NAND2_1529(II7667,WX1927,II7666);
nand NAND2_1530(II7668,CRC_OUT_8_8,II7666);
nand NAND2_1531(WX2548,II7667,II7668);
nand NAND2_1532(II7673,WX1928,CRC_OUT_8_7);
nand NAND2_1533(II7674,WX1928,II7673);
nand NAND2_1534(II7675,CRC_OUT_8_7,II7673);
nand NAND2_1535(WX2549,II7674,II7675);
nand NAND2_1536(II7680,WX1929,CRC_OUT_8_6);
nand NAND2_1537(II7681,WX1929,II7680);
nand NAND2_1538(II7682,CRC_OUT_8_6,II7680);
nand NAND2_1539(WX2550,II7681,II7682);
nand NAND2_1540(II7687,WX1930,CRC_OUT_8_5);
nand NAND2_1541(II7688,WX1930,II7687);
nand NAND2_1542(II7689,CRC_OUT_8_5,II7687);
nand NAND2_1543(WX2551,II7688,II7689);
nand NAND2_1544(II7694,WX1931,CRC_OUT_8_4);
nand NAND2_1545(II7695,WX1931,II7694);
nand NAND2_1546(II7696,CRC_OUT_8_4,II7694);
nand NAND2_1547(WX2552,II7695,II7696);
nand NAND2_1548(II7701,WX1933,CRC_OUT_8_2);
nand NAND2_1549(II7702,WX1933,II7701);
nand NAND2_1550(II7703,CRC_OUT_8_2,II7701);
nand NAND2_1551(WX2553,II7702,II7703);
nand NAND2_1552(II7708,WX1934,CRC_OUT_8_1);
nand NAND2_1553(II7709,WX1934,II7708);
nand NAND2_1554(II7710,CRC_OUT_8_1,II7708);
nand NAND2_1555(WX2554,II7709,II7710);
nand NAND2_1556(II7715,WX1935,CRC_OUT_8_0);
nand NAND2_1557(II7716,WX1935,II7715);
nand NAND2_1558(II7717,CRC_OUT_8_0,II7715);
nand NAND2_1559(WX2555,II7716,II7717);
nand NAND2_1560(II9998,WX3587,WX3231);
nand NAND2_1561(II9999,WX3587,II9998);
nand NAND2_1562(II10000,WX3231,II9998);
nand NAND2_1563(II9997,II9999,II10000);
nand NAND2_1564(II10005,WX3295,II9997);
nand NAND2_1565(II10006,WX3295,II10005);
nand NAND2_1566(II10007,II9997,II10005);
nand NAND2_1567(II9996,II10006,II10007);
nand NAND2_1568(II10013,WX3359,WX3423);
nand NAND2_1569(II10014,WX3359,II10013);
nand NAND2_1570(II10015,WX3423,II10013);
nand NAND2_1571(II10012,II10014,II10015);
nand NAND2_1572(II10020,II9996,II10012);
nand NAND2_1573(II10021,II9996,II10020);
nand NAND2_1574(II10022,II10012,II10020);
nand NAND2_1575(WX3486,II10021,II10022);
nand NAND2_1576(II10029,WX3587,WX3233);
nand NAND2_1577(II10030,WX3587,II10029);
nand NAND2_1578(II10031,WX3233,II10029);
nand NAND2_1579(II10028,II10030,II10031);
nand NAND2_1580(II10036,WX3297,II10028);
nand NAND2_1581(II10037,WX3297,II10036);
nand NAND2_1582(II10038,II10028,II10036);
nand NAND2_1583(II10027,II10037,II10038);
nand NAND2_1584(II10044,WX3361,WX3425);
nand NAND2_1585(II10045,WX3361,II10044);
nand NAND2_1586(II10046,WX3425,II10044);
nand NAND2_1587(II10043,II10045,II10046);
nand NAND2_1588(II10051,II10027,II10043);
nand NAND2_1589(II10052,II10027,II10051);
nand NAND2_1590(II10053,II10043,II10051);
nand NAND2_1591(WX3487,II10052,II10053);
nand NAND2_1592(II10060,WX3587,WX3235);
nand NAND2_1593(II10061,WX3587,II10060);
nand NAND2_1594(II10062,WX3235,II10060);
nand NAND2_1595(II10059,II10061,II10062);
nand NAND2_1596(II10067,WX3299,II10059);
nand NAND2_1597(II10068,WX3299,II10067);
nand NAND2_1598(II10069,II10059,II10067);
nand NAND2_1599(II10058,II10068,II10069);
nand NAND2_1600(II10075,WX3363,WX3427);
nand NAND2_1601(II10076,WX3363,II10075);
nand NAND2_1602(II10077,WX3427,II10075);
nand NAND2_1603(II10074,II10076,II10077);
nand NAND2_1604(II10082,II10058,II10074);
nand NAND2_1605(II10083,II10058,II10082);
nand NAND2_1606(II10084,II10074,II10082);
nand NAND2_1607(WX3488,II10083,II10084);
nand NAND2_1608(II10091,WX3587,WX3237);
nand NAND2_1609(II10092,WX3587,II10091);
nand NAND2_1610(II10093,WX3237,II10091);
nand NAND2_1611(II10090,II10092,II10093);
nand NAND2_1612(II10098,WX3301,II10090);
nand NAND2_1613(II10099,WX3301,II10098);
nand NAND2_1614(II10100,II10090,II10098);
nand NAND2_1615(II10089,II10099,II10100);
nand NAND2_1616(II10106,WX3365,WX3429);
nand NAND2_1617(II10107,WX3365,II10106);
nand NAND2_1618(II10108,WX3429,II10106);
nand NAND2_1619(II10105,II10107,II10108);
nand NAND2_1620(II10113,II10089,II10105);
nand NAND2_1621(II10114,II10089,II10113);
nand NAND2_1622(II10115,II10105,II10113);
nand NAND2_1623(WX3489,II10114,II10115);
nand NAND2_1624(II10122,WX3587,WX3239);
nand NAND2_1625(II10123,WX3587,II10122);
nand NAND2_1626(II10124,WX3239,II10122);
nand NAND2_1627(II10121,II10123,II10124);
nand NAND2_1628(II10129,WX3303,II10121);
nand NAND2_1629(II10130,WX3303,II10129);
nand NAND2_1630(II10131,II10121,II10129);
nand NAND2_1631(II10120,II10130,II10131);
nand NAND2_1632(II10137,WX3367,WX3431);
nand NAND2_1633(II10138,WX3367,II10137);
nand NAND2_1634(II10139,WX3431,II10137);
nand NAND2_1635(II10136,II10138,II10139);
nand NAND2_1636(II10144,II10120,II10136);
nand NAND2_1637(II10145,II10120,II10144);
nand NAND2_1638(II10146,II10136,II10144);
nand NAND2_1639(WX3490,II10145,II10146);
nand NAND2_1640(II10153,WX3587,WX3241);
nand NAND2_1641(II10154,WX3587,II10153);
nand NAND2_1642(II10155,WX3241,II10153);
nand NAND2_1643(II10152,II10154,II10155);
nand NAND2_1644(II10160,WX3305,II10152);
nand NAND2_1645(II10161,WX3305,II10160);
nand NAND2_1646(II10162,II10152,II10160);
nand NAND2_1647(II10151,II10161,II10162);
nand NAND2_1648(II10168,WX3369,WX3433);
nand NAND2_1649(II10169,WX3369,II10168);
nand NAND2_1650(II10170,WX3433,II10168);
nand NAND2_1651(II10167,II10169,II10170);
nand NAND2_1652(II10175,II10151,II10167);
nand NAND2_1653(II10176,II10151,II10175);
nand NAND2_1654(II10177,II10167,II10175);
nand NAND2_1655(WX3491,II10176,II10177);
nand NAND2_1656(II10184,WX3587,WX3243);
nand NAND2_1657(II10185,WX3587,II10184);
nand NAND2_1658(II10186,WX3243,II10184);
nand NAND2_1659(II10183,II10185,II10186);
nand NAND2_1660(II10191,WX3307,II10183);
nand NAND2_1661(II10192,WX3307,II10191);
nand NAND2_1662(II10193,II10183,II10191);
nand NAND2_1663(II10182,II10192,II10193);
nand NAND2_1664(II10199,WX3371,WX3435);
nand NAND2_1665(II10200,WX3371,II10199);
nand NAND2_1666(II10201,WX3435,II10199);
nand NAND2_1667(II10198,II10200,II10201);
nand NAND2_1668(II10206,II10182,II10198);
nand NAND2_1669(II10207,II10182,II10206);
nand NAND2_1670(II10208,II10198,II10206);
nand NAND2_1671(WX3492,II10207,II10208);
nand NAND2_1672(II10215,WX3587,WX3245);
nand NAND2_1673(II10216,WX3587,II10215);
nand NAND2_1674(II10217,WX3245,II10215);
nand NAND2_1675(II10214,II10216,II10217);
nand NAND2_1676(II10222,WX3309,II10214);
nand NAND2_1677(II10223,WX3309,II10222);
nand NAND2_1678(II10224,II10214,II10222);
nand NAND2_1679(II10213,II10223,II10224);
nand NAND2_1680(II10230,WX3373,WX3437);
nand NAND2_1681(II10231,WX3373,II10230);
nand NAND2_1682(II10232,WX3437,II10230);
nand NAND2_1683(II10229,II10231,II10232);
nand NAND2_1684(II10237,II10213,II10229);
nand NAND2_1685(II10238,II10213,II10237);
nand NAND2_1686(II10239,II10229,II10237);
nand NAND2_1687(WX3493,II10238,II10239);
nand NAND2_1688(II10246,WX3587,WX3247);
nand NAND2_1689(II10247,WX3587,II10246);
nand NAND2_1690(II10248,WX3247,II10246);
nand NAND2_1691(II10245,II10247,II10248);
nand NAND2_1692(II10253,WX3311,II10245);
nand NAND2_1693(II10254,WX3311,II10253);
nand NAND2_1694(II10255,II10245,II10253);
nand NAND2_1695(II10244,II10254,II10255);
nand NAND2_1696(II10261,WX3375,WX3439);
nand NAND2_1697(II10262,WX3375,II10261);
nand NAND2_1698(II10263,WX3439,II10261);
nand NAND2_1699(II10260,II10262,II10263);
nand NAND2_1700(II10268,II10244,II10260);
nand NAND2_1701(II10269,II10244,II10268);
nand NAND2_1702(II10270,II10260,II10268);
nand NAND2_1703(WX3494,II10269,II10270);
nand NAND2_1704(II10277,WX3587,WX3249);
nand NAND2_1705(II10278,WX3587,II10277);
nand NAND2_1706(II10279,WX3249,II10277);
nand NAND2_1707(II10276,II10278,II10279);
nand NAND2_1708(II10284,WX3313,II10276);
nand NAND2_1709(II10285,WX3313,II10284);
nand NAND2_1710(II10286,II10276,II10284);
nand NAND2_1711(II10275,II10285,II10286);
nand NAND2_1712(II10292,WX3377,WX3441);
nand NAND2_1713(II10293,WX3377,II10292);
nand NAND2_1714(II10294,WX3441,II10292);
nand NAND2_1715(II10291,II10293,II10294);
nand NAND2_1716(II10299,II10275,II10291);
nand NAND2_1717(II10300,II10275,II10299);
nand NAND2_1718(II10301,II10291,II10299);
nand NAND2_1719(WX3495,II10300,II10301);
nand NAND2_1720(II10308,WX3587,WX3251);
nand NAND2_1721(II10309,WX3587,II10308);
nand NAND2_1722(II10310,WX3251,II10308);
nand NAND2_1723(II10307,II10309,II10310);
nand NAND2_1724(II10315,WX3315,II10307);
nand NAND2_1725(II10316,WX3315,II10315);
nand NAND2_1726(II10317,II10307,II10315);
nand NAND2_1727(II10306,II10316,II10317);
nand NAND2_1728(II10323,WX3379,WX3443);
nand NAND2_1729(II10324,WX3379,II10323);
nand NAND2_1730(II10325,WX3443,II10323);
nand NAND2_1731(II10322,II10324,II10325);
nand NAND2_1732(II10330,II10306,II10322);
nand NAND2_1733(II10331,II10306,II10330);
nand NAND2_1734(II10332,II10322,II10330);
nand NAND2_1735(WX3496,II10331,II10332);
nand NAND2_1736(II10339,WX3587,WX3253);
nand NAND2_1737(II10340,WX3587,II10339);
nand NAND2_1738(II10341,WX3253,II10339);
nand NAND2_1739(II10338,II10340,II10341);
nand NAND2_1740(II10346,WX3317,II10338);
nand NAND2_1741(II10347,WX3317,II10346);
nand NAND2_1742(II10348,II10338,II10346);
nand NAND2_1743(II10337,II10347,II10348);
nand NAND2_1744(II10354,WX3381,WX3445);
nand NAND2_1745(II10355,WX3381,II10354);
nand NAND2_1746(II10356,WX3445,II10354);
nand NAND2_1747(II10353,II10355,II10356);
nand NAND2_1748(II10361,II10337,II10353);
nand NAND2_1749(II10362,II10337,II10361);
nand NAND2_1750(II10363,II10353,II10361);
nand NAND2_1751(WX3497,II10362,II10363);
nand NAND2_1752(II10370,WX3587,WX3255);
nand NAND2_1753(II10371,WX3587,II10370);
nand NAND2_1754(II10372,WX3255,II10370);
nand NAND2_1755(II10369,II10371,II10372);
nand NAND2_1756(II10377,WX3319,II10369);
nand NAND2_1757(II10378,WX3319,II10377);
nand NAND2_1758(II10379,II10369,II10377);
nand NAND2_1759(II10368,II10378,II10379);
nand NAND2_1760(II10385,WX3383,WX3447);
nand NAND2_1761(II10386,WX3383,II10385);
nand NAND2_1762(II10387,WX3447,II10385);
nand NAND2_1763(II10384,II10386,II10387);
nand NAND2_1764(II10392,II10368,II10384);
nand NAND2_1765(II10393,II10368,II10392);
nand NAND2_1766(II10394,II10384,II10392);
nand NAND2_1767(WX3498,II10393,II10394);
nand NAND2_1768(II10401,WX3587,WX3257);
nand NAND2_1769(II10402,WX3587,II10401);
nand NAND2_1770(II10403,WX3257,II10401);
nand NAND2_1771(II10400,II10402,II10403);
nand NAND2_1772(II10408,WX3321,II10400);
nand NAND2_1773(II10409,WX3321,II10408);
nand NAND2_1774(II10410,II10400,II10408);
nand NAND2_1775(II10399,II10409,II10410);
nand NAND2_1776(II10416,WX3385,WX3449);
nand NAND2_1777(II10417,WX3385,II10416);
nand NAND2_1778(II10418,WX3449,II10416);
nand NAND2_1779(II10415,II10417,II10418);
nand NAND2_1780(II10423,II10399,II10415);
nand NAND2_1781(II10424,II10399,II10423);
nand NAND2_1782(II10425,II10415,II10423);
nand NAND2_1783(WX3499,II10424,II10425);
nand NAND2_1784(II10432,WX3587,WX3259);
nand NAND2_1785(II10433,WX3587,II10432);
nand NAND2_1786(II10434,WX3259,II10432);
nand NAND2_1787(II10431,II10433,II10434);
nand NAND2_1788(II10439,WX3323,II10431);
nand NAND2_1789(II10440,WX3323,II10439);
nand NAND2_1790(II10441,II10431,II10439);
nand NAND2_1791(II10430,II10440,II10441);
nand NAND2_1792(II10447,WX3387,WX3451);
nand NAND2_1793(II10448,WX3387,II10447);
nand NAND2_1794(II10449,WX3451,II10447);
nand NAND2_1795(II10446,II10448,II10449);
nand NAND2_1796(II10454,II10430,II10446);
nand NAND2_1797(II10455,II10430,II10454);
nand NAND2_1798(II10456,II10446,II10454);
nand NAND2_1799(WX3500,II10455,II10456);
nand NAND2_1800(II10463,WX3587,WX3261);
nand NAND2_1801(II10464,WX3587,II10463);
nand NAND2_1802(II10465,WX3261,II10463);
nand NAND2_1803(II10462,II10464,II10465);
nand NAND2_1804(II10470,WX3325,II10462);
nand NAND2_1805(II10471,WX3325,II10470);
nand NAND2_1806(II10472,II10462,II10470);
nand NAND2_1807(II10461,II10471,II10472);
nand NAND2_1808(II10478,WX3389,WX3453);
nand NAND2_1809(II10479,WX3389,II10478);
nand NAND2_1810(II10480,WX3453,II10478);
nand NAND2_1811(II10477,II10479,II10480);
nand NAND2_1812(II10485,II10461,II10477);
nand NAND2_1813(II10486,II10461,II10485);
nand NAND2_1814(II10487,II10477,II10485);
nand NAND2_1815(WX3501,II10486,II10487);
nand NAND2_1816(II10494,WX3588,WX3263);
nand NAND2_1817(II10495,WX3588,II10494);
nand NAND2_1818(II10496,WX3263,II10494);
nand NAND2_1819(II10493,II10495,II10496);
nand NAND2_1820(II10501,WX3327,II10493);
nand NAND2_1821(II10502,WX3327,II10501);
nand NAND2_1822(II10503,II10493,II10501);
nand NAND2_1823(II10492,II10502,II10503);
nand NAND2_1824(II10509,WX3391,WX3455);
nand NAND2_1825(II10510,WX3391,II10509);
nand NAND2_1826(II10511,WX3455,II10509);
nand NAND2_1827(II10508,II10510,II10511);
nand NAND2_1828(II10516,II10492,II10508);
nand NAND2_1829(II10517,II10492,II10516);
nand NAND2_1830(II10518,II10508,II10516);
nand NAND2_1831(WX3502,II10517,II10518);
nand NAND2_1832(II10525,WX3588,WX3265);
nand NAND2_1833(II10526,WX3588,II10525);
nand NAND2_1834(II10527,WX3265,II10525);
nand NAND2_1835(II10524,II10526,II10527);
nand NAND2_1836(II10532,WX3329,II10524);
nand NAND2_1837(II10533,WX3329,II10532);
nand NAND2_1838(II10534,II10524,II10532);
nand NAND2_1839(II10523,II10533,II10534);
nand NAND2_1840(II10540,WX3393,WX3457);
nand NAND2_1841(II10541,WX3393,II10540);
nand NAND2_1842(II10542,WX3457,II10540);
nand NAND2_1843(II10539,II10541,II10542);
nand NAND2_1844(II10547,II10523,II10539);
nand NAND2_1845(II10548,II10523,II10547);
nand NAND2_1846(II10549,II10539,II10547);
nand NAND2_1847(WX3503,II10548,II10549);
nand NAND2_1848(II10556,WX3588,WX3267);
nand NAND2_1849(II10557,WX3588,II10556);
nand NAND2_1850(II10558,WX3267,II10556);
nand NAND2_1851(II10555,II10557,II10558);
nand NAND2_1852(II10563,WX3331,II10555);
nand NAND2_1853(II10564,WX3331,II10563);
nand NAND2_1854(II10565,II10555,II10563);
nand NAND2_1855(II10554,II10564,II10565);
nand NAND2_1856(II10571,WX3395,WX3459);
nand NAND2_1857(II10572,WX3395,II10571);
nand NAND2_1858(II10573,WX3459,II10571);
nand NAND2_1859(II10570,II10572,II10573);
nand NAND2_1860(II10578,II10554,II10570);
nand NAND2_1861(II10579,II10554,II10578);
nand NAND2_1862(II10580,II10570,II10578);
nand NAND2_1863(WX3504,II10579,II10580);
nand NAND2_1864(II10587,WX3588,WX3269);
nand NAND2_1865(II10588,WX3588,II10587);
nand NAND2_1866(II10589,WX3269,II10587);
nand NAND2_1867(II10586,II10588,II10589);
nand NAND2_1868(II10594,WX3333,II10586);
nand NAND2_1869(II10595,WX3333,II10594);
nand NAND2_1870(II10596,II10586,II10594);
nand NAND2_1871(II10585,II10595,II10596);
nand NAND2_1872(II10602,WX3397,WX3461);
nand NAND2_1873(II10603,WX3397,II10602);
nand NAND2_1874(II10604,WX3461,II10602);
nand NAND2_1875(II10601,II10603,II10604);
nand NAND2_1876(II10609,II10585,II10601);
nand NAND2_1877(II10610,II10585,II10609);
nand NAND2_1878(II10611,II10601,II10609);
nand NAND2_1879(WX3505,II10610,II10611);
nand NAND2_1880(II10618,WX3588,WX3271);
nand NAND2_1881(II10619,WX3588,II10618);
nand NAND2_1882(II10620,WX3271,II10618);
nand NAND2_1883(II10617,II10619,II10620);
nand NAND2_1884(II10625,WX3335,II10617);
nand NAND2_1885(II10626,WX3335,II10625);
nand NAND2_1886(II10627,II10617,II10625);
nand NAND2_1887(II10616,II10626,II10627);
nand NAND2_1888(II10633,WX3399,WX3463);
nand NAND2_1889(II10634,WX3399,II10633);
nand NAND2_1890(II10635,WX3463,II10633);
nand NAND2_1891(II10632,II10634,II10635);
nand NAND2_1892(II10640,II10616,II10632);
nand NAND2_1893(II10641,II10616,II10640);
nand NAND2_1894(II10642,II10632,II10640);
nand NAND2_1895(WX3506,II10641,II10642);
nand NAND2_1896(II10649,WX3588,WX3273);
nand NAND2_1897(II10650,WX3588,II10649);
nand NAND2_1898(II10651,WX3273,II10649);
nand NAND2_1899(II10648,II10650,II10651);
nand NAND2_1900(II10656,WX3337,II10648);
nand NAND2_1901(II10657,WX3337,II10656);
nand NAND2_1902(II10658,II10648,II10656);
nand NAND2_1903(II10647,II10657,II10658);
nand NAND2_1904(II10664,WX3401,WX3465);
nand NAND2_1905(II10665,WX3401,II10664);
nand NAND2_1906(II10666,WX3465,II10664);
nand NAND2_1907(II10663,II10665,II10666);
nand NAND2_1908(II10671,II10647,II10663);
nand NAND2_1909(II10672,II10647,II10671);
nand NAND2_1910(II10673,II10663,II10671);
nand NAND2_1911(WX3507,II10672,II10673);
nand NAND2_1912(II10680,WX3588,WX3275);
nand NAND2_1913(II10681,WX3588,II10680);
nand NAND2_1914(II10682,WX3275,II10680);
nand NAND2_1915(II10679,II10681,II10682);
nand NAND2_1916(II10687,WX3339,II10679);
nand NAND2_1917(II10688,WX3339,II10687);
nand NAND2_1918(II10689,II10679,II10687);
nand NAND2_1919(II10678,II10688,II10689);
nand NAND2_1920(II10695,WX3403,WX3467);
nand NAND2_1921(II10696,WX3403,II10695);
nand NAND2_1922(II10697,WX3467,II10695);
nand NAND2_1923(II10694,II10696,II10697);
nand NAND2_1924(II10702,II10678,II10694);
nand NAND2_1925(II10703,II10678,II10702);
nand NAND2_1926(II10704,II10694,II10702);
nand NAND2_1927(WX3508,II10703,II10704);
nand NAND2_1928(II10711,WX3588,WX3277);
nand NAND2_1929(II10712,WX3588,II10711);
nand NAND2_1930(II10713,WX3277,II10711);
nand NAND2_1931(II10710,II10712,II10713);
nand NAND2_1932(II10718,WX3341,II10710);
nand NAND2_1933(II10719,WX3341,II10718);
nand NAND2_1934(II10720,II10710,II10718);
nand NAND2_1935(II10709,II10719,II10720);
nand NAND2_1936(II10726,WX3405,WX3469);
nand NAND2_1937(II10727,WX3405,II10726);
nand NAND2_1938(II10728,WX3469,II10726);
nand NAND2_1939(II10725,II10727,II10728);
nand NAND2_1940(II10733,II10709,II10725);
nand NAND2_1941(II10734,II10709,II10733);
nand NAND2_1942(II10735,II10725,II10733);
nand NAND2_1943(WX3509,II10734,II10735);
nand NAND2_1944(II10742,WX3588,WX3279);
nand NAND2_1945(II10743,WX3588,II10742);
nand NAND2_1946(II10744,WX3279,II10742);
nand NAND2_1947(II10741,II10743,II10744);
nand NAND2_1948(II10749,WX3343,II10741);
nand NAND2_1949(II10750,WX3343,II10749);
nand NAND2_1950(II10751,II10741,II10749);
nand NAND2_1951(II10740,II10750,II10751);
nand NAND2_1952(II10757,WX3407,WX3471);
nand NAND2_1953(II10758,WX3407,II10757);
nand NAND2_1954(II10759,WX3471,II10757);
nand NAND2_1955(II10756,II10758,II10759);
nand NAND2_1956(II10764,II10740,II10756);
nand NAND2_1957(II10765,II10740,II10764);
nand NAND2_1958(II10766,II10756,II10764);
nand NAND2_1959(WX3510,II10765,II10766);
nand NAND2_1960(II10773,WX3588,WX3281);
nand NAND2_1961(II10774,WX3588,II10773);
nand NAND2_1962(II10775,WX3281,II10773);
nand NAND2_1963(II10772,II10774,II10775);
nand NAND2_1964(II10780,WX3345,II10772);
nand NAND2_1965(II10781,WX3345,II10780);
nand NAND2_1966(II10782,II10772,II10780);
nand NAND2_1967(II10771,II10781,II10782);
nand NAND2_1968(II10788,WX3409,WX3473);
nand NAND2_1969(II10789,WX3409,II10788);
nand NAND2_1970(II10790,WX3473,II10788);
nand NAND2_1971(II10787,II10789,II10790);
nand NAND2_1972(II10795,II10771,II10787);
nand NAND2_1973(II10796,II10771,II10795);
nand NAND2_1974(II10797,II10787,II10795);
nand NAND2_1975(WX3511,II10796,II10797);
nand NAND2_1976(II10804,WX3588,WX3283);
nand NAND2_1977(II10805,WX3588,II10804);
nand NAND2_1978(II10806,WX3283,II10804);
nand NAND2_1979(II10803,II10805,II10806);
nand NAND2_1980(II10811,WX3347,II10803);
nand NAND2_1981(II10812,WX3347,II10811);
nand NAND2_1982(II10813,II10803,II10811);
nand NAND2_1983(II10802,II10812,II10813);
nand NAND2_1984(II10819,WX3411,WX3475);
nand NAND2_1985(II10820,WX3411,II10819);
nand NAND2_1986(II10821,WX3475,II10819);
nand NAND2_1987(II10818,II10820,II10821);
nand NAND2_1988(II10826,II10802,II10818);
nand NAND2_1989(II10827,II10802,II10826);
nand NAND2_1990(II10828,II10818,II10826);
nand NAND2_1991(WX3512,II10827,II10828);
nand NAND2_1992(II10835,WX3588,WX3285);
nand NAND2_1993(II10836,WX3588,II10835);
nand NAND2_1994(II10837,WX3285,II10835);
nand NAND2_1995(II10834,II10836,II10837);
nand NAND2_1996(II10842,WX3349,II10834);
nand NAND2_1997(II10843,WX3349,II10842);
nand NAND2_1998(II10844,II10834,II10842);
nand NAND2_1999(II10833,II10843,II10844);
nand NAND2_2000(II10850,WX3413,WX3477);
nand NAND2_2001(II10851,WX3413,II10850);
nand NAND2_2002(II10852,WX3477,II10850);
nand NAND2_2003(II10849,II10851,II10852);
nand NAND2_2004(II10857,II10833,II10849);
nand NAND2_2005(II10858,II10833,II10857);
nand NAND2_2006(II10859,II10849,II10857);
nand NAND2_2007(WX3513,II10858,II10859);
nand NAND2_2008(II10866,WX3588,WX3287);
nand NAND2_2009(II10867,WX3588,II10866);
nand NAND2_2010(II10868,WX3287,II10866);
nand NAND2_2011(II10865,II10867,II10868);
nand NAND2_2012(II10873,WX3351,II10865);
nand NAND2_2013(II10874,WX3351,II10873);
nand NAND2_2014(II10875,II10865,II10873);
nand NAND2_2015(II10864,II10874,II10875);
nand NAND2_2016(II10881,WX3415,WX3479);
nand NAND2_2017(II10882,WX3415,II10881);
nand NAND2_2018(II10883,WX3479,II10881);
nand NAND2_2019(II10880,II10882,II10883);
nand NAND2_2020(II10888,II10864,II10880);
nand NAND2_2021(II10889,II10864,II10888);
nand NAND2_2022(II10890,II10880,II10888);
nand NAND2_2023(WX3514,II10889,II10890);
nand NAND2_2024(II10897,WX3588,WX3289);
nand NAND2_2025(II10898,WX3588,II10897);
nand NAND2_2026(II10899,WX3289,II10897);
nand NAND2_2027(II10896,II10898,II10899);
nand NAND2_2028(II10904,WX3353,II10896);
nand NAND2_2029(II10905,WX3353,II10904);
nand NAND2_2030(II10906,II10896,II10904);
nand NAND2_2031(II10895,II10905,II10906);
nand NAND2_2032(II10912,WX3417,WX3481);
nand NAND2_2033(II10913,WX3417,II10912);
nand NAND2_2034(II10914,WX3481,II10912);
nand NAND2_2035(II10911,II10913,II10914);
nand NAND2_2036(II10919,II10895,II10911);
nand NAND2_2037(II10920,II10895,II10919);
nand NAND2_2038(II10921,II10911,II10919);
nand NAND2_2039(WX3515,II10920,II10921);
nand NAND2_2040(II10928,WX3588,WX3291);
nand NAND2_2041(II10929,WX3588,II10928);
nand NAND2_2042(II10930,WX3291,II10928);
nand NAND2_2043(II10927,II10929,II10930);
nand NAND2_2044(II10935,WX3355,II10927);
nand NAND2_2045(II10936,WX3355,II10935);
nand NAND2_2046(II10937,II10927,II10935);
nand NAND2_2047(II10926,II10936,II10937);
nand NAND2_2048(II10943,WX3419,WX3483);
nand NAND2_2049(II10944,WX3419,II10943);
nand NAND2_2050(II10945,WX3483,II10943);
nand NAND2_2051(II10942,II10944,II10945);
nand NAND2_2052(II10950,II10926,II10942);
nand NAND2_2053(II10951,II10926,II10950);
nand NAND2_2054(II10952,II10942,II10950);
nand NAND2_2055(WX3516,II10951,II10952);
nand NAND2_2056(II10959,WX3588,WX3293);
nand NAND2_2057(II10960,WX3588,II10959);
nand NAND2_2058(II10961,WX3293,II10959);
nand NAND2_2059(II10958,II10960,II10961);
nand NAND2_2060(II10966,WX3357,II10958);
nand NAND2_2061(II10967,WX3357,II10966);
nand NAND2_2062(II10968,II10958,II10966);
nand NAND2_2063(II10957,II10967,II10968);
nand NAND2_2064(II10974,WX3421,WX3485);
nand NAND2_2065(II10975,WX3421,II10974);
nand NAND2_2066(II10976,WX3485,II10974);
nand NAND2_2067(II10973,II10975,II10976);
nand NAND2_2068(II10981,II10957,II10973);
nand NAND2_2069(II10982,II10957,II10981);
nand NAND2_2070(II10983,II10973,II10981);
nand NAND2_2071(WX3517,II10982,II10983);
nand NAND2_2072(II11062,WX3166,WX3071);
nand NAND2_2073(II11063,WX3166,II11062);
nand NAND2_2074(II11064,WX3071,II11062);
nand NAND2_2075(WX3592,II11063,II11064);
nand NAND2_2076(II11075,WX3167,WX3073);
nand NAND2_2077(II11076,WX3167,II11075);
nand NAND2_2078(II11077,WX3073,II11075);
nand NAND2_2079(WX3599,II11076,II11077);
nand NAND2_2080(II11088,WX3168,WX3075);
nand NAND2_2081(II11089,WX3168,II11088);
nand NAND2_2082(II11090,WX3075,II11088);
nand NAND2_2083(WX3606,II11089,II11090);
nand NAND2_2084(II11101,WX3169,WX3077);
nand NAND2_2085(II11102,WX3169,II11101);
nand NAND2_2086(II11103,WX3077,II11101);
nand NAND2_2087(WX3613,II11102,II11103);
nand NAND2_2088(II11114,WX3170,WX3079);
nand NAND2_2089(II11115,WX3170,II11114);
nand NAND2_2090(II11116,WX3079,II11114);
nand NAND2_2091(WX3620,II11115,II11116);
nand NAND2_2092(II11127,WX3171,WX3081);
nand NAND2_2093(II11128,WX3171,II11127);
nand NAND2_2094(II11129,WX3081,II11127);
nand NAND2_2095(WX3627,II11128,II11129);
nand NAND2_2096(II11140,WX3172,WX3083);
nand NAND2_2097(II11141,WX3172,II11140);
nand NAND2_2098(II11142,WX3083,II11140);
nand NAND2_2099(WX3634,II11141,II11142);
nand NAND2_2100(II11153,WX3173,WX3085);
nand NAND2_2101(II11154,WX3173,II11153);
nand NAND2_2102(II11155,WX3085,II11153);
nand NAND2_2103(WX3641,II11154,II11155);
nand NAND2_2104(II11166,WX3174,WX3087);
nand NAND2_2105(II11167,WX3174,II11166);
nand NAND2_2106(II11168,WX3087,II11166);
nand NAND2_2107(WX3648,II11167,II11168);
nand NAND2_2108(II11179,WX3175,WX3089);
nand NAND2_2109(II11180,WX3175,II11179);
nand NAND2_2110(II11181,WX3089,II11179);
nand NAND2_2111(WX3655,II11180,II11181);
nand NAND2_2112(II11192,WX3176,WX3091);
nand NAND2_2113(II11193,WX3176,II11192);
nand NAND2_2114(II11194,WX3091,II11192);
nand NAND2_2115(WX3662,II11193,II11194);
nand NAND2_2116(II11205,WX3177,WX3093);
nand NAND2_2117(II11206,WX3177,II11205);
nand NAND2_2118(II11207,WX3093,II11205);
nand NAND2_2119(WX3669,II11206,II11207);
nand NAND2_2120(II11218,WX3178,WX3095);
nand NAND2_2121(II11219,WX3178,II11218);
nand NAND2_2122(II11220,WX3095,II11218);
nand NAND2_2123(WX3676,II11219,II11220);
nand NAND2_2124(II11231,WX3179,WX3097);
nand NAND2_2125(II11232,WX3179,II11231);
nand NAND2_2126(II11233,WX3097,II11231);
nand NAND2_2127(WX3683,II11232,II11233);
nand NAND2_2128(II11244,WX3180,WX3099);
nand NAND2_2129(II11245,WX3180,II11244);
nand NAND2_2130(II11246,WX3099,II11244);
nand NAND2_2131(WX3690,II11245,II11246);
nand NAND2_2132(II11257,WX3181,WX3101);
nand NAND2_2133(II11258,WX3181,II11257);
nand NAND2_2134(II11259,WX3101,II11257);
nand NAND2_2135(WX3697,II11258,II11259);
nand NAND2_2136(II11270,WX3182,WX3103);
nand NAND2_2137(II11271,WX3182,II11270);
nand NAND2_2138(II11272,WX3103,II11270);
nand NAND2_2139(WX3704,II11271,II11272);
nand NAND2_2140(II11283,WX3183,WX3105);
nand NAND2_2141(II11284,WX3183,II11283);
nand NAND2_2142(II11285,WX3105,II11283);
nand NAND2_2143(WX3711,II11284,II11285);
nand NAND2_2144(II11296,WX3184,WX3107);
nand NAND2_2145(II11297,WX3184,II11296);
nand NAND2_2146(II11298,WX3107,II11296);
nand NAND2_2147(WX3718,II11297,II11298);
nand NAND2_2148(II11309,WX3185,WX3109);
nand NAND2_2149(II11310,WX3185,II11309);
nand NAND2_2150(II11311,WX3109,II11309);
nand NAND2_2151(WX3725,II11310,II11311);
nand NAND2_2152(II11322,WX3186,WX3111);
nand NAND2_2153(II11323,WX3186,II11322);
nand NAND2_2154(II11324,WX3111,II11322);
nand NAND2_2155(WX3732,II11323,II11324);
nand NAND2_2156(II11335,WX3187,WX3113);
nand NAND2_2157(II11336,WX3187,II11335);
nand NAND2_2158(II11337,WX3113,II11335);
nand NAND2_2159(WX3739,II11336,II11337);
nand NAND2_2160(II11348,WX3188,WX3115);
nand NAND2_2161(II11349,WX3188,II11348);
nand NAND2_2162(II11350,WX3115,II11348);
nand NAND2_2163(WX3746,II11349,II11350);
nand NAND2_2164(II11361,WX3189,WX3117);
nand NAND2_2165(II11362,WX3189,II11361);
nand NAND2_2166(II11363,WX3117,II11361);
nand NAND2_2167(WX3753,II11362,II11363);
nand NAND2_2168(II11374,WX3190,WX3119);
nand NAND2_2169(II11375,WX3190,II11374);
nand NAND2_2170(II11376,WX3119,II11374);
nand NAND2_2171(WX3760,II11375,II11376);
nand NAND2_2172(II11387,WX3191,WX3121);
nand NAND2_2173(II11388,WX3191,II11387);
nand NAND2_2174(II11389,WX3121,II11387);
nand NAND2_2175(WX3767,II11388,II11389);
nand NAND2_2176(II11400,WX3192,WX3123);
nand NAND2_2177(II11401,WX3192,II11400);
nand NAND2_2178(II11402,WX3123,II11400);
nand NAND2_2179(WX3774,II11401,II11402);
nand NAND2_2180(II11413,WX3193,WX3125);
nand NAND2_2181(II11414,WX3193,II11413);
nand NAND2_2182(II11415,WX3125,II11413);
nand NAND2_2183(WX3781,II11414,II11415);
nand NAND2_2184(II11426,WX3194,WX3127);
nand NAND2_2185(II11427,WX3194,II11426);
nand NAND2_2186(II11428,WX3127,II11426);
nand NAND2_2187(WX3788,II11427,II11428);
nand NAND2_2188(II11439,WX3195,WX3129);
nand NAND2_2189(II11440,WX3195,II11439);
nand NAND2_2190(II11441,WX3129,II11439);
nand NAND2_2191(WX3795,II11440,II11441);
nand NAND2_2192(II11452,WX3196,WX3131);
nand NAND2_2193(II11453,WX3196,II11452);
nand NAND2_2194(II11454,WX3131,II11452);
nand NAND2_2195(WX3802,II11453,II11454);
nand NAND2_2196(II11465,WX3197,WX3133);
nand NAND2_2197(II11466,WX3197,II11465);
nand NAND2_2198(II11467,WX3133,II11465);
nand NAND2_2199(WX3809,II11466,II11467);
nand NAND2_2200(II11480,WX3213,CRC_OUT_7_31);
nand NAND2_2201(II11481,WX3213,II11480);
nand NAND2_2202(II11482,CRC_OUT_7_31,II11480);
nand NAND2_2203(II11479,II11481,II11482);
nand NAND2_2204(II11487,CRC_OUT_7_15,II11479);
nand NAND2_2205(II11488,CRC_OUT_7_15,II11487);
nand NAND2_2206(II11489,II11479,II11487);
nand NAND2_2207(WX3817,II11488,II11489);
nand NAND2_2208(II11495,WX3218,CRC_OUT_7_31);
nand NAND2_2209(II11496,WX3218,II11495);
nand NAND2_2210(II11497,CRC_OUT_7_31,II11495);
nand NAND2_2211(II11494,II11496,II11497);
nand NAND2_2212(II11502,CRC_OUT_7_10,II11494);
nand NAND2_2213(II11503,CRC_OUT_7_10,II11502);
nand NAND2_2214(II11504,II11494,II11502);
nand NAND2_2215(WX3818,II11503,II11504);
nand NAND2_2216(II11510,WX3225,CRC_OUT_7_31);
nand NAND2_2217(II11511,WX3225,II11510);
nand NAND2_2218(II11512,CRC_OUT_7_31,II11510);
nand NAND2_2219(II11509,II11511,II11512);
nand NAND2_2220(II11517,CRC_OUT_7_3,II11509);
nand NAND2_2221(II11518,CRC_OUT_7_3,II11517);
nand NAND2_2222(II11519,II11509,II11517);
nand NAND2_2223(WX3819,II11518,II11519);
nand NAND2_2224(II11524,WX3229,CRC_OUT_7_31);
nand NAND2_2225(II11525,WX3229,II11524);
nand NAND2_2226(II11526,CRC_OUT_7_31,II11524);
nand NAND2_2227(WX3820,II11525,II11526);
nand NAND2_2228(II11531,WX3198,CRC_OUT_7_30);
nand NAND2_2229(II11532,WX3198,II11531);
nand NAND2_2230(II11533,CRC_OUT_7_30,II11531);
nand NAND2_2231(WX3821,II11532,II11533);
nand NAND2_2232(II11538,WX3199,CRC_OUT_7_29);
nand NAND2_2233(II11539,WX3199,II11538);
nand NAND2_2234(II11540,CRC_OUT_7_29,II11538);
nand NAND2_2235(WX3822,II11539,II11540);
nand NAND2_2236(II11545,WX3200,CRC_OUT_7_28);
nand NAND2_2237(II11546,WX3200,II11545);
nand NAND2_2238(II11547,CRC_OUT_7_28,II11545);
nand NAND2_2239(WX3823,II11546,II11547);
nand NAND2_2240(II11552,WX3201,CRC_OUT_7_27);
nand NAND2_2241(II11553,WX3201,II11552);
nand NAND2_2242(II11554,CRC_OUT_7_27,II11552);
nand NAND2_2243(WX3824,II11553,II11554);
nand NAND2_2244(II11559,WX3202,CRC_OUT_7_26);
nand NAND2_2245(II11560,WX3202,II11559);
nand NAND2_2246(II11561,CRC_OUT_7_26,II11559);
nand NAND2_2247(WX3825,II11560,II11561);
nand NAND2_2248(II11566,WX3203,CRC_OUT_7_25);
nand NAND2_2249(II11567,WX3203,II11566);
nand NAND2_2250(II11568,CRC_OUT_7_25,II11566);
nand NAND2_2251(WX3826,II11567,II11568);
nand NAND2_2252(II11573,WX3204,CRC_OUT_7_24);
nand NAND2_2253(II11574,WX3204,II11573);
nand NAND2_2254(II11575,CRC_OUT_7_24,II11573);
nand NAND2_2255(WX3827,II11574,II11575);
nand NAND2_2256(II11580,WX3205,CRC_OUT_7_23);
nand NAND2_2257(II11581,WX3205,II11580);
nand NAND2_2258(II11582,CRC_OUT_7_23,II11580);
nand NAND2_2259(WX3828,II11581,II11582);
nand NAND2_2260(II11587,WX3206,CRC_OUT_7_22);
nand NAND2_2261(II11588,WX3206,II11587);
nand NAND2_2262(II11589,CRC_OUT_7_22,II11587);
nand NAND2_2263(WX3829,II11588,II11589);
nand NAND2_2264(II11594,WX3207,CRC_OUT_7_21);
nand NAND2_2265(II11595,WX3207,II11594);
nand NAND2_2266(II11596,CRC_OUT_7_21,II11594);
nand NAND2_2267(WX3830,II11595,II11596);
nand NAND2_2268(II11601,WX3208,CRC_OUT_7_20);
nand NAND2_2269(II11602,WX3208,II11601);
nand NAND2_2270(II11603,CRC_OUT_7_20,II11601);
nand NAND2_2271(WX3831,II11602,II11603);
nand NAND2_2272(II11608,WX3209,CRC_OUT_7_19);
nand NAND2_2273(II11609,WX3209,II11608);
nand NAND2_2274(II11610,CRC_OUT_7_19,II11608);
nand NAND2_2275(WX3832,II11609,II11610);
nand NAND2_2276(II11615,WX3210,CRC_OUT_7_18);
nand NAND2_2277(II11616,WX3210,II11615);
nand NAND2_2278(II11617,CRC_OUT_7_18,II11615);
nand NAND2_2279(WX3833,II11616,II11617);
nand NAND2_2280(II11622,WX3211,CRC_OUT_7_17);
nand NAND2_2281(II11623,WX3211,II11622);
nand NAND2_2282(II11624,CRC_OUT_7_17,II11622);
nand NAND2_2283(WX3834,II11623,II11624);
nand NAND2_2284(II11629,WX3212,CRC_OUT_7_16);
nand NAND2_2285(II11630,WX3212,II11629);
nand NAND2_2286(II11631,CRC_OUT_7_16,II11629);
nand NAND2_2287(WX3835,II11630,II11631);
nand NAND2_2288(II11636,WX3214,CRC_OUT_7_14);
nand NAND2_2289(II11637,WX3214,II11636);
nand NAND2_2290(II11638,CRC_OUT_7_14,II11636);
nand NAND2_2291(WX3836,II11637,II11638);
nand NAND2_2292(II11643,WX3215,CRC_OUT_7_13);
nand NAND2_2293(II11644,WX3215,II11643);
nand NAND2_2294(II11645,CRC_OUT_7_13,II11643);
nand NAND2_2295(WX3837,II11644,II11645);
nand NAND2_2296(II11650,WX3216,CRC_OUT_7_12);
nand NAND2_2297(II11651,WX3216,II11650);
nand NAND2_2298(II11652,CRC_OUT_7_12,II11650);
nand NAND2_2299(WX3838,II11651,II11652);
nand NAND2_2300(II11657,WX3217,CRC_OUT_7_11);
nand NAND2_2301(II11658,WX3217,II11657);
nand NAND2_2302(II11659,CRC_OUT_7_11,II11657);
nand NAND2_2303(WX3839,II11658,II11659);
nand NAND2_2304(II11664,WX3219,CRC_OUT_7_9);
nand NAND2_2305(II11665,WX3219,II11664);
nand NAND2_2306(II11666,CRC_OUT_7_9,II11664);
nand NAND2_2307(WX3840,II11665,II11666);
nand NAND2_2308(II11671,WX3220,CRC_OUT_7_8);
nand NAND2_2309(II11672,WX3220,II11671);
nand NAND2_2310(II11673,CRC_OUT_7_8,II11671);
nand NAND2_2311(WX3841,II11672,II11673);
nand NAND2_2312(II11678,WX3221,CRC_OUT_7_7);
nand NAND2_2313(II11679,WX3221,II11678);
nand NAND2_2314(II11680,CRC_OUT_7_7,II11678);
nand NAND2_2315(WX3842,II11679,II11680);
nand NAND2_2316(II11685,WX3222,CRC_OUT_7_6);
nand NAND2_2317(II11686,WX3222,II11685);
nand NAND2_2318(II11687,CRC_OUT_7_6,II11685);
nand NAND2_2319(WX3843,II11686,II11687);
nand NAND2_2320(II11692,WX3223,CRC_OUT_7_5);
nand NAND2_2321(II11693,WX3223,II11692);
nand NAND2_2322(II11694,CRC_OUT_7_5,II11692);
nand NAND2_2323(WX3844,II11693,II11694);
nand NAND2_2324(II11699,WX3224,CRC_OUT_7_4);
nand NAND2_2325(II11700,WX3224,II11699);
nand NAND2_2326(II11701,CRC_OUT_7_4,II11699);
nand NAND2_2327(WX3845,II11700,II11701);
nand NAND2_2328(II11706,WX3226,CRC_OUT_7_2);
nand NAND2_2329(II11707,WX3226,II11706);
nand NAND2_2330(II11708,CRC_OUT_7_2,II11706);
nand NAND2_2331(WX3846,II11707,II11708);
nand NAND2_2332(II11713,WX3227,CRC_OUT_7_1);
nand NAND2_2333(II11714,WX3227,II11713);
nand NAND2_2334(II11715,CRC_OUT_7_1,II11713);
nand NAND2_2335(WX3847,II11714,II11715);
nand NAND2_2336(II11720,WX3228,CRC_OUT_7_0);
nand NAND2_2337(II11721,WX3228,II11720);
nand NAND2_2338(II11722,CRC_OUT_7_0,II11720);
nand NAND2_2339(WX3848,II11721,II11722);
nand NAND2_2340(II14003,WX4880,WX4524);
nand NAND2_2341(II14004,WX4880,II14003);
nand NAND2_2342(II14005,WX4524,II14003);
nand NAND2_2343(II14002,II14004,II14005);
nand NAND2_2344(II14010,WX4588,II14002);
nand NAND2_2345(II14011,WX4588,II14010);
nand NAND2_2346(II14012,II14002,II14010);
nand NAND2_2347(II14001,II14011,II14012);
nand NAND2_2348(II14018,WX4652,WX4716);
nand NAND2_2349(II14019,WX4652,II14018);
nand NAND2_2350(II14020,WX4716,II14018);
nand NAND2_2351(II14017,II14019,II14020);
nand NAND2_2352(II14025,II14001,II14017);
nand NAND2_2353(II14026,II14001,II14025);
nand NAND2_2354(II14027,II14017,II14025);
nand NAND2_2355(WX4779,II14026,II14027);
nand NAND2_2356(II14034,WX4880,WX4526);
nand NAND2_2357(II14035,WX4880,II14034);
nand NAND2_2358(II14036,WX4526,II14034);
nand NAND2_2359(II14033,II14035,II14036);
nand NAND2_2360(II14041,WX4590,II14033);
nand NAND2_2361(II14042,WX4590,II14041);
nand NAND2_2362(II14043,II14033,II14041);
nand NAND2_2363(II14032,II14042,II14043);
nand NAND2_2364(II14049,WX4654,WX4718);
nand NAND2_2365(II14050,WX4654,II14049);
nand NAND2_2366(II14051,WX4718,II14049);
nand NAND2_2367(II14048,II14050,II14051);
nand NAND2_2368(II14056,II14032,II14048);
nand NAND2_2369(II14057,II14032,II14056);
nand NAND2_2370(II14058,II14048,II14056);
nand NAND2_2371(WX4780,II14057,II14058);
nand NAND2_2372(II14065,WX4880,WX4528);
nand NAND2_2373(II14066,WX4880,II14065);
nand NAND2_2374(II14067,WX4528,II14065);
nand NAND2_2375(II14064,II14066,II14067);
nand NAND2_2376(II14072,WX4592,II14064);
nand NAND2_2377(II14073,WX4592,II14072);
nand NAND2_2378(II14074,II14064,II14072);
nand NAND2_2379(II14063,II14073,II14074);
nand NAND2_2380(II14080,WX4656,WX4720);
nand NAND2_2381(II14081,WX4656,II14080);
nand NAND2_2382(II14082,WX4720,II14080);
nand NAND2_2383(II14079,II14081,II14082);
nand NAND2_2384(II14087,II14063,II14079);
nand NAND2_2385(II14088,II14063,II14087);
nand NAND2_2386(II14089,II14079,II14087);
nand NAND2_2387(WX4781,II14088,II14089);
nand NAND2_2388(II14096,WX4880,WX4530);
nand NAND2_2389(II14097,WX4880,II14096);
nand NAND2_2390(II14098,WX4530,II14096);
nand NAND2_2391(II14095,II14097,II14098);
nand NAND2_2392(II14103,WX4594,II14095);
nand NAND2_2393(II14104,WX4594,II14103);
nand NAND2_2394(II14105,II14095,II14103);
nand NAND2_2395(II14094,II14104,II14105);
nand NAND2_2396(II14111,WX4658,WX4722);
nand NAND2_2397(II14112,WX4658,II14111);
nand NAND2_2398(II14113,WX4722,II14111);
nand NAND2_2399(II14110,II14112,II14113);
nand NAND2_2400(II14118,II14094,II14110);
nand NAND2_2401(II14119,II14094,II14118);
nand NAND2_2402(II14120,II14110,II14118);
nand NAND2_2403(WX4782,II14119,II14120);
nand NAND2_2404(II14127,WX4880,WX4532);
nand NAND2_2405(II14128,WX4880,II14127);
nand NAND2_2406(II14129,WX4532,II14127);
nand NAND2_2407(II14126,II14128,II14129);
nand NAND2_2408(II14134,WX4596,II14126);
nand NAND2_2409(II14135,WX4596,II14134);
nand NAND2_2410(II14136,II14126,II14134);
nand NAND2_2411(II14125,II14135,II14136);
nand NAND2_2412(II14142,WX4660,WX4724);
nand NAND2_2413(II14143,WX4660,II14142);
nand NAND2_2414(II14144,WX4724,II14142);
nand NAND2_2415(II14141,II14143,II14144);
nand NAND2_2416(II14149,II14125,II14141);
nand NAND2_2417(II14150,II14125,II14149);
nand NAND2_2418(II14151,II14141,II14149);
nand NAND2_2419(WX4783,II14150,II14151);
nand NAND2_2420(II14158,WX4880,WX4534);
nand NAND2_2421(II14159,WX4880,II14158);
nand NAND2_2422(II14160,WX4534,II14158);
nand NAND2_2423(II14157,II14159,II14160);
nand NAND2_2424(II14165,WX4598,II14157);
nand NAND2_2425(II14166,WX4598,II14165);
nand NAND2_2426(II14167,II14157,II14165);
nand NAND2_2427(II14156,II14166,II14167);
nand NAND2_2428(II14173,WX4662,WX4726);
nand NAND2_2429(II14174,WX4662,II14173);
nand NAND2_2430(II14175,WX4726,II14173);
nand NAND2_2431(II14172,II14174,II14175);
nand NAND2_2432(II14180,II14156,II14172);
nand NAND2_2433(II14181,II14156,II14180);
nand NAND2_2434(II14182,II14172,II14180);
nand NAND2_2435(WX4784,II14181,II14182);
nand NAND2_2436(II14189,WX4880,WX4536);
nand NAND2_2437(II14190,WX4880,II14189);
nand NAND2_2438(II14191,WX4536,II14189);
nand NAND2_2439(II14188,II14190,II14191);
nand NAND2_2440(II14196,WX4600,II14188);
nand NAND2_2441(II14197,WX4600,II14196);
nand NAND2_2442(II14198,II14188,II14196);
nand NAND2_2443(II14187,II14197,II14198);
nand NAND2_2444(II14204,WX4664,WX4728);
nand NAND2_2445(II14205,WX4664,II14204);
nand NAND2_2446(II14206,WX4728,II14204);
nand NAND2_2447(II14203,II14205,II14206);
nand NAND2_2448(II14211,II14187,II14203);
nand NAND2_2449(II14212,II14187,II14211);
nand NAND2_2450(II14213,II14203,II14211);
nand NAND2_2451(WX4785,II14212,II14213);
nand NAND2_2452(II14220,WX4880,WX4538);
nand NAND2_2453(II14221,WX4880,II14220);
nand NAND2_2454(II14222,WX4538,II14220);
nand NAND2_2455(II14219,II14221,II14222);
nand NAND2_2456(II14227,WX4602,II14219);
nand NAND2_2457(II14228,WX4602,II14227);
nand NAND2_2458(II14229,II14219,II14227);
nand NAND2_2459(II14218,II14228,II14229);
nand NAND2_2460(II14235,WX4666,WX4730);
nand NAND2_2461(II14236,WX4666,II14235);
nand NAND2_2462(II14237,WX4730,II14235);
nand NAND2_2463(II14234,II14236,II14237);
nand NAND2_2464(II14242,II14218,II14234);
nand NAND2_2465(II14243,II14218,II14242);
nand NAND2_2466(II14244,II14234,II14242);
nand NAND2_2467(WX4786,II14243,II14244);
nand NAND2_2468(II14251,WX4880,WX4540);
nand NAND2_2469(II14252,WX4880,II14251);
nand NAND2_2470(II14253,WX4540,II14251);
nand NAND2_2471(II14250,II14252,II14253);
nand NAND2_2472(II14258,WX4604,II14250);
nand NAND2_2473(II14259,WX4604,II14258);
nand NAND2_2474(II14260,II14250,II14258);
nand NAND2_2475(II14249,II14259,II14260);
nand NAND2_2476(II14266,WX4668,WX4732);
nand NAND2_2477(II14267,WX4668,II14266);
nand NAND2_2478(II14268,WX4732,II14266);
nand NAND2_2479(II14265,II14267,II14268);
nand NAND2_2480(II14273,II14249,II14265);
nand NAND2_2481(II14274,II14249,II14273);
nand NAND2_2482(II14275,II14265,II14273);
nand NAND2_2483(WX4787,II14274,II14275);
nand NAND2_2484(II14282,WX4880,WX4542);
nand NAND2_2485(II14283,WX4880,II14282);
nand NAND2_2486(II14284,WX4542,II14282);
nand NAND2_2487(II14281,II14283,II14284);
nand NAND2_2488(II14289,WX4606,II14281);
nand NAND2_2489(II14290,WX4606,II14289);
nand NAND2_2490(II14291,II14281,II14289);
nand NAND2_2491(II14280,II14290,II14291);
nand NAND2_2492(II14297,WX4670,WX4734);
nand NAND2_2493(II14298,WX4670,II14297);
nand NAND2_2494(II14299,WX4734,II14297);
nand NAND2_2495(II14296,II14298,II14299);
nand NAND2_2496(II14304,II14280,II14296);
nand NAND2_2497(II14305,II14280,II14304);
nand NAND2_2498(II14306,II14296,II14304);
nand NAND2_2499(WX4788,II14305,II14306);
nand NAND2_2500(II14313,WX4880,WX4544);
nand NAND2_2501(II14314,WX4880,II14313);
nand NAND2_2502(II14315,WX4544,II14313);
nand NAND2_2503(II14312,II14314,II14315);
nand NAND2_2504(II14320,WX4608,II14312);
nand NAND2_2505(II14321,WX4608,II14320);
nand NAND2_2506(II14322,II14312,II14320);
nand NAND2_2507(II14311,II14321,II14322);
nand NAND2_2508(II14328,WX4672,WX4736);
nand NAND2_2509(II14329,WX4672,II14328);
nand NAND2_2510(II14330,WX4736,II14328);
nand NAND2_2511(II14327,II14329,II14330);
nand NAND2_2512(II14335,II14311,II14327);
nand NAND2_2513(II14336,II14311,II14335);
nand NAND2_2514(II14337,II14327,II14335);
nand NAND2_2515(WX4789,II14336,II14337);
nand NAND2_2516(II14344,WX4880,WX4546);
nand NAND2_2517(II14345,WX4880,II14344);
nand NAND2_2518(II14346,WX4546,II14344);
nand NAND2_2519(II14343,II14345,II14346);
nand NAND2_2520(II14351,WX4610,II14343);
nand NAND2_2521(II14352,WX4610,II14351);
nand NAND2_2522(II14353,II14343,II14351);
nand NAND2_2523(II14342,II14352,II14353);
nand NAND2_2524(II14359,WX4674,WX4738);
nand NAND2_2525(II14360,WX4674,II14359);
nand NAND2_2526(II14361,WX4738,II14359);
nand NAND2_2527(II14358,II14360,II14361);
nand NAND2_2528(II14366,II14342,II14358);
nand NAND2_2529(II14367,II14342,II14366);
nand NAND2_2530(II14368,II14358,II14366);
nand NAND2_2531(WX4790,II14367,II14368);
nand NAND2_2532(II14375,WX4880,WX4548);
nand NAND2_2533(II14376,WX4880,II14375);
nand NAND2_2534(II14377,WX4548,II14375);
nand NAND2_2535(II14374,II14376,II14377);
nand NAND2_2536(II14382,WX4612,II14374);
nand NAND2_2537(II14383,WX4612,II14382);
nand NAND2_2538(II14384,II14374,II14382);
nand NAND2_2539(II14373,II14383,II14384);
nand NAND2_2540(II14390,WX4676,WX4740);
nand NAND2_2541(II14391,WX4676,II14390);
nand NAND2_2542(II14392,WX4740,II14390);
nand NAND2_2543(II14389,II14391,II14392);
nand NAND2_2544(II14397,II14373,II14389);
nand NAND2_2545(II14398,II14373,II14397);
nand NAND2_2546(II14399,II14389,II14397);
nand NAND2_2547(WX4791,II14398,II14399);
nand NAND2_2548(II14406,WX4880,WX4550);
nand NAND2_2549(II14407,WX4880,II14406);
nand NAND2_2550(II14408,WX4550,II14406);
nand NAND2_2551(II14405,II14407,II14408);
nand NAND2_2552(II14413,WX4614,II14405);
nand NAND2_2553(II14414,WX4614,II14413);
nand NAND2_2554(II14415,II14405,II14413);
nand NAND2_2555(II14404,II14414,II14415);
nand NAND2_2556(II14421,WX4678,WX4742);
nand NAND2_2557(II14422,WX4678,II14421);
nand NAND2_2558(II14423,WX4742,II14421);
nand NAND2_2559(II14420,II14422,II14423);
nand NAND2_2560(II14428,II14404,II14420);
nand NAND2_2561(II14429,II14404,II14428);
nand NAND2_2562(II14430,II14420,II14428);
nand NAND2_2563(WX4792,II14429,II14430);
nand NAND2_2564(II14437,WX4880,WX4552);
nand NAND2_2565(II14438,WX4880,II14437);
nand NAND2_2566(II14439,WX4552,II14437);
nand NAND2_2567(II14436,II14438,II14439);
nand NAND2_2568(II14444,WX4616,II14436);
nand NAND2_2569(II14445,WX4616,II14444);
nand NAND2_2570(II14446,II14436,II14444);
nand NAND2_2571(II14435,II14445,II14446);
nand NAND2_2572(II14452,WX4680,WX4744);
nand NAND2_2573(II14453,WX4680,II14452);
nand NAND2_2574(II14454,WX4744,II14452);
nand NAND2_2575(II14451,II14453,II14454);
nand NAND2_2576(II14459,II14435,II14451);
nand NAND2_2577(II14460,II14435,II14459);
nand NAND2_2578(II14461,II14451,II14459);
nand NAND2_2579(WX4793,II14460,II14461);
nand NAND2_2580(II14468,WX4880,WX4554);
nand NAND2_2581(II14469,WX4880,II14468);
nand NAND2_2582(II14470,WX4554,II14468);
nand NAND2_2583(II14467,II14469,II14470);
nand NAND2_2584(II14475,WX4618,II14467);
nand NAND2_2585(II14476,WX4618,II14475);
nand NAND2_2586(II14477,II14467,II14475);
nand NAND2_2587(II14466,II14476,II14477);
nand NAND2_2588(II14483,WX4682,WX4746);
nand NAND2_2589(II14484,WX4682,II14483);
nand NAND2_2590(II14485,WX4746,II14483);
nand NAND2_2591(II14482,II14484,II14485);
nand NAND2_2592(II14490,II14466,II14482);
nand NAND2_2593(II14491,II14466,II14490);
nand NAND2_2594(II14492,II14482,II14490);
nand NAND2_2595(WX4794,II14491,II14492);
nand NAND2_2596(II14499,WX4881,WX4556);
nand NAND2_2597(II14500,WX4881,II14499);
nand NAND2_2598(II14501,WX4556,II14499);
nand NAND2_2599(II14498,II14500,II14501);
nand NAND2_2600(II14506,WX4620,II14498);
nand NAND2_2601(II14507,WX4620,II14506);
nand NAND2_2602(II14508,II14498,II14506);
nand NAND2_2603(II14497,II14507,II14508);
nand NAND2_2604(II14514,WX4684,WX4748);
nand NAND2_2605(II14515,WX4684,II14514);
nand NAND2_2606(II14516,WX4748,II14514);
nand NAND2_2607(II14513,II14515,II14516);
nand NAND2_2608(II14521,II14497,II14513);
nand NAND2_2609(II14522,II14497,II14521);
nand NAND2_2610(II14523,II14513,II14521);
nand NAND2_2611(WX4795,II14522,II14523);
nand NAND2_2612(II14530,WX4881,WX4558);
nand NAND2_2613(II14531,WX4881,II14530);
nand NAND2_2614(II14532,WX4558,II14530);
nand NAND2_2615(II14529,II14531,II14532);
nand NAND2_2616(II14537,WX4622,II14529);
nand NAND2_2617(II14538,WX4622,II14537);
nand NAND2_2618(II14539,II14529,II14537);
nand NAND2_2619(II14528,II14538,II14539);
nand NAND2_2620(II14545,WX4686,WX4750);
nand NAND2_2621(II14546,WX4686,II14545);
nand NAND2_2622(II14547,WX4750,II14545);
nand NAND2_2623(II14544,II14546,II14547);
nand NAND2_2624(II14552,II14528,II14544);
nand NAND2_2625(II14553,II14528,II14552);
nand NAND2_2626(II14554,II14544,II14552);
nand NAND2_2627(WX4796,II14553,II14554);
nand NAND2_2628(II14561,WX4881,WX4560);
nand NAND2_2629(II14562,WX4881,II14561);
nand NAND2_2630(II14563,WX4560,II14561);
nand NAND2_2631(II14560,II14562,II14563);
nand NAND2_2632(II14568,WX4624,II14560);
nand NAND2_2633(II14569,WX4624,II14568);
nand NAND2_2634(II14570,II14560,II14568);
nand NAND2_2635(II14559,II14569,II14570);
nand NAND2_2636(II14576,WX4688,WX4752);
nand NAND2_2637(II14577,WX4688,II14576);
nand NAND2_2638(II14578,WX4752,II14576);
nand NAND2_2639(II14575,II14577,II14578);
nand NAND2_2640(II14583,II14559,II14575);
nand NAND2_2641(II14584,II14559,II14583);
nand NAND2_2642(II14585,II14575,II14583);
nand NAND2_2643(WX4797,II14584,II14585);
nand NAND2_2644(II14592,WX4881,WX4562);
nand NAND2_2645(II14593,WX4881,II14592);
nand NAND2_2646(II14594,WX4562,II14592);
nand NAND2_2647(II14591,II14593,II14594);
nand NAND2_2648(II14599,WX4626,II14591);
nand NAND2_2649(II14600,WX4626,II14599);
nand NAND2_2650(II14601,II14591,II14599);
nand NAND2_2651(II14590,II14600,II14601);
nand NAND2_2652(II14607,WX4690,WX4754);
nand NAND2_2653(II14608,WX4690,II14607);
nand NAND2_2654(II14609,WX4754,II14607);
nand NAND2_2655(II14606,II14608,II14609);
nand NAND2_2656(II14614,II14590,II14606);
nand NAND2_2657(II14615,II14590,II14614);
nand NAND2_2658(II14616,II14606,II14614);
nand NAND2_2659(WX4798,II14615,II14616);
nand NAND2_2660(II14623,WX4881,WX4564);
nand NAND2_2661(II14624,WX4881,II14623);
nand NAND2_2662(II14625,WX4564,II14623);
nand NAND2_2663(II14622,II14624,II14625);
nand NAND2_2664(II14630,WX4628,II14622);
nand NAND2_2665(II14631,WX4628,II14630);
nand NAND2_2666(II14632,II14622,II14630);
nand NAND2_2667(II14621,II14631,II14632);
nand NAND2_2668(II14638,WX4692,WX4756);
nand NAND2_2669(II14639,WX4692,II14638);
nand NAND2_2670(II14640,WX4756,II14638);
nand NAND2_2671(II14637,II14639,II14640);
nand NAND2_2672(II14645,II14621,II14637);
nand NAND2_2673(II14646,II14621,II14645);
nand NAND2_2674(II14647,II14637,II14645);
nand NAND2_2675(WX4799,II14646,II14647);
nand NAND2_2676(II14654,WX4881,WX4566);
nand NAND2_2677(II14655,WX4881,II14654);
nand NAND2_2678(II14656,WX4566,II14654);
nand NAND2_2679(II14653,II14655,II14656);
nand NAND2_2680(II14661,WX4630,II14653);
nand NAND2_2681(II14662,WX4630,II14661);
nand NAND2_2682(II14663,II14653,II14661);
nand NAND2_2683(II14652,II14662,II14663);
nand NAND2_2684(II14669,WX4694,WX4758);
nand NAND2_2685(II14670,WX4694,II14669);
nand NAND2_2686(II14671,WX4758,II14669);
nand NAND2_2687(II14668,II14670,II14671);
nand NAND2_2688(II14676,II14652,II14668);
nand NAND2_2689(II14677,II14652,II14676);
nand NAND2_2690(II14678,II14668,II14676);
nand NAND2_2691(WX4800,II14677,II14678);
nand NAND2_2692(II14685,WX4881,WX4568);
nand NAND2_2693(II14686,WX4881,II14685);
nand NAND2_2694(II14687,WX4568,II14685);
nand NAND2_2695(II14684,II14686,II14687);
nand NAND2_2696(II14692,WX4632,II14684);
nand NAND2_2697(II14693,WX4632,II14692);
nand NAND2_2698(II14694,II14684,II14692);
nand NAND2_2699(II14683,II14693,II14694);
nand NAND2_2700(II14700,WX4696,WX4760);
nand NAND2_2701(II14701,WX4696,II14700);
nand NAND2_2702(II14702,WX4760,II14700);
nand NAND2_2703(II14699,II14701,II14702);
nand NAND2_2704(II14707,II14683,II14699);
nand NAND2_2705(II14708,II14683,II14707);
nand NAND2_2706(II14709,II14699,II14707);
nand NAND2_2707(WX4801,II14708,II14709);
nand NAND2_2708(II14716,WX4881,WX4570);
nand NAND2_2709(II14717,WX4881,II14716);
nand NAND2_2710(II14718,WX4570,II14716);
nand NAND2_2711(II14715,II14717,II14718);
nand NAND2_2712(II14723,WX4634,II14715);
nand NAND2_2713(II14724,WX4634,II14723);
nand NAND2_2714(II14725,II14715,II14723);
nand NAND2_2715(II14714,II14724,II14725);
nand NAND2_2716(II14731,WX4698,WX4762);
nand NAND2_2717(II14732,WX4698,II14731);
nand NAND2_2718(II14733,WX4762,II14731);
nand NAND2_2719(II14730,II14732,II14733);
nand NAND2_2720(II14738,II14714,II14730);
nand NAND2_2721(II14739,II14714,II14738);
nand NAND2_2722(II14740,II14730,II14738);
nand NAND2_2723(WX4802,II14739,II14740);
nand NAND2_2724(II14747,WX4881,WX4572);
nand NAND2_2725(II14748,WX4881,II14747);
nand NAND2_2726(II14749,WX4572,II14747);
nand NAND2_2727(II14746,II14748,II14749);
nand NAND2_2728(II14754,WX4636,II14746);
nand NAND2_2729(II14755,WX4636,II14754);
nand NAND2_2730(II14756,II14746,II14754);
nand NAND2_2731(II14745,II14755,II14756);
nand NAND2_2732(II14762,WX4700,WX4764);
nand NAND2_2733(II14763,WX4700,II14762);
nand NAND2_2734(II14764,WX4764,II14762);
nand NAND2_2735(II14761,II14763,II14764);
nand NAND2_2736(II14769,II14745,II14761);
nand NAND2_2737(II14770,II14745,II14769);
nand NAND2_2738(II14771,II14761,II14769);
nand NAND2_2739(WX4803,II14770,II14771);
nand NAND2_2740(II14778,WX4881,WX4574);
nand NAND2_2741(II14779,WX4881,II14778);
nand NAND2_2742(II14780,WX4574,II14778);
nand NAND2_2743(II14777,II14779,II14780);
nand NAND2_2744(II14785,WX4638,II14777);
nand NAND2_2745(II14786,WX4638,II14785);
nand NAND2_2746(II14787,II14777,II14785);
nand NAND2_2747(II14776,II14786,II14787);
nand NAND2_2748(II14793,WX4702,WX4766);
nand NAND2_2749(II14794,WX4702,II14793);
nand NAND2_2750(II14795,WX4766,II14793);
nand NAND2_2751(II14792,II14794,II14795);
nand NAND2_2752(II14800,II14776,II14792);
nand NAND2_2753(II14801,II14776,II14800);
nand NAND2_2754(II14802,II14792,II14800);
nand NAND2_2755(WX4804,II14801,II14802);
nand NAND2_2756(II14809,WX4881,WX4576);
nand NAND2_2757(II14810,WX4881,II14809);
nand NAND2_2758(II14811,WX4576,II14809);
nand NAND2_2759(II14808,II14810,II14811);
nand NAND2_2760(II14816,WX4640,II14808);
nand NAND2_2761(II14817,WX4640,II14816);
nand NAND2_2762(II14818,II14808,II14816);
nand NAND2_2763(II14807,II14817,II14818);
nand NAND2_2764(II14824,WX4704,WX4768);
nand NAND2_2765(II14825,WX4704,II14824);
nand NAND2_2766(II14826,WX4768,II14824);
nand NAND2_2767(II14823,II14825,II14826);
nand NAND2_2768(II14831,II14807,II14823);
nand NAND2_2769(II14832,II14807,II14831);
nand NAND2_2770(II14833,II14823,II14831);
nand NAND2_2771(WX4805,II14832,II14833);
nand NAND2_2772(II14840,WX4881,WX4578);
nand NAND2_2773(II14841,WX4881,II14840);
nand NAND2_2774(II14842,WX4578,II14840);
nand NAND2_2775(II14839,II14841,II14842);
nand NAND2_2776(II14847,WX4642,II14839);
nand NAND2_2777(II14848,WX4642,II14847);
nand NAND2_2778(II14849,II14839,II14847);
nand NAND2_2779(II14838,II14848,II14849);
nand NAND2_2780(II14855,WX4706,WX4770);
nand NAND2_2781(II14856,WX4706,II14855);
nand NAND2_2782(II14857,WX4770,II14855);
nand NAND2_2783(II14854,II14856,II14857);
nand NAND2_2784(II14862,II14838,II14854);
nand NAND2_2785(II14863,II14838,II14862);
nand NAND2_2786(II14864,II14854,II14862);
nand NAND2_2787(WX4806,II14863,II14864);
nand NAND2_2788(II14871,WX4881,WX4580);
nand NAND2_2789(II14872,WX4881,II14871);
nand NAND2_2790(II14873,WX4580,II14871);
nand NAND2_2791(II14870,II14872,II14873);
nand NAND2_2792(II14878,WX4644,II14870);
nand NAND2_2793(II14879,WX4644,II14878);
nand NAND2_2794(II14880,II14870,II14878);
nand NAND2_2795(II14869,II14879,II14880);
nand NAND2_2796(II14886,WX4708,WX4772);
nand NAND2_2797(II14887,WX4708,II14886);
nand NAND2_2798(II14888,WX4772,II14886);
nand NAND2_2799(II14885,II14887,II14888);
nand NAND2_2800(II14893,II14869,II14885);
nand NAND2_2801(II14894,II14869,II14893);
nand NAND2_2802(II14895,II14885,II14893);
nand NAND2_2803(WX4807,II14894,II14895);
nand NAND2_2804(II14902,WX4881,WX4582);
nand NAND2_2805(II14903,WX4881,II14902);
nand NAND2_2806(II14904,WX4582,II14902);
nand NAND2_2807(II14901,II14903,II14904);
nand NAND2_2808(II14909,WX4646,II14901);
nand NAND2_2809(II14910,WX4646,II14909);
nand NAND2_2810(II14911,II14901,II14909);
nand NAND2_2811(II14900,II14910,II14911);
nand NAND2_2812(II14917,WX4710,WX4774);
nand NAND2_2813(II14918,WX4710,II14917);
nand NAND2_2814(II14919,WX4774,II14917);
nand NAND2_2815(II14916,II14918,II14919);
nand NAND2_2816(II14924,II14900,II14916);
nand NAND2_2817(II14925,II14900,II14924);
nand NAND2_2818(II14926,II14916,II14924);
nand NAND2_2819(WX4808,II14925,II14926);
nand NAND2_2820(II14933,WX4881,WX4584);
nand NAND2_2821(II14934,WX4881,II14933);
nand NAND2_2822(II14935,WX4584,II14933);
nand NAND2_2823(II14932,II14934,II14935);
nand NAND2_2824(II14940,WX4648,II14932);
nand NAND2_2825(II14941,WX4648,II14940);
nand NAND2_2826(II14942,II14932,II14940);
nand NAND2_2827(II14931,II14941,II14942);
nand NAND2_2828(II14948,WX4712,WX4776);
nand NAND2_2829(II14949,WX4712,II14948);
nand NAND2_2830(II14950,WX4776,II14948);
nand NAND2_2831(II14947,II14949,II14950);
nand NAND2_2832(II14955,II14931,II14947);
nand NAND2_2833(II14956,II14931,II14955);
nand NAND2_2834(II14957,II14947,II14955);
nand NAND2_2835(WX4809,II14956,II14957);
nand NAND2_2836(II14964,WX4881,WX4586);
nand NAND2_2837(II14965,WX4881,II14964);
nand NAND2_2838(II14966,WX4586,II14964);
nand NAND2_2839(II14963,II14965,II14966);
nand NAND2_2840(II14971,WX4650,II14963);
nand NAND2_2841(II14972,WX4650,II14971);
nand NAND2_2842(II14973,II14963,II14971);
nand NAND2_2843(II14962,II14972,II14973);
nand NAND2_2844(II14979,WX4714,WX4778);
nand NAND2_2845(II14980,WX4714,II14979);
nand NAND2_2846(II14981,WX4778,II14979);
nand NAND2_2847(II14978,II14980,II14981);
nand NAND2_2848(II14986,II14962,II14978);
nand NAND2_2849(II14987,II14962,II14986);
nand NAND2_2850(II14988,II14978,II14986);
nand NAND2_2851(WX4810,II14987,II14988);
nand NAND2_2852(II15067,WX4459,WX4364);
nand NAND2_2853(II15068,WX4459,II15067);
nand NAND2_2854(II15069,WX4364,II15067);
nand NAND2_2855(WX4885,II15068,II15069);
nand NAND2_2856(II15080,WX4460,WX4366);
nand NAND2_2857(II15081,WX4460,II15080);
nand NAND2_2858(II15082,WX4366,II15080);
nand NAND2_2859(WX4892,II15081,II15082);
nand NAND2_2860(II15093,WX4461,WX4368);
nand NAND2_2861(II15094,WX4461,II15093);
nand NAND2_2862(II15095,WX4368,II15093);
nand NAND2_2863(WX4899,II15094,II15095);
nand NAND2_2864(II15106,WX4462,WX4370);
nand NAND2_2865(II15107,WX4462,II15106);
nand NAND2_2866(II15108,WX4370,II15106);
nand NAND2_2867(WX4906,II15107,II15108);
nand NAND2_2868(II15119,WX4463,WX4372);
nand NAND2_2869(II15120,WX4463,II15119);
nand NAND2_2870(II15121,WX4372,II15119);
nand NAND2_2871(WX4913,II15120,II15121);
nand NAND2_2872(II15132,WX4464,WX4374);
nand NAND2_2873(II15133,WX4464,II15132);
nand NAND2_2874(II15134,WX4374,II15132);
nand NAND2_2875(WX4920,II15133,II15134);
nand NAND2_2876(II15145,WX4465,WX4376);
nand NAND2_2877(II15146,WX4465,II15145);
nand NAND2_2878(II15147,WX4376,II15145);
nand NAND2_2879(WX4927,II15146,II15147);
nand NAND2_2880(II15158,WX4466,WX4378);
nand NAND2_2881(II15159,WX4466,II15158);
nand NAND2_2882(II15160,WX4378,II15158);
nand NAND2_2883(WX4934,II15159,II15160);
nand NAND2_2884(II15171,WX4467,WX4380);
nand NAND2_2885(II15172,WX4467,II15171);
nand NAND2_2886(II15173,WX4380,II15171);
nand NAND2_2887(WX4941,II15172,II15173);
nand NAND2_2888(II15184,WX4468,WX4382);
nand NAND2_2889(II15185,WX4468,II15184);
nand NAND2_2890(II15186,WX4382,II15184);
nand NAND2_2891(WX4948,II15185,II15186);
nand NAND2_2892(II15197,WX4469,WX4384);
nand NAND2_2893(II15198,WX4469,II15197);
nand NAND2_2894(II15199,WX4384,II15197);
nand NAND2_2895(WX4955,II15198,II15199);
nand NAND2_2896(II15210,WX4470,WX4386);
nand NAND2_2897(II15211,WX4470,II15210);
nand NAND2_2898(II15212,WX4386,II15210);
nand NAND2_2899(WX4962,II15211,II15212);
nand NAND2_2900(II15223,WX4471,WX4388);
nand NAND2_2901(II15224,WX4471,II15223);
nand NAND2_2902(II15225,WX4388,II15223);
nand NAND2_2903(WX4969,II15224,II15225);
nand NAND2_2904(II15236,WX4472,WX4390);
nand NAND2_2905(II15237,WX4472,II15236);
nand NAND2_2906(II15238,WX4390,II15236);
nand NAND2_2907(WX4976,II15237,II15238);
nand NAND2_2908(II15249,WX4473,WX4392);
nand NAND2_2909(II15250,WX4473,II15249);
nand NAND2_2910(II15251,WX4392,II15249);
nand NAND2_2911(WX4983,II15250,II15251);
nand NAND2_2912(II15262,WX4474,WX4394);
nand NAND2_2913(II15263,WX4474,II15262);
nand NAND2_2914(II15264,WX4394,II15262);
nand NAND2_2915(WX4990,II15263,II15264);
nand NAND2_2916(II15275,WX4475,WX4396);
nand NAND2_2917(II15276,WX4475,II15275);
nand NAND2_2918(II15277,WX4396,II15275);
nand NAND2_2919(WX4997,II15276,II15277);
nand NAND2_2920(II15288,WX4476,WX4398);
nand NAND2_2921(II15289,WX4476,II15288);
nand NAND2_2922(II15290,WX4398,II15288);
nand NAND2_2923(WX5004,II15289,II15290);
nand NAND2_2924(II15301,WX4477,WX4400);
nand NAND2_2925(II15302,WX4477,II15301);
nand NAND2_2926(II15303,WX4400,II15301);
nand NAND2_2927(WX5011,II15302,II15303);
nand NAND2_2928(II15314,WX4478,WX4402);
nand NAND2_2929(II15315,WX4478,II15314);
nand NAND2_2930(II15316,WX4402,II15314);
nand NAND2_2931(WX5018,II15315,II15316);
nand NAND2_2932(II15327,WX4479,WX4404);
nand NAND2_2933(II15328,WX4479,II15327);
nand NAND2_2934(II15329,WX4404,II15327);
nand NAND2_2935(WX5025,II15328,II15329);
nand NAND2_2936(II15340,WX4480,WX4406);
nand NAND2_2937(II15341,WX4480,II15340);
nand NAND2_2938(II15342,WX4406,II15340);
nand NAND2_2939(WX5032,II15341,II15342);
nand NAND2_2940(II15353,WX4481,WX4408);
nand NAND2_2941(II15354,WX4481,II15353);
nand NAND2_2942(II15355,WX4408,II15353);
nand NAND2_2943(WX5039,II15354,II15355);
nand NAND2_2944(II15366,WX4482,WX4410);
nand NAND2_2945(II15367,WX4482,II15366);
nand NAND2_2946(II15368,WX4410,II15366);
nand NAND2_2947(WX5046,II15367,II15368);
nand NAND2_2948(II15379,WX4483,WX4412);
nand NAND2_2949(II15380,WX4483,II15379);
nand NAND2_2950(II15381,WX4412,II15379);
nand NAND2_2951(WX5053,II15380,II15381);
nand NAND2_2952(II15392,WX4484,WX4414);
nand NAND2_2953(II15393,WX4484,II15392);
nand NAND2_2954(II15394,WX4414,II15392);
nand NAND2_2955(WX5060,II15393,II15394);
nand NAND2_2956(II15405,WX4485,WX4416);
nand NAND2_2957(II15406,WX4485,II15405);
nand NAND2_2958(II15407,WX4416,II15405);
nand NAND2_2959(WX5067,II15406,II15407);
nand NAND2_2960(II15418,WX4486,WX4418);
nand NAND2_2961(II15419,WX4486,II15418);
nand NAND2_2962(II15420,WX4418,II15418);
nand NAND2_2963(WX5074,II15419,II15420);
nand NAND2_2964(II15431,WX4487,WX4420);
nand NAND2_2965(II15432,WX4487,II15431);
nand NAND2_2966(II15433,WX4420,II15431);
nand NAND2_2967(WX5081,II15432,II15433);
nand NAND2_2968(II15444,WX4488,WX4422);
nand NAND2_2969(II15445,WX4488,II15444);
nand NAND2_2970(II15446,WX4422,II15444);
nand NAND2_2971(WX5088,II15445,II15446);
nand NAND2_2972(II15457,WX4489,WX4424);
nand NAND2_2973(II15458,WX4489,II15457);
nand NAND2_2974(II15459,WX4424,II15457);
nand NAND2_2975(WX5095,II15458,II15459);
nand NAND2_2976(II15470,WX4490,WX4426);
nand NAND2_2977(II15471,WX4490,II15470);
nand NAND2_2978(II15472,WX4426,II15470);
nand NAND2_2979(WX5102,II15471,II15472);
nand NAND2_2980(II15485,WX4506,CRC_OUT_6_31);
nand NAND2_2981(II15486,WX4506,II15485);
nand NAND2_2982(II15487,CRC_OUT_6_31,II15485);
nand NAND2_2983(II15484,II15486,II15487);
nand NAND2_2984(II15492,CRC_OUT_6_15,II15484);
nand NAND2_2985(II15493,CRC_OUT_6_15,II15492);
nand NAND2_2986(II15494,II15484,II15492);
nand NAND2_2987(WX5110,II15493,II15494);
nand NAND2_2988(II15500,WX4511,CRC_OUT_6_31);
nand NAND2_2989(II15501,WX4511,II15500);
nand NAND2_2990(II15502,CRC_OUT_6_31,II15500);
nand NAND2_2991(II15499,II15501,II15502);
nand NAND2_2992(II15507,CRC_OUT_6_10,II15499);
nand NAND2_2993(II15508,CRC_OUT_6_10,II15507);
nand NAND2_2994(II15509,II15499,II15507);
nand NAND2_2995(WX5111,II15508,II15509);
nand NAND2_2996(II15515,WX4518,CRC_OUT_6_31);
nand NAND2_2997(II15516,WX4518,II15515);
nand NAND2_2998(II15517,CRC_OUT_6_31,II15515);
nand NAND2_2999(II15514,II15516,II15517);
nand NAND2_3000(II15522,CRC_OUT_6_3,II15514);
nand NAND2_3001(II15523,CRC_OUT_6_3,II15522);
nand NAND2_3002(II15524,II15514,II15522);
nand NAND2_3003(WX5112,II15523,II15524);
nand NAND2_3004(II15529,WX4522,CRC_OUT_6_31);
nand NAND2_3005(II15530,WX4522,II15529);
nand NAND2_3006(II15531,CRC_OUT_6_31,II15529);
nand NAND2_3007(WX5113,II15530,II15531);
nand NAND2_3008(II15536,WX4491,CRC_OUT_6_30);
nand NAND2_3009(II15537,WX4491,II15536);
nand NAND2_3010(II15538,CRC_OUT_6_30,II15536);
nand NAND2_3011(WX5114,II15537,II15538);
nand NAND2_3012(II15543,WX4492,CRC_OUT_6_29);
nand NAND2_3013(II15544,WX4492,II15543);
nand NAND2_3014(II15545,CRC_OUT_6_29,II15543);
nand NAND2_3015(WX5115,II15544,II15545);
nand NAND2_3016(II15550,WX4493,CRC_OUT_6_28);
nand NAND2_3017(II15551,WX4493,II15550);
nand NAND2_3018(II15552,CRC_OUT_6_28,II15550);
nand NAND2_3019(WX5116,II15551,II15552);
nand NAND2_3020(II15557,WX4494,CRC_OUT_6_27);
nand NAND2_3021(II15558,WX4494,II15557);
nand NAND2_3022(II15559,CRC_OUT_6_27,II15557);
nand NAND2_3023(WX5117,II15558,II15559);
nand NAND2_3024(II15564,WX4495,CRC_OUT_6_26);
nand NAND2_3025(II15565,WX4495,II15564);
nand NAND2_3026(II15566,CRC_OUT_6_26,II15564);
nand NAND2_3027(WX5118,II15565,II15566);
nand NAND2_3028(II15571,WX4496,CRC_OUT_6_25);
nand NAND2_3029(II15572,WX4496,II15571);
nand NAND2_3030(II15573,CRC_OUT_6_25,II15571);
nand NAND2_3031(WX5119,II15572,II15573);
nand NAND2_3032(II15578,WX4497,CRC_OUT_6_24);
nand NAND2_3033(II15579,WX4497,II15578);
nand NAND2_3034(II15580,CRC_OUT_6_24,II15578);
nand NAND2_3035(WX5120,II15579,II15580);
nand NAND2_3036(II15585,WX4498,CRC_OUT_6_23);
nand NAND2_3037(II15586,WX4498,II15585);
nand NAND2_3038(II15587,CRC_OUT_6_23,II15585);
nand NAND2_3039(WX5121,II15586,II15587);
nand NAND2_3040(II15592,WX4499,CRC_OUT_6_22);
nand NAND2_3041(II15593,WX4499,II15592);
nand NAND2_3042(II15594,CRC_OUT_6_22,II15592);
nand NAND2_3043(WX5122,II15593,II15594);
nand NAND2_3044(II15599,WX4500,CRC_OUT_6_21);
nand NAND2_3045(II15600,WX4500,II15599);
nand NAND2_3046(II15601,CRC_OUT_6_21,II15599);
nand NAND2_3047(WX5123,II15600,II15601);
nand NAND2_3048(II15606,WX4501,CRC_OUT_6_20);
nand NAND2_3049(II15607,WX4501,II15606);
nand NAND2_3050(II15608,CRC_OUT_6_20,II15606);
nand NAND2_3051(WX5124,II15607,II15608);
nand NAND2_3052(II15613,WX4502,CRC_OUT_6_19);
nand NAND2_3053(II15614,WX4502,II15613);
nand NAND2_3054(II15615,CRC_OUT_6_19,II15613);
nand NAND2_3055(WX5125,II15614,II15615);
nand NAND2_3056(II15620,WX4503,CRC_OUT_6_18);
nand NAND2_3057(II15621,WX4503,II15620);
nand NAND2_3058(II15622,CRC_OUT_6_18,II15620);
nand NAND2_3059(WX5126,II15621,II15622);
nand NAND2_3060(II15627,WX4504,CRC_OUT_6_17);
nand NAND2_3061(II15628,WX4504,II15627);
nand NAND2_3062(II15629,CRC_OUT_6_17,II15627);
nand NAND2_3063(WX5127,II15628,II15629);
nand NAND2_3064(II15634,WX4505,CRC_OUT_6_16);
nand NAND2_3065(II15635,WX4505,II15634);
nand NAND2_3066(II15636,CRC_OUT_6_16,II15634);
nand NAND2_3067(WX5128,II15635,II15636);
nand NAND2_3068(II15641,WX4507,CRC_OUT_6_14);
nand NAND2_3069(II15642,WX4507,II15641);
nand NAND2_3070(II15643,CRC_OUT_6_14,II15641);
nand NAND2_3071(WX5129,II15642,II15643);
nand NAND2_3072(II15648,WX4508,CRC_OUT_6_13);
nand NAND2_3073(II15649,WX4508,II15648);
nand NAND2_3074(II15650,CRC_OUT_6_13,II15648);
nand NAND2_3075(WX5130,II15649,II15650);
nand NAND2_3076(II15655,WX4509,CRC_OUT_6_12);
nand NAND2_3077(II15656,WX4509,II15655);
nand NAND2_3078(II15657,CRC_OUT_6_12,II15655);
nand NAND2_3079(WX5131,II15656,II15657);
nand NAND2_3080(II15662,WX4510,CRC_OUT_6_11);
nand NAND2_3081(II15663,WX4510,II15662);
nand NAND2_3082(II15664,CRC_OUT_6_11,II15662);
nand NAND2_3083(WX5132,II15663,II15664);
nand NAND2_3084(II15669,WX4512,CRC_OUT_6_9);
nand NAND2_3085(II15670,WX4512,II15669);
nand NAND2_3086(II15671,CRC_OUT_6_9,II15669);
nand NAND2_3087(WX5133,II15670,II15671);
nand NAND2_3088(II15676,WX4513,CRC_OUT_6_8);
nand NAND2_3089(II15677,WX4513,II15676);
nand NAND2_3090(II15678,CRC_OUT_6_8,II15676);
nand NAND2_3091(WX5134,II15677,II15678);
nand NAND2_3092(II15683,WX4514,CRC_OUT_6_7);
nand NAND2_3093(II15684,WX4514,II15683);
nand NAND2_3094(II15685,CRC_OUT_6_7,II15683);
nand NAND2_3095(WX5135,II15684,II15685);
nand NAND2_3096(II15690,WX4515,CRC_OUT_6_6);
nand NAND2_3097(II15691,WX4515,II15690);
nand NAND2_3098(II15692,CRC_OUT_6_6,II15690);
nand NAND2_3099(WX5136,II15691,II15692);
nand NAND2_3100(II15697,WX4516,CRC_OUT_6_5);
nand NAND2_3101(II15698,WX4516,II15697);
nand NAND2_3102(II15699,CRC_OUT_6_5,II15697);
nand NAND2_3103(WX5137,II15698,II15699);
nand NAND2_3104(II15704,WX4517,CRC_OUT_6_4);
nand NAND2_3105(II15705,WX4517,II15704);
nand NAND2_3106(II15706,CRC_OUT_6_4,II15704);
nand NAND2_3107(WX5138,II15705,II15706);
nand NAND2_3108(II15711,WX4519,CRC_OUT_6_2);
nand NAND2_3109(II15712,WX4519,II15711);
nand NAND2_3110(II15713,CRC_OUT_6_2,II15711);
nand NAND2_3111(WX5139,II15712,II15713);
nand NAND2_3112(II15718,WX4520,CRC_OUT_6_1);
nand NAND2_3113(II15719,WX4520,II15718);
nand NAND2_3114(II15720,CRC_OUT_6_1,II15718);
nand NAND2_3115(WX5140,II15719,II15720);
nand NAND2_3116(II15725,WX4521,CRC_OUT_6_0);
nand NAND2_3117(II15726,WX4521,II15725);
nand NAND2_3118(II15727,CRC_OUT_6_0,II15725);
nand NAND2_3119(WX5141,II15726,II15727);
nand NAND2_3120(II18008,WX6173,WX5817);
nand NAND2_3121(II18009,WX6173,II18008);
nand NAND2_3122(II18010,WX5817,II18008);
nand NAND2_3123(II18007,II18009,II18010);
nand NAND2_3124(II18015,WX5881,II18007);
nand NAND2_3125(II18016,WX5881,II18015);
nand NAND2_3126(II18017,II18007,II18015);
nand NAND2_3127(II18006,II18016,II18017);
nand NAND2_3128(II18023,WX5945,WX6009);
nand NAND2_3129(II18024,WX5945,II18023);
nand NAND2_3130(II18025,WX6009,II18023);
nand NAND2_3131(II18022,II18024,II18025);
nand NAND2_3132(II18030,II18006,II18022);
nand NAND2_3133(II18031,II18006,II18030);
nand NAND2_3134(II18032,II18022,II18030);
nand NAND2_3135(WX6072,II18031,II18032);
nand NAND2_3136(II18039,WX6173,WX5819);
nand NAND2_3137(II18040,WX6173,II18039);
nand NAND2_3138(II18041,WX5819,II18039);
nand NAND2_3139(II18038,II18040,II18041);
nand NAND2_3140(II18046,WX5883,II18038);
nand NAND2_3141(II18047,WX5883,II18046);
nand NAND2_3142(II18048,II18038,II18046);
nand NAND2_3143(II18037,II18047,II18048);
nand NAND2_3144(II18054,WX5947,WX6011);
nand NAND2_3145(II18055,WX5947,II18054);
nand NAND2_3146(II18056,WX6011,II18054);
nand NAND2_3147(II18053,II18055,II18056);
nand NAND2_3148(II18061,II18037,II18053);
nand NAND2_3149(II18062,II18037,II18061);
nand NAND2_3150(II18063,II18053,II18061);
nand NAND2_3151(WX6073,II18062,II18063);
nand NAND2_3152(II18070,WX6173,WX5821);
nand NAND2_3153(II18071,WX6173,II18070);
nand NAND2_3154(II18072,WX5821,II18070);
nand NAND2_3155(II18069,II18071,II18072);
nand NAND2_3156(II18077,WX5885,II18069);
nand NAND2_3157(II18078,WX5885,II18077);
nand NAND2_3158(II18079,II18069,II18077);
nand NAND2_3159(II18068,II18078,II18079);
nand NAND2_3160(II18085,WX5949,WX6013);
nand NAND2_3161(II18086,WX5949,II18085);
nand NAND2_3162(II18087,WX6013,II18085);
nand NAND2_3163(II18084,II18086,II18087);
nand NAND2_3164(II18092,II18068,II18084);
nand NAND2_3165(II18093,II18068,II18092);
nand NAND2_3166(II18094,II18084,II18092);
nand NAND2_3167(WX6074,II18093,II18094);
nand NAND2_3168(II18101,WX6173,WX5823);
nand NAND2_3169(II18102,WX6173,II18101);
nand NAND2_3170(II18103,WX5823,II18101);
nand NAND2_3171(II18100,II18102,II18103);
nand NAND2_3172(II18108,WX5887,II18100);
nand NAND2_3173(II18109,WX5887,II18108);
nand NAND2_3174(II18110,II18100,II18108);
nand NAND2_3175(II18099,II18109,II18110);
nand NAND2_3176(II18116,WX5951,WX6015);
nand NAND2_3177(II18117,WX5951,II18116);
nand NAND2_3178(II18118,WX6015,II18116);
nand NAND2_3179(II18115,II18117,II18118);
nand NAND2_3180(II18123,II18099,II18115);
nand NAND2_3181(II18124,II18099,II18123);
nand NAND2_3182(II18125,II18115,II18123);
nand NAND2_3183(WX6075,II18124,II18125);
nand NAND2_3184(II18132,WX6173,WX5825);
nand NAND2_3185(II18133,WX6173,II18132);
nand NAND2_3186(II18134,WX5825,II18132);
nand NAND2_3187(II18131,II18133,II18134);
nand NAND2_3188(II18139,WX5889,II18131);
nand NAND2_3189(II18140,WX5889,II18139);
nand NAND2_3190(II18141,II18131,II18139);
nand NAND2_3191(II18130,II18140,II18141);
nand NAND2_3192(II18147,WX5953,WX6017);
nand NAND2_3193(II18148,WX5953,II18147);
nand NAND2_3194(II18149,WX6017,II18147);
nand NAND2_3195(II18146,II18148,II18149);
nand NAND2_3196(II18154,II18130,II18146);
nand NAND2_3197(II18155,II18130,II18154);
nand NAND2_3198(II18156,II18146,II18154);
nand NAND2_3199(WX6076,II18155,II18156);
nand NAND2_3200(II18163,WX6173,WX5827);
nand NAND2_3201(II18164,WX6173,II18163);
nand NAND2_3202(II18165,WX5827,II18163);
nand NAND2_3203(II18162,II18164,II18165);
nand NAND2_3204(II18170,WX5891,II18162);
nand NAND2_3205(II18171,WX5891,II18170);
nand NAND2_3206(II18172,II18162,II18170);
nand NAND2_3207(II18161,II18171,II18172);
nand NAND2_3208(II18178,WX5955,WX6019);
nand NAND2_3209(II18179,WX5955,II18178);
nand NAND2_3210(II18180,WX6019,II18178);
nand NAND2_3211(II18177,II18179,II18180);
nand NAND2_3212(II18185,II18161,II18177);
nand NAND2_3213(II18186,II18161,II18185);
nand NAND2_3214(II18187,II18177,II18185);
nand NAND2_3215(WX6077,II18186,II18187);
nand NAND2_3216(II18194,WX6173,WX5829);
nand NAND2_3217(II18195,WX6173,II18194);
nand NAND2_3218(II18196,WX5829,II18194);
nand NAND2_3219(II18193,II18195,II18196);
nand NAND2_3220(II18201,WX5893,II18193);
nand NAND2_3221(II18202,WX5893,II18201);
nand NAND2_3222(II18203,II18193,II18201);
nand NAND2_3223(II18192,II18202,II18203);
nand NAND2_3224(II18209,WX5957,WX6021);
nand NAND2_3225(II18210,WX5957,II18209);
nand NAND2_3226(II18211,WX6021,II18209);
nand NAND2_3227(II18208,II18210,II18211);
nand NAND2_3228(II18216,II18192,II18208);
nand NAND2_3229(II18217,II18192,II18216);
nand NAND2_3230(II18218,II18208,II18216);
nand NAND2_3231(WX6078,II18217,II18218);
nand NAND2_3232(II18225,WX6173,WX5831);
nand NAND2_3233(II18226,WX6173,II18225);
nand NAND2_3234(II18227,WX5831,II18225);
nand NAND2_3235(II18224,II18226,II18227);
nand NAND2_3236(II18232,WX5895,II18224);
nand NAND2_3237(II18233,WX5895,II18232);
nand NAND2_3238(II18234,II18224,II18232);
nand NAND2_3239(II18223,II18233,II18234);
nand NAND2_3240(II18240,WX5959,WX6023);
nand NAND2_3241(II18241,WX5959,II18240);
nand NAND2_3242(II18242,WX6023,II18240);
nand NAND2_3243(II18239,II18241,II18242);
nand NAND2_3244(II18247,II18223,II18239);
nand NAND2_3245(II18248,II18223,II18247);
nand NAND2_3246(II18249,II18239,II18247);
nand NAND2_3247(WX6079,II18248,II18249);
nand NAND2_3248(II18256,WX6173,WX5833);
nand NAND2_3249(II18257,WX6173,II18256);
nand NAND2_3250(II18258,WX5833,II18256);
nand NAND2_3251(II18255,II18257,II18258);
nand NAND2_3252(II18263,WX5897,II18255);
nand NAND2_3253(II18264,WX5897,II18263);
nand NAND2_3254(II18265,II18255,II18263);
nand NAND2_3255(II18254,II18264,II18265);
nand NAND2_3256(II18271,WX5961,WX6025);
nand NAND2_3257(II18272,WX5961,II18271);
nand NAND2_3258(II18273,WX6025,II18271);
nand NAND2_3259(II18270,II18272,II18273);
nand NAND2_3260(II18278,II18254,II18270);
nand NAND2_3261(II18279,II18254,II18278);
nand NAND2_3262(II18280,II18270,II18278);
nand NAND2_3263(WX6080,II18279,II18280);
nand NAND2_3264(II18287,WX6173,WX5835);
nand NAND2_3265(II18288,WX6173,II18287);
nand NAND2_3266(II18289,WX5835,II18287);
nand NAND2_3267(II18286,II18288,II18289);
nand NAND2_3268(II18294,WX5899,II18286);
nand NAND2_3269(II18295,WX5899,II18294);
nand NAND2_3270(II18296,II18286,II18294);
nand NAND2_3271(II18285,II18295,II18296);
nand NAND2_3272(II18302,WX5963,WX6027);
nand NAND2_3273(II18303,WX5963,II18302);
nand NAND2_3274(II18304,WX6027,II18302);
nand NAND2_3275(II18301,II18303,II18304);
nand NAND2_3276(II18309,II18285,II18301);
nand NAND2_3277(II18310,II18285,II18309);
nand NAND2_3278(II18311,II18301,II18309);
nand NAND2_3279(WX6081,II18310,II18311);
nand NAND2_3280(II18318,WX6173,WX5837);
nand NAND2_3281(II18319,WX6173,II18318);
nand NAND2_3282(II18320,WX5837,II18318);
nand NAND2_3283(II18317,II18319,II18320);
nand NAND2_3284(II18325,WX5901,II18317);
nand NAND2_3285(II18326,WX5901,II18325);
nand NAND2_3286(II18327,II18317,II18325);
nand NAND2_3287(II18316,II18326,II18327);
nand NAND2_3288(II18333,WX5965,WX6029);
nand NAND2_3289(II18334,WX5965,II18333);
nand NAND2_3290(II18335,WX6029,II18333);
nand NAND2_3291(II18332,II18334,II18335);
nand NAND2_3292(II18340,II18316,II18332);
nand NAND2_3293(II18341,II18316,II18340);
nand NAND2_3294(II18342,II18332,II18340);
nand NAND2_3295(WX6082,II18341,II18342);
nand NAND2_3296(II18349,WX6173,WX5839);
nand NAND2_3297(II18350,WX6173,II18349);
nand NAND2_3298(II18351,WX5839,II18349);
nand NAND2_3299(II18348,II18350,II18351);
nand NAND2_3300(II18356,WX5903,II18348);
nand NAND2_3301(II18357,WX5903,II18356);
nand NAND2_3302(II18358,II18348,II18356);
nand NAND2_3303(II18347,II18357,II18358);
nand NAND2_3304(II18364,WX5967,WX6031);
nand NAND2_3305(II18365,WX5967,II18364);
nand NAND2_3306(II18366,WX6031,II18364);
nand NAND2_3307(II18363,II18365,II18366);
nand NAND2_3308(II18371,II18347,II18363);
nand NAND2_3309(II18372,II18347,II18371);
nand NAND2_3310(II18373,II18363,II18371);
nand NAND2_3311(WX6083,II18372,II18373);
nand NAND2_3312(II18380,WX6173,WX5841);
nand NAND2_3313(II18381,WX6173,II18380);
nand NAND2_3314(II18382,WX5841,II18380);
nand NAND2_3315(II18379,II18381,II18382);
nand NAND2_3316(II18387,WX5905,II18379);
nand NAND2_3317(II18388,WX5905,II18387);
nand NAND2_3318(II18389,II18379,II18387);
nand NAND2_3319(II18378,II18388,II18389);
nand NAND2_3320(II18395,WX5969,WX6033);
nand NAND2_3321(II18396,WX5969,II18395);
nand NAND2_3322(II18397,WX6033,II18395);
nand NAND2_3323(II18394,II18396,II18397);
nand NAND2_3324(II18402,II18378,II18394);
nand NAND2_3325(II18403,II18378,II18402);
nand NAND2_3326(II18404,II18394,II18402);
nand NAND2_3327(WX6084,II18403,II18404);
nand NAND2_3328(II18411,WX6173,WX5843);
nand NAND2_3329(II18412,WX6173,II18411);
nand NAND2_3330(II18413,WX5843,II18411);
nand NAND2_3331(II18410,II18412,II18413);
nand NAND2_3332(II18418,WX5907,II18410);
nand NAND2_3333(II18419,WX5907,II18418);
nand NAND2_3334(II18420,II18410,II18418);
nand NAND2_3335(II18409,II18419,II18420);
nand NAND2_3336(II18426,WX5971,WX6035);
nand NAND2_3337(II18427,WX5971,II18426);
nand NAND2_3338(II18428,WX6035,II18426);
nand NAND2_3339(II18425,II18427,II18428);
nand NAND2_3340(II18433,II18409,II18425);
nand NAND2_3341(II18434,II18409,II18433);
nand NAND2_3342(II18435,II18425,II18433);
nand NAND2_3343(WX6085,II18434,II18435);
nand NAND2_3344(II18442,WX6173,WX5845);
nand NAND2_3345(II18443,WX6173,II18442);
nand NAND2_3346(II18444,WX5845,II18442);
nand NAND2_3347(II18441,II18443,II18444);
nand NAND2_3348(II18449,WX5909,II18441);
nand NAND2_3349(II18450,WX5909,II18449);
nand NAND2_3350(II18451,II18441,II18449);
nand NAND2_3351(II18440,II18450,II18451);
nand NAND2_3352(II18457,WX5973,WX6037);
nand NAND2_3353(II18458,WX5973,II18457);
nand NAND2_3354(II18459,WX6037,II18457);
nand NAND2_3355(II18456,II18458,II18459);
nand NAND2_3356(II18464,II18440,II18456);
nand NAND2_3357(II18465,II18440,II18464);
nand NAND2_3358(II18466,II18456,II18464);
nand NAND2_3359(WX6086,II18465,II18466);
nand NAND2_3360(II18473,WX6173,WX5847);
nand NAND2_3361(II18474,WX6173,II18473);
nand NAND2_3362(II18475,WX5847,II18473);
nand NAND2_3363(II18472,II18474,II18475);
nand NAND2_3364(II18480,WX5911,II18472);
nand NAND2_3365(II18481,WX5911,II18480);
nand NAND2_3366(II18482,II18472,II18480);
nand NAND2_3367(II18471,II18481,II18482);
nand NAND2_3368(II18488,WX5975,WX6039);
nand NAND2_3369(II18489,WX5975,II18488);
nand NAND2_3370(II18490,WX6039,II18488);
nand NAND2_3371(II18487,II18489,II18490);
nand NAND2_3372(II18495,II18471,II18487);
nand NAND2_3373(II18496,II18471,II18495);
nand NAND2_3374(II18497,II18487,II18495);
nand NAND2_3375(WX6087,II18496,II18497);
nand NAND2_3376(II18504,WX6174,WX5849);
nand NAND2_3377(II18505,WX6174,II18504);
nand NAND2_3378(II18506,WX5849,II18504);
nand NAND2_3379(II18503,II18505,II18506);
nand NAND2_3380(II18511,WX5913,II18503);
nand NAND2_3381(II18512,WX5913,II18511);
nand NAND2_3382(II18513,II18503,II18511);
nand NAND2_3383(II18502,II18512,II18513);
nand NAND2_3384(II18519,WX5977,WX6041);
nand NAND2_3385(II18520,WX5977,II18519);
nand NAND2_3386(II18521,WX6041,II18519);
nand NAND2_3387(II18518,II18520,II18521);
nand NAND2_3388(II18526,II18502,II18518);
nand NAND2_3389(II18527,II18502,II18526);
nand NAND2_3390(II18528,II18518,II18526);
nand NAND2_3391(WX6088,II18527,II18528);
nand NAND2_3392(II18535,WX6174,WX5851);
nand NAND2_3393(II18536,WX6174,II18535);
nand NAND2_3394(II18537,WX5851,II18535);
nand NAND2_3395(II18534,II18536,II18537);
nand NAND2_3396(II18542,WX5915,II18534);
nand NAND2_3397(II18543,WX5915,II18542);
nand NAND2_3398(II18544,II18534,II18542);
nand NAND2_3399(II18533,II18543,II18544);
nand NAND2_3400(II18550,WX5979,WX6043);
nand NAND2_3401(II18551,WX5979,II18550);
nand NAND2_3402(II18552,WX6043,II18550);
nand NAND2_3403(II18549,II18551,II18552);
nand NAND2_3404(II18557,II18533,II18549);
nand NAND2_3405(II18558,II18533,II18557);
nand NAND2_3406(II18559,II18549,II18557);
nand NAND2_3407(WX6089,II18558,II18559);
nand NAND2_3408(II18566,WX6174,WX5853);
nand NAND2_3409(II18567,WX6174,II18566);
nand NAND2_3410(II18568,WX5853,II18566);
nand NAND2_3411(II18565,II18567,II18568);
nand NAND2_3412(II18573,WX5917,II18565);
nand NAND2_3413(II18574,WX5917,II18573);
nand NAND2_3414(II18575,II18565,II18573);
nand NAND2_3415(II18564,II18574,II18575);
nand NAND2_3416(II18581,WX5981,WX6045);
nand NAND2_3417(II18582,WX5981,II18581);
nand NAND2_3418(II18583,WX6045,II18581);
nand NAND2_3419(II18580,II18582,II18583);
nand NAND2_3420(II18588,II18564,II18580);
nand NAND2_3421(II18589,II18564,II18588);
nand NAND2_3422(II18590,II18580,II18588);
nand NAND2_3423(WX6090,II18589,II18590);
nand NAND2_3424(II18597,WX6174,WX5855);
nand NAND2_3425(II18598,WX6174,II18597);
nand NAND2_3426(II18599,WX5855,II18597);
nand NAND2_3427(II18596,II18598,II18599);
nand NAND2_3428(II18604,WX5919,II18596);
nand NAND2_3429(II18605,WX5919,II18604);
nand NAND2_3430(II18606,II18596,II18604);
nand NAND2_3431(II18595,II18605,II18606);
nand NAND2_3432(II18612,WX5983,WX6047);
nand NAND2_3433(II18613,WX5983,II18612);
nand NAND2_3434(II18614,WX6047,II18612);
nand NAND2_3435(II18611,II18613,II18614);
nand NAND2_3436(II18619,II18595,II18611);
nand NAND2_3437(II18620,II18595,II18619);
nand NAND2_3438(II18621,II18611,II18619);
nand NAND2_3439(WX6091,II18620,II18621);
nand NAND2_3440(II18628,WX6174,WX5857);
nand NAND2_3441(II18629,WX6174,II18628);
nand NAND2_3442(II18630,WX5857,II18628);
nand NAND2_3443(II18627,II18629,II18630);
nand NAND2_3444(II18635,WX5921,II18627);
nand NAND2_3445(II18636,WX5921,II18635);
nand NAND2_3446(II18637,II18627,II18635);
nand NAND2_3447(II18626,II18636,II18637);
nand NAND2_3448(II18643,WX5985,WX6049);
nand NAND2_3449(II18644,WX5985,II18643);
nand NAND2_3450(II18645,WX6049,II18643);
nand NAND2_3451(II18642,II18644,II18645);
nand NAND2_3452(II18650,II18626,II18642);
nand NAND2_3453(II18651,II18626,II18650);
nand NAND2_3454(II18652,II18642,II18650);
nand NAND2_3455(WX6092,II18651,II18652);
nand NAND2_3456(II18659,WX6174,WX5859);
nand NAND2_3457(II18660,WX6174,II18659);
nand NAND2_3458(II18661,WX5859,II18659);
nand NAND2_3459(II18658,II18660,II18661);
nand NAND2_3460(II18666,WX5923,II18658);
nand NAND2_3461(II18667,WX5923,II18666);
nand NAND2_3462(II18668,II18658,II18666);
nand NAND2_3463(II18657,II18667,II18668);
nand NAND2_3464(II18674,WX5987,WX6051);
nand NAND2_3465(II18675,WX5987,II18674);
nand NAND2_3466(II18676,WX6051,II18674);
nand NAND2_3467(II18673,II18675,II18676);
nand NAND2_3468(II18681,II18657,II18673);
nand NAND2_3469(II18682,II18657,II18681);
nand NAND2_3470(II18683,II18673,II18681);
nand NAND2_3471(WX6093,II18682,II18683);
nand NAND2_3472(II18690,WX6174,WX5861);
nand NAND2_3473(II18691,WX6174,II18690);
nand NAND2_3474(II18692,WX5861,II18690);
nand NAND2_3475(II18689,II18691,II18692);
nand NAND2_3476(II18697,WX5925,II18689);
nand NAND2_3477(II18698,WX5925,II18697);
nand NAND2_3478(II18699,II18689,II18697);
nand NAND2_3479(II18688,II18698,II18699);
nand NAND2_3480(II18705,WX5989,WX6053);
nand NAND2_3481(II18706,WX5989,II18705);
nand NAND2_3482(II18707,WX6053,II18705);
nand NAND2_3483(II18704,II18706,II18707);
nand NAND2_3484(II18712,II18688,II18704);
nand NAND2_3485(II18713,II18688,II18712);
nand NAND2_3486(II18714,II18704,II18712);
nand NAND2_3487(WX6094,II18713,II18714);
nand NAND2_3488(II18721,WX6174,WX5863);
nand NAND2_3489(II18722,WX6174,II18721);
nand NAND2_3490(II18723,WX5863,II18721);
nand NAND2_3491(II18720,II18722,II18723);
nand NAND2_3492(II18728,WX5927,II18720);
nand NAND2_3493(II18729,WX5927,II18728);
nand NAND2_3494(II18730,II18720,II18728);
nand NAND2_3495(II18719,II18729,II18730);
nand NAND2_3496(II18736,WX5991,WX6055);
nand NAND2_3497(II18737,WX5991,II18736);
nand NAND2_3498(II18738,WX6055,II18736);
nand NAND2_3499(II18735,II18737,II18738);
nand NAND2_3500(II18743,II18719,II18735);
nand NAND2_3501(II18744,II18719,II18743);
nand NAND2_3502(II18745,II18735,II18743);
nand NAND2_3503(WX6095,II18744,II18745);
nand NAND2_3504(II18752,WX6174,WX5865);
nand NAND2_3505(II18753,WX6174,II18752);
nand NAND2_3506(II18754,WX5865,II18752);
nand NAND2_3507(II18751,II18753,II18754);
nand NAND2_3508(II18759,WX5929,II18751);
nand NAND2_3509(II18760,WX5929,II18759);
nand NAND2_3510(II18761,II18751,II18759);
nand NAND2_3511(II18750,II18760,II18761);
nand NAND2_3512(II18767,WX5993,WX6057);
nand NAND2_3513(II18768,WX5993,II18767);
nand NAND2_3514(II18769,WX6057,II18767);
nand NAND2_3515(II18766,II18768,II18769);
nand NAND2_3516(II18774,II18750,II18766);
nand NAND2_3517(II18775,II18750,II18774);
nand NAND2_3518(II18776,II18766,II18774);
nand NAND2_3519(WX6096,II18775,II18776);
nand NAND2_3520(II18783,WX6174,WX5867);
nand NAND2_3521(II18784,WX6174,II18783);
nand NAND2_3522(II18785,WX5867,II18783);
nand NAND2_3523(II18782,II18784,II18785);
nand NAND2_3524(II18790,WX5931,II18782);
nand NAND2_3525(II18791,WX5931,II18790);
nand NAND2_3526(II18792,II18782,II18790);
nand NAND2_3527(II18781,II18791,II18792);
nand NAND2_3528(II18798,WX5995,WX6059);
nand NAND2_3529(II18799,WX5995,II18798);
nand NAND2_3530(II18800,WX6059,II18798);
nand NAND2_3531(II18797,II18799,II18800);
nand NAND2_3532(II18805,II18781,II18797);
nand NAND2_3533(II18806,II18781,II18805);
nand NAND2_3534(II18807,II18797,II18805);
nand NAND2_3535(WX6097,II18806,II18807);
nand NAND2_3536(II18814,WX6174,WX5869);
nand NAND2_3537(II18815,WX6174,II18814);
nand NAND2_3538(II18816,WX5869,II18814);
nand NAND2_3539(II18813,II18815,II18816);
nand NAND2_3540(II18821,WX5933,II18813);
nand NAND2_3541(II18822,WX5933,II18821);
nand NAND2_3542(II18823,II18813,II18821);
nand NAND2_3543(II18812,II18822,II18823);
nand NAND2_3544(II18829,WX5997,WX6061);
nand NAND2_3545(II18830,WX5997,II18829);
nand NAND2_3546(II18831,WX6061,II18829);
nand NAND2_3547(II18828,II18830,II18831);
nand NAND2_3548(II18836,II18812,II18828);
nand NAND2_3549(II18837,II18812,II18836);
nand NAND2_3550(II18838,II18828,II18836);
nand NAND2_3551(WX6098,II18837,II18838);
nand NAND2_3552(II18845,WX6174,WX5871);
nand NAND2_3553(II18846,WX6174,II18845);
nand NAND2_3554(II18847,WX5871,II18845);
nand NAND2_3555(II18844,II18846,II18847);
nand NAND2_3556(II18852,WX5935,II18844);
nand NAND2_3557(II18853,WX5935,II18852);
nand NAND2_3558(II18854,II18844,II18852);
nand NAND2_3559(II18843,II18853,II18854);
nand NAND2_3560(II18860,WX5999,WX6063);
nand NAND2_3561(II18861,WX5999,II18860);
nand NAND2_3562(II18862,WX6063,II18860);
nand NAND2_3563(II18859,II18861,II18862);
nand NAND2_3564(II18867,II18843,II18859);
nand NAND2_3565(II18868,II18843,II18867);
nand NAND2_3566(II18869,II18859,II18867);
nand NAND2_3567(WX6099,II18868,II18869);
nand NAND2_3568(II18876,WX6174,WX5873);
nand NAND2_3569(II18877,WX6174,II18876);
nand NAND2_3570(II18878,WX5873,II18876);
nand NAND2_3571(II18875,II18877,II18878);
nand NAND2_3572(II18883,WX5937,II18875);
nand NAND2_3573(II18884,WX5937,II18883);
nand NAND2_3574(II18885,II18875,II18883);
nand NAND2_3575(II18874,II18884,II18885);
nand NAND2_3576(II18891,WX6001,WX6065);
nand NAND2_3577(II18892,WX6001,II18891);
nand NAND2_3578(II18893,WX6065,II18891);
nand NAND2_3579(II18890,II18892,II18893);
nand NAND2_3580(II18898,II18874,II18890);
nand NAND2_3581(II18899,II18874,II18898);
nand NAND2_3582(II18900,II18890,II18898);
nand NAND2_3583(WX6100,II18899,II18900);
nand NAND2_3584(II18907,WX6174,WX5875);
nand NAND2_3585(II18908,WX6174,II18907);
nand NAND2_3586(II18909,WX5875,II18907);
nand NAND2_3587(II18906,II18908,II18909);
nand NAND2_3588(II18914,WX5939,II18906);
nand NAND2_3589(II18915,WX5939,II18914);
nand NAND2_3590(II18916,II18906,II18914);
nand NAND2_3591(II18905,II18915,II18916);
nand NAND2_3592(II18922,WX6003,WX6067);
nand NAND2_3593(II18923,WX6003,II18922);
nand NAND2_3594(II18924,WX6067,II18922);
nand NAND2_3595(II18921,II18923,II18924);
nand NAND2_3596(II18929,II18905,II18921);
nand NAND2_3597(II18930,II18905,II18929);
nand NAND2_3598(II18931,II18921,II18929);
nand NAND2_3599(WX6101,II18930,II18931);
nand NAND2_3600(II18938,WX6174,WX5877);
nand NAND2_3601(II18939,WX6174,II18938);
nand NAND2_3602(II18940,WX5877,II18938);
nand NAND2_3603(II18937,II18939,II18940);
nand NAND2_3604(II18945,WX5941,II18937);
nand NAND2_3605(II18946,WX5941,II18945);
nand NAND2_3606(II18947,II18937,II18945);
nand NAND2_3607(II18936,II18946,II18947);
nand NAND2_3608(II18953,WX6005,WX6069);
nand NAND2_3609(II18954,WX6005,II18953);
nand NAND2_3610(II18955,WX6069,II18953);
nand NAND2_3611(II18952,II18954,II18955);
nand NAND2_3612(II18960,II18936,II18952);
nand NAND2_3613(II18961,II18936,II18960);
nand NAND2_3614(II18962,II18952,II18960);
nand NAND2_3615(WX6102,II18961,II18962);
nand NAND2_3616(II18969,WX6174,WX5879);
nand NAND2_3617(II18970,WX6174,II18969);
nand NAND2_3618(II18971,WX5879,II18969);
nand NAND2_3619(II18968,II18970,II18971);
nand NAND2_3620(II18976,WX5943,II18968);
nand NAND2_3621(II18977,WX5943,II18976);
nand NAND2_3622(II18978,II18968,II18976);
nand NAND2_3623(II18967,II18977,II18978);
nand NAND2_3624(II18984,WX6007,WX6071);
nand NAND2_3625(II18985,WX6007,II18984);
nand NAND2_3626(II18986,WX6071,II18984);
nand NAND2_3627(II18983,II18985,II18986);
nand NAND2_3628(II18991,II18967,II18983);
nand NAND2_3629(II18992,II18967,II18991);
nand NAND2_3630(II18993,II18983,II18991);
nand NAND2_3631(WX6103,II18992,II18993);
nand NAND2_3632(II19072,WX5752,WX5657);
nand NAND2_3633(II19073,WX5752,II19072);
nand NAND2_3634(II19074,WX5657,II19072);
nand NAND2_3635(WX6178,II19073,II19074);
nand NAND2_3636(II19085,WX5753,WX5659);
nand NAND2_3637(II19086,WX5753,II19085);
nand NAND2_3638(II19087,WX5659,II19085);
nand NAND2_3639(WX6185,II19086,II19087);
nand NAND2_3640(II19098,WX5754,WX5661);
nand NAND2_3641(II19099,WX5754,II19098);
nand NAND2_3642(II19100,WX5661,II19098);
nand NAND2_3643(WX6192,II19099,II19100);
nand NAND2_3644(II19111,WX5755,WX5663);
nand NAND2_3645(II19112,WX5755,II19111);
nand NAND2_3646(II19113,WX5663,II19111);
nand NAND2_3647(WX6199,II19112,II19113);
nand NAND2_3648(II19124,WX5756,WX5665);
nand NAND2_3649(II19125,WX5756,II19124);
nand NAND2_3650(II19126,WX5665,II19124);
nand NAND2_3651(WX6206,II19125,II19126);
nand NAND2_3652(II19137,WX5757,WX5667);
nand NAND2_3653(II19138,WX5757,II19137);
nand NAND2_3654(II19139,WX5667,II19137);
nand NAND2_3655(WX6213,II19138,II19139);
nand NAND2_3656(II19150,WX5758,WX5669);
nand NAND2_3657(II19151,WX5758,II19150);
nand NAND2_3658(II19152,WX5669,II19150);
nand NAND2_3659(WX6220,II19151,II19152);
nand NAND2_3660(II19163,WX5759,WX5671);
nand NAND2_3661(II19164,WX5759,II19163);
nand NAND2_3662(II19165,WX5671,II19163);
nand NAND2_3663(WX6227,II19164,II19165);
nand NAND2_3664(II19176,WX5760,WX5673);
nand NAND2_3665(II19177,WX5760,II19176);
nand NAND2_3666(II19178,WX5673,II19176);
nand NAND2_3667(WX6234,II19177,II19178);
nand NAND2_3668(II19189,WX5761,WX5675);
nand NAND2_3669(II19190,WX5761,II19189);
nand NAND2_3670(II19191,WX5675,II19189);
nand NAND2_3671(WX6241,II19190,II19191);
nand NAND2_3672(II19202,WX5762,WX5677);
nand NAND2_3673(II19203,WX5762,II19202);
nand NAND2_3674(II19204,WX5677,II19202);
nand NAND2_3675(WX6248,II19203,II19204);
nand NAND2_3676(II19215,WX5763,WX5679);
nand NAND2_3677(II19216,WX5763,II19215);
nand NAND2_3678(II19217,WX5679,II19215);
nand NAND2_3679(WX6255,II19216,II19217);
nand NAND2_3680(II19228,WX5764,WX5681);
nand NAND2_3681(II19229,WX5764,II19228);
nand NAND2_3682(II19230,WX5681,II19228);
nand NAND2_3683(WX6262,II19229,II19230);
nand NAND2_3684(II19241,WX5765,WX5683);
nand NAND2_3685(II19242,WX5765,II19241);
nand NAND2_3686(II19243,WX5683,II19241);
nand NAND2_3687(WX6269,II19242,II19243);
nand NAND2_3688(II19254,WX5766,WX5685);
nand NAND2_3689(II19255,WX5766,II19254);
nand NAND2_3690(II19256,WX5685,II19254);
nand NAND2_3691(WX6276,II19255,II19256);
nand NAND2_3692(II19267,WX5767,WX5687);
nand NAND2_3693(II19268,WX5767,II19267);
nand NAND2_3694(II19269,WX5687,II19267);
nand NAND2_3695(WX6283,II19268,II19269);
nand NAND2_3696(II19280,WX5768,WX5689);
nand NAND2_3697(II19281,WX5768,II19280);
nand NAND2_3698(II19282,WX5689,II19280);
nand NAND2_3699(WX6290,II19281,II19282);
nand NAND2_3700(II19293,WX5769,WX5691);
nand NAND2_3701(II19294,WX5769,II19293);
nand NAND2_3702(II19295,WX5691,II19293);
nand NAND2_3703(WX6297,II19294,II19295);
nand NAND2_3704(II19306,WX5770,WX5693);
nand NAND2_3705(II19307,WX5770,II19306);
nand NAND2_3706(II19308,WX5693,II19306);
nand NAND2_3707(WX6304,II19307,II19308);
nand NAND2_3708(II19319,WX5771,WX5695);
nand NAND2_3709(II19320,WX5771,II19319);
nand NAND2_3710(II19321,WX5695,II19319);
nand NAND2_3711(WX6311,II19320,II19321);
nand NAND2_3712(II19332,WX5772,WX5697);
nand NAND2_3713(II19333,WX5772,II19332);
nand NAND2_3714(II19334,WX5697,II19332);
nand NAND2_3715(WX6318,II19333,II19334);
nand NAND2_3716(II19345,WX5773,WX5699);
nand NAND2_3717(II19346,WX5773,II19345);
nand NAND2_3718(II19347,WX5699,II19345);
nand NAND2_3719(WX6325,II19346,II19347);
nand NAND2_3720(II19358,WX5774,WX5701);
nand NAND2_3721(II19359,WX5774,II19358);
nand NAND2_3722(II19360,WX5701,II19358);
nand NAND2_3723(WX6332,II19359,II19360);
nand NAND2_3724(II19371,WX5775,WX5703);
nand NAND2_3725(II19372,WX5775,II19371);
nand NAND2_3726(II19373,WX5703,II19371);
nand NAND2_3727(WX6339,II19372,II19373);
nand NAND2_3728(II19384,WX5776,WX5705);
nand NAND2_3729(II19385,WX5776,II19384);
nand NAND2_3730(II19386,WX5705,II19384);
nand NAND2_3731(WX6346,II19385,II19386);
nand NAND2_3732(II19397,WX5777,WX5707);
nand NAND2_3733(II19398,WX5777,II19397);
nand NAND2_3734(II19399,WX5707,II19397);
nand NAND2_3735(WX6353,II19398,II19399);
nand NAND2_3736(II19410,WX5778,WX5709);
nand NAND2_3737(II19411,WX5778,II19410);
nand NAND2_3738(II19412,WX5709,II19410);
nand NAND2_3739(WX6360,II19411,II19412);
nand NAND2_3740(II19423,WX5779,WX5711);
nand NAND2_3741(II19424,WX5779,II19423);
nand NAND2_3742(II19425,WX5711,II19423);
nand NAND2_3743(WX6367,II19424,II19425);
nand NAND2_3744(II19436,WX5780,WX5713);
nand NAND2_3745(II19437,WX5780,II19436);
nand NAND2_3746(II19438,WX5713,II19436);
nand NAND2_3747(WX6374,II19437,II19438);
nand NAND2_3748(II19449,WX5781,WX5715);
nand NAND2_3749(II19450,WX5781,II19449);
nand NAND2_3750(II19451,WX5715,II19449);
nand NAND2_3751(WX6381,II19450,II19451);
nand NAND2_3752(II19462,WX5782,WX5717);
nand NAND2_3753(II19463,WX5782,II19462);
nand NAND2_3754(II19464,WX5717,II19462);
nand NAND2_3755(WX6388,II19463,II19464);
nand NAND2_3756(II19475,WX5783,WX5719);
nand NAND2_3757(II19476,WX5783,II19475);
nand NAND2_3758(II19477,WX5719,II19475);
nand NAND2_3759(WX6395,II19476,II19477);
nand NAND2_3760(II19490,WX5799,CRC_OUT_5_31);
nand NAND2_3761(II19491,WX5799,II19490);
nand NAND2_3762(II19492,CRC_OUT_5_31,II19490);
nand NAND2_3763(II19489,II19491,II19492);
nand NAND2_3764(II19497,CRC_OUT_5_15,II19489);
nand NAND2_3765(II19498,CRC_OUT_5_15,II19497);
nand NAND2_3766(II19499,II19489,II19497);
nand NAND2_3767(WX6403,II19498,II19499);
nand NAND2_3768(II19505,WX5804,CRC_OUT_5_31);
nand NAND2_3769(II19506,WX5804,II19505);
nand NAND2_3770(II19507,CRC_OUT_5_31,II19505);
nand NAND2_3771(II19504,II19506,II19507);
nand NAND2_3772(II19512,CRC_OUT_5_10,II19504);
nand NAND2_3773(II19513,CRC_OUT_5_10,II19512);
nand NAND2_3774(II19514,II19504,II19512);
nand NAND2_3775(WX6404,II19513,II19514);
nand NAND2_3776(II19520,WX5811,CRC_OUT_5_31);
nand NAND2_3777(II19521,WX5811,II19520);
nand NAND2_3778(II19522,CRC_OUT_5_31,II19520);
nand NAND2_3779(II19519,II19521,II19522);
nand NAND2_3780(II19527,CRC_OUT_5_3,II19519);
nand NAND2_3781(II19528,CRC_OUT_5_3,II19527);
nand NAND2_3782(II19529,II19519,II19527);
nand NAND2_3783(WX6405,II19528,II19529);
nand NAND2_3784(II19534,WX5815,CRC_OUT_5_31);
nand NAND2_3785(II19535,WX5815,II19534);
nand NAND2_3786(II19536,CRC_OUT_5_31,II19534);
nand NAND2_3787(WX6406,II19535,II19536);
nand NAND2_3788(II19541,WX5784,CRC_OUT_5_30);
nand NAND2_3789(II19542,WX5784,II19541);
nand NAND2_3790(II19543,CRC_OUT_5_30,II19541);
nand NAND2_3791(WX6407,II19542,II19543);
nand NAND2_3792(II19548,WX5785,CRC_OUT_5_29);
nand NAND2_3793(II19549,WX5785,II19548);
nand NAND2_3794(II19550,CRC_OUT_5_29,II19548);
nand NAND2_3795(WX6408,II19549,II19550);
nand NAND2_3796(II19555,WX5786,CRC_OUT_5_28);
nand NAND2_3797(II19556,WX5786,II19555);
nand NAND2_3798(II19557,CRC_OUT_5_28,II19555);
nand NAND2_3799(WX6409,II19556,II19557);
nand NAND2_3800(II19562,WX5787,CRC_OUT_5_27);
nand NAND2_3801(II19563,WX5787,II19562);
nand NAND2_3802(II19564,CRC_OUT_5_27,II19562);
nand NAND2_3803(WX6410,II19563,II19564);
nand NAND2_3804(II19569,WX5788,CRC_OUT_5_26);
nand NAND2_3805(II19570,WX5788,II19569);
nand NAND2_3806(II19571,CRC_OUT_5_26,II19569);
nand NAND2_3807(WX6411,II19570,II19571);
nand NAND2_3808(II19576,WX5789,CRC_OUT_5_25);
nand NAND2_3809(II19577,WX5789,II19576);
nand NAND2_3810(II19578,CRC_OUT_5_25,II19576);
nand NAND2_3811(WX6412,II19577,II19578);
nand NAND2_3812(II19583,WX5790,CRC_OUT_5_24);
nand NAND2_3813(II19584,WX5790,II19583);
nand NAND2_3814(II19585,CRC_OUT_5_24,II19583);
nand NAND2_3815(WX6413,II19584,II19585);
nand NAND2_3816(II19590,WX5791,CRC_OUT_5_23);
nand NAND2_3817(II19591,WX5791,II19590);
nand NAND2_3818(II19592,CRC_OUT_5_23,II19590);
nand NAND2_3819(WX6414,II19591,II19592);
nand NAND2_3820(II19597,WX5792,CRC_OUT_5_22);
nand NAND2_3821(II19598,WX5792,II19597);
nand NAND2_3822(II19599,CRC_OUT_5_22,II19597);
nand NAND2_3823(WX6415,II19598,II19599);
nand NAND2_3824(II19604,WX5793,CRC_OUT_5_21);
nand NAND2_3825(II19605,WX5793,II19604);
nand NAND2_3826(II19606,CRC_OUT_5_21,II19604);
nand NAND2_3827(WX6416,II19605,II19606);
nand NAND2_3828(II19611,WX5794,CRC_OUT_5_20);
nand NAND2_3829(II19612,WX5794,II19611);
nand NAND2_3830(II19613,CRC_OUT_5_20,II19611);
nand NAND2_3831(WX6417,II19612,II19613);
nand NAND2_3832(II19618,WX5795,CRC_OUT_5_19);
nand NAND2_3833(II19619,WX5795,II19618);
nand NAND2_3834(II19620,CRC_OUT_5_19,II19618);
nand NAND2_3835(WX6418,II19619,II19620);
nand NAND2_3836(II19625,WX5796,CRC_OUT_5_18);
nand NAND2_3837(II19626,WX5796,II19625);
nand NAND2_3838(II19627,CRC_OUT_5_18,II19625);
nand NAND2_3839(WX6419,II19626,II19627);
nand NAND2_3840(II19632,WX5797,CRC_OUT_5_17);
nand NAND2_3841(II19633,WX5797,II19632);
nand NAND2_3842(II19634,CRC_OUT_5_17,II19632);
nand NAND2_3843(WX6420,II19633,II19634);
nand NAND2_3844(II19639,WX5798,CRC_OUT_5_16);
nand NAND2_3845(II19640,WX5798,II19639);
nand NAND2_3846(II19641,CRC_OUT_5_16,II19639);
nand NAND2_3847(WX6421,II19640,II19641);
nand NAND2_3848(II19646,WX5800,CRC_OUT_5_14);
nand NAND2_3849(II19647,WX5800,II19646);
nand NAND2_3850(II19648,CRC_OUT_5_14,II19646);
nand NAND2_3851(WX6422,II19647,II19648);
nand NAND2_3852(II19653,WX5801,CRC_OUT_5_13);
nand NAND2_3853(II19654,WX5801,II19653);
nand NAND2_3854(II19655,CRC_OUT_5_13,II19653);
nand NAND2_3855(WX6423,II19654,II19655);
nand NAND2_3856(II19660,WX5802,CRC_OUT_5_12);
nand NAND2_3857(II19661,WX5802,II19660);
nand NAND2_3858(II19662,CRC_OUT_5_12,II19660);
nand NAND2_3859(WX6424,II19661,II19662);
nand NAND2_3860(II19667,WX5803,CRC_OUT_5_11);
nand NAND2_3861(II19668,WX5803,II19667);
nand NAND2_3862(II19669,CRC_OUT_5_11,II19667);
nand NAND2_3863(WX6425,II19668,II19669);
nand NAND2_3864(II19674,WX5805,CRC_OUT_5_9);
nand NAND2_3865(II19675,WX5805,II19674);
nand NAND2_3866(II19676,CRC_OUT_5_9,II19674);
nand NAND2_3867(WX6426,II19675,II19676);
nand NAND2_3868(II19681,WX5806,CRC_OUT_5_8);
nand NAND2_3869(II19682,WX5806,II19681);
nand NAND2_3870(II19683,CRC_OUT_5_8,II19681);
nand NAND2_3871(WX6427,II19682,II19683);
nand NAND2_3872(II19688,WX5807,CRC_OUT_5_7);
nand NAND2_3873(II19689,WX5807,II19688);
nand NAND2_3874(II19690,CRC_OUT_5_7,II19688);
nand NAND2_3875(WX6428,II19689,II19690);
nand NAND2_3876(II19695,WX5808,CRC_OUT_5_6);
nand NAND2_3877(II19696,WX5808,II19695);
nand NAND2_3878(II19697,CRC_OUT_5_6,II19695);
nand NAND2_3879(WX6429,II19696,II19697);
nand NAND2_3880(II19702,WX5809,CRC_OUT_5_5);
nand NAND2_3881(II19703,WX5809,II19702);
nand NAND2_3882(II19704,CRC_OUT_5_5,II19702);
nand NAND2_3883(WX6430,II19703,II19704);
nand NAND2_3884(II19709,WX5810,CRC_OUT_5_4);
nand NAND2_3885(II19710,WX5810,II19709);
nand NAND2_3886(II19711,CRC_OUT_5_4,II19709);
nand NAND2_3887(WX6431,II19710,II19711);
nand NAND2_3888(II19716,WX5812,CRC_OUT_5_2);
nand NAND2_3889(II19717,WX5812,II19716);
nand NAND2_3890(II19718,CRC_OUT_5_2,II19716);
nand NAND2_3891(WX6432,II19717,II19718);
nand NAND2_3892(II19723,WX5813,CRC_OUT_5_1);
nand NAND2_3893(II19724,WX5813,II19723);
nand NAND2_3894(II19725,CRC_OUT_5_1,II19723);
nand NAND2_3895(WX6433,II19724,II19725);
nand NAND2_3896(II19730,WX5814,CRC_OUT_5_0);
nand NAND2_3897(II19731,WX5814,II19730);
nand NAND2_3898(II19732,CRC_OUT_5_0,II19730);
nand NAND2_3899(WX6434,II19731,II19732);
nand NAND2_3900(II22013,WX7466,WX7110);
nand NAND2_3901(II22014,WX7466,II22013);
nand NAND2_3902(II22015,WX7110,II22013);
nand NAND2_3903(II22012,II22014,II22015);
nand NAND2_3904(II22020,WX7174,II22012);
nand NAND2_3905(II22021,WX7174,II22020);
nand NAND2_3906(II22022,II22012,II22020);
nand NAND2_3907(II22011,II22021,II22022);
nand NAND2_3908(II22028,WX7238,WX7302);
nand NAND2_3909(II22029,WX7238,II22028);
nand NAND2_3910(II22030,WX7302,II22028);
nand NAND2_3911(II22027,II22029,II22030);
nand NAND2_3912(II22035,II22011,II22027);
nand NAND2_3913(II22036,II22011,II22035);
nand NAND2_3914(II22037,II22027,II22035);
nand NAND2_3915(WX7365,II22036,II22037);
nand NAND2_3916(II22044,WX7466,WX7112);
nand NAND2_3917(II22045,WX7466,II22044);
nand NAND2_3918(II22046,WX7112,II22044);
nand NAND2_3919(II22043,II22045,II22046);
nand NAND2_3920(II22051,WX7176,II22043);
nand NAND2_3921(II22052,WX7176,II22051);
nand NAND2_3922(II22053,II22043,II22051);
nand NAND2_3923(II22042,II22052,II22053);
nand NAND2_3924(II22059,WX7240,WX7304);
nand NAND2_3925(II22060,WX7240,II22059);
nand NAND2_3926(II22061,WX7304,II22059);
nand NAND2_3927(II22058,II22060,II22061);
nand NAND2_3928(II22066,II22042,II22058);
nand NAND2_3929(II22067,II22042,II22066);
nand NAND2_3930(II22068,II22058,II22066);
nand NAND2_3931(WX7366,II22067,II22068);
nand NAND2_3932(II22075,WX7466,WX7114);
nand NAND2_3933(II22076,WX7466,II22075);
nand NAND2_3934(II22077,WX7114,II22075);
nand NAND2_3935(II22074,II22076,II22077);
nand NAND2_3936(II22082,WX7178,II22074);
nand NAND2_3937(II22083,WX7178,II22082);
nand NAND2_3938(II22084,II22074,II22082);
nand NAND2_3939(II22073,II22083,II22084);
nand NAND2_3940(II22090,WX7242,WX7306);
nand NAND2_3941(II22091,WX7242,II22090);
nand NAND2_3942(II22092,WX7306,II22090);
nand NAND2_3943(II22089,II22091,II22092);
nand NAND2_3944(II22097,II22073,II22089);
nand NAND2_3945(II22098,II22073,II22097);
nand NAND2_3946(II22099,II22089,II22097);
nand NAND2_3947(WX7367,II22098,II22099);
nand NAND2_3948(II22106,WX7466,WX7116);
nand NAND2_3949(II22107,WX7466,II22106);
nand NAND2_3950(II22108,WX7116,II22106);
nand NAND2_3951(II22105,II22107,II22108);
nand NAND2_3952(II22113,WX7180,II22105);
nand NAND2_3953(II22114,WX7180,II22113);
nand NAND2_3954(II22115,II22105,II22113);
nand NAND2_3955(II22104,II22114,II22115);
nand NAND2_3956(II22121,WX7244,WX7308);
nand NAND2_3957(II22122,WX7244,II22121);
nand NAND2_3958(II22123,WX7308,II22121);
nand NAND2_3959(II22120,II22122,II22123);
nand NAND2_3960(II22128,II22104,II22120);
nand NAND2_3961(II22129,II22104,II22128);
nand NAND2_3962(II22130,II22120,II22128);
nand NAND2_3963(WX7368,II22129,II22130);
nand NAND2_3964(II22137,WX7466,WX7118);
nand NAND2_3965(II22138,WX7466,II22137);
nand NAND2_3966(II22139,WX7118,II22137);
nand NAND2_3967(II22136,II22138,II22139);
nand NAND2_3968(II22144,WX7182,II22136);
nand NAND2_3969(II22145,WX7182,II22144);
nand NAND2_3970(II22146,II22136,II22144);
nand NAND2_3971(II22135,II22145,II22146);
nand NAND2_3972(II22152,WX7246,WX7310);
nand NAND2_3973(II22153,WX7246,II22152);
nand NAND2_3974(II22154,WX7310,II22152);
nand NAND2_3975(II22151,II22153,II22154);
nand NAND2_3976(II22159,II22135,II22151);
nand NAND2_3977(II22160,II22135,II22159);
nand NAND2_3978(II22161,II22151,II22159);
nand NAND2_3979(WX7369,II22160,II22161);
nand NAND2_3980(II22168,WX7466,WX7120);
nand NAND2_3981(II22169,WX7466,II22168);
nand NAND2_3982(II22170,WX7120,II22168);
nand NAND2_3983(II22167,II22169,II22170);
nand NAND2_3984(II22175,WX7184,II22167);
nand NAND2_3985(II22176,WX7184,II22175);
nand NAND2_3986(II22177,II22167,II22175);
nand NAND2_3987(II22166,II22176,II22177);
nand NAND2_3988(II22183,WX7248,WX7312);
nand NAND2_3989(II22184,WX7248,II22183);
nand NAND2_3990(II22185,WX7312,II22183);
nand NAND2_3991(II22182,II22184,II22185);
nand NAND2_3992(II22190,II22166,II22182);
nand NAND2_3993(II22191,II22166,II22190);
nand NAND2_3994(II22192,II22182,II22190);
nand NAND2_3995(WX7370,II22191,II22192);
nand NAND2_3996(II22199,WX7466,WX7122);
nand NAND2_3997(II22200,WX7466,II22199);
nand NAND2_3998(II22201,WX7122,II22199);
nand NAND2_3999(II22198,II22200,II22201);
nand NAND2_4000(II22206,WX7186,II22198);
nand NAND2_4001(II22207,WX7186,II22206);
nand NAND2_4002(II22208,II22198,II22206);
nand NAND2_4003(II22197,II22207,II22208);
nand NAND2_4004(II22214,WX7250,WX7314);
nand NAND2_4005(II22215,WX7250,II22214);
nand NAND2_4006(II22216,WX7314,II22214);
nand NAND2_4007(II22213,II22215,II22216);
nand NAND2_4008(II22221,II22197,II22213);
nand NAND2_4009(II22222,II22197,II22221);
nand NAND2_4010(II22223,II22213,II22221);
nand NAND2_4011(WX7371,II22222,II22223);
nand NAND2_4012(II22230,WX7466,WX7124);
nand NAND2_4013(II22231,WX7466,II22230);
nand NAND2_4014(II22232,WX7124,II22230);
nand NAND2_4015(II22229,II22231,II22232);
nand NAND2_4016(II22237,WX7188,II22229);
nand NAND2_4017(II22238,WX7188,II22237);
nand NAND2_4018(II22239,II22229,II22237);
nand NAND2_4019(II22228,II22238,II22239);
nand NAND2_4020(II22245,WX7252,WX7316);
nand NAND2_4021(II22246,WX7252,II22245);
nand NAND2_4022(II22247,WX7316,II22245);
nand NAND2_4023(II22244,II22246,II22247);
nand NAND2_4024(II22252,II22228,II22244);
nand NAND2_4025(II22253,II22228,II22252);
nand NAND2_4026(II22254,II22244,II22252);
nand NAND2_4027(WX7372,II22253,II22254);
nand NAND2_4028(II22261,WX7466,WX7126);
nand NAND2_4029(II22262,WX7466,II22261);
nand NAND2_4030(II22263,WX7126,II22261);
nand NAND2_4031(II22260,II22262,II22263);
nand NAND2_4032(II22268,WX7190,II22260);
nand NAND2_4033(II22269,WX7190,II22268);
nand NAND2_4034(II22270,II22260,II22268);
nand NAND2_4035(II22259,II22269,II22270);
nand NAND2_4036(II22276,WX7254,WX7318);
nand NAND2_4037(II22277,WX7254,II22276);
nand NAND2_4038(II22278,WX7318,II22276);
nand NAND2_4039(II22275,II22277,II22278);
nand NAND2_4040(II22283,II22259,II22275);
nand NAND2_4041(II22284,II22259,II22283);
nand NAND2_4042(II22285,II22275,II22283);
nand NAND2_4043(WX7373,II22284,II22285);
nand NAND2_4044(II22292,WX7466,WX7128);
nand NAND2_4045(II22293,WX7466,II22292);
nand NAND2_4046(II22294,WX7128,II22292);
nand NAND2_4047(II22291,II22293,II22294);
nand NAND2_4048(II22299,WX7192,II22291);
nand NAND2_4049(II22300,WX7192,II22299);
nand NAND2_4050(II22301,II22291,II22299);
nand NAND2_4051(II22290,II22300,II22301);
nand NAND2_4052(II22307,WX7256,WX7320);
nand NAND2_4053(II22308,WX7256,II22307);
nand NAND2_4054(II22309,WX7320,II22307);
nand NAND2_4055(II22306,II22308,II22309);
nand NAND2_4056(II22314,II22290,II22306);
nand NAND2_4057(II22315,II22290,II22314);
nand NAND2_4058(II22316,II22306,II22314);
nand NAND2_4059(WX7374,II22315,II22316);
nand NAND2_4060(II22323,WX7466,WX7130);
nand NAND2_4061(II22324,WX7466,II22323);
nand NAND2_4062(II22325,WX7130,II22323);
nand NAND2_4063(II22322,II22324,II22325);
nand NAND2_4064(II22330,WX7194,II22322);
nand NAND2_4065(II22331,WX7194,II22330);
nand NAND2_4066(II22332,II22322,II22330);
nand NAND2_4067(II22321,II22331,II22332);
nand NAND2_4068(II22338,WX7258,WX7322);
nand NAND2_4069(II22339,WX7258,II22338);
nand NAND2_4070(II22340,WX7322,II22338);
nand NAND2_4071(II22337,II22339,II22340);
nand NAND2_4072(II22345,II22321,II22337);
nand NAND2_4073(II22346,II22321,II22345);
nand NAND2_4074(II22347,II22337,II22345);
nand NAND2_4075(WX7375,II22346,II22347);
nand NAND2_4076(II22354,WX7466,WX7132);
nand NAND2_4077(II22355,WX7466,II22354);
nand NAND2_4078(II22356,WX7132,II22354);
nand NAND2_4079(II22353,II22355,II22356);
nand NAND2_4080(II22361,WX7196,II22353);
nand NAND2_4081(II22362,WX7196,II22361);
nand NAND2_4082(II22363,II22353,II22361);
nand NAND2_4083(II22352,II22362,II22363);
nand NAND2_4084(II22369,WX7260,WX7324);
nand NAND2_4085(II22370,WX7260,II22369);
nand NAND2_4086(II22371,WX7324,II22369);
nand NAND2_4087(II22368,II22370,II22371);
nand NAND2_4088(II22376,II22352,II22368);
nand NAND2_4089(II22377,II22352,II22376);
nand NAND2_4090(II22378,II22368,II22376);
nand NAND2_4091(WX7376,II22377,II22378);
nand NAND2_4092(II22385,WX7466,WX7134);
nand NAND2_4093(II22386,WX7466,II22385);
nand NAND2_4094(II22387,WX7134,II22385);
nand NAND2_4095(II22384,II22386,II22387);
nand NAND2_4096(II22392,WX7198,II22384);
nand NAND2_4097(II22393,WX7198,II22392);
nand NAND2_4098(II22394,II22384,II22392);
nand NAND2_4099(II22383,II22393,II22394);
nand NAND2_4100(II22400,WX7262,WX7326);
nand NAND2_4101(II22401,WX7262,II22400);
nand NAND2_4102(II22402,WX7326,II22400);
nand NAND2_4103(II22399,II22401,II22402);
nand NAND2_4104(II22407,II22383,II22399);
nand NAND2_4105(II22408,II22383,II22407);
nand NAND2_4106(II22409,II22399,II22407);
nand NAND2_4107(WX7377,II22408,II22409);
nand NAND2_4108(II22416,WX7466,WX7136);
nand NAND2_4109(II22417,WX7466,II22416);
nand NAND2_4110(II22418,WX7136,II22416);
nand NAND2_4111(II22415,II22417,II22418);
nand NAND2_4112(II22423,WX7200,II22415);
nand NAND2_4113(II22424,WX7200,II22423);
nand NAND2_4114(II22425,II22415,II22423);
nand NAND2_4115(II22414,II22424,II22425);
nand NAND2_4116(II22431,WX7264,WX7328);
nand NAND2_4117(II22432,WX7264,II22431);
nand NAND2_4118(II22433,WX7328,II22431);
nand NAND2_4119(II22430,II22432,II22433);
nand NAND2_4120(II22438,II22414,II22430);
nand NAND2_4121(II22439,II22414,II22438);
nand NAND2_4122(II22440,II22430,II22438);
nand NAND2_4123(WX7378,II22439,II22440);
nand NAND2_4124(II22447,WX7466,WX7138);
nand NAND2_4125(II22448,WX7466,II22447);
nand NAND2_4126(II22449,WX7138,II22447);
nand NAND2_4127(II22446,II22448,II22449);
nand NAND2_4128(II22454,WX7202,II22446);
nand NAND2_4129(II22455,WX7202,II22454);
nand NAND2_4130(II22456,II22446,II22454);
nand NAND2_4131(II22445,II22455,II22456);
nand NAND2_4132(II22462,WX7266,WX7330);
nand NAND2_4133(II22463,WX7266,II22462);
nand NAND2_4134(II22464,WX7330,II22462);
nand NAND2_4135(II22461,II22463,II22464);
nand NAND2_4136(II22469,II22445,II22461);
nand NAND2_4137(II22470,II22445,II22469);
nand NAND2_4138(II22471,II22461,II22469);
nand NAND2_4139(WX7379,II22470,II22471);
nand NAND2_4140(II22478,WX7466,WX7140);
nand NAND2_4141(II22479,WX7466,II22478);
nand NAND2_4142(II22480,WX7140,II22478);
nand NAND2_4143(II22477,II22479,II22480);
nand NAND2_4144(II22485,WX7204,II22477);
nand NAND2_4145(II22486,WX7204,II22485);
nand NAND2_4146(II22487,II22477,II22485);
nand NAND2_4147(II22476,II22486,II22487);
nand NAND2_4148(II22493,WX7268,WX7332);
nand NAND2_4149(II22494,WX7268,II22493);
nand NAND2_4150(II22495,WX7332,II22493);
nand NAND2_4151(II22492,II22494,II22495);
nand NAND2_4152(II22500,II22476,II22492);
nand NAND2_4153(II22501,II22476,II22500);
nand NAND2_4154(II22502,II22492,II22500);
nand NAND2_4155(WX7380,II22501,II22502);
nand NAND2_4156(II22509,WX7467,WX7142);
nand NAND2_4157(II22510,WX7467,II22509);
nand NAND2_4158(II22511,WX7142,II22509);
nand NAND2_4159(II22508,II22510,II22511);
nand NAND2_4160(II22516,WX7206,II22508);
nand NAND2_4161(II22517,WX7206,II22516);
nand NAND2_4162(II22518,II22508,II22516);
nand NAND2_4163(II22507,II22517,II22518);
nand NAND2_4164(II22524,WX7270,WX7334);
nand NAND2_4165(II22525,WX7270,II22524);
nand NAND2_4166(II22526,WX7334,II22524);
nand NAND2_4167(II22523,II22525,II22526);
nand NAND2_4168(II22531,II22507,II22523);
nand NAND2_4169(II22532,II22507,II22531);
nand NAND2_4170(II22533,II22523,II22531);
nand NAND2_4171(WX7381,II22532,II22533);
nand NAND2_4172(II22540,WX7467,WX7144);
nand NAND2_4173(II22541,WX7467,II22540);
nand NAND2_4174(II22542,WX7144,II22540);
nand NAND2_4175(II22539,II22541,II22542);
nand NAND2_4176(II22547,WX7208,II22539);
nand NAND2_4177(II22548,WX7208,II22547);
nand NAND2_4178(II22549,II22539,II22547);
nand NAND2_4179(II22538,II22548,II22549);
nand NAND2_4180(II22555,WX7272,WX7336);
nand NAND2_4181(II22556,WX7272,II22555);
nand NAND2_4182(II22557,WX7336,II22555);
nand NAND2_4183(II22554,II22556,II22557);
nand NAND2_4184(II22562,II22538,II22554);
nand NAND2_4185(II22563,II22538,II22562);
nand NAND2_4186(II22564,II22554,II22562);
nand NAND2_4187(WX7382,II22563,II22564);
nand NAND2_4188(II22571,WX7467,WX7146);
nand NAND2_4189(II22572,WX7467,II22571);
nand NAND2_4190(II22573,WX7146,II22571);
nand NAND2_4191(II22570,II22572,II22573);
nand NAND2_4192(II22578,WX7210,II22570);
nand NAND2_4193(II22579,WX7210,II22578);
nand NAND2_4194(II22580,II22570,II22578);
nand NAND2_4195(II22569,II22579,II22580);
nand NAND2_4196(II22586,WX7274,WX7338);
nand NAND2_4197(II22587,WX7274,II22586);
nand NAND2_4198(II22588,WX7338,II22586);
nand NAND2_4199(II22585,II22587,II22588);
nand NAND2_4200(II22593,II22569,II22585);
nand NAND2_4201(II22594,II22569,II22593);
nand NAND2_4202(II22595,II22585,II22593);
nand NAND2_4203(WX7383,II22594,II22595);
nand NAND2_4204(II22602,WX7467,WX7148);
nand NAND2_4205(II22603,WX7467,II22602);
nand NAND2_4206(II22604,WX7148,II22602);
nand NAND2_4207(II22601,II22603,II22604);
nand NAND2_4208(II22609,WX7212,II22601);
nand NAND2_4209(II22610,WX7212,II22609);
nand NAND2_4210(II22611,II22601,II22609);
nand NAND2_4211(II22600,II22610,II22611);
nand NAND2_4212(II22617,WX7276,WX7340);
nand NAND2_4213(II22618,WX7276,II22617);
nand NAND2_4214(II22619,WX7340,II22617);
nand NAND2_4215(II22616,II22618,II22619);
nand NAND2_4216(II22624,II22600,II22616);
nand NAND2_4217(II22625,II22600,II22624);
nand NAND2_4218(II22626,II22616,II22624);
nand NAND2_4219(WX7384,II22625,II22626);
nand NAND2_4220(II22633,WX7467,WX7150);
nand NAND2_4221(II22634,WX7467,II22633);
nand NAND2_4222(II22635,WX7150,II22633);
nand NAND2_4223(II22632,II22634,II22635);
nand NAND2_4224(II22640,WX7214,II22632);
nand NAND2_4225(II22641,WX7214,II22640);
nand NAND2_4226(II22642,II22632,II22640);
nand NAND2_4227(II22631,II22641,II22642);
nand NAND2_4228(II22648,WX7278,WX7342);
nand NAND2_4229(II22649,WX7278,II22648);
nand NAND2_4230(II22650,WX7342,II22648);
nand NAND2_4231(II22647,II22649,II22650);
nand NAND2_4232(II22655,II22631,II22647);
nand NAND2_4233(II22656,II22631,II22655);
nand NAND2_4234(II22657,II22647,II22655);
nand NAND2_4235(WX7385,II22656,II22657);
nand NAND2_4236(II22664,WX7467,WX7152);
nand NAND2_4237(II22665,WX7467,II22664);
nand NAND2_4238(II22666,WX7152,II22664);
nand NAND2_4239(II22663,II22665,II22666);
nand NAND2_4240(II22671,WX7216,II22663);
nand NAND2_4241(II22672,WX7216,II22671);
nand NAND2_4242(II22673,II22663,II22671);
nand NAND2_4243(II22662,II22672,II22673);
nand NAND2_4244(II22679,WX7280,WX7344);
nand NAND2_4245(II22680,WX7280,II22679);
nand NAND2_4246(II22681,WX7344,II22679);
nand NAND2_4247(II22678,II22680,II22681);
nand NAND2_4248(II22686,II22662,II22678);
nand NAND2_4249(II22687,II22662,II22686);
nand NAND2_4250(II22688,II22678,II22686);
nand NAND2_4251(WX7386,II22687,II22688);
nand NAND2_4252(II22695,WX7467,WX7154);
nand NAND2_4253(II22696,WX7467,II22695);
nand NAND2_4254(II22697,WX7154,II22695);
nand NAND2_4255(II22694,II22696,II22697);
nand NAND2_4256(II22702,WX7218,II22694);
nand NAND2_4257(II22703,WX7218,II22702);
nand NAND2_4258(II22704,II22694,II22702);
nand NAND2_4259(II22693,II22703,II22704);
nand NAND2_4260(II22710,WX7282,WX7346);
nand NAND2_4261(II22711,WX7282,II22710);
nand NAND2_4262(II22712,WX7346,II22710);
nand NAND2_4263(II22709,II22711,II22712);
nand NAND2_4264(II22717,II22693,II22709);
nand NAND2_4265(II22718,II22693,II22717);
nand NAND2_4266(II22719,II22709,II22717);
nand NAND2_4267(WX7387,II22718,II22719);
nand NAND2_4268(II22726,WX7467,WX7156);
nand NAND2_4269(II22727,WX7467,II22726);
nand NAND2_4270(II22728,WX7156,II22726);
nand NAND2_4271(II22725,II22727,II22728);
nand NAND2_4272(II22733,WX7220,II22725);
nand NAND2_4273(II22734,WX7220,II22733);
nand NAND2_4274(II22735,II22725,II22733);
nand NAND2_4275(II22724,II22734,II22735);
nand NAND2_4276(II22741,WX7284,WX7348);
nand NAND2_4277(II22742,WX7284,II22741);
nand NAND2_4278(II22743,WX7348,II22741);
nand NAND2_4279(II22740,II22742,II22743);
nand NAND2_4280(II22748,II22724,II22740);
nand NAND2_4281(II22749,II22724,II22748);
nand NAND2_4282(II22750,II22740,II22748);
nand NAND2_4283(WX7388,II22749,II22750);
nand NAND2_4284(II22757,WX7467,WX7158);
nand NAND2_4285(II22758,WX7467,II22757);
nand NAND2_4286(II22759,WX7158,II22757);
nand NAND2_4287(II22756,II22758,II22759);
nand NAND2_4288(II22764,WX7222,II22756);
nand NAND2_4289(II22765,WX7222,II22764);
nand NAND2_4290(II22766,II22756,II22764);
nand NAND2_4291(II22755,II22765,II22766);
nand NAND2_4292(II22772,WX7286,WX7350);
nand NAND2_4293(II22773,WX7286,II22772);
nand NAND2_4294(II22774,WX7350,II22772);
nand NAND2_4295(II22771,II22773,II22774);
nand NAND2_4296(II22779,II22755,II22771);
nand NAND2_4297(II22780,II22755,II22779);
nand NAND2_4298(II22781,II22771,II22779);
nand NAND2_4299(WX7389,II22780,II22781);
nand NAND2_4300(II22788,WX7467,WX7160);
nand NAND2_4301(II22789,WX7467,II22788);
nand NAND2_4302(II22790,WX7160,II22788);
nand NAND2_4303(II22787,II22789,II22790);
nand NAND2_4304(II22795,WX7224,II22787);
nand NAND2_4305(II22796,WX7224,II22795);
nand NAND2_4306(II22797,II22787,II22795);
nand NAND2_4307(II22786,II22796,II22797);
nand NAND2_4308(II22803,WX7288,WX7352);
nand NAND2_4309(II22804,WX7288,II22803);
nand NAND2_4310(II22805,WX7352,II22803);
nand NAND2_4311(II22802,II22804,II22805);
nand NAND2_4312(II22810,II22786,II22802);
nand NAND2_4313(II22811,II22786,II22810);
nand NAND2_4314(II22812,II22802,II22810);
nand NAND2_4315(WX7390,II22811,II22812);
nand NAND2_4316(II22819,WX7467,WX7162);
nand NAND2_4317(II22820,WX7467,II22819);
nand NAND2_4318(II22821,WX7162,II22819);
nand NAND2_4319(II22818,II22820,II22821);
nand NAND2_4320(II22826,WX7226,II22818);
nand NAND2_4321(II22827,WX7226,II22826);
nand NAND2_4322(II22828,II22818,II22826);
nand NAND2_4323(II22817,II22827,II22828);
nand NAND2_4324(II22834,WX7290,WX7354);
nand NAND2_4325(II22835,WX7290,II22834);
nand NAND2_4326(II22836,WX7354,II22834);
nand NAND2_4327(II22833,II22835,II22836);
nand NAND2_4328(II22841,II22817,II22833);
nand NAND2_4329(II22842,II22817,II22841);
nand NAND2_4330(II22843,II22833,II22841);
nand NAND2_4331(WX7391,II22842,II22843);
nand NAND2_4332(II22850,WX7467,WX7164);
nand NAND2_4333(II22851,WX7467,II22850);
nand NAND2_4334(II22852,WX7164,II22850);
nand NAND2_4335(II22849,II22851,II22852);
nand NAND2_4336(II22857,WX7228,II22849);
nand NAND2_4337(II22858,WX7228,II22857);
nand NAND2_4338(II22859,II22849,II22857);
nand NAND2_4339(II22848,II22858,II22859);
nand NAND2_4340(II22865,WX7292,WX7356);
nand NAND2_4341(II22866,WX7292,II22865);
nand NAND2_4342(II22867,WX7356,II22865);
nand NAND2_4343(II22864,II22866,II22867);
nand NAND2_4344(II22872,II22848,II22864);
nand NAND2_4345(II22873,II22848,II22872);
nand NAND2_4346(II22874,II22864,II22872);
nand NAND2_4347(WX7392,II22873,II22874);
nand NAND2_4348(II22881,WX7467,WX7166);
nand NAND2_4349(II22882,WX7467,II22881);
nand NAND2_4350(II22883,WX7166,II22881);
nand NAND2_4351(II22880,II22882,II22883);
nand NAND2_4352(II22888,WX7230,II22880);
nand NAND2_4353(II22889,WX7230,II22888);
nand NAND2_4354(II22890,II22880,II22888);
nand NAND2_4355(II22879,II22889,II22890);
nand NAND2_4356(II22896,WX7294,WX7358);
nand NAND2_4357(II22897,WX7294,II22896);
nand NAND2_4358(II22898,WX7358,II22896);
nand NAND2_4359(II22895,II22897,II22898);
nand NAND2_4360(II22903,II22879,II22895);
nand NAND2_4361(II22904,II22879,II22903);
nand NAND2_4362(II22905,II22895,II22903);
nand NAND2_4363(WX7393,II22904,II22905);
nand NAND2_4364(II22912,WX7467,WX7168);
nand NAND2_4365(II22913,WX7467,II22912);
nand NAND2_4366(II22914,WX7168,II22912);
nand NAND2_4367(II22911,II22913,II22914);
nand NAND2_4368(II22919,WX7232,II22911);
nand NAND2_4369(II22920,WX7232,II22919);
nand NAND2_4370(II22921,II22911,II22919);
nand NAND2_4371(II22910,II22920,II22921);
nand NAND2_4372(II22927,WX7296,WX7360);
nand NAND2_4373(II22928,WX7296,II22927);
nand NAND2_4374(II22929,WX7360,II22927);
nand NAND2_4375(II22926,II22928,II22929);
nand NAND2_4376(II22934,II22910,II22926);
nand NAND2_4377(II22935,II22910,II22934);
nand NAND2_4378(II22936,II22926,II22934);
nand NAND2_4379(WX7394,II22935,II22936);
nand NAND2_4380(II22943,WX7467,WX7170);
nand NAND2_4381(II22944,WX7467,II22943);
nand NAND2_4382(II22945,WX7170,II22943);
nand NAND2_4383(II22942,II22944,II22945);
nand NAND2_4384(II22950,WX7234,II22942);
nand NAND2_4385(II22951,WX7234,II22950);
nand NAND2_4386(II22952,II22942,II22950);
nand NAND2_4387(II22941,II22951,II22952);
nand NAND2_4388(II22958,WX7298,WX7362);
nand NAND2_4389(II22959,WX7298,II22958);
nand NAND2_4390(II22960,WX7362,II22958);
nand NAND2_4391(II22957,II22959,II22960);
nand NAND2_4392(II22965,II22941,II22957);
nand NAND2_4393(II22966,II22941,II22965);
nand NAND2_4394(II22967,II22957,II22965);
nand NAND2_4395(WX7395,II22966,II22967);
nand NAND2_4396(II22974,WX7467,WX7172);
nand NAND2_4397(II22975,WX7467,II22974);
nand NAND2_4398(II22976,WX7172,II22974);
nand NAND2_4399(II22973,II22975,II22976);
nand NAND2_4400(II22981,WX7236,II22973);
nand NAND2_4401(II22982,WX7236,II22981);
nand NAND2_4402(II22983,II22973,II22981);
nand NAND2_4403(II22972,II22982,II22983);
nand NAND2_4404(II22989,WX7300,WX7364);
nand NAND2_4405(II22990,WX7300,II22989);
nand NAND2_4406(II22991,WX7364,II22989);
nand NAND2_4407(II22988,II22990,II22991);
nand NAND2_4408(II22996,II22972,II22988);
nand NAND2_4409(II22997,II22972,II22996);
nand NAND2_4410(II22998,II22988,II22996);
nand NAND2_4411(WX7396,II22997,II22998);
nand NAND2_4412(II23077,WX7045,WX6950);
nand NAND2_4413(II23078,WX7045,II23077);
nand NAND2_4414(II23079,WX6950,II23077);
nand NAND2_4415(WX7471,II23078,II23079);
nand NAND2_4416(II23090,WX7046,WX6952);
nand NAND2_4417(II23091,WX7046,II23090);
nand NAND2_4418(II23092,WX6952,II23090);
nand NAND2_4419(WX7478,II23091,II23092);
nand NAND2_4420(II23103,WX7047,WX6954);
nand NAND2_4421(II23104,WX7047,II23103);
nand NAND2_4422(II23105,WX6954,II23103);
nand NAND2_4423(WX7485,II23104,II23105);
nand NAND2_4424(II23116,WX7048,WX6956);
nand NAND2_4425(II23117,WX7048,II23116);
nand NAND2_4426(II23118,WX6956,II23116);
nand NAND2_4427(WX7492,II23117,II23118);
nand NAND2_4428(II23129,WX7049,WX6958);
nand NAND2_4429(II23130,WX7049,II23129);
nand NAND2_4430(II23131,WX6958,II23129);
nand NAND2_4431(WX7499,II23130,II23131);
nand NAND2_4432(II23142,WX7050,WX6960);
nand NAND2_4433(II23143,WX7050,II23142);
nand NAND2_4434(II23144,WX6960,II23142);
nand NAND2_4435(WX7506,II23143,II23144);
nand NAND2_4436(II23155,WX7051,WX6962);
nand NAND2_4437(II23156,WX7051,II23155);
nand NAND2_4438(II23157,WX6962,II23155);
nand NAND2_4439(WX7513,II23156,II23157);
nand NAND2_4440(II23168,WX7052,WX6964);
nand NAND2_4441(II23169,WX7052,II23168);
nand NAND2_4442(II23170,WX6964,II23168);
nand NAND2_4443(WX7520,II23169,II23170);
nand NAND2_4444(II23181,WX7053,WX6966);
nand NAND2_4445(II23182,WX7053,II23181);
nand NAND2_4446(II23183,WX6966,II23181);
nand NAND2_4447(WX7527,II23182,II23183);
nand NAND2_4448(II23194,WX7054,WX6968);
nand NAND2_4449(II23195,WX7054,II23194);
nand NAND2_4450(II23196,WX6968,II23194);
nand NAND2_4451(WX7534,II23195,II23196);
nand NAND2_4452(II23207,WX7055,WX6970);
nand NAND2_4453(II23208,WX7055,II23207);
nand NAND2_4454(II23209,WX6970,II23207);
nand NAND2_4455(WX7541,II23208,II23209);
nand NAND2_4456(II23220,WX7056,WX6972);
nand NAND2_4457(II23221,WX7056,II23220);
nand NAND2_4458(II23222,WX6972,II23220);
nand NAND2_4459(WX7548,II23221,II23222);
nand NAND2_4460(II23233,WX7057,WX6974);
nand NAND2_4461(II23234,WX7057,II23233);
nand NAND2_4462(II23235,WX6974,II23233);
nand NAND2_4463(WX7555,II23234,II23235);
nand NAND2_4464(II23246,WX7058,WX6976);
nand NAND2_4465(II23247,WX7058,II23246);
nand NAND2_4466(II23248,WX6976,II23246);
nand NAND2_4467(WX7562,II23247,II23248);
nand NAND2_4468(II23259,WX7059,WX6978);
nand NAND2_4469(II23260,WX7059,II23259);
nand NAND2_4470(II23261,WX6978,II23259);
nand NAND2_4471(WX7569,II23260,II23261);
nand NAND2_4472(II23272,WX7060,WX6980);
nand NAND2_4473(II23273,WX7060,II23272);
nand NAND2_4474(II23274,WX6980,II23272);
nand NAND2_4475(WX7576,II23273,II23274);
nand NAND2_4476(II23285,WX7061,WX6982);
nand NAND2_4477(II23286,WX7061,II23285);
nand NAND2_4478(II23287,WX6982,II23285);
nand NAND2_4479(WX7583,II23286,II23287);
nand NAND2_4480(II23298,WX7062,WX6984);
nand NAND2_4481(II23299,WX7062,II23298);
nand NAND2_4482(II23300,WX6984,II23298);
nand NAND2_4483(WX7590,II23299,II23300);
nand NAND2_4484(II23311,WX7063,WX6986);
nand NAND2_4485(II23312,WX7063,II23311);
nand NAND2_4486(II23313,WX6986,II23311);
nand NAND2_4487(WX7597,II23312,II23313);
nand NAND2_4488(II23324,WX7064,WX6988);
nand NAND2_4489(II23325,WX7064,II23324);
nand NAND2_4490(II23326,WX6988,II23324);
nand NAND2_4491(WX7604,II23325,II23326);
nand NAND2_4492(II23337,WX7065,WX6990);
nand NAND2_4493(II23338,WX7065,II23337);
nand NAND2_4494(II23339,WX6990,II23337);
nand NAND2_4495(WX7611,II23338,II23339);
nand NAND2_4496(II23350,WX7066,WX6992);
nand NAND2_4497(II23351,WX7066,II23350);
nand NAND2_4498(II23352,WX6992,II23350);
nand NAND2_4499(WX7618,II23351,II23352);
nand NAND2_4500(II23363,WX7067,WX6994);
nand NAND2_4501(II23364,WX7067,II23363);
nand NAND2_4502(II23365,WX6994,II23363);
nand NAND2_4503(WX7625,II23364,II23365);
nand NAND2_4504(II23376,WX7068,WX6996);
nand NAND2_4505(II23377,WX7068,II23376);
nand NAND2_4506(II23378,WX6996,II23376);
nand NAND2_4507(WX7632,II23377,II23378);
nand NAND2_4508(II23389,WX7069,WX6998);
nand NAND2_4509(II23390,WX7069,II23389);
nand NAND2_4510(II23391,WX6998,II23389);
nand NAND2_4511(WX7639,II23390,II23391);
nand NAND2_4512(II23402,WX7070,WX7000);
nand NAND2_4513(II23403,WX7070,II23402);
nand NAND2_4514(II23404,WX7000,II23402);
nand NAND2_4515(WX7646,II23403,II23404);
nand NAND2_4516(II23415,WX7071,WX7002);
nand NAND2_4517(II23416,WX7071,II23415);
nand NAND2_4518(II23417,WX7002,II23415);
nand NAND2_4519(WX7653,II23416,II23417);
nand NAND2_4520(II23428,WX7072,WX7004);
nand NAND2_4521(II23429,WX7072,II23428);
nand NAND2_4522(II23430,WX7004,II23428);
nand NAND2_4523(WX7660,II23429,II23430);
nand NAND2_4524(II23441,WX7073,WX7006);
nand NAND2_4525(II23442,WX7073,II23441);
nand NAND2_4526(II23443,WX7006,II23441);
nand NAND2_4527(WX7667,II23442,II23443);
nand NAND2_4528(II23454,WX7074,WX7008);
nand NAND2_4529(II23455,WX7074,II23454);
nand NAND2_4530(II23456,WX7008,II23454);
nand NAND2_4531(WX7674,II23455,II23456);
nand NAND2_4532(II23467,WX7075,WX7010);
nand NAND2_4533(II23468,WX7075,II23467);
nand NAND2_4534(II23469,WX7010,II23467);
nand NAND2_4535(WX7681,II23468,II23469);
nand NAND2_4536(II23480,WX7076,WX7012);
nand NAND2_4537(II23481,WX7076,II23480);
nand NAND2_4538(II23482,WX7012,II23480);
nand NAND2_4539(WX7688,II23481,II23482);
nand NAND2_4540(II23495,WX7092,CRC_OUT_4_31);
nand NAND2_4541(II23496,WX7092,II23495);
nand NAND2_4542(II23497,CRC_OUT_4_31,II23495);
nand NAND2_4543(II23494,II23496,II23497);
nand NAND2_4544(II23502,CRC_OUT_4_15,II23494);
nand NAND2_4545(II23503,CRC_OUT_4_15,II23502);
nand NAND2_4546(II23504,II23494,II23502);
nand NAND2_4547(WX7696,II23503,II23504);
nand NAND2_4548(II23510,WX7097,CRC_OUT_4_31);
nand NAND2_4549(II23511,WX7097,II23510);
nand NAND2_4550(II23512,CRC_OUT_4_31,II23510);
nand NAND2_4551(II23509,II23511,II23512);
nand NAND2_4552(II23517,CRC_OUT_4_10,II23509);
nand NAND2_4553(II23518,CRC_OUT_4_10,II23517);
nand NAND2_4554(II23519,II23509,II23517);
nand NAND2_4555(WX7697,II23518,II23519);
nand NAND2_4556(II23525,WX7104,CRC_OUT_4_31);
nand NAND2_4557(II23526,WX7104,II23525);
nand NAND2_4558(II23527,CRC_OUT_4_31,II23525);
nand NAND2_4559(II23524,II23526,II23527);
nand NAND2_4560(II23532,CRC_OUT_4_3,II23524);
nand NAND2_4561(II23533,CRC_OUT_4_3,II23532);
nand NAND2_4562(II23534,II23524,II23532);
nand NAND2_4563(WX7698,II23533,II23534);
nand NAND2_4564(II23539,WX7108,CRC_OUT_4_31);
nand NAND2_4565(II23540,WX7108,II23539);
nand NAND2_4566(II23541,CRC_OUT_4_31,II23539);
nand NAND2_4567(WX7699,II23540,II23541);
nand NAND2_4568(II23546,WX7077,CRC_OUT_4_30);
nand NAND2_4569(II23547,WX7077,II23546);
nand NAND2_4570(II23548,CRC_OUT_4_30,II23546);
nand NAND2_4571(WX7700,II23547,II23548);
nand NAND2_4572(II23553,WX7078,CRC_OUT_4_29);
nand NAND2_4573(II23554,WX7078,II23553);
nand NAND2_4574(II23555,CRC_OUT_4_29,II23553);
nand NAND2_4575(WX7701,II23554,II23555);
nand NAND2_4576(II23560,WX7079,CRC_OUT_4_28);
nand NAND2_4577(II23561,WX7079,II23560);
nand NAND2_4578(II23562,CRC_OUT_4_28,II23560);
nand NAND2_4579(WX7702,II23561,II23562);
nand NAND2_4580(II23567,WX7080,CRC_OUT_4_27);
nand NAND2_4581(II23568,WX7080,II23567);
nand NAND2_4582(II23569,CRC_OUT_4_27,II23567);
nand NAND2_4583(WX7703,II23568,II23569);
nand NAND2_4584(II23574,WX7081,CRC_OUT_4_26);
nand NAND2_4585(II23575,WX7081,II23574);
nand NAND2_4586(II23576,CRC_OUT_4_26,II23574);
nand NAND2_4587(WX7704,II23575,II23576);
nand NAND2_4588(II23581,WX7082,CRC_OUT_4_25);
nand NAND2_4589(II23582,WX7082,II23581);
nand NAND2_4590(II23583,CRC_OUT_4_25,II23581);
nand NAND2_4591(WX7705,II23582,II23583);
nand NAND2_4592(II23588,WX7083,CRC_OUT_4_24);
nand NAND2_4593(II23589,WX7083,II23588);
nand NAND2_4594(II23590,CRC_OUT_4_24,II23588);
nand NAND2_4595(WX7706,II23589,II23590);
nand NAND2_4596(II23595,WX7084,CRC_OUT_4_23);
nand NAND2_4597(II23596,WX7084,II23595);
nand NAND2_4598(II23597,CRC_OUT_4_23,II23595);
nand NAND2_4599(WX7707,II23596,II23597);
nand NAND2_4600(II23602,WX7085,CRC_OUT_4_22);
nand NAND2_4601(II23603,WX7085,II23602);
nand NAND2_4602(II23604,CRC_OUT_4_22,II23602);
nand NAND2_4603(WX7708,II23603,II23604);
nand NAND2_4604(II23609,WX7086,CRC_OUT_4_21);
nand NAND2_4605(II23610,WX7086,II23609);
nand NAND2_4606(II23611,CRC_OUT_4_21,II23609);
nand NAND2_4607(WX7709,II23610,II23611);
nand NAND2_4608(II23616,WX7087,CRC_OUT_4_20);
nand NAND2_4609(II23617,WX7087,II23616);
nand NAND2_4610(II23618,CRC_OUT_4_20,II23616);
nand NAND2_4611(WX7710,II23617,II23618);
nand NAND2_4612(II23623,WX7088,CRC_OUT_4_19);
nand NAND2_4613(II23624,WX7088,II23623);
nand NAND2_4614(II23625,CRC_OUT_4_19,II23623);
nand NAND2_4615(WX7711,II23624,II23625);
nand NAND2_4616(II23630,WX7089,CRC_OUT_4_18);
nand NAND2_4617(II23631,WX7089,II23630);
nand NAND2_4618(II23632,CRC_OUT_4_18,II23630);
nand NAND2_4619(WX7712,II23631,II23632);
nand NAND2_4620(II23637,WX7090,CRC_OUT_4_17);
nand NAND2_4621(II23638,WX7090,II23637);
nand NAND2_4622(II23639,CRC_OUT_4_17,II23637);
nand NAND2_4623(WX7713,II23638,II23639);
nand NAND2_4624(II23644,WX7091,CRC_OUT_4_16);
nand NAND2_4625(II23645,WX7091,II23644);
nand NAND2_4626(II23646,CRC_OUT_4_16,II23644);
nand NAND2_4627(WX7714,II23645,II23646);
nand NAND2_4628(II23651,WX7093,CRC_OUT_4_14);
nand NAND2_4629(II23652,WX7093,II23651);
nand NAND2_4630(II23653,CRC_OUT_4_14,II23651);
nand NAND2_4631(WX7715,II23652,II23653);
nand NAND2_4632(II23658,WX7094,CRC_OUT_4_13);
nand NAND2_4633(II23659,WX7094,II23658);
nand NAND2_4634(II23660,CRC_OUT_4_13,II23658);
nand NAND2_4635(WX7716,II23659,II23660);
nand NAND2_4636(II23665,WX7095,CRC_OUT_4_12);
nand NAND2_4637(II23666,WX7095,II23665);
nand NAND2_4638(II23667,CRC_OUT_4_12,II23665);
nand NAND2_4639(WX7717,II23666,II23667);
nand NAND2_4640(II23672,WX7096,CRC_OUT_4_11);
nand NAND2_4641(II23673,WX7096,II23672);
nand NAND2_4642(II23674,CRC_OUT_4_11,II23672);
nand NAND2_4643(WX7718,II23673,II23674);
nand NAND2_4644(II23679,WX7098,CRC_OUT_4_9);
nand NAND2_4645(II23680,WX7098,II23679);
nand NAND2_4646(II23681,CRC_OUT_4_9,II23679);
nand NAND2_4647(WX7719,II23680,II23681);
nand NAND2_4648(II23686,WX7099,CRC_OUT_4_8);
nand NAND2_4649(II23687,WX7099,II23686);
nand NAND2_4650(II23688,CRC_OUT_4_8,II23686);
nand NAND2_4651(WX7720,II23687,II23688);
nand NAND2_4652(II23693,WX7100,CRC_OUT_4_7);
nand NAND2_4653(II23694,WX7100,II23693);
nand NAND2_4654(II23695,CRC_OUT_4_7,II23693);
nand NAND2_4655(WX7721,II23694,II23695);
nand NAND2_4656(II23700,WX7101,CRC_OUT_4_6);
nand NAND2_4657(II23701,WX7101,II23700);
nand NAND2_4658(II23702,CRC_OUT_4_6,II23700);
nand NAND2_4659(WX7722,II23701,II23702);
nand NAND2_4660(II23707,WX7102,CRC_OUT_4_5);
nand NAND2_4661(II23708,WX7102,II23707);
nand NAND2_4662(II23709,CRC_OUT_4_5,II23707);
nand NAND2_4663(WX7723,II23708,II23709);
nand NAND2_4664(II23714,WX7103,CRC_OUT_4_4);
nand NAND2_4665(II23715,WX7103,II23714);
nand NAND2_4666(II23716,CRC_OUT_4_4,II23714);
nand NAND2_4667(WX7724,II23715,II23716);
nand NAND2_4668(II23721,WX7105,CRC_OUT_4_2);
nand NAND2_4669(II23722,WX7105,II23721);
nand NAND2_4670(II23723,CRC_OUT_4_2,II23721);
nand NAND2_4671(WX7725,II23722,II23723);
nand NAND2_4672(II23728,WX7106,CRC_OUT_4_1);
nand NAND2_4673(II23729,WX7106,II23728);
nand NAND2_4674(II23730,CRC_OUT_4_1,II23728);
nand NAND2_4675(WX7726,II23729,II23730);
nand NAND2_4676(II23735,WX7107,CRC_OUT_4_0);
nand NAND2_4677(II23736,WX7107,II23735);
nand NAND2_4678(II23737,CRC_OUT_4_0,II23735);
nand NAND2_4679(WX7727,II23736,II23737);
nand NAND2_4680(II26018,WX8759,WX8403);
nand NAND2_4681(II26019,WX8759,II26018);
nand NAND2_4682(II26020,WX8403,II26018);
nand NAND2_4683(II26017,II26019,II26020);
nand NAND2_4684(II26025,WX8467,II26017);
nand NAND2_4685(II26026,WX8467,II26025);
nand NAND2_4686(II26027,II26017,II26025);
nand NAND2_4687(II26016,II26026,II26027);
nand NAND2_4688(II26033,WX8531,WX8595);
nand NAND2_4689(II26034,WX8531,II26033);
nand NAND2_4690(II26035,WX8595,II26033);
nand NAND2_4691(II26032,II26034,II26035);
nand NAND2_4692(II26040,II26016,II26032);
nand NAND2_4693(II26041,II26016,II26040);
nand NAND2_4694(II26042,II26032,II26040);
nand NAND2_4695(WX8658,II26041,II26042);
nand NAND2_4696(II26049,WX8759,WX8405);
nand NAND2_4697(II26050,WX8759,II26049);
nand NAND2_4698(II26051,WX8405,II26049);
nand NAND2_4699(II26048,II26050,II26051);
nand NAND2_4700(II26056,WX8469,II26048);
nand NAND2_4701(II26057,WX8469,II26056);
nand NAND2_4702(II26058,II26048,II26056);
nand NAND2_4703(II26047,II26057,II26058);
nand NAND2_4704(II26064,WX8533,WX8597);
nand NAND2_4705(II26065,WX8533,II26064);
nand NAND2_4706(II26066,WX8597,II26064);
nand NAND2_4707(II26063,II26065,II26066);
nand NAND2_4708(II26071,II26047,II26063);
nand NAND2_4709(II26072,II26047,II26071);
nand NAND2_4710(II26073,II26063,II26071);
nand NAND2_4711(WX8659,II26072,II26073);
nand NAND2_4712(II26080,WX8759,WX8407);
nand NAND2_4713(II26081,WX8759,II26080);
nand NAND2_4714(II26082,WX8407,II26080);
nand NAND2_4715(II26079,II26081,II26082);
nand NAND2_4716(II26087,WX8471,II26079);
nand NAND2_4717(II26088,WX8471,II26087);
nand NAND2_4718(II26089,II26079,II26087);
nand NAND2_4719(II26078,II26088,II26089);
nand NAND2_4720(II26095,WX8535,WX8599);
nand NAND2_4721(II26096,WX8535,II26095);
nand NAND2_4722(II26097,WX8599,II26095);
nand NAND2_4723(II26094,II26096,II26097);
nand NAND2_4724(II26102,II26078,II26094);
nand NAND2_4725(II26103,II26078,II26102);
nand NAND2_4726(II26104,II26094,II26102);
nand NAND2_4727(WX8660,II26103,II26104);
nand NAND2_4728(II26111,WX8759,WX8409);
nand NAND2_4729(II26112,WX8759,II26111);
nand NAND2_4730(II26113,WX8409,II26111);
nand NAND2_4731(II26110,II26112,II26113);
nand NAND2_4732(II26118,WX8473,II26110);
nand NAND2_4733(II26119,WX8473,II26118);
nand NAND2_4734(II26120,II26110,II26118);
nand NAND2_4735(II26109,II26119,II26120);
nand NAND2_4736(II26126,WX8537,WX8601);
nand NAND2_4737(II26127,WX8537,II26126);
nand NAND2_4738(II26128,WX8601,II26126);
nand NAND2_4739(II26125,II26127,II26128);
nand NAND2_4740(II26133,II26109,II26125);
nand NAND2_4741(II26134,II26109,II26133);
nand NAND2_4742(II26135,II26125,II26133);
nand NAND2_4743(WX8661,II26134,II26135);
nand NAND2_4744(II26142,WX8759,WX8411);
nand NAND2_4745(II26143,WX8759,II26142);
nand NAND2_4746(II26144,WX8411,II26142);
nand NAND2_4747(II26141,II26143,II26144);
nand NAND2_4748(II26149,WX8475,II26141);
nand NAND2_4749(II26150,WX8475,II26149);
nand NAND2_4750(II26151,II26141,II26149);
nand NAND2_4751(II26140,II26150,II26151);
nand NAND2_4752(II26157,WX8539,WX8603);
nand NAND2_4753(II26158,WX8539,II26157);
nand NAND2_4754(II26159,WX8603,II26157);
nand NAND2_4755(II26156,II26158,II26159);
nand NAND2_4756(II26164,II26140,II26156);
nand NAND2_4757(II26165,II26140,II26164);
nand NAND2_4758(II26166,II26156,II26164);
nand NAND2_4759(WX8662,II26165,II26166);
nand NAND2_4760(II26173,WX8759,WX8413);
nand NAND2_4761(II26174,WX8759,II26173);
nand NAND2_4762(II26175,WX8413,II26173);
nand NAND2_4763(II26172,II26174,II26175);
nand NAND2_4764(II26180,WX8477,II26172);
nand NAND2_4765(II26181,WX8477,II26180);
nand NAND2_4766(II26182,II26172,II26180);
nand NAND2_4767(II26171,II26181,II26182);
nand NAND2_4768(II26188,WX8541,WX8605);
nand NAND2_4769(II26189,WX8541,II26188);
nand NAND2_4770(II26190,WX8605,II26188);
nand NAND2_4771(II26187,II26189,II26190);
nand NAND2_4772(II26195,II26171,II26187);
nand NAND2_4773(II26196,II26171,II26195);
nand NAND2_4774(II26197,II26187,II26195);
nand NAND2_4775(WX8663,II26196,II26197);
nand NAND2_4776(II26204,WX8759,WX8415);
nand NAND2_4777(II26205,WX8759,II26204);
nand NAND2_4778(II26206,WX8415,II26204);
nand NAND2_4779(II26203,II26205,II26206);
nand NAND2_4780(II26211,WX8479,II26203);
nand NAND2_4781(II26212,WX8479,II26211);
nand NAND2_4782(II26213,II26203,II26211);
nand NAND2_4783(II26202,II26212,II26213);
nand NAND2_4784(II26219,WX8543,WX8607);
nand NAND2_4785(II26220,WX8543,II26219);
nand NAND2_4786(II26221,WX8607,II26219);
nand NAND2_4787(II26218,II26220,II26221);
nand NAND2_4788(II26226,II26202,II26218);
nand NAND2_4789(II26227,II26202,II26226);
nand NAND2_4790(II26228,II26218,II26226);
nand NAND2_4791(WX8664,II26227,II26228);
nand NAND2_4792(II26235,WX8759,WX8417);
nand NAND2_4793(II26236,WX8759,II26235);
nand NAND2_4794(II26237,WX8417,II26235);
nand NAND2_4795(II26234,II26236,II26237);
nand NAND2_4796(II26242,WX8481,II26234);
nand NAND2_4797(II26243,WX8481,II26242);
nand NAND2_4798(II26244,II26234,II26242);
nand NAND2_4799(II26233,II26243,II26244);
nand NAND2_4800(II26250,WX8545,WX8609);
nand NAND2_4801(II26251,WX8545,II26250);
nand NAND2_4802(II26252,WX8609,II26250);
nand NAND2_4803(II26249,II26251,II26252);
nand NAND2_4804(II26257,II26233,II26249);
nand NAND2_4805(II26258,II26233,II26257);
nand NAND2_4806(II26259,II26249,II26257);
nand NAND2_4807(WX8665,II26258,II26259);
nand NAND2_4808(II26266,WX8759,WX8419);
nand NAND2_4809(II26267,WX8759,II26266);
nand NAND2_4810(II26268,WX8419,II26266);
nand NAND2_4811(II26265,II26267,II26268);
nand NAND2_4812(II26273,WX8483,II26265);
nand NAND2_4813(II26274,WX8483,II26273);
nand NAND2_4814(II26275,II26265,II26273);
nand NAND2_4815(II26264,II26274,II26275);
nand NAND2_4816(II26281,WX8547,WX8611);
nand NAND2_4817(II26282,WX8547,II26281);
nand NAND2_4818(II26283,WX8611,II26281);
nand NAND2_4819(II26280,II26282,II26283);
nand NAND2_4820(II26288,II26264,II26280);
nand NAND2_4821(II26289,II26264,II26288);
nand NAND2_4822(II26290,II26280,II26288);
nand NAND2_4823(WX8666,II26289,II26290);
nand NAND2_4824(II26297,WX8759,WX8421);
nand NAND2_4825(II26298,WX8759,II26297);
nand NAND2_4826(II26299,WX8421,II26297);
nand NAND2_4827(II26296,II26298,II26299);
nand NAND2_4828(II26304,WX8485,II26296);
nand NAND2_4829(II26305,WX8485,II26304);
nand NAND2_4830(II26306,II26296,II26304);
nand NAND2_4831(II26295,II26305,II26306);
nand NAND2_4832(II26312,WX8549,WX8613);
nand NAND2_4833(II26313,WX8549,II26312);
nand NAND2_4834(II26314,WX8613,II26312);
nand NAND2_4835(II26311,II26313,II26314);
nand NAND2_4836(II26319,II26295,II26311);
nand NAND2_4837(II26320,II26295,II26319);
nand NAND2_4838(II26321,II26311,II26319);
nand NAND2_4839(WX8667,II26320,II26321);
nand NAND2_4840(II26328,WX8759,WX8423);
nand NAND2_4841(II26329,WX8759,II26328);
nand NAND2_4842(II26330,WX8423,II26328);
nand NAND2_4843(II26327,II26329,II26330);
nand NAND2_4844(II26335,WX8487,II26327);
nand NAND2_4845(II26336,WX8487,II26335);
nand NAND2_4846(II26337,II26327,II26335);
nand NAND2_4847(II26326,II26336,II26337);
nand NAND2_4848(II26343,WX8551,WX8615);
nand NAND2_4849(II26344,WX8551,II26343);
nand NAND2_4850(II26345,WX8615,II26343);
nand NAND2_4851(II26342,II26344,II26345);
nand NAND2_4852(II26350,II26326,II26342);
nand NAND2_4853(II26351,II26326,II26350);
nand NAND2_4854(II26352,II26342,II26350);
nand NAND2_4855(WX8668,II26351,II26352);
nand NAND2_4856(II26359,WX8759,WX8425);
nand NAND2_4857(II26360,WX8759,II26359);
nand NAND2_4858(II26361,WX8425,II26359);
nand NAND2_4859(II26358,II26360,II26361);
nand NAND2_4860(II26366,WX8489,II26358);
nand NAND2_4861(II26367,WX8489,II26366);
nand NAND2_4862(II26368,II26358,II26366);
nand NAND2_4863(II26357,II26367,II26368);
nand NAND2_4864(II26374,WX8553,WX8617);
nand NAND2_4865(II26375,WX8553,II26374);
nand NAND2_4866(II26376,WX8617,II26374);
nand NAND2_4867(II26373,II26375,II26376);
nand NAND2_4868(II26381,II26357,II26373);
nand NAND2_4869(II26382,II26357,II26381);
nand NAND2_4870(II26383,II26373,II26381);
nand NAND2_4871(WX8669,II26382,II26383);
nand NAND2_4872(II26390,WX8759,WX8427);
nand NAND2_4873(II26391,WX8759,II26390);
nand NAND2_4874(II26392,WX8427,II26390);
nand NAND2_4875(II26389,II26391,II26392);
nand NAND2_4876(II26397,WX8491,II26389);
nand NAND2_4877(II26398,WX8491,II26397);
nand NAND2_4878(II26399,II26389,II26397);
nand NAND2_4879(II26388,II26398,II26399);
nand NAND2_4880(II26405,WX8555,WX8619);
nand NAND2_4881(II26406,WX8555,II26405);
nand NAND2_4882(II26407,WX8619,II26405);
nand NAND2_4883(II26404,II26406,II26407);
nand NAND2_4884(II26412,II26388,II26404);
nand NAND2_4885(II26413,II26388,II26412);
nand NAND2_4886(II26414,II26404,II26412);
nand NAND2_4887(WX8670,II26413,II26414);
nand NAND2_4888(II26421,WX8759,WX8429);
nand NAND2_4889(II26422,WX8759,II26421);
nand NAND2_4890(II26423,WX8429,II26421);
nand NAND2_4891(II26420,II26422,II26423);
nand NAND2_4892(II26428,WX8493,II26420);
nand NAND2_4893(II26429,WX8493,II26428);
nand NAND2_4894(II26430,II26420,II26428);
nand NAND2_4895(II26419,II26429,II26430);
nand NAND2_4896(II26436,WX8557,WX8621);
nand NAND2_4897(II26437,WX8557,II26436);
nand NAND2_4898(II26438,WX8621,II26436);
nand NAND2_4899(II26435,II26437,II26438);
nand NAND2_4900(II26443,II26419,II26435);
nand NAND2_4901(II26444,II26419,II26443);
nand NAND2_4902(II26445,II26435,II26443);
nand NAND2_4903(WX8671,II26444,II26445);
nand NAND2_4904(II26452,WX8759,WX8431);
nand NAND2_4905(II26453,WX8759,II26452);
nand NAND2_4906(II26454,WX8431,II26452);
nand NAND2_4907(II26451,II26453,II26454);
nand NAND2_4908(II26459,WX8495,II26451);
nand NAND2_4909(II26460,WX8495,II26459);
nand NAND2_4910(II26461,II26451,II26459);
nand NAND2_4911(II26450,II26460,II26461);
nand NAND2_4912(II26467,WX8559,WX8623);
nand NAND2_4913(II26468,WX8559,II26467);
nand NAND2_4914(II26469,WX8623,II26467);
nand NAND2_4915(II26466,II26468,II26469);
nand NAND2_4916(II26474,II26450,II26466);
nand NAND2_4917(II26475,II26450,II26474);
nand NAND2_4918(II26476,II26466,II26474);
nand NAND2_4919(WX8672,II26475,II26476);
nand NAND2_4920(II26483,WX8759,WX8433);
nand NAND2_4921(II26484,WX8759,II26483);
nand NAND2_4922(II26485,WX8433,II26483);
nand NAND2_4923(II26482,II26484,II26485);
nand NAND2_4924(II26490,WX8497,II26482);
nand NAND2_4925(II26491,WX8497,II26490);
nand NAND2_4926(II26492,II26482,II26490);
nand NAND2_4927(II26481,II26491,II26492);
nand NAND2_4928(II26498,WX8561,WX8625);
nand NAND2_4929(II26499,WX8561,II26498);
nand NAND2_4930(II26500,WX8625,II26498);
nand NAND2_4931(II26497,II26499,II26500);
nand NAND2_4932(II26505,II26481,II26497);
nand NAND2_4933(II26506,II26481,II26505);
nand NAND2_4934(II26507,II26497,II26505);
nand NAND2_4935(WX8673,II26506,II26507);
nand NAND2_4936(II26514,WX8760,WX8435);
nand NAND2_4937(II26515,WX8760,II26514);
nand NAND2_4938(II26516,WX8435,II26514);
nand NAND2_4939(II26513,II26515,II26516);
nand NAND2_4940(II26521,WX8499,II26513);
nand NAND2_4941(II26522,WX8499,II26521);
nand NAND2_4942(II26523,II26513,II26521);
nand NAND2_4943(II26512,II26522,II26523);
nand NAND2_4944(II26529,WX8563,WX8627);
nand NAND2_4945(II26530,WX8563,II26529);
nand NAND2_4946(II26531,WX8627,II26529);
nand NAND2_4947(II26528,II26530,II26531);
nand NAND2_4948(II26536,II26512,II26528);
nand NAND2_4949(II26537,II26512,II26536);
nand NAND2_4950(II26538,II26528,II26536);
nand NAND2_4951(WX8674,II26537,II26538);
nand NAND2_4952(II26545,WX8760,WX8437);
nand NAND2_4953(II26546,WX8760,II26545);
nand NAND2_4954(II26547,WX8437,II26545);
nand NAND2_4955(II26544,II26546,II26547);
nand NAND2_4956(II26552,WX8501,II26544);
nand NAND2_4957(II26553,WX8501,II26552);
nand NAND2_4958(II26554,II26544,II26552);
nand NAND2_4959(II26543,II26553,II26554);
nand NAND2_4960(II26560,WX8565,WX8629);
nand NAND2_4961(II26561,WX8565,II26560);
nand NAND2_4962(II26562,WX8629,II26560);
nand NAND2_4963(II26559,II26561,II26562);
nand NAND2_4964(II26567,II26543,II26559);
nand NAND2_4965(II26568,II26543,II26567);
nand NAND2_4966(II26569,II26559,II26567);
nand NAND2_4967(WX8675,II26568,II26569);
nand NAND2_4968(II26576,WX8760,WX8439);
nand NAND2_4969(II26577,WX8760,II26576);
nand NAND2_4970(II26578,WX8439,II26576);
nand NAND2_4971(II26575,II26577,II26578);
nand NAND2_4972(II26583,WX8503,II26575);
nand NAND2_4973(II26584,WX8503,II26583);
nand NAND2_4974(II26585,II26575,II26583);
nand NAND2_4975(II26574,II26584,II26585);
nand NAND2_4976(II26591,WX8567,WX8631);
nand NAND2_4977(II26592,WX8567,II26591);
nand NAND2_4978(II26593,WX8631,II26591);
nand NAND2_4979(II26590,II26592,II26593);
nand NAND2_4980(II26598,II26574,II26590);
nand NAND2_4981(II26599,II26574,II26598);
nand NAND2_4982(II26600,II26590,II26598);
nand NAND2_4983(WX8676,II26599,II26600);
nand NAND2_4984(II26607,WX8760,WX8441);
nand NAND2_4985(II26608,WX8760,II26607);
nand NAND2_4986(II26609,WX8441,II26607);
nand NAND2_4987(II26606,II26608,II26609);
nand NAND2_4988(II26614,WX8505,II26606);
nand NAND2_4989(II26615,WX8505,II26614);
nand NAND2_4990(II26616,II26606,II26614);
nand NAND2_4991(II26605,II26615,II26616);
nand NAND2_4992(II26622,WX8569,WX8633);
nand NAND2_4993(II26623,WX8569,II26622);
nand NAND2_4994(II26624,WX8633,II26622);
nand NAND2_4995(II26621,II26623,II26624);
nand NAND2_4996(II26629,II26605,II26621);
nand NAND2_4997(II26630,II26605,II26629);
nand NAND2_4998(II26631,II26621,II26629);
nand NAND2_4999(WX8677,II26630,II26631);
nand NAND2_5000(II26638,WX8760,WX8443);
nand NAND2_5001(II26639,WX8760,II26638);
nand NAND2_5002(II26640,WX8443,II26638);
nand NAND2_5003(II26637,II26639,II26640);
nand NAND2_5004(II26645,WX8507,II26637);
nand NAND2_5005(II26646,WX8507,II26645);
nand NAND2_5006(II26647,II26637,II26645);
nand NAND2_5007(II26636,II26646,II26647);
nand NAND2_5008(II26653,WX8571,WX8635);
nand NAND2_5009(II26654,WX8571,II26653);
nand NAND2_5010(II26655,WX8635,II26653);
nand NAND2_5011(II26652,II26654,II26655);
nand NAND2_5012(II26660,II26636,II26652);
nand NAND2_5013(II26661,II26636,II26660);
nand NAND2_5014(II26662,II26652,II26660);
nand NAND2_5015(WX8678,II26661,II26662);
nand NAND2_5016(II26669,WX8760,WX8445);
nand NAND2_5017(II26670,WX8760,II26669);
nand NAND2_5018(II26671,WX8445,II26669);
nand NAND2_5019(II26668,II26670,II26671);
nand NAND2_5020(II26676,WX8509,II26668);
nand NAND2_5021(II26677,WX8509,II26676);
nand NAND2_5022(II26678,II26668,II26676);
nand NAND2_5023(II26667,II26677,II26678);
nand NAND2_5024(II26684,WX8573,WX8637);
nand NAND2_5025(II26685,WX8573,II26684);
nand NAND2_5026(II26686,WX8637,II26684);
nand NAND2_5027(II26683,II26685,II26686);
nand NAND2_5028(II26691,II26667,II26683);
nand NAND2_5029(II26692,II26667,II26691);
nand NAND2_5030(II26693,II26683,II26691);
nand NAND2_5031(WX8679,II26692,II26693);
nand NAND2_5032(II26700,WX8760,WX8447);
nand NAND2_5033(II26701,WX8760,II26700);
nand NAND2_5034(II26702,WX8447,II26700);
nand NAND2_5035(II26699,II26701,II26702);
nand NAND2_5036(II26707,WX8511,II26699);
nand NAND2_5037(II26708,WX8511,II26707);
nand NAND2_5038(II26709,II26699,II26707);
nand NAND2_5039(II26698,II26708,II26709);
nand NAND2_5040(II26715,WX8575,WX8639);
nand NAND2_5041(II26716,WX8575,II26715);
nand NAND2_5042(II26717,WX8639,II26715);
nand NAND2_5043(II26714,II26716,II26717);
nand NAND2_5044(II26722,II26698,II26714);
nand NAND2_5045(II26723,II26698,II26722);
nand NAND2_5046(II26724,II26714,II26722);
nand NAND2_5047(WX8680,II26723,II26724);
nand NAND2_5048(II26731,WX8760,WX8449);
nand NAND2_5049(II26732,WX8760,II26731);
nand NAND2_5050(II26733,WX8449,II26731);
nand NAND2_5051(II26730,II26732,II26733);
nand NAND2_5052(II26738,WX8513,II26730);
nand NAND2_5053(II26739,WX8513,II26738);
nand NAND2_5054(II26740,II26730,II26738);
nand NAND2_5055(II26729,II26739,II26740);
nand NAND2_5056(II26746,WX8577,WX8641);
nand NAND2_5057(II26747,WX8577,II26746);
nand NAND2_5058(II26748,WX8641,II26746);
nand NAND2_5059(II26745,II26747,II26748);
nand NAND2_5060(II26753,II26729,II26745);
nand NAND2_5061(II26754,II26729,II26753);
nand NAND2_5062(II26755,II26745,II26753);
nand NAND2_5063(WX8681,II26754,II26755);
nand NAND2_5064(II26762,WX8760,WX8451);
nand NAND2_5065(II26763,WX8760,II26762);
nand NAND2_5066(II26764,WX8451,II26762);
nand NAND2_5067(II26761,II26763,II26764);
nand NAND2_5068(II26769,WX8515,II26761);
nand NAND2_5069(II26770,WX8515,II26769);
nand NAND2_5070(II26771,II26761,II26769);
nand NAND2_5071(II26760,II26770,II26771);
nand NAND2_5072(II26777,WX8579,WX8643);
nand NAND2_5073(II26778,WX8579,II26777);
nand NAND2_5074(II26779,WX8643,II26777);
nand NAND2_5075(II26776,II26778,II26779);
nand NAND2_5076(II26784,II26760,II26776);
nand NAND2_5077(II26785,II26760,II26784);
nand NAND2_5078(II26786,II26776,II26784);
nand NAND2_5079(WX8682,II26785,II26786);
nand NAND2_5080(II26793,WX8760,WX8453);
nand NAND2_5081(II26794,WX8760,II26793);
nand NAND2_5082(II26795,WX8453,II26793);
nand NAND2_5083(II26792,II26794,II26795);
nand NAND2_5084(II26800,WX8517,II26792);
nand NAND2_5085(II26801,WX8517,II26800);
nand NAND2_5086(II26802,II26792,II26800);
nand NAND2_5087(II26791,II26801,II26802);
nand NAND2_5088(II26808,WX8581,WX8645);
nand NAND2_5089(II26809,WX8581,II26808);
nand NAND2_5090(II26810,WX8645,II26808);
nand NAND2_5091(II26807,II26809,II26810);
nand NAND2_5092(II26815,II26791,II26807);
nand NAND2_5093(II26816,II26791,II26815);
nand NAND2_5094(II26817,II26807,II26815);
nand NAND2_5095(WX8683,II26816,II26817);
nand NAND2_5096(II26824,WX8760,WX8455);
nand NAND2_5097(II26825,WX8760,II26824);
nand NAND2_5098(II26826,WX8455,II26824);
nand NAND2_5099(II26823,II26825,II26826);
nand NAND2_5100(II26831,WX8519,II26823);
nand NAND2_5101(II26832,WX8519,II26831);
nand NAND2_5102(II26833,II26823,II26831);
nand NAND2_5103(II26822,II26832,II26833);
nand NAND2_5104(II26839,WX8583,WX8647);
nand NAND2_5105(II26840,WX8583,II26839);
nand NAND2_5106(II26841,WX8647,II26839);
nand NAND2_5107(II26838,II26840,II26841);
nand NAND2_5108(II26846,II26822,II26838);
nand NAND2_5109(II26847,II26822,II26846);
nand NAND2_5110(II26848,II26838,II26846);
nand NAND2_5111(WX8684,II26847,II26848);
nand NAND2_5112(II26855,WX8760,WX8457);
nand NAND2_5113(II26856,WX8760,II26855);
nand NAND2_5114(II26857,WX8457,II26855);
nand NAND2_5115(II26854,II26856,II26857);
nand NAND2_5116(II26862,WX8521,II26854);
nand NAND2_5117(II26863,WX8521,II26862);
nand NAND2_5118(II26864,II26854,II26862);
nand NAND2_5119(II26853,II26863,II26864);
nand NAND2_5120(II26870,WX8585,WX8649);
nand NAND2_5121(II26871,WX8585,II26870);
nand NAND2_5122(II26872,WX8649,II26870);
nand NAND2_5123(II26869,II26871,II26872);
nand NAND2_5124(II26877,II26853,II26869);
nand NAND2_5125(II26878,II26853,II26877);
nand NAND2_5126(II26879,II26869,II26877);
nand NAND2_5127(WX8685,II26878,II26879);
nand NAND2_5128(II26886,WX8760,WX8459);
nand NAND2_5129(II26887,WX8760,II26886);
nand NAND2_5130(II26888,WX8459,II26886);
nand NAND2_5131(II26885,II26887,II26888);
nand NAND2_5132(II26893,WX8523,II26885);
nand NAND2_5133(II26894,WX8523,II26893);
nand NAND2_5134(II26895,II26885,II26893);
nand NAND2_5135(II26884,II26894,II26895);
nand NAND2_5136(II26901,WX8587,WX8651);
nand NAND2_5137(II26902,WX8587,II26901);
nand NAND2_5138(II26903,WX8651,II26901);
nand NAND2_5139(II26900,II26902,II26903);
nand NAND2_5140(II26908,II26884,II26900);
nand NAND2_5141(II26909,II26884,II26908);
nand NAND2_5142(II26910,II26900,II26908);
nand NAND2_5143(WX8686,II26909,II26910);
nand NAND2_5144(II26917,WX8760,WX8461);
nand NAND2_5145(II26918,WX8760,II26917);
nand NAND2_5146(II26919,WX8461,II26917);
nand NAND2_5147(II26916,II26918,II26919);
nand NAND2_5148(II26924,WX8525,II26916);
nand NAND2_5149(II26925,WX8525,II26924);
nand NAND2_5150(II26926,II26916,II26924);
nand NAND2_5151(II26915,II26925,II26926);
nand NAND2_5152(II26932,WX8589,WX8653);
nand NAND2_5153(II26933,WX8589,II26932);
nand NAND2_5154(II26934,WX8653,II26932);
nand NAND2_5155(II26931,II26933,II26934);
nand NAND2_5156(II26939,II26915,II26931);
nand NAND2_5157(II26940,II26915,II26939);
nand NAND2_5158(II26941,II26931,II26939);
nand NAND2_5159(WX8687,II26940,II26941);
nand NAND2_5160(II26948,WX8760,WX8463);
nand NAND2_5161(II26949,WX8760,II26948);
nand NAND2_5162(II26950,WX8463,II26948);
nand NAND2_5163(II26947,II26949,II26950);
nand NAND2_5164(II26955,WX8527,II26947);
nand NAND2_5165(II26956,WX8527,II26955);
nand NAND2_5166(II26957,II26947,II26955);
nand NAND2_5167(II26946,II26956,II26957);
nand NAND2_5168(II26963,WX8591,WX8655);
nand NAND2_5169(II26964,WX8591,II26963);
nand NAND2_5170(II26965,WX8655,II26963);
nand NAND2_5171(II26962,II26964,II26965);
nand NAND2_5172(II26970,II26946,II26962);
nand NAND2_5173(II26971,II26946,II26970);
nand NAND2_5174(II26972,II26962,II26970);
nand NAND2_5175(WX8688,II26971,II26972);
nand NAND2_5176(II26979,WX8760,WX8465);
nand NAND2_5177(II26980,WX8760,II26979);
nand NAND2_5178(II26981,WX8465,II26979);
nand NAND2_5179(II26978,II26980,II26981);
nand NAND2_5180(II26986,WX8529,II26978);
nand NAND2_5181(II26987,WX8529,II26986);
nand NAND2_5182(II26988,II26978,II26986);
nand NAND2_5183(II26977,II26987,II26988);
nand NAND2_5184(II26994,WX8593,WX8657);
nand NAND2_5185(II26995,WX8593,II26994);
nand NAND2_5186(II26996,WX8657,II26994);
nand NAND2_5187(II26993,II26995,II26996);
nand NAND2_5188(II27001,II26977,II26993);
nand NAND2_5189(II27002,II26977,II27001);
nand NAND2_5190(II27003,II26993,II27001);
nand NAND2_5191(WX8689,II27002,II27003);
nand NAND2_5192(II27082,WX8338,WX8243);
nand NAND2_5193(II27083,WX8338,II27082);
nand NAND2_5194(II27084,WX8243,II27082);
nand NAND2_5195(WX8764,II27083,II27084);
nand NAND2_5196(II27095,WX8339,WX8245);
nand NAND2_5197(II27096,WX8339,II27095);
nand NAND2_5198(II27097,WX8245,II27095);
nand NAND2_5199(WX8771,II27096,II27097);
nand NAND2_5200(II27108,WX8340,WX8247);
nand NAND2_5201(II27109,WX8340,II27108);
nand NAND2_5202(II27110,WX8247,II27108);
nand NAND2_5203(WX8778,II27109,II27110);
nand NAND2_5204(II27121,WX8341,WX8249);
nand NAND2_5205(II27122,WX8341,II27121);
nand NAND2_5206(II27123,WX8249,II27121);
nand NAND2_5207(WX8785,II27122,II27123);
nand NAND2_5208(II27134,WX8342,WX8251);
nand NAND2_5209(II27135,WX8342,II27134);
nand NAND2_5210(II27136,WX8251,II27134);
nand NAND2_5211(WX8792,II27135,II27136);
nand NAND2_5212(II27147,WX8343,WX8253);
nand NAND2_5213(II27148,WX8343,II27147);
nand NAND2_5214(II27149,WX8253,II27147);
nand NAND2_5215(WX8799,II27148,II27149);
nand NAND2_5216(II27160,WX8344,WX8255);
nand NAND2_5217(II27161,WX8344,II27160);
nand NAND2_5218(II27162,WX8255,II27160);
nand NAND2_5219(WX8806,II27161,II27162);
nand NAND2_5220(II27173,WX8345,WX8257);
nand NAND2_5221(II27174,WX8345,II27173);
nand NAND2_5222(II27175,WX8257,II27173);
nand NAND2_5223(WX8813,II27174,II27175);
nand NAND2_5224(II27186,WX8346,WX8259);
nand NAND2_5225(II27187,WX8346,II27186);
nand NAND2_5226(II27188,WX8259,II27186);
nand NAND2_5227(WX8820,II27187,II27188);
nand NAND2_5228(II27199,WX8347,WX8261);
nand NAND2_5229(II27200,WX8347,II27199);
nand NAND2_5230(II27201,WX8261,II27199);
nand NAND2_5231(WX8827,II27200,II27201);
nand NAND2_5232(II27212,WX8348,WX8263);
nand NAND2_5233(II27213,WX8348,II27212);
nand NAND2_5234(II27214,WX8263,II27212);
nand NAND2_5235(WX8834,II27213,II27214);
nand NAND2_5236(II27225,WX8349,WX8265);
nand NAND2_5237(II27226,WX8349,II27225);
nand NAND2_5238(II27227,WX8265,II27225);
nand NAND2_5239(WX8841,II27226,II27227);
nand NAND2_5240(II27238,WX8350,WX8267);
nand NAND2_5241(II27239,WX8350,II27238);
nand NAND2_5242(II27240,WX8267,II27238);
nand NAND2_5243(WX8848,II27239,II27240);
nand NAND2_5244(II27251,WX8351,WX8269);
nand NAND2_5245(II27252,WX8351,II27251);
nand NAND2_5246(II27253,WX8269,II27251);
nand NAND2_5247(WX8855,II27252,II27253);
nand NAND2_5248(II27264,WX8352,WX8271);
nand NAND2_5249(II27265,WX8352,II27264);
nand NAND2_5250(II27266,WX8271,II27264);
nand NAND2_5251(WX8862,II27265,II27266);
nand NAND2_5252(II27277,WX8353,WX8273);
nand NAND2_5253(II27278,WX8353,II27277);
nand NAND2_5254(II27279,WX8273,II27277);
nand NAND2_5255(WX8869,II27278,II27279);
nand NAND2_5256(II27290,WX8354,WX8275);
nand NAND2_5257(II27291,WX8354,II27290);
nand NAND2_5258(II27292,WX8275,II27290);
nand NAND2_5259(WX8876,II27291,II27292);
nand NAND2_5260(II27303,WX8355,WX8277);
nand NAND2_5261(II27304,WX8355,II27303);
nand NAND2_5262(II27305,WX8277,II27303);
nand NAND2_5263(WX8883,II27304,II27305);
nand NAND2_5264(II27316,WX8356,WX8279);
nand NAND2_5265(II27317,WX8356,II27316);
nand NAND2_5266(II27318,WX8279,II27316);
nand NAND2_5267(WX8890,II27317,II27318);
nand NAND2_5268(II27329,WX8357,WX8281);
nand NAND2_5269(II27330,WX8357,II27329);
nand NAND2_5270(II27331,WX8281,II27329);
nand NAND2_5271(WX8897,II27330,II27331);
nand NAND2_5272(II27342,WX8358,WX8283);
nand NAND2_5273(II27343,WX8358,II27342);
nand NAND2_5274(II27344,WX8283,II27342);
nand NAND2_5275(WX8904,II27343,II27344);
nand NAND2_5276(II27355,WX8359,WX8285);
nand NAND2_5277(II27356,WX8359,II27355);
nand NAND2_5278(II27357,WX8285,II27355);
nand NAND2_5279(WX8911,II27356,II27357);
nand NAND2_5280(II27368,WX8360,WX8287);
nand NAND2_5281(II27369,WX8360,II27368);
nand NAND2_5282(II27370,WX8287,II27368);
nand NAND2_5283(WX8918,II27369,II27370);
nand NAND2_5284(II27381,WX8361,WX8289);
nand NAND2_5285(II27382,WX8361,II27381);
nand NAND2_5286(II27383,WX8289,II27381);
nand NAND2_5287(WX8925,II27382,II27383);
nand NAND2_5288(II27394,WX8362,WX8291);
nand NAND2_5289(II27395,WX8362,II27394);
nand NAND2_5290(II27396,WX8291,II27394);
nand NAND2_5291(WX8932,II27395,II27396);
nand NAND2_5292(II27407,WX8363,WX8293);
nand NAND2_5293(II27408,WX8363,II27407);
nand NAND2_5294(II27409,WX8293,II27407);
nand NAND2_5295(WX8939,II27408,II27409);
nand NAND2_5296(II27420,WX8364,WX8295);
nand NAND2_5297(II27421,WX8364,II27420);
nand NAND2_5298(II27422,WX8295,II27420);
nand NAND2_5299(WX8946,II27421,II27422);
nand NAND2_5300(II27433,WX8365,WX8297);
nand NAND2_5301(II27434,WX8365,II27433);
nand NAND2_5302(II27435,WX8297,II27433);
nand NAND2_5303(WX8953,II27434,II27435);
nand NAND2_5304(II27446,WX8366,WX8299);
nand NAND2_5305(II27447,WX8366,II27446);
nand NAND2_5306(II27448,WX8299,II27446);
nand NAND2_5307(WX8960,II27447,II27448);
nand NAND2_5308(II27459,WX8367,WX8301);
nand NAND2_5309(II27460,WX8367,II27459);
nand NAND2_5310(II27461,WX8301,II27459);
nand NAND2_5311(WX8967,II27460,II27461);
nand NAND2_5312(II27472,WX8368,WX8303);
nand NAND2_5313(II27473,WX8368,II27472);
nand NAND2_5314(II27474,WX8303,II27472);
nand NAND2_5315(WX8974,II27473,II27474);
nand NAND2_5316(II27485,WX8369,WX8305);
nand NAND2_5317(II27486,WX8369,II27485);
nand NAND2_5318(II27487,WX8305,II27485);
nand NAND2_5319(WX8981,II27486,II27487);
nand NAND2_5320(II27500,WX8385,CRC_OUT_3_31);
nand NAND2_5321(II27501,WX8385,II27500);
nand NAND2_5322(II27502,CRC_OUT_3_31,II27500);
nand NAND2_5323(II27499,II27501,II27502);
nand NAND2_5324(II27507,CRC_OUT_3_15,II27499);
nand NAND2_5325(II27508,CRC_OUT_3_15,II27507);
nand NAND2_5326(II27509,II27499,II27507);
nand NAND2_5327(WX8989,II27508,II27509);
nand NAND2_5328(II27515,WX8390,CRC_OUT_3_31);
nand NAND2_5329(II27516,WX8390,II27515);
nand NAND2_5330(II27517,CRC_OUT_3_31,II27515);
nand NAND2_5331(II27514,II27516,II27517);
nand NAND2_5332(II27522,CRC_OUT_3_10,II27514);
nand NAND2_5333(II27523,CRC_OUT_3_10,II27522);
nand NAND2_5334(II27524,II27514,II27522);
nand NAND2_5335(WX8990,II27523,II27524);
nand NAND2_5336(II27530,WX8397,CRC_OUT_3_31);
nand NAND2_5337(II27531,WX8397,II27530);
nand NAND2_5338(II27532,CRC_OUT_3_31,II27530);
nand NAND2_5339(II27529,II27531,II27532);
nand NAND2_5340(II27537,CRC_OUT_3_3,II27529);
nand NAND2_5341(II27538,CRC_OUT_3_3,II27537);
nand NAND2_5342(II27539,II27529,II27537);
nand NAND2_5343(WX8991,II27538,II27539);
nand NAND2_5344(II27544,WX8401,CRC_OUT_3_31);
nand NAND2_5345(II27545,WX8401,II27544);
nand NAND2_5346(II27546,CRC_OUT_3_31,II27544);
nand NAND2_5347(WX8992,II27545,II27546);
nand NAND2_5348(II27551,WX8370,CRC_OUT_3_30);
nand NAND2_5349(II27552,WX8370,II27551);
nand NAND2_5350(II27553,CRC_OUT_3_30,II27551);
nand NAND2_5351(WX8993,II27552,II27553);
nand NAND2_5352(II27558,WX8371,CRC_OUT_3_29);
nand NAND2_5353(II27559,WX8371,II27558);
nand NAND2_5354(II27560,CRC_OUT_3_29,II27558);
nand NAND2_5355(WX8994,II27559,II27560);
nand NAND2_5356(II27565,WX8372,CRC_OUT_3_28);
nand NAND2_5357(II27566,WX8372,II27565);
nand NAND2_5358(II27567,CRC_OUT_3_28,II27565);
nand NAND2_5359(WX8995,II27566,II27567);
nand NAND2_5360(II27572,WX8373,CRC_OUT_3_27);
nand NAND2_5361(II27573,WX8373,II27572);
nand NAND2_5362(II27574,CRC_OUT_3_27,II27572);
nand NAND2_5363(WX8996,II27573,II27574);
nand NAND2_5364(II27579,WX8374,CRC_OUT_3_26);
nand NAND2_5365(II27580,WX8374,II27579);
nand NAND2_5366(II27581,CRC_OUT_3_26,II27579);
nand NAND2_5367(WX8997,II27580,II27581);
nand NAND2_5368(II27586,WX8375,CRC_OUT_3_25);
nand NAND2_5369(II27587,WX8375,II27586);
nand NAND2_5370(II27588,CRC_OUT_3_25,II27586);
nand NAND2_5371(WX8998,II27587,II27588);
nand NAND2_5372(II27593,WX8376,CRC_OUT_3_24);
nand NAND2_5373(II27594,WX8376,II27593);
nand NAND2_5374(II27595,CRC_OUT_3_24,II27593);
nand NAND2_5375(WX8999,II27594,II27595);
nand NAND2_5376(II27600,WX8377,CRC_OUT_3_23);
nand NAND2_5377(II27601,WX8377,II27600);
nand NAND2_5378(II27602,CRC_OUT_3_23,II27600);
nand NAND2_5379(WX9000,II27601,II27602);
nand NAND2_5380(II27607,WX8378,CRC_OUT_3_22);
nand NAND2_5381(II27608,WX8378,II27607);
nand NAND2_5382(II27609,CRC_OUT_3_22,II27607);
nand NAND2_5383(WX9001,II27608,II27609);
nand NAND2_5384(II27614,WX8379,CRC_OUT_3_21);
nand NAND2_5385(II27615,WX8379,II27614);
nand NAND2_5386(II27616,CRC_OUT_3_21,II27614);
nand NAND2_5387(WX9002,II27615,II27616);
nand NAND2_5388(II27621,WX8380,CRC_OUT_3_20);
nand NAND2_5389(II27622,WX8380,II27621);
nand NAND2_5390(II27623,CRC_OUT_3_20,II27621);
nand NAND2_5391(WX9003,II27622,II27623);
nand NAND2_5392(II27628,WX8381,CRC_OUT_3_19);
nand NAND2_5393(II27629,WX8381,II27628);
nand NAND2_5394(II27630,CRC_OUT_3_19,II27628);
nand NAND2_5395(WX9004,II27629,II27630);
nand NAND2_5396(II27635,WX8382,CRC_OUT_3_18);
nand NAND2_5397(II27636,WX8382,II27635);
nand NAND2_5398(II27637,CRC_OUT_3_18,II27635);
nand NAND2_5399(WX9005,II27636,II27637);
nand NAND2_5400(II27642,WX8383,CRC_OUT_3_17);
nand NAND2_5401(II27643,WX8383,II27642);
nand NAND2_5402(II27644,CRC_OUT_3_17,II27642);
nand NAND2_5403(WX9006,II27643,II27644);
nand NAND2_5404(II27649,WX8384,CRC_OUT_3_16);
nand NAND2_5405(II27650,WX8384,II27649);
nand NAND2_5406(II27651,CRC_OUT_3_16,II27649);
nand NAND2_5407(WX9007,II27650,II27651);
nand NAND2_5408(II27656,WX8386,CRC_OUT_3_14);
nand NAND2_5409(II27657,WX8386,II27656);
nand NAND2_5410(II27658,CRC_OUT_3_14,II27656);
nand NAND2_5411(WX9008,II27657,II27658);
nand NAND2_5412(II27663,WX8387,CRC_OUT_3_13);
nand NAND2_5413(II27664,WX8387,II27663);
nand NAND2_5414(II27665,CRC_OUT_3_13,II27663);
nand NAND2_5415(WX9009,II27664,II27665);
nand NAND2_5416(II27670,WX8388,CRC_OUT_3_12);
nand NAND2_5417(II27671,WX8388,II27670);
nand NAND2_5418(II27672,CRC_OUT_3_12,II27670);
nand NAND2_5419(WX9010,II27671,II27672);
nand NAND2_5420(II27677,WX8389,CRC_OUT_3_11);
nand NAND2_5421(II27678,WX8389,II27677);
nand NAND2_5422(II27679,CRC_OUT_3_11,II27677);
nand NAND2_5423(WX9011,II27678,II27679);
nand NAND2_5424(II27684,WX8391,CRC_OUT_3_9);
nand NAND2_5425(II27685,WX8391,II27684);
nand NAND2_5426(II27686,CRC_OUT_3_9,II27684);
nand NAND2_5427(WX9012,II27685,II27686);
nand NAND2_5428(II27691,WX8392,CRC_OUT_3_8);
nand NAND2_5429(II27692,WX8392,II27691);
nand NAND2_5430(II27693,CRC_OUT_3_8,II27691);
nand NAND2_5431(WX9013,II27692,II27693);
nand NAND2_5432(II27698,WX8393,CRC_OUT_3_7);
nand NAND2_5433(II27699,WX8393,II27698);
nand NAND2_5434(II27700,CRC_OUT_3_7,II27698);
nand NAND2_5435(WX9014,II27699,II27700);
nand NAND2_5436(II27705,WX8394,CRC_OUT_3_6);
nand NAND2_5437(II27706,WX8394,II27705);
nand NAND2_5438(II27707,CRC_OUT_3_6,II27705);
nand NAND2_5439(WX9015,II27706,II27707);
nand NAND2_5440(II27712,WX8395,CRC_OUT_3_5);
nand NAND2_5441(II27713,WX8395,II27712);
nand NAND2_5442(II27714,CRC_OUT_3_5,II27712);
nand NAND2_5443(WX9016,II27713,II27714);
nand NAND2_5444(II27719,WX8396,CRC_OUT_3_4);
nand NAND2_5445(II27720,WX8396,II27719);
nand NAND2_5446(II27721,CRC_OUT_3_4,II27719);
nand NAND2_5447(WX9017,II27720,II27721);
nand NAND2_5448(II27726,WX8398,CRC_OUT_3_2);
nand NAND2_5449(II27727,WX8398,II27726);
nand NAND2_5450(II27728,CRC_OUT_3_2,II27726);
nand NAND2_5451(WX9018,II27727,II27728);
nand NAND2_5452(II27733,WX8399,CRC_OUT_3_1);
nand NAND2_5453(II27734,WX8399,II27733);
nand NAND2_5454(II27735,CRC_OUT_3_1,II27733);
nand NAND2_5455(WX9019,II27734,II27735);
nand NAND2_5456(II27740,WX8400,CRC_OUT_3_0);
nand NAND2_5457(II27741,WX8400,II27740);
nand NAND2_5458(II27742,CRC_OUT_3_0,II27740);
nand NAND2_5459(WX9020,II27741,II27742);
nand NAND2_5460(II30023,WX10052,WX9696);
nand NAND2_5461(II30024,WX10052,II30023);
nand NAND2_5462(II30025,WX9696,II30023);
nand NAND2_5463(II30022,II30024,II30025);
nand NAND2_5464(II30030,WX9760,II30022);
nand NAND2_5465(II30031,WX9760,II30030);
nand NAND2_5466(II30032,II30022,II30030);
nand NAND2_5467(II30021,II30031,II30032);
nand NAND2_5468(II30038,WX9824,WX9888);
nand NAND2_5469(II30039,WX9824,II30038);
nand NAND2_5470(II30040,WX9888,II30038);
nand NAND2_5471(II30037,II30039,II30040);
nand NAND2_5472(II30045,II30021,II30037);
nand NAND2_5473(II30046,II30021,II30045);
nand NAND2_5474(II30047,II30037,II30045);
nand NAND2_5475(WX9951,II30046,II30047);
nand NAND2_5476(II30054,WX10052,WX9698);
nand NAND2_5477(II30055,WX10052,II30054);
nand NAND2_5478(II30056,WX9698,II30054);
nand NAND2_5479(II30053,II30055,II30056);
nand NAND2_5480(II30061,WX9762,II30053);
nand NAND2_5481(II30062,WX9762,II30061);
nand NAND2_5482(II30063,II30053,II30061);
nand NAND2_5483(II30052,II30062,II30063);
nand NAND2_5484(II30069,WX9826,WX9890);
nand NAND2_5485(II30070,WX9826,II30069);
nand NAND2_5486(II30071,WX9890,II30069);
nand NAND2_5487(II30068,II30070,II30071);
nand NAND2_5488(II30076,II30052,II30068);
nand NAND2_5489(II30077,II30052,II30076);
nand NAND2_5490(II30078,II30068,II30076);
nand NAND2_5491(WX9952,II30077,II30078);
nand NAND2_5492(II30085,WX10052,WX9700);
nand NAND2_5493(II30086,WX10052,II30085);
nand NAND2_5494(II30087,WX9700,II30085);
nand NAND2_5495(II30084,II30086,II30087);
nand NAND2_5496(II30092,WX9764,II30084);
nand NAND2_5497(II30093,WX9764,II30092);
nand NAND2_5498(II30094,II30084,II30092);
nand NAND2_5499(II30083,II30093,II30094);
nand NAND2_5500(II30100,WX9828,WX9892);
nand NAND2_5501(II30101,WX9828,II30100);
nand NAND2_5502(II30102,WX9892,II30100);
nand NAND2_5503(II30099,II30101,II30102);
nand NAND2_5504(II30107,II30083,II30099);
nand NAND2_5505(II30108,II30083,II30107);
nand NAND2_5506(II30109,II30099,II30107);
nand NAND2_5507(WX9953,II30108,II30109);
nand NAND2_5508(II30116,WX10052,WX9702);
nand NAND2_5509(II30117,WX10052,II30116);
nand NAND2_5510(II30118,WX9702,II30116);
nand NAND2_5511(II30115,II30117,II30118);
nand NAND2_5512(II30123,WX9766,II30115);
nand NAND2_5513(II30124,WX9766,II30123);
nand NAND2_5514(II30125,II30115,II30123);
nand NAND2_5515(II30114,II30124,II30125);
nand NAND2_5516(II30131,WX9830,WX9894);
nand NAND2_5517(II30132,WX9830,II30131);
nand NAND2_5518(II30133,WX9894,II30131);
nand NAND2_5519(II30130,II30132,II30133);
nand NAND2_5520(II30138,II30114,II30130);
nand NAND2_5521(II30139,II30114,II30138);
nand NAND2_5522(II30140,II30130,II30138);
nand NAND2_5523(WX9954,II30139,II30140);
nand NAND2_5524(II30147,WX10052,WX9704);
nand NAND2_5525(II30148,WX10052,II30147);
nand NAND2_5526(II30149,WX9704,II30147);
nand NAND2_5527(II30146,II30148,II30149);
nand NAND2_5528(II30154,WX9768,II30146);
nand NAND2_5529(II30155,WX9768,II30154);
nand NAND2_5530(II30156,II30146,II30154);
nand NAND2_5531(II30145,II30155,II30156);
nand NAND2_5532(II30162,WX9832,WX9896);
nand NAND2_5533(II30163,WX9832,II30162);
nand NAND2_5534(II30164,WX9896,II30162);
nand NAND2_5535(II30161,II30163,II30164);
nand NAND2_5536(II30169,II30145,II30161);
nand NAND2_5537(II30170,II30145,II30169);
nand NAND2_5538(II30171,II30161,II30169);
nand NAND2_5539(WX9955,II30170,II30171);
nand NAND2_5540(II30178,WX10052,WX9706);
nand NAND2_5541(II30179,WX10052,II30178);
nand NAND2_5542(II30180,WX9706,II30178);
nand NAND2_5543(II30177,II30179,II30180);
nand NAND2_5544(II30185,WX9770,II30177);
nand NAND2_5545(II30186,WX9770,II30185);
nand NAND2_5546(II30187,II30177,II30185);
nand NAND2_5547(II30176,II30186,II30187);
nand NAND2_5548(II30193,WX9834,WX9898);
nand NAND2_5549(II30194,WX9834,II30193);
nand NAND2_5550(II30195,WX9898,II30193);
nand NAND2_5551(II30192,II30194,II30195);
nand NAND2_5552(II30200,II30176,II30192);
nand NAND2_5553(II30201,II30176,II30200);
nand NAND2_5554(II30202,II30192,II30200);
nand NAND2_5555(WX9956,II30201,II30202);
nand NAND2_5556(II30209,WX10052,WX9708);
nand NAND2_5557(II30210,WX10052,II30209);
nand NAND2_5558(II30211,WX9708,II30209);
nand NAND2_5559(II30208,II30210,II30211);
nand NAND2_5560(II30216,WX9772,II30208);
nand NAND2_5561(II30217,WX9772,II30216);
nand NAND2_5562(II30218,II30208,II30216);
nand NAND2_5563(II30207,II30217,II30218);
nand NAND2_5564(II30224,WX9836,WX9900);
nand NAND2_5565(II30225,WX9836,II30224);
nand NAND2_5566(II30226,WX9900,II30224);
nand NAND2_5567(II30223,II30225,II30226);
nand NAND2_5568(II30231,II30207,II30223);
nand NAND2_5569(II30232,II30207,II30231);
nand NAND2_5570(II30233,II30223,II30231);
nand NAND2_5571(WX9957,II30232,II30233);
nand NAND2_5572(II30240,WX10052,WX9710);
nand NAND2_5573(II30241,WX10052,II30240);
nand NAND2_5574(II30242,WX9710,II30240);
nand NAND2_5575(II30239,II30241,II30242);
nand NAND2_5576(II30247,WX9774,II30239);
nand NAND2_5577(II30248,WX9774,II30247);
nand NAND2_5578(II30249,II30239,II30247);
nand NAND2_5579(II30238,II30248,II30249);
nand NAND2_5580(II30255,WX9838,WX9902);
nand NAND2_5581(II30256,WX9838,II30255);
nand NAND2_5582(II30257,WX9902,II30255);
nand NAND2_5583(II30254,II30256,II30257);
nand NAND2_5584(II30262,II30238,II30254);
nand NAND2_5585(II30263,II30238,II30262);
nand NAND2_5586(II30264,II30254,II30262);
nand NAND2_5587(WX9958,II30263,II30264);
nand NAND2_5588(II30271,WX10052,WX9712);
nand NAND2_5589(II30272,WX10052,II30271);
nand NAND2_5590(II30273,WX9712,II30271);
nand NAND2_5591(II30270,II30272,II30273);
nand NAND2_5592(II30278,WX9776,II30270);
nand NAND2_5593(II30279,WX9776,II30278);
nand NAND2_5594(II30280,II30270,II30278);
nand NAND2_5595(II30269,II30279,II30280);
nand NAND2_5596(II30286,WX9840,WX9904);
nand NAND2_5597(II30287,WX9840,II30286);
nand NAND2_5598(II30288,WX9904,II30286);
nand NAND2_5599(II30285,II30287,II30288);
nand NAND2_5600(II30293,II30269,II30285);
nand NAND2_5601(II30294,II30269,II30293);
nand NAND2_5602(II30295,II30285,II30293);
nand NAND2_5603(WX9959,II30294,II30295);
nand NAND2_5604(II30302,WX10052,WX9714);
nand NAND2_5605(II30303,WX10052,II30302);
nand NAND2_5606(II30304,WX9714,II30302);
nand NAND2_5607(II30301,II30303,II30304);
nand NAND2_5608(II30309,WX9778,II30301);
nand NAND2_5609(II30310,WX9778,II30309);
nand NAND2_5610(II30311,II30301,II30309);
nand NAND2_5611(II30300,II30310,II30311);
nand NAND2_5612(II30317,WX9842,WX9906);
nand NAND2_5613(II30318,WX9842,II30317);
nand NAND2_5614(II30319,WX9906,II30317);
nand NAND2_5615(II30316,II30318,II30319);
nand NAND2_5616(II30324,II30300,II30316);
nand NAND2_5617(II30325,II30300,II30324);
nand NAND2_5618(II30326,II30316,II30324);
nand NAND2_5619(WX9960,II30325,II30326);
nand NAND2_5620(II30333,WX10052,WX9716);
nand NAND2_5621(II30334,WX10052,II30333);
nand NAND2_5622(II30335,WX9716,II30333);
nand NAND2_5623(II30332,II30334,II30335);
nand NAND2_5624(II30340,WX9780,II30332);
nand NAND2_5625(II30341,WX9780,II30340);
nand NAND2_5626(II30342,II30332,II30340);
nand NAND2_5627(II30331,II30341,II30342);
nand NAND2_5628(II30348,WX9844,WX9908);
nand NAND2_5629(II30349,WX9844,II30348);
nand NAND2_5630(II30350,WX9908,II30348);
nand NAND2_5631(II30347,II30349,II30350);
nand NAND2_5632(II30355,II30331,II30347);
nand NAND2_5633(II30356,II30331,II30355);
nand NAND2_5634(II30357,II30347,II30355);
nand NAND2_5635(WX9961,II30356,II30357);
nand NAND2_5636(II30364,WX10052,WX9718);
nand NAND2_5637(II30365,WX10052,II30364);
nand NAND2_5638(II30366,WX9718,II30364);
nand NAND2_5639(II30363,II30365,II30366);
nand NAND2_5640(II30371,WX9782,II30363);
nand NAND2_5641(II30372,WX9782,II30371);
nand NAND2_5642(II30373,II30363,II30371);
nand NAND2_5643(II30362,II30372,II30373);
nand NAND2_5644(II30379,WX9846,WX9910);
nand NAND2_5645(II30380,WX9846,II30379);
nand NAND2_5646(II30381,WX9910,II30379);
nand NAND2_5647(II30378,II30380,II30381);
nand NAND2_5648(II30386,II30362,II30378);
nand NAND2_5649(II30387,II30362,II30386);
nand NAND2_5650(II30388,II30378,II30386);
nand NAND2_5651(WX9962,II30387,II30388);
nand NAND2_5652(II30395,WX10052,WX9720);
nand NAND2_5653(II30396,WX10052,II30395);
nand NAND2_5654(II30397,WX9720,II30395);
nand NAND2_5655(II30394,II30396,II30397);
nand NAND2_5656(II30402,WX9784,II30394);
nand NAND2_5657(II30403,WX9784,II30402);
nand NAND2_5658(II30404,II30394,II30402);
nand NAND2_5659(II30393,II30403,II30404);
nand NAND2_5660(II30410,WX9848,WX9912);
nand NAND2_5661(II30411,WX9848,II30410);
nand NAND2_5662(II30412,WX9912,II30410);
nand NAND2_5663(II30409,II30411,II30412);
nand NAND2_5664(II30417,II30393,II30409);
nand NAND2_5665(II30418,II30393,II30417);
nand NAND2_5666(II30419,II30409,II30417);
nand NAND2_5667(WX9963,II30418,II30419);
nand NAND2_5668(II30426,WX10052,WX9722);
nand NAND2_5669(II30427,WX10052,II30426);
nand NAND2_5670(II30428,WX9722,II30426);
nand NAND2_5671(II30425,II30427,II30428);
nand NAND2_5672(II30433,WX9786,II30425);
nand NAND2_5673(II30434,WX9786,II30433);
nand NAND2_5674(II30435,II30425,II30433);
nand NAND2_5675(II30424,II30434,II30435);
nand NAND2_5676(II30441,WX9850,WX9914);
nand NAND2_5677(II30442,WX9850,II30441);
nand NAND2_5678(II30443,WX9914,II30441);
nand NAND2_5679(II30440,II30442,II30443);
nand NAND2_5680(II30448,II30424,II30440);
nand NAND2_5681(II30449,II30424,II30448);
nand NAND2_5682(II30450,II30440,II30448);
nand NAND2_5683(WX9964,II30449,II30450);
nand NAND2_5684(II30457,WX10052,WX9724);
nand NAND2_5685(II30458,WX10052,II30457);
nand NAND2_5686(II30459,WX9724,II30457);
nand NAND2_5687(II30456,II30458,II30459);
nand NAND2_5688(II30464,WX9788,II30456);
nand NAND2_5689(II30465,WX9788,II30464);
nand NAND2_5690(II30466,II30456,II30464);
nand NAND2_5691(II30455,II30465,II30466);
nand NAND2_5692(II30472,WX9852,WX9916);
nand NAND2_5693(II30473,WX9852,II30472);
nand NAND2_5694(II30474,WX9916,II30472);
nand NAND2_5695(II30471,II30473,II30474);
nand NAND2_5696(II30479,II30455,II30471);
nand NAND2_5697(II30480,II30455,II30479);
nand NAND2_5698(II30481,II30471,II30479);
nand NAND2_5699(WX9965,II30480,II30481);
nand NAND2_5700(II30488,WX10052,WX9726);
nand NAND2_5701(II30489,WX10052,II30488);
nand NAND2_5702(II30490,WX9726,II30488);
nand NAND2_5703(II30487,II30489,II30490);
nand NAND2_5704(II30495,WX9790,II30487);
nand NAND2_5705(II30496,WX9790,II30495);
nand NAND2_5706(II30497,II30487,II30495);
nand NAND2_5707(II30486,II30496,II30497);
nand NAND2_5708(II30503,WX9854,WX9918);
nand NAND2_5709(II30504,WX9854,II30503);
nand NAND2_5710(II30505,WX9918,II30503);
nand NAND2_5711(II30502,II30504,II30505);
nand NAND2_5712(II30510,II30486,II30502);
nand NAND2_5713(II30511,II30486,II30510);
nand NAND2_5714(II30512,II30502,II30510);
nand NAND2_5715(WX9966,II30511,II30512);
nand NAND2_5716(II30519,WX10053,WX9728);
nand NAND2_5717(II30520,WX10053,II30519);
nand NAND2_5718(II30521,WX9728,II30519);
nand NAND2_5719(II30518,II30520,II30521);
nand NAND2_5720(II30526,WX9792,II30518);
nand NAND2_5721(II30527,WX9792,II30526);
nand NAND2_5722(II30528,II30518,II30526);
nand NAND2_5723(II30517,II30527,II30528);
nand NAND2_5724(II30534,WX9856,WX9920);
nand NAND2_5725(II30535,WX9856,II30534);
nand NAND2_5726(II30536,WX9920,II30534);
nand NAND2_5727(II30533,II30535,II30536);
nand NAND2_5728(II30541,II30517,II30533);
nand NAND2_5729(II30542,II30517,II30541);
nand NAND2_5730(II30543,II30533,II30541);
nand NAND2_5731(WX9967,II30542,II30543);
nand NAND2_5732(II30550,WX10053,WX9730);
nand NAND2_5733(II30551,WX10053,II30550);
nand NAND2_5734(II30552,WX9730,II30550);
nand NAND2_5735(II30549,II30551,II30552);
nand NAND2_5736(II30557,WX9794,II30549);
nand NAND2_5737(II30558,WX9794,II30557);
nand NAND2_5738(II30559,II30549,II30557);
nand NAND2_5739(II30548,II30558,II30559);
nand NAND2_5740(II30565,WX9858,WX9922);
nand NAND2_5741(II30566,WX9858,II30565);
nand NAND2_5742(II30567,WX9922,II30565);
nand NAND2_5743(II30564,II30566,II30567);
nand NAND2_5744(II30572,II30548,II30564);
nand NAND2_5745(II30573,II30548,II30572);
nand NAND2_5746(II30574,II30564,II30572);
nand NAND2_5747(WX9968,II30573,II30574);
nand NAND2_5748(II30581,WX10053,WX9732);
nand NAND2_5749(II30582,WX10053,II30581);
nand NAND2_5750(II30583,WX9732,II30581);
nand NAND2_5751(II30580,II30582,II30583);
nand NAND2_5752(II30588,WX9796,II30580);
nand NAND2_5753(II30589,WX9796,II30588);
nand NAND2_5754(II30590,II30580,II30588);
nand NAND2_5755(II30579,II30589,II30590);
nand NAND2_5756(II30596,WX9860,WX9924);
nand NAND2_5757(II30597,WX9860,II30596);
nand NAND2_5758(II30598,WX9924,II30596);
nand NAND2_5759(II30595,II30597,II30598);
nand NAND2_5760(II30603,II30579,II30595);
nand NAND2_5761(II30604,II30579,II30603);
nand NAND2_5762(II30605,II30595,II30603);
nand NAND2_5763(WX9969,II30604,II30605);
nand NAND2_5764(II30612,WX10053,WX9734);
nand NAND2_5765(II30613,WX10053,II30612);
nand NAND2_5766(II30614,WX9734,II30612);
nand NAND2_5767(II30611,II30613,II30614);
nand NAND2_5768(II30619,WX9798,II30611);
nand NAND2_5769(II30620,WX9798,II30619);
nand NAND2_5770(II30621,II30611,II30619);
nand NAND2_5771(II30610,II30620,II30621);
nand NAND2_5772(II30627,WX9862,WX9926);
nand NAND2_5773(II30628,WX9862,II30627);
nand NAND2_5774(II30629,WX9926,II30627);
nand NAND2_5775(II30626,II30628,II30629);
nand NAND2_5776(II30634,II30610,II30626);
nand NAND2_5777(II30635,II30610,II30634);
nand NAND2_5778(II30636,II30626,II30634);
nand NAND2_5779(WX9970,II30635,II30636);
nand NAND2_5780(II30643,WX10053,WX9736);
nand NAND2_5781(II30644,WX10053,II30643);
nand NAND2_5782(II30645,WX9736,II30643);
nand NAND2_5783(II30642,II30644,II30645);
nand NAND2_5784(II30650,WX9800,II30642);
nand NAND2_5785(II30651,WX9800,II30650);
nand NAND2_5786(II30652,II30642,II30650);
nand NAND2_5787(II30641,II30651,II30652);
nand NAND2_5788(II30658,WX9864,WX9928);
nand NAND2_5789(II30659,WX9864,II30658);
nand NAND2_5790(II30660,WX9928,II30658);
nand NAND2_5791(II30657,II30659,II30660);
nand NAND2_5792(II30665,II30641,II30657);
nand NAND2_5793(II30666,II30641,II30665);
nand NAND2_5794(II30667,II30657,II30665);
nand NAND2_5795(WX9971,II30666,II30667);
nand NAND2_5796(II30674,WX10053,WX9738);
nand NAND2_5797(II30675,WX10053,II30674);
nand NAND2_5798(II30676,WX9738,II30674);
nand NAND2_5799(II30673,II30675,II30676);
nand NAND2_5800(II30681,WX9802,II30673);
nand NAND2_5801(II30682,WX9802,II30681);
nand NAND2_5802(II30683,II30673,II30681);
nand NAND2_5803(II30672,II30682,II30683);
nand NAND2_5804(II30689,WX9866,WX9930);
nand NAND2_5805(II30690,WX9866,II30689);
nand NAND2_5806(II30691,WX9930,II30689);
nand NAND2_5807(II30688,II30690,II30691);
nand NAND2_5808(II30696,II30672,II30688);
nand NAND2_5809(II30697,II30672,II30696);
nand NAND2_5810(II30698,II30688,II30696);
nand NAND2_5811(WX9972,II30697,II30698);
nand NAND2_5812(II30705,WX10053,WX9740);
nand NAND2_5813(II30706,WX10053,II30705);
nand NAND2_5814(II30707,WX9740,II30705);
nand NAND2_5815(II30704,II30706,II30707);
nand NAND2_5816(II30712,WX9804,II30704);
nand NAND2_5817(II30713,WX9804,II30712);
nand NAND2_5818(II30714,II30704,II30712);
nand NAND2_5819(II30703,II30713,II30714);
nand NAND2_5820(II30720,WX9868,WX9932);
nand NAND2_5821(II30721,WX9868,II30720);
nand NAND2_5822(II30722,WX9932,II30720);
nand NAND2_5823(II30719,II30721,II30722);
nand NAND2_5824(II30727,II30703,II30719);
nand NAND2_5825(II30728,II30703,II30727);
nand NAND2_5826(II30729,II30719,II30727);
nand NAND2_5827(WX9973,II30728,II30729);
nand NAND2_5828(II30736,WX10053,WX9742);
nand NAND2_5829(II30737,WX10053,II30736);
nand NAND2_5830(II30738,WX9742,II30736);
nand NAND2_5831(II30735,II30737,II30738);
nand NAND2_5832(II30743,WX9806,II30735);
nand NAND2_5833(II30744,WX9806,II30743);
nand NAND2_5834(II30745,II30735,II30743);
nand NAND2_5835(II30734,II30744,II30745);
nand NAND2_5836(II30751,WX9870,WX9934);
nand NAND2_5837(II30752,WX9870,II30751);
nand NAND2_5838(II30753,WX9934,II30751);
nand NAND2_5839(II30750,II30752,II30753);
nand NAND2_5840(II30758,II30734,II30750);
nand NAND2_5841(II30759,II30734,II30758);
nand NAND2_5842(II30760,II30750,II30758);
nand NAND2_5843(WX9974,II30759,II30760);
nand NAND2_5844(II30767,WX10053,WX9744);
nand NAND2_5845(II30768,WX10053,II30767);
nand NAND2_5846(II30769,WX9744,II30767);
nand NAND2_5847(II30766,II30768,II30769);
nand NAND2_5848(II30774,WX9808,II30766);
nand NAND2_5849(II30775,WX9808,II30774);
nand NAND2_5850(II30776,II30766,II30774);
nand NAND2_5851(II30765,II30775,II30776);
nand NAND2_5852(II30782,WX9872,WX9936);
nand NAND2_5853(II30783,WX9872,II30782);
nand NAND2_5854(II30784,WX9936,II30782);
nand NAND2_5855(II30781,II30783,II30784);
nand NAND2_5856(II30789,II30765,II30781);
nand NAND2_5857(II30790,II30765,II30789);
nand NAND2_5858(II30791,II30781,II30789);
nand NAND2_5859(WX9975,II30790,II30791);
nand NAND2_5860(II30798,WX10053,WX9746);
nand NAND2_5861(II30799,WX10053,II30798);
nand NAND2_5862(II30800,WX9746,II30798);
nand NAND2_5863(II30797,II30799,II30800);
nand NAND2_5864(II30805,WX9810,II30797);
nand NAND2_5865(II30806,WX9810,II30805);
nand NAND2_5866(II30807,II30797,II30805);
nand NAND2_5867(II30796,II30806,II30807);
nand NAND2_5868(II30813,WX9874,WX9938);
nand NAND2_5869(II30814,WX9874,II30813);
nand NAND2_5870(II30815,WX9938,II30813);
nand NAND2_5871(II30812,II30814,II30815);
nand NAND2_5872(II30820,II30796,II30812);
nand NAND2_5873(II30821,II30796,II30820);
nand NAND2_5874(II30822,II30812,II30820);
nand NAND2_5875(WX9976,II30821,II30822);
nand NAND2_5876(II30829,WX10053,WX9748);
nand NAND2_5877(II30830,WX10053,II30829);
nand NAND2_5878(II30831,WX9748,II30829);
nand NAND2_5879(II30828,II30830,II30831);
nand NAND2_5880(II30836,WX9812,II30828);
nand NAND2_5881(II30837,WX9812,II30836);
nand NAND2_5882(II30838,II30828,II30836);
nand NAND2_5883(II30827,II30837,II30838);
nand NAND2_5884(II30844,WX9876,WX9940);
nand NAND2_5885(II30845,WX9876,II30844);
nand NAND2_5886(II30846,WX9940,II30844);
nand NAND2_5887(II30843,II30845,II30846);
nand NAND2_5888(II30851,II30827,II30843);
nand NAND2_5889(II30852,II30827,II30851);
nand NAND2_5890(II30853,II30843,II30851);
nand NAND2_5891(WX9977,II30852,II30853);
nand NAND2_5892(II30860,WX10053,WX9750);
nand NAND2_5893(II30861,WX10053,II30860);
nand NAND2_5894(II30862,WX9750,II30860);
nand NAND2_5895(II30859,II30861,II30862);
nand NAND2_5896(II30867,WX9814,II30859);
nand NAND2_5897(II30868,WX9814,II30867);
nand NAND2_5898(II30869,II30859,II30867);
nand NAND2_5899(II30858,II30868,II30869);
nand NAND2_5900(II30875,WX9878,WX9942);
nand NAND2_5901(II30876,WX9878,II30875);
nand NAND2_5902(II30877,WX9942,II30875);
nand NAND2_5903(II30874,II30876,II30877);
nand NAND2_5904(II30882,II30858,II30874);
nand NAND2_5905(II30883,II30858,II30882);
nand NAND2_5906(II30884,II30874,II30882);
nand NAND2_5907(WX9978,II30883,II30884);
nand NAND2_5908(II30891,WX10053,WX9752);
nand NAND2_5909(II30892,WX10053,II30891);
nand NAND2_5910(II30893,WX9752,II30891);
nand NAND2_5911(II30890,II30892,II30893);
nand NAND2_5912(II30898,WX9816,II30890);
nand NAND2_5913(II30899,WX9816,II30898);
nand NAND2_5914(II30900,II30890,II30898);
nand NAND2_5915(II30889,II30899,II30900);
nand NAND2_5916(II30906,WX9880,WX9944);
nand NAND2_5917(II30907,WX9880,II30906);
nand NAND2_5918(II30908,WX9944,II30906);
nand NAND2_5919(II30905,II30907,II30908);
nand NAND2_5920(II30913,II30889,II30905);
nand NAND2_5921(II30914,II30889,II30913);
nand NAND2_5922(II30915,II30905,II30913);
nand NAND2_5923(WX9979,II30914,II30915);
nand NAND2_5924(II30922,WX10053,WX9754);
nand NAND2_5925(II30923,WX10053,II30922);
nand NAND2_5926(II30924,WX9754,II30922);
nand NAND2_5927(II30921,II30923,II30924);
nand NAND2_5928(II30929,WX9818,II30921);
nand NAND2_5929(II30930,WX9818,II30929);
nand NAND2_5930(II30931,II30921,II30929);
nand NAND2_5931(II30920,II30930,II30931);
nand NAND2_5932(II30937,WX9882,WX9946);
nand NAND2_5933(II30938,WX9882,II30937);
nand NAND2_5934(II30939,WX9946,II30937);
nand NAND2_5935(II30936,II30938,II30939);
nand NAND2_5936(II30944,II30920,II30936);
nand NAND2_5937(II30945,II30920,II30944);
nand NAND2_5938(II30946,II30936,II30944);
nand NAND2_5939(WX9980,II30945,II30946);
nand NAND2_5940(II30953,WX10053,WX9756);
nand NAND2_5941(II30954,WX10053,II30953);
nand NAND2_5942(II30955,WX9756,II30953);
nand NAND2_5943(II30952,II30954,II30955);
nand NAND2_5944(II30960,WX9820,II30952);
nand NAND2_5945(II30961,WX9820,II30960);
nand NAND2_5946(II30962,II30952,II30960);
nand NAND2_5947(II30951,II30961,II30962);
nand NAND2_5948(II30968,WX9884,WX9948);
nand NAND2_5949(II30969,WX9884,II30968);
nand NAND2_5950(II30970,WX9948,II30968);
nand NAND2_5951(II30967,II30969,II30970);
nand NAND2_5952(II30975,II30951,II30967);
nand NAND2_5953(II30976,II30951,II30975);
nand NAND2_5954(II30977,II30967,II30975);
nand NAND2_5955(WX9981,II30976,II30977);
nand NAND2_5956(II30984,WX10053,WX9758);
nand NAND2_5957(II30985,WX10053,II30984);
nand NAND2_5958(II30986,WX9758,II30984);
nand NAND2_5959(II30983,II30985,II30986);
nand NAND2_5960(II30991,WX9822,II30983);
nand NAND2_5961(II30992,WX9822,II30991);
nand NAND2_5962(II30993,II30983,II30991);
nand NAND2_5963(II30982,II30992,II30993);
nand NAND2_5964(II30999,WX9886,WX9950);
nand NAND2_5965(II31000,WX9886,II30999);
nand NAND2_5966(II31001,WX9950,II30999);
nand NAND2_5967(II30998,II31000,II31001);
nand NAND2_5968(II31006,II30982,II30998);
nand NAND2_5969(II31007,II30982,II31006);
nand NAND2_5970(II31008,II30998,II31006);
nand NAND2_5971(WX9982,II31007,II31008);
nand NAND2_5972(II31087,WX9631,WX9536);
nand NAND2_5973(II31088,WX9631,II31087);
nand NAND2_5974(II31089,WX9536,II31087);
nand NAND2_5975(WX10057,II31088,II31089);
nand NAND2_5976(II31100,WX9632,WX9538);
nand NAND2_5977(II31101,WX9632,II31100);
nand NAND2_5978(II31102,WX9538,II31100);
nand NAND2_5979(WX10064,II31101,II31102);
nand NAND2_5980(II31113,WX9633,WX9540);
nand NAND2_5981(II31114,WX9633,II31113);
nand NAND2_5982(II31115,WX9540,II31113);
nand NAND2_5983(WX10071,II31114,II31115);
nand NAND2_5984(II31126,WX9634,WX9542);
nand NAND2_5985(II31127,WX9634,II31126);
nand NAND2_5986(II31128,WX9542,II31126);
nand NAND2_5987(WX10078,II31127,II31128);
nand NAND2_5988(II31139,WX9635,WX9544);
nand NAND2_5989(II31140,WX9635,II31139);
nand NAND2_5990(II31141,WX9544,II31139);
nand NAND2_5991(WX10085,II31140,II31141);
nand NAND2_5992(II31152,WX9636,WX9546);
nand NAND2_5993(II31153,WX9636,II31152);
nand NAND2_5994(II31154,WX9546,II31152);
nand NAND2_5995(WX10092,II31153,II31154);
nand NAND2_5996(II31165,WX9637,WX9548);
nand NAND2_5997(II31166,WX9637,II31165);
nand NAND2_5998(II31167,WX9548,II31165);
nand NAND2_5999(WX10099,II31166,II31167);
nand NAND2_6000(II31178,WX9638,WX9550);
nand NAND2_6001(II31179,WX9638,II31178);
nand NAND2_6002(II31180,WX9550,II31178);
nand NAND2_6003(WX10106,II31179,II31180);
nand NAND2_6004(II31191,WX9639,WX9552);
nand NAND2_6005(II31192,WX9639,II31191);
nand NAND2_6006(II31193,WX9552,II31191);
nand NAND2_6007(WX10113,II31192,II31193);
nand NAND2_6008(II31204,WX9640,WX9554);
nand NAND2_6009(II31205,WX9640,II31204);
nand NAND2_6010(II31206,WX9554,II31204);
nand NAND2_6011(WX10120,II31205,II31206);
nand NAND2_6012(II31217,WX9641,WX9556);
nand NAND2_6013(II31218,WX9641,II31217);
nand NAND2_6014(II31219,WX9556,II31217);
nand NAND2_6015(WX10127,II31218,II31219);
nand NAND2_6016(II31230,WX9642,WX9558);
nand NAND2_6017(II31231,WX9642,II31230);
nand NAND2_6018(II31232,WX9558,II31230);
nand NAND2_6019(WX10134,II31231,II31232);
nand NAND2_6020(II31243,WX9643,WX9560);
nand NAND2_6021(II31244,WX9643,II31243);
nand NAND2_6022(II31245,WX9560,II31243);
nand NAND2_6023(WX10141,II31244,II31245);
nand NAND2_6024(II31256,WX9644,WX9562);
nand NAND2_6025(II31257,WX9644,II31256);
nand NAND2_6026(II31258,WX9562,II31256);
nand NAND2_6027(WX10148,II31257,II31258);
nand NAND2_6028(II31269,WX9645,WX9564);
nand NAND2_6029(II31270,WX9645,II31269);
nand NAND2_6030(II31271,WX9564,II31269);
nand NAND2_6031(WX10155,II31270,II31271);
nand NAND2_6032(II31282,WX9646,WX9566);
nand NAND2_6033(II31283,WX9646,II31282);
nand NAND2_6034(II31284,WX9566,II31282);
nand NAND2_6035(WX10162,II31283,II31284);
nand NAND2_6036(II31295,WX9647,WX9568);
nand NAND2_6037(II31296,WX9647,II31295);
nand NAND2_6038(II31297,WX9568,II31295);
nand NAND2_6039(WX10169,II31296,II31297);
nand NAND2_6040(II31308,WX9648,WX9570);
nand NAND2_6041(II31309,WX9648,II31308);
nand NAND2_6042(II31310,WX9570,II31308);
nand NAND2_6043(WX10176,II31309,II31310);
nand NAND2_6044(II31321,WX9649,WX9572);
nand NAND2_6045(II31322,WX9649,II31321);
nand NAND2_6046(II31323,WX9572,II31321);
nand NAND2_6047(WX10183,II31322,II31323);
nand NAND2_6048(II31334,WX9650,WX9574);
nand NAND2_6049(II31335,WX9650,II31334);
nand NAND2_6050(II31336,WX9574,II31334);
nand NAND2_6051(WX10190,II31335,II31336);
nand NAND2_6052(II31347,WX9651,WX9576);
nand NAND2_6053(II31348,WX9651,II31347);
nand NAND2_6054(II31349,WX9576,II31347);
nand NAND2_6055(WX10197,II31348,II31349);
nand NAND2_6056(II31360,WX9652,WX9578);
nand NAND2_6057(II31361,WX9652,II31360);
nand NAND2_6058(II31362,WX9578,II31360);
nand NAND2_6059(WX10204,II31361,II31362);
nand NAND2_6060(II31373,WX9653,WX9580);
nand NAND2_6061(II31374,WX9653,II31373);
nand NAND2_6062(II31375,WX9580,II31373);
nand NAND2_6063(WX10211,II31374,II31375);
nand NAND2_6064(II31386,WX9654,WX9582);
nand NAND2_6065(II31387,WX9654,II31386);
nand NAND2_6066(II31388,WX9582,II31386);
nand NAND2_6067(WX10218,II31387,II31388);
nand NAND2_6068(II31399,WX9655,WX9584);
nand NAND2_6069(II31400,WX9655,II31399);
nand NAND2_6070(II31401,WX9584,II31399);
nand NAND2_6071(WX10225,II31400,II31401);
nand NAND2_6072(II31412,WX9656,WX9586);
nand NAND2_6073(II31413,WX9656,II31412);
nand NAND2_6074(II31414,WX9586,II31412);
nand NAND2_6075(WX10232,II31413,II31414);
nand NAND2_6076(II31425,WX9657,WX9588);
nand NAND2_6077(II31426,WX9657,II31425);
nand NAND2_6078(II31427,WX9588,II31425);
nand NAND2_6079(WX10239,II31426,II31427);
nand NAND2_6080(II31438,WX9658,WX9590);
nand NAND2_6081(II31439,WX9658,II31438);
nand NAND2_6082(II31440,WX9590,II31438);
nand NAND2_6083(WX10246,II31439,II31440);
nand NAND2_6084(II31451,WX9659,WX9592);
nand NAND2_6085(II31452,WX9659,II31451);
nand NAND2_6086(II31453,WX9592,II31451);
nand NAND2_6087(WX10253,II31452,II31453);
nand NAND2_6088(II31464,WX9660,WX9594);
nand NAND2_6089(II31465,WX9660,II31464);
nand NAND2_6090(II31466,WX9594,II31464);
nand NAND2_6091(WX10260,II31465,II31466);
nand NAND2_6092(II31477,WX9661,WX9596);
nand NAND2_6093(II31478,WX9661,II31477);
nand NAND2_6094(II31479,WX9596,II31477);
nand NAND2_6095(WX10267,II31478,II31479);
nand NAND2_6096(II31490,WX9662,WX9598);
nand NAND2_6097(II31491,WX9662,II31490);
nand NAND2_6098(II31492,WX9598,II31490);
nand NAND2_6099(WX10274,II31491,II31492);
nand NAND2_6100(II31505,WX9678,CRC_OUT_2_31);
nand NAND2_6101(II31506,WX9678,II31505);
nand NAND2_6102(II31507,CRC_OUT_2_31,II31505);
nand NAND2_6103(II31504,II31506,II31507);
nand NAND2_6104(II31512,CRC_OUT_2_15,II31504);
nand NAND2_6105(II31513,CRC_OUT_2_15,II31512);
nand NAND2_6106(II31514,II31504,II31512);
nand NAND2_6107(WX10282,II31513,II31514);
nand NAND2_6108(II31520,WX9683,CRC_OUT_2_31);
nand NAND2_6109(II31521,WX9683,II31520);
nand NAND2_6110(II31522,CRC_OUT_2_31,II31520);
nand NAND2_6111(II31519,II31521,II31522);
nand NAND2_6112(II31527,CRC_OUT_2_10,II31519);
nand NAND2_6113(II31528,CRC_OUT_2_10,II31527);
nand NAND2_6114(II31529,II31519,II31527);
nand NAND2_6115(WX10283,II31528,II31529);
nand NAND2_6116(II31535,WX9690,CRC_OUT_2_31);
nand NAND2_6117(II31536,WX9690,II31535);
nand NAND2_6118(II31537,CRC_OUT_2_31,II31535);
nand NAND2_6119(II31534,II31536,II31537);
nand NAND2_6120(II31542,CRC_OUT_2_3,II31534);
nand NAND2_6121(II31543,CRC_OUT_2_3,II31542);
nand NAND2_6122(II31544,II31534,II31542);
nand NAND2_6123(WX10284,II31543,II31544);
nand NAND2_6124(II31549,WX9694,CRC_OUT_2_31);
nand NAND2_6125(II31550,WX9694,II31549);
nand NAND2_6126(II31551,CRC_OUT_2_31,II31549);
nand NAND2_6127(WX10285,II31550,II31551);
nand NAND2_6128(II31556,WX9663,CRC_OUT_2_30);
nand NAND2_6129(II31557,WX9663,II31556);
nand NAND2_6130(II31558,CRC_OUT_2_30,II31556);
nand NAND2_6131(WX10286,II31557,II31558);
nand NAND2_6132(II31563,WX9664,CRC_OUT_2_29);
nand NAND2_6133(II31564,WX9664,II31563);
nand NAND2_6134(II31565,CRC_OUT_2_29,II31563);
nand NAND2_6135(WX10287,II31564,II31565);
nand NAND2_6136(II31570,WX9665,CRC_OUT_2_28);
nand NAND2_6137(II31571,WX9665,II31570);
nand NAND2_6138(II31572,CRC_OUT_2_28,II31570);
nand NAND2_6139(WX10288,II31571,II31572);
nand NAND2_6140(II31577,WX9666,CRC_OUT_2_27);
nand NAND2_6141(II31578,WX9666,II31577);
nand NAND2_6142(II31579,CRC_OUT_2_27,II31577);
nand NAND2_6143(WX10289,II31578,II31579);
nand NAND2_6144(II31584,WX9667,CRC_OUT_2_26);
nand NAND2_6145(II31585,WX9667,II31584);
nand NAND2_6146(II31586,CRC_OUT_2_26,II31584);
nand NAND2_6147(WX10290,II31585,II31586);
nand NAND2_6148(II31591,WX9668,CRC_OUT_2_25);
nand NAND2_6149(II31592,WX9668,II31591);
nand NAND2_6150(II31593,CRC_OUT_2_25,II31591);
nand NAND2_6151(WX10291,II31592,II31593);
nand NAND2_6152(II31598,WX9669,CRC_OUT_2_24);
nand NAND2_6153(II31599,WX9669,II31598);
nand NAND2_6154(II31600,CRC_OUT_2_24,II31598);
nand NAND2_6155(WX10292,II31599,II31600);
nand NAND2_6156(II31605,WX9670,CRC_OUT_2_23);
nand NAND2_6157(II31606,WX9670,II31605);
nand NAND2_6158(II31607,CRC_OUT_2_23,II31605);
nand NAND2_6159(WX10293,II31606,II31607);
nand NAND2_6160(II31612,WX9671,CRC_OUT_2_22);
nand NAND2_6161(II31613,WX9671,II31612);
nand NAND2_6162(II31614,CRC_OUT_2_22,II31612);
nand NAND2_6163(WX10294,II31613,II31614);
nand NAND2_6164(II31619,WX9672,CRC_OUT_2_21);
nand NAND2_6165(II31620,WX9672,II31619);
nand NAND2_6166(II31621,CRC_OUT_2_21,II31619);
nand NAND2_6167(WX10295,II31620,II31621);
nand NAND2_6168(II31626,WX9673,CRC_OUT_2_20);
nand NAND2_6169(II31627,WX9673,II31626);
nand NAND2_6170(II31628,CRC_OUT_2_20,II31626);
nand NAND2_6171(WX10296,II31627,II31628);
nand NAND2_6172(II31633,WX9674,CRC_OUT_2_19);
nand NAND2_6173(II31634,WX9674,II31633);
nand NAND2_6174(II31635,CRC_OUT_2_19,II31633);
nand NAND2_6175(WX10297,II31634,II31635);
nand NAND2_6176(II31640,WX9675,CRC_OUT_2_18);
nand NAND2_6177(II31641,WX9675,II31640);
nand NAND2_6178(II31642,CRC_OUT_2_18,II31640);
nand NAND2_6179(WX10298,II31641,II31642);
nand NAND2_6180(II31647,WX9676,CRC_OUT_2_17);
nand NAND2_6181(II31648,WX9676,II31647);
nand NAND2_6182(II31649,CRC_OUT_2_17,II31647);
nand NAND2_6183(WX10299,II31648,II31649);
nand NAND2_6184(II31654,WX9677,CRC_OUT_2_16);
nand NAND2_6185(II31655,WX9677,II31654);
nand NAND2_6186(II31656,CRC_OUT_2_16,II31654);
nand NAND2_6187(WX10300,II31655,II31656);
nand NAND2_6188(II31661,WX9679,CRC_OUT_2_14);
nand NAND2_6189(II31662,WX9679,II31661);
nand NAND2_6190(II31663,CRC_OUT_2_14,II31661);
nand NAND2_6191(WX10301,II31662,II31663);
nand NAND2_6192(II31668,WX9680,CRC_OUT_2_13);
nand NAND2_6193(II31669,WX9680,II31668);
nand NAND2_6194(II31670,CRC_OUT_2_13,II31668);
nand NAND2_6195(WX10302,II31669,II31670);
nand NAND2_6196(II31675,WX9681,CRC_OUT_2_12);
nand NAND2_6197(II31676,WX9681,II31675);
nand NAND2_6198(II31677,CRC_OUT_2_12,II31675);
nand NAND2_6199(WX10303,II31676,II31677);
nand NAND2_6200(II31682,WX9682,CRC_OUT_2_11);
nand NAND2_6201(II31683,WX9682,II31682);
nand NAND2_6202(II31684,CRC_OUT_2_11,II31682);
nand NAND2_6203(WX10304,II31683,II31684);
nand NAND2_6204(II31689,WX9684,CRC_OUT_2_9);
nand NAND2_6205(II31690,WX9684,II31689);
nand NAND2_6206(II31691,CRC_OUT_2_9,II31689);
nand NAND2_6207(WX10305,II31690,II31691);
nand NAND2_6208(II31696,WX9685,CRC_OUT_2_8);
nand NAND2_6209(II31697,WX9685,II31696);
nand NAND2_6210(II31698,CRC_OUT_2_8,II31696);
nand NAND2_6211(WX10306,II31697,II31698);
nand NAND2_6212(II31703,WX9686,CRC_OUT_2_7);
nand NAND2_6213(II31704,WX9686,II31703);
nand NAND2_6214(II31705,CRC_OUT_2_7,II31703);
nand NAND2_6215(WX10307,II31704,II31705);
nand NAND2_6216(II31710,WX9687,CRC_OUT_2_6);
nand NAND2_6217(II31711,WX9687,II31710);
nand NAND2_6218(II31712,CRC_OUT_2_6,II31710);
nand NAND2_6219(WX10308,II31711,II31712);
nand NAND2_6220(II31717,WX9688,CRC_OUT_2_5);
nand NAND2_6221(II31718,WX9688,II31717);
nand NAND2_6222(II31719,CRC_OUT_2_5,II31717);
nand NAND2_6223(WX10309,II31718,II31719);
nand NAND2_6224(II31724,WX9689,CRC_OUT_2_4);
nand NAND2_6225(II31725,WX9689,II31724);
nand NAND2_6226(II31726,CRC_OUT_2_4,II31724);
nand NAND2_6227(WX10310,II31725,II31726);
nand NAND2_6228(II31731,WX9691,CRC_OUT_2_2);
nand NAND2_6229(II31732,WX9691,II31731);
nand NAND2_6230(II31733,CRC_OUT_2_2,II31731);
nand NAND2_6231(WX10311,II31732,II31733);
nand NAND2_6232(II31738,WX9692,CRC_OUT_2_1);
nand NAND2_6233(II31739,WX9692,II31738);
nand NAND2_6234(II31740,CRC_OUT_2_1,II31738);
nand NAND2_6235(WX10312,II31739,II31740);
nand NAND2_6236(II31745,WX9693,CRC_OUT_2_0);
nand NAND2_6237(II31746,WX9693,II31745);
nand NAND2_6238(II31747,CRC_OUT_2_0,II31745);
nand NAND2_6239(WX10313,II31746,II31747);
nand NAND2_6240(II34028,WX11345,WX10989);
nand NAND2_6241(II34029,WX11345,II34028);
nand NAND2_6242(II34030,WX10989,II34028);
nand NAND2_6243(II34027,II34029,II34030);
nand NAND2_6244(II34035,WX11053,II34027);
nand NAND2_6245(II34036,WX11053,II34035);
nand NAND2_6246(II34037,II34027,II34035);
nand NAND2_6247(II34026,II34036,II34037);
nand NAND2_6248(II34043,WX11117,WX11181);
nand NAND2_6249(II34044,WX11117,II34043);
nand NAND2_6250(II34045,WX11181,II34043);
nand NAND2_6251(II34042,II34044,II34045);
nand NAND2_6252(II34050,II34026,II34042);
nand NAND2_6253(II34051,II34026,II34050);
nand NAND2_6254(II34052,II34042,II34050);
nand NAND2_6255(WX11244,II34051,II34052);
nand NAND2_6256(II34059,WX11345,WX10991);
nand NAND2_6257(II34060,WX11345,II34059);
nand NAND2_6258(II34061,WX10991,II34059);
nand NAND2_6259(II34058,II34060,II34061);
nand NAND2_6260(II34066,WX11055,II34058);
nand NAND2_6261(II34067,WX11055,II34066);
nand NAND2_6262(II34068,II34058,II34066);
nand NAND2_6263(II34057,II34067,II34068);
nand NAND2_6264(II34074,WX11119,WX11183);
nand NAND2_6265(II34075,WX11119,II34074);
nand NAND2_6266(II34076,WX11183,II34074);
nand NAND2_6267(II34073,II34075,II34076);
nand NAND2_6268(II34081,II34057,II34073);
nand NAND2_6269(II34082,II34057,II34081);
nand NAND2_6270(II34083,II34073,II34081);
nand NAND2_6271(WX11245,II34082,II34083);
nand NAND2_6272(II34090,WX11345,WX10993);
nand NAND2_6273(II34091,WX11345,II34090);
nand NAND2_6274(II34092,WX10993,II34090);
nand NAND2_6275(II34089,II34091,II34092);
nand NAND2_6276(II34097,WX11057,II34089);
nand NAND2_6277(II34098,WX11057,II34097);
nand NAND2_6278(II34099,II34089,II34097);
nand NAND2_6279(II34088,II34098,II34099);
nand NAND2_6280(II34105,WX11121,WX11185);
nand NAND2_6281(II34106,WX11121,II34105);
nand NAND2_6282(II34107,WX11185,II34105);
nand NAND2_6283(II34104,II34106,II34107);
nand NAND2_6284(II34112,II34088,II34104);
nand NAND2_6285(II34113,II34088,II34112);
nand NAND2_6286(II34114,II34104,II34112);
nand NAND2_6287(WX11246,II34113,II34114);
nand NAND2_6288(II34121,WX11345,WX10995);
nand NAND2_6289(II34122,WX11345,II34121);
nand NAND2_6290(II34123,WX10995,II34121);
nand NAND2_6291(II34120,II34122,II34123);
nand NAND2_6292(II34128,WX11059,II34120);
nand NAND2_6293(II34129,WX11059,II34128);
nand NAND2_6294(II34130,II34120,II34128);
nand NAND2_6295(II34119,II34129,II34130);
nand NAND2_6296(II34136,WX11123,WX11187);
nand NAND2_6297(II34137,WX11123,II34136);
nand NAND2_6298(II34138,WX11187,II34136);
nand NAND2_6299(II34135,II34137,II34138);
nand NAND2_6300(II34143,II34119,II34135);
nand NAND2_6301(II34144,II34119,II34143);
nand NAND2_6302(II34145,II34135,II34143);
nand NAND2_6303(WX11247,II34144,II34145);
nand NAND2_6304(II34152,WX11345,WX10997);
nand NAND2_6305(II34153,WX11345,II34152);
nand NAND2_6306(II34154,WX10997,II34152);
nand NAND2_6307(II34151,II34153,II34154);
nand NAND2_6308(II34159,WX11061,II34151);
nand NAND2_6309(II34160,WX11061,II34159);
nand NAND2_6310(II34161,II34151,II34159);
nand NAND2_6311(II34150,II34160,II34161);
nand NAND2_6312(II34167,WX11125,WX11189);
nand NAND2_6313(II34168,WX11125,II34167);
nand NAND2_6314(II34169,WX11189,II34167);
nand NAND2_6315(II34166,II34168,II34169);
nand NAND2_6316(II34174,II34150,II34166);
nand NAND2_6317(II34175,II34150,II34174);
nand NAND2_6318(II34176,II34166,II34174);
nand NAND2_6319(WX11248,II34175,II34176);
nand NAND2_6320(II34183,WX11345,WX10999);
nand NAND2_6321(II34184,WX11345,II34183);
nand NAND2_6322(II34185,WX10999,II34183);
nand NAND2_6323(II34182,II34184,II34185);
nand NAND2_6324(II34190,WX11063,II34182);
nand NAND2_6325(II34191,WX11063,II34190);
nand NAND2_6326(II34192,II34182,II34190);
nand NAND2_6327(II34181,II34191,II34192);
nand NAND2_6328(II34198,WX11127,WX11191);
nand NAND2_6329(II34199,WX11127,II34198);
nand NAND2_6330(II34200,WX11191,II34198);
nand NAND2_6331(II34197,II34199,II34200);
nand NAND2_6332(II34205,II34181,II34197);
nand NAND2_6333(II34206,II34181,II34205);
nand NAND2_6334(II34207,II34197,II34205);
nand NAND2_6335(WX11249,II34206,II34207);
nand NAND2_6336(II34214,WX11345,WX11001);
nand NAND2_6337(II34215,WX11345,II34214);
nand NAND2_6338(II34216,WX11001,II34214);
nand NAND2_6339(II34213,II34215,II34216);
nand NAND2_6340(II34221,WX11065,II34213);
nand NAND2_6341(II34222,WX11065,II34221);
nand NAND2_6342(II34223,II34213,II34221);
nand NAND2_6343(II34212,II34222,II34223);
nand NAND2_6344(II34229,WX11129,WX11193);
nand NAND2_6345(II34230,WX11129,II34229);
nand NAND2_6346(II34231,WX11193,II34229);
nand NAND2_6347(II34228,II34230,II34231);
nand NAND2_6348(II34236,II34212,II34228);
nand NAND2_6349(II34237,II34212,II34236);
nand NAND2_6350(II34238,II34228,II34236);
nand NAND2_6351(WX11250,II34237,II34238);
nand NAND2_6352(II34245,WX11345,WX11003);
nand NAND2_6353(II34246,WX11345,II34245);
nand NAND2_6354(II34247,WX11003,II34245);
nand NAND2_6355(II34244,II34246,II34247);
nand NAND2_6356(II34252,WX11067,II34244);
nand NAND2_6357(II34253,WX11067,II34252);
nand NAND2_6358(II34254,II34244,II34252);
nand NAND2_6359(II34243,II34253,II34254);
nand NAND2_6360(II34260,WX11131,WX11195);
nand NAND2_6361(II34261,WX11131,II34260);
nand NAND2_6362(II34262,WX11195,II34260);
nand NAND2_6363(II34259,II34261,II34262);
nand NAND2_6364(II34267,II34243,II34259);
nand NAND2_6365(II34268,II34243,II34267);
nand NAND2_6366(II34269,II34259,II34267);
nand NAND2_6367(WX11251,II34268,II34269);
nand NAND2_6368(II34276,WX11345,WX11005);
nand NAND2_6369(II34277,WX11345,II34276);
nand NAND2_6370(II34278,WX11005,II34276);
nand NAND2_6371(II34275,II34277,II34278);
nand NAND2_6372(II34283,WX11069,II34275);
nand NAND2_6373(II34284,WX11069,II34283);
nand NAND2_6374(II34285,II34275,II34283);
nand NAND2_6375(II34274,II34284,II34285);
nand NAND2_6376(II34291,WX11133,WX11197);
nand NAND2_6377(II34292,WX11133,II34291);
nand NAND2_6378(II34293,WX11197,II34291);
nand NAND2_6379(II34290,II34292,II34293);
nand NAND2_6380(II34298,II34274,II34290);
nand NAND2_6381(II34299,II34274,II34298);
nand NAND2_6382(II34300,II34290,II34298);
nand NAND2_6383(WX11252,II34299,II34300);
nand NAND2_6384(II34307,WX11345,WX11007);
nand NAND2_6385(II34308,WX11345,II34307);
nand NAND2_6386(II34309,WX11007,II34307);
nand NAND2_6387(II34306,II34308,II34309);
nand NAND2_6388(II34314,WX11071,II34306);
nand NAND2_6389(II34315,WX11071,II34314);
nand NAND2_6390(II34316,II34306,II34314);
nand NAND2_6391(II34305,II34315,II34316);
nand NAND2_6392(II34322,WX11135,WX11199);
nand NAND2_6393(II34323,WX11135,II34322);
nand NAND2_6394(II34324,WX11199,II34322);
nand NAND2_6395(II34321,II34323,II34324);
nand NAND2_6396(II34329,II34305,II34321);
nand NAND2_6397(II34330,II34305,II34329);
nand NAND2_6398(II34331,II34321,II34329);
nand NAND2_6399(WX11253,II34330,II34331);
nand NAND2_6400(II34338,WX11345,WX11009);
nand NAND2_6401(II34339,WX11345,II34338);
nand NAND2_6402(II34340,WX11009,II34338);
nand NAND2_6403(II34337,II34339,II34340);
nand NAND2_6404(II34345,WX11073,II34337);
nand NAND2_6405(II34346,WX11073,II34345);
nand NAND2_6406(II34347,II34337,II34345);
nand NAND2_6407(II34336,II34346,II34347);
nand NAND2_6408(II34353,WX11137,WX11201);
nand NAND2_6409(II34354,WX11137,II34353);
nand NAND2_6410(II34355,WX11201,II34353);
nand NAND2_6411(II34352,II34354,II34355);
nand NAND2_6412(II34360,II34336,II34352);
nand NAND2_6413(II34361,II34336,II34360);
nand NAND2_6414(II34362,II34352,II34360);
nand NAND2_6415(WX11254,II34361,II34362);
nand NAND2_6416(II34369,WX11345,WX11011);
nand NAND2_6417(II34370,WX11345,II34369);
nand NAND2_6418(II34371,WX11011,II34369);
nand NAND2_6419(II34368,II34370,II34371);
nand NAND2_6420(II34376,WX11075,II34368);
nand NAND2_6421(II34377,WX11075,II34376);
nand NAND2_6422(II34378,II34368,II34376);
nand NAND2_6423(II34367,II34377,II34378);
nand NAND2_6424(II34384,WX11139,WX11203);
nand NAND2_6425(II34385,WX11139,II34384);
nand NAND2_6426(II34386,WX11203,II34384);
nand NAND2_6427(II34383,II34385,II34386);
nand NAND2_6428(II34391,II34367,II34383);
nand NAND2_6429(II34392,II34367,II34391);
nand NAND2_6430(II34393,II34383,II34391);
nand NAND2_6431(WX11255,II34392,II34393);
nand NAND2_6432(II34400,WX11345,WX11013);
nand NAND2_6433(II34401,WX11345,II34400);
nand NAND2_6434(II34402,WX11013,II34400);
nand NAND2_6435(II34399,II34401,II34402);
nand NAND2_6436(II34407,WX11077,II34399);
nand NAND2_6437(II34408,WX11077,II34407);
nand NAND2_6438(II34409,II34399,II34407);
nand NAND2_6439(II34398,II34408,II34409);
nand NAND2_6440(II34415,WX11141,WX11205);
nand NAND2_6441(II34416,WX11141,II34415);
nand NAND2_6442(II34417,WX11205,II34415);
nand NAND2_6443(II34414,II34416,II34417);
nand NAND2_6444(II34422,II34398,II34414);
nand NAND2_6445(II34423,II34398,II34422);
nand NAND2_6446(II34424,II34414,II34422);
nand NAND2_6447(WX11256,II34423,II34424);
nand NAND2_6448(II34431,WX11345,WX11015);
nand NAND2_6449(II34432,WX11345,II34431);
nand NAND2_6450(II34433,WX11015,II34431);
nand NAND2_6451(II34430,II34432,II34433);
nand NAND2_6452(II34438,WX11079,II34430);
nand NAND2_6453(II34439,WX11079,II34438);
nand NAND2_6454(II34440,II34430,II34438);
nand NAND2_6455(II34429,II34439,II34440);
nand NAND2_6456(II34446,WX11143,WX11207);
nand NAND2_6457(II34447,WX11143,II34446);
nand NAND2_6458(II34448,WX11207,II34446);
nand NAND2_6459(II34445,II34447,II34448);
nand NAND2_6460(II34453,II34429,II34445);
nand NAND2_6461(II34454,II34429,II34453);
nand NAND2_6462(II34455,II34445,II34453);
nand NAND2_6463(WX11257,II34454,II34455);
nand NAND2_6464(II34462,WX11345,WX11017);
nand NAND2_6465(II34463,WX11345,II34462);
nand NAND2_6466(II34464,WX11017,II34462);
nand NAND2_6467(II34461,II34463,II34464);
nand NAND2_6468(II34469,WX11081,II34461);
nand NAND2_6469(II34470,WX11081,II34469);
nand NAND2_6470(II34471,II34461,II34469);
nand NAND2_6471(II34460,II34470,II34471);
nand NAND2_6472(II34477,WX11145,WX11209);
nand NAND2_6473(II34478,WX11145,II34477);
nand NAND2_6474(II34479,WX11209,II34477);
nand NAND2_6475(II34476,II34478,II34479);
nand NAND2_6476(II34484,II34460,II34476);
nand NAND2_6477(II34485,II34460,II34484);
nand NAND2_6478(II34486,II34476,II34484);
nand NAND2_6479(WX11258,II34485,II34486);
nand NAND2_6480(II34493,WX11345,WX11019);
nand NAND2_6481(II34494,WX11345,II34493);
nand NAND2_6482(II34495,WX11019,II34493);
nand NAND2_6483(II34492,II34494,II34495);
nand NAND2_6484(II34500,WX11083,II34492);
nand NAND2_6485(II34501,WX11083,II34500);
nand NAND2_6486(II34502,II34492,II34500);
nand NAND2_6487(II34491,II34501,II34502);
nand NAND2_6488(II34508,WX11147,WX11211);
nand NAND2_6489(II34509,WX11147,II34508);
nand NAND2_6490(II34510,WX11211,II34508);
nand NAND2_6491(II34507,II34509,II34510);
nand NAND2_6492(II34515,II34491,II34507);
nand NAND2_6493(II34516,II34491,II34515);
nand NAND2_6494(II34517,II34507,II34515);
nand NAND2_6495(WX11259,II34516,II34517);
nand NAND2_6496(II34524,WX11346,WX11021);
nand NAND2_6497(II34525,WX11346,II34524);
nand NAND2_6498(II34526,WX11021,II34524);
nand NAND2_6499(II34523,II34525,II34526);
nand NAND2_6500(II34531,WX11085,II34523);
nand NAND2_6501(II34532,WX11085,II34531);
nand NAND2_6502(II34533,II34523,II34531);
nand NAND2_6503(II34522,II34532,II34533);
nand NAND2_6504(II34539,WX11149,WX11213);
nand NAND2_6505(II34540,WX11149,II34539);
nand NAND2_6506(II34541,WX11213,II34539);
nand NAND2_6507(II34538,II34540,II34541);
nand NAND2_6508(II34546,II34522,II34538);
nand NAND2_6509(II34547,II34522,II34546);
nand NAND2_6510(II34548,II34538,II34546);
nand NAND2_6511(WX11260,II34547,II34548);
nand NAND2_6512(II34555,WX11346,WX11023);
nand NAND2_6513(II34556,WX11346,II34555);
nand NAND2_6514(II34557,WX11023,II34555);
nand NAND2_6515(II34554,II34556,II34557);
nand NAND2_6516(II34562,WX11087,II34554);
nand NAND2_6517(II34563,WX11087,II34562);
nand NAND2_6518(II34564,II34554,II34562);
nand NAND2_6519(II34553,II34563,II34564);
nand NAND2_6520(II34570,WX11151,WX11215);
nand NAND2_6521(II34571,WX11151,II34570);
nand NAND2_6522(II34572,WX11215,II34570);
nand NAND2_6523(II34569,II34571,II34572);
nand NAND2_6524(II34577,II34553,II34569);
nand NAND2_6525(II34578,II34553,II34577);
nand NAND2_6526(II34579,II34569,II34577);
nand NAND2_6527(WX11261,II34578,II34579);
nand NAND2_6528(II34586,WX11346,WX11025);
nand NAND2_6529(II34587,WX11346,II34586);
nand NAND2_6530(II34588,WX11025,II34586);
nand NAND2_6531(II34585,II34587,II34588);
nand NAND2_6532(II34593,WX11089,II34585);
nand NAND2_6533(II34594,WX11089,II34593);
nand NAND2_6534(II34595,II34585,II34593);
nand NAND2_6535(II34584,II34594,II34595);
nand NAND2_6536(II34601,WX11153,WX11217);
nand NAND2_6537(II34602,WX11153,II34601);
nand NAND2_6538(II34603,WX11217,II34601);
nand NAND2_6539(II34600,II34602,II34603);
nand NAND2_6540(II34608,II34584,II34600);
nand NAND2_6541(II34609,II34584,II34608);
nand NAND2_6542(II34610,II34600,II34608);
nand NAND2_6543(WX11262,II34609,II34610);
nand NAND2_6544(II34617,WX11346,WX11027);
nand NAND2_6545(II34618,WX11346,II34617);
nand NAND2_6546(II34619,WX11027,II34617);
nand NAND2_6547(II34616,II34618,II34619);
nand NAND2_6548(II34624,WX11091,II34616);
nand NAND2_6549(II34625,WX11091,II34624);
nand NAND2_6550(II34626,II34616,II34624);
nand NAND2_6551(II34615,II34625,II34626);
nand NAND2_6552(II34632,WX11155,WX11219);
nand NAND2_6553(II34633,WX11155,II34632);
nand NAND2_6554(II34634,WX11219,II34632);
nand NAND2_6555(II34631,II34633,II34634);
nand NAND2_6556(II34639,II34615,II34631);
nand NAND2_6557(II34640,II34615,II34639);
nand NAND2_6558(II34641,II34631,II34639);
nand NAND2_6559(WX11263,II34640,II34641);
nand NAND2_6560(II34648,WX11346,WX11029);
nand NAND2_6561(II34649,WX11346,II34648);
nand NAND2_6562(II34650,WX11029,II34648);
nand NAND2_6563(II34647,II34649,II34650);
nand NAND2_6564(II34655,WX11093,II34647);
nand NAND2_6565(II34656,WX11093,II34655);
nand NAND2_6566(II34657,II34647,II34655);
nand NAND2_6567(II34646,II34656,II34657);
nand NAND2_6568(II34663,WX11157,WX11221);
nand NAND2_6569(II34664,WX11157,II34663);
nand NAND2_6570(II34665,WX11221,II34663);
nand NAND2_6571(II34662,II34664,II34665);
nand NAND2_6572(II34670,II34646,II34662);
nand NAND2_6573(II34671,II34646,II34670);
nand NAND2_6574(II34672,II34662,II34670);
nand NAND2_6575(WX11264,II34671,II34672);
nand NAND2_6576(II34679,WX11346,WX11031);
nand NAND2_6577(II34680,WX11346,II34679);
nand NAND2_6578(II34681,WX11031,II34679);
nand NAND2_6579(II34678,II34680,II34681);
nand NAND2_6580(II34686,WX11095,II34678);
nand NAND2_6581(II34687,WX11095,II34686);
nand NAND2_6582(II34688,II34678,II34686);
nand NAND2_6583(II34677,II34687,II34688);
nand NAND2_6584(II34694,WX11159,WX11223);
nand NAND2_6585(II34695,WX11159,II34694);
nand NAND2_6586(II34696,WX11223,II34694);
nand NAND2_6587(II34693,II34695,II34696);
nand NAND2_6588(II34701,II34677,II34693);
nand NAND2_6589(II34702,II34677,II34701);
nand NAND2_6590(II34703,II34693,II34701);
nand NAND2_6591(WX11265,II34702,II34703);
nand NAND2_6592(II34710,WX11346,WX11033);
nand NAND2_6593(II34711,WX11346,II34710);
nand NAND2_6594(II34712,WX11033,II34710);
nand NAND2_6595(II34709,II34711,II34712);
nand NAND2_6596(II34717,WX11097,II34709);
nand NAND2_6597(II34718,WX11097,II34717);
nand NAND2_6598(II34719,II34709,II34717);
nand NAND2_6599(II34708,II34718,II34719);
nand NAND2_6600(II34725,WX11161,WX11225);
nand NAND2_6601(II34726,WX11161,II34725);
nand NAND2_6602(II34727,WX11225,II34725);
nand NAND2_6603(II34724,II34726,II34727);
nand NAND2_6604(II34732,II34708,II34724);
nand NAND2_6605(II34733,II34708,II34732);
nand NAND2_6606(II34734,II34724,II34732);
nand NAND2_6607(WX11266,II34733,II34734);
nand NAND2_6608(II34741,WX11346,WX11035);
nand NAND2_6609(II34742,WX11346,II34741);
nand NAND2_6610(II34743,WX11035,II34741);
nand NAND2_6611(II34740,II34742,II34743);
nand NAND2_6612(II34748,WX11099,II34740);
nand NAND2_6613(II34749,WX11099,II34748);
nand NAND2_6614(II34750,II34740,II34748);
nand NAND2_6615(II34739,II34749,II34750);
nand NAND2_6616(II34756,WX11163,WX11227);
nand NAND2_6617(II34757,WX11163,II34756);
nand NAND2_6618(II34758,WX11227,II34756);
nand NAND2_6619(II34755,II34757,II34758);
nand NAND2_6620(II34763,II34739,II34755);
nand NAND2_6621(II34764,II34739,II34763);
nand NAND2_6622(II34765,II34755,II34763);
nand NAND2_6623(WX11267,II34764,II34765);
nand NAND2_6624(II34772,WX11346,WX11037);
nand NAND2_6625(II34773,WX11346,II34772);
nand NAND2_6626(II34774,WX11037,II34772);
nand NAND2_6627(II34771,II34773,II34774);
nand NAND2_6628(II34779,WX11101,II34771);
nand NAND2_6629(II34780,WX11101,II34779);
nand NAND2_6630(II34781,II34771,II34779);
nand NAND2_6631(II34770,II34780,II34781);
nand NAND2_6632(II34787,WX11165,WX11229);
nand NAND2_6633(II34788,WX11165,II34787);
nand NAND2_6634(II34789,WX11229,II34787);
nand NAND2_6635(II34786,II34788,II34789);
nand NAND2_6636(II34794,II34770,II34786);
nand NAND2_6637(II34795,II34770,II34794);
nand NAND2_6638(II34796,II34786,II34794);
nand NAND2_6639(WX11268,II34795,II34796);
nand NAND2_6640(II34803,WX11346,WX11039);
nand NAND2_6641(II34804,WX11346,II34803);
nand NAND2_6642(II34805,WX11039,II34803);
nand NAND2_6643(II34802,II34804,II34805);
nand NAND2_6644(II34810,WX11103,II34802);
nand NAND2_6645(II34811,WX11103,II34810);
nand NAND2_6646(II34812,II34802,II34810);
nand NAND2_6647(II34801,II34811,II34812);
nand NAND2_6648(II34818,WX11167,WX11231);
nand NAND2_6649(II34819,WX11167,II34818);
nand NAND2_6650(II34820,WX11231,II34818);
nand NAND2_6651(II34817,II34819,II34820);
nand NAND2_6652(II34825,II34801,II34817);
nand NAND2_6653(II34826,II34801,II34825);
nand NAND2_6654(II34827,II34817,II34825);
nand NAND2_6655(WX11269,II34826,II34827);
nand NAND2_6656(II34834,WX11346,WX11041);
nand NAND2_6657(II34835,WX11346,II34834);
nand NAND2_6658(II34836,WX11041,II34834);
nand NAND2_6659(II34833,II34835,II34836);
nand NAND2_6660(II34841,WX11105,II34833);
nand NAND2_6661(II34842,WX11105,II34841);
nand NAND2_6662(II34843,II34833,II34841);
nand NAND2_6663(II34832,II34842,II34843);
nand NAND2_6664(II34849,WX11169,WX11233);
nand NAND2_6665(II34850,WX11169,II34849);
nand NAND2_6666(II34851,WX11233,II34849);
nand NAND2_6667(II34848,II34850,II34851);
nand NAND2_6668(II34856,II34832,II34848);
nand NAND2_6669(II34857,II34832,II34856);
nand NAND2_6670(II34858,II34848,II34856);
nand NAND2_6671(WX11270,II34857,II34858);
nand NAND2_6672(II34865,WX11346,WX11043);
nand NAND2_6673(II34866,WX11346,II34865);
nand NAND2_6674(II34867,WX11043,II34865);
nand NAND2_6675(II34864,II34866,II34867);
nand NAND2_6676(II34872,WX11107,II34864);
nand NAND2_6677(II34873,WX11107,II34872);
nand NAND2_6678(II34874,II34864,II34872);
nand NAND2_6679(II34863,II34873,II34874);
nand NAND2_6680(II34880,WX11171,WX11235);
nand NAND2_6681(II34881,WX11171,II34880);
nand NAND2_6682(II34882,WX11235,II34880);
nand NAND2_6683(II34879,II34881,II34882);
nand NAND2_6684(II34887,II34863,II34879);
nand NAND2_6685(II34888,II34863,II34887);
nand NAND2_6686(II34889,II34879,II34887);
nand NAND2_6687(WX11271,II34888,II34889);
nand NAND2_6688(II34896,WX11346,WX11045);
nand NAND2_6689(II34897,WX11346,II34896);
nand NAND2_6690(II34898,WX11045,II34896);
nand NAND2_6691(II34895,II34897,II34898);
nand NAND2_6692(II34903,WX11109,II34895);
nand NAND2_6693(II34904,WX11109,II34903);
nand NAND2_6694(II34905,II34895,II34903);
nand NAND2_6695(II34894,II34904,II34905);
nand NAND2_6696(II34911,WX11173,WX11237);
nand NAND2_6697(II34912,WX11173,II34911);
nand NAND2_6698(II34913,WX11237,II34911);
nand NAND2_6699(II34910,II34912,II34913);
nand NAND2_6700(II34918,II34894,II34910);
nand NAND2_6701(II34919,II34894,II34918);
nand NAND2_6702(II34920,II34910,II34918);
nand NAND2_6703(WX11272,II34919,II34920);
nand NAND2_6704(II34927,WX11346,WX11047);
nand NAND2_6705(II34928,WX11346,II34927);
nand NAND2_6706(II34929,WX11047,II34927);
nand NAND2_6707(II34926,II34928,II34929);
nand NAND2_6708(II34934,WX11111,II34926);
nand NAND2_6709(II34935,WX11111,II34934);
nand NAND2_6710(II34936,II34926,II34934);
nand NAND2_6711(II34925,II34935,II34936);
nand NAND2_6712(II34942,WX11175,WX11239);
nand NAND2_6713(II34943,WX11175,II34942);
nand NAND2_6714(II34944,WX11239,II34942);
nand NAND2_6715(II34941,II34943,II34944);
nand NAND2_6716(II34949,II34925,II34941);
nand NAND2_6717(II34950,II34925,II34949);
nand NAND2_6718(II34951,II34941,II34949);
nand NAND2_6719(WX11273,II34950,II34951);
nand NAND2_6720(II34958,WX11346,WX11049);
nand NAND2_6721(II34959,WX11346,II34958);
nand NAND2_6722(II34960,WX11049,II34958);
nand NAND2_6723(II34957,II34959,II34960);
nand NAND2_6724(II34965,WX11113,II34957);
nand NAND2_6725(II34966,WX11113,II34965);
nand NAND2_6726(II34967,II34957,II34965);
nand NAND2_6727(II34956,II34966,II34967);
nand NAND2_6728(II34973,WX11177,WX11241);
nand NAND2_6729(II34974,WX11177,II34973);
nand NAND2_6730(II34975,WX11241,II34973);
nand NAND2_6731(II34972,II34974,II34975);
nand NAND2_6732(II34980,II34956,II34972);
nand NAND2_6733(II34981,II34956,II34980);
nand NAND2_6734(II34982,II34972,II34980);
nand NAND2_6735(WX11274,II34981,II34982);
nand NAND2_6736(II34989,WX11346,WX11051);
nand NAND2_6737(II34990,WX11346,II34989);
nand NAND2_6738(II34991,WX11051,II34989);
nand NAND2_6739(II34988,II34990,II34991);
nand NAND2_6740(II34996,WX11115,II34988);
nand NAND2_6741(II34997,WX11115,II34996);
nand NAND2_6742(II34998,II34988,II34996);
nand NAND2_6743(II34987,II34997,II34998);
nand NAND2_6744(II35004,WX11179,WX11243);
nand NAND2_6745(II35005,WX11179,II35004);
nand NAND2_6746(II35006,WX11243,II35004);
nand NAND2_6747(II35003,II35005,II35006);
nand NAND2_6748(II35011,II34987,II35003);
nand NAND2_6749(II35012,II34987,II35011);
nand NAND2_6750(II35013,II35003,II35011);
nand NAND2_6751(WX11275,II35012,II35013);
nand NAND2_6752(II35092,WX10924,WX10829);
nand NAND2_6753(II35093,WX10924,II35092);
nand NAND2_6754(II35094,WX10829,II35092);
nand NAND2_6755(WX11350,II35093,II35094);
nand NAND2_6756(II35105,WX10925,WX10831);
nand NAND2_6757(II35106,WX10925,II35105);
nand NAND2_6758(II35107,WX10831,II35105);
nand NAND2_6759(WX11357,II35106,II35107);
nand NAND2_6760(II35118,WX10926,WX10833);
nand NAND2_6761(II35119,WX10926,II35118);
nand NAND2_6762(II35120,WX10833,II35118);
nand NAND2_6763(WX11364,II35119,II35120);
nand NAND2_6764(II35131,WX10927,WX10835);
nand NAND2_6765(II35132,WX10927,II35131);
nand NAND2_6766(II35133,WX10835,II35131);
nand NAND2_6767(WX11371,II35132,II35133);
nand NAND2_6768(II35144,WX10928,WX10837);
nand NAND2_6769(II35145,WX10928,II35144);
nand NAND2_6770(II35146,WX10837,II35144);
nand NAND2_6771(WX11378,II35145,II35146);
nand NAND2_6772(II35157,WX10929,WX10839);
nand NAND2_6773(II35158,WX10929,II35157);
nand NAND2_6774(II35159,WX10839,II35157);
nand NAND2_6775(WX11385,II35158,II35159);
nand NAND2_6776(II35170,WX10930,WX10841);
nand NAND2_6777(II35171,WX10930,II35170);
nand NAND2_6778(II35172,WX10841,II35170);
nand NAND2_6779(WX11392,II35171,II35172);
nand NAND2_6780(II35183,WX10931,WX10843);
nand NAND2_6781(II35184,WX10931,II35183);
nand NAND2_6782(II35185,WX10843,II35183);
nand NAND2_6783(WX11399,II35184,II35185);
nand NAND2_6784(II35196,WX10932,WX10845);
nand NAND2_6785(II35197,WX10932,II35196);
nand NAND2_6786(II35198,WX10845,II35196);
nand NAND2_6787(WX11406,II35197,II35198);
nand NAND2_6788(II35209,WX10933,WX10847);
nand NAND2_6789(II35210,WX10933,II35209);
nand NAND2_6790(II35211,WX10847,II35209);
nand NAND2_6791(WX11413,II35210,II35211);
nand NAND2_6792(II35222,WX10934,WX10849);
nand NAND2_6793(II35223,WX10934,II35222);
nand NAND2_6794(II35224,WX10849,II35222);
nand NAND2_6795(WX11420,II35223,II35224);
nand NAND2_6796(II35235,WX10935,WX10851);
nand NAND2_6797(II35236,WX10935,II35235);
nand NAND2_6798(II35237,WX10851,II35235);
nand NAND2_6799(WX11427,II35236,II35237);
nand NAND2_6800(II35248,WX10936,WX10853);
nand NAND2_6801(II35249,WX10936,II35248);
nand NAND2_6802(II35250,WX10853,II35248);
nand NAND2_6803(WX11434,II35249,II35250);
nand NAND2_6804(II35261,WX10937,WX10855);
nand NAND2_6805(II35262,WX10937,II35261);
nand NAND2_6806(II35263,WX10855,II35261);
nand NAND2_6807(WX11441,II35262,II35263);
nand NAND2_6808(II35274,WX10938,WX10857);
nand NAND2_6809(II35275,WX10938,II35274);
nand NAND2_6810(II35276,WX10857,II35274);
nand NAND2_6811(WX11448,II35275,II35276);
nand NAND2_6812(II35287,WX10939,WX10859);
nand NAND2_6813(II35288,WX10939,II35287);
nand NAND2_6814(II35289,WX10859,II35287);
nand NAND2_6815(WX11455,II35288,II35289);
nand NAND2_6816(II35300,WX10940,WX10861);
nand NAND2_6817(II35301,WX10940,II35300);
nand NAND2_6818(II35302,WX10861,II35300);
nand NAND2_6819(WX11462,II35301,II35302);
nand NAND2_6820(II35313,WX10941,WX10863);
nand NAND2_6821(II35314,WX10941,II35313);
nand NAND2_6822(II35315,WX10863,II35313);
nand NAND2_6823(WX11469,II35314,II35315);
nand NAND2_6824(II35326,WX10942,WX10865);
nand NAND2_6825(II35327,WX10942,II35326);
nand NAND2_6826(II35328,WX10865,II35326);
nand NAND2_6827(WX11476,II35327,II35328);
nand NAND2_6828(II35339,WX10943,WX10867);
nand NAND2_6829(II35340,WX10943,II35339);
nand NAND2_6830(II35341,WX10867,II35339);
nand NAND2_6831(WX11483,II35340,II35341);
nand NAND2_6832(II35352,WX10944,WX10869);
nand NAND2_6833(II35353,WX10944,II35352);
nand NAND2_6834(II35354,WX10869,II35352);
nand NAND2_6835(WX11490,II35353,II35354);
nand NAND2_6836(II35365,WX10945,WX10871);
nand NAND2_6837(II35366,WX10945,II35365);
nand NAND2_6838(II35367,WX10871,II35365);
nand NAND2_6839(WX11497,II35366,II35367);
nand NAND2_6840(II35378,WX10946,WX10873);
nand NAND2_6841(II35379,WX10946,II35378);
nand NAND2_6842(II35380,WX10873,II35378);
nand NAND2_6843(WX11504,II35379,II35380);
nand NAND2_6844(II35391,WX10947,WX10875);
nand NAND2_6845(II35392,WX10947,II35391);
nand NAND2_6846(II35393,WX10875,II35391);
nand NAND2_6847(WX11511,II35392,II35393);
nand NAND2_6848(II35404,WX10948,WX10877);
nand NAND2_6849(II35405,WX10948,II35404);
nand NAND2_6850(II35406,WX10877,II35404);
nand NAND2_6851(WX11518,II35405,II35406);
nand NAND2_6852(II35417,WX10949,WX10879);
nand NAND2_6853(II35418,WX10949,II35417);
nand NAND2_6854(II35419,WX10879,II35417);
nand NAND2_6855(WX11525,II35418,II35419);
nand NAND2_6856(II35430,WX10950,WX10881);
nand NAND2_6857(II35431,WX10950,II35430);
nand NAND2_6858(II35432,WX10881,II35430);
nand NAND2_6859(WX11532,II35431,II35432);
nand NAND2_6860(II35443,WX10951,WX10883);
nand NAND2_6861(II35444,WX10951,II35443);
nand NAND2_6862(II35445,WX10883,II35443);
nand NAND2_6863(WX11539,II35444,II35445);
nand NAND2_6864(II35456,WX10952,WX10885);
nand NAND2_6865(II35457,WX10952,II35456);
nand NAND2_6866(II35458,WX10885,II35456);
nand NAND2_6867(WX11546,II35457,II35458);
nand NAND2_6868(II35469,WX10953,WX10887);
nand NAND2_6869(II35470,WX10953,II35469);
nand NAND2_6870(II35471,WX10887,II35469);
nand NAND2_6871(WX11553,II35470,II35471);
nand NAND2_6872(II35482,WX10954,WX10889);
nand NAND2_6873(II35483,WX10954,II35482);
nand NAND2_6874(II35484,WX10889,II35482);
nand NAND2_6875(WX11560,II35483,II35484);
nand NAND2_6876(II35495,WX10955,WX10891);
nand NAND2_6877(II35496,WX10955,II35495);
nand NAND2_6878(II35497,WX10891,II35495);
nand NAND2_6879(WX11567,II35496,II35497);
nand NAND2_6880(II35510,WX10971,CRC_OUT_1_31);
nand NAND2_6881(II35511,WX10971,II35510);
nand NAND2_6882(II35512,CRC_OUT_1_31,II35510);
nand NAND2_6883(II35509,II35511,II35512);
nand NAND2_6884(II35517,CRC_OUT_1_15,II35509);
nand NAND2_6885(II35518,CRC_OUT_1_15,II35517);
nand NAND2_6886(II35519,II35509,II35517);
nand NAND2_6887(WX11575,II35518,II35519);
nand NAND2_6888(II35525,WX10976,CRC_OUT_1_31);
nand NAND2_6889(II35526,WX10976,II35525);
nand NAND2_6890(II35527,CRC_OUT_1_31,II35525);
nand NAND2_6891(II35524,II35526,II35527);
nand NAND2_6892(II35532,CRC_OUT_1_10,II35524);
nand NAND2_6893(II35533,CRC_OUT_1_10,II35532);
nand NAND2_6894(II35534,II35524,II35532);
nand NAND2_6895(WX11576,II35533,II35534);
nand NAND2_6896(II35540,WX10983,CRC_OUT_1_31);
nand NAND2_6897(II35541,WX10983,II35540);
nand NAND2_6898(II35542,CRC_OUT_1_31,II35540);
nand NAND2_6899(II35539,II35541,II35542);
nand NAND2_6900(II35547,CRC_OUT_1_3,II35539);
nand NAND2_6901(II35548,CRC_OUT_1_3,II35547);
nand NAND2_6902(II35549,II35539,II35547);
nand NAND2_6903(WX11577,II35548,II35549);
nand NAND2_6904(II35554,WX10987,CRC_OUT_1_31);
nand NAND2_6905(II35555,WX10987,II35554);
nand NAND2_6906(II35556,CRC_OUT_1_31,II35554);
nand NAND2_6907(WX11578,II35555,II35556);
nand NAND2_6908(II35561,WX10956,CRC_OUT_1_30);
nand NAND2_6909(II35562,WX10956,II35561);
nand NAND2_6910(II35563,CRC_OUT_1_30,II35561);
nand NAND2_6911(WX11579,II35562,II35563);
nand NAND2_6912(II35568,WX10957,CRC_OUT_1_29);
nand NAND2_6913(II35569,WX10957,II35568);
nand NAND2_6914(II35570,CRC_OUT_1_29,II35568);
nand NAND2_6915(WX11580,II35569,II35570);
nand NAND2_6916(II35575,WX10958,CRC_OUT_1_28);
nand NAND2_6917(II35576,WX10958,II35575);
nand NAND2_6918(II35577,CRC_OUT_1_28,II35575);
nand NAND2_6919(WX11581,II35576,II35577);
nand NAND2_6920(II35582,WX10959,CRC_OUT_1_27);
nand NAND2_6921(II35583,WX10959,II35582);
nand NAND2_6922(II35584,CRC_OUT_1_27,II35582);
nand NAND2_6923(WX11582,II35583,II35584);
nand NAND2_6924(II35589,WX10960,CRC_OUT_1_26);
nand NAND2_6925(II35590,WX10960,II35589);
nand NAND2_6926(II35591,CRC_OUT_1_26,II35589);
nand NAND2_6927(WX11583,II35590,II35591);
nand NAND2_6928(II35596,WX10961,CRC_OUT_1_25);
nand NAND2_6929(II35597,WX10961,II35596);
nand NAND2_6930(II35598,CRC_OUT_1_25,II35596);
nand NAND2_6931(WX11584,II35597,II35598);
nand NAND2_6932(II35603,WX10962,CRC_OUT_1_24);
nand NAND2_6933(II35604,WX10962,II35603);
nand NAND2_6934(II35605,CRC_OUT_1_24,II35603);
nand NAND2_6935(WX11585,II35604,II35605);
nand NAND2_6936(II35610,WX10963,CRC_OUT_1_23);
nand NAND2_6937(II35611,WX10963,II35610);
nand NAND2_6938(II35612,CRC_OUT_1_23,II35610);
nand NAND2_6939(WX11586,II35611,II35612);
nand NAND2_6940(II35617,WX10964,CRC_OUT_1_22);
nand NAND2_6941(II35618,WX10964,II35617);
nand NAND2_6942(II35619,CRC_OUT_1_22,II35617);
nand NAND2_6943(WX11587,II35618,II35619);
nand NAND2_6944(II35624,WX10965,CRC_OUT_1_21);
nand NAND2_6945(II35625,WX10965,II35624);
nand NAND2_6946(II35626,CRC_OUT_1_21,II35624);
nand NAND2_6947(WX11588,II35625,II35626);
nand NAND2_6948(II35631,WX10966,CRC_OUT_1_20);
nand NAND2_6949(II35632,WX10966,II35631);
nand NAND2_6950(II35633,CRC_OUT_1_20,II35631);
nand NAND2_6951(WX11589,II35632,II35633);
nand NAND2_6952(II35638,WX10967,CRC_OUT_1_19);
nand NAND2_6953(II35639,WX10967,II35638);
nand NAND2_6954(II35640,CRC_OUT_1_19,II35638);
nand NAND2_6955(WX11590,II35639,II35640);
nand NAND2_6956(II35645,WX10968,CRC_OUT_1_18);
nand NAND2_6957(II35646,WX10968,II35645);
nand NAND2_6958(II35647,CRC_OUT_1_18,II35645);
nand NAND2_6959(WX11591,II35646,II35647);
nand NAND2_6960(II35652,WX10969,CRC_OUT_1_17);
nand NAND2_6961(II35653,WX10969,II35652);
nand NAND2_6962(II35654,CRC_OUT_1_17,II35652);
nand NAND2_6963(WX11592,II35653,II35654);
nand NAND2_6964(II35659,WX10970,CRC_OUT_1_16);
nand NAND2_6965(II35660,WX10970,II35659);
nand NAND2_6966(II35661,CRC_OUT_1_16,II35659);
nand NAND2_6967(WX11593,II35660,II35661);
nand NAND2_6968(II35666,WX10972,CRC_OUT_1_14);
nand NAND2_6969(II35667,WX10972,II35666);
nand NAND2_6970(II35668,CRC_OUT_1_14,II35666);
nand NAND2_6971(WX11594,II35667,II35668);
nand NAND2_6972(II35673,WX10973,CRC_OUT_1_13);
nand NAND2_6973(II35674,WX10973,II35673);
nand NAND2_6974(II35675,CRC_OUT_1_13,II35673);
nand NAND2_6975(WX11595,II35674,II35675);
nand NAND2_6976(II35680,WX10974,CRC_OUT_1_12);
nand NAND2_6977(II35681,WX10974,II35680);
nand NAND2_6978(II35682,CRC_OUT_1_12,II35680);
nand NAND2_6979(WX11596,II35681,II35682);
nand NAND2_6980(II35687,WX10975,CRC_OUT_1_11);
nand NAND2_6981(II35688,WX10975,II35687);
nand NAND2_6982(II35689,CRC_OUT_1_11,II35687);
nand NAND2_6983(WX11597,II35688,II35689);
nand NAND2_6984(II35694,WX10977,CRC_OUT_1_9);
nand NAND2_6985(II35695,WX10977,II35694);
nand NAND2_6986(II35696,CRC_OUT_1_9,II35694);
nand NAND2_6987(WX11598,II35695,II35696);
nand NAND2_6988(II35701,WX10978,CRC_OUT_1_8);
nand NAND2_6989(II35702,WX10978,II35701);
nand NAND2_6990(II35703,CRC_OUT_1_8,II35701);
nand NAND2_6991(WX11599,II35702,II35703);
nand NAND2_6992(II35708,WX10979,CRC_OUT_1_7);
nand NAND2_6993(II35709,WX10979,II35708);
nand NAND2_6994(II35710,CRC_OUT_1_7,II35708);
nand NAND2_6995(WX11600,II35709,II35710);
nand NAND2_6996(II35715,WX10980,CRC_OUT_1_6);
nand NAND2_6997(II35716,WX10980,II35715);
nand NAND2_6998(II35717,CRC_OUT_1_6,II35715);
nand NAND2_6999(WX11601,II35716,II35717);
nand NAND2_7000(II35722,WX10981,CRC_OUT_1_5);
nand NAND2_7001(II35723,WX10981,II35722);
nand NAND2_7002(II35724,CRC_OUT_1_5,II35722);
nand NAND2_7003(WX11602,II35723,II35724);
nand NAND2_7004(II35729,WX10982,CRC_OUT_1_4);
nand NAND2_7005(II35730,WX10982,II35729);
nand NAND2_7006(II35731,CRC_OUT_1_4,II35729);
nand NAND2_7007(WX11603,II35730,II35731);
nand NAND2_7008(II35736,WX10984,CRC_OUT_1_2);
nand NAND2_7009(II35737,WX10984,II35736);
nand NAND2_7010(II35738,CRC_OUT_1_2,II35736);
nand NAND2_7011(WX11604,II35737,II35738);
nand NAND2_7012(II35743,WX10985,CRC_OUT_1_1);
nand NAND2_7013(II35744,WX10985,II35743);
nand NAND2_7014(II35745,CRC_OUT_1_1,II35743);
nand NAND2_7015(WX11605,II35744,II35745);
nand NAND2_7016(II35750,WX10986,CRC_OUT_1_0);
nand NAND2_7017(II35751,WX10986,II35750);
nand NAND2_7018(II35752,CRC_OUT_1_0,II35750);
nand NAND2_7019(WX11606,II35751,II35752);
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2004 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
reg [63:0] rf;
reg [63:0] rf2;
reg [63:0] biu;
reg b;
always @* begin
rf[63:32] = biu[63:32] & {32{b}};
rf[31:0] = {32{b}};
rf2 = rf;
rf2[31:0] = ~{32{b}};
end
reg [31:0] src1, src0, sr, mask;
wire [31:0] dualasr
= ((| src1[31:4])
? {{16{src0[31]}}, {16{src0[15]}}}
: ( ( sr & {2{mask[31:16]}})
| ( {{16{src0[31]}}, {16{src0[15]}}}
& {2{~mask[31:16]}})));
wire [31:0] sl_mask
= (32'hffffffff << src1[4:0]);
wire [31:0] sr_mask
= {sl_mask[0], sl_mask[1],
sl_mask[2], sl_mask[3], sl_mask[4],
sl_mask[5], sl_mask[6], sl_mask[7],
sl_mask[8], sl_mask[9],
sl_mask[10], sl_mask[11],
sl_mask[12], sl_mask[13], sl_mask[14],
sl_mask[15], sl_mask[16],
sl_mask[17], sl_mask[18], sl_mask[19],
sl_mask[20], sl_mask[21],
sl_mask[22], sl_mask[23], sl_mask[24],
sl_mask[25], sl_mask[26],
sl_mask[27], sl_mask[28], sl_mask[29],
sl_mask[30], sl_mask[31]};
wire [95:0] widerep = {2{({2{({2{ {b,b}, {b,{2{b}}}, {{2{b}},b}, {2{({2{b}})}} }})}})}};
wire [1:0] w = {2{b}};
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
`ifdef TEST_VERBOSE
$write("cyc=%0d d=%x %x %x %x %x %x\n", cyc, b, rf, rf2, dualasr, sl_mask, sr_mask);
`endif
if (cyc==1) begin
biu <= 64'h12451282_abadee00;
b <= 1'b0;
src1 <= 32'h00000001;
src0 <= 32'h9a4f1235;
sr <= 32'h0f19f567;
mask <= 32'h7af07ab4;
end
if (cyc==2) begin
biu <= 64'h12453382_abad8801;
b <= 1'b1;
if (rf != 64'h0) $stop;
if (rf2 != 64'h00000000ffffffff) $stop;
src1 <= 32'h0010000f;
src0 <= 32'h028aa336;
sr <= 32'h42ad0377;
mask <= 32'h1ab3b906;
if (dualasr != 32'h8f1f7060) $stop;
if (sl_mask != 32'hfffffffe) $stop;
if (sr_mask != 32'h7fffffff) $stop;
if (widerep != '0) $stop;
end
if (cyc==3) begin
biu <= 64'h12422382_77ad8802;
b <= 1'b1;
if (rf != 64'h12453382ffffffff) $stop;
if (rf2 != 64'h1245338200000000) $stop;
src1 <= 32'h0000000f;
src0 <= 32'h5c158f71;
sr <= 32'h7076c40a;
mask <= 32'h33eb3d44;
if (dualasr != 32'h0000ffff) $stop;
if (sl_mask != 32'hffff8000) $stop;
if (sr_mask != 32'h0001ffff) $stop;
if (widerep != '1) $stop;
end
if (cyc==4) begin
if (rf != 64'h12422382ffffffff) $stop;
if (rf2 != 64'h1242238200000000) $stop;
if (dualasr != 32'h3062cc1e) $stop;
if (sl_mask != 32'hffff8000) $stop;
if (sr_mask != 32'h0001ffff) $stop;
$write("*-* All Finished *-*\n");
if (widerep != '1) $stop;
$finish;
end
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O21BA_2_V
`define SKY130_FD_SC_HD__O21BA_2_V
/**
* o21ba: 2-input OR into first input of 2-input AND,
* 2nd input inverted.
*
* X = ((A1 | A2) & !B1_N)
*
* Verilog wrapper for o21ba with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__o21ba.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o21ba_2 (
X ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__o21ba base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o21ba_2 (
X ,
A1 ,
A2 ,
B1_N
);
output X ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__o21ba base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__O21BA_2_V
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.2
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
(* CORE_GENERATION_INFO="matrix_mult,hls_ip_2017_2,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z020clg484-1,HLS_INPUT_CLOCK=5.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=5.415000,HLS_SYN_LAT=88,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=3,HLS_SYN_FF=1012,HLS_SYN_LUT=635}" *)
module matrix_mult (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_idle,
ap_ready,
a_address0,
a_ce0,
a_q0,
a_address1,
a_ce1,
a_q1,
b_address0,
b_ce0,
b_q0,
b_address1,
b_ce1,
b_q1,
prod_address0,
prod_ce0,
prod_we0,
prod_d0
);
parameter ap_ST_fsm_state1 = 5'd1;
parameter ap_ST_fsm_pp0_stage0 = 5'd2;
parameter ap_ST_fsm_pp0_stage1 = 5'd4;
parameter ap_ST_fsm_pp0_stage2 = 5'd8;
parameter ap_ST_fsm_state17 = 5'd16;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
output ap_idle;
output ap_ready;
output [4:0] a_address0;
output a_ce0;
input [7:0] a_q0;
output [4:0] a_address1;
output a_ce1;
input [7:0] a_q1;
output [4:0] b_address0;
output b_ce0;
input [7:0] b_q0;
output [4:0] b_address1;
output b_ce1;
input [7:0] b_q1;
output [4:0] prod_address0;
output prod_ce0;
output prod_we0;
output [15:0] prod_d0;
reg ap_done;
reg ap_idle;
reg ap_ready;
reg[4:0] a_address0;
reg a_ce0;
reg[4:0] a_address1;
reg a_ce1;
reg[4:0] b_address0;
reg b_ce0;
reg[4:0] b_address1;
reg b_ce1;
reg prod_ce0;
reg prod_we0;
(* fsm_encoding = "none" *) reg [4:0] ap_CS_fsm;
wire ap_CS_fsm_state1;
reg [4:0] indvar_flatten_reg_172;
reg [2:0] i_reg_183;
reg [2:0] j_reg_194;
reg signed [7:0] reg_205;
wire ap_CS_fsm_pp0_stage0;
reg ap_enable_reg_pp0_iter1;
wire ap_block_state2_pp0_stage0_iter0;
wire ap_block_state5_pp0_stage0_iter1;
wire ap_block_state8_pp0_stage0_iter2;
wire ap_block_state11_pp0_stage0_iter3;
wire ap_block_state14_pp0_stage0_iter4;
wire ap_block_pp0_stage0_flag00011001;
reg [0:0] exitcond_flatten_reg_453;
wire ap_CS_fsm_pp0_stage2;
reg ap_enable_reg_pp0_iter2;
wire ap_block_state4_pp0_stage2_iter0;
wire ap_block_state7_pp0_stage2_iter1;
wire ap_block_state10_pp0_stage2_iter2;
wire ap_block_state13_pp0_stage2_iter3;
wire ap_block_state16_pp0_stage2_iter4;
wire ap_block_pp0_stage2_flag00011001;
reg [0:0] ap_reg_pp0_iter2_exitcond_flatten_reg_453;
reg signed [7:0] reg_209;
wire ap_CS_fsm_pp0_stage1;
wire ap_block_state3_pp0_stage1_iter0;
wire ap_block_state6_pp0_stage1_iter1;
wire ap_block_state9_pp0_stage1_iter2;
wire ap_block_state12_pp0_stage1_iter3;
wire ap_block_state15_pp0_stage1_iter4;
wire ap_block_pp0_stage1_flag00011001;
reg [0:0] ap_reg_pp0_iter1_exitcond_flatten_reg_453;
wire [0:0] exitcond_flatten_fu_214_p2;
reg [0:0] ap_reg_pp0_iter3_exitcond_flatten_reg_453;
reg [0:0] ap_reg_pp0_iter4_exitcond_flatten_reg_453;
wire [4:0] indvar_flatten_next_fu_220_p2;
reg [4:0] indvar_flatten_next_reg_457;
reg ap_enable_reg_pp0_iter0;
wire [2:0] j_mid2_fu_238_p3;
reg [2:0] j_mid2_reg_462;
reg [2:0] ap_reg_pp0_iter1_j_mid2_reg_462;
reg [2:0] ap_reg_pp0_iter2_j_mid2_reg_462;
wire [2:0] i_cast6_mid2_v_fu_246_p3;
reg [2:0] i_cast6_mid2_v_reg_471;
wire [5:0] tmp_7_fu_268_p2;
reg [5:0] tmp_7_reg_478;
reg [5:0] ap_reg_pp0_iter1_tmp_7_reg_478;
reg [5:0] ap_reg_pp0_iter2_tmp_7_reg_478;
wire [4:0] j_cast5_cast3_fu_274_p1;
reg [4:0] j_cast5_cast3_reg_488;
reg [4:0] ap_reg_pp0_iter1_j_cast5_cast3_reg_488;
reg [4:0] ap_reg_pp0_iter2_j_cast5_cast3_reg_488;
wire [3:0] tmp_12_fu_280_p2;
reg [3:0] tmp_12_reg_494;
wire [4:0] tmp_15_fu_286_p2;
reg [4:0] tmp_15_reg_499;
wire [5:0] tmp_8_fu_292_p2;
reg [5:0] tmp_8_reg_504;
wire [5:0] tmp_11_fu_297_p2;
reg [5:0] tmp_11_reg_509;
wire [2:0] j_1_fu_310_p2;
reg [2:0] j_1_reg_524;
reg signed [7:0] b_load_1_reg_539;
reg signed [7:0] a_load_1_reg_544;
wire [4:0] tmp_14_fu_323_p2;
reg [4:0] tmp_14_reg_549;
wire [5:0] tmp_9_fu_342_p2;
reg [5:0] tmp_9_reg_564;
wire [5:0] tmp_10_fu_347_p2;
reg [5:0] tmp_10_reg_569;
reg signed [7:0] b_load_3_reg_604;
wire [4:0] tmp_13_fu_387_p2;
reg [4:0] tmp_13_reg_614;
wire [5:0] tmp_16_fu_392_p2;
reg [5:0] tmp_16_reg_619;
reg [5:0] ap_reg_pp0_iter3_tmp_16_reg_619;
wire [15:0] grp_fu_336_p2;
reg [15:0] tmp_2_4_reg_649;
wire [15:0] grp_fu_362_p2;
reg [15:0] tmp_2_1_reg_654;
wire signed [15:0] grp_fu_432_p3;
reg signed [15:0] tmp4_reg_669;
reg ap_enable_reg_pp0_iter3;
wire signed [15:0] grp_fu_439_p3;
reg signed [15:0] tmp1_reg_674;
wire signed [15:0] grp_fu_446_p3;
reg signed [15:0] tmp3_reg_679;
reg ap_enable_reg_pp0_iter4;
(* use_dsp48 = "no" *) wire [15:0] tmp_3_4_fu_424_p2;
reg [15:0] tmp_3_4_reg_684;
wire ap_block_pp0_stage0_flag00011011;
reg ap_condition_pp0_exit_iter0_state2;
wire ap_block_pp0_stage2_flag00011011;
reg [4:0] indvar_flatten_phi_fu_176_p4;
wire ap_block_pp0_stage0_flag00000000;
reg [2:0] i_phi_fu_187_p4;
reg [2:0] j_phi_fu_198_p4;
wire [31:0] tmp_12_cast_fu_302_p1;
wire ap_block_pp0_stage2_flag00000000;
wire [31:0] tmp_15_cast_fu_306_p1;
wire [31:0] tmp_8_cast_fu_315_p1;
wire signed [31:0] tmp_11_cast_fu_319_p1;
wire [31:0] tmp_14_cast_fu_352_p1;
wire signed [31:0] tmp_9_cast_fu_368_p1;
wire ap_block_pp0_stage1_flag00000000;
wire signed [31:0] tmp_10_cast_fu_372_p1;
wire [31:0] j_cast5_fu_376_p1;
wire [31:0] tmp_7_cast_fu_380_p1;
wire [31:0] tmp_13_cast_fu_404_p1;
wire [31:0] tmp_16_cast_fu_428_p1;
wire [0:0] exitcond_fu_232_p2;
wire [2:0] i_1_fu_226_p2;
wire [4:0] tmp_fu_257_p3;
wire [5:0] i_cast6_mid2_cast_fu_254_p1;
wire [5:0] p_shl_cast_fu_264_p1;
wire [3:0] j_cast5_cast_fu_277_p1;
wire [5:0] j_cast5_cast4_fu_384_p1;
wire ap_CS_fsm_state17;
reg [4:0] ap_NS_fsm;
wire ap_block_pp0_stage1_flag00011011;
reg ap_idle_pp0;
wire ap_enable_pp0;
// power-on initialization
initial begin
#0 ap_CS_fsm = 5'd1;
#0 ap_enable_reg_pp0_iter1 = 1'b0;
#0 ap_enable_reg_pp0_iter2 = 1'b0;
#0 ap_enable_reg_pp0_iter0 = 1'b0;
#0 ap_enable_reg_pp0_iter3 = 1'b0;
#0 ap_enable_reg_pp0_iter4 = 1'b0;
end
matrix_mult_mul_8bkb #(
.ID( 1 ),
.NUM_STAGE( 5 ),
.din0_WIDTH( 8 ),
.din1_WIDTH( 8 ),
.dout_WIDTH( 16 ))
matrix_mult_mul_8bkb_U0(
.clk(ap_clk),
.reset(ap_rst),
.din0(reg_209),
.din1(reg_205),
.ce(1'b1),
.dout(grp_fu_336_p2)
);
matrix_mult_mul_8bkb #(
.ID( 1 ),
.NUM_STAGE( 5 ),
.din0_WIDTH( 8 ),
.din1_WIDTH( 8 ),
.dout_WIDTH( 16 ))
matrix_mult_mul_8bkb_U1(
.clk(ap_clk),
.reset(ap_rst),
.din0(a_load_1_reg_544),
.din1(b_load_1_reg_539),
.ce(1'b1),
.dout(grp_fu_362_p2)
);
matrix_mult_mac_mcud #(
.ID( 1 ),
.NUM_STAGE( 3 ),
.din0_WIDTH( 8 ),
.din1_WIDTH( 8 ),
.din2_WIDTH( 16 ),
.dout_WIDTH( 16 ))
matrix_mult_mac_mcud_U2(
.clk(ap_clk),
.reset(ap_rst),
.din0(a_q1),
.din1(b_load_3_reg_604),
.din2(tmp_2_4_reg_649),
.ce(1'b1),
.dout(grp_fu_432_p3)
);
matrix_mult_mac_mcud #(
.ID( 1 ),
.NUM_STAGE( 3 ),
.din0_WIDTH( 8 ),
.din1_WIDTH( 8 ),
.din2_WIDTH( 16 ),
.dout_WIDTH( 16 ))
matrix_mult_mac_mcud_U3(
.clk(ap_clk),
.reset(ap_rst),
.din0(a_q0),
.din1(reg_205),
.din2(tmp_2_1_reg_654),
.ce(1'b1),
.dout(grp_fu_439_p3)
);
matrix_mult_mac_mdEe #(
.ID( 1 ),
.NUM_STAGE( 3 ),
.din0_WIDTH( 8 ),
.din1_WIDTH( 8 ),
.din2_WIDTH( 16 ),
.dout_WIDTH( 16 ))
matrix_mult_mac_mdEe_U4(
.clk(ap_clk),
.reset(ap_rst),
.din0(reg_209),
.din1(b_q1),
.din2(tmp4_reg_669),
.ce(1'b1),
.dout(grp_fu_446_p3)
);
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_fsm_state1;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter0 <= 1'b0;
end else begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011011 == 1'b0) & (1'b1 == ap_condition_pp0_exit_iter0_state2))) begin
ap_enable_reg_pp0_iter0 <= 1'b0;
end else if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin
ap_enable_reg_pp0_iter0 <= 1'b1;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter1 <= 1'b0;
end else begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011011 == 1'b0))) begin
if ((1'b1 == ap_condition_pp0_exit_iter0_state2)) begin
ap_enable_reg_pp0_iter1 <= (ap_condition_pp0_exit_iter0_state2 ^ 1'b1);
end else if ((1'b1 == 1'b1)) begin
ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0;
end
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter2 <= 1'b0;
end else begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011011 == 1'b0))) begin
ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter3 <= 1'b0;
end else begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011011 == 1'b0))) begin
ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter4 <= 1'b0;
end else begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011011 == 1'b0))) begin
ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3;
end else if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin
ap_enable_reg_pp0_iter4 <= 1'b0;
end
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (exitcond_flatten_reg_453 == 1'd0))) begin
i_reg_183 <= i_cast6_mid2_v_reg_471;
end else if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin
i_reg_183 <= 3'd0;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (exitcond_flatten_reg_453 == 1'd0))) begin
indvar_flatten_reg_172 <= indvar_flatten_next_reg_457;
end else if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin
indvar_flatten_reg_172 <= 5'd0;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (exitcond_flatten_reg_453 == 1'd0))) begin
j_reg_194 <= j_1_reg_524;
end else if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin
j_reg_194 <= 3'd0;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage2_flag00011001 == 1'b0) & (1'd0 == ap_reg_pp0_iter2_exitcond_flatten_reg_453))) begin
reg_209 <= a_q0;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00011001 == 1'b0) & (1'd0 == ap_reg_pp0_iter1_exitcond_flatten_reg_453))) begin
reg_209 <= a_q1;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00011001 == 1'b0) & (1'd0 == ap_reg_pp0_iter1_exitcond_flatten_reg_453))) begin
a_load_1_reg_544 <= a_q0;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011001 == 1'b0))) begin
ap_reg_pp0_iter1_exitcond_flatten_reg_453 <= exitcond_flatten_reg_453;
ap_reg_pp0_iter1_j_mid2_reg_462 <= j_mid2_reg_462;
ap_reg_pp0_iter2_exitcond_flatten_reg_453 <= ap_reg_pp0_iter1_exitcond_flatten_reg_453;
ap_reg_pp0_iter2_j_mid2_reg_462 <= ap_reg_pp0_iter1_j_mid2_reg_462;
ap_reg_pp0_iter3_exitcond_flatten_reg_453 <= ap_reg_pp0_iter2_exitcond_flatten_reg_453;
ap_reg_pp0_iter4_exitcond_flatten_reg_453 <= ap_reg_pp0_iter3_exitcond_flatten_reg_453;
exitcond_flatten_reg_453 <= exitcond_flatten_fu_214_p2;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00011001 == 1'b0))) begin
ap_reg_pp0_iter1_j_cast5_cast3_reg_488[2 : 0] <= j_cast5_cast3_reg_488[2 : 0];
ap_reg_pp0_iter1_tmp_7_reg_478 <= tmp_7_reg_478;
ap_reg_pp0_iter2_j_cast5_cast3_reg_488[2 : 0] <= ap_reg_pp0_iter1_j_cast5_cast3_reg_488[2 : 0];
ap_reg_pp0_iter2_tmp_7_reg_478 <= ap_reg_pp0_iter1_tmp_7_reg_478;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011001 == 1'b0))) begin
ap_reg_pp0_iter3_tmp_16_reg_619 <= tmp_16_reg_619;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (exitcond_flatten_reg_453 == 1'd0))) begin
b_load_1_reg_539 <= b_q1;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_enable_reg_pp0_iter2) & (1'd0 == ap_reg_pp0_iter2_exitcond_flatten_reg_453) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00011001 == 1'b0))) begin
b_load_3_reg_604 <= b_q0;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter0) & (1'd0 == exitcond_flatten_fu_214_p2))) begin
i_cast6_mid2_v_reg_471 <= i_cast6_mid2_v_fu_246_p3;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter0))) begin
indvar_flatten_next_reg_457 <= indvar_flatten_next_fu_220_p2;
end
end
always @ (posedge ap_clk) begin
if (((exitcond_flatten_reg_453 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter0))) begin
j_1_reg_524 <= j_1_fu_310_p2;
end
end
always @ (posedge ap_clk) begin
if (((exitcond_flatten_reg_453 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00011001 == 1'b0))) begin
j_cast5_cast3_reg_488[2 : 0] <= j_cast5_cast3_fu_274_p1[2 : 0];
tmp_12_reg_494 <= tmp_12_fu_280_p2;
tmp_15_reg_499 <= tmp_15_fu_286_p2;
tmp_7_reg_478 <= tmp_7_fu_268_p2;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (1'd0 == exitcond_flatten_fu_214_p2))) begin
j_mid2_reg_462 <= j_mid2_fu_238_p3;
end
end
always @ (posedge ap_clk) begin
if ((((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (exitcond_flatten_reg_453 == 1'd0)) | ((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage2_flag00011001 == 1'b0) & (1'd0 == ap_reg_pp0_iter2_exitcond_flatten_reg_453)))) begin
reg_205 <= b_q0;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011001 == 1'b0) & (1'd0 == ap_reg_pp0_iter3_exitcond_flatten_reg_453) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
tmp1_reg_674 <= grp_fu_439_p3;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (1'd0 == ap_reg_pp0_iter3_exitcond_flatten_reg_453) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
tmp3_reg_679 <= grp_fu_446_p3;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00011001 == 1'b0) & (1'd0 == ap_reg_pp0_iter3_exitcond_flatten_reg_453) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
tmp4_reg_669 <= grp_fu_432_p3;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (1'd0 == ap_reg_pp0_iter1_exitcond_flatten_reg_453))) begin
tmp_10_reg_569 <= tmp_10_fu_347_p2;
tmp_9_reg_564 <= tmp_9_fu_342_p2;
end
end
always @ (posedge ap_clk) begin
if (((exitcond_flatten_reg_453 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011001 == 1'b0))) begin
tmp_11_reg_509 <= tmp_11_fu_297_p2;
tmp_8_reg_504 <= tmp_8_fu_292_p2;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011001 == 1'b0) & (1'd0 == ap_reg_pp0_iter2_exitcond_flatten_reg_453))) begin
tmp_13_reg_614 <= tmp_13_fu_387_p2;
tmp_16_reg_619 <= tmp_16_fu_392_p2;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011001 == 1'b0) & (1'd0 == ap_reg_pp0_iter1_exitcond_flatten_reg_453))) begin
tmp_14_reg_549 <= tmp_14_fu_323_p2;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00011001 == 1'b0) & (1'd0 == ap_reg_pp0_iter3_exitcond_flatten_reg_453))) begin
tmp_2_1_reg_654 <= grp_fu_362_p2;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (1'd0 == ap_reg_pp0_iter2_exitcond_flatten_reg_453))) begin
tmp_2_4_reg_649 <= grp_fu_336_p2;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00011001 == 1'b0) & (1'd0 == ap_reg_pp0_iter4_exitcond_flatten_reg_453))) begin
tmp_3_4_reg_684 <= tmp_3_4_fu_424_p2;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
a_address0 = tmp_7_cast_fu_380_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter2) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
a_address0 = tmp_9_cast_fu_368_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
a_address0 = tmp_8_cast_fu_315_p1;
end else begin
a_address0 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_enable_reg_pp0_iter2) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
a_address1 = tmp_10_cast_fu_372_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
a_address1 = tmp_11_cast_fu_319_p1;
end else begin
a_address1 = 'bx;
end
end
always @ (*) begin
if ((((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00011001 == 1'b0)) | ((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage2_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter2) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00011001 == 1'b0)))) begin
a_ce0 = 1'b1;
end else begin
a_ce0 = 1'b0;
end
end
always @ (*) begin
if ((((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter2) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00011001 == 1'b0)))) begin
a_ce1 = 1'b1;
end else begin
a_ce1 = 1'b0;
end
end
always @ (*) begin
if ((exitcond_flatten_fu_214_p2 == 1'd1)) begin
ap_condition_pp0_exit_iter0_state2 = 1'b1;
end else begin
ap_condition_pp0_exit_iter0_state2 = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state17)) begin
ap_done = 1'b1;
end else begin
ap_done = 1'b0;
end
end
always @ (*) begin
if (((1'b0 == ap_start) & (1'b1 == ap_CS_fsm_state1))) begin
ap_idle = 1'b1;
end else begin
ap_idle = 1'b0;
end
end
always @ (*) begin
if (((1'b0 == ap_enable_reg_pp0_iter0) & (1'b0 == ap_enable_reg_pp0_iter1) & (1'b0 == ap_enable_reg_pp0_iter2) & (1'b0 == ap_enable_reg_pp0_iter3) & (1'b0 == ap_enable_reg_pp0_iter4))) begin
ap_idle_pp0 = 1'b1;
end else begin
ap_idle_pp0 = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state17)) begin
ap_ready = 1'b1;
end else begin
ap_ready = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_enable_reg_pp0_iter2) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
b_address0 = j_cast5_fu_376_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
b_address0 = tmp_14_cast_fu_352_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter0) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
b_address0 = tmp_15_cast_fu_306_p1;
end else begin
b_address0 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter3) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
b_address1 = tmp_13_cast_fu_404_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter0) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
b_address1 = tmp_12_cast_fu_302_p1;
end else begin
b_address1 = 'bx;
end
end
always @ (*) begin
if ((((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter0)) | ((1'b1 == ap_enable_reg_pp0_iter2) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00011001 == 1'b0)) | ((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter2)))) begin
b_ce0 = 1'b1;
end else begin
b_ce0 = 1'b0;
end
end
always @ (*) begin
if ((((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter0)) | ((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter3)))) begin
b_ce1 = 1'b1;
end else begin
b_ce1 = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (exitcond_flatten_reg_453 == 1'd0) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
i_phi_fu_187_p4 = i_cast6_mid2_v_reg_471;
end else begin
i_phi_fu_187_p4 = i_reg_183;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (exitcond_flatten_reg_453 == 1'd0) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
indvar_flatten_phi_fu_176_p4 = indvar_flatten_next_reg_457;
end else begin
indvar_flatten_phi_fu_176_p4 = indvar_flatten_reg_172;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (exitcond_flatten_reg_453 == 1'd0) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
j_phi_fu_198_p4 = j_1_reg_524;
end else begin
j_phi_fu_198_p4 = j_reg_194;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
prod_ce0 = 1'b1;
end else begin
prod_ce0 = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter4) & (1'd0 == ap_reg_pp0_iter4_exitcond_flatten_reg_453))) begin
prod_we0 = 1'b1;
end else begin
prod_we0 = 1'b0;
end
end
always @ (*) begin
case (ap_CS_fsm)
ap_ST_fsm_state1 : begin
if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage0;
end else begin
ap_NS_fsm = ap_ST_fsm_state1;
end
end
ap_ST_fsm_pp0_stage0 : begin
if (((ap_block_pp0_stage0_flag00011011 == 1'b0) & ~((1'b1 == ap_enable_reg_pp0_iter0) & (ap_block_pp0_stage0_flag00011011 == 1'b0) & (exitcond_flatten_fu_214_p2 == 1'd1) & (ap_enable_reg_pp0_iter1 == 1'b0)))) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (ap_block_pp0_stage0_flag00011011 == 1'b0) & (exitcond_flatten_fu_214_p2 == 1'd1) & (ap_enable_reg_pp0_iter1 == 1'b0))) begin
ap_NS_fsm = ap_ST_fsm_state17;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage0;
end
end
ap_ST_fsm_pp0_stage1 : begin
if ((ap_block_pp0_stage1_flag00011011 == 1'b0)) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage2;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage1;
end
end
ap_ST_fsm_pp0_stage2 : begin
if (((ap_block_pp0_stage2_flag00011011 == 1'b0) & ~((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter4) & (ap_block_pp0_stage2_flag00011011 == 1'b0) & (ap_enable_reg_pp0_iter3 == 1'b0)))) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage0;
end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter4) & (ap_block_pp0_stage2_flag00011011 == 1'b0) & (ap_enable_reg_pp0_iter3 == 1'b0))) begin
ap_NS_fsm = ap_ST_fsm_state17;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage2;
end
end
ap_ST_fsm_state17 : begin
ap_NS_fsm = ap_ST_fsm_state1;
end
default : begin
ap_NS_fsm = 'bx;
end
endcase
end
assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1];
assign ap_CS_fsm_pp0_stage1 = ap_CS_fsm[32'd2];
assign ap_CS_fsm_pp0_stage2 = ap_CS_fsm[32'd3];
assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];
assign ap_CS_fsm_state17 = ap_CS_fsm[32'd4];
assign ap_block_pp0_stage0_flag00000000 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage0_flag00011001 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage0_flag00011011 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage1_flag00000000 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage1_flag00011001 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage1_flag00011011 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage2_flag00000000 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage2_flag00011001 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage2_flag00011011 = ~(1'b1 == 1'b1);
assign ap_block_state10_pp0_stage2_iter2 = ~(1'b1 == 1'b1);
assign ap_block_state11_pp0_stage0_iter3 = ~(1'b1 == 1'b1);
assign ap_block_state12_pp0_stage1_iter3 = ~(1'b1 == 1'b1);
assign ap_block_state13_pp0_stage2_iter3 = ~(1'b1 == 1'b1);
assign ap_block_state14_pp0_stage0_iter4 = ~(1'b1 == 1'b1);
assign ap_block_state15_pp0_stage1_iter4 = ~(1'b1 == 1'b1);
assign ap_block_state16_pp0_stage2_iter4 = ~(1'b1 == 1'b1);
assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1);
assign ap_block_state3_pp0_stage1_iter0 = ~(1'b1 == 1'b1);
assign ap_block_state4_pp0_stage2_iter0 = ~(1'b1 == 1'b1);
assign ap_block_state5_pp0_stage0_iter1 = ~(1'b1 == 1'b1);
assign ap_block_state6_pp0_stage1_iter1 = ~(1'b1 == 1'b1);
assign ap_block_state7_pp0_stage2_iter1 = ~(1'b1 == 1'b1);
assign ap_block_state8_pp0_stage0_iter2 = ~(1'b1 == 1'b1);
assign ap_block_state9_pp0_stage1_iter2 = ~(1'b1 == 1'b1);
assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1);
assign exitcond_flatten_fu_214_p2 = ((indvar_flatten_phi_fu_176_p4 == 5'd25) ? 1'b1 : 1'b0);
assign exitcond_fu_232_p2 = ((j_phi_fu_198_p4 == 3'd5) ? 1'b1 : 1'b0);
assign i_1_fu_226_p2 = (i_phi_fu_187_p4 + 3'd1);
assign i_cast6_mid2_cast_fu_254_p1 = i_cast6_mid2_v_reg_471;
assign i_cast6_mid2_v_fu_246_p3 = ((exitcond_fu_232_p2[0:0] === 1'b1) ? i_1_fu_226_p2 : i_phi_fu_187_p4);
assign indvar_flatten_next_fu_220_p2 = (indvar_flatten_phi_fu_176_p4 + 5'd1);
assign j_1_fu_310_p2 = (j_mid2_reg_462 + 3'd1);
assign j_cast5_cast3_fu_274_p1 = j_mid2_reg_462;
assign j_cast5_cast4_fu_384_p1 = ap_reg_pp0_iter2_j_mid2_reg_462;
assign j_cast5_cast_fu_277_p1 = j_mid2_reg_462;
assign j_cast5_fu_376_p1 = ap_reg_pp0_iter2_j_mid2_reg_462;
assign j_mid2_fu_238_p3 = ((exitcond_fu_232_p2[0:0] === 1'b1) ? 3'd0 : j_phi_fu_198_p4);
assign p_shl_cast_fu_264_p1 = tmp_fu_257_p3;
assign prod_address0 = tmp_16_cast_fu_428_p1;
assign prod_d0 = tmp_3_4_reg_684;
assign tmp_10_cast_fu_372_p1 = $signed(tmp_10_reg_569);
assign tmp_10_fu_347_p2 = (ap_reg_pp0_iter1_tmp_7_reg_478 + 6'd3);
assign tmp_11_cast_fu_319_p1 = $signed(tmp_11_reg_509);
assign tmp_11_fu_297_p2 = (tmp_7_reg_478 + 6'd4);
assign tmp_12_cast_fu_302_p1 = tmp_12_reg_494;
assign tmp_12_fu_280_p2 = (j_cast5_cast_fu_277_p1 + 4'd5);
assign tmp_13_cast_fu_404_p1 = tmp_13_reg_614;
assign tmp_13_fu_387_p2 = (ap_reg_pp0_iter2_j_cast5_cast3_reg_488 + 5'd10);
assign tmp_14_cast_fu_352_p1 = tmp_14_reg_549;
assign tmp_14_fu_323_p2 = (ap_reg_pp0_iter1_j_cast5_cast3_reg_488 + 5'd15);
assign tmp_15_cast_fu_306_p1 = tmp_15_reg_499;
assign tmp_15_fu_286_p2 = ($signed(j_cast5_cast3_fu_274_p1) + $signed(5'd20));
assign tmp_16_cast_fu_428_p1 = ap_reg_pp0_iter3_tmp_16_reg_619;
assign tmp_16_fu_392_p2 = (ap_reg_pp0_iter2_tmp_7_reg_478 + j_cast5_cast4_fu_384_p1);
assign tmp_3_4_fu_424_p2 = ($signed(tmp1_reg_674) + $signed(tmp3_reg_679));
assign tmp_7_cast_fu_380_p1 = ap_reg_pp0_iter2_tmp_7_reg_478;
assign tmp_7_fu_268_p2 = (i_cast6_mid2_cast_fu_254_p1 + p_shl_cast_fu_264_p1);
assign tmp_8_cast_fu_315_p1 = tmp_8_reg_504;
assign tmp_8_fu_292_p2 = (tmp_7_reg_478 + 6'd1);
assign tmp_9_cast_fu_368_p1 = $signed(tmp_9_reg_564);
assign tmp_9_fu_342_p2 = (ap_reg_pp0_iter1_tmp_7_reg_478 + 6'd2);
assign tmp_fu_257_p3 = {{i_cast6_mid2_v_reg_471}, {2'd0}};
always @ (posedge ap_clk) begin
j_cast5_cast3_reg_488[4:3] <= 2'b00;
ap_reg_pp0_iter1_j_cast5_cast3_reg_488[4:3] <= 2'b00;
ap_reg_pp0_iter2_j_cast5_cast3_reg_488[4:3] <= 2'b00;
end
endmodule //matrix_mult
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A2111OI_BEHAVIORAL_V
`define SKY130_FD_SC_LP__A2111OI_BEHAVIORAL_V
/**
* a2111oi: 2-input AND into first input of 4-input NOR.
*
* Y = !((A1 & A2) | B1 | C1 | D1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__a2111oi (
Y ,
A1,
A2,
B1,
C1,
D1
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out ;
wire nor0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out_Y, B1, C1, D1, and0_out);
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__A2111OI_BEHAVIORAL_V
|
module wb_7seg_new (clk_i, nrst_i, wb_adr_i, wb_dat_o, wb_dat_i, wb_sel_i, wb_we_i,
wb_stb_i, wb_cyc_i, wb_ack_o, wb_err_o, wb_int_o, DISP_SEL, DISP_LED);
input clk_i;
input nrst_i;
input [24:1] wb_adr_i;
output [15:0] wb_dat_o;
input [15:0] wb_dat_i;
input [1:0] wb_sel_i;
input wb_we_i;
input wb_stb_i;
input wb_cyc_i;
output wb_ack_o;
output wb_err_o;
output wb_int_o;
output reg [3:0] DISP_SEL;
output reg [6:0] DISP_LED;
reg [15:0] data_reg;
reg [6:0] disp_cnt;
reg [3:0] disp_data;
wire [6:0] disp_data_led;
reg [3:0] disp_pos;
always @(posedge clk_i or negedge nrst_i)
begin
if (nrst_i == 0)
data_reg <= 16'hABCD;
else
if (wb_stb_i && wb_we_i)
data_reg <= wb_dat_i;
end
assign wb_ack_o = wb_stb_i;
assign wb_err_o = 1'b0;
assign wb_int_o = 1'b0;
assign wb_dat_o = data_reg;
always @(posedge clk_i or negedge nrst_i)
begin
if (nrst_i == 0)
disp_cnt <= 7'b0000000;
else
disp_cnt <= disp_cnt + 1;
end
always @(posedge clk_i or negedge nrst_i)
begin
if (nrst_i == 0)
disp_pos <= 4'b0010;
else
if (disp_cnt == 7'b1111111)
disp_pos <= {DISP_SEL[2] , DISP_SEL[1] , DISP_SEL[0] , DISP_SEL[3]};
end
always @(posedge clk_i or negedge nrst_i)
begin
if (nrst_i == 0)
disp_data <= 4'b0000;
else
case (DISP_SEL)
4'b1000: disp_data <= data_reg[3:0];
4'b0100: disp_data <= data_reg[7:4];
4'b0010: disp_data <= data_reg[11:8];
4'b0001: disp_data <= data_reg[15:12];
endcase
end
disp_dec u0 (disp_data, disp_data_led);
always @(posedge clk_i or negedge nrst_i)
begin
if (nrst_i == 0)
DISP_LED <= 7'b0000000;
else
DISP_LED <= disp_data_led;
end
always @(posedge clk_i or negedge nrst_i)
begin
if (nrst_i == 0)
DISP_SEL <= 0;
else
DISP_SEL <= disp_pos;
end
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Mon May 29 21:36:04 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/ZyboIP/examples/zed_camera_hessian/zed_camera_hessian.srcs/sources_1/bd/system/ip/system_vga_hessian_0_0/system_vga_hessian_0_0_stub.v
// Design : system_vga_hessian_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "vga_hessian,Vivado 2016.4" *)
module system_vga_hessian_0_0(clk_x16, active, rst, x_addr, y_addr, g_in,
hessian_out)
/* synthesis syn_black_box black_box_pad_pin="clk_x16,active,rst,x_addr[9:0],y_addr[9:0],g_in[7:0],hessian_out[31:0]" */;
input clk_x16;
input active;
input rst;
input [9:0]x_addr;
input [9:0]y_addr;
input [7:0]g_in;
output [31:0]hessian_out;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:20:54 03/02/2016
// Design Name:
// Module Name: alu
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module alu(
output zero,
output [31:0] aluRes,
input [31:0] input1,
input [31:0] input2,
input [3:0] aluCtr
);
reg zero;
reg [31:0] aluRes;
always @ (input1 or input2 or aluCtr)
begin
if(aluCtr == 4'b0010) //+
aluRes = input1 + input2;
else if(aluCtr == 4'b0110) //-
begin
aluRes = input1 - input2;
if(aluRes == 0)
zero = 1;
else
zero = 0;
end
else if(aluCtr == 4'b0000) //&
begin
aluRes = input1 & input2;
if(aluRes == 0)
zero = 1;
else
zero = 0;
end
else if(aluCtr == 4'b0001) //|
begin
aluRes = input1 | input2;
if(aluRes == 0)
zero = 1;
else
zero = 0;
end
else if(aluCtr == 4'b0111) //slt
begin
if(input1 < input2)
begin
zero = 0;
aluRes = 1;
end
else
begin
zero = 1;
aluRes = 0;
end
end
else if(aluCtr == 4'b1100) //NOR
begin
aluRes = ~(input1 | input2);
if(aluRes == 0)
zero = 1;
else
zero = 0;
end
end
endmodule
|
// file: clk_wiz_0.v
//
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// CLK_OUT1____50.000______0.000______50.0______151.636_____98.575
// CLK_OUT2____25.000______0.000______50.0______175.402_____98.575
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
//----------------------------------------------------------------------------
// __primary_________100.000____________0.010
`timescale 1ps/1ps
module clk_wiz_0_clk_wiz
(// Clock in ports
input clk_in1,
// Clock out ports
output clk_out1,
output clk_out2,
// Status and control signals
output locked
);
// Input buffering
//------------------------------------
IBUF clkin1_ibufg
(.O (clk_in1_clk_wiz_0),
.I (clk_in1));
// Clocking PRIMITIVE
//------------------------------------
// Instantiation of the MMCM PRIMITIVE
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire [15:0] do_unused;
wire drdy_unused;
wire psdone_unused;
wire locked_int;
wire clkfbout_clk_wiz_0;
wire clkfbout_buf_clk_wiz_0;
wire clkfboutb_unused;
wire clkout0b_unused;
wire clkout1b_unused;
wire clkout2_unused;
wire clkout2b_unused;
wire clkout3_unused;
wire clkout3b_unused;
wire clkout4_unused;
wire clkout5_unused;
wire clkout6_unused;
wire clkfbstopped_unused;
wire clkinstopped_unused;
MMCME2_ADV
#(.BANDWIDTH ("OPTIMIZED"),
.CLKOUT4_CASCADE ("FALSE"),
.COMPENSATION ("ZHOLD"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (1),
.CLKFBOUT_MULT_F (8.000),
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS ("FALSE"),
.CLKOUT0_DIVIDE_F (20.000),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKOUT1_DIVIDE (40),
.CLKOUT1_PHASE (0.000),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKOUT1_USE_FINE_PS ("FALSE"),
.CLKIN1_PERIOD (10.0),
.REF_JITTER1 (0.010))
mmcm_adv_inst
// Output clocks
(
.CLKFBOUT (clkfbout_clk_wiz_0),
.CLKFBOUTB (clkfboutb_unused),
.CLKOUT0 (clk_out1_clk_wiz_0),
.CLKOUT0B (clkout0b_unused),
.CLKOUT1 (clk_out2_clk_wiz_0),
.CLKOUT1B (clkout1b_unused),
.CLKOUT2 (clkout2_unused),
.CLKOUT2B (clkout2b_unused),
.CLKOUT3 (clkout3_unused),
.CLKOUT3B (clkout3b_unused),
.CLKOUT4 (clkout4_unused),
.CLKOUT5 (clkout5_unused),
.CLKOUT6 (clkout6_unused),
// Input clock control
.CLKFBIN (clkfbout_buf_clk_wiz_0),
.CLKIN1 (clk_in1_clk_wiz_0),
.CLKIN2 (1'b0),
// Tied to always select the primary input clock
.CLKINSEL (1'b1),
// Ports for dynamic reconfiguration
.DADDR (7'h0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'h0),
.DO (do_unused),
.DRDY (drdy_unused),
.DWE (1'b0),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (psdone_unused),
// Other control and status signals
.LOCKED (locked_int),
.CLKINSTOPPED (clkinstopped_unused),
.CLKFBSTOPPED (clkfbstopped_unused),
.PWRDWN (1'b0),
.RST (1'b0));
assign locked = locked_int;
// Output buffering
//-----------------------------------
BUFG clkf_buf
(.O (clkfbout_buf_clk_wiz_0),
.I (clkfbout_clk_wiz_0));
BUFG clkout1_buf
(.O (clk_out1),
.I (clk_out1_clk_wiz_0));
BUFG clkout2_buf
(.O (clk_out2),
.I (clk_out2_clk_wiz_0));
endmodule
|
//
// Copyright (c) 2015 Jan Adelsbach <[email protected]>.
// All Rights Reserved.
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
/*
* FIXME: I assume that the storage location for channel exchange packets is
* always on core memory bank 0. Is this corrent?
*
* TODO: Replace logic buffer with regs quirk with system verilog "logic"
*/
/*
* The module behaves the same for channel 1 independently of whether it is
* initiated with SBS or SBS16, however if only using a normal SBS
* instantiating the module with the latter decreases LUT usage.
*/
module pdp1_sbs_decoder(sb_ireq1, sb_ireq2, sb_ireq3, sb_ireq4,
sav_ac, sav_io, sav_pc, sav_jmp);
parameter sbs_model = "SBS";
input sb_ireq1;
input sb_ireq2;
input sb_ireq3;
input sb_ireq4;
output [0:11] sav_ac;
output [0:11] sav_io;
output [0:11] sav_pc;
output [0:11] sav_jmp;
generate
if(sbs_model == "SBS") begin
assign sav_ac = 12'o0000;
assign sav_io = 12'o0002;
assign sav_pc = 12'o0001;
assign sav_jmp = 12'o0003;
end
else begin
reg [0:11] r_ac;
reg [0:11] r_pc;
reg [0:11] r_io;
reg [0:11] r_jmp;
assign sav_ac = r_ac;
assign sav_io = r_io;
assign sav_jmp = r_jmp;
assign sav_pc = r_pc;
always @(sb_ireq1 or sb_ireq2 or sb_ireq3 or sb_ireq4) begin
case({sb_ireq1, sb_ireq2, sb_ireq3, sb_ireq4})
4'b1XXX:
begin
r_ac <= 12'o0000;
r_pc <= 12'o0001;
r_io <= 12'o0002;
r_jmp <= 12'o0003;
end
4'bX1XX:
begin
r_ac <= 12'o0004;
r_pc <= 12'o0005;
r_io <= 12'o0006;
r_jmp <= 12'o0007;
end
4'bXX1X:
begin
r_ac <= 12'o0010;
r_pc <= 12'o0011;
r_io <= 12'o0012;
r_jmp <= 12'o0013;
end
4'bXXX1:
begin
r_ac <= 12'o0014;
r_pc <= 12'o0015;
r_io <= 12'o0016;
r_jmp <= 12'o0017;
end
default:
begin
r_ac <= 12'o0000;
r_pc <= 12'o0000;
r_io <= 12'o0000;
r_jmp <= 12'o0000;
end
endcase // case ({sb_ireq1, sb_ireq2, sb_ireq3, sb_ireq4})
end
end
endgenerate
endmodule // pdp1_sbs_decoder
|
/// date:2016/3/9
/// engineer: ZhaiShaoMin
module m_d_areg(//input
clk,
rst,
m_flits_d,
v_m_flits_d,
dc_done_access,
//output
m_d_areg_flits,
v_m_d_areg_flits,
m_d_areg_state
);
//input
input clk;
input rst;
input [143:0] m_flits_d;
input v_m_flits_d;
input dc_done_access;
//output
output [143:0] m_d_areg_flits;
output v_m_d_areg_flits;
output m_d_areg_state;
reg m_d_cstate;
reg [143:0] flits_reg;
assign v_m_d_areg_flits=m_d_cstate;
assign m_d_areg_state=m_d_cstate;// when m_d_cstate is 1, it means this module is busy and
// can't receive other flits. oterwise,able to receiving flits
always@(posedge clk)
begin
if(rst||dc_done_access)
flits_reg<=144'h0000;
else if(v_m_flits_d)
flits_reg<=m_flits_d;
end
always@(posedge clk)
begin
if(rst||dc_done_access)
m_d_cstate<=1'b0;
else if(v_m_flits_d)
m_d_cstate<=1'b1;
end
assign m_d_areg_flits=flits_reg;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NOR3B_PP_SYMBOL_V
`define SKY130_FD_SC_MS__NOR3B_PP_SYMBOL_V
/**
* nor3b: 3-input NOR, first input inverted.
*
* Y = (!(A | B)) & !C)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__nor3b (
//# {{data|Data Signals}}
input A ,
input B ,
input C_N ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__NOR3B_PP_SYMBOL_V
|
//-----------------------------------------------------------------------------
// processing_system7
// processor sub system wrapper
//-----------------------------------------------------------------------------
//
// ************************************************************************
// ** DISCLAIMER OF LIABILITY **
// ** **
// ** This file contains proprietary and confidential information of **
// ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
// ** from Xilinx, and may be used, copied and/or diSCLosed only **
// ** pursuant to the terms of a valid license agreement with Xilinx. **
// ** **
// ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
// ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
// ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
// ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
// ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
// ** does not warrant that functions included in the Materials will **
// ** meet the requirements of Licensee, or that the operation of the **
// ** Materials will be uninterrupted or error-free, or that defects **
// ** in the Materials will be corrected. Furthermore, Xilinx does **
// ** not warrant or make any representations regarding use, or the **
// ** results of the use, of the Materials in terms of correctness, **
// ** accuracy, reliability or otherwise. **
// ** **
// ** Xilinx products are not designed or intended to be fail-safe, **
// ** or for use in any application requiring fail-safe performance, **
// ** such as life-support or safety devices or systems, Class III **
// ** medical devices, nuclear facilities, applications related to **
// ** the deployment of airbags, or any other applications that could **
// ** lead to death, personal injury or severe property or **
// ** environmental damage (individually and collectively, "critical **
// ** applications"). Customer assumes the sole risk and liability **
// ** of any use of Xilinx products in critical applications, **
// ** subject only to applicable laws and regulations governing **
// ** limitations on product liability. **
// ** **
// ** Copyright 2010 Xilinx, Inc. **
// ** All rights reserved. **
// ** **
// ** This disclaimer and copyright notice must be retained as part **
// ** of this file at all times. **
// ************************************************************************
//
//-----------------------------------------------------------------------------
// Filename: processing_system7_v5_5_processing_system7.v
// Version: v1.00.a
// Description: This is the wrapper file for PSS.
//-----------------------------------------------------------------------------
// Structure: This section shows the hierarchical structure of
// pss_wrapper.
//
// --processing_system7_v5_5_processing_system7.v
// --PS7.v - Unisim component
//-----------------------------------------------------------------------------
// Author: SD
//
// History:
//
// SD 09/20/11 -- First version
// ~~~~~~
// Created the first version v2.00.a
// ^^^^^^
//------------------------------------------------------------------------------
// ^^^^^^
// SR 11/25/11 -- v3.00.a version
// ~~~~~~~
// Key changes are
// 1. Changed all clock, reset and clktrig ports to be individual
// signals instead of vectors. This is required for modeling of tools.
// 2. Interrupts are now defined as individual signals as well.
// 3. Added Clk buffer logic for FCLK_CLK
// 4. Includes the ACP related changes done
//
// TODO:
// 1. C_NUM_F2P_INTR_INPUTS needs to have control on the
// number of interrupt ports connected for IRQ_F2P.
//
//------------------------------------------------------------------------------
// ^^^^^^
// KP 12/07/11 -- v3.00.a version
// ~~~~~~~
// Key changes are
// C_NUM_F2P_INTR_INPUTS taken into account for IRQ_F2P
//------------------------------------------------------------------------------
// ^^^^^^
// NR 12/09/11 -- v3.00.a version
// ~~~~~~~
// Key changes are
// C_FCLK_CLK0_BUF to C_FCLK_CLK3_BUF parameters were updated
// to STRING and fix for CR 640523
//------------------------------------------------------------------------------
// ^^^^^^
// NR 12/13/11 -- v3.00.a version
// ~~~~~~~
// Key changes are
// Updated IRQ_F2P logic to address CR 641523.
//------------------------------------------------------------------------------
// ^^^^^^
// NR 02/01/12 -- v3.01.a version
// ~~~~~~~
// Key changes are
// Updated SDIO logic to address CR 636210.
// |
// Added C_PS7_SI_REV parameter to track SI Rev
// Removed compress/decompress logic to address CR 642527.
//------------------------------------------------------------------------------
// ^^^^^^
// NR 02/27/12 -- v3.01.a version
// ~~~~~~~
// Key changes are
// TTC(0,1)_WAVE_OUT and TTC(0,1)_CLK_IN vector signals are made as individual
// ports as fix for CR 646379
//------------------------------------------------------------------------------
// ^^^^^^
// NR 03/05/12 -- v3.01.a version
// ~~~~~~~
// Key changes are
// Added/updated compress/decompress logic to address 648393
//------------------------------------------------------------------------------
// ^^^^^^
// NR 03/14/12 -- v4.00.a version
// ~~~~~~~
// Unused parameters deleted CR 651120
// Addressed CR 651751
//------------------------------------------------------------------------------
// ^^^^^^
// NR 04/17/12 -- v4.01.a version
// ~~~~~~~
// Added FTM trace buffer functionality
// Added support for ACP AxUSER ports local update
//------------------------------------------------------------------------------
// ^^^^^^
// VR 05/18/12 -- v4.01.a version
// ~~~~~~~
// Fixed CR#659157
//------------------------------------------------------------------------------
// ^^^^^^
// VR 07/25/12 -- v4.01.a version
// ~~~~~~~
// Changed S_AXI_HP{1,2}_WACOUNT port's width to 6 from 8 to match unisim model
// Changed fclk_clktrig_gnd width to 4 from 16 to match unisim model
//------------------------------------------------------------------------------
// ^^^^^^
// VR 11/06/12 -- v5.00 version
// ~~~~~~~
// CR #682573
// Added BIBUF to fixed IO ports and IBUF to fixed input ports
//------------------------------------------------------------------------------
(*POWER= "<PROCESSOR name={system} numA9Cores={2} clockFreq={666.666667} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={533.333313} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={10} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={111.111115} usageRate={0.5} /><IO interface={I2C} ioStandard={} bidis={1} ioBank={} clockFreq={111.111115} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={8} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={6} ioBank={Vcco_p0} clockFreq={200} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1066.667} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>" *)
(* CORE_GENERATION_INFO = "processing_system7_v5.5 ,processing_system7_v5.5_user_configuration,{ PCW_UIPARAM_DDR_FREQ_MHZ=533.333313, PCW_UIPARAM_DDR_BANK_ADDR_COUNT=3, PCW_UIPARAM_DDR_ROW_ADDR_COUNT=14, PCW_UIPARAM_DDR_COL_ADDR_COUNT=10, PCW_UIPARAM_DDR_CL=7, PCW_UIPARAM_DDR_CWL=6, PCW_UIPARAM_DDR_T_RCD=7, PCW_UIPARAM_DDR_T_RP=7, PCW_UIPARAM_DDR_T_RC=49.5, PCW_UIPARAM_DDR_T_RAS_MIN=36.0, PCW_UIPARAM_DDR_T_FAW=45.0, PCW_UIPARAM_DDR_AL=0, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0=0.025, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1=0.028, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2=-0.009, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3=-0.061, PCW_UIPARAM_DDR_BOARD_DELAY0=0.41, PCW_UIPARAM_DDR_BOARD_DELAY1=0.411, PCW_UIPARAM_DDR_BOARD_DELAY2=0.341, PCW_UIPARAM_DDR_BOARD_DELAY3=0.358, PCW_UIPARAM_DDR_DQS_0_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_1_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_2_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_3_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_0_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_1_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_2_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_3_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH=68.4725, PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH=71.086, PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH=66.794, PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH=108.7385, PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH=64.1705, PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH=63.686, PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH=68.46, PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH=105.4895, PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH=61.0905, PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH=61.0905, PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH=61.0905, PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH=61.0905, PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY=160\
, PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY=160, PCW_CRYSTAL_PERIPHERAL_FREQMHZ=33.333333, PCW_APU_PERIPHERAL_FREQMHZ=666.666667, PCW_DCI_PERIPHERAL_FREQMHZ=10.159, PCW_QSPI_PERIPHERAL_FREQMHZ=200, PCW_SMC_PERIPHERAL_FREQMHZ=100, PCW_USB0_PERIPHERAL_FREQMHZ=60, PCW_USB1_PERIPHERAL_FREQMHZ=60, PCW_SDIO_PERIPHERAL_FREQMHZ=50, PCW_UART_PERIPHERAL_FREQMHZ=50, PCW_SPI_PERIPHERAL_FREQMHZ=166.666666, PCW_CAN_PERIPHERAL_FREQMHZ=100, PCW_CAN0_PERIPHERAL_FREQMHZ=-1, PCW_CAN1_PERIPHERAL_FREQMHZ=-1, PCW_WDT_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC_PERIPHERAL_FREQMHZ=50, PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK0_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK1_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK2_PERIPHERAL_FREQMHZ=133.333333, PCW_PCAP_PERIPHERAL_FREQMHZ=200, PCW_TPIU_PERIPHERAL_FREQMHZ=200, PCW_FPGA0_PERIPHERAL_FREQMHZ=100.000000, PCW_FPGA1_PERIPHERAL_FREQMHZ=10.000000, PCW_FPGA2_PERIPHERAL_FREQMHZ=50, PCW_FPGA3_PERIPHERAL_FREQMHZ=50, PCW_OVERRIDE_BASIC_CLOCK=0, PCW_ARMPLL_CTRL_FBDIV=40, PCW_IOPLL_CTRL_FBDIV=30, PCW_DDRPLL_CTRL_FBDIV=32, PCW_CPU_CPU_PLL_FREQMHZ=1333.333, PCW_IO_IO_PLL_FREQMHZ=1000.000, PCW_DDR_DDR_PLL_FREQMHZ=1066.667, PCW_USE_M_AXI_GP0=1, PCW_USE_M_AXI_GP1=0, PCW_USE_S_AXI_GP0=0, PCW_USE_S_AXI_GP1=0, PCW_USE_S_AXI_ACP=0, PCW_USE_S_AXI_HP0=0, PCW_USE_S_AXI_HP1=0, PCW_USE_S_AXI_HP2=0, PCW_USE_S_AXI_HP3=0, PCW_M_AXI_GP0_FREQMHZ=100\
, PCW_M_AXI_GP1_FREQMHZ=10, PCW_S_AXI_GP0_FREQMHZ=10, PCW_S_AXI_GP1_FREQMHZ=10, PCW_S_AXI_ACP_FREQMHZ=10, PCW_S_AXI_HP0_FREQMHZ=10, PCW_S_AXI_HP1_FREQMHZ=10, PCW_S_AXI_HP2_FREQMHZ=10, PCW_S_AXI_HP3_FREQMHZ=10, PCW_USE_CROSS_TRIGGER=0, PCW_FTM_CTI_IN0=DISABLED, PCW_FTM_CTI_IN1=DISABLED, PCW_FTM_CTI_IN2=DISABLED, PCW_FTM_CTI_IN3=DISABLED, PCW_FTM_CTI_OUT0=DISABLED, PCW_FTM_CTI_OUT1=DISABLED, PCW_FTM_CTI_OUT2=DISABLED, PCW_FTM_CTI_OUT3=DISABLED, PCW_UART0_BAUD_RATE=115200, PCW_UART1_BAUD_RATE=115200, PCW_S_AXI_HP0_DATA_WIDTH=64, PCW_S_AXI_HP1_DATA_WIDTH=64, PCW_S_AXI_HP2_DATA_WIDTH=64, PCW_S_AXI_HP3_DATA_WIDTH=64, PCW_IRQ_F2P_MODE=DIRECT, PCW_PRESET_BANK0_VOLTAGE=LVCMOS 3.3V, PCW_PRESET_BANK1_VOLTAGE=LVCMOS 1.8V, PCW_UIPARAM_DDR_ENABLE=1, PCW_UIPARAM_DDR_ADV_ENABLE=0, PCW_UIPARAM_DDR_MEMORY_TYPE=DDR 3, PCW_UIPARAM_DDR_ECC=Disabled, PCW_UIPARAM_DDR_BUS_WIDTH=32 Bit, PCW_UIPARAM_DDR_BL=8, PCW_UIPARAM_DDR_HIGH_TEMP=Normal (0-85), PCW_UIPARAM_DDR_PARTNO=MT41J128M16 HA-15E, PCW_UIPARAM_DDR_DRAM_WIDTH=16 Bits, PCW_UIPARAM_DDR_DEVICE_CAPACITY=2048 MBits, PCW_UIPARAM_DDR_SPEED_BIN=DDR3_1066F, PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL=1, PCW_UIPARAM_DDR_TRAIN_READ_GATE=1, PCW_UIPARAM_DDR_TRAIN_DATA_EYE=1, PCW_UIPARAM_DDR_CLOCK_STOP_EN=0, PCW_UIPARAM_DDR_USE_INTERNAL_VREF=1, PCW_DDR_PORT0_HPR_ENABLE=0, PCW_DDR_PORT1_HPR_ENABLE=0, PCW_DDR_PORT2_HPR_ENABLE=0, PCW_DDR_PORT3_HPR_ENABLE=0, PCW_DDR_HPRLPR_QUEUE_PARTITION=HPR(0)/LPR(32), PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL=2, PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL=15, PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL=2\
, PCW_NAND_PERIPHERAL_ENABLE=0, PCW_NAND_GRP_D8_ENABLE=0, PCW_NOR_PERIPHERAL_ENABLE=0, PCW_NOR_GRP_A25_ENABLE=0, PCW_NOR_GRP_CS0_ENABLE=0, PCW_NOR_GRP_SRAM_CS0_ENABLE=0, PCW_NOR_GRP_CS1_ENABLE=0, PCW_NOR_GRP_SRAM_CS1_ENABLE=0, PCW_NOR_GRP_SRAM_INT_ENABLE=0, PCW_QSPI_PERIPHERAL_ENABLE=1, PCW_QSPI_QSPI_IO=MIO 1 .. 6, PCW_QSPI_GRP_SINGLE_SS_ENABLE=1, PCW_QSPI_GRP_SINGLE_SS_IO=MIO 1 .. 6, PCW_QSPI_GRP_SS1_ENABLE=0, PCW_QSPI_GRP_IO1_ENABLE=0, PCW_QSPI_GRP_FBCLK_ENABLE=0, PCW_QSPI_INTERNAL_HIGHADDRESS=0xFCFFFFFF, PCW_SINGLE_QSPI_DATA_MODE=x4, PCW_ENET0_PERIPHERAL_ENABLE=1, PCW_ENET0_ENET0_IO=MIO 16 .. 27, PCW_ENET0_GRP_MDIO_ENABLE=1, PCW_ENET0_RESET_ENABLE=0, PCW_ENET1_PERIPHERAL_ENABLE=0, PCW_ENET1_GRP_MDIO_ENABLE=0, PCW_ENET1_RESET_ENABLE=0, PCW_SD0_PERIPHERAL_ENABLE=1, PCW_SD0_SD0_IO=MIO 40 .. 45, PCW_SD0_GRP_CD_ENABLE=1, PCW_SD0_GRP_CD_IO=MIO 47, PCW_SD0_GRP_WP_ENABLE=1, PCW_SD0_GRP_WP_IO=MIO 46, PCW_SD0_GRP_POW_ENABLE=0, PCW_SD1_PERIPHERAL_ENABLE=0, PCW_SD1_GRP_CD_ENABLE=0, PCW_SD1_GRP_WP_ENABLE=0, PCW_SD1_GRP_POW_ENABLE=0, PCW_UART0_PERIPHERAL_ENABLE=0, PCW_UART0_GRP_FULL_ENABLE=0, PCW_UART1_PERIPHERAL_ENABLE=1, PCW_UART1_UART1_IO=MIO 48 .. 49, PCW_UART1_GRP_FULL_ENABLE=0, PCW_SPI0_PERIPHERAL_ENABLE=0, PCW_SPI0_GRP_SS0_ENABLE=0, PCW_SPI0_GRP_SS1_ENABLE=0, PCW_SPI0_GRP_SS2_ENABLE=0, PCW_SPI1_PERIPHERAL_ENABLE=0, PCW_SPI1_GRP_SS0_ENABLE=0, PCW_SPI1_GRP_SS1_ENABLE=0, PCW_SPI1_GRP_SS2_ENABLE=0, PCW_CAN0_PERIPHERAL_ENABLE=0\
, PCW_CAN0_GRP_CLK_ENABLE=0, PCW_CAN1_PERIPHERAL_ENABLE=0, PCW_CAN1_GRP_CLK_ENABLE=0, PCW_TRACE_PERIPHERAL_ENABLE=0, PCW_TRACE_GRP_2BIT_ENABLE=0, PCW_TRACE_GRP_4BIT_ENABLE=0, PCW_TRACE_GRP_8BIT_ENABLE=0, PCW_TRACE_GRP_16BIT_ENABLE=0, PCW_TRACE_GRP_32BIT_ENABLE=0, PCW_WDT_PERIPHERAL_ENABLE=0, PCW_TTC0_PERIPHERAL_ENABLE=1, PCW_TTC0_TTC0_IO=EMIO, PCW_TTC1_PERIPHERAL_ENABLE=0, PCW_PJTAG_PERIPHERAL_ENABLE=0, PCW_USB0_PERIPHERAL_ENABLE=1, PCW_USB0_USB0_IO=MIO 28 .. 39, PCW_USB0_RESET_ENABLE=0, PCW_USB1_PERIPHERAL_ENABLE=0, PCW_USB1_RESET_ENABLE=0, PCW_I2C0_PERIPHERAL_ENABLE=1, PCW_I2C0_I2C0_IO=EMIO, PCW_I2C0_GRP_INT_ENABLE=1, PCW_I2C0_GRP_INT_IO=EMIO, PCW_I2C0_RESET_ENABLE=0, PCW_I2C1_PERIPHERAL_ENABLE=0, PCW_I2C1_GRP_INT_ENABLE=0, PCW_I2C1_RESET_ENABLE=0, PCW_GPIO_PERIPHERAL_ENABLE=0, PCW_GPIO_MIO_GPIO_ENABLE=1, PCW_GPIO_MIO_GPIO_IO=MIO, PCW_GPIO_EMIO_GPIO_ENABLE=0, PCW_APU_CLK_RATIO_ENABLE=6:2:1, PCW_ENET0_PERIPHERAL_FREQMHZ=1000 Mbps, PCW_ENET1_PERIPHERAL_FREQMHZ=1000 Mbps, PCW_CPU_PERIPHERAL_CLKSRC=ARM PLL, PCW_DDR_PERIPHERAL_CLKSRC=DDR PLL, PCW_SMC_PERIPHERAL_CLKSRC=IO PLL, PCW_QSPI_PERIPHERAL_CLKSRC=IO PLL, PCW_SDIO_PERIPHERAL_CLKSRC=IO PLL, PCW_UART_PERIPHERAL_CLKSRC=IO PLL, PCW_SPI_PERIPHERAL_CLKSRC=IO PLL, PCW_CAN_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK0_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK1_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK2_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK3_PERIPHERAL_CLKSRC=IO PLL, PCW_ENET0_PERIPHERAL_CLKSRC=IO PLL, PCW_ENET1_PERIPHERAL_CLKSRC=IO PLL, PCW_CAN0_PERIPHERAL_CLKSRC=External, PCW_CAN1_PERIPHERAL_CLKSRC=External\
, PCW_TPIU_PERIPHERAL_CLKSRC=External, PCW_TTC0_CLK0_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC0_CLK1_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC0_CLK2_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK0_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK1_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK2_PERIPHERAL_CLKSRC=CPU_1X, PCW_WDT_PERIPHERAL_CLKSRC=CPU_1X, PCW_DCI_PERIPHERAL_CLKSRC=DDR PLL, PCW_PCAP_PERIPHERAL_CLKSRC=IO PLL, PCW_USB_RESET_POLARITY=Active Low, PCW_ENET_RESET_POLARITY=Active Low, PCW_I2C_RESET_POLARITY=Active Low, PCW_FPGA_FCLK0_ENABLE=1, PCW_FPGA_FCLK1_ENABLE=1, PCW_FPGA_FCLK2_ENABLE=0, PCW_FPGA_FCLK3_ENABLE=0, PCW_NOR_SRAM_CS0_T_TR=1, PCW_NOR_SRAM_CS0_T_PC=1, PCW_NOR_SRAM_CS0_T_WP=1, PCW_NOR_SRAM_CS0_T_CEOE=1, PCW_NOR_SRAM_CS0_T_WC=11, PCW_NOR_SRAM_CS0_T_RC=11, PCW_NOR_SRAM_CS0_WE_TIME=0, PCW_NOR_SRAM_CS1_T_TR=1, PCW_NOR_SRAM_CS1_T_PC=1, PCW_NOR_SRAM_CS1_T_WP=1, PCW_NOR_SRAM_CS1_T_CEOE=1, PCW_NOR_SRAM_CS1_T_WC=11, PCW_NOR_SRAM_CS1_T_RC=11, PCW_NOR_SRAM_CS1_WE_TIME=0, PCW_NOR_CS0_T_TR=1, PCW_NOR_CS0_T_PC=1, PCW_NOR_CS0_T_WP=1, PCW_NOR_CS0_T_CEOE=1, PCW_NOR_CS0_T_WC=11, PCW_NOR_CS0_T_RC=11, PCW_NOR_CS0_WE_TIME=0, PCW_NOR_CS1_T_TR=1, PCW_NOR_CS1_T_PC=1, PCW_NOR_CS1_T_WP=1, PCW_NOR_CS1_T_CEOE=1, PCW_NOR_CS1_T_WC=11, PCW_NOR_CS1_T_RC=11, PCW_NOR_CS1_WE_TIME=0, PCW_NAND_CYCLES_T_RR=1, PCW_NAND_CYCLES_T_AR=1, PCW_NAND_CYCLES_T_CLR=1, PCW_NAND_CYCLES_T_WP=1, PCW_NAND_CYCLES_T_REA=1\
, PCW_NAND_CYCLES_T_WC=11, PCW_NAND_CYCLES_T_RC=11 }" *)
(* HW_HANDOFF = "ip_design_processing_system7_0_0.hwdef" *)
module processing_system7_v5_5_processing_system7
#(
parameter integer C_USE_DEFAULT_ACP_USER_VAL = 1,
parameter integer C_S_AXI_ACP_ARUSER_VAL = 31,
parameter integer C_S_AXI_ACP_AWUSER_VAL = 31,
parameter integer C_M_AXI_GP0_THREAD_ID_WIDTH = 12,
parameter integer C_M_AXI_GP1_THREAD_ID_WIDTH = 12,
parameter integer C_M_AXI_GP0_ENABLE_STATIC_REMAP = 1,
parameter integer C_M_AXI_GP1_ENABLE_STATIC_REMAP = 1,
parameter integer C_M_AXI_GP0_ID_WIDTH = 12,
parameter integer C_M_AXI_GP1_ID_WIDTH = 12,
parameter integer C_S_AXI_GP0_ID_WIDTH = 6,
parameter integer C_S_AXI_GP1_ID_WIDTH = 6,
parameter integer C_S_AXI_HP0_ID_WIDTH = 6,
parameter integer C_S_AXI_HP1_ID_WIDTH = 6,
parameter integer C_S_AXI_HP2_ID_WIDTH = 6,
parameter integer C_S_AXI_HP3_ID_WIDTH = 6,
parameter integer C_S_AXI_ACP_ID_WIDTH = 3,
parameter integer C_S_AXI_HP0_DATA_WIDTH = 64,
parameter integer C_S_AXI_HP1_DATA_WIDTH = 64,
parameter integer C_S_AXI_HP2_DATA_WIDTH = 64,
parameter integer C_S_AXI_HP3_DATA_WIDTH = 64,
parameter integer C_INCLUDE_ACP_TRANS_CHECK = 0,
parameter integer C_NUM_F2P_INTR_INPUTS = 1,
parameter C_FCLK_CLK0_BUF = "TRUE",
parameter C_FCLK_CLK1_BUF = "TRUE",
parameter C_FCLK_CLK2_BUF = "TRUE",
parameter C_FCLK_CLK3_BUF = "TRUE",
parameter integer C_EMIO_GPIO_WIDTH = 64,
parameter integer C_INCLUDE_TRACE_BUFFER = 0,
parameter integer C_TRACE_BUFFER_FIFO_SIZE = 128,
parameter integer C_TRACE_BUFFER_CLOCK_DELAY = 12,
parameter integer USE_TRACE_DATA_EDGE_DETECTOR = 0,
parameter integer C_TRACE_PIPELINE_WIDTH = 8,
parameter C_PS7_SI_REV = "PRODUCTION",
parameter integer C_EN_EMIO_ENET0 = 0,
parameter integer C_EN_EMIO_ENET1 = 0,
parameter integer C_EN_EMIO_TRACE = 0,
parameter integer C_DQ_WIDTH = 32,
parameter integer C_DQS_WIDTH = 4,
parameter integer C_DM_WIDTH = 4,
parameter integer C_MIO_PRIMITIVE = 54,
parameter C_PACKAGE_NAME = "clg484",
parameter C_IRQ_F2P_MODE = "DIRECT",
parameter C_TRACE_INTERNAL_WIDTH = 32,
parameter integer C_EN_EMIO_PJTAG = 0,
// Enable and disable AFI Secure transaction
parameter C_USE_AXI_NONSECURE = 0,
//parameters for HP enable ports
parameter C_USE_S_AXI_HP0 = 0,
parameter C_USE_S_AXI_HP1 = 0,
parameter C_USE_S_AXI_HP2 = 0,
parameter C_USE_S_AXI_HP3 = 0,
//parameters for GP and ACP enable ports */
parameter C_USE_M_AXI_GP0 = 0,
parameter C_USE_M_AXI_GP1 = 0,
parameter C_USE_S_AXI_GP0 = 0,
parameter C_USE_S_AXI_GP1 = 0,
parameter C_USE_S_AXI_ACP = 0,
parameter C_GP0_EN_MODIFIABLE_TXN=0,
parameter C_GP1_EN_MODIFIABLE_TXN=0
)
(
//FMIO =========================================
//FMIO CAN0
output CAN0_PHY_TX,
input CAN0_PHY_RX,
//FMIO CAN1
output CAN1_PHY_TX,
input CAN1_PHY_RX,
//FMIO ENET0
output reg ENET0_GMII_TX_EN = 'b0,
output reg ENET0_GMII_TX_ER = 'b0,
output ENET0_MDIO_MDC,
output ENET0_MDIO_O,
output ENET0_MDIO_T,
output ENET0_PTP_DELAY_REQ_RX,
output ENET0_PTP_DELAY_REQ_TX,
output ENET0_PTP_PDELAY_REQ_RX,
output ENET0_PTP_PDELAY_REQ_TX,
output ENET0_PTP_PDELAY_RESP_RX,
output ENET0_PTP_PDELAY_RESP_TX,
output ENET0_PTP_SYNC_FRAME_RX,
output ENET0_PTP_SYNC_FRAME_TX,
output ENET0_SOF_RX,
output ENET0_SOF_TX,
output reg [7:0] ENET0_GMII_TXD,
input ENET0_GMII_COL,
input ENET0_GMII_CRS,
input ENET0_GMII_RX_CLK,
input ENET0_GMII_RX_DV,
input ENET0_GMII_RX_ER,
input ENET0_GMII_TX_CLK,
input ENET0_MDIO_I,
input ENET0_EXT_INTIN,
input [7:0] ENET0_GMII_RXD,
//FMIO ENET1
output reg ENET1_GMII_TX_EN = 'b0,
output reg ENET1_GMII_TX_ER = 'b0,
output ENET1_MDIO_MDC,
output ENET1_MDIO_O,
output ENET1_MDIO_T,
output ENET1_PTP_DELAY_REQ_RX,
output ENET1_PTP_DELAY_REQ_TX,
output ENET1_PTP_PDELAY_REQ_RX,
output ENET1_PTP_PDELAY_REQ_TX,
output ENET1_PTP_PDELAY_RESP_RX,
output ENET1_PTP_PDELAY_RESP_TX,
output ENET1_PTP_SYNC_FRAME_RX,
output ENET1_PTP_SYNC_FRAME_TX,
output ENET1_SOF_RX,
output ENET1_SOF_TX,
output reg [7:0] ENET1_GMII_TXD,
input ENET1_GMII_COL,
input ENET1_GMII_CRS,
input ENET1_GMII_RX_CLK,
input ENET1_GMII_RX_DV,
input ENET1_GMII_RX_ER,
input ENET1_GMII_TX_CLK,
input ENET1_MDIO_I,
input ENET1_EXT_INTIN,
input [7:0] ENET1_GMII_RXD,
//FMIO GPIO
input [(C_EMIO_GPIO_WIDTH-1):0] GPIO_I,
output [(C_EMIO_GPIO_WIDTH-1):0] GPIO_O,
output [(C_EMIO_GPIO_WIDTH-1):0] GPIO_T,
//FMIO I2C0
input I2C0_SDA_I,
output I2C0_SDA_O,
output I2C0_SDA_T,
input I2C0_SCL_I,
output I2C0_SCL_O,
output I2C0_SCL_T,
//FMIO I2C1
input I2C1_SDA_I,
output I2C1_SDA_O,
output I2C1_SDA_T,
input I2C1_SCL_I,
output I2C1_SCL_O,
output I2C1_SCL_T,
//FMIO PJTAG
input PJTAG_TCK,
input PJTAG_TMS,
input PJTAG_TDI,
output PJTAG_TDO,
//FMIO SDIO0
output SDIO0_CLK,
input SDIO0_CLK_FB,
output SDIO0_CMD_O,
input SDIO0_CMD_I,
output SDIO0_CMD_T,
input [3:0] SDIO0_DATA_I,
output [3:0] SDIO0_DATA_O,
output [3:0] SDIO0_DATA_T,
output SDIO0_LED,
input SDIO0_CDN,
input SDIO0_WP,
output SDIO0_BUSPOW,
output [2:0] SDIO0_BUSVOLT,
//FMIO SDIO1
output SDIO1_CLK,
input SDIO1_CLK_FB,
output SDIO1_CMD_O,
input SDIO1_CMD_I,
output SDIO1_CMD_T,
input [3:0] SDIO1_DATA_I,
output [3:0] SDIO1_DATA_O,
output [3:0] SDIO1_DATA_T,
output SDIO1_LED,
input SDIO1_CDN,
input SDIO1_WP,
output SDIO1_BUSPOW,
output [2:0] SDIO1_BUSVOLT,
//FMIO SPI0
input SPI0_SCLK_I,
output SPI0_SCLK_O,
output SPI0_SCLK_T,
input SPI0_MOSI_I,
output SPI0_MOSI_O,
output SPI0_MOSI_T,
input SPI0_MISO_I,
output SPI0_MISO_O,
output SPI0_MISO_T,
input SPI0_SS_I,
output SPI0_SS_O,
output SPI0_SS1_O,
output SPI0_SS2_O,
output SPI0_SS_T,
//FMIO SPI1
input SPI1_SCLK_I,
output SPI1_SCLK_O,
output SPI1_SCLK_T,
input SPI1_MOSI_I,
output SPI1_MOSI_O,
output SPI1_MOSI_T,
input SPI1_MISO_I,
output SPI1_MISO_O,
output SPI1_MISO_T,
input SPI1_SS_I,
output SPI1_SS_O,
output SPI1_SS1_O,
output SPI1_SS2_O,
output SPI1_SS_T,
//FMIO UART0
output UART0_DTRN,
output UART0_RTSN,
output UART0_TX,
input UART0_CTSN,
input UART0_DCDN,
input UART0_DSRN,
input UART0_RIN,
input UART0_RX,
//FMIO UART1
output UART1_DTRN,
output UART1_RTSN,
output UART1_TX,
input UART1_CTSN,
input UART1_DCDN,
input UART1_DSRN,
input UART1_RIN,
input UART1_RX,
//FMIO TTC0
output TTC0_WAVE0_OUT,
output TTC0_WAVE1_OUT,
output TTC0_WAVE2_OUT,
input TTC0_CLK0_IN,
input TTC0_CLK1_IN,
input TTC0_CLK2_IN,
//FMIO TTC1
output TTC1_WAVE0_OUT,
output TTC1_WAVE1_OUT,
output TTC1_WAVE2_OUT,
input TTC1_CLK0_IN,
input TTC1_CLK1_IN,
input TTC1_CLK2_IN,
//WDT
input WDT_CLK_IN,
output WDT_RST_OUT,
//FTPORT
input TRACE_CLK,
output TRACE_CTL,
output [(C_TRACE_INTERNAL_WIDTH)-1:0] TRACE_DATA,
output reg TRACE_CLK_OUT,
// USB
output [1:0] USB0_PORT_INDCTL,
output USB0_VBUS_PWRSELECT,
input USB0_VBUS_PWRFAULT,
output [1:0] USB1_PORT_INDCTL,
output USB1_VBUS_PWRSELECT,
input USB1_VBUS_PWRFAULT,
input SRAM_INTIN,
//AIO ===================================================
//M_AXI_GP0
// -- Output
output M_AXI_GP0_ARESETN,
output M_AXI_GP0_ARVALID,
output M_AXI_GP0_AWVALID,
output M_AXI_GP0_BREADY,
output M_AXI_GP0_RREADY,
output M_AXI_GP0_WLAST,
output M_AXI_GP0_WVALID,
output [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_ARID,
output [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_AWID,
output [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_WID,
output [1:0] M_AXI_GP0_ARBURST,
output [1:0] M_AXI_GP0_ARLOCK,
output [2:0] M_AXI_GP0_ARSIZE,
output [1:0] M_AXI_GP0_AWBURST,
output [1:0] M_AXI_GP0_AWLOCK,
output [2:0] M_AXI_GP0_AWSIZE,
output [2:0] M_AXI_GP0_ARPROT,
output [2:0] M_AXI_GP0_AWPROT,
output [31:0] M_AXI_GP0_ARADDR,
output [31:0] M_AXI_GP0_AWADDR,
output [31:0] M_AXI_GP0_WDATA,
output [3:0] M_AXI_GP0_ARCACHE,
output [3:0] M_AXI_GP0_ARLEN,
output [3:0] M_AXI_GP0_ARQOS,
output [3:0] M_AXI_GP0_AWCACHE,
output [3:0] M_AXI_GP0_AWLEN,
output [3:0] M_AXI_GP0_AWQOS,
output [3:0] M_AXI_GP0_WSTRB,
// -- Input
input M_AXI_GP0_ACLK,
input M_AXI_GP0_ARREADY,
input M_AXI_GP0_AWREADY,
input M_AXI_GP0_BVALID,
input M_AXI_GP0_RLAST,
input M_AXI_GP0_RVALID,
input M_AXI_GP0_WREADY,
input [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_BID,
input [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_RID,
input [1:0] M_AXI_GP0_BRESP,
input [1:0] M_AXI_GP0_RRESP,
input [31:0] M_AXI_GP0_RDATA,
//M_AXI_GP1
// -- Output
output M_AXI_GP1_ARESETN,
output M_AXI_GP1_ARVALID,
output M_AXI_GP1_AWVALID,
output M_AXI_GP1_BREADY,
output M_AXI_GP1_RREADY,
output M_AXI_GP1_WLAST,
output M_AXI_GP1_WVALID,
output [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_ARID,
output [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_AWID,
output [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_WID,
output [1:0] M_AXI_GP1_ARBURST,
output [1:0] M_AXI_GP1_ARLOCK,
output [2:0] M_AXI_GP1_ARSIZE,
output [1:0] M_AXI_GP1_AWBURST,
output [1:0] M_AXI_GP1_AWLOCK,
output [2:0] M_AXI_GP1_AWSIZE,
output [2:0] M_AXI_GP1_ARPROT,
output [2:0] M_AXI_GP1_AWPROT,
output [31:0] M_AXI_GP1_ARADDR,
output [31:0] M_AXI_GP1_AWADDR,
output [31:0] M_AXI_GP1_WDATA,
output [3:0] M_AXI_GP1_ARCACHE,
output [3:0] M_AXI_GP1_ARLEN,
output [3:0] M_AXI_GP1_ARQOS,
output [3:0] M_AXI_GP1_AWCACHE,
output [3:0] M_AXI_GP1_AWLEN,
output [3:0] M_AXI_GP1_AWQOS,
output [3:0] M_AXI_GP1_WSTRB,
// -- Input
input M_AXI_GP1_ACLK,
input M_AXI_GP1_ARREADY,
input M_AXI_GP1_AWREADY,
input M_AXI_GP1_BVALID,
input M_AXI_GP1_RLAST,
input M_AXI_GP1_RVALID,
input M_AXI_GP1_WREADY,
input [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_BID,
input [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_RID,
input [1:0] M_AXI_GP1_BRESP,
input [1:0] M_AXI_GP1_RRESP,
input [31:0] M_AXI_GP1_RDATA,
// S_AXI_GP0
// -- Output
output S_AXI_GP0_ARESETN,
output S_AXI_GP0_ARREADY,
output S_AXI_GP0_AWREADY,
output S_AXI_GP0_BVALID,
output S_AXI_GP0_RLAST,
output S_AXI_GP0_RVALID,
output S_AXI_GP0_WREADY,
output [1:0] S_AXI_GP0_BRESP,
output [1:0] S_AXI_GP0_RRESP,
output [31:0] S_AXI_GP0_RDATA,
output [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_BID,
output [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_RID,
// -- Input
input S_AXI_GP0_ACLK,
input S_AXI_GP0_ARVALID,
input S_AXI_GP0_AWVALID,
input S_AXI_GP0_BREADY,
input S_AXI_GP0_RREADY,
input S_AXI_GP0_WLAST,
input S_AXI_GP0_WVALID,
input [1:0] S_AXI_GP0_ARBURST,
input [1:0] S_AXI_GP0_ARLOCK,
input [2:0] S_AXI_GP0_ARSIZE,
input [1:0] S_AXI_GP0_AWBURST,
input [1:0] S_AXI_GP0_AWLOCK,
input [2:0] S_AXI_GP0_AWSIZE,
input [2:0] S_AXI_GP0_ARPROT,
input [2:0] S_AXI_GP0_AWPROT,
input [31:0] S_AXI_GP0_ARADDR,
input [31:0] S_AXI_GP0_AWADDR,
input [31:0] S_AXI_GP0_WDATA,
input [3:0] S_AXI_GP0_ARCACHE,
input [3:0] S_AXI_GP0_ARLEN,
input [3:0] S_AXI_GP0_ARQOS,
input [3:0] S_AXI_GP0_AWCACHE,
input [3:0] S_AXI_GP0_AWLEN,
input [3:0] S_AXI_GP0_AWQOS,
input [3:0] S_AXI_GP0_WSTRB,
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_ARID,
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_AWID,
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_WID,
// S_AXI_GP1
// -- Output
output S_AXI_GP1_ARESETN,
output S_AXI_GP1_ARREADY,
output S_AXI_GP1_AWREADY,
output S_AXI_GP1_BVALID,
output S_AXI_GP1_RLAST,
output S_AXI_GP1_RVALID,
output S_AXI_GP1_WREADY,
output [1:0] S_AXI_GP1_BRESP,
output [1:0] S_AXI_GP1_RRESP,
output [31:0] S_AXI_GP1_RDATA,
output [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_BID,
output [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_RID,
// -- Input
input S_AXI_GP1_ACLK,
input S_AXI_GP1_ARVALID,
input S_AXI_GP1_AWVALID,
input S_AXI_GP1_BREADY,
input S_AXI_GP1_RREADY,
input S_AXI_GP1_WLAST,
input S_AXI_GP1_WVALID,
input [1:0] S_AXI_GP1_ARBURST,
input [1:0] S_AXI_GP1_ARLOCK,
input [2:0] S_AXI_GP1_ARSIZE,
input [1:0] S_AXI_GP1_AWBURST,
input [1:0] S_AXI_GP1_AWLOCK,
input [2:0] S_AXI_GP1_AWSIZE,
input [2:0] S_AXI_GP1_ARPROT,
input [2:0] S_AXI_GP1_AWPROT,
input [31:0] S_AXI_GP1_ARADDR,
input [31:0] S_AXI_GP1_AWADDR,
input [31:0] S_AXI_GP1_WDATA,
input [3:0] S_AXI_GP1_ARCACHE,
input [3:0] S_AXI_GP1_ARLEN,
input [3:0] S_AXI_GP1_ARQOS,
input [3:0] S_AXI_GP1_AWCACHE,
input [3:0] S_AXI_GP1_AWLEN,
input [3:0] S_AXI_GP1_AWQOS,
input [3:0] S_AXI_GP1_WSTRB,
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_ARID,
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_AWID,
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_WID,
//S_AXI_ACP
// -- Output
output S_AXI_ACP_ARESETN,
output S_AXI_ACP_ARREADY,
output S_AXI_ACP_AWREADY,
output S_AXI_ACP_BVALID,
output S_AXI_ACP_RLAST,
output S_AXI_ACP_RVALID,
output S_AXI_ACP_WREADY,
output [1:0] S_AXI_ACP_BRESP,
output [1:0] S_AXI_ACP_RRESP,
output [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_BID,
output [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_RID,
output [63:0] S_AXI_ACP_RDATA,
// -- Input
input S_AXI_ACP_ACLK,
input S_AXI_ACP_ARVALID,
input S_AXI_ACP_AWVALID,
input S_AXI_ACP_BREADY,
input S_AXI_ACP_RREADY,
input S_AXI_ACP_WLAST,
input S_AXI_ACP_WVALID,
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_ARID,
input [2:0] S_AXI_ACP_ARPROT,
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_AWID,
input [2:0] S_AXI_ACP_AWPROT,
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_WID,
input [31:0] S_AXI_ACP_ARADDR,
input [31:0] S_AXI_ACP_AWADDR,
input [3:0] S_AXI_ACP_ARCACHE,
input [3:0] S_AXI_ACP_ARLEN,
input [3:0] S_AXI_ACP_ARQOS,
input [3:0] S_AXI_ACP_AWCACHE,
input [3:0] S_AXI_ACP_AWLEN,
input [3:0] S_AXI_ACP_AWQOS,
input [1:0] S_AXI_ACP_ARBURST,
input [1:0] S_AXI_ACP_ARLOCK,
input [2:0] S_AXI_ACP_ARSIZE,
input [1:0] S_AXI_ACP_AWBURST,
input [1:0] S_AXI_ACP_AWLOCK,
input [2:0] S_AXI_ACP_AWSIZE,
input [4:0] S_AXI_ACP_ARUSER,
input [4:0] S_AXI_ACP_AWUSER,
input [63:0] S_AXI_ACP_WDATA,
input [7:0] S_AXI_ACP_WSTRB,
// S_AXI_HP_0
// -- Output
output S_AXI_HP0_ARESETN,
output S_AXI_HP0_ARREADY,
output S_AXI_HP0_AWREADY,
output S_AXI_HP0_BVALID,
output S_AXI_HP0_RLAST,
output S_AXI_HP0_RVALID,
output S_AXI_HP0_WREADY,
output [1:0] S_AXI_HP0_BRESP,
output [1:0] S_AXI_HP0_RRESP,
output [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_BID,
output [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_RID,
output [(C_S_AXI_HP0_DATA_WIDTH - 1) :0] S_AXI_HP0_RDATA,
output [7:0] S_AXI_HP0_RCOUNT,
output [7:0] S_AXI_HP0_WCOUNT,
output [2:0] S_AXI_HP0_RACOUNT,
output [5:0] S_AXI_HP0_WACOUNT,
// -- Input
input S_AXI_HP0_ACLK,
input S_AXI_HP0_ARVALID,
input S_AXI_HP0_AWVALID,
input S_AXI_HP0_BREADY,
input S_AXI_HP0_RDISSUECAP1_EN,
input S_AXI_HP0_RREADY,
input S_AXI_HP0_WLAST,
input S_AXI_HP0_WRISSUECAP1_EN,
input S_AXI_HP0_WVALID,
input [1:0] S_AXI_HP0_ARBURST,
input [1:0] S_AXI_HP0_ARLOCK,
input [2:0] S_AXI_HP0_ARSIZE,
input [1:0] S_AXI_HP0_AWBURST,
input [1:0] S_AXI_HP0_AWLOCK,
input [2:0] S_AXI_HP0_AWSIZE,
input [2:0] S_AXI_HP0_ARPROT,
input [2:0] S_AXI_HP0_AWPROT,
input [31:0] S_AXI_HP0_ARADDR,
input [31:0] S_AXI_HP0_AWADDR,
input [3:0] S_AXI_HP0_ARCACHE,
input [3:0] S_AXI_HP0_ARLEN,
input [3:0] S_AXI_HP0_ARQOS,
input [3:0] S_AXI_HP0_AWCACHE,
input [3:0] S_AXI_HP0_AWLEN,
input [3:0] S_AXI_HP0_AWQOS,
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_ARID,
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_AWID,
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_WID,
input [(C_S_AXI_HP0_DATA_WIDTH - 1) :0] S_AXI_HP0_WDATA,
input [((C_S_AXI_HP0_DATA_WIDTH/8)-1):0] S_AXI_HP0_WSTRB,
// S_AXI_HP1
// -- Output
output S_AXI_HP1_ARESETN,
output S_AXI_HP1_ARREADY,
output S_AXI_HP1_AWREADY,
output S_AXI_HP1_BVALID,
output S_AXI_HP1_RLAST,
output S_AXI_HP1_RVALID,
output S_AXI_HP1_WREADY,
output [1:0] S_AXI_HP1_BRESP,
output [1:0] S_AXI_HP1_RRESP,
output [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_BID,
output [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_RID,
output [(C_S_AXI_HP1_DATA_WIDTH - 1) :0] S_AXI_HP1_RDATA,
output [7:0] S_AXI_HP1_RCOUNT,
output [7:0] S_AXI_HP1_WCOUNT,
output [2:0] S_AXI_HP1_RACOUNT,
output [5:0] S_AXI_HP1_WACOUNT,
// -- Input
input S_AXI_HP1_ACLK,
input S_AXI_HP1_ARVALID,
input S_AXI_HP1_AWVALID,
input S_AXI_HP1_BREADY,
input S_AXI_HP1_RDISSUECAP1_EN,
input S_AXI_HP1_RREADY,
input S_AXI_HP1_WLAST,
input S_AXI_HP1_WRISSUECAP1_EN,
input S_AXI_HP1_WVALID,
input [1:0] S_AXI_HP1_ARBURST,
input [1:0] S_AXI_HP1_ARLOCK,
input [2:0] S_AXI_HP1_ARSIZE,
input [1:0] S_AXI_HP1_AWBURST,
input [1:0] S_AXI_HP1_AWLOCK,
input [2:0] S_AXI_HP1_AWSIZE,
input [2:0] S_AXI_HP1_ARPROT,
input [2:0] S_AXI_HP1_AWPROT,
input [31:0] S_AXI_HP1_ARADDR,
input [31:0] S_AXI_HP1_AWADDR,
input [3:0] S_AXI_HP1_ARCACHE,
input [3:0] S_AXI_HP1_ARLEN,
input [3:0] S_AXI_HP1_ARQOS,
input [3:0] S_AXI_HP1_AWCACHE,
input [3:0] S_AXI_HP1_AWLEN,
input [3:0] S_AXI_HP1_AWQOS,
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_ARID,
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_AWID,
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_WID,
input [(C_S_AXI_HP1_DATA_WIDTH - 1) :0] S_AXI_HP1_WDATA,
input [((C_S_AXI_HP1_DATA_WIDTH/8)-1):0] S_AXI_HP1_WSTRB,
// S_AXI_HP2
// -- Output
output S_AXI_HP2_ARESETN,
output S_AXI_HP2_ARREADY,
output S_AXI_HP2_AWREADY,
output S_AXI_HP2_BVALID,
output S_AXI_HP2_RLAST,
output S_AXI_HP2_RVALID,
output S_AXI_HP2_WREADY,
output [1:0] S_AXI_HP2_BRESP,
output [1:0] S_AXI_HP2_RRESP,
output [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_BID,
output [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_RID,
output [(C_S_AXI_HP2_DATA_WIDTH - 1) :0] S_AXI_HP2_RDATA,
output [7:0] S_AXI_HP2_RCOUNT,
output [7:0] S_AXI_HP2_WCOUNT,
output [2:0] S_AXI_HP2_RACOUNT,
output [5:0] S_AXI_HP2_WACOUNT,
// -- Input
input S_AXI_HP2_ACLK,
input S_AXI_HP2_ARVALID,
input S_AXI_HP2_AWVALID,
input S_AXI_HP2_BREADY,
input S_AXI_HP2_RDISSUECAP1_EN,
input S_AXI_HP2_RREADY,
input S_AXI_HP2_WLAST,
input S_AXI_HP2_WRISSUECAP1_EN,
input S_AXI_HP2_WVALID,
input [1:0] S_AXI_HP2_ARBURST,
input [1:0] S_AXI_HP2_ARLOCK,
input [2:0] S_AXI_HP2_ARSIZE,
input [1:0] S_AXI_HP2_AWBURST,
input [1:0] S_AXI_HP2_AWLOCK,
input [2:0] S_AXI_HP2_AWSIZE,
input [2:0] S_AXI_HP2_ARPROT,
input [2:0] S_AXI_HP2_AWPROT,
input [31:0] S_AXI_HP2_ARADDR,
input [31:0] S_AXI_HP2_AWADDR,
input [3:0] S_AXI_HP2_ARCACHE,
input [3:0] S_AXI_HP2_ARLEN,
input [3:0] S_AXI_HP2_ARQOS,
input [3:0] S_AXI_HP2_AWCACHE,
input [3:0] S_AXI_HP2_AWLEN,
input [3:0] S_AXI_HP2_AWQOS,
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_ARID,
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_AWID,
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_WID,
input [(C_S_AXI_HP2_DATA_WIDTH - 1) :0] S_AXI_HP2_WDATA,
input [((C_S_AXI_HP2_DATA_WIDTH/8)-1):0] S_AXI_HP2_WSTRB,
// S_AXI_HP_3
// -- Output
output S_AXI_HP3_ARESETN,
output S_AXI_HP3_ARREADY,
output S_AXI_HP3_AWREADY,
output S_AXI_HP3_BVALID,
output S_AXI_HP3_RLAST,
output S_AXI_HP3_RVALID,
output S_AXI_HP3_WREADY,
output [1:0] S_AXI_HP3_BRESP,
output [1:0] S_AXI_HP3_RRESP,
output [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_BID,
output [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_RID,
output [(C_S_AXI_HP3_DATA_WIDTH - 1) :0] S_AXI_HP3_RDATA,
output [7:0] S_AXI_HP3_RCOUNT,
output [7:0] S_AXI_HP3_WCOUNT,
output [2:0] S_AXI_HP3_RACOUNT,
output [5:0] S_AXI_HP3_WACOUNT,
// -- Input
input S_AXI_HP3_ACLK,
input S_AXI_HP3_ARVALID,
input S_AXI_HP3_AWVALID,
input S_AXI_HP3_BREADY,
input S_AXI_HP3_RDISSUECAP1_EN,
input S_AXI_HP3_RREADY,
input S_AXI_HP3_WLAST,
input S_AXI_HP3_WRISSUECAP1_EN,
input S_AXI_HP3_WVALID,
input [1:0] S_AXI_HP3_ARBURST,
input [1:0] S_AXI_HP3_ARLOCK,
input [2:0] S_AXI_HP3_ARSIZE,
input [1:0] S_AXI_HP3_AWBURST,
input [1:0] S_AXI_HP3_AWLOCK,
input [2:0] S_AXI_HP3_AWSIZE,
input [2:0] S_AXI_HP3_ARPROT,
input [2:0] S_AXI_HP3_AWPROT,
input [31:0] S_AXI_HP3_ARADDR,
input [31:0] S_AXI_HP3_AWADDR,
input [3:0] S_AXI_HP3_ARCACHE,
input [3:0] S_AXI_HP3_ARLEN,
input [3:0] S_AXI_HP3_ARQOS,
input [3:0] S_AXI_HP3_AWCACHE,
input [3:0] S_AXI_HP3_AWLEN,
input [3:0] S_AXI_HP3_AWQOS,
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_ARID,
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_AWID,
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_WID,
input [(C_S_AXI_HP3_DATA_WIDTH - 1) :0] S_AXI_HP3_WDATA,
input [((C_S_AXI_HP3_DATA_WIDTH/8)-1):0] S_AXI_HP3_WSTRB,
//FIO ========================================
//IRQ
//output [28:0] IRQ_P2F,
output IRQ_P2F_DMAC_ABORT ,
output IRQ_P2F_DMAC0,
output IRQ_P2F_DMAC1,
output IRQ_P2F_DMAC2,
output IRQ_P2F_DMAC3,
output IRQ_P2F_DMAC4,
output IRQ_P2F_DMAC5,
output IRQ_P2F_DMAC6,
output IRQ_P2F_DMAC7,
output IRQ_P2F_SMC,
output IRQ_P2F_QSPI,
output IRQ_P2F_CTI,
output IRQ_P2F_GPIO,
output IRQ_P2F_USB0,
output IRQ_P2F_ENET0,
output IRQ_P2F_ENET_WAKE0,
output IRQ_P2F_SDIO0,
output IRQ_P2F_I2C0,
output IRQ_P2F_SPI0,
output IRQ_P2F_UART0,
output IRQ_P2F_CAN0,
output IRQ_P2F_USB1,
output IRQ_P2F_ENET1,
output IRQ_P2F_ENET_WAKE1,
output IRQ_P2F_SDIO1,
output IRQ_P2F_I2C1,
output IRQ_P2F_SPI1,
output IRQ_P2F_UART1,
output IRQ_P2F_CAN1,
input [(C_NUM_F2P_INTR_INPUTS-1):0] IRQ_F2P,
input Core0_nFIQ,
input Core0_nIRQ,
input Core1_nFIQ,
input Core1_nIRQ,
//DMA
output [1:0] DMA0_DATYPE,
output DMA0_DAVALID,
output DMA0_DRREADY,
output DMA0_RSTN,
output [1:0] DMA1_DATYPE,
output DMA1_DAVALID,
output DMA1_DRREADY,
output DMA1_RSTN,
output [1:0] DMA2_DATYPE,
output DMA2_DAVALID,
output DMA2_DRREADY,
output DMA2_RSTN,
output [1:0] DMA3_DATYPE,
output DMA3_DAVALID,
output DMA3_DRREADY,
output DMA3_RSTN,
input DMA0_ACLK,
input DMA0_DAREADY,
input DMA0_DRLAST,
input DMA0_DRVALID,
input DMA1_ACLK,
input DMA1_DAREADY,
input DMA1_DRLAST,
input DMA1_DRVALID,
input DMA2_ACLK,
input DMA2_DAREADY,
input DMA2_DRLAST,
input DMA2_DRVALID,
input DMA3_ACLK,
input DMA3_DAREADY,
input DMA3_DRLAST,
input DMA3_DRVALID,
input [1:0] DMA0_DRTYPE,
input [1:0] DMA1_DRTYPE,
input [1:0] DMA2_DRTYPE,
input [1:0] DMA3_DRTYPE,
//FCLK
output FCLK_CLK3,
output FCLK_CLK2,
output FCLK_CLK1,
output FCLK_CLK0,
input FCLK_CLKTRIG3_N,
input FCLK_CLKTRIG2_N,
input FCLK_CLKTRIG1_N,
input FCLK_CLKTRIG0_N,
output FCLK_RESET3_N,
output FCLK_RESET2_N,
output FCLK_RESET1_N,
output FCLK_RESET0_N,
//FTMD
input [31:0] FTMD_TRACEIN_DATA,
input FTMD_TRACEIN_VALID,
input FTMD_TRACEIN_CLK,
input [3:0] FTMD_TRACEIN_ATID,
//FTMT
input FTMT_F2P_TRIG_0,
output FTMT_F2P_TRIGACK_0,
input FTMT_F2P_TRIG_1,
output FTMT_F2P_TRIGACK_1,
input FTMT_F2P_TRIG_2,
output FTMT_F2P_TRIGACK_2,
input FTMT_F2P_TRIG_3,
output FTMT_F2P_TRIGACK_3,
input [31:0] FTMT_F2P_DEBUG,
input FTMT_P2F_TRIGACK_0,
output FTMT_P2F_TRIG_0,
input FTMT_P2F_TRIGACK_1,
output FTMT_P2F_TRIG_1,
input FTMT_P2F_TRIGACK_2,
output FTMT_P2F_TRIG_2,
input FTMT_P2F_TRIGACK_3,
output FTMT_P2F_TRIG_3,
output [31:0] FTMT_P2F_DEBUG,
//FIDLE
input FPGA_IDLE_N,
//EVENT
output EVENT_EVENTO,
output [1:0] EVENT_STANDBYWFE,
output [1:0] EVENT_STANDBYWFI,
input EVENT_EVENTI,
//DARB
input [3:0] DDR_ARB,
inout [C_MIO_PRIMITIVE - 1:0] MIO,
//DDR
inout DDR_CAS_n, // CASB
inout DDR_CKE, // CKE
inout DDR_Clk_n, // CKN
inout DDR_Clk, // CKP
inout DDR_CS_n, // CSB
inout DDR_DRSTB, // DDR_DRSTB
inout DDR_ODT, // ODT
inout DDR_RAS_n, // RASB
inout DDR_WEB,
inout [2:0] DDR_BankAddr, // BA
inout [14:0] DDR_Addr, // A
inout DDR_VRN,
inout DDR_VRP,
inout [C_DM_WIDTH - 1:0] DDR_DM, // DM
inout [C_DQ_WIDTH - 1:0] DDR_DQ, // DQ
inout [C_DQS_WIDTH -1:0] DDR_DQS_n, // DQSN
inout [C_DQS_WIDTH - 1:0] DDR_DQS, // DQSP
inout PS_SRSTB, // SRSTB
inout PS_CLK, // CLK
inout PS_PORB // PORB
);
wire [11:0] M_AXI_GP0_AWID_FULL;
wire [11:0] M_AXI_GP0_WID_FULL;
wire [11:0] M_AXI_GP0_ARID_FULL;
wire [11:0] M_AXI_GP0_BID_FULL;
wire [11:0] M_AXI_GP0_RID_FULL;
wire [11:0] M_AXI_GP1_AWID_FULL;
wire [11:0] M_AXI_GP1_WID_FULL;
wire [11:0] M_AXI_GP1_ARID_FULL;
wire [11:0] M_AXI_GP1_BID_FULL;
wire [11:0] M_AXI_GP1_RID_FULL;
wire [3:0] M_AXI_GP0_ARCACHE_t;
wire [3:0] M_AXI_GP1_ARCACHE_t;
wire [3:0] M_AXI_GP0_AWCACHE_t;
wire [3:0] M_AXI_GP1_AWCACHE_t;
// Wires for connecting to the PS7
wire ENET0_GMII_TX_EN_i;
wire ENET0_GMII_TX_ER_i;
reg ENET0_GMII_COL_i;
reg ENET0_GMII_CRS_i;
reg ENET0_GMII_RX_DV_i;
reg ENET0_GMII_RX_ER_i;
reg [7:0] ENET0_GMII_RXD_i;
wire [7:0] ENET0_GMII_TXD_i;
wire ENET1_GMII_TX_EN_i;
wire ENET1_GMII_TX_ER_i;
reg ENET1_GMII_COL_i;
reg ENET1_GMII_CRS_i;
reg ENET1_GMII_RX_DV_i;
reg ENET1_GMII_RX_ER_i;
reg [7:0] ENET1_GMII_RXD_i;
wire [7:0] ENET1_GMII_TXD_i;
reg [31:0] FTMD_TRACEIN_DATA_notracebuf;
reg FTMD_TRACEIN_VALID_notracebuf;
reg [3:0] FTMD_TRACEIN_ATID_notracebuf;
wire [31:0] FTMD_TRACEIN_DATA_i;
wire FTMD_TRACEIN_VALID_i;
wire [3:0] FTMD_TRACEIN_ATID_i;
wire [31:0] FTMD_TRACEIN_DATA_tracebuf;
wire FTMD_TRACEIN_VALID_tracebuf;
wire [3:0] FTMD_TRACEIN_ATID_tracebuf;
wire [5:0] S_AXI_GP0_BID_out;
wire [5:0] S_AXI_GP0_RID_out;
wire [5:0] S_AXI_GP0_ARID_in;
wire [5:0] S_AXI_GP0_AWID_in;
wire [5:0] S_AXI_GP0_WID_in;
wire [5:0] S_AXI_GP1_BID_out;
wire [5:0] S_AXI_GP1_RID_out;
wire [5:0] S_AXI_GP1_ARID_in;
wire [5:0] S_AXI_GP1_AWID_in;
wire [5:0] S_AXI_GP1_WID_in;
wire [5:0] S_AXI_HP0_BID_out;
wire [5:0] S_AXI_HP0_RID_out;
wire [5:0] S_AXI_HP0_ARID_in;
wire [5:0] S_AXI_HP0_AWID_in;
wire [5:0] S_AXI_HP0_WID_in;
wire [5:0] S_AXI_HP1_BID_out;
wire [5:0] S_AXI_HP1_RID_out;
wire [5:0] S_AXI_HP1_ARID_in;
wire [5:0] S_AXI_HP1_AWID_in;
wire [5:0] S_AXI_HP1_WID_in;
wire [5:0] S_AXI_HP2_BID_out;
wire [5:0] S_AXI_HP2_RID_out;
wire [5:0] S_AXI_HP2_ARID_in;
wire [5:0] S_AXI_HP2_AWID_in;
wire [5:0] S_AXI_HP2_WID_in;
wire [5:0] S_AXI_HP3_BID_out;
wire [5:0] S_AXI_HP3_RID_out;
wire [5:0] S_AXI_HP3_ARID_in;
wire [5:0] S_AXI_HP3_AWID_in;
wire [5:0] S_AXI_HP3_WID_in;
wire [2:0] S_AXI_ACP_BID_out;
wire [2:0] S_AXI_ACP_RID_out;
wire [2:0] S_AXI_ACP_ARID_in;
wire [2:0] S_AXI_ACP_AWID_in;
wire [2:0] S_AXI_ACP_WID_in;
wire [63:0] S_AXI_HP0_WDATA_in;
wire [7:0] S_AXI_HP0_WSTRB_in;
wire [63:0] S_AXI_HP0_RDATA_out;
wire [63:0] S_AXI_HP1_WDATA_in;
wire [7:0] S_AXI_HP1_WSTRB_in;
wire [63:0] S_AXI_HP1_RDATA_out;
wire [63:0] S_AXI_HP2_WDATA_in;
wire [7:0] S_AXI_HP2_WSTRB_in;
wire [63:0] S_AXI_HP2_RDATA_out;
wire [63:0] S_AXI_HP3_WDATA_in;
wire [7:0] S_AXI_HP3_WSTRB_in;
wire [63:0] S_AXI_HP3_RDATA_out;
wire [1:0] M_AXI_GP0_ARSIZE_i;
wire [1:0] M_AXI_GP0_AWSIZE_i;
wire [1:0] M_AXI_GP1_ARSIZE_i;
wire [1:0] M_AXI_GP1_AWSIZE_i;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPBID_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPRID_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPARID_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPAWID_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPWID_W;
wire SAXIACPARREADY_W;
wire SAXIACPAWREADY_W;
wire SAXIACPBVALID_W;
wire SAXIACPRLAST_W;
wire SAXIACPRVALID_W;
wire SAXIACPWREADY_W;
wire [1:0] SAXIACPBRESP_W;
wire [1:0] SAXIACPRRESP_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_BID;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_RID;
wire [63:0] SAXIACPRDATA_W;
wire S_AXI_ATC_ARVALID;
wire S_AXI_ATC_AWVALID;
wire S_AXI_ATC_BREADY;
wire S_AXI_ATC_RREADY;
wire S_AXI_ATC_WLAST;
wire S_AXI_ATC_WVALID;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_ARID;
wire [2:0] S_AXI_ATC_ARPROT;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_AWID;
wire [2:0] S_AXI_ATC_AWPROT;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_WID;
wire [31:0] S_AXI_ATC_ARADDR;
wire [31:0] S_AXI_ATC_AWADDR;
wire [3:0] S_AXI_ATC_ARCACHE;
wire [3:0] S_AXI_ATC_ARLEN;
wire [3:0] S_AXI_ATC_ARQOS;
wire [3:0] S_AXI_ATC_AWCACHE;
wire [3:0] S_AXI_ATC_AWLEN;
wire [3:0] S_AXI_ATC_AWQOS;
wire [1:0] S_AXI_ATC_ARBURST;
wire [1:0] S_AXI_ATC_ARLOCK;
wire [2:0] S_AXI_ATC_ARSIZE;
wire [1:0] S_AXI_ATC_AWBURST;
wire [1:0] S_AXI_ATC_AWLOCK;
wire [2:0] S_AXI_ATC_AWSIZE;
wire [4:0] S_AXI_ATC_ARUSER;
wire [4:0] S_AXI_ATC_AWUSER;
wire [63:0] S_AXI_ATC_WDATA;
wire [7:0] S_AXI_ATC_WSTRB;
wire SAXIACPARVALID_W;
wire SAXIACPAWVALID_W;
wire SAXIACPBREADY_W;
wire SAXIACPRREADY_W;
wire SAXIACPWLAST_W;
wire SAXIACPWVALID_W;
wire [2:0] SAXIACPARPROT_W;
wire [2:0] SAXIACPAWPROT_W;
wire [31:0] SAXIACPARADDR_W;
wire [31:0] SAXIACPAWADDR_W;
wire [3:0] SAXIACPARCACHE_W;
wire [3:0] SAXIACPARLEN_W;
wire [3:0] SAXIACPARQOS_W;
wire [3:0] SAXIACPAWCACHE_W;
wire [3:0] SAXIACPAWLEN_W;
wire [3:0] SAXIACPAWQOS_W;
wire [1:0] SAXIACPARBURST_W;
wire [1:0] SAXIACPARLOCK_W;
wire [2:0] SAXIACPARSIZE_W;
wire [1:0] SAXIACPAWBURST_W;
wire [1:0] SAXIACPAWLOCK_W;
wire [2:0] SAXIACPAWSIZE_W;
wire [4:0] SAXIACPARUSER_W;
wire [4:0] SAXIACPAWUSER_W;
wire [63:0] SAXIACPWDATA_W;
wire [7:0] SAXIACPWSTRB_W;
// AxUSER signal update
wire [4:0] param_aruser;
wire [4:0] param_awuser;
// Added to address CR 651751
wire [3:0] fclk_clktrig_gnd = 4'h0;
wire [19:0] irq_f2p_i;
wire [15:0] irq_f2p_null = 16'h0000;
// EMIO I2C0
wire I2C0_SDA_T_n;
wire I2C0_SCL_T_n;
// EMIO I2C1
wire I2C1_SDA_T_n;
wire I2C1_SCL_T_n;
// EMIO SPI0
wire SPI0_SCLK_T_n;
wire SPI0_MOSI_T_n;
wire SPI0_MISO_T_n;
wire SPI0_SS_T_n;
// EMIO SPI1
wire SPI1_SCLK_T_n;
wire SPI1_MOSI_T_n;
wire SPI1_MISO_T_n;
wire SPI1_SS_T_n;
// EMIO GEM0
wire ENET0_MDIO_T_n;
// EMIO GEM1
wire ENET1_MDIO_T_n;
// EMIO GPIO
wire [(C_EMIO_GPIO_WIDTH-1):0] GPIO_T_n;
wire [63:0] gpio_out_t_n;
wire [63:0] gpio_out;
wire [63:0] gpio_in63_0;
//For Clock buffering
wire [3:0] FCLK_CLK_unbuffered;
wire [3:0] FCLK_CLK_buffered;
wire FCLK_CLK0_temp;
// EMIO PJTAG
wire PJTAG_TDO_O;
wire PJTAG_TDO_T;
wire PJTAG_TDO_T_n;
// EMIO SDIO0
wire SDIO0_CMD_T_n;
wire [3:0] SDIO0_DATA_T_n;
// EMIO SDIO1
wire SDIO1_CMD_T_n;
wire [3:0] SDIO1_DATA_T_n;
// buffered IO
wire [C_MIO_PRIMITIVE - 1:0] buffered_MIO;
wire buffered_DDR_WEB;
wire buffered_DDR_CAS_n;
wire buffered_DDR_CKE;
wire buffered_DDR_Clk_n;
wire buffered_DDR_Clk;
wire buffered_DDR_CS_n;
wire buffered_DDR_DRSTB;
wire buffered_DDR_ODT;
wire buffered_DDR_RAS_n;
wire [2:0] buffered_DDR_BankAddr;
wire [14:0] buffered_DDR_Addr;
wire buffered_DDR_VRN;
wire buffered_DDR_VRP;
wire [C_DM_WIDTH - 1:0] buffered_DDR_DM;
wire [C_DQ_WIDTH - 1:0] buffered_DDR_DQ;
wire [C_DQS_WIDTH -1:0] buffered_DDR_DQS_n;
wire [C_DQS_WIDTH - 1:0] buffered_DDR_DQS;
wire buffered_PS_SRSTB;
wire buffered_PS_CLK;
wire buffered_PS_PORB;
wire S_AXI_HP0_ACLK_temp;
wire S_AXI_HP1_ACLK_temp;
wire S_AXI_HP2_ACLK_temp;
wire S_AXI_HP3_ACLK_temp;
wire M_AXI_GP0_ACLK_temp;
wire M_AXI_GP1_ACLK_temp;
wire S_AXI_GP0_ACLK_temp;
wire S_AXI_GP1_ACLK_temp;
wire S_AXI_ACP_ACLK_temp;
wire [31:0] TRACE_DATA_i;
wire TRACE_CTL_i;
(* keep = "true" *) reg TRACE_CTL_PIPE [(C_TRACE_PIPELINE_WIDTH - 1):0];
(* keep = "true" *) reg [(C_TRACE_INTERNAL_WIDTH)-1:0] TRACE_DATA_PIPE [(C_TRACE_PIPELINE_WIDTH - 1):0];
// fixed CR #665394
integer j;
generate
if (C_EN_EMIO_TRACE == 1) begin
always @(posedge TRACE_CLK)
begin
TRACE_CTL_PIPE[C_TRACE_PIPELINE_WIDTH - 1] <= TRACE_CTL_i;
TRACE_DATA_PIPE[C_TRACE_PIPELINE_WIDTH - 1] <= TRACE_DATA_i[(C_TRACE_INTERNAL_WIDTH-1):0];
for (j=(C_TRACE_PIPELINE_WIDTH-1); j>0; j=j-1) begin
TRACE_CTL_PIPE[j-1] <= TRACE_CTL_PIPE[j];
TRACE_DATA_PIPE[j-1] <= TRACE_DATA_PIPE[j];
end
TRACE_CLK_OUT <= ~TRACE_CLK_OUT;
end
end
else
begin
always @*
begin
TRACE_CTL_PIPE[C_TRACE_PIPELINE_WIDTH - 1] <= 1'b0;
TRACE_DATA_PIPE[C_TRACE_PIPELINE_WIDTH - 1] <= 1'b0;
for (j=(C_TRACE_PIPELINE_WIDTH-1); j>0; j=j-1) begin
TRACE_CTL_PIPE[j-1] <= 1'b0;
TRACE_DATA_PIPE[j-1] <= 1'b0;
end
TRACE_CLK_OUT <= 1'b0;
end
end
endgenerate
assign TRACE_CTL = TRACE_CTL_PIPE[0];
assign TRACE_DATA = TRACE_DATA_PIPE[0];
//irq_p2f
// Updated IRQ_F2P logic to address CR 641523
generate
if(C_NUM_F2P_INTR_INPUTS == 0) begin : irq_f2p_select_null
assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,irq_f2p_null[15:0]};
end else if(C_NUM_F2P_INTR_INPUTS == 16) begin : irq_f2p_select_all
assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,IRQ_F2P[15:0]};
end else begin : irq_f2p_select
if (C_IRQ_F2P_MODE == "DIRECT") begin
assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,
irq_f2p_null[(15-C_NUM_F2P_INTR_INPUTS):0],
IRQ_F2P[(C_NUM_F2P_INTR_INPUTS-1):0]};
end else begin
assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,
IRQ_F2P[(C_NUM_F2P_INTR_INPUTS-1):0],
irq_f2p_null[(15-C_NUM_F2P_INTR_INPUTS):0]};
end
end
endgenerate
assign M_AXI_GP0_ARSIZE[2:0] = {1'b0, M_AXI_GP0_ARSIZE_i[1:0]};
assign M_AXI_GP0_AWSIZE[2:0] = {1'b0, M_AXI_GP0_AWSIZE_i[1:0]};
assign M_AXI_GP1_ARSIZE[2:0] = {1'b0, M_AXI_GP1_ARSIZE_i[1:0]};
assign M_AXI_GP1_AWSIZE[2:0] = {1'b0, M_AXI_GP1_AWSIZE_i[1:0]};
// Compress Function
// Modified as per CR 631955
//function [11:0] uncompress_id;
// input [5:0] id;
// begin
// case (id[5:0])
// // dmac0
// 6'd1 : uncompress_id = 12'b010000_1000_00 ;
// 6'd2 : uncompress_id = 12'b010000_0000_00 ;
// 6'd3 : uncompress_id = 12'b010000_0001_00 ;
// 6'd4 : uncompress_id = 12'b010000_0010_00 ;
// 6'd5 : uncompress_id = 12'b010000_0011_00 ;
// 6'd6 : uncompress_id = 12'b010000_0100_00 ;
// 6'd7 : uncompress_id = 12'b010000_0101_00 ;
// 6'd8 : uncompress_id = 12'b010000_0110_00 ;
// 6'd9 : uncompress_id = 12'b010000_0111_00 ;
// // ioum
// 6'd10 : uncompress_id = 12'b0100000_000_01 ;
// 6'd11 : uncompress_id = 12'b0100000_001_01 ;
// 6'd12 : uncompress_id = 12'b0100000_010_01 ;
// 6'd13 : uncompress_id = 12'b0100000_011_01 ;
// 6'd14 : uncompress_id = 12'b0100000_100_01 ;
// 6'd15 : uncompress_id = 12'b0100000_101_01 ;
// // devci
// 6'd16 : uncompress_id = 12'b1000_0000_0000 ;
// // dap
// 6'd17 : uncompress_id = 12'b1000_0000_0001 ;
// // l2m1 (CPU000)
// 6'd18 : uncompress_id = 12'b11_000_000_00_00 ;
// 6'd19 : uncompress_id = 12'b11_010_000_00_00 ;
// 6'd20 : uncompress_id = 12'b11_011_000_00_00 ;
// 6'd21 : uncompress_id = 12'b11_100_000_00_00 ;
// 6'd22 : uncompress_id = 12'b11_101_000_00_00 ;
// 6'd23 : uncompress_id = 12'b11_110_000_00_00 ;
// 6'd24 : uncompress_id = 12'b11_111_000_00_00 ;
// // l2m1 (CPU001)
// 6'd25 : uncompress_id = 12'b11_000_001_00_00 ;
// 6'd26 : uncompress_id = 12'b11_010_001_00_00 ;
// 6'd27 : uncompress_id = 12'b11_011_001_00_00 ;
// 6'd28 : uncompress_id = 12'b11_100_001_00_00 ;
// 6'd29 : uncompress_id = 12'b11_101_001_00_00 ;
// 6'd30 : uncompress_id = 12'b11_110_001_00_00 ;
// 6'd31 : uncompress_id = 12'b11_111_001_00_00 ;
// // l2m1 (L2CC)
// 6'd32 : uncompress_id = 12'b11_000_00101_00 ;
// 6'd33 : uncompress_id = 12'b11_000_01001_00 ;
// 6'd34 : uncompress_id = 12'b11_000_01101_00 ;
// 6'd35 : uncompress_id = 12'b11_000_10011_00 ;
// 6'd36 : uncompress_id = 12'b11_000_10111_00 ;
// 6'd37 : uncompress_id = 12'b11_000_11011_00 ;
// 6'd38 : uncompress_id = 12'b11_000_11111_00 ;
// 6'd39 : uncompress_id = 12'b11_000_00011_00 ;
// 6'd40 : uncompress_id = 12'b11_000_00111_00 ;
// 6'd41 : uncompress_id = 12'b11_000_01011_00 ;
// 6'd42 : uncompress_id = 12'b11_000_01111_00 ;
// 6'd43 : uncompress_id = 12'b11_000_00001_00 ;
// // l2m1 (ACP)
// 6'd44 : uncompress_id = 12'b11_000_10000_00 ;
// 6'd45 : uncompress_id = 12'b11_001_10000_00 ;
// 6'd46 : uncompress_id = 12'b11_010_10000_00 ;
// 6'd47 : uncompress_id = 12'b11_011_10000_00 ;
// 6'd48 : uncompress_id = 12'b11_100_10000_00 ;
// 6'd49 : uncompress_id = 12'b11_101_10000_00 ;
// 6'd50 : uncompress_id = 12'b11_110_10000_00 ;
// 6'd51 : uncompress_id = 12'b11_111_10000_00 ;
// default : uncompress_id = ~0;
// endcase
// end
//endfunction
//
//function [5:0] compress_id;
// input [11:0] id;
// begin
// case (id[11:0])
// // dmac0
// 12'b010000_1000_00 : compress_id = 'd1 ;
// 12'b010000_0000_00 : compress_id = 'd2 ;
// 12'b010000_0001_00 : compress_id = 'd3 ;
// 12'b010000_0010_00 : compress_id = 'd4 ;
// 12'b010000_0011_00 : compress_id = 'd5 ;
// 12'b010000_0100_00 : compress_id = 'd6 ;
// 12'b010000_0101_00 : compress_id = 'd7 ;
// 12'b010000_0110_00 : compress_id = 'd8 ;
// 12'b010000_0111_00 : compress_id = 'd9 ;
// // ioum
// 12'b0100000_000_01 : compress_id = 'd10 ;
// 12'b0100000_001_01 : compress_id = 'd11 ;
// 12'b0100000_010_01 : compress_id = 'd12 ;
// 12'b0100000_011_01 : compress_id = 'd13 ;
// 12'b0100000_100_01 : compress_id = 'd14 ;
// 12'b0100000_101_01 : compress_id = 'd15 ;
// // devci
// 12'b1000_0000_0000 : compress_id = 'd16 ;
// // dap
// 12'b1000_0000_0001 : compress_id = 'd17 ;
// // l2m1 (CPU000)
// 12'b11_000_000_00_00 : compress_id = 'd18 ;
// 12'b11_010_000_00_00 : compress_id = 'd19 ;
// 12'b11_011_000_00_00 : compress_id = 'd20 ;
// 12'b11_100_000_00_00 : compress_id = 'd21 ;
// 12'b11_101_000_00_00 : compress_id = 'd22 ;
// 12'b11_110_000_00_00 : compress_id = 'd23 ;
// 12'b11_111_000_00_00 : compress_id = 'd24 ;
// // l2m1 (CPU001)
// 12'b11_000_001_00_00 : compress_id = 'd25 ;
// 12'b11_010_001_00_00 : compress_id = 'd26 ;
// 12'b11_011_001_00_00 : compress_id = 'd27 ;
// 12'b11_100_001_00_00 : compress_id = 'd28 ;
// 12'b11_101_001_00_00 : compress_id = 'd29 ;
// 12'b11_110_001_00_00 : compress_id = 'd30 ;
// 12'b11_111_001_00_00 : compress_id = 'd31 ;
// // l2m1 (L2CC)
// 12'b11_000_00101_00 : compress_id = 'd32 ;
// 12'b11_000_01001_00 : compress_id = 'd33 ;
// 12'b11_000_01101_00 : compress_id = 'd34 ;
// 12'b11_000_10011_00 : compress_id = 'd35 ;
// 12'b11_000_10111_00 : compress_id = 'd36 ;
// 12'b11_000_11011_00 : compress_id = 'd37 ;
// 12'b11_000_11111_00 : compress_id = 'd38 ;
// 12'b11_000_00011_00 : compress_id = 'd39 ;
// 12'b11_000_00111_00 : compress_id = 'd40 ;
// 12'b11_000_01011_00 : compress_id = 'd41 ;
// 12'b11_000_01111_00 : compress_id = 'd42 ;
// 12'b11_000_00001_00 : compress_id = 'd43 ;
// // l2m1 (ACP)
// 12'b11_000_10000_00 : compress_id = 'd44 ;
// 12'b11_001_10000_00 : compress_id = 'd45 ;
// 12'b11_010_10000_00 : compress_id = 'd46 ;
// 12'b11_011_10000_00 : compress_id = 'd47 ;
// 12'b11_100_10000_00 : compress_id = 'd48 ;
// 12'b11_101_10000_00 : compress_id = 'd49 ;
// 12'b11_110_10000_00 : compress_id = 'd50 ;
// 12'b11_111_10000_00 : compress_id = 'd51 ;
// default: compress_id = ~0;
// endcase
// end
//endfunction
// Modified as per CR 648393
function [5:0] compress_id;
input [11:0] id;
begin
compress_id[0] = id[7] | (id[4] & id[2]) | (~id[11] & id[2]) | (id[11] & id[0]);
compress_id[1] = id[8] | id[5] | (~id[11] & id[3]);
compress_id[2] = id[9] | (id[6] & id[3] & id[2]) | (~id[11] & id[4]);
compress_id[3] = (id[11] & id[10] & id[4]) | (id[11] & id[10] & id[2]) | (~id[11] & id[10] & ~id[5] & ~id[0]);
compress_id[4] = (id[11] & id[3]) | (id[10] & id[0]) | (id[11] & id[10] & ~id[2] &~id[6]);
compress_id[5] = id[11] & id[10] & ~id[3];
end
endfunction
function [11:0] uncompress_id;
input [5:0] id;
begin
case (id[5:0])
// dmac0
6'b000_010 : uncompress_id = 12'b010000_1000_00 ;
6'b001_000 : uncompress_id = 12'b010000_0000_00 ;
6'b001_001 : uncompress_id = 12'b010000_0001_00 ;
6'b001_010 : uncompress_id = 12'b010000_0010_00 ;
6'b001_011 : uncompress_id = 12'b010000_0011_00 ;
6'b001_100 : uncompress_id = 12'b010000_0100_00 ;
6'b001_101 : uncompress_id = 12'b010000_0101_00 ;
6'b001_110 : uncompress_id = 12'b010000_0110_00 ;
6'b001_111 : uncompress_id = 12'b010000_0111_00 ;
// ioum
6'b010_000 : uncompress_id = 12'b0100000_000_01 ;
6'b010_001 : uncompress_id = 12'b0100000_001_01 ;
6'b010_010 : uncompress_id = 12'b0100000_010_01 ;
6'b010_011 : uncompress_id = 12'b0100000_011_01 ;
6'b010_100 : uncompress_id = 12'b0100000_100_01 ;
6'b010_101 : uncompress_id = 12'b0100000_101_01 ;
// devci
6'b000_000 : uncompress_id = 12'b1000_0000_0000 ;
// dap
6'b000_001 : uncompress_id = 12'b1000_0000_0001 ;
// l2m1 (CPU000)
6'b110_000 : uncompress_id = 12'b11_000_000_00_00 ;
6'b110_010 : uncompress_id = 12'b11_010_000_00_00 ;
6'b110_011 : uncompress_id = 12'b11_011_000_00_00 ;
6'b110_100 : uncompress_id = 12'b11_100_000_00_00 ;
6'b110_101 : uncompress_id = 12'b11_101_000_00_00 ;
6'b110_110 : uncompress_id = 12'b11_110_000_00_00 ;
6'b110_111 : uncompress_id = 12'b11_111_000_00_00 ;
// l2m1 (CPU001)
6'b111_000 : uncompress_id = 12'b11_000_001_00_00 ;
6'b111_010 : uncompress_id = 12'b11_010_001_00_00 ;
6'b111_011 : uncompress_id = 12'b11_011_001_00_00 ;
6'b111_100 : uncompress_id = 12'b11_100_001_00_00 ;
6'b111_101 : uncompress_id = 12'b11_101_001_00_00 ;
6'b111_110 : uncompress_id = 12'b11_110_001_00_00 ;
6'b111_111 : uncompress_id = 12'b11_111_001_00_00 ;
// l2m1 (L2CC)
6'b101_001 : uncompress_id = 12'b11_000_00101_00 ;
6'b101_010 : uncompress_id = 12'b11_000_01001_00 ;
6'b101_011 : uncompress_id = 12'b11_000_01101_00 ;
6'b011_100 : uncompress_id = 12'b11_000_10011_00 ;
6'b011_101 : uncompress_id = 12'b11_000_10111_00 ;
6'b011_110 : uncompress_id = 12'b11_000_11011_00 ;
6'b011_111 : uncompress_id = 12'b11_000_11111_00 ;
6'b011_000 : uncompress_id = 12'b11_000_00011_00 ;
6'b011_001 : uncompress_id = 12'b11_000_00111_00 ;
6'b011_010 : uncompress_id = 12'b11_000_01011_00 ;
6'b011_011 : uncompress_id = 12'b11_000_01111_00 ;
6'b101_000 : uncompress_id = 12'b11_000_00001_00 ;
// l2m1 (ACP)
6'b100_000 : uncompress_id = 12'b11_000_10000_00 ;
6'b100_001 : uncompress_id = 12'b11_001_10000_00 ;
6'b100_010 : uncompress_id = 12'b11_010_10000_00 ;
6'b100_011 : uncompress_id = 12'b11_011_10000_00 ;
6'b100_100 : uncompress_id = 12'b11_100_10000_00 ;
6'b100_101 : uncompress_id = 12'b11_101_10000_00 ;
6'b100_110 : uncompress_id = 12'b11_110_10000_00 ;
6'b100_111 : uncompress_id = 12'b11_111_10000_00 ;
default : uncompress_id = 12'hx ;
endcase
end
endfunction
// Static Remap logic Enablement and Disablement for C_M_AXI0 port
assign M_AXI_GP0_AWID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_AWID_FULL) : M_AXI_GP0_AWID_FULL;
assign M_AXI_GP0_WID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_WID_FULL) : M_AXI_GP0_WID_FULL;
assign M_AXI_GP0_ARID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_ARID_FULL) : M_AXI_GP0_ARID_FULL;
assign M_AXI_GP0_BID_FULL = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP0_BID) : M_AXI_GP0_BID;
assign M_AXI_GP0_RID_FULL = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP0_RID) : M_AXI_GP0_RID;
// Static Remap logic Enablement and Disablement for C_M_AXI1 port
assign M_AXI_GP1_AWID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_AWID_FULL) : M_AXI_GP1_AWID_FULL;
assign M_AXI_GP1_WID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_WID_FULL) : M_AXI_GP1_WID_FULL;
assign M_AXI_GP1_ARID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_ARID_FULL) : M_AXI_GP1_ARID_FULL;
assign M_AXI_GP1_BID_FULL = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP1_BID) : M_AXI_GP1_BID;
assign M_AXI_GP1_RID_FULL = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP1_RID) : M_AXI_GP1_RID;
//// Compress_id and uncompress_id has been removed to address CR 642527
//// AXI interconnect v1.05.a and beyond implements dynamic ID compression/decompression.
// assign M_AXI_GP0_AWID = M_AXI_GP0_AWID_FULL;
// assign M_AXI_GP0_WID = M_AXI_GP0_WID_FULL;
// assign M_AXI_GP0_ARID = M_AXI_GP0_ARID_FULL;
// assign M_AXI_GP0_BID_FULL = M_AXI_GP0_BID;
// assign M_AXI_GP0_RID_FULL = M_AXI_GP0_RID;
//
// assign M_AXI_GP1_AWID = M_AXI_GP1_AWID_FULL;
// assign M_AXI_GP1_WID = M_AXI_GP1_WID_FULL;
// assign M_AXI_GP1_ARID = M_AXI_GP1_ARID_FULL;
// assign M_AXI_GP1_BID_FULL = M_AXI_GP1_BID;
// assign M_AXI_GP1_RID_FULL = M_AXI_GP1_RID;
// Pipeline Stage for ENET0
generate
if (C_EN_EMIO_ENET0 == 1) begin
always @(posedge ENET0_GMII_TX_CLK)
begin
ENET0_GMII_TXD <= ENET0_GMII_TXD_i;
ENET0_GMII_TX_EN <= ENET0_GMII_TX_EN_i; //1'b0; //ENET0_GMII_TX_EN_i;
ENET0_GMII_TX_ER <= ENET0_GMII_TX_ER_i; //1'b0;//ENET0_GMII_TX_ER_i;
ENET0_GMII_COL_i <= ENET0_GMII_COL;
ENET0_GMII_CRS_i <= ENET0_GMII_CRS;
end
end
else
always@*
begin
ENET0_GMII_TXD <= 'b0;//ENET0_GMII_TXD_i;
ENET0_GMII_TX_EN <= 'b0;//ENET0_GMII_TX_EN_i; //1'b0; //ENET0_GMII_TX_EN_i;
ENET0_GMII_TX_ER <= 'b0;//ENET0_GMII_TX_ER_i; //1'b0;//ENET0_GMII_TX_ER_i;
ENET0_GMII_COL_i <= 'b0;
ENET0_GMII_CRS_i <= 'b0;
end
endgenerate
generate
if (C_EN_EMIO_ENET0 == 1) begin
always @(posedge ENET0_GMII_RX_CLK)
begin
ENET0_GMII_RXD_i <= ENET0_GMII_RXD;
ENET0_GMII_RX_DV_i <= ENET0_GMII_RX_DV;
ENET0_GMII_RX_ER_i <= ENET0_GMII_RX_ER;
end
end
else
begin
always @*
begin
ENET0_GMII_RXD_i <= 0;
ENET0_GMII_RX_DV_i <= 0;
ENET0_GMII_RX_ER_i <= 0;
end
end
endgenerate
// Pipeline Stage for ENET1
generate
if (C_EN_EMIO_ENET1 == 1) begin
always @(posedge ENET1_GMII_TX_CLK)
begin
ENET1_GMII_TXD <= ENET1_GMII_TXD_i;
ENET1_GMII_TX_EN <= ENET1_GMII_TX_EN_i;
ENET1_GMII_TX_ER <= ENET1_GMII_TX_ER_i;
ENET1_GMII_COL_i <= ENET1_GMII_COL;
ENET1_GMII_CRS_i <= ENET1_GMII_CRS;
end
end
else
begin
always@*
begin
ENET1_GMII_TXD <= 'b0;//ENET0_GMII_TXD_i;
ENET1_GMII_TX_EN <= 'b0;//ENET0_GMII_TX_EN_i; //1'b0; //ENET0_GMII_TX_EN_i;
ENET1_GMII_TX_ER <= 'b0;//ENET0_GMII_TX_ER_i; //1'b0;//ENET0_GMII_TX_ER_i;
ENET1_GMII_COL_i <= 0;
ENET1_GMII_CRS_i <= 0;
end
end
endgenerate
generate
if (C_EN_EMIO_ENET1 == 1) begin
always @(posedge ENET1_GMII_RX_CLK)
begin
ENET1_GMII_RXD_i <= ENET1_GMII_RXD;
ENET1_GMII_RX_DV_i <= ENET1_GMII_RX_DV;
ENET1_GMII_RX_ER_i <= ENET1_GMII_RX_ER;
end
end
else
begin
always @*
begin
ENET1_GMII_RXD_i <= 'b0;
ENET1_GMII_RX_DV_i <= 'b0;
ENET1_GMII_RX_ER_i <= 'b0;
end
end
endgenerate
// Trace buffer instantiated when C_INCLUDE_TRACE_BUFFER is 1.
generate
if (C_EN_EMIO_TRACE == 1) begin
if (C_INCLUDE_TRACE_BUFFER == 0) begin : gen_no_trace_buffer
// Pipeline Stage for Traceport ATID
always @(posedge FTMD_TRACEIN_CLK)
begin
FTMD_TRACEIN_DATA_notracebuf <= FTMD_TRACEIN_DATA;
FTMD_TRACEIN_VALID_notracebuf <= FTMD_TRACEIN_VALID;
FTMD_TRACEIN_ATID_notracebuf <= FTMD_TRACEIN_ATID;
end
assign FTMD_TRACEIN_DATA_i = FTMD_TRACEIN_DATA_notracebuf;
assign FTMD_TRACEIN_VALID_i = FTMD_TRACEIN_VALID_notracebuf;
assign FTMD_TRACEIN_ATID_i = FTMD_TRACEIN_ATID_notracebuf;
end else begin : gen_trace_buffer
processing_system7_v5_5_trace_buffer #(.FIFO_SIZE (C_TRACE_BUFFER_FIFO_SIZE),
.USE_TRACE_DATA_EDGE_DETECTOR(USE_TRACE_DATA_EDGE_DETECTOR),
.C_DELAY_CLKS(C_TRACE_BUFFER_CLOCK_DELAY)
)
trace_buffer_i (
.TRACE_CLK(FTMD_TRACEIN_CLK),
.RST(~FCLK_RESET0_N),
.TRACE_VALID_IN(FTMD_TRACEIN_VALID),
.TRACE_DATA_IN(FTMD_TRACEIN_DATA),
.TRACE_ATID_IN(FTMD_TRACEIN_ATID),
.TRACE_ATID_OUT(FTMD_TRACEIN_ATID_tracebuf),
.TRACE_VALID_OUT(FTMD_TRACEIN_VALID_tracebuf),
.TRACE_DATA_OUT(FTMD_TRACEIN_DATA_tracebuf)
);
assign FTMD_TRACEIN_DATA_i = FTMD_TRACEIN_DATA_tracebuf;
assign FTMD_TRACEIN_VALID_i = FTMD_TRACEIN_VALID_tracebuf;
assign FTMD_TRACEIN_ATID_i = FTMD_TRACEIN_ATID_tracebuf;
end
end
else
begin
assign FTMD_TRACEIN_DATA_i = 1'b0;
assign FTMD_TRACEIN_VALID_i = 1'b0;
assign FTMD_TRACEIN_ATID_i = 1'b0;
end
endgenerate
// ID Width Control on AXI Slave ports
// S_AXI_GP0
function [5:0] id_in_gp0;
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] axi_id_gp0_in;
begin
case (C_S_AXI_GP0_ID_WIDTH)
1: id_in_gp0 = {5'b0, axi_id_gp0_in};
2: id_in_gp0 = {4'b0, axi_id_gp0_in};
3: id_in_gp0 = {3'b0, axi_id_gp0_in};
4: id_in_gp0 = {2'b0, axi_id_gp0_in};
5: id_in_gp0 = {1'b0, axi_id_gp0_in};
6: id_in_gp0 = axi_id_gp0_in;
default : id_in_gp0 = axi_id_gp0_in;
endcase
end
endfunction
assign S_AXI_GP0_ARID_in = id_in_gp0(S_AXI_GP0_ARID);
assign S_AXI_GP0_AWID_in = id_in_gp0(S_AXI_GP0_AWID);
assign S_AXI_GP0_WID_in = id_in_gp0(S_AXI_GP0_WID);
function [5:0] id_out_gp0;
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] axi_id_gp0_out;
begin
case (C_S_AXI_GP0_ID_WIDTH)
1: id_out_gp0 = axi_id_gp0_out[0];
2: id_out_gp0 = axi_id_gp0_out[1:0];
3: id_out_gp0 = axi_id_gp0_out[2:0];
4: id_out_gp0 = axi_id_gp0_out[3:0];
5: id_out_gp0 = axi_id_gp0_out[4:0];
6: id_out_gp0 = axi_id_gp0_out;
default : id_out_gp0 = axi_id_gp0_out;
endcase
end
endfunction
assign S_AXI_GP0_BID = id_out_gp0(S_AXI_GP0_BID_out);
assign S_AXI_GP0_RID = id_out_gp0(S_AXI_GP0_RID_out);
// S_AXI_GP1
function [5:0] id_in_gp1;
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] axi_id_gp1_in;
begin
case (C_S_AXI_GP1_ID_WIDTH)
1: id_in_gp1 = {5'b0, axi_id_gp1_in};
2: id_in_gp1 = {4'b0, axi_id_gp1_in};
3: id_in_gp1 = {3'b0, axi_id_gp1_in};
4: id_in_gp1 = {2'b0, axi_id_gp1_in};
5: id_in_gp1 = {1'b0, axi_id_gp1_in};
6: id_in_gp1 = axi_id_gp1_in;
default : id_in_gp1 = axi_id_gp1_in;
endcase
end
endfunction
assign S_AXI_GP1_ARID_in = id_in_gp1(S_AXI_GP1_ARID);
assign S_AXI_GP1_AWID_in = id_in_gp1(S_AXI_GP1_AWID);
assign S_AXI_GP1_WID_in = id_in_gp1(S_AXI_GP1_WID);
function [5:0] id_out_gp1;
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] axi_id_gp1_out;
begin
case (C_S_AXI_GP1_ID_WIDTH)
1: id_out_gp1 = axi_id_gp1_out[0];
2: id_out_gp1 = axi_id_gp1_out[1:0];
3: id_out_gp1 = axi_id_gp1_out[2:0];
4: id_out_gp1 = axi_id_gp1_out[3:0];
5: id_out_gp1 = axi_id_gp1_out[4:0];
6: id_out_gp1 = axi_id_gp1_out;
default : id_out_gp1 = axi_id_gp1_out;
endcase
end
endfunction
assign S_AXI_GP1_BID = id_out_gp1(S_AXI_GP1_BID_out);
assign S_AXI_GP1_RID = id_out_gp1(S_AXI_GP1_RID_out);
// S_AXI_HP0
function [5:0] id_in_hp0;
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] axi_id_hp0_in;
begin
case (C_S_AXI_HP0_ID_WIDTH)
1: id_in_hp0 = {5'b0, axi_id_hp0_in};
2: id_in_hp0 = {4'b0, axi_id_hp0_in};
3: id_in_hp0 = {3'b0, axi_id_hp0_in};
4: id_in_hp0 = {2'b0, axi_id_hp0_in};
5: id_in_hp0 = {1'b0, axi_id_hp0_in};
6: id_in_hp0 = axi_id_hp0_in;
default : id_in_hp0 = axi_id_hp0_in;
endcase
end
endfunction
assign S_AXI_HP0_ARID_in = id_in_hp0(S_AXI_HP0_ARID);
assign S_AXI_HP0_AWID_in = id_in_hp0(S_AXI_HP0_AWID);
assign S_AXI_HP0_WID_in = id_in_hp0(S_AXI_HP0_WID);
function [5:0] id_out_hp0;
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] axi_id_hp0_out;
begin
case (C_S_AXI_HP0_ID_WIDTH)
1: id_out_hp0 = axi_id_hp0_out[0];
2: id_out_hp0 = axi_id_hp0_out[1:0];
3: id_out_hp0 = axi_id_hp0_out[2:0];
4: id_out_hp0 = axi_id_hp0_out[3:0];
5: id_out_hp0 = axi_id_hp0_out[4:0];
6: id_out_hp0 = axi_id_hp0_out;
default : id_out_hp0 = axi_id_hp0_out;
endcase
end
endfunction
assign S_AXI_HP0_BID = id_out_hp0(S_AXI_HP0_BID_out);
assign S_AXI_HP0_RID = id_out_hp0(S_AXI_HP0_RID_out);
assign S_AXI_HP0_WDATA_in = (C_S_AXI_HP0_DATA_WIDTH == 64) ? S_AXI_HP0_WDATA : {32'b0,S_AXI_HP0_WDATA};
assign S_AXI_HP0_WSTRB_in = (C_S_AXI_HP0_DATA_WIDTH == 64) ? S_AXI_HP0_WSTRB : {4'b0,S_AXI_HP0_WSTRB};
assign S_AXI_HP0_RDATA = (C_S_AXI_HP0_DATA_WIDTH == 64) ? S_AXI_HP0_RDATA_out : S_AXI_HP0_RDATA_out[31:0];
// S_AXI_HP1
function [5:0] id_in_hp1;
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] axi_id_hp1_in;
begin
case (C_S_AXI_HP1_ID_WIDTH)
1: id_in_hp1 = {5'b0, axi_id_hp1_in};
2: id_in_hp1 = {4'b0, axi_id_hp1_in};
3: id_in_hp1 = {3'b0, axi_id_hp1_in};
4: id_in_hp1 = {2'b0, axi_id_hp1_in};
5: id_in_hp1 = {1'b0, axi_id_hp1_in};
6: id_in_hp1 = axi_id_hp1_in;
default : id_in_hp1 = axi_id_hp1_in;
endcase
end
endfunction
assign S_AXI_HP1_ARID_in = id_in_hp1(S_AXI_HP1_ARID);
assign S_AXI_HP1_AWID_in = id_in_hp1(S_AXI_HP1_AWID);
assign S_AXI_HP1_WID_in = id_in_hp1(S_AXI_HP1_WID);
function [5:0] id_out_hp1;
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] axi_id_hp1_out;
begin
case (C_S_AXI_HP1_ID_WIDTH)
1: id_out_hp1 = axi_id_hp1_out[0];
2: id_out_hp1 = axi_id_hp1_out[1:0];
3: id_out_hp1 = axi_id_hp1_out[2:0];
4: id_out_hp1 = axi_id_hp1_out[3:0];
5: id_out_hp1 = axi_id_hp1_out[4:0];
6: id_out_hp1 = axi_id_hp1_out;
default : id_out_hp1 = axi_id_hp1_out;
endcase
end
endfunction
assign S_AXI_HP1_BID = id_out_hp1(S_AXI_HP1_BID_out);
assign S_AXI_HP1_RID = id_out_hp1(S_AXI_HP1_RID_out);
assign S_AXI_HP1_WDATA_in = (C_S_AXI_HP1_DATA_WIDTH == 64) ? S_AXI_HP1_WDATA : {32'b0,S_AXI_HP1_WDATA};
assign S_AXI_HP1_WSTRB_in = (C_S_AXI_HP1_DATA_WIDTH == 64) ? S_AXI_HP1_WSTRB : {4'b0,S_AXI_HP1_WSTRB};
assign S_AXI_HP1_RDATA = (C_S_AXI_HP1_DATA_WIDTH == 64) ? S_AXI_HP1_RDATA_out : S_AXI_HP1_RDATA_out[31:0];
// S_AXI_HP2
function [5:0] id_in_hp2;
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] axi_id_hp2_in;
begin
case (C_S_AXI_HP2_ID_WIDTH)
1: id_in_hp2 = {5'b0, axi_id_hp2_in};
2: id_in_hp2 = {4'b0, axi_id_hp2_in};
3: id_in_hp2 = {3'b0, axi_id_hp2_in};
4: id_in_hp2 = {2'b0, axi_id_hp2_in};
5: id_in_hp2 = {1'b0, axi_id_hp2_in};
6: id_in_hp2 = axi_id_hp2_in;
default : id_in_hp2 = axi_id_hp2_in;
endcase
end
endfunction
assign S_AXI_HP2_ARID_in = id_in_hp2(S_AXI_HP2_ARID);
assign S_AXI_HP2_AWID_in = id_in_hp2(S_AXI_HP2_AWID);
assign S_AXI_HP2_WID_in = id_in_hp2(S_AXI_HP2_WID);
function [5:0] id_out_hp2;
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] axi_id_hp2_out;
begin
case (C_S_AXI_HP2_ID_WIDTH)
1: id_out_hp2 = axi_id_hp2_out[0];
2: id_out_hp2 = axi_id_hp2_out[1:0];
3: id_out_hp2 = axi_id_hp2_out[2:0];
4: id_out_hp2 = axi_id_hp2_out[3:0];
5: id_out_hp2 = axi_id_hp2_out[4:0];
6: id_out_hp2 = axi_id_hp2_out;
default : id_out_hp2 = axi_id_hp2_out;
endcase
end
endfunction
assign S_AXI_HP2_BID = id_out_hp2(S_AXI_HP2_BID_out);
assign S_AXI_HP2_RID = id_out_hp2(S_AXI_HP2_RID_out);
assign S_AXI_HP2_WDATA_in = (C_S_AXI_HP2_DATA_WIDTH == 64) ? S_AXI_HP2_WDATA : {32'b0,S_AXI_HP2_WDATA};
assign S_AXI_HP2_WSTRB_in = (C_S_AXI_HP2_DATA_WIDTH == 64) ? S_AXI_HP2_WSTRB : {4'b0,S_AXI_HP2_WSTRB};
assign S_AXI_HP2_RDATA = (C_S_AXI_HP2_DATA_WIDTH == 64) ? S_AXI_HP2_RDATA_out : S_AXI_HP2_RDATA_out[31:0];
// S_AXI_HP3
function [5:0] id_in_hp3;
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] axi_id_hp3_in;
begin
case (C_S_AXI_HP3_ID_WIDTH)
1: id_in_hp3 = {5'b0, axi_id_hp3_in};
2: id_in_hp3 = {4'b0, axi_id_hp3_in};
3: id_in_hp3 = {3'b0, axi_id_hp3_in};
4: id_in_hp3 = {2'b0, axi_id_hp3_in};
5: id_in_hp3 = {1'b0, axi_id_hp3_in};
6: id_in_hp3 = axi_id_hp3_in;
default : id_in_hp3 = axi_id_hp3_in;
endcase
end
endfunction
assign S_AXI_HP3_ARID_in = id_in_hp3(S_AXI_HP3_ARID);
assign S_AXI_HP3_AWID_in = id_in_hp3(S_AXI_HP3_AWID);
assign S_AXI_HP3_WID_in = id_in_hp3(S_AXI_HP3_WID);
function [5:0] id_out_hp3;
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] axi_id_hp3_out;
begin
case (C_S_AXI_HP3_ID_WIDTH)
1: id_out_hp3 = axi_id_hp3_out[0];
2: id_out_hp3 = axi_id_hp3_out[1:0];
3: id_out_hp3 = axi_id_hp3_out[2:0];
4: id_out_hp3 = axi_id_hp3_out[3:0];
5: id_out_hp3 = axi_id_hp3_out[4:0];
6: id_out_hp3 = axi_id_hp3_out;
default : id_out_hp3 = axi_id_hp3_out;
endcase
end
endfunction
assign S_AXI_HP3_BID = id_out_hp3(S_AXI_HP3_BID_out);
assign S_AXI_HP3_RID = id_out_hp3(S_AXI_HP3_RID_out);
assign S_AXI_HP3_WDATA_in = (C_S_AXI_HP3_DATA_WIDTH == 64) ? S_AXI_HP3_WDATA : {32'b0,S_AXI_HP3_WDATA};
assign S_AXI_HP3_WSTRB_in = (C_S_AXI_HP3_DATA_WIDTH == 64) ? S_AXI_HP3_WSTRB : {4'b0,S_AXI_HP3_WSTRB};
assign S_AXI_HP3_RDATA = (C_S_AXI_HP3_DATA_WIDTH == 64) ? S_AXI_HP3_RDATA_out : S_AXI_HP3_RDATA_out[31:0];
// S_AXI_ACP
function [2:0] id_in_acp;
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] axi_id_acp_in;
begin
case (C_S_AXI_ACP_ID_WIDTH)
1: id_in_acp = {2'b0, axi_id_acp_in};
2: id_in_acp = {1'b0, axi_id_acp_in};
3: id_in_acp = axi_id_acp_in;
default : id_in_acp = axi_id_acp_in;
endcase
end
endfunction
assign S_AXI_ACP_ARID_in = id_in_acp(SAXIACPARID_W);
assign S_AXI_ACP_AWID_in = id_in_acp(SAXIACPAWID_W);
assign S_AXI_ACP_WID_in = id_in_acp(SAXIACPWID_W);
function [2:0] id_out_acp;
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] axi_id_acp_out;
begin
case (C_S_AXI_ACP_ID_WIDTH)
1: id_out_acp = axi_id_acp_out[0];
2: id_out_acp = axi_id_acp_out[1:0];
3: id_out_acp = axi_id_acp_out;
default : id_out_acp = axi_id_acp_out;
endcase
end
endfunction
assign SAXIACPBID_W = id_out_acp(S_AXI_ACP_BID_out);
assign SAXIACPRID_W = id_out_acp(S_AXI_ACP_RID_out);
// FMIO Tristate Inversion logic
//FMIO I2C0
assign I2C0_SDA_T = ~ I2C0_SDA_T_n;
assign I2C0_SCL_T = ~ I2C0_SCL_T_n;
//FMIO I2C1
assign I2C1_SDA_T = ~ I2C1_SDA_T_n;
assign I2C1_SCL_T = ~ I2C1_SCL_T_n;
//FMIO SPI0
assign SPI0_SCLK_T = ~ SPI0_SCLK_T_n;
assign SPI0_MOSI_T = ~ SPI0_MOSI_T_n;
assign SPI0_MISO_T = ~ SPI0_MISO_T_n;
assign SPI0_SS_T = ~ SPI0_SS_T_n;
//FMIO SPI1
assign SPI1_SCLK_T = ~ SPI1_SCLK_T_n;
assign SPI1_MOSI_T = ~ SPI1_MOSI_T_n;
assign SPI1_MISO_T = ~ SPI1_MISO_T_n;
assign SPI1_SS_T = ~ SPI1_SS_T_n;
// EMIO GEM0 MDIO
assign ENET0_MDIO_T = ~ ENET0_MDIO_T_n;
// EMIO GEM1 MDIO
assign ENET1_MDIO_T = ~ ENET1_MDIO_T_n;
// EMIO GPIO
assign GPIO_T = ~ GPIO_T_n;
// EMIO GPIO Width Control
function [63:0] gpio_width_adjust_in;
input [(C_EMIO_GPIO_WIDTH - 1) : 0] gpio_in;
begin
case (C_EMIO_GPIO_WIDTH)
1: gpio_width_adjust_in = {63'b0, gpio_in};
2: gpio_width_adjust_in = {62'b0, gpio_in};
3: gpio_width_adjust_in = {61'b0, gpio_in};
4: gpio_width_adjust_in = {60'b0, gpio_in};
5: gpio_width_adjust_in = {59'b0, gpio_in};
6: gpio_width_adjust_in = {58'b0, gpio_in};
7: gpio_width_adjust_in = {57'b0, gpio_in};
8: gpio_width_adjust_in = {56'b0, gpio_in};
9: gpio_width_adjust_in = {55'b0, gpio_in};
10: gpio_width_adjust_in = {54'b0, gpio_in};
11: gpio_width_adjust_in = {53'b0, gpio_in};
12: gpio_width_adjust_in = {52'b0, gpio_in};
13: gpio_width_adjust_in = {51'b0, gpio_in};
14: gpio_width_adjust_in = {50'b0, gpio_in};
15: gpio_width_adjust_in = {49'b0, gpio_in};
16: gpio_width_adjust_in = {48'b0, gpio_in};
17: gpio_width_adjust_in = {47'b0, gpio_in};
18: gpio_width_adjust_in = {46'b0, gpio_in};
19: gpio_width_adjust_in = {45'b0, gpio_in};
20: gpio_width_adjust_in = {44'b0, gpio_in};
21: gpio_width_adjust_in = {43'b0, gpio_in};
22: gpio_width_adjust_in = {42'b0, gpio_in};
23: gpio_width_adjust_in = {41'b0, gpio_in};
24: gpio_width_adjust_in = {40'b0, gpio_in};
25: gpio_width_adjust_in = {39'b0, gpio_in};
26: gpio_width_adjust_in = {38'b0, gpio_in};
27: gpio_width_adjust_in = {37'b0, gpio_in};
28: gpio_width_adjust_in = {36'b0, gpio_in};
29: gpio_width_adjust_in = {35'b0, gpio_in};
30: gpio_width_adjust_in = {34'b0, gpio_in};
31: gpio_width_adjust_in = {33'b0, gpio_in};
32: gpio_width_adjust_in = {32'b0, gpio_in};
33: gpio_width_adjust_in = {31'b0, gpio_in};
34: gpio_width_adjust_in = {30'b0, gpio_in};
35: gpio_width_adjust_in = {29'b0, gpio_in};
36: gpio_width_adjust_in = {28'b0, gpio_in};
37: gpio_width_adjust_in = {27'b0, gpio_in};
38: gpio_width_adjust_in = {26'b0, gpio_in};
39: gpio_width_adjust_in = {25'b0, gpio_in};
40: gpio_width_adjust_in = {24'b0, gpio_in};
41: gpio_width_adjust_in = {23'b0, gpio_in};
42: gpio_width_adjust_in = {22'b0, gpio_in};
43: gpio_width_adjust_in = {21'b0, gpio_in};
44: gpio_width_adjust_in = {20'b0, gpio_in};
45: gpio_width_adjust_in = {19'b0, gpio_in};
46: gpio_width_adjust_in = {18'b0, gpio_in};
47: gpio_width_adjust_in = {17'b0, gpio_in};
48: gpio_width_adjust_in = {16'b0, gpio_in};
49: gpio_width_adjust_in = {15'b0, gpio_in};
50: gpio_width_adjust_in = {14'b0, gpio_in};
51: gpio_width_adjust_in = {13'b0, gpio_in};
52: gpio_width_adjust_in = {12'b0, gpio_in};
53: gpio_width_adjust_in = {11'b0, gpio_in};
54: gpio_width_adjust_in = {10'b0, gpio_in};
55: gpio_width_adjust_in = {9'b0, gpio_in};
56: gpio_width_adjust_in = {8'b0, gpio_in};
57: gpio_width_adjust_in = {7'b0, gpio_in};
58: gpio_width_adjust_in = {6'b0, gpio_in};
59: gpio_width_adjust_in = {5'b0, gpio_in};
60: gpio_width_adjust_in = {4'b0, gpio_in};
61: gpio_width_adjust_in = {3'b0, gpio_in};
62: gpio_width_adjust_in = {2'b0, gpio_in};
63: gpio_width_adjust_in = {1'b0, gpio_in};
64: gpio_width_adjust_in = gpio_in;
default : gpio_width_adjust_in = gpio_in;
endcase
end
endfunction
assign gpio_in63_0 = gpio_width_adjust_in(GPIO_I);
function [63:0] gpio_width_adjust_out;
input [(C_EMIO_GPIO_WIDTH - 1) : 0] gpio_o;
begin
case (C_EMIO_GPIO_WIDTH)
1: gpio_width_adjust_out = gpio_o[0];
2: gpio_width_adjust_out = gpio_o[1:0];
3: gpio_width_adjust_out = gpio_o[2:0];
4: gpio_width_adjust_out = gpio_o[3:0];
5: gpio_width_adjust_out = gpio_o[4:0];
6: gpio_width_adjust_out = gpio_o[5:0];
7: gpio_width_adjust_out = gpio_o[6:0];
8: gpio_width_adjust_out = gpio_o[7:0];
9: gpio_width_adjust_out = gpio_o[8:0];
10: gpio_width_adjust_out = gpio_o[9:0];
11: gpio_width_adjust_out = gpio_o[10:0];
12: gpio_width_adjust_out = gpio_o[11:0];
13: gpio_width_adjust_out = gpio_o[12:0];
14: gpio_width_adjust_out = gpio_o[13:0];
15: gpio_width_adjust_out = gpio_o[14:0];
16: gpio_width_adjust_out = gpio_o[15:0];
17: gpio_width_adjust_out = gpio_o[16:0];
18: gpio_width_adjust_out = gpio_o[17:0];
19: gpio_width_adjust_out = gpio_o[18:0];
20: gpio_width_adjust_out = gpio_o[19:0];
21: gpio_width_adjust_out = gpio_o[20:0];
22: gpio_width_adjust_out = gpio_o[21:0];
23: gpio_width_adjust_out = gpio_o[22:0];
24: gpio_width_adjust_out = gpio_o[23:0];
25: gpio_width_adjust_out = gpio_o[24:0];
26: gpio_width_adjust_out = gpio_o[25:0];
27: gpio_width_adjust_out = gpio_o[26:0];
28: gpio_width_adjust_out = gpio_o[27:0];
29: gpio_width_adjust_out = gpio_o[28:0];
30: gpio_width_adjust_out = gpio_o[29:0];
31: gpio_width_adjust_out = gpio_o[30:0];
32: gpio_width_adjust_out = gpio_o[31:0];
33: gpio_width_adjust_out = gpio_o[32:0];
34: gpio_width_adjust_out = gpio_o[33:0];
35: gpio_width_adjust_out = gpio_o[34:0];
36: gpio_width_adjust_out = gpio_o[35:0];
37: gpio_width_adjust_out = gpio_o[36:0];
38: gpio_width_adjust_out = gpio_o[37:0];
39: gpio_width_adjust_out = gpio_o[38:0];
40: gpio_width_adjust_out = gpio_o[39:0];
41: gpio_width_adjust_out = gpio_o[40:0];
42: gpio_width_adjust_out = gpio_o[41:0];
43: gpio_width_adjust_out = gpio_o[42:0];
44: gpio_width_adjust_out = gpio_o[43:0];
45: gpio_width_adjust_out = gpio_o[44:0];
46: gpio_width_adjust_out = gpio_o[45:0];
47: gpio_width_adjust_out = gpio_o[46:0];
48: gpio_width_adjust_out = gpio_o[47:0];
49: gpio_width_adjust_out = gpio_o[48:0];
50: gpio_width_adjust_out = gpio_o[49:0];
51: gpio_width_adjust_out = gpio_o[50:0];
52: gpio_width_adjust_out = gpio_o[51:0];
53: gpio_width_adjust_out = gpio_o[52:0];
54: gpio_width_adjust_out = gpio_o[53:0];
55: gpio_width_adjust_out = gpio_o[54:0];
56: gpio_width_adjust_out = gpio_o[55:0];
57: gpio_width_adjust_out = gpio_o[56:0];
58: gpio_width_adjust_out = gpio_o[57:0];
59: gpio_width_adjust_out = gpio_o[58:0];
60: gpio_width_adjust_out = gpio_o[59:0];
61: gpio_width_adjust_out = gpio_o[60:0];
62: gpio_width_adjust_out = gpio_o[61:0];
63: gpio_width_adjust_out = gpio_o[62:0];
64: gpio_width_adjust_out = gpio_o;
default : gpio_width_adjust_out = gpio_o;
endcase
end
endfunction
assign GPIO_O[(C_EMIO_GPIO_WIDTH - 1) : 0] = gpio_width_adjust_out(gpio_out);
assign GPIO_T_n[(C_EMIO_GPIO_WIDTH - 1) : 0] = gpio_width_adjust_out(gpio_out_t_n);
// Adding OBUFT to JTAG out port
generate
if ( C_EN_EMIO_PJTAG == 1 ) begin : PJTAG_OBUFT_TRUE
OBUFT jtag_obuft_inst (
.O(PJTAG_TDO),
.I(PJTAG_TDO_O),
.T(PJTAG_TDO_T)
);
end
else
begin
assign PJTAG_TDO = 1'b0;
end
endgenerate
// -------
// EMIO PJTAG
assign PJTAG_TDO_T = ~ PJTAG_TDO_T_n;
// EMIO SDIO0 : No negation required as per CR#636210 for 1.0 version of Silicon,
// FOR Other SI REV, inversion is required
assign SDIO0_CMD_T = (C_PS7_SI_REV == "1.0") ? (SDIO0_CMD_T_n) : (~ SDIO0_CMD_T_n);
assign SDIO0_DATA_T[3:0] = (C_PS7_SI_REV == "1.0") ? (SDIO0_DATA_T_n[3:0]) : (~ SDIO0_DATA_T_n[3:0]);
// EMIO SDIO1 : No negation required as per CR#636210 for 1.0 version of Silicon,
// FOR Other SI REV, inversion is required
assign SDIO1_CMD_T = (C_PS7_SI_REV == "1.0") ? (SDIO1_CMD_T_n) : (~ SDIO1_CMD_T_n);
assign SDIO1_DATA_T[3:0] = (C_PS7_SI_REV == "1.0") ? (SDIO1_DATA_T_n[3:0]) : (~ SDIO1_DATA_T_n[3:0]);
// FCLK_CLK optional clock buffers
generate
if (C_FCLK_CLK0_BUF == "TRUE" | C_FCLK_CLK0_BUF == "true") begin : buffer_fclk_clk_0
BUFG FCLK_CLK_0_BUFG (.I(FCLK_CLK_unbuffered[0]), .O(FCLK_CLK_buffered[0]));
end
if (C_FCLK_CLK1_BUF == "TRUE" | C_FCLK_CLK1_BUF == "true") begin : buffer_fclk_clk_1
BUFG FCLK_CLK_1_BUFG (.I(FCLK_CLK_unbuffered[1]), .O(FCLK_CLK_buffered[1]));
end
if (C_FCLK_CLK2_BUF == "TRUE" | C_FCLK_CLK2_BUF == "true") begin : buffer_fclk_clk_2
BUFG FCLK_CLK_2_BUFG (.I(FCLK_CLK_unbuffered[2]), .O(FCLK_CLK_buffered[2]));
end
if (C_FCLK_CLK3_BUF == "TRUE" | C_FCLK_CLK3_BUF == "true") begin : buffer_fclk_clk_3
BUFG FCLK_CLK_3_BUFG (.I(FCLK_CLK_unbuffered[3]), .O(FCLK_CLK_buffered[3]));
end
endgenerate
assign FCLK_CLK0_temp = (C_FCLK_CLK0_BUF == "TRUE" | C_FCLK_CLK0_BUF == "true") ? FCLK_CLK_buffered[0] : FCLK_CLK_unbuffered[0];
assign FCLK_CLK1 = (C_FCLK_CLK1_BUF == "TRUE" | C_FCLK_CLK1_BUF == "true") ? FCLK_CLK_buffered[1] : FCLK_CLK_unbuffered[1];
assign FCLK_CLK2 = (C_FCLK_CLK2_BUF == "TRUE" | C_FCLK_CLK2_BUF == "true") ? FCLK_CLK_buffered[2] : FCLK_CLK_unbuffered[2];
assign FCLK_CLK3 = (C_FCLK_CLK3_BUF == "TRUE" | C_FCLK_CLK3_BUF == "true") ? FCLK_CLK_buffered[3] : FCLK_CLK_unbuffered[3];
assign FCLK_CLK0 = FCLK_CLK0_temp;
// Adding BIBUF for fixed IO Ports and IBUF for fixed Input Ports
BIBUF DDR_CAS_n_BIBUF (.PAD(DDR_CAS_n), .IO(buffered_DDR_CAS_n));
BIBUF DDR_CKE_BIBUF (.PAD(DDR_CKE), .IO(buffered_DDR_CKE));
BIBUF DDR_Clk_n_BIBUF (.PAD(DDR_Clk_n), .IO(buffered_DDR_Clk_n));
BIBUF DDR_Clk_BIBUF (.PAD(DDR_Clk), .IO(buffered_DDR_Clk));
BIBUF DDR_CS_n_BIBUF (.PAD(DDR_CS_n), .IO(buffered_DDR_CS_n));
BIBUF DDR_DRSTB_BIBUF (.PAD(DDR_DRSTB), .IO(buffered_DDR_DRSTB));
BIBUF DDR_ODT_BIBUF (.PAD(DDR_ODT), .IO(buffered_DDR_ODT));
BIBUF DDR_RAS_n_BIBUF (.PAD(DDR_RAS_n), .IO(buffered_DDR_RAS_n));
BIBUF DDR_WEB_BIBUF (.PAD(DDR_WEB), .IO(buffered_DDR_WEB));
BIBUF DDR_VRN_BIBUF (.PAD(DDR_VRN), .IO(buffered_DDR_VRN));
BIBUF DDR_VRP_BIBUF (.PAD(DDR_VRP), .IO(buffered_DDR_VRP));
BIBUF PS_SRSTB_BIBUF (.PAD(PS_SRSTB), .IO(buffered_PS_SRSTB));
BIBUF PS_CLK_BIBUF (.PAD(PS_CLK), .IO(buffered_PS_CLK));
BIBUF PS_PORB_BIBUF (.PAD(PS_PORB), .IO(buffered_PS_PORB));
genvar i;
generate
for (i=0; i < C_MIO_PRIMITIVE; i=i+1) begin
BIBUF MIO_BIBUF (.PAD(MIO[i]), .IO(buffered_MIO[i]));
end
endgenerate
generate
for (i=0; i < 3; i=i+1) begin
BIBUF DDR_BankAddr_BIBUF (.PAD(DDR_BankAddr[i]), .IO(buffered_DDR_BankAddr[i]));
end
endgenerate
generate
for (i=0; i < 15; i=i+1) begin
BIBUF DDR_Addr_BIBUF (.PAD(DDR_Addr[i]), .IO(buffered_DDR_Addr[i]));
end
endgenerate
generate
for (i=0; i < C_DM_WIDTH; i=i+1) begin
BIBUF DDR_DM_BIBUF (.PAD(DDR_DM[i]), .IO(buffered_DDR_DM[i]));
end
endgenerate
generate
for (i=0; i < C_DQ_WIDTH; i=i+1) begin
BIBUF DDR_DQ_BIBUF (.PAD(DDR_DQ[i]), .IO(buffered_DDR_DQ[i]));
end
endgenerate
generate
for (i=0; i < C_DQS_WIDTH; i=i+1) begin
BIBUF DDR_DQS_n_BIBUF (.PAD(DDR_DQS_n[i]), .IO(buffered_DDR_DQS_n[i]));
end
endgenerate
generate
for (i=0; i < C_DQS_WIDTH; i=i+1) begin
BIBUF DDR_DQS_BIBUF (.PAD(DDR_DQS[i]), .IO(buffered_DDR_DQS[i]));
end
endgenerate
// Connect FCLK in case of disable the AXI port for non Secure Transaction
//Start
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_HP0 == 0) begin
assign S_AXI_HP0_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_HP0_ACLK_temp = S_AXI_HP0_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_HP1 == 0) begin
assign S_AXI_HP1_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_HP1_ACLK_temp = S_AXI_HP1_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_HP2 == 0) begin
assign S_AXI_HP2_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_HP2_ACLK_temp = S_AXI_HP2_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_HP3 == 0) begin
assign S_AXI_HP3_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_HP3_ACLK_temp = S_AXI_HP3_ACLK;
end
endgenerate
//Start
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_M_AXI_GP0 == 0) begin
assign M_AXI_GP0_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign M_AXI_GP0_ACLK_temp = M_AXI_GP0_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_M_AXI_GP1 == 0) begin
assign M_AXI_GP1_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign M_AXI_GP1_ACLK_temp = M_AXI_GP1_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_GP0 == 0) begin
assign S_AXI_GP0_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_GP0_ACLK_temp = S_AXI_GP0_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_GP1 == 0) begin
assign S_AXI_GP1_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_GP1_ACLK_temp = S_AXI_GP1_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_ACP == 0) begin
assign S_AXI_ACP_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_ACP_ACLK_temp = S_AXI_ACP_ACLK;
end
endgenerate
assign M_AXI_GP0_ARCACHE=(C_GP0_EN_MODIFIABLE_TXN==1)?{{M_AXI_GP0_ARCACHE_t[3:2]},{1'b1},{M_AXI_GP0_ARCACHE_t[0]}}:M_AXI_GP0_ARCACHE_t ;
assign M_AXI_GP1_ARCACHE=(C_GP1_EN_MODIFIABLE_TXN==1)?{{M_AXI_GP1_ARCACHE_t[3:2]},{1'b1},{M_AXI_GP1_ARCACHE_t[0]}}:M_AXI_GP1_ARCACHE_t ;
assign M_AXI_GP0_AWCACHE=(C_GP0_EN_MODIFIABLE_TXN==1)?{{M_AXI_GP0_AWCACHE_t[3:2]},{1'b1},{M_AXI_GP0_AWCACHE_t[0]}}:M_AXI_GP0_AWCACHE_t ;
assign M_AXI_GP1_AWCACHE=(C_GP1_EN_MODIFIABLE_TXN==1)?{{M_AXI_GP1_AWCACHE_t[3:2]},{1'b1},{M_AXI_GP1_AWCACHE_t[0]}}:M_AXI_GP1_AWCACHE_t ;
//END
//====================
//PSS TOP
//====================
generate
if (C_PACKAGE_NAME == "clg225" ) begin
wire [21:0] dummy;
PS7 PS7_i (
.DMA0DATYPE (DMA0_DATYPE ),
.DMA0DAVALID (DMA0_DAVALID),
.DMA0DRREADY (DMA0_DRREADY),
.DMA0RSTN (DMA0_RSTN ),
.DMA1DATYPE (DMA1_DATYPE ),
.DMA1DAVALID (DMA1_DAVALID),
.DMA1DRREADY (DMA1_DRREADY),
.DMA1RSTN (DMA1_RSTN ),
.DMA2DATYPE (DMA2_DATYPE ),
.DMA2DAVALID (DMA2_DAVALID),
.DMA2DRREADY (DMA2_DRREADY),
.DMA2RSTN (DMA2_RSTN ),
.DMA3DATYPE (DMA3_DATYPE ),
.DMA3DAVALID (DMA3_DAVALID),
.DMA3DRREADY (DMA3_DRREADY),
.DMA3RSTN (DMA3_RSTN ),
.EMIOCAN0PHYTX (CAN0_PHY_TX ),
.EMIOCAN1PHYTX (CAN1_PHY_TX ),
.EMIOENET0GMIITXD (ENET0_GMII_TXD_i), // (ENET0_GMII_TXD_i ),
.EMIOENET0GMIITXEN (ENET0_GMII_TX_EN_i), // (ENET0_GMII_TX_EN_i),
.EMIOENET0GMIITXER (ENET0_GMII_TX_ER_i), // (ENET0_GMII_TX_ER_i),
.EMIOENET0MDIOMDC (ENET0_MDIO_MDC),
.EMIOENET0MDIOO (ENET0_MDIO_O ),
.EMIOENET0MDIOTN (ENET0_MDIO_T_n ),
.EMIOENET0PTPDELAYREQRX (ENET0_PTP_DELAY_REQ_RX),
.EMIOENET0PTPDELAYREQTX (ENET0_PTP_DELAY_REQ_TX),
.EMIOENET0PTPPDELAYREQRX (ENET0_PTP_PDELAY_REQ_RX),
.EMIOENET0PTPPDELAYREQTX (ENET0_PTP_PDELAY_REQ_TX),
.EMIOENET0PTPPDELAYRESPRX(ENET0_PTP_PDELAY_RESP_RX),
.EMIOENET0PTPPDELAYRESPTX(ENET0_PTP_PDELAY_RESP_TX),
.EMIOENET0PTPSYNCFRAMERX (ENET0_PTP_SYNC_FRAME_RX),
.EMIOENET0PTPSYNCFRAMETX (ENET0_PTP_SYNC_FRAME_TX),
.EMIOENET0SOFRX (ENET0_SOF_RX),
.EMIOENET0SOFTX (ENET0_SOF_TX),
.EMIOENET1GMIITXD (ENET1_GMII_TXD_i), //(ENET1_GMII_TXD_i),
.EMIOENET1GMIITXEN (ENET1_GMII_TX_EN_i), // (ENET1_GMII_TX_EN_i),
.EMIOENET1GMIITXER (ENET1_GMII_TX_ER_i), // (ENET1_GMII_TX_ER_i),
.EMIOENET1MDIOMDC (ENET1_MDIO_MDC),
.EMIOENET1MDIOO (ENET1_MDIO_O),
.EMIOENET1MDIOTN (ENET1_MDIO_T_n),
.EMIOENET1PTPDELAYREQRX (ENET1_PTP_DELAY_REQ_RX),
.EMIOENET1PTPDELAYREQTX (ENET1_PTP_DELAY_REQ_TX),
.EMIOENET1PTPPDELAYREQRX (ENET1_PTP_PDELAY_REQ_RX),
.EMIOENET1PTPPDELAYREQTX (ENET1_PTP_PDELAY_REQ_TX),
.EMIOENET1PTPPDELAYRESPRX(ENET1_PTP_PDELAY_RESP_RX),
.EMIOENET1PTPPDELAYRESPTX(ENET1_PTP_PDELAY_RESP_TX),
.EMIOENET1PTPSYNCFRAMERX (ENET1_PTP_SYNC_FRAME_RX),
.EMIOENET1PTPSYNCFRAMETX (ENET1_PTP_SYNC_FRAME_TX),
.EMIOENET1SOFRX (ENET1_SOF_RX),
.EMIOENET1SOFTX (ENET1_SOF_TX),
.EMIOGPIOO (gpio_out),
.EMIOGPIOTN (gpio_out_t_n),
.EMIOI2C0SCLO (I2C0_SCL_O),
.EMIOI2C0SCLTN (I2C0_SCL_T_n),
.EMIOI2C0SDAO (I2C0_SDA_O),
.EMIOI2C0SDATN (I2C0_SDA_T_n),
.EMIOI2C1SCLO (I2C1_SCL_O),
.EMIOI2C1SCLTN (I2C1_SCL_T_n),
.EMIOI2C1SDAO (I2C1_SDA_O),
.EMIOI2C1SDATN (I2C1_SDA_T_n),
.EMIOPJTAGTDO (PJTAG_TDO_O),
.EMIOPJTAGTDTN (PJTAG_TDO_T_n),
.EMIOSDIO0BUSPOW (SDIO0_BUSPOW),
.EMIOSDIO0CLK (SDIO0_CLK ),
.EMIOSDIO0CMDO (SDIO0_CMD_O ),
.EMIOSDIO0CMDTN (SDIO0_CMD_T_n ),
.EMIOSDIO0DATAO (SDIO0_DATA_O),
.EMIOSDIO0DATATN (SDIO0_DATA_T_n),
.EMIOSDIO0LED (SDIO0_LED),
.EMIOSDIO1BUSPOW (SDIO1_BUSPOW),
.EMIOSDIO1CLK (SDIO1_CLK ),
.EMIOSDIO1CMDO (SDIO1_CMD_O ),
.EMIOSDIO1CMDTN (SDIO1_CMD_T_n ),
.EMIOSDIO1DATAO (SDIO1_DATA_O),
.EMIOSDIO1DATATN (SDIO1_DATA_T_n),
.EMIOSDIO1LED (SDIO1_LED),
.EMIOSPI0MO (SPI0_MOSI_O),
.EMIOSPI0MOTN (SPI0_MOSI_T_n),
.EMIOSPI0SCLKO (SPI0_SCLK_O),
.EMIOSPI0SCLKTN (SPI0_SCLK_T_n),
.EMIOSPI0SO (SPI0_MISO_O),
.EMIOSPI0STN (SPI0_MISO_T_n),
.EMIOSPI0SSON ({SPI0_SS2_O,SPI0_SS1_O,SPI0_SS_O}),
.EMIOSPI0SSNTN (SPI0_SS_T_n),
.EMIOSPI1MO (SPI1_MOSI_O),
.EMIOSPI1MOTN (SPI1_MOSI_T_n),
.EMIOSPI1SCLKO (SPI1_SCLK_O),
.EMIOSPI1SCLKTN (SPI1_SCLK_T_n),
.EMIOSPI1SO (SPI1_MISO_O),
.EMIOSPI1STN (SPI1_MISO_T_n),
.EMIOSPI1SSON ({SPI1_SS2_O,SPI1_SS1_O,SPI1_SS_O}),
.EMIOSPI1SSNTN (SPI1_SS_T_n),
.EMIOTRACECTL (TRACE_CTL_i),
.EMIOTRACEDATA (TRACE_DATA_i),
.EMIOTTC0WAVEO ({TTC0_WAVE2_OUT,TTC0_WAVE1_OUT,TTC0_WAVE0_OUT}),
.EMIOTTC1WAVEO ({TTC1_WAVE2_OUT,TTC1_WAVE1_OUT,TTC1_WAVE0_OUT}),
.EMIOUART0DTRN (UART0_DTRN),
.EMIOUART0RTSN (UART0_RTSN),
.EMIOUART0TX (UART0_TX ),
.EMIOUART1DTRN (UART1_DTRN),
.EMIOUART1RTSN (UART1_RTSN),
.EMIOUART1TX (UART1_TX ),
.EMIOUSB0PORTINDCTL (USB0_PORT_INDCTL),
.EMIOUSB0VBUSPWRSELECT (USB0_VBUS_PWRSELECT),
.EMIOUSB1PORTINDCTL (USB1_PORT_INDCTL),
.EMIOUSB1VBUSPWRSELECT (USB1_VBUS_PWRSELECT),
.EMIOWDTRSTO (WDT_RST_OUT),
.EVENTEVENTO (EVENT_EVENTO),
.EVENTSTANDBYWFE (EVENT_STANDBYWFE),
.EVENTSTANDBYWFI (EVENT_STANDBYWFI),
.FCLKCLK (FCLK_CLK_unbuffered),
.FCLKRESETN ({FCLK_RESET3_N,FCLK_RESET2_N,FCLK_RESET1_N,FCLK_RESET0_N}),
.EMIOSDIO0BUSVOLT (SDIO0_BUSVOLT),
.EMIOSDIO1BUSVOLT (SDIO1_BUSVOLT),
.FTMTF2PTRIGACK ({FTMT_F2P_TRIGACK_3,FTMT_F2P_TRIGACK_2,FTMT_F2P_TRIGACK_1,FTMT_F2P_TRIGACK_0}),
.FTMTP2FDEBUG (FTMT_P2F_DEBUG ),
.FTMTP2FTRIG ({FTMT_P2F_TRIG_3,FTMT_P2F_TRIG_2,FTMT_P2F_TRIG_1,FTMT_P2F_TRIG_0}),
.IRQP2F ({IRQ_P2F_DMAC_ABORT, IRQ_P2F_DMAC7, IRQ_P2F_DMAC6, IRQ_P2F_DMAC5, IRQ_P2F_DMAC4, IRQ_P2F_DMAC3, IRQ_P2F_DMAC2, IRQ_P2F_DMAC1, IRQ_P2F_DMAC0, IRQ_P2F_SMC, IRQ_P2F_QSPI, IRQ_P2F_CTI, IRQ_P2F_GPIO, IRQ_P2F_USB0, IRQ_P2F_ENET0, IRQ_P2F_ENET_WAKE0, IRQ_P2F_SDIO0, IRQ_P2F_I2C0, IRQ_P2F_SPI0, IRQ_P2F_UART0, IRQ_P2F_CAN0, IRQ_P2F_USB1, IRQ_P2F_ENET1, IRQ_P2F_ENET_WAKE1, IRQ_P2F_SDIO1, IRQ_P2F_I2C1, IRQ_P2F_SPI1, IRQ_P2F_UART1, IRQ_P2F_CAN1}),
.MAXIGP0ARADDR (M_AXI_GP0_ARADDR),
.MAXIGP0ARBURST (M_AXI_GP0_ARBURST),
.MAXIGP0ARCACHE (M_AXI_GP0_ARCACHE_t),
.MAXIGP0ARESETN (M_AXI_GP0_ARESETN),
.MAXIGP0ARID (M_AXI_GP0_ARID_FULL ),
.MAXIGP0ARLEN (M_AXI_GP0_ARLEN ),
.MAXIGP0ARLOCK (M_AXI_GP0_ARLOCK ),
.MAXIGP0ARPROT (M_AXI_GP0_ARPROT ),
.MAXIGP0ARQOS (M_AXI_GP0_ARQOS ),
.MAXIGP0ARSIZE (M_AXI_GP0_ARSIZE_i ),
.MAXIGP0ARVALID (M_AXI_GP0_ARVALID),
.MAXIGP0AWADDR (M_AXI_GP0_AWADDR ),
.MAXIGP0AWBURST (M_AXI_GP0_AWBURST),
.MAXIGP0AWCACHE (M_AXI_GP0_AWCACHE_t),
.MAXIGP0AWID (M_AXI_GP0_AWID_FULL ),
.MAXIGP0AWLEN (M_AXI_GP0_AWLEN ),
.MAXIGP0AWLOCK (M_AXI_GP0_AWLOCK ),
.MAXIGP0AWPROT (M_AXI_GP0_AWPROT ),
.MAXIGP0AWQOS (M_AXI_GP0_AWQOS ),
.MAXIGP0AWSIZE (M_AXI_GP0_AWSIZE_i ),
.MAXIGP0AWVALID (M_AXI_GP0_AWVALID),
.MAXIGP0BREADY (M_AXI_GP0_BREADY ),
.MAXIGP0RREADY (M_AXI_GP0_RREADY ),
.MAXIGP0WDATA (M_AXI_GP0_WDATA ),
.MAXIGP0WID (M_AXI_GP0_WID_FULL ),
.MAXIGP0WLAST (M_AXI_GP0_WLAST ),
.MAXIGP0WSTRB (M_AXI_GP0_WSTRB ),
.MAXIGP0WVALID (M_AXI_GP0_WVALID ),
.MAXIGP1ARADDR (M_AXI_GP1_ARADDR ),
.MAXIGP1ARBURST (M_AXI_GP1_ARBURST),
.MAXIGP1ARCACHE (M_AXI_GP1_ARCACHE_t),
.MAXIGP1ARESETN (M_AXI_GP1_ARESETN),
.MAXIGP1ARID (M_AXI_GP1_ARID_FULL ),
.MAXIGP1ARLEN (M_AXI_GP1_ARLEN ),
.MAXIGP1ARLOCK (M_AXI_GP1_ARLOCK ),
.MAXIGP1ARPROT (M_AXI_GP1_ARPROT ),
.MAXIGP1ARQOS (M_AXI_GP1_ARQOS ),
.MAXIGP1ARSIZE (M_AXI_GP1_ARSIZE_i ),
.MAXIGP1ARVALID (M_AXI_GP1_ARVALID),
.MAXIGP1AWADDR (M_AXI_GP1_AWADDR ),
.MAXIGP1AWBURST (M_AXI_GP1_AWBURST),
.MAXIGP1AWCACHE (M_AXI_GP1_AWCACHE_t),
.MAXIGP1AWID (M_AXI_GP1_AWID_FULL ),
.MAXIGP1AWLEN (M_AXI_GP1_AWLEN ),
.MAXIGP1AWLOCK (M_AXI_GP1_AWLOCK ),
.MAXIGP1AWPROT (M_AXI_GP1_AWPROT ),
.MAXIGP1AWQOS (M_AXI_GP1_AWQOS ),
.MAXIGP1AWSIZE (M_AXI_GP1_AWSIZE_i ),
.MAXIGP1AWVALID (M_AXI_GP1_AWVALID),
.MAXIGP1BREADY (M_AXI_GP1_BREADY ),
.MAXIGP1RREADY (M_AXI_GP1_RREADY ),
.MAXIGP1WDATA (M_AXI_GP1_WDATA ),
.MAXIGP1WID (M_AXI_GP1_WID_FULL ),
.MAXIGP1WLAST (M_AXI_GP1_WLAST ),
.MAXIGP1WSTRB (M_AXI_GP1_WSTRB ),
.MAXIGP1WVALID (M_AXI_GP1_WVALID ),
.SAXIACPARESETN (S_AXI_ACP_ARESETN),
.SAXIACPARREADY (SAXIACPARREADY_W),
.SAXIACPAWREADY (SAXIACPAWREADY_W),
.SAXIACPBID (S_AXI_ACP_BID_out ),
.SAXIACPBRESP (SAXIACPBRESP_W ),
.SAXIACPBVALID (SAXIACPBVALID_W ),
.SAXIACPRDATA (SAXIACPRDATA_W ),
.SAXIACPRID (S_AXI_ACP_RID_out),
.SAXIACPRLAST (SAXIACPRLAST_W ),
.SAXIACPRRESP (SAXIACPRRESP_W ),
.SAXIACPRVALID (SAXIACPRVALID_W ),
.SAXIACPWREADY (SAXIACPWREADY_W ),
.SAXIGP0ARESETN (S_AXI_GP0_ARESETN),
.SAXIGP0ARREADY (S_AXI_GP0_ARREADY),
.SAXIGP0AWREADY (S_AXI_GP0_AWREADY),
.SAXIGP0BID (S_AXI_GP0_BID_out),
.SAXIGP0BRESP (S_AXI_GP0_BRESP ),
.SAXIGP0BVALID (S_AXI_GP0_BVALID ),
.SAXIGP0RDATA (S_AXI_GP0_RDATA ),
.SAXIGP0RID (S_AXI_GP0_RID_out ),
.SAXIGP0RLAST (S_AXI_GP0_RLAST ),
.SAXIGP0RRESP (S_AXI_GP0_RRESP ),
.SAXIGP0RVALID (S_AXI_GP0_RVALID ),
.SAXIGP0WREADY (S_AXI_GP0_WREADY ),
.SAXIGP1ARESETN (S_AXI_GP1_ARESETN),
.SAXIGP1ARREADY (S_AXI_GP1_ARREADY),
.SAXIGP1AWREADY (S_AXI_GP1_AWREADY),
.SAXIGP1BID (S_AXI_GP1_BID_out ),
.SAXIGP1BRESP (S_AXI_GP1_BRESP ),
.SAXIGP1BVALID (S_AXI_GP1_BVALID ),
.SAXIGP1RDATA (S_AXI_GP1_RDATA ),
.SAXIGP1RID (S_AXI_GP1_RID_out ),
.SAXIGP1RLAST (S_AXI_GP1_RLAST ),
.SAXIGP1RRESP (S_AXI_GP1_RRESP ),
.SAXIGP1RVALID (S_AXI_GP1_RVALID ),
.SAXIGP1WREADY (S_AXI_GP1_WREADY ),
.SAXIHP0ARESETN (S_AXI_HP0_ARESETN),
.SAXIHP0ARREADY (S_AXI_HP0_ARREADY),
.SAXIHP0AWREADY (S_AXI_HP0_AWREADY),
.SAXIHP0BID (S_AXI_HP0_BID_out ),
.SAXIHP0BRESP (S_AXI_HP0_BRESP ),
.SAXIHP0BVALID (S_AXI_HP0_BVALID ),
.SAXIHP0RACOUNT (S_AXI_HP0_RACOUNT),
.SAXIHP0RCOUNT (S_AXI_HP0_RCOUNT),
.SAXIHP0RDATA (S_AXI_HP0_RDATA_out),
.SAXIHP0RID (S_AXI_HP0_RID_out ),
.SAXIHP0RLAST (S_AXI_HP0_RLAST),
.SAXIHP0RRESP (S_AXI_HP0_RRESP),
.SAXIHP0RVALID (S_AXI_HP0_RVALID),
.SAXIHP0WCOUNT (S_AXI_HP0_WCOUNT),
.SAXIHP0WACOUNT (S_AXI_HP0_WACOUNT),
.SAXIHP0WREADY (S_AXI_HP0_WREADY),
.SAXIHP1ARESETN (S_AXI_HP1_ARESETN),
.SAXIHP1ARREADY (S_AXI_HP1_ARREADY),
.SAXIHP1AWREADY (S_AXI_HP1_AWREADY),
.SAXIHP1BID (S_AXI_HP1_BID_out ),
.SAXIHP1BRESP (S_AXI_HP1_BRESP ),
.SAXIHP1BVALID (S_AXI_HP1_BVALID ),
.SAXIHP1RACOUNT (S_AXI_HP1_RACOUNT ),
.SAXIHP1RCOUNT (S_AXI_HP1_RCOUNT ),
.SAXIHP1RDATA (S_AXI_HP1_RDATA_out),
.SAXIHP1RID (S_AXI_HP1_RID_out ),
.SAXIHP1RLAST (S_AXI_HP1_RLAST ),
.SAXIHP1RRESP (S_AXI_HP1_RRESP ),
.SAXIHP1RVALID (S_AXI_HP1_RVALID),
.SAXIHP1WACOUNT (S_AXI_HP1_WACOUNT),
.SAXIHP1WCOUNT (S_AXI_HP1_WCOUNT),
.SAXIHP1WREADY (S_AXI_HP1_WREADY),
.SAXIHP2ARESETN (S_AXI_HP2_ARESETN),
.SAXIHP2ARREADY (S_AXI_HP2_ARREADY),
.SAXIHP2AWREADY (S_AXI_HP2_AWREADY),
.SAXIHP2BID (S_AXI_HP2_BID_out ),
.SAXIHP2BRESP (S_AXI_HP2_BRESP),
.SAXIHP2BVALID (S_AXI_HP2_BVALID),
.SAXIHP2RACOUNT (S_AXI_HP2_RACOUNT),
.SAXIHP2RCOUNT (S_AXI_HP2_RCOUNT),
.SAXIHP2RDATA (S_AXI_HP2_RDATA_out),
.SAXIHP2RID (S_AXI_HP2_RID_out ),
.SAXIHP2RLAST (S_AXI_HP2_RLAST),
.SAXIHP2RRESP (S_AXI_HP2_RRESP),
.SAXIHP2RVALID (S_AXI_HP2_RVALID),
.SAXIHP2WACOUNT (S_AXI_HP2_WACOUNT),
.SAXIHP2WCOUNT (S_AXI_HP2_WCOUNT),
.SAXIHP2WREADY (S_AXI_HP2_WREADY),
.SAXIHP3ARESETN (S_AXI_HP3_ARESETN),
.SAXIHP3ARREADY (S_AXI_HP3_ARREADY),
.SAXIHP3AWREADY (S_AXI_HP3_AWREADY),
.SAXIHP3BID (S_AXI_HP3_BID_out),
.SAXIHP3BRESP (S_AXI_HP3_BRESP),
.SAXIHP3BVALID (S_AXI_HP3_BVALID),
.SAXIHP3RACOUNT (S_AXI_HP3_RACOUNT),
.SAXIHP3RCOUNT (S_AXI_HP3_RCOUNT),
.SAXIHP3RDATA (S_AXI_HP3_RDATA_out),
.SAXIHP3RID (S_AXI_HP3_RID_out),
.SAXIHP3RLAST (S_AXI_HP3_RLAST),
.SAXIHP3RRESP (S_AXI_HP3_RRESP),
.SAXIHP3RVALID (S_AXI_HP3_RVALID),
.SAXIHP3WCOUNT (S_AXI_HP3_WCOUNT),
.SAXIHP3WACOUNT (S_AXI_HP3_WACOUNT),
.SAXIHP3WREADY (S_AXI_HP3_WREADY),
.DDRARB (DDR_ARB),
.DMA0ACLK (DMA0_ACLK ),
.DMA0DAREADY (DMA0_DAREADY),
.DMA0DRLAST (DMA0_DRLAST ),
.DMA0DRTYPE (DMA0_DRTYPE),
.DMA0DRVALID (DMA0_DRVALID),
.DMA1ACLK (DMA1_ACLK ),
.DMA1DAREADY (DMA1_DAREADY),
.DMA1DRLAST (DMA1_DRLAST ),
.DMA1DRTYPE (DMA1_DRTYPE),
.DMA1DRVALID (DMA1_DRVALID),
.DMA2ACLK (DMA2_ACLK ),
.DMA2DAREADY (DMA2_DAREADY),
.DMA2DRLAST (DMA2_DRLAST ),
.DMA2DRTYPE (DMA2_DRTYPE),
.DMA2DRVALID (DMA2_DRVALID),
.DMA3ACLK (DMA3_ACLK ),
.DMA3DAREADY (DMA3_DAREADY),
.DMA3DRLAST (DMA3_DRLAST ),
.DMA3DRTYPE (DMA3_DRTYPE),
.DMA3DRVALID (DMA3_DRVALID),
.EMIOCAN0PHYRX (CAN0_PHY_RX),
.EMIOCAN1PHYRX (CAN1_PHY_RX),
.EMIOENET0EXTINTIN (ENET0_EXT_INTIN),
.EMIOENET0GMIICOL (ENET0_GMII_COL_i),
.EMIOENET0GMIICRS (ENET0_GMII_CRS_i),
.EMIOENET0GMIIRXCLK (ENET0_GMII_RX_CLK),
.EMIOENET0GMIIRXD (ENET0_GMII_RXD_i),
.EMIOENET0GMIIRXDV (ENET0_GMII_RX_DV_i),
.EMIOENET0GMIIRXER (ENET0_GMII_RX_ER_i),
.EMIOENET0GMIITXCLK (ENET0_GMII_TX_CLK),
.EMIOENET0MDIOI (ENET0_MDIO_I),
.EMIOENET1EXTINTIN (ENET1_EXT_INTIN),
.EMIOENET1GMIICOL (ENET1_GMII_COL_i),
.EMIOENET1GMIICRS (ENET1_GMII_CRS_i),
.EMIOENET1GMIIRXCLK (ENET1_GMII_RX_CLK),
.EMIOENET1GMIIRXD (ENET1_GMII_RXD_i),
.EMIOENET1GMIIRXDV (ENET1_GMII_RX_DV_i),
.EMIOENET1GMIIRXER (ENET1_GMII_RX_ER_i),
.EMIOENET1GMIITXCLK (ENET1_GMII_TX_CLK),
.EMIOENET1MDIOI (ENET1_MDIO_I),
.EMIOGPIOI (gpio_in63_0 ),
.EMIOI2C0SCLI (I2C0_SCL_I),
.EMIOI2C0SDAI (I2C0_SDA_I),
.EMIOI2C1SCLI (I2C1_SCL_I),
.EMIOI2C1SDAI (I2C1_SDA_I),
.EMIOPJTAGTCK (PJTAG_TCK),
.EMIOPJTAGTDI (PJTAG_TDI),
.EMIOPJTAGTMS (PJTAG_TMS),
.EMIOSDIO0CDN (SDIO0_CDN),
.EMIOSDIO0CLKFB (SDIO0_CLK_FB ),
.EMIOSDIO0CMDI (SDIO0_CMD_I ),
.EMIOSDIO0DATAI (SDIO0_DATA_I ),
.EMIOSDIO0WP (SDIO0_WP),
.EMIOSDIO1CDN (SDIO1_CDN),
.EMIOSDIO1CLKFB (SDIO1_CLK_FB ),
.EMIOSDIO1CMDI (SDIO1_CMD_I ),
.EMIOSDIO1DATAI (SDIO1_DATA_I ),
.EMIOSDIO1WP (SDIO1_WP),
.EMIOSPI0MI (SPI0_MISO_I),
.EMIOSPI0SCLKI (SPI0_SCLK_I),
.EMIOSPI0SI (SPI0_MOSI_I),
.EMIOSPI0SSIN (SPI0_SS_I),
.EMIOSPI1MI (SPI1_MISO_I),
.EMIOSPI1SCLKI (SPI1_SCLK_I),
.EMIOSPI1SI (SPI1_MOSI_I),
.EMIOSPI1SSIN (SPI1_SS_I),
.EMIOSRAMINTIN (SRAM_INTIN),
.EMIOTRACECLK (TRACE_CLK),
.EMIOTTC0CLKI ({TTC0_CLK2_IN, TTC0_CLK1_IN, TTC0_CLK0_IN}),
.EMIOTTC1CLKI ({TTC1_CLK2_IN, TTC1_CLK1_IN, TTC1_CLK0_IN}),
.EMIOUART0CTSN (UART0_CTSN),
.EMIOUART0DCDN (UART0_DCDN),
.EMIOUART0DSRN (UART0_DSRN),
.EMIOUART0RIN (UART0_RIN ),
.EMIOUART0RX (UART0_RX ),
.EMIOUART1CTSN (UART1_CTSN),
.EMIOUART1DCDN (UART1_DCDN),
.EMIOUART1DSRN (UART1_DSRN),
.EMIOUART1RIN (UART1_RIN ),
.EMIOUART1RX (UART1_RX ),
.EMIOUSB0VBUSPWRFAULT (USB0_VBUS_PWRFAULT),
.EMIOUSB1VBUSPWRFAULT (USB1_VBUS_PWRFAULT),
.EMIOWDTCLKI (WDT_CLK_IN),
.EVENTEVENTI (EVENT_EVENTI),
.FCLKCLKTRIGN (fclk_clktrig_gnd),
.FPGAIDLEN (FPGA_IDLE_N),
.FTMDTRACEINATID (FTMD_TRACEIN_ATID_i),
.FTMDTRACEINCLOCK (FTMD_TRACEIN_CLK),
.FTMDTRACEINDATA (FTMD_TRACEIN_DATA_i),
.FTMDTRACEINVALID (FTMD_TRACEIN_VALID_i),
.FTMTF2PDEBUG (FTMT_F2P_DEBUG ),
.FTMTF2PTRIG ({FTMT_F2P_TRIG_3,FTMT_F2P_TRIG_2,FTMT_F2P_TRIG_1,FTMT_F2P_TRIG_0}),
.FTMTP2FTRIGACK ({FTMT_P2F_TRIGACK_3,FTMT_P2F_TRIGACK_2,FTMT_P2F_TRIGACK_1,FTMT_P2F_TRIGACK_0}),
.IRQF2P (irq_f2p_i),
.MAXIGP0ACLK (M_AXI_GP0_ACLK_temp),
.MAXIGP0ARREADY (M_AXI_GP0_ARREADY),
.MAXIGP0AWREADY (M_AXI_GP0_AWREADY),
.MAXIGP0BID (M_AXI_GP0_BID_FULL ),
.MAXIGP0BRESP (M_AXI_GP0_BRESP ),
.MAXIGP0BVALID (M_AXI_GP0_BVALID ),
.MAXIGP0RDATA (M_AXI_GP0_RDATA ),
.MAXIGP0RID (M_AXI_GP0_RID_FULL ),
.MAXIGP0RLAST (M_AXI_GP0_RLAST ),
.MAXIGP0RRESP (M_AXI_GP0_RRESP ),
.MAXIGP0RVALID (M_AXI_GP0_RVALID ),
.MAXIGP0WREADY (M_AXI_GP0_WREADY ),
.MAXIGP1ACLK (M_AXI_GP1_ACLK_temp ),
.MAXIGP1ARREADY (M_AXI_GP1_ARREADY),
.MAXIGP1AWREADY (M_AXI_GP1_AWREADY),
.MAXIGP1BID (M_AXI_GP1_BID_FULL ),
.MAXIGP1BRESP (M_AXI_GP1_BRESP ),
.MAXIGP1BVALID (M_AXI_GP1_BVALID ),
.MAXIGP1RDATA (M_AXI_GP1_RDATA ),
.MAXIGP1RID (M_AXI_GP1_RID_FULL ),
.MAXIGP1RLAST (M_AXI_GP1_RLAST ),
.MAXIGP1RRESP (M_AXI_GP1_RRESP ),
.MAXIGP1RVALID (M_AXI_GP1_RVALID ),
.MAXIGP1WREADY (M_AXI_GP1_WREADY ),
.SAXIACPACLK (S_AXI_ACP_ACLK_temp ),
.SAXIACPARADDR (SAXIACPARADDR_W ),
.SAXIACPARBURST (SAXIACPARBURST_W),
.SAXIACPARCACHE (SAXIACPARCACHE_W),
.SAXIACPARID (S_AXI_ACP_ARID_in ),
.SAXIACPARLEN (SAXIACPARLEN_W ),
.SAXIACPARLOCK (SAXIACPARLOCK_W ),
.SAXIACPARPROT (SAXIACPARPROT_W ),
.SAXIACPARQOS (S_AXI_ACP_ARQOS ),
.SAXIACPARSIZE (SAXIACPARSIZE_W[1:0] ),
.SAXIACPARUSER (SAXIACPARUSER_W ),
.SAXIACPARVALID (SAXIACPARVALID_W),
.SAXIACPAWADDR (SAXIACPAWADDR_W ),
.SAXIACPAWBURST (SAXIACPAWBURST_W),
.SAXIACPAWCACHE (SAXIACPAWCACHE_W),
.SAXIACPAWID (S_AXI_ACP_AWID_in ),
.SAXIACPAWLEN (SAXIACPAWLEN_W ),
.SAXIACPAWLOCK (SAXIACPAWLOCK_W ),
.SAXIACPAWPROT (SAXIACPAWPROT_W ),
.SAXIACPAWQOS (S_AXI_ACP_AWQOS ),
.SAXIACPAWSIZE (SAXIACPAWSIZE_W[1:0] ),
.SAXIACPAWUSER (SAXIACPAWUSER_W ),
.SAXIACPAWVALID (SAXIACPAWVALID_W),
.SAXIACPBREADY (SAXIACPBREADY_W ),
.SAXIACPRREADY (SAXIACPRREADY_W ),
.SAXIACPWDATA (SAXIACPWDATA_W ),
.SAXIACPWID (S_AXI_ACP_WID_in ),
.SAXIACPWLAST (SAXIACPWLAST_W ),
.SAXIACPWSTRB (SAXIACPWSTRB_W ),
.SAXIACPWVALID (SAXIACPWVALID_W ),
.SAXIGP0ACLK (S_AXI_GP0_ACLK_temp ),
.SAXIGP0ARADDR (S_AXI_GP0_ARADDR ),
.SAXIGP0ARBURST (S_AXI_GP0_ARBURST),
.SAXIGP0ARCACHE (S_AXI_GP0_ARCACHE),
.SAXIGP0ARID (S_AXI_GP0_ARID_in ),
.SAXIGP0ARLEN (S_AXI_GP0_ARLEN ),
.SAXIGP0ARLOCK (S_AXI_GP0_ARLOCK ),
.SAXIGP0ARPROT (S_AXI_GP0_ARPROT ),
.SAXIGP0ARQOS (S_AXI_GP0_ARQOS ),
.SAXIGP0ARSIZE (S_AXI_GP0_ARSIZE[1:0] ),
.SAXIGP0ARVALID (S_AXI_GP0_ARVALID),
.SAXIGP0AWADDR (S_AXI_GP0_AWADDR ),
.SAXIGP0AWBURST (S_AXI_GP0_AWBURST),
.SAXIGP0AWCACHE (S_AXI_GP0_AWCACHE),
.SAXIGP0AWID (S_AXI_GP0_AWID_in ),
.SAXIGP0AWLEN (S_AXI_GP0_AWLEN ),
.SAXIGP0AWLOCK (S_AXI_GP0_AWLOCK ),
.SAXIGP0AWPROT (S_AXI_GP0_AWPROT ),
.SAXIGP0AWQOS (S_AXI_GP0_AWQOS ),
.SAXIGP0AWSIZE (S_AXI_GP0_AWSIZE[1:0] ),
.SAXIGP0AWVALID (S_AXI_GP0_AWVALID),
.SAXIGP0BREADY (S_AXI_GP0_BREADY ),
.SAXIGP0RREADY (S_AXI_GP0_RREADY ),
.SAXIGP0WDATA (S_AXI_GP0_WDATA ),
.SAXIGP0WID (S_AXI_GP0_WID_in ),
.SAXIGP0WLAST (S_AXI_GP0_WLAST ),
.SAXIGP0WSTRB (S_AXI_GP0_WSTRB ),
.SAXIGP0WVALID (S_AXI_GP0_WVALID ),
.SAXIGP1ACLK (S_AXI_GP1_ACLK_temp ),
.SAXIGP1ARADDR (S_AXI_GP1_ARADDR ),
.SAXIGP1ARBURST (S_AXI_GP1_ARBURST),
.SAXIGP1ARCACHE (S_AXI_GP1_ARCACHE),
.SAXIGP1ARID (S_AXI_GP1_ARID_in ),
.SAXIGP1ARLEN (S_AXI_GP1_ARLEN ),
.SAXIGP1ARLOCK (S_AXI_GP1_ARLOCK ),
.SAXIGP1ARPROT (S_AXI_GP1_ARPROT ),
.SAXIGP1ARQOS (S_AXI_GP1_ARQOS ),
.SAXIGP1ARSIZE (S_AXI_GP1_ARSIZE[1:0] ),
.SAXIGP1ARVALID (S_AXI_GP1_ARVALID),
.SAXIGP1AWADDR (S_AXI_GP1_AWADDR ),
.SAXIGP1AWBURST (S_AXI_GP1_AWBURST),
.SAXIGP1AWCACHE (S_AXI_GP1_AWCACHE),
.SAXIGP1AWID (S_AXI_GP1_AWID_in ),
.SAXIGP1AWLEN (S_AXI_GP1_AWLEN ),
.SAXIGP1AWLOCK (S_AXI_GP1_AWLOCK ),
.SAXIGP1AWPROT (S_AXI_GP1_AWPROT ),
.SAXIGP1AWQOS (S_AXI_GP1_AWQOS ),
.SAXIGP1AWSIZE (S_AXI_GP1_AWSIZE[1:0] ),
.SAXIGP1AWVALID (S_AXI_GP1_AWVALID),
.SAXIGP1BREADY (S_AXI_GP1_BREADY ),
.SAXIGP1RREADY (S_AXI_GP1_RREADY ),
.SAXIGP1WDATA (S_AXI_GP1_WDATA ),
.SAXIGP1WID (S_AXI_GP1_WID_in ),
.SAXIGP1WLAST (S_AXI_GP1_WLAST ),
.SAXIGP1WSTRB (S_AXI_GP1_WSTRB ),
.SAXIGP1WVALID (S_AXI_GP1_WVALID ),
.SAXIHP0ACLK (S_AXI_HP0_ACLK_temp ),
.SAXIHP0ARADDR (S_AXI_HP0_ARADDR),
.SAXIHP0ARBURST (S_AXI_HP0_ARBURST),
.SAXIHP0ARCACHE (S_AXI_HP0_ARCACHE),
.SAXIHP0ARID (S_AXI_HP0_ARID_in),
.SAXIHP0ARLEN (S_AXI_HP0_ARLEN),
.SAXIHP0ARLOCK (S_AXI_HP0_ARLOCK),
.SAXIHP0ARPROT (S_AXI_HP0_ARPROT),
.SAXIHP0ARQOS (S_AXI_HP0_ARQOS),
.SAXIHP0ARSIZE (S_AXI_HP0_ARSIZE[1:0]),
.SAXIHP0ARVALID (S_AXI_HP0_ARVALID),
.SAXIHP0AWADDR (S_AXI_HP0_AWADDR),
.SAXIHP0AWBURST (S_AXI_HP0_AWBURST),
.SAXIHP0AWCACHE (S_AXI_HP0_AWCACHE),
.SAXIHP0AWID (S_AXI_HP0_AWID_in),
.SAXIHP0AWLEN (S_AXI_HP0_AWLEN),
.SAXIHP0AWLOCK (S_AXI_HP0_AWLOCK),
.SAXIHP0AWPROT (S_AXI_HP0_AWPROT),
.SAXIHP0AWQOS (S_AXI_HP0_AWQOS),
.SAXIHP0AWSIZE (S_AXI_HP0_AWSIZE[1:0]),
.SAXIHP0AWVALID (S_AXI_HP0_AWVALID),
.SAXIHP0BREADY (S_AXI_HP0_BREADY),
.SAXIHP0RDISSUECAP1EN (S_AXI_HP0_RDISSUECAP1_EN),
.SAXIHP0RREADY (S_AXI_HP0_RREADY),
.SAXIHP0WDATA (S_AXI_HP0_WDATA_in),
.SAXIHP0WID (S_AXI_HP0_WID_in),
.SAXIHP0WLAST (S_AXI_HP0_WLAST),
.SAXIHP0WRISSUECAP1EN (S_AXI_HP0_WRISSUECAP1_EN),
.SAXIHP0WSTRB (S_AXI_HP0_WSTRB_in),
.SAXIHP0WVALID (S_AXI_HP0_WVALID),
.SAXIHP1ACLK (S_AXI_HP1_ACLK_temp),
.SAXIHP1ARADDR (S_AXI_HP1_ARADDR),
.SAXIHP1ARBURST (S_AXI_HP1_ARBURST),
.SAXIHP1ARCACHE (S_AXI_HP1_ARCACHE),
.SAXIHP1ARID (S_AXI_HP1_ARID_in),
.SAXIHP1ARLEN (S_AXI_HP1_ARLEN),
.SAXIHP1ARLOCK (S_AXI_HP1_ARLOCK),
.SAXIHP1ARPROT (S_AXI_HP1_ARPROT),
.SAXIHP1ARQOS (S_AXI_HP1_ARQOS),
.SAXIHP1ARSIZE (S_AXI_HP1_ARSIZE[1:0]),
.SAXIHP1ARVALID (S_AXI_HP1_ARVALID),
.SAXIHP1AWADDR (S_AXI_HP1_AWADDR),
.SAXIHP1AWBURST (S_AXI_HP1_AWBURST),
.SAXIHP1AWCACHE (S_AXI_HP1_AWCACHE),
.SAXIHP1AWID (S_AXI_HP1_AWID_in),
.SAXIHP1AWLEN (S_AXI_HP1_AWLEN),
.SAXIHP1AWLOCK (S_AXI_HP1_AWLOCK),
.SAXIHP1AWPROT (S_AXI_HP1_AWPROT),
.SAXIHP1AWQOS (S_AXI_HP1_AWQOS),
.SAXIHP1AWSIZE (S_AXI_HP1_AWSIZE[1:0]),
.SAXIHP1AWVALID (S_AXI_HP1_AWVALID),
.SAXIHP1BREADY (S_AXI_HP1_BREADY),
.SAXIHP1RDISSUECAP1EN (S_AXI_HP1_RDISSUECAP1_EN),
.SAXIHP1RREADY (S_AXI_HP1_RREADY),
.SAXIHP1WDATA (S_AXI_HP1_WDATA_in),
.SAXIHP1WID (S_AXI_HP1_WID_in),
.SAXIHP1WLAST (S_AXI_HP1_WLAST),
.SAXIHP1WRISSUECAP1EN (S_AXI_HP1_WRISSUECAP1_EN),
.SAXIHP1WSTRB (S_AXI_HP1_WSTRB_in),
.SAXIHP1WVALID (S_AXI_HP1_WVALID),
.SAXIHP2ACLK (S_AXI_HP2_ACLK_temp),
.SAXIHP2ARADDR (S_AXI_HP2_ARADDR),
.SAXIHP2ARBURST (S_AXI_HP2_ARBURST),
.SAXIHP2ARCACHE (S_AXI_HP2_ARCACHE),
.SAXIHP2ARID (S_AXI_HP2_ARID_in),
.SAXIHP2ARLEN (S_AXI_HP2_ARLEN),
.SAXIHP2ARLOCK (S_AXI_HP2_ARLOCK),
.SAXIHP2ARPROT (S_AXI_HP2_ARPROT),
.SAXIHP2ARQOS (S_AXI_HP2_ARQOS),
.SAXIHP2ARSIZE (S_AXI_HP2_ARSIZE[1:0]),
.SAXIHP2ARVALID (S_AXI_HP2_ARVALID),
.SAXIHP2AWADDR (S_AXI_HP2_AWADDR),
.SAXIHP2AWBURST (S_AXI_HP2_AWBURST),
.SAXIHP2AWCACHE (S_AXI_HP2_AWCACHE),
.SAXIHP2AWID (S_AXI_HP2_AWID_in),
.SAXIHP2AWLEN (S_AXI_HP2_AWLEN),
.SAXIHP2AWLOCK (S_AXI_HP2_AWLOCK),
.SAXIHP2AWPROT (S_AXI_HP2_AWPROT),
.SAXIHP2AWQOS (S_AXI_HP2_AWQOS),
.SAXIHP2AWSIZE (S_AXI_HP2_AWSIZE[1:0]),
.SAXIHP2AWVALID (S_AXI_HP2_AWVALID),
.SAXIHP2BREADY (S_AXI_HP2_BREADY),
.SAXIHP2RDISSUECAP1EN (S_AXI_HP2_RDISSUECAP1_EN),
.SAXIHP2RREADY (S_AXI_HP2_RREADY),
.SAXIHP2WDATA (S_AXI_HP2_WDATA_in),
.SAXIHP2WID (S_AXI_HP2_WID_in),
.SAXIHP2WLAST (S_AXI_HP2_WLAST),
.SAXIHP2WRISSUECAP1EN (S_AXI_HP2_WRISSUECAP1_EN),
.SAXIHP2WSTRB (S_AXI_HP2_WSTRB_in),
.SAXIHP2WVALID (S_AXI_HP2_WVALID),
.SAXIHP3ACLK (S_AXI_HP3_ACLK_temp),
.SAXIHP3ARADDR (S_AXI_HP3_ARADDR ),
.SAXIHP3ARBURST (S_AXI_HP3_ARBURST),
.SAXIHP3ARCACHE (S_AXI_HP3_ARCACHE),
.SAXIHP3ARID (S_AXI_HP3_ARID_in ),
.SAXIHP3ARLEN (S_AXI_HP3_ARLEN),
.SAXIHP3ARLOCK (S_AXI_HP3_ARLOCK),
.SAXIHP3ARPROT (S_AXI_HP3_ARPROT),
.SAXIHP3ARQOS (S_AXI_HP3_ARQOS),
.SAXIHP3ARSIZE (S_AXI_HP3_ARSIZE[1:0]),
.SAXIHP3ARVALID (S_AXI_HP3_ARVALID),
.SAXIHP3AWADDR (S_AXI_HP3_AWADDR),
.SAXIHP3AWBURST (S_AXI_HP3_AWBURST),
.SAXIHP3AWCACHE (S_AXI_HP3_AWCACHE),
.SAXIHP3AWID (S_AXI_HP3_AWID_in),
.SAXIHP3AWLEN (S_AXI_HP3_AWLEN),
.SAXIHP3AWLOCK (S_AXI_HP3_AWLOCK),
.SAXIHP3AWPROT (S_AXI_HP3_AWPROT),
.SAXIHP3AWQOS (S_AXI_HP3_AWQOS),
.SAXIHP3AWSIZE (S_AXI_HP3_AWSIZE[1:0]),
.SAXIHP3AWVALID (S_AXI_HP3_AWVALID),
.SAXIHP3BREADY (S_AXI_HP3_BREADY),
.SAXIHP3RDISSUECAP1EN (S_AXI_HP3_RDISSUECAP1_EN),
.SAXIHP3RREADY (S_AXI_HP3_RREADY),
.SAXIHP3WDATA (S_AXI_HP3_WDATA_in),
.SAXIHP3WID (S_AXI_HP3_WID_in),
.SAXIHP3WLAST (S_AXI_HP3_WLAST),
.SAXIHP3WRISSUECAP1EN (S_AXI_HP3_WRISSUECAP1_EN),
.SAXIHP3WSTRB (S_AXI_HP3_WSTRB_in),
.SAXIHP3WVALID (S_AXI_HP3_WVALID),
.DDRA (buffered_DDR_Addr),
.DDRBA (buffered_DDR_BankAddr),
.DDRCASB (buffered_DDR_CAS_n),
.DDRCKE (buffered_DDR_CKE),
.DDRCKN (buffered_DDR_Clk_n),
.DDRCKP (buffered_DDR_Clk),
.DDRCSB (buffered_DDR_CS_n),
.DDRDM (buffered_DDR_DM),
.DDRDQ (buffered_DDR_DQ),
.DDRDQSN (buffered_DDR_DQS_n),
.DDRDQSP (buffered_DDR_DQS),
.DDRDRSTB (buffered_DDR_DRSTB),
.DDRODT (buffered_DDR_ODT),
.DDRRASB (buffered_DDR_RAS_n),
.DDRVRN (buffered_DDR_VRN),
.DDRVRP (buffered_DDR_VRP),
.DDRWEB (buffered_DDR_WEB),
.MIO ({buffered_MIO[31:30],dummy[21:20],buffered_MIO[29:28],dummy[19:12],buffered_MIO[27:16],dummy[11:0],buffered_MIO[15:0]}),
.PSCLK (buffered_PS_CLK),
.PSPORB (buffered_PS_PORB),
.PSSRSTB (buffered_PS_SRSTB)
);
end
else begin
PS7 PS7_i (
.DMA0DATYPE (DMA0_DATYPE ),
.DMA0DAVALID (DMA0_DAVALID),
.DMA0DRREADY (DMA0_DRREADY),
.DMA0RSTN (DMA0_RSTN ),
.DMA1DATYPE (DMA1_DATYPE ),
.DMA1DAVALID (DMA1_DAVALID),
.DMA1DRREADY (DMA1_DRREADY),
.DMA1RSTN (DMA1_RSTN ),
.DMA2DATYPE (DMA2_DATYPE ),
.DMA2DAVALID (DMA2_DAVALID),
.DMA2DRREADY (DMA2_DRREADY),
.DMA2RSTN (DMA2_RSTN ),
.DMA3DATYPE (DMA3_DATYPE ),
.DMA3DAVALID (DMA3_DAVALID),
.DMA3DRREADY (DMA3_DRREADY),
.DMA3RSTN (DMA3_RSTN ),
.EMIOCAN0PHYTX (CAN0_PHY_TX ),
.EMIOCAN1PHYTX (CAN1_PHY_TX ),
.EMIOENET0GMIITXD (ENET0_GMII_TXD_i), // (ENET0_GMII_TXD_i ),
.EMIOENET0GMIITXEN (ENET0_GMII_TX_EN_i), // (ENET0_GMII_TX_EN_i),
.EMIOENET0GMIITXER (ENET0_GMII_TX_ER_i), // (ENET0_GMII_TX_ER_i),
.EMIOENET0MDIOMDC (ENET0_MDIO_MDC),
.EMIOENET0MDIOO (ENET0_MDIO_O ),
.EMIOENET0MDIOTN (ENET0_MDIO_T_n ),
.EMIOENET0PTPDELAYREQRX (ENET0_PTP_DELAY_REQ_RX),
.EMIOENET0PTPDELAYREQTX (ENET0_PTP_DELAY_REQ_TX),
.EMIOENET0PTPPDELAYREQRX (ENET0_PTP_PDELAY_REQ_RX),
.EMIOENET0PTPPDELAYREQTX (ENET0_PTP_PDELAY_REQ_TX),
.EMIOENET0PTPPDELAYRESPRX(ENET0_PTP_PDELAY_RESP_RX),
.EMIOENET0PTPPDELAYRESPTX(ENET0_PTP_PDELAY_RESP_TX),
.EMIOENET0PTPSYNCFRAMERX (ENET0_PTP_SYNC_FRAME_RX),
.EMIOENET0PTPSYNCFRAMETX (ENET0_PTP_SYNC_FRAME_TX),
.EMIOENET0SOFRX (ENET0_SOF_RX),
.EMIOENET0SOFTX (ENET0_SOF_TX),
.EMIOENET1GMIITXD (ENET1_GMII_TXD_i), // (ENET1_GMII_TXD_i),
.EMIOENET1GMIITXEN (ENET1_GMII_TX_EN_i), // (ENET1_GMII_TX_EN_i),
.EMIOENET1GMIITXER (ENET1_GMII_TX_ER_i), // (ENET1_GMII_TX_ER_i),
.EMIOENET1MDIOMDC (ENET1_MDIO_MDC),
.EMIOENET1MDIOO (ENET1_MDIO_O ),
.EMIOENET1MDIOTN (ENET1_MDIO_T_n),
.EMIOENET1PTPDELAYREQRX (ENET1_PTP_DELAY_REQ_RX),
.EMIOENET1PTPDELAYREQTX (ENET1_PTP_DELAY_REQ_TX),
.EMIOENET1PTPPDELAYREQRX (ENET1_PTP_PDELAY_REQ_RX),
.EMIOENET1PTPPDELAYREQTX (ENET1_PTP_PDELAY_REQ_TX),
.EMIOENET1PTPPDELAYRESPRX(ENET1_PTP_PDELAY_RESP_RX),
.EMIOENET1PTPPDELAYRESPTX(ENET1_PTP_PDELAY_RESP_TX),
.EMIOENET1PTPSYNCFRAMERX (ENET1_PTP_SYNC_FRAME_RX),
.EMIOENET1PTPSYNCFRAMETX (ENET1_PTP_SYNC_FRAME_TX),
.EMIOENET1SOFRX (ENET1_SOF_RX),
.EMIOENET1SOFTX (ENET1_SOF_TX),
.EMIOGPIOO (gpio_out),
.EMIOGPIOTN (gpio_out_t_n),
.EMIOI2C0SCLO (I2C0_SCL_O),
.EMIOI2C0SCLTN (I2C0_SCL_T_n),
.EMIOI2C0SDAO (I2C0_SDA_O),
.EMIOI2C0SDATN (I2C0_SDA_T_n),
.EMIOI2C1SCLO (I2C1_SCL_O),
.EMIOI2C1SCLTN (I2C1_SCL_T_n),
.EMIOI2C1SDAO (I2C1_SDA_O),
.EMIOI2C1SDATN (I2C1_SDA_T_n),
.EMIOPJTAGTDO (PJTAG_TDO_O),
.EMIOPJTAGTDTN (PJTAG_TDO_T_n),
.EMIOSDIO0BUSPOW (SDIO0_BUSPOW),
.EMIOSDIO0CLK (SDIO0_CLK ),
.EMIOSDIO0CMDO (SDIO0_CMD_O ),
.EMIOSDIO0CMDTN (SDIO0_CMD_T_n ),
.EMIOSDIO0DATAO (SDIO0_DATA_O),
.EMIOSDIO0DATATN (SDIO0_DATA_T_n),
.EMIOSDIO0LED (SDIO0_LED),
.EMIOSDIO1BUSPOW (SDIO1_BUSPOW),
.EMIOSDIO1CLK (SDIO1_CLK ),
.EMIOSDIO1CMDO (SDIO1_CMD_O ),
.EMIOSDIO1CMDTN (SDIO1_CMD_T_n ),
.EMIOSDIO1DATAO (SDIO1_DATA_O),
.EMIOSDIO1DATATN (SDIO1_DATA_T_n),
.EMIOSDIO1LED (SDIO1_LED),
.EMIOSPI0MO (SPI0_MOSI_O),
.EMIOSPI0MOTN (SPI0_MOSI_T_n),
.EMIOSPI0SCLKO (SPI0_SCLK_O),
.EMIOSPI0SCLKTN (SPI0_SCLK_T_n),
.EMIOSPI0SO (SPI0_MISO_O),
.EMIOSPI0STN (SPI0_MISO_T_n),
.EMIOSPI0SSON ({SPI0_SS2_O,SPI0_SS1_O,SPI0_SS_O}),
.EMIOSPI0SSNTN (SPI0_SS_T_n),
.EMIOSPI1MO (SPI1_MOSI_O),
.EMIOSPI1MOTN (SPI1_MOSI_T_n),
.EMIOSPI1SCLKO (SPI1_SCLK_O),
.EMIOSPI1SCLKTN (SPI1_SCLK_T_n),
.EMIOSPI1SO (SPI1_MISO_O),
.EMIOSPI1STN (SPI1_MISO_T_n),
.EMIOSPI1SSON ({SPI1_SS2_O,SPI1_SS1_O,SPI1_SS_O}),
.EMIOSPI1SSNTN (SPI1_SS_T_n),
.EMIOTRACECTL (TRACE_CTL_i),
.EMIOTRACEDATA (TRACE_DATA_i),
.EMIOTTC0WAVEO ({TTC0_WAVE2_OUT,TTC0_WAVE1_OUT,TTC0_WAVE0_OUT}),
.EMIOTTC1WAVEO ({TTC1_WAVE2_OUT,TTC1_WAVE1_OUT,TTC1_WAVE0_OUT}),
.EMIOUART0DTRN (UART0_DTRN),
.EMIOUART0RTSN (UART0_RTSN),
.EMIOUART0TX (UART0_TX ),
.EMIOUART1DTRN (UART1_DTRN),
.EMIOUART1RTSN (UART1_RTSN),
.EMIOUART1TX (UART1_TX ),
.EMIOUSB0PORTINDCTL (USB0_PORT_INDCTL),
.EMIOUSB0VBUSPWRSELECT (USB0_VBUS_PWRSELECT),
.EMIOUSB1PORTINDCTL (USB1_PORT_INDCTL),
.EMIOUSB1VBUSPWRSELECT (USB1_VBUS_PWRSELECT),
.EMIOWDTRSTO (WDT_RST_OUT),
.EVENTEVENTO (EVENT_EVENTO),
.EVENTSTANDBYWFE (EVENT_STANDBYWFE),
.EVENTSTANDBYWFI (EVENT_STANDBYWFI),
.FCLKCLK (FCLK_CLK_unbuffered),
.FCLKRESETN ({FCLK_RESET3_N,FCLK_RESET2_N,FCLK_RESET1_N,FCLK_RESET0_N}),
.EMIOSDIO0BUSVOLT (SDIO0_BUSVOLT),
.EMIOSDIO1BUSVOLT (SDIO1_BUSVOLT),
.FTMTF2PTRIGACK ({FTMT_F2P_TRIGACK_3,FTMT_F2P_TRIGACK_2,FTMT_F2P_TRIGACK_1,FTMT_F2P_TRIGACK_0}),
.FTMTP2FDEBUG (FTMT_P2F_DEBUG ),
.FTMTP2FTRIG ({FTMT_P2F_TRIG_3,FTMT_P2F_TRIG_2,FTMT_P2F_TRIG_1,FTMT_P2F_TRIG_0}),
.IRQP2F ({IRQ_P2F_DMAC_ABORT, IRQ_P2F_DMAC7, IRQ_P2F_DMAC6, IRQ_P2F_DMAC5, IRQ_P2F_DMAC4, IRQ_P2F_DMAC3, IRQ_P2F_DMAC2, IRQ_P2F_DMAC1, IRQ_P2F_DMAC0, IRQ_P2F_SMC, IRQ_P2F_QSPI, IRQ_P2F_CTI, IRQ_P2F_GPIO, IRQ_P2F_USB0, IRQ_P2F_ENET0, IRQ_P2F_ENET_WAKE0, IRQ_P2F_SDIO0, IRQ_P2F_I2C0, IRQ_P2F_SPI0, IRQ_P2F_UART0, IRQ_P2F_CAN0, IRQ_P2F_USB1, IRQ_P2F_ENET1, IRQ_P2F_ENET_WAKE1, IRQ_P2F_SDIO1, IRQ_P2F_I2C1, IRQ_P2F_SPI1, IRQ_P2F_UART1, IRQ_P2F_CAN1}),
.MAXIGP0ARADDR (M_AXI_GP0_ARADDR),
.MAXIGP0ARBURST (M_AXI_GP0_ARBURST),
.MAXIGP0ARCACHE (M_AXI_GP0_ARCACHE_t),
.MAXIGP0ARESETN (M_AXI_GP0_ARESETN),
.MAXIGP0ARID (M_AXI_GP0_ARID_FULL ),
.MAXIGP0ARLEN (M_AXI_GP0_ARLEN ),
.MAXIGP0ARLOCK (M_AXI_GP0_ARLOCK ),
.MAXIGP0ARPROT (M_AXI_GP0_ARPROT ),
.MAXIGP0ARQOS (M_AXI_GP0_ARQOS ),
.MAXIGP0ARSIZE (M_AXI_GP0_ARSIZE_i ),
.MAXIGP0ARVALID (M_AXI_GP0_ARVALID),
.MAXIGP0AWADDR (M_AXI_GP0_AWADDR ),
.MAXIGP0AWBURST (M_AXI_GP0_AWBURST),
.MAXIGP0AWCACHE (M_AXI_GP0_AWCACHE_t),
.MAXIGP0AWID (M_AXI_GP0_AWID_FULL ),
.MAXIGP0AWLEN (M_AXI_GP0_AWLEN ),
.MAXIGP0AWLOCK (M_AXI_GP0_AWLOCK ),
.MAXIGP0AWPROT (M_AXI_GP0_AWPROT ),
.MAXIGP0AWQOS (M_AXI_GP0_AWQOS ),
.MAXIGP0AWSIZE (M_AXI_GP0_AWSIZE_i ),
.MAXIGP0AWVALID (M_AXI_GP0_AWVALID),
.MAXIGP0BREADY (M_AXI_GP0_BREADY ),
.MAXIGP0RREADY (M_AXI_GP0_RREADY ),
.MAXIGP0WDATA (M_AXI_GP0_WDATA ),
.MAXIGP0WID (M_AXI_GP0_WID_FULL ),
.MAXIGP0WLAST (M_AXI_GP0_WLAST ),
.MAXIGP0WSTRB (M_AXI_GP0_WSTRB ),
.MAXIGP0WVALID (M_AXI_GP0_WVALID ),
.MAXIGP1ARADDR (M_AXI_GP1_ARADDR ),
.MAXIGP1ARBURST (M_AXI_GP1_ARBURST),
.MAXIGP1ARCACHE (M_AXI_GP1_ARCACHE_t),
.MAXIGP1ARESETN (M_AXI_GP1_ARESETN),
.MAXIGP1ARID (M_AXI_GP1_ARID_FULL ),
.MAXIGP1ARLEN (M_AXI_GP1_ARLEN ),
.MAXIGP1ARLOCK (M_AXI_GP1_ARLOCK ),
.MAXIGP1ARPROT (M_AXI_GP1_ARPROT ),
.MAXIGP1ARQOS (M_AXI_GP1_ARQOS ),
.MAXIGP1ARSIZE (M_AXI_GP1_ARSIZE_i ),
.MAXIGP1ARVALID (M_AXI_GP1_ARVALID),
.MAXIGP1AWADDR (M_AXI_GP1_AWADDR ),
.MAXIGP1AWBURST (M_AXI_GP1_AWBURST),
.MAXIGP1AWCACHE (M_AXI_GP1_AWCACHE_t),
.MAXIGP1AWID (M_AXI_GP1_AWID_FULL ),
.MAXIGP1AWLEN (M_AXI_GP1_AWLEN ),
.MAXIGP1AWLOCK (M_AXI_GP1_AWLOCK ),
.MAXIGP1AWPROT (M_AXI_GP1_AWPROT ),
.MAXIGP1AWQOS (M_AXI_GP1_AWQOS ),
.MAXIGP1AWSIZE (M_AXI_GP1_AWSIZE_i ),
.MAXIGP1AWVALID (M_AXI_GP1_AWVALID),
.MAXIGP1BREADY (M_AXI_GP1_BREADY ),
.MAXIGP1RREADY (M_AXI_GP1_RREADY ),
.MAXIGP1WDATA (M_AXI_GP1_WDATA ),
.MAXIGP1WID (M_AXI_GP1_WID_FULL ),
.MAXIGP1WLAST (M_AXI_GP1_WLAST ),
.MAXIGP1WSTRB (M_AXI_GP1_WSTRB ),
.MAXIGP1WVALID (M_AXI_GP1_WVALID ),
.SAXIACPARESETN (S_AXI_ACP_ARESETN),
.SAXIACPARREADY (SAXIACPARREADY_W),
.SAXIACPAWREADY (SAXIACPAWREADY_W),
.SAXIACPBID (S_AXI_ACP_BID_out ),
.SAXIACPBRESP (SAXIACPBRESP_W ),
.SAXIACPBVALID (SAXIACPBVALID_W ),
.SAXIACPRDATA (SAXIACPRDATA_W ),
.SAXIACPRID (S_AXI_ACP_RID_out),
.SAXIACPRLAST (SAXIACPRLAST_W ),
.SAXIACPRRESP (SAXIACPRRESP_W ),
.SAXIACPRVALID (SAXIACPRVALID_W ),
.SAXIACPWREADY (SAXIACPWREADY_W ),
.SAXIGP0ARESETN (S_AXI_GP0_ARESETN),
.SAXIGP0ARREADY (S_AXI_GP0_ARREADY),
.SAXIGP0AWREADY (S_AXI_GP0_AWREADY),
.SAXIGP0BID (S_AXI_GP0_BID_out),
.SAXIGP0BRESP (S_AXI_GP0_BRESP ),
.SAXIGP0BVALID (S_AXI_GP0_BVALID ),
.SAXIGP0RDATA (S_AXI_GP0_RDATA ),
.SAXIGP0RID (S_AXI_GP0_RID_out ),
.SAXIGP0RLAST (S_AXI_GP0_RLAST ),
.SAXIGP0RRESP (S_AXI_GP0_RRESP ),
.SAXIGP0RVALID (S_AXI_GP0_RVALID ),
.SAXIGP0WREADY (S_AXI_GP0_WREADY ),
.SAXIGP1ARESETN (S_AXI_GP1_ARESETN),
.SAXIGP1ARREADY (S_AXI_GP1_ARREADY),
.SAXIGP1AWREADY (S_AXI_GP1_AWREADY),
.SAXIGP1BID (S_AXI_GP1_BID_out ),
.SAXIGP1BRESP (S_AXI_GP1_BRESP ),
.SAXIGP1BVALID (S_AXI_GP1_BVALID ),
.SAXIGP1RDATA (S_AXI_GP1_RDATA ),
.SAXIGP1RID (S_AXI_GP1_RID_out ),
.SAXIGP1RLAST (S_AXI_GP1_RLAST ),
.SAXIGP1RRESP (S_AXI_GP1_RRESP ),
.SAXIGP1RVALID (S_AXI_GP1_RVALID ),
.SAXIGP1WREADY (S_AXI_GP1_WREADY ),
.SAXIHP0ARESETN (S_AXI_HP0_ARESETN),
.SAXIHP0ARREADY (S_AXI_HP0_ARREADY),
.SAXIHP0AWREADY (S_AXI_HP0_AWREADY),
.SAXIHP0BID (S_AXI_HP0_BID_out ),
.SAXIHP0BRESP (S_AXI_HP0_BRESP ),
.SAXIHP0BVALID (S_AXI_HP0_BVALID ),
.SAXIHP0RACOUNT (S_AXI_HP0_RACOUNT),
.SAXIHP0RCOUNT (S_AXI_HP0_RCOUNT),
.SAXIHP0RDATA (S_AXI_HP0_RDATA_out),
.SAXIHP0RID (S_AXI_HP0_RID_out ),
.SAXIHP0RLAST (S_AXI_HP0_RLAST),
.SAXIHP0RRESP (S_AXI_HP0_RRESP),
.SAXIHP0RVALID (S_AXI_HP0_RVALID),
.SAXIHP0WCOUNT (S_AXI_HP0_WCOUNT),
.SAXIHP0WACOUNT (S_AXI_HP0_WACOUNT),
.SAXIHP0WREADY (S_AXI_HP0_WREADY),
.SAXIHP1ARESETN (S_AXI_HP1_ARESETN),
.SAXIHP1ARREADY (S_AXI_HP1_ARREADY),
.SAXIHP1AWREADY (S_AXI_HP1_AWREADY),
.SAXIHP1BID (S_AXI_HP1_BID_out ),
.SAXIHP1BRESP (S_AXI_HP1_BRESP ),
.SAXIHP1BVALID (S_AXI_HP1_BVALID ),
.SAXIHP1RACOUNT (S_AXI_HP1_RACOUNT ),
.SAXIHP1RCOUNT (S_AXI_HP1_RCOUNT ),
.SAXIHP1RDATA (S_AXI_HP1_RDATA_out),
.SAXIHP1RID (S_AXI_HP1_RID_out ),
.SAXIHP1RLAST (S_AXI_HP1_RLAST ),
.SAXIHP1RRESP (S_AXI_HP1_RRESP ),
.SAXIHP1RVALID (S_AXI_HP1_RVALID),
.SAXIHP1WACOUNT (S_AXI_HP1_WACOUNT),
.SAXIHP1WCOUNT (S_AXI_HP1_WCOUNT),
.SAXIHP1WREADY (S_AXI_HP1_WREADY),
.SAXIHP2ARESETN (S_AXI_HP2_ARESETN),
.SAXIHP2ARREADY (S_AXI_HP2_ARREADY),
.SAXIHP2AWREADY (S_AXI_HP2_AWREADY),
.SAXIHP2BID (S_AXI_HP2_BID_out ),
.SAXIHP2BRESP (S_AXI_HP2_BRESP),
.SAXIHP2BVALID (S_AXI_HP2_BVALID),
.SAXIHP2RACOUNT (S_AXI_HP2_RACOUNT),
.SAXIHP2RCOUNT (S_AXI_HP2_RCOUNT),
.SAXIHP2RDATA (S_AXI_HP2_RDATA_out),
.SAXIHP2RID (S_AXI_HP2_RID_out ),
.SAXIHP2RLAST (S_AXI_HP2_RLAST),
.SAXIHP2RRESP (S_AXI_HP2_RRESP),
.SAXIHP2RVALID (S_AXI_HP2_RVALID),
.SAXIHP2WACOUNT (S_AXI_HP2_WACOUNT),
.SAXIHP2WCOUNT (S_AXI_HP2_WCOUNT),
.SAXIHP2WREADY (S_AXI_HP2_WREADY),
.SAXIHP3ARESETN (S_AXI_HP3_ARESETN),
.SAXIHP3ARREADY (S_AXI_HP3_ARREADY),
.SAXIHP3AWREADY (S_AXI_HP3_AWREADY),
.SAXIHP3BID (S_AXI_HP3_BID_out),
.SAXIHP3BRESP (S_AXI_HP3_BRESP),
.SAXIHP3BVALID (S_AXI_HP3_BVALID),
.SAXIHP3RACOUNT (S_AXI_HP3_RACOUNT),
.SAXIHP3RCOUNT (S_AXI_HP3_RCOUNT),
.SAXIHP3RDATA (S_AXI_HP3_RDATA_out),
.SAXIHP3RID (S_AXI_HP3_RID_out),
.SAXIHP3RLAST (S_AXI_HP3_RLAST),
.SAXIHP3RRESP (S_AXI_HP3_RRESP),
.SAXIHP3RVALID (S_AXI_HP3_RVALID),
.SAXIHP3WCOUNT (S_AXI_HP3_WCOUNT),
.SAXIHP3WACOUNT (S_AXI_HP3_WACOUNT),
.SAXIHP3WREADY (S_AXI_HP3_WREADY),
.DDRARB (DDR_ARB),
.DMA0ACLK (DMA0_ACLK ),
.DMA0DAREADY (DMA0_DAREADY),
.DMA0DRLAST (DMA0_DRLAST ),
.DMA0DRTYPE (DMA0_DRTYPE),
.DMA0DRVALID (DMA0_DRVALID),
.DMA1ACLK (DMA1_ACLK ),
.DMA1DAREADY (DMA1_DAREADY),
.DMA1DRLAST (DMA1_DRLAST ),
.DMA1DRTYPE (DMA1_DRTYPE),
.DMA1DRVALID (DMA1_DRVALID),
.DMA2ACLK (DMA2_ACLK ),
.DMA2DAREADY (DMA2_DAREADY),
.DMA2DRLAST (DMA2_DRLAST ),
.DMA2DRTYPE (DMA2_DRTYPE),
.DMA2DRVALID (DMA2_DRVALID),
.DMA3ACLK (DMA3_ACLK ),
.DMA3DAREADY (DMA3_DAREADY),
.DMA3DRLAST (DMA3_DRLAST ),
.DMA3DRTYPE (DMA3_DRTYPE),
.DMA3DRVALID (DMA3_DRVALID),
.EMIOCAN0PHYRX (CAN0_PHY_RX),
.EMIOCAN1PHYRX (CAN1_PHY_RX),
.EMIOENET0EXTINTIN (ENET0_EXT_INTIN),
.EMIOENET0GMIICOL (ENET0_GMII_COL_i),
.EMIOENET0GMIICRS (ENET0_GMII_CRS_i),
.EMIOENET0GMIIRXCLK (ENET0_GMII_RX_CLK),
.EMIOENET0GMIIRXD (ENET0_GMII_RXD_i),
.EMIOENET0GMIIRXDV (ENET0_GMII_RX_DV_i),
.EMIOENET0GMIIRXER (ENET0_GMII_RX_ER_i),
.EMIOENET0GMIITXCLK (ENET0_GMII_TX_CLK),
.EMIOENET0MDIOI (ENET0_MDIO_I),
.EMIOENET1EXTINTIN (ENET1_EXT_INTIN),
.EMIOENET1GMIICOL (ENET1_GMII_COL_i),
.EMIOENET1GMIICRS (ENET1_GMII_CRS_i),
.EMIOENET1GMIIRXCLK (ENET1_GMII_RX_CLK),
.EMIOENET1GMIIRXD (ENET1_GMII_RXD_i),
.EMIOENET1GMIIRXDV (ENET1_GMII_RX_DV_i),
.EMIOENET1GMIIRXER (ENET1_GMII_RX_ER_i),
.EMIOENET1GMIITXCLK (ENET1_GMII_TX_CLK),
.EMIOENET1MDIOI (ENET1_MDIO_I),
.EMIOGPIOI (gpio_in63_0 ),
.EMIOI2C0SCLI (I2C0_SCL_I),
.EMIOI2C0SDAI (I2C0_SDA_I),
.EMIOI2C1SCLI (I2C1_SCL_I),
.EMIOI2C1SDAI (I2C1_SDA_I),
.EMIOPJTAGTCK (PJTAG_TCK),
.EMIOPJTAGTDI (PJTAG_TDI),
.EMIOPJTAGTMS (PJTAG_TMS),
.EMIOSDIO0CDN (SDIO0_CDN),
.EMIOSDIO0CLKFB (SDIO0_CLK_FB ),
.EMIOSDIO0CMDI (SDIO0_CMD_I ),
.EMIOSDIO0DATAI (SDIO0_DATA_I ),
.EMIOSDIO0WP (SDIO0_WP),
.EMIOSDIO1CDN (SDIO1_CDN),
.EMIOSDIO1CLKFB (SDIO1_CLK_FB ),
.EMIOSDIO1CMDI (SDIO1_CMD_I ),
.EMIOSDIO1DATAI (SDIO1_DATA_I ),
.EMIOSDIO1WP (SDIO1_WP),
.EMIOSPI0MI (SPI0_MISO_I),
.EMIOSPI0SCLKI (SPI0_SCLK_I),
.EMIOSPI0SI (SPI0_MOSI_I),
.EMIOSPI0SSIN (SPI0_SS_I),
.EMIOSPI1MI (SPI1_MISO_I),
.EMIOSPI1SCLKI (SPI1_SCLK_I),
.EMIOSPI1SI (SPI1_MOSI_I),
.EMIOSPI1SSIN (SPI1_SS_I),
.EMIOSRAMINTIN (SRAM_INTIN),
.EMIOTRACECLK (TRACE_CLK),
.EMIOTTC0CLKI ({TTC0_CLK2_IN, TTC0_CLK1_IN, TTC0_CLK0_IN}),
.EMIOTTC1CLKI ({TTC1_CLK2_IN, TTC1_CLK1_IN, TTC1_CLK0_IN}),
.EMIOUART0CTSN (UART0_CTSN),
.EMIOUART0DCDN (UART0_DCDN),
.EMIOUART0DSRN (UART0_DSRN),
.EMIOUART0RIN (UART0_RIN ),
.EMIOUART0RX (UART0_RX ),
.EMIOUART1CTSN (UART1_CTSN),
.EMIOUART1DCDN (UART1_DCDN),
.EMIOUART1DSRN (UART1_DSRN),
.EMIOUART1RIN (UART1_RIN ),
.EMIOUART1RX (UART1_RX ),
.EMIOUSB0VBUSPWRFAULT (USB0_VBUS_PWRFAULT),
.EMIOUSB1VBUSPWRFAULT (USB1_VBUS_PWRFAULT),
.EMIOWDTCLKI (WDT_CLK_IN),
.EVENTEVENTI (EVENT_EVENTI),
.FCLKCLKTRIGN (fclk_clktrig_gnd),
.FPGAIDLEN (FPGA_IDLE_N),
.FTMDTRACEINATID (FTMD_TRACEIN_ATID_i),
.FTMDTRACEINCLOCK (FTMD_TRACEIN_CLK),
.FTMDTRACEINDATA (FTMD_TRACEIN_DATA_i),
.FTMDTRACEINVALID (FTMD_TRACEIN_VALID_i),
.FTMTF2PDEBUG (FTMT_F2P_DEBUG ),
.FTMTF2PTRIG ({FTMT_F2P_TRIG_3,FTMT_F2P_TRIG_2,FTMT_F2P_TRIG_1,FTMT_F2P_TRIG_0}),
.FTMTP2FTRIGACK ({FTMT_P2F_TRIGACK_3,FTMT_P2F_TRIGACK_2,FTMT_P2F_TRIGACK_1,FTMT_P2F_TRIGACK_0}),
.IRQF2P (irq_f2p_i),
.MAXIGP0ACLK (M_AXI_GP0_ACLK_temp),
.MAXIGP0ARREADY (M_AXI_GP0_ARREADY),
.MAXIGP0AWREADY (M_AXI_GP0_AWREADY),
.MAXIGP0BID (M_AXI_GP0_BID_FULL ),
.MAXIGP0BRESP (M_AXI_GP0_BRESP ),
.MAXIGP0BVALID (M_AXI_GP0_BVALID ),
.MAXIGP0RDATA (M_AXI_GP0_RDATA ),
.MAXIGP0RID (M_AXI_GP0_RID_FULL ),
.MAXIGP0RLAST (M_AXI_GP0_RLAST ),
.MAXIGP0RRESP (M_AXI_GP0_RRESP ),
.MAXIGP0RVALID (M_AXI_GP0_RVALID ),
.MAXIGP0WREADY (M_AXI_GP0_WREADY ),
.MAXIGP1ACLK (M_AXI_GP1_ACLK_temp ),
.MAXIGP1ARREADY (M_AXI_GP1_ARREADY),
.MAXIGP1AWREADY (M_AXI_GP1_AWREADY),
.MAXIGP1BID (M_AXI_GP1_BID_FULL ),
.MAXIGP1BRESP (M_AXI_GP1_BRESP ),
.MAXIGP1BVALID (M_AXI_GP1_BVALID ),
.MAXIGP1RDATA (M_AXI_GP1_RDATA ),
.MAXIGP1RID (M_AXI_GP1_RID_FULL ),
.MAXIGP1RLAST (M_AXI_GP1_RLAST ),
.MAXIGP1RRESP (M_AXI_GP1_RRESP ),
.MAXIGP1RVALID (M_AXI_GP1_RVALID ),
.MAXIGP1WREADY (M_AXI_GP1_WREADY ),
.SAXIACPACLK (S_AXI_ACP_ACLK_temp),
.SAXIACPARADDR (SAXIACPARADDR_W ),
.SAXIACPARBURST (SAXIACPARBURST_W),
.SAXIACPARCACHE (SAXIACPARCACHE_W),
.SAXIACPARID (S_AXI_ACP_ARID_in ),
.SAXIACPARLEN (SAXIACPARLEN_W ),
.SAXIACPARLOCK (SAXIACPARLOCK_W ),
.SAXIACPARPROT (SAXIACPARPROT_W ),
.SAXIACPARQOS (S_AXI_ACP_ARQOS ),
.SAXIACPARSIZE (SAXIACPARSIZE_W[1:0] ),
.SAXIACPARUSER (SAXIACPARUSER_W ),
.SAXIACPARVALID (SAXIACPARVALID_W),
.SAXIACPAWADDR (SAXIACPAWADDR_W ),
.SAXIACPAWBURST (SAXIACPAWBURST_W),
.SAXIACPAWCACHE (SAXIACPAWCACHE_W),
.SAXIACPAWID (S_AXI_ACP_AWID_in ),
.SAXIACPAWLEN (SAXIACPAWLEN_W ),
.SAXIACPAWLOCK (SAXIACPAWLOCK_W ),
.SAXIACPAWPROT (SAXIACPAWPROT_W ),
.SAXIACPAWQOS (S_AXI_ACP_AWQOS ),
.SAXIACPAWSIZE (SAXIACPAWSIZE_W[1:0] ),
.SAXIACPAWUSER (SAXIACPAWUSER_W ),
.SAXIACPAWVALID (SAXIACPAWVALID_W),
.SAXIACPBREADY (SAXIACPBREADY_W ),
.SAXIACPRREADY (SAXIACPRREADY_W ),
.SAXIACPWDATA (SAXIACPWDATA_W ),
.SAXIACPWID (S_AXI_ACP_WID_in ),
.SAXIACPWLAST (SAXIACPWLAST_W ),
.SAXIACPWSTRB (SAXIACPWSTRB_W ),
.SAXIACPWVALID (SAXIACPWVALID_W ),
.SAXIGP0ACLK (S_AXI_GP0_ACLK_temp ),
.SAXIGP0ARADDR (S_AXI_GP0_ARADDR ),
.SAXIGP0ARBURST (S_AXI_GP0_ARBURST),
.SAXIGP0ARCACHE (S_AXI_GP0_ARCACHE),
.SAXIGP0ARID (S_AXI_GP0_ARID_in ),
.SAXIGP0ARLEN (S_AXI_GP0_ARLEN ),
.SAXIGP0ARLOCK (S_AXI_GP0_ARLOCK ),
.SAXIGP0ARPROT (S_AXI_GP0_ARPROT ),
.SAXIGP0ARQOS (S_AXI_GP0_ARQOS ),
.SAXIGP0ARSIZE (S_AXI_GP0_ARSIZE[1:0] ),
.SAXIGP0ARVALID (S_AXI_GP0_ARVALID),
.SAXIGP0AWADDR (S_AXI_GP0_AWADDR ),
.SAXIGP0AWBURST (S_AXI_GP0_AWBURST),
.SAXIGP0AWCACHE (S_AXI_GP0_AWCACHE),
.SAXIGP0AWID (S_AXI_GP0_AWID_in ),
.SAXIGP0AWLEN (S_AXI_GP0_AWLEN ),
.SAXIGP0AWLOCK (S_AXI_GP0_AWLOCK ),
.SAXIGP0AWPROT (S_AXI_GP0_AWPROT ),
.SAXIGP0AWQOS (S_AXI_GP0_AWQOS ),
.SAXIGP0AWSIZE (S_AXI_GP0_AWSIZE[1:0] ),
.SAXIGP0AWVALID (S_AXI_GP0_AWVALID),
.SAXIGP0BREADY (S_AXI_GP0_BREADY ),
.SAXIGP0RREADY (S_AXI_GP0_RREADY ),
.SAXIGP0WDATA (S_AXI_GP0_WDATA ),
.SAXIGP0WID (S_AXI_GP0_WID_in ),
.SAXIGP0WLAST (S_AXI_GP0_WLAST ),
.SAXIGP0WSTRB (S_AXI_GP0_WSTRB ),
.SAXIGP0WVALID (S_AXI_GP0_WVALID ),
.SAXIGP1ACLK (S_AXI_GP1_ACLK_temp ),
.SAXIGP1ARADDR (S_AXI_GP1_ARADDR ),
.SAXIGP1ARBURST (S_AXI_GP1_ARBURST),
.SAXIGP1ARCACHE (S_AXI_GP1_ARCACHE),
.SAXIGP1ARID (S_AXI_GP1_ARID_in ),
.SAXIGP1ARLEN (S_AXI_GP1_ARLEN ),
.SAXIGP1ARLOCK (S_AXI_GP1_ARLOCK ),
.SAXIGP1ARPROT (S_AXI_GP1_ARPROT ),
.SAXIGP1ARQOS (S_AXI_GP1_ARQOS ),
.SAXIGP1ARSIZE (S_AXI_GP1_ARSIZE[1:0] ),
.SAXIGP1ARVALID (S_AXI_GP1_ARVALID),
.SAXIGP1AWADDR (S_AXI_GP1_AWADDR ),
.SAXIGP1AWBURST (S_AXI_GP1_AWBURST),
.SAXIGP1AWCACHE (S_AXI_GP1_AWCACHE),
.SAXIGP1AWID (S_AXI_GP1_AWID_in ),
.SAXIGP1AWLEN (S_AXI_GP1_AWLEN ),
.SAXIGP1AWLOCK (S_AXI_GP1_AWLOCK ),
.SAXIGP1AWPROT (S_AXI_GP1_AWPROT ),
.SAXIGP1AWQOS (S_AXI_GP1_AWQOS ),
.SAXIGP1AWSIZE (S_AXI_GP1_AWSIZE[1:0] ),
.SAXIGP1AWVALID (S_AXI_GP1_AWVALID),
.SAXIGP1BREADY (S_AXI_GP1_BREADY ),
.SAXIGP1RREADY (S_AXI_GP1_RREADY ),
.SAXIGP1WDATA (S_AXI_GP1_WDATA ),
.SAXIGP1WID (S_AXI_GP1_WID_in ),
.SAXIGP1WLAST (S_AXI_GP1_WLAST ),
.SAXIGP1WSTRB (S_AXI_GP1_WSTRB ),
.SAXIGP1WVALID (S_AXI_GP1_WVALID ),
.SAXIHP0ACLK (S_AXI_HP0_ACLK_temp ),
.SAXIHP0ARADDR (S_AXI_HP0_ARADDR),
.SAXIHP0ARBURST (S_AXI_HP0_ARBURST),
.SAXIHP0ARCACHE (S_AXI_HP0_ARCACHE),
.SAXIHP0ARID (S_AXI_HP0_ARID_in),
.SAXIHP0ARLEN (S_AXI_HP0_ARLEN),
.SAXIHP0ARLOCK (S_AXI_HP0_ARLOCK),
.SAXIHP0ARPROT (S_AXI_HP0_ARPROT),
.SAXIHP0ARQOS (S_AXI_HP0_ARQOS),
.SAXIHP0ARSIZE (S_AXI_HP0_ARSIZE[1:0]),
.SAXIHP0ARVALID (S_AXI_HP0_ARVALID),
.SAXIHP0AWADDR (S_AXI_HP0_AWADDR),
.SAXIHP0AWBURST (S_AXI_HP0_AWBURST),
.SAXIHP0AWCACHE (S_AXI_HP0_AWCACHE),
.SAXIHP0AWID (S_AXI_HP0_AWID_in),
.SAXIHP0AWLEN (S_AXI_HP0_AWLEN),
.SAXIHP0AWLOCK (S_AXI_HP0_AWLOCK),
.SAXIHP0AWPROT (S_AXI_HP0_AWPROT),
.SAXIHP0AWQOS (S_AXI_HP0_AWQOS),
.SAXIHP0AWSIZE (S_AXI_HP0_AWSIZE[1:0]),
.SAXIHP0AWVALID (S_AXI_HP0_AWVALID),
.SAXIHP0BREADY (S_AXI_HP0_BREADY),
.SAXIHP0RDISSUECAP1EN (S_AXI_HP0_RDISSUECAP1_EN),
.SAXIHP0RREADY (S_AXI_HP0_RREADY),
.SAXIHP0WDATA (S_AXI_HP0_WDATA_in),
.SAXIHP0WID (S_AXI_HP0_WID_in),
.SAXIHP0WLAST (S_AXI_HP0_WLAST),
.SAXIHP0WRISSUECAP1EN (S_AXI_HP0_WRISSUECAP1_EN),
.SAXIHP0WSTRB (S_AXI_HP0_WSTRB_in),
.SAXIHP0WVALID (S_AXI_HP0_WVALID),
.SAXIHP1ACLK (S_AXI_HP1_ACLK_temp),
.SAXIHP1ARADDR (S_AXI_HP1_ARADDR),
.SAXIHP1ARBURST (S_AXI_HP1_ARBURST),
.SAXIHP1ARCACHE (S_AXI_HP1_ARCACHE),
.SAXIHP1ARID (S_AXI_HP1_ARID_in),
.SAXIHP1ARLEN (S_AXI_HP1_ARLEN),
.SAXIHP1ARLOCK (S_AXI_HP1_ARLOCK),
.SAXIHP1ARPROT (S_AXI_HP1_ARPROT),
.SAXIHP1ARQOS (S_AXI_HP1_ARQOS),
.SAXIHP1ARSIZE (S_AXI_HP1_ARSIZE[1:0]),
.SAXIHP1ARVALID (S_AXI_HP1_ARVALID),
.SAXIHP1AWADDR (S_AXI_HP1_AWADDR),
.SAXIHP1AWBURST (S_AXI_HP1_AWBURST),
.SAXIHP1AWCACHE (S_AXI_HP1_AWCACHE),
.SAXIHP1AWID (S_AXI_HP1_AWID_in),
.SAXIHP1AWLEN (S_AXI_HP1_AWLEN),
.SAXIHP1AWLOCK (S_AXI_HP1_AWLOCK),
.SAXIHP1AWPROT (S_AXI_HP1_AWPROT),
.SAXIHP1AWQOS (S_AXI_HP1_AWQOS),
.SAXIHP1AWSIZE (S_AXI_HP1_AWSIZE[1:0]),
.SAXIHP1AWVALID (S_AXI_HP1_AWVALID),
.SAXIHP1BREADY (S_AXI_HP1_BREADY),
.SAXIHP1RDISSUECAP1EN (S_AXI_HP1_RDISSUECAP1_EN),
.SAXIHP1RREADY (S_AXI_HP1_RREADY),
.SAXIHP1WDATA (S_AXI_HP1_WDATA_in),
.SAXIHP1WID (S_AXI_HP1_WID_in),
.SAXIHP1WLAST (S_AXI_HP1_WLAST),
.SAXIHP1WRISSUECAP1EN (S_AXI_HP1_WRISSUECAP1_EN),
.SAXIHP1WSTRB (S_AXI_HP1_WSTRB_in),
.SAXIHP1WVALID (S_AXI_HP1_WVALID),
.SAXIHP2ACLK (S_AXI_HP2_ACLK_temp),
.SAXIHP2ARADDR (S_AXI_HP2_ARADDR),
.SAXIHP2ARBURST (S_AXI_HP2_ARBURST),
.SAXIHP2ARCACHE (S_AXI_HP2_ARCACHE),
.SAXIHP2ARID (S_AXI_HP2_ARID_in),
.SAXIHP2ARLEN (S_AXI_HP2_ARLEN),
.SAXIHP2ARLOCK (S_AXI_HP2_ARLOCK),
.SAXIHP2ARPROT (S_AXI_HP2_ARPROT),
.SAXIHP2ARQOS (S_AXI_HP2_ARQOS),
.SAXIHP2ARSIZE (S_AXI_HP2_ARSIZE[1:0]),
.SAXIHP2ARVALID (S_AXI_HP2_ARVALID),
.SAXIHP2AWADDR (S_AXI_HP2_AWADDR),
.SAXIHP2AWBURST (S_AXI_HP2_AWBURST),
.SAXIHP2AWCACHE (S_AXI_HP2_AWCACHE),
.SAXIHP2AWID (S_AXI_HP2_AWID_in),
.SAXIHP2AWLEN (S_AXI_HP2_AWLEN),
.SAXIHP2AWLOCK (S_AXI_HP2_AWLOCK),
.SAXIHP2AWPROT (S_AXI_HP2_AWPROT),
.SAXIHP2AWQOS (S_AXI_HP2_AWQOS),
.SAXIHP2AWSIZE (S_AXI_HP2_AWSIZE[1:0]),
.SAXIHP2AWVALID (S_AXI_HP2_AWVALID),
.SAXIHP2BREADY (S_AXI_HP2_BREADY),
.SAXIHP2RDISSUECAP1EN (S_AXI_HP2_RDISSUECAP1_EN),
.SAXIHP2RREADY (S_AXI_HP2_RREADY),
.SAXIHP2WDATA (S_AXI_HP2_WDATA_in),
.SAXIHP2WID (S_AXI_HP2_WID_in),
.SAXIHP2WLAST (S_AXI_HP2_WLAST),
.SAXIHP2WRISSUECAP1EN (S_AXI_HP2_WRISSUECAP1_EN),
.SAXIHP2WSTRB (S_AXI_HP2_WSTRB_in),
.SAXIHP2WVALID (S_AXI_HP2_WVALID),
.SAXIHP3ACLK (S_AXI_HP3_ACLK_temp),
.SAXIHP3ARADDR (S_AXI_HP3_ARADDR ),
.SAXIHP3ARBURST (S_AXI_HP3_ARBURST),
.SAXIHP3ARCACHE (S_AXI_HP3_ARCACHE),
.SAXIHP3ARID (S_AXI_HP3_ARID_in ),
.SAXIHP3ARLEN (S_AXI_HP3_ARLEN),
.SAXIHP3ARLOCK (S_AXI_HP3_ARLOCK),
.SAXIHP3ARPROT (S_AXI_HP3_ARPROT),
.SAXIHP3ARQOS (S_AXI_HP3_ARQOS),
.SAXIHP3ARSIZE (S_AXI_HP3_ARSIZE[1:0]),
.SAXIHP3ARVALID (S_AXI_HP3_ARVALID),
.SAXIHP3AWADDR (S_AXI_HP3_AWADDR),
.SAXIHP3AWBURST (S_AXI_HP3_AWBURST),
.SAXIHP3AWCACHE (S_AXI_HP3_AWCACHE),
.SAXIHP3AWID (S_AXI_HP3_AWID_in),
.SAXIHP3AWLEN (S_AXI_HP3_AWLEN),
.SAXIHP3AWLOCK (S_AXI_HP3_AWLOCK),
.SAXIHP3AWPROT (S_AXI_HP3_AWPROT),
.SAXIHP3AWQOS (S_AXI_HP3_AWQOS),
.SAXIHP3AWSIZE (S_AXI_HP3_AWSIZE[1:0]),
.SAXIHP3AWVALID (S_AXI_HP3_AWVALID),
.SAXIHP3BREADY (S_AXI_HP3_BREADY),
.SAXIHP3RDISSUECAP1EN (S_AXI_HP3_RDISSUECAP1_EN),
.SAXIHP3RREADY (S_AXI_HP3_RREADY),
.SAXIHP3WDATA (S_AXI_HP3_WDATA_in),
.SAXIHP3WID (S_AXI_HP3_WID_in),
.SAXIHP3WLAST (S_AXI_HP3_WLAST),
.SAXIHP3WRISSUECAP1EN (S_AXI_HP3_WRISSUECAP1_EN),
.SAXIHP3WSTRB (S_AXI_HP3_WSTRB_in),
.SAXIHP3WVALID (S_AXI_HP3_WVALID),
.DDRA (buffered_DDR_Addr),
.DDRBA (buffered_DDR_BankAddr),
.DDRCASB (buffered_DDR_CAS_n),
.DDRCKE (buffered_DDR_CKE),
.DDRCKN (buffered_DDR_Clk_n),
.DDRCKP (buffered_DDR_Clk),
.DDRCSB (buffered_DDR_CS_n),
.DDRDM (buffered_DDR_DM),
.DDRDQ (buffered_DDR_DQ),
.DDRDQSN (buffered_DDR_DQS_n),
.DDRDQSP (buffered_DDR_DQS),
.DDRDRSTB (buffered_DDR_DRSTB),
.DDRODT (buffered_DDR_ODT),
.DDRRASB (buffered_DDR_RAS_n),
.DDRVRN (buffered_DDR_VRN),
.DDRVRP (buffered_DDR_VRP),
.DDRWEB (buffered_DDR_WEB),
.MIO (buffered_MIO),
.PSCLK (buffered_PS_CLK),
.PSPORB (buffered_PS_PORB),
.PSSRSTB (buffered_PS_SRSTB)
);
end
endgenerate
// Generating the AxUSER Values locally when the C_USE_DEFAULT_ACP_USER_VAL is enabled.
// Otherwise a master connected to the ACP port will drive the AxUSER Ports
assign param_aruser = C_USE_DEFAULT_ACP_USER_VAL? C_S_AXI_ACP_ARUSER_VAL : S_AXI_ACP_ARUSER;
assign param_awuser = C_USE_DEFAULT_ACP_USER_VAL? C_S_AXI_ACP_AWUSER_VAL : S_AXI_ACP_AWUSER;
assign SAXIACPARADDR_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARADDR : S_AXI_ACP_ARADDR;
assign SAXIACPARBURST_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARBURST : S_AXI_ACP_ARBURST;
assign SAXIACPARCACHE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARCACHE : S_AXI_ACP_ARCACHE;
assign SAXIACPARLEN_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARLEN : S_AXI_ACP_ARLEN;
assign SAXIACPARLOCK_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARLOCK : S_AXI_ACP_ARLOCK;
assign SAXIACPARPROT_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARPROT : S_AXI_ACP_ARPROT;
assign SAXIACPARSIZE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARSIZE : S_AXI_ACP_ARSIZE;
//assign SAXIACPARUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARUSER : S_AXI_ACP_ARUSER;
assign SAXIACPARUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARUSER : param_aruser;
assign SAXIACPARVALID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARVALID : S_AXI_ACP_ARVALID ;
assign SAXIACPAWADDR_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWADDR : S_AXI_ACP_AWADDR;
assign SAXIACPAWBURST_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWBURST : S_AXI_ACP_AWBURST;
assign SAXIACPAWCACHE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWCACHE : S_AXI_ACP_AWCACHE;
assign SAXIACPAWLEN_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWLEN : S_AXI_ACP_AWLEN;
assign SAXIACPAWLOCK_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWLOCK : S_AXI_ACP_AWLOCK;
assign SAXIACPAWPROT_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWPROT : S_AXI_ACP_AWPROT;
assign SAXIACPAWSIZE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWSIZE : S_AXI_ACP_AWSIZE;
//assign SAXIACPAWUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWUSER : S_AXI_ACP_AWUSER;
assign SAXIACPAWUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWUSER : param_awuser;
assign SAXIACPAWVALID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWVALID : S_AXI_ACP_AWVALID;
assign SAXIACPBREADY_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_BREADY : S_AXI_ACP_BREADY;
assign SAXIACPRREADY_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_RREADY : S_AXI_ACP_RREADY;
assign SAXIACPWDATA_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WDATA : S_AXI_ACP_WDATA;
assign SAXIACPWLAST_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WLAST : S_AXI_ACP_WLAST;
assign SAXIACPWSTRB_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WSTRB : S_AXI_ACP_WSTRB;
assign SAXIACPWVALID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WVALID : S_AXI_ACP_WVALID;
assign SAXIACPARID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARID : S_AXI_ACP_ARID;
assign SAXIACPAWID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWID : S_AXI_ACP_AWID;
assign SAXIACPWID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WID : S_AXI_ACP_WID;
generate
if (C_INCLUDE_ACP_TRANS_CHECK == 0) begin : gen_no_atc
assign S_AXI_ACP_AWREADY = SAXIACPAWREADY_W;
assign S_AXI_ACP_WREADY = SAXIACPWREADY_W;
assign S_AXI_ACP_BID = SAXIACPBID_W;
assign S_AXI_ACP_BRESP = SAXIACPBRESP_W;
assign S_AXI_ACP_BVALID = SAXIACPBVALID_W;
assign S_AXI_ACP_RDATA = SAXIACPRDATA_W;
assign S_AXI_ACP_RID = SAXIACPRID_W;
assign S_AXI_ACP_RLAST = SAXIACPRLAST_W;
assign S_AXI_ACP_RRESP = SAXIACPRRESP_W;
assign S_AXI_ACP_RVALID = SAXIACPRVALID_W;
assign S_AXI_ACP_ARREADY = SAXIACPARREADY_W;
end else begin : gen_atc
processing_system7_v5_5_atc #(
.C_AXI_ID_WIDTH (C_S_AXI_ACP_ID_WIDTH),
.C_AXI_AWUSER_WIDTH (5),
.C_AXI_ARUSER_WIDTH (5)
)
atc_i (
// Global Signals
.ACLK (S_AXI_ACP_ACLK_temp),
.ARESETN (S_AXI_ACP_ARESETN),
// Slave Interface Write Address Ports
.S_AXI_AWID (S_AXI_ACP_AWID),
.S_AXI_AWADDR (S_AXI_ACP_AWADDR),
.S_AXI_AWLEN (S_AXI_ACP_AWLEN),
.S_AXI_AWSIZE (S_AXI_ACP_AWSIZE),
.S_AXI_AWBURST (S_AXI_ACP_AWBURST),
.S_AXI_AWLOCK (S_AXI_ACP_AWLOCK),
.S_AXI_AWCACHE (S_AXI_ACP_AWCACHE),
.S_AXI_AWPROT (S_AXI_ACP_AWPROT),
//.S_AXI_AWUSER (S_AXI_ACP_AWUSER),
.S_AXI_AWUSER (param_awuser),
.S_AXI_AWVALID (S_AXI_ACP_AWVALID),
.S_AXI_AWREADY (S_AXI_ACP_AWREADY),
// Slave Interface Write Data Ports
.S_AXI_WID (S_AXI_ACP_WID),
.S_AXI_WDATA (S_AXI_ACP_WDATA),
.S_AXI_WSTRB (S_AXI_ACP_WSTRB),
.S_AXI_WLAST (S_AXI_ACP_WLAST),
.S_AXI_WUSER (),
.S_AXI_WVALID (S_AXI_ACP_WVALID),
.S_AXI_WREADY (S_AXI_ACP_WREADY),
// Slave Interface Write Response Ports
.S_AXI_BID (S_AXI_ACP_BID),
.S_AXI_BRESP (S_AXI_ACP_BRESP),
.S_AXI_BUSER (),
.S_AXI_BVALID (S_AXI_ACP_BVALID),
.S_AXI_BREADY (S_AXI_ACP_BREADY),
// Slave Interface Read Address Ports
.S_AXI_ARID (S_AXI_ACP_ARID),
.S_AXI_ARADDR (S_AXI_ACP_ARADDR),
.S_AXI_ARLEN (S_AXI_ACP_ARLEN),
.S_AXI_ARSIZE (S_AXI_ACP_ARSIZE),
.S_AXI_ARBURST (S_AXI_ACP_ARBURST),
.S_AXI_ARLOCK (S_AXI_ACP_ARLOCK),
.S_AXI_ARCACHE (S_AXI_ACP_ARCACHE),
.S_AXI_ARPROT (S_AXI_ACP_ARPROT),
//.S_AXI_ARUSER (S_AXI_ACP_ARUSER),
.S_AXI_ARUSER (param_aruser),
.S_AXI_ARVALID (S_AXI_ACP_ARVALID),
.S_AXI_ARREADY (S_AXI_ACP_ARREADY),
// Slave Interface Read Data Ports
.S_AXI_RID (S_AXI_ACP_RID),
.S_AXI_RDATA (S_AXI_ACP_RDATA),
.S_AXI_RRESP (S_AXI_ACP_RRESP),
.S_AXI_RLAST (S_AXI_ACP_RLAST),
.S_AXI_RUSER (),
.S_AXI_RVALID (S_AXI_ACP_RVALID),
.S_AXI_RREADY (S_AXI_ACP_RREADY),
// Slave Interface Write Address Ports
.M_AXI_AWID (S_AXI_ATC_AWID),
.M_AXI_AWADDR (S_AXI_ATC_AWADDR),
.M_AXI_AWLEN (S_AXI_ATC_AWLEN),
.M_AXI_AWSIZE (S_AXI_ATC_AWSIZE),
.M_AXI_AWBURST (S_AXI_ATC_AWBURST),
.M_AXI_AWLOCK (S_AXI_ATC_AWLOCK),
.M_AXI_AWCACHE (S_AXI_ATC_AWCACHE),
.M_AXI_AWPROT (S_AXI_ATC_AWPROT),
.M_AXI_AWUSER (S_AXI_ATC_AWUSER),
.M_AXI_AWVALID (S_AXI_ATC_AWVALID),
.M_AXI_AWREADY (SAXIACPAWREADY_W),
// Slave Interface Write Data Ports
.M_AXI_WID (S_AXI_ATC_WID),
.M_AXI_WDATA (S_AXI_ATC_WDATA),
.M_AXI_WSTRB (S_AXI_ATC_WSTRB),
.M_AXI_WLAST (S_AXI_ATC_WLAST),
.M_AXI_WUSER (),
.M_AXI_WVALID (S_AXI_ATC_WVALID),
.M_AXI_WREADY (SAXIACPWREADY_W),
// Slave Interface Write Response Ports
.M_AXI_BID (SAXIACPBID_W),
.M_AXI_BRESP (SAXIACPBRESP_W),
.M_AXI_BUSER (),
.M_AXI_BVALID (SAXIACPBVALID_W),
.M_AXI_BREADY (S_AXI_ATC_BREADY),
// Slave Interface Read Address Ports
.M_AXI_ARID (S_AXI_ATC_ARID),
.M_AXI_ARADDR (S_AXI_ATC_ARADDR),
.M_AXI_ARLEN (S_AXI_ATC_ARLEN),
.M_AXI_ARSIZE (S_AXI_ATC_ARSIZE),
.M_AXI_ARBURST (S_AXI_ATC_ARBURST),
.M_AXI_ARLOCK (S_AXI_ATC_ARLOCK),
.M_AXI_ARCACHE (S_AXI_ATC_ARCACHE),
.M_AXI_ARPROT (S_AXI_ATC_ARPROT),
.M_AXI_ARUSER (S_AXI_ATC_ARUSER),
.M_AXI_ARVALID (S_AXI_ATC_ARVALID),
.M_AXI_ARREADY (SAXIACPARREADY_W),
// Slave Interface Read Data Ports
.M_AXI_RID (SAXIACPRID_W),
.M_AXI_RDATA (SAXIACPRDATA_W),
.M_AXI_RRESP (SAXIACPRRESP_W),
.M_AXI_RLAST (SAXIACPRLAST_W),
.M_AXI_RUSER (),
.M_AXI_RVALID (SAXIACPRVALID_W),
.M_AXI_RREADY (S_AXI_ATC_RREADY),
.ERROR_TRIGGER(),
.ERROR_TRANSACTION_ID()
);
end
endgenerate
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O21AI_BEHAVIORAL_V
`define SKY130_FD_SC_HS__O21AI_BEHAVIORAL_V
/**
* o21ai: 2-input OR into first input of 2-input NAND.
*
* Y = !((A1 | A2) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__o21ai (
Y ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
// Local signals
wire or0_out ;
wire nand0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y , B1, or0_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__O21AI_BEHAVIORAL_V
|
`include "macros.vh"
module top
(
inout [53:0] MIO,
inout PS_SRSTB,
inout PS_CLK,
inout PS_PORB,
inout DDR_Clk,
inout DDR_Clk_n,
inout DDR_CKE,
inout DDR_CS_n,
inout DDR_RAS_n,
inout DDR_CAS_n,
output DDR_WEB,
inout [2:0] DDR_BankAddr,
inout [14:0] DDR_Addr,
inout DDR_ODT,
inout DDR_DRSTB,
inout [31:0] DDR_DQ,
inout [3:0] DDR_DM,
inout [3:0] DDR_DQS,
inout [3:0] DDR_DQS_n,
inout DDR_VRN,
inout DDR_VRP,
// Camera IO
input [9:2] CAM0_DIN,
input CAM0_VSYNC,
input CAM0_HREF,
output CAM0_PWDN,
input CAM0_PCLK,
output CAM0_XCLK,
output CAM0_SIO_C,
inout CAM0_SIO_D,
input [9:2] CAM1_DIN,
input CAM1_VSYNC,
input CAM1_HREF,
output CAM1_PWDN,
input CAM1_PCLK,
output CAM1_XCLK,
output CAM1_SIO_C,
inout CAM1_SIO_D,
//output [3:0] debug,
output VGA_VS_n,
output VGA_HS_n,
output [4:0] VGA_red,
output [4:0] VGA_green,
output [4:0] VGA_blue
);
`include "ps7_include.vh";
wire FCLK0;
BUFG bufg0(.I(FCLKCLK[0]),.O(FCLK0));
wire FCLK1;
BUFG bufg1(.I(FCLKCLK[1]),.O(FCLK1));
wire rst_n;
assign ARESETN = FCLKRESETN[0];
assign rst_n = ARESETN;
wire CLK_25M;
wire CLK_24M;
wire CLK_48M;
ClkCtrl clks(
.CLKIN_100M(FCLK0),
.CLKIN_96M(FCLK1),
.CLK_25M(CLK_25M),
.CLK_24M(CLK_24M),
.CLK_48M(CLK_48M),
.rst_n(rst_n)
);
wire XCLK_DIV;
// debug counters
wire [31:0] cam_debug[3:0];
wire [7:0] display_debug;
wire [31:0] MMIO_CMD;
wire [31:0] MMIO_CAM0_CMD;
wire [31:0] MMIO_CAM1_CMD;
wire [31:0] MMIO_FRAME_BYTES0;
wire [31:0] MMIO_TRIBUF_ADDR0;
wire [31:0] MMIO_FRAME_BYTES1;
wire [31:0] MMIO_TRIBUF_ADDR1;
wire [31:0] MMIO_FRAME_BYTES2;
wire [31:0] MMIO_TRIBUF_ADDR2;
wire rw_cam0_cmd_valid;
wire [17:0] rw_cam0_resp;
wire rw_cam0_resp_valid;
wire rw_cam1_cmd_valid;
wire [17:0] rw_cam1_resp;
wire rw_cam1_resp_valid;
wire [31:0] pipe_in_cnt;
wire [31:0] pipe_out_cnt;
wire [31:0] pipe_in_tot;
wire [31:0] pipe_out_tot;
wire [31:0] debug[15:0];
MMIO_slave mmio(
.fclk(FCLK0),
.rst_n(rst_n),
.S_AXI_ACLK(S2M_GP0_AXI_ACLK),
.S_AXI_ARADDR(S2M_GP0_AXI_ARADDR),
.S_AXI_ARID(S2M_GP0_AXI_ARID),
.S_AXI_ARREADY(S2M_GP0_AXI_ARREADY),
.S_AXI_ARVALID(S2M_GP0_AXI_ARVALID),
.S_AXI_AWADDR(S2M_GP0_AXI_AWADDR),
.S_AXI_AWID(S2M_GP0_AXI_AWID),
.S_AXI_AWREADY(S2M_GP0_AXI_AWREADY),
.S_AXI_AWVALID(S2M_GP0_AXI_AWVALID),
.S_AXI_BID(S2M_GP0_AXI_BID),
.S_AXI_BREADY(S2M_GP0_AXI_BREADY),
.S_AXI_BRESP(S2M_GP0_AXI_BRESP),
.S_AXI_BVALID(S2M_GP0_AXI_BVALID),
.S_AXI_RDATA(S2M_GP0_AXI_RDATA),
.S_AXI_RID(S2M_GP0_AXI_RID),
.S_AXI_RLAST(S2M_GP0_AXI_RLAST),
.S_AXI_RREADY(S2M_GP0_AXI_RREADY),
.S_AXI_RRESP(S2M_GP0_AXI_RRESP),
.S_AXI_RVALID(S2M_GP0_AXI_RVALID),
.S_AXI_WDATA(S2M_GP0_AXI_WDATA),
.S_AXI_WREADY(S2M_GP0_AXI_WREADY),
.S_AXI_WSTRB(S2M_GP0_AXI_WSTRB),
.S_AXI_WVALID(S2M_GP0_AXI_WVALID),
.MMIO_CMD(MMIO_CMD[31:0]),
.MMIO_CAM0_CMD(MMIO_CAM0_CMD[31:0]),
.MMIO_CAM1_CMD(MMIO_CAM1_CMD[31:0]),
.MMIO_FRAME_BYTES0(MMIO_FRAME_BYTES0[31:0]),
.MMIO_TRIBUF_ADDR0(MMIO_TRIBUF_ADDR0[31:0]),
.MMIO_FRAME_BYTES1(MMIO_FRAME_BYTES1[31:0]),
.MMIO_TRIBUF_ADDR1(MMIO_TRIBUF_ADDR1[31:0]),
.MMIO_FRAME_BYTES2(MMIO_FRAME_BYTES2[31:0]),
.MMIO_TRIBUF_ADDR2(MMIO_TRIBUF_ADDR2[31:0]),
.debug0(debug[0]),
.debug1(debug[1]),
.debug2(debug[2]),
.debug3(debug[3]),
.debug4(debug[4]),
.debug5(debug[5]),
.debug6(debug[6]),
.debug7(debug[7]),
.debug8(debug[8]),
.debug9(debug[9]),
.debug10(debug[10]),
.debug11(debug[11]),
.debug12(debug[12]),
.debug13(debug[13]),
.debug14(debug[14]),
.debug15(debug[15]),
.rw_cam0_cmd_valid(rw_cam0_cmd_valid),
.rw_cam0_resp(rw_cam0_resp[17:0]),// {err,rw,addr,data}
.rw_cam0_resp_valid(rw_cam0_resp_valid),
.rw_cam1_cmd_valid(rw_cam1_cmd_valid),
.rw_cam1_resp(rw_cam1_resp[17:0]),// {err,rw,addr,data}
.rw_cam1_resp_valid(rw_cam1_resp_valid),
.MMIO_IRQ()
);
wire startall;
wire stopall;
assign startall = (MMIO_CMD == `CMD_START);
assign stopall = (MMIO_CMD == `CMD_STOP);
wire wr_sync0; // Allows you to sync frames
wire wr_frame_valid0;
wire wr_frame_ready0;
wire [31:0] wr_FRAME_BYTES0;
wire [31:0] wr_BUF_ADDR0;
wire wr_frame_done0;
//Read interface
wire rd_sync0; // allows you to sync frame reads
wire rd_frame_valid0;
wire rd_frame_ready0;
wire [31:0] rd_FRAME_BYTES0;
wire [31:0] rd_BUF_ADDR0;
wire rd_frame_done0;
assign wr_sync0 = 1;
assign rd_sync0 = 1;
tribuf_ctrl tribuf_ctrl0(
.fclk(FCLK0),
.rst_n(rst_n),
//MMIO interface
.start(startall),
.stop(stopall),
.FRAME_BYTES(MMIO_FRAME_BYTES0[31:0]),
.TRIBUF_ADDR(MMIO_TRIBUF_ADDR0[31:0]),
//Write interface (final renderer)
.wr_sync(wr_sync0),
.wr_frame_valid(wr_frame_valid0),
.wr_frame_ready(wr_frame_ready0),
.wr_FRAME_BYTES(wr_FRAME_BYTES0[31:0]),
.wr_BUF_ADDR(wr_BUF_ADDR0[31:0]),
.wr_frame_done(wr_frame_done0),
//Read interface pipe
.rd_sync(rd_sync0),
.rd_frame_valid(rd_frame_valid0),
.rd_frame_ready(rd_frame_ready0),
.rd_FRAME_BYTES(rd_FRAME_BYTES0[31:0]),
.rd_BUF_ADDR(rd_BUF_ADDR0[31:0]),
.rd_frame_done(rd_frame_done0),
.debug_wr_ptr(),
.debug_wr_cs(),
.debug_rd_cs(),
.debug_rd_ptr()
);
wire wr_sync1; // Allows you to sync frames
wire wr_frame_valid1;
wire wr_frame_ready1;
wire [31:0] wr_FRAME_BYTES1;
wire [31:0] wr_BUF_ADDR1;
wire wr_frame_done1;
//Read interface
wire rd_sync1; // allows you to sync frame reads
wire rd_frame_valid1;
wire rd_frame_ready1;
wire [31:0] rd_FRAME_BYTES1;
wire [31:0] rd_BUF_ADDR1;
wire rd_frame_done1;
assign wr_sync1 = 1;
assign rd_sync1 = 1;
tribuf_ctrl tribuf_ctrl1(
.fclk(FCLK0),
.rst_n(rst_n),
//MMIO interface
.start(startall),
.stop(stopall),
.FRAME_BYTES(MMIO_FRAME_BYTES1[31:0]),
.TRIBUF_ADDR(MMIO_TRIBUF_ADDR1[31:0]),
//Write interface (final renderer)
.wr_sync(wr_sync1),
.wr_frame_valid(wr_frame_valid1),
.wr_frame_ready(wr_frame_ready1),
.wr_FRAME_BYTES(wr_FRAME_BYTES1[31:0]),
.wr_BUF_ADDR(wr_BUF_ADDR1[31:0]),
.wr_frame_done(wr_frame_done1),
//Read interface pipe
.rd_sync(rd_sync1),
.rd_frame_valid(rd_frame_valid1),
.rd_frame_ready(rd_frame_ready1),
.rd_FRAME_BYTES(rd_FRAME_BYTES1[31:0]),
.rd_BUF_ADDR(rd_BUF_ADDR1[31:0]),
.rd_frame_done(rd_frame_done1),
.debug_wr_ptr(),
.debug_wr_cs(),
.debug_rd_cs(),
.debug_rd_ptr()
);
// Writer
wire wr_sync2;
wire wr_frame_valid2;
wire wr_frame_ready2;
wire [31:0] wr_FRAME_BYTES2;
wire [31:0] wr_BUF_ADDR2;
wire wr_frame_done2;
//Read interface
wire rd_sync2; // allows you to sync frame reads
wire rd_frame_valid2;
wire rd_frame_ready2;
wire [31:0] rd_FRAME_BYTES2;
wire [31:0] rd_BUF_ADDR2;
wire rd_frame_done2;
assign wr_sync2 = 1;
assign rd_sync2 = 1;
tribuf_ctrl tribuf_ctrl2(
.fclk(FCLK0),
.rst_n(rst_n),
//MMIO interface
.start(startall),
.stop(stopall),
.FRAME_BYTES(MMIO_FRAME_BYTES2[31:0]),
.TRIBUF_ADDR(MMIO_TRIBUF_ADDR2[31:0]),
//Write interface (final renderer)
.wr_sync(wr_sync2),
.wr_frame_valid(wr_frame_valid2),
.wr_frame_ready(wr_frame_ready2),
.wr_FRAME_BYTES(wr_FRAME_BYTES2[31:0]),
.wr_BUF_ADDR(wr_BUF_ADDR2[31:0]),
.wr_frame_done(wr_frame_done2),
//Read interface pipe
.rd_sync(rd_sync2),
.rd_frame_valid(rd_frame_valid2),
.rd_frame_ready(rd_frame_ready2),
.rd_FRAME_BYTES(rd_FRAME_BYTES2[31:0]),
.rd_BUF_ADDR(rd_BUF_ADDR2[31:0]),
.rd_frame_done(rd_frame_done2),
.debug_wr_ptr(),
.debug_wr_cs(),
.debug_rd_cs(),
.debug_rd_ptr()
);
//---------------------------------------------------------------
//---------------------------------------------------------------
// CAMERA 0
//---------------------------------------------------------------
wire [63:0] cam02dramw_data;
wire cam02dramw_valid;
wire cam02dramw_burst_valid;
wire cam02dramw_ready;
CamOV7660 cam0OV7660_inst(
//general
.fclk(FCLK0),
.CLK_24M(CLK_24M),
.CLK_48M(CLK_48M),
.rst_n(rst_n),
// Camera IO
.CAM_DIN(CAM0_DIN[9:2]),
.CAM_VSYNC(CAM0_VSYNC),
.CAM_HREF(CAM0_HREF),
.CAM_PWDN(CAM0_PWDN),
.CAM_PCLK(CAM0_PCLK),
.CAM_XCLK(CAM0_XCLK),
.CAM_SIO_C(CAM0_SIO_C),
.CAM_SIO_D(CAM0_SIO_D),
//Camera register setup
.rw_cmd(MMIO_CAM0_CMD[16:0]), //{rw,addr,data}
.rw_cmd_valid(rw_cam0_cmd_valid),
.rw_resp(rw_cam0_resp[17:0]),// {err,rw,addr,data}
.rw_resp_valid(rw_cam0_resp_valid),
//camera stream ctrl
.cam_cmd(`CMD_START),
.cam_cmd_valid(startall),
.cam_cmd_ready(),
//camera output
.sdata_burst_valid(cam02dramw_burst_valid),
.sdata_valid(cam02dramw_valid),
.sdata_ready(cam02dramw_ready),
.sdata(cam02dramw_data[63:0]),
// debug signals
.debug0(cam_debug[0]),
.debug1(cam_debug[1]),
.debug2(cam_debug[2]),
.debug3(cam_debug[3])
);
DramWriter cam0_writer(
.fclk(FCLK0),
.rst_n(rst_n),
.M2S_AXI_ACLK(M2S_HP0_AXI_ACLK),
.M2S_AXI_AWADDR(M2S_HP0_AXI_AWADDR),
.M2S_AXI_AWREADY(M2S_HP0_AXI_AWREADY),
.M2S_AXI_AWVALID(M2S_HP0_AXI_AWVALID),
.M2S_AXI_WDATA(M2S_HP0_AXI_WDATA),
.M2S_AXI_WREADY(M2S_HP0_AXI_WREADY),
.M2S_AXI_WVALID(M2S_HP0_AXI_WVALID),
.M2S_AXI_WLAST(M2S_HP0_AXI_WLAST),
.M2S_AXI_WSTRB(M2S_HP0_AXI_WSTRB),
.M2S_AXI_BRESP(M2S_HP0_AXI_BRESP),
.M2S_AXI_BREADY(M2S_HP0_AXI_BREADY),
.M2S_AXI_BVALID(M2S_HP0_AXI_BVALID),
.M2S_AXI_AWLEN(M2S_HP0_AXI_AWLEN),
.M2S_AXI_AWSIZE(M2S_HP0_AXI_AWSIZE),
.M2S_AXI_AWBURST(M2S_HP0_AXI_AWBURST),
.wr_frame_valid(wr_frame_valid0),
.wr_frame_ready(wr_frame_ready0),
.wr_FRAME_BYTES(wr_FRAME_BYTES0[31:0]),
.wr_BUF_ADDR(wr_BUF_ADDR0[31:0]),
.debug_astate(),
.din_burst_valid(cam02dramw_burst_valid),
.din_valid(cam02dramw_valid),
.din_ready(cam02dramw_ready),
.din(cam02dramw_data[63:0])
);
//-----------------------------------------------------------------------------
//---------------------------------------------------------------
// CAMERA 1
//---------------------------------------------------------------
wire [63:0] cam12dramw_data;
wire cam12dramw_valid;
wire cam12dramw_burst_valid;
wire cam12dramw_ready;
CamOV7660 cam1OV7660_inst(
//general
.fclk(FCLK0),
.CLK_24M(CLK_24M),
.CLK_48M(CLK_48M),
.rst_n(rst_n),
// Camera IO
.CAM_DIN(CAM1_DIN[9:2]),
.CAM_VSYNC(CAM1_VSYNC),
.CAM_HREF(CAM1_HREF),
.CAM_PWDN(CAM1_PWDN),
.CAM_PCLK(CAM1_PCLK),
.CAM_XCLK(CAM1_XCLK),
.CAM_SIO_C(CAM1_SIO_C),
.CAM_SIO_D(CAM1_SIO_D),
//Camera register setup
.rw_cmd(MMIO_CAM1_CMD[16:0]), //{rw,addr,data}
.rw_cmd_valid(rw_cam1_cmd_valid),
.rw_resp(rw_cam1_resp[17:0]),// {err,rw,addr,data}
.rw_resp_valid(rw_cam1_resp_valid),
//camera stream ctrl
.cam_cmd(`CMD_START),
.cam_cmd_valid(startall),
.cam_cmd_ready(),
//camera output
.sdata_burst_valid(cam12dramw_burst_valid),
.sdata_valid(cam12dramw_valid),
.sdata_ready(cam12dramw_ready),
.sdata(cam12dramw_data[63:0]),
// debug signals
.debug0(),
.debug1(),
.debug2(),
.debug3()
);
DramWriter cam1_writer(
.fclk(FCLK0),
.rst_n(rst_n),
.M2S_AXI_ACLK(M2S_HP1_AXI_ACLK),
.M2S_AXI_AWADDR(M2S_HP1_AXI_AWADDR),
.M2S_AXI_AWREADY(M2S_HP1_AXI_AWREADY),
.M2S_AXI_AWVALID(M2S_HP1_AXI_AWVALID),
.M2S_AXI_WDATA(M2S_HP1_AXI_WDATA),
.M2S_AXI_WREADY(M2S_HP1_AXI_WREADY),
.M2S_AXI_WVALID(M2S_HP1_AXI_WVALID),
.M2S_AXI_WLAST(M2S_HP1_AXI_WLAST),
.M2S_AXI_WSTRB(M2S_HP1_AXI_WSTRB),
.M2S_AXI_BRESP(M2S_HP1_AXI_BRESP),
.M2S_AXI_BREADY(M2S_HP1_AXI_BREADY),
.M2S_AXI_BVALID(M2S_HP1_AXI_BVALID),
.M2S_AXI_AWLEN(M2S_HP1_AXI_AWLEN),
.M2S_AXI_AWSIZE(M2S_HP1_AXI_AWSIZE),
.M2S_AXI_AWBURST(M2S_HP1_AXI_AWBURST),
.wr_frame_valid(wr_frame_valid1),
.wr_frame_ready(wr_frame_ready1),
.wr_FRAME_BYTES(wr_FRAME_BYTES1[31:0]),
.wr_BUF_ADDR(wr_BUF_ADDR1[31:0]),
.debug_astate(),
.din_burst_valid(cam12dramw_burst_valid),
.din_valid(cam12dramw_valid),
.din_ready(cam12dramw_ready),
.din(cam12dramw_data[63:0])
);
//-----------------------------------------------------------------------------
wire dramr02pipe_valid;
wire dramr02pipe_ready;
wire [63:0] dramr02pipe_data;
DramReaderBuf pipe_reader0(
.fclk(FCLK0),
.rst_n(rst_n),
.M2S_AXI_ACLK(), // clock is already driven
.M2S_AXI_ARADDR(M2S_HP0_AXI_ARADDR),
.M2S_AXI_ARREADY(M2S_HP0_AXI_ARREADY),
.M2S_AXI_ARVALID(M2S_HP0_AXI_ARVALID),
.M2S_AXI_RDATA(M2S_HP0_AXI_RDATA),
.M2S_AXI_RREADY(M2S_HP0_AXI_RREADY),
.M2S_AXI_RRESP(M2S_HP0_AXI_RRESP),
.M2S_AXI_RVALID(M2S_HP0_AXI_RVALID),
.M2S_AXI_RLAST(M2S_HP0_AXI_RLAST),
.M2S_AXI_ARLEN(M2S_HP0_AXI_ARLEN),
.M2S_AXI_ARSIZE(M2S_HP0_AXI_ARSIZE),
.M2S_AXI_ARBURST(M2S_HP0_AXI_ARBURST),
.rd_frame_valid(rd_frame_valid0),
.rd_frame_ready(rd_frame_ready0),
.rd_FRAME_BYTES(rd_FRAME_BYTES0[31:0]),
.rd_BUF_ADDR(rd_BUF_ADDR0[31:0]),
.debug_astate(),
.dout_ready(dramr02pipe_ready),
.dout_valid(dramr02pipe_valid),
.dout(dramr02pipe_data[63:0])
);
wire dramr12pipe_valid;
wire dramr12pipe_ready;
wire [63:0] dramr12pipe_data;
DramReaderBuf pipe_reader1(
.fclk(FCLK0),
.rst_n(rst_n),
.M2S_AXI_ACLK(), // clock is already driven
.M2S_AXI_ARADDR(M2S_HP1_AXI_ARADDR),
.M2S_AXI_ARREADY(M2S_HP1_AXI_ARREADY),
.M2S_AXI_ARVALID(M2S_HP1_AXI_ARVALID),
.M2S_AXI_RDATA(M2S_HP1_AXI_RDATA),
.M2S_AXI_RREADY(M2S_HP1_AXI_RREADY),
.M2S_AXI_RRESP(M2S_HP1_AXI_RRESP),
.M2S_AXI_RVALID(M2S_HP1_AXI_RVALID),
.M2S_AXI_RLAST(M2S_HP1_AXI_RLAST),
.M2S_AXI_ARLEN(M2S_HP1_AXI_ARLEN),
.M2S_AXI_ARSIZE(M2S_HP1_AXI_ARSIZE),
.M2S_AXI_ARBURST(M2S_HP1_AXI_ARBURST),
.rd_frame_valid(rd_frame_valid1),
.rd_frame_ready(rd_frame_ready1),
.rd_FRAME_BYTES(rd_FRAME_BYTES1[31:0]),
.rd_BUF_ADDR(rd_BUF_ADDR1[31:0]),
.debug_astate(),
.dout_ready(dramr12pipe_ready),
.dout_valid(dramr12pipe_valid),
.dout(dramr12pipe_data[63:0])
);
// PIPELINE
wire [3:0] num_frames;
wire dramr2pipe_valid;
wire dramr2pipe_ready;
wire [63:0] dramr2pipe_data;
wire ser02pipe_valid;
wire ser02pipe_ready;
wire [31:0] ser02pipe_data;
wire ser12pipe_valid;
wire ser12pipe_ready;
wire [31:0] ser12pipe_data;
/*
serializer #(.INLOGBITS(6), .OUTLOGBITS(5)) inst_cam0(
.clk(FCLK0),
.rst_n(rst_n),
.in_valid(dramr02pipe_valid),
.in_ready(dramr02pipe_ready),
.in_data(dramr02pipe_data),
.out_valid(ser02pipe_valid),
.out_ready(ser02pipe_ready),
.out_data(ser02pipe_data)
);
*/
wire [63:0] pipe2dramw_data;
wire pipe2dramw_valid;
wire pipe2dramw_ready;
assign dramr2pipe_valid = dramr02pipe_valid;
assign dramr2pipe_data = dramr02pipe_data;
assign dramr02pipe_ready = dramr2pipe_ready;
//`define DEBUG_REG(i,name,en) \
// reg [31:0] name; \
// `REG(FCLK0,name,2,name+(en)) \
// assign debug[i] = name;
//
//
//
//`DEBUG_REG(0,cam0_valid_cnt,ser02pipe_valid)
//`DEBUG_REG(1,cam1_valid_cnt,ser12pipe_valid)
//`DEBUG_REG(2,cam01_valid_cnt,dramr2pipe_valid)
//`DEBUG_REG(3,pipe_valid_cnt,pipe2dramw_valid)
//
//`DEBUG_REG(4,cam0_r,ser02pipe_ready)
//`DEBUG_REG(5,cam0_rv,ser02pipe_ready & ser02pipe_valid)
//`DEBUG_REG(6,cam0_rnv,ser02pipe_ready & !ser02pipe_valid)
//`DEBUG_REG(7,cam0_nrv,!ser02pipe_ready & ser02pipe_valid)
//
//`DEBUG_REG(8,cam1_r,ser12pipe_ready)
//`DEBUG_REG(9,cam1_rv,ser12pipe_ready & ser12pipe_valid)
//`DEBUG_REG(10,cam1_rnv,ser12pipe_ready & !ser12pipe_valid)
//`DEBUG_REG(11,cam1_nrv,!ser12pipe_ready & ser12pipe_valid)
//
//
//`DEBUG_REG(12,cami0_v,dramr02pipe_valid)
//`DEBUG_REG(13,cami0_r,dramr02pipe_ready)
//`DEBUG_REG(14,cami1_v,dramr12pipe_valid)
//`DEBUG_REG(15,cami1_r,dramr12pipe_ready)
pipeWrap pipeWrap_inst(
.clk(FCLK0),
.rst_n(rst_n),
.start(startall),
.in_valid(dramr2pipe_valid),
.in_ready(dramr2pipe_ready),
.in_data(dramr2pipe_data[63:0]),
.out_valid(pipe2dramw_valid),
.out_ready(pipe2dramw_ready),
.out_data(pipe2dramw_data[63:0])
);
DramWriterBuf pipe_writer2(
.fclk(FCLK0),
.rst_n(rst_n),
.M2S_AXI_ACLK(M2S_HP2_AXI_ACLK),
.M2S_AXI_AWADDR(M2S_HP2_AXI_AWADDR),
.M2S_AXI_AWREADY(M2S_HP2_AXI_AWREADY),
.M2S_AXI_AWVALID(M2S_HP2_AXI_AWVALID),
.M2S_AXI_WDATA(M2S_HP2_AXI_WDATA),
.M2S_AXI_WREADY(M2S_HP2_AXI_WREADY),
.M2S_AXI_WVALID(M2S_HP2_AXI_WVALID),
.M2S_AXI_WLAST(M2S_HP2_AXI_WLAST),
.M2S_AXI_WSTRB(M2S_HP2_AXI_WSTRB),
.M2S_AXI_BRESP(M2S_HP2_AXI_BRESP),
.M2S_AXI_BREADY(M2S_HP2_AXI_BREADY),
.M2S_AXI_BVALID(M2S_HP2_AXI_BVALID),
.M2S_AXI_AWLEN(M2S_HP2_AXI_AWLEN),
.M2S_AXI_AWSIZE(M2S_HP2_AXI_AWSIZE),
.M2S_AXI_AWBURST(M2S_HP2_AXI_AWBURST),
.wr_frame_valid(wr_frame_valid2),
.wr_frame_ready(wr_frame_ready2),
.wr_FRAME_BYTES(wr_FRAME_BYTES2[31:0]),
.wr_BUF_ADDR(wr_BUF_ADDR2[31:0]),
.debug_astate(),
//.din_valid(dramr12pipe_valid),
//.din_ready(dramr12pipe_ready),
//.din(dramr12pipe_data[63:0])
.din_valid(pipe2dramw_valid),
.din_ready(pipe2dramw_ready),
.din(pipe2dramw_data[63:0])
);
//-----------------------------------------------------------------------------
wire [31:0] cur_vga_addr;
wire [7:0] VGA_red_full;
wire [7:0] VGA_green_full;
wire [7:0] VGA_blue_full;
wire [31:0] vga_cmd;
wire vga_cmd_valid;
assign vga_cmd = startall ? `CMD_START : stopall ? `CMD_STOP : 32'h0;
assign vga_cmd_valid = startall | stopall;
wire dramr2display_burst_ready;
wire dramr2display_valid;
wire dramr2display_ready;
wire [63:0] dramr2display_data;
DramReader vga_reader2(
.fclk(FCLK0),
.rst_n(rst_n),
.M2S_AXI_ACLK(), // clock is already driven
.M2S_AXI_ARADDR(M2S_HP2_AXI_ARADDR),
.M2S_AXI_ARREADY(M2S_HP2_AXI_ARREADY),
.M2S_AXI_ARVALID(M2S_HP2_AXI_ARVALID),
.M2S_AXI_RDATA(M2S_HP2_AXI_RDATA),
.M2S_AXI_RREADY(M2S_HP2_AXI_RREADY),
.M2S_AXI_RRESP(M2S_HP2_AXI_RRESP),
.M2S_AXI_RVALID(M2S_HP2_AXI_RVALID),
.M2S_AXI_RLAST(M2S_HP2_AXI_RLAST),
.M2S_AXI_ARLEN(M2S_HP2_AXI_ARLEN),
.M2S_AXI_ARSIZE(M2S_HP2_AXI_ARSIZE),
.M2S_AXI_ARBURST(M2S_HP2_AXI_ARBURST),
.rd_frame_valid(rd_frame_valid2),
.rd_frame_ready(rd_frame_ready2),
.rd_FRAME_BYTES(rd_FRAME_BYTES2[31:0]),
.rd_BUF_ADDR(rd_BUF_ADDR2[31:0]),
.debug_astate(),
.dout_burst_ready(dramr2display_burst_ready),
.dout_ready(dramr2display_ready),
.dout_valid(dramr2display_valid),
.dout(dramr2display_data[63:0])
);
wire pvalid;
display vga_display(
.fclk(FCLK0),
.rst_n(rst_n),
.vgaclk(CLK_25M),
.vga_cmd(vga_cmd),
.vga_cmd_valid(vga_cmd_valid),
.vga_cmd_ready(),
.VGA_VS_n(VGA_VS_n),
.VGA_HS_n(VGA_HS_n),
.VGA_red(VGA_red_full[7:0]),
.VGA_green(VGA_green_full[7:0]),
.VGA_blue(VGA_blue_full[7:0]),
.pvalid(pvalid),
.sdata_burst_ready(dramr2display_burst_ready),
.sdata_valid(dramr2display_valid),
.sdata_ready(dramr2display_ready),
.sdata(dramr2display_data[63:0]),
.debug(display_debug[7:0])
);
assign VGA_red[4:0] = pvalid ? VGA_red_full[7:3] : 0;
assign VGA_green[4:0] = pvalid ? VGA_green_full[7:3] : 0;
assign VGA_blue[4:0] = pvalid ? VGA_blue_full[7:3] : 0;
endmodule : top
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__AND4BB_SYMBOL_V
`define SKY130_FD_SC_HDLL__AND4BB_SYMBOL_V
/**
* and4bb: 4-input AND, first two inputs inverted.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__and4bb (
//# {{data|Data Signals}}
input A_N,
input B_N,
input C ,
input D ,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__AND4BB_SYMBOL_V
|
//*****************************************************************************
// (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: calib_top.v
// /___/ /\ Date Last Modified: $Date: 2011/05/27 14:31:03 $
// \ \ / \ Date Created: Aug 03 2009
// \___\/\___\
//
//Device: 7 Series
//Design Name: DDR3 SDRAM
//Purpose:
//Purpose:
// Top-level for memory physical layer (PHY) interface
// NOTES:
// 1. Need to support multiple copies of CS outputs
// 2. DFI_DRAM_CKE_DISABLE not supported
//
//Reference:
//Revision History:
//*****************************************************************************
/******************************************************************************
**$Id: calib_top.v,v 1.22.10.2 2011/05/27 14:31:03 venkatp Exp $
**$Date: 2011/05/27 14:31:03 $
**$Author: venkatp $
**$Revision: 1.22.10.2 $
**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_2/data/dlib/7series/ddr3_sdram/verilog/rtl/phy/calib_top.v,v $
******************************************************************************/
`timescale 1ps/1ps
module calib_top #
(
parameter TCQ = 100,
parameter nCK_PER_CLK = 2, // # of memory clocks per CLK
parameter CLK_PERIOD = 3333, // Internal clock period (in ps)
parameter N_CTL_LANES = 3, // # of control byte lanes in the PHY
parameter DRAM_TYPE = "DDR3", // Memory I/F type: "DDR3", "DDR2"
parameter PRBS_WIDTH = 64, // The PRBS sequence is 2^PRBS_WIDTH
parameter HIGHEST_LANE = 4,
parameter HIGHEST_BANK = 3,
parameter DQS_BYTE_MAP
= 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00,
// Slot Conifg parameters
parameter [7:0] SLOT_1_CONFIG = 8'b0000_0000,
// DRAM bus widths
parameter BANK_WIDTH = 2, // # of bank bits
parameter COL_WIDTH = 10, // column address width
parameter nCS_PER_RANK = 1, // # of unique CS outputs per rank
parameter DQ_WIDTH = 64, // # of DQ (data)
parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH))
parameter DQS_WIDTH = 8, // # of DQS (strobe)
parameter DRAM_WIDTH = 8, // # of DQ per DQS
parameter ROW_WIDTH = 14, // DRAM address bus width
parameter RANKS = 1, // # of memory ranks in the interface
parameter CS_WIDTH = 1, // # of CS# signals in the interface
parameter CKE_WIDTH = 1, // # of cke outputs
parameter DDR2_DQSN_ENABLE = "YES", // Enable differential DQS for DDR2
parameter PER_BIT_DESKEW = "ON",
// calibration Address. The address given below will be used for calibration
// read and write operations.
parameter NUM_DQSFOUND_CAL = 3, // # of iteration of DQSFOUND calib
parameter CALIB_ROW_ADD = 16'h0000,// Calibration row address
parameter CALIB_COL_ADD = 12'h000, // Calibration column address
parameter CALIB_BA_ADD = 3'h0, // Calibration bank address
// DRAM mode settings
parameter AL = "0", // Additive Latency option
parameter ADDR_CMD_MODE = "1T", // ADDR/CTRL timing: "2T", "1T"
parameter BURST_MODE = "8", // Burst length
parameter BURST_TYPE = "SEQ", // Burst type
parameter nCL = 5, // Read CAS latency (in clk cyc)
parameter nCWL = 5, // Write CAS latency (in clk cyc)
parameter tRFC = 110000, // Refresh-to-command delay
parameter OUTPUT_DRV = "HIGH", // DRAM reduced output drive option
parameter REG_CTRL = "ON", // "ON" for registered DIMM
parameter RTT_NOM = "60", // ODT Nominal termination value
parameter RTT_WR = "60", // ODT Write termination value
parameter WRLVL = "OFF", // Enable write leveling
parameter USE_ODT_PORT = 1, // Support ODT output
// Simulation /debug options
parameter SIM_INIT_OPTION = "NONE", // Skip various initialization steps
parameter SIM_CAL_OPTION = "NONE", // Skip various calibration steps
parameter DEBUG_PORT = "OFF" // Enable debug port
)
(
input clk, // Internal (logic) clock
input rst, // Reset sync'ed to CLK
// Slot present inputs
input [7:0] slot_0_present,
input [7:0] slot_1_present,
// Hard PHY signals
// From PHY Ctrl Block
input phy_ctl_ready,
input phy_ctl_full,
input phy_cmd_full,
input phy_data_full,
// To PHY Ctrl Block
output write_calib,
output read_calib,
output calib_ctl_wren,
output calib_cmd_wren,
output [1:0] calib_seq,
output [3:0] calib_aux_out,
output [2:0] calib_cmd,
output calib_wrdata_en,
output [1:0] calib_rank_cnt,
output [1:0] calib_cas_slot,
output [5:0] calib_data_offset,
output [nCK_PER_CLK*ROW_WIDTH-1:0] phy_address,
output [nCK_PER_CLK*BANK_WIDTH-1:0]phy_bank,
output [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] phy_cs_n,
output [nCK_PER_CLK-1:0] phy_ras_n,
output [nCK_PER_CLK-1:0] phy_cas_n,
output [nCK_PER_CLK-1:0] phy_we_n,
output phy_reset_n,
// To hard PHY wrapper
output reg [5:0] calib_sel,
output reg calib_in_common,
output reg [HIGHEST_BANK-1:0] calib_zero_inputs,
output reg [HIGHEST_BANK-1:0] calib_zero_ctrl,
output reg phy_if_empty_def,
// output reg ck_addr_ctl_delay_done,
// From DQS Phaser_In
input pi_phaselocked,
input pi_phase_locked_all,
input pi_found_dqs,
input pi_dqs_found_all,
// To DQS Phaser_In
output pi_rst_stg1_cal,
output pi_en_stg2_f,
output pi_stg2_f_incdec,
output pi_stg2_load,
output [5:0] pi_stg2_reg_l,
// To DQ IDELAY
output idelay_ce,
output idelay_inc,
// To DQS Phaser_Out
output po_sel_stg2stg3,
output po_stg2_c_incdec,
output po_en_stg2_c,
output po_stg2_f_incdec,
output po_en_stg2_f,
output po_counter_load_en,
output po_counter_read_en,
input [8:0] po_counter_read_val,
// To command Phaser_Out
input phy_if_empty,
// Write data to OUT_FIFO
output [2*nCK_PER_CLK*DQ_WIDTH-1:0]phy_wrdata,
// To CNTVALUEIN input of DQ IDELAYs for perbit de-skew
output [5*RANKS*DQ_WIDTH-1:0] dlyval_dq,
// IN_FIFO read enable during write leveling, write calibration,
// and read leveling
// Read data from hard PHY fans out to mc and calib logic
input[2*nCK_PER_CLK*DQ_WIDTH-1:0] phy_rddata,
// To MC
output [6*RANKS-1:0] calib_rd_data_offset,
output phy_rddata_valid,
output calib_writes,
output init_calib_complete,
output pi_phase_locked_err,
output pi_dqsfound_err,
output wrcal_err,
// output [CKE_WIDTH-1:0] phy_cke,
// Debug Port
// Write leveling logic
// input [5*DQS_WIDTH-1:0] dbg_wr_dqs_tap_set,
// input [5*DQS_WIDTH-1:0] dbg_wr_dq_tap_set,
// input dbg_wr_tap_set_en,
// output [5*DQS_WIDTH-1:0] dbg_wl_odelay_dqs_tap_cnt,
// output [5*DQS_WIDTH-1:0] dbg_wl_odelay_dq_tap_cnt,
output dbg_wrlvl_start,
output dbg_wrlvl_done,
output dbg_wrlvl_err,
output [4:0] dbg_tap_cnt_during_wrlvl,
output dbg_wl_edge_detect_valid,
output [DQS_WIDTH-1:0] dbg_rd_data_edge_detect,
// Write Calibration Logic
output [99:0] dbg_phy_wrcal,
// Read leveling logic
output [1:0] dbg_rdlvl_start,
output [1:0] dbg_rdlvl_done,
output [1:0] dbg_rdlvl_err,
output [5*DQS_WIDTH-1:0] dbg_cpt_first_edge_cnt,
output [5*DQS_WIDTH-1:0] dbg_cpt_second_edge_cnt,
// Delay control
input dbg_idel_up_all,
input dbg_idel_down_all,
input dbg_idel_up_cpt,
input dbg_idel_down_cpt,
input [DQS_CNT_WIDTH-1:0] dbg_sel_idel_cpt,
input dbg_sel_all_idel_cpt,
output [255:0] dbg_phy_rdlvl, // Read leveling calibration
output [255:0] dbg_calib_top // General PHY debug
);
// Advance ODELAY of DQ by extra 0.25*tCK (quarter clock cycle) to center
// align DQ and DQS on writes. Round (up or down) value to nearest integer
// localparam integer SHIFT_TBY4_TAP
// = (CLK_PERIOD + (nCK_PER_CLK*(1000000/(REFCLK_FREQ*64))*2)-1) /
// (nCK_PER_CLK*(1000000/(REFCLK_FREQ*64))*4);
// Calculate number of slots in the system
localparam nSLOTS = 1 + (|SLOT_1_CONFIG ? 1 : 0);
wire [PRBS_WIDTH-1:0] prbs_o;
wire clk_en;
wire dqsfound_retry;
wire dqsfound_retry_done;
// wire phy_init_data_sel;
wire phy_rddata_en;
wire prech_done;
wire rdlvl_stg1_done;
reg rdlvl_stg1_done_r1;
wire pi_dqs_found_done;
wire rdlvl_stg1_err;
wire pi_dqs_found_err;
wire wrcal_pat_resume;
wire wrcal_resume_w;
wire rdlvl_prech_req;
wire rdlvl_last_byte_done;
wire rdlvl_stg1_start;
wire rdlvl_stg1_rank_done;
wire pi_dqs_found_start;
wire pi_dqs_found_rank_done;
// wire stg2_done_r;
wire wl_sm_start;
wire wrcal_start;
wire wrcal_rd_wait;
wire wrcal_prech_req;
wire wrcal_pat_err;
wire wrcal_done;
wire wrlvl_done;
wire wrlvl_err;
wire wrlvl_start;
wire ddr2_dly_done;
// wire ck_addr_cmd_delay_done;
// wire po_ck_addr_cmd_delay_done;
wire pi_calib_done;
wire detect_pi_found_dqs;
wire [5:0] rd_data_offset;
wire [6*RANKS-1:0] rd_data_offset_ranks;
wire [6*RANKS-1:0] rd_data_offset_ranks_mc;
// wire cmd_po_stg2_f_incdec;
// wire cmd_po_en_stg2_f;
wire po_stg3_f_incdec;
wire po_en_stg3_f;
wire po_stg2_ddr2_incdec;
wire po_en_stg2_ddr2;
wire dqs_po_stg2_f_incdec;
wire dqs_po_en_stg2_f;
wire dqs_wcal_po_stg2_f_incdec;
wire dqs_wcal_po_en_stg2_f;
wire dqs_wl_po_stg2_c_incdec;
wire wrcal_po_stg2_c_incdec;
wire dqs_wl_po_en_stg2_c;
wire wrcal_po_en_stg2_c;
// wire [1:0] ctl_lane_cnt;
// wire [DQS_CNT_WIDTH:0] po_stg3_dqs_cnt;
wire [DQS_CNT_WIDTH:0] po_stg2_wrcal_cnt;
// wire [DQS_CNT_WIDTH:0] pi_phaselock_calib_cnt;
wire [DQS_CNT_WIDTH:0] po_stg2_wl_cnt;
wire [DQS_CNT_WIDTH:0] po_stg2_ddr2_cnt;
wire [8:0] dqs_wl_po_stg2_reg_l;
wire dqs_wl_po_stg2_load;
wire [8:0] dqs_po_stg2_reg_l;
wire dqs_po_stg2_load;
wire dqs_po_dec_done;
// wire [DQS_CNT_WIDTH:0] pi_stg1_dqs_found_cnt;
wire [DQS_CNT_WIDTH:0] pi_stg2_rdlvl_cnt;
reg [DQS_CNT_WIDTH:0] byte_sel_cnt;
wire [3*DQS_WIDTH-1:0] wl_po_coarse_cnt;
wire [6*DQS_WIDTH-1:0] wl_po_fine_cnt;
wire phase_locked_err;
wire prbs_en;
wire phy_ctl_rdy_dly;
reg phy_if_empty_def_r1;
reg phy_if_empty_def_r2;
wire idelay_ce_int;
wire idelay_inc_int;
reg idelay_ce_r1;
reg idelay_ce_r2;
reg idelay_inc_r1;
reg idelay_inc_r2;
//*****************************************************************************
// Assertions to check correctness of parameter values
//*****************************************************************************
initial
begin
if (RANKS == 0) begin
$display ("Error: Invalid RANKS parameter. Must be 1 or greater");
$finish;
end
if (phy_ctl_full == 1'b1) begin
$display ("Error: Incorrect phy_ctl_full input value in 2:1 or 4:1 mode");
$finish;
end
end
//***************************************************************************
// Debug
//***************************************************************************
// Unused for now - use these as needed to bring up lower level signals
assign dbg_calib_top = 256'd0;
// Write Level and write calibration debug observation ports
assign dbg_wrlvl_start = wrlvl_start;
assign dbg_wrlvl_done = wrlvl_done;
assign dbg_wrlvl_err = wrlvl_err;
// assign dbg_wl_odelay_dqs_tap_cnt = dlyval_wrlvl_dqs;
// assign dbg_wl_odelay_dq_tap_cnt = dlyval_wrlvl_dq;
// Read Level debug observation ports
assign dbg_rdlvl_start = {pi_dqs_found_start, rdlvl_stg1_start};
assign dbg_rdlvl_done = {pi_dqs_found_done, rdlvl_stg1_done};
assign dbg_rdlvl_err = {pi_dqs_found_err, rdlvl_stg1_err};
//***************************************************************************
// Write leveling dependent signals
//***************************************************************************
assign wrcal_resume_w = (WRLVL == "ON") ? wrcal_pat_resume : 1'b0;
assign wrlvl_done_w = (WRLVL == "ON") ? wrlvl_done : 1'b1;
// assign ck_addr_cmd_delay_done = (WRLVL == "ON") ? po_ck_addr_cmd_delay_done :
// 1'b1;
assign po_sel_stg2stg3 = 1'b0;//(~dqs_dly_done) ? 1'b1 : 1'b0;
assign po_stg2_c_incdec = (wrlvl_done) ? wrcal_po_stg2_c_incdec :
dqs_wl_po_stg2_c_incdec;
assign po_en_stg2_c = (wrlvl_done) ? wrcal_po_en_stg2_c :
dqs_wl_po_en_stg2_c;
assign po_stg2_f_incdec = (~ddr2_dly_done && (DRAM_TYPE=="DDR2")) ?
po_stg2_ddr2_incdec :
(wrlvl_done)? dqs_wcal_po_stg2_f_incdec :
dqs_po_stg2_f_incdec;
assign po_en_stg2_f = (~ddr2_dly_done && (DRAM_TYPE=="DDR2")) ?
po_en_stg2_ddr2 :
(wrlvl_done)? dqs_wcal_po_en_stg2_f :
dqs_po_en_stg2_f;
assign idelay_ce = idelay_ce_r2;
assign idelay_inc = idelay_inc_r2;
assign clk_en = 1'b1;
assign po_counter_load_en = 1'b0;
//***************************************************************************
// Hard PHY signals
//***************************************************************************
assign calib_rd_data_offset = rd_data_offset_ranks_mc;
assign pi_phase_locked_err = phase_locked_err;
assign pi_dqsfound_err = pi_dqs_found_err;
assign wrcal_err = wrcal_pat_err;
//***************************************************************************
// MUX select logic to select current byte undergoing calibration
// Use DQS_CAL_MAP to determine the correlation between the physical
// byte numbering, and the byte numbering within the hard PHY
//***************************************************************************
always @(posedge clk) begin
if (rst) begin
byte_sel_cnt <= #TCQ 'd0;
calib_in_common <= #TCQ 1'b0;
end else if (~dqs_po_dec_done) begin
byte_sel_cnt <= #TCQ 'd0;
calib_in_common <= #TCQ 1'b1;
end else if (~ddr2_dly_done && (DRAM_TYPE=="DDR2")) begin
byte_sel_cnt <= #TCQ po_stg2_ddr2_cnt;
calib_in_common <= #TCQ 1'b0;
end else if (~wrlvl_done_w) begin
if (SIM_CAL_OPTION != "FAST_CAL") begin
byte_sel_cnt <= #TCQ po_stg2_wl_cnt;
calib_in_common <= #TCQ 1'b0;
end else begin
// Special case for FAST_CAL simulation only to ensure that
// calib_in_common isn't asserted too soon
if (!phy_ctl_rdy_dly) begin
byte_sel_cnt <= #TCQ 'd0;
calib_in_common <= #TCQ 1'b0;
end else begin
byte_sel_cnt <= #TCQ po_stg2_wl_cnt;
calib_in_common <= #TCQ 1'b1;
end
end
end else if (~pi_calib_done) begin
byte_sel_cnt <= #TCQ 'd0;
calib_in_common <= #TCQ 1'b1;
end else if (~pi_dqs_found_done) begin
byte_sel_cnt <= #TCQ 'd0;
calib_in_common <= #TCQ 1'b1;
end else if (~rdlvl_stg1_done && pi_calib_done) begin
byte_sel_cnt <= #TCQ pi_stg2_rdlvl_cnt;
calib_in_common <= #TCQ 1'b0;
end else if (~wrcal_done) begin
byte_sel_cnt <= #TCQ po_stg2_wrcal_cnt;
calib_in_common <= #TCQ 1'b0;
end
end
always @(posedge clk) begin
if (rst || init_calib_complete) begin
calib_sel <= #TCQ 6'b000100;
calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b1}};
calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b1}};
end else if (~dqs_po_dec_done) begin
calib_sel[2] <= #TCQ 1'b0;
calib_sel[1:0] <= #TCQ DQS_BYTE_MAP[(byte_sel_cnt*8)+:2];
calib_sel[5:3] <= #TCQ DQS_BYTE_MAP[((byte_sel_cnt*8)+4)+:3];
calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b0}};
calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b0}};
end else if ((~wrlvl_done_w) && (SIM_CAL_OPTION == "FAST_CAL")) begin
calib_sel[2] <= #TCQ 1'b0;
calib_sel[1:0] <= #TCQ DQS_BYTE_MAP[(byte_sel_cnt*8)+:2];
calib_sel[5:3] <= #TCQ DQS_BYTE_MAP[((byte_sel_cnt*8)+4)+:3];
calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b0}};
calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b1}};
end else begin
calib_sel[2] <= #TCQ 1'b0;
calib_sel[1:0] <= #TCQ DQS_BYTE_MAP[(byte_sel_cnt*8)+:2];
calib_sel[5:3] <= #TCQ DQS_BYTE_MAP[((byte_sel_cnt*8)+4)+:3];
calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b1}};
calib_zero_inputs[(1*DQS_BYTE_MAP[((byte_sel_cnt*8)+4)+:3])] <= #TCQ 1'b0;
calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b1}};
end
end
// Logic to reset IN_FIFO flags to account for the possibility that
// one or more PHASER_IN's have not correctly found the DQS preamble
// If this happens, we can still complete read leveling, but the # of
// words written into the IN_FIFO's may be an odd #, so that if the
// IN_FIFO is used in 2:1 mode ("8:4 mode"), there may be a "half" word
// of data left that can only be flushed out by reseting the IN_FIFO
always @(posedge clk) begin
rdlvl_stg1_done_r1 <= #TCQ rdlvl_stg1_done;
phy_if_empty_def_r1 <= #TCQ phy_if_empty_def;
phy_if_empty_def_r2 <= #TCQ phy_if_empty_def_r1;
end
always @(posedge clk) begin
if (rst || phy_if_empty_def_r2)
phy_if_empty_def <= #TCQ 1'b0;
else if (rdlvl_stg1_done && ~rdlvl_stg1_done_r1)
phy_if_empty_def <= #TCQ 1'b1;
end
// DQ IDELAY tap inc and ce signals registered to control calib_in_common
// signal during read leveling in FAST_CAL mode. The calib_in_common signal
// is only asserted for IDELAY tap increments not Phaser_IN tap increments
// in FAST_CAL mode. For Phaser_IN tap increments the Phaser_IN counter load
// inputs are used.
always @(posedge clk) begin
if (rst) begin
idelay_ce_r1 <= #TCQ 1'b0;
idelay_ce_r2 <= #TCQ 1'b0;
idelay_inc_r1 <= #TCQ 1'b0;
idelay_inc_r2 <= #TCQ 1'b0;
end else begin
idelay_ce_r1 <= #TCQ idelay_ce_int;
idelay_ce_r2 <= #TCQ idelay_ce_r1;
idelay_inc_r1 <= #TCQ idelay_inc_int;
idelay_inc_r2 <= #TCQ idelay_inc_r1;
end
end
//***************************************************************************
// PRBS Generator for Read Leveling Stage 1 - read window detection and
// DQS Centering
//***************************************************************************
prbs_gen #
(
.PRBS_WIDTH (PRBS_WIDTH)
)
u_prbs_gen
(
.clk (clk),
.clk_en (clk_en),
.rst (rst),
.prbs_o (prbs_o)
);
//***************************************************************************
// For DDR2. Delay DQS & DQ by 90' to satisfy the tDQSS spec
//***************************************************************************
generate
if(DRAM_TYPE=="DDR2") begin: gen_ddr2_delay
phy_ddr2_delay #
(
.TCQ (TCQ),
.nCK_PER_CLK (nCK_PER_CLK),
.DQS_WIDTH (DQS_WIDTH),
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.CLK_PERIOD (CLK_PERIOD)
)
u_phy_ddr2_delay
(
.clk (clk),
.rst (rst),
.phy_ctl_ready (phy_ctl_ready),
.po_stg2_f_incdec (po_stg2_ddr2_incdec),
.po_stg2_ddr2_cnt (po_stg2_ddr2_cnt),
.po_en_stg2_f (po_en_stg2_ddr2),
.ddr2_dly_done (ddr2_dly_done)
);
end else begin
assign ddr2_dly_done = 1'b1;
end
endgenerate
//***************************************************************************
// Initialization / Master PHY state logic (overall control during memory
// init, timing leveling)
//***************************************************************************
phy_init #
(
.TCQ (TCQ),
.nCK_PER_CLK (nCK_PER_CLK),
.CLK_PERIOD (CLK_PERIOD),
.DRAM_TYPE (DRAM_TYPE),
.PRBS_WIDTH (PRBS_WIDTH),
.BANK_WIDTH (BANK_WIDTH),
.COL_WIDTH (COL_WIDTH),
.nCS_PER_RANK (nCS_PER_RANK),
.DQ_WIDTH (DQ_WIDTH),
.DQS_WIDTH (DQS_WIDTH),
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.ROW_WIDTH (ROW_WIDTH),
.CS_WIDTH (CS_WIDTH),
.RANKS (RANKS),
.CKE_WIDTH (CKE_WIDTH),
.CALIB_ROW_ADD (CALIB_ROW_ADD),
.CALIB_COL_ADD (CALIB_COL_ADD),
.CALIB_BA_ADD (CALIB_BA_ADD),
.AL (AL),
.BURST_MODE (BURST_MODE),
.BURST_TYPE (BURST_TYPE),
// .nAL (nAL),
.nCL (nCL),
.nCWL (nCWL),
.tRFC (tRFC),
.OUTPUT_DRV (OUTPUT_DRV),
.REG_CTRL (REG_CTRL),
.ADDR_CMD_MODE (ADDR_CMD_MODE),
.RTT_NOM (RTT_NOM),
.RTT_WR (RTT_WR),
.WRLVL (WRLVL),
.USE_ODT_PORT (USE_ODT_PORT),
.DDR2_DQSN_ENABLE(DDR2_DQSN_ENABLE),
.nSLOTS (nSLOTS),
.SIM_INIT_OPTION (SIM_INIT_OPTION),
.SIM_CAL_OPTION (SIM_CAL_OPTION)
)
u_phy_init
(
.clk (clk),
.rst (rst),
.prbs_o (prbs_o),
.ddr2_dly_done (ddr2_dly_done),
.pi_dqs_found_all (pi_dqs_found_all),
.pi_phase_locked_all (pi_phase_locked_all),
// .phy_cke (phy_cke),
.pi_phase_locked_err (phase_locked_err),
.pi_calib_done (pi_calib_done),
.phy_if_empty (phy_if_empty),
.phy_ctl_ready (phy_ctl_ready),
.phy_ctl_full (phy_ctl_full),
.phy_cmd_full (phy_cmd_full),
.phy_data_full (phy_data_full),
.calib_ctl_wren (calib_ctl_wren),
.calib_cmd_wren (calib_cmd_wren),
.calib_wrdata_en (calib_wrdata_en),
.calib_seq (calib_seq),
.calib_aux_out (calib_aux_out),
.calib_rank_cnt (calib_rank_cnt),
.calib_cas_slot (calib_cas_slot),
.calib_data_offset (calib_data_offset),
.calib_cmd (calib_cmd),
.write_calib (write_calib),
.read_calib (read_calib),
.wrlvl_done (wrlvl_done),
.wrlvl_rank_done (wrlvl_rank_done),
.done_dqs_tap_inc (done_dqs_tap_inc),
.wl_sm_start (wl_sm_start),
.wr_lvl_start (wrlvl_start),
.slot_0_present (slot_0_present),
.slot_1_present (slot_1_present),
.rdlvl_stg1_done (rdlvl_stg1_done),
.rdlvl_stg1_rank_done (rdlvl_stg1_rank_done),
.rdlvl_stg1_start (rdlvl_stg1_start),
.rdlvl_prech_req (rdlvl_prech_req),
.rdlvl_last_byte_done (rdlvl_last_byte_done),
.pi_dqs_found_start (pi_dqs_found_start),
.dqsfound_retry (dqsfound_retry),
.pi_dqs_found_rank_done(pi_dqs_found_rank_done),
.pi_dqs_found_done (pi_dqs_found_done),
.detect_pi_found_dqs (detect_pi_found_dqs),
.rd_data_offset (rd_data_offset),
.rd_data_offset_ranks (rd_data_offset_ranks),
.wrcal_start (wrcal_start),
.wrcal_rd_wait (wrcal_rd_wait),
.wrcal_prech_req (wrcal_prech_req),
.wrcal_resume (wrcal_resume_w),
.wrcal_done (wrcal_done),
.prech_done (prech_done),
.prbs_en (prbs_en),
.calib_writes (calib_writes),
.init_calib_complete (init_calib_complete),
.phy_address (phy_address),
.phy_bank (phy_bank),
.phy_cas_n (phy_cas_n),
.phy_cs_n (phy_cs_n),
.phy_ras_n (phy_ras_n),
.phy_reset_n (phy_reset_n),
.phy_we_n (phy_we_n),
.phy_wrdata (phy_wrdata),
.phy_rddata_en (phy_rddata_en),
.phy_rddata_valid (phy_rddata_valid)
);
//*****************************************************************
// Write Calibration
//*****************************************************************
phy_wrcal #
(
.TCQ (TCQ),
.nCK_PER_CLK (nCK_PER_CLK),
.DQ_WIDTH (DQ_WIDTH),
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.DQS_WIDTH (DQS_WIDTH),
.DRAM_WIDTH (DRAM_WIDTH),
.SIM_CAL_OPTION (SIM_CAL_OPTION)
)
u_phy_wrcal
(
.clk (clk),
.rst (rst),
.wrcal_start (wrcal_start),
.wrcal_rd_wait (wrcal_rd_wait),
.dqsfound_retry_done (pi_dqs_found_done),
.dqsfound_retry (dqsfound_retry),
.phy_rddata_en (phy_rddata_en),
.wrcal_done (wrcal_done),
.wrcal_pat_err (wrcal_pat_err),
.wrcal_prech_req (wrcal_prech_req),
.prech_done (prech_done),
.rd_data (phy_rddata),
.dqs_po_stg2_c_incdec (wrcal_po_stg2_c_incdec),
.dqs_po_en_stg2_c (wrcal_po_en_stg2_c),
.dqs_wcal_po_stg2_f_incdec (dqs_wcal_po_stg2_f_incdec),
.dqs_wcal_po_en_stg2_f (dqs_wcal_po_en_stg2_f),
.wrcal_pat_resume (wrcal_pat_resume),
.po_stg2_wrcal_cnt (po_stg2_wrcal_cnt),
.wl_po_coarse_cnt (wl_po_coarse_cnt),
.wl_po_fine_cnt (wl_po_fine_cnt),
.dbg_phy_wrcal (dbg_phy_wrcal)
);
//***************************************************************************
// Write-leveling calibration logic
//***************************************************************************
generate
if (WRLVL == "ON") begin: mb_wrlvl_inst
phy_wrlvl #
(
.TCQ (TCQ),
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.DQ_WIDTH (DQ_WIDTH),
.DQS_WIDTH (DQS_WIDTH),
.DRAM_WIDTH (DRAM_WIDTH),
.RANKS (RANKS),
.CLK_PERIOD (CLK_PERIOD),
.nCK_PER_CLK (nCK_PER_CLK),
.SIM_CAL_OPTION (SIM_CAL_OPTION)
)
u_phy_wrlvl
(
.clk (clk),
.rst (rst),
.phy_ctl_ready (phy_ctl_ready),
.wr_level_start (wrlvl_start),
.wl_sm_start (wl_sm_start),
.rd_data_rise0 (phy_rddata[DQ_WIDTH-1:0]),
.dqs_po_dec_done (dqs_po_dec_done),
.phy_ctl_rdy_dly (phy_ctl_rdy_dly),
.wr_level_done (wrlvl_done),
.wrlvl_rank_done (wrlvl_rank_done),
.done_dqs_tap_inc (done_dqs_tap_inc),
.dqs_po_stg2_f_incdec (dqs_po_stg2_f_incdec),
.dqs_po_en_stg2_f (dqs_po_en_stg2_f),
.dqs_wl_po_stg2_c_incdec (dqs_wl_po_stg2_c_incdec),
.dqs_wl_po_en_stg2_c (dqs_wl_po_en_stg2_c),
.po_counter_read_en (po_counter_read_en),
.po_counter_read_val (po_counter_read_val),
.po_stg2_wl_cnt (po_stg2_wl_cnt),
.wrlvl_err (wrlvl_err),
.wl_po_coarse_cnt (wl_po_coarse_cnt),
.wl_po_fine_cnt (wl_po_fine_cnt),
.dbg_wl_tap_cnt (dbg_tap_cnt_during_wrlvl),
.dbg_wl_edge_detect_valid (dbg_wl_edge_detect_valid),
.dbg_rd_data_edge_detect (dbg_rd_data_edge_detect),
.dbg_dqs_count (),
.dbg_wl_state ()
);
end
endgenerate
//***************************************************************************
// Read data-offset calibration required for Phaser_In
//***************************************************************************
phy_dqs_found_cal #
(
.TCQ (TCQ),
.nCK_PER_CLK (nCK_PER_CLK),
.nCL (nCL),
.AL (AL),
.nCWL (nCWL),
.RANKS (RANKS),
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.DQS_WIDTH (DQS_WIDTH),
.DRAM_WIDTH (DRAM_WIDTH),
.REG_CTRL (REG_CTRL),
.NUM_DQSFOUND_CAL (NUM_DQSFOUND_CAL)
)
u_phy_dqs_found_cal
(
.clk (clk),
.rst (rst),
.pi_dqs_found_start (pi_dqs_found_start),
.dqsfound_retry (dqsfound_retry),
.detect_pi_found_dqs (detect_pi_found_dqs),
.pi_found_dqs (pi_found_dqs),
.pi_dqs_found_all (pi_dqs_found_all),
.pi_rst_stg1_cal (pi_rst_stg1_cal),
.rd_data_offset (rd_data_offset),
.pi_dqs_found_rank_done(pi_dqs_found_rank_done),
.pi_dqs_found_done (pi_dqs_found_done),
.dqsfound_retry_done (dqsfound_retry_done),
.pi_dqs_found_err (pi_dqs_found_err),
.rd_data_offset_ranks (rd_data_offset_ranks),
.rd_data_offset_ranks_mc (rd_data_offset_ranks_mc)
);
//***************************************************************************
// Read-leveling calibration logic
//***************************************************************************
phy_rdlvl #
(
.TCQ (TCQ),
.nCK_PER_CLK (nCK_PER_CLK),
.CLK_PERIOD (CLK_PERIOD),
.DQ_WIDTH (DQ_WIDTH),
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.DQS_WIDTH (DQS_WIDTH),
.DRAM_WIDTH (DRAM_WIDTH),
.RANKS (RANKS),
.PER_BIT_DESKEW (PER_BIT_DESKEW),
.SIM_CAL_OPTION (SIM_CAL_OPTION),
.DEBUG_PORT (DEBUG_PORT)
)
u_phy_rdlvl
(
.clk (clk),
.rst (rst),
.rdlvl_stg1_start (rdlvl_stg1_start),
.rdlvl_stg1_done (rdlvl_stg1_done),
.rdlvl_stg1_rnk_done (rdlvl_stg1_rank_done),
.rdlvl_stg1_err (rdlvl_stg1_err),
.rdlvl_prech_req (rdlvl_prech_req),
.rdlvl_last_byte_done (rdlvl_last_byte_done),
.prech_done (prech_done),
.phy_if_empty (phy_if_empty),
.rd_data (phy_rddata),
.pi_en_stg2_f (pi_en_stg2_f),
.pi_stg2_f_incdec (pi_stg2_f_incdec),
.pi_stg2_load (pi_stg2_load),
.pi_stg2_reg_l (pi_stg2_reg_l),
.idelay_ce (idelay_ce_int),
.idelay_inc (idelay_inc_int),
.pi_stg2_rdlvl_cnt (pi_stg2_rdlvl_cnt),
.dlyval_dq (dlyval_dq),
.dbg_cpt_first_edge_cnt (dbg_cpt_first_edge_cnt),
.dbg_cpt_second_edge_cnt (dbg_cpt_second_edge_cnt),
.dbg_idel_up_all (dbg_idel_up_all),
.dbg_idel_down_all (dbg_idel_down_all),
.dbg_idel_up_cpt (dbg_idel_up_cpt),
.dbg_idel_down_cpt (dbg_idel_down_cpt),
.dbg_sel_idel_cpt (dbg_sel_idel_cpt),
.dbg_sel_all_idel_cpt (dbg_sel_all_idel_cpt),
.dbg_phy_rdlvl (dbg_phy_rdlvl)
);
endmodule
|
`timescale 1ns / 1ps
module RegisterBanc(ReadData1, ReadData2, WriteData,ReadAddr1, ReadAddr2, WriteAddr, RegWrite, clk , ro);
output [31:0] ReadData1, ReadData2;
input [31:0] WriteData;
input [4:0] ReadAddr1, ReadAddr2, WriteAddr;
input [0:0] RegWrite, clk;
output [31:0] ro;
reg [31:0] Register [0:31];
initial begin
Register[0] = 32'd0;
Register[1] = 32'd0;
Register[2] = 32'd0;
Register[3] = 32'd0;
Register[4] = 32'd0;
Register[5] = 32'd0;
Register[6] = 32'd0;
Register[7] = 32'd0;
Register[8] = 32'd0;
Register[9] = 32'd0;
Register[10] = 32'd0;
Register[11] = 32'd0;
Register[12] = 32'd0;
Register[13] = 32'd0;
Register[14] = 32'd0;
Register[15] = 32'd0;
Register[16] = 32'd0;
Register[17] = 32'd0;
Register[18] = 32'd0;
Register[19] = 32'd0;
Register[20] = 32'd0;
Register[21] = 32'd0;
Register[22] = 32'd0;
Register[23] = 32'd0;
Register[24] = 32'd0;
Register[25] = 32'd0;
Register[26] = 32'd0;
Register[27] = 32'd0;
Register[28] = 32'd0;
Register[29] = 32'd0;
Register[30] = 32'd0;
Register[31] = 32'd0;
end
always @ (posedge clk) begin
if (RegWrite) begin
Register[WriteAddr] <= WriteData;
end
end
assign ReadData1 = Register[ReadAddr1];
assign ReadData2 = Register[ReadAddr2];
assign ro=Register[4'd2];
endmodule
|
/* Generated by Yosys 0.3.0+ (git sha1 3b52121) */
(* src = "../../verilog/sensorfsm.v:3" *)
module \$paramod\SensorFSM\DataWidth=8 (Reset_n_i, Clk_i, Enable_i, CpuIntr_o, SensorValue_o, MeasureFSM_Start_o, MeasureFSM_Done_i, MeasureFSM_Error_i, MeasureFSM_Byte0_i, MeasureFSM_Byte1_i, ParamThreshold_i, ParamCounterPresetH_i, ParamCounterPresetL_i);
(* src = "../../verilog/sensorfsm.v:146" *)
wire [31:0] \$0\SensorFSM_Timer[31:0] ;
(* src = "../../verilog/sensorfsm.v:169" *)
wire [15:0] \$0\Word0[15:0] ;
(* src = "../../verilog/sensorfsm.v:60" *)
wire \$2\MeasureFSM_Start_o[0:0] ;
(* src = "../../verilog/sensorfsm.v:60" *)
wire [2:0] \$2\SensorFSM_NextState[2:0] ;
(* src = "../../verilog/sensorfsm.v:60" *)
wire \$2\SensorFSM_StoreNewValue[0:0] ;
(* src = "../../verilog/sensorfsm.v:60" *)
wire \$2\SensorFSM_TimerPreset[0:0] ;
(* src = "../../verilog/sensorfsm.v:60" *)
wire [2:0] \$3\SensorFSM_NextState[2:0] ;
(* src = "../../verilog/sensorfsm.v:60" *)
wire \$3\SensorFSM_StoreNewValue[0:0] ;
(* src = "../../verilog/sensorfsm.v:60" *)
wire \$3\SensorFSM_TimerPreset[0:0] ;
(* src = "../../verilog/sensorfsm.v:60" *)
wire [2:0] \$4\SensorFSM_NextState[2:0] ;
(* src = "../../verilog/sensorfsm.v:60" *)
wire \$4\SensorFSM_TimerPreset[0:0] ;
(* src = "../../verilog/sensorfsm.v:60" *)
wire [2:0] \$5\SensorFSM_NextState[2:0] ;
(* src = "../../verilog/sensorfsm.v:60" *)
wire \$5\SensorFSM_TimerPreset[0:0] ;
(* src = "../../verilog/sensorfsm.v:60" *)
wire [2:0] \$6\SensorFSM_NextState[2:0] ;
(* src = "../../verilog/sensorfsm.v:60" *)
wire [2:0] \$7\SensorFSM_NextState[2:0] ;
(* src = "../../verilog/sensorfsm.v:60" *)
wire [2:0] \$8\SensorFSM_NextState[2:0] ;
wire \$procmux$195_CMP ;
wire \$procmux$202_CMP ;
wire \$procmux$207_CMP ;
wire \$procmux$210_CMP ;
wire \$procmux$257_CMP ;
wire [31:0] \$procmux$62_Y ;
(* src = "../../verilog/sensorfsm.v:160" *)
wire [31:0] \$sub$../../verilog/sensorfsm.v:160$51_Y ;
(* src = "../../verilog/sensorfsm.v:42" *)
wire [15:0] AbsDiffResult;
(* src = "../../verilog/sensorfsm.v:7" *)
input Clk_i;
(* src = "../../verilog/sensorfsm.v:10" *)
output CpuIntr_o;
(* src = "../../verilog/sensorfsm.v:184" *)
wire [16:0] DiffAB;
(* src = "../../verilog/sensorfsm.v:185" *)
wire [15:0] DiffBA;
(* src = "../../verilog/sensorfsm.v:9" *)
input Enable_i;
(* src = "../../verilog/sensorfsm.v:16" *)
input [7:0] MeasureFSM_Byte0_i;
(* src = "../../verilog/sensorfsm.v:17" *)
input [7:0] MeasureFSM_Byte1_i;
(* src = "../../verilog/sensorfsm.v:14" *)
input MeasureFSM_Done_i;
(* src = "../../verilog/sensorfsm.v:15" *)
input MeasureFSM_Error_i;
(* src = "../../verilog/sensorfsm.v:13" *)
output MeasureFSM_Start_o;
(* src = "../../verilog/sensorfsm.v:20" *)
input [15:0] ParamCounterPresetH_i;
(* src = "../../verilog/sensorfsm.v:21" *)
input [15:0] ParamCounterPresetL_i;
(* src = "../../verilog/sensorfsm.v:19" *)
input [15:0] ParamThreshold_i;
(* src = "../../verilog/sensorfsm.v:6" *)
input Reset_n_i;
(* src = "../../verilog/sensorfsm.v:35" *)
wire SensorFSM_DiffTooLarge;
(* src = "../../verilog/sensorfsm.v:31" *)
wire [2:0] SensorFSM_NextState;
(* src = "../../verilog/sensorfsm.v:30" *)
wire [2:0] SensorFSM_State;
(* src = "../../verilog/sensorfsm.v:36" *)
wire SensorFSM_StoreNewValue;
(* src = "../../verilog/sensorfsm.v:144" *)
wire [31:0] SensorFSM_Timer;
(* src = "../../verilog/sensorfsm.v:34" *)
wire SensorFSM_TimerEnable;
(* src = "../../verilog/sensorfsm.v:32" *)
wire SensorFSM_TimerOvfl;
(* src = "../../verilog/sensorfsm.v:33" *)
wire SensorFSM_TimerPreset;
(* src = "../../verilog/sensorfsm.v:40" *)
wire [15:0] SensorValue;
(* src = "../../verilog/sensorfsm.v:11" *)
output [15:0] SensorValue_o;
(* src = "../../verilog/sensorfsm.v:41" *)
wire [15:0] Word0;
(* src = "../../verilog/sensorfsm.v:165" *)
\$eq #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000100000),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000100000),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$eq$../../verilog/sensorfsm.v:165$52 (
.A(SensorFSM_Timer),
.B(0),
.Y(SensorFSM_TimerOvfl)
);
(* src = "../../verilog/sensorfsm.v:190" *)
\$gt #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000010000),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000010000),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$gt$../../verilog/sensorfsm.v:190$59 (
.A(AbsDiffResult),
.B(ParamThreshold_i),
.Y(SensorFSM_DiffTooLarge)
);
(* src = "../../verilog/sensorfsm.v:146" *)
\$adff #(
.ARST_POLARITY(1'b0),
.ARST_VALUE(32'b00000000000000000000000000000000),
.CLK_POLARITY(1'b1),
.WIDTH(32'b00000000000000000000000000100000)
) \$procdff$2816 (
.ARST(Reset_n_i),
.CLK(Clk_i),
.D(\$0\SensorFSM_Timer[31:0] ),
.Q(SensorFSM_Timer)
);
(* src = "../../verilog/sensorfsm.v:169" *)
\$adff #(
.ARST_POLARITY(1'b0),
.ARST_VALUE(16'b0000000000000000),
.CLK_POLARITY(1'b1),
.WIDTH(32'b00000000000000000000000000010000)
) \$procdff$2817 (
.ARST(Reset_n_i),
.CLK(Clk_i),
.D(\$0\Word0[15:0] ),
.Q(Word0)
);
(* src = "../../verilog/sensorfsm.v:48" *)
\$adff #(
.ARST_POLARITY(1'b0),
.ARST_VALUE(3'b000),
.CLK_POLARITY(1'b1),
.WIDTH(32'b00000000000000000000000000000011)
) \$procdff$2818 (
.ARST(Reset_n_i),
.CLK(Clk_i),
.D(SensorFSM_NextState),
.Q(SensorFSM_State)
);
\$pmux #(
.S_WIDTH(32'b00000000000000000000000000000010),
.WIDTH(32'b00000000000000000000000000000001)
) \$procmux$194 (
.A(1'b0),
.B({ MeasureFSM_Error_i, 1'b1 }),
.S({ \$procmux$202_CMP , \$procmux$195_CMP }),
.Y(CpuIntr_o)
);
\$eq #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000011),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000011),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$195_CMP0 (
.A(SensorFSM_State),
.B(3'b011),
.Y(\$procmux$195_CMP )
);
\$eq #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000011),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000011),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$202_CMP0 (
.A(SensorFSM_State),
.B(3'b010),
.Y(\$procmux$202_CMP )
);
\$eq #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000011),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000011),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$207_CMP0 (
.A(SensorFSM_State),
.B(3'b001),
.Y(\$procmux$207_CMP )
);
\$eq #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000011),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000011),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$210_CMP0 (
.A(SensorFSM_State),
.B(3'b000),
.Y(\$procmux$210_CMP )
);
\$and #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000001),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000001),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$227 (
.A(\$procmux$207_CMP ),
.B(\$2\MeasureFSM_Start_o[0:0] ),
.Y(MeasureFSM_Start_o)
);
\$and #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000001),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000001),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$243 (
.A(\$procmux$202_CMP ),
.B(\$2\SensorFSM_StoreNewValue[0:0] ),
.Y(SensorFSM_StoreNewValue)
);
\$pmux #(
.S_WIDTH(32'b00000000000000000000000000000101),
.WIDTH(32'b00000000000000000000000000000011)
) \$procmux$256 (
.A(SensorFSM_State),
.B({ \$2\SensorFSM_NextState[2:0] , \$3\SensorFSM_NextState[2:0] , \$5\SensorFSM_NextState[2:0] , 3'b001, \$8\SensorFSM_NextState[2:0] }),
.S({ \$procmux$210_CMP , \$procmux$207_CMP , \$procmux$202_CMP , \$procmux$195_CMP , \$procmux$257_CMP }),
.Y(SensorFSM_NextState)
);
\$eq #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000011),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000011),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$257_CMP0 (
.A(SensorFSM_State),
.B(3'b100),
.Y(\$procmux$257_CMP )
);
\$pmux #(
.S_WIDTH(32'b00000000000000000000000000000011),
.WIDTH(32'b00000000000000000000000000000001)
) \$procmux$285 (
.A(1'b0),
.B({ Enable_i, 1'b1, \$2\SensorFSM_StoreNewValue[0:0] }),
.S({ \$procmux$210_CMP , \$procmux$207_CMP , \$procmux$202_CMP }),
.Y(SensorFSM_TimerEnable)
);
\$pmux #(
.S_WIDTH(32'b00000000000000000000000000000011),
.WIDTH(32'b00000000000000000000000000000001)
) \$procmux$306 (
.A(1'b1),
.B({ \$2\SensorFSM_TimerPreset[0:0] , 1'b0, \$3\SensorFSM_TimerPreset[0:0] }),
.S({ \$procmux$210_CMP , \$procmux$207_CMP , \$procmux$202_CMP }),
.Y(SensorFSM_TimerPreset)
);
\$mux #(
.WIDTH(32'b00000000000000000000000000000011)
) \$procmux$334 (
.A(SensorFSM_State),
.B(3'b001),
.S(Enable_i),
.Y(\$2\SensorFSM_NextState[2:0] )
);
\$not #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000001),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$356 (
.A(Enable_i),
.Y(\$2\SensorFSM_TimerPreset[0:0] )
);
\$and #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000001),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000001),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$397 (
.A(Enable_i),
.B(SensorFSM_TimerOvfl),
.Y(\$2\MeasureFSM_Start_o[0:0] )
);
\$mux #(
.WIDTH(32'b00000000000000000000000000000011)
) \$procmux$419 (
.A(3'b000),
.B(\$4\SensorFSM_NextState[2:0] ),
.S(Enable_i),
.Y(\$3\SensorFSM_NextState[2:0] )
);
\$mux #(
.WIDTH(32'b00000000000000000000000000000011)
) \$procmux$439 (
.A(SensorFSM_State),
.B(3'b010),
.S(SensorFSM_TimerOvfl),
.Y(\$4\SensorFSM_NextState[2:0] )
);
\$mux #(
.WIDTH(32'b00000000000000000000000000000001)
) \$procmux$482 (
.A(\$3\SensorFSM_StoreNewValue[0:0] ),
.B(1'b0),
.S(MeasureFSM_Error_i),
.Y(\$2\SensorFSM_StoreNewValue[0:0] )
);
\$or #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000001),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000001),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$526 (
.A(\$4\SensorFSM_TimerPreset[0:0] ),
.B(MeasureFSM_Error_i),
.Y(\$3\SensorFSM_TimerPreset[0:0] )
);
\$mux #(
.WIDTH(32'b00000000000000000000000000000011)
) \$procmux$548 (
.A(\$6\SensorFSM_NextState[2:0] ),
.B(3'b100),
.S(MeasureFSM_Error_i),
.Y(\$5\SensorFSM_NextState[2:0] )
);
\$mux #(
.WIDTH(32'b00000000000000000000000000000011)
) \$procmux$590 (
.A(SensorFSM_State),
.B(\$7\SensorFSM_NextState[2:0] ),
.S(MeasureFSM_Done_i),
.Y(\$6\SensorFSM_NextState[2:0] )
);
\$and #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000001),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000001),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$613 (
.A(MeasureFSM_Done_i),
.B(SensorFSM_DiffTooLarge),
.Y(\$3\SensorFSM_StoreNewValue[0:0] )
);
\$mux #(
.WIDTH(32'b00000000000000000000000000100000)
) \$procmux$62 (
.A(SensorFSM_Timer),
.B(\$sub$../../verilog/sensorfsm.v:160$51_Y ),
.S(SensorFSM_TimerEnable),
.Y(\$procmux$62_Y )
);
\$mux #(
.WIDTH(32'b00000000000000000000000000100000)
) \$procmux$65 (
.A(\$procmux$62_Y ),
.B({ ParamCounterPresetH_i, ParamCounterPresetL_i }),
.S(SensorFSM_TimerPreset),
.Y(\$0\SensorFSM_Timer[31:0] )
);
\$mux #(
.WIDTH(32'b00000000000000000000000000000001)
) \$procmux$659 (
.A(1'b1),
.B(\$5\SensorFSM_TimerPreset[0:0] ),
.S(MeasureFSM_Done_i),
.Y(\$4\SensorFSM_TimerPreset[0:0] )
);
\$mux #(
.WIDTH(32'b00000000000000000000000000010000)
) \$procmux$68 (
.A(Word0),
.B({ MeasureFSM_Byte1_i, MeasureFSM_Byte0_i }),
.S(SensorFSM_StoreNewValue),
.Y(\$0\Word0[15:0] )
);
\$mux #(
.WIDTH(32'b00000000000000000000000000000011)
) \$procmux$681 (
.A(3'b001),
.B(3'b011),
.S(SensorFSM_DiffTooLarge),
.Y(\$7\SensorFSM_NextState[2:0] )
);
\$not #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000001),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$705 (
.A(SensorFSM_DiffTooLarge),
.Y(\$5\SensorFSM_TimerPreset[0:0] )
);
\$mux #(
.WIDTH(32'b00000000000000000000000000000011)
) \$procmux$772 (
.A(3'b000),
.B(SensorFSM_State),
.S(Enable_i),
.Y(\$8\SensorFSM_NextState[2:0] )
);
(* src = "../../verilog/sensorfsm.v:160" *)
\$sub #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000100000),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000001),
.Y_WIDTH(32'b00000000000000000000000000100000)
) \$sub$../../verilog/sensorfsm.v:160$51 (
.A(SensorFSM_Timer),
.B(1'b1),
.Y(\$sub$../../verilog/sensorfsm.v:160$51_Y )
);
(* src = "../../verilog/sensorfsm.v:186" *)
\$sub #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000010001),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000010001),
.Y_WIDTH(32'b00000000000000000000000000010001)
) \$sub$../../verilog/sensorfsm.v:186$56 (
.A({ 1'b0, MeasureFSM_Byte1_i, MeasureFSM_Byte0_i }),
.B({ 1'b0, Word0 }),
.Y(DiffAB)
);
(* src = "../../verilog/sensorfsm.v:187" *)
\$sub #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000010000),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000010000),
.Y_WIDTH(32'b00000000000000000000000000010000)
) \$sub$../../verilog/sensorfsm.v:187$57 (
.A(Word0),
.B({ MeasureFSM_Byte1_i, MeasureFSM_Byte0_i }),
.Y(DiffBA)
);
(* src = "../../verilog/sensorfsm.v:188" *)
\$mux #(
.WIDTH(32'b00000000000000000000000000010000)
) \$ternary$../../verilog/sensorfsm.v:188$58 (
.A(DiffAB[15:0]),
.B(DiffBA),
.S(DiffAB[16]),
.Y(AbsDiffResult)
);
assign SensorValue = { MeasureFSM_Byte1_i, MeasureFSM_Byte0_i };
assign SensorValue_o = Word0;
endmodule
(* src = "../../verilog/i2cfsm.v:3" *)
module I2CFSM(Reset_n_i, Clk_i, Start_i, Done_o, Error_o, Byte0_o, Byte1_o, I2C_ReceiveSend_n_o, I2C_ReadCount_o, I2C_StartProcess_o, I2C_Busy_i, I2C_FIFOReadNext_o, I2C_FIFOWrite_o, I2C_Data_o, I2C_Data_i, I2C_Error_i, ParamCounterPresetH_i, ParamCounterPresetL_i);
(* src = "../../verilog/i2cfsm.v:241" *)
wire [7:0] \$0\Byte0_o[7:0] ;
(* src = "../../verilog/i2cfsm.v:241" *)
wire [7:0] \$0\Byte1_o[7:0] ;
(* src = "../../verilog/i2cfsm.v:271" *)
wire [31:0] \$0\I2C_FSM_Timer[31:0] ;
(* src = "../../verilog/i2cfsm.v:98" *)
wire \$2\I2C_FIFOReadNext_o[0:0] ;
(* src = "../../verilog/i2cfsm.v:98" *)
wire [3:0] \$2\I2C_FSM_NextState[3:0] ;
(* src = "../../verilog/i2cfsm.v:98" *)
wire \$2\I2C_FSM_TimerEnable[0:0] ;
(* src = "../../verilog/i2cfsm.v:98" *)
wire \$2\I2C_FSM_TimerPreset[0:0] ;
(* src = "../../verilog/i2cfsm.v:98" *)
wire [3:0] \$3\I2C_FSM_NextState[3:0] ;
(* src = "../../verilog/i2cfsm.v:98" *)
wire [3:0] \$4\I2C_FSM_NextState[3:0] ;
(* src = "../../verilog/i2cfsm.v:98" *)
wire \$4\I2C_FSM_TimerEnable[0:0] ;
(* src = "../../verilog/i2cfsm.v:98" *)
wire [3:0] \$5\I2C_FSM_NextState[3:0] ;
(* src = "../../verilog/i2cfsm.v:98" *)
wire [3:0] \$6\I2C_FSM_NextState[3:0] ;
(* src = "../../verilog/i2cfsm.v:98" *)
wire [3:0] \$7\I2C_FSM_NextState[3:0] ;
wire \$auto$opt_reduce.cc:126:opt_mux$2832 ;
wire \$auto$opt_reduce.cc:126:opt_mux$2834 ;
wire \$procmux$1152_CMP ;
wire \$procmux$1153_CMP ;
wire \$procmux$1156_CMP ;
wire \$procmux$1157_CMP ;
wire \$procmux$1158_CMP ;
wire \$procmux$1161_CMP ;
wire \$procmux$1166_CMP ;
wire \$procmux$1167_CMP ;
wire \$procmux$1168_CMP ;
wire \$procmux$1169_CMP ;
wire \$procmux$1172_CMP ;
wire [31:0] \$procmux$803_Y ;
(* src = "../../verilog/i2cfsm.v:285" *)
wire [31:0] \$sub$../../verilog/i2cfsm.v:285$14_Y ;
(* src = "../../verilog/i2cfsm.v:10" *)
output [7:0] Byte0_o;
(* src = "../../verilog/i2cfsm.v:11" *)
output [7:0] Byte1_o;
(* src = "../../verilog/i2cfsm.v:5" *)
input Clk_i;
(* src = "../../verilog/i2cfsm.v:8" *)
output Done_o;
(* src = "../../verilog/i2cfsm.v:9" *)
output Error_o;
(* src = "../../verilog/i2cfsm.v:17" *)
input I2C_Busy_i;
(* src = "../../verilog/i2cfsm.v:22" *)
input [7:0] I2C_Data_i;
(* src = "../../verilog/i2cfsm.v:21" *)
output [7:0] I2C_Data_o;
(* src = "../../verilog/i2cfsm.v:24" *)
input I2C_Error_i;
(* src = "../../verilog/i2cfsm.v:19" *)
output I2C_FIFOReadNext_o;
(* src = "../../verilog/i2cfsm.v:20" *)
output I2C_FIFOWrite_o;
(* src = "../../verilog/i2cfsm.v:75" *)
wire [3:0] I2C_FSM_NextState;
(* src = "../../verilog/i2cfsm.v:74" *)
wire [3:0] I2C_FSM_State;
(* src = "../../verilog/i2cfsm.v:269" *)
wire [31:0] I2C_FSM_Timer;
(* src = "../../verilog/i2cfsm.v:78" *)
wire I2C_FSM_TimerEnable;
(* src = "../../verilog/i2cfsm.v:76" *)
wire I2C_FSM_TimerOvfl;
(* src = "../../verilog/i2cfsm.v:77" *)
wire I2C_FSM_TimerPreset;
(* src = "../../verilog/i2cfsm.v:80" *)
wire I2C_FSM_Wr0;
(* src = "../../verilog/i2cfsm.v:79" *)
wire I2C_FSM_Wr1;
(* src = "../../verilog/i2cfsm.v:15" *)
output [7:0] I2C_ReadCount_o;
(* src = "../../verilog/i2cfsm.v:14" *)
output I2C_ReceiveSend_n_o;
(* src = "../../verilog/i2cfsm.v:16" *)
output I2C_StartProcess_o;
(* src = "../../verilog/i2cfsm.v:26" *)
input [15:0] ParamCounterPresetH_i;
(* src = "../../verilog/i2cfsm.v:27" *)
input [15:0] ParamCounterPresetL_i;
(* src = "../../verilog/i2cfsm.v:4" *)
input Reset_n_i;
(* src = "../../verilog/i2cfsm.v:7" *)
input Start_i;
\$reduce_or #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000010),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$auto$opt_reduce.cc:130:opt_mux$2827 (
.A({ \$procmux$1153_CMP , \$procmux$1152_CMP }),
.Y(I2C_ReceiveSend_n_o)
);
\$reduce_or #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000011),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$auto$opt_reduce.cc:130:opt_mux$2831 (
.A({ \$procmux$1167_CMP , \$procmux$1157_CMP , \$procmux$1153_CMP }),
.Y(I2C_StartProcess_o)
);
\$reduce_or #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000010),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$auto$opt_reduce.cc:130:opt_mux$2833 (
.A({ \$procmux$1172_CMP , \$procmux$1161_CMP }),
.Y(\$auto$opt_reduce.cc:126:opt_mux$2832 )
);
\$reduce_or #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000011),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$auto$opt_reduce.cc:130:opt_mux$2835 (
.A({ \$procmux$1169_CMP , \$procmux$1168_CMP , \$procmux$1158_CMP }),
.Y(\$auto$opt_reduce.cc:126:opt_mux$2834 )
);
(* src = "../../verilog/i2cfsm.v:290" *)
\$eq #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000100000),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000100000),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$eq$../../verilog/i2cfsm.v:290$15 (
.A(I2C_FSM_Timer),
.B(0),
.Y(I2C_FSM_TimerOvfl)
);
(* src = "../../verilog/i2cfsm.v:241" *)
\$adff #(
.ARST_POLARITY(1'b0),
.ARST_VALUE(8'b00000000),
.CLK_POLARITY(1'b1),
.WIDTH(32'b00000000000000000000000000001000)
) \$procdff$2819 (
.ARST(Reset_n_i),
.CLK(Clk_i),
.D(\$0\Byte0_o[7:0] ),
.Q(Byte0_o)
);
(* src = "../../verilog/i2cfsm.v:241" *)
\$adff #(
.ARST_POLARITY(1'b0),
.ARST_VALUE(8'b00000000),
.CLK_POLARITY(1'b1),
.WIDTH(32'b00000000000000000000000000001000)
) \$procdff$2820 (
.ARST(Reset_n_i),
.CLK(Clk_i),
.D(\$0\Byte1_o[7:0] ),
.Q(Byte1_o)
);
(* src = "../../verilog/i2cfsm.v:271" *)
\$adff #(
.ARST_POLARITY(1'b0),
.ARST_VALUE(32'b00000000000000000000000000000000),
.CLK_POLARITY(1'b1),
.WIDTH(32'b00000000000000000000000000100000)
) \$procdff$2821 (
.ARST(Reset_n_i),
.CLK(Clk_i),
.D(\$0\I2C_FSM_Timer[31:0] ),
.Q(I2C_FSM_Timer)
);
(* src = "../../verilog/i2cfsm.v:86" *)
\$adff #(
.ARST_POLARITY(1'b0),
.ARST_VALUE(4'b0000),
.CLK_POLARITY(1'b1),
.WIDTH(32'b00000000000000000000000000000100)
) \$procdff$2822 (
.ARST(Reset_n_i),
.CLK(Clk_i),
.D(I2C_FSM_NextState),
.Q(I2C_FSM_State)
);
\$eq #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000100),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000100),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$1148_CMP0 (
.A(I2C_FSM_State),
.B(4'b1100),
.Y(Done_o)
);
\$eq #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000100),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000100),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$1149_CMP0 (
.A(I2C_FSM_State),
.B(4'b1011),
.Y(I2C_FSM_Wr0)
);
\$eq #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000100),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000100),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$1152_CMP0 (
.A(I2C_FSM_State),
.B(4'b1010),
.Y(\$procmux$1152_CMP )
);
\$eq #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000100),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000100),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$1153_CMP0 (
.A(I2C_FSM_State),
.B(4'b1001),
.Y(\$procmux$1153_CMP )
);
\$eq #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000100),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000100),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$1156_CMP0 (
.A(I2C_FSM_State),
.B(4'b1000),
.Y(\$procmux$1156_CMP )
);
\$eq #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000100),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000100),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$1157_CMP0 (
.A(I2C_FSM_State),
.B(4'b0111),
.Y(\$procmux$1157_CMP )
);
\$eq #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000100),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000100),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$1158_CMP0 (
.A(I2C_FSM_State),
.B(4'b0110),
.Y(\$procmux$1158_CMP )
);
\$eq #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000100),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000100),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$1161_CMP0 (
.A(I2C_FSM_State),
.B(4'b0101),
.Y(\$procmux$1161_CMP )
);
\$eq #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000100),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000100),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$1166_CMP0 (
.A(I2C_FSM_State),
.B(4'b0100),
.Y(\$procmux$1166_CMP )
);
\$eq #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000100),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000100),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$1167_CMP0 (
.A(I2C_FSM_State),
.B(4'b0011),
.Y(\$procmux$1167_CMP )
);
\$eq #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000100),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000100),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$1168_CMP0 (
.A(I2C_FSM_State),
.B(4'b0010),
.Y(\$procmux$1168_CMP )
);
\$eq #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000100),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000100),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$1169_CMP0 (
.A(I2C_FSM_State),
.B(4'b0001),
.Y(\$procmux$1169_CMP )
);
\$eq #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000100),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000100),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$1172_CMP0 (
.A(I2C_FSM_State),
.B(4'b0000),
.Y(\$procmux$1172_CMP )
);
\$and #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000001),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000001),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$1192 (
.A(\$procmux$1166_CMP ),
.B(I2C_Error_i),
.Y(Error_o)
);
\$pmux #(
.S_WIDTH(32'b00000000000000000000000000000010),
.WIDTH(32'b00000000000000000000000000000001)
) \$procmux$1202 (
.A(1'b0),
.B({ \$2\I2C_FIFOReadNext_o[0:0] , 1'b1 }),
.S({ \$procmux$1152_CMP , I2C_FSM_Wr0 }),
.Y(I2C_FIFOReadNext_o)
);
\$pmux #(
.S_WIDTH(32'b00000000000000000000000000000010),
.WIDTH(32'b00000000000000000000000000000001)
) \$procmux$1241 (
.A(1'b0),
.B({ \$2\I2C_FSM_TimerEnable[0:0] , \$4\I2C_FSM_TimerEnable[0:0] }),
.S({ \$procmux$1166_CMP , \$procmux$1161_CMP }),
.Y(I2C_FSM_TimerEnable)
);
\$pmux #(
.S_WIDTH(32'b00000000000000000000000000000010),
.WIDTH(32'b00000000000000000000000000000001)
) \$procmux$1268 (
.A(1'b1),
.B({ \$2\I2C_FSM_TimerPreset[0:0] , I2C_FSM_TimerOvfl }),
.S({ \$procmux$1166_CMP , \$procmux$1161_CMP }),
.Y(I2C_FSM_TimerPreset)
);
\$and #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000001),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000001),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$1313 (
.A(\$procmux$1152_CMP ),
.B(\$2\I2C_FIFOReadNext_o[0:0] ),
.Y(I2C_FSM_Wr1)
);
\$mux #(
.WIDTH(32'b00000000000000000000000000001000)
) \$procmux$1340 (
.A(8'b00000000),
.B(8'b00000010),
.S(I2C_ReceiveSend_n_o),
.Y(I2C_ReadCount_o)
);
\$pmux #(
.S_WIDTH(32'b00000000000000000000000000000100),
.WIDTH(32'b00000000000000000000000000001000)
) \$procmux$1425 (
.A(8'b00000000),
.B(52465809),
.S({ \$procmux$1169_CMP , \$procmux$1168_CMP , \$auto$opt_reduce.cc:126:opt_mux$2832 , \$procmux$1156_CMP }),
.Y(I2C_Data_o)
);
\$pmux #(
.S_WIDTH(32'b00000000000000000000000000000100),
.WIDTH(32'b00000000000000000000000000000001)
) \$procmux$1452 (
.A(1'b0),
.B({ Start_i, I2C_FSM_TimerOvfl, 1'b1, \$2\I2C_FIFOReadNext_o[0:0] }),
.S({ \$procmux$1172_CMP , \$procmux$1161_CMP , \$auto$opt_reduce.cc:126:opt_mux$2834 , \$procmux$1156_CMP }),
.Y(I2C_FIFOWrite_o)
);
\$pmux #(
.S_WIDTH(32'b00000000000000000000000000001101),
.WIDTH(32'b00000000000000000000000000000100)
) \$procmux$1471 (
.A(I2C_FSM_State),
.B({ \$2\I2C_FSM_NextState[3:0] , 12'b001000110100, \$3\I2C_FSM_NextState[3:0] , \$5\I2C_FSM_NextState[3:0] , 8'b01111000, \$6\I2C_FSM_NextState[3:0] , 4'b1010, \$7\I2C_FSM_NextState[3:0] , 8'b11000000 }),
.S({ \$procmux$1172_CMP , \$procmux$1169_CMP , \$procmux$1168_CMP , \$procmux$1167_CMP , \$procmux$1166_CMP , \$procmux$1161_CMP , \$procmux$1158_CMP , \$procmux$1157_CMP , \$procmux$1156_CMP , \$procmux$1153_CMP , \$procmux$1152_CMP , I2C_FSM_Wr0, Done_o }),
.Y(I2C_FSM_NextState)
);
\$mux #(
.WIDTH(32'b00000000000000000000000000000100)
) \$procmux$1521 (
.A(I2C_FSM_State),
.B(4'b0001),
.S(Start_i),
.Y(\$2\I2C_FSM_NextState[3:0] )
);
\$mux #(
.WIDTH(32'b00000000000000000000000000000001)
) \$procmux$1598 (
.A(\$2\I2C_FIFOReadNext_o[0:0] ),
.B(1'b0),
.S(I2C_Error_i),
.Y(\$2\I2C_FSM_TimerEnable[0:0] )
);
\$or #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000001),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000001),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$1626 (
.A(I2C_Busy_i),
.B(I2C_Error_i),
.Y(\$2\I2C_FSM_TimerPreset[0:0] )
);
\$mux #(
.WIDTH(32'b00000000000000000000000000000100)
) \$procmux$1654 (
.A(\$4\I2C_FSM_NextState[3:0] ),
.B(4'b0000),
.S(I2C_Error_i),
.Y(\$3\I2C_FSM_NextState[3:0] )
);
\$mux #(
.WIDTH(32'b00000000000000000000000000000100)
) \$procmux$1708 (
.A(4'b0101),
.B(I2C_FSM_State),
.S(I2C_Busy_i),
.Y(\$4\I2C_FSM_NextState[3:0] )
);
\$not #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000001),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$1766 (
.A(I2C_Busy_i),
.Y(\$2\I2C_FIFOReadNext_o[0:0] )
);
\$mux #(
.WIDTH(32'b00000000000000000000000000000100)
) \$procmux$1820 (
.A(I2C_FSM_State),
.B(4'b0110),
.S(I2C_FSM_TimerOvfl),
.Y(\$5\I2C_FSM_NextState[3:0] )
);
\$not #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000001),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$1876 (
.A(I2C_FSM_TimerOvfl),
.Y(\$4\I2C_FSM_TimerEnable[0:0] )
);
\$mux #(
.WIDTH(32'b00000000000000000000000000000100)
) \$procmux$1926 (
.A(4'b1001),
.B(I2C_FSM_State),
.S(I2C_Busy_i),
.Y(\$6\I2C_FSM_NextState[3:0] )
);
\$mux #(
.WIDTH(32'b00000000000000000000000000000100)
) \$procmux$2005 (
.A(4'b1011),
.B(I2C_FSM_State),
.S(I2C_Busy_i),
.Y(\$7\I2C_FSM_NextState[3:0] )
);
\$mux #(
.WIDTH(32'b00000000000000000000000000001000)
) \$procmux$793 (
.A(Byte0_o),
.B(I2C_Data_i),
.S(I2C_FSM_Wr0),
.Y(\$0\Byte0_o[7:0] )
);
\$mux #(
.WIDTH(32'b00000000000000000000000000001000)
) \$procmux$800 (
.A(Byte1_o),
.B(I2C_Data_i),
.S(I2C_FSM_Wr1),
.Y(\$0\Byte1_o[7:0] )
);
\$mux #(
.WIDTH(32'b00000000000000000000000000100000)
) \$procmux$803 (
.A(I2C_FSM_Timer),
.B(\$sub$../../verilog/i2cfsm.v:285$14_Y ),
.S(I2C_FSM_TimerEnable),
.Y(\$procmux$803_Y )
);
\$mux #(
.WIDTH(32'b00000000000000000000000000100000)
) \$procmux$806 (
.A(\$procmux$803_Y ),
.B({ ParamCounterPresetH_i, ParamCounterPresetL_i }),
.S(I2C_FSM_TimerPreset),
.Y(\$0\I2C_FSM_Timer[31:0] )
);
(* src = "../../verilog/i2cfsm.v:285" *)
\$sub #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000100000),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000001),
.Y_WIDTH(32'b00000000000000000000000000100000)
) \$sub$../../verilog/i2cfsm.v:285$14 (
.A(I2C_FSM_Timer),
.B(1'b1),
.Y(\$sub$../../verilog/i2cfsm.v:285$14_Y )
);
endmodule
(* src = "../../verilog/slowadt7410.v:1" *)
module SlowADT7410(Reset_n_i, Clk_i, Enable_i, CpuIntr_o, I2C_ReceiveSend_n_o, I2C_ReadCount_o, I2C_StartProcess_o, I2C_Busy_i, I2C_FIFOReadNext_o, I2C_FIFOWrite_o, I2C_Data_o, I2C_Data_i, I2C_Error_i, PeriodCounterPresetH_i, PeriodCounterPresetL_i, SensorValue_o, Threshold_i, WaitCounterPresetH_i, WaitCounterPresetL_i);
(* intersynth_port = "Clk_i" *)
(* src = "../../verilog/slowadt7410.v:5" *)
input Clk_i;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "ReconfModuleIRQs_s" *)
(* src = "../../verilog/slowadt7410.v:9" *)
output CpuIntr_o;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "ReconfModuleIn_s" *)
(* src = "../../verilog/slowadt7410.v:7" *)
input Enable_i;
(* src = "../../verilog/slowadt7410.v:45" *)
wire [7:0] I2CFSM_Byte0_s;
(* src = "../../verilog/slowadt7410.v:46" *)
wire [7:0] I2CFSM_Byte1_s;
(* src = "../../verilog/slowadt7410.v:43" *)
wire I2CFSM_Done_s;
(* src = "../../verilog/slowadt7410.v:44" *)
wire I2CFSM_Error_s;
(* src = "../../verilog/slowadt7410.v:42" *)
wire I2CFSM_Start_s;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "I2C_Busy" *)
(* src = "../../verilog/slowadt7410.v:17" *)
input I2C_Busy_i;
(* intersynth_conntype = "Byte" *)
(* intersynth_port = "I2C_DataOut" *)
(* src = "../../verilog/slowadt7410.v:25" *)
input [7:0] I2C_Data_i;
(* intersynth_conntype = "Byte" *)
(* intersynth_port = "I2C_DataIn" *)
(* src = "../../verilog/slowadt7410.v:23" *)
output [7:0] I2C_Data_o;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "I2C_Error" *)
(* src = "../../verilog/slowadt7410.v:27" *)
input I2C_Error_i;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "I2C_FIFOReadNext" *)
(* src = "../../verilog/slowadt7410.v:19" *)
output I2C_FIFOReadNext_o;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "I2C_FIFOWrite" *)
(* src = "../../verilog/slowadt7410.v:21" *)
output I2C_FIFOWrite_o;
(* intersynth_conntype = "Byte" *)
(* intersynth_port = "I2C_ReadCount" *)
(* src = "../../verilog/slowadt7410.v:13" *)
output [7:0] I2C_ReadCount_o;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "I2C_ReceiveSend_n" *)
(* src = "../../verilog/slowadt7410.v:11" *)
output I2C_ReceiveSend_n_o;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "I2C_StartProcess" *)
(* src = "../../verilog/slowadt7410.v:15" *)
output I2C_StartProcess_o;
(* intersynth_conntype = "Word" *)
(* intersynth_param = "PeriodCounterPresetH_i" *)
(* src = "../../verilog/slowadt7410.v:29" *)
input [15:0] PeriodCounterPresetH_i;
(* intersynth_conntype = "Word" *)
(* intersynth_param = "PeriodCounterPresetL_i" *)
(* src = "../../verilog/slowadt7410.v:31" *)
input [15:0] PeriodCounterPresetL_i;
(* intersynth_port = "Reset_n_i" *)
(* src = "../../verilog/slowadt7410.v:3" *)
input Reset_n_i;
(* intersynth_conntype = "Word" *)
(* intersynth_param = "SensorValue_o" *)
(* src = "../../verilog/slowadt7410.v:33" *)
output [15:0] SensorValue_o;
(* intersynth_conntype = "Word" *)
(* intersynth_param = "Threshold_i" *)
(* src = "../../verilog/slowadt7410.v:35" *)
input [15:0] Threshold_i;
(* intersynth_conntype = "Word" *)
(* intersynth_param = "WaitCounterPresetH_i" *)
(* src = "../../verilog/slowadt7410.v:37" *)
input [15:0] WaitCounterPresetH_i;
(* intersynth_conntype = "Word" *)
(* intersynth_param = "WaitCounterPresetL_i" *)
(* src = "../../verilog/slowadt7410.v:39" *)
input [15:0] WaitCounterPresetL_i;
(* src = "../../verilog/slowadt7410.v:48" *)
I2CFSM I2CFSM_1 (
.Byte0_o(I2CFSM_Byte0_s),
.Byte1_o(I2CFSM_Byte1_s),
.Clk_i(Clk_i),
.Done_o(I2CFSM_Done_s),
.Error_o(I2CFSM_Error_s),
.I2C_Busy_i(I2C_Busy_i),
.I2C_Data_i(I2C_Data_i),
.I2C_Data_o(I2C_Data_o),
.I2C_Error_i(I2C_Error_i),
.I2C_FIFOReadNext_o(I2C_FIFOReadNext_o),
.I2C_FIFOWrite_o(I2C_FIFOWrite_o),
.I2C_ReadCount_o(I2C_ReadCount_o),
.I2C_ReceiveSend_n_o(I2C_ReceiveSend_n_o),
.I2C_StartProcess_o(I2C_StartProcess_o),
.ParamCounterPresetH_i(WaitCounterPresetH_i),
.ParamCounterPresetL_i(WaitCounterPresetL_i),
.Reset_n_i(Reset_n_i),
.Start_i(I2CFSM_Start_s)
);
(* src = "../../verilog/slowadt7410.v:75" *)
\$paramod\SensorFSM\DataWidth=8 SensorFSM_1 (
.Clk_i(Clk_i),
.CpuIntr_o(CpuIntr_o),
.Enable_i(Enable_i),
.MeasureFSM_Byte0_i(I2CFSM_Byte0_s),
.MeasureFSM_Byte1_i(I2CFSM_Byte1_s),
.MeasureFSM_Done_i(I2CFSM_Done_s),
.MeasureFSM_Error_i(I2CFSM_Error_s),
.MeasureFSM_Start_o(I2CFSM_Start_s),
.ParamCounterPresetH_i(PeriodCounterPresetH_i),
.ParamCounterPresetL_i(PeriodCounterPresetL_i),
.ParamThreshold_i(Threshold_i),
.Reset_n_i(Reset_n_i),
.SensorValue_o(SensorValue_o)
);
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: BMSTU
// Engineer: Oleg Odintsov
//
// Create Date: 10:50:36 02/15/2012
// Design Name:
// Module Name: my6502
// Project Name: Agat Hardware Project
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Revision 0.02 - Fixed NMI bug
// Revision 0.03 - Updated clocking constants to support higher frequencies
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
// Specify following define to allow external
// clocking for phi1 and phi2
// In such case you may use ag6502_ext_clock module
// with baseclk frequency ~ 10 x phi_0
`define AG6502_EXTERNAL_CLOCK
`ifndef AG6502_EXTERNAL_CLOCK
module ag6502_clock(input phi_0, output phi_1, output phi_2);
wire phi_01;
not#3(phi_1,phi_0);
or(phi_01,~phi_0, phi_1);
not#1(phi_2, phi_01);
endmodule
`else
module ag6502_phase_shift(input baseclk, input phi_0, output reg phi_1);
parameter DELAY = 1; // delay in semi-waves of baseclk
initial phi_1 = 0;
integer cnt = 0;
always @(posedge baseclk) begin
if (phi_0 != phi_1) begin
if (!cnt) begin phi_1 <= phi_0; cnt <= DELAY; end
else cnt <= cnt - 1;
end
end
endmodule
// baseclk is used to simulate delays on a real hardware
/*module ag6502_ext_clock(input baseclk, input phi_0, output phi_1, output phi_2);
parameter DELAY1 = 2, DELAY2 = 0; // delays in semi-waves of baseclk
wire phi_1_neg, phi_01;
ag6502_phase_shift#DELAY1 d1(baseclk, phi_0, phi_1_neg);
assign phi_1 = ~phi_1_neg;
and(phi_01, phi_0, phi_1_neg);
ag6502_phase_shift#DELAY2 d2(baseclk, phi_01, phi_2);
endmodule*/
`endif
`define ALU_ORA 3'd0
`define ALU_AND 3'd1
`define ALU_EOR 3'd2
`define ALU_ADC 3'd3
`define ALU_ASL 3'd4
`define ALU_LSR 3'd5
`define ALU_ROL 3'd6
`define ALU_ROR 3'd7
module ag6502_decimal(ADD, D_IN, NEG, CORR);
input wire[4:0] ADD;
input wire D_IN, NEG;
output wire[4:0] CORR;
wire C9 = {ADD[4]^NEG, ADD[3:0]} > 5'd9;
assign CORR = D_IN?{C9^NEG, C9?ADD[3:0] + (NEG?4'd10:4'd6): ADD[3:0]}: ADD;
endmodule
module ag6502_alu(A, B, OP, NEG, C_IN, D_IN, R, C_OUT, V_OUT);
input wire[7:0] A, B;
input wire[2:0] OP;
input wire C_IN, D_IN, NEG;
output wire[7:0] R;
output wire C_OUT, V_OUT;
wire[4:0] ADD_L;
ag6502_decimal DL({1'b0, A[3:0]} + {1'b0, B[3:0]} + C_IN, D_IN, NEG, ADD_L);
wire CF_H = ADD_L[4];
wire[4:0] ADD_H;
ag6502_decimal DH({1'b0, A[7:4]} + {1'b0, B[7:4]} + CF_H, D_IN, NEG, ADD_H);
assign
{C_OUT,R} = (OP==`ALU_ORA)? A | B:
(OP==`ALU_AND)? A & B:
(OP==`ALU_EOR)? A ^ B:
(OP==`ALU_ADC)? {ADD_H, ADD_L[3:0]}:
(OP==`ALU_ASL)? {A[7], A[6:0], 1'b0}:
(OP==`ALU_LSR)? {A[0], 1'b0, A[7:1]}:
(OP==`ALU_ROL)? {A[7], A[6:0], C_IN}:
(OP==`ALU_ROR)? {A[0], C_IN, A[7:1]}:
8'bX;
assign V_OUT = (A[7] == B[7]) && (A[7] != R[7]);
endmodule
/*
System AB/DB discipline:
1. For CPU
Phi1 up => CPU set ab/db_out buses
Phi2 down => CPU reads data from db_in
2. For Memory / other devices
Phi2 up => perform read/write operation
*/
module ag6502(input phi_0,
`ifdef AG6502_EXTERNAL_CLOCK
input phi_1, input phi_2,
`else
output phi_1, output phi_2,
`endif
output reg[15:0] ab,
output wire read,
input[7:0] db_in, output reg[7:0] db_out,
input rdy,
input rst, input irq, input nmi,
input so,
output sync);
`ifndef AG6502_EXTERNAL_CLOCK
ag6502_clock cgen(phi_0, phi_1, phi_2);
`endif
reg rdyg = 1;
reg[2:0] T = 7;
reg[7:0] IR ='h00;
reg[15:0] PC = 0;
wire[7:0] PCH = PC[15:8], PCL = PC[7:0];
reg[7:0] EAL, EAH;
wire[15:0] EA = {EAH, EAL};
reg FLAG_C, FLAG_Z, FLAG_I, FLAG_D, FLAG_B, FLAG_V, FLAG_N;
reg[7:0] AC, X, Y, S = 0;
wire[7:0] P = {FLAG_N, FLAG_V, 1'b1, FLAG_B, FLAG_D, FLAG_I, FLAG_Z, FLAG_C};
wire[7:0] SB;
wire[7:0] ALU_A, ALU_B;
wire[7:0] RES;
wire[2:0] ALU_OP;
reg[8:0] eALU; // with carry
wire[7:0] ALU = eALU;
wire ALU_CF = eALU[8];
wire CF_IN, DF_IN;
wire CF_OUT, VF_OUT;
reg so_prev = 0;
reg nmi_prev = 0;
wire irq_active = ~irq & ~FLAG_I;
wire nmi_active = ~nmi & nmi_prev;
wire int_active = irq_active | nmi_active;
wire rst_active = ~rst;
wire so_active = so & ~so_prev;
wire[7:0] IR_in = int_active?8'b0:db_in;
wire[1:0] vec_bits=
nmi_active?2'b01:
rst_active?2'b10:
2'b11;
wire[15:0] vec_addr = {{13{1'b1}}, vec_bits, 1'b0};
wire[10:0] L = {T, IR};
`include "states.v"
assign read = ~A_RW_W;
assign sync = !T;
assign SB = A_SB_DB? db_in:
A_SB_AC? AC:
A_SB_X? X:
A_SB_Y? Y:
A_SB_S? S:
A_SB_P? P:
A_SB_ALU? ALU:
A_SB_0? 8'b0:
A_SB_PCH? PCH:
A_SB_PCL? PCL:
8'bX;
assign CF_IN = A_ALU_CF_0? 1'b0:
A_ALU_CF_1? 1'b1:
A_ALU_CF_ALUC? ALU_CF:
FLAG_C;
assign DF_IN = A_ALU_DF_D? FLAG_D: 1'b0;
assign ALU_A =
A_ALU_A_AC? AC:
A_ALU_A_X? X:
A_ALU_A_Y? Y:
A_ALU_A_DB? db_in:
A_ALU_A_EAL? EAL:
A_ALU_A_ALU? ALU:
A_ALU_A_S? S:
A_ALU_A_SIGN? (EAL[7]?8'b11111111:8'b00000001):
8'bX;
assign ALU_B = A_ALU_B_SB? SB:
A_ALU_B_NOTSB? ~SB:
8'bX;
assign ALU_OP = A_ALU_OP_ADC? `ALU_ADC:
A_ALU_OP_ORA? `ALU_ORA:
A_ALU_OP_EOR? `ALU_EOR:
A_ALU_OP_AND? `ALU_AND:
A_ALU_OP_ASL? `ALU_ASL:
A_ALU_OP_LSR? `ALU_LSR:
A_ALU_OP_ROL? `ALU_ROL:
A_ALU_OP_ROR? `ALU_ROR:
8'bX;
ag6502_alu alu(ALU_A, ALU_B, ALU_OP, A_ALU_B_NOTSB, CF_IN, DF_IN, RES, CF_OUT, VF_OUT);
always @(posedge phi_1) begin
if (E_AB__PC) ab <= PC;
else if (E_AB__EA) ab <= EA;
else if (E_AB__S) ab <= {8'b1, S};
if (E_DB__SB) db_out <= SB;
else if (E_DB__PCH) db_out <= PCH;
else if (E_DB__PCL) db_out <= PCL;
else if (E_DB__P) db_out <= P;
else if (E_DB__ALU) db_out <= ALU;
if (read) rdyg <= rdy;
end
wire cond;
assign cond =
E_T__0IFNF__IR_5_?(FLAG_N != IR[5]):
E_T__0IFVF__IR_5_?(FLAG_V != IR[5]):
E_T__0IFCF__IR_5_?(FLAG_C != IR[5]):
E_T__0IFZF__IR_5_?(FLAG_Z != IR[5]):
E_T__0IFZF__IR_5_?(FLAG_Z != IR[5]):
E_T__0IF_C7F? CF_OUT == EAL[7]:
E_T__0;
always @(negedge phi_2) if (rdyg) begin
if (E_PC__PC_1) begin
if (T || (!int_active && !rst_active)) PC <= PC + 1;
end else if (E_PC__EA) PC <= EA;
else begin
if (E_PCH__RES) PC[15:8] <= RES;
if (E_PCL__ALU) PC[7:0] <= ALU;
else if (E_PCL__RES) PC[7:0] <= RES;
else if (E_PCL__EAL) PC[7:0] <= EAL;
else if (E_PCL__DB) PC[7:0] <= db_in;
end
if (!T) begin
IR <= IR_in;
if (!IR_in) begin // BRK instruction
{EAH, EAL} <= vec_addr;
end
nmi_prev <= nmi;
end
if (E_N_Z__SB) begin FLAG_Z <= !SB; FLAG_N <= SB[7]; end
else if (E_N_Z__RES) begin FLAG_Z <= !RES; FLAG_N <= RES[7]; end
else if (E_N_Z__SB_RES) begin FLAG_Z <= !RES; FLAG_N <= SB[7]; end
if (E_C__RES) FLAG_C <= CF_OUT;
if (E_V__RES) FLAG_V <= VF_OUT;
else if (E_V__SB_6_) FLAG_V <= SB[6];
if (E_EAL__DB) EAL <= db_in;
else if (E_EAL__ALU) EAL <= ALU;
if (E_EA__DB) {EAH, EAL} <= { 8'b0, db_in };
else if (E_EAH__DB) EAH <= db_in;
else if (E_EAH__ALU) EAH <= ALU;
if (E_AC__SB) AC <= SB;
else if (E_AC__RES) AC <= RES;
if (E_S__ALU) S <= ALU;
if (E_X__SB) X <= SB;
else if (E_X__RES) X <= RES;
if (E_Y__SB) Y <= SB;
else if (E_Y__RES) Y <= RES;
if (E_S__SB) S <= SB;
if (E_P__SB) {FLAG_N, FLAG_V, FLAG_B, FLAG_D, FLAG_I, FLAG_Z, FLAG_C} <= {SB[7], SB[6], SB[4], SB[3], SB[2], SB[1], SB[0]};
else if (E_P__DB) {FLAG_N, FLAG_V, FLAG_B, FLAG_D, FLAG_I, FLAG_Z, FLAG_C} <= {db_in[7], db_in[6], db_in[4], db_in[3], db_in[2], db_in[1], db_in[0]};
if (E_CF__IR_5_) FLAG_C <= IR[5];
if (E_IF__IR_5_) FLAG_I <= IR[5];
if (E_DF__IR_5_) FLAG_D <= IR[5];
if (E_VF__0) FLAG_V <= 0;
else if (so_active) FLAG_V <= 1;
so_prev <= so;
eALU <= {CF_OUT, RES};
if (cond) begin
T <= 0;
if (!IR) begin
FLAG_B <= !int_active;
FLAG_I <= 1;
end
end else T <= T + ((E_T__T_1IF_ALUCZ && !ALU_CF)?2: 1);
if (rst_active) begin
T <= 1;
IR <= 0;
{EAH, EAL} <= vec_addr;
end
end
endmodule
|
// This tests SystemVerilog casting support
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012 by Iztok Jeras.
// Extended by Maciej Suminski
// Copied and modified by Martin Whitaker
// Copied and modified again by Lars-Peter Clausen
module test();
typedef struct packed signed { logic [7:0] x; } s08;
typedef struct packed signed { logic [15:0] x; } s16;
typedef struct packed signed { int x; } s32;
typedef struct packed signed { int x; shortint y; byte z; logic [7:0] w; } s64;
// variables used in casting
s08 var_08;
s16 var_16;
s32 var_32;
s64 var_64;
real var_real;
// error counter
bit err = 0;
initial begin
var_08 = s08'(4'sh5); if (var_08 !== 8'sh05) begin $display("FAILED -- var_08 = 'h%0h != 8'h05", var_08); err=1; end
var_16 = s16'(var_08); if (var_16 !== 16'sh05) begin $display("FAILED -- var_16 = 'h%0h != 16'h05", var_16); err=1; end
var_32 = s32'(var_16); if (var_32 !== 32'sh05) begin $display("FAILED -- var_32 = 'h%0h != 32'h05", var_32); err=1; end
var_64 = s64'(var_32); if (var_64 !== 64'sh05) begin $display("FAILED -- var_64 = 'h%0h != 64'h05", var_64); err=1; end
var_real = 13.4; var_08 = s08'(var_real); if (var_08 !== 13) begin $display("FAILED -- var_08 = %d != 13", var_08); err=1; end
var_real = 14.5; var_16 = s16'(var_real); if (var_16 !== 15) begin $display("FAILED -- var_16 = %d != 15", var_16); err=1; end
var_real = 15.6; var_32 = s32'(var_real); if (var_32 !== 16) begin $display("FAILED -- var_32 = %d != 16", var_32); err=1; end
var_real = -15.6; var_64 = s64'(var_real); if (var_64 !== -16) begin $display("FAILED -- var_64 = %d != -16", var_64); err=1; end
var_08 = s08'(4'hf); if (var_08 !== 8'sh0f) begin $display("FAILED -- var_08 = 'h%0h != 8'h0f", var_08); err=1; end
var_08 = s08'(4'shf); if (var_08 !== 8'shff) begin $display("FAILED -- var_08 = 'h%0h != 8'hff", var_08); err=1; end
var_16 = s08'(16'h0f0f); if (var_16 !== 16'sh0f) begin $display("FAILED -- var_16 = 'h%0h != 16'h0f", var_16); err=1; end
var_16 = s08'(4'shf) + 'd0; if (var_16 !== 16'shff) begin $display("FAILED -- var_16 = 'h%0h != 16'hff", var_16); err=1; end
if (!err) $display("PASSED");
end
endmodule // test
|
// 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9
// 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0
//----------------------------------------------------------------------------------------
//
// The MIT License (MIT)
// Copyright (c) 2016 Enrique Sedano ([email protected])
//
// Permission is hereby granted, free of charge, to any person obtaining a copy of this
// software and associated documentation files (the "Software"), to deal in the Software
// without restriction, including without limitation the rights to use, copy, modify,
// merge, publish, distribute, sublicense, and/or sell copies of the Software, and to
// permit persons to whom the Software is furnished to do so, subject to the following
// conditions:
//
// The above copyright notice and this permission notice shall be included in all copies
// or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
// PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
// HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF
// CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
// OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
//
//----------------------------------------------------------------------------------------
//----------------------------------------------------------------------------------------
//
// This module is a member of
// ____ __
// _ __/ __ \__ ______/ /_ __
// | | / / /_/ / / / / __ / / / /
// | |/ / _, _/ /_/ / /_/ / /_/ /
// |___/_/ |_|\__,_/\__,_/\__, /
// /____/ v 0.0 - Development
//
// Module: dpth_top.v
// Version: 0.0
// Description:
// Processing unit. Instantiates and connects the blocks of the processing
// unit of vRudy.
//----------------------------------------------------------------------------------------
`include "defines.vh"
module dpth_top (
//------------------------------
// Top level control signals
//------------------------------
input wire clk,
input wire rst_n,
//------------------------------
// Inputs from control
//------------------------------
input wire ld_ra,
input wire ld_ir,
input wire ld_pc,
input wire ld_rat,
input wire ld_rz,
input wire ld_rn,
input wire pc_at,
input wire [1:0] crf,
input wire erd,
input wire operate,
//------------------------------
// Outputs to control
//------------------------------
output wire [1:0] ir_ctrl,
output wire cond,
//------------------------------
// Input from memory
//------------------------------
input wire [15:0] m_out,
//------------------------------
// Outputs to memory
//------------------------------
output wire [15:0] m_in,
output wire [7:0] m_at
);
//------------------------------
// Local wires
//------------------------------
reg [3:0] sl;
wire [15:0] ir;
wire [15:0] rx;
wire [15:0] din;
//------------------------------
// Register file management
//------------------------------
dpth_regfile regfile (
// Top level control signals
.clk ( clk ),
// Input data
.rd_at ( sl ),
.wr_at ( ir[`IR_RD] ),
.wr_en ( erd ),
.din ( din ),
// Output data
.dout ( rx )
);
dpth_alu_top alu_top (
.clk ( clk ),
.rst_n ( rst_n ),
// Inputs
.rx ( rx ),
.m_data ( m_out ),
//------------------------------
// Outputs
//------------------------------
.ir ( ir ),
.alu_out ( din ),
.rz ( rz ),
.rn ( rn )
);
dpth_br_cnd br_cnd (
.z ( rz ),
.n ( rn ),
.irc ( ir[13:11] ),
.cond ( cond )
);
dpth_addr addr (
// Top level control signals
.clk ( clk ),
.rst_n ( rst_n ),
// Inputs
.ir_low ( ir[7:0] ),
.rx_low ( rx[7:0] ),
.ld_rat ( ld_rat ),
.ld_pc ( ld_pc ),
.pc_at ( pc_at ),
// Output
.m_at ( m_at )
);
always @(*)
begin
case (crf)
2'b00: sl <= ir[`IR_RD];
2'b01: sl <= ir[`IR_RI];
2'b10: sl <= ir[`IR_RF];
default: sl <= 3'b000;
endcase
end
//------------------------------
// Output assignments
//------------------------------
assign m_in = rx;
endmodule
//----------------------------------------------------------------------------------------
// Trivia: The "Rudimentary Machine" was the first processor microarchitecture I studied
// at university, back in 2002. Also in 2003, since I failed the subject the first time.
//----------------------------------------------------------------------------------------
// 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9
// 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0
|
//////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE SD Card Controller IP Core ////
//// ////
//// sd_controller_wb.v ////
//// ////
//// This file is part of the WISHBONE SD Card ////
//// Controller IP Core project ////
//// http://opencores.org/project,sd_card_controller ////
//// ////
//// Description ////
//// Wishbone interface responsible for comunication with core ////
//// ////
//// Author(s): ////
//// - Marek Czerski, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2013 Authors ////
//// ////
//// Based on original work by ////
//// Adam Edvardsson ([email protected]) ////
//// ////
//// Copyright (C) 2009 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
`include "sd_defines.h"
module sd_controller_wb(
// WISHBONE slave
wb_clk_i,
wb_rst_i,
wb_dat_i,
wb_dat_o,
wb_adr_i,
wb_sel_i,
wb_we_i,
wb_cyc_i,
wb_stb_i,
wb_ack_o,
cmd_start,
data_int_rst,
cmd_int_rst,
argument_reg,
command_reg,
response_0_reg,
response_1_reg,
response_2_reg,
response_3_reg,
software_reset_reg,
cmd_timeout_reg,
data_timeout_reg,
block_size_reg,
controll_setting_reg,
cmd_int_status_reg,
cmd_int_enable_reg,
clock_divider_reg,
block_count_reg,
dma_addr_reg,
data_int_status_reg,
data_int_enable_reg
);
// WISHBONE common
input wb_clk_i; // WISHBONE clock
input wb_rst_i; // WISHBONE reset
input [31:0] wb_dat_i; // WISHBONE data input
output reg [31:0] wb_dat_o; // WISHBONE data output
// WISHBONE error output
// WISHBONE slave
input [7:0] wb_adr_i; // WISHBONE address input
input [3:0] wb_sel_i; // WISHBONE byte select input
input wb_we_i; // WISHBONE write enable input
input wb_cyc_i; // WISHBONE cycle input
input wb_stb_i; // WISHBONE strobe input
output reg wb_ack_o; // WISHBONE acknowledge output
output reg cmd_start;
//Buss accessible registers
output [31:0] argument_reg;
output [`CMD_REG_SIZE-1:0] command_reg;
input wire [31:0] response_0_reg;
input wire [31:0] response_1_reg;
input wire [31:0] response_2_reg;
input wire [31:0] response_3_reg;
output [0:0] software_reset_reg;
output [`CMD_TIMEOUT_W-1:0] cmd_timeout_reg;
output [`DATA_TIMEOUT_W-1:0] data_timeout_reg;
output [`BLKSIZE_W-1:0] block_size_reg;
output [0:0] controll_setting_reg;
input wire [`INT_CMD_SIZE-1:0] cmd_int_status_reg;
output [`INT_CMD_SIZE-1:0] cmd_int_enable_reg;
output [7:0] clock_divider_reg;
input wire [`INT_DATA_SIZE-1:0] data_int_status_reg;
output [`INT_DATA_SIZE-1:0] data_int_enable_reg;
//Register Controll
output reg data_int_rst;
output reg cmd_int_rst;
output [`BLKCNT_W-1:0]block_count_reg;
output [31:0] dma_addr_reg;
wire we;
parameter voltage_controll_reg = `SUPPLY_VOLTAGE_mV;
parameter capabilies_reg = 16'b0000_0000_0000_0000;
assign we = (wb_we_i && ((wb_stb_i && wb_cyc_i) || wb_ack_o)) ? 1'b1 : 1'b0;
byte_en_reg #(32) argument_r(wb_clk_i, wb_rst_i, we && wb_adr_i == `argument, wb_sel_i, wb_dat_i, argument_reg);
byte_en_reg #(`CMD_REG_SIZE) command_r(wb_clk_i, wb_rst_i, we && wb_adr_i == `command, wb_sel_i[(`CMD_REG_SIZE-1)/8:0], wb_dat_i[`CMD_REG_SIZE-1:0], command_reg);
byte_en_reg #(1) reset_r(wb_clk_i, wb_rst_i, we && wb_adr_i == `reset, wb_sel_i[0], wb_dat_i[0], software_reset_reg);
byte_en_reg #(`CMD_TIMEOUT_W) cmd_timeout_r(wb_clk_i, wb_rst_i, we && wb_adr_i == `cmd_timeout, wb_sel_i[(`CMD_TIMEOUT_W-1)/8:0], wb_dat_i[`CMD_TIMEOUT_W-1:0], cmd_timeout_reg);
byte_en_reg #(`DATA_TIMEOUT_W) data_timeout_r(wb_clk_i, wb_rst_i, we && wb_adr_i == `data_timeout, wb_sel_i[(`DATA_TIMEOUT_W-1)/8:0], wb_dat_i[`DATA_TIMEOUT_W-1:0], data_timeout_reg);
byte_en_reg #(`BLKSIZE_W, `RESET_BLOCK_SIZE) block_size_r(wb_clk_i, wb_rst_i, we && wb_adr_i == `blksize, wb_sel_i[(`BLKSIZE_W-1)/8:0], wb_dat_i[`BLKSIZE_W-1:0], block_size_reg);
byte_en_reg #(1) controll_r(wb_clk_i, wb_rst_i, we && wb_adr_i == `controller, wb_sel_i[0], wb_dat_i[0], controll_setting_reg);
byte_en_reg #(`INT_CMD_SIZE) cmd_int_r(wb_clk_i, wb_rst_i, we && wb_adr_i == `cmd_iser, wb_sel_i[(`INT_CMD_SIZE-1)/8:0], wb_dat_i[`INT_CMD_SIZE-1:0], cmd_int_enable_reg);
byte_en_reg #(8) clock_d_r(wb_clk_i, wb_rst_i, we && wb_adr_i == `clock_d, wb_sel_i[0], wb_dat_i[7:0], clock_divider_reg);
byte_en_reg #(`INT_DATA_SIZE) data_int_r(wb_clk_i, wb_rst_i, we && wb_adr_i == `data_iser, wb_sel_i[(`INT_DATA_SIZE-1)/8:0], wb_dat_i[`INT_DATA_SIZE-1:0], data_int_enable_reg);
byte_en_reg #(`BLKCNT_W) block_count_r(wb_clk_i, wb_rst_i, we && wb_adr_i == `blkcnt, wb_sel_i[(`BLKCNT_W-1)/8:0], wb_dat_i[`BLKCNT_W-1:0], block_count_reg);
byte_en_reg #(32) dma_addr_r(wb_clk_i, wb_rst_i, we && wb_adr_i == `dst_src_addr, wb_sel_i[3:0], wb_dat_i, dma_addr_reg);
always @(posedge wb_clk_i or posedge wb_rst_i)
begin
if (wb_rst_i)begin
wb_ack_o <= 0;
cmd_start <= 0;
data_int_rst <= 0;
cmd_int_rst <= 0;
end
else
begin
cmd_start <= 0;
data_int_rst <= 0;
cmd_int_rst <= 0;
if ((wb_stb_i & wb_cyc_i) || wb_ack_o)begin
if (wb_we_i) begin
case (wb_adr_i)
`argument: cmd_start <= 1;//only msb triggers xfer
`cmd_isr: cmd_int_rst <= 1;
`data_isr: data_int_rst <= 1;
endcase
end
wb_ack_o <= wb_cyc_i & wb_stb_i & ~wb_ack_o;
end
end
end
always @(posedge wb_clk_i or posedge wb_rst_i)begin
if (wb_rst_i == 1)
wb_dat_o <= 0;
else
if (wb_stb_i & wb_cyc_i) begin //CS
case (wb_adr_i)
`argument: wb_dat_o <= argument_reg;
`command: wb_dat_o <= command_reg;
`resp0: wb_dat_o <= response_0_reg;
`resp1: wb_dat_o <= response_1_reg;
`resp2: wb_dat_o <= response_2_reg;
`resp3: wb_dat_o <= response_3_reg;
`controller: wb_dat_o <= controll_setting_reg;
`blksize: wb_dat_o <= block_size_reg;
`voltage: wb_dat_o <= voltage_controll_reg;
`reset: wb_dat_o <= software_reset_reg;
`cmd_timeout: wb_dat_o <= cmd_timeout_reg;
`data_timeout: wb_dat_o <= data_timeout_reg;
`cmd_isr: wb_dat_o <= cmd_int_status_reg;
`cmd_iser: wb_dat_o <= cmd_int_enable_reg;
`clock_d: wb_dat_o <= clock_divider_reg;
`capa: wb_dat_o <= capabilies_reg;
`data_isr: wb_dat_o <= data_int_status_reg;
`blkcnt: wb_dat_o <= block_count_reg;
`data_iser: wb_dat_o <= data_int_enable_reg;
`dst_src_addr: wb_dat_o <= dma_addr_reg;
endcase
end
end
endmodule
|
module rx_path_lookup
#(
parameter DEST_MAC_WIDTH = 48,
parameter NR_PORTS = 4,
parameter PORT_ID = 0,
parameter LOOKUP_MEM_ADDR_WIDTH = 9,
parameter LOOKUP_MEM_DATA_WIDTH = 64,
parameter VLAN_PRIO_WIDTH = 0,
parameter TIMESTAMP_WIDTH = 0,
// lookup memory address constants
parameter LOWER_ADDR_START = 20,
parameter UPPER_ADDR_START = 40,
parameter DEF_ADDR_START = 0,
parameter ENABLE_START = 63,
parameter PORTS_START = 60,
parameter PRIO_START = 48,
parameter SKIP_FRAME_START = 0,
parameter DEST_MAC_START = 0
)
(
clk,
reset,
lookup_in_dest,
lookup_in_vlan_enable,
lookup_in_vlan_prio,
lookup_in_valid,
lookup_in_timestamp,
lookup_in_ready,
lookup_out_ports,
lookup_out_prio,
lookup_out_skip,
lookup_out_timestamp,
lookup_out_valid,
mem_enable,
mem_addr,
mem_data
);
input clk ;
input reset;
// input interface
input [DEST_MAC_WIDTH-1:0] lookup_in_dest;
input lookup_in_vlan_enable;
input [VLAN_PRIO_WIDTH-1:0] lookup_in_vlan_prio;
input lookup_in_valid;
input [TIMESTAMP_WIDTH-1:0] lookup_in_timestamp;
output reg lookup_in_ready;
// output interface
output [NR_PORTS-1:0] lookup_out_ports;
output [VLAN_PRIO_WIDTH-1:0] lookup_out_prio;
output lookup_out_skip;
output [TIMESTAMP_WIDTH-1:0] lookup_out_timestamp;
output reg lookup_out_valid;
// lookup memory interface
output reg mem_enable;
output reg [LOOKUP_MEM_ADDR_WIDTH-1:0] mem_addr;
input [LOOKUP_MEM_DATA_WIDTH-1:0] mem_data;
parameter IDLE = 2'd0;
parameter READ_BASE = 2'd1;
parameter LOOKUP = 2'd2;
parameter READ_DEFAULT = 2'd3;
reg [1:0] state;
reg read_header_sig;
reg read_base_sig;
reg read_default_sig;
reg lookup_valid_sig;
reg read_lookup_sig;
reg update_sig;
reg mem_enable_d1;
reg [LOOKUP_MEM_ADDR_WIDTH-1 : 0] lower_sig;
reg [LOOKUP_MEM_ADDR_WIDTH-1 : 0] upper_sig;
// process registers
reg [DEST_MAC_WIDTH-1 : 0] dest_mac_reg;
reg vlan_enable_reg;
reg [VLAN_PRIO_WIDTH-1 : 0] vlan_prio_reg;
reg [LOOKUP_MEM_ADDR_WIDTH-1 : 0] lower_reg;
reg [LOOKUP_MEM_ADDR_WIDTH-1 : 0] upper_reg;
reg [LOOKUP_MEM_ADDR_WIDTH-1 : 0] median_reg;
reg [LOOKUP_MEM_ADDR_WIDTH-1 : 0] default_reg;
reg [NR_PORTS-1 : 0] ports_reg;
reg [VLAN_PRIO_WIDTH-1 : 0] prio_reg;
reg skip_frame_reg;
reg [TIMESTAMP_WIDTH-1 : 0] timestamp_reg;
// alias signals for memory read access
wire [LOOKUP_MEM_ADDR_WIDTH-1 : 0] mem_lower_sig;
wire [LOOKUP_MEM_ADDR_WIDTH-1 : 0] mem_upper_sig;
wire [LOOKUP_MEM_ADDR_WIDTH-1 : 0] mem_default_sig;
wire mem_lookup_enable_sig;
wire [NR_PORTS-1 : 0] mem_ports_sig;
wire [VLAN_PRIO_WIDTH-1 : 0] mem_prio_sig;
wire mem_skip_frame_sig;
wire [DEST_MAC_WIDTH-1 : 0] mem_dest_mac_sig;
// internal registers (to be connected to the outside, e.g. housekeeping processor)
reg [LOOKUP_MEM_ADDR_WIDTH-1 : 0] base_address = 'd0;
reg [LOOKUP_MEM_ADDR_WIDTH-1 : 0] mem_addr_sig;
assign mem_lower_sig = mem_data[LOWER_ADDR_START+LOOKUP_MEM_ADDR_WIDTH-1 : LOWER_ADDR_START];
assign mem_upper_sig = mem_data[UPPER_ADDR_START+LOOKUP_MEM_ADDR_WIDTH-1 : UPPER_ADDR_START];
assign mem_default_sig = mem_data[DEF_ADDR_START+LOOKUP_MEM_ADDR_WIDTH-1 : DEF_ADDR_START];
assign mem_lookup_enable_sig = mem_data[ENABLE_START];
assign mem_ports_sig = mem_data[PORTS_START+NR_PORTS-1 : PORTS_START];
assign mem_prio_sig = mem_data[PRIO_START+VLAN_PRIO_WIDTH-1 : PRIO_START];
assign mem_skip_frame_sig = mem_data[SKIP_FRAME_START];
assign mem_dest_mac_sig = mem_data[DEST_MAC_START+DEST_MAC_WIDTH-1 : DEST_MAC_START];
always @ (posedge clk)
begin
if (reset) begin
state <= IDLE;
read_header_sig <= 1'b0; // read_header_p
read_base_sig <= 1'b0; // write_internal_registers_p
read_default_sig <= 1'b0; // output_reg_p
lookup_valid_sig <= 1'b0; // output_valid_p
read_lookup_sig <= 1'b0; // output_reg_p
update_sig <= 1'b0; // write_internal_registers_p
upper_reg <= 'b0;
upper_sig <= 'b0;
lower_reg <= 'b0;
lower_sig <= 'b0;
median_reg <= 'b0;
default_reg <= 'b0;
mem_enable <= 1'b0;
mem_enable_d1 <= 1'b0;
mem_addr <= 'hFFF;
dest_mac_reg <= 'b0;
vlan_enable_reg <= 1'b0;
vlan_prio_reg <= 'b0;
timestamp_reg <= 'b0;
lookup_in_ready <= 1'b0;
end
else begin
// 1 Pulse
read_header_sig <= 1'b0;
read_base_sig <= 1'b0;
read_default_sig <= 1'b0;
lookup_valid_sig <= 1'b0;
read_lookup_sig <= 1'b0;
update_sig <= 1'b0;
lookup_in_ready <= 1'b0;
upper_reg <= upper_sig;
lower_reg <= lower_sig;
mem_enable_d1 <= mem_enable;
case(state)
IDLE : begin // waiting for a new header
if (lookup_in_valid) begin
state <= READ_BASE;
read_header_sig <= 1'b1; // read_header_p
mem_enable <= 1'b1;
mem_addr <= base_address;
// Hand shakes
dest_mac_reg <= lookup_in_dest;
vlan_enable_reg <= lookup_in_vlan_enable;
vlan_prio_reg <= lookup_in_vlan_prio;
timestamp_reg <= lookup_in_timestamp;
lookup_in_ready <= 1'b1;
end
end
READ_BASE : begin // read base address, determine if lookup is enabled
if (mem_enable_d1 && mem_enable) begin
mem_enable_d1 <= 1'b0; // force a 1 pulse wait
read_base_sig <= 1'b1; // internal_reg_p
default_reg <= mem_default_sig;
mem_enable <= 1'b1;
if (~mem_lookup_enable_sig) begin // lookup disabled, read default configuration
state <= READ_DEFAULT;
mem_addr <= mem_default_sig;
end
else begin // lookup enabled, search for address in the middle of binary lookup list
state <= LOOKUP;
upper_sig <= mem_upper_sig; // upper_add_lower_by2_f
upper_reg <= mem_upper_sig; // upper_add_lower_by2_f
lower_sig <= mem_lower_sig; // upper_add_lower_by2_f
lower_reg <= mem_lower_sig; // upper_add_lower_by2_f
mem_addr <= (mem_upper_sig + mem_lower_sig)/2; // upper_add_lower_by2_f
end
end
end
LOOKUP : begin // lookup the median memory address and check if the memory mac address matches the frame mac address
if (mem_enable_d1 && mem_enable) begin
mem_enable_d1 <= 1'b0; // force a 1 pulse wait
if (dest_mac_reg == mem_dest_mac_sig) begin // MAC ADDRESS found -> Algorithm terminates
state <= IDLE;
read_lookup_sig <= 1'b1; // output_reg_p
lookup_valid_sig <= 1'b1; // output_valid_p
mem_enable <= 1'b0;
end
else if (upper_reg == lower_reg) begin // MAC ADDRESS not found -> Algorithm terminats with default configuration
state <= READ_DEFAULT;
mem_addr <= default_reg;
//mem_enable <= 1'b1;
end
else begin // MAC ADDRESS not found, Algorithm not terminated yet, continue lookup with decreased search space
update_sig <= 1'b1; // internal_reg_p
//mem_addr <= median_reg[LOOKUP_MEM_ADDR_WIDTH-1:1]; // upper_add_lower_by2_f
// mem_enable <= 1'b1;
state <= LOOKUP;
if (dest_mac_reg > mem_dest_mac_sig) begin
if (upper_sig == lower_sig + 1'b1) begin
upper_sig <= lower_sig;
mem_addr <= lower_sig;
end
else begin
lower_sig <= mem_addr; // upper_add_lower_by2_f
mem_addr <= (upper_sig[LOOKUP_MEM_ADDR_WIDTH-1:1] + mem_addr[LOOKUP_MEM_ADDR_WIDTH-1:1] + (|{mem_addr[0],upper_sig[0]}));
end
end
else begin // dest_mac_reg < mem_dest_mac_sig
if (upper_sig == lower_sig + 1'b1) begin
upper_sig <= lower_sig;
mem_addr <= lower_sig;
end
else begin
upper_sig <= mem_addr; // upper_add_lower_by2_f
mem_addr <= (lower_sig[LOOKUP_MEM_ADDR_WIDTH-1:1] + mem_addr[LOOKUP_MEM_ADDR_WIDTH-1:1] + (|{mem_addr[0],lower_sig[0]}));
end
end
end
end
median_reg <= (upper_sig + lower_sig);
end
READ_DEFAULT : begin
if (mem_enable_d1 && mem_enable) begin
state <= IDLE;
read_default_sig <= 1'b1; // output_reg_p
lookup_valid_sig <= 1'b1; // output_valid_p
mem_enable <= 1'b0;
end
end
endcase
end
end
// updates the output value registers (ports, priority and skip)
always @ (posedge clk)
begin
if (reset) begin
ports_reg <= 'b0;
prio_reg <= 'b0;
skip_frame_reg <= 1'b0;
end
else begin
ports_reg <= ports_reg;
prio_reg <= prio_reg;
skip_frame_reg <= skip_frame_reg;
if (read_default_sig) begin
ports_reg <= mem_ports_sig;
ports_reg[PORT_ID] <= 1'b0;
if (lookup_in_vlan_enable)
prio_reg <= vlan_prio_reg;
else
prio_reg <= mem_prio_sig;
skip_frame_reg <= mem_skip_frame_sig;
end
else if (read_lookup_sig) begin
ports_reg <= mem_ports_sig;
ports_reg[PORT_ID] <= 1'b0; // comment for loopback functionality
if (lookup_in_vlan_enable)
prio_reg <= vlan_prio_reg;
else
prio_reg <= mem_prio_sig;
skip_frame_reg <= 1'b0;
end
end
end
// sets the output valid bit
always @ (posedge clk)
begin
if (reset)
lookup_out_valid <= 1'b0;
else begin
lookup_out_valid <= 1'b0;
if (lookup_valid_sig)
lookup_out_valid <= 1'b1;
end
end
// other outputs
assign lookup_out_ports = ports_reg;
assign lookup_out_prio = prio_reg;
assign lookup_out_skip = skip_frame_reg;
assign lookup_out_timestamp = timestamp_reg;
endmodule
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
module pixelq_op_AXIvideo2Mat (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_continue,
ap_idle,
ap_ready,
AXI_video_strm_V_data_V_dout,
AXI_video_strm_V_data_V_empty_n,
AXI_video_strm_V_data_V_read,
AXI_video_strm_V_keep_V_dout,
AXI_video_strm_V_keep_V_empty_n,
AXI_video_strm_V_keep_V_read,
AXI_video_strm_V_strb_V_dout,
AXI_video_strm_V_strb_V_empty_n,
AXI_video_strm_V_strb_V_read,
AXI_video_strm_V_user_V_dout,
AXI_video_strm_V_user_V_empty_n,
AXI_video_strm_V_user_V_read,
AXI_video_strm_V_last_V_dout,
AXI_video_strm_V_last_V_empty_n,
AXI_video_strm_V_last_V_read,
AXI_video_strm_V_id_V_dout,
AXI_video_strm_V_id_V_empty_n,
AXI_video_strm_V_id_V_read,
AXI_video_strm_V_dest_V_dout,
AXI_video_strm_V_dest_V_empty_n,
AXI_video_strm_V_dest_V_read,
img_rows_V_read,
img_cols_V_read,
img_data_stream_0_V_din,
img_data_stream_0_V_full_n,
img_data_stream_0_V_write,
img_data_stream_1_V_din,
img_data_stream_1_V_full_n,
img_data_stream_1_V_write,
img_data_stream_2_V_din,
img_data_stream_2_V_full_n,
img_data_stream_2_V_write
);
parameter ap_const_logic_1 = 1'b1;
parameter ap_const_logic_0 = 1'b0;
parameter ap_ST_st1_fsm_0 = 7'b1;
parameter ap_ST_st2_fsm_1 = 7'b10;
parameter ap_ST_st3_fsm_2 = 7'b100;
parameter ap_ST_st4_fsm_3 = 7'b1000;
parameter ap_ST_pp1_stg0_fsm_4 = 7'b10000;
parameter ap_ST_st7_fsm_5 = 7'b100000;
parameter ap_ST_st8_fsm_6 = 7'b1000000;
parameter ap_const_lv32_0 = 32'b00000000000000000000000000000000;
parameter ap_const_lv1_1 = 1'b1;
parameter ap_const_lv32_1 = 32'b1;
parameter ap_const_lv32_3 = 32'b11;
parameter ap_const_lv32_4 = 32'b100;
parameter ap_const_lv1_0 = 1'b0;
parameter ap_const_lv32_5 = 32'b101;
parameter ap_const_lv32_6 = 32'b110;
parameter ap_const_lv32_2 = 32'b10;
parameter ap_const_lv12_0 = 12'b000000000000;
parameter ap_const_lv12_1 = 12'b1;
parameter ap_const_lv32_8 = 32'b1000;
parameter ap_const_lv32_F = 32'b1111;
parameter ap_const_lv32_10 = 32'b10000;
parameter ap_const_lv32_17 = 32'b10111;
parameter ap_true = 1'b1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
input ap_continue;
output ap_idle;
output ap_ready;
input [23:0] AXI_video_strm_V_data_V_dout;
input AXI_video_strm_V_data_V_empty_n;
output AXI_video_strm_V_data_V_read;
input [2:0] AXI_video_strm_V_keep_V_dout;
input AXI_video_strm_V_keep_V_empty_n;
output AXI_video_strm_V_keep_V_read;
input [2:0] AXI_video_strm_V_strb_V_dout;
input AXI_video_strm_V_strb_V_empty_n;
output AXI_video_strm_V_strb_V_read;
input [0:0] AXI_video_strm_V_user_V_dout;
input AXI_video_strm_V_user_V_empty_n;
output AXI_video_strm_V_user_V_read;
input [0:0] AXI_video_strm_V_last_V_dout;
input AXI_video_strm_V_last_V_empty_n;
output AXI_video_strm_V_last_V_read;
input [0:0] AXI_video_strm_V_id_V_dout;
input AXI_video_strm_V_id_V_empty_n;
output AXI_video_strm_V_id_V_read;
input [0:0] AXI_video_strm_V_dest_V_dout;
input AXI_video_strm_V_dest_V_empty_n;
output AXI_video_strm_V_dest_V_read;
input [11:0] img_rows_V_read;
input [11:0] img_cols_V_read;
output [7:0] img_data_stream_0_V_din;
input img_data_stream_0_V_full_n;
output img_data_stream_0_V_write;
output [7:0] img_data_stream_1_V_din;
input img_data_stream_1_V_full_n;
output img_data_stream_1_V_write;
output [7:0] img_data_stream_2_V_din;
input img_data_stream_2_V_full_n;
output img_data_stream_2_V_write;
reg ap_done;
reg ap_idle;
reg ap_ready;
reg img_data_stream_0_V_write;
reg img_data_stream_1_V_write;
reg img_data_stream_2_V_write;
reg ap_done_reg = 1'b0;
(* fsm_encoding = "none" *) reg [6:0] ap_CS_fsm = 7'b1;
reg ap_sig_cseq_ST_st1_fsm_0;
reg ap_sig_bdd_26;
reg [11:0] p_1_reg_218;
reg [0:0] eol_1_reg_229;
reg [23:0] axi_data_V_1_reg_240;
reg [0:0] eol_reg_251;
reg ap_sig_bdd_94;
reg [23:0] tmp_data_V_reg_439;
reg ap_sig_cseq_ST_st2_fsm_1;
reg ap_sig_bdd_106;
wire AXI_video_strm_V_id_V0_status;
reg [0:0] tmp_last_V_reg_447;
wire [0:0] exitcond1_fu_353_p2;
reg ap_sig_cseq_ST_st4_fsm_3;
reg ap_sig_bdd_121;
wire [11:0] i_V_fu_358_p2;
reg [11:0] i_V_reg_463;
wire [0:0] exitcond2_fu_364_p2;
reg [0:0] exitcond2_reg_468;
reg ap_sig_cseq_ST_pp1_stg0_fsm_4;
reg ap_sig_bdd_132;
reg ap_reg_ppiten_pp1_it0 = 1'b0;
wire [0:0] brmerge_fu_378_p2;
reg ap_sig_bdd_151;
reg ap_reg_ppiten_pp1_it1 = 1'b0;
wire [11:0] j_V_fu_369_p2;
reg ap_sig_cseq_ST_st7_fsm_5;
reg ap_sig_bdd_167;
reg ap_sig_bdd_172;
reg [0:0] axi_last_V_3_reg_298;
reg [0:0] axi_last_V1_reg_187;
reg ap_sig_cseq_ST_st8_fsm_6;
reg ap_sig_bdd_190;
reg ap_sig_cseq_ST_st3_fsm_2;
reg ap_sig_bdd_197;
reg [23:0] axi_data_V_3_reg_310;
reg [23:0] axi_data_V1_reg_197;
reg [11:0] p_s_reg_207;
reg [0:0] axi_last_V_2_phi_fu_267_p4;
reg [23:0] p_Val2_s_phi_fu_279_p4;
reg [0:0] eol_2_phi_fu_291_p4;
wire [0:0] ap_reg_phiprechg_axi_last_V_2_reg_263pp1_it1;
wire [23:0] ap_reg_phiprechg_p_Val2_s_reg_275pp1_it1;
wire [0:0] ap_reg_phiprechg_eol_2_reg_287pp1_it1;
wire [0:0] axi_last_V_1_mux_fu_390_p2;
reg [0:0] eol_3_reg_322;
reg AXI_video_strm_V_id_V0_update;
reg [0:0] sof_1_fu_132;
wire [0:0] not_sof_2_fu_384_p2;
wire [0:0] tmp_user_V_fu_344_p1;
reg [6:0] ap_NS_fsm;
reg ap_sig_bdd_253;
/// the current state (ap_CS_fsm) of the state machine. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_CS_fsm
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_st1_fsm_0;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
/// ap_done_reg assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_done_reg
if (ap_rst == 1'b1) begin
ap_done_reg <= ap_const_logic_0;
end else begin
if ((ap_const_logic_1 == ap_continue)) begin
ap_done_reg <= ap_const_logic_0;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st4_fsm_3) & ~(exitcond1_fu_353_p2 == ap_const_lv1_0))) begin
ap_done_reg <= ap_const_logic_1;
end
end
end
/// ap_reg_ppiten_pp1_it0 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp1_it0
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp1_it0 <= ap_const_logic_0;
end else begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp1_stg0_fsm_4) & ~(ap_sig_bdd_151 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1)) & ~(exitcond2_fu_364_p2 == ap_const_lv1_0))) begin
ap_reg_ppiten_pp1_it0 <= ap_const_logic_0;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st4_fsm_3) & (exitcond1_fu_353_p2 == ap_const_lv1_0))) begin
ap_reg_ppiten_pp1_it0 <= ap_const_logic_1;
end
end
end
/// ap_reg_ppiten_pp1_it1 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp1_it1
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp1_it1 <= ap_const_logic_0;
end else begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp1_stg0_fsm_4) & ~(ap_sig_bdd_151 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1)))) begin
ap_reg_ppiten_pp1_it1 <= ap_reg_ppiten_pp1_it0;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st4_fsm_3) & (exitcond1_fu_353_p2 == ap_const_lv1_0))) begin
ap_reg_ppiten_pp1_it1 <= ap_const_logic_0;
end
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st3_fsm_2)) begin
axi_data_V1_reg_197 <= tmp_data_V_reg_439;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st8_fsm_6)) begin
axi_data_V1_reg_197 <= axi_data_V_3_reg_310;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp1_stg0_fsm_4) & (exitcond2_reg_468 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & ~(ap_sig_bdd_151 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1)))) begin
axi_data_V_1_reg_240 <= p_Val2_s_phi_fu_279_p4;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st4_fsm_3) & (exitcond1_fu_353_p2 == ap_const_lv1_0))) begin
axi_data_V_1_reg_240 <= axi_data_V1_reg_197;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp1_stg0_fsm_4) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & ~(ap_sig_bdd_151 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1)) & ~(exitcond2_reg_468 == ap_const_lv1_0))) begin
axi_data_V_3_reg_310 <= axi_data_V_1_reg_240;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st7_fsm_5) & (ap_const_lv1_0 == eol_3_reg_322) & ~ap_sig_bdd_172)) begin
axi_data_V_3_reg_310 <= AXI_video_strm_V_data_V_dout;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st3_fsm_2)) begin
axi_last_V1_reg_187 <= tmp_last_V_reg_447;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st8_fsm_6)) begin
axi_last_V1_reg_187 <= axi_last_V_3_reg_298;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp1_stg0_fsm_4) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & ~(ap_sig_bdd_151 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1)) & ~(exitcond2_reg_468 == ap_const_lv1_0))) begin
axi_last_V_3_reg_298 <= eol_1_reg_229;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st7_fsm_5) & (ap_const_lv1_0 == eol_3_reg_322) & ~ap_sig_bdd_172)) begin
axi_last_V_3_reg_298 <= AXI_video_strm_V_last_V_dout;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp1_stg0_fsm_4) & (exitcond2_reg_468 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & ~(ap_sig_bdd_151 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1)))) begin
eol_1_reg_229 <= axi_last_V_2_phi_fu_267_p4;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st4_fsm_3) & (exitcond1_fu_353_p2 == ap_const_lv1_0))) begin
eol_1_reg_229 <= axi_last_V1_reg_187;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp1_stg0_fsm_4) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & ~(ap_sig_bdd_151 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1)) & ~(exitcond2_reg_468 == ap_const_lv1_0))) begin
eol_3_reg_322 <= eol_reg_251;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st7_fsm_5) & (ap_const_lv1_0 == eol_3_reg_322) & ~ap_sig_bdd_172)) begin
eol_3_reg_322 <= AXI_video_strm_V_last_V_dout;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp1_stg0_fsm_4) & (exitcond2_reg_468 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & ~(ap_sig_bdd_151 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1)))) begin
eol_reg_251 <= eol_2_phi_fu_291_p4;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st4_fsm_3) & (exitcond1_fu_353_p2 == ap_const_lv1_0))) begin
eol_reg_251 <= ap_const_lv1_0;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp1_stg0_fsm_4) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & ~(ap_sig_bdd_151 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1)) & (exitcond2_fu_364_p2 == ap_const_lv1_0))) begin
p_1_reg_218 <= j_V_fu_369_p2;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st4_fsm_3) & (exitcond1_fu_353_p2 == ap_const_lv1_0))) begin
p_1_reg_218 <= ap_const_lv12_0;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st3_fsm_2)) begin
p_s_reg_207 <= ap_const_lv12_0;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st8_fsm_6)) begin
p_s_reg_207 <= i_V_reg_463;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp1_stg0_fsm_4) & (exitcond2_reg_468 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & ~(ap_sig_bdd_151 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1)))) begin
sof_1_fu_132 <= ap_const_lv1_0;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st3_fsm_2)) begin
sof_1_fu_132 <= ap_const_lv1_1;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp1_stg0_fsm_4) & ~(ap_sig_bdd_151 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1)))) begin
exitcond2_reg_468 <= exitcond2_fu_364_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st4_fsm_3)) begin
i_V_reg_463 <= i_V_fu_358_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & ~(AXI_video_strm_V_id_V0_status == ap_const_logic_0))) begin
tmp_data_V_reg_439 <= AXI_video_strm_V_data_V_dout;
tmp_last_V_reg_447 <= AXI_video_strm_V_last_V_dout;
end
end
/// AXI_video_strm_V_id_V0_update assign process. ///
always @ (ap_sig_cseq_ST_st2_fsm_1 or AXI_video_strm_V_id_V0_status or exitcond2_reg_468 or ap_sig_cseq_ST_pp1_stg0_fsm_4 or brmerge_fu_378_p2 or ap_sig_bdd_151 or ap_reg_ppiten_pp1_it1 or ap_sig_cseq_ST_st7_fsm_5 or ap_sig_bdd_172 or eol_3_reg_322)
begin
if ((((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & ~(AXI_video_strm_V_id_V0_status == ap_const_logic_0)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st7_fsm_5) & (ap_const_lv1_0 == eol_3_reg_322) & ~ap_sig_bdd_172) | ((ap_const_logic_1 == ap_sig_cseq_ST_pp1_stg0_fsm_4) & (exitcond2_reg_468 == ap_const_lv1_0) & (ap_const_lv1_0 == brmerge_fu_378_p2) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & ~(ap_sig_bdd_151 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1))))) begin
AXI_video_strm_V_id_V0_update = ap_const_logic_1;
end else begin
AXI_video_strm_V_id_V0_update = ap_const_logic_0;
end
end
/// ap_done assign process. ///
always @ (ap_done_reg or exitcond1_fu_353_p2 or ap_sig_cseq_ST_st4_fsm_3)
begin
if (((ap_const_logic_1 == ap_done_reg) | ((ap_const_logic_1 == ap_sig_cseq_ST_st4_fsm_3) & ~(exitcond1_fu_353_p2 == ap_const_lv1_0)))) begin
ap_done = ap_const_logic_1;
end else begin
ap_done = ap_const_logic_0;
end
end
/// ap_idle assign process. ///
always @ (ap_start or ap_sig_cseq_ST_st1_fsm_0)
begin
if ((~(ap_const_logic_1 == ap_start) & (ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0))) begin
ap_idle = ap_const_logic_1;
end else begin
ap_idle = ap_const_logic_0;
end
end
/// ap_ready assign process. ///
always @ (exitcond1_fu_353_p2 or ap_sig_cseq_ST_st4_fsm_3)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st4_fsm_3) & ~(exitcond1_fu_353_p2 == ap_const_lv1_0))) begin
ap_ready = ap_const_logic_1;
end else begin
ap_ready = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_pp1_stg0_fsm_4 assign process. ///
always @ (ap_sig_bdd_132)
begin
if (ap_sig_bdd_132) begin
ap_sig_cseq_ST_pp1_stg0_fsm_4 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_pp1_stg0_fsm_4 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st1_fsm_0 assign process. ///
always @ (ap_sig_bdd_26)
begin
if (ap_sig_bdd_26) begin
ap_sig_cseq_ST_st1_fsm_0 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st1_fsm_0 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st2_fsm_1 assign process. ///
always @ (ap_sig_bdd_106)
begin
if (ap_sig_bdd_106) begin
ap_sig_cseq_ST_st2_fsm_1 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st2_fsm_1 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st3_fsm_2 assign process. ///
always @ (ap_sig_bdd_197)
begin
if (ap_sig_bdd_197) begin
ap_sig_cseq_ST_st3_fsm_2 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st3_fsm_2 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st4_fsm_3 assign process. ///
always @ (ap_sig_bdd_121)
begin
if (ap_sig_bdd_121) begin
ap_sig_cseq_ST_st4_fsm_3 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st4_fsm_3 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st7_fsm_5 assign process. ///
always @ (ap_sig_bdd_167)
begin
if (ap_sig_bdd_167) begin
ap_sig_cseq_ST_st7_fsm_5 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st7_fsm_5 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st8_fsm_6 assign process. ///
always @ (ap_sig_bdd_190)
begin
if (ap_sig_bdd_190) begin
ap_sig_cseq_ST_st8_fsm_6 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st8_fsm_6 = ap_const_logic_0;
end
end
/// axi_last_V_2_phi_fu_267_p4 assign process. ///
always @ (AXI_video_strm_V_last_V_dout or eol_1_reg_229 or brmerge_fu_378_p2 or ap_reg_phiprechg_axi_last_V_2_reg_263pp1_it1 or ap_sig_bdd_253)
begin
if (ap_sig_bdd_253) begin
if (~(ap_const_lv1_0 == brmerge_fu_378_p2)) begin
axi_last_V_2_phi_fu_267_p4 = eol_1_reg_229;
end else if ((ap_const_lv1_0 == brmerge_fu_378_p2)) begin
axi_last_V_2_phi_fu_267_p4 = AXI_video_strm_V_last_V_dout;
end else begin
axi_last_V_2_phi_fu_267_p4 = ap_reg_phiprechg_axi_last_V_2_reg_263pp1_it1;
end
end else begin
axi_last_V_2_phi_fu_267_p4 = ap_reg_phiprechg_axi_last_V_2_reg_263pp1_it1;
end
end
/// eol_2_phi_fu_291_p4 assign process. ///
always @ (AXI_video_strm_V_last_V_dout or brmerge_fu_378_p2 or ap_reg_phiprechg_eol_2_reg_287pp1_it1 or axi_last_V_1_mux_fu_390_p2 or ap_sig_bdd_253)
begin
if (ap_sig_bdd_253) begin
if (~(ap_const_lv1_0 == brmerge_fu_378_p2)) begin
eol_2_phi_fu_291_p4 = axi_last_V_1_mux_fu_390_p2;
end else if ((ap_const_lv1_0 == brmerge_fu_378_p2)) begin
eol_2_phi_fu_291_p4 = AXI_video_strm_V_last_V_dout;
end else begin
eol_2_phi_fu_291_p4 = ap_reg_phiprechg_eol_2_reg_287pp1_it1;
end
end else begin
eol_2_phi_fu_291_p4 = ap_reg_phiprechg_eol_2_reg_287pp1_it1;
end
end
/// img_data_stream_0_V_write assign process. ///
always @ (exitcond2_reg_468 or ap_sig_cseq_ST_pp1_stg0_fsm_4 or ap_sig_bdd_151 or ap_reg_ppiten_pp1_it1)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp1_stg0_fsm_4) & (exitcond2_reg_468 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & ~(ap_sig_bdd_151 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1)))) begin
img_data_stream_0_V_write = ap_const_logic_1;
end else begin
img_data_stream_0_V_write = ap_const_logic_0;
end
end
/// img_data_stream_1_V_write assign process. ///
always @ (exitcond2_reg_468 or ap_sig_cseq_ST_pp1_stg0_fsm_4 or ap_sig_bdd_151 or ap_reg_ppiten_pp1_it1)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp1_stg0_fsm_4) & (exitcond2_reg_468 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & ~(ap_sig_bdd_151 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1)))) begin
img_data_stream_1_V_write = ap_const_logic_1;
end else begin
img_data_stream_1_V_write = ap_const_logic_0;
end
end
/// img_data_stream_2_V_write assign process. ///
always @ (exitcond2_reg_468 or ap_sig_cseq_ST_pp1_stg0_fsm_4 or ap_sig_bdd_151 or ap_reg_ppiten_pp1_it1)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp1_stg0_fsm_4) & (exitcond2_reg_468 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & ~(ap_sig_bdd_151 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1)))) begin
img_data_stream_2_V_write = ap_const_logic_1;
end else begin
img_data_stream_2_V_write = ap_const_logic_0;
end
end
/// p_Val2_s_phi_fu_279_p4 assign process. ///
always @ (AXI_video_strm_V_data_V_dout or axi_data_V_1_reg_240 or brmerge_fu_378_p2 or ap_reg_phiprechg_p_Val2_s_reg_275pp1_it1 or ap_sig_bdd_253)
begin
if (ap_sig_bdd_253) begin
if (~(ap_const_lv1_0 == brmerge_fu_378_p2)) begin
p_Val2_s_phi_fu_279_p4 = axi_data_V_1_reg_240;
end else if ((ap_const_lv1_0 == brmerge_fu_378_p2)) begin
p_Val2_s_phi_fu_279_p4 = AXI_video_strm_V_data_V_dout;
end else begin
p_Val2_s_phi_fu_279_p4 = ap_reg_phiprechg_p_Val2_s_reg_275pp1_it1;
end
end else begin
p_Val2_s_phi_fu_279_p4 = ap_reg_phiprechg_p_Val2_s_reg_275pp1_it1;
end
end
/// the next state (ap_NS_fsm) of the state machine. ///
always @ (ap_CS_fsm or ap_sig_bdd_94 or AXI_video_strm_V_id_V0_status or exitcond1_fu_353_p2 or ap_sig_cseq_ST_pp1_stg0_fsm_4 or ap_reg_ppiten_pp1_it0 or ap_sig_bdd_151 or ap_reg_ppiten_pp1_it1 or ap_sig_bdd_172 or eol_3_reg_322 or tmp_user_V_fu_344_p1)
begin
case (ap_CS_fsm)
ap_ST_st1_fsm_0 :
begin
if (~ap_sig_bdd_94) begin
ap_NS_fsm = ap_ST_st2_fsm_1;
end else begin
ap_NS_fsm = ap_ST_st1_fsm_0;
end
end
ap_ST_st2_fsm_1 :
begin
if ((~(AXI_video_strm_V_id_V0_status == ap_const_logic_0) & (ap_const_lv1_0 == tmp_user_V_fu_344_p1))) begin
ap_NS_fsm = ap_ST_st2_fsm_1;
end else if ((~(AXI_video_strm_V_id_V0_status == ap_const_logic_0) & ~(ap_const_lv1_0 == tmp_user_V_fu_344_p1))) begin
ap_NS_fsm = ap_ST_st3_fsm_2;
end else begin
ap_NS_fsm = ap_ST_st2_fsm_1;
end
end
ap_ST_st3_fsm_2 :
begin
ap_NS_fsm = ap_ST_st4_fsm_3;
end
ap_ST_st4_fsm_3 :
begin
if (~(exitcond1_fu_353_p2 == ap_const_lv1_0)) begin
ap_NS_fsm = ap_ST_st1_fsm_0;
end else begin
ap_NS_fsm = ap_ST_pp1_stg0_fsm_4;
end
end
ap_ST_pp1_stg0_fsm_4 :
begin
if (~((ap_const_logic_1 == ap_sig_cseq_ST_pp1_stg0_fsm_4) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & ~(ap_sig_bdd_151 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1)) & ~(ap_const_logic_1 == ap_reg_ppiten_pp1_it0))) begin
ap_NS_fsm = ap_ST_pp1_stg0_fsm_4;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_pp1_stg0_fsm_4) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & ~(ap_sig_bdd_151 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1)) & ~(ap_const_logic_1 == ap_reg_ppiten_pp1_it0))) begin
ap_NS_fsm = ap_ST_st7_fsm_5;
end else begin
ap_NS_fsm = ap_ST_pp1_stg0_fsm_4;
end
end
ap_ST_st7_fsm_5 :
begin
if (((ap_const_lv1_0 == eol_3_reg_322) & ~ap_sig_bdd_172)) begin
ap_NS_fsm = ap_ST_st7_fsm_5;
end else if ((~ap_sig_bdd_172 & ~(ap_const_lv1_0 == eol_3_reg_322))) begin
ap_NS_fsm = ap_ST_st8_fsm_6;
end else begin
ap_NS_fsm = ap_ST_st7_fsm_5;
end
end
ap_ST_st8_fsm_6 :
begin
ap_NS_fsm = ap_ST_st4_fsm_3;
end
default :
begin
ap_NS_fsm = 'bx;
end
endcase
end
assign AXI_video_strm_V_data_V_read = AXI_video_strm_V_id_V0_update;
assign AXI_video_strm_V_dest_V_read = AXI_video_strm_V_id_V0_update;
assign AXI_video_strm_V_id_V0_status = (AXI_video_strm_V_data_V_empty_n & AXI_video_strm_V_keep_V_empty_n & AXI_video_strm_V_strb_V_empty_n & AXI_video_strm_V_user_V_empty_n & AXI_video_strm_V_last_V_empty_n & AXI_video_strm_V_id_V_empty_n & AXI_video_strm_V_dest_V_empty_n);
assign AXI_video_strm_V_id_V_read = AXI_video_strm_V_id_V0_update;
assign AXI_video_strm_V_keep_V_read = AXI_video_strm_V_id_V0_update;
assign AXI_video_strm_V_last_V_read = AXI_video_strm_V_id_V0_update;
assign AXI_video_strm_V_strb_V_read = AXI_video_strm_V_id_V0_update;
assign AXI_video_strm_V_user_V_read = AXI_video_strm_V_id_V0_update;
assign ap_reg_phiprechg_axi_last_V_2_reg_263pp1_it1 = 'bx;
assign ap_reg_phiprechg_eol_2_reg_287pp1_it1 = 'bx;
assign ap_reg_phiprechg_p_Val2_s_reg_275pp1_it1 = 'bx;
/// ap_sig_bdd_106 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_106 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_1]);
end
/// ap_sig_bdd_121 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_121 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_3]);
end
/// ap_sig_bdd_132 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_132 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_4]);
end
/// ap_sig_bdd_151 assign process. ///
always @ (img_data_stream_0_V_full_n or img_data_stream_1_V_full_n or img_data_stream_2_V_full_n or AXI_video_strm_V_id_V0_status or exitcond2_reg_468 or brmerge_fu_378_p2)
begin
ap_sig_bdd_151 = (((AXI_video_strm_V_id_V0_status == ap_const_logic_0) & (exitcond2_reg_468 == ap_const_lv1_0) & (ap_const_lv1_0 == brmerge_fu_378_p2)) | ((exitcond2_reg_468 == ap_const_lv1_0) & (img_data_stream_0_V_full_n == ap_const_logic_0)) | ((exitcond2_reg_468 == ap_const_lv1_0) & (img_data_stream_1_V_full_n == ap_const_logic_0)) | ((exitcond2_reg_468 == ap_const_lv1_0) & (img_data_stream_2_V_full_n == ap_const_logic_0)));
end
/// ap_sig_bdd_167 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_167 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_5]);
end
/// ap_sig_bdd_172 assign process. ///
always @ (AXI_video_strm_V_id_V0_status or eol_3_reg_322)
begin
ap_sig_bdd_172 = ((AXI_video_strm_V_id_V0_status == ap_const_logic_0) & (ap_const_lv1_0 == eol_3_reg_322));
end
/// ap_sig_bdd_190 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_190 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_6]);
end
/// ap_sig_bdd_197 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_197 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_2]);
end
/// ap_sig_bdd_253 assign process. ///
always @ (exitcond2_reg_468 or ap_sig_cseq_ST_pp1_stg0_fsm_4 or ap_reg_ppiten_pp1_it1)
begin
ap_sig_bdd_253 = ((ap_const_logic_1 == ap_sig_cseq_ST_pp1_stg0_fsm_4) & (exitcond2_reg_468 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1));
end
/// ap_sig_bdd_26 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_26 = (ap_CS_fsm[ap_const_lv32_0] == ap_const_lv1_1);
end
/// ap_sig_bdd_94 assign process. ///
always @ (ap_start or ap_done_reg)
begin
ap_sig_bdd_94 = ((ap_start == ap_const_logic_0) | (ap_done_reg == ap_const_logic_1));
end
assign axi_last_V_1_mux_fu_390_p2 = (eol_1_reg_229 | not_sof_2_fu_384_p2);
assign brmerge_fu_378_p2 = (sof_1_fu_132 | eol_reg_251);
assign exitcond1_fu_353_p2 = (p_s_reg_207 == img_rows_V_read? 1'b1: 1'b0);
assign exitcond2_fu_364_p2 = (p_1_reg_218 == img_cols_V_read? 1'b1: 1'b0);
assign i_V_fu_358_p2 = (p_s_reg_207 + ap_const_lv12_1);
assign img_data_stream_0_V_din = p_Val2_s_phi_fu_279_p4[7:0];
assign img_data_stream_1_V_din = {{p_Val2_s_phi_fu_279_p4[ap_const_lv32_F : ap_const_lv32_8]}};
assign img_data_stream_2_V_din = {{p_Val2_s_phi_fu_279_p4[ap_const_lv32_17 : ap_const_lv32_10]}};
assign j_V_fu_369_p2 = (p_1_reg_218 + ap_const_lv12_1);
assign not_sof_2_fu_384_p2 = (sof_1_fu_132 ^ ap_const_lv1_1);
assign tmp_user_V_fu_344_p1 = AXI_video_strm_V_user_V_dout;
endmodule //pixelq_op_AXIvideo2Mat
|
/* -------------------------------------------------------------------------------
* (C)2007 Robert Mullins
* Computer Architecture Group, Computer Laboratory
* University of Cambridge, UK.
* -------------------------------------------------------------------------------
*
* FIFO
* ====
*
* Implementation notes:
*
* - Read and write pointers are simple ring counters
*
* - Number of items held in FIFO is recorded in shift register
* (Full/empty flags are most and least-significant bits of register)
*
* Examples:
*
* fifo_v #(.fifo_elements_t(int), .size(8)) myfifo (.*);
*
* Instantiates a FIFO that can hold up to 8 integers.
/************************************************************************************
*
* FIFO
*
************************************************************************************/
typedef struct packed
{
logic full, empty, nearly_full, nearly_empty;
} fifov_flags_t;
module LAG_fifo_v (push, pop, data_in, data_out, flags, clk, rst_n);
// max no. of entries
parameter size = 8;
input push, pop;
output fifov_flags_t flags;
input fifo_elements_t data_in;
output fifo_elements_t data_out;
input clk, rst_n;
logic fifo_push, fifo_pop;
fifo_elements_t fifo_data_out, data_out_tmp;
fifo_buffer #(.size(size))
fifo_buf (push, pop, data_in, data_out_tmp, clk, rst_n);
assign data_out = flags.empty ? '0 : data_out_tmp;
fifo_flags #(.size(size))
gen_flags(push, pop, flags, clk, rst_n);
endmodule // fifo_v
/************************************************************************************
*
* Maintain FIFO flags (full, nearly_full, nearly_empty and empty)
*
* This design uses a shift register to ensure flags are available quickly.
*
************************************************************************************/
module fifo_flags (push, pop, flags, clk, rst_n);
input push, pop;
output fifov_flags_t flags;
input clk, rst_n;
parameter size = 8;
reg [size:0] counter; // counter must hold 1..size + empty state
logic was_push, was_pop;
fifov_flags_t flags_reg;
logic add, sub, same;
/*
* maintain flags
*
*
* maintain shift register as counter to determine if FIFO is full or empty
* full=counter[size-1], empty=counter[0], etc..
* init: counter=1'b1;
* (push & !pop): shift left
* (pop & !push): shift right
*/
always@(posedge clk) begin
if (!rst_n) begin
counter<={{size{1'b0}},1'b1};
was_push<=1'b0;
was_pop<=1'b0;
end else begin
if (add) begin
assert (counter!={1'b1,{size{1'b0}}}) else $fatal;
counter <= {counter[size-1:0], 1'b0};
end else if (sub) begin
assert (counter!={{size{1'b0}},1'b1}) else $fatal;
counter <= {1'b0, counter[size:1]};
end
assert (counter!=0) else $fatal;
was_push<=push;
was_pop<=pop;
assert (push!==1'bx) else $fatal;
assert (pop!==1'bx) else $fatal;
end // else: !if(!rst_n)
end
assign add = was_push && !was_pop;
assign sub = was_pop && !was_push;
assign same = !(add || sub);
assign flags.full = (counter[size] && !sub) || (counter[size-1] && add);
assign flags.empty = (counter[0] && !add) || (counter[1] && sub);
assign flags.nearly_full = (counter[size-1:0] && same) || (counter[size] && sub) || (counter[size-2] && add);
assign flags.nearly_empty = (counter[1] && same) || (counter[0] && add) || (counter[2] && sub);
endmodule // fifo_flags
/************************************************************************************
*
* Simple core FIFO module
*
************************************************************************************/
module fifo_buffer (push, pop, data_in, data_out, clk, rst_n);
// max no. of entries
parameter int unsigned size = 4;
input push, pop;
input fifo_elements_t data_in;
output fifo_elements_t data_out;
input clk, rst_n;
// reg [size-1:0] rd_ptr, wt_ptr;
logic unsigned [size-1:0] rd_ptr, wt_ptr;
fifo_elements_t fifo_mem[0:size-1];
logic select_bypass;
integer i,j;
always@(posedge clk) begin
assert (size>=2) else $fatal();
if (!rst_n) begin
rd_ptr<={{size-1{1'b0}},1'b1};
wt_ptr<={{size-1{1'b0}},1'b1};
end else begin
if (push) begin
// enqueue new data
for (i=0; i<size; i++) begin
if (wt_ptr[i]==1'b1) begin
fifo_mem[i] <= data_in;
end
end
end
if (push) begin
// rotate write pointer
wt_ptr <= {wt_ptr[size-2:0], wt_ptr[size-1]};
end
if (pop) begin
// rotate read pointer
rd_ptr <= {rd_ptr[size-2:0], rd_ptr[size-1]};
end
end // else: !if(!rst_n)
end // always@ (posedge clk)
/*
*
* FIFO output is item pointed to by read pointer
*
*/
always_comb begin
//
// one bit of read pointer is always set, ensure synthesis tool
// doesn't add logic to force a default
//
data_out = 'x;
for (j=0; j<size; j++) begin
if (rd_ptr[j]==1'b1) begin
// output entry pointed to by read pointer
data_out = fifo_mem[j];
end
end
end
endmodule // fifo_buffer
|
/*
* File: imx_uocm.v
* Project: pippo
* Designer: kiss@pwrsemi
* Mainteiner: kiss@pwrsemi
* Checker:
* Description:
* general purpose synchronous single-port memory
* Notes:
* 1, currently signal "oe" is NOT driven by this module, it should be used by
* memory controller to tag validation of read data.
*/
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "def_pippo.v"
module imx_uocm(
clk,
ce, oe, we,
addr, di, doq
);
parameter aw = `UOCM_Word_BW; // 2**9 word = 2K Bytes (one xilinx block ram)
parameter dw = 32;
input clk;
input ce;
input we;
input oe;
input [aw-1:0] addr;
input [dw-1:0] di;
output [dw-1:0] doq;
//
// Internal wires and registers
//
reg [dw-1:0] mem [(1<<aw)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
reg [aw-1:0] addr_reg;
//
// boot flash
//
initial begin
$readmemh("boot_binary.dat", mem);
end
//
// read access
//
// memory read address register for synchronous access
always @(posedge clk) begin
if (ce)
addr_reg <= addr;
end
// Data output
assign doq = mem[addr_reg];
//
// write access
//
always @(posedge clk) begin
if (we && ce)
mem[addr] <= di;
end
endmodule
|
module subdivision_step_motor_driver (
// Qsys bus interface
input rsi_MRST_reset,
input csi_MCLK_clk,
input [31:0] avs_ctrl_writedata,
output [31:0] avs_ctrl_readdata,
input [3:0] avs_ctrl_byteenable,
input [2:0] avs_ctrl_address,
input avs_ctrl_write,
input avs_ctrl_read,
output avs_ctrl_waitrequest,
input rsi_PWMRST_reset,
input csi_PWMCLK_clk,
// step motor interface
output AX,
output AY,
output BX,
output BY,
output AE,
output BE
);
// Qsys bus controller
reg step;
reg forward_back;
reg on_off;
reg [31:0] PWM_width_A;
reg [31:0] PWM_width_B;
reg [31:0] PWM_frequent;
reg [31:0] read_data;
assign avs_ctrl_readdata = read_data;
always@(posedge csi_MCLK_clk or posedge rsi_MRST_reset)
begin
if(rsi_MRST_reset) begin
read_data <= 0;
on_off <= 0;
end
else if(avs_ctrl_write)
begin
case(avs_ctrl_address)
0: begin
if(avs_ctrl_byteenable[3]) PWM_frequent[31:24] <= avs_ctrl_writedata[31:24];
if(avs_ctrl_byteenable[2]) PWM_frequent[23:16] <= avs_ctrl_writedata[23:16];
if(avs_ctrl_byteenable[1]) PWM_frequent[15:8] <= avs_ctrl_writedata[15:8];
if(avs_ctrl_byteenable[0]) PWM_frequent[7:0] <= avs_ctrl_writedata[7:0];
end
1: begin
if(avs_ctrl_byteenable[3]) PWM_width_A[31:24] <= avs_ctrl_writedata[31:24];
if(avs_ctrl_byteenable[2]) PWM_width_A[23:16] <= avs_ctrl_writedata[23:16];
if(avs_ctrl_byteenable[1]) PWM_width_A[15:8] <= avs_ctrl_writedata[15:8];
if(avs_ctrl_byteenable[0]) PWM_width_A[7:0] <= avs_ctrl_writedata[7:0];
end
2: begin
if(avs_ctrl_byteenable[3]) PWM_width_B[31:24] <= avs_ctrl_writedata[31:24];
if(avs_ctrl_byteenable[2]) PWM_width_B[23:16] <= avs_ctrl_writedata[23:16];
if(avs_ctrl_byteenable[1]) PWM_width_B[15:8] <= avs_ctrl_writedata[15:8];
if(avs_ctrl_byteenable[0]) PWM_width_B[7:0] <= avs_ctrl_writedata[7:0];
end
3: step <= avs_ctrl_writedata[0];
4: forward_back <= avs_ctrl_writedata[0];
5: on_off <= avs_ctrl_writedata[0];
default:;
endcase
end
else if(avs_ctrl_read)
begin
case(avs_ctrl_address)
0: read_data <= PWM_frequent;
1: read_data <= PWM_width_A;
2: read_data <= PWM_width_B;
3: read_data <= {31'b0,step};
4: read_data <= {31'b0,forward_back};
default: read_data <= 32'b0;
endcase
end
end
//PWM controller
reg [31:0] PWM_A;
reg [31:0] PWM_B;
reg PWM_out_A;
reg PWM_out_B;
always @ (posedge csi_PWMCLK_clk or posedge rsi_PWMRST_reset)
begin
if(rsi_PWMRST_reset)
PWM_A <= 32'b0;
else
begin
PWM_A <= PWM_A + PWM_frequent;
PWM_out_A <=(PWM_A > PWM_width_A) ? 0:1;
end
end
always @ (posedge csi_PWMCLK_clk or posedge rsi_PWMRST_reset)
begin
if(rsi_PWMRST_reset)
PWM_B <= 32'b0;
else
begin
PWM_B <= PWM_B + PWM_frequent;
PWM_out_B <=(PWM_B > PWM_width_B) ? 0:1;
end
end
// step motor state
reg [0:3] motor_state;
always @ (posedge step or posedge rsi_MRST_reset)
begin
if(rsi_MRST_reset)
motor_state <= 4'b1001;
else
begin
if(forward_back)
case(motor_state)
4'b1001: motor_state<= 4'b1010;
4'b1010: motor_state<= 4'b0110;
4'b0110: motor_state<= 4'b0101;
4'b0101: motor_state<= 4'b1001;
endcase
else
case(motor_state)
4'b1010: motor_state<= 4'b1001;
4'b0110: motor_state<= 4'b1010;
4'b0101: motor_state<= 4'b0110;
4'b1001: motor_state<= 4'b0101;
endcase
end
end
reg ax, ay, bx, by;
always @ (motor_state)
begin
case(motor_state)
4'b1001: begin ax <= PWM_out_A; ay <= 0; bx <= 0; by <= PWM_out_B; end
4'b1010: begin ax <= PWM_out_A; ay <= 0; bx <= PWM_out_B; by <= 0; end
4'b0110: begin ax <= 0; ay <= PWM_out_A; bx <= PWM_out_B; by <= 0; end
4'b0101: begin ax <= 0; ay <= PWM_out_A; bx <= 0; by <= PWM_out_B; end
endcase
end
//output signal
assign AE = !on_off;
assign BE = !on_off;
assign AX = !ax;
assign AY = !ay;
assign BX = !bx;
assign BY = !by;
endmodule
|
package mypackage;
bit [7:0] pkg_addr;
bit [7:0] pkg_data;
endpackage
module times ();
time x;
initial x = 33ns; // Note no space
endmodule : times
interface itf #(parameter num_of_cli = 0);
logic blabla;
logic [7:0] addr, data[9];
modport Master(input data, date_delayed, output addr);
endinterface : itf
module test (
itf whole_int,
itf.test modported_int,
input logic clk, rst,
input logic d_in,
output logic d_out
);
import mypackage::*;
logic d_int;
logic [7:0] data_, bork[2];
assign d_int = d_in + pkg_data;
assign modported_int.data = data_;
always_ff @(posedge clk or negedge rst) begin
if (~rst) d_out <= '0;
else d_out <= d_int;
end
property p1;
@(posedge clk)
disable iff(!rst)
$rose(d_int) |-> ##1 d_int;
endproperty
//a1: assert property(p1) else $warning("\nProperty violated\n");
c1: cover property(p1) $display("\np1_cover\n");
endmodule : test
// Different ways of declaring pins/vars
module line49_diff_pins1 (
input in_nw, // Input, no type
input [1:0] in_vec[2:0], // Input, implicit
input in_nvec, // Isn't vectorized
output logic out_logic, // Output and var
output out_also_logic // "logic" sticks
);
endmodule
module line49_diff_pins2 (in2_nw, in2_vec, out2reg);
input in2_nw;
input [1:0] in2_vec [2:0];
output reg out2_reg;
input signed in2_signed;
var var1_imp;
var [1:0] var1_imp_vec [2:0];
var reg var1_imp_reg;
var logic var1_imp_logic;
endmodule
program automatic first_prog;
int i;
endprogram
// Importing
package imp_test_pkg;
typedef logic [7:0] byte_t;
typedef logic [15:0] word_t;
function afunc(integer w); afunc=0; endfunction
endpackage
module imp_test_mod;
import imp_test_pkg::byte_t;
byte_t some_byte;
endmodule
module imp_test_mod2;
import imp_test_pkg::*;
word_t some_word;
endmodule
module imp_test_mod3
( input imp_test_pkg::word_t wordin );
localparam FROM_FUNC = imp_test_pkg::afunc(1);
endmodule
module var_unnamed_block;
initial begin
integer var_in_unnamed;
end
endmodule
module cell_with_typeparam;
addr #(.PARAMTYPE(integer)) acell ();
endmodule
module arrayed_wire;
wire [3:0][7:0] n2;
endmodule
task empty_task; // sv design book
endtask
task empty_task2; // sv design book
integer i;
endtask
task check_casts;
typedef integer integer_t;
sum = a + integer '(3);
sum = a + integer_t '(3);
sum = a + 10'(3);
endtask
module comma_assign;
int n[1:2][1:3] = '{'{0,1,2}, '{3{4}}};
endmodule
task typed_pattern;
typedef int triple [1:3];
$mydisplay(triple'{0,1,2});
endtask
virtual class VclassWCopy;
extern function new();
virtual function VclassWCopy copy(input VclassWCopy src=null);
endfunction
endclass : VclassWCopy
function VclassWCopy::new();
endfunction : new
typedef class FwdClass;
function bit [3:0] FwdClass::ffunc (bit [3:0] in);
ffunc = in;
endfunction : ffunc
function VclassWCopy VclassWCopy::copy
(input VclassWCopy to);
dst = new();
endfunction : copy
task foreach_memref;
bit [0:52] [7:0] mem;
// It's *not* legal according to the grammar to have dotted/package ids here
foreach (mem[i]) $write("i=%x ", mem[i]); $display;
endtask
typedef class PreTypedefedClass;
class PreTypedefedClass;
extern function new();
endclass
typedef class PreTypedefedClass;
class NewInNew;
function new;
s_self = new;
endfunction : new
endclass
// std package
class TryStd;
semaphore s1;
std::semaphore s2;
mailbox #(integer) m1;
std::mailbox m2;
process p1;
std::process p2;
endclass
module cg_test1;
covergroup counter1 @ (posedge cyc);
cyc_bined : coverpoint cyc {
bins zero = {0};
bins low = {1,5};
bins mid = {[5:$]};
}
value_and_toggle:
cross cyc_value, toggle;
endgroup
endmodule
task randomize_dotted();
int vbl;
assert(vbl.randomize());
endtask
module prop_parens;
LABEL: cover property (@(posedge clk) ((foo[3:0] == 4'h0) & bar));
endmodule
class this_dot_tests;
task ass;
this.super.foo = this.bar;
endtask
endclass
module sized_out
#( parameter SZ = 4 )
( output logic [SZ-1:0] o_sized );
endmodule
class solve_size;
rand byte arrayed[];
rand bit b;
// The dot below doesn't seem legal according to grammar, but
// the intent makes sense, and it appears in the VMM
constraint solve_a_b { solve arrayed.size before b; }
endclass
class vmm_stuff;
task examples;
void'(this.a.funccall(x));
this.a.taskcall();
super.new(name2);
endtask
extern static local function bit foo1();
extern virtual protected function void foo2();
protected static string foo3;
extern function bit foo4();
static local bit foo5[string];
endclass
class vmm_cl_func_colon;
typedef enum int unsigned {FIRM} restart_e;
function void do_all(vmm_cl_func_colon::restart_e kind = vmm_cl_func_colon::FIRM);
endfunction
extern function int uses_class_type();
endclass
class vmm_cl_subenv;
extern protected virtual task do_reset(vmm_cl_func_colon::restart_e kind = vmm_cl_func_colon::FIRM);
endclass
task empty_comma;
extracomma1(,);
extracomma2("a",);
extracomma3("a",,"c");
extracomma4(,"b");
endtask
task vmm_more;
file_is_a_string(`__FILE__,`__LINE__);
foreach(this.text[i]) begin $display("%s\n", this.text[i]); end
// Not part of 1800-2005 grammar, but likely in 1800-2009
queue = '{};
-> this.item_taken;
endtask
// Extern Functions/tasks when defined must scope to the class they're in to get appropriate types
function int vmm_cl_func_colon::uses_class_type(restart_e note_uses_class_type);
var restart_e also_uses_class_type;
endfunction
module hidden_checks;
typedef int T;
sub (.T(123)); // Different T
task hidden;
typedef bit T; // Different T
endtask
endmodule
typedef struct packed signed {
rand int m_a;
bit [7:0] m_b;
} t_bug91;
t_bug91 v_bug91;
module bug98(interfacex x_if);
h inst_h(.push(x_if.pop));
endmodule
module bugas;
initial begin
ASSERT_CHK: assert (0) else $error("%m -- not allowed %d", 0);
end
endmodule
typedef enum [2:0] { ENUM_RANGED_VALUE } enum_ranged_t;
typedef struct packed { logic val; } t_bug202_struct;
typedef union packed { logic val; } t_bug202_union;
class ln288;
extern virtual function string extvirtstr;
extern virtual task extvirttask;
endclass
class cl_to_init;
extern function new();
extern static function cl_to_init init();
endclass
function cl_to_init cl_to_init::init();
endfunction
function cl_to_init::new();
endfunction
cl_to_init cl_inited = cl_to_init::init();
// pure virtual functions have no endfunction.
virtual class pure_virt_func_class;
pure virtual function string pure_virt_func();
pure virtual task pure_virt_task();
endclass
class extend_base;
typedef enum { EN_A, EN_B } base_enum;
virtual function extend_base create(); return null; endfunction
endclass
class extended extends extend_base;
typedef base_enum be_t; // type must come from base class
virtual function int create (); // Must override base's create
be_t mye;
endfunction
endclass
task rand_with_ln320();
if (!randomize(v) with { v > 0 && v < maxval; }) begin end
if (randomize(null)) begin end
endtask
task apply_request(data_req, input bit randomize = 1);
if (randomize == 1) begin
data_req.randomize(); // Generic method, not std::randomize
end
endtask
task foreach_class_scope_ln330;
foreach (extended::some_array[i,j]) begin end
endtask
module clkif_334;
always @(posedge top.clk iff !top.clken_l) begin end
endmodule
module gen_ln338;
generate
case (P)
32'b0: initial begin end
default: initial begin end
endcase
endgenerate
endmodule
module par_packed;
parameter logic [31:0] P1 [3:0] = '{ 1, 2, 3, 4 } ; // unpacked array
wire struct packed { logic ecc; logic [7:0] data; } memsig;
endmodule
module not_a_bug315;
typedef int supply_net_t;
input int i;
input imp_test_pkg::byte_t i;
input supply_net_t bug316;
endmodule
module bins_bracket;
parameter N = 2;
covergroup cg_debitor @(posedge eclk);
count: coverpoint count iff (erst_n) {
// 'std' overrides std:: package, which confuses VP
//bins std[] = { [0:N] };
}
endgroup
endmodule
virtual class ovm_void;
endclass
virtual class ovm_port_base #(type IF=ovm_void) extends ovm_void;
endclass
virtual class uvm_build_phase #(type BASE=ovm_void) extends BASE;
static const string type_name = "uvm_build_phase";
endclass
class bug627sub;
endclass
class bug627 #(type TYPE=bug627sub);
typedef TYPE types_t[$];
static function types_t f();
$display("%s", { TYPE::type_name });
return types;
endfunction
endclass
interface if_bug777;
wire a;
modport master (input a);
modport slave (output a);
endinterface
module bug777 (clk, ifport);
input clk;
if_bug777 ifport ();
if_bug777.mp ifportmp;
//if_bug777.mp ifportmp (); // Not legal
// Currently unsupported, parens required so VP knows is instance
//if_bug777 ifport;
endmodule
module bug778 ();
virtual if_bug777.master bar;
endmodule
class cls778;
virtual if_bug777.master bar;
endclass : cls778;
module bug810 #(
/*parameter*/ int unsigned DW = 32);
endmodule
interface test_if (input clk);
endinterface
module bug815 (
test_if bad[2]);
endmodule
module bug868 (ifmp);
if_bug777.master ifmp;
endmodule
|
`timescale 1ns / 1ps
`include "../rtl/aDefinitions.v"
`include "../rtl/gpu_definitions.v"
`include "../rtl/z80_opcode_definitions.v"
////////////////////////////////////////////////////////////////////////////////////
//
// pGB, yet another FPGA fully functional and super fun GB classic clone!
// Copyright (C) 2015-2016 Diego Valverde ([email protected])
//
// This program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public License
// as published by the Free Software Foundation; either version 2
// of the License, or (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
//
////////////////////////////////////////////////////////////////////////////////////
module tb_simple_dzcpu;
// Inputs
reg iClock;
reg iReset;
reg rResetDone;
wire [15:0] wFramBufferData, wFrameBufferAddress;
wire wFramBufferWe;
reg [15:0] rCurrentTileRow;
// Instantiate the Unit Under Test (UUT)
pGB uut (
.iClock(iClock),
.iReset(iReset),
.oFrameBufferWe( wFramBufferWe ),
.oFrameBufferData( wFramBufferData ),
.oFrameBufferAddr( wFrameBufferAddress )
);
//Instantiate a dummy frame buffer. In real life this goes in the LCD board
reg [15:0] rFrameBuffer[8191:0];
integer log, glog, trace, sound_trace, i,Pc, vram_log_8000_8fff, vram_log_9800_9bff;
integer frame_count = 0, k, frame;
reg rSimulationDone;
reg [63:0] InstCount;
//---------------------------------------------
//generate the clock signal here
always begin
#`CLOCK_CYCLE iClock = ! iClock;
end
//---------------------------------------------
//Update writes to the framebuffer
always @ ( posedge iClock )
begin
if ( wFramBufferWe )
begin
rFrameBuffer[ wFrameBufferAddress ] = wFramBufferData;
end
end //always
reg [255:1] FrameDumpName;
integer FrameDumpCount = 0;
always @ ( posedge iClock )
begin
if ( wFrameBufferAddress == 16'd8191 && wFramBufferWe == 1'b1)//8191
begin
$swrite(FrameDumpName,"generated_frames/frame.%01d.ppm",FrameDumpCount);
frame = $fopen(FrameDumpName);
$fwrite(frame,"P2\n");
$fwrite(frame,"256 256\n");
$fwrite(frame,"4\n");
$fwrite(frame,"#SCY %04x SCX %04x LY %04x wSC_Tile %04x\n",
uut.GPU.oSCY, uut.GPU.oSCX, uut.GPU.oLY, uut.GPU.wSC_Tile);
for (k = 0; k < 8191; k=k+1)
begin
rCurrentTileRow = rFrameBuffer[k];
$fwrite(frame, "%01x %01x %01x %01x %01x %01x %01x %01x ",
rCurrentTileRow[15:14],
rCurrentTileRow[13:12],
rCurrentTileRow[11:10],
rCurrentTileRow[9:8],
rCurrentTileRow[7:6],
rCurrentTileRow[5:4],
rCurrentTileRow[3:2],
rCurrentTileRow[1:0]);
if ((k+1) % 32 == 0)
$fwrite(frame,"\n#%d\n",k/32);
end
$fclose(frame);
FrameDumpCount = FrameDumpCount + 1;
`ifdef STOP_AFTER_FIRST_FRAME
$fwrite(log,"**** First frame complete. Stopping Simulation **** \n");
rSimulationDone = 1;
`endif
end
end
//-----------------------------------------------------------------
always @ (posedge iClock)
begin
wait(iReset != 1);
if (rSimulationDone == 1'b1)
begin
vram_log_8000_8fff = $fopen("papi_vram_8000_8fff.dump");
vram_log_9800_9bff = $fopen("papi_vram_9800_9bff.dump");
$display("Stopping Simulation and dumping memory");
$fwrite(log, "=== WORK MEMORY C000 - DFFFF ===\n");
$fwrite(log,"%02x: ",16'hc000);
for (i = 0; i < (16'hdfff-16'hc000); i = i + 1)
begin
$fwrite(log,"%02x ", uut.MMU.WORK_RAM.Ram[i]);
if ((i+1) % 16 == 0)
$fwrite(log,"\n %h: ", (16'hc000+i+1));
end
$fwrite(log,"\n\n=== PAGEZERO MEMORY ===\n\n");
for (i = 16'hff80; i <= 16'hffff; i = i + 1)
begin
if (i % 16 == 0)
$fwrite(log,"\n %h : ", i );
$fwrite(log,"%02h ",uut.MMU.ZERO_PAGE.Ram[i-16'hff80]);
end
//Dump the VMEM
$fwrite(log,"\n\n=== VIDEO MEMORY ===\n\n");
for (i = 16'h8000; i <= 16'h9fff; i = i + 1)
begin
if (i % 16 == 0)
begin
$fwrite(log,"\n %h : ", i );
if ( i <= 16'h8fff)
$fwrite(vram_log_8000_8fff,"\n %h : ", i );
if ( i >= 16'h9800 && i <= 16'h9bff)
$fwrite(vram_log_9800_9bff,"\n %h : ", i );
end
$fwrite(log,"%02h ",uut.MMU.VMEM.Ram[i- 16'h8000]);
if ( i <= 16'h8fff)
$fwrite(vram_log_8000_8fff,"%02h ",uut.MMU.VMEM.Ram[i- 16'h8000]);
if ( i >= 16'h9800 && i <= 16'h9bff)
$fwrite(vram_log_9800_9bff,"%02h ",uut.MMU.VMEM.Ram[i- 16'h8000]);
end
$fwrite(log,"\n\nTEST_RET_VAL %04h\n\n", {uut.MMU.ZERO_PAGE.Ram[ 16'hfffd - 16'hff80 ],uut.MMU.ZERO_PAGE.Ram[ 16'hfffc - 16'hff80 ]} );
$fwrite(log,"Simulation ended at time %dns\n", $time);
`ifdef ENABLE_CPU_LOG
$fclose( log );
`endif
`ifdef ENABLE_GPU_LOG
$fclose( glog );
`endif
`ifdef ENABLE_SOUND_TRACE
$fclose( sound_trace );
`endif
$fclose( vram_log_8000_8fff );
$fclose( vram_log_9800_9bff );
$finish();
end
end
//-----------------------------------------------------------------
initial begin
// Initialize Inputs
InstCount = 64'b0;
`ifdef ENABLE_CPU_LOG
log = $fopen("pgb_cpu.log");
`endif
`ifdef ENABLE_GPU_LOG
glog = $fopen("pgb_gpu.log");
`endif
`ifdef ENABLE_INSN_TRACE
trace = $fopen("pgb_trace.dump");
`endif
`ifdef ENABLE_SOUND_TRACE
sound_trace = $fopen("pgb_sound_trace.dump");
`endif
`ifdef VMEM_DUMP_PATH
$readmemh(
`VMEM_DUMP_PATH, uut.MMU.VMEM.Ram);
$fwrite(glog,"\n\n=== VIDEO MEMORY FROM FILE: %s===\n\n", `VMEM_DUMP_PATH);
for (i = 16'h8000; i <= 16'h9fff; i = i + 1)
begin
if (i % 16 == 0)
$fwrite(glog,"\n %h : ", i );
$fwrite(glog,"%02h ",uut.MMU.VMEM.Ram[i- 16'h8000]);
end
`endif
`ifdef OAM_DUMP_PATH
$readmemh(
`OAM_DUMP_PATH, uut.MMU.OAM.Ram);
$fwrite(glog,"\n\n=== OAM MEMORY FROM FILE: %s===\n\n", `OAM_DUMP_PATH);
for (i = 16'hfe00; i <= 16'hfe9f; i = i + 1)
begin
if (i % 16 == 0)
$fwrite(glog,"\n %h : ", i );
$fwrite(glog,"%02h ",uut.MMU.OAM.Ram[i- 16'hfe00]);
end
$fwrite(glog,"\n\n");
`endif
rResetDone = 1'b0;
$dumpfile("tb_simple_dzcpu.vcd");
$dumpvars(0,tb_simple_dzcpu);
$fwrite(log,"Simulation started at time %dns\n", $time);
rSimulationDone = 0;
iClock = 0;
iReset = 0;
// Wait 100 ns for global reset to finish
#100;
iReset = 1;
#10
iReset = 0;
`ifdef REG_A
uut.DZCPU.FFA.Q = `REG_A;
`endif
`ifdef REG_F
uut.DZCPU.FFFLAGS.Q = `REG_F;
`endif
`ifdef REG_B
uut.DZCPU.FFB.Q = `REG_B;
`endif
`ifdef REG_C
uut.DZCPU.FFC.Q = `REG_C;
`endif
`ifdef REG_H
uut.DZCPU.FFH.Q = `REG_H;
`endif
`ifdef REG_L
uut.DZCPU.FFL.Q = `REG_L;
`endif
`ifdef REG_D
uut.DZCPU.FFD.Q = `REG_D;
`endif
`ifdef REG_E
uut.DZCPU.FFE.Q = `REG_E;
`endif
`ifdef REG_SPL
uut.DZCPU.FFSPL.Q = `REG_SPL;
`endif
`ifdef REG_SPH
uut.DZCPU.FFSPH.Q = `REG_SPH;
`endif
`ifdef REG_LCDC
uut.GPU.FF_LCDC.Q = `REG_LCDC;
`endif
`ifdef REG_BGP
uut.GPU.FFS_BGP.Q = `REG_BGP;
`endif
`ifdef DISABLE_CPU
//Force GPU to start
uut.GPU.FF_SCX.Q = 8'h0;
uut.GPU.FF_SCY.Q = 8'h0;
uut.GPU.FF_LY.Q = 8'h0;
uut.GPU.FFS_OBP0.Q = 8'he4;
uut.GPU.FFS_OBP1.Q = 8'hc4;
uut.GPU.FFS_WY.Q = 8'h80;
uut.GPU.FFX_WX.Q =8'h06;
`endif
// Add stimulus here
//#500
#1000
rResetDone = 1'b1;
//#5000000
`ifdef SIMULATION_TIME_OUT
#`SIMULATION_TIME_OUT
`else
#500000000
`endif
$fwrite(log, "Simulation reached MAX time %hns",$time);
rSimulationDone = 1;
end
integer row_count=0;
`ifdef ENABLE_GPU_LOG
always @ ( posedge iClock )
begin
if (uut.GPU.wGpuActive)
begin
$fwrite(glog,"%05dns [GPU] IP:%d %h .",$time, uut.GPU.wIp, uut.GPU.wUop[`GPU_OP_RNG] );
case (uut.GPU.wUop[`GPU_OP_RNG])
`gnop: $fwrite(glog, "nop \n");
`gwrl: $fwrite(glog, "gwrl r[%h] = %h\n",uut.GPU.wUop[`GPU_DST_RNG],uut.GPU.wUop[`GPU_LIT_RNG]);
`gwrr: $fwrite(glog, "gwrr \n");
`gadd: $fwrite(glog, "gadd %h + %h = %h\n", uut.GPU.wOp1, uut.GPU.wOp0, uut.GPU.rResult);
`gsub: $fwrite(glog, "gsub %h - %h = %h\n",uut.GPU.wOp1, uut.GPU.wOp0, uut.GPU.rResult);
`gaddl: $fwrite(glog, "gaddl %h += %h = %h\n", uut.GPU.wOp1, uut.GPU.wUop[`GPU_LIT_RNG], uut.GPU.rResult );
`gjnz: $fwrite(glog, "gjnz \n");
`gwfbuffer: $fwrite(glog, "gwfbuffer \n");
`gsubl: $fwrite(glog, "gsubl %h -= %h = %h\n", uut.GPU.wOp1, uut.GPU.wUop[`GPU_LIT_RNG], uut.GPU.rResult);
`grvmem: $fwrite(glog,"grvmem @ %h\n", uut.GPU.oMcuAddr);
`gshl: $fwrite(glog,"gshl \n");
`gand: $fwrite(glog, "gand %h & %h = %h\n", uut.GPU.wOp1, uut.GPU.wOp0, uut.GPU.rResult);
`gjz: $fwrite(glog, "gjz \n");
`gsprtt: $fwrite(glog, " >>> gsprtt tile_row: %d tile_idx: %d sprite [%d , %d] , tile [%d %d ] = %h\n",
uut.GPU.wCurrentTileRow/2, uut.GPU.wCurrentTile,
uut.GPU.wSpriteCoordX, uut.GPU.wSpriteCoordY,
uut.GPU.wTileCoordX, uut.GPU.wTileCoordY, uut.GPU.wIsSpriteInCurrentTile);
endcase
//Print the Registers
$fwrite(glog,"\n %05s %05s %05s %05s %05s %05s %05s %05s %05s %05s %05s %05s %05s %05s %05s\n",
"Ip", "oAddr", "iData", "STAT",
"LCDC", "SCY", "SCX" , "LY",
"LYC", "DMA", "BGP", "BP0",
"BP1", "WY", "WX");
$fwrite(glog,"[regs] %04d %04x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
uut.GPU.wIp, uut.GPU.oMcuAddr, uut.GPU.iMcuReadData, uut.GPU.oSTAT,
uut.GPU.oLCDC, uut.GPU.oSCY, uut.GPU.oSCX, uut.GPU.oLY,
uut.GPU.oLYC, uut.GPU.oDMA, uut.GPU.oBGP, uut.GPU.oOBP0,
uut.GPU.oOBP1, uut.GPU.oWY, uut.GPU.oWX );
$fwrite(glog, "%04s %04s %04s %04s %06s %10s %10s %10s %10s %10s %10s\n", "Sh", "Sl","Bh", "Bl", "Bsel", "cur_tile", "tile_row", "fb_addr", "vmem_data", "sprite_x", "sprite_y");
$fwrite(glog, "0x%02x 0x%02x 0x%02x 0x%02x 0x%04x 0x%08x 0x%08x 0d%08d 0x%08x 0d%08d %08d\n",
uut.GPU.wSh, uut.GPU.wSl,uut.GPU.wBh, uut.GPU.wBl, uut.GPU.wR2, uut.GPU.wCurrentTile, uut.GPU.wCurrentTileRow, wFrameBufferAddress, uut.GPU.iMcuReadData, uut.GPU.wSpriteCoordX, uut.GPU.wSpriteCoordY);
$fwrite(glog, "\nBackground Tile Pixel Row:\n");
$fwrite(glog, "%02x %02x %02x %02x %02x %02x %02x %02x\n",
uut.GPU.wBgPixel7,uut.GPU.wBgPixel6,uut.GPU.wBgPixel5,uut.GPU.wBgPixel4,uut.GPU.wBgPixel3,uut.GPU.wBgPixel2,uut.GPU.wBgPixel1,uut.GPU.wBgPixel0);
$fwrite(glog, "\nSprite Tile Pixel Row:\n");
$fwrite(glog, "%02x %02x %02x %02x %02x %02x %02x %02x\n",
uut.GPU.wSprtPixel7,uut.GPU.wSprtPixel6,uut.GPU.wSprtPixel5,uut.GPU.wSprtPixel4,uut.GPU.wSprtPixel3,uut.GPU.wSprtPixel2,uut.GPU.wSprtPixel1,uut.GPU.wSprtPixel0);
$fwrite(glog, "\nFrame buffer Pixel Row:\n");
$fwrite(glog, "%02x %02x %02x %02x %02x %02x %02x %02x\n",
uut.GPU.wPixel7,uut.GPU.wPixel6,uut.GPU.wPixel5,uut.GPU.wPixel4,uut.GPU.wPixel3,uut.GPU.wPixel2,uut.GPU.wPixel1,uut.GPU.wPixel0);
$fwrite(glog,"\n\n\n");
end //if
end //always
`endif
`ifdef ENABLE_SOUND_TRACE
always @ ( posedge iClock )
begin
if (uut.MMU.iCpuWe)
begin
if (uut.MMU.iCpuAddr >= 16'hff10 && uut.MMU.iCpuAddr <= 16'hff23 )
begin
$fwrite(sound_trace,"%dns %04x @ %04x \n", $time, uut.MMU.iCpuData,uut.MMU.iCpuAddr );
$display("%dns %04x @ %04x \n", $time, uut.MMU.iCpuData,uut.MMU.iCpuAddr );
end
end
end //always
`endif
`ifdef ENABLE_CPU_LOG
always @ ( posedge iClock )
begin
wait(iReset != 1);
//if (uut.DZCPU.wPc == 16'h204)//16'h0fc // || uut.GPU.oLY == 8'hff) //This instructrion finishes copying the little (R)
//rSimulationDone = 1;
if (uut.DZCPU.rCurrentState == `DZCPU_START_FLOW)
begin
`ifdef ENABLE_INSN_TRACE
$fwrite(trace,"pc: %04x opcode: %x sp: %x HL: %04x AF: %04x BC: %04x DE: %04x\n",
uut.DZCPU.wPc, uut.DZCPU.iMCUData, {uut.DZCPU.wSpH,uut.DZCPU.wSpL},
{uut.DZCPU.wH,uut.DZCPU.wL},
{uut.DZCPU.wA,uut.DZCPU.wFlags},
{uut.DZCPU.wB,uut.DZCPU.wC},
{uut.DZCPU.wD,uut.DZCPU.wE}
);
`endif
Pc = uut.DZCPU.wPc;
$fwrite(log,"InsnCount: %d\n ", InstCount);
case (uut.DZCPU.wuOpFlowIdx)
1: $fwrite(log,"=== LDSPnn === %h \n", uut.DZCPU.iMCUData );
5: $fwrite(log,"=== LDHLnn === %h \n", uut.DZCPU.iMCUData );
9: $fwrite(log,"=== LDHLDA === %h \n", uut.DZCPU.iMCUData );
13: $fwrite(log,"=== MAPcb === %h \n", uut.DZCPU.iMCUData );
17: $fwrite(log,"=== JRNZn === %h \n", uut.DZCPU.iMCUData );
23: $fwrite(log,"=== LDrn_c === %h \n", uut.DZCPU.iMCUData );
26: $fwrite(log,"=== LDrn_a === %h \n", uut.DZCPU.iMCUData );
29: $fwrite(log,"=== LDIOCA === %h \n", uut.DZCPU.iMCUData );
32: $fwrite(log,"=== INCr_c === %h \n", uut.DZCPU.iMCUData );
33: $fwrite(log,"=== LDHLmr_a === %h \n", uut.DZCPU.iMCUData );
36: $fwrite(log,"=== LDIOnA === %h \n", uut.DZCPU.iMCUData );
43: $fwrite(log,"=== LDDEnn === %h \n", uut.DZCPU.iMCUData );
94: $fwrite(log,"=== LDADEm === %h \n", uut.DZCPU.iMCUData );
49: $fwrite(log,"=== CALLnn === %h \n", uut.DZCPU.iMCUData );
60: $fwrite(log,"=== LDrn_b === %h \n", uut.DZCPU.iMCUData );
63: $fwrite(log,"=== PUSHBC === %h \n", uut.DZCPU.iMCUData );
70: $fwrite(log,"=== RLA === %h \n", uut.DZCPU.iMCUData );
71: $fwrite(log,"=== POPBC === %h \n", uut.DZCPU.iMCUData );
300: $fwrite(log,"=== DECr_b === %h \n", uut.DZCPU.iMCUData );
78: $fwrite(log,"=== LDHLIA === %h \n", uut.DZCPU.iMCUData );
82: $fwrite(log,"=== INCHL === %h \n", uut.DZCPU.iMCUData );
252/*83*/: $fwrite(log,"=== RET === %h \n", uut.DZCPU.iMCUData );
89: $fwrite(log,"=== INCDE === %h \n", uut.DZCPU.iMCUData );
90: $fwrite(log,"=== CPn === %h \n", uut.DZCPU.iMCUData );
98: $fwrite(log,"=== LDmmA === %h \n", uut.DZCPU.iMCUData );
47: $fwrite(log,"=== DECr_a === %h \n", uut.DZCPU.iMCUData );
48: $fwrite(log,"=== DECr_c === %h \n", uut.DZCPU.iMCUData );
106: $fwrite(log,"=== JRZn === %h \n", uut.DZCPU.iMCUData );
112: $fwrite(log,"=== LDrn_l === %h \n", uut.DZCPU.iMCUData );
115: $fwrite(log,"=== JRn === %h \n", uut.DZCPU.iMCUData );
161: $fwrite(log,"=== INCr_b === %h \n", uut.DZCPU.iMCUData );
121: $fwrite(log,"=== LDrn_e === %h \n", uut.DZCPU.iMCUData );
124: $fwrite(log,"=== LDAIOn === %h \n", uut.DZCPU.iMCUData );
312: $fwrite(log,"=== INCr_h === %h \n", uut.DZCPU.iMCUData );
132: $fwrite(log,"=== SUBr_b === %h \n", uut.DZCPU.iMCUData );
135: $fwrite(log,"=== DECr_d === %h \n", uut.DZCPU.iMCUData );
136: $fwrite(log,"=== LDrn_d === %h \n", uut.DZCPU.iMCUData );
139: $fwrite(log,"=== JPnn === %h \n", uut.DZCPU.iMCUData );
146: $fwrite(log,"=== LDrn_h === %h \n", uut.DZCPU.iMCUData );
149: $fwrite(log,"=== LDAHLI === %h \n", uut.DZCPU.iMCUData );
154: $fwrite(log,"=== LDHLmn === %h \n", uut.DZCPU.iMCUData );
162: $fwrite(log,"=== NOP === \n");
163: $fwrite(log,"=== DI === \n", uut.DZCPU.iMCUData );
164: $fwrite(log,"=== INCr_d === %h \n", uut.DZCPU.iMCUData );
250/*165*/: $fwrite(log,"=== INCr_e === %h \n", uut.DZCPU.iMCUData );
166: $fwrite(log,"=== DECr_e === %h \n", uut.DZCPU.iMCUData );
168: $fwrite(log,"=== DECDE === %h \n", uut.DZCPU.iMCUData );
169: $fwrite(log,"=== DECBC === %h \n", uut.DZCPU.iMCUData );
170: $fwrite(log,"=== DECr_h === %h \n", uut.DZCPU.iMCUData );
172: $fwrite(log,"=== DECHL === %h \n", uut.DZCPU.iMCUData );
302: $fwrite(log,"=== INCr_a === %h \n", uut.DZCPU.iMCUData );
304: $fwrite(log,"=== INCSP === %h \n", uut.DZCPU.iMCUData ); //Increment SP
306: $fwrite(log,"=== DECSP === %h \n", uut.DZCPU.iMCUData );
308: $fwrite(log,"=== INCr_l === %h \n", uut.DZCPU.iMCUData );
310: $fwrite(log,"=== DECr_l === %h \n", uut.DZCPU.iMCUData );
175: $fwrite(log,"=== ADDr_a === %h \n", uut.DZCPU.iMCUData );
178: $fwrite(log,"=== ADDr_b === %h \n", uut.DZCPU.iMCUData );
184: $fwrite(log,"=== ADDr_c === %h \n", uut.DZCPU.iMCUData );
181: $fwrite(log,"=== SUBr_c === %h \n", uut.DZCPU.iMCUData );
187: $fwrite(log,"=== ADDr_d === %h \n", uut.DZCPU.iMCUData );
190: $fwrite(log,"=== ADDr_e === %h \n", uut.DZCPU.iMCUData );
193: $fwrite(log,"=== ADDr_h === %h \n", uut.DZCPU.iMCUData );
196: $fwrite(log,"=== ADDr_l === %h \n", uut.DZCPU.iMCUData );
199: $fwrite(log,"=== SUBr_d === %h \n", uut.DZCPU.iMCUData );
202: $fwrite(log,"=== SUBr_e === %h \n", uut.DZCPU.iMCUData );
205: $fwrite(log,"=== SUBr_h === %h \n", uut.DZCPU.iMCUData );
208: $fwrite(log,"=== SUBr_l === %h \n", uut.DZCPU.iMCUData );
211: $fwrite(log,"=== SUBr_a === %h \n", uut.DZCPU.iMCUData );
214: $fwrite(log,"=== PUSHDE === %h \n", uut.DZCPU.iMCUData );
220: $fwrite(log,"=== PUSHHL === %h \n", uut.DZCPU.iMCUData );
226: $fwrite(log,"=== POPDE === %h \n", uut.DZCPU.iMCUData );
232: $fwrite(log,"=== POPHL === %h \n", uut.DZCPU.iMCUData );
238: $fwrite(log,"=== LDHLmr_b === %h \n", uut.DZCPU.iMCUData );
241: $fwrite(log,"=== LDHLmr_c === %h \n", uut.DZCPU.iMCUData );
244: $fwrite(log,"=== LDHLmr_d === %h \n", uut.DZCPU.iMCUData );
247: $fwrite(log,"=== LDDEmA === %h \n", uut.DZCPU.iMCUData );
261: $fwrite(log,"=== PUSHAF === %h \n", uut.DZCPU.iMCUData );
267: $fwrite(log,"=== POPAF === %h \n", uut.DZCPU.iMCUData );
273: $fwrite(log,"=== LDBCnn === %h \n", uut.DZCPU.iMCUData );
83: $fwrite(log,"=== INCBC === %h \n", uut.DZCPU.iMCUData );
280: $fwrite(log,"=== LDAmm === %h \n", uut.DZCPU.iMCUData );
85: $fwrite(log,"=== ANDn === %h\n", uut.DZCPU.iMCUData );
289: $fwrite(log,"=== CALLNZnn === %h\n",uut.DZCPU.iMCUData );
314: $fwrite(log,"=== ADDn === %h\n",uut.DZCPU.iMCUData );
319: $fwrite(log,"=== SUBn === %h\n",uut.DZCPU.iMCUData );
324: $fwrite(log,"=== CPr_c === %h\n",uut.DZCPU.iMCUData );
327: $fwrite(log,"=== LDrHLm_b === %h\n",uut.DZCPU.iMCUData );
331: $fwrite(log,"=== LDrHLm_c === %h\n",uut.DZCPU.iMCUData );
335: $fwrite(log,"=== LDrHLm_d === %h\n",uut.DZCPU.iMCUData );
339: $fwrite(log,"=== XORHL === %h\n",uut.DZCPU.iMCUData );
345: $fwrite(log,"=== ADCn === %h\n",uut.DZCPU.iMCUData );
351: $fwrite(log,"=== ADDHLDE === %h\n",uut.DZCPU.iMCUData );
414: $fwrite(log,"=== JRNCn === %h\n",uut.DZCPU.iMCUData );
359: $fwrite(log,"=== XORn === %h\n",uut.DZCPU.iMCUData );
363: $fwrite(log,"=== RRA === %h\n",uut.DZCPU.iMCUData );
365: $fwrite(log,"=== RETNC === %h\n",uut.DZCPU.iMCUData );
377: $fwrite(log,"=== RETZ === %h\n",uut.DZCPU.iMCUData );
387: $fwrite(log,"=== ORHL === %h\n",uut.DZCPU.iMCUData );
391: $fwrite(log,"=== DECHLm === %h\n",uut.DZCPU.iMCUData );
397: $fwrite(log,"=== LDrHLm_l === %h\n",uut.DZCPU.iMCUData );
401: $fwrite(log,"=== RETNZ === %h\n",uut.DZCPU.iMCUData );
411: $fwrite(log,"=== ADDHLHL === %h\n",uut.DZCPU.iMCUData );
420: $fwrite(log,"=== ANDHL === %h\n",uut.DZCPU.iMCUData );
424: $fwrite(log,"=== LDHLmr_e === %h \n", uut.DZCPU.iMCUData );
427: $fwrite(log,"=== LDHLmr_h === %h \n", uut.DZCPU.iMCUData );
430: $fwrite(log,"=== LDHLmr_l === %h \n", uut.DZCPU.iMCUData );
433: $fwrite(log,"=== LDABCm === %h \n", uut.DZCPU.iMCUData );
437: $fwrite(log,"=== LDrHLm_a === %h \n", uut.DZCPU.iMCUData );
441: $fwrite(log,"=== LDrHLm_e === %h \n", uut.DZCPU.iMCUData );
445: $fwrite(log,"=== LDrHLm_h === %h \n", uut.DZCPU.iMCUData );
449: $fwrite(log,"=== ADCr_a === %h \n", uut.DZCPU.iMCUData );
453: $fwrite(log,"=== ADCr_b === %h \n", uut.DZCPU.iMCUData );
457: $fwrite(log,"=== ADCr_c === %h \n", uut.DZCPU.iMCUData );
461: $fwrite(log,"=== ADCr_d === %h \n", uut.DZCPU.iMCUData );
465: $fwrite(log,"=== ADCr_e === %h \n", uut.DZCPU.iMCUData );
469: $fwrite(log,"=== ADCr_h === %h \n", uut.DZCPU.iMCUData );
473: $fwrite(log,"=== ADCr_l === %h \n", uut.DZCPU.iMCUData );
default:
case (uut.DZCPU.iMCUData)
`LDrr_aa: $fwrite(log,"=== LDrr_aa === %h \n", uut.DZCPU.iMCUData );
`LDrr_bb: $fwrite(log,"=== LDrr_bb === %h \n", uut.DZCPU.iMCUData );
`LDrr_bc: $fwrite(log,"=== LDrr_bc === %h \n", uut.DZCPU.iMCUData );
`LDrr_bd: $fwrite(log,"=== LDrr_bd === %h \n", uut.DZCPU.iMCUData );
`LDrr_be: $fwrite(log,"=== LDrr_be === %h \n", uut.DZCPU.iMCUData );
`LDrr_bh: $fwrite(log,"=== LDrr_bh === %h \n", uut.DZCPU.iMCUData );
`LDrr_bl: $fwrite(log,"=== LDrr_bl === %h \n", uut.DZCPU.iMCUData );
`LDrr_eb: $fwrite(log,"=== LDrr_eb === %h \n", uut.DZCPU.iMCUData );
`LDrr_ee: $fwrite(log,"=== LDrr_ee === %h \n", uut.DZCPU.iMCUData );
`LDrr_eh: $fwrite(log,"=== LDrr_eh === %h \n", uut.DZCPU.iMCUData );
`LDrr_el: $fwrite(log,"=== LDrr_el === %h \n", uut.DZCPU.iMCUData );
`LDrr_ed: $fwrite(log,"=== LDrr_ed === %h \n", uut.DZCPU.iMCUData );
`LDrr_ec: $fwrite(log,"=== LDrr_ec === %h \n", uut.DZCPU.iMCUData );
`LDrr_la: $fwrite(log,"=== LDrr_la === %h \n", uut.DZCPU.iMCUData );
`LDrr_ll: $fwrite(log,"=== LDrr_ll === %h \n", uut.DZCPU.iMCUData );
`LDrr_lh: $fwrite(log,"=== LDrr_lh === %h \n", uut.DZCPU.iMCUData );
`LDrr_le: $fwrite(log,"=== LDrr_le === %h \n", uut.DZCPU.iMCUData );
`LDrr_ld: $fwrite(log,"=== LDrr_ld === %h \n", uut.DZCPU.iMCUData );
`LDrr_lc: $fwrite(log,"=== LDrr_lc === %h \n", uut.DZCPU.iMCUData );
`LDrr_lb: $fwrite(log,"=== LDrr_lb === %h \n", uut.DZCPU.iMCUData );
`LDrr_ba: $fwrite(log,"=== LDrr_ba === %h \n", uut.DZCPU.iMCUData );
`LDrr_cb: $fwrite(log,"=== LDrr_cb === %h \n", uut.DZCPU.iMCUData );
`LDrr_cc: $fwrite(log,"=== LDrr_cc === %h \n", uut.DZCPU.iMCUData );
`LDrr_cd: $fwrite(log,"=== LDrr_cd === %h \n", uut.DZCPU.iMCUData );
`LDrr_ce: $fwrite(log,"=== LDrr_ce === %h \n", uut.DZCPU.iMCUData );
`LDrr_ch: $fwrite(log,"=== LDrr_ch === %h \n", uut.DZCPU.iMCUData );
`LDrr_cl: $fwrite(log,"=== LDrr_cl === %h \n", uut.DZCPU.iMCUData );
`LDrr_ac: $fwrite(log,"=== LDrr_ac === %h \n", uut.DZCPU.iMCUData );
`LDrr_ad: $fwrite(log,"=== LDrr_ad === %h \n", uut.DZCPU.iMCUData );
`LDrr_ae: $fwrite(log,"=== LDrr_ae === %h \n", uut.DZCPU.iMCUData );
`LDrr_ha: $fwrite(log,"=== LDrr_ha === %h \n", uut.DZCPU.iMCUData );
`LDrr_da: $fwrite(log,"=== LDrr_da === %h \n", uut.DZCPU.iMCUData );
`LDrr_ea: $fwrite(log,"=== LDrr_ea === %h \n", uut.DZCPU.iMCUData );
`LDrr_ca: $fwrite(log,"=== LDrr_ca === %h \n", uut.DZCPU.iMCUData );
`LDrr_ah: $fwrite(log,"=== LDrr_ah === %h \n", uut.DZCPU.iMCUData );
`LDrr_al: $fwrite(log,"=== LDrr_al === %h \n", uut.DZCPU.iMCUData );
`LDrr_ab: $fwrite(log,"=== LDrr_ab === %h \n", uut.DZCPU.iMCUData );
`LDrr_de: $fwrite(log,"=== LDrr_de === %h \n", uut.DZCPU.iMCUData );
`LDrr_db: $fwrite(log,"=== LDrr_db === %h \n", uut.DZCPU.iMCUData );
`LDrr_dc: $fwrite(log,"=== LDrr_dc === %h \n", uut.DZCPU.iMCUData );
`LDrr_dd: $fwrite(log,"=== LDrr_dd === %h \n", uut.DZCPU.iMCUData );
`LDrr_dh: $fwrite(log,"=== LDrr_dh === %h \n", uut.DZCPU.iMCUData );
`LDrr_dl: $fwrite(log,"=== LDrr_dl === %h \n", uut.DZCPU.iMCUData );
`XORr_a: $fwrite(log,"=== XORr_a === %h \n", uut.DZCPU.iMCUData );
`XORr_b: $fwrite(log,"=== XORr_b === %h \n", uut.DZCPU.iMCUData );
`XORr_c: $fwrite(log,"=== XORr_c === %h \n", uut.DZCPU.iMCUData );
`XORr_d: $fwrite(log,"=== XORr_d === %h \n", uut.DZCPU.iMCUData );
`XORr_e: $fwrite(log,"=== XORr_e === %h \n", uut.DZCPU.iMCUData );
`XORr_l: $fwrite(log,"=== XORr_l === %h \n", uut.DZCPU.iMCUData );
`XORr_h: $fwrite(log,"=== XORr_h === %h \n", uut.DZCPU.iMCUData );
`ORr_b: $fwrite(log,"=== ORr_b === %h \n", uut.DZCPU.iMCUData );
`ORr_c: $fwrite(log,"=== ORr_c === %h \n", uut.DZCPU.iMCUData );
`ORr_a: $fwrite(log,"=== ORr_a === %h \n", uut.DZCPU.iMCUData );
`ORr_d: $fwrite(log,"=== ORr_d === %h \n", uut.DZCPU.iMCUData );
`ORr_e: $fwrite(log,"=== ORr_e === %h \n", uut.DZCPU.iMCUData );
`ORr_h: $fwrite(log,"=== ORr_h === %h \n", uut.DZCPU.iMCUData );
`ORr_l: $fwrite(log,"=== ORr_l === %h \n", uut.DZCPU.iMCUData );
//`ORn: $fwrite(log,"=== ORn === %h \n", uut.DZCPU.iMCUData );
`ANDr_b: $fwrite(log,"=== ANDr_b === %h \n", uut.DZCPU.iMCUData );
`ANDr_c: $fwrite(log,"=== ANDr_c === %h \n", uut.DZCPU.iMCUData );
`ANDr_a: $fwrite(log,"=== ANDr_a === %h \n", uut.DZCPU.iMCUData );
`ANDr_d: $fwrite(log,"=== ANDr_d === %h \n", uut.DZCPU.iMCUData );
`ANDr_e: $fwrite(log,"=== ANDr_e === %h \n", uut.DZCPU.iMCUData );
`ANDr_h: $fwrite(log,"=== ANDr_h === %h \n", uut.DZCPU.iMCUData );
`ANDr_l: $fwrite(log,"=== ANDr_l === %h \n", uut.DZCPU.iMCUData );
`ANDn: $fwrite(log,"=== ANDn === %h \n", uut.DZCPU.iMCUData );
`NOP: $fwrite(log,"=== NOP === %h \n", uut.DZCPU.iMCUData );
default:
begin
if (rResetDone)
begin
$display("=== Unknown Flow. Insns %h\n",uut.DZCPU.iMCUData);
$fwrite(log,"=== Unknown Flow. Insns %h\n",uut.DZCPU.iMCUData);
rSimulationDone = 1'b1;
end
end
endcase
endcase
InstCount = InstCount + 64'b1;
`ifdef STOP_AFTER_INSN_COUNT
if (InstCount >= `STOP_AFTER_INSN_COUNT)
begin
rSimulationDone = 1;
$fwrite(log,"**** InsnCount = %d. Stopping Simulation **** \n", InstCount);
end
`endif
end
if (uut.MMU.iGpuReadRequest)
begin
$fwrite(log,"%dns [MMU] Gpu requesting read @ %h (%h)\n ", $time, uut.MMU.iGpuAddr, uut.MMU.wVmemReadAddr);
$fwrite(glog,"%dns [MMU] Gpu requesting read @ %h (%h)\n ", $time, uut.MMU.iGpuAddr, uut.MMU.wVmemReadAddr);
end
if (uut.DZCPU.rFlowEnable)
begin
$fwrite(log,"%05dns [DZCPU] %d (%h) .",$time, uut.DZCPU.wuPc, uut.DZCPU.wuCmd);
case (uut.DZCPU.wuCmd)
`nop: $fwrite(log,"nop \n");
`sma: $fwrite(log,"sma %h\n", uut.DZCPU.oMCUAddr);
`srm:
begin
$fwrite(log,"srm %h %h\n", uut.DZCPU.wUopSrc, uut.DZCPU.iMCUData);
$fwrite(log,"[MMU] reading %h @ %h,\n", uut.MMU.oCpuData,uut.MMU.iCpuAddr);
end
`jcb:
begin
$fwrite(log,"jcb %h \n", uut.DZCPU.iMCUData);
end
`smw: $fwrite(log,"smw %h %h\n", uut.DZCPU.oMCUAddr, uut.DZCPU.oMCUData);
`bit: $fwrite(log,"bit %h & %b\n", uut.DZCPU.wRegData, uut.DZCPU.wBitMask);
`addx16:$fwrite(log,"addx16 %h += %h\n", uut.DZCPU.wX16, uut.DZCPU.wRegData);
`addx16u:$fwrite(log,"addx16u %h += %h\n", uut.DZCPU.wX16, uut.DZCPU.wRegData);
`spc: $fwrite(log,"spc %h\n", uut.DZCPU.wRegData);
`sx16r: $fwrite(log,"sx16r %h\n", uut.DZCPU.wRegData);
`sx8r: $fwrite(log,"sx8r %h\n", uut.DZCPU.wRegData);
`inc16:$fwrite(log,"inc16 %h\n", uut.DZCPU.wRegData);
`dec16: $fwrite(log,"dec16 %h\n", uut.DZCPU.wRegData);
`srx8:$fwrite(log,"srx8 %h\n", uut.DZCPU.wRegData);
`shl: $fwrite(log,"shl %h << 1 + %h\n", uut.DZCPU.wRegData, uut.DZCPU.wFlags[`flag_c] );
`subx16: $fwrite(log,"subx16 %h -= %h = %h\n", uut.DZCPU.wX16, uut.DZCPU.wRegData, uut.DZCPU.rUopDstRegData);
`srx16: $fwrite(log,"srx16 %h\n", uut.DZCPU.wRegData);
`ceti: $fwrite(log,"ceti %h\n", uut.DZCPU.wRegData);
`jint: $fwrite(log,"jint %h\n", uut.DZCPU.wRegData);
`seti: $fwrite(log,"set %h\n", uut.DZCPU.wRegData);
`anda: $fwrite(log,"anda %h\n", uut.DZCPU.wRegData);
`xorx16: $fwrite(log,"xorx16 %h\n", uut.DZCPU.wRegData);
`rrot: $fwrite(log,"rrot %h\n", uut.DZCPU.wRegData);
`xora: $fwrite(log,"xora %h\n", uut.DZCPU.wRegData);
`addx16r16: $fwrite(log,"addx16r16 %h + %h = %h\n", uut.DZCPU.wX16, uut.DZCPU.wRegData, uut.DZCPU.rUopDstRegData);
`z801bop:
begin
case (uut.DZCPU.iMCUData[7:3])
5'b10100: $fwrite(log,"%05dns a &= %h = %h\n", $time, uut.DZCPU.wRegData, uut.DZCPU.rZ80Result );
5'b10101: $fwrite(log,"%05dns a ^= %h = %h\n", $time, uut.DZCPU.wRegData, uut.DZCPU.rZ80Result );
endcase
end
default:
begin
$fwrite(log,"unknow uop %d Stopping Simulation\n", uut.DZCPU.wuCmd);
rSimulationDone = 1;
end
endcase
end
if (uut.MMU.iCpuWe)
begin
$fwrite(log,"%05dns [MMU] ", $time);
if (uut.MMU.iCpuAddr >= 16'hff00 && uut.MMU.iCpuAddr <= 16'hff7f )
$fwrite(log," [IO] ");
if (uut.MMU.iCpuAddr >= 16'hff10 && uut.MMU.iCpuAddr <= 16'hff23 )
$fwrite(log," [SOUND] ");
if (uut.MMU.iCpuAddr >= 16'hff40 && uut.MMU.iCpuAddr <= 16'hff4B )
$fwrite(log," [LCD] ");
if (uut.MMU.iCpuAddr >= 16'hff80 && uut.MMU.iCpuAddr <= 16'hffff )
$fwrite(log," [PAGEZERO] ");
if (uut.MMU.iCpuAddr >= 16'h8000 && uut.MMU.iCpuAddr <= 16'h87ff )
$fwrite(log," [VMEM Tiles 0] ");
if (uut.MMU.iCpuAddr >= 16'h8800 && uut.MMU.iCpuAddr <= 16'h8fff )
$fwrite(log," [VMEM Tiles 1] ");
if (uut.MMU.iCpuAddr >= 16'h9800 && uut.MMU.iCpuAddr <= 16'h9BFF)
$fwrite(log," [VMEM TileMap 0] ");
if (uut.MMU.iCpuAddr >= 16'h9C00 && uut.MMU.iCpuAddr <= 16'h9FFF)
$fwrite(log," [VMEM TileMap 1] ");
$fwrite(log,"Writting %h @ %h\n", uut.MMU.iCpuData,uut.MMU.iCpuAddr);
end
if (uut.DZCPU.wEof )
begin
$fwrite(log,"\n %04s %04s %02s %02s %02s %02s %02s %02s %02s %02s %02s %02s\n", "PC", "SP", "B", "C", "D" ,"E", "H", "L", "A", "F", "Flags", "x8", "x16");
$fwrite(log,"[regs] %04x %04x %02x %02x %02x %02x %02x %02x %02x %02x %b %02x %02x\n", Pc, {uut.DZCPU.wSpH,uut.DZCPU.wSpL}, uut.DZCPU.wB, uut.DZCPU.wC, uut.DZCPU.wD, uut.DZCPU.wE ,uut.DZCPU.wH, uut.DZCPU.wL, uut.DZCPU.wA,uut.DZCPU.wFlags, uut.DZCPU.wFlags, uut.DZCPU.wX8, uut.DZCPU.wX16);
$fwrite(log,"\n\n %05s %05s %05s %05s %05s %05s %05s %05s %05s %05s %05s %05s\n",
"STAT", "LCDC", "SCY", "SCX" , "LY",
"LYC", "DMA", "BGP", "BP0",
"BP1", "WY", "WX");
$fwrite(log,"[regs] %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
uut.GPU.oSTAT, uut.GPU.oLCDC, uut.GPU.oSCY, uut.GPU.oSCX, uut.GPU.oLY,
uut.GPU.oLYC, uut.GPU.oDMA, uut.GPU.oBGP, uut.GPU.oOBP0,
uut.GPU.oOBP1, uut.GPU.oWY, uut.GPU.oWX );
`ifdef CPU_TRACE_WORK_MEMORY
$fwrite(log, "=== WORK MEMORY C000 - DFFFF ===\n");
$fwrite(log,"%02h: ",16'hc000);
for (i = 0; i < 5*16; i = i + 1)
begin
$fwrite(log,"%02h ", uut.MMU.WORK_RAM.Ram[i]);
if ((i+1) % 16 == 0)
$fwrite(log,"\n %h: ", (16'hc000+i));
end
for (i = 8176; i < 8176+15*16; i = i + 1)
begin
$fwrite(log,"*%02x ", uut.MMU.WORK_RAM.Ram[i]);
if ((i+1) % 16 == 0)
$fwrite(log,"\n");
end
`endif
if (uut.GPU.oLY == 144)
$fwrite(log,"[SCREEN_FRAME_COMPLETED]\n");
$fwrite(log,"\n\n\n");
end
end
`endif //ENABLE_CPU_LOG
endmodule
|
/*
* These source files contain a hardware description of a network
* automatically generated by CONNECT (CONfigurable NEtwork Creation Tool).
*
* This product includes a hardware design developed by Carnegie Mellon
* University.
*
* Copyright (c) 2012 by Michael K. Papamichael, Carnegie Mellon University
*
* For more information, see the CONNECT project website at:
* http://www.ece.cmu.edu/~mpapamic/connect
*
* This design is provided for internal, non-commercial research use only,
* cannot be used for, or in support of, goods or services, and is not for
* redistribution, with or without modifications.
*
* You may not use the name "Carnegie Mellon University" or derivations
* thereof to endorse or promote products derived from this software.
*
* THE SOFTWARE IS PROVIDED "AS-IS" WITHOUT ANY WARRANTY OF ANY KIND, EITHER
* EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO ANY WARRANTY
* THAT THE SOFTWARE WILL CONFORM TO SPECIFICATIONS OR BE ERROR-FREE AND ANY
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* TITLE, OR NON-INFRINGEMENT. IN NO EVENT SHALL CARNEGIE MELLON UNIVERSITY
* BE LIABLE FOR ANY DAMAGES, INCLUDING BUT NOT LIMITED TO DIRECT, INDIRECT,
* SPECIAL OR CONSEQUENTIAL DAMAGES, ARISING OUT OF, RESULTING FROM, OR IN
* ANY WAY CONNECTED WITH THIS SOFTWARE (WHETHER OR NOT BASED UPON WARRANTY,
* CONTRACT, TORT OR OTHERWISE).
*
*/
//
// Generated by Bluespec Compiler, version 2012.01.A (build 26572, 2012-01-17)
//
// On Sat Feb 11 18:26:57 EST 2017
//
// Method conflict info:
// Method: in_ports_0_putRoutedFlit
// Conflict-free: in_ports_0_getNonFullVCs,
// in_ports_1_putRoutedFlit,
// in_ports_1_getNonFullVCs,
// in_ports_2_putRoutedFlit,
// in_ports_2_getNonFullVCs,
// in_ports_3_putRoutedFlit,
// in_ports_3_getNonFullVCs,
// in_ports_4_putRoutedFlit,
// in_ports_4_getNonFullVCs,
// out_ports_0_getFlit,
// out_ports_0_putNonFullVCs,
// out_ports_1_getFlit,
// out_ports_1_putNonFullVCs,
// out_ports_2_getFlit,
// out_ports_2_putNonFullVCs,
// out_ports_3_getFlit,
// out_ports_3_putNonFullVCs,
// out_ports_4_getFlit,
// out_ports_4_putNonFullVCs
// Conflicts: in_ports_0_putRoutedFlit
//
// Method: in_ports_0_getNonFullVCs
// Conflict-free: in_ports_0_putRoutedFlit,
// in_ports_0_getNonFullVCs,
// in_ports_1_putRoutedFlit,
// in_ports_1_getNonFullVCs,
// in_ports_2_putRoutedFlit,
// in_ports_2_getNonFullVCs,
// in_ports_3_putRoutedFlit,
// in_ports_3_getNonFullVCs,
// in_ports_4_putRoutedFlit,
// in_ports_4_getNonFullVCs,
// out_ports_0_getFlit,
// out_ports_0_putNonFullVCs,
// out_ports_1_getFlit,
// out_ports_1_putNonFullVCs,
// out_ports_2_getFlit,
// out_ports_2_putNonFullVCs,
// out_ports_3_getFlit,
// out_ports_3_putNonFullVCs,
// out_ports_4_getFlit,
// out_ports_4_putNonFullVCs
//
// Method: in_ports_1_putRoutedFlit
// Conflict-free: in_ports_0_putRoutedFlit,
// in_ports_0_getNonFullVCs,
// in_ports_1_getNonFullVCs,
// in_ports_2_putRoutedFlit,
// in_ports_2_getNonFullVCs,
// in_ports_3_putRoutedFlit,
// in_ports_3_getNonFullVCs,
// in_ports_4_putRoutedFlit,
// in_ports_4_getNonFullVCs,
// out_ports_0_getFlit,
// out_ports_0_putNonFullVCs,
// out_ports_1_getFlit,
// out_ports_1_putNonFullVCs,
// out_ports_2_getFlit,
// out_ports_2_putNonFullVCs,
// out_ports_3_getFlit,
// out_ports_3_putNonFullVCs,
// out_ports_4_getFlit,
// out_ports_4_putNonFullVCs
// Conflicts: in_ports_1_putRoutedFlit
//
// Method: in_ports_1_getNonFullVCs
// Conflict-free: in_ports_0_putRoutedFlit,
// in_ports_0_getNonFullVCs,
// in_ports_1_putRoutedFlit,
// in_ports_1_getNonFullVCs,
// in_ports_2_putRoutedFlit,
// in_ports_2_getNonFullVCs,
// in_ports_3_putRoutedFlit,
// in_ports_3_getNonFullVCs,
// in_ports_4_putRoutedFlit,
// in_ports_4_getNonFullVCs,
// out_ports_0_getFlit,
// out_ports_0_putNonFullVCs,
// out_ports_1_getFlit,
// out_ports_1_putNonFullVCs,
// out_ports_2_getFlit,
// out_ports_2_putNonFullVCs,
// out_ports_3_getFlit,
// out_ports_3_putNonFullVCs,
// out_ports_4_getFlit,
// out_ports_4_putNonFullVCs
//
// Method: in_ports_2_putRoutedFlit
// Conflict-free: in_ports_0_putRoutedFlit,
// in_ports_0_getNonFullVCs,
// in_ports_1_putRoutedFlit,
// in_ports_1_getNonFullVCs,
// in_ports_2_getNonFullVCs,
// in_ports_3_putRoutedFlit,
// in_ports_3_getNonFullVCs,
// in_ports_4_putRoutedFlit,
// in_ports_4_getNonFullVCs,
// out_ports_0_getFlit,
// out_ports_0_putNonFullVCs,
// out_ports_1_getFlit,
// out_ports_1_putNonFullVCs,
// out_ports_2_getFlit,
// out_ports_2_putNonFullVCs,
// out_ports_3_getFlit,
// out_ports_3_putNonFullVCs,
// out_ports_4_getFlit,
// out_ports_4_putNonFullVCs
// Conflicts: in_ports_2_putRoutedFlit
//
// Method: in_ports_2_getNonFullVCs
// Conflict-free: in_ports_0_putRoutedFlit,
// in_ports_0_getNonFullVCs,
// in_ports_1_putRoutedFlit,
// in_ports_1_getNonFullVCs,
// in_ports_2_putRoutedFlit,
// in_ports_2_getNonFullVCs,
// in_ports_3_putRoutedFlit,
// in_ports_3_getNonFullVCs,
// in_ports_4_putRoutedFlit,
// in_ports_4_getNonFullVCs,
// out_ports_0_getFlit,
// out_ports_0_putNonFullVCs,
// out_ports_1_getFlit,
// out_ports_1_putNonFullVCs,
// out_ports_2_getFlit,
// out_ports_2_putNonFullVCs,
// out_ports_3_getFlit,
// out_ports_3_putNonFullVCs,
// out_ports_4_getFlit,
// out_ports_4_putNonFullVCs
//
// Method: in_ports_3_putRoutedFlit
// Conflict-free: in_ports_0_putRoutedFlit,
// in_ports_0_getNonFullVCs,
// in_ports_1_putRoutedFlit,
// in_ports_1_getNonFullVCs,
// in_ports_2_putRoutedFlit,
// in_ports_2_getNonFullVCs,
// in_ports_3_getNonFullVCs,
// in_ports_4_putRoutedFlit,
// in_ports_4_getNonFullVCs,
// out_ports_0_getFlit,
// out_ports_0_putNonFullVCs,
// out_ports_1_getFlit,
// out_ports_1_putNonFullVCs,
// out_ports_2_getFlit,
// out_ports_2_putNonFullVCs,
// out_ports_3_getFlit,
// out_ports_3_putNonFullVCs,
// out_ports_4_getFlit,
// out_ports_4_putNonFullVCs
// Conflicts: in_ports_3_putRoutedFlit
//
// Method: in_ports_3_getNonFullVCs
// Conflict-free: in_ports_0_putRoutedFlit,
// in_ports_0_getNonFullVCs,
// in_ports_1_putRoutedFlit,
// in_ports_1_getNonFullVCs,
// in_ports_2_putRoutedFlit,
// in_ports_2_getNonFullVCs,
// in_ports_3_putRoutedFlit,
// in_ports_3_getNonFullVCs,
// in_ports_4_putRoutedFlit,
// in_ports_4_getNonFullVCs,
// out_ports_0_getFlit,
// out_ports_0_putNonFullVCs,
// out_ports_1_getFlit,
// out_ports_1_putNonFullVCs,
// out_ports_2_getFlit,
// out_ports_2_putNonFullVCs,
// out_ports_3_getFlit,
// out_ports_3_putNonFullVCs,
// out_ports_4_getFlit,
// out_ports_4_putNonFullVCs
//
// Method: in_ports_4_putRoutedFlit
// Conflict-free: in_ports_0_putRoutedFlit,
// in_ports_0_getNonFullVCs,
// in_ports_1_putRoutedFlit,
// in_ports_1_getNonFullVCs,
// in_ports_2_putRoutedFlit,
// in_ports_2_getNonFullVCs,
// in_ports_3_putRoutedFlit,
// in_ports_3_getNonFullVCs,
// in_ports_4_getNonFullVCs,
// out_ports_0_getFlit,
// out_ports_0_putNonFullVCs,
// out_ports_1_getFlit,
// out_ports_1_putNonFullVCs,
// out_ports_2_getFlit,
// out_ports_2_putNonFullVCs,
// out_ports_3_getFlit,
// out_ports_3_putNonFullVCs,
// out_ports_4_getFlit,
// out_ports_4_putNonFullVCs
// Conflicts: in_ports_4_putRoutedFlit
//
// Method: in_ports_4_getNonFullVCs
// Conflict-free: in_ports_0_putRoutedFlit,
// in_ports_0_getNonFullVCs,
// in_ports_1_putRoutedFlit,
// in_ports_1_getNonFullVCs,
// in_ports_2_putRoutedFlit,
// in_ports_2_getNonFullVCs,
// in_ports_3_putRoutedFlit,
// in_ports_3_getNonFullVCs,
// in_ports_4_putRoutedFlit,
// in_ports_4_getNonFullVCs,
// out_ports_0_getFlit,
// out_ports_0_putNonFullVCs,
// out_ports_1_getFlit,
// out_ports_1_putNonFullVCs,
// out_ports_2_getFlit,
// out_ports_2_putNonFullVCs,
// out_ports_3_getFlit,
// out_ports_3_putNonFullVCs,
// out_ports_4_getFlit,
// out_ports_4_putNonFullVCs
//
// Method: out_ports_0_getFlit
// Conflict-free: in_ports_0_putRoutedFlit,
// in_ports_0_getNonFullVCs,
// in_ports_1_putRoutedFlit,
// in_ports_1_getNonFullVCs,
// in_ports_2_putRoutedFlit,
// in_ports_2_getNonFullVCs,
// in_ports_3_putRoutedFlit,
// in_ports_3_getNonFullVCs,
// in_ports_4_putRoutedFlit,
// in_ports_4_getNonFullVCs,
// out_ports_0_getFlit,
// out_ports_1_getFlit,
// out_ports_2_getFlit,
// out_ports_3_getFlit,
// out_ports_4_getFlit
// Sequenced after (restricted): out_ports_0_putNonFullVCs,
// out_ports_1_putNonFullVCs,
// out_ports_2_putNonFullVCs,
// out_ports_3_putNonFullVCs,
// out_ports_4_putNonFullVCs
//
// Method: out_ports_0_putNonFullVCs
// Conflict-free: in_ports_0_putRoutedFlit,
// in_ports_0_getNonFullVCs,
// in_ports_1_putRoutedFlit,
// in_ports_1_getNonFullVCs,
// in_ports_2_putRoutedFlit,
// in_ports_2_getNonFullVCs,
// in_ports_3_putRoutedFlit,
// in_ports_3_getNonFullVCs,
// in_ports_4_putRoutedFlit,
// in_ports_4_getNonFullVCs,
// out_ports_1_putNonFullVCs,
// out_ports_2_putNonFullVCs,
// out_ports_3_putNonFullVCs,
// out_ports_4_putNonFullVCs
// Sequenced before (restricted): out_ports_0_getFlit,
// out_ports_1_getFlit,
// out_ports_2_getFlit,
// out_ports_3_getFlit,
// out_ports_4_getFlit
// Conflicts: out_ports_0_putNonFullVCs
//
// Method: out_ports_1_getFlit
// Conflict-free: in_ports_0_putRoutedFlit,
// in_ports_0_getNonFullVCs,
// in_ports_1_putRoutedFlit,
// in_ports_1_getNonFullVCs,
// in_ports_2_putRoutedFlit,
// in_ports_2_getNonFullVCs,
// in_ports_3_putRoutedFlit,
// in_ports_3_getNonFullVCs,
// in_ports_4_putRoutedFlit,
// in_ports_4_getNonFullVCs,
// out_ports_0_getFlit,
// out_ports_1_getFlit,
// out_ports_2_getFlit,
// out_ports_3_getFlit,
// out_ports_4_getFlit
// Sequenced after (restricted): out_ports_0_putNonFullVCs,
// out_ports_1_putNonFullVCs,
// out_ports_2_putNonFullVCs,
// out_ports_3_putNonFullVCs,
// out_ports_4_putNonFullVCs
//
// Method: out_ports_1_putNonFullVCs
// Conflict-free: in_ports_0_putRoutedFlit,
// in_ports_0_getNonFullVCs,
// in_ports_1_putRoutedFlit,
// in_ports_1_getNonFullVCs,
// in_ports_2_putRoutedFlit,
// in_ports_2_getNonFullVCs,
// in_ports_3_putRoutedFlit,
// in_ports_3_getNonFullVCs,
// in_ports_4_putRoutedFlit,
// in_ports_4_getNonFullVCs,
// out_ports_0_putNonFullVCs,
// out_ports_2_putNonFullVCs,
// out_ports_3_putNonFullVCs,
// out_ports_4_putNonFullVCs
// Sequenced before (restricted): out_ports_0_getFlit,
// out_ports_1_getFlit,
// out_ports_2_getFlit,
// out_ports_3_getFlit,
// out_ports_4_getFlit
// Conflicts: out_ports_1_putNonFullVCs
//
// Method: out_ports_2_getFlit
// Conflict-free: in_ports_0_putRoutedFlit,
// in_ports_0_getNonFullVCs,
// in_ports_1_putRoutedFlit,
// in_ports_1_getNonFullVCs,
// in_ports_2_putRoutedFlit,
// in_ports_2_getNonFullVCs,
// in_ports_3_putRoutedFlit,
// in_ports_3_getNonFullVCs,
// in_ports_4_putRoutedFlit,
// in_ports_4_getNonFullVCs,
// out_ports_0_getFlit,
// out_ports_1_getFlit,
// out_ports_2_getFlit,
// out_ports_3_getFlit,
// out_ports_4_getFlit
// Sequenced after (restricted): out_ports_0_putNonFullVCs,
// out_ports_1_putNonFullVCs,
// out_ports_2_putNonFullVCs,
// out_ports_3_putNonFullVCs,
// out_ports_4_putNonFullVCs
//
// Method: out_ports_2_putNonFullVCs
// Conflict-free: in_ports_0_putRoutedFlit,
// in_ports_0_getNonFullVCs,
// in_ports_1_putRoutedFlit,
// in_ports_1_getNonFullVCs,
// in_ports_2_putRoutedFlit,
// in_ports_2_getNonFullVCs,
// in_ports_3_putRoutedFlit,
// in_ports_3_getNonFullVCs,
// in_ports_4_putRoutedFlit,
// in_ports_4_getNonFullVCs,
// out_ports_0_putNonFullVCs,
// out_ports_1_putNonFullVCs,
// out_ports_3_putNonFullVCs,
// out_ports_4_putNonFullVCs
// Sequenced before (restricted): out_ports_0_getFlit,
// out_ports_1_getFlit,
// out_ports_2_getFlit,
// out_ports_3_getFlit,
// out_ports_4_getFlit
// Conflicts: out_ports_2_putNonFullVCs
//
// Method: out_ports_3_getFlit
// Conflict-free: in_ports_0_putRoutedFlit,
// in_ports_0_getNonFullVCs,
// in_ports_1_putRoutedFlit,
// in_ports_1_getNonFullVCs,
// in_ports_2_putRoutedFlit,
// in_ports_2_getNonFullVCs,
// in_ports_3_putRoutedFlit,
// in_ports_3_getNonFullVCs,
// in_ports_4_putRoutedFlit,
// in_ports_4_getNonFullVCs,
// out_ports_0_getFlit,
// out_ports_1_getFlit,
// out_ports_2_getFlit,
// out_ports_3_getFlit,
// out_ports_4_getFlit
// Sequenced after (restricted): out_ports_0_putNonFullVCs,
// out_ports_1_putNonFullVCs,
// out_ports_2_putNonFullVCs,
// out_ports_3_putNonFullVCs,
// out_ports_4_putNonFullVCs
//
// Method: out_ports_3_putNonFullVCs
// Conflict-free: in_ports_0_putRoutedFlit,
// in_ports_0_getNonFullVCs,
// in_ports_1_putRoutedFlit,
// in_ports_1_getNonFullVCs,
// in_ports_2_putRoutedFlit,
// in_ports_2_getNonFullVCs,
// in_ports_3_putRoutedFlit,
// in_ports_3_getNonFullVCs,
// in_ports_4_putRoutedFlit,
// in_ports_4_getNonFullVCs,
// out_ports_0_putNonFullVCs,
// out_ports_1_putNonFullVCs,
// out_ports_2_putNonFullVCs,
// out_ports_4_putNonFullVCs
// Sequenced before (restricted): out_ports_0_getFlit,
// out_ports_1_getFlit,
// out_ports_2_getFlit,
// out_ports_3_getFlit,
// out_ports_4_getFlit
// Conflicts: out_ports_3_putNonFullVCs
//
// Method: out_ports_4_getFlit
// Conflict-free: in_ports_0_putRoutedFlit,
// in_ports_0_getNonFullVCs,
// in_ports_1_putRoutedFlit,
// in_ports_1_getNonFullVCs,
// in_ports_2_putRoutedFlit,
// in_ports_2_getNonFullVCs,
// in_ports_3_putRoutedFlit,
// in_ports_3_getNonFullVCs,
// in_ports_4_putRoutedFlit,
// in_ports_4_getNonFullVCs,
// out_ports_0_getFlit,
// out_ports_1_getFlit,
// out_ports_2_getFlit,
// out_ports_3_getFlit,
// out_ports_4_getFlit
// Sequenced after (restricted): out_ports_0_putNonFullVCs,
// out_ports_1_putNonFullVCs,
// out_ports_2_putNonFullVCs,
// out_ports_3_putNonFullVCs,
// out_ports_4_putNonFullVCs
//
// Method: out_ports_4_putNonFullVCs
// Conflict-free: in_ports_0_putRoutedFlit,
// in_ports_0_getNonFullVCs,
// in_ports_1_putRoutedFlit,
// in_ports_1_getNonFullVCs,
// in_ports_2_putRoutedFlit,
// in_ports_2_getNonFullVCs,
// in_ports_3_putRoutedFlit,
// in_ports_3_getNonFullVCs,
// in_ports_4_putRoutedFlit,
// in_ports_4_getNonFullVCs,
// out_ports_0_putNonFullVCs,
// out_ports_1_putNonFullVCs,
// out_ports_2_putNonFullVCs,
// out_ports_3_putNonFullVCs
// Sequenced before (restricted): out_ports_0_getFlit,
// out_ports_1_getFlit,
// out_ports_2_getFlit,
// out_ports_3_getFlit,
// out_ports_4_getFlit
// Conflicts: out_ports_4_putNonFullVCs
//
//
// Ports:
// Name I/O size props
// in_ports_0_getNonFullVCs O 2 reg
// in_ports_1_getNonFullVCs O 2 reg
// in_ports_2_getNonFullVCs O 2 reg
// in_ports_3_getNonFullVCs O 2 reg
// in_ports_4_getNonFullVCs O 2 reg
// out_ports_0_getFlit O 71
// out_ports_1_getFlit O 71
// out_ports_2_getFlit O 71
// out_ports_3_getFlit O 71
// out_ports_4_getFlit O 71
// CLK I 1 clock
// RST_N I 1 reset
// in_ports_0_putRoutedFlit_flit_in I 74
// in_ports_1_putRoutedFlit_flit_in I 74
// in_ports_2_putRoutedFlit_flit_in I 74
// in_ports_3_putRoutedFlit_flit_in I 74
// in_ports_4_putRoutedFlit_flit_in I 74
// out_ports_0_putNonFullVCs_nonFullVCs I 2
// out_ports_1_putNonFullVCs_nonFullVCs I 2
// out_ports_2_putNonFullVCs_nonFullVCs I 2
// out_ports_3_putNonFullVCs_nonFullVCs I 2
// out_ports_4_putNonFullVCs_nonFullVCs I 2
// EN_in_ports_0_putRoutedFlit I 1
// EN_in_ports_1_putRoutedFlit I 1
// EN_in_ports_2_putRoutedFlit I 1
// EN_in_ports_3_putRoutedFlit I 1
// EN_in_ports_4_putRoutedFlit I 1
// EN_out_ports_0_putNonFullVCs I 1
// EN_out_ports_1_putNonFullVCs I 1
// EN_out_ports_2_putNonFullVCs I 1
// EN_out_ports_3_putNonFullVCs I 1
// EN_out_ports_4_putNonFullVCs I 1
// EN_in_ports_0_getNonFullVCs I 1 unused
// EN_in_ports_1_getNonFullVCs I 1 unused
// EN_in_ports_2_getNonFullVCs I 1 unused
// EN_in_ports_3_getNonFullVCs I 1 unused
// EN_in_ports_4_getNonFullVCs I 1 unused
// EN_out_ports_0_getFlit I 1 unused
// EN_out_ports_1_getFlit I 1 unused
// EN_out_ports_2_getFlit I 1 unused
// EN_out_ports_3_getFlit I 1 unused
// EN_out_ports_4_getFlit I 1 unused
//
// Combinational paths from inputs to outputs:
// (out_ports_0_putNonFullVCs_nonFullVCs,
// out_ports_1_putNonFullVCs_nonFullVCs,
// out_ports_2_putNonFullVCs_nonFullVCs,
// out_ports_3_putNonFullVCs_nonFullVCs,
// out_ports_4_putNonFullVCs_nonFullVCs,
// EN_out_ports_0_putNonFullVCs,
// EN_out_ports_1_putNonFullVCs,
// EN_out_ports_2_putNonFullVCs,
// EN_out_ports_3_putNonFullVCs,
// EN_out_ports_4_putNonFullVCs) -> out_ports_0_getFlit
// (out_ports_0_putNonFullVCs_nonFullVCs,
// out_ports_1_putNonFullVCs_nonFullVCs,
// out_ports_2_putNonFullVCs_nonFullVCs,
// out_ports_3_putNonFullVCs_nonFullVCs,
// out_ports_4_putNonFullVCs_nonFullVCs,
// EN_out_ports_0_putNonFullVCs,
// EN_out_ports_1_putNonFullVCs,
// EN_out_ports_2_putNonFullVCs,
// EN_out_ports_3_putNonFullVCs,
// EN_out_ports_4_putNonFullVCs) -> out_ports_1_getFlit
// (out_ports_0_putNonFullVCs_nonFullVCs,
// out_ports_1_putNonFullVCs_nonFullVCs,
// out_ports_2_putNonFullVCs_nonFullVCs,
// out_ports_3_putNonFullVCs_nonFullVCs,
// out_ports_4_putNonFullVCs_nonFullVCs,
// EN_out_ports_0_putNonFullVCs,
// EN_out_ports_1_putNonFullVCs,
// EN_out_ports_2_putNonFullVCs,
// EN_out_ports_3_putNonFullVCs,
// EN_out_ports_4_putNonFullVCs) -> out_ports_2_getFlit
// (out_ports_0_putNonFullVCs_nonFullVCs,
// out_ports_1_putNonFullVCs_nonFullVCs,
// out_ports_2_putNonFullVCs_nonFullVCs,
// out_ports_3_putNonFullVCs_nonFullVCs,
// out_ports_4_putNonFullVCs_nonFullVCs,
// EN_out_ports_0_putNonFullVCs,
// EN_out_ports_1_putNonFullVCs,
// EN_out_ports_2_putNonFullVCs,
// EN_out_ports_3_putNonFullVCs,
// EN_out_ports_4_putNonFullVCs) -> out_ports_3_getFlit
// (out_ports_0_putNonFullVCs_nonFullVCs,
// out_ports_1_putNonFullVCs_nonFullVCs,
// out_ports_2_putNonFullVCs_nonFullVCs,
// out_ports_3_putNonFullVCs_nonFullVCs,
// out_ports_4_putNonFullVCs_nonFullVCs,
// EN_out_ports_0_putNonFullVCs,
// EN_out_ports_1_putNonFullVCs,
// EN_out_ports_2_putNonFullVCs,
// EN_out_ports_3_putNonFullVCs,
// EN_out_ports_4_putNonFullVCs) -> out_ports_4_getFlit
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
module mkRouterCoreSimple(CLK,
RST_N,
in_ports_0_putRoutedFlit_flit_in,
EN_in_ports_0_putRoutedFlit,
EN_in_ports_0_getNonFullVCs,
in_ports_0_getNonFullVCs,
in_ports_1_putRoutedFlit_flit_in,
EN_in_ports_1_putRoutedFlit,
EN_in_ports_1_getNonFullVCs,
in_ports_1_getNonFullVCs,
in_ports_2_putRoutedFlit_flit_in,
EN_in_ports_2_putRoutedFlit,
EN_in_ports_2_getNonFullVCs,
in_ports_2_getNonFullVCs,
in_ports_3_putRoutedFlit_flit_in,
EN_in_ports_3_putRoutedFlit,
EN_in_ports_3_getNonFullVCs,
in_ports_3_getNonFullVCs,
in_ports_4_putRoutedFlit_flit_in,
EN_in_ports_4_putRoutedFlit,
EN_in_ports_4_getNonFullVCs,
in_ports_4_getNonFullVCs,
EN_out_ports_0_getFlit,
out_ports_0_getFlit,
out_ports_0_putNonFullVCs_nonFullVCs,
EN_out_ports_0_putNonFullVCs,
EN_out_ports_1_getFlit,
out_ports_1_getFlit,
out_ports_1_putNonFullVCs_nonFullVCs,
EN_out_ports_1_putNonFullVCs,
EN_out_ports_2_getFlit,
out_ports_2_getFlit,
out_ports_2_putNonFullVCs_nonFullVCs,
EN_out_ports_2_putNonFullVCs,
EN_out_ports_3_getFlit,
out_ports_3_getFlit,
out_ports_3_putNonFullVCs_nonFullVCs,
EN_out_ports_3_putNonFullVCs,
EN_out_ports_4_getFlit,
out_ports_4_getFlit,
out_ports_4_putNonFullVCs_nonFullVCs,
EN_out_ports_4_putNonFullVCs);
input CLK;
input RST_N;
// action method in_ports_0_putRoutedFlit
input [73 : 0] in_ports_0_putRoutedFlit_flit_in;
input EN_in_ports_0_putRoutedFlit;
// actionvalue method in_ports_0_getNonFullVCs
input EN_in_ports_0_getNonFullVCs;
output [1 : 0] in_ports_0_getNonFullVCs;
// action method in_ports_1_putRoutedFlit
input [73 : 0] in_ports_1_putRoutedFlit_flit_in;
input EN_in_ports_1_putRoutedFlit;
// actionvalue method in_ports_1_getNonFullVCs
input EN_in_ports_1_getNonFullVCs;
output [1 : 0] in_ports_1_getNonFullVCs;
// action method in_ports_2_putRoutedFlit
input [73 : 0] in_ports_2_putRoutedFlit_flit_in;
input EN_in_ports_2_putRoutedFlit;
// actionvalue method in_ports_2_getNonFullVCs
input EN_in_ports_2_getNonFullVCs;
output [1 : 0] in_ports_2_getNonFullVCs;
// action method in_ports_3_putRoutedFlit
input [73 : 0] in_ports_3_putRoutedFlit_flit_in;
input EN_in_ports_3_putRoutedFlit;
// actionvalue method in_ports_3_getNonFullVCs
input EN_in_ports_3_getNonFullVCs;
output [1 : 0] in_ports_3_getNonFullVCs;
// action method in_ports_4_putRoutedFlit
input [73 : 0] in_ports_4_putRoutedFlit_flit_in;
input EN_in_ports_4_putRoutedFlit;
// actionvalue method in_ports_4_getNonFullVCs
input EN_in_ports_4_getNonFullVCs;
output [1 : 0] in_ports_4_getNonFullVCs;
// actionvalue method out_ports_0_getFlit
input EN_out_ports_0_getFlit;
output [70 : 0] out_ports_0_getFlit;
// action method out_ports_0_putNonFullVCs
input [1 : 0] out_ports_0_putNonFullVCs_nonFullVCs;
input EN_out_ports_0_putNonFullVCs;
// actionvalue method out_ports_1_getFlit
input EN_out_ports_1_getFlit;
output [70 : 0] out_ports_1_getFlit;
// action method out_ports_1_putNonFullVCs
input [1 : 0] out_ports_1_putNonFullVCs_nonFullVCs;
input EN_out_ports_1_putNonFullVCs;
// actionvalue method out_ports_2_getFlit
input EN_out_ports_2_getFlit;
output [70 : 0] out_ports_2_getFlit;
// action method out_ports_2_putNonFullVCs
input [1 : 0] out_ports_2_putNonFullVCs_nonFullVCs;
input EN_out_ports_2_putNonFullVCs;
// actionvalue method out_ports_3_getFlit
input EN_out_ports_3_getFlit;
output [70 : 0] out_ports_3_getFlit;
// action method out_ports_3_putNonFullVCs
input [1 : 0] out_ports_3_putNonFullVCs_nonFullVCs;
input EN_out_ports_3_putNonFullVCs;
// actionvalue method out_ports_4_getFlit
input EN_out_ports_4_getFlit;
output [70 : 0] out_ports_4_getFlit;
// action method out_ports_4_putNonFullVCs
input [1 : 0] out_ports_4_putNonFullVCs_nonFullVCs;
input EN_out_ports_4_putNonFullVCs;
// signals for module outputs
wire [70 : 0] out_ports_0_getFlit,
out_ports_1_getFlit,
out_ports_2_getFlit,
out_ports_3_getFlit,
out_ports_4_getFlit;
wire [1 : 0] in_ports_0_getNonFullVCs,
in_ports_1_getNonFullVCs,
in_ports_2_getNonFullVCs,
in_ports_3_getNonFullVCs,
in_ports_4_getNonFullVCs;
// inlined wires
wire [70 : 0] hasFlitsToSend_perIn$wget,
hasFlitsToSend_perIn_1$wget,
hasFlitsToSend_perIn_2$wget,
hasFlitsToSend_perIn_3$wget,
hasFlitsToSend_perIn_4$wget;
// register activeVC_perIn_reg
reg [1 : 0] activeVC_perIn_reg;
wire [1 : 0] activeVC_perIn_reg$D_IN;
wire activeVC_perIn_reg$EN;
// register activeVC_perIn_reg_1
reg [1 : 0] activeVC_perIn_reg_1;
wire [1 : 0] activeVC_perIn_reg_1$D_IN;
wire activeVC_perIn_reg_1$EN;
// register activeVC_perIn_reg_2
reg [1 : 0] activeVC_perIn_reg_2;
wire [1 : 0] activeVC_perIn_reg_2$D_IN;
wire activeVC_perIn_reg_2$EN;
// register activeVC_perIn_reg_3
reg [1 : 0] activeVC_perIn_reg_3;
wire [1 : 0] activeVC_perIn_reg_3$D_IN;
wire activeVC_perIn_reg_3$EN;
// register activeVC_perIn_reg_4
reg [1 : 0] activeVC_perIn_reg_4;
wire [1 : 0] activeVC_perIn_reg_4$D_IN;
wire activeVC_perIn_reg_4$EN;
// register inPortVL_0
reg [2 : 0] inPortVL_0;
wire [2 : 0] inPortVL_0$D_IN;
wire inPortVL_0$EN;
// register inPortVL_0_1
reg [2 : 0] inPortVL_0_1;
wire [2 : 0] inPortVL_0_1$D_IN;
wire inPortVL_0_1$EN;
// register inPortVL_1
reg [2 : 0] inPortVL_1;
wire [2 : 0] inPortVL_1$D_IN;
wire inPortVL_1$EN;
// register inPortVL_1_1
reg [2 : 0] inPortVL_1_1;
wire [2 : 0] inPortVL_1_1$D_IN;
wire inPortVL_1_1$EN;
// register inPortVL_2
reg [2 : 0] inPortVL_2;
wire [2 : 0] inPortVL_2$D_IN;
wire inPortVL_2$EN;
// register inPortVL_2_1
reg [2 : 0] inPortVL_2_1;
wire [2 : 0] inPortVL_2_1$D_IN;
wire inPortVL_2_1$EN;
// register inPortVL_3
reg [2 : 0] inPortVL_3;
wire [2 : 0] inPortVL_3$D_IN;
wire inPortVL_3$EN;
// register inPortVL_3_1
reg [2 : 0] inPortVL_3_1;
wire [2 : 0] inPortVL_3_1$D_IN;
wire inPortVL_3_1$EN;
// register inPortVL_4
reg [2 : 0] inPortVL_4;
wire [2 : 0] inPortVL_4$D_IN;
wire inPortVL_4$EN;
// register inPortVL_4_1
reg [2 : 0] inPortVL_4_1;
wire [2 : 0] inPortVL_4_1$D_IN;
wire inPortVL_4_1$EN;
// register lockedVL_0
reg lockedVL_0;
wire lockedVL_0$D_IN, lockedVL_0$EN;
// register lockedVL_0_1
reg lockedVL_0_1;
wire lockedVL_0_1$D_IN, lockedVL_0_1$EN;
// register lockedVL_1
reg lockedVL_1;
wire lockedVL_1$D_IN, lockedVL_1$EN;
// register lockedVL_1_1
reg lockedVL_1_1;
wire lockedVL_1_1$D_IN, lockedVL_1_1$EN;
// register lockedVL_2
reg lockedVL_2;
wire lockedVL_2$D_IN, lockedVL_2$EN;
// register lockedVL_2_1
reg lockedVL_2_1;
wire lockedVL_2_1$D_IN, lockedVL_2_1$EN;
// register lockedVL_3
reg lockedVL_3;
wire lockedVL_3$D_IN, lockedVL_3$EN;
// register lockedVL_3_1
reg lockedVL_3_1;
wire lockedVL_3_1$D_IN, lockedVL_3_1$EN;
// register lockedVL_4
reg lockedVL_4;
wire lockedVL_4$D_IN, lockedVL_4$EN;
// register lockedVL_4_1
reg lockedVL_4_1;
wire lockedVL_4_1$D_IN, lockedVL_4_1$EN;
// register selectedIO_reg_0
reg selectedIO_reg_0;
wire selectedIO_reg_0$D_IN, selectedIO_reg_0$EN;
// register selectedIO_reg_0_1
reg selectedIO_reg_0_1;
wire selectedIO_reg_0_1$D_IN, selectedIO_reg_0_1$EN;
// register selectedIO_reg_0_2
reg selectedIO_reg_0_2;
wire selectedIO_reg_0_2$D_IN, selectedIO_reg_0_2$EN;
// register selectedIO_reg_0_3
reg selectedIO_reg_0_3;
wire selectedIO_reg_0_3$D_IN, selectedIO_reg_0_3$EN;
// register selectedIO_reg_0_4
reg selectedIO_reg_0_4;
wire selectedIO_reg_0_4$D_IN, selectedIO_reg_0_4$EN;
// register selectedIO_reg_1
reg selectedIO_reg_1;
wire selectedIO_reg_1$D_IN, selectedIO_reg_1$EN;
// register selectedIO_reg_1_1
reg selectedIO_reg_1_1;
wire selectedIO_reg_1_1$D_IN, selectedIO_reg_1_1$EN;
// register selectedIO_reg_1_2
reg selectedIO_reg_1_2;
wire selectedIO_reg_1_2$D_IN, selectedIO_reg_1_2$EN;
// register selectedIO_reg_1_3
reg selectedIO_reg_1_3;
wire selectedIO_reg_1_3$D_IN, selectedIO_reg_1_3$EN;
// register selectedIO_reg_1_4
reg selectedIO_reg_1_4;
wire selectedIO_reg_1_4$D_IN, selectedIO_reg_1_4$EN;
// register selectedIO_reg_2
reg selectedIO_reg_2;
wire selectedIO_reg_2$D_IN, selectedIO_reg_2$EN;
// register selectedIO_reg_2_1
reg selectedIO_reg_2_1;
wire selectedIO_reg_2_1$D_IN, selectedIO_reg_2_1$EN;
// register selectedIO_reg_2_2
reg selectedIO_reg_2_2;
wire selectedIO_reg_2_2$D_IN, selectedIO_reg_2_2$EN;
// register selectedIO_reg_2_3
reg selectedIO_reg_2_3;
wire selectedIO_reg_2_3$D_IN, selectedIO_reg_2_3$EN;
// register selectedIO_reg_2_4
reg selectedIO_reg_2_4;
wire selectedIO_reg_2_4$D_IN, selectedIO_reg_2_4$EN;
// register selectedIO_reg_3
reg selectedIO_reg_3;
wire selectedIO_reg_3$D_IN, selectedIO_reg_3$EN;
// register selectedIO_reg_3_1
reg selectedIO_reg_3_1;
wire selectedIO_reg_3_1$D_IN, selectedIO_reg_3_1$EN;
// register selectedIO_reg_3_2
reg selectedIO_reg_3_2;
wire selectedIO_reg_3_2$D_IN, selectedIO_reg_3_2$EN;
// register selectedIO_reg_3_3
reg selectedIO_reg_3_3;
wire selectedIO_reg_3_3$D_IN, selectedIO_reg_3_3$EN;
// register selectedIO_reg_3_4
reg selectedIO_reg_3_4;
wire selectedIO_reg_3_4$D_IN, selectedIO_reg_3_4$EN;
// register selectedIO_reg_4
reg selectedIO_reg_4;
wire selectedIO_reg_4$D_IN, selectedIO_reg_4$EN;
// register selectedIO_reg_4_1
reg selectedIO_reg_4_1;
wire selectedIO_reg_4_1$D_IN, selectedIO_reg_4_1$EN;
// register selectedIO_reg_4_2
reg selectedIO_reg_4_2;
wire selectedIO_reg_4_2$D_IN, selectedIO_reg_4_2$EN;
// register selectedIO_reg_4_3
reg selectedIO_reg_4_3;
wire selectedIO_reg_4_3$D_IN, selectedIO_reg_4_3$EN;
// register selectedIO_reg_4_4
reg selectedIO_reg_4_4;
wire selectedIO_reg_4_4$D_IN, selectedIO_reg_4_4$EN;
// ports of submodule flitBuffers
wire [69 : 0] flitBuffers$deq, flitBuffers$enq_data_in;
wire [1 : 0] flitBuffers$notEmpty, flitBuffers$notFull;
wire flitBuffers$EN_deq,
flitBuffers$EN_enq,
flitBuffers$deq_fifo_out,
flitBuffers$enq_fifo_in;
// ports of submodule flitBuffers_1
wire [69 : 0] flitBuffers_1$deq, flitBuffers_1$enq_data_in;
wire [1 : 0] flitBuffers_1$notEmpty, flitBuffers_1$notFull;
wire flitBuffers_1$EN_deq,
flitBuffers_1$EN_enq,
flitBuffers_1$deq_fifo_out,
flitBuffers_1$enq_fifo_in;
// ports of submodule flitBuffers_2
wire [69 : 0] flitBuffers_2$deq, flitBuffers_2$enq_data_in;
wire [1 : 0] flitBuffers_2$notEmpty, flitBuffers_2$notFull;
wire flitBuffers_2$EN_deq,
flitBuffers_2$EN_enq,
flitBuffers_2$deq_fifo_out,
flitBuffers_2$enq_fifo_in;
// ports of submodule flitBuffers_3
wire [69 : 0] flitBuffers_3$deq, flitBuffers_3$enq_data_in;
wire [1 : 0] flitBuffers_3$notEmpty, flitBuffers_3$notFull;
wire flitBuffers_3$EN_deq,
flitBuffers_3$EN_enq,
flitBuffers_3$deq_fifo_out,
flitBuffers_3$enq_fifo_in;
// ports of submodule flitBuffers_4
wire [69 : 0] flitBuffers_4$deq, flitBuffers_4$enq_data_in;
wire [1 : 0] flitBuffers_4$notEmpty, flitBuffers_4$notFull;
wire flitBuffers_4$EN_deq,
flitBuffers_4$EN_enq,
flitBuffers_4$deq_fifo_out,
flitBuffers_4$enq_fifo_in;
// ports of submodule outPortFIFOs_0
wire [2 : 0] outPortFIFOs_0$enq_sendData, outPortFIFOs_0$first;
wire outPortFIFOs_0$EN_clear, outPortFIFOs_0$EN_deq, outPortFIFOs_0$EN_enq;
// ports of submodule outPortFIFOs_0_1
wire [2 : 0] outPortFIFOs_0_1$enq_sendData, outPortFIFOs_0_1$first;
wire outPortFIFOs_0_1$EN_clear,
outPortFIFOs_0_1$EN_deq,
outPortFIFOs_0_1$EN_enq;
// ports of submodule outPortFIFOs_1
wire [2 : 0] outPortFIFOs_1$enq_sendData, outPortFIFOs_1$first;
wire outPortFIFOs_1$EN_clear, outPortFIFOs_1$EN_deq, outPortFIFOs_1$EN_enq;
// ports of submodule outPortFIFOs_1_1
wire [2 : 0] outPortFIFOs_1_1$enq_sendData, outPortFIFOs_1_1$first;
wire outPortFIFOs_1_1$EN_clear,
outPortFIFOs_1_1$EN_deq,
outPortFIFOs_1_1$EN_enq;
// ports of submodule outPortFIFOs_2
wire [2 : 0] outPortFIFOs_2$enq_sendData, outPortFIFOs_2$first;
wire outPortFIFOs_2$EN_clear, outPortFIFOs_2$EN_deq, outPortFIFOs_2$EN_enq;
// ports of submodule outPortFIFOs_2_1
wire [2 : 0] outPortFIFOs_2_1$enq_sendData, outPortFIFOs_2_1$first;
wire outPortFIFOs_2_1$EN_clear,
outPortFIFOs_2_1$EN_deq,
outPortFIFOs_2_1$EN_enq;
// ports of submodule outPortFIFOs_3
wire [2 : 0] outPortFIFOs_3$enq_sendData, outPortFIFOs_3$first;
wire outPortFIFOs_3$EN_clear, outPortFIFOs_3$EN_deq, outPortFIFOs_3$EN_enq;
// ports of submodule outPortFIFOs_3_1
wire [2 : 0] outPortFIFOs_3_1$enq_sendData, outPortFIFOs_3_1$first;
wire outPortFIFOs_3_1$EN_clear,
outPortFIFOs_3_1$EN_deq,
outPortFIFOs_3_1$EN_enq;
// ports of submodule outPortFIFOs_4
wire [2 : 0] outPortFIFOs_4$enq_sendData, outPortFIFOs_4$first;
wire outPortFIFOs_4$EN_clear, outPortFIFOs_4$EN_deq, outPortFIFOs_4$EN_enq;
// ports of submodule outPortFIFOs_4_1
wire [2 : 0] outPortFIFOs_4_1$enq_sendData, outPortFIFOs_4_1$first;
wire outPortFIFOs_4_1$EN_clear,
outPortFIFOs_4_1$EN_deq,
outPortFIFOs_4_1$EN_enq;
// ports of submodule routerAlloc
wire [24 : 0] routerAlloc$allocate, routerAlloc$allocate_alloc_input;
wire routerAlloc$EN_allocate, routerAlloc$EN_next;
// remaining internal signals
reg [69 : 0] IF_IF_outport_encoder_37_BIT_3_38_THEN_IF_outp_ETC___d1162,
IF_IF_outport_encoder_37_BIT_3_38_THEN_IF_outp_ETC___d1163,
IF_IF_outport_encoder_37_BIT_3_38_THEN_IF_outp_ETC___d1164,
IF_IF_outport_encoder_37_BIT_3_38_THEN_IF_outp_ETC___d1165;
reg IF_IF_outport_encoder_37_BIT_3_38_THEN_IF_outp_ETC___d1172,
IF_IF_outport_encoder_37_BIT_3_38_THEN_IF_outp_ETC___d1173,
IF_IF_outport_encoder_37_BIT_3_38_THEN_IF_outp_ETC___d1174,
IF_IF_outport_encoder_37_BIT_3_38_THEN_IF_outp_ETC___d1175,
IF_IF_outport_encoder_37_BIT_3_38_THEN_IF_outp_ETC___d671,
IF_IF_outport_encoder_37_BIT_3_38_THEN_IF_outp_ETC___d735,
IF_IF_outport_encoder_37_BIT_3_38_THEN_IF_outp_ETC___d799,
IF_IF_outport_encoder_37_BIT_3_38_THEN_IF_outp_ETC___d863,
IF_outPortFIFOs_0_1_first__12_EQ_0_13_THEN_sim_ETC___d1033,
IF_outPortFIFOs_0_first__98_EQ_0_99_THEN_NOT_s_ETC___d304,
IF_outPortFIFOs_0_first__98_EQ_0_99_THEN_simpl_ETC___d952,
IF_outPortFIFOs_1_1_first__71_EQ_0_72_THEN_sim_ETC___d1026,
IF_outPortFIFOs_1_first__57_EQ_0_58_THEN_NOT_s_ETC___d339,
IF_outPortFIFOs_1_first__57_EQ_0_58_THEN_simpl_ETC___d950,
IF_outPortFIFOs_2_1_first__29_EQ_0_30_THEN_sim_ETC___d1019,
IF_outPortFIFOs_2_first__15_EQ_0_16_THEN_NOT_s_ETC___d374,
IF_outPortFIFOs_2_first__15_EQ_0_16_THEN_simpl_ETC___d948,
IF_outPortFIFOs_3_1_first__8_EQ_0_9_THEN_simpl_ETC___d1013,
IF_outPortFIFOs_3_first__4_EQ_0_5_THEN_NOT_sim_ETC___d409,
IF_outPortFIFOs_3_first__4_EQ_0_5_THEN_simple__ETC___d946,
IF_outPortFIFOs_4_1_first__2_EQ_0_3_THEN_simpl_ETC___d1007,
IF_outPortFIFOs_4_first_EQ_0_THEN_NOT_simple_c_ETC___d444,
IF_outPortFIFOs_4_first_EQ_0_THEN_simple_credi_ETC___d944;
wire [69 : 0] IF_IF_outport_encoder_37_BIT_3_38_THEN_NOT_out_ETC___d1161,
IF_IF_outport_encoder_37_BIT_3_38_THEN_NOT_out_ETC___d612;
wire [4 : 0] IF_IF_outPortFIFOs_0_first__98_EQ_0_99_THEN_si_ETC___d235,
IF_IF_outPortFIFOs_1_first__57_EQ_0_58_THEN_si_ETC___d194,
IF_IF_outPortFIFOs_2_first__15_EQ_0_16_THEN_si_ETC___d152,
IF_IF_outPortFIFOs_3_first__4_EQ_0_5_THEN_simp_ETC___d111,
IF_IF_outPortFIFOs_4_first_EQ_0_THEN_simple_cr_ETC___d70,
IF_flitBuffers_1_notEmpty__55_BIT_0_56_THEN_IF_ETC___d195,
IF_flitBuffers_2_notEmpty__13_BIT_0_14_THEN_IF_ETC___d153,
IF_flitBuffers_3_notEmpty__2_BIT_0_3_THEN_IF_I_ETC___d112,
IF_flitBuffers_4_notEmpty_BIT_0_THEN_IF_IF_out_ETC___d71,
IF_flitBuffers_notEmpty__96_BIT_0_97_THEN_IF_I_ETC___d236;
wire [3 : 0] outport_encoder___d1113,
outport_encoder___d1114,
outport_encoder___d1115,
outport_encoder___d1116,
outport_encoder___d1117;
wire [2 : 0] IF_outport_encoder_02_BIT_3_03_THEN_IF_outport_ETC___d910,
IF_outport_encoder_02_BIT_3_03_THEN_IF_outport_ETC___d911,
IF_outport_encoder_02_BIT_3_03_THEN_IF_outport_ETC___d912,
IF_outport_encoder_02_BIT_3_03_THEN_IF_outport_ETC___d913,
IF_outport_encoder_32_BIT_3_33_THEN_IF_outport_ETC___d918,
IF_outport_encoder_32_BIT_3_33_THEN_IF_outport_ETC___d919,
IF_outport_encoder_32_BIT_3_33_THEN_IF_outport_ETC___d920,
IF_outport_encoder_32_BIT_3_33_THEN_IF_outport_ETC___d921,
IF_outport_encoder_67_BIT_3_68_THEN_IF_outport_ETC___d914,
IF_outport_encoder_67_BIT_3_68_THEN_IF_outport_ETC___d915,
IF_outport_encoder_67_BIT_3_68_THEN_IF_outport_ETC___d916,
IF_outport_encoder_67_BIT_3_68_THEN_IF_outport_ETC___d917,
active_in__h48706,
active_in__h50467,
active_in__h52228,
active_in__h53989;
wire IF_IF_outport_encoder_37_BIT_3_38_THEN_NOT_out_ETC___d1171,
IF_IF_outport_encoder_37_BIT_3_38_THEN_NOT_out_ETC___d580,
IF_IF_outport_encoder_37_BIT_3_38_THEN_NOT_out_ETC___d581,
IF_IF_outport_encoder_37_BIT_3_38_THEN_NOT_out_ETC___d582,
IF_IF_outport_encoder_37_BIT_3_38_THEN_NOT_out_ETC___d593,
IF_IF_outport_encoder_37_BIT_3_38_THEN_NOT_out_ETC___d594,
IF_IF_outport_encoder_37_BIT_3_38_THEN_NOT_out_ETC___d595,
IF_IF_outport_encoder_37_BIT_3_38_THEN_NOT_out_ETC___d596,
IF_outport_encoder_02_BIT_3_03_THEN_NOT_outpor_ETC___d1105,
IF_outport_encoder_02_BIT_3_03_THEN_NOT_outpor_ETC___d1106,
IF_outport_encoder_02_BIT_3_03_THEN_NOT_outpor_ETC___d1107,
IF_outport_encoder_02_BIT_3_03_THEN_NOT_outpor_ETC___d1108,
IF_outport_encoder_02_BIT_3_03_THEN_NOT_outpor_ETC___d1109,
IF_outport_encoder_02_BIT_3_03_THEN_NOT_outpor_ETC___d898,
IF_outport_encoder_02_BIT_3_03_THEN_NOT_outpor_ETC___d902,
IF_outport_encoder_02_BIT_3_03_THEN_NOT_outpor_ETC___d903,
IF_outport_encoder_02_BIT_3_03_THEN_outport_en_ETC___d1126,
IF_outport_encoder_02_BIT_3_03_THEN_outport_en_ETC___d1131,
IF_outport_encoder_02_BIT_3_03_THEN_outport_en_ETC___d1136,
IF_outport_encoder_02_BIT_3_03_THEN_outport_en_ETC___d1141,
IF_outport_encoder_02_BIT_3_03_THEN_outport_en_ETC___d1146,
IF_outport_encoder_32_BIT_3_33_THEN_NOT_outpor_ETC___d958,
IF_outport_encoder_32_BIT_3_33_THEN_NOT_outpor_ETC___d968,
IF_outport_encoder_32_BIT_3_33_THEN_NOT_outpor_ETC___d976,
IF_outport_encoder_32_BIT_3_33_THEN_NOT_outpor_ETC___d984,
IF_outport_encoder_32_BIT_3_33_THEN_NOT_outpor_ETC___d992,
IF_outport_encoder_32_BIT_3_33_THEN_outport_en_ETC___d1124,
IF_outport_encoder_32_BIT_3_33_THEN_outport_en_ETC___d1129,
IF_outport_encoder_32_BIT_3_33_THEN_outport_en_ETC___d1134,
IF_outport_encoder_32_BIT_3_33_THEN_outport_en_ETC___d1139,
IF_outport_encoder_32_BIT_3_33_THEN_outport_en_ETC___d1144,
IF_outport_encoder_37_BIT_3_38_THEN_NOT_outpor_ETC___d1047,
IF_outport_encoder_37_BIT_3_38_THEN_NOT_outpor_ETC___d1089,
IF_outport_encoder_37_BIT_3_38_THEN_NOT_outpor_ETC___d1090,
IF_outport_encoder_37_BIT_3_38_THEN_NOT_outpor_ETC___d1091,
IF_outport_encoder_37_BIT_3_38_THEN_outport_en_ETC___d1046,
IF_outport_encoder_37_BIT_3_38_THEN_outport_en_ETC___d1056,
IF_outport_encoder_37_BIT_3_38_THEN_outport_en_ETC___d1058,
IF_outport_encoder_37_BIT_3_38_THEN_outport_en_ETC___d1060,
IF_outport_encoder_37_BIT_3_38_THEN_outport_en_ETC___d1062,
IF_outport_encoder_67_BIT_3_68_THEN_NOT_outpor_ETC___d901,
IF_outport_encoder_67_BIT_3_68_THEN_NOT_outpor_ETC___d907,
IF_outport_encoder_67_BIT_3_68_THEN_NOT_outpor_ETC___d955,
IF_outport_encoder_67_BIT_3_68_THEN_NOT_outpor_ETC___d966,
IF_outport_encoder_67_BIT_3_68_THEN_NOT_outpor_ETC___d974,
IF_outport_encoder_67_BIT_3_68_THEN_NOT_outpor_ETC___d982,
IF_outport_encoder_67_BIT_3_68_THEN_NOT_outpor_ETC___d990,
IF_outport_encoder_67_BIT_3_68_THEN_outport_en_ETC___d1125,
IF_outport_encoder_67_BIT_3_68_THEN_outport_en_ETC___d1130,
IF_outport_encoder_67_BIT_3_68_THEN_outport_en_ETC___d1135,
IF_outport_encoder_67_BIT_3_68_THEN_outport_en_ETC___d1140,
IF_outport_encoder_67_BIT_3_68_THEN_outport_en_ETC___d1145,
fifo_out__h36476,
fifo_out__h37661,
fifo_out__h38207,
fifo_out__h38753,
fifo_out__h39299;
// actionvalue method in_ports_0_getNonFullVCs
assign in_ports_0_getNonFullVCs = flitBuffers$notFull ;
// actionvalue method in_ports_1_getNonFullVCs
assign in_ports_1_getNonFullVCs = flitBuffers_1$notFull ;
// actionvalue method in_ports_2_getNonFullVCs
assign in_ports_2_getNonFullVCs = flitBuffers_2$notFull ;
// actionvalue method in_ports_3_getNonFullVCs
assign in_ports_3_getNonFullVCs = flitBuffers_3$notFull ;
// actionvalue method in_ports_4_getNonFullVCs
assign in_ports_4_getNonFullVCs = flitBuffers_4$notFull ;
// actionvalue method out_ports_0_getFlit
assign out_ports_0_getFlit =
{ IF_outport_encoder_37_BIT_3_38_THEN_outport_en_ETC___d1046 &&
IF_IF_outport_encoder_37_BIT_3_38_THEN_NOT_out_ETC___d596,
IF_IF_outport_encoder_37_BIT_3_38_THEN_NOT_out_ETC___d1161 } ;
// actionvalue method out_ports_1_getFlit
assign out_ports_1_getFlit =
{ IF_outport_encoder_37_BIT_3_38_THEN_outport_en_ETC___d1056 &&
IF_IF_outport_encoder_37_BIT_3_38_THEN_IF_outp_ETC___d671,
IF_IF_outport_encoder_37_BIT_3_38_THEN_IF_outp_ETC___d1162 } ;
// actionvalue method out_ports_2_getFlit
assign out_ports_2_getFlit =
{ IF_outport_encoder_37_BIT_3_38_THEN_outport_en_ETC___d1058 &&
IF_IF_outport_encoder_37_BIT_3_38_THEN_IF_outp_ETC___d735,
IF_IF_outport_encoder_37_BIT_3_38_THEN_IF_outp_ETC___d1163 } ;
// actionvalue method out_ports_3_getFlit
assign out_ports_3_getFlit =
{ IF_outport_encoder_37_BIT_3_38_THEN_outport_en_ETC___d1060 &&
IF_IF_outport_encoder_37_BIT_3_38_THEN_IF_outp_ETC___d799,
IF_IF_outport_encoder_37_BIT_3_38_THEN_IF_outp_ETC___d1164 } ;
// actionvalue method out_ports_4_getFlit
assign out_ports_4_getFlit =
{ IF_outport_encoder_37_BIT_3_38_THEN_outport_en_ETC___d1062 &&
IF_IF_outport_encoder_37_BIT_3_38_THEN_IF_outp_ETC___d863,
IF_IF_outport_encoder_37_BIT_3_38_THEN_IF_outp_ETC___d1165 } ;
// submodule flitBuffers
mkInputVCQueues flitBuffers(.CLK(CLK),
.RST_N(RST_N),
.deq_fifo_out(flitBuffers$deq_fifo_out),
.enq_data_in(flitBuffers$enq_data_in),
.enq_fifo_in(flitBuffers$enq_fifo_in),
.EN_enq(flitBuffers$EN_enq),
.EN_deq(flitBuffers$EN_deq),
.deq(flitBuffers$deq),
.notEmpty(flitBuffers$notEmpty),
.notFull(flitBuffers$notFull));
// submodule flitBuffers_1
mkInputVCQueues flitBuffers_1(.CLK(CLK),
.RST_N(RST_N),
.deq_fifo_out(flitBuffers_1$deq_fifo_out),
.enq_data_in(flitBuffers_1$enq_data_in),
.enq_fifo_in(flitBuffers_1$enq_fifo_in),
.EN_enq(flitBuffers_1$EN_enq),
.EN_deq(flitBuffers_1$EN_deq),
.deq(flitBuffers_1$deq),
.notEmpty(flitBuffers_1$notEmpty),
.notFull(flitBuffers_1$notFull));
// submodule flitBuffers_2
mkInputVCQueues flitBuffers_2(.CLK(CLK),
.RST_N(RST_N),
.deq_fifo_out(flitBuffers_2$deq_fifo_out),
.enq_data_in(flitBuffers_2$enq_data_in),
.enq_fifo_in(flitBuffers_2$enq_fifo_in),
.EN_enq(flitBuffers_2$EN_enq),
.EN_deq(flitBuffers_2$EN_deq),
.deq(flitBuffers_2$deq),
.notEmpty(flitBuffers_2$notEmpty),
.notFull(flitBuffers_2$notFull));
// submodule flitBuffers_3
mkInputVCQueues flitBuffers_3(.CLK(CLK),
.RST_N(RST_N),
.deq_fifo_out(flitBuffers_3$deq_fifo_out),
.enq_data_in(flitBuffers_3$enq_data_in),
.enq_fifo_in(flitBuffers_3$enq_fifo_in),
.EN_enq(flitBuffers_3$EN_enq),
.EN_deq(flitBuffers_3$EN_deq),
.deq(flitBuffers_3$deq),
.notEmpty(flitBuffers_3$notEmpty),
.notFull(flitBuffers_3$notFull));
// submodule flitBuffers_4
mkInputVCQueues flitBuffers_4(.CLK(CLK),
.RST_N(RST_N),
.deq_fifo_out(flitBuffers_4$deq_fifo_out),
.enq_data_in(flitBuffers_4$enq_data_in),
.enq_fifo_in(flitBuffers_4$enq_fifo_in),
.EN_enq(flitBuffers_4$EN_enq),
.EN_deq(flitBuffers_4$EN_deq),
.deq(flitBuffers_4$deq),
.notEmpty(flitBuffers_4$notEmpty),
.notFull(flitBuffers_4$notFull));
// submodule outPortFIFOs_0
mkOutPortFIFO outPortFIFOs_0(.CLK(CLK),
.RST_N(RST_N),
.enq_sendData(outPortFIFOs_0$enq_sendData),
.EN_enq(outPortFIFOs_0$EN_enq),
.EN_deq(outPortFIFOs_0$EN_deq),
.EN_clear(outPortFIFOs_0$EN_clear),
.RDY_enq(),
.RDY_deq(),
.first(outPortFIFOs_0$first),
.RDY_first(),
.notFull(),
.RDY_notFull(),
.notEmpty(),
.RDY_notEmpty(),
.count(),
.RDY_count(),
.RDY_clear());
// submodule outPortFIFOs_0_1
mkOutPortFIFO outPortFIFOs_0_1(.CLK(CLK),
.RST_N(RST_N),
.enq_sendData(outPortFIFOs_0_1$enq_sendData),
.EN_enq(outPortFIFOs_0_1$EN_enq),
.EN_deq(outPortFIFOs_0_1$EN_deq),
.EN_clear(outPortFIFOs_0_1$EN_clear),
.RDY_enq(),
.RDY_deq(),
.first(outPortFIFOs_0_1$first),
.RDY_first(),
.notFull(),
.RDY_notFull(),
.notEmpty(),
.RDY_notEmpty(),
.count(),
.RDY_count(),
.RDY_clear());
// submodule outPortFIFOs_1
mkOutPortFIFO outPortFIFOs_1(.CLK(CLK),
.RST_N(RST_N),
.enq_sendData(outPortFIFOs_1$enq_sendData),
.EN_enq(outPortFIFOs_1$EN_enq),
.EN_deq(outPortFIFOs_1$EN_deq),
.EN_clear(outPortFIFOs_1$EN_clear),
.RDY_enq(),
.RDY_deq(),
.first(outPortFIFOs_1$first),
.RDY_first(),
.notFull(),
.RDY_notFull(),
.notEmpty(),
.RDY_notEmpty(),
.count(),
.RDY_count(),
.RDY_clear());
// submodule outPortFIFOs_1_1
mkOutPortFIFO outPortFIFOs_1_1(.CLK(CLK),
.RST_N(RST_N),
.enq_sendData(outPortFIFOs_1_1$enq_sendData),
.EN_enq(outPortFIFOs_1_1$EN_enq),
.EN_deq(outPortFIFOs_1_1$EN_deq),
.EN_clear(outPortFIFOs_1_1$EN_clear),
.RDY_enq(),
.RDY_deq(),
.first(outPortFIFOs_1_1$first),
.RDY_first(),
.notFull(),
.RDY_notFull(),
.notEmpty(),
.RDY_notEmpty(),
.count(),
.RDY_count(),
.RDY_clear());
// submodule outPortFIFOs_2
mkOutPortFIFO outPortFIFOs_2(.CLK(CLK),
.RST_N(RST_N),
.enq_sendData(outPortFIFOs_2$enq_sendData),
.EN_enq(outPortFIFOs_2$EN_enq),
.EN_deq(outPortFIFOs_2$EN_deq),
.EN_clear(outPortFIFOs_2$EN_clear),
.RDY_enq(),
.RDY_deq(),
.first(outPortFIFOs_2$first),
.RDY_first(),
.notFull(),
.RDY_notFull(),
.notEmpty(),
.RDY_notEmpty(),
.count(),
.RDY_count(),
.RDY_clear());
// submodule outPortFIFOs_2_1
mkOutPortFIFO outPortFIFOs_2_1(.CLK(CLK),
.RST_N(RST_N),
.enq_sendData(outPortFIFOs_2_1$enq_sendData),
.EN_enq(outPortFIFOs_2_1$EN_enq),
.EN_deq(outPortFIFOs_2_1$EN_deq),
.EN_clear(outPortFIFOs_2_1$EN_clear),
.RDY_enq(),
.RDY_deq(),
.first(outPortFIFOs_2_1$first),
.RDY_first(),
.notFull(),
.RDY_notFull(),
.notEmpty(),
.RDY_notEmpty(),
.count(),
.RDY_count(),
.RDY_clear());
// submodule outPortFIFOs_3
mkOutPortFIFO outPortFIFOs_3(.CLK(CLK),
.RST_N(RST_N),
.enq_sendData(outPortFIFOs_3$enq_sendData),
.EN_enq(outPortFIFOs_3$EN_enq),
.EN_deq(outPortFIFOs_3$EN_deq),
.EN_clear(outPortFIFOs_3$EN_clear),
.RDY_enq(),
.RDY_deq(),
.first(outPortFIFOs_3$first),
.RDY_first(),
.notFull(),
.RDY_notFull(),
.notEmpty(),
.RDY_notEmpty(),
.count(),
.RDY_count(),
.RDY_clear());
// submodule outPortFIFOs_3_1
mkOutPortFIFO outPortFIFOs_3_1(.CLK(CLK),
.RST_N(RST_N),
.enq_sendData(outPortFIFOs_3_1$enq_sendData),
.EN_enq(outPortFIFOs_3_1$EN_enq),
.EN_deq(outPortFIFOs_3_1$EN_deq),
.EN_clear(outPortFIFOs_3_1$EN_clear),
.RDY_enq(),
.RDY_deq(),
.first(outPortFIFOs_3_1$first),
.RDY_first(),
.notFull(),
.RDY_notFull(),
.notEmpty(),
.RDY_notEmpty(),
.count(),
.RDY_count(),
.RDY_clear());
// submodule outPortFIFOs_4
mkOutPortFIFO outPortFIFOs_4(.CLK(CLK),
.RST_N(RST_N),
.enq_sendData(outPortFIFOs_4$enq_sendData),
.EN_enq(outPortFIFOs_4$EN_enq),
.EN_deq(outPortFIFOs_4$EN_deq),
.EN_clear(outPortFIFOs_4$EN_clear),
.RDY_enq(),
.RDY_deq(),
.first(outPortFIFOs_4$first),
.RDY_first(),
.notFull(),
.RDY_notFull(),
.notEmpty(),
.RDY_notEmpty(),
.count(),
.RDY_count(),
.RDY_clear());
// submodule outPortFIFOs_4_1
mkOutPortFIFO outPortFIFOs_4_1(.CLK(CLK),
.RST_N(RST_N),
.enq_sendData(outPortFIFOs_4_1$enq_sendData),
.EN_enq(outPortFIFOs_4_1$EN_enq),
.EN_deq(outPortFIFOs_4_1$EN_deq),
.EN_clear(outPortFIFOs_4_1$EN_clear),
.RDY_enq(),
.RDY_deq(),
.first(outPortFIFOs_4_1$first),
.RDY_first(),
.notFull(),
.RDY_notFull(),
.notEmpty(),
.RDY_notEmpty(),
.count(),
.RDY_count(),
.RDY_clear());
// submodule routerAlloc
mkSepRouterAllocator routerAlloc(.pipeline(1'd0),
.CLK(CLK),
.RST_N(RST_N),
.allocate_alloc_input(routerAlloc$allocate_alloc_input),
.EN_allocate(routerAlloc$EN_allocate),
.EN_next(routerAlloc$EN_next),
.allocate(routerAlloc$allocate));
// inlined wires
assign hasFlitsToSend_perIn$wget = { 1'd1, flitBuffers$deq } ;
assign hasFlitsToSend_perIn_1$wget = { 1'd1, flitBuffers_1$deq } ;
assign hasFlitsToSend_perIn_2$wget = { 1'd1, flitBuffers_2$deq } ;
assign hasFlitsToSend_perIn_3$wget = { 1'd1, flitBuffers_3$deq } ;
assign hasFlitsToSend_perIn_4$wget = { 1'd1, flitBuffers_4$deq } ;
// register activeVC_perIn_reg
assign activeVC_perIn_reg$D_IN = 2'h0 ;
assign activeVC_perIn_reg$EN = 1'b0 ;
// register activeVC_perIn_reg_1
assign activeVC_perIn_reg_1$D_IN = 2'h0 ;
assign activeVC_perIn_reg_1$EN = 1'b0 ;
// register activeVC_perIn_reg_2
assign activeVC_perIn_reg_2$D_IN = 2'h0 ;
assign activeVC_perIn_reg_2$EN = 1'b0 ;
// register activeVC_perIn_reg_3
assign activeVC_perIn_reg_3$D_IN = 2'h0 ;
assign activeVC_perIn_reg_3$EN = 1'b0 ;
// register activeVC_perIn_reg_4
assign activeVC_perIn_reg_4$D_IN = 2'h0 ;
assign activeVC_perIn_reg_4$EN = 1'b0 ;
// register inPortVL_0
assign inPortVL_0$D_IN = 3'h0 ;
assign inPortVL_0$EN = 1'b0 ;
// register inPortVL_0_1
assign inPortVL_0_1$D_IN = 3'h0 ;
assign inPortVL_0_1$EN = 1'b0 ;
// register inPortVL_1
assign inPortVL_1$D_IN = 3'h0 ;
assign inPortVL_1$EN = 1'b0 ;
// register inPortVL_1_1
assign inPortVL_1_1$D_IN = 3'h0 ;
assign inPortVL_1_1$EN = 1'b0 ;
// register inPortVL_2
assign inPortVL_2$D_IN = 3'h0 ;
assign inPortVL_2$EN = 1'b0 ;
// register inPortVL_2_1
assign inPortVL_2_1$D_IN = 3'h0 ;
assign inPortVL_2_1$EN = 1'b0 ;
// register inPortVL_3
assign inPortVL_3$D_IN = 3'h0 ;
assign inPortVL_3$EN = 1'b0 ;
// register inPortVL_3_1
assign inPortVL_3_1$D_IN = 3'h0 ;
assign inPortVL_3_1$EN = 1'b0 ;
// register inPortVL_4
assign inPortVL_4$D_IN = 3'h0 ;
assign inPortVL_4$EN = 1'b0 ;
// register inPortVL_4_1
assign inPortVL_4_1$D_IN = 3'h0 ;
assign inPortVL_4_1$EN = 1'b0 ;
// register lockedVL_0
assign lockedVL_0$D_IN = 1'b0 ;
assign lockedVL_0$EN = 1'b0 ;
// register lockedVL_0_1
assign lockedVL_0_1$D_IN = 1'b0 ;
assign lockedVL_0_1$EN = 1'b0 ;
// register lockedVL_1
assign lockedVL_1$D_IN = 1'b0 ;
assign lockedVL_1$EN = 1'b0 ;
// register lockedVL_1_1
assign lockedVL_1_1$D_IN = 1'b0 ;
assign lockedVL_1_1$EN = 1'b0 ;
// register lockedVL_2
assign lockedVL_2$D_IN = 1'b0 ;
assign lockedVL_2$EN = 1'b0 ;
// register lockedVL_2_1
assign lockedVL_2_1$D_IN = 1'b0 ;
assign lockedVL_2_1$EN = 1'b0 ;
// register lockedVL_3
assign lockedVL_3$D_IN = 1'b0 ;
assign lockedVL_3$EN = 1'b0 ;
// register lockedVL_3_1
assign lockedVL_3_1$D_IN = 1'b0 ;
assign lockedVL_3_1$EN = 1'b0 ;
// register lockedVL_4
assign lockedVL_4$D_IN = 1'b0 ;
assign lockedVL_4$EN = 1'b0 ;
// register lockedVL_4_1
assign lockedVL_4_1$D_IN = 1'b0 ;
assign lockedVL_4_1$EN = 1'b0 ;
// register selectedIO_reg_0
assign selectedIO_reg_0$D_IN = 1'b0 ;
assign selectedIO_reg_0$EN = 1'b0 ;
// register selectedIO_reg_0_1
assign selectedIO_reg_0_1$D_IN = 1'b0 ;
assign selectedIO_reg_0_1$EN = 1'b0 ;
// register selectedIO_reg_0_2
assign selectedIO_reg_0_2$D_IN = 1'b0 ;
assign selectedIO_reg_0_2$EN = 1'b0 ;
// register selectedIO_reg_0_3
assign selectedIO_reg_0_3$D_IN = 1'b0 ;
assign selectedIO_reg_0_3$EN = 1'b0 ;
// register selectedIO_reg_0_4
assign selectedIO_reg_0_4$D_IN = 1'b0 ;
assign selectedIO_reg_0_4$EN = 1'b0 ;
// register selectedIO_reg_1
assign selectedIO_reg_1$D_IN = 1'b0 ;
assign selectedIO_reg_1$EN = 1'b0 ;
// register selectedIO_reg_1_1
assign selectedIO_reg_1_1$D_IN = 1'b0 ;
assign selectedIO_reg_1_1$EN = 1'b0 ;
// register selectedIO_reg_1_2
assign selectedIO_reg_1_2$D_IN = 1'b0 ;
assign selectedIO_reg_1_2$EN = 1'b0 ;
// register selectedIO_reg_1_3
assign selectedIO_reg_1_3$D_IN = 1'b0 ;
assign selectedIO_reg_1_3$EN = 1'b0 ;
// register selectedIO_reg_1_4
assign selectedIO_reg_1_4$D_IN = 1'b0 ;
assign selectedIO_reg_1_4$EN = 1'b0 ;
// register selectedIO_reg_2
assign selectedIO_reg_2$D_IN = 1'b0 ;
assign selectedIO_reg_2$EN = 1'b0 ;
// register selectedIO_reg_2_1
assign selectedIO_reg_2_1$D_IN = 1'b0 ;
assign selectedIO_reg_2_1$EN = 1'b0 ;
// register selectedIO_reg_2_2
assign selectedIO_reg_2_2$D_IN = 1'b0 ;
assign selectedIO_reg_2_2$EN = 1'b0 ;
// register selectedIO_reg_2_3
assign selectedIO_reg_2_3$D_IN = 1'b0 ;
assign selectedIO_reg_2_3$EN = 1'b0 ;
// register selectedIO_reg_2_4
assign selectedIO_reg_2_4$D_IN = 1'b0 ;
assign selectedIO_reg_2_4$EN = 1'b0 ;
// register selectedIO_reg_3
assign selectedIO_reg_3$D_IN = 1'b0 ;
assign selectedIO_reg_3$EN = 1'b0 ;
// register selectedIO_reg_3_1
assign selectedIO_reg_3_1$D_IN = 1'b0 ;
assign selectedIO_reg_3_1$EN = 1'b0 ;
// register selectedIO_reg_3_2
assign selectedIO_reg_3_2$D_IN = 1'b0 ;
assign selectedIO_reg_3_2$EN = 1'b0 ;
// register selectedIO_reg_3_3
assign selectedIO_reg_3_3$D_IN = 1'b0 ;
assign selectedIO_reg_3_3$EN = 1'b0 ;
// register selectedIO_reg_3_4
assign selectedIO_reg_3_4$D_IN = 1'b0 ;
assign selectedIO_reg_3_4$EN = 1'b0 ;
// register selectedIO_reg_4
assign selectedIO_reg_4$D_IN = 1'b0 ;
assign selectedIO_reg_4$EN = 1'b0 ;
// register selectedIO_reg_4_1
assign selectedIO_reg_4_1$D_IN = 1'b0 ;
assign selectedIO_reg_4_1$EN = 1'b0 ;
// register selectedIO_reg_4_2
assign selectedIO_reg_4_2$D_IN = 1'b0 ;
assign selectedIO_reg_4_2$EN = 1'b0 ;
// register selectedIO_reg_4_3
assign selectedIO_reg_4_3$D_IN = 1'b0 ;
assign selectedIO_reg_4_3$EN = 1'b0 ;
// register selectedIO_reg_4_4
assign selectedIO_reg_4_4$D_IN = 1'b0 ;
assign selectedIO_reg_4_4$EN = 1'b0 ;
// submodule flitBuffers
assign flitBuffers$deq_fifo_out = fifo_out__h36476 ;
assign flitBuffers$enq_data_in = in_ports_0_putRoutedFlit_flit_in[72:3] ;
assign flitBuffers$enq_fifo_in = in_ports_0_putRoutedFlit_flit_in[67] ;
assign flitBuffers$EN_enq =
EN_in_ports_0_putRoutedFlit &&
in_ports_0_putRoutedFlit_flit_in[73] ;
assign flitBuffers$EN_deq = outport_encoder___d1117[3] ;
// submodule flitBuffers_1
assign flitBuffers_1$deq_fifo_out = fifo_out__h37661 ;
assign flitBuffers_1$enq_data_in = in_ports_1_putRoutedFlit_flit_in[72:3] ;
assign flitBuffers_1$enq_fifo_in = in_ports_1_putRoutedFlit_flit_in[67] ;
assign flitBuffers_1$EN_enq =
EN_in_ports_1_putRoutedFlit &&
in_ports_1_putRoutedFlit_flit_in[73] ;
assign flitBuffers_1$EN_deq = outport_encoder___d1116[3] ;
// submodule flitBuffers_2
assign flitBuffers_2$deq_fifo_out = fifo_out__h38207 ;
assign flitBuffers_2$enq_data_in = in_ports_2_putRoutedFlit_flit_in[72:3] ;
assign flitBuffers_2$enq_fifo_in = in_ports_2_putRoutedFlit_flit_in[67] ;
assign flitBuffers_2$EN_enq =
EN_in_ports_2_putRoutedFlit &&
in_ports_2_putRoutedFlit_flit_in[73] ;
assign flitBuffers_2$EN_deq = outport_encoder___d1115[3] ;
// submodule flitBuffers_3
assign flitBuffers_3$deq_fifo_out = fifo_out__h38753 ;
assign flitBuffers_3$enq_data_in = in_ports_3_putRoutedFlit_flit_in[72:3] ;
assign flitBuffers_3$enq_fifo_in = in_ports_3_putRoutedFlit_flit_in[67] ;
assign flitBuffers_3$EN_enq =
EN_in_ports_3_putRoutedFlit &&
in_ports_3_putRoutedFlit_flit_in[73] ;
assign flitBuffers_3$EN_deq = outport_encoder___d1114[3] ;
// submodule flitBuffers_4
assign flitBuffers_4$deq_fifo_out = fifo_out__h39299 ;
assign flitBuffers_4$enq_data_in = in_ports_4_putRoutedFlit_flit_in[72:3] ;
assign flitBuffers_4$enq_fifo_in = in_ports_4_putRoutedFlit_flit_in[67] ;
assign flitBuffers_4$EN_enq =
EN_in_ports_4_putRoutedFlit &&
in_ports_4_putRoutedFlit_flit_in[73] ;
assign flitBuffers_4$EN_deq = outport_encoder___d1113[3] ;
// submodule outPortFIFOs_0
assign outPortFIFOs_0$enq_sendData = in_ports_0_putRoutedFlit_flit_in[2:0] ;
assign outPortFIFOs_0$EN_enq =
EN_in_ports_0_putRoutedFlit &&
in_ports_0_putRoutedFlit_flit_in[73] &&
!in_ports_0_putRoutedFlit_flit_in[67] ;
assign outPortFIFOs_0$EN_deq =
outport_encoder___d1117[3] && flitBuffers$notEmpty[0] &&
IF_outPortFIFOs_0_first__98_EQ_0_99_THEN_simpl_ETC___d952 ;
assign outPortFIFOs_0$EN_clear = 1'b0 ;
// submodule outPortFIFOs_0_1
assign outPortFIFOs_0_1$enq_sendData =
in_ports_0_putRoutedFlit_flit_in[2:0] ;
assign outPortFIFOs_0_1$EN_enq =
EN_in_ports_0_putRoutedFlit &&
in_ports_0_putRoutedFlit_flit_in[73] &&
in_ports_0_putRoutedFlit_flit_in[67] ;
assign outPortFIFOs_0_1$EN_deq =
outport_encoder___d1117[3] && fifo_out__h36476 ;
assign outPortFIFOs_0_1$EN_clear = 1'b0 ;
// submodule outPortFIFOs_1
assign outPortFIFOs_1$enq_sendData = in_ports_1_putRoutedFlit_flit_in[2:0] ;
assign outPortFIFOs_1$EN_enq =
EN_in_ports_1_putRoutedFlit &&
in_ports_1_putRoutedFlit_flit_in[73] &&
!in_ports_1_putRoutedFlit_flit_in[67] ;
assign outPortFIFOs_1$EN_deq =
outport_encoder___d1116[3] && flitBuffers_1$notEmpty[0] &&
IF_outPortFIFOs_1_first__57_EQ_0_58_THEN_simpl_ETC___d950 ;
assign outPortFIFOs_1$EN_clear = 1'b0 ;
// submodule outPortFIFOs_1_1
assign outPortFIFOs_1_1$enq_sendData =
in_ports_1_putRoutedFlit_flit_in[2:0] ;
assign outPortFIFOs_1_1$EN_enq =
EN_in_ports_1_putRoutedFlit &&
in_ports_1_putRoutedFlit_flit_in[73] &&
in_ports_1_putRoutedFlit_flit_in[67] ;
assign outPortFIFOs_1_1$EN_deq =
outport_encoder___d1116[3] && fifo_out__h37661 ;
assign outPortFIFOs_1_1$EN_clear = 1'b0 ;
// submodule outPortFIFOs_2
assign outPortFIFOs_2$enq_sendData = in_ports_2_putRoutedFlit_flit_in[2:0] ;
assign outPortFIFOs_2$EN_enq =
EN_in_ports_2_putRoutedFlit &&
in_ports_2_putRoutedFlit_flit_in[73] &&
!in_ports_2_putRoutedFlit_flit_in[67] ;
assign outPortFIFOs_2$EN_deq =
outport_encoder___d1115[3] && flitBuffers_2$notEmpty[0] &&
IF_outPortFIFOs_2_first__15_EQ_0_16_THEN_simpl_ETC___d948 ;
assign outPortFIFOs_2$EN_clear = 1'b0 ;
// submodule outPortFIFOs_2_1
assign outPortFIFOs_2_1$enq_sendData =
in_ports_2_putRoutedFlit_flit_in[2:0] ;
assign outPortFIFOs_2_1$EN_enq =
EN_in_ports_2_putRoutedFlit &&
in_ports_2_putRoutedFlit_flit_in[73] &&
in_ports_2_putRoutedFlit_flit_in[67] ;
assign outPortFIFOs_2_1$EN_deq =
outport_encoder___d1115[3] && fifo_out__h38207 ;
assign outPortFIFOs_2_1$EN_clear = 1'b0 ;
// submodule outPortFIFOs_3
assign outPortFIFOs_3$enq_sendData = in_ports_3_putRoutedFlit_flit_in[2:0] ;
assign outPortFIFOs_3$EN_enq =
EN_in_ports_3_putRoutedFlit &&
in_ports_3_putRoutedFlit_flit_in[73] &&
!in_ports_3_putRoutedFlit_flit_in[67] ;
assign outPortFIFOs_3$EN_deq =
outport_encoder___d1114[3] && flitBuffers_3$notEmpty[0] &&
IF_outPortFIFOs_3_first__4_EQ_0_5_THEN_simple__ETC___d946 ;
assign outPortFIFOs_3$EN_clear = 1'b0 ;
// submodule outPortFIFOs_3_1
assign outPortFIFOs_3_1$enq_sendData =
in_ports_3_putRoutedFlit_flit_in[2:0] ;
assign outPortFIFOs_3_1$EN_enq =
EN_in_ports_3_putRoutedFlit &&
in_ports_3_putRoutedFlit_flit_in[73] &&
in_ports_3_putRoutedFlit_flit_in[67] ;
assign outPortFIFOs_3_1$EN_deq =
outport_encoder___d1114[3] && fifo_out__h38753 ;
assign outPortFIFOs_3_1$EN_clear = 1'b0 ;
// submodule outPortFIFOs_4
assign outPortFIFOs_4$enq_sendData = in_ports_4_putRoutedFlit_flit_in[2:0] ;
assign outPortFIFOs_4$EN_enq =
EN_in_ports_4_putRoutedFlit &&
in_ports_4_putRoutedFlit_flit_in[73] &&
!in_ports_4_putRoutedFlit_flit_in[67] ;
assign outPortFIFOs_4$EN_deq =
outport_encoder___d1113[3] && flitBuffers_4$notEmpty[0] &&
IF_outPortFIFOs_4_first_EQ_0_THEN_simple_credi_ETC___d944 ;
assign outPortFIFOs_4$EN_clear = 1'b0 ;
// submodule outPortFIFOs_4_1
assign outPortFIFOs_4_1$enq_sendData =
in_ports_4_putRoutedFlit_flit_in[2:0] ;
assign outPortFIFOs_4_1$EN_enq =
EN_in_ports_4_putRoutedFlit &&
in_ports_4_putRoutedFlit_flit_in[73] &&
in_ports_4_putRoutedFlit_flit_in[67] ;
assign outPortFIFOs_4_1$EN_deq =
outport_encoder___d1113[3] && fifo_out__h39299 ;
assign outPortFIFOs_4_1$EN_clear = 1'b0 ;
// submodule routerAlloc
assign routerAlloc$allocate_alloc_input =
{ IF_flitBuffers_4_notEmpty_BIT_0_THEN_IF_IF_out_ETC___d71,
IF_flitBuffers_3_notEmpty__2_BIT_0_3_THEN_IF_I_ETC___d112,
IF_flitBuffers_2_notEmpty__13_BIT_0_14_THEN_IF_ETC___d153,
IF_flitBuffers_1_notEmpty__55_BIT_0_56_THEN_IF_ETC___d195,
IF_flitBuffers_notEmpty__96_BIT_0_97_THEN_IF_I_ETC___d236 } ;
assign routerAlloc$EN_allocate = 1'd1 ;
assign routerAlloc$EN_next = 1'd1 ;
// remaining internal signals
module_outport_encoder instance_outport_encoder_1(.outport_encoder_vec({ { 1'd1 &&
routerAlloc$allocate[4],
1'd1 &&
routerAlloc$allocate[3],
1'd1 &&
routerAlloc$allocate[2] },
1'd1 &&
routerAlloc$allocate[1],
1'd1 &&
routerAlloc$allocate[0] }),
.outport_encoder(outport_encoder___d1117));
module_outport_encoder instance_outport_encoder_0(.outport_encoder_vec({ { 1'd1 &&
routerAlloc$allocate[9],
1'd1 &&
routerAlloc$allocate[8],
1'd1 &&
routerAlloc$allocate[7] },
1'd1 &&
routerAlloc$allocate[6],
1'd1 &&
routerAlloc$allocate[5] }),
.outport_encoder(outport_encoder___d1116));
module_outport_encoder instance_outport_encoder_2(.outport_encoder_vec({ { 1'd1 &&
routerAlloc$allocate[14],
1'd1 &&
routerAlloc$allocate[13],
1'd1 &&
routerAlloc$allocate[12] },
1'd1 &&
routerAlloc$allocate[11],
1'd1 &&
routerAlloc$allocate[10] }),
.outport_encoder(outport_encoder___d1115));
module_outport_encoder instance_outport_encoder_4(.outport_encoder_vec({ { 1'd1 &&
routerAlloc$allocate[24],
1'd1 &&
routerAlloc$allocate[23],
1'd1 &&
routerAlloc$allocate[22] },
1'd1 &&
routerAlloc$allocate[21],
1'd1 &&
routerAlloc$allocate[20] }),
.outport_encoder(outport_encoder___d1113));
module_outport_encoder instance_outport_encoder_3(.outport_encoder_vec({ { 1'd1 &&
routerAlloc$allocate[19],
1'd1 &&
routerAlloc$allocate[18],
1'd1 &&
routerAlloc$allocate[17] },
1'd1 &&
routerAlloc$allocate[16],
1'd1 &&
routerAlloc$allocate[15] }),
.outport_encoder(outport_encoder___d1114));
assign IF_IF_outPortFIFOs_0_first__98_EQ_0_99_THEN_si_ETC___d235 =
IF_outPortFIFOs_0_first__98_EQ_0_99_THEN_simpl_ETC___d952 ?
{ outPortFIFOs_0$first == 3'd4,
outPortFIFOs_0$first == 3'd3,
outPortFIFOs_0$first == 3'd2,
outPortFIFOs_0$first == 3'd1,
outPortFIFOs_0$first == 3'd0 } :
{ flitBuffers$notEmpty[1] &&
IF_outPortFIFOs_0_1_first__12_EQ_0_13_THEN_sim_ETC___d1033 &&
outPortFIFOs_0_1$first == 3'd4,
flitBuffers$notEmpty[1] &&
IF_outPortFIFOs_0_1_first__12_EQ_0_13_THEN_sim_ETC___d1033 &&
outPortFIFOs_0_1$first == 3'd3,
flitBuffers$notEmpty[1] &&
IF_outPortFIFOs_0_1_first__12_EQ_0_13_THEN_sim_ETC___d1033 &&
outPortFIFOs_0_1$first == 3'd2,
flitBuffers$notEmpty[1] &&
IF_outPortFIFOs_0_1_first__12_EQ_0_13_THEN_sim_ETC___d1033 &&
outPortFIFOs_0_1$first == 3'd1,
flitBuffers$notEmpty[1] &&
IF_outPortFIFOs_0_1_first__12_EQ_0_13_THEN_sim_ETC___d1033 &&
outPortFIFOs_0_1$first == 3'd0 } ;
assign IF_IF_outPortFIFOs_1_first__57_EQ_0_58_THEN_si_ETC___d194 =
IF_outPortFIFOs_1_first__57_EQ_0_58_THEN_simpl_ETC___d950 ?
{ outPortFIFOs_1$first == 3'd4,
outPortFIFOs_1$first == 3'd3,
outPortFIFOs_1$first == 3'd2,
outPortFIFOs_1$first == 3'd1,
outPortFIFOs_1$first == 3'd0 } :
{ flitBuffers_1$notEmpty[1] &&
IF_outPortFIFOs_1_1_first__71_EQ_0_72_THEN_sim_ETC___d1026 &&
outPortFIFOs_1_1$first == 3'd4,
flitBuffers_1$notEmpty[1] &&
IF_outPortFIFOs_1_1_first__71_EQ_0_72_THEN_sim_ETC___d1026 &&
outPortFIFOs_1_1$first == 3'd3,
flitBuffers_1$notEmpty[1] &&
IF_outPortFIFOs_1_1_first__71_EQ_0_72_THEN_sim_ETC___d1026 &&
outPortFIFOs_1_1$first == 3'd2,
flitBuffers_1$notEmpty[1] &&
IF_outPortFIFOs_1_1_first__71_EQ_0_72_THEN_sim_ETC___d1026 &&
outPortFIFOs_1_1$first == 3'd1,
flitBuffers_1$notEmpty[1] &&
IF_outPortFIFOs_1_1_first__71_EQ_0_72_THEN_sim_ETC___d1026 &&
outPortFIFOs_1_1$first == 3'd0 } ;
assign IF_IF_outPortFIFOs_2_first__15_EQ_0_16_THEN_si_ETC___d152 =
IF_outPortFIFOs_2_first__15_EQ_0_16_THEN_simpl_ETC___d948 ?
{ outPortFIFOs_2$first == 3'd4,
outPortFIFOs_2$first == 3'd3,
outPortFIFOs_2$first == 3'd2,
outPortFIFOs_2$first == 3'd1,
outPortFIFOs_2$first == 3'd0 } :
{ flitBuffers_2$notEmpty[1] &&
IF_outPortFIFOs_2_1_first__29_EQ_0_30_THEN_sim_ETC___d1019 &&
outPortFIFOs_2_1$first == 3'd4,
flitBuffers_2$notEmpty[1] &&
IF_outPortFIFOs_2_1_first__29_EQ_0_30_THEN_sim_ETC___d1019 &&
outPortFIFOs_2_1$first == 3'd3,
flitBuffers_2$notEmpty[1] &&
IF_outPortFIFOs_2_1_first__29_EQ_0_30_THEN_sim_ETC___d1019 &&
outPortFIFOs_2_1$first == 3'd2,
flitBuffers_2$notEmpty[1] &&
IF_outPortFIFOs_2_1_first__29_EQ_0_30_THEN_sim_ETC___d1019 &&
outPortFIFOs_2_1$first == 3'd1,
flitBuffers_2$notEmpty[1] &&
IF_outPortFIFOs_2_1_first__29_EQ_0_30_THEN_sim_ETC___d1019 &&
outPortFIFOs_2_1$first == 3'd0 } ;
assign IF_IF_outPortFIFOs_3_first__4_EQ_0_5_THEN_simp_ETC___d111 =
IF_outPortFIFOs_3_first__4_EQ_0_5_THEN_simple__ETC___d946 ?
{ outPortFIFOs_3$first == 3'd4,
outPortFIFOs_3$first == 3'd3,
outPortFIFOs_3$first == 3'd2,
outPortFIFOs_3$first == 3'd1,
outPortFIFOs_3$first == 3'd0 } :
{ flitBuffers_3$notEmpty[1] &&
IF_outPortFIFOs_3_1_first__8_EQ_0_9_THEN_simpl_ETC___d1013 &&
outPortFIFOs_3_1$first == 3'd4,
flitBuffers_3$notEmpty[1] &&
IF_outPortFIFOs_3_1_first__8_EQ_0_9_THEN_simpl_ETC___d1013 &&
outPortFIFOs_3_1$first == 3'd3,
flitBuffers_3$notEmpty[1] &&
IF_outPortFIFOs_3_1_first__8_EQ_0_9_THEN_simpl_ETC___d1013 &&
outPortFIFOs_3_1$first == 3'd2,
flitBuffers_3$notEmpty[1] &&
IF_outPortFIFOs_3_1_first__8_EQ_0_9_THEN_simpl_ETC___d1013 &&
outPortFIFOs_3_1$first == 3'd1,
flitBuffers_3$notEmpty[1] &&
IF_outPortFIFOs_3_1_first__8_EQ_0_9_THEN_simpl_ETC___d1013 &&
outPortFIFOs_3_1$first == 3'd0 } ;
assign IF_IF_outPortFIFOs_4_first_EQ_0_THEN_simple_cr_ETC___d70 =
IF_outPortFIFOs_4_first_EQ_0_THEN_simple_credi_ETC___d944 ?
{ outPortFIFOs_4$first == 3'd4,
outPortFIFOs_4$first == 3'd3,
outPortFIFOs_4$first == 3'd2,
outPortFIFOs_4$first == 3'd1,
outPortFIFOs_4$first == 3'd0 } :
{ flitBuffers_4$notEmpty[1] &&
IF_outPortFIFOs_4_1_first__2_EQ_0_3_THEN_simpl_ETC___d1007 &&
outPortFIFOs_4_1$first == 3'd4,
flitBuffers_4$notEmpty[1] &&
IF_outPortFIFOs_4_1_first__2_EQ_0_3_THEN_simpl_ETC___d1007 &&
outPortFIFOs_4_1$first == 3'd3,
flitBuffers_4$notEmpty[1] &&
IF_outPortFIFOs_4_1_first__2_EQ_0_3_THEN_simpl_ETC___d1007 &&
outPortFIFOs_4_1$first == 3'd2,
flitBuffers_4$notEmpty[1] &&
IF_outPortFIFOs_4_1_first__2_EQ_0_3_THEN_simpl_ETC___d1007 &&
outPortFIFOs_4_1$first == 3'd1,
flitBuffers_4$notEmpty[1] &&
IF_outPortFIFOs_4_1_first__2_EQ_0_3_THEN_simpl_ETC___d1007 &&
outPortFIFOs_4_1$first == 3'd0 } ;
assign IF_IF_outport_encoder_37_BIT_3_38_THEN_NOT_out_ETC___d1161 =
IF_outport_encoder_37_BIT_3_38_THEN_NOT_outpor_ETC___d1047 ?
hasFlitsToSend_perIn$wget[69:0] :
(IF_outport_encoder_37_BIT_3_38_THEN_NOT_outpor_ETC___d1089 ?
hasFlitsToSend_perIn_1$wget[69:0] :
IF_IF_outport_encoder_37_BIT_3_38_THEN_NOT_out_ETC___d612) ;
assign IF_IF_outport_encoder_37_BIT_3_38_THEN_NOT_out_ETC___d1171 =
IF_outport_encoder_37_BIT_3_38_THEN_NOT_outpor_ETC___d1047 ?
!outport_encoder___d1117[3] || !hasFlitsToSend_perIn$wget[70] :
IF_IF_outport_encoder_37_BIT_3_38_THEN_NOT_out_ETC___d582 ;
assign IF_IF_outport_encoder_37_BIT_3_38_THEN_NOT_out_ETC___d580 =
IF_outport_encoder_37_BIT_3_38_THEN_NOT_outpor_ETC___d1091 ?
!outport_encoder___d1114[3] ||
!hasFlitsToSend_perIn_3$wget[70] :
outport_encoder___d1113[3] &&
outport_encoder___d1113[2:0] == 3'd0 &&
!hasFlitsToSend_perIn_4$wget[70] ;
assign IF_IF_outport_encoder_37_BIT_3_38_THEN_NOT_out_ETC___d581 =
IF_outport_encoder_37_BIT_3_38_THEN_NOT_outpor_ETC___d1090 ?
!outport_encoder___d1115[3] ||
!hasFlitsToSend_perIn_2$wget[70] :
IF_IF_outport_encoder_37_BIT_3_38_THEN_NOT_out_ETC___d580 ;
assign IF_IF_outport_encoder_37_BIT_3_38_THEN_NOT_out_ETC___d582 =
IF_outport_encoder_37_BIT_3_38_THEN_NOT_outpor_ETC___d1089 ?
!outport_encoder___d1116[3] ||
!hasFlitsToSend_perIn_1$wget[70] :
IF_IF_outport_encoder_37_BIT_3_38_THEN_NOT_out_ETC___d581 ;
assign IF_IF_outport_encoder_37_BIT_3_38_THEN_NOT_out_ETC___d593 =
IF_outport_encoder_37_BIT_3_38_THEN_NOT_outpor_ETC___d1091 ?
outport_encoder___d1114[3] && hasFlitsToSend_perIn_3$wget[70] :
!outport_encoder___d1113[3] ||
outport_encoder___d1113[2:0] != 3'd0 ||
hasFlitsToSend_perIn_4$wget[70] ;
assign IF_IF_outport_encoder_37_BIT_3_38_THEN_NOT_out_ETC___d594 =
IF_outport_encoder_37_BIT_3_38_THEN_NOT_outpor_ETC___d1090 ?
outport_encoder___d1115[3] && hasFlitsToSend_perIn_2$wget[70] :
IF_IF_outport_encoder_37_BIT_3_38_THEN_NOT_out_ETC___d593 ;
assign IF_IF_outport_encoder_37_BIT_3_38_THEN_NOT_out_ETC___d595 =
IF_outport_encoder_37_BIT_3_38_THEN_NOT_outpor_ETC___d1089 ?
outport_encoder___d1116[3] && hasFlitsToSend_perIn_1$wget[70] :
IF_IF_outport_encoder_37_BIT_3_38_THEN_NOT_out_ETC___d594 ;
assign IF_IF_outport_encoder_37_BIT_3_38_THEN_NOT_out_ETC___d596 =
IF_outport_encoder_37_BIT_3_38_THEN_NOT_outpor_ETC___d1047 ?
outport_encoder___d1117[3] && hasFlitsToSend_perIn$wget[70] :
IF_IF_outport_encoder_37_BIT_3_38_THEN_NOT_out_ETC___d595 ;
assign IF_IF_outport_encoder_37_BIT_3_38_THEN_NOT_out_ETC___d612 =
IF_outport_encoder_37_BIT_3_38_THEN_NOT_outpor_ETC___d1090 ?
hasFlitsToSend_perIn_2$wget[69:0] :
(IF_outport_encoder_37_BIT_3_38_THEN_NOT_outpor_ETC___d1091 ?
hasFlitsToSend_perIn_3$wget[69:0] :
hasFlitsToSend_perIn_4$wget[69:0]) ;
assign IF_flitBuffers_1_notEmpty__55_BIT_0_56_THEN_IF_ETC___d195 =
flitBuffers_1$notEmpty[0] ?
IF_IF_outPortFIFOs_1_first__57_EQ_0_58_THEN_si_ETC___d194 :
{ flitBuffers_1$notEmpty[1] &&
IF_outPortFIFOs_1_1_first__71_EQ_0_72_THEN_sim_ETC___d1026 &&
outPortFIFOs_1_1$first == 3'd4,
flitBuffers_1$notEmpty[1] &&
IF_outPortFIFOs_1_1_first__71_EQ_0_72_THEN_sim_ETC___d1026 &&
outPortFIFOs_1_1$first == 3'd3,
flitBuffers_1$notEmpty[1] &&
IF_outPortFIFOs_1_1_first__71_EQ_0_72_THEN_sim_ETC___d1026 &&
outPortFIFOs_1_1$first == 3'd2,
flitBuffers_1$notEmpty[1] &&
IF_outPortFIFOs_1_1_first__71_EQ_0_72_THEN_sim_ETC___d1026 &&
outPortFIFOs_1_1$first == 3'd1,
flitBuffers_1$notEmpty[1] &&
IF_outPortFIFOs_1_1_first__71_EQ_0_72_THEN_sim_ETC___d1026 &&
outPortFIFOs_1_1$first == 3'd0 } ;
assign IF_flitBuffers_2_notEmpty__13_BIT_0_14_THEN_IF_ETC___d153 =
flitBuffers_2$notEmpty[0] ?
IF_IF_outPortFIFOs_2_first__15_EQ_0_16_THEN_si_ETC___d152 :
{ flitBuffers_2$notEmpty[1] &&
IF_outPortFIFOs_2_1_first__29_EQ_0_30_THEN_sim_ETC___d1019 &&
outPortFIFOs_2_1$first == 3'd4,
flitBuffers_2$notEmpty[1] &&
IF_outPortFIFOs_2_1_first__29_EQ_0_30_THEN_sim_ETC___d1019 &&
outPortFIFOs_2_1$first == 3'd3,
flitBuffers_2$notEmpty[1] &&
IF_outPortFIFOs_2_1_first__29_EQ_0_30_THEN_sim_ETC___d1019 &&
outPortFIFOs_2_1$first == 3'd2,
flitBuffers_2$notEmpty[1] &&
IF_outPortFIFOs_2_1_first__29_EQ_0_30_THEN_sim_ETC___d1019 &&
outPortFIFOs_2_1$first == 3'd1,
flitBuffers_2$notEmpty[1] &&
IF_outPortFIFOs_2_1_first__29_EQ_0_30_THEN_sim_ETC___d1019 &&
outPortFIFOs_2_1$first == 3'd0 } ;
assign IF_flitBuffers_3_notEmpty__2_BIT_0_3_THEN_IF_I_ETC___d112 =
flitBuffers_3$notEmpty[0] ?
IF_IF_outPortFIFOs_3_first__4_EQ_0_5_THEN_simp_ETC___d111 :
{ flitBuffers_3$notEmpty[1] &&
IF_outPortFIFOs_3_1_first__8_EQ_0_9_THEN_simpl_ETC___d1013 &&
outPortFIFOs_3_1$first == 3'd4,
flitBuffers_3$notEmpty[1] &&
IF_outPortFIFOs_3_1_first__8_EQ_0_9_THEN_simpl_ETC___d1013 &&
outPortFIFOs_3_1$first == 3'd3,
flitBuffers_3$notEmpty[1] &&
IF_outPortFIFOs_3_1_first__8_EQ_0_9_THEN_simpl_ETC___d1013 &&
outPortFIFOs_3_1$first == 3'd2,
flitBuffers_3$notEmpty[1] &&
IF_outPortFIFOs_3_1_first__8_EQ_0_9_THEN_simpl_ETC___d1013 &&
outPortFIFOs_3_1$first == 3'd1,
flitBuffers_3$notEmpty[1] &&
IF_outPortFIFOs_3_1_first__8_EQ_0_9_THEN_simpl_ETC___d1013 &&
outPortFIFOs_3_1$first == 3'd0 } ;
assign IF_flitBuffers_4_notEmpty_BIT_0_THEN_IF_IF_out_ETC___d71 =
flitBuffers_4$notEmpty[0] ?
IF_IF_outPortFIFOs_4_first_EQ_0_THEN_simple_cr_ETC___d70 :
{ flitBuffers_4$notEmpty[1] &&
IF_outPortFIFOs_4_1_first__2_EQ_0_3_THEN_simpl_ETC___d1007 &&
outPortFIFOs_4_1$first == 3'd4,
flitBuffers_4$notEmpty[1] &&
IF_outPortFIFOs_4_1_first__2_EQ_0_3_THEN_simpl_ETC___d1007 &&
outPortFIFOs_4_1$first == 3'd3,
flitBuffers_4$notEmpty[1] &&
IF_outPortFIFOs_4_1_first__2_EQ_0_3_THEN_simpl_ETC___d1007 &&
outPortFIFOs_4_1$first == 3'd2,
flitBuffers_4$notEmpty[1] &&
IF_outPortFIFOs_4_1_first__2_EQ_0_3_THEN_simpl_ETC___d1007 &&
outPortFIFOs_4_1$first == 3'd1,
flitBuffers_4$notEmpty[1] &&
IF_outPortFIFOs_4_1_first__2_EQ_0_3_THEN_simpl_ETC___d1007 &&
outPortFIFOs_4_1$first == 3'd0 } ;
assign IF_flitBuffers_notEmpty__96_BIT_0_97_THEN_IF_I_ETC___d236 =
flitBuffers$notEmpty[0] ?
IF_IF_outPortFIFOs_0_first__98_EQ_0_99_THEN_si_ETC___d235 :
{ flitBuffers$notEmpty[1] &&
IF_outPortFIFOs_0_1_first__12_EQ_0_13_THEN_sim_ETC___d1033 &&
outPortFIFOs_0_1$first == 3'd4,
flitBuffers$notEmpty[1] &&
IF_outPortFIFOs_0_1_first__12_EQ_0_13_THEN_sim_ETC___d1033 &&
outPortFIFOs_0_1$first == 3'd3,
flitBuffers$notEmpty[1] &&
IF_outPortFIFOs_0_1_first__12_EQ_0_13_THEN_sim_ETC___d1033 &&
outPortFIFOs_0_1$first == 3'd2,
flitBuffers$notEmpty[1] &&
IF_outPortFIFOs_0_1_first__12_EQ_0_13_THEN_sim_ETC___d1033 &&
outPortFIFOs_0_1$first == 3'd1,
flitBuffers$notEmpty[1] &&
IF_outPortFIFOs_0_1_first__12_EQ_0_13_THEN_sim_ETC___d1033 &&
outPortFIFOs_0_1$first == 3'd0 } ;
assign IF_outport_encoder_02_BIT_3_03_THEN_IF_outport_ETC___d910 =
outport_encoder___d1114[3] ?
((outport_encoder___d1114[2:0] == 3'd1) ?
3'd3 :
IF_outport_encoder_67_BIT_3_68_THEN_IF_outport_ETC___d914) :
IF_outport_encoder_67_BIT_3_68_THEN_IF_outport_ETC___d914 ;
assign IF_outport_encoder_02_BIT_3_03_THEN_IF_outport_ETC___d911 =
outport_encoder___d1114[3] ?
((outport_encoder___d1114[2:0] == 3'd2) ?
3'd3 :
IF_outport_encoder_67_BIT_3_68_THEN_IF_outport_ETC___d915) :
IF_outport_encoder_67_BIT_3_68_THEN_IF_outport_ETC___d915 ;
assign IF_outport_encoder_02_BIT_3_03_THEN_IF_outport_ETC___d912 =
outport_encoder___d1114[3] ?
((outport_encoder___d1114[2:0] == 3'd3) ?
outport_encoder___d1114[2:0] :
IF_outport_encoder_67_BIT_3_68_THEN_IF_outport_ETC___d916) :
IF_outport_encoder_67_BIT_3_68_THEN_IF_outport_ETC___d916 ;
assign IF_outport_encoder_02_BIT_3_03_THEN_IF_outport_ETC___d913 =
outport_encoder___d1114[3] ?
((outport_encoder___d1114[2:0] == 3'd4) ?
3'd3 :
IF_outport_encoder_67_BIT_3_68_THEN_IF_outport_ETC___d917) :
IF_outport_encoder_67_BIT_3_68_THEN_IF_outport_ETC___d917 ;
assign IF_outport_encoder_02_BIT_3_03_THEN_NOT_outpor_ETC___d1105 =
outport_encoder___d1114[3] ?
outport_encoder___d1114[2:0] != 3'd0 &&
IF_outport_encoder_67_BIT_3_68_THEN_NOT_outpor_ETC___d955 :
IF_outport_encoder_67_BIT_3_68_THEN_NOT_outpor_ETC___d955 ;
assign IF_outport_encoder_02_BIT_3_03_THEN_NOT_outpor_ETC___d1106 =
outport_encoder___d1114[3] ?
outport_encoder___d1114[2:0] != 3'd1 &&
IF_outport_encoder_67_BIT_3_68_THEN_NOT_outpor_ETC___d966 :
IF_outport_encoder_67_BIT_3_68_THEN_NOT_outpor_ETC___d966 ;
assign IF_outport_encoder_02_BIT_3_03_THEN_NOT_outpor_ETC___d1107 =
outport_encoder___d1114[3] ?
outport_encoder___d1114[2:0] != 3'd2 &&
IF_outport_encoder_67_BIT_3_68_THEN_NOT_outpor_ETC___d974 :
IF_outport_encoder_67_BIT_3_68_THEN_NOT_outpor_ETC___d974 ;
assign IF_outport_encoder_02_BIT_3_03_THEN_NOT_outpor_ETC___d1108 =
outport_encoder___d1114[3] ?
outport_encoder___d1114[2:0] != 3'd3 &&
IF_outport_encoder_67_BIT_3_68_THEN_NOT_outpor_ETC___d982 :
IF_outport_encoder_67_BIT_3_68_THEN_NOT_outpor_ETC___d982 ;
assign IF_outport_encoder_02_BIT_3_03_THEN_NOT_outpor_ETC___d1109 =
outport_encoder___d1114[3] ?
outport_encoder___d1114[2:0] != 3'd4 &&
IF_outport_encoder_67_BIT_3_68_THEN_NOT_outpor_ETC___d990 :
IF_outport_encoder_67_BIT_3_68_THEN_NOT_outpor_ETC___d990 ;
assign IF_outport_encoder_02_BIT_3_03_THEN_NOT_outpor_ETC___d898 =
outport_encoder___d1114[3] ?
outport_encoder___d1114[2:0] != 3'd0 &&
IF_outport_encoder_67_BIT_3_68_THEN_NOT_outpor_ETC___d907 :
IF_outport_encoder_67_BIT_3_68_THEN_NOT_outpor_ETC___d907 ;
assign IF_outport_encoder_02_BIT_3_03_THEN_NOT_outpor_ETC___d902 =
outport_encoder___d1114[3] ?
outport_encoder___d1114[2:0] != 3'd0 &&
IF_outport_encoder_67_BIT_3_68_THEN_NOT_outpor_ETC___d901 :
IF_outport_encoder_67_BIT_3_68_THEN_NOT_outpor_ETC___d901 ;
assign IF_outport_encoder_02_BIT_3_03_THEN_NOT_outpor_ETC___d903 =
outport_encoder___d1114[3] ?
outport_encoder___d1114[2:0] != 3'd0 &&
outport_encoder___d1115[3] &&
outport_encoder___d1115[2:0] == 3'd0 :
outport_encoder___d1115[3] &&
outport_encoder___d1115[2:0] == 3'd0 ;
assign IF_outport_encoder_02_BIT_3_03_THEN_outport_en_ETC___d1126 =
outport_encoder___d1114[3] ?
outport_encoder___d1114[2:0] == 3'd0 ||
IF_outport_encoder_67_BIT_3_68_THEN_outport_en_ETC___d1125 :
IF_outport_encoder_67_BIT_3_68_THEN_outport_en_ETC___d1125 ;
assign IF_outport_encoder_02_BIT_3_03_THEN_outport_en_ETC___d1131 =
outport_encoder___d1114[3] ?
outport_encoder___d1114[2:0] == 3'd1 ||
IF_outport_encoder_67_BIT_3_68_THEN_outport_en_ETC___d1130 :
IF_outport_encoder_67_BIT_3_68_THEN_outport_en_ETC___d1130 ;
assign IF_outport_encoder_02_BIT_3_03_THEN_outport_en_ETC___d1136 =
outport_encoder___d1114[3] ?
outport_encoder___d1114[2:0] == 3'd2 ||
IF_outport_encoder_67_BIT_3_68_THEN_outport_en_ETC___d1135 :
IF_outport_encoder_67_BIT_3_68_THEN_outport_en_ETC___d1135 ;
assign IF_outport_encoder_02_BIT_3_03_THEN_outport_en_ETC___d1141 =
outport_encoder___d1114[3] ?
outport_encoder___d1114[2:0] == 3'd3 ||
IF_outport_encoder_67_BIT_3_68_THEN_outport_en_ETC___d1140 :
IF_outport_encoder_67_BIT_3_68_THEN_outport_en_ETC___d1140 ;
assign IF_outport_encoder_02_BIT_3_03_THEN_outport_en_ETC___d1146 =
outport_encoder___d1114[3] ?
outport_encoder___d1114[2:0] == 3'd4 ||
IF_outport_encoder_67_BIT_3_68_THEN_outport_en_ETC___d1145 :
IF_outport_encoder_67_BIT_3_68_THEN_outport_en_ETC___d1145 ;
assign IF_outport_encoder_32_BIT_3_33_THEN_IF_outport_ETC___d918 =
outport_encoder___d1116[3] ?
((outport_encoder___d1116[2:0] == 3'd1) ?
outport_encoder___d1116[2:0] :
3'd0) :
3'd0 ;
assign IF_outport_encoder_32_BIT_3_33_THEN_IF_outport_ETC___d919 =
outport_encoder___d1116[3] ?
((outport_encoder___d1116[2:0] == 3'd2) ? 3'd1 : 3'd0) :
3'd0 ;
assign IF_outport_encoder_32_BIT_3_33_THEN_IF_outport_ETC___d920 =
outport_encoder___d1116[3] ?
((outport_encoder___d1116[2:0] == 3'd3) ? 3'd1 : 3'd0) :
3'd0 ;
assign IF_outport_encoder_32_BIT_3_33_THEN_IF_outport_ETC___d921 =
outport_encoder___d1116[3] ?
((outport_encoder___d1116[2:0] == 3'd4) ? 3'd1 : 3'd0) :
3'd0 ;
assign IF_outport_encoder_32_BIT_3_33_THEN_NOT_outpor_ETC___d958 =
outport_encoder___d1116[3] ?
outport_encoder___d1116[2:0] != 3'd0 &&
(!outport_encoder___d1117[3] ||
outport_encoder___d1117[2:0] != 3'd0) :
!outport_encoder___d1117[3] ||
outport_encoder___d1117[2:0] != 3'd0 ;
assign IF_outport_encoder_32_BIT_3_33_THEN_NOT_outpor_ETC___d968 =
outport_encoder___d1116[3] ?
outport_encoder___d1116[2:0] != 3'd1 &&
(!outport_encoder___d1117[3] ||
outport_encoder___d1117[2:0] != 3'd1) :
!outport_encoder___d1117[3] ||
outport_encoder___d1117[2:0] != 3'd1 ;
assign IF_outport_encoder_32_BIT_3_33_THEN_NOT_outpor_ETC___d976 =
outport_encoder___d1116[3] ?
outport_encoder___d1116[2:0] != 3'd2 &&
(!outport_encoder___d1117[3] ||
outport_encoder___d1117[2:0] != 3'd2) :
!outport_encoder___d1117[3] ||
outport_encoder___d1117[2:0] != 3'd2 ;
assign IF_outport_encoder_32_BIT_3_33_THEN_NOT_outpor_ETC___d984 =
outport_encoder___d1116[3] ?
outport_encoder___d1116[2:0] != 3'd3 &&
(!outport_encoder___d1117[3] ||
outport_encoder___d1117[2:0] != 3'd3) :
!outport_encoder___d1117[3] ||
outport_encoder___d1117[2:0] != 3'd3 ;
assign IF_outport_encoder_32_BIT_3_33_THEN_NOT_outpor_ETC___d992 =
outport_encoder___d1116[3] ?
outport_encoder___d1116[2:0] != 3'd4 &&
(!outport_encoder___d1117[3] ||
outport_encoder___d1117[2:0] != 3'd4) :
!outport_encoder___d1117[3] ||
outport_encoder___d1117[2:0] != 3'd4 ;
assign IF_outport_encoder_32_BIT_3_33_THEN_outport_en_ETC___d1124 =
outport_encoder___d1116[3] ?
outport_encoder___d1116[2:0] == 3'd0 ||
outport_encoder___d1117[3] &&
outport_encoder___d1117[2:0] == 3'd0 :
outport_encoder___d1117[3] &&
outport_encoder___d1117[2:0] == 3'd0 ;
assign IF_outport_encoder_32_BIT_3_33_THEN_outport_en_ETC___d1129 =
outport_encoder___d1116[3] ?
outport_encoder___d1116[2:0] == 3'd1 ||
outport_encoder___d1117[3] &&
outport_encoder___d1117[2:0] == 3'd1 :
outport_encoder___d1117[3] &&
outport_encoder___d1117[2:0] == 3'd1 ;
assign IF_outport_encoder_32_BIT_3_33_THEN_outport_en_ETC___d1134 =
outport_encoder___d1116[3] ?
outport_encoder___d1116[2:0] == 3'd2 ||
outport_encoder___d1117[3] &&
outport_encoder___d1117[2:0] == 3'd2 :
outport_encoder___d1117[3] &&
outport_encoder___d1117[2:0] == 3'd2 ;
assign IF_outport_encoder_32_BIT_3_33_THEN_outport_en_ETC___d1139 =
outport_encoder___d1116[3] ?
outport_encoder___d1116[2:0] == 3'd3 ||
outport_encoder___d1117[3] &&
outport_encoder___d1117[2:0] == 3'd3 :
outport_encoder___d1117[3] &&
outport_encoder___d1117[2:0] == 3'd3 ;
assign IF_outport_encoder_32_BIT_3_33_THEN_outport_en_ETC___d1144 =
outport_encoder___d1116[3] ?
outport_encoder___d1116[2:0] == 3'd4 ||
outport_encoder___d1117[3] &&
outport_encoder___d1117[2:0] == 3'd4 :
outport_encoder___d1117[3] &&
outport_encoder___d1117[2:0] == 3'd4 ;
assign IF_outport_encoder_37_BIT_3_38_THEN_NOT_outpor_ETC___d1047 =
outport_encoder___d1113[3] ?
outport_encoder___d1113[2:0] != 3'd0 &&
IF_outport_encoder_02_BIT_3_03_THEN_NOT_outpor_ETC___d898 :
IF_outport_encoder_02_BIT_3_03_THEN_NOT_outpor_ETC___d898 ;
assign IF_outport_encoder_37_BIT_3_38_THEN_NOT_outpor_ETC___d1089 =
outport_encoder___d1113[3] ?
outport_encoder___d1113[2:0] != 3'd0 &&
IF_outport_encoder_02_BIT_3_03_THEN_NOT_outpor_ETC___d902 :
IF_outport_encoder_02_BIT_3_03_THEN_NOT_outpor_ETC___d902 ;
assign IF_outport_encoder_37_BIT_3_38_THEN_NOT_outpor_ETC___d1090 =
outport_encoder___d1113[3] ?
outport_encoder___d1113[2:0] != 3'd0 &&
IF_outport_encoder_02_BIT_3_03_THEN_NOT_outpor_ETC___d903 :
IF_outport_encoder_02_BIT_3_03_THEN_NOT_outpor_ETC___d903 ;
assign IF_outport_encoder_37_BIT_3_38_THEN_NOT_outpor_ETC___d1091 =
outport_encoder___d1113[3] ?
outport_encoder___d1113[2:0] != 3'd0 &&
outport_encoder___d1114[3] &&
outport_encoder___d1114[2:0] == 3'd0 :
outport_encoder___d1114[3] &&
outport_encoder___d1114[2:0] == 3'd0 ;
assign IF_outport_encoder_37_BIT_3_38_THEN_outport_en_ETC___d1046 =
outport_encoder___d1113[3] ?
outport_encoder___d1113[2:0] == 3'd0 ||
IF_outport_encoder_02_BIT_3_03_THEN_outport_en_ETC___d1126 :
IF_outport_encoder_02_BIT_3_03_THEN_outport_en_ETC___d1126 ;
assign IF_outport_encoder_37_BIT_3_38_THEN_outport_en_ETC___d1056 =
outport_encoder___d1113[3] ?
outport_encoder___d1113[2:0] == 3'd1 ||
IF_outport_encoder_02_BIT_3_03_THEN_outport_en_ETC___d1131 :
IF_outport_encoder_02_BIT_3_03_THEN_outport_en_ETC___d1131 ;
assign IF_outport_encoder_37_BIT_3_38_THEN_outport_en_ETC___d1058 =
outport_encoder___d1113[3] ?
outport_encoder___d1113[2:0] == 3'd2 ||
IF_outport_encoder_02_BIT_3_03_THEN_outport_en_ETC___d1136 :
IF_outport_encoder_02_BIT_3_03_THEN_outport_en_ETC___d1136 ;
assign IF_outport_encoder_37_BIT_3_38_THEN_outport_en_ETC___d1060 =
outport_encoder___d1113[3] ?
outport_encoder___d1113[2:0] == 3'd3 ||
IF_outport_encoder_02_BIT_3_03_THEN_outport_en_ETC___d1141 :
IF_outport_encoder_02_BIT_3_03_THEN_outport_en_ETC___d1141 ;
assign IF_outport_encoder_37_BIT_3_38_THEN_outport_en_ETC___d1062 =
outport_encoder___d1113[3] ?
outport_encoder___d1113[2:0] == 3'd4 ||
IF_outport_encoder_02_BIT_3_03_THEN_outport_en_ETC___d1146 :
IF_outport_encoder_02_BIT_3_03_THEN_outport_en_ETC___d1146 ;
assign IF_outport_encoder_67_BIT_3_68_THEN_IF_outport_ETC___d914 =
outport_encoder___d1115[3] ?
((outport_encoder___d1115[2:0] == 3'd1) ?
3'd2 :
IF_outport_encoder_32_BIT_3_33_THEN_IF_outport_ETC___d918) :
IF_outport_encoder_32_BIT_3_33_THEN_IF_outport_ETC___d918 ;
assign IF_outport_encoder_67_BIT_3_68_THEN_IF_outport_ETC___d915 =
outport_encoder___d1115[3] ?
((outport_encoder___d1115[2:0] == 3'd2) ?
outport_encoder___d1115[2:0] :
IF_outport_encoder_32_BIT_3_33_THEN_IF_outport_ETC___d919) :
IF_outport_encoder_32_BIT_3_33_THEN_IF_outport_ETC___d919 ;
assign IF_outport_encoder_67_BIT_3_68_THEN_IF_outport_ETC___d916 =
outport_encoder___d1115[3] ?
((outport_encoder___d1115[2:0] == 3'd3) ?
3'd2 :
IF_outport_encoder_32_BIT_3_33_THEN_IF_outport_ETC___d920) :
IF_outport_encoder_32_BIT_3_33_THEN_IF_outport_ETC___d920 ;
assign IF_outport_encoder_67_BIT_3_68_THEN_IF_outport_ETC___d917 =
outport_encoder___d1115[3] ?
((outport_encoder___d1115[2:0] == 3'd4) ?
3'd2 :
IF_outport_encoder_32_BIT_3_33_THEN_IF_outport_ETC___d921) :
IF_outport_encoder_32_BIT_3_33_THEN_IF_outport_ETC___d921 ;
assign IF_outport_encoder_67_BIT_3_68_THEN_NOT_outpor_ETC___d901 =
outport_encoder___d1115[3] ?
outport_encoder___d1115[2:0] != 3'd0 &&
outport_encoder___d1116[3] &&
outport_encoder___d1116[2:0] == 3'd0 :
outport_encoder___d1116[3] &&
outport_encoder___d1116[2:0] == 3'd0 ;
assign IF_outport_encoder_67_BIT_3_68_THEN_NOT_outpor_ETC___d907 =
outport_encoder___d1115[3] ?
outport_encoder___d1115[2:0] != 3'd0 &&
(!outport_encoder___d1116[3] ||
outport_encoder___d1116[2:0] != 3'd0) :
!outport_encoder___d1116[3] ||
outport_encoder___d1116[2:0] != 3'd0 ;
assign IF_outport_encoder_67_BIT_3_68_THEN_NOT_outpor_ETC___d955 =
outport_encoder___d1115[3] ?
outport_encoder___d1115[2:0] != 3'd0 &&
IF_outport_encoder_32_BIT_3_33_THEN_NOT_outpor_ETC___d958 :
IF_outport_encoder_32_BIT_3_33_THEN_NOT_outpor_ETC___d958 ;
assign IF_outport_encoder_67_BIT_3_68_THEN_NOT_outpor_ETC___d966 =
outport_encoder___d1115[3] ?
outport_encoder___d1115[2:0] != 3'd1 &&
IF_outport_encoder_32_BIT_3_33_THEN_NOT_outpor_ETC___d968 :
IF_outport_encoder_32_BIT_3_33_THEN_NOT_outpor_ETC___d968 ;
assign IF_outport_encoder_67_BIT_3_68_THEN_NOT_outpor_ETC___d974 =
outport_encoder___d1115[3] ?
outport_encoder___d1115[2:0] != 3'd2 &&
IF_outport_encoder_32_BIT_3_33_THEN_NOT_outpor_ETC___d976 :
IF_outport_encoder_32_BIT_3_33_THEN_NOT_outpor_ETC___d976 ;
assign IF_outport_encoder_67_BIT_3_68_THEN_NOT_outpor_ETC___d982 =
outport_encoder___d1115[3] ?
outport_encoder___d1115[2:0] != 3'd3 &&
IF_outport_encoder_32_BIT_3_33_THEN_NOT_outpor_ETC___d984 :
IF_outport_encoder_32_BIT_3_33_THEN_NOT_outpor_ETC___d984 ;
assign IF_outport_encoder_67_BIT_3_68_THEN_NOT_outpor_ETC___d990 =
outport_encoder___d1115[3] ?
outport_encoder___d1115[2:0] != 3'd4 &&
IF_outport_encoder_32_BIT_3_33_THEN_NOT_outpor_ETC___d992 :
IF_outport_encoder_32_BIT_3_33_THEN_NOT_outpor_ETC___d992 ;
assign IF_outport_encoder_67_BIT_3_68_THEN_outport_en_ETC___d1125 =
outport_encoder___d1115[3] ?
outport_encoder___d1115[2:0] == 3'd0 ||
IF_outport_encoder_32_BIT_3_33_THEN_outport_en_ETC___d1124 :
IF_outport_encoder_32_BIT_3_33_THEN_outport_en_ETC___d1124 ;
assign IF_outport_encoder_67_BIT_3_68_THEN_outport_en_ETC___d1130 =
outport_encoder___d1115[3] ?
outport_encoder___d1115[2:0] == 3'd1 ||
IF_outport_encoder_32_BIT_3_33_THEN_outport_en_ETC___d1129 :
IF_outport_encoder_32_BIT_3_33_THEN_outport_en_ETC___d1129 ;
assign IF_outport_encoder_67_BIT_3_68_THEN_outport_en_ETC___d1135 =
outport_encoder___d1115[3] ?
outport_encoder___d1115[2:0] == 3'd2 ||
IF_outport_encoder_32_BIT_3_33_THEN_outport_en_ETC___d1134 :
IF_outport_encoder_32_BIT_3_33_THEN_outport_en_ETC___d1134 ;
assign IF_outport_encoder_67_BIT_3_68_THEN_outport_en_ETC___d1140 =
outport_encoder___d1115[3] ?
outport_encoder___d1115[2:0] == 3'd3 ||
IF_outport_encoder_32_BIT_3_33_THEN_outport_en_ETC___d1139 :
IF_outport_encoder_32_BIT_3_33_THEN_outport_en_ETC___d1139 ;
assign IF_outport_encoder_67_BIT_3_68_THEN_outport_en_ETC___d1145 =
outport_encoder___d1115[3] ?
outport_encoder___d1115[2:0] == 3'd4 ||
IF_outport_encoder_32_BIT_3_33_THEN_outport_en_ETC___d1144 :
IF_outport_encoder_32_BIT_3_33_THEN_outport_en_ETC___d1144 ;
assign active_in__h48706 =
outport_encoder___d1113[3] ?
((outport_encoder___d1113[2:0] == 3'd1) ?
3'd4 :
IF_outport_encoder_02_BIT_3_03_THEN_IF_outport_ETC___d910) :
IF_outport_encoder_02_BIT_3_03_THEN_IF_outport_ETC___d910 ;
assign active_in__h50467 =
outport_encoder___d1113[3] ?
((outport_encoder___d1113[2:0] == 3'd2) ?
3'd4 :
IF_outport_encoder_02_BIT_3_03_THEN_IF_outport_ETC___d911) :
IF_outport_encoder_02_BIT_3_03_THEN_IF_outport_ETC___d911 ;
assign active_in__h52228 =
outport_encoder___d1113[3] ?
((outport_encoder___d1113[2:0] == 3'd3) ?
3'd4 :
IF_outport_encoder_02_BIT_3_03_THEN_IF_outport_ETC___d912) :
IF_outport_encoder_02_BIT_3_03_THEN_IF_outport_ETC___d912 ;
assign active_in__h53989 =
outport_encoder___d1113[3] ?
((outport_encoder___d1113[2:0] == 3'd4) ?
outport_encoder___d1113[2:0] :
IF_outport_encoder_02_BIT_3_03_THEN_IF_outport_ETC___d913) :
IF_outport_encoder_02_BIT_3_03_THEN_IF_outport_ETC___d913 ;
assign fifo_out__h36476 =
!flitBuffers$notEmpty[0] ||
IF_outPortFIFOs_0_first__98_EQ_0_99_THEN_NOT_s_ETC___d304 ;
assign fifo_out__h37661 =
!flitBuffers_1$notEmpty[0] ||
IF_outPortFIFOs_1_first__57_EQ_0_58_THEN_NOT_s_ETC___d339 ;
assign fifo_out__h38207 =
!flitBuffers_2$notEmpty[0] ||
IF_outPortFIFOs_2_first__15_EQ_0_16_THEN_NOT_s_ETC___d374 ;
assign fifo_out__h38753 =
!flitBuffers_3$notEmpty[0] ||
IF_outPortFIFOs_3_first__4_EQ_0_5_THEN_NOT_sim_ETC___d409 ;
assign fifo_out__h39299 =
!flitBuffers_4$notEmpty[0] ||
IF_outPortFIFOs_4_first_EQ_0_THEN_NOT_simple_c_ETC___d444 ;
always@(outPortFIFOs_0$first or
EN_out_ports_4_putNonFullVCs or
out_ports_4_putNonFullVCs_nonFullVCs or
EN_out_ports_0_putNonFullVCs or
out_ports_0_putNonFullVCs_nonFullVCs or
EN_out_ports_1_putNonFullVCs or
out_ports_1_putNonFullVCs_nonFullVCs or
EN_out_ports_2_putNonFullVCs or
out_ports_2_putNonFullVCs_nonFullVCs or
EN_out_ports_3_putNonFullVCs or
out_ports_3_putNonFullVCs_nonFullVCs)
begin
case (outPortFIFOs_0$first)
3'd0:
IF_outPortFIFOs_0_first__98_EQ_0_99_THEN_NOT_s_ETC___d304 =
!EN_out_ports_0_putNonFullVCs ||
!out_ports_0_putNonFullVCs_nonFullVCs[0];
3'd1:
IF_outPortFIFOs_0_first__98_EQ_0_99_THEN_NOT_s_ETC___d304 =
!EN_out_ports_1_putNonFullVCs ||
!out_ports_1_putNonFullVCs_nonFullVCs[0];
3'd2:
IF_outPortFIFOs_0_first__98_EQ_0_99_THEN_NOT_s_ETC___d304 =
!EN_out_ports_2_putNonFullVCs ||
!out_ports_2_putNonFullVCs_nonFullVCs[0];
3'd3:
IF_outPortFIFOs_0_first__98_EQ_0_99_THEN_NOT_s_ETC___d304 =
!EN_out_ports_3_putNonFullVCs ||
!out_ports_3_putNonFullVCs_nonFullVCs[0];
3'd4:
IF_outPortFIFOs_0_first__98_EQ_0_99_THEN_NOT_s_ETC___d304 =
!EN_out_ports_4_putNonFullVCs ||
!out_ports_4_putNonFullVCs_nonFullVCs[0];
default: IF_outPortFIFOs_0_first__98_EQ_0_99_THEN_NOT_s_ETC___d304 =
!EN_out_ports_4_putNonFullVCs ||
!out_ports_4_putNonFullVCs_nonFullVCs[0];
endcase
end
always@(outPortFIFOs_1$first or
EN_out_ports_4_putNonFullVCs or
out_ports_4_putNonFullVCs_nonFullVCs or
EN_out_ports_0_putNonFullVCs or
out_ports_0_putNonFullVCs_nonFullVCs or
EN_out_ports_1_putNonFullVCs or
out_ports_1_putNonFullVCs_nonFullVCs or
EN_out_ports_2_putNonFullVCs or
out_ports_2_putNonFullVCs_nonFullVCs or
EN_out_ports_3_putNonFullVCs or
out_ports_3_putNonFullVCs_nonFullVCs)
begin
case (outPortFIFOs_1$first)
3'd0:
IF_outPortFIFOs_1_first__57_EQ_0_58_THEN_NOT_s_ETC___d339 =
!EN_out_ports_0_putNonFullVCs ||
!out_ports_0_putNonFullVCs_nonFullVCs[0];
3'd1:
IF_outPortFIFOs_1_first__57_EQ_0_58_THEN_NOT_s_ETC___d339 =
!EN_out_ports_1_putNonFullVCs ||
!out_ports_1_putNonFullVCs_nonFullVCs[0];
3'd2:
IF_outPortFIFOs_1_first__57_EQ_0_58_THEN_NOT_s_ETC___d339 =
!EN_out_ports_2_putNonFullVCs ||
!out_ports_2_putNonFullVCs_nonFullVCs[0];
3'd3:
IF_outPortFIFOs_1_first__57_EQ_0_58_THEN_NOT_s_ETC___d339 =
!EN_out_ports_3_putNonFullVCs ||
!out_ports_3_putNonFullVCs_nonFullVCs[0];
3'd4:
IF_outPortFIFOs_1_first__57_EQ_0_58_THEN_NOT_s_ETC___d339 =
!EN_out_ports_4_putNonFullVCs ||
!out_ports_4_putNonFullVCs_nonFullVCs[0];
default: IF_outPortFIFOs_1_first__57_EQ_0_58_THEN_NOT_s_ETC___d339 =
!EN_out_ports_4_putNonFullVCs ||
!out_ports_4_putNonFullVCs_nonFullVCs[0];
endcase
end
always@(outPortFIFOs_2$first or
EN_out_ports_4_putNonFullVCs or
out_ports_4_putNonFullVCs_nonFullVCs or
EN_out_ports_0_putNonFullVCs or
out_ports_0_putNonFullVCs_nonFullVCs or
EN_out_ports_1_putNonFullVCs or
out_ports_1_putNonFullVCs_nonFullVCs or
EN_out_ports_2_putNonFullVCs or
out_ports_2_putNonFullVCs_nonFullVCs or
EN_out_ports_3_putNonFullVCs or
out_ports_3_putNonFullVCs_nonFullVCs)
begin
case (outPortFIFOs_2$first)
3'd0:
IF_outPortFIFOs_2_first__15_EQ_0_16_THEN_NOT_s_ETC___d374 =
!EN_out_ports_0_putNonFullVCs ||
!out_ports_0_putNonFullVCs_nonFullVCs[0];
3'd1:
IF_outPortFIFOs_2_first__15_EQ_0_16_THEN_NOT_s_ETC___d374 =
!EN_out_ports_1_putNonFullVCs ||
!out_ports_1_putNonFullVCs_nonFullVCs[0];
3'd2:
IF_outPortFIFOs_2_first__15_EQ_0_16_THEN_NOT_s_ETC___d374 =
!EN_out_ports_2_putNonFullVCs ||
!out_ports_2_putNonFullVCs_nonFullVCs[0];
3'd3:
IF_outPortFIFOs_2_first__15_EQ_0_16_THEN_NOT_s_ETC___d374 =
!EN_out_ports_3_putNonFullVCs ||
!out_ports_3_putNonFullVCs_nonFullVCs[0];
3'd4:
IF_outPortFIFOs_2_first__15_EQ_0_16_THEN_NOT_s_ETC___d374 =
!EN_out_ports_4_putNonFullVCs ||
!out_ports_4_putNonFullVCs_nonFullVCs[0];
default: IF_outPortFIFOs_2_first__15_EQ_0_16_THEN_NOT_s_ETC___d374 =
!EN_out_ports_4_putNonFullVCs ||
!out_ports_4_putNonFullVCs_nonFullVCs[0];
endcase
end
always@(outPortFIFOs_3$first or
EN_out_ports_4_putNonFullVCs or
out_ports_4_putNonFullVCs_nonFullVCs or
EN_out_ports_0_putNonFullVCs or
out_ports_0_putNonFullVCs_nonFullVCs or
EN_out_ports_1_putNonFullVCs or
out_ports_1_putNonFullVCs_nonFullVCs or
EN_out_ports_2_putNonFullVCs or
out_ports_2_putNonFullVCs_nonFullVCs or
EN_out_ports_3_putNonFullVCs or
out_ports_3_putNonFullVCs_nonFullVCs)
begin
case (outPortFIFOs_3$first)
3'd0:
IF_outPortFIFOs_3_first__4_EQ_0_5_THEN_NOT_sim_ETC___d409 =
!EN_out_ports_0_putNonFullVCs ||
!out_ports_0_putNonFullVCs_nonFullVCs[0];
3'd1:
IF_outPortFIFOs_3_first__4_EQ_0_5_THEN_NOT_sim_ETC___d409 =
!EN_out_ports_1_putNonFullVCs ||
!out_ports_1_putNonFullVCs_nonFullVCs[0];
3'd2:
IF_outPortFIFOs_3_first__4_EQ_0_5_THEN_NOT_sim_ETC___d409 =
!EN_out_ports_2_putNonFullVCs ||
!out_ports_2_putNonFullVCs_nonFullVCs[0];
3'd3:
IF_outPortFIFOs_3_first__4_EQ_0_5_THEN_NOT_sim_ETC___d409 =
!EN_out_ports_3_putNonFullVCs ||
!out_ports_3_putNonFullVCs_nonFullVCs[0];
3'd4:
IF_outPortFIFOs_3_first__4_EQ_0_5_THEN_NOT_sim_ETC___d409 =
!EN_out_ports_4_putNonFullVCs ||
!out_ports_4_putNonFullVCs_nonFullVCs[0];
default: IF_outPortFIFOs_3_first__4_EQ_0_5_THEN_NOT_sim_ETC___d409 =
!EN_out_ports_4_putNonFullVCs ||
!out_ports_4_putNonFullVCs_nonFullVCs[0];
endcase
end
always@(outPortFIFOs_4$first or
EN_out_ports_4_putNonFullVCs or
out_ports_4_putNonFullVCs_nonFullVCs or
EN_out_ports_0_putNonFullVCs or
out_ports_0_putNonFullVCs_nonFullVCs or
EN_out_ports_1_putNonFullVCs or
out_ports_1_putNonFullVCs_nonFullVCs or
EN_out_ports_2_putNonFullVCs or
out_ports_2_putNonFullVCs_nonFullVCs or
EN_out_ports_3_putNonFullVCs or
out_ports_3_putNonFullVCs_nonFullVCs)
begin
case (outPortFIFOs_4$first)
3'd0:
IF_outPortFIFOs_4_first_EQ_0_THEN_NOT_simple_c_ETC___d444 =
!EN_out_ports_0_putNonFullVCs ||
!out_ports_0_putNonFullVCs_nonFullVCs[0];
3'd1:
IF_outPortFIFOs_4_first_EQ_0_THEN_NOT_simple_c_ETC___d444 =
!EN_out_ports_1_putNonFullVCs ||
!out_ports_1_putNonFullVCs_nonFullVCs[0];
3'd2:
IF_outPortFIFOs_4_first_EQ_0_THEN_NOT_simple_c_ETC___d444 =
!EN_out_ports_2_putNonFullVCs ||
!out_ports_2_putNonFullVCs_nonFullVCs[0];
3'd3:
IF_outPortFIFOs_4_first_EQ_0_THEN_NOT_simple_c_ETC___d444 =
!EN_out_ports_3_putNonFullVCs ||
!out_ports_3_putNonFullVCs_nonFullVCs[0];
3'd4:
IF_outPortFIFOs_4_first_EQ_0_THEN_NOT_simple_c_ETC___d444 =
!EN_out_ports_4_putNonFullVCs ||
!out_ports_4_putNonFullVCs_nonFullVCs[0];
default: IF_outPortFIFOs_4_first_EQ_0_THEN_NOT_simple_c_ETC___d444 =
!EN_out_ports_4_putNonFullVCs ||
!out_ports_4_putNonFullVCs_nonFullVCs[0];
endcase
end
always@(outPortFIFOs_4_1$first or
EN_out_ports_4_putNonFullVCs or
out_ports_4_putNonFullVCs_nonFullVCs or
EN_out_ports_0_putNonFullVCs or
out_ports_0_putNonFullVCs_nonFullVCs or
EN_out_ports_1_putNonFullVCs or
out_ports_1_putNonFullVCs_nonFullVCs or
EN_out_ports_2_putNonFullVCs or
out_ports_2_putNonFullVCs_nonFullVCs or
EN_out_ports_3_putNonFullVCs or
out_ports_3_putNonFullVCs_nonFullVCs)
begin
case (outPortFIFOs_4_1$first)
3'd0:
IF_outPortFIFOs_4_1_first__2_EQ_0_3_THEN_simpl_ETC___d1007 =
EN_out_ports_0_putNonFullVCs &&
out_ports_0_putNonFullVCs_nonFullVCs[1];
3'd1:
IF_outPortFIFOs_4_1_first__2_EQ_0_3_THEN_simpl_ETC___d1007 =
EN_out_ports_1_putNonFullVCs &&
out_ports_1_putNonFullVCs_nonFullVCs[1];
3'd2:
IF_outPortFIFOs_4_1_first__2_EQ_0_3_THEN_simpl_ETC___d1007 =
EN_out_ports_2_putNonFullVCs &&
out_ports_2_putNonFullVCs_nonFullVCs[1];
3'd3:
IF_outPortFIFOs_4_1_first__2_EQ_0_3_THEN_simpl_ETC___d1007 =
EN_out_ports_3_putNonFullVCs &&
out_ports_3_putNonFullVCs_nonFullVCs[1];
default: IF_outPortFIFOs_4_1_first__2_EQ_0_3_THEN_simpl_ETC___d1007 =
EN_out_ports_4_putNonFullVCs &&
out_ports_4_putNonFullVCs_nonFullVCs[1];
endcase
end
always@(outPortFIFOs_4$first or
EN_out_ports_4_putNonFullVCs or
out_ports_4_putNonFullVCs_nonFullVCs or
EN_out_ports_0_putNonFullVCs or
out_ports_0_putNonFullVCs_nonFullVCs or
EN_out_ports_1_putNonFullVCs or
out_ports_1_putNonFullVCs_nonFullVCs or
EN_out_ports_2_putNonFullVCs or
out_ports_2_putNonFullVCs_nonFullVCs or
EN_out_ports_3_putNonFullVCs or
out_ports_3_putNonFullVCs_nonFullVCs)
begin
case (outPortFIFOs_4$first)
3'd0:
IF_outPortFIFOs_4_first_EQ_0_THEN_simple_credi_ETC___d944 =
EN_out_ports_0_putNonFullVCs &&
out_ports_0_putNonFullVCs_nonFullVCs[0];
3'd1:
IF_outPortFIFOs_4_first_EQ_0_THEN_simple_credi_ETC___d944 =
EN_out_ports_1_putNonFullVCs &&
out_ports_1_putNonFullVCs_nonFullVCs[0];
3'd2:
IF_outPortFIFOs_4_first_EQ_0_THEN_simple_credi_ETC___d944 =
EN_out_ports_2_putNonFullVCs &&
out_ports_2_putNonFullVCs_nonFullVCs[0];
3'd3:
IF_outPortFIFOs_4_first_EQ_0_THEN_simple_credi_ETC___d944 =
EN_out_ports_3_putNonFullVCs &&
out_ports_3_putNonFullVCs_nonFullVCs[0];
default: IF_outPortFIFOs_4_first_EQ_0_THEN_simple_credi_ETC___d944 =
EN_out_ports_4_putNonFullVCs &&
out_ports_4_putNonFullVCs_nonFullVCs[0];
endcase
end
always@(outPortFIFOs_3_1$first or
EN_out_ports_4_putNonFullVCs or
out_ports_4_putNonFullVCs_nonFullVCs or
EN_out_ports_0_putNonFullVCs or
out_ports_0_putNonFullVCs_nonFullVCs or
EN_out_ports_1_putNonFullVCs or
out_ports_1_putNonFullVCs_nonFullVCs or
EN_out_ports_2_putNonFullVCs or
out_ports_2_putNonFullVCs_nonFullVCs or
EN_out_ports_3_putNonFullVCs or
out_ports_3_putNonFullVCs_nonFullVCs)
begin
case (outPortFIFOs_3_1$first)
3'd0:
IF_outPortFIFOs_3_1_first__8_EQ_0_9_THEN_simpl_ETC___d1013 =
EN_out_ports_0_putNonFullVCs &&
out_ports_0_putNonFullVCs_nonFullVCs[1];
3'd1:
IF_outPortFIFOs_3_1_first__8_EQ_0_9_THEN_simpl_ETC___d1013 =
EN_out_ports_1_putNonFullVCs &&
out_ports_1_putNonFullVCs_nonFullVCs[1];
3'd2:
IF_outPortFIFOs_3_1_first__8_EQ_0_9_THEN_simpl_ETC___d1013 =
EN_out_ports_2_putNonFullVCs &&
out_ports_2_putNonFullVCs_nonFullVCs[1];
3'd3:
IF_outPortFIFOs_3_1_first__8_EQ_0_9_THEN_simpl_ETC___d1013 =
EN_out_ports_3_putNonFullVCs &&
out_ports_3_putNonFullVCs_nonFullVCs[1];
default: IF_outPortFIFOs_3_1_first__8_EQ_0_9_THEN_simpl_ETC___d1013 =
EN_out_ports_4_putNonFullVCs &&
out_ports_4_putNonFullVCs_nonFullVCs[1];
endcase
end
always@(outPortFIFOs_3$first or
EN_out_ports_4_putNonFullVCs or
out_ports_4_putNonFullVCs_nonFullVCs or
EN_out_ports_0_putNonFullVCs or
out_ports_0_putNonFullVCs_nonFullVCs or
EN_out_ports_1_putNonFullVCs or
out_ports_1_putNonFullVCs_nonFullVCs or
EN_out_ports_2_putNonFullVCs or
out_ports_2_putNonFullVCs_nonFullVCs or
EN_out_ports_3_putNonFullVCs or
out_ports_3_putNonFullVCs_nonFullVCs)
begin
case (outPortFIFOs_3$first)
3'd0:
IF_outPortFIFOs_3_first__4_EQ_0_5_THEN_simple__ETC___d946 =
EN_out_ports_0_putNonFullVCs &&
out_ports_0_putNonFullVCs_nonFullVCs[0];
3'd1:
IF_outPortFIFOs_3_first__4_EQ_0_5_THEN_simple__ETC___d946 =
EN_out_ports_1_putNonFullVCs &&
out_ports_1_putNonFullVCs_nonFullVCs[0];
3'd2:
IF_outPortFIFOs_3_first__4_EQ_0_5_THEN_simple__ETC___d946 =
EN_out_ports_2_putNonFullVCs &&
out_ports_2_putNonFullVCs_nonFullVCs[0];
3'd3:
IF_outPortFIFOs_3_first__4_EQ_0_5_THEN_simple__ETC___d946 =
EN_out_ports_3_putNonFullVCs &&
out_ports_3_putNonFullVCs_nonFullVCs[0];
default: IF_outPortFIFOs_3_first__4_EQ_0_5_THEN_simple__ETC___d946 =
EN_out_ports_4_putNonFullVCs &&
out_ports_4_putNonFullVCs_nonFullVCs[0];
endcase
end
always@(outPortFIFOs_2_1$first or
EN_out_ports_4_putNonFullVCs or
out_ports_4_putNonFullVCs_nonFullVCs or
EN_out_ports_0_putNonFullVCs or
out_ports_0_putNonFullVCs_nonFullVCs or
EN_out_ports_1_putNonFullVCs or
out_ports_1_putNonFullVCs_nonFullVCs or
EN_out_ports_2_putNonFullVCs or
out_ports_2_putNonFullVCs_nonFullVCs or
EN_out_ports_3_putNonFullVCs or
out_ports_3_putNonFullVCs_nonFullVCs)
begin
case (outPortFIFOs_2_1$first)
3'd0:
IF_outPortFIFOs_2_1_first__29_EQ_0_30_THEN_sim_ETC___d1019 =
EN_out_ports_0_putNonFullVCs &&
out_ports_0_putNonFullVCs_nonFullVCs[1];
3'd1:
IF_outPortFIFOs_2_1_first__29_EQ_0_30_THEN_sim_ETC___d1019 =
EN_out_ports_1_putNonFullVCs &&
out_ports_1_putNonFullVCs_nonFullVCs[1];
3'd2:
IF_outPortFIFOs_2_1_first__29_EQ_0_30_THEN_sim_ETC___d1019 =
EN_out_ports_2_putNonFullVCs &&
out_ports_2_putNonFullVCs_nonFullVCs[1];
3'd3:
IF_outPortFIFOs_2_1_first__29_EQ_0_30_THEN_sim_ETC___d1019 =
EN_out_ports_3_putNonFullVCs &&
out_ports_3_putNonFullVCs_nonFullVCs[1];
default: IF_outPortFIFOs_2_1_first__29_EQ_0_30_THEN_sim_ETC___d1019 =
EN_out_ports_4_putNonFullVCs &&
out_ports_4_putNonFullVCs_nonFullVCs[1];
endcase
end
always@(outPortFIFOs_2$first or
EN_out_ports_4_putNonFullVCs or
out_ports_4_putNonFullVCs_nonFullVCs or
EN_out_ports_0_putNonFullVCs or
out_ports_0_putNonFullVCs_nonFullVCs or
EN_out_ports_1_putNonFullVCs or
out_ports_1_putNonFullVCs_nonFullVCs or
EN_out_ports_2_putNonFullVCs or
out_ports_2_putNonFullVCs_nonFullVCs or
EN_out_ports_3_putNonFullVCs or
out_ports_3_putNonFullVCs_nonFullVCs)
begin
case (outPortFIFOs_2$first)
3'd0:
IF_outPortFIFOs_2_first__15_EQ_0_16_THEN_simpl_ETC___d948 =
EN_out_ports_0_putNonFullVCs &&
out_ports_0_putNonFullVCs_nonFullVCs[0];
3'd1:
IF_outPortFIFOs_2_first__15_EQ_0_16_THEN_simpl_ETC___d948 =
EN_out_ports_1_putNonFullVCs &&
out_ports_1_putNonFullVCs_nonFullVCs[0];
3'd2:
IF_outPortFIFOs_2_first__15_EQ_0_16_THEN_simpl_ETC___d948 =
EN_out_ports_2_putNonFullVCs &&
out_ports_2_putNonFullVCs_nonFullVCs[0];
3'd3:
IF_outPortFIFOs_2_first__15_EQ_0_16_THEN_simpl_ETC___d948 =
EN_out_ports_3_putNonFullVCs &&
out_ports_3_putNonFullVCs_nonFullVCs[0];
default: IF_outPortFIFOs_2_first__15_EQ_0_16_THEN_simpl_ETC___d948 =
EN_out_ports_4_putNonFullVCs &&
out_ports_4_putNonFullVCs_nonFullVCs[0];
endcase
end
always@(outPortFIFOs_1_1$first or
EN_out_ports_4_putNonFullVCs or
out_ports_4_putNonFullVCs_nonFullVCs or
EN_out_ports_0_putNonFullVCs or
out_ports_0_putNonFullVCs_nonFullVCs or
EN_out_ports_1_putNonFullVCs or
out_ports_1_putNonFullVCs_nonFullVCs or
EN_out_ports_2_putNonFullVCs or
out_ports_2_putNonFullVCs_nonFullVCs or
EN_out_ports_3_putNonFullVCs or
out_ports_3_putNonFullVCs_nonFullVCs)
begin
case (outPortFIFOs_1_1$first)
3'd0:
IF_outPortFIFOs_1_1_first__71_EQ_0_72_THEN_sim_ETC___d1026 =
EN_out_ports_0_putNonFullVCs &&
out_ports_0_putNonFullVCs_nonFullVCs[1];
3'd1:
IF_outPortFIFOs_1_1_first__71_EQ_0_72_THEN_sim_ETC___d1026 =
EN_out_ports_1_putNonFullVCs &&
out_ports_1_putNonFullVCs_nonFullVCs[1];
3'd2:
IF_outPortFIFOs_1_1_first__71_EQ_0_72_THEN_sim_ETC___d1026 =
EN_out_ports_2_putNonFullVCs &&
out_ports_2_putNonFullVCs_nonFullVCs[1];
3'd3:
IF_outPortFIFOs_1_1_first__71_EQ_0_72_THEN_sim_ETC___d1026 =
EN_out_ports_3_putNonFullVCs &&
out_ports_3_putNonFullVCs_nonFullVCs[1];
default: IF_outPortFIFOs_1_1_first__71_EQ_0_72_THEN_sim_ETC___d1026 =
EN_out_ports_4_putNonFullVCs &&
out_ports_4_putNonFullVCs_nonFullVCs[1];
endcase
end
always@(outPortFIFOs_0_1$first or
EN_out_ports_4_putNonFullVCs or
out_ports_4_putNonFullVCs_nonFullVCs or
EN_out_ports_0_putNonFullVCs or
out_ports_0_putNonFullVCs_nonFullVCs or
EN_out_ports_1_putNonFullVCs or
out_ports_1_putNonFullVCs_nonFullVCs or
EN_out_ports_2_putNonFullVCs or
out_ports_2_putNonFullVCs_nonFullVCs or
EN_out_ports_3_putNonFullVCs or
out_ports_3_putNonFullVCs_nonFullVCs)
begin
case (outPortFIFOs_0_1$first)
3'd0:
IF_outPortFIFOs_0_1_first__12_EQ_0_13_THEN_sim_ETC___d1033 =
EN_out_ports_0_putNonFullVCs &&
out_ports_0_putNonFullVCs_nonFullVCs[1];
3'd1:
IF_outPortFIFOs_0_1_first__12_EQ_0_13_THEN_sim_ETC___d1033 =
EN_out_ports_1_putNonFullVCs &&
out_ports_1_putNonFullVCs_nonFullVCs[1];
3'd2:
IF_outPortFIFOs_0_1_first__12_EQ_0_13_THEN_sim_ETC___d1033 =
EN_out_ports_2_putNonFullVCs &&
out_ports_2_putNonFullVCs_nonFullVCs[1];
3'd3:
IF_outPortFIFOs_0_1_first__12_EQ_0_13_THEN_sim_ETC___d1033 =
EN_out_ports_3_putNonFullVCs &&
out_ports_3_putNonFullVCs_nonFullVCs[1];
default: IF_outPortFIFOs_0_1_first__12_EQ_0_13_THEN_sim_ETC___d1033 =
EN_out_ports_4_putNonFullVCs &&
out_ports_4_putNonFullVCs_nonFullVCs[1];
endcase
end
always@(outPortFIFOs_1$first or
EN_out_ports_4_putNonFullVCs or
out_ports_4_putNonFullVCs_nonFullVCs or
EN_out_ports_0_putNonFullVCs or
out_ports_0_putNonFullVCs_nonFullVCs or
EN_out_ports_1_putNonFullVCs or
out_ports_1_putNonFullVCs_nonFullVCs or
EN_out_ports_2_putNonFullVCs or
out_ports_2_putNonFullVCs_nonFullVCs or
EN_out_ports_3_putNonFullVCs or
out_ports_3_putNonFullVCs_nonFullVCs)
begin
case (outPortFIFOs_1$first)
3'd0:
IF_outPortFIFOs_1_first__57_EQ_0_58_THEN_simpl_ETC___d950 =
EN_out_ports_0_putNonFullVCs &&
out_ports_0_putNonFullVCs_nonFullVCs[0];
3'd1:
IF_outPortFIFOs_1_first__57_EQ_0_58_THEN_simpl_ETC___d950 =
EN_out_ports_1_putNonFullVCs &&
out_ports_1_putNonFullVCs_nonFullVCs[0];
3'd2:
IF_outPortFIFOs_1_first__57_EQ_0_58_THEN_simpl_ETC___d950 =
EN_out_ports_2_putNonFullVCs &&
out_ports_2_putNonFullVCs_nonFullVCs[0];
3'd3:
IF_outPortFIFOs_1_first__57_EQ_0_58_THEN_simpl_ETC___d950 =
EN_out_ports_3_putNonFullVCs &&
out_ports_3_putNonFullVCs_nonFullVCs[0];
default: IF_outPortFIFOs_1_first__57_EQ_0_58_THEN_simpl_ETC___d950 =
EN_out_ports_4_putNonFullVCs &&
out_ports_4_putNonFullVCs_nonFullVCs[0];
endcase
end
always@(outPortFIFOs_0$first or
EN_out_ports_4_putNonFullVCs or
out_ports_4_putNonFullVCs_nonFullVCs or
EN_out_ports_0_putNonFullVCs or
out_ports_0_putNonFullVCs_nonFullVCs or
EN_out_ports_1_putNonFullVCs or
out_ports_1_putNonFullVCs_nonFullVCs or
EN_out_ports_2_putNonFullVCs or
out_ports_2_putNonFullVCs_nonFullVCs or
EN_out_ports_3_putNonFullVCs or
out_ports_3_putNonFullVCs_nonFullVCs)
begin
case (outPortFIFOs_0$first)
3'd0:
IF_outPortFIFOs_0_first__98_EQ_0_99_THEN_simpl_ETC___d952 =
EN_out_ports_0_putNonFullVCs &&
out_ports_0_putNonFullVCs_nonFullVCs[0];
3'd1:
IF_outPortFIFOs_0_first__98_EQ_0_99_THEN_simpl_ETC___d952 =
EN_out_ports_1_putNonFullVCs &&
out_ports_1_putNonFullVCs_nonFullVCs[0];
3'd2:
IF_outPortFIFOs_0_first__98_EQ_0_99_THEN_simpl_ETC___d952 =
EN_out_ports_2_putNonFullVCs &&
out_ports_2_putNonFullVCs_nonFullVCs[0];
3'd3:
IF_outPortFIFOs_0_first__98_EQ_0_99_THEN_simpl_ETC___d952 =
EN_out_ports_3_putNonFullVCs &&
out_ports_3_putNonFullVCs_nonFullVCs[0];
default: IF_outPortFIFOs_0_first__98_EQ_0_99_THEN_simpl_ETC___d952 =
EN_out_ports_4_putNonFullVCs &&
out_ports_4_putNonFullVCs_nonFullVCs[0];
endcase
end
always@(active_in__h48706 or
outport_encoder___d1113 or
hasFlitsToSend_perIn_4$wget or
outport_encoder___d1117 or
hasFlitsToSend_perIn$wget or
outport_encoder___d1116 or
hasFlitsToSend_perIn_1$wget or
outport_encoder___d1115 or
hasFlitsToSend_perIn_2$wget or
outport_encoder___d1114 or hasFlitsToSend_perIn_3$wget)
begin
case (active_in__h48706)
3'd0:
IF_IF_outport_encoder_37_BIT_3_38_THEN_IF_outp_ETC___d671 =
outport_encoder___d1117[3] && hasFlitsToSend_perIn$wget[70];
3'd1:
IF_IF_outport_encoder_37_BIT_3_38_THEN_IF_outp_ETC___d671 =
outport_encoder___d1116[3] && hasFlitsToSend_perIn_1$wget[70];
3'd2:
IF_IF_outport_encoder_37_BIT_3_38_THEN_IF_outp_ETC___d671 =
outport_encoder___d1115[3] && hasFlitsToSend_perIn_2$wget[70];
3'd3:
IF_IF_outport_encoder_37_BIT_3_38_THEN_IF_outp_ETC___d671 =
outport_encoder___d1114[3] && hasFlitsToSend_perIn_3$wget[70];
default: IF_IF_outport_encoder_37_BIT_3_38_THEN_IF_outp_ETC___d671 =
active_in__h48706 != 3'd4 ||
outport_encoder___d1113[3] &&
hasFlitsToSend_perIn_4$wget[70];
endcase
end
always@(active_in__h50467 or
outport_encoder___d1113 or
hasFlitsToSend_perIn_4$wget or
outport_encoder___d1117 or
hasFlitsToSend_perIn$wget or
outport_encoder___d1116 or
hasFlitsToSend_perIn_1$wget or
outport_encoder___d1115 or
hasFlitsToSend_perIn_2$wget or
outport_encoder___d1114 or hasFlitsToSend_perIn_3$wget)
begin
case (active_in__h50467)
3'd0:
IF_IF_outport_encoder_37_BIT_3_38_THEN_IF_outp_ETC___d735 =
outport_encoder___d1117[3] && hasFlitsToSend_perIn$wget[70];
3'd1:
IF_IF_outport_encoder_37_BIT_3_38_THEN_IF_outp_ETC___d735 =
outport_encoder___d1116[3] && hasFlitsToSend_perIn_1$wget[70];
3'd2:
IF_IF_outport_encoder_37_BIT_3_38_THEN_IF_outp_ETC___d735 =
outport_encoder___d1115[3] && hasFlitsToSend_perIn_2$wget[70];
3'd3:
IF_IF_outport_encoder_37_BIT_3_38_THEN_IF_outp_ETC___d735 =
outport_encoder___d1114[3] && hasFlitsToSend_perIn_3$wget[70];
default: IF_IF_outport_encoder_37_BIT_3_38_THEN_IF_outp_ETC___d735 =
active_in__h50467 != 3'd4 ||
outport_encoder___d1113[3] &&
hasFlitsToSend_perIn_4$wget[70];
endcase
end
always@(active_in__h52228 or
outport_encoder___d1113 or
hasFlitsToSend_perIn_4$wget or
outport_encoder___d1117 or
hasFlitsToSend_perIn$wget or
outport_encoder___d1116 or
hasFlitsToSend_perIn_1$wget or
outport_encoder___d1115 or
hasFlitsToSend_perIn_2$wget or
outport_encoder___d1114 or hasFlitsToSend_perIn_3$wget)
begin
case (active_in__h52228)
3'd0:
IF_IF_outport_encoder_37_BIT_3_38_THEN_IF_outp_ETC___d799 =
outport_encoder___d1117[3] && hasFlitsToSend_perIn$wget[70];
3'd1:
IF_IF_outport_encoder_37_BIT_3_38_THEN_IF_outp_ETC___d799 =
outport_encoder___d1116[3] && hasFlitsToSend_perIn_1$wget[70];
3'd2:
IF_IF_outport_encoder_37_BIT_3_38_THEN_IF_outp_ETC___d799 =
outport_encoder___d1115[3] && hasFlitsToSend_perIn_2$wget[70];
3'd3:
IF_IF_outport_encoder_37_BIT_3_38_THEN_IF_outp_ETC___d799 =
outport_encoder___d1114[3] && hasFlitsToSend_perIn_3$wget[70];
default: IF_IF_outport_encoder_37_BIT_3_38_THEN_IF_outp_ETC___d799 =
active_in__h52228 != 3'd4 ||
outport_encoder___d1113[3] &&
hasFlitsToSend_perIn_4$wget[70];
endcase
end
always@(active_in__h53989 or
outport_encoder___d1113 or
hasFlitsToSend_perIn_4$wget or
outport_encoder___d1117 or
hasFlitsToSend_perIn$wget or
outport_encoder___d1116 or
hasFlitsToSend_perIn_1$wget or
outport_encoder___d1115 or
hasFlitsToSend_perIn_2$wget or
outport_encoder___d1114 or hasFlitsToSend_perIn_3$wget)
begin
case (active_in__h53989)
3'd0:
IF_IF_outport_encoder_37_BIT_3_38_THEN_IF_outp_ETC___d863 =
outport_encoder___d1117[3] && hasFlitsToSend_perIn$wget[70];
3'd1:
IF_IF_outport_encoder_37_BIT_3_38_THEN_IF_outp_ETC___d863 =
outport_encoder___d1116[3] && hasFlitsToSend_perIn_1$wget[70];
3'd2:
IF_IF_outport_encoder_37_BIT_3_38_THEN_IF_outp_ETC___d863 =
outport_encoder___d1115[3] && hasFlitsToSend_perIn_2$wget[70];
3'd3:
IF_IF_outport_encoder_37_BIT_3_38_THEN_IF_outp_ETC___d863 =
outport_encoder___d1114[3] && hasFlitsToSend_perIn_3$wget[70];
default: IF_IF_outport_encoder_37_BIT_3_38_THEN_IF_outp_ETC___d863 =
active_in__h53989 != 3'd4 ||
outport_encoder___d1113[3] &&
hasFlitsToSend_perIn_4$wget[70];
endcase
end
always@(active_in__h48706 or
outport_encoder___d1113 or
hasFlitsToSend_perIn_4$wget or
outport_encoder___d1117 or
hasFlitsToSend_perIn$wget or
outport_encoder___d1116 or
hasFlitsToSend_perIn_1$wget or
outport_encoder___d1115 or
hasFlitsToSend_perIn_2$wget or
outport_encoder___d1114 or hasFlitsToSend_perIn_3$wget)
begin
case (active_in__h48706)
3'd0:
IF_IF_outport_encoder_37_BIT_3_38_THEN_IF_outp_ETC___d1172 =
!outport_encoder___d1117[3] || !hasFlitsToSend_perIn$wget[70];
3'd1:
IF_IF_outport_encoder_37_BIT_3_38_THEN_IF_outp_ETC___d1172 =
!outport_encoder___d1116[3] || !hasFlitsToSend_perIn_1$wget[70];
3'd2:
IF_IF_outport_encoder_37_BIT_3_38_THEN_IF_outp_ETC___d1172 =
!outport_encoder___d1115[3] || !hasFlitsToSend_perIn_2$wget[70];
3'd3:
IF_IF_outport_encoder_37_BIT_3_38_THEN_IF_outp_ETC___d1172 =
!outport_encoder___d1114[3] || !hasFlitsToSend_perIn_3$wget[70];
default: IF_IF_outport_encoder_37_BIT_3_38_THEN_IF_outp_ETC___d1172 =
active_in__h48706 == 3'd4 &&
(!outport_encoder___d1113[3] ||
!hasFlitsToSend_perIn_4$wget[70]);
endcase
end
always@(active_in__h50467 or
outport_encoder___d1113 or
hasFlitsToSend_perIn_4$wget or
outport_encoder___d1117 or
hasFlitsToSend_perIn$wget or
outport_encoder___d1116 or
hasFlitsToSend_perIn_1$wget or
outport_encoder___d1115 or
hasFlitsToSend_perIn_2$wget or
outport_encoder___d1114 or hasFlitsToSend_perIn_3$wget)
begin
case (active_in__h50467)
3'd0:
IF_IF_outport_encoder_37_BIT_3_38_THEN_IF_outp_ETC___d1173 =
!outport_encoder___d1117[3] || !hasFlitsToSend_perIn$wget[70];
3'd1:
IF_IF_outport_encoder_37_BIT_3_38_THEN_IF_outp_ETC___d1173 =
!outport_encoder___d1116[3] || !hasFlitsToSend_perIn_1$wget[70];
3'd2:
IF_IF_outport_encoder_37_BIT_3_38_THEN_IF_outp_ETC___d1173 =
!outport_encoder___d1115[3] || !hasFlitsToSend_perIn_2$wget[70];
3'd3:
IF_IF_outport_encoder_37_BIT_3_38_THEN_IF_outp_ETC___d1173 =
!outport_encoder___d1114[3] || !hasFlitsToSend_perIn_3$wget[70];
default: IF_IF_outport_encoder_37_BIT_3_38_THEN_IF_outp_ETC___d1173 =
active_in__h50467 == 3'd4 &&
(!outport_encoder___d1113[3] ||
!hasFlitsToSend_perIn_4$wget[70]);
endcase
end
always@(active_in__h52228 or
outport_encoder___d1113 or
hasFlitsToSend_perIn_4$wget or
outport_encoder___d1117 or
hasFlitsToSend_perIn$wget or
outport_encoder___d1116 or
hasFlitsToSend_perIn_1$wget or
outport_encoder___d1115 or
hasFlitsToSend_perIn_2$wget or
outport_encoder___d1114 or hasFlitsToSend_perIn_3$wget)
begin
case (active_in__h52228)
3'd0:
IF_IF_outport_encoder_37_BIT_3_38_THEN_IF_outp_ETC___d1174 =
!outport_encoder___d1117[3] || !hasFlitsToSend_perIn$wget[70];
3'd1:
IF_IF_outport_encoder_37_BIT_3_38_THEN_IF_outp_ETC___d1174 =
!outport_encoder___d1116[3] || !hasFlitsToSend_perIn_1$wget[70];
3'd2:
IF_IF_outport_encoder_37_BIT_3_38_THEN_IF_outp_ETC___d1174 =
!outport_encoder___d1115[3] || !hasFlitsToSend_perIn_2$wget[70];
3'd3:
IF_IF_outport_encoder_37_BIT_3_38_THEN_IF_outp_ETC___d1174 =
!outport_encoder___d1114[3] || !hasFlitsToSend_perIn_3$wget[70];
default: IF_IF_outport_encoder_37_BIT_3_38_THEN_IF_outp_ETC___d1174 =
active_in__h52228 == 3'd4 &&
(!outport_encoder___d1113[3] ||
!hasFlitsToSend_perIn_4$wget[70]);
endcase
end
always@(active_in__h53989 or
outport_encoder___d1113 or
hasFlitsToSend_perIn_4$wget or
outport_encoder___d1117 or
hasFlitsToSend_perIn$wget or
outport_encoder___d1116 or
hasFlitsToSend_perIn_1$wget or
outport_encoder___d1115 or
hasFlitsToSend_perIn_2$wget or
outport_encoder___d1114 or hasFlitsToSend_perIn_3$wget)
begin
case (active_in__h53989)
3'd0:
IF_IF_outport_encoder_37_BIT_3_38_THEN_IF_outp_ETC___d1175 =
!outport_encoder___d1117[3] || !hasFlitsToSend_perIn$wget[70];
3'd1:
IF_IF_outport_encoder_37_BIT_3_38_THEN_IF_outp_ETC___d1175 =
!outport_encoder___d1116[3] || !hasFlitsToSend_perIn_1$wget[70];
3'd2:
IF_IF_outport_encoder_37_BIT_3_38_THEN_IF_outp_ETC___d1175 =
!outport_encoder___d1115[3] || !hasFlitsToSend_perIn_2$wget[70];
3'd3:
IF_IF_outport_encoder_37_BIT_3_38_THEN_IF_outp_ETC___d1175 =
!outport_encoder___d1114[3] || !hasFlitsToSend_perIn_3$wget[70];
default: IF_IF_outport_encoder_37_BIT_3_38_THEN_IF_outp_ETC___d1175 =
active_in__h53989 == 3'd4 &&
(!outport_encoder___d1113[3] ||
!hasFlitsToSend_perIn_4$wget[70]);
endcase
end
always@(active_in__h48706 or
hasFlitsToSend_perIn_4$wget or
hasFlitsToSend_perIn$wget or
hasFlitsToSend_perIn_1$wget or
hasFlitsToSend_perIn_2$wget or hasFlitsToSend_perIn_3$wget)
begin
case (active_in__h48706)
3'd0:
IF_IF_outport_encoder_37_BIT_3_38_THEN_IF_outp_ETC___d1162 =
hasFlitsToSend_perIn$wget[69:0];
3'd1:
IF_IF_outport_encoder_37_BIT_3_38_THEN_IF_outp_ETC___d1162 =
hasFlitsToSend_perIn_1$wget[69:0];
3'd2:
IF_IF_outport_encoder_37_BIT_3_38_THEN_IF_outp_ETC___d1162 =
hasFlitsToSend_perIn_2$wget[69:0];
3'd3:
IF_IF_outport_encoder_37_BIT_3_38_THEN_IF_outp_ETC___d1162 =
hasFlitsToSend_perIn_3$wget[69:0];
3'd4:
IF_IF_outport_encoder_37_BIT_3_38_THEN_IF_outp_ETC___d1162 =
hasFlitsToSend_perIn_4$wget[69:0];
default: IF_IF_outport_encoder_37_BIT_3_38_THEN_IF_outp_ETC___d1162 =
hasFlitsToSend_perIn_4$wget[69:0];
endcase
end
always@(active_in__h50467 or
hasFlitsToSend_perIn_4$wget or
hasFlitsToSend_perIn$wget or
hasFlitsToSend_perIn_1$wget or
hasFlitsToSend_perIn_2$wget or hasFlitsToSend_perIn_3$wget)
begin
case (active_in__h50467)
3'd0:
IF_IF_outport_encoder_37_BIT_3_38_THEN_IF_outp_ETC___d1163 =
hasFlitsToSend_perIn$wget[69:0];
3'd1:
IF_IF_outport_encoder_37_BIT_3_38_THEN_IF_outp_ETC___d1163 =
hasFlitsToSend_perIn_1$wget[69:0];
3'd2:
IF_IF_outport_encoder_37_BIT_3_38_THEN_IF_outp_ETC___d1163 =
hasFlitsToSend_perIn_2$wget[69:0];
3'd3:
IF_IF_outport_encoder_37_BIT_3_38_THEN_IF_outp_ETC___d1163 =
hasFlitsToSend_perIn_3$wget[69:0];
3'd4:
IF_IF_outport_encoder_37_BIT_3_38_THEN_IF_outp_ETC___d1163 =
hasFlitsToSend_perIn_4$wget[69:0];
default: IF_IF_outport_encoder_37_BIT_3_38_THEN_IF_outp_ETC___d1163 =
hasFlitsToSend_perIn_4$wget[69:0];
endcase
end
always@(active_in__h52228 or
hasFlitsToSend_perIn_4$wget or
hasFlitsToSend_perIn$wget or
hasFlitsToSend_perIn_1$wget or
hasFlitsToSend_perIn_2$wget or hasFlitsToSend_perIn_3$wget)
begin
case (active_in__h52228)
3'd0:
IF_IF_outport_encoder_37_BIT_3_38_THEN_IF_outp_ETC___d1164 =
hasFlitsToSend_perIn$wget[69:0];
3'd1:
IF_IF_outport_encoder_37_BIT_3_38_THEN_IF_outp_ETC___d1164 =
hasFlitsToSend_perIn_1$wget[69:0];
3'd2:
IF_IF_outport_encoder_37_BIT_3_38_THEN_IF_outp_ETC___d1164 =
hasFlitsToSend_perIn_2$wget[69:0];
3'd3:
IF_IF_outport_encoder_37_BIT_3_38_THEN_IF_outp_ETC___d1164 =
hasFlitsToSend_perIn_3$wget[69:0];
3'd4:
IF_IF_outport_encoder_37_BIT_3_38_THEN_IF_outp_ETC___d1164 =
hasFlitsToSend_perIn_4$wget[69:0];
default: IF_IF_outport_encoder_37_BIT_3_38_THEN_IF_outp_ETC___d1164 =
hasFlitsToSend_perIn_4$wget[69:0];
endcase
end
always@(active_in__h53989 or
hasFlitsToSend_perIn_4$wget or
hasFlitsToSend_perIn$wget or
hasFlitsToSend_perIn_1$wget or
hasFlitsToSend_perIn_2$wget or hasFlitsToSend_perIn_3$wget)
begin
case (active_in__h53989)
3'd0:
IF_IF_outport_encoder_37_BIT_3_38_THEN_IF_outp_ETC___d1165 =
hasFlitsToSend_perIn$wget[69:0];
3'd1:
IF_IF_outport_encoder_37_BIT_3_38_THEN_IF_outp_ETC___d1165 =
hasFlitsToSend_perIn_1$wget[69:0];
3'd2:
IF_IF_outport_encoder_37_BIT_3_38_THEN_IF_outp_ETC___d1165 =
hasFlitsToSend_perIn_2$wget[69:0];
3'd3:
IF_IF_outport_encoder_37_BIT_3_38_THEN_IF_outp_ETC___d1165 =
hasFlitsToSend_perIn_3$wget[69:0];
3'd4:
IF_IF_outport_encoder_37_BIT_3_38_THEN_IF_outp_ETC___d1165 =
hasFlitsToSend_perIn_4$wget[69:0];
default: IF_IF_outport_encoder_37_BIT_3_38_THEN_IF_outp_ETC___d1165 =
hasFlitsToSend_perIn_4$wget[69:0];
endcase
end
// handling of inlined registers
always@(posedge CLK)
begin
if (!RST_N)
begin
activeVC_perIn_reg <= `BSV_ASSIGNMENT_DELAY
{ 1'd0, 1'bx /* unspecified value */ };
activeVC_perIn_reg_1 <= `BSV_ASSIGNMENT_DELAY
{ 1'd0, 1'bx /* unspecified value */ };
activeVC_perIn_reg_2 <= `BSV_ASSIGNMENT_DELAY
{ 1'd0, 1'bx /* unspecified value */ };
activeVC_perIn_reg_3 <= `BSV_ASSIGNMENT_DELAY
{ 1'd0, 1'bx /* unspecified value */ };
activeVC_perIn_reg_4 <= `BSV_ASSIGNMENT_DELAY
{ 1'd0, 1'bx /* unspecified value */ };
inPortVL_0 <= `BSV_ASSIGNMENT_DELAY 3'd0;
inPortVL_0_1 <= `BSV_ASSIGNMENT_DELAY 3'd0;
inPortVL_1 <= `BSV_ASSIGNMENT_DELAY 3'd0;
inPortVL_1_1 <= `BSV_ASSIGNMENT_DELAY 3'd0;
inPortVL_2 <= `BSV_ASSIGNMENT_DELAY 3'd0;
inPortVL_2_1 <= `BSV_ASSIGNMENT_DELAY 3'd0;
inPortVL_3 <= `BSV_ASSIGNMENT_DELAY 3'd0;
inPortVL_3_1 <= `BSV_ASSIGNMENT_DELAY 3'd0;
inPortVL_4 <= `BSV_ASSIGNMENT_DELAY 3'd0;
inPortVL_4_1 <= `BSV_ASSIGNMENT_DELAY 3'd0;
lockedVL_0 <= `BSV_ASSIGNMENT_DELAY 1'd0;
lockedVL_0_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
lockedVL_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
lockedVL_1_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
lockedVL_2 <= `BSV_ASSIGNMENT_DELAY 1'd0;
lockedVL_2_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
lockedVL_3 <= `BSV_ASSIGNMENT_DELAY 1'd0;
lockedVL_3_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
lockedVL_4 <= `BSV_ASSIGNMENT_DELAY 1'd0;
lockedVL_4_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
selectedIO_reg_0 <= `BSV_ASSIGNMENT_DELAY 1'd0;
selectedIO_reg_0_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
selectedIO_reg_0_2 <= `BSV_ASSIGNMENT_DELAY 1'd0;
selectedIO_reg_0_3 <= `BSV_ASSIGNMENT_DELAY 1'd0;
selectedIO_reg_0_4 <= `BSV_ASSIGNMENT_DELAY 1'd0;
selectedIO_reg_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
selectedIO_reg_1_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
selectedIO_reg_1_2 <= `BSV_ASSIGNMENT_DELAY 1'd0;
selectedIO_reg_1_3 <= `BSV_ASSIGNMENT_DELAY 1'd0;
selectedIO_reg_1_4 <= `BSV_ASSIGNMENT_DELAY 1'd0;
selectedIO_reg_2 <= `BSV_ASSIGNMENT_DELAY 1'd0;
selectedIO_reg_2_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
selectedIO_reg_2_2 <= `BSV_ASSIGNMENT_DELAY 1'd0;
selectedIO_reg_2_3 <= `BSV_ASSIGNMENT_DELAY 1'd0;
selectedIO_reg_2_4 <= `BSV_ASSIGNMENT_DELAY 1'd0;
selectedIO_reg_3 <= `BSV_ASSIGNMENT_DELAY 1'd0;
selectedIO_reg_3_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
selectedIO_reg_3_2 <= `BSV_ASSIGNMENT_DELAY 1'd0;
selectedIO_reg_3_3 <= `BSV_ASSIGNMENT_DELAY 1'd0;
selectedIO_reg_3_4 <= `BSV_ASSIGNMENT_DELAY 1'd0;
selectedIO_reg_4 <= `BSV_ASSIGNMENT_DELAY 1'd0;
selectedIO_reg_4_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
selectedIO_reg_4_2 <= `BSV_ASSIGNMENT_DELAY 1'd0;
selectedIO_reg_4_3 <= `BSV_ASSIGNMENT_DELAY 1'd0;
selectedIO_reg_4_4 <= `BSV_ASSIGNMENT_DELAY 1'd0;
end
else
begin
if (activeVC_perIn_reg$EN)
activeVC_perIn_reg <= `BSV_ASSIGNMENT_DELAY activeVC_perIn_reg$D_IN;
if (activeVC_perIn_reg_1$EN)
activeVC_perIn_reg_1 <= `BSV_ASSIGNMENT_DELAY
activeVC_perIn_reg_1$D_IN;
if (activeVC_perIn_reg_2$EN)
activeVC_perIn_reg_2 <= `BSV_ASSIGNMENT_DELAY
activeVC_perIn_reg_2$D_IN;
if (activeVC_perIn_reg_3$EN)
activeVC_perIn_reg_3 <= `BSV_ASSIGNMENT_DELAY
activeVC_perIn_reg_3$D_IN;
if (activeVC_perIn_reg_4$EN)
activeVC_perIn_reg_4 <= `BSV_ASSIGNMENT_DELAY
activeVC_perIn_reg_4$D_IN;
if (inPortVL_0$EN)
inPortVL_0 <= `BSV_ASSIGNMENT_DELAY inPortVL_0$D_IN;
if (inPortVL_0_1$EN)
inPortVL_0_1 <= `BSV_ASSIGNMENT_DELAY inPortVL_0_1$D_IN;
if (inPortVL_1$EN)
inPortVL_1 <= `BSV_ASSIGNMENT_DELAY inPortVL_1$D_IN;
if (inPortVL_1_1$EN)
inPortVL_1_1 <= `BSV_ASSIGNMENT_DELAY inPortVL_1_1$D_IN;
if (inPortVL_2$EN)
inPortVL_2 <= `BSV_ASSIGNMENT_DELAY inPortVL_2$D_IN;
if (inPortVL_2_1$EN)
inPortVL_2_1 <= `BSV_ASSIGNMENT_DELAY inPortVL_2_1$D_IN;
if (inPortVL_3$EN)
inPortVL_3 <= `BSV_ASSIGNMENT_DELAY inPortVL_3$D_IN;
if (inPortVL_3_1$EN)
inPortVL_3_1 <= `BSV_ASSIGNMENT_DELAY inPortVL_3_1$D_IN;
if (inPortVL_4$EN)
inPortVL_4 <= `BSV_ASSIGNMENT_DELAY inPortVL_4$D_IN;
if (inPortVL_4_1$EN)
inPortVL_4_1 <= `BSV_ASSIGNMENT_DELAY inPortVL_4_1$D_IN;
if (lockedVL_0$EN)
lockedVL_0 <= `BSV_ASSIGNMENT_DELAY lockedVL_0$D_IN;
if (lockedVL_0_1$EN)
lockedVL_0_1 <= `BSV_ASSIGNMENT_DELAY lockedVL_0_1$D_IN;
if (lockedVL_1$EN)
lockedVL_1 <= `BSV_ASSIGNMENT_DELAY lockedVL_1$D_IN;
if (lockedVL_1_1$EN)
lockedVL_1_1 <= `BSV_ASSIGNMENT_DELAY lockedVL_1_1$D_IN;
if (lockedVL_2$EN)
lockedVL_2 <= `BSV_ASSIGNMENT_DELAY lockedVL_2$D_IN;
if (lockedVL_2_1$EN)
lockedVL_2_1 <= `BSV_ASSIGNMENT_DELAY lockedVL_2_1$D_IN;
if (lockedVL_3$EN)
lockedVL_3 <= `BSV_ASSIGNMENT_DELAY lockedVL_3$D_IN;
if (lockedVL_3_1$EN)
lockedVL_3_1 <= `BSV_ASSIGNMENT_DELAY lockedVL_3_1$D_IN;
if (lockedVL_4$EN)
lockedVL_4 <= `BSV_ASSIGNMENT_DELAY lockedVL_4$D_IN;
if (lockedVL_4_1$EN)
lockedVL_4_1 <= `BSV_ASSIGNMENT_DELAY lockedVL_4_1$D_IN;
if (selectedIO_reg_0$EN)
selectedIO_reg_0 <= `BSV_ASSIGNMENT_DELAY selectedIO_reg_0$D_IN;
if (selectedIO_reg_0_1$EN)
selectedIO_reg_0_1 <= `BSV_ASSIGNMENT_DELAY selectedIO_reg_0_1$D_IN;
if (selectedIO_reg_0_2$EN)
selectedIO_reg_0_2 <= `BSV_ASSIGNMENT_DELAY selectedIO_reg_0_2$D_IN;
if (selectedIO_reg_0_3$EN)
selectedIO_reg_0_3 <= `BSV_ASSIGNMENT_DELAY selectedIO_reg_0_3$D_IN;
if (selectedIO_reg_0_4$EN)
selectedIO_reg_0_4 <= `BSV_ASSIGNMENT_DELAY selectedIO_reg_0_4$D_IN;
if (selectedIO_reg_1$EN)
selectedIO_reg_1 <= `BSV_ASSIGNMENT_DELAY selectedIO_reg_1$D_IN;
if (selectedIO_reg_1_1$EN)
selectedIO_reg_1_1 <= `BSV_ASSIGNMENT_DELAY selectedIO_reg_1_1$D_IN;
if (selectedIO_reg_1_2$EN)
selectedIO_reg_1_2 <= `BSV_ASSIGNMENT_DELAY selectedIO_reg_1_2$D_IN;
if (selectedIO_reg_1_3$EN)
selectedIO_reg_1_3 <= `BSV_ASSIGNMENT_DELAY selectedIO_reg_1_3$D_IN;
if (selectedIO_reg_1_4$EN)
selectedIO_reg_1_4 <= `BSV_ASSIGNMENT_DELAY selectedIO_reg_1_4$D_IN;
if (selectedIO_reg_2$EN)
selectedIO_reg_2 <= `BSV_ASSIGNMENT_DELAY selectedIO_reg_2$D_IN;
if (selectedIO_reg_2_1$EN)
selectedIO_reg_2_1 <= `BSV_ASSIGNMENT_DELAY selectedIO_reg_2_1$D_IN;
if (selectedIO_reg_2_2$EN)
selectedIO_reg_2_2 <= `BSV_ASSIGNMENT_DELAY selectedIO_reg_2_2$D_IN;
if (selectedIO_reg_2_3$EN)
selectedIO_reg_2_3 <= `BSV_ASSIGNMENT_DELAY selectedIO_reg_2_3$D_IN;
if (selectedIO_reg_2_4$EN)
selectedIO_reg_2_4 <= `BSV_ASSIGNMENT_DELAY selectedIO_reg_2_4$D_IN;
if (selectedIO_reg_3$EN)
selectedIO_reg_3 <= `BSV_ASSIGNMENT_DELAY selectedIO_reg_3$D_IN;
if (selectedIO_reg_3_1$EN)
selectedIO_reg_3_1 <= `BSV_ASSIGNMENT_DELAY selectedIO_reg_3_1$D_IN;
if (selectedIO_reg_3_2$EN)
selectedIO_reg_3_2 <= `BSV_ASSIGNMENT_DELAY selectedIO_reg_3_2$D_IN;
if (selectedIO_reg_3_3$EN)
selectedIO_reg_3_3 <= `BSV_ASSIGNMENT_DELAY selectedIO_reg_3_3$D_IN;
if (selectedIO_reg_3_4$EN)
selectedIO_reg_3_4 <= `BSV_ASSIGNMENT_DELAY selectedIO_reg_3_4$D_IN;
if (selectedIO_reg_4$EN)
selectedIO_reg_4 <= `BSV_ASSIGNMENT_DELAY selectedIO_reg_4$D_IN;
if (selectedIO_reg_4_1$EN)
selectedIO_reg_4_1 <= `BSV_ASSIGNMENT_DELAY selectedIO_reg_4_1$D_IN;
if (selectedIO_reg_4_2$EN)
selectedIO_reg_4_2 <= `BSV_ASSIGNMENT_DELAY selectedIO_reg_4_2$D_IN;
if (selectedIO_reg_4_3$EN)
selectedIO_reg_4_3 <= `BSV_ASSIGNMENT_DELAY selectedIO_reg_4_3$D_IN;
if (selectedIO_reg_4_4$EN)
selectedIO_reg_4_4 <= `BSV_ASSIGNMENT_DELAY selectedIO_reg_4_4$D_IN;
end
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
activeVC_perIn_reg = 2'h2;
activeVC_perIn_reg_1 = 2'h2;
activeVC_perIn_reg_2 = 2'h2;
activeVC_perIn_reg_3 = 2'h2;
activeVC_perIn_reg_4 = 2'h2;
inPortVL_0 = 3'h2;
inPortVL_0_1 = 3'h2;
inPortVL_1 = 3'h2;
inPortVL_1_1 = 3'h2;
inPortVL_2 = 3'h2;
inPortVL_2_1 = 3'h2;
inPortVL_3 = 3'h2;
inPortVL_3_1 = 3'h2;
inPortVL_4 = 3'h2;
inPortVL_4_1 = 3'h2;
lockedVL_0 = 1'h0;
lockedVL_0_1 = 1'h0;
lockedVL_1 = 1'h0;
lockedVL_1_1 = 1'h0;
lockedVL_2 = 1'h0;
lockedVL_2_1 = 1'h0;
lockedVL_3 = 1'h0;
lockedVL_3_1 = 1'h0;
lockedVL_4 = 1'h0;
lockedVL_4_1 = 1'h0;
selectedIO_reg_0 = 1'h0;
selectedIO_reg_0_1 = 1'h0;
selectedIO_reg_0_2 = 1'h0;
selectedIO_reg_0_3 = 1'h0;
selectedIO_reg_0_4 = 1'h0;
selectedIO_reg_1 = 1'h0;
selectedIO_reg_1_1 = 1'h0;
selectedIO_reg_1_2 = 1'h0;
selectedIO_reg_1_3 = 1'h0;
selectedIO_reg_1_4 = 1'h0;
selectedIO_reg_2 = 1'h0;
selectedIO_reg_2_1 = 1'h0;
selectedIO_reg_2_2 = 1'h0;
selectedIO_reg_2_3 = 1'h0;
selectedIO_reg_2_4 = 1'h0;
selectedIO_reg_3 = 1'h0;
selectedIO_reg_3_1 = 1'h0;
selectedIO_reg_3_2 = 1'h0;
selectedIO_reg_3_3 = 1'h0;
selectedIO_reg_3_4 = 1'h0;
selectedIO_reg_4 = 1'h0;
selectedIO_reg_4_1 = 1'h0;
selectedIO_reg_4_2 = 1'h0;
selectedIO_reg_4_3 = 1'h0;
selectedIO_reg_4_4 = 1'h0;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge CLK)
begin
#0;
if (RST_N) if (EN_out_ports_0_putNonFullVCs) $write("");
if (RST_N) if (EN_out_ports_0_putNonFullVCs) $write("");
if (RST_N) if (EN_out_ports_1_putNonFullVCs) $write("");
if (RST_N) if (EN_out_ports_1_putNonFullVCs) $write("");
if (RST_N) if (EN_out_ports_2_putNonFullVCs) $write("");
if (RST_N) if (EN_out_ports_2_putNonFullVCs) $write("");
if (RST_N) if (EN_out_ports_3_putNonFullVCs) $write("");
if (RST_N) if (EN_out_ports_3_putNonFullVCs) $write("");
if (RST_N) if (EN_out_ports_4_putNonFullVCs) $write("");
if (RST_N) if (EN_out_ports_4_putNonFullVCs) $write("");
if (RST_N)
if (outport_encoder___d1117[3] &&
flitBuffers$deq[64] != fifo_out__h36476)
$write("");
if (RST_N)
if (outport_encoder___d1116[3] &&
flitBuffers_1$deq[64] != fifo_out__h37661)
$write("");
if (RST_N)
if (outport_encoder___d1115[3] &&
flitBuffers_2$deq[64] != fifo_out__h38207)
$write("");
if (RST_N)
if (outport_encoder___d1114[3] &&
flitBuffers_3$deq[64] != fifo_out__h38753)
$write("");
if (RST_N)
if (outport_encoder___d1113[3] &&
flitBuffers_4$deq[64] != fifo_out__h39299)
$write("");
if (RST_N)
if (EN_out_ports_0_getFlit &&
IF_outport_encoder_37_BIT_3_38_THEN_outport_en_ETC___d1046 &&
(outport_encoder___d1113[3] ?
outport_encoder___d1113[2:0] != 3'd0 &&
IF_outport_encoder_02_BIT_3_03_THEN_NOT_outpor_ETC___d1105 :
IF_outport_encoder_02_BIT_3_03_THEN_NOT_outpor_ETC___d1105))
$write("");
if (RST_N)
if (EN_out_ports_0_getFlit &&
IF_outport_encoder_37_BIT_3_38_THEN_outport_en_ETC___d1046 &&
IF_IF_outport_encoder_37_BIT_3_38_THEN_NOT_out_ETC___d1171)
$display("Dynamic assertion failed: \"RouterSimple.bsv\", line 759, column 47\nOutput selected invalid flit!");
if (RST_N)
if (EN_out_ports_0_getFlit &&
IF_outport_encoder_37_BIT_3_38_THEN_outport_en_ETC___d1046 &&
IF_IF_outport_encoder_37_BIT_3_38_THEN_NOT_out_ETC___d1171)
$finish(32'd0);
if (RST_N)
if (EN_out_ports_0_getFlit &&
IF_outport_encoder_37_BIT_3_38_THEN_outport_en_ETC___d1046 &&
IF_IF_outport_encoder_37_BIT_3_38_THEN_NOT_out_ETC___d1171)
$display("Dynamic assertion failed: \"RouterSimple.bsv\", line 780, column 47\nAllocation selected input port with invalid flit!");
if (RST_N)
if (EN_out_ports_0_getFlit &&
IF_outport_encoder_37_BIT_3_38_THEN_outport_en_ETC___d1046 &&
IF_IF_outport_encoder_37_BIT_3_38_THEN_NOT_out_ETC___d1171)
$finish(32'd0);
if (RST_N)
if (EN_out_ports_1_getFlit &&
IF_outport_encoder_37_BIT_3_38_THEN_outport_en_ETC___d1056 &&
(outport_encoder___d1113[3] ?
outport_encoder___d1113[2:0] != 3'd1 &&
IF_outport_encoder_02_BIT_3_03_THEN_NOT_outpor_ETC___d1106 :
IF_outport_encoder_02_BIT_3_03_THEN_NOT_outpor_ETC___d1106))
$write("");
if (RST_N)
if (EN_out_ports_1_getFlit &&
IF_outport_encoder_37_BIT_3_38_THEN_outport_en_ETC___d1056 &&
IF_IF_outport_encoder_37_BIT_3_38_THEN_IF_outp_ETC___d1172)
$display("Dynamic assertion failed: \"RouterSimple.bsv\", line 759, column 47\nOutput selected invalid flit!");
if (RST_N)
if (EN_out_ports_1_getFlit &&
IF_outport_encoder_37_BIT_3_38_THEN_outport_en_ETC___d1056 &&
IF_IF_outport_encoder_37_BIT_3_38_THEN_IF_outp_ETC___d1172)
$finish(32'd0);
if (RST_N)
if (EN_out_ports_1_getFlit &&
IF_outport_encoder_37_BIT_3_38_THEN_outport_en_ETC___d1056 &&
IF_IF_outport_encoder_37_BIT_3_38_THEN_IF_outp_ETC___d1172)
$display("Dynamic assertion failed: \"RouterSimple.bsv\", line 780, column 47\nAllocation selected input port with invalid flit!");
if (RST_N)
if (EN_out_ports_1_getFlit &&
IF_outport_encoder_37_BIT_3_38_THEN_outport_en_ETC___d1056 &&
IF_IF_outport_encoder_37_BIT_3_38_THEN_IF_outp_ETC___d1172)
$finish(32'd0);
if (RST_N)
if (EN_out_ports_2_getFlit &&
IF_outport_encoder_37_BIT_3_38_THEN_outport_en_ETC___d1058 &&
(outport_encoder___d1113[3] ?
outport_encoder___d1113[2:0] != 3'd2 &&
IF_outport_encoder_02_BIT_3_03_THEN_NOT_outpor_ETC___d1107 :
IF_outport_encoder_02_BIT_3_03_THEN_NOT_outpor_ETC___d1107))
$write("");
if (RST_N)
if (EN_out_ports_2_getFlit &&
IF_outport_encoder_37_BIT_3_38_THEN_outport_en_ETC___d1058 &&
IF_IF_outport_encoder_37_BIT_3_38_THEN_IF_outp_ETC___d1173)
$display("Dynamic assertion failed: \"RouterSimple.bsv\", line 759, column 47\nOutput selected invalid flit!");
if (RST_N)
if (EN_out_ports_2_getFlit &&
IF_outport_encoder_37_BIT_3_38_THEN_outport_en_ETC___d1058 &&
IF_IF_outport_encoder_37_BIT_3_38_THEN_IF_outp_ETC___d1173)
$finish(32'd0);
if (RST_N)
if (EN_out_ports_2_getFlit &&
IF_outport_encoder_37_BIT_3_38_THEN_outport_en_ETC___d1058 &&
IF_IF_outport_encoder_37_BIT_3_38_THEN_IF_outp_ETC___d1173)
$display("Dynamic assertion failed: \"RouterSimple.bsv\", line 780, column 47\nAllocation selected input port with invalid flit!");
if (RST_N)
if (EN_out_ports_2_getFlit &&
IF_outport_encoder_37_BIT_3_38_THEN_outport_en_ETC___d1058 &&
IF_IF_outport_encoder_37_BIT_3_38_THEN_IF_outp_ETC___d1173)
$finish(32'd0);
if (RST_N)
if (EN_out_ports_3_getFlit &&
IF_outport_encoder_37_BIT_3_38_THEN_outport_en_ETC___d1060 &&
(outport_encoder___d1113[3] ?
outport_encoder___d1113[2:0] != 3'd3 &&
IF_outport_encoder_02_BIT_3_03_THEN_NOT_outpor_ETC___d1108 :
IF_outport_encoder_02_BIT_3_03_THEN_NOT_outpor_ETC___d1108))
$write("");
if (RST_N)
if (EN_out_ports_3_getFlit &&
IF_outport_encoder_37_BIT_3_38_THEN_outport_en_ETC___d1060 &&
IF_IF_outport_encoder_37_BIT_3_38_THEN_IF_outp_ETC___d1174)
$display("Dynamic assertion failed: \"RouterSimple.bsv\", line 759, column 47\nOutput selected invalid flit!");
if (RST_N)
if (EN_out_ports_3_getFlit &&
IF_outport_encoder_37_BIT_3_38_THEN_outport_en_ETC___d1060 &&
IF_IF_outport_encoder_37_BIT_3_38_THEN_IF_outp_ETC___d1174)
$finish(32'd0);
if (RST_N)
if (EN_out_ports_3_getFlit &&
IF_outport_encoder_37_BIT_3_38_THEN_outport_en_ETC___d1060 &&
IF_IF_outport_encoder_37_BIT_3_38_THEN_IF_outp_ETC___d1174)
$display("Dynamic assertion failed: \"RouterSimple.bsv\", line 780, column 47\nAllocation selected input port with invalid flit!");
if (RST_N)
if (EN_out_ports_3_getFlit &&
IF_outport_encoder_37_BIT_3_38_THEN_outport_en_ETC___d1060 &&
IF_IF_outport_encoder_37_BIT_3_38_THEN_IF_outp_ETC___d1174)
$finish(32'd0);
if (RST_N)
if (EN_out_ports_4_getFlit &&
IF_outport_encoder_37_BIT_3_38_THEN_outport_en_ETC___d1062 &&
(outport_encoder___d1113[3] ?
outport_encoder___d1113[2:0] != 3'd4 &&
IF_outport_encoder_02_BIT_3_03_THEN_NOT_outpor_ETC___d1109 :
IF_outport_encoder_02_BIT_3_03_THEN_NOT_outpor_ETC___d1109))
$write("");
if (RST_N)
if (EN_out_ports_4_getFlit &&
IF_outport_encoder_37_BIT_3_38_THEN_outport_en_ETC___d1062 &&
IF_IF_outport_encoder_37_BIT_3_38_THEN_IF_outp_ETC___d1175)
$display("Dynamic assertion failed: \"RouterSimple.bsv\", line 759, column 47\nOutput selected invalid flit!");
if (RST_N)
if (EN_out_ports_4_getFlit &&
IF_outport_encoder_37_BIT_3_38_THEN_outport_en_ETC___d1062 &&
IF_IF_outport_encoder_37_BIT_3_38_THEN_IF_outp_ETC___d1175)
$finish(32'd0);
if (RST_N)
if (EN_out_ports_4_getFlit &&
IF_outport_encoder_37_BIT_3_38_THEN_outport_en_ETC___d1062 &&
IF_IF_outport_encoder_37_BIT_3_38_THEN_IF_outp_ETC___d1175)
$display("Dynamic assertion failed: \"RouterSimple.bsv\", line 780, column 47\nAllocation selected input port with invalid flit!");
if (RST_N)
if (EN_out_ports_4_getFlit &&
IF_outport_encoder_37_BIT_3_38_THEN_outport_en_ETC___d1062 &&
IF_IF_outport_encoder_37_BIT_3_38_THEN_IF_outp_ETC___d1175)
$finish(32'd0);
end
// synopsys translate_on
endmodule // mkRouterCoreSimple
|
module opicorv32_control (
pcpi_int_wr,
decoded_imm_uj,
pcpi_int_rd,
mem_rdata_word,
decoded_rd,
decoded_rs1,
pcpi_int_wait,
pcpi_int_ready,
irq,
decoded_rs2,
decoded_imm,
resetn,
clk,
instr,
is,
mem_done,
next_pc,
reg_op1,
reg_op2,
trap,
mem_do_rinst,
mem_do_wdata,
mem_do_rdata,
mem_wordsize,
mem_do_prefetch,
pcpi_valid,
decoder_trigger,
decoder_trigger_q,
decoder_pseudo_trigger,
eoi,
ascii_state
);
input pcpi_int_wr;
input [31:0] decoded_imm_uj;
input [31:0] pcpi_int_rd;
input [31:0] mem_rdata_word;
input [5:0] decoded_rd;
input [5:0] decoded_rs1;
input pcpi_int_wait;
input pcpi_int_ready;
input [31:0] irq;
input [5:0] decoded_rs2;
input [31:0] decoded_imm;
input resetn;
input clk;
input [47:0] instr;
input [14:0] is;
input mem_done;
output [31:0] next_pc;
output [31:0] reg_op1;
output [31:0] reg_op2;
output trap;
output mem_do_rinst;
output mem_do_wdata;
output mem_do_rdata;
output [1:0] mem_wordsize;
output mem_do_prefetch;
output pcpi_valid;
output decoder_trigger;
output decoder_trigger_q;
output decoder_pseudo_trigger;
output [31:0] eoi;
output [127:0] ascii_state;
/* signal declarations */
wire [127:0] _5439 = 128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000011101000111001001100001011100000010000000100000;
wire [127:0] _5418 = 128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000011001100110010101110100011000110110100000100000;
wire [127:0] _5397 = 128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000011011000110010001011111011100100111001100110001;
wire [127:0] _5376 = 128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000011011000110010001011111011100100111001100110010;
wire [127:0] _5355 = 128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000011001010111100001100101011000110010000000100000;
wire [127:0] _5334 = 128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000011100110110100001101001011001100111010000100000;
wire [127:0] _5313 = 128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000011100110111010001101101011001010110110100100000;
wire [127:0] _5292 = 128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000011011000110010001101101011001010110110100100000;
wire [127:0] _5272 = 128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000110111001101111011011100110010100111111;
wire _5293;
wire [127:0] _5441;
wire _5314;
wire [127:0] _5442;
wire _5335;
wire [127:0] _5443;
wire _5356;
wire [127:0] _5444;
wire _5377;
wire [127:0] _5445;
wire _5398;
wire [127:0] _5446;
wire _5419;
wire [127:0] _5447;
wire _5440;
wire [127:0] ascii_state_0;
wire [31:0] _2612 = 32'b00000000000000000000000000000000;
wire [31:0] _2610 = 32'b00000000000000000000000000000000;
wire [31:0] _3661;
wire [31:0] _3662;
wire [31:0] _5187;
wire [31:0] _5188;
wire [31:0] _5189;
wire [31:0] _5190;
wire [31:0] _3740 = 32'b00000000000000000000000000000000;
wire [31:0] _5191;
wire [31:0] _5192;
wire [31:0] _5193;
wire [31:0] _5194;
wire [31:0] _5195;
wire [31:0] _5196;
wire _5197;
wire [31:0] _5198;
wire _5199;
wire [31:0] _5200;
wire [31:0] _2611;
reg [31:0] _2613;
wire _2616 = 1'b0;
wire _2614 = 1'b0;
wire _3869 = 1'b1;
wire _5179;
wire _5180;
wire _3888 = 1'b1;
wire _5181;
wire _5182;
wire _3944 = 1'b0;
wire _5183;
wire _5184;
wire _5185;
wire _5186;
wire _2615;
reg _2617;
wire _2620 = 1'b0;
wire _2618 = 1'b0;
wire _2619;
reg _2621;
wire [1:0] _2636 = 2'b00;
wire [1:0] _2634 = 2'b00;
wire [1:0] _3674 = 2'b00;
wire [1:0] _3879 = 2'b10;
wire [1:0] _3877 = 2'b01;
wire [1:0] _3881;
wire [1:0] _3875 = 2'b00;
wire _3878;
wire _3880;
wire _3882;
wire [1:0] _3883;
wire [1:0] _5140;
wire [1:0] _5141;
wire [1:0] _3924 = 2'b10;
wire [1:0] _3920 = 2'b01;
wire [1:0] _3928;
wire [1:0] _3918 = 2'b00;
wire _3921;
wire _3922;
wire _3923;
wire _3925;
wire _3926;
wire _3927;
wire _3929;
wire [1:0] _3930;
wire [1:0] _5142;
wire [1:0] _5143;
wire _5144;
wire [1:0] _5145;
wire _5146;
wire [1:0] _5147;
wire _5148;
wire [1:0] _5149;
wire [1:0] _2635;
reg [1:0] _2637;
wire _2652 = 1'b0;
wire _2650 = 1'b0;
wire _4129 = 1'b0;
wire _5031;
wire _5032;
wire _2651;
reg _2653;
wire _3353 = 1'b0;
wire _3351 = 1'b0;
wire _3554 = 1'b1;
wire _4755;
wire _4756;
wire _4757;
wire _4758;
wire _4759;
wire _4760;
wire _4761;
wire _4762;
wire _4763;
wire _4764;
wire _4765;
wire _4766;
wire _4767;
wire _4768;
wire _4769;
wire _4770;
wire _4771;
wire _4772;
wire _4773;
wire _4774;
wire _4775;
wire _4776;
wire _4777;
wire _4778;
wire _4779;
wire _4780;
wire _4781;
wire _4782;
wire _4783;
wire _4784;
wire _4785;
wire _4786;
wire _4787;
wire _4788;
wire _4789;
wire _4790;
wire _4791;
wire _4792;
wire _4793;
wire _4794;
wire _4795;
wire _4796;
wire _4797;
wire _4798;
wire _4799;
wire _4800;
wire _4801;
wire _4802;
wire _4803;
wire _4804;
wire _4805;
wire _4806;
wire _4807;
wire _4808;
wire _4809;
wire _4810;
wire _4811;
wire _4812;
wire _4813;
wire _4814;
wire _4815;
wire _4816;
wire _4817;
wire _4818;
wire _3657 = 1'b0;
wire _4819;
wire _4820;
wire _4821;
wire _4822;
wire _4823;
wire _3757 = 1'b1;
wire _3749 = 1'b1;
wire _3743 = 1'b1;
wire _3737 = 1'b1;
wire _3734 = 1'b1;
wire _3697 = 1'b1;
wire _4824;
wire _4825;
wire _4826;
wire _4827;
wire _4828;
wire _4829;
wire _4830;
wire _4831;
wire _4832;
wire _4833;
wire _3805 = 1'b1;
wire _4834;
wire _3868 = 1'b1;
wire _3935 = 1'b1;
wire _4835;
wire _4836;
wire _4837;
wire _4838;
wire _4839;
wire _4840;
wire _4841;
wire _4842;
wire _4843;
wire _4844;
wire [2:0] _2604 = 3'b000;
wire [2:0] _2594 = 3'b000;
wire [2:0] _5201;
wire [2:0] _5202;
wire [2:0] _5203;
wire [2:0] _5204;
wire [2:0] _5205;
wire [2:0] _5206;
wire [2:0] _5207;
wire [2:0] _5208;
wire [2:0] _5209;
wire [2:0] _5210;
wire [2:0] _5211;
wire [2:0] _5212;
wire [2:0] _5213;
wire [2:0] _5214;
wire [2:0] _5215;
wire [2:0] _5216;
wire [2:0] _5217;
wire [2:0] _5218;
wire [2:0] _5219;
wire [2:0] _5220;
wire [2:0] _5221;
wire [2:0] _5222;
wire [2:0] _5223;
wire [2:0] _5224;
wire [2:0] _2601 = 3'b001;
wire [2:0] _5225;
wire [2:0] _5226;
wire [2:0] _5227;
wire [2:0] _5228;
wire [2:0] _5229;
wire [2:0] _5230;
wire [2:0] _5231;
wire [2:0] _5232;
wire [2:0] _5233;
wire [2:0] _5234;
wire [2:0] _5235;
wire [2:0] _5236;
wire _2632 = 1'b0;
wire _2630 = 1'b0;
wire _3942 = 1'b0;
wire _3536;
wire _3537;
wire _3538;
wire _3539;
wire _3540;
wire _5150;
wire _5151;
wire _5152;
wire _3579;
wire _3580;
wire _3581;
wire _3584;
wire _3585;
wire _3586;
wire _3587;
wire _3588;
wire _3589;
wire _3590;
wire _3591;
wire _3592;
wire _3593;
wire _3594;
wire _3595;
wire _3596;
wire _3597;
wire _3598;
wire _3599;
wire _3600;
wire _3601;
wire _3602;
wire _3603;
wire _3604;
wire _3605;
wire _3606;
wire _3607;
wire _3608;
wire _3609;
wire _3610;
wire _3611;
wire _3612;
wire _3613;
wire _3614;
wire [31:0] _3582;
wire [31:0] _3583;
wire _3615;
wire _3616;
wire _3617;
wire _3618;
wire _3619;
wire _3620;
wire _3621;
wire _3622;
wire _3623;
wire _3624;
wire _3625;
wire _3626;
wire _3627;
wire _3628;
wire _3629;
wire _3630;
wire _3631;
wire _3632;
wire _3633;
wire _3634;
wire _3635;
wire _3636;
wire _3637;
wire _3638;
wire _3639;
wire _3640;
wire _3641;
wire _3642;
wire _3643;
wire _3644;
wire _3645;
wire _3646;
wire _3647;
wire _2624 = 1'b0;
wire _2622 = 1'b0;
wire _3808 = 1'b0;
wire _5167;
wire _5168;
wire _3870 = 1'b1;
wire _3871;
wire _3872;
wire _5169;
wire _5170;
wire _3889 = 1'b1;
wire _5171;
wire _5172;
wire _2648 = 1'b0;
wire _2646 = 1'b0;
wire _3938 = 1'b1;
wire _3941 = 1'b0;
wire _3551 = 1'b1;
wire _5036;
wire _5037;
wire _5038;
wire _5039;
wire _5040;
wire _5041;
wire _5042;
wire _5043;
wire _5044;
wire _5045;
wire _5046;
wire _5047;
wire _5048;
wire _5049;
wire _5050;
wire _5051;
wire _5052;
wire _5053;
wire _5054;
wire _5055;
wire _5056;
wire _5057;
wire _5058;
wire _5059;
wire _5060;
wire _5061;
wire _5062;
wire _5063;
wire _5064;
wire _5065;
wire _5066;
wire _5067;
wire _5068;
wire _5069;
wire _5070;
wire _5071;
wire _5072;
wire _5073;
wire _5074;
wire _5075;
wire _5076;
wire _5077;
wire _5078;
wire _5079;
wire _5080;
wire _5081;
wire _5082;
wire _5083;
wire _5084;
wire _5085;
wire _5086;
wire _5087;
wire _5088;
wire _5089;
wire _5090;
wire _5091;
wire _5092;
wire _5093;
wire _5094;
wire _5095;
wire _5096;
wire _5097;
wire _5098;
wire _5099;
wire _3544 = 1'b1;
wire _3541 = 1'b0;
wire _5100;
wire _3665 = 1'b1;
wire _3675;
wire _3676;
wire _3677;
wire _5033;
wire _5034;
wire _5035;
wire _5101;
wire _5102;
wire _5103;
wire _3784 = 1'b1;
wire _5104;
wire _5105;
wire _5106;
wire _3695 = 1'b1;
wire _3689 = 1'b1;
wire _3688;
wire _5107;
wire _3690;
wire _5108;
wire _5109;
wire _5110;
wire _5111;
wire _5112;
wire _5113;
wire _5114;
wire _5115;
wire _5116;
wire _5117;
wire _5118;
wire _5119;
wire _5120;
wire _3799 = 1'b1;
wire _5121;
wire _3791 = 1'b1;
wire _3790;
wire _5122;
wire _3792;
wire _5123;
wire _5124;
wire _5125;
wire _5126;
wire _5127;
wire _5128;
wire _5129;
wire _5130;
wire _5131;
wire _5132;
wire _5133;
wire _5134;
wire _3807 = 1'b1;
wire _3274;
wire _3271;
wire _3272;
wire _3280;
wire [30:0] _3260;
wire _3261;
wire _3262;
wire [31:0] _3263;
wire [30:0] _3264;
wire _3265;
wire _3266;
wire [31:0] _3267;
wire _3268;
wire _3269;
wire _3257;
wire _3258;
wire _3278;
wire _3282;
wire [30:0] _3247;
wire _3248;
wire _3249;
wire [31:0] _3250;
wire [30:0] _3251;
wire _3252;
wire _3253;
wire [31:0] _3254;
wire _3255;
wire [31:0] _2660 = 32'b00000000000000000000000000000000;
wire [31:0] _2658 = 32'b00000000000000000000000000000000;
wire [31:0] _4990;
wire [31:0] _3753 = 32'b00000000000000000000000000000000;
wire _3754;
wire [31:0] _3755;
wire [31:0] _3789 = 32'b00000000000000000000000000000000;
wire [31:0] _4991;
wire [31:0] _4992;
wire [31:0] _4993;
wire [31:0] _4994;
wire [31:0] _4995;
wire [31:0] _4996;
wire [31:0] _4997;
wire [31:0] _4998;
wire [3:0] _3853 = 4'b0000;
wire [27:0] _3854;
wire [31:0] _3855;
wire [27:0] _3847;
wire [3:0] _3848 = 4'b0000;
wire [31:0] _3849;
wire [31:0] _3859;
wire [27:0] _3838;
wire _3839;
wire [1:0] _3840;
wire [3:0] _3841;
wire [31:0] _3843;
wire _3850;
wire _3851;
wire _3852;
wire _3856;
wire _3857;
wire _3858;
wire _3860;
wire [31:0] _3861;
wire _3826 = 1'b0;
wire [30:0] _3827;
wire [31:0] _3828;
wire [30:0] _3820;
wire _3821 = 1'b0;
wire [31:0] _3822;
wire [31:0] _3832;
wire [30:0] _3814;
wire _3815;
wire [31:0] _3816;
wire _3823;
wire _3824;
wire _3825;
wire _3829;
wire _3830;
wire _3831;
wire _3833;
wire [31:0] _3834;
wire [31:0] _4999;
wire [4:0] _3866 = 5'b00000;
wire [4:0] _3385 = 5'b00000;
wire [4:0] _3383 = 5'b00000;
wire [4:0] _3785;
wire [4:0] _4544;
wire [4:0] _4545;
wire [4:0] _3693;
wire [4:0] _3691;
wire [4:0] _4546;
wire [4:0] _4547;
wire [4:0] _4548;
wire [4:0] _4549;
wire [4:0] _4550;
wire [4:0] _4551;
wire [4:0] _4552;
wire [4:0] _4553;
wire [4:0] _4554;
wire [4:0] _4555;
wire [4:0] _4556;
wire [4:0] _4557;
wire _3063;
wire _3064;
wire [31:0] _3066 = 32'b00000000000000000000000000000000;
wire [31:0] _3065 = 32'b00000000000000000000000000000000;
wire [31:0] _3670 = 32'b00000000000000000000000000000100;
wire [31:0] _3671;
wire [31:0] _4965;
wire [31:0] _3669;
wire [31:0] _4966;
wire [31:0] _3368 = 32'b00000000000000000000000000000000;
wire [31:0] _3552 = 32'b00000000000000000000000000000100;
wire [31:0] _3553;
wire _4667;
wire _4668;
wire _4669;
wire _4670;
wire _4671;
wire _4672;
wire _4673;
wire _4674;
wire _4675;
wire _4676;
wire _4677;
wire _4678;
wire _4679;
wire _4680;
wire _4681;
wire _4682;
wire _4683;
wire _4684;
wire _4685;
wire _4686;
wire _4687;
wire _4688;
wire _4689;
wire _4690;
wire _4691;
wire _4692;
wire _4693;
wire _4694;
wire _4695;
wire _4696;
wire _4697;
wire _4698;
wire _4699;
wire _4700;
wire _4701;
wire _4702;
wire _4703;
wire _4704;
wire _4705;
wire _4706;
wire _4707;
wire _4708;
wire _4709;
wire _4710;
wire _4711;
wire _4712;
wire _4713;
wire _4714;
wire _4715;
wire _4716;
wire _4717;
wire _4718;
wire _4719;
wire _4720;
wire _4721;
wire _4722;
wire _4723;
wire _4724;
wire _4725;
wire _4726;
wire _4727;
wire _4728;
wire _4729;
wire [31:0] _4730;
wire [31:0] _3543;
wire [31:0] _3548 = 32'b00000000000000000000000000000100;
wire [31:0] _3549;
wire [31:0] _4731;
wire [31:0] _3377 = 32'b00000000000000000000000000000000;
wire [31:0] _3375 = 32'b00000000000000000000000000000000;
wire [31:0] _3311;
wire [31:0] _3309;
wire [31:0] _3317;
wire [30:0] _3305 = 31'b0000000000000000000000000000000;
wire [31:0] _3307;
wire [31:0] _3294;
wire [31:0] _3315;
wire [31:0] _3319;
wire [31:0] _3290;
wire [31:0] _2656 = 32'b00000000000000000000000000000000;
wire [31:0] _2654 = 32'b00000000000000000000000000000000;
wire [31:0] _5013;
wire [31:0] _5014;
wire [31:0] _3788 = 32'b00000000000000000000000000000000;
wire [31:0] _5015;
wire _3692;
wire [31:0] _5016;
wire _3694;
wire [31:0] _5017;
wire _3696;
wire [31:0] _5018;
wire [31:0] _5019;
wire [31:0] _5020;
wire [31:0] _5021;
wire [31:0] _5022;
wire [31:0] _5023;
wire [31:0] _5024;
wire [31:0] _5025;
wire [31:0] _5026;
wire _5027;
wire [31:0] _5028;
wire _5029;
wire [31:0] _5030;
wire [31:0] _2655;
reg [31:0] _2657;
wire [31:0] _3286;
wire _3291;
wire _3292;
wire _3293;
wire [31:0] _3313;
wire _3295;
wire _3296;
wire _3297;
wire _3308;
wire _3316;
wire _3310;
wire _3312;
wire _3318;
wire _3320;
wire [31:0] _3321;
wire [31:0] _3376;
reg [31:0] _3378;
wire [31:0] _3381 = 32'b00000000000000000000000000000000;
wire [31:0] _3379 = 32'b00000000000000000000000000000000;
wire _4566;
wire _4567;
wire _4568;
wire _4569;
wire _4570;
wire _4571;
wire _4572;
wire _4573;
wire _4574;
wire _4575;
wire _4576;
wire _4577;
wire _4578;
wire _4579;
wire _4580;
wire _4581;
wire _4582;
wire _4583;
wire _4584;
wire _4585;
wire _4586;
wire _4587;
wire _4588;
wire _4589;
wire _4590;
wire _4591;
wire _4592;
wire _4593;
wire _4594;
wire _4595;
wire _4596;
wire _4597;
wire _4598;
wire _4599;
wire _4600;
wire _4601;
wire _4602;
wire _4603;
wire _4604;
wire _4605;
wire _4606;
wire _4607;
wire _4608;
wire _4609;
wire _4610;
wire _4611;
wire _4612;
wire _4613;
wire _4614;
wire _4615;
wire _4616;
wire _4617;
wire _4618;
wire _4619;
wire _4620;
wire _4621;
wire _4622;
wire _4623;
wire _4624;
wire _4625;
wire _4626;
wire _4627;
wire _4628;
wire [31:0] _4629;
wire [31:0] _4630;
wire [31:0] _4631;
wire [31:0] _4632;
wire [31:0] _4633;
wire [31:0] _4634;
wire [31:0] _3764;
wire [63:0] _3341 = 64'b0000000000000000000000000000000000000000000000000000000000000000;
wire [63:0] _3339 = 64'b0000000000000000000000000000000000000000000000000000000000000000;
wire [63:0] _3958 = 64'b0000000000000000000000000000000000000000000000000000000000000001;
wire [63:0] _3959;
wire [63:0] _4869;
wire [63:0] _3340;
reg [63:0] count_cycle;
wire [31:0] _3762;
wire [31:0] _3768;
wire [31:0] _3760;
wire [63:0] _3337 = 64'b0000000000000000000000000000000000000000000000000000000000000000;
wire [63:0] _3335 = 64'b0000000000000000000000000000000000000000000000000000000000000000;
wire [63:0] _3546 = 64'b0000000000000000000000000000000000000000000000000000000000000001;
wire [63:0] _3547;
wire [63:0] _4870;
wire [63:0] _4871;
wire [63:0] _4872;
wire [63:0] _4873;
wire _4874;
wire [63:0] _4875;
wire [63:0] _3336;
reg [63:0] _3338;
wire [31:0] _3758;
wire _3761;
wire [31:0] _3766;
wire _3763;
wire _3765;
wire _3769;
wire [31:0] _3770;
wire [31:0] _4635;
wire [31:0] _4636;
wire [31:0] _4637;
wire [31:0] _4638;
wire [31:0] _4639;
wire [31:0] _4640;
wire [31:0] _4641;
wire [31:0] _4642;
wire [31:0] _4643;
wire [31:0] _4644;
wire [31:0] _3371 = 32'b00000000000000000000000000000000;
wire [31:0] _39 = 32'b00000000000000000000000000000000;
wire _4665;
wire [31:0] _4666;
wire [31:0] _3370;
reg [31:0] _3372;
wire [31:0] _3811;
wire [31:0] _4645;
wire [15:0] _3899;
wire _3900;
wire [1:0] _3901;
wire [3:0] _3902;
wire [7:0] _3903;
wire [15:0] _3904;
wire [31:0] _3906;
wire [31:0] _3907;
wire [7:0] _3890;
wire _3891;
wire [1:0] _3892;
wire [3:0] _3893;
wire [7:0] _3894;
wire [15:0] _3895;
wire [23:0] _3896;
wire [31:0] _3898;
wire _3361 = 1'b0;
wire _3359 = 1'b0;
wire _3653 = 1'b0;
wire _3916;
wire _4743;
wire _4744;
wire _4745;
wire _4746;
wire _4747;
wire _4748;
wire _3360;
reg _3362;
wire _3365 = 1'b0;
wire _3363 = 1'b0;
wire _3654 = 1'b0;
wire _3917;
wire _4737;
wire _4738;
wire _4739;
wire _4740;
wire _4741;
wire _4742;
wire _3364;
reg _3366;
wire _3908;
wire [31:0] _3909;
wire _3911;
wire _3912;
wire [31:0] _4646;
wire [31:0] _4647;
wire [31:0] _4127 = 32'b00000000000000000000000000000000;
wire _4648;
wire [31:0] _4649;
wire _4650;
wire [31:0] _4651;
wire _4652;
wire [31:0] _4653;
wire _4654;
wire [31:0] _4655;
wire _4656;
wire [31:0] _4657;
wire _4658;
wire [31:0] _4659;
wire [31:0] _3380;
reg [31:0] _3382;
wire _3349 = 1'b0;
wire _3347 = 1'b0;
wire _3656 = 1'b0;
wire _3804 = 1'b1;
wire _4847;
wire _4848;
wire _4849;
wire _4850;
wire _4851;
wire _3348;
reg _3350;
wire [31:0] _3672;
wire [31:0] _3673;
wire [31:0] _40 = 32'b00000000000000000000000000010000;
wire [31:0] _4660;
wire [31:0] _4661;
wire [31:0] _4662;
wire [31:0] _3373 = 32'b00000000000000000000000000000000;
wire _4663;
wire [31:0] _4664;
wire [31:0] _3374;
wire [31:0] _4732;
wire [31:0] _4733;
wire [31:0] _4734;
wire _4735;
wire [31:0] _4736;
wire [31:0] _3367;
reg [31:0] _3369;
wire [31:0] _4967;
wire [31:0] _3659;
wire [31:0] _3660;
wire [31:0] _4968;
wire [31:0] _4969;
wire [31:0] _4970;
wire [31:0] _4971;
wire _3345 = 1'b0;
wire _3343 = 1'b0;
wire _3542 = 1'b1;
wire _3545;
wire _4852;
wire _3655 = 1'b0;
wire _4853;
wire _3555;
wire _3333 = 1'b0;
wire _3331 = 1'b0;
wire _3550 = 1'b1;
wire _4876;
wire _4877;
wire _4878;
wire _4879;
wire _4880;
wire _4881;
wire _4882;
wire _4883;
wire _4884;
wire _4885;
wire _4886;
wire _4887;
wire _4888;
wire _4889;
wire _4890;
wire _4891;
wire _4892;
wire _4893;
wire _4894;
wire _4895;
wire _4896;
wire _4897;
wire _4898;
wire _4899;
wire _4900;
wire _4901;
wire _4902;
wire _4903;
wire _4904;
wire _4905;
wire _4906;
wire [31:0] _3397 = 32'b00000000000000000000000000000000;
wire [31:0] _3395 = 32'b00000000000000000000000000000000;
wire _3433 = 1'b0;
wire _3702;
wire _4463;
wire _4464;
wire _4465;
wire _4466;
wire _4467;
wire _4468;
wire _4469;
wire _4470;
wire _4471;
wire _4472;
wire _3432;
reg _3434;
wire _3439 = 1'b0;
wire _3704;
wire _4443;
wire _4444;
wire _4445;
wire _4446;
wire _4447;
wire _4448;
wire _4449;
wire _4450;
wire _4451;
wire _4452;
wire _3438;
reg _3440;
wire _3442 = 1'b0;
wire _3705;
wire _4433;
wire _4434;
wire _4435;
wire _4436;
wire _4437;
wire _4438;
wire _4439;
wire _4440;
wire _4441;
wire _4442;
wire _3441;
reg _3443;
wire _3445 = 1'b0;
wire _3706;
wire _4423;
wire _4424;
wire _4425;
wire _4426;
wire _4427;
wire _4428;
wire _4429;
wire _4430;
wire _4431;
wire _4432;
wire _3444;
reg _3446;
wire _3448 = 1'b0;
wire _3707;
wire _4413;
wire _4414;
wire _4415;
wire _4416;
wire _4417;
wire _4418;
wire _4419;
wire _4420;
wire _4421;
wire _4422;
wire _3447;
reg _3449;
wire _3451 = 1'b0;
wire _3708;
wire _4403;
wire _4404;
wire _4405;
wire _4406;
wire _4407;
wire _4408;
wire _4409;
wire _4410;
wire _4411;
wire _4412;
wire _3450;
reg _3452;
wire _3454 = 1'b0;
wire _3709;
wire _4393;
wire _4394;
wire _4395;
wire _4396;
wire _4397;
wire _4398;
wire _4399;
wire _4400;
wire _4401;
wire _4402;
wire _3453;
reg _3455;
wire _3457 = 1'b0;
wire _3710;
wire _4383;
wire _4384;
wire _4385;
wire _4386;
wire _4387;
wire _4388;
wire _4389;
wire _4390;
wire _4391;
wire _4392;
wire _3456;
reg _3458;
wire _3460 = 1'b0;
wire _3711;
wire _4373;
wire _4374;
wire _4375;
wire _4376;
wire _4377;
wire _4378;
wire _4379;
wire _4380;
wire _4381;
wire _4382;
wire _3459;
reg _3461;
wire _3463 = 1'b0;
wire _3712;
wire _4363;
wire _4364;
wire _4365;
wire _4366;
wire _4367;
wire _4368;
wire _4369;
wire _4370;
wire _4371;
wire _4372;
wire _3462;
reg _3464;
wire _3466 = 1'b0;
wire _3713;
wire _4353;
wire _4354;
wire _4355;
wire _4356;
wire _4357;
wire _4358;
wire _4359;
wire _4360;
wire _4361;
wire _4362;
wire _3465;
reg _3467;
wire _3469 = 1'b0;
wire _3714;
wire _4343;
wire _4344;
wire _4345;
wire _4346;
wire _4347;
wire _4348;
wire _4349;
wire _4350;
wire _4351;
wire _4352;
wire _3468;
reg _3470;
wire _3472 = 1'b0;
wire _3715;
wire _4333;
wire _4334;
wire _4335;
wire _4336;
wire _4337;
wire _4338;
wire _4339;
wire _4340;
wire _4341;
wire _4342;
wire _3471;
reg _3473;
wire _3475 = 1'b0;
wire _3716;
wire _4323;
wire _4324;
wire _4325;
wire _4326;
wire _4327;
wire _4328;
wire _4329;
wire _4330;
wire _4331;
wire _4332;
wire _3474;
reg _3476;
wire _3478 = 1'b0;
wire _3717;
wire _4313;
wire _4314;
wire _4315;
wire _4316;
wire _4317;
wire _4318;
wire _4319;
wire _4320;
wire _4321;
wire _4322;
wire _3477;
reg _3479;
wire _3481 = 1'b0;
wire _3718;
wire _4303;
wire _4304;
wire _4305;
wire _4306;
wire _4307;
wire _4308;
wire _4309;
wire _4310;
wire _4311;
wire _4312;
wire _3480;
reg _3482;
wire _3484 = 1'b0;
wire _3719;
wire _4293;
wire _4294;
wire _4295;
wire _4296;
wire _4297;
wire _4298;
wire _4299;
wire _4300;
wire _4301;
wire _4302;
wire _3483;
reg _3485;
wire _3487 = 1'b0;
wire _3720;
wire _4283;
wire _4284;
wire _4285;
wire _4286;
wire _4287;
wire _4288;
wire _4289;
wire _4290;
wire _4291;
wire _4292;
wire _3486;
reg _3488;
wire _3490 = 1'b0;
wire _3721;
wire _4273;
wire _4274;
wire _4275;
wire _4276;
wire _4277;
wire _4278;
wire _4279;
wire _4280;
wire _4281;
wire _4282;
wire _3489;
reg _3491;
wire _3493 = 1'b0;
wire _3722;
wire _4263;
wire _4264;
wire _4265;
wire _4266;
wire _4267;
wire _4268;
wire _4269;
wire _4270;
wire _4271;
wire _4272;
wire _3492;
reg _3494;
wire _3496 = 1'b0;
wire _3723;
wire _4253;
wire _4254;
wire _4255;
wire _4256;
wire _4257;
wire _4258;
wire _4259;
wire _4260;
wire _4261;
wire _4262;
wire _3495;
reg _3497;
wire _3499 = 1'b0;
wire _3724;
wire _4243;
wire _4244;
wire _4245;
wire _4246;
wire _4247;
wire _4248;
wire _4249;
wire _4250;
wire _4251;
wire _4252;
wire _3498;
reg _3500;
wire _3502 = 1'b0;
wire _3725;
wire _4233;
wire _4234;
wire _4235;
wire _4236;
wire _4237;
wire _4238;
wire _4239;
wire _4240;
wire _4241;
wire _4242;
wire _3501;
reg _3503;
wire _3505 = 1'b0;
wire _3726;
wire _4223;
wire _4224;
wire _4225;
wire _4226;
wire _4227;
wire _4228;
wire _4229;
wire _4230;
wire _4231;
wire _4232;
wire _3504;
reg _3506;
wire _3508 = 1'b0;
wire _3727;
wire _4213;
wire _4214;
wire _4215;
wire _4216;
wire _4217;
wire _4218;
wire _4219;
wire _4220;
wire _4221;
wire _4222;
wire _3507;
reg _3509;
wire _3511 = 1'b0;
wire _3728;
wire _4203;
wire _4204;
wire _4205;
wire _4206;
wire _4207;
wire _4208;
wire _4209;
wire _4210;
wire _4211;
wire _4212;
wire _3510;
reg _3512;
wire _3514 = 1'b0;
wire _3729;
wire _4193;
wire _4194;
wire _4195;
wire _4196;
wire _4197;
wire _4198;
wire _4199;
wire _4200;
wire _4201;
wire _4202;
wire _3513;
reg _3515;
wire _3517 = 1'b0;
wire _3730;
wire _4183;
wire _4184;
wire _4185;
wire _4186;
wire _4187;
wire _4188;
wire _4189;
wire _4190;
wire _4191;
wire _4192;
wire _3516;
reg _3518;
wire _3520 = 1'b0;
wire _3731;
wire _4173;
wire _4174;
wire _4175;
wire _4176;
wire _4177;
wire _4178;
wire _4179;
wire _4180;
wire _4181;
wire _4182;
wire _3519;
reg _3521;
wire _3523 = 1'b0;
wire _3732;
wire _4163;
wire _4164;
wire _4165;
wire _4166;
wire _4167;
wire _4168;
wire _4169;
wire _4170;
wire _4171;
wire _4172;
wire _3522;
reg _3524;
wire _3526 = 1'b0;
wire _3733;
wire _4153;
wire _4154;
wire _4155;
wire _4156;
wire _4157;
wire _4158;
wire _4159;
wire _4160;
wire _4161;
wire _4162;
wire _3525;
reg _3527;
wire [31:0] _3528;
wire [31:0] _3658;
wire [31:0] _4522;
wire [31:0] _4523;
wire [31:0] _4524;
wire [31:0] _4525;
wire _3948 = 1'b1;
wire [31:0] _3951 = 32'b00000000000000000000000000000000;
wire [31:0] _3949 = 32'b00000000000000000000000000000001;
wire [31:0] _3950;
wire _3952;
wire _4520;
wire _3967;
wire _3968;
wire _3969;
wire _3970;
wire _3971;
wire _4519;
wire [31:0] _3953 = 32'b00000000000000000000000000000000;
wire [31:0] _3534 = 32'b00000000000000000000000000000000;
wire [31:0] _3532 = 32'b00000000000000000000000000000000;
wire _3698;
wire _3699;
wire _3700;
wire [31:0] _4131;
wire [31:0] _4132;
wire [31:0] _4133;
wire [31:0] _4134;
wire [31:0] _4135;
wire [31:0] _4136;
wire [31:0] _4137;
wire [31:0] _4138;
wire [31:0] _3946 = 32'b00000000000000000000000000000001;
wire [31:0] _3947;
wire [31:0] _4130;
wire _4139;
wire [31:0] _4140;
wire [31:0] _3533;
reg [31:0] _3535;
wire _3954;
wire _3955;
wire _3956;
wire _3957;
wire _4521;
wire _3399;
wire _3778 = 1'b1;
wire _3779;
wire _3780;
wire _3781;
wire _3782;
wire _4504;
wire _4505;
wire _4506;
wire _4507;
wire _3773 = 1'b1;
wire _3774;
wire _3775;
wire _3776;
wire _3777;
wire _4508;
wire _4509;
wire _4510;
wire _3793 = 1'b1;
wire _3393 = 1'b0;
wire _3391 = 1'b0;
wire _3666 = 1'b1;
wire _4528;
wire _4529;
wire _4530;
wire _3739 = 1'b0;
wire _4531;
wire _4532;
wire _4533;
wire _4534;
wire _4535;
wire _4536;
wire _4537;
wire _4538;
wire _4539;
wire _4540;
wire _3392;
reg _3394;
wire _3794;
wire _3436 = 1'b0;
wire [31:0] _37 = 32'b00000000000000000000000000000000;
wire _3238;
wire _3239;
wire [31:0] _3241 = 32'b00000000000000000000000000000000;
wire [31:0] _3240 = 32'b00000000000000000000000000000000;
reg [31:0] _3242;
wire _3233;
wire _3234;
wire [31:0] _3236 = 32'b00000000000000000000000000000000;
wire [31:0] _3235 = 32'b00000000000000000000000000000000;
reg [31:0] _3237;
wire _3228;
wire _3229;
wire [31:0] _3231 = 32'b00000000000000000000000000000000;
wire [31:0] _3230 = 32'b00000000000000000000000000000000;
reg [31:0] _3232;
wire _3223;
wire _3224;
wire [31:0] _3226 = 32'b00000000000000000000000000000000;
wire [31:0] _3225 = 32'b00000000000000000000000000000000;
reg [31:0] _3227;
wire _3218;
wire _3219;
wire [31:0] _3221 = 32'b00000000000000000000000000000000;
wire [31:0] _3220 = 32'b00000000000000000000000000000000;
reg [31:0] _3222;
wire _3213;
wire _3214;
wire [31:0] _3216 = 32'b00000000000000000000000000000000;
wire [31:0] _3215 = 32'b00000000000000000000000000000000;
reg [31:0] _3217;
wire _3208;
wire _3209;
wire [31:0] _3211 = 32'b00000000000000000000000000000000;
wire [31:0] _3210 = 32'b00000000000000000000000000000000;
reg [31:0] _3212;
wire _3203;
wire _3204;
wire [31:0] _3206 = 32'b00000000000000000000000000000000;
wire [31:0] _3205 = 32'b00000000000000000000000000000000;
reg [31:0] _3207;
wire _3198;
wire _3199;
wire [31:0] _3201 = 32'b00000000000000000000000000000000;
wire [31:0] _3200 = 32'b00000000000000000000000000000000;
reg [31:0] _3202;
wire _3193;
wire _3194;
wire [31:0] _3196 = 32'b00000000000000000000000000000000;
wire [31:0] _3195 = 32'b00000000000000000000000000000000;
reg [31:0] _3197;
wire _3188;
wire _3189;
wire [31:0] _3191 = 32'b00000000000000000000000000000000;
wire [31:0] _3190 = 32'b00000000000000000000000000000000;
reg [31:0] _3192;
wire _3183;
wire _3184;
wire [31:0] _3186 = 32'b00000000000000000000000000000000;
wire [31:0] _3185 = 32'b00000000000000000000000000000000;
reg [31:0] _3187;
wire _3178;
wire _3179;
wire [31:0] _3181 = 32'b00000000000000000000000000000000;
wire [31:0] _3180 = 32'b00000000000000000000000000000000;
reg [31:0] _3182;
wire _3173;
wire _3174;
wire [31:0] _3176 = 32'b00000000000000000000000000000000;
wire [31:0] _3175 = 32'b00000000000000000000000000000000;
reg [31:0] _3177;
wire _3168;
wire _3169;
wire [31:0] _3171 = 32'b00000000000000000000000000000000;
wire [31:0] _3170 = 32'b00000000000000000000000000000000;
reg [31:0] _3172;
wire _3163;
wire _3164;
wire [31:0] _3166 = 32'b00000000000000000000000000000000;
wire [31:0] _3165 = 32'b00000000000000000000000000000000;
reg [31:0] _3167;
wire _3158;
wire _3159;
wire [31:0] _3161 = 32'b00000000000000000000000000000000;
wire [31:0] _3160 = 32'b00000000000000000000000000000000;
reg [31:0] _3162;
wire _3153;
wire _3154;
wire [31:0] _3156 = 32'b00000000000000000000000000000000;
wire [31:0] _3155 = 32'b00000000000000000000000000000000;
reg [31:0] _3157;
wire _3148;
wire _3149;
wire [31:0] _3151 = 32'b00000000000000000000000000000000;
wire [31:0] _3150 = 32'b00000000000000000000000000000000;
reg [31:0] _3152;
wire _3143;
wire _3144;
wire [31:0] _3146 = 32'b00000000000000000000000000000000;
wire [31:0] _3145 = 32'b00000000000000000000000000000000;
reg [31:0] _3147;
wire _3138;
wire _3139;
wire [31:0] _3141 = 32'b00000000000000000000000000000000;
wire [31:0] _3140 = 32'b00000000000000000000000000000000;
reg [31:0] _3142;
wire _3133;
wire _3134;
wire [31:0] _3136 = 32'b00000000000000000000000000000000;
wire [31:0] _3135 = 32'b00000000000000000000000000000000;
reg [31:0] _3137;
wire _3128;
wire _3129;
wire [31:0] _3131 = 32'b00000000000000000000000000000000;
wire [31:0] _3130 = 32'b00000000000000000000000000000000;
reg [31:0] _3132;
wire _3123;
wire _3124;
wire [31:0] _3126 = 32'b00000000000000000000000000000000;
wire [31:0] _3125 = 32'b00000000000000000000000000000000;
reg [31:0] _3127;
wire _3118;
wire _3119;
wire [31:0] _3121 = 32'b00000000000000000000000000000000;
wire [31:0] _3120 = 32'b00000000000000000000000000000000;
reg [31:0] _3122;
wire _3113;
wire _3114;
wire [31:0] _3116 = 32'b00000000000000000000000000000000;
wire [31:0] _3115 = 32'b00000000000000000000000000000000;
reg [31:0] _3117;
wire _3108;
wire _3109;
wire [31:0] _3111 = 32'b00000000000000000000000000000000;
wire [31:0] _3110 = 32'b00000000000000000000000000000000;
reg [31:0] _3112;
wire _3103;
wire _3104;
wire [31:0] _3106 = 32'b00000000000000000000000000000000;
wire [31:0] _3105 = 32'b00000000000000000000000000000000;
reg [31:0] _3107;
wire _3098;
wire _3099;
wire [31:0] _3101 = 32'b00000000000000000000000000000000;
wire [31:0] _3100 = 32'b00000000000000000000000000000000;
reg [31:0] _3102;
wire _3093;
wire _3094;
wire [31:0] _3096 = 32'b00000000000000000000000000000000;
wire [31:0] _3095 = 32'b00000000000000000000000000000000;
reg [31:0] _3097;
wire _3088;
wire _3089;
wire [31:0] _3091 = 32'b00000000000000000000000000000000;
wire [31:0] _3090 = 32'b00000000000000000000000000000000;
reg [31:0] _3092;
wire _3083;
wire _3084;
wire [31:0] _3086 = 32'b00000000000000000000000000000000;
wire [31:0] _3085 = 32'b00000000000000000000000000000000;
reg [31:0] _3087;
wire _3078;
wire _3079;
wire [31:0] _3081 = 32'b00000000000000000000000000000000;
wire [31:0] _3080 = 32'b00000000000000000000000000000000;
reg [31:0] _3082;
wire _3073;
wire _3074;
wire [31:0] _3076 = 32'b00000000000000000000000000000000;
wire [31:0] _3075 = 32'b00000000000000000000000000000000;
reg [31:0] _3077;
wire _2679;
wire _2682;
wire _2690;
wire _2710;
wire _2758;
wire _2870;
wire _2680;
wire _2681;
wire _2689;
wire _2709;
wire _2757;
wire _2869;
wire _2683;
wire _2685;
wire _2688;
wire _2708;
wire _2756;
wire _2868;
wire _2684;
wire _2686;
wire _2687;
wire _2707;
wire _2755;
wire _2867;
wire _2691;
wire _2694;
wire _2701;
wire _2706;
wire _2754;
wire _2866;
wire _2692;
wire _2693;
wire _2700;
wire _2705;
wire _2753;
wire _2865;
wire _2695;
wire _2697;
wire _2699;
wire _2704;
wire _2752;
wire _2864;
wire _2696;
wire _2698;
wire _2702;
wire _2703;
wire _2751;
wire _2863;
wire _2711;
wire _2714;
wire _2722;
wire _2741;
wire _2750;
wire _2862;
wire _2712;
wire _2713;
wire _2721;
wire _2740;
wire _2749;
wire _2861;
wire _2715;
wire _2717;
wire _2720;
wire _2739;
wire _2748;
wire _2860;
wire _2716;
wire _2718;
wire _2719;
wire _2738;
wire _2747;
wire _2859;
wire _2723;
wire _2726;
wire _2733;
wire _2737;
wire _2746;
wire _2858;
wire _2724;
wire _2725;
wire _2732;
wire _2736;
wire _2745;
wire _2857;
wire _2727;
wire _2729;
wire _2731;
wire _2735;
wire _2744;
wire _2856;
wire _2728;
wire _2730;
wire _2734;
wire _2742;
wire _2743;
wire _2855;
wire _2759;
wire _2762;
wire _2770;
wire _2790;
wire _2837;
wire _2854;
wire _2760;
wire _2761;
wire _2769;
wire _2789;
wire _2836;
wire _2853;
wire _2763;
wire _2765;
wire _2768;
wire _2788;
wire _2835;
wire _2852;
wire _2764;
wire _2766;
wire _2767;
wire _2787;
wire _2834;
wire _2851;
wire _2771;
wire _2774;
wire _2781;
wire _2786;
wire _2833;
wire _2850;
wire _2772;
wire _2773;
wire _2780;
wire _2785;
wire _2832;
wire _2849;
wire _2775;
wire _2777;
wire _2779;
wire _2784;
wire _2831;
wire _2848;
wire _2776;
wire _2778;
wire _2782;
wire _2783;
wire _2830;
wire _2847;
wire _2791;
wire _2794;
wire _2802;
wire _2821;
wire _2829;
wire _2846;
wire _2792;
wire _2793;
wire _2801;
wire _2820;
wire _2828;
wire _2845;
wire _2795;
wire _2797;
wire _2800;
wire _2819;
wire _2827;
wire _2844;
wire _2796;
wire _2798;
wire _2799;
wire _2818;
wire _2826;
wire _2843;
wire _2803;
wire _2806;
wire _2813;
wire _2817;
wire _2825;
wire _2842;
wire _2804;
wire _2805;
wire _2812;
wire _2816;
wire _2824;
wire _2841;
wire _2807;
wire _2809;
wire _2811;
wire _2815;
wire _2823;
wire _2840;
wire _2808;
wire _2810;
wire _2814;
wire _2822;
wire _2838;
wire _2839;
wire _2871;
wire _2874;
wire _2882;
wire _2902;
wire _2950;
wire _3061;
wire _2872;
wire _2873;
wire _2881;
wire _2901;
wire _2949;
wire _3060;
wire _2875;
wire _2877;
wire _2880;
wire _2900;
wire _2948;
wire _3059;
wire _2876;
wire _2878;
wire _2879;
wire _2899;
wire _2947;
wire _3058;
wire _2883;
wire _2886;
wire _2893;
wire _2898;
wire _2946;
wire _3057;
wire _2884;
wire _2885;
wire _2892;
wire _2897;
wire _2945;
wire _3056;
wire _2887;
wire _2889;
wire _2891;
wire _2896;
wire _2944;
wire _3055;
wire _2888;
wire _2890;
wire _2894;
wire _2895;
wire _2943;
wire _3054;
wire _2903;
wire _2906;
wire _2914;
wire _2933;
wire _2942;
wire _3053;
wire _2904;
wire _2905;
wire _2913;
wire _2932;
wire _2941;
wire _3052;
wire _2907;
wire _2909;
wire _2912;
wire _2931;
wire _2940;
wire _3051;
wire _2908;
wire _2910;
wire _2911;
wire _2930;
wire _2939;
wire _3050;
wire _2915;
wire _2918;
wire _2925;
wire _2929;
wire _2938;
wire _3049;
wire _2916;
wire _2917;
wire _2924;
wire _2928;
wire _2937;
wire _3048;
wire _2919;
wire _2921;
wire _2923;
wire _2927;
wire _2936;
wire _3047;
wire _2920;
wire _2922;
wire _2926;
wire _2934;
wire _2935;
wire _3046;
wire _2951;
wire _2954;
wire _2962;
wire _2982;
wire _3029;
wire _3045;
wire _2952;
wire _2953;
wire _2961;
wire _2981;
wire _3028;
wire _3044;
wire _2955;
wire _2957;
wire _2960;
wire _2980;
wire _3027;
wire _3043;
wire _2956;
wire _2958;
wire _2959;
wire _2979;
wire _3026;
wire _3042;
wire _2963;
wire _2966;
wire _2973;
wire _2978;
wire _3025;
wire _3041;
wire _2964;
wire _2965;
wire _2972;
wire _2977;
wire _3024;
wire _3040;
wire _2967;
wire _2969;
wire _2971;
wire _2976;
wire _3023;
wire _3039;
wire _2968;
wire _2970;
wire _2974;
wire _2975;
wire _3022;
wire _3038;
wire _2983;
wire _2986;
wire _2994;
wire _3013;
wire _3021;
wire _3037;
wire _2984;
wire _2985;
wire _2993;
wire _3012;
wire _3020;
wire _3036;
wire _2987;
wire _2989;
wire _2992;
wire _3011;
wire _3019;
wire _3035;
wire _2988;
wire _2990;
wire _2991;
wire _3010;
wire _3018;
wire _3034;
wire _2995;
wire _2998;
wire _3005;
wire _3009;
wire _3017;
wire _3033;
wire _2996;
wire _2997;
wire _3004;
wire _3008;
wire _3016;
wire _3032;
wire _2999;
wire _3001;
wire _3003;
wire _3007;
wire _3015;
wire _3031;
wire _2673;
wire _2674;
wire _3000;
wire _2675;
wire _3002;
wire _2676;
wire _3006;
wire _2677;
wire _3014;
wire [5:0] _2668 = 6'b000000;
wire [5:0] _2666 = 6'b000000;
wire _3562;
wire [4:0] _3565 = 5'b00000;
wire [5:0] _3567;
wire [5:0] _3568 = 6'b100000;
wire [5:0] _3569;
wire [5:0] _3560 = 6'b000100;
wire [5:0] _3559 = 6'b000011;
wire _3561;
wire [5:0] _4975;
wire [5:0] _4976;
wire [5:0] _4977;
wire [5:0] _3744 = 6'b100000;
wire [5:0] _3745;
wire [5:0] _4978;
wire [5:0] _4979;
wire [5:0] _4980;
wire [5:0] _4981;
wire [5:0] _4982;
wire [5:0] _3809 = 6'b000000;
wire [5:0] _4983;
wire _4984;
wire [5:0] _4985;
wire _4986;
wire [5:0] _4987;
wire _4988;
wire [5:0] _4989;
wire [5:0] _2667;
reg [5:0] _2669;
wire _2678;
wire _3030;
wire [63:0] _3062;
wire _3068;
wire _4955;
wire _4956;
wire _4957;
wire _4958;
wire _3663;
wire _3664;
wire _4959;
wire [1:0] _3389 = 2'b00;
wire [1:0] _3387 = 2'b00;
wire [1:0] _3575 = 2'b01;
wire [1:0] _3571 = 2'b10;
wire [1:0] _3570 = 2'b00;
wire [1:0] _3572 = 2'b01;
wire _3573;
wire [1:0] _3574;
wire [1:0] _3576 = 2'b00;
wire _3577;
wire [1:0] _3578;
wire [1:0] _4541;
wire _4542;
wire [1:0] _4543;
wire [1:0] _3388;
reg [1:0] _3390;
wire _3667;
wire _3668;
wire _4960;
wire _4961;
wire _4962;
wire _4963;
wire _4964;
wire _2672;
wire _3069;
wire [31:0] _3071 = 32'b00000000000000000000000000000000;
wire [31:0] _3070 = 32'b00000000000000000000000000000000;
reg [31:0] _3072;
reg [31:0] _3244;
wire [31:0] _3678 = 32'b00000000000000000000000000000000;
wire [5:0] _3679 = 6'b000000;
wire _3680;
wire _3681;
wire [31:0] _3682;
wire [31:0] _3701;
wire _3703;
wire _4453;
wire _3735;
wire _3736;
wire _4454;
wire _4455;
wire _4456;
wire _4457;
wire _4458;
wire _4459;
wire _4460;
wire _4461;
wire _4462;
wire _3435;
reg _3437;
wire _3795;
wire _3796;
wire _3797;
wire _4511;
wire _3325 = 1'b0;
wire _3323 = 1'b0;
wire [3:0] _3960 = 4'b0000;
wire [3:0] _3329 = 4'b0000;
wire [3:0] _3327 = 4'b0000;
wire [3:0] _3963 = 4'b0001;
wire [3:0] _3964;
wire _4944;
wire _4945;
wire _4946;
wire _4947;
wire _4948;
wire _4949;
wire _4950;
wire [3:0] _4951;
wire [3:0] _3962 = 4'b1111;
wire _3965;
wire _2628 = 1'b0;
wire _2626 = 1'b0;
wire _3783 = 1'b0;
wire _3786 = 1'b1;
wire _5157;
wire _5158;
wire _5159;
wire _5160;
wire _3798 = 1'b0;
wire _3800 = 1'b1;
wire _5161;
wire _5162;
wire _5163;
wire _5164;
wire _5165;
wire _5166;
wire _2627;
reg _2629;
wire _3966;
wire [3:0] _4952;
wire [3:0] _4953;
wire [3:0] _3328;
reg [3:0] _3330;
wire _3961;
wire _4954;
wire _3324;
reg _3326;
wire _4512;
wire _4513;
wire _3801;
wire _3802;
wire _4514;
wire _3972;
wire _3973;
wire _3974;
wire _3975;
wire _3976;
wire _4503;
wire _4515;
wire _4516;
wire _4517;
wire _4518;
wire _3400;
wire _3977;
wire _3978;
wire _3979;
wire _3980;
wire _3981;
wire _4502;
wire _3401;
wire _3982;
wire _3983;
wire _3984;
wire _3985;
wire _3986;
wire _4501;
wire _3402;
wire _3987;
wire _3988;
wire _3989;
wire _3990;
wire _3991;
wire _4500;
wire _3403;
wire _3992;
wire _3993;
wire _3994;
wire _3995;
wire _3996;
wire _4499;
wire _3404;
wire _3997;
wire _3998;
wire _3999;
wire _4000;
wire _4001;
wire _4498;
wire _3405;
wire _4002;
wire _4003;
wire _4004;
wire _4005;
wire _4006;
wire _4497;
wire _3406;
wire _4007;
wire _4008;
wire _4009;
wire _4010;
wire _4011;
wire _4496;
wire _3407;
wire _4012;
wire _4013;
wire _4014;
wire _4015;
wire _4016;
wire _4495;
wire _3408;
wire _4017;
wire _4018;
wire _4019;
wire _4020;
wire _4021;
wire _4494;
wire _3409;
wire _4022;
wire _4023;
wire _4024;
wire _4025;
wire _4026;
wire _4493;
wire _3410;
wire _4027;
wire _4028;
wire _4029;
wire _4030;
wire _4031;
wire _4492;
wire _3411;
wire _4032;
wire _4033;
wire _4034;
wire _4035;
wire _4036;
wire _4491;
wire _3412;
wire _4037;
wire _4038;
wire _4039;
wire _4040;
wire _4041;
wire _4490;
wire _3413;
wire _4042;
wire _4043;
wire _4044;
wire _4045;
wire _4046;
wire _4489;
wire _3414;
wire _4047;
wire _4048;
wire _4049;
wire _4050;
wire _4051;
wire _4488;
wire _3415;
wire _4052;
wire _4053;
wire _4054;
wire _4055;
wire _4056;
wire _4487;
wire _3416;
wire _4057;
wire _4058;
wire _4059;
wire _4060;
wire _4061;
wire _4486;
wire _3417;
wire _4062;
wire _4063;
wire _4064;
wire _4065;
wire _4066;
wire _4485;
wire _3418;
wire _4067;
wire _4068;
wire _4069;
wire _4070;
wire _4071;
wire _4484;
wire _3419;
wire _4072;
wire _4073;
wire _4074;
wire _4075;
wire _4076;
wire _4483;
wire _3420;
wire _4077;
wire _4078;
wire _4079;
wire _4080;
wire _4081;
wire _4482;
wire _3421;
wire _4082;
wire _4083;
wire _4084;
wire _4085;
wire _4086;
wire _4481;
wire _3422;
wire _4087;
wire _4088;
wire _4089;
wire _4090;
wire _4091;
wire _4480;
wire _3423;
wire _4092;
wire _4093;
wire _4094;
wire _4095;
wire _4096;
wire _4479;
wire _3424;
wire _4097;
wire _4098;
wire _4099;
wire _4100;
wire _4101;
wire _4478;
wire _3425;
wire _4102;
wire _4103;
wire _4104;
wire _4105;
wire _4106;
wire _4477;
wire _3426;
wire _4107;
wire _4108;
wire _4109;
wire _4110;
wire _4111;
wire _4476;
wire _3427;
wire _4112;
wire _4113;
wire _4114;
wire _4115;
wire _4116;
wire _4475;
wire _3428;
wire _4117;
wire _4118;
wire _4119;
wire _4120;
wire _4121;
wire _4474;
wire _3429;
wire _4122;
wire [31:0] _38 = 32'b11111111111111111111111111111111;
wire _4123;
wire _4124;
wire _4125;
wire _4126;
wire _4473;
wire _3430;
wire [31:0] _3431;
wire _4526;
wire [31:0] _4527;
wire [31:0] _3396;
reg [31:0] _3398;
wire _4907;
wire _4908;
wire _4909;
wire _4910;
wire _4911;
wire _4912;
wire _4913;
wire _4914;
wire _4915;
wire _4916;
wire _4917;
wire _4918;
wire _4919;
wire _4920;
wire _4921;
wire _4922;
wire _4923;
wire _4924;
wire _4925;
wire _4926;
wire _4927;
wire _4928;
wire _4929;
wire _4930;
wire _4931;
wire _4932;
wire _4933;
wire _4934;
wire _4935;
wire _4936;
wire _4937;
wire _4938;
wire _4939;
wire _4940;
wire _4941;
wire _3943 = 1'b0;
wire _4942;
wire _4943;
wire _3332;
reg _3334;
wire _3556;
wire _3557;
wire _3558;
wire _4854;
wire _4855;
wire _3738 = 1'b1;
wire _3741;
wire _3742;
wire _4856;
wire _3746;
wire _3747;
wire _3748;
wire _4857;
wire _3750;
wire _3751;
wire _3752;
wire _4858;
wire _3756;
wire _4859;
wire _3772;
wire _4860;
wire _3787;
wire _4861;
wire _3806;
wire _4862;
wire _4863;
wire _4864;
wire _4865;
wire _4866;
wire _4867;
wire _4868;
wire _3344;
reg _3346;
wire [31:0] _4972;
wire [31:0] _2670 = 32'b00000000000000000000000000000000;
wire _4973;
wire [31:0] _4974;
wire [31:0] _2671;
reg [31:0] _3067;
reg [31:0] _3243;
wire [31:0] _3683 = 32'b00000000000000000000000000000000;
wire [5:0] _3684 = 6'b000000;
wire _3685;
wire _3686;
wire [31:0] _3687;
wire [4:0] _3803;
wire [4:0] _3836 = 5'b00100;
wire [4:0] _3837;
wire [4:0] _3812 = 5'b00001;
wire [4:0] _3813;
wire [4:0] _3863 = 5'b00100;
wire _3864;
wire _3865;
wire [4:0] _4558;
wire [4:0] _4559;
wire [4:0] _4128 = 5'b00000;
wire _4560;
wire [4:0] _4561;
wire _4562;
wire [4:0] _4563;
wire _4564;
wire [4:0] _4565;
wire [4:0] _3384;
reg [4:0] _3386;
wire _3867;
wire [31:0] _5000;
wire [31:0] _3874;
wire _2644 = 1'b0;
wire _2642 = 1'b0;
wire _3936 = 1'b1;
wire _3939 = 1'b0;
wire _5136;
wire _3873 = 1'b1;
wire _4149;
wire _4150;
wire _4151;
wire _4152;
wire _3529;
wire _5137;
wire _2643;
reg _2645;
wire _3885;
wire [31:0] _5001;
wire _3886;
wire _3887;
wire [31:0] _5002;
wire [31:0] _3914;
wire _2640 = 1'b0;
wire _2638 = 1'b0;
wire _3937 = 1'b1;
wire _3940 = 1'b0;
wire _5138;
wire _3913 = 1'b1;
wire _4145;
wire _4146;
wire _4147;
wire _4148;
wire _3530;
wire _5139;
wire _2639;
reg _2641;
wire _3932;
wire [31:0] _5003;
wire [31:0] _5004;
wire _5005;
wire [31:0] _5006;
wire _5007;
wire [31:0] _5008;
wire _5009;
wire [31:0] _5010;
wire _5011;
wire [31:0] _5012;
wire [31:0] _2659;
reg [31:0] _2661;
wire _3245;
wire _3256;
wire _3276;
wire _3259;
wire _3270;
wire _3279;
wire _3273;
wire _3275;
wire _3281;
wire _3283;
wire _3284;
wire _4141;
wire _3810;
wire _4142;
wire gnd = 1'b0;
wire _4143;
wire _4144;
wire _3531;
wire _5135;
wire _2647;
reg _2649;
wire _3945;
wire _5173;
wire _5174;
wire _5175;
wire _5176;
wire _5177;
wire _5178;
wire _2623;
reg _2625;
wire _3648;
wire _3649;
wire _3650;
wire vdd = 1'b1;
wire _3651;
wire _5153;
wire _5154;
wire _5155;
wire _5156;
wire _2631;
reg _2633;
wire _3933;
wire _3934;
wire [2:0] _5237;
wire [2:0] _2595 = 3'b111;
wire _5238;
wire [2:0] _5239;
wire [2:0] _2596 = 3'b110;
wire _5240;
wire [2:0] _5241;
wire [2:0] _2597 = 3'b101;
wire _5242;
wire [2:0] _5243;
wire [2:0] _2598 = 3'b100;
wire _5244;
wire [2:0] _5245;
wire [2:0] _2599 = 3'b011;
wire _5246;
wire [2:0] _5247;
wire [2:0] _2600 = 3'b010;
wire _5248;
wire [2:0] _5249;
wire [2:0] _2602 = 3'b000;
wire _5250;
wire [2:0] _5251;
wire [2:0] _2603;
reg [2:0] _2605;
wire _4845;
wire _4846;
wire _3352;
reg _3354;
wire _5252;
wire [31:0] _5253;
/* logic */
assign _5293 = _2595 == _2605;
assign _5441 = _5293 ? _5292 : _5272;
assign _5314 = _2596 == _2605;
assign _5442 = _5314 ? _5313 : _5441;
assign _5335 = _2597 == _2605;
assign _5443 = _5335 ? _5334 : _5442;
assign _5356 = _2598 == _2605;
assign _5444 = _5356 ? _5355 : _5443;
assign _5377 = _2599 == _2605;
assign _5445 = _5377 ? _5376 : _5444;
assign _5398 = _2600 == _2605;
assign _5446 = _5398 ? _5397 : _5445;
assign _5419 = _2602 == _2605;
assign _5447 = _5419 ? _5418 : _5446;
assign _5440 = _2601 == _2605;
assign ascii_state_0 = _5440 ? _5439 : _5447;
assign _3661 = ~ _3528;
assign _3662 = _3398 & _3661;
assign _5187 = _3664 ? _3662 : _2613;
assign _5188 = _3668 ? _2613 : _5187;
assign _5189 = _3354 ? _2613 : _5188;
assign _5190 = _3346 ? _2613 : _5189;
assign _5191 = _3742 ? _3740 : _2613;
assign _5192 = _3748 ? _2613 : _5191;
assign _5193 = _3752 ? _2613 : _5192;
assign _5194 = _3756 ? _2613 : _5193;
assign _5195 = _3772 ? _2613 : _5194;
assign _5196 = _3787 ? _2613 : _5195;
assign _5197 = _2605 == _2600;
assign _5198 = _5197 ? _5196 : _2613;
assign _5199 = _2605 == _2602;
assign _5200 = _5199 ? _5190 : _5198;
assign _2611 = _5200;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_2613 <= _2610;
else
_2613 <= _2611;
end
assign _5179 = _3872 ? _3869 : _3944;
assign _5180 = _3887 ? _5179 : _3944;
assign _5181 = _3912 ? _3888 : _3944;
assign _5182 = _3934 ? _5181 : _3944;
assign _5183 = _2605 == _2595;
assign _5184 = _5183 ? _5182 : _3944;
assign _5185 = _2605 == _2596;
assign _5186 = _5185 ? _5180 : _5184;
assign _2615 = _5186;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_2617 <= _2614;
else
_2617 <= _2615;
end
assign _2619 = _2625;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_2621 <= _2618;
else
_2621 <= _2619;
end
assign _3881 = _3880 ? _3879 : _3877;
assign _3878 = instr[16:16];
assign _3880 = instr[15:15];
assign _3882 = _3880 | _3878;
assign _3883 = _3882 ? _3881 : _3875;
assign _5140 = _3885 ? _3883 : _2637;
assign _5141 = _3887 ? _5140 : _2637;
assign _3928 = _3927 ? _3924 : _3920;
assign _3921 = instr[14:14];
assign _3922 = instr[11:11];
assign _3923 = _3922 | _3921;
assign _3925 = instr[13:13];
assign _3926 = instr[10:10];
assign _3927 = _3926 | _3925;
assign _3929 = _3927 | _3923;
assign _3930 = _3929 ? _3928 : _3918;
assign _5142 = _3932 ? _3930 : _2637;
assign _5143 = _3934 ? _5142 : _2637;
assign _5144 = _2605 == _2595;
assign _5145 = _5144 ? _5143 : _2637;
assign _5146 = _2605 == _2596;
assign _5147 = _5146 ? _5141 : _5145;
assign _5148 = _2605 == _2602;
assign _5149 = _5148 ? _3674 : _5147;
assign _2635 = _5149;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_2637 <= _2634;
else
_2637 <= _2635;
end
assign _5031 = _2605 == _2601;
assign _5032 = _5031 ? vdd : _4129;
assign _2651 = _5032;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_2653 <= _2650;
else
_2653 <= _2651;
end
assign _4755 = _3398[0:0];
assign _4756 = _3398[1:1];
assign _4757 = _3398[2:2];
assign _4758 = _3398[3:3];
assign _4759 = _3398[4:4];
assign _4760 = _3398[5:5];
assign _4761 = _3398[6:6];
assign _4762 = _3398[7:7];
assign _4763 = _3398[8:8];
assign _4764 = _3398[9:9];
assign _4765 = _3398[10:10];
assign _4766 = _3398[11:11];
assign _4767 = _3398[12:12];
assign _4768 = _3398[13:13];
assign _4769 = _3398[14:14];
assign _4770 = _3398[15:15];
assign _4771 = _3398[16:16];
assign _4772 = _3398[17:17];
assign _4773 = _3398[18:18];
assign _4774 = _3398[19:19];
assign _4775 = _3398[20:20];
assign _4776 = _3398[21:21];
assign _4777 = _3398[22:22];
assign _4778 = _3398[23:23];
assign _4779 = _3398[24:24];
assign _4780 = _3398[25:25];
assign _4781 = _3398[26:26];
assign _4782 = _3398[27:27];
assign _4783 = _3398[28:28];
assign _4784 = _3398[29:29];
assign _4785 = _3398[30:30];
assign _4786 = _3398[31:31];
assign _4787 = _4786 | _4785;
assign _4788 = _4787 | _4784;
assign _4789 = _4788 | _4783;
assign _4790 = _4789 | _4782;
assign _4791 = _4790 | _4781;
assign _4792 = _4791 | _4780;
assign _4793 = _4792 | _4779;
assign _4794 = _4793 | _4778;
assign _4795 = _4794 | _4777;
assign _4796 = _4795 | _4776;
assign _4797 = _4796 | _4775;
assign _4798 = _4797 | _4774;
assign _4799 = _4798 | _4773;
assign _4800 = _4799 | _4772;
assign _4801 = _4800 | _4771;
assign _4802 = _4801 | _4770;
assign _4803 = _4802 | _4769;
assign _4804 = _4803 | _4768;
assign _4805 = _4804 | _4767;
assign _4806 = _4805 | _4766;
assign _4807 = _4806 | _4765;
assign _4808 = _4807 | _4764;
assign _4809 = _4808 | _4763;
assign _4810 = _4809 | _4762;
assign _4811 = _4810 | _4761;
assign _4812 = _4811 | _4760;
assign _4813 = _4812 | _4759;
assign _4814 = _4813 | _4758;
assign _4815 = _4814 | _4757;
assign _4816 = _4815 | _4756;
assign _4817 = _4816 | _4755;
assign _4818 = _4817 ? _3554 : _3657;
assign _4819 = _3558 ? _4818 : _3657;
assign _4820 = _3651 ? _3657 : _4819;
assign _4821 = pcpi_int_ready ? pcpi_int_wr : _3354;
assign _4822 = vdd ? _4821 : _3354;
assign _4823 = vdd ? _4822 : _3354;
assign _4824 = _3700 ? _3697 : _3354;
assign _4825 = _3736 ? _3734 : _4824;
assign _4826 = _3742 ? _3737 : _4825;
assign _4827 = _3748 ? _3743 : _4826;
assign _4828 = _3752 ? _3749 : _4827;
assign _4829 = _3756 ? _3354 : _4828;
assign _4830 = _3772 ? _3757 : _4829;
assign _4831 = _3787 ? _4823 : _4830;
assign _4832 = pcpi_int_ready ? pcpi_int_wr : _3354;
assign _4833 = _3802 ? _4832 : _3354;
assign _4834 = _3810 ? _3284 : _3805;
assign _4835 = _2605 == _2595;
assign _4836 = _4835 ? _3935 : _3354;
assign _4837 = _2605 == _2597;
assign _4838 = _4837 ? _3868 : _4836;
assign _4839 = _2605 == _2598;
assign _4840 = _4839 ? _4834 : _4838;
assign _4841 = _2605 == _2599;
assign _4842 = _4841 ? _4833 : _4840;
assign _4843 = _2605 == _2600;
assign _4844 = _4843 ? _4831 : _4842;
assign _5201 = _3545 ? _2605 : _2600;
assign _5202 = _2625 ? _5201 : _2605;
assign _5203 = _3558 ? _2605 : _5202;
assign _5204 = _3651 ? _2605 : _5203;
assign _5205 = _3782 ? _2602 : _2601;
assign _5206 = _3326 ? _5205 : _2605;
assign _5207 = pcpi_int_ready ? _2602 : _5206;
assign _5208 = vdd ? _5207 : _2599;
assign _5209 = _3777 ? _2602 : _2601;
assign _5210 = vdd ? _5208 : _5209;
assign _5211 = _3688 ? _2597 : _2598;
assign _5212 = _3690 ? _2596 : _5211;
assign _5213 = vdd ? _5212 : _2599;
assign _5214 = _3692 ? _2598 : _5213;
assign _5215 = _3694 ? _2597 : _5214;
assign _5216 = _3696 ? _2595 : _5215;
assign _5217 = _3700 ? _2602 : _5216;
assign _5218 = _3736 ? _2602 : _5217;
assign _5219 = _3742 ? _2602 : _5218;
assign _5220 = _3748 ? _2602 : _5219;
assign _5221 = _3752 ? _2602 : _5220;
assign _5222 = _3756 ? _2598 : _5221;
assign _5223 = _3772 ? _2602 : _5222;
assign _5224 = _3787 ? _5210 : _5223;
assign _5225 = _3797 ? _2602 : _2601;
assign _5226 = _3326 ? _5225 : _2605;
assign _5227 = pcpi_int_ready ? _2602 : _5226;
assign _5228 = _3790 ? _2597 : _2598;
assign _5229 = _3792 ? _2596 : _5228;
assign _5230 = _3802 ? _5227 : _5229;
assign _5231 = mem_done ? _2602 : _2605;
assign _5232 = _3810 ? _5231 : _2602;
assign _5233 = _3867 ? _2602 : _2605;
assign _5234 = _3872 ? _2602 : _2605;
assign _5235 = _3887 ? _5234 : _2605;
assign _5236 = _3912 ? _2602 : _2605;
assign _3536 = instr[43:43];
assign _3537 = ~ _3536;
assign _3538 = instr[3:3];
assign _3539 = ~ _3538;
assign _3540 = _3539 & _3537;
assign _5150 = _3545 ? _2633 : _3540;
assign _5151 = _2625 ? _5150 : _2633;
assign _5152 = _3558 ? _2633 : _5151;
assign _3579 = _3390[0:0];
assign _3580 = _3390[1:1];
assign _3581 = _3580 | _3579;
assign _3584 = _3583[0:0];
assign _3585 = _3583[1:1];
assign _3586 = _3583[2:2];
assign _3587 = _3583[3:3];
assign _3588 = _3583[4:4];
assign _3589 = _3583[5:5];
assign _3590 = _3583[6:6];
assign _3591 = _3583[7:7];
assign _3592 = _3583[8:8];
assign _3593 = _3583[9:9];
assign _3594 = _3583[10:10];
assign _3595 = _3583[11:11];
assign _3596 = _3583[12:12];
assign _3597 = _3583[13:13];
assign _3598 = _3583[14:14];
assign _3599 = _3583[15:15];
assign _3600 = _3583[16:16];
assign _3601 = _3583[17:17];
assign _3602 = _3583[18:18];
assign _3603 = _3583[19:19];
assign _3604 = _3583[20:20];
assign _3605 = _3583[21:21];
assign _3606 = _3583[22:22];
assign _3607 = _3583[23:23];
assign _3608 = _3583[24:24];
assign _3609 = _3583[25:25];
assign _3610 = _3583[26:26];
assign _3611 = _3583[27:27];
assign _3612 = _3583[28:28];
assign _3613 = _3583[29:29];
assign _3614 = _3583[30:30];
assign _3582 = ~ _3528;
assign _3583 = _3398 & _3582;
assign _3615 = _3583[31:31];
assign _3616 = _3615 | _3614;
assign _3617 = _3616 | _3613;
assign _3618 = _3617 | _3612;
assign _3619 = _3618 | _3611;
assign _3620 = _3619 | _3610;
assign _3621 = _3620 | _3609;
assign _3622 = _3621 | _3608;
assign _3623 = _3622 | _3607;
assign _3624 = _3623 | _3606;
assign _3625 = _3624 | _3605;
assign _3626 = _3625 | _3604;
assign _3627 = _3626 | _3603;
assign _3628 = _3627 | _3602;
assign _3629 = _3628 | _3601;
assign _3630 = _3629 | _3600;
assign _3631 = _3630 | _3599;
assign _3632 = _3631 | _3598;
assign _3633 = _3632 | _3597;
assign _3634 = _3633 | _3596;
assign _3635 = _3634 | _3595;
assign _3636 = _3635 | _3594;
assign _3637 = _3636 | _3593;
assign _3638 = _3637 | _3592;
assign _3639 = _3638 | _3591;
assign _3640 = _3639 | _3590;
assign _3641 = _3640 | _3589;
assign _3642 = _3641 | _3588;
assign _3643 = _3642 | _3587;
assign _3644 = _3643 | _3586;
assign _3645 = _3644 | _3585;
assign _3646 = _3645 | _3584;
assign _3647 = ~ _3394;
assign _5167 = _3284 ? _3808 : _3945;
assign _5168 = _3810 ? _5167 : _3945;
assign _3871 = ~ _2633;
assign _3872 = _3871 & mem_done;
assign _5169 = _3872 ? _3870 : _3945;
assign _5170 = _3887 ? _5169 : _3945;
assign _5171 = _3912 ? _3889 : _3945;
assign _5172 = _3934 ? _5171 : _3945;
assign _5036 = _3398[0:0];
assign _5037 = _3398[1:1];
assign _5038 = _3398[2:2];
assign _5039 = _3398[3:3];
assign _5040 = _3398[4:4];
assign _5041 = _3398[5:5];
assign _5042 = _3398[6:6];
assign _5043 = _3398[7:7];
assign _5044 = _3398[8:8];
assign _5045 = _3398[9:9];
assign _5046 = _3398[10:10];
assign _5047 = _3398[11:11];
assign _5048 = _3398[12:12];
assign _5049 = _3398[13:13];
assign _5050 = _3398[14:14];
assign _5051 = _3398[15:15];
assign _5052 = _3398[16:16];
assign _5053 = _3398[17:17];
assign _5054 = _3398[18:18];
assign _5055 = _3398[19:19];
assign _5056 = _3398[20:20];
assign _5057 = _3398[21:21];
assign _5058 = _3398[22:22];
assign _5059 = _3398[23:23];
assign _5060 = _3398[24:24];
assign _5061 = _3398[25:25];
assign _5062 = _3398[26:26];
assign _5063 = _3398[27:27];
assign _5064 = _3398[28:28];
assign _5065 = _3398[29:29];
assign _5066 = _3398[30:30];
assign _5067 = _3398[31:31];
assign _5068 = _5067 | _5066;
assign _5069 = _5068 | _5065;
assign _5070 = _5069 | _5064;
assign _5071 = _5070 | _5063;
assign _5072 = _5071 | _5062;
assign _5073 = _5072 | _5061;
assign _5074 = _5073 | _5060;
assign _5075 = _5074 | _5059;
assign _5076 = _5075 | _5058;
assign _5077 = _5076 | _5057;
assign _5078 = _5077 | _5056;
assign _5079 = _5078 | _5055;
assign _5080 = _5079 | _5054;
assign _5081 = _5080 | _5053;
assign _5082 = _5081 | _5052;
assign _5083 = _5082 | _5051;
assign _5084 = _5083 | _5050;
assign _5085 = _5084 | _5049;
assign _5086 = _5085 | _5048;
assign _5087 = _5086 | _5047;
assign _5088 = _5087 | _5046;
assign _5089 = _5088 | _5045;
assign _5090 = _5089 | _5044;
assign _5091 = _5090 | _5043;
assign _5092 = _5091 | _5042;
assign _5093 = _5092 | _5041;
assign _5094 = _5093 | _5040;
assign _5095 = _5094 | _5039;
assign _5096 = _5095 | _5038;
assign _5097 = _5096 | _5037;
assign _5098 = _5097 | _5036;
assign _5099 = _5098 ? _3551 : _5035;
assign _5100 = _3545 ? _3544 : _3541;
assign _3675 = ~ _3334;
assign _3676 = ~ _2625;
assign _3677 = _3676 & _3675;
assign _5033 = _3668 ? _3665 : _3677;
assign _5034 = _3354 ? _3677 : _5033;
assign _5035 = _3346 ? _3677 : _5034;
assign _5101 = _2625 ? _5100 : _5035;
assign _5102 = _3558 ? _5099 : _5101;
assign _5103 = _3651 ? _5035 : _5102;
assign _5104 = pcpi_int_ready ? _3784 : _2649;
assign _5105 = vdd ? _5104 : _2649;
assign _5106 = vdd ? _5105 : _2649;
assign _3688 = is[5:5];
assign _5107 = _3688 ? _2649 : _2633;
assign _3690 = is[4:4];
assign _5108 = _3690 ? _3689 : _5107;
assign _5109 = vdd ? _5108 : _2649;
assign _5110 = _3692 ? _2633 : _5109;
assign _5111 = _3694 ? _2649 : _5110;
assign _5112 = _3696 ? _3695 : _5111;
assign _5113 = _3700 ? _2649 : _5112;
assign _5114 = _3736 ? _2649 : _5113;
assign _5115 = _3742 ? _2649 : _5114;
assign _5116 = _3748 ? _2649 : _5115;
assign _5117 = _3752 ? _2649 : _5116;
assign _5118 = _3756 ? _2633 : _5117;
assign _5119 = _3772 ? _2649 : _5118;
assign _5120 = _3787 ? _5106 : _5119;
assign _5121 = pcpi_int_ready ? _3799 : _2649;
assign _3790 = is[5:5];
assign _5122 = _3790 ? _2649 : _2633;
assign _3792 = is[4:4];
assign _5123 = _3792 ? _3791 : _5122;
assign _5124 = _3802 ? _5121 : _5123;
assign _5125 = _3867 ? _2633 : _2649;
assign _5126 = _2605 == _2597;
assign _5127 = _5126 ? _5125 : _2649;
assign _5128 = _2605 == _2599;
assign _5129 = _5128 ? _5124 : _5127;
assign _5130 = _2605 == _2600;
assign _5131 = _5130 ? _5120 : _5129;
assign _5132 = _2605 == _2602;
assign _5133 = _5132 ? _5103 : _5131;
assign _5134 = mem_done ? _3941 : _5133;
assign _3274 = _2661 == _2657;
assign _3271 = _2661 == _2657;
assign _3272 = ~ _3271;
assign _3280 = _3275 ? _3274 : _3272;
assign _3260 = _2657[30:0];
assign _3261 = _2657[31:31];
assign _3262 = ~ _3261;
assign _3263 = { _3262, _3260 };
assign _3264 = _2661[30:0];
assign _3265 = _2661[31:31];
assign _3266 = ~ _3265;
assign _3267 = { _3266, _3264 };
assign _3268 = _3267 < _3263;
assign _3269 = ~ _3268;
assign _3257 = _2661 < _2657;
assign _3258 = ~ _3257;
assign _3278 = _3270 ? _3269 : _3258;
assign _3282 = _3281 ? _3280 : _3278;
assign _3247 = _2657[30:0];
assign _3248 = _2657[31:31];
assign _3249 = ~ _3248;
assign _3250 = { _3249, _3247 };
assign _3251 = _2661[30:0];
assign _3252 = _2661[31:31];
assign _3253 = ~ _3252;
assign _3254 = { _3253, _3251 };
assign _3255 = _3254 < _3250;
assign _4990 = vdd ? _3682 : _3789;
assign _3754 = instr[0:0];
assign _3755 = _3754 ? _3753 : _3372;
assign _4991 = _3700 ? _3789 : _3682;
assign _4992 = _3736 ? _3789 : _4991;
assign _4993 = _3742 ? _3789 : _4992;
assign _4994 = _3748 ? _3789 : _4993;
assign _4995 = _3752 ? _3789 : _4994;
assign _4996 = _3756 ? _3755 : _4995;
assign _4997 = _3772 ? _3789 : _4996;
assign _4998 = _3787 ? _4990 : _4997;
assign _3854 = _2661[27:0];
assign _3855 = { _3854, _3853 };
assign _3847 = _2661[31:4];
assign _3849 = { _3848, _3847 };
assign _3859 = _3858 ? _3855 : _3849;
assign _3838 = _2661[31:4];
assign _3839 = _2661[31:31];
assign _3840 = { _3839, _3839 };
assign _3841 = { _3840, _3840 };
assign _3843 = { _3841, _3838 };
assign _3850 = instr[33:33];
assign _3851 = instr[25:25];
assign _3852 = _3851 | _3850;
assign _3856 = instr[29:29];
assign _3857 = instr[24:24];
assign _3858 = _3857 | _3856;
assign _3860 = _3858 | _3852;
assign _3861 = _3860 ? _3859 : _3843;
assign _3827 = _2661[30:0];
assign _3828 = { _3827, _3826 };
assign _3820 = _2661[31:1];
assign _3822 = { _3821, _3820 };
assign _3832 = _3831 ? _3828 : _3822;
assign _3814 = _2661[31:1];
assign _3815 = _2661[31:31];
assign _3816 = { _3815, _3814 };
assign _3823 = instr[33:33];
assign _3824 = instr[25:25];
assign _3825 = _3824 | _3823;
assign _3829 = instr[29:29];
assign _3830 = instr[24:24];
assign _3831 = _3830 | _3829;
assign _3833 = _3831 | _3825;
assign _3834 = _3833 ? _3832 : _3816;
assign _4999 = _3865 ? _3861 : _3834;
assign _3785 = _3687[4:0];
assign _4544 = vdd ? _3785 : _4128;
assign _4545 = vdd ? _4544 : _4128;
assign _3693 = decoded_rs2[4:0];
assign _3691 = _3687[4:0];
assign _4546 = vdd ? _3691 : _4128;
assign _4547 = _3692 ? _4128 : _4546;
assign _4548 = _3694 ? _3693 : _4547;
assign _4549 = _3696 ? _4128 : _4548;
assign _4550 = _3700 ? _4128 : _4549;
assign _4551 = _3736 ? _4128 : _4550;
assign _4552 = _3742 ? _4128 : _4551;
assign _4553 = _3748 ? _4128 : _4552;
assign _4554 = _3752 ? _4128 : _4553;
assign _4555 = _3756 ? _4128 : _4554;
assign _4556 = _3772 ? _4128 : _4555;
assign _4557 = _3787 ? _4545 : _4556;
assign _3063 = _3062[0:0];
assign _3064 = _2672 & _3063;
assign _3671 = _3372 + _3670;
assign _4965 = vdd ? _3671 : _2670;
assign _3669 = _3350 ? _3378 : _3382;
assign _4966 = vdd ? _3669 : _2670;
assign _3553 = _3374 + _3552;
assign _4667 = _3398[0:0];
assign _4668 = _3398[1:1];
assign _4669 = _3398[2:2];
assign _4670 = _3398[3:3];
assign _4671 = _3398[4:4];
assign _4672 = _3398[5:5];
assign _4673 = _3398[6:6];
assign _4674 = _3398[7:7];
assign _4675 = _3398[8:8];
assign _4676 = _3398[9:9];
assign _4677 = _3398[10:10];
assign _4678 = _3398[11:11];
assign _4679 = _3398[12:12];
assign _4680 = _3398[13:13];
assign _4681 = _3398[14:14];
assign _4682 = _3398[15:15];
assign _4683 = _3398[16:16];
assign _4684 = _3398[17:17];
assign _4685 = _3398[18:18];
assign _4686 = _3398[19:19];
assign _4687 = _3398[20:20];
assign _4688 = _3398[21:21];
assign _4689 = _3398[22:22];
assign _4690 = _3398[23:23];
assign _4691 = _3398[24:24];
assign _4692 = _3398[25:25];
assign _4693 = _3398[26:26];
assign _4694 = _3398[27:27];
assign _4695 = _3398[28:28];
assign _4696 = _3398[29:29];
assign _4697 = _3398[30:30];
assign _4698 = _3398[31:31];
assign _4699 = _4698 | _4697;
assign _4700 = _4699 | _4696;
assign _4701 = _4700 | _4695;
assign _4702 = _4701 | _4694;
assign _4703 = _4702 | _4693;
assign _4704 = _4703 | _4692;
assign _4705 = _4704 | _4691;
assign _4706 = _4705 | _4690;
assign _4707 = _4706 | _4689;
assign _4708 = _4707 | _4688;
assign _4709 = _4708 | _4687;
assign _4710 = _4709 | _4686;
assign _4711 = _4710 | _4685;
assign _4712 = _4711 | _4684;
assign _4713 = _4712 | _4683;
assign _4714 = _4713 | _4682;
assign _4715 = _4714 | _4681;
assign _4716 = _4715 | _4680;
assign _4717 = _4716 | _4679;
assign _4718 = _4717 | _4678;
assign _4719 = _4718 | _4677;
assign _4720 = _4719 | _4676;
assign _4721 = _4720 | _4675;
assign _4722 = _4721 | _4674;
assign _4723 = _4722 | _4673;
assign _4724 = _4723 | _4672;
assign _4725 = _4724 | _4671;
assign _4726 = _4725 | _4670;
assign _4727 = _4726 | _4669;
assign _4728 = _4727 | _4668;
assign _4729 = _4728 | _4667;
assign _4730 = _4729 ? _3553 : _3374;
assign _3543 = _3374 + decoded_imm_uj;
assign _3549 = _3374 + _3548;
assign _4731 = _3545 ? _3543 : _3549;
assign _3311 = _2661 + _2657;
assign _3309 = _2661 - _2657;
assign _3317 = _3312 ? _3311 : _3309;
assign _3307 = { _3305, _3284 };
assign _3294 = _2661 ^ _2657;
assign _3315 = _3308 ? _3307 : _3294;
assign _3319 = _3318 ? _3317 : _3315;
assign _3290 = _2661 | _2657;
assign _5013 = vdd ? _3687 : _3788;
assign _5014 = vdd ? _5013 : _3788;
assign _5015 = vdd ? _3687 : _3788;
assign _3692 = is[3:3];
assign _5016 = _3692 ? decoded_imm : _5015;
assign _3694 = is[2:2];
assign _5017 = _3694 ? _3788 : _5016;
assign _3696 = is[1:1];
assign _5018 = _3696 ? _3788 : _5017;
assign _5019 = _3700 ? _3788 : _5018;
assign _5020 = _3736 ? _3788 : _5019;
assign _5021 = _3742 ? _3788 : _5020;
assign _5022 = _3748 ? _3788 : _5021;
assign _5023 = _3752 ? _3788 : _5022;
assign _5024 = _3756 ? decoded_imm : _5023;
assign _5025 = _3772 ? _3788 : _5024;
assign _5026 = _3787 ? _5014 : _5025;
assign _5027 = _2605 == _2599;
assign _5028 = _5027 ? _3687 : _2657;
assign _5029 = _2605 == _2600;
assign _5030 = _5029 ? _5026 : _5028;
assign _2655 = _5030;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_2657 <= _2654;
else
_2657 <= _2655;
end
assign _3286 = _2661 & _2657;
assign _3291 = instr[35:35];
assign _3292 = instr[22:22];
assign _3293 = _3292 | _3291;
assign _3313 = _3293 ? _3290 : _3286;
assign _3295 = instr[32:32];
assign _3296 = instr[21:21];
assign _3297 = _3296 | _3295;
assign _3308 = is[13:13];
assign _3316 = _3308 | _3297;
assign _3310 = instr[28:28];
assign _3312 = is[6:6];
assign _3318 = _3312 | _3310;
assign _3320 = _3318 | _3316;
assign _3321 = _3320 ? _3319 : _3313;
assign _3376 = _3321;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_3378 <= _3375;
else
_3378 <= _3376;
end
assign _4566 = _3398[0:0];
assign _4567 = _3398[1:1];
assign _4568 = _3398[2:2];
assign _4569 = _3398[3:3];
assign _4570 = _3398[4:4];
assign _4571 = _3398[5:5];
assign _4572 = _3398[6:6];
assign _4573 = _3398[7:7];
assign _4574 = _3398[8:8];
assign _4575 = _3398[9:9];
assign _4576 = _3398[10:10];
assign _4577 = _3398[11:11];
assign _4578 = _3398[12:12];
assign _4579 = _3398[13:13];
assign _4580 = _3398[14:14];
assign _4581 = _3398[15:15];
assign _4582 = _3398[16:16];
assign _4583 = _3398[17:17];
assign _4584 = _3398[18:18];
assign _4585 = _3398[19:19];
assign _4586 = _3398[20:20];
assign _4587 = _3398[21:21];
assign _4588 = _3398[22:22];
assign _4589 = _3398[23:23];
assign _4590 = _3398[24:24];
assign _4591 = _3398[25:25];
assign _4592 = _3398[26:26];
assign _4593 = _3398[27:27];
assign _4594 = _3398[28:28];
assign _4595 = _3398[29:29];
assign _4596 = _3398[30:30];
assign _4597 = _3398[31:31];
assign _4598 = _4597 | _4596;
assign _4599 = _4598 | _4595;
assign _4600 = _4599 | _4594;
assign _4601 = _4600 | _4593;
assign _4602 = _4601 | _4592;
assign _4603 = _4602 | _4591;
assign _4604 = _4603 | _4590;
assign _4605 = _4604 | _4589;
assign _4606 = _4605 | _4588;
assign _4607 = _4606 | _4587;
assign _4608 = _4607 | _4586;
assign _4609 = _4608 | _4585;
assign _4610 = _4609 | _4584;
assign _4611 = _4610 | _4583;
assign _4612 = _4611 | _4582;
assign _4613 = _4612 | _4581;
assign _4614 = _4613 | _4580;
assign _4615 = _4614 | _4579;
assign _4616 = _4615 | _4578;
assign _4617 = _4616 | _4577;
assign _4618 = _4617 | _4576;
assign _4619 = _4618 | _4575;
assign _4620 = _4619 | _4574;
assign _4621 = _4620 | _4573;
assign _4622 = _4621 | _4572;
assign _4623 = _4622 | _4571;
assign _4624 = _4623 | _4570;
assign _4625 = _4624 | _4569;
assign _4626 = _4625 | _4568;
assign _4627 = _4626 | _4567;
assign _4628 = _4627 | _4566;
assign _4629 = _4628 ? _3398 : _4127;
assign _4630 = _3558 ? _4629 : _4127;
assign _4631 = _3651 ? _4127 : _4630;
assign _4632 = pcpi_int_ready ? pcpi_int_rd : _4127;
assign _4633 = vdd ? _4632 : _4127;
assign _4634 = vdd ? _4633 : _4127;
assign _3764 = count_cycle[31:0];
assign _3959 = count_cycle + _3958;
assign _4869 = vdd ? _3959 : count_cycle;
assign _3340 = _4869;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
count_cycle <= _3339;
else
count_cycle <= _3340;
end
assign _3762 = count_cycle[63:32];
assign _3768 = _3765 ? _3764 : _3762;
assign _3760 = _3338[31:0];
assign _3547 = _3338 + _3546;
assign _4870 = vdd ? _3547 : _3338;
assign _4871 = _2625 ? _4870 : _3338;
assign _4872 = _3558 ? _3338 : _4871;
assign _4873 = _3651 ? _3338 : _4872;
assign _4874 = _2605 == _2602;
assign _4875 = _4874 ? _4873 : _3338;
assign _3336 = _4875;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_3338 <= _3335;
else
_3338 <= _3336;
end
assign _3758 = _3338[63:32];
assign _3761 = instr[39:39];
assign _3766 = _3761 ? _3760 : _3758;
assign _3763 = instr[38:38];
assign _3765 = instr[37:37];
assign _3769 = _3765 | _3763;
assign _3770 = _3769 ? _3768 : _3766;
assign _4635 = _3700 ? _3535 : _4127;
assign _4636 = _3736 ? _3528 : _4635;
assign _4637 = _3742 ? _3244 : _4636;
assign _4638 = _3748 ? _3244 : _4637;
assign _4639 = _3752 ? _3244 : _4638;
assign _4640 = _3756 ? _4127 : _4639;
assign _4641 = _3772 ? _3770 : _4640;
assign _4642 = _3787 ? _4634 : _4641;
assign _4643 = pcpi_int_ready ? pcpi_int_rd : _4127;
assign _4644 = _3802 ? _4643 : _4127;
assign _4665 = _2605 == _2602;
assign _4666 = _4665 ? _3374 : _3372;
assign _3370 = _4666;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_3372 <= _39;
else
_3372 <= _3370;
end
assign _3811 = _3372 + decoded_imm;
assign _4645 = _3867 ? _2661 : _4127;
assign _3899 = mem_rdata_word[15:0];
assign _3900 = _3899[15:15];
assign _3901 = { _3900, _3900 };
assign _3902 = { _3901, _3901 };
assign _3903 = { _3902, _3902 };
assign _3904 = { _3903, _3903 };
assign _3906 = { _3904, _3899 };
assign _3907 = _3366 ? mem_rdata_word : _3906;
assign _3890 = mem_rdata_word[7:0];
assign _3891 = _3890[7:7];
assign _3892 = { _3891, _3891 };
assign _3893 = { _3892, _3892 };
assign _3894 = { _3893, _3893 };
assign _3895 = { _3894, _3894 };
assign _3896 = { _3895, _3894 };
assign _3898 = { _3896, _3890 };
assign _3916 = instr[11:11];
assign _4743 = _3932 ? _3916 : _3362;
assign _4744 = _3934 ? _4743 : _3362;
assign _4745 = _2605 == _2595;
assign _4746 = _4745 ? _4744 : _3362;
assign _4747 = _2605 == _2602;
assign _4748 = _4747 ? _3653 : _4746;
assign _3360 = _4748;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_3362 <= _3359;
else
_3362 <= _3360;
end
assign _3917 = is[10:10];
assign _4737 = _3932 ? _3917 : _3366;
assign _4738 = _3934 ? _4737 : _3366;
assign _4739 = _2605 == _2595;
assign _4740 = _4739 ? _4738 : _3366;
assign _4741 = _2605 == _2602;
assign _4742 = _4741 ? _3654 : _4740;
assign _3364 = _4742;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_3366 <= _3363;
else
_3366 <= _3364;
end
assign _3908 = _3366 | _3362;
assign _3909 = _3908 ? _3907 : _3898;
assign _3911 = ~ _2633;
assign _3912 = _3911 & mem_done;
assign _4646 = _3912 ? _3909 : _4127;
assign _4647 = _3934 ? _4646 : _4127;
assign _4648 = _2605 == _2595;
assign _4649 = _4648 ? _4647 : _4127;
assign _4650 = _2605 == _2597;
assign _4651 = _4650 ? _4645 : _4649;
assign _4652 = _2605 == _2598;
assign _4653 = _4652 ? _3811 : _4651;
assign _4654 = _2605 == _2599;
assign _4655 = _4654 ? _4644 : _4653;
assign _4656 = _2605 == _2600;
assign _4657 = _4656 ? _4642 : _4655;
assign _4658 = _2605 == _2602;
assign _4659 = _4658 ? _4631 : _4657;
assign _3380 = _4659;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_3382 <= _3379;
else
_3382 <= _3380;
end
assign _4847 = _3810 ? _3350 : _3804;
assign _4848 = _2605 == _2598;
assign _4849 = _4848 ? _4847 : _3350;
assign _4850 = _2605 == _2602;
assign _4851 = _4850 ? _3656 : _4849;
assign _3348 = _4851;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_3350 <= _3347;
else
_3350 <= _3348;
end
assign _3672 = _3350 ? _3378 : _3382;
assign _3673 = _3354 ? _3672 : _3369;
assign _4660 = _3668 ? _40 : _3369;
assign _4661 = _3354 ? _3369 : _4660;
assign _4662 = _3346 ? _3673 : _4661;
assign _4663 = _2605 == _2602;
assign _4664 = _4663 ? _4662 : _3373;
assign _3374 = _4664;
assign _4732 = _2625 ? _4731 : _3374;
assign _4733 = _3558 ? _4730 : _4732;
assign _4734 = _3651 ? _3374 : _4733;
assign _4735 = _2605 == _2602;
assign _4736 = _4735 ? _4734 : _3369;
assign _3367 = _4736;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_3369 <= _39;
else
_3369 <= _3367;
end
assign _4967 = vdd ? _3369 : _2670;
assign _3659 = ~ _3528;
assign _3660 = _3398 & _3659;
assign _4968 = vdd ? _3660 : _2670;
assign _4969 = _3664 ? _4968 : _2670;
assign _4970 = _3668 ? _4967 : _4969;
assign _4971 = _3354 ? _4966 : _4970;
assign _3545 = instr[2:2];
assign _4852 = _3545 ? _3542 : _3655;
assign _4853 = _2625 ? _4852 : _3655;
assign _3555 = instr[45:45];
assign _4876 = _3398[0:0];
assign _4877 = _3398[1:1];
assign _4878 = _3398[2:2];
assign _4879 = _3398[3:3];
assign _4880 = _3398[4:4];
assign _4881 = _3398[5:5];
assign _4882 = _3398[6:6];
assign _4883 = _3398[7:7];
assign _4884 = _3398[8:8];
assign _4885 = _3398[9:9];
assign _4886 = _3398[10:10];
assign _4887 = _3398[11:11];
assign _4888 = _3398[12:12];
assign _4889 = _3398[13:13];
assign _4890 = _3398[14:14];
assign _4891 = _3398[15:15];
assign _4892 = _3398[16:16];
assign _4893 = _3398[17:17];
assign _4894 = _3398[18:18];
assign _4895 = _3398[19:19];
assign _4896 = _3398[20:20];
assign _4897 = _3398[21:21];
assign _4898 = _3398[22:22];
assign _4899 = _3398[23:23];
assign _4900 = _3398[24:24];
assign _4901 = _3398[25:25];
assign _4902 = _3398[26:26];
assign _4903 = _3398[27:27];
assign _4904 = _3398[28:28];
assign _4905 = _3398[29:29];
assign _4906 = _3398[30:30];
assign _3702 = _3701[0:0];
assign _4463 = vdd ? _3702 : _3434;
assign _4464 = _3736 ? _4463 : _3434;
assign _4465 = _3742 ? _3434 : _4464;
assign _4466 = _3748 ? _3434 : _4465;
assign _4467 = _3752 ? _3434 : _4466;
assign _4468 = _3756 ? _3434 : _4467;
assign _4469 = _3772 ? _3434 : _4468;
assign _4470 = _3787 ? _3434 : _4469;
assign _4471 = _2605 == _2600;
assign _4472 = _4471 ? _4470 : _3434;
assign _3432 = _4472;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_3434 <= vdd;
else
_3434 <= _3432;
end
assign _3704 = _3701[2:2];
assign _4443 = vdd ? _3704 : _3440;
assign _4444 = _3736 ? _4443 : _3440;
assign _4445 = _3742 ? _3440 : _4444;
assign _4446 = _3748 ? _3440 : _4445;
assign _4447 = _3752 ? _3440 : _4446;
assign _4448 = _3756 ? _3440 : _4447;
assign _4449 = _3772 ? _3440 : _4448;
assign _4450 = _3787 ? _3440 : _4449;
assign _4451 = _2605 == _2600;
assign _4452 = _4451 ? _4450 : _3440;
assign _3438 = _4452;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_3440 <= vdd;
else
_3440 <= _3438;
end
assign _3705 = _3701[3:3];
assign _4433 = vdd ? _3705 : _3443;
assign _4434 = _3736 ? _4433 : _3443;
assign _4435 = _3742 ? _3443 : _4434;
assign _4436 = _3748 ? _3443 : _4435;
assign _4437 = _3752 ? _3443 : _4436;
assign _4438 = _3756 ? _3443 : _4437;
assign _4439 = _3772 ? _3443 : _4438;
assign _4440 = _3787 ? _3443 : _4439;
assign _4441 = _2605 == _2600;
assign _4442 = _4441 ? _4440 : _3443;
assign _3441 = _4442;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_3443 <= vdd;
else
_3443 <= _3441;
end
assign _3706 = _3701[4:4];
assign _4423 = vdd ? _3706 : _3446;
assign _4424 = _3736 ? _4423 : _3446;
assign _4425 = _3742 ? _3446 : _4424;
assign _4426 = _3748 ? _3446 : _4425;
assign _4427 = _3752 ? _3446 : _4426;
assign _4428 = _3756 ? _3446 : _4427;
assign _4429 = _3772 ? _3446 : _4428;
assign _4430 = _3787 ? _3446 : _4429;
assign _4431 = _2605 == _2600;
assign _4432 = _4431 ? _4430 : _3446;
assign _3444 = _4432;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_3446 <= vdd;
else
_3446 <= _3444;
end
assign _3707 = _3701[5:5];
assign _4413 = vdd ? _3707 : _3449;
assign _4414 = _3736 ? _4413 : _3449;
assign _4415 = _3742 ? _3449 : _4414;
assign _4416 = _3748 ? _3449 : _4415;
assign _4417 = _3752 ? _3449 : _4416;
assign _4418 = _3756 ? _3449 : _4417;
assign _4419 = _3772 ? _3449 : _4418;
assign _4420 = _3787 ? _3449 : _4419;
assign _4421 = _2605 == _2600;
assign _4422 = _4421 ? _4420 : _3449;
assign _3447 = _4422;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_3449 <= vdd;
else
_3449 <= _3447;
end
assign _3708 = _3701[6:6];
assign _4403 = vdd ? _3708 : _3452;
assign _4404 = _3736 ? _4403 : _3452;
assign _4405 = _3742 ? _3452 : _4404;
assign _4406 = _3748 ? _3452 : _4405;
assign _4407 = _3752 ? _3452 : _4406;
assign _4408 = _3756 ? _3452 : _4407;
assign _4409 = _3772 ? _3452 : _4408;
assign _4410 = _3787 ? _3452 : _4409;
assign _4411 = _2605 == _2600;
assign _4412 = _4411 ? _4410 : _3452;
assign _3450 = _4412;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_3452 <= vdd;
else
_3452 <= _3450;
end
assign _3709 = _3701[7:7];
assign _4393 = vdd ? _3709 : _3455;
assign _4394 = _3736 ? _4393 : _3455;
assign _4395 = _3742 ? _3455 : _4394;
assign _4396 = _3748 ? _3455 : _4395;
assign _4397 = _3752 ? _3455 : _4396;
assign _4398 = _3756 ? _3455 : _4397;
assign _4399 = _3772 ? _3455 : _4398;
assign _4400 = _3787 ? _3455 : _4399;
assign _4401 = _2605 == _2600;
assign _4402 = _4401 ? _4400 : _3455;
assign _3453 = _4402;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_3455 <= vdd;
else
_3455 <= _3453;
end
assign _3710 = _3701[8:8];
assign _4383 = vdd ? _3710 : _3458;
assign _4384 = _3736 ? _4383 : _3458;
assign _4385 = _3742 ? _3458 : _4384;
assign _4386 = _3748 ? _3458 : _4385;
assign _4387 = _3752 ? _3458 : _4386;
assign _4388 = _3756 ? _3458 : _4387;
assign _4389 = _3772 ? _3458 : _4388;
assign _4390 = _3787 ? _3458 : _4389;
assign _4391 = _2605 == _2600;
assign _4392 = _4391 ? _4390 : _3458;
assign _3456 = _4392;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_3458 <= vdd;
else
_3458 <= _3456;
end
assign _3711 = _3701[9:9];
assign _4373 = vdd ? _3711 : _3461;
assign _4374 = _3736 ? _4373 : _3461;
assign _4375 = _3742 ? _3461 : _4374;
assign _4376 = _3748 ? _3461 : _4375;
assign _4377 = _3752 ? _3461 : _4376;
assign _4378 = _3756 ? _3461 : _4377;
assign _4379 = _3772 ? _3461 : _4378;
assign _4380 = _3787 ? _3461 : _4379;
assign _4381 = _2605 == _2600;
assign _4382 = _4381 ? _4380 : _3461;
assign _3459 = _4382;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_3461 <= vdd;
else
_3461 <= _3459;
end
assign _3712 = _3701[10:10];
assign _4363 = vdd ? _3712 : _3464;
assign _4364 = _3736 ? _4363 : _3464;
assign _4365 = _3742 ? _3464 : _4364;
assign _4366 = _3748 ? _3464 : _4365;
assign _4367 = _3752 ? _3464 : _4366;
assign _4368 = _3756 ? _3464 : _4367;
assign _4369 = _3772 ? _3464 : _4368;
assign _4370 = _3787 ? _3464 : _4369;
assign _4371 = _2605 == _2600;
assign _4372 = _4371 ? _4370 : _3464;
assign _3462 = _4372;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_3464 <= vdd;
else
_3464 <= _3462;
end
assign _3713 = _3701[11:11];
assign _4353 = vdd ? _3713 : _3467;
assign _4354 = _3736 ? _4353 : _3467;
assign _4355 = _3742 ? _3467 : _4354;
assign _4356 = _3748 ? _3467 : _4355;
assign _4357 = _3752 ? _3467 : _4356;
assign _4358 = _3756 ? _3467 : _4357;
assign _4359 = _3772 ? _3467 : _4358;
assign _4360 = _3787 ? _3467 : _4359;
assign _4361 = _2605 == _2600;
assign _4362 = _4361 ? _4360 : _3467;
assign _3465 = _4362;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_3467 <= vdd;
else
_3467 <= _3465;
end
assign _3714 = _3701[12:12];
assign _4343 = vdd ? _3714 : _3470;
assign _4344 = _3736 ? _4343 : _3470;
assign _4345 = _3742 ? _3470 : _4344;
assign _4346 = _3748 ? _3470 : _4345;
assign _4347 = _3752 ? _3470 : _4346;
assign _4348 = _3756 ? _3470 : _4347;
assign _4349 = _3772 ? _3470 : _4348;
assign _4350 = _3787 ? _3470 : _4349;
assign _4351 = _2605 == _2600;
assign _4352 = _4351 ? _4350 : _3470;
assign _3468 = _4352;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_3470 <= vdd;
else
_3470 <= _3468;
end
assign _3715 = _3701[13:13];
assign _4333 = vdd ? _3715 : _3473;
assign _4334 = _3736 ? _4333 : _3473;
assign _4335 = _3742 ? _3473 : _4334;
assign _4336 = _3748 ? _3473 : _4335;
assign _4337 = _3752 ? _3473 : _4336;
assign _4338 = _3756 ? _3473 : _4337;
assign _4339 = _3772 ? _3473 : _4338;
assign _4340 = _3787 ? _3473 : _4339;
assign _4341 = _2605 == _2600;
assign _4342 = _4341 ? _4340 : _3473;
assign _3471 = _4342;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_3473 <= vdd;
else
_3473 <= _3471;
end
assign _3716 = _3701[14:14];
assign _4323 = vdd ? _3716 : _3476;
assign _4324 = _3736 ? _4323 : _3476;
assign _4325 = _3742 ? _3476 : _4324;
assign _4326 = _3748 ? _3476 : _4325;
assign _4327 = _3752 ? _3476 : _4326;
assign _4328 = _3756 ? _3476 : _4327;
assign _4329 = _3772 ? _3476 : _4328;
assign _4330 = _3787 ? _3476 : _4329;
assign _4331 = _2605 == _2600;
assign _4332 = _4331 ? _4330 : _3476;
assign _3474 = _4332;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_3476 <= vdd;
else
_3476 <= _3474;
end
assign _3717 = _3701[15:15];
assign _4313 = vdd ? _3717 : _3479;
assign _4314 = _3736 ? _4313 : _3479;
assign _4315 = _3742 ? _3479 : _4314;
assign _4316 = _3748 ? _3479 : _4315;
assign _4317 = _3752 ? _3479 : _4316;
assign _4318 = _3756 ? _3479 : _4317;
assign _4319 = _3772 ? _3479 : _4318;
assign _4320 = _3787 ? _3479 : _4319;
assign _4321 = _2605 == _2600;
assign _4322 = _4321 ? _4320 : _3479;
assign _3477 = _4322;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_3479 <= vdd;
else
_3479 <= _3477;
end
assign _3718 = _3701[16:16];
assign _4303 = vdd ? _3718 : _3482;
assign _4304 = _3736 ? _4303 : _3482;
assign _4305 = _3742 ? _3482 : _4304;
assign _4306 = _3748 ? _3482 : _4305;
assign _4307 = _3752 ? _3482 : _4306;
assign _4308 = _3756 ? _3482 : _4307;
assign _4309 = _3772 ? _3482 : _4308;
assign _4310 = _3787 ? _3482 : _4309;
assign _4311 = _2605 == _2600;
assign _4312 = _4311 ? _4310 : _3482;
assign _3480 = _4312;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_3482 <= vdd;
else
_3482 <= _3480;
end
assign _3719 = _3701[17:17];
assign _4293 = vdd ? _3719 : _3485;
assign _4294 = _3736 ? _4293 : _3485;
assign _4295 = _3742 ? _3485 : _4294;
assign _4296 = _3748 ? _3485 : _4295;
assign _4297 = _3752 ? _3485 : _4296;
assign _4298 = _3756 ? _3485 : _4297;
assign _4299 = _3772 ? _3485 : _4298;
assign _4300 = _3787 ? _3485 : _4299;
assign _4301 = _2605 == _2600;
assign _4302 = _4301 ? _4300 : _3485;
assign _3483 = _4302;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_3485 <= vdd;
else
_3485 <= _3483;
end
assign _3720 = _3701[18:18];
assign _4283 = vdd ? _3720 : _3488;
assign _4284 = _3736 ? _4283 : _3488;
assign _4285 = _3742 ? _3488 : _4284;
assign _4286 = _3748 ? _3488 : _4285;
assign _4287 = _3752 ? _3488 : _4286;
assign _4288 = _3756 ? _3488 : _4287;
assign _4289 = _3772 ? _3488 : _4288;
assign _4290 = _3787 ? _3488 : _4289;
assign _4291 = _2605 == _2600;
assign _4292 = _4291 ? _4290 : _3488;
assign _3486 = _4292;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_3488 <= vdd;
else
_3488 <= _3486;
end
assign _3721 = _3701[19:19];
assign _4273 = vdd ? _3721 : _3491;
assign _4274 = _3736 ? _4273 : _3491;
assign _4275 = _3742 ? _3491 : _4274;
assign _4276 = _3748 ? _3491 : _4275;
assign _4277 = _3752 ? _3491 : _4276;
assign _4278 = _3756 ? _3491 : _4277;
assign _4279 = _3772 ? _3491 : _4278;
assign _4280 = _3787 ? _3491 : _4279;
assign _4281 = _2605 == _2600;
assign _4282 = _4281 ? _4280 : _3491;
assign _3489 = _4282;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_3491 <= vdd;
else
_3491 <= _3489;
end
assign _3722 = _3701[20:20];
assign _4263 = vdd ? _3722 : _3494;
assign _4264 = _3736 ? _4263 : _3494;
assign _4265 = _3742 ? _3494 : _4264;
assign _4266 = _3748 ? _3494 : _4265;
assign _4267 = _3752 ? _3494 : _4266;
assign _4268 = _3756 ? _3494 : _4267;
assign _4269 = _3772 ? _3494 : _4268;
assign _4270 = _3787 ? _3494 : _4269;
assign _4271 = _2605 == _2600;
assign _4272 = _4271 ? _4270 : _3494;
assign _3492 = _4272;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_3494 <= vdd;
else
_3494 <= _3492;
end
assign _3723 = _3701[21:21];
assign _4253 = vdd ? _3723 : _3497;
assign _4254 = _3736 ? _4253 : _3497;
assign _4255 = _3742 ? _3497 : _4254;
assign _4256 = _3748 ? _3497 : _4255;
assign _4257 = _3752 ? _3497 : _4256;
assign _4258 = _3756 ? _3497 : _4257;
assign _4259 = _3772 ? _3497 : _4258;
assign _4260 = _3787 ? _3497 : _4259;
assign _4261 = _2605 == _2600;
assign _4262 = _4261 ? _4260 : _3497;
assign _3495 = _4262;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_3497 <= vdd;
else
_3497 <= _3495;
end
assign _3724 = _3701[22:22];
assign _4243 = vdd ? _3724 : _3500;
assign _4244 = _3736 ? _4243 : _3500;
assign _4245 = _3742 ? _3500 : _4244;
assign _4246 = _3748 ? _3500 : _4245;
assign _4247 = _3752 ? _3500 : _4246;
assign _4248 = _3756 ? _3500 : _4247;
assign _4249 = _3772 ? _3500 : _4248;
assign _4250 = _3787 ? _3500 : _4249;
assign _4251 = _2605 == _2600;
assign _4252 = _4251 ? _4250 : _3500;
assign _3498 = _4252;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_3500 <= vdd;
else
_3500 <= _3498;
end
assign _3725 = _3701[23:23];
assign _4233 = vdd ? _3725 : _3503;
assign _4234 = _3736 ? _4233 : _3503;
assign _4235 = _3742 ? _3503 : _4234;
assign _4236 = _3748 ? _3503 : _4235;
assign _4237 = _3752 ? _3503 : _4236;
assign _4238 = _3756 ? _3503 : _4237;
assign _4239 = _3772 ? _3503 : _4238;
assign _4240 = _3787 ? _3503 : _4239;
assign _4241 = _2605 == _2600;
assign _4242 = _4241 ? _4240 : _3503;
assign _3501 = _4242;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_3503 <= vdd;
else
_3503 <= _3501;
end
assign _3726 = _3701[24:24];
assign _4223 = vdd ? _3726 : _3506;
assign _4224 = _3736 ? _4223 : _3506;
assign _4225 = _3742 ? _3506 : _4224;
assign _4226 = _3748 ? _3506 : _4225;
assign _4227 = _3752 ? _3506 : _4226;
assign _4228 = _3756 ? _3506 : _4227;
assign _4229 = _3772 ? _3506 : _4228;
assign _4230 = _3787 ? _3506 : _4229;
assign _4231 = _2605 == _2600;
assign _4232 = _4231 ? _4230 : _3506;
assign _3504 = _4232;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_3506 <= vdd;
else
_3506 <= _3504;
end
assign _3727 = _3701[25:25];
assign _4213 = vdd ? _3727 : _3509;
assign _4214 = _3736 ? _4213 : _3509;
assign _4215 = _3742 ? _3509 : _4214;
assign _4216 = _3748 ? _3509 : _4215;
assign _4217 = _3752 ? _3509 : _4216;
assign _4218 = _3756 ? _3509 : _4217;
assign _4219 = _3772 ? _3509 : _4218;
assign _4220 = _3787 ? _3509 : _4219;
assign _4221 = _2605 == _2600;
assign _4222 = _4221 ? _4220 : _3509;
assign _3507 = _4222;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_3509 <= vdd;
else
_3509 <= _3507;
end
assign _3728 = _3701[26:26];
assign _4203 = vdd ? _3728 : _3512;
assign _4204 = _3736 ? _4203 : _3512;
assign _4205 = _3742 ? _3512 : _4204;
assign _4206 = _3748 ? _3512 : _4205;
assign _4207 = _3752 ? _3512 : _4206;
assign _4208 = _3756 ? _3512 : _4207;
assign _4209 = _3772 ? _3512 : _4208;
assign _4210 = _3787 ? _3512 : _4209;
assign _4211 = _2605 == _2600;
assign _4212 = _4211 ? _4210 : _3512;
assign _3510 = _4212;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_3512 <= vdd;
else
_3512 <= _3510;
end
assign _3729 = _3701[27:27];
assign _4193 = vdd ? _3729 : _3515;
assign _4194 = _3736 ? _4193 : _3515;
assign _4195 = _3742 ? _3515 : _4194;
assign _4196 = _3748 ? _3515 : _4195;
assign _4197 = _3752 ? _3515 : _4196;
assign _4198 = _3756 ? _3515 : _4197;
assign _4199 = _3772 ? _3515 : _4198;
assign _4200 = _3787 ? _3515 : _4199;
assign _4201 = _2605 == _2600;
assign _4202 = _4201 ? _4200 : _3515;
assign _3513 = _4202;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_3515 <= vdd;
else
_3515 <= _3513;
end
assign _3730 = _3701[28:28];
assign _4183 = vdd ? _3730 : _3518;
assign _4184 = _3736 ? _4183 : _3518;
assign _4185 = _3742 ? _3518 : _4184;
assign _4186 = _3748 ? _3518 : _4185;
assign _4187 = _3752 ? _3518 : _4186;
assign _4188 = _3756 ? _3518 : _4187;
assign _4189 = _3772 ? _3518 : _4188;
assign _4190 = _3787 ? _3518 : _4189;
assign _4191 = _2605 == _2600;
assign _4192 = _4191 ? _4190 : _3518;
assign _3516 = _4192;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_3518 <= vdd;
else
_3518 <= _3516;
end
assign _3731 = _3701[29:29];
assign _4173 = vdd ? _3731 : _3521;
assign _4174 = _3736 ? _4173 : _3521;
assign _4175 = _3742 ? _3521 : _4174;
assign _4176 = _3748 ? _3521 : _4175;
assign _4177 = _3752 ? _3521 : _4176;
assign _4178 = _3756 ? _3521 : _4177;
assign _4179 = _3772 ? _3521 : _4178;
assign _4180 = _3787 ? _3521 : _4179;
assign _4181 = _2605 == _2600;
assign _4182 = _4181 ? _4180 : _3521;
assign _3519 = _4182;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_3521 <= vdd;
else
_3521 <= _3519;
end
assign _3732 = _3701[30:30];
assign _4163 = vdd ? _3732 : _3524;
assign _4164 = _3736 ? _4163 : _3524;
assign _4165 = _3742 ? _3524 : _4164;
assign _4166 = _3748 ? _3524 : _4165;
assign _4167 = _3752 ? _3524 : _4166;
assign _4168 = _3756 ? _3524 : _4167;
assign _4169 = _3772 ? _3524 : _4168;
assign _4170 = _3787 ? _3524 : _4169;
assign _4171 = _2605 == _2600;
assign _4172 = _4171 ? _4170 : _3524;
assign _3522 = _4172;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_3524 <= vdd;
else
_3524 <= _3522;
end
assign _3733 = _3701[31:31];
assign _4153 = vdd ? _3733 : _3527;
assign _4154 = _3736 ? _4153 : _3527;
assign _4155 = _3742 ? _3527 : _4154;
assign _4156 = _3748 ? _3527 : _4155;
assign _4157 = _3752 ? _3527 : _4156;
assign _4158 = _3756 ? _3527 : _4157;
assign _4159 = _3772 ? _3527 : _4158;
assign _4160 = _3787 ? _3527 : _4159;
assign _4161 = _2605 == _2600;
assign _4162 = _4161 ? _4160 : _3527;
assign _3525 = _4162;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_3527 <= vdd;
else
_3527 <= _3525;
end
assign _3528 = { _3527, _3524, _3521, _3518, _3515, _3512, _3509, _3506, _3503, _3500, _3497, _3494, _3491, _3488, _3485, _3482, _3479, _3476, _3473, _3470, _3467, _3464, _3461, _3458, _3455, _3452, _3449, _3446, _3443, _3440, _3437, _3434 };
assign _3658 = _3431 & _3528;
assign _4522 = _3664 ? _3658 : _3431;
assign _4523 = _3668 ? _3431 : _4522;
assign _4524 = _3354 ? _3431 : _4523;
assign _4525 = _3346 ? _3431 : _4524;
assign _3950 = _3535 - _3949;
assign _3952 = _3950 == _3951;
assign _4520 = _3952 ? _3948 : _4519;
assign _3967 = irq[0:0];
assign _3968 = _38[0:0];
assign _3969 = _3398[0:0];
assign _3970 = _3969 & _3968;
assign _3971 = _3970 | _3967;
assign _4519 = vdd ? _3971 : gnd;
assign _3698 = instr[46:46];
assign _3699 = vdd & vdd;
assign _3700 = _3699 & _3698;
assign _4131 = _3700 ? _3682 : _4130;
assign _4132 = _3736 ? _4130 : _4131;
assign _4133 = _3742 ? _4130 : _4132;
assign _4134 = _3748 ? _4130 : _4133;
assign _4135 = _3752 ? _4130 : _4134;
assign _4136 = _3756 ? _4130 : _4135;
assign _4137 = _3772 ? _4130 : _4136;
assign _4138 = _3787 ? _4130 : _4137;
assign _3947 = _3535 - _3946;
assign _4130 = _3957 ? _3947 : _3535;
assign _4139 = _2605 == _2600;
assign _4140 = _4139 ? _4138 : _4130;
assign _3533 = _4140;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_3535 <= _3532;
else
_3535 <= _3533;
end
assign _3954 = _3535 == _3953;
assign _3955 = ~ _3954;
assign _3956 = vdd & vdd;
assign _3957 = _3956 & _3955;
assign _4521 = _3957 ? _4520 : _4519;
assign _3399 = _4521;
assign _3779 = ~ _3394;
assign _3780 = ~ _3437;
assign _3781 = vdd & _3780;
assign _3782 = _3781 & _3779;
assign _4504 = _3782 ? _3778 : _4503;
assign _4505 = _3326 ? _4504 : _4503;
assign _4506 = pcpi_int_ready ? _4503 : _4505;
assign _4507 = vdd ? _4506 : _4503;
assign _3774 = ~ _3394;
assign _3775 = ~ _3437;
assign _3776 = vdd & _3775;
assign _3777 = _3776 & _3774;
assign _4508 = _3777 ? _3773 : _4503;
assign _4509 = vdd ? _4507 : _4508;
assign _4510 = _3787 ? _4509 : _4503;
assign _4528 = _3668 ? _3666 : _3394;
assign _4529 = _3354 ? _3394 : _4528;
assign _4530 = _3346 ? _3394 : _4529;
assign _4531 = _3742 ? _3739 : _3394;
assign _4532 = _3748 ? _3394 : _4531;
assign _4533 = _3752 ? _3394 : _4532;
assign _4534 = _3756 ? _3394 : _4533;
assign _4535 = _3772 ? _3394 : _4534;
assign _4536 = _3787 ? _3394 : _4535;
assign _4537 = _2605 == _2600;
assign _4538 = _4537 ? _4536 : _3394;
assign _4539 = _2605 == _2602;
assign _4540 = _4539 ? _4530 : _4538;
assign _3392 = _4540;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_3394 <= _3391;
else
_3394 <= _3392;
end
assign _3794 = ~ _3394;
assign _3238 = _3062[35:35];
assign _3239 = _2672 & _3238;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_3242 <= _3240;
else
if (_3239)
_3242 <= _2671;
end
assign _3233 = _3062[34:34];
assign _3234 = _2672 & _3233;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_3237 <= _3235;
else
if (_3234)
_3237 <= _2671;
end
assign _3228 = _3062[33:33];
assign _3229 = _2672 & _3228;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_3232 <= _3230;
else
if (_3229)
_3232 <= _2671;
end
assign _3223 = _3062[32:32];
assign _3224 = _2672 & _3223;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_3227 <= _3225;
else
if (_3224)
_3227 <= _2671;
end
assign _3218 = _3062[31:31];
assign _3219 = _2672 & _3218;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_3222 <= _3220;
else
if (_3219)
_3222 <= _2671;
end
assign _3213 = _3062[30:30];
assign _3214 = _2672 & _3213;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_3217 <= _3215;
else
if (_3214)
_3217 <= _2671;
end
assign _3208 = _3062[29:29];
assign _3209 = _2672 & _3208;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_3212 <= _3210;
else
if (_3209)
_3212 <= _2671;
end
assign _3203 = _3062[28:28];
assign _3204 = _2672 & _3203;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_3207 <= _3205;
else
if (_3204)
_3207 <= _2671;
end
assign _3198 = _3062[27:27];
assign _3199 = _2672 & _3198;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_3202 <= _3200;
else
if (_3199)
_3202 <= _2671;
end
assign _3193 = _3062[26:26];
assign _3194 = _2672 & _3193;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_3197 <= _3195;
else
if (_3194)
_3197 <= _2671;
end
assign _3188 = _3062[25:25];
assign _3189 = _2672 & _3188;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_3192 <= _3190;
else
if (_3189)
_3192 <= _2671;
end
assign _3183 = _3062[24:24];
assign _3184 = _2672 & _3183;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_3187 <= _3185;
else
if (_3184)
_3187 <= _2671;
end
assign _3178 = _3062[23:23];
assign _3179 = _2672 & _3178;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_3182 <= _3180;
else
if (_3179)
_3182 <= _2671;
end
assign _3173 = _3062[22:22];
assign _3174 = _2672 & _3173;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_3177 <= _3175;
else
if (_3174)
_3177 <= _2671;
end
assign _3168 = _3062[21:21];
assign _3169 = _2672 & _3168;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_3172 <= _3170;
else
if (_3169)
_3172 <= _2671;
end
assign _3163 = _3062[20:20];
assign _3164 = _2672 & _3163;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_3167 <= _3165;
else
if (_3164)
_3167 <= _2671;
end
assign _3158 = _3062[19:19];
assign _3159 = _2672 & _3158;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_3162 <= _3160;
else
if (_3159)
_3162 <= _2671;
end
assign _3153 = _3062[18:18];
assign _3154 = _2672 & _3153;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_3157 <= _3155;
else
if (_3154)
_3157 <= _2671;
end
assign _3148 = _3062[17:17];
assign _3149 = _2672 & _3148;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_3152 <= _3150;
else
if (_3149)
_3152 <= _2671;
end
assign _3143 = _3062[16:16];
assign _3144 = _2672 & _3143;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_3147 <= _3145;
else
if (_3144)
_3147 <= _2671;
end
assign _3138 = _3062[15:15];
assign _3139 = _2672 & _3138;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_3142 <= _3140;
else
if (_3139)
_3142 <= _2671;
end
assign _3133 = _3062[14:14];
assign _3134 = _2672 & _3133;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_3137 <= _3135;
else
if (_3134)
_3137 <= _2671;
end
assign _3128 = _3062[13:13];
assign _3129 = _2672 & _3128;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_3132 <= _3130;
else
if (_3129)
_3132 <= _2671;
end
assign _3123 = _3062[12:12];
assign _3124 = _2672 & _3123;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_3127 <= _3125;
else
if (_3124)
_3127 <= _2671;
end
assign _3118 = _3062[11:11];
assign _3119 = _2672 & _3118;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_3122 <= _3120;
else
if (_3119)
_3122 <= _2671;
end
assign _3113 = _3062[10:10];
assign _3114 = _2672 & _3113;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_3117 <= _3115;
else
if (_3114)
_3117 <= _2671;
end
assign _3108 = _3062[9:9];
assign _3109 = _2672 & _3108;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_3112 <= _3110;
else
if (_3109)
_3112 <= _2671;
end
assign _3103 = _3062[8:8];
assign _3104 = _2672 & _3103;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_3107 <= _3105;
else
if (_3104)
_3107 <= _2671;
end
assign _3098 = _3062[7:7];
assign _3099 = _2672 & _3098;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_3102 <= _3100;
else
if (_3099)
_3102 <= _2671;
end
assign _3093 = _3062[6:6];
assign _3094 = _2672 & _3093;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_3097 <= _3095;
else
if (_3094)
_3097 <= _2671;
end
assign _3088 = _3062[5:5];
assign _3089 = _2672 & _3088;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_3092 <= _3090;
else
if (_3089)
_3092 <= _2671;
end
assign _3083 = _3062[4:4];
assign _3084 = _2672 & _3083;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_3087 <= _3085;
else
if (_3084)
_3087 <= _2671;
end
assign _3078 = _3062[3:3];
assign _3079 = _2672 & _3078;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_3082 <= _3080;
else
if (_3079)
_3082 <= _2671;
end
assign _3073 = _3062[2:2];
assign _3074 = _2672 & _3073;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_3077 <= _3075;
else
if (_3074)
_3077 <= _2671;
end
assign _2679 = ~ _2673;
assign _2682 = _2680 & _2679;
assign _2690 = _2686 & _2682;
assign _2710 = _2702 & _2690;
assign _2758 = _2742 & _2710;
assign _2870 = _2838 & _2758;
assign _2680 = ~ _2674;
assign _2681 = _2680 & _2673;
assign _2689 = _2686 & _2681;
assign _2709 = _2702 & _2689;
assign _2757 = _2742 & _2709;
assign _2869 = _2838 & _2757;
assign _2683 = ~ _2673;
assign _2685 = _2674 & _2683;
assign _2688 = _2686 & _2685;
assign _2708 = _2702 & _2688;
assign _2756 = _2742 & _2708;
assign _2868 = _2838 & _2756;
assign _2684 = _2674 & _2673;
assign _2686 = ~ _2675;
assign _2687 = _2686 & _2684;
assign _2707 = _2702 & _2687;
assign _2755 = _2742 & _2707;
assign _2867 = _2838 & _2755;
assign _2691 = ~ _2673;
assign _2694 = _2692 & _2691;
assign _2701 = _2675 & _2694;
assign _2706 = _2702 & _2701;
assign _2754 = _2742 & _2706;
assign _2866 = _2838 & _2754;
assign _2692 = ~ _2674;
assign _2693 = _2692 & _2673;
assign _2700 = _2675 & _2693;
assign _2705 = _2702 & _2700;
assign _2753 = _2742 & _2705;
assign _2865 = _2838 & _2753;
assign _2695 = ~ _2673;
assign _2697 = _2674 & _2695;
assign _2699 = _2675 & _2697;
assign _2704 = _2702 & _2699;
assign _2752 = _2742 & _2704;
assign _2864 = _2838 & _2752;
assign _2696 = _2674 & _2673;
assign _2698 = _2675 & _2696;
assign _2702 = ~ _2676;
assign _2703 = _2702 & _2698;
assign _2751 = _2742 & _2703;
assign _2863 = _2838 & _2751;
assign _2711 = ~ _2673;
assign _2714 = _2712 & _2711;
assign _2722 = _2718 & _2714;
assign _2741 = _2676 & _2722;
assign _2750 = _2742 & _2741;
assign _2862 = _2838 & _2750;
assign _2712 = ~ _2674;
assign _2713 = _2712 & _2673;
assign _2721 = _2718 & _2713;
assign _2740 = _2676 & _2721;
assign _2749 = _2742 & _2740;
assign _2861 = _2838 & _2749;
assign _2715 = ~ _2673;
assign _2717 = _2674 & _2715;
assign _2720 = _2718 & _2717;
assign _2739 = _2676 & _2720;
assign _2748 = _2742 & _2739;
assign _2860 = _2838 & _2748;
assign _2716 = _2674 & _2673;
assign _2718 = ~ _2675;
assign _2719 = _2718 & _2716;
assign _2738 = _2676 & _2719;
assign _2747 = _2742 & _2738;
assign _2859 = _2838 & _2747;
assign _2723 = ~ _2673;
assign _2726 = _2724 & _2723;
assign _2733 = _2675 & _2726;
assign _2737 = _2676 & _2733;
assign _2746 = _2742 & _2737;
assign _2858 = _2838 & _2746;
assign _2724 = ~ _2674;
assign _2725 = _2724 & _2673;
assign _2732 = _2675 & _2725;
assign _2736 = _2676 & _2732;
assign _2745 = _2742 & _2736;
assign _2857 = _2838 & _2745;
assign _2727 = ~ _2673;
assign _2729 = _2674 & _2727;
assign _2731 = _2675 & _2729;
assign _2735 = _2676 & _2731;
assign _2744 = _2742 & _2735;
assign _2856 = _2838 & _2744;
assign _2728 = _2674 & _2673;
assign _2730 = _2675 & _2728;
assign _2734 = _2676 & _2730;
assign _2742 = ~ _2677;
assign _2743 = _2742 & _2734;
assign _2855 = _2838 & _2743;
assign _2759 = ~ _2673;
assign _2762 = _2760 & _2759;
assign _2770 = _2766 & _2762;
assign _2790 = _2782 & _2770;
assign _2837 = _2677 & _2790;
assign _2854 = _2838 & _2837;
assign _2760 = ~ _2674;
assign _2761 = _2760 & _2673;
assign _2769 = _2766 & _2761;
assign _2789 = _2782 & _2769;
assign _2836 = _2677 & _2789;
assign _2853 = _2838 & _2836;
assign _2763 = ~ _2673;
assign _2765 = _2674 & _2763;
assign _2768 = _2766 & _2765;
assign _2788 = _2782 & _2768;
assign _2835 = _2677 & _2788;
assign _2852 = _2838 & _2835;
assign _2764 = _2674 & _2673;
assign _2766 = ~ _2675;
assign _2767 = _2766 & _2764;
assign _2787 = _2782 & _2767;
assign _2834 = _2677 & _2787;
assign _2851 = _2838 & _2834;
assign _2771 = ~ _2673;
assign _2774 = _2772 & _2771;
assign _2781 = _2675 & _2774;
assign _2786 = _2782 & _2781;
assign _2833 = _2677 & _2786;
assign _2850 = _2838 & _2833;
assign _2772 = ~ _2674;
assign _2773 = _2772 & _2673;
assign _2780 = _2675 & _2773;
assign _2785 = _2782 & _2780;
assign _2832 = _2677 & _2785;
assign _2849 = _2838 & _2832;
assign _2775 = ~ _2673;
assign _2777 = _2674 & _2775;
assign _2779 = _2675 & _2777;
assign _2784 = _2782 & _2779;
assign _2831 = _2677 & _2784;
assign _2848 = _2838 & _2831;
assign _2776 = _2674 & _2673;
assign _2778 = _2675 & _2776;
assign _2782 = ~ _2676;
assign _2783 = _2782 & _2778;
assign _2830 = _2677 & _2783;
assign _2847 = _2838 & _2830;
assign _2791 = ~ _2673;
assign _2794 = _2792 & _2791;
assign _2802 = _2798 & _2794;
assign _2821 = _2676 & _2802;
assign _2829 = _2677 & _2821;
assign _2846 = _2838 & _2829;
assign _2792 = ~ _2674;
assign _2793 = _2792 & _2673;
assign _2801 = _2798 & _2793;
assign _2820 = _2676 & _2801;
assign _2828 = _2677 & _2820;
assign _2845 = _2838 & _2828;
assign _2795 = ~ _2673;
assign _2797 = _2674 & _2795;
assign _2800 = _2798 & _2797;
assign _2819 = _2676 & _2800;
assign _2827 = _2677 & _2819;
assign _2844 = _2838 & _2827;
assign _2796 = _2674 & _2673;
assign _2798 = ~ _2675;
assign _2799 = _2798 & _2796;
assign _2818 = _2676 & _2799;
assign _2826 = _2677 & _2818;
assign _2843 = _2838 & _2826;
assign _2803 = ~ _2673;
assign _2806 = _2804 & _2803;
assign _2813 = _2675 & _2806;
assign _2817 = _2676 & _2813;
assign _2825 = _2677 & _2817;
assign _2842 = _2838 & _2825;
assign _2804 = ~ _2674;
assign _2805 = _2804 & _2673;
assign _2812 = _2675 & _2805;
assign _2816 = _2676 & _2812;
assign _2824 = _2677 & _2816;
assign _2841 = _2838 & _2824;
assign _2807 = ~ _2673;
assign _2809 = _2674 & _2807;
assign _2811 = _2675 & _2809;
assign _2815 = _2676 & _2811;
assign _2823 = _2677 & _2815;
assign _2840 = _2838 & _2823;
assign _2808 = _2674 & _2673;
assign _2810 = _2675 & _2808;
assign _2814 = _2676 & _2810;
assign _2822 = _2677 & _2814;
assign _2838 = ~ _2678;
assign _2839 = _2838 & _2822;
assign _2871 = ~ _2673;
assign _2874 = _2872 & _2871;
assign _2882 = _2878 & _2874;
assign _2902 = _2894 & _2882;
assign _2950 = _2934 & _2902;
assign _3061 = _2678 & _2950;
assign _2872 = ~ _2674;
assign _2873 = _2872 & _2673;
assign _2881 = _2878 & _2873;
assign _2901 = _2894 & _2881;
assign _2949 = _2934 & _2901;
assign _3060 = _2678 & _2949;
assign _2875 = ~ _2673;
assign _2877 = _2674 & _2875;
assign _2880 = _2878 & _2877;
assign _2900 = _2894 & _2880;
assign _2948 = _2934 & _2900;
assign _3059 = _2678 & _2948;
assign _2876 = _2674 & _2673;
assign _2878 = ~ _2675;
assign _2879 = _2878 & _2876;
assign _2899 = _2894 & _2879;
assign _2947 = _2934 & _2899;
assign _3058 = _2678 & _2947;
assign _2883 = ~ _2673;
assign _2886 = _2884 & _2883;
assign _2893 = _2675 & _2886;
assign _2898 = _2894 & _2893;
assign _2946 = _2934 & _2898;
assign _3057 = _2678 & _2946;
assign _2884 = ~ _2674;
assign _2885 = _2884 & _2673;
assign _2892 = _2675 & _2885;
assign _2897 = _2894 & _2892;
assign _2945 = _2934 & _2897;
assign _3056 = _2678 & _2945;
assign _2887 = ~ _2673;
assign _2889 = _2674 & _2887;
assign _2891 = _2675 & _2889;
assign _2896 = _2894 & _2891;
assign _2944 = _2934 & _2896;
assign _3055 = _2678 & _2944;
assign _2888 = _2674 & _2673;
assign _2890 = _2675 & _2888;
assign _2894 = ~ _2676;
assign _2895 = _2894 & _2890;
assign _2943 = _2934 & _2895;
assign _3054 = _2678 & _2943;
assign _2903 = ~ _2673;
assign _2906 = _2904 & _2903;
assign _2914 = _2910 & _2906;
assign _2933 = _2676 & _2914;
assign _2942 = _2934 & _2933;
assign _3053 = _2678 & _2942;
assign _2904 = ~ _2674;
assign _2905 = _2904 & _2673;
assign _2913 = _2910 & _2905;
assign _2932 = _2676 & _2913;
assign _2941 = _2934 & _2932;
assign _3052 = _2678 & _2941;
assign _2907 = ~ _2673;
assign _2909 = _2674 & _2907;
assign _2912 = _2910 & _2909;
assign _2931 = _2676 & _2912;
assign _2940 = _2934 & _2931;
assign _3051 = _2678 & _2940;
assign _2908 = _2674 & _2673;
assign _2910 = ~ _2675;
assign _2911 = _2910 & _2908;
assign _2930 = _2676 & _2911;
assign _2939 = _2934 & _2930;
assign _3050 = _2678 & _2939;
assign _2915 = ~ _2673;
assign _2918 = _2916 & _2915;
assign _2925 = _2675 & _2918;
assign _2929 = _2676 & _2925;
assign _2938 = _2934 & _2929;
assign _3049 = _2678 & _2938;
assign _2916 = ~ _2674;
assign _2917 = _2916 & _2673;
assign _2924 = _2675 & _2917;
assign _2928 = _2676 & _2924;
assign _2937 = _2934 & _2928;
assign _3048 = _2678 & _2937;
assign _2919 = ~ _2673;
assign _2921 = _2674 & _2919;
assign _2923 = _2675 & _2921;
assign _2927 = _2676 & _2923;
assign _2936 = _2934 & _2927;
assign _3047 = _2678 & _2936;
assign _2920 = _2674 & _2673;
assign _2922 = _2675 & _2920;
assign _2926 = _2676 & _2922;
assign _2934 = ~ _2677;
assign _2935 = _2934 & _2926;
assign _3046 = _2678 & _2935;
assign _2951 = ~ _2673;
assign _2954 = _2952 & _2951;
assign _2962 = _2958 & _2954;
assign _2982 = _2974 & _2962;
assign _3029 = _2677 & _2982;
assign _3045 = _2678 & _3029;
assign _2952 = ~ _2674;
assign _2953 = _2952 & _2673;
assign _2961 = _2958 & _2953;
assign _2981 = _2974 & _2961;
assign _3028 = _2677 & _2981;
assign _3044 = _2678 & _3028;
assign _2955 = ~ _2673;
assign _2957 = _2674 & _2955;
assign _2960 = _2958 & _2957;
assign _2980 = _2974 & _2960;
assign _3027 = _2677 & _2980;
assign _3043 = _2678 & _3027;
assign _2956 = _2674 & _2673;
assign _2958 = ~ _2675;
assign _2959 = _2958 & _2956;
assign _2979 = _2974 & _2959;
assign _3026 = _2677 & _2979;
assign _3042 = _2678 & _3026;
assign _2963 = ~ _2673;
assign _2966 = _2964 & _2963;
assign _2973 = _2675 & _2966;
assign _2978 = _2974 & _2973;
assign _3025 = _2677 & _2978;
assign _3041 = _2678 & _3025;
assign _2964 = ~ _2674;
assign _2965 = _2964 & _2673;
assign _2972 = _2675 & _2965;
assign _2977 = _2974 & _2972;
assign _3024 = _2677 & _2977;
assign _3040 = _2678 & _3024;
assign _2967 = ~ _2673;
assign _2969 = _2674 & _2967;
assign _2971 = _2675 & _2969;
assign _2976 = _2974 & _2971;
assign _3023 = _2677 & _2976;
assign _3039 = _2678 & _3023;
assign _2968 = _2674 & _2673;
assign _2970 = _2675 & _2968;
assign _2974 = ~ _2676;
assign _2975 = _2974 & _2970;
assign _3022 = _2677 & _2975;
assign _3038 = _2678 & _3022;
assign _2983 = ~ _2673;
assign _2986 = _2984 & _2983;
assign _2994 = _2990 & _2986;
assign _3013 = _2676 & _2994;
assign _3021 = _2677 & _3013;
assign _3037 = _2678 & _3021;
assign _2984 = ~ _2674;
assign _2985 = _2984 & _2673;
assign _2993 = _2990 & _2985;
assign _3012 = _2676 & _2993;
assign _3020 = _2677 & _3012;
assign _3036 = _2678 & _3020;
assign _2987 = ~ _2673;
assign _2989 = _2674 & _2987;
assign _2992 = _2990 & _2989;
assign _3011 = _2676 & _2992;
assign _3019 = _2677 & _3011;
assign _3035 = _2678 & _3019;
assign _2988 = _2674 & _2673;
assign _2990 = ~ _2675;
assign _2991 = _2990 & _2988;
assign _3010 = _2676 & _2991;
assign _3018 = _2677 & _3010;
assign _3034 = _2678 & _3018;
assign _2995 = ~ _2673;
assign _2998 = _2996 & _2995;
assign _3005 = _2675 & _2998;
assign _3009 = _2676 & _3005;
assign _3017 = _2677 & _3009;
assign _3033 = _2678 & _3017;
assign _2996 = ~ _2674;
assign _2997 = _2996 & _2673;
assign _3004 = _2675 & _2997;
assign _3008 = _2676 & _3004;
assign _3016 = _2677 & _3008;
assign _3032 = _2678 & _3016;
assign _2999 = ~ _2673;
assign _3001 = _2674 & _2999;
assign _3003 = _2675 & _3001;
assign _3007 = _2676 & _3003;
assign _3015 = _2677 & _3007;
assign _3031 = _2678 & _3015;
assign _2673 = _2669[0:0];
assign _2674 = _2669[1:1];
assign _3000 = _2674 & _2673;
assign _2675 = _2669[2:2];
assign _3002 = _2675 & _3000;
assign _2676 = _2669[3:3];
assign _3006 = _2676 & _3002;
assign _2677 = _2669[4:4];
assign _3014 = _2677 & _3006;
assign _3562 = _3390[0:0];
assign _3567 = { _3565, _3562 };
assign _3569 = _3568 | _3567;
assign _3561 = _3390[0:0];
assign _4975 = _3561 ? _3560 : _3559;
assign _4976 = vdd ? _3569 : _4975;
assign _4977 = _3651 ? _4976 : decoded_rd;
assign _3745 = _2669 | _3744;
assign _4978 = _3748 ? _3745 : _2669;
assign _4979 = _3752 ? _2669 : _4978;
assign _4980 = _3756 ? _2669 : _4979;
assign _4981 = _3772 ? _2669 : _4980;
assign _4982 = _3787 ? _2669 : _4981;
assign _4983 = _3810 ? _3809 : _2669;
assign _4984 = _2605 == _2598;
assign _4985 = _4984 ? _4983 : _2669;
assign _4986 = _2605 == _2600;
assign _4987 = _4986 ? _4982 : _4985;
assign _4988 = _2605 == _2602;
assign _4989 = _4988 ? _4977 : _4987;
assign _2667 = _4989;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_2669 <= _2666;
else
_2669 <= _2667;
end
assign _2678 = _2669[5:5];
assign _3030 = _2678 & _3014;
assign _3062 = { _3030, _3031, _3032, _3033, _3034, _3035, _3036, _3037, _3038, _3039, _3040, _3041, _3042, _3043, _3044, _3045, _3046, _3047, _3048, _3049, _3050, _3051, _3052, _3053, _3054, _3055, _3056, _3057, _3058, _3059, _3060, _3061, _2839, _2840, _2841, _2842, _2843, _2844, _2845, _2846, _2847, _2848, _2849, _2850, _2851, _2852, _2853, _2854, _2855, _2856, _2857, _2858, _2859, _2860, _2861, _2862, _2863, _2864, _2865, _2866, _2867, _2868, _2869, _2870 };
assign _3068 = _3062[1:1];
assign _4955 = vdd ? vdd : gnd;
assign _4956 = vdd ? vdd : gnd;
assign _4957 = vdd ? vdd : gnd;
assign _4958 = vdd ? vdd : gnd;
assign _3663 = _3390[1:1];
assign _3664 = vdd & _3663;
assign _4959 = _3664 ? _4958 : gnd;
assign _3573 = _3390 == _3572;
assign _3574 = _3573 ? _3571 : _3570;
assign _3577 = _3390 == _3576;
assign _3578 = _3577 ? _3575 : _3574;
assign _4541 = _3651 ? _3578 : _3390;
assign _4542 = _2605 == _2602;
assign _4543 = _4542 ? _4541 : _3390;
assign _3388 = _4543;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_3390 <= _3387;
else
_3390 <= _3388;
end
assign _3667 = _3390[0:0];
assign _3668 = vdd & _3667;
assign _4960 = _3668 ? _4957 : _4959;
assign _4961 = _3354 ? _4956 : _4960;
assign _4962 = _3346 ? _4955 : _4961;
assign _4963 = _2605 == _2602;
assign _4964 = _4963 ? _4962 : gnd;
assign _2672 = _4964;
assign _3069 = _2672 & _3068;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_3072 <= _3070;
else
if (_3069)
_3072 <= _2671;
end
always @* begin
case (decoded_rs1)
0: _3244 <= _3067;
1: _3244 <= _3072;
2: _3244 <= _3077;
3: _3244 <= _3082;
4: _3244 <= _3087;
5: _3244 <= _3092;
6: _3244 <= _3097;
7: _3244 <= _3102;
8: _3244 <= _3107;
9: _3244 <= _3112;
10: _3244 <= _3117;
11: _3244 <= _3122;
12: _3244 <= _3127;
13: _3244 <= _3132;
14: _3244 <= _3137;
15: _3244 <= _3142;
16: _3244 <= _3147;
17: _3244 <= _3152;
18: _3244 <= _3157;
19: _3244 <= _3162;
20: _3244 <= _3167;
21: _3244 <= _3172;
22: _3244 <= _3177;
23: _3244 <= _3182;
24: _3244 <= _3187;
25: _3244 <= _3192;
26: _3244 <= _3197;
27: _3244 <= _3202;
28: _3244 <= _3207;
29: _3244 <= _3212;
30: _3244 <= _3217;
31: _3244 <= _3222;
32: _3244 <= _3227;
33: _3244 <= _3232;
34: _3244 <= _3237;
default: _3244 <= _3242;
endcase
end
assign _3680 = decoded_rs1 == _3679;
assign _3681 = ~ _3680;
assign _3682 = _3681 ? _3244 : _3678;
assign _3701 = _3682 | _37;
assign _3703 = _3701[1:1];
assign _4453 = vdd ? _3703 : _3437;
assign _3735 = instr[44:44];
assign _3736 = vdd & _3735;
assign _4454 = _3736 ? _4453 : _3437;
assign _4455 = _3742 ? _3437 : _4454;
assign _4456 = _3748 ? _3437 : _4455;
assign _4457 = _3752 ? _3437 : _4456;
assign _4458 = _3756 ? _3437 : _4457;
assign _4459 = _3772 ? _3437 : _4458;
assign _4460 = _3787 ? _3437 : _4459;
assign _4461 = _2605 == _2600;
assign _4462 = _4461 ? _4460 : _3437;
assign _3435 = _4462;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_3437 <= vdd;
else
_3437 <= _3435;
end
assign _3795 = ~ _3437;
assign _3796 = vdd & _3795;
assign _3797 = _3796 & _3794;
assign _4511 = _3797 ? _3793 : _4503;
assign _3964 = _3330 - _3963;
assign _4944 = _3330[0:0];
assign _4945 = _3330[1:1];
assign _4946 = _3330[2:2];
assign _4947 = _3330[3:3];
assign _4948 = _4947 | _4946;
assign _4949 = _4948 | _4945;
assign _4950 = _4949 | _4944;
assign _4951 = _4950 ? _3964 : _3330;
assign _3965 = ~ pcpi_int_wait;
assign _5157 = pcpi_int_ready ? _3783 : _3786;
assign _5158 = vdd ? _5157 : _2629;
assign _5159 = vdd ? _5158 : _2629;
assign _5160 = _3787 ? _5159 : _2629;
assign _5161 = pcpi_int_ready ? _3798 : _3800;
assign _5162 = _3802 ? _5161 : _2629;
assign _5163 = _2605 == _2599;
assign _5164 = _5163 ? _5162 : _2629;
assign _5165 = _2605 == _2600;
assign _5166 = _5165 ? _5160 : _5164;
assign _2627 = _5166;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_2629 <= _2626;
else
_2629 <= _2627;
end
assign _3966 = _2629 & _3965;
assign _4952 = _3966 ? _4951 : _3962;
assign _4953 = vdd ? _4952 : _3330;
assign _3328 = _4953;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_3330 <= _3327;
else
_3330 <= _3328;
end
assign _3961 = _3330 == _3960;
assign _4954 = vdd ? _3961 : _3326;
assign _3324 = _4954;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_3326 <= _3323;
else
_3326 <= _3324;
end
assign _4512 = _3326 ? _4511 : _4503;
assign _4513 = pcpi_int_ready ? _4503 : _4512;
assign _3801 = instr[47:47];
assign _3802 = vdd & _3801;
assign _4514 = _3802 ? _4513 : _4503;
assign _3972 = irq[1:1];
assign _3973 = _38[1:1];
assign _3974 = _3398[1:1];
assign _3975 = _3974 & _3973;
assign _3976 = _3975 | _3972;
assign _4503 = vdd ? _3976 : gnd;
assign _4515 = _2605 == _2599;
assign _4516 = _4515 ? _4514 : _4503;
assign _4517 = _2605 == _2600;
assign _4518 = _4517 ? _4510 : _4516;
assign _3400 = _4518;
assign _3977 = irq[2:2];
assign _3978 = _38[2:2];
assign _3979 = _3398[2:2];
assign _3980 = _3979 & _3978;
assign _3981 = _3980 | _3977;
assign _4502 = vdd ? _3981 : gnd;
assign _3401 = _4502;
assign _3982 = irq[3:3];
assign _3983 = _38[3:3];
assign _3984 = _3398[3:3];
assign _3985 = _3984 & _3983;
assign _3986 = _3985 | _3982;
assign _4501 = vdd ? _3986 : gnd;
assign _3402 = _4501;
assign _3987 = irq[4:4];
assign _3988 = _38[4:4];
assign _3989 = _3398[4:4];
assign _3990 = _3989 & _3988;
assign _3991 = _3990 | _3987;
assign _4500 = vdd ? _3991 : gnd;
assign _3403 = _4500;
assign _3992 = irq[5:5];
assign _3993 = _38[5:5];
assign _3994 = _3398[5:5];
assign _3995 = _3994 & _3993;
assign _3996 = _3995 | _3992;
assign _4499 = vdd ? _3996 : gnd;
assign _3404 = _4499;
assign _3997 = irq[6:6];
assign _3998 = _38[6:6];
assign _3999 = _3398[6:6];
assign _4000 = _3999 & _3998;
assign _4001 = _4000 | _3997;
assign _4498 = vdd ? _4001 : gnd;
assign _3405 = _4498;
assign _4002 = irq[7:7];
assign _4003 = _38[7:7];
assign _4004 = _3398[7:7];
assign _4005 = _4004 & _4003;
assign _4006 = _4005 | _4002;
assign _4497 = vdd ? _4006 : gnd;
assign _3406 = _4497;
assign _4007 = irq[8:8];
assign _4008 = _38[8:8];
assign _4009 = _3398[8:8];
assign _4010 = _4009 & _4008;
assign _4011 = _4010 | _4007;
assign _4496 = vdd ? _4011 : gnd;
assign _3407 = _4496;
assign _4012 = irq[9:9];
assign _4013 = _38[9:9];
assign _4014 = _3398[9:9];
assign _4015 = _4014 & _4013;
assign _4016 = _4015 | _4012;
assign _4495 = vdd ? _4016 : gnd;
assign _3408 = _4495;
assign _4017 = irq[10:10];
assign _4018 = _38[10:10];
assign _4019 = _3398[10:10];
assign _4020 = _4019 & _4018;
assign _4021 = _4020 | _4017;
assign _4494 = vdd ? _4021 : gnd;
assign _3409 = _4494;
assign _4022 = irq[11:11];
assign _4023 = _38[11:11];
assign _4024 = _3398[11:11];
assign _4025 = _4024 & _4023;
assign _4026 = _4025 | _4022;
assign _4493 = vdd ? _4026 : gnd;
assign _3410 = _4493;
assign _4027 = irq[12:12];
assign _4028 = _38[12:12];
assign _4029 = _3398[12:12];
assign _4030 = _4029 & _4028;
assign _4031 = _4030 | _4027;
assign _4492 = vdd ? _4031 : gnd;
assign _3411 = _4492;
assign _4032 = irq[13:13];
assign _4033 = _38[13:13];
assign _4034 = _3398[13:13];
assign _4035 = _4034 & _4033;
assign _4036 = _4035 | _4032;
assign _4491 = vdd ? _4036 : gnd;
assign _3412 = _4491;
assign _4037 = irq[14:14];
assign _4038 = _38[14:14];
assign _4039 = _3398[14:14];
assign _4040 = _4039 & _4038;
assign _4041 = _4040 | _4037;
assign _4490 = vdd ? _4041 : gnd;
assign _3413 = _4490;
assign _4042 = irq[15:15];
assign _4043 = _38[15:15];
assign _4044 = _3398[15:15];
assign _4045 = _4044 & _4043;
assign _4046 = _4045 | _4042;
assign _4489 = vdd ? _4046 : gnd;
assign _3414 = _4489;
assign _4047 = irq[16:16];
assign _4048 = _38[16:16];
assign _4049 = _3398[16:16];
assign _4050 = _4049 & _4048;
assign _4051 = _4050 | _4047;
assign _4488 = vdd ? _4051 : gnd;
assign _3415 = _4488;
assign _4052 = irq[17:17];
assign _4053 = _38[17:17];
assign _4054 = _3398[17:17];
assign _4055 = _4054 & _4053;
assign _4056 = _4055 | _4052;
assign _4487 = vdd ? _4056 : gnd;
assign _3416 = _4487;
assign _4057 = irq[18:18];
assign _4058 = _38[18:18];
assign _4059 = _3398[18:18];
assign _4060 = _4059 & _4058;
assign _4061 = _4060 | _4057;
assign _4486 = vdd ? _4061 : gnd;
assign _3417 = _4486;
assign _4062 = irq[19:19];
assign _4063 = _38[19:19];
assign _4064 = _3398[19:19];
assign _4065 = _4064 & _4063;
assign _4066 = _4065 | _4062;
assign _4485 = vdd ? _4066 : gnd;
assign _3418 = _4485;
assign _4067 = irq[20:20];
assign _4068 = _38[20:20];
assign _4069 = _3398[20:20];
assign _4070 = _4069 & _4068;
assign _4071 = _4070 | _4067;
assign _4484 = vdd ? _4071 : gnd;
assign _3419 = _4484;
assign _4072 = irq[21:21];
assign _4073 = _38[21:21];
assign _4074 = _3398[21:21];
assign _4075 = _4074 & _4073;
assign _4076 = _4075 | _4072;
assign _4483 = vdd ? _4076 : gnd;
assign _3420 = _4483;
assign _4077 = irq[22:22];
assign _4078 = _38[22:22];
assign _4079 = _3398[22:22];
assign _4080 = _4079 & _4078;
assign _4081 = _4080 | _4077;
assign _4482 = vdd ? _4081 : gnd;
assign _3421 = _4482;
assign _4082 = irq[23:23];
assign _4083 = _38[23:23];
assign _4084 = _3398[23:23];
assign _4085 = _4084 & _4083;
assign _4086 = _4085 | _4082;
assign _4481 = vdd ? _4086 : gnd;
assign _3422 = _4481;
assign _4087 = irq[24:24];
assign _4088 = _38[24:24];
assign _4089 = _3398[24:24];
assign _4090 = _4089 & _4088;
assign _4091 = _4090 | _4087;
assign _4480 = vdd ? _4091 : gnd;
assign _3423 = _4480;
assign _4092 = irq[25:25];
assign _4093 = _38[25:25];
assign _4094 = _3398[25:25];
assign _4095 = _4094 & _4093;
assign _4096 = _4095 | _4092;
assign _4479 = vdd ? _4096 : gnd;
assign _3424 = _4479;
assign _4097 = irq[26:26];
assign _4098 = _38[26:26];
assign _4099 = _3398[26:26];
assign _4100 = _4099 & _4098;
assign _4101 = _4100 | _4097;
assign _4478 = vdd ? _4101 : gnd;
assign _3425 = _4478;
assign _4102 = irq[27:27];
assign _4103 = _38[27:27];
assign _4104 = _3398[27:27];
assign _4105 = _4104 & _4103;
assign _4106 = _4105 | _4102;
assign _4477 = vdd ? _4106 : gnd;
assign _3426 = _4477;
assign _4107 = irq[28:28];
assign _4108 = _38[28:28];
assign _4109 = _3398[28:28];
assign _4110 = _4109 & _4108;
assign _4111 = _4110 | _4107;
assign _4476 = vdd ? _4111 : gnd;
assign _3427 = _4476;
assign _4112 = irq[29:29];
assign _4113 = _38[29:29];
assign _4114 = _3398[29:29];
assign _4115 = _4114 & _4113;
assign _4116 = _4115 | _4112;
assign _4475 = vdd ? _4116 : gnd;
assign _3428 = _4475;
assign _4117 = irq[30:30];
assign _4118 = _38[30:30];
assign _4119 = _3398[30:30];
assign _4120 = _4119 & _4118;
assign _4121 = _4120 | _4117;
assign _4474 = vdd ? _4121 : gnd;
assign _3429 = _4474;
assign _4122 = irq[31:31];
assign _4123 = _38[31:31];
assign _4124 = _3398[31:31];
assign _4125 = _4124 & _4123;
assign _4126 = _4125 | _4122;
assign _4473 = vdd ? _4126 : gnd;
assign _3430 = _4473;
assign _3431 = { _3430, _3429, _3428, _3427, _3426, _3425, _3424, _3423, _3422, _3421, _3420, _3419, _3418, _3417, _3416, _3415, _3414, _3413, _3412, _3411, _3410, _3409, _3408, _3407, _3406, _3405, _3404, _3403, _3402, _3401, _3400, _3399 };
assign _4526 = _2605 == _2602;
assign _4527 = _4526 ? _4525 : _3431;
assign _3396 = _4527;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_3398 <= _3395;
else
_3398 <= _3396;
end
assign _4907 = _3398[31:31];
assign _4908 = _4907 | _4906;
assign _4909 = _4908 | _4905;
assign _4910 = _4909 | _4904;
assign _4911 = _4910 | _4903;
assign _4912 = _4911 | _4902;
assign _4913 = _4912 | _4901;
assign _4914 = _4913 | _4900;
assign _4915 = _4914 | _4899;
assign _4916 = _4915 | _4898;
assign _4917 = _4916 | _4897;
assign _4918 = _4917 | _4896;
assign _4919 = _4918 | _4895;
assign _4920 = _4919 | _4894;
assign _4921 = _4920 | _4893;
assign _4922 = _4921 | _4892;
assign _4923 = _4922 | _4891;
assign _4924 = _4923 | _4890;
assign _4925 = _4924 | _4889;
assign _4926 = _4925 | _4888;
assign _4927 = _4926 | _4887;
assign _4928 = _4927 | _4886;
assign _4929 = _4928 | _4885;
assign _4930 = _4929 | _4884;
assign _4931 = _4930 | _4883;
assign _4932 = _4931 | _4882;
assign _4933 = _4932 | _4881;
assign _4934 = _4933 | _4880;
assign _4935 = _4934 | _4879;
assign _4936 = _4935 | _4878;
assign _4937 = _4936 | _4877;
assign _4938 = _4937 | _4876;
assign _4939 = _4938 ? _3943 : _3550;
assign _4940 = _3558 ? _4939 : _3943;
assign _4941 = _3651 ? _3943 : _4940;
assign _4942 = _2605 == _2602;
assign _4943 = _4942 ? _4941 : _3943;
assign _3332 = _4943;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_3334 <= _3331;
else
_3334 <= _3332;
end
assign _3556 = _2625 | _3334;
assign _3557 = vdd & _3556;
assign _3558 = _3557 & _3555;
assign _4854 = _3558 ? _3655 : _4853;
assign _4855 = _3651 ? _3655 : _4854;
assign _3741 = instr[43:43];
assign _3742 = vdd & _3741;
assign _4856 = _3742 ? _3738 : _3346;
assign _3746 = instr[42:42];
assign _3747 = vdd & vdd;
assign _3748 = _3747 & _3746;
assign _4857 = _3748 ? _3346 : _4856;
assign _3750 = instr[41:41];
assign _3751 = vdd & vdd;
assign _3752 = _3751 & _3750;
assign _4858 = _3752 ? _3346 : _4857;
assign _3756 = is[0:0];
assign _4859 = _3756 ? _3346 : _4858;
assign _3772 = is[14:14];
assign _4860 = _3772 ? _3346 : _4859;
assign _3787 = instr[47:47];
assign _4861 = _3787 ? _3346 : _4860;
assign _3806 = instr[3:3];
assign _4862 = _3810 ? _3284 : _3806;
assign _4863 = _2605 == _2598;
assign _4864 = _4863 ? _4862 : _3346;
assign _4865 = _2605 == _2600;
assign _4866 = _4865 ? _4861 : _4864;
assign _4867 = _2605 == _2602;
assign _4868 = _4867 ? _4855 : _4866;
assign _3344 = _4868;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_3346 <= _3343;
else
_3346 <= _3344;
end
assign _4972 = _3346 ? _4965 : _4971;
assign _4973 = _2605 == _2602;
assign _4974 = _4973 ? _4972 : _2670;
assign _2671 = _4974;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_3067 <= _3065;
else
if (_3064)
_3067 <= _2671;
end
always @* begin
case (decoded_rs2)
0: _3243 <= _3067;
1: _3243 <= _3072;
2: _3243 <= _3077;
3: _3243 <= _3082;
4: _3243 <= _3087;
5: _3243 <= _3092;
6: _3243 <= _3097;
7: _3243 <= _3102;
8: _3243 <= _3107;
9: _3243 <= _3112;
10: _3243 <= _3117;
11: _3243 <= _3122;
12: _3243 <= _3127;
13: _3243 <= _3132;
14: _3243 <= _3137;
15: _3243 <= _3142;
16: _3243 <= _3147;
17: _3243 <= _3152;
18: _3243 <= _3157;
19: _3243 <= _3162;
20: _3243 <= _3167;
21: _3243 <= _3172;
22: _3243 <= _3177;
23: _3243 <= _3182;
24: _3243 <= _3187;
25: _3243 <= _3192;
26: _3243 <= _3197;
27: _3243 <= _3202;
28: _3243 <= _3207;
29: _3243 <= _3212;
30: _3243 <= _3217;
31: _3243 <= _3222;
32: _3243 <= _3227;
33: _3243 <= _3232;
34: _3243 <= _3237;
default: _3243 <= _3242;
endcase
end
assign _3685 = decoded_rs2 == _3684;
assign _3686 = ~ _3685;
assign _3687 = _3686 ? _3243 : _3683;
assign _3803 = _3687[4:0];
assign _3837 = _3386 - _3836;
assign _3813 = _3386 - _3812;
assign _3864 = _3386 < _3863;
assign _3865 = ~ _3864;
assign _4558 = _3865 ? _3837 : _3813;
assign _4559 = _3867 ? _4128 : _4558;
assign _4560 = _2605 == _2597;
assign _4561 = _4560 ? _4559 : _4128;
assign _4562 = _2605 == _2599;
assign _4563 = _4562 ? _3803 : _4561;
assign _4564 = _2605 == _2600;
assign _4565 = _4564 ? _4557 : _4563;
assign _3384 = _4565;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_3386 <= _3383;
else
_3386 <= _3384;
end
assign _3867 = _3386 == _3866;
assign _5000 = _3867 ? _2661 : _4999;
assign _3874 = _2661 + decoded_imm;
assign _5136 = mem_done ? _3939 : _2645;
assign _4149 = _3885 ? _3873 : gnd;
assign _4150 = _3887 ? _4149 : gnd;
assign _4151 = _2605 == _2596;
assign _4152 = _4151 ? _4150 : gnd;
assign _3529 = _4152;
assign _5137 = _3529 ? _3936 : _5136;
assign _2643 = _5137;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_2645 <= _2642;
else
_2645 <= _2643;
end
assign _3885 = ~ _2645;
assign _5001 = _3885 ? _3874 : _2661;
assign _3886 = ~ _2633;
assign _3887 = _3886 | mem_done;
assign _5002 = _3887 ? _5001 : _2661;
assign _3914 = _2661 + decoded_imm;
assign _5138 = mem_done ? _3940 : _2641;
assign _4145 = _3932 ? _3913 : gnd;
assign _4146 = _3934 ? _4145 : gnd;
assign _4147 = _2605 == _2595;
assign _4148 = _4147 ? _4146 : gnd;
assign _3530 = _4148;
assign _5139 = _3530 ? _3937 : _5138;
assign _2639 = _5139;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_2641 <= _2638;
else
_2641 <= _2639;
end
assign _3932 = ~ _2641;
assign _5003 = _3932 ? _3914 : _2661;
assign _5004 = _3934 ? _5003 : _2661;
assign _5005 = _2605 == _2595;
assign _5006 = _5005 ? _5004 : _2661;
assign _5007 = _2605 == _2596;
assign _5008 = _5007 ? _5002 : _5006;
assign _5009 = _2605 == _2597;
assign _5010 = _5009 ? _5000 : _5008;
assign _5011 = _2605 == _2600;
assign _5012 = _5011 ? _4998 : _5010;
assign _2659 = _5012;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_2661 <= _2658;
else
_2661 <= _2659;
end
assign _3245 = _2661 < _2657;
assign _3256 = is[7:7];
assign _3276 = _3256 ? _3255 : _3245;
assign _3259 = instr[9:9];
assign _3270 = instr[7:7];
assign _3279 = _3270 | _3259;
assign _3273 = instr[5:5];
assign _3275 = instr[4:4];
assign _3281 = _3275 | _3273;
assign _3283 = _3281 | _3279;
assign _3284 = _3283 ? _3282 : _3276;
assign _4141 = _3284 ? _3807 : gnd;
assign _3810 = is[9:9];
assign _4142 = _3810 ? _4141 : gnd;
assign _4143 = _2605 == _2598;
assign _4144 = _4143 ? _4142 : gnd;
assign _3531 = _4144;
assign _5135 = _3531 ? _3938 : _5134;
assign _2647 = _5135;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_2649 <= _2646;
else
_2649 <= _2647;
end
assign _3945 = _2649 & mem_done;
assign _5173 = _2605 == _2595;
assign _5174 = _5173 ? _5172 : _3945;
assign _5175 = _2605 == _2596;
assign _5176 = _5175 ? _5170 : _5174;
assign _5177 = _2605 == _2598;
assign _5178 = _5177 ? _5168 : _5176;
assign _2623 = _5178;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_2625 <= _2622;
else
_2625 <= _2623;
end
assign _3648 = _2625 & _3647;
assign _3649 = _3648 & _3646;
assign _3650 = _3649 | _3581;
assign _3651 = vdd & _3650;
assign _5153 = _3651 ? _2633 : _5152;
assign _5154 = _2605 == _2602;
assign _5155 = _5154 ? _5153 : _2633;
assign _5156 = mem_done ? _3942 : _5155;
assign _2631 = _5156;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_2633 <= _2630;
else
_2633 <= _2631;
end
assign _3933 = ~ _2633;
assign _3934 = _3933 | mem_done;
assign _5237 = _3934 ? _5236 : _2605;
assign _5238 = _2605 == _2595;
assign _5239 = _5238 ? _5237 : _2605;
assign _5240 = _2605 == _2596;
assign _5241 = _5240 ? _5235 : _5239;
assign _5242 = _2605 == _2597;
assign _5243 = _5242 ? _5233 : _5241;
assign _5244 = _2605 == _2598;
assign _5245 = _5244 ? _5232 : _5243;
assign _5246 = _2605 == _2599;
assign _5247 = _5246 ? _5230 : _5245;
assign _5248 = _2605 == _2600;
assign _5249 = _5248 ? _5224 : _5247;
assign _5250 = _2605 == _2602;
assign _5251 = _5250 ? _5204 : _5249;
assign _2603 = _5251;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_2605 <= _2594;
else
_2605 <= _2603;
end
assign _4845 = _2605 == _2602;
assign _4846 = _4845 ? _4820 : _4844;
assign _3352 = _4846;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_3354 <= _3351;
else
_3354 <= _3352;
end
assign _5252 = _3354 & _3346;
assign _5253 = _5252 ? _3382 : _3369;
/* aliases */
/* output assignments */
assign next_pc = _5253;
assign reg_op1 = _2661;
assign reg_op2 = _2657;
assign trap = _2653;
assign mem_do_rinst = _2649;
assign mem_do_wdata = _2645;
assign mem_do_rdata = _2641;
assign mem_wordsize = _2637;
assign mem_do_prefetch = _2633;
assign pcpi_valid = _2629;
assign decoder_trigger = _2625;
assign decoder_trigger_q = _2621;
assign decoder_pseudo_trigger = _2617;
assign eoi = _2613;
assign ascii_state = ascii_state_0;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__PROBEC_P_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__PROBEC_P_BEHAVIORAL_PP_V
/**
* probec_p: Virtual current probe point.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__probec_p (
X ,
A ,
VGND,
VNB ,
VPB ,
VPWR
);
// Module ports
output X ;
input A ;
input VGND;
input VNB ;
input VPB ;
input VPWR;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__PROBEC_P_BEHAVIORAL_PP_V
|
(* Copyright (c) 2009-2012, 2015, Adam Chlipala
*
* This work is licensed under a
* Creative Commons Attribution-Noncommercial-No Derivative Works 3.0
* Unported License.
* The license text is available at:
* http://creativecommons.org/licenses/by-nc-nd/3.0/
*)
(* begin hide *)
Require Import List.
Require Import DepList CpdtTactics.
Set Implicit Arguments.
Set Asymmetric Patterns.
(* end hide *)
(** printing $ %({}*% #(<a/>*# *)
(** printing ^ %*{})% #*<a/>)# *)
(** %\chapter{Universes and Axioms}% *)
(** Many traditional theorems can be proved in Coq without special knowledge of CIC, the logic behind the prover. A development just seems to be using a particular ASCII notation for standard formulas based on %\index{set theory}%set theory. Nonetheless, as we saw in Chapter 4, CIC differs from set theory in starting from fewer orthogonal primitives. It is possible to define the usual logical connectives as derived notions. The foundation of it all is a dependently typed functional programming language, based on dependent function types and inductive type families. By using the facilities of this language directly, we can accomplish some things much more easily than in mainstream math.
%\index{Gallina}%Gallina, which adds features to the more theoretical CIC%~\cite{CIC}%, is the logic implemented in Coq. It has a relatively simple foundation that can be defined rigorously in a page or two of formal proof rules. Still, there are some important subtleties that have practical ramifications. This chapter focuses on those subtleties, avoiding formal metatheory in favor of example code. *)
(** * The [Type] Hierarchy *)
(** %\index{type hierarchy}%Every object in Gallina has a type. *)
Check 0.
(** %\vspace{-.15in}% [[
0
: nat
]]
It is natural enough that zero be considered as a natural number. *)
Check nat.
(** %\vspace{-.15in}% [[
nat
: Set
]]
From a set theory perspective, it is unsurprising to consider the natural numbers as a "set." *)
Check Set.
(** %\vspace{-.15in}% [[
Set
: Type
]]
The type [Set] may be considered as the set of all sets, a concept that set theory handles in terms of%\index{class (in set theory)}% _classes_. In Coq, this more general notion is [Type]. *)
Check Type.
(** %\vspace{-.15in}% [[
Type
: Type
]]
Strangely enough, [Type] appears to be its own type. It is known that polymorphic languages with this property are inconsistent, via %\index{Girard's paradox}%Girard's paradox%~\cite{GirardsParadox}%. That is, using such a language to encode proofs is unwise, because it is possible to "prove" any proposition. What is really going on here?
Let us repeat some of our queries after toggling a flag related to Coq's printing behavior.%\index{Vernacular commands!Set Printing Universes}% *)
Set Printing Universes.
Check nat.
(** %\vspace{-.15in}% [[
nat
: Set
]]
*)
Check Set.
(** %\vspace{-.15in}% [[
Set
: Type $ (0)+1 ^
]]
*)
Check Type.
(** %\vspace{-.15in}% [[
Type $ Top.3 ^
: Type $ (Top.3)+1 ^
]]
Occurrences of [Type] are annotated with some additional information, inside comments. These annotations have to do with the secret behind [Type]: it really stands for an infinite hierarchy of types. The type of [Set] is [Type(0)], the type of [Type(0)] is [Type(1)], the type of [Type(1)] is [Type(2)], and so on. This is how we avoid the "[Type : Type]" paradox. As a convenience, the universe hierarchy drives Coq's one variety of subtyping. Any term whose type is [Type] at level [i] is automatically also described by [Type] at level [j] when [j > i].
In the outputs of our first [Check] query, we see that the type level of [Set]'s type is [(0)+1]. Here [0] stands for the level of [Set], and we increment it to arrive at the level that _classifies_ [Set].
In the third query's output, we see that the occurrence of [Type] that we check is assigned a fresh%\index{universe variable}% _universe variable_ [Top.3]. The output type increments [Top.3] to move up a level in the universe hierarchy. As we write code that uses definitions whose types mention universe variables, unification may refine the values of those variables. Luckily, the user rarely has to worry about the details.
Another crucial concept in CIC is%\index{predicativity}% _predicativity_. Consider these queries. *)
Check forall T : nat, fin T.
(** %\vspace{-.15in}% [[
forall T : nat, fin T
: Set
]]
*)
Check forall T : Set, T.
(** %\vspace{-.15in}% [[
forall T : Set, T
: Type $ max(0, (0)+1) ^
]]
*)
Check forall T : Type, T.
(** %\vspace{-.15in}% [[
forall T : Type $ Top.9 ^ , T
: Type $ max(Top.9, (Top.9)+1) ^
]]
These outputs demonstrate the rule for determining which universe a [forall] type lives in. In particular, for a type [forall x : T1, T2], we take the maximum of the universes of [T1] and [T2]. In the first example query, both [T1] ([nat]) and [T2] ([fin T]) are in [Set], so the [forall] type is in [Set], too. In the second query, [T1] is [Set], which is at level [(0)+1]; and [T2] is [T], which is at level [0]. Thus, the [forall] exists at the maximum of these two levels. The third example illustrates the same outcome, where we replace [Set] with an occurrence of [Type] that is assigned universe variable [Top.9]. This universe variable appears in the places where [0] appeared in the previous query.
The behind-the-scenes manipulation of universe variables gives us predicativity. Consider this simple definition of a polymorphic identity function, where the first argument [T] will automatically be marked as implicit, since it can be inferred from the type of the second argument [x]. *)
Definition id (T : Set) (x : T) : T := x.
Check id 0.
(** %\vspace{-.15in}% [[
id 0
: nat
Check id Set.
]]
<<
Error: Illegal application (Type Error):
...
The 1st term has type "Type (* (Top.15)+1 *)"
which should be coercible to "Set".
>>
The parameter [T] of [id] must be instantiated with a [Set]. The type [nat] is a [Set], but [Set] is not. We can try fixing the problem by generalizing our definition of [id]. *)
Reset id.
Definition id (T : Type) (x : T) : T := x.
Check id 0.
(** %\vspace{-.15in}% [[
id 0
: nat
]]
*)
Check id Set.
(** %\vspace{-.15in}% [[
id Set
: Type $ Top.17 ^
]]
*)
Check id Type.
(** %\vspace{-.15in}% [[
id Type $ Top.18 ^
: Type $ Top.19 ^
]]
*)
(** So far so good. As we apply [id] to different [T] values, the inferred index for [T]'s [Type] occurrence automatically moves higher up the type hierarchy.
[[
Check id id.
]]
<<
Error: Universe inconsistency (cannot enforce Top.16 < Top.16).
>>
%\index{universe inconsistency}%This error message reminds us that the universe variable for [T] still exists, even though it is usually hidden. To apply [id] to itself, that variable would need to be less than itself in the type hierarchy. Universe inconsistency error messages announce cases like this one where a term could only type-check by violating an implied constraint over universe variables. Such errors demonstrate that [Type] is _predicative_, where this word has a CIC meaning closely related to its usual mathematical meaning. A predicative system enforces the constraint that, when an object is defined using some sort of quantifier, none of the quantifiers may ever be instantiated with the object itself. %\index{impredicativity}%Impredicativity is associated with popular paradoxes in set theory, involving inconsistent constructions like "the set of all sets that do not contain themselves" (%\index{Russell's paradox}%Russell's paradox). Similar paradoxes would result from uncontrolled impredicativity in Coq. *)
(** ** Inductive Definitions *)
(** Predicativity restrictions also apply to inductive definitions. As an example, let us consider a type of expression trees that allows injection of any native Coq value. The idea is that an [exp T] stands for an encoded expression of type [T].
[[
Inductive exp : Set -> Set :=
| Const : forall T : Set, T -> exp T
| Pair : forall T1 T2, exp T1 -> exp T2 -> exp (T1 * T2)
| Eq : forall T, exp T -> exp T -> exp bool.
]]
<<
Error: Large non-propositional inductive types must be in Type.
>>
This definition is%\index{large inductive types}% _large_ in the sense that at least one of its constructors takes an argument whose type has type [Type]. Coq would be inconsistent if we allowed definitions like this one in their full generality. Instead, we must change [exp] to live in [Type]. We will go even further and move [exp]'s index to [Type] as well. *)
Inductive exp : Type -> Type :=
| Const : forall T, T -> exp T
| Pair : forall T1 T2, exp T1 -> exp T2 -> exp (T1 * T2)
| Eq : forall T, exp T -> exp T -> exp bool.
(** Note that before we had to include an annotation [: Set] for the variable [T] in [Const]'s type, but we need no annotation now. When the type of a variable is not known, and when that variable is used in a context where only types are allowed, Coq infers that the variable is of type [Type], the right behavior here, though it was wrong for the [Set] version of [exp].
Our new definition is accepted. We can build some sample expressions. *)
Check Const 0.
(** %\vspace{-.15in}% [[
Const 0
: exp nat
]]
*)
Check Pair (Const 0) (Const tt).
(** %\vspace{-.15in}% [[
Pair (Const 0) (Const tt)
: exp (nat * unit)
]]
*)
Check Eq (Const Set) (Const Type).
(** %\vspace{-.15in}% [[
Eq (Const Set) (Const Type $ Top.59 ^ )
: exp bool
]]
We can check many expressions, including fancy expressions that include types. However, it is not hard to hit a type-checking wall.
[[
Check Const (Const O).
]]
<<
Error: Universe inconsistency (cannot enforce Top.42 < Top.42).
>>
We are unable to instantiate the parameter [T] of [Const] with an [exp] type. To see why, it is helpful to print the annotated version of [exp]'s inductive definition. *)
(** [[
Print exp.
]]
%\vspace{-.15in}%[[
Inductive exp
: Type $ Top.8 ^ ->
Type
$ max(0, (Top.11)+1, (Top.14)+1, (Top.15)+1, (Top.19)+1) ^ :=
Const : forall T : Type $ Top.11 ^ , T -> exp T
| Pair : forall (T1 : Type $ Top.14 ^ ) (T2 : Type $ Top.15 ^ ),
exp T1 -> exp T2 -> exp (T1 * T2)
| Eq : forall T : Type $ Top.19 ^ , exp T -> exp T -> exp bool
]]
We see that the index type of [exp] has been assigned to universe level [Top.8]. In addition, each of the four occurrences of [Type] in the types of the constructors gets its own universe variable. Each of these variables appears explicitly in the type of [exp]. In particular, any type [exp T] lives at a universe level found by incrementing by one the maximum of the four argument variables. Therefore, [exp] _must_ live at a higher universe level than any type which may be passed to one of its constructors. This consequence led to the universe inconsistency.
Strangely, the universe variable [Top.8] only appears in one place. Is there no restriction imposed on which types are valid arguments to [exp]? In fact, there is a restriction, but it only appears in a global set of universe constraints that are maintained "off to the side," not appearing explicitly in types. We can print the current database.%\index{Vernacular commands!Print Universes}% *)
Print Universes.
(** %\vspace{-.15in}% [[
Top.19 < Top.9 <= Top.8
Top.15 < Top.9 <= Top.8 <= Coq.Init.Datatypes.38
Top.14 < Top.9 <= Top.8 <= Coq.Init.Datatypes.37
Top.11 < Top.9 <= Top.8
]]
The command outputs many more constraints, but we have collected only those that mention [Top] variables. We see one constraint for each universe variable associated with a constructor argument from [exp]'s definition. Universe variable [Top.19] is the type argument to [Eq]. The constraint for [Top.19] effectively says that [Top.19] must be less than [Top.8], the universe of [exp]'s indices; an intermediate variable [Top.9] appears as an artifact of the way the constraint was generated.
The next constraint, for [Top.15], is more complicated. This is the universe of the second argument to the [Pair] constructor. Not only must [Top.15] be less than [Top.8], but it also comes out that [Top.8] must be less than [Coq.Init.Datatypes.38]. What is this new universe variable? It is from the definition of the [prod] inductive family, to which types of the form [A * B] are desugared. *)
(* begin hide *)
(* begin thide *)
Inductive prod := pair.
Reset prod.
(* end thide *)
(* end hide *)
(** %\vspace{-.3in}%[[
Print prod.
]]
%\vspace{-.15in}%[[
Inductive prod (A : Type $ Coq.Init.Datatypes.37 ^ )
(B : Type $ Coq.Init.Datatypes.38 ^ )
: Type $ max(Coq.Init.Datatypes.37, Coq.Init.Datatypes.38) ^ :=
pair : A -> B -> A * B
]]
We see that the constraint is enforcing that indices to [exp] must not live in a higher universe level than [B]-indices to [prod]. The next constraint above establishes a symmetric condition for [A].
Thus it is apparent that Coq maintains a tortuous set of universe variable inequalities behind the scenes. It may look like some functions are polymorphic in the universe levels of their arguments, but what is really happening is imperative updating of a system of constraints, such that all uses of a function are consistent with a global set of universe levels. When the constraint system may not be evolved soundly, we get a universe inconsistency error.
%\medskip%
The annotated definition of [prod] reveals something interesting. A type [prod A B] lives at a universe that is the maximum of the universes of [A] and [B]. From our earlier experiments, we might expect that [prod]'s universe would in fact need to be _one higher_ than the maximum. The critical difference is that, in the definition of [prod], [A] and [B] are defined as _parameters_; that is, they appear named to the left of the main colon, rather than appearing (possibly unnamed) to the right.
Parameters are not as flexible as normal inductive type arguments. The range types of all of the constructors of a parameterized type must share the same parameters. Nonetheless, when it is possible to define a polymorphic type in this way, we gain the ability to use the new type family in more ways, without triggering universe inconsistencies. For instance, nested pairs of types are perfectly legal. *)
Check (nat, (Type, Set)).
(** %\vspace{-.15in}% [[
(nat, (Type $ Top.44 ^ , Set))
: Set * (Type $ Top.45 ^ * Type $ Top.46 ^ )
]]
The same cannot be done with a counterpart to [prod] that does not use parameters. *)
Inductive prod' : Type -> Type -> Type :=
| pair' : forall A B : Type, A -> B -> prod' A B.
(** %\vspace{-.15in}%[[
Check (pair' nat (pair' Type Set)).
]]
<<
Error: Universe inconsistency (cannot enforce Top.51 < Top.51).
>>
The key benefit parameters bring us is the ability to avoid quantifying over types in the types of constructors. Such quantification induces less-than constraints, while parameters only introduce less-than-or-equal-to constraints.
Coq includes one more (potentially confusing) feature related to parameters. While Gallina does not support real %\index{universe polymorphism}%universe polymorphism, there is a convenience facility that mimics universe polymorphism in some cases. We can illustrate what this means with a simple example. *)
Inductive foo (A : Type) : Type :=
| Foo : A -> foo A.
(* begin hide *)
Unset Printing Universes.
(* end hide *)
Check foo nat.
(** %\vspace{-.15in}% [[
foo nat
: Set
]]
*)
Check foo Set.
(** %\vspace{-.15in}% [[
foo Set
: Type
]]
*)
Check foo True.
(** %\vspace{-.15in}% [[
foo True
: Prop
]]
The basic pattern here is that Coq is willing to automatically build a "copied-and-pasted" version of an inductive definition, where some occurrences of [Type] have been replaced by [Set] or [Prop]. In each context, the type-checker tries to find the valid replacements that are lowest in the type hierarchy. Automatic cloning of definitions can be much more convenient than manual cloning. We have already taken advantage of the fact that we may re-use the same families of tuple and list types to form values in [Set] and [Type].
Imitation polymorphism can be confusing in some contexts. For instance, it is what is responsible for this weird behavior. *)
Inductive bar : Type := Bar : bar.
Check bar.
(** %\vspace{-.15in}% [[
bar
: Prop
]]
The type that Coq comes up with may be used in strictly more contexts than the type one might have expected. *)
(** ** Deciphering Baffling Messages About Inability to Unify *)
(** One of the most confusing sorts of Coq error messages arises from an interplay between universes, syntax notations, and %\index{implicit arguments}%implicit arguments. Consider the following innocuous lemma, which is symmetry of equality for the special case of types. *)
Theorem symmetry : forall A B : Type,
A = B
-> B = A.
intros ? ? H; rewrite H; reflexivity.
Qed.
(** Let us attempt an admittedly silly proof of the following theorem. *)
Theorem illustrative_but_silly_detour : unit = unit.
(** %\vspace{-.25in}%[[
apply symmetry.
]]
<<
Error: Impossible to unify "?35 = ?34" with "unit = unit".
>>
Coq tells us that we cannot, in fact, apply our lemma [symmetry] here, but the error message seems defective. In particular, one might think that [apply] should unify [?35] and [?34] with [unit] to ensure that the unification goes through. In fact, the issue is in a part of the unification problem that is _not_ shown to us in this error message!
The following command is the secret to getting better error messages in such cases:%\index{Vernacular commands!Set Printing All}% *)
Set Printing All.
(** %\vspace{-.15in}%[[
apply symmetry.
]]
<<
Error: Impossible to unify "@eq Type ?46 ?45" with "@eq Set unit unit".
>>
Now we can see the problem: it is the first, _implicit_ argument to the underlying equality function [eq] that disagrees across the two terms. The universe [Set] may be both an element and a subtype of [Type], but the two are not definitionally equal. *)
Abort.
(** A variety of changes to the theorem statement would lead to use of [Type] as the implicit argument of [eq]. Here is one such change. *)
Theorem illustrative_but_silly_detour : (unit : Type) = unit.
apply symmetry; reflexivity.
Qed.
(** There are many related issues that can come up with error messages, where one or both of notations and implicit arguments hide important details. The [Set Printing All] command turns off all such features and exposes underlying CIC terms.
For completeness, we mention one other class of confusing error message about inability to unify two terms that look obviously unifiable. Each unification variable has a scope; a unification variable instantiation may not mention variables that were not already defined within that scope, at the point in proof search where the unification variable was introduced. Consider this illustrative example: *)
Unset Printing All.
Theorem ex_symmetry : (exists x, x = 0) -> (exists x, 0 = x).
eexists.
(** %\vspace{-.15in}%[[
H : exists x : nat, x = 0
============================
0 = ?98
]]
*)
destruct H.
(** %\vspace{-.15in}%[[
x : nat
H : x = 0
============================
0 = ?99
]]
*)
(** %\vspace{-.2in}%[[
symmetry; exact H.
]]
<<
Error: In environment
x : nat
H : x = 0
The term "H" has type "x = 0" while it is expected to have type
"?99 = 0".
>>
The problem here is that variable [x] was introduced by [destruct] _after_ we introduced [?99] with [eexists], so the instantiation of [?99] may not mention [x]. A simple reordering of the proof solves the problem. *)
Restart.
destruct 1 as [x]; apply ex_intro with x; symmetry; assumption.
Qed.
(** This restriction for unification variables may seem counterintuitive, but it follows from the fact that CIC contains no concept of unification variable. Rather, to construct the final proof term, at the point in a proof where the unification variable is introduced, we replace it with the instantiation we eventually find for it. It is simply syntactically illegal to refer there to variables that are not in scope. Without such a restriction, we could trivially "prove" such non-theorems as [exists n : nat, forall m : nat, n = m] by [econstructor; intro; reflexivity]. *)
(** * The [Prop] Universe *)
(** In Chapter 4, we saw parallel versions of useful datatypes for "programs" and "proofs." The convention was that programs live in [Set], and proofs live in [Prop]. We gave little explanation for why it is useful to maintain this distinction. There is certainly documentation value from separating programs from proofs; in practice, different concerns apply to building the two types of objects. It turns out, however, that these concerns motivate formal differences between the two universes in Coq.
Recall the types [sig] and [ex], which are the program and proof versions of existential quantification. Their definitions differ only in one place, where [sig] uses [Type] and [ex] uses [Prop]. *)
Print sig.
(** %\vspace{-.15in}% [[
Inductive sig (A : Type) (P : A -> Prop) : Type :=
exist : forall x : A, P x -> sig P
]]
*)
Print ex.
(** %\vspace{-.15in}% [[
Inductive ex (A : Type) (P : A -> Prop) : Prop :=
ex_intro : forall x : A, P x -> ex P
]]
It is natural to want a function to extract the first components of data structures like these. Doing so is easy enough for [sig]. *)
Definition projS A (P : A -> Prop) (x : sig P) : A :=
match x with
| exist v _ => v
end.
(* begin hide *)
(* begin thide *)
Definition projE := O.
(* end thide *)
(* end hide *)
(** We run into trouble with a version that has been changed to work with [ex].
[[
Definition projE A (P : A -> Prop) (x : ex P) : A :=
match x with
| ex_intro v _ => v
end.
]]
<<
Error:
Incorrect elimination of "x" in the inductive type "ex":
the return type has sort "Type" while it should be "Prop".
Elimination of an inductive object of sort Prop
is not allowed on a predicate in sort Type
because proofs can be eliminated only to build proofs.
>>
In formal Coq parlance, %\index{elimination}%"elimination" means "pattern-matching." The typing rules of Gallina forbid us from pattern-matching on a discriminee whose type belongs to [Prop], whenever the result type of the [match] has a type besides [Prop]. This is a sort of "information flow" policy, where the type system ensures that the details of proofs can never have any effect on parts of a development that are not also marked as proofs.
This restriction matches informal practice. We think of programs and proofs as clearly separated, and, outside of constructive logic, the idea of computing with proofs is ill-formed. The distinction also has practical importance in Coq, where it affects the behavior of extraction.
Recall that %\index{program extraction}%extraction is Coq's facility for translating Coq developments into programs in general-purpose programming languages like OCaml. Extraction _erases_ proofs and leaves programs intact. A simple example with [sig] and [ex] demonstrates the distinction. *)
Definition sym_sig (x : sig (fun n => n = 0)) : sig (fun n => 0 = n) :=
match x with
| exist n pf => exist _ n (sym_eq pf)
end.
Extraction sym_sig.
(** <<
(** val sym_sig : nat -> nat **)
let sym_sig x = x
>>
Since extraction erases proofs, the second components of [sig] values are elided, making [sig] a simple identity type family. The [sym_sig] operation is thus an identity function. *)
Definition sym_ex (x : ex (fun n => n = 0)) : ex (fun n => 0 = n) :=
match x with
| ex_intro n pf => ex_intro _ n (sym_eq pf)
end.
Extraction sym_ex.
(** <<
(** val sym_ex : __ **)
let sym_ex = __
>>
In this example, the [ex] type itself is in [Prop], so whole [ex] packages are erased. Coq extracts every proposition as the (Coq-specific) type <<__>>, whose single constructor is <<__>>. Not only are proofs replaced by [__], but proof arguments to functions are also removed completely, as we see here.
Extraction is very helpful as an optimization over programs that contain proofs. In languages like Haskell, advanced features make it possible to program with proofs, as a way of convincing the type checker to accept particular definitions. Unfortunately, when proofs are encoded as values in GADTs%~\cite{GADT}%, these proofs exist at runtime and consume resources. In contrast, with Coq, as long as all proofs are kept within [Prop], extraction is guaranteed to erase them.
Many fans of the %\index{Curry-Howard correspondence}%Curry-Howard correspondence support the idea of _extracting programs from proofs_. In reality, few users of Coq and related tools do any such thing. Instead, extraction is better thought of as an optimization that reduces the runtime costs of expressive typing.
%\medskip%
We have seen two of the differences between proofs and programs: proofs are subject to an elimination restriction and are elided by extraction. The remaining difference is that [Prop] is%\index{impredicativity}% _impredicative_, as this example shows. *)
Check forall P Q : Prop, P \/ Q -> Q \/ P.
(** %\vspace{-.15in}% [[
forall P Q : Prop, P \/ Q -> Q \/ P
: Prop
]]
We see that it is possible to define a [Prop] that quantifies over other [Prop]s. This is fortunate, as we start wanting that ability even for such basic purposes as stating propositional tautologies. In the next section of this chapter, we will see some reasons why unrestricted impredicativity is undesirable. The impredicativity of [Prop] interacts crucially with the elimination restriction to avoid those pitfalls.
Impredicativity also allows us to implement a version of our earlier [exp] type that does not suffer from the weakness that we found. *)
Inductive expP : Type -> Prop :=
| ConstP : forall T, T -> expP T
| PairP : forall T1 T2, expP T1 -> expP T2 -> expP (T1 * T2)
| EqP : forall T, expP T -> expP T -> expP bool.
Check ConstP 0.
(** %\vspace{-.15in}% [[
ConstP 0
: expP nat
]]
*)
Check PairP (ConstP 0) (ConstP tt).
(** %\vspace{-.15in}% [[
PairP (ConstP 0) (ConstP tt)
: expP (nat * unit)
]]
*)
Check EqP (ConstP Set) (ConstP Type).
(** %\vspace{-.15in}% [[
EqP (ConstP Set) (ConstP Type)
: expP bool
]]
*)
Check ConstP (ConstP O).
(** %\vspace{-.15in}% [[
ConstP (ConstP 0)
: expP (expP nat)
]]
In this case, our victory is really a shallow one. As we have marked [expP] as a family of proofs, we cannot deconstruct our expressions in the usual programmatic ways, which makes them almost useless for the usual purposes. Impredicative quantification is much more useful in defining inductive families that we really think of as judgments. For instance, this code defines a notion of equality that is strictly more permissive than the base equality [=]. *)
Inductive eqPlus : forall T, T -> T -> Prop :=
| Base : forall T (x : T), eqPlus x x
| Func : forall dom ran (f1 f2 : dom -> ran),
(forall x : dom, eqPlus (f1 x) (f2 x))
-> eqPlus f1 f2.
Check (Base 0).
(** %\vspace{-.15in}% [[
Base 0
: eqPlus 0 0
]]
*)
Check (Func (fun n => n) (fun n => 0 + n) (fun n => Base n)).
(** %\vspace{-.15in}% [[
Func (fun n : nat => n) (fun n : nat => 0 + n) (fun n : nat => Base n)
: eqPlus (fun n : nat => n) (fun n : nat => 0 + n)
]]
*)
Check (Base (Base 1)).
(** %\vspace{-.15in}% [[
Base (Base 1)
: eqPlus (Base 1) (Base 1)
]]
*)
(** Stating equality facts about proofs may seem baroque, but we have already seen its utility in the chapter on reasoning about equality proofs. *)
(** * Axioms *)
(** While the specific logic Gallina is hardcoded into Coq's implementation, it is possible to add certain logical rules in a controlled way. In other words, Coq may be used to reason about many different refinements of Gallina where strictly more theorems are provable. We achieve this by asserting%\index{axioms}% _axioms_ without proof.
We will motivate the idea by touring through some standard axioms, as enumerated in Coq's online FAQ. I will add additional commentary as appropriate. *)
(** ** The Basics *)
(** One simple example of a useful axiom is the %\index{law of the excluded middle}%law of the excluded middle. *)
Require Import Classical_Prop.
Print classic.
(** %\vspace{-.15in}% [[
*** [ classic : forall P : Prop, P \/ ~ P ]
]]
In the implementation of module [Classical_Prop], this axiom was defined with the command%\index{Vernacular commands!Axiom}% *)
Axiom classic : forall P : Prop, P \/ ~ P.
(** An [Axiom] may be declared with any type, in any of the universes. There is a synonym %\index{Vernacular commands!Parameter}%[Parameter] for [Axiom], and that synonym is often clearer for assertions not of type [Prop]. For instance, we can assert the existence of objects with certain properties. *)
Parameter num : nat.
Axiom positive : num > 0.
Reset num.
(** This kind of "axiomatic presentation" of a theory is very common outside of higher-order logic. However, in Coq, it is almost always preferable to stick to defining your objects, functions, and predicates via inductive definitions and functional programming.
In general, there is a significant burden associated with any use of axioms. It is easy to assert a set of axioms that together is%\index{inconsistent axioms}% _inconsistent_. That is, a set of axioms may imply [False], which allows any theorem to be proved, which defeats the purpose of a proof assistant. For example, we could assert the following axiom, which is consistent by itself but inconsistent when combined with [classic]. *)
Axiom not_classic : ~ forall P : Prop, P \/ ~ P.
Theorem uhoh : False.
generalize classic not_classic; tauto.
Qed.
Theorem uhoh_again : 1 + 1 = 3.
destruct uhoh.
Qed.
Reset not_classic.
(** On the subject of the law of the excluded middle itself, this axiom is usually quite harmless, and many practical Coq developments assume it. It has been proved metatheoretically to be consistent with CIC. Here, "proved metatheoretically" means that someone proved on paper that excluded middle holds in a _model_ of CIC in set theory%~\cite{SetsInTypes}%. All of the other axioms that we will survey in this section hold in the same model, so they are all consistent together.
Recall that Coq implements%\index{constructive logic}% _constructive_ logic by default, where the law of the excluded middle is not provable. Proofs in constructive logic can be thought of as programs. A [forall] quantifier denotes a dependent function type, and a disjunction denotes a variant type. In such a setting, excluded middle could be interpreted as a decision procedure for arbitrary propositions, which computability theory tells us cannot exist. Thus, constructive logic with excluded middle can no longer be associated with our usual notion of programming.
Given all this, why is it all right to assert excluded middle as an axiom? The intuitive justification is that the elimination restriction for [Prop] prevents us from treating proofs as programs. An excluded middle axiom that quantified over [Set] instead of [Prop] _would_ be problematic. If a development used that axiom, we would not be able to extract the code to OCaml (soundly) without implementing a genuine universal decision procedure. In contrast, values whose types belong to [Prop] are always erased by extraction, so we sidestep the axiom's algorithmic consequences.
Because the proper use of axioms is so precarious, there are helpful commands for determining which axioms a theorem relies on.%\index{Vernacular commands!Print Assumptions}% *)
Theorem t1 : forall P : Prop, P -> ~ ~ P.
tauto.
Qed.
Print Assumptions t1.
(** <<
Closed under the global context
>>
*)
Theorem t2 : forall P : Prop, ~ ~ P -> P.
(** %\vspace{-.25in}%[[
tauto.
]]
<<
Error: tauto failed.
>>
*)
intro P; destruct (classic P); tauto.
Qed.
Print Assumptions t2.
(** %\vspace{-.15in}% [[
Axioms:
classic : forall P : Prop, P \/ ~ P
]]
It is possible to avoid this dependence in some specific cases, where excluded middle _is_ provable, for decidable families of propositions. *)
Theorem nat_eq_dec : forall n m : nat, n = m \/ n <> m.
induction n; destruct m; intuition; generalize (IHn m); intuition.
Qed.
Theorem t2' : forall n m : nat, ~ ~ (n = m) -> n = m.
intros n m; destruct (nat_eq_dec n m); tauto.
Qed.
Print Assumptions t2'.
(** <<
Closed under the global context
>>
%\bigskip%
Mainstream mathematical practice assumes excluded middle, so it can be useful to have it available in Coq developments, though it is also nice to know that a theorem is proved in a simpler formal system than classical logic. There is a similar story for%\index{proof irrelevance}% _proof irrelevance_, which simplifies proof issues that would not even arise in mainstream math. *)
Require Import ProofIrrelevance.
Print proof_irrelevance.
(** %\vspace{-.15in}% [[
*** [ proof_irrelevance : forall (P : Prop) (p1 p2 : P), p1 = p2 ]
]]
This axiom asserts that any two proofs of the same proposition are equal. Recall this example function from Chapter 6. *)
(* begin hide *)
Lemma zgtz : 0 > 0 -> False.
crush.
Qed.
(* end hide *)
Definition pred_strong1 (n : nat) : n > 0 -> nat :=
match n with
| O => fun pf : 0 > 0 => match zgtz pf with end
| S n' => fun _ => n'
end.
(** We might want to prove that different proofs of [n > 0] do not lead to different results from our richly typed predecessor function. *)
Theorem pred_strong1_irrel : forall n (pf1 pf2 : n > 0), pred_strong1 pf1 = pred_strong1 pf2.
destruct n; crush.
Qed.
(** The proof script is simple, but it involved peeking into the definition of [pred_strong1]. For more complicated function definitions, it can be considerably more work to prove that they do not discriminate on details of proof arguments. This can seem like a shame, since the [Prop] elimination restriction makes it impossible to write any function that does otherwise. Unfortunately, this fact is only true metatheoretically, unless we assert an axiom like [proof_irrelevance]. With that axiom, we can prove our theorem without consulting the definition of [pred_strong1]. *)
Theorem pred_strong1_irrel' : forall n (pf1 pf2 : n > 0), pred_strong1 pf1 = pred_strong1 pf2.
intros; f_equal; apply proof_irrelevance.
Qed.
(** %\bigskip%
In the chapter on equality, we already discussed some axioms that are related to proof irrelevance. In particular, Coq's standard library includes this axiom: *)
Require Import Eqdep.
Import Eq_rect_eq.
Print eq_rect_eq.
(** %\vspace{-.15in}% [[
*** [ eq_rect_eq :
forall (U : Type) (p : U) (Q : U -> Type) (x : Q p) (h : p = p),
x = eq_rect p Q x p h ]
]]
This axiom says that it is permissible to simplify pattern matches over proofs of equalities like [e = e]. The axiom is logically equivalent to some simpler corollaries. In the theorem names, "UIP" stands for %\index{unicity of identity proofs}%"unicity of identity proofs", where "identity" is a synonym for "equality." *)
Corollary UIP_refl : forall A (x : A) (pf : x = x), pf = eq_refl x.
intros; replace pf with (eq_rect x (eq x) (eq_refl x) x pf); [
symmetry; apply eq_rect_eq
| exact (match pf as pf' return match pf' in _ = y return x = y with
| eq_refl => eq_refl x
end = pf' with
| eq_refl => eq_refl _
end) ].
Qed.
Corollary UIP : forall A (x y : A) (pf1 pf2 : x = y), pf1 = pf2.
intros; generalize pf1 pf2; subst; intros;
match goal with
| [ |- ?pf1 = ?pf2 ] => rewrite (UIP_refl pf1); rewrite (UIP_refl pf2); reflexivity
end.
Qed.
(* begin hide *)
(* begin thide *)
Require Eqdep_dec.
(* end thide *)
(* end hide *)
(** These corollaries are special cases of proof irrelevance. In developments that only need proof irrelevance for equality, there is no need to assert full irrelevance.
Another facet of proof irrelevance is that, like excluded middle, it is often provable for specific propositions. For instance, [UIP] is provable whenever the type [A] has a decidable equality operation. The module [Eqdep_dec] of the standard library contains a proof. A similar phenomenon applies to other notable cases, including less-than proofs. Thus, it is often possible to use proof irrelevance without asserting axioms.
%\bigskip%
There are two more basic axioms that are often assumed, to avoid complications that do not arise in set theory. *)
Require Import FunctionalExtensionality.
Print functional_extensionality_dep.
(** %\vspace{-.15in}% [[
*** [ functional_extensionality_dep :
forall (A : Type) (B : A -> Type) (f g : forall x : A, B x),
(forall x : A, f x = g x) -> f = g ]
]]
This axiom says that two functions are equal if they map equal inputs to equal outputs. Such facts are not provable in general in CIC, but it is consistent to assume that they are.
A simple corollary shows that the same property applies to predicates. *)
Corollary predicate_extensionality : forall (A : Type) (B : A -> Prop) (f g : forall x : A, B x),
(forall x : A, f x = g x) -> f = g.
intros; apply functional_extensionality_dep; assumption.
Qed.
(** In some cases, one might prefer to assert this corollary as the axiom, to restrict the consequences to proofs and not programs. *)
(** ** Axioms of Choice *)
(** Some Coq axioms are also points of contention in mainstream math. The most prominent example is the %\index{axiom of choice}%axiom of choice. In fact, there are multiple versions that we might consider, and, considered in isolation, none of these versions means quite what it means in classical set theory.
First, it is possible to implement a choice operator _without_ axioms in some potentially surprising cases. *)
Require Import ConstructiveEpsilon.
Check constructive_definite_description.
(** %\vspace{-.15in}% [[
constructive_definite_description
: forall (A : Set) (f : A -> nat) (g : nat -> A),
(forall x : A, g (f x) = x) ->
forall P : A -> Prop,
(forall x : A, {P x} + { ~ P x}) ->
(exists! x : A, P x) -> {x : A | P x}
]]
*)
Print Assumptions constructive_definite_description.
(** <<
Closed under the global context
>>
This function transforms a decidable predicate [P] into a function that produces an element satisfying [P] from a proof that such an element exists. The functions [f] and [g], in conjunction with an associated injectivity property, are used to express the idea that the set [A] is countable. Under these conditions, a simple brute force algorithm gets the job done: we just enumerate all elements of [A], stopping when we find one satisfying [P]. The existence proof, specified in terms of _unique_ existence [exists!], guarantees termination. The definition of this operator in Coq uses some interesting techniques, as seen in the implementation of the [ConstructiveEpsilon] module.
Countable choice is provable in set theory without appealing to the general axiom of choice. To support the more general principle in Coq, we must also add an axiom. Here is a functional version of the axiom of unique choice. *)
Require Import ClassicalUniqueChoice.
Check dependent_unique_choice.
(** %\vspace{-.15in}% [[
dependent_unique_choice
: forall (A : Type) (B : A -> Type) (R : forall x : A, B x -> Prop),
(forall x : A, exists! y : B x, R x y) ->
exists f : forall x : A, B x,
forall x : A, R x (f x)
]]
This axiom lets us convert a relational specification [R] into a function implementing that specification. We need only prove that [R] is truly a function. An alternate, stronger formulation applies to cases where [R] maps each input to one or more outputs. We also simplify the statement of the theorem by considering only non-dependent function types. *)
(* begin hide *)
(* begin thide *)
Require RelationalChoice.
(* end thide *)
(* end hide *)
Require Import ClassicalChoice.
Check choice.
(** %\vspace{-.15in}% [[
choice
: forall (A B : Type) (R : A -> B -> Prop),
(forall x : A, exists y : B, R x y) ->
exists f : A -> B, forall x : A, R x (f x)
]]
This principle is proved as a theorem, based on the unique choice axiom and an additional axiom of relational choice from the [RelationalChoice] module.
In set theory, the axiom of choice is a fundamental philosophical commitment one makes about the universe of sets. In Coq, the choice axioms say something weaker. For instance, consider the simple restatement of the [choice] axiom where we replace existential quantification by its Curry-Howard analogue, subset types. *)
Definition choice_Set (A B : Type) (R : A -> B -> Prop) (H : forall x : A, {y : B | R x y})
: {f : A -> B | forall x : A, R x (f x)} :=
exist (fun f => forall x : A, R x (f x))
(fun x => proj1_sig (H x)) (fun x => proj2_sig (H x)).
(** %\smallskip{}%Via the Curry-Howard correspondence, this "axiom" can be taken to have the same meaning as the original. It is implemented trivially as a transformation not much deeper than uncurrying. Thus, we see that the utility of the axioms that we mentioned earlier comes in their usage to build programs from proofs. Normal set theory has no explicit proofs, so the meaning of the usual axiom of choice is subtly different. In Gallina, the axioms implement a controlled relaxation of the restrictions on information flow from proofs to programs.
However, when we combine an axiom of choice with the law of the excluded middle, the idea of "choice" becomes more interesting. Excluded middle gives us a highly non-computational way of constructing proofs, but it does not change the computational nature of programs. Thus, the axiom of choice is still giving us a way of translating between two different sorts of "programs," but the input programs (which are proofs) may be written in a rich language that goes beyond normal computability. This combination truly is more than repackaging a function with a different type.
%\bigskip%
The Coq tools support a command-line flag %\index{impredicative Set}%<<-impredicative-set>>, which modifies Gallina in a more fundamental way by making [Set] impredicative. A term like [forall T : Set, T] has type [Set], and inductive definitions in [Set] may have constructors that quantify over arguments of any types. To maintain consistency, an elimination restriction must be imposed, similarly to the restriction for [Prop]. The restriction only applies to large inductive types, where some constructor quantifies over a type of type [Type]. In such cases, a value in this inductive type may only be pattern-matched over to yield a result type whose type is [Set] or [Prop]. This rule contrasts with the rule for [Prop], where the restriction applies even to non-large inductive types, and where the result type may only have type [Prop].
In old versions of Coq, [Set] was impredicative by default. Later versions make [Set] predicative to avoid inconsistency with some classical axioms. In particular, one should watch out when using impredicative [Set] with axioms of choice. In combination with excluded middle or predicate extensionality, inconsistency can result. Impredicative [Set] can be useful for modeling inherently impredicative mathematical concepts, but almost all Coq developments get by fine without it. *)
(** ** Axioms and Computation *)
(** One additional axiom-related wrinkle arises from an aspect of Gallina that is very different from set theory: a notion of _computational equivalence_ is central to the definition of the formal system. Axioms tend not to play well with computation. Consider this example. We start by implementing a function that uses a type equality proof to perform a safe type-cast. *)
Definition cast (x y : Set) (pf : x = y) (v : x) : y :=
match pf with
| eq_refl => v
end.
(** Computation over programs that use [cast] can proceed smoothly. *)
Eval compute in (cast (eq_refl (nat -> nat)) (fun n => S n)) 12.
(** %\vspace{-.15in}%[[
= 13
: nat
]]
*)
(** Things do not go as smoothly when we use [cast] with proofs that rely on axioms. *)
Theorem t3 : (forall n : nat, fin (S n)) = (forall n : nat, fin (n + 1)).
change ((forall n : nat, (fun n => fin (S n)) n) = (forall n : nat, (fun n => fin (n + 1)) n));
rewrite (functional_extensionality (fun n => fin (n + 1)) (fun n => fin (S n))); crush.
Qed.
Eval compute in (cast t3 (fun _ => First)) 12.
(** %\vspace{-.15in}%[[
= match t3 in (_ = P) return P with
| eq_refl => fun n : nat => First
end 12
: fin (12 + 1)
]]
Computation gets stuck in a pattern-match on the proof [t3]. The structure of [t3] is not known, so the match cannot proceed. It turns out a more basic problem leads to this particular situation. We ended the proof of [t3] with [Qed], so the definition of [t3] is not available to computation. That mistake is easily fixed. *)
Reset t3.
Theorem t3 : (forall n : nat, fin (S n)) = (forall n : nat, fin (n + 1)).
change ((forall n : nat, (fun n => fin (S n)) n) = (forall n : nat, (fun n => fin (n + 1)) n));
rewrite (functional_extensionality (fun n => fin (n + 1)) (fun n => fin (S n))); crush.
Defined.
Eval compute in (cast t3 (fun _ => First)) 12.
(** %\vspace{-.15in}%[[
= match
match
match
functional_extensionality
....
]]
We elide most of the details. A very unwieldy tree of nested matches on equality proofs appears. This time evaluation really _is_ stuck on a use of an axiom.
If we are careful in using tactics to prove an equality, we can still compute with casts over the proof. *)
Lemma plus1 : forall n, S n = n + 1.
induction n; simpl; intuition.
Defined.
Theorem t4 : forall n, fin (S n) = fin (n + 1).
intro; f_equal; apply plus1.
Defined.
Eval compute in cast (t4 13) First.
(** %\vspace{-.15in}% [[
= First
: fin (13 + 1)
]]
This simple computational reduction hides the use of a recursive function to produce a suitable [eq_refl] proof term. The recursion originates in our use of [induction] in [t4]'s proof. *)
(** ** Methods for Avoiding Axioms *)
(** The last section demonstrated one reason to avoid axioms: they interfere with computational behavior of terms. A further reason is to reduce the philosophical commitment of a theorem. The more axioms one assumes, the harder it becomes to convince oneself that the formal system corresponds appropriately to one's intuitions. A refinement of this last point, in applications like %\index{proof-carrying code}%proof-carrying code%~\cite{PCC}% in computer security, has to do with minimizing the size of a%\index{trusted code base}% _trusted code base_. To convince ourselves that a theorem is true, we must convince ourselves of the correctness of the program that checks the theorem. Axioms effectively become new source code for the checking program, increasing the effort required to perform a correctness audit.
An earlier section gave one example of avoiding an axiom. We proved that [pred_strong1] is agnostic to details of the proofs passed to it as arguments, by unfolding the definition of the function. A "simpler" proof keeps the function definition opaque and instead applies a proof irrelevance axiom. By accepting a more complex proof, we reduce our philosophical commitment and trusted base. (By the way, the less-than relation that the proofs in question here prove turns out to admit proof irrelevance as a theorem provable within normal Gallina!)
One dark secret of the [dep_destruct] tactic that we have used several times is reliance on an axiom. Consider this simple case analysis principle for [fin] values: *)
Theorem fin_cases : forall n (f : fin (S n)), f = First \/ exists f', f = Next f'.
intros; dep_destruct f; eauto.
Qed.
(* begin hide *)
Require Import JMeq.
(* begin thide *)
Definition jme := (JMeq, JMeq_eq).
(* end thide *)
(* end hide *)
Print Assumptions fin_cases.
(** %\vspace{-.15in}%[[
Axioms:
JMeq_eq : forall (A : Type) (x y : A), JMeq x y -> x = y
]]
The proof depends on the [JMeq_eq] axiom that we met in the chapter on equality proofs. However, a smarter tactic could have avoided an axiom dependence. Here is an alternate proof via a slightly strange looking lemma. *)
(* begin thide *)
Lemma fin_cases_again' : forall n (f : fin n),
match n return fin n -> Prop with
| O => fun _ => False
| S n' => fun f => f = First \/ exists f', f = Next f'
end f.
destruct f; eauto.
Qed.
(** We apply a variant of the %\index{convoy pattern}%convoy pattern, which we are used to seeing in function implementations. Here, the pattern helps us state a lemma in a form where the argument to [fin] is a variable. Recall that, thanks to basic typing rules for pattern-matching, [destruct] will only work effectively on types whose non-parameter arguments are variables. The %\index{tactics!exact}%[exact] tactic, which takes as argument a literal proof term, now gives us an easy way of proving the original theorem. *)
Theorem fin_cases_again : forall n (f : fin (S n)), f = First \/ exists f', f = Next f'.
intros; exact (fin_cases_again' f).
Qed.
(* end thide *)
Print Assumptions fin_cases_again.
(** %\vspace{-.15in}%
<<
Closed under the global context
>>
*)
(* begin thide *)
(** As the Curry-Howard correspondence might lead us to expect, the same pattern may be applied in programming as in proving. Axioms are relevant in programming, too, because, while Coq includes useful extensions like [Program] that make dependently typed programming more straightforward, in general these extensions generate code that relies on axioms about equality. We can use clever pattern matching to write our code axiom-free.
As an example, consider a [Set] version of [fin_cases]. We use [Set] types instead of [Prop] types, so that return values have computational content and may be used to guide the behavior of algorithms. Beside that, we are essentially writing the same "proof" in a more explicit way. *)
Definition finOut n (f : fin n) : match n return fin n -> Type with
| O => fun _ => Empty_set
| _ => fun f => {f' : _ | f = Next f'} + {f = First}
end f :=
match f with
| First _ => inright _ (eq_refl _)
| Next _ f' => inleft _ (exist _ f' (eq_refl _))
end.
(* end thide *)
(** As another example, consider the following type of formulas in first-order logic. The intent of the type definition will not be important in what follows, but we give a quick intuition for the curious reader. Our formulas may include [forall] quantification over arbitrary [Type]s, and we index formulas by environments telling which variables are in scope and what their types are; such an environment is a [list Type]. A constructor [Inject] lets us include any Coq [Prop] as a formula, and [VarEq] and [Lift] can be used for variable references, in what is essentially the de Bruijn index convention. (Again, the detail in this paragraph is not important to understand the discussion that follows!) *)
Inductive formula : list Type -> Type :=
| Inject : forall Ts, Prop -> formula Ts
| VarEq : forall T Ts, T -> formula (T :: Ts)
| Lift : forall T Ts, formula Ts -> formula (T :: Ts)
| Forall : forall T Ts, formula (T :: Ts) -> formula Ts
| And : forall Ts, formula Ts -> formula Ts -> formula Ts.
(** This example is based on my own experiences implementing variants of a program logic called XCAP%~\cite{XCAP}%, which also includes an inductive predicate for characterizing which formulas are provable. Here I include a pared-down version of such a predicate, with only two constructors, which is sufficient to illustrate certain tricky issues. *)
Inductive proof : formula nil -> Prop :=
| PInject : forall (P : Prop), P -> proof (Inject nil P)
| PAnd : forall p q, proof p -> proof q -> proof (And p q).
(** Let us prove a lemma showing that a "[P /\ Q -> P]" rule is derivable within the rules of [proof]. *)
Theorem proj1 : forall p q, proof (And p q) -> proof p.
destruct 1.
(** %\vspace{-.15in}%[[
p : formula nil
q : formula nil
P : Prop
H : P
============================
proof p
]]
*)
(** We are reminded that [induction] and [destruct] do not work effectively on types with non-variable arguments. The first subgoal, shown above, is clearly unprovable. (Consider the case where [p = Inject nil False].)
An application of the %\index{tactics!dependent destruction}%[dependent destruction] tactic (the basis for [dep_destruct]) solves the problem handily. We use a shorthand with the %\index{tactics!intros}%[intros] tactic that lets us use question marks for variable names that do not matter. *)
Restart.
Require Import Program.
intros ? ? H; dependent destruction H; auto.
Qed.
Print Assumptions proj1.
(** %\vspace{-.15in}%[[
Axioms:
eq_rect_eq : forall (U : Type) (p : U) (Q : U -> Type) (x : Q p) (h : p = p),
x = eq_rect p Q x p h
]]
Unfortunately, that built-in tactic appeals to an axiom. It is still possible to avoid axioms by giving the proof via another odd-looking lemma. Here is a first attempt that fails at remaining axiom-free, using a common equality-based trick for supporting induction on non-variable arguments to type families. The trick works fine without axioms for datatypes more traditional than [formula], but we run into trouble with our current type. *)
Lemma proj1_again' : forall r, proof r
-> forall p q, r = And p q -> proof p.
destruct 1; crush.
(** %\vspace{-.15in}%[[
H0 : Inject [] P = And p q
============================
proof p
]]
The first goal looks reasonable. Hypothesis [H0] is clearly contradictory, as [discriminate] can show. *)
discriminate.
(** %\vspace{-.15in}%[[
H : proof p
H1 : And p q = And p0 q0
============================
proof p0
]]
It looks like we are almost done. Hypothesis [H1] gives [p = p0] by injectivity of constructors, and then [H] finishes the case. *)
injection H1; intros.
(* begin hide *)
(* begin thide *)
Definition existT' := existT.
(* end thide *)
(* end hide *)
(** Unfortunately, the "equality" that we expected between [p] and [p0] comes in a strange form:
[[
H3 : existT (fun Ts : list Type => formula Ts) []%list p =
existT (fun Ts : list Type => formula Ts) []%list p0
============================
proof p0
]]
It may take a bit of tinkering, but, reviewing Chapter 3's discussion of writing injection principles manually, it makes sense that an [existT] type is the most direct way to express the output of [injection] on a dependently typed constructor. The constructor [And] is dependently typed, since it takes a parameter [Ts] upon which the types of [p] and [q] depend. Let us not dwell further here on why this goal appears; the reader may like to attempt the (impossible) exercise of building a better injection lemma for [And], without using axioms.
How exactly does an axiom come into the picture here? Let us ask [crush] to finish the proof. *)
crush.
Qed.
Print Assumptions proj1_again'.
(** %\vspace{-.15in}%[[
Axioms:
eq_rect_eq : forall (U : Type) (p : U) (Q : U -> Type) (x : Q p) (h : p = p),
x = eq_rect p Q x p h
]]
It turns out that this familiar axiom about equality (or some other axiom) is required to deduce [p = p0] from the hypothesis [H3] above. The soundness of that proof step is neither provable nor disprovable in Gallina.
Hope is not lost, however. We can produce an even stranger looking lemma, which gives us the theorem without axioms. As always when we want to do case analysis on a term with a tricky dependent type, the key is to refactor the theorem statement so that every term we [match] on has _variables_ as its type indices; so instead of talking about proofs of [And p q], we talk about proofs of an arbitrary [r], but we only conclude anything interesting when [r] is an [And]. *)
Lemma proj1_again'' : forall r, proof r
-> match r with
| And Ps p _ => match Ps return formula Ps -> Prop with
| nil => fun p => proof p
| _ => fun _ => True
end p
| _ => True
end.
destruct 1; auto.
Qed.
Theorem proj1_again : forall p q, proof (And p q) -> proof p.
intros ? ? H; exact (proj1_again'' H).
Qed.
Print Assumptions proj1_again.
(** <<
Closed under the global context
>>
This example illustrates again how some of the same design patterns we learned for dependently typed programming can be used fruitfully in theorem statements.
%\medskip%
To close the chapter, we consider one final way to avoid dependence on axioms. Often this task is equivalent to writing definitions such that they _compute_. That is, we want Coq's normal reduction to be able to run certain programs to completion. Here is a simple example where such computation can get stuck. In proving properties of such functions, we would need to apply axioms like %\index{axiom K}%K manually to make progress.
Imagine we are working with %\index{deep embedding}%deeply embedded syntax of some programming language, where each term is considered to be in the scope of a number of free variables that hold normal Coq values. To enforce proper typing, we will need to model a Coq typing environment somehow. One natural choice is as a list of types, where variable number [i] will be treated as a reference to the [i]th element of the list. *)
Section withTypes.
Variable types : list Set.
(** To give the semantics of terms, we will need to represent value environments, which assign each variable a term of the proper type. *)
Variable values : hlist (fun x : Set => x) types.
(** Now imagine that we are writing some procedure that operates on a distinguished variable of type [nat]. A hypothesis formalizes this assumption, using the standard library function [nth_error] for looking up list elements by position. *)
Variable natIndex : nat.
Variable natIndex_ok : nth_error types natIndex = Some nat.
(** It is not hard to use this hypothesis to write a function for extracting the [nat] value in position [natIndex] of [values], starting with two helpful lemmas, each of which we finish with [Defined] to mark the lemma as transparent, so that its definition may be expanded during evaluation. *)
Lemma nth_error_nil : forall A n x,
nth_error (@nil A) n = Some x
-> False.
destruct n; simpl; unfold error; congruence.
Defined.
Implicit Arguments nth_error_nil [A n x].
Lemma Some_inj : forall A (x y : A),
Some x = Some y
-> x = y.
congruence.
Defined.
Fixpoint getNat (types' : list Set) (values' : hlist (fun x : Set => x) types')
(natIndex : nat) : (nth_error types' natIndex = Some nat) -> nat :=
match values' with
| HNil => fun pf => match nth_error_nil pf with end
| HCons t ts x values'' =>
match natIndex return nth_error (t :: ts) natIndex = Some nat -> nat with
| O => fun pf =>
match Some_inj pf in _ = T return T with
| eq_refl => x
end
| S natIndex' => getNat values'' natIndex'
end
end.
End withTypes.
(** The problem becomes apparent when we experiment with running [getNat] on a concrete [types] list. *)
Definition myTypes := unit :: nat :: bool :: nil.
Definition myValues : hlist (fun x : Set => x) myTypes :=
tt ::: 3 ::: false ::: HNil.
Definition myNatIndex := 1.
Theorem myNatIndex_ok : nth_error myTypes myNatIndex = Some nat.
reflexivity.
Defined.
Eval compute in getNat myValues myNatIndex myNatIndex_ok.
(** %\vspace{-.15in}%[[
= 3
]]
We have not hit the problem yet, since we proceeded with a concrete equality proof for [myNatIndex_ok]. However, consider a case where we want to reason about the behavior of [getNat] _independently_ of a specific proof. *)
Theorem getNat_is_reasonable : forall pf, getNat myValues myNatIndex pf = 3.
intro; compute.
(**
<<
1 subgoal
>>
%\vspace{-.3in}%[[
pf : nth_error myTypes myNatIndex = Some nat
============================
match
match
pf in (_ = y)
return (nat = match y with
| Some H => H
| None => nat
end)
with
| eq_refl => eq_refl
end in (_ = T) return T
with
| eq_refl => 3
end = 3
]]
Since the details of the equality proof [pf] are not known, computation can proceed no further. A rewrite with axiom K would allow us to make progress, but we can rethink the definitions a bit to avoid depending on axioms. *)
Abort.
(** Here is a definition of a function that turns out to be useful, though no doubt its purpose will be mysterious for now. A call [update ls n x] overwrites the [n]th position of the list [ls] with the value [x], padding the end of the list with extra [x] values as needed to ensure sufficient length. *)
Fixpoint copies A (x : A) (n : nat) : list A :=
match n with
| O => nil
| S n' => x :: copies x n'
end.
Fixpoint update A (ls : list A) (n : nat) (x : A) : list A :=
match ls with
| nil => copies x n ++ x :: nil
| y :: ls' => match n with
| O => x :: ls'
| S n' => y :: update ls' n' x
end
end.
(** Now let us revisit the definition of [getNat]. *)
Section withTypes'.
Variable types : list Set.
Variable natIndex : nat.
(** Here is the trick: instead of asserting properties about the list [types], we build a "new" list that is _guaranteed by construction_ to have those properties. *)
Definition types' := update types natIndex nat.
Variable values : hlist (fun x : Set => x) types'.
(** Now a bit of dependent pattern matching helps us rewrite [getNat] in a way that avoids any use of equality proofs. *)
Fixpoint skipCopies (n : nat)
: hlist (fun x : Set => x) (copies nat n ++ nat :: nil) -> nat :=
match n with
| O => fun vs => hhd vs
| S n' => fun vs => skipCopies n' (htl vs)
end.
Fixpoint getNat' (types'' : list Set) (natIndex : nat)
: hlist (fun x : Set => x) (update types'' natIndex nat) -> nat :=
match types'' with
| nil => skipCopies natIndex
| t :: types0 =>
match natIndex return hlist (fun x : Set => x)
(update (t :: types0) natIndex nat) -> nat with
| O => fun vs => hhd vs
| S natIndex' => fun vs => getNat' types0 natIndex' (htl vs)
end
end.
End withTypes'.
(** Now the surprise comes in how easy it is to _use_ [getNat']. While typing works by modification of a types list, we can choose parameters so that the modification has no effect. *)
Theorem getNat_is_reasonable : getNat' myTypes myNatIndex myValues = 3.
reflexivity.
Qed.
(** The same parameters as before work without alteration, and we avoid use of axioms. *)
|
module spi_slave(input clk, input rst, input ss, input mosi, output miso, input sck, output done, input [bc-1:0] din, output [bc-1:0] dout);
parameter bc=8; // bit count
parameter counter_bits = 6;
reg mosi_d, mosi_q;
reg ss_d, ss_q;
reg sck_d, sck_q;
reg sck_old_d, sck_old_q;
reg [bc-1:0] data_d, data_q;
reg done_d, done_q;
reg [counter_bits-1:0] bit_ct_d, bit_ct_q;
reg [bc-1:0] dout_d, dout_q;
reg miso_d, miso_q;
assign miso = miso_q;
assign done = done_q;
assign dout = dout_q;
always @(*) begin
ss_d = ss;
mosi_d = mosi;
miso_d = miso_q;
sck_d = sck;
sck_old_d = sck_q;
data_d = data_q;
done_d = 1'b0;
bit_ct_d = bit_ct_q;
dout_d = dout_q;
if (ss_q) begin // if slave select is high (deselcted)
bit_ct_d = 0; // reset bit counter
data_d = din; // read in data
miso_d = data_q[bc-1]; // output MSB
end else begin // else slave select is low (selected)
if (!sck_old_q && sck_q) begin // rising edge
data_d = {data_q[bc-2:0], mosi_q}; // read data in and shift
bit_ct_d = bit_ct_q + 1'b1; // increment the bit counter
if (bit_ct_q == bc-1) begin // if we are on the last bit
dout_d = {data_q[bc-2:0], mosi_q}; // output the byte
done_d = 1'b1; // set transfer done flag
data_d = din; // read in new byte
end
end else if (sck_old_q && !sck_q) begin // falling edge
miso_d = data_q[bc-1]; // output MSB
end
end
end
always @(posedge clk) begin
if (rst) begin
done_q <= 1'b0;
bit_ct_q <= 3'b0;
dout_q <= 8'b0;
miso_q <= 1'b1;
end else begin
done_q <= done_d;
bit_ct_q <= bit_ct_d;
dout_q <= dout_d;
miso_q <= miso_d;
end
sck_q <= sck_d;
mosi_q <= mosi_d;
ss_q <= ss_d;
data_q <= data_d;
sck_old_q <= sck_old_d;
end
endmodule
|
//
// Generated by Bluespec Compiler, version 2021.07 (build 4cac6eb)
//
//
// Ports:
// Name I/O size props
// RDY_server_reset_request_put O 1 reg
// RDY_server_reset_response_get O 1 reg
// valid O 1
// word_fst O 64
// word_snd O 5
// verbosity I 4
// CLK I 1 clock
// RST_N I 1 reset
// req_opcode I 7
// req_f7 I 7
// req_rm I 3
// req_rs2 I 5
// req_v1 I 64
// req_v2 I 64
// req_v3 I 64
// EN_server_reset_request_put I 1
// EN_server_reset_response_get I 1
// EN_req I 1
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkFBox_Core(verbosity,
CLK,
RST_N,
EN_server_reset_request_put,
RDY_server_reset_request_put,
EN_server_reset_response_get,
RDY_server_reset_response_get,
req_opcode,
req_f7,
req_rm,
req_rs2,
req_v1,
req_v2,
req_v3,
EN_req,
valid,
word_fst,
word_snd);
input [3 : 0] verbosity;
input CLK;
input RST_N;
// action method server_reset_request_put
input EN_server_reset_request_put;
output RDY_server_reset_request_put;
// action method server_reset_response_get
input EN_server_reset_response_get;
output RDY_server_reset_response_get;
// action method req
input [6 : 0] req_opcode;
input [6 : 0] req_f7;
input [2 : 0] req_rm;
input [4 : 0] req_rs2;
input [63 : 0] req_v1;
input [63 : 0] req_v2;
input [63 : 0] req_v3;
input EN_req;
// value method valid
output valid;
// value method word_fst
output [63 : 0] word_fst;
// value method word_snd
output [4 : 0] word_snd;
// signals for module outputs
wire [63 : 0] word_fst;
wire [4 : 0] word_snd;
wire RDY_server_reset_request_put, RDY_server_reset_response_get, valid;
// inlined wires
wire [68 : 0] dw_result$wget;
wire dw_valid$wget, dw_valid$whas;
// register requestR
reg [214 : 0] requestR;
wire [214 : 0] requestR$D_IN;
wire requestR$EN;
// register resultR
reg [69 : 0] resultR;
reg [69 : 0] resultR$D_IN;
wire resultR$EN;
// register stateR
reg [1 : 0] stateR;
reg [1 : 0] stateR$D_IN;
wire stateR$EN;
// ports of submodule fpu
reg [201 : 0] fpu$server_core_request_put;
wire [69 : 0] fpu$server_core_response_get;
wire fpu$EN_server_core_request_put,
fpu$EN_server_core_response_get,
fpu$EN_server_reset_request_put,
fpu$EN_server_reset_response_get,
fpu$RDY_server_core_request_put,
fpu$RDY_server_core_response_get,
fpu$RDY_server_reset_request_put,
fpu$RDY_server_reset_response_get;
// ports of submodule frmFpuF
wire frmFpuF$CLR, frmFpuF$DEQ, frmFpuF$D_IN, frmFpuF$ENQ;
// ports of submodule resetReqsF
wire resetReqsF$CLR,
resetReqsF$DEQ,
resetReqsF$EMPTY_N,
resetReqsF$ENQ,
resetReqsF$FULL_N;
// ports of submodule resetRspsF
wire resetRspsF$CLR,
resetRspsF$DEQ,
resetRspsF$EMPTY_N,
resetRspsF$ENQ,
resetRspsF$FULL_N;
// rule scheduling signals
wire CAN_FIRE_RL_doFADD_D,
CAN_FIRE_RL_doFADD_S,
CAN_FIRE_RL_doFCLASS_D,
CAN_FIRE_RL_doFCLASS_S,
CAN_FIRE_RL_doFCVT_D_L,
CAN_FIRE_RL_doFCVT_D_LU,
CAN_FIRE_RL_doFCVT_D_S,
CAN_FIRE_RL_doFCVT_D_W,
CAN_FIRE_RL_doFCVT_D_WU,
CAN_FIRE_RL_doFCVT_LU_D,
CAN_FIRE_RL_doFCVT_LU_S,
CAN_FIRE_RL_doFCVT_L_D,
CAN_FIRE_RL_doFCVT_L_S,
CAN_FIRE_RL_doFCVT_S_D,
CAN_FIRE_RL_doFCVT_S_L,
CAN_FIRE_RL_doFCVT_S_LU,
CAN_FIRE_RL_doFCVT_S_W,
CAN_FIRE_RL_doFCVT_S_WU,
CAN_FIRE_RL_doFCVT_WU_D,
CAN_FIRE_RL_doFCVT_WU_S,
CAN_FIRE_RL_doFCVT_W_D,
CAN_FIRE_RL_doFCVT_W_S,
CAN_FIRE_RL_doFDIV_D,
CAN_FIRE_RL_doFDIV_S,
CAN_FIRE_RL_doFEQ_D,
CAN_FIRE_RL_doFEQ_S,
CAN_FIRE_RL_doFLE_D,
CAN_FIRE_RL_doFLE_S,
CAN_FIRE_RL_doFLT_D,
CAN_FIRE_RL_doFLT_S,
CAN_FIRE_RL_doFMADD_D,
CAN_FIRE_RL_doFMADD_S,
CAN_FIRE_RL_doFMAX_D,
CAN_FIRE_RL_doFMAX_S,
CAN_FIRE_RL_doFMIN_D,
CAN_FIRE_RL_doFMIN_S,
CAN_FIRE_RL_doFMSUB_D,
CAN_FIRE_RL_doFMSUB_S,
CAN_FIRE_RL_doFMUL_D,
CAN_FIRE_RL_doFMUL_S,
CAN_FIRE_RL_doFMV_D_X,
CAN_FIRE_RL_doFMV_W_X,
CAN_FIRE_RL_doFMV_X_D,
CAN_FIRE_RL_doFMV_X_W,
CAN_FIRE_RL_doFNMADD_D,
CAN_FIRE_RL_doFNMADD_S,
CAN_FIRE_RL_doFNMSUB_D,
CAN_FIRE_RL_doFNMSUB_S,
CAN_FIRE_RL_doFSGNJN_D,
CAN_FIRE_RL_doFSGNJN_S,
CAN_FIRE_RL_doFSGNJX_D,
CAN_FIRE_RL_doFSGNJX_S,
CAN_FIRE_RL_doFSGNJ_D,
CAN_FIRE_RL_doFSGNJ_S,
CAN_FIRE_RL_doFSQRT_D,
CAN_FIRE_RL_doFSQRT_S,
CAN_FIRE_RL_doFSUB_D,
CAN_FIRE_RL_doFSUB_S,
CAN_FIRE_RL_rl_drive_fpu_result,
CAN_FIRE_RL_rl_get_fpu_result,
CAN_FIRE_RL_rl_reset_begin,
CAN_FIRE_RL_rl_reset_end,
CAN_FIRE_req,
CAN_FIRE_server_reset_request_put,
CAN_FIRE_server_reset_response_get,
WILL_FIRE_RL_doFADD_D,
WILL_FIRE_RL_doFADD_S,
WILL_FIRE_RL_doFCLASS_D,
WILL_FIRE_RL_doFCLASS_S,
WILL_FIRE_RL_doFCVT_D_L,
WILL_FIRE_RL_doFCVT_D_LU,
WILL_FIRE_RL_doFCVT_D_S,
WILL_FIRE_RL_doFCVT_D_W,
WILL_FIRE_RL_doFCVT_D_WU,
WILL_FIRE_RL_doFCVT_LU_D,
WILL_FIRE_RL_doFCVT_LU_S,
WILL_FIRE_RL_doFCVT_L_D,
WILL_FIRE_RL_doFCVT_L_S,
WILL_FIRE_RL_doFCVT_S_D,
WILL_FIRE_RL_doFCVT_S_L,
WILL_FIRE_RL_doFCVT_S_LU,
WILL_FIRE_RL_doFCVT_S_W,
WILL_FIRE_RL_doFCVT_S_WU,
WILL_FIRE_RL_doFCVT_WU_D,
WILL_FIRE_RL_doFCVT_WU_S,
WILL_FIRE_RL_doFCVT_W_D,
WILL_FIRE_RL_doFCVT_W_S,
WILL_FIRE_RL_doFDIV_D,
WILL_FIRE_RL_doFDIV_S,
WILL_FIRE_RL_doFEQ_D,
WILL_FIRE_RL_doFEQ_S,
WILL_FIRE_RL_doFLE_D,
WILL_FIRE_RL_doFLE_S,
WILL_FIRE_RL_doFLT_D,
WILL_FIRE_RL_doFLT_S,
WILL_FIRE_RL_doFMADD_D,
WILL_FIRE_RL_doFMADD_S,
WILL_FIRE_RL_doFMAX_D,
WILL_FIRE_RL_doFMAX_S,
WILL_FIRE_RL_doFMIN_D,
WILL_FIRE_RL_doFMIN_S,
WILL_FIRE_RL_doFMSUB_D,
WILL_FIRE_RL_doFMSUB_S,
WILL_FIRE_RL_doFMUL_D,
WILL_FIRE_RL_doFMUL_S,
WILL_FIRE_RL_doFMV_D_X,
WILL_FIRE_RL_doFMV_W_X,
WILL_FIRE_RL_doFMV_X_D,
WILL_FIRE_RL_doFMV_X_W,
WILL_FIRE_RL_doFNMADD_D,
WILL_FIRE_RL_doFNMADD_S,
WILL_FIRE_RL_doFNMSUB_D,
WILL_FIRE_RL_doFNMSUB_S,
WILL_FIRE_RL_doFSGNJN_D,
WILL_FIRE_RL_doFSGNJN_S,
WILL_FIRE_RL_doFSGNJX_D,
WILL_FIRE_RL_doFSGNJX_S,
WILL_FIRE_RL_doFSGNJ_D,
WILL_FIRE_RL_doFSGNJ_S,
WILL_FIRE_RL_doFSQRT_D,
WILL_FIRE_RL_doFSQRT_S,
WILL_FIRE_RL_doFSUB_D,
WILL_FIRE_RL_doFSUB_S,
WILL_FIRE_RL_rl_drive_fpu_result,
WILL_FIRE_RL_rl_get_fpu_result,
WILL_FIRE_RL_rl_reset_begin,
WILL_FIRE_RL_rl_reset_end,
WILL_FIRE_req,
WILL_FIRE_server_reset_request_put,
WILL_FIRE_server_reset_response_get;
// inputs to muxes for submodule ports
wire [214 : 0] MUX_requestR$write_1__VAL_2;
wire [201 : 0] MUX_fpu$server_core_request_put_1__VAL_1,
MUX_fpu$server_core_request_put_1__VAL_10,
MUX_fpu$server_core_request_put_1__VAL_11,
MUX_fpu$server_core_request_put_1__VAL_12,
MUX_fpu$server_core_request_put_1__VAL_13,
MUX_fpu$server_core_request_put_1__VAL_14,
MUX_fpu$server_core_request_put_1__VAL_15,
MUX_fpu$server_core_request_put_1__VAL_16,
MUX_fpu$server_core_request_put_1__VAL_17,
MUX_fpu$server_core_request_put_1__VAL_18,
MUX_fpu$server_core_request_put_1__VAL_2,
MUX_fpu$server_core_request_put_1__VAL_3,
MUX_fpu$server_core_request_put_1__VAL_4,
MUX_fpu$server_core_request_put_1__VAL_5,
MUX_fpu$server_core_request_put_1__VAL_6,
MUX_fpu$server_core_request_put_1__VAL_7,
MUX_fpu$server_core_request_put_1__VAL_8,
MUX_fpu$server_core_request_put_1__VAL_9;
wire [69 : 0] MUX_resultR$write_1__VAL_10,
MUX_resultR$write_1__VAL_11,
MUX_resultR$write_1__VAL_12,
MUX_resultR$write_1__VAL_13,
MUX_resultR$write_1__VAL_14,
MUX_resultR$write_1__VAL_15,
MUX_resultR$write_1__VAL_16,
MUX_resultR$write_1__VAL_17,
MUX_resultR$write_1__VAL_18,
MUX_resultR$write_1__VAL_19,
MUX_resultR$write_1__VAL_20,
MUX_resultR$write_1__VAL_21,
MUX_resultR$write_1__VAL_22,
MUX_resultR$write_1__VAL_23,
MUX_resultR$write_1__VAL_24,
MUX_resultR$write_1__VAL_25,
MUX_resultR$write_1__VAL_26,
MUX_resultR$write_1__VAL_27,
MUX_resultR$write_1__VAL_28,
MUX_resultR$write_1__VAL_29,
MUX_resultR$write_1__VAL_3,
MUX_resultR$write_1__VAL_30,
MUX_resultR$write_1__VAL_31,
MUX_resultR$write_1__VAL_32,
MUX_resultR$write_1__VAL_33,
MUX_resultR$write_1__VAL_34,
MUX_resultR$write_1__VAL_35,
MUX_resultR$write_1__VAL_36,
MUX_resultR$write_1__VAL_37,
MUX_resultR$write_1__VAL_38,
MUX_resultR$write_1__VAL_39,
MUX_resultR$write_1__VAL_4,
MUX_resultR$write_1__VAL_40,
MUX_resultR$write_1__VAL_41,
MUX_resultR$write_1__VAL_42,
MUX_resultR$write_1__VAL_43,
MUX_resultR$write_1__VAL_6,
MUX_resultR$write_1__VAL_7,
MUX_resultR$write_1__VAL_8,
MUX_resultR$write_1__VAL_9;
wire [68 : 0] MUX_dw_result$wset_1__VAL_1;
wire MUX_dw_result$wset_1__SEL_1;
// declarations used by system tasks
// synopsys translate_off
reg [31 : 0] v__h1224;
reg [31 : 0] v__h1777;
reg [31 : 0] v__h1966;
reg [31 : 0] v__h2168;
reg [31 : 0] v__h2418;
reg [31 : 0] v__h2593;
reg [31 : 0] v__h2768;
reg [31 : 0] v__h2950;
reg [31 : 0] v__h3139;
reg [31 : 0] v__h3337;
reg [31 : 0] v__h3520;
reg [31 : 0] v__h3693;
reg [31 : 0] v__h3882;
reg [31 : 0] v__h16640;
reg [31 : 0] v__h28741;
reg [31 : 0] v__h35941;
reg [31 : 0] v__h42829;
reg [31 : 0] v__h44905;
reg [31 : 0] v__h45689;
reg [31 : 0] v__h47303;
reg [31 : 0] v__h48090;
reg [31 : 0] v__h50764;
reg [31 : 0] v__h53335;
reg [31 : 0] v__h53495;
reg [31 : 0] v__h53671;
reg [31 : 0] v__h55194;
reg [31 : 0] v__h56303;
reg [31 : 0] v__h57430;
reg [31 : 0] v__h57911;
reg [31 : 0] v__h58124;
reg [31 : 0] v__h58311;
reg [31 : 0] v__h58491;
reg [31 : 0] v__h58676;
reg [31 : 0] v__h58848;
reg [31 : 0] v__h59020;
reg [31 : 0] v__h59199;
reg [31 : 0] v__h59386;
reg [31 : 0] v__h59583;
reg [31 : 0] v__h59744;
reg [31 : 0] v__h59907;
reg [31 : 0] v__h60075;
reg [31 : 0] v__h71274;
reg [31 : 0] v__h82193;
reg [31 : 0] v__h83807;
reg [31 : 0] v__h84594;
reg [31 : 0] v__h97596;
reg [31 : 0] v__h110093;
reg [31 : 0] v__h112152;
reg [31 : 0] v__h112936;
reg [31 : 0] v__h167802;
reg [31 : 0] v__h213792;
reg [31 : 0] v__h218378;
reg [31 : 0] v__h222864;
reg [31 : 0] v__h225599;
reg [31 : 0] v__h227516;
reg [31 : 0] v__h229453;
reg [31 : 0] v__h229605;
reg [31 : 0] v__h229762;
reg [31 : 0] v__h1218;
reg [31 : 0] v__h1771;
reg [31 : 0] v__h1960;
reg [31 : 0] v__h2162;
reg [31 : 0] v__h2412;
reg [31 : 0] v__h2587;
reg [31 : 0] v__h2762;
reg [31 : 0] v__h2944;
reg [31 : 0] v__h3133;
reg [31 : 0] v__h3331;
reg [31 : 0] v__h3514;
reg [31 : 0] v__h3687;
reg [31 : 0] v__h3876;
reg [31 : 0] v__h16634;
reg [31 : 0] v__h28735;
reg [31 : 0] v__h35935;
reg [31 : 0] v__h42823;
reg [31 : 0] v__h44899;
reg [31 : 0] v__h45683;
reg [31 : 0] v__h47297;
reg [31 : 0] v__h48084;
reg [31 : 0] v__h50758;
reg [31 : 0] v__h53329;
reg [31 : 0] v__h53489;
reg [31 : 0] v__h53665;
reg [31 : 0] v__h55188;
reg [31 : 0] v__h56297;
reg [31 : 0] v__h57424;
reg [31 : 0] v__h57905;
reg [31 : 0] v__h58118;
reg [31 : 0] v__h58305;
reg [31 : 0] v__h58485;
reg [31 : 0] v__h58670;
reg [31 : 0] v__h58842;
reg [31 : 0] v__h59014;
reg [31 : 0] v__h59193;
reg [31 : 0] v__h59380;
reg [31 : 0] v__h59577;
reg [31 : 0] v__h59738;
reg [31 : 0] v__h59901;
reg [31 : 0] v__h60069;
reg [31 : 0] v__h71268;
reg [31 : 0] v__h82187;
reg [31 : 0] v__h83801;
reg [31 : 0] v__h84588;
reg [31 : 0] v__h97590;
reg [31 : 0] v__h110087;
reg [31 : 0] v__h112146;
reg [31 : 0] v__h112930;
reg [31 : 0] v__h167796;
reg [31 : 0] v__h213786;
reg [31 : 0] v__h218372;
reg [31 : 0] v__h222858;
reg [31 : 0] v__h225593;
reg [31 : 0] v__h227510;
reg [31 : 0] v__h229447;
reg [31 : 0] v__h229599;
reg [31 : 0] v__h229756;
// synopsys translate_on
// remaining internal signals
reg [51 : 0] CASE_guard0129_0b0_sfd___39389_BITS_53_TO_2_0b_ETC__q78,
CASE_guard0129_0b0_sfd___39389_BITS_53_TO_2_0b_ETC__q79,
CASE_guard02175_0b0_theResult___snd11344_BITS__ETC__q175,
CASE_guard02175_0b0_theResult___snd11344_BITS__ETC__q176,
CASE_guard0346_0b0_sfd___30336_BITS_54_TO_3_0b_ETC__q93,
CASE_guard0346_0b0_sfd___30336_BITS_54_TO_3_0b_ETC__q94,
CASE_guard08246_0b0_sfd___37286_BITS_63_TO_12__ETC__q113,
CASE_guard08246_0b0_sfd___37286_BITS_63_TO_12__ETC__q114,
CASE_guard08975_0b0_sfd___37286_BITS_62_TO_11__ETC__q111,
CASE_guard08975_0b0_sfd___37286_BITS_62_TO_11__ETC__q112,
CASE_guard1075_0b0_sfd___30336_BITS_53_TO_2_0b_ETC__q91,
CASE_guard1075_0b0_sfd___30336_BITS_53_TO_2_0b_ETC__q92,
CASE_guard5721_0b0_sfd___35005_BITS_63_TO_12_0_ETC__q107,
CASE_guard5721_0b0_sfd___35005_BITS_63_TO_12_0_ETC__q108,
CASE_guard6451_0b0_sfd___35005_BITS_62_TO_11_0_ETC__q103,
CASE_guard6451_0b0_sfd___35005_BITS_62_TO_11_0_ETC__q104,
CASE_guard81312_0b0_theResult___snd90457_BITS__ETC__q171,
CASE_guard81312_0b0_theResult___snd90457_BITS__ETC__q172,
CASE_guard91853_0b0_sfdin01328_BITS_56_TO_5_0b_ETC__q173,
CASE_guard91853_0b0_sfdin01328_BITS_56_TO_5_0b_ETC__q174,
CASE_guard9399_0b0_sfd___39389_BITS_54_TO_3_0b_ETC__q82,
CASE_guard9399_0b0_sfd___39389_BITS_54_TO_3_0b_ETC__q83,
CASE_requestR_BITS_194_TO_192_0x1_450359962737_ETC__q7,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2474,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2492,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2661,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2676,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3013,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3031,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3170,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3185,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d5100,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d5127,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d5146;
reg [22 : 0] CASE_guard1384_0b0_sfd___31374_BITS_31_TO_9_0b_ETC__q64,
CASE_guard1384_0b0_sfd___31374_BITS_31_TO_9_0b_ETC__q65,
CASE_guard1910_0b0_sfd___31374_BITS_30_TO_8_0b_ETC__q62,
CASE_guard1910_0b0_sfd___31374_BITS_30_TO_8_0b_ETC__q63,
CASE_guard26038_0b0_sfdin35384_BITS_56_TO_34_0_ETC__q135,
CASE_guard26038_0b0_sfdin35384_BITS_56_TO_34_0_ETC__q136,
CASE_guard36028_0b0_theResult___snd45260_BITS__ETC__q137,
CASE_guard36028_0b0_theResult___snd45260_BITS__ETC__q138,
CASE_guard4468_0b0_sfd___34458_BITS_31_TO_9_0b_ETC__q51,
CASE_guard4468_0b0_sfd___34458_BITS_31_TO_9_0b_ETC__q52,
CASE_guard46250_0b0_sfdin55725_BITS_56_TO_34_0_ETC__q139,
CASE_guard46250_0b0_sfdin55725_BITS_56_TO_34_0_ETC__q140,
CASE_guard4995_0b0_sfd___34458_BITS_30_TO_8_0b_ETC__q53,
CASE_guard4995_0b0_sfd___34458_BITS_30_TO_8_0b_ETC__q54,
CASE_guard5015_0b0_sfd___35005_BITS_63_TO_41_0_ETC__q21,
CASE_guard5015_0b0_sfd___35005_BITS_63_TO_41_0_ETC__q22,
CASE_guard5545_0b0_sfd___35005_BITS_62_TO_40_0_ETC__q23,
CASE_guard5545_0b0_sfd___35005_BITS_62_TO_40_0_ETC__q24,
CASE_guard56369_0b0_theResult___snd65625_BITS__ETC__q141,
CASE_guard56369_0b0_theResult___snd65625_BITS__ETC__q142,
CASE_guard7296_0b0_sfd___37286_BITS_63_TO_41_0_ETC__q39,
CASE_guard7296_0b0_sfd___37286_BITS_63_TO_41_0_ETC__q40,
CASE_guard7822_0b0_sfd___37286_BITS_62_TO_40_0_ETC__q37,
CASE_guard7822_0b0_sfd___37286_BITS_62_TO_40_0_ETC__q38,
CASE_requestR_BITS_194_TO_192_0x1_8388607_0x2__ETC__q5,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1073,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1088,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1456,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1474,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1680,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1695,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4266,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4285,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4312,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4331,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d588,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d606;
reg [10 : 0] CASE_guard0129_0b0_x0144_BITS_10_TO_0_0b1_theR_ETC__q76,
CASE_guard0129_0b0_x0144_BITS_10_TO_0_0b1_x014_ETC__q77,
CASE_guard02175_0b0_theResult___fst_exp11398_0_ETC__q163,
CASE_guard02175_0b0_theResult___fst_exp11398_0_ETC__q164,
CASE_guard0346_0b0_0_0b1_0_0b10_out_exp0965_0b_ETC__q86,
CASE_guard0346_0b0_0_0b1_theResult___exp0962_0_ETC__q87,
CASE_guard08246_0b0_0_0b1_0_0b10_out_exp08865__ETC__q32,
CASE_guard08246_0b0_0_0b1_theResult___exp08862_ETC__q33,
CASE_guard08975_0b0_x08990_BITS_10_TO_0_0b1_th_ETC__q109,
CASE_guard08975_0b0_x08990_BITS_10_TO_0_0b1_x0_ETC__q110,
CASE_guard1075_0b0_x1090_BITS_10_TO_0_0b1_theR_ETC__q89,
CASE_guard1075_0b0_x1090_BITS_10_TO_0_0b1_x109_ETC__q90,
CASE_guard5721_0b0_0_0b1_0_0b10_out_exp6340_0b_ETC__q106,
CASE_guard5721_0b0_0_0b1_theResult___exp6337_0_ETC__q105,
CASE_guard6451_0b0_x6466_BITS_10_TO_0_0b1_theR_ETC__q101,
CASE_guard6451_0b0_x6466_BITS_10_TO_0_0b1_x646_ETC__q102,
CASE_guard81312_0b0_theResult___fst_exp90506_0_ETC__q159,
CASE_guard81312_0b0_theResult___fst_exp90506_0_ETC__q160,
CASE_guard91853_0b0_theResult___fst_exp01334_0_ETC__q161,
CASE_guard91853_0b0_theResult___fst_exp01334_0_ETC__q162,
CASE_guard9399_0b0_0_0b1_0_0b10_out_exp0018_0b_ETC__q81,
CASE_guard9399_0b0_0_0b1_theResult___exp0015_0_ETC__q80,
CASE_requestR_BITS_194_TO_192_0x1_2046_0x2_IF__ETC__q6,
CASE_requestR_BITS_194_TO_192_0x3_IF_guard0346_ETC__q88,
CASE_requestR_BITS_194_TO_192_0x3_IF_guard0824_ETC__q34,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2422,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2451,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2639,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2961,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2990,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3147,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4673,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4998,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d5067;
reg [7 : 0] CASE_guard1384_0b0_0_0b1_0_0b10_out_exp1800_0b_ETC__q57,
CASE_guard1384_0b0_0_0b1_theResult___exp1797_0_ETC__q58,
CASE_guard1910_0b0_x1925_BITS_7_TO_0_0b1_theRe_ETC__q60,
CASE_guard1910_0b0_x1925_BITS_7_TO_0_0b1_x1925_ETC__q61,
CASE_guard26038_0b0_theResult___fst_exp35390_0_ETC__q127,
CASE_guard26038_0b0_theResult___fst_exp35390_0_ETC__q128,
CASE_guard36028_0b0_theResult___fst_exp45309_0_ETC__q129,
CASE_guard36028_0b0_theResult___fst_exp45309_0_ETC__q130,
CASE_guard4468_0b0_0_0b1_0_0b10_out_exp4884_0b_ETC__q44,
CASE_guard4468_0b0_0_0b1_theResult___exp4881_0_ETC__q43,
CASE_guard46250_0b0_theResult___fst_exp55731_0_ETC__q131,
CASE_guard46250_0b0_theResult___fst_exp55731_0_ETC__q132,
CASE_guard4995_0b0_x5010_BITS_7_TO_0_0b1_theRe_ETC__q49,
CASE_guard4995_0b0_x5010_BITS_7_TO_0_0b1_x5010_ETC__q50,
CASE_guard5015_0b0_0_0b1_0_0b10_out_exp5434_0b_ETC__q18,
CASE_guard5015_0b0_0_0b1_theResult___exp5431_0_ETC__q17,
CASE_guard5545_0b0_x5560_BITS_7_TO_0_0b1_theRe_ETC__q19,
CASE_guard5545_0b0_x5560_BITS_7_TO_0_0b1_x5560_ETC__q20,
CASE_guard56369_0b0_theResult___fst_exp65679_0_ETC__q133,
CASE_guard56369_0b0_theResult___fst_exp65679_0_ETC__q134,
CASE_guard7296_0b0_0_0b1_0_0b10_out_exp7712_0b_ETC__q29,
CASE_guard7296_0b0_0_0b1_theResult___exp7709_0_ETC__q30,
CASE_guard7822_0b0_x7837_BITS_7_TO_0_0b1_theRe_ETC__q35,
CASE_guard7822_0b0_x7837_BITS_7_TO_0_0b1_x7837_ETC__q36,
CASE_requestR_BITS_194_TO_192_0x1_254_0x2_IF_r_ETC__q4,
CASE_requestR_BITS_194_TO_192_0x3_IF_guard1384_ETC__q59,
CASE_requestR_BITS_194_TO_192_0x3_IF_guard7296_ETC__q31,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1050,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1404,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1433,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1657,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3719,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3836,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4163,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4232,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d536,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d565;
reg [2 : 0] IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d61;
reg CASE_guard0129_0b0_requestR_BITS_191_TO_128_BI_ETC__q74,
CASE_guard02175_0b0_requestR_BITS_191_TO_128_B_ETC__q169,
CASE_guard26038_0b0_requestR_BITS_191_TO_128_B_ETC__q143,
CASE_guard36028_0b0_requestR_BITS_191_TO_128_B_ETC__q145,
CASE_guard4468_0b0_requestR_BITS_191_TO_128_BI_ETC__q45,
CASE_guard46250_0b0_requestR_BITS_191_TO_128_B_ETC__q147,
CASE_guard4995_0b0_requestR_BITS_191_TO_128_BI_ETC__q47,
CASE_guard5015_0b0_requestR_BITS_191_TO_128_BI_ETC__q13,
CASE_guard5545_0b0_requestR_BITS_191_TO_128_BI_ETC__q15,
CASE_guard56369_0b0_requestR_BITS_191_TO_128_B_ETC__q149,
CASE_guard5721_0b0_requestR_BITS_191_TO_128_BI_ETC__q97,
CASE_guard6451_0b0_requestR_BITS_191_TO_128_BI_ETC__q99,
CASE_guard81312_0b0_requestR_BITS_191_TO_128_B_ETC__q165,
CASE_guard91853_0b0_requestR_BITS_191_TO_128_B_ETC__q167,
CASE_guard9399_0b0_requestR_BITS_191_TO_128_BI_ETC__q72,
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q100,
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q14,
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q144,
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q146,
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q148,
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q150,
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q16,
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q166,
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q168,
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q170,
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q46,
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q48,
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q73,
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q75,
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q98;
wire [117 : 0] IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3224,
b__h110422,
x__h111322,
x__h112661;
wire [88 : 0] IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1757,
b__h43158,
x__h44058,
x__h45414;
wire [85 : 0] IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2731,
b__h82525,
x__h83201,
x__h84319;
wire [64 : 0] _1_CONCAT_DONTCARE_CONCAT_IF_requestR_3_BIT_214_ETC___d97,
_theResult_____2__h110357,
_theResult_____2__h43093,
out1___1__h111073,
out1___1__h43809;
wire [63 : 0] IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d1816,
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d1876,
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d2111,
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d2112,
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d2113,
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d2128,
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d2129,
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d2130,
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d2206,
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d2207,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1745,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1878,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3220,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3283,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3337,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d5333,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d5348,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d5426,
IF_NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_re_ETC___d1812,
IF_NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_re_ETC___d1814,
IF_NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_re_ETC___d1874,
IF_NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d3279,
IF_NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d3281,
IF_NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d3335,
requestR_BITS_127_TO_64__q3,
requestR_BITS_191_TO_128__q1,
requestR_BITS_63_TO_0__q8,
res___1__h229866,
res___1__h230304,
res___1__h230314,
res___1__h230333,
res___1__h57534,
res___1__h57770,
res___1__h57780,
res___1__h57799,
res__h166745,
res__h212818,
res__h217300,
res__h221886,
res__h224628,
res__h227363,
res__h229280,
res__h230349,
res__h230541,
res__h3932,
res__h48859,
res__h49096,
res__h54627,
res__h56150,
res__h57259,
res__h57815,
sfd___3__h15005,
sfd___3__h27286,
sfd__h3990,
x__h110179,
x__h112240,
x__h113022,
x__h16727,
x__h167888,
x__h213882,
x__h218468,
x__h222950,
x__h225685,
x__h227602,
x__h229846,
x__h230460,
x__h28828,
x__h3429,
x__h36028,
x__h3605,
x__h3778,
x__h42915,
x__h44993,
x__h45775,
x__h47391,
x__h48180,
x__h50854,
x__h53419,
x__h53579,
x__h53757,
x__h55280,
x__h56389,
x__h57514,
x__h59668,
x__h59829,
x__h59992,
x__h60162,
x__h71361,
x__h82279,
x__h83895,
x__h84681,
x__h97683;
wire [56 : 0] IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_IF_requestR_3_ETC__q117,
IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_IF_reques_ETC__q154,
IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_IF_requestR__ETC__q122,
IF_0_CONCAT_IF_IF_IF_requestR_3_BIT_214_4_THEN_ETC__q151,
IF_0_CONCAT_IF_IF_IF_requestR_3_BIT_214_4_THEN_ETC__q157,
IF_0_CONCAT_IF_IF_requestR_3_BIT_214_4_THEN_re_ETC__q119,
IF_0_CONCAT_IF_IF_requestR_3_BIT_214_4_THEN_re_ETC__q125,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1908,
_0b0_CONCAT_NOT_IF_IF_requestR_3_BIT_214_4_THEN_ETC___d4691,
_0b0_CONCAT_NOT_IF_requestR_3_BIT_214_4_THEN_re_ETC___d3858,
_theResult____h126028,
_theResult____h146240,
_theResult____h191843,
_theResult___snd__h135401,
_theResult___snd__h135412,
_theResult___snd__h135414,
_theResult___snd__h135424,
_theResult___snd__h135430,
_theResult___snd__h135453,
_theResult___snd__h145260,
_theResult___snd__h145262,
_theResult___snd__h145269,
_theResult___snd__h145275,
_theResult___snd__h145298,
_theResult___snd__h155742,
_theResult___snd__h155753,
_theResult___snd__h155755,
_theResult___snd__h155765,
_theResult___snd__h155771,
_theResult___snd__h155794,
_theResult___snd__h165625,
_theResult___snd__h165639,
_theResult___snd__h165645,
_theResult___snd__h165663,
_theResult___snd__h190457,
_theResult___snd__h190459,
_theResult___snd__h190466,
_theResult___snd__h190472,
_theResult___snd__h190495,
_theResult___snd__h201345,
_theResult___snd__h201356,
_theResult___snd__h201358,
_theResult___snd__h201368,
_theResult___snd__h201374,
_theResult___snd__h201397,
_theResult___snd__h211344,
_theResult___snd__h211358,
_theResult___snd__h211364,
_theResult___snd__h211382,
b__h46021,
result__h146853,
result__h192456,
sfd__h117253,
sfdin__h135384,
sfdin__h155725,
sfdin__h201328,
x__h146948,
x__h192551,
x__h46697,
x__h47815;
wire [54 : 0] sfd___3__h69389, sfd___3__h80336, sfd__h60177, sfd__h71373;
wire [53 : 0] sfd__h108263,
sfd__h109005,
sfd__h190524,
sfd__h201426,
sfd__h211417,
sfd__h69416,
sfd__h70159,
sfd__h80363,
sfd__h81105,
sfd__h95738,
sfd__h96481,
value__h82527;
wire [51 : 0] IF_IF_IF_IF_3074_MINUS_SEXT_IF_IF_requestR_3_B_ETC___d5121,
IF_IF_IF_IF_3074_MINUS_SEXT_IF_IF_requestR_3_B_ETC___d5123,
IF_IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d5094,
IF_IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d5096,
IF_IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d5140,
IF_IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d5142,
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2468,
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2470,
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2486,
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2488,
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d3007,
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d3009,
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d3025,
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d3027,
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d5153,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2496,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2680,
_theResult___fst_sfd__h108959,
_theResult___fst_sfd__h109714,
_theResult___fst_sfd__h109717,
_theResult___fst_sfd__h113549,
_theResult___fst_sfd__h174201,
_theResult___fst_sfd__h191260,
_theResult___fst_sfd__h191263,
_theResult___fst_sfd__h202162,
_theResult___fst_sfd__h202165,
_theResult___fst_sfd__h212177,
_theResult___fst_sfd__h212180,
_theResult___fst_sfd__h212189,
_theResult___fst_sfd__h212195,
_theResult___fst_sfd__h70113,
_theResult___fst_sfd__h70869,
_theResult___fst_sfd__h70872,
_theResult___fst_sfd__h81059,
_theResult___fst_sfd__h81814,
_theResult___fst_sfd__h81817,
_theResult___fst_sfd__h96435,
_theResult___fst_sfd__h97191,
_theResult___fst_sfd__h97194,
_theResult___sfd__h108863,
_theResult___sfd__h109618,
_theResult___sfd__h191162,
_theResult___sfd__h202064,
_theResult___sfd__h212079,
_theResult___sfd__h70016,
_theResult___sfd__h70772,
_theResult___sfd__h80963,
_theResult___sfd__h81718,
_theResult___sfd__h96338,
_theResult___sfd__h97094,
_theResult___snd_fst_sfd__h109720,
_theResult___snd_fst_sfd__h169840,
_theResult___snd_fst_sfd__h191266,
_theResult___snd_fst_sfd__h212183,
_theResult___snd_fst_sfd__h70875,
_theResult___snd_fst_sfd__h81820,
_theResult___snd_fst_sfd__h97197,
out___1_sfd__h167954,
out_sfd__h108866,
out_sfd__h109621,
out_sfd__h191165,
out_sfd__h202067,
out_sfd__h212082,
out_sfd__h70019,
out_sfd__h70775,
out_sfd__h80966,
out_sfd__h81721,
out_sfd__h96341,
out_sfd__h97097,
value__h113092;
wire [32 : 0] _theResult_____2__h45956,
_theResult_____2__h82460,
out1___1__h46448,
out1___1__h82952;
wire [31 : 0] IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d1967,
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d2022,
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d2108,
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d2109,
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d2123,
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d2125,
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d2126,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1904,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2024,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2719,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2790,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2851,
IF_NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_re_ETC___d1963,
IF_NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_re_ETC___d1965,
IF_NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_re_ETC___d2020,
IF_NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d2786,
IF_NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d2788,
IF_NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d2849,
IF_NOT_IF_IF_requestR_3_BIT_214_4_THEN_request_ETC___d2106,
IF_NOT_IF_IF_requestR_3_BIT_214_4_THEN_request_ETC___d2122,
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d48,
requestR_BITS_191_TO_128_BITS_31_TO_0__q2,
sfd___3__h34458,
sfd___3__h41374,
sfd__h28849,
x__h166751,
x__h28834,
x__h3436,
x__h3612,
x__h3785,
x__h3975,
x__h45778,
x__h47394,
x__h82282,
x__h83898;
wire [30 : 0] IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d37;
wire [24 : 0] sfd__h135482,
sfd__h145327,
sfd__h15032,
sfd__h15575,
sfd__h155823,
sfd__h165698,
sfd__h27313,
sfd__h27852,
sfd__h34485,
sfd__h35025,
sfd__h41401,
sfd__h41940,
value__h43160;
wire [23 : 0] NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2724,
NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2756,
NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2757,
NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2822,
NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d3249,
NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d3250,
NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d3308;
wire [22 : 0] IF_IF_IF_IF_0b0_CONCAT_NOT_IF_requestR_3_BIT_2_ETC___d4260,
IF_IF_IF_IF_0b0_CONCAT_NOT_IF_requestR_3_BIT_2_ETC___d4262,
IF_IF_IF_IF_3970_MINUS_SEXT_IF_requestR_3_BIT__ETC___d4306,
IF_IF_IF_IF_3970_MINUS_SEXT_IF_requestR_3_BIT__ETC___d4308,
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d1450,
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d1452,
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d1468,
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d1470,
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d4279,
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d4281,
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d4325,
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d4327,
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d582,
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d584,
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d600,
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d602,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4338,
_theResult___fst_sfd__h126011,
_theResult___fst_sfd__h136015,
_theResult___fst_sfd__h136018,
_theResult___fst_sfd__h145860,
_theResult___fst_sfd__h145863,
_theResult___fst_sfd__h15529,
_theResult___fst_sfd__h156356,
_theResult___fst_sfd__h156359,
_theResult___fst_sfd__h16082,
_theResult___fst_sfd__h16085,
_theResult___fst_sfd__h166255,
_theResult___fst_sfd__h166258,
_theResult___fst_sfd__h166267,
_theResult___fst_sfd__h166273,
_theResult___fst_sfd__h168212,
_theResult___fst_sfd__h27806,
_theResult___fst_sfd__h28358,
_theResult___fst_sfd__h28361,
_theResult___fst_sfd__h34979,
_theResult___fst_sfd__h35532,
_theResult___fst_sfd__h35535,
_theResult___fst_sfd__h41894,
_theResult___fst_sfd__h42446,
_theResult___fst_sfd__h42449,
_theResult___sfd__h135917,
_theResult___sfd__h145762,
_theResult___sfd__h15432,
_theResult___sfd__h156258,
_theResult___sfd__h15985,
_theResult___sfd__h166157,
_theResult___sfd__h27710,
_theResult___sfd__h28262,
_theResult___sfd__h34882,
_theResult___sfd__h35435,
_theResult___sfd__h41798,
_theResult___sfd__h42350,
_theResult___snd_fst_sfd__h117207,
_theResult___snd_fst_sfd__h145866,
_theResult___snd_fst_sfd__h16088,
_theResult___snd_fst_sfd__h166261,
_theResult___snd_fst_sfd__h28364,
_theResult___snd_fst_sfd__h35538,
_theResult___snd_fst_sfd__h42452,
out_sfd__h135920,
out_sfd__h145765,
out_sfd__h15435,
out_sfd__h156261,
out_sfd__h15988,
out_sfd__h166160,
out_sfd__h27713,
out_sfd__h28265,
out_sfd__h34885,
out_sfd__h35438,
out_sfd__h41801,
out_sfd__h42353,
sV1_sfd__h1473,
sV2_sfd__h1598,
value__h167957;
wire [19 : 0] NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1750,
NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1782,
NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1783,
NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1847,
NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1933,
NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1934,
NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1993;
wire [11 : 0] IF_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reques_ETC___d5007,
SEXT_IF_IF_requestR_3_BIT_214_4_THEN_requestR__ETC___d4684,
SEXT_IF_IF_requestR_3_BIT_214_4_THEN_requestR__ETC__q153,
SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_3_B_ETC___d3851,
SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_3_B_ETC__q121,
_3074_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_ETC___d3420,
_3074_MINUS_SEXT_IF_IF_requestR_3_BIT_214_4_THE_ETC___d4687,
_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d2342,
_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d2558,
_3970_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_21_ETC___d4541,
_3970_MINUS_SEXT_IF_requestR_3_BIT_214_4_THEN_r_ETC___d3854,
_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d2882,
_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d3068,
x__h108990,
x__h146981,
x__h192584,
x__h70144,
x__h81090,
x__h96466;
wire [10 : 0] IF_IF_IF_IF_3074_MINUS_SEXT_IF_IF_requestR_3_B_ETC___d4992,
IF_IF_IF_IF_3074_MINUS_SEXT_IF_IF_requestR_3_B_ETC___d4994,
IF_IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d4667,
IF_IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d4669,
IF_IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d5061,
IF_IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d5063,
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2419,
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2445,
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2447,
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2958,
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2984,
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2986,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2996,
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d2722,
SEXT_IF_IF_requestR_3_BIT_214_4_THEN_requestR__ETC__q156,
_theResult___exp__h108862,
_theResult___exp__h109617,
_theResult___exp__h191161,
_theResult___exp__h202063,
_theResult___exp__h212078,
_theResult___exp__h70015,
_theResult___exp__h70771,
_theResult___exp__h80962,
_theResult___exp__h81717,
_theResult___exp__h96337,
_theResult___exp__h97093,
_theResult___fst_exp__h108958,
_theResult___fst_exp__h109713,
_theResult___fst_exp__h109716,
_theResult___fst_exp__h174200,
_theResult___fst_exp__h190497,
_theResult___fst_exp__h190503,
_theResult___fst_exp__h190506,
_theResult___fst_exp__h191259,
_theResult___fst_exp__h191262,
_theResult___fst_exp__h201334,
_theResult___fst_exp__h201399,
_theResult___fst_exp__h201405,
_theResult___fst_exp__h201408,
_theResult___fst_exp__h202161,
_theResult___fst_exp__h202164,
_theResult___fst_exp__h211350,
_theResult___fst_exp__h211389,
_theResult___fst_exp__h211395,
_theResult___fst_exp__h211398,
_theResult___fst_exp__h212176,
_theResult___fst_exp__h212179,
_theResult___fst_exp__h212188,
_theResult___fst_exp__h212191,
_theResult___fst_exp__h70112,
_theResult___fst_exp__h70868,
_theResult___fst_exp__h70871,
_theResult___fst_exp__h81058,
_theResult___fst_exp__h81813,
_theResult___fst_exp__h81816,
_theResult___fst_exp__h96434,
_theResult___fst_exp__h97190,
_theResult___fst_exp__h97193,
_theResult___snd_fst_exp__h109719,
_theResult___snd_fst_exp__h109722,
_theResult___snd_fst_exp__h109725,
_theResult___snd_fst_exp__h191265,
_theResult___snd_fst_exp__h212182,
_theResult___snd_fst_exp__h70874,
_theResult___snd_fst_exp__h70877,
_theResult___snd_fst_exp__h70880,
_theResult___snd_fst_exp__h81819,
_theResult___snd_fst_exp__h81822,
_theResult___snd_fst_exp__h81825,
_theResult___snd_fst_exp__h97196,
_theResult___snd_fst_exp__h97199,
_theResult___snd_fst_exp__h97202,
din_inc___2_exp__h109755,
din_inc___2_exp__h212214,
din_inc___2_exp__h212244,
din_inc___2_exp__h212268,
din_inc___2_exp__h70914,
din_inc___2_exp__h81855,
din_inc___2_exp__h97236,
out_exp__h108865,
out_exp__h109620,
out_exp__h191164,
out_exp__h202066,
out_exp__h212081,
out_exp__h70018,
out_exp__h70774,
out_exp__h80965,
out_exp__h81720,
out_exp__h96340,
out_exp__h97096,
x__h167898;
wire [8 : 0] IF_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR__ETC___d4172,
_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d1321,
_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d1577,
_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d444,
_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d969,
x__h15560,
x__h27837,
x__h35010,
x__h41925;
wire [7 : 0] IF_IF_IF_IF_0b0_CONCAT_NOT_IF_requestR_3_BIT_2_ETC___d3713,
IF_IF_IF_IF_0b0_CONCAT_NOT_IF_requestR_3_BIT_2_ETC___d3715,
IF_IF_IF_IF_3970_MINUS_SEXT_IF_requestR_3_BIT__ETC___d4157,
IF_IF_IF_IF_3970_MINUS_SEXT_IF_requestR_3_BIT__ETC___d4159,
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d1401,
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d1427,
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d1429,
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d3830,
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d3832,
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d4226,
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d4228,
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d533,
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d559,
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d561,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1439,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1748,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d571,
SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_3_B_ETC__q124,
_theResult___exp__h135916,
_theResult___exp__h145761,
_theResult___exp__h15431,
_theResult___exp__h156257,
_theResult___exp__h15984,
_theResult___exp__h166156,
_theResult___exp__h27709,
_theResult___exp__h28261,
_theResult___exp__h34881,
_theResult___exp__h35434,
_theResult___exp__h41797,
_theResult___exp__h42349,
_theResult___fst_exp__h126010,
_theResult___fst_exp__h135390,
_theResult___fst_exp__h135455,
_theResult___fst_exp__h135461,
_theResult___fst_exp__h135464,
_theResult___fst_exp__h136014,
_theResult___fst_exp__h136017,
_theResult___fst_exp__h145300,
_theResult___fst_exp__h145306,
_theResult___fst_exp__h145309,
_theResult___fst_exp__h145859,
_theResult___fst_exp__h145862,
_theResult___fst_exp__h15528,
_theResult___fst_exp__h155731,
_theResult___fst_exp__h155796,
_theResult___fst_exp__h155802,
_theResult___fst_exp__h155805,
_theResult___fst_exp__h156355,
_theResult___fst_exp__h156358,
_theResult___fst_exp__h16081,
_theResult___fst_exp__h16084,
_theResult___fst_exp__h165631,
_theResult___fst_exp__h165670,
_theResult___fst_exp__h165676,
_theResult___fst_exp__h165679,
_theResult___fst_exp__h166254,
_theResult___fst_exp__h166257,
_theResult___fst_exp__h166266,
_theResult___fst_exp__h166269,
_theResult___fst_exp__h27805,
_theResult___fst_exp__h28357,
_theResult___fst_exp__h28360,
_theResult___fst_exp__h34978,
_theResult___fst_exp__h35531,
_theResult___fst_exp__h35534,
_theResult___fst_exp__h41893,
_theResult___fst_exp__h42445,
_theResult___fst_exp__h42448,
_theResult___snd_fst_exp__h145865,
_theResult___snd_fst_exp__h16087,
_theResult___snd_fst_exp__h16090,
_theResult___snd_fst_exp__h16093,
_theResult___snd_fst_exp__h166260,
_theResult___snd_fst_exp__h28363,
_theResult___snd_fst_exp__h28366,
_theResult___snd_fst_exp__h28369,
_theResult___snd_fst_exp__h35537,
_theResult___snd_fst_exp__h35540,
_theResult___snd_fst_exp__h35543,
_theResult___snd_fst_exp__h42451,
_theResult___snd_fst_exp__h42454,
_theResult___snd_fst_exp__h42457,
din_inc___2_exp__h16127,
din_inc___2_exp__h166288,
din_inc___2_exp__h166312,
din_inc___2_exp__h166342,
din_inc___2_exp__h166366,
din_inc___2_exp__h28399,
din_inc___2_exp__h35577,
din_inc___2_exp__h42487,
out_exp__h135919,
out_exp__h145764,
out_exp__h15434,
out_exp__h156260,
out_exp__h15987,
out_exp__h166159,
out_exp__h27712,
out_exp__h28264,
out_exp__h34884,
out_exp__h35437,
out_exp__h41800,
out_exp__h42352,
sV1_exp__h1472,
sV2_exp__h1597,
x__h113032;
wire [6 : 0] IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d441,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d966,
requestR_BITS_206_TO_200__q177;
wire [5 : 0] IF_IF_0b0_CONCAT_NOT_IF_requestR_3_BIT_214_4_T_ETC___d3654,
IF_IF_3074_MINUS_SEXT_IF_IF_requestR_3_BIT_214_ETC___d4933,
IF_IF_3970_MINUS_SEXT_IF_requestR_3_BIT_214_4__ETC___d4098,
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d1318,
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d2339,
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d4613,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1574,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2555,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3776;
wire [4 : 0] _0_CONCAT_IF_IF_0b0_CONCAT_NOT_IF_requestR_3_BI_ETC___d4396,
_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_IF_requestR__ETC___d5220,
_0_CONCAT_IF_IF_3970_MINUS_SEXT_IF_requestR_3_B_ETC___d4425,
_0_CONCAT_IF_IF_IF_requestR_3_BIT_214_4_THEN_re_ETC___d5203,
_0_CONCAT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d4408,
fcsr__h3933,
x__h109855,
x__h111943,
x__h112739,
x__h166866,
x__h212920,
x__h217430,
x__h227382,
x__h28503,
x__h35703,
x__h42591,
x__h44696,
x__h45492,
x__h47094,
x__h47893,
x__h50220,
x__h56169,
x__h71036,
x__h81955,
x__h83598,
x__h84397,
x__h97358;
wire [1 : 0] IF_sfd___30336_BIT_1_THEN_2_ELSE_0__q85,
IF_sfd___30336_BIT_2_THEN_2_ELSE_0__q84,
IF_sfd___31374_BIT_7_THEN_2_ELSE_0__q56,
IF_sfd___31374_BIT_8_THEN_2_ELSE_0__q55,
IF_sfd___34458_BIT_7_THEN_2_ELSE_0__q42,
IF_sfd___34458_BIT_8_THEN_2_ELSE_0__q41,
IF_sfd___35005_BIT_10_THEN_2_ELSE_0__q12,
IF_sfd___35005_BIT_11_THEN_2_ELSE_0__q11,
IF_sfd___35005_BIT_39_THEN_2_ELSE_0__q10,
IF_sfd___35005_BIT_40_THEN_2_ELSE_0__q9,
IF_sfd___37286_BIT_10_THEN_2_ELSE_0__q28,
IF_sfd___37286_BIT_11_THEN_2_ELSE_0__q27,
IF_sfd___37286_BIT_39_THEN_2_ELSE_0__q26,
IF_sfd___37286_BIT_40_THEN_2_ELSE_0__q25,
IF_sfd___39389_BIT_1_THEN_2_ELSE_0__q71,
IF_sfd___39389_BIT_2_THEN_2_ELSE_0__q70,
IF_sfdin01328_BIT_4_THEN_2_ELSE_0__q155,
IF_sfdin35384_BIT_33_THEN_2_ELSE_0__q118,
IF_sfdin55725_BIT_33_THEN_2_ELSE_0__q123,
IF_theResult___snd11344_BIT_4_THEN_2_ELSE_0__q158,
IF_theResult___snd45260_BIT_33_THEN_2_ELSE_0__q120,
IF_theResult___snd65625_BIT_33_THEN_2_ELSE_0__q126,
IF_theResult___snd90457_BIT_4_THEN_2_ELSE_0__q152,
IF_x11322_BIT_53_THEN_2_ELSE_0__q115,
IF_x12661_BIT_53_THEN_2_ELSE_0__q116,
IF_x3201_BIT_53_THEN_2_ELSE_0__q95,
IF_x4058_BIT_24_THEN_2_ELSE_0__q66,
IF_x4319_BIT_53_THEN_2_ELSE_0__q96,
IF_x5414_BIT_24_THEN_2_ELSE_0__q67,
IF_x6697_BIT_24_THEN_2_ELSE_0__q68,
IF_x7815_BIT_24_THEN_2_ELSE_0__q69,
guard__h108246,
guard__h108975,
guard__h110355,
guard__h111133,
guard__h112440,
guard__h126038,
guard__h136028,
guard__h146250,
guard__h15015,
guard__h15545,
guard__h156369,
guard__h181312,
guard__h191853,
guard__h202175,
guard__h27296,
guard__h27822,
guard__h34468,
guard__h34995,
guard__h41384,
guard__h41910,
guard__h43091,
guard__h43869,
guard__h45193,
guard__h45954,
guard__h46508,
guard__h47594,
guard__h69399,
guard__h70129,
guard__h80346,
guard__h81075,
guard__h82458,
guard__h83012,
guard__h84098,
guard__h95721,
guard__h96451;
wire IF_3074_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_21_ETC___d4358,
IF_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_2_ETC___d1379,
IF_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_2_ETC___d1529,
IF_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_2_ETC___d2398,
IF_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_2_ETC___d2513,
IF_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214__ETC___d1718,
IF_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214__ETC___d2697,
IF_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_2_ETC___d2937,
IF_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_2_ETC___d3054,
IF_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_2_ETC___d511,
IF_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_2_ETC___d693,
IF_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214__ETC___d1174,
IF_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214__ETC___d3208,
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d5188,
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d5189,
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d5224,
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d5227,
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d5234,
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d5248,
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d5260,
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d5272,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1520,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1523,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1532,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1774,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1806,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1868,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1885,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1896,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1925,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1957,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2014,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2032,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2043,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2067,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2077,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2081,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2090,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2091,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2092,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2095,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2097,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2115,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2156,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2167,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2171,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2748,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2780,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2843,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3045,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3048,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3057,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3241,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3273,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3329,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4378,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4429,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4440,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4456,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4469,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4482,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4617,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d5010,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d5326,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d684,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d687,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d696,
IF_NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_re_ETC___d1837,
IF_NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_re_ETC___d1983,
IF_NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d2812,
IF_NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d3298,
IF_NOT_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_B_ETC___d2399,
IF_NOT_3970_MINUS_0_CONCAT_IF_IF_IF_requestR_3_ETC___d5169,
IF_NOT_IF_requestR_3_BIT_214_4_THEN_requestR_3_ETC___d2101,
IF_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reques_ETC___d5186,
IF_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reques_ETC___d5246,
IF_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reques_ETC___d5258,
IF_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reques_ETC___d5270,
IF_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR__ETC___d4376,
IF_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR__ETC___d4454,
IF_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR__ETC___d4467,
IF_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR__ETC___d4480,
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d1165,
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d1168,
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d1177,
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d1709,
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d1712,
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d1721,
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d2103,
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d2169,
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d2861,
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d2872,
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d3199,
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d3202,
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d3211,
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d3346,
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d3357,
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d5294,
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d5302,
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d5306,
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d5315,
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d5317,
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d5318,
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d5322,
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d5323,
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d5339,
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d5363,
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d5373,
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d5378,
NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1785,
NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1849,
NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1936,
NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1995,
NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2759,
NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2824,
NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d3252,
NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d3310,
NOT_3074_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_2_ETC___d4448,
NOT_3074_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_2_ETC___d4476,
NOT_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_ETC___d1326,
NOT_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_ETC___d1826,
NOT_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_ETC___d1890,
NOT_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_ETC___d1975,
NOT_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_ETC___d2037,
NOT_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_ETC___d2104,
NOT_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_ETC___d2105,
NOT_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_ETC___d2166,
NOT_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_ETC___d2172,
NOT_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_ETC___d2192,
NOT_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_ETC___d2887,
NOT_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_ETC___d449,
NOT_IF_requestR_3_BIT_214_4_THEN_requestR_3_BI_ETC___d1059,
NOT_IF_requestR_3_BIT_214_4_THEN_requestR_3_BI_ETC___d1666,
NOT_IF_requestR_3_BIT_214_4_THEN_requestR_3_BI_ETC___d2801,
NOT_IF_requestR_3_BIT_214_4_THEN_requestR_3_BI_ETC___d2866,
NOT_IF_requestR_3_BIT_214_4_THEN_requestR_3_BI_ETC___d3156,
NOT_IF_requestR_3_BIT_214_4_THEN_requestR_3_BI_ETC___d3290,
NOT_IF_requestR_3_BIT_214_4_THEN_requestR_3_BI_ETC___d3351,
NOT_IF_requestR_3_BIT_214_4_THEN_requestR_3_BI_ETC___d5330,
NOT_IF_requestR_3_BIT_214_4_THEN_requestR_3_BI_ETC___d5374,
NOT_IF_requestR_3_BIT_214_4_THEN_requestR_3_BI_ETC___d5399,
NOT_verbosity_ULE_1_6___d27,
NOT_verbosity_ULE_2_01___d702,
SEXT_IF_IF_requestR_3_BIT_214_4_THEN_requestR__ETC___d4685,
SEXT_IF_IF_requestR_3_BIT_214_4_THEN_requestR__ETC___d4686,
SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_3_B_ETC___d3852,
SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_3_B_ETC___d3853,
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_IF_requestR_3_BI_ETC___d3656,
_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_IF_requestR__ETC___d4935,
_0_CONCAT_IF_IF_3970_MINUS_SEXT_IF_requestR_3_B_ETC___d4100,
_0_CONCAT_IF_IF_IF_requestR_3_BIT_214_4_THEN_re_ETC___d4615,
_0_CONCAT_IF_IF_IF_requestR_3_BIT_214_4_THEN_re_ETC___d5008,
_0_CONCAT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d3778,
_0_CONCAT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d4173,
_3074_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_ETC___d3421,
_3074_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_ETC___d3422,
_3074_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_ETC___d4411,
_3074_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_ETC___d4436,
_3074_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_ETC___d4463,
_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d1322,
_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d1324,
_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d1327,
_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d2343,
_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d2345,
_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d2347,
_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d1578,
_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d1579,
_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d1580,
_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d2559,
_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d2560,
_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d2561,
_3970_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_21_ETC___d4542,
_3970_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_21_ETC___d4543,
_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d2883,
_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d2885,
_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d2888,
_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d445,
_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d447,
_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d450,
_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d3069,
_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d3070,
_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d3071,
_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d970,
_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d971,
_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d972,
guard__h146848,
guard__h192451;
// action method server_reset_request_put
assign RDY_server_reset_request_put = resetReqsF$FULL_N ;
assign CAN_FIRE_server_reset_request_put = resetReqsF$FULL_N ;
assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ;
// action method server_reset_response_get
assign RDY_server_reset_response_get = resetRspsF$EMPTY_N ;
assign CAN_FIRE_server_reset_response_get = resetRspsF$EMPTY_N ;
assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ;
// action method req
assign CAN_FIRE_req = 1'd1 ;
assign WILL_FIRE_req = EN_req ;
// value method valid
assign valid = dw_valid$whas && dw_valid$wget ;
// value method word_fst
assign word_fst = dw_result$wget[68:5] ;
// value method word_snd
assign word_snd = dw_result$wget[4:0] ;
// submodule fpu
mkFPU fpu(.CLK(CLK),
.RST_N(RST_N),
.server_core_request_put(fpu$server_core_request_put),
.EN_server_core_request_put(fpu$EN_server_core_request_put),
.EN_server_core_response_get(fpu$EN_server_core_response_get),
.EN_server_reset_request_put(fpu$EN_server_reset_request_put),
.EN_server_reset_response_get(fpu$EN_server_reset_response_get),
.RDY_server_core_request_put(fpu$RDY_server_core_request_put),
.server_core_response_get(fpu$server_core_response_get),
.RDY_server_core_response_get(fpu$RDY_server_core_response_get),
.RDY_server_reset_request_put(fpu$RDY_server_reset_request_put),
.RDY_server_reset_response_get(fpu$RDY_server_reset_response_get));
// submodule frmFpuF
FIFO2 #(.width(32'd1), .guarded(1'd1)) frmFpuF(.RST(RST_N),
.CLK(CLK),
.D_IN(frmFpuF$D_IN),
.ENQ(frmFpuF$ENQ),
.DEQ(frmFpuF$DEQ),
.CLR(frmFpuF$CLR),
.D_OUT(),
.FULL_N(),
.EMPTY_N());
// submodule resetReqsF
FIFO20 #(.guarded(1'd1)) resetReqsF(.RST(RST_N),
.CLK(CLK),
.ENQ(resetReqsF$ENQ),
.DEQ(resetReqsF$DEQ),
.CLR(resetReqsF$CLR),
.FULL_N(resetReqsF$FULL_N),
.EMPTY_N(resetReqsF$EMPTY_N));
// submodule resetRspsF
FIFO20 #(.guarded(1'd1)) resetRspsF(.RST(RST_N),
.CLK(CLK),
.ENQ(resetRspsF$ENQ),
.DEQ(resetRspsF$DEQ),
.CLR(resetRspsF$CLR),
.FULL_N(resetRspsF$FULL_N),
.EMPTY_N(resetRspsF$EMPTY_N));
// rule RL_rl_reset_end
assign CAN_FIRE_RL_rl_reset_end =
fpu$RDY_server_reset_response_get && resetRspsF$FULL_N &&
stateR == 2'd0 ;
assign WILL_FIRE_RL_rl_reset_end = CAN_FIRE_RL_rl_reset_end ;
// rule RL_doFADD_S
assign CAN_FIRE_RL_doFADD_S =
fpu$RDY_server_core_request_put && requestR[214] &&
stateR == 2'd1 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h0 ;
assign WILL_FIRE_RL_doFADD_S = CAN_FIRE_RL_doFADD_S ;
// rule RL_doFSUB_S
assign CAN_FIRE_RL_doFSUB_S =
fpu$RDY_server_core_request_put && requestR[214] &&
stateR == 2'd1 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h04 ;
assign WILL_FIRE_RL_doFSUB_S = CAN_FIRE_RL_doFSUB_S ;
// rule RL_doFMUL_S
assign CAN_FIRE_RL_doFMUL_S =
fpu$RDY_server_core_request_put && requestR[214] &&
stateR == 2'd1 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h08 ;
assign WILL_FIRE_RL_doFMUL_S = CAN_FIRE_RL_doFMUL_S ;
// rule RL_doFMADD_S
assign CAN_FIRE_RL_doFMADD_S =
fpu$RDY_server_core_request_put && requestR[214] &&
stateR == 2'd1 &&
requestR[213:207] == 7'b1000011 &&
requestR_BITS_206_TO_200__q177[1:0] == 2'd0 ;
assign WILL_FIRE_RL_doFMADD_S = CAN_FIRE_RL_doFMADD_S ;
// rule RL_doFMSUB_S
assign CAN_FIRE_RL_doFMSUB_S =
fpu$RDY_server_core_request_put && requestR[214] &&
stateR == 2'd1 &&
requestR[213:207] == 7'b1000111 &&
requestR_BITS_206_TO_200__q177[1:0] == 2'd0 ;
assign WILL_FIRE_RL_doFMSUB_S = CAN_FIRE_RL_doFMSUB_S ;
// rule RL_doFNMADD_S
assign CAN_FIRE_RL_doFNMADD_S =
fpu$RDY_server_core_request_put && requestR[214] &&
stateR == 2'd1 &&
requestR[213:207] == 7'b1001111 &&
requestR_BITS_206_TO_200__q177[1:0] == 2'd0 ;
assign WILL_FIRE_RL_doFNMADD_S = CAN_FIRE_RL_doFNMADD_S ;
// rule RL_doFNMSUB_S
assign CAN_FIRE_RL_doFNMSUB_S =
fpu$RDY_server_core_request_put && requestR[214] &&
stateR == 2'd1 &&
requestR[213:207] == 7'b1001011 &&
requestR_BITS_206_TO_200__q177[1:0] == 2'd0 ;
assign WILL_FIRE_RL_doFNMSUB_S = CAN_FIRE_RL_doFNMSUB_S ;
// rule RL_doFDIV_S
assign CAN_FIRE_RL_doFDIV_S =
fpu$RDY_server_core_request_put && requestR[214] &&
stateR == 2'd1 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h0C ;
assign WILL_FIRE_RL_doFDIV_S = CAN_FIRE_RL_doFDIV_S ;
// rule RL_doFSQRT_S
assign CAN_FIRE_RL_doFSQRT_S =
fpu$RDY_server_core_request_put && requestR[214] &&
stateR == 2'd1 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h2C ;
assign WILL_FIRE_RL_doFSQRT_S = CAN_FIRE_RL_doFSQRT_S ;
// rule RL_doFSGNJ_S
assign CAN_FIRE_RL_doFSGNJ_S =
requestR[214] && stateR == 2'd1 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h10 &&
requestR[194:192] == 3'h0 ;
assign WILL_FIRE_RL_doFSGNJ_S = CAN_FIRE_RL_doFSGNJ_S ;
// rule RL_doFSGNJN_S
assign CAN_FIRE_RL_doFSGNJN_S =
requestR[214] && stateR == 2'd1 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h10 &&
requestR[194:192] == 3'h1 ;
assign WILL_FIRE_RL_doFSGNJN_S = CAN_FIRE_RL_doFSGNJN_S ;
// rule RL_doFSGNJX_S
assign CAN_FIRE_RL_doFSGNJX_S =
requestR[214] && stateR == 2'd1 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h10 &&
requestR[194:192] == 3'h2 ;
assign WILL_FIRE_RL_doFSGNJX_S = CAN_FIRE_RL_doFSGNJX_S ;
// rule RL_doFCVT_S_L
assign CAN_FIRE_RL_doFCVT_S_L =
requestR[214] && stateR == 2'd1 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h68 &&
requestR[199:195] == 5'd2 ;
assign WILL_FIRE_RL_doFCVT_S_L = CAN_FIRE_RL_doFCVT_S_L ;
// rule RL_doFCVT_S_LU
assign CAN_FIRE_RL_doFCVT_S_LU =
requestR[214] && stateR == 2'd1 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h68 &&
requestR[199:195] == 5'd3 ;
assign WILL_FIRE_RL_doFCVT_S_LU = CAN_FIRE_RL_doFCVT_S_LU ;
// rule RL_doFCVT_S_W
assign CAN_FIRE_RL_doFCVT_S_W =
requestR[214] && stateR == 2'd1 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h68 &&
requestR[199:195] == 5'd0 ;
assign WILL_FIRE_RL_doFCVT_S_W = CAN_FIRE_RL_doFCVT_S_W ;
// rule RL_doFCVT_S_WU
assign CAN_FIRE_RL_doFCVT_S_WU =
requestR[214] && stateR == 2'd1 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h68 &&
requestR[199:195] == 5'd1 ;
assign WILL_FIRE_RL_doFCVT_S_WU = CAN_FIRE_RL_doFCVT_S_WU ;
// rule RL_doFCVT_L_S
assign CAN_FIRE_RL_doFCVT_L_S =
requestR[214] && stateR == 2'd1 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h60 &&
requestR[199:195] == 5'd2 ;
assign WILL_FIRE_RL_doFCVT_L_S = CAN_FIRE_RL_doFCVT_L_S ;
// rule RL_doFCVT_LU_S
assign CAN_FIRE_RL_doFCVT_LU_S =
requestR[214] && stateR == 2'd1 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h60 &&
requestR[199:195] == 5'd3 ;
assign WILL_FIRE_RL_doFCVT_LU_S = CAN_FIRE_RL_doFCVT_LU_S ;
// rule RL_doFCVT_W_S
assign CAN_FIRE_RL_doFCVT_W_S =
requestR[214] && stateR == 2'd1 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h60 &&
requestR[199:195] == 5'd0 ;
assign WILL_FIRE_RL_doFCVT_W_S = CAN_FIRE_RL_doFCVT_W_S ;
// rule RL_doFCVT_WU_S
assign CAN_FIRE_RL_doFCVT_WU_S =
requestR[214] && stateR == 2'd1 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h60 &&
requestR[199:195] == 5'd1 ;
assign WILL_FIRE_RL_doFCVT_WU_S = CAN_FIRE_RL_doFCVT_WU_S ;
// rule RL_doFMIN_S
assign CAN_FIRE_RL_doFMIN_S =
requestR[214] && stateR == 2'd1 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h14 &&
requestR[194:192] == 3'h0 ;
assign WILL_FIRE_RL_doFMIN_S = CAN_FIRE_RL_doFMIN_S ;
// rule RL_doFMAX_S
assign CAN_FIRE_RL_doFMAX_S =
requestR[214] && stateR == 2'd1 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h14 &&
requestR[194:192] == 3'h1 ;
assign WILL_FIRE_RL_doFMAX_S = CAN_FIRE_RL_doFMAX_S ;
// rule RL_doFMV_W_X
assign CAN_FIRE_RL_doFMV_W_X =
requestR[214] && stateR == 2'd1 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h78 &&
requestR[194:192] == 3'h0 ;
assign WILL_FIRE_RL_doFMV_W_X = CAN_FIRE_RL_doFMV_W_X ;
// rule RL_doFMV_X_W
assign CAN_FIRE_RL_doFMV_X_W =
requestR[214] && stateR == 2'd1 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h70 &&
requestR[194:192] == 3'h0 ;
assign WILL_FIRE_RL_doFMV_X_W = CAN_FIRE_RL_doFMV_X_W ;
// rule RL_doFEQ_S
assign CAN_FIRE_RL_doFEQ_S =
requestR[214] && stateR == 2'd1 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h50 &&
requestR[194:192] == 3'h2 ;
assign WILL_FIRE_RL_doFEQ_S = CAN_FIRE_RL_doFEQ_S ;
// rule RL_doFLT_S
assign CAN_FIRE_RL_doFLT_S =
requestR[214] && stateR == 2'd1 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h50 &&
requestR[194:192] == 3'h1 ;
assign WILL_FIRE_RL_doFLT_S = CAN_FIRE_RL_doFLT_S ;
// rule RL_doFLE_S
assign CAN_FIRE_RL_doFLE_S =
requestR[214] && stateR == 2'd1 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h50 &&
requestR[194:192] == 3'h0 ;
assign WILL_FIRE_RL_doFLE_S = CAN_FIRE_RL_doFLE_S ;
// rule RL_doFCLASS_S
assign CAN_FIRE_RL_doFCLASS_S =
requestR[214] && stateR == 2'd1 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h70 &&
requestR[194:192] == 3'h1 ;
assign WILL_FIRE_RL_doFCLASS_S = CAN_FIRE_RL_doFCLASS_S ;
// rule RL_doFADD_D
assign CAN_FIRE_RL_doFADD_D =
fpu$RDY_server_core_request_put && requestR[214] &&
stateR == 2'd1 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h01 ;
assign WILL_FIRE_RL_doFADD_D = CAN_FIRE_RL_doFADD_D ;
// rule RL_doFSUB_D
assign CAN_FIRE_RL_doFSUB_D =
fpu$RDY_server_core_request_put && requestR[214] &&
stateR == 2'd1 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h05 ;
assign WILL_FIRE_RL_doFSUB_D = CAN_FIRE_RL_doFSUB_D ;
// rule RL_doFMUL_D
assign CAN_FIRE_RL_doFMUL_D =
fpu$RDY_server_core_request_put && requestR[214] &&
stateR == 2'd1 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h09 ;
assign WILL_FIRE_RL_doFMUL_D = CAN_FIRE_RL_doFMUL_D ;
// rule RL_doFMADD_D
assign CAN_FIRE_RL_doFMADD_D =
fpu$RDY_server_core_request_put && requestR[214] &&
stateR == 2'd1 &&
requestR[213:207] == 7'b1000011 &&
requestR_BITS_206_TO_200__q177[1:0] == 2'd1 ;
assign WILL_FIRE_RL_doFMADD_D = CAN_FIRE_RL_doFMADD_D ;
// rule RL_doFMSUB_D
assign CAN_FIRE_RL_doFMSUB_D =
fpu$RDY_server_core_request_put && requestR[214] &&
stateR == 2'd1 &&
requestR[213:207] == 7'b1000111 &&
requestR_BITS_206_TO_200__q177[1:0] == 2'd1 ;
assign WILL_FIRE_RL_doFMSUB_D = CAN_FIRE_RL_doFMSUB_D ;
// rule RL_doFNMADD_D
assign CAN_FIRE_RL_doFNMADD_D =
fpu$RDY_server_core_request_put && requestR[214] &&
stateR == 2'd1 &&
requestR[213:207] == 7'b1001111 &&
requestR_BITS_206_TO_200__q177[1:0] == 2'd1 ;
assign WILL_FIRE_RL_doFNMADD_D = CAN_FIRE_RL_doFNMADD_D ;
// rule RL_doFNMSUB_D
assign CAN_FIRE_RL_doFNMSUB_D =
fpu$RDY_server_core_request_put && requestR[214] &&
stateR == 2'd1 &&
requestR[213:207] == 7'b1001011 &&
requestR_BITS_206_TO_200__q177[1:0] == 2'd1 ;
assign WILL_FIRE_RL_doFNMSUB_D = CAN_FIRE_RL_doFNMSUB_D ;
// rule RL_doFDIV_D
assign CAN_FIRE_RL_doFDIV_D =
fpu$RDY_server_core_request_put && requestR[214] &&
stateR == 2'd1 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h0D ;
assign WILL_FIRE_RL_doFDIV_D = CAN_FIRE_RL_doFDIV_D ;
// rule RL_doFSQRT_D
assign CAN_FIRE_RL_doFSQRT_D =
fpu$RDY_server_core_request_put && requestR[214] &&
stateR == 2'd1 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h2D ;
assign WILL_FIRE_RL_doFSQRT_D = CAN_FIRE_RL_doFSQRT_D ;
// rule RL_doFSGNJ_D
assign CAN_FIRE_RL_doFSGNJ_D =
requestR[214] && stateR == 2'd1 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h11 &&
requestR[194:192] == 3'h0 ;
assign WILL_FIRE_RL_doFSGNJ_D = CAN_FIRE_RL_doFSGNJ_D ;
// rule RL_doFSGNJN_D
assign CAN_FIRE_RL_doFSGNJN_D =
requestR[214] && stateR == 2'd1 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h11 &&
requestR[194:192] == 3'h1 ;
assign WILL_FIRE_RL_doFSGNJN_D = CAN_FIRE_RL_doFSGNJN_D ;
// rule RL_doFSGNJX_D
assign CAN_FIRE_RL_doFSGNJX_D =
requestR[214] && stateR == 2'd1 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h11 &&
requestR[194:192] == 3'h2 ;
assign WILL_FIRE_RL_doFSGNJX_D = CAN_FIRE_RL_doFSGNJX_D ;
// rule RL_doFCVT_D_W
assign CAN_FIRE_RL_doFCVT_D_W =
requestR[214] && stateR == 2'd1 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h69 &&
requestR[199:195] == 5'd0 ;
assign WILL_FIRE_RL_doFCVT_D_W = CAN_FIRE_RL_doFCVT_D_W ;
// rule RL_doFCVT_D_WU
assign CAN_FIRE_RL_doFCVT_D_WU =
requestR[214] && stateR == 2'd1 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h69 &&
requestR[199:195] == 5'd1 ;
assign WILL_FIRE_RL_doFCVT_D_WU = CAN_FIRE_RL_doFCVT_D_WU ;
// rule RL_doFCVT_W_D
assign CAN_FIRE_RL_doFCVT_W_D =
requestR[214] && stateR == 2'd1 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h61 &&
requestR[199:195] == 5'd0 ;
assign WILL_FIRE_RL_doFCVT_W_D = CAN_FIRE_RL_doFCVT_W_D ;
// rule RL_doFCVT_WU_D
assign CAN_FIRE_RL_doFCVT_WU_D =
requestR[214] && stateR == 2'd1 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h61 &&
requestR[199:195] == 5'd1 ;
assign WILL_FIRE_RL_doFCVT_WU_D = CAN_FIRE_RL_doFCVT_WU_D ;
// rule RL_doFCVT_D_L
assign CAN_FIRE_RL_doFCVT_D_L =
requestR[214] && stateR == 2'd1 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h69 &&
requestR[199:195] == 5'd2 ;
assign WILL_FIRE_RL_doFCVT_D_L = CAN_FIRE_RL_doFCVT_D_L ;
// rule RL_doFCVT_D_LU
assign CAN_FIRE_RL_doFCVT_D_LU =
requestR[214] && stateR == 2'd1 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h69 &&
requestR[199:195] == 5'd3 ;
assign WILL_FIRE_RL_doFCVT_D_LU = CAN_FIRE_RL_doFCVT_D_LU ;
// rule RL_doFCVT_L_D
assign CAN_FIRE_RL_doFCVT_L_D =
requestR[214] && stateR == 2'd1 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h61 &&
requestR[199:195] == 5'd2 ;
assign WILL_FIRE_RL_doFCVT_L_D = CAN_FIRE_RL_doFCVT_L_D ;
// rule RL_doFCVT_LU_D
assign CAN_FIRE_RL_doFCVT_LU_D =
requestR[214] && stateR == 2'd1 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h61 &&
requestR[199:195] == 5'd3 ;
assign WILL_FIRE_RL_doFCVT_LU_D = CAN_FIRE_RL_doFCVT_LU_D ;
// rule RL_doFCVT_S_D
assign CAN_FIRE_RL_doFCVT_S_D =
requestR[214] && stateR == 2'd1 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h20 &&
requestR[199:195] == 5'd1 ;
assign WILL_FIRE_RL_doFCVT_S_D = CAN_FIRE_RL_doFCVT_S_D ;
// rule RL_doFCVT_D_S
assign CAN_FIRE_RL_doFCVT_D_S =
requestR[214] && stateR == 2'd1 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h21 &&
requestR[199:195] == 5'd0 ;
assign WILL_FIRE_RL_doFCVT_D_S = CAN_FIRE_RL_doFCVT_D_S ;
// rule RL_doFMIN_D
assign CAN_FIRE_RL_doFMIN_D =
requestR[214] && stateR == 2'd1 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h15 &&
requestR[194:192] == 3'h0 ;
assign WILL_FIRE_RL_doFMIN_D = CAN_FIRE_RL_doFMIN_D ;
// rule RL_doFMAX_D
assign CAN_FIRE_RL_doFMAX_D =
requestR[214] && stateR == 2'd1 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h15 &&
requestR[194:192] == 3'h1 ;
assign WILL_FIRE_RL_doFMAX_D = CAN_FIRE_RL_doFMAX_D ;
// rule RL_doFEQ_D
assign CAN_FIRE_RL_doFEQ_D =
requestR[214] && stateR == 2'd1 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h51 &&
requestR[194:192] == 3'h2 ;
assign WILL_FIRE_RL_doFEQ_D = CAN_FIRE_RL_doFEQ_D ;
// rule RL_doFLT_D
assign CAN_FIRE_RL_doFLT_D =
requestR[214] && stateR == 2'd1 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h51 &&
requestR[194:192] == 3'h1 ;
assign WILL_FIRE_RL_doFLT_D = CAN_FIRE_RL_doFLT_D ;
// rule RL_doFLE_D
assign CAN_FIRE_RL_doFLE_D =
requestR[214] && stateR == 2'd1 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h51 &&
requestR[194:192] == 3'h0 ;
assign WILL_FIRE_RL_doFLE_D = CAN_FIRE_RL_doFLE_D ;
// rule RL_doFMV_D_X
assign CAN_FIRE_RL_doFMV_D_X =
requestR[214] && stateR == 2'd1 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h79 &&
requestR[194:192] == 3'h0 ;
assign WILL_FIRE_RL_doFMV_D_X = CAN_FIRE_RL_doFMV_D_X ;
// rule RL_doFMV_X_D
assign CAN_FIRE_RL_doFMV_X_D =
requestR[214] && stateR == 2'd1 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h71 &&
requestR[194:192] == 3'h0 ;
assign WILL_FIRE_RL_doFMV_X_D = CAN_FIRE_RL_doFMV_X_D ;
// rule RL_doFCLASS_D
assign CAN_FIRE_RL_doFCLASS_D =
requestR[214] && stateR == 2'd1 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h71 &&
requestR[194:192] == 3'h1 ;
assign WILL_FIRE_RL_doFCLASS_D = CAN_FIRE_RL_doFCLASS_D ;
// rule RL_rl_get_fpu_result
assign CAN_FIRE_RL_rl_get_fpu_result = MUX_dw_result$wset_1__SEL_1 ;
assign WILL_FIRE_RL_rl_get_fpu_result = MUX_dw_result$wset_1__SEL_1 ;
// rule RL_rl_drive_fpu_result
assign CAN_FIRE_RL_rl_drive_fpu_result = stateR == 2'd3 ;
assign WILL_FIRE_RL_rl_drive_fpu_result = stateR == 2'd3 ;
// rule RL_rl_reset_begin
assign CAN_FIRE_RL_rl_reset_begin =
fpu$RDY_server_reset_request_put && resetReqsF$EMPTY_N ;
assign WILL_FIRE_RL_rl_reset_begin = CAN_FIRE_RL_rl_reset_begin ;
// inputs to muxes for submodule ports
assign MUX_dw_result$wset_1__SEL_1 =
fpu$RDY_server_core_response_get && stateR == 2'd2 ;
assign MUX_dw_result$wset_1__VAL_1 =
{ x__h230460, fpu$server_core_response_get[4:0] } ;
assign MUX_fpu$server_core_request_put_1__VAL_1 =
{ 33'h1AAAAAAAA,
requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31],
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d37,
33'h1AAAAAAAA,
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d48,
65'h0AAAAAAAAAAAAAAAA,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d61,
4'd0 } ;
assign MUX_fpu$server_core_request_put_1__VAL_2 =
{ 33'h1AAAAAAAA,
requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31],
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d37,
33'h1AAAAAAAA,
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d48,
65'h0AAAAAAAAAAAAAAAA,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d61,
4'd1 } ;
assign MUX_fpu$server_core_request_put_1__VAL_3 =
{ 33'h1AAAAAAAA,
requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31],
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d37,
33'h1AAAAAAAA,
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d48,
65'h0AAAAAAAAAAAAAAAA,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d61,
4'd2 } ;
assign MUX_fpu$server_core_request_put_1__VAL_4 =
{ 33'h1AAAAAAAA,
requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31],
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d37,
33'h1AAAAAAAA,
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d48,
_1_CONCAT_DONTCARE_CONCAT_IF_requestR_3_BIT_214_ETC___d97,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d61,
4'd5 } ;
assign MUX_fpu$server_core_request_put_1__VAL_5 =
{ 33'h1AAAAAAAA,
requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31],
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d37,
33'h1AAAAAAAA,
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d48,
_1_CONCAT_DONTCARE_CONCAT_IF_requestR_3_BIT_214_ETC___d97,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d61,
4'd6 } ;
assign MUX_fpu$server_core_request_put_1__VAL_6 =
{ 33'h1AAAAAAAA,
requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31],
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d37,
33'h1AAAAAAAA,
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d48,
_1_CONCAT_DONTCARE_CONCAT_IF_requestR_3_BIT_214_ETC___d97,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d61,
4'd7 } ;
assign MUX_fpu$server_core_request_put_1__VAL_7 =
{ 33'h1AAAAAAAA,
requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31],
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d37,
33'h1AAAAAAAA,
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d48,
_1_CONCAT_DONTCARE_CONCAT_IF_requestR_3_BIT_214_ETC___d97,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d61,
4'd8 } ;
assign MUX_fpu$server_core_request_put_1__VAL_8 =
{ 33'h1AAAAAAAA,
requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31],
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d37,
33'h1AAAAAAAA,
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d48,
65'h0AAAAAAAAAAAAAAAA,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d61,
4'd3 } ;
assign MUX_fpu$server_core_request_put_1__VAL_9 =
{ 33'h1AAAAAAAA,
requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31],
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d37,
130'h15555555555555554AAAAAAAAAAAAAAAA,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d61,
4'd4 } ;
assign MUX_fpu$server_core_request_put_1__VAL_10 =
{ 1'd0,
requestR[191:128],
1'd0,
requestR[127:64],
65'h0AAAAAAAAAAAAAAAA,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d61,
4'd0 } ;
assign MUX_fpu$server_core_request_put_1__VAL_11 =
{ 1'd0,
requestR[191:128],
1'd0,
requestR[127:64],
65'h0AAAAAAAAAAAAAAAA,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d61,
4'd1 } ;
assign MUX_fpu$server_core_request_put_1__VAL_12 =
{ 1'd0,
requestR[191:128],
1'd0,
requestR[127:64],
65'h0AAAAAAAAAAAAAAAA,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d61,
4'd2 } ;
assign MUX_fpu$server_core_request_put_1__VAL_13 =
{ 1'd0,
requestR[191:128],
1'd0,
requestR[127:64],
1'd0,
requestR[63:0],
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d61,
4'd5 } ;
assign MUX_fpu$server_core_request_put_1__VAL_14 =
{ 1'd0,
requestR[191:128],
1'd0,
requestR[127:64],
1'd0,
requestR[63:0],
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d61,
4'd6 } ;
assign MUX_fpu$server_core_request_put_1__VAL_15 =
{ 1'd0,
requestR[191:128],
1'd0,
requestR[127:64],
1'd0,
requestR[63:0],
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d61,
4'd7 } ;
assign MUX_fpu$server_core_request_put_1__VAL_16 =
{ 1'd0,
requestR[191:128],
1'd0,
requestR[127:64],
1'd0,
requestR[63:0],
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d61,
4'd8 } ;
assign MUX_fpu$server_core_request_put_1__VAL_17 =
{ 1'd0,
requestR[191:128],
1'd0,
requestR[127:64],
65'h0AAAAAAAAAAAAAAAA,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d61,
4'd3 } ;
assign MUX_fpu$server_core_request_put_1__VAL_18 =
{ 1'd0,
requestR[191:128],
130'h15555555555555554AAAAAAAAAAAAAAAA,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d61,
4'd4 } ;
assign MUX_requestR$write_1__VAL_2 =
{ 1'd1,
req_opcode,
req_f7,
req_rs2,
req_rm,
req_v1,
req_v2,
req_v3 } ;
assign MUX_resultR$write_1__VAL_3 =
{ 1'd1, x__h230460, fpu$server_core_response_get[4:0] } ;
assign MUX_resultR$write_1__VAL_4 = { 1'd1, x__h229846, 5'd0 } ;
assign MUX_resultR$write_1__VAL_6 = { 1'd1, requestR[191:128], 5'd0 } ;
assign MUX_resultR$write_1__VAL_7 = { 1'd1, x__h227602, x__h227382 } ;
assign MUX_resultR$write_1__VAL_8 = { 1'd1, x__h225685, x__h227382 } ;
assign MUX_resultR$write_1__VAL_9 = { 1'd1, x__h222950, x__h217430 } ;
assign MUX_resultR$write_1__VAL_10 = { 1'd1, x__h218468, x__h217430 } ;
assign MUX_resultR$write_1__VAL_11 = { 1'd1, x__h213882, x__h217430 } ;
assign MUX_resultR$write_1__VAL_12 = { 1'd1, x__h167888, x__h212920 } ;
assign MUX_resultR$write_1__VAL_13 = { 1'd1, x__h113022, x__h166866 } ;
assign MUX_resultR$write_1__VAL_14 = { 1'd1, x__h112240, x__h112739 } ;
assign MUX_resultR$write_1__VAL_15 = { 1'd1, x__h110179, x__h111943 } ;
assign MUX_resultR$write_1__VAL_16 = { 1'd1, x__h97683, x__h109855 } ;
assign MUX_resultR$write_1__VAL_17 = { 1'd1, x__h84681, x__h97358 } ;
assign MUX_resultR$write_1__VAL_18 = { 1'd1, x__h83895, x__h84397 } ;
assign MUX_resultR$write_1__VAL_19 = { 1'd1, x__h82279, x__h83598 } ;
assign MUX_resultR$write_1__VAL_20 = { 1'd1, x__h71361, x__h81955 } ;
assign MUX_resultR$write_1__VAL_21 = { 1'd1, x__h60162, x__h71036 } ;
assign MUX_resultR$write_1__VAL_22 = { 1'd1, x__h59992, 5'd0 } ;
assign MUX_resultR$write_1__VAL_23 = { 1'd1, x__h59829, 5'd0 } ;
assign MUX_resultR$write_1__VAL_24 = { 1'd1, x__h59668, 5'd0 } ;
assign MUX_resultR$write_1__VAL_25 = { 1'd1, x__h57514, 5'd0 } ;
assign MUX_resultR$write_1__VAL_26 = { 1'd1, x__h56389, x__h56169 } ;
assign MUX_resultR$write_1__VAL_27 = { 1'd1, x__h55280, x__h56169 } ;
assign MUX_resultR$write_1__VAL_28 = { 1'd1, x__h53757, x__h50220 } ;
assign MUX_resultR$write_1__VAL_29 = { 1'd1, x__h53579, 5'd0 } ;
assign MUX_resultR$write_1__VAL_30 = { 1'd1, x__h53419, 5'd0 } ;
assign MUX_resultR$write_1__VAL_31 = { 1'd1, x__h50854, x__h50220 } ;
assign MUX_resultR$write_1__VAL_32 = { 1'd1, x__h48180, x__h50220 } ;
assign MUX_resultR$write_1__VAL_33 = { 1'd1, x__h47391, x__h47893 } ;
assign MUX_resultR$write_1__VAL_34 = { 1'd1, x__h45775, x__h47094 } ;
assign MUX_resultR$write_1__VAL_35 = { 1'd1, x__h44993, x__h45492 } ;
assign MUX_resultR$write_1__VAL_36 = { 1'd1, x__h42915, x__h44696 } ;
assign MUX_resultR$write_1__VAL_37 = { 1'd1, x__h36028, x__h42591 } ;
assign MUX_resultR$write_1__VAL_38 = { 1'd1, x__h28828, x__h35703 } ;
assign MUX_resultR$write_1__VAL_39 = { 1'd1, x__h16727, x__h28503 } ;
assign MUX_resultR$write_1__VAL_40 = { 1'd1, res__h3932, fcsr__h3933 } ;
assign MUX_resultR$write_1__VAL_41 = { 1'd1, x__h3778, 5'd0 } ;
assign MUX_resultR$write_1__VAL_42 = { 1'd1, x__h3605, 5'd0 } ;
assign MUX_resultR$write_1__VAL_43 = { 1'd1, x__h3429, 5'd0 } ;
// inlined wires
assign dw_valid$wget = !WILL_FIRE_RL_rl_drive_fpu_result || resultR[69] ;
assign dw_valid$whas =
WILL_FIRE_RL_rl_drive_fpu_result ||
WILL_FIRE_RL_rl_get_fpu_result ;
assign dw_result$wget =
WILL_FIRE_RL_rl_get_fpu_result ?
MUX_dw_result$wset_1__VAL_1 :
resultR[68:0] ;
// register requestR
assign requestR$D_IN =
WILL_FIRE_RL_rl_reset_begin ?
215'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA :
MUX_requestR$write_1__VAL_2 ;
assign requestR$EN = WILL_FIRE_RL_rl_reset_begin || EN_req ;
// register resultR
always@(WILL_FIRE_RL_rl_reset_begin or
EN_req or
WILL_FIRE_RL_rl_get_fpu_result or
MUX_resultR$write_1__VAL_3 or
WILL_FIRE_RL_doFCLASS_D or
MUX_resultR$write_1__VAL_4 or
WILL_FIRE_RL_doFMV_X_D or
MUX_resultR$write_1__VAL_6 or
WILL_FIRE_RL_doFMV_D_X or
WILL_FIRE_RL_doFLE_D or
MUX_resultR$write_1__VAL_7 or
WILL_FIRE_RL_doFLT_D or
MUX_resultR$write_1__VAL_8 or
WILL_FIRE_RL_doFEQ_D or
MUX_resultR$write_1__VAL_9 or
WILL_FIRE_RL_doFMAX_D or
MUX_resultR$write_1__VAL_10 or
WILL_FIRE_RL_doFMIN_D or
MUX_resultR$write_1__VAL_11 or
WILL_FIRE_RL_doFCVT_D_S or
MUX_resultR$write_1__VAL_12 or
WILL_FIRE_RL_doFCVT_S_D or
MUX_resultR$write_1__VAL_13 or
WILL_FIRE_RL_doFCVT_LU_D or
MUX_resultR$write_1__VAL_14 or
WILL_FIRE_RL_doFCVT_L_D or
MUX_resultR$write_1__VAL_15 or
WILL_FIRE_RL_doFCVT_D_LU or
MUX_resultR$write_1__VAL_16 or
WILL_FIRE_RL_doFCVT_D_L or
MUX_resultR$write_1__VAL_17 or
WILL_FIRE_RL_doFCVT_WU_D or
MUX_resultR$write_1__VAL_18 or
WILL_FIRE_RL_doFCVT_W_D or
MUX_resultR$write_1__VAL_19 or
WILL_FIRE_RL_doFCVT_D_WU or
MUX_resultR$write_1__VAL_20 or
WILL_FIRE_RL_doFCVT_D_W or
MUX_resultR$write_1__VAL_21 or
WILL_FIRE_RL_doFSGNJX_D or
MUX_resultR$write_1__VAL_22 or
WILL_FIRE_RL_doFSGNJN_D or
MUX_resultR$write_1__VAL_23 or
WILL_FIRE_RL_doFSGNJ_D or
MUX_resultR$write_1__VAL_24 or
WILL_FIRE_RL_doFCLASS_S or
MUX_resultR$write_1__VAL_25 or
WILL_FIRE_RL_doFLE_S or
MUX_resultR$write_1__VAL_26 or
WILL_FIRE_RL_doFLT_S or
MUX_resultR$write_1__VAL_27 or
WILL_FIRE_RL_doFEQ_S or
MUX_resultR$write_1__VAL_28 or
WILL_FIRE_RL_doFMV_X_W or
MUX_resultR$write_1__VAL_29 or
WILL_FIRE_RL_doFMV_W_X or
MUX_resultR$write_1__VAL_30 or
WILL_FIRE_RL_doFMAX_S or
MUX_resultR$write_1__VAL_31 or
WILL_FIRE_RL_doFMIN_S or
MUX_resultR$write_1__VAL_32 or
WILL_FIRE_RL_doFCVT_WU_S or
MUX_resultR$write_1__VAL_33 or
WILL_FIRE_RL_doFCVT_W_S or
MUX_resultR$write_1__VAL_34 or
WILL_FIRE_RL_doFCVT_LU_S or
MUX_resultR$write_1__VAL_35 or
WILL_FIRE_RL_doFCVT_L_S or
MUX_resultR$write_1__VAL_36 or
WILL_FIRE_RL_doFCVT_S_WU or
MUX_resultR$write_1__VAL_37 or
WILL_FIRE_RL_doFCVT_S_W or
MUX_resultR$write_1__VAL_38 or
WILL_FIRE_RL_doFCVT_S_LU or
MUX_resultR$write_1__VAL_39 or
WILL_FIRE_RL_doFCVT_S_L or
MUX_resultR$write_1__VAL_40 or
WILL_FIRE_RL_doFSGNJX_S or
MUX_resultR$write_1__VAL_41 or
WILL_FIRE_RL_doFSGNJN_S or
MUX_resultR$write_1__VAL_42 or
WILL_FIRE_RL_doFSGNJ_S or MUX_resultR$write_1__VAL_43)
case (1'b1)
WILL_FIRE_RL_rl_reset_begin || EN_req:
resultR$D_IN = 70'h0AAAAAAAAAAAAAAAAA;
WILL_FIRE_RL_rl_get_fpu_result: resultR$D_IN = MUX_resultR$write_1__VAL_3;
WILL_FIRE_RL_doFCLASS_D: resultR$D_IN = MUX_resultR$write_1__VAL_4;
WILL_FIRE_RL_doFMV_X_D: resultR$D_IN = MUX_resultR$write_1__VAL_6;
WILL_FIRE_RL_doFMV_D_X: resultR$D_IN = MUX_resultR$write_1__VAL_6;
WILL_FIRE_RL_doFLE_D: resultR$D_IN = MUX_resultR$write_1__VAL_7;
WILL_FIRE_RL_doFLT_D: resultR$D_IN = MUX_resultR$write_1__VAL_8;
WILL_FIRE_RL_doFEQ_D: resultR$D_IN = MUX_resultR$write_1__VAL_9;
WILL_FIRE_RL_doFMAX_D: resultR$D_IN = MUX_resultR$write_1__VAL_10;
WILL_FIRE_RL_doFMIN_D: resultR$D_IN = MUX_resultR$write_1__VAL_11;
WILL_FIRE_RL_doFCVT_D_S: resultR$D_IN = MUX_resultR$write_1__VAL_12;
WILL_FIRE_RL_doFCVT_S_D: resultR$D_IN = MUX_resultR$write_1__VAL_13;
WILL_FIRE_RL_doFCVT_LU_D: resultR$D_IN = MUX_resultR$write_1__VAL_14;
WILL_FIRE_RL_doFCVT_L_D: resultR$D_IN = MUX_resultR$write_1__VAL_15;
WILL_FIRE_RL_doFCVT_D_LU: resultR$D_IN = MUX_resultR$write_1__VAL_16;
WILL_FIRE_RL_doFCVT_D_L: resultR$D_IN = MUX_resultR$write_1__VAL_17;
WILL_FIRE_RL_doFCVT_WU_D: resultR$D_IN = MUX_resultR$write_1__VAL_18;
WILL_FIRE_RL_doFCVT_W_D: resultR$D_IN = MUX_resultR$write_1__VAL_19;
WILL_FIRE_RL_doFCVT_D_WU: resultR$D_IN = MUX_resultR$write_1__VAL_20;
WILL_FIRE_RL_doFCVT_D_W: resultR$D_IN = MUX_resultR$write_1__VAL_21;
WILL_FIRE_RL_doFSGNJX_D: resultR$D_IN = MUX_resultR$write_1__VAL_22;
WILL_FIRE_RL_doFSGNJN_D: resultR$D_IN = MUX_resultR$write_1__VAL_23;
WILL_FIRE_RL_doFSGNJ_D: resultR$D_IN = MUX_resultR$write_1__VAL_24;
WILL_FIRE_RL_doFCLASS_S: resultR$D_IN = MUX_resultR$write_1__VAL_25;
WILL_FIRE_RL_doFLE_S: resultR$D_IN = MUX_resultR$write_1__VAL_26;
WILL_FIRE_RL_doFLT_S: resultR$D_IN = MUX_resultR$write_1__VAL_27;
WILL_FIRE_RL_doFEQ_S: resultR$D_IN = MUX_resultR$write_1__VAL_28;
WILL_FIRE_RL_doFMV_X_W: resultR$D_IN = MUX_resultR$write_1__VAL_29;
WILL_FIRE_RL_doFMV_W_X: resultR$D_IN = MUX_resultR$write_1__VAL_30;
WILL_FIRE_RL_doFMAX_S: resultR$D_IN = MUX_resultR$write_1__VAL_31;
WILL_FIRE_RL_doFMIN_S: resultR$D_IN = MUX_resultR$write_1__VAL_32;
WILL_FIRE_RL_doFCVT_WU_S: resultR$D_IN = MUX_resultR$write_1__VAL_33;
WILL_FIRE_RL_doFCVT_W_S: resultR$D_IN = MUX_resultR$write_1__VAL_34;
WILL_FIRE_RL_doFCVT_LU_S: resultR$D_IN = MUX_resultR$write_1__VAL_35;
WILL_FIRE_RL_doFCVT_L_S: resultR$D_IN = MUX_resultR$write_1__VAL_36;
WILL_FIRE_RL_doFCVT_S_WU: resultR$D_IN = MUX_resultR$write_1__VAL_37;
WILL_FIRE_RL_doFCVT_S_W: resultR$D_IN = MUX_resultR$write_1__VAL_38;
WILL_FIRE_RL_doFCVT_S_LU: resultR$D_IN = MUX_resultR$write_1__VAL_39;
WILL_FIRE_RL_doFCVT_S_L: resultR$D_IN = MUX_resultR$write_1__VAL_40;
WILL_FIRE_RL_doFSGNJX_S: resultR$D_IN = MUX_resultR$write_1__VAL_41;
WILL_FIRE_RL_doFSGNJN_S: resultR$D_IN = MUX_resultR$write_1__VAL_42;
WILL_FIRE_RL_doFSGNJ_S: resultR$D_IN = MUX_resultR$write_1__VAL_43;
default: resultR$D_IN = 70'h2AAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
assign resultR$EN =
WILL_FIRE_RL_rl_reset_begin || EN_req ||
WILL_FIRE_RL_doFMV_X_D ||
WILL_FIRE_RL_doFMV_D_X ||
WILL_FIRE_RL_doFSGNJ_S ||
WILL_FIRE_RL_doFSGNJN_S ||
WILL_FIRE_RL_doFSGNJX_S ||
WILL_FIRE_RL_doFCVT_S_L ||
WILL_FIRE_RL_doFCVT_S_LU ||
WILL_FIRE_RL_doFCVT_S_W ||
WILL_FIRE_RL_doFCVT_S_WU ||
WILL_FIRE_RL_doFCVT_L_S ||
WILL_FIRE_RL_doFCVT_LU_S ||
WILL_FIRE_RL_doFCVT_W_S ||
WILL_FIRE_RL_doFCVT_WU_S ||
WILL_FIRE_RL_doFMIN_S ||
WILL_FIRE_RL_doFMAX_S ||
WILL_FIRE_RL_doFMV_W_X ||
WILL_FIRE_RL_doFMV_X_W ||
WILL_FIRE_RL_doFEQ_S ||
WILL_FIRE_RL_doFLT_S ||
WILL_FIRE_RL_doFLE_S ||
WILL_FIRE_RL_doFCLASS_S ||
WILL_FIRE_RL_doFSGNJ_D ||
WILL_FIRE_RL_doFSGNJN_D ||
WILL_FIRE_RL_doFSGNJX_D ||
WILL_FIRE_RL_doFCVT_D_W ||
WILL_FIRE_RL_doFCVT_D_WU ||
WILL_FIRE_RL_doFCVT_W_D ||
WILL_FIRE_RL_doFCVT_WU_D ||
WILL_FIRE_RL_doFCVT_D_L ||
WILL_FIRE_RL_doFCVT_D_LU ||
WILL_FIRE_RL_doFCVT_L_D ||
WILL_FIRE_RL_doFCVT_LU_D ||
WILL_FIRE_RL_doFCVT_S_D ||
WILL_FIRE_RL_doFCVT_D_S ||
WILL_FIRE_RL_doFMIN_D ||
WILL_FIRE_RL_doFMAX_D ||
WILL_FIRE_RL_doFEQ_D ||
WILL_FIRE_RL_doFLT_D ||
WILL_FIRE_RL_doFLE_D ||
WILL_FIRE_RL_doFCLASS_D ||
WILL_FIRE_RL_rl_get_fpu_result ;
// register stateR
always@(WILL_FIRE_RL_rl_reset_begin or
EN_req or
WILL_FIRE_RL_rl_get_fpu_result or
WILL_FIRE_RL_doFCLASS_D or
WILL_FIRE_RL_doFMV_X_D or
WILL_FIRE_RL_doFMV_D_X or
WILL_FIRE_RL_doFLE_D or
WILL_FIRE_RL_doFLT_D or
WILL_FIRE_RL_doFEQ_D or
WILL_FIRE_RL_doFMAX_D or
WILL_FIRE_RL_doFMIN_D or
WILL_FIRE_RL_doFCVT_D_S or
WILL_FIRE_RL_doFCVT_S_D or
WILL_FIRE_RL_doFCVT_LU_D or
WILL_FIRE_RL_doFCVT_L_D or
WILL_FIRE_RL_doFCVT_D_LU or
WILL_FIRE_RL_doFCVT_D_L or
WILL_FIRE_RL_doFCVT_WU_D or
WILL_FIRE_RL_doFCVT_W_D or
WILL_FIRE_RL_doFCVT_D_WU or
WILL_FIRE_RL_doFCVT_D_W or
WILL_FIRE_RL_doFSGNJX_D or
WILL_FIRE_RL_doFSGNJN_D or
WILL_FIRE_RL_doFSGNJ_D or
WILL_FIRE_RL_doFSQRT_D or
WILL_FIRE_RL_doFDIV_D or
WILL_FIRE_RL_doFNMSUB_D or
WILL_FIRE_RL_doFNMADD_D or
WILL_FIRE_RL_doFMSUB_D or
WILL_FIRE_RL_doFMADD_D or
WILL_FIRE_RL_doFMUL_D or
WILL_FIRE_RL_doFSUB_D or
WILL_FIRE_RL_doFADD_D or
WILL_FIRE_RL_doFCLASS_S or
WILL_FIRE_RL_doFLE_S or
WILL_FIRE_RL_doFLT_S or
WILL_FIRE_RL_doFEQ_S or
WILL_FIRE_RL_doFMV_X_W or
WILL_FIRE_RL_doFMV_W_X or
WILL_FIRE_RL_doFMAX_S or
WILL_FIRE_RL_doFMIN_S or
WILL_FIRE_RL_doFCVT_WU_S or
WILL_FIRE_RL_doFCVT_W_S or
WILL_FIRE_RL_doFCVT_LU_S or
WILL_FIRE_RL_doFCVT_L_S or
WILL_FIRE_RL_doFCVT_S_WU or
WILL_FIRE_RL_doFCVT_S_W or
WILL_FIRE_RL_doFCVT_S_LU or
WILL_FIRE_RL_doFCVT_S_L or
WILL_FIRE_RL_doFSGNJX_S or
WILL_FIRE_RL_doFSGNJN_S or
WILL_FIRE_RL_doFSGNJ_S or
WILL_FIRE_RL_doFSQRT_S or
WILL_FIRE_RL_doFDIV_S or
WILL_FIRE_RL_doFNMSUB_S or
WILL_FIRE_RL_doFNMADD_S or
WILL_FIRE_RL_doFMSUB_S or
WILL_FIRE_RL_doFMADD_S or
WILL_FIRE_RL_doFMUL_S or
WILL_FIRE_RL_doFSUB_S or
WILL_FIRE_RL_doFADD_S or WILL_FIRE_RL_rl_reset_end)
case (1'b1)
WILL_FIRE_RL_rl_reset_begin: stateR$D_IN = 2'd0;
EN_req: stateR$D_IN = 2'd1;
WILL_FIRE_RL_rl_get_fpu_result || WILL_FIRE_RL_doFCLASS_D ||
WILL_FIRE_RL_doFMV_X_D ||
WILL_FIRE_RL_doFMV_D_X ||
WILL_FIRE_RL_doFLE_D ||
WILL_FIRE_RL_doFLT_D ||
WILL_FIRE_RL_doFEQ_D ||
WILL_FIRE_RL_doFMAX_D ||
WILL_FIRE_RL_doFMIN_D ||
WILL_FIRE_RL_doFCVT_D_S ||
WILL_FIRE_RL_doFCVT_S_D ||
WILL_FIRE_RL_doFCVT_LU_D ||
WILL_FIRE_RL_doFCVT_L_D ||
WILL_FIRE_RL_doFCVT_D_LU ||
WILL_FIRE_RL_doFCVT_D_L ||
WILL_FIRE_RL_doFCVT_WU_D ||
WILL_FIRE_RL_doFCVT_W_D ||
WILL_FIRE_RL_doFCVT_D_WU ||
WILL_FIRE_RL_doFCVT_D_W ||
WILL_FIRE_RL_doFSGNJX_D ||
WILL_FIRE_RL_doFSGNJN_D ||
WILL_FIRE_RL_doFSGNJ_D:
stateR$D_IN = 2'd3;
WILL_FIRE_RL_doFSQRT_D || WILL_FIRE_RL_doFDIV_D ||
WILL_FIRE_RL_doFNMSUB_D ||
WILL_FIRE_RL_doFNMADD_D ||
WILL_FIRE_RL_doFMSUB_D ||
WILL_FIRE_RL_doFMADD_D ||
WILL_FIRE_RL_doFMUL_D ||
WILL_FIRE_RL_doFSUB_D ||
WILL_FIRE_RL_doFADD_D:
stateR$D_IN = 2'd2;
WILL_FIRE_RL_doFCLASS_S || WILL_FIRE_RL_doFLE_S || WILL_FIRE_RL_doFLT_S ||
WILL_FIRE_RL_doFEQ_S ||
WILL_FIRE_RL_doFMV_X_W ||
WILL_FIRE_RL_doFMV_W_X ||
WILL_FIRE_RL_doFMAX_S ||
WILL_FIRE_RL_doFMIN_S ||
WILL_FIRE_RL_doFCVT_WU_S ||
WILL_FIRE_RL_doFCVT_W_S ||
WILL_FIRE_RL_doFCVT_LU_S ||
WILL_FIRE_RL_doFCVT_L_S ||
WILL_FIRE_RL_doFCVT_S_WU ||
WILL_FIRE_RL_doFCVT_S_W ||
WILL_FIRE_RL_doFCVT_S_LU ||
WILL_FIRE_RL_doFCVT_S_L ||
WILL_FIRE_RL_doFSGNJX_S ||
WILL_FIRE_RL_doFSGNJN_S ||
WILL_FIRE_RL_doFSGNJ_S:
stateR$D_IN = 2'd3;
WILL_FIRE_RL_doFSQRT_S || WILL_FIRE_RL_doFDIV_S ||
WILL_FIRE_RL_doFNMSUB_S ||
WILL_FIRE_RL_doFNMADD_S ||
WILL_FIRE_RL_doFMSUB_S ||
WILL_FIRE_RL_doFMADD_S ||
WILL_FIRE_RL_doFMUL_S ||
WILL_FIRE_RL_doFSUB_S ||
WILL_FIRE_RL_doFADD_S:
stateR$D_IN = 2'd2;
WILL_FIRE_RL_rl_reset_end: stateR$D_IN = 2'd1;
default: stateR$D_IN = 2'b10 /* unspecified value */ ;
endcase
assign stateR$EN =
WILL_FIRE_RL_rl_reset_begin || WILL_FIRE_RL_rl_reset_end ||
EN_req ||
WILL_FIRE_RL_doFSQRT_D ||
WILL_FIRE_RL_doFDIV_D ||
WILL_FIRE_RL_doFNMSUB_D ||
WILL_FIRE_RL_doFNMADD_D ||
WILL_FIRE_RL_doFMSUB_D ||
WILL_FIRE_RL_doFMADD_D ||
WILL_FIRE_RL_doFMUL_D ||
WILL_FIRE_RL_doFSUB_D ||
WILL_FIRE_RL_doFADD_D ||
WILL_FIRE_RL_doFSQRT_S ||
WILL_FIRE_RL_doFDIV_S ||
WILL_FIRE_RL_doFNMSUB_S ||
WILL_FIRE_RL_doFNMADD_S ||
WILL_FIRE_RL_doFMSUB_S ||
WILL_FIRE_RL_doFMADD_S ||
WILL_FIRE_RL_doFMUL_S ||
WILL_FIRE_RL_doFSUB_S ||
WILL_FIRE_RL_doFADD_S ||
WILL_FIRE_RL_rl_get_fpu_result ||
WILL_FIRE_RL_doFCLASS_D ||
WILL_FIRE_RL_doFMV_X_D ||
WILL_FIRE_RL_doFMV_D_X ||
WILL_FIRE_RL_doFLE_D ||
WILL_FIRE_RL_doFLT_D ||
WILL_FIRE_RL_doFEQ_D ||
WILL_FIRE_RL_doFMAX_D ||
WILL_FIRE_RL_doFMIN_D ||
WILL_FIRE_RL_doFCVT_D_S ||
WILL_FIRE_RL_doFCVT_S_D ||
WILL_FIRE_RL_doFCVT_LU_D ||
WILL_FIRE_RL_doFCVT_L_D ||
WILL_FIRE_RL_doFCVT_D_LU ||
WILL_FIRE_RL_doFCVT_D_L ||
WILL_FIRE_RL_doFCVT_WU_D ||
WILL_FIRE_RL_doFCVT_W_D ||
WILL_FIRE_RL_doFCVT_D_WU ||
WILL_FIRE_RL_doFCVT_D_W ||
WILL_FIRE_RL_doFSGNJX_D ||
WILL_FIRE_RL_doFSGNJN_D ||
WILL_FIRE_RL_doFSGNJ_D ||
WILL_FIRE_RL_doFCLASS_S ||
WILL_FIRE_RL_doFLE_S ||
WILL_FIRE_RL_doFLT_S ||
WILL_FIRE_RL_doFEQ_S ||
WILL_FIRE_RL_doFMV_X_W ||
WILL_FIRE_RL_doFMV_W_X ||
WILL_FIRE_RL_doFMAX_S ||
WILL_FIRE_RL_doFMIN_S ||
WILL_FIRE_RL_doFCVT_WU_S ||
WILL_FIRE_RL_doFCVT_W_S ||
WILL_FIRE_RL_doFCVT_LU_S ||
WILL_FIRE_RL_doFCVT_L_S ||
WILL_FIRE_RL_doFCVT_S_WU ||
WILL_FIRE_RL_doFCVT_S_W ||
WILL_FIRE_RL_doFCVT_S_LU ||
WILL_FIRE_RL_doFCVT_S_L ||
WILL_FIRE_RL_doFSGNJX_S ||
WILL_FIRE_RL_doFSGNJN_S ||
WILL_FIRE_RL_doFSGNJ_S ;
// submodule fpu
always@(WILL_FIRE_RL_doFADD_S or
MUX_fpu$server_core_request_put_1__VAL_1 or
WILL_FIRE_RL_doFSUB_S or
MUX_fpu$server_core_request_put_1__VAL_2 or
WILL_FIRE_RL_doFMUL_S or
MUX_fpu$server_core_request_put_1__VAL_3 or
WILL_FIRE_RL_doFMADD_S or
MUX_fpu$server_core_request_put_1__VAL_4 or
WILL_FIRE_RL_doFMSUB_S or
MUX_fpu$server_core_request_put_1__VAL_5 or
WILL_FIRE_RL_doFNMADD_S or
MUX_fpu$server_core_request_put_1__VAL_6 or
WILL_FIRE_RL_doFNMSUB_S or
MUX_fpu$server_core_request_put_1__VAL_7 or
WILL_FIRE_RL_doFDIV_S or
MUX_fpu$server_core_request_put_1__VAL_8 or
WILL_FIRE_RL_doFSQRT_S or
MUX_fpu$server_core_request_put_1__VAL_9 or
WILL_FIRE_RL_doFADD_D or
MUX_fpu$server_core_request_put_1__VAL_10 or
WILL_FIRE_RL_doFSUB_D or
MUX_fpu$server_core_request_put_1__VAL_11 or
WILL_FIRE_RL_doFMUL_D or
MUX_fpu$server_core_request_put_1__VAL_12 or
WILL_FIRE_RL_doFMADD_D or
MUX_fpu$server_core_request_put_1__VAL_13 or
WILL_FIRE_RL_doFMSUB_D or
MUX_fpu$server_core_request_put_1__VAL_14 or
WILL_FIRE_RL_doFNMADD_D or
MUX_fpu$server_core_request_put_1__VAL_15 or
WILL_FIRE_RL_doFNMSUB_D or
MUX_fpu$server_core_request_put_1__VAL_16 or
WILL_FIRE_RL_doFDIV_D or
MUX_fpu$server_core_request_put_1__VAL_17 or
WILL_FIRE_RL_doFSQRT_D or MUX_fpu$server_core_request_put_1__VAL_18)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_doFADD_S:
fpu$server_core_request_put =
MUX_fpu$server_core_request_put_1__VAL_1;
WILL_FIRE_RL_doFSUB_S:
fpu$server_core_request_put =
MUX_fpu$server_core_request_put_1__VAL_2;
WILL_FIRE_RL_doFMUL_S:
fpu$server_core_request_put =
MUX_fpu$server_core_request_put_1__VAL_3;
WILL_FIRE_RL_doFMADD_S:
fpu$server_core_request_put =
MUX_fpu$server_core_request_put_1__VAL_4;
WILL_FIRE_RL_doFMSUB_S:
fpu$server_core_request_put =
MUX_fpu$server_core_request_put_1__VAL_5;
WILL_FIRE_RL_doFNMADD_S:
fpu$server_core_request_put =
MUX_fpu$server_core_request_put_1__VAL_6;
WILL_FIRE_RL_doFNMSUB_S:
fpu$server_core_request_put =
MUX_fpu$server_core_request_put_1__VAL_7;
WILL_FIRE_RL_doFDIV_S:
fpu$server_core_request_put =
MUX_fpu$server_core_request_put_1__VAL_8;
WILL_FIRE_RL_doFSQRT_S:
fpu$server_core_request_put =
MUX_fpu$server_core_request_put_1__VAL_9;
WILL_FIRE_RL_doFADD_D:
fpu$server_core_request_put =
MUX_fpu$server_core_request_put_1__VAL_10;
WILL_FIRE_RL_doFSUB_D:
fpu$server_core_request_put =
MUX_fpu$server_core_request_put_1__VAL_11;
WILL_FIRE_RL_doFMUL_D:
fpu$server_core_request_put =
MUX_fpu$server_core_request_put_1__VAL_12;
WILL_FIRE_RL_doFMADD_D:
fpu$server_core_request_put =
MUX_fpu$server_core_request_put_1__VAL_13;
WILL_FIRE_RL_doFMSUB_D:
fpu$server_core_request_put =
MUX_fpu$server_core_request_put_1__VAL_14;
WILL_FIRE_RL_doFNMADD_D:
fpu$server_core_request_put =
MUX_fpu$server_core_request_put_1__VAL_15;
WILL_FIRE_RL_doFNMSUB_D:
fpu$server_core_request_put =
MUX_fpu$server_core_request_put_1__VAL_16;
WILL_FIRE_RL_doFDIV_D:
fpu$server_core_request_put =
MUX_fpu$server_core_request_put_1__VAL_17;
WILL_FIRE_RL_doFSQRT_D:
fpu$server_core_request_put =
MUX_fpu$server_core_request_put_1__VAL_18;
default: fpu$server_core_request_put =
202'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign fpu$EN_server_core_request_put =
WILL_FIRE_RL_doFADD_S || WILL_FIRE_RL_doFSUB_S ||
WILL_FIRE_RL_doFMUL_S ||
WILL_FIRE_RL_doFMADD_S ||
WILL_FIRE_RL_doFMSUB_S ||
WILL_FIRE_RL_doFNMADD_S ||
WILL_FIRE_RL_doFNMSUB_S ||
WILL_FIRE_RL_doFDIV_S ||
WILL_FIRE_RL_doFSQRT_S ||
WILL_FIRE_RL_doFADD_D ||
WILL_FIRE_RL_doFSUB_D ||
WILL_FIRE_RL_doFMUL_D ||
WILL_FIRE_RL_doFMADD_D ||
WILL_FIRE_RL_doFMSUB_D ||
WILL_FIRE_RL_doFNMADD_D ||
WILL_FIRE_RL_doFNMSUB_D ||
WILL_FIRE_RL_doFDIV_D ||
WILL_FIRE_RL_doFSQRT_D ;
assign fpu$EN_server_core_response_get = MUX_dw_result$wset_1__SEL_1 ;
assign fpu$EN_server_reset_request_put = CAN_FIRE_RL_rl_reset_begin ;
assign fpu$EN_server_reset_response_get = CAN_FIRE_RL_rl_reset_end ;
// submodule frmFpuF
assign frmFpuF$D_IN = 1'b0 ;
assign frmFpuF$ENQ = 1'b0 ;
assign frmFpuF$DEQ = 1'b0 ;
assign frmFpuF$CLR = CAN_FIRE_RL_rl_reset_begin ;
// submodule resetReqsF
assign resetReqsF$ENQ = EN_server_reset_request_put ;
assign resetReqsF$DEQ =
fpu$RDY_server_reset_request_put && resetReqsF$EMPTY_N ;
assign resetReqsF$CLR = 1'b0 ;
// submodule resetRspsF
assign resetRspsF$ENQ =
fpu$RDY_server_reset_response_get && resetRspsF$FULL_N &&
stateR == 2'd0 ;
assign resetRspsF$DEQ = EN_server_reset_response_get ;
assign resetRspsF$CLR = 1'b0 ;
// remaining internal signals
assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_IF_requestR_3_ETC__q117 =
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_IF_requestR_3_BI_ETC___d3656 ?
_theResult___snd__h135453 :
_theResult____h126028 ;
assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_IF_reques_ETC__q154 =
_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_IF_requestR__ETC___d4935 ?
_theResult___snd__h201397 :
_theResult____h191843 ;
assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_IF_requestR__ETC__q122 =
_0_CONCAT_IF_IF_3970_MINUS_SEXT_IF_requestR_3_B_ETC___d4100 ?
_theResult___snd__h155794 :
_theResult____h146240 ;
assign IF_0_CONCAT_IF_IF_IF_requestR_3_BIT_214_4_THEN_ETC__q151 =
_0_CONCAT_IF_IF_IF_requestR_3_BIT_214_4_THEN_re_ETC___d4615 ?
_theResult___snd__h190495 :
57'd0 ;
assign IF_0_CONCAT_IF_IF_IF_requestR_3_BIT_214_4_THEN_ETC__q157 =
_0_CONCAT_IF_IF_IF_requestR_3_BIT_214_4_THEN_re_ETC___d5008 ?
_theResult___snd__h190495 :
_theResult___snd__h211382 ;
assign IF_0_CONCAT_IF_IF_requestR_3_BIT_214_4_THEN_re_ETC__q119 =
_0_CONCAT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d3778 ?
_theResult___snd__h145298 :
57'd0 ;
assign IF_0_CONCAT_IF_IF_requestR_3_BIT_214_4_THEN_re_ETC__q125 =
_0_CONCAT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d4173 ?
_theResult___snd__h145298 :
_theResult___snd__h165663 ;
assign IF_3074_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_21_ETC___d4358 =
_3074_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_ETC___d3422 ?
((_theResult___fst_exp__h135390 == 8'd255) ?
requestR_BITS_191_TO_128__q1[63] :
((requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard26038_0b0_requestR_BITS_191_TO_128_B_ETC__q143 :
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q144)) :
((_theResult___fst_exp__h145309 == 8'd255) ?
requestR_BITS_191_TO_128__q1[63] :
((requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard36028_0b0_requestR_BITS_191_TO_128_B_ETC__q145 :
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q146)) ;
assign IF_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_2_ETC___d1379 =
_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d1327 ?
((requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard4468_0b0_requestR_BITS_191_TO_128_BI_ETC__q45 :
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q46) :
((x__h35010[7:0] == 8'd255) ?
requestR_BITS_191_TO_128__q1[31] :
((requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard4995_0b0_requestR_BITS_191_TO_128_BI_ETC__q47 :
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q48)) ;
assign IF_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_2_ETC___d1529 =
_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d1327 ?
guard__h34468 != 2'b0 :
x__h35010[7:0] != 8'd255 && guard__h34995 != 2'b0 ;
assign IF_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_2_ETC___d2398 =
_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d2347 ?
((requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard9399_0b0_requestR_BITS_191_TO_128_BI_ETC__q72 :
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q73) :
((x__h70144[10:0] == 11'd2047) ?
requestR_BITS_191_TO_128__q1[31] :
((requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard0129_0b0_requestR_BITS_191_TO_128_BI_ETC__q74 :
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q75)) ;
assign IF_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_2_ETC___d2513 =
_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d2347 ?
guard__h69399 != 2'b0 :
x__h70144[10:0] != 11'd2047 && guard__h70129 != 2'b0 ;
assign IF_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214__ETC___d1718 =
_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d1580 ?
guard__h41384 != 2'b0 :
x__h41925[7:0] != 8'd255 && guard__h41910 != 2'b0 ;
assign IF_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214__ETC___d2697 =
_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d2561 ?
guard__h80346 != 2'b0 :
x__h81090[10:0] != 11'd2047 && guard__h81075 != 2'b0 ;
assign IF_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_2_ETC___d2937 =
_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d2888 ?
((requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard5721_0b0_requestR_BITS_191_TO_128_BI_ETC__q97 :
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q98) :
((x__h96466[10:0] == 11'd2047) ?
requestR_BITS_191_TO_128__q1[63] :
((requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard6451_0b0_requestR_BITS_191_TO_128_BI_ETC__q99 :
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q100)) ;
assign IF_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_2_ETC___d3054 =
_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d2888 ?
guard__h95721 != 2'b0 :
x__h96466[10:0] != 11'd2047 && guard__h96451 != 2'b0 ;
assign IF_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_2_ETC___d511 =
_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d450 ?
((requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard5015_0b0_requestR_BITS_191_TO_128_BI_ETC__q13 :
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q14) :
((x__h15560[7:0] == 8'd255) ?
requestR_BITS_191_TO_128__q1[63] :
((requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard5545_0b0_requestR_BITS_191_TO_128_BI_ETC__q15 :
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q16)) ;
assign IF_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_2_ETC___d693 =
_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d450 ?
guard__h15015 != 2'b0 :
x__h15560[7:0] != 8'd255 && guard__h15545 != 2'b0 ;
assign IF_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214__ETC___d1174 =
_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d972 ?
guard__h27296 != 2'b0 :
x__h27837[7:0] != 8'd255 && guard__h27822 != 2'b0 ;
assign IF_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214__ETC___d3208 =
_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d3071 ?
guard__h108246 != 2'b0 :
x__h108990[10:0] != 11'd2047 && guard__h108975 != 2'b0 ;
assign IF_IF_0b0_CONCAT_NOT_IF_requestR_3_BIT_214_4_T_ETC___d3654 =
(_theResult____h126028[56] ?
6'd0 :
(_theResult____h126028[55] ?
6'd1 :
(_theResult____h126028[54] ?
6'd2 :
(_theResult____h126028[53] ?
6'd3 :
(_theResult____h126028[52] ?
6'd4 :
(_theResult____h126028[51] ?
6'd5 :
(_theResult____h126028[50] ?
6'd6 :
(_theResult____h126028[49] ?
6'd7 :
(_theResult____h126028[48] ?
6'd8 :
(_theResult____h126028[47] ?
6'd9 :
(_theResult____h126028[46] ?
6'd10 :
(_theResult____h126028[45] ?
6'd11 :
(_theResult____h126028[44] ?
6'd12 :
(_theResult____h126028[43] ?
6'd13 :
(_theResult____h126028[42] ?
6'd14 :
(_theResult____h126028[41] ?
6'd15 :
(_theResult____h126028[40] ?
6'd16 :
(_theResult____h126028[39] ?
6'd17 :
(_theResult____h126028[38] ?
6'd18 :
(_theResult____h126028[37] ?
6'd19 :
(_theResult____h126028[36] ?
6'd20 :
(_theResult____h126028[35] ?
6'd21 :
(_theResult____h126028[34] ?
6'd22 :
(_theResult____h126028[33] ?
6'd23 :
(_theResult____h126028[32] ?
6'd24 :
(_theResult____h126028[31] ?
6'd25 :
(_theResult____h126028[30] ?
6'd26 :
(_theResult____h126028[29] ?
6'd27 :
(_theResult____h126028[28] ?
6'd28 :
(_theResult____h126028[27] ?
6'd29 :
(_theResult____h126028[26] ?
6'd30 :
(_theResult____h126028[25] ?
6'd31 :
(_theResult____h126028[24] ?
6'd32 :
(_theResult____h126028[23] ?
6'd33 :
(_theResult____h126028[22] ?
6'd34 :
(_theResult____h126028[21] ?
6'd35 :
(_theResult____h126028[20] ?
6'd36 :
(_theResult____h126028[19] ?
6'd37 :
(_theResult____h126028[18] ?
6'd38 :
(_theResult____h126028[17] ?
6'd39 :
(_theResult____h126028[16] ?
6'd40 :
(_theResult____h126028[15] ?
6'd41 :
(_theResult____h126028[14] ?
6'd42 :
(_theResult____h126028[13] ?
6'd43 :
(_theResult____h126028[12] ?
6'd44 :
(_theResult____h126028[11] ?
6'd45 :
(_theResult____h126028[10] ?
6'd46 :
(_theResult____h126028[9] ?
6'd47 :
(_theResult____h126028[8] ?
6'd48 :
(_theResult____h126028[7] ?
6'd49 :
(_theResult____h126028[6] ?
6'd50 :
(_theResult____h126028[5] ?
6'd51 :
(_theResult____h126028[4] ?
6'd52 :
(_theResult____h126028[3] ?
6'd53 :
(_theResult____h126028[2] ?
6'd54 :
(_theResult____h126028[1] ?
6'd55 :
(_theResult____h126028[0] ?
6'd56 :
6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) -
6'd1 ;
assign IF_IF_3074_MINUS_SEXT_IF_IF_requestR_3_BIT_214_ETC___d4933 =
(_theResult____h191843[56] ?
6'd0 :
(_theResult____h191843[55] ?
6'd1 :
(_theResult____h191843[54] ?
6'd2 :
(_theResult____h191843[53] ?
6'd3 :
(_theResult____h191843[52] ?
6'd4 :
(_theResult____h191843[51] ?
6'd5 :
(_theResult____h191843[50] ?
6'd6 :
(_theResult____h191843[49] ?
6'd7 :
(_theResult____h191843[48] ?
6'd8 :
(_theResult____h191843[47] ?
6'd9 :
(_theResult____h191843[46] ?
6'd10 :
(_theResult____h191843[45] ?
6'd11 :
(_theResult____h191843[44] ?
6'd12 :
(_theResult____h191843[43] ?
6'd13 :
(_theResult____h191843[42] ?
6'd14 :
(_theResult____h191843[41] ?
6'd15 :
(_theResult____h191843[40] ?
6'd16 :
(_theResult____h191843[39] ?
6'd17 :
(_theResult____h191843[38] ?
6'd18 :
(_theResult____h191843[37] ?
6'd19 :
(_theResult____h191843[36] ?
6'd20 :
(_theResult____h191843[35] ?
6'd21 :
(_theResult____h191843[34] ?
6'd22 :
(_theResult____h191843[33] ?
6'd23 :
(_theResult____h191843[32] ?
6'd24 :
(_theResult____h191843[31] ?
6'd25 :
(_theResult____h191843[30] ?
6'd26 :
(_theResult____h191843[29] ?
6'd27 :
(_theResult____h191843[28] ?
6'd28 :
(_theResult____h191843[27] ?
6'd29 :
(_theResult____h191843[26] ?
6'd30 :
(_theResult____h191843[25] ?
6'd31 :
(_theResult____h191843[24] ?
6'd32 :
(_theResult____h191843[23] ?
6'd33 :
(_theResult____h191843[22] ?
6'd34 :
(_theResult____h191843[21] ?
6'd35 :
(_theResult____h191843[20] ?
6'd36 :
(_theResult____h191843[19] ?
6'd37 :
(_theResult____h191843[18] ?
6'd38 :
(_theResult____h191843[17] ?
6'd39 :
(_theResult____h191843[16] ?
6'd40 :
(_theResult____h191843[15] ?
6'd41 :
(_theResult____h191843[14] ?
6'd42 :
(_theResult____h191843[13] ?
6'd43 :
(_theResult____h191843[12] ?
6'd44 :
(_theResult____h191843[11] ?
6'd45 :
(_theResult____h191843[10] ?
6'd46 :
(_theResult____h191843[9] ?
6'd47 :
(_theResult____h191843[8] ?
6'd48 :
(_theResult____h191843[7] ?
6'd49 :
(_theResult____h191843[6] ?
6'd50 :
(_theResult____h191843[5] ?
6'd51 :
(_theResult____h191843[4] ?
6'd52 :
(_theResult____h191843[3] ?
6'd53 :
(_theResult____h191843[2] ?
6'd54 :
(_theResult____h191843[1] ?
6'd55 :
(_theResult____h191843[0] ?
6'd56 :
6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) -
6'd1 ;
assign IF_IF_3970_MINUS_SEXT_IF_requestR_3_BIT_214_4__ETC___d4098 =
(_theResult____h146240[56] ?
6'd0 :
(_theResult____h146240[55] ?
6'd1 :
(_theResult____h146240[54] ?
6'd2 :
(_theResult____h146240[53] ?
6'd3 :
(_theResult____h146240[52] ?
6'd4 :
(_theResult____h146240[51] ?
6'd5 :
(_theResult____h146240[50] ?
6'd6 :
(_theResult____h146240[49] ?
6'd7 :
(_theResult____h146240[48] ?
6'd8 :
(_theResult____h146240[47] ?
6'd9 :
(_theResult____h146240[46] ?
6'd10 :
(_theResult____h146240[45] ?
6'd11 :
(_theResult____h146240[44] ?
6'd12 :
(_theResult____h146240[43] ?
6'd13 :
(_theResult____h146240[42] ?
6'd14 :
(_theResult____h146240[41] ?
6'd15 :
(_theResult____h146240[40] ?
6'd16 :
(_theResult____h146240[39] ?
6'd17 :
(_theResult____h146240[38] ?
6'd18 :
(_theResult____h146240[37] ?
6'd19 :
(_theResult____h146240[36] ?
6'd20 :
(_theResult____h146240[35] ?
6'd21 :
(_theResult____h146240[34] ?
6'd22 :
(_theResult____h146240[33] ?
6'd23 :
(_theResult____h146240[32] ?
6'd24 :
(_theResult____h146240[31] ?
6'd25 :
(_theResult____h146240[30] ?
6'd26 :
(_theResult____h146240[29] ?
6'd27 :
(_theResult____h146240[28] ?
6'd28 :
(_theResult____h146240[27] ?
6'd29 :
(_theResult____h146240[26] ?
6'd30 :
(_theResult____h146240[25] ?
6'd31 :
(_theResult____h146240[24] ?
6'd32 :
(_theResult____h146240[23] ?
6'd33 :
(_theResult____h146240[22] ?
6'd34 :
(_theResult____h146240[21] ?
6'd35 :
(_theResult____h146240[20] ?
6'd36 :
(_theResult____h146240[19] ?
6'd37 :
(_theResult____h146240[18] ?
6'd38 :
(_theResult____h146240[17] ?
6'd39 :
(_theResult____h146240[16] ?
6'd40 :
(_theResult____h146240[15] ?
6'd41 :
(_theResult____h146240[14] ?
6'd42 :
(_theResult____h146240[13] ?
6'd43 :
(_theResult____h146240[12] ?
6'd44 :
(_theResult____h146240[11] ?
6'd45 :
(_theResult____h146240[10] ?
6'd46 :
(_theResult____h146240[9] ?
6'd47 :
(_theResult____h146240[8] ?
6'd48 :
(_theResult____h146240[7] ?
6'd49 :
(_theResult____h146240[6] ?
6'd50 :
(_theResult____h146240[5] ?
6'd51 :
(_theResult____h146240[4] ?
6'd52 :
(_theResult____h146240[3] ?
6'd53 :
(_theResult____h146240[2] ?
6'd54 :
(_theResult____h146240[1] ?
6'd55 :
(_theResult____h146240[0] ?
6'd56 :
6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) -
6'd1 ;
assign IF_IF_IF_IF_0b0_CONCAT_NOT_IF_requestR_3_BIT_2_ETC___d3713 =
(guard__h126038 == 2'b0 || requestR_BITS_191_TO_128__q1[63]) ?
_theResult___fst_exp__h135390 :
_theResult___exp__h135916 ;
assign IF_IF_IF_IF_0b0_CONCAT_NOT_IF_requestR_3_BIT_2_ETC___d3715 =
(guard__h126038 == 2'b0) ?
_theResult___fst_exp__h135390 :
(requestR_BITS_191_TO_128__q1[63] ?
_theResult___exp__h135916 :
_theResult___fst_exp__h135390) ;
assign IF_IF_IF_IF_0b0_CONCAT_NOT_IF_requestR_3_BIT_2_ETC___d4260 =
(guard__h126038 == 2'b0 || requestR_BITS_191_TO_128__q1[63]) ?
sfdin__h135384[56:34] :
_theResult___sfd__h135917 ;
assign IF_IF_IF_IF_0b0_CONCAT_NOT_IF_requestR_3_BIT_2_ETC___d4262 =
(guard__h126038 == 2'b0) ?
sfdin__h135384[56:34] :
(requestR_BITS_191_TO_128__q1[63] ?
_theResult___sfd__h135917 :
sfdin__h135384[56:34]) ;
assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_IF_requestR_3_B_ETC___d4992 =
(guard__h191853 == 2'b0 ||
requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31]) ?
_theResult___fst_exp__h201334 :
_theResult___exp__h202063 ;
assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_IF_requestR_3_B_ETC___d4994 =
(guard__h191853 == 2'b0) ?
_theResult___fst_exp__h201334 :
((requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31]) ?
_theResult___exp__h202063 :
_theResult___fst_exp__h201334) ;
assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_IF_requestR_3_B_ETC___d5121 =
(guard__h191853 == 2'b0 ||
requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31]) ?
sfdin__h201328[56:5] :
_theResult___sfd__h202064 ;
assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_IF_requestR_3_B_ETC___d5123 =
(guard__h191853 == 2'b0) ?
sfdin__h201328[56:5] :
((requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31]) ?
_theResult___sfd__h202064 :
sfdin__h201328[56:5]) ;
assign IF_IF_IF_IF_3970_MINUS_SEXT_IF_requestR_3_BIT__ETC___d4157 =
(guard__h146250 == 2'b0 || requestR_BITS_191_TO_128__q1[63]) ?
_theResult___fst_exp__h155731 :
_theResult___exp__h156257 ;
assign IF_IF_IF_IF_3970_MINUS_SEXT_IF_requestR_3_BIT__ETC___d4159 =
(guard__h146250 == 2'b0) ?
_theResult___fst_exp__h155731 :
(requestR_BITS_191_TO_128__q1[63] ?
_theResult___exp__h156257 :
_theResult___fst_exp__h155731) ;
assign IF_IF_IF_IF_3970_MINUS_SEXT_IF_requestR_3_BIT__ETC___d4306 =
(guard__h146250 == 2'b0 || requestR_BITS_191_TO_128__q1[63]) ?
sfdin__h155725[56:34] :
_theResult___sfd__h156258 ;
assign IF_IF_IF_IF_3970_MINUS_SEXT_IF_requestR_3_BIT__ETC___d4308 =
(guard__h146250 == 2'b0) ?
sfdin__h155725[56:34] :
(requestR_BITS_191_TO_128__q1[63] ?
_theResult___sfd__h156258 :
sfdin__h155725[56:34]) ;
assign IF_IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d4667 =
(guard__h181312 == 2'b0 ||
requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31]) ?
_theResult___fst_exp__h190506 :
_theResult___exp__h191161 ;
assign IF_IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d4669 =
(guard__h181312 == 2'b0) ?
_theResult___fst_exp__h190506 :
((requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31]) ?
_theResult___exp__h191161 :
_theResult___fst_exp__h190506) ;
assign IF_IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d5061 =
(guard__h202175 == 2'b0 ||
requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31]) ?
_theResult___fst_exp__h211398 :
_theResult___exp__h212078 ;
assign IF_IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d5063 =
(guard__h202175 == 2'b0) ?
_theResult___fst_exp__h211398 :
((requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31]) ?
_theResult___exp__h212078 :
_theResult___fst_exp__h211398) ;
assign IF_IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d5094 =
(guard__h181312 == 2'b0 ||
requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31]) ?
_theResult___snd__h190457[56:5] :
_theResult___sfd__h191162 ;
assign IF_IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d5096 =
(guard__h181312 == 2'b0) ?
_theResult___snd__h190457[56:5] :
((requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31]) ?
_theResult___sfd__h191162 :
_theResult___snd__h190457[56:5]) ;
assign IF_IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d5140 =
(guard__h202175 == 2'b0 ||
requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31]) ?
_theResult___snd__h211344[56:5] :
_theResult___sfd__h212079 ;
assign IF_IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d5142 =
(guard__h202175 == 2'b0) ?
_theResult___snd__h211344[56:5] :
((requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31]) ?
_theResult___sfd__h212079 :
_theResult___snd__h211344[56:5]) ;
assign IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d1401 =
(guard__h34468 == 2'b0) ?
8'd0 :
(requestR_BITS_191_TO_128__q1[31] ?
_theResult___exp__h34881 :
8'd0) ;
assign IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d1427 =
(guard__h34995 == 2'b0 || requestR_BITS_191_TO_128__q1[31]) ?
x__h35010[7:0] :
_theResult___exp__h35434 ;
assign IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d1429 =
(guard__h34995 == 2'b0) ?
x__h35010[7:0] :
(requestR_BITS_191_TO_128__q1[31] ?
_theResult___exp__h35434 :
x__h35010[7:0]) ;
assign IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d1450 =
(guard__h34468 == 2'b0 || requestR_BITS_191_TO_128__q1[31]) ?
sfd___3__h34458[31:9] :
_theResult___sfd__h34882 ;
assign IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d1452 =
(guard__h34468 == 2'b0) ?
sfd___3__h34458[31:9] :
(requestR_BITS_191_TO_128__q1[31] ?
_theResult___sfd__h34882 :
sfd___3__h34458[31:9]) ;
assign IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d1468 =
(guard__h34995 == 2'b0 || requestR_BITS_191_TO_128__q1[31]) ?
sfd___3__h34458[30:8] :
_theResult___sfd__h35435 ;
assign IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d1470 =
(guard__h34995 == 2'b0) ?
sfd___3__h34458[30:8] :
(requestR_BITS_191_TO_128__q1[31] ?
_theResult___sfd__h35435 :
sfd___3__h34458[30:8]) ;
assign IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2419 =
(guard__h69399 == 2'b0) ?
11'd0 :
(requestR_BITS_191_TO_128__q1[31] ?
_theResult___exp__h70015 :
11'd0) ;
assign IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2445 =
(guard__h70129 == 2'b0 || requestR_BITS_191_TO_128__q1[31]) ?
x__h70144[10:0] :
_theResult___exp__h70771 ;
assign IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2447 =
(guard__h70129 == 2'b0) ?
x__h70144[10:0] :
(requestR_BITS_191_TO_128__q1[31] ?
_theResult___exp__h70771 :
x__h70144[10:0]) ;
assign IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2468 =
(guard__h69399 == 2'b0 || requestR_BITS_191_TO_128__q1[31]) ?
sfd___3__h69389[54:3] :
_theResult___sfd__h70016 ;
assign IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2470 =
(guard__h69399 == 2'b0) ?
sfd___3__h69389[54:3] :
(requestR_BITS_191_TO_128__q1[31] ?
_theResult___sfd__h70016 :
sfd___3__h69389[54:3]) ;
assign IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2486 =
(guard__h70129 == 2'b0 || requestR_BITS_191_TO_128__q1[31]) ?
sfd___3__h69389[53:2] :
_theResult___sfd__h70772 ;
assign IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2488 =
(guard__h70129 == 2'b0) ?
sfd___3__h69389[53:2] :
(requestR_BITS_191_TO_128__q1[31] ?
_theResult___sfd__h70772 :
sfd___3__h69389[53:2]) ;
assign IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2958 =
(guard__h95721 == 2'b0) ?
11'd0 :
(requestR_BITS_191_TO_128__q1[63] ?
_theResult___exp__h96337 :
11'd0) ;
assign IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2984 =
(guard__h96451 == 2'b0 || requestR_BITS_191_TO_128__q1[63]) ?
x__h96466[10:0] :
_theResult___exp__h97093 ;
assign IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2986 =
(guard__h96451 == 2'b0) ?
x__h96466[10:0] :
(requestR_BITS_191_TO_128__q1[63] ?
_theResult___exp__h97093 :
x__h96466[10:0]) ;
assign IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d3007 =
(guard__h95721 == 2'b0 || requestR_BITS_191_TO_128__q1[63]) ?
sfd___3__h15005[63:12] :
_theResult___sfd__h96338 ;
assign IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d3009 =
(guard__h95721 == 2'b0) ?
sfd___3__h15005[63:12] :
(requestR_BITS_191_TO_128__q1[63] ?
_theResult___sfd__h96338 :
sfd___3__h15005[63:12]) ;
assign IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d3025 =
(guard__h96451 == 2'b0 || requestR_BITS_191_TO_128__q1[63]) ?
sfd___3__h15005[62:11] :
_theResult___sfd__h97094 ;
assign IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d3027 =
(guard__h96451 == 2'b0) ?
sfd___3__h15005[62:11] :
(requestR_BITS_191_TO_128__q1[63] ?
_theResult___sfd__h97094 :
sfd___3__h15005[62:11]) ;
assign IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d3830 =
(guard__h136028 == 2'b0 || requestR_BITS_191_TO_128__q1[63]) ?
_theResult___fst_exp__h145309 :
_theResult___exp__h145761 ;
assign IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d3832 =
(guard__h136028 == 2'b0) ?
_theResult___fst_exp__h145309 :
(requestR_BITS_191_TO_128__q1[63] ?
_theResult___exp__h145761 :
_theResult___fst_exp__h145309) ;
assign IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d4226 =
(guard__h156369 == 2'b0 || requestR_BITS_191_TO_128__q1[63]) ?
_theResult___fst_exp__h165679 :
_theResult___exp__h166156 ;
assign IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d4228 =
(guard__h156369 == 2'b0) ?
_theResult___fst_exp__h165679 :
(requestR_BITS_191_TO_128__q1[63] ?
_theResult___exp__h166156 :
_theResult___fst_exp__h165679) ;
assign IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d4279 =
(guard__h136028 == 2'b0 || requestR_BITS_191_TO_128__q1[63]) ?
_theResult___snd__h145260[56:34] :
_theResult___sfd__h145762 ;
assign IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d4281 =
(guard__h136028 == 2'b0) ?
_theResult___snd__h145260[56:34] :
(requestR_BITS_191_TO_128__q1[63] ?
_theResult___sfd__h145762 :
_theResult___snd__h145260[56:34]) ;
assign IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d4325 =
(guard__h156369 == 2'b0 || requestR_BITS_191_TO_128__q1[63]) ?
_theResult___snd__h165625[56:34] :
_theResult___sfd__h166157 ;
assign IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d4327 =
(guard__h156369 == 2'b0) ?
_theResult___snd__h165625[56:34] :
(requestR_BITS_191_TO_128__q1[63] ?
_theResult___sfd__h166157 :
_theResult___snd__h165625[56:34]) ;
assign IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d533 =
(guard__h15015 == 2'b0) ?
8'd0 :
(requestR_BITS_191_TO_128__q1[63] ?
_theResult___exp__h15431 :
8'd0) ;
assign IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d559 =
(guard__h15545 == 2'b0 || requestR_BITS_191_TO_128__q1[63]) ?
x__h15560[7:0] :
_theResult___exp__h15984 ;
assign IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d561 =
(guard__h15545 == 2'b0) ?
x__h15560[7:0] :
(requestR_BITS_191_TO_128__q1[63] ?
_theResult___exp__h15984 :
x__h15560[7:0]) ;
assign IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d582 =
(guard__h15015 == 2'b0 || requestR_BITS_191_TO_128__q1[63]) ?
sfd___3__h15005[63:41] :
_theResult___sfd__h15432 ;
assign IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d584 =
(guard__h15015 == 2'b0) ?
sfd___3__h15005[63:41] :
(requestR_BITS_191_TO_128__q1[63] ?
_theResult___sfd__h15432 :
sfd___3__h15005[63:41]) ;
assign IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d600 =
(guard__h15545 == 2'b0 || requestR_BITS_191_TO_128__q1[63]) ?
sfd___3__h15005[62:40] :
_theResult___sfd__h15985 ;
assign IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d602 =
(guard__h15545 == 2'b0) ?
sfd___3__h15005[62:40] :
(requestR_BITS_191_TO_128__q1[63] ?
_theResult___sfd__h15985 :
sfd___3__h15005[62:40]) ;
assign IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d1318 =
sfd__h28849[31] ?
6'd0 :
(sfd__h28849[30] ?
6'd1 :
(sfd__h28849[29] ?
6'd2 :
(sfd__h28849[28] ?
6'd3 :
(sfd__h28849[27] ?
6'd4 :
(sfd__h28849[26] ?
6'd5 :
(sfd__h28849[25] ?
6'd6 :
(sfd__h28849[24] ?
6'd7 :
(sfd__h28849[23] ?
6'd8 :
(sfd__h28849[22] ?
6'd9 :
(sfd__h28849[21] ?
6'd10 :
(sfd__h28849[20] ?
6'd11 :
(sfd__h28849[19] ?
6'd12 :
(sfd__h28849[18] ?
6'd13 :
(sfd__h28849[17] ?
6'd14 :
(sfd__h28849[16] ?
6'd15 :
(sfd__h28849[15] ?
6'd16 :
(sfd__h28849[14] ?
6'd17 :
(sfd__h28849[13] ?
6'd18 :
(sfd__h28849[12] ?
6'd19 :
(sfd__h28849[11] ?
6'd20 :
(sfd__h28849[10] ?
6'd21 :
(sfd__h28849[9] ?
6'd22 :
(sfd__h28849[8] ?
6'd23 :
(sfd__h28849[7] ?
6'd24 :
(sfd__h28849[6] ?
6'd25 :
(sfd__h28849[5] ?
6'd26 :
(sfd__h28849[4] ?
6'd27 :
(sfd__h28849[3] ?
6'd28 :
(sfd__h28849[2] ?
6'd29 :
(sfd__h28849[1] ?
6'd30 :
(sfd__h28849[0] ?
6'd31 :
6'd32))))))))))))))))))))))))))))))) ;
assign IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d1816 =
(sV1_exp__h1472 == 8'd255 && sV1_sfd__h1473 == 23'd0) ?
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1745 :
((sV1_exp__h1472 == 8'd0 && sV1_sfd__h1473 == 23'd0) ?
64'd0 :
IF_NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_re_ETC___d1814) ;
assign IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d1876 =
(sV1_exp__h1472 == 8'd0 && sV1_sfd__h1473 == 23'd0) ?
64'd0 :
(NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1847[19] ?
64'hFFFFFFFFFFFFFFFF :
IF_NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_re_ETC___d1874) ;
assign IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d1967 =
(sV1_exp__h1472 == 8'd255 && sV1_sfd__h1473 == 23'd0) ?
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1904 :
((sV1_exp__h1472 == 8'd0 && sV1_sfd__h1473 == 23'd0) ?
32'd0 :
IF_NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_re_ETC___d1965) ;
assign IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d2022 =
(sV1_exp__h1472 == 8'd0 && sV1_sfd__h1473 == 23'd0) ?
32'd0 :
(NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1993[19] ?
32'hFFFFFFFF :
IF_NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_re_ETC___d2020) ;
assign IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d2108 =
(sV2_exp__h1597 == 8'd255 && sV2_sfd__h1598[22] ||
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2077) ?
{ requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31],
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d37 } :
(IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2081 ?
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d48 :
IF_NOT_IF_IF_requestR_3_BIT_214_4_THEN_request_ETC___d2106) ;
assign IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d2109 =
(sV1_exp__h1472 == 8'd255 && sV1_sfd__h1473[22]) ?
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d48 :
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d2108 ;
assign IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d2111 =
(sV1_exp__h1472 == 8'd255 && sV1_sfd__h1473[22] &&
sV2_exp__h1597 == 8'd255 &&
sV2_sfd__h1598[22]) ?
64'hFFFFFFFF7FC00000 :
{ 32'hFFFFFFFF,
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d2109 } ;
assign IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d2112 =
(sV2_exp__h1597 == 8'd255 && sV2_sfd__h1598 != 23'd0 &&
!sV2_sfd__h1598[22]) ?
res__h49096 :
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d2111 ;
assign IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d2113 =
(sV1_exp__h1472 == 8'd255 && sV1_sfd__h1473 != 23'd0 &&
!sV1_sfd__h1473[22]) ?
res__h48859 :
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d2112 ;
assign IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d2123 =
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2081 ?
{ requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31],
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d37 } :
IF_NOT_IF_IF_requestR_3_BIT_214_4_THEN_request_ETC___d2122 ;
assign IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d2125 =
(sV2_exp__h1597 == 8'd255 && sV2_sfd__h1598[22]) ?
{ requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31],
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d37 } :
(IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2077 ?
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d48 :
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d2123) ;
assign IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d2126 =
(sV1_exp__h1472 == 8'd255 && sV1_sfd__h1473[22]) ?
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d48 :
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d2125 ;
assign IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d2128 =
(sV1_exp__h1472 == 8'd255 && sV1_sfd__h1473[22] &&
sV2_exp__h1597 == 8'd255 &&
sV2_sfd__h1598[22]) ?
64'hFFFFFFFF7FC00000 :
{ 32'hFFFFFFFF,
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d2126 } ;
assign IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d2129 =
(sV2_exp__h1597 == 8'd255 && sV2_sfd__h1598 != 23'd0 &&
!sV2_sfd__h1598[22]) ?
res__h49096 :
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d2128 ;
assign IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d2130 =
(sV1_exp__h1472 == 8'd255 && sV1_sfd__h1473 != 23'd0 &&
!sV1_sfd__h1473[22]) ?
res__h48859 :
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d2129 ;
assign IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d2206 =
(sV1_exp__h1472 == 8'd0 && sV1_sfd__h1473 == 23'd0) ?
res___1__h57780 :
((sV1_exp__h1472 == 8'd0) ? res___1__h57799 : res__h57815) ;
assign IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d2207 =
(sV1_exp__h1472 == 8'd255 && sV1_sfd__h1473 == 23'd0) ?
res___1__h57770 :
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d2206 ;
assign IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d2339 =
sfd__h28849[31] ?
6'd0 :
(sfd__h28849[30] ?
6'd1 :
(sfd__h28849[29] ?
6'd2 :
(sfd__h28849[28] ?
6'd3 :
(sfd__h28849[27] ?
6'd4 :
(sfd__h28849[26] ?
6'd5 :
(sfd__h28849[25] ?
6'd6 :
(sfd__h28849[24] ?
6'd7 :
(sfd__h28849[23] ?
6'd8 :
(sfd__h28849[22] ?
6'd9 :
(sfd__h28849[21] ?
6'd10 :
(sfd__h28849[20] ?
6'd11 :
(sfd__h28849[19] ?
6'd12 :
(sfd__h28849[18] ?
6'd13 :
(sfd__h28849[17] ?
6'd14 :
(sfd__h28849[16] ?
6'd15 :
(sfd__h28849[15] ?
6'd16 :
(sfd__h28849[14] ?
6'd17 :
(sfd__h28849[13] ?
6'd18 :
(sfd__h28849[12] ?
6'd19 :
(sfd__h28849[11] ?
6'd20 :
(sfd__h28849[10] ?
6'd21 :
(sfd__h28849[9] ?
6'd22 :
(sfd__h28849[8] ?
6'd23 :
(sfd__h28849[7] ?
6'd24 :
(sfd__h28849[6] ?
6'd25 :
(sfd__h28849[5] ?
6'd26 :
(sfd__h28849[4] ?
6'd27 :
(sfd__h28849[3] ?
6'd28 :
(sfd__h28849[2] ?
6'd29 :
(sfd__h28849[1] ?
6'd30 :
(sfd__h28849[0] ?
6'd31 :
6'd55))))))))))))))))))))))))))))))) ;
assign IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d441 =
sfd__h3990[63] ?
7'd0 :
(sfd__h3990[62] ?
7'd1 :
(sfd__h3990[61] ?
7'd2 :
(sfd__h3990[60] ?
7'd3 :
(sfd__h3990[59] ?
7'd4 :
(sfd__h3990[58] ?
7'd5 :
(sfd__h3990[57] ?
7'd6 :
(sfd__h3990[56] ?
7'd7 :
(sfd__h3990[55] ?
7'd8 :
(sfd__h3990[54] ?
7'd9 :
(sfd__h3990[53] ?
7'd10 :
(sfd__h3990[52] ?
7'd11 :
(sfd__h3990[51] ?
7'd12 :
(sfd__h3990[50] ?
7'd13 :
(sfd__h3990[49] ?
7'd14 :
(sfd__h3990[48] ?
7'd15 :
(sfd__h3990[47] ?
7'd16 :
(sfd__h3990[46] ?
7'd17 :
(sfd__h3990[45] ?
7'd18 :
(sfd__h3990[44] ?
7'd19 :
(sfd__h3990[43] ?
7'd20 :
(sfd__h3990[42] ?
7'd21 :
(sfd__h3990[41] ?
7'd22 :
(sfd__h3990[40] ?
7'd23 :
(sfd__h3990[39] ?
7'd24 :
(sfd__h3990[38] ?
7'd25 :
(sfd__h3990[37] ?
7'd26 :
(sfd__h3990[36] ?
7'd27 :
(sfd__h3990[35] ?
7'd28 :
(sfd__h3990[34] ?
7'd29 :
(sfd__h3990[33] ?
7'd30 :
(sfd__h3990[32] ?
7'd31 :
(sfd__h3990[31] ?
7'd32 :
(sfd__h3990[30] ?
7'd33 :
(sfd__h3990[29] ?
7'd34 :
(sfd__h3990[28] ?
7'd35 :
(sfd__h3990[27] ?
7'd36 :
(sfd__h3990[26] ?
7'd37 :
(sfd__h3990[25] ?
7'd38 :
(sfd__h3990[24] ?
7'd39 :
(sfd__h3990[23] ?
7'd40 :
(sfd__h3990[22] ?
7'd41 :
(sfd__h3990[21] ?
7'd42 :
(sfd__h3990[20] ?
7'd43 :
(sfd__h3990[19] ?
7'd44 :
(sfd__h3990[18] ?
7'd45 :
(sfd__h3990[17] ?
7'd46 :
(sfd__h3990[16] ?
7'd47 :
(sfd__h3990[15] ?
7'd48 :
(sfd__h3990[14] ?
7'd49 :
(sfd__h3990[13] ?
7'd50 :
(sfd__h3990[12] ?
7'd51 :
(sfd__h3990[11] ?
7'd52 :
(sfd__h3990[10] ?
7'd53 :
(sfd__h3990[9] ?
7'd54 :
(sfd__h3990[8] ?
7'd55 :
(sfd__h3990[7] ?
7'd56 :
(sfd__h3990[6] ?
7'd57 :
(sfd__h3990[5] ?
7'd58 :
(sfd__h3990[4] ?
7'd59 :
(sfd__h3990[3] ?
7'd60 :
(sfd__h3990[2] ?
7'd61 :
(sfd__h3990[1] ?
7'd62 :
(sfd__h3990[0] ?
7'd63 :
7'd64))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))) ;
assign IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d4613 =
((sV1_exp__h1472 == 8'd0) ?
(sV1_sfd__h1473[22] ?
6'd2 :
(sV1_sfd__h1473[21] ?
6'd3 :
(sV1_sfd__h1473[20] ?
6'd4 :
(sV1_sfd__h1473[19] ?
6'd5 :
(sV1_sfd__h1473[18] ?
6'd6 :
(sV1_sfd__h1473[17] ?
6'd7 :
(sV1_sfd__h1473[16] ?
6'd8 :
(sV1_sfd__h1473[15] ?
6'd9 :
(sV1_sfd__h1473[14] ?
6'd10 :
(sV1_sfd__h1473[13] ?
6'd11 :
(sV1_sfd__h1473[12] ?
6'd12 :
(sV1_sfd__h1473[11] ?
6'd13 :
(sV1_sfd__h1473[10] ?
6'd14 :
(sV1_sfd__h1473[9] ?
6'd15 :
(sV1_sfd__h1473[8] ?
6'd16 :
(sV1_sfd__h1473[7] ?
6'd17 :
(sV1_sfd__h1473[6] ?
6'd18 :
(sV1_sfd__h1473[5] ?
6'd19 :
(sV1_sfd__h1473[4] ?
6'd20 :
(sV1_sfd__h1473[3] ?
6'd21 :
(sV1_sfd__h1473[2] ?
6'd22 :
(sV1_sfd__h1473[1] ?
6'd23 :
(sV1_sfd__h1473[0] ?
6'd24 :
6'd57))))))))))))))))))))))) :
6'd1) -
6'd1 ;
assign IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d5153 =
(sV1_exp__h1472 == 8'd255 && sV1_sfd__h1473 != 23'd0) ?
_theResult___snd_fst_sfd__h169840 :
_theResult___fst_sfd__h212195 ;
assign IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d5188 =
(sV1_exp__h1472 == 8'd0) ?
IF_NOT_3970_MINUS_0_CONCAT_IF_IF_IF_requestR_3_ETC___d5169 :
(SEXT_IF_IF_requestR_3_BIT_214_4_THEN_requestR__ETC___d4685 ?
IF_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reques_ETC___d5186 :
requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31]) ;
assign IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d5189 =
(sV1_exp__h1472 == 8'd255 && sV1_sfd__h1473 != 23'd0 ||
(sV1_exp__h1472 == 8'd255 || sV1_exp__h1472 == 8'd0) &&
sV1_sfd__h1473 == 23'd0) ?
requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31] :
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d5188 ;
assign IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d5224 =
(sV1_exp__h1472 == 8'd0) ?
_3970_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_21_ETC___d4542 &&
!_3970_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_21_ETC___d4543 &&
_0_CONCAT_IF_IF_IF_requestR_3_BIT_214_4_THEN_re_ETC___d5203[4] :
SEXT_IF_IF_requestR_3_BIT_214_4_THEN_requestR__ETC___d4685 &&
SEXT_IF_IF_requestR_3_BIT_214_4_THEN_requestR__ETC___d4686 &&
_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_IF_requestR__ETC___d5220[4] ;
assign IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d5227 =
(sV1_exp__h1472 == 8'd255 && sV1_sfd__h1473 != 23'd0) ?
sV1_exp__h1472 == 8'd255 && sV1_sfd__h1473 != 23'd0 &&
!sV1_sfd__h1473[22] :
(sV1_exp__h1472 != 8'd255 || sV1_sfd__h1473 != 23'd0) &&
(sV1_exp__h1472 != 8'd0 || sV1_sfd__h1473 != 23'd0) &&
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d5224 ;
assign IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d5234 =
(sV1_exp__h1472 == 8'd0) ?
_3970_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_21_ETC___d4542 &&
!_3970_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_21_ETC___d4543 &&
_0_CONCAT_IF_IF_IF_requestR_3_BIT_214_4_THEN_re_ETC___d5203[3] :
SEXT_IF_IF_requestR_3_BIT_214_4_THEN_requestR__ETC___d4685 &&
SEXT_IF_IF_requestR_3_BIT_214_4_THEN_requestR__ETC___d4686 &&
_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_IF_requestR__ETC___d5220[3] ;
assign IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d5248 =
(sV1_exp__h1472 == 8'd0) ?
!_3970_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_21_ETC___d4542 ||
!_3970_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_21_ETC___d4543 &&
_0_CONCAT_IF_IF_IF_requestR_3_BIT_214_4_THEN_re_ETC___d5203[2] :
!SEXT_IF_IF_requestR_3_BIT_214_4_THEN_requestR__ETC___d4685 ||
IF_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reques_ETC___d5246 ;
assign IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d5260 =
(sV1_exp__h1472 == 8'd0) ?
_3970_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_21_ETC___d4542 &&
(_3970_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_21_ETC___d4543 ||
_0_CONCAT_IF_IF_IF_requestR_3_BIT_214_4_THEN_re_ETC___d5203[1]) :
SEXT_IF_IF_requestR_3_BIT_214_4_THEN_requestR__ETC___d4685 &&
IF_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reques_ETC___d5258 ;
assign IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d5272 =
(sV1_exp__h1472 == 8'd0) ?
!_3970_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_21_ETC___d4542 ||
!_3970_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_21_ETC___d4543 &&
_0_CONCAT_IF_IF_IF_requestR_3_BIT_214_4_THEN_re_ETC___d5203[0] :
!SEXT_IF_IF_requestR_3_BIT_214_4_THEN_requestR__ETC___d4685 ||
IF_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reques_ETC___d5270 ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1439 =
(requestR_BITS_191_TO_128__q1[31:0] == 32'd0 ||
!sfd__h28849[31] && !sfd__h28849[30] && !sfd__h28849[29] &&
!sfd__h28849[28] &&
!sfd__h28849[27] &&
!sfd__h28849[26] &&
!sfd__h28849[25] &&
!sfd__h28849[24] &&
!sfd__h28849[23] &&
!sfd__h28849[22] &&
!sfd__h28849[21] &&
!sfd__h28849[20] &&
!sfd__h28849[19] &&
!sfd__h28849[18] &&
!sfd__h28849[17] &&
!sfd__h28849[16] &&
!sfd__h28849[15] &&
!sfd__h28849[14] &&
!sfd__h28849[13] &&
!sfd__h28849[12] &&
!sfd__h28849[11] &&
!sfd__h28849[10] &&
!sfd__h28849[9] &&
!sfd__h28849[8] &&
!sfd__h28849[7] &&
!sfd__h28849[6] &&
!sfd__h28849[5] &&
!sfd__h28849[4] &&
!sfd__h28849[3] &&
!sfd__h28849[2] &&
!sfd__h28849[1] &&
!sfd__h28849[0]) ?
8'd0 :
_theResult___snd_fst_exp__h35543 ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1520 =
(sfd__h28849[31] || sfd__h28849[30] || sfd__h28849[29] ||
sfd__h28849[28] ||
sfd__h28849[27] ||
sfd__h28849[26] ||
sfd__h28849[25] ||
sfd__h28849[24] ||
sfd__h28849[23] ||
sfd__h28849[22] ||
sfd__h28849[21] ||
sfd__h28849[20] ||
sfd__h28849[19] ||
sfd__h28849[18] ||
sfd__h28849[17] ||
sfd__h28849[16] ||
sfd__h28849[15] ||
sfd__h28849[14] ||
sfd__h28849[13] ||
sfd__h28849[12] ||
sfd__h28849[11] ||
sfd__h28849[10] ||
sfd__h28849[9] ||
sfd__h28849[8] ||
sfd__h28849[7] ||
sfd__h28849[6] ||
sfd__h28849[5] ||
sfd__h28849[4] ||
sfd__h28849[3] ||
sfd__h28849[2] ||
sfd__h28849[1] ||
sfd__h28849[0]) &&
(!_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d1322 ||
!_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d1324 &&
!_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d1327 &&
_theResult___fst_exp__h35534 == 8'd255 &&
_theResult___fst_sfd__h35535 == 23'd0) ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1523 =
(sfd__h28849[31] || sfd__h28849[30] || sfd__h28849[29] ||
sfd__h28849[28] ||
sfd__h28849[27] ||
sfd__h28849[26] ||
sfd__h28849[25] ||
sfd__h28849[24] ||
sfd__h28849[23] ||
sfd__h28849[22] ||
sfd__h28849[21] ||
sfd__h28849[20] ||
sfd__h28849[19] ||
sfd__h28849[18] ||
sfd__h28849[17] ||
sfd__h28849[16] ||
sfd__h28849[15] ||
sfd__h28849[14] ||
sfd__h28849[13] ||
sfd__h28849[12] ||
sfd__h28849[11] ||
sfd__h28849[10] ||
sfd__h28849[9] ||
sfd__h28849[8] ||
sfd__h28849[7] ||
sfd__h28849[6] ||
sfd__h28849[5] ||
sfd__h28849[4] ||
sfd__h28849[3] ||
sfd__h28849[2] ||
sfd__h28849[1] ||
sfd__h28849[0]) &&
_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d1322 &&
_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d1324 ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1532 =
(sfd__h28849[31] || sfd__h28849[30] || sfd__h28849[29] ||
sfd__h28849[28] ||
sfd__h28849[27] ||
sfd__h28849[26] ||
sfd__h28849[25] ||
sfd__h28849[24] ||
sfd__h28849[23] ||
sfd__h28849[22] ||
sfd__h28849[21] ||
sfd__h28849[20] ||
sfd__h28849[19] ||
sfd__h28849[18] ||
sfd__h28849[17] ||
sfd__h28849[16] ||
sfd__h28849[15] ||
sfd__h28849[14] ||
sfd__h28849[13] ||
sfd__h28849[12] ||
sfd__h28849[11] ||
sfd__h28849[10] ||
sfd__h28849[9] ||
sfd__h28849[8] ||
sfd__h28849[7] ||
sfd__h28849[6] ||
sfd__h28849[5] ||
sfd__h28849[4] ||
sfd__h28849[3] ||
sfd__h28849[2] ||
sfd__h28849[1] ||
sfd__h28849[0]) &&
_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d1322 &&
!_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d1324 &&
IF_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_2_ETC___d1529 ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1574 =
requestR_BITS_191_TO_128__q1[31] ?
6'd0 :
(requestR_BITS_191_TO_128__q1[30] ?
6'd1 :
(requestR_BITS_191_TO_128__q1[29] ?
6'd2 :
(requestR_BITS_191_TO_128__q1[28] ?
6'd3 :
(requestR_BITS_191_TO_128__q1[27] ?
6'd4 :
(requestR_BITS_191_TO_128__q1[26] ?
6'd5 :
(requestR_BITS_191_TO_128__q1[25] ?
6'd6 :
(requestR_BITS_191_TO_128__q1[24] ?
6'd7 :
(requestR_BITS_191_TO_128__q1[23] ?
6'd8 :
(requestR_BITS_191_TO_128__q1[22] ?
6'd9 :
(requestR_BITS_191_TO_128__q1[21] ?
6'd10 :
(requestR_BITS_191_TO_128__q1[20] ?
6'd11 :
(requestR_BITS_191_TO_128__q1[19] ?
6'd12 :
(requestR_BITS_191_TO_128__q1[18] ?
6'd13 :
(requestR_BITS_191_TO_128__q1[17] ?
6'd14 :
(requestR_BITS_191_TO_128__q1[16] ?
6'd15 :
(requestR_BITS_191_TO_128__q1[15] ?
6'd16 :
(requestR_BITS_191_TO_128__q1[14] ?
6'd17 :
(requestR_BITS_191_TO_128__q1[13] ?
6'd18 :
(requestR_BITS_191_TO_128__q1[12] ?
6'd19 :
(requestR_BITS_191_TO_128__q1[11] ?
6'd20 :
(requestR_BITS_191_TO_128__q1[10] ?
6'd21 :
(requestR_BITS_191_TO_128__q1[9] ?
6'd22 :
(requestR_BITS_191_TO_128__q1[8] ?
6'd23 :
(requestR_BITS_191_TO_128__q1[7] ?
6'd24 :
(requestR_BITS_191_TO_128__q1[6] ?
6'd25 :
(requestR_BITS_191_TO_128__q1[5] ?
6'd26 :
(requestR_BITS_191_TO_128__q1[4] ?
6'd27 :
(requestR_BITS_191_TO_128__q1[3] ?
6'd28 :
(requestR_BITS_191_TO_128__q1[2] ?
6'd29 :
(requestR_BITS_191_TO_128__q1[1] ?
6'd30 :
(requestR_BITS_191_TO_128__q1[0] ?
6'd31 :
6'd32))))))))))))))))))))))))))))))) ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1745 =
(requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31]) ?
64'h8000000000000000 :
64'h7FFFFFFFFFFFFFFF ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1748 =
sV1_exp__h1472 - 8'd127 ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1757 =
(requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31]) ?
-b__h43158 :
b__h43158 ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1774 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
((guard__h43091 == 2'b10) ?
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1757[24] :
guard__h43091 == 2'b11) :
((requestR[194:192] == 3'h3) ?
guard__h43091 != 2'd0 :
requestR[194:192] == 3'h1 &&
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1757[88] &&
guard__h43091 != 2'd0) ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1806 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
((guard__h43869 == 2'b10) ?
x__h44058[25] :
guard__h43869 == 2'b11) :
((requestR[194:192] == 3'h3) ?
guard__h43869 != 2'd0 :
requestR[194:192] == 3'h1 && x__h44058[88] &&
guard__h43869 != 2'd0) ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1868 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
((guard__h45193 == 2'b10) ?
x__h45414[25] :
guard__h45193 == 2'b11) :
requestR[194:192] == 3'h3 && guard__h45193 != 2'd0 ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1878 =
(requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31]) ?
64'd0 :
((sV1_exp__h1472 == 8'd255 && sV1_sfd__h1473 == 23'd0) ?
64'hFFFFFFFFFFFFFFFF :
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d1876) ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1885 =
sV1_exp__h1472 == 8'd255 && sV1_sfd__h1473 != 23'd0 ||
sV1_exp__h1472 == 8'd255 && sV1_sfd__h1473 == 23'd0 ||
(sV1_exp__h1472 != 8'd0 || sV1_sfd__h1473 != 23'd0) &&
(NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1847[19] ||
NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1849 &&
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1868 &&
x__h45414[88:25] == 64'hFFFFFFFFFFFFFFFF) ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1896 =
{ IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1885,
3'd0,
(sV1_exp__h1472 != 8'd255 || sV1_sfd__h1473 == 23'd0) &&
(sV1_exp__h1472 != 8'd255 || sV1_sfd__h1473 != 23'd0) &&
NOT_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_ETC___d1890 } ==
5'd0 ||
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1885 ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1904 =
(requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31]) ?
32'h80000000 :
32'h7FFFFFFF ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1908 =
(requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31]) ?
-b__h46021 :
b__h46021 ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1925 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
((guard__h45954 == 2'b10) ?
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1908[24] :
guard__h45954 == 2'b11) :
((requestR[194:192] == 3'h3) ?
guard__h45954 != 2'd0 :
requestR[194:192] == 3'h1 &&
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1908[56] &&
guard__h45954 != 2'd0) ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1957 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
((guard__h46508 == 2'b10) ?
x__h46697[25] :
guard__h46508 == 2'b11) :
((requestR[194:192] == 3'h3) ?
guard__h46508 != 2'd0 :
requestR[194:192] == 3'h1 && x__h46697[56] &&
guard__h46508 != 2'd0) ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2014 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
((guard__h47594 == 2'b10) ?
x__h47815[25] :
guard__h47594 == 2'b11) :
requestR[194:192] == 3'h3 && guard__h47594 != 2'd0 ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2024 =
(requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31]) ?
32'd0 :
((sV1_exp__h1472 == 8'd255 && sV1_sfd__h1473 == 23'd0) ?
32'hFFFFFFFF :
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d2022) ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2032 =
sV1_exp__h1472 == 8'd255 && sV1_sfd__h1473 != 23'd0 ||
sV1_exp__h1472 == 8'd255 && sV1_sfd__h1473 == 23'd0 ||
(sV1_exp__h1472 != 8'd0 || sV1_sfd__h1473 != 23'd0) &&
(NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1993[19] ||
NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1995 &&
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2014 &&
x__h47815[56:25] == 32'hFFFFFFFF) ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2043 =
{ IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2032,
3'd0,
(sV1_exp__h1472 != 8'd255 || sV1_sfd__h1473 == 23'd0) &&
(sV1_exp__h1472 != 8'd255 || sV1_sfd__h1473 != 23'd0) &&
NOT_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_ETC___d2037 } ==
5'd0 ||
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2032 ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2067 =
sV1_exp__h1472 == 8'd255 && sV1_sfd__h1473 != 23'd0 &&
!sV1_sfd__h1473[22] &&
sV2_exp__h1597 == 8'd255 &&
sV2_sfd__h1598 != 23'd0 &&
!sV2_sfd__h1598[22] ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2077 =
sV1_exp__h1472 == 8'd0 && sV1_sfd__h1473 == 23'd0 &&
requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31] &&
sV2_exp__h1597 == 8'd0 &&
sV2_sfd__h1598 == 23'd0 &&
(requestR_BITS_127_TO_64__q3[63:32] != 32'hFFFFFFFF ||
!requestR_BITS_127_TO_64__q3[31]) ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2081 =
sV2_exp__h1597 == 8'd0 && sV2_sfd__h1598 == 23'd0 &&
requestR_BITS_127_TO_64__q3[63:32] == 32'hFFFFFFFF &&
requestR_BITS_127_TO_64__q3[31] &&
sV1_exp__h1472 == 8'd0 &&
sV1_sfd__h1473 == 23'd0 &&
(requestR_BITS_191_TO_128__q1[63:32] != 32'hFFFFFFFF ||
!requestR_BITS_191_TO_128__q1[31]) ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2090 =
sV1_exp__h1472 < sV2_exp__h1597 ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2091 =
sV1_exp__h1472 == sV2_exp__h1597 ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2092 =
sV1_sfd__h1473 < sV2_sfd__h1598 ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2095 =
sV1_exp__h1472 <= sV2_exp__h1597 ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2097 =
sV1_sfd__h1473 <= sV2_sfd__h1598 ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2115 =
sV1_exp__h1472 == 8'd255 && sV1_sfd__h1473 != 23'd0 &&
!sV1_sfd__h1473[22] ||
sV2_exp__h1597 == 8'd255 && sV2_sfd__h1598 != 23'd0 &&
!sV2_sfd__h1598[22] ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2156 =
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2115 ||
sV1_exp__h1472 == 8'd255 && sV1_sfd__h1473[22] ||
sV2_exp__h1597 == 8'd255 && sV2_sfd__h1598[22] ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2167 =
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2095 &&
(!IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2091 ||
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2097) &&
!IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2090 &&
(!IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2091 ||
!IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2092) ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2171 =
sV1_exp__h1472 == 8'd0 && sV1_sfd__h1473 == 23'd0 &&
sV2_exp__h1597 == 8'd0 &&
sV2_sfd__h1598 == 23'd0 ||
(requestR_BITS_191_TO_128__q1[63:32] != 32'hFFFFFFFF ||
!requestR_BITS_191_TO_128__q1[31] ||
requestR_BITS_127_TO_64__q3[63:32] == 32'hFFFFFFFF &&
requestR_BITS_127_TO_64__q3[31]) &&
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d2169 ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2496 =
(requestR_BITS_191_TO_128__q1[31:0] == 32'd0 ||
!_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d2343 ||
_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d2345) ?
52'd0 :
_theResult___snd_fst_sfd__h70875 ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2555 =
requestR_BITS_191_TO_128__q1[31] ?
6'd0 :
(requestR_BITS_191_TO_128__q1[30] ?
6'd1 :
(requestR_BITS_191_TO_128__q1[29] ?
6'd2 :
(requestR_BITS_191_TO_128__q1[28] ?
6'd3 :
(requestR_BITS_191_TO_128__q1[27] ?
6'd4 :
(requestR_BITS_191_TO_128__q1[26] ?
6'd5 :
(requestR_BITS_191_TO_128__q1[25] ?
6'd6 :
(requestR_BITS_191_TO_128__q1[24] ?
6'd7 :
(requestR_BITS_191_TO_128__q1[23] ?
6'd8 :
(requestR_BITS_191_TO_128__q1[22] ?
6'd9 :
(requestR_BITS_191_TO_128__q1[21] ?
6'd10 :
(requestR_BITS_191_TO_128__q1[20] ?
6'd11 :
(requestR_BITS_191_TO_128__q1[19] ?
6'd12 :
(requestR_BITS_191_TO_128__q1[18] ?
6'd13 :
(requestR_BITS_191_TO_128__q1[17] ?
6'd14 :
(requestR_BITS_191_TO_128__q1[16] ?
6'd15 :
(requestR_BITS_191_TO_128__q1[15] ?
6'd16 :
(requestR_BITS_191_TO_128__q1[14] ?
6'd17 :
(requestR_BITS_191_TO_128__q1[13] ?
6'd18 :
(requestR_BITS_191_TO_128__q1[12] ?
6'd19 :
(requestR_BITS_191_TO_128__q1[11] ?
6'd20 :
(requestR_BITS_191_TO_128__q1[10] ?
6'd21 :
(requestR_BITS_191_TO_128__q1[9] ?
6'd22 :
(requestR_BITS_191_TO_128__q1[8] ?
6'd23 :
(requestR_BITS_191_TO_128__q1[7] ?
6'd24 :
(requestR_BITS_191_TO_128__q1[6] ?
6'd25 :
(requestR_BITS_191_TO_128__q1[5] ?
6'd26 :
(requestR_BITS_191_TO_128__q1[4] ?
6'd27 :
(requestR_BITS_191_TO_128__q1[3] ?
6'd28 :
(requestR_BITS_191_TO_128__q1[2] ?
6'd29 :
(requestR_BITS_191_TO_128__q1[1] ?
6'd30 :
(requestR_BITS_191_TO_128__q1[0] ?
6'd31 :
6'd55))))))))))))))))))))))))))))))) ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2680 =
(requestR_BITS_191_TO_128__q1[31:0] == 32'd0 ||
!_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d2559 ||
_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d2560) ?
52'd0 :
_theResult___snd_fst_sfd__h81820 ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2719 =
requestR_BITS_191_TO_128__q1[63] ? 32'h80000000 : 32'h7FFFFFFF ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2731 =
requestR_BITS_191_TO_128__q1[63] ? -b__h82525 : b__h82525 ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2748 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
((guard__h82458 == 2'b10) ?
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2731[53] :
guard__h82458 == 2'b11) :
((requestR[194:192] == 3'h3) ?
guard__h82458 != 2'd0 :
requestR[194:192] == 3'h1 &&
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2731[85] &&
guard__h82458 != 2'd0) ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2780 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
((guard__h83012 == 2'b10) ?
x__h83201[54] :
guard__h83012 == 2'b11) :
((requestR[194:192] == 3'h3) ?
guard__h83012 != 2'd0 :
requestR[194:192] == 3'h1 && x__h83201[85] &&
guard__h83012 != 2'd0) ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2790 =
(requestR_BITS_191_TO_128__q1[62:52] == 11'd2047 &&
requestR_BITS_191_TO_128__q1[51:0] == 52'd0) ?
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2719 :
((requestR_BITS_191_TO_128__q1[62:52] == 11'd0 &&
requestR_BITS_191_TO_128__q1[51:0] == 52'd0) ?
32'd0 :
IF_NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d2788) ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2843 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
((guard__h84098 == 2'b10) ?
x__h84319[54] :
guard__h84098 == 2'b11) :
requestR[194:192] == 3'h3 && guard__h84098 != 2'd0 ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2851 =
(requestR_BITS_191_TO_128__q1[62:52] == 11'd0 &&
requestR_BITS_191_TO_128__q1[51:0] == 52'd0) ?
32'd0 :
(NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2822[23] ?
32'hFFFFFFFF :
IF_NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d2849) ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2996 =
(requestR[191:128] == 64'd0 ||
!sfd__h3990[63] && !sfd__h3990[62] && !sfd__h3990[61] &&
!sfd__h3990[60] &&
!sfd__h3990[59] &&
!sfd__h3990[58] &&
!sfd__h3990[57] &&
!sfd__h3990[56] &&
!sfd__h3990[55] &&
!sfd__h3990[54] &&
!sfd__h3990[53] &&
!sfd__h3990[52] &&
!sfd__h3990[51] &&
!sfd__h3990[50] &&
!sfd__h3990[49] &&
!sfd__h3990[48] &&
!sfd__h3990[47] &&
!sfd__h3990[46] &&
!sfd__h3990[45] &&
!sfd__h3990[44] &&
!sfd__h3990[43] &&
!sfd__h3990[42] &&
!sfd__h3990[41] &&
!sfd__h3990[40] &&
!sfd__h3990[39] &&
!sfd__h3990[38] &&
!sfd__h3990[37] &&
!sfd__h3990[36] &&
!sfd__h3990[35] &&
!sfd__h3990[34] &&
!sfd__h3990[33] &&
!sfd__h3990[32] &&
!sfd__h3990[31] &&
!sfd__h3990[30] &&
!sfd__h3990[29] &&
!sfd__h3990[28] &&
!sfd__h3990[27] &&
!sfd__h3990[26] &&
!sfd__h3990[25] &&
!sfd__h3990[24] &&
!sfd__h3990[23] &&
!sfd__h3990[22] &&
!sfd__h3990[21] &&
!sfd__h3990[20] &&
!sfd__h3990[19] &&
!sfd__h3990[18] &&
!sfd__h3990[17] &&
!sfd__h3990[16] &&
!sfd__h3990[15] &&
!sfd__h3990[14] &&
!sfd__h3990[13] &&
!sfd__h3990[12] &&
!sfd__h3990[11] &&
!sfd__h3990[10] &&
!sfd__h3990[9] &&
!sfd__h3990[8] &&
!sfd__h3990[7] &&
!sfd__h3990[6] &&
!sfd__h3990[5] &&
!sfd__h3990[4] &&
!sfd__h3990[3] &&
!sfd__h3990[2] &&
!sfd__h3990[1] &&
!sfd__h3990[0]) ?
11'd0 :
_theResult___snd_fst_exp__h97202 ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3045 =
(sfd__h3990[63] || sfd__h3990[62] || sfd__h3990[61] ||
sfd__h3990[60] ||
sfd__h3990[59] ||
sfd__h3990[58] ||
sfd__h3990[57] ||
sfd__h3990[56] ||
sfd__h3990[55] ||
sfd__h3990[54] ||
sfd__h3990[53] ||
sfd__h3990[52] ||
sfd__h3990[51] ||
sfd__h3990[50] ||
sfd__h3990[49] ||
sfd__h3990[48] ||
sfd__h3990[47] ||
sfd__h3990[46] ||
sfd__h3990[45] ||
sfd__h3990[44] ||
sfd__h3990[43] ||
sfd__h3990[42] ||
sfd__h3990[41] ||
sfd__h3990[40] ||
sfd__h3990[39] ||
sfd__h3990[38] ||
sfd__h3990[37] ||
sfd__h3990[36] ||
sfd__h3990[35] ||
sfd__h3990[34] ||
sfd__h3990[33] ||
sfd__h3990[32] ||
sfd__h3990[31] ||
sfd__h3990[30] ||
sfd__h3990[29] ||
sfd__h3990[28] ||
sfd__h3990[27] ||
sfd__h3990[26] ||
sfd__h3990[25] ||
sfd__h3990[24] ||
sfd__h3990[23] ||
sfd__h3990[22] ||
sfd__h3990[21] ||
sfd__h3990[20] ||
sfd__h3990[19] ||
sfd__h3990[18] ||
sfd__h3990[17] ||
sfd__h3990[16] ||
sfd__h3990[15] ||
sfd__h3990[14] ||
sfd__h3990[13] ||
sfd__h3990[12] ||
sfd__h3990[11] ||
sfd__h3990[10] ||
sfd__h3990[9] ||
sfd__h3990[8] ||
sfd__h3990[7] ||
sfd__h3990[6] ||
sfd__h3990[5] ||
sfd__h3990[4] ||
sfd__h3990[3] ||
sfd__h3990[2] ||
sfd__h3990[1] ||
sfd__h3990[0]) &&
(!_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d2883 ||
!_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d2885 &&
!_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d2888 &&
_theResult___fst_exp__h97193 == 11'd2047 &&
_theResult___fst_sfd__h97194 == 52'd0) ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3048 =
(sfd__h3990[63] || sfd__h3990[62] || sfd__h3990[61] ||
sfd__h3990[60] ||
sfd__h3990[59] ||
sfd__h3990[58] ||
sfd__h3990[57] ||
sfd__h3990[56] ||
sfd__h3990[55] ||
sfd__h3990[54] ||
sfd__h3990[53] ||
sfd__h3990[52] ||
sfd__h3990[51] ||
sfd__h3990[50] ||
sfd__h3990[49] ||
sfd__h3990[48] ||
sfd__h3990[47] ||
sfd__h3990[46] ||
sfd__h3990[45] ||
sfd__h3990[44] ||
sfd__h3990[43] ||
sfd__h3990[42] ||
sfd__h3990[41] ||
sfd__h3990[40] ||
sfd__h3990[39] ||
sfd__h3990[38] ||
sfd__h3990[37] ||
sfd__h3990[36] ||
sfd__h3990[35] ||
sfd__h3990[34] ||
sfd__h3990[33] ||
sfd__h3990[32] ||
sfd__h3990[31] ||
sfd__h3990[30] ||
sfd__h3990[29] ||
sfd__h3990[28] ||
sfd__h3990[27] ||
sfd__h3990[26] ||
sfd__h3990[25] ||
sfd__h3990[24] ||
sfd__h3990[23] ||
sfd__h3990[22] ||
sfd__h3990[21] ||
sfd__h3990[20] ||
sfd__h3990[19] ||
sfd__h3990[18] ||
sfd__h3990[17] ||
sfd__h3990[16] ||
sfd__h3990[15] ||
sfd__h3990[14] ||
sfd__h3990[13] ||
sfd__h3990[12] ||
sfd__h3990[11] ||
sfd__h3990[10] ||
sfd__h3990[9] ||
sfd__h3990[8] ||
sfd__h3990[7] ||
sfd__h3990[6] ||
sfd__h3990[5] ||
sfd__h3990[4] ||
sfd__h3990[3] ||
sfd__h3990[2] ||
sfd__h3990[1] ||
sfd__h3990[0]) &&
_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d2883 &&
_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d2885 ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3057 =
(sfd__h3990[63] || sfd__h3990[62] || sfd__h3990[61] ||
sfd__h3990[60] ||
sfd__h3990[59] ||
sfd__h3990[58] ||
sfd__h3990[57] ||
sfd__h3990[56] ||
sfd__h3990[55] ||
sfd__h3990[54] ||
sfd__h3990[53] ||
sfd__h3990[52] ||
sfd__h3990[51] ||
sfd__h3990[50] ||
sfd__h3990[49] ||
sfd__h3990[48] ||
sfd__h3990[47] ||
sfd__h3990[46] ||
sfd__h3990[45] ||
sfd__h3990[44] ||
sfd__h3990[43] ||
sfd__h3990[42] ||
sfd__h3990[41] ||
sfd__h3990[40] ||
sfd__h3990[39] ||
sfd__h3990[38] ||
sfd__h3990[37] ||
sfd__h3990[36] ||
sfd__h3990[35] ||
sfd__h3990[34] ||
sfd__h3990[33] ||
sfd__h3990[32] ||
sfd__h3990[31] ||
sfd__h3990[30] ||
sfd__h3990[29] ||
sfd__h3990[28] ||
sfd__h3990[27] ||
sfd__h3990[26] ||
sfd__h3990[25] ||
sfd__h3990[24] ||
sfd__h3990[23] ||
sfd__h3990[22] ||
sfd__h3990[21] ||
sfd__h3990[20] ||
sfd__h3990[19] ||
sfd__h3990[18] ||
sfd__h3990[17] ||
sfd__h3990[16] ||
sfd__h3990[15] ||
sfd__h3990[14] ||
sfd__h3990[13] ||
sfd__h3990[12] ||
sfd__h3990[11] ||
sfd__h3990[10] ||
sfd__h3990[9] ||
sfd__h3990[8] ||
sfd__h3990[7] ||
sfd__h3990[6] ||
sfd__h3990[5] ||
sfd__h3990[4] ||
sfd__h3990[3] ||
sfd__h3990[2] ||
sfd__h3990[1] ||
sfd__h3990[0]) &&
_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d2883 &&
!_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d2885 &&
IF_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_2_ETC___d3054 ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3220 =
requestR_BITS_191_TO_128__q1[63] ?
64'h8000000000000000 :
64'h7FFFFFFFFFFFFFFF ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3224 =
requestR_BITS_191_TO_128__q1[63] ? -b__h110422 : b__h110422 ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3241 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
((guard__h110355 == 2'b10) ?
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3224[53] :
guard__h110355 == 2'b11) :
((requestR[194:192] == 3'h3) ?
guard__h110355 != 2'd0 :
requestR[194:192] == 3'h1 &&
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3224[117] &&
guard__h110355 != 2'd0) ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3273 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
((guard__h111133 == 2'b10) ?
x__h111322[54] :
guard__h111133 == 2'b11) :
((requestR[194:192] == 3'h3) ?
guard__h111133 != 2'd0 :
requestR[194:192] == 3'h1 && x__h111322[117] &&
guard__h111133 != 2'd0) ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3283 =
(requestR_BITS_191_TO_128__q1[62:52] == 11'd2047 &&
requestR_BITS_191_TO_128__q1[51:0] == 52'd0) ?
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3220 :
((requestR_BITS_191_TO_128__q1[62:52] == 11'd0 &&
requestR_BITS_191_TO_128__q1[51:0] == 52'd0) ?
64'd0 :
IF_NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d3281) ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3329 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
((guard__h112440 == 2'b10) ?
x__h112661[54] :
guard__h112440 == 2'b11) :
requestR[194:192] == 3'h3 && guard__h112440 != 2'd0 ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3337 =
(requestR_BITS_191_TO_128__q1[62:52] == 11'd0 &&
requestR_BITS_191_TO_128__q1[51:0] == 52'd0) ?
64'd0 :
(NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d3308[23] ?
64'hFFFFFFFFFFFFFFFF :
IF_NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d3335) ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d37 =
(requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF) ?
requestR_BITS_191_TO_128__q1[30:0] :
31'h7FC00000 ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3776 =
((requestR_BITS_191_TO_128__q1[62:52] == 11'd0) ?
(requestR_BITS_191_TO_128__q1[51] ?
6'd2 :
(requestR_BITS_191_TO_128__q1[50] ?
6'd3 :
(requestR_BITS_191_TO_128__q1[49] ?
6'd4 :
(requestR_BITS_191_TO_128__q1[48] ?
6'd5 :
(requestR_BITS_191_TO_128__q1[47] ?
6'd6 :
(requestR_BITS_191_TO_128__q1[46] ?
6'd7 :
(requestR_BITS_191_TO_128__q1[45] ?
6'd8 :
(requestR_BITS_191_TO_128__q1[44] ?
6'd9 :
(requestR_BITS_191_TO_128__q1[43] ?
6'd10 :
(requestR_BITS_191_TO_128__q1[42] ?
6'd11 :
(requestR_BITS_191_TO_128__q1[41] ?
6'd12 :
(requestR_BITS_191_TO_128__q1[40] ?
6'd13 :
(requestR_BITS_191_TO_128__q1[39] ?
6'd14 :
(requestR_BITS_191_TO_128__q1[38] ?
6'd15 :
(requestR_BITS_191_TO_128__q1[37] ?
6'd16 :
(requestR_BITS_191_TO_128__q1[36] ?
6'd17 :
(requestR_BITS_191_TO_128__q1[35] ?
6'd18 :
(requestR_BITS_191_TO_128__q1[34] ?
6'd19 :
(requestR_BITS_191_TO_128__q1[33] ?
6'd20 :
(requestR_BITS_191_TO_128__q1[32] ?
6'd21 :
(requestR_BITS_191_TO_128__q1[31] ?
6'd22 :
(requestR_BITS_191_TO_128__q1[30] ?
6'd23 :
(requestR_BITS_191_TO_128__q1[29] ?
6'd24 :
(requestR_BITS_191_TO_128__q1[28] ?
6'd25 :
(requestR_BITS_191_TO_128__q1[27] ?
6'd26 :
(requestR_BITS_191_TO_128__q1[26] ?
6'd27 :
(requestR_BITS_191_TO_128__q1[25] ?
6'd28 :
(requestR_BITS_191_TO_128__q1[24] ?
6'd29 :
(requestR_BITS_191_TO_128__q1[23] ?
6'd30 :
(requestR_BITS_191_TO_128__q1[22] ?
6'd31 :
(requestR_BITS_191_TO_128__q1[21] ?
6'd32 :
(requestR_BITS_191_TO_128__q1[20] ?
6'd33 :
(requestR_BITS_191_TO_128__q1[19] ?
6'd34 :
(requestR_BITS_191_TO_128__q1[18] ?
6'd35 :
(requestR_BITS_191_TO_128__q1[17] ?
6'd36 :
(requestR_BITS_191_TO_128__q1[16] ?
6'd37 :
(requestR_BITS_191_TO_128__q1[15] ?
6'd38 :
(requestR_BITS_191_TO_128__q1[14] ?
6'd39 :
(requestR_BITS_191_TO_128__q1[13] ?
6'd40 :
(requestR_BITS_191_TO_128__q1[12] ?
6'd41 :
(requestR_BITS_191_TO_128__q1[11] ?
6'd42 :
(requestR_BITS_191_TO_128__q1[10] ?
6'd43 :
(requestR_BITS_191_TO_128__q1[9] ?
6'd44 :
(requestR_BITS_191_TO_128__q1[8] ?
6'd45 :
(requestR_BITS_191_TO_128__q1[7] ?
6'd46 :
(requestR_BITS_191_TO_128__q1[6] ?
6'd47 :
(requestR_BITS_191_TO_128__q1[5] ?
6'd48 :
(requestR_BITS_191_TO_128__q1[4] ?
6'd49 :
(requestR_BITS_191_TO_128__q1[3] ?
6'd50 :
(requestR_BITS_191_TO_128__q1[2] ?
6'd51 :
(requestR_BITS_191_TO_128__q1[1] ?
6'd52 :
(requestR_BITS_191_TO_128__q1[0] ?
6'd53 :
6'd57)))))))))))))))))))))))))))))))))))))))))))))))))))) :
6'd1) -
6'd1 ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4338 =
(requestR_BITS_191_TO_128__q1[62:52] == 11'd2047 &&
requestR_BITS_191_TO_128__q1[51:0] != 52'd0) ?
_theResult___snd_fst_sfd__h117207 :
_theResult___fst_sfd__h166273 ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4378 =
(requestR_BITS_191_TO_128__q1[62:52] == 11'd0) ?
(_3074_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_ETC___d3421 ?
IF_3074_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_21_ETC___d4358 :
requestR_BITS_191_TO_128__q1[63]) :
(SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_3_B_ETC___d3852 ?
IF_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR__ETC___d4376 :
requestR_BITS_191_TO_128__q1[63]) ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4429 =
(requestR_BITS_191_TO_128__q1[62:52] == 11'd0) ?
_3074_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_ETC___d4411 :
SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_3_B_ETC___d3852 &&
SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_3_B_ETC___d3853 &&
_0_CONCAT_IF_IF_3970_MINUS_SEXT_IF_requestR_3_B_ETC___d4425[4] ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4440 =
(requestR_BITS_191_TO_128__q1[62:52] == 11'd0) ?
_3074_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_ETC___d4436 :
SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_3_B_ETC___d3852 &&
SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_3_B_ETC___d3853 &&
_0_CONCAT_IF_IF_3970_MINUS_SEXT_IF_requestR_3_B_ETC___d4425[3] ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4456 =
(requestR_BITS_191_TO_128__q1[62:52] == 11'd0) ?
NOT_3074_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_2_ETC___d4448 :
!SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_3_B_ETC___d3852 ||
IF_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR__ETC___d4454 ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4469 =
(requestR_BITS_191_TO_128__q1[62:52] == 11'd0) ?
_3074_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_ETC___d4463 :
SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_3_B_ETC___d3852 &&
IF_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR__ETC___d4467 ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4482 =
(requestR_BITS_191_TO_128__q1[62:52] == 11'd0) ?
NOT_3074_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_2_ETC___d4476 :
!SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_3_B_ETC___d3852 ||
IF_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR__ETC___d4480 ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4617 =
sV1_exp__h1472 == 8'd0 && !sV1_sfd__h1473[22] &&
!sV1_sfd__h1473[21] &&
!sV1_sfd__h1473[20] &&
!sV1_sfd__h1473[19] &&
!sV1_sfd__h1473[18] &&
!sV1_sfd__h1473[17] &&
!sV1_sfd__h1473[16] &&
!sV1_sfd__h1473[15] &&
!sV1_sfd__h1473[14] &&
!sV1_sfd__h1473[13] &&
!sV1_sfd__h1473[12] &&
!sV1_sfd__h1473[11] &&
!sV1_sfd__h1473[10] &&
!sV1_sfd__h1473[9] &&
!sV1_sfd__h1473[8] &&
!sV1_sfd__h1473[7] &&
!sV1_sfd__h1473[6] &&
!sV1_sfd__h1473[5] &&
!sV1_sfd__h1473[4] &&
!sV1_sfd__h1473[3] &&
!sV1_sfd__h1473[2] &&
!sV1_sfd__h1473[1] &&
!sV1_sfd__h1473[0] ||
!_0_CONCAT_IF_IF_IF_requestR_3_BIT_214_4_THEN_re_ETC___d4615 ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d5010 =
sV1_exp__h1472 == 8'd0 && !sV1_sfd__h1473[22] &&
!sV1_sfd__h1473[21] &&
!sV1_sfd__h1473[20] &&
!sV1_sfd__h1473[19] &&
!sV1_sfd__h1473[18] &&
!sV1_sfd__h1473[17] &&
!sV1_sfd__h1473[16] &&
!sV1_sfd__h1473[15] &&
!sV1_sfd__h1473[14] &&
!sV1_sfd__h1473[13] &&
!sV1_sfd__h1473[12] &&
!sV1_sfd__h1473[11] &&
!sV1_sfd__h1473[10] &&
!sV1_sfd__h1473[9] &&
!sV1_sfd__h1473[8] &&
!sV1_sfd__h1473[7] &&
!sV1_sfd__h1473[6] &&
!sV1_sfd__h1473[5] &&
!sV1_sfd__h1473[4] &&
!sV1_sfd__h1473[3] &&
!sV1_sfd__h1473[2] &&
!sV1_sfd__h1473[1] &&
!sV1_sfd__h1473[0] ||
!_0_CONCAT_IF_IF_IF_requestR_3_BIT_214_4_THEN_re_ETC___d5008 ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d5326 =
requestR_BITS_191_TO_128__q1[63] ?
!IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d5315 ||
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d5317 &&
!IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d5318 :
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d5322 ||
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d5317 &&
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d5323 ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d5333 =
(requestR_BITS_127_TO_64__q3[62:52] == 11'd2047 &&
requestR_BITS_127_TO_64__q3[51] ||
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d5302) ?
requestR[191:128] :
(IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d5306 ?
requestR[127:64] :
res__h217300) ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d5348 =
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d5302 ?
requestR[127:64] :
(IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d5306 ?
requestR[191:128] :
res__h221886) ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d5426 =
(requestR_BITS_191_TO_128__q1[62:52] == 11'd0 &&
requestR_BITS_191_TO_128__q1[51:0] == 52'd0) ?
res___1__h230314 :
((requestR_BITS_191_TO_128__q1[62:52] == 11'd0) ?
res___1__h230333 :
res__h230349) ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d571 =
(requestR[191:128] == 64'd0 ||
!sfd__h3990[63] && !sfd__h3990[62] && !sfd__h3990[61] &&
!sfd__h3990[60] &&
!sfd__h3990[59] &&
!sfd__h3990[58] &&
!sfd__h3990[57] &&
!sfd__h3990[56] &&
!sfd__h3990[55] &&
!sfd__h3990[54] &&
!sfd__h3990[53] &&
!sfd__h3990[52] &&
!sfd__h3990[51] &&
!sfd__h3990[50] &&
!sfd__h3990[49] &&
!sfd__h3990[48] &&
!sfd__h3990[47] &&
!sfd__h3990[46] &&
!sfd__h3990[45] &&
!sfd__h3990[44] &&
!sfd__h3990[43] &&
!sfd__h3990[42] &&
!sfd__h3990[41] &&
!sfd__h3990[40] &&
!sfd__h3990[39] &&
!sfd__h3990[38] &&
!sfd__h3990[37] &&
!sfd__h3990[36] &&
!sfd__h3990[35] &&
!sfd__h3990[34] &&
!sfd__h3990[33] &&
!sfd__h3990[32] &&
!sfd__h3990[31] &&
!sfd__h3990[30] &&
!sfd__h3990[29] &&
!sfd__h3990[28] &&
!sfd__h3990[27] &&
!sfd__h3990[26] &&
!sfd__h3990[25] &&
!sfd__h3990[24] &&
!sfd__h3990[23] &&
!sfd__h3990[22] &&
!sfd__h3990[21] &&
!sfd__h3990[20] &&
!sfd__h3990[19] &&
!sfd__h3990[18] &&
!sfd__h3990[17] &&
!sfd__h3990[16] &&
!sfd__h3990[15] &&
!sfd__h3990[14] &&
!sfd__h3990[13] &&
!sfd__h3990[12] &&
!sfd__h3990[11] &&
!sfd__h3990[10] &&
!sfd__h3990[9] &&
!sfd__h3990[8] &&
!sfd__h3990[7] &&
!sfd__h3990[6] &&
!sfd__h3990[5] &&
!sfd__h3990[4] &&
!sfd__h3990[3] &&
!sfd__h3990[2] &&
!sfd__h3990[1] &&
!sfd__h3990[0]) ?
8'd0 :
_theResult___snd_fst_exp__h16093 ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d684 =
(sfd__h3990[63] || sfd__h3990[62] || sfd__h3990[61] ||
sfd__h3990[60] ||
sfd__h3990[59] ||
sfd__h3990[58] ||
sfd__h3990[57] ||
sfd__h3990[56] ||
sfd__h3990[55] ||
sfd__h3990[54] ||
sfd__h3990[53] ||
sfd__h3990[52] ||
sfd__h3990[51] ||
sfd__h3990[50] ||
sfd__h3990[49] ||
sfd__h3990[48] ||
sfd__h3990[47] ||
sfd__h3990[46] ||
sfd__h3990[45] ||
sfd__h3990[44] ||
sfd__h3990[43] ||
sfd__h3990[42] ||
sfd__h3990[41] ||
sfd__h3990[40] ||
sfd__h3990[39] ||
sfd__h3990[38] ||
sfd__h3990[37] ||
sfd__h3990[36] ||
sfd__h3990[35] ||
sfd__h3990[34] ||
sfd__h3990[33] ||
sfd__h3990[32] ||
sfd__h3990[31] ||
sfd__h3990[30] ||
sfd__h3990[29] ||
sfd__h3990[28] ||
sfd__h3990[27] ||
sfd__h3990[26] ||
sfd__h3990[25] ||
sfd__h3990[24] ||
sfd__h3990[23] ||
sfd__h3990[22] ||
sfd__h3990[21] ||
sfd__h3990[20] ||
sfd__h3990[19] ||
sfd__h3990[18] ||
sfd__h3990[17] ||
sfd__h3990[16] ||
sfd__h3990[15] ||
sfd__h3990[14] ||
sfd__h3990[13] ||
sfd__h3990[12] ||
sfd__h3990[11] ||
sfd__h3990[10] ||
sfd__h3990[9] ||
sfd__h3990[8] ||
sfd__h3990[7] ||
sfd__h3990[6] ||
sfd__h3990[5] ||
sfd__h3990[4] ||
sfd__h3990[3] ||
sfd__h3990[2] ||
sfd__h3990[1] ||
sfd__h3990[0]) &&
(!_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d445 ||
!_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d447 &&
!_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d450 &&
_theResult___fst_exp__h16084 == 8'd255 &&
_theResult___fst_sfd__h16085 == 23'd0) ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d687 =
(sfd__h3990[63] || sfd__h3990[62] || sfd__h3990[61] ||
sfd__h3990[60] ||
sfd__h3990[59] ||
sfd__h3990[58] ||
sfd__h3990[57] ||
sfd__h3990[56] ||
sfd__h3990[55] ||
sfd__h3990[54] ||
sfd__h3990[53] ||
sfd__h3990[52] ||
sfd__h3990[51] ||
sfd__h3990[50] ||
sfd__h3990[49] ||
sfd__h3990[48] ||
sfd__h3990[47] ||
sfd__h3990[46] ||
sfd__h3990[45] ||
sfd__h3990[44] ||
sfd__h3990[43] ||
sfd__h3990[42] ||
sfd__h3990[41] ||
sfd__h3990[40] ||
sfd__h3990[39] ||
sfd__h3990[38] ||
sfd__h3990[37] ||
sfd__h3990[36] ||
sfd__h3990[35] ||
sfd__h3990[34] ||
sfd__h3990[33] ||
sfd__h3990[32] ||
sfd__h3990[31] ||
sfd__h3990[30] ||
sfd__h3990[29] ||
sfd__h3990[28] ||
sfd__h3990[27] ||
sfd__h3990[26] ||
sfd__h3990[25] ||
sfd__h3990[24] ||
sfd__h3990[23] ||
sfd__h3990[22] ||
sfd__h3990[21] ||
sfd__h3990[20] ||
sfd__h3990[19] ||
sfd__h3990[18] ||
sfd__h3990[17] ||
sfd__h3990[16] ||
sfd__h3990[15] ||
sfd__h3990[14] ||
sfd__h3990[13] ||
sfd__h3990[12] ||
sfd__h3990[11] ||
sfd__h3990[10] ||
sfd__h3990[9] ||
sfd__h3990[8] ||
sfd__h3990[7] ||
sfd__h3990[6] ||
sfd__h3990[5] ||
sfd__h3990[4] ||
sfd__h3990[3] ||
sfd__h3990[2] ||
sfd__h3990[1] ||
sfd__h3990[0]) &&
_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d445 &&
_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d447 ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d696 =
(sfd__h3990[63] || sfd__h3990[62] || sfd__h3990[61] ||
sfd__h3990[60] ||
sfd__h3990[59] ||
sfd__h3990[58] ||
sfd__h3990[57] ||
sfd__h3990[56] ||
sfd__h3990[55] ||
sfd__h3990[54] ||
sfd__h3990[53] ||
sfd__h3990[52] ||
sfd__h3990[51] ||
sfd__h3990[50] ||
sfd__h3990[49] ||
sfd__h3990[48] ||
sfd__h3990[47] ||
sfd__h3990[46] ||
sfd__h3990[45] ||
sfd__h3990[44] ||
sfd__h3990[43] ||
sfd__h3990[42] ||
sfd__h3990[41] ||
sfd__h3990[40] ||
sfd__h3990[39] ||
sfd__h3990[38] ||
sfd__h3990[37] ||
sfd__h3990[36] ||
sfd__h3990[35] ||
sfd__h3990[34] ||
sfd__h3990[33] ||
sfd__h3990[32] ||
sfd__h3990[31] ||
sfd__h3990[30] ||
sfd__h3990[29] ||
sfd__h3990[28] ||
sfd__h3990[27] ||
sfd__h3990[26] ||
sfd__h3990[25] ||
sfd__h3990[24] ||
sfd__h3990[23] ||
sfd__h3990[22] ||
sfd__h3990[21] ||
sfd__h3990[20] ||
sfd__h3990[19] ||
sfd__h3990[18] ||
sfd__h3990[17] ||
sfd__h3990[16] ||
sfd__h3990[15] ||
sfd__h3990[14] ||
sfd__h3990[13] ||
sfd__h3990[12] ||
sfd__h3990[11] ||
sfd__h3990[10] ||
sfd__h3990[9] ||
sfd__h3990[8] ||
sfd__h3990[7] ||
sfd__h3990[6] ||
sfd__h3990[5] ||
sfd__h3990[4] ||
sfd__h3990[3] ||
sfd__h3990[2] ||
sfd__h3990[1] ||
sfd__h3990[0]) &&
_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d445 &&
!_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d447 &&
IF_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_2_ETC___d693 ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d966 =
requestR_BITS_191_TO_128__q1[63] ?
7'd0 :
(requestR_BITS_191_TO_128__q1[62] ?
7'd1 :
(requestR_BITS_191_TO_128__q1[61] ?
7'd2 :
(requestR_BITS_191_TO_128__q1[60] ?
7'd3 :
(requestR_BITS_191_TO_128__q1[59] ?
7'd4 :
(requestR_BITS_191_TO_128__q1[58] ?
7'd5 :
(requestR_BITS_191_TO_128__q1[57] ?
7'd6 :
(requestR_BITS_191_TO_128__q1[56] ?
7'd7 :
(requestR_BITS_191_TO_128__q1[55] ?
7'd8 :
(requestR_BITS_191_TO_128__q1[54] ?
7'd9 :
(requestR_BITS_191_TO_128__q1[53] ?
7'd10 :
(requestR_BITS_191_TO_128__q1[52] ?
7'd11 :
(requestR_BITS_191_TO_128__q1[51] ?
7'd12 :
(requestR_BITS_191_TO_128__q1[50] ?
7'd13 :
(requestR_BITS_191_TO_128__q1[49] ?
7'd14 :
(requestR_BITS_191_TO_128__q1[48] ?
7'd15 :
(requestR_BITS_191_TO_128__q1[47] ?
7'd16 :
(requestR_BITS_191_TO_128__q1[46] ?
7'd17 :
(requestR_BITS_191_TO_128__q1[45] ?
7'd18 :
(requestR_BITS_191_TO_128__q1[44] ?
7'd19 :
(requestR_BITS_191_TO_128__q1[43] ?
7'd20 :
(requestR_BITS_191_TO_128__q1[42] ?
7'd21 :
(requestR_BITS_191_TO_128__q1[41] ?
7'd22 :
(requestR_BITS_191_TO_128__q1[40] ?
7'd23 :
(requestR_BITS_191_TO_128__q1[39] ?
7'd24 :
(requestR_BITS_191_TO_128__q1[38] ?
7'd25 :
(requestR_BITS_191_TO_128__q1[37] ?
7'd26 :
(requestR_BITS_191_TO_128__q1[36] ?
7'd27 :
(requestR_BITS_191_TO_128__q1[35] ?
7'd28 :
(requestR_BITS_191_TO_128__q1[34] ?
7'd29 :
(requestR_BITS_191_TO_128__q1[33] ?
7'd30 :
(requestR_BITS_191_TO_128__q1[32] ?
7'd31 :
(requestR_BITS_191_TO_128__q1[31] ?
7'd32 :
(requestR_BITS_191_TO_128__q1[30] ?
7'd33 :
(requestR_BITS_191_TO_128__q1[29] ?
7'd34 :
(requestR_BITS_191_TO_128__q1[28] ?
7'd35 :
(requestR_BITS_191_TO_128__q1[27] ?
7'd36 :
(requestR_BITS_191_TO_128__q1[26] ?
7'd37 :
(requestR_BITS_191_TO_128__q1[25] ?
7'd38 :
(requestR_BITS_191_TO_128__q1[24] ?
7'd39 :
(requestR_BITS_191_TO_128__q1[23] ?
7'd40 :
(requestR_BITS_191_TO_128__q1[22] ?
7'd41 :
(requestR_BITS_191_TO_128__q1[21] ?
7'd42 :
(requestR_BITS_191_TO_128__q1[20] ?
7'd43 :
(requestR_BITS_191_TO_128__q1[19] ?
7'd44 :
(requestR_BITS_191_TO_128__q1[18] ?
7'd45 :
(requestR_BITS_191_TO_128__q1[17] ?
7'd46 :
(requestR_BITS_191_TO_128__q1[16] ?
7'd47 :
(requestR_BITS_191_TO_128__q1[15] ?
7'd48 :
(requestR_BITS_191_TO_128__q1[14] ?
7'd49 :
(requestR_BITS_191_TO_128__q1[13] ?
7'd50 :
(requestR_BITS_191_TO_128__q1[12] ?
7'd51 :
(requestR_BITS_191_TO_128__q1[11] ?
7'd52 :
(requestR_BITS_191_TO_128__q1[10] ?
7'd53 :
(requestR_BITS_191_TO_128__q1[9] ?
7'd54 :
(requestR_BITS_191_TO_128__q1[8] ?
7'd55 :
(requestR_BITS_191_TO_128__q1[7] ?
7'd56 :
(requestR_BITS_191_TO_128__q1[6] ?
7'd57 :
(requestR_BITS_191_TO_128__q1[5] ?
7'd58 :
(requestR_BITS_191_TO_128__q1[4] ?
7'd59 :
(requestR_BITS_191_TO_128__q1[3] ?
7'd60 :
(requestR_BITS_191_TO_128__q1[2] ?
7'd61 :
(requestR_BITS_191_TO_128__q1[1] ?
7'd62 :
(requestR_BITS_191_TO_128__q1[0] ?
7'd63 :
7'd64))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))) ;
assign IF_NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_re_ETC___d1812 =
NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1785 ?
(IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1806 ?
((x__h44058[88:25] == 64'h7FFFFFFFFFFFFFFF) ?
x__h44058[88:25] :
x__h44058[88:25] + 64'd1) :
x__h44058[88:25]) :
64'd0 ;
assign IF_NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_re_ETC___d1814 =
(NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1750 ==
20'd1048513) ?
((_theResult_____2__h43093[64:63] == 2'b11) ?
_theResult_____2__h43093[63:0] :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1745) :
(NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1783[19] ?
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1745 :
IF_NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_re_ETC___d1812) ;
assign IF_NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_re_ETC___d1837 =
(NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1750 ==
20'd1048513) ?
_theResult_____2__h43093[64:63] == 2'b11 &&
guard__h43091 != 2'd0 :
!NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1783[19] &&
(!NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1785 ||
guard__h43869 != 2'd0) ;
assign IF_NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_re_ETC___d1874 =
NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1849 ?
(IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1868 ?
((x__h45414[88:25] == 64'hFFFFFFFFFFFFFFFF) ?
x__h45414[88:25] :
x__h45414[88:25] + 64'd1) :
x__h45414[88:25]) :
64'd0 ;
assign IF_NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_re_ETC___d1963 =
NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1936 ?
(IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1957 ?
((x__h46697[56:25] == 32'h7FFFFFFF) ?
x__h46697[56:25] :
x__h46697[56:25] + 32'd1) :
x__h46697[56:25]) :
32'd0 ;
assign IF_NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_re_ETC___d1965 =
(NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1750 ==
20'd1048545) ?
((_theResult_____2__h45956[32:31] == 2'b11) ?
_theResult_____2__h45956[31:0] :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1904) :
(NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1934[19] ?
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1904 :
IF_NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_re_ETC___d1963) ;
assign IF_NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_re_ETC___d1983 =
(NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1750 ==
20'd1048545) ?
_theResult_____2__h45956[32:31] == 2'b11 &&
guard__h45954 != 2'd0 :
!NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1934[19] &&
(!NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1936 ||
guard__h46508 != 2'd0) ;
assign IF_NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_re_ETC___d2020 =
NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1995 ?
(IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2014 ?
((x__h47815[56:25] == 32'hFFFFFFFF) ?
x__h47815[56:25] :
x__h47815[56:25] + 32'd1) :
x__h47815[56:25]) :
32'd0 ;
assign IF_NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d2786 =
NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2759 ?
(IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2780 ?
((x__h83201[85:54] == 32'h7FFFFFFF) ?
x__h83201[85:54] :
x__h83201[85:54] + 32'd1) :
x__h83201[85:54]) :
32'd0 ;
assign IF_NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d2788 =
(NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2724 ==
24'd16777185) ?
((_theResult_____2__h82460[32:31] == 2'b11) ?
_theResult_____2__h82460[31:0] :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2719) :
(NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2757[23] ?
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2719 :
IF_NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d2786) ;
assign IF_NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d2812 =
(NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2724 ==
24'd16777185) ?
_theResult_____2__h82460[32:31] == 2'b11 &&
guard__h82458 != 2'd0 :
!NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2757[23] &&
(!NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2759 ||
guard__h83012 != 2'd0) ;
assign IF_NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d2849 =
NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2824 ?
(IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2843 ?
((x__h84319[85:54] == 32'hFFFFFFFF) ?
x__h84319[85:54] :
x__h84319[85:54] + 32'd1) :
x__h84319[85:54]) :
32'd0 ;
assign IF_NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d3279 =
NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d3252 ?
(IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3273 ?
((x__h111322[117:54] == 64'h7FFFFFFFFFFFFFFF) ?
x__h111322[117:54] :
x__h111322[117:54] + 64'd1) :
x__h111322[117:54]) :
64'd0 ;
assign IF_NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d3281 =
(NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2724 ==
24'd16777153) ?
((_theResult_____2__h110357[64:63] == 2'b11) ?
_theResult_____2__h110357[63:0] :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3220) :
(NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d3250[23] ?
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3220 :
IF_NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d3279) ;
assign IF_NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d3298 =
(NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2724 ==
24'd16777153) ?
_theResult_____2__h110357[64:63] == 2'b11 &&
guard__h110355 != 2'd0 :
!NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d3250[23] &&
(!NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d3252 ||
guard__h111133 != 2'd0) ;
assign IF_NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d3335 =
NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d3310 ?
(IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3329 ?
((x__h112661[117:54] == 64'hFFFFFFFFFFFFFFFF) ?
x__h112661[117:54] :
x__h112661[117:54] + 64'd1) :
x__h112661[117:54]) :
64'd0 ;
assign IF_NOT_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_B_ETC___d2399 =
(!_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d2343 ||
_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d2345) ?
requestR_BITS_191_TO_128__q1[31] :
IF_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_2_ETC___d2398 ;
assign IF_NOT_3970_MINUS_0_CONCAT_IF_IF_IF_requestR_3_ETC___d5169 =
(!_3970_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_21_ETC___d4542 ||
_3970_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_21_ETC___d4543 ||
_theResult___fst_exp__h190506 == 11'd2047) ?
requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31] :
((requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard81312_0b0_requestR_BITS_191_TO_128_B_ETC__q165 :
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q166) ;
assign IF_NOT_IF_IF_requestR_3_BIT_214_4_THEN_request_ETC___d2106 =
NOT_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_ETC___d2105 ?
{ requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31],
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d37 } :
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d48 ;
assign IF_NOT_IF_IF_requestR_3_BIT_214_4_THEN_request_ETC___d2122 =
NOT_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_ETC___d2105 ?
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d48 :
{ requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31],
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d37 } ;
assign IF_NOT_IF_requestR_3_BIT_214_4_THEN_requestR_3_ETC___d2101 =
(requestR_BITS_191_TO_128__q1[63:32] != 32'hFFFFFFFF ||
!requestR_BITS_191_TO_128__q1[31]) ?
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2090 ||
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2091 &&
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2092 :
!IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2095 ||
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2091 &&
!IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2097 ;
assign IF_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reques_ETC___d5007 =
((SEXT_IF_IF_requestR_3_BIT_214_4_THEN_requestR__ETC__q153[10:0] ==
11'd0) ?
12'd3074 :
{ SEXT_IF_IF_requestR_3_BIT_214_4_THEN_requestR__ETC__q156[10],
SEXT_IF_IF_requestR_3_BIT_214_4_THEN_requestR__ETC__q156 }) -
12'd3074 ;
assign IF_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reques_ETC___d5186 =
SEXT_IF_IF_requestR_3_BIT_214_4_THEN_requestR__ETC___d4686 ?
((_theResult___fst_exp__h201334 == 11'd2047) ?
requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31] :
((requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard91853_0b0_requestR_BITS_191_TO_128_B_ETC__q167 :
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q168)) :
((_theResult___fst_exp__h211398 == 11'd2047) ?
requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31] :
((requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard02175_0b0_requestR_BITS_191_TO_128_B_ETC__q169 :
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q170)) ;
assign IF_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reques_ETC___d5246 =
SEXT_IF_IF_requestR_3_BIT_214_4_THEN_requestR__ETC___d4686 ?
_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_IF_requestR__ETC___d5220[2] :
_theResult___fst_exp__h212179 == 11'd2047 &&
_theResult___fst_sfd__h212180 == 52'd0 ;
assign IF_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reques_ETC___d5258 =
SEXT_IF_IF_requestR_3_BIT_214_4_THEN_requestR__ETC___d4686 ?
_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_IF_requestR__ETC___d5220[1] :
_theResult___fst_exp__h211398 == 11'd0 &&
guard__h202175 != 2'b0 ;
assign IF_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reques_ETC___d5270 =
SEXT_IF_IF_requestR_3_BIT_214_4_THEN_requestR__ETC___d4686 ?
_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_IF_requestR__ETC___d5220[0] :
_theResult___fst_exp__h211398 != 11'd2047 &&
guard__h202175 != 2'b0 ;
assign IF_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR__ETC___d4172 =
((SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_3_B_ETC__q121[7:0] ==
8'd0) ?
9'd386 :
{ SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_3_B_ETC__q124[7],
SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_3_B_ETC__q124 }) -
9'd386 ;
assign IF_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR__ETC___d4376 =
SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_3_B_ETC___d3853 ?
((_theResult___fst_exp__h155731 == 8'd255) ?
requestR_BITS_191_TO_128__q1[63] :
((requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard46250_0b0_requestR_BITS_191_TO_128_B_ETC__q147 :
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q148)) :
((_theResult___fst_exp__h165679 == 8'd255) ?
requestR_BITS_191_TO_128__q1[63] :
((requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard56369_0b0_requestR_BITS_191_TO_128_B_ETC__q149 :
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q150)) ;
assign IF_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR__ETC___d4454 =
SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_3_B_ETC___d3853 ?
_0_CONCAT_IF_IF_3970_MINUS_SEXT_IF_requestR_3_B_ETC___d4425[2] :
_theResult___fst_exp__h166257 == 8'd255 &&
_theResult___fst_sfd__h166258 == 23'd0 ;
assign IF_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR__ETC___d4467 =
SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_3_B_ETC___d3853 ?
_0_CONCAT_IF_IF_3970_MINUS_SEXT_IF_requestR_3_B_ETC___d4425[1] :
_theResult___fst_exp__h165679 == 8'd0 &&
guard__h156369 != 2'b0 ;
assign IF_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR__ETC___d4480 =
SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_3_B_ETC___d3853 ?
_0_CONCAT_IF_IF_3970_MINUS_SEXT_IF_requestR_3_B_ETC___d4425[0] :
_theResult___fst_exp__h165679 != 8'd255 &&
guard__h156369 != 2'b0 ;
assign IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d1165 =
(requestR_BITS_191_TO_128__q1[63] ||
requestR_BITS_191_TO_128__q1[62] ||
requestR_BITS_191_TO_128__q1[61] ||
requestR_BITS_191_TO_128__q1[60] ||
requestR_BITS_191_TO_128__q1[59] ||
requestR_BITS_191_TO_128__q1[58] ||
requestR_BITS_191_TO_128__q1[57] ||
requestR_BITS_191_TO_128__q1[56] ||
requestR_BITS_191_TO_128__q1[55] ||
requestR_BITS_191_TO_128__q1[54] ||
requestR_BITS_191_TO_128__q1[53] ||
requestR_BITS_191_TO_128__q1[52] ||
requestR_BITS_191_TO_128__q1[51] ||
requestR_BITS_191_TO_128__q1[50] ||
requestR_BITS_191_TO_128__q1[49] ||
requestR_BITS_191_TO_128__q1[48] ||
requestR_BITS_191_TO_128__q1[47] ||
requestR_BITS_191_TO_128__q1[46] ||
requestR_BITS_191_TO_128__q1[45] ||
requestR_BITS_191_TO_128__q1[44] ||
requestR_BITS_191_TO_128__q1[43] ||
requestR_BITS_191_TO_128__q1[42] ||
requestR_BITS_191_TO_128__q1[41] ||
requestR_BITS_191_TO_128__q1[40] ||
requestR_BITS_191_TO_128__q1[39] ||
requestR_BITS_191_TO_128__q1[38] ||
requestR_BITS_191_TO_128__q1[37] ||
requestR_BITS_191_TO_128__q1[36] ||
requestR_BITS_191_TO_128__q1[35] ||
requestR_BITS_191_TO_128__q1[34] ||
requestR_BITS_191_TO_128__q1[33] ||
requestR_BITS_191_TO_128__q1[32] ||
requestR_BITS_191_TO_128__q1[31] ||
requestR_BITS_191_TO_128__q1[30] ||
requestR_BITS_191_TO_128__q1[29] ||
requestR_BITS_191_TO_128__q1[28] ||
requestR_BITS_191_TO_128__q1[27] ||
requestR_BITS_191_TO_128__q1[26] ||
requestR_BITS_191_TO_128__q1[25] ||
requestR_BITS_191_TO_128__q1[24] ||
requestR_BITS_191_TO_128__q1[23] ||
requestR_BITS_191_TO_128__q1[22] ||
requestR_BITS_191_TO_128__q1[21] ||
requestR_BITS_191_TO_128__q1[20] ||
requestR_BITS_191_TO_128__q1[19] ||
requestR_BITS_191_TO_128__q1[18] ||
requestR_BITS_191_TO_128__q1[17] ||
requestR_BITS_191_TO_128__q1[16] ||
requestR_BITS_191_TO_128__q1[15] ||
requestR_BITS_191_TO_128__q1[14] ||
requestR_BITS_191_TO_128__q1[13] ||
requestR_BITS_191_TO_128__q1[12] ||
requestR_BITS_191_TO_128__q1[11] ||
requestR_BITS_191_TO_128__q1[10] ||
requestR_BITS_191_TO_128__q1[9] ||
requestR_BITS_191_TO_128__q1[8] ||
requestR_BITS_191_TO_128__q1[7] ||
requestR_BITS_191_TO_128__q1[6] ||
requestR_BITS_191_TO_128__q1[5] ||
requestR_BITS_191_TO_128__q1[4] ||
requestR_BITS_191_TO_128__q1[3] ||
requestR_BITS_191_TO_128__q1[2] ||
requestR_BITS_191_TO_128__q1[1] ||
requestR_BITS_191_TO_128__q1[0]) &&
(!_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d970 ||
!_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d971 &&
!_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d972 &&
_theResult___fst_exp__h28360 == 8'd255 &&
_theResult___fst_sfd__h28361 == 23'd0) ;
assign IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d1168 =
(requestR_BITS_191_TO_128__q1[63] ||
requestR_BITS_191_TO_128__q1[62] ||
requestR_BITS_191_TO_128__q1[61] ||
requestR_BITS_191_TO_128__q1[60] ||
requestR_BITS_191_TO_128__q1[59] ||
requestR_BITS_191_TO_128__q1[58] ||
requestR_BITS_191_TO_128__q1[57] ||
requestR_BITS_191_TO_128__q1[56] ||
requestR_BITS_191_TO_128__q1[55] ||
requestR_BITS_191_TO_128__q1[54] ||
requestR_BITS_191_TO_128__q1[53] ||
requestR_BITS_191_TO_128__q1[52] ||
requestR_BITS_191_TO_128__q1[51] ||
requestR_BITS_191_TO_128__q1[50] ||
requestR_BITS_191_TO_128__q1[49] ||
requestR_BITS_191_TO_128__q1[48] ||
requestR_BITS_191_TO_128__q1[47] ||
requestR_BITS_191_TO_128__q1[46] ||
requestR_BITS_191_TO_128__q1[45] ||
requestR_BITS_191_TO_128__q1[44] ||
requestR_BITS_191_TO_128__q1[43] ||
requestR_BITS_191_TO_128__q1[42] ||
requestR_BITS_191_TO_128__q1[41] ||
requestR_BITS_191_TO_128__q1[40] ||
requestR_BITS_191_TO_128__q1[39] ||
requestR_BITS_191_TO_128__q1[38] ||
requestR_BITS_191_TO_128__q1[37] ||
requestR_BITS_191_TO_128__q1[36] ||
requestR_BITS_191_TO_128__q1[35] ||
requestR_BITS_191_TO_128__q1[34] ||
requestR_BITS_191_TO_128__q1[33] ||
requestR_BITS_191_TO_128__q1[32] ||
requestR_BITS_191_TO_128__q1[31] ||
requestR_BITS_191_TO_128__q1[30] ||
requestR_BITS_191_TO_128__q1[29] ||
requestR_BITS_191_TO_128__q1[28] ||
requestR_BITS_191_TO_128__q1[27] ||
requestR_BITS_191_TO_128__q1[26] ||
requestR_BITS_191_TO_128__q1[25] ||
requestR_BITS_191_TO_128__q1[24] ||
requestR_BITS_191_TO_128__q1[23] ||
requestR_BITS_191_TO_128__q1[22] ||
requestR_BITS_191_TO_128__q1[21] ||
requestR_BITS_191_TO_128__q1[20] ||
requestR_BITS_191_TO_128__q1[19] ||
requestR_BITS_191_TO_128__q1[18] ||
requestR_BITS_191_TO_128__q1[17] ||
requestR_BITS_191_TO_128__q1[16] ||
requestR_BITS_191_TO_128__q1[15] ||
requestR_BITS_191_TO_128__q1[14] ||
requestR_BITS_191_TO_128__q1[13] ||
requestR_BITS_191_TO_128__q1[12] ||
requestR_BITS_191_TO_128__q1[11] ||
requestR_BITS_191_TO_128__q1[10] ||
requestR_BITS_191_TO_128__q1[9] ||
requestR_BITS_191_TO_128__q1[8] ||
requestR_BITS_191_TO_128__q1[7] ||
requestR_BITS_191_TO_128__q1[6] ||
requestR_BITS_191_TO_128__q1[5] ||
requestR_BITS_191_TO_128__q1[4] ||
requestR_BITS_191_TO_128__q1[3] ||
requestR_BITS_191_TO_128__q1[2] ||
requestR_BITS_191_TO_128__q1[1] ||
requestR_BITS_191_TO_128__q1[0]) &&
_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d970 &&
_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d971 ;
assign IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d1177 =
(requestR_BITS_191_TO_128__q1[63] ||
requestR_BITS_191_TO_128__q1[62] ||
requestR_BITS_191_TO_128__q1[61] ||
requestR_BITS_191_TO_128__q1[60] ||
requestR_BITS_191_TO_128__q1[59] ||
requestR_BITS_191_TO_128__q1[58] ||
requestR_BITS_191_TO_128__q1[57] ||
requestR_BITS_191_TO_128__q1[56] ||
requestR_BITS_191_TO_128__q1[55] ||
requestR_BITS_191_TO_128__q1[54] ||
requestR_BITS_191_TO_128__q1[53] ||
requestR_BITS_191_TO_128__q1[52] ||
requestR_BITS_191_TO_128__q1[51] ||
requestR_BITS_191_TO_128__q1[50] ||
requestR_BITS_191_TO_128__q1[49] ||
requestR_BITS_191_TO_128__q1[48] ||
requestR_BITS_191_TO_128__q1[47] ||
requestR_BITS_191_TO_128__q1[46] ||
requestR_BITS_191_TO_128__q1[45] ||
requestR_BITS_191_TO_128__q1[44] ||
requestR_BITS_191_TO_128__q1[43] ||
requestR_BITS_191_TO_128__q1[42] ||
requestR_BITS_191_TO_128__q1[41] ||
requestR_BITS_191_TO_128__q1[40] ||
requestR_BITS_191_TO_128__q1[39] ||
requestR_BITS_191_TO_128__q1[38] ||
requestR_BITS_191_TO_128__q1[37] ||
requestR_BITS_191_TO_128__q1[36] ||
requestR_BITS_191_TO_128__q1[35] ||
requestR_BITS_191_TO_128__q1[34] ||
requestR_BITS_191_TO_128__q1[33] ||
requestR_BITS_191_TO_128__q1[32] ||
requestR_BITS_191_TO_128__q1[31] ||
requestR_BITS_191_TO_128__q1[30] ||
requestR_BITS_191_TO_128__q1[29] ||
requestR_BITS_191_TO_128__q1[28] ||
requestR_BITS_191_TO_128__q1[27] ||
requestR_BITS_191_TO_128__q1[26] ||
requestR_BITS_191_TO_128__q1[25] ||
requestR_BITS_191_TO_128__q1[24] ||
requestR_BITS_191_TO_128__q1[23] ||
requestR_BITS_191_TO_128__q1[22] ||
requestR_BITS_191_TO_128__q1[21] ||
requestR_BITS_191_TO_128__q1[20] ||
requestR_BITS_191_TO_128__q1[19] ||
requestR_BITS_191_TO_128__q1[18] ||
requestR_BITS_191_TO_128__q1[17] ||
requestR_BITS_191_TO_128__q1[16] ||
requestR_BITS_191_TO_128__q1[15] ||
requestR_BITS_191_TO_128__q1[14] ||
requestR_BITS_191_TO_128__q1[13] ||
requestR_BITS_191_TO_128__q1[12] ||
requestR_BITS_191_TO_128__q1[11] ||
requestR_BITS_191_TO_128__q1[10] ||
requestR_BITS_191_TO_128__q1[9] ||
requestR_BITS_191_TO_128__q1[8] ||
requestR_BITS_191_TO_128__q1[7] ||
requestR_BITS_191_TO_128__q1[6] ||
requestR_BITS_191_TO_128__q1[5] ||
requestR_BITS_191_TO_128__q1[4] ||
requestR_BITS_191_TO_128__q1[3] ||
requestR_BITS_191_TO_128__q1[2] ||
requestR_BITS_191_TO_128__q1[1] ||
requestR_BITS_191_TO_128__q1[0]) &&
_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d970 &&
!_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d971 &&
IF_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214__ETC___d1174 ;
assign IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d1709 =
(requestR_BITS_191_TO_128__q1[31] ||
requestR_BITS_191_TO_128__q1[30] ||
requestR_BITS_191_TO_128__q1[29] ||
requestR_BITS_191_TO_128__q1[28] ||
requestR_BITS_191_TO_128__q1[27] ||
requestR_BITS_191_TO_128__q1[26] ||
requestR_BITS_191_TO_128__q1[25] ||
requestR_BITS_191_TO_128__q1[24] ||
requestR_BITS_191_TO_128__q1[23] ||
requestR_BITS_191_TO_128__q1[22] ||
requestR_BITS_191_TO_128__q1[21] ||
requestR_BITS_191_TO_128__q1[20] ||
requestR_BITS_191_TO_128__q1[19] ||
requestR_BITS_191_TO_128__q1[18] ||
requestR_BITS_191_TO_128__q1[17] ||
requestR_BITS_191_TO_128__q1[16] ||
requestR_BITS_191_TO_128__q1[15] ||
requestR_BITS_191_TO_128__q1[14] ||
requestR_BITS_191_TO_128__q1[13] ||
requestR_BITS_191_TO_128__q1[12] ||
requestR_BITS_191_TO_128__q1[11] ||
requestR_BITS_191_TO_128__q1[10] ||
requestR_BITS_191_TO_128__q1[9] ||
requestR_BITS_191_TO_128__q1[8] ||
requestR_BITS_191_TO_128__q1[7] ||
requestR_BITS_191_TO_128__q1[6] ||
requestR_BITS_191_TO_128__q1[5] ||
requestR_BITS_191_TO_128__q1[4] ||
requestR_BITS_191_TO_128__q1[3] ||
requestR_BITS_191_TO_128__q1[2] ||
requestR_BITS_191_TO_128__q1[1] ||
requestR_BITS_191_TO_128__q1[0]) &&
(!_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d1578 ||
!_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d1579 &&
!_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d1580 &&
_theResult___fst_exp__h42448 == 8'd255 &&
_theResult___fst_sfd__h42449 == 23'd0) ;
assign IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d1712 =
(requestR_BITS_191_TO_128__q1[31] ||
requestR_BITS_191_TO_128__q1[30] ||
requestR_BITS_191_TO_128__q1[29] ||
requestR_BITS_191_TO_128__q1[28] ||
requestR_BITS_191_TO_128__q1[27] ||
requestR_BITS_191_TO_128__q1[26] ||
requestR_BITS_191_TO_128__q1[25] ||
requestR_BITS_191_TO_128__q1[24] ||
requestR_BITS_191_TO_128__q1[23] ||
requestR_BITS_191_TO_128__q1[22] ||
requestR_BITS_191_TO_128__q1[21] ||
requestR_BITS_191_TO_128__q1[20] ||
requestR_BITS_191_TO_128__q1[19] ||
requestR_BITS_191_TO_128__q1[18] ||
requestR_BITS_191_TO_128__q1[17] ||
requestR_BITS_191_TO_128__q1[16] ||
requestR_BITS_191_TO_128__q1[15] ||
requestR_BITS_191_TO_128__q1[14] ||
requestR_BITS_191_TO_128__q1[13] ||
requestR_BITS_191_TO_128__q1[12] ||
requestR_BITS_191_TO_128__q1[11] ||
requestR_BITS_191_TO_128__q1[10] ||
requestR_BITS_191_TO_128__q1[9] ||
requestR_BITS_191_TO_128__q1[8] ||
requestR_BITS_191_TO_128__q1[7] ||
requestR_BITS_191_TO_128__q1[6] ||
requestR_BITS_191_TO_128__q1[5] ||
requestR_BITS_191_TO_128__q1[4] ||
requestR_BITS_191_TO_128__q1[3] ||
requestR_BITS_191_TO_128__q1[2] ||
requestR_BITS_191_TO_128__q1[1] ||
requestR_BITS_191_TO_128__q1[0]) &&
_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d1578 &&
_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d1579 ;
assign IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d1721 =
(requestR_BITS_191_TO_128__q1[31] ||
requestR_BITS_191_TO_128__q1[30] ||
requestR_BITS_191_TO_128__q1[29] ||
requestR_BITS_191_TO_128__q1[28] ||
requestR_BITS_191_TO_128__q1[27] ||
requestR_BITS_191_TO_128__q1[26] ||
requestR_BITS_191_TO_128__q1[25] ||
requestR_BITS_191_TO_128__q1[24] ||
requestR_BITS_191_TO_128__q1[23] ||
requestR_BITS_191_TO_128__q1[22] ||
requestR_BITS_191_TO_128__q1[21] ||
requestR_BITS_191_TO_128__q1[20] ||
requestR_BITS_191_TO_128__q1[19] ||
requestR_BITS_191_TO_128__q1[18] ||
requestR_BITS_191_TO_128__q1[17] ||
requestR_BITS_191_TO_128__q1[16] ||
requestR_BITS_191_TO_128__q1[15] ||
requestR_BITS_191_TO_128__q1[14] ||
requestR_BITS_191_TO_128__q1[13] ||
requestR_BITS_191_TO_128__q1[12] ||
requestR_BITS_191_TO_128__q1[11] ||
requestR_BITS_191_TO_128__q1[10] ||
requestR_BITS_191_TO_128__q1[9] ||
requestR_BITS_191_TO_128__q1[8] ||
requestR_BITS_191_TO_128__q1[7] ||
requestR_BITS_191_TO_128__q1[6] ||
requestR_BITS_191_TO_128__q1[5] ||
requestR_BITS_191_TO_128__q1[4] ||
requestR_BITS_191_TO_128__q1[3] ||
requestR_BITS_191_TO_128__q1[2] ||
requestR_BITS_191_TO_128__q1[1] ||
requestR_BITS_191_TO_128__q1[0]) &&
_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d1578 &&
!_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d1579 &&
IF_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214__ETC___d1718 ;
assign IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d2103 =
requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31] &&
(requestR_BITS_127_TO_64__q3[63:32] != 32'hFFFFFFFF ||
!requestR_BITS_127_TO_64__q3[31]) ||
(requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31] ||
requestR_BITS_127_TO_64__q3[63:32] != 32'hFFFFFFFF ||
!requestR_BITS_127_TO_64__q3[31]) &&
IF_NOT_IF_requestR_3_BIT_214_4_THEN_requestR_3_ETC___d2101 ;
assign IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d2169 =
(requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31] ||
requestR_BITS_127_TO_64__q3[63:32] != 32'hFFFFFFFF ||
!requestR_BITS_127_TO_64__q3[31]) &&
((requestR_BITS_191_TO_128__q1[63:32] != 32'hFFFFFFFF ||
!requestR_BITS_191_TO_128__q1[31]) ?
NOT_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_ETC___d2166 :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2167) ;
assign IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d2722 =
requestR_BITS_191_TO_128__q1[62:52] - 11'd1023 ;
assign IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d2861 =
requestR_BITS_191_TO_128__q1[62:52] == 11'd2047 &&
requestR_BITS_191_TO_128__q1[51:0] != 52'd0 ||
requestR_BITS_191_TO_128__q1[62:52] == 11'd2047 &&
requestR_BITS_191_TO_128__q1[51:0] == 52'd0 ||
(requestR_BITS_191_TO_128__q1[62:52] != 11'd0 ||
requestR_BITS_191_TO_128__q1[51:0] != 52'd0) &&
(NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2822[23] ||
NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2824 &&
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2843 &&
x__h84319[85:54] == 32'hFFFFFFFF) ;
assign IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d2872 =
{ IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d2861,
3'd0,
(requestR_BITS_191_TO_128__q1[62:52] != 11'd2047 ||
requestR_BITS_191_TO_128__q1[51:0] == 52'd0) &&
(requestR_BITS_191_TO_128__q1[62:52] != 11'd2047 ||
requestR_BITS_191_TO_128__q1[51:0] != 52'd0) &&
NOT_IF_requestR_3_BIT_214_4_THEN_requestR_3_BI_ETC___d2866 } ==
5'd0 ||
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d2861 ;
assign IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d3199 =
(requestR_BITS_191_TO_128__q1[63] ||
requestR_BITS_191_TO_128__q1[62] ||
requestR_BITS_191_TO_128__q1[61] ||
requestR_BITS_191_TO_128__q1[60] ||
requestR_BITS_191_TO_128__q1[59] ||
requestR_BITS_191_TO_128__q1[58] ||
requestR_BITS_191_TO_128__q1[57] ||
requestR_BITS_191_TO_128__q1[56] ||
requestR_BITS_191_TO_128__q1[55] ||
requestR_BITS_191_TO_128__q1[54] ||
requestR_BITS_191_TO_128__q1[53] ||
requestR_BITS_191_TO_128__q1[52] ||
requestR_BITS_191_TO_128__q1[51] ||
requestR_BITS_191_TO_128__q1[50] ||
requestR_BITS_191_TO_128__q1[49] ||
requestR_BITS_191_TO_128__q1[48] ||
requestR_BITS_191_TO_128__q1[47] ||
requestR_BITS_191_TO_128__q1[46] ||
requestR_BITS_191_TO_128__q1[45] ||
requestR_BITS_191_TO_128__q1[44] ||
requestR_BITS_191_TO_128__q1[43] ||
requestR_BITS_191_TO_128__q1[42] ||
requestR_BITS_191_TO_128__q1[41] ||
requestR_BITS_191_TO_128__q1[40] ||
requestR_BITS_191_TO_128__q1[39] ||
requestR_BITS_191_TO_128__q1[38] ||
requestR_BITS_191_TO_128__q1[37] ||
requestR_BITS_191_TO_128__q1[36] ||
requestR_BITS_191_TO_128__q1[35] ||
requestR_BITS_191_TO_128__q1[34] ||
requestR_BITS_191_TO_128__q1[33] ||
requestR_BITS_191_TO_128__q1[32] ||
requestR_BITS_191_TO_128__q1[31] ||
requestR_BITS_191_TO_128__q1[30] ||
requestR_BITS_191_TO_128__q1[29] ||
requestR_BITS_191_TO_128__q1[28] ||
requestR_BITS_191_TO_128__q1[27] ||
requestR_BITS_191_TO_128__q1[26] ||
requestR_BITS_191_TO_128__q1[25] ||
requestR_BITS_191_TO_128__q1[24] ||
requestR_BITS_191_TO_128__q1[23] ||
requestR_BITS_191_TO_128__q1[22] ||
requestR_BITS_191_TO_128__q1[21] ||
requestR_BITS_191_TO_128__q1[20] ||
requestR_BITS_191_TO_128__q1[19] ||
requestR_BITS_191_TO_128__q1[18] ||
requestR_BITS_191_TO_128__q1[17] ||
requestR_BITS_191_TO_128__q1[16] ||
requestR_BITS_191_TO_128__q1[15] ||
requestR_BITS_191_TO_128__q1[14] ||
requestR_BITS_191_TO_128__q1[13] ||
requestR_BITS_191_TO_128__q1[12] ||
requestR_BITS_191_TO_128__q1[11] ||
requestR_BITS_191_TO_128__q1[10] ||
requestR_BITS_191_TO_128__q1[9] ||
requestR_BITS_191_TO_128__q1[8] ||
requestR_BITS_191_TO_128__q1[7] ||
requestR_BITS_191_TO_128__q1[6] ||
requestR_BITS_191_TO_128__q1[5] ||
requestR_BITS_191_TO_128__q1[4] ||
requestR_BITS_191_TO_128__q1[3] ||
requestR_BITS_191_TO_128__q1[2] ||
requestR_BITS_191_TO_128__q1[1] ||
requestR_BITS_191_TO_128__q1[0]) &&
(!_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d3069 ||
!_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d3070 &&
!_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d3071 &&
_theResult___fst_exp__h109716 == 11'd2047 &&
_theResult___fst_sfd__h109717 == 52'd0) ;
assign IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d3202 =
(requestR_BITS_191_TO_128__q1[63] ||
requestR_BITS_191_TO_128__q1[62] ||
requestR_BITS_191_TO_128__q1[61] ||
requestR_BITS_191_TO_128__q1[60] ||
requestR_BITS_191_TO_128__q1[59] ||
requestR_BITS_191_TO_128__q1[58] ||
requestR_BITS_191_TO_128__q1[57] ||
requestR_BITS_191_TO_128__q1[56] ||
requestR_BITS_191_TO_128__q1[55] ||
requestR_BITS_191_TO_128__q1[54] ||
requestR_BITS_191_TO_128__q1[53] ||
requestR_BITS_191_TO_128__q1[52] ||
requestR_BITS_191_TO_128__q1[51] ||
requestR_BITS_191_TO_128__q1[50] ||
requestR_BITS_191_TO_128__q1[49] ||
requestR_BITS_191_TO_128__q1[48] ||
requestR_BITS_191_TO_128__q1[47] ||
requestR_BITS_191_TO_128__q1[46] ||
requestR_BITS_191_TO_128__q1[45] ||
requestR_BITS_191_TO_128__q1[44] ||
requestR_BITS_191_TO_128__q1[43] ||
requestR_BITS_191_TO_128__q1[42] ||
requestR_BITS_191_TO_128__q1[41] ||
requestR_BITS_191_TO_128__q1[40] ||
requestR_BITS_191_TO_128__q1[39] ||
requestR_BITS_191_TO_128__q1[38] ||
requestR_BITS_191_TO_128__q1[37] ||
requestR_BITS_191_TO_128__q1[36] ||
requestR_BITS_191_TO_128__q1[35] ||
requestR_BITS_191_TO_128__q1[34] ||
requestR_BITS_191_TO_128__q1[33] ||
requestR_BITS_191_TO_128__q1[32] ||
requestR_BITS_191_TO_128__q1[31] ||
requestR_BITS_191_TO_128__q1[30] ||
requestR_BITS_191_TO_128__q1[29] ||
requestR_BITS_191_TO_128__q1[28] ||
requestR_BITS_191_TO_128__q1[27] ||
requestR_BITS_191_TO_128__q1[26] ||
requestR_BITS_191_TO_128__q1[25] ||
requestR_BITS_191_TO_128__q1[24] ||
requestR_BITS_191_TO_128__q1[23] ||
requestR_BITS_191_TO_128__q1[22] ||
requestR_BITS_191_TO_128__q1[21] ||
requestR_BITS_191_TO_128__q1[20] ||
requestR_BITS_191_TO_128__q1[19] ||
requestR_BITS_191_TO_128__q1[18] ||
requestR_BITS_191_TO_128__q1[17] ||
requestR_BITS_191_TO_128__q1[16] ||
requestR_BITS_191_TO_128__q1[15] ||
requestR_BITS_191_TO_128__q1[14] ||
requestR_BITS_191_TO_128__q1[13] ||
requestR_BITS_191_TO_128__q1[12] ||
requestR_BITS_191_TO_128__q1[11] ||
requestR_BITS_191_TO_128__q1[10] ||
requestR_BITS_191_TO_128__q1[9] ||
requestR_BITS_191_TO_128__q1[8] ||
requestR_BITS_191_TO_128__q1[7] ||
requestR_BITS_191_TO_128__q1[6] ||
requestR_BITS_191_TO_128__q1[5] ||
requestR_BITS_191_TO_128__q1[4] ||
requestR_BITS_191_TO_128__q1[3] ||
requestR_BITS_191_TO_128__q1[2] ||
requestR_BITS_191_TO_128__q1[1] ||
requestR_BITS_191_TO_128__q1[0]) &&
_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d3069 &&
_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d3070 ;
assign IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d3211 =
(requestR_BITS_191_TO_128__q1[63] ||
requestR_BITS_191_TO_128__q1[62] ||
requestR_BITS_191_TO_128__q1[61] ||
requestR_BITS_191_TO_128__q1[60] ||
requestR_BITS_191_TO_128__q1[59] ||
requestR_BITS_191_TO_128__q1[58] ||
requestR_BITS_191_TO_128__q1[57] ||
requestR_BITS_191_TO_128__q1[56] ||
requestR_BITS_191_TO_128__q1[55] ||
requestR_BITS_191_TO_128__q1[54] ||
requestR_BITS_191_TO_128__q1[53] ||
requestR_BITS_191_TO_128__q1[52] ||
requestR_BITS_191_TO_128__q1[51] ||
requestR_BITS_191_TO_128__q1[50] ||
requestR_BITS_191_TO_128__q1[49] ||
requestR_BITS_191_TO_128__q1[48] ||
requestR_BITS_191_TO_128__q1[47] ||
requestR_BITS_191_TO_128__q1[46] ||
requestR_BITS_191_TO_128__q1[45] ||
requestR_BITS_191_TO_128__q1[44] ||
requestR_BITS_191_TO_128__q1[43] ||
requestR_BITS_191_TO_128__q1[42] ||
requestR_BITS_191_TO_128__q1[41] ||
requestR_BITS_191_TO_128__q1[40] ||
requestR_BITS_191_TO_128__q1[39] ||
requestR_BITS_191_TO_128__q1[38] ||
requestR_BITS_191_TO_128__q1[37] ||
requestR_BITS_191_TO_128__q1[36] ||
requestR_BITS_191_TO_128__q1[35] ||
requestR_BITS_191_TO_128__q1[34] ||
requestR_BITS_191_TO_128__q1[33] ||
requestR_BITS_191_TO_128__q1[32] ||
requestR_BITS_191_TO_128__q1[31] ||
requestR_BITS_191_TO_128__q1[30] ||
requestR_BITS_191_TO_128__q1[29] ||
requestR_BITS_191_TO_128__q1[28] ||
requestR_BITS_191_TO_128__q1[27] ||
requestR_BITS_191_TO_128__q1[26] ||
requestR_BITS_191_TO_128__q1[25] ||
requestR_BITS_191_TO_128__q1[24] ||
requestR_BITS_191_TO_128__q1[23] ||
requestR_BITS_191_TO_128__q1[22] ||
requestR_BITS_191_TO_128__q1[21] ||
requestR_BITS_191_TO_128__q1[20] ||
requestR_BITS_191_TO_128__q1[19] ||
requestR_BITS_191_TO_128__q1[18] ||
requestR_BITS_191_TO_128__q1[17] ||
requestR_BITS_191_TO_128__q1[16] ||
requestR_BITS_191_TO_128__q1[15] ||
requestR_BITS_191_TO_128__q1[14] ||
requestR_BITS_191_TO_128__q1[13] ||
requestR_BITS_191_TO_128__q1[12] ||
requestR_BITS_191_TO_128__q1[11] ||
requestR_BITS_191_TO_128__q1[10] ||
requestR_BITS_191_TO_128__q1[9] ||
requestR_BITS_191_TO_128__q1[8] ||
requestR_BITS_191_TO_128__q1[7] ||
requestR_BITS_191_TO_128__q1[6] ||
requestR_BITS_191_TO_128__q1[5] ||
requestR_BITS_191_TO_128__q1[4] ||
requestR_BITS_191_TO_128__q1[3] ||
requestR_BITS_191_TO_128__q1[2] ||
requestR_BITS_191_TO_128__q1[1] ||
requestR_BITS_191_TO_128__q1[0]) &&
_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d3069 &&
!_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d3070 &&
IF_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214__ETC___d3208 ;
assign IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d3346 =
requestR_BITS_191_TO_128__q1[62:52] == 11'd2047 &&
requestR_BITS_191_TO_128__q1[51:0] != 52'd0 ||
requestR_BITS_191_TO_128__q1[62:52] == 11'd2047 &&
requestR_BITS_191_TO_128__q1[51:0] == 52'd0 ||
(requestR_BITS_191_TO_128__q1[62:52] != 11'd0 ||
requestR_BITS_191_TO_128__q1[51:0] != 52'd0) &&
(NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d3308[23] ||
NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d3310 &&
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3329 &&
x__h112661[117:54] == 64'hFFFFFFFFFFFFFFFF) ;
assign IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d3357 =
{ IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d3346,
3'd0,
(requestR_BITS_191_TO_128__q1[62:52] != 11'd2047 ||
requestR_BITS_191_TO_128__q1[51:0] == 52'd0) &&
(requestR_BITS_191_TO_128__q1[62:52] != 11'd2047 ||
requestR_BITS_191_TO_128__q1[51:0] != 52'd0) &&
NOT_IF_requestR_3_BIT_214_4_THEN_requestR_3_BI_ETC___d3351 } ==
5'd0 ||
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d3346 ;
assign IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d48 =
{ requestR_BITS_127_TO_64__q3[63:32] == 32'hFFFFFFFF &&
requestR_BITS_127_TO_64__q3[31],
(requestR_BITS_127_TO_64__q3[63:32] == 32'hFFFFFFFF) ?
requestR_BITS_127_TO_64__q3[30:0] :
31'h7FC00000 } ;
assign IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d5294 =
requestR_BITS_191_TO_128__q1[62:52] == 11'd2047 &&
requestR_BITS_191_TO_128__q1[51:0] != 52'd0 &&
!requestR_BITS_191_TO_128__q1[51] &&
requestR_BITS_127_TO_64__q3[62:52] == 11'd2047 &&
requestR_BITS_127_TO_64__q3[51:0] != 52'd0 &&
!requestR_BITS_127_TO_64__q3[51] ;
assign IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d5302 =
requestR_BITS_191_TO_128__q1[62:52] == 11'd0 &&
requestR_BITS_191_TO_128__q1[51:0] == 52'd0 &&
requestR_BITS_191_TO_128__q1[63] &&
requestR_BITS_127_TO_64__q3[62:52] == 11'd0 &&
requestR_BITS_127_TO_64__q3[51:0] == 52'd0 &&
!requestR_BITS_127_TO_64__q3[63] ;
assign IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d5306 =
requestR_BITS_127_TO_64__q3[62:52] == 11'd0 &&
requestR_BITS_127_TO_64__q3[51:0] == 52'd0 &&
requestR_BITS_127_TO_64__q3[63] &&
requestR_BITS_191_TO_128__q1[62:52] == 11'd0 &&
requestR_BITS_191_TO_128__q1[51:0] == 52'd0 &&
!requestR_BITS_191_TO_128__q1[63] ;
assign IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d5315 =
requestR_BITS_191_TO_128__q1[62:52] <=
requestR_BITS_127_TO_64__q3[62:52] ;
assign IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d5317 =
requestR_BITS_191_TO_128__q1[62:52] ==
requestR_BITS_127_TO_64__q3[62:52] ;
assign IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d5318 =
requestR_BITS_191_TO_128__q1[51:0] <=
requestR_BITS_127_TO_64__q3[51:0] ;
assign IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d5322 =
requestR_BITS_191_TO_128__q1[62:52] <
requestR_BITS_127_TO_64__q3[62:52] ;
assign IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d5323 =
requestR_BITS_191_TO_128__q1[51:0] <
requestR_BITS_127_TO_64__q3[51:0] ;
assign IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d5339 =
requestR_BITS_191_TO_128__q1[62:52] == 11'd2047 &&
requestR_BITS_191_TO_128__q1[51:0] != 52'd0 &&
!requestR_BITS_191_TO_128__q1[51] ||
requestR_BITS_127_TO_64__q3[62:52] == 11'd2047 &&
requestR_BITS_127_TO_64__q3[51:0] != 52'd0 &&
!requestR_BITS_127_TO_64__q3[51] ;
assign IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d5363 =
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d5339 ||
requestR_BITS_191_TO_128__q1[62:52] == 11'd2047 &&
requestR_BITS_191_TO_128__q1[51] ||
requestR_BITS_127_TO_64__q3[62:52] == 11'd2047 &&
requestR_BITS_127_TO_64__q3[51] ;
assign IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d5373 =
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d5315 &&
(!IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d5317 ||
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d5318) &&
!IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d5322 &&
(!IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d5317 ||
!IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d5323) ;
assign IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d5378 =
requestR_BITS_191_TO_128__q1[62:52] == 11'd0 &&
requestR_BITS_191_TO_128__q1[51:0] == 52'd0 &&
requestR_BITS_127_TO_64__q3[62:52] == 11'd0 &&
requestR_BITS_127_TO_64__q3[51:0] == 52'd0 ||
(!requestR_BITS_191_TO_128__q1[63] ||
requestR_BITS_127_TO_64__q3[63]) &&
(requestR_BITS_191_TO_128__q1[63] ||
!requestR_BITS_127_TO_64__q3[63]) &&
(requestR_BITS_191_TO_128__q1[63] ?
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d5373 :
NOT_IF_requestR_3_BIT_214_4_THEN_requestR_3_BI_ETC___d5374) ;
assign IF_sfd___30336_BIT_1_THEN_2_ELSE_0__q85 =
sfd___3__h80336[1] ? 2'd2 : 2'd0 ;
assign IF_sfd___30336_BIT_2_THEN_2_ELSE_0__q84 =
sfd___3__h80336[2] ? 2'd2 : 2'd0 ;
assign IF_sfd___31374_BIT_7_THEN_2_ELSE_0__q56 =
sfd___3__h41374[7] ? 2'd2 : 2'd0 ;
assign IF_sfd___31374_BIT_8_THEN_2_ELSE_0__q55 =
sfd___3__h41374[8] ? 2'd2 : 2'd0 ;
assign IF_sfd___34458_BIT_7_THEN_2_ELSE_0__q42 =
sfd___3__h34458[7] ? 2'd2 : 2'd0 ;
assign IF_sfd___34458_BIT_8_THEN_2_ELSE_0__q41 =
sfd___3__h34458[8] ? 2'd2 : 2'd0 ;
assign IF_sfd___35005_BIT_10_THEN_2_ELSE_0__q12 =
sfd___3__h15005[10] ? 2'd2 : 2'd0 ;
assign IF_sfd___35005_BIT_11_THEN_2_ELSE_0__q11 =
sfd___3__h15005[11] ? 2'd2 : 2'd0 ;
assign IF_sfd___35005_BIT_39_THEN_2_ELSE_0__q10 =
sfd___3__h15005[39] ? 2'd2 : 2'd0 ;
assign IF_sfd___35005_BIT_40_THEN_2_ELSE_0__q9 =
sfd___3__h15005[40] ? 2'd2 : 2'd0 ;
assign IF_sfd___37286_BIT_10_THEN_2_ELSE_0__q28 =
sfd___3__h27286[10] ? 2'd2 : 2'd0 ;
assign IF_sfd___37286_BIT_11_THEN_2_ELSE_0__q27 =
sfd___3__h27286[11] ? 2'd2 : 2'd0 ;
assign IF_sfd___37286_BIT_39_THEN_2_ELSE_0__q26 =
sfd___3__h27286[39] ? 2'd2 : 2'd0 ;
assign IF_sfd___37286_BIT_40_THEN_2_ELSE_0__q25 =
sfd___3__h27286[40] ? 2'd2 : 2'd0 ;
assign IF_sfd___39389_BIT_1_THEN_2_ELSE_0__q71 =
sfd___3__h69389[1] ? 2'd2 : 2'd0 ;
assign IF_sfd___39389_BIT_2_THEN_2_ELSE_0__q70 =
sfd___3__h69389[2] ? 2'd2 : 2'd0 ;
assign IF_sfdin01328_BIT_4_THEN_2_ELSE_0__q155 =
sfdin__h201328[4] ? 2'd2 : 2'd0 ;
assign IF_sfdin35384_BIT_33_THEN_2_ELSE_0__q118 =
sfdin__h135384[33] ? 2'd2 : 2'd0 ;
assign IF_sfdin55725_BIT_33_THEN_2_ELSE_0__q123 =
sfdin__h155725[33] ? 2'd2 : 2'd0 ;
assign IF_theResult___snd11344_BIT_4_THEN_2_ELSE_0__q158 =
_theResult___snd__h211344[4] ? 2'd2 : 2'd0 ;
assign IF_theResult___snd45260_BIT_33_THEN_2_ELSE_0__q120 =
_theResult___snd__h145260[33] ? 2'd2 : 2'd0 ;
assign IF_theResult___snd65625_BIT_33_THEN_2_ELSE_0__q126 =
_theResult___snd__h165625[33] ? 2'd2 : 2'd0 ;
assign IF_theResult___snd90457_BIT_4_THEN_2_ELSE_0__q152 =
_theResult___snd__h190457[4] ? 2'd2 : 2'd0 ;
assign IF_x11322_BIT_53_THEN_2_ELSE_0__q115 = x__h111322[53] ? 2'd2 : 2'd0 ;
assign IF_x12661_BIT_53_THEN_2_ELSE_0__q116 = x__h112661[53] ? 2'd2 : 2'd0 ;
assign IF_x3201_BIT_53_THEN_2_ELSE_0__q95 = x__h83201[53] ? 2'd2 : 2'd0 ;
assign IF_x4058_BIT_24_THEN_2_ELSE_0__q66 = x__h44058[24] ? 2'd2 : 2'd0 ;
assign IF_x4319_BIT_53_THEN_2_ELSE_0__q96 = x__h84319[53] ? 2'd2 : 2'd0 ;
assign IF_x5414_BIT_24_THEN_2_ELSE_0__q67 = x__h45414[24] ? 2'd2 : 2'd0 ;
assign IF_x6697_BIT_24_THEN_2_ELSE_0__q68 = x__h46697[24] ? 2'd2 : 2'd0 ;
assign IF_x7815_BIT_24_THEN_2_ELSE_0__q69 = x__h47815[24] ? 2'd2 : 2'd0 ;
assign NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1750 =
-{ {12{IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1748[7]}},
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1748 } ;
assign NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1782 =
NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1750 +
20'd64 ;
assign NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1783 =
NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1782 -
20'd2 ;
assign NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1785 =
(NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1783 ^
20'h80000) <=
20'd524352 ;
assign NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1847 =
NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1782 -
20'd1 ;
assign NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1849 =
(NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1847 ^
20'h80000) <=
20'd524352 ;
assign NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1933 =
NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1750 +
20'd32 ;
assign NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1934 =
NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1933 -
20'd2 ;
assign NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1936 =
(NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1934 ^
20'h80000) <=
20'd524320 ;
assign NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1993 =
NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1933 -
20'd1 ;
assign NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1995 =
(NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1993 ^
20'h80000) <=
20'd524320 ;
assign NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2724 =
-{ {13{IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d2722[10]}},
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d2722 } ;
assign NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2756 =
NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2724 +
24'd32 ;
assign NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2757 =
NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2756 -
24'd2 ;
assign NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2759 =
(NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2757 ^
24'h800000) <=
24'd8388640 ;
assign NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2822 =
NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2756 -
24'd1 ;
assign NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2824 =
(NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2822 ^
24'h800000) <=
24'd8388640 ;
assign NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d3249 =
NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2724 +
24'd64 ;
assign NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d3250 =
NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d3249 -
24'd2 ;
assign NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d3252 =
(NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d3250 ^
24'h800000) <=
24'd8388672 ;
assign NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d3308 =
NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d3249 -
24'd1 ;
assign NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d3310 =
(NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d3308 ^
24'h800000) <=
24'd8388672 ;
assign NOT_3074_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_2_ETC___d4448 =
!_3074_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_ETC___d3421 ||
(_3074_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_ETC___d3422 ?
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_IF_requestR_3_BI_ETC___d4396[2] :
_0_CONCAT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d4408[2]) ;
assign NOT_3074_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_2_ETC___d4476 =
!_3074_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_ETC___d3421 ||
(_3074_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_ETC___d3422 ?
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_IF_requestR_3_BI_ETC___d4396[0] :
_0_CONCAT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d4408[0]) ;
assign NOT_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_ETC___d1326 =
!sfd__h28849[31] && !sfd__h28849[30] && !sfd__h28849[29] &&
!sfd__h28849[28] &&
!sfd__h28849[27] &&
!sfd__h28849[26] &&
!sfd__h28849[25] &&
!sfd__h28849[24] &&
!sfd__h28849[23] &&
!sfd__h28849[22] &&
!sfd__h28849[21] &&
!sfd__h28849[20] &&
!sfd__h28849[19] &&
!sfd__h28849[18] &&
!sfd__h28849[17] &&
!sfd__h28849[16] &&
!sfd__h28849[15] &&
!sfd__h28849[14] &&
!sfd__h28849[13] &&
!sfd__h28849[12] &&
!sfd__h28849[11] &&
!sfd__h28849[10] &&
!sfd__h28849[9] &&
!sfd__h28849[8] &&
!sfd__h28849[7] &&
!sfd__h28849[6] &&
!sfd__h28849[5] &&
!sfd__h28849[4] &&
!sfd__h28849[3] &&
!sfd__h28849[2] &&
!sfd__h28849[1] &&
!sfd__h28849[0] ||
!_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d1322 ||
_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d1324 ;
assign NOT_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_ETC___d1826 =
(sV1_exp__h1472 != 8'd0 || sV1_sfd__h1473 != 23'd0) &&
((NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1750 ==
20'd1048513) ?
_theResult_____2__h43093[64:63] != 2'b11 :
NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1783[19] ||
NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1785 &&
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1806 &&
x__h44058[88:25] == 64'h7FFFFFFFFFFFFFFF) ;
assign NOT_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_ETC___d1890 =
(sV1_exp__h1472 != 8'd0 || sV1_sfd__h1473 != 23'd0) &&
!NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1847[19] &&
(!NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1849 ||
guard__h45193 != 2'd0) ;
assign NOT_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_ETC___d1975 =
(sV1_exp__h1472 != 8'd0 || sV1_sfd__h1473 != 23'd0) &&
((NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1750 ==
20'd1048545) ?
_theResult_____2__h45956[32:31] != 2'b11 :
NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1934[19] ||
NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1936 &&
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1957 &&
x__h46697[56:25] == 32'h7FFFFFFF) ;
assign NOT_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_ETC___d2037 =
(sV1_exp__h1472 != 8'd0 || sV1_sfd__h1473 != 23'd0) &&
!NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1993[19] &&
(!NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1995 ||
guard__h47594 != 2'd0) ;
assign NOT_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_ETC___d2104 =
(sV1_exp__h1472 != 8'd0 || sV1_sfd__h1473 != 23'd0 ||
sV2_exp__h1597 != 8'd0 ||
sV2_sfd__h1598 != 23'd0) &&
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d2103 ;
assign NOT_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_ETC___d2105 =
(sV1_exp__h1472 != 8'd255 || sV1_sfd__h1473 == 23'd0) &&
(sV2_exp__h1597 != 8'd255 || sV2_sfd__h1598 == 23'd0) &&
NOT_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_ETC___d2104 ;
assign NOT_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_ETC___d2166 =
!IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2090 &&
(!IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2091 ||
!IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2092) &&
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2095 &&
(!IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2091 ||
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2097) ;
assign NOT_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_ETC___d2172 =
(sV1_exp__h1472 != 8'd255 || sV1_sfd__h1473 == 23'd0) &&
(sV2_exp__h1597 != 8'd255 || sV2_sfd__h1598 == 23'd0) &&
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2171 ;
assign NOT_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_ETC___d2192 =
(sV1_exp__h1472 != 8'd255 || sV1_sfd__h1473 == 23'd0) &&
(sV2_exp__h1597 != 8'd255 || sV2_sfd__h1598 == 23'd0) &&
(IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d2103 ||
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2171) ;
assign NOT_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_ETC___d2887 =
!sfd__h3990[63] && !sfd__h3990[62] && !sfd__h3990[61] &&
!sfd__h3990[60] &&
!sfd__h3990[59] &&
!sfd__h3990[58] &&
!sfd__h3990[57] &&
!sfd__h3990[56] &&
!sfd__h3990[55] &&
!sfd__h3990[54] &&
!sfd__h3990[53] &&
!sfd__h3990[52] &&
!sfd__h3990[51] &&
!sfd__h3990[50] &&
!sfd__h3990[49] &&
!sfd__h3990[48] &&
!sfd__h3990[47] &&
!sfd__h3990[46] &&
!sfd__h3990[45] &&
!sfd__h3990[44] &&
!sfd__h3990[43] &&
!sfd__h3990[42] &&
!sfd__h3990[41] &&
!sfd__h3990[40] &&
!sfd__h3990[39] &&
!sfd__h3990[38] &&
!sfd__h3990[37] &&
!sfd__h3990[36] &&
!sfd__h3990[35] &&
!sfd__h3990[34] &&
!sfd__h3990[33] &&
!sfd__h3990[32] &&
!sfd__h3990[31] &&
!sfd__h3990[30] &&
!sfd__h3990[29] &&
!sfd__h3990[28] &&
!sfd__h3990[27] &&
!sfd__h3990[26] &&
!sfd__h3990[25] &&
!sfd__h3990[24] &&
!sfd__h3990[23] &&
!sfd__h3990[22] &&
!sfd__h3990[21] &&
!sfd__h3990[20] &&
!sfd__h3990[19] &&
!sfd__h3990[18] &&
!sfd__h3990[17] &&
!sfd__h3990[16] &&
!sfd__h3990[15] &&
!sfd__h3990[14] &&
!sfd__h3990[13] &&
!sfd__h3990[12] &&
!sfd__h3990[11] &&
!sfd__h3990[10] &&
!sfd__h3990[9] &&
!sfd__h3990[8] &&
!sfd__h3990[7] &&
!sfd__h3990[6] &&
!sfd__h3990[5] &&
!sfd__h3990[4] &&
!sfd__h3990[3] &&
!sfd__h3990[2] &&
!sfd__h3990[1] &&
!sfd__h3990[0] ||
!_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d2883 ||
_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d2885 ;
assign NOT_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_ETC___d449 =
!sfd__h3990[63] && !sfd__h3990[62] && !sfd__h3990[61] &&
!sfd__h3990[60] &&
!sfd__h3990[59] &&
!sfd__h3990[58] &&
!sfd__h3990[57] &&
!sfd__h3990[56] &&
!sfd__h3990[55] &&
!sfd__h3990[54] &&
!sfd__h3990[53] &&
!sfd__h3990[52] &&
!sfd__h3990[51] &&
!sfd__h3990[50] &&
!sfd__h3990[49] &&
!sfd__h3990[48] &&
!sfd__h3990[47] &&
!sfd__h3990[46] &&
!sfd__h3990[45] &&
!sfd__h3990[44] &&
!sfd__h3990[43] &&
!sfd__h3990[42] &&
!sfd__h3990[41] &&
!sfd__h3990[40] &&
!sfd__h3990[39] &&
!sfd__h3990[38] &&
!sfd__h3990[37] &&
!sfd__h3990[36] &&
!sfd__h3990[35] &&
!sfd__h3990[34] &&
!sfd__h3990[33] &&
!sfd__h3990[32] &&
!sfd__h3990[31] &&
!sfd__h3990[30] &&
!sfd__h3990[29] &&
!sfd__h3990[28] &&
!sfd__h3990[27] &&
!sfd__h3990[26] &&
!sfd__h3990[25] &&
!sfd__h3990[24] &&
!sfd__h3990[23] &&
!sfd__h3990[22] &&
!sfd__h3990[21] &&
!sfd__h3990[20] &&
!sfd__h3990[19] &&
!sfd__h3990[18] &&
!sfd__h3990[17] &&
!sfd__h3990[16] &&
!sfd__h3990[15] &&
!sfd__h3990[14] &&
!sfd__h3990[13] &&
!sfd__h3990[12] &&
!sfd__h3990[11] &&
!sfd__h3990[10] &&
!sfd__h3990[9] &&
!sfd__h3990[8] &&
!sfd__h3990[7] &&
!sfd__h3990[6] &&
!sfd__h3990[5] &&
!sfd__h3990[4] &&
!sfd__h3990[3] &&
!sfd__h3990[2] &&
!sfd__h3990[1] &&
!sfd__h3990[0] ||
!_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d445 ||
_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d447 ;
assign NOT_IF_requestR_3_BIT_214_4_THEN_requestR_3_BI_ETC___d1059 =
!requestR_BITS_191_TO_128__q1[63] &&
!requestR_BITS_191_TO_128__q1[62] &&
!requestR_BITS_191_TO_128__q1[61] &&
!requestR_BITS_191_TO_128__q1[60] &&
!requestR_BITS_191_TO_128__q1[59] &&
!requestR_BITS_191_TO_128__q1[58] &&
!requestR_BITS_191_TO_128__q1[57] &&
!requestR_BITS_191_TO_128__q1[56] &&
!requestR_BITS_191_TO_128__q1[55] &&
!requestR_BITS_191_TO_128__q1[54] &&
!requestR_BITS_191_TO_128__q1[53] &&
!requestR_BITS_191_TO_128__q1[52] &&
!requestR_BITS_191_TO_128__q1[51] &&
!requestR_BITS_191_TO_128__q1[50] &&
!requestR_BITS_191_TO_128__q1[49] &&
!requestR_BITS_191_TO_128__q1[48] &&
!requestR_BITS_191_TO_128__q1[47] &&
!requestR_BITS_191_TO_128__q1[46] &&
!requestR_BITS_191_TO_128__q1[45] &&
!requestR_BITS_191_TO_128__q1[44] &&
!requestR_BITS_191_TO_128__q1[43] &&
!requestR_BITS_191_TO_128__q1[42] &&
!requestR_BITS_191_TO_128__q1[41] &&
!requestR_BITS_191_TO_128__q1[40] &&
!requestR_BITS_191_TO_128__q1[39] &&
!requestR_BITS_191_TO_128__q1[38] &&
!requestR_BITS_191_TO_128__q1[37] &&
!requestR_BITS_191_TO_128__q1[36] &&
!requestR_BITS_191_TO_128__q1[35] &&
!requestR_BITS_191_TO_128__q1[34] &&
!requestR_BITS_191_TO_128__q1[33] &&
!requestR_BITS_191_TO_128__q1[32] &&
!requestR_BITS_191_TO_128__q1[31] &&
!requestR_BITS_191_TO_128__q1[30] &&
!requestR_BITS_191_TO_128__q1[29] &&
!requestR_BITS_191_TO_128__q1[28] &&
!requestR_BITS_191_TO_128__q1[27] &&
!requestR_BITS_191_TO_128__q1[26] &&
!requestR_BITS_191_TO_128__q1[25] &&
!requestR_BITS_191_TO_128__q1[24] &&
!requestR_BITS_191_TO_128__q1[23] &&
!requestR_BITS_191_TO_128__q1[22] &&
!requestR_BITS_191_TO_128__q1[21] &&
!requestR_BITS_191_TO_128__q1[20] &&
!requestR_BITS_191_TO_128__q1[19] &&
!requestR_BITS_191_TO_128__q1[18] &&
!requestR_BITS_191_TO_128__q1[17] &&
!requestR_BITS_191_TO_128__q1[16] &&
!requestR_BITS_191_TO_128__q1[15] &&
!requestR_BITS_191_TO_128__q1[14] &&
!requestR_BITS_191_TO_128__q1[13] &&
!requestR_BITS_191_TO_128__q1[12] &&
!requestR_BITS_191_TO_128__q1[11] &&
!requestR_BITS_191_TO_128__q1[10] &&
!requestR_BITS_191_TO_128__q1[9] &&
!requestR_BITS_191_TO_128__q1[8] &&
!requestR_BITS_191_TO_128__q1[7] &&
!requestR_BITS_191_TO_128__q1[6] &&
!requestR_BITS_191_TO_128__q1[5] &&
!requestR_BITS_191_TO_128__q1[4] &&
!requestR_BITS_191_TO_128__q1[3] &&
!requestR_BITS_191_TO_128__q1[2] &&
!requestR_BITS_191_TO_128__q1[1] &&
!requestR_BITS_191_TO_128__q1[0] ||
!_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d970 ||
_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d971 ;
assign NOT_IF_requestR_3_BIT_214_4_THEN_requestR_3_BI_ETC___d1666 =
!requestR_BITS_191_TO_128__q1[31] &&
!requestR_BITS_191_TO_128__q1[30] &&
!requestR_BITS_191_TO_128__q1[29] &&
!requestR_BITS_191_TO_128__q1[28] &&
!requestR_BITS_191_TO_128__q1[27] &&
!requestR_BITS_191_TO_128__q1[26] &&
!requestR_BITS_191_TO_128__q1[25] &&
!requestR_BITS_191_TO_128__q1[24] &&
!requestR_BITS_191_TO_128__q1[23] &&
!requestR_BITS_191_TO_128__q1[22] &&
!requestR_BITS_191_TO_128__q1[21] &&
!requestR_BITS_191_TO_128__q1[20] &&
!requestR_BITS_191_TO_128__q1[19] &&
!requestR_BITS_191_TO_128__q1[18] &&
!requestR_BITS_191_TO_128__q1[17] &&
!requestR_BITS_191_TO_128__q1[16] &&
!requestR_BITS_191_TO_128__q1[15] &&
!requestR_BITS_191_TO_128__q1[14] &&
!requestR_BITS_191_TO_128__q1[13] &&
!requestR_BITS_191_TO_128__q1[12] &&
!requestR_BITS_191_TO_128__q1[11] &&
!requestR_BITS_191_TO_128__q1[10] &&
!requestR_BITS_191_TO_128__q1[9] &&
!requestR_BITS_191_TO_128__q1[8] &&
!requestR_BITS_191_TO_128__q1[7] &&
!requestR_BITS_191_TO_128__q1[6] &&
!requestR_BITS_191_TO_128__q1[5] &&
!requestR_BITS_191_TO_128__q1[4] &&
!requestR_BITS_191_TO_128__q1[3] &&
!requestR_BITS_191_TO_128__q1[2] &&
!requestR_BITS_191_TO_128__q1[1] &&
!requestR_BITS_191_TO_128__q1[0] ||
!_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d1578 ||
_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d1579 ;
assign NOT_IF_requestR_3_BIT_214_4_THEN_requestR_3_BI_ETC___d2801 =
(requestR_BITS_191_TO_128__q1[62:52] != 11'd0 ||
requestR_BITS_191_TO_128__q1[51:0] != 52'd0) &&
((NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2724 ==
24'd16777185) ?
_theResult_____2__h82460[32:31] != 2'b11 :
NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2757[23] ||
NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2759 &&
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2780 &&
x__h83201[85:54] == 32'h7FFFFFFF) ;
assign NOT_IF_requestR_3_BIT_214_4_THEN_requestR_3_BI_ETC___d2866 =
(requestR_BITS_191_TO_128__q1[62:52] != 11'd0 ||
requestR_BITS_191_TO_128__q1[51:0] != 52'd0) &&
!NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2822[23] &&
(!NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2824 ||
guard__h84098 != 2'd0) ;
assign NOT_IF_requestR_3_BIT_214_4_THEN_requestR_3_BI_ETC___d3156 =
!requestR_BITS_191_TO_128__q1[63] &&
!requestR_BITS_191_TO_128__q1[62] &&
!requestR_BITS_191_TO_128__q1[61] &&
!requestR_BITS_191_TO_128__q1[60] &&
!requestR_BITS_191_TO_128__q1[59] &&
!requestR_BITS_191_TO_128__q1[58] &&
!requestR_BITS_191_TO_128__q1[57] &&
!requestR_BITS_191_TO_128__q1[56] &&
!requestR_BITS_191_TO_128__q1[55] &&
!requestR_BITS_191_TO_128__q1[54] &&
!requestR_BITS_191_TO_128__q1[53] &&
!requestR_BITS_191_TO_128__q1[52] &&
!requestR_BITS_191_TO_128__q1[51] &&
!requestR_BITS_191_TO_128__q1[50] &&
!requestR_BITS_191_TO_128__q1[49] &&
!requestR_BITS_191_TO_128__q1[48] &&
!requestR_BITS_191_TO_128__q1[47] &&
!requestR_BITS_191_TO_128__q1[46] &&
!requestR_BITS_191_TO_128__q1[45] &&
!requestR_BITS_191_TO_128__q1[44] &&
!requestR_BITS_191_TO_128__q1[43] &&
!requestR_BITS_191_TO_128__q1[42] &&
!requestR_BITS_191_TO_128__q1[41] &&
!requestR_BITS_191_TO_128__q1[40] &&
!requestR_BITS_191_TO_128__q1[39] &&
!requestR_BITS_191_TO_128__q1[38] &&
!requestR_BITS_191_TO_128__q1[37] &&
!requestR_BITS_191_TO_128__q1[36] &&
!requestR_BITS_191_TO_128__q1[35] &&
!requestR_BITS_191_TO_128__q1[34] &&
!requestR_BITS_191_TO_128__q1[33] &&
!requestR_BITS_191_TO_128__q1[32] &&
!requestR_BITS_191_TO_128__q1[31] &&
!requestR_BITS_191_TO_128__q1[30] &&
!requestR_BITS_191_TO_128__q1[29] &&
!requestR_BITS_191_TO_128__q1[28] &&
!requestR_BITS_191_TO_128__q1[27] &&
!requestR_BITS_191_TO_128__q1[26] &&
!requestR_BITS_191_TO_128__q1[25] &&
!requestR_BITS_191_TO_128__q1[24] &&
!requestR_BITS_191_TO_128__q1[23] &&
!requestR_BITS_191_TO_128__q1[22] &&
!requestR_BITS_191_TO_128__q1[21] &&
!requestR_BITS_191_TO_128__q1[20] &&
!requestR_BITS_191_TO_128__q1[19] &&
!requestR_BITS_191_TO_128__q1[18] &&
!requestR_BITS_191_TO_128__q1[17] &&
!requestR_BITS_191_TO_128__q1[16] &&
!requestR_BITS_191_TO_128__q1[15] &&
!requestR_BITS_191_TO_128__q1[14] &&
!requestR_BITS_191_TO_128__q1[13] &&
!requestR_BITS_191_TO_128__q1[12] &&
!requestR_BITS_191_TO_128__q1[11] &&
!requestR_BITS_191_TO_128__q1[10] &&
!requestR_BITS_191_TO_128__q1[9] &&
!requestR_BITS_191_TO_128__q1[8] &&
!requestR_BITS_191_TO_128__q1[7] &&
!requestR_BITS_191_TO_128__q1[6] &&
!requestR_BITS_191_TO_128__q1[5] &&
!requestR_BITS_191_TO_128__q1[4] &&
!requestR_BITS_191_TO_128__q1[3] &&
!requestR_BITS_191_TO_128__q1[2] &&
!requestR_BITS_191_TO_128__q1[1] &&
!requestR_BITS_191_TO_128__q1[0] ||
!_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d3069 ||
_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d3070 ;
assign NOT_IF_requestR_3_BIT_214_4_THEN_requestR_3_BI_ETC___d3290 =
(requestR_BITS_191_TO_128__q1[62:52] != 11'd0 ||
requestR_BITS_191_TO_128__q1[51:0] != 52'd0) &&
((NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2724 ==
24'd16777153) ?
_theResult_____2__h110357[64:63] != 2'b11 :
NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d3250[23] ||
NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d3252 &&
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3273 &&
x__h111322[117:54] == 64'h7FFFFFFFFFFFFFFF) ;
assign NOT_IF_requestR_3_BIT_214_4_THEN_requestR_3_BI_ETC___d3351 =
(requestR_BITS_191_TO_128__q1[62:52] != 11'd0 ||
requestR_BITS_191_TO_128__q1[51:0] != 52'd0) &&
!NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d3308[23] &&
(!NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d3310 ||
guard__h112440 != 2'd0) ;
assign NOT_IF_requestR_3_BIT_214_4_THEN_requestR_3_BI_ETC___d5330 =
(requestR_BITS_191_TO_128__q1[62:52] != 11'd2047 ||
requestR_BITS_191_TO_128__q1[51:0] == 52'd0) &&
(requestR_BITS_127_TO_64__q3[62:52] != 11'd2047 ||
requestR_BITS_127_TO_64__q3[51:0] == 52'd0) &&
(requestR_BITS_191_TO_128__q1[62:52] != 11'd0 ||
requestR_BITS_191_TO_128__q1[51:0] != 52'd0 ||
requestR_BITS_127_TO_64__q3[62:52] != 11'd0 ||
requestR_BITS_127_TO_64__q3[51:0] != 52'd0) &&
(requestR_BITS_191_TO_128__q1[63] &&
!requestR_BITS_127_TO_64__q3[63] ||
(requestR_BITS_191_TO_128__q1[63] ||
!requestR_BITS_127_TO_64__q3[63]) &&
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d5326) ;
assign NOT_IF_requestR_3_BIT_214_4_THEN_requestR_3_BI_ETC___d5374 =
!IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d5322 &&
(!IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d5317 ||
!IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d5323) &&
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d5315 &&
(!IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d5317 ||
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d5318) ;
assign NOT_IF_requestR_3_BIT_214_4_THEN_requestR_3_BI_ETC___d5399 =
(requestR_BITS_191_TO_128__q1[62:52] != 11'd2047 ||
requestR_BITS_191_TO_128__q1[51:0] == 52'd0) &&
(requestR_BITS_127_TO_64__q3[62:52] != 11'd2047 ||
requestR_BITS_127_TO_64__q3[51:0] == 52'd0) &&
(requestR_BITS_191_TO_128__q1[63] &&
!requestR_BITS_127_TO_64__q3[63] ||
(requestR_BITS_191_TO_128__q1[63] ||
!requestR_BITS_127_TO_64__q3[63]) &&
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d5326 ||
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d5378) ;
assign NOT_verbosity_ULE_1_6___d27 = verbosity > 4'd1 ;
assign NOT_verbosity_ULE_2_01___d702 = verbosity > 4'd2 ;
assign SEXT_IF_IF_requestR_3_BIT_214_4_THEN_requestR__ETC___d4684 =
{ {4{IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1748[7]}},
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1748 } ;
assign SEXT_IF_IF_requestR_3_BIT_214_4_THEN_requestR__ETC___d4685 =
(SEXT_IF_IF_requestR_3_BIT_214_4_THEN_requestR__ETC___d4684 ^
12'h800) <=
12'd3071 ;
assign SEXT_IF_IF_requestR_3_BIT_214_4_THEN_requestR__ETC___d4686 =
(SEXT_IF_IF_requestR_3_BIT_214_4_THEN_requestR__ETC___d4684 ^
12'h800) <
12'd1026 ;
assign SEXT_IF_IF_requestR_3_BIT_214_4_THEN_requestR__ETC__q153 =
SEXT_IF_IF_requestR_3_BIT_214_4_THEN_requestR__ETC___d4684 +
12'd1023 ;
assign SEXT_IF_IF_requestR_3_BIT_214_4_THEN_requestR__ETC__q156 =
SEXT_IF_IF_requestR_3_BIT_214_4_THEN_requestR__ETC__q153[10:0] -
11'd1023 ;
assign SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_3_B_ETC___d3851 =
{ IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d2722[10],
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d2722 } ;
assign SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_3_B_ETC___d3852 =
(SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_3_B_ETC___d3851 ^
12'h800) <=
12'd2175 ;
assign SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_3_B_ETC___d3853 =
(SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_3_B_ETC___d3851 ^
12'h800) <
12'd1922 ;
assign SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_3_B_ETC__q121 =
SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_3_B_ETC___d3851 +
12'd127 ;
assign SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_3_B_ETC__q124 =
SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_3_B_ETC__q121[7:0] -
8'd127 ;
assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_IF_requestR_3_BI_ETC___d3656 =
({ 3'd0,
IF_IF_0b0_CONCAT_NOT_IF_requestR_3_BIT_214_4_T_ETC___d3654 } ^
9'h100) <=
9'd256 ;
assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_IF_requestR_3_BI_ETC___d4396 =
{ 3'd0,
_theResult___fst_exp__h135390 == 8'd0 &&
(sfdin__h135384[56:34] == 23'd0 || guard__h126038 != 2'b0),
1'd0 } |
{ 2'd0,
_theResult___fst_exp__h136017 == 8'd255 &&
_theResult___fst_sfd__h136018 == 23'd0,
1'd0,
_theResult___fst_exp__h135390 != 8'd255 &&
guard__h126038 != 2'b0 } ;
assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_IF_requestR__ETC___d4935 =
({ 6'd0,
IF_IF_3074_MINUS_SEXT_IF_IF_requestR_3_BIT_214_ETC___d4933 } ^
12'h800) <=
12'd2048 ;
assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_IF_requestR__ETC___d5220 =
{ 3'd0,
_theResult___fst_exp__h201334 == 11'd0 &&
(sfdin__h201328[56:5] == 52'd0 || guard__h191853 != 2'b0),
1'd0 } |
{ 2'd0,
_theResult___fst_exp__h202164 == 11'd2047 &&
_theResult___fst_sfd__h202165 == 52'd0,
1'd0,
_theResult___fst_exp__h201334 != 11'd2047 &&
guard__h191853 != 2'b0 } ;
assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_IF_requestR_3_B_ETC___d4100 =
({ 3'd0,
IF_IF_3970_MINUS_SEXT_IF_requestR_3_BIT_214_4__ETC___d4098 } ^
9'h100) <=
9'd256 ;
assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_IF_requestR_3_B_ETC___d4425 =
{ 3'd0,
_theResult___fst_exp__h155731 == 8'd0 &&
(sfdin__h155725[56:34] == 23'd0 || guard__h146250 != 2'b0),
1'd0 } |
{ 2'd0,
_theResult___fst_exp__h156358 == 8'd255 &&
_theResult___fst_sfd__h156359 == 23'd0,
1'd0,
_theResult___fst_exp__h155731 != 8'd255 &&
guard__h146250 != 2'b0 } ;
assign _0_CONCAT_IF_IF_IF_requestR_3_BIT_214_4_THEN_re_ETC___d4615 =
({ 6'd0,
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d4613 } ^
12'h800) <=
12'd2944 ;
assign _0_CONCAT_IF_IF_IF_requestR_3_BIT_214_4_THEN_re_ETC___d5008 =
({ 6'd0,
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d4613 } ^
12'h800) <=
(IF_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reques_ETC___d5007 ^
12'h800) ;
assign _0_CONCAT_IF_IF_IF_requestR_3_BIT_214_4_THEN_re_ETC___d5203 =
{ 3'd0,
_theResult___fst_exp__h190506 == 11'd0 &&
guard__h181312 != 2'b0,
1'd0 } |
{ 2'd0,
_theResult___fst_exp__h191262 == 11'd2047 &&
_theResult___fst_sfd__h191263 == 52'd0,
1'd0,
_theResult___fst_exp__h190506 != 11'd2047 &&
guard__h181312 != 2'b0 } ;
assign _0_CONCAT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d3778 =
({ 3'd0,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3776 } ^
9'h100) <=
9'd384 ;
assign _0_CONCAT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d4173 =
({ 3'd0,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3776 } ^
9'h100) <=
(IF_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR__ETC___d4172 ^
9'h100) ;
assign _0_CONCAT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d4408 =
{ 3'd0,
_theResult___fst_exp__h145309 == 8'd0 &&
guard__h136028 != 2'b0,
1'd0 } |
{ 2'd0,
_theResult___fst_exp__h145862 == 8'd255 &&
_theResult___fst_sfd__h145863 == 23'd0,
1'd0,
_theResult___fst_exp__h145309 != 8'd255 &&
guard__h136028 != 2'b0 } ;
assign _0b0_CONCAT_NOT_IF_IF_requestR_3_BIT_214_4_THEN_ETC___d4691 =
b__h46021 >>
_3074_MINUS_SEXT_IF_IF_requestR_3_BIT_214_4_THE_ETC___d4687 ;
assign _0b0_CONCAT_NOT_IF_requestR_3_BIT_214_4_THEN_re_ETC___d3858 =
sfd__h117253 >>
_3970_MINUS_SEXT_IF_requestR_3_BIT_214_4_THEN_r_ETC___d3854 ;
assign _1_CONCAT_DONTCARE_CONCAT_IF_requestR_3_BIT_214_ETC___d97 =
{ 33'h1AAAAAAAA,
requestR_BITS_63_TO_0__q8[63:32] == 32'hFFFFFFFF &&
requestR_BITS_63_TO_0__q8[31],
(requestR_BITS_63_TO_0__q8[63:32] == 32'hFFFFFFFF) ?
requestR_BITS_63_TO_0__q8[30:0] :
31'h7FC00000 } ;
assign _3074_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_ETC___d3420 =
12'd3074 -
{ 6'd0,
requestR_BITS_191_TO_128__q1[51] ?
6'd0 :
(requestR_BITS_191_TO_128__q1[50] ?
6'd1 :
(requestR_BITS_191_TO_128__q1[49] ?
6'd2 :
(requestR_BITS_191_TO_128__q1[48] ?
6'd3 :
(requestR_BITS_191_TO_128__q1[47] ?
6'd4 :
(requestR_BITS_191_TO_128__q1[46] ?
6'd5 :
(requestR_BITS_191_TO_128__q1[45] ?
6'd6 :
(requestR_BITS_191_TO_128__q1[44] ?
6'd7 :
(requestR_BITS_191_TO_128__q1[43] ?
6'd8 :
(requestR_BITS_191_TO_128__q1[42] ?
6'd9 :
(requestR_BITS_191_TO_128__q1[41] ?
6'd10 :
(requestR_BITS_191_TO_128__q1[40] ?
6'd11 :
(requestR_BITS_191_TO_128__q1[39] ?
6'd12 :
(requestR_BITS_191_TO_128__q1[38] ?
6'd13 :
(requestR_BITS_191_TO_128__q1[37] ?
6'd14 :
(requestR_BITS_191_TO_128__q1[36] ?
6'd15 :
(requestR_BITS_191_TO_128__q1[35] ?
6'd16 :
(requestR_BITS_191_TO_128__q1[34] ?
6'd17 :
(requestR_BITS_191_TO_128__q1[33] ?
6'd18 :
(requestR_BITS_191_TO_128__q1[32] ?
6'd19 :
(requestR_BITS_191_TO_128__q1[31] ?
6'd20 :
(requestR_BITS_191_TO_128__q1[30] ?
6'd21 :
(requestR_BITS_191_TO_128__q1[29] ?
6'd22 :
(requestR_BITS_191_TO_128__q1[28] ?
6'd23 :
(requestR_BITS_191_TO_128__q1[27] ?
6'd24 :
(requestR_BITS_191_TO_128__q1[26] ?
6'd25 :
(requestR_BITS_191_TO_128__q1[25] ?
6'd26 :
(requestR_BITS_191_TO_128__q1[24] ?
6'd27 :
(requestR_BITS_191_TO_128__q1[23] ?
6'd28 :
(requestR_BITS_191_TO_128__q1[22] ?
6'd29 :
(requestR_BITS_191_TO_128__q1[21] ?
6'd30 :
(requestR_BITS_191_TO_128__q1[20] ?
6'd31 :
(requestR_BITS_191_TO_128__q1[19] ?
6'd32 :
(requestR_BITS_191_TO_128__q1[18] ?
6'd33 :
(requestR_BITS_191_TO_128__q1[17] ?
6'd34 :
(requestR_BITS_191_TO_128__q1[16] ?
6'd35 :
(requestR_BITS_191_TO_128__q1[15] ?
6'd36 :
(requestR_BITS_191_TO_128__q1[14] ?
6'd37 :
(requestR_BITS_191_TO_128__q1[13] ?
6'd38 :
(requestR_BITS_191_TO_128__q1[12] ?
6'd39 :
(requestR_BITS_191_TO_128__q1[11] ?
6'd40 :
(requestR_BITS_191_TO_128__q1[10] ?
6'd41 :
(requestR_BITS_191_TO_128__q1[9] ?
6'd42 :
(requestR_BITS_191_TO_128__q1[8] ?
6'd43 :
(requestR_BITS_191_TO_128__q1[7] ?
6'd44 :
(requestR_BITS_191_TO_128__q1[6] ?
6'd45 :
(requestR_BITS_191_TO_128__q1[5] ?
6'd46 :
(requestR_BITS_191_TO_128__q1[4] ?
6'd47 :
(requestR_BITS_191_TO_128__q1[3] ?
6'd48 :
(requestR_BITS_191_TO_128__q1[2] ?
6'd49 :
(requestR_BITS_191_TO_128__q1[1] ?
6'd50 :
(requestR_BITS_191_TO_128__q1[0] ?
6'd51 :
6'd52))))))))))))))))))))))))))))))))))))))))))))))))))) } ;
assign _3074_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_ETC___d3421 =
(_3074_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_ETC___d3420 ^
12'h800) <=
12'd2175 ;
assign _3074_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_ETC___d3422 =
(_3074_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_ETC___d3420 ^
12'h800) <
12'd1922 ;
assign _3074_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_ETC___d4411 =
_3074_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_ETC___d3421 &&
(_3074_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_ETC___d3422 ?
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_IF_requestR_3_BI_ETC___d4396[4] :
_0_CONCAT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d4408[4]) ;
assign _3074_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_ETC___d4436 =
_3074_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_ETC___d3421 &&
(_3074_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_ETC___d3422 ?
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_IF_requestR_3_BI_ETC___d4396[3] :
_0_CONCAT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d4408[3]) ;
assign _3074_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_ETC___d4463 =
_3074_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_ETC___d3421 &&
(_3074_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_ETC___d3422 ?
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_IF_requestR_3_BI_ETC___d4396[1] :
_0_CONCAT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d4408[1]) ;
assign _3074_MINUS_SEXT_IF_IF_requestR_3_BIT_214_4_THE_ETC___d4687 =
12'd3074 -
SEXT_IF_IF_requestR_3_BIT_214_4_THEN_requestR__ETC___d4684 ;
assign _32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d1321 =
(9'd32 -
{ 3'd0,
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d1318 }) -
9'd1 ;
assign _32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d1322 =
(_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d1321 ^
9'h100) <=
9'd383 ;
assign _32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d1324 =
(_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d1321 ^
9'h100) <
9'd107 ;
assign _32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d1327 =
(_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d1321 ^
9'h100) <
9'd130 ;
assign _32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d2342 =
(12'd32 -
{ 6'd0,
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d2339 }) -
12'd1 ;
assign _32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d2343 =
(_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d2342 ^
12'h800) <=
12'd3071 ;
assign _32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d2345 =
(_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d2342 ^
12'h800) <
12'd974 ;
assign _32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d2347 =
(_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d2342 ^
12'h800) <
12'd1026 ;
assign _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d1577 =
(9'd32 -
{ 3'd0,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1574 }) -
9'd1 ;
assign _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d1578 =
(_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d1577 ^
9'h100) <=
9'd383 ;
assign _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d1579 =
(_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d1577 ^
9'h100) <
9'd107 ;
assign _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d1580 =
(_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d1577 ^
9'h100) <
9'd130 ;
assign _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d2558 =
(12'd32 -
{ 6'd0,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2555 }) -
12'd1 ;
assign _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d2559 =
(_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d2558 ^
12'h800) <=
12'd3071 ;
assign _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d2560 =
(_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d2558 ^
12'h800) <
12'd974 ;
assign _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d2561 =
(_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d2558 ^
12'h800) <
12'd1026 ;
assign _3970_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_21_ETC___d4541 =
12'd3970 -
{ 7'd0,
sV1_sfd__h1473[22] ?
5'd0 :
(sV1_sfd__h1473[21] ?
5'd1 :
(sV1_sfd__h1473[20] ?
5'd2 :
(sV1_sfd__h1473[19] ?
5'd3 :
(sV1_sfd__h1473[18] ?
5'd4 :
(sV1_sfd__h1473[17] ?
5'd5 :
(sV1_sfd__h1473[16] ?
5'd6 :
(sV1_sfd__h1473[15] ?
5'd7 :
(sV1_sfd__h1473[14] ?
5'd8 :
(sV1_sfd__h1473[13] ?
5'd9 :
(sV1_sfd__h1473[12] ?
5'd10 :
(sV1_sfd__h1473[11] ?
5'd11 :
(sV1_sfd__h1473[10] ?
5'd12 :
(sV1_sfd__h1473[9] ?
5'd13 :
(sV1_sfd__h1473[8] ?
5'd14 :
(sV1_sfd__h1473[7] ?
5'd15 :
(sV1_sfd__h1473[6] ?
5'd16 :
(sV1_sfd__h1473[5] ?
5'd17 :
(sV1_sfd__h1473[4] ?
5'd18 :
(sV1_sfd__h1473[3] ?
5'd19 :
(sV1_sfd__h1473[2] ?
5'd20 :
(sV1_sfd__h1473[1] ?
5'd21 :
(sV1_sfd__h1473[0] ?
5'd22 :
5'd23)))))))))))))))))))))) } ;
assign _3970_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_21_ETC___d4542 =
(_3970_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_21_ETC___d4541 ^
12'h800) <=
12'd3071 ;
assign _3970_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_21_ETC___d4543 =
(_3970_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_21_ETC___d4541 ^
12'h800) <
12'd1026 ;
assign _3970_MINUS_SEXT_IF_requestR_3_BIT_214_4_THEN_r_ETC___d3854 =
12'd3970 -
SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_3_B_ETC___d3851 ;
assign _64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d2882 =
(12'd64 -
{ 5'd0,
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d441 }) -
12'd1 ;
assign _64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d2883 =
(_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d2882 ^
12'h800) <=
12'd3071 ;
assign _64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d2885 =
(_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d2882 ^
12'h800) <
12'd974 ;
assign _64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d2888 =
(_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d2882 ^
12'h800) <
12'd1026 ;
assign _64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d444 =
(9'd64 -
{ 2'd0,
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d441 }) -
9'd1 ;
assign _64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d445 =
(_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d444 ^
9'h100) <=
9'd383 ;
assign _64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d447 =
(_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d444 ^
9'h100) <
9'd107 ;
assign _64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d450 =
(_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d444 ^
9'h100) <
9'd130 ;
assign _64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d3068 =
(12'd64 -
{ 5'd0,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d966 }) -
12'd1 ;
assign _64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d3069 =
(_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d3068 ^
12'h800) <=
12'd3071 ;
assign _64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d3070 =
(_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d3068 ^
12'h800) <
12'd974 ;
assign _64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d3071 =
(_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d3068 ^
12'h800) <
12'd1026 ;
assign _64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d969 =
(9'd64 -
{ 2'd0,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d966 }) -
9'd1 ;
assign _64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d970 =
(_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d969 ^
9'h100) <=
9'd383 ;
assign _64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d971 =
(_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d969 ^
9'h100) <
9'd107 ;
assign _64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d972 =
(_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d969 ^
9'h100) <
9'd130 ;
assign _theResult_____2__h110357 =
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3241 ?
out1___1__h111073 :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3224[117:53] ;
assign _theResult_____2__h43093 =
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1774 ?
out1___1__h43809 :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1757[88:24] ;
assign _theResult_____2__h45956 =
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1925 ?
out1___1__h46448 :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1908[56:24] ;
assign _theResult_____2__h82460 =
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2748 ?
out1___1__h82952 :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2731[85:53] ;
assign _theResult____h126028 =
(value__h82527 == 54'd0) ? sfd__h117253 : 57'd1 ;
assign _theResult____h146240 =
((_3970_MINUS_SEXT_IF_requestR_3_BIT_214_4_THEN_r_ETC___d3854 ^
12'h800) <
12'd2105) ?
result__h146853 :
_theResult____h126028 ;
assign _theResult____h191843 =
((_3074_MINUS_SEXT_IF_IF_requestR_3_BIT_214_4_THE_ETC___d4687 ^
12'h800) <
12'd2105) ?
result__h192456 :
((value__h43160 == 25'd0) ? b__h46021 : 57'd1) ;
assign _theResult___exp__h108862 =
(sfd__h108263[53] || sfd__h108263[53:52] == 2'b01) ?
11'd1 :
11'd0 ;
assign _theResult___exp__h109617 =
sfd__h109005[53] ?
((x__h108990[10:0] == 11'd2046) ?
11'd2047 :
din_inc___2_exp__h109755) :
((x__h108990[10:0] == 11'd0 && sfd__h109005[53:52] == 2'b01) ?
11'd1 :
x__h108990[10:0]) ;
assign _theResult___exp__h135916 =
sfd__h135482[24] ?
((_theResult___fst_exp__h135390 == 8'd254) ?
8'd255 :
din_inc___2_exp__h166288) :
((_theResult___fst_exp__h135390 == 8'd0 &&
sfd__h135482[24:23] == 2'b01) ?
8'd1 :
_theResult___fst_exp__h135390) ;
assign _theResult___exp__h145761 =
sfd__h145327[24] ?
((_theResult___fst_exp__h145309 == 8'd254) ?
8'd255 :
din_inc___2_exp__h166312) :
((_theResult___fst_exp__h145309 == 8'd0 &&
sfd__h145327[24:23] == 2'b01) ?
8'd1 :
_theResult___fst_exp__h145309) ;
assign _theResult___exp__h15431 =
(sfd__h15032[24] || sfd__h15032[24:23] == 2'b01) ? 8'd1 : 8'd0 ;
assign _theResult___exp__h156257 =
sfd__h155823[24] ?
((_theResult___fst_exp__h155731 == 8'd254) ?
8'd255 :
din_inc___2_exp__h166342) :
((_theResult___fst_exp__h155731 == 8'd0 &&
sfd__h155823[24:23] == 2'b01) ?
8'd1 :
_theResult___fst_exp__h155731) ;
assign _theResult___exp__h15984 =
sfd__h15575[24] ?
((x__h15560[7:0] == 8'd254) ?
8'd255 :
din_inc___2_exp__h16127) :
((x__h15560[7:0] == 8'd0 && sfd__h15575[24:23] == 2'b01) ?
8'd1 :
x__h15560[7:0]) ;
assign _theResult___exp__h166156 =
sfd__h165698[24] ?
((_theResult___fst_exp__h165679 == 8'd254) ?
8'd255 :
din_inc___2_exp__h166366) :
((_theResult___fst_exp__h165679 == 8'd0 &&
sfd__h165698[24:23] == 2'b01) ?
8'd1 :
_theResult___fst_exp__h165679) ;
assign _theResult___exp__h191161 =
sfd__h190524[53] ?
((_theResult___fst_exp__h190506 == 11'd2046) ?
11'd2047 :
din_inc___2_exp__h212214) :
((_theResult___fst_exp__h190506 == 11'd0 &&
sfd__h190524[53:52] == 2'b01) ?
11'd1 :
_theResult___fst_exp__h190506) ;
assign _theResult___exp__h202063 =
sfd__h201426[53] ?
((_theResult___fst_exp__h201334 == 11'd2046) ?
11'd2047 :
din_inc___2_exp__h212244) :
((_theResult___fst_exp__h201334 == 11'd0 &&
sfd__h201426[53:52] == 2'b01) ?
11'd1 :
_theResult___fst_exp__h201334) ;
assign _theResult___exp__h212078 =
sfd__h211417[53] ?
((_theResult___fst_exp__h211398 == 11'd2046) ?
11'd2047 :
din_inc___2_exp__h212268) :
((_theResult___fst_exp__h211398 == 11'd0 &&
sfd__h211417[53:52] == 2'b01) ?
11'd1 :
_theResult___fst_exp__h211398) ;
assign _theResult___exp__h27709 =
(sfd__h27313[24] || sfd__h27313[24:23] == 2'b01) ? 8'd1 : 8'd0 ;
assign _theResult___exp__h28261 =
sfd__h27852[24] ?
((x__h27837[7:0] == 8'd254) ?
8'd255 :
din_inc___2_exp__h28399) :
((x__h27837[7:0] == 8'd0 && sfd__h27852[24:23] == 2'b01) ?
8'd1 :
x__h27837[7:0]) ;
assign _theResult___exp__h34881 =
(sfd__h34485[24] || sfd__h34485[24:23] == 2'b01) ? 8'd1 : 8'd0 ;
assign _theResult___exp__h35434 =
sfd__h35025[24] ?
((x__h35010[7:0] == 8'd254) ?
8'd255 :
din_inc___2_exp__h35577) :
((x__h35010[7:0] == 8'd0 && sfd__h35025[24:23] == 2'b01) ?
8'd1 :
x__h35010[7:0]) ;
assign _theResult___exp__h41797 =
(sfd__h41401[24] || sfd__h41401[24:23] == 2'b01) ? 8'd1 : 8'd0 ;
assign _theResult___exp__h42349 =
sfd__h41940[24] ?
((x__h41925[7:0] == 8'd254) ?
8'd255 :
din_inc___2_exp__h42487) :
((x__h41925[7:0] == 8'd0 && sfd__h41940[24:23] == 2'b01) ?
8'd1 :
x__h41925[7:0]) ;
assign _theResult___exp__h70015 =
(sfd__h69416[53] || sfd__h69416[53:52] == 2'b01) ?
11'd1 :
11'd0 ;
assign _theResult___exp__h70771 =
sfd__h70159[53] ?
((x__h70144[10:0] == 11'd2046) ?
11'd2047 :
din_inc___2_exp__h70914) :
((x__h70144[10:0] == 11'd0 && sfd__h70159[53:52] == 2'b01) ?
11'd1 :
x__h70144[10:0]) ;
assign _theResult___exp__h80962 =
(sfd__h80363[53] || sfd__h80363[53:52] == 2'b01) ?
11'd1 :
11'd0 ;
assign _theResult___exp__h81717 =
sfd__h81105[53] ?
((x__h81090[10:0] == 11'd2046) ?
11'd2047 :
din_inc___2_exp__h81855) :
((x__h81090[10:0] == 11'd0 && sfd__h81105[53:52] == 2'b01) ?
11'd1 :
x__h81090[10:0]) ;
assign _theResult___exp__h96337 =
(sfd__h95738[53] || sfd__h95738[53:52] == 2'b01) ?
11'd1 :
11'd0 ;
assign _theResult___exp__h97093 =
sfd__h96481[53] ?
((x__h96466[10:0] == 11'd2046) ?
11'd2047 :
din_inc___2_exp__h97236) :
((x__h96466[10:0] == 11'd0 && sfd__h96481[53:52] == 2'b01) ?
11'd1 :
x__h96466[10:0]) ;
assign _theResult___fst_exp__h108958 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard08246_0b0_0_0b1_0_0b10_out_exp08865__ETC__q32 :
CASE_requestR_BITS_194_TO_192_0x3_IF_guard0824_ETC__q34 ;
assign _theResult___fst_exp__h109713 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard08975_0b0_x08990_BITS_10_TO_0_0b1_x0_ETC__q110 :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3147 ;
assign _theResult___fst_exp__h109716 =
(x__h108990[10:0] == 11'd2047) ?
x__h108990[10:0] :
_theResult___fst_exp__h109713 ;
assign _theResult___fst_exp__h126010 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3) ?
8'd255 :
CASE_requestR_BITS_194_TO_192_0x1_254_0x2_IF_r_ETC__q4 ;
assign _theResult___fst_exp__h135390 =
_theResult____h126028[56] ?
8'd2 :
_theResult___fst_exp__h135464 ;
assign _theResult___fst_exp__h135455 =
8'd0 -
{ 2'd0,
IF_IF_0b0_CONCAT_NOT_IF_requestR_3_BIT_214_4_T_ETC___d3654 } ;
assign _theResult___fst_exp__h135461 =
(!_theResult____h126028[56] && !_theResult____h126028[55] &&
!_theResult____h126028[54] &&
!_theResult____h126028[53] &&
!_theResult____h126028[52] &&
!_theResult____h126028[51] &&
!_theResult____h126028[50] &&
!_theResult____h126028[49] &&
!_theResult____h126028[48] &&
!_theResult____h126028[47] &&
!_theResult____h126028[46] &&
!_theResult____h126028[45] &&
!_theResult____h126028[44] &&
!_theResult____h126028[43] &&
!_theResult____h126028[42] &&
!_theResult____h126028[41] &&
!_theResult____h126028[40] &&
!_theResult____h126028[39] &&
!_theResult____h126028[38] &&
!_theResult____h126028[37] &&
!_theResult____h126028[36] &&
!_theResult____h126028[35] &&
!_theResult____h126028[34] &&
!_theResult____h126028[33] &&
!_theResult____h126028[32] &&
!_theResult____h126028[31] &&
!_theResult____h126028[30] &&
!_theResult____h126028[29] &&
!_theResult____h126028[28] &&
!_theResult____h126028[27] &&
!_theResult____h126028[26] &&
!_theResult____h126028[25] &&
!_theResult____h126028[24] &&
!_theResult____h126028[23] &&
!_theResult____h126028[22] &&
!_theResult____h126028[21] &&
!_theResult____h126028[20] &&
!_theResult____h126028[19] &&
!_theResult____h126028[18] &&
!_theResult____h126028[17] &&
!_theResult____h126028[16] &&
!_theResult____h126028[15] &&
!_theResult____h126028[14] &&
!_theResult____h126028[13] &&
!_theResult____h126028[12] &&
!_theResult____h126028[11] &&
!_theResult____h126028[10] &&
!_theResult____h126028[9] &&
!_theResult____h126028[8] &&
!_theResult____h126028[7] &&
!_theResult____h126028[6] &&
!_theResult____h126028[5] &&
!_theResult____h126028[4] &&
!_theResult____h126028[3] &&
!_theResult____h126028[2] &&
!_theResult____h126028[1] &&
!_theResult____h126028[0] ||
!_0_CONCAT_IF_IF_0b0_CONCAT_NOT_IF_requestR_3_BI_ETC___d3656) ?
8'd0 :
_theResult___fst_exp__h135455 ;
assign _theResult___fst_exp__h135464 =
(!_theResult____h126028[56] && _theResult____h126028[55]) ?
8'd1 :
_theResult___fst_exp__h135461 ;
assign _theResult___fst_exp__h136014 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard26038_0b0_theResult___fst_exp35390_0_ETC__q128 :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3719 ;
assign _theResult___fst_exp__h136017 =
(_theResult___fst_exp__h135390 == 8'd255) ?
_theResult___fst_exp__h135390 :
_theResult___fst_exp__h136014 ;
assign _theResult___fst_exp__h145300 =
8'd129 -
{ 2'd0,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3776 } ;
assign _theResult___fst_exp__h145306 =
(requestR_BITS_191_TO_128__q1[62:52] == 11'd0 &&
!requestR_BITS_191_TO_128__q1[51] &&
!requestR_BITS_191_TO_128__q1[50] &&
!requestR_BITS_191_TO_128__q1[49] &&
!requestR_BITS_191_TO_128__q1[48] &&
!requestR_BITS_191_TO_128__q1[47] &&
!requestR_BITS_191_TO_128__q1[46] &&
!requestR_BITS_191_TO_128__q1[45] &&
!requestR_BITS_191_TO_128__q1[44] &&
!requestR_BITS_191_TO_128__q1[43] &&
!requestR_BITS_191_TO_128__q1[42] &&
!requestR_BITS_191_TO_128__q1[41] &&
!requestR_BITS_191_TO_128__q1[40] &&
!requestR_BITS_191_TO_128__q1[39] &&
!requestR_BITS_191_TO_128__q1[38] &&
!requestR_BITS_191_TO_128__q1[37] &&
!requestR_BITS_191_TO_128__q1[36] &&
!requestR_BITS_191_TO_128__q1[35] &&
!requestR_BITS_191_TO_128__q1[34] &&
!requestR_BITS_191_TO_128__q1[33] &&
!requestR_BITS_191_TO_128__q1[32] &&
!requestR_BITS_191_TO_128__q1[31] &&
!requestR_BITS_191_TO_128__q1[30] &&
!requestR_BITS_191_TO_128__q1[29] &&
!requestR_BITS_191_TO_128__q1[28] &&
!requestR_BITS_191_TO_128__q1[27] &&
!requestR_BITS_191_TO_128__q1[26] &&
!requestR_BITS_191_TO_128__q1[25] &&
!requestR_BITS_191_TO_128__q1[24] &&
!requestR_BITS_191_TO_128__q1[23] &&
!requestR_BITS_191_TO_128__q1[22] &&
!requestR_BITS_191_TO_128__q1[21] &&
!requestR_BITS_191_TO_128__q1[20] &&
!requestR_BITS_191_TO_128__q1[19] &&
!requestR_BITS_191_TO_128__q1[18] &&
!requestR_BITS_191_TO_128__q1[17] &&
!requestR_BITS_191_TO_128__q1[16] &&
!requestR_BITS_191_TO_128__q1[15] &&
!requestR_BITS_191_TO_128__q1[14] &&
!requestR_BITS_191_TO_128__q1[13] &&
!requestR_BITS_191_TO_128__q1[12] &&
!requestR_BITS_191_TO_128__q1[11] &&
!requestR_BITS_191_TO_128__q1[10] &&
!requestR_BITS_191_TO_128__q1[9] &&
!requestR_BITS_191_TO_128__q1[8] &&
!requestR_BITS_191_TO_128__q1[7] &&
!requestR_BITS_191_TO_128__q1[6] &&
!requestR_BITS_191_TO_128__q1[5] &&
!requestR_BITS_191_TO_128__q1[4] &&
!requestR_BITS_191_TO_128__q1[3] &&
!requestR_BITS_191_TO_128__q1[2] &&
!requestR_BITS_191_TO_128__q1[1] &&
!requestR_BITS_191_TO_128__q1[0] ||
!_0_CONCAT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d3778) ?
8'd0 :
_theResult___fst_exp__h145300 ;
assign _theResult___fst_exp__h145309 =
(requestR_BITS_191_TO_128__q1[62:52] == 11'd0) ?
_theResult___fst_exp__h145306 :
8'd129 ;
assign _theResult___fst_exp__h145859 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard36028_0b0_theResult___fst_exp45309_0_ETC__q130 :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3836 ;
assign _theResult___fst_exp__h145862 =
(_theResult___fst_exp__h145309 == 8'd255) ?
_theResult___fst_exp__h145309 :
_theResult___fst_exp__h145859 ;
assign _theResult___fst_exp__h15528 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard5015_0b0_0_0b1_0_0b10_out_exp5434_0b_ETC__q18 :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d536 ;
assign _theResult___fst_exp__h155731 =
_theResult____h146240[56] ?
8'd2 :
_theResult___fst_exp__h155805 ;
assign _theResult___fst_exp__h155796 =
8'd0 -
{ 2'd0,
IF_IF_3970_MINUS_SEXT_IF_requestR_3_BIT_214_4__ETC___d4098 } ;
assign _theResult___fst_exp__h155802 =
(!_theResult____h146240[56] && !_theResult____h146240[55] &&
!_theResult____h146240[54] &&
!_theResult____h146240[53] &&
!_theResult____h146240[52] &&
!_theResult____h146240[51] &&
!_theResult____h146240[50] &&
!_theResult____h146240[49] &&
!_theResult____h146240[48] &&
!_theResult____h146240[47] &&
!_theResult____h146240[46] &&
!_theResult____h146240[45] &&
!_theResult____h146240[44] &&
!_theResult____h146240[43] &&
!_theResult____h146240[42] &&
!_theResult____h146240[41] &&
!_theResult____h146240[40] &&
!_theResult____h146240[39] &&
!_theResult____h146240[38] &&
!_theResult____h146240[37] &&
!_theResult____h146240[36] &&
!_theResult____h146240[35] &&
!_theResult____h146240[34] &&
!_theResult____h146240[33] &&
!_theResult____h146240[32] &&
!_theResult____h146240[31] &&
!_theResult____h146240[30] &&
!_theResult____h146240[29] &&
!_theResult____h146240[28] &&
!_theResult____h146240[27] &&
!_theResult____h146240[26] &&
!_theResult____h146240[25] &&
!_theResult____h146240[24] &&
!_theResult____h146240[23] &&
!_theResult____h146240[22] &&
!_theResult____h146240[21] &&
!_theResult____h146240[20] &&
!_theResult____h146240[19] &&
!_theResult____h146240[18] &&
!_theResult____h146240[17] &&
!_theResult____h146240[16] &&
!_theResult____h146240[15] &&
!_theResult____h146240[14] &&
!_theResult____h146240[13] &&
!_theResult____h146240[12] &&
!_theResult____h146240[11] &&
!_theResult____h146240[10] &&
!_theResult____h146240[9] &&
!_theResult____h146240[8] &&
!_theResult____h146240[7] &&
!_theResult____h146240[6] &&
!_theResult____h146240[5] &&
!_theResult____h146240[4] &&
!_theResult____h146240[3] &&
!_theResult____h146240[2] &&
!_theResult____h146240[1] &&
!_theResult____h146240[0] ||
!_0_CONCAT_IF_IF_3970_MINUS_SEXT_IF_requestR_3_B_ETC___d4100) ?
8'd0 :
_theResult___fst_exp__h155796 ;
assign _theResult___fst_exp__h155805 =
(!_theResult____h146240[56] && _theResult____h146240[55]) ?
8'd1 :
_theResult___fst_exp__h155802 ;
assign _theResult___fst_exp__h156355 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard46250_0b0_theResult___fst_exp55731_0_ETC__q132 :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4163 ;
assign _theResult___fst_exp__h156358 =
(_theResult___fst_exp__h155731 == 8'd255) ?
_theResult___fst_exp__h155731 :
_theResult___fst_exp__h156355 ;
assign _theResult___fst_exp__h16081 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard5545_0b0_x5560_BITS_7_TO_0_0b1_x5560_ETC__q20 :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d565 ;
assign _theResult___fst_exp__h16084 =
(x__h15560[7:0] == 8'd255) ?
x__h15560[7:0] :
_theResult___fst_exp__h16081 ;
assign _theResult___fst_exp__h165631 =
(SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_3_B_ETC__q121[7:0] ==
8'd0) ?
8'd1 :
SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_3_B_ETC__q121[7:0] ;
assign _theResult___fst_exp__h165670 =
SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_3_B_ETC__q121[7:0] -
{ 2'd0,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3776 } ;
assign _theResult___fst_exp__h165676 =
(requestR_BITS_191_TO_128__q1[62:52] == 11'd0 &&
!requestR_BITS_191_TO_128__q1[51] &&
!requestR_BITS_191_TO_128__q1[50] &&
!requestR_BITS_191_TO_128__q1[49] &&
!requestR_BITS_191_TO_128__q1[48] &&
!requestR_BITS_191_TO_128__q1[47] &&
!requestR_BITS_191_TO_128__q1[46] &&
!requestR_BITS_191_TO_128__q1[45] &&
!requestR_BITS_191_TO_128__q1[44] &&
!requestR_BITS_191_TO_128__q1[43] &&
!requestR_BITS_191_TO_128__q1[42] &&
!requestR_BITS_191_TO_128__q1[41] &&
!requestR_BITS_191_TO_128__q1[40] &&
!requestR_BITS_191_TO_128__q1[39] &&
!requestR_BITS_191_TO_128__q1[38] &&
!requestR_BITS_191_TO_128__q1[37] &&
!requestR_BITS_191_TO_128__q1[36] &&
!requestR_BITS_191_TO_128__q1[35] &&
!requestR_BITS_191_TO_128__q1[34] &&
!requestR_BITS_191_TO_128__q1[33] &&
!requestR_BITS_191_TO_128__q1[32] &&
!requestR_BITS_191_TO_128__q1[31] &&
!requestR_BITS_191_TO_128__q1[30] &&
!requestR_BITS_191_TO_128__q1[29] &&
!requestR_BITS_191_TO_128__q1[28] &&
!requestR_BITS_191_TO_128__q1[27] &&
!requestR_BITS_191_TO_128__q1[26] &&
!requestR_BITS_191_TO_128__q1[25] &&
!requestR_BITS_191_TO_128__q1[24] &&
!requestR_BITS_191_TO_128__q1[23] &&
!requestR_BITS_191_TO_128__q1[22] &&
!requestR_BITS_191_TO_128__q1[21] &&
!requestR_BITS_191_TO_128__q1[20] &&
!requestR_BITS_191_TO_128__q1[19] &&
!requestR_BITS_191_TO_128__q1[18] &&
!requestR_BITS_191_TO_128__q1[17] &&
!requestR_BITS_191_TO_128__q1[16] &&
!requestR_BITS_191_TO_128__q1[15] &&
!requestR_BITS_191_TO_128__q1[14] &&
!requestR_BITS_191_TO_128__q1[13] &&
!requestR_BITS_191_TO_128__q1[12] &&
!requestR_BITS_191_TO_128__q1[11] &&
!requestR_BITS_191_TO_128__q1[10] &&
!requestR_BITS_191_TO_128__q1[9] &&
!requestR_BITS_191_TO_128__q1[8] &&
!requestR_BITS_191_TO_128__q1[7] &&
!requestR_BITS_191_TO_128__q1[6] &&
!requestR_BITS_191_TO_128__q1[5] &&
!requestR_BITS_191_TO_128__q1[4] &&
!requestR_BITS_191_TO_128__q1[3] &&
!requestR_BITS_191_TO_128__q1[2] &&
!requestR_BITS_191_TO_128__q1[1] &&
!requestR_BITS_191_TO_128__q1[0] ||
!_0_CONCAT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d4173) ?
8'd0 :
_theResult___fst_exp__h165670 ;
assign _theResult___fst_exp__h165679 =
(requestR_BITS_191_TO_128__q1[62:52] == 11'd0) ?
_theResult___fst_exp__h165676 :
_theResult___fst_exp__h165631 ;
assign _theResult___fst_exp__h166254 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard56369_0b0_theResult___fst_exp65679_0_ETC__q134 :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4232 ;
assign _theResult___fst_exp__h166257 =
(_theResult___fst_exp__h165679 == 8'd255) ?
_theResult___fst_exp__h165679 :
_theResult___fst_exp__h166254 ;
assign _theResult___fst_exp__h166266 =
(requestR_BITS_191_TO_128__q1[62:52] == 11'd0) ?
(_3074_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_ETC___d3421 ?
_theResult___snd_fst_exp__h145865 :
_theResult___fst_exp__h126010) :
(SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_3_B_ETC___d3852 ?
_theResult___snd_fst_exp__h166260 :
_theResult___fst_exp__h126010) ;
assign _theResult___fst_exp__h166269 =
(requestR_BITS_191_TO_128__q1[62:52] == 11'd0 &&
requestR_BITS_191_TO_128__q1[51:0] == 52'd0) ?
8'd0 :
_theResult___fst_exp__h166266 ;
assign _theResult___fst_exp__h174200 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3) ?
11'd2047 :
CASE_requestR_BITS_194_TO_192_0x1_2046_0x2_IF__ETC__q6 ;
assign _theResult___fst_exp__h190497 =
11'd897 -
{ 5'd0,
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d4613 } ;
assign _theResult___fst_exp__h190503 =
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4617 ?
11'd0 :
_theResult___fst_exp__h190497 ;
assign _theResult___fst_exp__h190506 =
(sV1_exp__h1472 == 8'd0) ?
_theResult___fst_exp__h190503 :
11'd897 ;
assign _theResult___fst_exp__h191259 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard81312_0b0_theResult___fst_exp90506_0_ETC__q160 :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4673 ;
assign _theResult___fst_exp__h191262 =
(_theResult___fst_exp__h190506 == 11'd2047) ?
_theResult___fst_exp__h190506 :
_theResult___fst_exp__h191259 ;
assign _theResult___fst_exp__h201334 =
_theResult____h191843[56] ?
11'd2 :
_theResult___fst_exp__h201408 ;
assign _theResult___fst_exp__h201399 =
11'd0 -
{ 5'd0,
IF_IF_3074_MINUS_SEXT_IF_IF_requestR_3_BIT_214_ETC___d4933 } ;
assign _theResult___fst_exp__h201405 =
(!_theResult____h191843[56] && !_theResult____h191843[55] &&
!_theResult____h191843[54] &&
!_theResult____h191843[53] &&
!_theResult____h191843[52] &&
!_theResult____h191843[51] &&
!_theResult____h191843[50] &&
!_theResult____h191843[49] &&
!_theResult____h191843[48] &&
!_theResult____h191843[47] &&
!_theResult____h191843[46] &&
!_theResult____h191843[45] &&
!_theResult____h191843[44] &&
!_theResult____h191843[43] &&
!_theResult____h191843[42] &&
!_theResult____h191843[41] &&
!_theResult____h191843[40] &&
!_theResult____h191843[39] &&
!_theResult____h191843[38] &&
!_theResult____h191843[37] &&
!_theResult____h191843[36] &&
!_theResult____h191843[35] &&
!_theResult____h191843[34] &&
!_theResult____h191843[33] &&
!_theResult____h191843[32] &&
!_theResult____h191843[31] &&
!_theResult____h191843[30] &&
!_theResult____h191843[29] &&
!_theResult____h191843[28] &&
!_theResult____h191843[27] &&
!_theResult____h191843[26] &&
!_theResult____h191843[25] &&
!_theResult____h191843[24] &&
!_theResult____h191843[23] &&
!_theResult____h191843[22] &&
!_theResult____h191843[21] &&
!_theResult____h191843[20] &&
!_theResult____h191843[19] &&
!_theResult____h191843[18] &&
!_theResult____h191843[17] &&
!_theResult____h191843[16] &&
!_theResult____h191843[15] &&
!_theResult____h191843[14] &&
!_theResult____h191843[13] &&
!_theResult____h191843[12] &&
!_theResult____h191843[11] &&
!_theResult____h191843[10] &&
!_theResult____h191843[9] &&
!_theResult____h191843[8] &&
!_theResult____h191843[7] &&
!_theResult____h191843[6] &&
!_theResult____h191843[5] &&
!_theResult____h191843[4] &&
!_theResult____h191843[3] &&
!_theResult____h191843[2] &&
!_theResult____h191843[1] &&
!_theResult____h191843[0] ||
!_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_IF_requestR__ETC___d4935) ?
11'd0 :
_theResult___fst_exp__h201399 ;
assign _theResult___fst_exp__h201408 =
(!_theResult____h191843[56] && _theResult____h191843[55]) ?
11'd1 :
_theResult___fst_exp__h201405 ;
assign _theResult___fst_exp__h202161 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard91853_0b0_theResult___fst_exp01334_0_ETC__q162 :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4998 ;
assign _theResult___fst_exp__h202164 =
(_theResult___fst_exp__h201334 == 11'd2047) ?
_theResult___fst_exp__h201334 :
_theResult___fst_exp__h202161 ;
assign _theResult___fst_exp__h211350 =
(SEXT_IF_IF_requestR_3_BIT_214_4_THEN_requestR__ETC__q153[10:0] ==
11'd0) ?
11'd1 :
SEXT_IF_IF_requestR_3_BIT_214_4_THEN_requestR__ETC__q153[10:0] ;
assign _theResult___fst_exp__h211389 =
SEXT_IF_IF_requestR_3_BIT_214_4_THEN_requestR__ETC__q153[10:0] -
{ 5'd0,
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d4613 } ;
assign _theResult___fst_exp__h211395 =
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d5010 ?
11'd0 :
_theResult___fst_exp__h211389 ;
assign _theResult___fst_exp__h211398 =
(sV1_exp__h1472 == 8'd0) ?
_theResult___fst_exp__h211395 :
_theResult___fst_exp__h211350 ;
assign _theResult___fst_exp__h212176 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard02175_0b0_theResult___fst_exp11398_0_ETC__q164 :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d5067 ;
assign _theResult___fst_exp__h212179 =
(_theResult___fst_exp__h211398 == 11'd2047) ?
_theResult___fst_exp__h211398 :
_theResult___fst_exp__h212176 ;
assign _theResult___fst_exp__h212188 =
(sV1_exp__h1472 == 8'd0) ?
(_3970_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_21_ETC___d4542 ?
_theResult___snd_fst_exp__h191265 :
_theResult___fst_exp__h174200) :
(SEXT_IF_IF_requestR_3_BIT_214_4_THEN_requestR__ETC___d4685 ?
_theResult___snd_fst_exp__h212182 :
_theResult___fst_exp__h174200) ;
assign _theResult___fst_exp__h212191 =
(sV1_exp__h1472 == 8'd0 && sV1_sfd__h1473 == 23'd0) ?
11'd0 :
_theResult___fst_exp__h212188 ;
assign _theResult___fst_exp__h27805 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard7296_0b0_0_0b1_0_0b10_out_exp7712_0b_ETC__q29 :
CASE_requestR_BITS_194_TO_192_0x3_IF_guard7296_ETC__q31 ;
assign _theResult___fst_exp__h28357 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard7822_0b0_x7837_BITS_7_TO_0_0b1_x7837_ETC__q36 :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1050 ;
assign _theResult___fst_exp__h28360 =
(x__h27837[7:0] == 8'd255) ?
x__h27837[7:0] :
_theResult___fst_exp__h28357 ;
assign _theResult___fst_exp__h34978 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard4468_0b0_0_0b1_0_0b10_out_exp4884_0b_ETC__q44 :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1404 ;
assign _theResult___fst_exp__h35531 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard4995_0b0_x5010_BITS_7_TO_0_0b1_x5010_ETC__q50 :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1433 ;
assign _theResult___fst_exp__h35534 =
(x__h35010[7:0] == 8'd255) ?
x__h35010[7:0] :
_theResult___fst_exp__h35531 ;
assign _theResult___fst_exp__h41893 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard1384_0b0_0_0b1_0_0b10_out_exp1800_0b_ETC__q57 :
CASE_requestR_BITS_194_TO_192_0x3_IF_guard1384_ETC__q59 ;
assign _theResult___fst_exp__h42445 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard1910_0b0_x1925_BITS_7_TO_0_0b1_x1925_ETC__q61 :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1657 ;
assign _theResult___fst_exp__h42448 =
(x__h41925[7:0] == 8'd255) ?
x__h41925[7:0] :
_theResult___fst_exp__h42445 ;
assign _theResult___fst_exp__h70112 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard9399_0b0_0_0b1_0_0b10_out_exp0018_0b_ETC__q81 :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2422 ;
assign _theResult___fst_exp__h70868 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard0129_0b0_x0144_BITS_10_TO_0_0b1_x014_ETC__q77 :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2451 ;
assign _theResult___fst_exp__h70871 =
(x__h70144[10:0] == 11'd2047) ?
x__h70144[10:0] :
_theResult___fst_exp__h70868 ;
assign _theResult___fst_exp__h81058 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard0346_0b0_0_0b1_0_0b10_out_exp0965_0b_ETC__q86 :
CASE_requestR_BITS_194_TO_192_0x3_IF_guard0346_ETC__q88 ;
assign _theResult___fst_exp__h81813 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard1075_0b0_x1090_BITS_10_TO_0_0b1_x109_ETC__q90 :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2639 ;
assign _theResult___fst_exp__h81816 =
(x__h81090[10:0] == 11'd2047) ?
x__h81090[10:0] :
_theResult___fst_exp__h81813 ;
assign _theResult___fst_exp__h96434 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard5721_0b0_0_0b1_0_0b10_out_exp6340_0b_ETC__q106 :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2961 ;
assign _theResult___fst_exp__h97190 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard6451_0b0_x6466_BITS_10_TO_0_0b1_x646_ETC__q102 :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2990 ;
assign _theResult___fst_exp__h97193 =
(x__h96466[10:0] == 11'd2047) ?
x__h96466[10:0] :
_theResult___fst_exp__h97190 ;
assign _theResult___fst_sfd__h108959 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard08246_0b0_sfd___37286_BITS_63_TO_12__ETC__q114 :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3170 ;
assign _theResult___fst_sfd__h109714 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard08975_0b0_sfd___37286_BITS_62_TO_11__ETC__q112 :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3185 ;
assign _theResult___fst_sfd__h109717 =
(x__h108990[10:0] == 11'd2047) ?
sfd___3__h27286[62:11] :
_theResult___fst_sfd__h109714 ;
assign _theResult___fst_sfd__h113549 =
{ 1'd1, requestR_BITS_191_TO_128__q1[50:0] } ;
assign _theResult___fst_sfd__h126011 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3) ?
23'd0 :
CASE_requestR_BITS_194_TO_192_0x1_8388607_0x2__ETC__q5 ;
assign _theResult___fst_sfd__h136015 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard26038_0b0_sfdin35384_BITS_56_TO_34_0_ETC__q136 :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4266 ;
assign _theResult___fst_sfd__h136018 =
(_theResult___fst_exp__h135390 == 8'd255) ?
sfdin__h135384[56:34] :
_theResult___fst_sfd__h136015 ;
assign _theResult___fst_sfd__h145860 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard36028_0b0_theResult___snd45260_BITS__ETC__q138 :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4285 ;
assign _theResult___fst_sfd__h145863 =
(_theResult___fst_exp__h145309 == 8'd255) ?
_theResult___snd__h145260[56:34] :
_theResult___fst_sfd__h145860 ;
assign _theResult___fst_sfd__h15529 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard5015_0b0_sfd___35005_BITS_63_TO_41_0_ETC__q22 :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d588 ;
assign _theResult___fst_sfd__h156356 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard46250_0b0_sfdin55725_BITS_56_TO_34_0_ETC__q140 :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4312 ;
assign _theResult___fst_sfd__h156359 =
(_theResult___fst_exp__h155731 == 8'd255) ?
sfdin__h155725[56:34] :
_theResult___fst_sfd__h156356 ;
assign _theResult___fst_sfd__h16082 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard5545_0b0_sfd___35005_BITS_62_TO_40_0_ETC__q24 :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d606 ;
assign _theResult___fst_sfd__h16085 =
(x__h15560[7:0] == 8'd255) ?
sfd___3__h15005[62:40] :
_theResult___fst_sfd__h16082 ;
assign _theResult___fst_sfd__h166255 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard56369_0b0_theResult___snd65625_BITS__ETC__q142 :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4331 ;
assign _theResult___fst_sfd__h166258 =
(_theResult___fst_exp__h165679 == 8'd255) ?
_theResult___snd__h165625[56:34] :
_theResult___fst_sfd__h166255 ;
assign _theResult___fst_sfd__h166267 =
(requestR_BITS_191_TO_128__q1[62:52] == 11'd0) ?
(_3074_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_ETC___d3421 ?
_theResult___snd_fst_sfd__h145866 :
_theResult___fst_sfd__h126011) :
(SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_3_B_ETC___d3852 ?
_theResult___snd_fst_sfd__h166261 :
_theResult___fst_sfd__h126011) ;
assign _theResult___fst_sfd__h166273 =
((requestR_BITS_191_TO_128__q1[62:52] == 11'd2047 ||
requestR_BITS_191_TO_128__q1[62:52] == 11'd0) &&
requestR_BITS_191_TO_128__q1[51:0] == 52'd0) ?
23'd0 :
_theResult___fst_sfd__h166267 ;
assign _theResult___fst_sfd__h168212 = { 1'd1, sV1_sfd__h1473[21:0] } ;
assign _theResult___fst_sfd__h174201 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3) ?
52'd0 :
CASE_requestR_BITS_194_TO_192_0x1_450359962737_ETC__q7 ;
assign _theResult___fst_sfd__h191260 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard81312_0b0_theResult___snd90457_BITS__ETC__q172 :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d5100 ;
assign _theResult___fst_sfd__h191263 =
(_theResult___fst_exp__h190506 == 11'd2047) ?
_theResult___snd__h190457[56:5] :
_theResult___fst_sfd__h191260 ;
assign _theResult___fst_sfd__h202162 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard91853_0b0_sfdin01328_BITS_56_TO_5_0b_ETC__q174 :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d5127 ;
assign _theResult___fst_sfd__h202165 =
(_theResult___fst_exp__h201334 == 11'd2047) ?
sfdin__h201328[56:5] :
_theResult___fst_sfd__h202162 ;
assign _theResult___fst_sfd__h212177 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard02175_0b0_theResult___snd11344_BITS__ETC__q176 :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d5146 ;
assign _theResult___fst_sfd__h212180 =
(_theResult___fst_exp__h211398 == 11'd2047) ?
_theResult___snd__h211344[56:5] :
_theResult___fst_sfd__h212177 ;
assign _theResult___fst_sfd__h212189 =
(sV1_exp__h1472 == 8'd0) ?
(_3970_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_21_ETC___d4542 ?
_theResult___snd_fst_sfd__h191266 :
_theResult___fst_sfd__h174201) :
(SEXT_IF_IF_requestR_3_BIT_214_4_THEN_requestR__ETC___d4685 ?
_theResult___snd_fst_sfd__h212183 :
_theResult___fst_sfd__h174201) ;
assign _theResult___fst_sfd__h212195 =
((sV1_exp__h1472 == 8'd255 || sV1_exp__h1472 == 8'd0) &&
sV1_sfd__h1473 == 23'd0) ?
52'd0 :
_theResult___fst_sfd__h212189 ;
assign _theResult___fst_sfd__h27806 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard7296_0b0_sfd___37286_BITS_63_TO_41_0_ETC__q40 :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1073 ;
assign _theResult___fst_sfd__h28358 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard7822_0b0_sfd___37286_BITS_62_TO_40_0_ETC__q38 :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1088 ;
assign _theResult___fst_sfd__h28361 =
(x__h27837[7:0] == 8'd255) ?
sfd___3__h27286[62:40] :
_theResult___fst_sfd__h28358 ;
assign _theResult___fst_sfd__h34979 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard4468_0b0_sfd___34458_BITS_31_TO_9_0b_ETC__q52 :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1456 ;
assign _theResult___fst_sfd__h35532 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard4995_0b0_sfd___34458_BITS_30_TO_8_0b_ETC__q54 :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1474 ;
assign _theResult___fst_sfd__h35535 =
(x__h35010[7:0] == 8'd255) ?
sfd___3__h34458[30:8] :
_theResult___fst_sfd__h35532 ;
assign _theResult___fst_sfd__h41894 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard1384_0b0_sfd___31374_BITS_31_TO_9_0b_ETC__q65 :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1680 ;
assign _theResult___fst_sfd__h42446 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard1910_0b0_sfd___31374_BITS_30_TO_8_0b_ETC__q63 :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1695 ;
assign _theResult___fst_sfd__h42449 =
(x__h41925[7:0] == 8'd255) ?
sfd___3__h41374[30:8] :
_theResult___fst_sfd__h42446 ;
assign _theResult___fst_sfd__h70113 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard9399_0b0_sfd___39389_BITS_54_TO_3_0b_ETC__q83 :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2474 ;
assign _theResult___fst_sfd__h70869 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard0129_0b0_sfd___39389_BITS_53_TO_2_0b_ETC__q79 :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2492 ;
assign _theResult___fst_sfd__h70872 =
(x__h70144[10:0] == 11'd2047) ?
sfd___3__h69389[53:2] :
_theResult___fst_sfd__h70869 ;
assign _theResult___fst_sfd__h81059 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard0346_0b0_sfd___30336_BITS_54_TO_3_0b_ETC__q94 :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2661 ;
assign _theResult___fst_sfd__h81814 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard1075_0b0_sfd___30336_BITS_53_TO_2_0b_ETC__q92 :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2676 ;
assign _theResult___fst_sfd__h81817 =
(x__h81090[10:0] == 11'd2047) ?
sfd___3__h80336[53:2] :
_theResult___fst_sfd__h81814 ;
assign _theResult___fst_sfd__h96435 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard5721_0b0_sfd___35005_BITS_63_TO_12_0_ETC__q108 :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3013 ;
assign _theResult___fst_sfd__h97191 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard6451_0b0_sfd___35005_BITS_62_TO_11_0_ETC__q104 :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3031 ;
assign _theResult___fst_sfd__h97194 =
(x__h96466[10:0] == 11'd2047) ?
sfd___3__h15005[62:11] :
_theResult___fst_sfd__h97191 ;
assign _theResult___sfd__h108863 =
sfd__h108263[53] ? sfd__h108263[52:1] : sfd__h108263[51:0] ;
assign _theResult___sfd__h109618 =
sfd__h109005[53] ?
((x__h108990[10:0] == 11'd2046) ? 52'd0 : sfd__h109005[52:1]) :
sfd__h109005[51:0] ;
assign _theResult___sfd__h135917 =
sfd__h135482[24] ?
((_theResult___fst_exp__h135390 == 8'd254) ?
23'd0 :
sfd__h135482[23:1]) :
sfd__h135482[22:0] ;
assign _theResult___sfd__h145762 =
sfd__h145327[24] ?
((_theResult___fst_exp__h145309 == 8'd254) ?
23'd0 :
sfd__h145327[23:1]) :
sfd__h145327[22:0] ;
assign _theResult___sfd__h15432 =
sfd__h15032[24] ? sfd__h15032[23:1] : sfd__h15032[22:0] ;
assign _theResult___sfd__h156258 =
sfd__h155823[24] ?
((_theResult___fst_exp__h155731 == 8'd254) ?
23'd0 :
sfd__h155823[23:1]) :
sfd__h155823[22:0] ;
assign _theResult___sfd__h15985 =
sfd__h15575[24] ?
((x__h15560[7:0] == 8'd254) ? 23'd0 : sfd__h15575[23:1]) :
sfd__h15575[22:0] ;
assign _theResult___sfd__h166157 =
sfd__h165698[24] ?
((_theResult___fst_exp__h165679 == 8'd254) ?
23'd0 :
sfd__h165698[23:1]) :
sfd__h165698[22:0] ;
assign _theResult___sfd__h191162 =
sfd__h190524[53] ?
((_theResult___fst_exp__h190506 == 11'd2046) ?
52'd0 :
sfd__h190524[52:1]) :
sfd__h190524[51:0] ;
assign _theResult___sfd__h202064 =
sfd__h201426[53] ?
((_theResult___fst_exp__h201334 == 11'd2046) ?
52'd0 :
sfd__h201426[52:1]) :
sfd__h201426[51:0] ;
assign _theResult___sfd__h212079 =
sfd__h211417[53] ?
((_theResult___fst_exp__h211398 == 11'd2046) ?
52'd0 :
sfd__h211417[52:1]) :
sfd__h211417[51:0] ;
assign _theResult___sfd__h27710 =
sfd__h27313[24] ? sfd__h27313[23:1] : sfd__h27313[22:0] ;
assign _theResult___sfd__h28262 =
sfd__h27852[24] ?
((x__h27837[7:0] == 8'd254) ? 23'd0 : sfd__h27852[23:1]) :
sfd__h27852[22:0] ;
assign _theResult___sfd__h34882 =
sfd__h34485[24] ? sfd__h34485[23:1] : sfd__h34485[22:0] ;
assign _theResult___sfd__h35435 =
sfd__h35025[24] ?
((x__h35010[7:0] == 8'd254) ? 23'd0 : sfd__h35025[23:1]) :
sfd__h35025[22:0] ;
assign _theResult___sfd__h41798 =
sfd__h41401[24] ? sfd__h41401[23:1] : sfd__h41401[22:0] ;
assign _theResult___sfd__h42350 =
sfd__h41940[24] ?
((x__h41925[7:0] == 8'd254) ? 23'd0 : sfd__h41940[23:1]) :
sfd__h41940[22:0] ;
assign _theResult___sfd__h70016 =
sfd__h69416[53] ? sfd__h69416[52:1] : sfd__h69416[51:0] ;
assign _theResult___sfd__h70772 =
sfd__h70159[53] ?
((x__h70144[10:0] == 11'd2046) ? 52'd0 : sfd__h70159[52:1]) :
sfd__h70159[51:0] ;
assign _theResult___sfd__h80963 =
sfd__h80363[53] ? sfd__h80363[52:1] : sfd__h80363[51:0] ;
assign _theResult___sfd__h81718 =
sfd__h81105[53] ?
((x__h81090[10:0] == 11'd2046) ? 52'd0 : sfd__h81105[52:1]) :
sfd__h81105[51:0] ;
assign _theResult___sfd__h96338 =
sfd__h95738[53] ? sfd__h95738[52:1] : sfd__h95738[51:0] ;
assign _theResult___sfd__h97094 =
sfd__h96481[53] ?
((x__h96466[10:0] == 11'd2046) ? 52'd0 : sfd__h96481[52:1]) :
sfd__h96481[51:0] ;
assign _theResult___snd__h135401 = { _theResult____h126028[55:0], 1'd0 } ;
assign _theResult___snd__h135412 =
(!_theResult____h126028[56] && _theResult____h126028[55]) ?
_theResult___snd__h135414 :
_theResult___snd__h135424 ;
assign _theResult___snd__h135414 = { _theResult____h126028[54:0], 2'd0 } ;
assign _theResult___snd__h135424 =
(!_theResult____h126028[56] && !_theResult____h126028[55] &&
!_theResult____h126028[54] &&
!_theResult____h126028[53] &&
!_theResult____h126028[52] &&
!_theResult____h126028[51] &&
!_theResult____h126028[50] &&
!_theResult____h126028[49] &&
!_theResult____h126028[48] &&
!_theResult____h126028[47] &&
!_theResult____h126028[46] &&
!_theResult____h126028[45] &&
!_theResult____h126028[44] &&
!_theResult____h126028[43] &&
!_theResult____h126028[42] &&
!_theResult____h126028[41] &&
!_theResult____h126028[40] &&
!_theResult____h126028[39] &&
!_theResult____h126028[38] &&
!_theResult____h126028[37] &&
!_theResult____h126028[36] &&
!_theResult____h126028[35] &&
!_theResult____h126028[34] &&
!_theResult____h126028[33] &&
!_theResult____h126028[32] &&
!_theResult____h126028[31] &&
!_theResult____h126028[30] &&
!_theResult____h126028[29] &&
!_theResult____h126028[28] &&
!_theResult____h126028[27] &&
!_theResult____h126028[26] &&
!_theResult____h126028[25] &&
!_theResult____h126028[24] &&
!_theResult____h126028[23] &&
!_theResult____h126028[22] &&
!_theResult____h126028[21] &&
!_theResult____h126028[20] &&
!_theResult____h126028[19] &&
!_theResult____h126028[18] &&
!_theResult____h126028[17] &&
!_theResult____h126028[16] &&
!_theResult____h126028[15] &&
!_theResult____h126028[14] &&
!_theResult____h126028[13] &&
!_theResult____h126028[12] &&
!_theResult____h126028[11] &&
!_theResult____h126028[10] &&
!_theResult____h126028[9] &&
!_theResult____h126028[8] &&
!_theResult____h126028[7] &&
!_theResult____h126028[6] &&
!_theResult____h126028[5] &&
!_theResult____h126028[4] &&
!_theResult____h126028[3] &&
!_theResult____h126028[2] &&
!_theResult____h126028[1] &&
!_theResult____h126028[0]) ?
_theResult____h126028 :
_theResult___snd__h135430 ;
assign _theResult___snd__h135430 =
{ IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_IF_requestR_3_ETC__q117[54:0],
2'd0 } ;
assign _theResult___snd__h135453 =
_theResult____h126028 <<
IF_IF_0b0_CONCAT_NOT_IF_requestR_3_BIT_214_4_T_ETC___d3654 ;
assign _theResult___snd__h145260 =
(requestR_BITS_191_TO_128__q1[62:52] == 11'd0) ?
_theResult___snd__h145269 :
_theResult___snd__h145262 ;
assign _theResult___snd__h145262 =
{ requestR_BITS_191_TO_128__q1[51:0], 5'd0 } ;
assign _theResult___snd__h145269 =
(requestR_BITS_191_TO_128__q1[62:52] == 11'd0 &&
!requestR_BITS_191_TO_128__q1[51] &&
!requestR_BITS_191_TO_128__q1[50] &&
!requestR_BITS_191_TO_128__q1[49] &&
!requestR_BITS_191_TO_128__q1[48] &&
!requestR_BITS_191_TO_128__q1[47] &&
!requestR_BITS_191_TO_128__q1[46] &&
!requestR_BITS_191_TO_128__q1[45] &&
!requestR_BITS_191_TO_128__q1[44] &&
!requestR_BITS_191_TO_128__q1[43] &&
!requestR_BITS_191_TO_128__q1[42] &&
!requestR_BITS_191_TO_128__q1[41] &&
!requestR_BITS_191_TO_128__q1[40] &&
!requestR_BITS_191_TO_128__q1[39] &&
!requestR_BITS_191_TO_128__q1[38] &&
!requestR_BITS_191_TO_128__q1[37] &&
!requestR_BITS_191_TO_128__q1[36] &&
!requestR_BITS_191_TO_128__q1[35] &&
!requestR_BITS_191_TO_128__q1[34] &&
!requestR_BITS_191_TO_128__q1[33] &&
!requestR_BITS_191_TO_128__q1[32] &&
!requestR_BITS_191_TO_128__q1[31] &&
!requestR_BITS_191_TO_128__q1[30] &&
!requestR_BITS_191_TO_128__q1[29] &&
!requestR_BITS_191_TO_128__q1[28] &&
!requestR_BITS_191_TO_128__q1[27] &&
!requestR_BITS_191_TO_128__q1[26] &&
!requestR_BITS_191_TO_128__q1[25] &&
!requestR_BITS_191_TO_128__q1[24] &&
!requestR_BITS_191_TO_128__q1[23] &&
!requestR_BITS_191_TO_128__q1[22] &&
!requestR_BITS_191_TO_128__q1[21] &&
!requestR_BITS_191_TO_128__q1[20] &&
!requestR_BITS_191_TO_128__q1[19] &&
!requestR_BITS_191_TO_128__q1[18] &&
!requestR_BITS_191_TO_128__q1[17] &&
!requestR_BITS_191_TO_128__q1[16] &&
!requestR_BITS_191_TO_128__q1[15] &&
!requestR_BITS_191_TO_128__q1[14] &&
!requestR_BITS_191_TO_128__q1[13] &&
!requestR_BITS_191_TO_128__q1[12] &&
!requestR_BITS_191_TO_128__q1[11] &&
!requestR_BITS_191_TO_128__q1[10] &&
!requestR_BITS_191_TO_128__q1[9] &&
!requestR_BITS_191_TO_128__q1[8] &&
!requestR_BITS_191_TO_128__q1[7] &&
!requestR_BITS_191_TO_128__q1[6] &&
!requestR_BITS_191_TO_128__q1[5] &&
!requestR_BITS_191_TO_128__q1[4] &&
!requestR_BITS_191_TO_128__q1[3] &&
!requestR_BITS_191_TO_128__q1[2] &&
!requestR_BITS_191_TO_128__q1[1] &&
!requestR_BITS_191_TO_128__q1[0]) ?
sfd__h117253 :
_theResult___snd__h145275 ;
assign _theResult___snd__h145275 =
{ IF_0_CONCAT_IF_IF_requestR_3_BIT_214_4_THEN_re_ETC__q119[54:0],
2'd0 } ;
assign _theResult___snd__h145298 =
sfd__h117253 <<
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3776 ;
assign _theResult___snd__h155742 = { _theResult____h146240[55:0], 1'd0 } ;
assign _theResult___snd__h155753 =
(!_theResult____h146240[56] && _theResult____h146240[55]) ?
_theResult___snd__h155755 :
_theResult___snd__h155765 ;
assign _theResult___snd__h155755 = { _theResult____h146240[54:0], 2'd0 } ;
assign _theResult___snd__h155765 =
(!_theResult____h146240[56] && !_theResult____h146240[55] &&
!_theResult____h146240[54] &&
!_theResult____h146240[53] &&
!_theResult____h146240[52] &&
!_theResult____h146240[51] &&
!_theResult____h146240[50] &&
!_theResult____h146240[49] &&
!_theResult____h146240[48] &&
!_theResult____h146240[47] &&
!_theResult____h146240[46] &&
!_theResult____h146240[45] &&
!_theResult____h146240[44] &&
!_theResult____h146240[43] &&
!_theResult____h146240[42] &&
!_theResult____h146240[41] &&
!_theResult____h146240[40] &&
!_theResult____h146240[39] &&
!_theResult____h146240[38] &&
!_theResult____h146240[37] &&
!_theResult____h146240[36] &&
!_theResult____h146240[35] &&
!_theResult____h146240[34] &&
!_theResult____h146240[33] &&
!_theResult____h146240[32] &&
!_theResult____h146240[31] &&
!_theResult____h146240[30] &&
!_theResult____h146240[29] &&
!_theResult____h146240[28] &&
!_theResult____h146240[27] &&
!_theResult____h146240[26] &&
!_theResult____h146240[25] &&
!_theResult____h146240[24] &&
!_theResult____h146240[23] &&
!_theResult____h146240[22] &&
!_theResult____h146240[21] &&
!_theResult____h146240[20] &&
!_theResult____h146240[19] &&
!_theResult____h146240[18] &&
!_theResult____h146240[17] &&
!_theResult____h146240[16] &&
!_theResult____h146240[15] &&
!_theResult____h146240[14] &&
!_theResult____h146240[13] &&
!_theResult____h146240[12] &&
!_theResult____h146240[11] &&
!_theResult____h146240[10] &&
!_theResult____h146240[9] &&
!_theResult____h146240[8] &&
!_theResult____h146240[7] &&
!_theResult____h146240[6] &&
!_theResult____h146240[5] &&
!_theResult____h146240[4] &&
!_theResult____h146240[3] &&
!_theResult____h146240[2] &&
!_theResult____h146240[1] &&
!_theResult____h146240[0]) ?
_theResult____h146240 :
_theResult___snd__h155771 ;
assign _theResult___snd__h155771 =
{ IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_IF_requestR__ETC__q122[54:0],
2'd0 } ;
assign _theResult___snd__h155794 =
_theResult____h146240 <<
IF_IF_3970_MINUS_SEXT_IF_requestR_3_BIT_214_4__ETC___d4098 ;
assign _theResult___snd__h165625 =
(requestR_BITS_191_TO_128__q1[62:52] == 11'd0) ?
_theResult___snd__h165639 :
_theResult___snd__h145262 ;
assign _theResult___snd__h165639 =
(requestR_BITS_191_TO_128__q1[62:52] == 11'd0 &&
!requestR_BITS_191_TO_128__q1[51] &&
!requestR_BITS_191_TO_128__q1[50] &&
!requestR_BITS_191_TO_128__q1[49] &&
!requestR_BITS_191_TO_128__q1[48] &&
!requestR_BITS_191_TO_128__q1[47] &&
!requestR_BITS_191_TO_128__q1[46] &&
!requestR_BITS_191_TO_128__q1[45] &&
!requestR_BITS_191_TO_128__q1[44] &&
!requestR_BITS_191_TO_128__q1[43] &&
!requestR_BITS_191_TO_128__q1[42] &&
!requestR_BITS_191_TO_128__q1[41] &&
!requestR_BITS_191_TO_128__q1[40] &&
!requestR_BITS_191_TO_128__q1[39] &&
!requestR_BITS_191_TO_128__q1[38] &&
!requestR_BITS_191_TO_128__q1[37] &&
!requestR_BITS_191_TO_128__q1[36] &&
!requestR_BITS_191_TO_128__q1[35] &&
!requestR_BITS_191_TO_128__q1[34] &&
!requestR_BITS_191_TO_128__q1[33] &&
!requestR_BITS_191_TO_128__q1[32] &&
!requestR_BITS_191_TO_128__q1[31] &&
!requestR_BITS_191_TO_128__q1[30] &&
!requestR_BITS_191_TO_128__q1[29] &&
!requestR_BITS_191_TO_128__q1[28] &&
!requestR_BITS_191_TO_128__q1[27] &&
!requestR_BITS_191_TO_128__q1[26] &&
!requestR_BITS_191_TO_128__q1[25] &&
!requestR_BITS_191_TO_128__q1[24] &&
!requestR_BITS_191_TO_128__q1[23] &&
!requestR_BITS_191_TO_128__q1[22] &&
!requestR_BITS_191_TO_128__q1[21] &&
!requestR_BITS_191_TO_128__q1[20] &&
!requestR_BITS_191_TO_128__q1[19] &&
!requestR_BITS_191_TO_128__q1[18] &&
!requestR_BITS_191_TO_128__q1[17] &&
!requestR_BITS_191_TO_128__q1[16] &&
!requestR_BITS_191_TO_128__q1[15] &&
!requestR_BITS_191_TO_128__q1[14] &&
!requestR_BITS_191_TO_128__q1[13] &&
!requestR_BITS_191_TO_128__q1[12] &&
!requestR_BITS_191_TO_128__q1[11] &&
!requestR_BITS_191_TO_128__q1[10] &&
!requestR_BITS_191_TO_128__q1[9] &&
!requestR_BITS_191_TO_128__q1[8] &&
!requestR_BITS_191_TO_128__q1[7] &&
!requestR_BITS_191_TO_128__q1[6] &&
!requestR_BITS_191_TO_128__q1[5] &&
!requestR_BITS_191_TO_128__q1[4] &&
!requestR_BITS_191_TO_128__q1[3] &&
!requestR_BITS_191_TO_128__q1[2] &&
!requestR_BITS_191_TO_128__q1[1] &&
!requestR_BITS_191_TO_128__q1[0]) ?
sfd__h117253 :
_theResult___snd__h165645 ;
assign _theResult___snd__h165645 =
{ IF_0_CONCAT_IF_IF_requestR_3_BIT_214_4_THEN_re_ETC__q125[54:0],
2'd0 } ;
assign _theResult___snd__h165663 =
sfd__h117253 <<
IF_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR__ETC___d4172 ;
assign _theResult___snd__h190457 =
(sV1_exp__h1472 == 8'd0) ?
_theResult___snd__h190466 :
_theResult___snd__h190459 ;
assign _theResult___snd__h190459 = { sV1_sfd__h1473, 34'd0 } ;
assign _theResult___snd__h190466 =
(sV1_exp__h1472 == 8'd0 && !sV1_sfd__h1473[22] &&
!sV1_sfd__h1473[21] &&
!sV1_sfd__h1473[20] &&
!sV1_sfd__h1473[19] &&
!sV1_sfd__h1473[18] &&
!sV1_sfd__h1473[17] &&
!sV1_sfd__h1473[16] &&
!sV1_sfd__h1473[15] &&
!sV1_sfd__h1473[14] &&
!sV1_sfd__h1473[13] &&
!sV1_sfd__h1473[12] &&
!sV1_sfd__h1473[11] &&
!sV1_sfd__h1473[10] &&
!sV1_sfd__h1473[9] &&
!sV1_sfd__h1473[8] &&
!sV1_sfd__h1473[7] &&
!sV1_sfd__h1473[6] &&
!sV1_sfd__h1473[5] &&
!sV1_sfd__h1473[4] &&
!sV1_sfd__h1473[3] &&
!sV1_sfd__h1473[2] &&
!sV1_sfd__h1473[1] &&
!sV1_sfd__h1473[0]) ?
b__h46021 :
_theResult___snd__h190472 ;
assign _theResult___snd__h190472 =
{ IF_0_CONCAT_IF_IF_IF_requestR_3_BIT_214_4_THEN_ETC__q151[54:0],
2'd0 } ;
assign _theResult___snd__h190495 =
b__h46021 <<
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d4613 ;
assign _theResult___snd__h201345 = { _theResult____h191843[55:0], 1'd0 } ;
assign _theResult___snd__h201356 =
(!_theResult____h191843[56] && _theResult____h191843[55]) ?
_theResult___snd__h201358 :
_theResult___snd__h201368 ;
assign _theResult___snd__h201358 = { _theResult____h191843[54:0], 2'd0 } ;
assign _theResult___snd__h201368 =
(!_theResult____h191843[56] && !_theResult____h191843[55] &&
!_theResult____h191843[54] &&
!_theResult____h191843[53] &&
!_theResult____h191843[52] &&
!_theResult____h191843[51] &&
!_theResult____h191843[50] &&
!_theResult____h191843[49] &&
!_theResult____h191843[48] &&
!_theResult____h191843[47] &&
!_theResult____h191843[46] &&
!_theResult____h191843[45] &&
!_theResult____h191843[44] &&
!_theResult____h191843[43] &&
!_theResult____h191843[42] &&
!_theResult____h191843[41] &&
!_theResult____h191843[40] &&
!_theResult____h191843[39] &&
!_theResult____h191843[38] &&
!_theResult____h191843[37] &&
!_theResult____h191843[36] &&
!_theResult____h191843[35] &&
!_theResult____h191843[34] &&
!_theResult____h191843[33] &&
!_theResult____h191843[32] &&
!_theResult____h191843[31] &&
!_theResult____h191843[30] &&
!_theResult____h191843[29] &&
!_theResult____h191843[28] &&
!_theResult____h191843[27] &&
!_theResult____h191843[26] &&
!_theResult____h191843[25] &&
!_theResult____h191843[24] &&
!_theResult____h191843[23] &&
!_theResult____h191843[22] &&
!_theResult____h191843[21] &&
!_theResult____h191843[20] &&
!_theResult____h191843[19] &&
!_theResult____h191843[18] &&
!_theResult____h191843[17] &&
!_theResult____h191843[16] &&
!_theResult____h191843[15] &&
!_theResult____h191843[14] &&
!_theResult____h191843[13] &&
!_theResult____h191843[12] &&
!_theResult____h191843[11] &&
!_theResult____h191843[10] &&
!_theResult____h191843[9] &&
!_theResult____h191843[8] &&
!_theResult____h191843[7] &&
!_theResult____h191843[6] &&
!_theResult____h191843[5] &&
!_theResult____h191843[4] &&
!_theResult____h191843[3] &&
!_theResult____h191843[2] &&
!_theResult____h191843[1] &&
!_theResult____h191843[0]) ?
_theResult____h191843 :
_theResult___snd__h201374 ;
assign _theResult___snd__h201374 =
{ IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_IF_reques_ETC__q154[54:0],
2'd0 } ;
assign _theResult___snd__h201397 =
_theResult____h191843 <<
IF_IF_3074_MINUS_SEXT_IF_IF_requestR_3_BIT_214_ETC___d4933 ;
assign _theResult___snd__h211344 =
(sV1_exp__h1472 == 8'd0) ?
_theResult___snd__h211358 :
_theResult___snd__h190459 ;
assign _theResult___snd__h211358 =
(sV1_exp__h1472 == 8'd0 && !sV1_sfd__h1473[22] &&
!sV1_sfd__h1473[21] &&
!sV1_sfd__h1473[20] &&
!sV1_sfd__h1473[19] &&
!sV1_sfd__h1473[18] &&
!sV1_sfd__h1473[17] &&
!sV1_sfd__h1473[16] &&
!sV1_sfd__h1473[15] &&
!sV1_sfd__h1473[14] &&
!sV1_sfd__h1473[13] &&
!sV1_sfd__h1473[12] &&
!sV1_sfd__h1473[11] &&
!sV1_sfd__h1473[10] &&
!sV1_sfd__h1473[9] &&
!sV1_sfd__h1473[8] &&
!sV1_sfd__h1473[7] &&
!sV1_sfd__h1473[6] &&
!sV1_sfd__h1473[5] &&
!sV1_sfd__h1473[4] &&
!sV1_sfd__h1473[3] &&
!sV1_sfd__h1473[2] &&
!sV1_sfd__h1473[1] &&
!sV1_sfd__h1473[0]) ?
b__h46021 :
_theResult___snd__h211364 ;
assign _theResult___snd__h211364 =
{ IF_0_CONCAT_IF_IF_IF_requestR_3_BIT_214_4_THEN_ETC__q157[54:0],
2'd0 } ;
assign _theResult___snd__h211382 =
b__h46021 <<
IF_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reques_ETC___d5007 ;
assign _theResult___snd_fst_exp__h109719 =
_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d3071 ?
_theResult___fst_exp__h108958 :
_theResult___fst_exp__h109716 ;
assign _theResult___snd_fst_exp__h109722 =
_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d3070 ?
11'd0 :
_theResult___snd_fst_exp__h109719 ;
assign _theResult___snd_fst_exp__h109725 =
_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d3069 ?
_theResult___snd_fst_exp__h109722 :
11'd2047 ;
assign _theResult___snd_fst_exp__h145865 =
_3074_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_ETC___d3422 ?
_theResult___fst_exp__h136017 :
_theResult___fst_exp__h145862 ;
assign _theResult___snd_fst_exp__h16087 =
_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d450 ?
_theResult___fst_exp__h15528 :
_theResult___fst_exp__h16084 ;
assign _theResult___snd_fst_exp__h16090 =
_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d447 ?
8'd0 :
_theResult___snd_fst_exp__h16087 ;
assign _theResult___snd_fst_exp__h16093 =
_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d445 ?
_theResult___snd_fst_exp__h16090 :
8'd255 ;
assign _theResult___snd_fst_exp__h166260 =
SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_3_B_ETC___d3853 ?
_theResult___fst_exp__h156358 :
_theResult___fst_exp__h166257 ;
assign _theResult___snd_fst_exp__h191265 =
_3970_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_21_ETC___d4543 ?
11'd0 :
_theResult___fst_exp__h191262 ;
assign _theResult___snd_fst_exp__h212182 =
SEXT_IF_IF_requestR_3_BIT_214_4_THEN_requestR__ETC___d4686 ?
_theResult___fst_exp__h202164 :
_theResult___fst_exp__h212179 ;
assign _theResult___snd_fst_exp__h28363 =
_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d972 ?
_theResult___fst_exp__h27805 :
_theResult___fst_exp__h28360 ;
assign _theResult___snd_fst_exp__h28366 =
_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d971 ?
8'd0 :
_theResult___snd_fst_exp__h28363 ;
assign _theResult___snd_fst_exp__h28369 =
_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d970 ?
_theResult___snd_fst_exp__h28366 :
8'd255 ;
assign _theResult___snd_fst_exp__h35537 =
_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d1327 ?
_theResult___fst_exp__h34978 :
_theResult___fst_exp__h35534 ;
assign _theResult___snd_fst_exp__h35540 =
_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d1324 ?
8'd0 :
_theResult___snd_fst_exp__h35537 ;
assign _theResult___snd_fst_exp__h35543 =
_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d1322 ?
_theResult___snd_fst_exp__h35540 :
8'd255 ;
assign _theResult___snd_fst_exp__h42451 =
_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d1580 ?
_theResult___fst_exp__h41893 :
_theResult___fst_exp__h42448 ;
assign _theResult___snd_fst_exp__h42454 =
_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d1579 ?
8'd0 :
_theResult___snd_fst_exp__h42451 ;
assign _theResult___snd_fst_exp__h42457 =
_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d1578 ?
_theResult___snd_fst_exp__h42454 :
8'd255 ;
assign _theResult___snd_fst_exp__h70874 =
_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d2347 ?
_theResult___fst_exp__h70112 :
_theResult___fst_exp__h70871 ;
assign _theResult___snd_fst_exp__h70877 =
_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d2345 ?
11'd0 :
_theResult___snd_fst_exp__h70874 ;
assign _theResult___snd_fst_exp__h70880 =
_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d2343 ?
_theResult___snd_fst_exp__h70877 :
11'd2047 ;
assign _theResult___snd_fst_exp__h81819 =
_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d2561 ?
_theResult___fst_exp__h81058 :
_theResult___fst_exp__h81816 ;
assign _theResult___snd_fst_exp__h81822 =
_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d2560 ?
11'd0 :
_theResult___snd_fst_exp__h81819 ;
assign _theResult___snd_fst_exp__h81825 =
_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d2559 ?
_theResult___snd_fst_exp__h81822 :
11'd2047 ;
assign _theResult___snd_fst_exp__h97196 =
_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d2888 ?
_theResult___fst_exp__h96434 :
_theResult___fst_exp__h97193 ;
assign _theResult___snd_fst_exp__h97199 =
_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d2885 ?
11'd0 :
_theResult___snd_fst_exp__h97196 ;
assign _theResult___snd_fst_exp__h97202 =
_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d2883 ?
_theResult___snd_fst_exp__h97199 :
11'd2047 ;
assign _theResult___snd_fst_sfd__h109720 =
_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d3071 ?
_theResult___fst_sfd__h108959 :
_theResult___fst_sfd__h109717 ;
assign _theResult___snd_fst_sfd__h117207 =
(value__h113092[51:29] == 23'd0) ?
23'd2097152 :
value__h113092[51:29] ;
assign _theResult___snd_fst_sfd__h145866 =
_3074_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_ETC___d3422 ?
_theResult___fst_sfd__h136018 :
_theResult___fst_sfd__h145863 ;
assign _theResult___snd_fst_sfd__h16088 =
_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d450 ?
_theResult___fst_sfd__h15529 :
_theResult___fst_sfd__h16085 ;
assign _theResult___snd_fst_sfd__h166261 =
SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_3_B_ETC___d3853 ?
_theResult___fst_sfd__h156359 :
_theResult___fst_sfd__h166258 ;
assign _theResult___snd_fst_sfd__h169840 =
(value__h167957 == 23'd0) ?
52'h4000000000000 :
out___1_sfd__h167954 ;
assign _theResult___snd_fst_sfd__h191266 =
_3970_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_21_ETC___d4543 ?
52'd0 :
_theResult___fst_sfd__h191263 ;
assign _theResult___snd_fst_sfd__h212183 =
SEXT_IF_IF_requestR_3_BIT_214_4_THEN_requestR__ETC___d4686 ?
_theResult___fst_sfd__h202165 :
_theResult___fst_sfd__h212180 ;
assign _theResult___snd_fst_sfd__h28364 =
_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d972 ?
_theResult___fst_sfd__h27806 :
_theResult___fst_sfd__h28361 ;
assign _theResult___snd_fst_sfd__h35538 =
_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d1327 ?
_theResult___fst_sfd__h34979 :
_theResult___fst_sfd__h35535 ;
assign _theResult___snd_fst_sfd__h42452 =
_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d1580 ?
_theResult___fst_sfd__h41894 :
_theResult___fst_sfd__h42449 ;
assign _theResult___snd_fst_sfd__h70875 =
_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d2347 ?
_theResult___fst_sfd__h70113 :
_theResult___fst_sfd__h70872 ;
assign _theResult___snd_fst_sfd__h81820 =
_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d2561 ?
_theResult___fst_sfd__h81059 :
_theResult___fst_sfd__h81817 ;
assign _theResult___snd_fst_sfd__h97197 =
_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d2888 ?
_theResult___fst_sfd__h96435 :
_theResult___fst_sfd__h97194 ;
assign b__h110422 = { value__h82527, 64'd0 } ;
assign b__h43158 = { value__h43160, 64'd0 } ;
assign b__h46021 = { value__h43160, 32'd0 } ;
assign b__h82525 = { value__h82527, 32'd0 } ;
assign din_inc___2_exp__h109755 = x__h108990[10:0] + 11'd1 ;
assign din_inc___2_exp__h16127 = x__h15560[7:0] + 8'd1 ;
assign din_inc___2_exp__h166288 = _theResult___fst_exp__h135390 + 8'd1 ;
assign din_inc___2_exp__h166312 = _theResult___fst_exp__h145309 + 8'd1 ;
assign din_inc___2_exp__h166342 = _theResult___fst_exp__h155731 + 8'd1 ;
assign din_inc___2_exp__h166366 = _theResult___fst_exp__h165679 + 8'd1 ;
assign din_inc___2_exp__h212214 = _theResult___fst_exp__h190506 + 11'd1 ;
assign din_inc___2_exp__h212244 = _theResult___fst_exp__h201334 + 11'd1 ;
assign din_inc___2_exp__h212268 = _theResult___fst_exp__h211398 + 11'd1 ;
assign din_inc___2_exp__h28399 = x__h27837[7:0] + 8'd1 ;
assign din_inc___2_exp__h35577 = x__h35010[7:0] + 8'd1 ;
assign din_inc___2_exp__h42487 = x__h41925[7:0] + 8'd1 ;
assign din_inc___2_exp__h70914 = x__h70144[10:0] + 11'd1 ;
assign din_inc___2_exp__h81855 = x__h81090[10:0] + 11'd1 ;
assign din_inc___2_exp__h97236 = x__h96466[10:0] + 11'd1 ;
assign fcsr__h3933 =
{ 2'd0,
requestR[191:128] != 64'd0 &&
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d684,
requestR[191:128] != 64'd0 &&
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d687,
requestR[191:128] != 64'd0 &&
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d696 } ;
assign guard__h108246 =
{ IF_sfd___37286_BIT_11_THEN_2_ELSE_0__q27[1],
{ sfd___3__h27286[10:0], 52'd0 } != 63'd0 } ;
assign guard__h108975 =
{ IF_sfd___37286_BIT_10_THEN_2_ELSE_0__q28[1],
{ sfd___3__h27286[9:0], 53'd0 } != 63'd0 } ;
assign guard__h110355 =
{ IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3224[52],
{ IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3224[51:0],
65'd0 } !=
117'd0 } ;
assign guard__h111133 =
{ IF_x11322_BIT_53_THEN_2_ELSE_0__q115[1],
{ x__h111322[52:0], 64'd0 } != 117'd0 } ;
assign guard__h112440 =
{ IF_x12661_BIT_53_THEN_2_ELSE_0__q116[1],
{ x__h112661[52:0], 64'd0 } != 117'd0 } ;
assign guard__h126038 =
{ IF_sfdin35384_BIT_33_THEN_2_ELSE_0__q118[1],
{ sfdin__h135384[32:0], 23'd0 } != 56'd0 } ;
assign guard__h136028 =
{ IF_theResult___snd45260_BIT_33_THEN_2_ELSE_0__q120[1],
{ _theResult___snd__h145260[32:0], 23'd0 } != 56'd0 } ;
assign guard__h146250 =
{ IF_sfdin55725_BIT_33_THEN_2_ELSE_0__q123[1],
{ sfdin__h155725[32:0], 23'd0 } != 56'd0 } ;
assign guard__h146848 = x__h146948 != 57'd0 ;
assign guard__h15015 =
{ IF_sfd___35005_BIT_40_THEN_2_ELSE_0__q9[1],
{ sfd___3__h15005[39:0], 23'd0 } != 63'd0 } ;
assign guard__h15545 =
{ IF_sfd___35005_BIT_39_THEN_2_ELSE_0__q10[1],
{ sfd___3__h15005[38:0], 24'd0 } != 63'd0 } ;
assign guard__h156369 =
{ IF_theResult___snd65625_BIT_33_THEN_2_ELSE_0__q126[1],
{ _theResult___snd__h165625[32:0], 23'd0 } != 56'd0 } ;
assign guard__h181312 =
{ IF_theResult___snd90457_BIT_4_THEN_2_ELSE_0__q152[1],
{ _theResult___snd__h190457[3:0], 52'd0 } != 56'd0 } ;
assign guard__h191853 =
{ IF_sfdin01328_BIT_4_THEN_2_ELSE_0__q155[1],
{ sfdin__h201328[3:0], 52'd0 } != 56'd0 } ;
assign guard__h192451 = x__h192551 != 57'd0 ;
assign guard__h202175 =
{ IF_theResult___snd11344_BIT_4_THEN_2_ELSE_0__q158[1],
{ _theResult___snd__h211344[3:0], 52'd0 } != 56'd0 } ;
assign guard__h27296 =
{ IF_sfd___37286_BIT_40_THEN_2_ELSE_0__q25[1],
{ sfd___3__h27286[39:0], 23'd0 } != 63'd0 } ;
assign guard__h27822 =
{ IF_sfd___37286_BIT_39_THEN_2_ELSE_0__q26[1],
{ sfd___3__h27286[38:0], 24'd0 } != 63'd0 } ;
assign guard__h34468 =
{ IF_sfd___34458_BIT_8_THEN_2_ELSE_0__q41[1],
{ sfd___3__h34458[7:0], 23'd0 } != 31'd0 } ;
assign guard__h34995 =
{ IF_sfd___34458_BIT_7_THEN_2_ELSE_0__q42[1],
{ sfd___3__h34458[6:0], 24'd0 } != 31'd0 } ;
assign guard__h41384 =
{ IF_sfd___31374_BIT_8_THEN_2_ELSE_0__q55[1],
{ sfd___3__h41374[7:0], 23'd0 } != 31'd0 } ;
assign guard__h41910 =
{ IF_sfd___31374_BIT_7_THEN_2_ELSE_0__q56[1],
{ sfd___3__h41374[6:0], 24'd0 } != 31'd0 } ;
assign guard__h43091 =
{ IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1757[23],
{ IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1757[22:0],
65'd0 } !=
88'd0 } ;
assign guard__h43869 =
{ IF_x4058_BIT_24_THEN_2_ELSE_0__q66[1],
{ x__h44058[23:0], 64'd0 } != 88'd0 } ;
assign guard__h45193 =
{ IF_x5414_BIT_24_THEN_2_ELSE_0__q67[1],
{ x__h45414[23:0], 64'd0 } != 88'd0 } ;
assign guard__h45954 =
{ IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1908[23],
{ IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1908[22:0],
33'd0 } !=
56'd0 } ;
assign guard__h46508 =
{ IF_x6697_BIT_24_THEN_2_ELSE_0__q68[1],
{ x__h46697[23:0], 32'd0 } != 56'd0 } ;
assign guard__h47594 =
{ IF_x7815_BIT_24_THEN_2_ELSE_0__q69[1],
{ x__h47815[23:0], 32'd0 } != 56'd0 } ;
assign guard__h69399 =
{ IF_sfd___39389_BIT_2_THEN_2_ELSE_0__q70[1],
{ sfd___3__h69389[1:0], 52'd0 } != 54'd0 } ;
assign guard__h70129 =
{ IF_sfd___39389_BIT_1_THEN_2_ELSE_0__q71[1],
{ sfd___3__h69389[0], 53'd0 } != 54'd0 } ;
assign guard__h80346 =
{ IF_sfd___30336_BIT_2_THEN_2_ELSE_0__q84[1],
{ sfd___3__h80336[1:0], 52'd0 } != 54'd0 } ;
assign guard__h81075 =
{ IF_sfd___30336_BIT_1_THEN_2_ELSE_0__q85[1],
{ sfd___3__h80336[0], 53'd0 } != 54'd0 } ;
assign guard__h82458 =
{ IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2731[52],
{ IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2731[51:0],
33'd0 } !=
85'd0 } ;
assign guard__h83012 =
{ IF_x3201_BIT_53_THEN_2_ELSE_0__q95[1],
{ x__h83201[52:0], 32'd0 } != 85'd0 } ;
assign guard__h84098 =
{ IF_x4319_BIT_53_THEN_2_ELSE_0__q96[1],
{ x__h84319[52:0], 32'd0 } != 85'd0 } ;
assign guard__h95721 =
{ IF_sfd___35005_BIT_11_THEN_2_ELSE_0__q11[1],
{ sfd___3__h15005[10:0], 52'd0 } != 63'd0 } ;
assign guard__h96451 =
{ IF_sfd___35005_BIT_10_THEN_2_ELSE_0__q12[1],
{ sfd___3__h15005[9:0], 53'd0 } != 63'd0 } ;
assign out1___1__h111073 =
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3224[117:53] +
65'd1 ;
assign out1___1__h43809 =
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1757[88:24] +
65'd1 ;
assign out1___1__h46448 =
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1908[56:24] +
33'd1 ;
assign out1___1__h82952 =
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2731[85:53] +
33'd1 ;
assign out___1_sfd__h167954 = { value__h167957, 29'd0 } ;
assign out_exp__h108865 =
sfd___3__h27286[12] ? _theResult___exp__h108862 : 11'd0 ;
assign out_exp__h109620 =
sfd___3__h27286[11] ?
_theResult___exp__h109617 :
x__h108990[10:0] ;
assign out_exp__h135919 =
sfdin__h135384[34] ?
_theResult___exp__h135916 :
_theResult___fst_exp__h135390 ;
assign out_exp__h145764 =
_theResult___snd__h145260[34] ?
_theResult___exp__h145761 :
_theResult___fst_exp__h145309 ;
assign out_exp__h15434 =
sfd___3__h15005[41] ? _theResult___exp__h15431 : 8'd0 ;
assign out_exp__h156260 =
sfdin__h155725[34] ?
_theResult___exp__h156257 :
_theResult___fst_exp__h155731 ;
assign out_exp__h15987 =
sfd___3__h15005[40] ? _theResult___exp__h15984 : x__h15560[7:0] ;
assign out_exp__h166159 =
_theResult___snd__h165625[34] ?
_theResult___exp__h166156 :
_theResult___fst_exp__h165679 ;
assign out_exp__h191164 =
_theResult___snd__h190457[5] ?
_theResult___exp__h191161 :
_theResult___fst_exp__h190506 ;
assign out_exp__h202066 =
sfdin__h201328[5] ?
_theResult___exp__h202063 :
_theResult___fst_exp__h201334 ;
assign out_exp__h212081 =
_theResult___snd__h211344[5] ?
_theResult___exp__h212078 :
_theResult___fst_exp__h211398 ;
assign out_exp__h27712 =
sfd___3__h27286[41] ? _theResult___exp__h27709 : 8'd0 ;
assign out_exp__h28264 =
sfd___3__h27286[40] ? _theResult___exp__h28261 : x__h27837[7:0] ;
assign out_exp__h34884 =
sfd___3__h34458[9] ? _theResult___exp__h34881 : 8'd0 ;
assign out_exp__h35437 =
sfd___3__h34458[8] ? _theResult___exp__h35434 : x__h35010[7:0] ;
assign out_exp__h41800 =
sfd___3__h41374[9] ? _theResult___exp__h41797 : 8'd0 ;
assign out_exp__h42352 =
sfd___3__h41374[8] ? _theResult___exp__h42349 : x__h41925[7:0] ;
assign out_exp__h70018 =
sfd___3__h69389[3] ? _theResult___exp__h70015 : 11'd0 ;
assign out_exp__h70774 =
sfd___3__h69389[2] ? _theResult___exp__h70771 : x__h70144[10:0] ;
assign out_exp__h80965 =
sfd___3__h80336[3] ? _theResult___exp__h80962 : 11'd0 ;
assign out_exp__h81720 =
sfd___3__h80336[2] ? _theResult___exp__h81717 : x__h81090[10:0] ;
assign out_exp__h96340 =
sfd___3__h15005[12] ? _theResult___exp__h96337 : 11'd0 ;
assign out_exp__h97096 =
sfd___3__h15005[11] ?
_theResult___exp__h97093 :
x__h96466[10:0] ;
assign out_sfd__h108866 =
sfd___3__h27286[12] ?
_theResult___sfd__h108863 :
sfd___3__h27286[63:12] ;
assign out_sfd__h109621 =
sfd___3__h27286[11] ?
_theResult___sfd__h109618 :
sfd___3__h27286[62:11] ;
assign out_sfd__h135920 =
sfdin__h135384[34] ?
_theResult___sfd__h135917 :
sfdin__h135384[56:34] ;
assign out_sfd__h145765 =
_theResult___snd__h145260[34] ?
_theResult___sfd__h145762 :
_theResult___snd__h145260[56:34] ;
assign out_sfd__h15435 =
sfd___3__h15005[41] ?
_theResult___sfd__h15432 :
sfd___3__h15005[63:41] ;
assign out_sfd__h156261 =
sfdin__h155725[34] ?
_theResult___sfd__h156258 :
sfdin__h155725[56:34] ;
assign out_sfd__h15988 =
sfd___3__h15005[40] ?
_theResult___sfd__h15985 :
sfd___3__h15005[62:40] ;
assign out_sfd__h166160 =
_theResult___snd__h165625[34] ?
_theResult___sfd__h166157 :
_theResult___snd__h165625[56:34] ;
assign out_sfd__h191165 =
_theResult___snd__h190457[5] ?
_theResult___sfd__h191162 :
_theResult___snd__h190457[56:5] ;
assign out_sfd__h202067 =
sfdin__h201328[5] ?
_theResult___sfd__h202064 :
sfdin__h201328[56:5] ;
assign out_sfd__h212082 =
_theResult___snd__h211344[5] ?
_theResult___sfd__h212079 :
_theResult___snd__h211344[56:5] ;
assign out_sfd__h27713 =
sfd___3__h27286[41] ?
_theResult___sfd__h27710 :
sfd___3__h27286[63:41] ;
assign out_sfd__h28265 =
sfd___3__h27286[40] ?
_theResult___sfd__h28262 :
sfd___3__h27286[62:40] ;
assign out_sfd__h34885 =
sfd___3__h34458[9] ?
_theResult___sfd__h34882 :
sfd___3__h34458[31:9] ;
assign out_sfd__h35438 =
sfd___3__h34458[8] ?
_theResult___sfd__h35435 :
sfd___3__h34458[30:8] ;
assign out_sfd__h41801 =
sfd___3__h41374[9] ?
_theResult___sfd__h41798 :
sfd___3__h41374[31:9] ;
assign out_sfd__h42353 =
sfd___3__h41374[8] ?
_theResult___sfd__h42350 :
sfd___3__h41374[30:8] ;
assign out_sfd__h70019 =
sfd___3__h69389[3] ?
_theResult___sfd__h70016 :
sfd___3__h69389[54:3] ;
assign out_sfd__h70775 =
sfd___3__h69389[2] ?
_theResult___sfd__h70772 :
sfd___3__h69389[53:2] ;
assign out_sfd__h80966 =
sfd___3__h80336[3] ?
_theResult___sfd__h80963 :
sfd___3__h80336[54:3] ;
assign out_sfd__h81721 =
sfd___3__h80336[2] ?
_theResult___sfd__h81718 :
sfd___3__h80336[53:2] ;
assign out_sfd__h96341 =
sfd___3__h15005[12] ?
_theResult___sfd__h96338 :
sfd___3__h15005[63:12] ;
assign out_sfd__h97097 =
sfd___3__h15005[11] ?
_theResult___sfd__h97094 :
sfd___3__h15005[62:11] ;
assign requestR_BITS_127_TO_64__q3 = requestR[127:64] ;
assign requestR_BITS_191_TO_128_BITS_31_TO_0__q2 =
requestR_BITS_191_TO_128__q1[31:0] ;
assign requestR_BITS_191_TO_128__q1 = requestR[191:128] ;
assign requestR_BITS_206_TO_200__q177 = requestR[206:200] ;
assign requestR_BITS_63_TO_0__q8 = requestR[63:0] ;
assign res___1__h229866 =
(requestR_BITS_191_TO_128__q1[62:52] == 11'd2047 &&
requestR_BITS_191_TO_128__q1[51]) ?
64'd512 :
64'd256 ;
assign res___1__h230304 =
requestR_BITS_191_TO_128__q1[63] ? 64'd1 : 64'd128 ;
assign res___1__h230314 =
requestR_BITS_191_TO_128__q1[63] ? 64'd8 : 64'd16 ;
assign res___1__h230333 =
requestR_BITS_191_TO_128__q1[63] ? 64'd4 : 64'd32 ;
assign res___1__h57534 =
(sV1_exp__h1472 == 8'd255 && sV1_sfd__h1473[22]) ?
64'd512 :
64'd256 ;
assign res___1__h57770 =
(requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31]) ?
64'd1 :
64'd128 ;
assign res___1__h57780 =
(requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31]) ?
64'd8 :
64'd16 ;
assign res___1__h57799 =
(requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31]) ?
64'd4 :
64'd32 ;
assign res__h166745 = { 32'hFFFFFFFF, x__h166751 } ;
assign res__h212818 =
{ IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d5189,
x__h167898,
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d5153 } ;
assign res__h217300 =
NOT_IF_requestR_3_BIT_214_4_THEN_requestR_3_BI_ETC___d5330 ?
requestR[191:128] :
requestR[127:64] ;
assign res__h221886 =
NOT_IF_requestR_3_BIT_214_4_THEN_requestR_3_BI_ETC___d5330 ?
requestR[127:64] :
requestR[191:128] ;
assign res__h224628 =
((requestR_BITS_191_TO_128__q1[62:52] != 11'd2047 ||
requestR_BITS_191_TO_128__q1[51:0] == 52'd0) &&
(requestR_BITS_127_TO_64__q3[62:52] != 11'd2047 ||
requestR_BITS_127_TO_64__q3[51:0] == 52'd0) &&
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d5378) ?
64'd1 :
64'd0 ;
assign res__h227363 =
NOT_IF_requestR_3_BIT_214_4_THEN_requestR_3_BI_ETC___d5330 ?
64'd1 :
64'd0 ;
assign res__h229280 =
NOT_IF_requestR_3_BIT_214_4_THEN_requestR_3_BI_ETC___d5399 ?
64'd1 :
64'd0 ;
assign res__h230349 = requestR_BITS_191_TO_128__q1[63] ? 64'd2 : 64'd64 ;
assign res__h230541 = { 32'hFFFFFFFF, fpu$server_core_response_get[36:5] } ;
assign res__h3932 = { 32'hFFFFFFFF, x__h3975 } ;
assign res__h48859 =
{ 32'hFFFFFFFF,
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d48 } ;
assign res__h49096 =
{ 32'hFFFFFFFF,
requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31],
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d37 } ;
assign res__h54627 =
NOT_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_ETC___d2172 ?
64'd1 :
64'd0 ;
assign res__h56150 =
NOT_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_ETC___d2105 ?
64'd1 :
64'd0 ;
assign res__h57259 =
NOT_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_ETC___d2192 ?
64'd1 :
64'd0 ;
assign res__h57815 =
(requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31]) ?
64'd2 :
64'd64 ;
assign result__h146853 =
{ _0b0_CONCAT_NOT_IF_requestR_3_BIT_214_4_THEN_re_ETC___d3858[56:1],
_0b0_CONCAT_NOT_IF_requestR_3_BIT_214_4_THEN_re_ETC___d3858[0] |
guard__h146848 } ;
assign result__h192456 =
{ _0b0_CONCAT_NOT_IF_IF_requestR_3_BIT_214_4_THEN_ETC___d4691[56:1],
_0b0_CONCAT_NOT_IF_IF_requestR_3_BIT_214_4_THEN_ETC___d4691[0] |
guard__h192451 } ;
assign sV1_exp__h1472 =
(requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF) ?
requestR_BITS_191_TO_128__q1[30:23] :
8'd255 ;
assign sV1_sfd__h1473 =
(requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF) ?
requestR_BITS_191_TO_128__q1[22:0] :
23'd4194304 ;
assign sV2_exp__h1597 =
(requestR_BITS_127_TO_64__q3[63:32] == 32'hFFFFFFFF) ?
requestR_BITS_127_TO_64__q3[30:23] :
8'd255 ;
assign sV2_sfd__h1598 =
(requestR_BITS_127_TO_64__q3[63:32] == 32'hFFFFFFFF) ?
requestR_BITS_127_TO_64__q3[22:0] :
23'd4194304 ;
assign sfd___3__h15005 =
sfd__h3990 <<
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d441 ;
assign sfd___3__h27286 =
requestR[191:128] <<
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d966 ;
assign sfd___3__h34458 =
sfd__h28849 <<
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d1318 ;
assign sfd___3__h41374 =
requestR_BITS_191_TO_128__q1[31:0] <<
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1574 ;
assign sfd___3__h69389 =
sfd__h60177 <<
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d2339 ;
assign sfd___3__h80336 =
sfd__h71373 <<
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2555 ;
assign sfd__h108263 = { 2'd0, sfd___3__h27286[63:12] } + 54'd1 ;
assign sfd__h109005 =
{ 1'b0, x__h108990[10:0] != 11'd0, sfd___3__h27286[62:11] } +
54'd1 ;
assign sfd__h117253 = { value__h82527, 3'd0 } ;
assign sfd__h135482 =
{ 1'b0,
_theResult___fst_exp__h135390 != 8'd0,
sfdin__h135384[56:34] } +
25'd1 ;
assign sfd__h145327 =
{ 1'b0,
_theResult___fst_exp__h145309 != 8'd0,
_theResult___snd__h145260[56:34] } +
25'd1 ;
assign sfd__h15032 = { 2'd0, sfd___3__h15005[63:41] } + 25'd1 ;
assign sfd__h15575 =
{ 1'b0, x__h15560[7:0] != 8'd0, sfd___3__h15005[62:40] } +
25'd1 ;
assign sfd__h155823 =
{ 1'b0,
_theResult___fst_exp__h155731 != 8'd0,
sfdin__h155725[56:34] } +
25'd1 ;
assign sfd__h165698 =
{ 1'b0,
_theResult___fst_exp__h165679 != 8'd0,
_theResult___snd__h165625[56:34] } +
25'd1 ;
assign sfd__h190524 =
{ 1'b0,
_theResult___fst_exp__h190506 != 11'd0,
_theResult___snd__h190457[56:5] } +
54'd1 ;
assign sfd__h201426 =
{ 1'b0,
_theResult___fst_exp__h201334 != 11'd0,
sfdin__h201328[56:5] } +
54'd1 ;
assign sfd__h211417 =
{ 1'b0,
_theResult___fst_exp__h211398 != 11'd0,
_theResult___snd__h211344[56:5] } +
54'd1 ;
assign sfd__h27313 = { 2'd0, sfd___3__h27286[63:41] } + 25'd1 ;
assign sfd__h27852 =
{ 1'b0, x__h27837[7:0] != 8'd0, sfd___3__h27286[62:40] } +
25'd1 ;
assign sfd__h28849 =
requestR_BITS_191_TO_128__q1[31] ?
-requestR_BITS_191_TO_128__q1[31:0] :
requestR_BITS_191_TO_128__q1[31:0] ;
assign sfd__h34485 = { 2'd0, sfd___3__h34458[31:9] } + 25'd1 ;
assign sfd__h35025 =
{ 1'b0, x__h35010[7:0] != 8'd0, sfd___3__h34458[30:8] } + 25'd1 ;
assign sfd__h3990 =
requestR_BITS_191_TO_128__q1[63] ?
-requestR[191:128] :
requestR[191:128] ;
assign sfd__h41401 = { 2'd0, sfd___3__h41374[31:9] } + 25'd1 ;
assign sfd__h41940 =
{ 1'b0, x__h41925[7:0] != 8'd0, sfd___3__h41374[30:8] } + 25'd1 ;
assign sfd__h60177 = { sfd__h28849, 23'd0 } ;
assign sfd__h69416 = { 2'd0, sfd___3__h69389[54:3] } + 54'd1 ;
assign sfd__h70159 =
{ 1'b0, x__h70144[10:0] != 11'd0, sfd___3__h69389[53:2] } +
54'd1 ;
assign sfd__h71373 = { requestR_BITS_191_TO_128__q1[31:0], 23'd0 } ;
assign sfd__h80363 = { 2'd0, sfd___3__h80336[54:3] } + 54'd1 ;
assign sfd__h81105 =
{ 1'b0, x__h81090[10:0] != 11'd0, sfd___3__h80336[53:2] } +
54'd1 ;
assign sfd__h95738 = { 2'd0, sfd___3__h15005[63:12] } + 54'd1 ;
assign sfd__h96481 =
{ 1'b0, x__h96466[10:0] != 11'd0, sfd___3__h15005[62:11] } +
54'd1 ;
assign sfdin__h135384 =
_theResult____h126028[56] ?
_theResult___snd__h135401 :
_theResult___snd__h135412 ;
assign sfdin__h155725 =
_theResult____h146240[56] ?
_theResult___snd__h155742 :
_theResult___snd__h155753 ;
assign sfdin__h201328 =
_theResult____h191843[56] ?
_theResult___snd__h201345 :
_theResult___snd__h201356 ;
assign value__h113092 =
(requestR_BITS_191_TO_128__q1[62:52] == 11'd2047 &&
requestR_BITS_191_TO_128__q1[51:0] != 52'd0 &&
!requestR_BITS_191_TO_128__q1[51]) ?
_theResult___fst_sfd__h113549 :
requestR_BITS_191_TO_128__q1[51:0] ;
assign value__h167957 =
(sV1_exp__h1472 == 8'd255 && sV1_sfd__h1473 != 23'd0 &&
!sV1_sfd__h1473[22]) ?
_theResult___fst_sfd__h168212 :
sV1_sfd__h1473 ;
assign value__h43160 = { 1'b0, sV1_exp__h1472 != 8'd0, sV1_sfd__h1473 } ;
assign value__h82527 =
{ 1'b0,
requestR_BITS_191_TO_128__q1[62:52] != 11'd0,
requestR_BITS_191_TO_128__q1[51:0] } ;
assign x__h108990 =
_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d3068 +
12'd1023 ;
assign x__h109855 =
{ 2'd0,
requestR[191:128] != 64'd0 &&
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d3199,
requestR[191:128] != 64'd0 &&
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d3202,
requestR[191:128] != 64'd0 &&
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d3211 } ;
assign x__h110179 =
(requestR_BITS_191_TO_128__q1[62:52] == 11'd2047 &&
requestR_BITS_191_TO_128__q1[51:0] != 52'd0 ||
!requestR_BITS_191_TO_128__q1[63] &&
requestR_BITS_191_TO_128__q1[62:52] == 11'd2047 &&
requestR_BITS_191_TO_128__q1[51:0] == 52'd0) ?
64'h7FFFFFFFFFFFFFFF :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3283 ;
assign x__h111322 =
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3224 >>
NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d3250 |
~(118'h3FFFFFFFFFFFFFFFFFFFFFFFFFFFFF >>
NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d3250) &
{118{IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3224[117]}} ;
assign x__h111943 =
{ requestR_BITS_191_TO_128__q1[62:52] == 11'd2047 &&
requestR_BITS_191_TO_128__q1[51:0] != 52'd0 ||
requestR_BITS_191_TO_128__q1[62:52] == 11'd2047 &&
requestR_BITS_191_TO_128__q1[51:0] == 52'd0 ||
NOT_IF_requestR_3_BIT_214_4_THEN_requestR_3_BI_ETC___d3290,
3'd0,
(requestR_BITS_191_TO_128__q1[62:52] != 11'd2047 ||
requestR_BITS_191_TO_128__q1[51:0] == 52'd0) &&
(requestR_BITS_191_TO_128__q1[62:52] != 11'd2047 ||
requestR_BITS_191_TO_128__q1[51:0] != 52'd0) &&
(requestR_BITS_191_TO_128__q1[62:52] != 11'd0 ||
requestR_BITS_191_TO_128__q1[51:0] != 52'd0) &&
IF_NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d3298 } ;
assign x__h112240 =
(requestR_BITS_191_TO_128__q1[62:52] == 11'd2047 &&
requestR_BITS_191_TO_128__q1[51:0] != 52'd0 ||
!requestR_BITS_191_TO_128__q1[63] &&
requestR_BITS_191_TO_128__q1[62:52] == 11'd2047 &&
requestR_BITS_191_TO_128__q1[51:0] == 52'd0) ?
64'hFFFFFFFFFFFFFFFF :
(requestR_BITS_191_TO_128__q1[63] ?
64'd0 :
((requestR_BITS_191_TO_128__q1[62:52] == 11'd2047 &&
requestR_BITS_191_TO_128__q1[51:0] == 52'd0) ?
64'hFFFFFFFFFFFFFFFF :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3337)) ;
assign x__h112661 =
{ requestR_BITS_191_TO_128__q1[62:52] != 11'd0,
requestR_BITS_191_TO_128__q1[51:0],
65'd0 } >>
NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d3308 ;
assign x__h112739 =
{ requestR_BITS_191_TO_128__q1[63] ?
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d3357 :
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d3346,
3'd0,
(requestR_BITS_191_TO_128__q1[62:52] != 11'd2047 ||
requestR_BITS_191_TO_128__q1[51:0] == 52'd0) &&
(requestR_BITS_191_TO_128__q1[62:52] != 11'd2047 ||
requestR_BITS_191_TO_128__q1[51:0] != 52'd0) &&
NOT_IF_requestR_3_BIT_214_4_THEN_requestR_3_BI_ETC___d3351 } ;
assign x__h113022 =
(x__h113032 == 8'd255 &&
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4338[22]) ?
64'hFFFFFFFF7FC00000 :
res__h166745 ;
assign x__h113032 =
(requestR_BITS_191_TO_128__q1[62:52] == 11'd2047) ?
8'd255 :
_theResult___fst_exp__h166269 ;
assign x__h146948 = sfd__h117253 << x__h146981 ;
assign x__h146981 =
12'd57 -
_3970_MINUS_SEXT_IF_requestR_3_BIT_214_4_THEN_r_ETC___d3854 ;
assign x__h15560 =
_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d444 +
9'd127 ;
assign x__h166751 =
{ (requestR_BITS_191_TO_128__q1[62:52] == 11'd2047 &&
requestR_BITS_191_TO_128__q1[51:0] != 52'd0 ||
(requestR_BITS_191_TO_128__q1[62:52] == 11'd2047 ||
requestR_BITS_191_TO_128__q1[62:52] == 11'd0) &&
requestR_BITS_191_TO_128__q1[51:0] == 52'd0) ?
requestR_BITS_191_TO_128__q1[63] :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4378,
x__h113032,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4338 } ;
assign x__h166866 =
{ (requestR_BITS_191_TO_128__q1[62:52] == 11'd2047 &&
requestR_BITS_191_TO_128__q1[51:0] != 52'd0) ?
requestR_BITS_191_TO_128__q1[62:52] == 11'd2047 &&
requestR_BITS_191_TO_128__q1[51:0] != 52'd0 &&
!requestR_BITS_191_TO_128__q1[51] :
(requestR_BITS_191_TO_128__q1[62:52] != 11'd2047 ||
requestR_BITS_191_TO_128__q1[51:0] != 52'd0) &&
(requestR_BITS_191_TO_128__q1[62:52] != 11'd0 ||
requestR_BITS_191_TO_128__q1[51:0] != 52'd0) &&
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4429,
(requestR_BITS_191_TO_128__q1[62:52] != 11'd2047 ||
requestR_BITS_191_TO_128__q1[51:0] == 52'd0) &&
(requestR_BITS_191_TO_128__q1[62:52] != 11'd2047 ||
requestR_BITS_191_TO_128__q1[51:0] != 52'd0) &&
(requestR_BITS_191_TO_128__q1[62:52] != 11'd0 ||
requestR_BITS_191_TO_128__q1[51:0] != 52'd0) &&
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4440,
(requestR_BITS_191_TO_128__q1[62:52] != 11'd2047 ||
requestR_BITS_191_TO_128__q1[51:0] == 52'd0) &&
(requestR_BITS_191_TO_128__q1[62:52] != 11'd2047 ||
requestR_BITS_191_TO_128__q1[51:0] != 52'd0) &&
(requestR_BITS_191_TO_128__q1[62:52] != 11'd0 ||
requestR_BITS_191_TO_128__q1[51:0] != 52'd0) &&
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4456,
(requestR_BITS_191_TO_128__q1[62:52] != 11'd2047 ||
requestR_BITS_191_TO_128__q1[51:0] == 52'd0) &&
(requestR_BITS_191_TO_128__q1[62:52] != 11'd2047 ||
requestR_BITS_191_TO_128__q1[51:0] != 52'd0) &&
(requestR_BITS_191_TO_128__q1[62:52] != 11'd0 ||
requestR_BITS_191_TO_128__q1[51:0] != 52'd0) &&
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4469,
(requestR_BITS_191_TO_128__q1[62:52] != 11'd2047 ||
requestR_BITS_191_TO_128__q1[51:0] == 52'd0) &&
(requestR_BITS_191_TO_128__q1[62:52] != 11'd2047 ||
requestR_BITS_191_TO_128__q1[51:0] != 52'd0) &&
(requestR_BITS_191_TO_128__q1[62:52] != 11'd0 ||
requestR_BITS_191_TO_128__q1[51:0] != 52'd0) &&
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4482 } ;
assign x__h16727 =
{ 33'h1FFFFFFFE,
(requestR[191:128] == 64'd0) ?
8'd0 :
_theResult___snd_fst_exp__h28369,
(requestR[191:128] == 64'd0 ||
NOT_IF_requestR_3_BIT_214_4_THEN_requestR_3_BI_ETC___d1059) ?
23'd0 :
_theResult___snd_fst_sfd__h28364 } ;
assign x__h167888 =
(x__h167898 == 11'd2047 &&
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d5153[51]) ?
64'h7FF8000000000000 :
res__h212818 ;
assign x__h167898 =
(sV1_exp__h1472 == 8'd255) ?
11'd2047 :
_theResult___fst_exp__h212191 ;
assign x__h192551 = b__h46021 << x__h192584 ;
assign x__h192584 =
12'd57 -
_3074_MINUS_SEXT_IF_IF_requestR_3_BIT_214_4_THE_ETC___d4687 ;
assign x__h212920 =
{ IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d5227,
(sV1_exp__h1472 != 8'd255 || sV1_sfd__h1473 == 23'd0) &&
(sV1_exp__h1472 != 8'd255 || sV1_sfd__h1473 != 23'd0) &&
(sV1_exp__h1472 != 8'd0 || sV1_sfd__h1473 != 23'd0) &&
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d5234,
(sV1_exp__h1472 != 8'd255 || sV1_sfd__h1473 == 23'd0) &&
(sV1_exp__h1472 != 8'd255 || sV1_sfd__h1473 != 23'd0) &&
(sV1_exp__h1472 != 8'd0 || sV1_sfd__h1473 != 23'd0) &&
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d5248,
(sV1_exp__h1472 != 8'd255 || sV1_sfd__h1473 == 23'd0) &&
(sV1_exp__h1472 != 8'd255 || sV1_sfd__h1473 != 23'd0) &&
(sV1_exp__h1472 != 8'd0 || sV1_sfd__h1473 != 23'd0) &&
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d5260,
(sV1_exp__h1472 != 8'd255 || sV1_sfd__h1473 == 23'd0) &&
(sV1_exp__h1472 != 8'd255 || sV1_sfd__h1473 != 23'd0) &&
(sV1_exp__h1472 != 8'd0 || sV1_sfd__h1473 != 23'd0) &&
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d5272 } ;
assign x__h213882 =
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d5294 ?
64'h7FF8000000000000 :
((requestR_BITS_191_TO_128__q1[62:52] == 11'd2047 &&
requestR_BITS_191_TO_128__q1[51:0] != 52'd0 &&
!requestR_BITS_191_TO_128__q1[51]) ?
requestR[127:64] :
((requestR_BITS_127_TO_64__q3[62:52] == 11'd2047 &&
requestR_BITS_127_TO_64__q3[51:0] != 52'd0 &&
!requestR_BITS_127_TO_64__q3[51]) ?
requestR[191:128] :
((requestR_BITS_191_TO_128__q1[62:52] == 11'd2047 &&
requestR_BITS_191_TO_128__q1[51] &&
requestR_BITS_127_TO_64__q3[62:52] == 11'd2047 &&
requestR_BITS_127_TO_64__q3[51]) ?
64'h7FF8000000000000 :
((requestR_BITS_191_TO_128__q1[62:52] == 11'd2047 &&
requestR_BITS_191_TO_128__q1[51]) ?
requestR[127:64] :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d5333)))) ;
assign x__h217430 =
{ IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d5339,
4'd0 } ;
assign x__h218468 =
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d5294 ?
64'h7FF8000000000000 :
((requestR_BITS_191_TO_128__q1[62:52] == 11'd2047 &&
requestR_BITS_191_TO_128__q1[51:0] != 52'd0 &&
!requestR_BITS_191_TO_128__q1[51]) ?
requestR[127:64] :
((requestR_BITS_127_TO_64__q3[62:52] == 11'd2047 &&
requestR_BITS_127_TO_64__q3[51:0] != 52'd0 &&
!requestR_BITS_127_TO_64__q3[51]) ?
requestR[191:128] :
((requestR_BITS_191_TO_128__q1[62:52] == 11'd2047 &&
requestR_BITS_191_TO_128__q1[51] &&
requestR_BITS_127_TO_64__q3[62:52] == 11'd2047 &&
requestR_BITS_127_TO_64__q3[51]) ?
64'h7FF8000000000000 :
((requestR_BITS_191_TO_128__q1[62:52] == 11'd2047 &&
requestR_BITS_191_TO_128__q1[51]) ?
requestR[127:64] :
((requestR_BITS_127_TO_64__q3[62:52] == 11'd2047 &&
requestR_BITS_127_TO_64__q3[51]) ?
requestR[191:128] :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d5348))))) ;
assign x__h222950 =
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d5363 ?
64'd0 :
res__h224628 ;
assign x__h225685 =
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d5363 ?
64'd0 :
res__h227363 ;
assign x__h227382 =
{ requestR_BITS_191_TO_128__q1[62:52] == 11'd2047 &&
requestR_BITS_191_TO_128__q1[51:0] != 52'd0 ||
requestR_BITS_127_TO_64__q3[62:52] == 11'd2047 &&
requestR_BITS_127_TO_64__q3[51:0] != 52'd0,
4'd0 } ;
assign x__h227602 =
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d5363 ?
64'd0 :
res__h229280 ;
assign x__h229846 =
(requestR_BITS_191_TO_128__q1[62:52] == 11'd2047 &&
requestR_BITS_191_TO_128__q1[51:0] != 52'd0) ?
res___1__h229866 :
((requestR_BITS_191_TO_128__q1[62:52] == 11'd2047 &&
requestR_BITS_191_TO_128__q1[51:0] == 52'd0) ?
res___1__h230304 :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d5426) ;
assign x__h230460 =
fpu$server_core_response_get[69] ?
((fpu$server_core_response_get[35:28] == 8'd255 &&
fpu$server_core_response_get[27:5] != 23'd0) ?
64'hFFFFFFFF7FC00000 :
res__h230541) :
((fpu$server_core_response_get[67:57] == 11'd2047 &&
fpu$server_core_response_get[56:5] != 52'd0) ?
64'h7FF8000000000000 :
fpu$server_core_response_get[68:5]) ;
assign x__h27837 =
_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d969 +
9'd127 ;
assign x__h28503 =
{ 2'd0,
requestR[191:128] != 64'd0 &&
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d1165,
requestR[191:128] != 64'd0 &&
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d1168,
requestR[191:128] != 64'd0 &&
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d1177 } ;
assign x__h28828 = { 32'hFFFFFFFF, x__h28834 } ;
assign x__h28834 =
{ requestR_BITS_191_TO_128__q1[31:0] != 32'd0 &&
(NOT_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_ETC___d1326 ?
requestR_BITS_191_TO_128__q1[31] :
IF_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_2_ETC___d1379),
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1439,
(requestR_BITS_191_TO_128__q1[31:0] == 32'd0 ||
NOT_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_ETC___d1326) ?
23'd0 :
_theResult___snd_fst_sfd__h35538 } ;
assign x__h3429 = { 32'hFFFFFFFF, x__h3436 } ;
assign x__h3436 =
{ requestR_BITS_127_TO_64__q3[63:32] == 32'hFFFFFFFF &&
requestR_BITS_127_TO_64__q3[31],
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d37 } ;
assign x__h35010 =
_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d1321 +
9'd127 ;
assign x__h35703 =
{ 2'd0,
requestR_BITS_191_TO_128__q1[31:0] != 32'd0 &&
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1520,
requestR_BITS_191_TO_128__q1[31:0] != 32'd0 &&
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1523,
requestR_BITS_191_TO_128__q1[31:0] != 32'd0 &&
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1532 } ;
assign x__h36028 =
{ 33'h1FFFFFFFE,
(requestR_BITS_191_TO_128__q1[31:0] == 32'd0) ?
8'd0 :
_theResult___snd_fst_exp__h42457,
(requestR_BITS_191_TO_128__q1[31:0] == 32'd0 ||
NOT_IF_requestR_3_BIT_214_4_THEN_requestR_3_BI_ETC___d1666) ?
23'd0 :
_theResult___snd_fst_sfd__h42452 } ;
assign x__h3605 = { 32'hFFFFFFFF, x__h3612 } ;
assign x__h3612 =
{ requestR_BITS_127_TO_64__q3[63:32] != 32'hFFFFFFFF ||
!requestR_BITS_127_TO_64__q3[31],
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d37 } ;
assign x__h3778 = { 32'hFFFFFFFF, x__h3785 } ;
assign x__h3785 =
{ (requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31]) !=
(requestR_BITS_127_TO_64__q3[63:32] == 32'hFFFFFFFF &&
requestR_BITS_127_TO_64__q3[31]),
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d37 } ;
assign x__h3975 =
{ requestR[191:128] != 64'd0 &&
(NOT_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_ETC___d449 ?
requestR_BITS_191_TO_128__q1[63] :
IF_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_2_ETC___d511),
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d571,
(requestR[191:128] == 64'd0 ||
NOT_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_ETC___d449) ?
23'd0 :
_theResult___snd_fst_sfd__h16088 } ;
assign x__h41925 =
_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d1577 +
9'd127 ;
assign x__h42591 =
{ 2'd0,
requestR_BITS_191_TO_128__q1[31:0] != 32'd0 &&
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d1709,
requestR_BITS_191_TO_128__q1[31:0] != 32'd0 &&
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d1712,
requestR_BITS_191_TO_128__q1[31:0] != 32'd0 &&
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d1721 } ;
assign x__h42915 =
(sV1_exp__h1472 == 8'd255 && sV1_sfd__h1473 != 23'd0 ||
(requestR_BITS_191_TO_128__q1[63:32] != 32'hFFFFFFFF ||
!requestR_BITS_191_TO_128__q1[31]) &&
sV1_exp__h1472 == 8'd255 &&
sV1_sfd__h1473 == 23'd0) ?
64'h7FFFFFFFFFFFFFFF :
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d1816 ;
assign x__h44058 =
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1757 >>
NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1783 |
~(89'h1FFFFFFFFFFFFFFFFFFFFFF >>
NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1783) &
{89{IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1757[88]}} ;
assign x__h44696 =
{ sV1_exp__h1472 == 8'd255 && sV1_sfd__h1473 != 23'd0 ||
sV1_exp__h1472 == 8'd255 && sV1_sfd__h1473 == 23'd0 ||
NOT_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_ETC___d1826,
3'd0,
(sV1_exp__h1472 != 8'd255 || sV1_sfd__h1473 == 23'd0) &&
(sV1_exp__h1472 != 8'd255 || sV1_sfd__h1473 != 23'd0) &&
(sV1_exp__h1472 != 8'd0 || sV1_sfd__h1473 != 23'd0) &&
IF_NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_re_ETC___d1837 } ;
assign x__h44993 =
(sV1_exp__h1472 == 8'd255 && sV1_sfd__h1473 != 23'd0 ||
(requestR_BITS_191_TO_128__q1[63:32] != 32'hFFFFFFFF ||
!requestR_BITS_191_TO_128__q1[31]) &&
sV1_exp__h1472 == 8'd255 &&
sV1_sfd__h1473 == 23'd0) ?
64'hFFFFFFFFFFFFFFFF :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1878 ;
assign x__h45414 =
{ sV1_exp__h1472 != 8'd0, sV1_sfd__h1473, 65'd0 } >>
NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1847 ;
assign x__h45492 =
{ (requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31]) ?
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1896 :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1885,
3'd0,
(sV1_exp__h1472 != 8'd255 || sV1_sfd__h1473 == 23'd0) &&
(sV1_exp__h1472 != 8'd255 || sV1_sfd__h1473 != 23'd0) &&
NOT_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_ETC___d1890 } ;
assign x__h45775 = { {32{x__h45778[31]}}, x__h45778 } ;
assign x__h45778 =
(sV1_exp__h1472 == 8'd255 && sV1_sfd__h1473 != 23'd0 ||
(requestR_BITS_191_TO_128__q1[63:32] != 32'hFFFFFFFF ||
!requestR_BITS_191_TO_128__q1[31]) &&
sV1_exp__h1472 == 8'd255 &&
sV1_sfd__h1473 == 23'd0) ?
32'h7FFFFFFF :
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d1967 ;
assign x__h46697 =
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1908 >>
NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1934 |
~(57'h1FFFFFFFFFFFFFF >>
NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1934) &
{57{IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1908[56]}} ;
assign x__h47094 =
{ sV1_exp__h1472 == 8'd255 && sV1_sfd__h1473 != 23'd0 ||
sV1_exp__h1472 == 8'd255 && sV1_sfd__h1473 == 23'd0 ||
NOT_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_ETC___d1975,
3'd0,
(sV1_exp__h1472 != 8'd255 || sV1_sfd__h1473 == 23'd0) &&
(sV1_exp__h1472 != 8'd255 || sV1_sfd__h1473 != 23'd0) &&
(sV1_exp__h1472 != 8'd0 || sV1_sfd__h1473 != 23'd0) &&
IF_NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_re_ETC___d1983 } ;
assign x__h47391 = { {32{x__h47394[31]}}, x__h47394 } ;
assign x__h47394 =
(sV1_exp__h1472 == 8'd255 && sV1_sfd__h1473 != 23'd0 ||
(requestR_BITS_191_TO_128__q1[63:32] != 32'hFFFFFFFF ||
!requestR_BITS_191_TO_128__q1[31]) &&
sV1_exp__h1472 == 8'd255 &&
sV1_sfd__h1473 == 23'd0) ?
32'hFFFFFFFF :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2024 ;
assign x__h47815 =
{ sV1_exp__h1472 != 8'd0, sV1_sfd__h1473, 33'd0 } >>
NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1993 ;
assign x__h47893 =
{ (requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31]) ?
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2043 :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2032,
3'd0,
(sV1_exp__h1472 != 8'd255 || sV1_sfd__h1473 == 23'd0) &&
(sV1_exp__h1472 != 8'd255 || sV1_sfd__h1473 != 23'd0) &&
NOT_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_ETC___d2037 } ;
assign x__h48180 =
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2067 ?
64'hFFFFFFFF7FC00000 :
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d2113 ;
assign x__h50220 =
{ IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2115,
4'd0 } ;
assign x__h50854 =
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2067 ?
64'hFFFFFFFF7FC00000 :
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d2130 ;
assign x__h53419 = { 32'hFFFFFFFF, requestR_BITS_191_TO_128__q1[31:0] } ;
assign x__h53579 =
{ {32{requestR_BITS_191_TO_128_BITS_31_TO_0__q2[31]}},
requestR_BITS_191_TO_128_BITS_31_TO_0__q2 } ;
assign x__h53757 =
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2156 ?
64'd0 :
res__h54627 ;
assign x__h55280 =
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2156 ?
64'd0 :
res__h56150 ;
assign x__h56169 =
{ sV1_exp__h1472 == 8'd255 && sV1_sfd__h1473 != 23'd0 ||
sV2_exp__h1597 == 8'd255 && sV2_sfd__h1598 != 23'd0,
4'd0 } ;
assign x__h56389 =
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2156 ?
64'd0 :
res__h57259 ;
assign x__h57514 =
(sV1_exp__h1472 == 8'd255 && sV1_sfd__h1473 != 23'd0) ?
res___1__h57534 :
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d2207 ;
assign x__h59668 =
{ requestR_BITS_127_TO_64__q3[63],
requestR_BITS_191_TO_128__q1[62:0] } ;
assign x__h59829 =
{ !requestR_BITS_127_TO_64__q3[63],
requestR_BITS_191_TO_128__q1[62:0] } ;
assign x__h59992 =
{ requestR_BITS_191_TO_128__q1[63] !=
requestR_BITS_127_TO_64__q3[63],
requestR_BITS_191_TO_128__q1[62:0] } ;
assign x__h60162 =
{ requestR_BITS_191_TO_128__q1[31:0] != 32'd0 &&
IF_NOT_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_B_ETC___d2399,
(requestR_BITS_191_TO_128__q1[31:0] == 32'd0) ?
11'd0 :
_theResult___snd_fst_exp__h70880,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2496 } ;
assign x__h70144 =
_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d2342 +
12'd1023 ;
assign x__h71036 =
{ 2'd0,
requestR_BITS_191_TO_128__q1[31:0] != 32'd0 &&
(!_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d2343 ||
!_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d2345 &&
!_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d2347 &&
_theResult___fst_exp__h70871 == 11'd2047 &&
_theResult___fst_sfd__h70872 == 52'd0),
requestR_BITS_191_TO_128__q1[31:0] != 32'd0 &&
_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d2343 &&
_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d2345,
requestR_BITS_191_TO_128__q1[31:0] != 32'd0 &&
_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d2343 &&
!_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d2345 &&
IF_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_2_ETC___d2513 } ;
assign x__h71361 =
{ 1'd0,
(requestR_BITS_191_TO_128__q1[31:0] == 32'd0) ?
11'd0 :
_theResult___snd_fst_exp__h81825,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2680 } ;
assign x__h81090 =
_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d2558 +
12'd1023 ;
assign x__h81955 =
{ 2'd0,
requestR_BITS_191_TO_128__q1[31:0] != 32'd0 &&
(!_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d2559 ||
!_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d2560 &&
!_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d2561 &&
_theResult___fst_exp__h81816 == 11'd2047 &&
_theResult___fst_sfd__h81817 == 52'd0),
requestR_BITS_191_TO_128__q1[31:0] != 32'd0 &&
_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d2559 &&
_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d2560,
requestR_BITS_191_TO_128__q1[31:0] != 32'd0 &&
_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d2559 &&
!_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d2560 &&
IF_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214__ETC___d2697 } ;
assign x__h82279 = { {32{x__h82282[31]}}, x__h82282 } ;
assign x__h82282 =
(requestR_BITS_191_TO_128__q1[62:52] == 11'd2047 &&
requestR_BITS_191_TO_128__q1[51:0] != 52'd0 ||
!requestR_BITS_191_TO_128__q1[63] &&
requestR_BITS_191_TO_128__q1[62:52] == 11'd2047 &&
requestR_BITS_191_TO_128__q1[51:0] == 52'd0) ?
32'h7FFFFFFF :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2790 ;
assign x__h83201 =
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2731 >>
NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2757 |
~(86'h3FFFFFFFFFFFFFFFFFFFFF >>
NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2757) &
{86{IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2731[85]}} ;
assign x__h83598 =
{ requestR_BITS_191_TO_128__q1[62:52] == 11'd2047 &&
requestR_BITS_191_TO_128__q1[51:0] != 52'd0 ||
requestR_BITS_191_TO_128__q1[62:52] == 11'd2047 &&
requestR_BITS_191_TO_128__q1[51:0] == 52'd0 ||
NOT_IF_requestR_3_BIT_214_4_THEN_requestR_3_BI_ETC___d2801,
3'd0,
(requestR_BITS_191_TO_128__q1[62:52] != 11'd2047 ||
requestR_BITS_191_TO_128__q1[51:0] == 52'd0) &&
(requestR_BITS_191_TO_128__q1[62:52] != 11'd2047 ||
requestR_BITS_191_TO_128__q1[51:0] != 52'd0) &&
(requestR_BITS_191_TO_128__q1[62:52] != 11'd0 ||
requestR_BITS_191_TO_128__q1[51:0] != 52'd0) &&
IF_NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d2812 } ;
assign x__h83895 = { {32{x__h83898[31]}}, x__h83898 } ;
assign x__h83898 =
(requestR_BITS_191_TO_128__q1[62:52] == 11'd2047 &&
requestR_BITS_191_TO_128__q1[51:0] != 52'd0 ||
!requestR_BITS_191_TO_128__q1[63] &&
requestR_BITS_191_TO_128__q1[62:52] == 11'd2047 &&
requestR_BITS_191_TO_128__q1[51:0] == 52'd0) ?
32'hFFFFFFFF :
(requestR_BITS_191_TO_128__q1[63] ?
32'd0 :
((requestR_BITS_191_TO_128__q1[62:52] == 11'd2047 &&
requestR_BITS_191_TO_128__q1[51:0] == 52'd0) ?
32'hFFFFFFFF :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2851)) ;
assign x__h84319 =
{ requestR_BITS_191_TO_128__q1[62:52] != 11'd0,
requestR_BITS_191_TO_128__q1[51:0],
33'd0 } >>
NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2822 ;
assign x__h84397 =
{ requestR_BITS_191_TO_128__q1[63] ?
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d2872 :
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d2861,
3'd0,
(requestR_BITS_191_TO_128__q1[62:52] != 11'd2047 ||
requestR_BITS_191_TO_128__q1[51:0] == 52'd0) &&
(requestR_BITS_191_TO_128__q1[62:52] != 11'd2047 ||
requestR_BITS_191_TO_128__q1[51:0] != 52'd0) &&
NOT_IF_requestR_3_BIT_214_4_THEN_requestR_3_BI_ETC___d2866 } ;
assign x__h84681 =
{ requestR[191:128] != 64'd0 &&
(NOT_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_ETC___d2887 ?
requestR_BITS_191_TO_128__q1[63] :
IF_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_2_ETC___d2937),
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2996,
(requestR[191:128] == 64'd0 ||
NOT_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_ETC___d2887) ?
52'd0 :
_theResult___snd_fst_sfd__h97197 } ;
assign x__h96466 =
_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d2882 +
12'd1023 ;
assign x__h97358 =
{ 2'd0,
requestR[191:128] != 64'd0 &&
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3045,
requestR[191:128] != 64'd0 &&
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3048,
requestR[191:128] != 64'd0 &&
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3057 } ;
assign x__h97683 =
{ 1'd0,
(requestR[191:128] == 64'd0) ?
11'd0 :
_theResult___snd_fst_exp__h109725,
(requestR[191:128] == 64'd0 ||
NOT_IF_requestR_3_BIT_214_4_THEN_requestR_3_BI_ETC___d3156) ?
52'd0 :
_theResult___snd_fst_sfd__h109720 } ;
always@(requestR or requestR_BITS_191_TO_128__q1)
begin
case (requestR[194:192])
3'h1: CASE_requestR_BITS_194_TO_192_0x1_254_0x2_IF_r_ETC__q4 = 8'd254;
3'h2:
CASE_requestR_BITS_194_TO_192_0x1_254_0x2_IF_r_ETC__q4 =
requestR_BITS_191_TO_128__q1[63] ? 8'd255 : 8'd254;
3'h3:
CASE_requestR_BITS_194_TO_192_0x1_254_0x2_IF_r_ETC__q4 =
requestR_BITS_191_TO_128__q1[63] ? 8'd254 : 8'd255;
default: CASE_requestR_BITS_194_TO_192_0x1_254_0x2_IF_r_ETC__q4 = 8'd0;
endcase
end
always@(requestR or requestR_BITS_191_TO_128__q1)
begin
case (requestR[194:192])
3'h1:
CASE_requestR_BITS_194_TO_192_0x1_8388607_0x2__ETC__q5 =
23'd8388607;
3'h2:
CASE_requestR_BITS_194_TO_192_0x1_8388607_0x2__ETC__q5 =
requestR_BITS_191_TO_128__q1[63] ? 23'd0 : 23'd8388607;
3'h3:
CASE_requestR_BITS_194_TO_192_0x1_8388607_0x2__ETC__q5 =
requestR_BITS_191_TO_128__q1[63] ? 23'd8388607 : 23'd0;
default: CASE_requestR_BITS_194_TO_192_0x1_8388607_0x2__ETC__q5 = 23'd0;
endcase
end
always@(requestR or requestR_BITS_191_TO_128__q1)
begin
case (requestR[194:192])
3'h1: CASE_requestR_BITS_194_TO_192_0x1_2046_0x2_IF__ETC__q6 = 11'd2046;
3'h2:
CASE_requestR_BITS_194_TO_192_0x1_2046_0x2_IF__ETC__q6 =
(requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31]) ?
11'd2047 :
11'd2046;
3'h3:
CASE_requestR_BITS_194_TO_192_0x1_2046_0x2_IF__ETC__q6 =
(requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31]) ?
11'd2046 :
11'd2047;
default: CASE_requestR_BITS_194_TO_192_0x1_2046_0x2_IF__ETC__q6 = 11'd0;
endcase
end
always@(requestR or requestR_BITS_191_TO_128__q1)
begin
case (requestR[194:192])
3'h1:
CASE_requestR_BITS_194_TO_192_0x1_450359962737_ETC__q7 =
52'hFFFFFFFFFFFFF;
3'h2:
CASE_requestR_BITS_194_TO_192_0x1_450359962737_ETC__q7 =
(requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31]) ?
52'd0 :
52'hFFFFFFFFFFFFF;
3'h3:
CASE_requestR_BITS_194_TO_192_0x1_450359962737_ETC__q7 =
(requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31]) ?
52'hFFFFFFFFFFFFF :
52'd0;
default: CASE_requestR_BITS_194_TO_192_0x1_450359962737_ETC__q7 = 52'd0;
endcase
end
always@(requestR)
begin
case (requestR[194:192])
3'h0:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d61 =
requestR[194:192];
3'h1: IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d61 = 3'd4;
3'h2: IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d61 = 3'd3;
3'h3: IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d61 = 3'd2;
3'h4: IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d61 = 3'd1;
default: IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d61 =
3'd0;
endcase
end
always@(guard__h15015 or requestR_BITS_191_TO_128__q1)
begin
case (guard__h15015)
2'b0, 2'b01, 2'b10:
CASE_guard5015_0b0_requestR_BITS_191_TO_128_BI_ETC__q13 =
requestR_BITS_191_TO_128__q1[63];
2'd3:
CASE_guard5015_0b0_requestR_BITS_191_TO_128_BI_ETC__q13 =
guard__h15015 == 2'b11 && requestR_BITS_191_TO_128__q1[63];
endcase
end
always@(requestR or requestR_BITS_191_TO_128__q1 or guard__h15015)
begin
case (requestR[194:192])
3'h2, 3'h3:
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q14 =
requestR_BITS_191_TO_128__q1[63];
3'h4:
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q14 =
(guard__h15015 == 2'b0) ?
requestR_BITS_191_TO_128__q1[63] :
(guard__h15015 == 2'b01 || guard__h15015 == 2'b10 ||
guard__h15015 == 2'b11) &&
requestR_BITS_191_TO_128__q1[63];
default: CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q14 =
requestR[194:192] == 3'h1 &&
requestR_BITS_191_TO_128__q1[63];
endcase
end
always@(guard__h15545 or requestR_BITS_191_TO_128__q1)
begin
case (guard__h15545)
2'b0, 2'b01, 2'b10:
CASE_guard5545_0b0_requestR_BITS_191_TO_128_BI_ETC__q15 =
requestR_BITS_191_TO_128__q1[63];
2'd3:
CASE_guard5545_0b0_requestR_BITS_191_TO_128_BI_ETC__q15 =
guard__h15545 == 2'b11 && requestR_BITS_191_TO_128__q1[63];
endcase
end
always@(requestR or requestR_BITS_191_TO_128__q1 or guard__h15545)
begin
case (requestR[194:192])
3'h2, 3'h3:
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q16 =
requestR_BITS_191_TO_128__q1[63];
3'h4:
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q16 =
(guard__h15545 == 2'b0) ?
requestR_BITS_191_TO_128__q1[63] :
(guard__h15545 == 2'b01 || guard__h15545 == 2'b10 ||
guard__h15545 == 2'b11) &&
requestR_BITS_191_TO_128__q1[63];
default: CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q16 =
requestR[194:192] == 3'h1 &&
requestR_BITS_191_TO_128__q1[63];
endcase
end
always@(guard__h15015 or _theResult___exp__h15431)
begin
case (guard__h15015)
2'b0: CASE_guard5015_0b0_0_0b1_theResult___exp5431_0_ETC__q17 = 8'd0;
2'b01, 2'b10, 2'b11:
CASE_guard5015_0b0_0_0b1_theResult___exp5431_0_ETC__q17 =
_theResult___exp__h15431;
endcase
end
always@(requestR or
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d533 or
guard__h15015 or
requestR_BITS_191_TO_128__q1 or
_theResult___exp__h15431 or
CASE_guard5015_0b0_0_0b1_theResult___exp5431_0_ETC__q17)
begin
case (requestR[194:192])
3'h2:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d536 =
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d533;
3'h3:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d536 =
(guard__h15015 == 2'b0 || requestR_BITS_191_TO_128__q1[63]) ?
8'd0 :
_theResult___exp__h15431;
3'h4:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d536 =
CASE_guard5015_0b0_0_0b1_theResult___exp5431_0_ETC__q17;
default: IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d536 =
8'd0;
endcase
end
always@(guard__h15015 or out_exp__h15434 or _theResult___exp__h15431)
begin
case (guard__h15015)
2'b0, 2'b01:
CASE_guard5015_0b0_0_0b1_0_0b10_out_exp5434_0b_ETC__q18 = 8'd0;
2'b10:
CASE_guard5015_0b0_0_0b1_0_0b10_out_exp5434_0b_ETC__q18 =
out_exp__h15434;
2'b11:
CASE_guard5015_0b0_0_0b1_0_0b10_out_exp5434_0b_ETC__q18 =
_theResult___exp__h15431;
endcase
end
always@(guard__h15545 or x__h15560 or _theResult___exp__h15984)
begin
case (guard__h15545)
2'b0:
CASE_guard5545_0b0_x5560_BITS_7_TO_0_0b1_theRe_ETC__q19 =
x__h15560[7:0];
2'b01, 2'b10, 2'b11:
CASE_guard5545_0b0_x5560_BITS_7_TO_0_0b1_theRe_ETC__q19 =
_theResult___exp__h15984;
endcase
end
always@(requestR or
x__h15560 or
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d561 or
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d559 or
CASE_guard5545_0b0_x5560_BITS_7_TO_0_0b1_theRe_ETC__q19)
begin
case (requestR[194:192])
3'h1:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d565 =
x__h15560[7:0];
3'h2:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d565 =
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d561;
3'h3:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d565 =
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d559;
3'h4:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d565 =
CASE_guard5545_0b0_x5560_BITS_7_TO_0_0b1_theRe_ETC__q19;
default: IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d565 =
8'd0;
endcase
end
always@(guard__h15545 or
x__h15560 or out_exp__h15987 or _theResult___exp__h15984)
begin
case (guard__h15545)
2'b0, 2'b01:
CASE_guard5545_0b0_x5560_BITS_7_TO_0_0b1_x5560_ETC__q20 =
x__h15560[7:0];
2'b10:
CASE_guard5545_0b0_x5560_BITS_7_TO_0_0b1_x5560_ETC__q20 =
out_exp__h15987;
2'b11:
CASE_guard5545_0b0_x5560_BITS_7_TO_0_0b1_x5560_ETC__q20 =
_theResult___exp__h15984;
endcase
end
always@(guard__h15015 or sfd___3__h15005 or _theResult___sfd__h15432)
begin
case (guard__h15015)
2'b0:
CASE_guard5015_0b0_sfd___35005_BITS_63_TO_41_0_ETC__q21 =
sfd___3__h15005[63:41];
2'b01, 2'b10, 2'b11:
CASE_guard5015_0b0_sfd___35005_BITS_63_TO_41_0_ETC__q21 =
_theResult___sfd__h15432;
endcase
end
always@(requestR or
sfd___3__h15005 or
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d584 or
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d582 or
CASE_guard5015_0b0_sfd___35005_BITS_63_TO_41_0_ETC__q21)
begin
case (requestR[194:192])
3'h1:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d588 =
sfd___3__h15005[63:41];
3'h2:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d588 =
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d584;
3'h3:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d588 =
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d582;
3'h4:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d588 =
CASE_guard5015_0b0_sfd___35005_BITS_63_TO_41_0_ETC__q21;
default: IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d588 =
23'd0;
endcase
end
always@(guard__h15015 or
sfd___3__h15005 or out_sfd__h15435 or _theResult___sfd__h15432)
begin
case (guard__h15015)
2'b0, 2'b01:
CASE_guard5015_0b0_sfd___35005_BITS_63_TO_41_0_ETC__q22 =
sfd___3__h15005[63:41];
2'b10:
CASE_guard5015_0b0_sfd___35005_BITS_63_TO_41_0_ETC__q22 =
out_sfd__h15435;
2'b11:
CASE_guard5015_0b0_sfd___35005_BITS_63_TO_41_0_ETC__q22 =
_theResult___sfd__h15432;
endcase
end
always@(guard__h15545 or sfd___3__h15005 or _theResult___sfd__h15985)
begin
case (guard__h15545)
2'b0:
CASE_guard5545_0b0_sfd___35005_BITS_62_TO_40_0_ETC__q23 =
sfd___3__h15005[62:40];
2'b01, 2'b10, 2'b11:
CASE_guard5545_0b0_sfd___35005_BITS_62_TO_40_0_ETC__q23 =
_theResult___sfd__h15985;
endcase
end
always@(requestR or
sfd___3__h15005 or
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d602 or
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d600 or
CASE_guard5545_0b0_sfd___35005_BITS_62_TO_40_0_ETC__q23)
begin
case (requestR[194:192])
3'h1:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d606 =
sfd___3__h15005[62:40];
3'h2:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d606 =
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d602;
3'h3:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d606 =
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d600;
3'h4:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d606 =
CASE_guard5545_0b0_sfd___35005_BITS_62_TO_40_0_ETC__q23;
default: IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d606 =
23'd0;
endcase
end
always@(guard__h15545 or
sfd___3__h15005 or out_sfd__h15988 or _theResult___sfd__h15985)
begin
case (guard__h15545)
2'b0, 2'b01:
CASE_guard5545_0b0_sfd___35005_BITS_62_TO_40_0_ETC__q24 =
sfd___3__h15005[62:40];
2'b10:
CASE_guard5545_0b0_sfd___35005_BITS_62_TO_40_0_ETC__q24 =
out_sfd__h15988;
2'b11:
CASE_guard5545_0b0_sfd___35005_BITS_62_TO_40_0_ETC__q24 =
_theResult___sfd__h15985;
endcase
end
always@(guard__h27296 or out_exp__h27712 or _theResult___exp__h27709)
begin
case (guard__h27296)
2'b0, 2'b01:
CASE_guard7296_0b0_0_0b1_0_0b10_out_exp7712_0b_ETC__q29 = 8'd0;
2'b10:
CASE_guard7296_0b0_0_0b1_0_0b10_out_exp7712_0b_ETC__q29 =
out_exp__h27712;
2'b11:
CASE_guard7296_0b0_0_0b1_0_0b10_out_exp7712_0b_ETC__q29 =
_theResult___exp__h27709;
endcase
end
always@(guard__h27296 or _theResult___exp__h27709)
begin
case (guard__h27296)
2'b0: CASE_guard7296_0b0_0_0b1_theResult___exp7709_0_ETC__q30 = 8'd0;
2'b01, 2'b10, 2'b11:
CASE_guard7296_0b0_0_0b1_theResult___exp7709_0_ETC__q30 =
_theResult___exp__h27709;
endcase
end
always@(requestR or
guard__h27296 or
_theResult___exp__h27709 or
CASE_guard7296_0b0_0_0b1_theResult___exp7709_0_ETC__q30)
begin
case (requestR[194:192])
3'h3:
CASE_requestR_BITS_194_TO_192_0x3_IF_guard7296_ETC__q31 =
(guard__h27296 == 2'b0) ? 8'd0 : _theResult___exp__h27709;
3'h4:
CASE_requestR_BITS_194_TO_192_0x3_IF_guard7296_ETC__q31 =
CASE_guard7296_0b0_0_0b1_theResult___exp7709_0_ETC__q30;
default: CASE_requestR_BITS_194_TO_192_0x3_IF_guard7296_ETC__q31 = 8'd0;
endcase
end
always@(guard__h108246 or out_exp__h108865 or _theResult___exp__h108862)
begin
case (guard__h108246)
2'b0, 2'b01:
CASE_guard08246_0b0_0_0b1_0_0b10_out_exp08865__ETC__q32 = 11'd0;
2'b10:
CASE_guard08246_0b0_0_0b1_0_0b10_out_exp08865__ETC__q32 =
out_exp__h108865;
2'b11:
CASE_guard08246_0b0_0_0b1_0_0b10_out_exp08865__ETC__q32 =
_theResult___exp__h108862;
endcase
end
always@(guard__h108246 or _theResult___exp__h108862)
begin
case (guard__h108246)
2'b0: CASE_guard08246_0b0_0_0b1_theResult___exp08862_ETC__q33 = 11'd0;
2'b01, 2'b10, 2'b11:
CASE_guard08246_0b0_0_0b1_theResult___exp08862_ETC__q33 =
_theResult___exp__h108862;
endcase
end
always@(requestR or
guard__h108246 or
_theResult___exp__h108862 or
CASE_guard08246_0b0_0_0b1_theResult___exp08862_ETC__q33)
begin
case (requestR[194:192])
3'h3:
CASE_requestR_BITS_194_TO_192_0x3_IF_guard0824_ETC__q34 =
(guard__h108246 == 2'b0) ? 11'd0 : _theResult___exp__h108862;
3'h4:
CASE_requestR_BITS_194_TO_192_0x3_IF_guard0824_ETC__q34 =
CASE_guard08246_0b0_0_0b1_theResult___exp08862_ETC__q33;
default: CASE_requestR_BITS_194_TO_192_0x3_IF_guard0824_ETC__q34 =
11'd0;
endcase
end
always@(guard__h27822 or x__h27837 or _theResult___exp__h28261)
begin
case (guard__h27822)
2'b0:
CASE_guard7822_0b0_x7837_BITS_7_TO_0_0b1_theRe_ETC__q35 =
x__h27837[7:0];
2'b01, 2'b10, 2'b11:
CASE_guard7822_0b0_x7837_BITS_7_TO_0_0b1_theRe_ETC__q35 =
_theResult___exp__h28261;
endcase
end
always@(requestR or
x__h27837 or
guard__h27822 or
_theResult___exp__h28261 or
CASE_guard7822_0b0_x7837_BITS_7_TO_0_0b1_theRe_ETC__q35)
begin
case (requestR[194:192])
3'h1, 3'h2:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1050 =
x__h27837[7:0];
3'h3:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1050 =
(guard__h27822 == 2'b0) ?
x__h27837[7:0] :
_theResult___exp__h28261;
3'h4:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1050 =
CASE_guard7822_0b0_x7837_BITS_7_TO_0_0b1_theRe_ETC__q35;
default: IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1050 =
8'd0;
endcase
end
always@(guard__h27822 or
x__h27837 or out_exp__h28264 or _theResult___exp__h28261)
begin
case (guard__h27822)
2'b0, 2'b01:
CASE_guard7822_0b0_x7837_BITS_7_TO_0_0b1_x7837_ETC__q36 =
x__h27837[7:0];
2'b10:
CASE_guard7822_0b0_x7837_BITS_7_TO_0_0b1_x7837_ETC__q36 =
out_exp__h28264;
2'b11:
CASE_guard7822_0b0_x7837_BITS_7_TO_0_0b1_x7837_ETC__q36 =
_theResult___exp__h28261;
endcase
end
always@(guard__h27822 or sfd___3__h27286 or _theResult___sfd__h28262)
begin
case (guard__h27822)
2'b0:
CASE_guard7822_0b0_sfd___37286_BITS_62_TO_40_0_ETC__q37 =
sfd___3__h27286[62:40];
2'b01, 2'b10, 2'b11:
CASE_guard7822_0b0_sfd___37286_BITS_62_TO_40_0_ETC__q37 =
_theResult___sfd__h28262;
endcase
end
always@(requestR or
sfd___3__h27286 or
guard__h27822 or
_theResult___sfd__h28262 or
CASE_guard7822_0b0_sfd___37286_BITS_62_TO_40_0_ETC__q37)
begin
case (requestR[194:192])
3'h1, 3'h2:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1088 =
sfd___3__h27286[62:40];
3'h3:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1088 =
(guard__h27822 == 2'b0) ?
sfd___3__h27286[62:40] :
_theResult___sfd__h28262;
3'h4:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1088 =
CASE_guard7822_0b0_sfd___37286_BITS_62_TO_40_0_ETC__q37;
default: IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1088 =
23'd0;
endcase
end
always@(guard__h27822 or
sfd___3__h27286 or out_sfd__h28265 or _theResult___sfd__h28262)
begin
case (guard__h27822)
2'b0, 2'b01:
CASE_guard7822_0b0_sfd___37286_BITS_62_TO_40_0_ETC__q38 =
sfd___3__h27286[62:40];
2'b10:
CASE_guard7822_0b0_sfd___37286_BITS_62_TO_40_0_ETC__q38 =
out_sfd__h28265;
2'b11:
CASE_guard7822_0b0_sfd___37286_BITS_62_TO_40_0_ETC__q38 =
_theResult___sfd__h28262;
endcase
end
always@(guard__h27296 or sfd___3__h27286 or _theResult___sfd__h27710)
begin
case (guard__h27296)
2'b0:
CASE_guard7296_0b0_sfd___37286_BITS_63_TO_41_0_ETC__q39 =
sfd___3__h27286[63:41];
2'b01, 2'b10, 2'b11:
CASE_guard7296_0b0_sfd___37286_BITS_63_TO_41_0_ETC__q39 =
_theResult___sfd__h27710;
endcase
end
always@(requestR or
sfd___3__h27286 or
guard__h27296 or
_theResult___sfd__h27710 or
CASE_guard7296_0b0_sfd___37286_BITS_63_TO_41_0_ETC__q39)
begin
case (requestR[194:192])
3'h1, 3'h2:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1073 =
sfd___3__h27286[63:41];
3'h3:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1073 =
(guard__h27296 == 2'b0) ?
sfd___3__h27286[63:41] :
_theResult___sfd__h27710;
3'h4:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1073 =
CASE_guard7296_0b0_sfd___37286_BITS_63_TO_41_0_ETC__q39;
default: IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1073 =
23'd0;
endcase
end
always@(guard__h27296 or
sfd___3__h27286 or out_sfd__h27713 or _theResult___sfd__h27710)
begin
case (guard__h27296)
2'b0, 2'b01:
CASE_guard7296_0b0_sfd___37286_BITS_63_TO_41_0_ETC__q40 =
sfd___3__h27286[63:41];
2'b10:
CASE_guard7296_0b0_sfd___37286_BITS_63_TO_41_0_ETC__q40 =
out_sfd__h27713;
2'b11:
CASE_guard7296_0b0_sfd___37286_BITS_63_TO_41_0_ETC__q40 =
_theResult___sfd__h27710;
endcase
end
always@(guard__h34468 or _theResult___exp__h34881)
begin
case (guard__h34468)
2'b0: CASE_guard4468_0b0_0_0b1_theResult___exp4881_0_ETC__q43 = 8'd0;
2'b01, 2'b10, 2'b11:
CASE_guard4468_0b0_0_0b1_theResult___exp4881_0_ETC__q43 =
_theResult___exp__h34881;
endcase
end
always@(requestR or
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d1401 or
guard__h34468 or
requestR_BITS_191_TO_128__q1 or
_theResult___exp__h34881 or
CASE_guard4468_0b0_0_0b1_theResult___exp4881_0_ETC__q43)
begin
case (requestR[194:192])
3'h2:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1404 =
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d1401;
3'h3:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1404 =
(guard__h34468 == 2'b0 || requestR_BITS_191_TO_128__q1[31]) ?
8'd0 :
_theResult___exp__h34881;
3'h4:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1404 =
CASE_guard4468_0b0_0_0b1_theResult___exp4881_0_ETC__q43;
default: IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1404 =
8'd0;
endcase
end
always@(guard__h34468 or out_exp__h34884 or _theResult___exp__h34881)
begin
case (guard__h34468)
2'b0, 2'b01:
CASE_guard4468_0b0_0_0b1_0_0b10_out_exp4884_0b_ETC__q44 = 8'd0;
2'b10:
CASE_guard4468_0b0_0_0b1_0_0b10_out_exp4884_0b_ETC__q44 =
out_exp__h34884;
2'b11:
CASE_guard4468_0b0_0_0b1_0_0b10_out_exp4884_0b_ETC__q44 =
_theResult___exp__h34881;
endcase
end
always@(guard__h34468 or requestR_BITS_191_TO_128__q1)
begin
case (guard__h34468)
2'b0, 2'b01, 2'b10:
CASE_guard4468_0b0_requestR_BITS_191_TO_128_BI_ETC__q45 =
requestR_BITS_191_TO_128__q1[31];
2'd3:
CASE_guard4468_0b0_requestR_BITS_191_TO_128_BI_ETC__q45 =
guard__h34468 == 2'b11 && requestR_BITS_191_TO_128__q1[31];
endcase
end
always@(requestR or requestR_BITS_191_TO_128__q1 or guard__h34468)
begin
case (requestR[194:192])
3'h2, 3'h3:
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q46 =
requestR_BITS_191_TO_128__q1[31];
3'h4:
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q46 =
(guard__h34468 == 2'b0) ?
requestR_BITS_191_TO_128__q1[31] :
(guard__h34468 == 2'b01 || guard__h34468 == 2'b10 ||
guard__h34468 == 2'b11) &&
requestR_BITS_191_TO_128__q1[31];
default: CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q46 =
requestR[194:192] == 3'h1 &&
requestR_BITS_191_TO_128__q1[31];
endcase
end
always@(guard__h34995 or requestR_BITS_191_TO_128__q1)
begin
case (guard__h34995)
2'b0, 2'b01, 2'b10:
CASE_guard4995_0b0_requestR_BITS_191_TO_128_BI_ETC__q47 =
requestR_BITS_191_TO_128__q1[31];
2'd3:
CASE_guard4995_0b0_requestR_BITS_191_TO_128_BI_ETC__q47 =
guard__h34995 == 2'b11 && requestR_BITS_191_TO_128__q1[31];
endcase
end
always@(requestR or requestR_BITS_191_TO_128__q1 or guard__h34995)
begin
case (requestR[194:192])
3'h2, 3'h3:
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q48 =
requestR_BITS_191_TO_128__q1[31];
3'h4:
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q48 =
(guard__h34995 == 2'b0) ?
requestR_BITS_191_TO_128__q1[31] :
(guard__h34995 == 2'b01 || guard__h34995 == 2'b10 ||
guard__h34995 == 2'b11) &&
requestR_BITS_191_TO_128__q1[31];
default: CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q48 =
requestR[194:192] == 3'h1 &&
requestR_BITS_191_TO_128__q1[31];
endcase
end
always@(guard__h34995 or x__h35010 or _theResult___exp__h35434)
begin
case (guard__h34995)
2'b0:
CASE_guard4995_0b0_x5010_BITS_7_TO_0_0b1_theRe_ETC__q49 =
x__h35010[7:0];
2'b01, 2'b10, 2'b11:
CASE_guard4995_0b0_x5010_BITS_7_TO_0_0b1_theRe_ETC__q49 =
_theResult___exp__h35434;
endcase
end
always@(requestR or
x__h35010 or
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d1429 or
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d1427 or
CASE_guard4995_0b0_x5010_BITS_7_TO_0_0b1_theRe_ETC__q49)
begin
case (requestR[194:192])
3'h1:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1433 =
x__h35010[7:0];
3'h2:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1433 =
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d1429;
3'h3:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1433 =
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d1427;
3'h4:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1433 =
CASE_guard4995_0b0_x5010_BITS_7_TO_0_0b1_theRe_ETC__q49;
default: IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1433 =
8'd0;
endcase
end
always@(guard__h34995 or
x__h35010 or out_exp__h35437 or _theResult___exp__h35434)
begin
case (guard__h34995)
2'b0, 2'b01:
CASE_guard4995_0b0_x5010_BITS_7_TO_0_0b1_x5010_ETC__q50 =
x__h35010[7:0];
2'b10:
CASE_guard4995_0b0_x5010_BITS_7_TO_0_0b1_x5010_ETC__q50 =
out_exp__h35437;
2'b11:
CASE_guard4995_0b0_x5010_BITS_7_TO_0_0b1_x5010_ETC__q50 =
_theResult___exp__h35434;
endcase
end
always@(guard__h34468 or sfd___3__h34458 or _theResult___sfd__h34882)
begin
case (guard__h34468)
2'b0:
CASE_guard4468_0b0_sfd___34458_BITS_31_TO_9_0b_ETC__q51 =
sfd___3__h34458[31:9];
2'b01, 2'b10, 2'b11:
CASE_guard4468_0b0_sfd___34458_BITS_31_TO_9_0b_ETC__q51 =
_theResult___sfd__h34882;
endcase
end
always@(requestR or
sfd___3__h34458 or
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d1452 or
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d1450 or
CASE_guard4468_0b0_sfd___34458_BITS_31_TO_9_0b_ETC__q51)
begin
case (requestR[194:192])
3'h1:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1456 =
sfd___3__h34458[31:9];
3'h2:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1456 =
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d1452;
3'h3:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1456 =
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d1450;
3'h4:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1456 =
CASE_guard4468_0b0_sfd___34458_BITS_31_TO_9_0b_ETC__q51;
default: IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1456 =
23'd0;
endcase
end
always@(guard__h34468 or
sfd___3__h34458 or out_sfd__h34885 or _theResult___sfd__h34882)
begin
case (guard__h34468)
2'b0, 2'b01:
CASE_guard4468_0b0_sfd___34458_BITS_31_TO_9_0b_ETC__q52 =
sfd___3__h34458[31:9];
2'b10:
CASE_guard4468_0b0_sfd___34458_BITS_31_TO_9_0b_ETC__q52 =
out_sfd__h34885;
2'b11:
CASE_guard4468_0b0_sfd___34458_BITS_31_TO_9_0b_ETC__q52 =
_theResult___sfd__h34882;
endcase
end
always@(guard__h34995 or sfd___3__h34458 or _theResult___sfd__h35435)
begin
case (guard__h34995)
2'b0:
CASE_guard4995_0b0_sfd___34458_BITS_30_TO_8_0b_ETC__q53 =
sfd___3__h34458[30:8];
2'b01, 2'b10, 2'b11:
CASE_guard4995_0b0_sfd___34458_BITS_30_TO_8_0b_ETC__q53 =
_theResult___sfd__h35435;
endcase
end
always@(requestR or
sfd___3__h34458 or
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d1470 or
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d1468 or
CASE_guard4995_0b0_sfd___34458_BITS_30_TO_8_0b_ETC__q53)
begin
case (requestR[194:192])
3'h1:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1474 =
sfd___3__h34458[30:8];
3'h2:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1474 =
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d1470;
3'h3:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1474 =
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d1468;
3'h4:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1474 =
CASE_guard4995_0b0_sfd___34458_BITS_30_TO_8_0b_ETC__q53;
default: IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1474 =
23'd0;
endcase
end
always@(guard__h34995 or
sfd___3__h34458 or out_sfd__h35438 or _theResult___sfd__h35435)
begin
case (guard__h34995)
2'b0, 2'b01:
CASE_guard4995_0b0_sfd___34458_BITS_30_TO_8_0b_ETC__q54 =
sfd___3__h34458[30:8];
2'b10:
CASE_guard4995_0b0_sfd___34458_BITS_30_TO_8_0b_ETC__q54 =
out_sfd__h35438;
2'b11:
CASE_guard4995_0b0_sfd___34458_BITS_30_TO_8_0b_ETC__q54 =
_theResult___sfd__h35435;
endcase
end
always@(guard__h41384 or out_exp__h41800 or _theResult___exp__h41797)
begin
case (guard__h41384)
2'b0, 2'b01:
CASE_guard1384_0b0_0_0b1_0_0b10_out_exp1800_0b_ETC__q57 = 8'd0;
2'b10:
CASE_guard1384_0b0_0_0b1_0_0b10_out_exp1800_0b_ETC__q57 =
out_exp__h41800;
2'b11:
CASE_guard1384_0b0_0_0b1_0_0b10_out_exp1800_0b_ETC__q57 =
_theResult___exp__h41797;
endcase
end
always@(guard__h41384 or _theResult___exp__h41797)
begin
case (guard__h41384)
2'b0: CASE_guard1384_0b0_0_0b1_theResult___exp1797_0_ETC__q58 = 8'd0;
2'b01, 2'b10, 2'b11:
CASE_guard1384_0b0_0_0b1_theResult___exp1797_0_ETC__q58 =
_theResult___exp__h41797;
endcase
end
always@(requestR or
guard__h41384 or
_theResult___exp__h41797 or
CASE_guard1384_0b0_0_0b1_theResult___exp1797_0_ETC__q58)
begin
case (requestR[194:192])
3'h3:
CASE_requestR_BITS_194_TO_192_0x3_IF_guard1384_ETC__q59 =
(guard__h41384 == 2'b0) ? 8'd0 : _theResult___exp__h41797;
3'h4:
CASE_requestR_BITS_194_TO_192_0x3_IF_guard1384_ETC__q59 =
CASE_guard1384_0b0_0_0b1_theResult___exp1797_0_ETC__q58;
default: CASE_requestR_BITS_194_TO_192_0x3_IF_guard1384_ETC__q59 = 8'd0;
endcase
end
always@(guard__h41910 or x__h41925 or _theResult___exp__h42349)
begin
case (guard__h41910)
2'b0:
CASE_guard1910_0b0_x1925_BITS_7_TO_0_0b1_theRe_ETC__q60 =
x__h41925[7:0];
2'b01, 2'b10, 2'b11:
CASE_guard1910_0b0_x1925_BITS_7_TO_0_0b1_theRe_ETC__q60 =
_theResult___exp__h42349;
endcase
end
always@(requestR or
x__h41925 or
guard__h41910 or
_theResult___exp__h42349 or
CASE_guard1910_0b0_x1925_BITS_7_TO_0_0b1_theRe_ETC__q60)
begin
case (requestR[194:192])
3'h1, 3'h2:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1657 =
x__h41925[7:0];
3'h3:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1657 =
(guard__h41910 == 2'b0) ?
x__h41925[7:0] :
_theResult___exp__h42349;
3'h4:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1657 =
CASE_guard1910_0b0_x1925_BITS_7_TO_0_0b1_theRe_ETC__q60;
default: IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1657 =
8'd0;
endcase
end
always@(guard__h41910 or
x__h41925 or out_exp__h42352 or _theResult___exp__h42349)
begin
case (guard__h41910)
2'b0, 2'b01:
CASE_guard1910_0b0_x1925_BITS_7_TO_0_0b1_x1925_ETC__q61 =
x__h41925[7:0];
2'b10:
CASE_guard1910_0b0_x1925_BITS_7_TO_0_0b1_x1925_ETC__q61 =
out_exp__h42352;
2'b11:
CASE_guard1910_0b0_x1925_BITS_7_TO_0_0b1_x1925_ETC__q61 =
_theResult___exp__h42349;
endcase
end
always@(guard__h41910 or sfd___3__h41374 or _theResult___sfd__h42350)
begin
case (guard__h41910)
2'b0:
CASE_guard1910_0b0_sfd___31374_BITS_30_TO_8_0b_ETC__q62 =
sfd___3__h41374[30:8];
2'b01, 2'b10, 2'b11:
CASE_guard1910_0b0_sfd___31374_BITS_30_TO_8_0b_ETC__q62 =
_theResult___sfd__h42350;
endcase
end
always@(requestR or
sfd___3__h41374 or
guard__h41910 or
_theResult___sfd__h42350 or
CASE_guard1910_0b0_sfd___31374_BITS_30_TO_8_0b_ETC__q62)
begin
case (requestR[194:192])
3'h1, 3'h2:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1695 =
sfd___3__h41374[30:8];
3'h3:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1695 =
(guard__h41910 == 2'b0) ?
sfd___3__h41374[30:8] :
_theResult___sfd__h42350;
3'h4:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1695 =
CASE_guard1910_0b0_sfd___31374_BITS_30_TO_8_0b_ETC__q62;
default: IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1695 =
23'd0;
endcase
end
always@(guard__h41910 or
sfd___3__h41374 or out_sfd__h42353 or _theResult___sfd__h42350)
begin
case (guard__h41910)
2'b0, 2'b01:
CASE_guard1910_0b0_sfd___31374_BITS_30_TO_8_0b_ETC__q63 =
sfd___3__h41374[30:8];
2'b10:
CASE_guard1910_0b0_sfd___31374_BITS_30_TO_8_0b_ETC__q63 =
out_sfd__h42353;
2'b11:
CASE_guard1910_0b0_sfd___31374_BITS_30_TO_8_0b_ETC__q63 =
_theResult___sfd__h42350;
endcase
end
always@(guard__h41384 or sfd___3__h41374 or _theResult___sfd__h41798)
begin
case (guard__h41384)
2'b0:
CASE_guard1384_0b0_sfd___31374_BITS_31_TO_9_0b_ETC__q64 =
sfd___3__h41374[31:9];
2'b01, 2'b10, 2'b11:
CASE_guard1384_0b0_sfd___31374_BITS_31_TO_9_0b_ETC__q64 =
_theResult___sfd__h41798;
endcase
end
always@(requestR or
sfd___3__h41374 or
guard__h41384 or
_theResult___sfd__h41798 or
CASE_guard1384_0b0_sfd___31374_BITS_31_TO_9_0b_ETC__q64)
begin
case (requestR[194:192])
3'h1, 3'h2:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1680 =
sfd___3__h41374[31:9];
3'h3:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1680 =
(guard__h41384 == 2'b0) ?
sfd___3__h41374[31:9] :
_theResult___sfd__h41798;
3'h4:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1680 =
CASE_guard1384_0b0_sfd___31374_BITS_31_TO_9_0b_ETC__q64;
default: IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1680 =
23'd0;
endcase
end
always@(guard__h41384 or
sfd___3__h41374 or out_sfd__h41801 or _theResult___sfd__h41798)
begin
case (guard__h41384)
2'b0, 2'b01:
CASE_guard1384_0b0_sfd___31374_BITS_31_TO_9_0b_ETC__q65 =
sfd___3__h41374[31:9];
2'b10:
CASE_guard1384_0b0_sfd___31374_BITS_31_TO_9_0b_ETC__q65 =
out_sfd__h41801;
2'b11:
CASE_guard1384_0b0_sfd___31374_BITS_31_TO_9_0b_ETC__q65 =
_theResult___sfd__h41798;
endcase
end
always@(guard__h69399 or requestR_BITS_191_TO_128__q1)
begin
case (guard__h69399)
2'b0, 2'b01, 2'b10:
CASE_guard9399_0b0_requestR_BITS_191_TO_128_BI_ETC__q72 =
requestR_BITS_191_TO_128__q1[31];
2'd3:
CASE_guard9399_0b0_requestR_BITS_191_TO_128_BI_ETC__q72 =
guard__h69399 == 2'b11 && requestR_BITS_191_TO_128__q1[31];
endcase
end
always@(requestR or requestR_BITS_191_TO_128__q1 or guard__h69399)
begin
case (requestR[194:192])
3'h2, 3'h3:
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q73 =
requestR_BITS_191_TO_128__q1[31];
3'h4:
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q73 =
(guard__h69399 == 2'b0) ?
requestR_BITS_191_TO_128__q1[31] :
(guard__h69399 == 2'b01 || guard__h69399 == 2'b10 ||
guard__h69399 == 2'b11) &&
requestR_BITS_191_TO_128__q1[31];
default: CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q73 =
requestR[194:192] == 3'h1 &&
requestR_BITS_191_TO_128__q1[31];
endcase
end
always@(guard__h70129 or requestR_BITS_191_TO_128__q1)
begin
case (guard__h70129)
2'b0, 2'b01, 2'b10:
CASE_guard0129_0b0_requestR_BITS_191_TO_128_BI_ETC__q74 =
requestR_BITS_191_TO_128__q1[31];
2'd3:
CASE_guard0129_0b0_requestR_BITS_191_TO_128_BI_ETC__q74 =
guard__h70129 == 2'b11 && requestR_BITS_191_TO_128__q1[31];
endcase
end
always@(requestR or requestR_BITS_191_TO_128__q1 or guard__h70129)
begin
case (requestR[194:192])
3'h2, 3'h3:
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q75 =
requestR_BITS_191_TO_128__q1[31];
3'h4:
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q75 =
(guard__h70129 == 2'b0) ?
requestR_BITS_191_TO_128__q1[31] :
(guard__h70129 == 2'b01 || guard__h70129 == 2'b10 ||
guard__h70129 == 2'b11) &&
requestR_BITS_191_TO_128__q1[31];
default: CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q75 =
requestR[194:192] == 3'h1 &&
requestR_BITS_191_TO_128__q1[31];
endcase
end
always@(guard__h70129 or x__h70144 or _theResult___exp__h70771)
begin
case (guard__h70129)
2'b0:
CASE_guard0129_0b0_x0144_BITS_10_TO_0_0b1_theR_ETC__q76 =
x__h70144[10:0];
2'b01, 2'b10, 2'b11:
CASE_guard0129_0b0_x0144_BITS_10_TO_0_0b1_theR_ETC__q76 =
_theResult___exp__h70771;
endcase
end
always@(requestR or
x__h70144 or
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2447 or
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2445 or
CASE_guard0129_0b0_x0144_BITS_10_TO_0_0b1_theR_ETC__q76)
begin
case (requestR[194:192])
3'h1:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2451 =
x__h70144[10:0];
3'h2:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2451 =
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2447;
3'h3:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2451 =
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2445;
3'h4:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2451 =
CASE_guard0129_0b0_x0144_BITS_10_TO_0_0b1_theR_ETC__q76;
default: IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2451 =
11'd0;
endcase
end
always@(guard__h70129 or
x__h70144 or out_exp__h70774 or _theResult___exp__h70771)
begin
case (guard__h70129)
2'b0, 2'b01:
CASE_guard0129_0b0_x0144_BITS_10_TO_0_0b1_x014_ETC__q77 =
x__h70144[10:0];
2'b10:
CASE_guard0129_0b0_x0144_BITS_10_TO_0_0b1_x014_ETC__q77 =
out_exp__h70774;
2'b11:
CASE_guard0129_0b0_x0144_BITS_10_TO_0_0b1_x014_ETC__q77 =
_theResult___exp__h70771;
endcase
end
always@(guard__h70129 or sfd___3__h69389 or _theResult___sfd__h70772)
begin
case (guard__h70129)
2'b0:
CASE_guard0129_0b0_sfd___39389_BITS_53_TO_2_0b_ETC__q78 =
sfd___3__h69389[53:2];
2'b01, 2'b10, 2'b11:
CASE_guard0129_0b0_sfd___39389_BITS_53_TO_2_0b_ETC__q78 =
_theResult___sfd__h70772;
endcase
end
always@(requestR or
sfd___3__h69389 or
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2488 or
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2486 or
CASE_guard0129_0b0_sfd___39389_BITS_53_TO_2_0b_ETC__q78)
begin
case (requestR[194:192])
3'h1:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2492 =
sfd___3__h69389[53:2];
3'h2:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2492 =
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2488;
3'h3:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2492 =
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2486;
3'h4:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2492 =
CASE_guard0129_0b0_sfd___39389_BITS_53_TO_2_0b_ETC__q78;
default: IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2492 =
52'd0;
endcase
end
always@(guard__h70129 or
sfd___3__h69389 or out_sfd__h70775 or _theResult___sfd__h70772)
begin
case (guard__h70129)
2'b0, 2'b01:
CASE_guard0129_0b0_sfd___39389_BITS_53_TO_2_0b_ETC__q79 =
sfd___3__h69389[53:2];
2'b10:
CASE_guard0129_0b0_sfd___39389_BITS_53_TO_2_0b_ETC__q79 =
out_sfd__h70775;
2'b11:
CASE_guard0129_0b0_sfd___39389_BITS_53_TO_2_0b_ETC__q79 =
_theResult___sfd__h70772;
endcase
end
always@(guard__h69399 or _theResult___exp__h70015)
begin
case (guard__h69399)
2'b0: CASE_guard9399_0b0_0_0b1_theResult___exp0015_0_ETC__q80 = 11'd0;
2'b01, 2'b10, 2'b11:
CASE_guard9399_0b0_0_0b1_theResult___exp0015_0_ETC__q80 =
_theResult___exp__h70015;
endcase
end
always@(requestR or
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2419 or
guard__h69399 or
requestR_BITS_191_TO_128__q1 or
_theResult___exp__h70015 or
CASE_guard9399_0b0_0_0b1_theResult___exp0015_0_ETC__q80)
begin
case (requestR[194:192])
3'h2:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2422 =
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2419;
3'h3:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2422 =
(guard__h69399 == 2'b0 || requestR_BITS_191_TO_128__q1[31]) ?
11'd0 :
_theResult___exp__h70015;
3'h4:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2422 =
CASE_guard9399_0b0_0_0b1_theResult___exp0015_0_ETC__q80;
default: IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2422 =
11'd0;
endcase
end
always@(guard__h69399 or out_exp__h70018 or _theResult___exp__h70015)
begin
case (guard__h69399)
2'b0, 2'b01:
CASE_guard9399_0b0_0_0b1_0_0b10_out_exp0018_0b_ETC__q81 = 11'd0;
2'b10:
CASE_guard9399_0b0_0_0b1_0_0b10_out_exp0018_0b_ETC__q81 =
out_exp__h70018;
2'b11:
CASE_guard9399_0b0_0_0b1_0_0b10_out_exp0018_0b_ETC__q81 =
_theResult___exp__h70015;
endcase
end
always@(guard__h69399 or sfd___3__h69389 or _theResult___sfd__h70016)
begin
case (guard__h69399)
2'b0:
CASE_guard9399_0b0_sfd___39389_BITS_54_TO_3_0b_ETC__q82 =
sfd___3__h69389[54:3];
2'b01, 2'b10, 2'b11:
CASE_guard9399_0b0_sfd___39389_BITS_54_TO_3_0b_ETC__q82 =
_theResult___sfd__h70016;
endcase
end
always@(requestR or
sfd___3__h69389 or
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2470 or
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2468 or
CASE_guard9399_0b0_sfd___39389_BITS_54_TO_3_0b_ETC__q82)
begin
case (requestR[194:192])
3'h1:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2474 =
sfd___3__h69389[54:3];
3'h2:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2474 =
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2470;
3'h3:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2474 =
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2468;
3'h4:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2474 =
CASE_guard9399_0b0_sfd___39389_BITS_54_TO_3_0b_ETC__q82;
default: IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2474 =
52'd0;
endcase
end
always@(guard__h69399 or
sfd___3__h69389 or out_sfd__h70019 or _theResult___sfd__h70016)
begin
case (guard__h69399)
2'b0, 2'b01:
CASE_guard9399_0b0_sfd___39389_BITS_54_TO_3_0b_ETC__q83 =
sfd___3__h69389[54:3];
2'b10:
CASE_guard9399_0b0_sfd___39389_BITS_54_TO_3_0b_ETC__q83 =
out_sfd__h70019;
2'b11:
CASE_guard9399_0b0_sfd___39389_BITS_54_TO_3_0b_ETC__q83 =
_theResult___sfd__h70016;
endcase
end
always@(guard__h80346 or out_exp__h80965 or _theResult___exp__h80962)
begin
case (guard__h80346)
2'b0, 2'b01:
CASE_guard0346_0b0_0_0b1_0_0b10_out_exp0965_0b_ETC__q86 = 11'd0;
2'b10:
CASE_guard0346_0b0_0_0b1_0_0b10_out_exp0965_0b_ETC__q86 =
out_exp__h80965;
2'b11:
CASE_guard0346_0b0_0_0b1_0_0b10_out_exp0965_0b_ETC__q86 =
_theResult___exp__h80962;
endcase
end
always@(guard__h80346 or _theResult___exp__h80962)
begin
case (guard__h80346)
2'b0: CASE_guard0346_0b0_0_0b1_theResult___exp0962_0_ETC__q87 = 11'd0;
2'b01, 2'b10, 2'b11:
CASE_guard0346_0b0_0_0b1_theResult___exp0962_0_ETC__q87 =
_theResult___exp__h80962;
endcase
end
always@(requestR or
guard__h80346 or
_theResult___exp__h80962 or
CASE_guard0346_0b0_0_0b1_theResult___exp0962_0_ETC__q87)
begin
case (requestR[194:192])
3'h3:
CASE_requestR_BITS_194_TO_192_0x3_IF_guard0346_ETC__q88 =
(guard__h80346 == 2'b0) ? 11'd0 : _theResult___exp__h80962;
3'h4:
CASE_requestR_BITS_194_TO_192_0x3_IF_guard0346_ETC__q88 =
CASE_guard0346_0b0_0_0b1_theResult___exp0962_0_ETC__q87;
default: CASE_requestR_BITS_194_TO_192_0x3_IF_guard0346_ETC__q88 =
11'd0;
endcase
end
always@(guard__h81075 or x__h81090 or _theResult___exp__h81717)
begin
case (guard__h81075)
2'b0:
CASE_guard1075_0b0_x1090_BITS_10_TO_0_0b1_theR_ETC__q89 =
x__h81090[10:0];
2'b01, 2'b10, 2'b11:
CASE_guard1075_0b0_x1090_BITS_10_TO_0_0b1_theR_ETC__q89 =
_theResult___exp__h81717;
endcase
end
always@(requestR or
x__h81090 or
guard__h81075 or
_theResult___exp__h81717 or
CASE_guard1075_0b0_x1090_BITS_10_TO_0_0b1_theR_ETC__q89)
begin
case (requestR[194:192])
3'h1, 3'h2:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2639 =
x__h81090[10:0];
3'h3:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2639 =
(guard__h81075 == 2'b0) ?
x__h81090[10:0] :
_theResult___exp__h81717;
3'h4:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2639 =
CASE_guard1075_0b0_x1090_BITS_10_TO_0_0b1_theR_ETC__q89;
default: IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2639 =
11'd0;
endcase
end
always@(guard__h81075 or
x__h81090 or out_exp__h81720 or _theResult___exp__h81717)
begin
case (guard__h81075)
2'b0, 2'b01:
CASE_guard1075_0b0_x1090_BITS_10_TO_0_0b1_x109_ETC__q90 =
x__h81090[10:0];
2'b10:
CASE_guard1075_0b0_x1090_BITS_10_TO_0_0b1_x109_ETC__q90 =
out_exp__h81720;
2'b11:
CASE_guard1075_0b0_x1090_BITS_10_TO_0_0b1_x109_ETC__q90 =
_theResult___exp__h81717;
endcase
end
always@(guard__h81075 or sfd___3__h80336 or _theResult___sfd__h81718)
begin
case (guard__h81075)
2'b0:
CASE_guard1075_0b0_sfd___30336_BITS_53_TO_2_0b_ETC__q91 =
sfd___3__h80336[53:2];
2'b01, 2'b10, 2'b11:
CASE_guard1075_0b0_sfd___30336_BITS_53_TO_2_0b_ETC__q91 =
_theResult___sfd__h81718;
endcase
end
always@(requestR or
sfd___3__h80336 or
guard__h81075 or
_theResult___sfd__h81718 or
CASE_guard1075_0b0_sfd___30336_BITS_53_TO_2_0b_ETC__q91)
begin
case (requestR[194:192])
3'h1, 3'h2:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2676 =
sfd___3__h80336[53:2];
3'h3:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2676 =
(guard__h81075 == 2'b0) ?
sfd___3__h80336[53:2] :
_theResult___sfd__h81718;
3'h4:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2676 =
CASE_guard1075_0b0_sfd___30336_BITS_53_TO_2_0b_ETC__q91;
default: IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2676 =
52'd0;
endcase
end
always@(guard__h81075 or
sfd___3__h80336 or out_sfd__h81721 or _theResult___sfd__h81718)
begin
case (guard__h81075)
2'b0, 2'b01:
CASE_guard1075_0b0_sfd___30336_BITS_53_TO_2_0b_ETC__q92 =
sfd___3__h80336[53:2];
2'b10:
CASE_guard1075_0b0_sfd___30336_BITS_53_TO_2_0b_ETC__q92 =
out_sfd__h81721;
2'b11:
CASE_guard1075_0b0_sfd___30336_BITS_53_TO_2_0b_ETC__q92 =
_theResult___sfd__h81718;
endcase
end
always@(guard__h80346 or sfd___3__h80336 or _theResult___sfd__h80963)
begin
case (guard__h80346)
2'b0:
CASE_guard0346_0b0_sfd___30336_BITS_54_TO_3_0b_ETC__q93 =
sfd___3__h80336[54:3];
2'b01, 2'b10, 2'b11:
CASE_guard0346_0b0_sfd___30336_BITS_54_TO_3_0b_ETC__q93 =
_theResult___sfd__h80963;
endcase
end
always@(requestR or
sfd___3__h80336 or
guard__h80346 or
_theResult___sfd__h80963 or
CASE_guard0346_0b0_sfd___30336_BITS_54_TO_3_0b_ETC__q93)
begin
case (requestR[194:192])
3'h1, 3'h2:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2661 =
sfd___3__h80336[54:3];
3'h3:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2661 =
(guard__h80346 == 2'b0) ?
sfd___3__h80336[54:3] :
_theResult___sfd__h80963;
3'h4:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2661 =
CASE_guard0346_0b0_sfd___30336_BITS_54_TO_3_0b_ETC__q93;
default: IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2661 =
52'd0;
endcase
end
always@(guard__h80346 or
sfd___3__h80336 or out_sfd__h80966 or _theResult___sfd__h80963)
begin
case (guard__h80346)
2'b0, 2'b01:
CASE_guard0346_0b0_sfd___30336_BITS_54_TO_3_0b_ETC__q94 =
sfd___3__h80336[54:3];
2'b10:
CASE_guard0346_0b0_sfd___30336_BITS_54_TO_3_0b_ETC__q94 =
out_sfd__h80966;
2'b11:
CASE_guard0346_0b0_sfd___30336_BITS_54_TO_3_0b_ETC__q94 =
_theResult___sfd__h80963;
endcase
end
always@(guard__h95721 or requestR_BITS_191_TO_128__q1)
begin
case (guard__h95721)
2'b0, 2'b01, 2'b10:
CASE_guard5721_0b0_requestR_BITS_191_TO_128_BI_ETC__q97 =
requestR_BITS_191_TO_128__q1[63];
2'd3:
CASE_guard5721_0b0_requestR_BITS_191_TO_128_BI_ETC__q97 =
guard__h95721 == 2'b11 && requestR_BITS_191_TO_128__q1[63];
endcase
end
always@(requestR or requestR_BITS_191_TO_128__q1 or guard__h95721)
begin
case (requestR[194:192])
3'h2, 3'h3:
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q98 =
requestR_BITS_191_TO_128__q1[63];
3'h4:
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q98 =
(guard__h95721 == 2'b0) ?
requestR_BITS_191_TO_128__q1[63] :
(guard__h95721 == 2'b01 || guard__h95721 == 2'b10 ||
guard__h95721 == 2'b11) &&
requestR_BITS_191_TO_128__q1[63];
default: CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q98 =
requestR[194:192] == 3'h1 &&
requestR_BITS_191_TO_128__q1[63];
endcase
end
always@(guard__h96451 or requestR_BITS_191_TO_128__q1)
begin
case (guard__h96451)
2'b0, 2'b01, 2'b10:
CASE_guard6451_0b0_requestR_BITS_191_TO_128_BI_ETC__q99 =
requestR_BITS_191_TO_128__q1[63];
2'd3:
CASE_guard6451_0b0_requestR_BITS_191_TO_128_BI_ETC__q99 =
guard__h96451 == 2'b11 && requestR_BITS_191_TO_128__q1[63];
endcase
end
always@(requestR or requestR_BITS_191_TO_128__q1 or guard__h96451)
begin
case (requestR[194:192])
3'h2, 3'h3:
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q100 =
requestR_BITS_191_TO_128__q1[63];
3'h4:
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q100 =
(guard__h96451 == 2'b0) ?
requestR_BITS_191_TO_128__q1[63] :
(guard__h96451 == 2'b01 || guard__h96451 == 2'b10 ||
guard__h96451 == 2'b11) &&
requestR_BITS_191_TO_128__q1[63];
default: CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q100 =
requestR[194:192] == 3'h1 &&
requestR_BITS_191_TO_128__q1[63];
endcase
end
always@(guard__h96451 or x__h96466 or _theResult___exp__h97093)
begin
case (guard__h96451)
2'b0:
CASE_guard6451_0b0_x6466_BITS_10_TO_0_0b1_theR_ETC__q101 =
x__h96466[10:0];
2'b01, 2'b10, 2'b11:
CASE_guard6451_0b0_x6466_BITS_10_TO_0_0b1_theR_ETC__q101 =
_theResult___exp__h97093;
endcase
end
always@(requestR or
x__h96466 or
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2986 or
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2984 or
CASE_guard6451_0b0_x6466_BITS_10_TO_0_0b1_theR_ETC__q101)
begin
case (requestR[194:192])
3'h1:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2990 =
x__h96466[10:0];
3'h2:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2990 =
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2986;
3'h3:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2990 =
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2984;
3'h4:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2990 =
CASE_guard6451_0b0_x6466_BITS_10_TO_0_0b1_theR_ETC__q101;
default: IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2990 =
11'd0;
endcase
end
always@(guard__h96451 or
x__h96466 or out_exp__h97096 or _theResult___exp__h97093)
begin
case (guard__h96451)
2'b0, 2'b01:
CASE_guard6451_0b0_x6466_BITS_10_TO_0_0b1_x646_ETC__q102 =
x__h96466[10:0];
2'b10:
CASE_guard6451_0b0_x6466_BITS_10_TO_0_0b1_x646_ETC__q102 =
out_exp__h97096;
2'b11:
CASE_guard6451_0b0_x6466_BITS_10_TO_0_0b1_x646_ETC__q102 =
_theResult___exp__h97093;
endcase
end
always@(guard__h96451 or sfd___3__h15005 or _theResult___sfd__h97094)
begin
case (guard__h96451)
2'b0:
CASE_guard6451_0b0_sfd___35005_BITS_62_TO_11_0_ETC__q103 =
sfd___3__h15005[62:11];
2'b01, 2'b10, 2'b11:
CASE_guard6451_0b0_sfd___35005_BITS_62_TO_11_0_ETC__q103 =
_theResult___sfd__h97094;
endcase
end
always@(requestR or
sfd___3__h15005 or
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d3027 or
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d3025 or
CASE_guard6451_0b0_sfd___35005_BITS_62_TO_11_0_ETC__q103)
begin
case (requestR[194:192])
3'h1:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3031 =
sfd___3__h15005[62:11];
3'h2:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3031 =
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d3027;
3'h3:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3031 =
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d3025;
3'h4:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3031 =
CASE_guard6451_0b0_sfd___35005_BITS_62_TO_11_0_ETC__q103;
default: IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3031 =
52'd0;
endcase
end
always@(guard__h96451 or
sfd___3__h15005 or out_sfd__h97097 or _theResult___sfd__h97094)
begin
case (guard__h96451)
2'b0, 2'b01:
CASE_guard6451_0b0_sfd___35005_BITS_62_TO_11_0_ETC__q104 =
sfd___3__h15005[62:11];
2'b10:
CASE_guard6451_0b0_sfd___35005_BITS_62_TO_11_0_ETC__q104 =
out_sfd__h97097;
2'b11:
CASE_guard6451_0b0_sfd___35005_BITS_62_TO_11_0_ETC__q104 =
_theResult___sfd__h97094;
endcase
end
always@(guard__h95721 or _theResult___exp__h96337)
begin
case (guard__h95721)
2'b0: CASE_guard5721_0b0_0_0b1_theResult___exp6337_0_ETC__q105 = 11'd0;
2'b01, 2'b10, 2'b11:
CASE_guard5721_0b0_0_0b1_theResult___exp6337_0_ETC__q105 =
_theResult___exp__h96337;
endcase
end
always@(requestR or
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2958 or
guard__h95721 or
requestR_BITS_191_TO_128__q1 or
_theResult___exp__h96337 or
CASE_guard5721_0b0_0_0b1_theResult___exp6337_0_ETC__q105)
begin
case (requestR[194:192])
3'h2:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2961 =
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2958;
3'h3:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2961 =
(guard__h95721 == 2'b0 || requestR_BITS_191_TO_128__q1[63]) ?
11'd0 :
_theResult___exp__h96337;
3'h4:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2961 =
CASE_guard5721_0b0_0_0b1_theResult___exp6337_0_ETC__q105;
default: IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2961 =
11'd0;
endcase
end
always@(guard__h95721 or out_exp__h96340 or _theResult___exp__h96337)
begin
case (guard__h95721)
2'b0, 2'b01:
CASE_guard5721_0b0_0_0b1_0_0b10_out_exp6340_0b_ETC__q106 = 11'd0;
2'b10:
CASE_guard5721_0b0_0_0b1_0_0b10_out_exp6340_0b_ETC__q106 =
out_exp__h96340;
2'b11:
CASE_guard5721_0b0_0_0b1_0_0b10_out_exp6340_0b_ETC__q106 =
_theResult___exp__h96337;
endcase
end
always@(guard__h95721 or sfd___3__h15005 or _theResult___sfd__h96338)
begin
case (guard__h95721)
2'b0:
CASE_guard5721_0b0_sfd___35005_BITS_63_TO_12_0_ETC__q107 =
sfd___3__h15005[63:12];
2'b01, 2'b10, 2'b11:
CASE_guard5721_0b0_sfd___35005_BITS_63_TO_12_0_ETC__q107 =
_theResult___sfd__h96338;
endcase
end
always@(requestR or
sfd___3__h15005 or
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d3009 or
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d3007 or
CASE_guard5721_0b0_sfd___35005_BITS_63_TO_12_0_ETC__q107)
begin
case (requestR[194:192])
3'h1:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3013 =
sfd___3__h15005[63:12];
3'h2:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3013 =
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d3009;
3'h3:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3013 =
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d3007;
3'h4:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3013 =
CASE_guard5721_0b0_sfd___35005_BITS_63_TO_12_0_ETC__q107;
default: IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3013 =
52'd0;
endcase
end
always@(guard__h95721 or
sfd___3__h15005 or out_sfd__h96341 or _theResult___sfd__h96338)
begin
case (guard__h95721)
2'b0, 2'b01:
CASE_guard5721_0b0_sfd___35005_BITS_63_TO_12_0_ETC__q108 =
sfd___3__h15005[63:12];
2'b10:
CASE_guard5721_0b0_sfd___35005_BITS_63_TO_12_0_ETC__q108 =
out_sfd__h96341;
2'b11:
CASE_guard5721_0b0_sfd___35005_BITS_63_TO_12_0_ETC__q108 =
_theResult___sfd__h96338;
endcase
end
always@(guard__h108975 or x__h108990 or _theResult___exp__h109617)
begin
case (guard__h108975)
2'b0:
CASE_guard08975_0b0_x08990_BITS_10_TO_0_0b1_th_ETC__q109 =
x__h108990[10:0];
2'b01, 2'b10, 2'b11:
CASE_guard08975_0b0_x08990_BITS_10_TO_0_0b1_th_ETC__q109 =
_theResult___exp__h109617;
endcase
end
always@(requestR or
x__h108990 or
guard__h108975 or
_theResult___exp__h109617 or
CASE_guard08975_0b0_x08990_BITS_10_TO_0_0b1_th_ETC__q109)
begin
case (requestR[194:192])
3'h1, 3'h2:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3147 =
x__h108990[10:0];
3'h3:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3147 =
(guard__h108975 == 2'b0) ?
x__h108990[10:0] :
_theResult___exp__h109617;
3'h4:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3147 =
CASE_guard08975_0b0_x08990_BITS_10_TO_0_0b1_th_ETC__q109;
default: IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3147 =
11'd0;
endcase
end
always@(guard__h108975 or
x__h108990 or out_exp__h109620 or _theResult___exp__h109617)
begin
case (guard__h108975)
2'b0, 2'b01:
CASE_guard08975_0b0_x08990_BITS_10_TO_0_0b1_x0_ETC__q110 =
x__h108990[10:0];
2'b10:
CASE_guard08975_0b0_x08990_BITS_10_TO_0_0b1_x0_ETC__q110 =
out_exp__h109620;
2'b11:
CASE_guard08975_0b0_x08990_BITS_10_TO_0_0b1_x0_ETC__q110 =
_theResult___exp__h109617;
endcase
end
always@(guard__h108975 or sfd___3__h27286 or _theResult___sfd__h109618)
begin
case (guard__h108975)
2'b0:
CASE_guard08975_0b0_sfd___37286_BITS_62_TO_11__ETC__q111 =
sfd___3__h27286[62:11];
2'b01, 2'b10, 2'b11:
CASE_guard08975_0b0_sfd___37286_BITS_62_TO_11__ETC__q111 =
_theResult___sfd__h109618;
endcase
end
always@(requestR or
sfd___3__h27286 or
guard__h108975 or
_theResult___sfd__h109618 or
CASE_guard08975_0b0_sfd___37286_BITS_62_TO_11__ETC__q111)
begin
case (requestR[194:192])
3'h1, 3'h2:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3185 =
sfd___3__h27286[62:11];
3'h3:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3185 =
(guard__h108975 == 2'b0) ?
sfd___3__h27286[62:11] :
_theResult___sfd__h109618;
3'h4:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3185 =
CASE_guard08975_0b0_sfd___37286_BITS_62_TO_11__ETC__q111;
default: IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3185 =
52'd0;
endcase
end
always@(guard__h108975 or
sfd___3__h27286 or out_sfd__h109621 or _theResult___sfd__h109618)
begin
case (guard__h108975)
2'b0, 2'b01:
CASE_guard08975_0b0_sfd___37286_BITS_62_TO_11__ETC__q112 =
sfd___3__h27286[62:11];
2'b10:
CASE_guard08975_0b0_sfd___37286_BITS_62_TO_11__ETC__q112 =
out_sfd__h109621;
2'b11:
CASE_guard08975_0b0_sfd___37286_BITS_62_TO_11__ETC__q112 =
_theResult___sfd__h109618;
endcase
end
always@(guard__h108246 or sfd___3__h27286 or _theResult___sfd__h108863)
begin
case (guard__h108246)
2'b0:
CASE_guard08246_0b0_sfd___37286_BITS_63_TO_12__ETC__q113 =
sfd___3__h27286[63:12];
2'b01, 2'b10, 2'b11:
CASE_guard08246_0b0_sfd___37286_BITS_63_TO_12__ETC__q113 =
_theResult___sfd__h108863;
endcase
end
always@(requestR or
sfd___3__h27286 or
guard__h108246 or
_theResult___sfd__h108863 or
CASE_guard08246_0b0_sfd___37286_BITS_63_TO_12__ETC__q113)
begin
case (requestR[194:192])
3'h1, 3'h2:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3170 =
sfd___3__h27286[63:12];
3'h3:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3170 =
(guard__h108246 == 2'b0) ?
sfd___3__h27286[63:12] :
_theResult___sfd__h108863;
3'h4:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3170 =
CASE_guard08246_0b0_sfd___37286_BITS_63_TO_12__ETC__q113;
default: IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3170 =
52'd0;
endcase
end
always@(guard__h108246 or
sfd___3__h27286 or out_sfd__h108866 or _theResult___sfd__h108863)
begin
case (guard__h108246)
2'b0, 2'b01:
CASE_guard08246_0b0_sfd___37286_BITS_63_TO_12__ETC__q114 =
sfd___3__h27286[63:12];
2'b10:
CASE_guard08246_0b0_sfd___37286_BITS_63_TO_12__ETC__q114 =
out_sfd__h108866;
2'b11:
CASE_guard08246_0b0_sfd___37286_BITS_63_TO_12__ETC__q114 =
_theResult___sfd__h108863;
endcase
end
always@(guard__h126038 or
_theResult___fst_exp__h135390 or _theResult___exp__h135916)
begin
case (guard__h126038)
2'b0:
CASE_guard26038_0b0_theResult___fst_exp35390_0_ETC__q127 =
_theResult___fst_exp__h135390;
2'b01, 2'b10, 2'b11:
CASE_guard26038_0b0_theResult___fst_exp35390_0_ETC__q127 =
_theResult___exp__h135916;
endcase
end
always@(requestR or
_theResult___fst_exp__h135390 or
IF_IF_IF_IF_0b0_CONCAT_NOT_IF_requestR_3_BIT_2_ETC___d3715 or
IF_IF_IF_IF_0b0_CONCAT_NOT_IF_requestR_3_BIT_2_ETC___d3713 or
CASE_guard26038_0b0_theResult___fst_exp35390_0_ETC__q127)
begin
case (requestR[194:192])
3'h1:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3719 =
_theResult___fst_exp__h135390;
3'h2:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3719 =
IF_IF_IF_IF_0b0_CONCAT_NOT_IF_requestR_3_BIT_2_ETC___d3715;
3'h3:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3719 =
IF_IF_IF_IF_0b0_CONCAT_NOT_IF_requestR_3_BIT_2_ETC___d3713;
3'h4:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3719 =
CASE_guard26038_0b0_theResult___fst_exp35390_0_ETC__q127;
default: IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3719 =
8'd0;
endcase
end
always@(guard__h126038 or
_theResult___fst_exp__h135390 or
out_exp__h135919 or _theResult___exp__h135916)
begin
case (guard__h126038)
2'b0, 2'b01:
CASE_guard26038_0b0_theResult___fst_exp35390_0_ETC__q128 =
_theResult___fst_exp__h135390;
2'b10:
CASE_guard26038_0b0_theResult___fst_exp35390_0_ETC__q128 =
out_exp__h135919;
2'b11:
CASE_guard26038_0b0_theResult___fst_exp35390_0_ETC__q128 =
_theResult___exp__h135916;
endcase
end
always@(guard__h136028 or
_theResult___fst_exp__h145309 or _theResult___exp__h145761)
begin
case (guard__h136028)
2'b0:
CASE_guard36028_0b0_theResult___fst_exp45309_0_ETC__q129 =
_theResult___fst_exp__h145309;
2'b01, 2'b10, 2'b11:
CASE_guard36028_0b0_theResult___fst_exp45309_0_ETC__q129 =
_theResult___exp__h145761;
endcase
end
always@(requestR or
_theResult___fst_exp__h145309 or
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d3832 or
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d3830 or
CASE_guard36028_0b0_theResult___fst_exp45309_0_ETC__q129)
begin
case (requestR[194:192])
3'h1:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3836 =
_theResult___fst_exp__h145309;
3'h2:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3836 =
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d3832;
3'h3:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3836 =
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d3830;
3'h4:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3836 =
CASE_guard36028_0b0_theResult___fst_exp45309_0_ETC__q129;
default: IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3836 =
8'd0;
endcase
end
always@(guard__h136028 or
_theResult___fst_exp__h145309 or
out_exp__h145764 or _theResult___exp__h145761)
begin
case (guard__h136028)
2'b0, 2'b01:
CASE_guard36028_0b0_theResult___fst_exp45309_0_ETC__q130 =
_theResult___fst_exp__h145309;
2'b10:
CASE_guard36028_0b0_theResult___fst_exp45309_0_ETC__q130 =
out_exp__h145764;
2'b11:
CASE_guard36028_0b0_theResult___fst_exp45309_0_ETC__q130 =
_theResult___exp__h145761;
endcase
end
always@(guard__h146250 or
_theResult___fst_exp__h155731 or _theResult___exp__h156257)
begin
case (guard__h146250)
2'b0:
CASE_guard46250_0b0_theResult___fst_exp55731_0_ETC__q131 =
_theResult___fst_exp__h155731;
2'b01, 2'b10, 2'b11:
CASE_guard46250_0b0_theResult___fst_exp55731_0_ETC__q131 =
_theResult___exp__h156257;
endcase
end
always@(requestR or
_theResult___fst_exp__h155731 or
IF_IF_IF_IF_3970_MINUS_SEXT_IF_requestR_3_BIT__ETC___d4159 or
IF_IF_IF_IF_3970_MINUS_SEXT_IF_requestR_3_BIT__ETC___d4157 or
CASE_guard46250_0b0_theResult___fst_exp55731_0_ETC__q131)
begin
case (requestR[194:192])
3'h1:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4163 =
_theResult___fst_exp__h155731;
3'h2:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4163 =
IF_IF_IF_IF_3970_MINUS_SEXT_IF_requestR_3_BIT__ETC___d4159;
3'h3:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4163 =
IF_IF_IF_IF_3970_MINUS_SEXT_IF_requestR_3_BIT__ETC___d4157;
3'h4:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4163 =
CASE_guard46250_0b0_theResult___fst_exp55731_0_ETC__q131;
default: IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4163 =
8'd0;
endcase
end
always@(guard__h146250 or
_theResult___fst_exp__h155731 or
out_exp__h156260 or _theResult___exp__h156257)
begin
case (guard__h146250)
2'b0, 2'b01:
CASE_guard46250_0b0_theResult___fst_exp55731_0_ETC__q132 =
_theResult___fst_exp__h155731;
2'b10:
CASE_guard46250_0b0_theResult___fst_exp55731_0_ETC__q132 =
out_exp__h156260;
2'b11:
CASE_guard46250_0b0_theResult___fst_exp55731_0_ETC__q132 =
_theResult___exp__h156257;
endcase
end
always@(guard__h156369 or
_theResult___fst_exp__h165679 or _theResult___exp__h166156)
begin
case (guard__h156369)
2'b0:
CASE_guard56369_0b0_theResult___fst_exp65679_0_ETC__q133 =
_theResult___fst_exp__h165679;
2'b01, 2'b10, 2'b11:
CASE_guard56369_0b0_theResult___fst_exp65679_0_ETC__q133 =
_theResult___exp__h166156;
endcase
end
always@(requestR or
_theResult___fst_exp__h165679 or
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d4228 or
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d4226 or
CASE_guard56369_0b0_theResult___fst_exp65679_0_ETC__q133)
begin
case (requestR[194:192])
3'h1:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4232 =
_theResult___fst_exp__h165679;
3'h2:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4232 =
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d4228;
3'h3:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4232 =
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d4226;
3'h4:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4232 =
CASE_guard56369_0b0_theResult___fst_exp65679_0_ETC__q133;
default: IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4232 =
8'd0;
endcase
end
always@(guard__h156369 or
_theResult___fst_exp__h165679 or
out_exp__h166159 or _theResult___exp__h166156)
begin
case (guard__h156369)
2'b0, 2'b01:
CASE_guard56369_0b0_theResult___fst_exp65679_0_ETC__q134 =
_theResult___fst_exp__h165679;
2'b10:
CASE_guard56369_0b0_theResult___fst_exp65679_0_ETC__q134 =
out_exp__h166159;
2'b11:
CASE_guard56369_0b0_theResult___fst_exp65679_0_ETC__q134 =
_theResult___exp__h166156;
endcase
end
always@(guard__h126038 or sfdin__h135384 or _theResult___sfd__h135917)
begin
case (guard__h126038)
2'b0:
CASE_guard26038_0b0_sfdin35384_BITS_56_TO_34_0_ETC__q135 =
sfdin__h135384[56:34];
2'b01, 2'b10, 2'b11:
CASE_guard26038_0b0_sfdin35384_BITS_56_TO_34_0_ETC__q135 =
_theResult___sfd__h135917;
endcase
end
always@(requestR or
sfdin__h135384 or
IF_IF_IF_IF_0b0_CONCAT_NOT_IF_requestR_3_BIT_2_ETC___d4262 or
IF_IF_IF_IF_0b0_CONCAT_NOT_IF_requestR_3_BIT_2_ETC___d4260 or
CASE_guard26038_0b0_sfdin35384_BITS_56_TO_34_0_ETC__q135)
begin
case (requestR[194:192])
3'h1:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4266 =
sfdin__h135384[56:34];
3'h2:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4266 =
IF_IF_IF_IF_0b0_CONCAT_NOT_IF_requestR_3_BIT_2_ETC___d4262;
3'h3:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4266 =
IF_IF_IF_IF_0b0_CONCAT_NOT_IF_requestR_3_BIT_2_ETC___d4260;
3'h4:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4266 =
CASE_guard26038_0b0_sfdin35384_BITS_56_TO_34_0_ETC__q135;
default: IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4266 =
23'd0;
endcase
end
always@(guard__h126038 or
sfdin__h135384 or out_sfd__h135920 or _theResult___sfd__h135917)
begin
case (guard__h126038)
2'b0, 2'b01:
CASE_guard26038_0b0_sfdin35384_BITS_56_TO_34_0_ETC__q136 =
sfdin__h135384[56:34];
2'b10:
CASE_guard26038_0b0_sfdin35384_BITS_56_TO_34_0_ETC__q136 =
out_sfd__h135920;
2'b11:
CASE_guard26038_0b0_sfdin35384_BITS_56_TO_34_0_ETC__q136 =
_theResult___sfd__h135917;
endcase
end
always@(guard__h136028 or
_theResult___snd__h145260 or _theResult___sfd__h145762)
begin
case (guard__h136028)
2'b0:
CASE_guard36028_0b0_theResult___snd45260_BITS__ETC__q137 =
_theResult___snd__h145260[56:34];
2'b01, 2'b10, 2'b11:
CASE_guard36028_0b0_theResult___snd45260_BITS__ETC__q137 =
_theResult___sfd__h145762;
endcase
end
always@(requestR or
_theResult___snd__h145260 or
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d4281 or
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d4279 or
CASE_guard36028_0b0_theResult___snd45260_BITS__ETC__q137)
begin
case (requestR[194:192])
3'h1:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4285 =
_theResult___snd__h145260[56:34];
3'h2:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4285 =
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d4281;
3'h3:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4285 =
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d4279;
3'h4:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4285 =
CASE_guard36028_0b0_theResult___snd45260_BITS__ETC__q137;
default: IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4285 =
23'd0;
endcase
end
always@(guard__h136028 or
_theResult___snd__h145260 or
out_sfd__h145765 or _theResult___sfd__h145762)
begin
case (guard__h136028)
2'b0, 2'b01:
CASE_guard36028_0b0_theResult___snd45260_BITS__ETC__q138 =
_theResult___snd__h145260[56:34];
2'b10:
CASE_guard36028_0b0_theResult___snd45260_BITS__ETC__q138 =
out_sfd__h145765;
2'b11:
CASE_guard36028_0b0_theResult___snd45260_BITS__ETC__q138 =
_theResult___sfd__h145762;
endcase
end
always@(guard__h146250 or sfdin__h155725 or _theResult___sfd__h156258)
begin
case (guard__h146250)
2'b0:
CASE_guard46250_0b0_sfdin55725_BITS_56_TO_34_0_ETC__q139 =
sfdin__h155725[56:34];
2'b01, 2'b10, 2'b11:
CASE_guard46250_0b0_sfdin55725_BITS_56_TO_34_0_ETC__q139 =
_theResult___sfd__h156258;
endcase
end
always@(requestR or
sfdin__h155725 or
IF_IF_IF_IF_3970_MINUS_SEXT_IF_requestR_3_BIT__ETC___d4308 or
IF_IF_IF_IF_3970_MINUS_SEXT_IF_requestR_3_BIT__ETC___d4306 or
CASE_guard46250_0b0_sfdin55725_BITS_56_TO_34_0_ETC__q139)
begin
case (requestR[194:192])
3'h1:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4312 =
sfdin__h155725[56:34];
3'h2:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4312 =
IF_IF_IF_IF_3970_MINUS_SEXT_IF_requestR_3_BIT__ETC___d4308;
3'h3:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4312 =
IF_IF_IF_IF_3970_MINUS_SEXT_IF_requestR_3_BIT__ETC___d4306;
3'h4:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4312 =
CASE_guard46250_0b0_sfdin55725_BITS_56_TO_34_0_ETC__q139;
default: IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4312 =
23'd0;
endcase
end
always@(guard__h146250 or
sfdin__h155725 or out_sfd__h156261 or _theResult___sfd__h156258)
begin
case (guard__h146250)
2'b0, 2'b01:
CASE_guard46250_0b0_sfdin55725_BITS_56_TO_34_0_ETC__q140 =
sfdin__h155725[56:34];
2'b10:
CASE_guard46250_0b0_sfdin55725_BITS_56_TO_34_0_ETC__q140 =
out_sfd__h156261;
2'b11:
CASE_guard46250_0b0_sfdin55725_BITS_56_TO_34_0_ETC__q140 =
_theResult___sfd__h156258;
endcase
end
always@(guard__h156369 or
_theResult___snd__h165625 or _theResult___sfd__h166157)
begin
case (guard__h156369)
2'b0:
CASE_guard56369_0b0_theResult___snd65625_BITS__ETC__q141 =
_theResult___snd__h165625[56:34];
2'b01, 2'b10, 2'b11:
CASE_guard56369_0b0_theResult___snd65625_BITS__ETC__q141 =
_theResult___sfd__h166157;
endcase
end
always@(requestR or
_theResult___snd__h165625 or
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d4327 or
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d4325 or
CASE_guard56369_0b0_theResult___snd65625_BITS__ETC__q141)
begin
case (requestR[194:192])
3'h1:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4331 =
_theResult___snd__h165625[56:34];
3'h2:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4331 =
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d4327;
3'h3:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4331 =
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d4325;
3'h4:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4331 =
CASE_guard56369_0b0_theResult___snd65625_BITS__ETC__q141;
default: IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4331 =
23'd0;
endcase
end
always@(guard__h156369 or
_theResult___snd__h165625 or
out_sfd__h166160 or _theResult___sfd__h166157)
begin
case (guard__h156369)
2'b0, 2'b01:
CASE_guard56369_0b0_theResult___snd65625_BITS__ETC__q142 =
_theResult___snd__h165625[56:34];
2'b10:
CASE_guard56369_0b0_theResult___snd65625_BITS__ETC__q142 =
out_sfd__h166160;
2'b11:
CASE_guard56369_0b0_theResult___snd65625_BITS__ETC__q142 =
_theResult___sfd__h166157;
endcase
end
always@(guard__h126038 or requestR_BITS_191_TO_128__q1)
begin
case (guard__h126038)
2'b0, 2'b01, 2'b10:
CASE_guard26038_0b0_requestR_BITS_191_TO_128_B_ETC__q143 =
requestR_BITS_191_TO_128__q1[63];
2'd3:
CASE_guard26038_0b0_requestR_BITS_191_TO_128_B_ETC__q143 =
guard__h126038 == 2'b11 && requestR_BITS_191_TO_128__q1[63];
endcase
end
always@(requestR or requestR_BITS_191_TO_128__q1 or guard__h126038)
begin
case (requestR[194:192])
3'h2, 3'h3:
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q144 =
requestR_BITS_191_TO_128__q1[63];
3'h4:
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q144 =
(guard__h126038 == 2'b0) ?
requestR_BITS_191_TO_128__q1[63] :
(guard__h126038 == 2'b01 || guard__h126038 == 2'b10 ||
guard__h126038 == 2'b11) &&
requestR_BITS_191_TO_128__q1[63];
default: CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q144 =
requestR[194:192] == 3'h1 &&
requestR_BITS_191_TO_128__q1[63];
endcase
end
always@(guard__h136028 or requestR_BITS_191_TO_128__q1)
begin
case (guard__h136028)
2'b0, 2'b01, 2'b10:
CASE_guard36028_0b0_requestR_BITS_191_TO_128_B_ETC__q145 =
requestR_BITS_191_TO_128__q1[63];
2'd3:
CASE_guard36028_0b0_requestR_BITS_191_TO_128_B_ETC__q145 =
guard__h136028 == 2'b11 && requestR_BITS_191_TO_128__q1[63];
endcase
end
always@(requestR or requestR_BITS_191_TO_128__q1 or guard__h136028)
begin
case (requestR[194:192])
3'h2, 3'h3:
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q146 =
requestR_BITS_191_TO_128__q1[63];
3'h4:
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q146 =
(guard__h136028 == 2'b0) ?
requestR_BITS_191_TO_128__q1[63] :
(guard__h136028 == 2'b01 || guard__h136028 == 2'b10 ||
guard__h136028 == 2'b11) &&
requestR_BITS_191_TO_128__q1[63];
default: CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q146 =
requestR[194:192] == 3'h1 &&
requestR_BITS_191_TO_128__q1[63];
endcase
end
always@(guard__h146250 or requestR_BITS_191_TO_128__q1)
begin
case (guard__h146250)
2'b0, 2'b01, 2'b10:
CASE_guard46250_0b0_requestR_BITS_191_TO_128_B_ETC__q147 =
requestR_BITS_191_TO_128__q1[63];
2'd3:
CASE_guard46250_0b0_requestR_BITS_191_TO_128_B_ETC__q147 =
guard__h146250 == 2'b11 && requestR_BITS_191_TO_128__q1[63];
endcase
end
always@(requestR or requestR_BITS_191_TO_128__q1 or guard__h146250)
begin
case (requestR[194:192])
3'h2, 3'h3:
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q148 =
requestR_BITS_191_TO_128__q1[63];
3'h4:
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q148 =
(guard__h146250 == 2'b0) ?
requestR_BITS_191_TO_128__q1[63] :
(guard__h146250 == 2'b01 || guard__h146250 == 2'b10 ||
guard__h146250 == 2'b11) &&
requestR_BITS_191_TO_128__q1[63];
default: CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q148 =
requestR[194:192] == 3'h1 &&
requestR_BITS_191_TO_128__q1[63];
endcase
end
always@(guard__h156369 or requestR_BITS_191_TO_128__q1)
begin
case (guard__h156369)
2'b0, 2'b01, 2'b10:
CASE_guard56369_0b0_requestR_BITS_191_TO_128_B_ETC__q149 =
requestR_BITS_191_TO_128__q1[63];
2'd3:
CASE_guard56369_0b0_requestR_BITS_191_TO_128_B_ETC__q149 =
guard__h156369 == 2'b11 && requestR_BITS_191_TO_128__q1[63];
endcase
end
always@(requestR or requestR_BITS_191_TO_128__q1 or guard__h156369)
begin
case (requestR[194:192])
3'h2, 3'h3:
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q150 =
requestR_BITS_191_TO_128__q1[63];
3'h4:
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q150 =
(guard__h156369 == 2'b0) ?
requestR_BITS_191_TO_128__q1[63] :
(guard__h156369 == 2'b01 || guard__h156369 == 2'b10 ||
guard__h156369 == 2'b11) &&
requestR_BITS_191_TO_128__q1[63];
default: CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q150 =
requestR[194:192] == 3'h1 &&
requestR_BITS_191_TO_128__q1[63];
endcase
end
always@(guard__h181312 or
_theResult___fst_exp__h190506 or _theResult___exp__h191161)
begin
case (guard__h181312)
2'b0:
CASE_guard81312_0b0_theResult___fst_exp90506_0_ETC__q159 =
_theResult___fst_exp__h190506;
2'b01, 2'b10, 2'b11:
CASE_guard81312_0b0_theResult___fst_exp90506_0_ETC__q159 =
_theResult___exp__h191161;
endcase
end
always@(requestR or
_theResult___fst_exp__h190506 or
IF_IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d4669 or
IF_IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d4667 or
CASE_guard81312_0b0_theResult___fst_exp90506_0_ETC__q159)
begin
case (requestR[194:192])
3'h1:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4673 =
_theResult___fst_exp__h190506;
3'h2:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4673 =
IF_IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d4669;
3'h3:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4673 =
IF_IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d4667;
3'h4:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4673 =
CASE_guard81312_0b0_theResult___fst_exp90506_0_ETC__q159;
default: IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4673 =
11'd0;
endcase
end
always@(guard__h181312 or
_theResult___fst_exp__h190506 or
out_exp__h191164 or _theResult___exp__h191161)
begin
case (guard__h181312)
2'b0, 2'b01:
CASE_guard81312_0b0_theResult___fst_exp90506_0_ETC__q160 =
_theResult___fst_exp__h190506;
2'b10:
CASE_guard81312_0b0_theResult___fst_exp90506_0_ETC__q160 =
out_exp__h191164;
2'b11:
CASE_guard81312_0b0_theResult___fst_exp90506_0_ETC__q160 =
_theResult___exp__h191161;
endcase
end
always@(guard__h191853 or
_theResult___fst_exp__h201334 or _theResult___exp__h202063)
begin
case (guard__h191853)
2'b0:
CASE_guard91853_0b0_theResult___fst_exp01334_0_ETC__q161 =
_theResult___fst_exp__h201334;
2'b01, 2'b10, 2'b11:
CASE_guard91853_0b0_theResult___fst_exp01334_0_ETC__q161 =
_theResult___exp__h202063;
endcase
end
always@(requestR or
_theResult___fst_exp__h201334 or
IF_IF_IF_IF_3074_MINUS_SEXT_IF_IF_requestR_3_B_ETC___d4994 or
IF_IF_IF_IF_3074_MINUS_SEXT_IF_IF_requestR_3_B_ETC___d4992 or
CASE_guard91853_0b0_theResult___fst_exp01334_0_ETC__q161)
begin
case (requestR[194:192])
3'h1:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4998 =
_theResult___fst_exp__h201334;
3'h2:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4998 =
IF_IF_IF_IF_3074_MINUS_SEXT_IF_IF_requestR_3_B_ETC___d4994;
3'h3:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4998 =
IF_IF_IF_IF_3074_MINUS_SEXT_IF_IF_requestR_3_B_ETC___d4992;
3'h4:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4998 =
CASE_guard91853_0b0_theResult___fst_exp01334_0_ETC__q161;
default: IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4998 =
11'd0;
endcase
end
always@(guard__h191853 or
_theResult___fst_exp__h201334 or
out_exp__h202066 or _theResult___exp__h202063)
begin
case (guard__h191853)
2'b0, 2'b01:
CASE_guard91853_0b0_theResult___fst_exp01334_0_ETC__q162 =
_theResult___fst_exp__h201334;
2'b10:
CASE_guard91853_0b0_theResult___fst_exp01334_0_ETC__q162 =
out_exp__h202066;
2'b11:
CASE_guard91853_0b0_theResult___fst_exp01334_0_ETC__q162 =
_theResult___exp__h202063;
endcase
end
always@(guard__h202175 or
_theResult___fst_exp__h211398 or _theResult___exp__h212078)
begin
case (guard__h202175)
2'b0:
CASE_guard02175_0b0_theResult___fst_exp11398_0_ETC__q163 =
_theResult___fst_exp__h211398;
2'b01, 2'b10, 2'b11:
CASE_guard02175_0b0_theResult___fst_exp11398_0_ETC__q163 =
_theResult___exp__h212078;
endcase
end
always@(requestR or
_theResult___fst_exp__h211398 or
IF_IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d5063 or
IF_IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d5061 or
CASE_guard02175_0b0_theResult___fst_exp11398_0_ETC__q163)
begin
case (requestR[194:192])
3'h1:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d5067 =
_theResult___fst_exp__h211398;
3'h2:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d5067 =
IF_IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d5063;
3'h3:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d5067 =
IF_IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d5061;
3'h4:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d5067 =
CASE_guard02175_0b0_theResult___fst_exp11398_0_ETC__q163;
default: IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d5067 =
11'd0;
endcase
end
always@(guard__h202175 or
_theResult___fst_exp__h211398 or
out_exp__h212081 or _theResult___exp__h212078)
begin
case (guard__h202175)
2'b0, 2'b01:
CASE_guard02175_0b0_theResult___fst_exp11398_0_ETC__q164 =
_theResult___fst_exp__h211398;
2'b10:
CASE_guard02175_0b0_theResult___fst_exp11398_0_ETC__q164 =
out_exp__h212081;
2'b11:
CASE_guard02175_0b0_theResult___fst_exp11398_0_ETC__q164 =
_theResult___exp__h212078;
endcase
end
always@(guard__h181312 or requestR_BITS_191_TO_128__q1)
begin
case (guard__h181312)
2'b0, 2'b01, 2'b10:
CASE_guard81312_0b0_requestR_BITS_191_TO_128_B_ETC__q165 =
requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31];
2'd3:
CASE_guard81312_0b0_requestR_BITS_191_TO_128_B_ETC__q165 =
guard__h181312 == 2'b11 &&
requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31];
endcase
end
always@(requestR or requestR_BITS_191_TO_128__q1 or guard__h181312)
begin
case (requestR[194:192])
3'h2, 3'h3:
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q166 =
requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31];
3'h4:
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q166 =
(guard__h181312 == 2'b0) ?
requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31] :
(guard__h181312 == 2'b01 || guard__h181312 == 2'b10 ||
guard__h181312 == 2'b11) &&
requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31];
default: CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q166 =
requestR[194:192] == 3'h1 &&
requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31];
endcase
end
always@(guard__h191853 or requestR_BITS_191_TO_128__q1)
begin
case (guard__h191853)
2'b0, 2'b01, 2'b10:
CASE_guard91853_0b0_requestR_BITS_191_TO_128_B_ETC__q167 =
requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31];
2'd3:
CASE_guard91853_0b0_requestR_BITS_191_TO_128_B_ETC__q167 =
guard__h191853 == 2'b11 &&
requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31];
endcase
end
always@(requestR or requestR_BITS_191_TO_128__q1 or guard__h191853)
begin
case (requestR[194:192])
3'h2, 3'h3:
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q168 =
requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31];
3'h4:
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q168 =
(guard__h191853 == 2'b0) ?
requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31] :
(guard__h191853 == 2'b01 || guard__h191853 == 2'b10 ||
guard__h191853 == 2'b11) &&
requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31];
default: CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q168 =
requestR[194:192] == 3'h1 &&
requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31];
endcase
end
always@(guard__h202175 or requestR_BITS_191_TO_128__q1)
begin
case (guard__h202175)
2'b0, 2'b01, 2'b10:
CASE_guard02175_0b0_requestR_BITS_191_TO_128_B_ETC__q169 =
requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31];
2'd3:
CASE_guard02175_0b0_requestR_BITS_191_TO_128_B_ETC__q169 =
guard__h202175 == 2'b11 &&
requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31];
endcase
end
always@(requestR or requestR_BITS_191_TO_128__q1 or guard__h202175)
begin
case (requestR[194:192])
3'h2, 3'h3:
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q170 =
requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31];
3'h4:
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q170 =
(guard__h202175 == 2'b0) ?
requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31] :
(guard__h202175 == 2'b01 || guard__h202175 == 2'b10 ||
guard__h202175 == 2'b11) &&
requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31];
default: CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q170 =
requestR[194:192] == 3'h1 &&
requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31];
endcase
end
always@(guard__h181312 or
_theResult___snd__h190457 or _theResult___sfd__h191162)
begin
case (guard__h181312)
2'b0:
CASE_guard81312_0b0_theResult___snd90457_BITS__ETC__q171 =
_theResult___snd__h190457[56:5];
2'b01, 2'b10, 2'b11:
CASE_guard81312_0b0_theResult___snd90457_BITS__ETC__q171 =
_theResult___sfd__h191162;
endcase
end
always@(requestR or
_theResult___snd__h190457 or
IF_IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d5096 or
IF_IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d5094 or
CASE_guard81312_0b0_theResult___snd90457_BITS__ETC__q171)
begin
case (requestR[194:192])
3'h1:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d5100 =
_theResult___snd__h190457[56:5];
3'h2:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d5100 =
IF_IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d5096;
3'h3:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d5100 =
IF_IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d5094;
3'h4:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d5100 =
CASE_guard81312_0b0_theResult___snd90457_BITS__ETC__q171;
default: IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d5100 =
52'd0;
endcase
end
always@(guard__h181312 or
_theResult___snd__h190457 or
out_sfd__h191165 or _theResult___sfd__h191162)
begin
case (guard__h181312)
2'b0, 2'b01:
CASE_guard81312_0b0_theResult___snd90457_BITS__ETC__q172 =
_theResult___snd__h190457[56:5];
2'b10:
CASE_guard81312_0b0_theResult___snd90457_BITS__ETC__q172 =
out_sfd__h191165;
2'b11:
CASE_guard81312_0b0_theResult___snd90457_BITS__ETC__q172 =
_theResult___sfd__h191162;
endcase
end
always@(guard__h191853 or sfdin__h201328 or _theResult___sfd__h202064)
begin
case (guard__h191853)
2'b0:
CASE_guard91853_0b0_sfdin01328_BITS_56_TO_5_0b_ETC__q173 =
sfdin__h201328[56:5];
2'b01, 2'b10, 2'b11:
CASE_guard91853_0b0_sfdin01328_BITS_56_TO_5_0b_ETC__q173 =
_theResult___sfd__h202064;
endcase
end
always@(requestR or
sfdin__h201328 or
IF_IF_IF_IF_3074_MINUS_SEXT_IF_IF_requestR_3_B_ETC___d5123 or
IF_IF_IF_IF_3074_MINUS_SEXT_IF_IF_requestR_3_B_ETC___d5121 or
CASE_guard91853_0b0_sfdin01328_BITS_56_TO_5_0b_ETC__q173)
begin
case (requestR[194:192])
3'h1:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d5127 =
sfdin__h201328[56:5];
3'h2:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d5127 =
IF_IF_IF_IF_3074_MINUS_SEXT_IF_IF_requestR_3_B_ETC___d5123;
3'h3:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d5127 =
IF_IF_IF_IF_3074_MINUS_SEXT_IF_IF_requestR_3_B_ETC___d5121;
3'h4:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d5127 =
CASE_guard91853_0b0_sfdin01328_BITS_56_TO_5_0b_ETC__q173;
default: IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d5127 =
52'd0;
endcase
end
always@(guard__h191853 or
sfdin__h201328 or out_sfd__h202067 or _theResult___sfd__h202064)
begin
case (guard__h191853)
2'b0, 2'b01:
CASE_guard91853_0b0_sfdin01328_BITS_56_TO_5_0b_ETC__q174 =
sfdin__h201328[56:5];
2'b10:
CASE_guard91853_0b0_sfdin01328_BITS_56_TO_5_0b_ETC__q174 =
out_sfd__h202067;
2'b11:
CASE_guard91853_0b0_sfdin01328_BITS_56_TO_5_0b_ETC__q174 =
_theResult___sfd__h202064;
endcase
end
always@(guard__h202175 or
_theResult___snd__h211344 or _theResult___sfd__h212079)
begin
case (guard__h202175)
2'b0:
CASE_guard02175_0b0_theResult___snd11344_BITS__ETC__q175 =
_theResult___snd__h211344[56:5];
2'b01, 2'b10, 2'b11:
CASE_guard02175_0b0_theResult___snd11344_BITS__ETC__q175 =
_theResult___sfd__h212079;
endcase
end
always@(requestR or
_theResult___snd__h211344 or
IF_IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d5142 or
IF_IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d5140 or
CASE_guard02175_0b0_theResult___snd11344_BITS__ETC__q175)
begin
case (requestR[194:192])
3'h1:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d5146 =
_theResult___snd__h211344[56:5];
3'h2:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d5146 =
IF_IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d5142;
3'h3:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d5146 =
IF_IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d5140;
3'h4:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d5146 =
CASE_guard02175_0b0_theResult___snd11344_BITS__ETC__q175;
default: IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d5146 =
52'd0;
endcase
end
always@(guard__h202175 or
_theResult___snd__h211344 or
out_sfd__h212082 or _theResult___sfd__h212079)
begin
case (guard__h202175)
2'b0, 2'b01:
CASE_guard02175_0b0_theResult___snd11344_BITS__ETC__q176 =
_theResult___snd__h211344[56:5];
2'b10:
CASE_guard02175_0b0_theResult___snd11344_BITS__ETC__q176 =
out_sfd__h212082;
2'b11:
CASE_guard02175_0b0_theResult___snd11344_BITS__ETC__q176 =
_theResult___sfd__h212079;
endcase
end
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
stateR <= `BSV_ASSIGNMENT_DELAY 2'd0;
end
else
begin
if (stateR$EN) stateR <= `BSV_ASSIGNMENT_DELAY stateR$D_IN;
end
if (requestR$EN) requestR <= `BSV_ASSIGNMENT_DELAY requestR$D_IN;
if (resultR$EN) resultR <= `BSV_ASSIGNMENT_DELAY resultR$D_IN;
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
requestR = 215'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
resultR = 70'h2AAAAAAAAAAAAAAAAA;
stateR = 2'h2;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge CLK)
begin
#0;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFADD_S && NOT_verbosity_ULE_1_6___d27)
begin
v__h1224 = $stime;
#0;
end
v__h1218 = v__h1224 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFADD_S && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFADD: ", v__h1218);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFSUB_S && NOT_verbosity_ULE_1_6___d27)
begin
v__h1777 = $stime;
#0;
end
v__h1771 = v__h1777 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFSUB_S && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFSUB: ", v__h1771);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFMUL_S && NOT_verbosity_ULE_1_6___d27)
begin
v__h1966 = $stime;
#0;
end
v__h1960 = v__h1966 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFMUL_S && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFMUL: ", v__h1960);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFMADD_S && NOT_verbosity_ULE_1_6___d27)
begin
v__h2168 = $stime;
#0;
end
v__h2162 = v__h2168 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFMADD_S && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFMADD_S ", v__h2162);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFMSUB_S && NOT_verbosity_ULE_1_6___d27)
begin
v__h2418 = $stime;
#0;
end
v__h2412 = v__h2418 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFMSUB_S && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFMSUB_S ", v__h2412);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFNMADD_S && NOT_verbosity_ULE_1_6___d27)
begin
v__h2593 = $stime;
#0;
end
v__h2587 = v__h2593 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFNMADD_S && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFNMADD_S ", v__h2587);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFNMSUB_S && NOT_verbosity_ULE_1_6___d27)
begin
v__h2768 = $stime;
#0;
end
v__h2762 = v__h2768 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFNMSUB_S && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFNMSUB_S ", v__h2762);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFDIV_S && NOT_verbosity_ULE_1_6___d27)
begin
v__h2950 = $stime;
#0;
end
v__h2944 = v__h2950 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFDIV_S && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFDIV_S ", v__h2944);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFSQRT_S && NOT_verbosity_ULE_1_6___d27)
begin
v__h3139 = $stime;
#0;
end
v__h3133 = v__h3139 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFSQRT_S && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFSQRT_S ", v__h3133);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFSGNJ_S && NOT_verbosity_ULE_1_6___d27)
begin
v__h3337 = $stime;
#0;
end
v__h3331 = v__h3337 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFSGNJ_S && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFSGNJ_S ", v__h3331);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFSGNJN_S && NOT_verbosity_ULE_1_6___d27)
begin
v__h3520 = $stime;
#0;
end
v__h3514 = v__h3520 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFSGNJN_S && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFSGNJN_S ", v__h3514);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFSGNJX_S && NOT_verbosity_ULE_1_6___d27)
begin
v__h3693 = $stime;
#0;
end
v__h3687 = v__h3693 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFSGNJX_S && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFSGNJX_S ", v__h3687);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFCVT_S_L && NOT_verbosity_ULE_1_6___d27)
begin
v__h3882 = $stime;
#0;
end
v__h3876 = v__h3882 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFCVT_S_L && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFCVT_S_L ", v__h3876);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFCVT_S_L && NOT_verbosity_ULE_2_01___d702)
$write("v1 = %08x, rmd = ", requestR[191:128]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFCVT_S_L && NOT_verbosity_ULE_2_01___d702 &&
(requestR[194:192] == 3'h0 ||
requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4))
$write("<Round Mode: Nearest Even>");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFCVT_S_L && NOT_verbosity_ULE_2_01___d702 &&
requestR[194:192] == 3'h4)
$write("<Round Mode: Nearest Away From Zero>");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFCVT_S_L && NOT_verbosity_ULE_2_01___d702 &&
requestR[194:192] == 3'h3)
$write("<Round Mode: +Infinity>");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFCVT_S_L && NOT_verbosity_ULE_2_01___d702 &&
requestR[194:192] == 3'h2)
$write("<Round Mode: -Infinity>");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFCVT_S_L && NOT_verbosity_ULE_2_01___d702 &&
requestR[194:192] == 3'h1)
$write("<Round Mode: Zero>");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFCVT_S_L && NOT_verbosity_ULE_2_01___d702)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFCVT_S_L && NOT_verbosity_ULE_2_01___d702)
$display(" Result: (%08x, %05b)", res__h3932, fcsr__h3933);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFCVT_S_LU && NOT_verbosity_ULE_1_6___d27)
begin
v__h16640 = $stime;
#0;
end
v__h16634 = v__h16640 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFCVT_S_LU && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFCVT_S_LU ", v__h16634);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFCVT_S_W && NOT_verbosity_ULE_1_6___d27)
begin
v__h28741 = $stime;
#0;
end
v__h28735 = v__h28741 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFCVT_S_W && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFCVT_S_W ", v__h28735);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFCVT_S_WU && NOT_verbosity_ULE_1_6___d27)
begin
v__h35941 = $stime;
#0;
end
v__h35935 = v__h35941 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFCVT_S_WU && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFCVT_S_WU ", v__h35935);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFCVT_L_S && NOT_verbosity_ULE_1_6___d27)
begin
v__h42829 = $stime;
#0;
end
v__h42823 = v__h42829 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFCVT_L_S && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFCVT_L_S ", v__h42823);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFCVT_LU_S && NOT_verbosity_ULE_1_6___d27)
begin
v__h44905 = $stime;
#0;
end
v__h44899 = v__h44905 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFCVT_LU_S && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFCVT_LU_S ", v__h44899);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFCVT_W_S && NOT_verbosity_ULE_1_6___d27)
begin
v__h45689 = $stime;
#0;
end
v__h45683 = v__h45689 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFCVT_W_S && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFCVT_W_S ", v__h45683);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFCVT_WU_S && NOT_verbosity_ULE_1_6___d27)
begin
v__h47303 = $stime;
#0;
end
v__h47297 = v__h47303 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFCVT_WU_S && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFCVT_WU_S ", v__h47297);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFMIN_S && NOT_verbosity_ULE_1_6___d27)
begin
v__h48090 = $stime;
#0;
end
v__h48084 = v__h48090 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFMIN_S && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFMIN_S ", v__h48084);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFMAX_S && NOT_verbosity_ULE_1_6___d27)
begin
v__h50764 = $stime;
#0;
end
v__h50758 = v__h50764 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFMAX_S && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFMAX_S ", v__h50758);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFMV_W_X && NOT_verbosity_ULE_1_6___d27)
begin
v__h53335 = $stime;
#0;
end
v__h53329 = v__h53335 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFMV_W_X && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFMV_W_X ", v__h53329);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFMV_X_W && NOT_verbosity_ULE_1_6___d27)
begin
v__h53495 = $stime;
#0;
end
v__h53489 = v__h53495 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFMV_X_W && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFMV_X_W ", v__h53489);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFEQ_S && NOT_verbosity_ULE_1_6___d27)
begin
v__h53671 = $stime;
#0;
end
v__h53665 = v__h53671 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFEQ_S && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFEQ_S ", v__h53665);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFLT_S && NOT_verbosity_ULE_1_6___d27)
begin
v__h55194 = $stime;
#0;
end
v__h55188 = v__h55194 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFLT_S && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFLT_S ", v__h55188);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFLE_S && NOT_verbosity_ULE_1_6___d27)
begin
v__h56303 = $stime;
#0;
end
v__h56297 = v__h56303 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFLE_S && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFLE_S ", v__h56297);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFCLASS_S && NOT_verbosity_ULE_1_6___d27)
begin
v__h57430 = $stime;
#0;
end
v__h57424 = v__h57430 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFCLASS_S && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFCLASS_S ", v__h57424);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFADD_D && NOT_verbosity_ULE_1_6___d27)
begin
v__h57911 = $stime;
#0;
end
v__h57905 = v__h57911 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFADD_D && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFADD_D ", v__h57905);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFSUB_D && NOT_verbosity_ULE_1_6___d27)
begin
v__h58124 = $stime;
#0;
end
v__h58118 = v__h58124 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFSUB_D && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFSUB_D ", v__h58118);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFMUL_D && NOT_verbosity_ULE_1_6___d27)
begin
v__h58311 = $stime;
#0;
end
v__h58305 = v__h58311 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFMUL_D && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFMUL_D ", v__h58305);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFMADD_D && NOT_verbosity_ULE_1_6___d27)
begin
v__h58491 = $stime;
#0;
end
v__h58485 = v__h58491 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFMADD_D && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFMADD_D ", v__h58485);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFMSUB_D && NOT_verbosity_ULE_1_6___d27)
begin
v__h58676 = $stime;
#0;
end
v__h58670 = v__h58676 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFMSUB_D && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFMSUB_D ", v__h58670);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFNMADD_D && NOT_verbosity_ULE_1_6___d27)
begin
v__h58848 = $stime;
#0;
end
v__h58842 = v__h58848 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFNMADD_D && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFNMADD_D ", v__h58842);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFNMSUB_D && NOT_verbosity_ULE_1_6___d27)
begin
v__h59020 = $stime;
#0;
end
v__h59014 = v__h59020 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFNMSUB_D && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFNMSUB_D ", v__h59014);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFDIV_D && NOT_verbosity_ULE_1_6___d27)
begin
v__h59199 = $stime;
#0;
end
v__h59193 = v__h59199 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFDIV_D && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFDIV_D ", v__h59193);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFSQRT_D && NOT_verbosity_ULE_1_6___d27)
begin
v__h59386 = $stime;
#0;
end
v__h59380 = v__h59386 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFSQRT_D && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFSQRT_D ", v__h59380);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFSGNJ_D && NOT_verbosity_ULE_1_6___d27)
begin
v__h59583 = $stime;
#0;
end
v__h59577 = v__h59583 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFSGNJ_D && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFSGNJ_D ", v__h59577);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFSGNJN_D && NOT_verbosity_ULE_1_6___d27)
begin
v__h59744 = $stime;
#0;
end
v__h59738 = v__h59744 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFSGNJN_D && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFSGNJN_D ", v__h59738);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFSGNJX_D && NOT_verbosity_ULE_1_6___d27)
begin
v__h59907 = $stime;
#0;
end
v__h59901 = v__h59907 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFSGNJX_D && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFSGNJX_D ", v__h59901);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFCVT_D_W && NOT_verbosity_ULE_1_6___d27)
begin
v__h60075 = $stime;
#0;
end
v__h60069 = v__h60075 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFCVT_D_W && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFCVT_D_W ", v__h60069);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFCVT_D_WU && NOT_verbosity_ULE_1_6___d27)
begin
v__h71274 = $stime;
#0;
end
v__h71268 = v__h71274 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFCVT_D_WU && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFCVT_D_WU ", v__h71268);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFCVT_W_D && NOT_verbosity_ULE_1_6___d27)
begin
v__h82193 = $stime;
#0;
end
v__h82187 = v__h82193 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFCVT_W_D && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFCVT_W_D ", v__h82187);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFCVT_WU_D && NOT_verbosity_ULE_1_6___d27)
begin
v__h83807 = $stime;
#0;
end
v__h83801 = v__h83807 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFCVT_WU_D && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFCVT_WU_D ", v__h83801);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFCVT_D_L && NOT_verbosity_ULE_1_6___d27)
begin
v__h84594 = $stime;
#0;
end
v__h84588 = v__h84594 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFCVT_D_L && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFCVT_D_L ", v__h84588);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFCVT_D_LU && NOT_verbosity_ULE_1_6___d27)
begin
v__h97596 = $stime;
#0;
end
v__h97590 = v__h97596 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFCVT_D_LU && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFCVT_D_LU ", v__h97590);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFCVT_L_D && NOT_verbosity_ULE_1_6___d27)
begin
v__h110093 = $stime;
#0;
end
v__h110087 = v__h110093 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFCVT_L_D && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFCVT_L_D ", v__h110087);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFCVT_LU_D && NOT_verbosity_ULE_1_6___d27)
begin
v__h112152 = $stime;
#0;
end
v__h112146 = v__h112152 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFCVT_LU_D && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFCVT_LU_D ", v__h112146);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFCVT_S_D && NOT_verbosity_ULE_1_6___d27)
begin
v__h112936 = $stime;
#0;
end
v__h112930 = v__h112936 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFCVT_S_D && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFCVT_S_D ", v__h112930);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFCVT_D_S && NOT_verbosity_ULE_1_6___d27)
begin
v__h167802 = $stime;
#0;
end
v__h167796 = v__h167802 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFCVT_D_S && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFCVT_D_S ", v__h167796);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFMIN_D && NOT_verbosity_ULE_1_6___d27)
begin
v__h213792 = $stime;
#0;
end
v__h213786 = v__h213792 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFMIN_D && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFMIN_D ", v__h213786);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFMAX_D && NOT_verbosity_ULE_1_6___d27)
begin
v__h218378 = $stime;
#0;
end
v__h218372 = v__h218378 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFMAX_D && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFMAX_D ", v__h218372);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFEQ_D && NOT_verbosity_ULE_1_6___d27)
begin
v__h222864 = $stime;
#0;
end
v__h222858 = v__h222864 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFEQ_D && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFEQ_D ", v__h222858);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFLT_D && NOT_verbosity_ULE_1_6___d27)
begin
v__h225599 = $stime;
#0;
end
v__h225593 = v__h225599 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFLT_D && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFLT_D ", v__h225593);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFLE_D && NOT_verbosity_ULE_1_6___d27)
begin
v__h227516 = $stime;
#0;
end
v__h227510 = v__h227516 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFLE_D && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFLE_D ", v__h227510);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFMV_D_X && NOT_verbosity_ULE_1_6___d27)
begin
v__h229453 = $stime;
#0;
end
v__h229447 = v__h229453 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFMV_D_X && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFMV_D_X ", v__h229447);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFMV_X_D && NOT_verbosity_ULE_1_6___d27)
begin
v__h229605 = $stime;
#0;
end
v__h229599 = v__h229605 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFMV_X_D && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFMV_X_D ", v__h229599);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFCLASS_D && NOT_verbosity_ULE_1_6___d27)
begin
v__h229762 = $stime;
#0;
end
v__h229756 = v__h229762 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFCLASS_D && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFCLASS_D ", v__h229756);
end
// synopsys translate_on
endmodule // mkFBox_Core
|
//#############################################################################
//# Function: Dual data rate input buffer #
//#############################################################################
//# Author: Andreas Olofsson #
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
module oh_iddr #(parameter DW = 1 // width of data inputs
)
(
input clk, // clock
input ce, // clock enable, set to high to clock in data
input [DW-1:0] din, // data input sampled on both edges of clock
output reg [DW-1:0] q1, // iddr rising edge sampled data
output reg [DW-1:0] q2 // iddr falling edge sampled data
);
//regs("sl"=stable low, "sh"=stable high)
reg [DW-1:0] q1_sl;
reg [DW-1:0] q2_sh;
// rising edge sample
always @ (posedge clk)
if(ce)
q1_sl[DW-1:0] <= din[DW-1:0];
// falling edge sample
always @ (negedge clk)
q2_sh[DW-1:0] <= din[DW-1:0];
// pipeline for alignment
always @ (posedge clk)
begin
q1[DW-1:0] <= q1_sl[DW-1:0];
q2[DW-1:0] <= q2_sh[DW-1:0];
end
endmodule // oh_iddr
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps / 1ps
`ifdef BASIL_SBUS
`define SPLIT_BUS
`elsif BASIL_TOPSBUS
`define SPLIT_BUS
`endif
`ifndef BASIL_SBUS
`include "utils/bus_to_ip.v"
`include "gpio/gpio_core.v"
`include "gpio/gpio.v"
`include "spi/spi.v"
`include "spi/spi_core.v"
`include "spi/blk_mem_gen_8_to_1_2k.v"
`include "pulse_gen/pulse_gen.v"
`include "pulse_gen/pulse_gen_core.v"
`include "bram_fifo/bram_fifo_core.v"
`include "bram_fifo/bram_fifo.v"
`include "fast_spi_rx/fast_spi_rx.v"
`include "fast_spi_rx/fast_spi_rx_core.v"
`include "utils/cdc_syncfifo.v"
`include "utils/generic_fifo.v"
`include "utils/cdc_pulse_sync.v"
`include "utils/CG_MOD_pos.v"
`include "utils/clock_divider.v"
`include "utils/3_stage_synchronizer.v"
`include "utils/RAMB16_S1_S9_sim.v"
`else
$fatal("Sbus modules not implemented yet");
`endif
module tb (
input wire BUS_CLK,
input wire BUS_RST,
input wire [31:0] BUS_ADD,
`ifndef SPLIT_BUS
inout wire [31:0] BUS_DATA,
`else
input wire [31:0] BUS_DATA_IN,
output wire [31:0] BUS_DATA_OUT,
`endif
input wire BUS_RD,
input wire BUS_WR,
output wire BUS_BYTE_ACCESS
);
// MODULE ADREESSES //
localparam GPIO_BASEADDR = 32'h0000;
localparam GPIO_HIGHADDR = 32'h1000-1;
localparam SPI_BASEADDR = 32'h1000; //0x1000
localparam SPI_HIGHADDR = 32'h2000-1; //0x300f
localparam FAST_SR_AQ_BASEADDR = 32'h2000;
localparam FAST_SR_AQ_HIGHADDR = 32'h3000-1;
localparam PULSE_BASEADDR = 32'h3000;
localparam PULSE_HIGHADDR = PULSE_BASEADDR + 15;
localparam FIFO_BASEADDR = 32'h8000;
localparam FIFO_HIGHADDR = 32'h9000-1;
localparam FIFO_BASEADDR_DATA = 32'h8000_0000;
localparam FIFO_HIGHADDR_DATA = 32'h9000_0000;
localparam ABUSWIDTH = 32;
assign BUS_BYTE_ACCESS = BUS_ADD < 32'h8000_0000 ? 1'b1 : 1'b0;
// BUS/SBUS //
// Connect tb internal bus to external split bus
`ifdef BASIL_TOPSBUS
wire [31:0] BUS_DATA;
assign BUS_DATA = BUS_DATA_IN;
assign BUS_DATA_OUT = BUS_DATA;
`elsif BASIL_SBUS
wire [31:0] BUS_DATA_OUT_1;
wire [31:0] BUS_DATA_OUT_2;
wire [31:0] BUS_DATA_OUT_3;
wire [31:0] BUS_DATA_OUT_4;
wire [31:0] BUS_DATA_OUT_5;
assign BUS_DATA_OUT = BUS_DATA_OUT_1 | BUS_DATA_OUT_2 | BUS_DATA_OUT_3 | BUS_DATA_OUT_4 | BUS_DATA_OUT_5;
`endif
// MODULES //
`ifndef BASIL_SBUS
gpio #(
`else
gpio_sbus #(
`endif
.BASEADDR(GPIO_BASEADDR),
.HIGHADDR(GPIO_HIGHADDR),
.ABUSWIDTH(ABUSWIDTH),
.IO_WIDTH(8),
.IO_DIRECTION(8'hff)
) i_gpio (
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
`ifndef BASIL_SBUS
.BUS_DATA(BUS_DATA[7:0]),
`else
.BUS_DATA_IN(BUS_DATA_IN[7:0]),
.BUS_DATA_OUT(BUS_DATA_OUT_1[7:0]),
`endif
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.IO()
);
wire SPI_CLK;
wire EX_START_PULSE;
`ifndef BASIL_SBUS
pulse_gen #(
`else
pulse_gen_sbus #(
`endif
.BASEADDR(PULSE_BASEADDR),
.HIGHADDR(PULSE_HIGHADDR),
.ABUSWIDTH(ABUSWIDTH)
) i_pulse_gen (
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
`ifndef BASIL_SBUS
.BUS_DATA(BUS_DATA[7:0]),
`else
.BUS_DATA_IN(BUS_DATA_IN[7:0]),
.BUS_DATA_OUT(BUS_DATA_OUT_2[7:0]),
`endif
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.PULSE_CLK(SPI_CLK),
.EXT_START(1'b0),
.PULSE(EX_START_PULSE)
);
clock_divider #(
.DIVISOR(4)
) i_clock_divisor_spi (
.CLK(BUS_CLK),
.RESET(1'b0),
.CE(),
.CLOCK(SPI_CLK)
);
wire SCLK, SDI, SDO, SEN, SLD;
`ifndef BASIL_SBUS
spi #(
`else
spi_sbus #(
`endif
.BASEADDR(SPI_BASEADDR),
.HIGHADDR(SPI_HIGHADDR),
.ABUSWIDTH(ABUSWIDTH),
.MEM_BYTES(16)
) i_spi (
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
`ifndef BASIL_SBUS
.BUS_DATA(BUS_DATA[7:0]),
`else
.BUS_DATA_IN(BUS_DATA_IN[7:0]),
.BUS_DATA_OUT(BUS_DATA_OUT_3[7:0]),
`endif
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.SPI_CLK(SPI_CLK),
.EXT_START(EX_START_PULSE),
.SCLK(SCLK),
.SDI(SDI),
.SDO(SDO),
.SEN(SEN),
.SLD(SLD)
);
assign SDO = SDI;
wire FIFO_READ_SPI_RX;
wire FIFO_EMPTY_SPI_RX;
wire [31:0] FIFO_DATA_SPI_RX;
`ifndef BASIL_SBUS
fast_spi_rx #(
`else
fast_spi_rx_sbus #(
`endif
.BASEADDR(FAST_SR_AQ_BASEADDR),
.HIGHADDR(FAST_SR_AQ_HIGHADDR),
.ABUSWIDTH(ABUSWIDTH)
) i_pixel_sr_fast_rx (
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
`ifndef BASIL_SBUS
.BUS_DATA(BUS_DATA[7:0]),
`else
.BUS_DATA_IN(BUS_DATA_IN[7:0]),
.BUS_DATA_OUT(BUS_DATA_OUT_4[7:0]),
`endif
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.SCLK(~SPI_CLK),
.SDI(SDI),
.SEN(SEN),
.FIFO_READ(FIFO_READ_SPI_RX),
.FIFO_EMPTY(FIFO_EMPTY_SPI_RX),
.FIFO_DATA(FIFO_DATA_SPI_RX)
);
wire FIFO_READ, FIFO_EMPTY;
wire [31:0] FIFO_DATA;
assign FIFO_DATA = FIFO_DATA_SPI_RX;
assign FIFO_EMPTY = FIFO_EMPTY_SPI_RX;
assign FIFO_READ_SPI_RX = FIFO_READ;
`ifndef BASIL_SBUS
bram_fifo #(
`else
bram_fifo_sbus #(
`endif
.BASEADDR(FIFO_BASEADDR),
.HIGHADDR(FIFO_HIGHADDR),
.BASEADDR_DATA(FIFO_BASEADDR_DATA),
.HIGHADDR_DATA(FIFO_HIGHADDR_DATA),
.ABUSWIDTH(ABUSWIDTH)
) i_out_fifo (
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
`ifndef BASIL_SBUS
.BUS_DATA(BUS_DATA),
`else
.BUS_DATA_IN(BUS_DATA_IN),
.BUS_DATA_OUT(BUS_DATA_OUT_5),
`endif
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.FIFO_READ_NEXT_OUT(FIFO_READ),
.FIFO_EMPTY_IN(FIFO_EMPTY),
.FIFO_DATA(FIFO_DATA),
.FIFO_NOT_EMPTY(),
.FIFO_FULL(),
.FIFO_NEAR_FULL(),
.FIFO_READ_ERROR()
);
`ifndef VERILATOR_SIM
initial begin
$dumpfile("spi.vcd");
$dumpvars(0);
end
`endif
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: playback_driver.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module playback_driver();
parameter inputwidth=157;
parameter outputwidth=130;
parameter clockwidth=1;
reg [256*8-1:0] stimfile;
reg [256*8-1:0] iofile;
initial begin
stimfile = "not_provided";
if($test$plusargs("stim_file")) begin
$value$plusargs("stim_file=%s", stimfile);
end
end
reg [inputwidth-1:0] input_vector;
reg [inputwidth-1:0] input_vector_a;
reg [outputwidth-1:0] output_vector_ref;
reg clock_vector;
initial begin
clock_vector = 1'b0;
forever #418 clock_vector = ~clock_vector;
end
integer fid, code;
integer mismatch;
initial begin
fid = $fopen(stimfile, "r");
end
always @(posedge clock_vector) begin
#20;
input_vector = input_vector_a;
code = $fscanf(fid, "%b\n", input_vector_a);
if(code == 0 || code == -1) begin
if(mismatch == 0)
$display("Playback PASSED!");
else
$display("Playback FAILED with %1d mismatches!", mismatch);
$finish;
end
@(negedge clock_vector);
#1;
$fscanf(fid, "%b\n", output_vector_ref);
end
task displayMismatch;
input [7:0] port;
input exp;
input got;
begin
if(port < 124) begin
$display("spc_pcx_data_pa[%3d]: Expect:%b Got:%b",port, exp , got);
end else
if(port < 125) begin
$display("spc_pcx_atom_pq : Expect:%b Got:%b", exp , got);
end else begin
$display("spc_pcx_req_pq[%1d] : Expect:%b Got:%b", port-125,exp , got);
end
end
endtask
wire [outputwidth-1:0] output_vector;
reg [outputwidth-1:0] output_vector_mask;
wire [outputwidth-1:0] output_vector_masked;
wire [outputwidth-1:0] output_vector_ref_masked;
// WIRE Definitions for remove
wire spc_sscan_so;
wire spc_scanout0;
wire spc_scanout1;
wire tst_ctu_mbist_done;
wire tst_ctu_mbist_fail;
wire spc_efc_ifuse_data;
wire spc_efc_dfuse_data;
// WIRE Definitions for constraint
wire [3:0] const_cpuid = 4'b0000;
wire [7:0] const_maskid = 8'h20;
wire ctu_tck = 1'b0;
wire ctu_sscan_se = 1'b0;
wire ctu_sscan_snap = 1'b0;
wire [3:0] ctu_sscan_tid = 4'h1;
wire ctu_tst_mbist_enable = 1'b0;
wire efc_spc_fuse_clk1 = 1'b0;
wire efc_spc_fuse_clk2 = 1'b0;
wire efc_spc_ifuse_ashift = 1'b0;
wire efc_spc_ifuse_dshift = 1'b0;
wire efc_spc_ifuse_data = 1'b0;
wire efc_spc_dfuse_ashift = 1'b0;
wire efc_spc_dfuse_dshift = 1'b0;
wire efc_spc_dfuse_data = 1'b0;
wire ctu_tst_macrotest = 1'b0;
wire ctu_tst_scan_disable = 1'b0;
wire ctu_tst_short_chain = 1'b0;
wire global_shift_enable = 1'b0;
wire ctu_tst_scanmode = 1'b0;
wire spc_scanin0 = 1'b0;
wire spc_scanin1 = 1'b0;
// WIRE Definitions for clock
wire gclk;
// WIRE Definitions for input
wire [4:0] pcx_spc_grant_px;
wire cpx_spc_data_rdy_cx2;
wire [144:0] cpx_spc_data_cx2;
wire cluster_cken;
wire cmp_grst_l;
wire cmp_arst_l;
wire ctu_tst_pre_grst_l;
wire adbginit_l;
wire gdbginit_l;
// WIRE Definitions for output
wire [4:0] spc_pcx_req_pq;
wire spc_pcx_atom_pq;
wire [123:0] spc_pcx_data_pa;
// WIRE Definitions for inout
sparc sparc0 (
.spc_pcx_req_pq (spc_pcx_req_pq),
.spc_pcx_atom_pq (spc_pcx_atom_pq),
.spc_pcx_data_pa (spc_pcx_data_pa),
.spc_sscan_so (spc_sscan_so),
.spc_scanout0 (spc_scanout0),
.spc_scanout1 (spc_scanout1),
.tst_ctu_mbist_done (tst_ctu_mbist_done),
.tst_ctu_mbist_fail (tst_ctu_mbist_fail),
.spc_efc_ifuse_data (spc_efc_ifuse_data),
.spc_efc_dfuse_data (spc_efc_dfuse_data),
.pcx_spc_grant_px (pcx_spc_grant_px),
.cpx_spc_data_rdy_cx2 (cpx_spc_data_rdy_cx2),
.cpx_spc_data_cx2 (cpx_spc_data_cx2),
.const_cpuid (const_cpuid),
.const_maskid (const_maskid),
.ctu_tck (ctu_tck),
.ctu_sscan_se (ctu_sscan_se),
.ctu_sscan_snap (ctu_sscan_snap),
.ctu_sscan_tid (ctu_sscan_tid),
.ctu_tst_mbist_enable (ctu_tst_mbist_enable),
.efc_spc_fuse_clk1 (efc_spc_fuse_clk1),
.efc_spc_fuse_clk2 (efc_spc_fuse_clk2),
.efc_spc_ifuse_ashift (efc_spc_ifuse_ashift),
.efc_spc_ifuse_dshift (efc_spc_ifuse_dshift),
.efc_spc_ifuse_data (efc_spc_ifuse_data),
.efc_spc_dfuse_ashift (efc_spc_dfuse_ashift),
.efc_spc_dfuse_dshift (efc_spc_dfuse_dshift),
.efc_spc_dfuse_data (efc_spc_dfuse_data),
.ctu_tst_macrotest (ctu_tst_macrotest),
.ctu_tst_scan_disable (ctu_tst_scan_disable),
.ctu_tst_short_chain (ctu_tst_short_chain),
.global_shift_enable (global_shift_enable),
.ctu_tst_scanmode (ctu_tst_scanmode),
.spc_scanin0 (spc_scanin0),
.spc_scanin1 (spc_scanin1),
.cluster_cken (cluster_cken),
.gclk (gclk),
.cmp_grst_l (cmp_grst_l),
.cmp_arst_l (cmp_arst_l),
.ctu_tst_pre_grst_l (ctu_tst_pre_grst_l),
.adbginit_l (adbginit_l),
.gdbginit_l (gdbginit_l)
);
task generate_mask;
integer i;
begin
for(i=0;i<outputwidth;i=i+1)
output_vector_mask[i] = (output_vector_ref[i] === 1'b0) | (output_vector_ref[i] === 1'b1);
end
endtask
assign {pcx_spc_grant_px, cpx_spc_data_rdy_cx2, cpx_spc_data_cx2, cluster_cken, cmp_grst_l, cmp_arst_l, ctu_tst_pre_grst_l, adbginit_l, gdbginit_l} = input_vector;
assign {gclk} = clock_vector;
assign output_vector = {spc_pcx_req_pq, spc_pcx_atom_pq, spc_pcx_data_pa};
assign output_vector_ref_masked = output_vector_ref & output_vector_mask;
assign output_vector_masked = output_vector & output_vector_mask;
always @(output_vector_ref)
generate_mask;
integer i;
initial generate_mask;
initial mismatch = 0;
always @(negedge gclk) begin
if(output_vector_ref_masked !== output_vector_masked) begin
mismatch = mismatch + 1;
for(i=0;i<outputwidth;i=i+1)
if(output_vector_ref_masked[i] !== output_vector_masked[i])
displayMismatch(i, output_vector_ref_masked[i], output_vector_masked[i]);
$display("Number of cycles mismatched %d\n",mismatch);
end
end
endmodule
module cmp_top();
playback_driver iop();
`ifdef DUMP_ON
initial
if($test$plusargs("dump"))
$fsdbDumpvars(0, cmp_top.iop);
`endif
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's interface to SPRs ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// Decoding of SPR addresses and access to SPRs ////
//// ////
//// To Do: ////
//// - make it smaller and faster ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_sprs.v,v $
// Revision 1.2 2006-12-22 08:34:00 vak
// The design is successfully compiled using on-chip RAM.
//
// Revision 1.1 2006/12/21 16:46:58 vak
// Initial revision imported from
// http://www.opencores.org/cvsget.cgi/or1k/orp/orp_soc/rtl/verilog.
//
// Revision 1.11 2004/04/05 08:29:57 lampret
// Merged branch_qmem into main tree.
//
// Revision 1.9.4.1 2003/12/17 13:43:38 simons
// Exception prefix configuration changed.
//
// Revision 1.9 2002/09/07 05:42:02 lampret
// Added optional SR[CY]. Added define to enable additional (compare) flag modifiers. Defines are OR1200_IMPL_ADDC and OR1200_ADDITIONAL_FLAG_MODIFIERS.
//
// Revision 1.8 2002/08/28 01:44:25 lampret
// Removed some commented RTL. Fixed SR/ESR flag bug.
//
// Revision 1.7 2002/03/29 15:16:56 lampret
// Some of the warnings fixed.
//
// Revision 1.6 2002/03/11 01:26:57 lampret
// Changed generation of SPR address. Now it is ORed from base and offset instead of a sum.
//
// Revision 1.5 2002/02/01 19:56:54 lampret
// Fixed combinational loops.
//
// Revision 1.4 2002/01/23 07:52:36 lampret
// Changed default reset values for SR and ESR to match or1ksim's. Fixed flop model in or1200_dpram_32x32 when OR1200_XILINX_RAM32X1D is defined.
//
// Revision 1.3 2002/01/19 09:27:49 lampret
// SR[TEE] should be zero after reset.
//
// Revision 1.2 2002/01/18 07:56:00 lampret
// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.12 2001/11/23 21:42:31 simons
// Program counter divided to PPC and NPC.
//
// Revision 1.11 2001/11/23 08:38:51 lampret
// Changed DSR/DRR behavior and exception detection.
//
// Revision 1.10 2001/11/12 01:45:41 lampret
// Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports.
//
// Revision 1.9 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.8 2001/10/14 13:12:10 lampret
// MP3 version.
//
// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
// no message
//
// Revision 1.3 2001/08/13 03:36:20 lampret
// Added cfg regs. Moved all defines into one defines.v file. More cleanup.
//
// Revision 1.2 2001/08/09 13:39:33 lampret
// Major clean-up.
//
// Revision 1.1 2001/07/20 00:46:21 lampret
// Development version of RTL. Libraries are missing.
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
module or1200_sprs(
// Clk & Rst
clk, rst,
// Internal CPU interface
flagforw, flag_we, flag, cyforw, cy_we, carry,
addrbase, addrofs, dat_i, alu_op, branch_op,
epcr, eear, esr, except_started,
to_wbmux, epcr_we, eear_we, esr_we, pc_we, sr_we, to_sr, sr,
spr_dat_cfgr, spr_dat_rf, spr_dat_npc, spr_dat_ppc, spr_dat_mac,
// From/to other RISC units
spr_dat_pic, spr_dat_tt, spr_dat_pm,
spr_dat_dmmu, spr_dat_immu, spr_dat_du,
spr_addr, spr_dat_o, spr_cs, spr_we,
du_addr, du_dat_du, du_read,
du_write, du_dat_cpu
);
parameter width = `OR1200_OPERAND_WIDTH;
//
// I/O Ports
//
//
// Internal CPU interface
//
input clk; // Clock
input rst; // Reset
input flagforw; // From ALU
input flag_we; // From ALU
output flag; // SR[F]
input cyforw; // From ALU
input cy_we; // From ALU
output carry; // SR[CY]
input [width-1:0] addrbase; // SPR base address
input [15:0] addrofs; // SPR offset
input [width-1:0] dat_i; // SPR write data
input [`OR1200_ALUOP_WIDTH-1:0] alu_op; // ALU operation
input [`OR1200_BRANCHOP_WIDTH-1:0] branch_op; // Branch operation
input [width-1:0] epcr; // EPCR0
input [width-1:0] eear; // EEAR0
input [`OR1200_SR_WIDTH-1:0] esr; // ESR0
input except_started; // Exception was started
output [width-1:0] to_wbmux; // For l.mfspr
output epcr_we; // EPCR0 write enable
output eear_we; // EEAR0 write enable
output esr_we; // ESR0 write enable
output pc_we; // PC write enable
output sr_we; // Write enable SR
output [`OR1200_SR_WIDTH-1:0] to_sr; // Data to SR
output [`OR1200_SR_WIDTH-1:0] sr; // SR
input [31:0] spr_dat_cfgr; // Data from CFGR
input [31:0] spr_dat_rf; // Data from RF
input [31:0] spr_dat_npc; // Data from NPC
input [31:0] spr_dat_ppc; // Data from PPC
input [31:0] spr_dat_mac; // Data from MAC
//
// To/from other RISC units
//
input [31:0] spr_dat_pic; // Data from PIC
input [31:0] spr_dat_tt; // Data from TT
input [31:0] spr_dat_pm; // Data from PM
input [31:0] spr_dat_dmmu; // Data from DMMU
input [31:0] spr_dat_immu; // Data from IMMU
input [31:0] spr_dat_du; // Data from DU
output [31:0] spr_addr; // SPR Address
output [31:0] spr_dat_o; // Data to unit
output [31:0] spr_cs; // Unit select
output spr_we; // SPR write enable
//
// To/from Debug Unit
//
input [width-1:0] du_addr; // Address
input [width-1:0] du_dat_du; // Data from DU to SPRS
input du_read; // Read qualifier
input du_write; // Write qualifier
output [width-1:0] du_dat_cpu; // Data from SPRS to DU
//
// Internal regs & wires
//
reg [`OR1200_SR_WIDTH-1:0] sr; // SR
reg write_spr; // Write SPR
reg read_spr; // Read SPR
reg [width-1:0] to_wbmux; // For l.mfspr
wire cfgr_sel; // Select for cfg regs
wire rf_sel; // Select for RF
wire npc_sel; // Select for NPC
wire ppc_sel; // Select for PPC
wire sr_sel; // Select for SR
wire epcr_sel; // Select for EPCR0
wire eear_sel; // Select for EEAR0
wire esr_sel; // Select for ESR0
wire [31:0] sys_data; // Read data from system SPRs
wire du_access; // Debug unit access
wire [`OR1200_ALUOP_WIDTH-1:0] sprs_op; // ALU operation
reg [31:0] unqualified_cs; // Unqualified chip selects
//
// Decide if it is debug unit access
//
assign du_access = du_read | du_write;
//
// Generate sprs opcode
//
assign sprs_op = du_write ? `OR1200_ALUOP_MTSR : du_read ? `OR1200_ALUOP_MFSR : alu_op;
//
// Generate SPR address from base address and offset
// OR from debug unit address
//
assign spr_addr = du_access ? du_addr : addrbase | {16'h0000, addrofs};
//
// SPR is written by debug unit or by l.mtspr
//
assign spr_dat_o = du_write ? du_dat_du : dat_i;
//
// debug unit data input:
// - write into debug unit SPRs by debug unit itself
// - read of SPRS by debug unit
// - write into debug unit SPRs by l.mtspr
//
assign du_dat_cpu = du_write ? du_dat_du : du_read ? to_wbmux : dat_i;
//
// Write into SPRs when l.mtspr
//
assign spr_we = du_write | write_spr;
//
// Qualify chip selects
//
assign spr_cs = unqualified_cs & {32{read_spr | write_spr}};
//
// Decoding of groups
//
always @(spr_addr)
case (spr_addr[`OR1200_SPR_GROUP_BITS]) // synopsys parallel_case
`OR1200_SPR_GROUP_WIDTH'd00: unqualified_cs = 32'b00000000_00000000_00000000_00000001;
`OR1200_SPR_GROUP_WIDTH'd01: unqualified_cs = 32'b00000000_00000000_00000000_00000010;
`OR1200_SPR_GROUP_WIDTH'd02: unqualified_cs = 32'b00000000_00000000_00000000_00000100;
`OR1200_SPR_GROUP_WIDTH'd03: unqualified_cs = 32'b00000000_00000000_00000000_00001000;
`OR1200_SPR_GROUP_WIDTH'd04: unqualified_cs = 32'b00000000_00000000_00000000_00010000;
`OR1200_SPR_GROUP_WIDTH'd05: unqualified_cs = 32'b00000000_00000000_00000000_00100000;
`OR1200_SPR_GROUP_WIDTH'd06: unqualified_cs = 32'b00000000_00000000_00000000_01000000;
`OR1200_SPR_GROUP_WIDTH'd07: unqualified_cs = 32'b00000000_00000000_00000000_10000000;
`OR1200_SPR_GROUP_WIDTH'd08: unqualified_cs = 32'b00000000_00000000_00000001_00000000;
`OR1200_SPR_GROUP_WIDTH'd09: unqualified_cs = 32'b00000000_00000000_00000010_00000000;
`OR1200_SPR_GROUP_WIDTH'd10: unqualified_cs = 32'b00000000_00000000_00000100_00000000;
`OR1200_SPR_GROUP_WIDTH'd11: unqualified_cs = 32'b00000000_00000000_00001000_00000000;
`OR1200_SPR_GROUP_WIDTH'd12: unqualified_cs = 32'b00000000_00000000_00010000_00000000;
`OR1200_SPR_GROUP_WIDTH'd13: unqualified_cs = 32'b00000000_00000000_00100000_00000000;
`OR1200_SPR_GROUP_WIDTH'd14: unqualified_cs = 32'b00000000_00000000_01000000_00000000;
`OR1200_SPR_GROUP_WIDTH'd15: unqualified_cs = 32'b00000000_00000000_10000000_00000000;
`OR1200_SPR_GROUP_WIDTH'd16: unqualified_cs = 32'b00000000_00000001_00000000_00000000;
`OR1200_SPR_GROUP_WIDTH'd17: unqualified_cs = 32'b00000000_00000010_00000000_00000000;
`OR1200_SPR_GROUP_WIDTH'd18: unqualified_cs = 32'b00000000_00000100_00000000_00000000;
`OR1200_SPR_GROUP_WIDTH'd19: unqualified_cs = 32'b00000000_00001000_00000000_00000000;
`OR1200_SPR_GROUP_WIDTH'd20: unqualified_cs = 32'b00000000_00010000_00000000_00000000;
`OR1200_SPR_GROUP_WIDTH'd21: unqualified_cs = 32'b00000000_00100000_00000000_00000000;
`OR1200_SPR_GROUP_WIDTH'd22: unqualified_cs = 32'b00000000_01000000_00000000_00000000;
`OR1200_SPR_GROUP_WIDTH'd23: unqualified_cs = 32'b00000000_10000000_00000000_00000000;
`OR1200_SPR_GROUP_WIDTH'd24: unqualified_cs = 32'b00000001_00000000_00000000_00000000;
`OR1200_SPR_GROUP_WIDTH'd25: unqualified_cs = 32'b00000010_00000000_00000000_00000000;
`OR1200_SPR_GROUP_WIDTH'd26: unqualified_cs = 32'b00000100_00000000_00000000_00000000;
`OR1200_SPR_GROUP_WIDTH'd27: unqualified_cs = 32'b00001000_00000000_00000000_00000000;
`OR1200_SPR_GROUP_WIDTH'd28: unqualified_cs = 32'b00010000_00000000_00000000_00000000;
`OR1200_SPR_GROUP_WIDTH'd29: unqualified_cs = 32'b00100000_00000000_00000000_00000000;
`OR1200_SPR_GROUP_WIDTH'd30: unqualified_cs = 32'b01000000_00000000_00000000_00000000;
`OR1200_SPR_GROUP_WIDTH'd31: unqualified_cs = 32'b10000000_00000000_00000000_00000000;
endcase
//
// SPRs System Group
//
//
// What to write into SR
//
assign to_sr[`OR1200_SR_FO:`OR1200_SR_OV] =
(branch_op == `OR1200_BRANCHOP_RFE) ? esr[`OR1200_SR_FO:`OR1200_SR_OV] :
(write_spr && sr_sel) ? {1'b1, spr_dat_o[`OR1200_SR_FO-1:`OR1200_SR_OV]}:
sr[`OR1200_SR_FO:`OR1200_SR_OV];
assign to_sr[`OR1200_SR_CY] =
(branch_op == `OR1200_BRANCHOP_RFE) ? esr[`OR1200_SR_CY] :
cy_we ? cyforw :
(write_spr && sr_sel) ? spr_dat_o[`OR1200_SR_CY] :
sr[`OR1200_SR_CY];
assign to_sr[`OR1200_SR_F] =
(branch_op == `OR1200_BRANCHOP_RFE) ? esr[`OR1200_SR_F] :
flag_we ? flagforw :
(write_spr && sr_sel) ? spr_dat_o[`OR1200_SR_F] :
sr[`OR1200_SR_F];
assign to_sr[`OR1200_SR_CE:`OR1200_SR_SM] =
(branch_op == `OR1200_BRANCHOP_RFE) ? esr[`OR1200_SR_CE:`OR1200_SR_SM] :
(write_spr && sr_sel) ? spr_dat_o[`OR1200_SR_CE:`OR1200_SR_SM]:
sr[`OR1200_SR_CE:`OR1200_SR_SM];
//
// Selects for system SPRs
//
assign cfgr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:4] == `OR1200_SPR_CFGR));
assign rf_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:5] == `OR1200_SPR_RF));
assign npc_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_NPC));
assign ppc_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_PPC));
assign sr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_SR));
assign epcr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_EPCR));
assign eear_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_EEAR));
assign esr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_ESR));
//
// Write enables for system SPRs
//
assign sr_we = (write_spr && sr_sel) | (branch_op == `OR1200_BRANCHOP_RFE) | flag_we | cy_we;
assign pc_we = (write_spr && (npc_sel | ppc_sel));
assign epcr_we = (write_spr && epcr_sel);
assign eear_we = (write_spr && eear_sel);
assign esr_we = (write_spr && esr_sel);
//
// Output from system SPRs
//
assign sys_data = (spr_dat_cfgr & {32{read_spr & cfgr_sel}}) |
(spr_dat_rf & {32{read_spr & rf_sel}}) |
(spr_dat_npc & {32{read_spr & npc_sel}}) |
(spr_dat_ppc & {32{read_spr & ppc_sel}}) |
({{32-`OR1200_SR_WIDTH{1'b0}},sr} & {32{read_spr & sr_sel}}) |
(epcr & {32{read_spr & epcr_sel}}) |
(eear & {32{read_spr & eear_sel}}) |
({{32-`OR1200_SR_WIDTH{1'b0}},esr} & {32{read_spr & esr_sel}});
//
// Flag alias
//
assign flag = sr[`OR1200_SR_F];
//
// Carry alias
//
assign carry = sr[`OR1200_SR_CY];
//
// Supervision register
//
always @(posedge clk or posedge rst)
if (rst)
sr <= #1 {1'b1, {`OR1200_SR_WIDTH-2{1'b0}}, 1'b1};
else if (except_started) begin
sr[`OR1200_SR_SM] <= #1 1'b1;
sr[`OR1200_SR_TEE] <= #1 1'b0;
sr[`OR1200_SR_IEE] <= #1 1'b0;
sr[`OR1200_SR_DME] <= #1 1'b0;
sr[`OR1200_SR_IME] <= #1 1'b0;
end
else if (sr_we)
sr <= #1 to_sr[`OR1200_SR_WIDTH-1:0];
//
// MTSPR/MFSPR interface
//
always @(sprs_op or spr_addr or sys_data or spr_dat_mac or spr_dat_pic or spr_dat_pm or
spr_dat_dmmu or spr_dat_immu or spr_dat_du or spr_dat_tt) begin
case (sprs_op) // synopsys parallel_case
`OR1200_ALUOP_MTSR : begin
write_spr = 1'b1;
read_spr = 1'b0;
to_wbmux = 32'b0;
end
`OR1200_ALUOP_MFSR : begin
casex (spr_addr[`OR1200_SPR_GROUP_BITS]) // synopsys parallel_case
`OR1200_SPR_GROUP_TT:
to_wbmux = spr_dat_tt;
`OR1200_SPR_GROUP_PIC:
to_wbmux = spr_dat_pic;
`OR1200_SPR_GROUP_PM:
to_wbmux = spr_dat_pm;
`OR1200_SPR_GROUP_DMMU:
to_wbmux = spr_dat_dmmu;
`OR1200_SPR_GROUP_IMMU:
to_wbmux = spr_dat_immu;
`OR1200_SPR_GROUP_MAC:
to_wbmux = spr_dat_mac;
`OR1200_SPR_GROUP_DU:
to_wbmux = spr_dat_du;
`OR1200_SPR_GROUP_SYS:
to_wbmux = sys_data;
default:
to_wbmux = 32'b0;
endcase
write_spr = 1'b0;
read_spr = 1'b1;
end
default : begin
write_spr = 1'b0;
read_spr = 1'b0;
to_wbmux = 32'b0;
end
endcase
end
endmodule
|
`ifndef XILINX
module MULT18X18S
// The module was copied from the Ettus UHD code.
(output reg signed [35:0] P,
input signed [17:0] A,
input signed [17:0] B,
input C, // Clock
input CE, // Clock Enable
input R // Synchronous Reset
);
always @(posedge C)
if(R)
P <= 36'sd0;
else if(CE)
begin
P <= A * B;
end
endmodule
`endif
module multiply
#(
parameter WDTH = 0
)
(
input wire clk,
input wire rst_n,
input wire signed [WDTH-1:0] x,
input wire signed [WDTH-1:0] y,
output wire signed [WDTH-1:0] z
);
reg ce;
initial
ce <= 1'b1;
wire signed [17:0] xb;
wire signed [17:0] yb;
assign xb = x;
assign yb = y;
wire signed [35:0] xy;
MULT18X18S multer (.P(xy), .A(xb), .B(yb), .C(clk), .CE(ce), .R(~rst_n));
assign z = xy >>> (WDTH-1);
always @ (posedge clk)
begin
//xy <= xb * yb;
//z <= xy >>> (WDTH-2);
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DFRTN_TB_V
`define SKY130_FD_SC_HS__DFRTN_TB_V
/**
* dfrtn: Delay flop, inverted reset, inverted clock,
* complementary outputs.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__dfrtn.v"
module top();
// Inputs are registered
reg RESET_B;
reg D;
reg VPWR;
reg VGND;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
RESET_B = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 RESET_B = 1'b0;
#60 VGND = 1'b0;
#80 VPWR = 1'b0;
#100 D = 1'b1;
#120 RESET_B = 1'b1;
#140 VGND = 1'b1;
#160 VPWR = 1'b1;
#180 D = 1'b0;
#200 RESET_B = 1'b0;
#220 VGND = 1'b0;
#240 VPWR = 1'b0;
#260 VPWR = 1'b1;
#280 VGND = 1'b1;
#300 RESET_B = 1'b1;
#320 D = 1'b1;
#340 VPWR = 1'bx;
#360 VGND = 1'bx;
#380 RESET_B = 1'bx;
#400 D = 1'bx;
end
// Create a clock
reg CLK_N;
initial
begin
CLK_N = 1'b0;
end
always
begin
#5 CLK_N = ~CLK_N;
end
sky130_fd_sc_hs__dfrtn dut (.RESET_B(RESET_B), .D(D), .VPWR(VPWR), .VGND(VGND), .Q(Q), .CLK_N(CLK_N));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__DFRTN_TB_V
|
// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
// Date : Mon Sep 16 05:33:22 2019
// Host : varun-laptop running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_pointer_basic_0_1_sim_netlist.v
// Design : design_1_pointer_basic_0_1
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "design_1_pointer_basic_0_1,pointer_basic,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* IP_DEFINITION_SOURCE = "HLS" *)
(* X_CORE_INFO = "pointer_basic,Vivado 2018.2" *) (* hls_module = "yes" *)
(* NotValidForBitStream *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
(s_axi_pointer_basic_io_AWADDR,
s_axi_pointer_basic_io_AWVALID,
s_axi_pointer_basic_io_AWREADY,
s_axi_pointer_basic_io_WDATA,
s_axi_pointer_basic_io_WSTRB,
s_axi_pointer_basic_io_WVALID,
s_axi_pointer_basic_io_WREADY,
s_axi_pointer_basic_io_BRESP,
s_axi_pointer_basic_io_BVALID,
s_axi_pointer_basic_io_BREADY,
s_axi_pointer_basic_io_ARADDR,
s_axi_pointer_basic_io_ARVALID,
s_axi_pointer_basic_io_ARREADY,
s_axi_pointer_basic_io_RDATA,
s_axi_pointer_basic_io_RRESP,
s_axi_pointer_basic_io_RVALID,
s_axi_pointer_basic_io_RREADY,
ap_clk,
ap_rst_n,
interrupt);
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io AWADDR" *) input [4:0]s_axi_pointer_basic_io_AWADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io AWVALID" *) input s_axi_pointer_basic_io_AWVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io AWREADY" *) output s_axi_pointer_basic_io_AWREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io WDATA" *) input [31:0]s_axi_pointer_basic_io_WDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io WSTRB" *) input [3:0]s_axi_pointer_basic_io_WSTRB;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io WVALID" *) input s_axi_pointer_basic_io_WVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io WREADY" *) output s_axi_pointer_basic_io_WREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io BRESP" *) output [1:0]s_axi_pointer_basic_io_BRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io BVALID" *) output s_axi_pointer_basic_io_BVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io BREADY" *) input s_axi_pointer_basic_io_BREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io ARADDR" *) input [4:0]s_axi_pointer_basic_io_ARADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io ARVALID" *) input s_axi_pointer_basic_io_ARVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io ARREADY" *) output s_axi_pointer_basic_io_ARREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io RDATA" *) output [31:0]s_axi_pointer_basic_io_RDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io RRESP" *) output [1:0]s_axi_pointer_basic_io_RRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io RVALID" *) output s_axi_pointer_basic_io_RVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io RREADY" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s_axi_pointer_basic_io, ADDR_WIDTH 5, DATA_WIDTH 32, PROTOCOL AXI4LITE, READ_WRITE_MODE READ_WRITE, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {CLK {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}, FREQ_HZ 50000000, ID_WIDTH 0, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_2_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0" *) input s_axi_pointer_basic_io_RREADY;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 ap_clk CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME ap_clk, ASSOCIATED_BUSIF s_axi_pointer_basic_io, ASSOCIATED_RESET ap_rst_n, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {CLK {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}, FREQ_HZ 50000000, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_2_FCLK_CLK0" *) input ap_clk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 ap_rst_n RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME ap_rst_n, POLARITY ACTIVE_LOW, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {RST {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}" *) input ap_rst_n;
(* X_INTERFACE_INFO = "xilinx.com:signal:interrupt:1.0 interrupt INTERRUPT" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME interrupt, SENSITIVITY LEVEL_HIGH, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {INTERRUPT {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}, PortWidth 1" *) output interrupt;
wire ap_clk;
wire ap_rst_n;
wire interrupt;
wire [4:0]s_axi_pointer_basic_io_ARADDR;
wire s_axi_pointer_basic_io_ARREADY;
wire s_axi_pointer_basic_io_ARVALID;
wire [4:0]s_axi_pointer_basic_io_AWADDR;
wire s_axi_pointer_basic_io_AWREADY;
wire s_axi_pointer_basic_io_AWVALID;
wire s_axi_pointer_basic_io_BREADY;
wire [1:0]s_axi_pointer_basic_io_BRESP;
wire s_axi_pointer_basic_io_BVALID;
wire [31:0]s_axi_pointer_basic_io_RDATA;
wire s_axi_pointer_basic_io_RREADY;
wire [1:0]s_axi_pointer_basic_io_RRESP;
wire s_axi_pointer_basic_io_RVALID;
wire [31:0]s_axi_pointer_basic_io_WDATA;
wire s_axi_pointer_basic_io_WREADY;
wire [3:0]s_axi_pointer_basic_io_WSTRB;
wire s_axi_pointer_basic_io_WVALID;
(* C_S_AXI_DATA_WIDTH = "32" *)
(* C_S_AXI_POINTER_BASIC_IO_ADDR_WIDTH = "5" *)
(* C_S_AXI_POINTER_BASIC_IO_DATA_WIDTH = "32" *)
(* C_S_AXI_POINTER_BASIC_IO_WSTRB_WIDTH = "4" *)
(* C_S_AXI_WSTRB_WIDTH = "4" *)
(* ap_ST_fsm_state1 = "3'b001" *)
(* ap_ST_fsm_state2 = "3'b010" *)
(* ap_ST_fsm_state3 = "3'b100" *)
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_pointer_basic inst
(.ap_clk(ap_clk),
.ap_rst_n(ap_rst_n),
.interrupt(interrupt),
.s_axi_pointer_basic_io_ARADDR(s_axi_pointer_basic_io_ARADDR),
.s_axi_pointer_basic_io_ARREADY(s_axi_pointer_basic_io_ARREADY),
.s_axi_pointer_basic_io_ARVALID(s_axi_pointer_basic_io_ARVALID),
.s_axi_pointer_basic_io_AWADDR(s_axi_pointer_basic_io_AWADDR),
.s_axi_pointer_basic_io_AWREADY(s_axi_pointer_basic_io_AWREADY),
.s_axi_pointer_basic_io_AWVALID(s_axi_pointer_basic_io_AWVALID),
.s_axi_pointer_basic_io_BREADY(s_axi_pointer_basic_io_BREADY),
.s_axi_pointer_basic_io_BRESP(s_axi_pointer_basic_io_BRESP),
.s_axi_pointer_basic_io_BVALID(s_axi_pointer_basic_io_BVALID),
.s_axi_pointer_basic_io_RDATA(s_axi_pointer_basic_io_RDATA),
.s_axi_pointer_basic_io_RREADY(s_axi_pointer_basic_io_RREADY),
.s_axi_pointer_basic_io_RRESP(s_axi_pointer_basic_io_RRESP),
.s_axi_pointer_basic_io_RVALID(s_axi_pointer_basic_io_RVALID),
.s_axi_pointer_basic_io_WDATA(s_axi_pointer_basic_io_WDATA),
.s_axi_pointer_basic_io_WREADY(s_axi_pointer_basic_io_WREADY),
.s_axi_pointer_basic_io_WSTRB(s_axi_pointer_basic_io_WSTRB),
.s_axi_pointer_basic_io_WVALID(s_axi_pointer_basic_io_WVALID));
endmodule
(* C_S_AXI_DATA_WIDTH = "32" *) (* C_S_AXI_POINTER_BASIC_IO_ADDR_WIDTH = "5" *) (* C_S_AXI_POINTER_BASIC_IO_DATA_WIDTH = "32" *)
(* C_S_AXI_POINTER_BASIC_IO_WSTRB_WIDTH = "4" *) (* C_S_AXI_WSTRB_WIDTH = "4" *) (* ap_ST_fsm_state1 = "3'b001" *)
(* ap_ST_fsm_state2 = "3'b010" *) (* ap_ST_fsm_state3 = "3'b100" *) (* hls_module = "yes" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_pointer_basic
(ap_clk,
ap_rst_n,
s_axi_pointer_basic_io_AWVALID,
s_axi_pointer_basic_io_AWREADY,
s_axi_pointer_basic_io_AWADDR,
s_axi_pointer_basic_io_WVALID,
s_axi_pointer_basic_io_WREADY,
s_axi_pointer_basic_io_WDATA,
s_axi_pointer_basic_io_WSTRB,
s_axi_pointer_basic_io_ARVALID,
s_axi_pointer_basic_io_ARREADY,
s_axi_pointer_basic_io_ARADDR,
s_axi_pointer_basic_io_RVALID,
s_axi_pointer_basic_io_RREADY,
s_axi_pointer_basic_io_RDATA,
s_axi_pointer_basic_io_RRESP,
s_axi_pointer_basic_io_BVALID,
s_axi_pointer_basic_io_BREADY,
s_axi_pointer_basic_io_BRESP,
interrupt);
input ap_clk;
input ap_rst_n;
input s_axi_pointer_basic_io_AWVALID;
output s_axi_pointer_basic_io_AWREADY;
input [4:0]s_axi_pointer_basic_io_AWADDR;
input s_axi_pointer_basic_io_WVALID;
output s_axi_pointer_basic_io_WREADY;
input [31:0]s_axi_pointer_basic_io_WDATA;
input [3:0]s_axi_pointer_basic_io_WSTRB;
input s_axi_pointer_basic_io_ARVALID;
output s_axi_pointer_basic_io_ARREADY;
input [4:0]s_axi_pointer_basic_io_ARADDR;
output s_axi_pointer_basic_io_RVALID;
input s_axi_pointer_basic_io_RREADY;
output [31:0]s_axi_pointer_basic_io_RDATA;
output [1:0]s_axi_pointer_basic_io_RRESP;
output s_axi_pointer_basic_io_BVALID;
input s_axi_pointer_basic_io_BREADY;
output [1:0]s_axi_pointer_basic_io_BRESP;
output interrupt;
wire \<const0> ;
wire \acc[0]_i_2_n_0 ;
wire \acc[0]_i_3_n_0 ;
wire \acc[0]_i_4_n_0 ;
wire \acc[0]_i_5_n_0 ;
wire \acc[12]_i_2_n_0 ;
wire \acc[12]_i_3_n_0 ;
wire \acc[12]_i_4_n_0 ;
wire \acc[12]_i_5_n_0 ;
wire \acc[16]_i_2_n_0 ;
wire \acc[16]_i_3_n_0 ;
wire \acc[16]_i_4_n_0 ;
wire \acc[16]_i_5_n_0 ;
wire \acc[20]_i_2_n_0 ;
wire \acc[20]_i_3_n_0 ;
wire \acc[20]_i_4_n_0 ;
wire \acc[20]_i_5_n_0 ;
wire \acc[24]_i_2_n_0 ;
wire \acc[24]_i_3_n_0 ;
wire \acc[24]_i_4_n_0 ;
wire \acc[24]_i_5_n_0 ;
wire \acc[28]_i_2_n_0 ;
wire \acc[28]_i_3_n_0 ;
wire \acc[28]_i_4_n_0 ;
wire \acc[28]_i_5_n_0 ;
wire \acc[4]_i_2_n_0 ;
wire \acc[4]_i_3_n_0 ;
wire \acc[4]_i_4_n_0 ;
wire \acc[4]_i_5_n_0 ;
wire \acc[8]_i_2_n_0 ;
wire \acc[8]_i_3_n_0 ;
wire \acc[8]_i_4_n_0 ;
wire \acc[8]_i_5_n_0 ;
wire [31:0]acc_reg;
wire \acc_reg[0]_i_1_n_0 ;
wire \acc_reg[0]_i_1_n_1 ;
wire \acc_reg[0]_i_1_n_2 ;
wire \acc_reg[0]_i_1_n_3 ;
wire \acc_reg[0]_i_1_n_4 ;
wire \acc_reg[0]_i_1_n_5 ;
wire \acc_reg[0]_i_1_n_6 ;
wire \acc_reg[0]_i_1_n_7 ;
wire \acc_reg[12]_i_1_n_0 ;
wire \acc_reg[12]_i_1_n_1 ;
wire \acc_reg[12]_i_1_n_2 ;
wire \acc_reg[12]_i_1_n_3 ;
wire \acc_reg[12]_i_1_n_4 ;
wire \acc_reg[12]_i_1_n_5 ;
wire \acc_reg[12]_i_1_n_6 ;
wire \acc_reg[12]_i_1_n_7 ;
wire \acc_reg[16]_i_1_n_0 ;
wire \acc_reg[16]_i_1_n_1 ;
wire \acc_reg[16]_i_1_n_2 ;
wire \acc_reg[16]_i_1_n_3 ;
wire \acc_reg[16]_i_1_n_4 ;
wire \acc_reg[16]_i_1_n_5 ;
wire \acc_reg[16]_i_1_n_6 ;
wire \acc_reg[16]_i_1_n_7 ;
wire \acc_reg[20]_i_1_n_0 ;
wire \acc_reg[20]_i_1_n_1 ;
wire \acc_reg[20]_i_1_n_2 ;
wire \acc_reg[20]_i_1_n_3 ;
wire \acc_reg[20]_i_1_n_4 ;
wire \acc_reg[20]_i_1_n_5 ;
wire \acc_reg[20]_i_1_n_6 ;
wire \acc_reg[20]_i_1_n_7 ;
wire \acc_reg[24]_i_1_n_0 ;
wire \acc_reg[24]_i_1_n_1 ;
wire \acc_reg[24]_i_1_n_2 ;
wire \acc_reg[24]_i_1_n_3 ;
wire \acc_reg[24]_i_1_n_4 ;
wire \acc_reg[24]_i_1_n_5 ;
wire \acc_reg[24]_i_1_n_6 ;
wire \acc_reg[24]_i_1_n_7 ;
wire \acc_reg[28]_i_1_n_1 ;
wire \acc_reg[28]_i_1_n_2 ;
wire \acc_reg[28]_i_1_n_3 ;
wire \acc_reg[28]_i_1_n_4 ;
wire \acc_reg[28]_i_1_n_5 ;
wire \acc_reg[28]_i_1_n_6 ;
wire \acc_reg[28]_i_1_n_7 ;
wire \acc_reg[4]_i_1_n_0 ;
wire \acc_reg[4]_i_1_n_1 ;
wire \acc_reg[4]_i_1_n_2 ;
wire \acc_reg[4]_i_1_n_3 ;
wire \acc_reg[4]_i_1_n_4 ;
wire \acc_reg[4]_i_1_n_5 ;
wire \acc_reg[4]_i_1_n_6 ;
wire \acc_reg[4]_i_1_n_7 ;
wire \acc_reg[8]_i_1_n_0 ;
wire \acc_reg[8]_i_1_n_1 ;
wire \acc_reg[8]_i_1_n_2 ;
wire \acc_reg[8]_i_1_n_3 ;
wire \acc_reg[8]_i_1_n_4 ;
wire \acc_reg[8]_i_1_n_5 ;
wire \acc_reg[8]_i_1_n_6 ;
wire \acc_reg[8]_i_1_n_7 ;
wire \ap_CS_fsm_reg_n_0_[0] ;
wire ap_CS_fsm_state2;
wire ap_CS_fsm_state3;
wire [1:0]ap_NS_fsm;
wire ap_NS_fsm1;
wire ap_clk;
wire ap_rst_n;
wire ap_rst_n_inv;
wire [31:0]d_i;
wire [31:0]d_read_reg_52;
wire interrupt;
wire [4:0]s_axi_pointer_basic_io_ARADDR;
wire s_axi_pointer_basic_io_ARREADY;
wire s_axi_pointer_basic_io_ARVALID;
wire [4:0]s_axi_pointer_basic_io_AWADDR;
wire s_axi_pointer_basic_io_AWREADY;
wire s_axi_pointer_basic_io_AWVALID;
wire s_axi_pointer_basic_io_BREADY;
wire s_axi_pointer_basic_io_BVALID;
wire [31:0]s_axi_pointer_basic_io_RDATA;
wire s_axi_pointer_basic_io_RREADY;
wire s_axi_pointer_basic_io_RVALID;
wire [31:0]s_axi_pointer_basic_io_WDATA;
wire s_axi_pointer_basic_io_WREADY;
wire [3:0]s_axi_pointer_basic_io_WSTRB;
wire s_axi_pointer_basic_io_WVALID;
wire [3:3]\NLW_acc_reg[28]_i_1_CO_UNCONNECTED ;
assign s_axi_pointer_basic_io_BRESP[1] = \<const0> ;
assign s_axi_pointer_basic_io_BRESP[0] = \<const0> ;
assign s_axi_pointer_basic_io_RRESP[1] = \<const0> ;
assign s_axi_pointer_basic_io_RRESP[0] = \<const0> ;
GND GND
(.G(\<const0> ));
LUT2 #(
.INIT(4'h6))
\acc[0]_i_2
(.I0(d_read_reg_52[3]),
.I1(acc_reg[3]),
.O(\acc[0]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\acc[0]_i_3
(.I0(d_read_reg_52[2]),
.I1(acc_reg[2]),
.O(\acc[0]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\acc[0]_i_4
(.I0(d_read_reg_52[1]),
.I1(acc_reg[1]),
.O(\acc[0]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\acc[0]_i_5
(.I0(d_read_reg_52[0]),
.I1(acc_reg[0]),
.O(\acc[0]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\acc[12]_i_2
(.I0(d_read_reg_52[15]),
.I1(acc_reg[15]),
.O(\acc[12]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\acc[12]_i_3
(.I0(d_read_reg_52[14]),
.I1(acc_reg[14]),
.O(\acc[12]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\acc[12]_i_4
(.I0(d_read_reg_52[13]),
.I1(acc_reg[13]),
.O(\acc[12]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\acc[12]_i_5
(.I0(d_read_reg_52[12]),
.I1(acc_reg[12]),
.O(\acc[12]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\acc[16]_i_2
(.I0(d_read_reg_52[19]),
.I1(acc_reg[19]),
.O(\acc[16]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\acc[16]_i_3
(.I0(d_read_reg_52[18]),
.I1(acc_reg[18]),
.O(\acc[16]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\acc[16]_i_4
(.I0(d_read_reg_52[17]),
.I1(acc_reg[17]),
.O(\acc[16]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\acc[16]_i_5
(.I0(d_read_reg_52[16]),
.I1(acc_reg[16]),
.O(\acc[16]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\acc[20]_i_2
(.I0(d_read_reg_52[23]),
.I1(acc_reg[23]),
.O(\acc[20]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\acc[20]_i_3
(.I0(d_read_reg_52[22]),
.I1(acc_reg[22]),
.O(\acc[20]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\acc[20]_i_4
(.I0(d_read_reg_52[21]),
.I1(acc_reg[21]),
.O(\acc[20]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\acc[20]_i_5
(.I0(d_read_reg_52[20]),
.I1(acc_reg[20]),
.O(\acc[20]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\acc[24]_i_2
(.I0(d_read_reg_52[27]),
.I1(acc_reg[27]),
.O(\acc[24]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\acc[24]_i_3
(.I0(d_read_reg_52[26]),
.I1(acc_reg[26]),
.O(\acc[24]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\acc[24]_i_4
(.I0(d_read_reg_52[25]),
.I1(acc_reg[25]),
.O(\acc[24]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\acc[24]_i_5
(.I0(d_read_reg_52[24]),
.I1(acc_reg[24]),
.O(\acc[24]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\acc[28]_i_2
(.I0(acc_reg[31]),
.I1(d_read_reg_52[31]),
.O(\acc[28]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\acc[28]_i_3
(.I0(d_read_reg_52[30]),
.I1(acc_reg[30]),
.O(\acc[28]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\acc[28]_i_4
(.I0(d_read_reg_52[29]),
.I1(acc_reg[29]),
.O(\acc[28]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\acc[28]_i_5
(.I0(d_read_reg_52[28]),
.I1(acc_reg[28]),
.O(\acc[28]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\acc[4]_i_2
(.I0(d_read_reg_52[7]),
.I1(acc_reg[7]),
.O(\acc[4]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\acc[4]_i_3
(.I0(d_read_reg_52[6]),
.I1(acc_reg[6]),
.O(\acc[4]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\acc[4]_i_4
(.I0(d_read_reg_52[5]),
.I1(acc_reg[5]),
.O(\acc[4]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\acc[4]_i_5
(.I0(d_read_reg_52[4]),
.I1(acc_reg[4]),
.O(\acc[4]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\acc[8]_i_2
(.I0(d_read_reg_52[11]),
.I1(acc_reg[11]),
.O(\acc[8]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\acc[8]_i_3
(.I0(d_read_reg_52[10]),
.I1(acc_reg[10]),
.O(\acc[8]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\acc[8]_i_4
(.I0(d_read_reg_52[9]),
.I1(acc_reg[9]),
.O(\acc[8]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\acc[8]_i_5
(.I0(d_read_reg_52[8]),
.I1(acc_reg[8]),
.O(\acc[8]_i_5_n_0 ));
FDRE #(
.INIT(1'b0))
\acc_reg[0]
(.C(ap_clk),
.CE(ap_CS_fsm_state2),
.D(\acc_reg[0]_i_1_n_7 ),
.Q(acc_reg[0]),
.R(1'b0));
CARRY4 \acc_reg[0]_i_1
(.CI(1'b0),
.CO({\acc_reg[0]_i_1_n_0 ,\acc_reg[0]_i_1_n_1 ,\acc_reg[0]_i_1_n_2 ,\acc_reg[0]_i_1_n_3 }),
.CYINIT(1'b0),
.DI(d_read_reg_52[3:0]),
.O({\acc_reg[0]_i_1_n_4 ,\acc_reg[0]_i_1_n_5 ,\acc_reg[0]_i_1_n_6 ,\acc_reg[0]_i_1_n_7 }),
.S({\acc[0]_i_2_n_0 ,\acc[0]_i_3_n_0 ,\acc[0]_i_4_n_0 ,\acc[0]_i_5_n_0 }));
FDRE #(
.INIT(1'b0))
\acc_reg[10]
(.C(ap_clk),
.CE(ap_CS_fsm_state2),
.D(\acc_reg[8]_i_1_n_5 ),
.Q(acc_reg[10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\acc_reg[11]
(.C(ap_clk),
.CE(ap_CS_fsm_state2),
.D(\acc_reg[8]_i_1_n_4 ),
.Q(acc_reg[11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\acc_reg[12]
(.C(ap_clk),
.CE(ap_CS_fsm_state2),
.D(\acc_reg[12]_i_1_n_7 ),
.Q(acc_reg[12]),
.R(1'b0));
CARRY4 \acc_reg[12]_i_1
(.CI(\acc_reg[8]_i_1_n_0 ),
.CO({\acc_reg[12]_i_1_n_0 ,\acc_reg[12]_i_1_n_1 ,\acc_reg[12]_i_1_n_2 ,\acc_reg[12]_i_1_n_3 }),
.CYINIT(1'b0),
.DI(d_read_reg_52[15:12]),
.O({\acc_reg[12]_i_1_n_4 ,\acc_reg[12]_i_1_n_5 ,\acc_reg[12]_i_1_n_6 ,\acc_reg[12]_i_1_n_7 }),
.S({\acc[12]_i_2_n_0 ,\acc[12]_i_3_n_0 ,\acc[12]_i_4_n_0 ,\acc[12]_i_5_n_0 }));
FDRE #(
.INIT(1'b0))
\acc_reg[13]
(.C(ap_clk),
.CE(ap_CS_fsm_state2),
.D(\acc_reg[12]_i_1_n_6 ),
.Q(acc_reg[13]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\acc_reg[14]
(.C(ap_clk),
.CE(ap_CS_fsm_state2),
.D(\acc_reg[12]_i_1_n_5 ),
.Q(acc_reg[14]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\acc_reg[15]
(.C(ap_clk),
.CE(ap_CS_fsm_state2),
.D(\acc_reg[12]_i_1_n_4 ),
.Q(acc_reg[15]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\acc_reg[16]
(.C(ap_clk),
.CE(ap_CS_fsm_state2),
.D(\acc_reg[16]_i_1_n_7 ),
.Q(acc_reg[16]),
.R(1'b0));
CARRY4 \acc_reg[16]_i_1
(.CI(\acc_reg[12]_i_1_n_0 ),
.CO({\acc_reg[16]_i_1_n_0 ,\acc_reg[16]_i_1_n_1 ,\acc_reg[16]_i_1_n_2 ,\acc_reg[16]_i_1_n_3 }),
.CYINIT(1'b0),
.DI(d_read_reg_52[19:16]),
.O({\acc_reg[16]_i_1_n_4 ,\acc_reg[16]_i_1_n_5 ,\acc_reg[16]_i_1_n_6 ,\acc_reg[16]_i_1_n_7 }),
.S({\acc[16]_i_2_n_0 ,\acc[16]_i_3_n_0 ,\acc[16]_i_4_n_0 ,\acc[16]_i_5_n_0 }));
FDRE #(
.INIT(1'b0))
\acc_reg[17]
(.C(ap_clk),
.CE(ap_CS_fsm_state2),
.D(\acc_reg[16]_i_1_n_6 ),
.Q(acc_reg[17]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\acc_reg[18]
(.C(ap_clk),
.CE(ap_CS_fsm_state2),
.D(\acc_reg[16]_i_1_n_5 ),
.Q(acc_reg[18]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\acc_reg[19]
(.C(ap_clk),
.CE(ap_CS_fsm_state2),
.D(\acc_reg[16]_i_1_n_4 ),
.Q(acc_reg[19]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\acc_reg[1]
(.C(ap_clk),
.CE(ap_CS_fsm_state2),
.D(\acc_reg[0]_i_1_n_6 ),
.Q(acc_reg[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\acc_reg[20]
(.C(ap_clk),
.CE(ap_CS_fsm_state2),
.D(\acc_reg[20]_i_1_n_7 ),
.Q(acc_reg[20]),
.R(1'b0));
CARRY4 \acc_reg[20]_i_1
(.CI(\acc_reg[16]_i_1_n_0 ),
.CO({\acc_reg[20]_i_1_n_0 ,\acc_reg[20]_i_1_n_1 ,\acc_reg[20]_i_1_n_2 ,\acc_reg[20]_i_1_n_3 }),
.CYINIT(1'b0),
.DI(d_read_reg_52[23:20]),
.O({\acc_reg[20]_i_1_n_4 ,\acc_reg[20]_i_1_n_5 ,\acc_reg[20]_i_1_n_6 ,\acc_reg[20]_i_1_n_7 }),
.S({\acc[20]_i_2_n_0 ,\acc[20]_i_3_n_0 ,\acc[20]_i_4_n_0 ,\acc[20]_i_5_n_0 }));
FDRE #(
.INIT(1'b0))
\acc_reg[21]
(.C(ap_clk),
.CE(ap_CS_fsm_state2),
.D(\acc_reg[20]_i_1_n_6 ),
.Q(acc_reg[21]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\acc_reg[22]
(.C(ap_clk),
.CE(ap_CS_fsm_state2),
.D(\acc_reg[20]_i_1_n_5 ),
.Q(acc_reg[22]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\acc_reg[23]
(.C(ap_clk),
.CE(ap_CS_fsm_state2),
.D(\acc_reg[20]_i_1_n_4 ),
.Q(acc_reg[23]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\acc_reg[24]
(.C(ap_clk),
.CE(ap_CS_fsm_state2),
.D(\acc_reg[24]_i_1_n_7 ),
.Q(acc_reg[24]),
.R(1'b0));
CARRY4 \acc_reg[24]_i_1
(.CI(\acc_reg[20]_i_1_n_0 ),
.CO({\acc_reg[24]_i_1_n_0 ,\acc_reg[24]_i_1_n_1 ,\acc_reg[24]_i_1_n_2 ,\acc_reg[24]_i_1_n_3 }),
.CYINIT(1'b0),
.DI(d_read_reg_52[27:24]),
.O({\acc_reg[24]_i_1_n_4 ,\acc_reg[24]_i_1_n_5 ,\acc_reg[24]_i_1_n_6 ,\acc_reg[24]_i_1_n_7 }),
.S({\acc[24]_i_2_n_0 ,\acc[24]_i_3_n_0 ,\acc[24]_i_4_n_0 ,\acc[24]_i_5_n_0 }));
FDRE #(
.INIT(1'b0))
\acc_reg[25]
(.C(ap_clk),
.CE(ap_CS_fsm_state2),
.D(\acc_reg[24]_i_1_n_6 ),
.Q(acc_reg[25]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\acc_reg[26]
(.C(ap_clk),
.CE(ap_CS_fsm_state2),
.D(\acc_reg[24]_i_1_n_5 ),
.Q(acc_reg[26]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\acc_reg[27]
(.C(ap_clk),
.CE(ap_CS_fsm_state2),
.D(\acc_reg[24]_i_1_n_4 ),
.Q(acc_reg[27]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\acc_reg[28]
(.C(ap_clk),
.CE(ap_CS_fsm_state2),
.D(\acc_reg[28]_i_1_n_7 ),
.Q(acc_reg[28]),
.R(1'b0));
CARRY4 \acc_reg[28]_i_1
(.CI(\acc_reg[24]_i_1_n_0 ),
.CO({\NLW_acc_reg[28]_i_1_CO_UNCONNECTED [3],\acc_reg[28]_i_1_n_1 ,\acc_reg[28]_i_1_n_2 ,\acc_reg[28]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,d_read_reg_52[30:28]}),
.O({\acc_reg[28]_i_1_n_4 ,\acc_reg[28]_i_1_n_5 ,\acc_reg[28]_i_1_n_6 ,\acc_reg[28]_i_1_n_7 }),
.S({\acc[28]_i_2_n_0 ,\acc[28]_i_3_n_0 ,\acc[28]_i_4_n_0 ,\acc[28]_i_5_n_0 }));
FDRE #(
.INIT(1'b0))
\acc_reg[29]
(.C(ap_clk),
.CE(ap_CS_fsm_state2),
.D(\acc_reg[28]_i_1_n_6 ),
.Q(acc_reg[29]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\acc_reg[2]
(.C(ap_clk),
.CE(ap_CS_fsm_state2),
.D(\acc_reg[0]_i_1_n_5 ),
.Q(acc_reg[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\acc_reg[30]
(.C(ap_clk),
.CE(ap_CS_fsm_state2),
.D(\acc_reg[28]_i_1_n_5 ),
.Q(acc_reg[30]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\acc_reg[31]
(.C(ap_clk),
.CE(ap_CS_fsm_state2),
.D(\acc_reg[28]_i_1_n_4 ),
.Q(acc_reg[31]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\acc_reg[3]
(.C(ap_clk),
.CE(ap_CS_fsm_state2),
.D(\acc_reg[0]_i_1_n_4 ),
.Q(acc_reg[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\acc_reg[4]
(.C(ap_clk),
.CE(ap_CS_fsm_state2),
.D(\acc_reg[4]_i_1_n_7 ),
.Q(acc_reg[4]),
.R(1'b0));
CARRY4 \acc_reg[4]_i_1
(.CI(\acc_reg[0]_i_1_n_0 ),
.CO({\acc_reg[4]_i_1_n_0 ,\acc_reg[4]_i_1_n_1 ,\acc_reg[4]_i_1_n_2 ,\acc_reg[4]_i_1_n_3 }),
.CYINIT(1'b0),
.DI(d_read_reg_52[7:4]),
.O({\acc_reg[4]_i_1_n_4 ,\acc_reg[4]_i_1_n_5 ,\acc_reg[4]_i_1_n_6 ,\acc_reg[4]_i_1_n_7 }),
.S({\acc[4]_i_2_n_0 ,\acc[4]_i_3_n_0 ,\acc[4]_i_4_n_0 ,\acc[4]_i_5_n_0 }));
FDRE #(
.INIT(1'b0))
\acc_reg[5]
(.C(ap_clk),
.CE(ap_CS_fsm_state2),
.D(\acc_reg[4]_i_1_n_6 ),
.Q(acc_reg[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\acc_reg[6]
(.C(ap_clk),
.CE(ap_CS_fsm_state2),
.D(\acc_reg[4]_i_1_n_5 ),
.Q(acc_reg[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\acc_reg[7]
(.C(ap_clk),
.CE(ap_CS_fsm_state2),
.D(\acc_reg[4]_i_1_n_4 ),
.Q(acc_reg[7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\acc_reg[8]
(.C(ap_clk),
.CE(ap_CS_fsm_state2),
.D(\acc_reg[8]_i_1_n_7 ),
.Q(acc_reg[8]),
.R(1'b0));
CARRY4 \acc_reg[8]_i_1
(.CI(\acc_reg[4]_i_1_n_0 ),
.CO({\acc_reg[8]_i_1_n_0 ,\acc_reg[8]_i_1_n_1 ,\acc_reg[8]_i_1_n_2 ,\acc_reg[8]_i_1_n_3 }),
.CYINIT(1'b0),
.DI(d_read_reg_52[11:8]),
.O({\acc_reg[8]_i_1_n_4 ,\acc_reg[8]_i_1_n_5 ,\acc_reg[8]_i_1_n_6 ,\acc_reg[8]_i_1_n_7 }),
.S({\acc[8]_i_2_n_0 ,\acc[8]_i_3_n_0 ,\acc[8]_i_4_n_0 ,\acc[8]_i_5_n_0 }));
FDRE #(
.INIT(1'b0))
\acc_reg[9]
(.C(ap_clk),
.CE(ap_CS_fsm_state2),
.D(\acc_reg[8]_i_1_n_6 ),
.Q(acc_reg[9]),
.R(1'b0));
(* FSM_ENCODING = "none" *)
FDSE #(
.INIT(1'b1))
\ap_CS_fsm_reg[0]
(.C(ap_clk),
.CE(1'b1),
.D(ap_NS_fsm[0]),
.Q(\ap_CS_fsm_reg_n_0_[0] ),
.S(ap_rst_n_inv));
(* FSM_ENCODING = "none" *)
FDRE #(
.INIT(1'b0))
\ap_CS_fsm_reg[1]
(.C(ap_clk),
.CE(1'b1),
.D(ap_NS_fsm[1]),
.Q(ap_CS_fsm_state2),
.R(ap_rst_n_inv));
(* FSM_ENCODING = "none" *)
FDRE #(
.INIT(1'b0))
\ap_CS_fsm_reg[2]
(.C(ap_clk),
.CE(1'b1),
.D(ap_CS_fsm_state2),
.Q(ap_CS_fsm_state3),
.R(ap_rst_n_inv));
FDRE \d_read_reg_52_reg[0]
(.C(ap_clk),
.CE(ap_NS_fsm1),
.D(d_i[0]),
.Q(d_read_reg_52[0]),
.R(1'b0));
FDRE \d_read_reg_52_reg[10]
(.C(ap_clk),
.CE(ap_NS_fsm1),
.D(d_i[10]),
.Q(d_read_reg_52[10]),
.R(1'b0));
FDRE \d_read_reg_52_reg[11]
(.C(ap_clk),
.CE(ap_NS_fsm1),
.D(d_i[11]),
.Q(d_read_reg_52[11]),
.R(1'b0));
FDRE \d_read_reg_52_reg[12]
(.C(ap_clk),
.CE(ap_NS_fsm1),
.D(d_i[12]),
.Q(d_read_reg_52[12]),
.R(1'b0));
FDRE \d_read_reg_52_reg[13]
(.C(ap_clk),
.CE(ap_NS_fsm1),
.D(d_i[13]),
.Q(d_read_reg_52[13]),
.R(1'b0));
FDRE \d_read_reg_52_reg[14]
(.C(ap_clk),
.CE(ap_NS_fsm1),
.D(d_i[14]),
.Q(d_read_reg_52[14]),
.R(1'b0));
FDRE \d_read_reg_52_reg[15]
(.C(ap_clk),
.CE(ap_NS_fsm1),
.D(d_i[15]),
.Q(d_read_reg_52[15]),
.R(1'b0));
FDRE \d_read_reg_52_reg[16]
(.C(ap_clk),
.CE(ap_NS_fsm1),
.D(d_i[16]),
.Q(d_read_reg_52[16]),
.R(1'b0));
FDRE \d_read_reg_52_reg[17]
(.C(ap_clk),
.CE(ap_NS_fsm1),
.D(d_i[17]),
.Q(d_read_reg_52[17]),
.R(1'b0));
FDRE \d_read_reg_52_reg[18]
(.C(ap_clk),
.CE(ap_NS_fsm1),
.D(d_i[18]),
.Q(d_read_reg_52[18]),
.R(1'b0));
FDRE \d_read_reg_52_reg[19]
(.C(ap_clk),
.CE(ap_NS_fsm1),
.D(d_i[19]),
.Q(d_read_reg_52[19]),
.R(1'b0));
FDRE \d_read_reg_52_reg[1]
(.C(ap_clk),
.CE(ap_NS_fsm1),
.D(d_i[1]),
.Q(d_read_reg_52[1]),
.R(1'b0));
FDRE \d_read_reg_52_reg[20]
(.C(ap_clk),
.CE(ap_NS_fsm1),
.D(d_i[20]),
.Q(d_read_reg_52[20]),
.R(1'b0));
FDRE \d_read_reg_52_reg[21]
(.C(ap_clk),
.CE(ap_NS_fsm1),
.D(d_i[21]),
.Q(d_read_reg_52[21]),
.R(1'b0));
FDRE \d_read_reg_52_reg[22]
(.C(ap_clk),
.CE(ap_NS_fsm1),
.D(d_i[22]),
.Q(d_read_reg_52[22]),
.R(1'b0));
FDRE \d_read_reg_52_reg[23]
(.C(ap_clk),
.CE(ap_NS_fsm1),
.D(d_i[23]),
.Q(d_read_reg_52[23]),
.R(1'b0));
FDRE \d_read_reg_52_reg[24]
(.C(ap_clk),
.CE(ap_NS_fsm1),
.D(d_i[24]),
.Q(d_read_reg_52[24]),
.R(1'b0));
FDRE \d_read_reg_52_reg[25]
(.C(ap_clk),
.CE(ap_NS_fsm1),
.D(d_i[25]),
.Q(d_read_reg_52[25]),
.R(1'b0));
FDRE \d_read_reg_52_reg[26]
(.C(ap_clk),
.CE(ap_NS_fsm1),
.D(d_i[26]),
.Q(d_read_reg_52[26]),
.R(1'b0));
FDRE \d_read_reg_52_reg[27]
(.C(ap_clk),
.CE(ap_NS_fsm1),
.D(d_i[27]),
.Q(d_read_reg_52[27]),
.R(1'b0));
FDRE \d_read_reg_52_reg[28]
(.C(ap_clk),
.CE(ap_NS_fsm1),
.D(d_i[28]),
.Q(d_read_reg_52[28]),
.R(1'b0));
FDRE \d_read_reg_52_reg[29]
(.C(ap_clk),
.CE(ap_NS_fsm1),
.D(d_i[29]),
.Q(d_read_reg_52[29]),
.R(1'b0));
FDRE \d_read_reg_52_reg[2]
(.C(ap_clk),
.CE(ap_NS_fsm1),
.D(d_i[2]),
.Q(d_read_reg_52[2]),
.R(1'b0));
FDRE \d_read_reg_52_reg[30]
(.C(ap_clk),
.CE(ap_NS_fsm1),
.D(d_i[30]),
.Q(d_read_reg_52[30]),
.R(1'b0));
FDRE \d_read_reg_52_reg[31]
(.C(ap_clk),
.CE(ap_NS_fsm1),
.D(d_i[31]),
.Q(d_read_reg_52[31]),
.R(1'b0));
FDRE \d_read_reg_52_reg[3]
(.C(ap_clk),
.CE(ap_NS_fsm1),
.D(d_i[3]),
.Q(d_read_reg_52[3]),
.R(1'b0));
FDRE \d_read_reg_52_reg[4]
(.C(ap_clk),
.CE(ap_NS_fsm1),
.D(d_i[4]),
.Q(d_read_reg_52[4]),
.R(1'b0));
FDRE \d_read_reg_52_reg[5]
(.C(ap_clk),
.CE(ap_NS_fsm1),
.D(d_i[5]),
.Q(d_read_reg_52[5]),
.R(1'b0));
FDRE \d_read_reg_52_reg[6]
(.C(ap_clk),
.CE(ap_NS_fsm1),
.D(d_i[6]),
.Q(d_read_reg_52[6]),
.R(1'b0));
FDRE \d_read_reg_52_reg[7]
(.C(ap_clk),
.CE(ap_NS_fsm1),
.D(d_i[7]),
.Q(d_read_reg_52[7]),
.R(1'b0));
FDRE \d_read_reg_52_reg[8]
(.C(ap_clk),
.CE(ap_NS_fsm1),
.D(d_i[8]),
.Q(d_read_reg_52[8]),
.R(1'b0));
FDRE \d_read_reg_52_reg[9]
(.C(ap_clk),
.CE(ap_NS_fsm1),
.D(d_i[9]),
.Q(d_read_reg_52[9]),
.R(1'b0));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_pointer_basic_pointer_basic_io_s_axi pointer_basic_pointer_basic_io_s_axi_U
(.D(acc_reg),
.E(ap_NS_fsm1),
.Q({ap_CS_fsm_state3,ap_CS_fsm_state2,\ap_CS_fsm_reg_n_0_[0] }),
.SR(ap_rst_n_inv),
.\ap_CS_fsm_reg[1] (ap_NS_fsm),
.ap_clk(ap_clk),
.ap_rst_n(ap_rst_n),
.\d_read_reg_52_reg[31] (d_i),
.interrupt(interrupt),
.out({s_axi_pointer_basic_io_BVALID,s_axi_pointer_basic_io_WREADY,s_axi_pointer_basic_io_AWREADY}),
.s_axi_pointer_basic_io_ARADDR(s_axi_pointer_basic_io_ARADDR),
.s_axi_pointer_basic_io_ARVALID(s_axi_pointer_basic_io_ARVALID),
.s_axi_pointer_basic_io_AWADDR(s_axi_pointer_basic_io_AWADDR),
.s_axi_pointer_basic_io_AWVALID(s_axi_pointer_basic_io_AWVALID),
.s_axi_pointer_basic_io_BREADY(s_axi_pointer_basic_io_BREADY),
.s_axi_pointer_basic_io_RDATA(s_axi_pointer_basic_io_RDATA),
.s_axi_pointer_basic_io_RREADY(s_axi_pointer_basic_io_RREADY),
.s_axi_pointer_basic_io_RVALID({s_axi_pointer_basic_io_RVALID,s_axi_pointer_basic_io_ARREADY}),
.s_axi_pointer_basic_io_WDATA(s_axi_pointer_basic_io_WDATA),
.s_axi_pointer_basic_io_WSTRB(s_axi_pointer_basic_io_WSTRB),
.s_axi_pointer_basic_io_WVALID(s_axi_pointer_basic_io_WVALID));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_pointer_basic_pointer_basic_io_s_axi
(out,
s_axi_pointer_basic_io_RVALID,
SR,
\d_read_reg_52_reg[31] ,
s_axi_pointer_basic_io_RDATA,
interrupt,
\ap_CS_fsm_reg[1] ,
E,
ap_clk,
Q,
ap_rst_n,
s_axi_pointer_basic_io_WDATA,
s_axi_pointer_basic_io_WSTRB,
s_axi_pointer_basic_io_ARADDR,
s_axi_pointer_basic_io_AWADDR,
D,
s_axi_pointer_basic_io_ARVALID,
s_axi_pointer_basic_io_RREADY,
s_axi_pointer_basic_io_AWVALID,
s_axi_pointer_basic_io_WVALID,
s_axi_pointer_basic_io_BREADY);
output [2:0]out;
output [1:0]s_axi_pointer_basic_io_RVALID;
output [0:0]SR;
output [31:0]\d_read_reg_52_reg[31] ;
output [31:0]s_axi_pointer_basic_io_RDATA;
output interrupt;
output [1:0]\ap_CS_fsm_reg[1] ;
output [0:0]E;
input ap_clk;
input [2:0]Q;
input ap_rst_n;
input [31:0]s_axi_pointer_basic_io_WDATA;
input [3:0]s_axi_pointer_basic_io_WSTRB;
input [4:0]s_axi_pointer_basic_io_ARADDR;
input [4:0]s_axi_pointer_basic_io_AWADDR;
input [31:0]D;
input s_axi_pointer_basic_io_ARVALID;
input s_axi_pointer_basic_io_RREADY;
input s_axi_pointer_basic_io_AWVALID;
input s_axi_pointer_basic_io_WVALID;
input s_axi_pointer_basic_io_BREADY;
wire [31:0]D;
wire [0:0]E;
wire \FSM_onehot_rstate[1]_i_1_n_0 ;
wire \FSM_onehot_rstate[2]_i_1_n_0 ;
(* RTL_KEEP = "yes" *) wire \FSM_onehot_rstate_reg_n_0_[0] ;
wire \FSM_onehot_wstate[1]_i_1_n_0 ;
wire \FSM_onehot_wstate[2]_i_1_n_0 ;
wire \FSM_onehot_wstate[3]_i_2_n_0 ;
(* RTL_KEEP = "yes" *) wire \FSM_onehot_wstate_reg_n_0_[0] ;
wire [2:0]Q;
wire [0:0]SR;
wire [1:0]\ap_CS_fsm_reg[1] ;
wire ap_clk;
wire ap_idle;
wire ap_rst_n;
wire ap_start;
wire ar_hs;
wire [31:0]\d_read_reg_52_reg[31] ;
wire int_ap_done;
wire int_ap_done_i_1_n_0;
wire int_ap_done_i_2_n_0;
wire int_ap_idle;
wire int_ap_ready;
wire int_ap_start_i_1_n_0;
wire int_ap_start_i_2_n_0;
wire int_ap_start_i_3_n_0;
wire int_auto_restart;
wire int_auto_restart_i_1_n_0;
wire \int_d_i[0]_i_1_n_0 ;
wire \int_d_i[10]_i_1_n_0 ;
wire \int_d_i[11]_i_1_n_0 ;
wire \int_d_i[12]_i_1_n_0 ;
wire \int_d_i[13]_i_1_n_0 ;
wire \int_d_i[14]_i_1_n_0 ;
wire \int_d_i[15]_i_1_n_0 ;
wire \int_d_i[16]_i_1_n_0 ;
wire \int_d_i[17]_i_1_n_0 ;
wire \int_d_i[18]_i_1_n_0 ;
wire \int_d_i[19]_i_1_n_0 ;
wire \int_d_i[1]_i_1_n_0 ;
wire \int_d_i[20]_i_1_n_0 ;
wire \int_d_i[21]_i_1_n_0 ;
wire \int_d_i[22]_i_1_n_0 ;
wire \int_d_i[23]_i_1_n_0 ;
wire \int_d_i[24]_i_1_n_0 ;
wire \int_d_i[25]_i_1_n_0 ;
wire \int_d_i[26]_i_1_n_0 ;
wire \int_d_i[27]_i_1_n_0 ;
wire \int_d_i[28]_i_1_n_0 ;
wire \int_d_i[29]_i_1_n_0 ;
wire \int_d_i[2]_i_1_n_0 ;
wire \int_d_i[30]_i_1_n_0 ;
wire \int_d_i[31]_i_1_n_0 ;
wire \int_d_i[31]_i_2_n_0 ;
wire \int_d_i[31]_i_3_n_0 ;
wire \int_d_i[3]_i_1_n_0 ;
wire \int_d_i[4]_i_1_n_0 ;
wire \int_d_i[5]_i_1_n_0 ;
wire \int_d_i[6]_i_1_n_0 ;
wire \int_d_i[7]_i_1_n_0 ;
wire \int_d_i[8]_i_1_n_0 ;
wire \int_d_i[9]_i_1_n_0 ;
wire [31:0]int_d_o;
wire int_d_o_ap_vld;
wire int_d_o_ap_vld_i_1_n_0;
wire int_gie_i_1_n_0;
wire int_gie_reg_n_0;
wire \int_ier[0]_i_1_n_0 ;
wire \int_ier[1]_i_1_n_0 ;
wire \int_ier[1]_i_2_n_0 ;
wire \int_ier_reg_n_0_[0] ;
wire \int_ier_reg_n_0_[1] ;
wire int_isr;
wire int_isr7_out;
wire \int_isr[0]_i_1_n_0 ;
wire \int_isr[1]_i_1_n_0 ;
wire \int_isr_reg_n_0_[0] ;
wire interrupt;
(* RTL_KEEP = "yes" *) wire [2:0]out;
wire p_1_in;
wire [7:0]rdata;
wire \rdata[0]_i_2_n_0 ;
wire \rdata[0]_i_3_n_0 ;
wire \rdata[10]_i_1_n_0 ;
wire \rdata[11]_i_1_n_0 ;
wire \rdata[12]_i_1_n_0 ;
wire \rdata[13]_i_1_n_0 ;
wire \rdata[14]_i_1_n_0 ;
wire \rdata[15]_i_1_n_0 ;
wire \rdata[16]_i_1_n_0 ;
wire \rdata[17]_i_1_n_0 ;
wire \rdata[18]_i_1_n_0 ;
wire \rdata[19]_i_1_n_0 ;
wire \rdata[1]_i_2_n_0 ;
wire \rdata[1]_i_3_n_0 ;
wire \rdata[1]_i_4_n_0 ;
wire \rdata[20]_i_1_n_0 ;
wire \rdata[21]_i_1_n_0 ;
wire \rdata[22]_i_1_n_0 ;
wire \rdata[23]_i_1_n_0 ;
wire \rdata[24]_i_1_n_0 ;
wire \rdata[25]_i_1_n_0 ;
wire \rdata[26]_i_1_n_0 ;
wire \rdata[27]_i_1_n_0 ;
wire \rdata[28]_i_1_n_0 ;
wire \rdata[29]_i_1_n_0 ;
wire \rdata[30]_i_1_n_0 ;
wire \rdata[31]_i_1_n_0 ;
wire \rdata[31]_i_3_n_0 ;
wire \rdata[4]_i_1_n_0 ;
wire \rdata[5]_i_1_n_0 ;
wire \rdata[6]_i_1_n_0 ;
wire \rdata[7]_i_2_n_0 ;
wire \rdata[7]_i_3_n_0 ;
wire \rdata[8]_i_1_n_0 ;
wire \rdata[9]_i_1_n_0 ;
wire [4:0]s_axi_pointer_basic_io_ARADDR;
wire s_axi_pointer_basic_io_ARVALID;
wire [4:0]s_axi_pointer_basic_io_AWADDR;
wire s_axi_pointer_basic_io_AWVALID;
wire s_axi_pointer_basic_io_BREADY;
wire [31:0]s_axi_pointer_basic_io_RDATA;
wire s_axi_pointer_basic_io_RREADY;
(* RTL_KEEP = "yes" *) wire [1:0]s_axi_pointer_basic_io_RVALID;
wire [31:0]s_axi_pointer_basic_io_WDATA;
wire [3:0]s_axi_pointer_basic_io_WSTRB;
wire s_axi_pointer_basic_io_WVALID;
wire waddr;
wire \waddr_reg_n_0_[0] ;
wire \waddr_reg_n_0_[1] ;
wire \waddr_reg_n_0_[2] ;
wire \waddr_reg_n_0_[3] ;
wire \waddr_reg_n_0_[4] ;
LUT4 #(
.INIT(16'h8BFB))
\FSM_onehot_rstate[1]_i_1
(.I0(s_axi_pointer_basic_io_RREADY),
.I1(s_axi_pointer_basic_io_RVALID[1]),
.I2(s_axi_pointer_basic_io_RVALID[0]),
.I3(s_axi_pointer_basic_io_ARVALID),
.O(\FSM_onehot_rstate[1]_i_1_n_0 ));
LUT4 #(
.INIT(16'h8F88))
\FSM_onehot_rstate[2]_i_1
(.I0(s_axi_pointer_basic_io_ARVALID),
.I1(s_axi_pointer_basic_io_RVALID[0]),
.I2(s_axi_pointer_basic_io_RREADY),
.I3(s_axi_pointer_basic_io_RVALID[1]),
.O(\FSM_onehot_rstate[2]_i_1_n_0 ));
(* FSM_ENCODED_STATES = "RDIDLE:010,RDDATA:100,iSTATE:001" *)
(* KEEP = "yes" *)
FDSE #(
.INIT(1'b1))
\FSM_onehot_rstate_reg[0]
(.C(ap_clk),
.CE(1'b1),
.D(1'b0),
.Q(\FSM_onehot_rstate_reg_n_0_[0] ),
.S(SR));
(* FSM_ENCODED_STATES = "RDIDLE:010,RDDATA:100,iSTATE:001" *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\FSM_onehot_rstate_reg[1]
(.C(ap_clk),
.CE(1'b1),
.D(\FSM_onehot_rstate[1]_i_1_n_0 ),
.Q(s_axi_pointer_basic_io_RVALID[0]),
.R(SR));
(* FSM_ENCODED_STATES = "RDIDLE:010,RDDATA:100,iSTATE:001" *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\FSM_onehot_rstate_reg[2]
(.C(ap_clk),
.CE(1'b1),
.D(\FSM_onehot_rstate[2]_i_1_n_0 ),
.Q(s_axi_pointer_basic_io_RVALID[1]),
.R(SR));
LUT5 #(
.INIT(32'hFF272227))
\FSM_onehot_wstate[1]_i_1
(.I0(out[0]),
.I1(s_axi_pointer_basic_io_AWVALID),
.I2(out[1]),
.I3(out[2]),
.I4(s_axi_pointer_basic_io_BREADY),
.O(\FSM_onehot_wstate[1]_i_1_n_0 ));
LUT4 #(
.INIT(16'h8F88))
\FSM_onehot_wstate[2]_i_1
(.I0(s_axi_pointer_basic_io_AWVALID),
.I1(out[0]),
.I2(s_axi_pointer_basic_io_WVALID),
.I3(out[1]),
.O(\FSM_onehot_wstate[2]_i_1_n_0 ));
LUT1 #(
.INIT(2'h1))
\FSM_onehot_wstate[3]_i_1
(.I0(ap_rst_n),
.O(SR));
LUT4 #(
.INIT(16'h8F88))
\FSM_onehot_wstate[3]_i_2
(.I0(s_axi_pointer_basic_io_WVALID),
.I1(out[1]),
.I2(s_axi_pointer_basic_io_BREADY),
.I3(out[2]),
.O(\FSM_onehot_wstate[3]_i_2_n_0 ));
(* FSM_ENCODED_STATES = "WRDATA:0100,WRRESP:1000,WRIDLE:0010,iSTATE:0001" *)
(* KEEP = "yes" *)
FDSE #(
.INIT(1'b1))
\FSM_onehot_wstate_reg[0]
(.C(ap_clk),
.CE(1'b1),
.D(1'b0),
.Q(\FSM_onehot_wstate_reg_n_0_[0] ),
.S(SR));
(* FSM_ENCODED_STATES = "WRDATA:0100,WRRESP:1000,WRIDLE:0010,iSTATE:0001" *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\FSM_onehot_wstate_reg[1]
(.C(ap_clk),
.CE(1'b1),
.D(\FSM_onehot_wstate[1]_i_1_n_0 ),
.Q(out[0]),
.R(SR));
(* FSM_ENCODED_STATES = "WRDATA:0100,WRRESP:1000,WRIDLE:0010,iSTATE:0001" *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\FSM_onehot_wstate_reg[2]
(.C(ap_clk),
.CE(1'b1),
.D(\FSM_onehot_wstate[2]_i_1_n_0 ),
.Q(out[1]),
.R(SR));
(* FSM_ENCODED_STATES = "WRDATA:0100,WRRESP:1000,WRIDLE:0010,iSTATE:0001" *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\FSM_onehot_wstate_reg[3]
(.C(ap_clk),
.CE(1'b1),
.D(\FSM_onehot_wstate[3]_i_2_n_0 ),
.Q(out[2]),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT4 #(
.INIT(16'h5515))
\ap_CS_fsm[0]_i_1
(.I0(Q[1]),
.I1(Q[0]),
.I2(ap_start),
.I3(Q[2]),
.O(\ap_CS_fsm_reg[1] [0]));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT4 #(
.INIT(16'h0008))
\ap_CS_fsm[1]_i_1
(.I0(Q[0]),
.I1(ap_start),
.I2(Q[2]),
.I3(Q[1]),
.O(\ap_CS_fsm_reg[1] [1]));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT2 #(
.INIT(4'h8))
\d_read_reg_52[31]_i_1
(.I0(ap_start),
.I1(Q[0]),
.O(E));
LUT6 #(
.INIT(64'hFFFEFFFFAAAAAAAA))
int_ap_done_i_1
(.I0(Q[2]),
.I1(s_axi_pointer_basic_io_ARADDR[4]),
.I2(s_axi_pointer_basic_io_ARADDR[2]),
.I3(s_axi_pointer_basic_io_ARADDR[3]),
.I4(int_ap_done_i_2_n_0),
.I5(int_ap_done),
.O(int_ap_done_i_1_n_0));
LUT4 #(
.INIT(16'h0008))
int_ap_done_i_2
(.I0(s_axi_pointer_basic_io_ARVALID),
.I1(s_axi_pointer_basic_io_RVALID[0]),
.I2(s_axi_pointer_basic_io_ARADDR[0]),
.I3(s_axi_pointer_basic_io_ARADDR[1]),
.O(int_ap_done_i_2_n_0));
FDRE #(
.INIT(1'b0))
int_ap_done_reg
(.C(ap_clk),
.CE(1'b1),
.D(int_ap_done_i_1_n_0),
.Q(int_ap_done),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT2 #(
.INIT(4'h2))
int_ap_idle_i_1
(.I0(Q[0]),
.I1(ap_start),
.O(ap_idle));
FDRE int_ap_idle_reg
(.C(ap_clk),
.CE(1'b1),
.D(ap_idle),
.Q(int_ap_idle),
.R(SR));
FDRE int_ap_ready_reg
(.C(ap_clk),
.CE(1'b1),
.D(Q[2]),
.Q(int_ap_ready),
.R(SR));
LUT6 #(
.INIT(64'hFBBBBBBBF8888888))
int_ap_start_i_1
(.I0(int_auto_restart),
.I1(Q[2]),
.I2(int_ap_start_i_2_n_0),
.I3(int_ap_start_i_3_n_0),
.I4(s_axi_pointer_basic_io_WDATA[0]),
.I5(ap_start),
.O(int_ap_start_i_1_n_0));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT2 #(
.INIT(4'h2))
int_ap_start_i_2
(.I0(s_axi_pointer_basic_io_WSTRB[0]),
.I1(\waddr_reg_n_0_[2] ),
.O(int_ap_start_i_2_n_0));
LUT6 #(
.INIT(64'h0000000000001000))
int_ap_start_i_3
(.I0(\waddr_reg_n_0_[0] ),
.I1(\waddr_reg_n_0_[1] ),
.I2(s_axi_pointer_basic_io_WVALID),
.I3(out[1]),
.I4(\waddr_reg_n_0_[3] ),
.I5(\waddr_reg_n_0_[4] ),
.O(int_ap_start_i_3_n_0));
FDRE #(
.INIT(1'b0))
int_ap_start_reg
(.C(ap_clk),
.CE(1'b1),
.D(int_ap_start_i_1_n_0),
.Q(ap_start),
.R(SR));
LUT5 #(
.INIT(32'hEFFF2000))
int_auto_restart_i_1
(.I0(s_axi_pointer_basic_io_WDATA[7]),
.I1(\waddr_reg_n_0_[2] ),
.I2(s_axi_pointer_basic_io_WSTRB[0]),
.I3(int_ap_start_i_3_n_0),
.I4(int_auto_restart),
.O(int_auto_restart_i_1_n_0));
FDRE #(
.INIT(1'b0))
int_auto_restart_reg
(.C(ap_clk),
.CE(1'b1),
.D(int_auto_restart_i_1_n_0),
.Q(int_auto_restart),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT3 #(
.INIT(8'hB8))
\int_d_i[0]_i_1
(.I0(s_axi_pointer_basic_io_WDATA[0]),
.I1(s_axi_pointer_basic_io_WSTRB[0]),
.I2(\d_read_reg_52_reg[31] [0]),
.O(\int_d_i[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT3 #(
.INIT(8'hB8))
\int_d_i[10]_i_1
(.I0(s_axi_pointer_basic_io_WDATA[10]),
.I1(s_axi_pointer_basic_io_WSTRB[1]),
.I2(\d_read_reg_52_reg[31] [10]),
.O(\int_d_i[10]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT3 #(
.INIT(8'hB8))
\int_d_i[11]_i_1
(.I0(s_axi_pointer_basic_io_WDATA[11]),
.I1(s_axi_pointer_basic_io_WSTRB[1]),
.I2(\d_read_reg_52_reg[31] [11]),
.O(\int_d_i[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT3 #(
.INIT(8'hB8))
\int_d_i[12]_i_1
(.I0(s_axi_pointer_basic_io_WDATA[12]),
.I1(s_axi_pointer_basic_io_WSTRB[1]),
.I2(\d_read_reg_52_reg[31] [12]),
.O(\int_d_i[12]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT3 #(
.INIT(8'hB8))
\int_d_i[13]_i_1
(.I0(s_axi_pointer_basic_io_WDATA[13]),
.I1(s_axi_pointer_basic_io_WSTRB[1]),
.I2(\d_read_reg_52_reg[31] [13]),
.O(\int_d_i[13]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT3 #(
.INIT(8'hB8))
\int_d_i[14]_i_1
(.I0(s_axi_pointer_basic_io_WDATA[14]),
.I1(s_axi_pointer_basic_io_WSTRB[1]),
.I2(\d_read_reg_52_reg[31] [14]),
.O(\int_d_i[14]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT3 #(
.INIT(8'hB8))
\int_d_i[15]_i_1
(.I0(s_axi_pointer_basic_io_WDATA[15]),
.I1(s_axi_pointer_basic_io_WSTRB[1]),
.I2(\d_read_reg_52_reg[31] [15]),
.O(\int_d_i[15]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT3 #(
.INIT(8'hB8))
\int_d_i[16]_i_1
(.I0(s_axi_pointer_basic_io_WDATA[16]),
.I1(s_axi_pointer_basic_io_WSTRB[2]),
.I2(\d_read_reg_52_reg[31] [16]),
.O(\int_d_i[16]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT3 #(
.INIT(8'hB8))
\int_d_i[17]_i_1
(.I0(s_axi_pointer_basic_io_WDATA[17]),
.I1(s_axi_pointer_basic_io_WSTRB[2]),
.I2(\d_read_reg_52_reg[31] [17]),
.O(\int_d_i[17]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT3 #(
.INIT(8'hB8))
\int_d_i[18]_i_1
(.I0(s_axi_pointer_basic_io_WDATA[18]),
.I1(s_axi_pointer_basic_io_WSTRB[2]),
.I2(\d_read_reg_52_reg[31] [18]),
.O(\int_d_i[18]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT3 #(
.INIT(8'hB8))
\int_d_i[19]_i_1
(.I0(s_axi_pointer_basic_io_WDATA[19]),
.I1(s_axi_pointer_basic_io_WSTRB[2]),
.I2(\d_read_reg_52_reg[31] [19]),
.O(\int_d_i[19]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT3 #(
.INIT(8'hB8))
\int_d_i[1]_i_1
(.I0(s_axi_pointer_basic_io_WDATA[1]),
.I1(s_axi_pointer_basic_io_WSTRB[0]),
.I2(\d_read_reg_52_reg[31] [1]),
.O(\int_d_i[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT3 #(
.INIT(8'hB8))
\int_d_i[20]_i_1
(.I0(s_axi_pointer_basic_io_WDATA[20]),
.I1(s_axi_pointer_basic_io_WSTRB[2]),
.I2(\d_read_reg_52_reg[31] [20]),
.O(\int_d_i[20]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT3 #(
.INIT(8'hB8))
\int_d_i[21]_i_1
(.I0(s_axi_pointer_basic_io_WDATA[21]),
.I1(s_axi_pointer_basic_io_WSTRB[2]),
.I2(\d_read_reg_52_reg[31] [21]),
.O(\int_d_i[21]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT3 #(
.INIT(8'hB8))
\int_d_i[22]_i_1
(.I0(s_axi_pointer_basic_io_WDATA[22]),
.I1(s_axi_pointer_basic_io_WSTRB[2]),
.I2(\d_read_reg_52_reg[31] [22]),
.O(\int_d_i[22]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT3 #(
.INIT(8'hB8))
\int_d_i[23]_i_1
(.I0(s_axi_pointer_basic_io_WDATA[23]),
.I1(s_axi_pointer_basic_io_WSTRB[2]),
.I2(\d_read_reg_52_reg[31] [23]),
.O(\int_d_i[23]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT3 #(
.INIT(8'hB8))
\int_d_i[24]_i_1
(.I0(s_axi_pointer_basic_io_WDATA[24]),
.I1(s_axi_pointer_basic_io_WSTRB[3]),
.I2(\d_read_reg_52_reg[31] [24]),
.O(\int_d_i[24]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT3 #(
.INIT(8'hB8))
\int_d_i[25]_i_1
(.I0(s_axi_pointer_basic_io_WDATA[25]),
.I1(s_axi_pointer_basic_io_WSTRB[3]),
.I2(\d_read_reg_52_reg[31] [25]),
.O(\int_d_i[25]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT3 #(
.INIT(8'hB8))
\int_d_i[26]_i_1
(.I0(s_axi_pointer_basic_io_WDATA[26]),
.I1(s_axi_pointer_basic_io_WSTRB[3]),
.I2(\d_read_reg_52_reg[31] [26]),
.O(\int_d_i[26]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT3 #(
.INIT(8'hB8))
\int_d_i[27]_i_1
(.I0(s_axi_pointer_basic_io_WDATA[27]),
.I1(s_axi_pointer_basic_io_WSTRB[3]),
.I2(\d_read_reg_52_reg[31] [27]),
.O(\int_d_i[27]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT3 #(
.INIT(8'hB8))
\int_d_i[28]_i_1
(.I0(s_axi_pointer_basic_io_WDATA[28]),
.I1(s_axi_pointer_basic_io_WSTRB[3]),
.I2(\d_read_reg_52_reg[31] [28]),
.O(\int_d_i[28]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT3 #(
.INIT(8'hB8))
\int_d_i[29]_i_1
(.I0(s_axi_pointer_basic_io_WDATA[29]),
.I1(s_axi_pointer_basic_io_WSTRB[3]),
.I2(\d_read_reg_52_reg[31] [29]),
.O(\int_d_i[29]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT3 #(
.INIT(8'hB8))
\int_d_i[2]_i_1
(.I0(s_axi_pointer_basic_io_WDATA[2]),
.I1(s_axi_pointer_basic_io_WSTRB[0]),
.I2(\d_read_reg_52_reg[31] [2]),
.O(\int_d_i[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT3 #(
.INIT(8'hB8))
\int_d_i[30]_i_1
(.I0(s_axi_pointer_basic_io_WDATA[30]),
.I1(s_axi_pointer_basic_io_WSTRB[3]),
.I2(\d_read_reg_52_reg[31] [30]),
.O(\int_d_i[30]_i_1_n_0 ));
LUT3 #(
.INIT(8'h08))
\int_d_i[31]_i_1
(.I0(\int_d_i[31]_i_3_n_0 ),
.I1(\waddr_reg_n_0_[4] ),
.I2(\waddr_reg_n_0_[2] ),
.O(\int_d_i[31]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT3 #(
.INIT(8'hB8))
\int_d_i[31]_i_2
(.I0(s_axi_pointer_basic_io_WDATA[31]),
.I1(s_axi_pointer_basic_io_WSTRB[3]),
.I2(\d_read_reg_52_reg[31] [31]),
.O(\int_d_i[31]_i_2_n_0 ));
LUT5 #(
.INIT(32'h00000040))
\int_d_i[31]_i_3
(.I0(\waddr_reg_n_0_[3] ),
.I1(out[1]),
.I2(s_axi_pointer_basic_io_WVALID),
.I3(\waddr_reg_n_0_[1] ),
.I4(\waddr_reg_n_0_[0] ),
.O(\int_d_i[31]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT3 #(
.INIT(8'hB8))
\int_d_i[3]_i_1
(.I0(s_axi_pointer_basic_io_WDATA[3]),
.I1(s_axi_pointer_basic_io_WSTRB[0]),
.I2(\d_read_reg_52_reg[31] [3]),
.O(\int_d_i[3]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT3 #(
.INIT(8'hB8))
\int_d_i[4]_i_1
(.I0(s_axi_pointer_basic_io_WDATA[4]),
.I1(s_axi_pointer_basic_io_WSTRB[0]),
.I2(\d_read_reg_52_reg[31] [4]),
.O(\int_d_i[4]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT3 #(
.INIT(8'hB8))
\int_d_i[5]_i_1
(.I0(s_axi_pointer_basic_io_WDATA[5]),
.I1(s_axi_pointer_basic_io_WSTRB[0]),
.I2(\d_read_reg_52_reg[31] [5]),
.O(\int_d_i[5]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT3 #(
.INIT(8'hB8))
\int_d_i[6]_i_1
(.I0(s_axi_pointer_basic_io_WDATA[6]),
.I1(s_axi_pointer_basic_io_WSTRB[0]),
.I2(\d_read_reg_52_reg[31] [6]),
.O(\int_d_i[6]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT3 #(
.INIT(8'hB8))
\int_d_i[7]_i_1
(.I0(s_axi_pointer_basic_io_WDATA[7]),
.I1(s_axi_pointer_basic_io_WSTRB[0]),
.I2(\d_read_reg_52_reg[31] [7]),
.O(\int_d_i[7]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT3 #(
.INIT(8'hB8))
\int_d_i[8]_i_1
(.I0(s_axi_pointer_basic_io_WDATA[8]),
.I1(s_axi_pointer_basic_io_WSTRB[1]),
.I2(\d_read_reg_52_reg[31] [8]),
.O(\int_d_i[8]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT3 #(
.INIT(8'hB8))
\int_d_i[9]_i_1
(.I0(s_axi_pointer_basic_io_WDATA[9]),
.I1(s_axi_pointer_basic_io_WSTRB[1]),
.I2(\d_read_reg_52_reg[31] [9]),
.O(\int_d_i[9]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\int_d_i_reg[0]
(.C(ap_clk),
.CE(\int_d_i[31]_i_1_n_0 ),
.D(\int_d_i[0]_i_1_n_0 ),
.Q(\d_read_reg_52_reg[31] [0]),
.R(SR));
FDRE #(
.INIT(1'b0))
\int_d_i_reg[10]
(.C(ap_clk),
.CE(\int_d_i[31]_i_1_n_0 ),
.D(\int_d_i[10]_i_1_n_0 ),
.Q(\d_read_reg_52_reg[31] [10]),
.R(SR));
FDRE #(
.INIT(1'b0))
\int_d_i_reg[11]
(.C(ap_clk),
.CE(\int_d_i[31]_i_1_n_0 ),
.D(\int_d_i[11]_i_1_n_0 ),
.Q(\d_read_reg_52_reg[31] [11]),
.R(SR));
FDRE #(
.INIT(1'b0))
\int_d_i_reg[12]
(.C(ap_clk),
.CE(\int_d_i[31]_i_1_n_0 ),
.D(\int_d_i[12]_i_1_n_0 ),
.Q(\d_read_reg_52_reg[31] [12]),
.R(SR));
FDRE #(
.INIT(1'b0))
\int_d_i_reg[13]
(.C(ap_clk),
.CE(\int_d_i[31]_i_1_n_0 ),
.D(\int_d_i[13]_i_1_n_0 ),
.Q(\d_read_reg_52_reg[31] [13]),
.R(SR));
FDRE #(
.INIT(1'b0))
\int_d_i_reg[14]
(.C(ap_clk),
.CE(\int_d_i[31]_i_1_n_0 ),
.D(\int_d_i[14]_i_1_n_0 ),
.Q(\d_read_reg_52_reg[31] [14]),
.R(SR));
FDRE #(
.INIT(1'b0))
\int_d_i_reg[15]
(.C(ap_clk),
.CE(\int_d_i[31]_i_1_n_0 ),
.D(\int_d_i[15]_i_1_n_0 ),
.Q(\d_read_reg_52_reg[31] [15]),
.R(SR));
FDRE #(
.INIT(1'b0))
\int_d_i_reg[16]
(.C(ap_clk),
.CE(\int_d_i[31]_i_1_n_0 ),
.D(\int_d_i[16]_i_1_n_0 ),
.Q(\d_read_reg_52_reg[31] [16]),
.R(SR));
FDRE #(
.INIT(1'b0))
\int_d_i_reg[17]
(.C(ap_clk),
.CE(\int_d_i[31]_i_1_n_0 ),
.D(\int_d_i[17]_i_1_n_0 ),
.Q(\d_read_reg_52_reg[31] [17]),
.R(SR));
FDRE #(
.INIT(1'b0))
\int_d_i_reg[18]
(.C(ap_clk),
.CE(\int_d_i[31]_i_1_n_0 ),
.D(\int_d_i[18]_i_1_n_0 ),
.Q(\d_read_reg_52_reg[31] [18]),
.R(SR));
FDRE #(
.INIT(1'b0))
\int_d_i_reg[19]
(.C(ap_clk),
.CE(\int_d_i[31]_i_1_n_0 ),
.D(\int_d_i[19]_i_1_n_0 ),
.Q(\d_read_reg_52_reg[31] [19]),
.R(SR));
FDRE #(
.INIT(1'b0))
\int_d_i_reg[1]
(.C(ap_clk),
.CE(\int_d_i[31]_i_1_n_0 ),
.D(\int_d_i[1]_i_1_n_0 ),
.Q(\d_read_reg_52_reg[31] [1]),
.R(SR));
FDRE #(
.INIT(1'b0))
\int_d_i_reg[20]
(.C(ap_clk),
.CE(\int_d_i[31]_i_1_n_0 ),
.D(\int_d_i[20]_i_1_n_0 ),
.Q(\d_read_reg_52_reg[31] [20]),
.R(SR));
FDRE #(
.INIT(1'b0))
\int_d_i_reg[21]
(.C(ap_clk),
.CE(\int_d_i[31]_i_1_n_0 ),
.D(\int_d_i[21]_i_1_n_0 ),
.Q(\d_read_reg_52_reg[31] [21]),
.R(SR));
FDRE #(
.INIT(1'b0))
\int_d_i_reg[22]
(.C(ap_clk),
.CE(\int_d_i[31]_i_1_n_0 ),
.D(\int_d_i[22]_i_1_n_0 ),
.Q(\d_read_reg_52_reg[31] [22]),
.R(SR));
FDRE #(
.INIT(1'b0))
\int_d_i_reg[23]
(.C(ap_clk),
.CE(\int_d_i[31]_i_1_n_0 ),
.D(\int_d_i[23]_i_1_n_0 ),
.Q(\d_read_reg_52_reg[31] [23]),
.R(SR));
FDRE #(
.INIT(1'b0))
\int_d_i_reg[24]
(.C(ap_clk),
.CE(\int_d_i[31]_i_1_n_0 ),
.D(\int_d_i[24]_i_1_n_0 ),
.Q(\d_read_reg_52_reg[31] [24]),
.R(SR));
FDRE #(
.INIT(1'b0))
\int_d_i_reg[25]
(.C(ap_clk),
.CE(\int_d_i[31]_i_1_n_0 ),
.D(\int_d_i[25]_i_1_n_0 ),
.Q(\d_read_reg_52_reg[31] [25]),
.R(SR));
FDRE #(
.INIT(1'b0))
\int_d_i_reg[26]
(.C(ap_clk),
.CE(\int_d_i[31]_i_1_n_0 ),
.D(\int_d_i[26]_i_1_n_0 ),
.Q(\d_read_reg_52_reg[31] [26]),
.R(SR));
FDRE #(
.INIT(1'b0))
\int_d_i_reg[27]
(.C(ap_clk),
.CE(\int_d_i[31]_i_1_n_0 ),
.D(\int_d_i[27]_i_1_n_0 ),
.Q(\d_read_reg_52_reg[31] [27]),
.R(SR));
FDRE #(
.INIT(1'b0))
\int_d_i_reg[28]
(.C(ap_clk),
.CE(\int_d_i[31]_i_1_n_0 ),
.D(\int_d_i[28]_i_1_n_0 ),
.Q(\d_read_reg_52_reg[31] [28]),
.R(SR));
FDRE #(
.INIT(1'b0))
\int_d_i_reg[29]
(.C(ap_clk),
.CE(\int_d_i[31]_i_1_n_0 ),
.D(\int_d_i[29]_i_1_n_0 ),
.Q(\d_read_reg_52_reg[31] [29]),
.R(SR));
FDRE #(
.INIT(1'b0))
\int_d_i_reg[2]
(.C(ap_clk),
.CE(\int_d_i[31]_i_1_n_0 ),
.D(\int_d_i[2]_i_1_n_0 ),
.Q(\d_read_reg_52_reg[31] [2]),
.R(SR));
FDRE #(
.INIT(1'b0))
\int_d_i_reg[30]
(.C(ap_clk),
.CE(\int_d_i[31]_i_1_n_0 ),
.D(\int_d_i[30]_i_1_n_0 ),
.Q(\d_read_reg_52_reg[31] [30]),
.R(SR));
FDRE #(
.INIT(1'b0))
\int_d_i_reg[31]
(.C(ap_clk),
.CE(\int_d_i[31]_i_1_n_0 ),
.D(\int_d_i[31]_i_2_n_0 ),
.Q(\d_read_reg_52_reg[31] [31]),
.R(SR));
FDRE #(
.INIT(1'b0))
\int_d_i_reg[3]
(.C(ap_clk),
.CE(\int_d_i[31]_i_1_n_0 ),
.D(\int_d_i[3]_i_1_n_0 ),
.Q(\d_read_reg_52_reg[31] [3]),
.R(SR));
FDRE #(
.INIT(1'b0))
\int_d_i_reg[4]
(.C(ap_clk),
.CE(\int_d_i[31]_i_1_n_0 ),
.D(\int_d_i[4]_i_1_n_0 ),
.Q(\d_read_reg_52_reg[31] [4]),
.R(SR));
FDRE #(
.INIT(1'b0))
\int_d_i_reg[5]
(.C(ap_clk),
.CE(\int_d_i[31]_i_1_n_0 ),
.D(\int_d_i[5]_i_1_n_0 ),
.Q(\d_read_reg_52_reg[31] [5]),
.R(SR));
FDRE #(
.INIT(1'b0))
\int_d_i_reg[6]
(.C(ap_clk),
.CE(\int_d_i[31]_i_1_n_0 ),
.D(\int_d_i[6]_i_1_n_0 ),
.Q(\d_read_reg_52_reg[31] [6]),
.R(SR));
FDRE #(
.INIT(1'b0))
\int_d_i_reg[7]
(.C(ap_clk),
.CE(\int_d_i[31]_i_1_n_0 ),
.D(\int_d_i[7]_i_1_n_0 ),
.Q(\d_read_reg_52_reg[31] [7]),
.R(SR));
FDRE #(
.INIT(1'b0))
\int_d_i_reg[8]
(.C(ap_clk),
.CE(\int_d_i[31]_i_1_n_0 ),
.D(\int_d_i[8]_i_1_n_0 ),
.Q(\d_read_reg_52_reg[31] [8]),
.R(SR));
FDRE #(
.INIT(1'b0))
\int_d_i_reg[9]
(.C(ap_clk),
.CE(\int_d_i[31]_i_1_n_0 ),
.D(\int_d_i[9]_i_1_n_0 ),
.Q(\d_read_reg_52_reg[31] [9]),
.R(SR));
LUT6 #(
.INIT(64'hBFFFFFFFAAAAAAAA))
int_d_o_ap_vld_i_1
(.I0(Q[2]),
.I1(s_axi_pointer_basic_io_ARADDR[2]),
.I2(s_axi_pointer_basic_io_ARADDR[4]),
.I3(s_axi_pointer_basic_io_ARADDR[3]),
.I4(int_ap_done_i_2_n_0),
.I5(int_d_o_ap_vld),
.O(int_d_o_ap_vld_i_1_n_0));
FDRE int_d_o_ap_vld_reg
(.C(ap_clk),
.CE(1'b1),
.D(int_d_o_ap_vld_i_1_n_0),
.Q(int_d_o_ap_vld),
.R(SR));
FDRE #(
.INIT(1'b0))
\int_d_o_reg[0]
(.C(ap_clk),
.CE(Q[2]),
.D(D[0]),
.Q(int_d_o[0]),
.R(SR));
FDRE #(
.INIT(1'b0))
\int_d_o_reg[10]
(.C(ap_clk),
.CE(Q[2]),
.D(D[10]),
.Q(int_d_o[10]),
.R(SR));
FDRE #(
.INIT(1'b0))
\int_d_o_reg[11]
(.C(ap_clk),
.CE(Q[2]),
.D(D[11]),
.Q(int_d_o[11]),
.R(SR));
FDRE #(
.INIT(1'b0))
\int_d_o_reg[12]
(.C(ap_clk),
.CE(Q[2]),
.D(D[12]),
.Q(int_d_o[12]),
.R(SR));
FDRE #(
.INIT(1'b0))
\int_d_o_reg[13]
(.C(ap_clk),
.CE(Q[2]),
.D(D[13]),
.Q(int_d_o[13]),
.R(SR));
FDRE #(
.INIT(1'b0))
\int_d_o_reg[14]
(.C(ap_clk),
.CE(Q[2]),
.D(D[14]),
.Q(int_d_o[14]),
.R(SR));
FDRE #(
.INIT(1'b0))
\int_d_o_reg[15]
(.C(ap_clk),
.CE(Q[2]),
.D(D[15]),
.Q(int_d_o[15]),
.R(SR));
FDRE #(
.INIT(1'b0))
\int_d_o_reg[16]
(.C(ap_clk),
.CE(Q[2]),
.D(D[16]),
.Q(int_d_o[16]),
.R(SR));
FDRE #(
.INIT(1'b0))
\int_d_o_reg[17]
(.C(ap_clk),
.CE(Q[2]),
.D(D[17]),
.Q(int_d_o[17]),
.R(SR));
FDRE #(
.INIT(1'b0))
\int_d_o_reg[18]
(.C(ap_clk),
.CE(Q[2]),
.D(D[18]),
.Q(int_d_o[18]),
.R(SR));
FDRE #(
.INIT(1'b0))
\int_d_o_reg[19]
(.C(ap_clk),
.CE(Q[2]),
.D(D[19]),
.Q(int_d_o[19]),
.R(SR));
FDRE #(
.INIT(1'b0))
\int_d_o_reg[1]
(.C(ap_clk),
.CE(Q[2]),
.D(D[1]),
.Q(int_d_o[1]),
.R(SR));
FDRE #(
.INIT(1'b0))
\int_d_o_reg[20]
(.C(ap_clk),
.CE(Q[2]),
.D(D[20]),
.Q(int_d_o[20]),
.R(SR));
FDRE #(
.INIT(1'b0))
\int_d_o_reg[21]
(.C(ap_clk),
.CE(Q[2]),
.D(D[21]),
.Q(int_d_o[21]),
.R(SR));
FDRE #(
.INIT(1'b0))
\int_d_o_reg[22]
(.C(ap_clk),
.CE(Q[2]),
.D(D[22]),
.Q(int_d_o[22]),
.R(SR));
FDRE #(
.INIT(1'b0))
\int_d_o_reg[23]
(.C(ap_clk),
.CE(Q[2]),
.D(D[23]),
.Q(int_d_o[23]),
.R(SR));
FDRE #(
.INIT(1'b0))
\int_d_o_reg[24]
(.C(ap_clk),
.CE(Q[2]),
.D(D[24]),
.Q(int_d_o[24]),
.R(SR));
FDRE #(
.INIT(1'b0))
\int_d_o_reg[25]
(.C(ap_clk),
.CE(Q[2]),
.D(D[25]),
.Q(int_d_o[25]),
.R(SR));
FDRE #(
.INIT(1'b0))
\int_d_o_reg[26]
(.C(ap_clk),
.CE(Q[2]),
.D(D[26]),
.Q(int_d_o[26]),
.R(SR));
FDRE #(
.INIT(1'b0))
\int_d_o_reg[27]
(.C(ap_clk),
.CE(Q[2]),
.D(D[27]),
.Q(int_d_o[27]),
.R(SR));
FDRE #(
.INIT(1'b0))
\int_d_o_reg[28]
(.C(ap_clk),
.CE(Q[2]),
.D(D[28]),
.Q(int_d_o[28]),
.R(SR));
FDRE #(
.INIT(1'b0))
\int_d_o_reg[29]
(.C(ap_clk),
.CE(Q[2]),
.D(D[29]),
.Q(int_d_o[29]),
.R(SR));
FDRE #(
.INIT(1'b0))
\int_d_o_reg[2]
(.C(ap_clk),
.CE(Q[2]),
.D(D[2]),
.Q(int_d_o[2]),
.R(SR));
FDRE #(
.INIT(1'b0))
\int_d_o_reg[30]
(.C(ap_clk),
.CE(Q[2]),
.D(D[30]),
.Q(int_d_o[30]),
.R(SR));
FDRE #(
.INIT(1'b0))
\int_d_o_reg[31]
(.C(ap_clk),
.CE(Q[2]),
.D(D[31]),
.Q(int_d_o[31]),
.R(SR));
FDRE #(
.INIT(1'b0))
\int_d_o_reg[3]
(.C(ap_clk),
.CE(Q[2]),
.D(D[3]),
.Q(int_d_o[3]),
.R(SR));
FDRE #(
.INIT(1'b0))
\int_d_o_reg[4]
(.C(ap_clk),
.CE(Q[2]),
.D(D[4]),
.Q(int_d_o[4]),
.R(SR));
FDRE #(
.INIT(1'b0))
\int_d_o_reg[5]
(.C(ap_clk),
.CE(Q[2]),
.D(D[5]),
.Q(int_d_o[5]),
.R(SR));
FDRE #(
.INIT(1'b0))
\int_d_o_reg[6]
(.C(ap_clk),
.CE(Q[2]),
.D(D[6]),
.Q(int_d_o[6]),
.R(SR));
FDRE #(
.INIT(1'b0))
\int_d_o_reg[7]
(.C(ap_clk),
.CE(Q[2]),
.D(D[7]),
.Q(int_d_o[7]),
.R(SR));
FDRE #(
.INIT(1'b0))
\int_d_o_reg[8]
(.C(ap_clk),
.CE(Q[2]),
.D(D[8]),
.Q(int_d_o[8]),
.R(SR));
FDRE #(
.INIT(1'b0))
\int_d_o_reg[9]
(.C(ap_clk),
.CE(Q[2]),
.D(D[9]),
.Q(int_d_o[9]),
.R(SR));
LUT5 #(
.INIT(32'hBFFF8000))
int_gie_i_1
(.I0(s_axi_pointer_basic_io_WDATA[0]),
.I1(int_ap_start_i_3_n_0),
.I2(\waddr_reg_n_0_[2] ),
.I3(s_axi_pointer_basic_io_WSTRB[0]),
.I4(int_gie_reg_n_0),
.O(int_gie_i_1_n_0));
FDRE #(
.INIT(1'b0))
int_gie_reg
(.C(ap_clk),
.CE(1'b1),
.D(int_gie_i_1_n_0),
.Q(int_gie_reg_n_0),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'hFFEF0020))
\int_ier[0]_i_1
(.I0(s_axi_pointer_basic_io_WDATA[0]),
.I1(\waddr_reg_n_0_[2] ),
.I2(s_axi_pointer_basic_io_WSTRB[0]),
.I3(\int_ier[1]_i_2_n_0 ),
.I4(\int_ier_reg_n_0_[0] ),
.O(\int_ier[0]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFEF0020))
\int_ier[1]_i_1
(.I0(s_axi_pointer_basic_io_WDATA[1]),
.I1(\waddr_reg_n_0_[2] ),
.I2(s_axi_pointer_basic_io_WSTRB[0]),
.I3(\int_ier[1]_i_2_n_0 ),
.I4(\int_ier_reg_n_0_[1] ),
.O(\int_ier[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFF7FFFF))
\int_ier[1]_i_2
(.I0(out[1]),
.I1(s_axi_pointer_basic_io_WVALID),
.I2(\waddr_reg_n_0_[1] ),
.I3(\waddr_reg_n_0_[0] ),
.I4(\waddr_reg_n_0_[3] ),
.I5(\waddr_reg_n_0_[4] ),
.O(\int_ier[1]_i_2_n_0 ));
FDRE #(
.INIT(1'b0))
\int_ier_reg[0]
(.C(ap_clk),
.CE(1'b1),
.D(\int_ier[0]_i_1_n_0 ),
.Q(\int_ier_reg_n_0_[0] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\int_ier_reg[1]
(.C(ap_clk),
.CE(1'b1),
.D(\int_ier[1]_i_1_n_0 ),
.Q(\int_ier_reg_n_0_[1] ),
.R(SR));
LUT6 #(
.INIT(64'hFFFFDFFFFFFF2000))
\int_isr[0]_i_1
(.I0(s_axi_pointer_basic_io_WDATA[0]),
.I1(\int_ier[1]_i_2_n_0 ),
.I2(s_axi_pointer_basic_io_WSTRB[0]),
.I3(\waddr_reg_n_0_[2] ),
.I4(int_isr7_out),
.I5(\int_isr_reg_n_0_[0] ),
.O(\int_isr[0]_i_1_n_0 ));
LUT2 #(
.INIT(4'h8))
\int_isr[0]_i_2
(.I0(Q[2]),
.I1(\int_ier_reg_n_0_[0] ),
.O(int_isr7_out));
LUT6 #(
.INIT(64'hFFFFDFFFFFFF2000))
\int_isr[1]_i_1
(.I0(s_axi_pointer_basic_io_WDATA[1]),
.I1(\int_ier[1]_i_2_n_0 ),
.I2(s_axi_pointer_basic_io_WSTRB[0]),
.I3(\waddr_reg_n_0_[2] ),
.I4(int_isr),
.I5(p_1_in),
.O(\int_isr[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT2 #(
.INIT(4'h8))
\int_isr[1]_i_2
(.I0(Q[2]),
.I1(\int_ier_reg_n_0_[1] ),
.O(int_isr));
FDRE #(
.INIT(1'b0))
\int_isr_reg[0]
(.C(ap_clk),
.CE(1'b1),
.D(\int_isr[0]_i_1_n_0 ),
.Q(\int_isr_reg_n_0_[0] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\int_isr_reg[1]
(.C(ap_clk),
.CE(1'b1),
.D(\int_isr[1]_i_1_n_0 ),
.Q(p_1_in),
.R(SR));
LUT3 #(
.INIT(8'hA8))
interrupt_INST_0
(.I0(int_gie_reg_n_0),
.I1(p_1_in),
.I2(\int_isr_reg_n_0_[0] ),
.O(interrupt));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'h000000B8))
\rdata[0]_i_1
(.I0(\rdata[0]_i_2_n_0 ),
.I1(s_axi_pointer_basic_io_ARADDR[4]),
.I2(\rdata[0]_i_3_n_0 ),
.I3(s_axi_pointer_basic_io_ARADDR[0]),
.I4(s_axi_pointer_basic_io_ARADDR[1]),
.O(rdata[0]));
LUT5 #(
.INIT(32'hA0A0CFC0))
\rdata[0]_i_2
(.I0(int_d_o_ap_vld),
.I1(int_d_o[0]),
.I2(s_axi_pointer_basic_io_ARADDR[3]),
.I3(\d_read_reg_52_reg[31] [0]),
.I4(s_axi_pointer_basic_io_ARADDR[2]),
.O(\rdata[0]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\rdata[0]_i_3
(.I0(\int_isr_reg_n_0_[0] ),
.I1(\int_ier_reg_n_0_[0] ),
.I2(s_axi_pointer_basic_io_ARADDR[3]),
.I3(int_gie_reg_n_0),
.I4(s_axi_pointer_basic_io_ARADDR[2]),
.I5(ap_start),
.O(\rdata[0]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT3 #(
.INIT(8'hB8))
\rdata[10]_i_1
(.I0(int_d_o[10]),
.I1(s_axi_pointer_basic_io_ARADDR[3]),
.I2(\d_read_reg_52_reg[31] [10]),
.O(\rdata[10]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT3 #(
.INIT(8'hB8))
\rdata[11]_i_1
(.I0(int_d_o[11]),
.I1(s_axi_pointer_basic_io_ARADDR[3]),
.I2(\d_read_reg_52_reg[31] [11]),
.O(\rdata[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT3 #(
.INIT(8'hB8))
\rdata[12]_i_1
(.I0(int_d_o[12]),
.I1(s_axi_pointer_basic_io_ARADDR[3]),
.I2(\d_read_reg_52_reg[31] [12]),
.O(\rdata[12]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT3 #(
.INIT(8'hB8))
\rdata[13]_i_1
(.I0(int_d_o[13]),
.I1(s_axi_pointer_basic_io_ARADDR[3]),
.I2(\d_read_reg_52_reg[31] [13]),
.O(\rdata[13]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT3 #(
.INIT(8'hB8))
\rdata[14]_i_1
(.I0(int_d_o[14]),
.I1(s_axi_pointer_basic_io_ARADDR[3]),
.I2(\d_read_reg_52_reg[31] [14]),
.O(\rdata[14]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT3 #(
.INIT(8'hB8))
\rdata[15]_i_1
(.I0(int_d_o[15]),
.I1(s_axi_pointer_basic_io_ARADDR[3]),
.I2(\d_read_reg_52_reg[31] [15]),
.O(\rdata[15]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT3 #(
.INIT(8'hB8))
\rdata[16]_i_1
(.I0(int_d_o[16]),
.I1(s_axi_pointer_basic_io_ARADDR[3]),
.I2(\d_read_reg_52_reg[31] [16]),
.O(\rdata[16]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT3 #(
.INIT(8'hB8))
\rdata[17]_i_1
(.I0(int_d_o[17]),
.I1(s_axi_pointer_basic_io_ARADDR[3]),
.I2(\d_read_reg_52_reg[31] [17]),
.O(\rdata[17]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT3 #(
.INIT(8'hB8))
\rdata[18]_i_1
(.I0(int_d_o[18]),
.I1(s_axi_pointer_basic_io_ARADDR[3]),
.I2(\d_read_reg_52_reg[31] [18]),
.O(\rdata[18]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT3 #(
.INIT(8'hB8))
\rdata[19]_i_1
(.I0(int_d_o[19]),
.I1(s_axi_pointer_basic_io_ARADDR[3]),
.I2(\d_read_reg_52_reg[31] [19]),
.O(\rdata[19]_i_1_n_0 ));
LUT6 #(
.INIT(64'hE0E0E0E0E0E0E0EE))
\rdata[1]_i_1
(.I0(\rdata[1]_i_2_n_0 ),
.I1(\rdata[1]_i_3_n_0 ),
.I2(\rdata[1]_i_4_n_0 ),
.I3(s_axi_pointer_basic_io_ARADDR[4]),
.I4(s_axi_pointer_basic_io_ARADDR[0]),
.I5(s_axi_pointer_basic_io_ARADDR[1]),
.O(rdata[1]));
LUT6 #(
.INIT(64'hF2F2F2F2F2F2FFF2))
\rdata[1]_i_2
(.I0(s_axi_pointer_basic_io_ARADDR[4]),
.I1(s_axi_pointer_basic_io_ARADDR[0]),
.I2(s_axi_pointer_basic_io_ARADDR[1]),
.I3(int_ap_done),
.I4(s_axi_pointer_basic_io_ARADDR[3]),
.I5(s_axi_pointer_basic_io_ARADDR[2]),
.O(\rdata[1]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'hA808))
\rdata[1]_i_3
(.I0(s_axi_pointer_basic_io_ARADDR[3]),
.I1(\int_ier_reg_n_0_[1] ),
.I2(s_axi_pointer_basic_io_ARADDR[2]),
.I3(p_1_in),
.O(\rdata[1]_i_3_n_0 ));
LUT6 #(
.INIT(64'h00000000000000E2))
\rdata[1]_i_4
(.I0(\d_read_reg_52_reg[31] [1]),
.I1(s_axi_pointer_basic_io_ARADDR[3]),
.I2(int_d_o[1]),
.I3(s_axi_pointer_basic_io_ARADDR[1]),
.I4(s_axi_pointer_basic_io_ARADDR[0]),
.I5(s_axi_pointer_basic_io_ARADDR[2]),
.O(\rdata[1]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT3 #(
.INIT(8'hB8))
\rdata[20]_i_1
(.I0(int_d_o[20]),
.I1(s_axi_pointer_basic_io_ARADDR[3]),
.I2(\d_read_reg_52_reg[31] [20]),
.O(\rdata[20]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT3 #(
.INIT(8'hB8))
\rdata[21]_i_1
(.I0(int_d_o[21]),
.I1(s_axi_pointer_basic_io_ARADDR[3]),
.I2(\d_read_reg_52_reg[31] [21]),
.O(\rdata[21]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT3 #(
.INIT(8'hB8))
\rdata[22]_i_1
(.I0(int_d_o[22]),
.I1(s_axi_pointer_basic_io_ARADDR[3]),
.I2(\d_read_reg_52_reg[31] [22]),
.O(\rdata[22]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT3 #(
.INIT(8'hB8))
\rdata[23]_i_1
(.I0(int_d_o[23]),
.I1(s_axi_pointer_basic_io_ARADDR[3]),
.I2(\d_read_reg_52_reg[31] [23]),
.O(\rdata[23]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT3 #(
.INIT(8'hB8))
\rdata[24]_i_1
(.I0(int_d_o[24]),
.I1(s_axi_pointer_basic_io_ARADDR[3]),
.I2(\d_read_reg_52_reg[31] [24]),
.O(\rdata[24]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT3 #(
.INIT(8'hB8))
\rdata[25]_i_1
(.I0(int_d_o[25]),
.I1(s_axi_pointer_basic_io_ARADDR[3]),
.I2(\d_read_reg_52_reg[31] [25]),
.O(\rdata[25]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT3 #(
.INIT(8'hB8))
\rdata[26]_i_1
(.I0(int_d_o[26]),
.I1(s_axi_pointer_basic_io_ARADDR[3]),
.I2(\d_read_reg_52_reg[31] [26]),
.O(\rdata[26]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT3 #(
.INIT(8'hB8))
\rdata[27]_i_1
(.I0(int_d_o[27]),
.I1(s_axi_pointer_basic_io_ARADDR[3]),
.I2(\d_read_reg_52_reg[31] [27]),
.O(\rdata[27]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT3 #(
.INIT(8'hB8))
\rdata[28]_i_1
(.I0(int_d_o[28]),
.I1(s_axi_pointer_basic_io_ARADDR[3]),
.I2(\d_read_reg_52_reg[31] [28]),
.O(\rdata[28]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT3 #(
.INIT(8'hB8))
\rdata[29]_i_1
(.I0(int_d_o[29]),
.I1(s_axi_pointer_basic_io_ARADDR[3]),
.I2(\d_read_reg_52_reg[31] [29]),
.O(\rdata[29]_i_1_n_0 ));
LUT6 #(
.INIT(64'h000000000AFC0A0C))
\rdata[2]_i_1
(.I0(int_d_o[2]),
.I1(\d_read_reg_52_reg[31] [2]),
.I2(\rdata[7]_i_2_n_0 ),
.I3(s_axi_pointer_basic_io_ARADDR[3]),
.I4(int_ap_idle),
.I5(\rdata[7]_i_3_n_0 ),
.O(rdata[2]));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT3 #(
.INIT(8'hB8))
\rdata[30]_i_1
(.I0(int_d_o[30]),
.I1(s_axi_pointer_basic_io_ARADDR[3]),
.I2(\d_read_reg_52_reg[31] [30]),
.O(\rdata[30]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFD000000000000))
\rdata[31]_i_1
(.I0(s_axi_pointer_basic_io_ARADDR[4]),
.I1(s_axi_pointer_basic_io_ARADDR[2]),
.I2(s_axi_pointer_basic_io_ARADDR[0]),
.I3(s_axi_pointer_basic_io_ARADDR[1]),
.I4(s_axi_pointer_basic_io_ARVALID),
.I5(s_axi_pointer_basic_io_RVALID[0]),
.O(\rdata[31]_i_1_n_0 ));
LUT2 #(
.INIT(4'h8))
\rdata[31]_i_2
(.I0(s_axi_pointer_basic_io_RVALID[0]),
.I1(s_axi_pointer_basic_io_ARVALID),
.O(ar_hs));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT3 #(
.INIT(8'hB8))
\rdata[31]_i_3
(.I0(int_d_o[31]),
.I1(s_axi_pointer_basic_io_ARADDR[3]),
.I2(\d_read_reg_52_reg[31] [31]),
.O(\rdata[31]_i_3_n_0 ));
LUT6 #(
.INIT(64'h000000000AFC0A0C))
\rdata[3]_i_1
(.I0(int_d_o[3]),
.I1(\d_read_reg_52_reg[31] [3]),
.I2(\rdata[7]_i_2_n_0 ),
.I3(s_axi_pointer_basic_io_ARADDR[3]),
.I4(int_ap_ready),
.I5(\rdata[7]_i_3_n_0 ),
.O(rdata[3]));
LUT3 #(
.INIT(8'hB8))
\rdata[4]_i_1
(.I0(int_d_o[4]),
.I1(s_axi_pointer_basic_io_ARADDR[3]),
.I2(\d_read_reg_52_reg[31] [4]),
.O(\rdata[4]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT3 #(
.INIT(8'hB8))
\rdata[5]_i_1
(.I0(int_d_o[5]),
.I1(s_axi_pointer_basic_io_ARADDR[3]),
.I2(\d_read_reg_52_reg[31] [5]),
.O(\rdata[5]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT3 #(
.INIT(8'hB8))
\rdata[6]_i_1
(.I0(int_d_o[6]),
.I1(s_axi_pointer_basic_io_ARADDR[3]),
.I2(\d_read_reg_52_reg[31] [6]),
.O(\rdata[6]_i_1_n_0 ));
LUT6 #(
.INIT(64'h000000000AFC0A0C))
\rdata[7]_i_1
(.I0(int_d_o[7]),
.I1(\d_read_reg_52_reg[31] [7]),
.I2(\rdata[7]_i_2_n_0 ),
.I3(s_axi_pointer_basic_io_ARADDR[3]),
.I4(int_auto_restart),
.I5(\rdata[7]_i_3_n_0 ),
.O(rdata[7]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT3 #(
.INIT(8'h45))
\rdata[7]_i_2
(.I0(s_axi_pointer_basic_io_ARADDR[1]),
.I1(s_axi_pointer_basic_io_ARADDR[0]),
.I2(s_axi_pointer_basic_io_ARADDR[4]),
.O(\rdata[7]_i_2_n_0 ));
LUT3 #(
.INIT(8'hFE))
\rdata[7]_i_3
(.I0(s_axi_pointer_basic_io_ARADDR[2]),
.I1(s_axi_pointer_basic_io_ARADDR[0]),
.I2(s_axi_pointer_basic_io_ARADDR[1]),
.O(\rdata[7]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT3 #(
.INIT(8'hB8))
\rdata[8]_i_1
(.I0(int_d_o[8]),
.I1(s_axi_pointer_basic_io_ARADDR[3]),
.I2(\d_read_reg_52_reg[31] [8]),
.O(\rdata[8]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT3 #(
.INIT(8'hB8))
\rdata[9]_i_1
(.I0(int_d_o[9]),
.I1(s_axi_pointer_basic_io_ARADDR[3]),
.I2(\d_read_reg_52_reg[31] [9]),
.O(\rdata[9]_i_1_n_0 ));
FDRE \rdata_reg[0]
(.C(ap_clk),
.CE(ar_hs),
.D(rdata[0]),
.Q(s_axi_pointer_basic_io_RDATA[0]),
.R(1'b0));
FDRE \rdata_reg[10]
(.C(ap_clk),
.CE(ar_hs),
.D(\rdata[10]_i_1_n_0 ),
.Q(s_axi_pointer_basic_io_RDATA[10]),
.R(\rdata[31]_i_1_n_0 ));
FDRE \rdata_reg[11]
(.C(ap_clk),
.CE(ar_hs),
.D(\rdata[11]_i_1_n_0 ),
.Q(s_axi_pointer_basic_io_RDATA[11]),
.R(\rdata[31]_i_1_n_0 ));
FDRE \rdata_reg[12]
(.C(ap_clk),
.CE(ar_hs),
.D(\rdata[12]_i_1_n_0 ),
.Q(s_axi_pointer_basic_io_RDATA[12]),
.R(\rdata[31]_i_1_n_0 ));
FDRE \rdata_reg[13]
(.C(ap_clk),
.CE(ar_hs),
.D(\rdata[13]_i_1_n_0 ),
.Q(s_axi_pointer_basic_io_RDATA[13]),
.R(\rdata[31]_i_1_n_0 ));
FDRE \rdata_reg[14]
(.C(ap_clk),
.CE(ar_hs),
.D(\rdata[14]_i_1_n_0 ),
.Q(s_axi_pointer_basic_io_RDATA[14]),
.R(\rdata[31]_i_1_n_0 ));
FDRE \rdata_reg[15]
(.C(ap_clk),
.CE(ar_hs),
.D(\rdata[15]_i_1_n_0 ),
.Q(s_axi_pointer_basic_io_RDATA[15]),
.R(\rdata[31]_i_1_n_0 ));
FDRE \rdata_reg[16]
(.C(ap_clk),
.CE(ar_hs),
.D(\rdata[16]_i_1_n_0 ),
.Q(s_axi_pointer_basic_io_RDATA[16]),
.R(\rdata[31]_i_1_n_0 ));
FDRE \rdata_reg[17]
(.C(ap_clk),
.CE(ar_hs),
.D(\rdata[17]_i_1_n_0 ),
.Q(s_axi_pointer_basic_io_RDATA[17]),
.R(\rdata[31]_i_1_n_0 ));
FDRE \rdata_reg[18]
(.C(ap_clk),
.CE(ar_hs),
.D(\rdata[18]_i_1_n_0 ),
.Q(s_axi_pointer_basic_io_RDATA[18]),
.R(\rdata[31]_i_1_n_0 ));
FDRE \rdata_reg[19]
(.C(ap_clk),
.CE(ar_hs),
.D(\rdata[19]_i_1_n_0 ),
.Q(s_axi_pointer_basic_io_RDATA[19]),
.R(\rdata[31]_i_1_n_0 ));
FDRE \rdata_reg[1]
(.C(ap_clk),
.CE(ar_hs),
.D(rdata[1]),
.Q(s_axi_pointer_basic_io_RDATA[1]),
.R(1'b0));
FDRE \rdata_reg[20]
(.C(ap_clk),
.CE(ar_hs),
.D(\rdata[20]_i_1_n_0 ),
.Q(s_axi_pointer_basic_io_RDATA[20]),
.R(\rdata[31]_i_1_n_0 ));
FDRE \rdata_reg[21]
(.C(ap_clk),
.CE(ar_hs),
.D(\rdata[21]_i_1_n_0 ),
.Q(s_axi_pointer_basic_io_RDATA[21]),
.R(\rdata[31]_i_1_n_0 ));
FDRE \rdata_reg[22]
(.C(ap_clk),
.CE(ar_hs),
.D(\rdata[22]_i_1_n_0 ),
.Q(s_axi_pointer_basic_io_RDATA[22]),
.R(\rdata[31]_i_1_n_0 ));
FDRE \rdata_reg[23]
(.C(ap_clk),
.CE(ar_hs),
.D(\rdata[23]_i_1_n_0 ),
.Q(s_axi_pointer_basic_io_RDATA[23]),
.R(\rdata[31]_i_1_n_0 ));
FDRE \rdata_reg[24]
(.C(ap_clk),
.CE(ar_hs),
.D(\rdata[24]_i_1_n_0 ),
.Q(s_axi_pointer_basic_io_RDATA[24]),
.R(\rdata[31]_i_1_n_0 ));
FDRE \rdata_reg[25]
(.C(ap_clk),
.CE(ar_hs),
.D(\rdata[25]_i_1_n_0 ),
.Q(s_axi_pointer_basic_io_RDATA[25]),
.R(\rdata[31]_i_1_n_0 ));
FDRE \rdata_reg[26]
(.C(ap_clk),
.CE(ar_hs),
.D(\rdata[26]_i_1_n_0 ),
.Q(s_axi_pointer_basic_io_RDATA[26]),
.R(\rdata[31]_i_1_n_0 ));
FDRE \rdata_reg[27]
(.C(ap_clk),
.CE(ar_hs),
.D(\rdata[27]_i_1_n_0 ),
.Q(s_axi_pointer_basic_io_RDATA[27]),
.R(\rdata[31]_i_1_n_0 ));
FDRE \rdata_reg[28]
(.C(ap_clk),
.CE(ar_hs),
.D(\rdata[28]_i_1_n_0 ),
.Q(s_axi_pointer_basic_io_RDATA[28]),
.R(\rdata[31]_i_1_n_0 ));
FDRE \rdata_reg[29]
(.C(ap_clk),
.CE(ar_hs),
.D(\rdata[29]_i_1_n_0 ),
.Q(s_axi_pointer_basic_io_RDATA[29]),
.R(\rdata[31]_i_1_n_0 ));
FDRE \rdata_reg[2]
(.C(ap_clk),
.CE(ar_hs),
.D(rdata[2]),
.Q(s_axi_pointer_basic_io_RDATA[2]),
.R(1'b0));
FDRE \rdata_reg[30]
(.C(ap_clk),
.CE(ar_hs),
.D(\rdata[30]_i_1_n_0 ),
.Q(s_axi_pointer_basic_io_RDATA[30]),
.R(\rdata[31]_i_1_n_0 ));
FDRE \rdata_reg[31]
(.C(ap_clk),
.CE(ar_hs),
.D(\rdata[31]_i_3_n_0 ),
.Q(s_axi_pointer_basic_io_RDATA[31]),
.R(\rdata[31]_i_1_n_0 ));
FDRE \rdata_reg[3]
(.C(ap_clk),
.CE(ar_hs),
.D(rdata[3]),
.Q(s_axi_pointer_basic_io_RDATA[3]),
.R(1'b0));
FDRE \rdata_reg[4]
(.C(ap_clk),
.CE(ar_hs),
.D(\rdata[4]_i_1_n_0 ),
.Q(s_axi_pointer_basic_io_RDATA[4]),
.R(\rdata[31]_i_1_n_0 ));
FDRE \rdata_reg[5]
(.C(ap_clk),
.CE(ar_hs),
.D(\rdata[5]_i_1_n_0 ),
.Q(s_axi_pointer_basic_io_RDATA[5]),
.R(\rdata[31]_i_1_n_0 ));
FDRE \rdata_reg[6]
(.C(ap_clk),
.CE(ar_hs),
.D(\rdata[6]_i_1_n_0 ),
.Q(s_axi_pointer_basic_io_RDATA[6]),
.R(\rdata[31]_i_1_n_0 ));
FDRE \rdata_reg[7]
(.C(ap_clk),
.CE(ar_hs),
.D(rdata[7]),
.Q(s_axi_pointer_basic_io_RDATA[7]),
.R(1'b0));
FDRE \rdata_reg[8]
(.C(ap_clk),
.CE(ar_hs),
.D(\rdata[8]_i_1_n_0 ),
.Q(s_axi_pointer_basic_io_RDATA[8]),
.R(\rdata[31]_i_1_n_0 ));
FDRE \rdata_reg[9]
(.C(ap_clk),
.CE(ar_hs),
.D(\rdata[9]_i_1_n_0 ),
.Q(s_axi_pointer_basic_io_RDATA[9]),
.R(\rdata[31]_i_1_n_0 ));
LUT2 #(
.INIT(4'h8))
\waddr[4]_i_1
(.I0(out[0]),
.I1(s_axi_pointer_basic_io_AWVALID),
.O(waddr));
FDRE \waddr_reg[0]
(.C(ap_clk),
.CE(waddr),
.D(s_axi_pointer_basic_io_AWADDR[0]),
.Q(\waddr_reg_n_0_[0] ),
.R(1'b0));
FDRE \waddr_reg[1]
(.C(ap_clk),
.CE(waddr),
.D(s_axi_pointer_basic_io_AWADDR[1]),
.Q(\waddr_reg_n_0_[1] ),
.R(1'b0));
FDRE \waddr_reg[2]
(.C(ap_clk),
.CE(waddr),
.D(s_axi_pointer_basic_io_AWADDR[2]),
.Q(\waddr_reg_n_0_[2] ),
.R(1'b0));
FDRE \waddr_reg[3]
(.C(ap_clk),
.CE(waddr),
.D(s_axi_pointer_basic_io_AWADDR[3]),
.Q(\waddr_reg_n_0_[3] ),
.R(1'b0));
FDRE \waddr_reg[4]
(.C(ap_clk),
.CE(waddr),
.D(s_axi_pointer_basic_io_AWADDR[4]),
.Q(\waddr_reg_n_0_[4] ),
.R(1'b0));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
module image_filter_Block_proc (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_continue,
ap_idle,
ap_ready,
rows,
cols,
ap_return_0,
ap_return_1,
ap_return_2,
ap_return_3,
ap_return_4,
ap_return_5,
ap_return_6,
ap_return_7,
ap_return_8,
ap_return_9,
ap_return_10,
ap_return_11,
ap_return_12,
ap_return_13,
ap_return_14,
ap_return_15,
ap_return_16,
ap_return_17
);
parameter ap_const_logic_1 = 1'b1;
parameter ap_const_logic_0 = 1'b0;
parameter ap_ST_st1_fsm_0 = 1'b1;
parameter ap_const_lv32_0 = 32'b00000000000000000000000000000000;
parameter ap_const_lv1_1 = 1'b1;
parameter ap_const_lv12_0 = 12'b000000000000;
parameter ap_true = 1'b1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
input ap_continue;
output ap_idle;
output ap_ready;
input [31:0] rows;
input [31:0] cols;
output [11:0] ap_return_0;
output [11:0] ap_return_1;
output [11:0] ap_return_2;
output [11:0] ap_return_3;
output [11:0] ap_return_4;
output [11:0] ap_return_5;
output [11:0] ap_return_6;
output [11:0] ap_return_7;
output [11:0] ap_return_8;
output [11:0] ap_return_9;
output [11:0] ap_return_10;
output [11:0] ap_return_11;
output [11:0] ap_return_12;
output [11:0] ap_return_13;
output [11:0] ap_return_14;
output [11:0] ap_return_15;
output [11:0] ap_return_16;
output [11:0] ap_return_17;
reg ap_done;
reg ap_idle;
reg ap_ready;
reg[11:0] ap_return_0;
reg[11:0] ap_return_1;
reg[11:0] ap_return_2;
reg[11:0] ap_return_3;
reg[11:0] ap_return_4;
reg[11:0] ap_return_5;
reg[11:0] ap_return_6;
reg[11:0] ap_return_7;
reg[11:0] ap_return_8;
reg[11:0] ap_return_9;
reg[11:0] ap_return_10;
reg[11:0] ap_return_11;
reg[11:0] ap_return_12;
reg[11:0] ap_return_13;
reg[11:0] ap_return_14;
reg[11:0] ap_return_15;
reg[11:0] ap_return_16;
reg[11:0] ap_return_17;
reg ap_done_reg = 1'b0;
(* fsm_encoding = "none" *) reg [0:0] ap_CS_fsm = 1'b1;
reg ap_sig_cseq_ST_st1_fsm_0;
reg ap_sig_bdd_20;
reg ap_sig_bdd_52;
wire [11:0] img_0_rows_V_fu_31_p1;
wire [11:0] img_0_cols_V_fu_35_p1;
reg [11:0] ap_return_0_preg = 12'b000000000000;
reg [11:0] ap_return_1_preg = 12'b000000000000;
reg [11:0] ap_return_2_preg = 12'b000000000000;
reg [11:0] ap_return_3_preg = 12'b000000000000;
reg [11:0] ap_return_4_preg = 12'b000000000000;
reg [11:0] ap_return_5_preg = 12'b000000000000;
reg [11:0] ap_return_6_preg = 12'b000000000000;
reg [11:0] ap_return_7_preg = 12'b000000000000;
reg [11:0] ap_return_8_preg = 12'b000000000000;
reg [11:0] ap_return_9_preg = 12'b000000000000;
reg [11:0] ap_return_10_preg = 12'b000000000000;
reg [11:0] ap_return_11_preg = 12'b000000000000;
reg [11:0] ap_return_12_preg = 12'b000000000000;
reg [11:0] ap_return_13_preg = 12'b000000000000;
reg [11:0] ap_return_14_preg = 12'b000000000000;
reg [11:0] ap_return_15_preg = 12'b000000000000;
reg [11:0] ap_return_16_preg = 12'b000000000000;
reg [11:0] ap_return_17_preg = 12'b000000000000;
reg [0:0] ap_NS_fsm;
/// the current state (ap_CS_fsm) of the state machine. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_CS_fsm
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_st1_fsm_0;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
/// ap_done_reg assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_done_reg
if (ap_rst == 1'b1) begin
ap_done_reg <= ap_const_logic_0;
end else begin
if ((ap_const_logic_1 == ap_continue)) begin
ap_done_reg <= ap_const_logic_0;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~ap_sig_bdd_52)) begin
ap_done_reg <= ap_const_logic_1;
end
end
end
/// ap_return_0_preg assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_return_0_preg
if (ap_rst == 1'b1) begin
ap_return_0_preg <= ap_const_lv12_0;
end else begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~ap_sig_bdd_52)) begin
ap_return_0_preg <= img_0_rows_V_fu_31_p1;
end
end
end
/// ap_return_10_preg assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_return_10_preg
if (ap_rst == 1'b1) begin
ap_return_10_preg <= ap_const_lv12_0;
end else begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~ap_sig_bdd_52)) begin
ap_return_10_preg <= img_0_rows_V_fu_31_p1;
end
end
end
/// ap_return_11_preg assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_return_11_preg
if (ap_rst == 1'b1) begin
ap_return_11_preg <= ap_const_lv12_0;
end else begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~ap_sig_bdd_52)) begin
ap_return_11_preg <= img_0_rows_V_fu_31_p1;
end
end
end
/// ap_return_12_preg assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_return_12_preg
if (ap_rst == 1'b1) begin
ap_return_12_preg <= ap_const_lv12_0;
end else begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~ap_sig_bdd_52)) begin
ap_return_12_preg <= img_0_cols_V_fu_35_p1;
end
end
end
/// ap_return_13_preg assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_return_13_preg
if (ap_rst == 1'b1) begin
ap_return_13_preg <= ap_const_lv12_0;
end else begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~ap_sig_bdd_52)) begin
ap_return_13_preg <= img_0_cols_V_fu_35_p1;
end
end
end
/// ap_return_14_preg assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_return_14_preg
if (ap_rst == 1'b1) begin
ap_return_14_preg <= ap_const_lv12_0;
end else begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~ap_sig_bdd_52)) begin
ap_return_14_preg <= img_0_rows_V_fu_31_p1;
end
end
end
/// ap_return_15_preg assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_return_15_preg
if (ap_rst == 1'b1) begin
ap_return_15_preg <= ap_const_lv12_0;
end else begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~ap_sig_bdd_52)) begin
ap_return_15_preg <= img_0_cols_V_fu_35_p1;
end
end
end
/// ap_return_16_preg assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_return_16_preg
if (ap_rst == 1'b1) begin
ap_return_16_preg <= ap_const_lv12_0;
end else begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~ap_sig_bdd_52)) begin
ap_return_16_preg <= img_0_rows_V_fu_31_p1;
end
end
end
/// ap_return_17_preg assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_return_17_preg
if (ap_rst == 1'b1) begin
ap_return_17_preg <= ap_const_lv12_0;
end else begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~ap_sig_bdd_52)) begin
ap_return_17_preg <= img_0_cols_V_fu_35_p1;
end
end
end
/// ap_return_1_preg assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_return_1_preg
if (ap_rst == 1'b1) begin
ap_return_1_preg <= ap_const_lv12_0;
end else begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~ap_sig_bdd_52)) begin
ap_return_1_preg <= img_0_rows_V_fu_31_p1;
end
end
end
/// ap_return_2_preg assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_return_2_preg
if (ap_rst == 1'b1) begin
ap_return_2_preg <= ap_const_lv12_0;
end else begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~ap_sig_bdd_52)) begin
ap_return_2_preg <= img_0_cols_V_fu_35_p1;
end
end
end
/// ap_return_3_preg assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_return_3_preg
if (ap_rst == 1'b1) begin
ap_return_3_preg <= ap_const_lv12_0;
end else begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~ap_sig_bdd_52)) begin
ap_return_3_preg <= img_0_cols_V_fu_35_p1;
end
end
end
/// ap_return_4_preg assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_return_4_preg
if (ap_rst == 1'b1) begin
ap_return_4_preg <= ap_const_lv12_0;
end else begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~ap_sig_bdd_52)) begin
ap_return_4_preg <= img_0_rows_V_fu_31_p1;
end
end
end
/// ap_return_5_preg assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_return_5_preg
if (ap_rst == 1'b1) begin
ap_return_5_preg <= ap_const_lv12_0;
end else begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~ap_sig_bdd_52)) begin
ap_return_5_preg <= img_0_cols_V_fu_35_p1;
end
end
end
/// ap_return_6_preg assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_return_6_preg
if (ap_rst == 1'b1) begin
ap_return_6_preg <= ap_const_lv12_0;
end else begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~ap_sig_bdd_52)) begin
ap_return_6_preg <= img_0_rows_V_fu_31_p1;
end
end
end
/// ap_return_7_preg assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_return_7_preg
if (ap_rst == 1'b1) begin
ap_return_7_preg <= ap_const_lv12_0;
end else begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~ap_sig_bdd_52)) begin
ap_return_7_preg <= img_0_rows_V_fu_31_p1;
end
end
end
/// ap_return_8_preg assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_return_8_preg
if (ap_rst == 1'b1) begin
ap_return_8_preg <= ap_const_lv12_0;
end else begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~ap_sig_bdd_52)) begin
ap_return_8_preg <= img_0_cols_V_fu_35_p1;
end
end
end
/// ap_return_9_preg assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_return_9_preg
if (ap_rst == 1'b1) begin
ap_return_9_preg <= ap_const_lv12_0;
end else begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~ap_sig_bdd_52)) begin
ap_return_9_preg <= img_0_cols_V_fu_35_p1;
end
end
end
/// ap_done assign process. ///
always @ (ap_done_reg or ap_sig_cseq_ST_st1_fsm_0 or ap_sig_bdd_52)
begin
if (((ap_const_logic_1 == ap_done_reg) | ((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~ap_sig_bdd_52))) begin
ap_done = ap_const_logic_1;
end else begin
ap_done = ap_const_logic_0;
end
end
/// ap_idle assign process. ///
always @ (ap_start or ap_sig_cseq_ST_st1_fsm_0)
begin
if ((~(ap_const_logic_1 == ap_start) & (ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0))) begin
ap_idle = ap_const_logic_1;
end else begin
ap_idle = ap_const_logic_0;
end
end
/// ap_ready assign process. ///
always @ (ap_sig_cseq_ST_st1_fsm_0 or ap_sig_bdd_52)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~ap_sig_bdd_52)) begin
ap_ready = ap_const_logic_1;
end else begin
ap_ready = ap_const_logic_0;
end
end
/// ap_return_0 assign process. ///
always @ (ap_sig_cseq_ST_st1_fsm_0 or ap_sig_bdd_52 or img_0_rows_V_fu_31_p1 or ap_return_0_preg)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~ap_sig_bdd_52)) begin
ap_return_0 = img_0_rows_V_fu_31_p1;
end else begin
ap_return_0 = ap_return_0_preg;
end
end
/// ap_return_1 assign process. ///
always @ (ap_sig_cseq_ST_st1_fsm_0 or ap_sig_bdd_52 or img_0_rows_V_fu_31_p1 or ap_return_1_preg)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~ap_sig_bdd_52)) begin
ap_return_1 = img_0_rows_V_fu_31_p1;
end else begin
ap_return_1 = ap_return_1_preg;
end
end
/// ap_return_10 assign process. ///
always @ (ap_sig_cseq_ST_st1_fsm_0 or ap_sig_bdd_52 or img_0_rows_V_fu_31_p1 or ap_return_10_preg)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~ap_sig_bdd_52)) begin
ap_return_10 = img_0_rows_V_fu_31_p1;
end else begin
ap_return_10 = ap_return_10_preg;
end
end
/// ap_return_11 assign process. ///
always @ (ap_sig_cseq_ST_st1_fsm_0 or ap_sig_bdd_52 or img_0_rows_V_fu_31_p1 or ap_return_11_preg)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~ap_sig_bdd_52)) begin
ap_return_11 = img_0_rows_V_fu_31_p1;
end else begin
ap_return_11 = ap_return_11_preg;
end
end
/// ap_return_12 assign process. ///
always @ (ap_sig_cseq_ST_st1_fsm_0 or ap_sig_bdd_52 or img_0_cols_V_fu_35_p1 or ap_return_12_preg)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~ap_sig_bdd_52)) begin
ap_return_12 = img_0_cols_V_fu_35_p1;
end else begin
ap_return_12 = ap_return_12_preg;
end
end
/// ap_return_13 assign process. ///
always @ (ap_sig_cseq_ST_st1_fsm_0 or ap_sig_bdd_52 or img_0_cols_V_fu_35_p1 or ap_return_13_preg)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~ap_sig_bdd_52)) begin
ap_return_13 = img_0_cols_V_fu_35_p1;
end else begin
ap_return_13 = ap_return_13_preg;
end
end
/// ap_return_14 assign process. ///
always @ (ap_sig_cseq_ST_st1_fsm_0 or ap_sig_bdd_52 or img_0_rows_V_fu_31_p1 or ap_return_14_preg)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~ap_sig_bdd_52)) begin
ap_return_14 = img_0_rows_V_fu_31_p1;
end else begin
ap_return_14 = ap_return_14_preg;
end
end
/// ap_return_15 assign process. ///
always @ (ap_sig_cseq_ST_st1_fsm_0 or ap_sig_bdd_52 or img_0_cols_V_fu_35_p1 or ap_return_15_preg)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~ap_sig_bdd_52)) begin
ap_return_15 = img_0_cols_V_fu_35_p1;
end else begin
ap_return_15 = ap_return_15_preg;
end
end
/// ap_return_16 assign process. ///
always @ (ap_sig_cseq_ST_st1_fsm_0 or ap_sig_bdd_52 or img_0_rows_V_fu_31_p1 or ap_return_16_preg)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~ap_sig_bdd_52)) begin
ap_return_16 = img_0_rows_V_fu_31_p1;
end else begin
ap_return_16 = ap_return_16_preg;
end
end
/// ap_return_17 assign process. ///
always @ (ap_sig_cseq_ST_st1_fsm_0 or ap_sig_bdd_52 or img_0_cols_V_fu_35_p1 or ap_return_17_preg)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~ap_sig_bdd_52)) begin
ap_return_17 = img_0_cols_V_fu_35_p1;
end else begin
ap_return_17 = ap_return_17_preg;
end
end
/// ap_return_2 assign process. ///
always @ (ap_sig_cseq_ST_st1_fsm_0 or ap_sig_bdd_52 or img_0_cols_V_fu_35_p1 or ap_return_2_preg)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~ap_sig_bdd_52)) begin
ap_return_2 = img_0_cols_V_fu_35_p1;
end else begin
ap_return_2 = ap_return_2_preg;
end
end
/// ap_return_3 assign process. ///
always @ (ap_sig_cseq_ST_st1_fsm_0 or ap_sig_bdd_52 or img_0_cols_V_fu_35_p1 or ap_return_3_preg)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~ap_sig_bdd_52)) begin
ap_return_3 = img_0_cols_V_fu_35_p1;
end else begin
ap_return_3 = ap_return_3_preg;
end
end
/// ap_return_4 assign process. ///
always @ (ap_sig_cseq_ST_st1_fsm_0 or ap_sig_bdd_52 or img_0_rows_V_fu_31_p1 or ap_return_4_preg)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~ap_sig_bdd_52)) begin
ap_return_4 = img_0_rows_V_fu_31_p1;
end else begin
ap_return_4 = ap_return_4_preg;
end
end
/// ap_return_5 assign process. ///
always @ (ap_sig_cseq_ST_st1_fsm_0 or ap_sig_bdd_52 or img_0_cols_V_fu_35_p1 or ap_return_5_preg)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~ap_sig_bdd_52)) begin
ap_return_5 = img_0_cols_V_fu_35_p1;
end else begin
ap_return_5 = ap_return_5_preg;
end
end
/// ap_return_6 assign process. ///
always @ (ap_sig_cseq_ST_st1_fsm_0 or ap_sig_bdd_52 or img_0_rows_V_fu_31_p1 or ap_return_6_preg)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~ap_sig_bdd_52)) begin
ap_return_6 = img_0_rows_V_fu_31_p1;
end else begin
ap_return_6 = ap_return_6_preg;
end
end
/// ap_return_7 assign process. ///
always @ (ap_sig_cseq_ST_st1_fsm_0 or ap_sig_bdd_52 or img_0_rows_V_fu_31_p1 or ap_return_7_preg)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~ap_sig_bdd_52)) begin
ap_return_7 = img_0_rows_V_fu_31_p1;
end else begin
ap_return_7 = ap_return_7_preg;
end
end
/// ap_return_8 assign process. ///
always @ (ap_sig_cseq_ST_st1_fsm_0 or ap_sig_bdd_52 or img_0_cols_V_fu_35_p1 or ap_return_8_preg)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~ap_sig_bdd_52)) begin
ap_return_8 = img_0_cols_V_fu_35_p1;
end else begin
ap_return_8 = ap_return_8_preg;
end
end
/// ap_return_9 assign process. ///
always @ (ap_sig_cseq_ST_st1_fsm_0 or ap_sig_bdd_52 or img_0_cols_V_fu_35_p1 or ap_return_9_preg)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~ap_sig_bdd_52)) begin
ap_return_9 = img_0_cols_V_fu_35_p1;
end else begin
ap_return_9 = ap_return_9_preg;
end
end
/// ap_sig_cseq_ST_st1_fsm_0 assign process. ///
always @ (ap_sig_bdd_20)
begin
if (ap_sig_bdd_20) begin
ap_sig_cseq_ST_st1_fsm_0 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st1_fsm_0 = ap_const_logic_0;
end
end
/// the next state (ap_NS_fsm) of the state machine. ///
always @ (ap_CS_fsm or ap_sig_bdd_52)
begin
case (ap_CS_fsm)
ap_ST_st1_fsm_0 :
begin
ap_NS_fsm = ap_ST_st1_fsm_0;
end
default :
begin
ap_NS_fsm = 'bx;
end
endcase
end
/// ap_sig_bdd_20 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_20 = (ap_CS_fsm[ap_const_lv32_0] == ap_const_lv1_1);
end
/// ap_sig_bdd_52 assign process. ///
always @ (ap_start or ap_done_reg)
begin
ap_sig_bdd_52 = ((ap_start == ap_const_logic_0) | (ap_done_reg == ap_const_logic_1));
end
assign img_0_cols_V_fu_35_p1 = cols[11:0];
assign img_0_rows_V_fu_31_p1 = rows[11:0];
endmodule //image_filter_Block_proc
|
//i2s_writer.v
/*
Distributed under the MIT license.
Copyright (c) 2011 Dave McCoy ([email protected])
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
`timescale 1 ns/1 ps
module i2s_writer (
rst,
clk,
//control/status
enable,
starved,
//clock
i2s_clock,
//mem controller interface
audio_data_request,
audio_data_ack,
audio_data,
audio_lr_bit,
//physical connections
i2s_data,
i2s_lr
);
parameter DATA_SIZE = 32;
input rst;
input clk;
input enable;
input i2s_clock;
output reg audio_data_request;
input audio_data_ack;
input [23:0] audio_data;
input audio_lr_bit;
output reg i2s_data;
output reg i2s_lr;
output reg starved;
//parameter
parameter START = 4'h0;
parameter REQUEST_DATA = 4'h1;
parameter DATA_READY = 4'h2;
//registers/wires
reg [7:0] bit_count;
reg [23:0] new_audio_data;
reg new_audio_lr_bit;
reg [23:0] audio_shifter;
//writer state machine
reg [3:0] state;
//asynchronous logic
//synchronous logic
always @ (posedge rst or negedge i2s_clock) begin
if (rst) begin
bit_count <= DATA_SIZE -1;
new_audio_data <= 0;
new_audio_lr_bit <= 0;
audio_shifter <= 0;
state <= START;
starved <= 0;
i2s_data <= 0;
i2s_lr <= 0;
audio_data_request <= 0;
end
else if (enable) begin
starved <= 0;
case (state)
START: begin
audio_data_request <= 1;
if (audio_data_ack) begin
audio_data_request <= 0;
state <= DATA_READY;
new_audio_data <= {1'b0, audio_data[23:1]};
//new_audio_data <= audio_data[23:0];
new_audio_lr_bit <= audio_lr_bit;
end
end
REQUEST_DATA: begin
audio_data_request <= 1;
if (audio_data_ack) begin
audio_data_request <= 0;
state <= DATA_READY;
new_audio_data <= audio_data;
new_audio_lr_bit <= audio_lr_bit;
end
end
DATA_READY: begin
//wait for the bit count to reach 0
if (bit_count == DATA_SIZE - 2) begin
state <= REQUEST_DATA;
end
end
default: begin
state <= REQUEST_DATA;
end
endcase
//continusously shift data out
if (bit_count == 0) begin
if (state == DATA_READY) begin
//put the new data into the shifter and reset the bit_count
bit_count <= DATA_SIZE - 1;
audio_shifter <= new_audio_data;
i2s_lr <= new_audio_lr_bit;
new_audio_data <= 0;
new_audio_lr_bit<= 0;
end
else begin
//starved, can't do anything
starved <= 1;
i2s_data <= 0;
end
end
else begin
//shift out data
bit_count <= bit_count - 1;
i2s_data <= audio_shifter[23];
audio_shifter <= {audio_shifter[22:0], 1'b0};
end
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__PROBEC_P_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__PROBEC_P_FUNCTIONAL_PP_V
/**
* probec_p: Virtual current probe point.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__probec_p (
X ,
A ,
VGND,
VNB ,
VPB ,
VPWR
);
// Module ports
output X ;
input A ;
input VGND;
input VNB ;
input VPB ;
input VPWR;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__PROBEC_P_FUNCTIONAL_PP_V
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
// Date : Thu Oct 26 22:45:02 2017
// Host : Juice-Laptop running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/RATCPU/Experiments/Experiment7-Its_Alive/IPI-BD/RAT/ip/RAT_prog_rom_0_0/RAT_prog_rom_0_0_stub.v
// Design : RAT_prog_rom_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "prog_rom,Vivado 2016.4" *)
module RAT_prog_rom_0_0(ADDRESS, INSTRUCTION, CLK)
/* synthesis syn_black_box black_box_pad_pin="ADDRESS[9:0],INSTRUCTION[17:0],CLK" */;
input [9:0]ADDRESS;
output [17:0]INSTRUCTION;
input CLK;
endmodule
|
/*
** -----------------------------------------------------------------------------**
** encoderDCAC353.v
**
** RLL encoder for JPEG compressor
**
** Copyright (C) 2002-2008 Elphel, Inc
**
** -----------------------------------------------------------------------------**
** This file is part of X353
** X353 is free software - hardware description language (HDL) code.
**
** This program is free software: you can redistribute it and/or modify
** it under the terms of the GNU General Public License as published by
** the Free Software Foundation, either version 3 of the License, or
** (at your option) any later version.
**
** This program is distributed in the hope that it will be useful,
** but WITHOUT ANY WARRANTY; without even the implied warranty of
** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
** GNU General Public License for more details.
**
** You should have received a copy of the GNU General Public License
** along with this program. If not, see <http://www.gnu.org/licenses/>.
** -----------------------------------------------------------------------------**
**
*/
// Accepts 13-bits signed data (only 12-bit can be ecoded), so DC difference (to be encoded) is limited (saturated) to 12 bits, not the value itself
// AC - always limited to 800 .. 7ff
module encoderDCAC(clk,
en,
// firsti, // was "first MCU in a frame" (@ stb)
lasti, // was "last MCU in a frame" (@ stb)
first_blocki, // first block in frame - save fifo write address (@ stb)
comp_numberi, // [2:0] component number 0..2 in color, 0..3 - in jp4diff, >= 4 - don't use (@ stb)
comp_firsti, // fitst this component in a frame (reset DC) (@ stb)
comp_colori, // use color - huffman? (@ stb)
comp_lastinmbi, // last component in a macroblock (@ stb) is it needed?
stb, // strobe that writes firsti, lasti, tni,average
zdi, // [11:0] zigzag-reordered data input
first_blockz, // first block input (@zds)
zds, // strobe - one ahead of the DC component output
last, //
do,
dv
);
input clk;
input en;
// input firsti;
input lasti;
input first_blocki; // first block in frame - save fifo write address (@ stb)
input [2:0] comp_numberi; // [2:0] component number 0..2 in color, 0..3 - in jp4diff, >= 4 - don't use (@ stb)
input comp_firsti; // fitst this component in a frame (reset DC) (@ stb)
input comp_colori; // use color - huffman? (@ stb)
input comp_lastinmbi; // last component in a macroblock (@ stb)
input stb;
input [12:0] zdi;
input first_blockz; // first block input (@zds)
input zds;
output last;
output [15:0] do;
output dv;
// reg [2:0] ic;
// reg [2:0] oc;
reg last;
// 8x13 DC storage memory
reg [12:0] dc_mem[7:0];
reg [12:0] dc_diff0, dc_diff;
wire [11:0] dc_diff_limited= (dc_diff[12]==dc_diff[11])? dc_diff[11:0] : {~dc_diff[11],{11{dc_diff[11]}}}; // difference (to be encoded) limited to fit 12 bits
reg [12:0] dc_restored; // corrected DC value of the current block, compensated to fit difference to 12 bits
reg [5:0] rll_cntr;
reg [15:0] do;
// reg dv0;
reg dv;
//
reg [5:0] cntr;
// reg ac_on;
reg [11:0] ac_in;
wire izero=(ac_in[11:0]==12'b0);
reg [14:0] val_r; // DC diff/AC values to be sent out, registered
reg DCACen; // enable DC/AC (2 cycles ahead of do
wire rll_out;
// wire eob_out;
wire pre_dv;
reg was_nonzero_AC;
reg [12:0] zdi_d;
reg [3:0] zds_d;
// wire dc_mem_we= zds_d[3]; // not needed
wire DC_tosend= zds_d[2];
wire pre_DCACen= zds_d[1];
wire [2:0] comp_numbero; // [2:0] component number 0..2 in color, 0..3 - in jp4diff, >= 4 - don't use
wire comp_firsto; // first this component in a frame (reset DC)
wire comp_coloro; // use color - huffman?
// wire first_blocko; // first block in frame - save fifo write address
wire comp_lastinmbo; // last component in a macroblock
wire lasto; // last macroblock in a frame
reg [2:0] block_mem_ra;
reg [2:0] block_mem_wa;
reg [2:0] block_mem_wa_save;
reg [6:0] block_mem[0:7];
wire [6:0] block_mem_o=block_mem[block_mem_ra[2:0]];
assign comp_numbero[2:0]= block_mem_o[2:0];
assign comp_firsto= block_mem_o[3];
assign comp_coloro= block_mem_o[4];
// assign first_blocko= block_mem_o[5];
assign comp_lastinmbo= block_mem_o[5];
assign lasto= block_mem_o[6];
always @ (posedge clk) begin
if (stb) block_mem[block_mem_wa[2:0]] <= {lasti, comp_lastinmbi, /*first_blocki,*/ comp_colori,comp_firsti,comp_numberi[2:0]};
if (!en) block_mem_wa[2:0] <= 3'h0;
else if (stb) block_mem_wa[2:0] <= block_mem_wa[2:0] +1;
if (stb && first_blocki) block_mem_wa_save[2:0] <= block_mem_wa[2:0];
if (!en) block_mem_ra[2:0] <= 3'h0;
else if (zds) block_mem_ra[2:0] <= first_blockz?block_mem_wa_save[2:0]:(block_mem_ra[2:0] +1);
end
assign rll_out= ((val_r[12] && !val_r[14]) || (ac_in[11:0]!=12'b0)) && (rll_cntr[5:0]!=6'b0);
assign pre_dv=rll_out || val_r[14] || was_nonzero_AC;
always @ (posedge clk) begin
val_r[14:0] <={ DC_tosend?
{en,
comp_coloro,
comp_lastinmbo && lasto, // last component's in a frame DC coefficient
dc_diff_limited[11:0]}:
{2'b0,
(cntr[5:0]==6'h3f),
ac_in[11:0]}};
was_nonzero_AC <= en && (ac_in[11:0]!=12'b0) && DCACen;
if (pre_dv) do <= rll_out? {3'b0,val_r[12],6'b0,rll_cntr[5:0]}:{1'b1,val_r[14:0]};
dv <= pre_dv;
DCACen <= en && (pre_DCACen || (DCACen && (cntr[5:0]!=6'h3f))); // adjust
if (!DCACen) cntr[5:0] <=6'b0;
else cntr[5:0] <=cntr[5:0]+1;
end
always @ (posedge clk) begin
zdi_d[12:0] <= zdi[12:0];
ac_in[11:0] <= (zdi_d[12]==zdi_d[11])? zdi_d[11:0]:{~zdi_d[11],{11{zdi_d[11]}}}; // always // delay + saturation
if (DC_tosend || !izero || !DCACen) rll_cntr[5:0] <= 6'h0;
else if (DCACen) rll_cntr[5:0] <= rll_cntr[5:0] +1 ;
if (DC_tosend) last <= lasto;
end
// DC components
always @ (posedge clk) begin
zds_d[3:0] <= {zds_d[2:0], zds};
if (zds_d[0]) dc_diff0[12:0] <= comp_firsto?13'b0:dc_mem[comp_numbero[2:0]];
if (zds_d[1]) dc_diff [12:0] <= zdi_d[12:0]-dc_diff0[12:0];
if (zds_d[2]) dc_restored[12:0] <= dc_diff0[12:0] + {dc_diff_limited[11],dc_diff_limited[11:0]};
if (zds_d[3]) dc_mem[comp_numbero[2:0]] <= dc_restored[12:0];
end
// Generate output stream to facilitate huffman encoding. The data will go to FIFO (16x) to compensate for possible long Huffman codes
// and/or zero-byte insertions
// format:
// {2'b11, color,last block, dc[11:0]} - DC data
// {2'b10, 1'b0, last coeff, ac[11:0]} - AC data (last coeff is set if it is last- 63-rd AC coefficient)
// {2'h00, 2'b00, 6'b0,rll[ 5:0]} - RLL zeroes.
// {2'h00, 2'b01, 6'b0,rll[ 5:0]} - end of block. lower 6 bits will have length that should be ignored
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
// Date : Fri Oct 27 10:21:12 2017
// Host : Juice-Laptop running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/RATCPU/Experiments/Experiment8-GeterDone/IPI-BD/RAT/ip/RAT_xlslice_0_1/RAT_xlslice_0_1_stub.v
// Design : RAT_xlslice_0_1
// Purpose : Stub declaration of top-level module interface
// Device : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "xlslice,Vivado 2016.4" *)
module RAT_xlslice_0_1(Din, Dout)
/* synthesis syn_black_box black_box_pad_pin="Din[9:0],Dout[7:0]" */;
input [9:0]Din;
output [7:0]Dout;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__CLKDLYINV3SD3_BLACKBOX_V
`define SKY130_FD_SC_HS__CLKDLYINV3SD3_BLACKBOX_V
/**
* clkdlyinv3sd3: Clock Delay Inverter 3-stage 0.50um length inner
* stage gate.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__clkdlyinv3sd3 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__CLKDLYINV3SD3_BLACKBOX_V
|
/*
* Copyright (c) 2015, Arch Labolatory
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
`default_nettype wire
`timescale 1 ps / 1 ps
module system (
output wire clk_sys,
input wire reset_sys,
input wire clk_vga,
input wire reset_vga,
input wire clk_200m,
input wire dram_rst_in,
output wire dram_rst_out,
inout wire [15:0] DDR2DQ,
inout wire [1:0] DDR2DQS_N,
inout wire [1:0] DDR2DQS_P,
output wire [12:0] DDR2ADDR,
output wire [2:0] DDR2BA,
output wire DDR2RAS_N,
output wire DDR2CAS_N,
output wire DDR2WE_N,
output wire [0:0] DDR2CK_P,
output wire [0:0] DDR2CK_N,
output wire [0:0] DDR2CKE,
output wire [0:0] DDR2CS_N,
output wire [1:0] DDR2DM,
output wire [0:0] DDR2ODT,
output wire reset_only_ao486,
output wire vga_clock,
output wire vga_sync_n,
output wire vga_blank_n,
output wire vga_horiz_sync,
output wire vga_vert_sync,
output wire [7:0] vga_r,
output wire [7:0] vga_g,
output wire [7:0] vga_b,
inout wire ps2_kbclk,
inout wire ps2_kbdat,
inout wire [3:0] sd_dat,
inout wire sd_cmd,
output wire sd_clk,
output wire sdram_read,
output wire sdram_write,
output wire dram_read,
output wire dram_write
);
wire [7:0] ide_3f6_writedata;
wire ide_3f6_write;
wire ide_3f6_read;
wire [7:0] ide_3f6_readdata;
wire pic_interrupt_do;
wire [7:0] pic_interrupt_vector;
wire ao486_interrupt_done;
wire bios_loader_waitrequest;
wire [31:0] bios_loader_writedata;
wire [27:0] bios_loader_address;
wire bios_loader_write;
wire bios_loader_read;
wire [31:0] bios_loader_readdata;
wire bios_loader_debugaccess;
wire [3:0] bios_loader_byteenable;
wire hdd_avalon_master_waitrequest;
wire [31:0] hdd_avalon_master_writedata;
wire [31:0] hdd_avalon_master_address;
wire hdd_avalon_master_write;
wire hdd_avalon_master_read;
wire [31:0] hdd_avalon_master_readdata;
wire hdd_avalon_master_readdatavalid;
wire ao486_avalon_memory_waitrequest;
wire [2:0] ao486_avalon_memory_burstcount;
wire [31:0] ao486_avalon_memory_writedata;
wire [31:0] ao486_avalon_memory_address;
wire ao486_avalon_memory_write;
wire ao486_avalon_memory_read;
wire [31:0] ao486_avalon_memory_readdata;
wire ao486_avalon_memory_readdatavalid;
wire [3:0] ao486_avalon_memory_byteenable;
wire ao486_avalon_io_waitrequest;
wire [31:0] ao486_avalon_io_writedata;
wire [15:0] ao486_avalon_io_address;
wire ao486_avalon_io_write;
wire ao486_avalon_io_read;
wire [31:0] ao486_avalon_io_readdata;
wire ao486_avalon_io_readdatavalid;
wire [3:0] ao486_avalon_io_byteenable;
wire [3:0] vga_io_b_address;
wire vga_io_b_write;
wire [7:0] vga_io_b_writedata;
wire vga_io_b_read;
wire [7:0] vga_io_b_readdata;
wire [3:0] vga_io_c_address;
wire vga_io_c_write;
wire [7:0] vga_io_c_writedata;
wire vga_io_c_read;
wire [7:0] vga_io_c_readdata;
wire [3:0] vga_io_d_address;
wire vga_io_d_write;
wire [7:0] vga_io_d_writedata;
wire vga_io_d_read;
wire [7:0] vga_io_d_readdata;
wire [2:0] ps2_io_address;
wire ps2_io_write;
wire [7:0] ps2_io_writedata;
wire ps2_io_read;
wire [7:0] ps2_io_readdata;
wire [3:0] ps2_sysctl_address;
wire ps2_sysctl_write;
wire [7:0] ps2_sysctl_writedata;
wire ps2_sysctl_read;
wire [7:0] ps2_sysctl_readdata;
wire [1:0] pit_io_address;
wire pit_io_write;
wire [7:0] pit_io_writedata;
wire pit_io_read;
wire [7:0] pit_io_readdata;
wire rtc_io_address;
wire rtc_io_write;
wire [7:0] rtc_io_writedata;
wire rtc_io_read;
wire [7:0] rtc_io_readdata;
wire pic_master_address;
wire pic_master_write;
wire [7:0] pic_master_writedata;
wire pic_master_read;
wire [7:0] pic_master_readdata;
wire pic_slave_address;
wire pic_slave_write;
wire [7:0] pic_slave_writedata;
wire pic_slave_read;
wire [7:0] pic_slave_readdata;
wire hdd_io_address;
wire hdd_io_write;
wire [31:0] hdd_io_writedata;
wire hdd_io_read;
wire [31:0] hdd_io_readdata;
wire [3:0] hdd_io_byteenable;
wire pc_bus_mem_waitrequest;
wire [2:0] pc_bus_mem_burstcount;
wire [31:0] pc_bus_mem_writedata;
wire [29:0] pc_bus_mem_address;
wire pc_bus_mem_write;
wire pc_bus_mem_read;
wire [31:0] pc_bus_mem_readdata;
wire pc_bus_mem_readdatavalid;
wire [3:0] pc_bus_mem_byteenable;
wire pc_bus_vga_waitrequest;
wire [2:0] pc_bus_vga_burstcount;
wire [31:0] pc_bus_vga_writedata;
wire [31:0] pc_bus_vga_address;
wire pc_bus_vga_write;
wire pc_bus_vga_read;
wire [31:0] pc_bus_vga_readdata;
wire pc_bus_vga_readdatavalid;
wire [3:0] pc_bus_vga_byteenable;
wire [16:0] vga_mem_address;
wire vga_mem_read;
wire [7:0] vga_mem_readdata;
wire vga_mem_write;
wire [7:0] vga_mem_writedata;
wire [8:0] hdd_sd_slave_address;
wire hdd_sd_slave_read;
wire [31:0] hdd_sd_slave_readdata;
wire hdd_sd_slave_write;
wire [31:0] hdd_sd_slave_writedata;
wire [24:0] sdram_address;
wire [3:0] sdram_byteenable;
wire [31:0] sdram_readdata;
wire [31:0] sdram_writedata;
wire sdram_waitrequest;
wire sdram_readdatavalid;
wire [31:0] pc_bus_sdram_address;
wire pc_bus_sdram_read;
wire [31:0] pc_bus_sdram_readdata;
wire pc_bus_sdram_write;
wire [31:0] pc_bus_sdram_writedata;
wire pc_bus_sdram_waitrequest;
wire pc_bus_sdram_readdatavalid;
wire [2:0] pc_bus_sdram_burstcount;
wire [3:0] pc_bus_sdram_byteenable;
wire [31:0] driver_sd_avm_address;
wire driver_sd_avm_read;
wire [31:0] driver_sd_avm_readdata;
wire driver_sd_avm_write;
wire [31:0] driver_sd_avm_writedata;
wire driver_sd_avm_waitrequest;
wire driver_sd_avm_readdatavalid;
wire [31:0] driver_sd_avm_readdata_from_sdram;
wire driver_sd_avm_readdatavalid_from_sdram;
wire driver_sd_avm_waitrequest_from_sdram;
wire ps2_irq_keyb;
wire ps2_irq_mouse;
wire pit_irq;
wire rtc_irq;
wire floppy_irq;
wire hdd_irq;
wire [15:0] pic_interrupt_input;
wire ao486_rst;
assign reset_only_ao486 = ao486_rst;
wire [1:0] driver_sd_avs_address;
wire driver_sd_avs_read;
wire [31:0] driver_sd_avs_readdata;
wire driver_sd_avs_write;
wire [31:0] driver_sd_avs_writedata;
wire [26:0] dram_address;
wire [127:0] dram_writedata;
wire [127:0] dram_readdata;
wire dram_readdatavalid;
wire dram_waitrequest;
ao486 ao486 (
.clk (clk_sys),
.rst (ao486_rst),
.avm_address (ao486_avalon_memory_address),
.avm_writedata (ao486_avalon_memory_writedata),
.avm_byteenable (ao486_avalon_memory_byteenable),
.avm_burstcount (ao486_avalon_memory_burstcount),
.avm_write (ao486_avalon_memory_write),
.avm_read (ao486_avalon_memory_read),
.avm_waitrequest (ao486_avalon_memory_waitrequest),
.avm_readdatavalid (ao486_avalon_memory_readdatavalid),
.avm_readdata (ao486_avalon_memory_readdata),
.interrupt_do (pic_interrupt_do),
.interrupt_vector (pic_interrupt_vector),
.interrupt_done (ao486_interrupt_done),
.avalon_io_address (ao486_avalon_io_address),
.avalon_io_byteenable (ao486_avalon_io_byteenable),
.avalon_io_read (ao486_avalon_io_read),
.avalon_io_readdatavalid (ao486_avalon_io_readdatavalid),
.avalon_io_readdata (ao486_avalon_io_readdata),
.avalon_io_write (ao486_avalon_io_write),
.avalon_io_writedata (ao486_avalon_io_writedata),
.avalon_io_waitrequest (ao486_avalon_io_waitrequest)
);
bios_loader bios_loader (
.clk (clk_sys),
.rst (reset_sys),
.address (bios_loader_address),
.byteenable (bios_loader_byteenable),
.read (bios_loader_read),
.readdata (bios_loader_readdata),
.waitrequest (bios_loader_waitrequest),
.write (bios_loader_write),
.writedata (bios_loader_writedata)
);
pc_bus pc_bus (
.clk (clk_sys),
.mem_address (pc_bus_mem_address),
.mem_byteenable (pc_bus_mem_byteenable),
.mem_read (pc_bus_mem_read),
.mem_readdata (pc_bus_mem_readdata),
.mem_write (pc_bus_mem_write),
.mem_writedata (pc_bus_mem_writedata),
.mem_waitrequest (pc_bus_mem_waitrequest),
.mem_readdatavalid (pc_bus_mem_readdatavalid),
.mem_burstcount (pc_bus_mem_burstcount),
.rst (reset_sys),
.vga_address (pc_bus_vga_address),
.vga_byteenable (pc_bus_vga_byteenable),
.vga_read (pc_bus_vga_read),
.vga_readdata (pc_bus_vga_readdata),
.vga_write (pc_bus_vga_write),
.vga_writedata (pc_bus_vga_writedata),
.vga_waitrequest (pc_bus_vga_waitrequest),
.vga_readdatavalid (pc_bus_vga_readdatavalid),
.vga_burstcount (pc_bus_vga_burstcount),
.sdram_address (pc_bus_sdram_address),
.sdram_byteenable (pc_bus_sdram_byteenable),
.sdram_read (pc_bus_sdram_read),
.sdram_readdata (pc_bus_sdram_readdata),
.sdram_write (pc_bus_sdram_write),
.sdram_writedata (pc_bus_sdram_writedata),
.sdram_waitrequest (pc_bus_sdram_waitrequest),
.sdram_readdatavalid (pc_bus_sdram_readdatavalid),
.sdram_burstcount (pc_bus_sdram_burstcount)
);
vga vga (
.io_b_address (vga_io_b_address),
.io_b_read (vga_io_b_read),
.io_b_readdata (vga_io_b_readdata),
.io_b_write (vga_io_b_write),
.io_b_writedata (vga_io_b_writedata),
.io_c_address (vga_io_c_address),
.io_c_read (vga_io_c_read),
.io_c_readdata (vga_io_c_readdata),
.io_c_write (vga_io_c_write),
.io_c_writedata (vga_io_c_writedata),
.io_d_address (vga_io_d_address),
.io_d_read (vga_io_d_read),
.io_d_readdata (vga_io_d_readdata),
.io_d_write (vga_io_d_write),
.io_d_writedata (vga_io_d_writedata),
.mem_address (vga_mem_address),
.mem_read (vga_mem_read),
.mem_readdata (vga_mem_readdata),
.mem_write (vga_mem_write),
.mem_writedata (vga_mem_writedata),
.clk_sys (clk_sys),
.clk_26 (clk_vga),
.rst (reset_vga),
.vga_clock (vga_clock),
.vga_sync_n (vga_sync_n),
.vga_blank_n (vga_blank_n),
.vga_horiz_sync (vga_horiz_sync),
.vga_vert_sync (vga_vert_sync),
.vga_r (vga_r),
.vga_g (vga_g),
.vga_b (vga_b)
);
cache #(.cache_entry(10))
cache(
.clk (clk_sys),
.rst (reset_sys),
.i_p_addr (sdram_address),
.i_p_byte_en (sdram_byteenable),
.i_p_writedata (sdram_writedata),
.i_p_write (sdram_write),
.i_p_read (sdram_read),
.o_p_readdata (sdram_readdata),
.o_p_readdata_valid (sdram_readdatavalid),
.o_p_waitrequest (sdram_waitrequest),
.o_m_addr (dram_address),
.o_m_writedata (dram_writedata),
.o_m_write (dram_write),
.o_m_read (dram_read),
.i_m_readdata (dram_readdata),
.i_m_readdata_valid (dram_readdatavalid),
.i_m_waitrequest (dram_waitrequest)
);
DRAMCON sdram (
.CLK200M (clk_200m),
.RST_IN (dram_rst_in),
.CLK_OUT (clk_sys),
.RST_OUT (dram_rst_out),
.D_ADDR (dram_address),
.D_DIN (dram_writedata),
.D_WE (dram_write),
.D_RE (dram_read),
.D_DOUT (dram_readdata),
.D_DOUTEN (dram_readdatavalid),
.D_BUSY (dram_waitrequest),
.DDR2DQ (DDR2DQ),
.DDR2DQS_N (DDR2DQS_N),
.DDR2DQS_P (DDR2DQS_P),
.DDR2ADDR (DDR2ADDR),
.DDR2BA (DDR2BA),
.DDR2RAS_N (DDR2RAS_N),
.DDR2CAS_N (DDR2CAS_N),
.DDR2WE_N (DDR2WE_N),
.DDR2CK_P (DDR2CK_P),
.DDR2CK_N (DDR2CK_N),
.DDR2CKE (DDR2CKE),
.DDR2CS_N (DDR2CS_N),
.DDR2DM (DDR2DM),
.DDR2ODT (DDR2ODT)
);
rtc rtc (
.clk (clk_sys),
.io_address (rtc_io_address),
.io_read (rtc_io_read),
.io_readdata (rtc_io_readdata),
.io_write (rtc_io_write),
.io_writedata (rtc_io_writedata),
.rst (reset_sys),
.irq (rtc_irq)
);
pit pit (
.clk (clk_sys),
.io_address (pit_io_address),
.io_read (pit_io_read),
.io_readdata (pit_io_readdata),
.io_write (pit_io_write),
.io_writedata (pit_io_writedata),
.rst (reset_sys),
.irq (pit_irq)
);
assign pic_interrupt_input = {1'b0, hdd_irq, 1'b0, ps2_irq_mouse, 3'b0, rtc_irq, 6'b0, ps2_irq_keyb, pit_irq};
pic pic (
.clk (clk_sys),
.master_address (pic_master_address),
.master_read (pic_master_read),
.master_readdata (pic_master_readdata),
.master_write (pic_master_write),
.master_writedata (pic_master_writedata),
.slave_address (pic_slave_address),
.slave_read (pic_slave_read),
.slave_readdata (pic_slave_readdata),
.slave_write (pic_slave_write),
.slave_writedata (pic_slave_writedata),
.rst (reset_sys),
.interrupt_vector (pic_interrupt_vector),
.interrupt_done (ao486_interrupt_done),
.interrupt_do (pic_interrupt_do),
.interrupt_input (pic_interrupt_input)
);
hdd hdd (
.clk (clk_sys),
.io_address (hdd_io_address),
.io_byteenable (hdd_io_byteenable),
.io_read (hdd_io_read),
.io_readdata (hdd_io_readdata),
.io_write (hdd_io_write),
.io_writedata (hdd_io_writedata),
.sd_slave_address (hdd_sd_slave_address),
.sd_slave_read (hdd_sd_slave_read),
.sd_slave_readdata (hdd_sd_slave_readdata),
.sd_slave_write (hdd_sd_slave_write),
.sd_slave_writedata (hdd_sd_slave_writedata),
.rst (reset_sys),
.irq (hdd_irq),
.sd_master_address (hdd_avalon_master_address),
.sd_master_waitrequest (hdd_avalon_master_waitrequest),
.sd_master_read (hdd_avalon_master_read),
.sd_master_readdatavalid (hdd_avalon_master_readdatavalid),
.sd_master_readdata (hdd_avalon_master_readdata),
.sd_master_write (hdd_avalon_master_write),
.sd_master_writedata (hdd_avalon_master_writedata),
.ide_3f6_read (ide_3f6_read),
.ide_3f6_readdata (ide_3f6_readdata),
.ide_3f6_write (ide_3f6_write),
.ide_3f6_writedata (ide_3f6_writedata)
);
ao486_rst_controller ao486_rst_controller(
.clk_sys (clk_sys),
.rst (reset_sys),
.ao486_rst (ao486_rst),
.address (bios_loader_address[4:3]),
.write (bios_loader_write && bios_loader_address[15:4] == 12'h886),
.writedata (bios_loader_writedata)
);
ps2 ps2 (
.clk (clk_sys),
.io_address (ps2_io_address),
.io_read (ps2_io_read),
.io_readdata (ps2_io_readdata),
.io_write (ps2_io_write),
.io_writedata (ps2_io_writedata),
.sysctl_address (ps2_sysctl_address),
.sysctl_read (ps2_sysctl_read),
.sysctl_readdata (ps2_sysctl_readdata),
.sysctl_write (ps2_sysctl_write),
.sysctl_writedata (ps2_sysctl_writedata),
.rst (reset_sys),
.irq_mouse (ps2_irq_mouse),
.ps2_kbclk (ps2_kbclk),
.ps2_kbdat (ps2_kbdat),
.irq_keyb (ps2_irq_keyb)
);
driver_sd driver_sd (
.clk (clk_sys),
.avs_address (driver_sd_avs_address),
.avs_read (driver_sd_avs_read),
.avs_readdata (driver_sd_avs_readdata),
.avs_write (driver_sd_avs_write),
.avs_writedata (driver_sd_avs_writedata),
.avm_waitrequest (driver_sd_avm_waitrequest),
.avm_read (driver_sd_avm_read),
.avm_readdata (driver_sd_avm_readdata),
.avm_readdatavalid (driver_sd_avm_readdatavalid),
.avm_write (driver_sd_avm_write),
.avm_writedata (driver_sd_avm_writedata),
.avm_address (driver_sd_avm_address),
.rst (reset_sys),
.sd_cmd (sd_cmd),
.sd_dat (sd_dat),
.sd_clk (sd_clk)
);
assign hdd_sd_slave_address = driver_sd_avm_address[10:2];
assign hdd_sd_slave_read = driver_sd_avm_read && (driver_sd_avm_address[31:11] == 21'h000000);
assign hdd_sd_slave_write = driver_sd_avm_write && (driver_sd_avm_address[31:11] == 21'h000000);
assign hdd_sd_slave_writedata = driver_sd_avm_writedata;
reg hdd_sd_slave_readdatavalid;
always @(posedge clk_sys) hdd_sd_slave_readdatavalid <= hdd_sd_slave_read;
assign driver_sd_avm_readdata = (hdd_sd_slave_readdatavalid) ? hdd_sd_slave_readdata :
driver_sd_avm_readdata_from_sdram;
assign driver_sd_avm_readdatavalid = hdd_sd_slave_readdatavalid || driver_sd_avm_readdatavalid_from_sdram;
assign driver_sd_avm_waitrequest = driver_sd_avm_waitrequest_from_sdram;
to_sdram bus_to_sdram (
.clk_sys (clk_sys),
.rst (reset_sys),
.ao486_rst (ao486_rst),
.pc_bus_sdram_address (pc_bus_sdram_address),
.pc_bus_sdram_write (pc_bus_sdram_write),
.pc_bus_sdram_writedata (pc_bus_sdram_writedata),
.pc_bus_sdram_read (pc_bus_sdram_read),
.pc_bus_sdram_readdata (pc_bus_sdram_readdata),
.pc_bus_sdram_readdatavalid (pc_bus_sdram_readdatavalid),
.pc_bus_sdram_byteenable (pc_bus_sdram_byteenable),
.pc_bus_sdram_burstcount (pc_bus_sdram_burstcount),
.pc_bus_sdram_waitrequest (pc_bus_sdram_waitrequest),
.driver_sd_avm_address (driver_sd_avm_address),
.driver_sd_avm_write (driver_sd_avm_write),
.driver_sd_avm_writedata (driver_sd_avm_writedata),
.driver_sd_avm_read (driver_sd_avm_read),
.driver_sd_avm_readdata (driver_sd_avm_readdata_from_sdram),
.driver_sd_avm_readdatavalid (driver_sd_avm_readdatavalid_from_sdram),
.driver_sd_avm_waitrequest (driver_sd_avm_waitrequest_from_sdram),
.sdram_address (sdram_address),
.sdram_write (sdram_write),
.sdram_writedata (sdram_writedata),
.sdram_read (sdram_read),
.sdram_readdata (sdram_readdata),
.sdram_readdatavalid (sdram_readdatavalid),
.sdram_byteenable (sdram_byteenable),
.sdram_waitrequest (sdram_waitrequest),
.sdram_chipselect (sdram_chipselect)
);
to_driver_sd_avs bus_to_driver_sd_avs (
.clk_sys (clk_sys),
.rst (reset_sys),
.ao486_rst (ao486_rst),
.hdd_avalon_master_address (hdd_avalon_master_address),
.hdd_avalon_master_write (hdd_avalon_master_write),
.hdd_avalon_master_writedata (hdd_avalon_master_writedata),
.hdd_avalon_master_read (hdd_avalon_master_read),
.hdd_avalon_master_readdata (hdd_avalon_master_readdata),
.hdd_avalon_master_readdatavalid (hdd_avalon_master_readdatavalid),
.hdd_avalon_master_waitrequest (hdd_avalon_master_waitrequest),
.bios_loader_address (bios_loader_address),
.bios_loader_write (bios_loader_write),
.bios_loader_writedata (bios_loader_writedata),
.bios_loader_read (bios_loader_read),
.bios_loader_readdata (bios_loader_readdata),
.bios_loader_waitrequest (bios_loader_waitrequest),
.bios_loader_byteenable (bios_loader_byteenable),
.driver_sd_avs_address (driver_sd_avs_address),
.driver_sd_avs_write (driver_sd_avs_write),
.driver_sd_avs_writedata (driver_sd_avs_writedata),
.driver_sd_avs_read (driver_sd_avs_read),
.driver_sd_avs_readdata (driver_sd_avs_readdata)
);
pc_bus_to_vga pc_bus_to_vga (
.clk_sys (clk_sys),
.rst (reset_sys),
.pc_bus_vga_address (pc_bus_vga_address),
.pc_bus_vga_write (pc_bus_vga_write),
.pc_bus_vga_writedata (pc_bus_vga_writedata),
.pc_bus_vga_read (pc_bus_vga_read),
.pc_bus_vga_readdata (pc_bus_vga_readdata),
.pc_bus_vga_readdatavalid (pc_bus_vga_readdatavalid),
.pc_bus_vga_byteenable (pc_bus_vga_byteenable),
.pc_bus_vga_burstcount (pc_bus_vga_burstcount),
.pc_bus_vga_waitrequest (pc_bus_vga_waitrequest),
.vga_mem_address (vga_mem_address),
.vga_mem_write (vga_mem_write),
.vga_mem_writedata (vga_mem_writedata),
.vga_mem_read (vga_mem_read),
.vga_mem_readdata (vga_mem_readdata)
);
assign pc_bus_mem_address = ao486_avalon_memory_address[31:2];
assign pc_bus_mem_write = ao486_avalon_memory_write;
assign pc_bus_mem_read = ao486_avalon_memory_read;
assign pc_bus_mem_writedata = ao486_avalon_memory_writedata;
assign pc_bus_mem_byteenable = ao486_avalon_memory_byteenable;
assign pc_bus_mem_burstcount = ao486_avalon_memory_burstcount;
assign ao486_avalon_memory_readdata = pc_bus_mem_readdata;
assign ao486_avalon_memory_readdatavalid = pc_bus_mem_readdatavalid;
assign ao486_avalon_memory_waitrequest = pc_bus_mem_waitrequest;
io_bus io_bus(
.clk_sys (clk_sys),
.rst (reset_sys),
.ao486_avalon_io_address (ao486_avalon_io_address),
.ao486_avalon_io_waitrequest (ao486_avalon_io_waitrequest),
.ao486_avalon_io_byteenable (ao486_avalon_io_byteenable),
.ao486_avalon_io_read (ao486_avalon_io_read),
.ao486_avalon_io_readdata (ao486_avalon_io_readdata),
.ao486_avalon_io_readdatavalid (ao486_avalon_io_readdatavalid),
.ao486_avalon_io_write (ao486_avalon_io_write),
.ao486_avalon_io_writedata (ao486_avalon_io_writedata),
.vga_io_b_address (vga_io_b_address),
.vga_io_b_write (vga_io_b_write),
.vga_io_b_writedata (vga_io_b_writedata),
.vga_io_b_read (vga_io_b_read),
.vga_io_b_readdata (vga_io_b_readdata),
.vga_io_c_address (vga_io_c_address),
.vga_io_c_write (vga_io_c_write),
.vga_io_c_writedata (vga_io_c_writedata),
.vga_io_c_read (vga_io_c_read),
.vga_io_c_readdata (vga_io_c_readdata),
.vga_io_d_address (vga_io_d_address),
.vga_io_d_write (vga_io_d_write),
.vga_io_d_writedata (vga_io_d_writedata),
.vga_io_d_read (vga_io_d_read),
.vga_io_d_readdata (vga_io_d_readdata),
.ps2_io_address (ps2_io_address),
.ps2_io_write (ps2_io_write),
.ps2_io_writedata (ps2_io_writedata),
.ps2_io_read (ps2_io_read),
.ps2_io_readdata (ps2_io_readdata),
.ps2_sysctl_address (ps2_sysctl_address),
.ps2_sysctl_write (ps2_sysctl_write),
.ps2_sysctl_writedata (ps2_sysctl_writedata),
.ps2_sysctl_read (ps2_sysctl_read),
.ps2_sysctl_readdata (ps2_sysctl_readdata),
.pit_io_address (pit_io_address),
.pit_io_write (pit_io_write),
.pit_io_writedata (pit_io_writedata),
.pit_io_read (pit_io_read),
.pit_io_readdata (pit_io_readdata),
.rtc_io_address (rtc_io_address),
.rtc_io_write (rtc_io_write),
.rtc_io_writedata (rtc_io_writedata),
.rtc_io_read (rtc_io_read),
.rtc_io_readdata (rtc_io_readdata),
.pic_master_address (pic_master_address),
.pic_master_write (pic_master_write),
.pic_master_writedata (pic_master_writedata),
.pic_master_read (pic_master_read),
.pic_master_readdata (pic_master_readdata),
.pic_slave_address (pic_slave_address),
.pic_slave_write (pic_slave_write),
.pic_slave_writedata (pic_slave_writedata),
.pic_slave_read (pic_slave_read),
.pic_slave_readdata (pic_slave_readdata),
.hdd_io_address (hdd_io_address),
.hdd_io_write (hdd_io_write),
.hdd_io_writedata (hdd_io_writedata),
.hdd_io_read (hdd_io_read),
.hdd_io_readdata (hdd_io_readdata),
.hdd_io_byteenable (hdd_io_byteenable),
.ide_3f6_write (ide_3f6_write),
.ide_3f6_writedata (ide_3f6_writedata),
.ide_3f6_read (ide_3f6_read),
.ide_3f6_readdata (ide_3f6_readdata)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A32O_TB_V
`define SKY130_FD_SC_HD__A32O_TB_V
/**
* a32o: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input OR.
*
* X = ((A1 & A2 & A3) | (B1 & B2))
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__a32o.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg A3;
reg B1;
reg B2;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
A3 = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 A3 = 1'b0;
#80 B1 = 1'b0;
#100 B2 = 1'b0;
#120 VGND = 1'b0;
#140 VNB = 1'b0;
#160 VPB = 1'b0;
#180 VPWR = 1'b0;
#200 A1 = 1'b1;
#220 A2 = 1'b1;
#240 A3 = 1'b1;
#260 B1 = 1'b1;
#280 B2 = 1'b1;
#300 VGND = 1'b1;
#320 VNB = 1'b1;
#340 VPB = 1'b1;
#360 VPWR = 1'b1;
#380 A1 = 1'b0;
#400 A2 = 1'b0;
#420 A3 = 1'b0;
#440 B1 = 1'b0;
#460 B2 = 1'b0;
#480 VGND = 1'b0;
#500 VNB = 1'b0;
#520 VPB = 1'b0;
#540 VPWR = 1'b0;
#560 VPWR = 1'b1;
#580 VPB = 1'b1;
#600 VNB = 1'b1;
#620 VGND = 1'b1;
#640 B2 = 1'b1;
#660 B1 = 1'b1;
#680 A3 = 1'b1;
#700 A2 = 1'b1;
#720 A1 = 1'b1;
#740 VPWR = 1'bx;
#760 VPB = 1'bx;
#780 VNB = 1'bx;
#800 VGND = 1'bx;
#820 B2 = 1'bx;
#840 B1 = 1'bx;
#860 A3 = 1'bx;
#880 A2 = 1'bx;
#900 A1 = 1'bx;
end
sky130_fd_sc_hd__a32o dut (.A1(A1), .A2(A2), .A3(A3), .B1(B1), .B2(B2), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__A32O_TB_V
|
//-----------------------------------------------------------------
// RISC-V Core
// V1.0.1
// Ultra-Embedded.com
// Copyright 2014-2019
//
// [email protected]
//
// License: BSD
//-----------------------------------------------------------------
//
// Copyright (c) 2014-2019, Ultra-Embedded.com
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer
// in the documentation and/or other materials provided with the
// distribution.
// - Neither the name of the author nor the names of its contributors
// may be used to endorse or promote products derived from this
// software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
// SUCH DAMAGE.
//-----------------------------------------------------------------
module riscv_csr_regfile
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
#(
parameter SUPPORT_MTIMECMP = 1,
parameter SUPPORT_SUPER = 0
)
//-----------------------------------------------------------------
// Ports
//-----------------------------------------------------------------
(
input clk_i
,input rst_i
,input ext_intr_i
,input timer_intr_i
,input [31:0] cpu_id_i
,input [31:0] misa_i
,input [5:0] exception_i
,input [31:0] exception_pc_i
,input [31:0] exception_addr_i
// CSR read port
,input csr_ren_i
,input [11:0] csr_raddr_i
,output [31:0] csr_rdata_o
// CSR write port
,input [11:0] csr_waddr_i
,input [31:0] csr_wdata_i
,output csr_branch_o
,output [31:0] csr_target_o
// CSR registers
,output [1:0] priv_o
,output [31:0] status_o
,output [31:0] satp_o
// Masked interrupt output
,output [31:0] interrupt_o
);
//-----------------------------------------------------------------
// Includes
//-----------------------------------------------------------------
`include "riscv_defs.v"
//-----------------------------------------------------------------
// Registers / Wires
//-----------------------------------------------------------------
// CSR - Machine
reg [31:0] csr_mepc_q;
reg [31:0] csr_mcause_q;
reg [31:0] csr_sr_q;
reg [31:0] csr_mtvec_q;
reg [31:0] csr_mip_q;
reg [31:0] csr_mie_q;
reg [1:0] csr_mpriv_q;
reg [31:0] csr_mcycle_q;
reg [31:0] csr_mcycle_h_q;
reg [31:0] csr_mscratch_q;
reg [31:0] csr_mtval_q;
reg [31:0] csr_mtimecmp_q;
reg csr_mtime_ie_q;
reg [31:0] csr_medeleg_q;
reg [31:0] csr_mideleg_q;
// CSR - Supervisor
reg [31:0] csr_sepc_q;
reg [31:0] csr_stvec_q;
reg [31:0] csr_scause_q;
reg [31:0] csr_stval_q;
reg [31:0] csr_satp_q;
reg [31:0] csr_sscratch_q;
//-----------------------------------------------------------------
// Masked Interrupts
//-----------------------------------------------------------------
reg [31:0] irq_pending_r;
reg [31:0] irq_masked_r;
reg [1:0] irq_priv_r;
reg m_enabled_r;
reg [31:0] m_interrupts_r;
reg s_enabled_r;
reg [31:0] s_interrupts_r;
always @ *
begin
if (SUPPORT_SUPER)
begin
irq_pending_r = (csr_mip_q & csr_mie_q);
m_enabled_r = (csr_mpriv_q < `PRIV_MACHINE) || (csr_mpriv_q == `PRIV_MACHINE && csr_sr_q[`SR_MIE_R]);
s_enabled_r = (csr_mpriv_q < `PRIV_SUPER) || (csr_mpriv_q == `PRIV_SUPER && csr_sr_q[`SR_SIE_R]);
m_interrupts_r = m_enabled_r ? (irq_pending_r & ~csr_mideleg_q) : 32'b0;
s_interrupts_r = s_enabled_r ? (irq_pending_r & csr_mideleg_q) : 32'b0;
irq_masked_r = (|m_interrupts_r) ? m_interrupts_r : s_interrupts_r;
irq_priv_r = (|m_interrupts_r) ? `PRIV_MACHINE : `PRIV_SUPER;
end
else
begin
irq_pending_r = (csr_mip_q & csr_mie_q);
irq_masked_r = csr_sr_q[`SR_MIE_R] ? irq_pending_r : 32'b0;
irq_priv_r = `PRIV_MACHINE;
end
end
reg [1:0] irq_priv_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
irq_priv_q <= `PRIV_MACHINE;
else if (|irq_masked_r)
irq_priv_q <= irq_priv_r;
assign interrupt_o = irq_masked_r;
reg csr_mip_upd_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
csr_mip_upd_q <= 1'b0;
else if ((csr_ren_i && csr_raddr_i == `CSR_MIP) || (csr_ren_i && csr_raddr_i == `CSR_SIP))
csr_mip_upd_q <= 1'b1;
else if (csr_waddr_i == `CSR_MIP || csr_waddr_i == `CSR_SIP || (|exception_i))
csr_mip_upd_q <= 1'b0;
wire buffer_mip_w = (csr_ren_i && csr_raddr_i == `CSR_MIP) | (csr_ren_i && csr_raddr_i == `CSR_SIP) | csr_mip_upd_q;
//-----------------------------------------------------------------
// CSR Read Port
//-----------------------------------------------------------------
reg [31:0] rdata_r;
always @ *
begin
rdata_r = 32'b0;
case (csr_raddr_i)
// CSR - Machine
`CSR_MSCRATCH: rdata_r = csr_mscratch_q & `CSR_MSCRATCH_MASK;
`CSR_MEPC: rdata_r = csr_mepc_q & `CSR_MEPC_MASK;
`CSR_MTVEC: rdata_r = csr_mtvec_q & `CSR_MTVEC_MASK;
`CSR_MCAUSE: rdata_r = csr_mcause_q & `CSR_MCAUSE_MASK;
`CSR_MTVAL: rdata_r = csr_mtval_q & `CSR_MTVAL_MASK;
`CSR_MSTATUS: rdata_r = csr_sr_q & `CSR_MSTATUS_MASK;
`CSR_MIP: rdata_r = csr_mip_q & `CSR_MIP_MASK;
`CSR_MIE: rdata_r = csr_mie_q & `CSR_MIE_MASK;
`CSR_MCYCLE,
`CSR_MTIME: rdata_r = csr_mcycle_q;
`CSR_MTIMEH: rdata_r = csr_mcycle_h_q;
`CSR_MHARTID: rdata_r = cpu_id_i;
`CSR_MISA: rdata_r = misa_i;
`CSR_MEDELEG: rdata_r = SUPPORT_SUPER ? (csr_medeleg_q & `CSR_MEDELEG_MASK) : 32'b0;
`CSR_MIDELEG: rdata_r = SUPPORT_SUPER ? (csr_mideleg_q & `CSR_MIDELEG_MASK) : 32'b0;
// Non-std behaviour
`CSR_MTIMECMP: rdata_r = SUPPORT_MTIMECMP ? csr_mtimecmp_q : 32'b0;
// CSR - Super
`CSR_SSTATUS: rdata_r = SUPPORT_SUPER ? (csr_sr_q & `CSR_SSTATUS_MASK) : 32'b0;
`CSR_SIP: rdata_r = SUPPORT_SUPER ? (csr_mip_q & `CSR_SIP_MASK) : 32'b0;
`CSR_SIE: rdata_r = SUPPORT_SUPER ? (csr_mie_q & `CSR_SIE_MASK) : 32'b0;
`CSR_SEPC: rdata_r = SUPPORT_SUPER ? (csr_sepc_q & `CSR_SEPC_MASK) : 32'b0;
`CSR_STVEC: rdata_r = SUPPORT_SUPER ? (csr_stvec_q & `CSR_STVEC_MASK) : 32'b0;
`CSR_SCAUSE: rdata_r = SUPPORT_SUPER ? (csr_scause_q & `CSR_SCAUSE_MASK) : 32'b0;
`CSR_STVAL: rdata_r = SUPPORT_SUPER ? (csr_stval_q & `CSR_STVAL_MASK) : 32'b0;
`CSR_SATP: rdata_r = SUPPORT_SUPER ? (csr_satp_q & `CSR_SATP_MASK) : 32'b0;
`CSR_SSCRATCH: rdata_r = SUPPORT_SUPER ? (csr_sscratch_q & `CSR_SSCRATCH_MASK) : 32'b0;
default: rdata_r = 32'b0;
endcase
end
assign csr_rdata_o = rdata_r;
assign priv_o = csr_mpriv_q;
assign status_o = csr_sr_q;
assign satp_o = csr_satp_q;
//-----------------------------------------------------------------
// CSR register next state
//-----------------------------------------------------------------
// CSR - Machine
reg [31:0] csr_mepc_r;
reg [31:0] csr_mcause_r;
reg [31:0] csr_mtval_r;
reg [31:0] csr_sr_r;
reg [31:0] csr_mtvec_r;
reg [31:0] csr_mip_r;
reg [31:0] csr_mie_r;
reg [1:0] csr_mpriv_r;
reg [31:0] csr_mcycle_r;
reg [31:0] csr_mscratch_r;
reg [31:0] csr_mtimecmp_r;
reg csr_mtime_ie_r;
reg [31:0] csr_medeleg_r;
reg [31:0] csr_mideleg_r;
reg [31:0] csr_mip_next_q;
reg [31:0] csr_mip_next_r;
// CSR - Supervisor
reg [31:0] csr_sepc_r;
reg [31:0] csr_stvec_r;
reg [31:0] csr_scause_r;
reg [31:0] csr_stval_r;
reg [31:0] csr_satp_r;
reg [31:0] csr_sscratch_r;
wire is_exception_w = ((exception_i & `EXCEPTION_TYPE_MASK) == `EXCEPTION_EXCEPTION);
wire exception_s_w = SUPPORT_SUPER ? ((csr_mpriv_q <= `PRIV_SUPER) & is_exception_w & csr_medeleg_q[{1'b0, exception_i[`EXCEPTION_SUBTYPE_R]}]) : 1'b0;
always @ *
begin
// CSR - Machine
csr_mip_next_r = csr_mip_next_q;
csr_mepc_r = csr_mepc_q;
csr_sr_r = csr_sr_q;
csr_mcause_r = csr_mcause_q;
csr_mtval_r = csr_mtval_q;
csr_mtvec_r = csr_mtvec_q;
csr_mip_r = csr_mip_q;
csr_mie_r = csr_mie_q;
csr_mpriv_r = csr_mpriv_q;
csr_mscratch_r = csr_mscratch_q;
csr_mcycle_r = csr_mcycle_q + 32'd1;
csr_mtimecmp_r = csr_mtimecmp_q;
csr_mtime_ie_r = csr_mtime_ie_q;
csr_medeleg_r = csr_medeleg_q;
csr_mideleg_r = csr_mideleg_q;
// CSR - Super
csr_sepc_r = csr_sepc_q;
csr_stvec_r = csr_stvec_q;
csr_scause_r = csr_scause_q;
csr_stval_r = csr_stval_q;
csr_satp_r = csr_satp_q;
csr_sscratch_r = csr_sscratch_q;
// Interrupts
if ((exception_i & `EXCEPTION_TYPE_MASK) == `EXCEPTION_INTERRUPT)
begin
// Machine mode interrupts
if (irq_priv_q == `PRIV_MACHINE)
begin
// Save interrupt / supervisor state
csr_sr_r[`SR_MPIE_R] = csr_sr_r[`SR_MIE_R];
csr_sr_r[`SR_MPP_R] = csr_mpriv_q;
// Disable interrupts and enter supervisor mode
csr_sr_r[`SR_MIE_R] = 1'b0;
// Raise priviledge to machine level
csr_mpriv_r = `PRIV_MACHINE;
// Record interrupt source PC
csr_mepc_r = exception_pc_i;
csr_mtval_r = 32'b0;
// Piority encoded interrupt cause
if (interrupt_o[`IRQ_M_SOFT])
csr_mcause_r = `MCAUSE_INTERRUPT + 32'd`IRQ_M_SOFT;
else if (interrupt_o[`IRQ_M_TIMER])
csr_mcause_r = `MCAUSE_INTERRUPT + 32'd`IRQ_M_TIMER;
else if (interrupt_o[`IRQ_M_EXT])
csr_mcause_r = `MCAUSE_INTERRUPT + 32'd`IRQ_M_EXT;
end
// Supervisor mode interrupts
else
begin
// Save interrupt / supervisor state
csr_sr_r[`SR_SPIE_R] = csr_sr_r[`SR_SIE_R];
csr_sr_r[`SR_SPP_R] = (csr_mpriv_q == `PRIV_SUPER);
// Disable interrupts and enter supervisor mode
csr_sr_r[`SR_SIE_R] = 1'b0;
// Raise priviledge to machine level
csr_mpriv_r = `PRIV_SUPER;
// Record fault source PC
csr_sepc_r = exception_pc_i;
csr_stval_r = 32'b0;
// Piority encoded interrupt cause
if (interrupt_o[`IRQ_S_SOFT])
csr_scause_r = `MCAUSE_INTERRUPT + 32'd`IRQ_S_SOFT;
else if (interrupt_o[`IRQ_S_TIMER])
csr_scause_r = `MCAUSE_INTERRUPT + 32'd`IRQ_S_TIMER;
else if (interrupt_o[`IRQ_S_EXT])
csr_scause_r = `MCAUSE_INTERRUPT + 32'd`IRQ_S_EXT;
end
end
// Exception return
else if (exception_i >= `EXCEPTION_ERET_U && exception_i <= `EXCEPTION_ERET_M)
begin
// MRET (return from machine)
if (exception_i[1:0] == `PRIV_MACHINE)
begin
// Set privilege level to previous MPP
csr_mpriv_r = csr_sr_r[`SR_MPP_R];
// Interrupt enable pop
csr_sr_r[`SR_MIE_R] = csr_sr_r[`SR_MPIE_R];
csr_sr_r[`SR_MPIE_R] = 1'b1;
// TODO: Set next MPP to user mode??
csr_sr_r[`SR_MPP_R] = `SR_MPP_U;
end
// SRET (return from supervisor)
else
begin
// Set privilege level to previous privilege level
csr_mpriv_r = csr_sr_r[`SR_SPP_R] ? `PRIV_SUPER : `PRIV_USER;
// Interrupt enable pop
csr_sr_r[`SR_SIE_R] = csr_sr_r[`SR_SPIE_R];
csr_sr_r[`SR_SPIE_R] = 1'b1;
// Set next SPP to user mode
csr_sr_r[`SR_SPP_R] = 1'b0;
end
end
// Exception - handled in super mode
else if (is_exception_w && exception_s_w)
begin
// Save interrupt / supervisor state
csr_sr_r[`SR_SPIE_R] = csr_sr_r[`SR_SIE_R];
csr_sr_r[`SR_SPP_R] = (csr_mpriv_q == `PRIV_SUPER);
// Disable interrupts and enter supervisor mode
csr_sr_r[`SR_SIE_R] = 1'b0;
// Raise priviledge to machine level
csr_mpriv_r = `PRIV_SUPER;
// Record fault source PC
csr_sepc_r = exception_pc_i;
// Bad address / PC
case (exception_i)
`EXCEPTION_MISALIGNED_FETCH,
`EXCEPTION_FAULT_FETCH,
`EXCEPTION_PAGE_FAULT_INST: csr_stval_r = exception_pc_i;
`EXCEPTION_ILLEGAL_INSTRUCTION,
`EXCEPTION_MISALIGNED_LOAD,
`EXCEPTION_FAULT_LOAD,
`EXCEPTION_MISALIGNED_STORE,
`EXCEPTION_FAULT_STORE,
`EXCEPTION_PAGE_FAULT_LOAD,
`EXCEPTION_PAGE_FAULT_STORE: csr_stval_r = exception_addr_i;
default: csr_stval_r = 32'b0;
endcase
// Fault cause
csr_scause_r = {28'b0, exception_i[3:0]};
end
// Exception - handled in machine mode
else if (is_exception_w)
begin
// Save interrupt / supervisor state
csr_sr_r[`SR_MPIE_R] = csr_sr_r[`SR_MIE_R];
csr_sr_r[`SR_MPP_R] = csr_mpriv_q;
// Disable interrupts and enter supervisor mode
csr_sr_r[`SR_MIE_R] = 1'b0;
// Raise priviledge to machine level
csr_mpriv_r = `PRIV_MACHINE;
// Record fault source PC
csr_mepc_r = exception_pc_i;
// Bad address / PC
case (exception_i)
`EXCEPTION_MISALIGNED_FETCH,
`EXCEPTION_FAULT_FETCH,
`EXCEPTION_PAGE_FAULT_INST: csr_mtval_r = exception_pc_i;
`EXCEPTION_ILLEGAL_INSTRUCTION,
`EXCEPTION_MISALIGNED_LOAD,
`EXCEPTION_FAULT_LOAD,
`EXCEPTION_MISALIGNED_STORE,
`EXCEPTION_FAULT_STORE,
`EXCEPTION_PAGE_FAULT_LOAD,
`EXCEPTION_PAGE_FAULT_STORE: csr_mtval_r = exception_addr_i;
default: csr_mtval_r = 32'b0;
endcase
// Fault cause
csr_mcause_r = {28'b0, exception_i[3:0]};
end
else
begin
case (csr_waddr_i)
// CSR - Machine
`CSR_MSCRATCH: csr_mscratch_r = csr_wdata_i & `CSR_MSCRATCH_MASK;
`CSR_MEPC: csr_mepc_r = csr_wdata_i & `CSR_MEPC_MASK;
`CSR_MTVEC: csr_mtvec_r = csr_wdata_i & `CSR_MTVEC_MASK;
`CSR_MCAUSE: csr_mcause_r = csr_wdata_i & `CSR_MCAUSE_MASK;
`CSR_MTVAL: csr_mtval_r = csr_wdata_i & `CSR_MTVAL_MASK;
`CSR_MSTATUS: csr_sr_r = csr_wdata_i & `CSR_MSTATUS_MASK;
`CSR_MIP: csr_mip_r = csr_wdata_i & `CSR_MIP_MASK;
`CSR_MIE: csr_mie_r = csr_wdata_i & `CSR_MIE_MASK;
`CSR_MEDELEG: csr_medeleg_r = csr_wdata_i & `CSR_MEDELEG_MASK;
`CSR_MIDELEG: csr_mideleg_r = csr_wdata_i & `CSR_MIDELEG_MASK;
// Non-std behaviour
`CSR_MTIMECMP:
begin
csr_mtimecmp_r = csr_wdata_i & `CSR_MTIMECMP_MASK;
csr_mtime_ie_r = 1'b1;
end
// CSR - Super
`CSR_SEPC: csr_sepc_r = csr_wdata_i & `CSR_SEPC_MASK;
`CSR_STVEC: csr_stvec_r = csr_wdata_i & `CSR_STVEC_MASK;
`CSR_SCAUSE: csr_scause_r = csr_wdata_i & `CSR_SCAUSE_MASK;
`CSR_STVAL: csr_stval_r = csr_wdata_i & `CSR_STVAL_MASK;
`CSR_SATP: csr_satp_r = csr_wdata_i & `CSR_SATP_MASK;
`CSR_SSCRATCH: csr_sscratch_r = csr_wdata_i & `CSR_SSCRATCH_MASK;
`CSR_SSTATUS: csr_sr_r = (csr_sr_r & ~`CSR_SSTATUS_MASK) | (csr_wdata_i & `CSR_SSTATUS_MASK);
`CSR_SIP: csr_mip_r = (csr_mip_r & ~`CSR_SIP_MASK) | (csr_wdata_i & `CSR_SIP_MASK);
`CSR_SIE: csr_mie_r = (csr_mie_r & ~`CSR_SIE_MASK) | (csr_wdata_i & `CSR_SIE_MASK);
default:
;
endcase
end
// External interrupts
// NOTE: If the machine level interrupts are delegated to supervisor, route the interrupts there instead..
if (ext_intr_i && csr_mideleg_q[`SR_IP_MEIP_R]) csr_mip_next_r[`SR_IP_SEIP_R] = 1'b1;
if (ext_intr_i && ~csr_mideleg_q[`SR_IP_MEIP_R]) csr_mip_next_r[`SR_IP_MEIP_R] = 1'b1;
if (timer_intr_i && csr_mideleg_q[`SR_IP_MTIP_R]) csr_mip_next_r[`SR_IP_STIP_R] = 1'b1;
if (timer_intr_i && ~csr_mideleg_q[`SR_IP_MTIP_R]) csr_mip_next_r[`SR_IP_MTIP_R] = 1'b1;
// Optional: Internal timer compare interrupt
if (SUPPORT_MTIMECMP && csr_mcycle_q == csr_mtimecmp_q)
begin
if (csr_mideleg_q[`SR_IP_MTIP_R])
csr_mip_next_r[`SR_IP_STIP_R] = csr_mtime_ie_q;
else
csr_mip_next_r[`SR_IP_MTIP_R] = csr_mtime_ie_q;
csr_mtime_ie_r = 1'b0;
end
csr_mip_r = csr_mip_r | csr_mip_next_r;
end
//-----------------------------------------------------------------
// Sequential
//-----------------------------------------------------------------
`ifdef verilator
`define HAS_SIM_CTRL
`endif
`ifdef verilog_sim
`define HAS_SIM_CTRL
`endif
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
begin
// CSR - Machine
csr_mepc_q <= 32'b0;
csr_sr_q <= 32'b0;
csr_mcause_q <= 32'b0;
csr_mtval_q <= 32'b0;
csr_mtvec_q <= 32'b0;
csr_mip_q <= 32'b0;
csr_mie_q <= 32'b0;
csr_mpriv_q <= `PRIV_MACHINE;
csr_mcycle_q <= 32'b0;
csr_mcycle_h_q <= 32'b0;
csr_mscratch_q <= 32'b0;
csr_mtimecmp_q <= 32'b0;
csr_mtime_ie_q <= 1'b0;
csr_medeleg_q <= 32'b0;
csr_mideleg_q <= 32'b0;
// CSR - Super
csr_sepc_q <= 32'b0;
csr_stvec_q <= 32'b0;
csr_scause_q <= 32'b0;
csr_stval_q <= 32'b0;
csr_satp_q <= 32'b0;
csr_sscratch_q <= 32'b0;
csr_mip_next_q <= 32'b0;
end
else
begin
// CSR - Machine
csr_mepc_q <= csr_mepc_r;
csr_sr_q <= csr_sr_r;
csr_mcause_q <= csr_mcause_r;
csr_mtval_q <= csr_mtval_r;
csr_mtvec_q <= csr_mtvec_r;
csr_mip_q <= csr_mip_r;
csr_mie_q <= csr_mie_r;
csr_mpriv_q <= SUPPORT_SUPER ? csr_mpriv_r : `PRIV_MACHINE;
csr_mcycle_q <= csr_mcycle_r;
csr_mscratch_q <= csr_mscratch_r;
csr_mtimecmp_q <= SUPPORT_MTIMECMP ? csr_mtimecmp_r : 32'b0;
csr_mtime_ie_q <= SUPPORT_MTIMECMP ? csr_mtime_ie_r : 1'b0;
csr_medeleg_q <= SUPPORT_SUPER ? (csr_medeleg_r & `CSR_MEDELEG_MASK) : 32'b0;
csr_mideleg_q <= SUPPORT_SUPER ? (csr_mideleg_r & `CSR_MIDELEG_MASK) : 32'b0;
// CSR - Super
csr_sepc_q <= SUPPORT_SUPER ? (csr_sepc_r & `CSR_SEPC_MASK) : 32'b0;
csr_stvec_q <= SUPPORT_SUPER ? (csr_stvec_r & `CSR_STVEC_MASK) : 32'b0;
csr_scause_q <= SUPPORT_SUPER ? (csr_scause_r & `CSR_SCAUSE_MASK) : 32'b0;
csr_stval_q <= SUPPORT_SUPER ? (csr_stval_r & `CSR_STVAL_MASK) : 32'b0;
csr_satp_q <= SUPPORT_SUPER ? (csr_satp_r & `CSR_SATP_MASK) : 32'b0;
csr_sscratch_q <= SUPPORT_SUPER ? (csr_sscratch_r & `CSR_SSCRATCH_MASK) : 32'b0;
csr_mip_next_q <= buffer_mip_w ? csr_mip_next_r : 32'b0;
// Increment upper cycle counter on lower 32-bit overflow
if (csr_mcycle_q == 32'hFFFFFFFF)
csr_mcycle_h_q <= csr_mcycle_h_q + 32'd1;
`ifdef HAS_SIM_CTRL
// CSR SIM_CTRL (or DSCRATCH)
if ((csr_waddr_i == `CSR_DSCRATCH || csr_waddr_i == `CSR_SIM_CTRL) && ~(|exception_i))
begin
case (csr_wdata_i & 32'hFF000000)
`CSR_SIM_CTRL_EXIT:
begin
//exit(csr_wdata_i[7:0]);
$finish;
$finish;
end
`CSR_SIM_CTRL_PUTC:
begin
$write("%c", csr_wdata_i[7:0]);
end
endcase
end
`endif
end
//-----------------------------------------------------------------
// CSR branch
//-----------------------------------------------------------------
reg branch_r;
reg [31:0] branch_target_r;
always @ *
begin
branch_r = 1'b0;
branch_target_r = 32'b0;
// Interrupts
if (exception_i == `EXCEPTION_INTERRUPT)
begin
branch_r = 1'b1;
branch_target_r = (irq_priv_q == `PRIV_MACHINE) ? csr_mtvec_q : csr_stvec_q;
end
// Exception return
else if (exception_i >= `EXCEPTION_ERET_U && exception_i <= `EXCEPTION_ERET_M)
begin
// MRET (return from machine)
if (exception_i[1:0] == `PRIV_MACHINE)
begin
branch_r = 1'b1;
branch_target_r = csr_mepc_q;
end
// SRET (return from supervisor)
else
begin
branch_r = 1'b1;
branch_target_r = csr_sepc_q;
end
end
// Exception - handled in super mode
else if (is_exception_w && exception_s_w)
begin
branch_r = 1'b1;
branch_target_r = csr_stvec_q;
end
// Exception - handled in machine mode
else if (is_exception_w)
begin
branch_r = 1'b1;
branch_target_r = csr_mtvec_q;
end
// Fence / SATP register writes cause pipeline flushes
else if (exception_i == `EXCEPTION_FENCE)
begin
branch_r = 1'b1;
branch_target_r = exception_pc_i + 32'd4;
end
end
assign csr_branch_o = branch_r;
assign csr_target_o = branch_target_r;
`ifdef verilator
function [31:0] get_mcycle; /*verilator public*/
begin
get_mcycle = csr_mcycle_q;
end
endfunction
`endif
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O22A_PP_SYMBOL_V
`define SKY130_FD_SC_LP__O22A_PP_SYMBOL_V
/**
* o22a: 2-input OR into both inputs of 2-input AND.
*
* X = ((A1 | A2) & (B1 | B2))
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__o22a (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
input B2 ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__O22A_PP_SYMBOL_V
|
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