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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NAND3B_TB_V
`define SKY130_FD_SC_LP__NAND3B_TB_V
/**
* nand3b: 3-input NAND, first input inverted.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__nand3b.v"
module top();
// Inputs are registered
reg A_N;
reg B;
reg C;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A_N = 1'bX;
B = 1'bX;
C = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A_N = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A_N = 1'b1;
#180 B = 1'b1;
#200 C = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A_N = 1'b0;
#320 B = 1'b0;
#340 C = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 C = 1'b1;
#540 B = 1'b1;
#560 A_N = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 C = 1'bx;
#680 B = 1'bx;
#700 A_N = 1'bx;
end
sky130_fd_sc_lp__nand3b dut (.A_N(A_N), .B(B), .C(C), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__NAND3B_TB_V
|
/*******************************************************
* File Name : hdl/ks7.v
* Module Name : Karatsuba Multiplier
* Author : Chester Rebeiro
* Institute : Indian Institute of Technology, Madras
* Creation Time :
* Comment : Automatically generated from ks.c
********************************************************/
module Sks7(a, b, d);
input wire [6:0] a;
input wire [6:0] b;
output wire [12:0] d;
wire [4:0] m1;
wire [6:0] m2;
wire [6:0] m3;
wire [3:0] ahl;
wire [3:0] bhl;
Sks4 ksm1(a[3:0], b[3:0], m2);
//Sks3 ksm2(a[6:4], b[6:4], m1);
assign m1 = a[6:4] * b[6:4];
assign ahl[2:0] = a[6:4] ^ a[2:0];
assign ahl[3] = a[3];
assign bhl[2:0] = b[6:4] ^ b[2:0];
assign bhl[3] = b[3];
Sks4 ksm3(ahl, bhl, m3);
assign d[00] = m2[00];
assign d[01] = m2[01];
assign d[02] = m2[02];
assign d[03] = m2[03];
assign d[04] = m2[04] ^ m1[00] ^ m2[00] ^ m3[00];
assign d[05] = m2[05] ^ m1[01] ^ m2[01] ^ m3[01];
assign d[06] = m2[06] ^ m1[02] ^ m2[02] ^ m3[02];
assign d[07] = m1[03] ^ m2[03] ^ m3[03];
assign d[08] = m1[04] ^ m2[04] ^ m3[04] ^ m1[00];
assign d[09] = m2[05] ^ m3[05] ^ m1[01];
assign d[10] = m2[06] ^ m3[06] ^ m1[02];
assign d[11] = m1[03];
assign d[12] = m1[04];
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: sparc_exu_eclcomp7.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Module Name: sparc_exu_eclcomp7
// Description: This block is a 7 bit comparator. It takes 2 inputs
// and outputs a 1 on out if they are equal.
*/
module sparc_exu_eclcomp7 (/*AUTOARG*/
// Outputs
out,
// Inputs
in1, in2
) ;
input [6:0] in1;
input [6:0] in2;
output out;
wire [6:0] in1xorin2;
wire nor1out;
wire nor2out;
wire nor3out;
wire nandout;
assign in1xorin2 = in1 ^ in2;
assign nor1out = ~(in1xorin2[0] | in1xorin2[1]);
assign nor2out = ~(in1xorin2[2] | in1xorin2[3]);
assign nor3out = ~(in1xorin2[4] | in1xorin2[5]);
assign nandout = ~(nor1out & nor2out & nor3out);
assign out = ~(in1xorin2[6] | nandout);
endmodule // sparc_exu_eclcomp7
|
//////////////////////////////////////////////////////////////////////
/// ////
/// ORPSoC top for ML501 board ////
/// ////
/// Instantiates modules, depending on ORPSoC defines file ////
/// ////
/// Julius Baxter, [email protected] ////
/// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009, 2010 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
`include "orpsoc-defines.v"
`include "synthesis-defines.v"
module orpsoc_top
(
`ifdef JTAG_DEBUG
tdo_pad_o, tms_pad_i, tck_pad_i, tdi_pad_i, jtag_gnd, jtag_vdd,
`elsif ADV_DEBUG
tdo_pad_o, tms_pad_i, tck_pad_i, tdi_pad_i, jtag_gnd, jtag_vdd,
`endif
`ifdef XILINX_DDR2
ddr2_a, ddr2_ba, ddr2_ras_n, ddr2_cas_n, ddr2_we_n,
ddr2_cs_n, ddr2_odt, ddr2_cke, ddr2_dm,
ddr2_dq, ddr2_dqs, ddr2_dqs_n, ddr2_ck, ddr2_ck_n,
`endif
`ifdef XILINX_SSRAM
sram_clk, sram_clk_fb, sram_flash_addr, sram_flash_data,
sram_cen, sram_flash_oe_n, sram_flash_we_n, sram_bw,
sram_adv_ld_n, sram_mode,
`endif
`ifdef UART0
uart0_srx_pad_i, uart0_stx_pad_o,
uart0_srx_expheader_pad_i, uart0_stx_expheader_pad_o,
`endif
`ifdef SPI0
spi0_mosi_o, spi0_ss_o,/* spi0_sck_o, spi0_miso_i,via STARTUP_VIRTEX5*/
`endif
`ifdef I2C0
i2c0_sda_io, i2c0_scl_io,
`endif
`ifdef I2C1
i2c1_sda_io, i2c1_scl_io,
`endif
`ifdef GPIO0
gpio0_io,
`endif
`ifdef ETH0
eth0_tx_clk, eth0_tx_data, eth0_tx_en, eth0_tx_er,
eth0_rx_clk, eth0_rx_data, eth0_dv, eth0_rx_er,
eth0_col, eth0_crs,
eth0_mdc_pad_o, eth0_md_pad_io,
`ifdef ETH0_PHY_RST
eth0_rst_n_o,
`endif
`endif
sys_clk_in_p,sys_clk_in_n,
rst_n_pad_i
);
`include "orpsoc-params.v"
input sys_clk_in_p,sys_clk_in_n;
input rst_n_pad_i;
`ifdef JTAG_DEBUG
output tdo_pad_o;
input tms_pad_i;
input tck_pad_i;
input tdi_pad_i;
output jtag_gnd;
output jtag_vdd;
`elsif ADV_DEBUG
output tdo_pad_o;
input tms_pad_i;
input tck_pad_i;
input tdi_pad_i;
output jtag_gnd;
output jtag_vdd;
`endif
`ifdef XILINX_DDR2
output [12:0] ddr2_a;
output [1:0] ddr2_ba;
output ddr2_ras_n;
output ddr2_cas_n;
output ddr2_we_n;
output [1:0] ddr2_cs_n;
output [1:0] ddr2_odt;
output [1:0] ddr2_cke;
output [7:0] ddr2_dm;
inout [63:0] ddr2_dq;
inout [7:0] ddr2_dqs;
inout [7:0] ddr2_dqs_n;
output [1:0] ddr2_ck;
output [1:0] ddr2_ck_n;
`endif
`ifdef XILINX_SSRAM
// ZBT SSRAM
output sram_clk;
input sram_clk_fb;
output [21:1] sram_flash_addr;
inout [31:0] sram_flash_data;
output sram_cen;
output sram_flash_oe_n;
output sram_flash_we_n;
output [3:0] sram_bw;
output sram_adv_ld_n;
output sram_mode;
`endif
`ifdef UART0
input uart0_srx_pad_i;
output uart0_stx_pad_o;
// Duplicates of the UART signals, this time to the USB debug cable
input uart0_srx_expheader_pad_i;
output uart0_stx_expheader_pad_o;
`endif
`ifdef SPI0
output spi0_mosi_o;
output [spi0_ss_width-1:0] spi0_ss_o;
/* via STARTUP_VIRTEX5
output spi0_sck_o;
input spi0_miso_i;
*/
`endif
`ifdef I2C0
inout i2c0_sda_io, i2c0_scl_io;
`endif
`ifdef I2C1
inout i2c1_sda_io, i2c1_scl_io;
`endif
`ifdef GPIO0
inout [gpio0_io_width-1:0] gpio0_io;
`endif
`ifdef ETH0
input eth0_tx_clk;
output [3:0] eth0_tx_data;
output eth0_tx_en;
output eth0_tx_er;
input eth0_rx_clk;
input [3:0] eth0_rx_data;
input eth0_dv;
input eth0_rx_er;
input eth0_col;
input eth0_crs;
output eth0_mdc_pad_o;
inout eth0_md_pad_io;
`ifdef ETH0_PHY_RST
output eth0_rst_n_o;
`endif
`endif // `ifdef ETH0
////////////////////////////////////////////////////////////////////////
//
// Clock and reset generation module
//
////////////////////////////////////////////////////////////////////////
//
// Wires
//
wire wb_clk, wb_rst;
wire ddr2_if_clk, ddr2_if_rst;
wire clk200;
wire dbg_tck;
clkgen clkgen0
(
.sys_clk_in_p (sys_clk_in_p),
.sys_clk_in_n (sys_clk_in_n),
.wb_clk_o (wb_clk),
.wb_rst_o (wb_rst),
`ifdef JTAG_DEBUG
.tck_pad_i (tck_pad_i),
.dbg_tck_o (dbg_tck),
`endif
`ifdef XILINX_DDR2
.ddr2_if_clk_o (ddr2_if_clk),
.ddr2_if_rst_o (ddr2_if_rst),
.clk200_o (clk200),
`endif
// Asynchronous active low reset
.rst_n_pad_i (rst_n_pad_i)
);
////////////////////////////////////////////////////////////////////////
//
// Arbiter
//
////////////////////////////////////////////////////////////////////////
// Wire naming convention:
// First: wishbone master or slave (wbm/wbs)
// Second: Which bus it's on instruction or data (i/d)
// Third: Between which module and the arbiter the wires are
// Fourth: Signal name
// Fifth: Direction relative to module (not bus/arbiter!)
// ie. wbm_d_or12_adr_o is address OUT from the or1200
// OR1200 instruction bus wires
wire [wb_aw-1:0] wbm_i_or12_adr_o;
wire [wb_dw-1:0] wbm_i_or12_dat_o;
wire [3:0] wbm_i_or12_sel_o;
wire wbm_i_or12_we_o;
wire wbm_i_or12_cyc_o;
wire wbm_i_or12_stb_o;
wire [2:0] wbm_i_or12_cti_o;
wire [1:0] wbm_i_or12_bte_o;
wire [wb_dw-1:0] wbm_i_or12_dat_i;
wire wbm_i_or12_ack_i;
wire wbm_i_or12_err_i;
wire wbm_i_or12_rty_i;
// OR1200 data bus wires
wire [wb_aw-1:0] wbm_d_or12_adr_o;
wire [wb_dw-1:0] wbm_d_or12_dat_o;
wire [3:0] wbm_d_or12_sel_o;
wire wbm_d_or12_we_o;
wire wbm_d_or12_cyc_o;
wire wbm_d_or12_stb_o;
wire [2:0] wbm_d_or12_cti_o;
wire [1:0] wbm_d_or12_bte_o;
wire [wb_dw-1:0] wbm_d_or12_dat_i;
wire wbm_d_or12_ack_i;
wire wbm_d_or12_err_i;
wire wbm_d_or12_rty_i;
// Debug interface bus wires
wire [wb_aw-1:0] wbm_d_dbg_adr_o;
wire [wb_dw-1:0] wbm_d_dbg_dat_o;
wire [3:0] wbm_d_dbg_sel_o;
wire wbm_d_dbg_we_o;
wire wbm_d_dbg_cyc_o;
wire wbm_d_dbg_stb_o;
wire [2:0] wbm_d_dbg_cti_o;
wire [1:0] wbm_d_dbg_bte_o;
wire [wb_dw-1:0] wbm_d_dbg_dat_i;
wire wbm_d_dbg_ack_i;
wire wbm_d_dbg_err_i;
wire wbm_d_dbg_rty_i;
// Byte bus bridge master signals
wire [wb_aw-1:0] wbm_b_d_adr_o;
wire [wb_dw-1:0] wbm_b_d_dat_o;
wire [3:0] wbm_b_d_sel_o;
wire wbm_b_d_we_o;
wire wbm_b_d_cyc_o;
wire wbm_b_d_stb_o;
wire [2:0] wbm_b_d_cti_o;
wire [1:0] wbm_b_d_bte_o;
wire [wb_dw-1:0] wbm_b_d_dat_i;
wire wbm_b_d_ack_i;
wire wbm_b_d_err_i;
wire wbm_b_d_rty_i;
// Instruction bus slave wires //
// rom0 instruction bus wires
wire [31:0] wbs_i_rom0_adr_i;
wire [wbs_i_rom0_data_width-1:0] wbs_i_rom0_dat_i;
wire [3:0] wbs_i_rom0_sel_i;
wire wbs_i_rom0_we_i;
wire wbs_i_rom0_cyc_i;
wire wbs_i_rom0_stb_i;
wire [2:0] wbs_i_rom0_cti_i;
wire [1:0] wbs_i_rom0_bte_i;
wire [wbs_i_rom0_data_width-1:0] wbs_i_rom0_dat_o;
wire wbs_i_rom0_ack_o;
wire wbs_i_rom0_err_o;
wire wbs_i_rom0_rty_o;
// mc0 instruction bus wires
wire [31:0] wbs_i_mc0_adr_i;
wire [wbs_i_mc0_data_width-1:0] wbs_i_mc0_dat_i;
wire [3:0] wbs_i_mc0_sel_i;
wire wbs_i_mc0_we_i;
wire wbs_i_mc0_cyc_i;
wire wbs_i_mc0_stb_i;
wire [2:0] wbs_i_mc0_cti_i;
wire [1:0] wbs_i_mc0_bte_i;
wire [wbs_i_mc0_data_width-1:0] wbs_i_mc0_dat_o;
wire wbs_i_mc0_ack_o;
wire wbs_i_mc0_err_o;
wire wbs_i_mc0_rty_o;
// Data bus slave wires //
// mc0 data bus wires
wire [31:0] wbs_d_mc0_adr_i;
wire [wbs_d_mc0_data_width-1:0] wbs_d_mc0_dat_i;
wire [3:0] wbs_d_mc0_sel_i;
wire wbs_d_mc0_we_i;
wire wbs_d_mc0_cyc_i;
wire wbs_d_mc0_stb_i;
wire [2:0] wbs_d_mc0_cti_i;
wire [1:0] wbs_d_mc0_bte_i;
wire [wbs_d_mc0_data_width-1:0] wbs_d_mc0_dat_o;
wire wbs_d_mc0_ack_o;
wire wbs_d_mc0_err_o;
wire wbs_d_mc0_rty_o;
// i2c0 wires
wire [31:0] wbs_d_i2c0_adr_i;
wire [wbs_d_i2c0_data_width-1:0] wbs_d_i2c0_dat_i;
wire [3:0] wbs_d_i2c0_sel_i;
wire wbs_d_i2c0_we_i;
wire wbs_d_i2c0_cyc_i;
wire wbs_d_i2c0_stb_i;
wire [2:0] wbs_d_i2c0_cti_i;
wire [1:0] wbs_d_i2c0_bte_i;
wire [wbs_d_i2c0_data_width-1:0] wbs_d_i2c0_dat_o;
wire wbs_d_i2c0_ack_o;
wire wbs_d_i2c0_err_o;
wire wbs_d_i2c0_rty_o;
// i2c1 wires
wire [31:0] wbs_d_i2c1_adr_i;
wire [wbs_d_i2c1_data_width-1:0] wbs_d_i2c1_dat_i;
wire [3:0] wbs_d_i2c1_sel_i;
wire wbs_d_i2c1_we_i;
wire wbs_d_i2c1_cyc_i;
wire wbs_d_i2c1_stb_i;
wire [2:0] wbs_d_i2c1_cti_i;
wire [1:0] wbs_d_i2c1_bte_i;
wire [wbs_d_i2c1_data_width-1:0] wbs_d_i2c1_dat_o;
wire wbs_d_i2c1_ack_o;
wire wbs_d_i2c1_err_o;
wire wbs_d_i2c1_rty_o;
// spi0 wires
wire [31:0] wbs_d_spi0_adr_i;
wire [wbs_d_spi0_data_width-1:0] wbs_d_spi0_dat_i;
wire [3:0] wbs_d_spi0_sel_i;
wire wbs_d_spi0_we_i;
wire wbs_d_spi0_cyc_i;
wire wbs_d_spi0_stb_i;
wire [2:0] wbs_d_spi0_cti_i;
wire [1:0] wbs_d_spi0_bte_i;
wire [wbs_d_spi0_data_width-1:0] wbs_d_spi0_dat_o;
wire wbs_d_spi0_ack_o;
wire wbs_d_spi0_err_o;
wire wbs_d_spi0_rty_o;
// uart0 wires
wire [31:0] wbs_d_uart0_adr_i;
wire [wbs_d_uart0_data_width-1:0] wbs_d_uart0_dat_i;
wire [3:0] wbs_d_uart0_sel_i;
wire wbs_d_uart0_we_i;
wire wbs_d_uart0_cyc_i;
wire wbs_d_uart0_stb_i;
wire [2:0] wbs_d_uart0_cti_i;
wire [1:0] wbs_d_uart0_bte_i;
wire [wbs_d_uart0_data_width-1:0] wbs_d_uart0_dat_o;
wire wbs_d_uart0_ack_o;
wire wbs_d_uart0_err_o;
wire wbs_d_uart0_rty_o;
// gpio0 wires
wire [31:0] wbs_d_gpio0_adr_i;
wire [wbs_d_gpio0_data_width-1:0] wbs_d_gpio0_dat_i;
wire [3:0] wbs_d_gpio0_sel_i;
wire wbs_d_gpio0_we_i;
wire wbs_d_gpio0_cyc_i;
wire wbs_d_gpio0_stb_i;
wire [2:0] wbs_d_gpio0_cti_i;
wire [1:0] wbs_d_gpio0_bte_i;
wire [wbs_d_gpio0_data_width-1:0] wbs_d_gpio0_dat_o;
wire wbs_d_gpio0_ack_o;
wire wbs_d_gpio0_err_o;
wire wbs_d_gpio0_rty_o;
// eth0 slave wires
wire [31:0] wbs_d_eth0_adr_i;
wire [wbs_d_eth0_data_width-1:0] wbs_d_eth0_dat_i;
wire [3:0] wbs_d_eth0_sel_i;
wire wbs_d_eth0_we_i;
wire wbs_d_eth0_cyc_i;
wire wbs_d_eth0_stb_i;
wire [2:0] wbs_d_eth0_cti_i;
wire [1:0] wbs_d_eth0_bte_i;
wire [wbs_d_eth0_data_width-1:0] wbs_d_eth0_dat_o;
wire wbs_d_eth0_ack_o;
wire wbs_d_eth0_err_o;
wire wbs_d_eth0_rty_o;
// eth0 master wires
wire [wbm_eth0_addr_width-1:0] wbm_eth0_adr_o;
wire [wbm_eth0_data_width-1:0] wbm_eth0_dat_o;
wire [3:0] wbm_eth0_sel_o;
wire wbm_eth0_we_o;
wire wbm_eth0_cyc_o;
wire wbm_eth0_stb_o;
wire [2:0] wbm_eth0_cti_o;
wire [1:0] wbm_eth0_bte_o;
wire [wbm_eth0_data_width-1:0] wbm_eth0_dat_i;
wire wbm_eth0_ack_i;
wire wbm_eth0_err_i;
wire wbm_eth0_rty_i;
//
// Wishbone instruction bus arbiter
//
arbiter_ibus arbiter_ibus0
(
// Instruction Bus Master
// Inputs to arbiter from master
.wbm_adr_o (wbm_i_or12_adr_o),
.wbm_dat_o (wbm_i_or12_dat_o),
.wbm_sel_o (wbm_i_or12_sel_o),
.wbm_we_o (wbm_i_or12_we_o),
.wbm_cyc_o (wbm_i_or12_cyc_o),
.wbm_stb_o (wbm_i_or12_stb_o),
.wbm_cti_o (wbm_i_or12_cti_o),
.wbm_bte_o (wbm_i_or12_bte_o),
// Outputs to master from arbiter
.wbm_dat_i (wbm_i_or12_dat_i),
.wbm_ack_i (wbm_i_or12_ack_i),
.wbm_err_i (wbm_i_or12_err_i),
.wbm_rty_i (wbm_i_or12_rty_i),
// Slave 0
// Inputs to slave from arbiter
.wbs0_adr_i (wbs_i_rom0_adr_i),
.wbs0_dat_i (wbs_i_rom0_dat_i),
.wbs0_sel_i (wbs_i_rom0_sel_i),
.wbs0_we_i (wbs_i_rom0_we_i),
.wbs0_cyc_i (wbs_i_rom0_cyc_i),
.wbs0_stb_i (wbs_i_rom0_stb_i),
.wbs0_cti_i (wbs_i_rom0_cti_i),
.wbs0_bte_i (wbs_i_rom0_bte_i),
// Outputs from slave to arbiter
.wbs0_dat_o (wbs_i_rom0_dat_o),
.wbs0_ack_o (wbs_i_rom0_ack_o),
.wbs0_err_o (wbs_i_rom0_err_o),
.wbs0_rty_o (wbs_i_rom0_rty_o),
// Slave 1
// Inputs to slave from arbiter
.wbs1_adr_i (wbs_i_mc0_adr_i),
.wbs1_dat_i (wbs_i_mc0_dat_i),
.wbs1_sel_i (wbs_i_mc0_sel_i),
.wbs1_we_i (wbs_i_mc0_we_i),
.wbs1_cyc_i (wbs_i_mc0_cyc_i),
.wbs1_stb_i (wbs_i_mc0_stb_i),
.wbs1_cti_i (wbs_i_mc0_cti_i),
.wbs1_bte_i (wbs_i_mc0_bte_i),
// Outputs from slave to arbiter
.wbs1_dat_o (wbs_i_mc0_dat_o),
.wbs1_ack_o (wbs_i_mc0_ack_o),
.wbs1_err_o (wbs_i_mc0_err_o),
.wbs1_rty_o (wbs_i_mc0_rty_o),
// Clock, reset inputs
.wb_clk (wb_clk),
.wb_rst (wb_rst));
defparam arbiter_ibus0.wb_addr_match_width = ibus_arb_addr_match_width;
defparam arbiter_ibus0.slave0_adr = ibus_arb_slave0_adr; // FLASH ROM
defparam arbiter_ibus0.slave1_adr = ibus_arb_slave1_adr; // Main memory
//
// Wishbone data bus arbiter
//
arbiter_dbus arbiter_dbus0
(
// Master 0
// Inputs to arbiter from master
.wbm0_adr_o (wbm_d_or12_adr_o),
.wbm0_dat_o (wbm_d_or12_dat_o),
.wbm0_sel_o (wbm_d_or12_sel_o),
.wbm0_we_o (wbm_d_or12_we_o),
.wbm0_cyc_o (wbm_d_or12_cyc_o),
.wbm0_stb_o (wbm_d_or12_stb_o),
.wbm0_cti_o (wbm_d_or12_cti_o),
.wbm0_bte_o (wbm_d_or12_bte_o),
// Outputs to master from arbiter
.wbm0_dat_i (wbm_d_or12_dat_i),
.wbm0_ack_i (wbm_d_or12_ack_i),
.wbm0_err_i (wbm_d_or12_err_i),
.wbm0_rty_i (wbm_d_or12_rty_i),
// Master 0
// Inputs to arbiter from master
.wbm1_adr_o (wbm_d_dbg_adr_o),
.wbm1_dat_o (wbm_d_dbg_dat_o),
.wbm1_we_o (wbm_d_dbg_we_o),
.wbm1_cyc_o (wbm_d_dbg_cyc_o),
.wbm1_sel_o (wbm_d_dbg_sel_o),
.wbm1_stb_o (wbm_d_dbg_stb_o),
.wbm1_cti_o (wbm_d_dbg_cti_o),
.wbm1_bte_o (wbm_d_dbg_bte_o),
// Outputs to master from arbiter
.wbm1_dat_i (wbm_d_dbg_dat_i),
.wbm1_ack_i (wbm_d_dbg_ack_i),
.wbm1_err_i (wbm_d_dbg_err_i),
.wbm1_rty_i (wbm_d_dbg_rty_i),
// Slaves
.wbs0_adr_i (wbs_d_mc0_adr_i),
.wbs0_dat_i (wbs_d_mc0_dat_i),
.wbs0_sel_i (wbs_d_mc0_sel_i),
.wbs0_we_i (wbs_d_mc0_we_i),
.wbs0_cyc_i (wbs_d_mc0_cyc_i),
.wbs0_stb_i (wbs_d_mc0_stb_i),
.wbs0_cti_i (wbs_d_mc0_cti_i),
.wbs0_bte_i (wbs_d_mc0_bte_i),
.wbs0_dat_o (wbs_d_mc0_dat_o),
.wbs0_ack_o (wbs_d_mc0_ack_o),
.wbs0_err_o (wbs_d_mc0_err_o),
.wbs0_rty_o (wbs_d_mc0_rty_o),
.wbs1_adr_i (wbs_d_eth0_adr_i),
.wbs1_dat_i (wbs_d_eth0_dat_i),
.wbs1_sel_i (wbs_d_eth0_sel_i),
.wbs1_we_i (wbs_d_eth0_we_i),
.wbs1_cyc_i (wbs_d_eth0_cyc_i),
.wbs1_stb_i (wbs_d_eth0_stb_i),
.wbs1_cti_i (wbs_d_eth0_cti_i),
.wbs1_bte_i (wbs_d_eth0_bte_i),
.wbs1_dat_o (wbs_d_eth0_dat_o),
.wbs1_ack_o (wbs_d_eth0_ack_o),
.wbs1_err_o (wbs_d_eth0_err_o),
.wbs1_rty_o (wbs_d_eth0_rty_o),
.wbs2_adr_i (wbm_b_d_adr_o),
.wbs2_dat_i (wbm_b_d_dat_o),
.wbs2_sel_i (wbm_b_d_sel_o),
.wbs2_we_i (wbm_b_d_we_o),
.wbs2_cyc_i (wbm_b_d_cyc_o),
.wbs2_stb_i (wbm_b_d_stb_o),
.wbs2_cti_i (wbm_b_d_cti_o),
.wbs2_bte_i (wbm_b_d_bte_o),
.wbs2_dat_o (wbm_b_d_dat_i),
.wbs2_ack_o (wbm_b_d_ack_i),
.wbs2_err_o (wbm_b_d_err_i),
.wbs2_rty_o (wbm_b_d_rty_i),
// Clock, reset inputs
.wb_clk (wb_clk),
.wb_rst (wb_rst));
// These settings are from top level params file
defparam arbiter_dbus0.wb_addr_match_width = dbus_arb_wb_addr_match_width;
defparam arbiter_dbus0.wb_num_slaves = dbus_arb_wb_num_slaves;
defparam arbiter_dbus0.slave0_adr = dbus_arb_slave0_adr;
defparam arbiter_dbus0.slave1_adr = dbus_arb_slave1_adr;
//
// Wishbone byte-wide bus arbiter
//
arbiter_bytebus arbiter_bytebus0
(
// Master 0
// Inputs to arbiter from master
.wbm0_adr_o (wbm_b_d_adr_o),
.wbm0_dat_o (wbm_b_d_dat_o),
.wbm0_sel_o (wbm_b_d_sel_o),
.wbm0_we_o (wbm_b_d_we_o),
.wbm0_cyc_o (wbm_b_d_cyc_o),
.wbm0_stb_o (wbm_b_d_stb_o),
.wbm0_cti_o (wbm_b_d_cti_o),
.wbm0_bte_o (wbm_b_d_bte_o),
// Outputs to master from arbiter
.wbm0_dat_i (wbm_b_d_dat_i),
.wbm0_ack_i (wbm_b_d_ack_i),
.wbm0_err_i (wbm_b_d_err_i),
.wbm0_rty_i (wbm_b_d_rty_i),
// Byte bus slaves
.wbs0_adr_i (wbs_d_uart0_adr_i),
.wbs0_dat_i (wbs_d_uart0_dat_i),
.wbs0_we_i (wbs_d_uart0_we_i),
.wbs0_cyc_i (wbs_d_uart0_cyc_i),
.wbs0_stb_i (wbs_d_uart0_stb_i),
.wbs0_cti_i (wbs_d_uart0_cti_i),
.wbs0_bte_i (wbs_d_uart0_bte_i),
.wbs0_dat_o (wbs_d_uart0_dat_o),
.wbs0_ack_o (wbs_d_uart0_ack_o),
.wbs0_err_o (wbs_d_uart0_err_o),
.wbs0_rty_o (wbs_d_uart0_rty_o),
.wbs1_adr_i (wbs_d_gpio0_adr_i),
.wbs1_dat_i (wbs_d_gpio0_dat_i),
.wbs1_we_i (wbs_d_gpio0_we_i),
.wbs1_cyc_i (wbs_d_gpio0_cyc_i),
.wbs1_stb_i (wbs_d_gpio0_stb_i),
.wbs1_cti_i (wbs_d_gpio0_cti_i),
.wbs1_bte_i (wbs_d_gpio0_bte_i),
.wbs1_dat_o (wbs_d_gpio0_dat_o),
.wbs1_ack_o (wbs_d_gpio0_ack_o),
.wbs1_err_o (wbs_d_gpio0_err_o),
.wbs1_rty_o (wbs_d_gpio0_rty_o),
.wbs2_adr_i (wbs_d_i2c0_adr_i),
.wbs2_dat_i (wbs_d_i2c0_dat_i),
.wbs2_we_i (wbs_d_i2c0_we_i),
.wbs2_cyc_i (wbs_d_i2c0_cyc_i),
.wbs2_stb_i (wbs_d_i2c0_stb_i),
.wbs2_cti_i (wbs_d_i2c0_cti_i),
.wbs2_bte_i (wbs_d_i2c0_bte_i),
.wbs2_dat_o (wbs_d_i2c0_dat_o),
.wbs2_ack_o (wbs_d_i2c0_ack_o),
.wbs2_err_o (wbs_d_i2c0_err_o),
.wbs2_rty_o (wbs_d_i2c0_rty_o),
.wbs3_adr_i (wbs_d_i2c1_adr_i),
.wbs3_dat_i (wbs_d_i2c1_dat_i),
.wbs3_we_i (wbs_d_i2c1_we_i),
.wbs3_cyc_i (wbs_d_i2c1_cyc_i),
.wbs3_stb_i (wbs_d_i2c1_stb_i),
.wbs3_cti_i (wbs_d_i2c1_cti_i),
.wbs3_bte_i (wbs_d_i2c1_bte_i),
.wbs3_dat_o (wbs_d_i2c1_dat_o),
.wbs3_ack_o (wbs_d_i2c1_ack_o),
.wbs3_err_o (wbs_d_i2c1_err_o),
.wbs3_rty_o (wbs_d_i2c1_rty_o),
.wbs4_adr_i (wbs_d_spi0_adr_i),
.wbs4_dat_i (wbs_d_spi0_dat_i),
.wbs4_we_i (wbs_d_spi0_we_i),
.wbs4_cyc_i (wbs_d_spi0_cyc_i),
.wbs4_stb_i (wbs_d_spi0_stb_i),
.wbs4_cti_i (wbs_d_spi0_cti_i),
.wbs4_bte_i (wbs_d_spi0_bte_i),
.wbs4_dat_o (wbs_d_spi0_dat_o),
.wbs4_ack_o (wbs_d_spi0_ack_o),
.wbs4_err_o (wbs_d_spi0_err_o),
.wbs4_rty_o (wbs_d_spi0_rty_o),
// Clock, reset inputs
.wb_clk (wb_clk),
.wb_rst (wb_rst));
defparam arbiter_bytebus0.wb_addr_match_width = bbus_arb_wb_addr_match_width;
defparam arbiter_bytebus0.wb_num_slaves = bbus_arb_wb_num_slaves;
defparam arbiter_bytebus0.slave0_adr = bbus_arb_slave0_adr;
defparam arbiter_bytebus0.slave1_adr = bbus_arb_slave1_adr;
defparam arbiter_bytebus0.slave2_adr = bbus_arb_slave2_adr;
defparam arbiter_bytebus0.slave3_adr = bbus_arb_slave3_adr;
defparam arbiter_bytebus0.slave4_adr = bbus_arb_slave4_adr;
//
// Wires
//
wire [30:0] or1200_pic_ints;
wire [31:0] or1200_dbg_dat_i;
wire [31:0] or1200_dbg_adr_i;
wire or1200_dbg_we_i;
wire or1200_dbg_stb_i;
wire or1200_dbg_ack_o;
wire [31:0] or1200_dbg_dat_o;
wire or1200_dbg_stall_i;
wire or1200_dbg_ewt_i;
wire [3:0] or1200_dbg_lss_o;
wire [1:0] or1200_dbg_is_o;
wire [10:0] or1200_dbg_wp_o;
wire or1200_dbg_bp_o;
wire or1200_dbg_rst;
wire or1200_clk, or1200_rst;
wire sig_tick;
`ifdef JTAG_DEBUG
assign jtag_gnd = 0;
assign jtag_vdd = 1;
////////////////////////////////////////////////////////////////////////
//
// JTAG TAP
//
////////////////////////////////////////////////////////////////////////
//
// Wires
//
wire dbg_if_select;
wire dbg_if_tdo;
wire jtag_tap_tdo;
wire jtag_tap_shift_dr, jtag_tap_pause_dr,
jtag_tap_upate_dr, jtag_tap_capture_dr;
//
// Instantiation
//
jtag_tap jtag_tap0
(
// Ports to pads
.tdo_pad_o (tdo_pad_o),
.tms_pad_i (tms_pad_i),
.tck_pad_i (dbg_tck),
.trst_pad_i (async_rst),
.tdi_pad_i (tdi_pad_i),
.tdo_padoe_o (tdo_padoe_o),
.tdo_o (jtag_tap_tdo),
.shift_dr_o (jtag_tap_shift_dr),
.pause_dr_o (jtag_tap_pause_dr),
.update_dr_o (jtag_tap_update_dr),
.capture_dr_o (jtag_tap_capture_dr),
.extest_select_o (),
.sample_preload_select_o (),
.mbist_select_o (),
.debug_select_o (dbg_if_select),
.bs_chain_tdi_i (1'b0),
.mbist_tdi_i (1'b0),
.debug_tdi_i (dbg_if_tdo)
);
////////////////////////////////////////////////////////////////////////
//
// OR1200 Debug Interface
//
////////////////////////////////////////////////////////////////////////
dbg_if dbg_if0
(
// OR1200 interface
.cpu0_clk_i (or1200_clk),
.cpu0_rst_o (or1200_dbg_rst),
.cpu0_addr_o (or1200_dbg_adr_i),
.cpu0_data_o (or1200_dbg_dat_i),
.cpu0_stb_o (or1200_dbg_stb_i),
.cpu0_we_o (or1200_dbg_we_i),
.cpu0_data_i (or1200_dbg_dat_o),
.cpu0_ack_i (or1200_dbg_ack_o),
.cpu0_stall_o (or1200_dbg_stall_i),
.cpu0_bp_i (or1200_dbg_bp_o),
// TAP interface
.tck_i (dbg_tck),
.tdi_i (jtag_tap_tdo),
.tdo_o (dbg_if_tdo),
.rst_i (wb_rst),
.shift_dr_i (jtag_tap_shift_dr),
.pause_dr_i (jtag_tap_pause_dr),
.update_dr_i (jtag_tap_update_dr),
.debug_select_i (dbg_if_select),
// Wishbone debug master
.wb_clk_i (wb_clk),
.wb_dat_i (wbm_d_dbg_dat_i),
.wb_ack_i (wbm_d_dbg_ack_i),
.wb_err_i (wbm_d_dbg_err_i),
.wb_adr_o (wbm_d_dbg_adr_o),
.wb_dat_o (wbm_d_dbg_dat_o),
.wb_cyc_o (wbm_d_dbg_cyc_o),
.wb_stb_o (wbm_d_dbg_stb_o),
.wb_sel_o (wbm_d_dbg_sel_o),
.wb_we_o (wbm_d_dbg_we_o ),
.wb_cti_o (wbm_d_dbg_cti_o),
.wb_cab_o (/* UNUSED */),
.wb_bte_o (wbm_d_dbg_bte_o)
);
`elsif ADV_DEBUG
wire jtag_tck;
wire debug_tdi;
wire debug_tdo;
wire capture_dr;
wire shift_dr;
wire pause_dr;
wire update_dr;
wire debug_select;
wire test_logic_reset;
adbg_top dbg_top(
// JTAG pins
.tck_i ( jtag_tck ),
.tdi_i ( debug_tdi ),
.tdo_o ( debug_tdo ),
.rst_i ( test_logic_reset ), //cable without rst
// Boundary Scan signals
.capture_dr_i ( capture_dr ),
.shift_dr_i ( shift_dr ),
.pause_dr_i ( pause_dr ),
.update_dr_i ( update_dr ),
.debug_select_i( debug_select ),
// WISHBONE common
.wb_clk_i ( wb_clk ),
.wb_rst_i ( wb_rst ),
// WISHBONE master interface
.wb_adr_o ( wbm_d_dbg_adr_o ),
.wb_dat_i ( wbm_d_dbg_dat_i ),
.wb_dat_o ( wbm_d_dbg_dat_o ),
.wb_sel_o ( wbm_d_dbg_sel_o ),
.wb_we_o ( wbm_d_dbg_we_o ),
.wb_stb_o ( wbm_d_dbg_stb_o ),
.wb_cyc_o ( wbm_d_dbg_cyc_o ),
.wb_ack_i ( wbm_d_dbg_ack_i ),
.wb_err_i ( wbm_d_dbg_err_i ),
.wb_cti_o ( wbm_d_dbg_cti_o ),
.wb_bte_o ( wbm_d_dbg_bte_o ),
// RISC signals
.cpu0_clk_i ( wb_clk ),
.cpu0_addr_o ( or1200_dbg_adr_i ),
.cpu0_data_i ( or1200_dbg_dat_o ),
.cpu0_data_o ( or1200_dbg_dat_i ),
.cpu0_bp_i ( or1200_dbg_bp_o ),
.cpu0_stall_o( or1200_dbg_stall_i ),
.cpu0_stb_o ( or1200_dbg_stb_i ),
.cpu0_we_o ( or1200_dbg_we_i ),
.cpu0_ack_i ( or1200_dbg_ack_o ),
.cpu0_rst_o ( or1200_dbg_rst)
);
xilinx_internal_jtag tap_top(
.tck_o( jtag_tck ),
.debug_tdo_i( debug_tdo ),
.tdi_o( debug_tdi ),
.test_logic_reset_o( test_logic_reset ),
.run_test_idle_o( ),
.shift_dr_o( shift_dr ),
.capture_dr_o( capture_dr ),
.pause_dr_o( pause_dr ),
.update_dr_o( update_dr ),
.debug_select_o( debug_select )
);
assign tdo_pad_o = 0;
////////////////////////////////////////////////////////////////////////
`else // !`ifdef JTAG_DEBUG !`ifdef ADV_DEBUG
assign wbm_d_dbg_adr_o = 0;
assign wbm_d_dbg_dat_o = 0;
assign wbm_d_dbg_cyc_o = 0;
assign wbm_d_dbg_stb_o = 0;
assign wbm_d_dbg_sel_o = 0;
assign wbm_d_dbg_we_o = 0;
assign wbm_d_dbg_cti_o = 0;
assign wbm_d_dbg_bte_o = 0;
assign or1200_dbg_adr_i = 0;
assign or1200_dbg_dat_i = 0;
assign or1200_dbg_stb_i = 0;
assign or1200_dbg_we_i = 0;
assign or1200_dbg_stall_i = 0;
////////////////////////////////////////////////////////////////////////
`endif // !`ifdef JTAG_DEBUG and ! `ifdef ADV_DEBUG
////////////////////////////////////////////////////////////////////////
//
// OpenRISC processor
//
////////////////////////////////////////////////////////////////////////
//
// Assigns
//
assign or1200_clk = wb_clk;
assign or1200_rst = wb_rst | or1200_dbg_rst;
//
// Instantiation
//
or1200_top or1200_top0
(
// Instruction bus, clocks, reset
.iwb_clk_i (wb_clk),
.iwb_rst_i (wb_rst),
.iwb_ack_i (wbm_i_or12_ack_i),
.iwb_err_i (wbm_i_or12_err_i),
.iwb_rty_i (wbm_i_or12_rty_i),
.iwb_dat_i (wbm_i_or12_dat_i),
.iwb_cyc_o (wbm_i_or12_cyc_o),
.iwb_adr_o (wbm_i_or12_adr_o),
.iwb_stb_o (wbm_i_or12_stb_o),
.iwb_we_o (wbm_i_or12_we_o),
.iwb_sel_o (wbm_i_or12_sel_o),
.iwb_dat_o (wbm_i_or12_dat_o),
.iwb_cti_o (wbm_i_or12_cti_o),
.iwb_bte_o (wbm_i_or12_bte_o),
// Data bus, clocks, reset
.dwb_clk_i (wb_clk),
.dwb_rst_i (wb_rst),
.dwb_ack_i (wbm_d_or12_ack_i),
.dwb_err_i (wbm_d_or12_err_i),
.dwb_rty_i (wbm_d_or12_rty_i),
.dwb_dat_i (wbm_d_or12_dat_i),
.dwb_cyc_o (wbm_d_or12_cyc_o),
.dwb_adr_o (wbm_d_or12_adr_o),
.dwb_stb_o (wbm_d_or12_stb_o),
.dwb_we_o (wbm_d_or12_we_o),
.dwb_sel_o (wbm_d_or12_sel_o),
.dwb_dat_o (wbm_d_or12_dat_o),
.dwb_cti_o (wbm_d_or12_cti_o),
.dwb_bte_o (wbm_d_or12_bte_o),
// Debug interface ports
.dbg_stall_i (or1200_dbg_stall_i),
//.dbg_ewt_i (or1200_dbg_ewt_i),
.dbg_ewt_i (1'b0),
.dbg_lss_o (or1200_dbg_lss_o),
.dbg_is_o (or1200_dbg_is_o),
.dbg_wp_o (or1200_dbg_wp_o),
.dbg_bp_o (or1200_dbg_bp_o),
.dbg_adr_i (or1200_dbg_adr_i),
.dbg_we_i (or1200_dbg_we_i ),
.dbg_stb_i (or1200_dbg_stb_i),
.dbg_dat_i (or1200_dbg_dat_i),
.dbg_dat_o (or1200_dbg_dat_o),
.dbg_ack_o (or1200_dbg_ack_o),
.pm_clksd_o (),
.pm_dc_gate_o (),
.pm_ic_gate_o (),
.pm_dmmu_gate_o (),
.pm_immu_gate_o (),
.pm_tt_gate_o (),
.pm_cpu_gate_o (),
.pm_wakeup_o (),
.pm_lvolt_o (),
// Core clocks, resets
.clk_i (or1200_clk),
.rst_i (or1200_rst),
.clmode_i (2'b00),
// Interrupts
.pic_ints_i (or1200_pic_ints),
.sig_tick(sig_tick),
/*
.mbist_so_o (),
.mbist_si_i (0),
.mbist_ctrl_i (0),
*/
.pm_cpustall_i (1'b0)
);
////////////////////////////////////////////////////////////////////////
`ifdef XILINX_DDR2
////////////////////////////////////////////////////////////////////////
//
// Xilinx MIG DDR2 controller, Wishbone interface
//
////////////////////////////////////////////////////////////////////////
xilinx_ddr2 xilinx_ddr2_0
(
.wbm0_adr_i (wbm_eth0_adr_o),
.wbm0_bte_i (wbm_eth0_bte_o),
.wbm0_cti_i (wbm_eth0_cti_o),
.wbm0_cyc_i (wbm_eth0_cyc_o),
.wbm0_dat_i (wbm_eth0_dat_o),
.wbm0_sel_i (wbm_eth0_sel_o),
.wbm0_stb_i (wbm_eth0_stb_o),
.wbm0_we_i (wbm_eth0_we_o),
.wbm0_ack_o (wbm_eth0_ack_i),
.wbm0_err_o (wbm_eth0_err_i),
.wbm0_rty_o (wbm_eth0_rty_i),
.wbm0_dat_o (wbm_eth0_dat_i),
.wbm1_adr_i (wbs_d_mc0_adr_i),
.wbm1_bte_i (wbs_d_mc0_bte_i),
.wbm1_cti_i (wbs_d_mc0_cti_i),
.wbm1_cyc_i (wbs_d_mc0_cyc_i),
.wbm1_dat_i (wbs_d_mc0_dat_i),
.wbm1_sel_i (wbs_d_mc0_sel_i),
.wbm1_stb_i (wbs_d_mc0_stb_i),
.wbm1_we_i (wbs_d_mc0_we_i),
.wbm1_ack_o (wbs_d_mc0_ack_o),
.wbm1_err_o (wbs_d_mc0_err_o),
.wbm1_rty_o (wbs_d_mc0_rty_o),
.wbm1_dat_o (wbs_d_mc0_dat_o),
.wbm2_adr_i (wbs_i_mc0_adr_i),
.wbm2_bte_i (wbs_i_mc0_bte_i),
.wbm2_cti_i (wbs_i_mc0_cti_i),
.wbm2_cyc_i (wbs_i_mc0_cyc_i),
.wbm2_dat_i (wbs_i_mc0_dat_i),
.wbm2_sel_i (wbs_i_mc0_sel_i),
.wbm2_stb_i (wbs_i_mc0_stb_i),
.wbm2_we_i (wbs_i_mc0_we_i),
.wbm2_ack_o (wbs_i_mc0_ack_o),
.wbm2_err_o (wbs_i_mc0_err_o),
.wbm2_rty_o (wbs_i_mc0_rty_o),
.wbm2_dat_o (wbs_i_mc0_dat_o),
.wb_clk (wb_clk),
.wb_rst (wb_rst),
.ddr2_a (ddr2_a[12:0]),
.ddr2_ba (ddr2_ba[1:0]),
.ddr2_ras_n (ddr2_ras_n),
.ddr2_cas_n (ddr2_cas_n),
.ddr2_we_n (ddr2_we_n),
.ddr2_cs_n (ddr2_cs_n),
.ddr2_odt (ddr2_odt),
.ddr2_cke (ddr2_cke),
.ddr2_dm (ddr2_dm[7:0]),
.ddr2_ck (ddr2_ck[1:0]),
.ddr2_ck_n (ddr2_ck_n[1:0]),
.ddr2_dq (ddr2_dq[63:0]),
.ddr2_dqs (ddr2_dqs[7:0]),
.ddr2_dqs_n (ddr2_dqs_n[7:0]),
.ddr2_if_clk (ddr2_if_clk),
.clk200 (clk200),
.ddr2_if_rst (ddr2_if_rst)
);
`endif
`ifdef ROM_WB
////////////////////////////////////////////////////////////////////////
//
// ROM
//
////////////////////////////////////////////////////////////////////////
rom rom0
(
.wb_dat_o (wbs_i_rom0_dat_o),
.wb_ack_o (wbs_i_rom0_ack_o),
.wb_adr_i (wbs_i_rom0_adr_i[(wbs_i_rom0_addr_width+2)-1:2]),
.wb_stb_i (wbs_i_rom0_stb_i),
.wb_cyc_i (wbs_i_rom0_cyc_i),
.wb_cti_i (wbs_i_rom0_cti_i),
.wb_bte_i (wbs_i_rom0_bte_i),
.wb_clk (wb_clk),
.wb_rst (wb_rst));
defparam rom0.addr_width = wbs_i_rom0_addr_width;
`else // !`ifdef ROM_WB
assign wbs_i_rom0_dat_o = 0;
assign wbs_i_rom0_ack_o = 0;
`endif // !`ifdef ROM_WB
assign wbs_i_rom0_err_o = 0;
assign wbs_i_rom0_rty_o = 0;
////////////////////////////////////////////////////////////////////////
`ifdef RAM_WB
////////////////////////////////////////////////////////////////////////
//
// Generic RAM
//
////////////////////////////////////////////////////////////////////////
ram_wb ram_wb0
(
// Wishbone slave interface 0
.wbm0_dat_i (wbs_i_mc0_dat_i),
.wbm0_adr_i (wbs_i_mc0_adr_i),
.wbm0_sel_i (wbs_i_mc0_sel_i),
.wbm0_cti_i (wbs_i_mc0_cti_i),
.wbm0_bte_i (wbs_i_mc0_bte_i),
.wbm0_we_i (wbs_i_mc0_we_i ),
.wbm0_cyc_i (wbs_i_mc0_cyc_i),
.wbm0_stb_i (wbs_i_mc0_stb_i),
.wbm0_dat_o (wbs_i_mc0_dat_o),
.wbm0_ack_o (wbs_i_mc0_ack_o),
.wbm0_err_o (wbs_i_mc0_err_o),
.wbm0_rty_o (wbs_i_mc0_rty_o),
// Wishbone slave interface 1
.wbm1_dat_i (wbs_d_mc0_dat_i),
.wbm1_adr_i (wbs_d_mc0_adr_i),
.wbm1_sel_i (wbs_d_mc0_sel_i),
.wbm1_cti_i (wbs_d_mc0_cti_i),
.wbm1_bte_i (wbs_d_mc0_bte_i),
.wbm1_we_i (wbs_d_mc0_we_i ),
.wbm1_cyc_i (wbs_d_mc0_cyc_i),
.wbm1_stb_i (wbs_d_mc0_stb_i),
.wbm1_dat_o (wbs_d_mc0_dat_o),
.wbm1_ack_o (wbs_d_mc0_ack_o),
.wbm1_err_o (wbs_d_mc0_err_o),
.wbm1_rty_o (wbs_d_mc0_rty_o),
// Wishbone slave interface 2
.wbm2_dat_i (wbm_eth0_dat_o),
.wbm2_adr_i (wbm_eth0_adr_o),
.wbm2_sel_i (wbm_eth0_sel_o),
.wbm2_cti_i (wbm_eth0_cti_o),
.wbm2_bte_i (wbm_eth0_bte_o),
.wbm2_we_i (wbm_eth0_we_o ),
.wbm2_cyc_i (wbm_eth0_cyc_o),
.wbm2_stb_i (wbm_eth0_stb_o),
.wbm2_dat_o (wbm_eth0_dat_i),
.wbm2_ack_o (wbm_eth0_ack_i),
.wbm2_err_o (wbm_eth0_err_i),
.wbm2_rty_o (wbm_eth0_rty_i),
// Clock, reset
.wb_clk_i (wb_clk),
.wb_rst_i (wb_rst));
defparam ram_wb0.aw = wb_aw;
defparam ram_wb0.dw = wb_dw;
defparam ram_wb0.mem_size_bytes = (256*1024*1024); // 8MB
defparam ram_wb0.mem_adr_width = 28; // log2(8192*1024)
////////////////////////////////////////////////////////////////////////
`endif // `ifdef RAM_WB
`ifdef ETH0
//
// Wires
//
wire eth0_irq;
wire [3:0] eth0_mtxd;
wire eth0_mtxen;
wire eth0_mtxerr;
wire eth0_mtx_clk;
wire eth0_mrx_clk;
wire [3:0] eth0_mrxd;
wire eth0_mrxdv;
wire eth0_mrxerr;
wire eth0_mcoll;
wire eth0_mcrs;
wire eth0_speed;
wire eth0_duplex;
wire eth0_link;
// Management interface wires
wire eth0_md_i;
wire eth0_md_o;
wire eth0_md_oe;
//
// assigns
// Hook up MII wires
assign eth0_mtx_clk = eth0_tx_clk;
assign eth0_tx_data = eth0_mtxd[3:0];
assign eth0_tx_en = eth0_mtxen;
assign eth0_tx_er = eth0_mtxerr;
assign eth0_mrxd[3:0] = eth0_rx_data;
assign eth0_mrxdv = eth0_dv;
assign eth0_mrxerr = eth0_rx_er;
assign eth0_mrx_clk = eth0_rx_clk;
assign eth0_mcoll = eth0_col;
assign eth0_mcrs = eth0_crs;
`ifdef XILINX
// Xilinx primitive for MDIO tristate
IOBUF iobuf_phy_smi_data
(
// Outputs
.O (eth0_md_i),
// Inouts
.IO (eth0_md_pad_io),
// Inputs
.I (eth0_md_o),
.T (!eth0_md_oe));
`else // !`ifdef XILINX
// Generic technology tristate control for management interface
assign eth0_md_pad_io = eth0_md_oe ? eth0_md_o : 1'bz;
assign eth0_md_i = eth0_md_pad_io;
`endif // !`ifdef XILINX
`ifdef ETH0_PHY_RST
assign eth0_rst_n_o = !wb_rst;
`endif
ethmac ethmac0
(
// Wishbone Slave interface
.wb_clk_i (wb_clk),
.wb_rst_i (wb_rst),
.wb_dat_i (wbs_d_eth0_dat_i[31:0]),
.wb_adr_i (wbs_d_eth0_adr_i[wbs_d_eth0_addr_width-1:2]),
.wb_sel_i (wbs_d_eth0_sel_i[3:0]),
.wb_we_i (wbs_d_eth0_we_i),
.wb_cyc_i (wbs_d_eth0_cyc_i),
.wb_stb_i (wbs_d_eth0_stb_i),
.wb_dat_o (wbs_d_eth0_dat_o[31:0]),
.wb_err_o (wbs_d_eth0_err_o),
.wb_ack_o (wbs_d_eth0_ack_o),
// Wishbone Master Interface
.m_wb_adr_o (wbm_eth0_adr_o[31:0]),
.m_wb_sel_o (wbm_eth0_sel_o[3:0]),
.m_wb_we_o (wbm_eth0_we_o),
.m_wb_dat_o (wbm_eth0_dat_o[31:0]),
.m_wb_cyc_o (wbm_eth0_cyc_o),
.m_wb_stb_o (wbm_eth0_stb_o),
.m_wb_cti_o (wbm_eth0_cti_o[2:0]),
.m_wb_bte_o (wbm_eth0_bte_o[1:0]),
.m_wb_dat_i (wbm_eth0_dat_i[31:0]),
.m_wb_ack_i (wbm_eth0_ack_i),
.m_wb_err_i (wbm_eth0_err_i),
// Ethernet MII interface
// Transmit
.mtxd_pad_o (eth0_mtxd[3:0]),
.mtxen_pad_o (eth0_mtxen),
.mtxerr_pad_o (eth0_mtxerr),
.mtx_clk_pad_i (eth0_mtx_clk),
// Receive
.mrx_clk_pad_i (eth0_mrx_clk),
.mrxd_pad_i (eth0_mrxd[3:0]),
.mrxdv_pad_i (eth0_mrxdv),
.mrxerr_pad_i (eth0_mrxerr),
.mcoll_pad_i (eth0_mcoll),
.mcrs_pad_i (eth0_mcrs),
// Management interface
.md_pad_i (eth0_md_i),
.mdc_pad_o (eth0_mdc_pad_o),
.md_pad_o (eth0_md_o),
.md_padoe_o (eth0_md_oe),
// Processor interrupt
.int_o (eth0_irq)
/*
.mbist_so_o (),
.mbist_si_i (),
.mbist_ctrl_i ()
*/
);
assign wbs_d_eth0_rty_o = 0;
`else
assign wbs_d_eth0_dat_o = 0;
assign wbs_d_eth0_err_o = 0;
assign wbs_d_eth0_ack_o = 0;
assign wbs_d_eth0_rty_o = 0;
assign wbm_eth0_adr_o = 0;
assign wbm_eth0_sel_o = 0;
assign wbm_eth0_we_o = 0;
assign wbm_eth0_dat_o = 0;
assign wbm_eth0_cyc_o = 0;
assign wbm_eth0_stb_o = 0;
assign wbm_eth0_cti_o = 0;
assign wbm_eth0_bte_o = 0;
`endif
`ifdef UART0
////////////////////////////////////////////////////////////////////////
//
// UART0
//
////////////////////////////////////////////////////////////////////////
//
// Wires
//
wire uart0_srx;
wire uart0_stx;
wire uart0_irq;
//
// Assigns
//
assign wbs_d_uart0_err_o = 0;
assign wbs_d_uart0_rty_o = 0;
// Two UART lines coming to single one (ensure they go high when unconnected)
assign uart0_srx = uart0_srx_pad_i & uart0_srx_expheader_pad_i;
assign uart0_stx_pad_o = uart0_stx;
assign uart0_stx_expheader_pad_o = uart0_stx;
uart_top uart16550_0
(
// Wishbone slave interface
.wb_clk_i (wb_clk),
.wb_rst_i (wb_rst),
.wb_adr_i (wbs_d_uart0_adr_i[uart0_addr_width-1:0]),
.wb_dat_i (wbs_d_uart0_dat_i),
.wb_we_i (wbs_d_uart0_we_i),
.wb_stb_i (wbs_d_uart0_stb_i),
.wb_cyc_i (wbs_d_uart0_cyc_i),
//.wb_sel_i (),
.wb_dat_o (wbs_d_uart0_dat_o),
.wb_ack_o (wbs_d_uart0_ack_o),
.int_o (uart0_irq),
.stx_pad_o (uart0_stx),
.rts_pad_o (),
.dtr_pad_o (),
// .baud_o (),
// Inputs
.srx_pad_i (uart0_srx),
.cts_pad_i (1'b0),
.dsr_pad_i (1'b0),
.ri_pad_i (1'b0),
.dcd_pad_i (1'b0));
////////////////////////////////////////////////////////////////////////
`else // !`ifdef UART0
//
// Assigns
//
assign wbs_d_uart0_err_o = 0;
assign wbs_d_uart0_rty_o = 0;
assign wbs_d_uart0_ack_o = 0;
assign wbs_d_uart0_dat_o = 0;
////////////////////////////////////////////////////////////////////////
`endif // !`ifdef UART0
`ifdef SPI0
////////////////////////////////////////////////////////////////////////
//
// SPI0 controller
//
////////////////////////////////////////////////////////////////////////
//
// Wires
//
wire spi0_irq;
//
// Assigns
//
assign wbs_d_spi0_err_o = 0;
assign wbs_d_spi0_rty_o = 0;
//assign spi0_hold_n_o = 1;
//assign spi0_w_n_o = 1;
simple_spi spi0
(
// Wishbone slave interface
.clk_i (wb_clk),
.rst_i (wb_rst),
.cyc_i (wbs_d_spi0_cyc_i),
.stb_i (wbs_d_spi0_stb_i),
.adr_i (wbs_d_spi0_adr_i[spi0_wb_adr_width-1:0]),
.we_i (wbs_d_spi0_we_i),
.dat_i (wbs_d_spi0_dat_i),
.dat_o (wbs_d_spi0_dat_o),
.ack_o (wbs_d_spi0_ack_o),
// SPI IRQ
.inta_o (spi0_irq),
// External SPI interface
.sck_o (spi0_sck_o),
.ss_o (spi0_ss_o),
.mosi_o (spi0_mosi_o),
.miso_i (spi0_miso_i)
);
defparam spi0.slave_select_width = spi0_ss_width;
// SPI clock and MISO lines must go through STARTUP_VIRTEX5 block.
STARTUP_VIRTEX5 startup_virtex5
(
.CFGCLK(),
.CFGMCLK(),
.DINSPI(spi0_miso_i),
.EOS(),
.TCKSPI(),
.CLK(),
.GSR(1'b0),
.GTS(1'b0),
.USRCCLKO(spi0_sck_o),
.USRCCLKTS(1'b0),
.USRDONEO(),
.USRDONETS()
);
////////////////////////////////////////////////////////////////////////
`else // !`ifdef SPI0
//
// Assigns
//
assign wbs_d_spi0_dat_o = 0;
assign wbs_d_spi0_ack_o = 0;
assign wbs_d_spi0_err_o = 0;
assign wbs_d_spi0_rty_o = 0;
////////////////////////////////////////////////////////////////////////
`endif // !`ifdef SPI0
`ifdef I2C0
////////////////////////////////////////////////////////////////////////
//
// i2c controller 0
//
////////////////////////////////////////////////////////////////////////
//
// Wires
//
wire i2c0_irq;
wire scl0_pad_o;
wire scl0_padoen_o;
wire sda0_pad_o;
wire sda0_padoen_o;
i2c_master_slave
#
(
.DEFAULT_SLAVE_ADDR(HV0_SADR)
)
i2c_master_slave0
(
.wb_clk_i (wb_clk),
.wb_rst_i (wb_rst),
.arst_i (wb_rst),
.wb_adr_i (wbs_d_i2c0_adr_i[i2c_0_wb_adr_width-1:0]),
.wb_dat_i (wbs_d_i2c0_dat_i),
.wb_we_i (wbs_d_i2c0_we_i ),
.wb_cyc_i (wbs_d_i2c0_cyc_i),
.wb_stb_i (wbs_d_i2c0_stb_i),
.wb_dat_o (wbs_d_i2c0_dat_o),
.wb_ack_o (wbs_d_i2c0_ack_o),
.scl_pad_i (i2c0_scl_io ),
.scl_pad_o (scl0_pad_o ),
.scl_padoen_o (scl0_padoen_o ),
.sda_pad_i (i2c0_sda_io ),
.sda_pad_o (sda0_pad_o ),
.sda_padoen_o (sda0_padoen_o ),
// Interrupt
.wb_inta_o (i2c0_irq)
);
assign wbs_d_i2c0_err_o = 0;
assign wbs_d_i2c0_rty_o = 0;
// i2c phy lines
assign i2c0_scl_io = scl0_padoen_o ? 1'bz : scl0_pad_o;
assign i2c0_sda_io = sda0_padoen_o ? 1'bz : sda0_pad_o;
////////////////////////////////////////////////////////////////////////
`else // !`ifdef I2C0
assign wbs_d_i2c0_dat_o = 0;
assign wbs_d_i2c0_ack_o = 0;
assign wbs_d_i2c0_err_o = 0;
assign wbs_d_i2c0_rty_o = 0;
////////////////////////////////////////////////////////////////////////
`endif // !`ifdef I2C0
`ifdef I2C1
////////////////////////////////////////////////////////////////////////
//
// i2c controller 1
//
////////////////////////////////////////////////////////////////////////
//
// Wires
//
wire i2c1_irq;
wire scl1_pad_o;
wire scl1_padoen_o;
wire sda1_pad_o;
wire sda1_padoen_o;
i2c_master_slave
#
(
.DEFAULT_SLAVE_ADDR(HV1_SADR)
)
i2c_master_slave1
(
.wb_clk_i (wb_clk),
.wb_rst_i (wb_rst),
.arst_i (wb_rst),
.wb_adr_i (wbs_d_i2c1_adr_i[i2c_1_wb_adr_width-1:0]),
.wb_dat_i (wbs_d_i2c1_dat_i),
.wb_we_i (wbs_d_i2c1_we_i ),
.wb_cyc_i (wbs_d_i2c1_cyc_i),
.wb_stb_i (wbs_d_i2c1_stb_i),
.wb_dat_o (wbs_d_i2c1_dat_o),
.wb_ack_o (wbs_d_i2c1_ack_o),
.scl_pad_i (i2c1_scl_io ),
.scl_pad_o (scl1_pad_o ),
.scl_padoen_o (scl1_padoen_o ),
.sda_pad_i (i2c1_sda_io ),
.sda_pad_o (sda1_pad_o ),
.sda_padoen_o (sda1_padoen_o ),
// Interrupt
.wb_inta_o (i2c1_irq)
);
assign wbs_d_i2c1_err_o = 0;
assign wbs_d_i2c1_rty_o = 0;
// i2c phy lines
assign i2c1_scl_io = scl1_padoen_o ? 1'bz : scl1_pad_o;
assign i2c1_sda_io = sda1_padoen_o ? 1'bz : sda1_pad_o;
////////////////////////////////////////////////////////////////////////
`else // !`ifdef I2C1
assign wbs_d_i2c1_dat_o = 0;
assign wbs_d_i2c1_ack_o = 0;
assign wbs_d_i2c1_err_o = 0;
assign wbs_d_i2c1_rty_o = 0;
////////////////////////////////////////////////////////////////////////
`endif // !`ifdef I2C1
`ifdef GPIO0
////////////////////////////////////////////////////////////////////////
//
// GPIO 0
//
////////////////////////////////////////////////////////////////////////
gpio gpio0
(
// GPIO bus
.gpio_io (gpio0_io[gpio0_io_width-1:0]),
// Wishbone slave interface
.wb_adr_i (wbs_d_gpio0_adr_i[gpio0_wb_adr_width-1:0]),
.wb_dat_i (wbs_d_gpio0_dat_i),
.wb_we_i (wbs_d_gpio0_we_i),
.wb_cyc_i (wbs_d_gpio0_cyc_i),
.wb_stb_i (wbs_d_gpio0_stb_i),
.wb_cti_i (wbs_d_gpio0_cti_i),
.wb_bte_i (wbs_d_gpio0_bte_i),
.wb_dat_o (wbs_d_gpio0_dat_o),
.wb_ack_o (wbs_d_gpio0_ack_o),
.wb_err_o (wbs_d_gpio0_err_o),
.wb_rty_o (wbs_d_gpio0_rty_o),
.wb_clk (wb_clk),
.wb_rst (wb_rst)
);
defparam gpio0.gpio_io_width = gpio0_io_width;
defparam gpio0.gpio_dir_reset_val = gpio0_dir_reset_val;
defparam gpio0.gpio_o_reset_val = gpio0_o_reset_val;
////////////////////////////////////////////////////////////////////////
`else // !`ifdef GPIO0
assign wbs_d_gpio0_dat_o = 0;
assign wbs_d_gpio0_ack_o = 0;
assign wbs_d_gpio0_err_o = 0;
assign wbs_d_gpio0_rty_o = 0;
////////////////////////////////////////////////////////////////////////
`endif // !`ifdef GPIO0
////////////////////////////////////////////////////////////////////////
//
// OR1200 Interrupt assignment
//
////////////////////////////////////////////////////////////////////////
assign or1200_pic_ints[0] = 0; // Non-maskable inside OR1200
assign or1200_pic_ints[1] = 0; // Non-maskable inside OR1200
`ifdef UART0
assign or1200_pic_ints[2] = uart0_irq;
`else
assign or1200_pic_ints[2] = 0;
`endif
assign or1200_pic_ints[3] = 0;
`ifdef ETH0
assign or1200_pic_ints[4] = eth0_irq;
`else
assign or1200_pic_ints[4] = 0;
`endif
assign or1200_pic_ints[5] = 0;
`ifdef SPI0
assign or1200_pic_ints[6] = spi0_irq;
`else
assign or1200_pic_ints[6] = 0;
`endif
assign or1200_pic_ints[7] = 0;
assign or1200_pic_ints[8] = 0;
assign or1200_pic_ints[9] = 0;
`ifdef I2C0
assign or1200_pic_ints[10] = i2c0_irq;
`else
assign or1200_pic_ints[10] = 0;
`endif
`ifdef I2C1
assign or1200_pic_ints[11] = i2c1_irq;
`else
assign or1200_pic_ints[11] = 0;
`endif
assign or1200_pic_ints[12] = 0;
assign or1200_pic_ints[13] = 0;
assign or1200_pic_ints[14] = 0;
assign or1200_pic_ints[15] = 0;
assign or1200_pic_ints[16] = 0;
assign or1200_pic_ints[17] = 0;
assign or1200_pic_ints[18] = 0;
assign or1200_pic_ints[19] = 0;
assign or1200_pic_ints[20] = 0;
assign or1200_pic_ints[21] = 0;
assign or1200_pic_ints[22] = 0;
assign or1200_pic_ints[23] = 0;
assign or1200_pic_ints[24] = 0;
assign or1200_pic_ints[25] = 0;
assign or1200_pic_ints[26] = 0;
assign or1200_pic_ints[27] = 0;
assign or1200_pic_ints[28] = 0;
assign or1200_pic_ints[29] = 0;
assign or1200_pic_ints[30] = 0;
endmodule // orpsoc_top
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLRTN_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__DLRTN_PP_BLACKBOX_V
/**
* dlrtn: Delay latch, inverted reset, inverted enable, single output.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__dlrtn (
Q ,
RESET_B,
D ,
GATE_N ,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input RESET_B;
input D ;
input GATE_N ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLRTN_PP_BLACKBOX_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__CLKDLYINV5SD2_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__CLKDLYINV5SD2_FUNCTIONAL_PP_V
/**
* clkdlyinv5sd2: Clock Delay Inverter 5-stage 0.25um length inner
* stage gate.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__clkdlyinv5sd2 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y , A );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__CLKDLYINV5SD2_FUNCTIONAL_PP_V
|
/*
Line Size : 64byte
Way : 4Way Set Assicatiev
Tag : /2bit LRU Bit(VALID)/20bit Address
Purging : Write Through Algorithm
*/
//`include "processor.h"
`default_nettype none
module l1_data_cache_64entry_4way_line64b_bus_8b_damy(
/********************************
System
********************************/
input wire iCLOCK,
input wire inRESET,
//Remove
input wire iREMOVE,
/********************************
Search
********************************/
//Search Request
input wire iRD_REQ,
output wire oRD_BUSY,
input wire [31:0] iRD_ADDR, //Tag:22bit | Index:4bit(4Way*16Entry) | LineSize:6bit(64B)
//Search Output Result
output wire oRD_VALID,
output wire oRD_HIT,
input wire iRD_BUSY,
output wire [31:0] oRD_DATA,
output wire [13:0] oRD_MMU_FLAGS,
/********************************
Upload
********************************/
input wire iUP_REQ,
output wire oUP_BUSY,
input wire [1:0] iUP_ORDER,
input wire [3:0] iUP_MASK,
input wire [31:0] iUP_ADDR,
input wire [31:0] iUP_DATA,
/********************************
Write Request
********************************/
input wire iWR_REQ,
output wire oWR_BUSY,
input wire [31:0] iWR_ADDR, //Tag:22bit | Index:4bit(4Way*16Entry) | LineSize:6bit(64B)
input wire [511:0] iWR_DATA,
input wire [255:0] iWR_MMU_FLAGS
);
assign oRD_BUSY = 1'b0;
assign oRD_MMU_FLAGS = 14'h0;
reg b_req_valid;
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_req_valid <= 1'b0;
end
else if(iREMOVE)begin
b_req_valid <= 1'b0;
end
else begin
b_req_valid <= iRD_REQ;
end
end
assign oRD_VALID = b_req_valid;
assign oRD_HIT = 1'b0;
assign oRD_DATA = 32'h0;
assign oUP_BUSY = 1'b0;
assign oWR_BUSY = 1'b0;
endmodule
module l1_data_cache_64entry_4way_line64b_bus_8b(
/********************************
System
********************************/
input wire iCLOCK,
input wire inRESET,
//Remove
input wire iREMOVE,
/********************************
Search
********************************/
//Search Request
input wire iRD_REQ,
output wire oRD_BUSY,
input wire [31:0] iRD_ADDR, //Tag:22bit | Index:4bit(4Way*16Entry) | LineSize:6bit(64B)
//Search Output Result
output wire oRD_VALID,
output wire oRD_HIT,
input wire iRD_BUSY,
output wire [31:0] oRD_DATA,
output wire [13:0] oRD_MMU_FLAGS,
/********************************
Upload
********************************/
input wire iUP_REQ,
output wire oUP_BUSY,
input wire [1:0] iUP_ORDER,
input wire [3:0] iUP_MASK,
input wire [31:0] iUP_ADDR,
input wire [31:0] iUP_DATA,
/********************************
Write Request
********************************/
input wire iWR_REQ,
output wire oWR_BUSY,
input wire [31:0] iWR_ADDR, //Tag:22bit | Index:4bit(4Way*16Entry) | LineSize:6bit(64B)
input wire [511:0] iWR_DATA,
input wire [255:0] iWR_MMU_FLAGS
);
/**********************************************
Wire and Register
**********************************************/
//Lock Condition
wire this_read_lock;
wire this_write_lock;
//Output Buffer
reg b_rd_hit;
reg [1:0] b_rd_way;
reg [31:0] b_rd_addr;
//Cache Control
wire upload_need;
wire [1:0] upload_way;
wire [3:0] upload_pointer;
wire [3:0] read_pointer;
wire read_hit;
wire [1:0] read_way;
wire [3:0] write_pointer;
wire [1:0] write_way;
//Memory Data Block
wire [511:0] memory_way0_out_data;
wire [511:0] memory_way1_out_data;
wire [511:0] memory_way2_out_data;
wire [511:0] memory_way3_out_data;
wire memory_write_way0_condition;
wire memory_write_way1_condition;
wire memory_write_way2_condition;
wire memory_write_way3_condition;
wire [63:0] memory_write_byte_enable;
wire [511:0] memory_write_data;
//MMU Flag Block
wire [255:0] memory_mmuflag_way0_out_data;
wire [255:0] memory_mmuflag_way1_out_data;
wire [255:0] memory_mmuflag_way2_out_data;
wire [255:0] memory_mmuflag_way3_out_data;
wire [255:0] memory_mmuflag_write_data;
wire [31:0] memory_mmuflag_write_byte_enable;
//Generate
integer i;
//Tag:22bit | Index:4bit(4Way*16Entry) | LineSize:6bit(64B)
reg [23:0] tag0[0:15]; //LRU_Status:2bit | AddressTag:22bit
reg [23:0] tag1[0:15]; //LRU_Status:2bit | AddressTag:22bit
reg [23:0] tag2[0:15]; //LRU_Status:2bit | AddressTag:22bit
reg [23:0] tag3[0:15]; //LRU_Status:2bit | AddressTag:22bit
reg b_load_req_valid;
/**********************************************
Lock
**********************************************/
assign this_read_lock = iRD_BUSY;
assign this_write_lock = iUP_REQ;
/********************************************
LRU Control - Timer
********************************************/
wire lru_valid;
reg [15:0] b_lru_timer;
assign lru_valid = (b_lru_timer == 16'hFFFF)? 1'b1 : 1'b0;
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_lru_timer <= 16'h0;
end
else if(iREMOVE)begin
b_lru_timer <= 16'h0;
end
else begin
if(!this_read_lock)begin
b_lru_timer <= b_lru_timer + 16'h1;
end
end
end
/********************************************
Control
********************************************/
assign {upload_need, upload_way} = func_upload_check(iUP_ADDR[31:10], tag0[upload_pointer], tag1[upload_pointer], tag2[upload_pointer], tag3[upload_pointer]);
assign upload_pointer = iUP_ADDR[9:6];
assign read_pointer = iRD_ADDR[9:6];
assign {read_hit, read_way} = func_hit_check(iRD_ADDR[31:10], tag0[read_pointer], tag1[read_pointer], tag2[read_pointer], tag3[read_pointer]);
assign write_pointer = iWR_ADDR[9:6];
assign write_way = func_write_way_search(
iWR_ADDR[31:10],
func_get_address_tag(tag0[write_pointer]),
func_get_address_tag(tag1[write_pointer]),
func_get_address_tag(tag2[write_pointer]),
func_get_address_tag(tag3[write_pointer]),
func_get_status_tag(tag0[write_pointer]),
func_get_status_tag(tag1[write_pointer]),
func_get_status_tag(tag2[write_pointer]),
func_get_status_tag(tag3[write_pointer])
);
/********************************************
Data Memory Block
********************************************/
assign memory_write_way0_condition = (!this_write_lock && iWR_REQ && write_way == 2'h0) || (iUP_REQ && upload_need && upload_way == 2'h0);
assign memory_write_way1_condition = (!this_write_lock && iWR_REQ && write_way == 2'h1) || (iUP_REQ && upload_need && upload_way == 2'h1);
assign memory_write_way2_condition = (!this_write_lock && iWR_REQ && write_way == 2'h2) || (iUP_REQ && upload_need && upload_way == 2'h2);
assign memory_write_way3_condition = (!this_write_lock && iWR_REQ && write_way == 2'h3) || (iUP_REQ && upload_need && upload_way == 2'h3);
assign memory_write_byte_enable = (iUP_REQ)? func_up_mask_gen(iUP_ADDR[5:2], iUP_MASK) : {64{1'b1}};
function [63:0] func_up_mask_gen;
input [3:0] func_wordsel;
input [3:0] func_mask;
begin
func_up_mask_gen = {60'h0, func_mask} << (func_wordsel*4);
end
endfunction
assign memory_write_data = (iUP_REQ)? {16{iUP_DATA}} : iWR_DATA;
wire memory_mmuflag_write_way0_condition;
wire memory_mmuflag_write_way1_condition;
wire memory_mmuflag_write_way2_condition;
wire memory_mmuflag_write_way3_condition;
assign memory_mmuflag_write_way0_condition = (!this_write_lock && iWR_REQ && write_way == 2'h0) || (iUP_REQ && upload_need && upload_way == 2'h0);
assign memory_mmuflag_write_way1_condition = (!this_write_lock && iWR_REQ && write_way == 2'h1) || (iUP_REQ && upload_need && upload_way == 2'h1);
assign memory_mmuflag_write_way2_condition = (!this_write_lock && iWR_REQ && write_way == 2'h2) || (iUP_REQ && upload_need && upload_way == 2'h2);
assign memory_mmuflag_write_way3_condition = (!this_write_lock && iWR_REQ && write_way == 2'h3) || (iUP_REQ && upload_need && upload_way == 2'h3);
assign memory_mmuflag_write_byte_enable = (iUP_REQ)? {32{1'b0}} : {32{1'b1}};
assign memory_mmuflag_write_data = iWR_MMU_FLAGS;
/*---------------------------------------
Altera Quartus II MegaWizard
Name : Data RAM
Type : RAM
Port : Dual Port(1Read+1Write)
ReadPort : None Latch
Entry : 16
Data Bit : 512bit
Read Latch : none
Byte Enable : YES(64bit)
Read==Write : Dont care
---------------------------------------*/
/*
`ifdef MIST1032ISA_SIMULATION
damy_memory_16entry_512bit MEMORY_DAMY_BLOCK0(
.iCLOCK(iCLOCK),
.iBYTE_ENA(memory_write_byte_enable),
//Write
.iWR_ENA(memory_write_way0_condition),
.iWR_ADDR(write_pointer),
.iWR_DATA(memory_write_data),
//Read
.iRD_ADDR(read_pointer),
.oRD_DATA(memory_way0_out_data)
);
damy_memory_16entry_512bit MEMORY_DAMY_BLOCK1(
.iCLOCK(iCLOCK),
.iBYTE_ENA(memory_write_byte_enable),
//Write
.iWR_ENA(memory_write_way1_condition),
.iWR_ADDR(write_pointer),
.iWR_DATA(memory_write_data),
//Read
.iRD_ADDR(read_pointer),
.oRD_DATA(memory_way1_out_data)
);
damy_memory_16entry_512bit MEMORY_DAMY_BLOCK2(
.iCLOCK(iCLOCK),
.iBYTE_ENA(memory_write_byte_enable),
//Write
.iWR_ENA(memory_write_way2_condition),
.iWR_ADDR(write_pointer),
.iWR_DATA(memory_write_data),
//Read
.iRD_ADDR(read_pointer),
.oRD_DATA(memory_way2_out_data)
);
damy_memory_16entry_512bit MEMORY_DAMY_BLOCK3(
.iCLOCK(iCLOCK),
.iBYTE_ENA(memory_write_byte_enable),
//Write
.iWR_ENA(memory_write_way3_condition),
.iWR_ADDR(write_pointer),
.iWR_DATA(memory_write_data),
//Read
.iRD_ADDR(read_pointer),
.oRD_DATA(memory_way3_out_data)
);
*/
//`else
cache_ram_16entry_512bit MEMORY_BLOCK0(
.clock(iCLOCK),
.data(memory_write_data), //512bit
.rdaddress(read_pointer), //4bit
.wraddress(write_pointer), //4bit
.byteena_a(memory_write_byte_enable), //64bit
.wren(memory_write_way0_condition),
.q(memory_way0_out_data) //512bit
);
cache_ram_16entry_512bit MEMORY_BLOCK1(
.clock(iCLOCK),
.data(memory_write_data), //512bit
.rdaddress(read_pointer), //4bit
.wraddress(write_pointer), //4bit
.byteena_a(memory_write_byte_enable), //64bit
.wren(memory_write_way1_condition),
.q(memory_way1_out_data) //512bit
);
cache_ram_16entry_512bit MEMORY_BLOCK2(
.clock(iCLOCK),
.data(memory_write_data), //512bit
.rdaddress(read_pointer), //4bit
.wraddress(write_pointer), //4bit
.byteena_a(memory_write_byte_enable), //64bit
.wren(memory_write_way2_condition),
.q(memory_way2_out_data) //512bit
);
cache_ram_16entry_512bit MEMORY_BLOCK3(
.clock(iCLOCK),
.data(memory_write_data), //512bit
.rdaddress(read_pointer), //4bit
.wraddress(write_pointer), //4bit
.byteena_a(memory_write_byte_enable), //64bit
.wren(memory_write_way3_condition),
.q(memory_way3_out_data) //512bit
);
//`endif
/*---------------------------------------
Altera Quartus II MegaWizard
Name : MMU Flag RAM
Type : RAM
Port : Dual Port(1Read+1Write)
ReadPort : None Latch
Memory Word : 128W
Data Bit : 12bit
Read Latch : none
Byte Enable : YES(8bit)
Read==Write : Dont care
---------------------------------------*/
/*`ifdef MIST1032ISA_SIMULATION
damy_memory_16entry_256bit MEMORY_MMUFLAG_DAMY_BLOCK0(
.iCLOCK(iCLOCK),
.iBYTE_ENA(memory_mmuflag_write_byte_enable),
//Write
.iWR_ENA(memory_mmuflag_write_way0_condition),
.iWR_ADDR(write_pointer),
.iWR_DATA(memory_mmuflag_write_data),
//Read
.iRD_ADDR(read_pointer),
.oRD_DATA(memory_mmuflag_way0_out_data)
);
damy_memory_16entry_256bit MEMORY_MMUFLAG_DAMY_BLOCK1(
.iCLOCK(iCLOCK),
.iBYTE_ENA(memory_mmuflag_write_byte_enable),
//Write
.iWR_ENA(memory_mmuflag_write_way1_condition),
.iWR_ADDR(write_pointer),
.iWR_DATA(memory_mmuflag_write_data),
//Read
.iRD_ADDR(read_pointer),
.oRD_DATA(memory_mmuflag_way1_out_data)
);
damy_memory_16entry_256bit MEMORY_MMUFLAG_DAMY_BLOCK2(
.iCLOCK(iCLOCK),
.iBYTE_ENA(memory_mmuflag_write_byte_enable),
//Write
.iWR_ENA(memory_mmuflag_write_way2_condition),
.iWR_ADDR(write_pointer),
.iWR_DATA(memory_mmuflag_write_data),
//Read
.iRD_ADDR(read_pointer),
.oRD_DATA(memory_mmuflag_way2_out_data)
);
damy_memory_16entry_256bit MEMORY_MMUFLAG_DAMY_BLOCK3(
.iCLOCK(iCLOCK),
.iBYTE_ENA(memory_mmuflag_write_byte_enable),
//Write
.iWR_ENA(memory_mmuflag_write_way3_condition),
.iWR_ADDR(write_pointer),
.iWR_DATA(memory_mmuflag_write_data),
//Read
.iRD_ADDR(read_pointer),
.oRD_DATA(memory_mmuflag_way3_out_data)
);
`else*/
cache_ram_16entry_256bit MEMORY_MMUFLAG_BLOCK0(
.clock(iCLOCK),
.byteena_a(memory_mmuflag_write_byte_enable),
.data(memory_mmuflag_write_data), //256bit
.rdaddress(read_pointer), //4bit
.wraddress(write_pointer), //4bit
.wren(memory_mmuflag_write_way0_condition),
.q(memory_mmuflag_way0_out_data) //256bit
);
cache_ram_16entry_256bit MEMORY_MMUFLAG_BLOCK1(
.clock(iCLOCK),
.byteena_a(memory_mmuflag_write_byte_enable),
.data(memory_mmuflag_write_data), //256bit
.rdaddress(read_pointer), //4bit
.wraddress(write_pointer), //4bit
.wren(memory_mmuflag_write_way1_condition),
.q(memory_mmuflag_way1_out_data) //256bit
);
cache_ram_16entry_256bit MEMORY_MMUFLAG_BLOCK2(
.clock(iCLOCK),
.byteena_a(memory_mmuflag_write_byte_enable),
.data(memory_mmuflag_write_data), //256bit
.rdaddress(read_pointer), //4bit
.wraddress(write_pointer), //4bit
.wren(memory_mmuflag_write_way2_condition),
.q(memory_mmuflag_way2_out_data) //256bit
);
cache_ram_16entry_256bit MEMORY_MMUFLAG_BLOCK3(
.clock(iCLOCK),
.byteena_a(memory_mmuflag_write_byte_enable),
.data(memory_mmuflag_write_data), //256bit
.rdaddress(read_pointer), //4bit
.wraddress(write_pointer), //4bit
.wren(memory_mmuflag_write_way3_condition),
.q(memory_mmuflag_way3_out_data) //256bit
);
//`endif
/********************************************
Function
********************************************/
//Upload Check
function [2:0] func_upload_check; //[2]:Upload Need Flag | [1:0] Upload Way
input [21:0] func_request_addr;
input [23:0] func_way0;
input [23:0] func_way1;
input [23:0] func_way2;
input [23:0] func_way3;
begin
if(func_request_addr == func_way0[21:0] && func_way0[23:22] != 2'h0)begin
func_upload_check = {1'b1, 2'h0};
end
else if(func_request_addr == func_way1[21:0] && func_way0[23:22] != 2'h0)begin
func_upload_check = {1'b1, 2'h1};
end
else if(func_request_addr == func_way2[21:0] && func_way0[23:22] != 2'h0)begin
func_upload_check = {1'b1, 2'h2};
end
else if(func_request_addr == func_way3[21:0] && func_way0[23:22] != 2'h0)begin
func_upload_check = {1'b1, 2'h3};
end
else begin
func_upload_check = 3'h0;
end
end
endfunction
//Upload Byte Enable Generate
function [63:0] func_upload_enable_byte_gen;
input [5:0] func_addr;
input [1:0] func_order;
begin
case(func_order)
2'h0 : func_upload_enable_byte_gen = 64'h0000000000000001 << func_addr[5:0];
2'h1 : func_upload_enable_byte_gen = 64'h0000000000000003 << (func_addr[5:1]*2);
2'h2 : func_upload_enable_byte_gen = 64'h000000000000000F << (func_addr[5:2]*4);
default : func_upload_enable_byte_gen = 64'h0000000000000000;
endcase
end
endfunction
//Low Pryority Line Search
function [1:0] func_write_way_search;
input [21:0] write_addr;
input [21:0] way0_adder_tag;
input [21:0] way1_adder_tag;
input [21:0] way2_adder_tag;
input [21:0] way3_adder_tag;
input [1:0] way0_status;
input [1:0] way1_status;
input [1:0] way2_status;
input [1:0] way3_status;
begin
//LINE Update
if(write_addr == way0_adder_tag)begin
func_write_way_search = 2'h0;
end
else if(write_addr == way1_adder_tag)begin
func_write_way_search = 2'h1;
end
else if(write_addr == way2_adder_tag)begin
func_write_way_search = 2'h2;
end
else if(write_addr == way3_adder_tag)begin
func_write_way_search = 2'h3;
end
//New Write
else if(way0_status == 2'h0)
func_write_way_search = 2'h0;
else if(way1_status == 2'h0)
func_write_way_search = 2'h1;
else if(way2_status == 2'h0)
func_write_way_search = 2'h2;
else if(way3_status == 2'h0)
func_write_way_search = 2'h3;
else if(way0_status == 2'h1)
func_write_way_search = 2'h0;
else if(way1_status == 2'h1)
func_write_way_search = 2'h1;
else if(way2_status == 2'h1)
func_write_way_search = 2'h2;
else if(way3_status == 2'h1)
func_write_way_search = 2'h3;
else if(way0_status == 2'h2)
func_write_way_search = 2'h0;
else if(way1_status == 2'h2)
func_write_way_search = 2'h1;
else if(way2_status == 2'h2)
func_write_way_search = 2'h2;
else if(way3_status == 2'h2)
func_write_way_search = 2'h3;
else
func_write_way_search = 2'h3;
end
endfunction
function [2:0] func_hit_check; //[2]:Hit | [1:0] Hit Way
input [21:0] func_request_addr;
input [23:0] func_way0;
input [23:0] func_way1;
input [23:0] func_way2;
input [23:0] func_way3;
begin
if(func_request_addr == func_way0[21:0] && func_way0[23:22] != 2'h0)begin
func_hit_check = {1'b1, 2'h0};
end
else if(func_request_addr == func_way1[21:0] && func_way1[23:22] != 2'h0)begin
func_hit_check = {1'b1, 2'h1};
end
else if(func_request_addr == func_way2[21:0] && func_way2[23:22] != 2'h0)begin
func_hit_check = {1'b1, 2'h2};
end
else if(func_request_addr == func_way3[21:0] && func_way3[23:22] != 2'h0)begin
func_hit_check = {1'b1, 2'h3};
end
else begin
//No Hit
func_hit_check = {1'b0, 2'h0};
end
end
endfunction
//Pryority & Valid
function [1:0] func_get_status_tag;
input [23:0] func_tag;
begin
func_get_status_tag = func_tag[23:22];
end
endfunction
//Get Tag Address
function [21:0] func_get_address_tag;
input [23:0] func_tag;
begin
func_get_address_tag = func_tag[21:0];
end
endfunction
function [31:0] func_data_selector;
input [3:0] func_select;
input [511:0] func_data;
begin
case(func_select)
4'h0 : func_data_selector = func_data[31:0];
4'h1 : func_data_selector = func_data[63:32];
4'h2 : func_data_selector = func_data[95:64];
4'h3 : func_data_selector = func_data[127:96];
4'h4 : func_data_selector = func_data[159:128];
4'h5 : func_data_selector = func_data[191:160];
4'h6 : func_data_selector = func_data[223:192];
4'h7 : func_data_selector = func_data[255:224];
4'h8 : func_data_selector = func_data[287:256];
4'h9 : func_data_selector = func_data[319:288];
4'ha : func_data_selector = func_data[351:320];
4'hb : func_data_selector = func_data[383:352];
4'hc : func_data_selector = func_data[415:384];
4'hd : func_data_selector = func_data[447:416];
4'he : func_data_selector = func_data[479:448];
4'hf : func_data_selector = func_data[511:480];
endcase
end
endfunction
function [13:0] func_mmu_flags_selector;
input [3:0] func_select;
input [255:0] func_data;
begin
case(func_select)
4'h0 : func_mmu_flags_selector = func_data[13:0];
4'h1 : func_mmu_flags_selector = func_data[29:16];
4'h2 : func_mmu_flags_selector = func_data[45:32];
4'h3 : func_mmu_flags_selector = func_data[61:48];
4'h4 : func_mmu_flags_selector = func_data[77:64];
4'h5 : func_mmu_flags_selector = func_data[93:80];
4'h6 : func_mmu_flags_selector = func_data[109:96];
4'h7 : func_mmu_flags_selector = func_data[125:112];
4'h8 : func_mmu_flags_selector = func_data[141:128];
4'h9 : func_mmu_flags_selector = func_data[157:144];
4'ha : func_mmu_flags_selector = func_data[173:160];
4'hb : func_mmu_flags_selector = func_data[189:176];
4'hc : func_mmu_flags_selector = func_data[205:192];
4'hd : func_mmu_flags_selector = func_data[221:208];
4'he : func_mmu_flags_selector = func_data[237:224];
4'hf : func_mmu_flags_selector = func_data[253:240];
endcase
end
endfunction
function [23:0] func_lru_control;
input [23:0] func_tag;
begin
if(func_tag[23:22] != 2'h0 && func_tag[23:22] != 2'h1)begin
func_lru_control = {(func_tag[23:22] - 2'h1), func_tag[21:0]};
end
else begin
func_lru_control = func_tag;
end
end
endfunction
/********************************************
Tag Pryority & Tag Control
********************************************/
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
for(i = 0; i < 16; i = i + 1)begin
/*
if(`PROCESSOR_DATA_RESET_EN)begin
tag0[i] <= tag0[i] & 24'h000000; //Clear LRU_Status bit
tag1[i] <= tag1[i] & 24'h000000; //Clear LRU_Status bit
tag2[i] <= tag2[i] & 24'h000000; //Clear LRU_Status bit
tag3[i] <= tag3[i] & 24'h000000; //Clear LRU_Status bit
end
else begin
tag0[i] <= tag0[i] & 24'h3FFFFF; //Clear LRU_Status bit
tag1[i] <= tag1[i] & 24'h3FFFFF; //Clear LRU_Status bit
tag2[i] <= tag2[i] & 24'h3FFFFF; //Clear LRU_Status bit
tag3[i] <= tag3[i] & 24'h3FFFFF; //Clear LRU_Status bit
end
*/
tag0[i] <= tag0[i] & 24'h000000; //Clear LRU_Status bit
tag1[i] <= tag1[i] & 24'h000000; //Clear LRU_Status bit
tag2[i] <= tag2[i] & 24'h000000; //Clear LRU_Status bit
tag3[i] <= tag3[i] & 24'h000000; //Clear LRU_Status bit
end
b_load_req_valid <= 1'b0;
end
else if(iREMOVE)begin
for(i = 0; i < 16; i = i + 1)begin
/*
if(`PROCESSOR_DATA_RESET_EN)begin
tag0[i] <= tag0[i] & 24'h000000; //Clear LRU_Status bit
tag1[i] <= tag1[i] & 24'h000000; //Clear LRU_Status bit
tag2[i] <= tag2[i] & 24'h000000; //Clear LRU_Status bit
tag3[i] <= tag3[i] & 24'h000000; //Clear LRU_Status bit
end
else begin
tag0[i] <= tag0[i] & 24'h3FFFFF; //Clear LRU_Status bit
tag1[i] <= tag1[i] & 24'h3FFFFF; //Clear LRU_Status bit
tag2[i] <= tag2[i] & 24'h3FFFFF; //Clear LRU_Status bit
tag3[i] <= tag3[i] & 24'h3FFFFF; //Clear LRU_Status bit
end
*/
tag0[i] <= tag0[i] & 24'h000000; //Clear LRU_Status bit
tag1[i] <= tag1[i] & 24'h000000; //Clear LRU_Status bit
tag2[i] <= tag2[i] & 24'h000000; //Clear LRU_Status bit
tag3[i] <= tag3[i] & 24'h000000; //Clear LRU_Status bit
end
b_load_req_valid <= 1'b0;
end
else begin
//Request Valid
if(!this_read_lock)begin
b_load_req_valid <= iRD_REQ;
end
//Upload
if(iUP_REQ)begin
if(upload_need)begin
case(upload_way)
2'h0: tag0[write_pointer] <= {((func_get_status_tag(tag0[upload_pointer]) != 2'b11)? func_get_status_tag(tag0[upload_pointer]) + 2'h1 : func_get_status_tag(tag0[upload_pointer])), func_get_address_tag(tag0[upload_pointer])};
2'h1: tag1[write_pointer] <= {((func_get_status_tag(tag1[upload_pointer]) != 2'b11)? func_get_status_tag(tag1[upload_pointer]) + 2'h1 : func_get_status_tag(tag1[upload_pointer])), func_get_address_tag(tag1[upload_pointer])};
2'h2: tag2[write_pointer] <= {((func_get_status_tag(tag2[upload_pointer]) != 2'b11)? func_get_status_tag(tag2[upload_pointer]) + 2'h1 : func_get_status_tag(tag2[upload_pointer])), func_get_address_tag(tag2[upload_pointer])};
2'h3: tag3[write_pointer] <= {((func_get_status_tag(tag3[upload_pointer]) != 2'b11)? func_get_status_tag(tag3[upload_pointer]) + 2'h1 : func_get_status_tag(tag3[upload_pointer])), func_get_address_tag(tag3[upload_pointer])};
endcase
end
end
//Write
else if(iWR_REQ)begin
case(write_way)
2'h0: tag0[write_pointer] <= {2'b11, iWR_ADDR[31:10]};
2'h1: tag1[write_pointer] <= {2'b11, iWR_ADDR[31:10]};
2'h2: tag2[write_pointer] <= {2'b11, iWR_ADDR[31:10]};
2'h3: tag3[write_pointer] <= {2'b11, iWR_ADDR[31:10]};
endcase
end
else begin
//Read & LRU Controal
if(!this_read_lock)begin
if(iRD_REQ && read_hit && lru_valid)begin
for(i = 0; i < 16; i = i + 1)begin : READ_AND_RLU
//TAG0
if(read_pointer == i[3:0] && read_way == 2'h0)begin
tag0[read_pointer] <= {2'b11, func_get_address_tag(tag0[read_pointer])};
end
else begin
if(func_get_status_tag(tag0[i[3:0]]) != 2'h0 && func_get_status_tag(tag0[i[3:0]]) != 2'h1)begin
tag0[i[3:0]] <= {(func_get_status_tag(tag0[i[3:0]]) - 2'h1), func_get_address_tag(tag0[i[3:0]])};
end
end
//TAG1
if(read_pointer == i[3:0] && read_way == 2'h1)begin
tag1[read_pointer] <= {2'b11, func_get_address_tag(tag1[read_pointer])};
end
else begin
if(func_get_status_tag(tag1[i[3:0]]) != 2'h0 && func_get_status_tag(tag1[i[3:0]]) != 2'h1)begin
tag1[i[3:0]] <= {(func_get_status_tag(tag1[i[3:0]]) - 2'h1), func_get_address_tag(tag1[i[3:0]])};
end
end
//TAG2
if(read_pointer == i[3:0] && read_way == 2'h2)begin
tag2[read_pointer] <= {2'b11, func_get_address_tag(tag2[read_pointer])};
end
else begin
if(func_get_status_tag(tag2[i[3:0]]) != 2'h0 && func_get_status_tag(tag2[i[3:0]]) != 2'h1)begin
tag2[i[3:0]] <= {(func_get_status_tag(tag2[i[3:0]]) - 2'h1), func_get_address_tag(tag2[i[3:0]])};
end
end
//TAG3
if(read_pointer == i[3:0] && read_way == 2'h3)begin
tag3[read_pointer] <= {2'b11, func_get_address_tag(tag3[read_pointer])};
end
else begin
if(func_get_status_tag(tag3[i[3:0]]) != 2'h0 && func_get_status_tag(tag3[i[3:0]]) != 2'h1)begin
tag3[i[3:0]] <= {(func_get_status_tag(tag3[i[3:0]]) - 2'h1), func_get_address_tag(tag3[i[3:0]])};
end
end
end
end
//Read Only
else if(iRD_REQ && read_hit)begin
case(read_way)//synthesis parallel_case full_case
2'h0 :
begin
if(func_get_status_tag(tag0[read_pointer]) != 2'b11)begin
tag0[read_pointer] <= {2'b11/*(func_get_status_tag(tag0[read_pointer]) + 2'h1)*/, func_get_address_tag(tag0[read_pointer])};
end
end
2'h1 :
begin
if(func_get_status_tag(tag1[read_pointer]) != 2'b11)begin
tag1[read_pointer] <= {2'b11, func_get_address_tag(tag1[read_pointer])};
end
end
2'h2 :
begin
if(func_get_status_tag(tag2[read_pointer]) != 2'b11)begin
tag2[read_pointer] <= {2'b11, func_get_address_tag(tag2[read_pointer])};
end
end
2'h3 :
begin
if(func_get_status_tag(tag3[read_pointer]) != 2'b11)begin
tag3[read_pointer] <= {2'b11, func_get_address_tag(tag3[read_pointer])};
end
end
endcase
end
//LRU Controal
else if(lru_valid)begin
for(i = 0; i < 16; i = i + 1)begin
tag0[i] <= func_lru_control(tag0[i]);
tag1[i] <= func_lru_control(tag1[i]);
tag2[i] <= func_lru_control(tag2[i]);
tag3[i] <= func_lru_control(tag3[i]);
end
end
end //End !Lock
end
end
end //always
/********************************************
Output Buffer
********************************************/
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_rd_hit <= 1'h0;
b_rd_way <= 2'h0;
b_rd_addr <= 32'h0;
end
else begin
if(!this_read_lock)begin
b_rd_hit <= read_hit;
b_rd_way <= read_way;
b_rd_addr <= iRD_ADDR;
end
end
end
/*****************************************************
Output Assign
*****************************************************/
assign oRD_BUSY = iRD_BUSY || (iRD_REQ && iWR_REQ && iRD_ADDR == iWR_ADDR);
assign oRD_VALID = b_load_req_valid && !this_read_lock;
assign oRD_HIT = b_load_req_valid && !this_read_lock && b_rd_hit;
assign oRD_DATA = (b_load_req_valid && !this_read_lock && b_rd_hit)? (
(b_rd_way == 2'h0)? func_data_selector(b_rd_addr[5:2], memory_way0_out_data) : (
(b_rd_way == 2'h1)? func_data_selector(b_rd_addr[5:2], memory_way1_out_data) : (
(b_rd_way == 2'h2)? func_data_selector(b_rd_addr[5:2], memory_way2_out_data) : func_data_selector(b_rd_addr[5:2], memory_way3_out_data)
)
)
) : 64'h0;
assign oRD_MMU_FLAGS = (b_load_req_valid && !this_read_lock && b_rd_hit)? (
(b_rd_way == 2'h0)? func_mmu_flags_selector(b_rd_addr[5:2], memory_mmuflag_way0_out_data) : (
(b_rd_way == 2'h1)? func_mmu_flags_selector(b_rd_addr[5:2], memory_mmuflag_way1_out_data) : (
(b_rd_way == 2'h2)? func_mmu_flags_selector(b_rd_addr[5:2], memory_mmuflag_way2_out_data) : func_mmu_flags_selector(b_rd_addr[5:2], memory_mmuflag_way3_out_data)
)
)
) : 14'h0;
assign oWR_BUSY = this_write_lock;
assign oUP_BUSY = iWR_REQ;
endmodule
`default_nettype wire
|
/* This example is an FSM that interacts with the lcd_control.v module.
It first sends the string "18545" to the LCD module
It then waits for the nextString input to be asserted
It then sends the string "ECE" to the LCD module
It then waits forever.
*/
module testFSM(clkFSM,
resetFSM,
initDone,
writeDone,
nextString,
data,
writeStart);
input clkFSM;
input resetFSM;
input initDone;
input writeDone;
input nextString;
output [7:0] data;
output writeStart;
reg [7:0] data;
reg writeStart;
reg [5:0] state,next_state;
`define idle 6'b000000
`define data1 6'b000001
`define wait1 6'b100001
`define data2 6'b000010
`define wait2 6'b100010
`define data3 6'b000011
`define wait3 6'b100011
`define data4 6'b000100
`define wait4 6'b100100
`define data5 6'b000101
`define wait5 6'b100101
`define data6 6'b000110
`define wait6 6'b100110
`define data7 6'b000111
`define wait7 6'b100111
`define data8 6'b001000
`define wait8 6'b101000
`define waitClear 6'b011111
`define finish 6'b111111
/* first write 18545, then write ECE to LCD */
always @ (clkFSM or state or initDone or writeDone or nextString)
begin
next_state <= `idle;
data = 8'b00000000;
writeStart = 'b0;
case(state)
`idle :
begin
if(initDone == 1'b1)
next_state <= `data1;
else
next_state <= `idle;
end
`data1 :
begin
data = 8'b00110001; //1
writeStart = 1'b1;
next_state <= `wait1;
end
`wait1 :
begin
data = 8'b00110001;
if(writeDone == 1'b1)
next_state <= `data2;
else
next_state <= `wait1;
end
`data2 :
begin
data = 8'b00111000; //8
writeStart = 1'b1;
next_state <= `wait2;
end
`wait2 :
begin
data = 8'b00111000;
if(writeDone == 1'b1)
next_state <= `data3;
else
next_state <= `wait2;
end
`data3 :
begin
data = 8'b00110101; //5
writeStart = 1'b1;
next_state <= `wait3;
end
`wait3 :
begin
data = 8'b00110101;
if(writeDone == 1'b1)
next_state <= `data4;
else
next_state <= `wait3;
end
`data4 :
begin
data = 8'b00110100; //4
writeStart = 1'b1;
next_state <= `wait4;
end
`wait4 :
begin
data = 8'b00110100;
if(writeDone == 1'b1)
next_state <= `data5;
else
next_state <= `wait4;
end
`data5 :
begin
data = 8'b00110101; //5
writeStart = 1'b1;
next_state <= `wait5;
end
`wait5 :
begin
data = 8'b00110101;
if(writeDone == 1'b1)
next_state <= `waitClear;
else
next_state <= `wait5;
end
`waitClear :
begin
if(nextString == 'b1)
begin
next_state <= `data6;
end
else
begin
next_state <= `waitClear;
end
end
`data6 :
begin
data = 8'b01000101; //E
writeStart = 1'b1;
next_state <= `wait6;
end
`wait6 :
begin
data = 8'b01000101;
if(writeDone == 1'b1)
next_state <= `data7;
else
next_state <= `wait6;
end
`data7 :
begin
data = 8'b01000011; //C
writeStart = 1'b1;
next_state <= `wait7;
end
`wait7 :
begin
data = 8'b01000011;
if(writeDone == 1'b1)
next_state <= `data8;
else
next_state <= `wait7;
end
`data8 :
begin
data = 8'b01000101; //E
writeStart = 1'b1;
next_state <= `wait8;
end
`wait8 :
begin
data = 8'b01000101;
if(writeDone == 1'b1)
next_state <= `finish;
else
next_state <= `wait8;
end
`finish :
begin
next_state <= `finish;
end
endcase
end
//registers state variables
always @ (posedge clkFSM)
begin
if (resetFSM)
begin
state <= `idle;
end
else
begin
state <= next_state;
end
end // always
endmodule
|
//-----------------------------------------------------------------------------
// File : test_setup.v
// Creation date : 28.11.2017
// Creation time : 16:08:33
// Description : Test arrangement for verifying wishbone-to-CPU bridge.
// Created by : TermosPullo
// Tool : Kactus2 3.4.1184 32-bit
// Plugin : Verilog generator 2.1
// This file was generated based on IP-XACT component tut.fi:communication.bridge.test:wb_cpu.setup:1.0
// whose XML file is D:/kactus2Repos/ipxactexamplelib/tut.fi/communication.bridge.test/wb_cpu.setup/1.0/wb_cpu.setup.1.0.xml
//-----------------------------------------------------------------------------
module test_setup();
// wb_master_cpu_slave_0_wb_master_to_wb_cpu.bench_0_wb_slave wires:
wire wb_master_cpu_slave_0_wb_master_to_wb_cpu_bench_0_wb_slaveack;
wire [15:0] wb_master_cpu_slave_0_wb_master_to_wb_cpu_bench_0_wb_slaveadr;
wire wb_master_cpu_slave_0_wb_master_to_wb_cpu_bench_0_wb_slavecyc;
wire [31:0] wb_master_cpu_slave_0_wb_master_to_wb_cpu_bench_0_wb_slavedat_ms;
wire [31:0] wb_master_cpu_slave_0_wb_master_to_wb_cpu_bench_0_wb_slavedat_sm;
wire wb_master_cpu_slave_0_wb_master_to_wb_cpu_bench_0_wb_slaveerr;
wire wb_master_cpu_slave_0_wb_master_to_wb_cpu_bench_0_wb_slavestb;
wire wb_master_cpu_slave_0_wb_master_to_wb_cpu_bench_0_wb_slavewe;
// wb_master_cpu_slave_0_wb_system_to_clock_generator_0_wb_system wires:
wire wb_master_cpu_slave_0_wb_system_to_clock_generator_0_wb_systemclk;
wire wb_master_cpu_slave_0_wb_system_to_clock_generator_0_wb_systemrst;
// wb_master_cpu_slave_0_contoller_to_wb_cpu.bench_0_memory_interface wires:
wire [15:0] wb_master_cpu_slave_0_contoller_to_wb_cpu_bench_0_memory_interfaceaddress;
wire [31:0] wb_master_cpu_slave_0_contoller_to_wb_cpu_bench_0_memory_interfacedata_ms;
wire [31:0] wb_master_cpu_slave_0_contoller_to_wb_cpu_bench_0_memory_interfacedata_sm;
wire wb_master_cpu_slave_0_contoller_to_wb_cpu_bench_0_memory_interfacemaster_rdy;
wire wb_master_cpu_slave_0_contoller_to_wb_cpu_bench_0_memory_interfaceslave_rdy;
wire wb_master_cpu_slave_0_contoller_to_wb_cpu_bench_0_memory_interfacewe;
// clock_generator_0 port wires:
wire clock_generator_0_clk_o;
wire clock_generator_0_rst_o;
// wb_cpu.bench_0 port wires:
wire wb_cpu_bench_0_clk_i;
wire [15:0] wb_cpu_bench_0_mem_address_o;
wire [31:0] wb_cpu_bench_0_mem_data_i;
wire [31:0] wb_cpu_bench_0_mem_data_o;
wire wb_cpu_bench_0_mem_master_rdy;
wire wb_cpu_bench_0_mem_slave_rdy;
wire wb_cpu_bench_0_mem_we_o;
wire wb_cpu_bench_0_rst_i;
wire wb_cpu_bench_0_wb_ack_o;
wire [15:0] wb_cpu_bench_0_wb_adr_i;
wire wb_cpu_bench_0_wb_cyc_i;
wire [31:0] wb_cpu_bench_0_wb_dat_i;
wire [31:0] wb_cpu_bench_0_wb_dat_o;
wire wb_cpu_bench_0_wb_err_o;
wire wb_cpu_bench_0_wb_stb_i;
wire wb_cpu_bench_0_wb_we_i;
// wb_master_cpu_slave_0 port wires:
wire wb_master_cpu_slave_0_clk_i;
wire [15:0] wb_master_cpu_slave_0_mem_address_in;
wire [31:0] wb_master_cpu_slave_0_mem_data_in;
wire [31:0] wb_master_cpu_slave_0_mem_data_out;
wire wb_master_cpu_slave_0_mem_master_rdy;
wire wb_master_cpu_slave_0_mem_slave_rdy;
wire wb_master_cpu_slave_0_mem_we_in;
wire wb_master_cpu_slave_0_rst_i;
wire wb_master_cpu_slave_0_wb_ack_i;
wire [15:0] wb_master_cpu_slave_0_wb_adr_o;
wire wb_master_cpu_slave_0_wb_cyc_o;
wire [31:0] wb_master_cpu_slave_0_wb_dat_i;
wire [31:0] wb_master_cpu_slave_0_wb_dat_o;
wire wb_master_cpu_slave_0_wb_err_i;
wire wb_master_cpu_slave_0_wb_stb_o;
wire wb_master_cpu_slave_0_wb_we_o;
// clock_generator_0 assignments:
assign wb_master_cpu_slave_0_wb_system_to_clock_generator_0_wb_systemclk = clock_generator_0_clk_o;
assign wb_master_cpu_slave_0_wb_system_to_clock_generator_0_wb_systemrst = clock_generator_0_rst_o;
// wb_cpu.bench_0 assignments:
assign wb_cpu_bench_0_clk_i = wb_master_cpu_slave_0_wb_system_to_clock_generator_0_wb_systemclk;
assign wb_master_cpu_slave_0_contoller_to_wb_cpu_bench_0_memory_interfaceaddress[15:0] = wb_cpu_bench_0_mem_address_o[15:0];
assign wb_cpu_bench_0_mem_data_i[31:0] = wb_master_cpu_slave_0_contoller_to_wb_cpu_bench_0_memory_interfacedata_sm[31:0];
assign wb_master_cpu_slave_0_contoller_to_wb_cpu_bench_0_memory_interfacedata_ms[31:0] = wb_cpu_bench_0_mem_data_o[31:0];
assign wb_master_cpu_slave_0_contoller_to_wb_cpu_bench_0_memory_interfacemaster_rdy = wb_cpu_bench_0_mem_master_rdy;
assign wb_cpu_bench_0_mem_slave_rdy = wb_master_cpu_slave_0_contoller_to_wb_cpu_bench_0_memory_interfaceslave_rdy;
assign wb_master_cpu_slave_0_contoller_to_wb_cpu_bench_0_memory_interfacewe = wb_cpu_bench_0_mem_we_o;
assign wb_cpu_bench_0_rst_i = wb_master_cpu_slave_0_wb_system_to_clock_generator_0_wb_systemrst;
assign wb_master_cpu_slave_0_wb_master_to_wb_cpu_bench_0_wb_slaveack = wb_cpu_bench_0_wb_ack_o;
assign wb_cpu_bench_0_wb_adr_i[15:0] = wb_master_cpu_slave_0_wb_master_to_wb_cpu_bench_0_wb_slaveadr[15:0];
assign wb_cpu_bench_0_wb_cyc_i = wb_master_cpu_slave_0_wb_master_to_wb_cpu_bench_0_wb_slavecyc;
assign wb_cpu_bench_0_wb_dat_i[31:0] = wb_master_cpu_slave_0_wb_master_to_wb_cpu_bench_0_wb_slavedat_ms[31:0];
assign wb_master_cpu_slave_0_wb_master_to_wb_cpu_bench_0_wb_slavedat_sm[31:0] = wb_cpu_bench_0_wb_dat_o[31:0];
assign wb_master_cpu_slave_0_wb_master_to_wb_cpu_bench_0_wb_slaveerr = wb_cpu_bench_0_wb_err_o;
assign wb_cpu_bench_0_wb_stb_i = wb_master_cpu_slave_0_wb_master_to_wb_cpu_bench_0_wb_slavestb;
assign wb_cpu_bench_0_wb_we_i = wb_master_cpu_slave_0_wb_master_to_wb_cpu_bench_0_wb_slavewe;
// wb_master_cpu_slave_0 assignments:
assign wb_master_cpu_slave_0_clk_i = wb_master_cpu_slave_0_wb_system_to_clock_generator_0_wb_systemclk;
assign wb_master_cpu_slave_0_mem_address_in[15:0] = wb_master_cpu_slave_0_contoller_to_wb_cpu_bench_0_memory_interfaceaddress[15:0];
assign wb_master_cpu_slave_0_mem_data_in[31:0] = wb_master_cpu_slave_0_contoller_to_wb_cpu_bench_0_memory_interfacedata_ms[31:0];
assign wb_master_cpu_slave_0_contoller_to_wb_cpu_bench_0_memory_interfacedata_sm[31:0] = wb_master_cpu_slave_0_mem_data_out[31:0];
assign wb_master_cpu_slave_0_mem_master_rdy = wb_master_cpu_slave_0_contoller_to_wb_cpu_bench_0_memory_interfacemaster_rdy;
assign wb_master_cpu_slave_0_contoller_to_wb_cpu_bench_0_memory_interfaceslave_rdy = wb_master_cpu_slave_0_mem_slave_rdy;
assign wb_master_cpu_slave_0_mem_we_in = wb_master_cpu_slave_0_contoller_to_wb_cpu_bench_0_memory_interfacewe;
assign wb_master_cpu_slave_0_rst_i = wb_master_cpu_slave_0_wb_system_to_clock_generator_0_wb_systemrst;
assign wb_master_cpu_slave_0_wb_ack_i = wb_master_cpu_slave_0_wb_master_to_wb_cpu_bench_0_wb_slaveack;
assign wb_master_cpu_slave_0_wb_master_to_wb_cpu_bench_0_wb_slaveadr[15:0] = wb_master_cpu_slave_0_wb_adr_o[15:0];
assign wb_master_cpu_slave_0_wb_master_to_wb_cpu_bench_0_wb_slavecyc = wb_master_cpu_slave_0_wb_cyc_o;
assign wb_master_cpu_slave_0_wb_dat_i[31:0] = wb_master_cpu_slave_0_wb_master_to_wb_cpu_bench_0_wb_slavedat_sm[31:0];
assign wb_master_cpu_slave_0_wb_master_to_wb_cpu_bench_0_wb_slavedat_ms[31:0] = wb_master_cpu_slave_0_wb_dat_o[31:0];
assign wb_master_cpu_slave_0_wb_err_i = wb_master_cpu_slave_0_wb_master_to_wb_cpu_bench_0_wb_slaveerr;
assign wb_master_cpu_slave_0_wb_master_to_wb_cpu_bench_0_wb_slavestb = wb_master_cpu_slave_0_wb_stb_o;
assign wb_master_cpu_slave_0_wb_master_to_wb_cpu_bench_0_wb_slavewe = wb_master_cpu_slave_0_wb_we_o;
// IP-XACT VLNV: tut.fi:other.test:clock_generator:1.1
clock_generator clock_generator_0(
// Interface: wb_system
.clk_o (clock_generator_0_clk_o),
.rst_o (clock_generator_0_rst_o));
// IP-XACT VLNV: tut.fi:communication.bridge.test:wb_cpu.bench:1.0
wb_slave_mem_master #(
.ADDR_WIDTH (16),
.DATA_WIDTH (32),
.DATA_COUNT (8),
.BASE_ADDRESS (3840))
wb_cpu_bench_0(
// Interface: memory_interface
.mem_data_i (wb_cpu_bench_0_mem_data_i),
.mem_slave_rdy (wb_cpu_bench_0_mem_slave_rdy),
.mem_address_o (wb_cpu_bench_0_mem_address_o),
.mem_data_o (wb_cpu_bench_0_mem_data_o),
.mem_master_rdy (wb_cpu_bench_0_mem_master_rdy),
.mem_we_o (wb_cpu_bench_0_mem_we_o),
// Interface: wb_slave
.wb_adr_i (wb_cpu_bench_0_wb_adr_i),
.wb_cyc_i (wb_cpu_bench_0_wb_cyc_i),
.wb_dat_i (wb_cpu_bench_0_wb_dat_i),
.wb_stb_i (wb_cpu_bench_0_wb_stb_i),
.wb_we_i (wb_cpu_bench_0_wb_we_i),
.wb_ack_o (wb_cpu_bench_0_wb_ack_o),
.wb_dat_o (wb_cpu_bench_0_wb_dat_o),
.wb_err_o (wb_cpu_bench_0_wb_err_o),
// Interface: wb_system
.clk_i (wb_cpu_bench_0_clk_i),
.rst_i (wb_cpu_bench_0_rst_i));
// IP-XACT VLNV: tut.fi:communication.bridge:wb_master_cpu_slave:1.0
wb_master #(
.ADDR_WIDTH (16),
.DATA_WIDTH (32),
.BASE_ADDRESS (3840),
.RANGE (512))
wb_master_cpu_slave_0(
// Interface: contoller
.mem_address_in (wb_master_cpu_slave_0_mem_address_in),
.mem_data_in (wb_master_cpu_slave_0_mem_data_in),
.mem_master_rdy (wb_master_cpu_slave_0_mem_master_rdy),
.mem_we_in (wb_master_cpu_slave_0_mem_we_in),
.mem_data_out (wb_master_cpu_slave_0_mem_data_out),
.mem_slave_rdy (wb_master_cpu_slave_0_mem_slave_rdy),
// Interface: wb_master
.wb_ack_i (wb_master_cpu_slave_0_wb_ack_i),
.wb_dat_i (wb_master_cpu_slave_0_wb_dat_i),
.wb_err_i (wb_master_cpu_slave_0_wb_err_i),
.wb_adr_o (wb_master_cpu_slave_0_wb_adr_o),
.wb_cyc_o (wb_master_cpu_slave_0_wb_cyc_o),
.wb_dat_o (wb_master_cpu_slave_0_wb_dat_o),
.wb_stb_o (wb_master_cpu_slave_0_wb_stb_o),
.wb_we_o (wb_master_cpu_slave_0_wb_we_o),
// Interface: wb_system
.clk_i (wb_master_cpu_slave_0_clk_i),
.rst_i (wb_master_cpu_slave_0_rst_i));
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__OR2B_FUNCTIONAL_V
`define SKY130_FD_SC_MS__OR2B_FUNCTIONAL_V
/**
* or2b: 2-input OR, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__or2b (
X ,
A ,
B_N
);
// Module ports
output X ;
input A ;
input B_N;
// Local signals
wire not0_out ;
wire or0_out_X;
// Name Output Other arguments
not not0 (not0_out , B_N );
or or0 (or0_out_X, not0_out, A );
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__OR2B_FUNCTIONAL_V
|
///////////////////////////////////////////////////////////////////////////////
//
// Project: Aurora Module Generator version 2.8
//
// Date: $Date: 2007/09/28 12:50:35 $
// Tag: $Name: i+HEAD+134158 $
// File: $RCSfile: gtp_wrapper.ejava,v $
// Rev: $Revision: 1.2 $
//
// Company: Xilinx
//
// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR
// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
// APPLICATION OR STANDARD, XILINX IS MAKING NO
// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
// REQUIRE FOR YOUR IMPLEMENTATION. XILINX
// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
// PURPOSE.
//
// (c) Copyright 2004 Xilinx, Inc.
// All rights reserved.
//
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version : 7.1i
// \ \ Application :
// / / Filename : GTP_WRAPPER.v
// /___/ /\ Timestamp : 02/08/2005 09:12:43
// \ \ / \
// \___\/\___\
//
//Command:
//Design Name: GTP_WRAPPER
//
// Module GTP_WRAPPER
// Generated by Xilinx Architecture Wizard
// Written for synthesis tool: XST
`timescale 1ns / 1ps
module aurora_201_GTP_WRAPPER #
(
// Simulation attributes
parameter SIM_GTPRESET_SPEEDUP= 0, // Set to 1 to speed up sim reset
parameter SIM_PLL_PERDIV2 = 9'h14d, // Set to the VCO Unit Interval time
// Channel bond MASTER/SLAVE connection
parameter CHAN_BOND_MODE_0 = "OFF",
parameter CHAN_BOND_MODE_1 = "OFF",
// Refclk attributes
parameter CLKINDC_B = "TRUE"
)
(
//---------------------- Loopback and Powerdown Ports ----------------------
LOOPBACK_IN,
//--------------------- Receive Ports - 8b10b Decoder ----------------------
RXCHARISCOMMA_OUT,
RXCHARISK_OUT,
RXDISPERR_OUT,
RXNOTINTABLE_OUT,
//----------------- Receive Ports - Channel Bonding Ports -----------------
ENCHANSYNC_IN,
CHBONDDONE_OUT,
//----------------- Receive Ports - Clock Correction Ports -----------------
RXBUFERR_OUT,
//------------- Receive Ports - Comma Detection and Alignment --------------
RXREALIGN_OUT,
ENMCOMMAALIGN_IN,
ENPCOMMAALIGN_IN,
//----------------- Receive Ports - RX Data Path interface -----------------
RXDATA_OUT,
RXRECCLK1_OUT,
RXRECCLK2_OUT,
RXRESET_IN,
RXUSRCLK_IN,
RXUSRCLK2_IN,
//----- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
RX1N_IN,
RX1P_IN,
//--------------- Receive Ports - RX Polarity Control Ports ----------------
RXPOLARITY_IN,
//------------------- Shared Ports - Tile and PLL Ports --------------------
REFCLK,
GTPRESET_IN,
PLLLKDET_OUT,
POWERDOWN_IN,
//-------------- Transmit Ports - 8b10b Encoder Control Ports --------------
TXCHARISK_IN,
//---------------- Transmit Ports - TX Data Path interface -----------------
TXDATA_IN,
TXOUTCLK1_OUT,
TXOUTCLK2_OUT,
TXRESET_IN,
TXUSRCLK_IN,
TXUSRCLK2_IN,
TXBUFERR_OUT,
//------------- Transmit Ports - TX Driver and OOB signalling --------------
TX1N_OUT,
TX1P_OUT
);
//***************************** Port Declarations *****************************
//---------------------- Loopback and Powerdown Ports ----------------------
input [2:0] LOOPBACK_IN;
//--------------------- Receive Ports - 8b10b Decoder ----------------------
output [1:0] RXCHARISCOMMA_OUT;
output [1:0] RXCHARISK_OUT;
output [1:0] RXDISPERR_OUT;
output [1:0] RXNOTINTABLE_OUT;
//----------------- Receive Ports - Channel Bonding Ports -----------------
input ENCHANSYNC_IN;
output CHBONDDONE_OUT;
//----------------- Receive Ports - Clock Correction Ports -----------------
output RXBUFERR_OUT;
//------------- Receive Ports - Comma Detection and Alignment --------------
output RXREALIGN_OUT;
input ENMCOMMAALIGN_IN;
input ENPCOMMAALIGN_IN;
//----------------- Receive Ports - RX Data Path interface -----------------
output [15:0] RXDATA_OUT;
output RXRECCLK1_OUT;
output RXRECCLK2_OUT;
input RXRESET_IN;
input RXUSRCLK_IN;
input RXUSRCLK2_IN;
//----- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
input RX1N_IN;
input RX1P_IN;
//--------------- Receive Ports - RX Polarity Control Ports ----------------
input RXPOLARITY_IN;
//------------------- Shared Ports - Tile and PLL Ports --------------------
input REFCLK;
input GTPRESET_IN;
output PLLLKDET_OUT;
input POWERDOWN_IN;
//-------------- Transmit Ports - 8b10b Encoder Control Ports --------------
input [1:0] TXCHARISK_IN;
//---------------- Transmit Ports - TX Data Path interface -----------------
input [15:0] TXDATA_IN;
output TXOUTCLK1_OUT;
output TXOUTCLK2_OUT;
input TXRESET_IN;
output TXBUFERR_OUT;
input TXUSRCLK_IN;
input TXUSRCLK2_IN;
//------------- Transmit Ports - TX Driver and OOB signalling --------------
output TX1N_OUT;
output TX1P_OUT;
//***************************** Wire Declarations *****************************
// Ground and VCC signals
wire tied_to_ground_i;
wire [63:0] tied_to_ground_vec_i;
wire tied_to_vcc_i;
wire [63:0] tied_to_vcc_vec_i;
// floating input port connection signals
wire [1:0] open_rxbufstatus_i;
wire open_txbufstatus_i;
// wire to output lock signal
wire plllkdet_i;
// Electrical idle reset logic signals
wire rxenelecidleresetb_i;
wire rxelecidle0_i;
wire resetdone0_i;
wire rxelecidlereset0_i;
wire rxelecidle1_i;
wire resetdone1_i;
wire rxelecidlereset1_i;
// Channel Bonding 3
wire [2:0] chbondi;
wire [2:0] chbondo;
wire [2:0] chbondi_unused_i;
wire serialloopback_i;
//***************************** Register Declarations *****************************
// All TX inputs registered
//********************************* Main Body of Code**************************
//------------------------- Static signal Assigments ---------------------
assign tied_to_ground_i = 1'b0;
assign tied_to_ground_vec_i = 64'h0000000000000000;
assign tied_to_vcc_i = 1'b1;
assign tied_to_vcc_vec_i = 64'hffffffffffffffff;
// Assign lock signals
assign PLLLKDET_OUT = plllkdet_i;
assign serialloopback_i = !LOOPBACK_IN[0] && LOOPBACK_IN[1] && !LOOPBACK_IN[2];
//------------------------- Electrical Idle Reset Circuit ---------------
//Drive RXELECIDLERESET with elec idle reset enabled during normal operation when RXELECIDLE goes high
assign rxelecidlereset0_i = (rxelecidle0_i && resetdone0_i) && !serialloopback_i;
assign rxelecidlereset1_i = (rxelecidle1_i && resetdone1_i) && !serialloopback_i;
assign rxenelecidleresetb_i = !(rxelecidlereset0_i||rxelecidlereset1_i);
// Channel Bonding
assign chbondi_unused_i = 3'b000;
assign chbondi = chbondi_unused_i;
//------------------------- GTP Instantiations --------------------------
//*************************************************************************************************
//-----------------------------------ODD GTP------------------------------------------------
//*************************************************************************************************
GTP_DUAL #
(
//_______________________ Simulation-Only Attributes __________________
.SIM_GTPRESET_SPEEDUP (SIM_GTPRESET_SPEEDUP),
.SIM_PLL_PERDIV2 (SIM_PLL_PERDIV2),
//___________________________ Shared Attributes _______________________
//---------------------- Tile and PLL Attributes ----------------------
.CLK25_DIVIDER (5),
.CLKINDC_B (CLKINDC_B),
.OOB_CLK_DIVIDER (4),
.OVERSAMPLE_MODE ("FALSE"),
.PLL_DIVSEL_FB (2),
.PLL_DIVSEL_REF (1),
.PLL_TXDIVSEL_COMM_OUT (1),
.TX_SYNC_FILTERB (1),
//______________________ Transmit Interface Attributes ________________
//----------------- TX Buffering and Phase Alignment ------------------
.TX_BUFFER_USE_0 ("TRUE"),
.TX_XCLK_SEL_0 ("TXOUT"),
.TXRX_INVERT_0 (5'b00000),
.TX_BUFFER_USE_1 ("TRUE"),
.TX_XCLK_SEL_1 ("TXOUT"),
.TXRX_INVERT_1 (5'b00000),
//------------------- TX Serial Line Rate settings --------------------
.PLL_TXDIVSEL_OUT_0 (2),
.PLL_TXDIVSEL_OUT_1 (2),
//------------------- TX Driver and OOB signalling --------------------
.TX_DIFF_BOOST_0 ("TRUE"),
.TX_DIFF_BOOST_1 ("TRUE"),
//---------------- TX Pipe Control for PCI Express/SATA ---------------
.COM_BURST_VAL_0 (4'b1111),
.COM_BURST_VAL_1 (4'b1111),
//_______________________ Receive Interface Attributes ________________
//---------- RX Driver,OOB signalling,Coupling and Eq.,CDR ------------
.AC_CAP_DIS_0 ("FALSE"),
.OOBDETECT_THRESHOLD_0 (3'b110),
.PMA_CDR_SCAN_0 (27'h6404035),
.PMA_RX_CFG_0 (25'h09F0088),
.RCV_TERM_GND_0 ("FALSE"),
.RCV_TERM_MID_0 ("TRUE"),
.RCV_TERM_VTTRX_0 ("TRUE"),
.TERMINATION_IMP_0 (50),
.AC_CAP_DIS_1 ("FALSE"),
.OOBDETECT_THRESHOLD_1 (3'b110),
.PMA_CDR_SCAN_1 (27'h6404035),
.PMA_RX_CFG_1 (25'h09F0088),
.RCV_TERM_GND_1 ("FALSE"),
.RCV_TERM_MID_1 ("TRUE"),
.RCV_TERM_VTTRX_1 ("TRUE"),
.TERMINATION_IMP_1 (50),
.TERMINATION_CTRL (5'b10100),
.TERMINATION_OVRD ("FALSE"),
//------------------- RX Serial Line Rate Settings --------------------
.PLL_RXDIVSEL_OUT_0 (2),
.PLL_SATA_0 ("FALSE"),
.PLL_RXDIVSEL_OUT_1 (2),
.PLL_SATA_1 ("FALSE"),
//------------------------- PRBS Detection ----------------------------
.PRBS_ERR_THRESHOLD_0 (32'h00000008),
.PRBS_ERR_THRESHOLD_1 (32'h00000008),
//------------------- Comma Detection and Alignment -------------------
.ALIGN_COMMA_WORD_0 (2),
.COMMA_10B_ENABLE_0 (10'b1111111111),
.COMMA_DOUBLE_0 ("FALSE"),
.DEC_MCOMMA_DETECT_0 ("TRUE"),
.DEC_PCOMMA_DETECT_0 ("TRUE"),
.DEC_VALID_COMMA_ONLY_0 ("FALSE"),
.MCOMMA_10B_VALUE_0 (10'b1010000011),
.MCOMMA_DETECT_0 ("TRUE"),
.PCOMMA_10B_VALUE_0 (10'b0101111100),
.PCOMMA_DETECT_0 ("TRUE"),
.RX_SLIDE_MODE_0 ("PCS"),
.ALIGN_COMMA_WORD_1 (2),
.COMMA_10B_ENABLE_1 (10'b1111111111),
.COMMA_DOUBLE_1 ("FALSE"),
.DEC_MCOMMA_DETECT_1 ("TRUE"),
.DEC_PCOMMA_DETECT_1 ("TRUE"),
.DEC_VALID_COMMA_ONLY_1 ("FALSE"),
.MCOMMA_10B_VALUE_1 (10'b1010000011),
.MCOMMA_DETECT_1 ("TRUE"),
.PCOMMA_10B_VALUE_1 (10'b0101111100),
.PCOMMA_DETECT_1 ("TRUE"),
.RX_SLIDE_MODE_1 ("PCS"),
//------------------- RX Loss-of-sync State Machine -------------------
.RX_LOSS_OF_SYNC_FSM_0 ("FALSE"),
.RX_LOS_INVALID_INCR_0 (8),
.RX_LOS_THRESHOLD_0 (128),
.RX_LOSS_OF_SYNC_FSM_1 ("FALSE"),
.RX_LOS_INVALID_INCR_1 (8),
.RX_LOS_THRESHOLD_1 (128),
//------------ RX Elastic Buffer and Phase alignment ports ------------
.RX_BUFFER_USE_0 ("TRUE"),
.RX_XCLK_SEL_0 ("RXREC"),
.RX_BUFFER_USE_1 ("TRUE"),
.RX_XCLK_SEL_1 ("RXREC"),
//--------------------- Clock Correction Attributes -------------------
.CLK_CORRECT_USE_0 ("TRUE"),
.CLK_COR_ADJ_LEN_0 (2),
.CLK_COR_DET_LEN_0 (2),
.CLK_COR_INSERT_IDLE_FLAG_0 ("FALSE"),
.CLK_COR_KEEP_IDLE_0 ("FALSE"),
.CLK_COR_MAX_LAT_0 (32),
.CLK_COR_MIN_LAT_0 (16),
.CLK_COR_PRECEDENCE_0 ("TRUE"),
.CLK_COR_REPEAT_WAIT_0 (0),
.CLK_COR_SEQ_1_1_0 (10'b0111110111),
.CLK_COR_SEQ_1_2_0 (10'b0111110111),
.CLK_COR_SEQ_1_3_0 (10'b0000000000),
.CLK_COR_SEQ_1_4_0 (10'b0000000000),
.CLK_COR_SEQ_1_ENABLE_0 (4'b0011),
.CLK_COR_SEQ_2_1_0 (10'b0000000000),
.CLK_COR_SEQ_2_2_0 (10'b0000000000),
.CLK_COR_SEQ_2_3_0 (10'b0000000000),
.CLK_COR_SEQ_2_4_0 (10'b0000000000),
.CLK_COR_SEQ_2_ENABLE_0 (4'b0000),
.CLK_COR_SEQ_2_USE_0 ("FALSE"),
.RX_DECODE_SEQ_MATCH_0 ("TRUE"),
.CLK_CORRECT_USE_1 ("TRUE"),
.CLK_COR_ADJ_LEN_1 (2),
.CLK_COR_DET_LEN_1 (2),
.CLK_COR_INSERT_IDLE_FLAG_1 ("FALSE"),
.CLK_COR_KEEP_IDLE_1 ("FALSE"),
.CLK_COR_MAX_LAT_1 (32),
.CLK_COR_MIN_LAT_1 (16),
.CLK_COR_PRECEDENCE_1 ("TRUE"),
.CLK_COR_REPEAT_WAIT_1 (0),
.CLK_COR_SEQ_1_1_1 (10'b0111110111),
.CLK_COR_SEQ_1_2_1 (10'b0111110111),
.CLK_COR_SEQ_1_3_1 (10'b0000000000),
.CLK_COR_SEQ_1_4_1 (10'b0000000000),
.CLK_COR_SEQ_1_ENABLE_1 (4'b0011),
.CLK_COR_SEQ_2_1_1 (10'b0000000000),
.CLK_COR_SEQ_2_2_1 (10'b0000000000),
.CLK_COR_SEQ_2_3_1 (10'b0000000000),
.CLK_COR_SEQ_2_4_1 (10'b0000000000),
.CLK_COR_SEQ_2_ENABLE_1 (4'b0000),
.CLK_COR_SEQ_2_USE_1 ("FALSE"),
.RX_DECODE_SEQ_MATCH_1 ("TRUE"),
//-------------------- Channel Bonding Attributes ---------------------
.CHAN_BOND_1_MAX_SKEW_0 (7),
.CHAN_BOND_2_MAX_SKEW_0 (7),
.CHAN_BOND_LEVEL_0 (3'h0),
.CHAN_BOND_MODE_0 ("OFF"),
.CHAN_BOND_SEQ_1_1_0 (10'b0101111100),
.CHAN_BOND_SEQ_1_2_0 (10'b0000000000),
.CHAN_BOND_SEQ_1_3_0 (10'b0000000000),
.CHAN_BOND_SEQ_1_4_0 (10'b0000000000),
.CHAN_BOND_SEQ_1_ENABLE_0 (4'b0001),
.CHAN_BOND_SEQ_2_1_0 (10'b0000000000),
.CHAN_BOND_SEQ_2_2_0 (10'b0000000000),
.CHAN_BOND_SEQ_2_3_0 (10'b0000000000),
.CHAN_BOND_SEQ_2_4_0 (10'b0000000000),
.CHAN_BOND_SEQ_2_ENABLE_0 (4'b0000),
.CHAN_BOND_SEQ_2_USE_0 ("FALSE"),
.CHAN_BOND_SEQ_LEN_0 (1),
.PCI_EXPRESS_MODE_0 ("FALSE"),
.CHAN_BOND_1_MAX_SKEW_1 (7),
.CHAN_BOND_2_MAX_SKEW_1 (7),
.CHAN_BOND_LEVEL_1 (3'h0),
.CHAN_BOND_MODE_1 (CHAN_BOND_MODE_1),
.CHAN_BOND_SEQ_1_1_1 (10'b0101111100),
.CHAN_BOND_SEQ_1_2_1 (10'b0000000000),
.CHAN_BOND_SEQ_1_3_1 (10'b0000000000),
.CHAN_BOND_SEQ_1_4_1 (10'b0000000000),
.CHAN_BOND_SEQ_1_ENABLE_1 (4'b0001),
.CHAN_BOND_SEQ_2_1_1 (10'b0000000000),
.CHAN_BOND_SEQ_2_2_1 (10'b0000000000),
.CHAN_BOND_SEQ_2_3_1 (10'b0000000000),
.CHAN_BOND_SEQ_2_4_1 (10'b0000000000),
.CHAN_BOND_SEQ_2_ENABLE_1 (4'b0000),
.CHAN_BOND_SEQ_2_USE_1 ("FALSE"),
.CHAN_BOND_SEQ_LEN_1 (1),
.PCI_EXPRESS_MODE_1 ("FALSE"),
//---------------- RX Attributes for PCI Express/SATA ---------------
.RX_STATUS_FMT_0 ("PCIE"),
.SATA_BURST_VAL_0 (3'b100),
.SATA_IDLE_VAL_0 (3'b100),
.SATA_MAX_BURST_0 (7),
.SATA_MAX_INIT_0 (22),
.SATA_MAX_WAKE_0 (7),
.SATA_MIN_BURST_0 (4),
.SATA_MIN_INIT_0 (12),
.SATA_MIN_WAKE_0 (4),
.TRANS_TIME_FROM_P2_0 (16'h0060),
.TRANS_TIME_NON_P2_0 (16'h0025),
.TRANS_TIME_TO_P2_0 (16'h0100),
.RX_STATUS_FMT_1 ("PCIE"),
.SATA_BURST_VAL_1 (3'b100),
.SATA_IDLE_VAL_1 (3'b100),
.SATA_MAX_BURST_1 (7),
.SATA_MAX_INIT_1 (22),
.SATA_MAX_WAKE_1 (7),
.SATA_MIN_BURST_1 (4),
.SATA_MIN_INIT_1 (12),
.SATA_MIN_WAKE_1 (4),
.TRANS_TIME_FROM_P2_1 (16'h0060),
.TRANS_TIME_NON_P2_1 (16'h0025),
.TRANS_TIME_TO_P2_1 (16'h0100)
)
GTP_DUAL_INST (
//---------------------- Loopback and Powerdown Ports ----------------------
.LOOPBACK0 (3'b000),
.LOOPBACK1 (LOOPBACK_IN),
.RXPOWERDOWN0 (tied_to_ground_vec_i[1:0]),
.RXPOWERDOWN1 ({POWERDOWN_IN,POWERDOWN_IN}),
.TXPOWERDOWN0 (tied_to_ground_vec_i[1:0]),
.TXPOWERDOWN1 ({POWERDOWN_IN,POWERDOWN_IN}),
//--------------------- Receive Ports - 8b10b Decoder ----------------------
.RXCHARISCOMMA0 (),
.RXCHARISCOMMA1 (RXCHARISCOMMA_OUT ),
.RXCHARISK0 (),
.RXCHARISK1 (RXCHARISK_OUT),
.RXDEC8B10BUSE0 (tied_to_vcc_i),
.RXDEC8B10BUSE1 (tied_to_vcc_i),
.RXDISPERR0 (),
.RXDISPERR1 (RXDISPERR_OUT),
.RXNOTINTABLE0 (),
.RXNOTINTABLE1 (RXNOTINTABLE_OUT),
.RXRUNDISP0 ( ),
.RXRUNDISP1 ( ),
//----------------- Receive Ports - Channel Bonding Ports ------------------
.RXCHANBONDSEQ0 ( ),
.RXCHANBONDSEQ1 ( ),
.RXCHBONDI0 (tied_to_ground_vec_i[2:0]),
.RXCHBONDI1 (chbondi),
.RXCHBONDO0 ( ),
.RXCHBONDO1 (chbondo ),
.RXENCHANSYNC0 (tied_to_ground_i),
.RXENCHANSYNC1 (ENCHANSYNC_IN),
//----------------- Receive Ports - Clock Correction Ports -----------------
.RXCLKCORCNT0 (),
.RXCLKCORCNT1 (),
//------------- Receive Ports - Comma Detection and Alignment --------------
.RXBYTEISALIGNED0 ( ),
.RXBYTEISALIGNED1 ( ),
.RXBYTEREALIGN0 ( ),
.RXBYTEREALIGN1 (RXREALIGN_OUT),
.RXCOMMADET0 ( ),
.RXCOMMADET1 ( ),
.RXCOMMADETUSE0 (tied_to_vcc_i),
.RXCOMMADETUSE1 (tied_to_vcc_i),
.RXENMCOMMAALIGN0 (tied_to_ground_i),
.RXENMCOMMAALIGN1 (ENMCOMMAALIGN_IN),
.RXENPCOMMAALIGN0 (tied_to_ground_i),
.RXENPCOMMAALIGN1 (ENPCOMMAALIGN_IN),
.RXSLIDE0 (tied_to_ground_i),
.RXSLIDE1 (tied_to_ground_i),
//--------------------- Receive Ports - PRBS Detection ---------------------
.PRBSCNTRESET0 (tied_to_ground_i),
.PRBSCNTRESET1 (tied_to_ground_i),
.RXENPRBSTST0 (tied_to_ground_vec_i[1:0]),
.RXENPRBSTST1 (tied_to_ground_vec_i[1:0]),
.RXPRBSERR0 ( ),
.RXPRBSERR1 ( ),
//----------------- Receive Ports - RX Data Path interface -----------------
.RXDATA0 (),
.RXDATA1 (RXDATA_OUT),
.RXDATAWIDTH0 (tied_to_vcc_i),
.RXDATAWIDTH1 (tied_to_vcc_i),
.RXRECCLK0 (),
.RXRECCLK1 (RXRECCLK1_OUT),
.RXRESET0 (tied_to_ground_i),
.RXRESET1 (RXRESET_IN),
.RXUSRCLK0 (tied_to_ground_i),
.RXUSRCLK1 (RXUSRCLK_IN),
.RXUSRCLK20 (tied_to_ground_i),
.RXUSRCLK21 (RXUSRCLK2_IN),
//----- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
.RXCDRRESET0 (tied_to_ground_i),
.RXCDRRESET1 (tied_to_ground_i),
.RXELECIDLE0 (rxelecidle0_i),
.RXELECIDLE1 (rxelecidle1_i),
.RXELECIDLERESET0 (rxelecidlereset0_i),
.RXELECIDLERESET1 (rxelecidlereset1_i),
.RXENEQB0 (tied_to_ground_i),
.RXENEQB1 (tied_to_ground_i),
.RXEQMIX0 (tied_to_ground_vec_i[1:0]),
.RXEQMIX1 (tied_to_ground_vec_i[1:0]),
.RXEQPOLE0 (tied_to_ground_vec_i[3:0]),
.RXEQPOLE1 (tied_to_ground_vec_i[3:0]),
.RXN0 (),
.RXN1 (RX1N_IN),
.RXP0 (),
.RXP1 (RX1P_IN),
//------ Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
.RXBUFRESET0 (tied_to_ground_i),
.RXBUFRESET1 (tied_to_ground_i),
.RXBUFSTATUS0 ( ),
.RXBUFSTATUS1 ({RXBUFERR_OUT,open_rxbufstatus_i} ),
.RXCHANISALIGNED0 (),
.RXCHANISALIGNED1 (CHBONDDONE_OUT ),
.RXCHANREALIGN0 ( ),
.RXCHANREALIGN1 ( ),
.RXPMASETPHASE0 (tied_to_ground_i),
.RXPMASETPHASE1 (tied_to_ground_i),
.RXSTATUS0 ( ),
.RXSTATUS1 ( ),
//------------- Receive Ports - RX Loss-of-sync State Machine --------------
.RXLOSSOFSYNC0 ( ),
.RXLOSSOFSYNC1 ( ),
//-------------------- Receive Ports - RX Oversampling ---------------------
.RXENSAMPLEALIGN0 (tied_to_ground_i),
.RXENSAMPLEALIGN1 (tied_to_ground_i),
.RXOVERSAMPLEERR0 ( ),
.RXOVERSAMPLEERR1 ( ),
//------------ Receive Ports - RX Pipe Control for PCI Express -------------
.PHYSTATUS0 ( ),
.PHYSTATUS1 ( ),
.RXVALID0 ( ),
.RXVALID1 ( ),
//--------------- Receive Ports - RX Polarity Control Ports ----------------
.RXPOLARITY0 (tied_to_ground_i),
.RXPOLARITY1 (RXPOLARITY_IN),
//----------- Shared Ports - Dynamic Reconfiguration Port (DRP) ------------
.DADDR (tied_to_ground_vec_i[6:0]),
.DCLK (tied_to_ground_i),
.DEN (tied_to_ground_i),
.DI (tied_to_ground_vec_i[15:0]),
.DO ( ),
.DRDY ( ),
.DWE (tied_to_ground_i),
//------------------- Shared Ports - Tile and PLL Ports --------------------
.CLKIN (REFCLK),
.GTPRESET (GTPRESET_IN),
.GTPTEST (tied_to_ground_vec_i[3:0]),
.INTDATAWIDTH (tied_to_vcc_i),
.PLLLKDET (plllkdet_i),
.PLLLKDETEN (tied_to_vcc_i),
.PLLPOWERDOWN (POWERDOWN_IN),
.REFCLKOUT (),
.REFCLKPWRDNB (tied_to_vcc_i),
.RESETDONE0 (resetdone0_i),
.RESETDONE1 (resetdone1_i),
.RXENELECIDLERESETB (rxenelecidleresetb_i),
.TXENPMAPHASEALIGN (tied_to_ground_i),
.TXPMASETPHASE (tied_to_ground_i),
//-------------- Transmit Ports - 8b10b Encoder Control Ports --------------
.TXBYPASS8B10B0 (tied_to_ground_vec_i[1:0]),
.TXBYPASS8B10B1 (tied_to_ground_vec_i[1:0]),
.TXCHARDISPMODE0 (tied_to_ground_vec_i[1:0]),
.TXCHARDISPMODE1 (tied_to_ground_vec_i[1:0]),
.TXCHARDISPVAL0 (tied_to_ground_vec_i[1:0]),
.TXCHARDISPVAL1 (tied_to_ground_vec_i[1:0]),
.TXCHARISK0 (tied_to_ground_vec_i[1:0]),
.TXCHARISK1 (TXCHARISK_IN),
.TXENC8B10BUSE0 (tied_to_vcc_i),
.TXENC8B10BUSE1 (tied_to_vcc_i),
.TXKERR0 ( ),
.TXKERR1 ( ),
.TXRUNDISP0 ( ),
.TXRUNDISP1 ( ),
//----------- Transmit Ports - TX Buffering and Phase Alignment ------------
.TXBUFSTATUS0 ( ),
.TXBUFSTATUS1 ({TXBUFERR_OUT, open_txbufstatus_i}),
//---------------- Transmit Ports - TX Data Path interface -----------------
.TXDATA0 (tied_to_ground_vec_i[15:0]),
.TXDATA1 (TXDATA_IN),
.TXDATAWIDTH0 (tied_to_vcc_i),
.TXDATAWIDTH1 (tied_to_vcc_i),
.TXOUTCLK0 (),
.TXOUTCLK1 (TXOUTCLK1_OUT),
.TXRESET0 (tied_to_ground_i),
.TXRESET1 (TXRESET_IN),
.TXUSRCLK0 (tied_to_ground_i),
.TXUSRCLK1 (TXUSRCLK_IN ),
.TXUSRCLK20 (tied_to_ground_i),
.TXUSRCLK21 (TXUSRCLK2_IN),
//------------- Transmit Ports - TX Driver and OOB signalling --------------
.TXBUFDIFFCTRL0 (3'b000),
.TXBUFDIFFCTRL1 (3'b000),
.TXDIFFCTRL0 (3'b000),
.TXDIFFCTRL1 (3'b000),
.TXINHIBIT0 (tied_to_ground_i),
.TXINHIBIT1 (tied_to_ground_i),
.TXN0 (),
.TXN1 (TX1N_OUT),
.TXP0 (),
.TXP1 (TX1P_OUT),
.TXPREEMPHASIS0 (3'b011),
.TXPREEMPHASIS1 (3'b011),
//------------------- Transmit Ports - TX PRBS Generator -------------------
.TXENPRBSTST0 (tied_to_ground_vec_i[1:0]),
.TXENPRBSTST1 (tied_to_ground_vec_i[1:0]),
//------------------ Transmit Ports - TX Polarity Control ------------------
.TXPOLARITY0 (tied_to_ground_i),
.TXPOLARITY1 (tied_to_ground_i),
//--------------- Transmit Ports - TX Ports for PCI Express ----------------
.TXDETECTRX0 (tied_to_ground_i),
.TXDETECTRX1 (tied_to_ground_i),
.TXELECIDLE0 (tied_to_ground_i),
.TXELECIDLE1 (tied_to_ground_i),
//------------------- Transmit Ports - TX Ports for SATA -------------------
.TXCOMSTART0 (tied_to_ground_i),
.TXCOMSTART1 (tied_to_ground_i),
.TXCOMTYPE0 (tied_to_ground_i),
.TXCOMTYPE1 (tied_to_ground_i)
);
endmodule
|
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module data_fifo (
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrfull);
parameter WIDTH = 24;
input [WIDTH-1:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [WIDTH-1:0] q;
output rdempty;
output wrfull;
wire [WIDTH-1:0] sub_wire0;
wire sub_wire1;
wire sub_wire2;
wire [WIDTH-1:0] q = sub_wire0[WIDTH-1:0];
wire rdempty = sub_wire1;
wire wrfull = sub_wire2;
dcfifo dcfifo_component (
.data (data),
.rdclk (rdclk),
.rdreq (rdreq),
.wrclk (wrclk),
.wrreq (wrreq),
.q (sub_wire0),
.rdempty (sub_wire1),
.wrfull (sub_wire2),
.aclr (),
.eccstatus (),
.rdfull (),
.rdusedw (),
.wrempty (),
.wrusedw ());
defparam
dcfifo_component.intended_device_family = "Cyclone 10 LP",
dcfifo_component.lpm_numwords = 4,
dcfifo_component.lpm_showahead = "OFF",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = WIDTH,
dcfifo_component.lpm_widthu = 2,
dcfifo_component.overflow_checking = "ON",
dcfifo_component.rdsync_delaypipe = 5,
dcfifo_component.underflow_checking = "ON",
dcfifo_component.use_eab = "OFF",
dcfifo_component.wrsync_delaypipe = 5;
endmodule
|
module rom
(
input clk,
input reset_n,
input [5:0] addr,
output load,
output shift,
output sclk,
output output_enable_n,
output latch_enable
);
reg [4:0] rom_data, data_reg;
always @(posedge clk, negedge reset_n)
begin
if (!reset_n)
begin
data_reg <= 5'b00010;
end
else
begin
data_reg <= rom_data;
end
end
always @*
begin
case (addr)
// data = load, shift, sclk, oe_n, le
6'd00: rom_data = 5'b10000;
6'd01: rom_data = 5'b00000;
6'd02: rom_data = 5'b01100;
6'd03: rom_data = 5'b00100;
6'd04: rom_data = 5'b00000;
6'd05: rom_data = 5'b01100;
6'd06: rom_data = 5'b00100;
6'd07: rom_data = 5'b00000;
6'd08: rom_data = 5'b01100;
6'd09: rom_data = 5'b00100;
6'd10: rom_data = 5'b00000;
6'd11: rom_data = 5'b01100;
6'd12: rom_data = 5'b00100;
6'd13: rom_data = 5'b00000;
6'd14: rom_data = 5'b01100;
6'd15: rom_data = 5'b00100;
6'd16: rom_data = 5'b00000;
6'd17: rom_data = 5'b01100;
6'd18: rom_data = 5'b00100;
6'd19: rom_data = 5'b00000;
6'd20: rom_data = 5'b01100;
6'd21: rom_data = 5'b00100;
6'd22: rom_data = 5'b00000;
6'd23: rom_data = 5'b01100;
6'd24: rom_data = 5'b00100;
6'd25: rom_data = 5'b00000; // Data clocked in
6'd26: rom_data = 5'b01100;
6'd27: rom_data = 5'b00100;
6'd28: rom_data = 5'b00000;
6'd29: rom_data = 5'b01100;
6'd30: rom_data = 5'b00100;
6'd31: rom_data = 5'b00000;
6'd32: rom_data = 5'b01100;
6'd33: rom_data = 5'b00100;
6'd34: rom_data = 5'b00000;
6'd35: rom_data = 5'b01100;
6'd36: rom_data = 5'b00100;
6'd37: rom_data = 5'b00000;
6'd38: rom_data = 5'b01100;
6'd39: rom_data = 5'b00100;
6'd40: rom_data = 5'b00000;
6'd41: rom_data = 5'b01100;
6'd42: rom_data = 5'b00100;
6'd43: rom_data = 5'b00000;
6'd44: rom_data = 5'b01100;
6'd45: rom_data = 5'b00100;
6'd46: rom_data = 5'b00000;
6'd47: rom_data = 5'b00100;
6'd48: rom_data = 5'b00100;
6'd49: rom_data = 5'b00000; // Data clocked in
6'd50: rom_data = 5'b00001; // Data latched
6'd51: rom_data = 5'b00001;
6'd52: rom_data = 5'b00001;
6'd53: rom_data = 5'b00001;
6'd54: rom_data = 5'b00000;
6'd55: rom_data = 5'b00000;
6'd56: rom_data = 5'b00000;
6'd57: rom_data = 5'b00000;
6'd58: rom_data = 5'b00000;
6'd59: rom_data = 5'b00000;
6'd60: rom_data = 5'b00000;
6'd61: rom_data = 5'b00000;
6'd62: rom_data = 5'b00000;
6'd63: rom_data = 5'b00000;
endcase // case (addr)
end // always @ *
assign load = data_reg[4];
assign shift = data_reg[3];
assign sclk = data_reg[2];
assign output_enable_n = data_reg[1];
assign latch_enable = data_reg[0];
endmodule
|
//`define EXERCISER_DEBUG
`define NULL 0
`timescale 1ns / 1 ps
module rc_pcs_pipe_top (
input wire refclkp,
input wire refclkn,
input wire RESET_n,
input wire ffc_quad_rst,
input wire [1:0] PowerDown,
input wire TxDetectRx_Loopback,
output wire PCLK,
`ifdef DataWidth_8
output wire PCLK_by_2,
`endif
output reg PhyStatus,
output wire ffs_plol,
`ifdef Channel_0
input wire hdinp0,
input wire hdinn0,
output wire hdoutp0,
output wire hdoutn0,
`endif
`ifdef Channel_1
input wire hdinp1,
input wire hdinn1,
output wire hdoutp1,
output wire hdoutn1,
`endif
`ifdef Channel_2
input wire hdinp2,
input wire hdinn2,
output wire hdoutp2,
output wire hdoutn2,
`endif
`ifdef Channel_3
input wire hdinp3,
input wire hdinn3,
output wire hdoutp3,
output wire hdoutn3,
`endif
input wire [`DataWidth-1:0] TxData_0,
input wire [`BusWidth-1:0] TxDataK_0,
input wire TxCompliance_0,
input wire TxElecIdle_0,
input wire RxPolarity_0,
input wire scisel_0,
input wire scien_0,
output wire [`DataWidth-1:0] RxData_0,
output wire [`BusWidth-1:0] RxDataK_0,
output wire RxValid_0,
output wire RxElecIdle_0,
output wire [2:0] RxStatus_0,
output wire ffs_rlol_ch0,
`ifdef X4
input wire [`DataWidth-1:0] TxData_1,
input wire [`BusWidth-1:0] TxDataK_1,
input wire TxCompliance_1,
input wire TxElecIdle_1,
input wire RxPolarity_1,
input wire scisel_1,
input wire scien_1,
output wire [`DataWidth-1:0] RxData_1,
output wire [`BusWidth-1:0] RxDataK_1,
output wire RxValid_1,
output wire RxElecIdle_1,
output wire [2:0] RxStatus_1,
// output ffs_rlol_ch1,
input wire [`DataWidth-1:0] TxData_2,
input wire [`BusWidth-1:0] TxDataK_2,
input wire TxCompliance_2,
input wire TxElecIdle_2,
input wire RxPolarity_2,
input wire scisel_2,
input wire scien_2,
output wire [`DataWidth-1:0] RxData_2,
output wire [`BusWidth-1:0] RxDataK_2,
output wire RxValid_2,
output wire RxElecIdle_2,
output wire [2:0] RxStatus_2,
// output ffs_rlol_ch2,
input wire [`DataWidth-1:0] TxData_3,
input wire [`BusWidth-1:0] TxDataK_3,
input wire TxCompliance_3,
input wire TxElecIdle_3,
input wire RxPolarity_3,
input wire scisel_3,
input wire scien_3,
output wire [`DataWidth-1:0] RxData_3,
output wire [`BusWidth-1:0] RxDataK_3,
output wire RxValid_3,
output wire RxElecIdle_3,
output wire [2:0] RxStatus_3,
// output ffs_rlol_ch3,
`endif // X4
input [7:0] sciwritedata,
input [5:0] sciaddress,
input sciselaux,
input scienaux,
input scird,
input sciwstn,
output[7:0] scireaddata,
input wire phy_l0,
input wire [3:0] phy_cfgln,
input wire ctc_disable,
input wire flip_lanes
);
// =============================================================================
// Parameters
// =============================================================================
`ifdef DataWidth_8
localparam ONE_US = 8'b11111111; // 1 Micro sec = 256 clks
localparam ONE_US_4BYTE = 8'b00000101; // 1 us + 6 clks
`endif
`ifdef DataWidth_16
localparam ONE_US = 7'b1111111; // 1 Micro sec = 128 clks
localparam ONE_US_4BYTE = 7'b0000010; // 1 us + 3 clks
`endif
localparam PCIE_DET_IDLE = 2'b00;
localparam PCIE_DET_EN = 2'b01;
localparam PCIE_CT = 2'b10;
localparam PCIE_DONE = 2'b11;
// =============================================================================
// Wires & Regs
// =============================================================================
wire clk_250;
wire clk_125;
wire [19:0] cout;
wire ffs_rlol_ch1;
wire ffs_rlol_ch2;
wire ffs_rlol_ch3;
wire fpsc_vlo;
wire [11:0] cin;
wire ffc_trst;
wire ffc_macro_rst;
wire ffc_lane_tx_rst;
wire ffc_lane_rx_rst;
wire ffc_signal_detect;
wire ffc_enb_cgalign;
//wire sync_rst;
reg sync_rst;
wire ff_tx_f_clk;
wire ff_tx_h_clk;
`ifdef ECP3
wire ff_tx_f_clk_0;
wire ff_tx_f_clk_1;
wire ff_tx_f_clk_2;
wire ff_tx_f_clk_3;
wire ff_tx_h_clk_0;
wire ff_tx_h_clk_1;
wire ff_tx_h_clk_2;
wire ff_tx_h_clk_3;
`endif
`ifdef X1
`ifdef Channel_0
wire ffs_pcie_done_0;
wire ffs_pcie_con_0;
wire RxValid_0_in;
wire RxElecIdle_0_in;
wire [7:0] RxData_0_in;
wire RxDataK_0_in;
wire [2:0] RxStatus_0_in;
wire [7:0] TxData_0_out;
wire TxDataK_0_out;
wire flip_RxValid_0;
wire [`DataWidth-1:0] flip_RxData_0;
wire [`BusWidth-1:0] flip_RxDataK_0;
wire flip_RxElecIdle_0;
wire [2:0] flip_RxStatus_0;
wire [`DataWidth-1:0] flip_TxData_0;
wire [`BusWidth-1:0] flip_TxDataK_0;
//wire flip_TxElecIdle_0;
wire flip_TxElecIdle_0;
wire flip_TxCompliance_0;
wire flip_scisel_0;
wire flip_scien_0;
wire flip_RxPolarity_0;
wire [3:0] flip_phy_cfgln;
assign RxValid_0 = flip_RxValid_0;
assign RxData_0 = flip_RxData_0;
assign RxDataK_0 = flip_RxDataK_0;
assign RxElecIdle_0 = flip_RxElecIdle_0;
assign RxStatus_0 = flip_RxStatus_0;
assign flip_TxData_0 = TxData_0;
assign flip_TxDataK_0 = TxDataK_0;
assign flip_TxElecIdle_0 = TxElecIdle_0;
assign flip_TxCompliance_0 = TxCompliance_0;
assign flip_RxPolarity_0 = RxPolarity_0;
assign flip_scisel_0 = scisel_0;
assign flip_scien_0 = scien_0;
assign flip_phy_cfgln = phy_cfgln;
`endif
`ifdef Channel_1
wire ffs_pcie_done_1;
wire ffs_pcie_con_1;
wire RxValid_1_in;
wire RxElecIdle_1_in;
wire [7:0] RxData_1_in;
wire RxDataK_1_in;
wire [2:0] RxStatus_1_in;
wire [7:0] TxData_1_out;
wire TxDataK_1_out;
wire flip_RxValid_1;
wire [`DataWidth-1:0] flip_RxData_1;
wire [`BusWidth-1:0] flip_RxDataK_1;
wire flip_RxElecIdle_1;
wire [2:0] flip_RxStatus_1;
wire [`DataWidth-1:0] flip_TxData_1;
wire [`BusWidth-1:0] flip_TxDataK_1;
wire flip_TxElecIdle_1;
wire flip_TxCompliance_1;
wire flip_scisel_1;
wire flip_scien_1;
wire flip_RxPolarity_1;
wire [3:0] flip_phy_cfgln;
assign RxValid_0 = flip_RxValid_1;
assign RxData_0 = flip_RxData_1;
assign RxDataK_0 = flip_RxDataK_1;
assign RxElecIdle_0 = flip_RxElecIdle_1;
assign RxStatus_0 = flip_RxStatus_1;
assign flip_TxData_1 = TxData_0;
assign flip_TxDataK_1 = TxDataK_0;
assign flip_TxElecIdle_1 = TxElecIdle_0;
assign flip_TxCompliance_1 = TxCompliance_0;
assign flip_RxPolarity_1 = RxPolarity_0;
assign flip_scisel_1 = scisel_0;
assign flip_scien_1 = scien_0;
assign flip_phy_cfgln = phy_cfgln;
assign ffs_pcie_con_0 = ffs_pcie_con_1;
`endif // Channel_1
`ifdef Channel_2
wire ffs_pcie_done_2;
wire ffs_pcie_con_2;
wire RxValid_2_in;
wire RxElecIdle_2_in;
wire [7:0] RxData_2_in;
wire RxDataK_2_in;
wire [2:0] RxStatus_2_in;
wire [7:0] TxData_2_out;
wire TxDataK_2_out;
wire flip_RxValid_2;
wire [`DataWidth-1:0] flip_RxData_2;
wire [`BusWidth-1:0] flip_RxDataK_2;
wire flip_RxElecIdle_2;
wire [2:0] flip_RxStatus_2;
wire [`DataWidth-1:0] flip_TxData_2;
wire [`BusWidth-1:0] flip_TxDataK_2;
wire flip_TxElecIdle_2;
wire flip_TxCompliance_2;
wire flip_scisel_2;
wire flip_scien_2;
wire flip_RxPolarity_2;
wire [3:0] flip_phy_cfgln;
assign RxValid_0 = flip_RxValid_2;
assign RxData_0 = flip_RxData_2;
assign RxDataK_0 = flip_RxDataK_2;
assign RxElecIdle_0 = flip_RxElecIdle_2;
assign RxStatus_0 = flip_RxStatus_2;
assign flip_TxData_2 = TxData_0;
assign flip_TxDataK_2 = TxDataK_0;
assign flip_TxElecIdle_2 = TxElecIdle_0;
assign flip_TxCompliance_2 = TxCompliance_0;
assign flip_RxPolarity_2 = RxPolarity_0;
assign flip_scisel_2 = scisel_0;
assign flip_scien_2 = scien_0;
assign flip_phy_cfgln = phy_cfgln;
assign ffs_pcie_con_0 = ffs_pcie_con_2;
`endif // Channel_2
`ifdef Channel_3
wire ffs_pcie_done_3;
wire ffs_pcie_con_3;
wire RxValid_3_in;
wire RxElecIdle_3_in;
wire [7:0] RxData_3_in;
wire RxDataK_3_in;
wire [2:0] RxStatus_3_in;
wire [7:0] TxData_3_out;
wire TxDataK_3_out;
wire flip_RxValid_3;
wire [`DataWidth-1:0] flip_RxData_3;
wire [`BusWidth-1:0] flip_RxDataK_3;
wire flip_RxElecIdle_3;
wire [2:0] flip_RxStatus_3;
wire [`DataWidth-1:0] flip_TxData_3;
wire [`BusWidth-1:0] flip_TxDataK_3;
wire flip_TxElecIdle_3;
wire flip_TxCompliance_3;
wire flip_scisel_3;
wire flip_scien_3;
wire flip_RxPolarity_3;
wire [3:0] flip_phy_cfgln;
assign RxValid_0 = flip_RxValid_3;
assign RxData_0 = flip_RxData_3;
assign RxDataK_0 = flip_RxDataK_3;
assign RxElecIdle_0 = flip_RxElecIdle_3;
assign RxStatus_0 = flip_RxStatus_3;
assign flip_TxData_3 = TxData_0;
assign flip_TxDataK_3 = TxDataK_0;
assign flip_TxElecIdle_3 = TxElecIdle_0;
assign flip_TxCompliance_3 = TxCompliance_0;
assign flip_RxPolarity_3 = RxPolarity_0;
assign flip_scisel_3 = scisel_0;
assign flip_scien_3 = scien_0;
assign flip_phy_cfgln = phy_cfgln;
assign ffs_pcie_con_0 = ffs_pcie_con_3;
`endif // Channel_3
`endif
`ifdef X4
wire [3:0] flip_phy_cfgln;
wire RxValid_0_in;
wire RxElecIdle_0_in;
wire [7:0] RxData_0_in;
wire RxDataK_0_in;
wire [2:0] RxStatus_0_in;
wire [7:0] TxData_0_out;
wire TxDataK_0_out;
wire flip_RxValid_0;
wire [`DataWidth-1:0] flip_RxData_0;
wire [`BusWidth-1:0] flip_RxDataK_0;
wire flip_RxElecIdle_0;
wire [2:0] flip_RxStatus_0;
wire [`DataWidth-1:0] flip_TxData_0;
wire [`BusWidth-1:0] flip_TxDataK_0;
wire flip_TxElecIdle_0;
wire flip_TxCompliance_0;
wire flip_scisel_0;
wire flip_scien_0;
wire flip_RxPolarity_0;
wire RxValid_1_in;
wire RxElecIdle_1_in;
wire [7:0] RxData_1_in;
wire RxDataK_1_in;
wire [2:0] RxStatus_1_in;
wire [7:0] TxData_1_out;
wire TxDataK_1_out;
wire flip_RxValid_1;
wire [`DataWidth-1:0] flip_RxData_1;
wire [`BusWidth-1:0] flip_RxDataK_1;
wire flip_RxElecIdle_1;
wire [2:0] flip_RxStatus_1;
wire [`DataWidth-1:0] flip_TxData_1;
wire [`BusWidth-1:0] flip_TxDataK_1;
wire flip_TxElecIdle_1;
wire flip_TxCompliance_1;
wire flip_scisel_1;
wire flip_scien_1;
wire flip_RxPolarity_1;
wire RxValid_2_in;
wire RxElecIdle_2_in;
wire [7:0] RxData_2_in;
wire RxDataK_2_in;
wire [2:0] RxStatus_2_in;
wire [7:0] TxData_2_out;
wire TxDataK_2_out;
wire flip_RxValid_2;
wire [`DataWidth-1:0] flip_RxData_2;
wire [`BusWidth-1:0] flip_RxDataK_2;
wire flip_RxElecIdle_2;
wire [2:0] flip_RxStatus_2;
wire [`DataWidth-1:0] flip_TxData_2;
wire [`BusWidth-1:0] flip_TxDataK_2;
wire flip_TxElecIdle_2;
wire flip_TxCompliance_2;
wire flip_scisel_2;
wire flip_scien_2;
wire flip_RxPolarity_2;
wire RxValid_3_in;
wire RxElecIdle_3_in;
wire [7:0] RxData_3_in;
wire RxDataK_3_in;
wire [2:0] RxStatus_3_in;
wire [7:0] TxData_3_out;
wire TxDataK_3_out;
wire flip_RxValid_3;
wire [`DataWidth-1:0] flip_RxData_3;
wire [`BusWidth-1:0] flip_RxDataK_3;
wire flip_RxElecIdle_3;
wire [2:0] flip_RxStatus_3;
wire [`DataWidth-1:0] flip_TxData_3;
wire [`BusWidth-1:0] flip_TxDataK_3;
wire flip_TxElecIdle_3;
wire flip_TxCompliance_3;
wire flip_scisel_3;
wire flip_scien_3;
wire flip_RxPolarity_3;
wire ffs_pcie_done_0;
wire ffs_pcie_done_1;
wire ffs_pcie_done_2;
wire ffs_pcie_done_3;
wire ffs_pcie_con_0;
wire ffs_pcie_con_1;
wire ffs_pcie_con_2;
wire ffs_pcie_con_3;
// =============================================================================
// Flip Logic (for X4 Only)
// =============================================================================
assign {RxValid_3, RxValid_2, RxValid_1, RxValid_0} = flip_lanes ?
{flip_RxValid_0, flip_RxValid_1, flip_RxValid_2, flip_RxValid_3}:
{flip_RxValid_3, flip_RxValid_2, flip_RxValid_1, flip_RxValid_0};
assign {RxData_3, RxData_2, RxData_1, RxData_0} = flip_lanes ?
{flip_RxData_0, flip_RxData_1, flip_RxData_2, flip_RxData_3}:
{flip_RxData_3, flip_RxData_2, flip_RxData_1, flip_RxData_0};
assign {RxDataK_3, RxDataK_2, RxDataK_1, RxDataK_0} = flip_lanes ?
{flip_RxDataK_0, flip_RxDataK_1, flip_RxDataK_2, flip_RxDataK_3}:
{flip_RxDataK_3, flip_RxDataK_2, flip_RxDataK_1, flip_RxDataK_0};
assign {RxElecIdle_3, RxElecIdle_2, RxElecIdle_1, RxElecIdle_0} = flip_lanes ?
{flip_RxElecIdle_0, flip_RxElecIdle_1, flip_RxElecIdle_2, flip_RxElecIdle_3}:
{flip_RxElecIdle_3, flip_RxElecIdle_2, flip_RxElecIdle_1, flip_RxElecIdle_0};
assign {RxStatus_3, RxStatus_2, RxStatus_1, RxStatus_0} = flip_lanes ?
{flip_RxStatus_0, flip_RxStatus_1, flip_RxStatus_2, flip_RxStatus_3}:
{flip_RxStatus_3, flip_RxStatus_2, flip_RxStatus_1, flip_RxStatus_0};
assign {flip_TxData_3, flip_TxData_2, flip_TxData_1, flip_TxData_0} = flip_lanes ?
{TxData_0, TxData_1, TxData_2, TxData_3}:
{TxData_3, TxData_2, TxData_1, TxData_0};
assign {flip_TxDataK_3, flip_TxDataK_2, flip_TxDataK_1, flip_TxDataK_0} = flip_lanes ?
{TxDataK_0, TxDataK_1, TxDataK_2, TxDataK_3}:
{TxDataK_3, TxDataK_2, TxDataK_1, TxDataK_0};
assign {flip_TxElecIdle_3, flip_TxElecIdle_2, flip_TxElecIdle_1, flip_TxElecIdle_0} = flip_lanes ?
{TxElecIdle_0, TxElecIdle_1, TxElecIdle_2, TxElecIdle_3}:
{TxElecIdle_3, TxElecIdle_2, TxElecIdle_1, TxElecIdle_0};
assign {flip_TxCompliance_3, flip_TxCompliance_2, flip_TxCompliance_1, flip_TxCompliance_0} = flip_lanes ?
{TxCompliance_0, TxCompliance_1, TxCompliance_2, TxCompliance_3}:
{TxCompliance_3, TxCompliance_2, TxCompliance_1, TxCompliance_0};
assign {flip_RxPolarity_3, flip_RxPolarity_2, flip_RxPolarity_1, flip_RxPolarity_0} = flip_lanes ?
{RxPolarity_0, RxPolarity_1, RxPolarity_2, RxPolarity_3}:
{RxPolarity_3, RxPolarity_2, RxPolarity_1, RxPolarity_0};
assign {flip_scisel_3, flip_scisel_2, flip_scisel_1, flip_scisel_0} = flip_lanes ?
{scisel_0, scisel_1, scisel_2, scisel_3}:
{scisel_3, scisel_2, scisel_1, scisel_0};
assign {flip_scien_3, flip_scien_2, flip_scien_1, flip_scien_0} = flip_lanes ?
{scien_0, scien_1, scien_2, scien_3}:
{scien_3, scien_2, scien_1, scien_0};
assign {flip_phy_cfgln[3], flip_phy_cfgln[2], flip_phy_cfgln[1], flip_phy_cfgln[0]} = flip_lanes ?
{phy_cfgln[0], phy_cfgln[1], phy_cfgln[2], phy_cfgln[3]}:
{phy_cfgln[3], phy_cfgln[2], phy_cfgln[1], phy_cfgln[0]};
`endif // X4
// =============================================================================
// =============================================================================
//For PowerDown
`ifdef X4
reg ffc_pwdnb_0;
reg ffc_pwdnb_1;
reg ffc_pwdnb_2;
reg ffc_pwdnb_3;
reg ffc_rrst_0;
reg ffc_rrst_1;
reg ffc_rrst_2;
reg ffc_rrst_3;
`endif // X4
`ifdef X1
wire ffc_pwdnb_0;
wire ffc_pwdnb_1;
wire ffc_pwdnb_2;
wire ffc_pwdnb_3;
wire ffc_rrst_0;
wire ffc_rrst_1;
wire ffc_rrst_2;
wire ffc_rrst_3;
`endif // X1
//For DETECT State Machine
reg [1:0] cs_reqdet_sm;
reg detsm_done;
reg [3:0] det_result; // Only for RTL sim
reg pcie_con_0;
reg pcie_con_1;
reg pcie_con_2;
reg pcie_con_3;
reg ffc_pcie_ct;
reg ffc_pcie_det_en_0;
reg ffc_pcie_det_en_1;
reg ffc_pcie_det_en_2;
reg ffc_pcie_det_en_3;
reg cnt_enable;
reg cntdone_en;
reg cntdone_ct;
`ifdef DataWidth_8
reg [7:0] detsm_cnt; // 1 us (256 clks)
`endif
`ifdef DataWidth_16
reg [6:0] detsm_cnt; // 1 us (128 clks)
`endif
wire done_all_re;
wire done_0_re;
wire done_1_re;
wire done_2_re;
wire done_3_re;
reg done_0_reg;
reg done_0_d0 /* synthesis syn_srlstyle="registers" */;
reg done_0_d1 /* synthesis syn_srlstyle="registers" */;
reg done_1_reg;
reg done_1_d0 /* synthesis syn_srlstyle="registers" */;
reg done_1_d1 /* synthesis syn_srlstyle="registers" */;
reg done_2_reg;
reg done_2_d0 /* synthesis syn_srlstyle="registers" */;
reg done_2_d1 /* synthesis syn_srlstyle="registers" */;
reg done_3_reg;
reg done_3_d0 /* synthesis syn_srlstyle="registers" */;
reg done_3_d1 /* synthesis syn_srlstyle="registers" */;
reg done_all;
reg done_all_reg /* synthesis syn_srlstyle="registers" */;
reg detect_req;
reg detect_req_del /* synthesis syn_srlstyle="registers" */;
reg enable_det_ch0 ;
reg enable_det_ch1 ;
reg enable_det_ch2 ;
reg enable_det_ch3 ;
wire enable_det_int ;
wire enable_det_all ;
reg PLOL_sync;
reg PLOL_pclk /* synthesis syn_srlstyle="registers" */;
reg [1:0] PowerDown_reg /* synthesis syn_srlstyle="registers" */;
reg PLOL_hsync;
reg PLOL_hclk;
// Signals for Masking RxValid for 4 MS
reg [16:0] count_ms;
reg count_ms_enable;
reg [2:0] num_ms;
reg pcs_wait_done;
reg detection_done;
reg start_count;
reg start_count_del;
reg [3:0] RxEI_sync;
reg [3:0] RxEI;
reg [3:0] RxEI_masked_sync;
reg [3:0] RxEI_masked;
wire EI_Det_0;
wire EI_Det_1;
wire EI_Det_2;
wire EI_Det_3;
reg [3:0] EI_low;
reg [3:0] EI_low_pulse;
reg reset_counter;
reg allEI_high;
reg [3:0] RxLOL_sync;
reg [3:0] RxLOL;
reg [3:0] RxLOL_del;
reg [3:0] RxLOL_posedge;
// Signals for Masking EI for 1 us (false glitch)
reg check;
reg start_mask;
reg [6:0] ei_counter;
// Signals for sync_rst generation
reg [3:0] rlol_sync;
reg [3:0] rx_elec /* synthesis syn_srlstyle="registers" */;
reg [3:0] rlol_fclk /* synthesis syn_srlstyle="registers" */;
reg [3:0] rlol_rst_ch;
// For Default Values / RTL Simulation
reg Int_RxElecIdle_ch0;
reg Int_RxElecIdle_ch1;
reg Int_RxElecIdle_ch2;
reg Int_RxElecIdle_ch3;
reg Int_ffs_rlol_ch0;
reg Int_ffs_rlol_ch1;
reg Int_ffs_rlol_ch2;
reg Int_ffs_rlol_ch3;
wire RxElecIdle_ch0_8; //Required for 4 MS mask from PIPE TOP
wire RxElecIdle_ch1_8;
wire RxElecIdle_ch2_8;
wire RxElecIdle_ch3_8;
wire ff_rx_fclk_0 /* synthesis syn_keep=1 */;
wire ff_rx_fclk_1 /* synthesis syn_keep=1 */;
wire ff_rx_fclk_2 /* synthesis syn_keep=1 */;
wire ff_rx_fclk_3 /* synthesis syn_keep=1 */;
// =============================================================================
VLO fpsc_vlo_inst (.Z(fpsc_vlo));
VHI fpsc_vhi_inst (.Z(fpsc_vhi));
assign cin = 12'h0;
assign ffc_trst = fpsc_vlo;
assign ffc_macro_rst = fpsc_vlo;
assign ffc_lane_tx_rst = sync_rst;
assign ffc_lane_rx_rst = sync_rst;
assign ffc_signal_detect = 1'b0;
assign ffc_enb_cgalign = 1'b1;
//--------- RK MOD ----------
`ifdef ECP3
`ifdef X4
assign ff_tx_f_clk = ff_tx_f_clk_0;
assign ff_tx_h_clk = ff_tx_h_clk_0;
`else
`ifdef Channel_0
assign ff_tx_f_clk = ff_tx_f_clk_0;
assign ff_tx_h_clk = ff_tx_h_clk_0;
`endif
`ifdef Channel_1
assign ff_tx_f_clk = ff_tx_f_clk_1;
assign ff_tx_h_clk = ff_tx_h_clk_1;
`endif
`ifdef Channel_2
assign ff_tx_f_clk = ff_tx_f_clk_2;
assign ff_tx_h_clk = ff_tx_h_clk_2;
`endif
`ifdef Channel_3
assign ff_tx_f_clk = ff_tx_f_clk_3;
assign ff_tx_h_clk = ff_tx_h_clk_3;
`endif
`endif
`endif
assign clk_250 = ff_tx_f_clk;
assign clk_125 = ff_tx_h_clk;
`ifdef DataWidth_8 //8-bit PIPE
assign PCLK = ff_tx_f_clk; // 250 Mhz clock
assign PCLK_by_2 = ff_tx_h_clk; // 125 Mhz clock
`else //16-bit PIPE
assign PCLK = ff_tx_h_clk; // 125 Mhz clock
`endif
// =============================================================================
// Power down unused channels when in downgrade mode and when in L0
// =============================================================================
assign pwdn = ~(PowerDown[1] & PowerDown[0]);
`ifdef X1
`ifdef Channel_0
assign ffc_pwdnb_0 = pwdn; //Active LOW
assign ffc_rrst_0 = 1'b0; //Active HIGH
`endif
`ifdef Channel_1
assign ffc_pwdnb_1 = pwdn;
assign ffc_rrst_1 = 1'b0;
`endif
`ifdef Channel_2
assign ffc_pwdnb_2 = pwdn;
assign ffc_rrst_2 = 1'b0;
`endif
`ifdef Channel_3
assign ffc_pwdnb_3 = pwdn;
assign ffc_rrst_3 = 1'b0;
`endif
`endif // X1
`ifdef X4
always @(posedge PCLK or negedge RESET_n) begin
if(!RESET_n) begin
ffc_pwdnb_0 <= 1'b1;
ffc_pwdnb_1 <= 1'b1;
ffc_pwdnb_2 <= 1'b1;
ffc_pwdnb_3 <= 1'b1;
ffc_rrst_0 <= 1'b0;
ffc_rrst_1 <= 1'b0;
ffc_rrst_2 <= 1'b0;
ffc_rrst_3 <= 1'b0;
end
else begin
ffc_pwdnb_0 <= pwdn;
ffc_pwdnb_1 <= pwdn;
ffc_pwdnb_2 <= pwdn;
ffc_pwdnb_3 <= pwdn;
if (phy_l0) begin
ffc_rrst_0 <= ~flip_phy_cfgln[3];
ffc_rrst_1 <= ~flip_phy_cfgln[2];
ffc_rrst_2 <= ~flip_phy_cfgln[1];
ffc_rrst_3 <= ~flip_phy_cfgln[0];
end
else begin
ffc_rrst_0 <= 1'b0;
ffc_rrst_1 <= 1'b0;
ffc_rrst_2 <= 1'b0;
ffc_rrst_3 <= 1'b0;
end
end
end
`endif // X4
// =============================================================================
// sync_rst generation :
// Generate LANE TX and RX reset to synchonise all the SERDES and CTC channels
// so that the any channel skew causes by delayed start of clocks are is removed
// Generate sync_rst is rst when
// when any channel LOS OF LOCK is seen, (Useful in X1 downgrade mode)
// when all channel LOS OF LOCK is seen, (Useful in X4 downgrade mode)
// =============================================================================
reg lol_all_d0 /* synthesis syn_srlstyle="registers" */;
reg lol_all_d1 /* synthesis syn_srlstyle="registers" */;
reg lol_all_d2 /* synthesis syn_srlstyle="registers" */;
reg lol_all_d3 /* synthesis syn_srlstyle="registers" */;
reg lol_all_d4 /* synthesis syn_srlstyle="registers" */;
reg lol_all_d5 /* synthesis syn_srlstyle="registers" */;
reg lol_all_d6 /* synthesis syn_srlstyle="registers" */;
reg lol_all_d7 /* synthesis syn_srlstyle="registers" */;
always @(posedge clk_250 or negedge RESET_n) begin
if(!RESET_n) begin
lol_all_d0 <= 1'b1;
lol_all_d1 <= 1'b1;
lol_all_d2 <= 1'b1;
lol_all_d3 <= 1'b1;
lol_all_d4 <= 1'b1;
lol_all_d5 <= 1'b1;
lol_all_d6 <= 1'b1;
lol_all_d7 <= 1'b1;
sync_rst <= 1'b1;
end
else begin
`ifdef X1
`ifdef Channel_0
lol_all_d0 <= rlol_rst_ch[0];
`endif
`ifdef Channel_1
lol_all_d0 <= rlol_rst_ch[1];
`endif
`ifdef Channel_2
lol_all_d0 <= rlol_rst_ch[2];
`endif
`ifdef Channel_3
lol_all_d0 <= rlol_rst_ch[3];
`endif
`endif // X1
`ifdef X4
// When all LOL goes LOW
lol_all_d0 <= rlol_rst_ch[3] | rlol_rst_ch[2] | rlol_rst_ch[1] | rlol_rst_ch[0];
`endif // X4
lol_all_d1 <= lol_all_d0;
lol_all_d2 <= lol_all_d1;
lol_all_d3 <= lol_all_d2;
lol_all_d4 <= lol_all_d3;
lol_all_d5 <= lol_all_d4;
lol_all_d6 <= lol_all_d5;
lol_all_d7 <= lol_all_d6;
sync_rst <= (~lol_all_d1 & lol_all_d7) ;
end
end
// =============================================================================
// This Option/define is Meant for Debugging with Lattice (LSV) Agilent
// Exerciser ONLY. Others don't use this define.
// =============================================================================
`ifdef EXERCISER_DEBUG
// ====================================================================
// LSV Agilent Exerciser Tx-L0 has got problem & always is in Elec Idle
// Force the RxEI Lane0/3 LOW
// ====================================================================
`ifdef X4
reg [3:0] RxElecIdle_x_in_sync1;
reg [3:0] RxElecIdle_x_in_sync2;
reg RxElecIdle_0_in_temp;
reg RxElecIdle_3_in_temp;
// ====================================================================
// For X4 : Force the RxEI Lane0/3 LOW when ALL other RxEIs are LOW
// ====================================================================
always @(posedge clk_125 or negedge RESET_n) begin
if(!RESET_n) begin
RxElecIdle_x_in_sync1 <= 4'b1111;
RxElecIdle_x_in_sync2 <= 4'b1111;
RxElecIdle_0_in_temp <= 1'b1;
RxElecIdle_3_in_temp <= 1'b1;
end
else begin
RxElecIdle_x_in_sync1 <= {RxElecIdle_3_in,RxElecIdle_2_in,RxElecIdle_1_in,RxElecIdle_0_in};
RxElecIdle_x_in_sync2 <= RxElecIdle_x_in_sync1;
if(RxElecIdle_x_in_sync2 == 4'b0001)
RxElecIdle_0_in_temp <= 1'b0;
else
RxElecIdle_0_in_temp <= RxElecIdle_x_in_sync2[0];
if(RxElecIdle_x_in_sync2 == 4'b1000) //Lane reversal for Solution Board
RxElecIdle_3_in_temp <= 1'b0;
else
RxElecIdle_3_in_temp <= RxElecIdle_x_in_sync2[3];
end
end
`endif
// ====================================================================
// For X1: Force the RxEI Lane0/3 LOW when RxValid is HIGH
// ====================================================================
`ifdef X1
reg RxElecIdle_x_in_sync1;
reg RxElecIdle_x_in_sync2;
reg RxElecIdle_0_in_temp;
reg RxElecIdle_3_in_temp;
reg RxValid_x_in_sync1;
reg RxValid_x_in_sync2;
always @(posedge clk_125 or negedge RESET_n) begin
if(!RESET_n) begin
RxElecIdle_x_in_sync1 <= 1'b1;
RxElecIdle_x_in_sync2 <= 1'b1;
RxElecIdle_0_in_temp <= 1'b1;
RxElecIdle_3_in_temp <= 1'b1;
RxValid_x_in_sync1 <= 1'b0;
RxValid_x_in_sync2 <= 1'b0;
end
else begin
`ifdef Channel_0
RxElecIdle_x_in_sync1 <= RxElecIdle_0_in;
RxElecIdle_x_in_sync2 <= RxElecIdle_x_in_sync1;
RxValid_x_in_sync1 <= RxValid_0_in;
RxValid_x_in_sync2 <= RxValid_x_in_sync1;
//RxEI & RxValid : both are HIGH
if(RxElecIdle_x_in_sync2 && RxValid_x_in_sync2)
RxElecIdle_0_in_temp <= 1'b0;
else
RxElecIdle_0_in_temp <= RxElecIdle_x_in_sync2;
`endif
`ifdef Channel_3
RxElecIdle_x_in_sync1 <= RxElecIdle_3_in;
RxElecIdle_x_in_sync2 <= RxElecIdle_x_in_sync1;
RxValid_x_in_sync1 <= RxValid_3_in;
RxValid_x_in_sync2 <= RxValid_x_in_sync1;
//RxEI & RxValid : both are HIGH
if(RxElecIdle_x_in_sync2 && RxValid_x_in_sync2)
RxElecIdle_3_in_temp <= 1'b0;
else
RxElecIdle_3_in_temp <= RxElecIdle_x_in_sync2;
`endif
end
end
`endif
`endif
// ======================= RK MODIFICATIONS START ==============================
// New signals :
// pcs_wait_done_ch0, 1,2,3 -- for Rx_valid
// rlol_ch0, 1,2,3 -- for sync_rst
// =============================================================================
// 1 MS Timer -- 18-bit : 250,000 clks (250Mhz)
// count_ms can go upto 262,144 clks (1 ms + 48 us)
// DETECT to POLLING (P1 to P0): the timer starts & after 4 MS, RxValids
// are passed.
// =============================================================================
///// inputs : pcs_wait_done
///// inputs : pcs_wait_done, start_mask, Int_RxElecIdle_ch0/1/2/3
///// outputs : RxElecIdle_ch0_8 (masked EI)
///// inputs : detsm_done
// =============================================================================
// Make Default values in case of X1
// =============================================================================
always@*
begin
// If defined, take from PCS otherwise assign default values
pcie_con_0 = 1'b0;
pcie_con_1 = 1'b0;
pcie_con_2 = 1'b0;
pcie_con_3 = 1'b0;
Int_RxElecIdle_ch0 = 1'b1;
Int_RxElecIdle_ch1 = 1'b1;
Int_RxElecIdle_ch2 = 1'b1;
Int_RxElecIdle_ch3 = 1'b1;
Int_ffs_rlol_ch0 = 1'b1;
Int_ffs_rlol_ch1 = 1'b1;
Int_ffs_rlol_ch2 = 1'b1;
Int_ffs_rlol_ch3 = 1'b1;
`ifdef Channel_0
pcie_con_0 = ffs_pcie_con_0;
`ifdef EXERCISER_DEBUG
Int_RxElecIdle_ch0 = RxElecIdle_0_in_temp;
`else
Int_RxElecIdle_ch0 = RxElecIdle_0_in;
`endif
Int_ffs_rlol_ch0 = ffs_rlol_ch0;
`endif
`ifdef Channel_1
pcie_con_1 = ffs_pcie_con_1;
Int_RxElecIdle_ch1 = RxElecIdle_1_in;
Int_ffs_rlol_ch1 = ffs_rlol_ch1;
`endif
`ifdef Channel_2
pcie_con_2 = ffs_pcie_con_2;
Int_RxElecIdle_ch2 = RxElecIdle_2_in;
Int_ffs_rlol_ch2 = ffs_rlol_ch2;
`endif
`ifdef Channel_3
pcie_con_3 = ffs_pcie_con_3;
`ifdef EXERCISER_DEBUG
Int_RxElecIdle_ch3 = RxElecIdle_3_in_temp;
`else
Int_RxElecIdle_ch3 = RxElecIdle_3_in;
`endif
Int_ffs_rlol_ch3 = ffs_rlol_ch3;
`endif
// synopsys translate_off
// PCS Sim. Model is not giving Result
pcie_con_0 = det_result[0];
pcie_con_1 = det_result[1];
pcie_con_2 = det_result[2];
pcie_con_3 = det_result[3];
// synopsys translate_on
end
// EIDet = 4'b1111 --> when ALL LANES are DETECTED & All lanes are NOT in Elec Idle
// ffs_pcie_con_0/1/2/3 are already stabilized & qualified with "detection_done"
assign EI_Det_0 = ~(RxEI_masked[0]) & pcie_con_0;
assign EI_Det_1 = ~(RxEI_masked[1]) & pcie_con_1;
assign EI_Det_2 = ~(RxEI_masked[2]) & pcie_con_2;
assign EI_Det_3 = ~(RxEI_masked[3]) & pcie_con_3;
//always @(posedge PCLK or negedge RESET_n) begin
always @(posedge clk_125 or negedge RESET_n) begin
if(!RESET_n) begin
count_ms <= 17'b00000000000000000; // 17-bits for 1 MS
count_ms_enable <= 1'b0;
num_ms <= 3'b000;
pcs_wait_done <= 1'b0;
detection_done <= 1'b0;
start_count <= 1'b0;
start_count_del <= 1'b0;
RxEI_sync <= 4'b1111;
RxEI <= 4'b1111;
RxEI_masked_sync <= 4'b1111;
RxEI_masked <= 4'b1111;
EI_low <= 4'b0000;
EI_low_pulse <= 4'b0000;
reset_counter <= 1'b0;
allEI_high <= 1'b0;
RxLOL_sync <= 4'b1111;
RxLOL <= 4'b1111;
RxLOL_del <= 4'b1111;
RxLOL_posedge <= 4'b0000;
end
else begin
//Sync.
RxLOL_sync <= {Int_ffs_rlol_ch3, Int_ffs_rlol_ch2, Int_ffs_rlol_ch1, Int_ffs_rlol_ch0};
RxLOL <= RxLOL_sync;
//For "1us Masked RxElecIdle -> RxElecIdle_ch0_8" Take PCS EI
RxEI_sync <= {Int_RxElecIdle_ch3, Int_RxElecIdle_ch2, Int_RxElecIdle_ch1, Int_RxElecIdle_ch0};
RxEI <= RxEI_sync;
//Use "Masked RxElecIdle -> RxElecIdle_ch0_8" for 4MS Mask
RxEI_masked_sync <= {RxElecIdle_ch3_8, RxElecIdle_ch2_8, RxElecIdle_ch1_8, RxElecIdle_ch0_8};
RxEI_masked <= RxEI_masked_sync;
// After COUNTER enabled, Reset conditions :
// 1) Any EI going LOW
// 2) ALL EI going HIGH
// keep reset ON until at least one EI goes LOW
// 3) Any RLOL going HIGH (qualified with corresponding EI LOW)
// 1) Any EI going LOW
// ffs_pcie_con_0/1/2/3 stable & qualified with "count_ms_enable"
EI_low[0] <= count_ms_enable & EI_Det_0;
EI_low[1] <= count_ms_enable & EI_Det_1;
EI_low[2] <= count_ms_enable & EI_Det_2;
EI_low[3] <= count_ms_enable & EI_Det_3;
// Generate "reset counter pulse" whenever EI goes on ANY channel
EI_low_pulse[0] <= ~(EI_low[0]) & count_ms_enable & EI_Det_0;
EI_low_pulse[1] <= ~(EI_low[1]) & count_ms_enable & EI_Det_1;
EI_low_pulse[2] <= ~(EI_low[2]) & count_ms_enable & EI_Det_2;
EI_low_pulse[3] <= ~(EI_low[3]) & count_ms_enable & EI_Det_3;
// 2) ALL EI going HIGH
// keep reset ON until at least one EI goes LOW
//Timer already started & then ALL EIs are HIGH
if (count_ms_enable == 1'b1 && EI_low == 4'b0000)
allEI_high <= 1'b1; // Means EI LOW gone
else
allEI_high <= 1'b0;
// 3) Any RLOL going HIGH (qualified with corresponding EI LOW)
RxLOL_del <= RxLOL;
RxLOL_posedge[0] <= EI_low[0] & RxLOL[0] & ~(RxLOL_del[0]);
RxLOL_posedge[1] <= EI_low[1] & RxLOL[1] & ~(RxLOL_del[1]);
RxLOL_posedge[2] <= EI_low[2] & RxLOL[2] & ~(RxLOL_del[2]);
RxLOL_posedge[3] <= EI_low[3] & RxLOL[3] & ~(RxLOL_del[3]);
// Reset Counter = 1 + 2 + 3
// ANY EI low pulse -OR- all EI high -OR- ANY RLOL Posedge
if ((EI_low_pulse != 4'b0000) || (allEI_high == 1'b1) || (RxLOL_posedge != 4'b0000))
reset_counter <= 1'b1;
else
reset_counter <= 1'b0;
// Any lane DETECTED & NOT in EI
//if (detsm_done == 1'b1)
//detection_done <= 1'b1
//else if (start_count == 1'b1)
//detection_done <= 1'b0;
if(detection_done == 1'b1) begin
if (start_count == 1'b1)
detection_done <= 1'b0; // change the signal name
end
else if (RxEI_masked == 4'b1111 && count_ms_enable == 1'b0)
detection_done <= 1'b1;
//Start Timer after DETECT & AT LEAST ONE Lane is not in EI
// Reset the count with any EI LOW after that
// ie counts from Last EI low
//Any lane DETECTED & NOT in EI
start_count <= detection_done & (EI_Det_0 | EI_Det_1 | EI_Det_2 | EI_Det_3);
start_count_del <= start_count;
// 1 MS Timer
if (count_ms_enable == 1'b1 && reset_counter == 1'b0)
count_ms <= count_ms + 1'b1;
else // EI gone LOW, start again
count_ms <= 17'b00000000000000000;
// 1 MS Timer Enable -- From DETECT to POLLING
// After detect pulse & then ANY EI gone ZERO
if ((start_count == 1'b1) && (start_count_del == 1'b0)) //Pulse
count_ms_enable <= 1'b1;
else if (num_ms == 3'b100) //4 MS
count_ms_enable <= 1'b0;
// No. of MS
if (count_ms == 17'b11111111111111111)
num_ms <= num_ms + 1'b1;
else if (num_ms == 3'b100) //4 MS
num_ms <= 3'b000;
// pcs_wait_done for bit lock & symbol lock
// Waiting for PCS to give stabilized RxValid
if (num_ms == 3'b100) //4 MS
pcs_wait_done <= 1'b1; // Enable passing the RX Valid
//else if (detsm_done == 1'b1)
else if (RxEI_masked == 4'b1111)
//else if (RxEI_masked == "1111" && count_ms_enable == '0')
pcs_wait_done <= 1'b0; // Disable when in DETECT
// synopsys translate_off
// 1 MS Timer ==> 8 clks Timer
if (count_ms_enable == 1'b1 && reset_counter == 1'b0)
count_ms[2:0] <= count_ms[2:0] + 1'b1;
else // EI gone LOW, start again
count_ms <= "00000000000000000";
// No. of MS
if (count_ms[2:0] == 3'b111)
num_ms <= num_ms + 1'b1;
else if (num_ms == 3'b100) //4 MS ==> 4x8=32 clks
num_ms <= 3'b000;
// synopsys translate_on
end
end
// =============================================================================
// Masking the RxEIDLE Glitch (otherside Rcvr Detction)
// =============================================================================
always @(posedge clk_125 or negedge RESET_n) begin
if(!RESET_n) begin
check <= 1'b0;
start_mask <= 1'b0;
ei_counter <= 7'b0000000;
PLOL_hsync <= 1'b1;
PLOL_hclk <= 1'b1;
end
else begin
// Sync.
PLOL_hsync <= ffs_plol;
PLOL_hclk <= PLOL_hsync;
if (PLOL_hclk == 1'b0) begin
if (RxEI == 4'b1111)
check <= 1'b1;
if (ei_counter == 7'b1111111) begin // 128 clks (1us)
start_mask <= 1'b0;
check <= 1'b0;
end
else if (check == 1'b1 && RxEI != 4'b1111) // Any lane goes low
start_mask <= 1'b1;
// synopsys translate_off
if (ei_counter[2:0] == 3'b111) begin // 7 clks (1us)
start_mask <= 1'b0;
check <= 1'b0;
end
else if (check == 1'b1 && RxEI != 4'b1111) // Any lane goes low
start_mask <= 1'b1;
// synopsys translate_on
end
else begin
check <= 1'b0;
start_mask <= 1'b0;
end
if(start_mask == 1'b1)
ei_counter <= ei_counter + 1'b1;
else
ei_counter <= 7'b0000000;
end
end
// =============================================================================
// Sync_rst generation :
// Qualify the RLOL with RxElecIdle
// PCS RLOL is toggling even when ElecIdle is asserted
// No data during this time
// =============================================================================
always @(posedge clk_250 or negedge RESET_n) begin
if(!RESET_n) begin
rlol_sync <= 4'b1111;
rx_elec <= 4'b1111;
rlol_fclk <= 4'b1111;
rlol_rst_ch <= 4'b1111; //RLOL qualifed with EI
end
else begin
// Use Masked RxElecIdle
rx_elec <= {RxElecIdle_ch3_8, RxElecIdle_ch2_8, RxElecIdle_ch1_8, RxElecIdle_ch0_8};
//Sync
rlol_sync <= {Int_ffs_rlol_ch3, Int_ffs_rlol_ch2, Int_ffs_rlol_ch1, Int_ffs_rlol_ch0};
rlol_fclk <= rlol_sync;
// Combine LOL and ElecIdle for sync_rst
rlol_rst_ch[0] <= rlol_fclk[0] | rx_elec[0];
rlol_rst_ch[1] <= rlol_fclk[1] | rx_elec[1];
rlol_rst_ch[2] <= rlol_fclk[2] | rx_elec[2];
rlol_rst_ch[3] <= rlol_fclk[3] | rx_elec[3];
end
end
// ======================= RK MODIFICATIONS END ===============================
// =============================================================================
// pipe_top instantiation per channel
// =============================================================================
`ifdef Channel_0
rc_pipe_top pipe_top_0(
.RESET_n (RESET_n) ,
.PCLK (PCLK) ,
.clk_250 (clk_250),
.ffs_plol (ffs_plol) ,
.TxDetectRx_Loopback (TxDetectRx_Loopback) ,
.PowerDown (PowerDown) ,
.ctc_disable (ctc_disable),
.TxData_in (flip_TxData_0) ,
.TxDataK_in (flip_TxDataK_0) ,
.TxElecIdle_in (flip_TxElecIdle_0) ,
.RxPolarity_in (flip_RxPolarity_0) ,
.RxData_in (RxData_0_in) ,
.RxDataK_in (RxDataK_0_in) ,
.RxStatus_in (RxStatus_0_in) ,
.RxValid_in (RxValid_0_in) ,
.RxElecIdle_in (Int_RxElecIdle_ch0) ,
.ff_rx_fclk_chx (ff_rx_fclk_0) ,
.pcie_con_x (pcie_con_0),
.pcs_wait_done (pcs_wait_done), //RK NEW
.start_mask (start_mask), //RK NEW
.detsm_done (detsm_done), //RK NEW
.RxElecIdle_chx_8 (RxElecIdle_ch0_8), //RK NEW
.TxData_out (TxData_0_out) ,
.TxDataK_out (TxDataK_0_out) ,
.TxElecIdle_out (TxElecIdle_0_out) , //RK NEW
.RxPolarity_out (RxPolarity_0_out) ,
.RxData_out (flip_RxData_0) ,
.RxDataK_out (flip_RxDataK_0) ,
.RxStatus_out (flip_RxStatus_0) ,
.RxValid_out (flip_RxValid_0) ,
.RxElecIdle_out (flip_RxElecIdle_0) ,
.ffc_fb_loopback (ffc_fb_loopback_0)
);
`endif
`ifdef Channel_1
rc_pipe_top pipe_top_1(
.RESET_n (RESET_n) ,
.PCLK (PCLK) ,
.clk_250 (clk_250),
.ffs_plol (ffs_plol) ,
.TxDetectRx_Loopback (TxDetectRx_Loopback) ,
.PowerDown (PowerDown) ,
.ctc_disable (ctc_disable),
.TxData_in (flip_TxData_1) ,
.TxDataK_in (flip_TxDataK_1) ,
.TxElecIdle_in (flip_TxElecIdle_1) ,
.RxPolarity_in (flip_RxPolarity_1) ,
.RxData_in (RxData_1_in) ,
.RxDataK_in (RxDataK_1_in) ,
.RxStatus_in (RxStatus_1_in) ,
.RxValid_in (RxValid_1_in) ,
.RxElecIdle_in (Int_RxElecIdle_ch1) ,
.ff_rx_fclk_chx (ff_rx_fclk_1) ,
.pcie_con_x (pcie_con_1),
.pcs_wait_done (pcs_wait_done),
.start_mask (start_mask),
.detsm_done (detsm_done),
.RxElecIdle_chx_8 (RxElecIdle_ch1_8),
.TxData_out (TxData_1_out) ,
.TxDataK_out (TxDataK_1_out) ,
.TxElecIdle_out (TxElecIdle_1_out) ,
.RxPolarity_out (RxPolarity_1_out) ,
.RxData_out (flip_RxData_1) ,
.RxDataK_out (flip_RxDataK_1) ,
.RxStatus_out (flip_RxStatus_1) ,
.RxValid_out (flip_RxValid_1) ,
.RxElecIdle_out (flip_RxElecIdle_1) ,
.ffc_fb_loopback (ffc_fb_loopback_1)
);
`endif
`ifdef Channel_2
rc_pipe_top pipe_top_2(
.RESET_n (RESET_n) ,
.PCLK (PCLK) ,
.clk_250 (clk_250),
.ffs_plol (ffs_plol) ,
.TxDetectRx_Loopback (TxDetectRx_Loopback) ,
.PowerDown (PowerDown) ,
.ctc_disable (ctc_disable),
.TxData_in (flip_TxData_2) ,
.TxDataK_in (flip_TxDataK_2) ,
.TxElecIdle_in (flip_TxElecIdle_2) ,
.RxPolarity_in (flip_RxPolarity_2) ,
.RxData_in (RxData_2_in) ,
.RxDataK_in (RxDataK_2_in) ,
.RxStatus_in (RxStatus_2_in) ,
.RxValid_in (RxValid_2_in) ,
.RxElecIdle_in (Int_RxElecIdle_ch2) ,
.ff_rx_fclk_chx (ff_rx_fclk_2) ,
.pcie_con_x (pcie_con_2),
.pcs_wait_done (pcs_wait_done),
.start_mask (start_mask),
.detsm_done (detsm_done),
.RxElecIdle_chx_8 (RxElecIdle_ch2_8),
.TxData_out (TxData_2_out) ,
.TxDataK_out (TxDataK_2_out) ,
.TxElecIdle_out (TxElecIdle_2_out) ,
.RxPolarity_out (RxPolarity_2_out) ,
.RxData_out (flip_RxData_2) ,
.RxDataK_out (flip_RxDataK_2) ,
.RxStatus_out (flip_RxStatus_2) ,
.RxValid_out (flip_RxValid_2) ,
.RxElecIdle_out (flip_RxElecIdle_2) ,
.ffc_fb_loopback (ffc_fb_loopback_2)
);
`endif
`ifdef Channel_3
rc_pipe_top pipe_top_3(
.RESET_n (RESET_n) ,
.PCLK (PCLK) ,
.clk_250 (clk_250),
.ffs_plol (ffs_plol) ,
.TxDetectRx_Loopback (TxDetectRx_Loopback) ,
.PowerDown (PowerDown) ,
.ctc_disable (ctc_disable),
.TxData_in (flip_TxData_3) ,
.TxDataK_in (flip_TxDataK_3) ,
.TxElecIdle_in (flip_TxElecIdle_3) ,
.RxPolarity_in (flip_RxPolarity_3) ,
.RxData_in (RxData_3_in) ,
.RxDataK_in (RxDataK_3_in) ,
.RxStatus_in (RxStatus_3_in) ,
.RxValid_in (RxValid_3_in) ,
.RxElecIdle_in (Int_RxElecIdle_ch3) ,
.ff_rx_fclk_chx (ff_rx_fclk_3) ,
.pcie_con_x (pcie_con_3),
.pcs_wait_done (pcs_wait_done),
.start_mask (start_mask),
.detsm_done (detsm_done),
.RxElecIdle_chx_8 (RxElecIdle_ch3_8),
.TxData_out (TxData_3_out) ,
.TxDataK_out (TxDataK_3_out) ,
.TxElecIdle_out (TxElecIdle_3_out) ,
.RxPolarity_out (RxPolarity_3_out) ,
.RxData_out (flip_RxData_3) ,
.RxDataK_out (flip_RxDataK_3) ,
.RxStatus_out (flip_RxStatus_3) ,
.RxValid_out (flip_RxValid_3) ,
.RxElecIdle_out (flip_RxElecIdle_3) ,
.ffc_fb_loopback (ffc_fb_loopback_3)
);
`endif
// =============================================================================
// pcs_top instantiation
// =============================================================================
rc_pcs_top pcs_top_0 (
// Common for all 4 Channels
// Resets
.ffc_lane_tx_rst (ffc_lane_tx_rst) ,
.ffc_lane_rx_rst (ffc_lane_rx_rst) ,
.ffc_trst (ffc_trst) ,
.ffc_quad_rst (ffc_quad_rst) ,
.ffc_macro_rst (ffc_macro_rst) ,
// Clocks
.refclkp (refclkp) ,
.refclkn (refclkn) ,
//.PCLK (PCLK) , --RK
.PCLK (ff_tx_f_clk) ,
`ifdef ECP3
`ifdef Channel_0
.ff_tx_f_clk_0 (ff_tx_f_clk_0) ,
.ff_tx_h_clk_0 (ff_tx_h_clk_0) ,
`endif
`ifdef Channel_1
.ff_tx_f_clk_1 (ff_tx_f_clk_1) ,
.ff_tx_h_clk_1 (ff_tx_h_clk_1) ,
`endif
`ifdef Channel_2
.ff_tx_f_clk_2 (ff_tx_f_clk_2) ,
.ff_tx_h_clk_2 (ff_tx_h_clk_2) ,
`endif
`ifdef Channel_3
.ff_tx_f_clk_3 (ff_tx_f_clk_3) ,
.ff_tx_h_clk_3 (ff_tx_h_clk_3) ,
`endif
`else
.ff_tx_f_clk (ff_tx_f_clk) ,
.ff_tx_h_clk (ff_tx_h_clk) ,
`endif
.ffc_signal_detect (ffc_signal_detect) ,
.ffc_enb_cgalign (ffc_enb_cgalign) ,
.ffs_plol (ffs_plol) ,
// SCI Interface
.sciwstn (sciwstn) ,
.sciwritedata (sciwritedata),
.sciaddress (sciaddress) ,
.scienaux (scienaux) ,
.sciselaux (sciselaux) ,
.scird (scird) ,
.scireaddata (scireaddata) ,
`ifdef Channel_0
.hdinp0 (hdinp0) ,
.hdinn0 (hdinn0) ,
.TxData_ch0 (TxData_0_out) ,
.TxDataK_ch0 (TxDataK_0_out) ,
.TxCompliance_ch0 (flip_TxCompliance_0) ,
//.TxElecIdle_ch0 (flip_TxElecIdle_0) , //RK
.TxElecIdle_ch0 (TxElecIdle_0_out),
.ffc_txpwdnb_0 (ffc_pwdnb_0) ,
.ffc_rxpwdnb_0 (ffc_pwdnb_0) ,
.ffc_rrst_ch0 (ffc_rrst_0) ,
.ffc_pcie_ct_ch0 (ffc_pcie_ct) ,
.ffc_pcie_det_en_ch0 (ffc_pcie_det_en_0) ,
.ffc_fb_loopback_ch0 (ffc_fb_loopback_0) ,
.RxPolarity_ch0 (RxPolarity_0_out) ,
.scisel_ch0 (flip_scisel_0) ,
.scien_ch0 (flip_scien_0) ,
.ff_rx_fclk_ch0 (ff_rx_fclk_0) ,
.hdoutp0 (hdoutp0) ,
.hdoutn0 (hdoutn0) ,
.RxData_ch0 (RxData_0_in) ,
.RxDataK_ch0 (RxDataK_0_in) ,
.RxStatus_ch0 (RxStatus_0_in) ,
.RxValid_ch0 (RxValid_0_in) ,
.RxElecIdle_ch0 (RxElecIdle_0_in) ,
.ffs_rlol_ch0 (ffs_rlol_ch0) ,
.ffs_pcie_done_0 (ffs_pcie_done_0) ,
.ffs_pcie_con_0 (ffs_pcie_con_0) ,
`endif
`ifdef Channel_1
.hdinp1 (hdinp1) ,
.hdinn1 (hdinn1) ,
.TxData_ch1 (TxData_1_out) ,
.TxDataK_ch1 (TxDataK_1_out) ,
.TxCompliance_ch1 (flip_TxCompliance_1) ,
.TxElecIdle_ch1 (TxElecIdle_1_out),
.ffc_txpwdnb_1 (ffc_pwdnb_1) ,
.ffc_rxpwdnb_1 (ffc_pwdnb_1) ,
.ffc_rrst_ch1 (ffc_rrst_1) ,
.ffc_pcie_ct_ch1 (ffc_pcie_ct) ,
.ffc_pcie_det_en_ch1 (ffc_pcie_det_en_1) ,
.ffc_fb_loopback_ch1 (ffc_fb_loopback_1) ,
.RxPolarity_ch1 (RxPolarity_1_out) ,
.scisel_ch1 (flip_scisel_1) ,
.scien_ch1 (flip_scien_1) ,
.ff_rx_fclk_ch1 (ff_rx_fclk_1) ,
.hdoutp1 (hdoutp1) ,
.hdoutn1 (hdoutn1) ,
.RxData_ch1 (RxData_1_in) ,
.RxDataK_ch1 (RxDataK_1_in) ,
.RxStatus_ch1 (RxStatus_1_in) ,
.RxValid_ch1 (RxValid_1_in) ,
.RxElecIdle_ch1 (RxElecIdle_1_in) ,
.ffs_rlol_ch1 (ffs_rlol_ch1) ,
.ffs_pcie_done_1 (ffs_pcie_done_1) ,
.ffs_pcie_con_1 (ffs_pcie_con_1) ,
`endif
`ifdef Channel_2
.hdinp2 (hdinp2) ,
.hdinn2 (hdinn2) ,
.TxData_ch2 (TxData_2_out) ,
.TxDataK_ch2 (TxDataK_2_out) ,
.TxCompliance_ch2 (flip_TxCompliance_2) ,
.TxElecIdle_ch2 (TxElecIdle_2_out),
.ffc_txpwdnb_2 (ffc_pwdnb_2) ,
.ffc_rxpwdnb_2 (ffc_pwdnb_2) ,
.ffc_rrst_ch2 (ffc_rrst_2) ,
.ffc_pcie_ct_ch2 (ffc_pcie_ct) ,
.ffc_pcie_det_en_ch2 (ffc_pcie_det_en_2) ,
.ffc_fb_loopback_ch2 (ffc_fb_loopback_2) ,
.RxPolarity_ch2 (RxPolarity_2_out) ,
.scisel_ch2 (flip_scisel_2) ,
.scien_ch2 (flip_scien_2) ,
.ff_rx_fclk_ch2 (ff_rx_fclk_2) ,
.hdoutp2 (hdoutp2) ,
.hdoutn2 (hdoutn2) ,
.RxData_ch2 (RxData_2_in) ,
.RxDataK_ch2 (RxDataK_2_in) ,
.RxStatus_ch2 (RxStatus_2_in) ,
.RxValid_ch2 (RxValid_2_in) ,
.RxElecIdle_ch2 (RxElecIdle_2_in) ,
.ffs_rlol_ch2 (ffs_rlol_ch2) ,
.ffs_pcie_done_2 (ffs_pcie_done_2) ,
.ffs_pcie_con_2 (ffs_pcie_con_2) ,
`endif
`ifdef Channel_3
.hdinp3 (hdinp3) ,
.hdinn3 (hdinn3) ,
.TxData_ch3 (TxData_3_out) ,
.TxDataK_ch3 (TxDataK_3_out) ,
.TxCompliance_ch3 (flip_TxCompliance_3) ,
.TxElecIdle_ch3 (TxElecIdle_3_out),
.ffc_txpwdnb_3 (ffc_pwdnb_3) ,
.ffc_rxpwdnb_3 (ffc_pwdnb_3) ,
.ffc_rrst_ch3 (ffc_rrst_3) ,
.ffc_pcie_ct_ch3 (ffc_pcie_ct) ,
.ffc_pcie_det_en_ch3 (ffc_pcie_det_en_3) ,
.ffc_fb_loopback_ch3 (ffc_fb_loopback_3) ,
.RxPolarity_ch3 (RxPolarity_3_out) ,
.scisel_ch3 (flip_scisel_3) ,
.scien_ch3 (flip_scien_3) ,
.ff_rx_fclk_ch3 (ff_rx_fclk_3) ,
.hdoutp3 (hdoutp3) ,
.hdoutn3 (hdoutn3) ,
.RxData_ch3 (RxData_3_in) ,
.RxDataK_ch3 (RxDataK_3_in) ,
.RxStatus_ch3 (RxStatus_3_in) ,
.RxValid_ch3 (RxValid_3_in) ,
.RxElecIdle_ch3 (RxElecIdle_3_in) ,
.ffs_rlol_ch3 (ffs_rlol_ch3) ,
.ffs_pcie_done_3 (ffs_pcie_done_3) ,
.ffs_pcie_con_3 (ffs_pcie_con_3) ,
`endif
.cin (cin) ,
.cout (cout)
);
// =============================================================================
// Enable detect signal for detect statemachine
// =============================================================================
assign enable_det_int = (PowerDown == 2'b10) & TxDetectRx_Loopback ;
`ifdef X4
assign enable_det_all = (enable_det_int & flip_TxElecIdle_0 & flip_TxElecIdle_1 &
flip_TxElecIdle_2 & flip_TxElecIdle_3) ? 1'b1 : 1'b0;
`endif
// =============================================================================
//Assert enable det as long as TxDetectRx_Loopback is asserted by FPGA side
//when Serdes is in normal mode and TxElecIdle_ch0/1/2/3 is active.
// =============================================================================
always @(posedge PCLK or negedge RESET_n) begin //PIPE signals : Use hclk -- RK
if(!RESET_n) begin
enable_det_ch0 <= 1'b0;
enable_det_ch1 <= 1'b0;
enable_det_ch2 <= 1'b0;
enable_det_ch3 <= 1'b0;
detect_req <= 1'b0;
detect_req_del <= 1'b0;
end
else begin
`ifdef X1
`ifdef Channel_0
enable_det_ch0 <= (enable_det_int & flip_TxElecIdle_0) ? 1'b1 : 1'b0;
detect_req <= enable_det_ch0;
`endif
`ifdef Channel_1
enable_det_ch1 <= (enable_det_int & flip_TxElecIdle_1) ? 1'b1 : 1'b0;
detect_req <= enable_det_ch1;
`endif
`ifdef Channel_2
enable_det_ch2 <= (enable_det_int & flip_TxElecIdle_2) ? 1'b1 : 1'b0;
detect_req <= enable_det_ch2;
`endif
`ifdef Channel_3
enable_det_ch3 <= (enable_det_int & flip_TxElecIdle_3) ? 1'b1 : 1'b0;
detect_req <= enable_det_ch3;
`endif
`endif // X1
`ifdef X4
enable_det_ch0 <= enable_det_all ;
enable_det_ch1 <= enable_det_all ;
enable_det_ch2 <= enable_det_all ;
enable_det_ch3 <= enable_det_all ;
detect_req <= enable_det_ch0 & enable_det_ch1 & enable_det_ch2 & enable_det_ch3;
`endif // X4
detect_req_del <= detect_req; // For Rising Edge
end
end
// Use Flopped signals to see raising edge to remove any setup issues for
// data comming from PCS
assign done_0_re = (done_0_d0 & !done_0_d1);
assign done_1_re = (done_1_d0 & !done_1_d1);
assign done_2_re = (done_2_d0 & !done_2_d1);
assign done_3_re = (done_3_d0 & !done_3_d1);
assign done_all_re = done_all & !done_all_reg;
// =============================================================================
// The Following state machine generates the "ffc_pcie_det_done" and
// "ffc_pcie_ct" as per T-Spec page 81.
// =============================================================================
always @(posedge PCLK or negedge RESET_n) begin //125 or 250 Mhz
if (!RESET_n) begin
detsm_done <= 0;
ffc_pcie_ct <= 0;
ffc_pcie_det_en_0 <= 0;
ffc_pcie_det_en_1 <= 0;
ffc_pcie_det_en_2 <= 0;
ffc_pcie_det_en_3 <= 0;
cs_reqdet_sm <= PCIE_DET_IDLE;
cnt_enable <= 1'b0;
done_0_reg <= 1'b0;
done_0_d0 <= 1'b0;
done_0_d1 <= 1'b0;
done_1_reg <= 1'b0;
done_1_d0 <= 1'b0;
done_1_d1 <= 1'b0;
done_2_reg <= 1'b0;
done_2_d0 <= 1'b0;
done_2_d1 <= 1'b0;
done_3_reg <= 1'b0;
done_3_d0 <= 1'b0;
done_3_d1 <= 1'b0;
done_all <= 1'b0;
done_all_reg <= 1'b0;
det_result <= 0; // Only for RTL sim
end
else begin
// Sync the async signal from PCS (dont use _reg signals)
`ifdef Channel_0
done_0_reg <= ffs_pcie_done_0;
done_0_d0 <= done_0_reg;
done_0_d1 <= done_0_d0;
`endif
`ifdef Channel_1
done_1_reg <= ffs_pcie_done_1;
done_1_d0 <= done_1_reg;
done_1_d1 <= done_1_d0;
`endif
`ifdef Channel_2
done_2_reg <= ffs_pcie_done_2;
done_2_d0 <= done_2_reg;
done_2_d1 <= done_2_d0;
`endif
`ifdef Channel_3
done_3_reg <= ffs_pcie_done_3;
done_3_d0 <= done_3_reg;
done_3_d1 <= done_3_d0;
`endif
done_all_reg <= done_all;
`ifdef X4
done_all <= done_0_d1 & done_1_d1 & done_2_d1 & done_3_d1;
`endif
`ifdef X1
`ifdef Channel_0
done_all <= done_0_d1;
`endif
`ifdef Channel_1
done_all <= done_1_d1;
`endif
`ifdef Channel_2
done_all <= done_2_d1;
`endif
`ifdef Channel_3
done_all <= done_3_d1;
`endif
`endif
case(cs_reqdet_sm) //----- Wait for Det Request
PCIE_DET_IDLE: begin
ffc_pcie_det_en_0 <= 1'b0;
ffc_pcie_det_en_1 <= 1'b0;
ffc_pcie_det_en_2 <= 1'b0;
ffc_pcie_det_en_3 <= 1'b0;
ffc_pcie_ct <= 1'b0;
cnt_enable <= 1'b0;
detsm_done <= 1'b0;
// Rising Edge of Det Request
if (detect_req == 1'b1 && detect_req_del == 1'b0) begin
cs_reqdet_sm <= PCIE_DET_EN;
ffc_pcie_det_en_0 <= 1'b1;
ffc_pcie_det_en_1 <= 1'b1;
ffc_pcie_det_en_2 <= 1'b1;
ffc_pcie_det_en_3 <= 1'b1;
cnt_enable <= 1'b1;
end
end
// Wait for 120 Ns
PCIE_DET_EN: begin
if (cntdone_en) begin
cs_reqdet_sm <= PCIE_CT;
ffc_pcie_ct <= 1'b1;
//cnt_enable <= 1'b0; //Reset the counter
end
end
// Wait for 4 Byte Clocks
PCIE_CT: begin
//cnt_enable <= 1'b1; // Enable for Count 2
if (cntdone_ct) begin
cs_reqdet_sm <= PCIE_DONE;
ffc_pcie_ct <= 1'b0;
end
// synopsys translate_off
det_result <= 4'b0000;
// synopsys translate_on
end
// Wait for done to go high for all channels
PCIE_DONE: begin
cnt_enable <= 1'b0;
// ALL DONEs are asserted (Rising Edge)
if (done_all_re) begin //pulse
cs_reqdet_sm <= PCIE_DET_IDLE;
detsm_done <= 1'b1;
end
// DONE makes det_en ZERO individually (DONE Rising Edge)
if (done_0_re) begin //pulse
ffc_pcie_det_en_0 <= 1'b0;
// synopsys translate_off
det_result[0] <= 1'b1;
// synopsys translate_on
end
if (done_1_re) begin //pulse
ffc_pcie_det_en_1 <= 1'b0;
// synopsys translate_off
det_result[1] <= 1'b1;
// synopsys translate_on
end
if (done_2_re) begin //pulse
ffc_pcie_det_en_2 <= 1'b0;
// synopsys translate_off
det_result[2] <= 1'b1;
// synopsys translate_on
end
if (done_3_re) begin //pulse
ffc_pcie_det_en_3 <= 1'b0;
// synopsys translate_off
det_result[3] <= 1'b1;
// synopsys translate_on
end
end
endcase
end
end
always @(posedge PCLK or negedge RESET_n) begin //125 or 250 Mhz
if(!RESET_n) begin
detsm_cnt <= 'd0;
cntdone_en <= 1'b0;
cntdone_ct <= 1'b0;
end
else begin
// Detect State machine Counter
if (cnt_enable)
detsm_cnt <= detsm_cnt + 1'b1;
else
detsm_cnt <= 0;
// pcie_det_en time
if (detsm_cnt == ONE_US) // 1 us
cntdone_en <= 1'b1;
else
cntdone_en <= 1'b0;
// pcie_ct time
if (detsm_cnt == ONE_US_4BYTE) // 2 clks = 16 ns -> 4 byte clks
cntdone_ct <= 1'b1;
else
cntdone_ct <= 1'b0;
// synopsys translate_off
// pcie_det_en time -- after 16 clks
if (detsm_cnt[4:0] == 5'b10000) // 1 us --> 16 clks
cntdone_en <= 1'b1;
else
cntdone_en <= 1'b0;
// pcie_ct time -- after 19 clks
if (detsm_cnt[4:0] == 5'b10011) // 2 clks = 16 ns -> 4 byte clks
cntdone_ct <= 1'b1;
else
cntdone_ct <= 1'b0;
// synopsys translate_on
end
end
// =============================================================================
// PhyStatus Generation - Det Result and State Changes
// =============================================================================
always @(posedge PCLK or negedge RESET_n) begin //125 or 250 Mhz
if(!RESET_n) begin
PhyStatus <= 1'b1;
PowerDown_reg <= 2'b00;
PLOL_sync <= 1'b1;
PLOL_pclk <= 1'b1;
end
else begin
// Sync.
PLOL_sync <= ffs_plol;
PLOL_pclk <= PLOL_sync;
PowerDown_reg <= PowerDown;
if (PLOL_pclk == 1'b0) begin // wait for PLL LOCK
if ((PowerDown_reg == 2'b00 && PowerDown == 2'b11) ||
(PowerDown_reg == 2'b11 && PowerDown == 2'b10) ||
(PowerDown_reg == 2'b00 && PowerDown == 2'b01) ||
(PowerDown_reg == 2'b01 && PowerDown == 2'b00) ||
(PowerDown_reg == 2'b00 && PowerDown == 2'b10) ||
(PowerDown_reg == 2'b10 && PowerDown == 2'b00) ||
(detsm_done == 1'b1))
PhyStatus <= 1'b1;
else
PhyStatus <= 1'b0;
end
end
end
endmodule
|
`timescale 1ns / 1ps
module KEYBOARD (ROW, KEY_BUFFER, PRESS_VALID, COLUMN, reset, circuit_clk, clk);
input clk, circuit_clk;
input reset;
input [3:0] COLUMN;
output [3:0] ROW;
output [3:0] KEY_BUFFER;
output PRESS_VALID;
reg [3:0] ROW;
reg [3:0] DEBOUNCE_COUNT;
reg [3:0] SCAN_CODE;
reg [4:0] KEY_CODE;
reg [3:0] KEY_BUFFER;
reg PRESS;
wire PRESS_VALID;
/***************************
* Scanning Code Generator *
***************************/
always @(posedge clk or negedge reset)
begin
if (!reset)
SCAN_CODE <= 4'h0;
else if (PRESS)
SCAN_CODE <= SCAN_CODE + 1;
end
/*********************
* Scanning Keyboard *
*********************/
always @(SCAN_CODE or COLUMN)
begin
case (SCAN_CODE[3:2])
2'b00 : ROW = 4'b1110;
2'b01 : ROW = 4'b1101;
2'b10 : ROW = 4'b1011;
2'b11 : ROW = 4'b0111;
endcase
case (SCAN_CODE[1:0])
2'b00 : PRESS = COLUMN[0];
2'b01 : PRESS = COLUMN[1];
2'b10 : PRESS = COLUMN[2];
2'b11 : PRESS = COLUMN[3];
endcase
end
/********************
* Debounce Circuit *
********************/
always @(posedge circuit_clk or negedge reset)
begin
if (!reset)
DEBOUNCE_COUNT <= 4'h0;
else if (PRESS)
DEBOUNCE_COUNT <= 4'h0;
else if (DEBOUNCE_COUNT <= 4'hE)
DEBOUNCE_COUNT <= DEBOUNCE_COUNT + 1;
end
assign PRESS_VALID = (DEBOUNCE_COUNT == 4'hD) ?
1'b1 : 1'b0;
/******************
* Fetch Key Code *
******************/
always @(negedge circuit_clk or negedge reset)
begin
if (!reset)
KEY_CODE <= 5'b10000;
else if (PRESS_VALID)
KEY_CODE <= {1'b0,SCAN_CODE};
else
KEY_CODE <= 5'b10000;
end
/********************************
* Convert Key Code Into Number *
********************************/
always @(KEY_CODE)
begin
case (KEY_CODE)
{1'b0,4'hC} : KEY_BUFFER = 4'h0; // 0
{1'b0,4'hD} : KEY_BUFFER = 4'h1; // 1
{1'b0,4'h9} : KEY_BUFFER = 4'h2; // 2
{1'b0,4'h5} : KEY_BUFFER = 4'h3; // 3
{1'b0,4'hE} : KEY_BUFFER = 4'h4; // 4
{1'b0,4'hA} : KEY_BUFFER = 4'h5; // 5
{1'b0,4'h6} : KEY_BUFFER = 4'h6; // 6
{1'b0,4'hF} : KEY_BUFFER = 4'h7; // 7
{1'b0,4'hB} : KEY_BUFFER = 4'h8; // 8
{1'b0,4'h7} : KEY_BUFFER = 4'h9; // 9
{1'b0,4'h8} : KEY_BUFFER = 4'hA; // A
{1'b0,4'h4} : KEY_BUFFER = 4'hB; // B
{1'b0,4'h3} : KEY_BUFFER = 4'hC; // C
{1'b0,4'h2} : KEY_BUFFER = 4'hD; // D
{1'b0,4'h1} : KEY_BUFFER = 4'hE; // E
{1'b0,4'h0} : KEY_BUFFER = 4'hF; // F
default: KEY_BUFFER = 4'h0;
endcase
end
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Virtex-6 Integrated Block for PCI Express
// File : pcie_bram_top_v6.v
// Version : 2.3
//--
//-- Description: BlockRAM top level module for Virtex6 PCIe Block
//--
//--
//--
//--------------------------------------------------------------------------------
`timescale 1ns/1ns
module pcie_bram_top_v6
#(
parameter DEV_CAP_MAX_PAYLOAD_SUPPORTED = 0,
parameter VC0_TX_LASTPACKET = 31,
parameter TLM_TX_OVERHEAD = 24,
parameter TL_TX_RAM_RADDR_LATENCY = 1,
parameter TL_TX_RAM_RDATA_LATENCY = 2,
parameter TL_TX_RAM_WRITE_LATENCY = 1,
parameter VC0_RX_LIMIT = 'h1FFF,
parameter TL_RX_RAM_RADDR_LATENCY = 1,
parameter TL_RX_RAM_RDATA_LATENCY = 2,
parameter TL_RX_RAM_WRITE_LATENCY = 1
)
(
input user_clk_i,
input reset_i,
input mim_tx_wen,
input [12:0] mim_tx_waddr,
input [71:0] mim_tx_wdata,
input mim_tx_ren,
input mim_tx_rce,
input [12:0] mim_tx_raddr,
output [71:0] mim_tx_rdata,
input mim_rx_wen,
input [12:0] mim_rx_waddr,
input [71:0] mim_rx_wdata,
input mim_rx_ren,
input mim_rx_rce,
input [12:0] mim_rx_raddr,
output [71:0] mim_rx_rdata
);
// TX calculations
localparam MPS_BYTES = ((DEV_CAP_MAX_PAYLOAD_SUPPORTED == 0) ? 128 :
(DEV_CAP_MAX_PAYLOAD_SUPPORTED == 1) ? 256 :
(DEV_CAP_MAX_PAYLOAD_SUPPORTED == 2) ? 512 :
1024 );
localparam BYTES_TX = (VC0_TX_LASTPACKET + 1) * (MPS_BYTES + TLM_TX_OVERHEAD);
localparam ROWS_TX = 1;
localparam COLS_TX = ((BYTES_TX <= 4096) ? 1 :
(BYTES_TX <= 8192) ? 2 :
(BYTES_TX <= 16384) ? 4 :
(BYTES_TX <= 32768) ? 8 :
18
);
// RX calculations
localparam ROWS_RX = 1;
localparam COLS_RX = ((VC0_RX_LIMIT < 'h0200) ? 1 :
(VC0_RX_LIMIT < 'h0400) ? 2 :
(VC0_RX_LIMIT < 'h0800) ? 4 :
(VC0_RX_LIMIT < 'h1000) ? 8 :
18
);
initial begin
$display("[%t] %m ROWS_TX %0d COLS_TX %0d", $time, ROWS_TX, COLS_TX);
$display("[%t] %m ROWS_RX %0d COLS_RX %0d", $time, ROWS_RX, COLS_RX);
end
pcie_brams_v6 #(.NUM_BRAMS (COLS_TX),
.RAM_RADDR_LATENCY(TL_TX_RAM_RADDR_LATENCY),
.RAM_RDATA_LATENCY(TL_TX_RAM_RDATA_LATENCY),
.RAM_WRITE_LATENCY(TL_TX_RAM_WRITE_LATENCY))
pcie_brams_tx
(
.user_clk_i(user_clk_i),
.reset_i(reset_i),
.waddr(mim_tx_waddr),
.wen(mim_tx_wen),
.ren(mim_tx_ren),
.rce(mim_tx_rce),
.wdata(mim_tx_wdata),
.raddr(mim_tx_raddr),
.rdata(mim_tx_rdata)
);
pcie_brams_v6 #(.NUM_BRAMS (COLS_RX),
.RAM_RADDR_LATENCY(TL_RX_RAM_RADDR_LATENCY),
.RAM_RDATA_LATENCY(TL_RX_RAM_RDATA_LATENCY),
.RAM_WRITE_LATENCY(TL_RX_RAM_WRITE_LATENCY))
pcie_brams_rx
(
.user_clk_i(user_clk_i),
.reset_i(reset_i),
.waddr(mim_rx_waddr),
.wen(mim_rx_wen),
.ren(mim_rx_ren),
.rce(mim_rx_rce),
.wdata(mim_rx_wdata),
.raddr(mim_rx_raddr),
.rdata(mim_rx_rdata)
);
endmodule // pcie_bram_top
|
//==================================================================================================
// Filename : uart.v
// Created On : 2015-01-09 07:45:55
// Last Modified : 2015-05-24 21:07:29
// Revision :
// Author : Angel Terrones
// Company : Universidad Simón Bolívar
// Email : [email protected]
//
// Description : UART module. Configuration: 115200, 8N1. No flow control
// With slave port.
// Based on the Rx module from XUM project.
// Author: Grant Ayers ([email protected])
//==================================================================================================
module uart(
input clk,
input rst,
// Bus I/O
input [2:0] uart_address, // Address
input [7:0] uart_data_i, // Data from bus
input uart_wr, // Byte select
input uart_enable, // Enable operation
output reg [7:0] uart_data_o, // Data to bus
output reg uart_ready, // Ready operation
// Interrupt: Data available in Rx fifo
output uart_rx_ready_int, //
output uart_rx_full_int, //
// Off chip I/O
input uart_rx, // Rx pin
output uart_tx // Tx pin
);
//--------------------------------------------------------------------------
// "local variables": FIFO size and address of registers
//--------------------------------------------------------------------------
localparam DATA_WIDTH = 8; // Bit-width of FIFO data (should be 8)
localparam ADDR_WIDTH = 8; // 2^ADDR_WIDTH words of FIFO space
localparam RX_TX_BUFFER = 0; // base address: In/Out buffer
localparam TX_COUNT_L = 1; // base address: Tx fifo count, low byte
localparam TX_COUNT_H = 2; // base address: Tx fifo count, high byte
localparam RX_COUNT_L = 3; // base address: Rx fifo count, low byte
localparam RX_COUNT_H = 4; // base address: Rx fifo count, high byte
//--------------------------------------------------------------------------
// Rx/Tx "clocks"
//--------------------------------------------------------------------------
wire uart_tick;
wire uart_tick_16x;
//--------------------------------------------------------------------------
// Rx signals
//--------------------------------------------------------------------------
wire [7:0] rx_data; // Raw bytes coming in from uart
wire rx_data_ready; // Synchronous pulse indicating data from Rx
wire rx_fifo_empty;
wire [7:0] rx_read_data;
//--------------------------------------------------------------------------
// Tx signals
//--------------------------------------------------------------------------
reg tx_fifo_deQ = 0;
reg tx_start = 0;
wire tx_free;
wire tx_fifo_empty;
wire [7:0] tx_fifo_data_out;
reg [7:0] tx_input_data;
//--------------------------------------------------------------------------
// Handle Tx FIFO
//--------------------------------------------------------------------------
assign uart_rx_ready_int = ~rx_fifo_empty;
always @(posedge clk) begin
if (rst) begin
tx_fifo_deQ <= 0;
tx_start <= 0;
end
else begin
if (~tx_fifo_empty & tx_free & uart_tick) begin
tx_fifo_deQ <= 1;
tx_start <= 1;
end
else begin
tx_fifo_deQ <= 0;
tx_start <= 0;
end
end
end
//--------------------------------------------------------------------------
// Handle R to this module
//--------------------------------------------------------------------------
wire [ADDR_WIDTH : 0] tx_count;
wire [ADDR_WIDTH : 0] rx_count;
always @(posedge clk) begin
if (~uart_wr & uart_enable) begin
case (uart_address)
RX_TX_BUFFER : begin uart_data_o <= rx_read_data; uart_ready <= 1'b1; end
TX_COUNT_L : begin uart_data_o <= tx_count[7:0]; uart_ready <= 1'b1; end
TX_COUNT_H : begin uart_data_o <= tx_count[ADDR_WIDTH:8]; uart_ready <= 1'b1; end
RX_COUNT_L : begin uart_data_o <= rx_count[7:0]; uart_ready <= 1'b1; end
RX_COUNT_H : begin uart_data_o <= rx_count[ADDR_WIDTH:8]; uart_ready <= 1'b1; end
default : begin uart_data_o <= 8'hxx; uart_ready <= 1'b1; end
endcase
end
else begin
uart_data_o <= 8'hxx;
uart_ready <= 1'b0;
end
end
//--------------------------------------------------------------------------
// Handle W to this module
//--------------------------------------------------------------------------
always @(posedge clk) begin
if (uart_wr & uart_enable) begin
case (uart_address)
RX_TX_BUFFER : begin tx_input_data <= uart_data_i; uart_ready <= 1'b1; end
default : begin tx_input_data <= 8'hxx; uart_ready <= 1'b1; end
endcase
end
else begin
tx_input_data <= 8'hxx;
uart_ready <= 1'b0;
end
end
//--------------------------------------------------------------------------
// Instantiate modules
//--------------------------------------------------------------------------
uart_clock clks (
.clk ( clk ),
.uart_tick ( uart_tick ),
.uart_tick_16x ( uart_tick_16x )
);
uart_tx tx (
.clk ( clk ),
.rst ( rst ),
.uart_tick ( uart_tick ),
.TxD_data ( tx_fifo_data_out ),
.TxD_start ( tx_start ),
.ready ( tx_free ),
.TxD ( uart_tx )
);
uart_rx rx (
.clk ( clk ),
.rst ( rst ),
.RxD ( uart_rx ),
.uart_tick_16x ( uart_tick_16x ),
.RxD_data ( rx_data ),
.ready ( rx_data_ready )
);
fifo #(
.DATA_WIDTH (DATA_WIDTH),
.ADDR_WIDTH (ADDR_WIDTH))
tx_buffer (
.clk ( clk ),
.rst ( rst ),
.enqueue ( uart_wr & uart_enable & ~uart_ready ),
.dequeue ( tx_fifo_deQ ),
.data_i ( tx_input_data ),
.data_o ( tx_fifo_data_out ),
.count ( tx_count ),
.empty ( tx_fifo_empty ),
.full ( )
);
fifo #(
.DATA_WIDTH (DATA_WIDTH),
.ADDR_WIDTH (ADDR_WIDTH))
rx_buffer (
.clk ( clk ),
.rst ( rst ),
.enqueue ( rx_data_ready ),
.dequeue ( ~uart_wr & uart_enable & ~uart_ready ),
.data_i ( rx_data ),
.data_o ( rx_read_data ),
.count ( rx_count ),
.empty ( rx_fifo_empty ),
.full ( uart_rx_full_int )
);
endmodule
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps/1ps
`default_nettype none
module spi_core
#(
parameter ABUSWIDTH = 16,
parameter MEM_BYTES = 16
)(
input wire BUS_CLK,
input wire BUS_RST,
input wire [ABUSWIDTH-1:0] BUS_ADD,
input wire [7:0] BUS_DATA_IN,
input wire BUS_RD,
input wire BUS_WR,
output reg [7:0] BUS_DATA_OUT,
input wire SPI_CLK,
output wire SCLK,
input wire SDO,
output reg SDI,
input wire EXT_START,
output reg SEN,
output reg SLD
);
localparam VERSION = 2;
reg [7:0] status_regs [15:0];
wire RST;
wire SOFT_RST;
assign RST = BUS_RST || SOFT_RST;
localparam DEF_BIT_OUT = 8*MEM_BYTES;
always @(posedge BUS_CLK) begin
if(RST) begin
status_regs[0] <= 0;
status_regs[1] <= 0;
status_regs[2] <= 0;
status_regs[3] <= DEF_BIT_OUT[7:0]; //bits
status_regs[4] <= DEF_BIT_OUT[15:8]; //bits
status_regs[5] <= 4; //wait
status_regs[6] <= 0; //wait
status_regs[7] <= 0; //wait
status_regs[8] <= 0; //wait
status_regs[9] <= 1; //repeat
status_regs[10] <= 0; //repeat
status_regs[11] <= 0; //repeat
status_regs[12] <= 0; //repeat
status_regs[13] <= 0; //0:enable external start
end
else if(BUS_WR && BUS_ADD < 16)
status_regs[BUS_ADD[3:0]] <= BUS_DATA_IN;
end
reg [7:0] BUS_IN_MEM;
reg [7:0] BUS_OUT_MEM;
wire START;
assign SOFT_RST = (BUS_ADD==0 && BUS_WR);
assign START = (BUS_ADD==1 && BUS_WR);
wire [15:0] CONF_BIT_OUT;
assign CONF_BIT_OUT = {status_regs[4],status_regs[3]};
// TODO: not yet used
wire [7:0] CONF_CLK_DIV;
assign CONF_CLK_DIV = status_regs[2];
reg CONF_DONE;
wire [31:0] CONF_WAIT;
assign CONF_WAIT = {status_regs[8], status_regs[7], status_regs[6], status_regs[5]};
wire [31:0] CONF_REPEAT;
assign CONF_REPEAT = {status_regs[12], status_regs[11], status_regs[10], status_regs[9]};
wire CONF_EN;
assign CONF_EN = status_regs[13][0];
reg [7:0] BUS_DATA_OUT_REG;
always@(posedge BUS_CLK) begin
if(BUS_RD) begin
if(BUS_ADD == 0)
BUS_DATA_OUT_REG <= VERSION;
else if(BUS_ADD == 1)
BUS_DATA_OUT_REG <= {7'b0, CONF_DONE};
else if(BUS_ADD == 13)
BUS_DATA_OUT_REG <= {7'b0, CONF_EN};
else if(BUS_ADD == 14)
BUS_DATA_OUT_REG <= MEM_BYTES[7:0];
else if(BUS_ADD == 15)
BUS_DATA_OUT_REG <= MEM_BYTES[15:8];
else if (BUS_ADD < 16)
BUS_DATA_OUT_REG <= status_regs[BUS_ADD[3:0]];
end
end
// if one has a synchronous memory need this to give data on next clock after read
// limitation: this module still needs to be addressed
reg [ABUSWIDTH-1:0] PREV_BUS_ADD;
always @ (posedge BUS_CLK) begin
if(BUS_RD) begin
PREV_BUS_ADD <= BUS_ADD;
end
end
always @(*) begin
if(PREV_BUS_ADD < 16)
BUS_DATA_OUT = BUS_DATA_OUT_REG;
else if(PREV_BUS_ADD < 16+MEM_BYTES)
BUS_DATA_OUT = BUS_IN_MEM;
else if(PREV_BUS_ADD < 16+MEM_BYTES+MEM_BYTES)
BUS_DATA_OUT = BUS_OUT_MEM;
else
BUS_DATA_OUT = 8'hxx;
end
reg [32:0] out_bit_cnt;
wire [13:0] memout_addrb;
assign memout_addrb = out_bit_cnt;
wire [10:0] memout_addra;
assign memout_addra = (BUS_ADD-16);
reg [7:0] BUS_DATA_IN_IB;
wire [7:0] BUS_IN_MEM_IB;
wire [7:0] BUS_OUT_MEM_IB;
integer i;
always @(*) begin
for(i=0;i<8;i=i+1) begin
BUS_DATA_IN_IB[i] = BUS_DATA_IN[7-i];
BUS_IN_MEM[i] = BUS_IN_MEM_IB[7-i];
BUS_OUT_MEM[i] = BUS_OUT_MEM_IB[7-i];
end
end
wire SDI_MEM;
blk_mem_gen_8_to_1_2k memout(
.CLKA(BUS_CLK),
.CLKB(SPI_CLK),
.DOUTA(BUS_IN_MEM_IB),
.DOUTB(SDI_MEM),
.WEA(BUS_WR && BUS_ADD >=16 && BUS_ADD < 16+MEM_BYTES),
.WEB(1'b0),
.ADDRA(memout_addra),
.ADDRB(memout_addrb),
.DINA(BUS_DATA_IN_IB),
.DINB(1'b0)
);
wire [10:0] ADDRA_MIN;
assign ADDRA_MIN = (BUS_ADD-16-MEM_BYTES);
wire [13:0] ADDRB_MIN;
assign ADDRB_MIN = out_bit_cnt-1;
reg SEN_INT;
blk_mem_gen_8_to_1_2k memin(
.CLKA(BUS_CLK),
.CLKB(SPI_CLK),
.DOUTA(BUS_OUT_MEM_IB),
.DOUTB(),
.WEA(1'b0),
.WEB(SEN_INT),
.ADDRA(ADDRA_MIN),
.ADDRB(ADDRB_MIN),
.DINA(BUS_DATA_IN_IB),
.DINB(SDO)
);
wire RST_SYNC;
wire RST_SOFT_SYNC;
cdc_pulse_sync rst_pulse_sync (.clk_in(BUS_CLK), .pulse_in(RST), .clk_out(SPI_CLK), .pulse_out(RST_SOFT_SYNC));
assign RST_SYNC = RST_SOFT_SYNC || BUS_RST;
wire START_SYNC;
cdc_pulse_sync start_pulse_sync (.clk_in(BUS_CLK), .pulse_in(START), .clk_out(SPI_CLK), .pulse_out(START_SYNC));
wire EXT_START_PULSE;
reg [2:0] EXT_START_FF;
always @(posedge SPI_CLK) // first stage
begin
EXT_START_FF[0] <= EXT_START;
EXT_START_FF[1] <= EXT_START_FF[0];
EXT_START_FF[2] <= EXT_START_FF[1];
end
assign EXT_START_PULSE = !EXT_START_FF[2] & EXT_START_FF[1];
wire [32:0] STOP_BIT;
assign STOP_BIT = CONF_BIT_OUT + CONF_WAIT;
reg [31:0] REPEAT_COUNT;
wire REP_START;
assign REP_START = (out_bit_cnt == STOP_BIT && (CONF_REPEAT==0 || REPEAT_COUNT < CONF_REPEAT));
reg REP_START_DLY;
always @ (posedge SPI_CLK)
REP_START_DLY <= REP_START;
always @ (posedge SPI_CLK)
if (RST_SYNC)
SEN_INT <= 0;
else if(START_SYNC || (EXT_START_PULSE && CONF_EN) || REP_START_DLY)
SEN_INT <= 1;
else if(out_bit_cnt == CONF_BIT_OUT)
SEN_INT <= 0;
always @ (posedge SPI_CLK)
if (RST_SYNC)
out_bit_cnt <= 0;
else if(START_SYNC || (EXT_START_PULSE && CONF_EN))
out_bit_cnt <= 1;
else if(out_bit_cnt == STOP_BIT)
out_bit_cnt <= 0;
//else if(out_bit_cnt == CONF_BIT_OUT & REPEAT_COUNT == CONF_REPEAT & CONF_REPEAT!=0)
// out_bit_cnt <= 0;
else if(REP_START_DLY)
out_bit_cnt <= 1;
else if(out_bit_cnt != 0)
out_bit_cnt <= out_bit_cnt + 1;
always @ (posedge SPI_CLK)
if (RST_SYNC || START_SYNC || (EXT_START_PULSE && CONF_EN))
REPEAT_COUNT <= 1;
else if(out_bit_cnt == STOP_BIT)
REPEAT_COUNT <= REPEAT_COUNT + 1;
reg [1:0] sync_ld;
always @(posedge SPI_CLK) begin
sync_ld[0] <= SEN_INT;
sync_ld[1] <= sync_ld[0];
end
always @(posedge SPI_CLK)
SLD <= (sync_ld[1]==1 && sync_ld[0]==0);
wire DONE = out_bit_cnt == STOP_BIT && REPEAT_COUNT >= CONF_REPEAT;
wire DONE_SYNC, EXT_START_PULSE_SYNC;
cdc_pulse_sync done_pulse_sync (.clk_in(SPI_CLK), .pulse_in(DONE), .clk_out(BUS_CLK), .pulse_out(DONE_SYNC));
cdc_pulse_sync done_pulse_ext_start (.clk_in(SPI_CLK), .pulse_in(EXT_START_PULSE), .clk_out(BUS_CLK), .pulse_out(EXT_START_PULSE_SYNC));
always @(posedge BUS_CLK)
if(RST)
CONF_DONE <= 1;
else if(START || (EXT_START_PULSE_SYNC && CONF_EN))
CONF_DONE <= 0;
else if(DONE_SYNC)
CONF_DONE <= 1;
CG_MOD_pos icg2(.ck_in(SPI_CLK), .enable(SEN), .ck_out(SCLK));
always @(negedge SPI_CLK)
SDI <= SDI_MEM & SEN_INT;
always @(negedge SPI_CLK)
SEN <= SEN_INT;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__XNOR2_LP_V
`define SKY130_FD_SC_LP__XNOR2_LP_V
/**
* xnor2: 2-input exclusive NOR.
*
* Y = !(A ^ B)
*
* Verilog wrapper for xnor2 with size for low power.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__xnor2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__xnor2_lp (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__xnor2 base (
.Y(Y),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__xnor2_lp (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__xnor2 base (
.Y(Y),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__XNOR2_LP_V
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.2
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1ns/1ps
module convolve_kernel_fbkb
#(parameter
ID = 7,
NUM_STAGE = 9,
din0_WIDTH = 32,
din1_WIDTH = 32,
dout_WIDTH = 32
)(
input wire clk,
input wire reset,
input wire ce,
input wire [din0_WIDTH-1:0] din0,
input wire [din1_WIDTH-1:0] din1,
output wire [dout_WIDTH-1:0] dout
);
//------------------------Local signal-------------------
wire aclk;
wire aclken;
wire a_tvalid;
wire [31:0] a_tdata;
wire b_tvalid;
wire [31:0] b_tdata;
wire r_tvalid;
wire [31:0] r_tdata;
reg [din0_WIDTH-1:0] din0_buf1;
reg [din1_WIDTH-1:0] din1_buf1;
//------------------------Instantiation------------------
convolve_kernel_ap_fadd_7_full_dsp_32 convolve_kernel_ap_fadd_7_full_dsp_32_u (
.aclk ( aclk ),
.aclken ( aclken ),
.s_axis_a_tvalid ( a_tvalid ),
.s_axis_a_tdata ( a_tdata ),
.s_axis_b_tvalid ( b_tvalid ),
.s_axis_b_tdata ( b_tdata ),
.m_axis_result_tvalid ( r_tvalid ),
.m_axis_result_tdata ( r_tdata )
);
//------------------------Body---------------------------
assign aclk = clk;
assign aclken = ce;
assign a_tvalid = 1'b1;
assign a_tdata = din0_buf1;
assign b_tvalid = 1'b1;
assign b_tdata = din1_buf1;
assign dout = r_tdata;
always @(posedge clk) begin
if (ce) begin
din0_buf1 <= din0;
din1_buf1 <= din1;
end
end
endmodule
|
/*
Copyright (C) 2016 Cedric Orban
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/*
Basic datapath. Parameterized so the network size can be modified with ease.
*/
`include "DeepGATE_include.v"
module tile_datapath #(
parameter SIZE = 16'd256, //# of processing units in this tile
parameter LOOP = 16'd4, //nodes calculated per processing unit
parameter PRV_SIZE = 16'd10, //# of processing units in previous tile
parameter PRV_LOOP = 16'd10, //nodes per processing unit in previous tile
parameter BIAS = 16'd0, //per-layer biasing
parameter WEIGHT_WIDTH = 3
)(
input clk_i,
input rst_i,
input en_i,
input [7:0] data_i,
input [$clog2(SIZE) - 1'b1:0] sig_mux_sel_i,
input [SIZE*WEIGHT_WIDTH - 1:0] weight_bus_i,
output wire [7:0] data_o
);
wire [9:0] mux_o;
wire [SIZE*10 - 1:0] proc_unit_o;
genvar i;
generate
for(i = 0; i < SIZE; i = i + 1) begin: PU
processing_unit #(
.PRV_SIZE (PRV_SIZE),
.PRV_LOOP (PRV_LOOP),
.BIAS (BIAS),
.WEIGHT_WIDTH (WEIGHT_WIDTH))
PU(
.clk_i (clk_i),
.rst_i (rst_i),
.en_i (en_i),
.weight_i (weight_bus_i[`IDX(i, WEIGHT_WIDTH)]),
.data_i (data_i),
.proc_unit_o (proc_unit_o[`ID10(i)])
);
end
endgenerate
sig_mux #(
.SIZE(SIZE),
.WIDTH(10)
)
sig_mux(
.sel(sig_mux_sel_i),
.mux_i(proc_unit_o),
.mux_o(mux_o)
);
sig_368p sig_368p(
.sig_i(mux_o),
.sig_o(data_o)
);
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:57:15 07/09/2015
// Design Name:
// Module Name: Serializer_10_1
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Serializer_10_1
( input [9:0] Data,
input Clk_10,
input Clk_2,
input Strobe,
output Out
);
reg Status;
reg [9:0] FullData; // Buffered Data in
reg [4:0] HalfData; // Buffered Data out
wire cascade_in;
wire cascade_out;
initial
begin
Status = 1'b0;
FullData[4:0] = 5'h000;
HalfData[4:0] = 5'h00;
end
always @(posedge Clk_2)
begin
if (Status == 1'b0)
begin
FullData[4:0] = Data[9:5];
HalfData[4:0] = Data[4:0];
Status = 1'b1;
end
else
begin
HalfData[4:0] = FullData[4:0];
Status = 1'b0;
end
end
OSERDES2 #(.DATA_RATE_OQ("SDR"),
.DATA_RATE_OT("SDR"),
.DATA_WIDTH(5),
.SERDES_MODE("MASTER")
) MasterSerDes(.CLK0(Clk_10),
.CLK1(1'b0),
.CLKDIV(Clk_2),
.IOCE(Strobe),
.D4(1'b0),
.D3(1'b0),
.D2(1'b0),
.D1(HalfData[4]),
.OCE(1'b1),
.RST(1'b0),
.T4(1'b0),
.T3(1'b0),
.T2(1'b0),
.T1(1'b0),
.TCE(1'b0),
.SHIFTIN1(1'b0),
.SHIFTIN2(1'b0),
.SHIFTIN3(cascade_in),
.SHIFTIN4(1'b0),
.TRAIN(1'b0),
.OQ(Out),
.TQ(),
.SHIFTOUT1(cascade_out),
.SHIFTOUT2(),
.SHIFTOUT3(),
.SHIFTOUT4());
OSERDES2 #(.DATA_RATE_OQ("SDR"),
.DATA_RATE_OT("SDR"),
.DATA_WIDTH(5),
.SERDES_MODE("SLAVE")
) SlaveSerDes(.CLK0(Clk_10),
.CLK1(1'b0),
.CLKDIV(Clk_2),
.IOCE(Strobe),
.D4(HalfData[3]),
.D3(HalfData[2]),
.D2(HalfData[1]),
.D1(HalfData[0]),
.OCE(1'b1),
.RST(1'b0),
.T4(1'b0),
.T3(1'b0),
.T2(1'b0),
.T1(1'b0),
.TCE(1'b0),
.SHIFTIN1(cascade_out),
.SHIFTIN2(1'b0),
.SHIFTIN3(1'b0),
.SHIFTIN4(1'b0),
.TRAIN(1'b0),
.OQ(),
.TQ(),
.SHIFTOUT1(),
.SHIFTOUT2(),
.SHIFTOUT3(cascade_in),
.SHIFTOUT4());
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__OR3B_PP_SYMBOL_V
`define SKY130_FD_SC_LP__OR3B_PP_SYMBOL_V
/**
* or3b: 3-input OR, first input inverted.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__or3b (
//# {{data|Data Signals}}
input A ,
input B ,
input C_N ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__OR3B_PP_SYMBOL_V
|
/* wb_cdc_tb. Part of wb_intercon
*
* ISC License
*
* Copyright (C) 2019 Olof Kindgren <[email protected]>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
/*Testbench for wb_cdc
*/
`default_nettype none
module wb_cdc_tb
#(parameter AUTORUN = 1);
localparam aw = 32;
localparam dw = 32;
localparam MEM_SIZE = 256;
reg wbm_clk = 1'b1;
reg wbm_rst = 1'b1;
reg wbs_clk = 1'b1;
reg wbs_rst = 1'b1;
wire [aw-1:0] wbm_m2s_adr;
wire [dw-1:0] wbm_m2s_dat;
wire [3:0] wbm_m2s_sel;
wire wbm_m2s_we ;
wire wbm_m2s_cyc;
wire wbm_m2s_stb;
wire [dw-1:0] wbm_s2m_dat;
wire wbm_s2m_ack;
wire [aw-1:0] wbs_m2s_adr;
wire [dw-1:0] wbs_m2s_dat;
wire [3:0] wbs_m2s_sel;
wire wbs_m2s_we ;
wire wbs_m2s_cyc;
wire wbs_m2s_stb;
wire [dw-1:0] wbs_s2m_dat;
wire wbs_s2m_ack;
wire done;
integer TRANSACTIONS;
generate
if (AUTORUN) begin
vlog_tb_utils vtu();
vlog_tap_generator #("wb_cdc.tap", 1) vtg();
initial begin
run;
vtg.ok("wb_cdc: All tests passed!");
$finish;
end
end
endgenerate
task run;
begin
transactor.bfm.reset;
@(posedge wbs_clk) wbs_rst = 1'b0;
@(posedge wbm_clk) wbm_rst = 1'b0;
if($value$plusargs("transactions=%d", TRANSACTIONS))
transactor.set_transactions(TRANSACTIONS);
transactor.display_settings;
transactor.run();
transactor.display_stats;
end
endtask
always #5 wbm_clk <= ~wbm_clk;
always #3 wbs_clk <= ~wbs_clk;
wb_bfm_transactor
#(.MEM_HIGH (MEM_SIZE-1),
.AUTORUN (0),
.VERBOSE (0))
transactor
(.wb_clk_i (wbm_clk),
.wb_rst_i (1'b0),
.wb_adr_o (wbm_m2s_adr),
.wb_dat_o (wbm_m2s_dat),
.wb_sel_o (wbm_m2s_sel),
.wb_we_o (wbm_m2s_we),
.wb_cyc_o (wbm_m2s_cyc),
.wb_stb_o (wbm_m2s_stb),
.wb_cti_o (),
.wb_bte_o (),
.wb_dat_i (wbm_s2m_dat),
.wb_ack_i (wbm_s2m_ack),
.wb_err_i (1'b0),
.wb_rty_i (1'b0),
//Test Control
.done());
wb_cdc
#(.AW(aw))
dut
(.wbm_clk (wbm_clk),
.wbm_rst (wbm_rst),
// Master Interface
.wbm_adr_i (wbm_m2s_adr),
.wbm_dat_i (wbm_m2s_dat),
.wbm_sel_i (wbm_m2s_sel),
.wbm_we_i (wbm_m2s_we ),
.wbm_cyc_i (wbm_m2s_cyc),
.wbm_stb_i (wbm_m2s_stb),
.wbm_dat_o (wbm_s2m_dat),
.wbm_ack_o (wbm_s2m_ack),
// Wishbone Slave interface
.wbs_clk (wbs_clk),
.wbs_rst (wbs_rst),
.wbs_adr_o (wbs_m2s_adr),
.wbs_dat_o (wbs_m2s_dat),
.wbs_sel_o (wbs_m2s_sel),
.wbs_we_o (wbs_m2s_we),
.wbs_cyc_o (wbs_m2s_cyc),
.wbs_stb_o (wbs_m2s_stb),
.wbs_dat_i (wbs_s2m_dat),
.wbs_ack_i (wbs_s2m_ack & !wbs_rst));
wb_bfm_memory
#(.DEBUG (0),
.mem_size_bytes(MEM_SIZE))
mem
(.wb_clk_i (wbs_clk),
.wb_rst_i (wbs_rst),
.wb_adr_i (wbs_m2s_adr),
.wb_dat_i (wbs_m2s_dat),
.wb_sel_i (wbs_m2s_sel),
.wb_we_i (wbs_m2s_we),
.wb_cyc_i (wbs_m2s_cyc),
.wb_stb_i (wbs_m2s_stb),
.wb_cti_i (3'b000),
.wb_bte_i (2'b00),
.wb_dat_o (wbs_s2m_dat),
.wb_ack_o (wbs_s2m_ack),
.wb_err_o (),
.wb_rty_o ());
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__AND4B_BEHAVIORAL_V
`define SKY130_FD_SC_HS__AND4B_BEHAVIORAL_V
/**
* and4b: 4-input AND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__and4b (
X ,
A_N ,
B ,
C ,
D ,
VPWR,
VGND
);
// Module ports
output X ;
input A_N ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
// Local signals
wire D not0_out ;
wire and0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
not not0 (not0_out , A_N );
and and0 (and0_out_X , not0_out, B, C, D );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__AND4B_BEHAVIORAL_V
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: user.org:user:fmrv32im:1.0
// IP Revision: 6
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module fmrv32im_artya7_fmrv32im_0 (
RST_N,
CLK,
I_MEM_WAIT,
I_MEM_ENA,
I_MEM_ADDR,
I_MEM_RDATA,
I_MEM_BADMEM_EXCPT,
D_MEM_WAIT,
D_MEM_ENA,
D_MEM_WSTB,
D_MEM_ADDR,
D_MEM_WDATA,
D_MEM_RDATA,
D_MEM_BADMEM_EXCPT,
EXT_INTERRUPT,
TIMER_EXPIRED
);
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST_N RST" *)
input wire RST_N;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
input wire CLK;
(* X_INTERFACE_INFO = "user.org:user:MEM_BUS:1.0 I_MEM_BUS MEM_WAIT" *)
input wire I_MEM_WAIT;
(* X_INTERFACE_INFO = "user.org:user:MEM_BUS:1.0 I_MEM_BUS MEM_ENA" *)
output wire I_MEM_ENA;
(* X_INTERFACE_INFO = "user.org:user:MEM_BUS:1.0 I_MEM_BUS MEM_ADDR" *)
output wire [31 : 0] I_MEM_ADDR;
(* X_INTERFACE_INFO = "user.org:user:MEM_BUS:1.0 I_MEM_BUS MEM_RDATA" *)
input wire [31 : 0] I_MEM_RDATA;
(* X_INTERFACE_INFO = "user.org:user:MEM_BUS:1.0 I_MEM_BUS MEM_BADMEM_EXCPT" *)
input wire I_MEM_BADMEM_EXCPT;
(* X_INTERFACE_INFO = "user.org:user:MEM_BUS:1.0 D_MEM_BUS MEM_WAIT" *)
input wire D_MEM_WAIT;
(* X_INTERFACE_INFO = "user.org:user:MEM_BUS:1.0 D_MEM_BUS MEM_ENA" *)
output wire D_MEM_ENA;
(* X_INTERFACE_INFO = "user.org:user:MEM_BUS:1.0 D_MEM_BUS MEM_WSTB" *)
output wire [3 : 0] D_MEM_WSTB;
(* X_INTERFACE_INFO = "user.org:user:MEM_BUS:1.0 D_MEM_BUS MEM_ADDR" *)
output wire [31 : 0] D_MEM_ADDR;
(* X_INTERFACE_INFO = "user.org:user:MEM_BUS:1.0 D_MEM_BUS MEM_WDATA" *)
output wire [31 : 0] D_MEM_WDATA;
(* X_INTERFACE_INFO = "user.org:user:MEM_BUS:1.0 D_MEM_BUS MEM_RDATA" *)
input wire [31 : 0] D_MEM_RDATA;
(* X_INTERFACE_INFO = "user.org:user:MEM_BUS:1.0 D_MEM_BUS MEM_BADMEM_EXCPT" *)
input wire D_MEM_BADMEM_EXCPT;
(* X_INTERFACE_INFO = "xilinx.com:signal:interrupt:1.0 EXT_INTERRUPT INTERRUPT" *)
input wire EXT_INTERRUPT;
input wire TIMER_EXPIRED;
fmrv32im #(
.MADD33_ADDON(0)
) inst (
.RST_N(RST_N),
.CLK(CLK),
.I_MEM_WAIT(I_MEM_WAIT),
.I_MEM_ENA(I_MEM_ENA),
.I_MEM_ADDR(I_MEM_ADDR),
.I_MEM_RDATA(I_MEM_RDATA),
.I_MEM_BADMEM_EXCPT(I_MEM_BADMEM_EXCPT),
.D_MEM_WAIT(D_MEM_WAIT),
.D_MEM_ENA(D_MEM_ENA),
.D_MEM_WSTB(D_MEM_WSTB),
.D_MEM_ADDR(D_MEM_ADDR),
.D_MEM_WDATA(D_MEM_WDATA),
.D_MEM_RDATA(D_MEM_RDATA),
.D_MEM_BADMEM_EXCPT(D_MEM_BADMEM_EXCPT),
.EXT_INTERRUPT(EXT_INTERRUPT),
.TIMER_EXPIRED(TIMER_EXPIRED)
);
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Fri Jan 13 17:33:49 2017
// Host : KLight-PC running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// D:/Document/Verilog/VGA/VGA.srcs/sources_1/ip/bg_low_1/bg_low_sim_netlist.v
// Design : bg_low
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "bg_low,blk_mem_gen_v8_3_5,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "blk_mem_gen_v8_3_5,Vivado 2016.4" *)
(* NotValidForBitStream *)
module bg_low
(clka,
wea,
addra,
dina,
douta);
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *) input clka;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *) input [0:0]wea;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *) input [10:0]addra;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *) input [11:0]dina;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *) output [11:0]douta;
wire [10:0]addra;
wire clka;
wire [11:0]dina;
wire [11:0]douta;
wire [0:0]wea;
wire NLW_U0_dbiterr_UNCONNECTED;
wire NLW_U0_rsta_busy_UNCONNECTED;
wire NLW_U0_rstb_busy_UNCONNECTED;
wire NLW_U0_s_axi_arready_UNCONNECTED;
wire NLW_U0_s_axi_awready_UNCONNECTED;
wire NLW_U0_s_axi_bvalid_UNCONNECTED;
wire NLW_U0_s_axi_dbiterr_UNCONNECTED;
wire NLW_U0_s_axi_rlast_UNCONNECTED;
wire NLW_U0_s_axi_rvalid_UNCONNECTED;
wire NLW_U0_s_axi_sbiterr_UNCONNECTED;
wire NLW_U0_s_axi_wready_UNCONNECTED;
wire NLW_U0_sbiterr_UNCONNECTED;
wire [11:0]NLW_U0_doutb_UNCONNECTED;
wire [10:0]NLW_U0_rdaddrecc_UNCONNECTED;
wire [3:0]NLW_U0_s_axi_bid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED;
wire [10:0]NLW_U0_s_axi_rdaddrecc_UNCONNECTED;
wire [11:0]NLW_U0_s_axi_rdata_UNCONNECTED;
wire [3:0]NLW_U0_s_axi_rid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED;
(* C_ADDRA_WIDTH = "11" *)
(* C_ADDRB_WIDTH = "11" *)
(* C_ALGORITHM = "1" *)
(* C_AXI_ID_WIDTH = "4" *)
(* C_AXI_SLAVE_TYPE = "0" *)
(* C_AXI_TYPE = "1" *)
(* C_BYTE_SIZE = "9" *)
(* C_COMMON_CLK = "0" *)
(* C_COUNT_18K_BRAM = "0" *)
(* C_COUNT_36K_BRAM = "1" *)
(* C_CTRL_ECC_ALGO = "NONE" *)
(* C_DEFAULT_DATA = "0" *)
(* C_DISABLE_WARN_BHV_COLL = "0" *)
(* C_DISABLE_WARN_BHV_RANGE = "0" *)
(* C_ELABORATION_DIR = "./" *)
(* C_ENABLE_32BIT_ADDRESS = "0" *)
(* C_EN_DEEPSLEEP_PIN = "0" *)
(* C_EN_ECC_PIPE = "0" *)
(* C_EN_RDADDRA_CHG = "0" *)
(* C_EN_RDADDRB_CHG = "0" *)
(* C_EN_SAFETY_CKT = "0" *)
(* C_EN_SHUTDOWN_PIN = "0" *)
(* C_EN_SLEEP_PIN = "0" *)
(* C_EST_POWER_SUMMARY = "Estimated Power for IP : 2.5912999999999999 mW" *)
(* C_FAMILY = "artix7" *)
(* C_HAS_AXI_ID = "0" *)
(* C_HAS_ENA = "0" *)
(* C_HAS_ENB = "0" *)
(* C_HAS_INJECTERR = "0" *)
(* C_HAS_MEM_OUTPUT_REGS_A = "1" *)
(* C_HAS_MEM_OUTPUT_REGS_B = "0" *)
(* C_HAS_MUX_OUTPUT_REGS_A = "0" *)
(* C_HAS_MUX_OUTPUT_REGS_B = "0" *)
(* C_HAS_REGCEA = "0" *)
(* C_HAS_REGCEB = "0" *)
(* C_HAS_RSTA = "0" *)
(* C_HAS_RSTB = "0" *)
(* C_HAS_SOFTECC_INPUT_REGS_A = "0" *)
(* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *)
(* C_INITA_VAL = "0" *)
(* C_INITB_VAL = "0" *)
(* C_INIT_FILE = "bg_low.mem" *)
(* C_INIT_FILE_NAME = "bg_low.mif" *)
(* C_INTERFACE_TYPE = "0" *)
(* C_LOAD_INIT_FILE = "1" *)
(* C_MEM_TYPE = "0" *)
(* C_MUX_PIPELINE_STAGES = "0" *)
(* C_PRIM_TYPE = "1" *)
(* C_READ_DEPTH_A = "1092" *)
(* C_READ_DEPTH_B = "1092" *)
(* C_READ_WIDTH_A = "12" *)
(* C_READ_WIDTH_B = "12" *)
(* C_RSTRAM_A = "0" *)
(* C_RSTRAM_B = "0" *)
(* C_RST_PRIORITY_A = "CE" *)
(* C_RST_PRIORITY_B = "CE" *)
(* C_SIM_COLLISION_CHECK = "ALL" *)
(* C_USE_BRAM_BLOCK = "0" *)
(* C_USE_BYTE_WEA = "0" *)
(* C_USE_BYTE_WEB = "0" *)
(* C_USE_DEFAULT_DATA = "0" *)
(* C_USE_ECC = "0" *)
(* C_USE_SOFTECC = "0" *)
(* C_USE_URAM = "0" *)
(* C_WEA_WIDTH = "1" *)
(* C_WEB_WIDTH = "1" *)
(* C_WRITE_DEPTH_A = "1092" *)
(* C_WRITE_DEPTH_B = "1092" *)
(* C_WRITE_MODE_A = "WRITE_FIRST" *)
(* C_WRITE_MODE_B = "WRITE_FIRST" *)
(* C_WRITE_WIDTH_A = "12" *)
(* C_WRITE_WIDTH_B = "12" *)
(* C_XDEVICEFAMILY = "artix7" *)
(* downgradeipidentifiedwarnings = "yes" *)
bg_low_blk_mem_gen_v8_3_5 U0
(.addra(addra),
.addrb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.clka(clka),
.clkb(1'b0),
.dbiterr(NLW_U0_dbiterr_UNCONNECTED),
.deepsleep(1'b0),
.dina(dina),
.dinb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.douta(douta),
.doutb(NLW_U0_doutb_UNCONNECTED[11:0]),
.eccpipece(1'b0),
.ena(1'b0),
.enb(1'b0),
.injectdbiterr(1'b0),
.injectsbiterr(1'b0),
.rdaddrecc(NLW_U0_rdaddrecc_UNCONNECTED[10:0]),
.regcea(1'b0),
.regceb(1'b0),
.rsta(1'b0),
.rsta_busy(NLW_U0_rsta_busy_UNCONNECTED),
.rstb(1'b0),
.rstb_busy(NLW_U0_rstb_busy_UNCONNECTED),
.s_aclk(1'b0),
.s_aresetn(1'b0),
.s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arburst({1'b0,1'b0}),
.s_axi_arid({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED),
.s_axi_arsize({1'b0,1'b0,1'b0}),
.s_axi_arvalid(1'b0),
.s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awburst({1'b0,1'b0}),
.s_axi_awid({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED),
.s_axi_awsize({1'b0,1'b0,1'b0}),
.s_axi_awvalid(1'b0),
.s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[3:0]),
.s_axi_bready(1'b0),
.s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]),
.s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED),
.s_axi_dbiterr(NLW_U0_s_axi_dbiterr_UNCONNECTED),
.s_axi_injectdbiterr(1'b0),
.s_axi_injectsbiterr(1'b0),
.s_axi_rdaddrecc(NLW_U0_s_axi_rdaddrecc_UNCONNECTED[10:0]),
.s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[11:0]),
.s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[3:0]),
.s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED),
.s_axi_rready(1'b0),
.s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]),
.s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED),
.s_axi_sbiterr(NLW_U0_s_axi_sbiterr_UNCONNECTED),
.s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wlast(1'b0),
.s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED),
.s_axi_wstrb(1'b0),
.s_axi_wvalid(1'b0),
.sbiterr(NLW_U0_sbiterr_UNCONNECTED),
.shutdown(1'b0),
.sleep(1'b0),
.wea(wea),
.web(1'b0));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_generic_cstr" *)
module bg_low_blk_mem_gen_generic_cstr
(douta,
clka,
addra,
dina,
wea);
output [11:0]douta;
input clka;
input [10:0]addra;
input [11:0]dina;
input [0:0]wea;
wire [10:0]addra;
wire clka;
wire [11:0]dina;
wire [11:0]douta;
wire [0:0]wea;
bg_low_blk_mem_gen_prim_width \ramloop[0].ram.r
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module bg_low_blk_mem_gen_prim_width
(douta,
clka,
addra,
dina,
wea);
output [11:0]douta;
input clka;
input [10:0]addra;
input [11:0]dina;
input [0:0]wea;
wire [10:0]addra;
wire clka;
wire [11:0]dina;
wire [11:0]douta;
wire [0:0]wea;
bg_low_blk_mem_gen_prim_wrapper_init \prim_init.ram
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module bg_low_blk_mem_gen_prim_wrapper_init
(douta,
clka,
addra,
dina,
wea);
output [11:0]douta;
input clka;
input [10:0]addra;
input [11:0]dina;
input [0:0]wea;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_37 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_38 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_45 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_46 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_87 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88 ;
wire [10:0]addra;
wire clka;
wire [11:0]dina;
wire [11:0]douta;
wire [0:0]wea;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:16]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:2]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h1C001C001C001C0024001C001C001C001C001C001C001C001C001C001C001C00),
.INIT_01(256'h1D041D041D041D041D041D041C001C0024001C001C001C001C001C001C001C00),
.INIT_02(256'h1D041D041D041D041D041D041D041D041D041D041D041D041D041D041D041D04),
.INIT_03(256'h2C001D041D0434001D041D0434001D041D0434001D041D041D041D041D041D04),
.INIT_04(256'h353735371D041D042C001D041D0434001D041D0434001D041D0434001D041D04),
.INIT_05(256'h3E0835373E083E0835373537353735373E083E0835373E083E0835373E083E08),
.INIT_06(256'h1D373E081D373E081D371D371D373E0835373537353735373E083E0835373E08),
.INIT_07(256'h35373E081D371D371D373E081D373E081D371D371D373E0835373E081D371D37),
.INIT_08(256'h35371D373E081D37353735373537261935373E081D37353735371D371D373E08),
.INIT_09(256'h353700002619353735371D373E081D37353735373537261935373E081D373537),
.INIT_0A(256'h1D371D3735373537353700002619353704011D3735371D371D371D3735373537),
.INIT_0B(256'h2619261926193E0826192619261926193E0826192619353704011D3735371D37),
.INIT_0C(256'h3E08261926193E082619261926193E0826192619261926193E08261926193E08),
.INIT_0D(256'h3E083E0826192E3B3E0826192E3B3E0826193E082E3B26193E083E0826192E3B),
.INIT_0E(256'h2E3B2E3B2E3B2E3B2E3B2E3B26192E3B3E0826192E3B3E0826193E082E3B2619),
.INIT_0F(256'h2E3B2E3B2E3B2E3B2E3B2E3B2E3B2E3B2E3B2E3B2E3B2E3B2E3B2E3B2E3B2E3B),
.INIT_10(256'h2E3B2E3B3F382E3B0C002E3B2E3B2E3B2E3B2E3B2E3B04002E3B2E3B2E3B2E3B),
.INIT_11(256'h3F382E3B2E3B04002E3B2E3B3F382E3B0C002E3B2E3B2E3B2E3B2E3B2E3B0400),
.INIT_12(256'h3E0804002E3B2E3B3F382E3B2E3B3E08371D2E3B2E3B2E3B3E0804002E3B2E3B),
.INIT_13(256'h2E3B2E3B2E3B2E3B2E3B2E3B2E3B2E3B3F382E3B2E3B3E08371D2E3B2E3B2E3B),
.INIT_14(256'h2E3B2E3B3F383E082E3B2E3B2E3B2E3B2E3B2E3B2E3B2E3B2E3B2E3B3F383E08),
.INIT_15(256'h3F3F3F3F3F3F040026192619261926192619261926192619261926192E3B2E3B),
.INIT_16(256'h371D0400371D371D3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F),
.INIT_17(256'h2E3B2E3B2E3B2E3B2E3B2E3B2E3B2E3B2E3B3F3F3F3F0400371D371D371D371D),
.INIT_18(256'h3F3F3F3F371D3F38371D371D371D371D371D371D2E3B2E3B2E3B2E3B2E3B2E3B),
.INIT_19(256'h371D371D371D0400371D371D371D371D371D371D371D371D371D371D371D0000),
.INIT_1A(256'h371D371D371D371D371D371D00003F3F00003F3800003F3800003F383F381400),
.INIT_1B(256'h3F383F383F383F383F383F38371D371D371D371D371D371D371D371D371D371D),
.INIT_1C(256'h3E083E083F383F383F383E083F383E083F383F383F383F383F3800003F3F0001),
.INIT_1D(256'h3E083F383F383F3800003F3F3F3F3F383F383F383F383F383F383F383F383E08),
.INIT_1E(256'h3E083F383F383F383E083F383F383E083E083F383F383F383F383F383F383F38),
.INIT_1F(256'h3E0800013E083E083F383F383E083F383F383E083F3800003F3F00013F380001),
.INIT_20(256'h3F383F3800003F3F00013F303F383F383F383F383E083F383E083F383F383E08),
.INIT_21(256'h3F383F3F3F383F383F3F3F383F383F383F383F383F3F3F383F383F383F3F3F38),
.INIT_22(256'h3F383F383F303E083F303F383F383E083F383F3F3F3F000114003F383F3F3F38),
.INIT_23(256'h00003F3F00003F383F383F383F303E083F303F383F303F383F383E083F383F38),
.INIT_24(256'h3F383F383F303F303F383F303F303F383F303F303F303F383F303F383F303F38),
.INIT_25(256'h000100000001000000000000000000003F3F00003F303F383F303F303F383F38),
.INIT_26(256'h0001000000000000000000000000000000000000000000000001000000000000),
.INIT_27(256'h3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F),
.INIT_28(256'h3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F),
.INIT_29(256'h3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F),
.INIT_2A(256'h3E083F3F3E083F383E083F383F383F383E083F3F3F3F3F383F3F3F3F3F3F3F3F),
.INIT_2B(256'h3F3F3F383F3F3F383E083F3F3E083F383E083F383F383F383E083F3F3F3F3F38),
.INIT_2C(256'h3F383F383F383F383F3F3F383F383F383F383F383F3F3F383F383F383F383F38),
.INIT_2D(256'h3F383F3F3F383F383F3F3F383E083F383F3F3F383F383F383F383F383F3F3F38),
.INIT_2E(256'h3F383F383F383F383F383F3F3F383F383F3F3F383E083F383F383F383F383F38),
.INIT_2F(256'h3F3F3F383F383F383F383F3F3F383F3F3F383E083F3814003F3F3F383E083F38),
.INIT_30(256'h3E083F3F3E083F383F3F3F383F383F383F383F3F3F383F3F3F383E083F381400),
.INIT_31(256'h3F3F3F383F383F383E083F3F3E083F383E083F383F383F383F3F3F383F383F38),
.INIT_32(256'h3F383E083F3F3F3F3F3F3F383F3F3F383F383F3F3E083F383E083F383F383F38),
.INIT_33(256'h3F383F3F3F383E083F383E083F3F3F3F3F3F3F383F3F3F383F383F3F3F383E08),
.INIT_34(256'h3F383F383F3F14003F3F3E083F383F383F383F383F3F3F3F3F383F383F3F1400),
.INIT_35(256'h3E083F3F3F383F383F383F383F3F14003F3F3E083F383F383F383F383F3F3F3F),
.INIT_36(256'h3E083F383F383F383E083F3F3F383F383F383F383F3F3F383E083F383F383F38),
.INIT_37(256'h3F383F3F3F3F3F383F3F3F383F383F383F383F3F3F383F3F3F383F383F3F3F38),
.INIT_38(256'h3F383F3F3F3F3F3F3F383F3F3F3F3F3F3F3F3F383F383F3F3F383F3F3F3F3F3F),
.INIT_39(256'h3F383F3F000D3F383F38000D3F383F3F3F3F3F3F3F3F3F3F3F383F3F3F3F3F38),
.INIT_3A(256'h3F3F3F3F3F3F3F3F3F3F3F383F3F3F383F38000D3F383F3F3F3F3F3F3F3F3F3F),
.INIT_3B(256'h3E083F3F3F38000D371D3F3F3F3F3F3F3F3F1D373F3F3F383E083E083F383F3F),
.INIT_3C(256'h3F383F3F3F383F383F3F3F3F3F3F3F3F3F383F3F000D3F383F38000D3F3F3F38),
.INIT_3D(256'h3F3F3E083F383F3F3F383F3F3F383F38233F3F3F3F3F000D3F383F3F3F3F3F38),
.INIT_3E(256'h3F38233F3E083E08233F3E083F38233F3F383E08233F3F3F3F38000D3E083E08),
.INIT_3F(256'h3E08233F3E083F38233F3F383E08233F233F3F383F38233F3F383E08000D3F3F),
.INIT_40(256'h3F3F3F383F3F233F3E08233F371D3F38000D1D373E08000D3F3F3F383F3F3F3F),
.INIT_41(256'h233F3F383F3F371D3F383F38000D3F383F3F233F3F383F38233F3F383F3F233F),
.INIT_42(256'h000D1D373F3F000D3E083F383F3F371D3F383F38000D3F383F3F233F3F383F38),
.INIT_43(256'h3F38233F3F383F3F3F3F220F220F233F233F3F38371D233F3F38233F371D3F3F),
.INIT_44(256'h000000000000000000000000000000000000000000000000233F3F38371D233F),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(18),
.READ_WIDTH_B(18),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(18),
.WRITE_WIDTH_B(18))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina[11:6],1'b0,1'b0,dina[5:0]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:16],\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_37 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_38 ,douta[11:6],\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_45 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_46 ,douta[5:0]}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:2],\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_87 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88 }),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({wea,wea,wea,wea}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_top" *)
module bg_low_blk_mem_gen_top
(douta,
clka,
addra,
dina,
wea);
output [11:0]douta;
input clka;
input [10:0]addra;
input [11:0]dina;
input [0:0]wea;
wire [10:0]addra;
wire clka;
wire [11:0]dina;
wire [11:0]douta;
wire [0:0]wea;
bg_low_blk_mem_gen_generic_cstr \valid.cstr
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.wea(wea));
endmodule
(* C_ADDRA_WIDTH = "11" *) (* C_ADDRB_WIDTH = "11" *) (* C_ALGORITHM = "1" *)
(* C_AXI_ID_WIDTH = "4" *) (* C_AXI_SLAVE_TYPE = "0" *) (* C_AXI_TYPE = "1" *)
(* C_BYTE_SIZE = "9" *) (* C_COMMON_CLK = "0" *) (* C_COUNT_18K_BRAM = "0" *)
(* C_COUNT_36K_BRAM = "1" *) (* C_CTRL_ECC_ALGO = "NONE" *) (* C_DEFAULT_DATA = "0" *)
(* C_DISABLE_WARN_BHV_COLL = "0" *) (* C_DISABLE_WARN_BHV_RANGE = "0" *) (* C_ELABORATION_DIR = "./" *)
(* C_ENABLE_32BIT_ADDRESS = "0" *) (* C_EN_DEEPSLEEP_PIN = "0" *) (* C_EN_ECC_PIPE = "0" *)
(* C_EN_RDADDRA_CHG = "0" *) (* C_EN_RDADDRB_CHG = "0" *) (* C_EN_SAFETY_CKT = "0" *)
(* C_EN_SHUTDOWN_PIN = "0" *) (* C_EN_SLEEP_PIN = "0" *) (* C_EST_POWER_SUMMARY = "Estimated Power for IP : 2.5912999999999999 mW" *)
(* C_FAMILY = "artix7" *) (* C_HAS_AXI_ID = "0" *) (* C_HAS_ENA = "0" *)
(* C_HAS_ENB = "0" *) (* C_HAS_INJECTERR = "0" *) (* C_HAS_MEM_OUTPUT_REGS_A = "1" *)
(* C_HAS_MEM_OUTPUT_REGS_B = "0" *) (* C_HAS_MUX_OUTPUT_REGS_A = "0" *) (* C_HAS_MUX_OUTPUT_REGS_B = "0" *)
(* C_HAS_REGCEA = "0" *) (* C_HAS_REGCEB = "0" *) (* C_HAS_RSTA = "0" *)
(* C_HAS_RSTB = "0" *) (* C_HAS_SOFTECC_INPUT_REGS_A = "0" *) (* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *)
(* C_INITA_VAL = "0" *) (* C_INITB_VAL = "0" *) (* C_INIT_FILE = "bg_low.mem" *)
(* C_INIT_FILE_NAME = "bg_low.mif" *) (* C_INTERFACE_TYPE = "0" *) (* C_LOAD_INIT_FILE = "1" *)
(* C_MEM_TYPE = "0" *) (* C_MUX_PIPELINE_STAGES = "0" *) (* C_PRIM_TYPE = "1" *)
(* C_READ_DEPTH_A = "1092" *) (* C_READ_DEPTH_B = "1092" *) (* C_READ_WIDTH_A = "12" *)
(* C_READ_WIDTH_B = "12" *) (* C_RSTRAM_A = "0" *) (* C_RSTRAM_B = "0" *)
(* C_RST_PRIORITY_A = "CE" *) (* C_RST_PRIORITY_B = "CE" *) (* C_SIM_COLLISION_CHECK = "ALL" *)
(* C_USE_BRAM_BLOCK = "0" *) (* C_USE_BYTE_WEA = "0" *) (* C_USE_BYTE_WEB = "0" *)
(* C_USE_DEFAULT_DATA = "0" *) (* C_USE_ECC = "0" *) (* C_USE_SOFTECC = "0" *)
(* C_USE_URAM = "0" *) (* C_WEA_WIDTH = "1" *) (* C_WEB_WIDTH = "1" *)
(* C_WRITE_DEPTH_A = "1092" *) (* C_WRITE_DEPTH_B = "1092" *) (* C_WRITE_MODE_A = "WRITE_FIRST" *)
(* C_WRITE_MODE_B = "WRITE_FIRST" *) (* C_WRITE_WIDTH_A = "12" *) (* C_WRITE_WIDTH_B = "12" *)
(* C_XDEVICEFAMILY = "artix7" *) (* ORIG_REF_NAME = "blk_mem_gen_v8_3_5" *) (* downgradeipidentifiedwarnings = "yes" *)
module bg_low_blk_mem_gen_v8_3_5
(clka,
rsta,
ena,
regcea,
wea,
addra,
dina,
douta,
clkb,
rstb,
enb,
regceb,
web,
addrb,
dinb,
doutb,
injectsbiterr,
injectdbiterr,
eccpipece,
sbiterr,
dbiterr,
rdaddrecc,
sleep,
deepsleep,
shutdown,
rsta_busy,
rstb_busy,
s_aclk,
s_aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
s_axi_injectsbiterr,
s_axi_injectdbiterr,
s_axi_sbiterr,
s_axi_dbiterr,
s_axi_rdaddrecc);
input clka;
input rsta;
input ena;
input regcea;
input [0:0]wea;
input [10:0]addra;
input [11:0]dina;
output [11:0]douta;
input clkb;
input rstb;
input enb;
input regceb;
input [0:0]web;
input [10:0]addrb;
input [11:0]dinb;
output [11:0]doutb;
input injectsbiterr;
input injectdbiterr;
input eccpipece;
output sbiterr;
output dbiterr;
output [10:0]rdaddrecc;
input sleep;
input deepsleep;
input shutdown;
output rsta_busy;
output rstb_busy;
input s_aclk;
input s_aresetn;
input [3:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input s_axi_awvalid;
output s_axi_awready;
input [11:0]s_axi_wdata;
input [0:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [3:0]s_axi_bid;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [3:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input s_axi_arvalid;
output s_axi_arready;
output [3:0]s_axi_rid;
output [11:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
input s_axi_injectsbiterr;
input s_axi_injectdbiterr;
output s_axi_sbiterr;
output s_axi_dbiterr;
output [10:0]s_axi_rdaddrecc;
wire \<const0> ;
wire [10:0]addra;
wire clka;
wire [11:0]dina;
wire [11:0]douta;
wire [0:0]wea;
assign dbiterr = \<const0> ;
assign doutb[11] = \<const0> ;
assign doutb[10] = \<const0> ;
assign doutb[9] = \<const0> ;
assign doutb[8] = \<const0> ;
assign doutb[7] = \<const0> ;
assign doutb[6] = \<const0> ;
assign doutb[5] = \<const0> ;
assign doutb[4] = \<const0> ;
assign doutb[3] = \<const0> ;
assign doutb[2] = \<const0> ;
assign doutb[1] = \<const0> ;
assign doutb[0] = \<const0> ;
assign rdaddrecc[10] = \<const0> ;
assign rdaddrecc[9] = \<const0> ;
assign rdaddrecc[8] = \<const0> ;
assign rdaddrecc[7] = \<const0> ;
assign rdaddrecc[6] = \<const0> ;
assign rdaddrecc[5] = \<const0> ;
assign rdaddrecc[4] = \<const0> ;
assign rdaddrecc[3] = \<const0> ;
assign rdaddrecc[2] = \<const0> ;
assign rdaddrecc[1] = \<const0> ;
assign rdaddrecc[0] = \<const0> ;
assign rsta_busy = \<const0> ;
assign rstb_busy = \<const0> ;
assign s_axi_arready = \<const0> ;
assign s_axi_awready = \<const0> ;
assign s_axi_bid[3] = \<const0> ;
assign s_axi_bid[2] = \<const0> ;
assign s_axi_bid[1] = \<const0> ;
assign s_axi_bid[0] = \<const0> ;
assign s_axi_bresp[1] = \<const0> ;
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_bvalid = \<const0> ;
assign s_axi_dbiterr = \<const0> ;
assign s_axi_rdaddrecc[10] = \<const0> ;
assign s_axi_rdaddrecc[9] = \<const0> ;
assign s_axi_rdaddrecc[8] = \<const0> ;
assign s_axi_rdaddrecc[7] = \<const0> ;
assign s_axi_rdaddrecc[6] = \<const0> ;
assign s_axi_rdaddrecc[5] = \<const0> ;
assign s_axi_rdaddrecc[4] = \<const0> ;
assign s_axi_rdaddrecc[3] = \<const0> ;
assign s_axi_rdaddrecc[2] = \<const0> ;
assign s_axi_rdaddrecc[1] = \<const0> ;
assign s_axi_rdaddrecc[0] = \<const0> ;
assign s_axi_rdata[11] = \<const0> ;
assign s_axi_rdata[10] = \<const0> ;
assign s_axi_rdata[9] = \<const0> ;
assign s_axi_rdata[8] = \<const0> ;
assign s_axi_rdata[7] = \<const0> ;
assign s_axi_rdata[6] = \<const0> ;
assign s_axi_rdata[5] = \<const0> ;
assign s_axi_rdata[4] = \<const0> ;
assign s_axi_rdata[3] = \<const0> ;
assign s_axi_rdata[2] = \<const0> ;
assign s_axi_rdata[1] = \<const0> ;
assign s_axi_rdata[0] = \<const0> ;
assign s_axi_rid[3] = \<const0> ;
assign s_axi_rid[2] = \<const0> ;
assign s_axi_rid[1] = \<const0> ;
assign s_axi_rid[0] = \<const0> ;
assign s_axi_rlast = \<const0> ;
assign s_axi_rresp[1] = \<const0> ;
assign s_axi_rresp[0] = \<const0> ;
assign s_axi_rvalid = \<const0> ;
assign s_axi_sbiterr = \<const0> ;
assign s_axi_wready = \<const0> ;
assign sbiterr = \<const0> ;
GND GND
(.G(\<const0> ));
bg_low_blk_mem_gen_v8_3_5_synth inst_blk_mem_gen
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_v8_3_5_synth" *)
module bg_low_blk_mem_gen_v8_3_5_synth
(douta,
clka,
addra,
dina,
wea);
output [11:0]douta;
input clka;
input [10:0]addra;
input [11:0]dina;
input [0:0]wea;
wire [10:0]addra;
wire clka;
wire [11:0]dina;
wire [11:0]douta;
wire [0:0]wea;
bg_low_blk_mem_gen_top \gnbram.gnativebmg.native_blk_mem_gen
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.wea(wea));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__MUX4_4_V
`define SKY130_FD_SC_LP__MUX4_4_V
/**
* mux4: 4-input multiplexer.
*
* Verilog wrapper for mux4 with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__mux4.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__mux4_4 (
X ,
A0 ,
A1 ,
A2 ,
A3 ,
S0 ,
S1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A0 ;
input A1 ;
input A2 ;
input A3 ;
input S0 ;
input S1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__mux4 base (
.X(X),
.A0(A0),
.A1(A1),
.A2(A2),
.A3(A3),
.S0(S0),
.S1(S1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__mux4_4 (
X ,
A0,
A1,
A2,
A3,
S0,
S1
);
output X ;
input A0;
input A1;
input A2;
input A3;
input S0;
input S1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__mux4 base (
.X(X),
.A0(A0),
.A1(A1),
.A2(A2),
.A3(A3),
.S0(S0),
.S1(S1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__MUX4_4_V
|
module top_with_timer_4
(
input wire clk,
//input events
input wire VPulse_eI_1,
input wire VPulse_eI_2,
input wire VPulse_eI_3,
input wire VPulse_eI_4,
//output events
output wire VPace_eO_1,
output wire VPace_eO_2,
output wire VPace_eO_3,
output wire VPace_eO_4,
output wire VRefractory_eO_1,
output wire VRefractory_eO_2,
output wire VRefractory_eO_3,
output wire VRefractory_eO_4,
input reset
);
top_with_timer t1(
.clk(clk),
//input events
.VPulse_eI(VPulse_eI_1),
//output events
.VPace_eO(VPace_eO_1),
.VRefractory_eO(VRefractory_eO_1),
.reset(reset)
);
top_with_timer t2(
.clk(clk),
//input events
.VPulse_eI(VPulse_eI_2),
//output events
.VPace_eO(VPace_eO_2),
.VRefractory_eO(VRefractory_eO_2),
.reset(reset)
);
top_with_timer t3(
.clk(clk),
//input events
.VPulse_eI(VPulse_eI_3),
//output events
.VPace_eO(VPace_eO_3),
.VRefractory_eO(VRefractory_eO_3),
.reset(reset)
);
top_with_timer t4(
.clk(clk),
//input events
.VPulse_eI(VPulse_eI_4),
//output events
.VPace_eO(VPace_eO_4),
.VRefractory_eO(VRefractory_eO_4),
.reset(reset)
);
endmodule
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlconcat:2.1
// IP Revision: 1
(* X_CORE_INFO = "xlconcat_v2_1_1_xlconcat,Vivado 2017.2" *)
(* CHECK_LICENSE_TYPE = "bd_350b_slot_0_w_0,xlconcat_v2_1_1_xlconcat,{}" *)
(* CORE_GENERATION_INFO = "bd_350b_slot_0_w_0,xlconcat_v2_1_1_xlconcat,{x_ipProduct=Vivado 2017.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlconcat,x_ipVersion=2.1,x_ipCoreRevision=1,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,IN0_WIDTH=1,IN1_WIDTH=1,IN2_WIDTH=1,IN3_WIDTH=1,IN4_WIDTH=1,IN5_WIDTH=1,IN6_WIDTH=1,IN7_WIDTH=1,IN8_WIDTH=1,IN9_WIDTH=1,IN10_WIDTH=1,IN11_WIDTH=1,IN12_WIDTH=1,IN13_WIDTH=1,IN14_WIDTH=1,IN15_WIDTH=1,IN16_WIDTH=1,IN17_WIDTH=1,IN18_WIDTH=1,IN19_WIDTH=1,IN20_WIDTH=1,IN21_WIDTH=1,IN22_WIDTH=1,IN23_WI\
DTH=1,IN24_WIDTH=1,IN25_WIDTH=1,IN26_WIDTH=1,IN27_WIDTH=1,IN28_WIDTH=1,IN29_WIDTH=1,IN30_WIDTH=1,IN31_WIDTH=1,dout_width=2,NUM_PORTS=2}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module bd_350b_slot_0_w_0 (
In0,
In1,
dout
);
input wire [0 : 0] In0;
input wire [0 : 0] In1;
output wire [1 : 0] dout;
xlconcat_v2_1_1_xlconcat #(
.IN0_WIDTH(1),
.IN1_WIDTH(1),
.IN2_WIDTH(1),
.IN3_WIDTH(1),
.IN4_WIDTH(1),
.IN5_WIDTH(1),
.IN6_WIDTH(1),
.IN7_WIDTH(1),
.IN8_WIDTH(1),
.IN9_WIDTH(1),
.IN10_WIDTH(1),
.IN11_WIDTH(1),
.IN12_WIDTH(1),
.IN13_WIDTH(1),
.IN14_WIDTH(1),
.IN15_WIDTH(1),
.IN16_WIDTH(1),
.IN17_WIDTH(1),
.IN18_WIDTH(1),
.IN19_WIDTH(1),
.IN20_WIDTH(1),
.IN21_WIDTH(1),
.IN22_WIDTH(1),
.IN23_WIDTH(1),
.IN24_WIDTH(1),
.IN25_WIDTH(1),
.IN26_WIDTH(1),
.IN27_WIDTH(1),
.IN28_WIDTH(1),
.IN29_WIDTH(1),
.IN30_WIDTH(1),
.IN31_WIDTH(1),
.dout_width(2),
.NUM_PORTS(2)
) inst (
.In0(In0),
.In1(In1),
.In2(1'B0),
.In3(1'B0),
.In4(1'B0),
.In5(1'B0),
.In6(1'B0),
.In7(1'B0),
.In8(1'B0),
.In9(1'B0),
.In10(1'B0),
.In11(1'B0),
.In12(1'B0),
.In13(1'B0),
.In14(1'B0),
.In15(1'B0),
.In16(1'B0),
.In17(1'B0),
.In18(1'B0),
.In19(1'B0),
.In20(1'B0),
.In21(1'B0),
.In22(1'B0),
.In23(1'B0),
.In24(1'B0),
.In25(1'B0),
.In26(1'B0),
.In27(1'B0),
.In28(1'B0),
.In29(1'B0),
.In30(1'B0),
.In31(1'B0),
.dout(dout)
);
endmodule
|
module premuat1_4(
i_0,
i_1,
i_2,
i_3,
o_0,
o_1,
o_2,
o_3
);
// ********************************************
//
// INPUT / OUTPUT DECLARATION
//
// ********************************************
input signed [18:0] i_0;
input signed [18:0] i_1;
input signed [18:0] i_2;
input signed [18:0] i_3;
output signed [18:0] o_0;
output signed [18:0] o_1;
output signed [18:0] o_2;
output signed [18:0] o_3;
// ********************************************
//
// Combinational Logic
//
// ********************************************
assign o_0=i_0;
assign o_1=i_2;
assign o_2=i_1;
assign o_3=i_3;
endmodule
|
module DDS(
clk,
reset,
key_s4,
clk_25M,
out_wave,
choose
);
parameter WIDTH = 8;
parameter N = 16;
input [2:0] choose;
input key_s4;
reg [N-1:0] data;
input clk;
input reset;
output [WIDTH-1:0] out_wave;
reg [WIDTH-1:0] sine;
reg [WIDTH-1:0] AM;
reg [WIDTH-1:0] FM;
reg [WIDTH-1:0] ASK;
reg [WIDTH-1:0] FSK;
reg [WIDTH-1:0] out_wave;
output clk_25M;
reg [N-1:0] ADD_A;
reg [N-1:0] ADD_B;
reg [N-1:0] ADD_C;
reg [N-1:0] ADD_D;
wire [WIDTH-1:0] sine_D;
wire [WIDTH-1:0] sine_D_high;
wire [WIDTH-1:0] FM_D;
wire [WIDTH-1:0] AM_D;
wire [WIDTH-1:0] ROM_Address;
wire [WIDTH-1:0] ROM_Address_high;
assign ROM_Address = ADD_B[N-1:N-WIDTH];
assign ROM_Address_high = ADD_D[N-1:N-WIDTH];
reg clk_25M;
reg clk_4;
reg clk_3;
integer count;
integer count2;
initial
begin
clk_4 <= 0;
clk_3 <= 0;
clk_25M <= 0;
count = 0;
data = 16'h0080;
count2 = 0;
ASK <= 0;
FSK <= 0;
end
always @ (posedge clk_4 or negedge reset)
begin
if(!reset)
begin
ADD_A <= 0;
ADD_B <= 0;
sine <= 0;
AM <= 0;
FM <= 0;
end
else
begin
ADD_A <= data;
ADD_B <= ADD_B + ADD_A;
sine <= sine_D;
AM <= AM_D;
FM <= FM_D;
end
end
sine_ROM sine_ROM_inst (
.address ( ROM_Address ),
.clock ( clk_4 ),
.q ( sine_D )
);
AM_ROM AM_ROM_inst (
.address ( ROM_Address ),
.clock ( clk_4 ),
.q ( AM_D )
);
FM_ROM FM_ROM_inst (
.address ( ROM_Address ),
.clock ( clk_4 ),
.q ( FM_D )
);
sine_ROM sine_ROM_high_inst (
.address ( ROM_Address_high ),
.clock ( clk_3 ),
.q ( sine_D_high )
);
always @ (posedge clk)
begin
if(count >= 9)
begin
count <= 0;
clk_4 <= ~clk_4;
end
else count <= count+1;
end
always @ (posedge clk)
begin
if(count2 >= 4)
begin
count2 <= 0;
clk_3 <= ~clk_3;
end
else count2 <= count2+1;
end
always @ (posedge clk)
clk_25M <= ~clk_25M;
always @ (posedge clk_25M)
case (choose)
3'b000:out_wave <= sine;
3'b001:out_wave <= AM;
3'b010:out_wave <= FM;
3'b011:out_wave <= ASK;
3'b100:out_wave <= FSK;
default:out_wave <= 0;
endcase
always @ (posedge clk_3 or negedge reset)
begin
if(!reset)
begin
ADD_C <= 0;
ADD_D <= 0;
end
else
begin
ADD_C <= data;
ADD_D <= ADD_D + ADD_C;
end
end
always @ (posedge clk_4)
begin
if (key_s4)
ASK <= sine_D;
else
ASK <= 0;
end
always @ (posedge clk_3)
begin
if (key_s4)
FSK <= sine_D_high;
else
FSK <= sine_D;
end
endmodule
|
/*
-- ============================================================================
-- FILE NAME : id_reg.v
-- DESCRIPTION : ID¥¹¥Æ©`¥¸¥Ñ¥¤¥×¥é¥¤¥ó¥ì¥¸¥¹¥¿
-- ----------------------------------------------------------------------------
-- Revision Date Coding_by Comment
-- 1.0.0 2011/06/27 suito ÐÂÒ×÷³É
-- ============================================================================
*/
/********** ¹²Í¨¥Ø¥Ã¥À¥Õ¥¡¥¤¥ë **********/
`include "nettype.h"
`include "global_config.h"
`include "stddef.h"
/********** e¥Ø¥Ã¥À¥Õ¥¡¥¤¥ë **********/
`include "isa.h"
`include "cpu.h"
/********** ¥â¥¸¥å©`¥ë **********/
module id_reg (
/********** ¥¯¥í¥Ã¥¯ & ¥ê¥»¥Ã¥È **********/
input wire clk, // ¥¯¥í¥Ã¥¯
input wire reset, // ·ÇͬÆڥꥻ¥Ã¥È
/********** ¥Ç¥³©`¥É½Y¹û **********/
input wire [`AluOpBus] alu_op, // ALU¥ª¥Ú¥ì©`¥·¥ç¥ó
input wire [`WordDataBus] alu_in_0, // ALUÈëÁ¦ 0
input wire [`WordDataBus] alu_in_1, // ALUÈëÁ¦ 1
input wire br_flag, // ·Ö᪥ե饰
input wire [`MemOpBus] mem_op, // ¥á¥â¥ê¥ª¥Ú¥ì©`¥·¥ç¥ó
input wire [`WordDataBus] mem_wr_data, // ¥á¥â¥êø¤Þz¤ß¥Ç©`¥¿
input wire [`CtrlOpBus] ctrl_op, // ÖÆÓù¥ª¥Ú¥ì©`¥·¥ç¥ó
input wire [`RegAddrBus] dst_addr, // øÓå쥸¥¹¥¿ø¤Þz¤ß¥¢¥É¥ì¥¹
input wire gpr_we_, // øÓå쥸¥¹¥¿ø¤Þz¤ßÓп
input wire [`IsaExpBus] exp_code, // ÀýÍ⥳©`¥É
/********** ¥Ñ¥¤¥×¥é¥¤¥óÖÆÓùÐźŠ**********/
input wire stall, // ¥¹¥È©`¥ë
input wire flush, // ¥Õ¥é¥Ã¥·¥å
/********** IF/ID¥Ñ¥¤¥×¥é¥¤¥ó¥ì¥¸¥¹¥¿ **********/
input wire [`WordAddrBus] if_pc, // ¥×¥í¥°¥é¥à¥«¥¦¥ó¥¿
input wire if_en, // ¥Ñ¥¤¥×¥é¥¤¥ó¥Ç©`¥¿¤ÎÓп
/********** ID/EX¥Ñ¥¤¥×¥é¥¤¥ó¥ì¥¸¥¹¥¿ **********/
output reg [`WordAddrBus] id_pc, // ¥×¥í¥°¥é¥à¥«¥¦¥ó¥¿
output reg id_en, // ¥Ñ¥¤¥×¥é¥¤¥ó¥Ç©`¥¿¤ÎÓп
output reg [`AluOpBus] id_alu_op, // ALU¥ª¥Ú¥ì©`¥·¥ç¥ó
output reg [`WordDataBus] id_alu_in_0, // ALUÈëÁ¦ 0
output reg [`WordDataBus] id_alu_in_1, // ALUÈëÁ¦ 1
output reg id_br_flag, // ·Ö᪥ե饰
output reg [`MemOpBus] id_mem_op, // ¥á¥â¥ê¥ª¥Ú¥ì©`¥·¥ç¥ó
output reg [`WordDataBus] id_mem_wr_data, // ¥á¥â¥êø¤Þz¤ß¥Ç©`¥¿
output reg [`CtrlOpBus] id_ctrl_op, // ÖÆÓù¥ª¥Ú¥ì©`¥·¥ç¥ó
output reg [`RegAddrBus] id_dst_addr, // øÓå쥸¥¹¥¿ø¤Þz¤ß¥¢¥É¥ì¥¹
output reg id_gpr_we_, // øÓå쥸¥¹¥¿ø¤Þz¤ßÓп
output reg [`IsaExpBus] id_exp_code // ÀýÍ⥳©`¥É
);
/********** ¥Ñ¥¤¥×¥é¥¤¥ó¥ì¥¸¥¹¥¿ **********/
always @(posedge clk or `RESET_EDGE reset) begin
if (reset == `RESET_ENABLE) begin
/* ·ÇͬÆڥꥻ¥Ã¥È */
id_pc <= #1 `WORD_ADDR_W'h0;
id_en <= #1 `DISABLE;
id_alu_op <= #1 `ALU_OP_NOP;
id_alu_in_0 <= #1 `WORD_DATA_W'h0;
id_alu_in_1 <= #1 `WORD_DATA_W'h0;
id_br_flag <= #1 `DISABLE;
id_mem_op <= #1 `MEM_OP_NOP;
id_mem_wr_data <= #1 `WORD_DATA_W'h0;
id_ctrl_op <= #1 `CTRL_OP_NOP;
id_dst_addr <= #1 `REG_ADDR_W'd0;
id_gpr_we_ <= #1 `DISABLE_;
id_exp_code <= #1 `ISA_EXP_NO_EXP;
end else begin
/* ¥Ñ¥¤¥×¥é¥¤¥ó¥ì¥¸¥¹¥¿¤Î¸üР*/
if (stall == `DISABLE) begin
if (flush == `ENABLE) begin // ¥Õ¥é¥Ã¥·¥å
id_pc <= #1 `WORD_ADDR_W'h0;
id_en <= #1 `DISABLE;
id_alu_op <= #1 `ALU_OP_NOP;
id_alu_in_0 <= #1 `WORD_DATA_W'h0;
id_alu_in_1 <= #1 `WORD_DATA_W'h0;
id_br_flag <= #1 `DISABLE;
id_mem_op <= #1 `MEM_OP_NOP;
id_mem_wr_data <= #1 `WORD_DATA_W'h0;
id_ctrl_op <= #1 `CTRL_OP_NOP;
id_dst_addr <= #1 `REG_ADDR_W'd0;
id_gpr_we_ <= #1 `DISABLE_;
id_exp_code <= #1 `ISA_EXP_NO_EXP;
end else begin // ´Î¤Î¥Ç©`¥¿
id_pc <= #1 if_pc;
id_en <= #1 if_en;
id_alu_op <= #1 alu_op;
id_alu_in_0 <= #1 alu_in_0;
id_alu_in_1 <= #1 alu_in_1;
id_br_flag <= #1 br_flag;
id_mem_op <= #1 mem_op;
id_mem_wr_data <= #1 mem_wr_data;
id_ctrl_op <= #1 ctrl_op;
id_dst_addr <= #1 dst_addr;
id_gpr_we_ <= #1 gpr_we_;
id_exp_code <= #1 exp_code;
end
end
end
end
endmodule
|
/*
* .--------------. .----------------. .------------.
* | .------------. | .--------------. | .----------. |
* | | ____ ____ | | | ____ ____ | | | ______ | |
* | ||_ || _|| | ||_ \ / _|| | | .' ___ || |
* ___ _ __ ___ _ __ | | | |__| | | | | | \/ | | | |/ .' \_|| |
* / _ \| '_ \ / _ \ '_ \ | | | __ | | | | | |\ /| | | | || | | |
* (_) | |_) | __/ | | || | _| | | |_ | | | _| |_\/_| |_ | | |\ `.___.'\| |
* \___/| .__/ \___|_| |_|| ||____||____|| | ||_____||_____|| | | `._____.'| |
* | | | | | | | | | | | |
* |_| | '------------' | '--------------' | '----------' |
* '--------------' '----------------' '------------'
*
* openHMC - An Open Source Hybrid Memory Cube Controller
* (C) Copyright 2014 Computer Architecture Group - University of Heidelberg
* www.ziti.uni-heidelberg.de
* B6, 26
* 68159 Mannheim
* Germany
*
* Contact: [email protected]
* http://ra.ziti.uni-heidelberg.de/openhmc
*
* This source file is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This source file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this source file. If not, see <http://www.gnu.org/licenses/>.
*
*
* Module name: openhmc_sync_fifo
*
*/
`default_nettype none
module openhmc_sync_fifo #(
`ifdef CAG_ASSERTIONS
parameter DISABLE_EMPTY_ASSERT = 0,
parameter DISABLE_SHIFT_OUT_ASSERT = 0,
parameter DISABLE_XCHECK_ASSERT = 0,
`endif
parameter DATASIZE = 8,
parameter ADDRSIZE = 8
) (
//----------------------------------
//----SYSTEM INTERFACE
//----------------------------------
input wire clk,
input wire res_n,
//----------------------------------
//----Signals
//----------------------------------
input wire [DATASIZE-1:0] d_in,
input wire shift_in,
input wire shift_out,
output wire [DATASIZE-1:0] d_out,
output wire empty
);
//=====================================================================================================
//-----------------------------------------------------------------------------------------------------
//---------WIRING AND SIGNAL STUFF---------------------------------------------------------------------
//-----------------------------------------------------------------------------------------------------
//=====================================================================================================
wire si, so; // internal gated shift signals
reg full_r1, full_r2;
wire full_1, full_2, full_3;
reg full_m2, full_m1;
reg [DATASIZE-1:0] d_out_r1, d_out_r2;
wire [DATASIZE-1:0] d_out_m2, d_out_2, d_out_3;
wire mux_rm_2;
reg [ADDRSIZE -1:0] ra_m, wa_m; //addr after register similar to signal internal to sram
reg [ADDRSIZE -1:0] ra, wa; // address calculated for the next read
wire wen, ren;
wire m_empty;
assign full_1 = full_r1 || full_m1 || (full_m2 && full_r2);
assign full_2 = full_r2 || full_m2;
//=====================================================================================================
//-----------------------------------------------------------------------------------------------------
//---------LOGIC STARTS HERE---------------------------------------------------------------------------
//-----------------------------------------------------------------------------------------------------
//=====================================================================================================
always @ (posedge clk or negedge res_n) begin
if (!res_n) begin
d_out_r1 <= {DATASIZE {1'b0}};
d_out_r2 <= {DATASIZE {1'b0}};
full_r1 <= 1'b0;
full_r2 <= 1'b0;
end else begin
// Register stage 1 (conditions shouldn't overlap)
if ((full_2 && !full_1 && si && !so) || // fill stage
(full_1 && m_empty && si && so)) begin // shift through
d_out_r1 <= d_in;
full_r1 <= 1'b1;
end
if (full_r1 && so && (!si || !m_empty)) begin // shift out
full_r1 <= 1'b0;
end
// Register stage 2 (conditions shouldn't overlap)
if (full_3 && ((!full_2 && si && !so) || // fill stage
(full_2 && !full_1 && si && so))) begin // shift through
d_out_r2 <= d_in;
full_r2 <= 1'b1;
end
if (full_r1 && so) begin // shift through
d_out_r2 <= d_out_r1;
full_r2 <= 1'b1;
end
if (full_m2 && ((!full_r2 && !so) || // Rescue
(full_r2 && so))) begin
d_out_r2 <= d_out_m2;
full_r2 <= 1'b1;
end
if (full_r2 &&
((!full_r1 && !full_m2 && so && !si) || // shift out
(full_m1 && si && so))) begin // shift through with RAM
full_r2 <= 1'b0;
end
end
end
// assign outputs and inputs to module interface
assign d_out = d_out_3;
assign empty = !full_3; // if the last stage is empty, the fifo is empty
assign si = shift_in;
assign so = shift_out;
wire [ADDRSIZE:0] fifo_ram_count = wa_m - ra_m;
assign mux_rm_2 = full_r2; // mux control of SRAM data bypass if only one value in stage r2
assign d_out_2 = mux_rm_2 ? d_out_r2 : d_out_m2; // additional data mux for SRAM bypass
// write port control of SRAM
assign wen = si && !so && full_1 // enter new value into SRAM, because regs are filled
|| si && !m_empty; // if a value is in the SRAM, then we have to shift through or shift in
// read port control of SRAM
assign ren = so && !m_empty;
assign m_empty = (wa_m == ra_m);
always @ (posedge clk or negedge res_n) begin
if (!res_n) begin
full_m1 <= 1'b0;
full_m2 <= 1'b0;
end else begin
full_m1 <= ren; // no control of m1
full_m2 <= full_m1
|| full_m2 && !so && full_r2; // no rescue possible
end
end
// pointer management
always @(*) begin
wa = wa_m + 1'b1; // wa_m is the address stored in mem addr register
ra = ra_m + 1'b1;
end
always @ (posedge clk or negedge res_n) begin
if (!res_n) begin
wa_m <= {ADDRSIZE {1'b0}};
ra_m <= {ADDRSIZE {1'b0}};
end else begin
if (wen) begin
wa_m <= wa; // next mem write addr to mem addr register
end
if (ren) begin
ra_m <= ra;
end
end
end
//=====================================================================================================
//-----------------------------------------------------------------------------------------------------
//---------INSTANTIATIONS HERE-------------------------------------------------------------------------
//-----------------------------------------------------------------------------------------------------
//=====================================================================================================
openhmc_sync_fifo_reg_stage #(.DWIDTH(DATASIZE))
sync_fifo_reg_stage_3_I (
.clk(clk),
.res_n(res_n),
.d_in(d_in),
.d_in_p(d_out_2),
.p_full(full_2),
.n_full(1'b1),
.si(si),
.so(so),
.full(full_3),
.d_out(d_out_3)
);
openhmc_ram #(
.DATASIZE(DATASIZE), // Memory data word width
.ADDRSIZE(ADDRSIZE), // Number of memory address bits
.PIPELINED(1)
)
ram(
.clk(clk),
.wen(wen),
.wdata(d_in),
.waddr(wa),
.ren(ren),
.raddr(ra),
.rdata(d_out_m2)
);
`ifdef CAG_ASSERTIONS
if (DISABLE_SHIFT_OUT_ASSERT == 0)
shift_out_and_empty: assert property (@(posedge clk) disable iff(!res_n) (shift_out |-> !empty));
if (DISABLE_XCHECK_ASSERT == 0)
dout_known: assert property (@(posedge clk) disable iff(!res_n) (!empty |-> !$isunknown(d_out)));
final
begin
if (DISABLE_EMPTY_ASSERT == 0)
begin
empty_not_set_assert: assert (empty);
end
end
`endif // CAG_ASSERTIONS
endmodule
`default_nettype wire
|
/*
* vga.v
*
* VGA signal generator. Generates hsync/vsync timing, and retrieves
* pixel data from async FIFO.
*
* (C) Arlet Ottens, <[email protected]>
*/
module vga(
input clk, // main clock
output reg vtrigger, // start of new screen (clk domain)
input [15:0] fifo_data, // fifo data (clk domain)
input fifo_write, // fifo write enable (clk domain)
output fifo_full, // fifo full signal (clk domain)
input pclk, // pixel clock input (async)
output reg hsync, // horizontal sync output (pclk domain)
output reg vsync, // vertical sync output (pclk domain)
output [15:0] rgb // 16 bit RGB-565 output (pclk domain)
);
/*
* states (used for both H and V state machines)
*/
parameter
VIDEO = 2'd0, // active video area
FRONT = 2'd1, // front porch
SYNC = 2'd2, // sync pulse
BACK = 2'd3; // back porch
/*
* horizontal state
*/
reg [11:0] hcount = 0; // down counter for horizontal state
reg [1:0] hnext = SYNC; // next horizontal state
wire hcount_done = hcount <= 1; // done when count is 1 (or 0).
reg [11:0] htiming[3:0]; // horizontal timing lookup table
reg next_line; // one cycle trigger for vertical state
reg hactive = 0; // '1' during active display
/*
* vertical state
*/
reg [11:0] vcount = 0; // down counter for vertical state
reg [1:0] vnext = BACK; // next vertical state
wire vcount_done = vcount <= 1; // done when count is 1 (or 0).
reg [11:0] vtiming[3:0]; // vertical timing lookup table
reg vactive = 0; // '1' during active display
initial begin
htiming[VIDEO] = 640;
htiming[FRONT] = 16;
htiming[SYNC] = 96;
htiming[BACK] = 48;
vtiming[VIDEO] = 480;
vtiming[FRONT] = 10;
vtiming[SYNC] = 2;
vtiming[BACK] = 33;
end
initial
$monitor( "%d", vnext );
/*
* horizontal logic
*/
always @(posedge pclk)
if( hcount_done )
hcount <= htiming[hnext];
else
hcount <= hcount - 1;
always @(posedge pclk)
if( hcount_done )
hnext <= hnext + 1;
always @(posedge pclk) begin
hsync <= hnext == BACK;
hactive <= hnext == FRONT;
end
always @(posedge pclk)
next_line <= hcount_done & hsync;
/*
* vertical logic
*/
always @(posedge pclk)
if( next_line )
if( vcount_done )
vcount <= vtiming[vnext];
else
vcount <= vcount - 1;
always @(posedge pclk)
if( next_line )
if( vcount_done )
vnext <= vnext + 1;
always @(posedge pclk) begin
vsync <= vnext == BACK;
vactive <= vnext == FRONT;
end
reg vsync0;
reg vsync1;
reg vsync2;
/*
* synchronize vsync to 'clk' domain:
* generate one cycle trigger when vsync falls
*/
always @(posedge clk) begin
vsync0 <= vsync;
vsync1 <= vsync0;
vsync2 <= vsync1;
vtrigger <= vsync2 & ~vsync1;
end
/*
* data output
*/
wire [17:0] fifo_out;
wire fifo_read = hnext == FRONT && vnext == FRONT;
wire fifo_empty;
/*
* fifo for incoming pixel data
*/
async_fifo fifo(
.clka(clk),
.in({2'b0,fifo_data}),
.wr(fifo_write),
.full(fifo_full),
.clkb(pclk),
.out(fifo_out),
.rd(fifo_read),
.empty(fifo_empty)
);
assign rgb = hactive & vactive ? fifo_out[15:0] : 0;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A21BO_BLACKBOX_V
`define SKY130_FD_SC_LS__A21BO_BLACKBOX_V
/**
* a21bo: 2-input AND into first input of 2-input OR,
* 2nd input inverted.
*
* X = ((A1 & A2) | (!B1_N))
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__a21bo (
X ,
A1 ,
A2 ,
B1_N
);
output X ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__A21BO_BLACKBOX_V
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_bb
//
// Generated
// by: wig
// on: Tue Jun 27 05:12:12 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../verilog.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_bb.v,v 1.6 2006/07/04 09:54:11 wig Exp $
// $Date: 2006/07/04 09:54:11 $
// $Log: ent_bb.v,v $
// Revision 1.6 2006/07/04 09:54:11 wig
// Update more testcases, add configuration/cfgfile
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
//
// Generator: mix_0.pl Revision: 1.46 , [email protected]
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of ent_bb
//
// No user `defines in this module
module ent_bb
//
// Generated Module inst_bb
//
(
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
endmodule
//
// End of Generated Module rtl of ent_bb
//
//
//!End of Module/s
// --------------------------------------------------------------
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__CLKDLYINV3SD3_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__CLKDLYINV3SD3_BEHAVIORAL_PP_V
/**
* clkdlyinv3sd3: Clock Delay Inverter 3-stage 0.50um length inner
* stage gate.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__clkdlyinv3sd3 (
Y ,
A ,
VPWR,
VGND
);
// Module ports
output Y ;
input A ;
input VPWR;
input VGND;
// Local signals
wire not0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y , A );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, not0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__CLKDLYINV3SD3_BEHAVIORAL_PP_V
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: sparc_tlu_dec64.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Module Name: sparc_tlu_dec64
// Description:
// 6 -> 64 decoder
*/
module sparc_tlu_dec64(/*AUTOARG*/
// Outputs
out,
// Inputs
in
);
input [5:0] in;
output [63:0] out;
wire [5:0] in;
reg [63:0] out;
integer i;
always @ (in)
begin
for (i=0;i<64;i=i+1)
begin
if (i[5:0] == in[5:0])
out[i] = 1'b1;
else
out[i] = 1'b0;
end
end
endmodule // sparc_tlu_dec64
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O2BB2A_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__O2BB2A_BEHAVIORAL_PP_V
/**
* o2bb2a: 2-input NAND and 2-input OR into 2-input AND.
*
* X = (!(A1 & A2) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__o2bb2a (
X ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out ;
wire or0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
nand nand0 (nand0_out , A2_N, A1_N );
or or0 (or0_out , B2, B1 );
and and0 (and0_out_X , nand0_out, or0_out );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__O2BB2A_BEHAVIORAL_PP_V
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_r_l2d_32k.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
//FPGA_SYN enables all FPGA related modifications
`ifdef FPGA_SYN
`define FPGA_SYN_RED
`endif
module bw_r_l2d_32k (/*AUTOARG*/
// Outputs
decc_out, so, l2d_fuse_data_out,
// Inputs
decc_in_l, decc_read_in, word_en_l, way_sel_l, set_l,
col_offset_l, wr_en_l, rclk, arst_l, mem_write_disable,
sehold, se, si, fuse_l2d_wren, fuse_l2d_rden,
fuse_l2d_rid, fuse_clk1, fuse_clk2,
fuse_l2d_data_in, fuse_read_data_in
);
input [155:0] decc_in_l;
input [155:0] decc_read_in;
input [3:0] word_en_l;
input [1:0] way_sel_l;
input [9:0] set_l;
input col_offset_l;
input wr_en_l;
input rclk;
input arst_l;
// Test signals
input mem_write_disable;
input sehold;
input se;
input si;
// Efuse inputs
input fuse_l2d_wren;
input fuse_l2d_rden;
input [2:0] fuse_l2d_rid;
input fuse_clk1;
input fuse_clk2;
input fuse_l2d_data_in;
input fuse_read_data_in;
output [155:0] decc_out ;
output so;
// Efuse outputs
output l2d_fuse_data_out;
reg [155:0] tmp_decc_out;
reg [155:0] decc_out_tmp;
reg [155:0] reg_decc_in;
`ifdef DEFINE_0IN
`else
reg [155:0] way0_decc[1023:0] ;
reg [155:0] way1_decc[1023:0] ;
`endif
wire acc_en_d1;
reg [1:0] way_sel_d1;
reg [9:0] set_d1;
reg [3:0] word_en_d1;
reg wr_en_d1;
reg [155:0] decc_in_d1;
reg [155:0] decc_out_d1;
reg col_offset_d1;
wire [1:0] way_sel_sehold;
wire [9:0] set_sehold;
wire [3:0] word_en_sehold;
wire wr_en_sehold;
wire [155:0] decc_in_sehold;
wire col_offset;
wire [155:0] decc_out ;
// JC begin
// Because of this 2 cycle block,
// The following codes are just helping me for Innologic verification
// stop_1_cyc: when col_offset = 1, the next cycle will be ignore
// keep_rd_out: The output data will be kept for another cycle
reg keep_rd_out;
reg stop_1_cyc;
always @(posedge rclk) begin
if (col_offset && (|way_sel_sehold)) begin
stop_1_cyc <= 1'b1;
end
else stop_1_cyc <= 1'b0;
if (acc_en_d1 & ~wr_en_d1) begin
keep_rd_out <= 1'b1;
end
else keep_rd_out <= 1'b0;
end
// JC end
assign wr_en_sehold = (sehold) ? wr_en_d1 : ~wr_en_l;
assign set_sehold = (sehold) ? set_d1 : ~set_l;
assign way_sel_sehold = (sehold) ? way_sel_d1 : ~way_sel_l;
assign word_en_sehold = (sehold) ? word_en_d1 : ~word_en_l;
// In Circuits, we use se to disable write, however, I modified testbench as following
// to verify write disable:
// force inno_tb_top.xtor.xcnt.se_l = ~mem_write_disable ;
assign col_offset = (stop_1_cyc || mem_write_disable ) ? (1'b0) : ~col_offset_l ;
assign acc_en_d1 = col_offset_d1 & (|way_sel_d1);
always @(posedge rclk) begin
col_offset_d1 <= col_offset;
way_sel_d1 <= way_sel_sehold;
set_d1 <= set_sehold;
word_en_d1 <= word_en_sehold;
wr_en_d1 <= wr_en_sehold;
// JC
// EVEN THOUGH We don't have any write data latch,
// Our write-data drivers act like latch which gating by
// Worden signals.
decc_in_d1 <= ~decc_in_l;
// JC
//This is NOT output flops, but we can keep read outs for
// 2 cycles.
decc_out_d1 <= decc_out_tmp;
end
`ifdef DEFINE_0IN
wire [155:0] decc_out0, decc_out1;
wire [155:0] wm = { {39{word_en_d1[3]}}, {39{word_en_d1[2]}}, {39{word_en_d1[1]}}, {39{word_en_d1[0]}} };
wire we0 = acc_en_d1 & wr_en_d1 & way_sel_d1[0];
wire we1 = acc_en_d1 & wr_en_d1 & way_sel_d1[1];
l2data_axis data_array0 (.data_out (decc_out0[155:0]),
.rclk (rclk),
.adr (set_d1[9:0]),
.data_in (decc_in_d1[155:0]),
.we (we0),
.wm (wm[155:0]) );
l2data_axis data_array1 (.data_out (decc_out1[155:0]),
.rclk (rclk),
.adr (set_d1[9:0]),
.data_in (decc_in_d1[155:0]),
.we (we1),
.wm (wm[155:0]) );
always @(/*AUTOSENSE*/acc_en_d1 or decc_in_d1 or decc_out0
or decc_out1 or way_sel_d1 or word_en_d1 or wr_en_d1) begin
if (acc_en_d1 & ~wr_en_d1) begin
//////////////////////////
// 16 or 64B byte read
//////////////////////////
decc_out_tmp = way_sel_d1[0] ? decc_out0[155:0] : decc_out1[155:0];
end
if (acc_en_d1 & wr_en_d1) begin
//////////////////////////
// Store word/dword OR 64B store
//////////////////////////
tmp_decc_out = way_sel_d1[0] ? decc_out0[155:0] : decc_out1[155:0];
//////////////////////////////////////
// Write data based on Word enables.
//////////////////////////////////////
reg_decc_in[155:117] = (decc_in_d1[155:117] & {39{word_en_d1[3]}} |
tmp_decc_out[155:117] & {39{~word_en_d1[3]}});
reg_decc_in[116:78] = (decc_in_d1[116:78] & {39{word_en_d1[2]}} |
tmp_decc_out[116:78] & {39{~word_en_d1[2]}});
reg_decc_in[77:39] = (decc_in_d1[77:39] & {39{word_en_d1[1]}} |
tmp_decc_out[77:39] & {39{~word_en_d1[1]}});
reg_decc_in[38:0] = (decc_in_d1[38:0] & {39{word_en_d1[0]}} |
tmp_decc_out[38:0] & {39{~word_en_d1[0]}});
//////////////////////////////////////////////////////////
// the store data gets reflected onto the read output bus
//////////////////////////////////////////////////////////
// decc_out_tmp[155:0] = reg_decc_in[155:0];
// Store data is *not* reflected onto the read output bus in the physical implementation
decc_out_tmp[155:0] = 156'b0;
end // of write operation
if (~acc_en_d1) begin
// no access
decc_out_tmp[155:0] = 156'b0;
end
end // of always block
`else
always @(/*AUTOSENSE*/acc_en_d1 or decc_in_d1 or set_d1
or way_sel_d1 or word_en_d1 or wr_en_d1) begin
`ifdef INNO_MUXEX
`else
//----- PURELY FOR VERIFICATION -----------------------
if(wr_en_d1==1'bx) begin
`ifdef MODELSIM
$display("L2_DATA_ERR"," wr en error %b ", wr_en_d1);
`else
$error("L2_DATA_ERR"," wr en error %b ", wr_en_d1);
`endif
end
//----- PURELY FOR VERIFICATION -----------------------
`endif
//////////////////
// MEMORY ACCESS
//////////////////
if (acc_en_d1) begin
`ifdef INNO_MUXEX
`else
//----- PURELY FOR VERIFICATION -----------------------
if(set_d1==10'bx) begin
`ifdef MODELSIM
$error("L2_DATA_ERR"," index error %h ", set_d1[9:0]);
`else
$display("L2_DATA_ERR"," index error %h ", set_d1[9:0]);
`endif
end
//----- PURELY FOR VERIFICATION -----------------------
`endif
if (~wr_en_d1) begin
//////////////////////////
// 16 or 64B byte read
//////////////////////////
decc_out_tmp = way_sel_d1[0] ? way0_decc[set_d1] : way1_decc[set_d1];
//JC: For keeping data for 2 cycle
// keep_rd_out = 2'b01;
end
else begin
//////////////////////////
// Store word/dword OR 64B store
//////////////////////////
tmp_decc_out = way_sel_d1[0] ? way0_decc[set_d1] : way1_decc[set_d1];
// keep_rd_out = 2'b00;
//////////////////////////////////////
// Write data based on Word enables.
//////////////////////////////////////
reg_decc_in[155:117] = (decc_in_d1[155:117] & {39{word_en_d1[3]}} |
tmp_decc_out[155:117] & {39{~word_en_d1[3]}});
reg_decc_in[116:78] = (decc_in_d1[116:78] & {39{word_en_d1[2]}} |
tmp_decc_out[116:78] & {39{~word_en_d1[2]}});
reg_decc_in[77:39] = (decc_in_d1[77:39] & {39{word_en_d1[1]}} |
tmp_decc_out[77:39] & {39{~word_en_d1[1]}});
reg_decc_in[38:0] = (decc_in_d1[38:0] & {39{word_en_d1[0]}} |
tmp_decc_out[38:0] & {39{~word_en_d1[0]}});
if (way_sel_d1[0]) way0_decc[set_d1] = reg_decc_in;
if (way_sel_d1[1]) way1_decc[set_d1] = reg_decc_in;
//////////////////////////////////////////////////////////
// the store data gets reflected onto the read output bus
//////////////////////////////////////////////////////////
// decc_out_tmp[155:0] = reg_decc_in[155:0];
// Store data is *not* reflected onto the read output bus in the physical implementation
decc_out_tmp[155:0] = 156'b0;
end // of write operation
end
else begin
// no access
decc_out_tmp[155:0] = 156'b0;
end
end // of always block
`endif
// Modeling wired-OR
// JC we don't have any flop in this level
// assign decc_out[155:0] = decc_out_d1[155:0] | decc_read_in[155:0];
assign decc_out[155:0] = (acc_en_d1 & ~wr_en_d1) ? 156'bX : (keep_rd_out) ?
(decc_out_d1[155:0] | decc_read_in[155:0]) :
(decc_out_tmp[155:0] | decc_read_in[155:0]);
/////////////////////////////////////////////////////////////////////
// Redundancy Registers
/////////////////////////////////////////////////////////////////////
reg [8:0] s_red_reg0;
reg [8:0] s_red_reg1;
reg [8:0] s_red_reg2;
reg [8:0] s_red_reg3;
reg [8:0] s_red_reg4;
reg [8:0] s_red_reg5;
reg [8:0] m_red_reg0;
reg [8:0] m_red_reg1;
reg [8:0] m_red_reg2;
reg [8:0] m_red_reg3;
reg [8:0] m_red_reg4;
reg [8:0] m_red_reg5;
wire l2d_fuse_data_out;
assign l2d_fuse_data_out = s_red_reg5[8];
always @(arst_l or fuse_clk1 or fuse_l2d_rid or fuse_l2d_wren or fuse_l2d_rden
or fuse_l2d_data_in or fuse_read_data_in
or s_red_reg0 or s_red_reg1 or s_red_reg2
or s_red_reg3 or s_red_reg4 or s_red_reg5) begin
if (!arst_l) begin
m_red_reg0[8:0] = 9'b0;
m_red_reg1[8:0] = 9'b0;
m_red_reg2[8:0] = 9'b0;
m_red_reg3[8:0] = 9'b0;
m_red_reg4[8:0] = 9'b0;
m_red_reg5[8:0] = 9'b0;
end
if (arst_l && fuse_clk1) begin
/////////////////////////////////
// Write operation
/////////////////////////////////
if (fuse_l2d_wren) begin
case (fuse_l2d_rid) //selecting among the six registers
3'b101: m_red_reg0[8:0] = {s_red_reg0[7:0], fuse_l2d_data_in};// bottom odd row
3'b011: m_red_reg1[8:0] = {s_red_reg1[7:0], fuse_l2d_data_in};// bottom even row
3'b010: m_red_reg2[8:0] = {s_red_reg2[7:0], fuse_l2d_data_in};// bottom column
3'b100: m_red_reg3[8:0] = {s_red_reg3[7:0], fuse_l2d_data_in};// top odd row
3'b001: m_red_reg4[8:0] = {s_red_reg4[7:0], fuse_l2d_data_in};// top even row
3'b000: m_red_reg5[8:0] = {s_red_reg5[7:0], fuse_l2d_data_in};// top column
default: ;
endcase // case(fuse_l2d_rid)
end // if (fuse_l2d_wren)
/////////////////////////////////
// Read operation
/////////////////////////////////
//JC This is just temporary fix for read operation, rid = 3'b111 will turn on everything
else if (fuse_l2d_rden) begin
m_red_reg0[8:0] = {s_red_reg0[7:0], fuse_read_data_in};
m_red_reg1[8:0] = {s_red_reg1[7:0], s_red_reg0[8]};
m_red_reg2[8:0] = {s_red_reg2[7:0], s_red_reg1[8]};
m_red_reg3[8:0] = {s_red_reg3[7:0], s_red_reg2[8]};
m_red_reg4[8:0] = {s_red_reg4[7:0], s_red_reg3[8]};
m_red_reg5[8:0] = {s_red_reg5[7:0], s_red_reg4[8]};
end // if (fuse_l2d_rden)
end // if (fuse_clk1)
end // always @ (fuse_clk1 or...
// always @(posedge efc_scdata_fuse_clk1) begin
always @(arst_l or fuse_clk2 or fuse_l2d_rid or fuse_l2d_wren or fuse_l2d_rden
or m_red_reg0 or m_red_reg1 or m_red_reg2
or m_red_reg3 or m_red_reg4 or m_red_reg5) begin
`ifdef DEFINE_0IN
`else
`ifdef FPGA_SYN_RED
`else
if (!arst_l) begin
m_red_reg0[8:0] = 9'b0;
m_red_reg1[8:0] = 9'b0;
m_red_reg2[8:0] = 9'b0;
m_red_reg3[8:0] = 9'b0;
m_red_reg4[8:0] = 9'b0;
m_red_reg5[8:0] = 9'b0;
end
`endif
`endif
if (fuse_clk2) begin
if (fuse_l2d_wren) begin
case (fuse_l2d_rid) //selecting among the six registers
3'b101: s_red_reg0[8:0] = m_red_reg0[8:0];// bottom odd row
3'b011: s_red_reg1[8:0] = m_red_reg1[8:0];// bottom even row
3'b010: s_red_reg2[8:0] = m_red_reg2[8:0];// bottom column
3'b100: s_red_reg3[8:0] = m_red_reg3[8:0];// top odd row
3'b001: s_red_reg4[8:0] = m_red_reg4[8:0];// top even row
3'b000: s_red_reg5[8:0] = m_red_reg5[8:0];// top column
default: ;
endcase // case(fuse_l2d_rid)
end // if (fuse_l2d_wren)
else if (fuse_l2d_rden) begin
s_red_reg0[8:0] = m_red_reg0[8:0];// bottom odd row
s_red_reg1[8:0] = m_red_reg1[8:0];// bottom even row
s_red_reg2[8:0] = m_red_reg2[8:0];// bottom column
s_red_reg3[8:0] = m_red_reg3[8:0];// top odd row
s_red_reg4[8:0] = m_red_reg4[8:0];// top even row
s_red_reg5[8:0] = m_red_reg5[8:0];// top column
end // if (fuse_l2d_rden)
end // if (fuse_clk2)
end // always @ (fuse_clk2 or...
endmodule // bw_r_l2d_32k
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__FA_BEHAVIORAL_V
`define SKY130_FD_SC_HS__FA_BEHAVIORAL_V
/**
* fa: Full adder.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__fa (
COUT,
SUM ,
A ,
B ,
CIN ,
VPWR,
VGND
);
// Module ports
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
input VPWR;
input VGND;
// Local signals
wire CIN or0_out ;
wire CIN and0_out ;
wire CIN and1_out ;
wire csi_opt_276, nor0_out ;
wire csi_opt_276, nor1_out ;
wire or1_out_COUT ;
wire u_vpwr_vgnd0_out_COUT;
wire and2_out ;
wire or2_out_SUM ;
wire u_vpwr_vgnd1_out_SUM ;
// Name Output Other arguments
or or0 (or0_out , CIN, B );
and and0 (and0_out , or0_out, A );
and and1 (and1_out , B, CIN );
or or1 (or1_out_COUT , and1_out, and0_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_COUT, or1_out_COUT, VPWR, VGND);
buf buf0 (COUT , u_vpwr_vgnd0_out_COUT );
and and2 (and2_out , CIN, A, B );
nor nor0 (nor0_out , A, or0_out );
nor nor1 (nor1_out , nor0_out, COUT );
or or2 (or2_out_SUM , nor1_out, and2_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd1 (u_vpwr_vgnd1_out_SUM , or2_out_SUM, VPWR, VGND );
buf buf1 (SUM , u_vpwr_vgnd1_out_SUM );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__FA_BEHAVIORAL_V
|
/*
* DSI Core
* Copyright (C) 2013-2014 twl <[email protected]>
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 3 of the License, or (at your option) any later version.
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
*/
`timescale 1ns/1ps
`include "dsi_defs.vh"
/*
* dsi_timing_gen.v
*
* Image timing generator - produces the display refresh timing (hsync, vsync, blanking, etc.)
* The image is delivered by a simple FIFO interface, pixel-by-pixel. The output requests
* particular packets from the Packet Assembler.
*/
module dsi_timing_gen
(
clk_i,
rst_n_i,
fifo_empty_i,
fifo_rd_o,
fifo_pixels_i,
pix_vsync_i,
pix_next_frame_o,
p_req_o,
p_islong_o,
p_type_o,
p_wcount_o,
p_command_o,
p_payload_o,
p_dreq_i,
p_last_o,
host_a_i,
host_d_i,
host_d_o,
host_wr_i
);
parameter g_pixels_per_clock = 1;
localparam g_pixel_width = g_pixels_per_clock * 24;
input clk_i;
input rst_n_i;
input fifo_empty_i;
output fifo_rd_o;
input [g_pixel_width - 1: 0] fifo_pixels_i;
input pix_vsync_i;
output reg pix_next_frame_o;
output reg p_req_o, p_islong_o;
output reg [5:0] p_type_o;
output reg [15:0] p_wcount_o, p_command_o;
output [g_pixel_width-1:0] p_payload_o;
input p_dreq_i;
output reg p_last_o;
input [3:0] host_a_i;
input [31:0] host_d_i;
output reg [31:0] host_d_o;
input host_wr_i;
`define ST_BPORCH 0
`define ST_FPORCH 1
`define ST_HSYNC_START 2
`define ST_HSYNC_END 3
`define ST_HSYNC_ACTIVE 4
`define ST_LINE 6
`define ST_VSYNC_PACKET 7
`define ST_STOP 8
`define ST_LONG_PACKET 9
`define ST_LP 10
reg [3:0] state, next_state;
reg [11:0] h_count, v_count;
reg [11:0] h_front_porch, h_back_porch, h_active, h_total;
reg [11:0] v_front_porch, v_back_porch, v_active, v_total;
reg enable = 0;
reg disp_en_mask;
reg [11:0] pixel_counter, pixel_counter_d0;
reg force_lp = 0;
// host registers
always@(posedge clk_i)
if(!rst_n_i)
begin
enable <= 0;
force_lp <= 0;
end else if(host_wr_i) begin
case (host_a_i)
0:h_front_porch <= host_d_i;
1:h_back_porch <= host_d_i;
2:h_active <= host_d_i;
3:h_total <= host_d_i;
4:v_front_porch <= host_d_i;
5:v_back_porch <= host_d_i;
6:v_active <= host_d_i;
7:v_total <= host_d_i;
8: begin
enable<=host_d_i[0];
force_lp <= host_d_i[1];
end
endcase // case (host_a_i)
end
task send(input long, input [5:0] ptype, input [15:0] count, input[3:0] _next_state, input is_last);
begin
if(p_dreq_i) begin
p_islong_o <= long;
p_type_o <= ptype;
p_wcount_o <= count;
p_command_o <= 0;
p_last_o <= is_last;
pixel_counter <= count;
if(long)
state <= `ST_LONG_PACKET;
else
state <= _next_state;
next_state <= _next_state;
end // if (p_dreq_i)
end
endtask // send
reg push_pixels, push_pixels_d0;
reg waiting_frame = 0;
always@(posedge clk_i)
if(!rst_n_i || !enable) begin
v_count <= 0;
state <= `ST_LP;
pixel_counter <= h_total;
p_req_o <= 0;
p_last_o <= 0;
disp_en_mask <= 0;
push_pixels <= 0;
push_pixels_d0 <= 0;
pix_next_frame_o <= 0;
end else begin
push_pixels_d0 <= push_pixels;
case (state)
`ST_FPORCH:
begin
push_pixels<=0;
push_pixels_d0<=0;
if(v_count == v_back_porch) begin
disp_en_mask <= 1;
end else if(v_count == v_front_porch) begin
disp_en_mask <= 0;
end
if(force_lp) begin
p_req_o <= 0;
state <= `ST_LP;
pixel_counter <= 0;
end else
send(1, `PTYPE_BLANKING, h_front_porch, `ST_HSYNC_START, 0);
end // case: `ST_FPORCH
`ST_HSYNC_START: begin
p_req_o <= 1;
if(v_count == 0)
send(0, `PTYPE_VSYNC_START, h_total, `ST_BPORCH, 0);
else if (v_count == v_total)
send(0, `PTYPE_HSYNC_START, h_total, `ST_LP, 1);
else
send(0, `PTYPE_HSYNC_START, h_total, `ST_BPORCH, 0);
end
`ST_BPORCH:
send(1, `PTYPE_BLANKING, h_back_porch, `ST_LINE, 0);
`ST_LINE:
begin
send(1, disp_en_mask ? `PTYPE_RGB24: `PTYPE_BLANKING, h_active, `ST_FPORCH, 0);
if(p_dreq_i) begin
if(v_count == v_total)
v_count <= 0;
else
v_count <= v_count + 1;
push_pixels <= disp_en_mask;
end
end
`ST_LP: begin
p_req_o <= 0;
if(pixel_counter == 0) begin
if(pix_vsync_i && !force_lp) begin
state <= `ST_HSYNC_START;
pix_next_frame_o <= 0;
end
v_count <= 0;
end else begin
pix_next_frame_o <= 1;
pixel_counter <= pixel_counter - 1;
end // else: !if(pixel_counter == 0)
end
`ST_LONG_PACKET:
begin
if(p_dreq_i) begin
pixel_counter <= pixel_counter - ( 3 * g_pixels_per_clock );
pixel_counter_d0 <= pixel_counter;
end
if(pixel_counter == 0)
begin
push_pixels <=0;
state <= next_state;
end
end
endcase // case (state)
end // else: !if(!rst_n_i || !enable)
assign fifo_rd_o = (push_pixels && p_dreq_i);
assign p_payload_o = (push_pixels || push_pixels_d0 ? fifo_pixels_i : 0);
endmodule // dsi_timing_gen
|
//-------------------------------------------------------------------------
// This Verilog file was developed by Altera Corporation. It may be
// freely copied and/or distributed at no cost. Any persons using this
// file for any purpose do so at their own risk, and are responsible for
// the results of such use. Altera Corporation does not guarantee that
// this file is complete, correct, or fit for any particular purpose.
// NO WARRANTY OF ANY KIND IS EXPRESSED OR IMPLIED. This notice must
// accompany any copy of this file.
//------------------------------------------------------------------------
//
// Quartus Prime 16.1.0 Build 196 10/24/2016
//
//------------------------------------------------------------------------
// LPM Synthesizable Models (Support string type generic)
// These models are based on LPM version 220 (EIA-IS103 October 1998).
//------------------------------------------------------------------------
//
//-----------------------------------------------------------------------------
// Assumptions:
//
// 1. The default value for LPM_SVALUE, LPM_AVALUE, LPM_PVALUE, and
// LPM_STRENGTH is string UNUSED.
//
//-----------------------------------------------------------------------------
// Verilog Language Issues:
//
// Two dimensional ports are not supported. Modules with two dimensional
// ports are implemented as one dimensional signal of (LPM_SIZE * LPM_WIDTH)
// bits wide.
//
//-----------------------------------------------------------------------------
//START_MODULE_NAME------------------------------------------------------------
//
// Module Name : LPM_MEMORY_INITIALIZATION
//
// Description : Common function to read intel-hex format data file with
// extension .hex and creates the equivalent verilog format
// data file with extension .ver.
//
// Limitation : Supports only record type '00'(data record), '01'(end of
// file record) and '02'(extended segment address record).
//
// Results expected: Creates the verilog format data file with extension .ver
// and return the name of the file.
//
//END_MODULE_NAME--------------------------------------------------------------
//See also: https://github.com/twosigma/verilator_support
// verilator lint_off COMBDLY
// verilator lint_off INITIALDLY
// verilator lint_off MULTIDRIVEN
// verilator lint_off UNSIGNED
// verilator lint_off WIDTH
// BEGINNING OF MODULE
`timescale 1 ps / 1 ps
`define LPM_TRUE 1
`define LPM_FALSE 0
`define LPM_NULL 0
`define LPM_EOF -1
`define LPM_MAX_NAME_SZ 128
`define LPM_MAX_WIDTH 256
`define LPM_COLON ":"
`define LPM_DOT "."
`define LPM_NEWLINE "\n"
`define LPM_CARRIAGE_RETURN 8'h0D
`define LPM_SPACE " "
`define LPM_TAB "\t"
`define LPM_OPEN_BRACKET "["
`define LPM_CLOSE_BRACKET "]"
`define LPM_OFFSET 9
`define LPM_H10 8'h10
`define LPM_H10000 20'h10000
`define LPM_AWORD 8
`define LPM_MASK15 32'h000000FF
`define LPM_EXT_STR "ver"
`define LPM_PERCENT "%"
`define LPM_MINUS "-"
`define LPM_SEMICOLON ";"
`define LPM_EQUAL "="
// MODULE DECLARATION
module LPM_MEMORY_INITIALIZATION;
/****************************************************************/
/* convert uppercase character values to lowercase. */
/****************************************************************/
function [8:1] tolower;
input [8:1] given_character;
reg [8:1] conv_char;
begin
if ((given_character >= 65) && (given_character <= 90)) // ASCII number of 'A' is 65, 'Z' is 90
begin
conv_char = given_character + 32; // 32 is the difference in the position of 'A' and 'a' in the ASCII char set
tolower = conv_char;
end
else
tolower = given_character;
end
endfunction
/****************************************************************/
/* Read in Altera-mif format data to verilog format data. */
/****************************************************************/
task convert_mif2ver;
input[`LPM_MAX_NAME_SZ*8 : 1] in_file;
input width;
output [`LPM_MAX_NAME_SZ*8 : 1] out_file;
reg [`LPM_MAX_NAME_SZ*8 : 1] in_file;
reg [`LPM_MAX_NAME_SZ*8 : 1] out_file;
reg [`LPM_MAX_NAME_SZ*8 : 1] buffer;
reg [`LPM_MAX_WIDTH : 0] memory_data1, memory_data2;
reg [8 : 1] c;
reg [3 : 0] hex, tmp_char;
reg [24 : 1] address_radix, data_radix;
reg get_width;
reg get_depth;
reg get_data_radix;
reg get_address_radix;
reg width_found;
reg depth_found;
reg data_radix_found;
reg address_radix_found;
reg get_address_data_pairs;
reg get_address;
reg get_data;
reg display_address;
reg invalid_address;
reg get_start_address;
reg get_end_address;
reg done;
reg error_status;
reg first_rec;
reg last_rec;
integer width;
integer memory_width, memory_depth;
integer value;
integer ifp, ofp, r, r2;
integer i, j, k, m, n;
integer off_addr, nn, address, tt, cc, aah, aal, dd, sum ;
integer start_address, end_address;
integer line_no;
integer character_count;
integer comment_with_percent_found;
integer comment_with_double_minus_found;
begin
done = `LPM_FALSE;
error_status = `LPM_FALSE;
first_rec = `LPM_FALSE;
last_rec = `LPM_FALSE;
comment_with_percent_found = `LPM_FALSE;
comment_with_double_minus_found = `LPM_FALSE;
off_addr= 0;
nn= 0;
address = 0;
start_address = 0;
end_address = 0;
tt= 0;
cc= 0;
aah= 0;
aal= 0;
dd= 0;
sum = 0;
line_no = 1;
c = 0;
hex = 0;
value = 0;
buffer = "";
character_count = 0;
memory_width = 0;
memory_depth = 0;
memory_data1 = {(`LPM_MAX_WIDTH+1) {1'b0}};
memory_data2 = {(`LPM_MAX_WIDTH+1) {1'b0}};
address_radix = "hex";
data_radix = "hex";
get_width = `LPM_FALSE;
get_depth = `LPM_FALSE;
get_data_radix = `LPM_FALSE;
get_address_radix = `LPM_FALSE;
width_found = `LPM_FALSE;
depth_found = `LPM_FALSE;
data_radix_found = `LPM_FALSE;
address_radix_found = `LPM_FALSE;
get_address_data_pairs = `LPM_FALSE;
display_address = `LPM_FALSE;
invalid_address = `LPM_FALSE;
get_start_address = `LPM_FALSE;
get_end_address = `LPM_FALSE;
if((in_file[4*8 : 1] == ".dat") || (in_file[4*8 : 1] == ".DAT"))
out_file = in_file;
else
begin
ifp = $fopen(in_file, "r");
if (ifp == `LPM_NULL)
begin
$display("ERROR: cannot read %0s.", in_file);
$display("Time: %0t Instance: %m", $time);
done = `LPM_TRUE;
end
out_file = in_file;
if((out_file[4*8 : 1] == ".mif") || (out_file[4*8 : 1] == ".MIF"))
out_file[3*8 : 1] = `LPM_EXT_STR;
else
begin
$display("ERROR: Invalid input file name %0s. Expecting file with .mif extension and Altera-mif data format.", in_file);
$display("Time: %0t Instance: %m", $time);
done = `LPM_TRUE;
end
if (!done)
begin
ofp = $fopen(out_file, "w");
if (ofp == `LPM_NULL)
begin
$display("ERROR : cannot write %0s.", out_file);
$display("Time: %0t Instance: %m", $time);
done = `LPM_TRUE;
end
end
while((!done) && (!error_status))
begin : READER
r = $fgetc(ifp);
if (r == `LPM_EOF)
begin
// to do : add more checking on whether a particular assigment(width, depth, memory/address) are mising
if(!first_rec)
begin
error_status = `LPM_TRUE;
$display("WARNING: %0s, Intel-hex data file is empty.", in_file);
$display ("Time: %0t Instance: %m", $time);
end
else if (!get_address_data_pairs)
begin
error_status = `LPM_TRUE;
$display("ERROR: %0s, line %0d, Missing `content begin` statement.", in_file, line_no);
$display("Time: %0t Instance: %m", $time);
end
else if(!last_rec)
begin
error_status = `LPM_TRUE;
$display("ERROR: %0s, line %0d, Missing `end` statement.", in_file, line_no);
$display("Time: %0t Instance: %m", $time);
end
done = `LPM_TRUE;
end
else if ((r == `LPM_NEWLINE) || (r == `LPM_CARRIAGE_RETURN))
begin
if ((buffer == "contentbegin") && (get_address_data_pairs == `LPM_FALSE))
begin
get_address_data_pairs = `LPM_TRUE;
get_address = `LPM_TRUE;
buffer = "";
end
else if (buffer == "content")
begin
// continue to next character
end
else
if (buffer != "")
begin
// found invalid syntax in the particular line.
error_status = `LPM_TRUE;
$display("ERROR: %0s, line %0d, Invalid Altera-mif record.", in_file, line_no);
$display("Time: %0t Instance: %m", $time);
disable READER;
end
line_no = line_no +1;
end
else if ((r == `LPM_SPACE) || (r == `LPM_TAB))
begin
// continue to next character;
end
else if (r == `LPM_PERCENT)
begin
// Ignore all the characters which which is part of comment.
r = $fgetc(ifp);
while ((r != `LPM_PERCENT) && (r != `LPM_NEWLINE) && (r != `LPM_CARRIAGE_RETURN))
begin
r = $fgetc(ifp);
end
if ((r == `LPM_NEWLINE) || (r == `LPM_CARRIAGE_RETURN))
begin
line_no = line_no +1;
if ((buffer == "contentbegin") && (get_address_data_pairs == `LPM_FALSE))
begin
get_address_data_pairs = `LPM_TRUE;
get_address = `LPM_TRUE;
buffer = "";
end
end
end
else if (r == `LPM_MINUS)
begin
r = $fgetc(ifp);
if (r == `LPM_MINUS)
begin
// Ignore all the characters which which is part of comment.
r = $fgetc(ifp);
while ((r != `LPM_NEWLINE) && (r != `LPM_CARRIAGE_RETURN))
begin
r = $fgetc(ifp);
end
if ((r == `LPM_NEWLINE) || (r == `LPM_CARRIAGE_RETURN))
begin
line_no = line_no +1;
if ((buffer == "contentbegin") && (get_address_data_pairs == `LPM_FALSE))
begin
get_address_data_pairs = `LPM_TRUE;
get_address = `LPM_TRUE;
buffer = "";
end
end
end
else
begin
error_status = `LPM_TRUE;
$display("ERROR: %0s, line %0d, Invalid Altera-mif record.", in_file, line_no);
$display("Time: %0t Instance: %m", $time);
done = `LPM_TRUE;
disable READER;
end
end
else if (r == `LPM_EQUAL)
begin
if (buffer == "width")
begin
if (width_found == `LPM_FALSE)
begin
get_width = `LPM_TRUE;
buffer = "";
end
else
begin
error_status = `LPM_TRUE;
$display("ERROR: %0s, line %0d, Width has already been specified once.", in_file, line_no);
$display("Time: %0t Instance: %m", $time);
end
end
else if (buffer == "depth")
begin
get_depth = `LPM_TRUE;
buffer = "";
end
else if (buffer == "data_radix")
begin
get_data_radix = `LPM_TRUE;
buffer = "";
end
else if (buffer == "address_radix")
begin
get_address_radix = `LPM_TRUE;
buffer = "";
end
else
begin
error_status = `LPM_TRUE;
$display("ERROR: %0s, line %0d, Unknown setting (%0s).", in_file, line_no, buffer);
$display("Time: %0t Instance: %m", $time);
end
end
else if (r == `LPM_COLON)
begin
if (!get_address_data_pairs)
begin
error_status = `LPM_TRUE;
$display("ERROR: %0s, line %0d, Missing `content begin` statement.", in_file, line_no);
$display("Time: %0t Instance: %m", $time);
end
else if (invalid_address == `LPM_TRUE)
begin
error_status = `LPM_TRUE;
$display("ERROR: %0s, line %0d, Invalid data record.", in_file, line_no);
$display("Time: %0t Instance: %m", $time);
end
begin
get_address = `LPM_FALSE;
get_data = `LPM_TRUE;
display_address = `LPM_TRUE;
end
end
else if (r == `LPM_DOT)
begin
r = $fgetc(ifp);
if (r == `LPM_DOT)
begin
if (get_start_address == `LPM_TRUE)
begin
start_address = address;
address = 0;
get_start_address = `LPM_FALSE;
get_end_address = `LPM_TRUE;
end
else
begin
error_status = `LPM_TRUE;
$display("ERROR: %0s, line %0d, Invalid Altera-mif record.", in_file, line_no);
$display("Time: %0t Instance: %m", $time);
done = `LPM_TRUE;
disable READER;
end
end
else
begin
error_status = `LPM_TRUE;
$display("ERROR: %0s, line %0d, Invalid Altera-mif record.", in_file, line_no);
$display("Time: %0t Instance: %m", $time);
done = `LPM_TRUE;
disable READER;
end
end
else if (r == `LPM_OPEN_BRACKET)
begin
get_start_address = `LPM_TRUE;
end
else if (r == `LPM_CLOSE_BRACKET)
begin
if (get_end_address == `LPM_TRUE)
begin
end_address = address;
address = 0;
get_end_address = `LPM_FALSE;
end
else
begin
error_status = `LPM_TRUE;
$display("ERROR: %0s, line %0d, Invalid Altera-mif record.", in_file, line_no);
$display("Time: %0t Instance: %m", $time);
done = `LPM_TRUE;
disable READER;
end
end
else if (r == `LPM_SEMICOLON)
begin
if (get_width == `LPM_TRUE)
begin
width_found = `LPM_TRUE;
memory_width = value;
value = 0;
get_width = `LPM_FALSE;
end
else if (get_depth == `LPM_TRUE)
begin
depth_found = `LPM_TRUE;
memory_depth = value;
value = 0;
get_depth = `LPM_FALSE;
end
else if (get_data_radix == `LPM_TRUE)
begin
data_radix_found = `LPM_TRUE;
get_data_radix = `LPM_FALSE;
if ((buffer == "bin") || (buffer == "oct") || (buffer == "dec") || (buffer == "uns") ||
(buffer == "hex"))
begin
data_radix = buffer[24 : 1];
end
else
begin
error_status = `LPM_TRUE;
$display("ERROR: %0s, line %0d, Invalid assignment (%0s) to data_radix.", in_file, line_no, buffer);
$display("Time: %0t Instance: %m", $time);
end
buffer = "";
end
else if (get_address_radix == `LPM_TRUE)
begin
address_radix_found = `LPM_TRUE;
get_address_radix = `LPM_FALSE;
if ((buffer == "bin") || (buffer == "oct") || (buffer == "dec") || (buffer == "uns") ||
(buffer == "hex"))
begin
address_radix = buffer[24 : 1];
end
else
begin
error_status = `LPM_TRUE;
$display("ERROR: %0s, line %0d, Invalid assignment (%0s) to address radix.", in_file, line_no, buffer);
$display("Time: %0t Instance: %m", $time);
end
buffer = "";
end
else if (buffer == "end")
begin
if (get_address_data_pairs == `LPM_TRUE)
begin
last_rec = `LPM_TRUE;
buffer = "";
end
else
begin
error_status = `LPM_TRUE;
$display("ERROR: %0s, line %0d, Missing `content begin` statement.", in_file, line_no);
$display("Time: %0t Instance: %m", $time);
end
end
else if (get_data == `LPM_TRUE)
begin
get_address = `LPM_TRUE;
get_data = `LPM_FALSE;
buffer = "";
character_count = 0;
if (start_address != end_address)
begin
for (address = start_address; address <= end_address; address = address+1)
begin
$fdisplay(ofp,"@%0h", address);
for (i = memory_width -1; i >= 0; i = i-1 )
begin
hex[(i % 4)] = memory_data1[i];
if ((i % 4) == 0)
begin
$fwrite(ofp, "%0h", hex);
hex = 0;
end
end
$fwrite(ofp, "\n");
end
start_address = 0;
end_address = 0;
address = 0;
hex = 0;
memory_data1 = {(`LPM_MAX_WIDTH+1) {1'b0}};
end
else
begin
if (display_address == `LPM_TRUE)
begin
$fdisplay(ofp,"@%0h", address);
display_address = `LPM_FALSE;
end
for (i = memory_width -1; i >= 0; i = i-1 )
begin
hex[(i % 4)] = memory_data1[i];
if ((i % 4) == 0)
begin
$fwrite(ofp, "%0h", hex);
hex = 0;
end
end
$fwrite(ofp, "\n");
address = 0;
hex = 0;
memory_data1 = {(`LPM_MAX_WIDTH+1) {1'b0}};
end
end
else
begin
error_status = `LPM_TRUE;
$display("ERROR: %0s, line %0d, Invalid assigment.", in_file, line_no);
$display("Time: %0t Instance: %m", $time);
end
end
else if ((get_width == `LPM_TRUE) || (get_depth == `LPM_TRUE))
begin
if ((r >= "0") && (r <= "9"))
value = (value * 10) + (r - 'h30);
else
begin
error_status = `LPM_TRUE;
$display("ERROR: %0s, line %0d, Invalid assignment to width/depth.", in_file, line_no);
$display("Time: %0t Instance: %m", $time);
end
end
else if (get_address == `LPM_TRUE)
begin
if (address_radix == "hex")
begin
if ((r >= "0") && (r <= "9"))
value = (r - 'h30);
else if ((r >= "A") && (r <= "F"))
value = 10 + (r - 'h41);
else if ((r >= "a") && (r <= "f"))
value = 10 + (r - 'h61);
else
begin
invalid_address = `LPM_TRUE;
end
address = (address * 16) + value;
end
else if ((address_radix == "dec"))
begin
if ((r >= "0") && (r <= "9"))
value = (r - 'h30);
else
begin
invalid_address = `LPM_TRUE;
end
address = (address * 10) + value;
end
else if (address_radix == "uns")
begin
if ((r >= "0") && (r <= "9"))
value = (r - 'h30);
else
begin
invalid_address = `LPM_TRUE;
end
address = (address * 10) + value;
end
else if (address_radix == "bin")
begin
if ((r >= "0") && (r <= "1"))
value = (r - 'h30);
else
begin
invalid_address = `LPM_TRUE;
end
address = (address * 2) + value;
end
else if (address_radix == "oct")
begin
if ((r >= "0") && (r <= "7"))
value = (r - 'h30);
else
begin
invalid_address = `LPM_TRUE;
end
address = (address * 8) + value;
end
if ((r >= 65) && (r <= 90))
c = tolower(r);
else
c = r;
{tmp_char,buffer} = {buffer, c};
end
else if (get_data == `LPM_TRUE)
begin
character_count = character_count +1;
if (data_radix == "hex")
begin
if ((r >= "0") && (r <= "9"))
value = (r - 'h30);
else if ((r >= "A") && (r <= "F"))
value = 10 + (r - 'h41);
else if ((r >= "a") && (r <= "f"))
value = 10 + (r - 'h61);
else
begin
error_status = `LPM_TRUE;
$display("ERROR: %0s, line %0d, Invalid data record.", in_file, line_no);
$display("Time: %0t Instance: %m", $time);
done = `LPM_TRUE;
disable READER;
end
memory_data1 = (memory_data1 * 16) + value;
end
else if ((data_radix == "dec"))
begin
if ((r >= "0") && (r <= "9"))
value = (r - 'h30);
else
begin
error_status = `LPM_TRUE;
$display("ERROR: %0s, line %0d, Invalid data record.", in_file, line_no);
$display("Time: %0t Instance: %m", $time);
done = `LPM_TRUE;
disable READER;
end
memory_data1 = (memory_data1 * 10) + value;
end
else if (data_radix == "uns")
begin
if ((r >= "0") && (r <= "9"))
value = (r - 'h30);
else
begin
error_status = `LPM_TRUE;
$display("ERROR: %0s, line %0d, Invalid data record.", in_file, line_no);
$display("Time: %0t Instance: %m", $time);
done = `LPM_TRUE;
disable READER;
end
memory_data1 = (memory_data1 * 10) + value;
end
else if (data_radix == "bin")
begin
if ((r >= "0") && (r <= "1"))
value = (r - 'h30);
else
begin
error_status = `LPM_TRUE;
$display("ERROR: %0s, line %0d, Invalid data record.", in_file, line_no);
$display("Time: %0t Instance: %m", $time);
done = `LPM_TRUE;
disable READER;
end
memory_data1 = (memory_data1 * 2) + value;
end
else if (data_radix == "oct")
begin
if ((r >= "0") && (r <= "7"))
value = (r - 'h30);
else
begin
error_status = `LPM_TRUE;
$display("ERROR: %0s, line %0d, Invalid data record.", in_file, line_no);
$display("Time: %0t Instance: %m", $time);
done = `LPM_TRUE;
disable READER;
end
memory_data1 = (memory_data1 * 8) + value;
end
end
else
begin
first_rec = `LPM_TRUE;
if ((r >= 65) && (r <= 90))
c = tolower(r);
else
c = r;
{tmp_char,buffer} = {buffer, c};
end
end
$fclose(ifp);
$fclose(ofp);
end
end
endtask // convert_mif2ver
/****************************************************************/
/* Read in Intel-hex format data to verilog format data. */
/* Intel-hex format :nnaaaaattddddcc */
/****************************************************************/
task convert_hex2ver;
input[`LPM_MAX_NAME_SZ*8 : 1] in_file;
input width;
output [`LPM_MAX_NAME_SZ*8 : 1] out_file;
reg [`LPM_MAX_NAME_SZ*8 : 1] in_file;
reg [`LPM_MAX_NAME_SZ*8 : 1] out_file;
reg [8:1] c;
reg [3:0] hex, tmp_char;
reg done;
reg error_status;
reg first_rec;
reg last_rec;
integer width;
integer ifp, ofp, r, r2;
integer i, j, k, m, n;
integer off_addr, nn, aaaa, tt, cc, aah, aal, dd, sum ;
integer line_no;
begin
done = `LPM_FALSE;
error_status = `LPM_FALSE;
first_rec = `LPM_FALSE;
last_rec = `LPM_FALSE;
off_addr= 0;
nn= 0;
aaaa= 0;
tt= 0;
cc= 0;
aah= 0;
aal= 0;
dd= 0;
sum = 0;
line_no = 1;
c = 0;
hex = 0;
if((in_file[4*8 : 1] == ".dat") || (in_file[4*8 : 1] == ".DAT"))
out_file = in_file;
else
begin
ifp = $fopen(in_file, "r");
if (ifp == `LPM_NULL)
begin
$display("ERROR: cannot read %0s.", in_file);
$display("Time: %0t Instance: %m", $time);
done = `LPM_TRUE;
end
out_file = in_file;
if((out_file[4*8 : 1] == ".hex") || (out_file[4*8 : 1] == ".HEX"))
out_file[3*8 : 1] = `LPM_EXT_STR;
else
begin
$display("ERROR: Invalid input file name %0s. Expecting file with .hex extension and Intel-hex data format.", in_file);
$display("Time: %0t Instance: %m", $time);
done = `LPM_TRUE;
end
if (!done)
begin
ofp = $fopen(out_file, "w");
if (ofp == `LPM_NULL)
begin
$display("ERROR : cannot write %0s.", out_file);
$display("Time: %0t Instance: %m", $time);
done = `LPM_TRUE;
end
end
while((!done) && (!error_status))
begin : READER
r = $fgetc(ifp);
if (r == `LPM_EOF)
begin
if(!first_rec)
begin
error_status = `LPM_TRUE;
$display("WARNING: %0s, Intel-hex data file is empty.", in_file);
$display ("Time: %0t Instance: %m", $time);
end
else if(!last_rec)
begin
error_status = `LPM_TRUE;
$display("ERROR: %0s, line %0d, Missing the last record.", in_file, line_no);
$display("Time: %0t Instance: %m", $time);
end
end
else if (r == `LPM_COLON)
begin
first_rec = `LPM_TRUE;
nn= 0;
aaaa= 0;
tt= 0;
cc= 0;
aah= 0;
aal= 0;
dd= 0;
sum = 0;
// get record length bytes
for (i = 0; i < 2; i = i+1)
begin
r = $fgetc(ifp);
if ((r >= "0") && (r <= "9"))
nn = (nn * 16) + (r - 'h30);
else if ((r >= "A") && (r <= "F"))
nn = (nn * 16) + 10 + (r - 'h41);
else if ((r >= "a") && (r <= "f"))
nn = (nn * 16) + 10 + (r - 'h61);
else
begin
error_status = `LPM_TRUE;
$display("ERROR: %0s, line %0d, Invalid INTEL HEX record.", in_file, line_no);
$display("Time: %0t Instance: %m", $time);
done = `LPM_TRUE;
disable READER;
end
end
// get address bytes
for (i = 0; i < 4; i = i+1)
begin
r = $fgetc(ifp);
if ((r >= "0") && (r <= "9"))
hex = (r - 'h30);
else if ((r >= "A") && (r <= "F"))
hex = 10 + (r - 'h41);
else if ((r >= "a") && (r <= "f"))
hex = 10 + (r - 'h61);
else
begin
error_status = `LPM_TRUE;
$display("ERROR: %0s, line %0d, Invalid INTEL HEX record.", in_file, line_no);
$display("Time: %0t Instance: %m", $time);
done = `LPM_TRUE;
disable READER;
end
aaaa = (aaaa * 16) + hex;
if (i < 2)
aal = (aal * 16) + hex;
else
aah = (aah * 16) + hex;
end
// get record type bytes
for (i = 0; i < 2; i = i+1)
begin
r = $fgetc(ifp);
if ((r >= "0") && (r <= "9"))
tt = (tt * 16) + (r - 'h30);
else if ((r >= "A") && (r <= "F"))
tt = (tt * 16) + 10 + (r - 'h41);
else if ((r >= "a") && (r <= "f"))
tt = (tt * 16) + 10 + (r - 'h61);
else
begin
error_status = `LPM_TRUE;
$display("ERROR: %0s, line %0d, Invalid INTEL HEX record.", in_file, line_no);
$display("Time: %0t Instance: %m", $time);
done = `LPM_TRUE;
disable READER;
end
end
if((tt == 2) && (nn != 2) )
begin
error_status = `LPM_TRUE;
$display("ERROR: %0s, line %0d, Invalid data record.", in_file, line_no);
$display("Time: %0t Instance: %m", $time);
end
else
begin
// get the sum of all the bytes for record length, address and record types
sum = nn + aah + aal + tt ;
// check the record type
case(tt)
// normal_record
8'h00 :
begin
first_rec = `LPM_TRUE;
i = 0;
k = width / `LPM_AWORD;
if ((width % `LPM_AWORD) != 0)
k = k + 1;
// k = no. of bytes per entry.
while (i < nn)
begin
$fdisplay(ofp,"@%0h", (aaaa + off_addr));
for (j = 1; j <= k; j = j +1)
begin
if ((k - j +1) > nn)
begin
for(m = 1; m <= 2; m= m+1)
begin
if((((k-j)*8) + ((3-m)*4) - width) < 4)
$fwrite(ofp, "0");
end
end
else
begin
// get the data bytes
for(m = 1; m <= 2; m= m+1)
begin
r = $fgetc(ifp);
if ((r >= "0") && (r <= "9"))
hex = (r - 'h30);
else if ((r >= "A") && (r <= "F"))
hex = 10 + (r - 'h41);
else if ((r >= "a") && (r <= "f"))
hex = 10 + (r - 'h61);
else
begin
error_status = `LPM_TRUE;
$display("ERROR: %0s, line %0d, Invalid INTEL HEX record.", in_file, line_no);
$display("Time: %0t Instance: %m", $time);
done = `LPM_TRUE;
disable READER;
end
if((((k-j)*8) + ((3-m)*4) - width) < 4)
$fwrite(ofp, "%h", hex);
dd = (dd * 16) + hex;
if(m % 2 == 0)
begin
sum = sum + dd;
dd = 0;
end
end
end
end
$fwrite(ofp, "\n");
i = i + k;
aaaa = aaaa + 1;
end // end of while (i < nn)
end
// last record
8'h01:
begin
last_rec = `LPM_TRUE;
done = `LPM_TRUE;
end
// address base record
8'h02:
begin
off_addr= 0;
// get the extended segment address record
for(i = 1; i <= (nn*2); i= i+1)
begin
r = $fgetc(ifp);
if ((r >= "0") && (r <= "9"))
hex = (r - 'h30);
else if ((r >= "A") && (r <= "F"))
hex = 10 + (r - 'h41);
else if ((r >= "a") && (r <= "f"))
hex = 10 + (r - 'h61);
else
begin
error_status = `LPM_TRUE;
$display("ERROR: %0s, line %0d, Invalid INTEL HEX record.", in_file, line_no);
$display("Time: %0t Instance: %m", $time);
done = `LPM_TRUE;
disable READER;
end
off_addr = (off_addr * `LPM_H10) + hex;
dd = (dd * 16) + hex;
if(i % 2 == 0)
begin
sum = sum + dd;
dd = 0;
end
end
off_addr = off_addr * `LPM_H10;
end
// address base record
8'h03:
// get the start segment address record
for(i = 1; i <= (nn*2); i= i+1)
begin
r = $fgetc(ifp);
if ((r >= "0") && (r <= "9"))
hex = (r - 'h30);
else if ((r >= "A") && (r <= "F"))
hex = 10 + (r - 'h41);
else if ((r >= "a") && (r <= "f"))
hex = 10 + (r - 'h61);
else
begin
error_status = `LPM_TRUE;
$display("ERROR: %0s, line %0d, Invalid INTEL HEX record.", in_file, line_no);
$display("Time: %0t Instance: %m", $time);
done = `LPM_TRUE;
disable READER;
end
dd = (dd * 16) + hex;
if(i % 2 == 0)
begin
sum = sum + dd;
dd = 0;
end
end
// address base record
8'h04:
begin
off_addr= 0;
// get the extended linear address record
for(i = 1; i <= (nn*2); i= i+1)
begin
r = $fgetc(ifp);
if ((r >= "0") && (r <= "9"))
hex = (r - 'h30);
else if ((r >= "A") && (r <= "F"))
hex = 10 + (r - 'h41);
else if ((r >= "a") && (r <= "f"))
hex = 10 + (r - 'h61);
else
begin
error_status = `LPM_TRUE;
$display("ERROR: %0s, line %0d, Invalid INTEL HEX record.", in_file, line_no);
$display("Time: %0t Instance: %m", $time);
done = `LPM_TRUE;
disable READER;
end
off_addr = (off_addr * `LPM_H10) + hex;
dd = (dd * 16) + hex;
if(i % 2 == 0)
begin
sum = sum + dd;
dd = 0;
end
end
off_addr = off_addr * `LPM_H10000;
end
// address base record
8'h05:
// get the start linear address record
for(i = 1; i <= (nn*2); i= i+1)
begin
r = $fgetc(ifp);
if ((r >= "0") && (r <= "9"))
hex = (r - 'h30);
else if ((r >= "A") && (r <= "F"))
hex = 10 + (r - 'h41);
else if ((r >= "a") && (r <= "f"))
hex = 10 + (r - 'h61);
else
begin
error_status = `LPM_TRUE;
$display("ERROR: %0s, line %0d, Invalid INTEL HEX record.", in_file, line_no);
$display("Time: %0t Instance: %m", $time);
done = `LPM_TRUE;
disable READER;
end
dd = (dd * 16) + hex;
if(i % 2 == 0)
begin
sum = sum + dd;
dd = 0;
end
end
default:
begin
error_status = `LPM_TRUE;
$display("ERROR: %0s, line %0d, Unknown record type.", in_file, line_no);
$display("Time: %0t Instance: %m", $time);
end
endcase
// get the checksum bytes
for (i = 0; i < 2; i = i+1)
begin
r = $fgetc(ifp);
if ((r >= "0") && (r <= "9"))
cc = (cc * 16) + (r - 'h30);
else if ((r >= "A") && (r <= "F"))
cc = 10 + (cc * 16) + (r - 'h41);
else if ((r >= "a") && (r <= "f"))
cc = 10 + (cc * 16) + (r - 'h61);
else
begin
error_status = `LPM_TRUE;
$display("ERROR: %0s, line %0d, Invalid INTEL HEX record.", in_file, line_no);
$display("Time: %0t Instance: %m", $time);
done = `LPM_TRUE;
disable READER;
end
end
// Perform check sum.
if(((~sum+1)& `LPM_MASK15) != cc)
begin
error_status = `LPM_TRUE;
$display("ERROR: %0s, line %0d, Invalid checksum.", in_file, line_no);
$display("Time: %0t Instance: %m", $time);
end
end
end
else if ((r == `LPM_NEWLINE) || (r == `LPM_CARRIAGE_RETURN))
begin
line_no = line_no +1;
end
else if (r == `LPM_SPACE)
begin
// continue to next character;
end
else
begin
error_status = `LPM_TRUE;
$display("ERROR:%0s, line %0d, Invalid INTEL HEX record.", in_file, line_no);
$display("Time: %0t Instance: %m", $time);
done = `LPM_TRUE;
end
end
$fclose(ifp);
$fclose(ofp);
end
end
endtask // convert_hex2ver
task convert_to_ver_file;
input[`LPM_MAX_NAME_SZ*8 : 1] in_file;
input width;
output [`LPM_MAX_NAME_SZ*8 : 1] out_file;
reg [`LPM_MAX_NAME_SZ*8 : 1] in_file;
reg [`LPM_MAX_NAME_SZ*8 : 1] out_file;
integer width;
begin
if((in_file[4*8 : 1] == ".hex") || (in_file[4*8 : 1] == ".HEX") ||
(in_file[4*8 : 1] == ".dat") || (in_file[4*8 : 1] == ".DAT"))
convert_hex2ver(in_file, width, out_file);
else if((in_file[4*8 : 1] == ".mif") || (in_file[4*8 : 1] == ".MIF"))
convert_mif2ver(in_file, width, out_file);
else
begin
$display("ERROR: Invalid input file name %0s. Expecting file with .hex extension (with Intel-hex data format) or .mif extension (with Altera-mif data format).", in_file);
$display("Time: %0t Instance: %m", $time);
end
end
endtask // convert_to_ver_file
endmodule // LPM_MEMORY_INITIALIZATION
//START_MODULE_NAME------------------------------------------------------------
//
// Module Name : LPM_HINT_EVALUATION
//
// Description : Common function to grep the value of altera specific parameters
// within the lpm_hint parameter.
//
// Limitation : No error checking to check whether the content of the lpm_hint
// is valid or not.
//
// Results expected: If the target parameter found, return the value of the parameter.
// Otherwise, return empty string.
//
//END_MODULE_NAME--------------------------------------------------------------
// BEGINNING OF MODULE
`timescale 1 ps / 1 ps
// MODULE DECLARATION
module LPM_HINT_EVALUATION;
// FUNCTON DECLARATION
// This function will search through the string (given string) to look for a match for the
// a given parameter(compare_param_name). It will return the value for the given parameter.
function [8*200:1] GET_PARAMETER_VALUE;
input [8*200:1] given_string; // string to be searched
input [8*50:1] compare_param_name; // parameter name to be looking for in the given_string.
integer param_value_char_count; // to indicate current character count in the param_value
integer param_name_char_count; // to indicate current character count in the param_name
integer white_space_count;
reg extract_param_value; // if 1 mean extracting parameters value from given string
reg extract_param_name; // if 1 mean extracting parameters name from given string
reg param_found; // to indicate whether compare_param_name have been found in the given_string
reg include_white_space; // if 1, include white space in the parameter value
reg [8*200:1] reg_string; // to store the value of the given string
reg [8*50:1] param_name; // to store parameter name
reg [8*20:1] param_value; // to store parameter value
reg [8:1] tmp; // to get the value of the current byte
begin
reg_string = given_string;
param_value_char_count = 0;
param_name_char_count =0;
extract_param_value = 1;
extract_param_name = 0;
param_found = 0;
include_white_space = 0;
white_space_count = 0;
tmp = reg_string[8:1];
// checking every bytes of the reg_string from right to left.
while ((tmp != 0 ) && (param_found != 1))
begin
tmp = reg_string[8:1];
//if tmp != ' ' or should include white space (trailing white space are ignored)
if((tmp != 32) || (include_white_space == 1))
begin
if(tmp == 32)
begin
white_space_count = 1;
end
else if(tmp == 61) // if tmp = '='
begin
extract_param_value = 0;
extract_param_name = 1; // subsequent bytes should be part of param_name
include_white_space = 0; // ignore the white space (if any) between param_name and '='
white_space_count = 0;
param_value = param_value >> (8 * (20 - param_value_char_count));
param_value_char_count = 0;
end
else if (tmp == 44) // if tmp = ','
begin
extract_param_value = 1; // subsequent bytes should be part of param_value
extract_param_name = 0;
param_name = param_name >> (8 * (50 - param_name_char_count));
param_name_char_count = 0;
if(param_name == compare_param_name)
param_found = 1; // the compare_param_name have been found in the reg_string
end
else
begin
if(extract_param_value == 1)
begin
param_value_char_count = param_value_char_count + white_space_count + 1;
include_white_space = 1;
if(white_space_count > 0)
begin
param_value = {8'b100000, param_value[20*8:9]};
white_space_count = 0;
end
param_value = {tmp, param_value[20*8:9]};
end
else if(extract_param_name == 1)
begin
param_name = {tmp, param_name[50*8:9]};
param_name_char_count = param_name_char_count + 1;
end
end
end
reg_string = reg_string >> 8; // shift 1 byte to the right
end
// for the case whether param_name is the left most part of the reg_string
if(extract_param_name == 1)
begin
param_name = param_name >> (8 * (50 - param_name_char_count));
if(param_name == compare_param_name)
param_found = 1;
end
if (param_found == 1)
GET_PARAMETER_VALUE = param_value; // return the value of the parameter been looking for
else
GET_PARAMETER_VALUE = ""; // return empty string if parameter not found
end
endfunction
endmodule // LPM_HINT_EVALUATION
// BEGINNING OF MODULE
`timescale 1 ps / 1 ps
// MODULE DECLARATION
module LPM_DEVICE_FAMILIES;
function IS_FAMILY_CYCLONE;
input[8*20:1] device;
reg is_cyclone;
begin
if ((device == "Cyclone") || (device == "CYCLONE") || (device == "cyclone") || (device == "ACEX2K") || (device == "acex2k") || (device == "ACEX 2K") || (device == "acex 2k") || (device == "Tornado") || (device == "TORNADO") || (device == "tornado"))
is_cyclone = 1;
else
is_cyclone = 0;
IS_FAMILY_CYCLONE = is_cyclone;
end
endfunction //IS_FAMILY_CYCLONE
function IS_FAMILY_MAX3000A;
input[8*20:1] device;
reg is_max3000a;
begin
if ((device == "MAX3000A") || (device == "max3000a") || (device == "MAX 3000A") || (device == "max 3000a"))
is_max3000a = 1;
else
is_max3000a = 0;
IS_FAMILY_MAX3000A = is_max3000a;
end
endfunction //IS_FAMILY_MAX3000A
function IS_FAMILY_MAX7000A;
input[8*20:1] device;
reg is_max7000a;
begin
if ((device == "MAX7000A") || (device == "max7000a") || (device == "MAX 7000A") || (device == "max 7000a"))
is_max7000a = 1;
else
is_max7000a = 0;
IS_FAMILY_MAX7000A = is_max7000a;
end
endfunction //IS_FAMILY_MAX7000A
function IS_FAMILY_MAX7000AE;
input[8*20:1] device;
reg is_max7000ae;
begin
if ((device == "MAX7000AE") || (device == "max7000ae") || (device == "MAX 7000AE") || (device == "max 7000ae"))
is_max7000ae = 1;
else
is_max7000ae = 0;
IS_FAMILY_MAX7000AE = is_max7000ae;
end
endfunction //IS_FAMILY_MAX7000AE
function IS_FAMILY_MAX7000B;
input[8*20:1] device;
reg is_max7000b;
begin
if ((device == "MAX7000B") || (device == "max7000b") || (device == "MAX 7000B") || (device == "max 7000b"))
is_max7000b = 1;
else
is_max7000b = 0;
IS_FAMILY_MAX7000B = is_max7000b;
end
endfunction //IS_FAMILY_MAX7000B
function IS_FAMILY_MAX7000S;
input[8*20:1] device;
reg is_max7000s;
begin
if ((device == "MAX7000S") || (device == "max7000s") || (device == "MAX 7000S") || (device == "max 7000s"))
is_max7000s = 1;
else
is_max7000s = 0;
IS_FAMILY_MAX7000S = is_max7000s;
end
endfunction //IS_FAMILY_MAX7000S
function IS_FAMILY_STRATIXGX;
input[8*20:1] device;
reg is_stratixgx;
begin
if ((device == "Stratix GX") || (device == "STRATIX GX") || (device == "stratix gx") || (device == "Stratix-GX") || (device == "STRATIX-GX") || (device == "stratix-gx") || (device == "StratixGX") || (device == "STRATIXGX") || (device == "stratixgx") || (device == "Aurora") || (device == "AURORA") || (device == "aurora"))
is_stratixgx = 1;
else
is_stratixgx = 0;
IS_FAMILY_STRATIXGX = is_stratixgx;
end
endfunction //IS_FAMILY_STRATIXGX
function IS_FAMILY_STRATIX;
input[8*20:1] device;
reg is_stratix;
begin
if ((device == "Stratix") || (device == "STRATIX") || (device == "stratix") || (device == "Yeager") || (device == "YEAGER") || (device == "yeager"))
is_stratix = 1;
else
is_stratix = 0;
IS_FAMILY_STRATIX = is_stratix;
end
endfunction //IS_FAMILY_STRATIX
function FEATURE_FAMILY_BASE_STRATIX;
input[8*20:1] device;
reg var_family_base_stratix;
begin
if (IS_FAMILY_STRATIX(device) || IS_FAMILY_STRATIXGX(device) )
var_family_base_stratix = 1;
else
var_family_base_stratix = 0;
FEATURE_FAMILY_BASE_STRATIX = var_family_base_stratix;
end
endfunction //FEATURE_FAMILY_BASE_STRATIX
function FEATURE_FAMILY_BASE_CYCLONE;
input[8*20:1] device;
reg var_family_base_cyclone;
begin
if (IS_FAMILY_CYCLONE(device) )
var_family_base_cyclone = 1;
else
var_family_base_cyclone = 0;
FEATURE_FAMILY_BASE_CYCLONE = var_family_base_cyclone;
end
endfunction //FEATURE_FAMILY_BASE_CYCLONE
function FEATURE_FAMILY_MAX;
input[8*20:1] device;
reg var_family_max;
begin
if ((device == "MAX5000") || IS_FAMILY_MAX3000A(device) || (device == "MAX7000") || IS_FAMILY_MAX7000A(device) || IS_FAMILY_MAX7000AE(device) || (device == "MAX7000E") || IS_FAMILY_MAX7000S(device) || IS_FAMILY_MAX7000B(device) || (device == "MAX9000") )
var_family_max = 1;
else
var_family_max = 0;
FEATURE_FAMILY_MAX = var_family_max;
end
endfunction //FEATURE_FAMILY_MAX
function IS_VALID_FAMILY;
input[8*20:1] device;
reg is_valid;
begin
if (((device == "Arria 10") || (device == "ARRIA 10") || (device == "arria 10") || (device == "Arria10") || (device == "ARRIA10") || (device == "arria10") || (device == "Arria VI") || (device == "ARRIA VI") || (device == "arria vi") || (device == "ArriaVI") || (device == "ARRIAVI") || (device == "arriavi") || (device == "Night Fury") || (device == "NIGHT FURY") || (device == "night fury") || (device == "nightfury") || (device == "NIGHTFURY") || (device == "Arria 10 (GX/SX/GT)") || (device == "ARRIA 10 (GX/SX/GT)") || (device == "arria 10 (gx/sx/gt)") || (device == "Arria10(GX/SX/GT)") || (device == "ARRIA10(GX/SX/GT)") || (device == "arria10(gx/sx/gt)") || (device == "Arria 10 (GX)") || (device == "ARRIA 10 (GX)") || (device == "arria 10 (gx)") || (device == "Arria10(GX)") || (device == "ARRIA10(GX)") || (device == "arria10(gx)") || (device == "Arria 10 (SX)") || (device == "ARRIA 10 (SX)") || (device == "arria 10 (sx)") || (device == "Arria10(SX)") || (device == "ARRIA10(SX)") || (device == "arria10(sx)") || (device == "Arria 10 (GT)") || (device == "ARRIA 10 (GT)") || (device == "arria 10 (gt)") || (device == "Arria10(GT)") || (device == "ARRIA10(GT)") || (device == "arria10(gt)"))
|| ((device == "Arria GX") || (device == "ARRIA GX") || (device == "arria gx") || (device == "ArriaGX") || (device == "ARRIAGX") || (device == "arriagx") || (device == "Stratix II GX Lite") || (device == "STRATIX II GX LITE") || (device == "stratix ii gx lite") || (device == "StratixIIGXLite") || (device == "STRATIXIIGXLITE") || (device == "stratixiigxlite"))
|| ((device == "Arria II GX") || (device == "ARRIA II GX") || (device == "arria ii gx") || (device == "ArriaIIGX") || (device == "ARRIAIIGX") || (device == "arriaiigx") || (device == "Arria IIGX") || (device == "ARRIA IIGX") || (device == "arria iigx") || (device == "ArriaII GX") || (device == "ARRIAII GX") || (device == "arriaii gx") || (device == "Arria II") || (device == "ARRIA II") || (device == "arria ii") || (device == "ArriaII") || (device == "ARRIAII") || (device == "arriaii") || (device == "Arria II (GX/E)") || (device == "ARRIA II (GX/E)") || (device == "arria ii (gx/e)") || (device == "ArriaII(GX/E)") || (device == "ARRIAII(GX/E)") || (device == "arriaii(gx/e)") || (device == "PIRANHA") || (device == "piranha"))
|| ((device == "Arria II GZ") || (device == "ARRIA II GZ") || (device == "arria ii gz") || (device == "ArriaII GZ") || (device == "ARRIAII GZ") || (device == "arriaii gz") || (device == "Arria IIGZ") || (device == "ARRIA IIGZ") || (device == "arria iigz") || (device == "ArriaIIGZ") || (device == "ARRIAIIGZ") || (device == "arriaiigz"))
|| ((device == "Arria V GZ") || (device == "ARRIA V GZ") || (device == "arria v gz") || (device == "ArriaVGZ") || (device == "ARRIAVGZ") || (device == "arriavgz"))
|| ((device == "Arria V") || (device == "ARRIA V") || (device == "arria v") || (device == "Arria V (GT/GX)") || (device == "ARRIA V (GT/GX)") || (device == "arria v (gt/gx)") || (device == "ArriaV(GT/GX)") || (device == "ARRIAV(GT/GX)") || (device == "arriav(gt/gx)") || (device == "ArriaV") || (device == "ARRIAV") || (device == "arriav") || (device == "Arria V (GT/GX/ST/SX)") || (device == "ARRIA V (GT/GX/ST/SX)") || (device == "arria v (gt/gx/st/sx)") || (device == "ArriaV(GT/GX/ST/SX)") || (device == "ARRIAV(GT/GX/ST/SX)") || (device == "arriav(gt/gx/st/sx)") || (device == "Arria V (GT)") || (device == "ARRIA V (GT)") || (device == "arria v (gt)") || (device == "ArriaV(GT)") || (device == "ARRIAV(GT)") || (device == "arriav(gt)") || (device == "Arria V (GX)") || (device == "ARRIA V (GX)") || (device == "arria v (gx)") || (device == "ArriaV(GX)") || (device == "ARRIAV(GX)") || (device == "arriav(gx)") || (device == "Arria V (ST)") || (device == "ARRIA V (ST)") || (device == "arria v (st)") || (device == "ArriaV(ST)") || (device == "ARRIAV(ST)") || (device == "arriav(st)") || (device == "Arria V (SX)") || (device == "ARRIA V (SX)") || (device == "arria v (sx)") || (device == "ArriaV(SX)") || (device == "ARRIAV(SX)") || (device == "arriav(sx)"))
|| ((device == "BS") || (device == "bs"))
|| ((device == "Cyclone II") || (device == "CYCLONE II") || (device == "cyclone ii") || (device == "Cycloneii") || (device == "CYCLONEII") || (device == "cycloneii") || (device == "Magellan") || (device == "MAGELLAN") || (device == "magellan") || (device == "CycloneII") || (device == "CYCLONEII") || (device == "cycloneii"))
|| ((device == "Cyclone III LS") || (device == "CYCLONE III LS") || (device == "cyclone iii ls") || (device == "CycloneIIILS") || (device == "CYCLONEIIILS") || (device == "cycloneiiils") || (device == "Cyclone III LPS") || (device == "CYCLONE III LPS") || (device == "cyclone iii lps") || (device == "Cyclone LPS") || (device == "CYCLONE LPS") || (device == "cyclone lps") || (device == "CycloneLPS") || (device == "CYCLONELPS") || (device == "cyclonelps") || (device == "Tarpon") || (device == "TARPON") || (device == "tarpon") || (device == "Cyclone IIIE") || (device == "CYCLONE IIIE") || (device == "cyclone iiie"))
|| ((device == "Cyclone III") || (device == "CYCLONE III") || (device == "cyclone iii") || (device == "CycloneIII") || (device == "CYCLONEIII") || (device == "cycloneiii") || (device == "Barracuda") || (device == "BARRACUDA") || (device == "barracuda") || (device == "Cuda") || (device == "CUDA") || (device == "cuda") || (device == "CIII") || (device == "ciii"))
|| ((device == "Cyclone IV E") || (device == "CYCLONE IV E") || (device == "cyclone iv e") || (device == "CycloneIV E") || (device == "CYCLONEIV E") || (device == "cycloneiv e") || (device == "Cyclone IVE") || (device == "CYCLONE IVE") || (device == "cyclone ive") || (device == "CycloneIVE") || (device == "CYCLONEIVE") || (device == "cycloneive"))
|| ((device == "Cyclone IV GX") || (device == "CYCLONE IV GX") || (device == "cyclone iv gx") || (device == "Cyclone IVGX") || (device == "CYCLONE IVGX") || (device == "cyclone ivgx") || (device == "CycloneIV GX") || (device == "CYCLONEIV GX") || (device == "cycloneiv gx") || (device == "CycloneIVGX") || (device == "CYCLONEIVGX") || (device == "cycloneivgx") || (device == "Cyclone IV") || (device == "CYCLONE IV") || (device == "cyclone iv") || (device == "CycloneIV") || (device == "CYCLONEIV") || (device == "cycloneiv") || (device == "Cyclone IV (GX)") || (device == "CYCLONE IV (GX)") || (device == "cyclone iv (gx)") || (device == "CycloneIV(GX)") || (device == "CYCLONEIV(GX)") || (device == "cycloneiv(gx)") || (device == "Cyclone III GX") || (device == "CYCLONE III GX") || (device == "cyclone iii gx") || (device == "CycloneIII GX") || (device == "CYCLONEIII GX") || (device == "cycloneiii gx") || (device == "Cyclone IIIGX") || (device == "CYCLONE IIIGX") || (device == "cyclone iiigx") || (device == "CycloneIIIGX") || (device == "CYCLONEIIIGX") || (device == "cycloneiiigx") || (device == "Cyclone III GL") || (device == "CYCLONE III GL") || (device == "cyclone iii gl") || (device == "CycloneIII GL") || (device == "CYCLONEIII GL") || (device == "cycloneiii gl") || (device == "Cyclone IIIGL") || (device == "CYCLONE IIIGL") || (device == "cyclone iiigl") || (device == "CycloneIIIGL") || (device == "CYCLONEIIIGL") || (device == "cycloneiiigl") || (device == "Stingray") || (device == "STINGRAY") || (device == "stingray"))
|| ((device == "Cyclone V") || (device == "CYCLONE V") || (device == "cyclone v") || (device == "CycloneV") || (device == "CYCLONEV") || (device == "cyclonev") || (device == "Cyclone V (GT/GX/E/SX)") || (device == "CYCLONE V (GT/GX/E/SX)") || (device == "cyclone v (gt/gx/e/sx)") || (device == "CycloneV(GT/GX/E/SX)") || (device == "CYCLONEV(GT/GX/E/SX)") || (device == "cyclonev(gt/gx/e/sx)") || (device == "Cyclone V (E/GX/GT/SX/SE/ST)") || (device == "CYCLONE V (E/GX/GT/SX/SE/ST)") || (device == "cyclone v (e/gx/gt/sx/se/st)") || (device == "CycloneV(E/GX/GT/SX/SE/ST)") || (device == "CYCLONEV(E/GX/GT/SX/SE/ST)") || (device == "cyclonev(e/gx/gt/sx/se/st)") || (device == "Cyclone V (E)") || (device == "CYCLONE V (E)") || (device == "cyclone v (e)") || (device == "CycloneV(E)") || (device == "CYCLONEV(E)") || (device == "cyclonev(e)") || (device == "Cyclone V (GX)") || (device == "CYCLONE V (GX)") || (device == "cyclone v (gx)") || (device == "CycloneV(GX)") || (device == "CYCLONEV(GX)") || (device == "cyclonev(gx)") || (device == "Cyclone V (GT)") || (device == "CYCLONE V (GT)") || (device == "cyclone v (gt)") || (device == "CycloneV(GT)") || (device == "CYCLONEV(GT)") || (device == "cyclonev(gt)") || (device == "Cyclone V (SX)") || (device == "CYCLONE V (SX)") || (device == "cyclone v (sx)") || (device == "CycloneV(SX)") || (device == "CYCLONEV(SX)") || (device == "cyclonev(sx)") || (device == "Cyclone V (SE)") || (device == "CYCLONE V (SE)") || (device == "cyclone v (se)") || (device == "CycloneV(SE)") || (device == "CYCLONEV(SE)") || (device == "cyclonev(se)") || (device == "Cyclone V (ST)") || (device == "CYCLONE V (ST)") || (device == "cyclone v (st)") || (device == "CycloneV(ST)") || (device == "CYCLONEV(ST)") || (device == "cyclonev(st)"))
|| ((device == "Cyclone") || (device == "CYCLONE") || (device == "cyclone") || (device == "ACEX2K") || (device == "acex2k") || (device == "ACEX 2K") || (device == "acex 2k") || (device == "Tornado") || (device == "TORNADO") || (device == "tornado"))
|| ((device == "HardCopy II") || (device == "HARDCOPY II") || (device == "hardcopy ii") || (device == "HardCopyII") || (device == "HARDCOPYII") || (device == "hardcopyii") || (device == "Fusion") || (device == "FUSION") || (device == "fusion"))
|| ((device == "HardCopy III") || (device == "HARDCOPY III") || (device == "hardcopy iii") || (device == "HardCopyIII") || (device == "HARDCOPYIII") || (device == "hardcopyiii") || (device == "HCX") || (device == "hcx"))
|| ((device == "HardCopy IV") || (device == "HARDCOPY IV") || (device == "hardcopy iv") || (device == "HardCopyIV") || (device == "HARDCOPYIV") || (device == "hardcopyiv") || (device == "HardCopy IV (GX)") || (device == "HARDCOPY IV (GX)") || (device == "hardcopy iv (gx)") || (device == "HardCopy IV (E)") || (device == "HARDCOPY IV (E)") || (device == "hardcopy iv (e)") || (device == "HardCopyIV(GX)") || (device == "HARDCOPYIV(GX)") || (device == "hardcopyiv(gx)") || (device == "HardCopyIV(E)") || (device == "HARDCOPYIV(E)") || (device == "hardcopyiv(e)") || (device == "HCXIV") || (device == "hcxiv") || (device == "HardCopy IV (GX/E)") || (device == "HARDCOPY IV (GX/E)") || (device == "hardcopy iv (gx/e)") || (device == "HardCopy IV (E/GX)") || (device == "HARDCOPY IV (E/GX)") || (device == "hardcopy iv (e/gx)") || (device == "HardCopyIV(GX/E)") || (device == "HARDCOPYIV(GX/E)") || (device == "hardcopyiv(gx/e)") || (device == "HardCopyIV(E/GX)") || (device == "HARDCOPYIV(E/GX)") || (device == "hardcopyiv(e/gx)"))
|| ((device == "MAX 10") || (device == "max 10") || (device == "MAX 10 FPGA") || (device == "max 10 fpga") || (device == "Zippleback") || (device == "ZIPPLEBACK") || (device == "zippleback") || (device == "MAX10") || (device == "max10") || (device == "MAX 10 (DA/DF/DC/SA/SC)") || (device == "max 10 (da/df/dc/sa/sc)") || (device == "MAX10(DA/DF/DC/SA/SC)") || (device == "max10(da/df/dc/sa/sc)") || (device == "MAX 10 (DA)") || (device == "max 10 (da)") || (device == "MAX10(DA)") || (device == "max10(da)") || (device == "MAX 10 (DF)") || (device == "max 10 (df)") || (device == "MAX10(DF)") || (device == "max10(df)") || (device == "MAX 10 (DC)") || (device == "max 10 (dc)") || (device == "MAX10(DC)") || (device == "max10(dc)") || (device == "MAX 10 (SA)") || (device == "max 10 (sa)") || (device == "MAX10(SA)") || (device == "max10(sa)") || (device == "MAX 10 (SC)") || (device == "max 10 (sc)") || (device == "MAX10(SC)") || (device == "max10(sc)"))
|| ((device == "MAX II") || (device == "max ii") || (device == "MAXII") || (device == "maxii") || (device == "Tsunami") || (device == "TSUNAMI") || (device == "tsunami"))
|| ((device == "MAX V") || (device == "max v") || (device == "MAXV") || (device == "maxv") || (device == "Jade") || (device == "JADE") || (device == "jade"))
|| ((device == "MAX3000A") || (device == "max3000a") || (device == "MAX 3000A") || (device == "max 3000a"))
|| ((device == "MAX7000A") || (device == "max7000a") || (device == "MAX 7000A") || (device == "max 7000a"))
|| ((device == "MAX7000AE") || (device == "max7000ae") || (device == "MAX 7000AE") || (device == "max 7000ae"))
|| ((device == "MAX7000B") || (device == "max7000b") || (device == "MAX 7000B") || (device == "max 7000b"))
|| ((device == "MAX7000S") || (device == "max7000s") || (device == "MAX 7000S") || (device == "max 7000s"))
|| ((device == "Stratix 10") || (device == "STRATIX 10") || (device == "stratix 10") || (device == "Stratix10") || (device == "STRATIX10") || (device == "stratix10") || (device == "nadder") || (device == "NADDER") || (device == "Stratix 10 (GX/SX)") || (device == "STRATIX 10 (GX/SX)") || (device == "stratix 10 (gx/sx)") || (device == "Stratix10(GX/SX)") || (device == "STRATIX10(GX/SX)") || (device == "stratix10(gx/sx)") || (device == "Stratix 10 (GX)") || (device == "STRATIX 10 (GX)") || (device == "stratix 10 (gx)") || (device == "Stratix10(GX)") || (device == "STRATIX10(GX)") || (device == "stratix10(gx)") || (device == "Stratix 10 (SX)") || (device == "STRATIX 10 (SX)") || (device == "stratix 10 (sx)") || (device == "Stratix10(SX)") || (device == "STRATIX10(SX)") || (device == "stratix10(sx)"))
|| ((device == "Stratix GX") || (device == "STRATIX GX") || (device == "stratix gx") || (device == "Stratix-GX") || (device == "STRATIX-GX") || (device == "stratix-gx") || (device == "StratixGX") || (device == "STRATIXGX") || (device == "stratixgx") || (device == "Aurora") || (device == "AURORA") || (device == "aurora"))
|| ((device == "Stratix II GX") || (device == "STRATIX II GX") || (device == "stratix ii gx") || (device == "StratixIIGX") || (device == "STRATIXIIGX") || (device == "stratixiigx"))
|| ((device == "Stratix II") || (device == "STRATIX II") || (device == "stratix ii") || (device == "StratixII") || (device == "STRATIXII") || (device == "stratixii") || (device == "Armstrong") || (device == "ARMSTRONG") || (device == "armstrong"))
|| ((device == "Stratix III") || (device == "STRATIX III") || (device == "stratix iii") || (device == "StratixIII") || (device == "STRATIXIII") || (device == "stratixiii") || (device == "Titan") || (device == "TITAN") || (device == "titan") || (device == "SIII") || (device == "siii"))
|| ((device == "Stratix IV") || (device == "STRATIX IV") || (device == "stratix iv") || (device == "TGX") || (device == "tgx") || (device == "StratixIV") || (device == "STRATIXIV") || (device == "stratixiv") || (device == "Stratix IV (GT)") || (device == "STRATIX IV (GT)") || (device == "stratix iv (gt)") || (device == "Stratix IV (GX)") || (device == "STRATIX IV (GX)") || (device == "stratix iv (gx)") || (device == "Stratix IV (E)") || (device == "STRATIX IV (E)") || (device == "stratix iv (e)") || (device == "StratixIV(GT)") || (device == "STRATIXIV(GT)") || (device == "stratixiv(gt)") || (device == "StratixIV(GX)") || (device == "STRATIXIV(GX)") || (device == "stratixiv(gx)") || (device == "StratixIV(E)") || (device == "STRATIXIV(E)") || (device == "stratixiv(e)") || (device == "StratixIIIGX") || (device == "STRATIXIIIGX") || (device == "stratixiiigx") || (device == "Stratix IV (GT/GX/E)") || (device == "STRATIX IV (GT/GX/E)") || (device == "stratix iv (gt/gx/e)") || (device == "Stratix IV (GT/E/GX)") || (device == "STRATIX IV (GT/E/GX)") || (device == "stratix iv (gt/e/gx)") || (device == "Stratix IV (E/GT/GX)") || (device == "STRATIX IV (E/GT/GX)") || (device == "stratix iv (e/gt/gx)") || (device == "Stratix IV (E/GX/GT)") || (device == "STRATIX IV (E/GX/GT)") || (device == "stratix iv (e/gx/gt)") || (device == "StratixIV(GT/GX/E)") || (device == "STRATIXIV(GT/GX/E)") || (device == "stratixiv(gt/gx/e)") || (device == "StratixIV(GT/E/GX)") || (device == "STRATIXIV(GT/E/GX)") || (device == "stratixiv(gt/e/gx)") || (device == "StratixIV(E/GX/GT)") || (device == "STRATIXIV(E/GX/GT)") || (device == "stratixiv(e/gx/gt)") || (device == "StratixIV(E/GT/GX)") || (device == "STRATIXIV(E/GT/GX)") || (device == "stratixiv(e/gt/gx)") || (device == "Stratix IV (GX/E)") || (device == "STRATIX IV (GX/E)") || (device == "stratix iv (gx/e)") || (device == "StratixIV(GX/E)") || (device == "STRATIXIV(GX/E)") || (device == "stratixiv(gx/e)"))
|| ((device == "Stratix V") || (device == "STRATIX V") || (device == "stratix v") || (device == "StratixV") || (device == "STRATIXV") || (device == "stratixv") || (device == "Stratix V (GS)") || (device == "STRATIX V (GS)") || (device == "stratix v (gs)") || (device == "StratixV(GS)") || (device == "STRATIXV(GS)") || (device == "stratixv(gs)") || (device == "Stratix V (GT)") || (device == "STRATIX V (GT)") || (device == "stratix v (gt)") || (device == "StratixV(GT)") || (device == "STRATIXV(GT)") || (device == "stratixv(gt)") || (device == "Stratix V (GX)") || (device == "STRATIX V (GX)") || (device == "stratix v (gx)") || (device == "StratixV(GX)") || (device == "STRATIXV(GX)") || (device == "stratixv(gx)") || (device == "Stratix V (GS/GX)") || (device == "STRATIX V (GS/GX)") || (device == "stratix v (gs/gx)") || (device == "StratixV(GS/GX)") || (device == "STRATIXV(GS/GX)") || (device == "stratixv(gs/gx)") || (device == "Stratix V (GS/GT)") || (device == "STRATIX V (GS/GT)") || (device == "stratix v (gs/gt)") || (device == "StratixV(GS/GT)") || (device == "STRATIXV(GS/GT)") || (device == "stratixv(gs/gt)") || (device == "Stratix V (GT/GX)") || (device == "STRATIX V (GT/GX)") || (device == "stratix v (gt/gx)") || (device == "StratixV(GT/GX)") || (device == "STRATIXV(GT/GX)") || (device == "stratixv(gt/gx)") || (device == "Stratix V (GX/GS)") || (device == "STRATIX V (GX/GS)") || (device == "stratix v (gx/gs)") || (device == "StratixV(GX/GS)") || (device == "STRATIXV(GX/GS)") || (device == "stratixv(gx/gs)") || (device == "Stratix V (GT/GS)") || (device == "STRATIX V (GT/GS)") || (device == "stratix v (gt/gs)") || (device == "StratixV(GT/GS)") || (device == "STRATIXV(GT/GS)") || (device == "stratixv(gt/gs)") || (device == "Stratix V (GX/GT)") || (device == "STRATIX V (GX/GT)") || (device == "stratix v (gx/gt)") || (device == "StratixV(GX/GT)") || (device == "STRATIXV(GX/GT)") || (device == "stratixv(gx/gt)") || (device == "Stratix V (GS/GT/GX)") || (device == "STRATIX V (GS/GT/GX)") || (device == "stratix v (gs/gt/gx)") || (device == "Stratix V (GS/GX/GT)") || (device == "STRATIX V (GS/GX/GT)") || (device == "stratix v (gs/gx/gt)") || (device == "Stratix V (GT/GS/GX)") || (device == "STRATIX V (GT/GS/GX)") || (device == "stratix v (gt/gs/gx)") || (device == "Stratix V (GT/GX/GS)") || (device == "STRATIX V (GT/GX/GS)") || (device == "stratix v (gt/gx/gs)") || (device == "Stratix V (GX/GS/GT)") || (device == "STRATIX V (GX/GS/GT)") || (device == "stratix v (gx/gs/gt)") || (device == "Stratix V (GX/GT/GS)") || (device == "STRATIX V (GX/GT/GS)") || (device == "stratix v (gx/gt/gs)") || (device == "StratixV(GS/GT/GX)") || (device == "STRATIXV(GS/GT/GX)") || (device == "stratixv(gs/gt/gx)") || (device == "StratixV(GS/GX/GT)") || (device == "STRATIXV(GS/GX/GT)") || (device == "stratixv(gs/gx/gt)") || (device == "StratixV(GT/GS/GX)") || (device == "STRATIXV(GT/GS/GX)") || (device == "stratixv(gt/gs/gx)") || (device == "StratixV(GT/GX/GS)") || (device == "STRATIXV(GT/GX/GS)") || (device == "stratixv(gt/gx/gs)") || (device == "StratixV(GX/GS/GT)") || (device == "STRATIXV(GX/GS/GT)") || (device == "stratixv(gx/gs/gt)") || (device == "StratixV(GX/GT/GS)") || (device == "STRATIXV(GX/GT/GS)") || (device == "stratixv(gx/gt/gs)") || (device == "Stratix V (GS/GT/GX/E)") || (device == "STRATIX V (GS/GT/GX/E)") || (device == "stratix v (gs/gt/gx/e)") || (device == "StratixV(GS/GT/GX/E)") || (device == "STRATIXV(GS/GT/GX/E)") || (device == "stratixv(gs/gt/gx/e)") || (device == "Stratix V (E)") || (device == "STRATIX V (E)") || (device == "stratix v (e)") || (device == "StratixV(E)") || (device == "STRATIXV(E)") || (device == "stratixv(e)"))
|| ((device == "Stratix") || (device == "STRATIX") || (device == "stratix") || (device == "Yeager") || (device == "YEAGER") || (device == "yeager"))
|| ((device == "eFPGA 28 HPM") || (device == "EFPGA 28 HPM") || (device == "efpga 28 hpm") || (device == "eFPGA28HPM") || (device == "EFPGA28HPM") || (device == "efpga28hpm") || (device == "Bedrock") || (device == "BEDROCK") || (device == "bedrock")))
is_valid = 1;
else
is_valid = 0;
IS_VALID_FAMILY = is_valid;
end
endfunction // IS_VALID_FAMILY
endmodule // LPM_DEVICE_FAMILIES
//START_MODULE_NAME------------------------------------------------------------
//
// Module Name : lpm_constant
//
// Description : Parameterized constant generator megafunction. lpm_constant
// may be useful for convert a parameter into a constant.
//
// Limitation : n/a
//
// Results expected: Value specified by the argument to LPM_CVALUE.
//
//END_MODULE_NAME--------------------------------------------------------------
// BEGINNING OF MODULE
`timescale 1 ps / 1 ps
// MODULE DECLARATION
module lpm_constant (
result // Value specified by the argument to LPM_CVALUE. (Required)
);
// GLOBAL PARAMETER DECLARATION
parameter lpm_width = 1; // Width of the result[] port. (Required)
parameter lpm_cvalue = 0; // Constant value to be driven out on the
// result[] port. (Required)
parameter lpm_strength = "UNUSED";
parameter lpm_type = "lpm_constant";
parameter lpm_hint = "UNUSED";
// OUTPUT PORT DECLARATION
output [lpm_width-1:0] result;
// INTERNAL REGISTERS DECLARATION
reg[32:0] int_value;
// INITIAL CONSTRUCT BLOCK
initial
begin
if (lpm_width <= 0)
begin
$display("Value of lpm_width parameter must be greater than 0(ERROR)");
$display("Time: %0t Instance: %m", $time);
$finish;
end
int_value = lpm_cvalue;
end
// CONTINOUS ASSIGNMENT
assign result = int_value[lpm_width-1:0];
endmodule // lpm_constant
//START_MODULE_NAME------------------------------------------------------------
//
// Module Name : lpm_inv
//
// Description : Parameterized inverter megafunction.
//
// Limitation : n/a
//
// Results expected: Inverted value of input data
//
//END_MODULE_NAME--------------------------------------------------------------
// BEGINNING OF MODULE
`timescale 1 ps / 1 ps
// MODULE DECLARATION
module lpm_inv (
data, // Data input to the lpm_inv. (Required)
result // inverted result. (Required)
);
// GLOBAL PARAMETER DECLARATION
parameter lpm_width = 1; // Width of the data[] and result[] ports. (Required)
parameter lpm_type = "lpm_inv";
parameter lpm_hint = "UNUSED";
// INPUT PORT DECLARATION
input [lpm_width-1:0] data;
// OUTPUT PORT DECLARATION
output [lpm_width-1:0] result;
// INTERNAL REGISTERS DECLARATION
reg [lpm_width-1:0] result;
// INITIAL CONSTRUCT BLOCK
initial
begin
if (lpm_width <= 0)
begin
$display("Value of lpm_width parameter must be greater than 0 (ERROR)");
$display("Time: %0t Instance: %m", $time);
$finish;
end
end
// ALWAYS CONSTRUCT BLOCK
always @(data)
result = ~data;
endmodule // lpm_inv
//START_MODULE_NAME------------------------------------------------------------
//
// Module Name : lpm_and
//
// Description : Parameterized AND gate. This megafunction takes in data inputs
// for a number of AND gates.
//
// Limitation : n/a
//
// Results expected: Each result[] bit is the result of each AND gate.
//
//END_MODULE_NAME--------------------------------------------------------------
// BEGINNING OF MODULE
`timescale 1 ps / 1 ps
// MODULE DECLARATION
module lpm_and (
data, // Data input to the AND gate. (Required)
result // Result of the AND operators. (Required)
);
// GLOBAL PARAMETER DECLARATION
// Width of the data[][] and result[] ports. Number of AND gates. (Required)
parameter lpm_width = 1;
// Number of inputs to each AND gate. Number of input buses. (Required)
parameter lpm_size = 1;
parameter lpm_type = "lpm_and";
parameter lpm_hint = "UNUSED";
// INPUT PORT DECLARATION
input [(lpm_size * lpm_width)-1:0] data;
// OUTPUT PORT DECLARATION
output [lpm_width-1:0] result;
// INTERNAL REGISTER/SIGNAL DECLARATION
reg [lpm_width-1:0] result_tmp;
// LOCAL INTEGER DECLARATION
integer i;
integer j;
integer k;
// INITIAL CONSTRUCT BLOCK
initial
begin
if (lpm_width <= 0)
begin
$display("Value of lpm_width parameter must be greater than 0(ERROR)");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if (lpm_size <= 0)
begin
$display("Value of lpm_size parameter must be greater than 0(ERROR)");
$display("Time: %0t Instance: %m", $time);
$finish;
end
end
// ALWAYS CONSTRUCT BLOCK
always @(data)
begin
for (i=0; i<lpm_width; i=i+1)
begin
result_tmp[i] = 1'b1;
for (j=0; j<lpm_size; j=j+1)
begin
k = (j * lpm_width) + i;
result_tmp[i] = result_tmp[i] & data[k];
end
end
end
// CONTINOUS ASSIGNMENT
assign result = result_tmp;
endmodule // lpm_and
//START_MODULE_NAME------------------------------------------------------------
//
// Module Name : lpm_or
//
// Description : Parameterized OR gate megafunction. This megafunction takes in
// data inputs for a number of OR gates.
//
// Limitation : n/a
//
// Results expected: Each result[] bit is the result of each OR gate.
//
//END_MODULE_NAME--------------------------------------------------------------
// BEGINNING OF MODULE
`timescale 1 ps / 1 ps
// MODULE DECLARATION
module lpm_or (
data, // Data input to the OR gates. (Required)
result // Result of OR operators. (Required)
);
// GLOBAL PARAMETER DECLARATION
// Width of the data[] and result[] ports. Number of OR gates. (Required)
parameter lpm_width = 1;
// Number of inputs to each OR gate. Number of input buses. (Required)
parameter lpm_size = 1;
parameter lpm_type = "lpm_or";
parameter lpm_hint = "UNUSED";
// INPUT PORT DECLARATION
input [(lpm_size * lpm_width)-1:0] data;
// OUTPUT PORT DECLARATION
output [lpm_width-1:0] result;
// INTERNAL REGISTER/SIGNAL DECLARATION
reg [lpm_width-1:0] result_tmp;
// LOCAL INTEGER DECLARATION
integer i;
integer j;
integer k;
// INITIAL CONSTRUCT BLOCK
initial
begin
if (lpm_width <= 0)
begin
$display("Value of lpm_width parameter must be greater than 0 (ERROR)");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if (lpm_size <= 0)
begin
$display("Value of lpm_size parameter must be greater than 0 (ERROR)");
$display("Time: %0t Instance: %m", $time);
$finish;
end
end
// ALWAYS CONSTRUCT BLOCK
always @(data)
begin
for (i=0; i<lpm_width; i=i+1)
begin
result_tmp[i] = 1'b0;
for (j=0; j<lpm_size; j=j+1)
begin
k = (j * lpm_width) + i;
result_tmp[i] = result_tmp[i] | data[k];
end
end
end
// CONTINOUS ASSIGNMENT
assign result = result_tmp;
endmodule // lpm_or
//START_MODULE_NAME------------------------------------------------------------
//
// Module Name : lpm_xor
//
// Description : Parameterized XOR gate megafunction. This megafunction takes in
// data inputs for a number of XOR gates.
//
// Limitation : n/a.
//
// Results expected: Each result[] bit is the result of each XOR gates.
//
//END_MODULE_NAME--------------------------------------------------------------
// BEGINNING OF MODULE
`timescale 1 ps / 1 ps
// MODULE DECLARATION
module lpm_xor (
data, // Data input to the XOR gates. (Required)
result // Result of XOR operators. (Required)
);
// GLOBAL PARAMETER DECLARATION
// Width of the data[] and result[] ports. Number of XOR gates. (Required)
parameter lpm_width = 1;
// Number of inputs to each XOR gate. Number of input buses. (Required)
parameter lpm_size = 1;
parameter lpm_type = "lpm_xor";
parameter lpm_hint = "UNUSED";
// INPUT PORT DECLARATION
input [(lpm_size * lpm_width)-1:0] data;
// OUTPUT PORT DECLARATION
output [lpm_width-1:0] result;
// INTERNAL REGISTER/SIGNAL DECLARATION
reg [lpm_width-1:0] result_tmp;
// LOCAL INTEGER DECLARATION
integer i;
integer j;
integer k;
// INITIAL CONSTRUCT BLOCK
initial
begin
if (lpm_width <= 0)
begin
$display("Value of lpm_width parameter must be greater than 0 (ERROR)");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if (lpm_size <= 0)
begin
$display("Value of lpm_size parameter must be greater than 0 (ERROR)");
$display("Time: %0t Instance: %m", $time);
$finish;
end
end
// ALWAYS CONSTRUCT BLOCK
always @(data)
begin
for (i=0; i<lpm_width; i=i+1)
begin
result_tmp[i] = 1'b0;
for (j=0; j<lpm_size; j=j+1)
begin
k = (j * lpm_width) + i;
result_tmp[i] = result_tmp[i] ^ data[k];
end
end
end
// CONTINOUS ASSIGNMENT
assign result = result_tmp;
endmodule // lpm_xor
//START_MODULE_NAME------------------------------------------------------------
//
// Module Name : lpm_bustri
//
// Description : Parameterized tri-state buffer. lpm_bustri is useful for
// controlling both unidirectional and bidirectional I/O bus
// controllers.
//
// Limitation : n/a
//
// Results expected: Belows are the three configurations which are valid:
//
// 1) Only the input ports data[LPM_WIDTH-1..0] and enabledt are
// present, and only the output ports tridata[LPM_WIDTH-1..0]
// are present.
//
// ----------------------------------------------------
// | Input | Output |
// |====================================================|
// | enabledt | tridata[LPM_WIDTH-1..0] |
// |----------------------------------------------------|
// | 0 | Z |
// |----------------------------------------------------|
// | 1 | DATA[LPM_WIDTH-1..0] |
// ----------------------------------------------------
//
// 2) Only the input ports tridata[LPM_WIDTH-1..0] and enabletr
// are present, and only the output ports result[LPM_WIDTH-1..0]
// are present.
//
// ----------------------------------------------------
// | Input | Output |
// |====================================================|
// | enabletr | result[LPM_WIDTH-1..0] |
// |----------------------------------------------------|
// | 0 | Z |
// |----------------------------------------------------|
// | 1 | tridata[LPM_WIDTH-1..0] |
// ----------------------------------------------------
//
// 3) All ports are present: input ports data[LPM_WIDTH-1..0],
// enabledt, and enabletr; output ports result[LPM_WIDTH-1..0];
// and bidirectional ports tridata[LPM_WIDTH-1..0].
//
// ----------------------------------------------------------------------------
// | Input | Bidirectional | Output |
// |----------------------------------------------------------------------------|
// | enabledt | enabletr | tridata[LPM_WIDTH-1..0] | result[LPM_WIDTH-1..0] |
// |============================================================================|
// | 0 | 0 | Z (input) | Z |
// |----------------------------------------------------------------------------|
// | 0 | 1 | Z (input) | tridata[LPM_WIDTH-1..0] |
// |----------------------------------------------------------------------------|
// | 1 | 0 | data[LPM_WIDTH-1..0] | Z |
// |----------------------------------------------------------------------------|
// | 1 | 1 | data[LPM_WIDTH-1..0] | data[LPM_WIDTH-1..0] |
// ----------------------------------------------------------------------------
//
//
//END_MODULE_NAME--------------------------------------------------------------
// BEGINNING OF MODULE
`timescale 1 ps / 1 ps
// MODULE DECLARATION
module lpm_bustri (
tridata, // Bidirectional bus signal. (Required)
data, // Data input to the tridata[] bus. (Required)
enabletr, // If high, enables tridata[] onto the result bus.
enabledt, // If high, enables data onto the tridata[] bus.
result // Output from the tridata[] bus.
);
// GLOBAL PARAMETER DECLARATION
parameter lpm_width = 1;
parameter lpm_type = "lpm_bustri";
parameter lpm_hint = "UNUSED";
// INPUT PORT DECLARATION
input [lpm_width-1:0] data;
input enabletr;
input enabledt;
// OUTPUT PORT DECLARATION
output [lpm_width-1:0] result;
// INPUT/OUTPUT PORT DECLARATION
inout [lpm_width-1:0] tridata;
// INTERNAL REGISTERS DECLARATION
reg [lpm_width-1:0] result;
// INTERNAL TRI DECLARATION
tri1 enabletr;
tri1 enabledt;
wire i_enabledt;
wire i_enabletr;
buf (i_enabledt, enabledt);
buf (i_enabletr, enabletr);
// INITIAL CONSTRUCT BLOCK
initial
begin
if (lpm_width <= 0)
begin
$display("Value of lpm_width parameter must be greater than 0(ERROR)");
$display("Time: %0t Instance: %m", $time);
$finish;
end
end
// ALWAYS CONSTRUCT BLOCK
always @(data or tridata or i_enabletr or i_enabledt)
begin
if ((i_enabledt == 1'b0) && (i_enabletr == 1'b1))
begin
result = tridata;
end
else if ((i_enabledt == 1'b1) && (i_enabletr == 1'b1))
begin
result = data;
end
else
begin
result = {lpm_width{1'bz}};
end
end
// CONTINOUS ASSIGNMENT
assign tridata = (i_enabledt == 1) ? data : {lpm_width{1'bz}};
endmodule // lpm_bustri
//START_MODULE_NAME------------------------------------------------------------
//
// Module Name : lpm_mux
//
// Description : Parameterized multiplexer megafunctions.
//
// Limitation : n/a
//
// Results expected: Selected input port.
//
//END_MODULE_NAME--------------------------------------------------------------
// BEGINNING OF MODULE
`timescale 1 ps / 1 ps
// MODULE DECLARATION
module lpm_mux (
data, // Data input. (Required)
sel, // Selects one of the input buses. (Required)
clock, // Clock for pipelined usage
aclr, // Asynchronous clear for pipelined usage.
clken, // Clock enable for pipelined usage.
result // Selected input port. (Required)
);
// GLOBAL PARAMETER DECLARATION
parameter lpm_width = 1; // Width of the data[][] and result[] ports. (Required)
parameter lpm_size = 2; // Number of input buses to the multiplexer. (Required)
parameter lpm_widths = 1; // Width of the sel[] input port. (Required)
parameter lpm_pipeline = 0; // Specifies the number of Clock cycles of latency
// associated with the result[] output.
parameter lpm_type = "lpm_mux";
parameter lpm_hint = "UNUSED";
// INPUT PORT DECLARATION
input [(lpm_size * lpm_width)-1:0] data;
input [lpm_widths-1:0] sel;
input clock;
input aclr;
input clken;
// OUTPUT PORT DECLARATION
output [lpm_width-1:0] result;
// INTERNAL REGISTER/SIGNAL DECLARATION
reg [lpm_width-1:0] result_pipe [lpm_pipeline+1:0];
reg [lpm_width-1:0] tmp_result;
// LOCAL INTEGER DECLARATION
integer i;
integer pipe_ptr;
// INTERNAL TRI DECLARATION
tri0 aclr;
tri0 clock;
tri1 clken;
wire i_aclr;
wire i_clock;
wire i_clken;
buf (i_aclr, aclr);
buf (i_clock, clock);
buf (i_clken, clken);
// INITIAL CONSTRUCT BLOCK
initial
begin
if (lpm_width <= 0)
begin
$display("Value of lpm_width parameter must be greater than 0 (ERROR)");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if (lpm_size <= 1)
begin
$display("Value of lpm_size parameter must be greater than 1 (ERROR)");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if (lpm_widths <= 0)
begin
$display("Value of lpm_widths parameter must be greater than 0 (ERROR)");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if (lpm_pipeline < 0)
begin
$display("Value of lpm_pipeline parameter must NOT less than 0 (ERROR)");
$display("Time: %0t Instance: %m", $time);
$finish;
end
pipe_ptr = 0;
end
// ALWAYS CONSTRUCT BLOCK
always @(data or sel)
begin
tmp_result = 0;
if (sel < lpm_size)
begin
for (i = 0; i < lpm_width; i = i + 1)
tmp_result[i] = data[(sel * lpm_width) + i];
end
else
tmp_result = {lpm_width{1'bx}};
end
always @(posedge i_clock or posedge i_aclr)
begin
if (i_aclr)
begin
for (i = 0; i <= (lpm_pipeline+1); i = i + 1)
result_pipe[i] <= 1'b0;
pipe_ptr <= 0;
end
else if (i_clken == 1'b1)
begin
result_pipe[pipe_ptr] <= tmp_result;
if (lpm_pipeline > 1)
pipe_ptr <= (pipe_ptr + 1) % lpm_pipeline;
end
end
// CONTINOUS ASSIGNMENT
assign result = (lpm_pipeline > 0) ? result_pipe[pipe_ptr] : tmp_result;
endmodule // lpm_mux
// END OF MODULE
//START_MODULE_NAME------------------------------------------------------------
//
// Module Name : lpm_decode
//
// Description : Parameterized decoder megafunction.
//
// Limitation : n/a
//
// Results expected: Decoded output.
//
//END_MODULE_NAME--------------------------------------------------------------
// BEGINNING OF MODULE
`timescale 1 ps / 1 ps
// MODULE DECLARATION
module lpm_decode (
data, // Data input. Treated as an unsigned binary encoded number. (Required)
enable, // Enable. All outputs low when not active.
clock, // Clock for pipelined usage.
aclr, // Asynchronous clear for pipelined usage.
clken, // Clock enable for pipelined usage.
eq // Decoded output. (Required)
);
// GLOBAL PARAMETER DECLARATION
parameter lpm_width = 1; // Width of the data[] port, or the
// input value to be decoded. (Required)
parameter lpm_decodes = 1 << lpm_width; // Number of explicit decoder outputs. (Required)
parameter lpm_pipeline = 0; // Number of Clock cycles of latency
parameter lpm_type = "lpm_decode";
parameter lpm_hint = "UNUSED";
// INPUT PORT DECLARATION
input [lpm_width-1:0] data;
input enable;
input clock;
input aclr;
input clken;
// OUTPUT PORT DECLARATION
output [lpm_decodes-1:0] eq;
// INTERNAL REGISTER/SIGNAL DECLARATION
reg [lpm_decodes-1:0] eq_pipe [(lpm_pipeline+1):0];
reg [lpm_decodes-1:0] tmp_eq;
// LOCAL INTEGER DECLARATION
integer i;
integer pipe_ptr;
// INTERNAL TRI DECLARATION
tri1 enable;
tri0 clock;
tri0 aclr;
tri1 clken;
wire i_clock;
wire i_clken;
wire i_aclr;
wire i_enable;
buf (i_clock, clock);
buf (i_clken, clken);
buf (i_aclr, aclr);
buf (i_enable, enable);
// INITIAL CONSTRUCT BLOCK
initial
begin
if (lpm_width <= 0)
begin
$display("Value of lpm_width parameter must be greater than 0 (ERROR)");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if (lpm_decodes <= 0)
begin
$display("Value of lpm_decodes parameter must be greater than 0 (ERROR)");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if (lpm_decodes > (1 << lpm_width))
begin
$display("Value of lpm_decodes parameter must be less or equal to 2^lpm_width (ERROR)");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if (lpm_pipeline < 0)
begin
$display("Value of lpm_pipeline parameter must be greater or equal to 0 (ERROR)");
$display("Time: %0t Instance: %m", $time);
$finish;
end
pipe_ptr = 0;
end
// ALWAYS CONSTRUCT BLOCK
always @(data or i_enable)
begin
tmp_eq = {lpm_decodes{1'b0}};
if (i_enable)
tmp_eq[data] = 1'b1;
end
always @(posedge i_clock or posedge i_aclr)
begin
if (i_aclr)
begin
for (i = 0; i <= lpm_pipeline; i = i + 1)
eq_pipe[i] <= {lpm_decodes{1'b0}};
pipe_ptr <= 0;
end
else if (clken == 1'b1)
begin
eq_pipe[pipe_ptr] <= tmp_eq;
if (lpm_pipeline > 1)
pipe_ptr <= (pipe_ptr + 1) % lpm_pipeline;
end
end
assign eq = (lpm_pipeline > 0) ? eq_pipe[pipe_ptr] : tmp_eq;
endmodule // lpm_decode
// END OF MODULE
//START_MODULE_NAME------------------------------------------------------------
//
// Module Name : lpm_clshift
//
// Description : Parameterized combinatorial logic shifter or barrel shifter
// megafunction.
//
// Limitation : n/a
//
// Results expected: Return the shifted data and underflow/overflow status bit.
//
//END_MODULE_NAME--------------------------------------------------------------
// BEGINNING OF MODULE
`timescale 1 ps / 1 ps
// MODULE DECLARATION
module lpm_clshift (
data, // Data to be shifted. (Required)
distance, // Number of positions to shift data[] in the direction specified
// by the direction port. (Required)
direction, // Direction of shift. Low = left (toward the MSB),
// high = right (toward the LSB).
clock, // Clock for pipelined usage.
aclr, // Asynchronous clear for pipelined usage.
clken, // Clock enable for pipelined usage.
result, // Shifted data. (Required)
underflow, // Logical or arithmetic underflow.
overflow // Logical or arithmetic overflow.
);
// GLOBAL PARAMETER DECLARATION
parameter lpm_width = 1; // Width of the data[] and result[] ports. Must be
// greater than 0 (Required)
parameter lpm_widthdist = 1; // Width of the distance[] input port. (Required)
parameter lpm_shifttype = "LOGICAL"; // Type of shifting operation to be performed.
parameter lpm_pipeline = 0; // Number of Clock cycles of latency
parameter lpm_type = "lpm_clshift";
parameter lpm_hint = "UNUSED";
// INPUT PORT DECLARATION
input [lpm_width-1:0] data;
input [lpm_widthdist-1:0] distance;
input direction;
input clock;
input aclr;
input clken;
// OUTPUT PORT DECLARATION
output [lpm_width-1:0] result;
output underflow;
output overflow;
// INTERNAL REGISTERS DECLARATION
reg [lpm_width-1:0] ONES;
reg [lpm_width-1:0] ZEROS;
reg [lpm_width-1:0] tmp_result;
reg tmp_underflow;
reg tmp_overflow;
reg [lpm_width-1:0] result_pipe [(lpm_pipeline+1):0];
reg [(lpm_pipeline+1):0] overflow_pipe;
reg [(lpm_pipeline+1):0] underflow_pipe;
// LOCAL INTEGER DECLARATION
integer i;
integer i1;
integer pipe_ptr;
// INTERNAL TRI DECLARATION
tri0 direction;
tri0 clock;
tri0 aclr;
tri1 clken;
wire i_direction;
wire i_clock;
wire i_clken;
wire i_aclr;
buf (i_direction, direction);
buf (i_clock, clock);
buf (i_clken, clken);
buf (i_aclr, aclr);
// FUNCTON DECLARATION
// Perform logival shift operation
function [lpm_width+1:0] LogicShift;
input [lpm_width-1:0] data;
input [lpm_widthdist-1:0] shift_num;
input direction;
reg [lpm_width-1:0] tmp_buf;
reg underflow;
reg overflow;
begin
tmp_buf = data;
overflow = 1'b0;
underflow = 1'b0;
if ((direction) && (shift_num > 0)) // shift right
begin
tmp_buf = data >> shift_num;
if ((data != ZEROS) && ((shift_num >= lpm_width) || (tmp_buf == ZEROS)))
underflow = 1'b1;
end
else if (shift_num > 0) // shift left
begin
tmp_buf = data << shift_num;
if ((data != ZEROS) && ((shift_num >= lpm_width)
|| ((data >> (lpm_width-shift_num)) != ZEROS)))
overflow = 1'b1;
end
LogicShift = {overflow,underflow,tmp_buf[lpm_width-1:0]};
end
endfunction // LogicShift
// Perform Arithmetic shift operation
function [lpm_width+1:0] ArithShift;
input [lpm_width-1:0] data;
input [lpm_widthdist-1:0] shift_num;
input direction;
reg [lpm_width-1:0] tmp_buf;
reg underflow;
reg overflow;
integer i;
integer i1;
begin
tmp_buf = data;
overflow = 1'b0;
underflow = 1'b0;
if (shift_num < lpm_width)
begin
if ((direction) && (shift_num > 0)) // shift right
begin
if (data[lpm_width-1] == 1'b0) // positive number
begin
tmp_buf = data >> shift_num;
if ((data != ZEROS) && ((shift_num >= lpm_width) || (tmp_buf == ZEROS)))
underflow = 1'b1;
end
else // negative number
begin
tmp_buf = (data >> shift_num) | (ONES << (lpm_width - shift_num));
if ((data != ONES) && ((shift_num >= lpm_width-1) || (tmp_buf == ONES)))
underflow = 1'b1;
end
end
else if (shift_num > 0) // shift left
begin
tmp_buf = data << shift_num;
for (i=lpm_width-1; i >= lpm_width-shift_num; i=i-1)
begin
if(data[i-1] != data[lpm_width-1])
overflow = 1'b1;
end
end
end
else // shift_num >= lpm_width
begin
if (direction)
begin
for (i=0; i < lpm_width; i=i+1)
tmp_buf[i] = data[lpm_width-1];
underflow = 1'b1;
end
else
begin
tmp_buf = {lpm_width{1'b0}};
if (data != ZEROS)
begin
overflow = 1'b1;
end
end
end
ArithShift = {overflow,underflow,tmp_buf[lpm_width-1:0]};
end
endfunction // ArithShift
// Perform rotate shift operation
function [lpm_width+1:0] RotateShift;
input [lpm_width-1:0] data;
input [lpm_widthdist-1:0] shift_num;
input direction;
reg [lpm_width-1:0] tmp_buf;
begin
tmp_buf = data;
if ((direction) && (shift_num > 0)) // shift right
tmp_buf = (data >> shift_num) | (data << (lpm_width - shift_num));
else if (shift_num > 0) // shift left
tmp_buf = (data << shift_num) | (data >> (lpm_width - shift_num));
RotateShift = {2'bx, tmp_buf[lpm_width-1:0]};
end
endfunction // RotateShift
// INITIAL CONSTRUCT BLOCK
initial
begin
if ((lpm_shifttype != "LOGICAL") &&
(lpm_shifttype != "ARITHMETIC") &&
(lpm_shifttype != "ROTATE") &&
(lpm_shifttype != "UNUSED")) // non-LPM 220 standard
begin
$display("Error! LPM_SHIFTTYPE value must be \"LOGICAL\", \"ARITHMETIC\", or \"ROTATE\".");
$display("Time: %0t Instance: %m", $time);
end
if (lpm_width <= 0)
begin
$display("Value of lpm_width parameter must be greater than 0(ERROR)");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if (lpm_widthdist <= 0)
begin
$display("Value of lpm_widthdist parameter must be greater than 0(ERROR)");
$display("Time: %0t Instance: %m", $time);
$finish;
end
for (i=0; i < lpm_width; i=i+1)
begin
ONES[i] = 1'b1;
ZEROS[i] = 1'b0;
end
for (i = 0; i <= lpm_pipeline; i = i + 1)
begin
result_pipe[i] = ZEROS;
overflow_pipe[i] = 1'b0;
underflow_pipe[i] = 1'b0;
end
tmp_result = ZEROS;
tmp_underflow = 1'b0;
tmp_overflow = 1'b0;
pipe_ptr = 0;
end
// ALWAYS CONSTRUCT BLOCK
always @(data or i_direction or distance)
begin
if ((lpm_shifttype == "LOGICAL") || (lpm_shifttype == "UNUSED"))
{tmp_overflow, tmp_underflow, tmp_result} = LogicShift(data, distance, i_direction);
else if (lpm_shifttype == "ARITHMETIC")
{tmp_overflow, tmp_underflow, tmp_result} = ArithShift(data, distance, i_direction);
else if (lpm_shifttype == "ROTATE")
{tmp_overflow, tmp_underflow, tmp_result} = RotateShift(data, distance, i_direction);
end
always @(posedge i_clock or posedge i_aclr)
begin
if (i_aclr)
begin
for (i1 = 0; i1 <= lpm_pipeline; i1 = i1 + 1)
begin
result_pipe[i1] <= {lpm_width{1'b0}};
overflow_pipe[i1] <= 1'b0;
underflow_pipe[i1] <= 1'b0;
end
pipe_ptr <= 0;
end
else if (i_clken == 1'b1)
begin
result_pipe[pipe_ptr] <= tmp_result;
overflow_pipe[pipe_ptr] <= tmp_overflow;
underflow_pipe[pipe_ptr] <= tmp_underflow;
if (lpm_pipeline > 1)
pipe_ptr <= (pipe_ptr + 1) % lpm_pipeline;
end
end
assign result = (lpm_pipeline > 0) ? result_pipe[pipe_ptr] : tmp_result;
assign overflow = (lpm_pipeline > 0) ? overflow_pipe[pipe_ptr] : tmp_overflow;
assign underflow = (lpm_pipeline > 0) ? underflow_pipe[pipe_ptr] : tmp_underflow;
endmodule // lpm_clshift
//START_MODULE_NAME------------------------------------------------------------
//
// Module Name : lpm_add_sub
//
// Description : Parameterized adder/subtractor megafunction.
//
// Limitation : n/a
//
// Results expected: If performs as adder, the result will be dataa[]+datab[]+cin.
// If performs as subtractor, the result will be dataa[]-datab[]+cin-1.
// Also returns carry out bit and overflow status bit.
//
//END_MODULE_NAME--------------------------------------------------------------
// BEGINNING OF MODULE
`timescale 1 ps / 1 ps
// MODULE DECLARATION
module lpm_add_sub (
dataa, // Augend/Minuend
datab, // Addend/Subtrahend
cin, // Carry-in to the low-order bit.
add_sub, // If the signal is high, the operation = dataa[]+datab[]+cin.
// If the signal is low, the operation = dataa[]-datab[]+cin-1.
clock, // Clock for pipelined usage.
aclr, // Asynchronous clear for pipelined usage.
clken, // Clock enable for pipelined usage.
result, // dataa[]+datab[]+cin or dataa[]-datab[]+cin-1
cout, // Carry-out (borrow-in) of the MSB.
overflow // Result exceeds available precision.
);
// GLOBAL PARAMETER DECLARATION
parameter lpm_width = 1; // Width of the dataa[],datab[], and result[] ports.
parameter lpm_representation = "SIGNED"; // Type of addition performed
parameter lpm_direction = "UNUSED"; // Specify the operation of the lpm_add_sub function
parameter lpm_pipeline = 0; // Number of Clock cycles of latency
parameter lpm_type = "lpm_add_sub";
parameter lpm_hint = "UNUSED";
// INPUT PORT DECLARATION
input [lpm_width-1:0] dataa;
input [lpm_width-1:0] datab;
input cin;
input add_sub;
input clock;
input aclr;
input clken;
// OUTPUT PORT DECLARATION
output [lpm_width-1:0] result;
output cout;
output overflow;
// INTERNAL REGISTER/SIGNAL DECLARATION
reg [lpm_width-1:0] result_pipe [(lpm_pipeline+1):0];
reg [(lpm_pipeline+1):0] cout_pipe;
reg [(lpm_pipeline+1):0] overflow_pipe;
reg tmp_cout;
reg tmp_overflow;
reg [lpm_width-1:0] tmp_result;
reg i_cin;
// LOCAL INTEGER DECLARATION
integer borrow;
integer i;
integer pipe_ptr;
// INTERNAL TRI DECLARATION
tri1 i_add_sub;
tri0 i_aclr;
tri1 i_clken;
tri0 i_clock;
// INITIAL CONSTRUCT BLOCK
initial
begin
// check if lpm_width < 0
if (lpm_width <= 0)
begin
$display("Error! LPM_WIDTH must be greater than 0.\n");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if ((lpm_direction != "ADD") &&
(lpm_direction != "SUB") &&
(lpm_direction != "UNUSED") && // non-LPM 220 standard
(lpm_direction != "DEFAULT")) // non-LPM 220 standard
begin
$display("Error! LPM_DIRECTION value must be \"ADD\" or \"SUB\".");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if ((lpm_representation != "SIGNED") &&
(lpm_representation != "UNSIGNED"))
begin
$display("Error! LPM_REPRESENTATION value must be \"SIGNED\" or \"UNSIGNED\".");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if (lpm_pipeline < 0)
begin
$display("Error! LPM_PIPELINE must be greater than or equal to 0.\n");
$display("Time: %0t Instance: %m", $time);
$finish;
end
for (i = 0; i <= (lpm_pipeline+1); i = i + 1)
begin
result_pipe[i] = 'b0;
cout_pipe[i] = 1'b0;
overflow_pipe[i] = 1'b0;
end
pipe_ptr = 0;
end
// ALWAYS CONSTRUCT BLOCK
always @(cin or dataa or datab or i_add_sub)
begin
i_cin = 1'b0;
borrow = 1'b0;
// cout is the same for both signed and unsign representation.
if ((lpm_direction == "ADD") || ((i_add_sub == 1) &&
((lpm_direction == "UNUSED") || (lpm_direction == "DEFAULT")) ))
begin
i_cin = (cin === 1'bz) ? 0 : cin;
{tmp_cout, tmp_result} = dataa + datab + i_cin;
tmp_overflow = tmp_cout;
end
else if ((lpm_direction == "SUB") || ((i_add_sub == 0) &&
((lpm_direction == "UNUSED") || (lpm_direction == "DEFAULT")) ))
begin
i_cin = (cin === 1'bz) ? 1 : cin;
borrow = (~i_cin) ? 1 : 0;
{tmp_overflow, tmp_result} = dataa - datab - borrow;
tmp_cout = (dataa >= (datab+borrow))?1:0;
end
if (lpm_representation == "SIGNED")
begin
// perform the addtion or subtraction operation
if ((lpm_direction == "ADD") || ((i_add_sub == 1) &&
((lpm_direction == "UNUSED") || (lpm_direction == "DEFAULT")) ))
begin
tmp_result = dataa + datab + i_cin;
tmp_overflow = ((dataa[lpm_width-1] == datab[lpm_width-1]) &&
(dataa[lpm_width-1] != tmp_result[lpm_width-1])) ?
1 : 0;
end
else if ((lpm_direction == "SUB") || ((i_add_sub == 0) &&
((lpm_direction == "UNUSED") || (lpm_direction == "DEFAULT")) ))
begin
tmp_result = dataa - datab - borrow;
tmp_overflow = ((dataa[lpm_width-1] != datab[lpm_width-1]) &&
(dataa[lpm_width-1] != tmp_result[lpm_width-1])) ?
1 : 0;
end
end
end
always @(posedge i_clock or posedge i_aclr)
begin
if (i_aclr)
begin
for (i = 0; i <= (lpm_pipeline+1); i = i + 1)
begin
result_pipe[i] <= {lpm_width{1'b0}};
cout_pipe[i] <= 1'b0;
overflow_pipe[i] <= 1'b0;
end
pipe_ptr <= 0;
end
else if (i_clken == 1)
begin
result_pipe[pipe_ptr] <= tmp_result;
cout_pipe[pipe_ptr] <= tmp_cout;
overflow_pipe[pipe_ptr] <= tmp_overflow;
if (lpm_pipeline > 1)
pipe_ptr <= (pipe_ptr + 1) % lpm_pipeline;
end
end
// CONTINOUS ASSIGNMENT
assign result = (lpm_pipeline > 0) ? result_pipe[pipe_ptr] : tmp_result;
assign cout = (lpm_pipeline > 0) ? cout_pipe[pipe_ptr] : tmp_cout;
assign overflow = (lpm_pipeline > 0) ? overflow_pipe[pipe_ptr] : tmp_overflow;
assign i_clock = clock;
assign i_aclr = aclr;
assign i_clken = clken;
assign i_add_sub = add_sub;
endmodule // lpm_add_sub
// END OF MODULE
//START_MODULE_NAME------------------------------------------------------------
//
// Module Name : lpm_compare
//
// Description : Parameterized comparator megafunction. The comparator will
// compare between data[] and datab[] and return the status of
// comparation for the following operation.
// 1) dataa[] < datab[].
// 2) dataa[] == datab[].
// 3) dataa[] > datab[].
// 4) dataa[] >= datab[].
// 5) dataa[] != datab[].
// 6) dataa[] <= datab[].
//
// Limitation : n/a
//
// Results expected: Return status bits of the comparision between dataa[] and
// datab[].
//
//END_MODULE_NAME--------------------------------------------------------------
// BEGINNING OF MODULE
`timescale 1 ps / 1 ps
// MODULE DECLARATION
module lpm_compare (
dataa, // Value to be compared to datab[]. (Required)
datab, // Value to be compared to dataa[]. (Required)
clock, // Clock for pipelined usage.
aclr, // Asynchronous clear for pipelined usage.
clken, // Clock enable for pipelined usage.
// One of the following ports must be present.
alb, // High (1) if dataa[] < datab[].
aeb, // High (1) if dataa[] == datab[].
agb, // High (1) if dataa[] > datab[].
aleb, // High (1) if dataa[] <= datab[].
aneb, // High (1) if dataa[] != datab[].
ageb // High (1) if dataa[] >= datab[].
);
// GLOBAL PARAMETER DECLARATION
parameter lpm_width = 1; // Width of the dataa[] and datab[] ports. (Required)
parameter lpm_representation = "UNSIGNED"; // Type of comparison performed:
// "SIGNED", "UNSIGNED"
parameter lpm_pipeline = 0; // Specifies the number of Clock cycles of latency
// associated with the alb, aeb, agb, ageb, aleb,
// or aneb output.
parameter lpm_type = "lpm_compare";
parameter lpm_hint = "UNUSED";
// INPUT PORT DECLARATION
input [lpm_width-1:0] dataa;
input [lpm_width-1:0] datab;
input clock;
input aclr;
input clken;
// OUTPUT PORT DECLARATION
output alb;
output aeb;
output agb;
output aleb;
output aneb;
output ageb;
// INTERNAL REGISTERS DECLARATION
reg [lpm_pipeline+1:0] alb_pipe;
reg [lpm_pipeline+1:0] aeb_pipe;
reg [lpm_pipeline+1:0] agb_pipe;
reg [lpm_pipeline+1:0] aleb_pipe;
reg [lpm_pipeline+1:0] aneb_pipe;
reg [lpm_pipeline+1:0] ageb_pipe;
reg tmp_alb;
reg tmp_aeb;
reg tmp_agb;
reg tmp_aleb;
reg tmp_aneb;
reg tmp_ageb;
// LOCAL INTEGER DECLARATION
integer i;
integer pipe_ptr;
// INTERNAL TRI DECLARATION
tri0 aclr;
tri0 clock;
tri1 clken;
wire i_aclr;
wire i_clock;
wire i_clken;
buf (i_aclr, aclr);
buf (i_clock, clock);
buf (i_clken, clken);
// INITIAL CONSTRUCT BLOCK
initial
begin
if ((lpm_representation != "SIGNED") &&
(lpm_representation != "UNSIGNED"))
begin
$display("Error! LPM_REPRESENTATION value must be \"SIGNED\" or \"UNSIGNED\".");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if (lpm_width <= 0)
begin
$display("Value of lpm_width parameter must be greater than 0(ERROR)");
$display("Time: %0t Instance: %m", $time);
$finish;
end
pipe_ptr = 0;
end
// ALWAYS CONSTRUCT BLOCK
// get the status of comparison
always @(dataa or datab)
begin
tmp_aeb = (dataa == datab);
tmp_aneb = (dataa != datab);
if ((lpm_representation == "SIGNED") &&
((dataa[lpm_width-1] ^ datab[lpm_width-1]) == 1))
begin
// create latency
tmp_alb = (dataa > datab);
tmp_agb = (dataa < datab);
tmp_aleb = (dataa >= datab);
tmp_ageb = (dataa <= datab);
end
else
begin
// create latency
tmp_alb = (dataa < datab);
tmp_agb = (dataa > datab);
tmp_aleb = (dataa <= datab);
tmp_ageb = (dataa >= datab);
end
end
// pipelining process
always @(posedge i_clock or posedge i_aclr)
begin
if (i_aclr) // reset all variables
begin
for (i = 0; i <= (lpm_pipeline + 1); i = i + 1)
begin
aeb_pipe[i] <= 1'b0;
agb_pipe[i] <= 1'b0;
alb_pipe[i] <= 1'b0;
aleb_pipe[i] <= 1'b0;
aneb_pipe[i] <= 1'b0;
ageb_pipe[i] <= 1'b0;
end
pipe_ptr <= 0;
end
else if (i_clken == 1)
begin
alb_pipe[pipe_ptr] <= tmp_alb;
aeb_pipe[pipe_ptr] <= tmp_aeb;
agb_pipe[pipe_ptr] <= tmp_agb;
aleb_pipe[pipe_ptr] <= tmp_aleb;
aneb_pipe[pipe_ptr] <= tmp_aneb;
ageb_pipe[pipe_ptr] <= tmp_ageb;
if (lpm_pipeline > 1)
pipe_ptr <= (pipe_ptr + 1) % lpm_pipeline;
end
end
// CONTINOUS ASSIGNMENT
assign alb = (lpm_pipeline > 0) ? alb_pipe[pipe_ptr] : tmp_alb;
assign aeb = (lpm_pipeline > 0) ? aeb_pipe[pipe_ptr] : tmp_aeb;
assign agb = (lpm_pipeline > 0) ? agb_pipe[pipe_ptr] : tmp_agb;
assign aleb = (lpm_pipeline > 0) ? aleb_pipe[pipe_ptr] : tmp_aleb;
assign aneb = (lpm_pipeline > 0) ? aneb_pipe[pipe_ptr] : tmp_aneb;
assign ageb = (lpm_pipeline > 0) ? ageb_pipe[pipe_ptr] : tmp_ageb;
endmodule // lpm_compare
//START_MODULE_NAME------------------------------------------------------------
//
// Module Name : lpm_mult
//
// Description : Parameterized multiplier megafunction.
//
// Limitation : n/a
//
// Results expected: dataa[] * datab[] + sum[].
//
//END_MODULE_NAME--------------------------------------------------------------
// BEGINNING OF MODULE
`timescale 1 ps / 1 ps
// MODULE DECLARATION
module lpm_mult (
dataa, // Multiplicand. (Required)
datab, // Multiplier. (Required)
sum, // Partial sum.
aclr, // Asynchronous clear for pipelined usage.
sclr, // Synchronous clear for pipelined usage.
clock, // Clock for pipelined usage.
clken, // Clock enable for pipelined usage.
result // result = dataa[] * datab[] + sum. The product LSB is aligned with the sum LSB.
);
// GLOBAL PARAMETER DECLARATION
parameter lpm_widtha = 1; // Width of the dataa[] port. (Required)
parameter lpm_widthb = 1; // Width of the datab[] port. (Required)
parameter lpm_widthp = 1; // Width of the result[] port. (Required)
parameter lpm_widths = 1; // Width of the sum[] port. (Required)
parameter lpm_representation = "UNSIGNED"; // Type of multiplication performed
parameter lpm_pipeline = 0; // Number of clock cycles of latency
parameter lpm_type = "lpm_mult";
parameter lpm_hint = "UNUSED";
// INPUT PORT DECLARATION
input [lpm_widtha-1:0] dataa;
input [lpm_widthb-1:0] datab;
input [lpm_widths-1:0] sum;
input aclr;
input sclr;
input clock;
input clken;
// OUTPUT PORT DECLARATION
output [lpm_widthp-1:0] result;
// INTERNAL REGISTER/SIGNAL DECLARATION
reg [lpm_widthp-1:0] result_pipe [lpm_pipeline+1:0];
reg [lpm_widthp-1:0] i_prod;
reg [lpm_widthp-1:0] t_p;
reg [lpm_widths-1:0] i_prod_s;
reg [lpm_widths-1:0] t_s;
reg [lpm_widtha+lpm_widthb-1:0] i_prod_ab;
reg [lpm_widtha-1:0] t_a;
reg [lpm_widthb-1:0] t_b;
reg sign_ab;
reg sign_s;
reg [8*5:1] input_a_is_constant;
reg [8*5:1] input_b_is_constant;
reg [8*lpm_widtha:1] input_a_fixed_value;
reg [8*lpm_widthb:1] input_b_fixed_value;
reg [lpm_widtha-1:0] dataa_fixed;
reg [lpm_widthb-1:0] datab_fixed;
// LOCAL INTEGER DECLARATION
integer i;
integer pipe_ptr;
// INTERNAL WIRE DECLARATION
wire [lpm_widtha-1:0] dataa_wire;
wire [lpm_widthb-1:0] datab_wire;
// INTERNAL TRI DECLARATION
tri0 aclr;
tri0 sclr;
tri0 clock;
tri1 clken;
wire i_aclr;
wire i_sclr;
wire i_clock;
wire i_clken;
buf (i_aclr, aclr);
buf (i_sclr, sclr);
buf (i_clock, clock);
buf (i_clken, clken);
// COMPONENT INSTANTIATIONS
LPM_HINT_EVALUATION eva();
// FUNCTION DECLARATION
// convert string to binary bits.
function integer str2bin;
input [8*256:1] str;
input str_width;
reg [8*256:1] reg_str;
reg [255:0] bin;
reg [8:1] tmp;
integer m;
integer str_width;
begin
reg_str = str;
for (m=0; m < str_width; m=m+1)
begin
tmp = reg_str[8:1];
reg_str = reg_str >> 8;
case (tmp)
"0" : bin[m] = 1'b0;
"1" : bin[m] = 1'b1;
default: bin[m] = 1'bx;
endcase
end
str2bin = bin;
end
endfunction
// INITIAL CONSTRUCT BLOCK
initial
begin
// check if lpm_widtha > 0
if (lpm_widtha <= 0)
begin
$display("Error! lpm_widtha must be greater than 0.\n");
$display("Time: %0t Instance: %m", $time);
$finish;
end
// check if lpm_widthb > 0
if (lpm_widthb <= 0)
begin
$display("Error! lpm_widthb must be greater than 0.\n");
$display("Time: %0t Instance: %m", $time);
$finish;
end
// check if lpm_widthp > 0
if (lpm_widthp <= 0)
begin
$display("Error! lpm_widthp must be greater than 0.\n");
$display("Time: %0t Instance: %m", $time);
$finish;
end
// check if lpm_widthp > 0
if (lpm_widths <= 0)
begin
$display("Error! lpm_widths must be greater than 0.\n");
$display("Time: %0t Instance: %m", $time);
$finish;
end
// check for valid lpm_rep value
if ((lpm_representation != "SIGNED") && (lpm_representation != "UNSIGNED"))
begin
$display("Error! lpm_representation value must be \"SIGNED\" or \"UNSIGNED\".", $time);
$display("Time: %0t Instance: %m", $time);
$finish;
end
input_a_is_constant = eva.GET_PARAMETER_VALUE(lpm_hint, "INPUT_A_IS_CONSTANT");
if (input_a_is_constant == "FIXED")
begin
input_a_fixed_value = eva.GET_PARAMETER_VALUE(lpm_hint, "INPUT_A_FIXED_VALUE");
dataa_fixed = str2bin(input_a_fixed_value, lpm_widtha);
end
input_b_is_constant = eva.GET_PARAMETER_VALUE(lpm_hint, "INPUT_B_IS_CONSTANT");
if (input_b_is_constant == "FIXED")
begin
input_b_fixed_value = eva.GET_PARAMETER_VALUE(lpm_hint, "INPUT_B_FIXED_VALUE");
datab_fixed = str2bin(input_b_fixed_value, lpm_widthb);
end
pipe_ptr = 0;
end
// ALWAYS CONSTRUCT BLOCK
always @(dataa_wire or datab_wire or sum)
begin
t_a = dataa_wire;
t_b = datab_wire;
t_s = sum;
sign_ab = 1'b0;
sign_s = 1'b0;
// if inputs are sign number
if (lpm_representation == "SIGNED")
begin
sign_ab = dataa_wire[lpm_widtha-1] ^ datab_wire[lpm_widthb-1];
sign_s = sum[lpm_widths-1];
// if negative number, represent them as 2 compliment number.
if (dataa_wire[lpm_widtha-1] == 1)
t_a = (~dataa_wire) + 1;
if (datab_wire[lpm_widthb-1] == 1)
t_b = (~datab_wire) + 1;
if (sum[lpm_widths-1] == 1)
t_s = (~sum) + 1;
end
// if sum port is not used
if (sum === {lpm_widths{1'bz}})
begin
t_s = {lpm_widths{1'b0}};
sign_s = 1'b0;
end
if (sign_ab == sign_s)
begin
i_prod = (t_a * t_b) + t_s;
i_prod_s = (t_a * t_b) + t_s;
i_prod_ab = (t_a * t_b) + t_s;
end
else
begin
i_prod = (t_a * t_b) - t_s;
i_prod_s = (t_a * t_b) - t_s;
i_prod_ab = (t_a * t_b) - t_s;
end
// if dataa[] * datab[] produces negative number, compliment the result
if (sign_ab)
begin
i_prod = (~i_prod) + 1;
i_prod_s = (~i_prod_s) + 1;
i_prod_ab = (~i_prod_ab) + 1;
end
if ((lpm_widthp < lpm_widths) || (lpm_widthp < (lpm_widtha+lpm_widthb)))
for (i = 0; i < lpm_widthp; i = i + 1)
i_prod[lpm_widthp-1-i] = (lpm_widths > lpm_widtha+lpm_widthb)
? i_prod_s[lpm_widths-1-i]
: i_prod_ab[lpm_widtha+lpm_widthb-1-i];
end
always @(posedge i_clock or posedge i_aclr)
begin
if (i_aclr) // clear the pipeline for result to 0
begin
for (i = 0; i <= (lpm_pipeline + 1); i = i + 1)
result_pipe[i] <= {lpm_widthp{1'b0}};
pipe_ptr <= 0;
end
else if (i_clken == 1)
begin
if(i_sclr)
begin
for (i = 0; i <= (lpm_pipeline + 1); i = i + 1)
result_pipe[i] <= {lpm_widthp{1'b0}};
pipe_ptr <= 0;
end
else
begin
result_pipe[pipe_ptr] <= i_prod;
if (lpm_pipeline > 1)
pipe_ptr <= (pipe_ptr + 1) % lpm_pipeline;
end
end
end
// CONTINOUS ASSIGNMENT
assign dataa_wire = (input_a_is_constant == "FIXED") ? dataa_fixed : dataa;
assign datab_wire = (input_b_is_constant == "FIXED") ? datab_fixed : datab;
assign result = (lpm_pipeline > 0) ? result_pipe[pipe_ptr] : i_prod;
endmodule // lpm_mult
// END OF MODULE
//START_MODULE_NAME------------------------------------------------------------
//
// Module Name : lpm_divide
//
// Description : Parameterized divider megafunction. This function performs a
// divide operation such that denom * quotient + remain = numer
// The function allows for all combinations of signed(two's
// complement) and unsigned inputs. If any of the inputs is
// signed, the output is signed. Otherwise the output is unsigned.
// The function also allows the remainder to be specified as
// always positive (in which case remain >= 0); otherwise remain
// is zero or the same sign as the numerator
// (this parameter is ignored in the case of purely unsigned
// division). Finally the function is also pipelinable.
//
// Limitation : n/a
//
// Results expected: Return quotient and remainder.
//
//END_MODULE_NAME--------------------------------------------------------------
// BEGINNING OF MODULE
`timescale 1 ps / 1 ps
// MODULE DECLARATION
module lpm_divide (
numer, // The numerator (Required)
denom, // The denominator (Required)
clock, // Clock input for pipelined usage
aclr, // Asynchronous clear signal
clken, // Clock enable for pipelined usage.
quotient, // Quotient (Required)
remain // Remainder (Required)
);
// GLOBAL PARAMETER DECLARATION
parameter lpm_widthn = 1; // Width of the numer[] and quotient[] port. (Required)
parameter lpm_widthd = 1; // Width of the denom[] and remain[] port. (Required)
parameter lpm_nrepresentation = "UNSIGNED"; // The representation of numer
parameter lpm_drepresentation = "UNSIGNED"; // The representation of denom
parameter lpm_pipeline = 0; // Number of Clock cycles of latency
parameter lpm_type = "lpm_divide";
parameter lpm_hint = "LPM_REMAINDERPOSITIVE=TRUE";
// INPUT PORT DECLARATION
input [lpm_widthn-1:0] numer;
input [lpm_widthd-1:0] denom;
input clock;
input aclr;
input clken;
// OUTPUT PORT DECLARATION
output [lpm_widthn-1:0] quotient;
output [lpm_widthd-1:0] remain;
// INTERNAL REGISTER/SIGNAL DECLARATION
reg [lpm_widthn-1:0] quotient_pipe [lpm_pipeline+1:0];
reg [lpm_widthd-1:0] remain_pipe [lpm_pipeline+1:0];
reg [lpm_widthn-1:0] tmp_quotient;
reg [lpm_widthd-1:0] tmp_remain;
reg [lpm_widthn-1:0] not_numer;
reg [lpm_widthn-1:0] int_numer;
reg [lpm_widthd-1:0] not_denom;
reg [lpm_widthd-1:0] int_denom;
reg [lpm_widthn-1:0] t_numer;
reg [lpm_widthn-1:0] t_q;
reg [lpm_widthd-1:0] t_denom;
reg [lpm_widthd-1:0] t_r;
reg sign_q;
reg sign_r;
reg sign_n;
reg sign_d;
reg [8*5:1] lpm_remainderpositive;
// LOCAL INTEGER DECLARATION
integer i;
integer rsig;
integer pipe_ptr;
// INTERNAL TRI DECLARATION
tri0 aclr;
tri0 clock;
tri1 clken;
wire i_aclr;
wire i_clock;
wire i_clken;
buf (i_aclr, aclr);
buf (i_clock, clock);
buf (i_clken, clken);
// COMPONENT INSTANTIATIONS
LPM_HINT_EVALUATION eva();
// INITIAL CONSTRUCT BLOCK
initial
begin
// check if lpm_widthn > 0
if (lpm_widthn <= 0)
begin
$display("Error! LPM_WIDTHN must be greater than 0.\n");
$display("Time: %0t Instance: %m", $time);
$finish;
end
// check if lpm_widthd > 0
if (lpm_widthd <= 0)
begin
$display("Error! LPM_WIDTHD must be greater than 0.\n");
$display("Time: %0t Instance: %m", $time);
$finish;
end
// check for valid lpm_nrepresentation value
if ((lpm_nrepresentation != "SIGNED") && (lpm_nrepresentation != "UNSIGNED"))
begin
$display("Error! LPM_NREPRESENTATION value must be \"SIGNED\" or \"UNSIGNED\".");
$display("Time: %0t Instance: %m", $time);
$finish;
end
// check for valid lpm_drepresentation value
if ((lpm_drepresentation != "SIGNED") && (lpm_drepresentation != "UNSIGNED"))
begin
$display("Error! LPM_DREPRESENTATION value must be \"SIGNED\" or \"UNSIGNED\".");
$display("Time: %0t Instance: %m", $time);
$finish;
end
// check for valid lpm_remainderpositive value
lpm_remainderpositive = eva.GET_PARAMETER_VALUE(lpm_hint, "LPM_REMAINDERPOSITIVE");
if ((lpm_remainderpositive == "TRUE") &&
(lpm_remainderpositive == "FALSE"))
begin
$display("Error! LPM_REMAINDERPOSITIVE value must be \"TRUE\" or \"FALSE\".");
$display("Time: %0t Instance: %m", $time);
$finish;
end
for (i = 0; i <= (lpm_pipeline+1); i = i + 1)
begin
quotient_pipe[i] <= {lpm_widthn{1'b0}};
remain_pipe[i] <= {lpm_widthd{1'b0}};
end
pipe_ptr = 0;
end
// ALWAYS CONSTRUCT BLOCK
always @(numer or denom or lpm_remainderpositive)
begin
sign_q = 1'b0;
sign_r = 1'b0;
sign_n = 1'b0;
sign_d = 1'b0;
t_numer = numer;
t_denom = denom;
if (lpm_nrepresentation == "SIGNED")
if (numer[lpm_widthn-1] == 1'b1)
begin
t_numer = ~numer + 1; // numer is negative number
sign_n = 1'b1;
end
if (lpm_drepresentation == "SIGNED")
if (denom[lpm_widthd-1] == 1'b1)
begin
t_denom = ~denom + 1; // denom is negative numbrt
sign_d = 1'b1;
end
t_q = t_numer / t_denom; // get quotient
t_r = t_numer % t_denom; // get remainder
sign_q = sign_n ^ sign_d;
sign_r = (t_r != {lpm_widthd{1'b0}}) ? sign_n : 1'b0;
// Pipeline the result
tmp_quotient = (sign_q == 1'b1) ? (~t_q + 1) : t_q;
tmp_remain = (sign_r == 1'b1) ? (~t_r + 1) : t_r;
// Recalculate the quotient and remainder if remainder is negative number
// and LPM_REMAINDERPOSITIVE=TRUE.
if ((sign_r) && (lpm_remainderpositive == "TRUE"))
begin
tmp_quotient = tmp_quotient + ((sign_d == 1'b1) ? 1 : -1 );
tmp_remain = tmp_remain + t_denom;
end
end
always @(posedge i_clock or posedge i_aclr)
begin
if (i_aclr)
begin
for (i = 0; i <= (lpm_pipeline+1); i = i + 1)
begin
quotient_pipe[i] <= {lpm_widthn{1'b0}};
remain_pipe[i] <= {lpm_widthd{1'b0}};
end
pipe_ptr <= 0;
end
else if (i_clken)
begin
quotient_pipe[pipe_ptr] <= tmp_quotient;
remain_pipe[pipe_ptr] <= tmp_remain;
if (lpm_pipeline > 1)
pipe_ptr <= (pipe_ptr + 1) % lpm_pipeline;
end
end
// CONTINOUS ASSIGNMENT
assign quotient = (lpm_pipeline > 0) ? quotient_pipe[pipe_ptr] : tmp_quotient;
assign remain = (lpm_pipeline > 0) ? remain_pipe[pipe_ptr] : tmp_remain;
endmodule // lpm_divide
// END OF MODULE
//START_MODULE_NAME------------------------------------------------------------
//
// Module Name : lpm_abs
//
// Description : Parameterized absolute value megafunction. This megafunction
// requires the input data to be signed number.
//
// Limitation : n/a
//
// Results expected: Return absolute value of data and the overflow status
//
//END_MODULE_NAME--------------------------------------------------------------
// BEGINNING OF MODULE
`timescale 1 ps / 1 ps
// MODULE DECLARATION
module lpm_abs (
data, // Signed number (Required)
result, // Absolute value of data[].
overflow // High if data = -2 ^ (LPM_WIDTH-1).
);
// GLOBAL PARAMETER DECLARATION
parameter lpm_width = 1; // Width of the data[] and result[] ports.(Required)
parameter lpm_type = "lpm_abs";
parameter lpm_hint = "UNUSED";
// INPUT PORT DECLARATION
input [lpm_width-1:0] data;
// OUTPUT PORT DECLARATION
output [lpm_width-1:0] result;
output overflow;
// INTERNAL REGISTER/SIGNAL DECLARATION
reg [lpm_width-1:0] result_tmp;
reg overflow;
// INITIAL CONSTRUCT BLOCK
initial
begin
if (lpm_width <= 0)
begin
$display("Value of lpm_width parameter must be greater than 0(ERROR)");
$display("Time: %0t Instance: %m", $time);
$finish;
end
end
// ALWAYS CONSTRUCT BLOCK
always @(data)
begin
result_tmp = (data[lpm_width-1] == 1) ? (~data) + 1 : data;
overflow = (data[lpm_width-1] == 1) ? (result_tmp == (1<<(lpm_width-1))) : 0;
end
// CONTINOUS ASSIGNMENT
assign result = result_tmp;
endmodule // lpm_abs
//START_MODULE_NAME------------------------------------------------------------
//
// Module Name : lpm_counter
//
// Description : Parameterized counter megafunction. The lpm_counter
// megafunction is a binary counter that features an up,
// down, or up/down counter with optional synchronous or
// asynchronous clear, set, and load ports.
//
// Limitation : n/a
//
// Results expected: Data output from the counter and carry-out of the MSB.
//
//END_MODULE_NAME--------------------------------------------------------------
// BEGINNING OF MODULE
`timescale 1 ps / 1 ps
// MODULE DECLARATION
module lpm_counter (
clock, // Positive-edge-triggered clock. (Required)
clk_en, // Clock enable input. Enables all synchronous activities.
cnt_en, // Count enable input. Disables the count when low (0) without
// affecting sload, sset, or sclr.
updown, // Controls the direction of the count. High (1) = count up.
// Low (0) = count down.
aclr, // Asynchronous clear input.
aset, // Asynchronous set input.
aload, // Asynchronous load input. Asynchronously loads the counter with
// the value on the data input.
sclr, // Synchronous clear input. Clears the counter on the next active
// clock edge.
sset, // Synchronous set input. Sets the counter on the next active clock edge.
sload, // Synchronous load input. Loads the counter with data[] on the next
// active clock edge.
data, // Parallel data input to the counter.
cin, // Carry-in to the low-order bit.
q, // Data output from the counter.
cout, // Carry-out of the MSB.
eq // Counter decode output. Active high when the counter reaches the specified
// count value.
);
// GLOBAL PARAMETER DECLARATION
parameter lpm_width = 1; //The number of bits in the count, or the width of the q[]
// and data[] ports, if they are used. (Required)
parameter lpm_direction = "UNUSED"; // Direction of the count.
parameter lpm_modulus = 0; // The maximum count, plus one.
parameter lpm_avalue = "UNUSED"; // Constant value that is loaded when aset is high.
parameter lpm_svalue = "UNUSED"; // Constant value that is loaded on the rising edge
// of clock when sset is high.
parameter lpm_pvalue = "UNUSED";
parameter lpm_port_updown = "PORT_CONNECTIVITY";
parameter lpm_type = "lpm_counter";
parameter lpm_hint = "UNUSED";
// INPUT PORT DECLARATION
input clock;
input clk_en;
input cnt_en;
input updown;
input aclr;
input aset;
input aload;
input sclr;
input sset;
input sload;
input [lpm_width-1:0] data;
input cin;
// OUTPUT PORT DECLARATION
output [lpm_width-1:0] q;
output cout;
output [15:0] eq;
// INTERNAL REGISTER/SIGNAL DECLARATION
reg [lpm_width-1:0] tmp_count;
reg [lpm_width-1:0] adata;
reg use_adata;
reg tmp_updown;
reg [lpm_width:0] tmp_modulus;
reg [lpm_width:0] max_modulus;
reg [lpm_width-1:0] svalue;
reg [lpm_width-1:0] avalue;
reg [lpm_width-1:0] pvalue;
// INTERNAL WIRE DECLARATION
wire w_updown;
wire [lpm_width-1:0] final_count;
// LOCAL INTEGER DECLARATION
integer i;
// INTERNAL TRI DECLARATION
tri1 clk_en;
tri1 cnt_en;
tri0 aclr;
tri0 aset;
tri0 aload;
tri0 sclr;
tri0 sset;
tri0 sload;
tri1 cin;
tri1 updown_z;
wire i_clk_en;
wire i_cnt_en;
wire i_aclr;
wire i_aset;
wire i_aload;
wire i_sclr;
wire i_sset;
wire i_sload;
wire i_cin;
wire i_updown;
buf (i_clk_en, clk_en);
buf (i_cnt_en, cnt_en);
buf (i_aclr, aclr);
buf (i_aset, aset);
buf (i_aload, aload);
buf (i_sclr, sclr);
buf (i_sset, sset);
buf (i_sload, sload);
buf (i_cin, cin);
buf (i_updown, updown_z);
// TASK DECLARATION
task string_to_reg;
input [8*40:1] string_value;
output [lpm_width-1:0] value;
reg [8*40:1] reg_s;
reg [8:1] digit;
reg [8:1] tmp;
reg [lpm_width-1:0] ivalue;
integer m;
begin
ivalue = {lpm_width{1'b0}};
reg_s = string_value;
for (m=1; m<=40; m=m+1)
begin
tmp = reg_s[320:313];
digit = tmp & 8'b00001111;
reg_s = reg_s << 8;
ivalue = ivalue * 10 + digit;
end
value = ivalue;
end
endtask
// INITIAL CONSTRUCT BLOCK
initial
begin
max_modulus = 1 << lpm_width;
// check if lpm_width < 0
if (lpm_width <= 0)
begin
$display("Error! LPM_WIDTH must be greater than 0.\n");
$display("Time: %0t Instance: %m", $time);
$finish;
end
// check if lpm_modulus < 0
if (lpm_modulus < 0)
begin
$display("Error! LPM_MODULUS must be greater or equal to 0.\n");
$display("Time: %0t Instance: %m", $time);
$finish;
end
// check if lpm_modulus > 1<<lpm_width
if (lpm_modulus > max_modulus)
begin
$display("Warning! LPM_MODULUS should be within 1 to 2^LPM_WIDTH. Assuming no modulus input.\n");
$display ("Time: %0t Instance: %m", $time);
end
// check if lpm_direction valid
if ((lpm_direction != "UNUSED") && (lpm_direction != "DEFAULT") &&
(lpm_direction != "UP") && (lpm_direction != "DOWN"))
begin
$display("Error! LPM_DIRECTION must be \"UP\" or \"DOWN\" if used.\n");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if (lpm_avalue == "UNUSED")
avalue = {lpm_width{1'b1}};
else
string_to_reg(lpm_avalue, avalue);
if (lpm_svalue == "UNUSED")
svalue = {lpm_width{1'b1}};
else
string_to_reg(lpm_svalue, svalue);
if (lpm_pvalue == "UNUSED")
pvalue = {lpm_width{1'b0}};
else
string_to_reg(lpm_pvalue, pvalue);
tmp_modulus = ((lpm_modulus == 0) || (lpm_modulus > max_modulus))
? max_modulus : lpm_modulus;
tmp_count = pvalue;
use_adata = 1'b0;
end
// NCSIM will only assigns 1'bZ to unconnected port at time 0fs + 1
// verilator lint_off STMTDLY
initial #0
// verilator lint_on STMTDLY
begin
// // check if lpm_direction valid
if ((lpm_direction != "UNUSED") && (lpm_direction != "DEFAULT") && (updown !== 1'bz) &&
(lpm_port_updown == "PORT_CONNECTIVITY"))
begin
$display("Error! LPM_DIRECTION and UPDOWN cannot be used at the same time.\n");
$display("Time: %0t Instance: %m", $time);
$finish;
end
end
// ALWAYS CONSTRUCT BLOCK
always @(posedge i_aclr or posedge i_aset or posedge i_aload or posedge clock)
begin
if (i_aclr || i_aset || i_aload)
use_adata <= 1'b1;
else if ($time > 0)
begin
if (i_clk_en)
begin
use_adata <= 1'b0;
if (i_sclr)
tmp_count <= 0;
else if (i_sset)
tmp_count <= svalue;
else if (i_sload)
tmp_count <= data;
else if (i_cnt_en && i_cin)
begin
if (w_updown)
tmp_count <= (final_count == tmp_modulus-1) ? 0
: final_count+1;
else
tmp_count <= (final_count == 0) ? tmp_modulus-1
: final_count-1;
end
else
tmp_count <= final_count;
end
end
end
always @(i_aclr or i_aset or i_aload or data or avalue)
begin
if (i_aclr)
begin
adata <= 0;
end
else if (i_aset)
begin
adata <= avalue;
end
else if (i_aload)
adata <= data;
end
// CONTINOUS ASSIGNMENT
assign q = final_count;
assign final_count = (use_adata == 1'b1) ? adata : tmp_count;
assign cout = (i_cin && (((w_updown==0) && (final_count==0)) ||
((w_updown==1) && ((final_count==tmp_modulus-1) ||
(final_count=={lpm_width{1'b1}}))) ))
? 1'b1 : 1'b0;
assign updown_z = updown;
assign w_updown = (lpm_port_updown == "PORT_USED") ? i_updown :
(lpm_port_updown == "PORT_UNUSED") ? ((lpm_direction == "DOWN") ? 1'b0 : 1'b1) :
((((lpm_direction == "UNUSED") || (lpm_direction == "DEFAULT")) && (i_updown == 1)) ||
(lpm_direction == "UP"))
? 1'b1 : 1'b0;
assign eq = {16{1'b0}};
endmodule // lpm_counter
// END OF MODULE
//START_MODULE_NAME------------------------------------------------------------
//
// Module Name : lpm_latch
//
// Description : Parameterized latch megafunction.
//
// Limitation : n/a
//
// Results expected: Data output from the latch.
//
//END_MODULE_NAME--------------------------------------------------------------
// BEGINNING OF MODULE
`timescale 1 ps / 1 ps
// MODULE DECLARATION
module lpm_latch (
data, // Data input to the latch.
gate, // Latch enable input. High = flow-through, low = latch. (Required)
aclr, // Asynchronous clear input.
aset, // Asynchronous set input.
aconst,
q // Data output from the latch.
);
// GLOBAL PARAMETER DECLARATION
parameter lpm_width = 1; // Width of the data[] and q[] ports. (Required)
parameter lpm_avalue = "UNUSED"; // Constant value that is loaded when aset is high.
parameter lpm_pvalue = "UNUSED";
parameter lpm_type = "lpm_latch";
parameter lpm_hint = "UNUSED";
// INPUT PORT DECLARATION
input [lpm_width-1:0] data;
input gate;
input aclr;
input aset;
input aconst;
// OUTPUT PORT DECLARATION
output [lpm_width-1:0] q;
// INTERNAL REGISTER/SIGNAL DECLARATION
reg [lpm_width-1:0] q;
reg [lpm_width-1:0] avalue;
reg [lpm_width-1:0] pvalue;
// INTERNAL TRI DECLARATION
tri0 [lpm_width-1:0] data;
tri0 aclr;
tri0 aset;
tri0 aconst;
wire i_aclr;
wire i_aset;
buf (i_aclr, aclr);
buf (i_aset, aset);
// TASK DECLARATION
task string_to_reg;
input [8*40:1] string_value;
output [lpm_width-1:0] value;
reg [8*40:1] reg_s;
reg [8:1] digit;
reg [8:1] tmp;
reg [lpm_width-1:0] ivalue;
integer m;
begin
ivalue = {lpm_width{1'b0}};
reg_s = string_value;
for (m=1; m<=40; m=m+1)
begin
tmp = reg_s[320:313];
digit = tmp & 8'b00001111;
reg_s = reg_s << 8;
ivalue = ivalue * 10 + digit;
end
value = ivalue;
end
endtask
// INITIAL CONSTRUCT BLOCK
initial
begin
if (lpm_width <= 0)
begin
$display("Value of lpm_width parameter must be greater than 0 (ERROR)");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if (lpm_pvalue != "UNUSED")
begin
string_to_reg(lpm_pvalue, pvalue);
q = pvalue;
end
if (lpm_avalue == "UNUSED")
avalue = {lpm_width{1'b1}};
else
string_to_reg(lpm_avalue, avalue);
end
// ALWAYS CONSTRUCT BLOCK
always @(data or gate or i_aclr or i_aset or avalue)
begin
if (i_aclr)
q <= {lpm_width{1'b0}};
else if (i_aset)
q <= avalue;
else if (gate)
q <= data;
end
endmodule // lpm_latch
//START_MODULE_NAME------------------------------------------------------------
//
// Module Name : lpm_ff
//
// Description : Parameterized flipflop megafunction. The lpm_ff function
// contains features that are not available in the DFF, DFFE,
// DFFEA, TFF, and TFFE primitives, such as synchronous or
// asynchronous set, clear, and load inputs.
//
// Limitation : n/a
//
// Results expected: Data output from D or T flipflops.
//
//END_MODULE_NAME--------------------------------------------------------------
// BEGINNING OF MODULE
`timescale 1 ps / 1 ps
// MODULE DECLARATION
module lpm_ff (
data, // T-type flipflop: Toggle enable
// D-type flipflop: Data input
clock, // Positive-edge-triggered clock. (Required)
enable, // Clock enable input.
aclr, // Asynchronous clear input.
aset, // Asynchronous set input.
aload, // Asynchronous load input. Asynchronously loads the flipflop with
// the value on the data input.
sclr, // Synchronous clear input.
sset, // Synchronous set input.
sload, // Synchronous load input. Loads the flipflop with the value on the
// data input on the next active clock edge.
q // Data output from D or T flipflops. (Required)
);
// GLOBAL PARAMETER DECLARATION
parameter lpm_width = 1; // Width of the data[] and q[] ports. (Required)
parameter lpm_avalue = "UNUSED"; // Constant value that is loaded when aset is high.
parameter lpm_svalue = "UNUSED"; // Constant value that is loaded on the rising edge
// of clock when sset is high.
parameter lpm_pvalue = "UNUSED";
parameter lpm_fftype = "DFF"; // Type of flipflop
parameter lpm_type = "lpm_ff";
parameter lpm_hint = "UNUSED";
// INPUT PORT DECLARATION
input [lpm_width-1:0] data;
input clock;
input enable;
input aclr;
input aset;
input aload;
input sclr;
input sset;
input sload ;
// OUTPUT PORT DECLARATION
output [lpm_width-1:0] q;
// INTERNAL REGISTER/SIGNAL DECLARATION
reg [lpm_width-1:0] tmp_q;
reg [lpm_width-1:0] adata;
reg use_adata;
reg [lpm_width-1:0] svalue;
reg [lpm_width-1:0] avalue;
reg [lpm_width-1:0] pvalue;
// INTERNAL WIRE DECLARATION
wire [lpm_width-1:0] final_q;
// LOCAL INTEGER DECLARATION
integer i;
// INTERNAL TRI DECLARATION
tri1 [lpm_width-1:0] data;
tri1 enable;
tri0 sload;
tri0 sclr;
tri0 sset;
tri0 aload;
tri0 aclr;
tri0 aset;
wire i_enable;
wire i_sload;
wire i_sclr;
wire i_sset;
wire i_aload;
wire i_aclr;
wire i_aset;
buf (i_enable, enable);
buf (i_sload, sload);
buf (i_sclr, sclr);
buf (i_sset, sset);
buf (i_aload, aload);
buf (i_aclr, aclr);
buf (i_aset, aset);
// TASK DECLARATION
task string_to_reg;
input [8*40:1] string_value;
output [lpm_width-1:0] value;
reg [8*40:1] reg_s;
reg [8:1] digit;
reg [8:1] tmp;
reg [lpm_width-1:0] ivalue;
integer m;
begin
ivalue = {lpm_width{1'b0}};
reg_s = string_value;
for (m=1; m<=40; m=m+1)
begin
tmp = reg_s[320:313];
digit = tmp & 8'b00001111;
reg_s = reg_s << 8;
ivalue = ivalue * 10 + digit;
end
value = ivalue;
end
endtask
// INITIAL CONSTRUCT BLOCK
initial
begin
if (lpm_width <= 0)
begin
$display("Value of lpm_width parameter must be greater than 0(ERROR)");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if ((lpm_fftype != "DFF") &&
(lpm_fftype != "TFF") &&
(lpm_fftype != "UNUSED")) // non-LPM 220 standard
begin
$display("Error! LPM_FFTYPE value must be \"DFF\" or \"TFF\".");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if (lpm_avalue == "UNUSED")
avalue = {lpm_width{1'b1}};
else
string_to_reg(lpm_avalue, avalue);
if (lpm_svalue == "UNUSED")
svalue = {lpm_width{1'b1}};
else
string_to_reg(lpm_svalue, svalue);
if (lpm_pvalue == "UNUSED")
pvalue = {lpm_width{1'b0}};
else
string_to_reg(lpm_pvalue, pvalue);
tmp_q = pvalue;
use_adata = 1'b0;
end
// ALWAYS CONSTRUCT BLOCK
always @(posedge i_aclr or posedge i_aset or posedge i_aload or posedge clock)
begin // Asynchronous process
if (i_aclr || i_aset || i_aload)
use_adata <= 1'b1;
else if ($time > 0)
begin // Synchronous process
if (i_enable)
begin
use_adata <= 1'b0;
if (i_sclr)
tmp_q <= 0;
else if (i_sset)
tmp_q <= svalue;
else if (i_sload) // Load data
tmp_q <= data;
else
begin
if (lpm_fftype == "TFF") // toggle
begin
for (i = 0; i < lpm_width; i=i+1)
if (data[i] == 1'b1)
tmp_q[i] <= ~final_q[i];
else
tmp_q[i] <= final_q[i];
end
else // DFF, load data
tmp_q <= data;
end
end
end
end
always @(i_aclr or i_aset or i_aload or data or avalue or pvalue)
begin
if (i_aclr === 1'b1)
adata <= {lpm_width{1'b0}};
else if (i_aclr === 1'bx)
adata <= {lpm_width{1'bx}};
else if (i_aset)
adata <= avalue;
else if (i_aload)
adata <= data;
else if ((i_aclr === 1'b0) && ($time == 0))
adata <= pvalue;
end
// CONTINOUS ASSIGNMENT
assign q = final_q;
assign final_q = (use_adata == 1'b1) ? adata : tmp_q;
endmodule // lpm_ff
// END OF MODULE
//START_MODULE_NAME------------------------------------------------------------
//
// Module Name : lpm_shiftreg
//
// Description : Parameterized shift register megafunction.
//
// Limitation : n/a
//
// Results expected: Data output from the shift register and the Serial shift data output.
//
//END_MODULE_NAME--------------------------------------------------------------
// BEGINNING OF MODULE
`timescale 1 ps / 1 ps
// MODULE DECLARATION
module lpm_shiftreg (
data, // Data input to the shift register.
clock, // Positive-edge-triggered clock. (Required)
enable, // Clock enable input
shiftin, // Serial shift data input.
load, // Synchronous parallel load. High (1): load operation;
// low (0): shift operation.
aclr, // Asynchronous clear input.
aset, // Asynchronous set input.
sclr, // Synchronous clear input.
sset, // Synchronous set input.
q, // Data output from the shift register.
shiftout // Serial shift data output.
);
// GLOBAL PARAMETER DECLARATION
parameter lpm_width = 1; // Width of the data[] and q ports. (Required)
parameter lpm_direction = "LEFT"; // Values are "LEFT", "RIGHT", and "UNUSED".
parameter lpm_avalue = "UNUSED"; // Constant value that is loaded when aset is high.
parameter lpm_svalue = "UNUSED"; // Constant value that is loaded on the rising edge
// of clock when sset is high.
parameter lpm_pvalue = "UNUSED";
parameter lpm_type = "lpm_shiftreg";
parameter lpm_hint = "UNUSED";
// INPUT PORT DECLARATION
input [lpm_width-1:0] data;
input clock;
input enable;
input shiftin;
input load;
input aclr;
input aset;
input sclr;
input sset;
// OUTPUT PORT DECLARATION
output [lpm_width-1:0] q;
output shiftout;
// INTERNAL REGISTER/SIGNAL DECLARATION
reg [lpm_width-1:0] tmp_q;
reg abit;
reg [lpm_width-1:0] svalue;
reg [lpm_width-1:0] avalue;
reg [lpm_width-1:0] pvalue;
// LOCAL INTEGER DECLARATION
integer i;
// INTERNAL WIRE DECLARATION
wire tmp_shiftout;
// INTERNAL TRI DECLARATION
tri1 enable;
tri1 shiftin;
tri0 load;
tri0 aclr;
tri0 aset;
tri0 sclr;
tri0 sset;
wire i_enable;
wire i_shiftin;
wire i_load;
wire i_aclr;
wire i_aset;
wire i_sclr;
wire i_sset;
buf (i_enable, enable);
buf (i_shiftin, shiftin);
buf (i_load, load);
buf (i_aclr, aclr);
buf (i_aset, aset);
buf (i_sclr, sclr);
buf (i_sset, sset);
// TASK DECLARATION
task string_to_reg;
input [8*40:1] string_value;
output [lpm_width-1:0] value;
reg [8*40:1] reg_s;
reg [8:1] digit;
reg [8:1] tmp;
reg [lpm_width-1:0] ivalue;
integer m;
begin
ivalue = {lpm_width{1'b0}};
reg_s = string_value;
for (m=1; m<=40; m=m+1)
begin
tmp = reg_s[320:313];
digit = tmp & 8'b00001111;
reg_s = reg_s << 8;
ivalue = ivalue * 10 + digit;
end
value = ivalue;
end
endtask
// INITIAL CONSTRUCT BLOCK
initial
begin
if (lpm_width <= 0)
begin
$display("Value of lpm_width parameter must be greater than 0 (ERROR)");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if ((lpm_direction != "LEFT") &&
(lpm_direction != "RIGHT") &&
(lpm_direction != "UNUSED")) // non-LPM 220 standard
begin
$display("Error! LPM_DIRECTION value must be \"LEFT\" or \"RIGHT\".");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if (lpm_avalue == "UNUSED")
avalue = {lpm_width{1'b1}};
else
string_to_reg(lpm_avalue, avalue);
if (lpm_svalue == "UNUSED")
svalue = {lpm_width{1'b1}};
else
string_to_reg(lpm_svalue, svalue);
if (lpm_pvalue == "UNUSED")
pvalue = {lpm_width{1'b0}};
else
string_to_reg(lpm_pvalue, pvalue);
tmp_q = pvalue;
end
// ALWAYS CONSTRUCT BLOCK
always @(i_aclr or i_aset or avalue)
begin
if (i_aclr)
tmp_q <= {lpm_width{1'b0}};
else if (i_aset)
tmp_q <= avalue;
end
always @(posedge clock)
begin
if (i_aclr)
tmp_q <= (i_aset) ? {lpm_width{1'bx}} : {lpm_width{1'b0}};
else if (i_aset)
tmp_q <= avalue;
else
begin
if (i_enable)
begin
if (i_sclr)
tmp_q <= {lpm_width{1'b0}};
else if (i_sset)
tmp_q <= svalue;
else if (i_load)
tmp_q <= data;
else if (!i_load)
begin
if ((lpm_direction == "LEFT") || (lpm_direction == "UNUSED"))
{abit,tmp_q} <= {tmp_q,i_shiftin};
else if (lpm_direction == "RIGHT")
{tmp_q,abit} <= {i_shiftin,tmp_q};
end
end
end
end
// CONTINOUS ASSIGNMENT
assign tmp_shiftout = (lpm_direction == "RIGHT") ? tmp_q[0]
: tmp_q[lpm_width-1];
assign q = tmp_q;
assign shiftout = tmp_shiftout;
endmodule // lpm_shiftreg
// END OF MODULE
//START_MODULE_NAME------------------------------------------------------------
//
// Module Name : lpm_ram_dq
//
// Description : Parameterized RAM with separate input and output ports megafunction.
// lpm_ram_dq implement asynchronous memory or memory with synchronous
// inputs and/or outputs.
//
// Limitation : n/a
//
// Results expected: Data output from the memory.
//
//END_MODULE_NAME--------------------------------------------------------------
// BEGINNING OF MODULE
`timescale 1 ps / 1 ps
// MODULE DECLARATION
module lpm_ram_dq (
data, // Data input to the memory. (Required)
address, // Address input to the memory. (Required)
inclock, // Synchronizes memory loading.
outclock, // Synchronizes q outputs from memory.
we, // Write enable input. Enables write operations to the memory when high. (Required)
q // Data output from the memory. (Required)
);
// GLOBAL PARAMETER DECLARATION
parameter lpm_width = 1; // Width of data[] and q[] ports. (Required)
parameter lpm_widthad = 1; // Width of the address port. (Required)
parameter lpm_numwords = 1 << lpm_widthad; // Number of words stored in memory.
parameter lpm_indata = "REGISTERED"; // Controls whether the data port is registered.
parameter lpm_address_control = "REGISTERED"; // Controls whether the address and we ports are registered.
parameter lpm_outdata = "REGISTERED"; // Controls whether the q ports are registered.
parameter lpm_file = "UNUSED"; // Name of the file containing RAM initialization data.
parameter use_eab = "ON"; // Specified whether to use the EAB or not.
parameter intended_device_family = "Stratix";
parameter lpm_type = "lpm_ram_dq";
parameter lpm_hint = "UNUSED";
// INPUT PORT DECLARATION
input [lpm_width-1:0] data;
input [lpm_widthad-1:0] address;
input inclock;
input outclock;
input we;
// OUTPUT PORT DECLARATION
output [lpm_width-1:0] q;
// INTERNAL REGISTER/SIGNAL DECLARATION
reg [lpm_width-1:0] mem_data [lpm_numwords-1:0];
reg [lpm_width-1:0] tmp_q;
reg [lpm_width-1:0] pdata;
reg [lpm_width-1:0] in_data;
reg [lpm_widthad-1:0] paddress;
reg pwe;
reg [lpm_width-1:0] ZEROS, ONES, UNKNOWN;
`ifdef VERILATOR
reg [`LPM_MAX_NAME_SZ*8:1] ram_initf;
`else
reg [8*256:1] ram_initf;
`endif
// LOCAL INTEGER DECLARATION
integer i;
// INTERNAL TRI DECLARATION
tri0 inclock;
tri0 outclock;
wire i_inclock;
wire i_outclock;
buf (i_inclock, inclock);
buf (i_outclock, outclock);
// COMPONENT INSTANTIATIONS
LPM_DEVICE_FAMILIES dev ();
LPM_MEMORY_INITIALIZATION mem ();
// FUNCTON DECLARATION
// Check the validity of the address.
function ValidAddress;
input [lpm_widthad-1:0] paddress;
begin
ValidAddress = 1'b0;
if (^paddress === {lpm_widthad{1'bx}})
begin
$display("%t:Error! Invalid address.\n", $time);
$display("Time: %0t Instance: %m", $time);
end
else if (paddress >= lpm_numwords)
begin
$display("%t:Error! Address out of bound on RAM.\n", $time);
$display("Time: %0t Instance: %m", $time);
end
else
ValidAddress = 1'b1;
end
endfunction
// INITIAL CONSTRUCT BLOCK
initial
begin
// Initialize the internal data register.
pdata = {lpm_width{1'b0}};
paddress = {lpm_widthad{1'b0}};
pwe = 1'b0;
if (lpm_width <= 0)
begin
$display("Error! LPM_WIDTH parameter must be greater than 0.");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if (lpm_widthad <= 0)
begin
$display("Error! LPM_WIDTHAD parameter must be greater than 0.");
$display("Time: %0t Instance: %m", $time);
$finish;
end
// check for number of words out of bound
if ((lpm_numwords > (1 << lpm_widthad)) ||
(lpm_numwords <= (1 << (lpm_widthad-1))))
begin
$display("Error! The ceiling of log2(LPM_NUMWORDS) must equal to LPM_WIDTHAD.");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if ((lpm_address_control != "REGISTERED") && (lpm_address_control != "UNREGISTERED"))
begin
$display("Error! LPM_ADDRESS_CONTROL must be \"REGISTERED\" or \"UNREGISTERED\".");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if ((lpm_indata != "REGISTERED") && (lpm_indata != "UNREGISTERED"))
begin
$display("Error! LPM_INDATA must be \"REGISTERED\" or \"UNREGISTERED\".");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if ((lpm_outdata != "REGISTERED") && (lpm_outdata != "UNREGISTERED"))
begin
$display("Error! LPM_OUTDATA must be \"REGISTERED\" or \"UNREGISTERED\".");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if (dev.IS_VALID_FAMILY(intended_device_family) == 0)
begin
$display ("Error! Unknown INTENDED_DEVICE_FAMILY=%s.", intended_device_family);
$display("Time: %0t Instance: %m", $time);
$finish;
end
for (i=0; i < lpm_width; i=i+1)
begin
ZEROS[i] = 1'b0;
ONES[i] = 1'b1;
UNKNOWN[i] = 1'bX;
end
for (i = 0; i < lpm_numwords; i=i+1)
mem_data[i] = {lpm_width{1'b0}};
// load data to the RAM
if (lpm_file != "UNUSED")
begin
mem.convert_to_ver_file(lpm_file, lpm_width, ram_initf);
$readmemh(ram_initf, mem_data);
end
tmp_q = ZEROS;
end
// ALWAYS CONSTRUCT BLOCK
always @(posedge i_inclock)
begin
if (lpm_address_control == "REGISTERED")
begin
if ((we) && (use_eab != "ON") &&
(lpm_hint != "USE_EAB=ON"))
begin
if (lpm_indata == "REGISTERED")
mem_data[address] <= data;
else
mem_data[address] <= pdata;
end
paddress <= address;
pwe <= we;
end
if (lpm_indata == "REGISTERED")
pdata <= data;
end
always @(data)
begin
if (lpm_indata == "UNREGISTERED")
pdata <= data;
end
always @(address)
begin
if (lpm_address_control == "UNREGISTERED")
paddress <= address;
end
always @(we)
begin
if (lpm_address_control == "UNREGISTERED")
pwe <= we;
end
always @(pdata or paddress or pwe)
begin :UNREGISTERED_INCLOCK
if (ValidAddress(paddress))
begin
if ((lpm_address_control == "UNREGISTERED") && (pwe))
mem_data[paddress] <= pdata;
end
else
begin
if (lpm_outdata == "UNREGISTERED")
tmp_q <= {lpm_width{1'bx}};
end
end
always @(posedge i_outclock)
begin
if (lpm_outdata == "REGISTERED")
begin
if (ValidAddress(paddress))
tmp_q <= mem_data[paddress];
else
tmp_q <= {lpm_width{1'bx}};
end
end
always @(i_inclock or pwe or paddress or pdata)
begin
if ((lpm_address_control == "REGISTERED") && (pwe))
if ((use_eab == "ON") || (lpm_hint == "USE_EAB=ON"))
begin
if (i_inclock == 1'b0)
mem_data[paddress] = pdata;
end
end
// CONTINOUS ASSIGNMENT
assign q = (lpm_outdata == "UNREGISTERED") ? mem_data[paddress] : tmp_q;
endmodule // lpm_ram_dq
// END OF MODULE
//START_MODULE_NAME------------------------------------------------------------
//
// Module Name : lpm_ram_dp
//
// Description : Parameterized dual-port RAM megafunction.
//
// Limitation : n/a
//
// Results expected: Data output from the memory.
//
//END_MODULE_NAME--------------------------------------------------------------
// BEGINNING OF MODULE
`timescale 1 ps / 1 ps
// MODULE DECLARATION
module lpm_ram_dp (
data, // Data input to the memory. (Required)
rdaddress, // Read address input to the memory. (Required)
wraddress, // Write address input to the memory. (Required)
rdclock, // Positive-edge-triggered clock for read operation.
rdclken, // Clock enable for rdclock.
wrclock, // Positive-edge-triggered clock for write operation.
wrclken, // Clock enable for wrclock.
rden, // Read enable input. Disables reading when low (0).
wren, // Write enable input. (Required)
q // Data output from the memory. (Required)
);
// GLOBAL PARAMETER DECLARATION
parameter lpm_width = 1; // Width of the data[] and q[] ports. (Required)
parameter lpm_widthad = 1; // Width of the rdaddress[] and wraddress[] ports. (Required)
parameter lpm_numwords = 1 << lpm_widthad; // Number of words stored in memory.
parameter lpm_indata = "REGISTERED"; // Determines the clock used by the data port.
parameter lpm_rdaddress_control = "REGISTERED"; // Determines the clock used by the rdaddress and rden ports.
parameter lpm_wraddress_control = "REGISTERED"; // Determines the clock used by the wraddress and wren ports.
parameter lpm_outdata = "REGISTERED"; // Determines the clock used by the q[] pxort.
parameter lpm_file = "UNUSED"; // Name of the file containing RAM initialization data.
parameter use_eab = "ON"; // Specified whether to use the EAB or not.
parameter rden_used = "TRUE"; // Specified whether to use the rden port or not.
parameter intended_device_family = "Stratix";
parameter lpm_type = "lpm_ram_dp";
parameter lpm_hint = "UNUSED";
// INPUT PORT DECLARATION
input [lpm_width-1:0] data;
input [lpm_widthad-1:0] rdaddress;
input [lpm_widthad-1:0] wraddress;
input rdclock;
input rdclken;
input wrclock;
input wrclken;
input rden;
input wren;
// OUTPUT PORT DECLARATION
output [lpm_width-1:0] q;
// INTERNAL REGISTER/SIGNAL DECLARATION
reg [lpm_width-1:0] mem_data [(1<<lpm_widthad)-1:0];
reg [lpm_width-1:0] i_data_reg, i_data_tmp, i_q_reg, i_q_tmp;
reg [lpm_widthad-1:0] i_wraddress_reg, i_wraddress_tmp;
reg [lpm_widthad-1:0] i_rdaddress_reg, i_rdaddress_tmp;
reg i_wren_reg, i_wren_tmp, i_rden_reg, i_rden_tmp;
`ifdef VERILATOR
reg [`LPM_MAX_NAME_SZ*8:1] ram_initf;
`else
reg [8*256:1] ram_initf;
`endif
// LOCAL INTEGER DECLARATION
integer i, i_numwords;
// INTERNAL TRI DECLARATION
tri0 wrclock;
tri1 wrclken;
tri0 rdclock;
tri1 rdclken;
tri0 wren;
tri1 rden;
wire i_inclock;
wire i_inclocken;
wire i_outclock;
wire i_outclocken;
wire i_wren;
wire i_rden;
buf (i_inclock, wrclock);
buf (i_inclocken, wrclken);
buf (i_outclock, rdclock);
buf (i_outclocken, rdclken);
buf (i_wren, wren);
buf (i_rden, rden);
// COMPONENT INSTANTIATIONS
LPM_DEVICE_FAMILIES dev ();
LPM_MEMORY_INITIALIZATION mem ();
// FUNCTON DECLARATION
function ValidAddress;
input [lpm_widthad-1:0] paddress;
begin
ValidAddress = 1'b0;
if (^paddress === {lpm_widthad{1'bx}})
begin
$display("%t:Error! Invalid address.\n", $time);
$display("Time: %0t Instance: %m", $time);
end
else if (paddress >= lpm_numwords)
begin
$display("%t:Error! Address out of bound on RAM.\n", $time);
$display("Time: %0t Instance: %m", $time);
end
else
ValidAddress = 1'b1;
end
endfunction
// INITIAL CONSTRUCT BLOCK
initial
begin
// Check for invalid parameters
if (lpm_width < 1)
begin
$display("Error! lpm_width parameter must be greater than 0.");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if (lpm_widthad < 1)
begin
$display("Error! lpm_widthad parameter must be greater than 0.");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if ((lpm_indata != "REGISTERED") && (lpm_indata != "UNREGISTERED"))
begin
$display("Error! lpm_indata must be \"REGISTERED\" or \"UNREGISTERED\".");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if ((lpm_outdata != "REGISTERED") && (lpm_outdata != "UNREGISTERED"))
begin
$display("Error! lpm_outdata must be \"REGISTERED\" or \"UNREGISTERED\".");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if ((lpm_wraddress_control != "REGISTERED") && (lpm_wraddress_control != "UNREGISTERED"))
begin
$display("Error! lpm_wraddress_control must be \"REGISTERED\" or \"UNREGISTERED\".");
$display("Time: %0t Instance: %m", $time);
end
if ((lpm_rdaddress_control != "REGISTERED") && (lpm_rdaddress_control != "UNREGISTERED"))
begin
$display("Error! lpm_rdaddress_control must be \"REGISTERED\" or \"UNREGISTERED\".");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if (dev.IS_VALID_FAMILY(intended_device_family) == 0)
begin
$display ("Error! Unknown INTENDED_DEVICE_FAMILY=%s.", intended_device_family);
$display("Time: %0t Instance: %m", $time);
$finish;
end
// Initialize mem_data
i_numwords = (lpm_numwords) ? lpm_numwords : (1<<lpm_widthad);
if (lpm_file == "UNUSED")
for (i=0; i<i_numwords; i=i+1)
mem_data[i] = {lpm_width{1'b0}};
else
begin
mem.convert_to_ver_file(lpm_file, lpm_width, ram_initf);
$readmemh(ram_initf, mem_data);
end
// Initialize registers
i_data_reg = {lpm_width{1'b0}};
i_wraddress_reg = {lpm_widthad{1'b0}};
i_rdaddress_reg = {lpm_widthad{1'b0}};
i_wren_reg = 1'b0;
if (rden_used == "TRUE")
i_rden_reg = 1'b0;
else
i_rden_reg = 1'b1;
// Initialize output
i_q_reg = {lpm_width{1'b0}};
if ((use_eab == "ON") || (lpm_hint == "USE_EAB=ON"))
begin
i_q_tmp = {lpm_width{1'b1}};
end
else
i_q_tmp = {lpm_width{1'b0}};
end
// ALWAYS CONSTRUCT BLOCK
always @(posedge i_inclock)
begin
if (lpm_indata == "REGISTERED")
if ((i_inclocken == 1'b1) && ($time > 0))
i_data_reg <= data;
if (lpm_wraddress_control == "REGISTERED")
if ((i_inclocken == 1'b1) && ($time > 0))
begin
i_wraddress_reg <= wraddress;
i_wren_reg <= i_wren;
end
end
always @(posedge i_outclock)
begin
if (lpm_outdata == "REGISTERED")
if ((i_outclocken == 1'b1) && ($time > 0))
begin
i_q_reg <= i_q_tmp;
end
if (lpm_rdaddress_control == "REGISTERED")
if ((i_outclocken == 1'b1) && ($time > 0))
begin
i_rdaddress_reg <= rdaddress;
i_rden_reg <= i_rden;
end
end
//=========
// Memory
//=========
always @(i_data_tmp or i_wren_tmp or i_wraddress_tmp or negedge i_inclock)
begin
if (i_wren_tmp == 1'b1)
if (ValidAddress(i_wraddress_tmp))
begin
if (((use_eab == "ON") || (lpm_hint == "USE_EAB=ON")) &&
(lpm_wraddress_control == "REGISTERED"))
begin
if (i_inclock == 1'b0)
mem_data[i_wraddress_tmp] <= i_data_tmp;
end
else
mem_data[i_wraddress_tmp] <= i_data_tmp;
end
end
always @(i_rden_tmp or i_rdaddress_tmp or mem_data[i_rdaddress_tmp])
begin
if (i_rden_tmp == 1'b1)
i_q_tmp = (ValidAddress(i_rdaddress_tmp))
? mem_data[i_rdaddress_tmp]
: {lpm_width{1'bx}};
end
//=======
// Sync
//=======
always @(wraddress or i_wraddress_reg)
i_wraddress_tmp = (lpm_wraddress_control == "REGISTERED")
? i_wraddress_reg
: wraddress;
always @(rdaddress or i_rdaddress_reg)
i_rdaddress_tmp = (lpm_rdaddress_control == "REGISTERED")
? i_rdaddress_reg
: rdaddress;
always @(i_wren or i_wren_reg)
i_wren_tmp = (lpm_wraddress_control == "REGISTERED")
? i_wren_reg
: i_wren;
always @(i_rden or i_rden_reg)
i_rden_tmp = (lpm_rdaddress_control == "REGISTERED")
? i_rden_reg
: i_rden;
always @(data or i_data_reg)
i_data_tmp = (lpm_indata == "REGISTERED")
? i_data_reg
: data;
// CONTINOUS ASSIGNMENT
assign q = (lpm_outdata == "REGISTERED") ? i_q_reg : i_q_tmp;
endmodule // lpm_ram_dp
// END OF MODULE
//START_MODULE_NAME------------------------------------------------------------
//
// Module Name : lpm_ram_io
//
// Description : Parameterized RAM with a single I/O port megafunction
//
// Limitation : This megafunction is provided only for backward
// compatibility in Cyclone, Stratix, and Stratix GX designs;
// instead, Altera recommends using the altsyncram
// megafunction
//
// Results expected: Output of RAM content at bi-directional DIO.
//
//END_MODULE_NAME--------------------------------------------------------------
`timescale 1 ps / 1 ps
// MODULE DECLARATION
module lpm_ram_io ( dio, inclock, outclock, we, memenab, outenab, address );
// PARAMETER DECLARATION
parameter lpm_type = "lpm_ram_io";
parameter lpm_width = 1;
parameter lpm_widthad = 1;
parameter lpm_numwords = 1<< lpm_widthad;
parameter lpm_indata = "REGISTERED";
parameter lpm_address_control = "REGISTERED";
parameter lpm_outdata = "REGISTERED";
parameter lpm_file = "UNUSED";
parameter lpm_hint = "UNUSED";
parameter use_eab = "ON";
parameter intended_device_family = "UNUSED";
// INPUT PORT DECLARATION
input [lpm_widthad-1:0] address;
input inclock, outclock, we;
input memenab;
input outenab;
// INPUT/OUTPUT PORT DECLARATION
inout [lpm_width-1:0] dio;
// INTERNAL REGISTERS DECLARATION
reg [lpm_width-1:0] mem_data [lpm_numwords-1:0];
reg [lpm_width-1:0] tmp_io;
reg [lpm_width-1:0] tmp_q;
reg [lpm_width-1:0] pdio;
reg [lpm_widthad-1:0] paddress;
reg [lpm_widthad-1:0] paddress_tmp;
reg pwe;
`ifdef VERILATOR
reg [`LPM_MAX_NAME_SZ*8:1] ram_initf;
`else
reg [8*256:1] ram_initf;
`endif
// INTERNAL WIRE DECLARATION
wire [lpm_width-1:0] read_data;
wire i_inclock;
wire i_outclock;
wire i_memenab;
wire i_outenab;
// LOCAL INTEGER DECLARATION
integer i;
// INTERNAL TRI DECLARATION
tri0 inclock;
tri0 outclock;
tri1 memenab;
tri1 outenab;
// INTERNAL BUF DECLARATION
buf (i_inclock, inclock);
buf (i_outclock, outclock);
buf (i_memenab, memenab);
buf (i_outenab, outenab);
// FUNCTON DECLARATION
function ValidAddress;
input [lpm_widthad-1:0] paddress;
begin
ValidAddress = 1'b0;
if (^paddress === {lpm_widthad{1'bx}})
begin
$display("%t:Error: Invalid address.", $time);
$display("Time: %0t Instance: %m", $time);
$finish;
end
else if (paddress >= lpm_numwords)
begin
$display("%t:Error: Address out of bound on RAM.", $time);
$display("Time: %0t Instance: %m", $time);
$finish;
end
else
ValidAddress = 1'b1;
end
endfunction
// COMPONENT INSTANTIATIONS
LPM_MEMORY_INITIALIZATION mem ();
// INITIAL CONSTRUCT BLOCK
initial
begin
if (lpm_width <= 0)
begin
$display("Error! LPM_WIDTH parameter must be greater than 0.");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if (lpm_widthad <= 0)
begin
$display("Error! LPM_WIDTHAD parameter must be greater than 0.");
$display("Time: %0t Instance: %m", $time);
$finish;
end
// check for number of words out of bound
if ((lpm_numwords > (1 << lpm_widthad))
||(lpm_numwords <= (1 << (lpm_widthad-1))))
begin
$display("Error! The ceiling of log2(LPM_NUMWORDS) must equal to LPM_WIDTHAD.");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if ((lpm_indata != "REGISTERED") && (lpm_indata != "UNREGISTERED"))
begin
$display("Error! LPM_INDATA must be \"REGISTERED\" or \"UNREGISTERED\".");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if ((lpm_address_control != "REGISTERED") && (lpm_address_control != "UNREGISTERED"))
begin
$display("Error! LPM_ADDRESS_CONTROL must be \"REGISTERED\" or \"UNREGISTERED\".");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if ((lpm_outdata != "REGISTERED") && (lpm_outdata != "UNREGISTERED"))
begin
$display("Error! LPM_OUTDATA must be \"REGISTERED\" or \"UNREGISTERED\".");
$display("Time: %0t Instance: %m", $time);
$finish;
end
for (i = 0; i < lpm_numwords; i=i+1)
mem_data[i] = {lpm_width{1'b0}};
// Initialize input/output
pwe = 1'b0;
pdio = {lpm_width{1'b0}};
paddress = {lpm_widthad{1'b0}};
paddress_tmp = {lpm_widthad{1'b0}};
tmp_io = {lpm_width{1'b0}};
tmp_q = {lpm_width{1'b0}};
// load data to the RAM
if (lpm_file != "UNUSED")
begin
mem.convert_to_ver_file(lpm_file, lpm_width, ram_initf);
$readmemh(ram_initf, mem_data);
end
end
// ALWAYS CONSTRUCT BLOCK
always @(dio)
begin
if (lpm_indata == "UNREGISTERED")
pdio <= dio;
end
always @(address)
begin
if (lpm_address_control == "UNREGISTERED")
paddress <= address;
end
always @(we)
begin
if (lpm_address_control == "UNREGISTERED")
pwe <= we;
end
always @(posedge i_inclock)
begin
if (lpm_indata == "REGISTERED")
pdio <= dio;
if (lpm_address_control == "REGISTERED")
begin
paddress <= address;
pwe <= we;
end
end
always @(pdio or paddress or pwe or i_memenab)
begin
if (ValidAddress(paddress))
begin
paddress_tmp <= paddress;
if (lpm_address_control == "UNREGISTERED")
if (pwe && i_memenab)
mem_data[paddress] <= pdio;
end
else
begin
if (lpm_outdata == "UNREGISTERED")
tmp_q <= {lpm_width{1'bx}};
end
end
always @(read_data)
begin
if (lpm_outdata == "UNREGISTERED")
tmp_q <= read_data;
end
always @(negedge i_inclock or pdio)
begin
if (lpm_address_control == "REGISTERED")
if ((use_eab == "ON") || (lpm_hint == "USE_EAB=ON"))
if (pwe && i_memenab && (i_inclock == 1'b0))
mem_data[paddress] = pdio;
end
always @(posedge i_inclock)
begin
if (lpm_address_control == "REGISTERED")
if ((use_eab == "OFF") && pwe && i_memenab)
mem_data[paddress] <= pdio;
end
always @(posedge i_outclock)
begin
if (lpm_outdata == "REGISTERED")
tmp_q <= mem_data[paddress];
end
always @(i_memenab or i_outenab or tmp_q)
begin
if (i_memenab && i_outenab)
tmp_io = tmp_q;
else if ((!i_memenab) || (i_memenab && (!i_outenab)))
tmp_io = {lpm_width{1'bz}};
end
// CONTINOUS ASSIGNMENT
assign dio = tmp_io;
assign read_data = mem_data[paddress_tmp];
endmodule // lpm_ram_io
//START_MODULE_NAME------------------------------------------------------------
//
// Module Name : lpm_rom
//
// Description : Parameterized ROM megafunction. This megafunction is provided
// only for backward compatibility in Cyclone, Stratix, and
// Stratix GX designs; instead, Altera recommends using the
// altsyncram megafunction.
//
// Limitation : This option is available for all Altera devices supported by
// the Quartus II software except MAX 3000 and MAX 7000 devices.
//
// Results expected: Output of memory.
//
//END_MODULE_NAME--------------------------------------------------------------
// BEGINNING OF MODULE
`timescale 1 ps / 1 ps
// MODULE DECLARATION
module lpm_rom (
address, // Address input to the memory. (Required)
inclock, // Clock for input registers.
outclock, // Clock for output registers.
memenab, // Memory enable input.
q // Output of memory. (Required)
);
// GLOBAL PARAMETER DECLARATION
parameter lpm_width = 1; // Width of the q[] port. (Required)
parameter lpm_widthad = 1; // Width of the address[] port. (Required)
parameter lpm_numwords = 0; // Number of words stored in memory.
parameter lpm_address_control = "REGISTERED"; // Indicates whether the address port is registered.
parameter lpm_outdata = "REGISTERED"; // Indicates whether the q and eq ports are registered.
parameter lpm_file = ""; // Name of the memory file containing ROM initialization data
parameter intended_device_family = "Stratix";
parameter lpm_type = "lpm_rom";
parameter lpm_hint = "UNUSED";
// LOCAL_PARAMETERS_BEGIN
parameter NUM_WORDS = (lpm_numwords == 0) ? (1 << lpm_widthad) : lpm_numwords;
// LOCAL_PARAMETERS_END
// INPUT PORT DECLARATION
input [lpm_widthad-1:0] address;
input inclock;
input outclock;
input memenab;
// OUTPUT PORT DECLARATION
output [lpm_width-1:0] q;
// INTERNAL REGISTER/SIGNAL DECLARATION
reg [lpm_width-1:0] mem_data [0:NUM_WORDS-1];
reg [lpm_widthad-1:0] address_reg;
reg [lpm_width-1:0] tmp_q_reg;
`ifdef VERILATOR
reg [`LPM_MAX_NAME_SZ*8:1] rom_initf;
`else
reg [8*256:1] rom_initf;
`endif
// INTERNAL WIRE DECLARATION
wire [lpm_widthad-1:0] w_address;
wire [lpm_width-1:0] w_read_data;
wire i_inclock;
wire i_outclock;
wire i_memenab;
// LOCAL INTEGER DECLARATION
integer i;
// INTERNAL TRI DECLARATION
tri0 inclock;
tri0 outclock;
tri1 memenab;
buf (i_inclock, inclock);
buf (i_outclock, outclock);
buf (i_memenab, memenab);
// COMPONENT INSTANTIATIONS
LPM_DEVICE_FAMILIES dev ();
LPM_MEMORY_INITIALIZATION mem ();
// FUNCTON DECLARATION
// Check the validity of the address.
function ValidAddress;
input [lpm_widthad-1:0] address;
begin
ValidAddress = 1'b0;
if (^address == {lpm_widthad{1'bx}})
begin
$display("%d:Error: Invalid address.", $time);
$display("Time: %0t Instance: %m", $time);
$finish;
end
else if (address >= NUM_WORDS)
begin
$display("%d:Error: Address out of bound on ROM.", $time);
$display("Time: %0t Instance: %m", $time);
$finish;
end
else
ValidAddress = 1'b1;
end
endfunction
// INITIAL CONSTRUCT BLOCK
initial
begin
// Initialize output
tmp_q_reg = {lpm_width{1'b0}};
address_reg = {lpm_widthad{1'b0}};
if (lpm_width <= 0)
begin
$display("Error! LPM_WIDTH parameter must be greater than 0.");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if (lpm_widthad <= 0)
begin
$display("Error! LPM_WIDTHAD parameter must be greater than 0.");
$display("Time: %0t Instance: %m", $time);
$finish;
end
// check for number of words out of bound
if ((NUM_WORDS > (1 << lpm_widthad)) ||
(NUM_WORDS <= (1 << (lpm_widthad-1))))
begin
$display("Error! The ceiling of log2(LPM_NUMWORDS) must equal to LPM_WIDTHAD.");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if ((lpm_address_control != "REGISTERED") &&
(lpm_address_control != "UNREGISTERED"))
begin
$display("Error! LPM_ADDRESS_CONTROL must be \"REGISTERED\" or \"UNREGISTERED\".");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if ((lpm_outdata != "REGISTERED") && (lpm_outdata != "UNREGISTERED"))
begin
$display("Error! LPM_OUTDATA must be \"REGISTERED\" or \"UNREGISTERED\".");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if (dev.IS_VALID_FAMILY(intended_device_family) == 0)
begin
$display ("Error! Unknown INTENDED_DEVICE_FAMILY=%s.", intended_device_family);
$display("Time: %0t Instance: %m", $time);
$finish;
end
if (dev.FEATURE_FAMILY_MAX(intended_device_family) == 1)
begin
$display ("Error! LPM_ROM megafunction does not support %s devices.", intended_device_family);
$display("Time: %0t Instance: %m", $time);
$finish;
end
for (i = 0; i < NUM_WORDS; i=i+1)
mem_data[i] = {lpm_width{1'b0}};
// load data to the ROM
if ((lpm_file == "") || (lpm_file == "UNUSED"))
begin
$display("Warning: LPM_ROM must have data file for initialization.\n");
$display ("Time: %0t Instance: %m", $time);
end
else
begin
mem.convert_to_ver_file(lpm_file, lpm_width, rom_initf);
$readmemh(rom_initf, mem_data);
end
end
always @(posedge i_inclock)
begin
if (lpm_address_control == "REGISTERED")
address_reg <= address; // address port is registered
end
always @(w_address or w_read_data)
begin
if (ValidAddress(w_address))
begin
if (lpm_outdata == "UNREGISTERED")
// Load the output register with the contents of the memory location
// pointed to by address[].
tmp_q_reg <= w_read_data;
end
else
begin
if (lpm_outdata == "UNREGISTERED")
tmp_q_reg <= {lpm_width{1'bx}};
end
end
always @(posedge i_outclock)
begin
if (lpm_outdata == "REGISTERED")
begin
if (ValidAddress(w_address))
tmp_q_reg <= w_read_data;
else
tmp_q_reg <= {lpm_width{1'bx}};
end
end
// CONTINOUS ASSIGNMENT
assign w_address = (lpm_address_control == "REGISTERED") ? address_reg : address;
assign w_read_data = mem_data[w_address];
assign q = (i_memenab) ? tmp_q_reg : {lpm_width{1'bz}};
endmodule // lpm_rom
// END OF MODULE
//START_MODULE_NAME------------------------------------------------------------
//
// Module Name : lpm_fifo
//
// Description :
//
// Limitation :
//
// Results expected:
//
//END_MODULE_NAME--------------------------------------------------------------
`timescale 1 ps / 1 ps
module lpm_fifo ( data,
clock,
wrreq,
rdreq,
aclr,
sclr,
q,
usedw,
full,
empty );
// GLOBAL PARAMETER DECLARATION
parameter lpm_width = 1;
parameter lpm_widthu = 1;
parameter lpm_numwords = 2;
parameter lpm_showahead = "OFF";
parameter lpm_type = "lpm_fifo";
parameter lpm_hint = "";
// INPUT PORT DECLARATION
input [lpm_width-1:0] data;
input clock;
input wrreq;
input rdreq;
input aclr;
input sclr;
// OUTPUT PORT DECLARATION
output [lpm_width-1:0] q;
output [lpm_widthu-1:0] usedw;
output full;
output empty;
// INTERNAL REGISTERS DECLARATION
reg [lpm_width-1:0] mem_data [(1<<lpm_widthu):0];
reg [lpm_width-1:0] tmp_data;
reg [lpm_widthu-1:0] count_id;
reg [lpm_widthu-1:0] read_id;
reg [lpm_widthu-1:0] write_id;
reg write_flag;
reg full_flag;
reg empty_flag;
reg [lpm_width-1:0] tmp_q;
reg [8*5:1] overflow_checking;
reg [8*5:1] underflow_checking;
reg [8*20:1] allow_rwcycle_when_full;
reg [8*20:1] intended_device_family;
// INTERNAL WIRE DECLARATION
wire valid_rreq;
wire valid_wreq;
// INTERNAL TRI DECLARATION
tri0 aclr;
// LOCAL INTEGER DECLARATION
integer i;
// COMPONENT INSTANTIATIONS
LPM_DEVICE_FAMILIES dev ();
LPM_HINT_EVALUATION eva();
// INITIAL CONSTRUCT BLOCK
initial
begin
if (lpm_width <= 0)
begin
$display ("Error! LPM_WIDTH must be greater than 0.");
$display("Time: %0t Instance: %m", $time);
$stop;
end
if (lpm_numwords <= 1)
begin
$display ("Error! LPM_NUMWORDS must be greater than or equal to 2.");
$display("Time: %0t Instance: %m", $time);
$stop;
end
if ((lpm_widthu !=1) && (lpm_numwords > (1 << lpm_widthu)))
begin
$display ("Error! LPM_NUMWORDS must equal to the ceiling of log2(LPM_WIDTHU).");
$display("Time: %0t Instance: %m", $time);
$stop;
end
if (lpm_numwords <= (1 << (lpm_widthu - 1)))
begin
$display ("Error! LPM_WIDTHU is too big for the specified LPM_NUMWORDS.");
$display("Time: %0t Instance: %m", $time);
$stop;
end
overflow_checking = eva.GET_PARAMETER_VALUE(lpm_hint, "OVERFLOW_CHECKING");
if(overflow_checking == "")
overflow_checking = "ON";
else if ((overflow_checking != "ON") && (overflow_checking != "OFF"))
begin
$display ("Error! OVERFLOW_CHECKING must equal to either 'ON' or 'OFF'");
$display("Time: %0t Instance: %m", $time);
$stop;
end
underflow_checking = eva.GET_PARAMETER_VALUE(lpm_hint, "UNDERFLOW_CHECKING");
if(underflow_checking == "")
underflow_checking = "ON";
else if ((underflow_checking != "ON") && (underflow_checking != "OFF"))
begin
$display ("Error! UNDERFLOW_CHECKING must equal to either 'ON' or 'OFF'");
$display("Time: %0t Instance: %m", $time);
$stop;
end
allow_rwcycle_when_full = eva.GET_PARAMETER_VALUE(lpm_hint, "ALLOW_RWCYCLE_WHEN_FULL");
if (allow_rwcycle_when_full == "")
allow_rwcycle_when_full = "OFF";
else if ((allow_rwcycle_when_full != "ON") && (allow_rwcycle_when_full != "OFF"))
begin
$display ("Error! ALLOW_RWCYCLE_WHEN_FULL must equal to either 'ON' or 'OFF'");
$display("Time: %0t Instance: %m", $time);
$stop;
end
intended_device_family = eva.GET_PARAMETER_VALUE(lpm_hint, "INTENDED_DEVICE_FAMILY");
if (intended_device_family == "")
intended_device_family = "Stratix II";
else if (dev.IS_VALID_FAMILY(intended_device_family) == 0)
begin
$display ("Error! Unknown INTENDED_DEVICE_FAMILY=%s.", intended_device_family);
$display("Time: %0t Instance: %m", $time);
$stop;
end
for (i = 0; i < (1<<lpm_widthu); i = i + 1)
begin
if (dev.FEATURE_FAMILY_BASE_STRATIX(intended_device_family) ||
dev.FEATURE_FAMILY_BASE_CYCLONE(intended_device_family))
mem_data[i] <= {lpm_width{1'bx}};
else
mem_data[i] <= {lpm_width{1'b0}};
end
tmp_data <= 0;
if (dev.FEATURE_FAMILY_BASE_STRATIX(intended_device_family) ||
dev.FEATURE_FAMILY_BASE_CYCLONE(intended_device_family))
tmp_q <= {lpm_width{1'bx}};
else
tmp_q <= {lpm_width{1'b0}};
write_flag <= 1'b0;
count_id <= 0;
read_id <= 0;
write_id <= 0;
full_flag <= 1'b0;
empty_flag <= 1'b1;
end
// ALWAYS CONSTRUCT BLOCK
always @(posedge clock or posedge aclr)
begin
if (aclr)
begin
if (!(dev.FEATURE_FAMILY_BASE_STRATIX(intended_device_family) ||
dev.FEATURE_FAMILY_BASE_CYCLONE(intended_device_family)))
begin
if (lpm_showahead == "ON")
tmp_q <= mem_data[0];
else
tmp_q <= {lpm_width{1'b0}};
end
read_id <= 0;
count_id <= 0;
full_flag <= 1'b0;
empty_flag <= 1'b1;
if (valid_wreq && (dev.FEATURE_FAMILY_BASE_STRATIX(intended_device_family) ||
dev.FEATURE_FAMILY_BASE_CYCLONE(intended_device_family)))
begin
tmp_data <= data;
write_flag <= 1'b1;
end
else
write_id <= 0;
end
else if (sclr)
begin
if ((lpm_showahead == "ON") || (dev.FEATURE_FAMILY_BASE_STRATIX(intended_device_family) ||
dev.FEATURE_FAMILY_BASE_CYCLONE(intended_device_family)))
tmp_q <= mem_data[0];
else
tmp_q <= mem_data[read_id];
read_id <= 0;
count_id <= 0;
full_flag <= 1'b0;
empty_flag <= 1'b1;
if (valid_wreq)
begin
tmp_data <= data;
write_flag <= 1'b1;
end
else
write_id <= 0;
end
else
begin
// Both WRITE and READ operations
if (valid_wreq && valid_rreq)
begin
tmp_data <= data;
write_flag <= 1'b1;
empty_flag <= 1'b0;
if (allow_rwcycle_when_full == "OFF")
begin
full_flag <= 1'b0;
end
if (read_id >= ((1 << lpm_widthu) - 1))
begin
if (lpm_showahead == "ON")
tmp_q <= mem_data[0];
else
tmp_q <= mem_data[read_id];
read_id <= 0;
end
else
begin
if (lpm_showahead == "ON")
tmp_q <= mem_data[read_id + 1];
else
tmp_q <= mem_data[read_id];
read_id <= read_id + 1;
end
end
// WRITE operation only
else if (valid_wreq)
begin
tmp_data <= data;
empty_flag <= 1'b0;
write_flag <= 1'b1;
if (count_id >= (1 << lpm_widthu) - 1)
count_id <= 0;
else
count_id <= count_id + 1;
if ((count_id == lpm_numwords - 1) && (empty_flag == 1'b0))
full_flag <= 1'b1;
if (lpm_showahead == "ON")
tmp_q <= mem_data[read_id];
end
// READ operation only
else if (valid_rreq)
begin
full_flag <= 1'b0;
if (count_id <= 0)
count_id <= {lpm_widthu{1'b1}};
else
count_id <= count_id - 1;
if ((count_id == 1) && (full_flag == 1'b0))
empty_flag <= 1'b1;
if (read_id >= ((1<<lpm_widthu) - 1))
begin
if (lpm_showahead == "ON")
tmp_q <= mem_data[0];
else
tmp_q <= mem_data[read_id];
read_id <= 0;
end
else
begin
if (lpm_showahead == "ON")
tmp_q <= mem_data[read_id + 1];
else
tmp_q <= mem_data[read_id];
read_id <= read_id + 1;
end
end // if Both WRITE and READ operations
end // if aclr
end // @(posedge clock)
always @(negedge clock)
begin
if (write_flag)
begin
write_flag <= 1'b0;
mem_data[write_id] <= tmp_data;
if (sclr || aclr || (write_id >= ((1 << lpm_widthu) - 1)))
write_id <= 0;
else
write_id <= write_id + 1;
end
if ((lpm_showahead == "ON") && ($time > 0))
tmp_q <= ((write_flag == 1'b1) && (write_id == read_id)) ?
tmp_data : mem_data[read_id];
end // @(negedge clock)
// CONTINOUS ASSIGNMENT
assign valid_rreq = (underflow_checking == "OFF") ? rdreq : rdreq && ~empty_flag;
assign valid_wreq = (overflow_checking == "OFF") ? wrreq :
(allow_rwcycle_when_full == "ON") ? wrreq && (!full_flag || rdreq) :
wrreq && !full_flag;
assign q = tmp_q;
assign full = full_flag;
assign empty = empty_flag;
assign usedw = count_id;
endmodule // lpm_fifo
// END OF MODULE
//START_MODULE_NAME------------------------------------------------------------
//
// Module Name : lpm_fifo_dc_dffpipe
//
// Description : Dual Clocks FIFO
//
// Limitation :
//
// Results expected:
//
//END_MODULE_NAME--------------------------------------------------------------
// BEGINNING OF MODULE
`timescale 1 ps / 1 ps
// MODULE DECLARATION
module lpm_fifo_dc_dffpipe (d,
clock,
aclr,
q);
// GLOBAL PARAMETER DECLARATION
parameter lpm_delay = 1;
parameter lpm_width = 64;
// INPUT PORT DECLARATION
input [lpm_width-1:0] d;
input clock;
input aclr;
// OUTPUT PORT DECLARATION
output [lpm_width-1:0] q;
// INTERNAL REGISTERS DECLARATION
reg [lpm_width-1:0] dffpipe [lpm_delay:0];
reg [lpm_width-1:0] q;
// LOCAL INTEGER DECLARATION
integer delay;
integer i;
// INITIAL CONSTRUCT BLOCK
initial
begin
delay <= lpm_delay - 1;
for (i = 0; i <= lpm_delay; i = i + 1)
dffpipe[i] <= 0;
q <= 0;
end
// ALWAYS CONSTRUCT BLOCK
always @(posedge aclr or posedge clock)
begin
if (aclr)
begin
for (i = 0; i <= lpm_delay; i = i + 1)
dffpipe[i] <= 0;
q <= 0;
end
else if (clock)
begin
if ((lpm_delay > 0) && ($time > 0))
begin
`ifdef VERILATOR
if (lpm_delay > 0)
`else
if (delay > 0)
`endif
begin
`ifdef VERILATOR
for (i = lpm_delay-1; i > 0; i = i - 1)
`else
for (i = delay; i > 0; i = i - 1)
`endif
dffpipe[i] <= dffpipe[i - 1];
q <= dffpipe[delay - 1];
end
else
q <= d;
dffpipe[0] <= d;
end
end
end // @(posedge aclr or posedge clock)
always @(d)
begin
if (lpm_delay == 0)
q <= d;
end // @(d)
endmodule // lpm_fifo_dc_dffpipe
// END OF MODULE
//START_MODULE_NAME------------------------------------------------------------
//
// Module Name : lpm_fifo_dc_fefifo
//
// Description : Dual Clock FIFO
//
// Limitation :
//
// Results expected:
//
//END_MODULE_NAME--------------------------------------------------------------
// BEGINNING OF MODULE
`timescale 1 ps / 1 ps
// MODULE DECLARATION
module lpm_fifo_dc_fefifo ( usedw_in,
wreq,
rreq,
clock,
aclr,
empty,
full);
// GLOBAL PARAMETER DECLARATION
parameter lpm_widthad = 1;
parameter lpm_numwords = 1;
parameter underflow_checking = "ON";
parameter overflow_checking = "ON";
parameter lpm_mode = "READ";
parameter lpm_hint = "";
// INPUT PORT DECLARATION
input [lpm_widthad-1:0] usedw_in;
input wreq;
input rreq;
input clock;
input aclr;
// OUTPUT PORT DECLARATION
output empty;
output full;
// INTERNAL REGISTERS DECLARATION
reg [1:0] sm_empty;
reg lrreq;
reg i_empty;
reg i_full;
reg [8*5:1] i_overflow_checking;
reg [8*5:1] i_underflow_checking;
// LOCAL INTEGER DECLARATION
integer almostfull;
// COMPONENT INSTANTIATIONS
LPM_HINT_EVALUATION eva();
// INITIAL CONSTRUCT BLOCK
initial
begin
if ((lpm_mode != "READ") && (lpm_mode != "WRITE"))
begin
$display ("Error! LPM_MODE must be READ or WRITE.");
$display("Time: %0t Instance: %m", $time);
$stop;
end
i_overflow_checking = eva.GET_PARAMETER_VALUE(lpm_hint, "OVERFLOW_CHECKING");
if (i_overflow_checking == "")
begin
if ((overflow_checking != "ON") && (overflow_checking != "OFF"))
begin
$display ("Error! OVERFLOW_CHECKING must equal to either 'ON' or 'OFF'");
$display("Time: %0t Instance: %m", $time);
$stop;
end
else
i_overflow_checking = overflow_checking;
end
else if ((i_overflow_checking != "ON") && (i_overflow_checking != "OFF"))
begin
$display ("Error! OVERFLOW_CHECKING must equal to either 'ON' or 'OFF'");
$display("Time: %0t Instance: %m", $time);
$stop;
end
i_underflow_checking = eva.GET_PARAMETER_VALUE(lpm_hint, "UNDERFLOW_CHECKING");
if(i_underflow_checking == "")
begin
if ((underflow_checking != "ON") && (underflow_checking != "OFF"))
begin
$display ("Error! UNDERFLOW_CHECKING must equal to either 'ON' or 'OFF'");
$display("Time: %0t Instance: %m", $time);
$stop;
end
else
i_underflow_checking = underflow_checking;
end
else if ((i_underflow_checking != "ON") && (i_underflow_checking != "OFF"))
begin
$display ("Error! UNDERFLOW_CHECKING must equal to either 'ON' or 'OFF'");
$display("Time: %0t Instance: %m", $time);
$stop;
end
sm_empty <= 2'b00;
i_empty <= 1'b1;
i_full <= 1'b0;
lrreq <= 1'b0;
if (lpm_numwords >= 3)
almostfull <= lpm_numwords - 3;
else
almostfull <= 0;
end
// ALWAYS CONSTRUCT BLOCK
always @(posedge aclr)
begin
sm_empty <= 2'b00;
i_empty <= 1'b1;
i_full <= 1'b0;
lrreq <= 1'b0;
end // @(posedge aclr)
always @(posedge clock)
begin
if (i_underflow_checking == "OFF")
lrreq <= rreq;
else
lrreq <= rreq && ~i_empty;
if (~aclr && ($time > 0))
begin
if (lpm_mode == "READ")
begin
// verilator lint_off CASEX
casex (sm_empty)
// verilator lint_on CASEX
// state_empty
2'b00:
if (usedw_in != 0)
sm_empty <= 2'b01;
// state_non_empty
// verilator lint_off CMPCONST
2'b01:
if (rreq && (((usedw_in == 1) && !lrreq) || ((usedw_in == 2) && lrreq)))
sm_empty <= 2'b10;
// state_emptywait
2'b10:
if (usedw_in > 1)
sm_empty <= 2'b01;
else
sm_empty <= 2'b00;
// verilator lint_on CMPCONST
default:
begin
$display ("Error! Invalid sm_empty state in read mode.");
$display("Time: %0t Instance: %m", $time);
end
endcase
end // if (lpm_mode == "READ")
else if (lpm_mode == "WRITE")
begin
// verilator lint_off CASEX
casex (sm_empty)
// verilator lint_on CASEX
// state_empty
2'b00:
if (wreq)
sm_empty <= 2'b01;
// state_one
2'b01:
if (!wreq)
sm_empty <= 2'b11;
// state_non_empty
2'b11:
if (wreq)
sm_empty <= 2'b01;
else if (usedw_in == 0)
sm_empty <= 2'b00;
default:
begin
$display ("Error! Invalid sm_empty state in write mode.");
$display("Time: %0t Instance: %m", $time);
end
endcase
end // if (lpm_mode == "WRITE")
if (~aclr && (usedw_in >= almostfull) && ($time > 0))
i_full <= 1'b1;
else
i_full <= 1'b0;
end // if (~aclr && $time > 0)
end // @(posedge clock)
always @(sm_empty)
begin
i_empty <= !sm_empty[0];
end
// @(sm_empty)
// CONTINOUS ASSIGNMENT
assign empty = i_empty;
assign full = i_full;
endmodule // lpm_fifo_dc_fefifo
// END OF MODULE
//START_MODULE_NAME------------------------------------------------------------
//
// Module Name : lpm_fifo_dc_async
//
// Description : Asynchronous Dual Clocks FIFO
//
// Limitation :
//
// Results expected:
//
//END_MODULE_NAME--------------------------------------------------------------
// BEGINNING OF MODULE
`timescale 1 ps / 1 ps
// MODULE DECLARATION
module lpm_fifo_dc_async ( data,
rdclk,
wrclk,
aclr,
rdreq,
wrreq,
rdfull,
wrfull,
rdempty,
wrempty,
rdusedw,
wrusedw,
q);
// GLOBAL PARAMETER DECLARATION
parameter lpm_width = 1;
parameter lpm_widthu = 1;
parameter lpm_numwords = 2;
parameter delay_rdusedw = 1;
parameter delay_wrusedw = 1;
parameter rdsync_delaypipe = 3;
parameter wrsync_delaypipe = 3;
parameter lpm_showahead = "OFF";
parameter underflow_checking = "ON";
parameter overflow_checking = "ON";
parameter lpm_hint = "INTENDED_DEVICE_FAMILY=Stratix";
// INPUT PORT DECLARATION
input [lpm_width-1:0] data;
input rdclk;
input wrclk;
input aclr;
input wrreq;
input rdreq;
// OUTPUT PORT DECLARATION
output rdfull;
output wrfull;
output rdempty;
output wrempty;
output [lpm_widthu-1:0] rdusedw;
output [lpm_widthu-1:0] wrusedw;
output [lpm_width-1:0] q;
// INTERNAL REGISTERS DECLARATION
reg [lpm_width-1:0] mem_data [(1<<lpm_widthu)-1:0];
reg [lpm_width-1:0] i_data_tmp;
reg [lpm_widthu-1:0] i_rdptr;
reg [lpm_widthu-1:0] i_wrptr;
reg [lpm_widthu-1:0] i_wrptr_tmp;
reg i_rdenclock;
reg i_wren_tmp;
reg [lpm_widthu-1:0] i_wr_udwn;
reg [lpm_widthu-1:0] i_rd_udwn;
reg i_showahead_flag;
reg i_showahead_flag1;
reg [lpm_widthu:0] i_rdusedw;
reg [lpm_widthu-1:0] i_wrusedw;
reg [lpm_width-1:0] i_q_tmp;
reg [8*5:1] i_overflow_checking;
reg [8*5:1] i_underflow_checking;
reg [8*10:1] use_eab;
reg [8*20:1] intended_device_family;
// INTERNAL WIRE DECLARATION
wire w_rden;
wire w_wren;
wire w_rdempty;
wire w_wrempty;
wire w_rdfull;
wire w_wrfull;
wire [lpm_widthu-1:0] w_rdptrrg;
wire [lpm_widthu-1:0] w_wrdelaycycle;
wire [lpm_widthu-1:0] w_ws_nbrp;
wire [lpm_widthu-1:0] w_rs_nbwp;
wire [lpm_widthu-1:0] w_ws_dbrp;
wire [lpm_widthu-1:0] w_rs_dbwp;
wire [lpm_widthu-1:0] w_rd_dbuw;
wire [lpm_widthu-1:0] w_wr_dbuw;
wire [lpm_widthu-1:0] w_rdusedw;
wire [lpm_widthu-1:0] w_wrusedw;
// INTERNAL TRI DECLARATION
tri0 aclr;
// LOCAL INTEGER DECLARATION
integer i;
// COMPONENT INSTANTIATIONS
LPM_DEVICE_FAMILIES dev ();
LPM_HINT_EVALUATION eva();
// INITIAL CONSTRUCT BLOCK
initial
begin
if((lpm_showahead != "ON") && (lpm_showahead != "OFF"))
begin
$display ("Error! lpm_showahead must be ON or OFF.");
$display("Time: %0t Instance: %m", $time);
$stop;
end
i_overflow_checking = eva.GET_PARAMETER_VALUE(lpm_hint, "OVERFLOW_CHECKING");
if (i_overflow_checking == "")
begin
if ((overflow_checking != "ON") && (overflow_checking != "OFF"))
begin
$display ("Error! OVERFLOW_CHECKING must equal to either 'ON' or 'OFF'");
$display("Time: %0t Instance: %m", $time);
$stop;
end
else
i_overflow_checking = overflow_checking;
end
else if ((i_overflow_checking != "ON") && (i_overflow_checking != "OFF"))
begin
$display ("Error! OVERFLOW_CHECKING must equal to either 'ON' or 'OFF'");
$display("Time: %0t Instance: %m", $time);
$stop;
end
i_underflow_checking = eva.GET_PARAMETER_VALUE(lpm_hint, "UNDERFLOW_CHECKING");
if(i_underflow_checking == "")
begin
if ((underflow_checking != "ON") && (underflow_checking != "OFF"))
begin
$display ("Error! UNDERFLOW_CHECKING must equal to either 'ON' or 'OFF'");
$display("Time: %0t Instance: %m", $time);
$stop;
end
else
i_underflow_checking = underflow_checking;
end
else if ((i_underflow_checking != "ON") && (i_underflow_checking != "OFF"))
begin
$display ("Error! UNDERFLOW_CHECKING must equal to either 'ON' or 'OFF'");
$display("Time: %0t Instance: %m", $time);
$stop;
end
use_eab = eva.GET_PARAMETER_VALUE(lpm_hint, "USE_EAB");
if(use_eab == "")
use_eab = "ON";
else if ((use_eab != "ON") && (use_eab != "OFF"))
begin
$display ("Error! USE_EAB must equal to either 'ON' or 'OFF'");
$display("Time: %0t Instance: %m", $time);
$stop;
end
intended_device_family = eva.GET_PARAMETER_VALUE(lpm_hint, "INTENDED_DEVICE_FAMILY");
if (intended_device_family == "")
intended_device_family = "Stratix II";
else if (dev.IS_VALID_FAMILY(intended_device_family) == 0)
begin
$display ("Error! Unknown INTENDED_DEVICE_FAMILY=%s.", intended_device_family);
$display("Time: %0t Instance: %m", $time);
$stop;
end
for (i = 0; i < (1 << lpm_widthu); i = i + 1)
mem_data[i] <= 0;
i_data_tmp <= 0;
i_rdptr <= 0;
i_wrptr <= 0;
i_wrptr_tmp <= 0;
i_wren_tmp <= 0;
i_wr_udwn <= 0;
i_rd_udwn <= 0;
i_rdusedw <= 0;
i_wrusedw <= 0;
i_q_tmp <= 0;
end
// COMPONENT INSTANTIATIONS
// Delays & DFF Pipes
lpm_fifo_dc_dffpipe DP_RDPTR_D (
.d (i_rdptr),
.clock (i_rdenclock),
.aclr (aclr),
.q (w_rdptrrg));
lpm_fifo_dc_dffpipe DP_WRPTR_D (
.d (i_wrptr),
.clock (wrclk),
.aclr (aclr),
.q (w_wrdelaycycle));
defparam
DP_RDPTR_D.lpm_delay = 0,
DP_RDPTR_D.lpm_width = lpm_widthu,
DP_WRPTR_D.lpm_delay = 1,
DP_WRPTR_D.lpm_width = lpm_widthu;
lpm_fifo_dc_dffpipe DP_WS_NBRP (
.d (w_rdptrrg),
.clock (wrclk),
.aclr (aclr),
.q (w_ws_nbrp));
lpm_fifo_dc_dffpipe DP_RS_NBWP (
.d (w_wrdelaycycle),
.clock (rdclk),
.aclr (aclr),
.q (w_rs_nbwp));
lpm_fifo_dc_dffpipe DP_WS_DBRP (
.d (w_ws_nbrp),
.clock (wrclk),
.aclr (aclr),
.q (w_ws_dbrp));
lpm_fifo_dc_dffpipe DP_RS_DBWP (
.d (w_rs_nbwp),
.clock (rdclk),
.aclr (aclr),
.q (w_rs_dbwp));
defparam
DP_WS_NBRP.lpm_delay = wrsync_delaypipe,
DP_WS_NBRP.lpm_width = lpm_widthu,
DP_RS_NBWP.lpm_delay = rdsync_delaypipe,
DP_RS_NBWP.lpm_width = lpm_widthu,
DP_WS_DBRP.lpm_delay = 1, // gray_delaypipe
DP_WS_DBRP.lpm_width = lpm_widthu,
DP_RS_DBWP.lpm_delay = 1, // gray_delaypipe
DP_RS_DBWP.lpm_width = lpm_widthu;
lpm_fifo_dc_dffpipe DP_WRUSEDW (
.d (i_wr_udwn),
.clock (wrclk),
.aclr (aclr),
.q (w_wrusedw));
lpm_fifo_dc_dffpipe DP_RDUSEDW (
.d (i_rd_udwn),
.clock (rdclk),
.aclr (aclr),
.q (w_rdusedw));
lpm_fifo_dc_dffpipe DP_WR_DBUW (
.d (i_wr_udwn),
.clock (wrclk),
.aclr (aclr),
.q (w_wr_dbuw));
lpm_fifo_dc_dffpipe DP_RD_DBUW (
.d (i_rd_udwn),
.clock (rdclk),
.aclr (aclr),
.q (w_rd_dbuw));
defparam
DP_WRUSEDW.lpm_delay = delay_wrusedw,
DP_WRUSEDW.lpm_width = lpm_widthu,
DP_RDUSEDW.lpm_delay = delay_rdusedw,
DP_RDUSEDW.lpm_width = lpm_widthu,
DP_WR_DBUW.lpm_delay = 1, // wrusedw_delaypipe
DP_WR_DBUW.lpm_width = lpm_widthu,
DP_RD_DBUW.lpm_delay = 1, // rdusedw_delaypipe
DP_RD_DBUW.lpm_width = lpm_widthu;
// Empty/Full
lpm_fifo_dc_fefifo WR_FE (
.usedw_in (w_wr_dbuw),
.wreq (wrreq),
.rreq (rdreq),
.clock (wrclk),
.aclr (aclr),
.empty (w_wrempty),
.full (w_wrfull));
lpm_fifo_dc_fefifo RD_FE (
.usedw_in (w_rd_dbuw),
.rreq (rdreq),
.wreq(wrreq),
.clock (rdclk),
.aclr (aclr),
.empty (w_rdempty),
.full (w_rdfull));
defparam
WR_FE.lpm_widthad = lpm_widthu,
WR_FE.lpm_numwords = lpm_numwords,
WR_FE.underflow_checking = underflow_checking,
WR_FE.overflow_checking = overflow_checking,
WR_FE.lpm_mode = "WRITE",
WR_FE.lpm_hint = lpm_hint,
RD_FE.lpm_widthad = lpm_widthu,
RD_FE.lpm_numwords = lpm_numwords,
RD_FE.underflow_checking = underflow_checking,
RD_FE.overflow_checking = overflow_checking,
RD_FE.lpm_mode = "READ",
RD_FE.lpm_hint = lpm_hint;
// ALWAYS CONSTRUCT BLOCK
always @(posedge aclr)
begin
i_rdptr <= 0;
i_wrptr <= 0;
if (!(dev.FEATURE_FAMILY_BASE_STRATIX(intended_device_family) ||
dev.FEATURE_FAMILY_BASE_CYCLONE(intended_device_family)) ||
(use_eab == "OFF"))
if (lpm_showahead == "ON")
i_q_tmp <= mem_data[0];
else
i_q_tmp <= 0;
end // @(posedge aclr)
// FIFOram
always @(posedge wrclk)
begin
if (aclr && (!(dev.FEATURE_FAMILY_BASE_STRATIX(intended_device_family) ||
dev.FEATURE_FAMILY_BASE_CYCLONE(intended_device_family)) ||
(use_eab == "OFF")))
begin
i_data_tmp <= 0;
i_wrptr_tmp <= 0;
i_wren_tmp <= 0;
end
else if (wrclk && ($time > 0))
begin
i_data_tmp <= data;
i_wrptr_tmp <= i_wrptr;
i_wren_tmp <= w_wren;
if (w_wren)
begin
if (~aclr && ((i_wrptr < (1<<lpm_widthu)-1) || (i_overflow_checking == "OFF")))
i_wrptr <= i_wrptr + 1;
else
i_wrptr <= 0;
if (use_eab == "OFF")
begin
mem_data[i_wrptr] <= data;
if (lpm_showahead == "ON")
i_showahead_flag1 <= 1'b1;
end
end
end
end // @(posedge wrclk)
always @(negedge wrclk)
begin
if ((~wrclk && (use_eab == "ON")) && ($time > 0))
begin
if (i_wren_tmp)
begin
mem_data[i_wrptr_tmp] <= i_data_tmp;
end
if (lpm_showahead == "ON")
i_showahead_flag1 <= 1'b1;
end
end // @(negedge wrclk)
always @(posedge rdclk)
begin
if (aclr && (!(dev.FEATURE_FAMILY_BASE_STRATIX(intended_device_family) ||
dev.FEATURE_FAMILY_BASE_CYCLONE(intended_device_family)) ||
(use_eab == "OFF")))
begin
if (lpm_showahead == "ON")
i_q_tmp <= mem_data[0];
else
i_q_tmp <= 0;
end
else if (rdclk && w_rden && ($time > 0))
begin
if (~aclr && ((i_rdptr < (1<<lpm_widthu)-1) || (i_underflow_checking == "OFF")))
i_rdptr <= i_rdptr + 1;
else
i_rdptr <= 0;
if (lpm_showahead == "ON")
i_showahead_flag1 <= 1'b1;
else
i_q_tmp <= mem_data[i_rdptr];
end
end // @(rdclk)
always @(posedge i_showahead_flag)
begin
i_q_tmp <= mem_data[i_rdptr];
i_showahead_flag1 <= 1'b0;
end // @(posedge i_showahead_flag)
always @(i_showahead_flag1)
begin
i_showahead_flag <= i_showahead_flag1;
end // @(i_showahead_flag1)
// Delays & DFF Pipes
always @(negedge rdclk)
begin
i_rdenclock <= 0;
end // @(negedge rdclk)
always @(posedge rdclk)
begin
if (w_rden)
i_rdenclock <= 1;
end // @(posedge rdclk)
always @(i_wrptr or w_ws_dbrp)
begin
i_wr_udwn <= i_wrptr - w_ws_dbrp;
end // @(i_wrptr or w_ws_dbrp)
always @(i_rdptr or w_rs_dbwp)
begin
i_rd_udwn <= w_rs_dbwp - i_rdptr;
end // @(i_rdptr or w_rs_dbwp)
// CONTINOUS ASSIGNMENT
assign w_rden = (i_underflow_checking == "OFF") ? rdreq : rdreq && !w_rdempty;
assign w_wren = (i_overflow_checking == "OFF") ? wrreq : wrreq && !w_wrfull;
assign q = i_q_tmp;
assign wrfull = w_wrfull;
assign rdfull = w_rdfull;
assign wrempty = w_wrempty;
assign rdempty = w_rdempty;
assign wrusedw = w_wrusedw;
assign rdusedw = w_rdusedw;
endmodule // lpm_fifo_dc_async
// END OF MODULE
//START_MODULE_NAME------------------------------------------------------------
//
// Module Name : lpm_fifo_dc
//
// Description :
//
// Limitation :
//
// Results expected:
//
//END_MODULE_NAME--------------------------------------------------------------
// BEGINNING OF MODULE
`timescale 1 ps / 1 ps
// MODULE DECLARATION
module lpm_fifo_dc (data,
rdclock,
wrclock,
aclr,
rdreq,
wrreq,
rdfull,
wrfull,
rdempty,
wrempty,
rdusedw,
wrusedw,
q);
// GLOBAL PARAMETER DECLARATION
parameter lpm_width = 1;
parameter lpm_widthu = 1;
parameter lpm_numwords = 2;
parameter lpm_showahead = "OFF";
parameter underflow_checking = "ON";
parameter overflow_checking = "ON";
parameter lpm_hint = "";
parameter lpm_type = "lpm_fifo_dc";
// LOCAL PARAMETER DECLARATION
parameter delay_rdusedw = 1;
parameter delay_wrusedw = 1;
parameter rdsync_delaypipe = 3;
parameter wrsync_delaypipe = 3;
// INPUT PORT DECLARATION
input [lpm_width-1:0] data;
input rdclock;
input wrclock;
input aclr;
input rdreq;
input wrreq;
// OUTPUT PORT DECLARATION
output rdfull;
output wrfull;
output rdempty;
output wrempty;
output [lpm_widthu-1:0] rdusedw;
output [lpm_widthu-1:0] wrusedw;
output [lpm_width-1:0] q;
// internal reg
wire w_rdfull_s;
wire w_wrfull_s;
wire w_rdempty_s;
wire w_wrempty_s;
wire w_rdfull_a;
wire w_wrfull_a;
wire w_rdempty_a;
wire w_wrempty_a;
wire [lpm_widthu-1:0] w_rdusedw_s;
wire [lpm_widthu-1:0] w_wrusedw_s;
wire [lpm_widthu-1:0] w_rdusedw_a;
wire [lpm_widthu-1:0] w_wrusedw_a;
wire [lpm_width-1:0] w_q_s;
wire [lpm_width-1:0] w_q_a;
wire i_aclr;
// INTERNAL TRI DECLARATION
tri0 aclr;
buf (i_aclr, aclr);
// COMPONENT INSTANTIATIONS
lpm_fifo_dc_async ASYNC (
.data (data),
.rdclk (rdclock),
.wrclk (wrclock),
.aclr (i_aclr),
.rdreq (rdreq),
.wrreq (wrreq),
.rdfull (w_rdfull_a),
.wrfull (w_wrfull_a),
.rdempty (w_rdempty_a),
.wrempty (w_wrempty_a),
.rdusedw (w_rdusedw_a),
.wrusedw (w_wrusedw_a),
.q (w_q_a) );
defparam
ASYNC.lpm_width = lpm_width,
ASYNC.lpm_widthu = lpm_widthu,
ASYNC.lpm_numwords = lpm_numwords,
ASYNC.delay_rdusedw = delay_rdusedw,
ASYNC.delay_wrusedw = delay_wrusedw,
ASYNC.rdsync_delaypipe = rdsync_delaypipe,
ASYNC.wrsync_delaypipe = wrsync_delaypipe,
ASYNC.lpm_showahead = lpm_showahead,
ASYNC.underflow_checking = underflow_checking,
ASYNC.overflow_checking = overflow_checking,
ASYNC.lpm_hint = lpm_hint;
// CONTINOUS ASSIGNMENT
assign rdfull = w_rdfull_a;
assign wrfull = w_wrfull_a;
assign rdempty = w_rdempty_a;
assign wrempty = w_wrempty_a;
assign rdusedw = w_rdusedw_a;
assign wrusedw = w_wrusedw_a;
assign q = w_q_a;
endmodule // lpm_fifo_dc
// END OF MODULE
//START_MODULE_NAME------------------------------------------------------------
//
// Module Name : lpm_inpad
//
// Description :
//
// Limitation : n/a
//
// Results expected:
//
//END_MODULE_NAME--------------------------------------------------------------
// BEGINNING OF MODULE
`timescale 1 ps / 1 ps
// MODULE DECLARATION
module lpm_inpad (
pad,
result
);
// GLOBAL PARAMETER DECLARATION
parameter lpm_width = 1;
parameter lpm_type = "lpm_inpad";
parameter lpm_hint = "UNUSED";
// INPUT PORT DECLARATION
input [lpm_width-1:0] pad;
// OUTPUT PORT DECLARATION
output [lpm_width-1:0] result;
// INTERNAL REGISTER/SIGNAL DECLARATION
reg [lpm_width-1:0] result;
// INITIAL CONSTRUCT BLOCK
initial
begin
if (lpm_width <= 0)
begin
$display("Value of lpm_width parameter must be greater than 0(ERROR)");
$display("Time: %0t Instance: %m", $time);
$finish;
end
end
// ALWAYS CONSTRUCT BLOCK
always @(pad)
begin
result = pad;
end
endmodule // lpm_inpad
// END OF MODULE
//START_MODULE_NAME------------------------------------------------------------
//
// Module Name : lpm_outpad
//
// Description :
//
// Limitation : n/a
//
// Results expected:
//
//END_MODULE_NAME--------------------------------------------------------------
// BEGINNING OF MODULE
`timescale 1 ps / 1 ps
// MODULE DECLARATION
module lpm_outpad (
data,
pad
);
// GLOBAL PARAMETER DECLARATION
parameter lpm_width = 1;
parameter lpm_type = "lpm_outpad";
parameter lpm_hint = "UNUSED";
// INPUT PORT DECLARATION
input [lpm_width-1:0] data;
// OUTPUT PORT DECLARATION
output [lpm_width-1:0] pad;
// INTERNAL REGISTER/SIGNAL DECLARATION
reg [lpm_width-1:0] pad;
// INITIAL CONSTRUCT BLOCK
initial
begin
if (lpm_width <= 0)
begin
$display("Value of lpm_width parameter must be greater than 0(ERROR)");
$display("Time: %0t Instance: %m", $time);
$finish;
end
end
// ALWAYS CONSTRUCT BLOCK
always @(data)
begin
pad = data;
end
endmodule // lpm_outpad
// END OF MODULE
//START_MODULE_NAME------------------------------------------------------------
//
// Module Name : lpm_bipad
//
// Description :
//
// Limitation : n/a
//
// Results expected:
//
//END_MODULE_NAME--------------------------------------------------------------
// BEGINNING OF MODULE
`timescale 1 ps / 1 ps
// MODULE DECLARATION
module lpm_bipad (
data,
enable,
result,
pad
);
// GLOBAL PARAMETER DECLARATION
parameter lpm_width = 1;
parameter lpm_type = "lpm_bipad";
parameter lpm_hint = "UNUSED";
// INPUT PORT DECLARATION
input [lpm_width-1:0] data;
input enable;
// OUTPUT PORT DECLARATION
output [lpm_width-1:0] result;
// INPUT/OUTPUT PORT DECLARATION
inout [lpm_width-1:0] pad;
// INTERNAL REGISTER/SIGNAL DECLARATION
reg [lpm_width-1:0] result;
// INITIAL CONSTRUCT BLOCK
initial
begin
if (lpm_width <= 0)
begin
$display("Value of lpm_width parameter must be greater than 0(ERROR)");
$display("Time: %0t Instance: %m", $time);
$finish;
end
end
// ALWAYS CONSTRUCT BLOCK
always @(data or pad or enable)
begin
if (enable == 1)
begin
result = {lpm_width{1'bz}};
end
else if (enable == 0)
begin
result = pad;
end
end
// CONTINOUS ASSIGNMENT
assign pad = (enable == 1) ? data : {lpm_width{1'bz}};
endmodule // lpm_bipad
// END OF MODULE
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__OR4BB_PP_SYMBOL_V
`define SKY130_FD_SC_MS__OR4BB_PP_SYMBOL_V
/**
* or4bb: 4-input OR, first two inputs inverted.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__or4bb (
//# {{data|Data Signals}}
input A ,
input B ,
input C_N ,
input D_N ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__OR4BB_PP_SYMBOL_V
|
//----------------------------------------------------------------------------
//`timescale 1 ns / 100 ps
module fifo_TB;
//----------------------------------------------------------------------------
// Parameter (may differ for physical synthesis)
//----------------------------------------------------------------------------
parameter tck = 2; // clock period in ns
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
reg clk;
reg rst;
reg rd,wr;
reg [7:0] data_in;
//----------------------------------------------------------------------------
// Device Under Test
//------------------------------------------------------------------
fifo uut(.reset(rst),.clk(clk),.rd1(rd),.wr1(wr),.data_in(data_in));
/* Clocking device */
initial begin
clk <= 0;
rst <=1;
#(2*tck) rst=0;
end
always #(tck/2) clk <= ~clk;
initial begin
wr<=1'b0; #1 ;
wr<=1'b1; #100 ;
wr<=1'b0; #1 ;
end
initial begin
rd<=1'b0; #25 ;
rd<=1'b1; #1020 ;
rd<=1'b0; #2 ;
end
initial begin
#4;
data_in="h"; #1;
data_in="o"; #1;
data_in="l"; #1;
data_in="a"; #1 ;
data_in=" "; #1 ;
data_in="m"; #1;
data_in="u"; #1 ;
data_in="n"; #1 ;
data_in="d"; #1 ;
data_in="o"; #1;
data_in="."; #1 ;
data_in="1"; #1 ;
data_in="2"; #1 ;
data_in="3"; #1 ;
data_in="4"; #1 ;
data_in="5"; #1 ;
data_in="6"; #1 ;
data_in="7"; #1;
data_in="8"; #1 ;
data_in="9"; #1 ;
data_in="0"; #1 ;
end
initial begin: TEST_CASE
$dumpfile("fifo_TB.vcd");
$dumpvars(-1, uut);
#(200) $finish;
end
endmodule //
|
module basic_checker
import bsg_cache_non_blocking_pkg::*;
#(parameter `BSG_INV_PARAM(data_width_p)
, parameter `BSG_INV_PARAM(id_width_p)
, parameter `BSG_INV_PARAM(addr_width_p)
, parameter `BSG_INV_PARAM(cache_pkt_width_lp)
, parameter data_mask_width_lp=(data_width_p>>3)
, parameter `BSG_INV_PARAM(mem_size_p)
)
(
input clk_i
, input reset_i
, input en_i
, input [cache_pkt_width_lp-1:0] cache_pkt_i
, input ready_o
, input v_i
, input [id_width_p-1:0] id_o
, input [data_width_p-1:0] data_o
, input v_o
, input yumi_i
);
`declare_bsg_cache_non_blocking_pkt_s(id_width_p,addr_width_p,data_width_p);
bsg_cache_non_blocking_pkt_s cache_pkt;
assign cache_pkt = cache_pkt_i;
// shadow mem
logic [data_width_p-1:0] shadow_mem [mem_size_p-1:0];
logic [data_width_p-1:0] result [*];
wire [addr_width_p-1:0] cache_pkt_word_addr = cache_pkt.addr[addr_width_p-1:2];
// store logic
logic [data_width_p-1:0] store_data;
logic [data_mask_width_lp-1:0] store_mask;
always_comb begin
case (cache_pkt.opcode)
SW: begin
store_data = cache_pkt.data;
store_mask = 4'b1111;
end
SH: begin
store_data = {2{cache_pkt.data[15:0]}};
store_mask = {
{2{ cache_pkt.addr[1]}},
{2{~cache_pkt.addr[1]}}
};
end
SB: begin
store_data = {4{cache_pkt.data[7:0]}};
store_mask = {
cache_pkt.addr[1] & cache_pkt.addr[0],
cache_pkt.addr[1] & ~cache_pkt.addr[0],
~cache_pkt.addr[1] & cache_pkt.addr[0],
~cache_pkt.addr[1] & ~cache_pkt.addr[0]
};
end
SM: begin
store_data = cache_pkt.data;
store_mask = cache_pkt.mask;
end
default: begin
store_data = '0;
store_mask = '0;
end
endcase
end
// load logic
logic [data_width_p-1:0] load_data, load_data_final;
logic [7:0] byte_sel;
logic [15:0] half_sel;
assign load_data = shadow_mem[cache_pkt_word_addr];
bsg_mux #(
.els_p(4)
,.width_p(8)
) byte_mux (
.data_i(load_data)
,.sel_i(cache_pkt.addr[1:0])
,.data_o(byte_sel)
);
bsg_mux #(
.els_p(2)
,.width_p(16)
) half_mux (
.data_i(load_data)
,.sel_i(cache_pkt.addr[1])
,.data_o(half_sel)
);
always_comb begin
case (cache_pkt.opcode)
LW: load_data_final = load_data;
LH: load_data_final = {{16{half_sel[15]}}, half_sel};
LB: load_data_final = {{24{byte_sel[7]}}, byte_sel};
LHU: load_data_final = {{16{1'b0}}, half_sel};
LBU: load_data_final = {{24{1'b0}}, byte_sel};
default: load_data_final = '0;
endcase
end
always_ff @ (posedge clk_i) begin
if (reset_i) begin
for (integer i = 0; i < mem_size_p; i++)
shadow_mem[i] <= '0;
end
else begin
if (en_i) begin
if (v_i & ready_o) begin
case (cache_pkt.opcode)
TAGST: begin
result[cache_pkt.id] = '0;
end
ALOCK, AUNLOCK: begin
result[cache_pkt.id] = '0;
end
TAGFL, AFL, AFLINV: begin
result[cache_pkt.id] = '0;
end
SB, SH, SW, SM: begin
result[cache_pkt.id] = '0;
for (integer i = 0; i < data_mask_width_lp; i++)
if (store_mask[i])
shadow_mem[cache_pkt_word_addr][8*i+:8] <= store_data[8*i+:8];
end
LW, LH, LB, LHU, LBU: begin
result[cache_pkt.id] = load_data_final;
end
endcase
end
end
end
if (~reset_i & v_o & yumi_i & en_i) begin
$display("id=%d, data=%x", id_o, data_o);
assert(result[id_o] == data_o)
else $fatal("[BSG_FATAL] Output does not match expected result. Id= %d, Expected: %x. Actual: %x",
id_o, result[id_o], data_o);
end
end
endmodule
`BSG_ABSTRACT_MODULE(basic_checker)
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__XNOR3_SYMBOL_V
`define SKY130_FD_SC_MS__XNOR3_SYMBOL_V
/**
* xnor3: 3-input exclusive NOR.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__xnor3 (
//# {{data|Data Signals}}
input A,
input B,
input C,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__XNOR3_SYMBOL_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 12/13/2015 11:06:55 AM
// Design Name:
// Module Name: SD_Control
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments: Need to add timeouts for command response states and handle additional response errors.
//
//////////////////////////////////////////////////////////////////////////////////
module SD_Control(
input SD_Clock, //200MHz
input Reset, //Active-High
input [7:0] SD_Data_in,
output reg Write_out, //Active-High
output Clock_Speed, // 0 = 400KHz, 1 = 25MHz
output reg [7:0] SD_Data_out,
output CS_out,
input Data_Send_Complete,
output reg [4:0] CurrentState,
input Read_in,
input Write_in,
output Ready_out,
input [29:0] Address_in,
input [4095:0] DDR_Data_out,
output reg [4095:0] DDR_Data_in);
wire [2:0] BitCount;
wire [8:0] ByteCount;
reg [4:0] NextState;
wire CountReset, BitEnable, ByteEnable;
parameter SD_STATE_INIT = 5'b00000;
parameter SD_STATE_CMD0 = 5'b00001;
parameter SD_STATE_CMD0_Response = 5'b00010;
parameter SD_STATE_DELAY1 = 5'b00011;
parameter SD_STATE_CMD55 = 5'b00100;
parameter SD_STATE_CMD55_Response = 5'b00101;
parameter SD_STATE_DELAY2 = 5'b00110;
parameter SD_STATE_ACMD41 = 5'b00111;
parameter SD_STATE_ACMD41_Response = 5'b01000;
parameter SD_STATE_IDLE = 5'b01001;
parameter SD_STATE_CMD17 = 5'b01010;
parameter SD_STATE_CMD17_Response = 5'b01011;
parameter SD_STATE_READTOKEN = 5'b01100;
parameter SD_STATE_READBLOCK = 5'b01101;
parameter SD_STATE_READCRC = 5'b01110;
parameter SD_STATE_READACK = 5'b01111;
parameter SD_STATE_CMD24 = 5'b10000;
parameter SD_STATE_CMD24_Response = 5'b10001;
parameter SD_STATE_WRITEDELAY = 5'b10010;
parameter SD_STATE_WRITETOKEN = 5'b10011;
parameter SD_STATE_WRITEBLOCK = 5'b10100;
parameter SD_STATE_WRITECRC = 5'b10101;
parameter SD_STATE_WRITERESPONSE = 5'b10110;
parameter SD_STATE_WRITEACK = 5'b10111;
initial DDR_Data_in = 4095'd0;
Counter #(.CountWidth(3)) Bit(
.Clock_in (SD_Clock),
.Enable_in (BitEnable),
.Reset_in (CountReset),
.Count_out (BitCount));
Counter #(.CountWidth(9)) Byte(
.Clock_in (SD_Clock),
.Enable_in (ByteEnable),
.Reset_in (CountReset),
.Count_out (ByteCount));
// Assignments
assign Ready_out = (CurrentState == SD_STATE_READACK || CurrentState == SD_STATE_WRITEACK);
assign CS_out = (CurrentState == SD_STATE_INIT);
assign Clock_Speed = ~(CurrentState == SD_STATE_INIT || CurrentState == SD_STATE_CMD0 || CurrentState == SD_STATE_CMD0_Response
|| CurrentState == SD_STATE_DELAY1 || CurrentState == SD_STATE_CMD55 || CurrentState == SD_STATE_CMD55_Response
|| CurrentState == SD_STATE_DELAY2 || CurrentState == SD_STATE_ACMD41 || CurrentState == SD_STATE_ACMD41_Response);
assign BitEnable = ~((CurrentState == SD_STATE_IDLE) && (SD_Data_in[0] == 1'b0)); //Disable all counting while SD card is busy.
assign ByteEnable = ((BitCount==3'd7)&&~(CurrentState == SD_STATE_IDLE && ByteCount == 9'd1))||(CurrentState == SD_STATE_WRITEBLOCK); //Ensure atleast 1Byte delay between end of reads and writes.
assign CountReset = (Reset) || ((CurrentState == SD_STATE_INIT) && (ByteCount == 9'd9) && (BitCount == 3'd2)) ||
((CurrentState == SD_STATE_CMD0_Response) && (~SD_Data_in[7])) ||
((CurrentState == SD_STATE_CMD55_Response) && (~SD_Data_in[7])) ||
((CurrentState == SD_STATE_ACMD41_Response) && (~SD_Data_in[7])) ||
((CurrentState == SD_STATE_DELAY1) && (ByteCount == 9'd1)) ||
((CurrentState == SD_STATE_DELAY2) && (ByteCount == 9'd1)) ||
((CurrentState == SD_STATE_IDLE) && (ByteCount == 9'd1) && ((~Write_in)||(~Read_in))) ||
((CurrentState == SD_STATE_READTOKEN) && (~SD_Data_in[0])) ||
((CurrentState == SD_STATE_CMD24_Response) && (~SD_Data_in[7])) ||
(CurrentState == SD_STATE_WRITETOKEN);
always @ (posedge SD_Clock)
begin
Write_out = ((CurrentState == SD_STATE_CMD0)||(CurrentState == SD_STATE_CMD55)||(CurrentState == SD_STATE_ACMD41)||
(CurrentState == SD_STATE_CMD17)||(CurrentState == SD_STATE_CMD24)||(CurrentState == SD_STATE_WRITETOKEN)||
(CurrentState == SD_STATE_WRITEBLOCK)||(CurrentState == SD_STATE_WRITECRC));
//Data Out
case (CurrentState)
SD_STATE_CMD0:
case (BitCount)
3'd0 : SD_Data_out = 8'h40;
3'd5 : SD_Data_out = 8'h95;
default : SD_Data_out = 8'h00;
endcase
SD_STATE_CMD55:
case (BitCount)
3'd0 : SD_Data_out = 8'h77;
default : SD_Data_out = 8'h00;
endcase
SD_STATE_ACMD41:
case (BitCount)
3'd0 : SD_Data_out = 8'h69;
default : SD_Data_out = 8'h00;
endcase
SD_STATE_CMD17:
case (BitCount)
3'd0 : SD_Data_out = 8'h51;
3'd1 : SD_Data_out = Address_in[29:22];
3'd2 : SD_Data_out = Address_in[21:14];
3'd3 : SD_Data_out = Address_in[13:6];
3'd4 : SD_Data_out = {Address_in[5:0],2'b0};
default : SD_Data_out = 8'h00;
endcase
SD_STATE_CMD24:
case (BitCount)
3'd0 : SD_Data_out = 8'h58;
3'd1 : SD_Data_out = Address_in[29:22];
3'd2 : SD_Data_out = Address_in[21:14];
3'd3 : SD_Data_out = Address_in[13:6];
3'd4 : SD_Data_out = {Address_in[5:0],2'b0};
default : SD_Data_out = 8'h00;
endcase
SD_STATE_WRITETOKEN:
SD_Data_out = 8'hfe;
SD_STATE_WRITEBLOCK:
SD_Data_out = DDR_Data_out[4095-(8*ByteCount)-:8];
default : SD_Data_out = 8'hff;
endcase
//Data In
if ((CurrentState == SD_STATE_READBLOCK) && (BitCount == 3'd7)) DDR_Data_in[4095-(8*ByteCount)-:8] = SD_Data_in;
end
// Synchronous State Transistion
always @ (posedge SD_Clock) CurrentState = (Reset) ? SD_STATE_INIT : NextState;
// State Logic
always @ (*)
case (CurrentState)
SD_STATE_INIT : NextState = (ByteCount == 9'd9 && BitCount == 3'd2) ? SD_STATE_CMD0 : SD_STATE_INIT;
SD_STATE_CMD0 : NextState = (BitCount == 3'd5) ? SD_STATE_CMD0_Response : SD_STATE_CMD0;
SD_STATE_CMD0_Response : NextState = (~SD_Data_in[7]) ? (SD_Data_in == 8'h01) ? SD_STATE_DELAY1 : SD_STATE_INIT : SD_STATE_CMD0_Response;
SD_STATE_DELAY1 : NextState = (ByteCount == 9'd1) ? SD_STATE_CMD55 : SD_STATE_DELAY1;
SD_STATE_CMD55 : NextState = (BitCount == 3'd5) ? SD_STATE_CMD55_Response : SD_STATE_CMD55;
SD_STATE_CMD55_Response : NextState = (~SD_Data_in[7]) ? (SD_Data_in == 8'h01) ? SD_STATE_DELAY2 : SD_STATE_INIT : SD_STATE_CMD55_Response;
SD_STATE_DELAY2 : NextState = (ByteCount == 9'd1) ? SD_STATE_ACMD41 : SD_STATE_DELAY2;
SD_STATE_ACMD41 : NextState = (BitCount == 3'd5) ? SD_STATE_ACMD41_Response : SD_STATE_ACMD41;
SD_STATE_ACMD41_Response : NextState = (~SD_Data_in[7]) ? (SD_Data_in == 8'h00) ? SD_STATE_IDLE : (SD_Data_in == 8'b01) ? SD_STATE_CMD55 : SD_STATE_INIT : SD_STATE_ACMD41_Response;
SD_STATE_IDLE : NextState = (ByteCount == 9'd1) ? (Write_in) ? SD_STATE_CMD24 : (Read_in) ? SD_STATE_CMD17 : SD_STATE_IDLE : SD_STATE_IDLE;
SD_STATE_CMD17 : NextState = (BitCount == 3'd5) ? SD_STATE_CMD17_Response : SD_STATE_CMD17;
SD_STATE_CMD17_Response : NextState = (ByteCount == 9'd20) ? SD_STATE_CMD17 : (~SD_Data_in[7]) ? (SD_Data_in == 8'h00) ? SD_STATE_READTOKEN : (SD_Data_in == 8'h01) ? SD_STATE_INIT : SD_STATE_CMD24 : SD_STATE_CMD17_Response;
SD_STATE_READTOKEN : NextState = (~SD_Data_in[0]) ? SD_STATE_READBLOCK : SD_STATE_READTOKEN;
SD_STATE_READBLOCK : NextState = ((ByteCount == 9'd511) && (BitCount == 3'd7)) ? SD_STATE_READCRC : SD_STATE_READBLOCK;
SD_STATE_READCRC : NextState = (ByteCount == 9'd2) ? SD_STATE_READACK : SD_STATE_READCRC;
SD_STATE_READACK : NextState = (~Read_in) ? SD_STATE_IDLE : SD_STATE_READACK;
SD_STATE_CMD24 : NextState = (BitCount == 3'd5) ? SD_STATE_CMD24_Response : SD_STATE_CMD24;
SD_STATE_CMD24_Response : NextState = (ByteCount == 9'd20) ? SD_STATE_CMD24 : (~SD_Data_in[7]) ? (SD_Data_in == 8'h00) ? SD_STATE_WRITEDELAY : (SD_Data_in == 8'h01) ? SD_STATE_INIT : SD_STATE_CMD24 : SD_STATE_CMD24_Response;
SD_STATE_WRITEDELAY : NextState = (ByteCount == 9'd1) ? SD_STATE_WRITETOKEN : SD_STATE_WRITEDELAY;
SD_STATE_WRITETOKEN : NextState = SD_STATE_WRITEBLOCK;
SD_STATE_WRITEBLOCK : NextState = (ByteCount == 9'd511) ? SD_STATE_WRITECRC : SD_STATE_WRITEBLOCK;
SD_STATE_WRITECRC : NextState = (ByteCount == 9'd2) ? SD_STATE_WRITERESPONSE : SD_STATE_WRITECRC;
SD_STATE_WRITERESPONSE : NextState = (SD_Data_in[4:0]==5'b00101) ? SD_STATE_WRITEACK : (SD_Data_in[4:0]==5'b01011 || SD_Data_in[4:0]==5'b01101) ? SD_STATE_IDLE : SD_STATE_WRITERESPONSE;
SD_STATE_WRITEACK : NextState = (~Write_in) ? SD_STATE_IDLE : SD_STATE_WRITEACK;
default : NextState = SD_STATE_INIT;
endcase
endmodule
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module hpdmc_banktimer(
input sys_clk,
input sdram_rst,
input tim_cas,
input [1:0] tim_wr,
input read,
input write,
output reg precharge_safe
);
reg [2:0] counter;
always @(posedge sys_clk) begin
if(sdram_rst) begin
counter <= 3'd0;
precharge_safe <= 1'b1;
end else begin
if(read) begin
/* see p.26 of datasheet :
* "A Read burst may be followed by, or truncated with, a Precharge command
* to the same bank. The Precharge command should be issued x cycles after
* the Read command, where x equals the number of desired data element
* pairs"
*/
counter <= 3'd4;
precharge_safe <= 1'b0;
end else if(write) begin
counter <= {1'b1, tim_wr};
precharge_safe <= 1'b0;
end else begin
if(counter == 3'b1)
precharge_safe <= 1'b1;
if(~precharge_safe)
counter <= counter - 3'b1;
end
end
end
endmodule
|
module testcall();
reg clk;
reg reset;
reg [7:0] snoopa;
reg [7:0] snoopd;
reg snoopp;
discus dcs(.clk(clk),
.reset(reset),
.snoop_clk(clk),
.snoopa(snoopa),
.snoopd(snoopd),
.snoopq(),
.snoopm(1'b0),
.snoopp(snoopp));
wire[7:0] prgram[0:9] = {
8'h03, 8'h00,
8'ha8,
8'h06, 8'h00,
8'ha8,
8'h09, 8'h00,
8'ha8,
8'ha8
};
initial begin : testit
integer i;
clk = 0;
snoopp = 1;
reset = 1;
for (i = 0; i <= 255; i = i + 1) begin
if (prgram[i] != 0) begin
snoopa = i;
snoopd = prgram[i];
clk = 0;
#10;
clk = 1;
#10;
clk = 0;
end
end
snoopp = 0;
reset = 0;
for (i = 0; i <= 40; i = i + 1) begin
clk = 0;
#10;
clk = 1;
#10;
clk = 0;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__UDP_DLATCH_PR_SYMBOL_V
`define SKY130_FD_SC_LS__UDP_DLATCH_PR_SYMBOL_V
/**
* udp_dlatch$PR: D-latch, gated clear direct / gate active high
* (Q output UDP)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__udp_dlatch$PR (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET,
//# {{clocks|Clocking}}
input GATE
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__UDP_DLATCH_PR_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NOR3_1_V
`define SKY130_FD_SC_LP__NOR3_1_V
/**
* nor3: 3-input NOR.
*
* Y = !(A | B | C | !D)
*
* Verilog wrapper for nor3 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__nor3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nor3_1 (
Y ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__nor3 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nor3_1 (
Y,
A,
B,
C
);
output Y;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__nor3 base (
.Y(Y),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__NOR3_1_V
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// (C) 2001-2010 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//
// -----------------------------------------------
// False path marker module
// This module creates a level of flops for the
// targetted clock, and cut the timing path to the
// flops using embedded SDC constraint
//
// Only use this module to clock cross the path
// that is being clock crossed properly by correct
// concept.
// -----------------------------------------------
`timescale 1ns / 1ns
module altera_tse_false_path_marker
#(
parameter MARKER_WIDTH = 1
)
(
input reset,
input clk,
input [MARKER_WIDTH - 1 : 0] data_in,
output [MARKER_WIDTH - 1 : 0] data_out
);
(*preserve*) reg [MARKER_WIDTH - 1 : 0] data_out_reg;
assign data_out = data_out_reg;
always @(posedge clk or posedge reset)
begin
if (reset)
begin
data_out_reg <= {MARKER_WIDTH{1'b0}};
end
else
begin
data_out_reg <= data_in;
end
end
endmodule
|
// (C) 2001-2017 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module hps_sdram_p0_generic_ddio(
datain,
halfratebypass,
dataout,
clk_hr,
clk_fr
);
parameter WIDTH = 1;
localparam DATA_IN_WIDTH = 4 * WIDTH;
localparam DATA_OUT_WIDTH = WIDTH;
input [DATA_IN_WIDTH-1:0] datain;
input halfratebypass;
input [WIDTH-1:0] clk_hr;
input [WIDTH-1:0] clk_fr;
output [DATA_OUT_WIDTH-1:0] dataout;
generate
genvar pin;
for (pin = 0; pin < WIDTH; pin = pin + 1)
begin:acblock
wire fr_data_hi;
wire fr_data_lo;
cyclonev_ddio_out
#(
.half_rate_mode("true"),
.use_new_clocking_model("true"),
.async_mode("none")
) hr_to_fr_hi (
.datainhi(datain[pin * 4]),
.datainlo(datain[pin * 4 + 2]),
.dataout(fr_data_hi),
.clkhi (clk_hr[pin]),
.clklo (clk_hr[pin]),
.hrbypass(halfratebypass),
.muxsel (clk_hr[pin])
);
cyclonev_ddio_out
#(
.half_rate_mode("true"),
.use_new_clocking_model("true"),
.async_mode("none")
) hr_to_fr_lo (
.datainhi(datain[pin * 4 + 1]),
.datainlo(datain[pin * 4 + 3]),
.dataout(fr_data_lo),
.clkhi (clk_hr[pin]),
.clklo (clk_hr[pin]),
.hrbypass(halfratebypass),
.muxsel (clk_hr[pin])
);
cyclonev_ddio_out
#(
.async_mode("none"),
.half_rate_mode("false"),
.sync_mode("none"),
.use_new_clocking_model("true")
) ddio_out (
.datainhi(fr_data_hi),
.datainlo(fr_data_lo),
.dataout(dataout[pin]),
.clkhi (clk_fr[pin]),
.clklo (clk_fr[pin]),
.muxsel (clk_fr[pin])
);
end
endgenerate
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Sun May 28 18:34:36 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top system_ov7670_controller_0_0 -prefix
// system_ov7670_controller_0_0_ system_ov7670_controller_0_0_stub.v
// Design : system_ov7670_controller_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "ov7670_controller,Vivado 2016.4" *)
module system_ov7670_controller_0_0(clk, resend, config_finished, sioc, siod, reset,
pwdn, xclk)
/* synthesis syn_black_box black_box_pad_pin="clk,resend,config_finished,sioc,siod,reset,pwdn,xclk" */;
input clk;
input resend;
output config_finished;
output sioc;
inout siod;
output reset;
output pwdn;
output xclk;
endmodule
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title : 3D Texel Pipeline
// File : de3d_texel_pipe.v
// Author : Frank Bruno
// Created : 14-May-2011
// RCS File : $Source:$
// Status : $Id:$
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
// This is the OpenGL/ Direct3D Fixed Function pipeline.
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
module de3d_texel_pipe
#
(
parameter fract = 9
)
(
input de_clk, // Drawing engine clock.
input de_rstn, // Drawing engine reset.
input pix_valid, // Valid pixel
input clip, // Rectangular Clip Signal
input last, // Rectangular Clip Signal
input msk_last, // Rectangular Clip Signal
input fg_bgn, // foreground/background bit
input [15:0] current_x, // X location of pixel
input [15:0] current_y, // X location of pixel
input [31:0] current_argb, // Current interpolated value of ARGB
input [23:0] current_spec, // Specular color
input [7:0] current_fog, // fog table value
input [31:0] c3d_2, // 3D control register.
input [31:0] tex_2, // texture control register.
input [(fract-1):0] current_u, // U fractional portion.
input [(fract-1):0] current_v, // V fractional portion.
input [5:0] current_gamma, // Gamma for trilinear.
input [31:0] ul_tex, // Texels in
input [31:0] ur_tex, // Texels in
input [31:0] ll_tex, // Texels in
input [31:0] lr_tex, // Texels in
// From 2D Core.
input [1:0] ps_2, // Pixel size
input [23:0] alpha_2, // Alpha Compare Value
input [17:0] acntrl_2, // Alpha Control Register
input [31:0] fog_value, // Fog Color Value
// The two key values must be programmed
// by software to match the texel fmt.
input [23:0] key_low, // Low color in the chroma clip range
input [23:0] key_hi, // High color in the chroma clip range
input pc_busy, // Pixel Cache busy
output reg [31:0] formatted_pixel, // Current Pixel to Pixel Cache
output reg [7:0] current_alpha, // Current Alpha to Pixel Cache
output reg [15:0] x_out, // X_POS from F Register
output reg [15:0] y_out, // Y_POS from F Register
output reg pc_valid, // Load Pixel Signal to Pixel Cache
output reg pc_last, // Last pixel to flush PC
output reg pc_msk_last, // Mask the last pixel.
output reg pc_fg_bgn, // Fore ground/Back ground select.
output reg pop_xy, // Pop the current X&Y location
output reg pop_spec, // Pop the current X&Y location
output reg pop_argb, // Pop the current ARGB location
output reg pop_z, // Pop Z.
output reg pop_fog, // Pop Fog, this can be Vertex or Table fog..
output reg ps565s_20, // Pipeline source format
output reg ps565s_21, // Pipeline source format
output reg [2:0] val3, // dither lookup
output reg [1:0] val2, // dither lookup
output reg inc_red, // dither increment
output reg inc_green, // dither increment
output reg inc_blue, // dither increment
output reg [5:0] rr_out, // Red and blue intermediate
output reg [6:0] gg_out, // Green intermediate
output reg [5:0] bb_out // Red and blue intermediate
);
`include "../include/define_3d.h"
localparam
BLUE = 0,
GREEN = 1,
RED = 2,
ALPHA = 3;
wire ps8 = ~|ps_2;
wire ps565s = &ps_2;
wire ps16s = ~ps_2[1] & ps_2[0];
// ALPHA Registers.
wire [7:0] alpha_test = alpha_2[23:16]; // Alpha Compare Value
wire alpha_comp_en = acntrl_2[14]; // Alpha Compare Enable Bit
wire [2:0] alpha_comp_op = acntrl_2[13:11];// Alpha clipping operator
wire alpha_sel = acntrl_2[15]; // Alpha Select Bit
wire alpha_mod = acntrl_2[16]; // Alpha_modulation bit
wire alpha_bl_sel = acntrl_2[17]; // Alpha blending
// 3D Control register.
wire ps8p = c3d_2`D3_P8; // 8 bpp Palletized mode
wire fog_en = c3d_2`D3_FEN; // Enable or disable fog
wire spec_enable = c3d_2`D3_SPE; // Spec Highlight Enable.
wire rgb_select = c3d_2`D3_RSL; // select RGB
wire tex_bl_sel = c3d_2`D3_TBS; // Texture blending
wire dither_op = c3d_2`D3_DOP; // Dither Control Bits
wire key_en = c3d_2`D3_KYE; // Enable color keying
wire key_pol = c3d_2`D3_KYP; // key polarity: 0 = inclusive
// TextureD Control register.
wire decal_a_blend = 0; // (FIX ME) Texture Decal Alpha Blend Mode
wire rgb_modulation = tex_2`T_RGBM; // Texture Map RGB Modulation Mode
wire texture_map = tex_2`T_TM; // Texture Map Mode Bit
// wire near_mode = tex_2`T_NMM; // Nearest U,V Address Mode
// wire near_mode_mag = tex_2`T_NMG; // Nearest U,V Address Mode
reg [31:0] texel_pipe1_0; // Pipeline texels
reg [31:0] texel_pipe1_1; // Pipeline texels
reg [31:0] texel_pipe1_2; // Pipeline texels
reg [31:0] texel_pipe1_3; // Pipeline texels
reg [16:0] ul_3, ur_3, ll_3, lr_3;
reg [16:0] ul_2, ur_2, ll_2, lr_2;
reg [16:0] ul_1, ur_1, ll_1, lr_1;
reg [16:0] ul_0, ur_0, ll_0, lr_0;
reg signed [fract:0] u_fract, u_fract_m1;
reg signed [fract:0] v_fract[5:1], v_fract_m1;
reg [17:0] upper_tex[3:0], lower_tex[3:0];
reg [7:0] upper_tex_clamp[3:0], lower_tex_clamp[3:0];
reg [16:0] texel_top[3:0], texel_bot[3:0];
reg [17:0] texel_bi_full[3:0];
reg [7:0] texel_bi[10:7][3:0];
reg [7:0] one_minus_alpha_8;
reg [7:0] one_minus[3:0];
reg [7:0] current_argb_d[2:0][2:0]; // delayed 1 cycle
reg [8:0] spec_add[2:0]; // Specular + shaded
reg alpha_clip; // Clip signal due to alpha test
reg [7:0] alpha_argb_pipe[11:9];// Pipeline alpha
reg [16:0] temp9, temp9a; // alpha calculation variables
reg [7:0] one_minus_10[3:0];
reg [7:0] alpha_pipe[12:10]; // Pipeline alpha
reg [15:0] temp16[2:0], temp16a[2:0];
reg [7:0] final_color[19:12][2:0]; // Pipeline colors
reg [7:0] final_alpha[19:12]; // Pipeline alpha
reg [7:0] fog_m1; // Fog value - 1
reg [7:0] fog_factor_pipe; // Pipeline fog factor
// reg [23:0] fog1, fog2;
reg [15:0] fog1_red, fog2_red;
reg [15:0] fog1_grn, fog2_grn;
reg [15:0] fog1_blu, fog2_blu;
reg [15:0] x_pipe[20:17];
reg [15:0] y_pipe[20:17];
reg [8:0] fogged_color[2:0];
// reg ps565s_20; // Pipeline source format
// reg ps565s_21; // Pipeline source format
// reg [2:0] val3; // dither lookup
// reg [1:0] val2; // dither lookup
// reg inc_red; // dither increment
// reg inc_green; // dither increment
// reg inc_blue; // dither increment
// reg [5:0] rr_out; // Red and blue intermediate
// reg [5:0] bb_out; // Red and blue intermediate
// reg [6:0] gg_out; // Green intermediate
reg [1:0] alpha_lt; // alpha compare
reg [1:0] alpha_gt; // alpha compare
reg [1:0] alpha_eq; // alpha compare
reg alpha_tex_sel; // alpha from texture or shader
reg [20:0] pipe_valid; // Pipeline pix valid
reg [16:13] alpha_clip_pipe; // Pipeline for Alpha Clip.
reg [20:1] clip_key; // Clip signal
reg [20:17] clip_pipe; // Clip signal
reg [20:17] pipe_last; // Pipeline the last signal.
reg [20:17] pipe_last_msk; // Pipeline the mask last signal.
reg [20:17] pipe_fg_bgn; // Pipeline the fg_bgn signal.
reg [3:0] key_clip; // Texel Keying clip signals
reg [5:0] gamma_pipe[13:1]; // Gamma Pipe.
// Pipelined signals
// CCS and border color FIFO
wire [31:0] texel[3:0]; // Texels in
wire border_empty; // Border FIFO empty
wire border_full; // Border FIFO full
wire [31:0] border_out; // border color from FIFO
wire [7:0] border_used; // border color used words
wire ccs_out; // border clamp pipelined
wire opengl; // Opengl mode
wire val_comb; // Valid control setup
wire d3d;
// wire nearest_md;
assign opengl = tex_bl_sel | alpha_bl_sel;
assign d3d = spec_enable;
assign val_comb = ~(opengl & d3d);
// assign nearest_md = near_mode | near_mode_mag;
always @* begin
// if(texture_map & !pc_busy) pop_argb = pipe_valid[6];
// else if(!pc_busy)pop_argb = pix_valid;
// else pop_argb = 1'b0;
if(texture_map) pop_argb = pipe_valid[6];
else pop_argb = pix_valid;
end
always @(posedge de_clk, negedge de_rstn)
if (!de_rstn) begin
clip_pipe <= 0;
clip_key <= 0;
pipe_valid <= 21'b0;
pipe_last <= 0;
pipe_last_msk <= 0;
alpha_tex_sel <= 1'b0;
end else begin
alpha_tex_sel <= texture_map & ~alpha_sel;
if(texture_map) begin
pipe_valid <= pipe_valid << 1 | (pix_valid);
clip_key <= clip_key << 1 | (&key_clip);
// Need to handle nearest for clipping
end else
pipe_valid <= pipe_valid << 1 | {(pix_valid), 7'h0};
//if (alpha_clip_pipe[16]) clip_pipe[17] <= 1'b0;
clip_pipe <= clip_pipe << 1 | (clip | alpha_clip_pipe[16]);
pipe_last <= pipe_last << 1 | (last);
pipe_last_msk <= pipe_last_msk << 1 | (msk_last);
pipe_fg_bgn <= pipe_fg_bgn << 1 | (fg_bgn);
end
`ifdef RTL_SIM
reg [4:0] pipe_number;
always @* begin
case(pipe_valid)
21'b000000000000000000000:pipe_number = 5'd0;
21'b000000000000000000001:pipe_number = 5'd1;
21'b000000000000000000010:pipe_number = 5'd2;
21'b000000000000000000100:pipe_number = 5'd3;
21'b000000000000000001000:pipe_number = 5'd4;
21'b000000000000000010000:pipe_number = 5'd5;
21'b000000000000000100000:pipe_number = 5'd6;
21'b000000000000001000000:pipe_number = 5'd7;
21'b000000000000010000000:pipe_number = 5'd8;
21'b000000000000100000000:pipe_number = 5'd9;
21'b000000000001000000000:pipe_number = 5'd10;
21'b000000000010000000000:pipe_number = 5'd11;
21'b000000000100000000000:pipe_number = 5'd12;
21'b000000001000000000000:pipe_number = 5'd13;
21'b000000010000000000000:pipe_number = 5'd14;
21'b000000100000000000000:pipe_number = 5'd15;
21'b000001000000000000000:pipe_number = 5'd16;
21'b000010000000000000000:pipe_number = 5'd17;
21'b000100000000000000000:pipe_number = 5'd18;
21'b001000000000000000000:pipe_number = 5'd19;
21'b010000000000000000000:pipe_number = 5'd20;
21'b100000000000000000000:pipe_number = 5'd21;
endcase
end
`endif
`ifdef RTL_SIM
reg [7:0] sample_0;
reg [7:0] sample_1;
reg [7:0] sample_2;
reg [7:0] sample_3;
always @(posedge de_clk) begin
if (pix_valid)
case ({|current_u[fract-1:0], |current_v[fract-1:0]})
2'b00: begin
// $display("Filtered texel: %h", texel[0]);
end
2'b01: begin
sample_0 = ul_tex[7:0] * current_v[fract-1:0] +
ll_tex[7:0] * (1 - current_v[fract-1:0]);
sample_1 = ul_tex[15:8] * current_v[fract-1:0] +
ll_tex[15:8] * (1 - current_v[fract-1:0]);
sample_2 = ul_tex[23:16] * current_v[fract-1:0] +
ll_tex[23:16] * (1 - current_v[fract-1:0]);
sample_3 = ul_tex[31:24] * current_v[fract-1:0] +
ll_tex[31:24] * (1 - current_v[fract-1:0]);
// $display("Filtered texel: %h", {sample[3], sample[2], sample[1], sample[0]});
end
2'b10: begin
sample_0 = ul_tex[7:0] * current_u[fract-1:0] +
ur_tex[7:0] * (1 - current_u[fract-1:0]);
sample_1 = ul_tex[15:8] * current_u[fract-1:0] +
ur_tex[15:8] * (1 - current_u[fract-1:0]);
sample_2 = ul_tex[23:16] * current_u[fract-1:0] +
ur_tex[23:16] * (1 - current_u[fract-1:0]);
sample_3 = ul_tex[31:24] * current_u[fract-1:0] +
ur_tex[31:24] * (1 - current_u[fract-1:0]);
// $display("Filtered texel: %h", {sample[3], sample[2], sample[1], sample[0]});
end
2'b11: begin
sample_0 = (ul_tex[7:0] * current_u[fract-1:0] +
ur_tex[7:0] * (1 - current_u[fract-1:0])) * current_v[fract-1:0] +
(ll_tex[7:0] * current_u[fract-1:0] +
lr_tex[7:0] * (1 - current_u[fract-1:0])) * (1 - current_v[fract-1:0]);
sample_1 = (ul_tex[15:8] * current_u[fract-1:0] +
ur_tex[15:8] * (1 - current_u[fract-1:0])) * current_v[fract-1:0] +
(ll_tex[15:8] * current_u[fract-1:0] +
lr_tex[15:8] * (1 - current_u[fract-1:0])) * (1 - current_v[fract-1:0]);
sample_2 = (ul_tex[23:16] * current_u[fract-1:0] +
ur_tex[23:16] * (1 - current_u[fract-1:0])) * current_v[fract-1:0] +
(ll_tex[23:16] * current_u[fract-1:0] +
lr_tex[23:16] * (1 - current_u[fract-1:0])) * (1 - current_v[fract-1:0]);
sample_3 = (ul_tex[31:24] * current_u[fract-1:0] +
ur_tex[31:24] * (1 - current_u[fract-1:0])) * current_v[fract-1:0] +
(ll_tex[31:24] * current_u[fract-1:0] +
lr_tex[31:24] * (1 - current_u[fract-1:0])) * (1 - current_v[fract-1:0]);
// $display("Filtered texel: %h", {sample[3], sample[2], sample[1], sample[0]});
end // case: 2'b11
endcase // case ({|current_u[fract-1:0], |current_v[fract-1:0]})
end // always @ (posedge de_clk)
`endif
always @(posedge de_clk, negedge de_rstn)
if (!de_rstn) begin
pop_spec <= 1'b0;
pop_xy <= 1'b0;
pop_z <= 1'b0;
end else begin
// Pipe 1:
// Key texels
gamma_pipe[1] <= current_gamma;
key_clip[0] <= texel_key(key_en, key_pol, ul_tex, key_low, key_hi);
key_clip[1] <= texel_key(key_en, key_pol, ur_tex, key_low, key_hi);
key_clip[2] <= texel_key(key_en, key_pol, ll_tex, key_low, key_hi);
key_clip[3] <= texel_key(key_en, key_pol, lr_tex, key_low, key_hi);
texel_pipe1_0 <= ul_tex;
texel_pipe1_1 <= ur_tex;
texel_pipe1_2 <= ll_tex;
texel_pipe1_3 <= lr_tex;
// Pipeline fractions
v_fract[1] <= {1'b0, current_v[fract-1:0]};
u_fract <= {1'b0, current_u[fract-1:0]};
u_fract_m1 <= (~|current_u[fract-1:0]) ? (1'b1 << fract) : {1'b0, ~current_u[fract-1:0]};
// Pipe 2:
//texel_pipe2[l2] <= key_clip[l2] ? 32'b0 : texel_pipe1[l2];
gamma_pipe[2] <= gamma_pipe[1];
// Bilinear math - Left/ Right
ul_0 <= ({8{~key_clip[0]}} & texel_pipe1_0[7:0]) * u_fract_m1;
ul_1 <= ({8{~key_clip[0]}} & texel_pipe1_0[15:8]) * u_fract_m1;
ul_2 <= ({8{~key_clip[0]}} & texel_pipe1_0[23:16]) * u_fract_m1;
ul_3 <= ({8{~key_clip[0]}} & texel_pipe1_0[31:24]) * u_fract_m1;
ur_0 <= ({8{~key_clip[1]}} & texel_pipe1_1[7:0]) * u_fract;
ur_1 <= ({8{~key_clip[1]}} & texel_pipe1_1[15:8]) * u_fract;
ur_2 <= ({8{~key_clip[1]}} & texel_pipe1_1[23:16]) * u_fract;
ur_3 <= ({8{~key_clip[1]}} & texel_pipe1_1[31:24]) * u_fract;
ll_0 <= ({8{~key_clip[2]}} & texel_pipe1_2[7:0]) * u_fract_m1;
ll_1 <= ({8{~key_clip[2]}} & texel_pipe1_2[15:8]) * u_fract_m1;
ll_2 <= ({8{~key_clip[2]}} & texel_pipe1_2[23:16]) * u_fract_m1;
ll_3 <= ({8{~key_clip[2]}} & texel_pipe1_2[31:24]) * u_fract_m1;
lr_0 <= ({8{~key_clip[3]}} & texel_pipe1_3[7:0]) * u_fract;
lr_1 <= ({8{~key_clip[3]}} & texel_pipe1_3[15:8]) * u_fract;
lr_2 <= ({8{~key_clip[3]}} & texel_pipe1_3[23:16]) * u_fract;
lr_3 <= ({8{~key_clip[3]}} & texel_pipe1_3[31:24]) * u_fract;
// Pipe 2: Take 1- the fractions
v_fract[2] <= v_fract[1];
// Pipe 3:
gamma_pipe[3] <= gamma_pipe[2];
v_fract[3] <= v_fract[2];
upper_tex[0] <= ul_0 + ur_0;
upper_tex[1] <= ul_1 + ur_1;
upper_tex[2] <= ul_2 + ur_2;
upper_tex[3] <= ul_3 + ur_3;
lower_tex[0] <= ll_0 + lr_0;
lower_tex[1] <= ll_1 + lr_1;
lower_tex[2] <= ll_2 + lr_2;
lower_tex[3] <= ll_3 + lr_3;
// Pipe 4:
gamma_pipe[4] <= gamma_pipe[3];
// Clamp texels
if (upper_tex[0][17] || &upper_tex[0][16:9]) upper_tex_clamp[0] <= 8'hFF;
else upper_tex_clamp[0] <= (upper_tex[0] >> fract) + upper_tex[0][fract-8'h1];
if (upper_tex[1][17] || &upper_tex[1][16:9]) upper_tex_clamp[1] <= 8'hFF;
else upper_tex_clamp[1] <= (upper_tex[1] >> fract) + upper_tex[1][fract-8'h1];
if (upper_tex[2][17] || &upper_tex[2][16:9]) upper_tex_clamp[2] <= 8'hFF;
else upper_tex_clamp[2] <= (upper_tex[2] >> fract) + upper_tex[2][fract-8'h1];
if (upper_tex[3][17] || &upper_tex[3][16:9]) upper_tex_clamp[3] <= 8'hFF;
else upper_tex_clamp[3] <= (upper_tex[3] >> fract) + upper_tex[3][fract-8'h1];
if (lower_tex[0][17] || &lower_tex[0][16:9]) lower_tex_clamp[0] <= 8'hFF;
else lower_tex_clamp[0] <= (lower_tex[0] >> fract) + lower_tex[0][fract-8'h1];
if (lower_tex[1][17] || &lower_tex[1][16:9]) lower_tex_clamp[1] <= 8'hFF;
else lower_tex_clamp[1] <= (lower_tex[1] >> fract) + lower_tex[1][fract-8'h1];
if (lower_tex[2][17] || &lower_tex[2][16:9]) lower_tex_clamp[2] <= 8'hFF;
else lower_tex_clamp[2] <= (lower_tex[2] >> fract) + lower_tex[2][fract-8'h1];
if (lower_tex[3][17] || &lower_tex[3][16:9]) lower_tex_clamp[3] <= 8'hFF;
else lower_tex_clamp[3] <= (lower_tex[3] >> fract) + lower_tex[3][fract-8'h1];
v_fract[4] <= v_fract[3];
v_fract_m1 <= (~|v_fract[3]) ? (1'b1 << fract) : {1'b0, ~v_fract[3][fract-1:0]};
// Pipe 5:
gamma_pipe[5] <= gamma_pipe[4];
// Blinear Math - Upper / Lower
texel_top[0] <= upper_tex_clamp[0] * v_fract_m1;
texel_top[1] <= upper_tex_clamp[1] * v_fract_m1;
texel_top[2] <= upper_tex_clamp[2] * v_fract_m1;
texel_top[3] <= upper_tex_clamp[3] * v_fract_m1;
texel_bot[0] <= lower_tex_clamp[0] * v_fract[4];
texel_bot[1] <= lower_tex_clamp[1] * v_fract[4];
texel_bot[2] <= lower_tex_clamp[2] * v_fract[4];
texel_bot[3] <= lower_tex_clamp[3] * v_fract[4];
// Pipe 6:
gamma_pipe[6] <= gamma_pipe[5];
texel_bi_full[0] <= texel_top[0] + texel_bot[0];
texel_bi_full[1] <= texel_top[1] + texel_bot[1];
texel_bi_full[2] <= texel_top[2] + texel_bot[2];
texel_bi_full[3] <= texel_top[3] + texel_bot[3];
// Pipe 7:
gamma_pipe[7] <= gamma_pipe[6];
// Final Bilinear filtered
// pop_argb <= pipe_valid[6];
if (texel_bi_full[0][17] || &texel_bi_full[0][16:9]) texel_bi[7][0] <= 8'hFF;
else texel_bi[7][0] <= (texel_bi_full[0] >> fract) + texel_bi_full[0][fract-8'h1];
if (texel_bi_full[1][17] || &texel_bi_full[1][16:9]) texel_bi[7][1] <= 8'hFF;
else texel_bi[7][1] <= (texel_bi_full[1] >> fract) + texel_bi_full[1][fract-8'h1];
if (texel_bi_full[2][17] || &texel_bi_full[2][16:9]) texel_bi[7][2] <= 8'hFF;
else texel_bi[7][2] <= (texel_bi_full[2] >> fract) + texel_bi_full[2][fract-8'h1];
if (texel_bi_full[3][17] || &texel_bi_full[3][16:9]) texel_bi[7][3] <= 8'hFF;
else texel_bi[7][3] <= (texel_bi_full[3] >> fract) + texel_bi_full[3][fract-8'h1];
// Pipe 8:
gamma_pipe[8] <= gamma_pipe[7];
// Modulation
one_minus_alpha_8 <= ~texel_bi[7][ALPHA] + 8'h1;
texel_bi[8][0] <= texel_bi[7][0];
texel_bi[8][1] <= texel_bi[7][1];
texel_bi[8][2] <= texel_bi[7][2];
texel_bi[8][3] <= texel_bi[7][3];
// Pipe 9:
gamma_pipe[9] <= gamma_pipe[8];
// Modulation
alpha_argb_pipe[9] <= current_argb[31:24];
current_argb_d[0][RED] <= current_argb[23:16];
current_argb_d[0][GREEN] <= current_argb[15:8];
current_argb_d[0][BLUE] <= current_argb[7:0];
texel_bi[9][0] <= texel_bi[8][0];
texel_bi[9][1] <= texel_bi[8][1];
texel_bi[9][2] <= texel_bi[8][2];
texel_bi[9][3] <= texel_bi[8][3];
case ({alpha_bl_sel, alpha_mod})
/*
2'b00: begin
// Texture Alpha, no modulation
temp9 <= {texel_bi[8][ALPHA], 8'h0};
temp9a <= 16'h0;
end
2'b10: begin
// Vertex Alpha, no modulation
temp9 <= {current_argb[31:24], 8'h0};
temp9a <= 16'h0;
end
2'b01: begin
// Modulate texture Alpha and Vertex Alpha
temp9 <= |texel_bi[8][ALPHA] ? one_minus_alpha_8 * current_argb[ALPHA] : {current_argb[ALPHA], 8'b0};
temp9a <= texel_bi[8][ALPHA] * current_argb[ALPHA];
end
2'b11: begin
// Vertex Alpha, no modulation
temp9 <= 16'h0;
temp9a <= 16'h0;
end
*/
2'b01: begin
// Vertex Alpha, no modulation
temp9 <= current_argb[31:24] * texel_bi[8][ALPHA];
temp9a <= 16'h0;
end
2'b10: begin
// Modulate texture Alpha and Vertex Alpha
temp9 <= |texel_bi[8][ALPHA] ? one_minus_alpha_8 * current_argb[ALPHA] : {current_argb[ALPHA], 8'b0};
temp9a <= texel_bi[8][ALPHA] * current_argb[ALPHA];
end
default: begin
// Texture Alpha, no modulation
temp9 <= {texel_bi[8][ALPHA], 8'h0};
temp9a <= 16'h0;
end
endcase // case ({alpha_bl_sel, alpha_mod})
// Pipe 10:
gamma_pipe[10] <= gamma_pipe[9];
pop_spec <= pipe_valid[9];
alpha_argb_pipe[10] <= alpha_argb_pipe[9];
current_argb_d[1][RED] <= current_argb_d[0][RED];
current_argb_d[1][GREEN] <= current_argb_d[0][GREEN];
current_argb_d[1][BLUE] <= current_argb_d[0][BLUE];
texel_bi[10][0] <= texel_bi[9][0];
one_minus_10[0] <= ~texel_bi[9][0];
texel_bi[10][1] <= texel_bi[9][1];
one_minus_10[1] <= ~texel_bi[9][1];
texel_bi[10][2] <= texel_bi[9][2];
one_minus_10[2] <= ~texel_bi[9][2];
texel_bi[10][3] <= texel_bi[9][3];
one_minus_10[3] <= ~texel_bi[9][3];
alpha_pipe[10] <= (temp9 >> 8) + (temp9a >> 8) + (temp9[7] | temp9a[7]);
// Pipe 11:
gamma_pipe[11] <= gamma_pipe[10];
pop_fog <= pipe_valid[10];
alpha_argb_pipe[11] <= alpha_argb_pipe[10];
current_argb_d[2][RED] <= current_argb_d[1][RED];
current_argb_d[2][GREEN] <= current_argb_d[1][GREEN];
current_argb_d[2][BLUE] <= current_argb_d[1][BLUE];
alpha_pipe[11] <= alpha_pipe[10];
alpha_lt[1] <= alpha_pipe[10] < alpha_test;
alpha_gt[1] <= alpha_pipe[10] > alpha_test;
alpha_eq[1] <= alpha_pipe[10] == alpha_test;
alpha_lt[0] <= alpha_argb_pipe[10] < alpha_test;
alpha_gt[0] <= alpha_argb_pipe[10] > alpha_test;
alpha_eq[0] <= alpha_argb_pipe[10] == alpha_test;
case ({val_comb, tex_bl_sel, rgb_modulation, decal_a_blend})
4'b1010: begin
temp16[0] <= texel_bi[10][0] * current_argb_d[1][0];
temp16a[0] <= 16'h0;
temp16[1] <= texel_bi[10][1] * current_argb_d[1][1];
temp16a[1] <= 16'h0;
temp16[2] <= texel_bi[10][2] * current_argb_d[1][2];
temp16a[2] <= 16'h0;
end
4'b1100: begin
temp16[0] <= |texel_bi[10][0] ?
one_minus_10[0] * current_argb_d[1][0] :
current_argb_d[1][0] << 8;
temp16[1] <= |texel_bi[10][1] ?
one_minus_10[1] * current_argb_d[1][1] :
current_argb_d[1][1] << 8;
temp16[2] <= |texel_bi[10][2] ?
one_minus_10[2] * current_argb_d[1][2] :
current_argb_d[1][2] << 8;
temp16a[0] <= texel_bi[10][0] * current_argb_d[1][0];
temp16a[1] <= texel_bi[10][1] * current_argb_d[1][1];
temp16a[2] <= texel_bi[10][2] * current_argb_d[1][2];
end
4'b1001: begin
temp16[0] <= texel_bi[10][0] * alpha_pipe[10];
temp16[1] <= texel_bi[10][1] * alpha_pipe[10];
temp16[2] <= texel_bi[10][2] * alpha_pipe[10];
temp16a[0] <= |alpha_pipe[10] ?
current_argb_d[1][0] * one_minus_10[0] :
current_argb_d[1][0] << 8;
temp16a[1] <= |alpha_pipe[10] ?
current_argb_d[1][1] * one_minus_10[1] :
current_argb_d[1][1] << 8;
temp16a[2] <= |alpha_pipe[10] ?
current_argb_d[1][2] * one_minus_10[2] :
current_argb_d[1][2] << 8;
end
default: begin
temp16[0] <= texel_bi[10][0] << 8;
temp16a[0] <= 8'h0;
temp16[1] <= texel_bi[10][1] << 8;
temp16a[1] <= 8'h0;
temp16[2] <= texel_bi[10][2] << 8;
temp16a[2] <= 8'h0;
end
endcase // case ({val_comb, tex_bl_sel, rgb_modulation, decal_a_blend})
// Pipe 12: Final stage
gamma_pipe[12] <= gamma_pipe[11];
if (texture_map & ~rgb_select) begin
final_color[12][0] <= (temp16[0] >> 8) + (temp16a[0] >> 8) +
(temp16[0][7] | temp16a[0][7]);
final_color[12][1] <= (temp16[1] >> 8) + (temp16a[1] >> 8) +
(temp16[1][7] | temp16a[1][7]);
final_color[12][2] <= (temp16[2] >> 8) + (temp16a[2] >> 8) +
(temp16[2][7] | temp16a[2][7]);
end
else begin
final_color[12][0] <= current_argb_d[2][0];
final_color[12][1] <= current_argb_d[2][1];
final_color[12][2] <= current_argb_d[2][2];
end
final_alpha[12] <= (texture_map & ~alpha_sel) ? alpha_pipe[11] :
alpha_argb_pipe[11];
casex ({alpha_comp_en, alpha_tex_sel, alpha_comp_op})
5'b0xxxx: alpha_clip <= 1'b0; // Not enabled
5'b1x000: alpha_clip <= 1'b1; // NEVER
5'b1x001: alpha_clip <= 1'b0; // ALWAYS
5'b10010: alpha_clip <= ~alpha_lt[0]; // LESS
5'b10011: alpha_clip <= ~(alpha_lt[0] | alpha_eq[0]); // LEQUAL
5'b10100: alpha_clip <= ~alpha_eq[0]; // EQUAL
5'b10101: alpha_clip <= ~(alpha_gt[0] | alpha_eq[0]); // GEQUAL
5'b10110: alpha_clip <= ~alpha_gt[0]; // GREATER
5'b10111: alpha_clip <= alpha_eq[0]; // NOTEQUAL
5'b11010: alpha_clip <= ~alpha_lt[1]; // LESS
5'b11011: alpha_clip <= ~(alpha_lt[1] | alpha_eq[1]); // LEQUAL
5'b11100: alpha_clip <= ~alpha_eq[1]; // EQUAL
5'b11101: alpha_clip <= ~(alpha_gt[1] | alpha_eq[1]); // GEQUAL
5'b11110: alpha_clip <= ~alpha_gt[1]; // GREATER
5'b11111: alpha_clip <= alpha_eq[1]; // NOTEQUAL
endcase // casex ({alpha_enable, alpha_comp_op})
// Pipe 13:
gamma_pipe[13] <= gamma_pipe[12];
alpha_clip_pipe[13] <= alpha_clip;
spec_add[RED] <= final_color[12][RED] + current_spec[23:16];
spec_add[GREEN] <= final_color[12][GREEN] + current_spec[15:8];
spec_add[BLUE] <= final_color[12][BLUE] + current_spec[7:0];
final_color[13][RED] <= final_color[12][RED];
final_color[13][GREEN] <= final_color[12][GREEN];
final_color[13][BLUE] <= final_color[12][BLUE];
final_alpha[13] <= final_alpha[12];
// Pipe 14:
alpha_clip_pipe[14] <= alpha_clip_pipe[13];
pop_xy <= pipe_valid[13];
// tex_2`T_MLM // trilinear enable.
// tex_2`T_MLP // trilinear pass.
casex({tex_2`T_MLM, tex_2`T_MLP})
2'b0x:begin // No trilinear.
//fog_m1 <= ~current_fog + 9'h1;
fog_m1 <= ~current_fog;
fog_factor_pipe <= current_fog;
end
2'b10:begin // trilinear first pass.
//fog_m1 <= ~{gamma_pipe[13],3'b000} + 9'h1;
fog_m1 <= ~{gamma_pipe[13],gamma_pipe[13][5:4]};
fog_factor_pipe <= {gamma_pipe[13],gamma_pipe[13][5:4]};
end
2'b11:begin // trilinear second pass.
fog_m1 <= {gamma_pipe[13],gamma_pipe[13][5:4]};
//fog_factor_pipe <= ~{gamma_pipe[13],3'b000} + 9'h1;
fog_factor_pipe <= ~{gamma_pipe[13],gamma_pipe[13][5:4]};
end
endcase
final_alpha[14] <= final_alpha[13];
if (~opengl && d3d) begin
final_color[14][RED] <= spec_add[RED][8] ? 8'hFF : spec_add[RED][7:0];
final_color[14][GREEN] <= spec_add[GREEN][8] ? 8'hFF : spec_add[GREEN][7:0];
final_color[14][BLUE] <= spec_add[BLUE][8] ? 8'hFF : spec_add[BLUE][7:0];
end else begin
final_color[14][RED] <= final_color[13][RED];
final_color[14][GREEN] <= final_color[13][GREEN];
final_color[14][BLUE] <= final_color[13][BLUE];
end
// Pipe 15: Fog Multiply
alpha_clip_pipe[15] <= alpha_clip_pipe[14];
final_alpha[15] <= final_alpha[14];
final_color[15][RED] <= final_color[14][RED];
final_color[15][GREEN] <= final_color[14][GREEN];
final_color[15][BLUE] <= final_color[14][BLUE];
// fog1[RED*8+:8] <= final_color[14][RED] * fog_factor_pipe;
// fog1[GREEN*8+:8] <= final_color[14][GREEN] * fog_factor_pipe;
// fog1[BLUE*8+:8] <= final_color[14][BLUE] * fog_factor_pipe;
// fog2[RED*8+:8] <= fog_value[RED*8+:8] * fog_m1;
// fog2[GREEN*8+:8] <= fog_value[GREEN*8+:8] * fog_m1;
// fog2[BLUE*8+:8] <= fog_value[BLUE*8+:8] * fog_m1;
//
fog1_red <= final_color[14][RED] * fog_factor_pipe;
fog1_grn <= final_color[14][GREEN] * fog_factor_pipe;
fog1_blu <= final_color[14][BLUE] * fog_factor_pipe;
fog2_red <= fog_value[RED*8+:8] * fog_m1;
fog2_grn <= fog_value[GREEN*8+:8] * fog_m1;
fog2_blu <= fog_value[BLUE*8+:8] * fog_m1;
// pipe 16: Fog Add
alpha_clip_pipe[16] <= alpha_clip_pipe[15];
final_alpha[16] <= final_alpha[15];
final_color[16][RED] <= final_color[15][RED];
final_color[16][GREEN] <= final_color[15][GREEN];
final_color[16][BLUE] <= final_color[15][BLUE];
// fogged_color[RED] <= fog1[RED*8+:8] + fog2[RED*8+:8];
// fogged_color[GREEN] <= fog1[GREEN*8+:8] + fog2[GREEN*8+:8];
// fogged_color[BLUE] <= fog1[BLUE*8+:8] + fog2[BLUE*8+:8];
fogged_color[RED] <= fog1_red[15:8] + fog2_red[15:8] +
(fog1_red[7] | fog2_red[7]);
fogged_color[GREEN] <= fog1_grn[15:8] + fog2_grn[15:8] +
(fog1_grn[7] | fog2_grn[7]);
fogged_color[BLUE] <= fog1_blu[15:8] + fog2_blu[15:8] +
(fog1_blu[7] | fog2_blu[7]);
// Pipe 17: Fog Normalize
final_alpha[17] <= final_alpha[16];
if (fog_en) begin
final_color[17][RED] <= fogged_color[RED][8] ? 8'hFF : fogged_color[RED][7:0];
final_color[17][GREEN] <= fogged_color[GREEN][8] ? 8'hFF : fogged_color[GREEN][7:0];
final_color[17][BLUE] <= fogged_color[BLUE][8] ? 8'hFF : fogged_color[BLUE][7:0];
end else begin
final_color[17][RED] <= final_color[16][RED];
final_color[17][GREEN] <= final_color[16][GREEN];
final_color[17][BLUE] <= final_color[16][BLUE];
end
// Look up Dither values
val3 = dith4x4_3(current_x[1:0],current_y[1:0]);
val2 = dith2x2_2(current_x[0],current_y[0]);
x_pipe[17] <= current_x;
y_pipe[17] <= current_y;
// Pipe 18: Dither
pop_z <= pipe_valid[17];
final_alpha[18] <= final_alpha[17];
final_color[18][RED] <= final_color[17][RED];
final_color[18][GREEN] <= final_color[17][GREEN];
final_color[18][BLUE] <= final_color[17][BLUE];
inc_red <= final_color[17][RED][2:0] > val3;
inc_green <= (ps565s) ? final_color[17][GREEN][1:0] > val2 :
final_color[17][GREEN][2:0] > val3;
inc_blue <= final_color[17][BLUE][2:0] > val3;
x_pipe[18] <= x_pipe[17];
y_pipe[18] <= y_pipe[17];
ps565s_20 <= ps565s;
// Pipe 19: Do dither Add
final_alpha[19] <= final_alpha[18];
final_color[19][RED] <= final_color[18][RED];
final_color[19][GREEN] <= final_color[18][GREEN];
final_color[19][BLUE] <= final_color[18][BLUE];
rr_out <= final_color[18][RED][7:3] + inc_red;
bb_out <= final_color[18][BLUE][7:3] + inc_blue;
if (ps565s_20) gg_out <= final_color[18][GREEN][7:2] + inc_green;
else gg_out <= {final_color[18][GREEN][7:3],1'b0} + {inc_green,1'b0};
x_pipe[19] <= x_pipe[18];
y_pipe[19] <= y_pipe[18];
ps565s_21 <= ps565s_20;
// Pipe 20: Select output
current_alpha <= final_alpha[19];
casex ({ps565s_21, ps16s, ps8, ps8p}) /* synopsys parallel_case */
// 565 - 16bpp Format
4'b1xxx: begin
x_out <= {x_pipe[19], 1'b0};
formatted_pixel[31:16] <= 16'h0000;
if (dither_op) begin
formatted_pixel[15:11] <= rr_out[5] ? 5'h1F : rr_out[4:0];
formatted_pixel[10:5] <= gg_out[6] ? 6'h3F : gg_out[5:0];
formatted_pixel[4:0] <= bb_out[5] ? 5'h1F : bb_out[4:0];
end else begin
formatted_pixel[15:11] <= final_color[19][RED][7:3];
formatted_pixel[10:5] <= final_color[19][GREEN][7:2];
formatted_pixel[4:0] <= final_color[19][BLUE][7:3];
end
end
// 1555 - 16bpp Format
4'b01xx: begin
x_out <= {x_pipe[19], 1'b0};
formatted_pixel[31:16] <= 16'h0000;
formatted_pixel[15] <= final_alpha[19][7];
if (dither_op) begin
formatted_pixel[14:10] <= rr_out[5] ? 5'h1F : rr_out[4:0];
formatted_pixel[9:5] <= gg_out[6] ? 5'h1F : gg_out[5:1];
formatted_pixel[4:0] <= bb_out[5] ? 5'h1F : bb_out[4:0];
end else begin
formatted_pixel[14:10] <= final_color[19][RED][7:3];
formatted_pixel[9:5] <= final_color[19][GREEN][7:3];
formatted_pixel[4:0] <= final_color[19][BLUE][7:3];
end
end
// 8bpp Indexed (332) Format
4'b0011: begin
x_out <= x_pipe[19];
formatted_pixel[31:8] = 24'h000000;
if (dither_op) begin
formatted_pixel[7:5] <= rr_out[3] ? 3'h7 : rr_out[4:2];
formatted_pixel[4:2] <= gg_out[3] ? 3'h7 : gg_out[5:3];
formatted_pixel[1:0] <= bb_out[2] ? 2'h3 : bb_out[4:3];
end else begin
formatted_pixel[7:5] <= final_color[19][RED][7:5];
formatted_pixel[4:2] <= final_color[19][GREEN][7:5];
formatted_pixel[1:0] <= final_color[19][BLUE][7:6];
end
end
// 8bpp (blue channel) Format
4'b0010: begin
x_out <= x_pipe[19];
formatted_pixel <= dither_op ? {24'h000000, bb_out[4:0], 3'b0} : final_color[19][BLUE];
end
// 32bpp ARGB Format
default: begin
x_out <= {x_pipe[19], 2'b00};
formatted_pixel <= (dither_op) ?
{
// rr_out[4:0], 3'b0,
// gg_out[5:0], 2'b0,
// bb_out[4:0], 3'b0
final_alpha[19],
final_color[19][RED],
final_color[19][GREEN],
final_color[19][BLUE]
} :
{
final_alpha[19],
final_color[19][RED],
final_color[19][GREEN],
final_color[19][BLUE]
};
end
endcase
pc_valid <= (pipe_valid[18] & ~clip_pipe[19] & ~clip_key[18]) | (pipe_valid[18] & pipe_last[19]);
y_out <= y_pipe[19];
pc_fg_bgn <= pipe_fg_bgn[19];
pc_last <= pipe_last[19];
pc_msk_last <= pipe_last_msk[19] | (pipe_last[19] & (clip_pipe[19] | clip_key[18]));
end // else: !if(!de_rstn)
function texel_key;
input key_en; // Enable keying
input key_pol; // 0 = inclusive, 1 = exclusive
input [23:0] texel; // Texel to compare
input [23:0] key_low; // Low key color
input [23:0] key_hi; // Low key color
reg gt_low;
reg eq_low;
reg lt_hi;
reg eq_hi;
reg [2:0] inclusive;
integer i;
begin
for (i = 0; i < 3; i = i + 1) begin
gt_low = texel[i*8+:8] > key_low[i*8+:8];
eq_low = texel[i*8+:8] == key_low[i*8+:8];
lt_hi = texel[i*8+:8] < key_hi[i*8+:8];
eq_hi = texel[i*8+:8] == key_hi[i*8+:8];
inclusive[i] = (gt_low | eq_low) & (lt_hi | eq_hi);
end
texel_key = key_en & (key_pol ? ~&inclusive : &inclusive);
end
endfunction // for
/*
* function dith4x4_3:
* This function implements an ordered dither matrix, for converting 8-bit
* pixels to 5-bit pixels. It is a modification of a D4 Bayer matrix, as
* described in Computer Graphics, Practices and Principles (Foley, Van Dam,
* et. al.) D4' is a standard D4 matrix (4-bit entries) with the LSB of each
* entry truncated.
*
* D4:
* 0 8 2 10
* 12 4 14 6
* 3 11 1 9
* 15 7 13 5
*
* D4':
* 0 4 1 5
* 6 2 7 3
* 1 5 0 4
* 7 3 6 2
*
*/
function [2:0] dith4x4_3;
input [1:0] x;
input [1:0] y;
begin
case ({y,x})
4'b00_00: dith4x4_3 = 0; // 0/8 = 0;
4'b00_01: dith4x4_3 = 4; // 4/8 = 0.5;
4'b00_10: dith4x4_3 = 1; // 1/8 = 0.125;
4'b00_11: dith4x4_3 = 5; // 5/8 = 0.625;
4'b01_00: dith4x4_3 = 6; // 6/8 = 0.75;
4'b01_01: dith4x4_3 = 2; // 2/8 = 0.25;
4'b01_10: dith4x4_3 = 7; // 7/8 = 0.875;
4'b01_11: dith4x4_3 = 3; // 3/8 = 0.375;
4'b10_00: dith4x4_3 = 1; // 1/8 = 0.125;
4'b10_01: dith4x4_3 = 5; // 5/8 = 0.625;
4'b10_10: dith4x4_3 = 0; // 0/8 = 0;
4'b10_11: dith4x4_3 = 4; // 4/8 = 0.5;
4'b11_00: dith4x4_3 = 7; // 7/8 = 0.875;
4'b11_01: dith4x4_3 = 3; // 3/8 = 0.375;
4'b11_10: dith4x4_3 = 6; // 6/8 = 0.75;
4'b11_11: dith4x4_3 = 2; // 2/8 = 0.25;
endcase // case ({y,x})
end
endfunction // dith4x4_3
/*
* function dith2x2_2:
* This function implements an ordered dither matrix, for converting 8-bit
* pixels to 6-bit pixels. It is a standard D2 Bayer matrix, as
* described in Computer Graphics, Practices and Principles (Foley, Van Dam,
* et. al.)
*
* D2:
* 0 2
* 3 1
*
*/
function [1:0] dith2x2_2;
input x;
input y;
begin
case ({y,x})
2'b0_0: dith2x2_2 = 0; // 0/4 = 0;
2'b0_1: dith2x2_2 = 2; // 2/4 = 0.4;
2'b1_0: dith2x2_2 = 1; // 1/4 = 0.25;
2'b1_1: dith2x2_2 = 3; // 3/4 = 0/75;
endcase // case ({y,x})
end
endfunction // dith4x4_3
endmodule
|
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version : 12.4
// \ \ Application : xaw2verilog
// / / Filename : master_clk.v
// /___/ /\ Timestamp : 05/02/2013 05:55:56
// \ \ / \
// \___\/\___\
//
//Command: xaw2verilog -intstyle C:/Users/rodriguj/Documents/proyectos_xilinx/ula_replacement_tests/test3/ipcore_dir/master_clk.xaw -st master_clk.v
//Design Name: master_clk
//Device: xc3s100e-4vq100
//
// Module master_clk
// Generated by Xilinx Architecture Wizard
// Written for synthesis tool: XST
// Period Jitter (unit interval) for block DCM_SP_INST = 0.04 UI
// Period Jitter (Peak-to-Peak) for block DCM_SP_INST = 3.20 ns
`timescale 1ns / 1ps
module master_clk(CLKIN_IN,
CLKDV_OUT,
CLKFX_OUT,
CLKIN_IBUFG_OUT,
CLK0_OUT);
input CLKIN_IN;
output CLKDV_OUT;
output CLKFX_OUT;
output CLKIN_IBUFG_OUT;
output CLK0_OUT;
wire CLKDV_BUF;
wire CLKFB_IN;
wire CLKFX_BUF;
wire CLKIN_IBUFG;
wire CLK0_BUF;
wire GND_BIT;
assign GND_BIT = 0;
assign CLKIN_IBUFG_OUT = CLKIN_IBUFG;
assign CLK0_OUT = CLKFB_IN;
BUFG CLKDV_BUFG_INST (.I(CLKDV_BUF),
.O(CLKDV_OUT));
BUFG CLKFX_BUFG_INST (.I(CLKFX_BUF),
.O(CLKFX_OUT));
IBUFG CLKIN_IBUFG_INST (.I(CLKIN_IN),
.O(CLKIN_IBUFG));
BUFG CLK0_BUFG_INST (.I(CLK0_BUF),
.O(CLKFB_IN));
DCM_SP #( .CLK_FEEDBACK("1X"), .CLKDV_DIVIDE(5.0), .CLKFX_DIVIDE(20),
.CLKFX_MULTIPLY(4), .CLKIN_DIVIDE_BY_2("FALSE"),
.CLKIN_PERIOD(20.000), .CLKOUT_PHASE_SHIFT("NONE"),
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), .DFS_FREQUENCY_MODE("LOW"),
.DLL_FREQUENCY_MODE("LOW"), .DUTY_CYCLE_CORRECTION("TRUE"),
.FACTORY_JF(16'hC080), .PHASE_SHIFT(0), .STARTUP_WAIT("FALSE") )
DCM_SP_INST (.CLKFB(CLKFB_IN),
.CLKIN(CLKIN_IBUFG),
.DSSEN(GND_BIT),
.PSCLK(GND_BIT),
.PSEN(GND_BIT),
.PSINCDEC(GND_BIT),
.RST(GND_BIT),
.CLKDV(CLKDV_BUF),
.CLKFX(CLKFX_BUF),
.CLKFX180(),
.CLK0(CLK0_BUF),
.CLK2X(),
.CLK2X180(),
.CLK90(),
.CLK180(),
.CLK270(),
.LOCKED(),
.PSDONE(),
.STATUS());
endmodule
|
//-----------------------------------------------------------------------------------------------------------------------------
//
// COPYRIGHT (C) 2011, VIPcore Group, Fudan University
//
// THIS FILE MAY NOT BE MODIFIED OR REDISTRIBUTED WITHOUT THE
// EXPRESSED WRITTEN CONSENT OF VIPcore Group
//
// VIPcore : http://soc.fudan.edu.cn/vip
// IP Owner : Yibo FAN
// Contact : [email protected]
//-----------------------------------------------------------------------------------------------------------------------------
// Filename : cabac_binari_cre.v
// Author : chewein
// Created : 2014-10-18
// Description : syntax element binarization
//-----------------------------------------------------------------------------------------------------------------------------
`include "enc_defines.v"
module cabac_binari_cre(
clk ,
rst_n ,
coded_flag_i ,
coded_symbol_i ,
go_param_i ,
ctx_pair_cre_0_o ,
ctx_pair_cre_1_o ,
ctx_pair_cre_2_o ,
ctx_pair_cre_3_o ,
ctx_pair_valid_num_o
);
//-----------------------------------------------------------------------------------------------------------------------------
//
// input and output signals declaration
//
//-----------------------------------------------------------------------------------------------------------------------------
input clk ;
input rst_n ;
input coded_flag_i ;
input [ 15:0 ] coded_symbol_i ;
input [ 2:0 ] go_param_i ; // maximum : 4
output [ 10:0 ] ctx_pair_cre_0_o ; // coeff_cnt_i = 5'd11
output [ 10:0 ] ctx_pair_cre_1_o ; // coeff_cnt_i = 5'd11
output [ 10:0 ] ctx_pair_cre_2_o ; // coeff_cnt_i = 5'd11
output [ 10:0 ] ctx_pair_cre_3_o ; // coeff_cnt_i = 5'd11
output [ 2:0 ] ctx_pair_valid_num_o ;
reg [ 10:0 ] ctx_pair_cre_0_o ;
reg [ 10:0 ] ctx_pair_cre_1_o ;
reg [ 10:0 ] ctx_pair_cre_2_o ;
reg [ 10:0 ] ctx_pair_cre_3_o ;
//-----------------------------------------------------------------------------------------------------------------------------
//
// calculation length1 , length2 ,bins1, bins2 : symbol <(3<<go_param_i) : coeff_cnt_i = 5'd8
//
//-----------------------------------------------------------------------------------------------------------------------------
wire symbol_lt_param_w ;
wire [ 3:0 ] cre_length_0_0_w ; // coeff_cnt_i = 5'd9
wire [ 3:0 ] cre_length_0_1_w ; // coeff_cnt_i = 5'd9
wire [ 10:0 ] cre_bins_0_0_w ; // coeff_cnt_i = 5'd9
reg [ 10:0 ] cre_bins_0_1_r ; // coeff_cnt_i = 5'd9
assign symbol_lt_param_w = (coded_symbol_i<(8'b0000011<<go_param_i));
assign cre_length_0_0_w = (coded_symbol_i>>go_param_i) + 1'b1 ;
assign cre_length_0_1_w = {1'b0,go_param_i } ;
assign cre_bins_0_0_w = (11'd1<<cre_length_0_0_w)-2'd2 ;
always @* begin
case(go_param_i)
3'd0 : cre_bins_0_1_r = 11'd0 ; // coded_symbol_i % 1
3'd1 : cre_bins_0_1_r = {6'b0,4'b0000,coded_symbol_i[0] } ; // coded_symbol_i % 2
3'd2 : cre_bins_0_1_r = {6'b0,3'b000 ,coded_symbol_i[1:0]} ; // coded_symbol_i % 4
3'd3 : cre_bins_0_1_r = {6'b0,2'b00 ,coded_symbol_i[2:0]} ; // coded_symbol_i % 8
3'd4 : cre_bins_0_1_r = {6'b0,1'b0 ,coded_symbol_i[3:0]} ; // coded_symbol_i % 16
default: cre_bins_0_1_r = 11'd0 ;
endcase
end
reg coded_flag_d1_r ;
reg symbol_lt_param_d1_r ;
reg [ 3:0 ] cre_length_0_0_d1_r ; // coeff_cnt_i = 5'd10
reg [ 3:0 ] cre_length_0_1_d1_r ; // coeff_cnt_i = 5'd10
reg [ 10:0 ] cre_bins_0_0_d1_r ; // coeff_cnt_i = 5'd10
reg [ 10:0 ] cre_bins_0_1_d1_r ; // coeff_cnt_i = 5'd10
reg [ 2:0 ] go_param_d1_r ;
// delay 1 cycle
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
coded_flag_d1_r <= 1'b0 ;
symbol_lt_param_d1_r <= 1'b0 ;
cre_length_0_0_d1_r <= 4'd0 ;
cre_length_0_1_d1_r <= 4'd0 ;
cre_bins_0_0_d1_r <= 11'd0 ;
cre_bins_0_1_d1_r <= 11'd0 ;
go_param_d1_r <= 3'd0 ;
end
else begin
coded_flag_d1_r <= coded_flag_i ;
symbol_lt_param_d1_r <= symbol_lt_param_w ;
cre_length_0_0_d1_r <= cre_length_0_0_w ;
cre_length_0_1_d1_r <= cre_length_0_1_w ;
cre_bins_0_0_d1_r <= cre_bins_0_0_w ;
cre_bins_0_1_d1_r <= cre_bins_0_1_r ;
go_param_d1_r <= go_param_i ;
end
end
//-----------------------------------------------------------------------------------------------------------------------------
//
// calculation length1 , length2 ,bins1, bins2 : symbol >=(3<<go_param_i) : coeff_cnt_i = 5'd8
//
//-----------------------------------------------------------------------------------------------------------------------------
wire [ 3:0 ] cre_length_1_0_w ; // coeff_cnt_i = 5'd10
wire [ 3:0 ] cre_length_1_1_w ; // coeff_cnt_i = 5'd10
wire [ 10:0 ] cre_bins_1_0_w ; // coeff_cnt_i = 5'd10
wire [ 10:0 ] cre_bins_1_1_w ; // coeff_cnt_i = 5'd10
wire [ 3:0 ] length_i ={1'b0,go_param_i} ;
wire [ 15:0 ] symbol_i =coded_symbol_i-(8'b00000011<<go_param_i);
wire [ 15:0 ] symbol_0_0_w , symbol_0_1_w ; // coeff_cnt_i = 5'd9
wire [ 15:0 ] symbol_0_2_w , symbol_0_3_w ; // coeff_cnt_i = 5'd9
wire [ 3:0 ] length_0_0_w , length_0_1_w ; // coeff_cnt_i = 5'd9
wire [ 3:0 ] length_0_2_w , length_0_3_w ; // coeff_cnt_i = 5'd9
reg [ 15:0 ] symbol_1_0_r ; // coeff_cnt_i = 5'd10
wire [ 15:0 ] symbol_1_1_w ; // coeff_cnt_i = 5'd10
wire [ 15:0 ] symbol_1_2_w , symbol_1_3_w ; // coeff_cnt_i = 5'd10
reg [ 3:0 ] length_1_0_r ; // coeff_cnt_i = 5'd10
wire [ 3:0 ] length_1_1_w ; // coeff_cnt_i = 5'd10
wire [ 3:0 ] length_1_2_w , length_1_3_w ; // coeff_cnt_i = 5'd10
assign symbol_0_0_w = (symbol_i >=(16'b1<<length_i ))? ( symbol_i - (16'b1<<length_i) ): symbol_i ;
assign length_0_0_w = (symbol_i >=(16'b1<<length_i ))? length_i + 4'd1 : length_i ;
assign symbol_0_1_w = (symbol_0_0_w>=(16'b1<<length_0_0_w))? ( symbol_0_0_w - ( 16'b1<<length_0_0_w)): symbol_0_0_w ;
assign length_0_1_w = (symbol_0_0_w>=(16'b1<<length_0_0_w))? length_0_0_w + 4'd1 : length_0_0_w ;
assign symbol_0_2_w = (symbol_0_1_w>=(16'b1<<length_0_1_w))? ( symbol_0_1_w - (16'b1<<length_0_1_w) ): symbol_0_1_w ;
assign length_0_2_w = (symbol_0_1_w>=(16'b1<<length_0_1_w))? length_0_1_w + 4'd1 : length_0_1_w ;
assign symbol_0_3_w = (symbol_0_2_w>=(16'b1<<length_0_2_w))? ( symbol_0_2_w - (16'b1<<length_0_2_w) ): symbol_0_2_w ;
assign length_0_3_w = (symbol_0_2_w>=(16'b1<<length_0_2_w))? length_0_2_w + 4'd1 : length_0_2_w ;
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
symbol_1_0_r <= 16'd0 ;
length_1_0_r <= 4'd0 ;
end
else if( (symbol_0_3_w>=(16'b1<<length_0_3_w) ) ) begin
symbol_1_0_r <= symbol_0_3_w - (16'b1<<length_0_3_w) ;
length_1_0_r <= length_0_3_w + 1'b1 ;
end
else begin
symbol_1_0_r <= symbol_0_3_w ;
length_1_0_r <= length_0_3_w ;
end
end
assign symbol_1_1_w = (symbol_1_0_r>=(16'b1<<length_1_0_r))? symbol_1_0_r - ( 16'b1<<length_1_0_r ) : symbol_1_0_r ;
assign length_1_1_w = (symbol_1_0_r>=(16'b1<<length_1_0_r))? length_1_0_r + 4'd1 : length_1_0_r ;
assign symbol_1_2_w = (symbol_1_1_w>=(16'b1<<length_1_1_w))? symbol_1_1_w - (16'b1<<length_1_1_w ) : symbol_1_1_w ;
assign length_1_2_w = (symbol_1_1_w>=(16'b1<<length_1_1_w))? length_1_1_w + 4'd1 : length_1_1_w ;
assign symbol_1_3_w = (symbol_1_2_w>=(16'b1<<length_1_2_w))? symbol_1_2_w - (16'b1<<length_1_2_w ) : symbol_1_2_w ;
assign length_1_3_w = (symbol_1_2_w>=(16'b1<<length_1_2_w))? length_1_2_w + 4'd1 : length_1_2_w ;
assign cre_length_1_0_w = 4'd4 + length_1_3_w - go_param_d1_r ; // coeff_cnt_i = 5'd9
assign cre_length_1_1_w = length_1_3_w ; // coeff_cnt_i = 5'd9
assign cre_bins_1_0_w = (11'd1<<cre_length_1_0_w)- 2'd2 ; // coeff_cnt_i = 5'd9
assign cre_bins_1_1_w = symbol_1_3_w[10:0] ; // coeff_cnt_i = 5'd9
//-----------------------------------------------------------------------------------------------------------------------------
//
// output signals
//
//-----------------------------------------------------------------------------------------------------------------------------
wire [3:0] length_0_d1_minus5_w = cre_length_0_0_d1_r-4'd5 ;
wire [3:0] length_1_d1_minus5_w = cre_length_0_1_d1_r-4'd5 ;
wire [3:0] length_2_d1_minus5_w = cre_length_1_0_w -4'd5 ;
wire [3:0] length_3_d1_minus5_w = cre_length_1_1_w -4'd5 ;
wire [1:0] coding_mdoe = {coded_flag_d1_r,!coded_flag_d1_r} ;
reg [2:0] ctx_pair_valid_num_r ;
// ctx_pair_valid_num_r
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
ctx_pair_valid_num_r <= 3'd0 ;
else if(coded_flag_d1_r)
ctx_pair_valid_num_r <= 3'd4 ;
else
ctx_pair_valid_num_r <= 3'd0 ;
end
// ctx_pair_valid_num_o
assign ctx_pair_valid_num_o = ctx_pair_valid_num_r ;
reg [ 4:0 ] length_total_r ;
reg [19:0 ] bins_total_r ;
wire [3:0] length_total_minus5_w = length_total_r-4'd5 ;
wire [3:0] length_total_minus10_w = length_total_r-4'd10 ;
wire [3:0] length_total_minus15_w = length_total_r-4'd15 ;
always @* begin
if(symbol_lt_param_d1_r) begin
length_total_r = cre_length_0_0_d1_r + cre_length_0_1_d1_r ;
bins_total_r = (cre_bins_0_0_d1_r<<cre_length_0_1_d1_r) + cre_bins_0_1_d1_r[9:0] ;
end
else begin
length_total_r = cre_length_1_0_w + cre_length_1_1_w ;
bins_total_r = (cre_bins_1_0_w<<cre_length_1_1_w) + cre_bins_1_1_w[9:0] ;
end
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
ctx_pair_cre_0_o <= {2'b01,1'b0,8'hff} ;
ctx_pair_cre_1_o <= {2'b01,1'b0,8'hff} ;
ctx_pair_cre_2_o <= {2'b01,1'b0,8'hff} ;
ctx_pair_cre_3_o <= {2'b01,1'b0,8'hff} ;
end
else if(length_total_r<5'd6) begin
ctx_pair_cre_0_o <= {coding_mdoe,1'b0,length_total_r[2:0],bins_total_r[4:0]} ;
ctx_pair_cre_1_o <= {2'b01,1'b0,8'hff} ;
ctx_pair_cre_2_o <= {2'b01,1'b0,8'hff} ;
ctx_pair_cre_3_o <= {2'b01,1'b0,8'hff} ;
end
else if(length_total_r<5'd11) begin
ctx_pair_cre_0_o <= {coding_mdoe,1'b0,length_total_minus5_w[2:0],bins_total_r[9:5]} ;
ctx_pair_cre_1_o <= {coding_mdoe,1'b0,3'd5 ,bins_total_r[4:0]} ;
ctx_pair_cre_2_o <= {2'b01,1'b0,8'hff} ;
ctx_pair_cre_3_o <= {2'b01,1'b0,8'hff} ;
end
else if(length_total_r<5'd16) begin
ctx_pair_cre_0_o <= {coding_mdoe,1'b0,length_total_minus10_w[2:0],bins_total_r[14:10]} ;
ctx_pair_cre_1_o <= {coding_mdoe,1'b0,3'd5 ,bins_total_r[ 9:5 ]} ;
ctx_pair_cre_2_o <= {coding_mdoe,1'b0,3'd5 ,bins_total_r[ 4:0 ]} ;
ctx_pair_cre_3_o <= {2'b01,1'b0,8'hff} ;
end
else begin
ctx_pair_cre_0_o <= {coding_mdoe,1'b0,length_total_minus15_w[2:0],bins_total_r[19:15]} ;
ctx_pair_cre_1_o <= {coding_mdoe,1'b0,3'd5 ,bins_total_r[14:10]} ;
ctx_pair_cre_2_o <= {coding_mdoe,1'b0,3'd5 ,bins_total_r[ 9:5 ]} ;
ctx_pair_cre_3_o <= {coding_mdoe,1'b0,3'd5 ,bins_total_r[ 4:0 ]} ;
end
end
/*
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
ctx_pair_cre_0_o <= 11'd0 ;
ctx_pair_cre_1_o <= 11'd0 ;
end
else if(symbol_lt_param_d1_r) begin
if(cre_length_0_0_d1_r<4'd6) begin
ctx_pair_cre_0_o <= {coding_mdoe,1'b0,cre_length_0_0_d1_r[2:0],cre_bins_0_0_d1_r[4:0] };
ctx_pair_cre_1_o <= {2'b01 ,1'b0,8'hff };
end
else begin
ctx_pair_cre_0_o <= {coding_mdoe,1'b0,length_0_d1_minus5_w[2:0],cre_bins_0_0_d1_r[9:5]};
ctx_pair_cre_1_o <= {coding_mdoe,1'b0,3'd5 ,cre_bins_0_0_d1_r[4:0]};
end
end
else begin
if(cre_length_1_0_w<4'd6) begin
ctx_pair_cre_0_o <= {coding_mdoe,1'b0,cre_length_1_0_w[2:0] ,cre_bins_1_0_w[4:0] };
ctx_pair_cre_1_o <= {2'b01 ,1'b0,8'hff };
end
else begin
ctx_pair_cre_0_o <= {coding_mdoe,1'b0,length_2_d1_minus5_w[2:0],cre_bins_1_0_w[9:5] };
ctx_pair_cre_1_o <= {coding_mdoe,1'b0,3'd5 ,cre_bins_1_0_w[4:0] };
end
end
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
ctx_pair_cre_2_o <= 11'd0 ;
ctx_pair_cre_3_o <= 11'd0 ;
end
else if(symbol_lt_param_d1_r) begin
if(cre_length_0_1_d1_r<4'd6) begin
ctx_pair_cre_2_o <= {coding_mdoe,1'b0,cre_length_0_1_d1_r[2:0],cre_bins_0_1_d1_r[4:0] };
ctx_pair_cre_3_o <= {2'b01 ,1'b0,8'hff };
end
else begin
ctx_pair_cre_2_o <= {coding_mdoe,1'b0,length_1_d1_minus5_w[2:0],cre_bins_0_1_d1_r[9:5]};
ctx_pair_cre_3_o <= {coding_mdoe,1'b0,3'd5 ,cre_bins_0_1_d1_r[4:0]};
end
end
else begin
if(cre_length_1_1_w<4'd6) begin
ctx_pair_cre_2_o <= {coding_mdoe,1'b0,cre_length_1_1_w[2:0] ,cre_bins_1_1_w[4:0] };
ctx_pair_cre_3_o <= {2'b01 ,1'b0,8'hff };
end
else begin
ctx_pair_cre_2_o <= {coding_mdoe,1'b0,length_3_d1_minus5_w[2:0],cre_bins_1_1_w[9:5] };
ctx_pair_cre_3_o <= {coding_mdoe,1'b0,3'd5 ,cre_bins_1_1_w[4:0] };
end
end
end
*/
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__UDP_DLATCH_PR_PP_PKG_S_SYMBOL_V
`define SKY130_FD_SC_LP__UDP_DLATCH_PR_PP_PKG_S_SYMBOL_V
/**
* udp_dlatch$PR_pp$PKG$s: D-latch, gated clear direct / gate active
* high (Q output UDP)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__udp_dlatch$PR_pp$PKG$s (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET ,
//# {{clocks|Clocking}}
input GATE ,
//# {{power|Power}}
input SLEEP_B,
input KAPWR ,
input VPWR ,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__UDP_DLATCH_PR_PP_PKG_S_SYMBOL_V
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: iobdg_1r2w_vec.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Module Name: iobdg_1r2w_vec
// Description: 1r2w bit vector implemented using FF's.
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
`include "sys.h" // system level definition file which contains the
// time scale definition
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
// Interface signal list declarations
////////////////////////////////////////////////////////////////////////
module iobdg_1r2w_vec (/*AUTOARG*/
// Outputs
dout, dout_vec,
// Inputs
clk, rst_l, tx_en, rd_a, wr1_a, wr2_a, din1, din2, wen1, wen2
);
parameter WIDTH = 32;
parameter INDEX = 5;
////////////////////////////////////////////////////////////////////////
// Signal declarations
////////////////////////////////////////////////////////////////////////
input clk;
input rst_l;
input tx_en;
input [INDEX-1:0] rd_a;
input [INDEX-1:0] wr1_a;
input [INDEX-1:0] wr2_a;
input din1;
input din2;
input wen1;
input wen2;
output dout;
output [WIDTH-1:0] dout_vec;
wire [INDEX-1:0] wr1_a_d1;
wire [INDEX-1:0] wr2_a_d1;
wire din1_d1;
wire din2_d1;
wire wen1_d1;
wire wen2_d1;
wire [WIDTH-1:0] wr1_a_dec_d1;
wire [WIDTH-1:0] wr2_a_dec_d1;
wire [WIDTH-1:0] wen1_dec_d1;
wire [WIDTH-1:0] wen2_dec_d1;
wire [WIDTH-1:0] vec;
reg [WIDTH-1:0] vec_next;
wire [INDEX-1:0] rd_a_d1;
wire [WIDTH-1:0] rd_a_dec_d1;
wire dout;
integer i;
////////////////////////////////////////////////////////////////////////
// Code starts here
////////////////////////////////////////////////////////////////////////
// Flop write address, write data and write enable
dff_ns #(INDEX) wr1_a_d1_ff (.din(wr1_a),
.clk(clk),
.q(wr1_a_d1));
dff_ns #(INDEX) wr2_a_d1_ff (.din(wr2_a),
.clk(clk),
.q(wr2_a_d1));
dff_ns #(1) din1_d1_ff (.din(din1),
.clk(clk),
.q(din1_d1));
dff_ns #(1) din2_d1_ff (.din(din2),
.clk(clk),
.q(din2_d1));
dff_ns #(1) wen1_d1_ff (.din(wen1),
.clk(clk),
.q(wen1_d1));
dff_ns #(1) wen2_d1_ff (.din(wen2),
.clk(clk),
.q(wen2_d1));
assign wr1_a_dec_d1 = 1'b1 << wr1_a_d1;
assign wr2_a_dec_d1 = 1'b1 << wr2_a_d1;
assign wen1_dec_d1 = {WIDTH{wen1_d1}} & wr1_a_dec_d1;
assign wen2_dec_d1 = {WIDTH{wen2_d1}} & wr2_a_dec_d1;
always @(/*AUTOSENSE*/din1_d1 or din2_d1 or rst_l or vec
or wen1_dec_d1 or wen2_dec_d1)
begin
for (i=0; i<WIDTH; i=i+1)
begin
vec_next[i] = ~rst_l ? 1'b0 :
wen1_dec_d1[i] ? din1_d1 :
wen2_dec_d1[i] ? din2_d1 :
vec[i];
end
end
// FF's for storage
dff_ns #(WIDTH) vec_ff (.din(vec_next),
.clk(clk),
.q(vec));
// Send vector to other clock domain
dffe_ns #(WIDTH) dout_vec_ff (.din(vec),
.en(tx_en),
.clk(clk),
.q(dout_vec));
// Flop read address
dff_ns #(INDEX) rd_a_d1_ff (.din(rd_a),
.clk(clk),
.q(rd_a_d1));
assign rd_a_dec_d1 = 1'b1 << rd_a_d1;
assign dout = |(vec & rd_a_dec_d1);
endmodule // iobdg_1r2w_vec
// Local Variables:
// verilog-auto-sense-defines-constant:t
// End:
|
/************************************************************************
buffer.v
Data buffer module
Domesday Duplicator - LaserDisc RF sampler
Copyright (C) 2018 Simon Inns
This file is part of Domesday Duplicator.
Domesday Duplicator is free software: you can redistribute it and/or
modify it under the terms of the GNU General Public License as
published by the Free Software Foundation, either version 3 of the
License, or (at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
Email: [email protected]
************************************************************************/
module buffer (
input nReset,
input writeClock,
input readClock,
input isReading,
input [9:0] dataIn,
output reg bufferOverflow,
output reg dataAvailable,
output [15:0] dataOut_16bit
);
// Convert 10 bit data out to 16-bit (unsigned and unscaled)
wire [9:0] dataOut_10bit;
assign dataOut_16bit[9:0] = dataOut_10bit;
assign dataOut_16bit[15:10] = 6'b0;
// FIFO buffer size in words
// Note: The size of this buffer must match the buffer size used
// by the FX3 (which is set to 8192 16-bit words per buffer) as this
// must match the size of the USB3 end-point which is 16Kbytes
//
localparam bufferSize = 14'd8191; // 0 - 8191 = 8192 words
// "Ping-pong" buffer storing 8192 10-bit words per buffer
reg currentWriteBuffer; // 0 = write to ping buffer read from pong,
// 1 = write to pong buffer read from ping
// Define various buffer signals and values
// Buffer signals (write clock sync'd)
wire pingAsyncClear_wr;
wire pongAsyncClear_wr;
wire pingEmptyFlag_wr;
wire pongEmptyFlag_wr;
wire [13:0] pingUsedWords_wr;
wire [13:0] pongUsedWords_wr;
// Buffer signals (read clock sync'd)
wire pingEmptyFlag_rd;
wire pongEmptyFlag_rd;
wire [13:0] pingUsedWords_rd;
wire [13:0] pongUsedWords_rd;
// Data out buses
wire [9:0] pingdataOut;
wire [9:0] pongdataOut;
// Define the ping buffer (0) - 8192 10-bit words
IPfifo pingBuffer (
.aclr(pingAsyncClear_wr),
.data(pingDataIn), // 10-bit [9:0]
.rdclk(readClock),
.rdreq(pingReadRequest),
.wrclk(writeClock),
.wrreq(pingWriteRequest),
.q(pingdataOut), // 10-bit [9:0]
.rdempty(pingEmptyFlag_rd),
.rdusedw(pingUsedWords_rd), // 14-bit [13:0]
.wrempty(pingEmptyFlag_wr),
.wrusedw(pingUsedWords_wr) // 14-bit [13:0]
);
// Define the pong buffer (1) - 8192 10-bit words
IPfifo pongBuffer (
.aclr(pongAsyncClear_wr),
.data(pongDataIn), // 10-bit [9:0]
.rdclk(readClock),
.rdreq(pongReadRequest),
.wrclk(writeClock),
.wrreq(pongWriteRequest),
.q(pongdataOut), // 10-bit [9:0]
.rdempty(pongEmptyFlag_rd),
.rdusedw(pongUsedWords_rd), // 14-bit [13:0]
.wrempty(pongEmptyFlag_wr),
.wrusedw(pongUsedWords_wr) // 14-bit [13:0]
);
// Route the control signals according to the currently selected write buffer
wire [9:0] pingDataIn;
wire [9:0] pongDataIn;
wire pingReadRequest;
wire pongReadRequest;
wire pingWriteRequest;
wire pongWriteRequest;
// if current write buffer = ping then send data to ping buffer
// else send data to pong buffer
assign pingDataIn = currentWriteBuffer ? 10'd0 : dataIn;
assign pongDataIn = currentWriteBuffer ? dataIn : 10'd0;
// if current write buffer = ping the dataOut_10bit = pong buffer else dataOut_10bit = pingBuffer
assign dataOut_10bit = currentWriteBuffer ? pingdataOut : pongdataOut;
// If current write buffer = ping then read from pong else read from ping
assign pingReadRequest = currentWriteBuffer ? isReading : 1'b0;
assign pongReadRequest = currentWriteBuffer ? 1'b0 : isReading;
// if current write buffer = ping then write to ping else write to pong
assign pingWriteRequest = currentWriteBuffer ? 1'b0 : 1'b1;
assign pongWriteRequest = currentWriteBuffer ? 1'b1 : 1'b0;
// Define registers for the async clear flags and map to registers
// Note: the async clear flag can cause the empty flag to glitch when
// asserted, so we have to sync it with the nReset signal to avoid
// issues on reset.
reg pingAsyncClear_reg;
reg pongAsyncClear_reg;
assign pingAsyncClear_wr = pingAsyncClear_reg | !nReset;
assign pongAsyncClear_wr = pongAsyncClear_reg | !nReset;
// Register to track activation of the overflow flag (0-1024 10-bit)
reg [9:0] bufferOverflowHold;
// FIFO Write-side logic (controls switching between ping and pong buffers)
always @ (posedge writeClock, negedge nReset) begin
if (!nReset) begin
// Clear all registers on reset
currentWriteBuffer <= 1'b0;
bufferOverflow <= 1'b0;
bufferOverflowHold <= 10'd0;
pingAsyncClear_reg <= 1'b0;
pongAsyncClear_reg <= 1'b0;
end else begin
// Which buffer is being written to?
if (currentWriteBuffer) begin
// Current write buffer is pong
// Is the pong buffer nearly full?
if (pongUsedWords_wr == bufferSize - 2) begin
// Check that the ping buffer has been emptied...
if (!pingEmptyFlag_wr) begin
// Flag an overflow error
bufferOverflow <= 1'b1;
// Set the ping buffer async clear (empty the ping buffer)
pingAsyncClear_reg <= 1'b1;
end
end
// Is the pong buffer 1 word from full?
if (pongUsedWords_wr == bufferSize - 1) begin
// Reset the ping buffer async clear
pingAsyncClear_reg <= 1'b0;
// Switch to the ping buffer
currentWriteBuffer <= 1'b0;
end
end else begin
// Current write buffer is ping
// Is the ping buffer nearly full?
if (pingUsedWords_wr == bufferSize - 2) begin
// Check that the pong buffer has been emptied...
if (!pongEmptyFlag_wr) begin
// Flag an overflow error
bufferOverflow <= 1'b1;
// Set the pong buffer async clear (empty the pong buffer)
pongAsyncClear_reg <= 1'b1;
end
end
// Is the ping buffer 1 word from full?
if (pingUsedWords_wr == bufferSize - 1) begin
// Reset the pong buffer async clear
pongAsyncClear_reg <= 1'b0;
// Switch to the pong buffer
currentWriteBuffer <= 1'b1;
end
end
// Track and clear the buffer overflow flag
// Note: This holds the error signal high
// for 1000 write clock cycles
if (bufferOverflow == 1'b1) begin
// Increment the hold counter
bufferOverflowHold <= bufferOverflowHold + 10'd1;
// If the hold clock-cycles is exceeded, clear the flag
if (bufferOverflowHold > 10'd1000) begin
bufferOverflow <= 1'b0;
end
end
end
end
// FIFO read-side logic
// Control the data available flag (on the read side)
// Note: This is responsible for setting the flag when
// data is available and clearing the flag once all
// the available data has been read.
always @ (posedge readClock, negedge nReset) begin
if (!nReset) begin
// On reset default to data unavailable
dataAvailable <= 1'b0;
end else begin
// Which buffer is being read from to?
if (currentWriteBuffer) begin
// Reading from ping buffer
// Is the ping buffer full?
if (pingUsedWords_rd == bufferSize) begin
dataAvailable <= 1'b1;
end else begin
// Is the ping buffer empty?
if (pingEmptyFlag_rd) begin
dataAvailable <= 1'b0;
end
end
end else begin
// Reading from pong buffer
// Is the pong buffer full?
if (pongUsedWords_rd == bufferSize) begin
dataAvailable <= 1'b1;
end else begin
// Is the pong buffer empty?
if (pongEmptyFlag_rd) begin
dataAvailable <= 1'b0;
end
end
end
end
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:06:45 03/31/2015
// Design Name:
// Module Name: Adder64
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Adder64(
input [63:0] A,
input [63:0] B,
input C0,
output [3:0] P,
output [3:0] G,
output [63:0] sum,
output SF,
output CF,
output OF,
output PF,
output ZF
);
wire[15:0] p,g;
wire[4:0] C;
wire[3:0] sf,cf,of,pf,zf;
pg_to_PG pgtoPG(p,g,P,G);
ParallelCarry4 PC(P,G,C0,C);
Adder16 a1(A[15:0],B[15:0],C[0],p[3:0],g[3:0],sum[15:0],sf[0],cf[0],of[0],pf[0],zf[0]),
a2(A[31:16],B[31:16],C[1],p[7:4],g[7:4],sum[31:16],sf[1],cf[1],of[1],pf[1],zf[1]),
a3(A[47:32],B[47:32],C[2],p[11:8],g[11:8],sum[47:32],sf[2],cf[2],of[2],pf[2],zf[2]),
a4(A[63:48],B[63:48],C[3],p[15:12],g[15:12],sum[63:48],sf[3],cf[3],of[3],pf[3],zf[3]);
assign SF=sf[3],
CF=C[4],
OF=of[3],
PF=^pf[3:0],
ZF= ~|(~zf[3:0]);
endmodule
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title : External PLL Interface.
// File : pll_intf.v
// Author : Jim Macleod
// Created : 30-Dec-2005
// RCS File : $Source:
// Status : $Id:
//
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
//
//
//
/////////////////////////////////////////////////////////////////////////////////
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ns / 10 ps
module pll_intf
(
input hclk,
input hresetn,
input p_update,
input [23:0] pll_params,
input m66_en,
input alt_pll_lock,
output reg sclk,
output reg sdat,
output reg sdat_oe,
output reg sclk_oe,
output reg shift_done,
output reg ext_pll_locked
);
// Power on reset register size.
`define POR_SIZE 8
parameter dev_adr = 7'h69,
low = 3'b0_00,
high = 3'b0_01,
sdata = 3'b0_10,
tri_state = 3'b1_01,
p_start_0 = 6'h0,
p_start_1 = 6'h1,
p_start_2 = 6'h2,
p_dat_0_0 = 6'h3,
p_dat_0_1 = 6'h4,
p_dat_0_2 = 6'h5,
p_dat_1_0 = 6'h6,
p_dat_1_1 = 6'h7,
p_dat_1_2 = 6'h8,
p_dat_2_0 = 6'h9,
p_dat_2_1 = 6'ha,
p_dat_2_2 = 6'hb,
p_dat_3_0 = 6'hc,
p_dat_3_1 = 6'hd,
p_dat_3_2 = 6'he,
p_dat_4_0 = 6'hf,
p_dat_4_1 = 6'h10,
p_dat_4_2 = 6'h11,
p_dat_5_0 = 6'h12,
p_dat_5_1 = 6'h13,
p_dat_5_2 = 6'h14,
p_dat_6_0 = 6'h15,
p_dat_6_1 = 6'h16,
p_dat_6_2 = 6'h17,
p_dat_7_0 = 6'h18,
p_dat_7_1 = 6'h19,
p_dat_7_2 = 6'h1a,
p_ack_0 = 6'h1b,
p_ack_1 = 6'h1c,
p_ack_2 = 6'h1d,
p_stop_0 = 6'h1e,
p_stop_1 = 6'h1f,
p_stop_2 = 6'h20;
/////////////////////////////////////////////////////////////////////////////////////
//
// The formula is:
// Fpll = Freq x (PT/QT)
// Where
// PT = (2 x (P + 3)) + PO
// And
// QT = Q + 2
// We have post scaler = 1/2
//
parameter
// MEM_P=10'h00D, MEM_Q=8'h01, MEM_LF=3'b010, MEM_P0=1'b0, MEM_POST=7'h4 // 100MHz.
// MEM_P=10'h013, MEM_Q=8'h03, MEM_LF=3'b100, MEM_P0=1'b0, MEM_POST=7'h3 // 110MHz.
// MEM_P=10'h014, MEM_Q=8'h03, MEM_LF=3'b100, MEM_P0=1'b0, MEM_POST=7'h3 // 115MHz.
// MEM_P=10'h015, MEM_Q=8'h03, MEM_LF=3'b100, MEM_P0=1'b0, MEM_POST=7'h3 // 120MHz.
// MEM_P=10'h007, MEM_Q=8'h00, MEM_LF=3'b100, MEM_P0=1'b0, MEM_POST=7'h3 // 125MHz.
// MEM_P=10'h017, MEM_Q=8'h03, MEM_LF=3'b100, MEM_P0=1'b0, MEM_POST=7'h3 // 130MHz.
// MEM_P=10'h082, MEM_Q=8'h17, MEM_LF=3'b100, MEM_P0=1'b0, MEM_POST=7'h3 // 133MHz.
MEM_P=10'h00F, MEM_Q=8'h03, MEM_LF=3'b010, MEM_P0=1'b0, MEM_POST=7'h2 // 135MHz.
// MEM_P=10'h035, MEM_Q=8'h0D, MEM_LF=3'b100, MEM_P0=1'b0, MEM_POST=7'h2 // 140MHz.
// MEM_P=10'h11B, MEM_Q=8'h49, MEM_LF=3'b100, MEM_P0=1'b0, MEM_POST=7'h2 // 143MHz.
// MEM_P=10'h037, MEM_Q=8'h0D, MEM_LF=3'b100, MEM_P0=1'b0, MEM_POST=7'h2 // 145MHz.
// MEM_P=10'h005, MEM_Q=8'h00, MEM_LF=3'b100, MEM_P0=1'b0, MEM_POST=7'h2 // 150MHz.
// MEM_P=10'h03B, MEM_Q=8'h0D, MEM_LF=3'b100, MEM_P0=1'b0, MEM_POST=7'h2 // 155MHz.
// MEM_P=10'h03D, MEM_Q=8'h0D, MEM_LF=3'b100, MEM_P0=1'b0, MEM_POST=7'h2 // 160MHz.
// MEM_P=10'h149, MEM_Q=8'h19, MEM_LF=3'b100, MEM_P0=1'b0, MEM_POST=7'h2 // 166MHz.
;
/////////////////////////////////////////////////////////////////////////////////////
reg [11:0] clkcnt;
reg [2:0] write_phase;
reg [5:0] p_cstate;
reg [7:0] shift_count;
reg load_shifter;
reg shift_enable;
reg [323:0] p_shifter;
reg [2:0] sdat_sel;
reg sclk_a;
reg sclk_en;
wire p0;
wire [3:0] preg;
wire [9:0] mreg;
wire [8:0] nreg;
reg [`POR_SIZE-1:0] por_reg;
reg [18:0] pll_counter;
reg po_reset;
reg reset_flag;
reg reset_flag_1;
reg reset_update;
reg por_flag;
reg clr_por;
reg alt_pll_lock_sync;
reg alt_pll_lock_3;
reg alt_pll_lock_2;
reg alt_pll_lock_1;
assign {p0, preg, mreg, nreg} = pll_params;
wire [2:0] LF = (mreg > 1043) ? 3'b100 :
(mreg > 834) ? 3'b011 :
(mreg > 626) ? 3'b010 :
(mreg > 231) ? 3'b001 : 3'b000;
//////////////////////////////////////////////////////////////////////////
// Syncronize the lock signal from the altera PLL
// This provides lock time for back door programing of
// the external PLL.
// Detects the ALT_PLL loss of lock.
//
always @(posedge hclk)
begin
alt_pll_lock_sync <= alt_pll_lock_3 & ~alt_pll_lock_2;
alt_pll_lock_3 <= alt_pll_lock_2;
alt_pll_lock_2 <= alt_pll_lock_1;
alt_pll_lock_1 <= alt_pll_lock;
end
//////////////////////////////////////////////////////////////////////////
//
//
//
//
//
always @(posedge hclk or negedge hresetn)
begin
if(!hresetn) pll_counter <= 19'h50000;
else if(shift_done) pll_counter <= 19'h50000;
else if(alt_pll_lock_sync) pll_counter <= 19'h50000;
else if(|pll_counter) pll_counter <= pll_counter - 19'h1;
end
always @(posedge hclk or negedge hresetn)
begin
if(!hresetn) ext_pll_locked <= 1'b0;
else if(p_update | reset_update | alt_pll_lock_sync) ext_pll_locked <= 1'b0;
else if(pll_counter == 19'h00001) ext_pll_locked <= 1'b1;
end
//////////////////////////////////////////////////////////////////////////
//
// Power on Reset.
//
always @(posedge hclk)
begin
if(~&por_reg)
begin
por_reg <= por_reg + `POR_SIZE'h1;
po_reset <= 1'b1;
end
else po_reset <= 1'b0;
end
//////////////////////////////////////////////////////////////////////////
//
// Generate clk divider
//
always @(posedge hclk)
begin
if(|clkcnt & |p_cstate) clkcnt <= clkcnt - 7'h1;
else if(m66_en)clkcnt <= 7'h38;
else clkcnt <= 7'h1c;
end
// generate clock enable signal
wire ena_edge = ~|clkcnt;
always @(posedge hclk)
begin
reset_update <= reset_flag_1 & ~reset_flag;
reset_flag_1 <= reset_flag;
reset_flag <= po_reset;
if(reset_flag_1 & ~reset_flag) por_flag <= 1'b1;
else if(clr_por) por_flag <= 1'b0;
end
//////////////////////////////////////////////////////////////////////////
//
// External PLL programing state machine.
//
always @(posedge hclk or negedge hresetn)
begin
if(!hresetn)
begin
p_cstate <= 6'h0;
load_shifter <= 1'b0;
shift_enable <= 1'b0;
sclk_a <= 1'b1;
shift_count <= 8'h0;
write_phase <= 3'b0;
shift_done <= 1'b0;
sclk_en <= 1'b0;
sdat_sel <= tri_state;
clr_por <= 1'b0;
end
else begin
load_shifter <= 1'b0;
shift_enable <= 1'b0;
shift_done <= 1'b0;
sdat_sel <= sdata;
sclk_en <= 1'b1;
clr_por <= 1'b0;
case(p_cstate)
p_start_0:
begin
sclk_a <= 1'b1;
if(p_update | reset_update)
begin
p_cstate <= p_start_1;
shift_count <= 8'h2;
load_shifter <= 1'b1;
end
else begin
p_cstate <= p_start_0;
sclk_en <= 1'b1;
sdat_sel <= tri_state;
end
end
p_start_1:
begin
sclk_a <= 1'b1;
sdat_sel <= low;
if(ena_edge) p_cstate <= p_start_2;
end
p_start_2:
begin
sclk_a <= 1'b0;
sdat_sel <= low;
if(ena_edge) p_cstate <= p_dat_0_0;
end
p_dat_0_0: begin sclk_a <= 1'b0; if(ena_edge) p_cstate <= p_dat_0_1; end
p_dat_0_1: begin sclk_a <= 1'b1; if(ena_edge) p_cstate <= p_dat_0_2; end
p_dat_0_2: begin sclk_a <= 1'b0; if(ena_edge) p_cstate <= p_dat_1_0; shift_enable <= 1'b1; end
p_dat_1_0: begin sclk_a <= 1'b0; if(ena_edge) p_cstate <= p_dat_1_1; end
p_dat_1_1: begin sclk_a <= 1'b1; if(ena_edge) p_cstate <= p_dat_1_2; end
p_dat_1_2: begin sclk_a <= 1'b0; if(ena_edge) p_cstate <= p_dat_2_0; shift_enable <= 1'b1; end
p_dat_2_0: begin sclk_a <= 1'b0; if(ena_edge) p_cstate <= p_dat_2_1; end
p_dat_2_1: begin sclk_a <= 1'b1; if(ena_edge) p_cstate <= p_dat_2_2; end
p_dat_2_2: begin sclk_a <= 1'b0; if(ena_edge) p_cstate <= p_dat_3_0; shift_enable <= 1'b1; end
p_dat_3_0: begin sclk_a <= 1'b0; if(ena_edge) p_cstate <= p_dat_3_1; end
p_dat_3_1: begin sclk_a <= 1'b1; if(ena_edge) p_cstate <= p_dat_3_2; end
p_dat_3_2: begin sclk_a <= 1'b0; if(ena_edge) p_cstate <= p_dat_4_0; shift_enable <= 1'b1; end
p_dat_4_0: begin sclk_a <= 1'b0; if(ena_edge) p_cstate <= p_dat_4_1; end
p_dat_4_1: begin sclk_a <= 1'b1; if(ena_edge) p_cstate <= p_dat_4_2; end
p_dat_4_2: begin sclk_a <= 1'b0; if(ena_edge) p_cstate <= p_dat_5_0; shift_enable <= 1'b1; end
p_dat_5_0: begin sclk_a <= 1'b0; if(ena_edge) p_cstate <= p_dat_5_1; end
p_dat_5_1: begin sclk_a <= 1'b1; if(ena_edge) p_cstate <= p_dat_5_2; end
p_dat_5_2: begin sclk_a <= 1'b0; if(ena_edge) p_cstate <= p_dat_6_0; shift_enable <= 1'b1; end
p_dat_6_0: begin sclk_a <= 1'b0; if(ena_edge) p_cstate <= p_dat_6_1; end
p_dat_6_1: begin sclk_a <= 1'b1; if(ena_edge) p_cstate <= p_dat_6_2; end
p_dat_6_2: begin sclk_a <= 1'b0; if(ena_edge) p_cstate <= p_dat_7_0; shift_enable <= 1'b1; end
p_dat_7_0: begin sclk_a <= 1'b0; if(ena_edge) p_cstate <= p_dat_7_1; end
p_dat_7_1: begin sclk_a <= 1'b1; if(ena_edge) p_cstate <= p_dat_7_2; end
p_dat_7_2: begin sclk_a <= 1'b0; if(ena_edge) p_cstate <= p_ack_0; shift_enable <= 1'b1; end
p_ack_0: begin
sclk_a <= 1'b0;
sdat_sel <= tri_state;
if(ena_edge) p_cstate <= p_ack_1;
end
p_ack_1: begin
sclk_a <= 1'b1;
sdat_sel <= tri_state;
if(ena_edge) p_cstate <= p_ack_2;
end
p_ack_2: begin
sclk_a <= 1'b0;
sdat_sel <= tri_state;
shift_enable <= 1'b1;
if(ena_edge && (|shift_count))
begin
p_cstate <= p_dat_0_0;
shift_count <= shift_count - 8'h1;
end
else if(ena_edge) p_cstate <= p_stop_0;
end
p_stop_0: begin
sclk_a <= 1'b0;
sdat_sel <= low;
if(ena_edge) p_cstate <= p_stop_1;
end
p_stop_1: begin
sclk_a <= 1'b1;
sdat_sel <= low;
if(ena_edge) p_cstate <= p_stop_2;
end
p_stop_2: begin
sclk_a <= 1'b1;
sdat_sel <= high;
casex({por_flag, ena_edge, write_phase})
5'bx_1_000:
begin
shift_count <= 8'h2;
p_cstate <= p_start_1;
write_phase <= 3'b001;
end
5'bx_1_001:
begin
shift_count <= 8'h5;
p_cstate <= p_start_1;
write_phase <= 3'b010;
end
5'bx_1_010:
begin
shift_count <= 8'h08;
p_cstate <= p_start_1;
write_phase <= 3'b011;
end
5'b1_1_011:
begin
shift_count <= 8'h2;
p_cstate <= p_start_1;
write_phase <= 3'b100;
end
5'b1_1_100:
begin
shift_count <= 8'h6;
p_cstate <= p_start_1;
write_phase <= 3'b101;
end
5'b1_1_101:
begin
shift_count <= 8'h4;
p_cstate <= p_start_1;
write_phase <= 3'b110;
end
5'b1_1_110, 5'b0_1_011:
begin
p_cstate <= p_start_0;
write_phase <= 3'b000;
shift_done <= 1'b1;
clr_por <= 1'b1;
end
default: p_cstate <= p_stop_2;
endcase
end
default:begin
p_cstate <= 6'h0;
load_shifter <= 1'b0;
shift_enable <= 1'b0;
sclk_a <= 1'b1;
shift_count <= 8'h0;
write_phase <= 5'b1;
shift_done <= 1'b0;
sdat_sel <= high;
clr_por <= 1'b0;
end
endcase
end
end
always @(posedge hclk or negedge hresetn) begin
if(!hresetn) begin
p_shifter <= 324'h0;
end else if(load_shifter) begin
// Turn off PLL Number 2 (write_phase 0).
p_shifter[323:317] <= dev_adr; // Device Address 7'h69.
p_shifter[316] <= 1'b0; // R/W, 0 = write.
p_shifter[315] <= 1'bz; // Ack bit from Slave.
p_shifter[314:307] <= 8'h13; // Start Address(0x13).
p_shifter[306] <= 1'bz; // Ack bit from Slave.
p_shifter[305:298] <= 8'h00; // {1'b0, PLL2_En, PLL2_LF[2:0], PLL2_PO, PLL2_P[9:8]}
p_shifter[297] <= 1'bz; // Ack bit from Slave.
// Turn off PLL Number 3 (write_phase 1).
p_shifter[296:290] <= dev_adr; // Device Address 7'h69.
p_shifter[289] <= 1'b0; // R/W, 0 = write.
p_shifter[288] <= 1'bz; // Ack bit from Slave.
p_shifter[287:280] <= 8'h16; // Start Address(0x16).
p_shifter[279] <= 1'bz; // Ack bit from Slave.
p_shifter[278:271] <= 8'h00; // {1'b0, PLL2_En, PLL2_LF[2:0], PLL2_PO, PLL2_P[9:8]}
p_shifter[270] <= 1'bz; // Ack bit from Slave.
// Program PLL 2 and 3 (write_phase 2).
p_shifter[269:263] <= dev_adr; // Device Address 7'h69.
p_shifter[262] <= 1'b0; // R/W, 0 = write.
p_shifter[261] <= 1'bz; // Ack bit from Slave.
p_shifter[260:253] <= 8'h08; // Start Address.
p_shifter[252] <= 1'bz; // Ack bit from Slave.
// 0x08 CLKA
p_shifter[251:244] <= {4'h0, preg}; // Pixel Clock Zero Post Scaler.
p_shifter[243] <= 1'bz; // Ack bit from Slave.
// 0x09 CLKA
p_shifter[242:235] <= {4'h0, preg}; // Pixel Clock Zero Post Scaler.
p_shifter[234] <= 1'bz; // Ack bit from Slave.
// 0x0A CLKB
p_shifter[233:226] <= 8'h1; // VGA Clock Zero Post Scaler.
p_shifter[225] <= 1'bz; // Ack bit from Slave.
// 0x0B CLKB
p_shifter[224:217] <= 8'h1; // VGA Clock Post Scaler.
p_shifter[216] <= 1'bz; // Ack bit from Slave.
// Program PLL 2 and 3 (write_phase 3).
p_shifter[215:209] <= dev_adr; // Device Address 7'h69.
p_shifter[208] <= 1'b0; // R/W, 0 = write.
p_shifter[207] <= 1'bz; // Ack bit from Slave.
p_shifter[206:199] <= 8'h11; // Start Address.
p_shifter[198] <= 1'bz; // Ack bit from Slave.
// 0x11
p_shifter[197:190] <= 8'h3; // PLL 2 Q, VGA CLock Pre Scale N
p_shifter[189] <= 1'bz; // Ack bit from Slave.
// 0x12
p_shifter[188:181] <= 8'h1; // PLL 2 P, VGA CLock Mult M
p_shifter[180] <= 1'bz; // Ack bit from Slave.
// 0x13
p_shifter[179:172] <= 8'h40; // {1'b0, PLL2_En, PLL2_LF[2:0], PLL2_PO, PLL2_P[9:8]}
p_shifter[171] <= 1'bz; // Ack bit from Slave.
// 0x14
p_shifter[170:163] <= nreg[7:0]; // PLL 3 Q, Pix/CRT One CLock Pre Scale N
p_shifter[162] <= 1'bz; // Ack bit from Slave.
// 0x15
p_shifter[161:154] <= mreg[7:0]; // PLL 3 P, Pix/CRT One CLock Mult M
p_shifter[153] <= 1'bz; // Ack bit from Slave.
// 0x16
p_shifter[152:145] <= {2'h1, LF, p0, mreg[9:8]}; // {1'b0, PLL3_En, PLL3_LF[2:0], PLL3_PO, PLL3_P[9:8]}
p_shifter[144] <= 1'bz; // Ack bit from Slave.
// 0x17
// p_shifter[143:136] <= 8'b000000_10; // {OscCap[5:0], OscDrv[1:0]}
p_shifter[143:136] <= 8'b000000_00; // {OscCap[5:0], OscDrv[1:0]}
p_shifter[135] <= 1'bz; // Ack bit from Slave.
/////////////////////////////////////////////////////////////////////////////////
//
// The remainder of the parameters only get programmed on POR.
//
// Turn off PLL Number 1 (write_phase 4).
p_shifter[134:128] <= dev_adr; // Device Address.
p_shifter[127] <= 1'b0; // R/W, 0 = write.
p_shifter[126] <= 1'bz; // Ack bit from Slave.
p_shifter[125:118] <= 8'h4B; // Start Address.
p_shifter[117] <= 1'bz; // Ack bit from Slave.
p_shifter[116:109] <= {1'b0, 1'b1, 6'h0}; // {1'b0, PLL1_En, PLL1_LF[2:0], PLL1_PO, PLL1_P[9:8]}
p_shifter[108] <= 1'bz; // Ack bit from Slave.
// Turn off PLL Number 1 (write_phase 5).
p_shifter[107:101] <= dev_adr; // Device Address.
p_shifter[100] <= 1'b0; // R/W, 0 = write.
p_shifter[99] <= 1'bz; // Ack bit from Slave.
p_shifter[98:91] <= 8'h0C; // Start Address.
p_shifter[90] <= 1'bz; // Ack bit from Slave.
// 0x0C CLKC
p_shifter[89:82] <= {1'b0, MEM_POST}; // Memory Clock Post Scaler.
p_shifter[81] <= 1'bz; // Ack bit from Slave.
// 0x0D CLKD
p_shifter[80:73] <= 8'h0; // Not Used, zero turns off the output.
p_shifter[72] <= 1'bz; // Ack bit from Slave.
// 0x0E CLKD, CLKC, CLKB, CLKA
p_shifter[71:64] <= 8'b00_01_10_11; // {ClkD_FS[2:1], ClkC_FS[2:1], ClkB_FS[2:1], ClkA_FS[2:1]}
p_shifter[63] <= 1'bz; // Ack bit from Slave.
// 0x0F
p_shifter[62:55] <= 8'b01_01_0_1_00; // Clk(C,X) AC Adj, Clk(A,B,D,E) AC Adj, PdnEn, Xbuf OE, ClkE Div.
p_shifter[54] <= 1'bz; // Ack bit from Slave.
// 0x10
p_shifter[53:46] <= 8'b01_01_01_01; // Clk(X) DC Adj, Clk(D,E) DC Adj, CLk(C) DC Adj, Clk(A,B) DC Adj.
p_shifter[45] <= 1'bz; // Ack bit from Slave.
// Program PLL 1 (write_phase 6).
p_shifter[044:038] <= dev_adr; // Device Address.
p_shifter[037] <= 1'b0; // R/W, 0 = write.
p_shifter[036] <= 1'bz; // Ack bit from Slave.
p_shifter[035:028] <= 8'h49; // Start Address.
p_shifter[027] <= 1'bz; // Ack bit from Slave.
// 0x49
p_shifter[026:019] <= MEM_Q; // PLL 1 Q, MC CLock Pre Scale N
p_shifter[018] <= 1'bz; // Ack bit from Slave.
// 0x4A
p_shifter[017:010] <= MEM_P[7:0]; // PLL 1 P, MC Zero CLock Mult M
p_shifter[009] <= 1'bz; // Ack bit from Slave.
// 0x4B
// {1'b0, PLL1_En, PLL1_LF[2:0], PLL1_PO, PLL1_P[9:8]}
p_shifter[008:001] <= {1'b0, 1'b1, MEM_LF, MEM_P0, MEM_P[9:8]};
// p_shifter[008:001] <= {1'b0, 1'b1, 3'b000, 1'b0, 2'b00}; // {1'b0, PLL1_En, PLL1_LF[2:0], PLL1_PO, PLL1_P[9:8]}
p_shifter[000] <= 1'bz; // Ack bit from Slave.
end
else if(shift_enable & ena_edge) p_shifter <= p_shifter << 1;
end
always @(posedge hclk)
begin
sdat <= (sdat_sel[1:0] == low) ? 1'b0 :
(sdat_sel[1:0] == high) ? 1'b1 : p_shifter[323];
sclk <= sclk_a;
sdat_oe <= ~sdat_sel[2];
sclk_oe <= sclk_en;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A311OI_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__A311OI_PP_BLACKBOX_V
/**
* a311oi: 3-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2 & A3) | B1 | C1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__a311oi (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__A311OI_PP_BLACKBOX_V
|
`timescale 1 ns / 1 ps
module PWM_v1_0 #
(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Parameters of Axi Slave Bus Interface PWM_AXI
parameter integer C_PWM_AXI_DATA_WIDTH = 32,
parameter integer C_PWM_AXI_ADDR_WIDTH = 4
)
(
// Users to add ports here
output wire pwm,
output wire interrupt,
// User ports ends
// Do not modify the ports beyond this line
// Ports of Axi Slave Bus Interface PWM_AXI
input wire pwm_axi_aclk,
input wire pwm_axi_aresetn,
input wire [C_PWM_AXI_ADDR_WIDTH-1 : 0] pwm_axi_awaddr,
input wire [2 : 0] pwm_axi_awprot,
input wire pwm_axi_awvalid,
output wire pwm_axi_awready,
input wire [C_PWM_AXI_DATA_WIDTH-1 : 0] pwm_axi_wdata,
input wire [(C_PWM_AXI_DATA_WIDTH/8)-1 : 0] pwm_axi_wstrb,
input wire pwm_axi_wvalid,
output wire pwm_axi_wready,
output wire [1 : 0] pwm_axi_bresp,
output wire pwm_axi_bvalid,
input wire pwm_axi_bready,
input wire [C_PWM_AXI_ADDR_WIDTH-1 : 0] pwm_axi_araddr,
input wire [2 : 0] pwm_axi_arprot,
input wire pwm_axi_arvalid,
output wire pwm_axi_arready,
output wire [C_PWM_AXI_DATA_WIDTH-1 : 0] pwm_axi_rdata,
output wire [1 : 0] pwm_axi_rresp,
output wire pwm_axi_rvalid,
input wire pwm_axi_rready
);
wire [C_PWM_AXI_DATA_WIDTH-1:0]duty_reg;
wire [C_PWM_AXI_DATA_WIDTH-1:0]period_reg;
wire [C_PWM_AXI_DATA_WIDTH-1:0]ctrl_reg;
wire [C_PWM_AXI_DATA_WIDTH-1:0]status_reg;
// Instantiation of Axi Bus Interface PWM_AXI
PWM_v1_0_PWM_AXI # (
.C_S_AXI_DATA_WIDTH(C_PWM_AXI_DATA_WIDTH),
.C_S_AXI_ADDR_WIDTH(C_PWM_AXI_ADDR_WIDTH)
) PWM_v1_0_PWM_AXI_inst (
.duty_reg_out(duty_reg),
.period_reg_out(period_reg),
.ctrl_reg_out(ctrl_reg),
.status_reg_out(status_reg),
.S_AXI_ACLK(pwm_axi_aclk),
.S_AXI_ARESETN(pwm_axi_aresetn),
.S_AXI_AWADDR(pwm_axi_awaddr),
.S_AXI_AWPROT(pwm_axi_awprot),
.S_AXI_AWVALID(pwm_axi_awvalid),
.S_AXI_AWREADY(pwm_axi_awready),
.S_AXI_WDATA(pwm_axi_wdata),
.S_AXI_WSTRB(pwm_axi_wstrb),
.S_AXI_WVALID(pwm_axi_wvalid),
.S_AXI_WREADY(pwm_axi_wready),
.S_AXI_BRESP(pwm_axi_bresp),
.S_AXI_BVALID(pwm_axi_bvalid),
.S_AXI_BREADY(pwm_axi_bready),
.S_AXI_ARADDR(pwm_axi_araddr),
.S_AXI_ARPROT(pwm_axi_arprot),
.S_AXI_ARVALID(pwm_axi_arvalid),
.S_AXI_ARREADY(pwm_axi_arready),
.S_AXI_RDATA(pwm_axi_rdata),
.S_AXI_RRESP(pwm_axi_rresp),
.S_AXI_RVALID(pwm_axi_rvalid),
.S_AXI_RREADY(pwm_axi_rready)
);
integer count=0;
integer max=4096;
reg enable=1'b0;
// Add user logic here
always@(posedge (pwm_axi_aclk))begin
if (ctrl_reg[0]==1)begin//Ctrl_reg 0 = enable
enable<=1;
max<=period_reg;
end
else
enable<=0;
if (ctrl_reg[1]==1)begin//Ctrl_reg 1 = hardware pwm
end
else begin
end
end
always@(posedge(pwm_axi_aclk))begin
if (enable==1'b1)begin
if (count<max)
count=count+1;
else
count=0;
end
else
count=0;
end
assign pwm = duty_reg < count ? 1'b1 : 1'b0;
assign interrupt = (count == max) ? 1'b1: 1'b0;
// User logic ends
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Sun Apr 09 08:27:07 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// C:/ZyboIP/examples/ov7670_hessian_split/ov7670_hessian_split.srcs/sources_1/bd/system/ip/system_vga_split_controller_0_0/system_vga_split_controller_0_0_sim_netlist.v
// Design : system_vga_split_controller_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "system_vga_split_controller_0_0,vga_split_controller,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "vga_split_controller,Vivado 2016.4" *)
(* NotValidForBitStream *)
module system_vga_split_controller_0_0
(rgb_0,
rgb_1,
clock,
hsync,
rgb);
input [15:0]rgb_0;
input [15:0]rgb_1;
(* x_interface_info = "xilinx.com:signal:clock:1.0 clock CLK" *) input clock;
input hsync;
output [15:0]rgb;
wire clock;
wire hsync;
wire [15:0]rgb;
wire [15:0]rgb_0;
wire [15:0]rgb_1;
system_vga_split_controller_0_0_vga_split_controller U0
(.clock(clock),
.hsync(hsync),
.rgb(rgb),
.rgb_0(rgb_0),
.rgb_1(rgb_1));
endmodule
(* ORIG_REF_NAME = "vga_split_controller" *)
module system_vga_split_controller_0_0_vga_split_controller
(rgb,
clock,
hsync,
rgb_0,
rgb_1);
output [15:0]rgb;
input clock;
input hsync;
input [15:0]rgb_0;
input [15:0]rgb_1;
wire clock;
wire \counter[0]_i_2_n_0 ;
wire \counter[0]_i_3_n_0 ;
wire \counter[0]_i_4_n_0 ;
wire \counter[0]_i_5_n_0 ;
wire \counter[12]_i_2_n_0 ;
wire \counter[12]_i_3_n_0 ;
wire \counter[12]_i_4_n_0 ;
wire \counter[12]_i_5_n_0 ;
wire \counter[16]_i_2_n_0 ;
wire \counter[16]_i_3_n_0 ;
wire \counter[16]_i_4_n_0 ;
wire \counter[16]_i_5_n_0 ;
wire \counter[20]_i_2_n_0 ;
wire \counter[20]_i_3_n_0 ;
wire \counter[20]_i_4_n_0 ;
wire \counter[20]_i_5_n_0 ;
wire \counter[24]_i_2_n_0 ;
wire \counter[24]_i_3_n_0 ;
wire \counter[24]_i_4_n_0 ;
wire \counter[24]_i_5_n_0 ;
wire \counter[28]_i_2_n_0 ;
wire \counter[28]_i_3_n_0 ;
wire \counter[28]_i_4_n_0 ;
wire \counter[28]_i_5_n_0 ;
wire \counter[4]_i_2_n_0 ;
wire \counter[4]_i_3_n_0 ;
wire \counter[4]_i_4_n_0 ;
wire \counter[4]_i_5_n_0 ;
wire \counter[8]_i_2_n_0 ;
wire \counter[8]_i_3_n_0 ;
wire \counter[8]_i_4_n_0 ;
wire \counter[8]_i_5_n_0 ;
wire [31:6]counter_reg;
wire \counter_reg[0]_i_1_n_0 ;
wire \counter_reg[0]_i_1_n_1 ;
wire \counter_reg[0]_i_1_n_2 ;
wire \counter_reg[0]_i_1_n_3 ;
wire \counter_reg[0]_i_1_n_4 ;
wire \counter_reg[0]_i_1_n_5 ;
wire \counter_reg[0]_i_1_n_6 ;
wire \counter_reg[0]_i_1_n_7 ;
wire \counter_reg[12]_i_1_n_0 ;
wire \counter_reg[12]_i_1_n_1 ;
wire \counter_reg[12]_i_1_n_2 ;
wire \counter_reg[12]_i_1_n_3 ;
wire \counter_reg[12]_i_1_n_4 ;
wire \counter_reg[12]_i_1_n_5 ;
wire \counter_reg[12]_i_1_n_6 ;
wire \counter_reg[12]_i_1_n_7 ;
wire \counter_reg[16]_i_1_n_0 ;
wire \counter_reg[16]_i_1_n_1 ;
wire \counter_reg[16]_i_1_n_2 ;
wire \counter_reg[16]_i_1_n_3 ;
wire \counter_reg[16]_i_1_n_4 ;
wire \counter_reg[16]_i_1_n_5 ;
wire \counter_reg[16]_i_1_n_6 ;
wire \counter_reg[16]_i_1_n_7 ;
wire \counter_reg[20]_i_1_n_0 ;
wire \counter_reg[20]_i_1_n_1 ;
wire \counter_reg[20]_i_1_n_2 ;
wire \counter_reg[20]_i_1_n_3 ;
wire \counter_reg[20]_i_1_n_4 ;
wire \counter_reg[20]_i_1_n_5 ;
wire \counter_reg[20]_i_1_n_6 ;
wire \counter_reg[20]_i_1_n_7 ;
wire \counter_reg[24]_i_1_n_0 ;
wire \counter_reg[24]_i_1_n_1 ;
wire \counter_reg[24]_i_1_n_2 ;
wire \counter_reg[24]_i_1_n_3 ;
wire \counter_reg[24]_i_1_n_4 ;
wire \counter_reg[24]_i_1_n_5 ;
wire \counter_reg[24]_i_1_n_6 ;
wire \counter_reg[24]_i_1_n_7 ;
wire \counter_reg[28]_i_1_n_1 ;
wire \counter_reg[28]_i_1_n_2 ;
wire \counter_reg[28]_i_1_n_3 ;
wire \counter_reg[28]_i_1_n_4 ;
wire \counter_reg[28]_i_1_n_5 ;
wire \counter_reg[28]_i_1_n_6 ;
wire \counter_reg[28]_i_1_n_7 ;
wire \counter_reg[4]_i_1_n_0 ;
wire \counter_reg[4]_i_1_n_1 ;
wire \counter_reg[4]_i_1_n_2 ;
wire \counter_reg[4]_i_1_n_3 ;
wire \counter_reg[4]_i_1_n_4 ;
wire \counter_reg[4]_i_1_n_5 ;
wire \counter_reg[4]_i_1_n_6 ;
wire \counter_reg[4]_i_1_n_7 ;
wire \counter_reg[8]_i_1_n_0 ;
wire \counter_reg[8]_i_1_n_1 ;
wire \counter_reg[8]_i_1_n_2 ;
wire \counter_reg[8]_i_1_n_3 ;
wire \counter_reg[8]_i_1_n_4 ;
wire \counter_reg[8]_i_1_n_5 ;
wire \counter_reg[8]_i_1_n_6 ;
wire \counter_reg[8]_i_1_n_7 ;
wire \counter_reg_n_0_[0] ;
wire \counter_reg_n_0_[1] ;
wire \counter_reg_n_0_[2] ;
wire \counter_reg_n_0_[3] ;
wire \counter_reg_n_0_[4] ;
wire \counter_reg_n_0_[5] ;
wire hsync;
wire p_0_in;
wire [15:0]p_1_in;
wire [15:0]rgb;
wire rgb1;
wire rgb1_carry__0_i_1_n_0;
wire rgb1_carry__0_i_2_n_0;
wire rgb1_carry__0_i_3_n_0;
wire rgb1_carry__0_i_4_n_0;
wire rgb1_carry__0_n_0;
wire rgb1_carry__0_n_1;
wire rgb1_carry__0_n_2;
wire rgb1_carry__0_n_3;
wire rgb1_carry__1_i_1_n_0;
wire rgb1_carry__1_i_2_n_0;
wire rgb1_carry__1_i_3_n_0;
wire rgb1_carry__1_i_4_n_0;
wire rgb1_carry__1_n_0;
wire rgb1_carry__1_n_1;
wire rgb1_carry__1_n_2;
wire rgb1_carry__1_n_3;
wire rgb1_carry__2_i_1_n_0;
wire rgb1_carry_i_1_n_0;
wire rgb1_carry_i_2_n_0;
wire rgb1_carry_i_3_n_0;
wire rgb1_carry_i_4_n_0;
wire rgb1_carry_i_5_n_0;
wire rgb1_carry_i_6_n_0;
wire rgb1_carry_n_0;
wire rgb1_carry_n_1;
wire rgb1_carry_n_2;
wire rgb1_carry_n_3;
wire [15:0]rgb_0;
wire [15:0]rgb_1;
wire [3:3]\NLW_counter_reg[28]_i_1_CO_UNCONNECTED ;
wire [3:0]NLW_rgb1_carry_O_UNCONNECTED;
wire [3:0]NLW_rgb1_carry__0_O_UNCONNECTED;
wire [3:0]NLW_rgb1_carry__1_O_UNCONNECTED;
wire [3:1]NLW_rgb1_carry__2_CO_UNCONNECTED;
wire [3:0]NLW_rgb1_carry__2_O_UNCONNECTED;
LUT1 #(
.INIT(2'h2))
\counter[0]_i_2
(.I0(\counter_reg_n_0_[3] ),
.O(\counter[0]_i_2_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[0]_i_3
(.I0(\counter_reg_n_0_[2] ),
.O(\counter[0]_i_3_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[0]_i_4
(.I0(\counter_reg_n_0_[1] ),
.O(\counter[0]_i_4_n_0 ));
LUT1 #(
.INIT(2'h1))
\counter[0]_i_5
(.I0(\counter_reg_n_0_[0] ),
.O(\counter[0]_i_5_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[12]_i_2
(.I0(counter_reg[15]),
.O(\counter[12]_i_2_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[12]_i_3
(.I0(counter_reg[14]),
.O(\counter[12]_i_3_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[12]_i_4
(.I0(counter_reg[13]),
.O(\counter[12]_i_4_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[12]_i_5
(.I0(counter_reg[12]),
.O(\counter[12]_i_5_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[16]_i_2
(.I0(counter_reg[19]),
.O(\counter[16]_i_2_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[16]_i_3
(.I0(counter_reg[18]),
.O(\counter[16]_i_3_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[16]_i_4
(.I0(counter_reg[17]),
.O(\counter[16]_i_4_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[16]_i_5
(.I0(counter_reg[16]),
.O(\counter[16]_i_5_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[20]_i_2
(.I0(counter_reg[23]),
.O(\counter[20]_i_2_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[20]_i_3
(.I0(counter_reg[22]),
.O(\counter[20]_i_3_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[20]_i_4
(.I0(counter_reg[21]),
.O(\counter[20]_i_4_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[20]_i_5
(.I0(counter_reg[20]),
.O(\counter[20]_i_5_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[24]_i_2
(.I0(counter_reg[27]),
.O(\counter[24]_i_2_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[24]_i_3
(.I0(counter_reg[26]),
.O(\counter[24]_i_3_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[24]_i_4
(.I0(counter_reg[25]),
.O(\counter[24]_i_4_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[24]_i_5
(.I0(counter_reg[24]),
.O(\counter[24]_i_5_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[28]_i_2
(.I0(counter_reg[31]),
.O(\counter[28]_i_2_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[28]_i_3
(.I0(counter_reg[30]),
.O(\counter[28]_i_3_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[28]_i_4
(.I0(counter_reg[29]),
.O(\counter[28]_i_4_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[28]_i_5
(.I0(counter_reg[28]),
.O(\counter[28]_i_5_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[4]_i_2
(.I0(counter_reg[7]),
.O(\counter[4]_i_2_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[4]_i_3
(.I0(counter_reg[6]),
.O(\counter[4]_i_3_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[4]_i_4
(.I0(\counter_reg_n_0_[5] ),
.O(\counter[4]_i_4_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[4]_i_5
(.I0(\counter_reg_n_0_[4] ),
.O(\counter[4]_i_5_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[8]_i_2
(.I0(counter_reg[11]),
.O(\counter[8]_i_2_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[8]_i_3
(.I0(counter_reg[10]),
.O(\counter[8]_i_3_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[8]_i_4
(.I0(counter_reg[9]),
.O(\counter[8]_i_4_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[8]_i_5
(.I0(counter_reg[8]),
.O(\counter[8]_i_5_n_0 ));
FDRE #(
.INIT(1'b0))
\counter_reg[0]
(.C(clock),
.CE(1'b1),
.D(\counter_reg[0]_i_1_n_7 ),
.Q(\counter_reg_n_0_[0] ),
.R(hsync));
CARRY4 \counter_reg[0]_i_1
(.CI(1'b0),
.CO({\counter_reg[0]_i_1_n_0 ,\counter_reg[0]_i_1_n_1 ,\counter_reg[0]_i_1_n_2 ,\counter_reg[0]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b1}),
.O({\counter_reg[0]_i_1_n_4 ,\counter_reg[0]_i_1_n_5 ,\counter_reg[0]_i_1_n_6 ,\counter_reg[0]_i_1_n_7 }),
.S({\counter[0]_i_2_n_0 ,\counter[0]_i_3_n_0 ,\counter[0]_i_4_n_0 ,\counter[0]_i_5_n_0 }));
FDRE #(
.INIT(1'b0))
\counter_reg[10]
(.C(clock),
.CE(1'b1),
.D(\counter_reg[8]_i_1_n_5 ),
.Q(counter_reg[10]),
.R(hsync));
FDRE #(
.INIT(1'b0))
\counter_reg[11]
(.C(clock),
.CE(1'b1),
.D(\counter_reg[8]_i_1_n_4 ),
.Q(counter_reg[11]),
.R(hsync));
FDRE #(
.INIT(1'b0))
\counter_reg[12]
(.C(clock),
.CE(1'b1),
.D(\counter_reg[12]_i_1_n_7 ),
.Q(counter_reg[12]),
.R(hsync));
CARRY4 \counter_reg[12]_i_1
(.CI(\counter_reg[8]_i_1_n_0 ),
.CO({\counter_reg[12]_i_1_n_0 ,\counter_reg[12]_i_1_n_1 ,\counter_reg[12]_i_1_n_2 ,\counter_reg[12]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\counter_reg[12]_i_1_n_4 ,\counter_reg[12]_i_1_n_5 ,\counter_reg[12]_i_1_n_6 ,\counter_reg[12]_i_1_n_7 }),
.S({\counter[12]_i_2_n_0 ,\counter[12]_i_3_n_0 ,\counter[12]_i_4_n_0 ,\counter[12]_i_5_n_0 }));
FDRE #(
.INIT(1'b0))
\counter_reg[13]
(.C(clock),
.CE(1'b1),
.D(\counter_reg[12]_i_1_n_6 ),
.Q(counter_reg[13]),
.R(hsync));
FDRE #(
.INIT(1'b0))
\counter_reg[14]
(.C(clock),
.CE(1'b1),
.D(\counter_reg[12]_i_1_n_5 ),
.Q(counter_reg[14]),
.R(hsync));
FDRE #(
.INIT(1'b0))
\counter_reg[15]
(.C(clock),
.CE(1'b1),
.D(\counter_reg[12]_i_1_n_4 ),
.Q(counter_reg[15]),
.R(hsync));
FDRE #(
.INIT(1'b0))
\counter_reg[16]
(.C(clock),
.CE(1'b1),
.D(\counter_reg[16]_i_1_n_7 ),
.Q(counter_reg[16]),
.R(hsync));
CARRY4 \counter_reg[16]_i_1
(.CI(\counter_reg[12]_i_1_n_0 ),
.CO({\counter_reg[16]_i_1_n_0 ,\counter_reg[16]_i_1_n_1 ,\counter_reg[16]_i_1_n_2 ,\counter_reg[16]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\counter_reg[16]_i_1_n_4 ,\counter_reg[16]_i_1_n_5 ,\counter_reg[16]_i_1_n_6 ,\counter_reg[16]_i_1_n_7 }),
.S({\counter[16]_i_2_n_0 ,\counter[16]_i_3_n_0 ,\counter[16]_i_4_n_0 ,\counter[16]_i_5_n_0 }));
FDRE #(
.INIT(1'b0))
\counter_reg[17]
(.C(clock),
.CE(1'b1),
.D(\counter_reg[16]_i_1_n_6 ),
.Q(counter_reg[17]),
.R(hsync));
FDRE #(
.INIT(1'b0))
\counter_reg[18]
(.C(clock),
.CE(1'b1),
.D(\counter_reg[16]_i_1_n_5 ),
.Q(counter_reg[18]),
.R(hsync));
FDRE #(
.INIT(1'b0))
\counter_reg[19]
(.C(clock),
.CE(1'b1),
.D(\counter_reg[16]_i_1_n_4 ),
.Q(counter_reg[19]),
.R(hsync));
FDRE #(
.INIT(1'b0))
\counter_reg[1]
(.C(clock),
.CE(1'b1),
.D(\counter_reg[0]_i_1_n_6 ),
.Q(\counter_reg_n_0_[1] ),
.R(hsync));
FDRE #(
.INIT(1'b0))
\counter_reg[20]
(.C(clock),
.CE(1'b1),
.D(\counter_reg[20]_i_1_n_7 ),
.Q(counter_reg[20]),
.R(hsync));
CARRY4 \counter_reg[20]_i_1
(.CI(\counter_reg[16]_i_1_n_0 ),
.CO({\counter_reg[20]_i_1_n_0 ,\counter_reg[20]_i_1_n_1 ,\counter_reg[20]_i_1_n_2 ,\counter_reg[20]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\counter_reg[20]_i_1_n_4 ,\counter_reg[20]_i_1_n_5 ,\counter_reg[20]_i_1_n_6 ,\counter_reg[20]_i_1_n_7 }),
.S({\counter[20]_i_2_n_0 ,\counter[20]_i_3_n_0 ,\counter[20]_i_4_n_0 ,\counter[20]_i_5_n_0 }));
FDRE #(
.INIT(1'b0))
\counter_reg[21]
(.C(clock),
.CE(1'b1),
.D(\counter_reg[20]_i_1_n_6 ),
.Q(counter_reg[21]),
.R(hsync));
FDRE #(
.INIT(1'b0))
\counter_reg[22]
(.C(clock),
.CE(1'b1),
.D(\counter_reg[20]_i_1_n_5 ),
.Q(counter_reg[22]),
.R(hsync));
FDRE #(
.INIT(1'b0))
\counter_reg[23]
(.C(clock),
.CE(1'b1),
.D(\counter_reg[20]_i_1_n_4 ),
.Q(counter_reg[23]),
.R(hsync));
FDRE #(
.INIT(1'b0))
\counter_reg[24]
(.C(clock),
.CE(1'b1),
.D(\counter_reg[24]_i_1_n_7 ),
.Q(counter_reg[24]),
.R(hsync));
CARRY4 \counter_reg[24]_i_1
(.CI(\counter_reg[20]_i_1_n_0 ),
.CO({\counter_reg[24]_i_1_n_0 ,\counter_reg[24]_i_1_n_1 ,\counter_reg[24]_i_1_n_2 ,\counter_reg[24]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\counter_reg[24]_i_1_n_4 ,\counter_reg[24]_i_1_n_5 ,\counter_reg[24]_i_1_n_6 ,\counter_reg[24]_i_1_n_7 }),
.S({\counter[24]_i_2_n_0 ,\counter[24]_i_3_n_0 ,\counter[24]_i_4_n_0 ,\counter[24]_i_5_n_0 }));
FDRE #(
.INIT(1'b0))
\counter_reg[25]
(.C(clock),
.CE(1'b1),
.D(\counter_reg[24]_i_1_n_6 ),
.Q(counter_reg[25]),
.R(hsync));
FDRE #(
.INIT(1'b0))
\counter_reg[26]
(.C(clock),
.CE(1'b1),
.D(\counter_reg[24]_i_1_n_5 ),
.Q(counter_reg[26]),
.R(hsync));
FDRE #(
.INIT(1'b0))
\counter_reg[27]
(.C(clock),
.CE(1'b1),
.D(\counter_reg[24]_i_1_n_4 ),
.Q(counter_reg[27]),
.R(hsync));
FDRE #(
.INIT(1'b0))
\counter_reg[28]
(.C(clock),
.CE(1'b1),
.D(\counter_reg[28]_i_1_n_7 ),
.Q(counter_reg[28]),
.R(hsync));
CARRY4 \counter_reg[28]_i_1
(.CI(\counter_reg[24]_i_1_n_0 ),
.CO({\NLW_counter_reg[28]_i_1_CO_UNCONNECTED [3],\counter_reg[28]_i_1_n_1 ,\counter_reg[28]_i_1_n_2 ,\counter_reg[28]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\counter_reg[28]_i_1_n_4 ,\counter_reg[28]_i_1_n_5 ,\counter_reg[28]_i_1_n_6 ,\counter_reg[28]_i_1_n_7 }),
.S({\counter[28]_i_2_n_0 ,\counter[28]_i_3_n_0 ,\counter[28]_i_4_n_0 ,\counter[28]_i_5_n_0 }));
FDRE #(
.INIT(1'b0))
\counter_reg[29]
(.C(clock),
.CE(1'b1),
.D(\counter_reg[28]_i_1_n_6 ),
.Q(counter_reg[29]),
.R(hsync));
FDRE #(
.INIT(1'b0))
\counter_reg[2]
(.C(clock),
.CE(1'b1),
.D(\counter_reg[0]_i_1_n_5 ),
.Q(\counter_reg_n_0_[2] ),
.R(hsync));
FDRE #(
.INIT(1'b0))
\counter_reg[30]
(.C(clock),
.CE(1'b1),
.D(\counter_reg[28]_i_1_n_5 ),
.Q(counter_reg[30]),
.R(hsync));
FDRE #(
.INIT(1'b0))
\counter_reg[31]
(.C(clock),
.CE(1'b1),
.D(\counter_reg[28]_i_1_n_4 ),
.Q(counter_reg[31]),
.R(hsync));
FDRE #(
.INIT(1'b0))
\counter_reg[3]
(.C(clock),
.CE(1'b1),
.D(\counter_reg[0]_i_1_n_4 ),
.Q(\counter_reg_n_0_[3] ),
.R(hsync));
FDRE #(
.INIT(1'b0))
\counter_reg[4]
(.C(clock),
.CE(1'b1),
.D(\counter_reg[4]_i_1_n_7 ),
.Q(\counter_reg_n_0_[4] ),
.R(hsync));
CARRY4 \counter_reg[4]_i_1
(.CI(\counter_reg[0]_i_1_n_0 ),
.CO({\counter_reg[4]_i_1_n_0 ,\counter_reg[4]_i_1_n_1 ,\counter_reg[4]_i_1_n_2 ,\counter_reg[4]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\counter_reg[4]_i_1_n_4 ,\counter_reg[4]_i_1_n_5 ,\counter_reg[4]_i_1_n_6 ,\counter_reg[4]_i_1_n_7 }),
.S({\counter[4]_i_2_n_0 ,\counter[4]_i_3_n_0 ,\counter[4]_i_4_n_0 ,\counter[4]_i_5_n_0 }));
FDRE #(
.INIT(1'b0))
\counter_reg[5]
(.C(clock),
.CE(1'b1),
.D(\counter_reg[4]_i_1_n_6 ),
.Q(\counter_reg_n_0_[5] ),
.R(hsync));
FDRE #(
.INIT(1'b0))
\counter_reg[6]
(.C(clock),
.CE(1'b1),
.D(\counter_reg[4]_i_1_n_5 ),
.Q(counter_reg[6]),
.R(hsync));
FDRE #(
.INIT(1'b0))
\counter_reg[7]
(.C(clock),
.CE(1'b1),
.D(\counter_reg[4]_i_1_n_4 ),
.Q(counter_reg[7]),
.R(hsync));
FDRE #(
.INIT(1'b0))
\counter_reg[8]
(.C(clock),
.CE(1'b1),
.D(\counter_reg[8]_i_1_n_7 ),
.Q(counter_reg[8]),
.R(hsync));
CARRY4 \counter_reg[8]_i_1
(.CI(\counter_reg[4]_i_1_n_0 ),
.CO({\counter_reg[8]_i_1_n_0 ,\counter_reg[8]_i_1_n_1 ,\counter_reg[8]_i_1_n_2 ,\counter_reg[8]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\counter_reg[8]_i_1_n_4 ,\counter_reg[8]_i_1_n_5 ,\counter_reg[8]_i_1_n_6 ,\counter_reg[8]_i_1_n_7 }),
.S({\counter[8]_i_2_n_0 ,\counter[8]_i_3_n_0 ,\counter[8]_i_4_n_0 ,\counter[8]_i_5_n_0 }));
FDRE #(
.INIT(1'b0))
\counter_reg[9]
(.C(clock),
.CE(1'b1),
.D(\counter_reg[8]_i_1_n_6 ),
.Q(counter_reg[9]),
.R(hsync));
CARRY4 rgb1_carry
(.CI(1'b0),
.CO({rgb1_carry_n_0,rgb1_carry_n_1,rgb1_carry_n_2,rgb1_carry_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,rgb1_carry_i_1_n_0,rgb1_carry_i_2_n_0}),
.O(NLW_rgb1_carry_O_UNCONNECTED[3:0]),
.S({rgb1_carry_i_3_n_0,rgb1_carry_i_4_n_0,rgb1_carry_i_5_n_0,rgb1_carry_i_6_n_0}));
CARRY4 rgb1_carry__0
(.CI(rgb1_carry_n_0),
.CO({rgb1_carry__0_n_0,rgb1_carry__0_n_1,rgb1_carry__0_n_2,rgb1_carry__0_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_rgb1_carry__0_O_UNCONNECTED[3:0]),
.S({rgb1_carry__0_i_1_n_0,rgb1_carry__0_i_2_n_0,rgb1_carry__0_i_3_n_0,rgb1_carry__0_i_4_n_0}));
LUT2 #(
.INIT(4'h1))
rgb1_carry__0_i_1
(.I0(counter_reg[20]),
.I1(counter_reg[21]),
.O(rgb1_carry__0_i_1_n_0));
LUT2 #(
.INIT(4'h1))
rgb1_carry__0_i_2
(.I0(counter_reg[18]),
.I1(counter_reg[19]),
.O(rgb1_carry__0_i_2_n_0));
LUT2 #(
.INIT(4'h1))
rgb1_carry__0_i_3
(.I0(counter_reg[16]),
.I1(counter_reg[17]),
.O(rgb1_carry__0_i_3_n_0));
LUT2 #(
.INIT(4'h1))
rgb1_carry__0_i_4
(.I0(counter_reg[14]),
.I1(counter_reg[15]),
.O(rgb1_carry__0_i_4_n_0));
CARRY4 rgb1_carry__1
(.CI(rgb1_carry__0_n_0),
.CO({rgb1_carry__1_n_0,rgb1_carry__1_n_1,rgb1_carry__1_n_2,rgb1_carry__1_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_rgb1_carry__1_O_UNCONNECTED[3:0]),
.S({rgb1_carry__1_i_1_n_0,rgb1_carry__1_i_2_n_0,rgb1_carry__1_i_3_n_0,rgb1_carry__1_i_4_n_0}));
LUT2 #(
.INIT(4'h1))
rgb1_carry__1_i_1
(.I0(counter_reg[28]),
.I1(counter_reg[29]),
.O(rgb1_carry__1_i_1_n_0));
LUT2 #(
.INIT(4'h1))
rgb1_carry__1_i_2
(.I0(counter_reg[26]),
.I1(counter_reg[27]),
.O(rgb1_carry__1_i_2_n_0));
LUT2 #(
.INIT(4'h1))
rgb1_carry__1_i_3
(.I0(counter_reg[24]),
.I1(counter_reg[25]),
.O(rgb1_carry__1_i_3_n_0));
LUT2 #(
.INIT(4'h1))
rgb1_carry__1_i_4
(.I0(counter_reg[22]),
.I1(counter_reg[23]),
.O(rgb1_carry__1_i_4_n_0));
CARRY4 rgb1_carry__2
(.CI(rgb1_carry__1_n_0),
.CO({NLW_rgb1_carry__2_CO_UNCONNECTED[3:1],rgb1}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,counter_reg[31]}),
.O(NLW_rgb1_carry__2_O_UNCONNECTED[3:0]),
.S({1'b0,1'b0,1'b0,rgb1_carry__2_i_1_n_0}));
LUT2 #(
.INIT(4'h1))
rgb1_carry__2_i_1
(.I0(counter_reg[30]),
.I1(counter_reg[31]),
.O(rgb1_carry__2_i_1_n_0));
LUT2 #(
.INIT(4'h1))
rgb1_carry_i_1
(.I0(counter_reg[8]),
.I1(counter_reg[9]),
.O(rgb1_carry_i_1_n_0));
LUT2 #(
.INIT(4'h1))
rgb1_carry_i_2
(.I0(counter_reg[6]),
.I1(counter_reg[7]),
.O(rgb1_carry_i_2_n_0));
LUT2 #(
.INIT(4'h1))
rgb1_carry_i_3
(.I0(counter_reg[12]),
.I1(counter_reg[13]),
.O(rgb1_carry_i_3_n_0));
LUT2 #(
.INIT(4'h1))
rgb1_carry_i_4
(.I0(counter_reg[10]),
.I1(counter_reg[11]),
.O(rgb1_carry_i_4_n_0));
LUT2 #(
.INIT(4'h2))
rgb1_carry_i_5
(.I0(counter_reg[8]),
.I1(counter_reg[9]),
.O(rgb1_carry_i_5_n_0));
LUT2 #(
.INIT(4'h2))
rgb1_carry_i_6
(.I0(counter_reg[6]),
.I1(counter_reg[7]),
.O(rgb1_carry_i_6_n_0));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT3 #(
.INIT(8'hAC))
\rgb[0]_i_1
(.I0(rgb_0[0]),
.I1(rgb_1[0]),
.I2(rgb1),
.O(p_1_in[0]));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT3 #(
.INIT(8'hAC))
\rgb[10]_i_1
(.I0(rgb_0[10]),
.I1(rgb_1[10]),
.I2(rgb1),
.O(p_1_in[10]));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT3 #(
.INIT(8'hAC))
\rgb[11]_i_1
(.I0(rgb_0[11]),
.I1(rgb_1[11]),
.I2(rgb1),
.O(p_1_in[11]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT3 #(
.INIT(8'hAC))
\rgb[12]_i_1
(.I0(rgb_0[12]),
.I1(rgb_1[12]),
.I2(rgb1),
.O(p_1_in[12]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT3 #(
.INIT(8'hAC))
\rgb[13]_i_1
(.I0(rgb_0[13]),
.I1(rgb_1[13]),
.I2(rgb1),
.O(p_1_in[13]));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT3 #(
.INIT(8'hAC))
\rgb[14]_i_1
(.I0(rgb_0[14]),
.I1(rgb_1[14]),
.I2(rgb1),
.O(p_1_in[14]));
LUT1 #(
.INIT(2'h1))
\rgb[15]_i_1
(.I0(hsync),
.O(p_0_in));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT3 #(
.INIT(8'hAC))
\rgb[15]_i_2
(.I0(rgb_0[15]),
.I1(rgb_1[15]),
.I2(rgb1),
.O(p_1_in[15]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT3 #(
.INIT(8'hAC))
\rgb[1]_i_1
(.I0(rgb_0[1]),
.I1(rgb_1[1]),
.I2(rgb1),
.O(p_1_in[1]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT3 #(
.INIT(8'hAC))
\rgb[2]_i_1
(.I0(rgb_0[2]),
.I1(rgb_1[2]),
.I2(rgb1),
.O(p_1_in[2]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT3 #(
.INIT(8'hAC))
\rgb[3]_i_1
(.I0(rgb_0[3]),
.I1(rgb_1[3]),
.I2(rgb1),
.O(p_1_in[3]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT3 #(
.INIT(8'hAC))
\rgb[4]_i_1
(.I0(rgb_0[4]),
.I1(rgb_1[4]),
.I2(rgb1),
.O(p_1_in[4]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT3 #(
.INIT(8'hAC))
\rgb[5]_i_1
(.I0(rgb_0[5]),
.I1(rgb_1[5]),
.I2(rgb1),
.O(p_1_in[5]));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT3 #(
.INIT(8'hAC))
\rgb[6]_i_1
(.I0(rgb_0[6]),
.I1(rgb_1[6]),
.I2(rgb1),
.O(p_1_in[6]));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT3 #(
.INIT(8'hAC))
\rgb[7]_i_1
(.I0(rgb_0[7]),
.I1(rgb_1[7]),
.I2(rgb1),
.O(p_1_in[7]));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT3 #(
.INIT(8'hAC))
\rgb[8]_i_1
(.I0(rgb_0[8]),
.I1(rgb_1[8]),
.I2(rgb1),
.O(p_1_in[8]));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT3 #(
.INIT(8'hAC))
\rgb[9]_i_1
(.I0(rgb_0[9]),
.I1(rgb_1[9]),
.I2(rgb1),
.O(p_1_in[9]));
FDRE \rgb_reg[0]
(.C(clock),
.CE(p_0_in),
.D(p_1_in[0]),
.Q(rgb[0]),
.R(1'b0));
FDRE \rgb_reg[10]
(.C(clock),
.CE(p_0_in),
.D(p_1_in[10]),
.Q(rgb[10]),
.R(1'b0));
FDRE \rgb_reg[11]
(.C(clock),
.CE(p_0_in),
.D(p_1_in[11]),
.Q(rgb[11]),
.R(1'b0));
FDRE \rgb_reg[12]
(.C(clock),
.CE(p_0_in),
.D(p_1_in[12]),
.Q(rgb[12]),
.R(1'b0));
FDRE \rgb_reg[13]
(.C(clock),
.CE(p_0_in),
.D(p_1_in[13]),
.Q(rgb[13]),
.R(1'b0));
FDRE \rgb_reg[14]
(.C(clock),
.CE(p_0_in),
.D(p_1_in[14]),
.Q(rgb[14]),
.R(1'b0));
FDRE \rgb_reg[15]
(.C(clock),
.CE(p_0_in),
.D(p_1_in[15]),
.Q(rgb[15]),
.R(1'b0));
FDRE \rgb_reg[1]
(.C(clock),
.CE(p_0_in),
.D(p_1_in[1]),
.Q(rgb[1]),
.R(1'b0));
FDRE \rgb_reg[2]
(.C(clock),
.CE(p_0_in),
.D(p_1_in[2]),
.Q(rgb[2]),
.R(1'b0));
FDRE \rgb_reg[3]
(.C(clock),
.CE(p_0_in),
.D(p_1_in[3]),
.Q(rgb[3]),
.R(1'b0));
FDRE \rgb_reg[4]
(.C(clock),
.CE(p_0_in),
.D(p_1_in[4]),
.Q(rgb[4]),
.R(1'b0));
FDRE \rgb_reg[5]
(.C(clock),
.CE(p_0_in),
.D(p_1_in[5]),
.Q(rgb[5]),
.R(1'b0));
FDRE \rgb_reg[6]
(.C(clock),
.CE(p_0_in),
.D(p_1_in[6]),
.Q(rgb[6]),
.R(1'b0));
FDRE \rgb_reg[7]
(.C(clock),
.CE(p_0_in),
.D(p_1_in[7]),
.Q(rgb[7]),
.R(1'b0));
FDRE \rgb_reg[8]
(.C(clock),
.CE(p_0_in),
.D(p_1_in[8]),
.Q(rgb[8]),
.R(1'b0));
FDRE \rgb_reg[9]
(.C(clock),
.CE(p_0_in),
.D(p_1_in[9]),
.Q(rgb[9]),
.R(1'b0));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
//
// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24)
//
//
//
//
// Ports:
// Name I/O size props
// RDY_server_reset_request_put O 1 reg
// RDY_server_reset_response_get O 1 reg
// RDY_set_addr_map O 1 const
// slave_awready O 1 reg
// slave_wready O 1 reg
// slave_bvalid O 1 reg
// slave_bid O 4 reg
// slave_bresp O 2 reg
// slave_arready O 1 reg
// slave_rvalid O 1 reg
// slave_rid O 4 reg
// slave_rdata O 64 reg
// slave_rresp O 2 reg
// slave_rlast O 1 reg
// get_to_console_get O 8 reg
// RDY_get_to_console_get O 1 reg
// RDY_put_from_console_put O 1 reg
// intr O 1
// CLK I 1 clock
// RST_N I 1 reset
// set_addr_map_addr_base I 64 reg
// set_addr_map_addr_lim I 64 reg
// slave_awvalid I 1
// slave_awid I 4 reg
// slave_awaddr I 64 reg
// slave_awlen I 8 reg
// slave_awsize I 3 reg
// slave_awburst I 2 reg
// slave_awlock I 1 reg
// slave_awcache I 4 reg
// slave_awprot I 3 reg
// slave_awqos I 4 reg
// slave_awregion I 4 reg
// slave_wvalid I 1
// slave_wdata I 64 reg
// slave_wstrb I 8 reg
// slave_wlast I 1 reg
// slave_bready I 1
// slave_arvalid I 1
// slave_arid I 4 reg
// slave_araddr I 64 reg
// slave_arlen I 8 reg
// slave_arsize I 3 reg
// slave_arburst I 2 reg
// slave_arlock I 1 reg
// slave_arcache I 4 reg
// slave_arprot I 3 reg
// slave_arqos I 4 reg
// slave_arregion I 4 reg
// slave_rready I 1
// put_from_console_put I 8 reg
// EN_server_reset_request_put I 1
// EN_server_reset_response_get I 1
// EN_set_addr_map I 1
// EN_put_from_console_put I 1
// EN_get_to_console_get I 1
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkUART(CLK,
RST_N,
EN_server_reset_request_put,
RDY_server_reset_request_put,
EN_server_reset_response_get,
RDY_server_reset_response_get,
set_addr_map_addr_base,
set_addr_map_addr_lim,
EN_set_addr_map,
RDY_set_addr_map,
slave_awvalid,
slave_awid,
slave_awaddr,
slave_awlen,
slave_awsize,
slave_awburst,
slave_awlock,
slave_awcache,
slave_awprot,
slave_awqos,
slave_awregion,
slave_awready,
slave_wvalid,
slave_wdata,
slave_wstrb,
slave_wlast,
slave_wready,
slave_bvalid,
slave_bid,
slave_bresp,
slave_bready,
slave_arvalid,
slave_arid,
slave_araddr,
slave_arlen,
slave_arsize,
slave_arburst,
slave_arlock,
slave_arcache,
slave_arprot,
slave_arqos,
slave_arregion,
slave_arready,
slave_rvalid,
slave_rid,
slave_rdata,
slave_rresp,
slave_rlast,
slave_rready,
EN_get_to_console_get,
get_to_console_get,
RDY_get_to_console_get,
put_from_console_put,
EN_put_from_console_put,
RDY_put_from_console_put,
intr);
input CLK;
input RST_N;
// action method server_reset_request_put
input EN_server_reset_request_put;
output RDY_server_reset_request_put;
// action method server_reset_response_get
input EN_server_reset_response_get;
output RDY_server_reset_response_get;
// action method set_addr_map
input [63 : 0] set_addr_map_addr_base;
input [63 : 0] set_addr_map_addr_lim;
input EN_set_addr_map;
output RDY_set_addr_map;
// action method slave_m_awvalid
input slave_awvalid;
input [3 : 0] slave_awid;
input [63 : 0] slave_awaddr;
input [7 : 0] slave_awlen;
input [2 : 0] slave_awsize;
input [1 : 0] slave_awburst;
input slave_awlock;
input [3 : 0] slave_awcache;
input [2 : 0] slave_awprot;
input [3 : 0] slave_awqos;
input [3 : 0] slave_awregion;
// value method slave_m_awready
output slave_awready;
// action method slave_m_wvalid
input slave_wvalid;
input [63 : 0] slave_wdata;
input [7 : 0] slave_wstrb;
input slave_wlast;
// value method slave_m_wready
output slave_wready;
// value method slave_m_bvalid
output slave_bvalid;
// value method slave_m_bid
output [3 : 0] slave_bid;
// value method slave_m_bresp
output [1 : 0] slave_bresp;
// value method slave_m_buser
// action method slave_m_bready
input slave_bready;
// action method slave_m_arvalid
input slave_arvalid;
input [3 : 0] slave_arid;
input [63 : 0] slave_araddr;
input [7 : 0] slave_arlen;
input [2 : 0] slave_arsize;
input [1 : 0] slave_arburst;
input slave_arlock;
input [3 : 0] slave_arcache;
input [2 : 0] slave_arprot;
input [3 : 0] slave_arqos;
input [3 : 0] slave_arregion;
// value method slave_m_arready
output slave_arready;
// value method slave_m_rvalid
output slave_rvalid;
// value method slave_m_rid
output [3 : 0] slave_rid;
// value method slave_m_rdata
output [63 : 0] slave_rdata;
// value method slave_m_rresp
output [1 : 0] slave_rresp;
// value method slave_m_rlast
output slave_rlast;
// value method slave_m_ruser
// action method slave_m_rready
input slave_rready;
// actionvalue method get_to_console_get
input EN_get_to_console_get;
output [7 : 0] get_to_console_get;
output RDY_get_to_console_get;
// action method put_from_console_put
input [7 : 0] put_from_console_put;
input EN_put_from_console_put;
output RDY_put_from_console_put;
// value method intr
output intr;
// signals for module outputs
wire [63 : 0] slave_rdata;
wire [7 : 0] get_to_console_get;
wire [3 : 0] slave_bid, slave_rid;
wire [1 : 0] slave_bresp, slave_rresp;
wire RDY_get_to_console_get,
RDY_put_from_console_put,
RDY_server_reset_request_put,
RDY_server_reset_response_get,
RDY_set_addr_map,
intr,
slave_arready,
slave_awready,
slave_bvalid,
slave_rlast,
slave_rvalid,
slave_wready;
// register cfg_verbosity
reg [7 : 0] cfg_verbosity;
wire [7 : 0] cfg_verbosity$D_IN;
wire cfg_verbosity$EN;
// register rg_addr_base
reg [63 : 0] rg_addr_base;
wire [63 : 0] rg_addr_base$D_IN;
wire rg_addr_base$EN;
// register rg_addr_lim
reg [63 : 0] rg_addr_lim;
wire [63 : 0] rg_addr_lim$D_IN;
wire rg_addr_lim$EN;
// register rg_dll
reg [7 : 0] rg_dll;
wire [7 : 0] rg_dll$D_IN;
wire rg_dll$EN;
// register rg_dlm
reg [7 : 0] rg_dlm;
wire [7 : 0] rg_dlm$D_IN;
wire rg_dlm$EN;
// register rg_fcr
reg [7 : 0] rg_fcr;
wire [7 : 0] rg_fcr$D_IN;
wire rg_fcr$EN;
// register rg_ier
reg [7 : 0] rg_ier;
wire [7 : 0] rg_ier$D_IN;
wire rg_ier$EN;
// register rg_lcr
reg [7 : 0] rg_lcr;
wire [7 : 0] rg_lcr$D_IN;
wire rg_lcr$EN;
// register rg_lsr
reg [7 : 0] rg_lsr;
reg [7 : 0] rg_lsr$D_IN;
wire rg_lsr$EN;
// register rg_mcr
reg [7 : 0] rg_mcr;
wire [7 : 0] rg_mcr$D_IN;
wire rg_mcr$EN;
// register rg_msr
reg [7 : 0] rg_msr;
wire [7 : 0] rg_msr$D_IN;
wire rg_msr$EN;
// register rg_rbr
reg [7 : 0] rg_rbr;
wire [7 : 0] rg_rbr$D_IN;
wire rg_rbr$EN;
// register rg_scr
reg [7 : 0] rg_scr;
wire [7 : 0] rg_scr$D_IN;
wire rg_scr$EN;
// register rg_state
reg rg_state;
wire rg_state$D_IN, rg_state$EN;
// register rg_thr
reg [7 : 0] rg_thr;
wire [7 : 0] rg_thr$D_IN;
wire rg_thr$EN;
// ports of submodule f_from_console
wire [7 : 0] f_from_console$D_IN, f_from_console$D_OUT;
wire f_from_console$CLR,
f_from_console$DEQ,
f_from_console$EMPTY_N,
f_from_console$ENQ,
f_from_console$FULL_N;
// ports of submodule f_reset_reqs
wire f_reset_reqs$CLR,
f_reset_reqs$DEQ,
f_reset_reqs$EMPTY_N,
f_reset_reqs$ENQ,
f_reset_reqs$FULL_N;
// ports of submodule f_reset_rsps
wire f_reset_rsps$CLR,
f_reset_rsps$DEQ,
f_reset_rsps$EMPTY_N,
f_reset_rsps$ENQ,
f_reset_rsps$FULL_N;
// ports of submodule f_to_console
wire [7 : 0] f_to_console$D_IN, f_to_console$D_OUT;
wire f_to_console$CLR,
f_to_console$DEQ,
f_to_console$EMPTY_N,
f_to_console$ENQ,
f_to_console$FULL_N;
// ports of submodule slave_xactor_f_rd_addr
wire [96 : 0] slave_xactor_f_rd_addr$D_IN, slave_xactor_f_rd_addr$D_OUT;
wire slave_xactor_f_rd_addr$CLR,
slave_xactor_f_rd_addr$DEQ,
slave_xactor_f_rd_addr$EMPTY_N,
slave_xactor_f_rd_addr$ENQ,
slave_xactor_f_rd_addr$FULL_N;
// ports of submodule slave_xactor_f_rd_data
wire [70 : 0] slave_xactor_f_rd_data$D_IN, slave_xactor_f_rd_data$D_OUT;
wire slave_xactor_f_rd_data$CLR,
slave_xactor_f_rd_data$DEQ,
slave_xactor_f_rd_data$EMPTY_N,
slave_xactor_f_rd_data$ENQ,
slave_xactor_f_rd_data$FULL_N;
// ports of submodule slave_xactor_f_wr_addr
wire [96 : 0] slave_xactor_f_wr_addr$D_IN, slave_xactor_f_wr_addr$D_OUT;
wire slave_xactor_f_wr_addr$CLR,
slave_xactor_f_wr_addr$DEQ,
slave_xactor_f_wr_addr$EMPTY_N,
slave_xactor_f_wr_addr$ENQ,
slave_xactor_f_wr_addr$FULL_N;
// ports of submodule slave_xactor_f_wr_data
wire [72 : 0] slave_xactor_f_wr_data$D_IN, slave_xactor_f_wr_data$D_OUT;
wire slave_xactor_f_wr_data$CLR,
slave_xactor_f_wr_data$DEQ,
slave_xactor_f_wr_data$EMPTY_N,
slave_xactor_f_wr_data$ENQ,
slave_xactor_f_wr_data$FULL_N;
// ports of submodule slave_xactor_f_wr_resp
wire [5 : 0] slave_xactor_f_wr_resp$D_IN, slave_xactor_f_wr_resp$D_OUT;
wire slave_xactor_f_wr_resp$CLR,
slave_xactor_f_wr_resp$DEQ,
slave_xactor_f_wr_resp$EMPTY_N,
slave_xactor_f_wr_resp$ENQ,
slave_xactor_f_wr_resp$FULL_N;
// rule scheduling signals
wire CAN_FIRE_RL_rl_process_rd_req,
CAN_FIRE_RL_rl_process_wr_req,
CAN_FIRE_RL_rl_receive,
CAN_FIRE_RL_rl_reset,
CAN_FIRE_get_to_console_get,
CAN_FIRE_put_from_console_put,
CAN_FIRE_server_reset_request_put,
CAN_FIRE_server_reset_response_get,
CAN_FIRE_set_addr_map,
CAN_FIRE_slave_m_arvalid,
CAN_FIRE_slave_m_awvalid,
CAN_FIRE_slave_m_bready,
CAN_FIRE_slave_m_rready,
CAN_FIRE_slave_m_wvalid,
WILL_FIRE_RL_rl_process_rd_req,
WILL_FIRE_RL_rl_process_wr_req,
WILL_FIRE_RL_rl_receive,
WILL_FIRE_RL_rl_reset,
WILL_FIRE_get_to_console_get,
WILL_FIRE_put_from_console_put,
WILL_FIRE_server_reset_request_put,
WILL_FIRE_server_reset_response_get,
WILL_FIRE_set_addr_map,
WILL_FIRE_slave_m_arvalid,
WILL_FIRE_slave_m_awvalid,
WILL_FIRE_slave_m_bready,
WILL_FIRE_slave_m_rready,
WILL_FIRE_slave_m_wvalid;
// inputs to muxes for submodule ports
wire [7 : 0] MUX_rg_lsr$write_1__VAL_3;
wire MUX_rg_lsr$write_1__SEL_3;
// declarations used by system tasks
// synopsys translate_off
reg [31 : 0] v__h1992;
reg [31 : 0] v__h2869;
reg [31 : 0] v__h2357;
reg [31 : 0] v__h2200;
reg [31 : 0] v__h3288;
reg [31 : 0] v__h3576;
reg [31 : 0] v__h5025;
reg [31 : 0] v__h3915;
reg [31 : 0] v__h3763;
reg [31 : 0] v__h5335;
reg [31 : 0] v__h5777;
reg [31 : 0] v__h5887;
reg [31 : 0] v__h1812;
reg [31 : 0] v__h1806;
reg [31 : 0] v__h1986;
reg [31 : 0] v__h2194;
reg [31 : 0] v__h2351;
reg [31 : 0] v__h2863;
reg [31 : 0] v__h3282;
reg [31 : 0] v__h3570;
reg [31 : 0] v__h3757;
reg [31 : 0] v__h3909;
reg [31 : 0] v__h5019;
reg [31 : 0] v__h5329;
reg [31 : 0] v__h5771;
reg [31 : 0] v__h5881;
// synopsys translate_on
// remaining internal signals
reg [63 : 0] x__h4063;
reg [7 : 0] y_avValue_snd__h3033;
wire [63 : 0] rdata___1__h3181,
rdata__h3123,
rdr_rdata__h3156,
result__h4081,
result__h4111,
result__h4138,
result__h4165,
result__h4192,
result__h4219,
result__h4246,
result__h4273,
result__h4300,
result__h4327,
result__h4354,
result__h4381,
result__h4408,
result__h4435,
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35,
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156;
wire [7 : 0] fn_iir__h1357,
new_lsr__h5544,
x__h3184,
y_avValue_snd__h3046,
y_avValue_snd__h3059,
y_avValue_snd__h3074,
y_avValue_snd__h3088;
wire [1 : 0] rdr_rresp__h3157,
v__h3531,
v__h3702,
v__h3846,
v__h3998,
y_avValue_fst__h3087,
y_avValue_fst__h3101,
y_avValue_fst__h3115;
wire NOT_cfg_verbosity_read_ULE_1_43___d144,
NOT_slave_xactor_f_rd_addr_first__4_BITS_92_TO_ETC___d48,
NOT_slave_xactor_f_wr_addr_first__50_BITS_92_T_ETC___d192,
NOT_slave_xactor_f_wr_addr_first__50_BITS_92_T_ETC___d258,
NOT_slave_xactor_f_wr_addr_first__50_BITS_92_T_ETC___d263,
NOT_slave_xactor_f_wr_addr_first__50_BITS_92_T_ETC___d267,
NOT_slave_xactor_f_wr_addr_first__50_BITS_92_T_ETC___d271,
NOT_slave_xactor_f_wr_addr_first__50_BITS_92_T_ETC___d275,
NOT_slave_xactor_f_wr_addr_first__50_BITS_92_T_ETC___d279,
NOT_slave_xactor_f_wr_addr_first__50_BITS_92_T_ETC___d283,
NOT_slave_xactor_f_wr_addr_first__50_BITS_92_T_ETC___d316,
NOT_slave_xactor_f_wr_addr_first__50_BITS_92_T_ETC___d322,
NOT_slave_xactor_f_wr_addr_first__50_BITS_92_T_ETC___d329,
NOT_slave_xactor_f_wr_addr_first__50_BITS_92_T_ETC___d335,
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17,
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d19,
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152,
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153,
slave_xactor_f_wr_resp_i_notFull__49_AND_slave_ETC___d172;
// action method server_reset_request_put
assign RDY_server_reset_request_put = f_reset_reqs$FULL_N ;
assign CAN_FIRE_server_reset_request_put = f_reset_reqs$FULL_N ;
assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ;
// action method server_reset_response_get
assign RDY_server_reset_response_get = f_reset_rsps$EMPTY_N ;
assign CAN_FIRE_server_reset_response_get = f_reset_rsps$EMPTY_N ;
assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ;
// action method set_addr_map
assign RDY_set_addr_map = 1'd1 ;
assign CAN_FIRE_set_addr_map = 1'd1 ;
assign WILL_FIRE_set_addr_map = EN_set_addr_map ;
// action method slave_m_awvalid
assign CAN_FIRE_slave_m_awvalid = 1'd1 ;
assign WILL_FIRE_slave_m_awvalid = 1'd1 ;
// value method slave_m_awready
assign slave_awready = slave_xactor_f_wr_addr$FULL_N ;
// action method slave_m_wvalid
assign CAN_FIRE_slave_m_wvalid = 1'd1 ;
assign WILL_FIRE_slave_m_wvalid = 1'd1 ;
// value method slave_m_wready
assign slave_wready = slave_xactor_f_wr_data$FULL_N ;
// value method slave_m_bvalid
assign slave_bvalid = slave_xactor_f_wr_resp$EMPTY_N ;
// value method slave_m_bid
assign slave_bid = slave_xactor_f_wr_resp$D_OUT[5:2] ;
// value method slave_m_bresp
assign slave_bresp = slave_xactor_f_wr_resp$D_OUT[1:0] ;
// action method slave_m_bready
assign CAN_FIRE_slave_m_bready = 1'd1 ;
assign WILL_FIRE_slave_m_bready = 1'd1 ;
// action method slave_m_arvalid
assign CAN_FIRE_slave_m_arvalid = 1'd1 ;
assign WILL_FIRE_slave_m_arvalid = 1'd1 ;
// value method slave_m_arready
assign slave_arready = slave_xactor_f_rd_addr$FULL_N ;
// value method slave_m_rvalid
assign slave_rvalid = slave_xactor_f_rd_data$EMPTY_N ;
// value method slave_m_rid
assign slave_rid = slave_xactor_f_rd_data$D_OUT[70:67] ;
// value method slave_m_rdata
assign slave_rdata = slave_xactor_f_rd_data$D_OUT[66:3] ;
// value method slave_m_rresp
assign slave_rresp = slave_xactor_f_rd_data$D_OUT[2:1] ;
// value method slave_m_rlast
assign slave_rlast = slave_xactor_f_rd_data$D_OUT[0] ;
// action method slave_m_rready
assign CAN_FIRE_slave_m_rready = 1'd1 ;
assign WILL_FIRE_slave_m_rready = 1'd1 ;
// actionvalue method get_to_console_get
assign get_to_console_get = f_to_console$D_OUT ;
assign RDY_get_to_console_get = f_to_console$EMPTY_N ;
assign CAN_FIRE_get_to_console_get = f_to_console$EMPTY_N ;
assign WILL_FIRE_get_to_console_get = EN_get_to_console_get ;
// action method put_from_console_put
assign RDY_put_from_console_put = f_from_console$FULL_N ;
assign CAN_FIRE_put_from_console_put = f_from_console$FULL_N ;
assign WILL_FIRE_put_from_console_put = EN_put_from_console_put ;
// value method intr
assign intr = !fn_iir__h1357[0] ;
// submodule f_from_console
FIFO2 #(.width(32'd8), .guarded(32'd1)) f_from_console(.RST(RST_N),
.CLK(CLK),
.D_IN(f_from_console$D_IN),
.ENQ(f_from_console$ENQ),
.DEQ(f_from_console$DEQ),
.CLR(f_from_console$CLR),
.D_OUT(f_from_console$D_OUT),
.FULL_N(f_from_console$FULL_N),
.EMPTY_N(f_from_console$EMPTY_N));
// submodule f_reset_reqs
FIFO20 #(.guarded(32'd1)) f_reset_reqs(.RST(RST_N),
.CLK(CLK),
.ENQ(f_reset_reqs$ENQ),
.DEQ(f_reset_reqs$DEQ),
.CLR(f_reset_reqs$CLR),
.FULL_N(f_reset_reqs$FULL_N),
.EMPTY_N(f_reset_reqs$EMPTY_N));
// submodule f_reset_rsps
FIFO20 #(.guarded(32'd1)) f_reset_rsps(.RST(RST_N),
.CLK(CLK),
.ENQ(f_reset_rsps$ENQ),
.DEQ(f_reset_rsps$DEQ),
.CLR(f_reset_rsps$CLR),
.FULL_N(f_reset_rsps$FULL_N),
.EMPTY_N(f_reset_rsps$EMPTY_N));
// submodule f_to_console
FIFO2 #(.width(32'd8), .guarded(32'd1)) f_to_console(.RST(RST_N),
.CLK(CLK),
.D_IN(f_to_console$D_IN),
.ENQ(f_to_console$ENQ),
.DEQ(f_to_console$DEQ),
.CLR(f_to_console$CLR),
.D_OUT(f_to_console$D_OUT),
.FULL_N(f_to_console$FULL_N),
.EMPTY_N(f_to_console$EMPTY_N));
// submodule slave_xactor_f_rd_addr
FIFO2 #(.width(32'd97), .guarded(32'd1)) slave_xactor_f_rd_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(slave_xactor_f_rd_addr$D_IN),
.ENQ(slave_xactor_f_rd_addr$ENQ),
.DEQ(slave_xactor_f_rd_addr$DEQ),
.CLR(slave_xactor_f_rd_addr$CLR),
.D_OUT(slave_xactor_f_rd_addr$D_OUT),
.FULL_N(slave_xactor_f_rd_addr$FULL_N),
.EMPTY_N(slave_xactor_f_rd_addr$EMPTY_N));
// submodule slave_xactor_f_rd_data
FIFO2 #(.width(32'd71), .guarded(32'd1)) slave_xactor_f_rd_data(.RST(RST_N),
.CLK(CLK),
.D_IN(slave_xactor_f_rd_data$D_IN),
.ENQ(slave_xactor_f_rd_data$ENQ),
.DEQ(slave_xactor_f_rd_data$DEQ),
.CLR(slave_xactor_f_rd_data$CLR),
.D_OUT(slave_xactor_f_rd_data$D_OUT),
.FULL_N(slave_xactor_f_rd_data$FULL_N),
.EMPTY_N(slave_xactor_f_rd_data$EMPTY_N));
// submodule slave_xactor_f_wr_addr
FIFO2 #(.width(32'd97), .guarded(32'd1)) slave_xactor_f_wr_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(slave_xactor_f_wr_addr$D_IN),
.ENQ(slave_xactor_f_wr_addr$ENQ),
.DEQ(slave_xactor_f_wr_addr$DEQ),
.CLR(slave_xactor_f_wr_addr$CLR),
.D_OUT(slave_xactor_f_wr_addr$D_OUT),
.FULL_N(slave_xactor_f_wr_addr$FULL_N),
.EMPTY_N(slave_xactor_f_wr_addr$EMPTY_N));
// submodule slave_xactor_f_wr_data
FIFO2 #(.width(32'd73), .guarded(32'd1)) slave_xactor_f_wr_data(.RST(RST_N),
.CLK(CLK),
.D_IN(slave_xactor_f_wr_data$D_IN),
.ENQ(slave_xactor_f_wr_data$ENQ),
.DEQ(slave_xactor_f_wr_data$DEQ),
.CLR(slave_xactor_f_wr_data$CLR),
.D_OUT(slave_xactor_f_wr_data$D_OUT),
.FULL_N(slave_xactor_f_wr_data$FULL_N),
.EMPTY_N(slave_xactor_f_wr_data$EMPTY_N));
// submodule slave_xactor_f_wr_resp
FIFO2 #(.width(32'd6), .guarded(32'd1)) slave_xactor_f_wr_resp(.RST(RST_N),
.CLK(CLK),
.D_IN(slave_xactor_f_wr_resp$D_IN),
.ENQ(slave_xactor_f_wr_resp$ENQ),
.DEQ(slave_xactor_f_wr_resp$DEQ),
.CLR(slave_xactor_f_wr_resp$CLR),
.D_OUT(slave_xactor_f_wr_resp$D_OUT),
.FULL_N(slave_xactor_f_wr_resp$FULL_N),
.EMPTY_N(slave_xactor_f_wr_resp$EMPTY_N));
// rule RL_rl_process_rd_req
assign CAN_FIRE_RL_rl_process_rd_req =
slave_xactor_f_rd_addr$EMPTY_N &&
slave_xactor_f_rd_data$FULL_N &&
rg_state ;
assign WILL_FIRE_RL_rl_process_rd_req =
CAN_FIRE_RL_rl_process_rd_req && !WILL_FIRE_RL_rl_receive ;
// rule RL_rl_process_wr_req
assign CAN_FIRE_RL_rl_process_wr_req =
slave_xactor_f_wr_addr$EMPTY_N &&
slave_xactor_f_wr_data$EMPTY_N &&
slave_xactor_f_wr_resp_i_notFull__49_AND_slave_ETC___d172 &&
rg_state ;
assign WILL_FIRE_RL_rl_process_wr_req = CAN_FIRE_RL_rl_process_wr_req ;
// rule RL_rl_receive
assign CAN_FIRE_RL_rl_receive = f_from_console$EMPTY_N && !rg_lsr[0] ;
assign WILL_FIRE_RL_rl_receive = CAN_FIRE_RL_rl_receive ;
// rule RL_rl_reset
assign CAN_FIRE_RL_rl_reset = f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N ;
assign WILL_FIRE_RL_rl_reset = CAN_FIRE_RL_rl_reset ;
// inputs to muxes for submodule ports
assign MUX_rg_lsr$write_1__SEL_3 =
WILL_FIRE_RL_rl_process_rd_req &&
NOT_slave_xactor_f_rd_addr_first__4_BITS_92_TO_ETC___d48 ;
assign MUX_rg_lsr$write_1__VAL_3 = { rg_lsr[7:1], 1'd0 } ;
// register cfg_verbosity
assign cfg_verbosity$D_IN = 8'h0 ;
assign cfg_verbosity$EN = 1'b0 ;
// register rg_addr_base
assign rg_addr_base$D_IN = set_addr_map_addr_base ;
assign rg_addr_base$EN = EN_set_addr_map ;
// register rg_addr_lim
assign rg_addr_lim$D_IN = set_addr_map_addr_lim ;
assign rg_addr_lim$EN = EN_set_addr_map ;
// register rg_dll
assign rg_dll$D_IN = WILL_FIRE_RL_rl_reset ? 8'd0 : x__h4063[7:0] ;
assign rg_dll$EN =
WILL_FIRE_RL_rl_process_wr_req &&
NOT_slave_xactor_f_wr_addr_first__50_BITS_92_T_ETC___d258 ||
WILL_FIRE_RL_rl_reset ;
// register rg_dlm
assign rg_dlm$D_IN = WILL_FIRE_RL_rl_reset ? 8'd0 : x__h4063[7:0] ;
assign rg_dlm$EN =
WILL_FIRE_RL_rl_process_wr_req &&
NOT_slave_xactor_f_wr_addr_first__50_BITS_92_T_ETC___d267 ||
WILL_FIRE_RL_rl_reset ;
// register rg_fcr
assign rg_fcr$D_IN = WILL_FIRE_RL_rl_reset ? 8'd0 : x__h4063[7:0] ;
assign rg_fcr$EN =
WILL_FIRE_RL_rl_process_wr_req &&
NOT_slave_xactor_f_wr_addr_first__50_BITS_92_T_ETC___d271 ||
WILL_FIRE_RL_rl_reset ;
// register rg_ier
assign rg_ier$D_IN = WILL_FIRE_RL_rl_reset ? 8'd0 : x__h4063[7:0] ;
assign rg_ier$EN =
WILL_FIRE_RL_rl_process_wr_req &&
NOT_slave_xactor_f_wr_addr_first__50_BITS_92_T_ETC___d263 ||
WILL_FIRE_RL_rl_reset ;
// register rg_lcr
assign rg_lcr$D_IN = WILL_FIRE_RL_rl_reset ? 8'd0 : x__h4063[7:0] ;
assign rg_lcr$EN =
WILL_FIRE_RL_rl_process_wr_req &&
NOT_slave_xactor_f_wr_addr_first__50_BITS_92_T_ETC___d275 ||
WILL_FIRE_RL_rl_reset ;
// register rg_lsr
always@(WILL_FIRE_RL_rl_reset or
WILL_FIRE_RL_rl_receive or
new_lsr__h5544 or
MUX_rg_lsr$write_1__SEL_3 or MUX_rg_lsr$write_1__VAL_3)
case (1'b1)
WILL_FIRE_RL_rl_reset: rg_lsr$D_IN = 8'd96;
WILL_FIRE_RL_rl_receive: rg_lsr$D_IN = new_lsr__h5544;
MUX_rg_lsr$write_1__SEL_3: rg_lsr$D_IN = MUX_rg_lsr$write_1__VAL_3;
default: rg_lsr$D_IN = 8'b10101010 /* unspecified value */ ;
endcase
assign rg_lsr$EN =
WILL_FIRE_RL_rl_process_rd_req &&
NOT_slave_xactor_f_rd_addr_first__4_BITS_92_TO_ETC___d48 ||
WILL_FIRE_RL_rl_receive ||
WILL_FIRE_RL_rl_reset ;
// register rg_mcr
assign rg_mcr$D_IN = WILL_FIRE_RL_rl_reset ? 8'd0 : x__h4063[7:0] ;
assign rg_mcr$EN =
WILL_FIRE_RL_rl_process_wr_req &&
NOT_slave_xactor_f_wr_addr_first__50_BITS_92_T_ETC___d279 ||
WILL_FIRE_RL_rl_reset ;
// register rg_msr
assign rg_msr$D_IN = 8'd0 ;
assign rg_msr$EN = CAN_FIRE_RL_rl_reset ;
// register rg_rbr
assign rg_rbr$D_IN = f_from_console$D_OUT ;
assign rg_rbr$EN = CAN_FIRE_RL_rl_receive ;
// register rg_scr
assign rg_scr$D_IN = WILL_FIRE_RL_rl_reset ? 8'd0 : x__h4063[7:0] ;
assign rg_scr$EN =
WILL_FIRE_RL_rl_process_wr_req &&
NOT_slave_xactor_f_wr_addr_first__50_BITS_92_T_ETC___d283 ||
WILL_FIRE_RL_rl_reset ;
// register rg_state
assign rg_state$D_IN = 1'd1 ;
assign rg_state$EN = f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N ;
// register rg_thr
assign rg_thr$D_IN = x__h4063[7:0] ;
assign rg_thr$EN =
WILL_FIRE_RL_rl_process_wr_req &&
NOT_slave_xactor_f_wr_addr_first__50_BITS_92_T_ETC___d192 ;
// submodule f_from_console
assign f_from_console$D_IN = put_from_console_put ;
assign f_from_console$ENQ = EN_put_from_console_put ;
assign f_from_console$DEQ = CAN_FIRE_RL_rl_receive ;
assign f_from_console$CLR = 1'b0 ;
// submodule f_reset_reqs
assign f_reset_reqs$ENQ = EN_server_reset_request_put ;
assign f_reset_reqs$DEQ = f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N ;
assign f_reset_reqs$CLR = 1'b0 ;
// submodule f_reset_rsps
assign f_reset_rsps$ENQ = f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N ;
assign f_reset_rsps$DEQ = EN_server_reset_response_get ;
assign f_reset_rsps$CLR = 1'b0 ;
// submodule f_to_console
assign f_to_console$D_IN = x__h4063[7:0] ;
assign f_to_console$ENQ =
WILL_FIRE_RL_rl_process_wr_req &&
NOT_slave_xactor_f_wr_addr_first__50_BITS_92_T_ETC___d192 ;
assign f_to_console$DEQ = EN_get_to_console_get ;
assign f_to_console$CLR = 1'b0 ;
// submodule slave_xactor_f_rd_addr
assign slave_xactor_f_rd_addr$D_IN =
{ slave_arid,
slave_araddr,
slave_arlen,
slave_arsize,
slave_arburst,
slave_arlock,
slave_arcache,
slave_arprot,
slave_arqos,
slave_arregion } ;
assign slave_xactor_f_rd_addr$ENQ =
slave_arvalid && slave_xactor_f_rd_addr$FULL_N ;
assign slave_xactor_f_rd_addr$DEQ = WILL_FIRE_RL_rl_process_rd_req ;
assign slave_xactor_f_rd_addr$CLR =
f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N ;
// submodule slave_xactor_f_rd_data
assign slave_xactor_f_rd_data$D_IN =
{ slave_xactor_f_rd_addr$D_OUT[96:93],
rdr_rdata__h3156,
rdr_rresp__h3157,
1'd1 } ;
assign slave_xactor_f_rd_data$ENQ = WILL_FIRE_RL_rl_process_rd_req ;
assign slave_xactor_f_rd_data$DEQ =
slave_rready && slave_xactor_f_rd_data$EMPTY_N ;
assign slave_xactor_f_rd_data$CLR =
f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N ;
// submodule slave_xactor_f_wr_addr
assign slave_xactor_f_wr_addr$D_IN =
{ slave_awid,
slave_awaddr,
slave_awlen,
slave_awsize,
slave_awburst,
slave_awlock,
slave_awcache,
slave_awprot,
slave_awqos,
slave_awregion } ;
assign slave_xactor_f_wr_addr$ENQ =
slave_awvalid && slave_xactor_f_wr_addr$FULL_N ;
assign slave_xactor_f_wr_addr$DEQ = CAN_FIRE_RL_rl_process_wr_req ;
assign slave_xactor_f_wr_addr$CLR =
f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N ;
// submodule slave_xactor_f_wr_data
assign slave_xactor_f_wr_data$D_IN =
{ slave_wdata, slave_wstrb, slave_wlast } ;
assign slave_xactor_f_wr_data$ENQ =
slave_wvalid && slave_xactor_f_wr_data$FULL_N ;
assign slave_xactor_f_wr_data$DEQ = CAN_FIRE_RL_rl_process_wr_req ;
assign slave_xactor_f_wr_data$CLR =
f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N ;
// submodule slave_xactor_f_wr_resp
assign slave_xactor_f_wr_resp$D_IN =
{ slave_xactor_f_wr_addr$D_OUT[96:93], v__h3531 } ;
assign slave_xactor_f_wr_resp$ENQ = CAN_FIRE_RL_rl_process_wr_req ;
assign slave_xactor_f_wr_resp$DEQ =
slave_bready && slave_xactor_f_wr_resp$EMPTY_N ;
assign slave_xactor_f_wr_resp$CLR =
f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N ;
// remaining internal signals
assign NOT_cfg_verbosity_read_ULE_1_43___d144 = cfg_verbosity > 8'd1 ;
assign NOT_slave_xactor_f_rd_addr_first__4_BITS_92_TO_ETC___d48 =
!slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d19 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[1:0] ==
2'd0 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[63:5] ==
59'd0 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[4:2] ==
3'h0 &&
!rg_lcr[7] ;
assign NOT_slave_xactor_f_wr_addr_first__50_BITS_92_T_ETC___d192 =
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[1:0] ==
2'd0 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[63:5] ==
59'd0 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[4:2] ==
3'h0 &&
!rg_lcr[7] ;
assign NOT_slave_xactor_f_wr_addr_first__50_BITS_92_T_ETC___d258 =
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[1:0] ==
2'd0 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[63:5] ==
59'd0 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[4:2] ==
3'h0 &&
rg_lcr[7] ;
assign NOT_slave_xactor_f_wr_addr_first__50_BITS_92_T_ETC___d263 =
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[1:0] ==
2'd0 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[63:5] ==
59'd0 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[4:2] ==
3'h1 &&
!rg_lcr[7] ;
assign NOT_slave_xactor_f_wr_addr_first__50_BITS_92_T_ETC___d267 =
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[1:0] ==
2'd0 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[63:5] ==
59'd0 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[4:2] ==
3'h1 &&
rg_lcr[7] ;
assign NOT_slave_xactor_f_wr_addr_first__50_BITS_92_T_ETC___d271 =
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[1:0] ==
2'd0 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[63:5] ==
59'd0 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[4:2] ==
3'h2 ;
assign NOT_slave_xactor_f_wr_addr_first__50_BITS_92_T_ETC___d275 =
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[1:0] ==
2'd0 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[63:5] ==
59'd0 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[4:2] ==
3'h3 ;
assign NOT_slave_xactor_f_wr_addr_first__50_BITS_92_T_ETC___d279 =
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[1:0] ==
2'd0 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[63:5] ==
59'd0 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[4:2] ==
3'h4 ;
assign NOT_slave_xactor_f_wr_addr_first__50_BITS_92_T_ETC___d283 =
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[1:0] ==
2'd0 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[63:5] ==
59'd0 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[4:2] ==
3'h7 ;
assign NOT_slave_xactor_f_wr_addr_first__50_BITS_92_T_ETC___d316 =
(slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[4:2] !=
3'h1 ||
!rg_lcr[7]) &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[4:2] !=
3'h2 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[4:2] !=
3'h3 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[4:2] !=
3'h4 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[4:2] !=
3'h5 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[4:2] !=
3'h6 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[4:2] !=
3'h7 &&
slave_xactor_f_wr_data$D_OUT[0] ;
assign NOT_slave_xactor_f_wr_addr_first__50_BITS_92_T_ETC___d322 =
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[1:0] ==
2'd0 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[63:5] ==
59'd0 &&
(slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[4:2] !=
3'h0 ||
rg_lcr[7]) &&
(slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[4:2] !=
3'h0 ||
!rg_lcr[7]) &&
(slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[4:2] !=
3'h1 ||
rg_lcr[7]) &&
NOT_slave_xactor_f_wr_addr_first__50_BITS_92_T_ETC___d316 ;
assign NOT_slave_xactor_f_wr_addr_first__50_BITS_92_T_ETC___d329 =
(slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[4:2] !=
3'h1 ||
!rg_lcr[7]) &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[4:2] !=
3'h2 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[4:2] !=
3'h3 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[4:2] !=
3'h4 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[4:2] !=
3'h5 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[4:2] !=
3'h6 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[4:2] !=
3'h7 &&
!slave_xactor_f_wr_data$D_OUT[0] ;
assign NOT_slave_xactor_f_wr_addr_first__50_BITS_92_T_ETC___d335 =
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[1:0] ==
2'd0 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[63:5] ==
59'd0 &&
(slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[4:2] !=
3'h0 ||
rg_lcr[7]) &&
(slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[4:2] !=
3'h0 ||
!rg_lcr[7]) &&
(slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[4:2] !=
3'h1 ||
rg_lcr[7]) &&
NOT_slave_xactor_f_wr_addr_first__50_BITS_92_T_ETC___d329 ;
assign fn_iir__h1357 =
(rg_ier[0] && rg_lsr[0]) ? 8'h04 : (rg_ier[1] ? 8'h02 : 8'h01) ;
assign new_lsr__h5544 = { rg_lsr[7:1], 1'd1 } ;
assign rdata___1__h3181 = { 24'd0, x__h3184, 32'd0 } ;
assign rdata__h3123 = { 56'd0, x__h3184 } ;
assign rdr_rdata__h3156 =
(slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[2:0] ==
3'b100) ?
rdata___1__h3181 :
rdata__h3123 ;
assign rdr_rresp__h3157 =
(slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 ||
!slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d19) ?
2'b11 :
y_avValue_fst__h3115 ;
assign result__h4081 = { 56'd0, slave_xactor_f_wr_data$D_OUT[16:9] } ;
assign result__h4111 = { 56'd0, slave_xactor_f_wr_data$D_OUT[24:17] } ;
assign result__h4138 = { 56'd0, slave_xactor_f_wr_data$D_OUT[32:25] } ;
assign result__h4165 = { 56'd0, slave_xactor_f_wr_data$D_OUT[40:33] } ;
assign result__h4192 = { 56'd0, slave_xactor_f_wr_data$D_OUT[48:41] } ;
assign result__h4219 = { 56'd0, slave_xactor_f_wr_data$D_OUT[56:49] } ;
assign result__h4246 = { 56'd0, slave_xactor_f_wr_data$D_OUT[64:57] } ;
assign result__h4273 = { 56'd0, slave_xactor_f_wr_data$D_OUT[72:65] } ;
assign result__h4300 = { 48'd0, slave_xactor_f_wr_data$D_OUT[24:9] } ;
assign result__h4327 = { 48'd0, slave_xactor_f_wr_data$D_OUT[40:25] } ;
assign result__h4354 = { 48'd0, slave_xactor_f_wr_data$D_OUT[56:41] } ;
assign result__h4381 = { 48'd0, slave_xactor_f_wr_data$D_OUT[72:57] } ;
assign result__h4408 = { 32'd0, slave_xactor_f_wr_data$D_OUT[40:9] } ;
assign result__h4435 = { 32'd0, slave_xactor_f_wr_data$D_OUT[72:41] } ;
assign slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 =
slave_xactor_f_rd_addr$D_OUT[92:29] < rg_addr_base ;
assign slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d19 =
slave_xactor_f_rd_addr$D_OUT[92:29] < rg_addr_lim ;
assign slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35 =
slave_xactor_f_rd_addr$D_OUT[92:29] - rg_addr_base ;
assign slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 =
slave_xactor_f_wr_addr$D_OUT[92:29] < rg_addr_base ;
assign slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153 =
slave_xactor_f_wr_addr$D_OUT[92:29] < rg_addr_lim ;
assign slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156 =
slave_xactor_f_wr_addr$D_OUT[92:29] - rg_addr_base ;
assign slave_xactor_f_wr_resp_i_notFull__49_AND_slave_ETC___d172 =
slave_xactor_f_wr_resp$FULL_N &&
(slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 ||
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153 ||
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[1:0] !=
2'd0 ||
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[63:5] !=
59'd0 ||
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[4:2] !=
3'h0 ||
rg_lcr[7] ||
f_to_console$FULL_N) ;
assign v__h3531 =
(slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 ||
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153) ?
2'b11 :
v__h3702 ;
assign v__h3702 =
(slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[1:0] ==
2'd0) ?
v__h3846 :
2'b10 ;
assign v__h3846 =
(slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[63:5] ==
59'd0) ?
v__h3998 :
2'b11 ;
assign v__h3998 = y_avValue_fst__h3087 ;
assign x__h3184 =
(slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 ||
!slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d19 ||
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[1:0] !=
2'd0 ||
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[63:5] !=
59'd0) ?
8'd0 :
y_avValue_snd__h3088 ;
assign y_avValue_fst__h3087 = 2'b0 ;
assign y_avValue_fst__h3101 =
(slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[63:5] ==
59'd0) ?
y_avValue_fst__h3087 :
2'b11 ;
assign y_avValue_fst__h3115 =
(slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[1:0] ==
2'd0) ?
y_avValue_fst__h3101 :
2'b10 ;
assign y_avValue_snd__h3046 =
(slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[4:2] ==
3'h1 &&
rg_lcr[7]) ?
rg_dlm :
y_avValue_snd__h3033 ;
assign y_avValue_snd__h3059 =
(slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[4:2] ==
3'h1 &&
!rg_lcr[7]) ?
rg_ier :
y_avValue_snd__h3046 ;
assign y_avValue_snd__h3074 =
(slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[4:2] ==
3'h0 &&
rg_lcr[7]) ?
rg_dll :
y_avValue_snd__h3059 ;
assign y_avValue_snd__h3088 =
(slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[4:2] ==
3'h0 &&
!rg_lcr[7]) ?
rg_rbr :
y_avValue_snd__h3074 ;
always@(slave_xactor_f_wr_data$D_OUT or
result__h4081 or
result__h4111 or
result__h4300 or
result__h4138 or
result__h4165 or
result__h4327 or
result__h4408 or
result__h4192 or
result__h4219 or
result__h4354 or
result__h4246 or result__h4273 or result__h4381 or result__h4435)
begin
case (slave_xactor_f_wr_data$D_OUT[8:1])
8'b00000001: x__h4063 = result__h4081;
8'b00000010: x__h4063 = result__h4111;
8'b00000011: x__h4063 = result__h4300;
8'b00000100: x__h4063 = result__h4138;
8'b00001000: x__h4063 = result__h4165;
8'b00001100: x__h4063 = result__h4327;
8'b00001111: x__h4063 = result__h4408;
8'b00010000: x__h4063 = result__h4192;
8'b00100000: x__h4063 = result__h4219;
8'b00110000: x__h4063 = result__h4354;
8'b01000000: x__h4063 = result__h4246;
8'b10000000: x__h4063 = result__h4273;
8'b11000000: x__h4063 = result__h4381;
8'b11110000: x__h4063 = result__h4435;
8'b11111111: x__h4063 = slave_xactor_f_wr_data$D_OUT[72:9];
default: x__h4063 = 64'd0;
endcase
end
always@(slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35 or
fn_iir__h1357 or rg_lcr or rg_mcr or rg_lsr or rg_msr or rg_scr)
begin
case (slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[4:2])
3'h2: y_avValue_snd__h3033 = fn_iir__h1357;
3'h3: y_avValue_snd__h3033 = rg_lcr;
3'h4: y_avValue_snd__h3033 = rg_mcr;
3'h5: y_avValue_snd__h3033 = rg_lsr;
3'h6: y_avValue_snd__h3033 = rg_msr;
3'h7: y_avValue_snd__h3033 = rg_scr;
default: y_avValue_snd__h3033 = 8'd0;
endcase
end
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 8'd0;
rg_dll <= `BSV_ASSIGNMENT_DELAY 8'd0;
rg_dlm <= `BSV_ASSIGNMENT_DELAY 8'd0;
rg_fcr <= `BSV_ASSIGNMENT_DELAY 8'd0;
rg_ier <= `BSV_ASSIGNMENT_DELAY 8'd0;
rg_lcr <= `BSV_ASSIGNMENT_DELAY 8'd0;
rg_lsr <= `BSV_ASSIGNMENT_DELAY 8'd96;
rg_mcr <= `BSV_ASSIGNMENT_DELAY 8'd0;
rg_msr <= `BSV_ASSIGNMENT_DELAY 8'd0;
rg_scr <= `BSV_ASSIGNMENT_DELAY 8'd0;
rg_state <= `BSV_ASSIGNMENT_DELAY 1'd0;
end
else
begin
if (cfg_verbosity$EN)
cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN;
if (rg_dll$EN) rg_dll <= `BSV_ASSIGNMENT_DELAY rg_dll$D_IN;
if (rg_dlm$EN) rg_dlm <= `BSV_ASSIGNMENT_DELAY rg_dlm$D_IN;
if (rg_fcr$EN) rg_fcr <= `BSV_ASSIGNMENT_DELAY rg_fcr$D_IN;
if (rg_ier$EN) rg_ier <= `BSV_ASSIGNMENT_DELAY rg_ier$D_IN;
if (rg_lcr$EN) rg_lcr <= `BSV_ASSIGNMENT_DELAY rg_lcr$D_IN;
if (rg_lsr$EN) rg_lsr <= `BSV_ASSIGNMENT_DELAY rg_lsr$D_IN;
if (rg_mcr$EN) rg_mcr <= `BSV_ASSIGNMENT_DELAY rg_mcr$D_IN;
if (rg_msr$EN) rg_msr <= `BSV_ASSIGNMENT_DELAY rg_msr$D_IN;
if (rg_scr$EN) rg_scr <= `BSV_ASSIGNMENT_DELAY rg_scr$D_IN;
if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN;
end
if (rg_addr_base$EN)
rg_addr_base <= `BSV_ASSIGNMENT_DELAY rg_addr_base$D_IN;
if (rg_addr_lim$EN) rg_addr_lim <= `BSV_ASSIGNMENT_DELAY rg_addr_lim$D_IN;
if (rg_rbr$EN) rg_rbr <= `BSV_ASSIGNMENT_DELAY rg_rbr$D_IN;
if (rg_thr$EN) rg_thr <= `BSV_ASSIGNMENT_DELAY rg_thr$D_IN;
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
cfg_verbosity = 8'hAA;
rg_addr_base = 64'hAAAAAAAAAAAAAAAA;
rg_addr_lim = 64'hAAAAAAAAAAAAAAAA;
rg_dll = 8'hAA;
rg_dlm = 8'hAA;
rg_fcr = 8'hAA;
rg_ier = 8'hAA;
rg_lcr = 8'hAA;
rg_lsr = 8'hAA;
rg_mcr = 8'hAA;
rg_msr = 8'hAA;
rg_rbr = 8'hAA;
rg_scr = 8'hAA;
rg_state = 1'h0;
rg_thr = 8'hAA;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge CLK)
begin
#0;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
(slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 ||
!slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d19))
begin
v__h1992 = $stime;
#0;
end
v__h1986 = v__h1992 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
(slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 ||
!slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d19))
$display("%0d: %m.rl_process_rd_req: ERROR: UART addr out of bounds",
v__h1986);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
(slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 ||
!slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d19))
$display(" UART base addr 0x%0h limit addr 0x%0h",
rg_addr_base,
rg_addr_lim);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
(slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 ||
!slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d19))
$write(" AXI4 request: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
(slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 ||
!slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d19))
$write("AXI4_Rd_Addr { ", "arid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
(slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 ||
!slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d19))
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
(slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 ||
!slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d19))
$write(", ", "araddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
(slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 ||
!slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d19))
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
(slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 ||
!slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d19))
$write(", ", "arlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
(slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 ||
!slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d19))
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
(slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 ||
!slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d19))
$write(", ", "arsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
(slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 ||
!slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d19))
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
(slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 ||
!slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d19))
$write(", ", "arburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
(slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 ||
!slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d19))
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
(slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 ||
!slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d19))
$write(", ", "arlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
(slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 ||
!slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d19))
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
(slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 ||
!slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d19))
$write(", ", "arcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
(slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 ||
!slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d19))
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
(slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 ||
!slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d19))
$write(", ", "arprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
(slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 ||
!slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d19))
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
(slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 ||
!slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d19))
$write(", ", "arqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
(slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 ||
!slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d19))
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
(slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 ||
!slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d19))
$write(", ", "arregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
(slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 ||
!slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d19))
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
(slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 ||
!slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d19))
$write(", ", "aruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
(slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 ||
!slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d19))
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
(slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 ||
!slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d19))
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
!slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d19 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[1:0] ==
2'd0 &&
1'b0)
begin
v__h2869 = $stime;
#0;
end
v__h2863 = v__h2869 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
!slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d19 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[1:0] ==
2'd0 &&
1'b0)
$display("%0d: %m.rl_process_rd_req: ERROR: UART unsupported addr",
v__h2863);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
!slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d19 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[1:0] ==
2'd0 &&
1'b0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
!slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d19 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[1:0] ==
2'd0 &&
1'b0)
$write("AXI4_Rd_Addr { ", "arid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
!slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d19 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[1:0] ==
2'd0 &&
1'b0)
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
!slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d19 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[1:0] ==
2'd0 &&
1'b0)
$write(", ", "araddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
!slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d19 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[1:0] ==
2'd0 &&
1'b0)
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
!slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d19 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[1:0] ==
2'd0 &&
1'b0)
$write(", ", "arlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
!slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d19 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[1:0] ==
2'd0 &&
1'b0)
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
!slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d19 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[1:0] ==
2'd0 &&
1'b0)
$write(", ", "arsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
!slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d19 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[1:0] ==
2'd0 &&
1'b0)
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
!slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d19 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[1:0] ==
2'd0 &&
1'b0)
$write(", ", "arburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
!slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d19 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[1:0] ==
2'd0 &&
1'b0)
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
!slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d19 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[1:0] ==
2'd0 &&
1'b0)
$write(", ", "arlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
!slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d19 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[1:0] ==
2'd0 &&
1'b0)
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
!slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d19 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[1:0] ==
2'd0 &&
1'b0)
$write(", ", "arcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
!slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d19 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[1:0] ==
2'd0 &&
1'b0)
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
!slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d19 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[1:0] ==
2'd0 &&
1'b0)
$write(", ", "arprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
!slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d19 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[1:0] ==
2'd0 &&
1'b0)
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
!slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d19 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[1:0] ==
2'd0 &&
1'b0)
$write(", ", "arqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
!slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d19 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[1:0] ==
2'd0 &&
1'b0)
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
!slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d19 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[1:0] ==
2'd0 &&
1'b0)
$write(", ", "arregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
!slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d19 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[1:0] ==
2'd0 &&
1'b0)
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
!slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d19 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[1:0] ==
2'd0 &&
1'b0)
$write(", ", "aruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
!slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d19 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[1:0] ==
2'd0 &&
1'b0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
!slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d19 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[1:0] ==
2'd0 &&
1'b0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
!slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d19 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[1:0] ==
2'd0 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[63:5] !=
59'd0)
begin
v__h2357 = $stime;
#0;
end
v__h2351 = v__h2357 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
!slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d19 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[1:0] ==
2'd0 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[63:5] !=
59'd0)
$display("%0d: %m.rl_process_rd_req: ERROR: UART unsupported addr",
v__h2351);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
!slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d19 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[1:0] ==
2'd0 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[63:5] !=
59'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
!slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d19 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[1:0] ==
2'd0 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[63:5] !=
59'd0)
$write("AXI4_Rd_Addr { ", "arid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
!slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d19 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[1:0] ==
2'd0 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[63:5] !=
59'd0)
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
!slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d19 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[1:0] ==
2'd0 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[63:5] !=
59'd0)
$write(", ", "araddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
!slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d19 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[1:0] ==
2'd0 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[63:5] !=
59'd0)
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
!slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d19 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[1:0] ==
2'd0 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[63:5] !=
59'd0)
$write(", ", "arlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
!slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d19 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[1:0] ==
2'd0 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[63:5] !=
59'd0)
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
!slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d19 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[1:0] ==
2'd0 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[63:5] !=
59'd0)
$write(", ", "arsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
!slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d19 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[1:0] ==
2'd0 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[63:5] !=
59'd0)
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
!slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d19 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[1:0] ==
2'd0 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[63:5] !=
59'd0)
$write(", ", "arburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
!slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d19 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[1:0] ==
2'd0 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[63:5] !=
59'd0)
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
!slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d19 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[1:0] ==
2'd0 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[63:5] !=
59'd0)
$write(", ", "arlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
!slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d19 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[1:0] ==
2'd0 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[63:5] !=
59'd0)
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
!slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d19 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[1:0] ==
2'd0 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[63:5] !=
59'd0)
$write(", ", "arcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
!slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d19 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[1:0] ==
2'd0 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[63:5] !=
59'd0)
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
!slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d19 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[1:0] ==
2'd0 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[63:5] !=
59'd0)
$write(", ", "arprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
!slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d19 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[1:0] ==
2'd0 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[63:5] !=
59'd0)
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
!slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d19 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[1:0] ==
2'd0 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[63:5] !=
59'd0)
$write(", ", "arqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
!slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d19 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[1:0] ==
2'd0 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[63:5] !=
59'd0)
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
!slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d19 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[1:0] ==
2'd0 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[63:5] !=
59'd0)
$write(", ", "arregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
!slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d19 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[1:0] ==
2'd0 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[63:5] !=
59'd0)
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
!slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d19 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[1:0] ==
2'd0 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[63:5] !=
59'd0)
$write(", ", "aruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
!slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d19 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[1:0] ==
2'd0 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[63:5] !=
59'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
!slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d19 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[1:0] ==
2'd0 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[63:5] !=
59'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
!slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d19 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[1:0] !=
2'd0)
begin
v__h2200 = $stime;
#0;
end
v__h2194 = v__h2200 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
!slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d19 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[1:0] !=
2'd0)
$display("%0d: %m.rl_process_rd_req: ERROR: UART misaligned addr",
v__h2194);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
!slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d19 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[1:0] !=
2'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
!slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d19 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[1:0] !=
2'd0)
$write("AXI4_Rd_Addr { ", "arid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
!slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d19 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[1:0] !=
2'd0)
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
!slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d19 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[1:0] !=
2'd0)
$write(", ", "araddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
!slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d19 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[1:0] !=
2'd0)
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
!slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d19 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[1:0] !=
2'd0)
$write(", ", "arlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
!slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d19 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[1:0] !=
2'd0)
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
!slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d19 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[1:0] !=
2'd0)
$write(", ", "arsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
!slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d19 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[1:0] !=
2'd0)
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
!slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d19 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[1:0] !=
2'd0)
$write(", ", "arburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
!slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d19 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[1:0] !=
2'd0)
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
!slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d19 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[1:0] !=
2'd0)
$write(", ", "arlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
!slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d19 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[1:0] !=
2'd0)
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
!slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d19 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[1:0] !=
2'd0)
$write(", ", "arcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
!slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d19 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[1:0] !=
2'd0)
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
!slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d19 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[1:0] !=
2'd0)
$write(", ", "arprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
!slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d19 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[1:0] !=
2'd0)
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
!slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d19 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[1:0] !=
2'd0)
$write(", ", "arqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
!slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d19 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[1:0] !=
2'd0)
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
!slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d19 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[1:0] !=
2'd0)
$write(", ", "arregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
!slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d19 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[1:0] !=
2'd0)
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
!slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d19 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[1:0] !=
2'd0)
$write(", ", "aruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
!slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d19 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[1:0] !=
2'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
!slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d19 &&
slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d35[1:0] !=
2'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_cfg_verbosity_read_ULE_1_43___d144)
begin
v__h3288 = $stime;
#0;
end
v__h3282 = v__h3288 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_cfg_verbosity_read_ULE_1_43___d144)
$display("%0d: %m.rl_process_rd_req", v__h3282);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_cfg_verbosity_read_ULE_1_43___d144)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_cfg_verbosity_read_ULE_1_43___d144)
$write("AXI4_Rd_Addr { ", "arid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_cfg_verbosity_read_ULE_1_43___d144)
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_cfg_verbosity_read_ULE_1_43___d144)
$write(", ", "araddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_cfg_verbosity_read_ULE_1_43___d144)
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_cfg_verbosity_read_ULE_1_43___d144)
$write(", ", "arlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_cfg_verbosity_read_ULE_1_43___d144)
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_cfg_verbosity_read_ULE_1_43___d144)
$write(", ", "arsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_cfg_verbosity_read_ULE_1_43___d144)
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_cfg_verbosity_read_ULE_1_43___d144)
$write(", ", "arburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_cfg_verbosity_read_ULE_1_43___d144)
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_cfg_verbosity_read_ULE_1_43___d144)
$write(", ", "arlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_cfg_verbosity_read_ULE_1_43___d144)
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_cfg_verbosity_read_ULE_1_43___d144)
$write(", ", "arcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_cfg_verbosity_read_ULE_1_43___d144)
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_cfg_verbosity_read_ULE_1_43___d144)
$write(", ", "arprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_cfg_verbosity_read_ULE_1_43___d144)
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_cfg_verbosity_read_ULE_1_43___d144)
$write(", ", "arqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_cfg_verbosity_read_ULE_1_43___d144)
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_cfg_verbosity_read_ULE_1_43___d144)
$write(", ", "arregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_cfg_verbosity_read_ULE_1_43___d144)
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_cfg_verbosity_read_ULE_1_43___d144)
$write(", ", "aruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_cfg_verbosity_read_ULE_1_43___d144)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_cfg_verbosity_read_ULE_1_43___d144)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_cfg_verbosity_read_ULE_1_43___d144)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_cfg_verbosity_read_ULE_1_43___d144)
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_cfg_verbosity_read_ULE_1_43___d144)
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_cfg_verbosity_read_ULE_1_43___d144)
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_cfg_verbosity_read_ULE_1_43___d144)
$write("'h%h", rdr_rdata__h3156);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_cfg_verbosity_read_ULE_1_43___d144)
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_cfg_verbosity_read_ULE_1_43___d144)
$write("'h%h", rdr_rresp__h3157);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_cfg_verbosity_read_ULE_1_43___d144)
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_cfg_verbosity_read_ULE_1_43___d144)
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_cfg_verbosity_read_ULE_1_43___d144)
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_cfg_verbosity_read_ULE_1_43___d144)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_cfg_verbosity_read_ULE_1_43___d144)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
(slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 ||
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153))
begin
v__h3576 = $stime;
#0;
end
v__h3570 = v__h3576 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
(slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 ||
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153))
$display("%0d: %m.rl_process_rd_req: ERROR: UART addr out of bounds",
v__h3570);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
(slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 ||
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153))
$display(" UART base addr 0x%0h limit addr 0x%0h",
rg_addr_base,
rg_addr_lim);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
(slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 ||
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153))
$write(" AXI4 request: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
(slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 ||
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153))
$write("AXI4_Wr_Addr { ", "awid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
(slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 ||
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153))
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
(slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 ||
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153))
$write(", ", "awaddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
(slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 ||
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153))
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
(slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 ||
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153))
$write(", ", "awlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
(slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 ||
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153))
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
(slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 ||
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153))
$write(", ", "awsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
(slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 ||
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153))
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
(slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 ||
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153))
$write(", ", "awburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
(slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 ||
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153))
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
(slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 ||
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153))
$write(", ", "awlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
(slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 ||
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153))
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
(slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 ||
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153))
$write(", ", "awcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
(slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 ||
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153))
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
(slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 ||
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153))
$write(", ", "awprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
(slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 ||
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153))
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
(slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 ||
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153))
$write(", ", "awqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
(slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 ||
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153))
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
(slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 ||
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153))
$write(", ", "awregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
(slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 ||
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153))
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
(slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 ||
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153))
$write(", ", "awuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
(slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 ||
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153))
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
(slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 ||
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153))
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[1:0] ==
2'd0 &&
1'b0)
begin
v__h5025 = $stime;
#0;
end
v__h5019 = v__h5025 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[1:0] ==
2'd0 &&
1'b0)
$display("%0d: %m.rl_process_wr_req: ERROR: UART unsupported addr",
v__h5019);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[1:0] ==
2'd0 &&
1'b0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[1:0] ==
2'd0 &&
1'b0)
$write("AXI4_Wr_Addr { ", "awid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[1:0] ==
2'd0 &&
1'b0)
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[1:0] ==
2'd0 &&
1'b0)
$write(", ", "awaddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[1:0] ==
2'd0 &&
1'b0)
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[1:0] ==
2'd0 &&
1'b0)
$write(", ", "awlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[1:0] ==
2'd0 &&
1'b0)
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[1:0] ==
2'd0 &&
1'b0)
$write(", ", "awsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[1:0] ==
2'd0 &&
1'b0)
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[1:0] ==
2'd0 &&
1'b0)
$write(", ", "awburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[1:0] ==
2'd0 &&
1'b0)
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[1:0] ==
2'd0 &&
1'b0)
$write(", ", "awlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[1:0] ==
2'd0 &&
1'b0)
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[1:0] ==
2'd0 &&
1'b0)
$write(", ", "awcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[1:0] ==
2'd0 &&
1'b0)
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[1:0] ==
2'd0 &&
1'b0)
$write(", ", "awprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[1:0] ==
2'd0 &&
1'b0)
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[1:0] ==
2'd0 &&
1'b0)
$write(", ", "awqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[1:0] ==
2'd0 &&
1'b0)
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[1:0] ==
2'd0 &&
1'b0)
$write(", ", "awregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[1:0] ==
2'd0 &&
1'b0)
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[1:0] ==
2'd0 &&
1'b0)
$write(", ", "awuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[1:0] ==
2'd0 &&
1'b0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[1:0] ==
2'd0 &&
1'b0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[1:0] ==
2'd0 &&
1'b0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[1:0] ==
2'd0 &&
1'b0)
$write("AXI4_Wr_Data { ", "wdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[1:0] ==
2'd0 &&
1'b0)
$write("'h%h", slave_xactor_f_wr_data$D_OUT[72:9]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[1:0] ==
2'd0 &&
1'b0)
$write(", ", "wstrb: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[1:0] ==
2'd0 &&
1'b0)
$write("'h%h", slave_xactor_f_wr_data$D_OUT[8:1]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[1:0] ==
2'd0 &&
1'b0)
$write(", ", "wlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_slave_xactor_f_wr_addr_first__50_BITS_92_T_ETC___d322)
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_slave_xactor_f_wr_addr_first__50_BITS_92_T_ETC___d335)
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[1:0] ==
2'd0 &&
1'b0)
$write(", ", "wuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[1:0] ==
2'd0 &&
1'b0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[1:0] ==
2'd0 &&
1'b0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[1:0] ==
2'd0 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[63:5] !=
59'd0)
begin
v__h3915 = $stime;
#0;
end
v__h3909 = v__h3915 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[1:0] ==
2'd0 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[63:5] !=
59'd0)
$display("%0d: %m.rl_process_wr_req: ERROR: UART unsupported addr",
v__h3909);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[1:0] ==
2'd0 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[63:5] !=
59'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[1:0] ==
2'd0 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[63:5] !=
59'd0)
$write("AXI4_Wr_Addr { ", "awid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[1:0] ==
2'd0 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[63:5] !=
59'd0)
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[1:0] ==
2'd0 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[63:5] !=
59'd0)
$write(", ", "awaddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[1:0] ==
2'd0 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[63:5] !=
59'd0)
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[1:0] ==
2'd0 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[63:5] !=
59'd0)
$write(", ", "awlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[1:0] ==
2'd0 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[63:5] !=
59'd0)
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[1:0] ==
2'd0 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[63:5] !=
59'd0)
$write(", ", "awsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[1:0] ==
2'd0 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[63:5] !=
59'd0)
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[1:0] ==
2'd0 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[63:5] !=
59'd0)
$write(", ", "awburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[1:0] ==
2'd0 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[63:5] !=
59'd0)
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[1:0] ==
2'd0 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[63:5] !=
59'd0)
$write(", ", "awlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[1:0] ==
2'd0 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[63:5] !=
59'd0)
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[1:0] ==
2'd0 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[63:5] !=
59'd0)
$write(", ", "awcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[1:0] ==
2'd0 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[63:5] !=
59'd0)
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[1:0] ==
2'd0 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[63:5] !=
59'd0)
$write(", ", "awprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[1:0] ==
2'd0 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[63:5] !=
59'd0)
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[1:0] ==
2'd0 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[63:5] !=
59'd0)
$write(", ", "awqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[1:0] ==
2'd0 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[63:5] !=
59'd0)
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[1:0] ==
2'd0 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[63:5] !=
59'd0)
$write(", ", "awregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[1:0] ==
2'd0 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[63:5] !=
59'd0)
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[1:0] ==
2'd0 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[63:5] !=
59'd0)
$write(", ", "awuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[1:0] ==
2'd0 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[63:5] !=
59'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[1:0] ==
2'd0 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[63:5] !=
59'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[1:0] !=
2'd0)
begin
v__h3763 = $stime;
#0;
end
v__h3757 = v__h3763 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[1:0] !=
2'd0)
$display("%0d: %m.rl_process_wr_req: ERROR: UART misaligned addr",
v__h3757);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[1:0] !=
2'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[1:0] !=
2'd0)
$write("AXI4_Wr_Addr { ", "awid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[1:0] !=
2'd0)
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[1:0] !=
2'd0)
$write(", ", "awaddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[1:0] !=
2'd0)
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[1:0] !=
2'd0)
$write(", ", "awlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[1:0] !=
2'd0)
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[1:0] !=
2'd0)
$write(", ", "awsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[1:0] !=
2'd0)
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[1:0] !=
2'd0)
$write(", ", "awburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[1:0] !=
2'd0)
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[1:0] !=
2'd0)
$write(", ", "awlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[1:0] !=
2'd0)
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[1:0] !=
2'd0)
$write(", ", "awcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[1:0] !=
2'd0)
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[1:0] !=
2'd0)
$write(", ", "awprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[1:0] !=
2'd0)
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[1:0] !=
2'd0)
$write(", ", "awqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[1:0] !=
2'd0)
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[1:0] !=
2'd0)
$write(", ", "awregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[1:0] !=
2'd0)
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[1:0] !=
2'd0)
$write(", ", "awuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[1:0] !=
2'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
!slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d152 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d153 &&
slave_xactor_f_wr_addr_first__50_BITS_92_TO_29_ETC___d156[1:0] !=
2'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_43___d144)
begin
v__h5335 = $stime;
#0;
end
v__h5329 = v__h5335 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_43___d144)
$display("%0d: %m.rl_process_wr_req", v__h5329);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_43___d144)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_43___d144)
$write("AXI4_Wr_Addr { ", "awid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_43___d144)
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_43___d144)
$write(", ", "awaddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_43___d144)
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_43___d144)
$write(", ", "awlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_43___d144)
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_43___d144)
$write(", ", "awsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_43___d144)
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_43___d144)
$write(", ", "awburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_43___d144)
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_43___d144)
$write(", ", "awlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_43___d144)
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_43___d144)
$write(", ", "awcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_43___d144)
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_43___d144)
$write(", ", "awprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_43___d144)
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_43___d144)
$write(", ", "awqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_43___d144)
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_43___d144)
$write(", ", "awregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_43___d144)
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_43___d144)
$write(", ", "awuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_43___d144)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_43___d144)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_43___d144)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_43___d144)
$write("AXI4_Wr_Data { ", "wdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_43___d144)
$write("'h%h", slave_xactor_f_wr_data$D_OUT[72:9]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_43___d144)
$write(", ", "wstrb: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_43___d144)
$write("'h%h", slave_xactor_f_wr_data$D_OUT[8:1]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_43___d144)
$write(", ", "wlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_43___d144 &&
slave_xactor_f_wr_data$D_OUT[0])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_43___d144 &&
!slave_xactor_f_wr_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_43___d144)
$write(", ", "wuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_43___d144)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_43___d144)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_43___d144)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_43___d144)
$write("AXI4_Wr_Resp { ", "bid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_43___d144)
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_43___d144)
$write(", ", "bresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_43___d144)
$write("'h%h", v__h3531);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_43___d144)
$write(", ", "buser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_43___d144)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_43___d144)
$write("\n");
if (EN_set_addr_map && set_addr_map_addr_base[2:0] != 3'd0)
begin
v__h5777 = $stime;
#0;
end
v__h5771 = v__h5777 / 32'd10;
if (EN_set_addr_map && set_addr_map_addr_base[2:0] != 3'd0)
$display("%0d: WARNING: UART.set_addr_map: addr_base 0x%0h is not 8-Byte-aligned",
v__h5771,
set_addr_map_addr_base);
if (EN_set_addr_map && set_addr_map_addr_lim[2:0] != 3'd0)
begin
v__h5887 = $stime;
#0;
end
v__h5881 = v__h5887 / 32'd10;
if (EN_set_addr_map && set_addr_map_addr_lim[2:0] != 3'd0)
$display("%0d: WARNING: UART.set_addr_map: addr_lim 0x%0h is not 8-Byte-aligned",
v__h5881,
set_addr_map_addr_lim);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_receive && NOT_cfg_verbosity_read_ULE_1_43___d144)
$display("UART_Model.rl_receive: received char 0x%0h; new_lsr = 0x%0h",
f_from_console$D_OUT,
new_lsr__h5544);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reset && cfg_verbosity != 8'd0)
begin
v__h1812 = $stime;
#0;
end
v__h1806 = v__h1812 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reset && cfg_verbosity != 8'd0)
$display("%0d: UART.rl_reset", v__h1806);
end
// synopsys translate_on
endmodule // mkUART
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A22OI_PP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__A22OI_PP_BLACKBOX_V
/**
* a22oi: 2-input AND into both inputs of 2-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2))
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__a22oi (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A22OI_PP_BLACKBOX_V
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: lsu_dctl.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
/////////////////////////////////////////////////////////////////
/*
// Description: LSU Data Cache Control and Minor Datapath
// - Tag Comparison - hit/miss.
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
`include "sys.h" // system level definition file which contains the
// time scale definition
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
`include "lsu.h"
module lsu_dctl ( /*AUTOARG*/
// Outputs
lsu_tlu_nucleus_ctxt_m, lsu_quad_word_access_g, so, dctl_rst_l,
lsu_tlu_wsr_inst_e, lsu_l2fill_fpld_e, dva_vld_m_bf,
lsu_no_spc_pref, ifu_tlu_flush_fd_w, ifu_tlu_flush_fd2_w,
ifu_tlu_flush_fd3_w, ifu_lsu_flush_w, lsu_tlu_thrid_d,
lsu_diagnstc_data_sel, lsu_diagnstc_va_sel, lsu_err_addr_sel,
dva_bit_wr_en_e, dva_wr_adr_e, lsu_exu_ldst_miss_w2,
lsu_exu_dfill_vld_w2, lsu_ffu_ld_vld, lsu_ld_miss_wb,
lsu_dtlb_bypass_e, ld_pcx_pkt_g, tlb_ldst_cam_vld, ldxa_internal,
lsu_ifu_ldsta_internal_e, lsu_ifu_ldst_cmplt, lsu_ifu_itlb_en,
lsu_ifu_icache_en, lmq_byp_data_en_w2, lmq_byp_data_fmx_sel,
lmq_byp_data_mxsel0, lmq_byp_data_mxsel1, lmq_byp_data_mxsel2,
lmq_byp_data_mxsel3, lmq_byp_ldxa_mxsel0, lmq_byp_ldxa_mxsel1,
lmq_byp_ldxa_mxsel2, lmq_byp_ldxa_mxsel3, lsu_ld_thrd_byp_sel_e,
dcache_byte_wr_en_e, lsu_dcache_wr_vld_e, lsu_ldstub_g,
lsu_swap_g, lsu_tlu_dtlb_done, lsu_exu_thr_m, merge7_sel_byte0_m,
merge7_sel_byte7_m, merge6_sel_byte1_m, merge6_sel_byte6_m,
merge5_sel_byte2_m, merge5_sel_byte5_m, merge4_sel_byte3_m,
merge4_sel_byte4_m, merge3_sel_byte0_m, merge3_sel_byte3_m,
merge3_sel_byte4_m, merge3_sel_byte7_default_m, merge3_sel_byte_m,
merge2_sel_byte1_m, merge2_sel_byte2_m, merge2_sel_byte5_m,
merge2_sel_byte6_default_m, merge2_sel_byte_m, merge0_sel_byte0_m,
merge0_sel_byte1_m, merge0_sel_byte2_m,
merge0_sel_byte3_default_m, merge0_sel_byte4_m,
merge0_sel_byte5_m, merge0_sel_byte6_m,
merge0_sel_byte7_default_m, merge1_sel_byte0_m,
merge1_sel_byte1_m, merge1_sel_byte2_m,
merge1_sel_byte3_default_m, merge1_sel_byte4_m,
merge1_sel_byte5_m, merge1_sel_byte6_m,
merge1_sel_byte7_default_m, merge0_sel_byte_1h_m,
merge1_sel_byte_1h_m, merge1_sel_byte_2h_m, lsu_dtlb_cam_real_e,
lsu_dtagv_wr_vld_e, lsu_dtag_wrreq_x_e, lsu_dtag_index_sel_x_e,
lsu_dtlb_wr_vld_e, lsu_dtlb_tag_rd_e, lsu_dtlb_data_rd_e,
lsu_dtlb_dmp_vld_e, lsu_dtlb_dmp_all_e, lsu_dtlb_rwindex_vld_e,
lsu_dtlb_invalid_all_l_m, lsu_tlu_tlb_ld_inst_m,
lsu_tlu_tlb_st_inst_m, lsu_tlu_tlb_access_tid_m,
lsu_tlb_data_rd_vld_g, lsu_tlb_st_sel_m, lsu_va_wtchpt0_wr_en_l,
lsu_va_wtchpt1_wr_en_l, lsu_va_wtchpt2_wr_en_l,
lsu_va_wtchpt3_wr_en_l, thread0_m, thread1_m, thread2_m,
thread3_m, lsu_dctldp_thread0_m, lsu_dctldp_thread1_m,
lsu_dctldp_thread2_m, lsu_dctldp_thread3_m, thread0_g, thread1_g,
thread2_g, thread3_g, lsu_tlu_nonalt_ldst_m,
lsu_tlu_xslating_ldst_m, lsu_tlu_ctxt_sel_m, lsu_tlu_write_op_m,
lsu_dtlb_addr_mask_l_e, dva_din_e,
lsu_diagnstc_dtagv_prty_invrt_e, lsu_ifu_asi_load,
lsu_ifu_asi_thrid, lsu_ifu_asi_vld, lsu_quad_asi_e,
lsu_local_ldxa_sel_g, lsu_dtag_rsel_m, lsu_tlbop_force_swo,
lsu_atomic_pkt2_bsel_g, lsu_dcache_tag_perror_g,
lsu_dcache_data_perror_g, lsu_ifu_l2_unc_error,
lsu_ifu_l2_corr_error, lsu_ifu_dcache_data_perror,
lsu_ifu_dcache_tag_perror, lsu_ifu_error_tid, lsu_ifu_io_error,
lsu_tlu_squash_va_oor_m, lsu_squash_va_oor_m, tlb_cam_hit_g,
lsu_st_hw_le_g, lsu_st_w_or_dbl_le_g, lsu_st_x_le_g,
lsu_swap_sel_default_g, lsu_swap_sel_default_byte_7_2_g,
lsu_st_rmo_m, lsu_bst_in_pipe_m, lsu_snap_blk_st_m, lsu_blk_st_m,
lsu_blkst_pgnum_m, lsu_ffu_blk_asi_e, lsu_blk_asi_m,
lsu_nonalt_nucl_access_m, dcache_alt_mx_sel_e,
dcache_alt_mx_sel_e_bf, dcache_rvld_e, lsu_dc_iob_access_e,
lsu_ifu_ldst_miss_w, lsu_ifu_dc_parity_error_w2,
lsu_ldst_inst_vld_e, lsu_local_ldxa_tlbrd_sel_g,
lsu_local_diagnstc_tagrd_sel_g, lsu_va_wtchpt_sel_g,
asi_state_wr_thrd, thread0_d, thread1_d, thread2_d, thread3_d,
tlu_lsu_asi_update_g, pctxt_state_wr_thrd, sctxt_state_wr_thrd,
thread_pctxt, thread_sctxt, thread_actxt, thread_default,
thread0_ctxt, thread1_ctxt, thread2_ctxt, thread3_ctxt,
pid_state_wr_en, thread0_e, thread1_e, thread2_e, thread3_e,
dfture_tap_wr_mx_sel, lctl_rst, lsu_ctl_state_wr_en,
lsuctl_ctlbits_wr_en, dfture_tap_rd_en, bist_tap_wr_en,
bistctl_wr_en, bist_ctl_reg_wr_en, mrgn_tap_wr_en, ldiagctl_wr_en,
misc_ctl_sel_din, lsu_asi_sel_fmx1, lsu_asi_sel_fmx2,
tlb_access_en0_g, tlb_access_en1_g, tlb_access_en2_g,
tlb_access_en3_g, tlb_access_sel_thrd0, tlb_access_sel_thrd1,
tlb_access_sel_thrd2, tlb_access_sel_default, mrgnctl_wr_en,
hpv_priv_m, hpstate_en_m, dcache_arry_data_sel_m, dtlb_bypass_m,
lsu_alt_space_m, atomic_m, ldst_dbl_m, fp_ldst_m, lda_internal_m,
sta_internal_m, cam_real_m, data_rd_vld_g, tag_rd_vld_g,
ldst_sz_m, asi_internal_m, rd_only_ltlb_asi_e, wr_only_ltlb_asi_e,
dfill_tlb_asi_e, ifill_tlb_asi_e, nofault_asi_m, as_if_user_asi_m,
atomic_asi_m, phy_use_ec_asi_m, phy_byp_ec_asi_m, quad_asi_m,
binit_quad_asi_m, blk_asi_m, recognized_asi_m, strm_asi_m,
mmu_rd_only_asi_m, rd_only_asi_m, wr_only_asi_m, unimp_asi_m,
va_wtchpt_cmp_en_m, lsu_tlu_async_ttype_vld_w2,
lsu_tlu_async_ttype_w2, lsu_tlu_async_tid_w2, async_tlb_index,
l2fill_vld_m, ld_thrd_byp_mxsel_m, morphed_addr_m,
signed_ldst_byte_m, signed_ldst_hw_m, signed_ldst_w_m,
lsu_tlb_asi_data_perr_g, lsu_tlb_asi_tag_perr_g, lsu_sscan_data,
lsu_ld_inst_vld_g, lsu_dcache_rand, lsu_encd_way_hit,
lsu_way_hit_or, lsu_memref_m, lsu_flsh_inst_m,
lsu_ifu_asi_data_en_l, lsu_dcache_fill_addr_e,
lsu_dcache_fill_addr_e_err, lsu_thread_g, lmq_ldd_vld,
lsu_bist_rsel_way_e, lsu_dcache_fill_way_e, lmq_ld_addr_b3,
lsu_outstanding_rmo_st_max, lsu_dcfill_data_mx_sel_e,
// Inputs
si, se, sehold, rst_tri_en, rclk, grst_l, arst_l,
lsu_diag_va_prty_invrt, dva_svld_e, dva_snp_bit_wr_en_e,
dva_snp_addr_e, lsu_tte_data_cp_g, lsu_l2fill_vld, ld_inst_vld_e,
st_inst_vld_e, ifu_lsu_ldst_fp_e, ldst_sz_e,
lsu_ldst_va_b12_b11_m, lsu_ldst_va_b7_b0_m, ifu_lsu_rd_e,
tlb_cam_hit, ifu_tlu_sraddr_d, ifu_tlu_wsr_inst_d,
ifu_lsu_alt_space_d, tlu_lsu_int_ldxa_vld_w2,
tlu_lsu_int_ld_ill_va_w2, tlu_lsu_ldxa_tid_w2,
ifu_lsu_ldxa_data_vld_w2, ifu_lsu_ldxa_illgl_va_w2,
ifu_lsu_ldxa_tid_w2, ifu_lsu_asi_rd_unc, tlu_lsu_tl_zero,
ifu_lsu_thrid_s, ifu_lsu_ldst_dbl_e, ld_stb_full_raw_w2,
ld_sec_active, ifu_tlu_inst_vld_m, lsu_l2fill_bendian_m,
lmq0_l2fill_fpld, lmq1_l2fill_fpld, lmq2_l2fill_fpld,
lmq3_l2fill_fpld, cache_way_hit_buf1, cache_hit, lmq0_byp_misc_sz,
lmq1_byp_misc_sz, lmq2_byp_misc_sz, lmq3_byp_misc_sz,
lsu_l2fill_sign_extend_m, lsu_l1hit_sign_extend_e,
tlu_lsu_pstate_cle, tlu_lsu_pstate_am, tlb_pgnum, tlb_demap_nctxt,
tlb_demap_pctxt, tlb_demap_sctxt, tlb_demap_actxt,
tlb_demap_thrid, ifu_lsu_casa_e, ifu_lsu_ldstub_e, ifu_lsu_swap_e,
lsu_atm_st_cmplt_e, lsu_cpx_pkt_atm_st_cmplt,
spu_lsu_ldxa_data_vld_w2, spu_lsu_ldxa_illgl_va_w2,
spu_lsu_ldxa_tid_w2, spu_lsu_stxa_ack_tid, spu_lsu_stxa_ack,
spu_lsu_unc_error_w2, spu_lsu_int_w2, tlu_lsu_stxa_ack,
tlu_lsu_stxa_ack_tid, lsu_tlb_invert_endian_g, lmq0_ncache_ld,
lmq1_ncache_ld, lmq2_ncache_ld, lmq3_ncache_ld, ifu_tlu_mb_inst_e,
ifu_tlu_flsh_inst_e, lsu_stb_empty, tlu_dtlb_tag_rd_g,
tlu_dtlb_data_rd_g, tlu_dtlb_dmp_vld_g, tlu_dtlb_dmp_all_g,
tlu_dtlb_rw_index_vld_g, tlu_dtlb_invalidate_all_g,
lsu_st_wr_dcache, tlu_lsu_asi_update_m, tlu_lsu_tid_m,
lsu_rd_dtag_parity_g, dcache_rparity_err_wb,
lsu_diagnstc_wr_data_b0, lsu_byp_ldd_oddrd_m, tlu_lsu_redmode,
tlu_lsu_redmode_rst_d1, dva_vld_m, lsu_dfill_tid_e,
ifu_lsu_asi_ack, lsu_intrpt_cmplt, lsu_iobrdge_tap_rq_type_b8,
lsu_iobrdge_tap_rq_type_b6_b3, lsu_iobrdge_tap_rq_type_b1_b0,
lsu_iobrdge_fwd_pkt_vld, lsu_cpx_ld_dtag_perror_e,
lsu_cpx_ld_dcache_perror_e, lsu_cpx_pkt_ld_err, ifu_lsu_nceen,
tlu_lsu_ldxa_async_data_vld, tlu_lsu_hpv_priv, tlu_lsu_hpstate_en,
ifu_lsu_memref_d, ifu_lsu_pref_inst_e, lsu_pref_pcx_req,
lsu_cpx_pkt_prefetch2, lsu_ld_pcx_rq_sel_d2,
lsu_pcx_req_squash_d1, lsu_bld_helper_cmplt_m, lsu_bld_cnt_m,
lsu_bld_reset, ffu_lsu_blk_st_e, lsu_stb_rmo_st_issue,
lsu_cpx_rmo_st_ack, lsu_dfq_flsh_cmplt, stb_cam_hit,
ifu_tlu_flush_m, ctu_sscan_tid, tte_data_perror_unc,
asi_tte_data_perror, asi_tte_tag_perror, tlu_dtlb_rw_index_g,
lsu_local_early_flush_g, lsu_dfq_vld, gdbginit_l, dc_direct_map,
asi_d, lsu_dctl_asi_state_m, lsu_ldst_va_g, lsu_ifu_err_addr_b39,
lsu_dp_ctl_reg0, lsu_dp_ctl_reg1, lsu_dp_ctl_reg2,
lsu_dp_ctl_reg3, ldd_in_dfq_out, dcache_iob_addr_e,
mbist_dcache_index, mbist_dcache_word, lsu_diagnstc_wr_addr_e,
st_dcfill_addr, lsu_dfq_ld_vld, lsu_dfq_st_vld, lmq0_ldd_vld,
lmq1_ldd_vld, lmq2_ldd_vld, lmq3_ldd_vld, lsu_dfq_byp_tid,
dfq_byp_ff_en, lsu_dcache_iob_way_e, mbist_dcache_way,
lsu_diagnstc_wr_way_e, lsu_st_way_e, lmq0_pcx_pkt_way,
lmq1_pcx_pkt_way, lmq2_pcx_pkt_way, lmq3_pcx_pkt_way,
lmq0_ld_rq_type, lmq1_ld_rq_type, lmq2_ld_rq_type,
lmq3_ld_rq_type, lmq0_pcx_pkt_addr, lmq1_pcx_pkt_addr,
lmq2_pcx_pkt_addr, lmq3_pcx_pkt_addr, lsu_ttype_vld_m2,
tlu_early_flush_pipe2_w, lsu_st_dcfill_size_e, mbist_dcache_write,
mbist_dcache_read
) ;
output lsu_tlu_nucleus_ctxt_m ;// access is nucleus context
output lsu_quad_word_access_g ; // 128b ld request.
input si;
input se;
input sehold ;
input rst_tri_en ;
output so;
input rclk ;
input grst_l;
input arst_l;
output dctl_rst_l;
input lsu_diag_va_prty_invrt ;
input dva_svld_e ;
input [15:0] dva_snp_bit_wr_en_e;
input [4:0] dva_snp_addr_e;
input lsu_tte_data_cp_g ; // cp bit from tlb
input lsu_l2fill_vld ; // fill from dfq to d$.
input ld_inst_vld_e ; // load accesses d$.
input st_inst_vld_e ; // load accesses d$.
input ifu_lsu_ldst_fp_e ; // fp load or store
input [1:0] ldst_sz_e ; // sz of ld/st xsaction.
input [12:11] lsu_ldst_va_b12_b11_m;
input [7:0] lsu_ldst_va_b7_b0_m;
input [4:0] ifu_lsu_rd_e; // primary rd of ld
input tlb_cam_hit ; // xlation hits in tlb.
// Read/Write Privileged State Register Access.
input [6:0] ifu_tlu_sraddr_d ; // addr of sr(st/pr)
input ifu_tlu_wsr_inst_d ; // valid wr sr(st/pr)
output lsu_tlu_wsr_inst_e ; // valid wr sr(st/pr)
input ifu_lsu_alt_space_d; // alternate space ld/st
input tlu_lsu_int_ldxa_vld_w2 ; // tlu ldxa data is valid (intrpt/scpd)
input tlu_lsu_int_ld_ill_va_w2 ; // tlu ldxa'va is invalid (intrpt/scpd)
input [1:0] tlu_lsu_ldxa_tid_w2 ; // thread id for tlu ldxa data.
input ifu_lsu_ldxa_data_vld_w2 ; // ifu ldxa data is valid
input ifu_lsu_ldxa_illgl_va_w2 ; // ifu ldxa with illgl va
input [1:0] ifu_lsu_ldxa_tid_w2 ; // thread id for ifu ldxa data.
input ifu_lsu_asi_rd_unc ; // unc error for tlb rd
input [3:0] tlu_lsu_tl_zero ; // trap level is zero.
input [1:0] ifu_lsu_thrid_s ; // thread id
input ifu_lsu_ldst_dbl_e ; // ldd, atomic quad.
input ld_stb_full_raw_w2 ; // full raw for load-thread0
input ld_sec_active ; // secondary bypassing
input ifu_tlu_inst_vld_m ; // inst vld in w stage
input lsu_l2fill_bendian_m ;
//input lsu_l2fill_fpld_e ; // fp load
output lsu_l2fill_fpld_e ; // fp load
input lmq0_l2fill_fpld ; // fp load
input lmq1_l2fill_fpld ; // fp load
input lmq2_l2fill_fpld ; // fp load
input lmq3_l2fill_fpld ; // fp load
input [3:0] cache_way_hit_buf1 ; // hit in set of cache.
input cache_hit;
//input [3:0] lsu_byp_misc_addr_m ; // lower 3bits of addr for ldxa/raw etc
input [1:0] lmq0_byp_misc_sz ; // size for ldxa/raw etc
input [1:0] lmq1_byp_misc_sz ; // size for ldxa/raw etc
input [1:0] lmq2_byp_misc_sz ; // size for ldxa/raw etc
input [1:0] lmq3_byp_misc_sz ; // size for ldxa/raw etc
input lsu_l2fill_sign_extend_m ; // l2fill requires sign-extension
input lsu_l1hit_sign_extend_e ; // l1hit requires sign-extension
input [3:0] tlu_lsu_pstate_cle ; // current little endian
input [3:0] tlu_lsu_pstate_am ; // address mask
input [39:10] tlb_pgnum ;
input tlb_demap_nctxt; // demap with nctxt
input tlb_demap_pctxt; // demap with pctxt
input tlb_demap_sctxt; // demap with sctxt
input tlb_demap_actxt; // demap w autodemap ctxt
input [1:0] tlb_demap_thrid; // demap thrid
input ifu_lsu_casa_e ; // compare-swap instr
input ifu_lsu_ldstub_e ; // ldstub
input ifu_lsu_swap_e ; // swap
input lsu_atm_st_cmplt_e ; // atm st ack will restart thread
input lsu_cpx_pkt_atm_st_cmplt ; // applies to atomic ld also.
input spu_lsu_ldxa_data_vld_w2 ; // ldxa data from spu is valid
input spu_lsu_ldxa_illgl_va_w2 ; // ldxa data from spu with illgl va
input [1:0] spu_lsu_ldxa_tid_w2 ; // ldxa data from spu is valid
input [1:0] spu_lsu_stxa_ack_tid ; // stxa data from spu is valid
input spu_lsu_stxa_ack ; // write to sdata reg complete
input spu_lsu_unc_error_w2 ;
input spu_lsu_int_w2 ; // spu disrupting trap.
input tlu_lsu_stxa_ack ; // for mmu reads/writes/demaps
input [1:0] tlu_lsu_stxa_ack_tid ; // for mmu reads/writes/demaps - tid
input lsu_tlb_invert_endian_g ;
//input lsu_ncache_ld_e ; // non-cacheable ld from dfq
input lmq0_ncache_ld;
input lmq1_ncache_ld;
input lmq2_ncache_ld;
input lmq3_ncache_ld;
input ifu_tlu_mb_inst_e ; // membar instruction
input ifu_tlu_flsh_inst_e ; // flush instruction
input [3:0] lsu_stb_empty ; // thread's stb is empty
//input tlu_dtlb_wr_vld_g ;
input tlu_dtlb_tag_rd_g ;
input tlu_dtlb_data_rd_g ;
input tlu_dtlb_dmp_vld_g ;
input tlu_dtlb_dmp_all_g ;
input tlu_dtlb_rw_index_vld_g ;
input tlu_dtlb_invalidate_all_g ;
input lsu_st_wr_dcache ;
input tlu_lsu_asi_update_m ; // update asi
input [1:0] tlu_lsu_tid_m ; // thread for asi update
input [3:0] lsu_rd_dtag_parity_g; // calculated tag parity
input dcache_rparity_err_wb; // calculated tag parity
input lsu_diagnstc_wr_data_b0 ;
input lsu_byp_ldd_oddrd_m ; // rd fill for non-alt ldd
input [3:0] tlu_lsu_redmode ; // redmode
input [3:0] tlu_lsu_redmode_rst_d1 ; // redmode
//input [2:0] const_cpuid ; // cpu's id
input [3:0] dva_vld_m ; // valid bits for cache.
output [3:0] dva_vld_m_bf;
input [1:0] lsu_dfill_tid_e ; // thread id
input ifu_lsu_asi_ack; // asi ack from ifu
input [3:0] lsu_intrpt_cmplt ; // intrpt can restart thread
//input [8:0] lsu_iobrdge_tap_rq_type ;
input [8:8] lsu_iobrdge_tap_rq_type_b8 ;
input [6:3] lsu_iobrdge_tap_rq_type_b6_b3 ;
input [1:0] lsu_iobrdge_tap_rq_type_b1_b0 ;
input lsu_iobrdge_fwd_pkt_vld ;
input lsu_cpx_ld_dtag_perror_e ; // dtag parity error on issue
input lsu_cpx_ld_dcache_perror_e ;// dcache parity error on issue
//input [1:1] lsu_cpx_atm_st_err ; // atomic st error field
input [1:0] lsu_cpx_pkt_ld_err ; // err field - cpx ld pkt
input [3:0] ifu_lsu_nceen ; // uncorrectible error enable
input tlu_lsu_ldxa_async_data_vld ; // tlu_lsu_ldxa_data_vld is for async op.
input [3:0] tlu_lsu_hpv_priv ; // hypervisor privilege modified
input [3:0] tlu_lsu_hpstate_en ; // enable bit from hpstate
input ifu_lsu_memref_d;
input ifu_lsu_pref_inst_e ; // prefetch inst
input lsu_pref_pcx_req ; // pref sent to pcx
input lsu_cpx_pkt_prefetch2 ; // ld is prefetch
// pref counter
input [3:0] lsu_ld_pcx_rq_sel_d2 ;
input lsu_pcx_req_squash_d1;
input lsu_bld_helper_cmplt_m ; // bld helper completes.
input [2:0] lsu_bld_cnt_m ;
input lsu_bld_reset ;
output [3:0] lsu_no_spc_pref;
input ffu_lsu_blk_st_e ; // blk st helper signalled by ffu
input [3:0] lsu_stb_rmo_st_issue ; // thread's stb issues rmo st
input [3:0] lsu_cpx_rmo_st_ack ; // rmo ack clears
input [3:0] lsu_dfq_flsh_cmplt ;
input stb_cam_hit ;
input ifu_tlu_flush_m;
output ifu_tlu_flush_fd_w;
output ifu_tlu_flush_fd2_w;
output ifu_tlu_flush_fd3_w;
output ifu_lsu_flush_w;
input [3:0] ctu_sscan_tid ;
//input tte_data_perror_corr ;
input tte_data_perror_unc ;
input asi_tte_data_perror ;
input asi_tte_tag_perror ;
input [5:0] tlu_dtlb_rw_index_g ;
input lsu_local_early_flush_g ;
//input lsu_error_pa_b39_m ;
input lsu_dfq_vld;
input gdbginit_l ;
input dc_direct_map ;
output [1:0] lsu_tlu_thrid_d ;
output [3:0] lsu_diagnstc_data_sel ;
output [3:0] lsu_diagnstc_va_sel ;
output [2:0] lsu_err_addr_sel ;
output [15:0] dva_bit_wr_en_e;
output [10:6] dva_wr_adr_e;
output lsu_exu_ldst_miss_w2 ; // load misses in d$.
//output [3:0] lsu_way_hit ; // ld/st access hits in d$.
output lsu_exu_dfill_vld_w2 ; // data fill to irf(exu).
output lsu_ffu_ld_vld ; // fp load writes to frf
output lsu_ld_miss_wb ; // load misses in d$.
//output lsu_ld_hit_wb ; // load hits in d$.
output lsu_dtlb_bypass_e ; // dtlb is bypassed
output [`LMQ_WIDTH-1:40] ld_pcx_pkt_g ; // ld miss pkt for thread.
output tlb_ldst_cam_vld ;
//output stxa_internal ; // internal stxa, stg g
output ldxa_internal ; // internal ldxa, stg g
output lsu_ifu_ldsta_internal_e ; // any internal asi
output [3:0] lsu_ifu_ldst_cmplt ;
output [3:0] lsu_ifu_itlb_en ;
output [3:0] lsu_ifu_icache_en ;
output [3:0] lmq_byp_data_en_w2 ;
output [3:0] lmq_byp_data_fmx_sel ; // final data sel for lmq byp
output [3:0] lmq_byp_data_mxsel0 ; // ldxa vs stb bypass data sel.
output [3:0] lmq_byp_data_mxsel1 ; // ldxa vs stb bypass data sel.
output [3:0] lmq_byp_data_mxsel2 ; // ldxa vs stb bypass data sel.
output [3:0] lmq_byp_data_mxsel3 ; // ldxa vs stb bypass data sel.
output [2:0] lmq_byp_ldxa_mxsel0 ; // ldxa data sel - thread0
output [2:0] lmq_byp_ldxa_mxsel1 ; // ldxa data sel - thread1
output [2:0] lmq_byp_ldxa_mxsel2 ; // ldxa data sel - thread2
output [2:0] lmq_byp_ldxa_mxsel3 ; // ldxa data sel - thread3
output [2:0] lsu_ld_thrd_byp_sel_e ;
output [15:0] dcache_byte_wr_en_e ; // 16-byte write enable mask.
output lsu_dcache_wr_vld_e ; // write to dcache.
output lsu_ldstub_g ; // ldstub(a) instruction
output lsu_swap_g ; // swap(a) instruction
output lsu_tlu_dtlb_done; // dtlb rd/dmp/wr cmplt
output [1:0] lsu_exu_thr_m ;
output merge7_sel_byte0_m;
output merge7_sel_byte7_m;
output merge6_sel_byte1_m;
output merge6_sel_byte6_m;
output merge5_sel_byte2_m;
output merge5_sel_byte5_m;
output merge4_sel_byte3_m;
output merge4_sel_byte4_m;
output merge3_sel_byte0_m;
output merge3_sel_byte3_m;
output merge3_sel_byte4_m;
output merge3_sel_byte7_default_m;
output merge3_sel_byte_m ;
output merge2_sel_byte1_m;
output merge2_sel_byte2_m;
output merge2_sel_byte5_m;
output merge2_sel_byte6_default_m;
output merge2_sel_byte_m ;
output merge0_sel_byte0_m, merge0_sel_byte1_m;
output merge0_sel_byte2_m, merge0_sel_byte3_default_m;
output merge0_sel_byte4_m, merge0_sel_byte5_m;
output merge0_sel_byte6_m, merge0_sel_byte7_default_m;
output merge1_sel_byte0_m, merge1_sel_byte1_m;
output merge1_sel_byte2_m, merge1_sel_byte3_default_m;
output merge1_sel_byte4_m, merge1_sel_byte5_m;
output merge1_sel_byte6_m, merge1_sel_byte7_default_m;
output merge0_sel_byte_1h_m ;
output merge1_sel_byte_1h_m, merge1_sel_byte_2h_m ;
output lsu_dtlb_cam_real_e ;
output lsu_dtagv_wr_vld_e ;
output lsu_dtag_wrreq_x_e ;
output lsu_dtag_index_sel_x_e ;
output lsu_dtlb_wr_vld_e ;
output lsu_dtlb_tag_rd_e ;
output lsu_dtlb_data_rd_e ;
output lsu_dtlb_dmp_vld_e ;
output lsu_dtlb_dmp_all_e ;
output lsu_dtlb_rwindex_vld_e ;
output lsu_dtlb_invalid_all_l_m ;
output lsu_tlu_tlb_ld_inst_m ;
output lsu_tlu_tlb_st_inst_m ;
output [1:0] lsu_tlu_tlb_access_tid_m ;
output lsu_tlb_data_rd_vld_g ;
output [3:0] lsu_tlb_st_sel_m ;
output lsu_va_wtchpt0_wr_en_l;
output lsu_va_wtchpt1_wr_en_l;
output lsu_va_wtchpt2_wr_en_l;
output lsu_va_wtchpt3_wr_en_l;
output thread0_m;
output thread1_m;
output thread2_m;
output thread3_m;
output lsu_dctldp_thread0_m;
output lsu_dctldp_thread1_m;
output lsu_dctldp_thread2_m;
output lsu_dctldp_thread3_m;
output thread0_g;
output thread1_g;
output thread2_g;
output thread3_g;
output lsu_tlu_nonalt_ldst_m ; // non-alternate load or store
output lsu_tlu_xslating_ldst_m ;// xslating ldst,atomic etc
output [2:0] lsu_tlu_ctxt_sel_m; // context selected:0-p,1-s,2-n
output lsu_tlu_write_op_m; // fault occurs for data write operation
output lsu_dtlb_addr_mask_l_e ; // address mask applies
output dva_din_e;
output lsu_diagnstc_dtagv_prty_invrt_e ;
output lsu_ifu_asi_load; // asi load to ifu
output [1:0] lsu_ifu_asi_thrid; // asi event thrid to ifu
output lsu_ifu_asi_vld; // asi event vld - ld+st
output lsu_quad_asi_e ;
//output lsu_tlu_64kpg_hit_g ; // 64k page page accessed
output lsu_local_ldxa_sel_g;
output [3:0] lsu_dtag_rsel_m ; // dtag way sel
output lsu_tlbop_force_swo ;
output [2:0] lsu_atomic_pkt2_bsel_g ;
output lsu_dcache_tag_perror_g ; // dcache tag parity error
output lsu_dcache_data_perror_g ; // dcache data parity error
output lsu_ifu_l2_unc_error ; // l2 uncorrectible error
output lsu_ifu_l2_corr_error ; // l2 correctible error
output lsu_ifu_dcache_data_perror ; // dcache data parity error
output lsu_ifu_dcache_tag_perror ; // dcache tag parity error
output [1:0] lsu_ifu_error_tid ; // thread id for error
output lsu_ifu_io_error ; // error on io ld
//output [1:0] lsu_tlu_derr_tid_g ; // daccess error tid
output lsu_tlu_squash_va_oor_m ; // squash va_oor for mem-op.
output lsu_squash_va_oor_m ; // squash va_oor for mem-op.
output tlb_cam_hit_g ; // xlation hits in tlb.
output lsu_st_hw_le_g;
output lsu_st_w_or_dbl_le_g;
output lsu_st_x_le_g;
output lsu_swap_sel_default_g;
output lsu_swap_sel_default_byte_7_2_g;
output lsu_st_rmo_m ; // rmo store in m stage
output lsu_bst_in_pipe_m ; // 1st helper for bst.
output lsu_snap_blk_st_m ; // snap blk st state
output lsu_blk_st_m ; // blk st in m
output [39:10] lsu_blkst_pgnum_m ;
output lsu_ffu_blk_asi_e ; // blk
output lsu_blk_asi_m ;
output lsu_nonalt_nucl_access_m ;
//output [3:0] lsu_spu_stb_empty ;
output dcache_alt_mx_sel_e;
output dcache_alt_mx_sel_e_bf;
output dcache_rvld_e;
output lsu_dc_iob_access_e ; // dcache iob access
output lsu_ifu_ldst_miss_w ;
output lsu_ifu_dc_parity_error_w2;
output lsu_ldst_inst_vld_e;
output lsu_local_ldxa_tlbrd_sel_g;
output lsu_local_diagnstc_tagrd_sel_g;
output lsu_va_wtchpt_sel_g;
input [7:0] asi_d;
input [7:0] lsu_dctl_asi_state_m;
output [3:0] asi_state_wr_thrd;
output thread0_d;
output thread1_d;
output thread2_d;
output thread3_d;
output tlu_lsu_asi_update_g;
output [3:0] pctxt_state_wr_thrd ;
output [3:0] sctxt_state_wr_thrd ;
output thread_pctxt;
output thread_sctxt;
output thread_actxt;
output thread_default;
output thread0_ctxt;
output thread1_ctxt;
output thread2_ctxt;
output thread3_ctxt;
output [3:0] pid_state_wr_en;
output thread0_e;
output thread1_e;
output thread2_e;
output thread3_e;
output dfture_tap_wr_mx_sel;
output [3:0] lctl_rst;
output [3:0] lsu_ctl_state_wr_en;
output [3:0] lsuctl_ctlbits_wr_en;
output [3:0] dfture_tap_rd_en;
output bist_tap_wr_en;
output bistctl_wr_en;
output bist_ctl_reg_wr_en;
output mrgn_tap_wr_en;
output ldiagctl_wr_en;
output [3:0] misc_ctl_sel_din ;
output [2:0] lsu_asi_sel_fmx1;
output [2:0] lsu_asi_sel_fmx2;
output tlb_access_en0_g;
output tlb_access_en1_g;
output tlb_access_en2_g;
output tlb_access_en3_g;
output tlb_access_sel_thrd0;
output tlb_access_sel_thrd1;
output tlb_access_sel_thrd2;
output tlb_access_sel_default;
input [7:0] lsu_ldst_va_g;
output mrgnctl_wr_en;
input lsu_ifu_err_addr_b39;
input [5:0] lsu_dp_ctl_reg0;
input [5:0] lsu_dp_ctl_reg1;
input [5:0] lsu_dp_ctl_reg2;
input [5:0] lsu_dp_ctl_reg3;
input ldd_in_dfq_out; //from qctl2
output hpv_priv_m;
output hpstate_en_m;
output dcache_arry_data_sel_m;
output dtlb_bypass_m;
output lsu_alt_space_m;
output atomic_m;
output ldst_dbl_m;
output fp_ldst_m;
output lda_internal_m;
output sta_internal_m;
output cam_real_m;
output data_rd_vld_g;
output tag_rd_vld_g;
output [1:0] ldst_sz_m;
output asi_internal_m;
// output ld_inst_vld_unflushed;
// output st_inst_vld_unflushed;
output rd_only_ltlb_asi_e;
output wr_only_ltlb_asi_e;
output dfill_tlb_asi_e;
output ifill_tlb_asi_e;
output nofault_asi_m;
output as_if_user_asi_m;
output atomic_asi_m;
output phy_use_ec_asi_m;
output phy_byp_ec_asi_m;
output quad_asi_m;
output binit_quad_asi_m;
output blk_asi_m;
output recognized_asi_m;
output strm_asi_m;
output mmu_rd_only_asi_m;
output rd_only_asi_m;
output wr_only_asi_m;
output unimp_asi_m;
output va_wtchpt_cmp_en_m;
output lsu_tlu_async_ttype_vld_w2 ; // daccess error - asynchronous
output [6:0] lsu_tlu_async_ttype_w2 ;
output [1:0] lsu_tlu_async_tid_w2 ; // asynchronous trap - thread
output [5:0] async_tlb_index ;
//=========================================
//dc_fill CP
//=========================================
output l2fill_vld_m; //to qdp1
output [3:0] ld_thrd_byp_mxsel_m ; //to qdp1
output [7:0] morphed_addr_m; //to dcdp
output signed_ldst_byte_m; //to dcdp
// output unsigned_ldst_byte_m; //to dcdp
output signed_ldst_hw_m; //to dcdp
// output unsigned_ldst_hw_m; //to dcdp
output signed_ldst_w_m; //to dcdp
// output unsigned_ldst_w_m; //to dcdp
output lsu_tlb_asi_data_perr_g ;
output lsu_tlb_asi_tag_perr_g ;
output [14:13] lsu_sscan_data ;
output [3:0] lsu_ld_inst_vld_g ;
output [1:0] lsu_dcache_rand;
output [1:0] lsu_encd_way_hit;
output lsu_way_hit_or;
// output lsu_quad_asi_g;
output lsu_memref_m ;
output lsu_flsh_inst_m ;
output lsu_ifu_asi_data_en_l ;
//dcfill_addr [10:0]
input [7:0] dcache_iob_addr_e;
input [6:0] mbist_dcache_index;
input mbist_dcache_word;
input [10:0] lsu_diagnstc_wr_addr_e;
input [10:0] st_dcfill_addr;
output [10:3] lsu_dcache_fill_addr_e;
output [10:4] lsu_dcache_fill_addr_e_err;
input lsu_dfq_ld_vld;
input lsu_dfq_st_vld;
output [3:0] lsu_thread_g;
//=========================================
//LMQ thread sel
//=========================================
input lmq0_ldd_vld; //from qdp1
input lmq1_ldd_vld;
input lmq2_ldd_vld;
input lmq3_ldd_vld;
output lmq_ldd_vld; //to qctl2
input [1:0] lsu_dfq_byp_tid; //from qdp2
input dfq_byp_ff_en; //from qctl2
input [1:0] lsu_dcache_iob_way_e; //from qdp2
input [1:0] mbist_dcache_way;
output [3:0] lsu_bist_rsel_way_e;
input [1:0] lsu_diagnstc_wr_way_e ; //from dctldp
input [1:0] lsu_st_way_e; //from qdp2
input [1:0] lmq0_pcx_pkt_way; //from qctl1
input [1:0] lmq1_pcx_pkt_way;
input [1:0] lmq2_pcx_pkt_way;
input [1:0] lmq3_pcx_pkt_way;
output [3:0] lsu_dcache_fill_way_e;
input [2:0] lmq0_ld_rq_type ; // for identifying atomic ld.
input [2:0] lmq1_ld_rq_type ; // for identifying atomic ld.
input [2:0] lmq2_ld_rq_type ; // for identifying atomic ld.
input [2:0] lmq3_ld_rq_type ; // for identifying atomic ld.
input [10:0] lmq0_pcx_pkt_addr;
input [10:0] lmq1_pcx_pkt_addr;
input [10:0] lmq2_pcx_pkt_addr;
input [10:0] lmq3_pcx_pkt_addr;
output lmq_ld_addr_b3;
output [3:0] lsu_outstanding_rmo_st_max;
input lsu_ttype_vld_m2;
input tlu_early_flush_pipe2_w;
input [1:0] lsu_st_dcfill_size_e;
input mbist_dcache_write;
input mbist_dcache_read;
output lsu_dcfill_data_mx_sel_e;
wire [3:0] ld_thrd_byp_sel_e ;
wire ifu_asi_vld,ifu_asi_vld_d1 ;
wire [1:0] dcache_wr_size_e ;
wire lsu_ncache_ld_e;
wire lsu_diagnstc_wr_src_sel_e ; // dcache/dtag/v write - diag
wire dctl_flush_pipe_w ; // flush pipe due to error
wire dctl_early_flush_w;
wire [10:0] lmq_pcx_pkt_addr;
wire [2:0] lmq_ld_rq_type_e;
wire [10:0] dcache_fill_addr_e;
wire [2:0] dcache_wr_addr_e ;
wire lsuctl_dtlb_byp_e ;
wire cam_perr_unc0,asi_data_perr0,asi_tag_perr0,ifu_unc_err0 ;
wire cam_perr_unc1,asi_data_perr1,asi_tag_perr1,ifu_unc_err1 ;
wire cam_perr_unc2,asi_data_perr2,asi_tag_perr2,ifu_unc_err2 ;
wire cam_perr_unc3,asi_data_perr3,asi_tag_perr3,ifu_unc_err3 ;
wire cam_perr_unc_e, asi_data_perr_e,asi_tag_perr_e,ifu_unc_err_e ;
wire cam_perr_unc_m, asi_data_perr_m,asi_tag_perr_m,ifu_unc_err_m ;
wire cam_perr_unc_g, asi_data_perr_g,asi_tag_perr_g,ifu_unc_err_g ;
//wire cam_real_err_e, cam_real_err_m ;
wire [3:0] squash_byp_cmplt,squash_byp_cmplt_m, squash_byp_cmplt_g ;
wire ld_inst_vld_m,ld_inst_vld_g ;
wire st_inst_vld_m,st_inst_vld_g ;
wire fp_ldst_m,fp_ldst_g,fp_ldst_w2 ;
wire lsu_ld_hit_wb, lsu_ld_miss_wb ;
wire [3:0] lsu_way_hit ;
wire [1:0] ldst_sz_m,ldst_sz_g ;
wire [4:0] ld_rd_m, ld_rd_g ;
wire lsu_dtlb_bypass_g,dtlb_bypass_e,dtlb_bypass_m ;
wire [6:0] lsu_sraddr_e ;
//wire lsu_rsr_inst_e,lsu_rsr_inst_m, lsu_rsr_inst_w ;
wire lsu_wsr_inst_e;
wire pctxt_state_en, sctxt_state_en ;
wire asi_state_wr_en ;
//wire [3:0] pctxt_state_rd_en, sctxt_state_rd_en ;
wire lsu_alt_space_m,lsu_alt_space_g ;
wire ldxa_internal, stxa_internal ;
wire lsu_ctl_state_en;
//wire [3:0] lsu_ctl_state_rd_en;
wire [3:0] lsu_ctl_state_wr_en ;
//wire [7:0] imm_asi_e,imm_asi_m,imm_asi_g ;
//wire imm_asi_vld_e,imm_asi_vld_m,imm_asi_vld_g;
//wire [7:0] asi_state0,asi_state1,asi_state2,asi_state3 ;
wire ldsta_internal_e,sta_internal_e,lda_internal_e;
wire sta_internal_m,lda_internal_m;
wire [7:0] asi_d ;
wire [1:0] thrid_d,thrid_e,thrid_m, thrid_g, thrid_w2, thrid_w3, ldxa_thrid_w2 ;
wire stxa_internal_d1, stxa_internal_d2 ;
wire ld_pcx_pkt_vld_e ;
wire ld_pcx_pkt_vld_m ;
wire ld_pcx_pkt_vld_g ;
wire ldst_dbl_m, ldst_dbl_g;
wire ldd_force_l2access_w2, ldd_force_l2access_w3;
//wire ld_stb_full_raw_w2 ;
wire ld_stb_full_raw_w3 ;
wire ldbyp0_vld_rst, ldbyp0_vld_en, ldbyp0_fpld ;
wire ldbyp1_vld_rst, ldbyp1_vld_en, ldbyp1_fpld ;
wire ldbyp2_vld_rst, ldbyp2_vld_en, ldbyp2_fpld ;
wire ldbyp3_vld_rst, ldbyp3_vld_en, ldbyp3_fpld ;
//wire ldbyp0_vld_en_d1,ldbyp1_vld_en_d1,ldbyp2_vld_en_d1,ldbyp3_vld_en_d1 ;
wire thread0_e,thread1_e,thread2_e,thread3_e;
wire thread0_d,thread1_d,thread2_d,thread3_d;
wire thread0_m,thread1_m,thread2_m,thread3_m;
wire thread0_g,thread1_g,thread2_g,thread3_g;
wire thread0_w2,thread1_w2,thread2_w2,thread3_w2;
wire thread0_w3,thread1_w3,thread2_w3,thread3_w3;
wire tlu_stxa_thread0_w2,tlu_stxa_thread1_w2 ;
wire tlu_stxa_thread2_w2,tlu_stxa_thread3_w2 ;
wire tlu_ldxa_thread0_w2,tlu_ldxa_thread1_w2 ;
wire tlu_ldxa_thread2_w2,tlu_ldxa_thread3_w2 ;
wire spu_ldxa_thread0_w2,spu_ldxa_thread1_w2 ;
wire spu_ldxa_thread2_w2,spu_ldxa_thread3_w2 ;
wire spu_stxa_thread0,spu_stxa_thread1 ;
wire spu_stxa_thread2,spu_stxa_thread3 ;
wire ifu_ldxa_thread0_w2,ifu_ldxa_thread1_w2 ;
wire ifu_ldxa_thread2_w2,ifu_ldxa_thread3_w2 ;
wire ifu_stxa_thread0_w2,ifu_stxa_thread1_w2 ;
wire ifu_stxa_thread2_w2,ifu_stxa_thread3_w2 ;
wire ldbyp0_vld, ldbyp1_vld, ldbyp2_vld, ldbyp3_vld ;
//wire ld_any_byp_data_vld ;
wire [3:0] asi_state_wr_thrd;
wire [3:0] pctxt_state_wr_thrd ;
wire [3:0] sctxt_state_wr_thrd ;
wire tlb_cam_hit_g ;
wire ld_inst_vld_unflushed ;
wire st_inst_vld_unflushed ;
wire [7:0] baddr_m ;
wire [15:0] byte_wr_enable ;
//wire [1:0] st_size ;
//wire l2fill_bendian_g ;
wire ldst_byte,ldst_hword,ldst_word,ldst_dword;
wire byte_m,hword_m,word_m,dword_m;
wire tlb_invert_endian_g ;
//wire [7:0] l2fill_bytes_msb_m, l2fill_bytes_msb_g ;
//wire byte_g, hword_g, word_g ;
wire signed_ldst_m ;
//wire unsigned_ldst_m ;
//wire sign_bit_g ;
//wire [7:0] align_bytes_msb ;
wire l2fill_vld_m, l2fill_vld_g ;
wire l2fill_fpld_e, l2fill_fpld_m, l2fill_fpld_g ;
wire pstate_cle_e, pstate_cle_m, pstate_cle_g ;
wire l1hit_lendian_g ;
wire l1hit_sign_extend_m, l1hit_sign_extend_g ;
wire demap_thread0, demap_thread1, demap_thread2, demap_thread3 ;
wire misc_byte_m,misc_hword_m,misc_word_m,misc_dword_m;
wire byp_word_g;
//wire [15:0] byp_baddr_g ;
//wire ld_stb_hit_g ;
wire atomic_ld_squash_e ;
wire atomic_m,atomic_g,atomic_w2, atomic_w3 ;
wire [2:0] ld_rq_type ;
wire ncache_pcx_rq_g ;
wire lmq_pkt_vld_g ;
wire tlb_lng_ltncy_asi_d,tlb_lng_ltncy_asi_e, tlb_lng_ltncy_asi_m,tlb_lng_ltncy_asi_g ;
wire recognized_asi_d,recognized_asi_e,recognized_asi_m,recognized_asi_g,recognized_asi_tmp ;
wire asi_internal_d, asi_internal_e ;
wire asi_internal_m, asi_internal_g ;
wire dcache_byp_asi_d, dcache_byp_asi_e ;
wire dcache_byp_asi_m, dcache_byp_asi_g ;
wire phy_use_ec_asi_d,phy_use_ec_asi_e,phy_use_ec_asi_m;
wire phy_byp_ec_asi_d,phy_byp_ec_asi_e,phy_byp_ec_asi_m;
wire lendian_asi_d, lendian_asi_e;
wire lendian_asi_m, lendian_asi_g;
wire intrpt_disp_asi_d,intrpt_disp_asi_e,intrpt_disp_asi_m,intrpt_disp_asi_g ;
wire nofault_asi_d, nofault_asi_e, nofault_asi_m ;
wire nucleus_asi_d, nucleus_asi_e ;
wire primary_asi_d, primary_asi_e ;
wire quad_asi_d,quad_asi_e,quad_asi_m,quad_asi_g;
wire binit_quad_asi_d,binit_quad_asi_e,binit_quad_asi_m,binit_quad_asi_g ;
wire secondary_asi_d, secondary_asi_e ;
wire tlb_byp_asi_d, tlb_byp_asi_e;
wire thread0_ctxt, thread1_ctxt ;
wire thread2_ctxt, thread3_ctxt ;
wire altspace_ldst_e, non_altspace_ldst_e ;
wire altspace_ldst_m, altspace_ldst_g ;
wire non_altspace_ldst_m, non_altspace_ldst_g ;
wire thread_pctxt, thread_sctxt, thread_nctxt, thread_actxt ;
wire ncache_asild_rq_g ;
//SC wire pstate_priv, pstate_priv_m ;
//SC wire priv_pg_usr_mode ;
//SC wire nonwr_pg_st_access ;
//SC wire nfo_pg_nonnfo_asi ;
//wire daccess_excptn ;
wire mbar_inst_m,flsh_inst_m ;
wire mbar_inst_g,flsh_inst_g ;
wire bsync0_reset,bsync1_reset;
wire bsync2_reset,bsync3_reset ;
wire bsync0_en,bsync1_en ;
wire bsync2_en,bsync3_en ;
wire flush_inst0_g,mbar_inst0_g ;
wire flush_inst1_g,mbar_inst1_g ;
wire flush_inst2_g,mbar_inst2_g ;
wire flush_inst3_g,mbar_inst3_g ;
wire dfill_thread0,dfill_thread1;
wire dfill_thread2,dfill_thread3;
wire mbar_vld0, flsh_vld0 ;
wire mbar_vld1, flsh_vld1 ;
wire mbar_vld2, flsh_vld2 ;
wire mbar_vld3, flsh_vld3 ;
wire [1:0] dfq_tid_m,dfq_tid_g;
wire [1:0] ldbyp_tid_m ;
wire stxa_stall_asi_g ;
wire stxa_stall_wr_cmplt0, stxa_stall_wr_cmplt1 ;
wire stxa_stall_wr_cmplt2, stxa_stall_wr_cmplt3 ;
wire stxa_stall_wr_cmplt0_d1, stxa_stall_wr_cmplt1_d1 ;
wire stxa_stall_wr_cmplt2_d1, stxa_stall_wr_cmplt3_d1 ;
wire dtlb_done ;
wire tag_rd_vld_m, tag_rd_vld_g ;
wire data_rd_vld_m, data_rd_vld_g ;
wire tlb_demap_vld ;
wire dtlb_done_d1 ;
wire dtlb_done_d2 ;
wire tlu_lsu_asi_update_g ;
wire [1:0] tlu_lsu_tid_g ;
wire tsa_update_asi0,tsa_update_asi1;
wire tsa_update_asi2,tsa_update_asi3;
wire tlb_ld_inst0,tlb_ld_inst1,tlb_ld_inst2,tlb_ld_inst3 ;
wire tlb_st_inst0,tlb_st_inst1,tlb_st_inst2,tlb_st_inst3 ;
wire tlb_access_en0_e,tlb_access_en1_e,tlb_access_en2_e,tlb_access_en3_e ;
wire tlb_access_en0_m,tlb_access_en1_m,tlb_access_en2_m,tlb_access_en3_m ;
wire tlb_access_en0_tmp,tlb_access_en1_tmp,tlb_access_en2_tmp,tlb_access_en3_tmp ;
wire tlb_access_en0_g,tlb_access_en1_g,tlb_access_en2_g,tlb_access_en3_g ;
wire tlb_access_en0_unflushed,tlb_access_en1_unflushed,tlb_access_en2_unflushed,tlb_access_en3_unflushed ;
wire tlb_access_rst0,tlb_access_rst1,tlb_access_rst2,tlb_access_rst3 ;
wire tlb_access_sel_thrd0,tlb_access_sel_thrd1;
wire tlb_access_sel_thrd2,tlb_access_sel_thrd3;
wire tlb_access_blocked ;
wire tlb_access_pending ;
wire tlb_access_initiated ;
//wire tlb_pending_access_rst ;
wire vw_wtchpt_cmp_en_m,vr_wtchpt_cmp_en_m ;
//wire va_b12_3_match_m,va_b47_40_match_m ;
//wire va_b12_3_match_g,va_b47_40_match_g ;
//wire wtchpt_msk_match_m,wtchpt_msk_match_g ;
wire as_if_user_asi_d,as_if_user_asi_e,as_if_user_asi_m;
//SC wire as_if_usr_priv_pg ;
//SC wire priv_action,priv_action_m ;
//SC wire stdf_maddr_not_align, lddf_maddr_not_align ;
//wire [8:0] early_ttype_m,early_ttype_g ;
//wire early_trap_vld_m, early_trap_vld_g ;
//SC wire atm_access_w_nc, atm_access_unsup_asi ;
wire atomic_asi_d,atomic_asi_e,atomic_asi_m ;
//wire dflush_asi_d,dflush_asi_e,dflush_asi_m,dflush_asi_g;
wire blk_asi_d,blk_asi_e,blk_asi_m, blk_asi_g ;
wire fpld_byp_data_vld ;
//wire [7:0] dcache_rd_parity ;
wire dcache_rd_parity_error ;
//SC wire tte_data_parity_error ;
wire [3:0] dtag_parity_error;
//wire dtag_mtag_parity_error ;
//wire daccess_error ;
//SC wire dmmu_miss_g ;
wire [2:0] ctxt_sel_e ;
wire dc_diagnstc_asi_d, dc_diagnstc_asi_e ;
wire dc_diagnstc_asi_m, dc_diagnstc_asi_g ;
wire dtagv_diagnstc_asi_d, dtagv_diagnstc_asi_e ;
wire dtagv_diagnstc_asi_m, dtagv_diagnstc_asi_g ;
//wire dc_diagnstc_wr_e,dtagv_diagnstc_wr_e ;
//wire dside_diagnstc_wr_e ;
wire dc_diagnstc_wr_en,dtagv_diagnstc_wr_en ;
wire dtagv_diagnstc_rd_g ;
wire dc0_diagnstc_asi,dtagv0_diagnstc_asi;
wire dc1_diagnstc_asi,dtagv1_diagnstc_asi;
wire dc2_diagnstc_asi,dtagv2_diagnstc_asi;
wire dc3_diagnstc_asi,dtagv3_diagnstc_asi;
//wire [3:0] lngltncy_st_go ;
wire [3:0] tlb_st_data_sel_m ;
wire dc0_diagnstc_wr_en, dc1_diagnstc_wr_en, dc2_diagnstc_wr_en, dc3_diagnstc_wr_en ;
wire dtagv0_diagnstc_wr_en, dtagv1_diagnstc_wr_en, dtagv2_diagnstc_wr_en, dtagv3_diagnstc_wr_en ;
//wire merge2_sel_byte7, merge3_sel_byte7 ;
//SC wire hw_align_addr,wd_align_addr,dw_align_addr;
wire hw_size,wd_size,dw_size;
//SC wire mem_addr_not_align ;
wire wr_only_asi_d,wr_only_asi_e,wr_only_asi_m ;
wire rd_only_asi_d,rd_only_asi_e,rd_only_asi_m ;
wire mmu_rd_only_asi_d,mmu_rd_only_asi_e,mmu_rd_only_asi_m ;
wire unimp_asi_d,unimp_asi_e,unimp_asi_m;
wire dmmu_asi58_d,dmmu_asi58_e,dmmu_asi58_m;
wire immu_asi50_d,immu_asi50_e,immu_asi50_m;
wire ifu_asi_store ;
wire nontlb_asi0, nontlb_asi1, nontlb_asi2, nontlb_asi3 ;
//wire stxa_stall_reset ;
wire ifu_nontlb0_asi,ifu_nontlb1_asi,ifu_nontlb2_asi,ifu_nontlb3_asi;
wire ifu_nontlb_asi_d, ifu_nontlb_asi_e,ifu_nontlb_asi_m,ifu_nontlb_asi_g ;
wire [2:0] lsu_asi_sel_fmx1 ;
wire [2:0] lsu_asi_sel_fmx2;
wire lsu_asi_rd_en, lsu_asi_rd_en_w2 ;
//wire [12:0] pctxt_state ;
//wire [12:0] sctxt_state ;
//wire [1:0] dcache_rand,dcache_rand_new ;
wire dtlb_inv_all_e,dtlb_inv_all_m ;
wire dtlb_wr_vld_d1,dtlb_tag_rd_d1,dtlb_data_rd_d1,dtlb_dmp_vld_d1,dtlb_inv_all_d1 ;
wire ldst_in_pipe ;
wire tlbop_init, tlbop_init_d1, tlbop_init_d2 ;
wire tlbop_init_d3, tlbop_init_d4, tlbop_init_d5 ;
wire [3:0] ldxa_illgl_va_cmplt,ldxa_illgl_va_cmplt_d1 ;
wire lsuctl_va_vld ;
wire lsuctl_illgl_va ;
wire sctxt_va_vld;
//wire scxt_ldxa_illgl_va ;
wire pctxt_va_vld;
wire pscxt_ldxa_illgl_va ;
wire lsu_asi_illgl_va ;
wire [3:0] lsu_asi_illgl_va_cmplt,lsu_asi_illgl_va_cmplt_w2 ;
wire bistctl_va_vld,mrgnctl_va_vld,ldiagctl_va_vld ;
wire bistctl_state_en,mrgnctl_state_en,ldiagctl_state_en ;
wire mrgnctl_illgl_va ;
wire asi42_illgl_va ;
wire [3:0] tap_thread ;
wire mrgn_tap_wr_en ;
wire bist_tap_wr_en ;
wire [3:0] dfture_tap_rd_d1;
wire [3:0] dfture_tap_wr_en;
//wire dfture_tap_rd_sel ;
wire misc_asi_rd_en ;
wire [3:0] lsuctl_ctlbits_wr_en ;
wire bistctl_wr_en;
wire mrgnctl_wr_en;
//wire ldiagctl_rd_en,ldiagctl_wr_en;
wire casa_m, casa_g ;
wire tte_data_perror_unc ;
wire asi_tte_data_perror,asi_tte_tag_perror ;
wire [1:0] dfill_tid_m,dfill_tid_g ;
wire dtag_error_m,dcache_error_m;
wire dtag_error_g,dcache_error_g;
wire dtag_error_w2,dcache_error_w2;
wire l2_unc_error_e,l2_corr_error_e;
wire l2_unc_error_m,l2_corr_error_m;
wire l2_unc_error_g,l2_corr_error_g;
wire l2_unc_error_w2,l2_corr_error_w2;
wire unc_err_trap_e,unc_err_trap_m,unc_err_trap_g ;
//wire corr_err_trap_e, corr_err_trap_m, corr_err_trap_g ;
wire dtag_perror_g ;
wire ifill_tlb_asi_d,dfill_tlb_asi_d,rd_only_ltlb_asi_d,wr_only_ltlb_asi_d ;
wire ifill_tlb_asi_e,dfill_tlb_asi_e,rd_only_ltlb_asi_e,wr_only_ltlb_asi_e ;
//SC wire tlb_daccess_excptn_e,tlb_daccess_error_e ;
//SC wire tlb_daccess_excptn_m,tlb_daccess_error_m ;
//SC wire tlb_daccess_excptn_g,tlb_daccess_error_g ;
wire thread_tl_zero ;
wire pid_va_vld, pid_state_en ;
wire [3:0] pid_state_wr_en ;
//wire [3:0] pid_state_rd_en ;
//wire [2:0] pid_state ;
wire [3:0] intld_byp_cmplt ;
//wire hpv_priv,hpstate_en ;
wire hpv_priv_m,hpstate_en_m ;
wire hpv_priv_e,hpstate_en_e ;
wire blkst_m, blkst_g ;
//wire dc_direct_map ;
wire spubyp_trap_active_e,spubyp_trap_active_m, spubyp_trap_active_g ;
wire [6:0] spubyp_ttype ;
wire spu_trap ;
wire spu_trap0, spu_trap1, spu_trap2, spu_trap3 ;
wire [6:0] spu_ttype ;
wire spubyp0_trap,spubyp1_trap,spubyp2_trap,spubyp3_trap;
wire [6:0] spubyp0_ttype,spubyp1_ttype,spubyp2_ttype,spubyp3_ttype;
wire bendian_g ;
//wire va_wtchpt_rd_en, pa_wtchpt_rd_en;
//wire lsu_bendian_access_g;
wire lsu_tlb_tag_rd_vld_g ;
wire lsu_dtlb_invalid_all_m ;
wire [3:0] dva_vld_g;
wire lsu_diagnstc_asi_rd_en;
wire [3:0] ld_thrd_byp_sel_g ;
wire [3:0] lmq_byp_data_sel0 ; // ldxa vs stb bypass data sel.
wire [3:0] lmq_byp_data_sel1 ; // ldxa vs stb bypass data sel.
wire [3:0] lmq_byp_data_sel2 ; // ldxa vs stb bypass data sel.
wire [3:0] lmq_byp_data_sel3 ; // ldxa vs stb bypass data sel.
wire [2:0] lmq_byp_ldxa_sel0 ; // ldxa data sel - thread0
wire [2:0] lmq_byp_ldxa_sel1 ; // ldxa data sel - thread1
wire [2:0] lmq_byp_ldxa_sel2 ; // ldxa data sel - thread2
wire [2:0] lmq_byp_ldxa_sel3 ; // ldxa data sel - thread3
wire endian_mispred_g ;
wire ld_inst_vld_w2, ld_inst_vld_w3;
wire [3:0] lmq_byp_data_raw_sel_d1;
wire [3:0] lmq_byp_data_raw_sel_d2;
wire asi_st_vld_g ;
wire ignore_fill;
wire [3:0] pend_atm_ld_ue ;
wire [2:0] lsu_byp_misc_addr_m ; // lower 3bits of addr for ldxa/raw etc
wire [1:0] lsu_byp_misc_sz_m ; // size for ldxa/raw etc
//==========================================================
//RESET, CLK
//==========================================================
wire reset;
// assign reset = ~rst_l;
wire dbb_reset_l;
wire clk;
dffrl_async rstff(.din (grst_l),
.q (dbb_reset_l),
.clk (clk), .se(se), .si(), .so(),
.rst_l (arst_l));
assign reset = ~dbb_reset_l;
assign dctl_rst_l = dbb_reset_l;
assign clk = rclk;
wire lsu_bist_wvld_e ; // bist writes to cache
wire lsu_bist_rvld_e ; // bist reads dcache
dff_s #(2) mbist_stge (
.din ({mbist_dcache_write, mbist_dcache_read}),
.q ({lsu_bist_wvld_e, lsu_bist_rvld_e }),
.clk (clk),
.se (se), .si (), .so ()
);
//===========================================================
//from lsu_excpctl
//wire lsu_flush_pipe_w ; // flush - local to lsu
// assign lsu_flush_pipe_w = dctl_flush_pipe_w;
//===========================================================
//
assign lsu_ldst_inst_vld_e = ld_inst_vld_e | st_inst_vld_e;
//wire lsu_l2fill_bendian_g;
wire memref_e;
dff_s #(1) stge_ad_e (
.din (ifu_lsu_memref_d),
.q (memref_e),
.clk (clk),
.se (se), .si (), .so ()
);
//=================================================================================================
// SHADOW SCAN
//=================================================================================================
wire sscan_data_13, sscan_data_14 ;
// stb status - this monitors the stb state
assign sscan_data_13 =
ctu_sscan_tid[0] & lsu_stb_empty[0] |
ctu_sscan_tid[1] & lsu_stb_empty[1] |
ctu_sscan_tid[2] & lsu_stb_empty[2] |
ctu_sscan_tid[3] & lsu_stb_empty[3] ;
// Monitors outstanding long-latency asi transactions - hangs thread. Doesn't cover all asi.
assign sscan_data_14 =
ctu_sscan_tid[0] & (tlb_ld_inst0 | tlb_st_inst0) |
ctu_sscan_tid[1] & (tlb_ld_inst1 | tlb_st_inst1) |
ctu_sscan_tid[2] & (tlb_ld_inst2 | tlb_st_inst2) |
ctu_sscan_tid[3] & (tlb_ld_inst3 | tlb_st_inst3) ;
dff_s #(2) stg_d1 (
.din ({sscan_data_14,sscan_data_13}),
.q (lsu_sscan_data[14:13]),
.clk (clk),
.se (se), .si (), .so ()
);
//=========================================================================================
// INST_VLD_W GENERATION
//=========================================================================================
wire flush_w_inst_vld_m ;
wire lsu_inst_vld_w ;
assign flush_w_inst_vld_m =
ifu_tlu_inst_vld_m &
~(dctl_flush_pipe_w & (thrid_m[1:0] == thrid_g[1:0])) ; // really lsu_flush_pipe_w
dff_s stgw_ivld (
.din (flush_w_inst_vld_m),
.q (lsu_inst_vld_w),
.clk (clk),
.se (se), .si (), .so ()
);
// Specifically for qctl2. Does not include flush-pipe, but does include ifu's flush.
wire ld_vld ;
wire ifu_lsu_flush_w;
wire ifu_tlu_flush_fd_w_q, ifu_tlu_flush_fd2_w_q, ifu_tlu_flush_fd3_w_q;
dff_s #(4) ifu_tlu_flush_stgw (
.din ({ifu_tlu_flush_m,ifu_tlu_flush_m, ifu_tlu_flush_m, ifu_tlu_flush_m} ),
.q ({ifu_lsu_flush_w,ifu_tlu_flush_fd_w_q,ifu_tlu_flush_fd2_w_q,ifu_tlu_flush_fd3_w_q}),
.clk (clk),
.se (se), .si (), .so ()
);
bw_u1_buf_30x UZfix_ifu_tlu_flush_fd_w ( .a(ifu_tlu_flush_fd_w_q), .z(ifu_tlu_flush_fd_w) );
bw_u1_buf_30x UZfix_ifu_tlu_flush_fd2_w ( .a(ifu_tlu_flush_fd2_w_q), .z(ifu_tlu_flush_fd2_w) );
bw_u1_buf_30x UZfix_ifu_tlu_flush_fd3_w ( .a(ifu_tlu_flush_fd3_w_q), .z(ifu_tlu_flush_fd3_w) );
assign ld_vld = ld_inst_vld_unflushed & lsu_inst_vld_w & ~ifu_lsu_flush_w ;
wire ld_vld_w_flush ;
assign ld_vld_w_flush = ld_vld & ~dctl_flush_pipe_w ;
assign lsu_ld_inst_vld_g[0] = ld_vld_w_flush & thread0_g ;
assign lsu_ld_inst_vld_g[1] = ld_vld_w_flush & thread1_g ;
assign lsu_ld_inst_vld_g[2] = ld_vld_w_flush & thread2_g ;
assign lsu_ld_inst_vld_g[3] = ld_vld_w_flush & thread3_g ;
//=========================================================================================
// TLB Control
//=========================================================================================
wire alt_space_e ;
dff_s #(1) aspace_e (
.din (ifu_lsu_alt_space_d),
.q (alt_space_e),
.clk (clk),
.se (se), .si (), .so ()
);
//Atomics require translation.
assign tlb_ldst_cam_vld =
memref_e &
~dtlb_bypass_e & ~(asi_internal_e & alt_space_e) ;
// in hyper-lite mode, assumption is that real translation is not supported -
// a miss in tlb with real-translation enabled would result in real-address
// translation miss. This would be purely accidental on software's part.
//wire dtlb_real_byp_e ;
//assign dtlb_real_byp_e = hpstate_en_e & ~hpv_priv_e ;
// In hyper-lite mode, no concept of real xslation.
assign lsu_dtlb_cam_real_e =
// lsu-ctl based RA->PA
( lsuctl_dtlb_byp_e & ~hpv_priv_e & hpstate_en_e) |
// means RA->PA if used by hypervisor.
( tlb_byp_asi_e & hpstate_en_e & altspace_ldst_e) ;
//( tlb_byp_asi_e & dtlb_real_byp_e & altspace_ldst_e) ;
assign demap_thread0 = ~tlb_demap_thrid[1] & ~tlb_demap_thrid[0] ;
assign demap_thread1 = ~tlb_demap_thrid[1] & tlb_demap_thrid[0] ;
assign demap_thread2 = tlb_demap_thrid[1] & ~tlb_demap_thrid[0] ;
assign demap_thread3 = tlb_demap_thrid[1] & tlb_demap_thrid[0] ;
// demap access and regular ldst access to tlb are assumed to
// be mutex.
assign thread0_ctxt = ( demap_thread0 & tlb_demap_vld) |
(~tlb_demap_vld & thread0_e) ;
//(thread0_e & memref_e) ;
assign thread1_ctxt = ( demap_thread1 & tlb_demap_vld) |
(~tlb_demap_vld & thread1_e) ;
//(thread1_e & memref_e) ;
assign thread2_ctxt = ( demap_thread2 & tlb_demap_vld) |
(~tlb_demap_vld & thread2_e) ;
//(thread2_e & memref_e) ;
assign thread3_ctxt = ( demap_thread3 & tlb_demap_vld) |
(~tlb_demap_vld & thread3_e) ;
//(thread3_e & memref_e) ;
assign altspace_ldst_e = memref_e & alt_space_e ;
assign non_altspace_ldst_e = memref_e & ~alt_space_e ;
dff_s #(2) aspace_stgm (
.din ({altspace_ldst_e,non_altspace_ldst_e}),
.q ({altspace_ldst_m,non_altspace_ldst_m}),
.clk (clk),
.se (se), .si (), .so ()
);
dff_s #(2) aspace_stgg (
.din ({altspace_ldst_m,non_altspace_ldst_m}),
.q ({altspace_ldst_g,non_altspace_ldst_g}),
.clk (clk),
.se (se), .si (), .so ()
);
wire [3:0] tl_zero_d1 ;
dff_s #(4) tlz_stgd1 (
.din (tlu_lsu_tl_zero[3:0]),
.q (tl_zero_d1[3:0]),
.clk (clk),
.se (se), .si (), .so ()
);
mux4ds #(1) trap_level_zero_mux (
.in0 (tl_zero_d1[0]),
.in1 (tl_zero_d1[1]),
.in2 (tl_zero_d1[2]),
.in3 (tl_zero_d1[3]),
.sel0 (thread0_e),
.sel1 (thread1_e),
.sel2 (thread2_e),
.sel3 (thread3_e),
.dout (thread_tl_zero)
);
wire thread_tl_zero_m ;
dff_s #(1) ttlz_stgm (
.din (thread_tl_zero),
.q (thread_tl_zero_m),
.clk (clk),
.se (se), .si (), .so ()
);
assign lsu_nonalt_nucl_access_m = non_altspace_ldst_m & ~thread_tl_zero_m ;
// Note : autodemap will need to be or'ed into tlb_demap_vld !!!
// use of tlu_lsu_tl_zero needs to be threaded.
assign thread_pctxt = ( tlb_demap_pctxt & tlb_demap_vld) | // demap
( non_altspace_ldst_e & thread_tl_zero) | // ldst. non-alt- space
( altspace_ldst_e & primary_asi_e) | // ldst. alt_space
(~(memref_e | tlb_demap_vld)) ; // default for pipe
//(~(ld_inst_vld_e | st_inst_vld_e | tlb_demap_vld)) ; // default for pipe
assign thread_sctxt = ( tlb_demap_sctxt & tlb_demap_vld) | // demap
( altspace_ldst_e & secondary_asi_e) ; // ldst. alt_space
assign thread_nctxt = ( tlb_demap_nctxt & tlb_demap_vld) | // demap
( non_altspace_ldst_e & ~thread_tl_zero) | // ldst. non-alt- space
( altspace_ldst_e & nucleus_asi_e) ; // ldst. alt_space
assign thread_actxt = tlb_demap_actxt & tlb_demap_vld ;
//tmp
wire thread_default;
assign thread_default = ~(thread_pctxt | thread_sctxt | thread_actxt);
wire [3:0] pstate_am ;
dff_s #(4) psam_stgd1 (
.din (tlu_lsu_pstate_am[3:0]),
.q (pstate_am[3:0]),
.clk (clk),
.se (se), .si (), .so ()
);
//assign lsu_dtlb_addr_mask_l_e =
// thread0_e ? ~pstate_am[0] :
// thread1_e ? ~pstate_am[1] :
// thread2_e ? ~pstate_am[2] :
// ~pstate_am[3] ;
mux4ds #(1) pstate_am_mux (
.in0 (~pstate_am[0]),
.in1 (~pstate_am[1]),
.in2 (~pstate_am[2]),
.in3 (~pstate_am[3]),
.sel0 (thread0_e),
.sel1 (thread1_e),
.sel2 (thread2_e),
.sel3 (thread3_e),
.dout (lsu_dtlb_addr_mask_l_e)
);
//=========================================================================================
// TLB RD/WR/DMP HANDLING
//=========================================================================================
// To speed up the tlb miss handler, wr_vld will now be generated based on
// admp occurence. lsu_dtlb_wr_vld_g is to be ignored. The following paths
// can be improved
// admp->write initiation (+2)
// write->completion initiation (+3)
wire admp_write ;
assign admp_write = lsu_dtlb_dmp_vld_e & tlb_demap_actxt ;
wire admp_rst ;
assign admp_rst = reset | lsu_dtlb_wr_vld_e ;
wire local_dtlb_wr_vld_g ;
dffre_s #(1) twr_stgd1 (
.din (admp_write),
.q (local_dtlb_wr_vld_g),
.clk (clk),
.en (admp_write), .rst (admp_rst),
.se (se), .si (), .so ()
);
wire dtlb_wr_init_d1,dtlb_wr_init_d2,dtlb_wr_init_d3 ;
// Handshake between tlu and lsu needs to be fine-tuned !!!
assign lsu_dtlb_wr_vld_e = local_dtlb_wr_vld_g & ~(memref_e | dtlb_wr_init_d1 | dtlb_wr_init_d2) ;
//assign lsu_dtlb_wr_vld_e = tlu_dtlb_wr_vld_g & ~(memref_e | dtlb_done_d1 | dtlb_done_d2) ;
assign lsu_dtlb_tag_rd_e = tlu_dtlb_tag_rd_g & ~(memref_e | dtlb_done_d1 | dtlb_done_d2) ;
assign lsu_dtlb_data_rd_e = tlu_dtlb_data_rd_g & ~(memref_e | dtlb_done_d1 | dtlb_done_d2) ;
assign lsu_dtlb_dmp_vld_e = tlu_dtlb_dmp_vld_g & ~(memref_e | dtlb_done_d1 | dtlb_done_d2) ;
wire lsu_dtlb_dmp_all_e_tmp;
assign lsu_dtlb_dmp_all_e_tmp = tlu_dtlb_dmp_all_g & ~(memref_e | dtlb_done_d1 | dtlb_done_d2) ;
bw_u1_buf_5x UZsize_lsu_dtlb_dmp_all_e (.a(lsu_dtlb_dmp_all_e_tmp), .z(lsu_dtlb_dmp_all_e));
assign lsu_dtlb_rwindex_vld_e = tlu_dtlb_rw_index_vld_g & ~(memref_e | dtlb_wr_init_d1 | dtlb_wr_init_d2) ;
//assign lsu_dtlb_rwindex_vld_e = tlu_dtlb_rw_index_vld_g & ~(memref_e | dtlb_done_d1 | dtlb_done_d2) ;
// Can remove reset once invalidate asi in place !!!
// assign lsu_dtlb_invalid_all_w2 = reset | tlu_dtlb_invalidate_all_g ;
assign tlb_demap_vld = lsu_dtlb_dmp_vld_e ;
// Switchout for threads. Force threads to swo if tlb operation does not occur for over 5 cycles.
dff_s #(5) tlbop_stgd1 (
//.din ({tlu_dtlb_wr_vld_g,tlu_dtlb_tag_rd_g,tlu_dtlb_data_rd_g,tlu_dtlb_dmp_vld_g,
.din ({local_dtlb_wr_vld_g,tlu_dtlb_tag_rd_g,tlu_dtlb_data_rd_g,tlu_dtlb_dmp_vld_g,
tlu_dtlb_invalidate_all_g}),
.q ({dtlb_wr_vld_d1,dtlb_tag_rd_d1,dtlb_data_rd_d1,dtlb_dmp_vld_d1,
dtlb_inv_all_d1}),
.clk (clk),
.se (se), .si (), .so ()
);
// Detect event.
//bug6193 / ECO bug6511
assign ldst_in_pipe = memref_e ;
assign tlbop_init =
((~dtlb_wr_vld_d1 & local_dtlb_wr_vld_g) |
(~dtlb_tag_rd_d1 & tlu_dtlb_tag_rd_g) |
(~dtlb_data_rd_d1 & tlu_dtlb_data_rd_g) |
(~dtlb_inv_all_d1 & tlu_dtlb_invalidate_all_g) |
(~dtlb_dmp_vld_d1 & tlu_dtlb_dmp_vld_g)) & ldst_in_pipe ;
dff_s #(1) tlbinit_stgd1 ( .din (tlbop_init), .q (tlbop_init_d1),
.clk (clk), .se (se), .si (), .so ());
dff_s #(1) tlbinit_stgd2 ( .din (tlbop_init_d1 & ldst_in_pipe), .q (tlbop_init_d2),
.clk (clk), .se (se), .si (), .so ());
dff_s #(1) tlbinit_stgd3 ( .din (tlbop_init_d2 & ldst_in_pipe), .q (tlbop_init_d3),
.clk (clk), .se (se), .si (), .so ());
dff_s #(1) tlbinit_stgd4 ( .din (tlbop_init_d3 & ldst_in_pipe), .q (tlbop_init_d4),
.clk (clk), .se (se), .si (), .so ());
dff_s #(1) tlbinit_stgd5 ( .din (tlbop_init_d4 & ldst_in_pipe), .q (tlbop_init_d5),
.clk (clk), .se (se), .si (), .so ());
assign lsu_tlbop_force_swo = tlbop_init_d5 & ldst_in_pipe ;
//assign dtlb_done = lsu_dtlb_wr_vld_e | lsu_dtlb_tag_rd_e |
assign dtlb_done = lsu_dtlb_tag_rd_e | lsu_dtlb_data_rd_e |
lsu_dtlb_dmp_vld_e | dtlb_inv_all_e ;
assign dtlb_inv_all_e = tlu_dtlb_invalidate_all_g & ~(memref_e | dtlb_done_d1 | dtlb_done_d2) ;
dff_s #(3) dn_stgd1 (
.din ({dtlb_done,lsu_dtlb_tag_rd_e,lsu_dtlb_data_rd_e}),
.q ({dtlb_done_d1,tag_rd_vld_m,data_rd_vld_m}),
.clk (clk),
.se (se), .si (), .so ()
);
wire dtlb_inv_all_din ;
assign dtlb_inv_all_din = sehold ? dtlb_inv_all_m : dtlb_inv_all_e ;
dff_s #(1) dinv_stgd1 (
.din (dtlb_inv_all_din),
.q (dtlb_inv_all_m),
.clk (clk),
.se (se), .si (), .so ()
);
assign lsu_dtlb_invalid_all_m = dtlb_inv_all_m ;
// added by sureshT
assign lsu_dtlb_invalid_all_l_m = ~lsu_dtlb_invalid_all_m;
dff_s #(3) dn_stgd2 (
.din ({dtlb_done_d1,tag_rd_vld_m,data_rd_vld_m}),
.q ({dtlb_done_d2,tag_rd_vld_g,data_rd_vld_g}),
.clk (clk),
.se (se), .si (), .so ()
);
assign lsu_tlb_data_rd_vld_g = data_rd_vld_g ;
assign lsu_tlb_tag_rd_vld_g = tag_rd_vld_g ;
//assign lsu_tlb_st_vld_g = ~lsu_tlb_tag_rd_vld_g & ~lsu_tlb_data_rd_vld_g ;
// The handshake will have to change !!!
assign lsu_tlu_dtlb_done =
dtlb_done_d2 | // rest
dtlb_wr_init_d3 ; // write
// Note : if mx_sel bit is high, then it selects va instead of pa.
//=========================================================================================
// State/ASI Registers.
//=========================================================================================
dff_s #(8) stctl_stg_e (
.din ({ifu_tlu_sraddr_d[6:0],ifu_tlu_wsr_inst_d}),
.q ({lsu_sraddr_e[6:0], lsu_wsr_inst_e}),
.clk (clk),
.se (se), .si (), .so ()
);
assign lsu_tlu_wsr_inst_e = lsu_wsr_inst_e;
wire asi_state_wr_en_e, asi_state_wr_en_m;
assign asi_state_wr_en_e =
~lsu_sraddr_e[6] & // 1=hypervisor
~lsu_sraddr_e[5] & // =0 for state reg.
~lsu_sraddr_e[4] & ~lsu_sraddr_e[3] &
~lsu_sraddr_e[2] & lsu_sraddr_e[1] &
lsu_sraddr_e[0] &
lsu_wsr_inst_e ; // write
dff_s #(2) stctl_stg_m (
.din ({asi_state_wr_en_e, alt_space_e}),
.q ({asi_state_wr_en_m, lsu_alt_space_m}),
.clk (clk),
.se (se), .si (), .so ()
);
dff_s #(2) stctl_stg_w (
.din ({asi_state_wr_en_m, lsu_alt_space_m}),
.q ({asi_state_wr_en, lsu_alt_space_g}),
.clk (clk),
.se (se), .si (), .so ()
);
//assign asi_state_wr_en =
// ~lsu_sraddr_w[6] & // 1=hypervisor
// ~lsu_sraddr_w[5] & // =0 for state reg.
// ~lsu_sraddr_w[4] & ~lsu_sraddr_w[3] &
// ~lsu_sraddr_w[2] & lsu_sraddr_w[1] &
// lsu_sraddr_w[0] &
// lsu_wsr_inst_w ; // write
dff_s #(3) asi_stgw (
.din ({tlu_lsu_asi_update_m,tlu_lsu_tid_m[1:0]}),
.q ({tlu_lsu_asi_update_g,tlu_lsu_tid_g[1:0]}),
.clk (clk),
.se (se), .si (), .so ()
);
assign tsa_update_asi0 = ~tlu_lsu_tid_g[1] & ~tlu_lsu_tid_g[0] & tlu_lsu_asi_update_g ;
assign tsa_update_asi1 = ~tlu_lsu_tid_g[1] & tlu_lsu_tid_g[0] & tlu_lsu_asi_update_g ;
assign tsa_update_asi2 = tlu_lsu_tid_g[1] & ~tlu_lsu_tid_g[0] & tlu_lsu_asi_update_g ;
assign tsa_update_asi3 = tlu_lsu_tid_g[1] & tlu_lsu_tid_g[0] & tlu_lsu_asi_update_g ;
assign asi_state_wr_thrd[0] =
((asi_state_wr_en & thread0_g) | tsa_update_asi0) & lsu_inst_vld_w & ~dctl_early_flush_w ;
//((asi_state_wr_en & thread0_g) | tsa_update_asi0) & lsu_inst_vld_w & ~lsu_flush_pipe_w ;
assign asi_state_wr_thrd[1] =
((asi_state_wr_en & thread1_g) | tsa_update_asi1) & lsu_inst_vld_w & ~dctl_early_flush_w ;
assign asi_state_wr_thrd[2] =
((asi_state_wr_en & thread2_g) | tsa_update_asi2) & lsu_inst_vld_w & ~dctl_early_flush_w ;
assign asi_state_wr_thrd[3] =
((asi_state_wr_en & thread3_g) | tsa_update_asi3) & lsu_inst_vld_w & ~dctl_early_flush_w ;
// dc diagnstc will swo on write.
assign sta_internal_e = asi_internal_e & st_inst_vld_e & alt_space_e ;
// dc diagnstc will not swo on read.
assign lda_internal_e = asi_internal_e & ~dc_diagnstc_asi_e & ld_inst_vld_e & alt_space_e ;
assign ldsta_internal_e = sta_internal_e | lda_internal_e ;
// MMU_ASI
// Do no switch out for lds. lds switched out thru ldst_miss.
// qualification must be removed.
assign lsu_ifu_ldsta_internal_e = asi_internal_e ;
//assign lsu_ifu_ldsta_internal_e = asi_internal_e & ~ld_inst_vld_e ;
dff_s #(2) stai_stgm (
.din ({sta_internal_e,lda_internal_e}),
.q ({sta_internal_m,lda_internal_m}),
.clk (clk),
.se (se), .si (), .so ()
);
wire stxa_internal_m;
assign stxa_internal_m = sta_internal_m & ~(dtagv_diagnstc_asi_m | dc_diagnstc_asi_m);
dff_s #(2) stai_stgg (
.din ({stxa_internal_m, lda_internal_m}),
.q ({stxa_internal, ldxa_internal}),
.clk (clk),
.se (se), .si (), .so ()
);
wire [7:0] ldst_va_g;
assign ldst_va_g[7:0] = lsu_ldst_va_g[7:0];
wire [7:0] lsu_asi_state ;
dff_s #(8) asistate_stgg (
.din (lsu_dctl_asi_state_m[7:0]),
.q (lsu_asi_state[7:0]),
.clk (clk),
.se (se), .si (), .so ()
);
assign pctxt_va_vld = (ldst_va_g[7:0] == 8'h08) ;
assign pctxt_state_en = (lsu_asi_state[7:0] == 8'h21) & pctxt_va_vld &
lsu_alt_space_g & lsu_inst_vld_w ;
//assign pctxt_state_wr_thrd[0] = pctxt_state_en & st_inst_vld_g & thread0_g ;
assign pctxt_state_wr_thrd[0] = pctxt_state_en & asi_st_vld_g & thread0_g ;
assign pctxt_state_wr_thrd[1] = pctxt_state_en & asi_st_vld_g & thread1_g ;
assign pctxt_state_wr_thrd[2] = pctxt_state_en & asi_st_vld_g & thread2_g ;
assign pctxt_state_wr_thrd[3] = pctxt_state_en & asi_st_vld_g & thread3_g ;
//assign pctxt_state_rd_en[0] = pctxt_state_en & ld_inst_vld_g & thread0_g ;
//assign pctxt_state_rd_en[0] = pctxt_state_en & asi_ld_vld_g & thread0_g ;
//assign pctxt_state_rd_en[1] = pctxt_state_en & asi_ld_vld_g & thread1_g ;
//assign pctxt_state_rd_en[2] = pctxt_state_en & asi_ld_vld_g & thread2_g ;
//assign pctxt_state_rd_en[3] = pctxt_state_en & asi_ld_vld_g & thread3_g ;
assign sctxt_va_vld = (ldst_va_g[7:0] == 8'h10) ;
assign sctxt_state_en = (lsu_asi_state[7:0] == 8'h21) & sctxt_va_vld &
lsu_alt_space_g & lsu_inst_vld_w ;
assign pscxt_ldxa_illgl_va =
(lsu_asi_state[7:0] == 8'h21) & ~(pctxt_va_vld | sctxt_va_vld) &
lsu_alt_space_g & lsu_inst_vld_w ;
//assign sctxt_state_wr_thrd[0] = sctxt_state_en & st_inst_vld_g & thread0_g ;
assign sctxt_state_wr_thrd[0] = sctxt_state_en & asi_st_vld_g & thread0_g ;
assign sctxt_state_wr_thrd[1] = sctxt_state_en & asi_st_vld_g & thread1_g ;
assign sctxt_state_wr_thrd[2] = sctxt_state_en & asi_st_vld_g & thread2_g ;
assign sctxt_state_wr_thrd[3] = sctxt_state_en & asi_st_vld_g & thread3_g ;
//assign sctxt_state_rd_en[0] = sctxt_state_en & ld_inst_vld_g & thread0_g ;
//assign sctxt_state_rd_en[0] = sctxt_state_en & asi_ld_vld_g & thread0_g ;
//assign sctxt_state_rd_en[1] = sctxt_state_en & asi_ld_vld_g & thread1_g ;
//assign sctxt_state_rd_en[2] = sctxt_state_en & asi_ld_vld_g & thread2_g ;
//assign sctxt_state_rd_en[3] = sctxt_state_en & asi_ld_vld_g & thread3_g ;
// LSU CONTROL REGISTER. ASI=0x45,VA=0x00.
// b0 - i$ enable.
// b1 - d$ enable.
// b2 - immu enable.
// b3 - dmmu enable.
assign lsuctl_va_vld = (ldst_va_g[7:0] == 8'h00);
assign lsu_ctl_state_en = (lsu_asi_state[7:0] == 8'h45) & lsuctl_va_vld &
lsu_alt_space_g & lsu_inst_vld_w ;
assign lsuctl_illgl_va = (lsu_asi_state[7:0] == 8'h45) & ~lsuctl_va_vld &
lsu_alt_space_g & lsu_inst_vld_w ;
wire [3:0] lctl_rst ;
//assign lsu_ctl_state_wr_en[0] = (lsu_ctl_state_en & st_inst_vld_g & thread0_g) | lctl_rst[0] ;
assign lsu_ctl_state_wr_en[0] = (lsu_ctl_state_en & asi_st_vld_g & thread0_g) | lctl_rst[0] ;
assign lsu_ctl_state_wr_en[1] = (lsu_ctl_state_en & asi_st_vld_g & thread1_g) | lctl_rst[1] ;
assign lsu_ctl_state_wr_en[2] = (lsu_ctl_state_en & asi_st_vld_g & thread2_g) | lctl_rst[2];
assign lsu_ctl_state_wr_en[3] = (lsu_ctl_state_en & asi_st_vld_g & thread3_g) | lctl_rst[3];
//assign lsu_ctl_state_rd_en[0] = lsu_ctl_state_en & ld_inst_vld_g & thread0_g ;
//assign lsu_ctl_state_rd_en[0] = lsu_ctl_state_en & asi_ld_vld_g & thread0_g ;
//assign lsu_ctl_state_rd_en[1] = lsu_ctl_state_en & asi_ld_vld_g & thread1_g ;
//assign lsu_ctl_state_rd_en[2] = lsu_ctl_state_en & asi_ld_vld_g & thread2_g ;
//assign lsu_ctl_state_rd_en[3] = lsu_ctl_state_en & asi_ld_vld_g & thread3_g ;
wire [3:0] redmode_rst ;
//dff #(4) rdmode_stgd1 (
// .din ({tlu_lsu_redmode_rst[3:0]}),
// .q ({redmode_rst[3:0]}),
// .clk (clk),
// .se (se), .si (), .so ()
// );
assign redmode_rst[3:0] = tlu_lsu_redmode_rst_d1[3:0];
assign lctl_rst[0] = redmode_rst[0] | reset ;
assign lctl_rst[1] = redmode_rst[1] | reset ;
assign lctl_rst[2] = redmode_rst[2] | reset ;
assign lctl_rst[3] = redmode_rst[3] | reset ;
assign lsuctl_ctlbits_wr_en[0] = lsu_ctl_state_wr_en[0] | dfture_tap_wr_en[0] | lctl_rst[0];
assign lsuctl_ctlbits_wr_en[1] = lsu_ctl_state_wr_en[1] | dfture_tap_wr_en[1] | lctl_rst[1];
assign lsuctl_ctlbits_wr_en[2] = lsu_ctl_state_wr_en[2] | dfture_tap_wr_en[2] | lctl_rst[2];
assign lsuctl_ctlbits_wr_en[3] = lsu_ctl_state_wr_en[3] | dfture_tap_wr_en[3] | lctl_rst[3];
assign dfture_tap_wr_mx_sel = | dfture_tap_wr_en[3:0];
// Could enhance bypass/enable conditions by adding all asi conditions.
wire [5:0] lsu_ctl_reg0;
wire [5:0] lsu_ctl_reg1;
wire [5:0] lsu_ctl_reg2;
wire [5:0] lsu_ctl_reg3;
assign lsu_ctl_reg0[5:0] = lsu_dp_ctl_reg0[5:0];
assign lsu_ctl_reg1[5:0] = lsu_dp_ctl_reg1[5:0];
assign lsu_ctl_reg2[5:0] = lsu_dp_ctl_reg2[5:0];
assign lsu_ctl_reg3[5:0] = lsu_dp_ctl_reg3[5:0];
wire lsu_dcache_enable;
assign lsu_dcache_enable =
((lsu_ctl_reg0[1] & thread0_e) | (lsu_ctl_reg1[1] & thread1_e) |
(lsu_ctl_reg2[1] & thread2_e) | (lsu_ctl_reg3[1] & thread3_e)) ;
assign lsuctl_dtlb_byp_e =
(~lsu_ctl_reg0[3] & thread0_e) | (~lsu_ctl_reg1[3] & thread1_e) |
(~lsu_ctl_reg2[3] & thread2_e) | (~lsu_ctl_reg3[3] & thread3_e) ;
assign dtlb_bypass_e =
(lsuctl_dtlb_byp_e & ~hpstate_en_e) | // hpv enabled - byp is RA->PA for supv.
( tlb_byp_asi_e & ~hpstate_en_e & altspace_ldst_e) | // altspace tlb bypass - non-hpv
((hpv_priv_e & hpstate_en_e) & ~(alt_space_e & (as_if_user_asi_e | tlb_byp_asi_e)));
// hpv enabled VA->PA
assign lsu_dtlb_bypass_e = dtlb_bypass_e ;
wire dcache_enable_m,dcache_enable_g ;
dff_s #(2) dbyp_stgm (
.din ({dtlb_bypass_e,lsu_dcache_enable}),
.q ({dtlb_bypass_m,dcache_enable_m}),
.clk (clk),
.se (se), .si (), .so ()
);
dff_s #(2) dbyp_stgg (
.din ({dtlb_bypass_m,dcache_enable_m}),
.q ({lsu_dtlb_bypass_g,dcache_enable_g}),
.clk (clk),
.se (se), .si (), .so ()
);
wire lsu_ctl_reg0_bf_b0, lsu_ctl_reg1_bf_b0, lsu_ctl_reg2_bf_b0, lsu_ctl_reg3_bf_b0;
wire lsu_ctl_reg0_bf_b2, lsu_ctl_reg1_bf_b2, lsu_ctl_reg2_bf_b2, lsu_ctl_reg3_bf_b2;
bw_u1_buf_1x UZsize_ctl_reg0_b0 ( .a(lsu_ctl_reg0[0]), .z(lsu_ctl_reg0_bf_b0) );
bw_u1_buf_1x UZsize_ctl_reg0_b2 ( .a(lsu_ctl_reg0[2]), .z(lsu_ctl_reg0_bf_b2) );
bw_u1_buf_1x UZsize_ctl_reg1_b0 ( .a(lsu_ctl_reg1[0]), .z(lsu_ctl_reg1_bf_b0) );
bw_u1_buf_1x UZsize_ctl_reg1_b2 ( .a(lsu_ctl_reg1[2]), .z(lsu_ctl_reg1_bf_b2) );
bw_u1_buf_1x UZsize_ctl_reg2_b0 ( .a(lsu_ctl_reg2[0]), .z(lsu_ctl_reg2_bf_b0) );
bw_u1_buf_1x UZsize_ctl_reg2_b2 ( .a(lsu_ctl_reg2[2]), .z(lsu_ctl_reg2_bf_b2) );
bw_u1_buf_1x UZsize_ctl_reg3_b0 ( .a(lsu_ctl_reg3[0]), .z(lsu_ctl_reg3_bf_b0) );
bw_u1_buf_1x UZsize_ctl_reg3_b2 ( .a(lsu_ctl_reg3[2]), .z(lsu_ctl_reg3_bf_b2) );
assign lsu_ifu_icache_en[3:0] =
{lsu_ctl_reg3_bf_b0,lsu_ctl_reg2_bf_b0,lsu_ctl_reg1_bf_b0,lsu_ctl_reg0_bf_b0} & ~tlu_lsu_redmode[3:0] ;
assign lsu_ifu_itlb_en[3:0] =
{lsu_ctl_reg3_bf_b2,lsu_ctl_reg2_bf_b2,lsu_ctl_reg1_bf_b2,lsu_ctl_reg0_bf_b2} & ~tlu_lsu_redmode[3:0] ;
//=========================================================================================
// DCACHE Access thru IOBrdge
//=========================================================================================
wire iob_fwdpkt_vld ;
dff_s iobvld_stg (
.din (lsu_iobrdge_fwd_pkt_vld),
.q (iob_fwdpkt_vld),
.clk (clk),
.se (se), .si (), .so ()
);
wire dcache_iob_wr_e, dcache_iob_rd_e ;
wire dcache_iob_wr, dcache_iob_rd ;
assign dcache_iob_wr =
~lsu_iobrdge_tap_rq_type_b8[8] & lsu_iobrdge_tap_rq_type_b6_b3[6] & lsu_iobrdge_fwd_pkt_vld ;
assign dcache_iob_rd =
lsu_iobrdge_tap_rq_type_b8[8] & lsu_iobrdge_tap_rq_type_b6_b3[6] & lsu_iobrdge_fwd_pkt_vld ;
dff_s #(2) dcrw_stge (
.din ({dcache_iob_wr,dcache_iob_rd}),
.q ({dcache_iob_wr_e,dcache_iob_rd_e}),
.clk (clk),
.se (se), .si (), .so ()
);
assign lsu_dc_iob_access_e = dcache_iob_wr_e | dcache_iob_rd_e ;
//=========================================================================================
// Miscellaneous ASI
//=========================================================================================
// Defeature effects the asi lsu_ctl_reg.
// Margin ASI
// Diag ASI - No TAP access
// BIST ASI
assign tap_thread[0] = ~lsu_iobrdge_tap_rq_type_b1_b0[1] & ~lsu_iobrdge_tap_rq_type_b1_b0[0] ;
assign tap_thread[1] = ~lsu_iobrdge_tap_rq_type_b1_b0[1] & lsu_iobrdge_tap_rq_type_b1_b0[0] ;
assign tap_thread[2] = lsu_iobrdge_tap_rq_type_b1_b0[1] & ~lsu_iobrdge_tap_rq_type_b1_b0[0] ;
assign tap_thread[3] = lsu_iobrdge_tap_rq_type_b1_b0[1] & lsu_iobrdge_tap_rq_type_b1_b0[0] ;
wire bist_tap_rd,bist_tap_wr ;
assign bist_tap_rd =
lsu_iobrdge_tap_rq_type_b8[8] & lsu_iobrdge_tap_rq_type_b6_b3[5] & iob_fwdpkt_vld ;
assign bist_tap_wr =
~lsu_iobrdge_tap_rq_type_b8[8] & lsu_iobrdge_tap_rq_type_b6_b3[5] & iob_fwdpkt_vld ;
/*
dff_s #(2) bstrw_stge (
.din ({bist_tap_rd,bist_tap_wr}),
.q ({bist_tap_rd_en,bist_tap_wr_en}),
.clk (clk),
.se (se), .si (), .so ()
);
*/
dff_s #(1) bstrw_stge (
.din ({bist_tap_wr}),
.q ({bist_tap_wr_en}),
.clk (clk),
.se (se), .si (), .so ()
);
wire mrgn_tap_rd,mrgn_tap_wr ;
assign mrgn_tap_rd =
lsu_iobrdge_tap_rq_type_b8[8] & lsu_iobrdge_tap_rq_type_b6_b3[4] & iob_fwdpkt_vld ;
assign mrgn_tap_wr =
~lsu_iobrdge_tap_rq_type_b8[8] & lsu_iobrdge_tap_rq_type_b6_b3[4] & iob_fwdpkt_vld ;
/*
dff_s #(2) mrgnrw_stge (
.din ({mrgn_tap_rd,mrgn_tap_wr}),
.q ({mrgn_tap_rd_en,mrgn_tap_wr_en}),
.clk (clk),
.se (se), .si (), .so ()
);
*/
dff_s #(1) mrgnrw_stge (
.din ({mrgn_tap_wr}),
.q ({mrgn_tap_wr_en}),
.clk (clk),
.se (se), .si (), .so ()
);
wire dfture_access_vld ;
wire [3:0] dfture_tap_rd,dfture_tap_wr ;
assign dfture_access_vld = lsu_iobrdge_tap_rq_type_b6_b3[3] & iob_fwdpkt_vld ;
assign dfture_tap_rd[0] =
lsu_iobrdge_tap_rq_type_b8[8] & dfture_access_vld & tap_thread[0] ;
assign dfture_tap_rd[1] =
lsu_iobrdge_tap_rq_type_b8[8] & dfture_access_vld & tap_thread[1] ;
assign dfture_tap_rd[2] =
lsu_iobrdge_tap_rq_type_b8[8] & dfture_access_vld & tap_thread[2] ;
assign dfture_tap_rd[3] =
lsu_iobrdge_tap_rq_type_b8[8] & dfture_access_vld & tap_thread[3] ;
wire dfture_tap_rd_default;
assign dfture_tap_rd_default = ~| dfture_tap_rd[2:0];
assign dfture_tap_wr[0] =
~lsu_iobrdge_tap_rq_type_b8[8] & dfture_access_vld & tap_thread[0] ;
assign dfture_tap_wr[1] =
~lsu_iobrdge_tap_rq_type_b8[8] & dfture_access_vld & tap_thread[1] ;
assign dfture_tap_wr[2] =
~lsu_iobrdge_tap_rq_type_b8[8] & dfture_access_vld & tap_thread[2] ;
assign dfture_tap_wr[3] =
~lsu_iobrdge_tap_rq_type_b8[8] & dfture_access_vld & tap_thread[3] ;
dff_s #(8) dftrw_stge (
.din ({dfture_tap_rd_default, dfture_tap_rd[2:0],dfture_tap_wr[3:0]}),
.q ({dfture_tap_rd_d1[3:0], dfture_tap_wr_en[3:0]}),
.clk (clk),
.se (se), .si (), .so ()
);
assign dfture_tap_rd_en [0] = dfture_tap_rd_d1[0] & ~rst_tri_en;
assign dfture_tap_rd_en [1] = dfture_tap_rd_d1[1] & ~rst_tri_en;
assign dfture_tap_rd_en [2] = dfture_tap_rd_d1[2] & ~rst_tri_en;
assign dfture_tap_rd_en [3] = dfture_tap_rd_d1[3] | rst_tri_en;
// BIST_Controller ASI
wire bistctl_va_vld_m,bistctl_state_en_m;
assign bistctl_va_vld_m = (lsu_ldst_va_b7_b0_m[7:0] == 8'h00);
assign bistctl_state_en_m = (lsu_dctl_asi_state_m[7:0] == 8'h42) & bistctl_va_vld_m &
lsu_alt_space_m ;
dff_s #(2) bistdcd_stw (
.din ({bistctl_va_vld_m,bistctl_state_en_m}),
.q ({bistctl_va_vld,bistctl_state_en}),
.clk (clk),
.se (se), .si (), .so ()
);
// asi42 dealt with as a whole.
/*assign bistctl_illgl_va = (lsu_asi_state[7:0] == 8'h42) & ~bistctl_va_vld &
lsu_alt_space_g ;*/
//assign bistctl_rd_en = bistctl_state_en & asi_ld_vld_g ;
assign bistctl_wr_en = (bistctl_state_en & asi_st_vld_g) | bist_tap_wr_en ;
//assign bistctl_rd_en = bistctl_state_en & ld_inst_vld_g ;
//assign bistctl_wr_en = (bistctl_state_en & st_inst_vld_g) | bist_tap_wr_en ;
//test_stub interface. bist_tap_wr_en should exclude?
assign bist_ctl_reg_wr_en = bistctl_wr_en;
// Self-Timed Margin Control ASI
wire mrgnctl_va_vld_m,mrgnctl_state_en_m;
assign mrgnctl_va_vld_m = (lsu_ldst_va_b7_b0_m[7:0] == 8'h00);
assign mrgnctl_state_en_m = (lsu_dctl_asi_state_m[7:0] == 8'h44) & mrgnctl_va_vld_m &
lsu_alt_space_m ;
dff_s #(2) mrgndcd_stw (
.din ({mrgnctl_va_vld_m,mrgnctl_state_en_m}),
.q ({mrgnctl_va_vld,mrgnctl_state_en}),
.clk (clk),
.se (se), .si (), .so ()
);
assign mrgnctl_illgl_va = (lsu_asi_state[7:0] == 8'h44) & ~mrgnctl_va_vld &
lsu_alt_space_g ;
assign mrgnctl_wr_en = ((mrgnctl_state_en & asi_st_vld_g) | mrgn_tap_wr_en | ~dctl_rst_l) & ~sehold; //bug 4508
// LSU Diag Reg ASI
// No access from tap.
wire ldiagctl_va_vld_m,ldiagctl_state_en_m;
assign ldiagctl_va_vld_m = (lsu_ldst_va_b7_b0_m[7:0] == 8'h10);
assign ldiagctl_state_en_m = (lsu_dctl_asi_state_m[7:0] == 8'h42) & ldiagctl_va_vld_m &
lsu_alt_space_m ;
dff_s #(2) ldiagdcd_stw (
.din ({ldiagctl_va_vld_m,ldiagctl_state_en_m}),
.q ({ldiagctl_va_vld,ldiagctl_state_en}),
.clk (clk),
.se (se), .si (), .so ()
);
// asi42 dealt with as a whole.
/*assign ldiagctl_illgl_va = (lsu_asi_state[7:0] == 8'h42) & ~ldiagctl_va_vld &
lsu_alt_space_g ;*/
wire asi42_g ;
wire ifu_asi42_flush_g ;
assign ifu_asi42_flush_g =
bistctl_state_en | ldiagctl_state_en | // lsu's asi42 should not set asi queue.
(asi42_g & asi42_illgl_va) ; // illgl-va should not set asi queue.
//assign ldiagctl_rd_en = ldiagctl_state_en & asi_ld_vld_g ;
assign ldiagctl_wr_en = (ldiagctl_state_en & asi_st_vld_g) | reset;
//assign ldiagctl_rd_en = ldiagctl_state_en & ld_inst_vld_g ;
//assign ldiagctl_wr_en = (ldiagctl_state_en & st_inst_vld_g) | reset;
wire instmsk_va_vld ;
assign instmsk_va_vld = (ldst_va_g[7:0] == 8'h08);
assign asi42_g = (lsu_asi_state[7:0] == 8'h42) ;
assign asi42_illgl_va =
asi42_g &
~(ldiagctl_va_vld | bistctl_va_vld | instmsk_va_vld) &
lsu_alt_space_g ;
//=========================================================================================
// Partition ID Register
//=========================================================================================
// ASI=58, VA=0x80, Per thread
// The pid is to be used by tlb-cam, and writes to tlb. It is kept in the lsu
// as it is used by the dtlb, plus changes to mmu_dp are to be kept to a minimum.
// Trap if supervisor accesses hyperpriv asi - see supv_use_hyp. Could be incorrect.
// Correct on merge to mainline.
// The VA compares can probably be shortened.
assign pid_va_vld = (ldst_va_g[7:0] == 8'h80);
assign pid_state_en = (lsu_asi_state[7:0] == 8'h58) & pid_va_vld &
lsu_alt_space_g & lsu_inst_vld_w ;
//assign pid_illgl_va = (lsu_asi_state[7:0] == 8'h58) & ~pid_va_vld &
// lsu_alt_space_g & lsu_inst_vld_w ;
// remove reset ??
//assign pid_state_wr_en[0] = (pid_state_en & st_inst_vld_g & thread0_g) | reset ;
assign pid_state_wr_en[0] = (pid_state_en & asi_st_vld_g & thread0_g) | reset ;
assign pid_state_wr_en[1] = (pid_state_en & asi_st_vld_g & thread1_g) | reset ;
assign pid_state_wr_en[2] = (pid_state_en & asi_st_vld_g & thread2_g) | reset ;
assign pid_state_wr_en[3] = (pid_state_en & asi_st_vld_g & thread3_g) | reset ;
//assign pid_state_rd_en[0] = pid_state_en & ld_inst_vld_g & thread0_g ;
//assign pid_state_rd_en[0] = pid_state_en & asi_ld_vld_g & thread0_g ;
//assign pid_state_rd_en[1] = pid_state_en & asi_ld_vld_g & thread1_g ;
//assign pid_state_rd_en[2] = pid_state_en & asi_ld_vld_g & thread2_g ;
//assign pid_state_rd_en[3] = pid_state_en & asi_ld_vld_g & thread3_g ;
//=========================================================================================
// Local LDXA Read
//=========================================================================================
// Timing : rd_en changed to _en with inst_vld
//wire [3:0] misc_ctl_sel ;
wire misc_tap_rd_sel ;
/*
assign misc_tap_rd_sel = mrgn_tap_rd_en | bist_tap_rd_en | dfture_tap_rd_sel ;
assign misc_ctl_sel[0] = bist_tap_rd_en | (~misc_tap_rd_sel & bistctl_state_en & ld_inst_vld_unflushed) ;
assign misc_ctl_sel[1] = mrgn_tap_rd_en | (~misc_tap_rd_sel & mrgnctl_state_en & ld_inst_vld_unflushed) ;
assign misc_ctl_sel[3] = dfture_tap_rd_sel ;
//assign misc_ctl_sel[2] = (~misc_tap_rd_sel & ldiagctl_state_en & ld_inst_vld_unflushed) ;
assign misc_ctl_sel[2] = ~(misc_ctl_sel[0] | misc_ctl_sel[1] | misc_ctl_sel[3] ); //force default
*/
//****push misc_ctl_sel in previosu cycle*****
wire [3:0] misc_ctl_sel_din;
//0-in bug, priority encode tap requests to prevent illegal type through one-hot mux
wire dfture_tap_rd_or ;
assign dfture_tap_rd_or = | (dfture_tap_rd [3:0]);
assign misc_tap_rd_sel = mrgn_tap_rd | bist_tap_rd | dfture_tap_rd_or ;
assign misc_ctl_sel_din[0] = bist_tap_rd |
(~misc_tap_rd_sel & bistctl_state_en_m & ld_inst_vld_m) ;
assign misc_ctl_sel_din[1] = (~bist_tap_rd & mrgn_tap_rd) |
(~misc_tap_rd_sel & mrgnctl_state_en_m & ld_inst_vld_m) ;
assign misc_ctl_sel_din[3] = ~bist_tap_rd & ~mrgn_tap_rd & dfture_tap_rd_or;
assign misc_ctl_sel_din[2] = ~(misc_ctl_sel_din[0] | misc_ctl_sel_din[1] | misc_ctl_sel_din[3] ) ;
// ASI accesses should be mutex except for non-access cases.
assign lsu_asi_sel_fmx1[0] = pctxt_state_en & ld_inst_vld_unflushed;
assign lsu_asi_sel_fmx1[1] = sctxt_state_en & ld_inst_vld_unflushed & ~lsu_asi_sel_fmx1[0];
assign lsu_asi_sel_fmx1[2] = ~(|lsu_asi_sel_fmx1[1:0]); //force default
assign lsu_asi_sel_fmx2[0] = |lsu_asi_sel_fmx1[1:0] | (pid_state_en & ld_inst_vld_unflushed) ;
assign lsu_asi_sel_fmx2[1] = lsu_ctl_state_en & ld_inst_vld_unflushed & ~(lsu_asi_sel_fmx2[0]);
assign lsu_asi_sel_fmx2[2] = ~(|lsu_asi_sel_fmx2[1:0]) ; //force default
wire va_wtchpt_en;
wire lsu_asi_rd_sel ;
//assign lsu_asi_rd_sel = ((|lsu_asi_sel_fmx1[1:0]) |
// ((pid_state_en | va_wtchpt_en) & ld_inst_vld_unflushed) |
// (|lsu_asi_sel_fmx2[1:0]) |
// misc_asi_rd_en) &
// lsu_inst_vld_w ;
assign lsu_asi_rd_sel = ((|lsu_asi_sel_fmx1[1:0]) |
(pid_state_en & ld_inst_vld_unflushed) | //remove va_wtchpt_en
(|lsu_asi_sel_fmx2[1:0]) |
misc_asi_rd_en) &
lsu_inst_vld_w ;
assign lsu_asi_rd_en = (lsu_asi_rd_sel | lsu_va_wtchpt_sel_g) & ~dctl_early_flush_w ; //add va_wtchpt
//assign lsu_asi_rd_en = lsu_asi_rd_sel & ~lsu_flush_pipe_w ;
assign misc_asi_rd_en = (bistctl_state_en | mrgnctl_state_en | ldiagctl_state_en) & ld_inst_vld_unflushed ;
assign lsu_local_ldxa_sel_g = lsu_asi_rd_sel & ~rst_tri_en ; // w/o flush
assign lsu_local_ldxa_tlbrd_sel_g = (lsu_tlb_tag_rd_vld_g | lsu_tlb_data_rd_vld_g) & ~rst_tri_en;
assign lsu_va_wtchpt_sel_g = (va_wtchpt_en & ld_inst_vld_unflushed) & ~rst_tri_en;
assign lsu_local_diagnstc_tagrd_sel_g = (~(lsu_local_ldxa_sel_g | lsu_local_ldxa_tlbrd_sel_g |
lsu_va_wtchpt_sel_g)) | rst_tri_en; //add va_wtchpt
// or diagnostic read w/ asi read enable
assign lsu_diagnstc_asi_rd_en = lsu_asi_rd_en | dtagv_diagnstc_rd_g ; //Bug 3959
//assign lsu_diagnstc_asi_rd_en = lsu_asi_rd_en | dtagv_diagnstc_rd_g | lsu_local_ldxa_tlbrd_sel_g;
dff_s #(1) lldxa_stw2 (
.din (lsu_diagnstc_asi_rd_en),
.q (lsu_asi_rd_en_w2),
.clk (clk),
.se (se), .si (), .so ()
);
wire ldxa_tlbrd0_w2,ldxa_tlbrd1_w2,ldxa_tlbrd2_w2,ldxa_tlbrd3_w2;
wire ldxa_tlbrd0_w3,ldxa_tlbrd1_w3,ldxa_tlbrd2_w3,ldxa_tlbrd3_w3;
// stg mismatched intentionally. stxa_tid decode can be used by ldxa.
assign ldxa_tlbrd3_w2 = tlu_stxa_thread3_w2 & lsu_local_ldxa_tlbrd_sel_g ;
assign ldxa_tlbrd2_w2 = tlu_stxa_thread2_w2 & lsu_local_ldxa_tlbrd_sel_g ;
assign ldxa_tlbrd1_w2 = tlu_stxa_thread1_w2 & lsu_local_ldxa_tlbrd_sel_g ;
assign ldxa_tlbrd0_w2 = tlu_stxa_thread0_w2 & lsu_local_ldxa_tlbrd_sel_g ;
// Bug 3959
dff_s #(4) tlbrd_stw3 (
.din ({ldxa_tlbrd3_w2,ldxa_tlbrd2_w2,
ldxa_tlbrd1_w2,ldxa_tlbrd0_w2}),
.q ({ldxa_tlbrd3_w3,ldxa_tlbrd2_w3,
ldxa_tlbrd1_w3,ldxa_tlbrd0_w3}),
.clk (clk),
.se (se), .si (), .so ()
);
// pid and va-wtchpt va removed.
assign lsu_asi_illgl_va =
lsuctl_illgl_va | pscxt_ldxa_illgl_va | mrgnctl_illgl_va | asi42_illgl_va ;
assign lsu_asi_illgl_va_cmplt[0] = lsu_asi_illgl_va & ld_inst_vld_g & thread0_g ;
assign lsu_asi_illgl_va_cmplt[1] = lsu_asi_illgl_va & ld_inst_vld_g & thread1_g ;
assign lsu_asi_illgl_va_cmplt[2] = lsu_asi_illgl_va & ld_inst_vld_g & thread2_g ;
assign lsu_asi_illgl_va_cmplt[3] = lsu_asi_illgl_va & ld_inst_vld_g & thread3_g ;
dff_s #(4) lsuillgl_stgw2(
.din (lsu_asi_illgl_va_cmplt[3:0]),
.q (lsu_asi_illgl_va_cmplt_w2[3:0]),
.clk (clk),
.se (se), .si (), .so ()
);
//=========================================================================================
// ASI_DCACHE_TAG way decode
//=========================================================================================
// Bug 4569.
// add sehold. adding in dctldp flop will cause critical path.
wire [3:0] dtag_rsel_dcd,dtag_rsel_hold ;
assign dtag_rsel_dcd[3:0] = {(lsu_ldst_va_b12_b11_m[12:11] == 2'b11),
(lsu_ldst_va_b12_b11_m[12:11] == 2'b10),
(lsu_ldst_va_b12_b11_m[12:11] == 2'b01),
(lsu_ldst_va_b12_b11_m[12:11] == 2'b00)};
//bug5994
dffe_s #(4) dtag_hold (
.din (dtag_rsel_dcd[3:0]),
.q (dtag_rsel_hold[3:0]),
.en (sehold),
.clk (clk),
.se (se), .si (), .so ()
);
assign lsu_dtag_rsel_m[3:0] = sehold ? dtag_rsel_hold[3:0] : dtag_rsel_dcd[3:0] ;
//=========================================================================================
// Watchpoint Control
//=========================================================================================
wire va_vld;
assign va_vld = (ldst_va_g[7:0] == 8'h38);
assign va_wtchpt_en = (lsu_asi_state[7:0] == 8'h58) & va_vld &
lsu_alt_space_g & lsu_inst_vld_w ;
// Illegal va checking for asi 58 done in MMU.
// one VA watchptr supported per thread
// Need to read register !!!
// Switchout thread on read.
// qualify with inst_vld_w.
//assign va_wtchpt_rd_en = va_wtchpt_en & ld_inst_vld_g ;
wire va_wtchpt0_wr_en, va_wtchpt1_wr_en, va_wtchpt2_wr_en, va_wtchpt3_wr_en;
//assign va_wtchpt0_wr_en = va_wtchpt_en & st_inst_vld_g & thread0_g;
assign va_wtchpt0_wr_en = va_wtchpt_en & asi_st_vld_g & thread0_g;
assign va_wtchpt1_wr_en = va_wtchpt_en & asi_st_vld_g & thread1_g;
assign va_wtchpt2_wr_en = va_wtchpt_en & asi_st_vld_g & thread2_g;
assign va_wtchpt3_wr_en = va_wtchpt_en & asi_st_vld_g & thread3_g;
assign lsu_va_wtchpt0_wr_en_l = ~va_wtchpt0_wr_en ;
assign lsu_va_wtchpt1_wr_en_l = ~va_wtchpt1_wr_en ;
assign lsu_va_wtchpt2_wr_en_l = ~va_wtchpt2_wr_en ;
assign lsu_va_wtchpt3_wr_en_l = ~va_wtchpt3_wr_en ;
assign vw_wtchpt_cmp_en_m = // VA Write Watchpoint Enable
(thread0_m & lsu_ctl_reg0[4]) |
(thread1_m & lsu_ctl_reg1[4]) |
(thread2_m & lsu_ctl_reg2[4]) |
(thread3_m & lsu_ctl_reg3[4]) ;
assign vr_wtchpt_cmp_en_m = // VA Read Watchpoint Enable
(thread0_m & lsu_ctl_reg0[5]) |
(thread1_m & lsu_ctl_reg1[5]) |
(thread2_m & lsu_ctl_reg2[5]) |
(thread3_m & lsu_ctl_reg3[5]) ;
assign va_wtchpt_cmp_en_m =
(vw_wtchpt_cmp_en_m & st_inst_vld_m) |
(vr_wtchpt_cmp_en_m & ld_inst_vld_m) ;
//=========================================================================================
// Hit/Miss/Fill Control
//=========================================================================================
dff_s #(10) stg_m (
.din ({ld_inst_vld_e, st_inst_vld_e,ldst_sz_e[1:0],
ifu_lsu_rd_e[4:0],ifu_lsu_ldst_fp_e}),
.q ({ld_inst_vld_m, st_inst_vld_m,ldst_sz_m[1:0],
ld_rd_m[4:0],fp_ldst_m}),
.clk (clk),
.se (se), .si (), .so ()
);
wire dcache_arry_data_sel_e;
assign dcache_arry_data_sel_e = lsu_bist_rvld_e | ld_inst_vld_e | dcache_iob_rd_e ;
dff_s #(1) dcache_arry_data_sel_stgm (
.din (dcache_arry_data_sel_e),
.q (dcache_arry_data_sel_m),
.clk (clk),
.se (se), .si (), .so ()
);
dff_s #(10) stg_g (
.din ({ld_inst_vld_m, st_inst_vld_m,ldst_sz_m[1:0],
ld_rd_m[4:0],fp_ldst_m}),
.q ({ld_inst_vld_unflushed, st_inst_vld_unflushed,ldst_sz_g[1:0],
ld_rd_g[4:0],fp_ldst_g}),
.clk (clk),
.se (se), .si (), .so ()
);
//assign asi_ld_vld_g = ld_inst_vld_unflushed & lsu_inst_vld_w & ~dctl_early_flush_w ;
assign asi_st_vld_g = st_inst_vld_unflushed & lsu_inst_vld_w & ~dctl_early_flush_w ;
assign ld_inst_vld_g = ld_inst_vld_unflushed & lsu_inst_vld_w & ~dctl_flush_pipe_w ;
assign st_inst_vld_g = st_inst_vld_unflushed & lsu_inst_vld_w & ~dctl_flush_pipe_w ;
assign lsu_way_hit[0] = cache_way_hit_buf1[0] & dcache_enable_g ;
assign lsu_way_hit[1] = cache_way_hit_buf1[1] & dcache_enable_g ;
assign lsu_way_hit[2] = cache_way_hit_buf1[2] & dcache_enable_g ;
assign lsu_way_hit[3] = cache_way_hit_buf1[3] & dcache_enable_g ;
//assign st_set_index_g[5:0] = ldst_va_g[9:4] ;
//assign st_set_way_g[3:1] = lsu_way_hit[3:1] ;
// This should contain ld miss, MMU miss, exception.
// should tlb_cam_miss be factored in or can miss/hit be solely
// based on way_hit.
wire tlb_cam_hit_mod ;
dff_s stgcmiss_g (
.din (tlb_cam_hit),
.q (tlb_cam_hit_mod),
.clk (clk),
.se (se), .si (), .so ()
);
// NOTE !! qualification with tte_data_parity_error removed for timing.
assign tlb_cam_hit_g = tlb_cam_hit_mod ;
//assign tlb_cam_hit_g = tlb_cam_hit_mod & ~tte_data_parity_error ;
/*assign ld_stb_hit_g =
ld_stb0_full_raw_g | ld_stb1_full_raw_g |
ld_stb2_full_raw_g | ld_stb3_full_raw_g |
ld_stb0_partial_raw_g | ld_stb1_partial_raw_g |
ld_stb2_partial_raw_g | ld_stb3_partial_raw_g ; */
wire nceen_pipe_m, nceen_pipe_g ;
wire [3:0] lsu_nceen_d1;
dff_s #(4) nceen_stg (
.din (ifu_lsu_nceen[3:0]),
.q (lsu_nceen_d1[3:0]),
.clk (clk),
.se (se), .si (), .so ()
);
assign nceen_pipe_m =
(thread0_m & lsu_nceen_d1[0]) | (thread1_m & lsu_nceen_d1[1]) |
(thread2_m & lsu_nceen_d1[2]) | (thread3_m & lsu_nceen_d1[3]) ;
dff_s #(1) stgg_een (
.din (nceen_pipe_m),
.q (nceen_pipe_g),
.clk (clk),
.se (se), .si (), .so ()
);
//wire tte_data_perror_corr_en ;
wire tte_data_perror_unc_en ;
// separate ld from st for error reporting.
assign tte_data_perror_unc_en = ld_inst_vld_unflushed & tte_data_perror_unc & nceen_pipe_g ;
//assign tte_data_perror_unc_en = tte_data_perror_unc & nceen_pipe_g ;
//assign tte_data_perror_corr_en = tte_data_perror_corr ;
//assign tte_data_perror_corr_en = tte_data_perror_corr & ceen_pipe_g ;
wire dtlb_perror_en_w,dtlb_perror_en_w2,dtlb_perror_en_w3 ;
assign dtlb_perror_en_w = tte_data_perror_unc_en ;
//assign dtlb_perror_en_w = tte_data_perror_unc_en | tte_data_perror_corr_en ;
dff_s #(1) stgw2_perr (
.din (dtlb_perror_en_w),
.q (dtlb_perror_en_w2),
.clk (clk),
.se (se), .si (), .so ()
);
dff_s #(1) stgw3_perr (
.din (dtlb_perror_en_w2),
.q (dtlb_perror_en_w3),
.clk (clk),
.se (se), .si (), .so ()
);
// For now, "or" ld_inst_vld_g and ldst_dbl. Ultimately, it ldst_dbl
// needs to cause ld_inst_vld_g to be asserted.
// st and ld ldst_dbl terms are redundant.
// Diagnostic Dcache access will force a hit in cache. Whatever is read
// out will be written back to irf regardless of whether hit or not. The
// expectation is that cache has been set up to hit.
// lsu_dcache_enable is redundant as factored in lsu_way_hit !!!
// squash both ld_miss and ld_hit in cause of dtlb unc data error.
wire ldd_force_l2access_g;
wire int_ldd_g, fp_ldd_g;
assign fp_ldd_g = fp_ldst_g & ~(blk_asi_g & lsu_alt_space_g);
//sas code need int_ldd_g
assign int_ldd_g = ldst_dbl_g & ~fp_ldd_g;
assign ldd_force_l2access_g = int_ldd_g;
assign lsu_ld_miss_wb =
(~(|lsu_way_hit[3:0]) | ~dcache_enable_g | ~(tlb_cam_hit_g | lsu_dtlb_bypass_g) |
ldxa_internal | ldd_force_l2access_g | atomic_g | endian_mispred_g | // remove stb_cam_hit
dcache_rd_parity_error | dtag_perror_g) &
~((dc_diagnstc_asi_g & lsu_alt_space_g)) &
//~(tte_data_perror_unc_en | tte_data_perror_corr_en | (dc_diagnstc_asi_g & lsu_alt_space_g)) &
(ld_vld & (~lsu_alt_space_g | (lsu_alt_space_g & recognized_asi_g))) |
//(ld_inst_vld_g & (~lsu_alt_space_g | (lsu_alt_space_g & recognized_asi_g))) |
//(ldst_dbl_g & st_inst_vld_g) // signal ld-miss for stdbl.
ncache_asild_rq_g ; // asi ld requires bypass
assign lsu_ld_hit_wb =
((|lsu_way_hit[3:0]) & dcache_enable_g & (tlb_cam_hit_g | lsu_dtlb_bypass_g) & //bug3702
~ldxa_internal & ~dcache_rd_parity_error & ~dtag_perror_g & ~endian_mispred_g &
~ldd_force_l2access_g & ~atomic_g & ~ncache_asild_rq_g) & // remove stb_cam_hit
~((dc_diagnstc_asi_g & lsu_alt_space_g)) &
//~(tte_data_perror_unc_en | tte_data_perror_corr_en | (dc_diagnstc_asi_g & lsu_alt_space_g)) &
ld_vld & (~lsu_alt_space_g | (lsu_alt_space_g & recognized_asi_g)) ;
//ld_inst_vld_g & (~lsu_alt_space_g | (lsu_alt_space_g & recognized_asi_g)) ;
// force hit for diagnostic write.
// correctible dtlb data parity error on cam will cause dmmu miss.
// prefetch will rely on the ld_inst_vld/st_inst_vld not being asserted
// to prevent mmu_miss from being signalled if prefetch does not translate.
// Timing Change : Remove data perror from dmmu_miss ; to be treated as disrupting trap.
//SC assign dmmu_miss_g =
//SC ~tlb_cam_hit_mod & ~lsu_dtlb_bypass_g &
//SC //~(tlb_cam_hit_mod & ~tte_data_perror_corr) & ~lsu_dtlb_bypass_g &
//SC ((ld_inst_vld_unflushed & lsu_inst_vld_w) |
//SC (st_inst_vld_unflushed & lsu_inst_vld_w)) &
//SC ~(ldxa_internal | stxa_internal | early_trap_vld_g) ;
//SC wire dmmu_miss_only_g ;
//SC assign dmmu_miss_only_g =
//SC ~tlb_cam_hit_mod & ~lsu_dtlb_bypass_g &
//SC //~(tlb_cam_hit_mod & ~tte_data_perror_corr) & ~lsu_dtlb_bypass_g &
//SC ((ld_inst_vld_unflushed & lsu_inst_vld_w) |
//SC (st_inst_vld_unflushed & lsu_inst_vld_w)) &
//SC ~(ldxa_internal | stxa_internal);
// Atomic Handling :
// Bypass to irf will occur. However, the loads will not write to cache/tag etc.
// Exceptions, tlb miss will have to be included.
// diagnostic dcache/dtagv will read respective arrays in pipeline. (changed!)
// They will not switch out thread with this assumption.
//dc_diagnstc will not switch out, dtagv will switch out
//wire dc_diagnstc_rd_g;
//assign dc_diagnstc_rd_g = dc_diagnstc_asi_g & ld_inst_vld_g & lsu_alt_space_g ;
//wire dc0_diagnstc_rd_g,dc1_diagnstc_rd_g,dc2_diagnstc_rd_g,dc3_diagnstc_rd_g ;
//wire dc0_diagnstc_rd_w2,dc1_diagnstc_rd_w2,dc2_diagnstc_rd_w2,dc3_diagnstc_rd_w2 ;
//assign dc0_diagnstc_rd_g = dc_diagnstc_rd_g & thread0_g ;
//assign dc1_diagnstc_rd_g = dc_diagnstc_rd_g & thread1_g ;
//assign dc2_diagnstc_rd_g = dc_diagnstc_rd_g & thread2_g ;
//assign dc3_diagnstc_rd_g = dc_diagnstc_rd_g & thread3_g ;
//dff #(4) stgw2_dcdiag (
// .din ({dc3_diagnstc_rd_g,dc2_diagnstc_rd_g,dc1_diagnstc_rd_g,dc0_diagnstc_rd_g}),
// .q ({dc3_diagnstc_rd_w2,dc2_diagnstc_rd_w2,dc1_diagnstc_rd_w2,dc0_diagnstc_rd_w2}),
// .clk (clk),
// .se (se), .si (), .so ()
// );
assign dtagv_diagnstc_rd_g = dtagv_diagnstc_asi_g & ld_inst_vld_g & lsu_alt_space_g ;
// Prefetch will swo thread if it does not miss in tlb.
dff_s stgm_prf (
.din (ifu_lsu_pref_inst_e),
.q (pref_inst_m),
.clk (clk),
.se (se), .si (), .so ()
);
dff_s stgg_prf (
.din (pref_inst_m),
.q (pref_inst_g),
.clk (clk),
.se (se), .si (), .so ()
);
//assign lsu_ifu_data_error_w = 1'b0 ;
// is this redundant ? isn't lsu_ncache_ld_e sufficient ?
assign atomic_ld_squash_e =
~lmq_ld_rq_type_e[2] & lmq_ld_rq_type_e[1] & lmq_ld_rq_type_e[0] ;
// bypass will occur with hit in d$ or data return from L2.
// Fill for dcache diagnostic rd will happen regardless. dfill vld qualified with
// flush_pipe and inst_vld !!!
//timing fix. move logic to previous cycle M.
//assign lsu_exu_dfill_vld_w2 =
// (l2fill_vld_g & ~(unc_err_trap_g | l2fill_fpld_g)) | // fill
// (~fp_ldst_g & ld_inst_vld_unflushed & lsu_inst_vld_w) | // in pipe
// intld_byp_data_vld ; // bypass
wire lsu_exu_dfill_vld_m;
wire intld_byp_data_vld_e,intld_byp_data_vld_m ;
wire intld_byp_data_vld ;
wire ldxa_swo_annul ;
assign lsu_exu_dfill_vld_m =
(l2fill_vld_m & ~(unc_err_trap_m | l2fill_fpld_m)) | // fill
(~fp_ldst_m & ld_inst_vld_m &
~(ldxa_swo_annul & lsu_alt_space_m) & flush_w_inst_vld_m) | // in pipe
intld_byp_data_vld_m ; // bypass
dff_s #(1) dfill_vld_stgg (
.din (lsu_exu_dfill_vld_m),
.q (lsu_exu_dfill_vld_w2),
.clk (clk),
.se (se), .si (), .so ()
);
//------
// Bld errors : Bug 4315
// Errors need to be accummulated across helpers. Once unc error detected
// in any helper, then all further writes to frf are squashed.
// daccess_error trap taken at very end if *any* helper had an unc error.
wire bld_cnt_max_m,bld_cnt_max_g ;
assign bld_cnt_max_m = lsu_bld_cnt_m[2] & lsu_bld_cnt_m[1] & lsu_bld_cnt_m[0] ;
wire [1:0] cpx_ld_err_m ;
dff_s #(3) lderr_stgm (
.din ({lsu_cpx_pkt_ld_err[1:0],bld_cnt_max_m}),
.q ({cpx_ld_err_m[1:0],bld_cnt_max_g}),
.clk (clk),
.se (se), .si (), .so ()
);
wire [1:0] bld_err ;
wire [1:0] bld_err_din ;
wire bld_rst ;
// Accummulate errors.
assign bld_err_din[1:0] = cpx_ld_err_m[1:0] | bld_err[1:0] ;
assign bld_rst = reset | lsu_bld_reset ;
dffre_s #(2) blderr_ff (
.din (bld_err_din[1:0]),
.q (bld_err[1:0]),
.clk (clk),
.en (lsu_bld_helper_cmplt_m), .rst (bld_rst),
.se (se), .si (), .so ()
);
wire bld_helper_cmplt_g ;
dff_s bldh_stgg (
.din (lsu_bld_helper_cmplt_m),
.q (bld_helper_cmplt_g),
.clk (clk),
.se (se), .si (), .so ()
);
wire bld_unc_err_pend_g, bld_unc_err_pend_w2 ;
assign bld_unc_err_pend_g = bld_err[1] & bld_helper_cmplt_g ;
wire bld_corr_err_pend_g, bld_corr_err_pend_w2 ;
// pended unc error gets priority.
assign bld_corr_err_pend_g = bld_err[0] & ~bld_err[1] & bld_helper_cmplt_g ;
wire bld_squash_err_g,bld_squash_err_w2 ;
// bld cnt should be vld till g
assign bld_squash_err_g = bld_helper_cmplt_g & ~bld_cnt_max_g ;
dff_s #(3) bldsq_stgw2 (
.din ({bld_squash_err_g,bld_unc_err_pend_g,bld_corr_err_pend_g}),
.q ({bld_squash_err_w2,bld_unc_err_pend_w2,bld_corr_err_pend_w2}),
.clk (clk),
.se (se), .si (), .so ()
);
//------
wire stb_cam_hit_w2 ;
wire fld_vld_sync_no_camhit,fld_vld_sync_no_camhit_w2 ;
wire fld_vld_async,fld_vld_async_w2 ;
dff_s #(3) stbchit_stg (
.din ({stb_cam_hit,fld_vld_sync_no_camhit,fld_vld_async}),
.q ({stb_cam_hit_w2,fld_vld_sync_no_camhit_w2,fld_vld_async_w2}),
.clk (clk),
.se (se), .si (), .so ()
);
assign fld_vld_sync_no_camhit =
(lsu_ld_hit_wb & ~tte_data_perror_unc_en & fp_ldst_g &
~dctl_flush_pipe_w) ; // l1hit
assign fld_vld_async =
(l2fill_vld_g & l2fill_fpld_g & ~(unc_err_trap_g | bld_unc_err_pend_g)) |
// fill from l2, // bug 3705, 4315(err_trap)
fpld_byp_data_vld ; // bypass data
assign lsu_ffu_ld_vld =
(fld_vld_sync_no_camhit_w2 & ~stb_cam_hit_w2) |
fld_vld_async_w2 ;
/*dff #(1) fldvld_stgw2 (
.din (ffu_ld_vld),
.q (lsu_ffu_ld_vld),
.clk (clk),
.se (1'b0), .si (), .so ()
); */
dff_s #(2) dtid_stgm (
.din (lsu_dfill_tid_e[1:0]),
.q (dfq_tid_m[1:0]),
.clk (clk),
.se (se), .si (), .so ()
);
dff_s #(2) dtid_stgg (
.din (dfq_tid_m[1:0]),
.q (dfq_tid_g[1:0]),
.clk (clk),
.se (se), .si (), .so ()
);
// Timing Change - shifting dfill-data sel gen. to m-stage
//assign ldbyp_tid[0] = ld_thrd_byp_sel_g[1] | ld_thrd_byp_sel_g[3] ;
//assign ldbyp_tid[1] = ld_thrd_byp_sel_g[2] | ld_thrd_byp_sel_g[3] ;
wire [3:0] ld_thrd_byp_sel_m ;
assign ldbyp_tid_m[0] = ld_thrd_byp_sel_m[1] | ld_thrd_byp_sel_m[3] ;
assign ldbyp_tid_m[1] = ld_thrd_byp_sel_m[2] | ld_thrd_byp_sel_m[3] ;
/*assign lsu_exu_thr_g[1:0] = ld_inst_vld_unflushed ? thrid_g[1:0] :
l2fill_vld_g ? dfq_tid_g[1:0] : ldbyp_tid[1:0] ; */
assign lsu_exu_thr_m[1:0] = ld_inst_vld_m ? thrid_m[1:0] :
l2fill_vld_m ? dfq_tid_m[1:0] : ldbyp_tid_m[1:0] ;
// What is the policy for load-double/atomics to update cache ?
// cas will not update cache. similary neither will ldstub nor cas.
// BIST will effect dcache only, not tags and vld bits.
// Removed dcache_enable from dc_diagnstc_wr_en !!!
wire l2fill_vld_e ;
wire dcache_alt_src_wr_e ;
assign l2fill_vld_e = lsu_l2fill_vld & ~lsu_cpx_pkt_prefetch2 ;
assign lsu_dcache_wr_vld_e =
(l2fill_vld_e & ~ignore_fill & ~atomic_ld_squash_e & ~ld_sec_active & ~lsu_ncache_ld_e) |
lsu_st_wr_dcache | // st writes from stb
dcache_alt_src_wr_e ;
assign dcache_alt_src_wr_e =
(lsu_diagnstc_wr_src_sel_e & dc_diagnstc_wr_en)
| lsu_bist_wvld_e // bist engine writes to cache
| dcache_iob_wr_e ; // iobridge request write to dcache
//d$ valid bit
wire dv_diagnstic_wr;
assign dv_diagnstic_wr = (lsu_diagnstc_wr_src_sel_e & dtagv_diagnstc_wr_en & lsu_diagnstc_wr_data_b0) ;
wire dva_din_e;
wire ld_fill_e;
assign ld_fill_e= (l2fill_vld_e & ~atomic_ld_squash_e & ~ld_sec_active & ~lsu_ncache_ld_e) ; //ld-fill
//######################################
//snp => dva_din = 0
//ld fill => dva_din = 1
//diag wrt => dva_din = wrt_value
//######################################
assign dva_din_e = ld_fill_e | //ld-fill
dv_diagnstic_wr; // diagnostic write valid bit
// iob rd dominates
wire lsu_dc_alt_rd_vld_e;
assign lsu_dc_alt_rd_vld_e = dcache_iob_rd_e | lsu_bist_rvld_e ;
//?? default when no ld in pipe
assign dcache_alt_mx_sel_e =
//lsu_dcache_wr_vld_e | : Timing
dcache_alt_src_wr_e | // rm st updates/fill - ~ld_inst_vld_e.
lsu_dcache_wr_vld_e |
lsu_dc_alt_rd_vld_e | ~ld_inst_vld_e;
assign dcache_alt_mx_sel_e_bf = dcache_alt_mx_sel_e;
wire dcache_rvld_e_tmp, dcache_rvld_e_minbf;
assign dcache_rvld_e_tmp = ld_inst_vld_e | lsu_dc_alt_rd_vld_e ;
bw_u1_minbuf_5x UZfix_dcache_rvld_e_minbf (.a(dcache_rvld_e_tmp), .z(dcache_rvld_e_minbf));
assign dcache_rvld_e = dcache_rvld_e_minbf;
wire lsu_dtag_wr_vld_e_tmp;
assign lsu_dtag_wr_vld_e_tmp =
ld_fill_e & ~ignore_fill | //ld fill //bug3601, 3676
(lsu_diagnstc_wr_src_sel_e & dtagv_diagnstc_wr_en) ; // dtag/vld diagnostic wr
bw_u1_buf_30x UZsize_lsu_dtag_wrreq_x ( .a(lsu_dtag_wr_vld_e_tmp), .z(lsu_dtag_wrreq_x_e) );
bw_u1_buf_30x UZsize_lsu_dtag_index_sel_x ( .a(lsu_dtag_wr_vld_e_tmp), .z(lsu_dtag_index_sel_x_e) );
assign lsu_dtagv_wr_vld_e =
lsu_dtag_wr_vld_e_tmp | // fill
dva_svld_e | // snp
lsu_bist_wvld_e ; // bist clears dva by default
// mem cell change for dva
wire [15:0] dva_fill_bit_wr_en_e;
assign dva_fill_bit_wr_en_e[15] = dcache_fill_addr_e[5] & dcache_fill_addr_e[4] & lsu_dcache_fill_way_e[3];
assign dva_fill_bit_wr_en_e[14] = dcache_fill_addr_e[5] & dcache_fill_addr_e[4] & lsu_dcache_fill_way_e[2];
assign dva_fill_bit_wr_en_e[13] = dcache_fill_addr_e[5] & dcache_fill_addr_e[4] & lsu_dcache_fill_way_e[1];
assign dva_fill_bit_wr_en_e[12] = dcache_fill_addr_e[5] & dcache_fill_addr_e[4] & lsu_dcache_fill_way_e[0];
assign dva_fill_bit_wr_en_e[11] = dcache_fill_addr_e[5] & ~dcache_fill_addr_e[4] & lsu_dcache_fill_way_e[3];
assign dva_fill_bit_wr_en_e[10] = dcache_fill_addr_e[5] & ~dcache_fill_addr_e[4] & lsu_dcache_fill_way_e[2];
assign dva_fill_bit_wr_en_e[09] = dcache_fill_addr_e[5] & ~dcache_fill_addr_e[4] & lsu_dcache_fill_way_e[1];
assign dva_fill_bit_wr_en_e[08] = dcache_fill_addr_e[5] & ~dcache_fill_addr_e[4] & lsu_dcache_fill_way_e[0];
assign dva_fill_bit_wr_en_e[07] = ~dcache_fill_addr_e[5] & dcache_fill_addr_e[4] & lsu_dcache_fill_way_e[3];
assign dva_fill_bit_wr_en_e[06] = ~dcache_fill_addr_e[5] & dcache_fill_addr_e[4] & lsu_dcache_fill_way_e[2];
assign dva_fill_bit_wr_en_e[05] = ~dcache_fill_addr_e[5] & dcache_fill_addr_e[4] & lsu_dcache_fill_way_e[1];
assign dva_fill_bit_wr_en_e[04] = ~dcache_fill_addr_e[5] & dcache_fill_addr_e[4] & lsu_dcache_fill_way_e[0];
assign dva_fill_bit_wr_en_e[03] = ~dcache_fill_addr_e[5] & ~dcache_fill_addr_e[4] & lsu_dcache_fill_way_e[3];
assign dva_fill_bit_wr_en_e[02] = ~dcache_fill_addr_e[5] & ~dcache_fill_addr_e[4] & lsu_dcache_fill_way_e[2];
assign dva_fill_bit_wr_en_e[01] = ~dcache_fill_addr_e[5] & ~dcache_fill_addr_e[4] & lsu_dcache_fill_way_e[1];
assign dva_fill_bit_wr_en_e[00] = ~dcache_fill_addr_e[5] & ~dcache_fill_addr_e[4] & lsu_dcache_fill_way_e[0];
wire [15:0] dva_bit_wr_en_e;
assign dva_bit_wr_en_e[15:0] = dva_svld_e ? dva_snp_bit_wr_en_e[15:0] : dva_fill_bit_wr_en_e;
wire [4:0] dva_snp_addr_e_bf;
bw_u1_buf_5x UZsize_dva_snp_addr_e_bf_b4 (.a(dva_snp_addr_e[4]), .z(dva_snp_addr_e_bf[4]));
bw_u1_buf_5x UZsize_dva_snp_addr_e_bf_b3 (.a(dva_snp_addr_e[3]), .z(dva_snp_addr_e_bf[3]));
bw_u1_buf_5x UZsize_dva_snp_addr_e_bf_b2 (.a(dva_snp_addr_e[2]), .z(dva_snp_addr_e_bf[2]));
bw_u1_buf_5x UZsize_dva_snp_addr_e_bf_b1 (.a(dva_snp_addr_e[1]), .z(dva_snp_addr_e_bf[1]));
bw_u1_buf_5x UZsize_dva_snp_addr_e_bf_b0 (.a(dva_snp_addr_e[0]), .z(dva_snp_addr_e_bf[0]));
assign dva_wr_adr_e[10:6] = dva_svld_e ? dva_snp_addr_e_bf[4:0] : dcache_fill_addr_e[10:6];
// should ldxa_data_vld be included ?
assign dfill_thread0 = ~lsu_dfill_tid_e[1] & ~lsu_dfill_tid_e[0] ;
assign dfill_thread1 = ~lsu_dfill_tid_e[1] & lsu_dfill_tid_e[0] ;
assign dfill_thread2 = lsu_dfill_tid_e[1] & ~lsu_dfill_tid_e[0] ;
assign dfill_thread3 = lsu_dfill_tid_e[1] & lsu_dfill_tid_e[0] ;
assign l2fill_fpld_e = lsu_l2fill_fpld_e ;
//=========================================================================================
// LD/ST COMPLETE SIGNAL
//=========================================================================================
// Prefetch
wire pref_tlbmiss_g ;
assign pref_tlbmiss_g =
pref_inst_g &
(~tlb_cam_hit_g | (tlb_cam_hit_g & tlb_pgnum[39])) // nop on tlbmiss or io access
& lsu_inst_vld_w & ~dctl_flush_pipe_w ; // Bug 4318 bug6406/eco6619
//assign pref_tlbmiss_g = pref_inst_g & lsu_inst_vld_w & ~tlb_cam_hit_g ;
wire [3:0] pref_tlbmiss_cmplt,pref_tlbmiss_cmplt_d1,pref_tlbmiss_cmplt_d2 ;
assign pref_tlbmiss_cmplt[0] = pref_tlbmiss_g & thread0_g ;
assign pref_tlbmiss_cmplt[1] = pref_tlbmiss_g & thread1_g ;
assign pref_tlbmiss_cmplt[2] = pref_tlbmiss_g & thread2_g ;
assign pref_tlbmiss_cmplt[3] = pref_tlbmiss_g & thread3_g ;
dff_s #(4) pfcmpl_stgd1 (
.din (pref_tlbmiss_cmplt[3:0]),
.q (pref_tlbmiss_cmplt_d1[3:0]),
.clk (clk),
.se (se), .si (), .so ()
);
dff_s #(4) pfcmpl_stgd2 (
.din (pref_tlbmiss_cmplt_d1[3:0]),
.q (pref_tlbmiss_cmplt_d2[3:0]),
.clk (clk),
.se (se), .si (), .so ()
);
// *** add diagnstc rd and prefetch(tlb-miss) signals. ***
// *** add ifu asi ack.
// This equation is critical and needs to be optimized.
wire [3:0] lsu_pcx_pref_issue;
wire diag_wr_cmplt0,diag_wr_cmplt1,diag_wr_cmplt2,diag_wr_cmplt3;
wire ldst_cmplt_late_0, ldst_cmplt_late_1 ;
wire ldst_cmplt_late_2, ldst_cmplt_late_3 ;
wire ldst_cmplt_late_0_d1, ldst_cmplt_late_1_d1 ;
wire ldst_cmplt_late_2_d1, ldst_cmplt_late_3_d1 ;
assign ignore_fill = lmq_ldd_vld & ~ldd_in_dfq_out;
assign lsu_ifu_ldst_cmplt[0] =
// * can be early or
((stxa_internal_d2 & thread0_w3) | stxa_stall_wr_cmplt0_d1) |
// * late signal and critical.
// Can this be snapped earlier ?
//(((l2fill_vld_e & ~atomic_ld_squash_e & ~ignore_fill)) //Bug 3624
(((l2fill_vld_e & ~ignore_fill)) // 1st fill for ldd.
& ~l2fill_fpld_e & ~lsu_cpx_pkt_atm_st_cmplt &
~(lsu_cpx_pkt_ld_err[1] & lsu_nceen_d1[0]) & dfill_thread0) |
intld_byp_cmplt[0] |
// * early-or signals
ldst_cmplt_late_0_d1 ;
wire atm_st_cmplt0 ;
assign atm_st_cmplt0 = lsu_atm_st_cmplt_e & dfill_thread0 ;
assign ldst_cmplt_late_0 =
(atm_st_cmplt0 & ~pend_atm_ld_ue[0]) | // Bug 3624,4048
bsync0_reset |
lsu_intrpt_cmplt[0] |
diag_wr_cmplt0 |
// dc0_diagnstc_rd_w2 |
ldxa_illgl_va_cmplt_d1[0] |
pref_tlbmiss_cmplt_d2[0] |
lsu_pcx_pref_issue[0];
assign lsu_ifu_ldst_cmplt[1] =
((stxa_internal_d2 & thread1_w3) | stxa_stall_wr_cmplt1_d1) |
(((l2fill_vld_e & ~ignore_fill)) // // 1st fill for ldd
& ~l2fill_fpld_e & ~lsu_cpx_pkt_atm_st_cmplt &
~(lsu_cpx_pkt_ld_err[1] & lsu_nceen_d1[1]) & dfill_thread1) |
intld_byp_cmplt[1] |
ldst_cmplt_late_1_d1 ;
wire atm_st_cmplt1 ;
assign atm_st_cmplt1 = lsu_atm_st_cmplt_e & dfill_thread1 ;
assign ldst_cmplt_late_1 =
(atm_st_cmplt1 & ~pend_atm_ld_ue[1]) | // Bug 3624,4048
bsync1_reset |
lsu_intrpt_cmplt[1] |
diag_wr_cmplt1 |
// dc1_diagnstc_rd_w2 |
ldxa_illgl_va_cmplt_d1[1] |
pref_tlbmiss_cmplt_d2[1] |
lsu_pcx_pref_issue[1];
assign lsu_ifu_ldst_cmplt[2] =
((stxa_internal_d2 & thread2_w3) | stxa_stall_wr_cmplt2_d1) |
(((l2fill_vld_e & ~ignore_fill)) // 1st fill for ldd.
& ~l2fill_fpld_e & ~lsu_cpx_pkt_atm_st_cmplt &
~(lsu_cpx_pkt_ld_err[1] & lsu_nceen_d1[2]) & dfill_thread2) |
intld_byp_cmplt[2] |
ldst_cmplt_late_2_d1 ;
wire atm_st_cmplt2 ;
assign atm_st_cmplt2 = lsu_atm_st_cmplt_e & dfill_thread2 ;
assign ldst_cmplt_late_2 =
(atm_st_cmplt2 & ~pend_atm_ld_ue[2]) | // Bug 3624,4048
bsync2_reset |
lsu_intrpt_cmplt[2] |
diag_wr_cmplt2 |
// dc2_diagnstc_rd_w2 |
ldxa_illgl_va_cmplt_d1[2] |
pref_tlbmiss_cmplt_d2[2] |
lsu_pcx_pref_issue[2];
assign lsu_ifu_ldst_cmplt[3] =
((stxa_internal_d2 & thread3_w3) | stxa_stall_wr_cmplt3_d1) |
//(((l2fill_vld_e & atomic_st_cmplt) |
(((l2fill_vld_e & ~ignore_fill)) // 1st fill for ldd.
& ~l2fill_fpld_e & ~lsu_cpx_pkt_atm_st_cmplt &
~(lsu_cpx_pkt_ld_err[1] & lsu_nceen_d1[3]) & dfill_thread3) |
intld_byp_cmplt[3] |
ldst_cmplt_late_3_d1 ;
wire atm_st_cmplt3 ;
assign atm_st_cmplt3 = lsu_atm_st_cmplt_e & dfill_thread3 ;
assign ldst_cmplt_late_3 =
(atm_st_cmplt3 & ~pend_atm_ld_ue[3]) | // Bug 3624,4048
bsync3_reset |
lsu_intrpt_cmplt[3] |
diag_wr_cmplt3 |
// dc3_diagnstc_rd_w2 |
ldxa_illgl_va_cmplt_d1[3] |
pref_tlbmiss_cmplt_d2[3] |
lsu_pcx_pref_issue[3];
dff_s #(4) ldstcmplt_d1 (
.din ({ldst_cmplt_late_3,ldst_cmplt_late_2,ldst_cmplt_late_1,ldst_cmplt_late_0}),
.q ({ldst_cmplt_late_3_d1,ldst_cmplt_late_2_d1,
ldst_cmplt_late_1_d1,ldst_cmplt_late_0_d1}),
.clk (clk),
.se (se), .si (), .so ()
);
//=========================================================================================
// LD/ST MISS SIGNAL - IFU
//=========================================================================================
// Switchout of internal asi ld
// Do not switchout for tag-target,
assign ldxa_swo_annul =
(lsu_dctl_asi_state_m[7:4] == 4'h3) | // ldxa to 0x3X does not swo
(((lsu_dctl_asi_state_m[7:0] == 8'h58) & // tag-target,tag-access,sfsr,sfar
~((lsu_ldst_va_b7_b0_m[7:0] == 8'h38) | (lsu_ldst_va_b7_b0_m[7:0] == 8'h80))) | // wtcpt/pid
(lsu_dctl_asi_state_m[7:0] == 8'h50)) |
mmu_rd_only_asi_m ;
wire ldxa_internal_swo_m,ldxa_internal_swo_g ;
assign ldxa_internal_swo_m = lda_internal_m & ~ldxa_swo_annul ;
// This represents *all* ld asi.
wire asi_internal_ld_m,asi_internal_ld_g ;
assign asi_internal_ld_m =
asi_internal_m & ld_inst_vld_m & lsu_alt_space_m ;
dff_s #(2) ldaswo_stgg (
.din ({ldxa_internal_swo_m,asi_internal_ld_m}),
.q ({ldxa_internal_swo_g,asi_internal_ld_g}),
.clk (clk),
.se (se), .si (), .so ()
);
wire common_ldst_miss_w ;
assign common_ldst_miss_w =
(~(cache_hit & (tlb_cam_hit_g | lsu_dtlb_bypass_g)) | // include miss in tlb;bypass
~dcache_enable_g | //
//endian_mispred_g | // endian mispredict
ldd_force_l2access_g | // ifu to incorporate directly
ncache_asild_rq_g ) & // bypass asi
~asi_internal_ld_g ;
assign lsu_ifu_ldst_miss_w =
(common_ldst_miss_w | // common between ifu and exu.
// MMU_ASI : ifu must switch out early only for stores.
ldxa_internal_swo_g)
// ldxa_internal | // ifu incorporates directly
// atomic_g | // ifu incorporates directly
// ld_stb_hit_g | // late
// stb_cam_hit) // ** rm once ifu uses late signal. **
// dcache_rd_parity_error | // late
// dtag_perror_g) & | // late
& (lsu_inst_vld_w & ld_inst_vld_unflushed) ; // flush uptil m accounted for.
// & ld_inst_vld_g ; // assume flush=1 clears ldst_miss=1
// ~tte_data_perror_unc & // in flush
// (ld_inst_vld_g & (~lsu_alt_space_g | (lsu_alt_space_g & recognized_asi_g))) |
// ncache_asild_rq_g ; // asi ld requires bypass
//timing fix
wire lsu_ifu_dc_parity_error_w;
assign lsu_ifu_dc_parity_error_w =
(
lsu_dcache_data_perror_g | // bug 4267
lsu_dcache_tag_perror_g |
endian_mispred_g | // endian mispredict ; mv'ed from ldst_miss
tte_data_perror_unc_en) ;
/*
wire lsu_ld_inst_vld_flush_w, lsu_ld_inst_vld_flush_w2;
assign lsu_ld_inst_vld_flush_w = lsu_inst_vld_w & ld_inst_vld_unflushed & ~dctl_flush_pipe_w ;
dff_s #(1) lsu_ld_inst_vld_flush_stgw2 (
.din (lsu_ld_inst_vld_flush_w),
.q (lsu_ld_inst_vld_flush_w2),
.clk (clk),
.se (se), .si (), .so ()
);
*/
wire lsu_ifu_dc_parity_error_w2_q;
dff_s #(1) lsu_ifu_dc_parity_error_stgw2 (
.din (lsu_ifu_dc_parity_error_w),
.q (lsu_ifu_dc_parity_error_w2_q),
.clk (clk),
.se (se), .si (), .so ()
);
assign lsu_ifu_dc_parity_error_w2 = (lsu_ifu_dc_parity_error_w2_q | stb_cam_hit_w2) & ld_inst_vld_w2;
//=========================================================================================
// LD/ST MISS SIGNAL - EXU
//=========================================================================================
// for a diagnstc access to the cache, the if it misses in the cache, then
// ldst_miss is asserted, preventing a write into the cache, but code is
// allowed to continue executing.
wire exu_ldst_miss_g_no_stb_cam_hit ;
assign exu_ldst_miss_g_no_stb_cam_hit =
(common_ldst_miss_w |
ldxa_internal_swo_g |
endian_mispred_g |
atomic_g |
lsu_dcache_data_perror_g |
lsu_dcache_tag_perror_g |
tte_data_perror_unc_en |
pref_inst_g) & ld_inst_vld_unflushed & lsu_inst_vld_w ; // flush qual done in exu
wire ld_inst_vld_no_flush_w, ld_inst_vld_no_flush_w2;
assign ld_inst_vld_no_flush_w = ld_inst_vld_unflushed & lsu_inst_vld_w;
dff_s #(1) ld_inst_vld_no_flush_stgw2 (
.din (ld_inst_vld_no_flush_w),
.q (ld_inst_vld_no_flush_w2),
.clk (clk),
.se (se), .si (), .so ()
);
wire lsu_exu_ldst_miss_w2_tmp;
dff_s #(1) exuldstmiss_stgw2 (
.din (exu_ldst_miss_g_no_stb_cam_hit),
.q (lsu_exu_ldst_miss_w2_tmp),
.clk (clk),
.se (se), .si (), .so ()
);
assign lsu_exu_ldst_miss_w2 = (lsu_exu_ldst_miss_w2_tmp | stb_cam_hit_w2) & ld_inst_vld_no_flush_w2;
wire lsu_ldst_miss_w2;
assign lsu_ldst_miss_w2 = lsu_exu_ldst_miss_w2 ;
//=========================================================================================
// RMO Store control data
//=========================================================================================
assign lsu_st_rmo_m = (st_inst_vld_m & (binit_quad_asi_m | blk_asi_m) & lsu_alt_space_m) | blkst_m ;
assign lsu_bst_in_pipe_m = (st_inst_vld_m & blk_asi_m & lsu_alt_space_m) ;
//=========================================================================================
// ASI BUS
//=========================================================================================
// *** This logic is now used by all long-latency asi operations on chip. ***
// Start with SDATA Reg for Streaming
wire strm_asi, strm_asi_m ;
assign strm_asi_m = (lsu_dctl_asi_state_m[7:0]==8'h40) ;
dff_s strm_stgg (
.din (strm_asi_m),
.q (strm_asi),
.clk (clk),
.se (se), .si (), .so ()
);
assign stxa_stall_asi_g =
strm_asi & ((ldst_va_g[7:0] == 8'h80)) ; // ma ctl
/*strm_asi & ( (ldst_va_g[7:0] == 8'h18) | // streaming stxa to sdata
(ldst_va_g[7:0] == 8'h00) | // stream ctl
(ldst_va_g[7:0] == 8'h08) ) ; // ma ctl */
wire dtlb_wr_cmplt0, dtlb_wr_cmplt1;
wire dtlb_wr_cmplt2, dtlb_wr_cmplt3;
assign dtlb_wr_cmplt0 = demap_thread0 & lsu_dtlb_wr_vld_e ;
assign dtlb_wr_cmplt1 = demap_thread1 & lsu_dtlb_wr_vld_e ;
assign dtlb_wr_cmplt2 = demap_thread2 & lsu_dtlb_wr_vld_e ;
assign dtlb_wr_cmplt3 = demap_thread3 & lsu_dtlb_wr_vld_e ;
dff_s dtlbw_stgd1 (
.din (lsu_dtlb_wr_vld_e),
.q (dtlb_wr_init_d1),
.clk (clk),
.se (se), .si (), .so ()
);
dff_s dtlbw_stgd2 (
.din (dtlb_wr_init_d1),
.q (dtlb_wr_init_d2),
.clk (clk),
.se (se), .si (), .so ()
);
dff_s dtlbw_stgd3 (
.din (dtlb_wr_init_d2),
.q (dtlb_wr_init_d3),
.clk (clk),
.se (se), .si (), .so ()
);
wire dtlb_wr_init_d4 ;
dff_s dtlbw_stgd4 (
.din (dtlb_wr_init_d3),
.q (dtlb_wr_init_d4),
.clk (clk),
.se (se), .si (), .so ()
);
wire tlb_access_sel_thrd3_d1,tlb_access_sel_thrd2_d1;
wire tlb_access_sel_thrd1_d1,tlb_access_sel_thrd0_d1 ;
wire ifu_asi_store_cmplt_en, ifu_asi_store_cmplt_en_d1 ;
assign stxa_stall_wr_cmplt0 = (spu_lsu_stxa_ack & spu_stxa_thread0) |
(tlu_stxa_thread0_w2 & tlu_lsu_stxa_ack & ~dtlb_wr_init_d4) |
(ifu_asi_store_cmplt_en_d1 & tlb_access_sel_thrd0_d1) |
dtlb_wr_cmplt0 ;
assign stxa_stall_wr_cmplt1 = (spu_lsu_stxa_ack & spu_stxa_thread1) |
(tlu_stxa_thread1_w2 & tlu_lsu_stxa_ack & ~dtlb_wr_init_d4) |
(ifu_asi_store_cmplt_en_d1 & tlb_access_sel_thrd1_d1) |
dtlb_wr_cmplt1 ;
assign stxa_stall_wr_cmplt2 = (spu_lsu_stxa_ack & spu_stxa_thread2) |
(tlu_stxa_thread2_w2 & tlu_lsu_stxa_ack & ~dtlb_wr_init_d4) |
(ifu_asi_store_cmplt_en_d1 & tlb_access_sel_thrd2_d1) |
dtlb_wr_cmplt2 ;
assign stxa_stall_wr_cmplt3 = (spu_lsu_stxa_ack & spu_stxa_thread3) |
(tlu_stxa_thread3_w2 & tlu_lsu_stxa_ack & ~dtlb_wr_init_d4) |
(ifu_asi_store_cmplt_en_d1 & tlb_access_sel_thrd3_d1) |
dtlb_wr_cmplt3 ;
dff_s #(4) stxastall_stgd1 (
.din ({stxa_stall_wr_cmplt3,stxa_stall_wr_cmplt2,
stxa_stall_wr_cmplt1,stxa_stall_wr_cmplt0}),
.q ({stxa_stall_wr_cmplt3_d1,stxa_stall_wr_cmplt2_d1,
stxa_stall_wr_cmplt1_d1,stxa_stall_wr_cmplt0_d1}),
.clk (clk),
.se (se), .si (), .so ()
);
// enable speculates on inst not being flushed
// Only dside diagnostic writes will be logged for long-latency action. dside diagnostic
// reads are aligned to pipe.
wire wr_dc_diag_asi_e, wr_dtagv_diag_asi_e ;
assign wr_dc_diag_asi_e = dc_diagnstc_asi_e & st_inst_vld_e ;
assign wr_dtagv_diag_asi_e = dtagv_diagnstc_asi_e & st_inst_vld_e ;
assign tlb_access_en0_e =
(tlb_lng_ltncy_asi_e | wr_dc_diag_asi_e | wr_dtagv_diag_asi_e | ifu_nontlb_asi_e)
& thread0_e & alt_space_e ;
assign tlb_access_en1_e =
(tlb_lng_ltncy_asi_e | wr_dc_diag_asi_e | wr_dtagv_diag_asi_e | ifu_nontlb_asi_e)
& thread1_e & alt_space_e ;
assign tlb_access_en2_e =
(tlb_lng_ltncy_asi_e | wr_dc_diag_asi_e | wr_dtagv_diag_asi_e | ifu_nontlb_asi_e)
& thread2_e & alt_space_e ;
assign tlb_access_en3_e =
(tlb_lng_ltncy_asi_e | wr_dc_diag_asi_e | wr_dtagv_diag_asi_e | ifu_nontlb_asi_e)
& thread3_e & alt_space_e ;
dff_s #(4) tlbac_stgm (
.din ({tlb_access_en0_e,tlb_access_en1_e,tlb_access_en2_e,tlb_access_en3_e}),
.q ({tlb_access_en0_tmp,tlb_access_en1_tmp,tlb_access_en2_tmp,tlb_access_en3_tmp}),
.clk (clk),
.se (se), .si (), .so ()
);
wire ldst_vld_m = ld_inst_vld_m | st_inst_vld_m ;
assign tlb_access_en0_m = tlb_access_en0_tmp & ldst_vld_m ;
assign tlb_access_en1_m = tlb_access_en1_tmp & ldst_vld_m ;
assign tlb_access_en2_m = tlb_access_en2_tmp & ldst_vld_m ;
assign tlb_access_en3_m = tlb_access_en3_tmp & ldst_vld_m ;
dff_s #(4) tlbac_stgw (
.din ({tlb_access_en0_m,tlb_access_en1_m,tlb_access_en2_m,tlb_access_en3_m}),
.q ({tlb_access_en0_unflushed,tlb_access_en1_unflushed,tlb_access_en2_unflushed,tlb_access_en3_unflushed}),
.clk (clk),
.se (se), .si (), .so ()
);
// Flush ld/st with as=42 belonging to lsu. bistctl and ldiag
assign tlb_access_en0_g = tlb_access_en0_unflushed & lsu_inst_vld_w & ~(dctl_early_flush_w | ifu_asi42_flush_g) ;
//assign tlb_access_en0_g = tlb_access_en0_unflushed & lsu_inst_vld_w & ~(dctl_flush_pipe_w | ifu_asi42_flush_g) ;
assign tlb_access_en1_g = tlb_access_en1_unflushed & lsu_inst_vld_w & ~(dctl_early_flush_w | ifu_asi42_flush_g) ;
assign tlb_access_en2_g = tlb_access_en2_unflushed & lsu_inst_vld_w & ~(dctl_early_flush_w | ifu_asi42_flush_g) ;
assign tlb_access_en3_g = tlb_access_en3_unflushed & lsu_inst_vld_w & ~(dctl_early_flush_w | ifu_asi42_flush_g) ;
assign diag_wr_cmplt0 = lsu_diagnstc_wr_src_sel_e & tlb_access_sel_thrd0_d1 ;
assign diag_wr_cmplt1 = lsu_diagnstc_wr_src_sel_e & tlb_access_sel_thrd1_d1 ;
assign diag_wr_cmplt2 = lsu_diagnstc_wr_src_sel_e & tlb_access_sel_thrd2_d1 ;
assign diag_wr_cmplt3 = lsu_diagnstc_wr_src_sel_e & tlb_access_sel_thrd3_d1 ;
wire ifu_tlb_rd_cmplt0,ifu_tlb_rd_cmplt1,ifu_tlb_rd_cmplt2,ifu_tlb_rd_cmplt3 ;
wire st_sqsh_m, ifu_asi_ack_d1 ;
assign ifu_tlb_rd_cmplt0 = (ifu_ldxa_thread0_w2 & ifu_lsu_ldxa_data_vld_w2 & ~ifu_nontlb0_asi) ;
assign ifu_tlb_rd_cmplt1 = (ifu_ldxa_thread1_w2 & ifu_lsu_ldxa_data_vld_w2 & ~ifu_nontlb1_asi) ;
assign ifu_tlb_rd_cmplt2 = (ifu_ldxa_thread2_w2 & ifu_lsu_ldxa_data_vld_w2 & ~ifu_nontlb2_asi) ;
assign ifu_tlb_rd_cmplt3 = (ifu_ldxa_thread3_w2 & ifu_lsu_ldxa_data_vld_w2 & ~ifu_nontlb3_asi) ;
// stxa ack will share tid with ldxa
// This should be qualified with inst_vld_w also !!!
// ldxa_data_vld needs to be removed once full interface in !!!
assign tlb_access_rst0 = reset |
(tlu_ldxa_thread0_w2 & tlu_lsu_ldxa_async_data_vld) |
(tlu_stxa_thread0_w2 & tlu_lsu_stxa_ack) |
(ifu_tlb_rd_cmplt0) |
(ifu_stxa_thread0_w2 & ifu_lsu_asi_ack) |
diag_wr_cmplt0 ;
assign tlb_access_rst1 = reset |
(tlu_ldxa_thread1_w2 & tlu_lsu_ldxa_async_data_vld) |
(tlu_stxa_thread1_w2 & tlu_lsu_stxa_ack) |
(ifu_tlb_rd_cmplt1) |
(ifu_stxa_thread1_w2 & ifu_lsu_asi_ack) |
diag_wr_cmplt1 ;
assign tlb_access_rst2 = reset |
(tlu_ldxa_thread2_w2 & tlu_lsu_ldxa_async_data_vld) |
(tlu_stxa_thread2_w2 & tlu_lsu_stxa_ack) |
(ifu_tlb_rd_cmplt2) |
(ifu_stxa_thread2_w2 & ifu_lsu_asi_ack) |
diag_wr_cmplt2 ;
assign tlb_access_rst3 = reset |
(tlu_ldxa_thread3_w2 & tlu_lsu_ldxa_async_data_vld) |
(tlu_stxa_thread3_w2 & tlu_lsu_stxa_ack) |
(ifu_tlb_rd_cmplt3) |
(ifu_stxa_thread3_w2 & ifu_lsu_asi_ack) |
diag_wr_cmplt3 ;
// tlb_ld_inst* and tlb_st_inst* are generically used to indicate a read or write.
// Thread 0
dffre_s #(2) asiv_thrd0 (
.din ({ld_inst_vld_g,st_inst_vld_g}),
.q ({tlb_ld_inst0,tlb_st_inst0}),
.rst (tlb_access_rst0), .en (tlb_access_en0_g),
.clk (clk),
.se (se), .si (), .so ()
);
dffe_s #(3) asiv_thrd0_sec (
.din ({dc_diagnstc_asi_g,dtagv_diagnstc_asi_g,ifu_nontlb_asi_g}),
.q ({dc0_diagnstc_asi,dtagv0_diagnstc_asi,ifu_nontlb0_asi}),
.en (tlb_access_en0_g),
.clk (clk),
.se (se), .si (), .so ()
);
assign nontlb_asi0 = dc0_diagnstc_asi | dtagv0_diagnstc_asi | ifu_nontlb0_asi ;
// Thread 1
dffre_s #(2) asiv_thrd1 (
.din ({ld_inst_vld_g,st_inst_vld_g}),
.q ({tlb_ld_inst1,tlb_st_inst1}),
.rst (tlb_access_rst1), .en (tlb_access_en1_g),
.clk (clk),
.se (se), .si (), .so ()
);
dffe_s #(3) asiv_thrd1_sec (
.din ({dc_diagnstc_asi_g,dtagv_diagnstc_asi_g,ifu_nontlb_asi_g}),
.q ({dc1_diagnstc_asi,dtagv1_diagnstc_asi,ifu_nontlb1_asi}),
.en (tlb_access_en1_g),
.clk (clk),
.se (se), .si (), .so ()
);
assign nontlb_asi1 = dc1_diagnstc_asi | dtagv1_diagnstc_asi | ifu_nontlb1_asi ;
// Thread 2
dffre_s #(2) asiv_thrd2 (
.din ({ld_inst_vld_g,st_inst_vld_g}),
.q ({tlb_ld_inst2,tlb_st_inst2}),
.rst (tlb_access_rst2), .en (tlb_access_en2_g),
.clk (clk),
.se (se), .si (), .so ()
);
dffe_s #(3) asiv_thrd2_sec (
.din ({dc_diagnstc_asi_g,dtagv_diagnstc_asi_g,ifu_nontlb_asi_g}),
.q ({dc2_diagnstc_asi,dtagv2_diagnstc_asi,ifu_nontlb2_asi}),
.en (tlb_access_en2_g),
.clk (clk),
.se (se), .si (), .so ()
);
assign nontlb_asi2 = dc2_diagnstc_asi | dtagv2_diagnstc_asi | ifu_nontlb2_asi ;
// Thread 3
dffre_s #(2) asiv_thrd3 (
.din ({ld_inst_vld_g,st_inst_vld_g}),
.q ({tlb_ld_inst3,tlb_st_inst3}),
.rst (tlb_access_rst3), .en (tlb_access_en3_g),
.clk (clk),
.se (se), .si (), .so ()
);
dffe_s #(3) asiv_thrd3_sec (
.din ({dc_diagnstc_asi_g,dtagv_diagnstc_asi_g,ifu_nontlb_asi_g}),
.q ({dc3_diagnstc_asi,dtagv3_diagnstc_asi,ifu_nontlb3_asi}),
.en (tlb_access_en3_g),
.clk (clk),
.se (se), .si (), .so ()
);
assign nontlb_asi3 = dc3_diagnstc_asi | dtagv3_diagnstc_asi | ifu_nontlb3_asi ;
//---
// Prioritization of threaded events from asi queue.
// - It is not expected that a significant bias will exist in selecting
// 1 of 4 possible events from the asi queue because of the low frequency
// of such events. However, to bulletproof we will prioritize the events
// in a fifo manner.
//---
// Control :
wire [3:0] fifo_top ;
wire asi_fifo0_vld,asi_fifo1_vld,asi_fifo2_vld,asi_fifo3_vld;
assign fifo_top[0] = ~asi_fifo0_vld ;
assign fifo_top[1] = ~asi_fifo1_vld & asi_fifo0_vld ;
assign fifo_top[2] = ~asi_fifo2_vld & asi_fifo1_vld & asi_fifo0_vld ;
assign fifo_top[3] = ~asi_fifo3_vld & asi_fifo2_vld & asi_fifo1_vld & asi_fifo0_vld ;
// Check for timing on flush.
// Do not confuse thread# with fifo entry#.
wire fifo_wr, fifo_shift ;
assign fifo_wr =
tlb_access_en0_g | tlb_access_en1_g | tlb_access_en2_g | tlb_access_en3_g ;
assign fifo_shift =
tlb_access_rst0 | tlb_access_rst1 | tlb_access_rst2 | tlb_access_rst3 ;
wire [3:0] fifo_top_wr ;
assign fifo_top_wr[0] = fifo_top[0] & fifo_wr ;
assign fifo_top_wr[1] = fifo_top[1] & fifo_wr ;
assign fifo_top_wr[2] = fifo_top[2] & fifo_wr ;
assign fifo_top_wr[3] = fifo_top[3] & fifo_wr ;
// Matrix for Data Selection.
// shift | wr | din for entry
// 0 0 na
// 0 1 thrid_g
// 1 0 q
// 1 1 q if top is not 1 above
// 1 1 thrid_g if top is 1 above
// shift writeable entry into correct position, if exists.
wire asi_fifo0_sel,asi_fifo1_sel,asi_fifo2_sel ;
assign asi_fifo0_sel = fifo_shift ? fifo_top_wr[1] : fifo_top_wr[0] ;
assign asi_fifo1_sel = fifo_shift ? fifo_top_wr[2] : fifo_top_wr[1] ;
assign asi_fifo2_sel = fifo_shift ? fifo_top_wr[3] : fifo_top_wr[2] ;
wire [1:0] asi_fifo3_din,asi_fifo2_din,asi_fifo1_din,asi_fifo0_din ;
wire [1:0] asi_fifo3_q,asi_fifo2_q,asi_fifo1_q,asi_fifo0_q ;
assign asi_fifo0_din[1:0] = asi_fifo0_sel ? thrid_g[1:0] : asi_fifo1_q[1:0] ;
assign asi_fifo1_din[1:0] = asi_fifo1_sel ? thrid_g[1:0] : asi_fifo2_q[1:0] ;
assign asi_fifo2_din[1:0] = asi_fifo2_sel ? thrid_g[1:0] : asi_fifo3_q[1:0] ;
assign asi_fifo3_din[1:0] = thrid_g[1:0] ; // can never shift into.
// Matrix for Enable
// shift | wr | Entry Written ?
// 0 0 0
// 0 1 if top
// 1 0 if entry+1 is vld
// 1 1 if entry itself is vld => as is.
wire wr_not_sh,sh_not_wr,wr_and_sh ;
assign wr_not_sh = fifo_wr & ~fifo_shift ; // write not shift
assign sh_not_wr = ~fifo_wr & fifo_shift ; // shift not write
assign wr_and_sh = fifo_wr & fifo_shift ; // shift and write
wire asi_fifo0_vin,asi_fifo1_vin,asi_fifo2_vin,asi_fifo3_vin ;
assign asi_fifo0_vin =
(wr_not_sh & fifo_top[0]) |
(sh_not_wr & asi_fifo1_vld) |
(wr_and_sh & asi_fifo0_vld) ;
assign asi_fifo1_vin =
(wr_not_sh & fifo_top[1]) |
(sh_not_wr & asi_fifo2_vld) |
(wr_and_sh & asi_fifo1_vld) ;
assign asi_fifo2_vin =
(wr_not_sh & fifo_top[2]) |
(sh_not_wr & asi_fifo3_vld) |
(wr_and_sh & asi_fifo2_vld) ;
assign asi_fifo3_vin =
(wr_not_sh & fifo_top[3]) |
(wr_and_sh & asi_fifo3_vld) ;
wire asi_fifo0_en,asi_fifo1_en,asi_fifo2_en,asi_fifo3_en ;
assign asi_fifo0_en = (fifo_wr & fifo_top[0]) | fifo_shift ;
assign asi_fifo1_en = (fifo_wr & fifo_top[1]) | fifo_shift ;
assign asi_fifo2_en = (fifo_wr & fifo_top[2]) | fifo_shift ;
assign asi_fifo3_en = (fifo_wr & fifo_top[3]) | fifo_shift ;
wire asi_fifo3_rst,asi_fifo2_rst,asi_fifo1_rst,asi_fifo0_rst ;
assign asi_fifo0_rst = reset ;
assign asi_fifo1_rst = reset ;
assign asi_fifo2_rst = reset ;
assign asi_fifo3_rst = reset ;
// Datapath :
// fifo entry 0 is earliest. fifo entry 3 is latest.
dffe_s #(2) asiq_fifo_0 (
.din (asi_fifo0_din[1:0]),
.q (asi_fifo0_q[1:0]),
.en (asi_fifo0_en),
.clk (clk),
.se (se), .si (), .so ()
);
dffre_s asiqv_fifo_0 (
.din (asi_fifo0_vin),
.q (asi_fifo0_vld),
.en (asi_fifo0_en), .rst (asi_fifo0_rst),
.clk (clk),
.se (se), .si (), .so ()
);
wire asi_sel_thrd3,asi_sel_thrd2,asi_sel_thrd1,asi_sel_thrd0;
assign asi_sel_thrd0 = ~asi_fifo0_q[1] & ~asi_fifo0_q[0] & (tlb_ld_inst0 | tlb_st_inst0) ;
assign asi_sel_thrd1 = ~asi_fifo0_q[1] & asi_fifo0_q[0] & (tlb_ld_inst1 | tlb_st_inst1) ;
assign asi_sel_thrd2 = asi_fifo0_q[1] & ~asi_fifo0_q[0] & (tlb_ld_inst2 | tlb_st_inst2) ;
assign asi_sel_thrd3 = asi_fifo0_q[1] & asi_fifo0_q[0] & (tlb_ld_inst3 | tlb_st_inst3) ;
dffe_s #(2) asiq_fifo_1 (
.din (asi_fifo1_din[1:0]),
.q (asi_fifo1_q[1:0]),
.en (asi_fifo1_en),
.clk (clk),
.se (se), .si (), .so ()
);
dffre_s asiqv_fifo_1 (
.din (asi_fifo1_vin),
.q (asi_fifo1_vld),
.en (asi_fifo1_en), .rst (asi_fifo1_rst),
.clk (clk),
.se (se), .si (), .so ()
);
dffe_s #(2) asiq_fifo_2 (
.din (asi_fifo2_din[1:0]),
.q (asi_fifo2_q[1:0]),
.en (asi_fifo2_en),
.clk (clk),
.se (se), .si (), .so ()
);
dffre_s asiqv_fifo_2 (
.din (asi_fifo2_vin),
.q (asi_fifo2_vld),
.en (asi_fifo2_en), .rst (asi_fifo2_rst),
.clk (clk),
.se (se), .si (), .so ()
);
dffe_s #(2) asiq_fifo_3 (
.din (asi_fifo3_din[1:0]),
.q (asi_fifo3_q[1:0]),
.en (asi_fifo3_en),
.clk (clk),
.se (se), .si (), .so ()
);
dffre_s asiqv_fifo_3 (
.din (asi_fifo3_vin),
.q (asi_fifo3_vld),
.en (asi_fifo3_en), .rst (asi_fifo3_rst),
.clk (clk),
.se (se), .si (), .so ()
);
//---
assign tlb_access_initiated =
((tlb_access_sel_thrd0 & ~tlb_access_rst0) |
(tlb_access_sel_thrd1 & ~tlb_access_rst1) |
(tlb_access_sel_thrd2 & ~tlb_access_rst2) |
(tlb_access_sel_thrd3 & ~tlb_access_rst3)) & ~tlb_access_pending ;
wire tlb_blocking_rst ;
assign tlb_blocking_rst = reset |
tlu_lsu_stxa_ack | tlu_lsu_ldxa_async_data_vld |
ifu_tlb_rd_cmplt0 | ifu_tlb_rd_cmplt1 |
ifu_tlb_rd_cmplt2 | ifu_tlb_rd_cmplt3 |
ifu_lsu_asi_ack |
lsu_diagnstc_wr_src_sel_e;
// MMU/IFU/DIAG Action is pending
dffre_s #(1) tlbpnd (
.din (tlb_access_initiated),
.q (tlb_access_pending),
.rst (tlb_blocking_rst), .en (tlb_access_initiated),
.clk (clk),
.se (se), .si (), .so ()
);
/*wire asi_pend0,asi_pend1,asi_pend2,asi_pend3 ;
dffre_s #(4) asithrdpnd (
.din ({tlb_access_sel_thrd3,tlb_access_sel_thrd2,
tlb_access_sel_thrd1,tlb_access_sel_thrd0}),
.q ({asi_pend3,asi_pend2,asi_pend1,asi_pend0}),
.rst (tlb_blocking_rst), .en (tlb_access_initiated),
.clk (clk),
.se (se), .si (), .so ()
);
wire asi_pend_non_thrd0 ;
assign asi_pend_non_thrd0 = asi_pend1 | asi_pend2 | asi_pend3 ;
wire asi_pend_non_thrd1 ;
assign asi_pend_non_thrd1 = asi_pend0 | asi_pend2 | asi_pend3 ;
wire asi_pend_non_thrd2 ;
assign asi_pend_non_thrd2 = asi_pend0 | asi_pend1 | asi_pend3 ;
wire asi_pend_non_thrd3 ;
assign asi_pend_non_thrd3 = asi_pend0 | asi_pend1 | asi_pend2 ; */
// Would like to remove st_inst_vld_m. This is however required to
// source rs3 data to tlu/mmu. Send rs3_data directly !!!
wire diag_wr_src, diag_wr_src_d1, diag_wr_src_d2 ;
assign tlb_access_blocked =
(tlb_access_pending & ~ifu_asi_vld_d1 & ~diag_wr_src_d1) |
(st_sqsh_m & ~(ifu_asi_vld_d1 & ~ifu_asi_ack_d1) & ~diag_wr_src_d1) ; // Bug 4875
//(st_inst_vld_m & ~lsu_ifu_asi_vld_d1 & ~diag_wr_src_d1) ;
// fixed priority. tlb accesses are issued speculatively in the m-stage and are
// Change priority to round-robin !!!
// flushed in the g-stage in the tlu if necessary.
// diagnstc writes will block for cache/tag access.
// This means that access can be blocked if a st is
// in the m-stage or a memref in the d stage. (!!!)
// In this case, it is better to stage a different
// bus for rs3 data.
// Note : Selection Process.
// 1. Priority Encoded selection if no access pending.
// This may have to be changed to prevent bias towards a
// single thread.
// 2. Once thread is selected :
// a. generate single pulse - mmu. tlb_access_blocked
// used for this purpose.
// b. generate window - ifu/diag. To prevent spurious change
// in selects, asi_pend_non_thrdx and tlb_access_pending
// qual. is required.
assign tlb_access_sel_thrd0 = ~rst_tri_en &
asi_sel_thrd0 & ~tlb_access_blocked ;
assign tlb_access_sel_thrd1 = ~rst_tri_en &
asi_sel_thrd1 & ~tlb_access_blocked ;
assign tlb_access_sel_thrd2 = ~rst_tri_en &
asi_sel_thrd2 & ~tlb_access_blocked ;
assign tlb_access_sel_thrd3 = ~rst_tri_en &
asi_sel_thrd3 & ~tlb_access_blocked ;
//assign tlb_access_sel_thrd0 = ~rst_tri_en & (
// (tlb_ld_inst0 | tlb_st_inst0) & ~tlb_access_blocked &
// ~asi_pend_non_thrd0 );
//assign tlb_access_sel_thrd1 = ~rst_tri_en & (
// (tlb_ld_inst1 | tlb_st_inst1) &
// ~(((tlb_ld_inst0 | tlb_st_inst0) & ~tlb_access_pending) | tlb_access_blocked) &
// ~asi_pend_non_thrd1 );
//assign tlb_access_sel_thrd2 = ~rst_tri_en & (
// (tlb_ld_inst2 | tlb_st_inst2) &
// ~(((tlb_ld_inst0 | tlb_st_inst0 | tlb_ld_inst1 | tlb_st_inst1) & ~tlb_access_pending)
// | tlb_access_blocked) &
// ~asi_pend_non_thrd2 );
//assign tlb_access_sel_thrd3 = ~rst_tri_en & (
// (tlb_ld_inst3 | tlb_st_inst3) &
// ~(((tlb_ld_inst0 | tlb_st_inst0 | tlb_ld_inst1 | tlb_st_inst1 |
// tlb_ld_inst2 | tlb_st_inst2) & ~tlb_access_pending) | tlb_access_blocked) &
// ~asi_pend_non_thrd3 );
dff_s #(4) selt_stgd1 (
.din ({tlb_access_sel_thrd3,tlb_access_sel_thrd2,
tlb_access_sel_thrd1,tlb_access_sel_thrd0}),
.q ({tlb_access_sel_thrd3_d1,tlb_access_sel_thrd2_d1,
tlb_access_sel_thrd1_d1,tlb_access_sel_thrd0_d1}),
.clk (clk),
.se (se), .si (), .so ()
);
wire tlb_access_sel_default;
assign tlb_access_sel_default = rst_tri_en | (
~(tlb_access_sel_thrd2 | tlb_access_sel_thrd1 | tlb_access_sel_thrd0));
dff_s #(4) lsu_diagnstc_data_sel_ff (
.din ({tlb_access_sel_default,tlb_access_sel_thrd2,
tlb_access_sel_thrd1,tlb_access_sel_thrd0}),
.q ({lsu_diagnstc_data_sel[3:0]}),
.clk (clk),
.se (se), .si (), .so ()
);
dff_s #(4) lsu_diagnstc_va_sel_ff (
.din ({tlb_access_sel_default,tlb_access_sel_thrd2,
tlb_access_sel_thrd1,tlb_access_sel_thrd0}),
.q ({lsu_diagnstc_va_sel[3:0]}),
.clk (clk),
.se (se), .si (), .so ()
);
// Begin - Bug 3487
assign st_sqsh_m =
(st_inst_vld_m & asi_internal_m & lsu_alt_space_m) ; // Squash as bus required for stxa.
assign tlb_st_data_sel_m[0] = (tlb_access_sel_thrd0 & ~st_sqsh_m) | (st_sqsh_m & thread0_m) ;
assign tlb_st_data_sel_m[1] = (tlb_access_sel_thrd1 & ~st_sqsh_m) | (st_sqsh_m & thread1_m) ;
assign tlb_st_data_sel_m[2] = (tlb_access_sel_thrd2 & ~st_sqsh_m) | (st_sqsh_m & thread2_m) ;
assign tlb_st_data_sel_m[3] = ~|tlb_st_data_sel_m[2:0];
assign lsu_ifu_asi_data_en_l = ~(ifu_asi_vld & tlb_access_initiated) ;
// End - Bug 3487
/*assign tlb_st_data_sel_m[0] = tlb_access_sel_thrd0 | ((st_inst_vld_m & thread0_m) & tlb_access_blocked) ;
assign tlb_st_data_sel_m[1] = tlb_access_sel_thrd1 | ((st_inst_vld_m & thread1_m) & tlb_access_blocked) ;
assign tlb_st_data_sel_m[2] = tlb_access_sel_thrd2 | ((st_inst_vld_m & thread2_m) & tlb_access_blocked) ;
assign tlb_st_data_sel_m[3] = ~|tlb_st_data_sel_m[2:0];*/
//assign lsu_tlb_st_sel_m[3:0] = tlb_st_data_sel_m[3:0] ;
assign lsu_tlb_st_sel_m[0] = tlb_st_data_sel_m[0] & ~rst_tri_en;
assign lsu_tlb_st_sel_m[1] = tlb_st_data_sel_m[1] & ~rst_tri_en;
assign lsu_tlb_st_sel_m[2] = tlb_st_data_sel_m[2] & ~rst_tri_en;
assign lsu_tlb_st_sel_m[3] = tlb_st_data_sel_m[3] | rst_tri_en;
assign lsu_tlu_tlb_ld_inst_m =
(tlb_access_sel_thrd0 & tlb_ld_inst0 & ~nontlb_asi0) |
(tlb_access_sel_thrd1 & tlb_ld_inst1 & ~nontlb_asi1) |
(tlb_access_sel_thrd2 & tlb_ld_inst2 & ~nontlb_asi2) |
(tlb_access_sel_thrd3 & tlb_ld_inst3 & ~nontlb_asi3) ;
// diagnstic write for dside will not go thru tlu.
assign lsu_tlu_tlb_st_inst_m =
(tlb_access_sel_thrd0 & tlb_st_inst0 & ~nontlb_asi0) |
(tlb_access_sel_thrd1 & tlb_st_inst1 & ~nontlb_asi1) |
(tlb_access_sel_thrd2 & tlb_st_inst2 & ~nontlb_asi2) |
(tlb_access_sel_thrd3 & tlb_st_inst3 & ~nontlb_asi3) ;
assign lsu_tlu_tlb_access_tid_m[0] = tlb_access_sel_thrd1 | tlb_access_sel_thrd3 ;
assign lsu_tlu_tlb_access_tid_m[1] = tlb_access_sel_thrd2 | tlb_access_sel_thrd3 ;
// Diagnostic write to dcache
assign dc0_diagnstc_wr_en = (tlb_access_sel_thrd0 & tlb_st_inst0 & dc0_diagnstc_asi) ;
assign dc1_diagnstc_wr_en = (tlb_access_sel_thrd1 & tlb_st_inst1 & dc1_diagnstc_asi) ;
assign dc2_diagnstc_wr_en = (tlb_access_sel_thrd2 & tlb_st_inst2 & dc2_diagnstc_asi) ;
assign dc3_diagnstc_wr_en = (tlb_access_sel_thrd3 & tlb_st_inst3 & dc3_diagnstc_asi) ;
assign dc_diagnstc_wr_en =
dc0_diagnstc_wr_en | dc1_diagnstc_wr_en | dc2_diagnstc_wr_en | dc3_diagnstc_wr_en ;
// Diagnostic write to dtag/vld
assign dtagv0_diagnstc_wr_en = (tlb_access_sel_thrd0 & tlb_st_inst0 & dtagv0_diagnstc_asi) ;
assign dtagv1_diagnstc_wr_en = (tlb_access_sel_thrd1 & tlb_st_inst1 & dtagv1_diagnstc_asi) ;
assign dtagv2_diagnstc_wr_en = (tlb_access_sel_thrd2 & tlb_st_inst2 & dtagv2_diagnstc_asi) ;
assign dtagv3_diagnstc_wr_en = (tlb_access_sel_thrd3 & tlb_st_inst3 & dtagv3_diagnstc_asi) ;
assign dtagv_diagnstc_wr_en =
dtagv0_diagnstc_wr_en | dtagv1_diagnstc_wr_en | dtagv2_diagnstc_wr_en | dtagv3_diagnstc_wr_en ;
// If a diagnostic access is selected in a cycle, then the earliest the
// e-stage can occur for the write is 2-cycles later.
assign diag_wr_src = dtagv_diagnstc_wr_en | dc_diagnstc_wr_en ;
wire diag_wr_src_with_rst;
assign diag_wr_src_with_rst = diag_wr_src & ~lsu_diagnstc_wr_src_sel_e;
dff_s #(1) diagwr_d1 (
.din (diag_wr_src_with_rst),
.q (diag_wr_src_d1),
.clk (clk),
.se (se), .si (), .so ()
);
wire diag_wr_src_d1_with_rst;
assign diag_wr_src_d1_with_rst = diag_wr_src_d1 & ~lsu_diagnstc_wr_src_sel_e;
dff_s #(1) diagwr_d2 (
.din (diag_wr_src_d1_with_rst),
.q (diag_wr_src_d2),
.clk (clk),
.se (se), .si (), .so ()
);
// If there is no memory reference, then the diag access is free to go.
// tlb_access_blocked must be set appr.
wire diag_wr_src_sel_d1, diag_wr_src_sel_din;
//bug4057: kill diagnostic write if dfq has valid requests to l1d$
//assign diag_wr_src_sel_din = diag_wr_src_d2 & ~memref_e;
assign diag_wr_src_sel_din = diag_wr_src_d2 & ~(memref_e | lsu_dfq_vld);
assign lsu_diagnstc_wr_src_sel_e = ~diag_wr_src_sel_d1 & diag_wr_src_sel_din ;
dff_s #(1) diagwrsel_d1 (
.din (diag_wr_src_sel_din),
.q (diag_wr_src_sel_d1),
.clk (clk),
.se (se), .si (), .so ()
);
// Decode for diagnostic cache/dtag/vld write
//wire [13:11] lngltncy_ldst_va;
//assign lngltncy_ldst_va[13:11]= lsu_lngltncy_ldst_va[13:11];
//assign lsu_diagnstc_wr_way_e[0] = ~lngltncy_ldst_va[12] & ~lngltncy_ldst_va[11] ;
//assign lsu_diagnstc_wr_way_e[1] = ~lngltncy_ldst_va[12] & lngltncy_ldst_va[11] ;
//assign lsu_diagnstc_wr_way_e[2] = lngltncy_ldst_va[12] & ~lngltncy_ldst_va[11] ;
//assign lsu_diagnstc_wr_way_e[3] = lngltncy_ldst_va[12] & lngltncy_ldst_va[11] ;
assign lsu_diagnstc_dtagv_prty_invrt_e =
lsu_diag_va_prty_invrt & dtagv_diagnstc_wr_en & lsu_diagnstc_wr_src_sel_e ;
// ASI Interface to IFU
assign lsu_ifu_asi_load =
(tlb_access_sel_thrd0 & tlb_ld_inst0 & ifu_nontlb0_asi) |
(tlb_access_sel_thrd1 & tlb_ld_inst1 & ifu_nontlb1_asi) |
(tlb_access_sel_thrd2 & tlb_ld_inst2 & ifu_nontlb2_asi) |
(tlb_access_sel_thrd3 & tlb_ld_inst3 & ifu_nontlb3_asi) ;
assign ifu_asi_store =
(tlb_access_sel_thrd0 & tlb_st_inst0 & ifu_nontlb0_asi) |
(tlb_access_sel_thrd1 & tlb_st_inst1 & ifu_nontlb1_asi) |
(tlb_access_sel_thrd2 & tlb_st_inst2 & ifu_nontlb2_asi) |
(tlb_access_sel_thrd3 & tlb_st_inst3 & ifu_nontlb3_asi) ;
assign ifu_asi_vld = lsu_ifu_asi_load | ifu_asi_store ;
dff_s #(2) iasiv_d1 (
.din ({ifu_asi_vld,ifu_lsu_asi_ack}),
.q ({ifu_asi_vld_d1,ifu_asi_ack_d1}),
.clk (clk),
.se (se), .si (), .so ()
);
// Bug 3932 - delay asi_vld for ifu.
assign lsu_ifu_asi_vld = ifu_asi_vld_d1 & ~ifu_asi_ack_d1 ;
assign ifu_asi_store_cmplt_en = ifu_asi_store & ifu_lsu_asi_ack ;
dff_s #(1) iasist_d1 (
.din (ifu_asi_store_cmplt_en),
.q (ifu_asi_store_cmplt_en_d1),
.clk (clk),
.se (se), .si (), .so ()
);
assign lsu_ifu_asi_thrid[1:0] = lsu_tlu_tlb_access_tid_m[1:0] ;
//=========================================================================================
// MEMBAR/FLUSH HANDLING
//=========================================================================================
// Check for skids in this area - verification.
wire [3:0] no_spc_rmo_st ;
// Can membar/flush cause switch out from front end ??? Need to remove from
// ldst_miss if case.
// membar/flush will both swo thread and assert flush.
// membar will signal completion once stb for thread empty
// flush will signal completion once flush pkt is visible at head of cfq and
// i-side invalidates are complete
// ** flush bit needs to be added to dfq **
dff_s #(2) bsync_stgm (
.din ({ifu_tlu_mb_inst_e,ifu_tlu_flsh_inst_e}),
.q ({mbar_inst_m,flsh_inst_m}),
.clk (clk),
.se (se), .si (), .so ()
);
assign lsu_flsh_inst_m = flsh_inst_m ;
wire mbar_inst_unflushed,flsh_inst_unflushed ;
dff_s #(2) bsync_stgg (
.din ({mbar_inst_m,flsh_inst_m}),
.q ({mbar_inst_unflushed,flsh_inst_unflushed}),
.clk (clk),
.se (se), .si (), .so ()
);
wire [3:0] flsh_cmplt_d1 ;
/*dff #(4) flshcmplt (
.din (lsu_dfq_flsh_cmplt[3:0]),
.q (flsh_cmplt_d1[3:0]),
.clk (clk),
.se (se), .si (), .so ()
);*/
// now flopped in dctl
assign flsh_cmplt_d1[3:0] = lsu_dfq_flsh_cmplt[3:0] ;
assign mbar_inst_g = mbar_inst_unflushed & lsu_inst_vld_w ;
assign flsh_inst_g = flsh_inst_unflushed & lsu_inst_vld_w ;
// THREAD0 MEMBAR/FLUSH
// barrier sync
assign bsync0_reset =
reset | (mbar_vld0 & lsu_stb_empty[0] & no_spc_rmo_st[0])
| (flsh_vld0 & flsh_cmplt_d1[0]) ;
assign bsync0_en = (flush_inst0_g | mbar_inst0_g) & lsu_inst_vld_w & ~dctl_flush_pipe_w ;
assign flush_inst0_g = flsh_inst_g & thread0_g ;
assign mbar_inst0_g = mbar_inst_g & thread0_g ;
// bsyncs are set in g-stage to allow earlier stores in pipe to drain to
// thread's stb
dffre_s #(2) bsync_vld0 (
.din ({mbar_inst0_g,flush_inst0_g}),
.q ({mbar_vld0,flsh_vld0}),
.rst (bsync0_reset), .en (bsync0_en),
.clk (clk),
.se (se), .si (), .so ()
);
// THREAD1 MEMBAR/FLUSH
// barrier sync
assign bsync1_reset =
reset | (mbar_vld1 & lsu_stb_empty[1] & no_spc_rmo_st[1])
| (flsh_vld1 & flsh_cmplt_d1[1]) ;
assign bsync1_en = (flush_inst1_g | mbar_inst1_g) & lsu_inst_vld_w & ~dctl_flush_pipe_w ;
assign flush_inst1_g = flsh_inst_g & thread1_g ;
assign mbar_inst1_g = mbar_inst_g & thread1_g ;
// bsyncs are set in g-stage to allow earlier stores in pipe to drain to
// thread's stb
dffre_s #(2) bsync_vld1 (
.din ({mbar_inst1_g,flush_inst1_g}),
.q ({mbar_vld1,flsh_vld1}),
.rst (bsync1_reset), .en (bsync1_en),
.clk (clk),
.se (se), .si (), .so ()
);
// THREAD2 MEMBAR/FLUSH
// barrier sync
assign bsync2_reset =
reset | (mbar_vld2 & lsu_stb_empty[2] & no_spc_rmo_st[2])
| (flsh_vld2 & flsh_cmplt_d1[2]) ;
assign bsync2_en = (flush_inst2_g | mbar_inst2_g) & lsu_inst_vld_w & ~dctl_flush_pipe_w ;
assign flush_inst2_g = flsh_inst_g & thread2_g ;
assign mbar_inst2_g = mbar_inst_g & thread2_g ;
// bsyncs are set in g-stage to allow earlier stores in pipe to drain to
// thread's stb
dffre_s #(2) bsync_vld2 (
.din ({mbar_inst2_g,flush_inst2_g}),
.q ({mbar_vld2,flsh_vld2}),
.rst (bsync2_reset), .en (bsync2_en),
.clk (clk),
.se (se), .si (), .so ()
);
// THREAD3 MEMBAR/FLUSH
// barrier sync
assign bsync3_reset =
reset | (mbar_vld3 & lsu_stb_empty[3] & no_spc_rmo_st[3])
| (flsh_vld3 & flsh_cmplt_d1[3]) ;
assign bsync3_en = (flush_inst3_g | mbar_inst3_g) & lsu_inst_vld_w & ~dctl_flush_pipe_w ;
assign flush_inst3_g = flsh_inst_g & thread3_g ;
assign mbar_inst3_g = mbar_inst_g & thread3_g ;
// bsyncs are set in g-stage to allow earlier stores in pipe to drain to
// thread's stb
dffre_s #(2) bsync_vld3 (
.din ({mbar_inst3_g,flush_inst3_g}),
.q ({mbar_vld3,flsh_vld3}),
.rst (bsync3_reset), .en (bsync3_en),
.clk (clk),
.se (se), .si (), .so ()
);
//=========================================================================================
// RMO Store Ack Count
//=========================================================================================
// Each thread maintains an 8b outstanding rmo ack count. To avoid overflow,
// it is the responsiblity of software to insert a membar after at most 256 rmo stores.
// 03/08/2003 now change from 256 to 16
// 8 outstanding instead of 16
wire [3:0] ackcnt0,ackcnt1,ackcnt2,ackcnt3 ;
wire [3:0] ackcnt0_din,ackcnt1_din,ackcnt2_din,ackcnt3_din ;
// st_rmo_issue/st_rmo_ack vectors are one hot.
// Adders(2). Need two as two separate threads can be incremented and decremented
// in a cycle.
wire [3:0] ackcnt_incr, ackcnt_decr ;
wire [3:0] ackcnt_mx_incr, ackcnt_mx_decr ;
wire [3:0] acknt_mx_incr_sel;
assign acknt_mx_incr_sel[3:0] = lsu_stb_rmo_st_issue[3:0];
assign ackcnt_mx_incr[3:0] =
(acknt_mx_incr_sel[0] ? ackcnt0[3:0] : 4'b0) |
(acknt_mx_incr_sel[1] ? ackcnt1[3:0] : 4'b0) |
(acknt_mx_incr_sel[2] ? ackcnt2[3:0] : 4'b0) |
(acknt_mx_incr_sel[3] ? ackcnt3[3:0] : 4'b0) ;
wire [3:0] acknt_mx_decr_sel;
assign acknt_mx_decr_sel[3:0] = lsu_cpx_rmo_st_ack[3:0];
assign ackcnt_mx_decr[3:0] =
(acknt_mx_decr_sel[0] ? ackcnt0[3:0] : 4'b0 ) |
(acknt_mx_decr_sel[1] ? ackcnt1[3:0] : 4'b0 ) |
(acknt_mx_decr_sel[2] ? ackcnt2[3:0] : 4'b0 ) |
(acknt_mx_decr_sel[3] ? ackcnt3[3:0] : 4'b0 ) ;
assign ackcnt_incr[3:0] = ackcnt_mx_incr[3:0] + 4'b0001 ;
assign ackcnt_decr[3:0] = ackcnt_mx_decr[3:0] - 4'b0001 ;
assign ackcnt0_din[3:0] = lsu_cpx_rmo_st_ack[0] ? ackcnt_decr[3:0] : ackcnt_incr[3:0] ;
assign ackcnt1_din[3:0] = lsu_cpx_rmo_st_ack[1] ? ackcnt_decr[3:0] : ackcnt_incr[3:0] ;
assign ackcnt2_din[3:0] = lsu_cpx_rmo_st_ack[2] ? ackcnt_decr[3:0] : ackcnt_incr[3:0] ;
assign ackcnt3_din[3:0] = lsu_cpx_rmo_st_ack[3] ? ackcnt_decr[3:0] : ackcnt_incr[3:0] ;
wire [3:0] ackcnt_en ;
// if both occur in the same cycle then they cancel out.
assign ackcnt_en[0] = lsu_stb_rmo_st_issue[0] ^ lsu_cpx_rmo_st_ack[0] ;
assign ackcnt_en[1] = lsu_stb_rmo_st_issue[1] ^ lsu_cpx_rmo_st_ack[1] ;
assign ackcnt_en[2] = lsu_stb_rmo_st_issue[2] ^ lsu_cpx_rmo_st_ack[2] ;
assign ackcnt_en[3] = lsu_stb_rmo_st_issue[3] ^ lsu_cpx_rmo_st_ack[3] ;
// Thread0
dffre_s #(4) ackcnt0_ff (
.din (ackcnt0_din[3:0]),
.q (ackcnt0[3:0]),
.rst (reset), .en (ackcnt_en[0]),
.clk (clk),
.se (se), .si (), .so ()
);
// Thread1
dffre_s #(4) ackcnt1_ff (
.din (ackcnt1_din[3:0]),
.q (ackcnt1[3:0]),
.rst (reset), .en (ackcnt_en[1]),
.clk (clk),
.se (se), .si (), .so ()
);
// Thread2
dffre_s #(4) ackcnt2_ff (
.din (ackcnt2_din[3:0]),
.q (ackcnt2[3:0]),
.rst (reset), .en (ackcnt_en[2]),
.clk (clk),
.se (se), .si (), .so ()
);
// Thread3
dffre_s #(4) ackcnt3_ff (
.din (ackcnt3_din[3:0]),
.q (ackcnt3[3:0]),
.rst (reset), .en (ackcnt_en[3]),
.clk (clk),
.se (se), .si (), .so ()
);
assign no_spc_rmo_st[0] = ~(|ackcnt0[3:0]) ;
assign no_spc_rmo_st[1] = ~(|ackcnt1[3:0]) ;
assign no_spc_rmo_st[2] = ~(|ackcnt2[3:0]) ;
assign no_spc_rmo_st[3] = ~(|ackcnt3[3:0]) ;
//8 outstanding rmo st will throttle the PCX issue st
assign lsu_outstanding_rmo_st_max [0] = ackcnt0[3];
assign lsu_outstanding_rmo_st_max [1] = ackcnt1[3];
assign lsu_outstanding_rmo_st_max [2] = ackcnt2[3];
assign lsu_outstanding_rmo_st_max [3] = ackcnt3[3];
// streaming unit does not have to care about outstanding rmo sparc-stores.
// membar will take care of that. spu must insert appr. delay in sampling signal.
/*dff #(4) spustb_d1 ( // moved to stb_rwctl
.din (lsu_stb_empty[3:0]),
.q (lsu_spu_stb_empty[3:0]),
.clk (clk),
.se (se), .si (), .so ()
); */
//assign lsu_spu_stb_empty[3:0] = lsu_stb_empty[3:0] ;
//=========================================================================================
// Thread Staging
//=========================================================================================
// Thread staging can be optimized.
dff_s #(2) thrid_stgd (
.din (ifu_lsu_thrid_s[1:0]),
.q (thrid_d[1:0]),
.clk (clk),
.se (se), .si (), .so ()
);
dff_s #(2) lsu_tlu_thrid_stgd (
.din (ifu_lsu_thrid_s[1:0]),
.q (lsu_tlu_thrid_d[1:0]),
.clk (clk),
.se (se), .si (), .so ()
);
//assign lsu_tlu_thrid_d[1:0] = thrid_d[1:0] ;
assign thread0_d = ~thrid_d[1] & ~thrid_d[0] ;
assign thread1_d = ~thrid_d[1] & thrid_d[0] ;
assign thread2_d = thrid_d[1] & ~thrid_d[0] ;
assign thread3_d = thrid_d[1] & thrid_d[0] ;
dff_s #(2) thrid_stge (
.din (thrid_d[1:0]),
.q (thrid_e[1:0]),
.clk (clk),
.se (se), .si (), .so ()
);
assign thread0_e = ~thrid_e[1] & ~thrid_e[0] ;
assign thread1_e = ~thrid_e[1] & thrid_e[0] ;
assign thread2_e = thrid_e[1] & ~thrid_e[0] ;
assign thread3_e = thrid_e[1] & thrid_e[0] ;
dff_s #(2) thrid_stgm (
.din (thrid_e[1:0]),
.q (thrid_m[1:0]),
.clk (clk),
.se (se), .si (), .so ()
);
assign thread0_m = ~thrid_m[1] & ~thrid_m[0] ;
assign thread1_m = ~thrid_m[1] & thrid_m[0] ;
assign thread2_m = thrid_m[1] & ~thrid_m[0] ;
assign thread3_m = thrid_m[1] & thrid_m[0] ;
bw_u1_buf_30x UZfix_thread0_m ( .a(thread0_m), .z(lsu_dctldp_thread0_m) );
bw_u1_buf_30x UZfix_thread1_m ( .a(thread1_m), .z(lsu_dctldp_thread1_m) );
bw_u1_buf_30x UZfix_thread2_m ( .a(thread2_m), .z(lsu_dctldp_thread2_m) );
bw_u1_buf_30x UZfix_thread3_m ( .a(thread3_m), .z(lsu_dctldp_thread3_m) );
dff_s #(2) thrid_stgg (
.din (thrid_m[1:0]),
.q (thrid_g[1:0]),
.clk (clk),
.se (se), .si (), .so ()
);
assign thread0_g = ~thrid_g[1] & ~thrid_g[0] ;
assign thread1_g = ~thrid_g[1] & thrid_g[0] ;
assign thread2_g = thrid_g[1] & ~thrid_g[0] ;
assign thread3_g = thrid_g[1] & thrid_g[0] ;
dff_s #(2) thrid_stgw2 (
.din (thrid_g[1:0]),
.q (thrid_w2[1:0]),
.clk (clk),
.se (se), .si (), .so ()
);
assign thread0_w2 = ~thrid_w2[1] & ~thrid_w2[0] ;
assign thread1_w2 = ~thrid_w2[1] & thrid_w2[0] ;
assign thread2_w2 = thrid_w2[1] & ~thrid_w2[0] ;
assign thread3_w2 = thrid_w2[1] & thrid_w2[0] ;
dff_s #(2) thrid_stgw3 (
.din (thrid_w2[1:0]),
.q (thrid_w3[1:0]),
.clk (clk),
.se (se), .si (), .so ()
);
assign thread0_w3 = ~thrid_w3[1] & ~thrid_w3[0] ;
assign thread1_w3 = ~thrid_w3[1] & thrid_w3[0] ;
assign thread2_w3 = thrid_w3[1] & ~thrid_w3[0] ;
assign thread3_w3 = thrid_w3[1] & thrid_w3[0] ;
//dff #(4) thrid_stgw3 (
// .din ({thread0_w2,thread1_w2,thread2_w2,thread3_w2}),
// .q ({thread0_w3,thread1_w3,thread2_w3,thread3_w3}),
// .clk (clk),
// .se (se), .si (), .so ()
// );
// ldxa thread id
assign ldxa_thrid_w2[1:0] = tlu_lsu_ldxa_tid_w2[1:0] ;
assign tlu_ldxa_thread0_w2 = ~ldxa_thrid_w2[1] & ~ldxa_thrid_w2[0] ;
assign tlu_ldxa_thread1_w2 = ~ldxa_thrid_w2[1] & ldxa_thrid_w2[0] ;
assign tlu_ldxa_thread2_w2 = ldxa_thrid_w2[1] & ~ldxa_thrid_w2[0] ;
assign tlu_ldxa_thread3_w2 = ldxa_thrid_w2[1] & ldxa_thrid_w2[0] ;
assign spu_stxa_thread0 = ~spu_lsu_stxa_ack_tid[1] & ~spu_lsu_stxa_ack_tid[0] ;
assign spu_stxa_thread1 = ~spu_lsu_stxa_ack_tid[1] & spu_lsu_stxa_ack_tid[0] ;
assign spu_stxa_thread2 = spu_lsu_stxa_ack_tid[1] & ~spu_lsu_stxa_ack_tid[0] ;
assign spu_stxa_thread3 = spu_lsu_stxa_ack_tid[1] & spu_lsu_stxa_ack_tid[0] ;
assign spu_ldxa_thread0_w2 = ~spu_lsu_ldxa_tid_w2[1] & ~spu_lsu_ldxa_tid_w2[0] ;
assign spu_ldxa_thread1_w2 = ~spu_lsu_ldxa_tid_w2[1] & spu_lsu_ldxa_tid_w2[0] ;
assign spu_ldxa_thread2_w2 = spu_lsu_ldxa_tid_w2[1] & ~spu_lsu_ldxa_tid_w2[0] ;
assign spu_ldxa_thread3_w2 = spu_lsu_ldxa_tid_w2[1] & spu_lsu_ldxa_tid_w2[0] ;
assign ifu_ldxa_thread0_w2 = ~ifu_lsu_ldxa_tid_w2[1] & ~ifu_lsu_ldxa_tid_w2[0] ;
assign ifu_ldxa_thread1_w2 = ~ifu_lsu_ldxa_tid_w2[1] & ifu_lsu_ldxa_tid_w2[0] ;
assign ifu_ldxa_thread2_w2 = ifu_lsu_ldxa_tid_w2[1] & ~ifu_lsu_ldxa_tid_w2[0] ;
assign ifu_ldxa_thread3_w2 = ifu_lsu_ldxa_tid_w2[1] & ifu_lsu_ldxa_tid_w2[0] ;
wire [1:0] ifu_nontlb_asi_tid ;
dff_s #(2) iasi_tid (
.din (lsu_ifu_asi_thrid[1:0]),
.q (ifu_nontlb_asi_tid[1:0]),
.clk (clk),
.se (se), .si (), .so ()
);
assign ifu_stxa_thread0_w2 = ~ifu_nontlb_asi_tid[1] & ~ifu_nontlb_asi_tid[0] ;
assign ifu_stxa_thread1_w2 = ~ifu_nontlb_asi_tid[1] & ifu_nontlb_asi_tid[0] ;
assign ifu_stxa_thread2_w2 = ifu_nontlb_asi_tid[1] & ~ifu_nontlb_asi_tid[0] ;
assign ifu_stxa_thread3_w2 = ifu_nontlb_asi_tid[1] & ifu_nontlb_asi_tid[0] ;
assign tlu_stxa_thread0_w2 = ~tlu_lsu_stxa_ack_tid[1] & ~tlu_lsu_stxa_ack_tid[0] ;
assign tlu_stxa_thread1_w2 = ~tlu_lsu_stxa_ack_tid[1] & tlu_lsu_stxa_ack_tid[0] ;
assign tlu_stxa_thread2_w2 = tlu_lsu_stxa_ack_tid[1] & ~tlu_lsu_stxa_ack_tid[0] ;
assign tlu_stxa_thread3_w2 = tlu_lsu_stxa_ack_tid[1] & tlu_lsu_stxa_ack_tid[0] ;
//=========================================================================================
// Exception Handling
//=========================================================================================
// tlb related exceptions/errors
//SC assign tlb_daccess_excptn_e =
//SC ((rd_only_ltlb_asi_e & st_inst_vld_e) |
//SC (wr_only_ltlb_asi_e & ld_inst_vld_e)) & alt_space_e ;
//SC assign tlb_daccess_error_e =
//SC ((dfill_tlb_asi_e & ~lsu_tlb_writeable) |
//SC (ifill_tlb_asi_e & ~ifu_lsu_tlb_writeable)) & st_inst_vld_e & alt_space_e ;
//SC dff #(2) tlbex_stgm (
//SC .din ({tlb_daccess_excptn_e,tlb_daccess_error_e}),
//SC .q ({tlb_daccess_excptn_m,tlb_daccess_error_m}),
//SC .clk (clk),
//SC .se (se), .si (), .so ()
//SC );
//SC dff #(2) tlbex_stgg (
//SC .din ({tlb_daccess_excptn_m,tlb_daccess_error_m}),
//SC .q ({tlb_daccess_excptn_g,tlb_daccess_error_g}),
//SC .clk (clk),
//SC .se (se), .si (), .so ()
//SC );
//assign pstate_priv_m =
// thread0_m ? tlu_lsu_pstate_priv[0] :
// thread1_m ? tlu_lsu_pstate_priv[1] :
// thread2_m ? tlu_lsu_pstate_priv[2] :
// tlu_lsu_pstate_priv[3] ;
//SC mux4ds #(1) pstate_priv_m_mux (
//SC .in0 (tlu_lsu_pstate_priv[0]),
//SC .in1 (tlu_lsu_pstate_priv[1]),
//SC .in2 (tlu_lsu_pstate_priv[2]),
//SC .in3 (tlu_lsu_pstate_priv[3]),
//SC .sel0 (thread0_m),
//SC .sel1 (thread1_m),
//SC .sel2 (thread2_m),
//SC .sel3 (thread3_m),
//SC .dout (pstate_priv_m)
//SC );
//SC dff priv_stgg (
//SC .din (pstate_priv_m),
//SC .q (pstate_priv),
//SC .clk (clk),
//SC .se (se), .si (), .so ()
//SC );
// privilege violation - priv page accessed in user mode
//SC assign priv_pg_usr_mode = // data access exception; TT=h30
//SC (ld_inst_vld_unflushed | st_inst_vld_unflushed) & ~(pstate_priv | hpv_priv) & tlb_rd_tte_data[`STLB_DATA_P] ;
// protection violation - store to a page that does not have write permission
//SC assign nonwr_pg_st_access = // data access protection; TT=h33
//SC st_inst_vld_unflushed &
//SC ~tlb_rd_tte_data[`STLB_DATA_W] & ~lsu_dtlb_bypass_g & tlb_cam_hit_g ;
//lsu_dtlb_bypass_g) ; // W=1 in bypass mode - In bypass mode this trap will never happen !!!
//SC wire daccess_prot ;
//SC assign daccess_prot = nonwr_pg_st_access ;
//((~lsu_dtlb_bypass_g & tlb_cam_hit_g) | (tlb_byp_asi_g & lsu_alt_space_g)) ;
// access to a page marked with the nfo with an asi other than nfo asi.
//SC assign nfo_pg_nonnfo_asi = // data access exception; TT=h30
//SC (ld_inst_vld_unflushed | st_inst_vld_unflushed) & // any access
//SC ((~nofault_asi_g & lsu_alt_space_g) | ~lsu_alt_space_g) // in alternate space or not
//SC & tlb_rd_tte_data[`STLB_DATA_NFO] ;
// as_if_usr asi accesses priv page.
//SC assign as_if_usr_priv_pg = // data access exception; TT=h30
//SC (ld_inst_vld_unflushed | st_inst_vld_unflushed) & as_if_user_asi_g & lsu_alt_space_g &
//SC tlb_rd_tte_data[`STLB_DATA_P] ;
// non-cacheable address - iospace or cp=0 (???)
// atomic access to non-cacheable space.
//SC assign atm_access_w_nc = atomic_g & tlb_pgnum[39] ; // io space
// atomic inst with unsupported asi.
//SC assign atm_access_unsup_asi = atomic_g & ~atomic_asi_g & lsu_alt_space_g ;
//SC wire tlb_tte_vld_g ;
//SC assign tlb_tte_vld_g = ~lsu_dtlb_bypass_g & tlb_cam_hit_g ;
//SC wire pg_with_ebit ;
//SC assign pg_with_ebit =
//SC (tlb_rd_tte_data[`STLB_DATA_E] & tlb_tte_vld_g) | // tte
//SC (lsu_dtlb_bypass_g & ~(phy_use_ec_asi_g & lsu_alt_space_g)) | // regular bypass
//SC (tlb_byp_asi_g & ~phy_use_ec_asi_g & lsu_alt_space_g) ; // phy_byp
//SC wire spec_access_epage ;
//SC assign spec_access_epage =
//SC ((ld_inst_vld_unflushed & nofault_asi_g & lsu_alt_space_g) | // spec load
//SC flsh_inst_g) & // flush inst
//SC pg_with_ebit ; // page with side effects
// tlb_rd_tte_data[`STLB_DATA_E] ; // page with side effects
//SC wire quad_asi_non_ldstda ;
// quad-asi used with non ldda/stda
// remove st_inst_vld - stquad unused
// the equation may be incorrect - needs to be for a non-ldda
//SC assign quad_asi_non_ldstda = quad_asi_g & lsu_alt_space_g & ~ldst_dbl_g &
//SC (ld_inst_vld_unflushed | st_inst_vld_unflushed) ;
// need to put in similar exception for binit st
//SC wire binit_asi_non_ldda ;
//SC assign binit_asi_non_ldda = binit_quad_asi_g & lsu_alt_space_g & ~ldst_dbl_g &
//SC (ld_inst_vld_unflushed) ;
//SC wire blk_asi_non_ldstdfa ;
//SC assign blk_asi_non_ldstdfa = blk_asi_g & lsu_alt_space_g &
//SC ~(ldst_dbl_g & fp_ldst_g) & (ld_inst_vld_unflushed | st_inst_vld_unflushed) ;
// trap on illegal asi
//SC wire illegal_asi_trap_g ;
//SC assign illegal_asi_trap_g =
//SC (ld_inst_vld_unflushed | st_inst_vld_unflushed) &
//SC lsu_alt_space_g & ~recognized_asi_g & lsu_inst_vld_w ;
// This can be pushed back into previous cycle.
//SC wire wr_to_strm_sync ;
//SC assign wr_to_strm_sync =
//SC strm_asi & ((ldst_va_g[7:0] == 8'hA0) | (ldst_va_g[7:0] == 8'h68)) &
//SC st_inst_vld_unflushed & lsu_alt_space_g ;
// This should not be double-anded with tlb_tte_vld_g. Check !!!
//SC assign daccess_excptn =
//SC ((priv_pg_usr_mode | as_if_usr_priv_pg | nfo_pg_nonnfo_asi |
//SC atm_access_w_nc | atm_access_unsup_asi))
//SC & tlb_tte_vld_g |
//SC spec_access_epage |
//SC asi_related_trap_g | quad_asi_non_ldstda | tlb_daccess_excptn_g |
//SC illegal_asi_trap_g | spv_use_hpv | binit_asi_non_ldda | wr_to_strm_sync |
//SC blk_asi_non_ldstdfa ;
// HPV Changes
// Push back into previous stage.
// qualification with hpv_priv and hpstate_en required to ensure hypervisor
// is not trying to access.
//assign hpv_priv_e =
// thread0_e ? tlu_lsu_hpv_priv[0] :
// thread1_e ? tlu_lsu_hpv_priv[1] :
// thread2_e ? tlu_lsu_hpv_priv[2] :
// tlu_lsu_hpv_priv[3] ;
// Timing change :
wire [3:0] hpv_priv_d1 ;
wire [3:0] hpstate_en_d1 ;
dff_s #(8) hpv_stgd1 (
.din ({tlu_lsu_hpv_priv[3:0],tlu_lsu_hpstate_en[3:0]}),
.q ({hpv_priv_d1[3:0],hpstate_en_d1[3:0]}),
.clk (clk),
.se (se), .si (), .so ()
);
mux4ds #(1) hpv_priv_e_mux (
.in0 (hpv_priv_d1[0]),
.in1 (hpv_priv_d1[1]),
.in2 (hpv_priv_d1[2]),
.in3 (hpv_priv_d1[3]),
.sel0 (thread0_e),
.sel1 (thread1_e),
.sel2 (thread2_e),
.sel3 (thread3_e),
.dout (hpv_priv_e)
);
//assign hpstate_en_e =
// thread0_e ? tlu_lsu_hpstate_en[0] :
// thread1_e ? tlu_lsu_hpstate_en[1] :
// thread2_e ? tlu_lsu_hpstate_en[2] :
// tlu_lsu_hpstate_en[3] ;
mux4ds #(1) hpstate_en_e_mux (
.in0 (hpstate_en_d1[0]),
.in1 (hpstate_en_d1[1]),
.in2 (hpstate_en_d1[2]),
.in3 (hpstate_en_d1[3]),
.sel0 (thread0_e),
.sel1 (thread1_e),
.sel2 (thread2_e),
.sel3 (thread3_e),
.dout (hpstate_en_e)
);
dff_s #(2) hpv_stgm (
.din ({hpv_priv_e, hpstate_en_e}),
.q ({hpv_priv_m, hpstate_en_m}),
.clk (clk),
.se (se), .si (), .so ()
);
//dff #(2) hpv_stgg (
// .din ({hpv_priv_m, hpstate_en_m}),
// .q ({hpv_priv, hpstate_en}),
// .clk (clk),
// .se (se), .si (), .so ()
// );
/*assign priv_action = (ld_inst_vld_unflushed | st_inst_vld_unflushed) & ~lsu_asi_state[7] &
~pstate_priv & ~(hpv_priv & hpstate_en) & lsu_alt_space_g ;*/
// Generate a stage earlier
//SC assign priv_action_m = (ld_inst_vld_m | st_inst_vld_m) & ~lsu_dctl_asi_state_m[7] &
//SC ~pstate_priv_m & ~(hpv_priv_m & hpstate_en_m) & lsu_alt_space_m ;
//SC dff pact_stgg (
//SC .din (priv_action_m),
//SC .q (priv_action),
//SC .clk (clk),
//SC .se (se), .si (), .so ()
//SC );
// Take data_access exception if supervisor uses hypervisor asi
//SC wire hpv_asi_range ;
//SC assign hpv_asi_range =
//SC ~lsu_asi_state[7] & (
//SC (~lsu_asi_state[6] & lsu_asi_state[5] & lsu_asi_state[4]) | // 0x3?
//SC ( lsu_asi_state[6])); // 0x4?,5?,6?,7?
// Take data_access exception if supervisor uses hypervisor asi
//SC `ifdef SPARC_HPV_EN
//SC assign spv_use_hpv = (ld_inst_vld_unflushed | st_inst_vld_unflushed) &
//SC hpv_asi_range &
//SC //~lsu_asi_state[7] & lsu_asi_state[6] & lsu_asi_state[5] & // 0x30-0x7f
//SC pstate_priv & ~hpv_priv & lsu_alt_space_g ;
//SC `else
//SC assign spv_use_hpv = 1'b0 ;
//SC `endif
// EARLY TRAPS
// memory address not aligned
//SC wire qw_align_addr,blk_align_addr ;
//SC assign hw_align_addr = ~ldst_va_m[0] ; // half-word addr
//SC assign wd_align_addr = ~ldst_va_m[1] & ~ldst_va_m[0] ; // word addr
//SC assign dw_align_addr = ~ldst_va_m[2] & ~ldst_va_m[1] & ~ldst_va_m[0] ; // dw addr
//SC assign qw_align_addr = ~ldst_va_m[3] & ~ldst_va_m[2] & ~ldst_va_m[1] & ~ldst_va_m[0] ; // qw addr
//SC assign blk_align_addr =
//SC ~ldst_va_m[5] & ~ldst_va_m[4] & ~ldst_va_m[3] &
//SC ~ldst_va_m[2] & ~ldst_va_m[1] & ~ldst_va_m[0] ; // 64B aligned addr for block ld/st
//assign byte_size = ~ldst_sz_m[1] & ~ldst_sz_m[0] ; // byte size
//assign hw_size = ~ldst_sz_m[1] & ldst_sz_m[0] ; // half-word size
//assign wd_size = ldst_sz_m[1] & ~ldst_sz_m[0] ; // word size
//assign dw_size = ldst_sz_m[1] & ldst_sz_m[0] ; // double-word size
//assign byte_size = byte_m;
assign hw_size = hword_m;
assign wd_size = word_m;
assign dw_size = dword_m;
//SC assign mem_addr_not_align
//SC = ((hw_size & ~hw_align_addr) | // half-word check
//SC (wd_size & ~wd_align_addr) | // word check
//SC (dw_size & ~dw_align_addr) | // double word check
//SC ((quad_asi_m | binit_quad_asi_m) & lsu_alt_space_m & ldst_dbl_m & ~qw_align_addr) | // quad word check
//SC (blk_asi_m & lsu_alt_space_m & fp_ldst_m & ldst_dbl_m & ~blk_align_addr)) & // 64B blk ld/st check
//SC //(blk_asi_m & lsu_alt_space_m & blk_asi_m & ~blk_align_addr)) & // 64B blk ld/st check
//SC (ld_inst_vld_m | st_inst_vld_m) ;
//SC assign stdf_maddr_not_align
//SC = st_inst_vld_m & fp_ldst_m & ldst_dbl_m & wd_align_addr & ~dw_align_addr ;
//SC assign lddf_maddr_not_align
//SC = ld_inst_vld_m & fp_ldst_m & ldst_dbl_m & wd_align_addr & ~dw_align_addr ;
// internal asi access by ld/st other than ldxa/stxa/lddfa/stdfa.
// qual with ldst_dbl_m needed. lda and stda should take trap if accessing internal asi.
//SC assign asi_internal_non_xdw
//SC = (st_inst_vld_m | ld_inst_vld_m) & lsu_alt_space_m & asi_internal_m & ~(dw_size & ~ldst_dbl_m) ;
// asi related
// rd-only mmu asi requiring va decode.
//SC wire mmu_rd_only_asi_wva_m ;
//SC assign mmu_rd_only_asi_wva_m =
//SC ((lsu_dctl_asi_state_m[7:0]==8'h58) & (
//SC (ldst_va_m[8:0] == 9'h000) | // dtag_target
//SC (ldst_va_m[8:0] == 9'h020))) | // dsync_far
//SC ((lsu_dctl_asi_state_m[7:0]==8'h50) &
//SC (ldst_va_m[8:0] == 9'h000)) ; // itag_target
//SC assign wr_to_rd_only_asi =
//SC (mmu_rd_only_asi_wva_m |// mmu with non-unique asi
//SC mmu_rd_only_asi_m | // mmu with unique asi
//SC rd_only_asi_m) // non mmu
//SC & st_inst_vld_m & lsu_alt_space_m ;
//SC assign rd_of_wr_only_asi = wr_only_asi_m & ld_inst_vld_m & lsu_alt_space_m ;
//SC assign unimp_asi_used = unimp_asi_m & (ld_inst_vld_m | st_inst_vld_m) & lsu_alt_space_m ;
//assign asi_related_trap_m = wr_to_rd_only_asi | rd_of_wr_only_asi | unimp_asi_used | asi_internal_non_xdw ;
//SC assign early_trap_vld_m = stdf_maddr_not_align | lddf_maddr_not_align | mem_addr_not_align ;
//SC assign lsu_tlu_misalign_addr_ldst_atm_m = early_trap_vld_m ;
// mux select order must be maintained
//SC assign early_ttype_m[8:0] =
//SC stdf_maddr_not_align ? 9'h036 :
//SC lddf_maddr_not_align ? 9'h035 :
//SC mem_addr_not_align ? 9'h034 : 9'hxxx ;
//SC dff #(11) etrp_stgg (
//SC .din ({early_ttype_m[8:0],early_trap_vld_m,asi_related_trap_m}),
//SC .q ({early_ttype_g[8:0],early_trap_vld_g,asi_related_trap_g}),
//SC .clk (clk),
//SC .se (se), .si (), .so ()
//SC );
//SC wire nceen_pipe_g ;
//SC assign nceen_pipe_g =
//SC (thread0_g & ifu_lsu_nceen[0]) | (thread1_g & ifu_lsu_nceen[1]) |
//SC (thread2_g & ifu_lsu_nceen[2]) | (thread3_g & ifu_lsu_nceen[3]) ;
//SC wire nceen_fill_e,nceen_fill_m,nceen_fill_g ;
//SC assign nceen_fill_e =
//SC (dfill_thread0 & ifu_lsu_nceen[0]) | (dfill_thread1 & ifu_lsu_nceen[1]) |
//SC (dfill_thread2 & ifu_lsu_nceen[2]) | (dfill_thread3 & ifu_lsu_nceen[3]) ;
//SC dff #(1) nce_stgm (
//SC .din (nceen_fill_e),
//SC .q (nceen_fill_m),
//SC .clk (clk),
//SC .se (se), .si (), .so ()
//SC );
//SC dff #(1) nce_stgg (
//SC .din (nceen_fill_m),
//SC .q (nceen_fill_g),
//SC .clk (clk),
//SC .se (se), .si (), .so ()
//SC );
//SC assign daccess_error = 1'b0 ;
// Commented out currently for timing reasons. This needs to be
// rolled into the ttype_vld sent to the tlu, but can be left out
// of the flush sent to the remaining units.
/*((tte_data_perror_unc) & nceen_pipe_g & // on xslate
~(early_trap_vld_g | priv_action | va_wtchpt_match | dmmu_miss_g)) |
tlb_asi_unc_err_g | // asi read
(unc_err_trap_g & nceen_fill_g) | // cache data
tlb_daccess_error_g ; // tlb not writeable */
//SC assign lsu_tlu_async_dacc_err_g = unc_err_trap_g | tlb_asi_unc_err_g ;
//SC assign lsu_tlu_dmmu_miss_g = dmmu_miss_g ;
wire cam_real_m ;
dff_s real_stgm (
.din (lsu_dtlb_cam_real_e),
.q (cam_real_m),
.clk (clk),
.se (se), .si (), .so ()
);
// dff real_stgg (
// .din (cam_real_m),
// .q (cam_real_g),
// .clk (clk),
// .se (se), .si (), .so ()
// );
assign lsu_tlu_nonalt_ldst_m = (st_inst_vld_m | ld_inst_vld_m) & ~lsu_alt_space_m ;
assign lsu_tlu_xslating_ldst_m = (st_inst_vld_m | ld_inst_vld_m) &
(((~asi_internal_m & recognized_asi_m) & lsu_alt_space_m) | // Bug 4327
~lsu_alt_space_m) ;
assign ctxt_sel_e[0] = thread_pctxt ;
assign ctxt_sel_e[1] = thread_sctxt ;
assign ctxt_sel_e[2] =
thread_nctxt |
(~(thread_pctxt | thread_sctxt) & // default to nucleus - translating asi
~(alt_space_e & (asi_internal_e | ~recognized_asi_e ))) ; //bug3660
// nontranslating asi to select 11 in CT
// field of dsfsr.
dff_s #(3) ctxsel (
.din (ctxt_sel_e[2:0]),
.q (lsu_tlu_ctxt_sel_m[2:0]),
.clk (clk),
.se (se), .si (), .so ()
);
assign lsu_tlu_nucleus_ctxt_m = lsu_tlu_ctxt_sel_m[2] ;
assign lsu_tlu_write_op_m = st_inst_vld_m | atomic_m ;
// va_oor_m check needs to be in case of bypass, pstate.am=1, internal and illegal asi.
// pstate.am squashing is done locally in tlu.
assign lsu_tlu_squash_va_oor_m =
dtlb_bypass_m | // bypass
//sta_internal_m | lda_internal_m | // internal asi
(asi_internal_m & lsu_alt_space_m) | // Bug 5156
(~recognized_asi_tmp & lsu_alt_space_m) ; // illegal asi // Timing change.
assign lsu_squash_va_oor_m = lsu_tlu_squash_va_oor_m;
//=========================================================================================
// Generate Flush Pipe
//=========================================================================================
//SC wire other_flush_pipe_w ;
// lsu_tlu_ttype_vld needs to be optimized in terms of timing.
//SC assign other_flush_pipe_w = tlu_early_flush_pipe_w | (lsu_tlu_ttype_vld_m2 & lsu_inst_vld_w);
//SC assign lsu_ifu_flush_pipe_w = other_flush_pipe_w ;
//SC assign lsu_exu_flush_pipe_w = other_flush_pipe_w ;
//SC assign lsu_ffu_flush_pipe_w = other_flush_pipe_w ;
//SC //assign lsu_flush_pipe_w = other_flush_pipe_w | ifu_tlu_flush_w ;
//=========================================================================================
// Early Traps to SPU
//=========================================================================================
// detect st to ma/strm sync - data-access exception.
//SC wire st_to_sync_dexcp_m ;
// qual with alt_space not required - spu will do it.
//SC assign st_to_sync_dexcp_m =
//SC strm_asi_m & ((ldst_va_m[7:0] == 8'ha0) | (ldst_va_m[7:0] == 8'h68)) & st_inst_vld_m ;
//SC wire spu_early_flush_m ;
//SC assign spu_early_flush_m =
//SC priv_action_m |
//SC mem_addr_not_align |
//SC st_to_sync_dexcp_m ;
//SC dff eflushspu_g (
//SC .din (spu_early_flush_m),
//SC .q (lsu_spu_early_flush_g),
//SC .clk (clk),
//SC .se (se), .si (), .so ()
//SC );
//SC dff eflushtlu_g (
//SC .din (spu_early_flush_m),
//SC .q (lsu_tlu_early_flush_w),
//SC .clk (clk),
//SC .se (se), .si (), .so ()
//SC );
//=========================================================================================
// Parity Error Checking
//=========================================================================================
// DCache Parity Error
// - Parity Check is done for entire 64b. No attempt is made to match on size. A
// parity error will force a miss and refetch a line to the same way of the cache.
// - Logging of error is done in g-stage of issue.
// - Trap taken on data return
wire dcache_perr_en ;
assign dcache_perr_en =
dcache_enable_g & ~(asi_internal_g & lsu_alt_space_g) &
~atomic_g &
// dcache_rd_parity_err qualified with cache_way_hit - could be x.
(lsu_dtlb_bypass_g | (~lsu_dtlb_bypass_g & tlb_cam_hit_g)) ;
assign dcache_rd_parity_error = dcache_rparity_err_wb & dcache_perr_en ;
// dtag parity error gets priority over dcache priority.
assign lsu_dcache_data_perror_g =
dcache_rd_parity_error & ld_inst_vld_unflushed & lsu_inst_vld_w & ~dtag_perror_g &
dcache_perr_en ;
// dcache_enable_g & ~(asi_internal_g & lsu_alt_space_g) &
// ~atomic_g ;
// DTLB Parity Errors.
// ASI read of Tag/Data :
// - uncorrectible error
// - logging occurs on read.
// - precise trap is taken when ldxa completes if nceen set.
// - if not set then ldxa is allowed to complete.
// CAM Read of Tag/Data :
// - correctible if locked bit not set.
// - takes disrupting trap later.
// - uncorrectible if locked bit set.
// - both are treated as precise traps.
// - if errors not enabled, then load completes as if hit in L1.
// ** TLB error will cause a trap which will preclude concurrent dcache,dtag **
// ** parity errors. **
//SC assign tte_data_parity_error =
//SC tlb_rd_tte_data_parity ^ lsu_rd_tte_data_parity ;
//SC assign tte_tag_parity_error =
//SC tlb_rd_tte_tag_parity ^ lsu_rd_tte_tag_parity ;
// cam related tte data parity error - error assumed correctible if locked
// bit is not set. Will cause a dmmu_miss for correction.
// qualify with cam_hit ??
//SC assign tte_data_perror_corr =
//SC tte_data_parity_error & ~tlb_rd_tte_data_locked & tlb_tte_vld_g &
//SC (ld_inst_vld_unflushed | st_inst_vld_unflushed) & lsu_inst_vld_w ;
// same as above except error is treated as uncorrectible. This is to be posted to
// error status register which will cause a disrupting trap later.
//SC assign tte_data_perror_unc =
//SC tte_data_parity_error & tlb_rd_tte_data_locked & tlb_tte_vld_g &
//SC (ld_inst_vld_unflushed | st_inst_vld_unflushed) & lsu_inst_vld_w ;
// Asi rd parity error detection
//SC assign asi_tte_data_perror =
//SC tte_data_parity_error & data_rd_vld_g ;
// For data tte read, both tag and data arrays are read.
// Parity error on asi read of tag should not be reported.
//SC assign asi_tte_tag_perror =
//SC tte_tag_parity_error & tag_rd_vld_g & ~data_rd_vld_g ;
//SC assign lsu_tlu_asi_rd_unc = asi_tte_data_perror | asi_tte_tag_perror ;
// asi rd parity errors need to be reported thru asi bus
/*assign lsu_ifu_tlb_data_ce = tte_data_perror_corr ;
assign lsu_ifu_tlb_data_ue = tte_data_perror_unc | asi_tte_data_perror ;
assign lsu_ifu_tlb_tag_ue = asi_tte_tag_perror ; */
//SC wire tlb_data_ue_g ;
//SC assign tlb_data_ue_g = tte_data_perror_unc | asi_tte_data_perror ;
//SC dff #(3) terr_stgd1 (
//SC .din ({tte_data_perror_corr,tlb_data_ue_g,asi_tte_tag_perror}),
//SC .q ({lsu_ifu_tlb_data_ce,lsu_ifu_tlb_data_ue,lsu_ifu_tlb_tag_ue}),
//SC .clk (clk),
//SC .se (se), .si (), .so ()
//SC );
// Dtag Parity Error
// - corrected thru special mechanism
// - correctible error
// - Trap taken on data return
// move parity error calculation to g stage
dff_s #(4) dva_vld_g_ff (
.din (dva_vld_m[3:0]),
.q (dva_vld_g[3:0]),
.clk (clk),
.se (se), .si (), .so ()
);
assign dva_vld_m_bf[3:0] = dva_vld_m[3:0];
wire dtag_perr_en ;
assign dtag_perr_en =
dcache_enable_g & ~(asi_internal_g & lsu_alt_space_g) & // Bug 3541
~(lsu_alt_space_g & blk_asi_g) & // Bug 3926.
~atomic_g & // Bug 4274,4297
~pref_inst_g ; // Bug 5046
assign dtag_parity_error[0] =
lsu_rd_dtag_parity_g[0] & dva_vld_g[0] & dtag_perr_en;
assign dtag_parity_error[1] =
lsu_rd_dtag_parity_g[1] & dva_vld_g[1] & dtag_perr_en ;
assign dtag_parity_error[2] =
lsu_rd_dtag_parity_g[2] & dva_vld_g[2] & dtag_perr_en ;
assign dtag_parity_error[3] =
lsu_rd_dtag_parity_g[3] & dva_vld_g[3] & dtag_perr_en ;
assign dtag_perror_g = |dtag_parity_error[3:0] ;
assign lsu_dcache_tag_perror_g =
(|dtag_parity_error[3:0]) & ld_inst_vld_unflushed & lsu_inst_vld_w &
// Correction pkt should not be generated to io.
~(tlb_pgnum[39] & (lsu_dtlb_bypass_g | (~lsu_dtlb_bypass_g & tlb_cam_hit_g))) ;
// (|dtag_parity_error[3:0]) & ld_inst_vld_unflushed & lsu_inst_vld_w &
// ~(lsu_alt_space_g & blk_asi_g) & // Bug 3926.
// // Correction pkt should not be generated to io.
// ~(tlb_pgnum[39] & (lsu_dtlb_bypass_g | (~lsu_dtlb_bypass_g & tlb_cam_hit_g))) &
// ~atomic_g ; // Bug 4274,4297
//=========================================================================================
// Error Related Traps
//=========================================================================================
//bug6382/eco6621
dff_s #(2) derrtrp_stgm (
.din ({lsu_cpx_ld_dtag_perror_e & ~ignore_fill, lsu_cpx_ld_dcache_perror_e & ~ignore_fill}),
.q ({dtag_error_m,dcache_error_m}),
.clk (clk),
.se (se), .si (), .so ()
);
dff_s #(2) derrtrp_stgg (
.din ({dtag_error_m,dcache_error_m}),
.q ({dtag_error_g,dcache_error_g}),
.clk (clk),
.se (se), .si (), .so ()
);
dff_s #(2) derrtrp_stgw2 (
.din ({dtag_error_g,dcache_error_g}),
.q ({dtag_error_w2,dcache_error_w2}),
.clk (clk),
.se (se), .si (), .so ()
);
assign lsu_ifu_dcache_data_perror = dcache_error_w2 & ~bld_squash_err_w2; //bug6382/eco6621
assign lsu_ifu_dcache_tag_perror = dtag_error_w2 ;
assign l2_unc_error_e = lsu_cpx_pkt_ld_err[1] & l2fill_vld_e & ~ignore_fill ; // Bug 4998
assign l2_corr_error_e = lsu_cpx_pkt_ld_err[0] & l2fill_vld_e & ~ignore_fill ;
dff_s #(2) lerrtrp_stgm (
.din ({l2_unc_error_e,l2_corr_error_e}),
.q ({l2_unc_error_m,l2_corr_error_m}),
.clk (clk),
.se (se), .si (), .so ()
);
dff_s #(2) lerrtrp_stgg (
.din ({l2_unc_error_m,l2_corr_error_m}),
.q ({l2_unc_error_g,l2_corr_error_g}),
.clk (clk),
.se (se), .si (), .so ()
);
dff_s #(2) lerrtrp_stgw2 (
.din ({l2_unc_error_g,l2_corr_error_g}),
.q ({l2_unc_error_w2,l2_corr_error_w2}),
.clk (clk),
.se (se), .si (), .so ()
);
assign lsu_ifu_l2_unc_error = // Bug 4315
(l2_unc_error_w2 | bld_unc_err_pend_w2) & ~lsu_ifu_err_addr_b39 & ~bld_squash_err_w2 ;
assign lsu_ifu_l2_corr_error =
(l2_corr_error_w2 | bld_corr_err_pend_w2) & ~bld_squash_err_w2 ;
wire fill_err_trap_e ;
//assign unc_err_trap_e =
assign fill_err_trap_e =
(lsu_cpx_pkt_ld_err[1] & l2fill_vld_e) ;
/*(lsu_cpx_atm_st_err[1] & lsu_atm_st_cmplt_e)) &
((dfill_thread0 & ifu_lsu_nceen[0]) |
(dfill_thread1 & ifu_lsu_nceen[1]) |
(dfill_thread2 & ifu_lsu_nceen[2]) |
(dfill_thread3 & ifu_lsu_nceen[3])) ; */ // Bug 3624
assign unc_err_trap_e = fill_err_trap_e ;
/*assign corr_err_trap_e =
((lsu_cpx_pkt_ld_err[0] | lsu_cpx_ld_dtag_perror_e | lsu_cpx_ld_dcache_perror_e) &
l2fill_vld_e) |
(lsu_cpx_atm_st_err[0] & lsu_atm_st_cmplt_e)) &
& ~unc_err_trap_e &
((dfill_thread0 & ifu_lsu_ceen[0]) |
(dfill_thread1 & ifu_lsu_ceen[1]) |
(dfill_thread2 & ifu_lsu_ceen[2]) |
(dfill_thread3 & ifu_lsu_ceen[3])) ; */
dff_s #(1) errtrp_stgm (
.din ({unc_err_trap_e}),
.q ({unc_err_trap_m}),
.clk (clk),
.se (se), .si (), .so ()
);
dff_s #(1) errtrp_stgg (
.din ({unc_err_trap_m}),
.q ({unc_err_trap_g}),
.clk (clk),
.se (se), .si (), .so ()
);
// The tlu should source demap_thrid for all tlb operations !!!
dff_s #(2) filla_stgm (
.din ({lsu_dfill_tid_e[1:0]}),
.q ({dfill_tid_m[1:0]}),
.clk (clk),
.se (se), .si (), .so ()
);
dff_s #(2) filla_stgg (
.din ({dfill_tid_m[1:0]}),
.q ({dfill_tid_g[1:0]}),
.clk (clk),
.se (se), .si (), .so ()
);
//=========================================================================================
// LSU to IRF Data Bypass Control
//=========================================================================================
assign spu_trap = spu_lsu_unc_error_w2 ;
assign spu_trap0 = spu_trap & spu_ldxa_thread0_w2 ;
assign spu_trap1 = spu_trap & spu_ldxa_thread1_w2 ;
assign spu_trap2 = spu_trap & spu_ldxa_thread2_w2 ;
assign spu_trap3 = spu_trap & spu_ldxa_thread3_w2 ;
assign spu_ttype[6:0] = spu_lsu_int_w2 ? 7'h70 : 7'h32 ;
dff_s #(2) lfraw_stgw2 (
.din ({ld_inst_vld_g,fp_ldst_g}),
.q ({ld_inst_vld_w2,fp_ldst_w2}),
.clk (clk),
.se (se), .si (), .so ()
);
dff_s #(2) lfraw_stgw3 (
.din ({ld_stb_full_raw_w2, ld_inst_vld_w2}),
.q ({ld_stb_full_raw_w3, ld_inst_vld_w3}),
.clk (clk),
.se (se), .si (), .so ()
);
// Delay all ldbyp*vld_en by a cycle for write of unc error
//dff #(4) lbypen_stgd1 (
// .din ({ldbyp0_vld_en,ldbyp1_vld_en,ldbyp2_vld_en,ldbyp3_vld_en}),
// .q ({ldbyp0_vld_en_d1,ldbyp1_vld_en_d1,ldbyp2_vld_en_d1,ldbyp3_vld_en_d1}),
// .clk (clk),
// .se (se), .si (), .so ()
// );
wire fp_ldst_thrd0_w2,fp_ldst_thrd1_w2,fp_ldst_thrd2_w2,fp_ldst_thrd3_w2 ;
wire fp_ldst_thrd0_w3,fp_ldst_thrd1_w3,fp_ldst_thrd2_w3,fp_ldst_thrd3_w3 ;
wire fp_ldst_thrd0_w4,fp_ldst_thrd1_w4,fp_ldst_thrd2_w4,fp_ldst_thrd3_w4 ;
wire fp_ldst_thrd0_w5,fp_ldst_thrd1_w5,fp_ldst_thrd2_w5,fp_ldst_thrd3_w5 ;
//RAW read STB at W3 (changed from W2)
dff_s #(4) fp_ldst_stg_w3 (
.din ({fp_ldst_thrd0_w2,fp_ldst_thrd1_w2,fp_ldst_thrd2_w2,fp_ldst_thrd3_w2}),
.q ({fp_ldst_thrd0_w3,fp_ldst_thrd1_w3,fp_ldst_thrd2_w3,fp_ldst_thrd3_w3}),
.clk (clk),
.se (se), .si (), .so ()
);
dff_s #(4) fp_ldst_stg_w4 (
.din ({fp_ldst_thrd0_w3,fp_ldst_thrd1_w3,fp_ldst_thrd2_w3,fp_ldst_thrd3_w3}),
.q ({fp_ldst_thrd0_w4,fp_ldst_thrd1_w4,fp_ldst_thrd2_w4,fp_ldst_thrd3_w4}),
.clk (clk),
.se (se), .si (), .so ()
);
dff_s #(4) fp_ldst_stg_w5 (
.din ({fp_ldst_thrd0_w4,fp_ldst_thrd1_w4,fp_ldst_thrd2_w4,fp_ldst_thrd3_w4}),
.q ({fp_ldst_thrd0_w5,fp_ldst_thrd1_w5,fp_ldst_thrd2_w5,fp_ldst_thrd3_w5}),
.clk (clk),
.se (se), .si (), .so ()
);
// THREAD 0
wire tte_data_perror_unc_w2,asi_tte_data_perror_w2,asi_tte_tag_perror_w2 ;
// if nceen/ceen=0, then tte_data_perror* are not logged for trap generation. Earlier error-reporting
// is however never screened off.
// asi_tte* however has to be logged in order to report errors thru the asiQ. Traps must be squashed.
dff_s #(3) ltlbrd_w2 (
.din ({tte_data_perror_unc_en,asi_tte_data_perror,asi_tte_tag_perror}),
.q ({tte_data_perror_unc_w2,asi_tte_data_perror_w2,asi_tte_tag_perror_w2}),
.clk (clk),
.se (se), .si (), .so ()
);
// Error Table for Queue
// ** In all cases; squash writes to irf.
// | Error Reporting | Trap ? |
// ifu_lsu_asi_rd_unc | NA;done by ifu | daccess-error |
// tte_data_perror_unc_w2 | sync;in pipe | daccess-error |
// tte_data_perror_corr_w2 | sync;in pipe | dmmu-miss | --> NA !! all unc.
// asi_tte_data_perror_w2 | async;out of Q | daccess-error |
// asi_tte_tag_perror_w2 | async;out of Q | daccess-error |
wire [3:0] tlb_err_en_w2 ;
// used for xslate errors - enable queues
//assign tlb_err_en_w2[0] = (tte_data_perror_unc_w2 | tte_data_perror_corr_w2) & thread0_w2 ;
assign tlb_err_en_w2[0] = tte_data_perror_unc_w2 & thread0_w2 ;
assign tlb_err_en_w2[1] = tte_data_perror_unc_w2 & thread1_w2 ;
assign tlb_err_en_w2[2] = tte_data_perror_unc_w2 & thread2_w2 ;
assign tlb_err_en_w2[3] = tte_data_perror_unc_w2 & thread3_w2 ;
assign ldbyp0_vld_rst =
(reset | (ld_thrd_byp_sel_e[0])) |
atm_st_cmplt0 ; // Bug 4048
// thread qualification required.
//assign ldbyp0_vld_en = (lmq_byp_data_en_w2[0] &
// ~(|lmq_byp_data_sel0[2:1])) // do not set vld for cas/stdbl
// | spu_trap0 ;
wire atm_ld_w_uerr ;
assign atm_ld_w_uerr = l2fill_vld_e & lsu_cpx_pkt_atm_st_cmplt & lsu_cpx_pkt_ld_err[1] ;
//bug6525 notes
// spu ldxa and spu trap can async with the main pipe, and cause more than one ldbyp*_vld_en asserted
// at the same cycle
assign ldbyp0_vld_en = lmq_byp_data_raw_sel_d2[0] | //ld hit stb RAW bypass
lmq_byp_data_sel0[3] | //ldxa (ifu, spu*, lsu)
(atm_ld_w_uerr & lsu_nceen_d1[0] & dfill_thread0) | //atomic
lmq_byp_data_fmx_sel[0] | //tlu ldxa
tlb_err_en_w2[0] | //tlb parity err
spu_trap0 ; //spu trap*
assign fp_ldst_thrd0_w2 = fp_ldst_w2 & thread0_w2 & ld_inst_vld_w2 ;
// ld valid
wire ldbyp0_vld_tmp ;
dffre_s #(1) ldbyp0_vld_ff (
.din (ldbyp0_vld_en),
.q (ldbyp0_vld_tmp),
.rst (ldbyp0_vld_rst), .en (ldbyp0_vld_en),
.clk (clk),
.se (se), .si (), .so ()
);
// Bug 5379 - make ld ue invisible in q until atm st ack resets.
assign ldbyp0_vld = ldbyp0_vld_tmp & ~pend_atm_ld_ue[0] ;
// assumes that rw_index is not reset at mmu.
wire [6:0] misc_data_in ;
wire [6:0] misc_data0,misc_data1,misc_data2,misc_data3 ;
wire misc_sel ;
wire [5:0] rw_index_d1 ;
dff_s #(6) rwind_d1 (
.din (tlu_dtlb_rw_index_g[5:0]),
.q (rw_index_d1[5:0]),
.clk (clk),
.se (se), .si (), .so ()
);
assign misc_sel = asi_tte_data_perror_w2 | asi_tte_tag_perror_w2 ;
assign misc_data_in[6:0] = misc_sel ? {1'b0,rw_index_d1[5:0]} : spu_ttype[6:0] ;
dffe_s #(9) ldbyp0_other_ff (
.din ({fp_ldst_thrd0_w5,spu_trap0,misc_data_in[6:0]}), //bug6525 fix2
.q ({ldbyp0_fpld,spubyp0_trap,misc_data0[6:0]}),
.en (ldbyp0_vld_en),
.clk (clk),
.se (se), .si (), .so ()
);
dffre_s #(5) ldbyp0_err_ff (
.din ({tte_data_perror_unc_w2,atm_ld_w_uerr,
asi_tte_data_perror_w2,asi_tte_tag_perror_w2,ifu_lsu_asi_rd_unc}),
.q ({cam_perr_unc0,pend_atm_ld_ue[0],asi_data_perr0,asi_tag_perr0,
ifu_unc_err0}),
.rst (ldbyp0_vld_rst), .en (ldbyp0_vld_en & ~spu_trap0 & ~lmq_byp_ldxa_sel0[1]), //bug6525 fix2
.clk (clk),
.se (se), .si (), .so ()
);
//assign ldbyp0_unc_err = ldbyp0_unc_err_q & ifu_lsu_nceen[0] ;
// THREAD 1
assign ldbyp1_vld_rst =
(reset | (ld_thrd_byp_sel_e[1])) |
atm_st_cmplt1 ; // Bug 4048
assign fp_ldst_thrd1_w2 = fp_ldst_w2 & thread1_w2 & ld_inst_vld_w2 ;
// thread qualification required.
//assign ldbyp1_vld_en = (lmq_byp_data_en_w2[1] &
// ~(|lmq_byp_data_sel1[2:1])) | // do not set vld for cas/stdbl
// | spu_trap1 ;
assign ldbyp1_vld_en = lmq_byp_data_raw_sel_d2[1] |
lmq_byp_data_sel1[3] |
(atm_ld_w_uerr & lsu_nceen_d1[1] & dfill_thread1) |
lmq_byp_data_fmx_sel[1] |
tlb_err_en_w2[1] |
spu_trap1 ;
// ld valid
wire ldbyp1_vld_tmp ;
dffre_s #(1) ldbyp1_vld_ff (
.din (ldbyp1_vld_en),
.q (ldbyp1_vld_tmp),
.rst (ldbyp1_vld_rst), .en (ldbyp1_vld_en),
.clk (clk),
.se (se), .si (), .so ()
);
assign ldbyp1_vld = ldbyp1_vld_tmp & ~pend_atm_ld_ue[1] ;
dffe_s #(9) ldbyp1_other_ff (
.din ({fp_ldst_thrd1_w5,spu_trap1,misc_data_in[6:0]}), //bug6525 fix2
.q ({ldbyp1_fpld,spubyp1_trap,misc_data1[6:0]}),
.en (ldbyp1_vld_en),
.clk (clk),
.se (se), .si (), .so ()
);
// The tlb rd unc errors are delayed a cycle wrt to ldxa_data
// No reset required
dffre_s #(5) ldbyp1_err_ff (
.din ({tte_data_perror_unc_w2,atm_ld_w_uerr,
asi_tte_data_perror_w2,asi_tte_tag_perror_w2,ifu_lsu_asi_rd_unc}),
.q ({cam_perr_unc1,pend_atm_ld_ue[1],asi_data_perr1,asi_tag_perr1,
ifu_unc_err1}),
.rst (ldbyp1_vld_rst), .en (ldbyp1_vld_en & ~spu_trap1 & ~lmq_byp_ldxa_sel1[1]), //bug6525 fix2
.clk (clk),
.se (se), .si (), .so ()
);
//assign ldbyp1_unc_err = ldbyp1_unc_err_q & ifu_lsu_nceen[1] ;
// THREAD 2
assign ldbyp2_vld_rst =
(reset | (ld_thrd_byp_sel_e[2])) |
atm_st_cmplt2 ; // Bug 4048
// thread qualification required.
//assign ldbyp2_vld_en = (lmq_byp_data_en_w2[2] &
// ~(|lmq_byp_data_sel2[2:1])) | // do not set vld for cas/stdbl
// spu_trap2 ;
assign ldbyp2_vld_en = lmq_byp_data_raw_sel_d2[2] |
lmq_byp_data_sel2[3] |
(atm_ld_w_uerr & lsu_nceen_d1[2] & dfill_thread2) |
lmq_byp_data_fmx_sel[2] |
tlb_err_en_w2[2] |
spu_trap2 ;
assign fp_ldst_thrd2_w2 = fp_ldst_w2 & thread2_w2 & ld_inst_vld_w2 ;
// ld valid
wire ldbyp2_vld_tmp ;
dffre_s #(1) ldbyp2_vld_ff (
.din (ldbyp2_vld_en),
.q (ldbyp2_vld_tmp),
.rst (ldbyp2_vld_rst), .en (ldbyp2_vld_en),
.clk (clk),
.se (se), .si (), .so ()
);
assign ldbyp2_vld = ldbyp2_vld_tmp & ~pend_atm_ld_ue[2] ;
dffe_s #(9) ldbyp2_other_ff (
.din ({fp_ldst_thrd2_w5,spu_trap2,misc_data_in[6:0]}), //bug6525 fix2
.q ({ldbyp2_fpld,spubyp2_trap,misc_data2[6:0]}),
.en (ldbyp2_vld_en),
.clk (clk),
.se (se), .si (), .so ()
);
dffre_s #(5) ldbyp2_err_ff (
.din ({tte_data_perror_unc_w2, atm_ld_w_uerr,
asi_tte_data_perror_w2,asi_tte_tag_perror_w2,ifu_lsu_asi_rd_unc}),
.q ({cam_perr_unc2,pend_atm_ld_ue[2],asi_data_perr2,asi_tag_perr2,
ifu_unc_err2}),
.rst (ldbyp2_vld_rst), .en (ldbyp2_vld_en & ~spu_trap2 & ~lmq_byp_ldxa_sel2[1]), //bug6525 fix2
.clk (clk),
.se (se), .si (), .so ()
);
//assign ldbyp2_unc_err = ldbyp2_unc_err_q & ifu_lsu_nceen[2] ;
// THREAD 3
assign ldbyp3_vld_rst =
(reset | (ld_thrd_byp_sel_e[3])) |
atm_st_cmplt3 ; // Bug 4048
// thread qualification required.
//assign ldbyp3_vld_en = (lmq_byp_data_en_w2[3] &
// ~(|lmq_byp_data_sel3[2:1])) | // do not set vld for cas/stdbl
// | spu_trap3 ;
assign ldbyp3_vld_en = lmq_byp_data_raw_sel_d2[3] |
lmq_byp_data_sel3[3] |
(atm_ld_w_uerr & lsu_nceen_d1[3] & dfill_thread3) |
lmq_byp_data_fmx_sel[3] |
tlb_err_en_w2[3] |
spu_trap3 ;
assign fp_ldst_thrd3_w2 = fp_ldst_w2 & thread3_w2 & ld_inst_vld_w2 ;
// ld valid
wire ldbyp3_vld_tmp ;
dffre_s #(1) ldbyp3_vld_ff (
.din (ldbyp3_vld_en),
.q (ldbyp3_vld_tmp),
.rst (ldbyp3_vld_rst), .en (ldbyp3_vld_en),
.clk (clk),
.se (se), .si (), .so ()
);
assign ldbyp3_vld = ldbyp3_vld_tmp & ~pend_atm_ld_ue[3] ;
dffe_s #(9) ldbyp3_other_ff (
.din ({fp_ldst_thrd3_w5,spu_trap3,misc_data_in[6:0]}), //bug6525 fix2
.q ({ldbyp3_fpld,spubyp3_trap,misc_data3[6:0]}),
.en (ldbyp3_vld_en),
.clk (clk),
.se (se), .si (), .so ()
);
dffre_s #(5) ldbyp3_err_ff (
.din ({tte_data_perror_unc_w2,atm_ld_w_uerr,
asi_tte_data_perror_w2,asi_tte_tag_perror_w2,ifu_lsu_asi_rd_unc}),
.q ({cam_perr_unc3,pend_atm_ld_ue[3],asi_data_perr3,asi_tag_perr3,
ifu_unc_err3}),
.rst (ldbyp3_vld_rst), .en (ldbyp3_vld_en & ~spu_trap3 & ~lmq_byp_ldxa_sel3[1]), //bug6525 fix2
.clk (clk),
.se (se), .si (), .so ()
);
//assign ldbyp3_unc_err = ldbyp3_unc_err_q & ifu_lsu_nceen[3] ;
//assign ld_any_byp_data_vld =
// ldbyp0_vld | ldbyp1_vld | ldbyp2_vld | ldbyp3_vld ;
dff_s #(4) stgm_sqshcmplt (
.din (squash_byp_cmplt[3:0]),
.q (squash_byp_cmplt_m[3:0]),
.clk (clk),
.se (se), .si (), .so ()
);
dff_s #(4) stgg_sqshcmplt (
.din (squash_byp_cmplt_m[3:0]),
.q (squash_byp_cmplt_g[3:0]),
.clk (clk),
.se (se), .si (), .so ()
);
assign fpld_byp_data_vld =
(ld_thrd_byp_sel_g[0] & ldbyp0_fpld & ~squash_byp_cmplt_g[0]) | // Bug 4998
(ld_thrd_byp_sel_g[1] & ldbyp1_fpld & ~squash_byp_cmplt_g[1]) |
(ld_thrd_byp_sel_g[2] & ldbyp2_fpld & ~squash_byp_cmplt_g[2]) |
(ld_thrd_byp_sel_g[3] & ldbyp3_fpld & ~squash_byp_cmplt_g[3]) ;
//assign intld_byp_data_vld = |intld_byp_cmplt[3:0] ;
// squash for spu-trap situation.
assign intld_byp_data_vld_e =
//(intld_byp_cmplt[0] & ~spubyp0_trap) |
(intld_byp_cmplt[0]) | // squash now thru squash_byp_cmplt
(intld_byp_cmplt[1]) |
(intld_byp_cmplt[2]) |
(intld_byp_cmplt[3]) ;
dff_s stgm_ibvld (
.din (intld_byp_data_vld_e),
.q (intld_byp_data_vld_m),
.clk (clk),
.se (se), .si (), .so ()
);
// to be removed - intld_byp_data_vld in lsu_mon.v
/*
dff_s stgg_ibvld (
.din (intld_byp_data_vld_m),
.q (intld_byp_data_vld),
.clk (clk),
.se (se), .si (), .so ()
);
*/
assign spubyp_trap_active_e =
//(intld_byp_cmplt[0] & spubyp0_trap) | // Bug 4040
(ld_thrd_byp_sel_e[0] & spubyp0_trap) |
(ld_thrd_byp_sel_e[1] & spubyp1_trap) |
(ld_thrd_byp_sel_e[2] & spubyp2_trap) |
(ld_thrd_byp_sel_e[3] & spubyp3_trap) ;
dff_s stgm_strmtrp (
.din (spubyp_trap_active_e),
.q (spubyp_trap_active_m),
.clk (clk),
.se (se), .si (), .so ()
);
dff_s stgg_strmtrp (
.din (spubyp_trap_active_m),
.q (spubyp_trap_active_g),
.clk (clk),
.se (se), .si (), .so ()
);
assign spubyp0_ttype[6:0] = misc_data0[6:0] ;
assign spubyp1_ttype[6:0] = misc_data1[6:0] ;
assign spubyp2_ttype[6:0] = misc_data2[6:0] ;
assign spubyp3_ttype[6:0] = misc_data3[6:0] ;
mux4ds #(7) mux_spubyp_ttype (
.in0(spubyp0_ttype[6:0]),
.in1(spubyp1_ttype[6:0]),
.in2(spubyp2_ttype[6:0]),
.in3(spubyp3_ttype[6:0]),
.sel0(ld_thrd_byp_mxsel_m[0]),
.sel1(ld_thrd_byp_mxsel_m[1]),
.sel2(ld_thrd_byp_mxsel_m[2]),
.sel3(ld_thrd_byp_mxsel_m[3]),
.dout(spubyp_ttype[6:0])
);
assign intld_byp_cmplt[0] = (ld_thrd_byp_sel_e[0] & ~(ldbyp0_fpld | squash_byp_cmplt[0])) ;
assign intld_byp_cmplt[1] = (ld_thrd_byp_sel_e[1] & ~(ldbyp1_fpld | squash_byp_cmplt[1])) ;
assign intld_byp_cmplt[2] = (ld_thrd_byp_sel_e[2] & ~(ldbyp2_fpld | squash_byp_cmplt[2])) ;
assign intld_byp_cmplt[3] = (ld_thrd_byp_sel_e[3] & ~(ldbyp3_fpld | squash_byp_cmplt[3])) ;
dff_s #(2) stgm_l2fv (
.din ({l2fill_vld_e,lsu_l2fill_fpld_e}),
.q ({l2fill_vld_m,l2fill_fpld_m}),
.clk (clk),
.se (se), .si (), .so ()
);
dff_s #(2) stgg_l2fv (
.din ({l2fill_vld_m,l2fill_fpld_m}),
.q ({l2fill_vld_g,l2fill_fpld_g}),
.clk (clk),
.se (se), .si (), .so ()
);
// write to irf will need to be postphoned by a few cycles.
// may wish to find more bubbles by counting misses !!!
//assign lsu_irf_byp_data_src[0] = ld_inst_vld_unflushed ;
//assign lsu_irf_byp_data_src[1] = l2fill_vld_g ;
//assign lsu_irf_byp_data_src[2] =
// ~l2fill_vld_g & // no dfq fill
// ~ld_inst_vld_unflushed ; // no ld/st in pipe.
//~(ld_inst_vld_unflushed | st_inst_vld_unflushed) ; // no ld/st in pipe.
// Timing Change.
//ld_any_byp_data_vld ; // full raw bypasses data
// Store to load full raw bypassing. Plus ldxa data bypassing.
// ldxa-data may be bypassed asap if port available.
// ldxa/stb raw and atomics assumed to be mutually exclusive.
wire int_ldxa_vld ;
assign int_ldxa_vld = tlu_lsu_int_ldxa_vld_w2 & ~tlu_lsu_int_ld_ill_va_w2 ;
assign lmq_byp_data_fmx_sel[0] = int_ldxa_vld & thread0_w2 ;
assign lmq_byp_data_fmx_sel[1] = int_ldxa_vld & thread1_w2 ;
assign lmq_byp_data_fmx_sel[2] = int_ldxa_vld & thread2_w2 ;
assign lmq_byp_data_fmx_sel[3] = int_ldxa_vld & thread3_w2 ;
assign lmq_byp_data_en_w2[0] = (|lmq_byp_data_sel0[3:0]) | lmq_byp_data_fmx_sel[0] ;
assign lmq_byp_data_en_w2[1] = (|lmq_byp_data_sel1[3:0]) | lmq_byp_data_fmx_sel[1] ;
assign lmq_byp_data_en_w2[2] = (|lmq_byp_data_sel2[3:0]) | lmq_byp_data_fmx_sel[2] ;
assign lmq_byp_data_en_w2[3] = (|lmq_byp_data_sel3[3:0]) | lmq_byp_data_fmx_sel[3] ;
/*
assign stq_pkt2_data_en[0] =
st_inst_vld_g & ldst_dbl_g & quad_asi_g & thread0_g ;
assign stq_pkt2_data_en[1] =
st_inst_vld_g & ldst_dbl_g & quad_asi_g & thread1_g ;
assign stq_pkt2_data_en[2] =
st_inst_vld_g & ldst_dbl_g & quad_asi_g & thread2_g ;
assign stq_pkt2_data_en[3] =
st_inst_vld_g & ldst_dbl_g & quad_asi_g & thread3_g ;
*/
// casxa to be decoded as doubleword.
// casa to be decoded as word.
// ldstuba to be decoded as byte.
// casa, casxa and ldstuba needed to be decoded as alternate space insts with optional
// imm_asi use.
// An atomic will switch out a thread.
wire ifu_ldxa_vld, spu_ldxa_vld ;
assign ifu_ldxa_vld = ifu_lsu_ldxa_data_vld_w2 & ~ifu_lsu_ldxa_illgl_va_w2 ;
//assign tlu_ldxa_vld = tlu_lsu_ldxa_data_vld_w2 & ~tlu_lsu_ldxa_illgl_va_w2 ;
assign spu_ldxa_vld = spu_lsu_ldxa_data_vld_w2 & ~spu_lsu_ldxa_illgl_va_w2 ;
wire int_ldxa_ivld ;
assign int_ldxa_ivld = tlu_lsu_int_ldxa_vld_w2 & tlu_lsu_int_ld_ill_va_w2 ;
// ldxa data returns need to cmplt thread without writing to register file
assign ldxa_illgl_va_cmplt[0] =
((ifu_lsu_ldxa_data_vld_w2 & ifu_lsu_ldxa_illgl_va_w2) & ifu_ldxa_thread0_w2) |
//((tlu_lsu_ldxa_data_vld_w2 & tlu_lsu_ldxa_illgl_va_w2) & tlu_ldxa_thread0_w2) |
((spu_lsu_ldxa_data_vld_w2 & spu_lsu_ldxa_illgl_va_w2) & spu_ldxa_thread0_w2) |
(int_ldxa_ivld & thread0_w2) |
lsu_asi_illgl_va_cmplt_w2[0] ;
assign ldxa_illgl_va_cmplt[1] =
((ifu_lsu_ldxa_data_vld_w2 & ifu_lsu_ldxa_illgl_va_w2) & ifu_ldxa_thread1_w2) |
//((tlu_lsu_ldxa_data_vld_w2 & tlu_lsu_ldxa_illgl_va_w2) & tlu_ldxa_thread1_w2) |
((spu_lsu_ldxa_data_vld_w2 & spu_lsu_ldxa_illgl_va_w2) & spu_ldxa_thread1_w2) |
(int_ldxa_ivld & thread1_w2) |
lsu_asi_illgl_va_cmplt_w2[1] ;
assign ldxa_illgl_va_cmplt[2] =
((ifu_lsu_ldxa_data_vld_w2 & ifu_lsu_ldxa_illgl_va_w2) & ifu_ldxa_thread2_w2) |
//((tlu_lsu_ldxa_data_vld_w2 & tlu_lsu_ldxa_illgl_va_w2) & tlu_ldxa_thread2_w2) |
((spu_lsu_ldxa_data_vld_w2 & spu_lsu_ldxa_illgl_va_w2) & spu_ldxa_thread2_w2) |
(int_ldxa_ivld & thread2_w2) |
lsu_asi_illgl_va_cmplt_w2[2] ;
assign ldxa_illgl_va_cmplt[3] =
((ifu_lsu_ldxa_data_vld_w2 & ifu_lsu_ldxa_illgl_va_w2) & ifu_ldxa_thread3_w2) |
//((tlu_lsu_ldxa_data_vld_w2 & tlu_lsu_ldxa_illgl_va_w2) & tlu_ldxa_thread3_w2) |
((spu_lsu_ldxa_data_vld_w2 & spu_lsu_ldxa_illgl_va_w2) & spu_ldxa_thread3_w2) |
(int_ldxa_ivld & thread3_w2) |
lsu_asi_illgl_va_cmplt_w2[3] ;
dff_s #(4) illglva_cmplt_d1 (
.din (ldxa_illgl_va_cmplt[3:0]),
.q (ldxa_illgl_va_cmplt_d1[3:0]),
.clk (clk),
.se (se), .si (), .so ()
);
// Thread0
// Should be able to remove thread qualification for full-raw.
// Could have and e stage store and w2 stage stb rd in same cycle !!! Qualify select3
// with select0 to give the earlier event priority.
assign lmq_byp_ldxa_sel0[0] = ifu_ldxa_vld & ifu_ldxa_thread0_w2 ;
//assign lmq_byp_ldxa_sel0[1] = tlu_ldxa_vld & tlu_ldxa_thread0_w2 ;
assign lmq_byp_ldxa_sel0[1] = spu_ldxa_vld & spu_ldxa_thread0_w2 ;
assign lmq_byp_ldxa_sel0[2] = (lsu_asi_rd_en_w2 & thread0_w2) | ldxa_tlbrd0_w3 ;
wire fraw_annul0,fraw_annul1,fraw_annul2,fraw_annul3 ;
wire ldst_miss0,ldst_miss1,ldst_miss2,ldst_miss3 ;
//RAW read STB at W3 (not W2)
// E M W W2 W3 w4
//LD cam_hit RD STB, flop in byp FFs
//inst+1 D E
//inst+2 D E <= squash (stxa) rs3_e to write into byp FFs
//
assign fraw_annul0 = ld_stb_full_raw_w3 & thread0_w3 & ld_inst_vld_w3;
assign fraw_annul1 = ld_stb_full_raw_w3 & thread1_w3 & ld_inst_vld_w3;
assign fraw_annul2 = ld_stb_full_raw_w3 & thread2_w3 & ld_inst_vld_w3;
assign fraw_annul3 = ld_stb_full_raw_w3 & thread3_w3 & ld_inst_vld_w3;
assign ldst_miss0 = lsu_ldst_miss_w2 & thread0_w2 ;
assign ldst_miss1 = lsu_ldst_miss_w2 & thread1_w2 ;
assign ldst_miss2 = lsu_ldst_miss_w2 & thread2_w2 ;
assign ldst_miss3 = lsu_ldst_miss_w2 & thread3_w2 ;
wire fraw_annul0_d1,fraw_annul1_d1,fraw_annul2_d1,fraw_annul3_d1 ;
wire ldst_miss0_d1,ldst_miss1_d1,ldst_miss2_d1,ldst_miss3_d1 ;
dff_s #(4) fraw_d1 (
.din ({fraw_annul3,fraw_annul2,fraw_annul1,fraw_annul0}),
.q ({fraw_annul3_d1,fraw_annul2_d1,fraw_annul1_d1,fraw_annul0_d1}),
.clk (clk),
.se (se), .si (), .so ()
);
dff_s #(4) ldstm_d1 (
.din ({ldst_miss3,ldst_miss2,ldst_miss1,ldst_miss0}),
.q ({ldst_miss3_d1,ldst_miss2_d1,ldst_miss1_d1,ldst_miss0_d1}),
.clk (clk),
.se (se), .si (), .so ()
);
//wire memref_d ;
//assign memref_d = ifu_lsu_memref_d ;
/*wire mref_vld0,mref_vld1,mref_vld2,mref_vld3;
wire mref_vld0_d1,mref_vld1_d1,mref_vld2_d1,mref_vld3_d1;
// Bug 3053 - prevent overwrite of ldxa data with subsequent st-data
assign mref_vld0 = (memref_d | memref_e) & ~(lsu_ldst_miss_w2 & thread0_w2) ;
assign mref_vld1 = (memref_d | memref_e) & ~(lsu_ldst_miss_w2 & thread1_w2) ;
assign mref_vld2 = (memref_d | memref_e) & ~(lsu_ldst_miss_w2 & thread2_w2) ;
assign mref_vld3 = (memref_d | memref_e) & ~(lsu_ldst_miss_w2 & thread3_w2) ;
dff_s #(4) mrefv_d1 (
.din ({mref_vld3,mref_vld2,mref_vld1,mref_vld0}),
.q ({mref_vld3_d1,mref_vld2_d1,mref_vld1_d1,mref_vld0_d1}),
.clk (clk),
.se (se), .si (), .so ()
); */
//RAW timing change
assign lmq_byp_data_sel0[0] = ld_stb_full_raw_w3 & ~(ldd_force_l2access_w3 | atomic_w3 | dtlb_perror_en_w3) & thread0_w3 & ld_inst_vld_w3 ;
//assign lmq_byp_data_sel0[1] = st_inst_vld_e & thread0_e & ~ifu_lsu_casa_e & ~fraw_annul0 ;
// Timing fix - at most ld will also update the bypass buffer also.
//assign lmq_byp_data_sel0[1] = memref_e & thread0_e & ~ifu_lsu_casa_e & ~fraw_annul0 ; //bug3009
assign lmq_byp_data_sel0[1] = ~lmq_byp_data_sel0[0] & memref_e & thread0_e & ~ifu_lsu_casa_e &
~(fraw_annul0 | fraw_annul0_d1 | ldst_miss0 | ldst_miss0_d1); // Bug 3053,3180
//assign lmq_byp_data_sel0[1] = mref_vld0_d1 & thread0_e & ~ifu_lsu_casa_e & ~(fraw_annul0 | fraw_annul0_d1); // Bug 3053
//assign lmq_byp_data_sel0[1] = memref_e & thread0_e & ~ifu_lsu_casa_e & ~(fraw_annul0 | fraw_annul0_d1);
assign lmq_byp_data_sel0[2] = ~(|lmq_byp_data_sel0[1:0]) & casa_g & thread0_g & lsu_inst_vld_w & ~fraw_annul0_d1 ;
assign lmq_byp_data_sel0[3] = |lmq_byp_ldxa_sel0[2:0];
//assign lmq_byp_data_sel0[3] = |lmq_byp_ldxa_sel0[3:0];
// Thread1
assign lmq_byp_ldxa_sel1[0] = ifu_ldxa_vld & ifu_ldxa_thread1_w2 ;
//assign lmq_byp_ldxa_sel1[1] = tlu_ldxa_vld & tlu_ldxa_thread1_w2 ;
assign lmq_byp_ldxa_sel1[1] = spu_ldxa_vld & spu_ldxa_thread1_w2 ;
assign lmq_byp_ldxa_sel1[2] = (lsu_asi_rd_en_w2 & thread1_w2) | ldxa_tlbrd1_w3 ;
assign lmq_byp_data_sel1[0] = ld_stb_full_raw_w3 & ~(ldd_force_l2access_w3 | atomic_w3 | dtlb_perror_en_w3) & ld_inst_vld_w3 & thread1_w3 ;
assign lmq_byp_data_sel1[1] = ~lmq_byp_data_sel1[0] & memref_e & thread1_e & ~ifu_lsu_casa_e &
~(fraw_annul1 | fraw_annul1_d1 | ldst_miss1 | ldst_miss1_d1); // Bug 3053,3180
//assign lmq_byp_data_sel1[1] = memref_e & thread1_e & ~ifu_lsu_casa_e & ~fraw_annul1; // bug3009
//assign lmq_byp_data_sel1[1] = mref_vld1_d1 & thread1_e & ~ifu_lsu_casa_e & ~(fraw_annul1 | fraw_annul1_d1);
//assign lmq_byp_data_sel1[1] = memref_e & thread1_e & ~ifu_lsu_casa_e & ~(fraw_annul1 | fraw_annul1_d1); // Bug 3053
assign lmq_byp_data_sel1[2] = ~(|lmq_byp_data_sel1[1:0]) & casa_g & thread1_g & lsu_inst_vld_w & ~fraw_annul1_d1 ;
assign lmq_byp_data_sel1[3] = |lmq_byp_ldxa_sel1[2:0];
// Thread2
assign lmq_byp_ldxa_sel2[0] = ifu_ldxa_vld & ifu_ldxa_thread2_w2 ;
//assign lmq_byp_ldxa_sel2[1] = tlu_ldxa_vld & tlu_ldxa_thread2_w2 ;
assign lmq_byp_ldxa_sel2[1] = spu_ldxa_vld & spu_ldxa_thread2_w2 ;
assign lmq_byp_ldxa_sel2[2] = (lsu_asi_rd_en_w2 & thread2_w2) | ldxa_tlbrd2_w3 ;
assign lmq_byp_data_sel2[0] = ld_stb_full_raw_w3 & ~(ldd_force_l2access_w3 | atomic_w3 | dtlb_perror_en_w3) & ld_inst_vld_w3 & thread2_w3 ;
//assign lmq_byp_data_sel2[1] = memref_e & thread2_e & ~ifu_lsu_casa_e & ~fraw_annul2; // bug3009
assign lmq_byp_data_sel2[1] = ~lmq_byp_data_sel2[0] & memref_e & thread2_e & ~ifu_lsu_casa_e &
~(fraw_annul2 | fraw_annul2_d1 | ldst_miss2 | ldst_miss2_d1); // Bug 3053,3180
//assign lmq_byp_data_sel2[1] = memref_e & thread2_e & ~ifu_lsu_casa_e & ~(fraw_annul2 | fraw_annul2_d1); // Bug 3053
assign lmq_byp_data_sel2[2] = ~(|lmq_byp_data_sel2[1:0]) & casa_g & thread2_g & lsu_inst_vld_w & ~fraw_annul2_d1 ;
assign lmq_byp_data_sel2[3] = |lmq_byp_ldxa_sel2[2:0];
// Thread3
assign lmq_byp_ldxa_sel3[0] = ifu_ldxa_vld & ifu_ldxa_thread3_w2 ;
//assign lmq_byp_ldxa_sel3[1] = tlu_ldxa_vld & tlu_ldxa_thread3_w2 ;
assign lmq_byp_ldxa_sel3[1] = spu_ldxa_vld & spu_ldxa_thread3_w2 ;
assign lmq_byp_ldxa_sel3[2] = (lsu_asi_rd_en_w2 & thread3_w2) | ldxa_tlbrd3_w3 ;
assign lmq_byp_data_sel3[0] = ld_stb_full_raw_w3 & ~(ldd_force_l2access_w3 | atomic_w3 | dtlb_perror_en_w3) & ld_inst_vld_w3 & thread3_w3 ;
assign lmq_byp_data_sel3[1] = ~lmq_byp_data_sel3[0] & memref_e & thread3_e & ~ifu_lsu_casa_e &
~(fraw_annul3 | fraw_annul3_d1 | ldst_miss3 | ldst_miss3_d1); // Bug 3053,3180
//assign lmq_byp_data_sel3[1] = memref_e & thread3_e & ~ifu_lsu_casa_e & ~(fraw_annul3 | fraw_annul3_d1); // Bug 3053
assign lmq_byp_data_sel3[2] = ~(|lmq_byp_data_sel3[1:0]) & casa_g & thread3_g & lsu_inst_vld_w & ~fraw_annul3_d1 ;
assign lmq_byp_data_sel3[3] = |lmq_byp_ldxa_sel3[2:0];
dff_s #(4) ff_lmq_byp_data_raw_sel_d1 (
.din ({lmq_byp_data_sel3[0], lmq_byp_data_sel2[0],
lmq_byp_data_sel1[0], lmq_byp_data_sel0[0]}),
.q (lmq_byp_data_raw_sel_d1[3:0]),
.clk (clk),
.se (se), .si (), .so ()
);
dff_s #(4) ff_lmq_byp_data_raw_sel_d2 (
.din (lmq_byp_data_raw_sel_d1[3:0]),
.q (lmq_byp_data_raw_sel_d2[3:0]),
.clk (clk),
.se (se), .si (), .so ()
);
wire lsu_irf_raw_byp_e;
// Includes both ldxa and raw bypass.
assign lsu_irf_raw_byp_e =
~l2fill_vld_e & // no dfq fill
~(memref_e) ; // no ld/st in pipe.
//~(ld_inst_vld_e | st_inst_vld_e) ; // no ld/st in pipe.
// bug 5379 plus misc (randomize selection to prevent deadlock.
wire [3:0] bypass_sel ;
assign bypass_sel[0] = lsu_dcache_rand[0] ?
ldbyp0_vld : (ldbyp0_vld & ~(ldbyp3_vld | ldbyp2_vld | ldbyp1_vld)) ;
assign bypass_sel[1] = lsu_dcache_rand[0] ?
(ldbyp1_vld & ~ldbyp0_vld) : (ldbyp1_vld & ~(ldbyp3_vld | ldbyp2_vld)) ;
assign bypass_sel[2] = lsu_dcache_rand[0] ?
(ldbyp2_vld & ~(ldbyp0_vld | ldbyp1_vld)) : (ldbyp2_vld & ~ldbyp3_vld) ;
assign bypass_sel[3] = lsu_dcache_rand[0] ?
(ldbyp3_vld & ~(ldbyp0_vld | ldbyp1_vld | ldbyp2_vld)) : ldbyp3_vld ;
assign ld_thrd_byp_sel_e[0] = bypass_sel[0] & lsu_irf_raw_byp_e ;
assign ld_thrd_byp_sel_e[1] = bypass_sel[1] & lsu_irf_raw_byp_e ;
assign ld_thrd_byp_sel_e[2] = bypass_sel[2] & lsu_irf_raw_byp_e ;
assign ld_thrd_byp_sel_e[3] = bypass_sel[3] & lsu_irf_raw_byp_e ;
/*assign ld_thrd_byp_sel_e[0] = ldbyp0_vld & lsu_irf_raw_byp_e ;
assign ld_thrd_byp_sel_e[1] = ldbyp1_vld & lsu_irf_raw_byp_e &
~ldbyp0_vld ;
assign ld_thrd_byp_sel_e[2] = ldbyp2_vld & lsu_irf_raw_byp_e &
~(ldbyp0_vld | ldbyp1_vld);
assign ld_thrd_byp_sel_e[3] = ldbyp3_vld & lsu_irf_raw_byp_e &
~(ldbyp0_vld | ldbyp1_vld | ldbyp2_vld) ; */
//assign lsu_ld_thrd_byp_sel_e[2:0] = ld_thrd_byp_sel_e[2:0];
bw_u1_buf_30x UZsize_lsu_ld_thrd_byp_sel_e_b2 (.a(ld_thrd_byp_sel_e[2]), .z(lsu_ld_thrd_byp_sel_e[2]));
bw_u1_buf_30x UZsize_lsu_ld_thrd_byp_sel_e_b1 (.a(ld_thrd_byp_sel_e[1]), .z(lsu_ld_thrd_byp_sel_e[1]));
bw_u1_buf_30x UZsize_lsu_ld_thrd_byp_sel_e_b0 (.a(ld_thrd_byp_sel_e[0]), .z(lsu_ld_thrd_byp_sel_e[0]));
dff_s #(4) tbyp_stgd1 (
.din (ld_thrd_byp_sel_e[3:0]),
.q (ld_thrd_byp_sel_m[3:0]),
.clk (clk),
.se (se), .si (), .so ()
);
//assign ld_thrd_byp_mxsel_m[2:0] = ld_thrd_byp_sel_m[2:0];
//assign ld_thrd_byp_mxsel_m[3] = ~|ld_thrd_byp_sel_m[2:0];
assign ld_thrd_byp_mxsel_m[0] = ld_thrd_byp_sel_m[0] & ~rst_tri_en;
assign ld_thrd_byp_mxsel_m[1] = ld_thrd_byp_sel_m[1] & ~rst_tri_en;
assign ld_thrd_byp_mxsel_m[2] = ld_thrd_byp_sel_m[2] & ~rst_tri_en;
assign ld_thrd_byp_mxsel_m[3] = (~|ld_thrd_byp_sel_m[2:0]) | rst_tri_en;
dff_s #(4) tbyp_stgd2 (
.din (ld_thrd_byp_sel_m[3:0]),
.q (ld_thrd_byp_sel_g[3:0]),
.clk (clk),
.se (se), .si (), .so ()
);
//should move to M stage
//assign ld_thrd_byp_mxsel_g[2:0] = ld_thrd_byp_sel_g[2:0];
//assign ld_thrd_byp_mxsel_g[3] = ~|ld_thrd_byp_sel_g[2:0];
assign lmq_byp_ldxa_mxsel0[1:0] = lmq_byp_ldxa_sel0[1:0];
assign lmq_byp_ldxa_mxsel0[2] = ~|lmq_byp_ldxa_sel0[1:0];
assign lmq_byp_ldxa_mxsel1[1:0] = lmq_byp_ldxa_sel1[1:0];
assign lmq_byp_ldxa_mxsel1[2] = ~|lmq_byp_ldxa_sel1[1:0];
assign lmq_byp_ldxa_mxsel2[1:0] = lmq_byp_ldxa_sel2[1:0];
assign lmq_byp_ldxa_mxsel2[2] = ~|lmq_byp_ldxa_sel2[1:0];
assign lmq_byp_ldxa_mxsel3[1:0] = lmq_byp_ldxa_sel3[1:0];
assign lmq_byp_ldxa_mxsel3[2] = ~|lmq_byp_ldxa_sel3[1:0];
assign lmq_byp_data_mxsel0[0] = lmq_byp_data_sel0[0] & ~rst_tri_en | sehold;
assign lmq_byp_data_mxsel0[1] = lmq_byp_data_sel0[1] & ~rst_tri_en & ~sehold;
assign lmq_byp_data_mxsel0[2] = lmq_byp_data_sel0[2] & ~rst_tri_en & ~sehold;
assign lmq_byp_data_mxsel0[3] = (~|lmq_byp_data_sel0[2:0] | rst_tri_en) & ~sehold;
assign lmq_byp_data_mxsel1[0] = lmq_byp_data_sel1[0] & ~rst_tri_en | sehold;
assign lmq_byp_data_mxsel1[1] = lmq_byp_data_sel1[1] & ~rst_tri_en & ~sehold;
assign lmq_byp_data_mxsel1[2] = lmq_byp_data_sel1[2] & ~rst_tri_en & ~sehold;
assign lmq_byp_data_mxsel1[3] = (~|lmq_byp_data_sel1[2:0] | rst_tri_en) & ~sehold;
assign lmq_byp_data_mxsel2[0] = lmq_byp_data_sel2[0] & ~rst_tri_en | sehold;
assign lmq_byp_data_mxsel2[1] = lmq_byp_data_sel2[1] & ~rst_tri_en & ~sehold;
assign lmq_byp_data_mxsel2[2] = lmq_byp_data_sel2[2] & ~rst_tri_en & ~sehold;
assign lmq_byp_data_mxsel2[3] = (~|lmq_byp_data_sel2[2:0] | rst_tri_en) & ~sehold;
assign lmq_byp_data_mxsel3[0] = lmq_byp_data_sel3[0] & ~rst_tri_en | sehold;
assign lmq_byp_data_mxsel3[1] = lmq_byp_data_sel3[1] & ~rst_tri_en & ~sehold;
assign lmq_byp_data_mxsel3[2] = lmq_byp_data_sel3[2] & ~rst_tri_en & ~sehold;
assign lmq_byp_data_mxsel3[3] = (~|lmq_byp_data_sel3[2:0] | rst_tri_en) & ~sehold;
//=========================================================================================
// Error Based Traps/Reporting
//
//=========================================================================================
// !!! ORIGINAL ABOVE !!!
// Error Table for Queue
// ** In all cases; squash writes to irf.
// | Error Reporting | Trap ? |
// ifu_lsu_asi_rd_unc | NA;done by ifu | daccess-error |
// tte_data_perror_unc_w2 | sync;in pipe | daccess-error |
// tte_data_perror_corr_w2 | sync;in pipe | dmmu-miss |
// asi_tte_data_perror_w2 | async;out of Q | daccess-error |
// asi_tte_tag_perror_w2 | async;out of Q | daccess-error |
assign squash_byp_cmplt[0] =
((cam_perr_unc0 |
asi_data_perr0 |
asi_tag_perr0 |
ifu_unc_err0 ) & lsu_nceen_d1[0]) |
pend_atm_ld_ue[0] |
spubyp0_trap ; // Bug 3873. add spu trap squash. (change reverted).
assign squash_byp_cmplt[1] =
((cam_perr_unc1 | asi_data_perr1 | asi_tag_perr1 | ifu_unc_err1) & lsu_nceen_d1[1]) |
pend_atm_ld_ue[1] | spubyp1_trap ;
assign squash_byp_cmplt[2] =
((cam_perr_unc2 | asi_data_perr2 | asi_tag_perr2 | ifu_unc_err2) & lsu_nceen_d1[2]) |
pend_atm_ld_ue[2] | spubyp2_trap ;
assign squash_byp_cmplt[3] =
((cam_perr_unc3 | asi_data_perr3 | asi_tag_perr3 | ifu_unc_err3) & lsu_nceen_d1[3]) |
pend_atm_ld_ue[3] | spubyp3_trap ;
assign cam_perr_unc_e =
(ld_thrd_byp_sel_e[0] & cam_perr_unc0) |
(ld_thrd_byp_sel_e[1] & cam_perr_unc1) |
(ld_thrd_byp_sel_e[2] & cam_perr_unc2) |
(ld_thrd_byp_sel_e[3] & cam_perr_unc3) ;
assign asi_data_perr_e =
(ld_thrd_byp_sel_e[0] & asi_data_perr0) |
(ld_thrd_byp_sel_e[1] & asi_data_perr1) |
(ld_thrd_byp_sel_e[2] & asi_data_perr2) |
(ld_thrd_byp_sel_e[3] & asi_data_perr3) ;
assign asi_tag_perr_e =
(ld_thrd_byp_sel_e[0] & asi_tag_perr0) |
(ld_thrd_byp_sel_e[1] & asi_tag_perr1) |
(ld_thrd_byp_sel_e[2] & asi_tag_perr2) |
(ld_thrd_byp_sel_e[3] & asi_tag_perr3) ;
assign ifu_unc_err_e =
(ld_thrd_byp_sel_e[0] & ifu_unc_err0) |
(ld_thrd_byp_sel_e[1] & ifu_unc_err1) |
(ld_thrd_byp_sel_e[2] & ifu_unc_err2) |
(ld_thrd_byp_sel_e[3] & ifu_unc_err3) ;
wire atm_st_unc_err_e,atm_st_unc_err_m,atm_st_unc_err_g ;
assign atm_st_unc_err_e =
(atm_st_cmplt0 & pend_atm_ld_ue[0]) |
(atm_st_cmplt1 & pend_atm_ld_ue[1]) |
(atm_st_cmplt2 & pend_atm_ld_ue[2]) |
(atm_st_cmplt3 & pend_atm_ld_ue[3]) ;
dff_s #(5) stgm_tlberr (
.din ({cam_perr_unc_e,asi_data_perr_e,
asi_tag_perr_e,ifu_unc_err_e,atm_st_unc_err_e}),
.q ({cam_perr_unc_m,asi_data_perr_m,
asi_tag_perr_m,ifu_unc_err_m,atm_st_unc_err_m}),
.clk (clk),
.se (se), .si (), .so ()
);
dff_s #(5) stgg_tlberr (
.din ({cam_perr_unc_m,asi_data_perr_m,
asi_tag_perr_m,ifu_unc_err_m,atm_st_unc_err_m}),
.q ({cam_perr_unc_g,asi_data_perr_g,
asi_tag_perr_g,ifu_unc_err_g,atm_st_unc_err_g}),
.clk (clk),
.se (se), .si (), .so ()
);
assign lsu_tlb_asi_data_perr_g = asi_data_perr_g ;
assign lsu_tlb_asi_tag_perr_g = asi_tag_perr_g ;
// Asynchronous Trap Reporting to TLU (Traps are still precise).
// This version of nceen is meant specifically for trap reporting
// out of the asi queue.
wire nceen_m, nceen_g ;
assign nceen_m =
(ld_thrd_byp_sel_m[0] & lsu_nceen_d1[0]) |
(ld_thrd_byp_sel_m[1] & lsu_nceen_d1[1]) |
(ld_thrd_byp_sel_m[2] & lsu_nceen_d1[2]) |
(ld_thrd_byp_sel_m[3] & lsu_nceen_d1[3]) ;
wire nceen_dfq_m,nceen_dfq_g ;
// This version is meant specifically for lds reporting traps
// from the dfq.
assign nceen_dfq_m =
((~dfq_tid_m[1] & ~dfq_tid_m[0]) & lsu_nceen_d1[0]) |
((~dfq_tid_m[1] & dfq_tid_m[0]) & lsu_nceen_d1[1]) |
(( dfq_tid_m[1] & ~dfq_tid_m[0]) & lsu_nceen_d1[2]) |
(( dfq_tid_m[1] & dfq_tid_m[0]) & lsu_nceen_d1[3]) ;
dff_s #(2) trpen_stg (
.din ({nceen_m,nceen_dfq_m}),
.q ({nceen_g,nceen_dfq_g}),
.clk (clk),
.se (se), .si (), .so ()
);
// l2c/dram
wire atm_ld_w_uerr_m ;
dff_s #(1) atmldu_stm (
.din (atm_ld_w_uerr),
.q (atm_ld_w_uerr_m),
.clk (clk),
.se (se), .si (), .so ()
);
wire pmem_unc_error_m,pmem_unc_error_g ;
assign pmem_unc_error_m =
l2_unc_error_m & // bug3666
~atm_ld_w_uerr_m ; //bug4048 - squash for atm ld with error.
wire pmem_unc_error_tmp ;
dff_s #(1) pmem_stg (
.din (pmem_unc_error_m),
.q (pmem_unc_error_tmp),
.clk (clk),
.se (se), .si (), .so ()
);
assign pmem_unc_error_g =
(pmem_unc_error_tmp | bld_unc_err_pend_g) & ~bld_squash_err_g ;
wire async_ttype_vld_g ;
wire [6:0] async_ttype_g ;
wire [1:0] async_tid_g ;
//wire st_dtlb_perr_en ;
//assign st_dtlb_perr_en = st_inst_vld_unflushed & tte_data_perror_unc & nceen_pipe_g ;
// traps are not to be taken if enables are not set. The asi rds of the tlb must
// thus complete as usual.
assign async_ttype_vld_g =
(((cam_perr_unc_g | asi_data_perr_g | asi_tag_perr_g | ifu_unc_err_g) & nceen_g) |
(pmem_unc_error_g & nceen_dfq_g)) | // Bug 3335,3518
atm_st_unc_err_g | // Bug 4048
//lsu_defr_trp_taken_g |
//st_dtlb_perr_en |
//cam_perr_corr_g |
spubyp_trap_active_g ;
wire [6:0] async_ttype_m ;
assign async_ttype_m[6:0] =
spubyp_trap_active_m ? spubyp_ttype[6:0] : 7'h32 ;
dff_s #(7) attype_stg (
.din (async_ttype_m[6:0]),
.q (async_ttype_g[6:0]),
.clk (clk),
.se (se), .si (), .so ()
);
wire [1:0] async_err_tid_e,async_err_tid_m,async_err_tid_g ;
assign async_err_tid_e[0] = ld_thrd_byp_sel_e[1] | ld_thrd_byp_sel_e[3] ;
assign async_err_tid_e[1] = ld_thrd_byp_sel_e[3] | ld_thrd_byp_sel_e[2] ;
dff_s #(2) ldbyperr_stgm (
.din (async_err_tid_e[1:0]),
.q (async_err_tid_m[1:0]),
.clk (clk),
.se (se), .si (), .so ()
);
dff_s #(2) ldbyperr_stgg (
.din (async_err_tid_m[1:0]),
.q (async_err_tid_g[1:0]),
.clk (clk),
.se (se), .si (), .so ()
);
wire sel_dfq_tid ;
assign sel_dfq_tid = pmem_unc_error_g | atm_st_unc_err_g ;
assign async_tid_g[1:0] =
//lsu_defr_trp_taken_g ? thrid_g[1:0] : // Bug 4660 - remove.
sel_dfq_tid ? // Bug 3335,4048
dfq_tid_g[1:0] : async_err_tid_g[1:0] ;
// Delay async_trp interface to TLU by a cycle.
dff_s #(10) asynctrp_stgw2 (
.din ({async_ttype_vld_g,async_tid_g[1:0],async_ttype_g[6:0]}),
.q ({lsu_tlu_async_ttype_vld_w2,lsu_tlu_async_tid_w2[1:0],
lsu_tlu_async_ttype_w2[6:0]}),
.clk (clk),
.se (se), .si (), .so ()
);
// Asynchronous Error Reporting to IFU
// Partial.
wire sync_error_sel ;
wire memref_m ,memref_g;
dff_s #(1) memref_stgg (
.din (memref_m),
.q (memref_g),
.clk (clk),
.se (se), .si (), .so ()
);
//assign sync_error_sel = tte_data_perror_unc | tte_data_perror_corr ;
//for in1 or in2 to be selected, memref_g must be 0.
//in1 is reported thru the bypass/asi queues, in2 thru the dfq.
//So err_addr_sel[0] can be memref_g.
assign sync_error_sel = memref_g;
wire async_error_sel ;
assign async_error_sel = asi_data_perr_g | asi_tag_perr_g ;
assign lsu_err_addr_sel[0] = sync_error_sel & ~rst_tri_en;
assign lsu_err_addr_sel[1] = async_error_sel & ~rst_tri_en;
assign lsu_err_addr_sel[2] = ~(sync_error_sel | async_error_sel) | rst_tri_en;
//mux4ds #(6) async_tlb_index_mx(
// .in0 (misc_data0[5:0]),
// .in1 (misc_data1[5:0]),
// .in2 (misc_data2[5:0]),
// .in3 (misc_data3[5:0]),
// .sel0 (ld_thrd_byp_sel_g[0]),
// .sel1 (ld_thrd_byp_sel_g[1]),
// .sel2 (ld_thrd_byp_sel_g[2]),
// .sel3 (ld_thrd_byp_sel_g[3]),
// .dout (async_tlb_index[5:0])
// );
assign async_tlb_index[5:0] =
(ld_thrd_byp_sel_g[0] ? misc_data0[5:0] : 6'b0) |
(ld_thrd_byp_sel_g[1] ? misc_data1[5:0] : 6'b0) |
(ld_thrd_byp_sel_g[2] ? misc_data2[5:0] : 6'b0) |
(ld_thrd_byp_sel_g[3] ? misc_data3[5:0] : 6'b0) ;
wire [1:0] err_tid_g ;
//assign err_tid_g[1:0] =
// sync_error_sel ? thrid_g[1:0] :
// async_error_sel ? async_err_tid_g[1:0] : dfill_tid_g[1:0] ;
mux3ds #(2) err_tid_mx (
.in0 (thrid_g[1:0]),
.in1 (async_err_tid_g[1:0]),
.in2 (dfill_tid_g[1:0]),
.sel0(lsu_err_addr_sel[0]),
.sel1(lsu_err_addr_sel[1]),
.sel2(lsu_err_addr_sel[2]),
.dout(err_tid_g[1:0])
);
// Can shift to m.
//assign lsu_tlu_derr_tid_g[1:0] = err_tid_g[1:0] ;
dff_s #(2) errad_stgg (
.din (err_tid_g[1:0]),
.q (lsu_ifu_error_tid[1:0]),
.clk (clk),
.se (se), .si (), .so ()
);
assign lsu_ifu_io_error = //l2_unc_error_w2 & lsu_ifu_err_addr_b39 ;
// extend for bld to io space.
(l2_unc_error_w2 | bld_unc_err_pend_w2) & lsu_ifu_err_addr_b39 & ~bld_squash_err_w2 ;
//=========================================================================================
wire stxa_internal_cmplt ;
assign stxa_internal_cmplt =
stxa_internal &
~(intrpt_disp_asi_g | stxa_stall_asi_g | (ifu_nontlb_asi_g & ~ifu_asi42_flush_g) | tlb_lng_ltncy_asi_g) &
lsu_inst_vld_w & ~dctl_early_flush_w ;
//lsu_inst_vld_w & ~dctl_flush_pipe_w ;
// Need to add stxa's related to ifu non-tlb asi.
dff_s stxa_int_d1 (
.din (stxa_internal_cmplt),
//.din (stxa_internal & ~(stxa_stall_asi_g | tlb_lng_ltncy_asi_g) & lsu_inst_vld_w),
.q (stxa_internal_d1),
.clk (clk),
.se (se), .si (), .so ()
);
dff_s stxa_int_d2 (
.din (stxa_internal_d1),
.q (stxa_internal_d2),
.clk (clk),
.se (se), .si (), .so ()
);
//=========================================================================================
// Replacement Algorithm for Cache
//=========================================================================================
// Increment Condition.
wire lfsr_incr, lfsr_incr_d1 ;
assign lfsr_incr =
ld_inst_vld_g & ~lsu_way_hit_or & ~ldxa_internal &
~ncache_pcx_rq_g ; // must be cacheable
dff_s lfsrd1_ff (
.din (lfsr_incr),
.q (lfsr_incr_d1),
.clk (clk),
.se (se), .si (), .so ()
);
wire lfsr_rst ;
assign lfsr_rst =
reset |
~gdbginit_l | // debug init.
dc_direct_map ; // direct map mode will reset.
// Bug 4027
lsu_dcache_lfsr lfsr(.out (lsu_dcache_rand[1:0]),
.clk (clk),
.advance (lfsr_incr_d1),
.reset (lfsr_rst),
.se (se),
.si (),
.so ());
//assign lsu_dcache_rand[1:0] = dcache_rand[1:0];
/*assign dcache_rand_new[1:0] = dcache_rand[1:0] + {1'b0, lsu_ld_miss_wb} ;
dffre_s #(2) drand (
.din (dcache_rand_new[1:0]),
.q (dcache_rand[1:0]),
.rst (reset), .en (lsu_ld_miss_wb),
.clk (clk),
.se (se), .si (), .so ()
);
assign lsu_dcache_rand[1:0] = dcache_rand[1:0]; */
//=========================================================================================
// Packet Assembly
//=========================================================================================
assign lsu_encd_way_hit[0] = cache_way_hit_buf1[1] | cache_way_hit_buf1[3] ;
assign lsu_encd_way_hit[1] = cache_way_hit_buf1[2] | cache_way_hit_buf1[3] ;
//assign lsu_way_hit_or = |lsu_way_hit[3:0];
assign lsu_way_hit_or = |cache_way_hit_buf1[3:0]; // Bug 3940
//assign stb_byp_pkt_vld_e = st_inst_vld_e & ~(ldsta_internal_e & alt_space_e);
assign ld_pcx_pkt_vld_e = ld_inst_vld_e & ~(ldsta_internal_e & alt_space_e);
dff_s #(5) pktctl_stgm (
.din ({ifu_lsu_ldst_dbl_e, ld_pcx_pkt_vld_e,
ifu_lsu_casa_e,ifu_lsu_ldstub_e,ifu_lsu_swap_e}),
.q ({ldst_dbl_m, ld_pcx_pkt_vld_m,
casa_m,ldstub_m,swap_m}),
.clk (clk),
.se (se), .si (), .so ()
);
assign atomic_m = casa_m | ldstub_m | swap_m ;
dff_s #(6) pktctl_stgg (
.din ({ldst_dbl_m, ld_pcx_pkt_vld_m,
casa_m,ldstub_m,swap_m,atomic_m}),
.q ({ldst_dbl_g, ld_pcx_pkt_vld_g,
casa_g,ldstub_g,swap_g,atomic_g}),
.clk (clk),
.se (se), .si (), .so ()
);
dff_s #(2) pktctl_stgw2 (
.din ({ldd_force_l2access_g, atomic_g}),
.q ({ldd_force_l2access_w2,atomic_w2}),
.clk (clk),
.se (se), .si (), .so ()
);
dff_s #(2) pktctl_stgw3 (
.din ({ldd_force_l2access_w2, atomic_w2}),
.q ({ldd_force_l2access_w3, atomic_w3}),
.clk (clk),
.se (se), .si (), .so ()
);
assign lsu_ldstub_g = ldstub_g ;
assign lsu_swap_g = swap_g ;
// Choose way for load. If load hits in dcache but sent out to xbar because
// of partial raw then need to use hit way else use random. Similarly, dcache
// parity error will force a miss and fill to same way.
// Moved to qctl1
// For direct-map mode, assume that addition set-index bits 12:11 are
// used to file line in set.
//assign ld_way[1:0] =
// (|lsu_way_hit[3:0]) ?
// {lsu_encd_way_hit[1],lsu_encd_way_hit[0]} :
// lsu_ld_sec_hit_l2access_g ? lsu_ld_sec_hit_wy_g[1:0] :
// (dc_direct_map ? ldst_va_g[12:11] : dcache_rand[1:0]) ;
// set to 011 for atomic - only cas encoding used for pcx pkt.
assign ld_rq_type[2:0] =
atomic_g ? 3'b011 : // cas pkt 2/ldstub/swap
// (ldst_dbl_g & st_inst_vld_g & quad_asi_g) ? 3'b001 : // stquad - label as store.
3'b000 ; // normal load
//assign lmq_pkt_vld_g = ld_pcx_pkt_vld_g | (ldst_dbl_g & st_inst_vld_unflushed) | pref_inst_g ;
assign lmq_pkt_vld_g = ld_pcx_pkt_vld_g | pref_inst_g ;
// Moved to qctl1
// 2'b01 encodes ld as st-quad pkt2. 2'b00 needed for cas-pkt2
//assign lmq_pkt_way_g[1:0] =
//(ldst_dbl_g & st_inst_vld_unflushed & quad_asi_g) ? 2'b01 :
// casa_g ? 2'b00 : ld_way[1:0] ;
// ld is 128b request.
wire qword_access_g;
assign qword_access_g =
(quad_asi_g | blk_asi_g ) & lsu_alt_space_g & ld_inst_vld_unflushed ;
assign lsu_quad_word_access_g = qword_access_g ;
wire fp_ld_inst_g ;
assign fp_ld_inst_g = fp_ldst_g & ld_inst_vld_g ;
wire ldst_sz_b0_g ;
assign ldst_sz_b0_g =
ldst_sz_g[0] &
~(ldst_dbl_g & ~fp_ldst_g &
(~lsu_alt_space_g | (lsu_alt_space_g & ~quad_asi_g))) ;
// word for ld-dbl
wire asi_real_iomem_m,asi_real_iomem_g ;
assign asi_real_iomem_m =
(dtlb_bypass_m & (phy_use_ec_asi_m | phy_byp_ec_asi_m) & lsu_alt_space_m) ;
dff_s #(1) stgg_asir (
.din (asi_real_iomem_m),
.q (asi_real_iomem_g),
.clk (clk),
.se (se), .si (), .so ()
);
assign ncache_pcx_rq_g =
atomic_g | // cas,ldstub,swap
asi_real_iomem_g | // real_mem, real_io
~dcache_enable_g | // dcache disabled : Bug 5174 (accidental removal)
((tlb_pgnum[39] & ~lsu_dtlb_bypass_g & tlb_cam_hit_g) | // IO - tlb not in bypass
(tlb_pgnum[39] & lsu_dtlb_bypass_g)) | // IO - tlb bypass
(~lsu_tte_data_cp_g & tlb_cam_hit_g) | // cp bit is clear
((quad_asi_g | binit_quad_asi_g | blk_asi_g) & lsu_alt_space_g & ldst_dbl_g & ld_inst_vld_unflushed) | // quad-ld
pref_inst_g ; // pref will not alloc. in L2 dir
//wire dflush_ld_g ;
//assign dflush_ld_g = dflush_asi_g & lsu_alt_space_g ;
// st-quad pkt1 and pkt2 need different addresses !!
// ** should be able to reduce the width, rd2,stquad,lmq_pkt_way **
//assign ld_pcx_pkt_g[`LMQ_WIDTH-1:0] =
//bug3601
//dbl_data_return will become lmq_ldd
//it includes quad ld, int ldd, block ld, all these cases need return data twice.
wire dbl_data_return;
assign dbl_data_return = ldst_dbl_g & ~ (fp_ldst_g & ~ (blk_asi_g & lsu_alt_space_g));
assign ld_pcx_pkt_g[`LMQ_WIDTH-1:40] =
{lmq_pkt_vld_g,
1'b0, //dflush_ld_g, bug 4580
pref_inst_g,
fp_ld_inst_g,
l1hit_sign_extend_g,
//lsu_bendian_access_g,
bendian_g, // l2fill_bendian removed.
ld_rd_g[4:0], // use rd1 only for now.
dbl_data_return, //bug 3601
//ldst_dbl_g & ~fp_ldst_g, // rd2 used by ld double.
{ld_rd_g[4:1],~ld_rd_g[0]}, // rd2 to be used with atomics.
ld_rq_type[2:0],
ncache_pcx_rq_g, // NC.
//lmq_pkt_way_g[1:0], // replacement way
2'b00,
ldst_sz_g[1],ldst_sz_b0_g};
//{tlb_pgnum[39:10], ldst_va_g[9:0]}};
//=========================================================================================
// Byte Masking for writes
//=========================================================================================
// Byte-enables will be generated in cycle prior to fill (E-stage)
// Reads and writes are mutex as array is single-ported.
// byte-enables are handled thru read-modify-writes.
// Create 16b Write Mask based on size and va ;
// This is to be put in the DFQ once the DFQ is on-line.
wire [2:0] dc_waddr_m ;
dff_s #(4) stgm_addr (
.din ({memref_e, dcache_wr_addr_e[2:0]}),
.q ({memref_m, dc_waddr_m[2:0]}),
.clk (clk),
.se (se), .si (), .so ()
);
assign lsu_memref_m = memref_m ;
//wire [3:0] rwaddr_enc ;
//assign rwaddr_enc[3:0] = memref_m ?
// lsu_ldst_va_b7_b0_m[3:0] : dc_waddr_m[3:0];
wire [2:0] rwaddr_enc ;
assign rwaddr_enc[2:0] = memref_m ?
lsu_ldst_va_b7_b0_m[2:0] : dc_waddr_m[2:0];
wire [1:0] wr_size;
assign wr_size[1:0] = dcache_wr_size_e[1:0];
wire wr_hword, wr_word, wr_dword;
//assign wr_byte = ~wr_size[1] & ~wr_size[0] ; // 01
assign wr_hword = ~wr_size[1] & wr_size[0] ; // 01
assign wr_word = wr_size[1] & ~wr_size[0] ; // 10
assign wr_dword = wr_size[1] & wr_size[0] ; // 11
assign ldst_byte = ~ldst_sz_e[1] & ~ldst_sz_e[0] ; // 01
assign ldst_hword = ~ldst_sz_e[1] & ldst_sz_e[0] ; // 01
assign ldst_word = ldst_sz_e[1] & ~ldst_sz_e[0] ; // 10
assign ldst_dword = ldst_sz_e[1] & ldst_sz_e[0] ; // 11
// In Bypass mode, endianness is determined by asi.
// Need to complete this equation.
// Note : add MMU disable bypass conditions !!!
assign tlb_invert_endian_g = lsu_tlb_invert_endian_g & ~lsu_dtlb_bypass_g & tlb_cam_hit_g ;
// Is qualification with reset needed ?
//assign l2fill_bendian_g = lsu_l2fill_bendian_g & ~reset;
//assign pstate_cle_m =
// thread0_m ? tlu_lsu_pstate_cle[0] :
// thread1_m ? tlu_lsu_pstate_cle[1] :
// thread2_m ? tlu_lsu_pstate_cle[2] :
// tlu_lsu_pstate_cle[3] ;
mux4ds #(1) pstate_cle_e_mux (
.in0 (tlu_lsu_pstate_cle[0]),
.in1 (tlu_lsu_pstate_cle[1]),
.in2 (tlu_lsu_pstate_cle[2]),
.in3 (tlu_lsu_pstate_cle[3]),
.sel0 (thread0_e),
.sel1 (thread1_e),
.sel2 (thread2_e),
.sel3 (thread3_e),
.dout (pstate_cle_e)
);
dff_s #(1) stgm_pstatecle (
.din (pstate_cle_e),
.q (pstate_cle_m),
.clk (clk),
.se (se), .si (), .so ()
);
dff_s #(1) stgg_pstatecle (
.din (pstate_cle_m),
.q (pstate_cle_g),
.clk (clk),
.se (se), .si (), .so ()
);
//SPARC V9 page 52. pstate.cle should only affect implicit ASI
assign l1hit_lendian_g =
((non_altspace_ldst_g & (pstate_cle_g ^ tlb_invert_endian_g)) | // non altspace ldst
(altspace_ldst_g & (lendian_asi_g ^ tlb_invert_endian_g))) // altspace ldst
& ~(asi_internal_g & lsu_alt_space_g); // internal asi is big-endian
wire l1hit_lendian_predict_m ;
// Predict endian-ness in m-stage. Assume tte.IE=0
assign l1hit_lendian_predict_m =
((non_altspace_ldst_m & pstate_cle_m) | // non altspace ldst
(altspace_ldst_m & lendian_asi_m)) // altspace ldst
& ~asi_internal_m ; // internal asi is big-endian
// Further, decode of ASI is not factored into endian calculation.
//assign lsu_bendian_access_g = (ld_inst_vld_unflushed | st_inst_vld_unflushed) ?
// ~l1hit_lendian_g : l2fill_bendian_g ;
// m stage endian signal is predicted for in-pipe lds only.
wire bendian_pred_m, bendian_pred_g ;
assign bendian_pred_m = (ld_inst_vld_m | st_inst_vld_m) ?
~l1hit_lendian_predict_m : lsu_l2fill_bendian_m ;
dff_s #(1) stgg_bendpr(
.din (bendian_pred_m),
.q (bendian_pred_g),
.clk (clk),
.se (se), .si (), .so ()
);
// mispredict applies to only in-pipe lds.
assign endian_mispred_g = bendian_pred_g ^ ~l1hit_lendian_g ;
// Staging for alignment on read from l1 or fill to l2.
dff_s #(4) stgm_sz (
.din ({ldst_byte, ldst_hword, ldst_word, ldst_dword}),
.q ({byte_m,hword_m,word_m,dword_m}),
.clk (clk),
.se (se), .si (), .so ()
);
wire [7:0] rwaddr_dcd_part ;
assign rwaddr_dcd_part[0] = ~rwaddr_enc[2] & ~rwaddr_enc[1] & ~rwaddr_enc[0] ;
assign rwaddr_dcd_part[1] = ~rwaddr_enc[2] & ~rwaddr_enc[1] & rwaddr_enc[0] ;
assign rwaddr_dcd_part[2] = ~rwaddr_enc[2] & rwaddr_enc[1] & ~rwaddr_enc[0] ;
assign rwaddr_dcd_part[3] = ~rwaddr_enc[2] & rwaddr_enc[1] & rwaddr_enc[0] ;
assign rwaddr_dcd_part[4] = rwaddr_enc[2] & ~rwaddr_enc[1] & ~rwaddr_enc[0] ;
assign rwaddr_dcd_part[5] = rwaddr_enc[2] & ~rwaddr_enc[1] & rwaddr_enc[0] ;
assign rwaddr_dcd_part[6] = rwaddr_enc[2] & rwaddr_enc[1] & ~rwaddr_enc[0] ;
assign rwaddr_dcd_part[7] = rwaddr_enc[2] & rwaddr_enc[1] & rwaddr_enc[0] ;
assign baddr_m[7:0] = rwaddr_dcd_part[7:0];
/*
assign baddr_m[0] = ~rwaddr_enc[3] & rwaddr_dcd_part[0] ;
assign baddr_m[1] = ~rwaddr_enc[3] & rwaddr_dcd_part[1] ;
assign baddr_m[2] = ~rwaddr_enc[3] & rwaddr_dcd_part[2] ;
assign baddr_m[3] = ~rwaddr_enc[3] & rwaddr_dcd_part[3] ;
assign baddr_m[4] = ~rwaddr_enc[3] & rwaddr_dcd_part[4] ;
assign baddr_m[5] = ~rwaddr_enc[3] & rwaddr_dcd_part[5] ;
assign baddr_m[6] = ~rwaddr_enc[3] & rwaddr_dcd_part[6] ;
assign baddr_m[7] = ~rwaddr_enc[3] & rwaddr_dcd_part[7] ;
assign baddr_m[8] = rwaddr_enc[3] & rwaddr_dcd_part[0] ;
assign baddr_m[9] = rwaddr_enc[3] & rwaddr_dcd_part[1] ;
assign baddr_m[10] = rwaddr_enc[3] & rwaddr_dcd_part[2] ;
assign baddr_m[11] = rwaddr_enc[3] & rwaddr_dcd_part[3] ;
assign baddr_m[12] = rwaddr_enc[3] & rwaddr_dcd_part[4] ;
assign baddr_m[13] = rwaddr_enc[3] & rwaddr_dcd_part[5] ;
assign baddr_m[14] = rwaddr_enc[3] & rwaddr_dcd_part[6] ;
assign baddr_m[15] = rwaddr_enc[3] & rwaddr_dcd_part[7] ;
*/
// Byte Address to start write from. Quantity can be byte/hword/word/dword.
// E-stage decoding for write to cache.
wire [3:0] waddr_enc ;
wire [7:0] waddr_dcd_part ;
wire [15:0] waddr_dcd ;
assign waddr_dcd_part[0] = ~waddr_enc[2] & ~waddr_enc[1] & ~waddr_enc[0] ;
assign waddr_dcd_part[1] = ~waddr_enc[2] & ~waddr_enc[1] & waddr_enc[0] ;
assign waddr_dcd_part[2] = ~waddr_enc[2] & waddr_enc[1] & ~waddr_enc[0] ;
assign waddr_dcd_part[3] = ~waddr_enc[2] & waddr_enc[1] & waddr_enc[0] ;
assign waddr_dcd_part[4] = waddr_enc[2] & ~waddr_enc[1] & ~waddr_enc[0] ;
assign waddr_dcd_part[5] = waddr_enc[2] & ~waddr_enc[1] & waddr_enc[0] ;
assign waddr_dcd_part[6] = waddr_enc[2] & waddr_enc[1] & ~waddr_enc[0] ;
assign waddr_dcd_part[7] = waddr_enc[2] & waddr_enc[1] & waddr_enc[0] ;
assign waddr_dcd[0] = ~waddr_enc[3] & waddr_dcd_part[0] ;
assign waddr_dcd[1] = ~waddr_enc[3] & waddr_dcd_part[1] ;
assign waddr_dcd[2] = ~waddr_enc[3] & waddr_dcd_part[2] ;
assign waddr_dcd[3] = ~waddr_enc[3] & waddr_dcd_part[3] ;
assign waddr_dcd[4] = ~waddr_enc[3] & waddr_dcd_part[4] ;
assign waddr_dcd[5] = ~waddr_enc[3] & waddr_dcd_part[5] ;
assign waddr_dcd[6] = ~waddr_enc[3] & waddr_dcd_part[6] ;
assign waddr_dcd[7] = ~waddr_enc[3] & waddr_dcd_part[7] ;
assign waddr_dcd[8] = waddr_enc[3] & waddr_dcd_part[0] ;
assign waddr_dcd[9] = waddr_enc[3] & waddr_dcd_part[1] ;
assign waddr_dcd[10] = waddr_enc[3] & waddr_dcd_part[2] ;
assign waddr_dcd[11] = waddr_enc[3] & waddr_dcd_part[3] ;
assign waddr_dcd[12] = waddr_enc[3] & waddr_dcd_part[4] ;
assign waddr_dcd[13] = waddr_enc[3] & waddr_dcd_part[5] ;
assign waddr_dcd[14] = waddr_enc[3] & waddr_dcd_part[6] ;
assign waddr_dcd[15] = waddr_enc[3] & waddr_dcd_part[7] ;
// Byte enables for 16 bytes.
//bug6216/eco6624
wire write_16byte_e;
assign write_16byte_e = l2fill_vld_e | lsu_bist_wvld_e;
assign byte_wr_enable[15] =
write_16byte_e | waddr_dcd[0] ;
assign byte_wr_enable[14] =
write_16byte_e | waddr_dcd[1] |
(wr_hword & waddr_dcd[0]) | (wr_word & waddr_dcd[0]) |
(wr_dword & waddr_dcd[0]) ;
assign byte_wr_enable[13] =
write_16byte_e | waddr_dcd[2] |
(wr_word & waddr_dcd[0]) | (wr_dword & waddr_dcd[0]) ;
assign byte_wr_enable[12] =
write_16byte_e | waddr_dcd[3] |
(wr_hword & waddr_dcd[2]) | (wr_word & waddr_dcd[0]) |
(wr_dword & waddr_dcd[0]) ;
assign byte_wr_enable[11] =
write_16byte_e | waddr_dcd[4] |
(wr_dword & waddr_dcd[0]) ;
assign byte_wr_enable[10] =
write_16byte_e | waddr_dcd[5] |
(wr_hword & waddr_dcd[4]) | (wr_word & waddr_dcd[4]) |
(wr_dword & waddr_dcd[0]) ;
assign byte_wr_enable[9] =
write_16byte_e | waddr_dcd[6] |
(wr_word & waddr_dcd[4]) | (wr_dword & waddr_dcd[0]) ;
assign byte_wr_enable[8] =
write_16byte_e | waddr_dcd[7] |
(wr_hword & waddr_dcd[6]) | (wr_word & waddr_dcd[4]) |
(wr_dword & waddr_dcd[0]) ;
assign byte_wr_enable[7] =
write_16byte_e | waddr_dcd[8] ;
assign byte_wr_enable[6] =
write_16byte_e | waddr_dcd[9] |
(wr_hword & waddr_dcd[8]) | (wr_word & waddr_dcd[8]) |
(wr_dword & waddr_dcd[8]) ;
assign byte_wr_enable[5] =
write_16byte_e | waddr_dcd[10] |
(wr_word & waddr_dcd[8]) | (wr_dword & waddr_dcd[8]) ;
assign byte_wr_enable[4] =
write_16byte_e | waddr_dcd[11] |
(wr_hword & waddr_dcd[10]) | (wr_word & waddr_dcd[8]) |
(wr_dword & waddr_dcd[8]) ;
assign byte_wr_enable[3] =
write_16byte_e | waddr_dcd[12] |
(wr_dword & waddr_dcd[8]) ;
assign byte_wr_enable[2] =
write_16byte_e | waddr_dcd[13] |
(wr_hword & waddr_dcd[12]) | (wr_word & waddr_dcd[12]) |
(wr_dword & waddr_dcd[8]) ;
assign byte_wr_enable[1] =
write_16byte_e | waddr_dcd[14] |
(wr_word & waddr_dcd[12]) | (wr_dword & waddr_dcd[8]) ;
assign byte_wr_enable[0] =
write_16byte_e | waddr_dcd[15] |
(wr_hword & waddr_dcd[14]) | (wr_word & waddr_dcd[12]) |
(wr_dword & waddr_dcd[8]) ;
assign dcache_byte_wr_en_e[15:0] = byte_wr_enable[15:0] ;
//assign lsu_st_byte_addr_g[15:0] = byp_baddr_g[15:0] ;
//=========================================================================================
// Sign/Zero-Extension
//=========================================================================================
dff_s #(1) stgm_msb (
.din ({lsu_l1hit_sign_extend_e}),
.q ({l1hit_sign_extend_m}),
.clk (clk),
.se (se), .si (), .so ()
);
dff_s #(1) stgg_msb (
.din ({l1hit_sign_extend_m}),
.q ({l1hit_sign_extend_g}),
.clk (clk),
.se (se), .si (), .so ()
);
//wire [1:0] lsu_byp_misc_sz_g ;
/*dff #(2) ff_lsu_byp_misc_sz_g (
.din (lsu_byp_misc_sz_m[1:0]),
.q (lsu_byp_misc_sz_g[1:0]),
.clk (clk),
.se (se), .si (), .so ()
); */
assign misc_byte_m = ~lsu_byp_misc_sz_m[1] & ~lsu_byp_misc_sz_m[0] ; // 00
assign misc_hword_m = ~lsu_byp_misc_sz_m[1] & lsu_byp_misc_sz_m[0] ; // 01
assign misc_word_m = lsu_byp_misc_sz_m[1] & ~lsu_byp_misc_sz_m[0] ; // 10
assign misc_dword_m = lsu_byp_misc_sz_m[1] & lsu_byp_misc_sz_m[0] ; // 11
wire byp_byte_m,byp_hword_m,byp_word_m,byp_dword_m;
assign byp_byte_m = (ld_inst_vld_m) ? byte_m : misc_byte_m ;
assign byp_hword_m = (ld_inst_vld_m) ? hword_m : misc_hword_m ;
assign byp_word_m = (ld_inst_vld_m) ? word_m : misc_word_m ;
assign byp_dword_m = (ld_inst_vld_m) ? dword_m : misc_dword_m ;
/*assign byp_byte_g = (|lsu_irf_byp_data_src[2:1]) ? misc_byte_g : byte_g ;
assign byp_hword_g = (|lsu_irf_byp_data_src[2:1]) ? misc_hword_g : hword_g ;
assign byp_word_g = (|lsu_irf_byp_data_src[2:1]) ? misc_word_g : word_g ;*/
dff_s #(1) bypsz_stgg(
.din ({byp_word_m}),
.q ({byp_word_g}),
.clk (clk),
.se (se), .si (), .so ()
);
//wire [3:0] misc_waddr_m ;
//assign misc_waddr_m[3:0] = {lsu_byp_misc_addr_m[3],lsu_byp_misc_addr_m[2]^lsu_byp_ldd_oddrd_m,lsu_byp_misc_addr_m[1:0]} ;
wire [2:0] misc_waddr_m ;
assign misc_waddr_m[2:0] = {lsu_byp_misc_addr_m[2]^lsu_byp_ldd_oddrd_m,lsu_byp_misc_addr_m[1:0]} ;
//wire [15:0] misc_baddr_m ;
wire [7:0] misc_baddr_m ;
// m-stage decoding
// Might be better to stage encoded waddr, mux and then decode.
/*
assign misc_baddr_m[0] = ~misc_waddr_m[3] & ~misc_waddr_m[2] & ~misc_waddr_m[1] & ~misc_waddr_m[0] ;
assign misc_baddr_m[1] = ~misc_waddr_m[3] & ~misc_waddr_m[2] & ~misc_waddr_m[1] & misc_waddr_m[0] ;
assign misc_baddr_m[2] = ~misc_waddr_m[3] & ~misc_waddr_m[2] & misc_waddr_m[1] & ~misc_waddr_m[0] ;
assign misc_baddr_m[3] = ~misc_waddr_m[3] & ~misc_waddr_m[2] & misc_waddr_m[1] & misc_waddr_m[0] ;
assign misc_baddr_m[4] = ~misc_waddr_m[3] & misc_waddr_m[2] & ~misc_waddr_m[1] & ~misc_waddr_m[0] ;
assign misc_baddr_m[5] = ~misc_waddr_m[3] & misc_waddr_m[2] & ~misc_waddr_m[1] & misc_waddr_m[0] ;
assign misc_baddr_m[6] = ~misc_waddr_m[3] & misc_waddr_m[2] & misc_waddr_m[1] & ~misc_waddr_m[0] ;
assign misc_baddr_m[7] = ~misc_waddr_m[3] & misc_waddr_m[2] & misc_waddr_m[1] & misc_waddr_m[0] ;
assign misc_baddr_m[8] = misc_waddr_m[3] & ~misc_waddr_m[2] & ~misc_waddr_m[1] & ~misc_waddr_m[0] ;
assign misc_baddr_m[9] = misc_waddr_m[3] & ~misc_waddr_m[2] & ~misc_waddr_m[1] & misc_waddr_m[0] ;
assign misc_baddr_m[10] = misc_waddr_m[3] & ~misc_waddr_m[2] & misc_waddr_m[1] & ~misc_waddr_m[0] ;
assign misc_baddr_m[11] = misc_waddr_m[3] & ~misc_waddr_m[2] & misc_waddr_m[1] & misc_waddr_m[0] ;
assign misc_baddr_m[12] = misc_waddr_m[3] & misc_waddr_m[2] & ~misc_waddr_m[1] & ~misc_waddr_m[0] ;
assign misc_baddr_m[13] = misc_waddr_m[3] & misc_waddr_m[2] & ~misc_waddr_m[1] & misc_waddr_m[0] ;
assign misc_baddr_m[14] = misc_waddr_m[3] & misc_waddr_m[2] & misc_waddr_m[1] & ~misc_waddr_m[0] ;
assign misc_baddr_m[15] = misc_waddr_m[3] & misc_waddr_m[2] & misc_waddr_m[1] & misc_waddr_m[0] ;
*/
assign misc_baddr_m[0] = ~misc_waddr_m[2] & ~misc_waddr_m[1] & ~misc_waddr_m[0] ;
assign misc_baddr_m[1] = ~misc_waddr_m[2] & ~misc_waddr_m[1] & misc_waddr_m[0] ;
assign misc_baddr_m[2] = ~misc_waddr_m[2] & misc_waddr_m[1] & ~misc_waddr_m[0] ;
assign misc_baddr_m[3] = ~misc_waddr_m[2] & misc_waddr_m[1] & misc_waddr_m[0] ;
assign misc_baddr_m[4] = misc_waddr_m[2] & ~misc_waddr_m[1] & ~misc_waddr_m[0] ;
assign misc_baddr_m[5] = misc_waddr_m[2] & ~misc_waddr_m[1] & misc_waddr_m[0] ;
assign misc_baddr_m[6] = misc_waddr_m[2] & misc_waddr_m[1] & ~misc_waddr_m[0] ;
assign misc_baddr_m[7] = misc_waddr_m[2] & misc_waddr_m[1] & misc_waddr_m[0] ;
//wire [15:0] byp_baddr_m ;
//assign byp_baddr_m[15:0] = (~(ld_inst_vld_m | st_inst_vld_m)) ? misc_baddr_m[15:0] : baddr_m[15:0] ;
wire [7:0] byp_baddr_m ;
assign byp_baddr_m[7:0] = (~(ld_inst_vld_m | st_inst_vld_m)) ? misc_baddr_m[7:0] : baddr_m[7:0] ;
wire l2fill_sign_extend_m;
assign l2fill_sign_extend_m = lsu_l2fill_sign_extend_m ;
//?? why need st ??
assign signed_ldst_m = (ld_inst_vld_m | st_inst_vld_m) ?
l1hit_sign_extend_m : l2fill_sign_extend_m ;
//assign unsigned_ldst_m = ~signed_ldst_m ;
assign signed_ldst_byte_m = signed_ldst_m & byp_byte_m;
// assign unsigned_ldst_byte_m = unsigned_ldst_m & byp_byte_m;
assign signed_ldst_hw_m = signed_ldst_m & ( byp_byte_m | byp_hword_m );
// assign unsigned_ldst_hw_m = unsigned_ldst_m & ( byp_byte_m | byp_hword_m );
assign signed_ldst_w_m = signed_ldst_m & ( byp_byte_m | byp_hword_m | byp_word_m );
// assign unsigned_ldst_w_m = unsigned_ldst_m & ( byp_byte_m | byp_hword_m | byp_word_m );
//C assign align_bytes_msb[7:0] = (ld_inst_vld_unflushed | st_inst_vld_unflushed) ? lsu_l1hit_bytes_msb_g[7:0] :
//C (l2fill_vld_g ? l2fill_bytes_msb_g[7:0] : lsu_misc_bytes_msb_g[7:0]) ;
//assign align_bytes_msb[7:0] = (ld_inst_vld_unflushed | st_inst_vld_unflushed) ? lsu_l1hit_bytes_msb_g[7:0] :
// (lsu_irf_byp_data_src[2] ? lsu_misc_bytes_msb_g[7:0] : l2fill_bytes_msb_g[7:0]) ;
// For little-endian accesses, the following morphing must occur to the byte addr.
//
// Byte Addr(lower 3b)
// 000(0) -> 001(1) (hw)
// -> 011(3) (w)
// -> 111(7) (dw)
// 001(1) -> not morphed
// 010(2) -> 011(3) (hw)
// 011(3) -> not morphed
// 100(4) -> 101(5) (hw)
// -> 111(7) (w)
// 101(5) -> not morphed
// 110(6) -> 111(7) (hw)
// 111(7) -> not morphed
wire [7:0] merged_addr_m ;
wire [7:0] morphed_addr_m ;
//wire bendian ;
//assign merged_addr_m[7:0] = byp_baddr_m[15:8] | byp_baddr_m[7:0] ;
assign merged_addr_m[7:0] = byp_baddr_m[7:0] ;
assign morphed_addr_m[0]
= merged_addr_m[0] & ~(~bendian_pred_m & ~byp_byte_m) ;
assign morphed_addr_m[1]
= merged_addr_m[1] | (merged_addr_m[0] & ~bendian_pred_m & byp_hword_m) ;
assign morphed_addr_m[2]
= merged_addr_m[2] & ~(~bendian_pred_m & byp_hword_m) ;
assign morphed_addr_m[3]
= merged_addr_m[3] | (merged_addr_m[0] & ~bendian_pred_m & byp_word_m) |
(merged_addr_m[2] & ~bendian_pred_m & byp_hword_m) ;
assign morphed_addr_m[4]
= merged_addr_m[4] & ~(~bendian_pred_m & (byp_hword_m | byp_word_m)) ;
assign morphed_addr_m[5]
= merged_addr_m[5] | (merged_addr_m[4] & ~bendian_pred_m & byp_hword_m) ;
assign morphed_addr_m[6]
= merged_addr_m[6] & ~(~bendian_pred_m & byp_hword_m) ;
assign morphed_addr_m[7]
= merged_addr_m[7] | (merged_addr_m[0] & ~bendian_pred_m & ~(byp_byte_m | byp_hword_m | byp_word_m)) |
(merged_addr_m[4] & ~bendian_pred_m & byp_word_m) | (merged_addr_m[6] & ~bendian_pred_m & byp_hword_m) ;
//=========================================================================================
// ALIGNMENT CONTROL FOR DCDP
//=========================================================================================
// First generate control for swapping related to endianness.
// byte7-byte0 is source data from cache etc.
// swap7-swap0 is result of endianness swapping.
// First logical level - Swapping of bytes.
// Swap byte 0
wire swap0_sel_byte0, swap0_sel_byte1, swap0_sel_byte3 ;
wire swap1_sel_byte0, swap1_sel_byte1, swap1_sel_byte2, swap1_sel_byte6 ;
wire swap2_sel_byte1, swap2_sel_byte2, swap2_sel_byte3, swap2_sel_byte5 ;
wire swap3_sel_byte0, swap3_sel_byte2, swap3_sel_byte3, swap3_sel_byte4 ;
wire swap4_sel_byte3, swap4_sel_byte4, swap4_sel_byte5 ;
wire swap5_sel_byte2, swap5_sel_byte4, swap5_sel_byte5, swap5_sel_byte6 ;
wire swap6_sel_byte1, swap6_sel_byte5, swap6_sel_byte6 ;
wire swap7_sel_byte0, swap7_sel_byte4, swap7_sel_byte6, swap7_sel_byte7 ;
//assign bendian = bendian_pred_m ;
//assign bendian = lsu_bendian_access_g ;
assign swap0_sel_byte0 = bendian_pred_m | (~bendian_pred_m & byp_byte_m) ;
assign swap0_sel_byte1 = ~bendian_pred_m & byp_hword_m ;
assign swap0_sel_byte3 = ~bendian_pred_m & byp_word_m ;
// could be substituted with dword encoding.
//assign swap0_sel_byte7 = ~bendian_pred_m & ~(byp_word_m | byp_hword_m | byp_byte_m) ;
// Swap byp_byte_m 1
assign swap1_sel_byte0 = ~bendian_pred_m & byp_hword_m ;
assign swap1_sel_byte1 = bendian_pred_m | (~bendian_pred_m & byp_byte_m) ;
assign swap1_sel_byte2 = ~bendian_pred_m & byp_word_m ;
assign swap1_sel_byte6 = ~bendian_pred_m & ~(byp_word_m | byp_hword_m | byp_byte_m) ;
// Swap byp_byte_m 2
assign swap2_sel_byte1 = ~bendian_pred_m & byp_word_m ;
assign swap2_sel_byte2 = bendian_pred_m | (~bendian_pred_m & byp_byte_m) ;
assign swap2_sel_byte3 = ~bendian_pred_m & byp_hword_m ;
assign swap2_sel_byte5 = ~bendian_pred_m & ~(byp_word_m | byp_hword_m | byp_byte_m) ;
// Swap byp_byte_m 3
assign swap3_sel_byte0 = ~bendian_pred_m & byp_word_m ;
assign swap3_sel_byte2 = ~bendian_pred_m & byp_hword_m ;
assign swap3_sel_byte3 = bendian_pred_m | (~bendian_pred_m & byp_byte_m) ;
assign swap3_sel_byte4 = ~bendian_pred_m & ~(byp_word_m | byp_hword_m | byp_byte_m) ;
// Swap byp_byte_m 4
assign swap4_sel_byte3 = ~bendian_pred_m & ~(byp_word_m | byp_hword_m | byp_byte_m) ;
assign swap4_sel_byte4 = bendian_pred_m | (~bendian_pred_m & byp_byte_m) ;
assign swap4_sel_byte5 = ~bendian_pred_m & byp_hword_m ;
//assign swap4_sel_byte7 = ~bendian_pred_m & byp_word_m ;
// Swap byp_byte_m 5
assign swap5_sel_byte2 = ~bendian_pred_m & ~(byp_word_m | byp_hword_m | byp_byte_m) ;
assign swap5_sel_byte4 = ~bendian_pred_m & byp_hword_m ;
assign swap5_sel_byte5 = bendian_pred_m | (~bendian_pred_m & byp_byte_m) ;
assign swap5_sel_byte6 = ~bendian_pred_m & byp_word_m ;
// Swap byp_byte_m 6
assign swap6_sel_byte1 = ~bendian_pred_m & ~(byp_word_m | byp_hword_m | byp_byte_m) ;
assign swap6_sel_byte5 = ~bendian_pred_m & byp_word_m ;
assign swap6_sel_byte6 = bendian_pred_m | (~bendian_pred_m & byp_byte_m) ;
//assign swap6_sel_byte7 = ~bendian_pred_m & byp_hword_m ;
// Swap byp_byte_m 7
assign swap7_sel_byte0 = ~bendian_pred_m & ~(byp_word_m | byp_hword_m | byp_byte_m) ;
assign swap7_sel_byte4 = ~bendian_pred_m & byp_word_m ;
assign swap7_sel_byte6 = ~bendian_pred_m & byp_hword_m ;
assign swap7_sel_byte7 = bendian_pred_m | (~bendian_pred_m & byp_byte_m) ;
// 2nd logical level - Alignment.
// rjust7-rjust0 is result of alignment operation.
// sbyte7-sbyte0 is the result of the endian swapping from the 1st logic level.
wire rjust0_sel_sbyte0, rjust0_sel_sbyte1, rjust0_sel_sbyte2, rjust0_sel_sbyte3 ;
wire rjust0_sel_sbyte4, rjust0_sel_sbyte5, rjust0_sel_sbyte6, rjust0_sel_sbyte7 ;
wire rjust1_sel_sbyte1, rjust1_sel_sbyte3, rjust1_sel_sbyte5, rjust1_sel_sbyte7 ;
wire rjust2_sel_sbyte2, rjust2_sel_sbyte6 ;
wire rjust3_sel_sbyte3, rjust3_sel_sbyte7 ;
// Aligned Byte 0
assign rjust0_sel_sbyte0 =
~(rjust0_sel_sbyte1 | rjust0_sel_sbyte2 | rjust0_sel_sbyte3 |
rjust0_sel_sbyte4 | rjust0_sel_sbyte5 | rjust0_sel_sbyte6 |
rjust0_sel_sbyte7) ;
assign rjust0_sel_sbyte1 =
// ((byp_baddr_m[14] | byp_baddr_m[6]) & byp_byte_m) ;
((byp_baddr_m[6]) & byp_byte_m) ;
assign rjust0_sel_sbyte2 =
// ((byp_baddr_m[12] | byp_baddr_m[4]) & byp_hword_m) |
((byp_baddr_m[4]) & byp_hword_m) |
// ((byp_baddr_m[13] | byp_baddr_m[5]) & byp_byte_m) ;
((byp_baddr_m[5]) & byp_byte_m) ;
assign rjust0_sel_sbyte3 =
// (byp_baddr_m[12] | byp_baddr_m[4]) & byp_byte_m ;
(byp_baddr_m[4]) & byp_byte_m ;
assign rjust0_sel_sbyte4 =
// ((byp_baddr_m[10] | byp_baddr_m[2]) & byp_hword_m) |
// ((byp_baddr_m[11] | byp_baddr_m[3]) & byp_byte_m) |
// ((byp_baddr_m[8] | byp_baddr_m[0]) & byp_word_m) ;
((byp_baddr_m[2]) & byp_hword_m) |
((byp_baddr_m[3]) & byp_byte_m) |
((byp_baddr_m[0]) & byp_word_m) ;
assign rjust0_sel_sbyte5 =
// ((byp_baddr_m[10] | byp_baddr_m[2]) & byp_byte_m) ;
((byp_baddr_m[2]) & byp_byte_m) ;
assign rjust0_sel_sbyte6 =
// ((byp_baddr_m[8] | byp_baddr_m[0]) & byp_hword_m) |
// ((byp_baddr_m[9] | byp_baddr_m[1]) & byp_byte_m) ;
((byp_baddr_m[0]) & byp_hword_m) |
((byp_baddr_m[1]) & byp_byte_m) ;
assign rjust0_sel_sbyte7 =
// (byp_baddr_m[8] | byp_baddr_m[0]) & byp_byte_m ;
(byp_baddr_m[0]) & byp_byte_m ;
// Aligned Byte 1
assign rjust1_sel_sbyte1 =
~(rjust1_sel_sbyte3 | rjust1_sel_sbyte5 | rjust1_sel_sbyte7) ;
assign rjust1_sel_sbyte3 =
// (byp_baddr_m[12] | byp_baddr_m[4]) & byp_hword_m ;
(byp_baddr_m[4]) & byp_hword_m ;
assign rjust1_sel_sbyte5 =
// ((byp_baddr_m[10] | byp_baddr_m[2]) & byp_hword_m) |
// ((byp_baddr_m[8] | byp_baddr_m[0]) & byp_word_m) ;
((byp_baddr_m[2]) & byp_hword_m) |
((byp_baddr_m[0]) & byp_word_m) ;
assign rjust1_sel_sbyte7 =
// (byp_baddr_m[8] | byp_baddr_m[0]) & byp_hword_m ;
(byp_baddr_m[0]) & byp_hword_m ;
// Aligned Byte 2
assign rjust2_sel_sbyte2 = ~rjust2_sel_sbyte6 ;
//assign rjust2_sel_sbyte6 = (byp_baddr_m[8] | byp_baddr_m[0]) & byp_word_m ;
assign rjust2_sel_sbyte6 = (byp_baddr_m[0]) & byp_word_m ;
// Aligned Byte 3
assign rjust3_sel_sbyte3 = ~rjust3_sel_sbyte7 ;
//assign rjust3_sel_sbyte7 = (byp_baddr_m[8] | byp_baddr_m[0]) & byp_word_m ;
assign rjust3_sel_sbyte7 = (byp_baddr_m[0]) & byp_word_m ;
// 3rd logical level - Complete alignment. Sign-Extension/Zero-Extension.
// merge7-merge0 corresponds to cumulative swapping and alignment result.
// byte[7]-byte[0] refers to the original pre-swap/alignment data.
wire merge7_sel_byte0_m, merge7_sel_byte7_m;
wire merge6_sel_byte1_m, merge6_sel_byte6_m;
wire merge5_sel_byte2_m, merge5_sel_byte5_m;
wire merge4_sel_byte3_m, merge4_sel_byte4_m;
wire merge3_sel_byte0_m, merge3_sel_byte3_m;
wire merge3_sel_byte4_m, merge3_sel_byte7_m,merge3_sel_byte_m;
wire merge2_sel_byte1_m, merge2_sel_byte2_m, merge2_sel_byte5_m;
wire merge2_sel_byte6_m, merge2_sel_byte_m;
wire merge0_sel_byte0_m, merge0_sel_byte1_m;
wire merge0_sel_byte2_m, merge0_sel_byte3_m;
wire merge0_sel_byte4_m, merge0_sel_byte5_m;
wire merge0_sel_byte6_m;
wire merge1_sel_byte0_m, merge1_sel_byte1_m;
wire merge1_sel_byte2_m, merge1_sel_byte3_m;
wire merge1_sel_byte4_m, merge1_sel_byte5_m;
wire merge1_sel_byte6_m, merge1_sel_byte7_m;
wire merge0_sel_byte_1h_m,merge1_sel_byte_1h_m, merge1_sel_byte_2h_m;
// Final Merged Byte 0
assign merge0_sel_byte0_m =
(rjust0_sel_sbyte0 & swap0_sel_byte0) |
(rjust0_sel_sbyte1 & swap1_sel_byte0) |
(rjust0_sel_sbyte3 & swap3_sel_byte0) |
(rjust0_sel_sbyte7 & swap7_sel_byte0) ;
assign merge0_sel_byte1_m =
(rjust0_sel_sbyte0 & swap0_sel_byte1) |
(rjust0_sel_sbyte1 & swap1_sel_byte1) |
(rjust0_sel_sbyte2 & swap2_sel_byte1) |
(rjust0_sel_sbyte6 & swap6_sel_byte1) ;
assign merge0_sel_byte2_m =
(rjust0_sel_sbyte1 & swap1_sel_byte2) |
(rjust0_sel_sbyte2 & swap2_sel_byte2) |
(rjust0_sel_sbyte3 & swap3_sel_byte2) |
(rjust0_sel_sbyte5 & swap5_sel_byte2) ;
assign merge0_sel_byte3_m =
(rjust0_sel_sbyte0 & swap0_sel_byte3) |
(rjust0_sel_sbyte2 & swap2_sel_byte3) |
(rjust0_sel_sbyte3 & swap3_sel_byte3) |
(rjust0_sel_sbyte4 & swap4_sel_byte3) ;
assign merge0_sel_byte3_default_m = ~ (merge0_sel_byte0_m | merge0_sel_byte1_m | merge0_sel_byte2_m);
assign merge0_sel_byte4_m =
(rjust0_sel_sbyte3 & swap3_sel_byte4) |
(rjust0_sel_sbyte4 & swap4_sel_byte4) |
(rjust0_sel_sbyte5 & swap5_sel_byte4) |
(rjust0_sel_sbyte7 & swap7_sel_byte4) ;
assign merge0_sel_byte5_m =
(rjust0_sel_sbyte2 & swap2_sel_byte5) |
(rjust0_sel_sbyte4 & swap4_sel_byte5) |
(rjust0_sel_sbyte5 & swap5_sel_byte5) |
(rjust0_sel_sbyte6 & swap6_sel_byte5) ;
assign merge0_sel_byte6_m =
(rjust0_sel_sbyte1 & swap1_sel_byte6) |
(rjust0_sel_sbyte5 & swap5_sel_byte6) |
(rjust0_sel_sbyte6 & swap6_sel_byte6) |
(rjust0_sel_sbyte7 & swap7_sel_byte6) ;
//assign merge0_sel_byte7_m =
// (rjust0_sel_sbyte0 & swap0_sel_byte7) |
// (rjust0_sel_sbyte4 & swap4_sel_byte7) |
// (rjust0_sel_sbyte6 & swap6_sel_byte7) |
// (rjust0_sel_sbyte7 & swap7_sel_byte7) ;
assign merge0_sel_byte7_default_m = ~(merge0_sel_byte4_m | merge0_sel_byte5_m | merge0_sel_byte6_m);
assign merge0_sel_byte_1h_m =
merge0_sel_byte0_m | merge0_sel_byte1_m | merge0_sel_byte2_m | merge0_sel_byte3_m ;
// Final Merged Byte 1
assign merge1_sel_byte0_m =
(rjust1_sel_sbyte1 & swap1_sel_byte0) |
(rjust1_sel_sbyte3 & swap3_sel_byte0) |
(rjust1_sel_sbyte7 & swap7_sel_byte0) ;
assign merge1_sel_byte1_m =
(rjust1_sel_sbyte1 & swap1_sel_byte1) ;
assign merge1_sel_byte2_m =
(rjust1_sel_sbyte1 & swap1_sel_byte2) |
(rjust1_sel_sbyte3 & swap3_sel_byte2) |
(rjust1_sel_sbyte5 & swap5_sel_byte2) ;
assign merge1_sel_byte3_m =
(rjust1_sel_sbyte3 & swap3_sel_byte3) ;
assign merge1_sel_byte3_default_m = ~( merge1_sel_byte0_m | merge1_sel_byte1_m | merge1_sel_byte2_m);
assign merge1_sel_byte4_m =
(rjust1_sel_sbyte3 & swap3_sel_byte4) |
(rjust1_sel_sbyte5 & swap5_sel_byte4) |
(rjust1_sel_sbyte7 & swap7_sel_byte4) ;
assign merge1_sel_byte5_m =
(rjust1_sel_sbyte5 & swap5_sel_byte5) ;
assign merge1_sel_byte6_m =
(rjust1_sel_sbyte1 & swap1_sel_byte6) |
(rjust1_sel_sbyte5 & swap5_sel_byte6) |
(rjust1_sel_sbyte7 & swap7_sel_byte6) ;
assign merge1_sel_byte7_m =
(rjust1_sel_sbyte7 & swap7_sel_byte7) ;
assign merge1_sel_byte7_default_m = ~( merge1_sel_byte4_m | merge1_sel_byte5_m | merge1_sel_byte6_m);
assign merge1_sel_byte_1h_m = ~byp_byte_m &
(merge1_sel_byte0_m | merge1_sel_byte1_m | merge1_sel_byte2_m | merge1_sel_byte3_m) ;
assign merge1_sel_byte_2h_m = ~byp_byte_m &
(merge1_sel_byte4_m | merge1_sel_byte5_m | merge1_sel_byte6_m | merge1_sel_byte7_m) ;
// Final Merged Byte 2
assign merge2_sel_byte1_m =
(rjust2_sel_sbyte2 & swap2_sel_byte1) |
(rjust2_sel_sbyte6 & swap6_sel_byte1) ;
assign merge2_sel_byte2_m =
(rjust2_sel_sbyte2 & swap2_sel_byte2) ;
assign merge2_sel_byte5_m =
(rjust2_sel_sbyte2 & swap2_sel_byte5) |
(rjust2_sel_sbyte6 & swap6_sel_byte5) ;
assign merge2_sel_byte6_m =
(rjust2_sel_sbyte6 & swap6_sel_byte6) ;
assign merge2_sel_byte6_default_m = ~(merge2_sel_byte1_m | merge2_sel_byte2_m | merge2_sel_byte5_m);
assign merge2_sel_byte_m = ~byp_byte_m & ~byp_hword_m &
(merge2_sel_byte1_m | merge2_sel_byte2_m | merge2_sel_byte5_m | merge2_sel_byte6_m);
// Final Merged Byte 3
assign merge3_sel_byte0_m =
(rjust3_sel_sbyte3 & swap3_sel_byte0) |
(rjust3_sel_sbyte7 & swap7_sel_byte0) ;
assign merge3_sel_byte3_m =
(rjust3_sel_sbyte3 & swap3_sel_byte3) ;
assign merge3_sel_byte4_m =
(rjust3_sel_sbyte3 & swap3_sel_byte4) |
(rjust3_sel_sbyte7 & swap7_sel_byte4) ;
assign merge3_sel_byte7_m =
(rjust3_sel_sbyte7 & swap7_sel_byte7) ;
assign merge3_sel_byte7_default_m = ~(merge3_sel_byte0_m | merge3_sel_byte3_m | merge3_sel_byte4_m);
assign merge3_sel_byte_m = ~byp_byte_m & ~byp_hword_m &
(merge3_sel_byte0_m | merge3_sel_byte3_m | merge3_sel_byte4_m | merge3_sel_byte7_m);
// Final Merged Byte 4
assign merge4_sel_byte3_m = byp_dword_m & swap4_sel_byte3 ;
assign merge4_sel_byte4_m = byp_dword_m & swap4_sel_byte4 ;
// Final Merged Byte 5
assign merge5_sel_byte2_m = byp_dword_m & swap5_sel_byte2 ;
assign merge5_sel_byte5_m = byp_dword_m & swap5_sel_byte5 ;
// Final Merged Byte 6
assign merge6_sel_byte1_m = byp_dword_m & swap6_sel_byte1 ;
assign merge6_sel_byte6_m = byp_dword_m & swap6_sel_byte6 ;
// Final Merged Byte 7
assign merge7_sel_byte0_m = byp_dword_m & swap7_sel_byte0 ;
assign merge7_sel_byte7_m = byp_dword_m & swap7_sel_byte7 ;
//=========================================================================================
// STQ/CAS 2ND PKT FORMATTING
//=========================================================================================
// stq and cas write to an extra buffer. stq always uses a full 64bits.
// cas may use either 64b or 32b. stq requires at most endian alignment.
// cas may require both address and endian alignment.
// Byte Alignment. Assume 8 bytes, 7-0
// Case 1 : 7,6,5,4,3,2,1,0
// Case 2 : 3,2,1,0,0,1,2,3
// Case 3 : 0,1,2,3,4,5,6,7
wire casa_wd_g ;
assign casa_wd_g = casa_g & byp_word_g ;
wire casa_dwd_g ;
assign casa_dwd_g = casa_g & ~byp_word_g ;
// Change bendian to bendian_g - should not be dependent on fill.
//assign lsu_atomic_pkt2_bsel_g[2] = // Case 1
// (casa_dwd_g & bendian_g) | // bendian stq and dw cas
// (casa_wd_g & bendian_g & ldst_va_g[2]) ; // bendian_g wd casa addr to uhalf
assign lsu_atomic_pkt2_bsel_g[2] = ~| (lsu_atomic_pkt2_bsel_g[1:0]) | rst_tri_en ; //one-hot default
assign lsu_atomic_pkt2_bsel_g[1] = // Case 2
((casa_wd_g & bendian_g & ~ldst_va_g[2]) | // bendian_g wd casa addr to lhalf
(casa_wd_g & ~bendian_g & ldst_va_g[2])) & ~rst_tri_en ; // lendian wd casa addr to uhalf
assign lsu_atomic_pkt2_bsel_g[0] = // Case 3
((casa_dwd_g & ~bendian_g) | // lendian stq and dw cas
(casa_wd_g & ~bendian_g & ~ldst_va_g[2])) & ~rst_tri_en ; // lendian wd cas addr to lhalf
// Alignment done in qdp1
//=========================================================================================
// ASI DECODE
//=========================================================================================
// Note : tlb_byp_asi same as phy_use/phy_byp asi.
lsu_asi_decode asi_decode (/*AUTOINST*/
// Outputs
.asi_internal_d(asi_internal_d),
.nucleus_asi_d(nucleus_asi_d),
.primary_asi_d(primary_asi_d),
.secondary_asi_d(secondary_asi_d),
.lendian_asi_d(lendian_asi_d),
.nofault_asi_d(nofault_asi_d),
.quad_asi_d (quad_asi_d),
.binit_quad_asi_d(binit_quad_asi_d),
.dcache_byp_asi_d(dcache_byp_asi_d),
.tlb_lng_ltncy_asi_d(tlb_lng_ltncy_asi_d),
.tlb_byp_asi_d(tlb_byp_asi_d),
.as_if_user_asi_d(as_if_user_asi_d),
.atomic_asi_d(atomic_asi_d),
.blk_asi_d (blk_asi_d),
.dc_diagnstc_asi_d(dc_diagnstc_asi_d),
.dtagv_diagnstc_asi_d(dtagv_diagnstc_asi_d),
.wr_only_asi_d(wr_only_asi_d),
.rd_only_asi_d(rd_only_asi_d),
.unimp_asi_d (unimp_asi_d),
.ifu_nontlb_asi_d(ifu_nontlb_asi_d),
.recognized_asi_d(recognized_asi_d),
.ifill_tlb_asi_d(ifill_tlb_asi_d),
.dfill_tlb_asi_d(dfill_tlb_asi_d),
.rd_only_ltlb_asi_d(rd_only_ltlb_asi_d),
.wr_only_ltlb_asi_d(wr_only_ltlb_asi_d),
.phy_use_ec_asi_d(phy_use_ec_asi_d),
.phy_byp_ec_asi_d(phy_byp_ec_asi_d),
.mmu_rd_only_asi_d(mmu_rd_only_asi_d),
.intrpt_disp_asi_d(intrpt_disp_asi_d),
.dmmu_asi58_d(dmmu_asi58_d),
.immu_asi50_d(immu_asi50_d),
// Inputs
.asi_d (asi_d[7:0]));
dff_s #(31) asidcd_stge (
.din ({asi_internal_d,primary_asi_d,secondary_asi_d,nucleus_asi_d,
lendian_asi_d, tlb_byp_asi_d, dcache_byp_asi_d,nofault_asi_d,
tlb_lng_ltncy_asi_d,as_if_user_asi_d,atomic_asi_d, blk_asi_d,
dc_diagnstc_asi_d,dtagv_diagnstc_asi_d,
wr_only_asi_d, rd_only_asi_d,mmu_rd_only_asi_d,unimp_asi_d,dmmu_asi58_d, immu_asi50_d, quad_asi_d, binit_quad_asi_d,
ifu_nontlb_asi_d,recognized_asi_d, ifill_tlb_asi_d,
dfill_tlb_asi_d, rd_only_ltlb_asi_d,wr_only_ltlb_asi_d,phy_use_ec_asi_d, phy_byp_ec_asi_d, intrpt_disp_asi_d}),
.q ({asi_internal_e,primary_asi_e,secondary_asi_e,nucleus_asi_e,
lendian_asi_e, tlb_byp_asi_e, dcache_byp_asi_e,nofault_asi_e,
tlb_lng_ltncy_asi_e,as_if_user_asi_e,atomic_asi_e, blk_asi_e,
dc_diagnstc_asi_e,dtagv_diagnstc_asi_e,
wr_only_asi_e, rd_only_asi_e,mmu_rd_only_asi_e,unimp_asi_e,dmmu_asi58_e, immu_asi50_e, quad_asi_e, binit_quad_asi_e,
ifu_nontlb_asi_e,recognized_asi_e,ifill_tlb_asi_e,
dfill_tlb_asi_e,rd_only_ltlb_asi_e,wr_only_ltlb_asi_e,phy_use_ec_asi_e, phy_byp_ec_asi_e, intrpt_disp_asi_e}),
.clk (clk),
.se (se), .si (), .so ()
);
assign lsu_ffu_blk_asi_e = blk_asi_e & alt_space_e;
assign lsu_quad_asi_e = quad_asi_e ;
wire unimp_asi_tmp ;
dff_s #(23) asidcd_stgm (
.din ({asi_internal_e,dcache_byp_asi_e,nofault_asi_e,lendian_asi_e,tlb_lng_ltncy_asi_e,
as_if_user_asi_e,atomic_asi_e, blk_asi_e,dc_diagnstc_asi_e,dtagv_diagnstc_asi_e,
wr_only_asi_e, rd_only_asi_e,mmu_rd_only_asi_e,unimp_asi_e,dmmu_asi58_e, immu_asi50_e, quad_asi_e,binit_quad_asi_e,recognized_asi_e,
ifu_nontlb_asi_e,phy_use_ec_asi_e, phy_byp_ec_asi_e, intrpt_disp_asi_e}),
.q ({asi_internal_m,dcache_byp_asi_m,nofault_asi_m,lendian_asi_m,tlb_lng_ltncy_asi_m,
as_if_user_asi_m,atomic_asi_m, blk_asi_m,dc_diagnstc_asi_m,dtagv_diagnstc_asi_m,
wr_only_asi_m, rd_only_asi_m,mmu_rd_only_asi_m,unimp_asi_tmp,dmmu_asi58_m, immu_asi50_m, quad_asi_m,binit_quad_asi_m,recognized_asi_tmp,
ifu_nontlb_asi_m,phy_use_ec_asi_m, phy_byp_ec_asi_m, intrpt_disp_asi_m}),
.clk (clk),
.se (se), .si (), .so ()
);
assign lsu_blk_asi_m = blk_asi_m ;
wire pa_wtchpt_unimp_m ; // Bug 3408
wire d_tsb_unimp_m, i_tsb_unimp_m, pctxt_unimp_m, sctxt_unimp_m;
wire unimp_m;
assign pa_wtchpt_unimp_m = dmmu_asi58_m & (lsu_ldst_va_b7_b0_m[7:0] == 8'h40);
assign d_tsb_unimp_m = dmmu_asi58_m & (lsu_ldst_va_b7_b0_m[7:0] == 8'h28);
assign pctxt_unimp_m = dmmu_asi58_m & (lsu_ldst_va_b7_b0_m[7:0] == 8'h8);
assign sctxt_unimp_m = dmmu_asi58_m & (lsu_ldst_va_b7_b0_m[7:0] == 8'h10);
assign i_tsb_unimp_m = immu_asi50_m & (lsu_ldst_va_b7_b0_m[7:0] == 8'h28);
assign unimp_m = pa_wtchpt_unimp_m |
d_tsb_unimp_m | i_tsb_unimp_m |
pctxt_unimp_m | sctxt_unimp_m;
assign unimp_asi_m = unimp_asi_tmp | unimp_m ;
assign recognized_asi_m = recognized_asi_tmp | unimp_m ;
dff_s #(12) asidcd_stgg (
.din ({asi_internal_m,dcache_byp_asi_m, lendian_asi_m,tlb_lng_ltncy_asi_m,
blk_asi_m,dc_diagnstc_asi_m,dtagv_diagnstc_asi_m,quad_asi_m,
binit_quad_asi_m,recognized_asi_m,ifu_nontlb_asi_m, intrpt_disp_asi_m}),
.q ({asi_internal_g,dcache_byp_asi_g, lendian_asi_g,tlb_lng_ltncy_asi_g,
blk_asi_g,dc_diagnstc_asi_g,dtagv_diagnstc_asi_g,quad_asi_g,
binit_quad_asi_g,recognized_asi_g,ifu_nontlb_asi_g, intrpt_disp_asi_g}),
.clk (clk),
.se (se), .si (), .so ()
);
//assign lsu_quad_asi_g = quad_asi_g;
assign ncache_asild_rq_g = dcache_byp_asi_g & altspace_ldst_g ;
//st data alignment control signals
wire st_sz_hw_g, st_sz_w_g, st_sz_dw_g, stdbl_g;
wire stdbl_m;
//assign stdbl_m = ldst_dbl_m & (~lsu_alt_space_m | (lsu_alt_space_m & ~blk_asi_m)) ;
assign stdbl_m = ldst_dbl_m ;
dff_s #(4) ff_st_sz_m (
.din ({hw_size, wd_size, dw_size, stdbl_m }),
.q ({st_sz_hw_g, st_sz_w_g, st_sz_dw_g, stdbl_g}),
.clk (clk),
.se (se), .si (), .so ()
);
//assign bendian = lsu_bendian_access_g ; // bendian store
wire swap_sel_default_g, swap_sel_default_byte_7_2_g, st_hw_le_g,st_w_or_dbl_le_g,st_x_le_g;
assign bendian_g = ~l1hit_lendian_g ;
//assign swap_sel_default_g = (bendian_g | (~bendian_g & st_sz_b_g)) ;
assign swap_sel_default_g = ~ (st_hw_le_g | st_w_or_dbl_le_g | st_x_le_g);
assign swap_sel_default_byte_7_2_g = ~ (st_w_or_dbl_le_g | st_x_le_g);
assign st_hw_le_g = (st_sz_hw_g & ~bendian_g) & (~stdbl_g | fp_ldst_g) & st_inst_vld_unflushed ; //0-in bug
//bug 3169
// std(a) on floating point is the same as stx(a)
assign st_w_or_dbl_le_g = ((st_sz_w_g | (stdbl_g & ~fp_ldst_g)) & ~bendian_g) & st_inst_vld_unflushed ;
assign st_x_le_g = (st_sz_dw_g & (~stdbl_g | fp_ldst_g) & ~bendian_g) & st_inst_vld_unflushed;
wire blkst_m_tmp ;
dff_s stgm_bst (
.din (ffu_lsu_blk_st_e),
.q (blkst_m_tmp),
.clk (clk),
.se (se), .si (), .so ()
);
assign blkst_m = blkst_m_tmp & ~(st_inst_vld_m | flsh_inst_m
| ld_inst_vld_m) ; // Bug 3444
assign lsu_blk_st_m = blkst_m ;
dff_s stgg_bst (
.din (blkst_m),
.q (blkst_g),
.clk (clk),
.se (se), .si (), .so ()
);
wire bst_swap_sel_default_g, bst_swap_sel_default_byte_7_2_g,bst_st_hw_le_g,bst_st_w_or_dbl_le_g,bst_st_x_le_g;
assign lsu_swap_sel_default_g = (blkst_g ? bst_swap_sel_default_g : swap_sel_default_g) | rst_tri_en ;
assign lsu_swap_sel_default_byte_7_2_g = (blkst_g ? bst_swap_sel_default_byte_7_2_g : swap_sel_default_byte_7_2_g)
| rst_tri_en ;
assign lsu_st_hw_le_g = (blkst_g ? bst_st_hw_le_g : st_hw_le_g) & ~rst_tri_en ;
assign lsu_st_w_or_dbl_le_g = (blkst_g ? bst_st_w_or_dbl_le_g : st_w_or_dbl_le_g) & ~rst_tri_en ;
assign lsu_st_x_le_g = (blkst_g ? bst_st_x_le_g : st_x_le_g) & ~rst_tri_en ;
//=========================================================================================
// BLK STORE
//=========================================================================================
// Blk-St Handling : Snap state in g-stage of issue from IFU.
wire snap_blk_st_m,snap_blk_st_g ;
assign snap_blk_st_m = st_inst_vld_m & blk_asi_m & lsu_alt_space_m & fp_ldst_m;
assign lsu_snap_blk_st_m = snap_blk_st_m ;
wire snap_blk_st_local_m;
assign snap_blk_st_local_m = snap_blk_st_m & ifu_tlu_inst_vld_m ;
dff_s stgg_snap (
.din (snap_blk_st_local_m),
.q (snap_blk_st_g),
.clk (clk),
.se (se), .si (), .so ()
);
// output to be used in g-stage.
dffe_s #(5) bst_state_g (
.din ({lsu_swap_sel_default_g, lsu_swap_sel_default_byte_7_2_g, lsu_st_hw_le_g,
lsu_st_w_or_dbl_le_g,lsu_st_x_le_g}),
.q ({bst_swap_sel_default_g, bst_swap_sel_default_byte_7_2_g, bst_st_hw_le_g,
bst_st_w_or_dbl_le_g,bst_st_x_le_g}),
.en (snap_blk_st_g),
.clk (clk),
.se (se), .si (), .so ()
);
// snapped in g, used in m
wire [39:10] blkst_pgnum_m;
dffe_s #(30) bst_pg_g (
.din (tlb_pgnum[39:10]),
.q (blkst_pgnum_m[39:10]),
.en (snap_blk_st_g),
.clk (clk),
.se (se), .si (), .so ()
);
bw_u1_minbuf_5x UZfix_lsu_blkst_pgnum_m_b10 (.a(blkst_pgnum_m[10]), .z(lsu_blkst_pgnum_m[10]));
bw_u1_minbuf_5x UZfix_lsu_blkst_pgnum_m_b11 (.a(blkst_pgnum_m[11]), .z(lsu_blkst_pgnum_m[11]));
bw_u1_minbuf_5x UZfix_lsu_blkst_pgnum_m_b12 (.a(blkst_pgnum_m[12]), .z(lsu_blkst_pgnum_m[12]));
bw_u1_minbuf_5x UZfix_lsu_blkst_pgnum_m_b13 (.a(blkst_pgnum_m[13]), .z(lsu_blkst_pgnum_m[13]));
bw_u1_minbuf_5x UZfix_lsu_blkst_pgnum_m_b14 (.a(blkst_pgnum_m[14]), .z(lsu_blkst_pgnum_m[14]));
bw_u1_minbuf_5x UZfix_lsu_blkst_pgnum_m_b15 (.a(blkst_pgnum_m[15]), .z(lsu_blkst_pgnum_m[15]));
bw_u1_minbuf_5x UZfix_lsu_blkst_pgnum_m_b16 (.a(blkst_pgnum_m[16]), .z(lsu_blkst_pgnum_m[16]));
bw_u1_minbuf_5x UZfix_lsu_blkst_pgnum_m_b17 (.a(blkst_pgnum_m[17]), .z(lsu_blkst_pgnum_m[17]));
bw_u1_minbuf_5x UZfix_lsu_blkst_pgnum_m_b18 (.a(blkst_pgnum_m[18]), .z(lsu_blkst_pgnum_m[18]));
bw_u1_minbuf_5x UZfix_lsu_blkst_pgnum_m_b19 (.a(blkst_pgnum_m[19]), .z(lsu_blkst_pgnum_m[19]));
bw_u1_minbuf_5x UZfix_lsu_blkst_pgnum_m_b20 (.a(blkst_pgnum_m[20]), .z(lsu_blkst_pgnum_m[20]));
bw_u1_minbuf_5x UZfix_lsu_blkst_pgnum_m_b21 (.a(blkst_pgnum_m[21]), .z(lsu_blkst_pgnum_m[21]));
bw_u1_minbuf_5x UZfix_lsu_blkst_pgnum_m_b22 (.a(blkst_pgnum_m[22]), .z(lsu_blkst_pgnum_m[22]));
bw_u1_minbuf_5x UZfix_lsu_blkst_pgnum_m_b23 (.a(blkst_pgnum_m[23]), .z(lsu_blkst_pgnum_m[23]));
bw_u1_minbuf_5x UZfix_lsu_blkst_pgnum_m_b24 (.a(blkst_pgnum_m[24]), .z(lsu_blkst_pgnum_m[24]));
bw_u1_minbuf_5x UZfix_lsu_blkst_pgnum_m_b25 (.a(blkst_pgnum_m[25]), .z(lsu_blkst_pgnum_m[25]));
bw_u1_minbuf_5x UZfix_lsu_blkst_pgnum_m_b26 (.a(blkst_pgnum_m[26]), .z(lsu_blkst_pgnum_m[26]));
bw_u1_minbuf_5x UZfix_lsu_blkst_pgnum_m_b27 (.a(blkst_pgnum_m[27]), .z(lsu_blkst_pgnum_m[27]));
bw_u1_minbuf_5x UZfix_lsu_blkst_pgnum_m_b28 (.a(blkst_pgnum_m[28]), .z(lsu_blkst_pgnum_m[28]));
bw_u1_minbuf_5x UZfix_lsu_blkst_pgnum_m_b29 (.a(blkst_pgnum_m[29]), .z(lsu_blkst_pgnum_m[29]));
bw_u1_minbuf_5x UZfix_lsu_blkst_pgnum_m_b30 (.a(blkst_pgnum_m[30]), .z(lsu_blkst_pgnum_m[30]));
bw_u1_minbuf_5x UZfix_lsu_blkst_pgnum_m_b31 (.a(blkst_pgnum_m[31]), .z(lsu_blkst_pgnum_m[31]));
bw_u1_minbuf_5x UZfix_lsu_blkst_pgnum_m_b32 (.a(blkst_pgnum_m[32]), .z(lsu_blkst_pgnum_m[32]));
bw_u1_minbuf_5x UZfix_lsu_blkst_pgnum_m_b33 (.a(blkst_pgnum_m[33]), .z(lsu_blkst_pgnum_m[33]));
bw_u1_minbuf_5x UZfix_lsu_blkst_pgnum_m_b34 (.a(blkst_pgnum_m[34]), .z(lsu_blkst_pgnum_m[34]));
bw_u1_minbuf_5x UZfix_lsu_blkst_pgnum_m_b35 (.a(blkst_pgnum_m[35]), .z(lsu_blkst_pgnum_m[35]));
bw_u1_minbuf_5x UZfix_lsu_blkst_pgnum_m_b36 (.a(blkst_pgnum_m[36]), .z(lsu_blkst_pgnum_m[36]));
bw_u1_minbuf_5x UZfix_lsu_blkst_pgnum_m_b37 (.a(blkst_pgnum_m[37]), .z(lsu_blkst_pgnum_m[37]));
bw_u1_minbuf_5x UZfix_lsu_blkst_pgnum_m_b38 (.a(blkst_pgnum_m[38]), .z(lsu_blkst_pgnum_m[38]));
bw_u1_minbuf_5x UZfix_lsu_blkst_pgnum_m_b39 (.a(blkst_pgnum_m[39]), .z(lsu_blkst_pgnum_m[39]));
//=========================================================================================
// Prefetch Count
//=========================================================================================
wire [3:0] lsu_cpx_pref_ack;
wire [3:0] no_spc_pref;
wire [3:0] pref_ackcnt0,pref_ackcnt1,pref_ackcnt2,pref_ackcnt3 ;
wire [3:0] pref_ackcnt0_din,pref_ackcnt1_din,pref_ackcnt2_din,pref_ackcnt3_din ;
wire [3:0] pref_ackcnt_incr, pref_ackcnt_decr ;
wire [3:0] pref_ackcnt_mx_incr, pref_ackcnt_mx_decr ;
wire lsu_pref_pcx_req_d1;
dff_s #(1) pref_pcx_req_stg (
.din (lsu_pref_pcx_req),
.q (lsu_pref_pcx_req_d1),
.clk (clk),
.se (se), .si (), .so ()
);
assign lsu_pcx_pref_issue[0] = lsu_pref_pcx_req_d1 & lsu_ld_pcx_rq_sel_d2[0] & ~lsu_pcx_req_squash_d1;
assign lsu_pcx_pref_issue[1] = lsu_pref_pcx_req_d1 & lsu_ld_pcx_rq_sel_d2[1] & ~lsu_pcx_req_squash_d1;
assign lsu_pcx_pref_issue[2] = lsu_pref_pcx_req_d1 & lsu_ld_pcx_rq_sel_d2[2] & ~lsu_pcx_req_squash_d1;
assign lsu_pcx_pref_issue[3] = lsu_pref_pcx_req_d1 & lsu_ld_pcx_rq_sel_d2[3] & ~lsu_pcx_req_squash_d1;
wire [3:0] pref_acknt_mx_incr_sel;
assign pref_acknt_mx_incr_sel[3:0] = lsu_pcx_pref_issue[3:0];
assign pref_ackcnt_mx_incr[3:0] =
(pref_acknt_mx_incr_sel[0] ? pref_ackcnt0[3:0] : 4'b0) |
(pref_acknt_mx_incr_sel[1] ? pref_ackcnt1[3:0] : 4'b0) |
(pref_acknt_mx_incr_sel[2] ? pref_ackcnt2[3:0] : 4'b0) |
(pref_acknt_mx_incr_sel[3] ? pref_ackcnt3[3:0] : 4'b0) ;
//====================================================================================
// prefetch ack back from CPX
wire dcfill_active_e;
assign dcfill_active_e = lsu_dfq_ld_vld & ~memref_e ;
wire dfq_thread0, dfq_thread1, dfq_thread2, dfq_thread3;
assign dfq_thread0 = dfill_thread0;
assign dfq_thread1 = dfill_thread1;
assign dfq_thread2 = dfill_thread2;
assign dfq_thread3 = dfill_thread3;
assign lsu_cpx_pref_ack[0] = dfq_thread0 & dcfill_active_e & lsu_cpx_pkt_prefetch2;
assign lsu_cpx_pref_ack[1] = dfq_thread1 & dcfill_active_e & lsu_cpx_pkt_prefetch2;
assign lsu_cpx_pref_ack[2] = dfq_thread2 & dcfill_active_e & lsu_cpx_pkt_prefetch2;
assign lsu_cpx_pref_ack[3] = dfq_thread3 & dcfill_active_e & lsu_cpx_pkt_prefetch2;
wire [3:0] pref_acknt_mx_decr_sel;
assign pref_acknt_mx_decr_sel[3:0] = lsu_cpx_pref_ack[3:0];
assign pref_ackcnt_mx_decr[3:0] =
(pref_acknt_mx_decr_sel[0] ? pref_ackcnt0[3:0] : 4'b0) |
(pref_acknt_mx_decr_sel[1] ? pref_ackcnt1[3:0] : 4'b0) |
(pref_acknt_mx_decr_sel[2] ? pref_ackcnt2[3:0] : 4'b0) |
(pref_acknt_mx_decr_sel[3] ? pref_ackcnt3[3:0] : 4'b0) ;
assign pref_ackcnt_incr[3:0] = pref_ackcnt_mx_incr[3:0] + 4'b0001 ;
assign pref_ackcnt_decr[3:0] = pref_ackcnt_mx_decr[3:0] - 4'b0001 ;
assign pref_ackcnt0_din[3:0] = lsu_cpx_pref_ack[0] ? pref_ackcnt_decr[3:0] : pref_ackcnt_incr[3:0] ;
assign pref_ackcnt1_din[3:0] = lsu_cpx_pref_ack[1] ? pref_ackcnt_decr[3:0] : pref_ackcnt_incr[3:0] ;
assign pref_ackcnt2_din[3:0] = lsu_cpx_pref_ack[2] ? pref_ackcnt_decr[3:0] : pref_ackcnt_incr[3:0] ;
assign pref_ackcnt3_din[3:0] = lsu_cpx_pref_ack[3] ? pref_ackcnt_decr[3:0] : pref_ackcnt_incr[3:0] ;
wire [3:0] pref_ackcnt_en ;
// if both occur in the same cycle then they cancel out.
assign pref_ackcnt_en[0] = lsu_pcx_pref_issue[0] ^ lsu_cpx_pref_ack[0] ;
assign pref_ackcnt_en[1] = lsu_pcx_pref_issue[1] ^ lsu_cpx_pref_ack[1] ;
assign pref_ackcnt_en[2] = lsu_pcx_pref_issue[2] ^ lsu_cpx_pref_ack[2] ;
assign pref_ackcnt_en[3] = lsu_pcx_pref_issue[3] ^ lsu_cpx_pref_ack[3] ;
// Thread0
dffre_s #(4) pref_ackcnt0_ff (
.din (pref_ackcnt0_din[3:0]),
.q (pref_ackcnt0[3:0]),
.rst (reset), .en (pref_ackcnt_en[0]),
.clk (clk),
.se (se), .si (), .so ()
);
// Thread1
dffre_s #(4) pref_ackcnt1_ff (
.din (pref_ackcnt1_din[3:0]),
.q (pref_ackcnt1[3:0]),
.rst (reset), .en (pref_ackcnt_en[1]),
.clk (clk),
.se (se), .si (), .so ()
);
// Thread2
dffre_s #(4) pref_ackcnt2_ff (
.din (pref_ackcnt2_din[3:0]),
.q (pref_ackcnt2[3:0]),
.rst (reset), .en (pref_ackcnt_en[2]),
.clk (clk),
.se (se), .si (), .so ()
);
// Thread3
dffre_s #(4) pref_ackcnt3_ff (
.din (pref_ackcnt3_din[3:0]),
.q (pref_ackcnt3[3:0]),
.rst (reset), .en (pref_ackcnt_en[3]),
.clk (clk),
.se (se), .si (), .so ()
);
assign no_spc_pref[0] = pref_ackcnt0[3] ;
assign no_spc_pref[1] = pref_ackcnt1[3] ;
assign no_spc_pref[2] = pref_ackcnt2[3] ;
assign no_spc_pref[3] = pref_ackcnt3[3] ;
assign lsu_no_spc_pref[3:0] = no_spc_pref[3:0];
//====================================================================
wire lsu_bist_e;
assign lsu_bist_e = lsu_bist_wvld_e | lsu_bist_rvld_e;
wire [10:0] lmq_pcx_pkt_addr_din;
wire [3:0] dfq_byp_thrd_sel;
mux4ds #(11) lmq_pcx_pkt_addr_mux (
.in0 ({lmq0_pcx_pkt_addr[10:0]}),
.in1 ({lmq1_pcx_pkt_addr[10:0]}),
.in2 ({lmq2_pcx_pkt_addr[10:0]}),
.in3 ({lmq3_pcx_pkt_addr[10:0]}),
.sel0(dfq_byp_thrd_sel[0]),
.sel1(dfq_byp_thrd_sel[1]),
.sel2(dfq_byp_thrd_sel[2]),
.sel3(dfq_byp_thrd_sel[3]),
.dout({lmq_pcx_pkt_addr_din[10:0]})
);
dffe_s #(11) lmq_pcx_pkt_addr_ff (
.din ({lmq_pcx_pkt_addr_din[10:0]}),
.q ({lmq_pcx_pkt_addr[10:0]}),
.en (dfq_byp_ff_en),
.clk (clk),
.se (se), .si (), .so ()
);
wire [10:4] lmq_pcx_pkt_addr_minbf;
bw_u1_minbuf_5x UZfix_lmq_pcx_pkt_addr_minbf_b10 (.a(lmq_pcx_pkt_addr[10]), .z(lmq_pcx_pkt_addr_minbf[10]));
bw_u1_minbuf_5x UZfix_lmq_pcx_pkt_addr_minbf_b9 (.a(lmq_pcx_pkt_addr[9]), .z(lmq_pcx_pkt_addr_minbf[9]));
bw_u1_minbuf_5x UZfix_lmq_pcx_pkt_addr_minbf_b8 (.a(lmq_pcx_pkt_addr[8]), .z(lmq_pcx_pkt_addr_minbf[8]));
bw_u1_minbuf_5x UZfix_lmq_pcx_pkt_addr_minbf_b7 (.a(lmq_pcx_pkt_addr[7]), .z(lmq_pcx_pkt_addr_minbf[7]));
bw_u1_minbuf_5x UZfix_lmq_pcx_pkt_addr_minbf_b6 (.a(lmq_pcx_pkt_addr[6]), .z(lmq_pcx_pkt_addr_minbf[6]));
bw_u1_minbuf_5x UZfix_lmq_pcx_pkt_addr_minbf_b5 (.a(lmq_pcx_pkt_addr[5]), .z(lmq_pcx_pkt_addr_minbf[5]));
bw_u1_minbuf_5x UZfix_lmq_pcx_pkt_addr_minbf_b4 (.a(lmq_pcx_pkt_addr[4]), .z(lmq_pcx_pkt_addr_minbf[4]));
assign lmq_ld_addr_b3 = lmq_pcx_pkt_addr[3];
assign dcache_fill_addr_e[10:0] =
{11{lsu_dc_iob_access_e}} & {dcache_iob_addr_e[7:0],3'b000} |
{11{lsu_bist_wvld_e | lsu_bist_rvld_e}} & {mbist_dcache_index[6:0], mbist_dcache_word, 3'b000} |
{11{lsu_diagnstc_wr_src_sel_e}} & lsu_diagnstc_wr_addr_e[10:0] |
{11{lsu_dfq_st_vld}} & st_dcfill_addr[10:0] |
{11{lsu_dfq_ld_vld}} & {lmq_pcx_pkt_addr_minbf[10:4], lmq_pcx_pkt_addr[3:0]};
assign lsu_dcache_fill_addr_e[10:3] = dcache_fill_addr_e[10:3];
wire [10:4] dcache_fill_addr_e_tmp;
assign dcache_fill_addr_e_tmp[10:4] = dcache_fill_addr_e[10:4];
bw_u1_buf_30x UZfix_lsu_dcache_fill_addr_e_err_b10 ( .a(dcache_fill_addr_e_tmp[10]), .z(lsu_dcache_fill_addr_e_err[10]));
bw_u1_buf_30x UZfix_lsu_dcache_fill_addr_e_err_b9 ( .a(dcache_fill_addr_e_tmp[9]), .z(lsu_dcache_fill_addr_e_err[9] ));
bw_u1_buf_30x UZfix_lsu_dcache_fill_addr_e_err_b8 ( .a(dcache_fill_addr_e_tmp[8]), .z(lsu_dcache_fill_addr_e_err[8]));
bw_u1_buf_30x UZfix_lsu_dcache_fill_addr_e_err_b7 ( .a(dcache_fill_addr_e_tmp[7]), .z(lsu_dcache_fill_addr_e_err[7]));
bw_u1_buf_30x UZfix_lsu_dcache_fill_addr_e_err_b6 ( .a(dcache_fill_addr_e_tmp[6]), .z(lsu_dcache_fill_addr_e_err[6]));
bw_u1_buf_30x UZfix_lsu_dcache_fill_addr_e_err_b5 ( .a(dcache_fill_addr_e_tmp[5]), .z(lsu_dcache_fill_addr_e_err[5]));
bw_u1_buf_30x UZfix_lsu_dcache_fill_addr_e_err_b4 ( .a(dcache_fill_addr_e_tmp[4]), .z(lsu_dcache_fill_addr_e_err[4]));
// used as ld bypass
assign dcache_wr_addr_e[2:0] = dcache_fill_addr_e[2:0];
//ldfill doesn't need to create wrt byte msk, always fill one line
assign waddr_enc[3:0] =
{4{lsu_dc_iob_access_e}} & {dcache_iob_addr_e[0],3'b000} |
{4{lsu_bist_e}} & {mbist_dcache_word, 3'b000} |
{4{lsu_diagnstc_wr_src_sel_e}} & lsu_diagnstc_wr_addr_e[3:0] |
{4{lsu_dfq_st_vld}} & st_dcfill_addr[3:0] ;
//==============================================================
/*
dff_s #(4) lsu_thread_stgg (
.din ({thread3_m, thread2_m, thread1_m,thread0_m}),
.q (lsu_thread_g[3:0]),
.clk (clk),
.se (se), .si (), .so ()
);
*/
assign lsu_thread_g[3] = thread3_g;
assign lsu_thread_g[2] = thread2_g;
assign lsu_thread_g[1] = thread1_g;
assign lsu_thread_g[0] = thread0_g;
//===============================================================
//LMQ thread sel
//===============================================================
//lmq_ldd_vld
assign dfq_byp_thrd_sel[0] = ~lsu_dfq_byp_tid[1] & ~lsu_dfq_byp_tid[0];
assign dfq_byp_thrd_sel[1] = ~lsu_dfq_byp_tid[1] & lsu_dfq_byp_tid[0];
assign dfq_byp_thrd_sel[2] = lsu_dfq_byp_tid[1] & ~lsu_dfq_byp_tid[0];
assign dfq_byp_thrd_sel[3] = lsu_dfq_byp_tid[1] & lsu_dfq_byp_tid[0];
wire lmq_ldd_vld_din;
mux4ds #(1) lmq_ldd_vld_mux (
.in0 ({lmq0_ldd_vld}),
.in1 ({lmq1_ldd_vld}),
.in2 ({lmq2_ldd_vld}),
.in3 ({lmq3_ldd_vld}),
.sel0(dfq_byp_thrd_sel[0]),
.sel1(dfq_byp_thrd_sel[1]),
.sel2(dfq_byp_thrd_sel[2]),
.sel3(dfq_byp_thrd_sel[3]),
.dout({lmq_ldd_vld_din})
);
dffe_s #(1) lmq_ldd_vld_ff (
.din ({lmq_ldd_vld_din}),
.q ({lmq_ldd_vld}),
.en (dfq_byp_ff_en),
.clk (clk),
.se (se), .si (), .so ()
);
//bist
wire [1:0] bist_way_enc_e;
wire [3:0] bist_way_e;
assign bist_way_enc_e[1:0] = lsu_dc_iob_access_e ?
lsu_dcache_iob_way_e[1:0] : mbist_dcache_way[1:0] ;
assign bist_way_e[0] = ~bist_way_enc_e[1] & ~bist_way_enc_e[0] ;
assign bist_way_e[1] = ~bist_way_enc_e[1] & bist_way_enc_e[0] ;
assign bist_way_e[2] = bist_way_enc_e[1] & ~bist_way_enc_e[0] ;
assign bist_way_e[3] = bist_way_enc_e[1] & bist_way_enc_e[0] ;
assign lsu_bist_rsel_way_e[3:0] = bist_way_e[3:0];
wire lmq_l2fill_fp_din;
assign lmq_l2fill_fp_din =
dfq_byp_thrd_sel[0] & lmq0_l2fill_fpld |
dfq_byp_thrd_sel[1] & lmq1_l2fill_fpld |
dfq_byp_thrd_sel[2] & lmq2_l2fill_fpld |
dfq_byp_thrd_sel[3] & lmq3_l2fill_fpld ;
dffe_s #(1) lmq_l2fill_fp_ff (
.din (lmq_l2fill_fp_din),
.q (lsu_l2fill_fpld_e),
.en (dfq_byp_ff_en),
.clk (clk),
.se (se), .si (), .so ()
);
wire lmq_ncache_ld_din;
assign lmq_ncache_ld_din =
dfq_byp_thrd_sel[0] & lmq0_ncache_ld |
dfq_byp_thrd_sel[1] & lmq1_ncache_ld |
dfq_byp_thrd_sel[2] & lmq2_ncache_ld |
dfq_byp_thrd_sel[3] & lmq3_ncache_ld ;
dffe_s #(1) lmq_ncache_ld_ff (
.din (lmq_ncache_ld_din),
.q (lsu_ncache_ld_e),
.en (dfq_byp_ff_en),
.clk (clk),
.se (se), .si (), .so ()
);
//lmq
wire [1:0] lmq_ldfill_way_din;
mux4ds #(2) lmq_ldfill_way_mux (
.in0 ({lmq0_pcx_pkt_way[1:0]}),
.in1 ({lmq1_pcx_pkt_way[1:0]}),
.in2 ({lmq2_pcx_pkt_way[1:0]}),
.in3 ({lmq3_pcx_pkt_way[1:0]}),
.sel0(dfq_byp_thrd_sel[0]),
.sel1(dfq_byp_thrd_sel[1]),
.sel2(dfq_byp_thrd_sel[2]),
.sel3(dfq_byp_thrd_sel[3]),
.dout({lmq_ldfill_way_din[1:0]})
);
wire [1:0] lmq_ldfill_way;
dffe_s #(2) lmq_ldfill_way_ff (
.din ({lmq_ldfill_way_din[1:0]}),
.q ({lmq_ldfill_way[1:0]}),
.en (dfq_byp_ff_en),
.clk (clk),
.se (se), .si (), .so ()
);
wire [1:0] dcache_fill_way_enc_e;
assign dcache_fill_way_enc_e[1:0] =
{2{lsu_dc_iob_access_e}} & lsu_dcache_iob_way_e[1:0] |
{2{lsu_bist_e}} & bist_way_enc_e[1:0] |
{2{lsu_diagnstc_wr_src_sel_e}} & lsu_diagnstc_wr_way_e[1:0]|
{2{lsu_dfq_st_vld}} & lsu_st_way_e[1:0] |
{2{lsu_dfq_ld_vld}} & lmq_ldfill_way[1:0];
assign lsu_dcache_fill_way_e[0] = ~dcache_fill_way_enc_e[1] & ~dcache_fill_way_enc_e[0];
assign lsu_dcache_fill_way_e[1] = ~dcache_fill_way_enc_e[1] & dcache_fill_way_enc_e[0];
assign lsu_dcache_fill_way_e[2] = dcache_fill_way_enc_e[1] & ~dcache_fill_way_enc_e[0];
assign lsu_dcache_fill_way_e[3] = dcache_fill_way_enc_e[1] & dcache_fill_way_enc_e[0];
//ld_rq_type
wire [2:0] lmq_ld_rq_type_din;
mux4ds #(3) lmq_ld_rq_type_mux (
.in0 ({lmq0_ld_rq_type[2:0]}),
.in1 ({lmq1_ld_rq_type[2:0]}),
.in2 ({lmq2_ld_rq_type[2:0]}),
.in3 ({lmq3_ld_rq_type[2:0]}),
.sel0(dfq_byp_thrd_sel[0]),
.sel1(dfq_byp_thrd_sel[1]),
.sel2(dfq_byp_thrd_sel[2]),
.sel3(dfq_byp_thrd_sel[3]),
.dout({lmq_ld_rq_type_din[2:0]})
);
dffe_s #(3) lmq_ld_rq_type_e_ff (
.din ({lmq_ld_rq_type_din[2:0]}),
.q ({lmq_ld_rq_type_e[2:0]}),
.en (dfq_byp_ff_en),
.clk (clk),
.se (se), .si (), .so ()
);
//================================================================
wire other_flush_pipe_w ;
assign other_flush_pipe_w = tlu_early_flush_pipe2_w | (lsu_ttype_vld_m2 & lsu_inst_vld_w);
assign dctl_flush_pipe_w = other_flush_pipe_w | ifu_lsu_flush_w ;
// Staged ifu_tlu_flush_m should be used !!
assign dctl_early_flush_w = (lsu_local_early_flush_g | tlu_early_flush_pipe2_w | ifu_lsu_flush_w) ;
//================================================================
// dcfill size
wire dcfill_size_mx_sel_e;
//bug6216/eco6624
assign dcfill_size_mx_sel_e = lsu_dc_iob_access_e | lsu_diagnstc_wr_src_sel_e;
mux2ds #(2) dcache_wr_size_e_mux (
.in0(2'b11),
.in1(lsu_st_dcfill_size_e[1:0]),
.sel0(dcfill_size_mx_sel_e),
.sel1(~dcfill_size_mx_sel_e),
.dout(dcache_wr_size_e[1:0])
);
//assign lsu_dcfill_data_mx_sel_e = (dcache_iob_wr_e | dcache_iob_rd_e | lsu_bist_wvld_e);
wire dcfill_data_mx_sel_e_l;
bw_u1_nor3_8x UZsize_dcfill_data_mx_sel_e_l (.a (dcache_iob_wr_e),
.b (dcache_iob_rd_e),
.c (lsu_bist_wvld_e),
.z (dcfill_data_mx_sel_e_l));
bw_u1_inv_30x UZsize_dcfill_data_mx_sel_e ( .a(dcfill_data_mx_sel_e_l), .z (lsu_dcfill_data_mx_sel_e));
//================================================================
wire [3:0] dfq_thread_e;
assign dfq_thread_e[0] = ~lsu_dfill_tid_e[1] & ~lsu_dfill_tid_e[0];
assign dfq_thread_e[1] = ~lsu_dfill_tid_e[1] & lsu_dfill_tid_e[0];
assign dfq_thread_e[2] = lsu_dfill_tid_e[1] & ~lsu_dfill_tid_e[0];
assign dfq_thread_e[3] = lsu_dfill_tid_e[1] & lsu_dfill_tid_e[0];
wire [3:0] dfq_byp_sel_e;
assign dfq_byp_sel_e[0] = dfq_thread_e[0] & dcfill_active_e & ~lsu_cpx_pkt_prefetch2;
assign dfq_byp_sel_e[1] = dfq_thread_e[1] & dcfill_active_e & ~lsu_cpx_pkt_prefetch2;
assign dfq_byp_sel_e[2] = dfq_thread_e[2] & dcfill_active_e & ~lsu_cpx_pkt_prefetch2;
assign dfq_byp_sel_e[3] = dfq_thread_e[3] & dcfill_active_e & ~lsu_cpx_pkt_prefetch2;
wire [3:0] lmq_byp_misc_sel_e ;
assign lmq_byp_misc_sel_e[0] = ld_thrd_byp_sel_e[0] | // select for ldxa/raw.
dfq_byp_sel_e[0] ; // select for dfq.
assign lmq_byp_misc_sel_e[1] = ld_thrd_byp_sel_e[1] | // select for ldxa/raw.
dfq_byp_sel_e[1] ; // select for dfq.
assign lmq_byp_misc_sel_e[2] = ld_thrd_byp_sel_e[2] | // select for ldxa/raw.
dfq_byp_sel_e[2] ; // select for dfq.
assign lmq_byp_misc_sel_e[3] = ld_thrd_byp_sel_e[3] |
dfq_byp_sel_e[3] ;
wire [2:0] byp_misc_addr_e;
assign byp_misc_addr_e[2:0] = (lmq_byp_misc_sel_e[0] ? lmq0_pcx_pkt_addr[2:0] : 3'b0) |
(lmq_byp_misc_sel_e[1] ? lmq1_pcx_pkt_addr[2:0] : 3'b0) |
(lmq_byp_misc_sel_e[2] ? lmq2_pcx_pkt_addr[2:0] : 3'b0) |
(lmq_byp_misc_sel_e[3] ? lmq3_pcx_pkt_addr[2:0] : 3'b0) ;
wire [1:0] byp_misc_sz_e;
assign byp_misc_sz_e[1:0] = (lmq_byp_misc_sel_e[0] ? lmq0_byp_misc_sz[1:0] : 2'b0) |
(lmq_byp_misc_sel_e[1] ? lmq1_byp_misc_sz[1:0] : 2'b0) |
(lmq_byp_misc_sel_e[2] ? lmq2_byp_misc_sz[1:0] : 2'b0) |
(lmq_byp_misc_sel_e[3] ? lmq3_byp_misc_sz[1:0] : 2'b0) ;
dff_s #(5) lmq_byp_misc_stgm (
.din ({byp_misc_addr_e[2:0], byp_misc_sz_e[1:0]}),
.q ({lsu_byp_misc_addr_m[2:0], lsu_byp_misc_sz_m[1:0]}),
.clk (clk),
.se (se), .si (), .so ()
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__CLKDLYINV3SD3_FUNCTIONAL_V
`define SKY130_FD_SC_LS__CLKDLYINV3SD3_FUNCTIONAL_V
/**
* clkdlyinv3sd3: Clock Delay Inverter 3-stage 0.50um length inner
* stage gate.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__clkdlyinv3sd3 (
Y,
A
);
// Module ports
output Y;
input A;
// Local signals
wire not0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y, A );
buf buf0 (Y , not0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__CLKDLYINV3SD3_FUNCTIONAL_V
|
//////////////////////////////////////////////////////////////////////
//// ////
//// usbHost.v ////
//// ////
//// This file is part of the usbhostslave opencores effort.
//// <http://www.opencores.org/cores//> ////
//// ////
//// Module Description: ////
//// Top level module
//// ////
//// To Do: ////
////
//// ////
//// Author(s): ////
//// - Steve Fielding, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from <http://www.opencores.org/lgpl.shtml> ////
//// ////
//////////////////////////////////////////////////////////////////////
//
`include "timescale.v"
module usbHost(
clk_i,
rst_i,
address_i,
data_i,
data_o,
we_i,
strobe_i,
ack_o,
usbClk,
hostSOFSentIntOut,
hostConnEventIntOut,
hostResumeIntOut,
hostTransDoneIntOut,
USBWireDataIn,
USBWireDataInTick,
USBWireDataOut,
USBWireDataOutTick,
USBWireCtrlOut,
USBFullSpeed
);
parameter HOST_FIFO_DEPTH = 64; //HOST_FIFO_DEPTH = 2^HOST_ADDR_WIDTH
parameter HOST_FIFO_ADDR_WIDTH = 6;
input clk_i; //Wishbone bus clock. Maximum 5*usbClk=240MHz
input rst_i; //Wishbone bus sync reset. Synchronous to 'clk_i'. Resets all logic
input [7:0] address_i; //Wishbone bus address in
input [7:0] data_i; //Wishbone bus data in
output [7:0] data_o; //Wishbone bus data out
input we_i; //Wishbone bus write enable in
input strobe_i; //Wishbone bus strobe in
output ack_o; //Wishbone bus acknowledge out
input usbClk; //usb clock. 48Mhz +/-0.25%
output hostSOFSentIntOut;
output hostConnEventIntOut;
output hostResumeIntOut;
output hostTransDoneIntOut;
input [1:0] USBWireDataIn;
output [1:0] USBWireDataOut;
output USBWireDataOutTick;
output USBWireDataInTick;
output USBWireCtrlOut;
output USBFullSpeed;
wire clk_i;
wire rst_i;
wire [7:0] address_i;
wire [7:0] data_i;
wire [7:0] data_o;
wire we_i;
wire strobe_i;
wire ack_o;
wire usbClk;
wire hostSOFSentIntOut;
wire hostConnEventIntOut;
wire hostResumeIntOut;
wire hostTransDoneIntOut;
wire [1:0] USBWireDataIn;
wire [1:0] USBWireDataOut;
wire USBWireDataOutTick;
wire USBWireDataInTick;
wire USBWireCtrlOut;
wire USBFullSpeed;
//internal wiring
wire hostControlSel;
wire slaveControlSel;
wire hostRxFifoSel;
wire hostTxFifoSel;
wire hostSlaveMuxSel;
wire [7:0] dataFromHostControl;
wire [7:0] dataFromSlaveControl;
wire [7:0] dataFromHostRxFifo;
wire [7:0] dataFromHostTxFifo;
wire [7:0] dataFromHostSlaveMux;
wire hostTxFifoRE;
wire [7:0] hostTxFifoData;
wire hostTxFifoEmpty;
wire hostRxFifoWE;
wire [7:0] hostRxFifoData;
wire hostRxFifoFull;
wire [7:0] RxCtrlOut;
wire [7:0] RxDataFromSIE;
wire RxDataOutWEn;
wire fullSpeedBitRateFromHost;
wire fullSpeedPolarityFromHost;
wire SIEPortWEnFromHost;
wire SIEPortTxRdy;
wire [7:0] SIEPortDataInFromHost;
wire [7:0] SIEPortCtrlInFromHost;
wire [1:0] connectState;
wire resumeDetected;
wire [7:0] SIEPortDataInToSIE;
wire SIEPortWEnToSIE;
wire [7:0] SIEPortCtrlInToSIE;
wire fullSpeedPolarityToSIE;
wire fullSpeedBitRateToSIE;
wire noActivityTimeOut;
wire rstSyncToBusClk;
wire rstSyncToUsbClk;
wire noActivityTimeOutEnableToSIE;
wire noActivityTimeOutEnableFromHost;
// This is not a bug.
// USBFullSpeed controls the PHY edge speed.
// The only time that the PHY needs to operate with low speed edge rate is
// when the host is directly connected to a low speed device. And when this is true, fullSpeedPolarity
// will be low. When the host is connected to a low speed device via a hub, then speed can be full or low
// but according to spec edge speed must be full rate edge speed.
assign USBFullSpeed = fullSpeedPolarityToSIE;
//assign USBFullSpeed = fullSpeedBitRateToSIE;
usbHostControl u_usbHostControl(
.busClk(clk_i),
.rstSyncToBusClk(rstSyncToBusClk),
.usbClk(usbClk),
.rstSyncToUsbClk(rstSyncToUsbClk),
.TxFifoRE(hostTxFifoRE),
.TxFifoData(hostTxFifoData),
.TxFifoEmpty(hostTxFifoEmpty),
.RxFifoWE(hostRxFifoWE),
.RxFifoData(hostRxFifoData),
.RxFifoFull(hostRxFifoFull),
.RxByteStatus(RxCtrlOut),
.RxData(RxDataFromSIE),
.RxDataValid(RxDataOutWEn),
.SIERxTimeOut(noActivityTimeOut),
.SIERxTimeOutEn(noActivityTimeOutEnableFromHost),
.fullSpeedRate(fullSpeedBitRateFromHost),
.fullSpeedPol(fullSpeedPolarityFromHost),
.HCTxPortEn(SIEPortWEnFromHost),
.HCTxPortRdy(SIEPortTxRdy),
.HCTxPortData(SIEPortDataInFromHost),
.HCTxPortCtrl(SIEPortCtrlInFromHost),
.connectStateIn(connectState),
.resumeDetectedIn(resumeDetected),
.busAddress(address_i[3:0]),
.busDataIn(data_i),
.busDataOut(dataFromHostControl),
.busWriteEn(we_i),
.busStrobe_i(strobe_i),
.SOFSentIntOut(hostSOFSentIntOut),
.connEventIntOut(hostConnEventIntOut),
.resumeIntOut(hostResumeIntOut),
.transDoneIntOut(hostTransDoneIntOut),
.hostControlSelect(hostControlSel) );
wishBoneBI u_wishBoneBI (
.address(address_i),
.dataIn(data_i),
.dataOut(data_o),
.writeEn(we_i),
.strobe_i(strobe_i),
.ack_o(ack_o),
.clk(clk_i),
.rst(rstSyncToBusClk),
.hostControlSel(hostControlSel),
.hostRxFifoSel(hostRxFifoSel),
.hostTxFifoSel(hostTxFifoSel),
.slaveControlSel(),
.slaveEP0RxFifoSel(),
.slaveEP1RxFifoSel(),
.slaveEP2RxFifoSel(),
.slaveEP3RxFifoSel(),
.slaveEP0TxFifoSel(),
.slaveEP1TxFifoSel(),
.slaveEP2TxFifoSel(),
.slaveEP3TxFifoSel(),
.hostSlaveMuxSel(hostSlaveMuxSel),
.dataFromHostControl(dataFromHostControl),
.dataFromHostRxFifo(dataFromHostRxFifo),
.dataFromHostTxFifo(dataFromHostTxFifo),
.dataFromSlaveControl(8'h00),
.dataFromEP0RxFifo(8'h00),
.dataFromEP1RxFifo(8'h00),
.dataFromEP2RxFifo(8'h00),
.dataFromEP3RxFifo(8'h00),
.dataFromEP0TxFifo(8'h00),
.dataFromEP1TxFifo(8'h00),
.dataFromEP2TxFifo(8'h00),
.dataFromEP3TxFifo(8'h00),
.dataFromHostSlaveMux(dataFromHostSlaveMux)
);
assign SIEPortCtrlInToSIE = SIEPortCtrlInFromHost;
assign SIEPortDataInToSIE = SIEPortDataInFromHost;
assign SIEPortWEnToSIE = SIEPortWEnFromHost;
assign fullSpeedPolarityToSIE = fullSpeedPolarityFromHost;
assign fullSpeedBitRateToSIE = fullSpeedBitRateFromHost;
assign noActivityTimeOutEnableToSIE = noActivityTimeOutEnableFromHost;
hostSlaveMuxBI u_hostSlaveMuxBI (
.dataIn(data_i),
.dataOut(dataFromHostSlaveMux),
.address(address_i[0]),
.writeEn(we_i),
.strobe_i(strobe_i),
.usbClk(usbClk),
.busClk(clk_i),
.hostMode(hostMode),
.hostSlaveMuxSel(hostSlaveMuxSel),
.rstFromWire(rst_i),
.rstSyncToBusClkOut(rstSyncToBusClk),
.rstSyncToUsbClkOut(rstSyncToUsbClk)
);
usbSerialInterfaceEngine u_usbSerialInterfaceEngine(
.clk(usbClk),
.rst(rstSyncToUsbClk),
.USBWireDataIn(USBWireDataIn),
.USBWireDataOut(USBWireDataOut),
.USBWireDataInTick(USBWireDataInTick),
.USBWireDataOutTick(USBWireDataOutTick),
.USBWireCtrlOut(USBWireCtrlOut),
.connectState(connectState),
.resumeDetected(resumeDetected),
.RxCtrlOut(RxCtrlOut),
.RxDataOutWEn(RxDataOutWEn),
.RxDataOut(RxDataFromSIE),
.SIEPortCtrlIn(SIEPortCtrlInToSIE),
.SIEPortDataIn(SIEPortDataInToSIE),
.SIEPortTxRdy(SIEPortTxRdy),
.SIEPortWEn(SIEPortWEnToSIE),
.fullSpeedPolarity(fullSpeedPolarityToSIE),
.fullSpeedBitRate(fullSpeedBitRateToSIE),
.noActivityTimeOut(noActivityTimeOut),
.noActivityTimeOutEnable(noActivityTimeOutEnableToSIE)
);
//---Host fifos
TxFifo #(HOST_FIFO_DEPTH, HOST_FIFO_ADDR_WIDTH) HostTxFifo (
.usbClk(usbClk),
.busClk(clk_i),
.rstSyncToBusClk(rstSyncToBusClk),
.rstSyncToUsbClk(rstSyncToUsbClk),
.fifoREn(hostTxFifoRE),
.fifoEmpty(hostTxFifoEmpty),
.busAddress(address_i[2:0]),
.busWriteEn(we_i),
.busStrobe_i(strobe_i),
.busFifoSelect(hostTxFifoSel),
.busDataIn(data_i),
.busDataOut(dataFromHostTxFifo),
.fifoDataOut(hostTxFifoData) );
RxFifo #(HOST_FIFO_DEPTH, HOST_FIFO_ADDR_WIDTH) HostRxFifo(
.usbClk(usbClk),
.busClk(clk_i),
.rstSyncToBusClk(rstSyncToBusClk),
.rstSyncToUsbClk(rstSyncToUsbClk),
.fifoWEn(hostRxFifoWE),
.fifoFull(hostRxFifoFull),
.busAddress(address_i[2:0]),
.busWriteEn(we_i),
.busStrobe_i(strobe_i),
.busFifoSelect(hostRxFifoSel),
.busDataIn(data_i),
.busDataOut(dataFromHostRxFifo),
.fifoDataIn(hostRxFifoData) );
endmodule
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2013 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file controller_command_fifo.v when simulating
// the core, controller_command_fifo. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module controller_command_fifo(
clk,
rst,
din,
wr_en,
rd_en,
dout,
full,
empty,
data_count
);
input clk;
input rst;
input [127 : 0] din;
input wr_en;
input rd_en;
output [127 : 0] dout;
output full;
output empty;
output [4 : 0] data_count;
// synthesis translate_off
FIFO_GENERATOR_V8_4 #(
.C_ADD_NGC_CONSTRAINT(0),
.C_APPLICATION_TYPE_AXIS(0),
.C_APPLICATION_TYPE_RACH(0),
.C_APPLICATION_TYPE_RDCH(0),
.C_APPLICATION_TYPE_WACH(0),
.C_APPLICATION_TYPE_WDCH(0),
.C_APPLICATION_TYPE_WRCH(0),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_AXI_DATA_WIDTH(64),
.C_AXI_ID_WIDTH(4),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_TYPE(0),
.C_AXI_WUSER_WIDTH(1),
.C_AXIS_TDATA_WIDTH(64),
.C_AXIS_TDEST_WIDTH(4),
.C_AXIS_TID_WIDTH(8),
.C_AXIS_TKEEP_WIDTH(4),
.C_AXIS_TSTRB_WIDTH(4),
.C_AXIS_TUSER_WIDTH(4),
.C_AXIS_TYPE(0),
.C_COMMON_CLOCK(1),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(5),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH(128),
.C_DIN_WIDTH_AXIS(1),
.C_DIN_WIDTH_RACH(32),
.C_DIN_WIDTH_RDCH(64),
.C_DIN_WIDTH_WACH(32),
.C_DIN_WIDTH_WDCH(64),
.C_DIN_WIDTH_WRCH(2),
.C_DOUT_RST_VAL("0"),
.C_DOUT_WIDTH(128),
.C_ENABLE_RLOCS(0),
.C_ENABLE_RST_SYNC(1),
.C_ERROR_INJECTION_TYPE(0),
.C_ERROR_INJECTION_TYPE_AXIS(0),
.C_ERROR_INJECTION_TYPE_RACH(0),
.C_ERROR_INJECTION_TYPE_RDCH(0),
.C_ERROR_INJECTION_TYPE_WACH(0),
.C_ERROR_INJECTION_TYPE_WDCH(0),
.C_ERROR_INJECTION_TYPE_WRCH(0),
.C_FAMILY("virtex6"),
.C_FULL_FLAGS_RST_VAL(1),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(0),
.C_HAS_AXI_ARUSER(0),
.C_HAS_AXI_AWUSER(0),
.C_HAS_AXI_BUSER(0),
.C_HAS_AXI_RD_CHANNEL(0),
.C_HAS_AXI_RUSER(0),
.C_HAS_AXI_WR_CHANNEL(0),
.C_HAS_AXI_WUSER(0),
.C_HAS_AXIS_TDATA(0),
.C_HAS_AXIS_TDEST(0),
.C_HAS_AXIS_TID(0),
.C_HAS_AXIS_TKEEP(0),
.C_HAS_AXIS_TLAST(0),
.C_HAS_AXIS_TREADY(1),
.C_HAS_AXIS_TSTRB(0),
.C_HAS_AXIS_TUSER(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(1),
.C_HAS_DATA_COUNTS_AXIS(0),
.C_HAS_DATA_COUNTS_RACH(0),
.C_HAS_DATA_COUNTS_RDCH(0),
.C_HAS_DATA_COUNTS_WACH(0),
.C_HAS_DATA_COUNTS_WDCH(0),
.C_HAS_DATA_COUNTS_WRCH(0),
.C_HAS_INT_CLK(0),
.C_HAS_MASTER_CE(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_PROG_FLAGS_AXIS(0),
.C_HAS_PROG_FLAGS_RACH(0),
.C_HAS_PROG_FLAGS_RDCH(0),
.C_HAS_PROG_FLAGS_WACH(0),
.C_HAS_PROG_FLAGS_WDCH(0),
.C_HAS_PROG_FLAGS_WRCH(0),
.C_HAS_RD_DATA_COUNT(0),
.C_HAS_RD_RST(0),
.C_HAS_RST(1),
.C_HAS_SLAVE_CE(0),
.C_HAS_SRST(0),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(0),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(0),
.C_IMPLEMENTATION_TYPE_AXIS(1),
.C_IMPLEMENTATION_TYPE_RACH(1),
.C_IMPLEMENTATION_TYPE_RDCH(1),
.C_IMPLEMENTATION_TYPE_WACH(1),
.C_IMPLEMENTATION_TYPE_WDCH(1),
.C_IMPLEMENTATION_TYPE_WRCH(1),
.C_INIT_WR_PNTR_VAL(0),
.C_INTERFACE_TYPE(0),
.C_MEMORY_TYPE(1),
.C_MIF_FILE_NAME("BlankString"),
.C_MSGON_VAL(1),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(0),
.C_PRELOAD_REGS(1),
.C_PRIM_FIFO_TYPE("512x72"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(5),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_EMPTY_TYPE_AXIS(5),
.C_PROG_EMPTY_TYPE_RACH(5),
.C_PROG_EMPTY_TYPE_RDCH(5),
.C_PROG_EMPTY_TYPE_WACH(5),
.C_PROG_EMPTY_TYPE_WDCH(5),
.C_PROG_EMPTY_TYPE_WRCH(5),
.C_PROG_FULL_THRESH_ASSERT_VAL(15),
.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023),
.C_PROG_FULL_THRESH_NEGATE_VAL(14),
.C_PROG_FULL_TYPE(0),
.C_PROG_FULL_TYPE_AXIS(5),
.C_PROG_FULL_TYPE_RACH(5),
.C_PROG_FULL_TYPE_RDCH(5),
.C_PROG_FULL_TYPE_WACH(5),
.C_PROG_FULL_TYPE_WDCH(5),
.C_PROG_FULL_TYPE_WRCH(5),
.C_RACH_TYPE(0),
.C_RD_DATA_COUNT_WIDTH(5),
.C_RD_DEPTH(16),
.C_RD_FREQ(1),
.C_RD_PNTR_WIDTH(4),
.C_RDCH_TYPE(0),
.C_REG_SLICE_MODE_AXIS(0),
.C_REG_SLICE_MODE_RACH(0),
.C_REG_SLICE_MODE_RDCH(0),
.C_REG_SLICE_MODE_WACH(0),
.C_REG_SLICE_MODE_WDCH(0),
.C_REG_SLICE_MODE_WRCH(0),
.C_SYNCHRONIZER_STAGE(2),
.C_UNDERFLOW_LOW(0),
.C_USE_COMMON_OVERFLOW(0),
.C_USE_COMMON_UNDERFLOW(0),
.C_USE_DEFAULT_SETTINGS(0),
.C_USE_DOUT_RST(1),
.C_USE_ECC(0),
.C_USE_ECC_AXIS(0),
.C_USE_ECC_RACH(0),
.C_USE_ECC_RDCH(0),
.C_USE_ECC_WACH(0),
.C_USE_ECC_WDCH(0),
.C_USE_ECC_WRCH(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(1),
.C_VALID_LOW(0),
.C_WACH_TYPE(0),
.C_WDCH_TYPE(0),
.C_WR_ACK_LOW(0),
.C_WR_DATA_COUNT_WIDTH(5),
.C_WR_DEPTH(16),
.C_WR_DEPTH_AXIS(1024),
.C_WR_DEPTH_RACH(16),
.C_WR_DEPTH_RDCH(1024),
.C_WR_DEPTH_WACH(16),
.C_WR_DEPTH_WDCH(1024),
.C_WR_DEPTH_WRCH(16),
.C_WR_FREQ(1),
.C_WR_PNTR_WIDTH(4),
.C_WR_PNTR_WIDTH_AXIS(10),
.C_WR_PNTR_WIDTH_RACH(4),
.C_WR_PNTR_WIDTH_RDCH(10),
.C_WR_PNTR_WIDTH_WACH(4),
.C_WR_PNTR_WIDTH_WDCH(10),
.C_WR_PNTR_WIDTH_WRCH(4),
.C_WR_RESPONSE_LATENCY(1),
.C_WRCH_TYPE(0)
)
inst (
.CLK(clk),
.RST(rst),
.DIN(din),
.WR_EN(wr_en),
.RD_EN(rd_en),
.DOUT(dout),
.FULL(full),
.EMPTY(empty),
.DATA_COUNT(data_count),
.BACKUP(),
.BACKUP_MARKER(),
.SRST(),
.WR_CLK(),
.WR_RST(),
.RD_CLK(),
.RD_RST(),
.PROG_EMPTY_THRESH(),
.PROG_EMPTY_THRESH_ASSERT(),
.PROG_EMPTY_THRESH_NEGATE(),
.PROG_FULL_THRESH(),
.PROG_FULL_THRESH_ASSERT(),
.PROG_FULL_THRESH_NEGATE(),
.INT_CLK(),
.INJECTDBITERR(),
.INJECTSBITERR(),
.ALMOST_FULL(),
.WR_ACK(),
.OVERFLOW(),
.ALMOST_EMPTY(),
.VALID(),
.UNDERFLOW(),
.RD_DATA_COUNT(),
.WR_DATA_COUNT(),
.PROG_FULL(),
.PROG_EMPTY(),
.SBITERR(),
.DBITERR(),
.M_ACLK(),
.S_ACLK(),
.S_ARESETN(),
.M_ACLK_EN(),
.S_ACLK_EN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWLOCK(),
.S_AXI_AWCACHE(),
.S_AXI_AWPROT(),
.S_AXI_AWQOS(),
.S_AXI_AWREGION(),
.S_AXI_AWUSER(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WID(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WUSER(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BUSER(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.M_AXI_AWID(),
.M_AXI_AWADDR(),
.M_AXI_AWLEN(),
.M_AXI_AWSIZE(),
.M_AXI_AWBURST(),
.M_AXI_AWLOCK(),
.M_AXI_AWCACHE(),
.M_AXI_AWPROT(),
.M_AXI_AWQOS(),
.M_AXI_AWREGION(),
.M_AXI_AWUSER(),
.M_AXI_AWVALID(),
.M_AXI_AWREADY(),
.M_AXI_WID(),
.M_AXI_WDATA(),
.M_AXI_WSTRB(),
.M_AXI_WLAST(),
.M_AXI_WUSER(),
.M_AXI_WVALID(),
.M_AXI_WREADY(),
.M_AXI_BID(),
.M_AXI_BRESP(),
.M_AXI_BUSER(),
.M_AXI_BVALID(),
.M_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARLOCK(),
.S_AXI_ARCACHE(),
.S_AXI_ARPROT(),
.S_AXI_ARQOS(),
.S_AXI_ARREGION(),
.S_AXI_ARUSER(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RUSER(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.M_AXI_ARID(),
.M_AXI_ARADDR(),
.M_AXI_ARLEN(),
.M_AXI_ARSIZE(),
.M_AXI_ARBURST(),
.M_AXI_ARLOCK(),
.M_AXI_ARCACHE(),
.M_AXI_ARPROT(),
.M_AXI_ARQOS(),
.M_AXI_ARREGION(),
.M_AXI_ARUSER(),
.M_AXI_ARVALID(),
.M_AXI_ARREADY(),
.M_AXI_RID(),
.M_AXI_RDATA(),
.M_AXI_RRESP(),
.M_AXI_RLAST(),
.M_AXI_RUSER(),
.M_AXI_RVALID(),
.M_AXI_RREADY(),
.S_AXIS_TVALID(),
.S_AXIS_TREADY(),
.S_AXIS_TDATA(),
.S_AXIS_TSTRB(),
.S_AXIS_TKEEP(),
.S_AXIS_TLAST(),
.S_AXIS_TID(),
.S_AXIS_TDEST(),
.S_AXIS_TUSER(),
.M_AXIS_TVALID(),
.M_AXIS_TREADY(),
.M_AXIS_TDATA(),
.M_AXIS_TSTRB(),
.M_AXIS_TKEEP(),
.M_AXIS_TLAST(),
.M_AXIS_TID(),
.M_AXIS_TDEST(),
.M_AXIS_TUSER(),
.AXI_AW_INJECTSBITERR(),
.AXI_AW_INJECTDBITERR(),
.AXI_AW_PROG_FULL_THRESH(),
.AXI_AW_PROG_EMPTY_THRESH(),
.AXI_AW_DATA_COUNT(),
.AXI_AW_WR_DATA_COUNT(),
.AXI_AW_RD_DATA_COUNT(),
.AXI_AW_SBITERR(),
.AXI_AW_DBITERR(),
.AXI_AW_OVERFLOW(),
.AXI_AW_UNDERFLOW(),
.AXI_W_INJECTSBITERR(),
.AXI_W_INJECTDBITERR(),
.AXI_W_PROG_FULL_THRESH(),
.AXI_W_PROG_EMPTY_THRESH(),
.AXI_W_DATA_COUNT(),
.AXI_W_WR_DATA_COUNT(),
.AXI_W_RD_DATA_COUNT(),
.AXI_W_SBITERR(),
.AXI_W_DBITERR(),
.AXI_W_OVERFLOW(),
.AXI_W_UNDERFLOW(),
.AXI_B_INJECTSBITERR(),
.AXI_B_INJECTDBITERR(),
.AXI_B_PROG_FULL_THRESH(),
.AXI_B_PROG_EMPTY_THRESH(),
.AXI_B_DATA_COUNT(),
.AXI_B_WR_DATA_COUNT(),
.AXI_B_RD_DATA_COUNT(),
.AXI_B_SBITERR(),
.AXI_B_DBITERR(),
.AXI_B_OVERFLOW(),
.AXI_B_UNDERFLOW(),
.AXI_AR_INJECTSBITERR(),
.AXI_AR_INJECTDBITERR(),
.AXI_AR_PROG_FULL_THRESH(),
.AXI_AR_PROG_EMPTY_THRESH(),
.AXI_AR_DATA_COUNT(),
.AXI_AR_WR_DATA_COUNT(),
.AXI_AR_RD_DATA_COUNT(),
.AXI_AR_SBITERR(),
.AXI_AR_DBITERR(),
.AXI_AR_OVERFLOW(),
.AXI_AR_UNDERFLOW(),
.AXI_R_INJECTSBITERR(),
.AXI_R_INJECTDBITERR(),
.AXI_R_PROG_FULL_THRESH(),
.AXI_R_PROG_EMPTY_THRESH(),
.AXI_R_DATA_COUNT(),
.AXI_R_WR_DATA_COUNT(),
.AXI_R_RD_DATA_COUNT(),
.AXI_R_SBITERR(),
.AXI_R_DBITERR(),
.AXI_R_OVERFLOW(),
.AXI_R_UNDERFLOW(),
.AXIS_INJECTSBITERR(),
.AXIS_INJECTDBITERR(),
.AXIS_PROG_FULL_THRESH(),
.AXIS_PROG_EMPTY_THRESH(),
.AXIS_DATA_COUNT(),
.AXIS_WR_DATA_COUNT(),
.AXIS_RD_DATA_COUNT(),
.AXIS_SBITERR(),
.AXIS_DBITERR(),
.AXIS_OVERFLOW(),
.AXIS_UNDERFLOW()
);
// synthesis translate_on
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__INV_PP_SYMBOL_V
`define SKY130_FD_SC_LP__INV_PP_SYMBOL_V
/**
* inv: Inverter.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__inv (
//# {{data|Data Signals}}
input A ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__INV_PP_SYMBOL_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 23:45:15 04/19/2015
// Design Name:
// Module Name: exponent_finder
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module exponent_finder(
input clk,
input [63:0] boundary,
input input_enable,
input [8:0] base,
output reg [7:0] exponent,
output reg ready
);
reg [7:0] next_exponent;
reg next_ready;
reg [10:0] temp_product;
reg [10:0] next_temp_product;
initial begin
next_ready = 0;
next_exponent = 0;
next_temp_product = 1;
end
always @(posedge clk) begin
ready <= next_ready;
exponent <= next_exponent;
temp_product <= next_temp_product;
end
always @(*) begin
if (input_enable) begin
if (temp_product < boundary) begin
next_temp_product = temp_product * base;
next_ready = 0;
next_exponent = exponent + 1;
end else begin
next_temp_product = temp_product;
next_ready = 1;
next_exponent = exponent;
end
end else begin
if (ready) begin
next_ready = 1;
next_exponent = exponent;
next_temp_product = 1;
end else begin
next_temp_product = 1;
next_ready = 0;
next_exponent = 0;
end
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFRTP_4_V
`define SKY130_FD_SC_LP__SDFRTP_4_V
/**
* sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
* single output.
*
* Verilog wrapper for sdfrtp with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__sdfrtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__sdfrtp_4 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_lp__sdfrtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__sdfrtp_4 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__sdfrtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.RESET_B(RESET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFRTP_4_V
|
module stage_ex(
input reset ,
input [31:0] instruction_i ,
output [31:0] instruction_o ,
input [ 7:0] operator_i ,
output [ 7:0] operator_o ,
input [ 2:0] category ,
input [31:0] operand_a_i ,
output [31:0] operand_a_o ,
input [31:0] operand_b_i ,
output [31:0] operand_b_o ,
input register_write_enable_i ,
output reg register_write_enable_o ,
input [ 4:0] register_write_address_i ,
output reg [ 4:0] register_write_address_o ,
input [31:0] register_write_data_i ,
output reg [31:0] register_write_data_o ,
output reg register_hi_write_enable ,
output reg [31:0] register_hi_write_data ,
output reg register_lo_write_enable ,
output reg [31:0] register_lo_write_data ,
input mem_register_hi_write_enable,
input [31:0] mem_register_hi_write_data ,
input mem_register_lo_write_enable,
input [31:0] mem_register_lo_write_data ,
input [31:0] wb_register_hi_read_data ,
input wb_register_hi_write_enable ,
input [31:0] wb_register_hi_write_data ,
input [31:0] wb_register_lo_read_data ,
input wb_register_lo_write_enable ,
input [31:0] wb_register_lo_write_data ,
output reg stall_request
);
wire [31:0] operand_a_complement = ~operand_a_i + 1;
wire [31:0] operand_b_complement = ~operand_b_i + 1;
wire [31:0] operand_sum = operand_a_i + (operator_i == `OPERATOR_SLT ||
operator_i == `OPERATOR_SUB ||
operator_i == `OPERATOR_SUBU ?
operand_b_complement :
operand_b_i
);
assign instruction_o = instruction_i;
assign operator_o = operator_i ;
assign operand_a_o = operand_a_i ;
assign operand_b_o = operand_b_i ;
reg [31:0] register_hi;
always @ (*) begin
if (reset == `RESET_ENABLE) begin
register_hi <= 32'b0;
end
else if (mem_register_hi_write_enable == `WRITE_ENABLE) begin
register_hi <= mem_register_hi_write_data;
end
else if (wb_register_hi_write_enable == `WRITE_ENABLE) begin
register_hi <= wb_register_hi_write_data;
end
else begin
register_hi <= wb_register_hi_read_data;
end
end
reg [31:0] register_lo;
always @ (*) begin
if (reset == `RESET_ENABLE) begin
register_lo <= 32'b0;
end
else if (mem_register_lo_write_enable == `WRITE_ENABLE) begin
register_lo <= mem_register_lo_write_data;
end
else if (wb_register_lo_write_enable == `WRITE_ENABLE) begin
register_lo <= wb_register_lo_write_data;
end
else begin
register_lo <= wb_register_lo_read_data;
end
end
reg [31:0] result_logic;
always @ (*) begin
if (reset == `RESET_ENABLE) begin
result_logic <= 32'b0;
end
else begin
case (operator_i)
`OPERATOR_AND : begin
result_logic <= operand_a_i & operand_b_i;
end
`OPERATOR_OR : begin
result_logic <= operand_a_i | operand_b_i;
end
`OPERATOR_XOR : begin
result_logic <= operand_a_i ^ operand_b_i;
end
`OPERATOR_NOR : begin
result_logic <= ~(operand_a_i | operand_b_i);
end
default : begin
result_logic <= 32'b0;
end
endcase
end
end
reg [31:0] result_shift;
always @ (*) begin
if (reset == `RESET_ENABLE) begin
result_shift <= 32'b0;
end
else begin
case (operator_i)
`OPERATOR_SLL : begin
result_shift <= operand_b_i << operand_a_i[4:0];
end
`OPERATOR_SRL : begin
result_shift <= operand_b_i >> operand_a_i[4:0];
end
`OPERATOR_SRA : begin
result_shift <= ({32 {operand_b_i[31]}} << (6'd32 - {1'b0, operand_a_i[4:0]})) | operand_b_i >> operand_a_i[4:0];
end
default : begin
result_shift <= 32'b0;
end
endcase
end
end
reg [31:0] result_move;
always @ (*) begin
if (reset == `RESET_ENABLE) begin
result_move <= 32'b0;
end
else begin
case (operator_i)
`OPERATOR_MFHI : begin
result_move <= register_hi;
end
`OPERATOR_MFLO : begin
result_move <= register_lo;
end
`OPERATOR_MOVN : begin
result_move <= operand_a_i;
end
`OPERATOR_MOVZ : begin
result_move <= operand_a_i;
end
default : begin
result_move <= 32'b0;
end
endcase
end
end
reg [63:0] result_arithmetic;
always @ (*) begin
if (reset == `RESET_ENABLE) begin
result_arithmetic <= 32'b0;
end
else begin
case (operator_i)
`OPERATOR_SLT : begin
result_arithmetic <= (operand_a_i[31] == 1'b1 && operand_b_i[31] == 1'b0) ||
(operand_a_i[31] == 1'b0 && operand_b_i[31] == 1'b0 && operand_sum[31] == 1'b1) ||
(operand_a_i[31] == 1'b1 && operand_b_i[31] == 1'b1 && operand_sum[31] == 1'b1);
end
`OPERATOR_SLTU : begin
result_arithmetic <= operand_a_i < operand_b_i;
end
`OPERATOR_ADD, `OPERATOR_ADDU, `OPERATOR_SUB, `OPERATOR_SUBU : begin
result_arithmetic <= operand_sum;
end
`OPERATOR_CLZ : begin
result_arithmetic <= operand_a_i[31] == 1'b1 ? 32'd0 :
operand_a_i[30] == 1'b1 ? 32'd1 :
operand_a_i[29] == 1'b1 ? 32'd2 :
operand_a_i[28] == 1'b1 ? 32'd3 :
operand_a_i[27] == 1'b1 ? 32'd4 :
operand_a_i[26] == 1'b1 ? 32'd5 :
operand_a_i[25] == 1'b1 ? 32'd6 :
operand_a_i[24] == 1'b1 ? 32'd7 :
operand_a_i[23] == 1'b1 ? 32'd8 :
operand_a_i[22] == 1'b1 ? 32'd9 :
operand_a_i[21] == 1'b1 ? 32'd10 :
operand_a_i[20] == 1'b1 ? 32'd11 :
operand_a_i[19] == 1'b1 ? 32'd12 :
operand_a_i[18] == 1'b1 ? 32'd13 :
operand_a_i[17] == 1'b1 ? 32'd14 :
operand_a_i[16] == 1'b1 ? 32'd15 :
operand_a_i[15] == 1'b1 ? 32'd16 :
operand_a_i[14] == 1'b1 ? 32'd17 :
operand_a_i[13] == 1'b1 ? 32'd18 :
operand_a_i[12] == 1'b1 ? 32'd19 :
operand_a_i[11] == 1'b1 ? 32'd20 :
operand_a_i[10] == 1'b1 ? 32'd21 :
operand_a_i[9] == 1'b1 ? 32'd22 :
operand_a_i[8] == 1'b1 ? 32'd23 :
operand_a_i[7] == 1'b1 ? 32'd24 :
operand_a_i[6] == 1'b1 ? 32'd25 :
operand_a_i[5] == 1'b1 ? 32'd26 :
operand_a_i[4] == 1'b1 ? 32'd27 :
operand_a_i[3] == 1'b1 ? 32'd28 :
operand_a_i[2] == 1'b1 ? 32'd29 :
operand_a_i[1] == 1'b1 ? 32'd30 :
operand_a_i[0] == 1'b1 ? 32'd31 :
32'd32 ;
end
`OPERATOR_CLO : begin
result_arithmetic <= operand_a_i[31] == 1'b0 ? 32'd0 :
operand_a_i[30] == 1'b0 ? 32'd1 :
operand_a_i[29] == 1'b0 ? 32'd2 :
operand_a_i[28] == 1'b0 ? 32'd3 :
operand_a_i[27] == 1'b0 ? 32'd4 :
operand_a_i[26] == 1'b0 ? 32'd5 :
operand_a_i[25] == 1'b0 ? 32'd6 :
operand_a_i[24] == 1'b0 ? 32'd7 :
operand_a_i[23] == 1'b0 ? 32'd8 :
operand_a_i[22] == 1'b0 ? 32'd9 :
operand_a_i[21] == 1'b0 ? 32'd10 :
operand_a_i[20] == 1'b0 ? 32'd11 :
operand_a_i[19] == 1'b0 ? 32'd12 :
operand_a_i[18] == 1'b0 ? 32'd13 :
operand_a_i[17] == 1'b0 ? 32'd14 :
operand_a_i[16] == 1'b0 ? 32'd15 :
operand_a_i[15] == 1'b0 ? 32'd16 :
operand_a_i[14] == 1'b0 ? 32'd17 :
operand_a_i[13] == 1'b0 ? 32'd18 :
operand_a_i[12] == 1'b0 ? 32'd19 :
operand_a_i[11] == 1'b0 ? 32'd20 :
operand_a_i[10] == 1'b0 ? 32'd21 :
operand_a_i[9] == 1'b0 ? 32'd22 :
operand_a_i[8] == 1'b0 ? 32'd23 :
operand_a_i[7] == 1'b0 ? 32'd24 :
operand_a_i[6] == 1'b0 ? 32'd25 :
operand_a_i[5] == 1'b0 ? 32'd26 :
operand_a_i[4] == 1'b0 ? 32'd27 :
operand_a_i[3] == 1'b0 ? 32'd28 :
operand_a_i[2] == 1'b0 ? 32'd29 :
operand_a_i[1] == 1'b0 ? 32'd30 :
operand_a_i[0] == 1'b0 ? 32'd31 :
32'd32 ;
end
`OPERATOR_MULT, `OPERATOR_MUL : begin
if (operand_a_i[31] == 1'b0 && operand_b_i[31] == 1'b0) begin
result_arithmetic <= operand_a_i * operand_b_i;
end
else if (operand_a_i[31] == 1'b0 && operand_b_i[31] == 1'b1) begin
result_arithmetic <= ~(operand_a_i * operand_b_complement) + 1;
end
else if (operand_a_i[31] == 1'b1 && operand_b_i[31] == 1'b0) begin
result_arithmetic <= ~(operand_a_complement * operand_b_i) + 1;
end
else if (operand_a_i[31] == 1'b1 && operand_b_i[31] == 1'b1) begin
result_arithmetic <= operand_a_complement * operand_b_complement;
end
end
`OPERATOR_MULTU : begin
result_arithmetic <= operand_a_i * operand_b_i;
end
default : begin
result_arithmetic <= 32'b0;
end
endcase
end
end
reg [31:0] result_jump;
always @ (*) begin
if (reset == `RESET_ENABLE) begin
result_jump <= 32'b0;
end
else begin
result_jump <= register_write_data_i;
end
end
always @ (*) begin
case (operator_i)
`OPERATOR_ADD : begin
if ((operand_a_i[31] == 1'b0 && operand_b_i[31] == 1'b0 && operand_sum[31] == 1'b1) ||
(operand_a_i[31] == 1'b1 && operand_b_i[31] == 1'b1 && operand_sum[31] == 1'b0)
) begin
register_write_enable_o <= `WRITE_DISABLE;
end
else begin
register_write_enable_o <= register_write_enable_i;
end
end
`OPERATOR_SUB : begin
if ((operand_a_i[31] == 1'b0 && operand_b_complement[31] == 1'b0 && operand_sum[31] == 1'b1) ||
(operand_a_i[31] == 1'b1 && operand_b_complement[31] == 1'b1 && operand_sum[31] == 1'b0)
) begin
register_write_enable_o <= `WRITE_DISABLE;
end
else begin
register_write_enable_o <= register_write_enable_i;
end
end
default : begin
register_write_enable_o <= register_write_enable_i;
end
endcase
register_write_address_o <= register_write_address_i;
case (category)
`CATEGORY_LOGIC : begin
register_write_data_o <= result_logic;
end
`CATEGORY_SHIFT : begin
register_write_data_o <= result_shift;
end
`CATEGORY_MOVE : begin
register_write_data_o <= result_move;
end
`CATEGORY_ARITHMETIC : begin
register_write_data_o <= result_arithmetic[31:0];
end
`CATEGORY_JUMP : begin
register_write_data_o <= result_jump;
end
default : begin
register_write_data_o <= 32'b0;
end
endcase
end
always @ (*) begin
if (reset == `RESET_ENABLE) begin
register_hi_write_enable <= `WRITE_DISABLE;
register_hi_write_data <= 32'b0 ;
register_lo_write_enable <= `WRITE_DISABLE;
register_lo_write_data <= 32'b0 ;
end
else begin
case (operator_i)
`OPERATOR_MTHI : begin
register_hi_write_enable <= `WRITE_ENABLE ;
register_hi_write_data <= operand_a_i ;
register_lo_write_enable <= `WRITE_DISABLE;
register_lo_write_data <= 32'b0 ;
end
`OPERATOR_MTLO : begin
register_hi_write_enable <= `WRITE_DISABLE;
register_hi_write_data <= 32'b0 ;
register_lo_write_enable <= `WRITE_ENABLE ;
register_lo_write_data <= operand_a_i ;
end
`OPERATOR_MULT, `OPERATOR_MULTU : begin
register_hi_write_enable <= `WRITE_ENABLE ;
register_hi_write_data <= result_arithmetic[63:32];
register_lo_write_enable <= `WRITE_ENABLE ;
register_lo_write_data <= result_arithmetic[31:0] ;
end
default : begin
register_hi_write_enable <= `WRITE_DISABLE;
register_hi_write_data <= 32'b0 ;
register_lo_write_enable <= `WRITE_DISABLE;
register_lo_write_data <= 32'b0 ;
end
endcase
end
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date:
// Design Name:
// Module Name: sgb
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
`include "config.vh"
module sgb(
input RST,
output CPU_RST,
input CLK,
input CLK_SYSCLK,
// MMIO interface
//input ENABLE,
input SNES_RD_start,
input SNES_WR_end,
input [23:0] SNES_ADDR,
input [7:0] DATA_IN,
output [7:0] DATA_OUT,
// ROM interface
input ROM_BUS_RDY,
output ROM_BUS_RRQ,
output ROM_BUS_WRQ,
output ROM_BUS_WORD,
output [23:0] ROM_BUS_ADDR,
input [7:0] ROM_BUS_RDDATA,
output [7:0] ROM_BUS_WRDATA,
output ROM_FREE_SLOT,
// Audio interface
output [19:0] APU_DAT,
output APU_CLK_EDGE,
// RTC interface
output [55:0] RTC_DAT,
input [55:0] RTC_DAT_IN,
input RTC_DAT_WE,
input RTC_DAT_RD,
// MBC interface
input [3:0] MAPPER,
input [23:0] SAVERAM_MASK,
input [23:0] ROM_MASK,
// Halt inferface
input HLT_REQ,
output HLT_RSP,
// Debug state
input MCU_RRQ,
input MCU_WRQ,
input [18:0] MCU_ADDR,
input [7:0] MCU_DATA_IN,
output MCU_RSP,
output [7:0] MCU_DATA_OUT,
// Features
input [15:0] FEAT,
// Configuration
input [7:0] reg_group_in,
input [7:0] reg_index_in,
input [7:0] reg_value_in,
input [7:0] reg_invmask_in,
input reg_we_in,
input [7:0] reg_read_in,
output [7:0] config_data_out,
output [11:0] DBG_ADDR,
input [7:0] DBG_CHEAT_DATA_IN,
input [7:0] DBG_MAIN_DATA_IN
);
integer i;
//-------------------------------------------------------------------
// DESCRIPTION
//-------------------------------------------------------------------
// This is an HDL implementation of the Super Game Boy 2 SNES cartridge.
// It is tailored to SD2SNES so that (1) it is easy to maintain along
// with the other cart implementations and (2) improve the chance
// it will fit on the MK2.
//
// Super Game Boy 2
// ----------------
// The SGB2 is a SNES cartridge with the following components
// which allows for a GB game to execute and generate pixel data for the
// SNES to DMA and render with its own PPU. Audio generated by
// the GB APU plays through the L-R analog pins on the cartridge bus.
//
// SGB2-CPU - Unified GB CPU, APU, and PPU chip with integrated 8KB VRAM.
// WRAM - 8KB GB work RAM
// ICD2 - SGB<->SNES interface chip
// SYS-SGB2 - SNES boot and execution ROM
// CIC - protection/lockout chip
//
// Like the original GB, the SGB2 has a 8-bit Z80/8080 ISA compatible CPU,
// a APU supporting 4 channel audio, and a PPU capable of generating
// pixel data for a 160x144 2b gray-scale screen.
//
// In addition to the standard GB hardware the SGB2 also contains the
// SYS-SGB2 and ICD2 chips. These provide the code and interface by
// which the SNES CPU boots and communicates with the GB hardware in
// order to copy and render the GB video output via the SNES PPU.
//
// The ICD2 provides an interface to the GB domain via the GB system bus
// (ICD2, WRAM, GB cart bus) as well as an interface to the SNES domain
// via the SNES cart bus. Row buffers within the ICD2 store digital pixel
// output data from the GB CPU which the SNES typically accesses via DMA.
//
// The SNES ROM provides several standard features including: boot support,
// overlays, palette control, joypad reads, etc. More generally it
// implements a packet-based protocol which enables communication with
// the SGB2's ICD2.
//
// Clocks/Rates:
// 4.194304 MHz fast/cpu clock
// 1.048576 MHz slow/system/bus clock
// 9198 KHz Horizontal Freq
// 59.73 Hz Vertical Freq
//
// Instructions and bus activity take 1 or more bus clocks.
//
// CARTS
// -----
// The SD2SNES must implement not only the SGB2 but also any logic
// supported by the GB cart. The mappers reside in this file.
//
// SD2SNES
// -------
// The SD2SNES MK2 has the following resources available for implementing
// the SGB2:
//
// 16MB PSRAM - GB cart, GB WRAM, GB SaveRAM, GB boot ROM
// 512KB RAM - SNES ROM
// 32KB BRAM - VRAM, OAM, HRAM, SNESCMD, MSU/DAC
// (FPGA)
// 1 DCM/PLL
//
// Address Maps
// ------------
// GAMEBOY
// 0000-3FFF 16KB ROM Bank // PSRAM 000000-7FFFFF
// 4000-7FFF 16KB ROM Bank // PSRAM 000000-7FFFFF
// 8000-9FFF 8KB Video RAM (VRAM) // BRAM 8KB
// A000-BFFF 8KB External RAM (SaveRAM) // PSRAM E00000-EFFFFF 512KB
// C000-CFFF 4KB Work RAM Bank 0 (WRAM) // PSRAM 80C000-80CFFF 4KB
// D000-DFFF 4KB Work RAM Bank 1 (WRAM) // PSRAM 80D000-80DFFF 4KB
// E000-FDFF Same as C000-DDFF (ECHO) (typically not used) // Mirror
// FE00-FE9F Sprite Attribute Table (OAM) // BRAM
// FEA0-FEFF Unused
// FF00-FF7F I/O Ports // Reg
// FF80-FFFE High RAM (HRAM) // BRAM
// FFFF Interrupt Enable Register // Reg
//
// SNES
// 000000-07FFFF SGB SNES ROM (512KB) // 512KB RAM
//
// MCU
// 000000-7FFFFF PSRAM
// 800000-87FFFF SGB
// 800000-8000FF BOOT ROM
// 800100-807FFF <unmapped> see 000000-7FFFFF
// 808000-809FFF VRAM
// 80A000-80BFFF <unmapped> see E00000-EFFFFF
// 80C000-80DFFF WRAM
// 80FE00-80FFFF OAM, IO, etc
// 810000- Debug (read only)
// 880000-8FFFFF RAM
// 900000-FFFFFF PSRAM
wire [15:0] CPU_SYS_ADDR;
wire [1:0] CPU_PPU_PIXEL;
wire [1:0] CPU_P1O;
wire [3:0] CPU_P1I;
wire ICD2_CLK_CPU_EDGE;
wire REG_REQ;
wire [7:0] REG_ADDR;
wire [7:0] REG_REQ_DATA;
reg [7:0] MBC_REG_DATA;
wire [7:0] DBG_DBG_DATA_OUT;
wire [7:0] DBG_MBC_DATA_OUT;
wire ICD2_CPU_RST;
assign CPU_RST = ICD2_CPU_RST;
wire MBC_BUS_RDY;
wire [7:0] MBC_BUS_RDDATA;
parameter CONFIG_REGISTERS = 8;
reg [7:0] config_r[CONFIG_REGISTERS-1:0]; initial for (i = 0; i < CONFIG_REGISTERS; i = i + 1) config_r[i] = 8'h00;
assign APU_CLK_EDGE = ICD2_CLK_CPU_EDGE;
wire CPU_SYS_REQ;
wire CPU_SYS_WR;
wire CPU_BOOTROM_ACTIVE;
wire CPU_FREE_SLOT;
wire CPU_PPU_DOT_EDGE;
wire CPU_PPU_PIXEL_VALID;
wire CPU_PPU_VSYNC_EDGE;
wire CPU_PPU_HSYNC_EDGE;
wire IDL_ICD;
wire [7:0] DBG_ICD2_DATA_OUT;
wire CPU_DBG_BRK;
//-------------------------------------------------------------------
// SGB2-CPU
//-------------------------------------------------------------------
sgb_cpu cpu(
.RST(RST),
.CPU_RST(ICD2_CPU_RST),
.CLK(CLK),
.CLK_CPU_EDGE(ICD2_CLK_CPU_EDGE),
.SYS_RDY(MBC_BUS_RDY),
.SYS_REQ(CPU_SYS_REQ),
.SYS_WR(CPU_SYS_WR),
.SYS_ADDR(CPU_SYS_ADDR),
.SYS_RDDATA(MBC_BUS_RDDATA),
.SYS_WRDATA(ROM_BUS_WRDATA),
.BOOTROM_ACTIVE(CPU_BOOTROM_ACTIVE),
.FREE_SLOT(CPU_FREE_SLOT),
.PPU_DOT_EDGE(CPU_PPU_DOT_EDGE),
.PPU_PIXEL_VALID(CPU_PPU_PIXEL_VALID),
.PPU_PIXEL(CPU_PPU_PIXEL),
.PPU_VSYNC_EDGE(CPU_PPU_VSYNC_EDGE),
.PPU_HSYNC_EDGE(CPU_PPU_HSYNC_EDGE),
.APU_DAT(APU_DAT),
.P1O(CPU_P1O),
.P1I(CPU_P1I),
.HLT_REQ(HLT_REQ),
.HLT_RSP(HLT_RSP),
.IDL_ICD(IDL_ICD),
.FEAT(FEAT),
.REG_REQ(REG_REQ),
.REG_ADDR(REG_ADDR),
.REG_REQ_DATA(REG_REQ_DATA),
.MBC_REG_DATA(MBC_REG_DATA),
.MCU_RRQ(MCU_RRQ),
.MCU_WRQ(MCU_WRQ),
.MCU_ADDR(MCU_ADDR),
.MCU_DATA_IN(MCU_DATA_IN),
.MCU_RSP(MCU_RSP),
.MCU_DATA_OUT(MCU_DATA_OUT),
.DBG_ADDR(DBG_ADDR),
.DBG_ICD2_DATA_IN(DBG_ICD2_DATA_OUT),
.DBG_MBC_DATA_IN(DBG_MBC_DATA_OUT),
.DBG_CHEAT_DATA_IN(DBG_CHEAT_DATA_IN),
.DBG_MAIN_DATA_IN(DBG_MAIN_DATA_IN),
.DBG_CONFIG({config_r[7],config_r[6],config_r[5],config_r[4],config_r[3],config_r[2],config_r[1],config_r[0]}),
.DBG_BRK(CPU_DBG_BRK)
);
//-------------------------------------------------------------------
// ICD2
//-------------------------------------------------------------------
sgb_icd2 icd2(
.RST(RST),
.CPU_RST(ICD2_CPU_RST),
.CLK(CLK),
.CLK_SYSCLK(CLK_SYSCLK),
.CLK_CPU_EDGE(ICD2_CLK_CPU_EDGE),
.SNES_RD_start(SNES_RD_start),
.SNES_WR_end(SNES_WR_end),
.SNES_ADDR(SNES_ADDR),
.DATA_IN(DATA_IN),
.DATA_OUT(DATA_OUT),
.BOOTROM_ACTIVE(CPU_BOOTROM_ACTIVE),
.PPU_DOT_EDGE(CPU_PPU_DOT_EDGE),
.PPU_PIXEL_VALID(CPU_PPU_PIXEL_VALID),
.PPU_PIXEL(CPU_PPU_PIXEL),
.PPU_VSYNC_EDGE(CPU_PPU_VSYNC_EDGE),
.PPU_HSYNC_EDGE(CPU_PPU_HSYNC_EDGE),
.P1I(CPU_P1O),
.P1O(CPU_P1I),
.IDL(IDL_ICD),
.FEAT(FEAT),
.DBG_ADDR(DBG_ADDR),
.DBG_DATA_OUT(DBG_ICD2_DATA_OUT)
);
//-------------------------------------------------------------------
// RTC
//-------------------------------------------------------------------
`define RTC_CTL_DAY 0
`define RTC_CTL_HALT 6
`define RTC_CTL_CARRY 7
reg [5:0] rtc_sec_r = 0; // 08
reg [5:0] rtc_min_r = 0; // 09
reg [4:0] rtc_hrs_r = 0; // 0A
reg [7:0] rtc_day_r = 0; // 0B
reg [7:0] rtc_ctl_r = 0; // 0C
reg [31:0] rtc_tick_r = 0;
reg rtc_write_r;
reg [7:0] rtc_write_address_r;
reg [7:0] rtc_write_data_r;
reg rtc_written_r = 0;
reg dbg_rtc_write_r = 0;
wire rtc_tick_ast = &rtc_tick_r[26:26] & &rtc_tick_r[24:24] & &rtc_tick_r[16:15] & &rtc_tick_r[13:10] & &rtc_tick_r[7:0]; // 84000000-1
wire rtc_sec_ast = &rtc_sec_r[5:3] & &rtc_sec_r[1:0]; // 60-1
wire rtc_min_ast = &rtc_min_r[5:3] & &rtc_min_r[1:0]; // 60-1
wire rtc_hrs_ast = rtc_min_r[4:4] & &rtc_min_r[2:0]; // 23-1
wire rtc_day_ast = &{rtc_ctl_r[`RTC_CTL_DAY],rtc_day_r}; // 511
wire MBC_RTC_write;
wire [7:0] MBC_RTC_address;
wire [7:0] MBC_RTC_data;
assign RTC_DAT = {rtc_written_r, rtc_tick_r[30:24],rtc_tick_r[23:16],rtc_ctl_r,rtc_day_r,3'h0,rtc_hrs_r,2'h0,rtc_min_r,2'h0,rtc_sec_r};
always @(posedge CLK) begin
rtc_tick_r <= (rtc_tick_ast | rtc_ctl_r[`RTC_CTL_HALT]) ? 0 : rtc_tick_r + 1;
if (rtc_tick_ast) rtc_sec_r <= rtc_sec_ast ? 6'd0 : rtc_sec_r + 6'd1;
if (rtc_tick_ast & rtc_sec_ast) rtc_min_r <= rtc_min_ast ? 6'd0 : rtc_min_r + 6'd1;
if (rtc_tick_ast & rtc_sec_ast & rtc_min_ast) rtc_hrs_r <= rtc_hrs_ast ? 5'd0 : rtc_hrs_r + 5'd1;
if (rtc_tick_ast & rtc_sec_ast & rtc_min_ast & rtc_hrs_ast) {rtc_ctl_r[`RTC_CTL_DAY],rtc_day_r} <= rtc_day_ast ? 9'd0 : {rtc_ctl_r[`RTC_CTL_DAY],rtc_day_r} + 9'd1;
if (rtc_tick_ast & rtc_sec_ast & rtc_min_ast & rtc_hrs_ast & rtc_day_ast) rtc_ctl_r[`RTC_CTL_CARRY] <= 1;
if (ICD2_CPU_RST) begin
rtc_write_r <= 0;
end
else begin
rtc_write_r <= 0;
if (MBC_RTC_write) begin
rtc_write_r <= 1;
rtc_write_address_r <= MBC_RTC_address;
rtc_write_data_r <= MBC_RTC_data;
rtc_written_r <= 1;
end
else begin
if (RTC_DAT_RD & ~rtc_ctl_r[`RTC_CTL_HALT]) rtc_written_r <= 0;
end
end
if (rtc_write_r) begin
case (rtc_write_address_r)
8'h08: rtc_sec_r[5:0] <= rtc_write_data_r[5:0];
8'h09: rtc_min_r[5:0] <= rtc_write_data_r[5:0];
8'h0A: rtc_hrs_r[4:0] <= rtc_write_data_r[4:0];
8'h0B: rtc_day_r[7:0] <= rtc_write_data_r[7:0];
8'h0C: rtc_ctl_r[7:0] <= rtc_write_data_r[7:0];
endcase
end
if (RTC_DAT_WE) begin
dbg_rtc_write_r <= 1;
{rtc_tick_r[31:24],rtc_tick_r[23:16],rtc_ctl_r,rtc_day_r,/*3'h0,*/rtc_hrs_r,/*2'h0,*/rtc_min_r,/*2'h0,*/rtc_sec_r} <= {RTC_DAT_IN[55:24],RTC_DAT_IN[20:16],RTC_DAT_IN[13:8],RTC_DAT_IN[5:0]};
end
end
//-------------------------------------------------------------------
// MAP
//-------------------------------------------------------------------
`define MAPPER_ID 2:0
`define MAPPER_EX 3:3
reg [8:0] mbc_rom_bank_r;
reg [8:0] mbc_rom0_bank_r;
reg [6:0] mbc_ram_bank_r;
reg mbc_reg_ram_enabled_r;
reg [7:0] mbc_reg_ram_r;
reg mbc_reg_rom_bank_upper_r;
reg [7:0] mbc_reg_rom_bank_r;
reg [7:0] mbc_reg_bank_r;
reg mbc_reg_mode_r;
reg mbc_rtc_write_r;
reg [7:0] mbc_rtc_sec_r = 0;
reg [7:0] mbc_rtc_min_r = 0;
reg [7:0] mbc_rtc_hrs_r = 0;
reg [7:0] mbc_rtc_day_r = 0;
reg [7:0] mbc_rtc_ctl_r = 0;
`define MBC_DELAY 2 // minimum 2
reg [`MBC_DELAY-1:0] mbc_req_r;
reg mbc_req_rtc_r;
reg mbc_req_hc3_r;
reg mbc_req_cam_r;
reg mbc_req_srm_mbc2_r;
reg [7:0] mbc_data_r;
reg [7:0] mbc_hc3_data_r;
reg [7:0] dbg_data_r;
// provide state for saves
always @(*) begin
case (REG_ADDR)
8'h70: MBC_REG_DATA = mbc_reg_ram_enabled_r;
8'h71: MBC_REG_DATA = mbc_reg_rom_bank_upper_r;
8'h72: MBC_REG_DATA = mbc_reg_rom_bank_r;
8'h73: MBC_REG_DATA = mbc_reg_bank_r;
8'h74: MBC_REG_DATA = mbc_reg_mode_r;
default: MBC_REG_DATA = 0;
endcase
end
// handle expansion bit
`ifdef SGB_EXTRA_MAPPERS
wire mbc_map_hc3 = MAPPER[`MAPPER_EX] && MAPPER[`MAPPER_ID] == 4; // HUC3 (incomplete)
wire mbc_map_cam = MAPPER[`MAPPER_EX] && MAPPER[`MAPPER_ID] == 5; // CAM (incomplete)
`else
wire mbc_map_hc3 = 0;
wire mbc_map_cam = 0;
`endif
wire mbc_map_rtc = MAPPER[`MAPPER_EX] && MAPPER[`MAPPER_ID] == 3; // MBC3 supports RTC
wire mbc_map_mlt = MAPPER[`MAPPER_EX] && MAPPER[`MAPPER_ID] == 1; // MBC1 supports (M)ulticart (MBC1M)
// MAP has logic to translate the CPU address
// to ROM (bootROM), SaveRAM, and WRAM addresses. It represents
// the cartridge addressing logic, some basic CPU address
// logic to handle boot ROM, as well as SD2SNES specific addressing.
// NOTE: we can ignore checking address for 8000-9FFF because they are never sent here
// These are only valid on the first cycle of the request.
wire mbc_bus_mbc = CPU_SYS_REQ & CPU_SYS_WR & ~CPU_SYS_ADDR[15];
wire mbc_bus_dis = CPU_SYS_REQ & CPU_SYS_WR & CPU_SYS_ADDR[15] & ~CPU_SYS_ADDR[14] & ~mbc_reg_ram_enabled_r;
wire mbc_bus_rtc = CPU_SYS_REQ & CPU_SYS_ADDR[15] & ~CPU_SYS_ADDR[14] & mbc_reg_ram_enabled_r & |mbc_reg_bank_r[7:3] & mbc_map_rtc;
wire mbc_bus_hc3 = CPU_SYS_REQ & CPU_SYS_ADDR[15] & ~CPU_SYS_ADDR[14] & (8'hB <= mbc_reg_ram_r[7:0] && mbc_reg_ram_r[7:0] <= 8'hD) & mbc_map_hc3;
wire mbc_bus_cam = CPU_SYS_REQ & CPU_SYS_ADDR[15] & ~CPU_SYS_ADDR[14] & mbc_reg_bank_r[4] & mbc_map_cam;
wire mbc_bus_req = mbc_bus_mbc | mbc_bus_rtc | mbc_bus_hc3 | mbc_bus_cam | mbc_bus_dis;
assign ROM_BUS_RRQ = CPU_SYS_REQ & ~CPU_SYS_WR & ~mbc_bus_req;
assign ROM_BUS_WRQ = CPU_SYS_REQ & CPU_SYS_WR & ~mbc_bus_req;
assign ROM_BUS_WORD = 0; // SGB has 8b data bus
wire BOOTROM = CPU_BOOTROM_ACTIVE & ~|CPU_SYS_ADDR[13:8];
assign ROM_BUS_ADDR = ( (~|CPU_SYS_ADDR[15:14]) ? ({BOOTROM,(mbc_rom0_bank_r[8:0] & ROM_MASK[22:14]),(CPU_SYS_ADDR[13:0] & ROM_MASK[13:0])}) // ROM 0000-3FFF -> 000000-003FFF,800000-8000FF (cart+boot)
: (~CPU_SYS_ADDR[15]) ? ({1'h0, (mbc_rom_bank_r[8:0] & ROM_MASK[22:14]),(CPU_SYS_ADDR[13:0] & ROM_MASK[13:0])}) // ROM 4000-7FFF -> 004000-7FFFFF (cart)
// VRAM 8000-9FFF -> NA - 8 KB (BRAM)
: (~CPU_SYS_ADDR[14]) ? {4'hE,(mbc_ram_bank_r[6:0] & SAVERAM_MASK[19:13]),(CPU_SYS_ADDR[12:0] & SAVERAM_MASK[12:0])} // SaveRAM A000-BFFF -> E00000-EFFFFF - 8KB
: {8'h80,3'b110, CPU_SYS_ADDR[12:0]} // WRAM C000-DFFF -> 80C000-80DFFF 4+4=8KB
); // E000-FDFF -> 80C000-80DDFF (mirror of C000-DDFF)
// OAM FE00-FE9F -> NA - 160B (BRAM)
// - FEA0-FEFF -> NA
// REG FF00-FF7F -> NA - 128B (REG)
// FFFF
// HRAM FF80-FFFE -> NA - 127B (BRAM)
assign DBG_MBC_DATA_OUT = dbg_data_r;
assign ROM_FREE_SLOT = CPU_FREE_SLOT;
assign MBC_BUS_RDY = ~|mbc_req_r ? ROM_BUS_RDY : mbc_req_r[`MBC_DELAY-1];
assign MBC_BUS_RDDATA = ~|mbc_req_r ? {(mbc_req_srm_mbc2_r ? 4'hF : ROM_BUS_RDDATA[7:4]),ROM_BUS_RDDATA[3:0]} : mbc_data_r;
assign MBC_RTC_write = mbc_rtc_write_r;
assign MBC_RTC_address = mbc_reg_bank_r[7:0];
assign MBC_RTC_data = ROM_BUS_WRDATA;
always @(posedge CLK) begin
if (RST) begin
mbc_reg_ram_enabled_r <= 0;
mbc_reg_ram_r <= 0;
mbc_reg_rom_bank_upper_r <= 0;
mbc_reg_rom_bank_r <= 8'h01;
mbc_reg_bank_r <= 8'h00;
mbc_reg_mode_r <= 0;
mbc_hc3_data_r <= 1;
end
else begin
if (mbc_bus_mbc) begin
if (MAPPER[`MAPPER_ID] == 2) begin
if (~CPU_SYS_ADDR[14]) begin
if (CPU_SYS_ADDR[8]) mbc_reg_rom_bank_r[7:0] <= ROM_BUS_WRDATA[7:0]; else mbc_reg_ram_enabled_r <= (ROM_BUS_WRDATA[3:0] == 4'hA) ? 1'b1 : 1'b0;
end
end
else begin
case (CPU_SYS_ADDR[14:13])
0: begin
mbc_reg_ram_enabled_r <= (ROM_BUS_WRDATA[3:0] == 4'hA) ? 1'b1 : 1'b0;
mbc_reg_ram_r <= ROM_BUS_WRDATA[7:0];
end
1: begin
if (MAPPER[`MAPPER_ID] == 3) begin
if (CPU_SYS_ADDR[12]) mbc_reg_rom_bank_upper_r <= ROM_BUS_WRDATA[0]; else mbc_reg_rom_bank_r[7:0] <= ROM_BUS_WRDATA[7:0];
end
else begin
mbc_reg_rom_bank_upper_r <= 0;
mbc_reg_rom_bank_r[7:0] <= ROM_BUS_WRDATA[7:0];
end
end
2: mbc_reg_bank_r[7:0] <= ROM_BUS_WRDATA[7:0];
3: begin
mbc_reg_mode_r <= ROM_BUS_WRDATA[0];
if (~mbc_reg_mode_r & ROM_BUS_WRDATA[0]) begin
// Save RTC for MBC3
mbc_rtc_sec_r <= {2'h0,rtc_sec_r};
mbc_rtc_min_r <= {2'h0,rtc_min_r};
mbc_rtc_hrs_r <= {3'h0,rtc_hrs_r};
mbc_rtc_day_r <= rtc_day_r;
mbc_rtc_ctl_r <= rtc_ctl_r;
end
end
endcase
end
end
end
if (ICD2_CPU_RST) begin
mbc_req_r <= 0;
mbc_req_srm_mbc2_r <= 0;
mbc_rtc_write_r <= 0;
end
else begin
// MBC memory requests
mbc_req_r <= {mbc_req_r[`MBC_DELAY-2:0],mbc_bus_req};
if (CPU_SYS_REQ) mbc_req_rtc_r <= mbc_bus_rtc;
if (CPU_SYS_REQ) mbc_req_hc3_r <= mbc_bus_hc3;
if (CPU_SYS_REQ) mbc_req_cam_r <= mbc_bus_cam;
if (CPU_SYS_REQ) mbc_req_srm_mbc2_r <= MAPPER[`MAPPER_ID] == 2 && (CPU_SYS_ADDR[15] & ~CPU_SYS_ADDR[14]);
if (mbc_req_r[0]) begin
if (mbc_req_rtc_r) begin
case (mbc_reg_bank_r)
8'h08: mbc_data_r <= mbc_rtc_sec_r;
8'h09: mbc_data_r <= mbc_rtc_min_r;
8'h0A: mbc_data_r <= mbc_rtc_hrs_r;
8'h0B: mbc_data_r <= mbc_rtc_day_r;
8'h0C: mbc_data_r <= {mbc_rtc_ctl_r[7:6],5'h1F,mbc_rtc_ctl_r[0]};
default: mbc_data_r <= 8'hFF;
endcase
end
else if (mbc_req_hc3_r) begin
case (mbc_reg_ram_r)
8'h0D: mbc_data_r <= 1;
default: mbc_data_r <= mbc_hc3_data_r;
endcase
end
else if (mbc_req_cam_r) begin
mbc_data_r <= 0; // not implemented
end
else begin
mbc_data_r <= 8'hFF;
end
end
if (mbc_bus_rtc & CPU_SYS_WR) begin
mbc_rtc_write_r <= 1;
end
else if (rtc_write_r) begin
mbc_rtc_write_r <= 0;
end
end
mbc_ram_bank_r[6:0] <= ( MAPPER[`MAPPER_ID] == 1 ? {5'h00,((mbc_reg_mode_r & ~mbc_map_mlt) ? mbc_reg_bank_r[1:0] : 2'h0)}
: MAPPER[`MAPPER_ID] == 2 ? 7'h00
: MAPPER[`MAPPER_ID] == 3 ? {3'h0,mbc_reg_bank_r[3:0]}
`ifdef SGB_EXTRA_MAPPERS
: MAPPER[`MAPPER_ID] == 4 ? ((MAPPER[`MAPPER_EX] | mbc_reg_mode_r) ? {3'h0,mbc_reg_bank_r[3:0]} : 7'h00)
`endif
: MAPPER[`MAPPER_ID] == 5 ? {3'h0,mbc_reg_bank_r[3:0]}
: 7'h00
);
mbc_rom_bank_r[8:0] <= ( MAPPER[`MAPPER_ID] == 1 ? (mbc_map_mlt ? {3'h0,mbc_reg_bank_r[1],({mbc_reg_bank_r[0],mbc_reg_rom_bank_r[3:0]} | ~|{mbc_reg_bank_r[0],mbc_reg_rom_bank_r[3:0]})}
: {2'h0,mbc_reg_bank_r[1:0],(mbc_reg_rom_bank_r[4:0] | ~|mbc_reg_rom_bank_r[4:0])})
: MAPPER[`MAPPER_ID] == 2 ? {5'h00,mbc_reg_rom_bank_r[3:0] | ~|mbc_reg_rom_bank_r[3:0]}
: MAPPER[`MAPPER_ID] == 3 ? {1'b0,mbc_reg_rom_bank_r[7:0] | ~|mbc_reg_rom_bank_r[7:0]}
`ifdef SGB_EXTRA_MAPPERS
: MAPPER[`MAPPER_ID] == 4 ? {((MAPPER[`MAPPER_EX] | mbc_reg_mode_r) ? {1'b0,mbc_reg_rom_bank_r[7:6]} : mbc_reg_bank_r[2:0]),(mbc_reg_rom_bank_r[5:0] | ~|mbc_reg_rom_bank_r[5:0])}
`endif
: MAPPER[`MAPPER_ID] == 5 ? {mbc_reg_rom_bank_upper_r,mbc_reg_rom_bank_r[7:0]}
: 9'h001
);
mbc_rom0_bank_r[8:0] <= ( MAPPER[`MAPPER_ID] == 1 ? {2'h0,(mbc_reg_mode_r ? (mbc_map_mlt ? {1'b0,mbc_reg_bank_r[1:0]} : {mbc_reg_bank_r[1:0],1'b0}) : 3'h0),4'h0}
: 9'h000
);
`ifdef SGB_SAVE_STATES
// write in state for loads
if (REG_REQ) begin
case (REG_ADDR)
8'h70: mbc_reg_ram_enabled_r <= REG_REQ_DATA[0];
8'h71: mbc_reg_rom_bank_upper_r <= REG_REQ_DATA[0];
8'h72: mbc_reg_rom_bank_r <= REG_REQ_DATA;
8'h73: mbc_reg_bank_r <= REG_REQ_DATA;
8'h74: mbc_reg_mode_r <= REG_REQ_DATA[0];
endcase
end
`endif
`ifdef SGB_DEBUG
casez(DBG_ADDR[3:0])
4'h0: dbg_data_r <= mbc_reg_ram_enabled_r;
4'h1: dbg_data_r <= mbc_reg_mode_r;
4'h2: dbg_data_r <= mbc_reg_rom_bank_r;
4'h3: dbg_data_r <= mbc_reg_bank_r;
4'h4: dbg_data_r <= mbc_rom_bank_r[7:0]; // missing bit 8
4'h5: dbg_data_r <= mbc_ram_bank_r;
4'h6: dbg_data_r <= CPU_BOOTROM_ACTIVE;
4'h7: dbg_data_r <= dbg_rtc_write_r;
4'h8: dbg_data_r <= rtc_sec_r;
4'h9: dbg_data_r <= rtc_min_r;
4'hA: dbg_data_r <= rtc_hrs_r;
4'hB: dbg_data_r <= rtc_day_r;
4'hC: dbg_data_r <= rtc_ctl_r;
4'hD: dbg_data_r <= MAPPER;
4'hE: dbg_data_r <= mbc_req_r;
4'hF: dbg_data_r <= mbc_data_r;
default: dbg_data_r <= 0;
endcase
`endif
end
`ifdef SGB_DEBUG
//-------------------------------------------------------------------
// CONFIG
//-------------------------------------------------------------------
always @(posedge CLK) begin
if (reg_we_in && (reg_group_in == 8'h03)) begin
if (reg_index_in < CONFIG_REGISTERS) config_r[reg_index_in] <= (config_r[reg_index_in] & reg_invmask_in) | (reg_value_in & ~reg_invmask_in);
end
else begin
config_r[0][0] <= config_r[0][0] | CPU_DBG_BRK;
end
end
assign config_data_out = config_r[reg_read_in];
`endif
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: dram_ddr_pad_rptr_south.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module dram_ddr_pad_rptr_south ( /*AUTOARG*/
// Outputs
io_dram_data_valid_buf, io_dram_ecc_in_buf, io_dram_data_in_buf,
dram_io_cas_l_buf, dram_io_channel_disabled_buf, dram_io_cke_buf,
dram_io_clk_enable_buf, dram_io_drive_data_buf,
dram_io_drive_enable_buf, dram_io_pad_clk_inv_buf,
dram_io_pad_enable_buf, dram_io_ras_l_buf, dram_io_write_en_l_buf,
dram_io_addr_buf, dram_io_bank_buf, dram_io_cs_l_buf,
dram_io_data_out_buf, dram_io_ptr_clk_inv_buf,
// Inputs
io_dram_data_valid, io_dram_ecc_in, io_dram_data_in,
dram_io_cas_l, dram_io_channel_disabled, dram_io_cke,
dram_io_clk_enable, dram_io_drive_data, dram_io_drive_enable,
dram_io_pad_clk_inv, dram_io_pad_enable, dram_io_ras_l,
dram_io_write_en_l, dram_io_addr, dram_io_bank, dram_io_cs_l,
dram_io_data_out, dram_io_ptr_clk_inv
);
/*OUTPUTS*/
output io_dram_data_valid_buf;
output [31:0] io_dram_ecc_in_buf;
output [255:0] io_dram_data_in_buf;
output dram_io_cas_l_buf;
output dram_io_channel_disabled_buf;
output dram_io_cke_buf;
output dram_io_clk_enable_buf;
output dram_io_drive_data_buf;
output dram_io_drive_enable_buf;
output dram_io_pad_clk_inv_buf;
output dram_io_pad_enable_buf;
output dram_io_ras_l_buf;
output dram_io_write_en_l_buf;
output [14:0] dram_io_addr_buf;
output [2:0] dram_io_bank_buf;
output [3:0] dram_io_cs_l_buf;
output [287:0] dram_io_data_out_buf;
output [4:0] dram_io_ptr_clk_inv_buf;
/*INPUTS*/
input io_dram_data_valid;
input [31:0] io_dram_ecc_in;
input [255:0] io_dram_data_in;
input dram_io_cas_l;
input dram_io_channel_disabled;
input dram_io_cke;
input dram_io_clk_enable;
input dram_io_drive_data;
input dram_io_drive_enable;
input dram_io_pad_clk_inv;
input dram_io_pad_enable;
input dram_io_ras_l;
input dram_io_write_en_l;
input [14:0] dram_io_addr;
input [2:0] dram_io_bank;
input [3:0] dram_io_cs_l;
input [287:0] dram_io_data_out;
input [4:0] dram_io_ptr_clk_inv;
/************************* CODE *********************************/
assign io_dram_data_in_buf = io_dram_data_in[255:0];
assign io_dram_data_valid_buf = io_dram_data_valid;
assign io_dram_ecc_in_buf = io_dram_ecc_in[31:0];
assign dram_io_addr_buf = dram_io_addr[14:0];
assign dram_io_bank_buf = dram_io_bank[2:0];
assign dram_io_cas_l_buf = dram_io_cas_l;
assign dram_io_channel_disabled_buf = dram_io_channel_disabled;
assign dram_io_cke_buf = dram_io_cke;
assign dram_io_clk_enable_buf = dram_io_clk_enable;
assign dram_io_cs_l_buf = dram_io_cs_l[3:0];
assign dram_io_data_out_buf = dram_io_data_out[287:0];
assign dram_io_drive_data_buf = dram_io_drive_data;
assign dram_io_drive_enable_buf = dram_io_drive_enable;
assign dram_io_pad_clk_inv_buf = dram_io_pad_clk_inv;
assign dram_io_pad_enable_buf = dram_io_pad_enable;
assign dram_io_ptr_clk_inv_buf = dram_io_ptr_clk_inv[4:0];
assign dram_io_ras_l_buf = dram_io_ras_l;
assign dram_io_write_en_l_buf = dram_io_write_en_l;
endmodule
|
// Generated by FIR Compiler
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
// Copyright (C) 1991-2005 Altera Corporation
// Any megafunction design, and related net list (encrypted or decrypted),
// support information, device programming or simulation file, and any other
// associated documentation or information provided by Altera or a partner
// under Altera's Megafunction Partnership Program may be used only to
// program PLD devices (but not masked PLD devices) from Altera. Any other
// use of such megafunction design, net list, support information, device
// programming or simulation file, or any other related documentation or
// information is prohibited for any other purpose, including, but not
// limited to modification, reverse engineering, de-compiling, or use with
// any other silicon devices, unless such use is explicitly licensed under
// a separate agreement with Altera or a megafunction partner. Title to
// the intellectual property, including patents, copyrights, trademarks,
// trade secrets, or maskworks, embodied in any such megafunction design,
// net list, support information, device programming or simulation file, or
// any other related documentation or information provided by Altera or a
// megafunction partner, remains with Altera, the megafunction partner, or
// their respective licensors. No other licenses, including any licenses
// needed under any third party's intellectual property, are provided herein.
// 00
// altera message_off 10036
(* altera_attribute = "-name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410" *)
module fir_band_pass_st (clk,
rst,
data_in,
clk_en,
rdy_to_ld,
done,
fir_result);
parameter DATA_WIDTH = 11;
parameter COEF_WIDTH = 11;
parameter ACCUM_WIDTH = 24;
parameter MSB_RM = 0;
parameter LSB_RM = 8;
parameter WIDTH_SAT = ACCUM_WIDTH-LSB_RM;
input clk, rst;
input [DATA_WIDTH-1:0] data_in;
input clk_en;
output rdy_to_ld;
wire rdy_to_ld;
wire rdy_int;
wire data_ld;
output done;
wire done;
wire done_int;
output [ACCUM_WIDTH-MSB_RM-LSB_RM-1:0] fir_result;
wire addr_low;
assign addr_low = 1'b0;
//--- Parallel TDL Storage ---
wire inv_rst;
assign inv_rst = ~rst;
assign data_ld = rdy_int;
wire [10:0] tdl_0_n;
wire [10:0] tdl_1_n;
wire [10:0] tdl_2_n;
wire [10:0] tdl_3_n;
wire [10:0] tdl_4_n;
wire [10:0] tdl_5_n;
wire [10:0] tdl_6_n;
wire [10:0] tdl_7_n;
wire [10:0] tdl_8_n;
wire [10:0] tdl_9_n;
wire [10:0] tdl_10_n;
wire [10:0] tdl_11_n;
wire [10:0] tdl_12_n;
wire [10:0] tdl_13_n;
wire [10:0] tdl_14_n;
wire [10:0] tdl_15_n;
wire [10:0] tdl_16_n;
wire [10:0] tdl_17_n;
wire [10:0] tdl_18_n;
wire [10:0] tdl_19_n;
wire [10:0] tdl_20_n;
wire [10:0] tdl_21_n;
wire [10:0] tdl_22_n;
wire [10:0] tdl_23_n;
wire [10:0] tdl_24_n;
wire [10:0] tdl_25_n;
wire [10:0] tdl_26_n;
wire [10:0] tdl_27_n;
wire [10:0] tdl_28_n;
wire [10:0] tdl_29_n;
wire [10:0] tdl_30_n;
wire [10:0] tdl_31_n;
//--- TDL ---
tdl_da_lc Utdldalc0n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(data_in), .data_out(tdl_0_n) );
defparam Utdldalc0n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc1n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_0_n), .data_out(tdl_1_n) );
defparam Utdldalc1n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc2n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_1_n), .data_out(tdl_2_n) );
defparam Utdldalc2n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc3n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_2_n), .data_out(tdl_3_n) );
defparam Utdldalc3n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc4n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_3_n), .data_out(tdl_4_n) );
defparam Utdldalc4n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc5n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_4_n), .data_out(tdl_5_n) );
defparam Utdldalc5n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc6n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_5_n), .data_out(tdl_6_n) );
defparam Utdldalc6n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc7n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_6_n), .data_out(tdl_7_n) );
defparam Utdldalc7n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc8n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_7_n), .data_out(tdl_8_n) );
defparam Utdldalc8n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc9n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_8_n), .data_out(tdl_9_n) );
defparam Utdldalc9n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc10n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_9_n), .data_out(tdl_10_n) );
defparam Utdldalc10n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc11n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_10_n), .data_out(tdl_11_n) );
defparam Utdldalc11n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc12n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_11_n), .data_out(tdl_12_n) );
defparam Utdldalc12n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc13n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_12_n), .data_out(tdl_13_n) );
defparam Utdldalc13n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc14n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_13_n), .data_out(tdl_14_n) );
defparam Utdldalc14n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc15n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_14_n), .data_out(tdl_15_n) );
defparam Utdldalc15n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc16n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_15_n), .data_out(tdl_16_n) );
defparam Utdldalc16n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc17n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_16_n), .data_out(tdl_17_n) );
defparam Utdldalc17n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc18n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_17_n), .data_out(tdl_18_n) );
defparam Utdldalc18n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc19n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_18_n), .data_out(tdl_19_n) );
defparam Utdldalc19n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc20n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_19_n), .data_out(tdl_20_n) );
defparam Utdldalc20n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc21n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_20_n), .data_out(tdl_21_n) );
defparam Utdldalc21n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc22n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_21_n), .data_out(tdl_22_n) );
defparam Utdldalc22n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc23n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_22_n), .data_out(tdl_23_n) );
defparam Utdldalc23n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc24n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_23_n), .data_out(tdl_24_n) );
defparam Utdldalc24n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc25n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_24_n), .data_out(tdl_25_n) );
defparam Utdldalc25n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc26n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_25_n), .data_out(tdl_26_n) );
defparam Utdldalc26n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc27n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_26_n), .data_out(tdl_27_n) );
defparam Utdldalc27n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc28n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_27_n), .data_out(tdl_28_n) );
defparam Utdldalc28n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc29n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_28_n), .data_out(tdl_29_n) );
defparam Utdldalc29n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc30n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_29_n), .data_out(tdl_30_n) );
defparam Utdldalc30n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc31n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_30_n), .data_out(tdl_31_n) );
defparam Utdldalc31n.WIDTH = DATA_WIDTH;
// --- ROM LUTs ----
// symmetrical adders ...
wire [11:0] sym_res_0_n;
sadd_cen U_0_sym_add (.clk(clk), .gclk_en(clk_en), .ain(tdl_0_n), .bin(tdl_31_n), .res(sym_res_0_n) );
defparam U_0_sym_add.IN_WIDTH = 11;
defparam U_0_sym_add.PIPE_DEPTH = 1;
wire [11:0] sym_res_1_n;
sadd_cen U_1_sym_add (.clk(clk), .gclk_en(clk_en), .ain(tdl_1_n), .bin(tdl_30_n), .res(sym_res_1_n) );
defparam U_1_sym_add.IN_WIDTH = 11;
defparam U_1_sym_add.PIPE_DEPTH = 1;
wire [11:0] sym_res_2_n;
sadd_cen U_2_sym_add (.clk(clk), .gclk_en(clk_en), .ain(tdl_2_n), .bin(tdl_29_n), .res(sym_res_2_n) );
defparam U_2_sym_add.IN_WIDTH = 11;
defparam U_2_sym_add.PIPE_DEPTH = 1;
wire [11:0] sym_res_3_n;
sadd_cen U_3_sym_add (.clk(clk), .gclk_en(clk_en), .ain(tdl_3_n), .bin(tdl_28_n), .res(sym_res_3_n) );
defparam U_3_sym_add.IN_WIDTH = 11;
defparam U_3_sym_add.PIPE_DEPTH = 1;
wire [11:0] sym_res_4_n;
sadd_cen U_4_sym_add (.clk(clk), .gclk_en(clk_en), .ain(tdl_4_n), .bin(tdl_27_n), .res(sym_res_4_n) );
defparam U_4_sym_add.IN_WIDTH = 11;
defparam U_4_sym_add.PIPE_DEPTH = 1;
wire [11:0] sym_res_5_n;
sadd_cen U_5_sym_add (.clk(clk), .gclk_en(clk_en), .ain(tdl_5_n), .bin(tdl_26_n), .res(sym_res_5_n) );
defparam U_5_sym_add.IN_WIDTH = 11;
defparam U_5_sym_add.PIPE_DEPTH = 1;
wire [11:0] sym_res_6_n;
sadd_cen U_6_sym_add (.clk(clk), .gclk_en(clk_en), .ain(tdl_6_n), .bin(tdl_25_n), .res(sym_res_6_n) );
defparam U_6_sym_add.IN_WIDTH = 11;
defparam U_6_sym_add.PIPE_DEPTH = 1;
wire [11:0] sym_res_7_n;
sadd_cen U_7_sym_add (.clk(clk), .gclk_en(clk_en), .ain(tdl_7_n), .bin(tdl_24_n), .res(sym_res_7_n) );
defparam U_7_sym_add.IN_WIDTH = 11;
defparam U_7_sym_add.PIPE_DEPTH = 1;
wire [11:0] sym_res_8_n;
sadd_cen U_8_sym_add (.clk(clk), .gclk_en(clk_en), .ain(tdl_8_n), .bin(tdl_23_n), .res(sym_res_8_n) );
defparam U_8_sym_add.IN_WIDTH = 11;
defparam U_8_sym_add.PIPE_DEPTH = 1;
wire [11:0] sym_res_9_n;
sadd_cen U_9_sym_add (.clk(clk), .gclk_en(clk_en), .ain(tdl_9_n), .bin(tdl_22_n), .res(sym_res_9_n) );
defparam U_9_sym_add.IN_WIDTH = 11;
defparam U_9_sym_add.PIPE_DEPTH = 1;
wire [11:0] sym_res_10_n;
sadd_cen U_10_sym_add (.clk(clk), .gclk_en(clk_en), .ain(tdl_10_n), .bin(tdl_21_n), .res(sym_res_10_n) );
defparam U_10_sym_add.IN_WIDTH = 11;
defparam U_10_sym_add.PIPE_DEPTH = 1;
wire [11:0] sym_res_11_n;
sadd_cen U_11_sym_add (.clk(clk), .gclk_en(clk_en), .ain(tdl_11_n), .bin(tdl_20_n), .res(sym_res_11_n) );
defparam U_11_sym_add.IN_WIDTH = 11;
defparam U_11_sym_add.PIPE_DEPTH = 1;
wire [11:0] sym_res_12_n;
sadd_cen U_12_sym_add (.clk(clk), .gclk_en(clk_en), .ain(tdl_12_n), .bin(tdl_19_n), .res(sym_res_12_n) );
defparam U_12_sym_add.IN_WIDTH = 11;
defparam U_12_sym_add.PIPE_DEPTH = 1;
wire [11:0] sym_res_13_n;
sadd_cen U_13_sym_add (.clk(clk), .gclk_en(clk_en), .ain(tdl_13_n), .bin(tdl_18_n), .res(sym_res_13_n) );
defparam U_13_sym_add.IN_WIDTH = 11;
defparam U_13_sym_add.PIPE_DEPTH = 1;
wire [11:0] sym_res_14_n;
sadd_cen U_14_sym_add (.clk(clk), .gclk_en(clk_en), .ain(tdl_14_n), .bin(tdl_17_n), .res(sym_res_14_n) );
defparam U_14_sym_add.IN_WIDTH = 11;
defparam U_14_sym_add.PIPE_DEPTH = 1;
wire [11:0] sym_res_15_n;
sadd_cen U_15_sym_add (.clk(clk), .gclk_en(clk_en), .ain(tdl_15_n), .bin(tdl_16_n), .res(sym_res_15_n) );
defparam U_15_sym_add.IN_WIDTH = 11;
defparam U_15_sym_add.PIPE_DEPTH = 1;
wire [10:0] lut_val_0_n_0_pp;
rom_lut_r_cen Ur0_n_0_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_4_n[0],sym_res_3_n[0],sym_res_2_n[0],sym_res_1_n[0] } ), .data_out( lut_val_0_n_0_pp[5:0]) ) ;
defparam Ur0_n_0_pp.DATA_WIDTH = 6;
defparam Ur0_n_0_pp.C0 = 6'd 0;
defparam Ur0_n_0_pp.C1 = 6'd 1;
defparam Ur0_n_0_pp.C2 = 6'd 59;
defparam Ur0_n_0_pp.C3 = 6'd 60;
defparam Ur0_n_0_pp.C4 = 6'd 50;
defparam Ur0_n_0_pp.C5 = 6'd 51;
defparam Ur0_n_0_pp.C6 = 6'd 45;
defparam Ur0_n_0_pp.C7 = 6'd 46;
defparam Ur0_n_0_pp.C8 = 6'd 2;
defparam Ur0_n_0_pp.C9 = 6'd 3;
defparam Ur0_n_0_pp.CA = 6'd 61;
defparam Ur0_n_0_pp.CB = 6'd 62;
defparam Ur0_n_0_pp.CC = 6'd 52;
defparam Ur0_n_0_pp.CD = 6'd 53;
defparam Ur0_n_0_pp.CE = 6'd 47;
defparam Ur0_n_0_pp.CF = 6'd 48;
assign lut_val_0_n_0_pp[10] = lut_val_0_n_0_pp[5];
assign lut_val_0_n_0_pp[9] = lut_val_0_n_0_pp[5];
assign lut_val_0_n_0_pp[8] = lut_val_0_n_0_pp[5];
assign lut_val_0_n_0_pp[7] = lut_val_0_n_0_pp[5];
assign lut_val_0_n_0_pp[6] = lut_val_0_n_0_pp[5];
wire [10:0] lut_val_0_n_1_pp;
rom_lut_r_cen Ur0_n_1_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_4_n[1],sym_res_3_n[1],sym_res_2_n[1],sym_res_1_n[1] } ), .data_out( lut_val_0_n_1_pp[5:0]) ) ;
defparam Ur0_n_1_pp.DATA_WIDTH = 6;
defparam Ur0_n_1_pp.C0 = 6'd 0;
defparam Ur0_n_1_pp.C1 = 6'd 1;
defparam Ur0_n_1_pp.C2 = 6'd 59;
defparam Ur0_n_1_pp.C3 = 6'd 60;
defparam Ur0_n_1_pp.C4 = 6'd 50;
defparam Ur0_n_1_pp.C5 = 6'd 51;
defparam Ur0_n_1_pp.C6 = 6'd 45;
defparam Ur0_n_1_pp.C7 = 6'd 46;
defparam Ur0_n_1_pp.C8 = 6'd 2;
defparam Ur0_n_1_pp.C9 = 6'd 3;
defparam Ur0_n_1_pp.CA = 6'd 61;
defparam Ur0_n_1_pp.CB = 6'd 62;
defparam Ur0_n_1_pp.CC = 6'd 52;
defparam Ur0_n_1_pp.CD = 6'd 53;
defparam Ur0_n_1_pp.CE = 6'd 47;
defparam Ur0_n_1_pp.CF = 6'd 48;
assign lut_val_0_n_1_pp[10] = lut_val_0_n_1_pp[5];
assign lut_val_0_n_1_pp[9] = lut_val_0_n_1_pp[5];
assign lut_val_0_n_1_pp[8] = lut_val_0_n_1_pp[5];
assign lut_val_0_n_1_pp[7] = lut_val_0_n_1_pp[5];
assign lut_val_0_n_1_pp[6] = lut_val_0_n_1_pp[5];
wire [10:0] lut_val_0_n_2_pp;
rom_lut_r_cen Ur0_n_2_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_4_n[2],sym_res_3_n[2],sym_res_2_n[2],sym_res_1_n[2] } ), .data_out( lut_val_0_n_2_pp[5:0]) ) ;
defparam Ur0_n_2_pp.DATA_WIDTH = 6;
defparam Ur0_n_2_pp.C0 = 6'd 0;
defparam Ur0_n_2_pp.C1 = 6'd 1;
defparam Ur0_n_2_pp.C2 = 6'd 59;
defparam Ur0_n_2_pp.C3 = 6'd 60;
defparam Ur0_n_2_pp.C4 = 6'd 50;
defparam Ur0_n_2_pp.C5 = 6'd 51;
defparam Ur0_n_2_pp.C6 = 6'd 45;
defparam Ur0_n_2_pp.C7 = 6'd 46;
defparam Ur0_n_2_pp.C8 = 6'd 2;
defparam Ur0_n_2_pp.C9 = 6'd 3;
defparam Ur0_n_2_pp.CA = 6'd 61;
defparam Ur0_n_2_pp.CB = 6'd 62;
defparam Ur0_n_2_pp.CC = 6'd 52;
defparam Ur0_n_2_pp.CD = 6'd 53;
defparam Ur0_n_2_pp.CE = 6'd 47;
defparam Ur0_n_2_pp.CF = 6'd 48;
assign lut_val_0_n_2_pp[10] = lut_val_0_n_2_pp[5];
assign lut_val_0_n_2_pp[9] = lut_val_0_n_2_pp[5];
assign lut_val_0_n_2_pp[8] = lut_val_0_n_2_pp[5];
assign lut_val_0_n_2_pp[7] = lut_val_0_n_2_pp[5];
assign lut_val_0_n_2_pp[6] = lut_val_0_n_2_pp[5];
wire [10:0] lut_val_0_n_3_pp;
rom_lut_r_cen Ur0_n_3_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_4_n[3],sym_res_3_n[3],sym_res_2_n[3],sym_res_1_n[3] } ), .data_out( lut_val_0_n_3_pp[5:0]) ) ;
defparam Ur0_n_3_pp.DATA_WIDTH = 6;
defparam Ur0_n_3_pp.C0 = 6'd 0;
defparam Ur0_n_3_pp.C1 = 6'd 1;
defparam Ur0_n_3_pp.C2 = 6'd 59;
defparam Ur0_n_3_pp.C3 = 6'd 60;
defparam Ur0_n_3_pp.C4 = 6'd 50;
defparam Ur0_n_3_pp.C5 = 6'd 51;
defparam Ur0_n_3_pp.C6 = 6'd 45;
defparam Ur0_n_3_pp.C7 = 6'd 46;
defparam Ur0_n_3_pp.C8 = 6'd 2;
defparam Ur0_n_3_pp.C9 = 6'd 3;
defparam Ur0_n_3_pp.CA = 6'd 61;
defparam Ur0_n_3_pp.CB = 6'd 62;
defparam Ur0_n_3_pp.CC = 6'd 52;
defparam Ur0_n_3_pp.CD = 6'd 53;
defparam Ur0_n_3_pp.CE = 6'd 47;
defparam Ur0_n_3_pp.CF = 6'd 48;
assign lut_val_0_n_3_pp[10] = lut_val_0_n_3_pp[5];
assign lut_val_0_n_3_pp[9] = lut_val_0_n_3_pp[5];
assign lut_val_0_n_3_pp[8] = lut_val_0_n_3_pp[5];
assign lut_val_0_n_3_pp[7] = lut_val_0_n_3_pp[5];
assign lut_val_0_n_3_pp[6] = lut_val_0_n_3_pp[5];
wire [10:0] lut_val_0_n_4_pp;
rom_lut_r_cen Ur0_n_4_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_4_n[4],sym_res_3_n[4],sym_res_2_n[4],sym_res_1_n[4] } ), .data_out( lut_val_0_n_4_pp[5:0]) ) ;
defparam Ur0_n_4_pp.DATA_WIDTH = 6;
defparam Ur0_n_4_pp.C0 = 6'd 0;
defparam Ur0_n_4_pp.C1 = 6'd 1;
defparam Ur0_n_4_pp.C2 = 6'd 59;
defparam Ur0_n_4_pp.C3 = 6'd 60;
defparam Ur0_n_4_pp.C4 = 6'd 50;
defparam Ur0_n_4_pp.C5 = 6'd 51;
defparam Ur0_n_4_pp.C6 = 6'd 45;
defparam Ur0_n_4_pp.C7 = 6'd 46;
defparam Ur0_n_4_pp.C8 = 6'd 2;
defparam Ur0_n_4_pp.C9 = 6'd 3;
defparam Ur0_n_4_pp.CA = 6'd 61;
defparam Ur0_n_4_pp.CB = 6'd 62;
defparam Ur0_n_4_pp.CC = 6'd 52;
defparam Ur0_n_4_pp.CD = 6'd 53;
defparam Ur0_n_4_pp.CE = 6'd 47;
defparam Ur0_n_4_pp.CF = 6'd 48;
assign lut_val_0_n_4_pp[10] = lut_val_0_n_4_pp[5];
assign lut_val_0_n_4_pp[9] = lut_val_0_n_4_pp[5];
assign lut_val_0_n_4_pp[8] = lut_val_0_n_4_pp[5];
assign lut_val_0_n_4_pp[7] = lut_val_0_n_4_pp[5];
assign lut_val_0_n_4_pp[6] = lut_val_0_n_4_pp[5];
wire [10:0] lut_val_0_n_5_pp;
rom_lut_r_cen Ur0_n_5_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_4_n[5],sym_res_3_n[5],sym_res_2_n[5],sym_res_1_n[5] } ), .data_out( lut_val_0_n_5_pp[5:0]) ) ;
defparam Ur0_n_5_pp.DATA_WIDTH = 6;
defparam Ur0_n_5_pp.C0 = 6'd 0;
defparam Ur0_n_5_pp.C1 = 6'd 1;
defparam Ur0_n_5_pp.C2 = 6'd 59;
defparam Ur0_n_5_pp.C3 = 6'd 60;
defparam Ur0_n_5_pp.C4 = 6'd 50;
defparam Ur0_n_5_pp.C5 = 6'd 51;
defparam Ur0_n_5_pp.C6 = 6'd 45;
defparam Ur0_n_5_pp.C7 = 6'd 46;
defparam Ur0_n_5_pp.C8 = 6'd 2;
defparam Ur0_n_5_pp.C9 = 6'd 3;
defparam Ur0_n_5_pp.CA = 6'd 61;
defparam Ur0_n_5_pp.CB = 6'd 62;
defparam Ur0_n_5_pp.CC = 6'd 52;
defparam Ur0_n_5_pp.CD = 6'd 53;
defparam Ur0_n_5_pp.CE = 6'd 47;
defparam Ur0_n_5_pp.CF = 6'd 48;
assign lut_val_0_n_5_pp[10] = lut_val_0_n_5_pp[5];
assign lut_val_0_n_5_pp[9] = lut_val_0_n_5_pp[5];
assign lut_val_0_n_5_pp[8] = lut_val_0_n_5_pp[5];
assign lut_val_0_n_5_pp[7] = lut_val_0_n_5_pp[5];
assign lut_val_0_n_5_pp[6] = lut_val_0_n_5_pp[5];
wire [10:0] lut_val_0_n_6_pp;
rom_lut_r_cen Ur0_n_6_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_4_n[6],sym_res_3_n[6],sym_res_2_n[6],sym_res_1_n[6] } ), .data_out( lut_val_0_n_6_pp[5:0]) ) ;
defparam Ur0_n_6_pp.DATA_WIDTH = 6;
defparam Ur0_n_6_pp.C0 = 6'd 0;
defparam Ur0_n_6_pp.C1 = 6'd 1;
defparam Ur0_n_6_pp.C2 = 6'd 59;
defparam Ur0_n_6_pp.C3 = 6'd 60;
defparam Ur0_n_6_pp.C4 = 6'd 50;
defparam Ur0_n_6_pp.C5 = 6'd 51;
defparam Ur0_n_6_pp.C6 = 6'd 45;
defparam Ur0_n_6_pp.C7 = 6'd 46;
defparam Ur0_n_6_pp.C8 = 6'd 2;
defparam Ur0_n_6_pp.C9 = 6'd 3;
defparam Ur0_n_6_pp.CA = 6'd 61;
defparam Ur0_n_6_pp.CB = 6'd 62;
defparam Ur0_n_6_pp.CC = 6'd 52;
defparam Ur0_n_6_pp.CD = 6'd 53;
defparam Ur0_n_6_pp.CE = 6'd 47;
defparam Ur0_n_6_pp.CF = 6'd 48;
assign lut_val_0_n_6_pp[10] = lut_val_0_n_6_pp[5];
assign lut_val_0_n_6_pp[9] = lut_val_0_n_6_pp[5];
assign lut_val_0_n_6_pp[8] = lut_val_0_n_6_pp[5];
assign lut_val_0_n_6_pp[7] = lut_val_0_n_6_pp[5];
assign lut_val_0_n_6_pp[6] = lut_val_0_n_6_pp[5];
wire [10:0] lut_val_0_n_7_pp;
rom_lut_r_cen Ur0_n_7_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_4_n[7],sym_res_3_n[7],sym_res_2_n[7],sym_res_1_n[7] } ), .data_out( lut_val_0_n_7_pp[5:0]) ) ;
defparam Ur0_n_7_pp.DATA_WIDTH = 6;
defparam Ur0_n_7_pp.C0 = 6'd 0;
defparam Ur0_n_7_pp.C1 = 6'd 1;
defparam Ur0_n_7_pp.C2 = 6'd 59;
defparam Ur0_n_7_pp.C3 = 6'd 60;
defparam Ur0_n_7_pp.C4 = 6'd 50;
defparam Ur0_n_7_pp.C5 = 6'd 51;
defparam Ur0_n_7_pp.C6 = 6'd 45;
defparam Ur0_n_7_pp.C7 = 6'd 46;
defparam Ur0_n_7_pp.C8 = 6'd 2;
defparam Ur0_n_7_pp.C9 = 6'd 3;
defparam Ur0_n_7_pp.CA = 6'd 61;
defparam Ur0_n_7_pp.CB = 6'd 62;
defparam Ur0_n_7_pp.CC = 6'd 52;
defparam Ur0_n_7_pp.CD = 6'd 53;
defparam Ur0_n_7_pp.CE = 6'd 47;
defparam Ur0_n_7_pp.CF = 6'd 48;
assign lut_val_0_n_7_pp[10] = lut_val_0_n_7_pp[5];
assign lut_val_0_n_7_pp[9] = lut_val_0_n_7_pp[5];
assign lut_val_0_n_7_pp[8] = lut_val_0_n_7_pp[5];
assign lut_val_0_n_7_pp[7] = lut_val_0_n_7_pp[5];
assign lut_val_0_n_7_pp[6] = lut_val_0_n_7_pp[5];
wire [10:0] lut_val_0_n_8_pp;
rom_lut_r_cen Ur0_n_8_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_4_n[8],sym_res_3_n[8],sym_res_2_n[8],sym_res_1_n[8] } ), .data_out( lut_val_0_n_8_pp[5:0]) ) ;
defparam Ur0_n_8_pp.DATA_WIDTH = 6;
defparam Ur0_n_8_pp.C0 = 6'd 0;
defparam Ur0_n_8_pp.C1 = 6'd 1;
defparam Ur0_n_8_pp.C2 = 6'd 59;
defparam Ur0_n_8_pp.C3 = 6'd 60;
defparam Ur0_n_8_pp.C4 = 6'd 50;
defparam Ur0_n_8_pp.C5 = 6'd 51;
defparam Ur0_n_8_pp.C6 = 6'd 45;
defparam Ur0_n_8_pp.C7 = 6'd 46;
defparam Ur0_n_8_pp.C8 = 6'd 2;
defparam Ur0_n_8_pp.C9 = 6'd 3;
defparam Ur0_n_8_pp.CA = 6'd 61;
defparam Ur0_n_8_pp.CB = 6'd 62;
defparam Ur0_n_8_pp.CC = 6'd 52;
defparam Ur0_n_8_pp.CD = 6'd 53;
defparam Ur0_n_8_pp.CE = 6'd 47;
defparam Ur0_n_8_pp.CF = 6'd 48;
assign lut_val_0_n_8_pp[10] = lut_val_0_n_8_pp[5];
assign lut_val_0_n_8_pp[9] = lut_val_0_n_8_pp[5];
assign lut_val_0_n_8_pp[8] = lut_val_0_n_8_pp[5];
assign lut_val_0_n_8_pp[7] = lut_val_0_n_8_pp[5];
assign lut_val_0_n_8_pp[6] = lut_val_0_n_8_pp[5];
wire [10:0] lut_val_0_n_9_pp;
rom_lut_r_cen Ur0_n_9_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_4_n[9],sym_res_3_n[9],sym_res_2_n[9],sym_res_1_n[9] } ), .data_out( lut_val_0_n_9_pp[5:0]) ) ;
defparam Ur0_n_9_pp.DATA_WIDTH = 6;
defparam Ur0_n_9_pp.C0 = 6'd 0;
defparam Ur0_n_9_pp.C1 = 6'd 1;
defparam Ur0_n_9_pp.C2 = 6'd 59;
defparam Ur0_n_9_pp.C3 = 6'd 60;
defparam Ur0_n_9_pp.C4 = 6'd 50;
defparam Ur0_n_9_pp.C5 = 6'd 51;
defparam Ur0_n_9_pp.C6 = 6'd 45;
defparam Ur0_n_9_pp.C7 = 6'd 46;
defparam Ur0_n_9_pp.C8 = 6'd 2;
defparam Ur0_n_9_pp.C9 = 6'd 3;
defparam Ur0_n_9_pp.CA = 6'd 61;
defparam Ur0_n_9_pp.CB = 6'd 62;
defparam Ur0_n_9_pp.CC = 6'd 52;
defparam Ur0_n_9_pp.CD = 6'd 53;
defparam Ur0_n_9_pp.CE = 6'd 47;
defparam Ur0_n_9_pp.CF = 6'd 48;
assign lut_val_0_n_9_pp[10] = lut_val_0_n_9_pp[5];
assign lut_val_0_n_9_pp[9] = lut_val_0_n_9_pp[5];
assign lut_val_0_n_9_pp[8] = lut_val_0_n_9_pp[5];
assign lut_val_0_n_9_pp[7] = lut_val_0_n_9_pp[5];
assign lut_val_0_n_9_pp[6] = lut_val_0_n_9_pp[5];
wire [10:0] lut_val_0_n_10_pp;
rom_lut_r_cen Ur0_n_10_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_4_n[10],sym_res_3_n[10],sym_res_2_n[10],sym_res_1_n[10] } ), .data_out( lut_val_0_n_10_pp[5:0]) ) ;
defparam Ur0_n_10_pp.DATA_WIDTH = 6;
defparam Ur0_n_10_pp.C0 = 6'd 0;
defparam Ur0_n_10_pp.C1 = 6'd 1;
defparam Ur0_n_10_pp.C2 = 6'd 59;
defparam Ur0_n_10_pp.C3 = 6'd 60;
defparam Ur0_n_10_pp.C4 = 6'd 50;
defparam Ur0_n_10_pp.C5 = 6'd 51;
defparam Ur0_n_10_pp.C6 = 6'd 45;
defparam Ur0_n_10_pp.C7 = 6'd 46;
defparam Ur0_n_10_pp.C8 = 6'd 2;
defparam Ur0_n_10_pp.C9 = 6'd 3;
defparam Ur0_n_10_pp.CA = 6'd 61;
defparam Ur0_n_10_pp.CB = 6'd 62;
defparam Ur0_n_10_pp.CC = 6'd 52;
defparam Ur0_n_10_pp.CD = 6'd 53;
defparam Ur0_n_10_pp.CE = 6'd 47;
defparam Ur0_n_10_pp.CF = 6'd 48;
assign lut_val_0_n_10_pp[10] = lut_val_0_n_10_pp[5];
assign lut_val_0_n_10_pp[9] = lut_val_0_n_10_pp[5];
assign lut_val_0_n_10_pp[8] = lut_val_0_n_10_pp[5];
assign lut_val_0_n_10_pp[7] = lut_val_0_n_10_pp[5];
assign lut_val_0_n_10_pp[6] = lut_val_0_n_10_pp[5];
wire [10:0] lut_val_0_n_11_pp;
rom_lut_r_cen Ur0_n_11_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_4_n[11],sym_res_3_n[11],sym_res_2_n[11],sym_res_1_n[11] } ), .data_out( lut_val_0_n_11_pp[5:0]) ) ;
defparam Ur0_n_11_pp.DATA_WIDTH = 6;
defparam Ur0_n_11_pp.C0 = 6'd 0;
defparam Ur0_n_11_pp.C1 = 6'd 63;
defparam Ur0_n_11_pp.C2 = 6'd 5;
defparam Ur0_n_11_pp.C3 = 6'd 4;
defparam Ur0_n_11_pp.C4 = 6'd 14;
defparam Ur0_n_11_pp.C5 = 6'd 13;
defparam Ur0_n_11_pp.C6 = 6'd 19;
defparam Ur0_n_11_pp.C7 = 6'd 18;
defparam Ur0_n_11_pp.C8 = 6'd 62;
defparam Ur0_n_11_pp.C9 = 6'd 61;
defparam Ur0_n_11_pp.CA = 6'd 3;
defparam Ur0_n_11_pp.CB = 6'd 2;
defparam Ur0_n_11_pp.CC = 6'd 12;
defparam Ur0_n_11_pp.CD = 6'd 11;
defparam Ur0_n_11_pp.CE = 6'd 17;
defparam Ur0_n_11_pp.CF = 6'd 16;
assign lut_val_0_n_11_pp[10] = lut_val_0_n_11_pp[5];
assign lut_val_0_n_11_pp[9] = lut_val_0_n_11_pp[5];
assign lut_val_0_n_11_pp[8] = lut_val_0_n_11_pp[5];
assign lut_val_0_n_11_pp[7] = lut_val_0_n_11_pp[5];
assign lut_val_0_n_11_pp[6] = lut_val_0_n_11_pp[5];
wire [10:0] lut_val_1_n_0_pp;
rom_lut_r_cen Ur1_n_0_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_9_n[0],sym_res_7_n[0],sym_res_6_n[0],sym_res_5_n[0] } ), .data_out( lut_val_1_n_0_pp[8:0]) ) ;
defparam Ur1_n_0_pp.DATA_WIDTH = 9;
defparam Ur1_n_0_pp.C0 = 9'd 0;
defparam Ur1_n_0_pp.C1 = 9'd 486;
defparam Ur1_n_0_pp.C2 = 9'd 14;
defparam Ur1_n_0_pp.C3 = 9'd 500;
defparam Ur1_n_0_pp.C4 = 9'd 70;
defparam Ur1_n_0_pp.C5 = 9'd 44;
defparam Ur1_n_0_pp.C6 = 9'd 84;
defparam Ur1_n_0_pp.C7 = 9'd 58;
defparam Ur1_n_0_pp.C8 = 9'd 127;
defparam Ur1_n_0_pp.C9 = 9'd 101;
defparam Ur1_n_0_pp.CA = 9'd 141;
defparam Ur1_n_0_pp.CB = 9'd 115;
defparam Ur1_n_0_pp.CC = 9'd 197;
defparam Ur1_n_0_pp.CD = 9'd 171;
defparam Ur1_n_0_pp.CE = 9'd 211;
defparam Ur1_n_0_pp.CF = 9'd 185;
assign lut_val_1_n_0_pp[10] = lut_val_1_n_0_pp[8];
assign lut_val_1_n_0_pp[9] = lut_val_1_n_0_pp[8];
wire [10:0] lut_val_1_n_1_pp;
rom_lut_r_cen Ur1_n_1_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_9_n[1],sym_res_7_n[1],sym_res_6_n[1],sym_res_5_n[1] } ), .data_out( lut_val_1_n_1_pp[8:0]) ) ;
defparam Ur1_n_1_pp.DATA_WIDTH = 9;
defparam Ur1_n_1_pp.C0 = 9'd 0;
defparam Ur1_n_1_pp.C1 = 9'd 486;
defparam Ur1_n_1_pp.C2 = 9'd 14;
defparam Ur1_n_1_pp.C3 = 9'd 500;
defparam Ur1_n_1_pp.C4 = 9'd 70;
defparam Ur1_n_1_pp.C5 = 9'd 44;
defparam Ur1_n_1_pp.C6 = 9'd 84;
defparam Ur1_n_1_pp.C7 = 9'd 58;
defparam Ur1_n_1_pp.C8 = 9'd 127;
defparam Ur1_n_1_pp.C9 = 9'd 101;
defparam Ur1_n_1_pp.CA = 9'd 141;
defparam Ur1_n_1_pp.CB = 9'd 115;
defparam Ur1_n_1_pp.CC = 9'd 197;
defparam Ur1_n_1_pp.CD = 9'd 171;
defparam Ur1_n_1_pp.CE = 9'd 211;
defparam Ur1_n_1_pp.CF = 9'd 185;
assign lut_val_1_n_1_pp[10] = lut_val_1_n_1_pp[8];
assign lut_val_1_n_1_pp[9] = lut_val_1_n_1_pp[8];
wire [10:0] lut_val_1_n_2_pp;
rom_lut_r_cen Ur1_n_2_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_9_n[2],sym_res_7_n[2],sym_res_6_n[2],sym_res_5_n[2] } ), .data_out( lut_val_1_n_2_pp[8:0]) ) ;
defparam Ur1_n_2_pp.DATA_WIDTH = 9;
defparam Ur1_n_2_pp.C0 = 9'd 0;
defparam Ur1_n_2_pp.C1 = 9'd 486;
defparam Ur1_n_2_pp.C2 = 9'd 14;
defparam Ur1_n_2_pp.C3 = 9'd 500;
defparam Ur1_n_2_pp.C4 = 9'd 70;
defparam Ur1_n_2_pp.C5 = 9'd 44;
defparam Ur1_n_2_pp.C6 = 9'd 84;
defparam Ur1_n_2_pp.C7 = 9'd 58;
defparam Ur1_n_2_pp.C8 = 9'd 127;
defparam Ur1_n_2_pp.C9 = 9'd 101;
defparam Ur1_n_2_pp.CA = 9'd 141;
defparam Ur1_n_2_pp.CB = 9'd 115;
defparam Ur1_n_2_pp.CC = 9'd 197;
defparam Ur1_n_2_pp.CD = 9'd 171;
defparam Ur1_n_2_pp.CE = 9'd 211;
defparam Ur1_n_2_pp.CF = 9'd 185;
assign lut_val_1_n_2_pp[10] = lut_val_1_n_2_pp[8];
assign lut_val_1_n_2_pp[9] = lut_val_1_n_2_pp[8];
wire [10:0] lut_val_1_n_3_pp;
rom_lut_r_cen Ur1_n_3_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_9_n[3],sym_res_7_n[3],sym_res_6_n[3],sym_res_5_n[3] } ), .data_out( lut_val_1_n_3_pp[8:0]) ) ;
defparam Ur1_n_3_pp.DATA_WIDTH = 9;
defparam Ur1_n_3_pp.C0 = 9'd 0;
defparam Ur1_n_3_pp.C1 = 9'd 486;
defparam Ur1_n_3_pp.C2 = 9'd 14;
defparam Ur1_n_3_pp.C3 = 9'd 500;
defparam Ur1_n_3_pp.C4 = 9'd 70;
defparam Ur1_n_3_pp.C5 = 9'd 44;
defparam Ur1_n_3_pp.C6 = 9'd 84;
defparam Ur1_n_3_pp.C7 = 9'd 58;
defparam Ur1_n_3_pp.C8 = 9'd 127;
defparam Ur1_n_3_pp.C9 = 9'd 101;
defparam Ur1_n_3_pp.CA = 9'd 141;
defparam Ur1_n_3_pp.CB = 9'd 115;
defparam Ur1_n_3_pp.CC = 9'd 197;
defparam Ur1_n_3_pp.CD = 9'd 171;
defparam Ur1_n_3_pp.CE = 9'd 211;
defparam Ur1_n_3_pp.CF = 9'd 185;
assign lut_val_1_n_3_pp[10] = lut_val_1_n_3_pp[8];
assign lut_val_1_n_3_pp[9] = lut_val_1_n_3_pp[8];
wire [10:0] lut_val_1_n_4_pp;
rom_lut_r_cen Ur1_n_4_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_9_n[4],sym_res_7_n[4],sym_res_6_n[4],sym_res_5_n[4] } ), .data_out( lut_val_1_n_4_pp[8:0]) ) ;
defparam Ur1_n_4_pp.DATA_WIDTH = 9;
defparam Ur1_n_4_pp.C0 = 9'd 0;
defparam Ur1_n_4_pp.C1 = 9'd 486;
defparam Ur1_n_4_pp.C2 = 9'd 14;
defparam Ur1_n_4_pp.C3 = 9'd 500;
defparam Ur1_n_4_pp.C4 = 9'd 70;
defparam Ur1_n_4_pp.C5 = 9'd 44;
defparam Ur1_n_4_pp.C6 = 9'd 84;
defparam Ur1_n_4_pp.C7 = 9'd 58;
defparam Ur1_n_4_pp.C8 = 9'd 127;
defparam Ur1_n_4_pp.C9 = 9'd 101;
defparam Ur1_n_4_pp.CA = 9'd 141;
defparam Ur1_n_4_pp.CB = 9'd 115;
defparam Ur1_n_4_pp.CC = 9'd 197;
defparam Ur1_n_4_pp.CD = 9'd 171;
defparam Ur1_n_4_pp.CE = 9'd 211;
defparam Ur1_n_4_pp.CF = 9'd 185;
assign lut_val_1_n_4_pp[10] = lut_val_1_n_4_pp[8];
assign lut_val_1_n_4_pp[9] = lut_val_1_n_4_pp[8];
wire [10:0] lut_val_1_n_5_pp;
rom_lut_r_cen Ur1_n_5_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_9_n[5],sym_res_7_n[5],sym_res_6_n[5],sym_res_5_n[5] } ), .data_out( lut_val_1_n_5_pp[8:0]) ) ;
defparam Ur1_n_5_pp.DATA_WIDTH = 9;
defparam Ur1_n_5_pp.C0 = 9'd 0;
defparam Ur1_n_5_pp.C1 = 9'd 486;
defparam Ur1_n_5_pp.C2 = 9'd 14;
defparam Ur1_n_5_pp.C3 = 9'd 500;
defparam Ur1_n_5_pp.C4 = 9'd 70;
defparam Ur1_n_5_pp.C5 = 9'd 44;
defparam Ur1_n_5_pp.C6 = 9'd 84;
defparam Ur1_n_5_pp.C7 = 9'd 58;
defparam Ur1_n_5_pp.C8 = 9'd 127;
defparam Ur1_n_5_pp.C9 = 9'd 101;
defparam Ur1_n_5_pp.CA = 9'd 141;
defparam Ur1_n_5_pp.CB = 9'd 115;
defparam Ur1_n_5_pp.CC = 9'd 197;
defparam Ur1_n_5_pp.CD = 9'd 171;
defparam Ur1_n_5_pp.CE = 9'd 211;
defparam Ur1_n_5_pp.CF = 9'd 185;
assign lut_val_1_n_5_pp[10] = lut_val_1_n_5_pp[8];
assign lut_val_1_n_5_pp[9] = lut_val_1_n_5_pp[8];
wire [10:0] lut_val_1_n_6_pp;
rom_lut_r_cen Ur1_n_6_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_9_n[6],sym_res_7_n[6],sym_res_6_n[6],sym_res_5_n[6] } ), .data_out( lut_val_1_n_6_pp[8:0]) ) ;
defparam Ur1_n_6_pp.DATA_WIDTH = 9;
defparam Ur1_n_6_pp.C0 = 9'd 0;
defparam Ur1_n_6_pp.C1 = 9'd 486;
defparam Ur1_n_6_pp.C2 = 9'd 14;
defparam Ur1_n_6_pp.C3 = 9'd 500;
defparam Ur1_n_6_pp.C4 = 9'd 70;
defparam Ur1_n_6_pp.C5 = 9'd 44;
defparam Ur1_n_6_pp.C6 = 9'd 84;
defparam Ur1_n_6_pp.C7 = 9'd 58;
defparam Ur1_n_6_pp.C8 = 9'd 127;
defparam Ur1_n_6_pp.C9 = 9'd 101;
defparam Ur1_n_6_pp.CA = 9'd 141;
defparam Ur1_n_6_pp.CB = 9'd 115;
defparam Ur1_n_6_pp.CC = 9'd 197;
defparam Ur1_n_6_pp.CD = 9'd 171;
defparam Ur1_n_6_pp.CE = 9'd 211;
defparam Ur1_n_6_pp.CF = 9'd 185;
assign lut_val_1_n_6_pp[10] = lut_val_1_n_6_pp[8];
assign lut_val_1_n_6_pp[9] = lut_val_1_n_6_pp[8];
wire [10:0] lut_val_1_n_7_pp;
rom_lut_r_cen Ur1_n_7_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_9_n[7],sym_res_7_n[7],sym_res_6_n[7],sym_res_5_n[7] } ), .data_out( lut_val_1_n_7_pp[8:0]) ) ;
defparam Ur1_n_7_pp.DATA_WIDTH = 9;
defparam Ur1_n_7_pp.C0 = 9'd 0;
defparam Ur1_n_7_pp.C1 = 9'd 486;
defparam Ur1_n_7_pp.C2 = 9'd 14;
defparam Ur1_n_7_pp.C3 = 9'd 500;
defparam Ur1_n_7_pp.C4 = 9'd 70;
defparam Ur1_n_7_pp.C5 = 9'd 44;
defparam Ur1_n_7_pp.C6 = 9'd 84;
defparam Ur1_n_7_pp.C7 = 9'd 58;
defparam Ur1_n_7_pp.C8 = 9'd 127;
defparam Ur1_n_7_pp.C9 = 9'd 101;
defparam Ur1_n_7_pp.CA = 9'd 141;
defparam Ur1_n_7_pp.CB = 9'd 115;
defparam Ur1_n_7_pp.CC = 9'd 197;
defparam Ur1_n_7_pp.CD = 9'd 171;
defparam Ur1_n_7_pp.CE = 9'd 211;
defparam Ur1_n_7_pp.CF = 9'd 185;
assign lut_val_1_n_7_pp[10] = lut_val_1_n_7_pp[8];
assign lut_val_1_n_7_pp[9] = lut_val_1_n_7_pp[8];
wire [10:0] lut_val_1_n_8_pp;
rom_lut_r_cen Ur1_n_8_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_9_n[8],sym_res_7_n[8],sym_res_6_n[8],sym_res_5_n[8] } ), .data_out( lut_val_1_n_8_pp[8:0]) ) ;
defparam Ur1_n_8_pp.DATA_WIDTH = 9;
defparam Ur1_n_8_pp.C0 = 9'd 0;
defparam Ur1_n_8_pp.C1 = 9'd 486;
defparam Ur1_n_8_pp.C2 = 9'd 14;
defparam Ur1_n_8_pp.C3 = 9'd 500;
defparam Ur1_n_8_pp.C4 = 9'd 70;
defparam Ur1_n_8_pp.C5 = 9'd 44;
defparam Ur1_n_8_pp.C6 = 9'd 84;
defparam Ur1_n_8_pp.C7 = 9'd 58;
defparam Ur1_n_8_pp.C8 = 9'd 127;
defparam Ur1_n_8_pp.C9 = 9'd 101;
defparam Ur1_n_8_pp.CA = 9'd 141;
defparam Ur1_n_8_pp.CB = 9'd 115;
defparam Ur1_n_8_pp.CC = 9'd 197;
defparam Ur1_n_8_pp.CD = 9'd 171;
defparam Ur1_n_8_pp.CE = 9'd 211;
defparam Ur1_n_8_pp.CF = 9'd 185;
assign lut_val_1_n_8_pp[10] = lut_val_1_n_8_pp[8];
assign lut_val_1_n_8_pp[9] = lut_val_1_n_8_pp[8];
wire [10:0] lut_val_1_n_9_pp;
rom_lut_r_cen Ur1_n_9_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_9_n[9],sym_res_7_n[9],sym_res_6_n[9],sym_res_5_n[9] } ), .data_out( lut_val_1_n_9_pp[8:0]) ) ;
defparam Ur1_n_9_pp.DATA_WIDTH = 9;
defparam Ur1_n_9_pp.C0 = 9'd 0;
defparam Ur1_n_9_pp.C1 = 9'd 486;
defparam Ur1_n_9_pp.C2 = 9'd 14;
defparam Ur1_n_9_pp.C3 = 9'd 500;
defparam Ur1_n_9_pp.C4 = 9'd 70;
defparam Ur1_n_9_pp.C5 = 9'd 44;
defparam Ur1_n_9_pp.C6 = 9'd 84;
defparam Ur1_n_9_pp.C7 = 9'd 58;
defparam Ur1_n_9_pp.C8 = 9'd 127;
defparam Ur1_n_9_pp.C9 = 9'd 101;
defparam Ur1_n_9_pp.CA = 9'd 141;
defparam Ur1_n_9_pp.CB = 9'd 115;
defparam Ur1_n_9_pp.CC = 9'd 197;
defparam Ur1_n_9_pp.CD = 9'd 171;
defparam Ur1_n_9_pp.CE = 9'd 211;
defparam Ur1_n_9_pp.CF = 9'd 185;
assign lut_val_1_n_9_pp[10] = lut_val_1_n_9_pp[8];
assign lut_val_1_n_9_pp[9] = lut_val_1_n_9_pp[8];
wire [10:0] lut_val_1_n_10_pp;
rom_lut_r_cen Ur1_n_10_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_9_n[10],sym_res_7_n[10],sym_res_6_n[10],sym_res_5_n[10] } ), .data_out( lut_val_1_n_10_pp[8:0]) ) ;
defparam Ur1_n_10_pp.DATA_WIDTH = 9;
defparam Ur1_n_10_pp.C0 = 9'd 0;
defparam Ur1_n_10_pp.C1 = 9'd 486;
defparam Ur1_n_10_pp.C2 = 9'd 14;
defparam Ur1_n_10_pp.C3 = 9'd 500;
defparam Ur1_n_10_pp.C4 = 9'd 70;
defparam Ur1_n_10_pp.C5 = 9'd 44;
defparam Ur1_n_10_pp.C6 = 9'd 84;
defparam Ur1_n_10_pp.C7 = 9'd 58;
defparam Ur1_n_10_pp.C8 = 9'd 127;
defparam Ur1_n_10_pp.C9 = 9'd 101;
defparam Ur1_n_10_pp.CA = 9'd 141;
defparam Ur1_n_10_pp.CB = 9'd 115;
defparam Ur1_n_10_pp.CC = 9'd 197;
defparam Ur1_n_10_pp.CD = 9'd 171;
defparam Ur1_n_10_pp.CE = 9'd 211;
defparam Ur1_n_10_pp.CF = 9'd 185;
assign lut_val_1_n_10_pp[10] = lut_val_1_n_10_pp[8];
assign lut_val_1_n_10_pp[9] = lut_val_1_n_10_pp[8];
wire [10:0] lut_val_1_n_11_pp;
rom_lut_r_cen Ur1_n_11_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_9_n[11],sym_res_7_n[11],sym_res_6_n[11],sym_res_5_n[11] } ), .data_out( lut_val_1_n_11_pp[8:0]) ) ;
defparam Ur1_n_11_pp.DATA_WIDTH = 9;
defparam Ur1_n_11_pp.C0 = 9'd 0;
defparam Ur1_n_11_pp.C1 = 9'd 26;
defparam Ur1_n_11_pp.C2 = 9'd 498;
defparam Ur1_n_11_pp.C3 = 9'd 12;
defparam Ur1_n_11_pp.C4 = 9'd 442;
defparam Ur1_n_11_pp.C5 = 9'd 468;
defparam Ur1_n_11_pp.C6 = 9'd 428;
defparam Ur1_n_11_pp.C7 = 9'd 454;
defparam Ur1_n_11_pp.C8 = 9'd 385;
defparam Ur1_n_11_pp.C9 = 9'd 411;
defparam Ur1_n_11_pp.CA = 9'd 371;
defparam Ur1_n_11_pp.CB = 9'd 397;
defparam Ur1_n_11_pp.CC = 9'd 315;
defparam Ur1_n_11_pp.CD = 9'd 341;
defparam Ur1_n_11_pp.CE = 9'd 301;
defparam Ur1_n_11_pp.CF = 9'd 327;
assign lut_val_1_n_11_pp[10] = lut_val_1_n_11_pp[8];
assign lut_val_1_n_11_pp[9] = lut_val_1_n_11_pp[8];
wire [10:0] lut_val_2_n_0_pp;
rom_lut_r_cen Ur2_n_0_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_13_n[0],sym_res_12_n[0],sym_res_11_n[0],sym_res_10_n[0] } ), .data_out( lut_val_2_n_0_pp[10:0]) ) ;
defparam Ur2_n_0_pp.DATA_WIDTH = 11;
defparam Ur2_n_0_pp.C0 = 11'd 0;
defparam Ur2_n_0_pp.C1 = 11'd 47;
defparam Ur2_n_0_pp.C2 = 11'd 1874;
defparam Ur2_n_0_pp.C3 = 11'd 1921;
defparam Ur2_n_0_pp.C4 = 11'd 36;
defparam Ur2_n_0_pp.C5 = 11'd 83;
defparam Ur2_n_0_pp.C6 = 11'd 1910;
defparam Ur2_n_0_pp.C7 = 11'd 1957;
defparam Ur2_n_0_pp.C8 = 11'd 1568;
defparam Ur2_n_0_pp.C9 = 11'd 1615;
defparam Ur2_n_0_pp.CA = 11'd 1394;
defparam Ur2_n_0_pp.CB = 11'd 1441;
defparam Ur2_n_0_pp.CC = 11'd 1604;
defparam Ur2_n_0_pp.CD = 11'd 1651;
defparam Ur2_n_0_pp.CE = 11'd 1430;
defparam Ur2_n_0_pp.CF = 11'd 1477;
wire [10:0] lut_val_2_n_1_pp;
rom_lut_r_cen Ur2_n_1_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_13_n[1],sym_res_12_n[1],sym_res_11_n[1],sym_res_10_n[1] } ), .data_out( lut_val_2_n_1_pp[10:0]) ) ;
defparam Ur2_n_1_pp.DATA_WIDTH = 11;
defparam Ur2_n_1_pp.C0 = 11'd 0;
defparam Ur2_n_1_pp.C1 = 11'd 47;
defparam Ur2_n_1_pp.C2 = 11'd 1874;
defparam Ur2_n_1_pp.C3 = 11'd 1921;
defparam Ur2_n_1_pp.C4 = 11'd 36;
defparam Ur2_n_1_pp.C5 = 11'd 83;
defparam Ur2_n_1_pp.C6 = 11'd 1910;
defparam Ur2_n_1_pp.C7 = 11'd 1957;
defparam Ur2_n_1_pp.C8 = 11'd 1568;
defparam Ur2_n_1_pp.C9 = 11'd 1615;
defparam Ur2_n_1_pp.CA = 11'd 1394;
defparam Ur2_n_1_pp.CB = 11'd 1441;
defparam Ur2_n_1_pp.CC = 11'd 1604;
defparam Ur2_n_1_pp.CD = 11'd 1651;
defparam Ur2_n_1_pp.CE = 11'd 1430;
defparam Ur2_n_1_pp.CF = 11'd 1477;
wire [10:0] lut_val_2_n_2_pp;
rom_lut_r_cen Ur2_n_2_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_13_n[2],sym_res_12_n[2],sym_res_11_n[2],sym_res_10_n[2] } ), .data_out( lut_val_2_n_2_pp[10:0]) ) ;
defparam Ur2_n_2_pp.DATA_WIDTH = 11;
defparam Ur2_n_2_pp.C0 = 11'd 0;
defparam Ur2_n_2_pp.C1 = 11'd 47;
defparam Ur2_n_2_pp.C2 = 11'd 1874;
defparam Ur2_n_2_pp.C3 = 11'd 1921;
defparam Ur2_n_2_pp.C4 = 11'd 36;
defparam Ur2_n_2_pp.C5 = 11'd 83;
defparam Ur2_n_2_pp.C6 = 11'd 1910;
defparam Ur2_n_2_pp.C7 = 11'd 1957;
defparam Ur2_n_2_pp.C8 = 11'd 1568;
defparam Ur2_n_2_pp.C9 = 11'd 1615;
defparam Ur2_n_2_pp.CA = 11'd 1394;
defparam Ur2_n_2_pp.CB = 11'd 1441;
defparam Ur2_n_2_pp.CC = 11'd 1604;
defparam Ur2_n_2_pp.CD = 11'd 1651;
defparam Ur2_n_2_pp.CE = 11'd 1430;
defparam Ur2_n_2_pp.CF = 11'd 1477;
wire [10:0] lut_val_2_n_3_pp;
rom_lut_r_cen Ur2_n_3_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_13_n[3],sym_res_12_n[3],sym_res_11_n[3],sym_res_10_n[3] } ), .data_out( lut_val_2_n_3_pp[10:0]) ) ;
defparam Ur2_n_3_pp.DATA_WIDTH = 11;
defparam Ur2_n_3_pp.C0 = 11'd 0;
defparam Ur2_n_3_pp.C1 = 11'd 47;
defparam Ur2_n_3_pp.C2 = 11'd 1874;
defparam Ur2_n_3_pp.C3 = 11'd 1921;
defparam Ur2_n_3_pp.C4 = 11'd 36;
defparam Ur2_n_3_pp.C5 = 11'd 83;
defparam Ur2_n_3_pp.C6 = 11'd 1910;
defparam Ur2_n_3_pp.C7 = 11'd 1957;
defparam Ur2_n_3_pp.C8 = 11'd 1568;
defparam Ur2_n_3_pp.C9 = 11'd 1615;
defparam Ur2_n_3_pp.CA = 11'd 1394;
defparam Ur2_n_3_pp.CB = 11'd 1441;
defparam Ur2_n_3_pp.CC = 11'd 1604;
defparam Ur2_n_3_pp.CD = 11'd 1651;
defparam Ur2_n_3_pp.CE = 11'd 1430;
defparam Ur2_n_3_pp.CF = 11'd 1477;
wire [10:0] lut_val_2_n_4_pp;
rom_lut_r_cen Ur2_n_4_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_13_n[4],sym_res_12_n[4],sym_res_11_n[4],sym_res_10_n[4] } ), .data_out( lut_val_2_n_4_pp[10:0]) ) ;
defparam Ur2_n_4_pp.DATA_WIDTH = 11;
defparam Ur2_n_4_pp.C0 = 11'd 0;
defparam Ur2_n_4_pp.C1 = 11'd 47;
defparam Ur2_n_4_pp.C2 = 11'd 1874;
defparam Ur2_n_4_pp.C3 = 11'd 1921;
defparam Ur2_n_4_pp.C4 = 11'd 36;
defparam Ur2_n_4_pp.C5 = 11'd 83;
defparam Ur2_n_4_pp.C6 = 11'd 1910;
defparam Ur2_n_4_pp.C7 = 11'd 1957;
defparam Ur2_n_4_pp.C8 = 11'd 1568;
defparam Ur2_n_4_pp.C9 = 11'd 1615;
defparam Ur2_n_4_pp.CA = 11'd 1394;
defparam Ur2_n_4_pp.CB = 11'd 1441;
defparam Ur2_n_4_pp.CC = 11'd 1604;
defparam Ur2_n_4_pp.CD = 11'd 1651;
defparam Ur2_n_4_pp.CE = 11'd 1430;
defparam Ur2_n_4_pp.CF = 11'd 1477;
wire [10:0] lut_val_2_n_5_pp;
rom_lut_r_cen Ur2_n_5_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_13_n[5],sym_res_12_n[5],sym_res_11_n[5],sym_res_10_n[5] } ), .data_out( lut_val_2_n_5_pp[10:0]) ) ;
defparam Ur2_n_5_pp.DATA_WIDTH = 11;
defparam Ur2_n_5_pp.C0 = 11'd 0;
defparam Ur2_n_5_pp.C1 = 11'd 47;
defparam Ur2_n_5_pp.C2 = 11'd 1874;
defparam Ur2_n_5_pp.C3 = 11'd 1921;
defparam Ur2_n_5_pp.C4 = 11'd 36;
defparam Ur2_n_5_pp.C5 = 11'd 83;
defparam Ur2_n_5_pp.C6 = 11'd 1910;
defparam Ur2_n_5_pp.C7 = 11'd 1957;
defparam Ur2_n_5_pp.C8 = 11'd 1568;
defparam Ur2_n_5_pp.C9 = 11'd 1615;
defparam Ur2_n_5_pp.CA = 11'd 1394;
defparam Ur2_n_5_pp.CB = 11'd 1441;
defparam Ur2_n_5_pp.CC = 11'd 1604;
defparam Ur2_n_5_pp.CD = 11'd 1651;
defparam Ur2_n_5_pp.CE = 11'd 1430;
defparam Ur2_n_5_pp.CF = 11'd 1477;
wire [10:0] lut_val_2_n_6_pp;
rom_lut_r_cen Ur2_n_6_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_13_n[6],sym_res_12_n[6],sym_res_11_n[6],sym_res_10_n[6] } ), .data_out( lut_val_2_n_6_pp[10:0]) ) ;
defparam Ur2_n_6_pp.DATA_WIDTH = 11;
defparam Ur2_n_6_pp.C0 = 11'd 0;
defparam Ur2_n_6_pp.C1 = 11'd 47;
defparam Ur2_n_6_pp.C2 = 11'd 1874;
defparam Ur2_n_6_pp.C3 = 11'd 1921;
defparam Ur2_n_6_pp.C4 = 11'd 36;
defparam Ur2_n_6_pp.C5 = 11'd 83;
defparam Ur2_n_6_pp.C6 = 11'd 1910;
defparam Ur2_n_6_pp.C7 = 11'd 1957;
defparam Ur2_n_6_pp.C8 = 11'd 1568;
defparam Ur2_n_6_pp.C9 = 11'd 1615;
defparam Ur2_n_6_pp.CA = 11'd 1394;
defparam Ur2_n_6_pp.CB = 11'd 1441;
defparam Ur2_n_6_pp.CC = 11'd 1604;
defparam Ur2_n_6_pp.CD = 11'd 1651;
defparam Ur2_n_6_pp.CE = 11'd 1430;
defparam Ur2_n_6_pp.CF = 11'd 1477;
wire [10:0] lut_val_2_n_7_pp;
rom_lut_r_cen Ur2_n_7_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_13_n[7],sym_res_12_n[7],sym_res_11_n[7],sym_res_10_n[7] } ), .data_out( lut_val_2_n_7_pp[10:0]) ) ;
defparam Ur2_n_7_pp.DATA_WIDTH = 11;
defparam Ur2_n_7_pp.C0 = 11'd 0;
defparam Ur2_n_7_pp.C1 = 11'd 47;
defparam Ur2_n_7_pp.C2 = 11'd 1874;
defparam Ur2_n_7_pp.C3 = 11'd 1921;
defparam Ur2_n_7_pp.C4 = 11'd 36;
defparam Ur2_n_7_pp.C5 = 11'd 83;
defparam Ur2_n_7_pp.C6 = 11'd 1910;
defparam Ur2_n_7_pp.C7 = 11'd 1957;
defparam Ur2_n_7_pp.C8 = 11'd 1568;
defparam Ur2_n_7_pp.C9 = 11'd 1615;
defparam Ur2_n_7_pp.CA = 11'd 1394;
defparam Ur2_n_7_pp.CB = 11'd 1441;
defparam Ur2_n_7_pp.CC = 11'd 1604;
defparam Ur2_n_7_pp.CD = 11'd 1651;
defparam Ur2_n_7_pp.CE = 11'd 1430;
defparam Ur2_n_7_pp.CF = 11'd 1477;
wire [10:0] lut_val_2_n_8_pp;
rom_lut_r_cen Ur2_n_8_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_13_n[8],sym_res_12_n[8],sym_res_11_n[8],sym_res_10_n[8] } ), .data_out( lut_val_2_n_8_pp[10:0]) ) ;
defparam Ur2_n_8_pp.DATA_WIDTH = 11;
defparam Ur2_n_8_pp.C0 = 11'd 0;
defparam Ur2_n_8_pp.C1 = 11'd 47;
defparam Ur2_n_8_pp.C2 = 11'd 1874;
defparam Ur2_n_8_pp.C3 = 11'd 1921;
defparam Ur2_n_8_pp.C4 = 11'd 36;
defparam Ur2_n_8_pp.C5 = 11'd 83;
defparam Ur2_n_8_pp.C6 = 11'd 1910;
defparam Ur2_n_8_pp.C7 = 11'd 1957;
defparam Ur2_n_8_pp.C8 = 11'd 1568;
defparam Ur2_n_8_pp.C9 = 11'd 1615;
defparam Ur2_n_8_pp.CA = 11'd 1394;
defparam Ur2_n_8_pp.CB = 11'd 1441;
defparam Ur2_n_8_pp.CC = 11'd 1604;
defparam Ur2_n_8_pp.CD = 11'd 1651;
defparam Ur2_n_8_pp.CE = 11'd 1430;
defparam Ur2_n_8_pp.CF = 11'd 1477;
wire [10:0] lut_val_2_n_9_pp;
rom_lut_r_cen Ur2_n_9_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_13_n[9],sym_res_12_n[9],sym_res_11_n[9],sym_res_10_n[9] } ), .data_out( lut_val_2_n_9_pp[10:0]) ) ;
defparam Ur2_n_9_pp.DATA_WIDTH = 11;
defparam Ur2_n_9_pp.C0 = 11'd 0;
defparam Ur2_n_9_pp.C1 = 11'd 47;
defparam Ur2_n_9_pp.C2 = 11'd 1874;
defparam Ur2_n_9_pp.C3 = 11'd 1921;
defparam Ur2_n_9_pp.C4 = 11'd 36;
defparam Ur2_n_9_pp.C5 = 11'd 83;
defparam Ur2_n_9_pp.C6 = 11'd 1910;
defparam Ur2_n_9_pp.C7 = 11'd 1957;
defparam Ur2_n_9_pp.C8 = 11'd 1568;
defparam Ur2_n_9_pp.C9 = 11'd 1615;
defparam Ur2_n_9_pp.CA = 11'd 1394;
defparam Ur2_n_9_pp.CB = 11'd 1441;
defparam Ur2_n_9_pp.CC = 11'd 1604;
defparam Ur2_n_9_pp.CD = 11'd 1651;
defparam Ur2_n_9_pp.CE = 11'd 1430;
defparam Ur2_n_9_pp.CF = 11'd 1477;
wire [10:0] lut_val_2_n_10_pp;
rom_lut_r_cen Ur2_n_10_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_13_n[10],sym_res_12_n[10],sym_res_11_n[10],sym_res_10_n[10] } ), .data_out( lut_val_2_n_10_pp[10:0]) ) ;
defparam Ur2_n_10_pp.DATA_WIDTH = 11;
defparam Ur2_n_10_pp.C0 = 11'd 0;
defparam Ur2_n_10_pp.C1 = 11'd 47;
defparam Ur2_n_10_pp.C2 = 11'd 1874;
defparam Ur2_n_10_pp.C3 = 11'd 1921;
defparam Ur2_n_10_pp.C4 = 11'd 36;
defparam Ur2_n_10_pp.C5 = 11'd 83;
defparam Ur2_n_10_pp.C6 = 11'd 1910;
defparam Ur2_n_10_pp.C7 = 11'd 1957;
defparam Ur2_n_10_pp.C8 = 11'd 1568;
defparam Ur2_n_10_pp.C9 = 11'd 1615;
defparam Ur2_n_10_pp.CA = 11'd 1394;
defparam Ur2_n_10_pp.CB = 11'd 1441;
defparam Ur2_n_10_pp.CC = 11'd 1604;
defparam Ur2_n_10_pp.CD = 11'd 1651;
defparam Ur2_n_10_pp.CE = 11'd 1430;
defparam Ur2_n_10_pp.CF = 11'd 1477;
wire [10:0] lut_val_2_n_11_pp;
rom_lut_r_cen Ur2_n_11_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_13_n[11],sym_res_12_n[11],sym_res_11_n[11],sym_res_10_n[11] } ), .data_out( lut_val_2_n_11_pp[10:0]) ) ;
defparam Ur2_n_11_pp.DATA_WIDTH = 11;
defparam Ur2_n_11_pp.C0 = 11'd 0;
defparam Ur2_n_11_pp.C1 = 11'd 2001;
defparam Ur2_n_11_pp.C2 = 11'd 174;
defparam Ur2_n_11_pp.C3 = 11'd 127;
defparam Ur2_n_11_pp.C4 = 11'd 2012;
defparam Ur2_n_11_pp.C5 = 11'd 1965;
defparam Ur2_n_11_pp.C6 = 11'd 138;
defparam Ur2_n_11_pp.C7 = 11'd 91;
defparam Ur2_n_11_pp.C8 = 11'd 480;
defparam Ur2_n_11_pp.C9 = 11'd 433;
defparam Ur2_n_11_pp.CA = 11'd 654;
defparam Ur2_n_11_pp.CB = 11'd 607;
defparam Ur2_n_11_pp.CC = 11'd 444;
defparam Ur2_n_11_pp.CD = 11'd 397;
defparam Ur2_n_11_pp.CE = 11'd 618;
defparam Ur2_n_11_pp.CF = 11'd 571;
wire [10:0] lut_val_3_n_0_pp;
rom_lut_r_cen Ur3_n_0_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {addr_low,addr_low,sym_res_15_n[0],sym_res_14_n[0] } ), .data_out( lut_val_3_n_0_pp[10:0]) ) ;
defparam Ur3_n_0_pp.DATA_WIDTH = 11;
defparam Ur3_n_0_pp.C0 = 11'd 0;
defparam Ur3_n_0_pp.C1 = 11'd 1429;
defparam Ur3_n_0_pp.C2 = 11'd 1023;
defparam Ur3_n_0_pp.C3 = 11'd 404;
defparam Ur3_n_0_pp.C4 = 11'd 0;
defparam Ur3_n_0_pp.C5 = 11'd 1429;
defparam Ur3_n_0_pp.C6 = 11'd 1023;
defparam Ur3_n_0_pp.C7 = 11'd 404;
defparam Ur3_n_0_pp.C8 = 11'd 0;
defparam Ur3_n_0_pp.C9 = 11'd 1429;
defparam Ur3_n_0_pp.CA = 11'd 1023;
defparam Ur3_n_0_pp.CB = 11'd 404;
defparam Ur3_n_0_pp.CC = 11'd 0;
defparam Ur3_n_0_pp.CD = 11'd 1429;
defparam Ur3_n_0_pp.CE = 11'd 1023;
defparam Ur3_n_0_pp.CF = 11'd 404;
wire [10:0] lut_val_3_n_1_pp;
rom_lut_r_cen Ur3_n_1_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {addr_low,addr_low,sym_res_15_n[1],sym_res_14_n[1] } ), .data_out( lut_val_3_n_1_pp[10:0]) ) ;
defparam Ur3_n_1_pp.DATA_WIDTH = 11;
defparam Ur3_n_1_pp.C0 = 11'd 0;
defparam Ur3_n_1_pp.C1 = 11'd 1429;
defparam Ur3_n_1_pp.C2 = 11'd 1023;
defparam Ur3_n_1_pp.C3 = 11'd 404;
defparam Ur3_n_1_pp.C4 = 11'd 0;
defparam Ur3_n_1_pp.C5 = 11'd 1429;
defparam Ur3_n_1_pp.C6 = 11'd 1023;
defparam Ur3_n_1_pp.C7 = 11'd 404;
defparam Ur3_n_1_pp.C8 = 11'd 0;
defparam Ur3_n_1_pp.C9 = 11'd 1429;
defparam Ur3_n_1_pp.CA = 11'd 1023;
defparam Ur3_n_1_pp.CB = 11'd 404;
defparam Ur3_n_1_pp.CC = 11'd 0;
defparam Ur3_n_1_pp.CD = 11'd 1429;
defparam Ur3_n_1_pp.CE = 11'd 1023;
defparam Ur3_n_1_pp.CF = 11'd 404;
wire [10:0] lut_val_3_n_2_pp;
rom_lut_r_cen Ur3_n_2_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {addr_low,addr_low,sym_res_15_n[2],sym_res_14_n[2] } ), .data_out( lut_val_3_n_2_pp[10:0]) ) ;
defparam Ur3_n_2_pp.DATA_WIDTH = 11;
defparam Ur3_n_2_pp.C0 = 11'd 0;
defparam Ur3_n_2_pp.C1 = 11'd 1429;
defparam Ur3_n_2_pp.C2 = 11'd 1023;
defparam Ur3_n_2_pp.C3 = 11'd 404;
defparam Ur3_n_2_pp.C4 = 11'd 0;
defparam Ur3_n_2_pp.C5 = 11'd 1429;
defparam Ur3_n_2_pp.C6 = 11'd 1023;
defparam Ur3_n_2_pp.C7 = 11'd 404;
defparam Ur3_n_2_pp.C8 = 11'd 0;
defparam Ur3_n_2_pp.C9 = 11'd 1429;
defparam Ur3_n_2_pp.CA = 11'd 1023;
defparam Ur3_n_2_pp.CB = 11'd 404;
defparam Ur3_n_2_pp.CC = 11'd 0;
defparam Ur3_n_2_pp.CD = 11'd 1429;
defparam Ur3_n_2_pp.CE = 11'd 1023;
defparam Ur3_n_2_pp.CF = 11'd 404;
wire [10:0] lut_val_3_n_3_pp;
rom_lut_r_cen Ur3_n_3_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {addr_low,addr_low,sym_res_15_n[3],sym_res_14_n[3] } ), .data_out( lut_val_3_n_3_pp[10:0]) ) ;
defparam Ur3_n_3_pp.DATA_WIDTH = 11;
defparam Ur3_n_3_pp.C0 = 11'd 0;
defparam Ur3_n_3_pp.C1 = 11'd 1429;
defparam Ur3_n_3_pp.C2 = 11'd 1023;
defparam Ur3_n_3_pp.C3 = 11'd 404;
defparam Ur3_n_3_pp.C4 = 11'd 0;
defparam Ur3_n_3_pp.C5 = 11'd 1429;
defparam Ur3_n_3_pp.C6 = 11'd 1023;
defparam Ur3_n_3_pp.C7 = 11'd 404;
defparam Ur3_n_3_pp.C8 = 11'd 0;
defparam Ur3_n_3_pp.C9 = 11'd 1429;
defparam Ur3_n_3_pp.CA = 11'd 1023;
defparam Ur3_n_3_pp.CB = 11'd 404;
defparam Ur3_n_3_pp.CC = 11'd 0;
defparam Ur3_n_3_pp.CD = 11'd 1429;
defparam Ur3_n_3_pp.CE = 11'd 1023;
defparam Ur3_n_3_pp.CF = 11'd 404;
wire [10:0] lut_val_3_n_4_pp;
rom_lut_r_cen Ur3_n_4_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {addr_low,addr_low,sym_res_15_n[4],sym_res_14_n[4] } ), .data_out( lut_val_3_n_4_pp[10:0]) ) ;
defparam Ur3_n_4_pp.DATA_WIDTH = 11;
defparam Ur3_n_4_pp.C0 = 11'd 0;
defparam Ur3_n_4_pp.C1 = 11'd 1429;
defparam Ur3_n_4_pp.C2 = 11'd 1023;
defparam Ur3_n_4_pp.C3 = 11'd 404;
defparam Ur3_n_4_pp.C4 = 11'd 0;
defparam Ur3_n_4_pp.C5 = 11'd 1429;
defparam Ur3_n_4_pp.C6 = 11'd 1023;
defparam Ur3_n_4_pp.C7 = 11'd 404;
defparam Ur3_n_4_pp.C8 = 11'd 0;
defparam Ur3_n_4_pp.C9 = 11'd 1429;
defparam Ur3_n_4_pp.CA = 11'd 1023;
defparam Ur3_n_4_pp.CB = 11'd 404;
defparam Ur3_n_4_pp.CC = 11'd 0;
defparam Ur3_n_4_pp.CD = 11'd 1429;
defparam Ur3_n_4_pp.CE = 11'd 1023;
defparam Ur3_n_4_pp.CF = 11'd 404;
wire [10:0] lut_val_3_n_5_pp;
rom_lut_r_cen Ur3_n_5_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {addr_low,addr_low,sym_res_15_n[5],sym_res_14_n[5] } ), .data_out( lut_val_3_n_5_pp[10:0]) ) ;
defparam Ur3_n_5_pp.DATA_WIDTH = 11;
defparam Ur3_n_5_pp.C0 = 11'd 0;
defparam Ur3_n_5_pp.C1 = 11'd 1429;
defparam Ur3_n_5_pp.C2 = 11'd 1023;
defparam Ur3_n_5_pp.C3 = 11'd 404;
defparam Ur3_n_5_pp.C4 = 11'd 0;
defparam Ur3_n_5_pp.C5 = 11'd 1429;
defparam Ur3_n_5_pp.C6 = 11'd 1023;
defparam Ur3_n_5_pp.C7 = 11'd 404;
defparam Ur3_n_5_pp.C8 = 11'd 0;
defparam Ur3_n_5_pp.C9 = 11'd 1429;
defparam Ur3_n_5_pp.CA = 11'd 1023;
defparam Ur3_n_5_pp.CB = 11'd 404;
defparam Ur3_n_5_pp.CC = 11'd 0;
defparam Ur3_n_5_pp.CD = 11'd 1429;
defparam Ur3_n_5_pp.CE = 11'd 1023;
defparam Ur3_n_5_pp.CF = 11'd 404;
wire [10:0] lut_val_3_n_6_pp;
rom_lut_r_cen Ur3_n_6_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {addr_low,addr_low,sym_res_15_n[6],sym_res_14_n[6] } ), .data_out( lut_val_3_n_6_pp[10:0]) ) ;
defparam Ur3_n_6_pp.DATA_WIDTH = 11;
defparam Ur3_n_6_pp.C0 = 11'd 0;
defparam Ur3_n_6_pp.C1 = 11'd 1429;
defparam Ur3_n_6_pp.C2 = 11'd 1023;
defparam Ur3_n_6_pp.C3 = 11'd 404;
defparam Ur3_n_6_pp.C4 = 11'd 0;
defparam Ur3_n_6_pp.C5 = 11'd 1429;
defparam Ur3_n_6_pp.C6 = 11'd 1023;
defparam Ur3_n_6_pp.C7 = 11'd 404;
defparam Ur3_n_6_pp.C8 = 11'd 0;
defparam Ur3_n_6_pp.C9 = 11'd 1429;
defparam Ur3_n_6_pp.CA = 11'd 1023;
defparam Ur3_n_6_pp.CB = 11'd 404;
defparam Ur3_n_6_pp.CC = 11'd 0;
defparam Ur3_n_6_pp.CD = 11'd 1429;
defparam Ur3_n_6_pp.CE = 11'd 1023;
defparam Ur3_n_6_pp.CF = 11'd 404;
wire [10:0] lut_val_3_n_7_pp;
rom_lut_r_cen Ur3_n_7_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {addr_low,addr_low,sym_res_15_n[7],sym_res_14_n[7] } ), .data_out( lut_val_3_n_7_pp[10:0]) ) ;
defparam Ur3_n_7_pp.DATA_WIDTH = 11;
defparam Ur3_n_7_pp.C0 = 11'd 0;
defparam Ur3_n_7_pp.C1 = 11'd 1429;
defparam Ur3_n_7_pp.C2 = 11'd 1023;
defparam Ur3_n_7_pp.C3 = 11'd 404;
defparam Ur3_n_7_pp.C4 = 11'd 0;
defparam Ur3_n_7_pp.C5 = 11'd 1429;
defparam Ur3_n_7_pp.C6 = 11'd 1023;
defparam Ur3_n_7_pp.C7 = 11'd 404;
defparam Ur3_n_7_pp.C8 = 11'd 0;
defparam Ur3_n_7_pp.C9 = 11'd 1429;
defparam Ur3_n_7_pp.CA = 11'd 1023;
defparam Ur3_n_7_pp.CB = 11'd 404;
defparam Ur3_n_7_pp.CC = 11'd 0;
defparam Ur3_n_7_pp.CD = 11'd 1429;
defparam Ur3_n_7_pp.CE = 11'd 1023;
defparam Ur3_n_7_pp.CF = 11'd 404;
wire [10:0] lut_val_3_n_8_pp;
rom_lut_r_cen Ur3_n_8_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {addr_low,addr_low,sym_res_15_n[8],sym_res_14_n[8] } ), .data_out( lut_val_3_n_8_pp[10:0]) ) ;
defparam Ur3_n_8_pp.DATA_WIDTH = 11;
defparam Ur3_n_8_pp.C0 = 11'd 0;
defparam Ur3_n_8_pp.C1 = 11'd 1429;
defparam Ur3_n_8_pp.C2 = 11'd 1023;
defparam Ur3_n_8_pp.C3 = 11'd 404;
defparam Ur3_n_8_pp.C4 = 11'd 0;
defparam Ur3_n_8_pp.C5 = 11'd 1429;
defparam Ur3_n_8_pp.C6 = 11'd 1023;
defparam Ur3_n_8_pp.C7 = 11'd 404;
defparam Ur3_n_8_pp.C8 = 11'd 0;
defparam Ur3_n_8_pp.C9 = 11'd 1429;
defparam Ur3_n_8_pp.CA = 11'd 1023;
defparam Ur3_n_8_pp.CB = 11'd 404;
defparam Ur3_n_8_pp.CC = 11'd 0;
defparam Ur3_n_8_pp.CD = 11'd 1429;
defparam Ur3_n_8_pp.CE = 11'd 1023;
defparam Ur3_n_8_pp.CF = 11'd 404;
wire [10:0] lut_val_3_n_9_pp;
rom_lut_r_cen Ur3_n_9_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {addr_low,addr_low,sym_res_15_n[9],sym_res_14_n[9] } ), .data_out( lut_val_3_n_9_pp[10:0]) ) ;
defparam Ur3_n_9_pp.DATA_WIDTH = 11;
defparam Ur3_n_9_pp.C0 = 11'd 0;
defparam Ur3_n_9_pp.C1 = 11'd 1429;
defparam Ur3_n_9_pp.C2 = 11'd 1023;
defparam Ur3_n_9_pp.C3 = 11'd 404;
defparam Ur3_n_9_pp.C4 = 11'd 0;
defparam Ur3_n_9_pp.C5 = 11'd 1429;
defparam Ur3_n_9_pp.C6 = 11'd 1023;
defparam Ur3_n_9_pp.C7 = 11'd 404;
defparam Ur3_n_9_pp.C8 = 11'd 0;
defparam Ur3_n_9_pp.C9 = 11'd 1429;
defparam Ur3_n_9_pp.CA = 11'd 1023;
defparam Ur3_n_9_pp.CB = 11'd 404;
defparam Ur3_n_9_pp.CC = 11'd 0;
defparam Ur3_n_9_pp.CD = 11'd 1429;
defparam Ur3_n_9_pp.CE = 11'd 1023;
defparam Ur3_n_9_pp.CF = 11'd 404;
wire [10:0] lut_val_3_n_10_pp;
rom_lut_r_cen Ur3_n_10_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {addr_low,addr_low,sym_res_15_n[10],sym_res_14_n[10] } ), .data_out( lut_val_3_n_10_pp[10:0]) ) ;
defparam Ur3_n_10_pp.DATA_WIDTH = 11;
defparam Ur3_n_10_pp.C0 = 11'd 0;
defparam Ur3_n_10_pp.C1 = 11'd 1429;
defparam Ur3_n_10_pp.C2 = 11'd 1023;
defparam Ur3_n_10_pp.C3 = 11'd 404;
defparam Ur3_n_10_pp.C4 = 11'd 0;
defparam Ur3_n_10_pp.C5 = 11'd 1429;
defparam Ur3_n_10_pp.C6 = 11'd 1023;
defparam Ur3_n_10_pp.C7 = 11'd 404;
defparam Ur3_n_10_pp.C8 = 11'd 0;
defparam Ur3_n_10_pp.C9 = 11'd 1429;
defparam Ur3_n_10_pp.CA = 11'd 1023;
defparam Ur3_n_10_pp.CB = 11'd 404;
defparam Ur3_n_10_pp.CC = 11'd 0;
defparam Ur3_n_10_pp.CD = 11'd 1429;
defparam Ur3_n_10_pp.CE = 11'd 1023;
defparam Ur3_n_10_pp.CF = 11'd 404;
wire [10:0] lut_val_3_n_11_pp;
rom_lut_r_cen Ur3_n_11_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {addr_low,addr_low,sym_res_15_n[11],sym_res_14_n[11] } ), .data_out( lut_val_3_n_11_pp[10:0]) ) ;
defparam Ur3_n_11_pp.DATA_WIDTH = 11;
defparam Ur3_n_11_pp.C0 = 11'd 0;
defparam Ur3_n_11_pp.C1 = 11'd 619;
defparam Ur3_n_11_pp.C2 = 11'd 1025;
defparam Ur3_n_11_pp.C3 = 11'd 1644;
defparam Ur3_n_11_pp.C4 = 11'd 0;
defparam Ur3_n_11_pp.C5 = 11'd 619;
defparam Ur3_n_11_pp.C6 = 11'd 1025;
defparam Ur3_n_11_pp.C7 = 11'd 1644;
defparam Ur3_n_11_pp.C8 = 11'd 0;
defparam Ur3_n_11_pp.C9 = 11'd 619;
defparam Ur3_n_11_pp.CA = 11'd 1025;
defparam Ur3_n_11_pp.CB = 11'd 1644;
defparam Ur3_n_11_pp.CC = 11'd 0;
defparam Ur3_n_11_pp.CD = 11'd 619;
defparam Ur3_n_11_pp.CE = 11'd 1025;
defparam Ur3_n_11_pp.CF = 11'd 1644;
// ---- partial product adder tree ----
wire [21:0] lut_0_bit_0_fill;
wire [21:0] lut_0_bit_1_fill;
wire [21:0] lut_0_bit_2_fill;
wire [21:0] lut_0_bit_3_fill;
wire [21:0] lut_0_bit_4_fill;
wire [21:0] lut_0_bit_5_fill;
wire [21:0] lut_0_bit_6_fill;
wire [21:0] lut_0_bit_7_fill;
wire [21:0] lut_0_bit_8_fill;
wire [21:0] lut_0_bit_9_fill;
wire [21:0] lut_0_bit_10_fill;
wire [21:0] lut_0_bit_11_fill;
assign lut_0_bit_0_fill = {lut_val_0_n_0_pp[10], lut_val_0_n_0_pp[10], lut_val_0_n_0_pp[10], lut_val_0_n_0_pp[10], lut_val_0_n_0_pp[10], lut_val_0_n_0_pp[10], lut_val_0_n_0_pp[10], lut_val_0_n_0_pp[10], lut_val_0_n_0_pp[10], lut_val_0_n_0_pp[10], lut_val_0_n_0_pp[10], lut_val_0_n_0_pp };
assign lut_0_bit_1_fill = {lut_val_0_n_1_pp[10], lut_val_0_n_1_pp[10], lut_val_0_n_1_pp[10], lut_val_0_n_1_pp[10], lut_val_0_n_1_pp[10], lut_val_0_n_1_pp[10], lut_val_0_n_1_pp[10], lut_val_0_n_1_pp[10], lut_val_0_n_1_pp[10], lut_val_0_n_1_pp[10], lut_val_0_n_1_pp, 1'd0 };
assign lut_0_bit_2_fill = {lut_val_0_n_2_pp[10], lut_val_0_n_2_pp[10], lut_val_0_n_2_pp[10], lut_val_0_n_2_pp[10], lut_val_0_n_2_pp[10], lut_val_0_n_2_pp[10], lut_val_0_n_2_pp[10], lut_val_0_n_2_pp[10], lut_val_0_n_2_pp[10], lut_val_0_n_2_pp, 2'd0 };
assign lut_0_bit_3_fill = {lut_val_0_n_3_pp[10], lut_val_0_n_3_pp[10], lut_val_0_n_3_pp[10], lut_val_0_n_3_pp[10], lut_val_0_n_3_pp[10], lut_val_0_n_3_pp[10], lut_val_0_n_3_pp[10], lut_val_0_n_3_pp[10], lut_val_0_n_3_pp, 3'd0 };
assign lut_0_bit_4_fill = {lut_val_0_n_4_pp[10], lut_val_0_n_4_pp[10], lut_val_0_n_4_pp[10], lut_val_0_n_4_pp[10], lut_val_0_n_4_pp[10], lut_val_0_n_4_pp[10], lut_val_0_n_4_pp[10], lut_val_0_n_4_pp, 4'd0 };
assign lut_0_bit_5_fill = {lut_val_0_n_5_pp[10], lut_val_0_n_5_pp[10], lut_val_0_n_5_pp[10], lut_val_0_n_5_pp[10], lut_val_0_n_5_pp[10], lut_val_0_n_5_pp[10], lut_val_0_n_5_pp, 5'd0 };
assign lut_0_bit_6_fill = {lut_val_0_n_6_pp[10], lut_val_0_n_6_pp[10], lut_val_0_n_6_pp[10], lut_val_0_n_6_pp[10], lut_val_0_n_6_pp[10], lut_val_0_n_6_pp, 6'd0 };
assign lut_0_bit_7_fill = {lut_val_0_n_7_pp[10], lut_val_0_n_7_pp[10], lut_val_0_n_7_pp[10], lut_val_0_n_7_pp[10], lut_val_0_n_7_pp, 7'd0 };
assign lut_0_bit_8_fill = {lut_val_0_n_8_pp[10], lut_val_0_n_8_pp[10], lut_val_0_n_8_pp[10], lut_val_0_n_8_pp, 8'd0 };
assign lut_0_bit_9_fill = {lut_val_0_n_9_pp[10], lut_val_0_n_9_pp[10], lut_val_0_n_9_pp, 9'd0 };
assign lut_0_bit_10_fill = {lut_val_0_n_10_pp[10], lut_val_0_n_10_pp, 10'd0 };
assign lut_0_bit_11_fill = { lut_val_0_n_11_pp, 11'd0 };
wire [22:0] tree_0_pp_l_0_n_0_n;
sadd_lpm_cen Uadd_0_lut_l_0_n_0_n (.clk(clk), .gclk_en(clk_en), .ain(lut_0_bit_0_fill), .bin(lut_0_bit_1_fill), .res(tree_0_pp_l_0_n_0_n) );
defparam Uadd_0_lut_l_0_n_0_n.IN_WIDTH = 22;
defparam Uadd_0_lut_l_0_n_0_n.PIPE_DEPTH = 3;
wire [22:0] tree_0_pp_l_0_n_1_n;
sadd_lpm_cen Uadd_0_lut_l_0_n_1_n (.clk(clk), .gclk_en(clk_en), .ain(lut_0_bit_2_fill), .bin(lut_0_bit_3_fill), .res(tree_0_pp_l_0_n_1_n) );
defparam Uadd_0_lut_l_0_n_1_n.IN_WIDTH = 22;
defparam Uadd_0_lut_l_0_n_1_n.PIPE_DEPTH = 3;
wire [22:0] tree_0_pp_l_0_n_2_n;
sadd_lpm_cen Uadd_0_lut_l_0_n_2_n (.clk(clk), .gclk_en(clk_en), .ain(lut_0_bit_4_fill), .bin(lut_0_bit_5_fill), .res(tree_0_pp_l_0_n_2_n) );
defparam Uadd_0_lut_l_0_n_2_n.IN_WIDTH = 22;
defparam Uadd_0_lut_l_0_n_2_n.PIPE_DEPTH = 3;
wire [22:0] tree_0_pp_l_0_n_3_n;
sadd_lpm_cen Uadd_0_lut_l_0_n_3_n (.clk(clk), .gclk_en(clk_en), .ain(lut_0_bit_6_fill), .bin(lut_0_bit_7_fill), .res(tree_0_pp_l_0_n_3_n) );
defparam Uadd_0_lut_l_0_n_3_n.IN_WIDTH = 22;
defparam Uadd_0_lut_l_0_n_3_n.PIPE_DEPTH = 3;
wire [22:0] tree_0_pp_l_0_n_4_n;
sadd_lpm_cen Uadd_0_lut_l_0_n_4_n (.clk(clk), .gclk_en(clk_en), .ain(lut_0_bit_8_fill), .bin(lut_0_bit_9_fill), .res(tree_0_pp_l_0_n_4_n) );
defparam Uadd_0_lut_l_0_n_4_n.IN_WIDTH = 22;
defparam Uadd_0_lut_l_0_n_4_n.PIPE_DEPTH = 3;
wire [22:0] tree_0_pp_l_0_n_5_n;
sadd_lpm_cen Uadd_0_lut_l_0_n_5_n (.clk(clk), .gclk_en(clk_en), .ain(lut_0_bit_10_fill), .bin(lut_0_bit_11_fill), .res(tree_0_pp_l_0_n_5_n) );
defparam Uadd_0_lut_l_0_n_5_n.IN_WIDTH = 22;
defparam Uadd_0_lut_l_0_n_5_n.PIPE_DEPTH = 3;
wire [23:0] tree_0_pp_l_1_n_0_n;
sadd_lpm_cen Uadd_0_lut_l_1_n_0_n (.clk(clk), .gclk_en(clk_en), .ain(tree_0_pp_l_0_n_0_n), .bin(tree_0_pp_l_0_n_1_n), .res(tree_0_pp_l_1_n_0_n) );
defparam Uadd_0_lut_l_1_n_0_n.IN_WIDTH = 23;
defparam Uadd_0_lut_l_1_n_0_n.PIPE_DEPTH = 3;
wire [23:0] tree_0_pp_l_1_n_1_n;
sadd_lpm_cen Uadd_0_lut_l_1_n_1_n (.clk(clk), .gclk_en(clk_en), .ain(tree_0_pp_l_0_n_2_n), .bin(tree_0_pp_l_0_n_3_n), .res(tree_0_pp_l_1_n_1_n) );
defparam Uadd_0_lut_l_1_n_1_n.IN_WIDTH = 23;
defparam Uadd_0_lut_l_1_n_1_n.PIPE_DEPTH = 3;
wire [23:0] tree_0_pp_l_1_n_2_n;
sadd_lpm_cen Uadd_0_lut_l_1_n_2_n (.clk(clk), .gclk_en(clk_en), .ain(tree_0_pp_l_0_n_4_n), .bin(tree_0_pp_l_0_n_5_n), .res(tree_0_pp_l_1_n_2_n) );
defparam Uadd_0_lut_l_1_n_2_n.IN_WIDTH = 23;
defparam Uadd_0_lut_l_1_n_2_n.PIPE_DEPTH = 3;
wire [24:0] tree_0_pp_l_2_n_0_n;
sadd_lpm_cen Uadd_0_lut_l_2_n_0_n (.clk(clk), .gclk_en(clk_en), .ain(tree_0_pp_l_1_n_0_n), .bin(tree_0_pp_l_1_n_1_n), .res(tree_0_pp_l_2_n_0_n) );
defparam Uadd_0_lut_l_2_n_0_n.IN_WIDTH = 24;
defparam Uadd_0_lut_l_2_n_0_n.PIPE_DEPTH = 3;
wire [24:0] tree_0_pp_l_2_n_1_n;
sadd_lpm_cen Uadd_0_lut_l_2_n_1_n (.clk(clk), .gclk_en(clk_en), .ain(tree_0_pp_l_1_n_2_n), .bin(24'd0), .res(tree_0_pp_l_2_n_1_n) );
defparam Uadd_0_lut_l_2_n_1_n.IN_WIDTH = 24;
defparam Uadd_0_lut_l_2_n_1_n.PIPE_DEPTH = 3;
wire [25:0] tree_0_pp_l_3_n_0_n;
sadd_lpm_cen Uadd_0_lut_l_3_n_0_n (.clk(clk), .gclk_en(clk_en), .ain(tree_0_pp_l_2_n_0_n), .bin(tree_0_pp_l_2_n_1_n), .res(tree_0_pp_l_3_n_0_n) );
defparam Uadd_0_lut_l_3_n_0_n.IN_WIDTH = 25;
defparam Uadd_0_lut_l_3_n_0_n.PIPE_DEPTH = 3;
wire [25:0] lut_val_0_n;
assign lut_val_0_n=tree_0_pp_l_3_n_0_n;
// ---- partial product adder tree ----
wire [21:0] lut_1_bit_0_fill;
wire [21:0] lut_1_bit_1_fill;
wire [21:0] lut_1_bit_2_fill;
wire [21:0] lut_1_bit_3_fill;
wire [21:0] lut_1_bit_4_fill;
wire [21:0] lut_1_bit_5_fill;
wire [21:0] lut_1_bit_6_fill;
wire [21:0] lut_1_bit_7_fill;
wire [21:0] lut_1_bit_8_fill;
wire [21:0] lut_1_bit_9_fill;
wire [21:0] lut_1_bit_10_fill;
wire [21:0] lut_1_bit_11_fill;
assign lut_1_bit_0_fill = {lut_val_1_n_0_pp[10], lut_val_1_n_0_pp[10], lut_val_1_n_0_pp[10], lut_val_1_n_0_pp[10], lut_val_1_n_0_pp[10], lut_val_1_n_0_pp[10], lut_val_1_n_0_pp[10], lut_val_1_n_0_pp[10], lut_val_1_n_0_pp[10], lut_val_1_n_0_pp[10], lut_val_1_n_0_pp[10], lut_val_1_n_0_pp };
assign lut_1_bit_1_fill = {lut_val_1_n_1_pp[10], lut_val_1_n_1_pp[10], lut_val_1_n_1_pp[10], lut_val_1_n_1_pp[10], lut_val_1_n_1_pp[10], lut_val_1_n_1_pp[10], lut_val_1_n_1_pp[10], lut_val_1_n_1_pp[10], lut_val_1_n_1_pp[10], lut_val_1_n_1_pp[10], lut_val_1_n_1_pp, 1'd0 };
assign lut_1_bit_2_fill = {lut_val_1_n_2_pp[10], lut_val_1_n_2_pp[10], lut_val_1_n_2_pp[10], lut_val_1_n_2_pp[10], lut_val_1_n_2_pp[10], lut_val_1_n_2_pp[10], lut_val_1_n_2_pp[10], lut_val_1_n_2_pp[10], lut_val_1_n_2_pp[10], lut_val_1_n_2_pp, 2'd0 };
assign lut_1_bit_3_fill = {lut_val_1_n_3_pp[10], lut_val_1_n_3_pp[10], lut_val_1_n_3_pp[10], lut_val_1_n_3_pp[10], lut_val_1_n_3_pp[10], lut_val_1_n_3_pp[10], lut_val_1_n_3_pp[10], lut_val_1_n_3_pp[10], lut_val_1_n_3_pp, 3'd0 };
assign lut_1_bit_4_fill = {lut_val_1_n_4_pp[10], lut_val_1_n_4_pp[10], lut_val_1_n_4_pp[10], lut_val_1_n_4_pp[10], lut_val_1_n_4_pp[10], lut_val_1_n_4_pp[10], lut_val_1_n_4_pp[10], lut_val_1_n_4_pp, 4'd0 };
assign lut_1_bit_5_fill = {lut_val_1_n_5_pp[10], lut_val_1_n_5_pp[10], lut_val_1_n_5_pp[10], lut_val_1_n_5_pp[10], lut_val_1_n_5_pp[10], lut_val_1_n_5_pp[10], lut_val_1_n_5_pp, 5'd0 };
assign lut_1_bit_6_fill = {lut_val_1_n_6_pp[10], lut_val_1_n_6_pp[10], lut_val_1_n_6_pp[10], lut_val_1_n_6_pp[10], lut_val_1_n_6_pp[10], lut_val_1_n_6_pp, 6'd0 };
assign lut_1_bit_7_fill = {lut_val_1_n_7_pp[10], lut_val_1_n_7_pp[10], lut_val_1_n_7_pp[10], lut_val_1_n_7_pp[10], lut_val_1_n_7_pp, 7'd0 };
assign lut_1_bit_8_fill = {lut_val_1_n_8_pp[10], lut_val_1_n_8_pp[10], lut_val_1_n_8_pp[10], lut_val_1_n_8_pp, 8'd0 };
assign lut_1_bit_9_fill = {lut_val_1_n_9_pp[10], lut_val_1_n_9_pp[10], lut_val_1_n_9_pp, 9'd0 };
assign lut_1_bit_10_fill = {lut_val_1_n_10_pp[10], lut_val_1_n_10_pp, 10'd0 };
assign lut_1_bit_11_fill = { lut_val_1_n_11_pp, 11'd0 };
wire [22:0] tree_1_pp_l_0_n_0_n;
sadd_lpm_cen Uadd_1_lut_l_0_n_0_n (.clk(clk), .gclk_en(clk_en), .ain(lut_1_bit_0_fill), .bin(lut_1_bit_1_fill), .res(tree_1_pp_l_0_n_0_n) );
defparam Uadd_1_lut_l_0_n_0_n.IN_WIDTH = 22;
defparam Uadd_1_lut_l_0_n_0_n.PIPE_DEPTH = 3;
wire [22:0] tree_1_pp_l_0_n_1_n;
sadd_lpm_cen Uadd_1_lut_l_0_n_1_n (.clk(clk), .gclk_en(clk_en), .ain(lut_1_bit_2_fill), .bin(lut_1_bit_3_fill), .res(tree_1_pp_l_0_n_1_n) );
defparam Uadd_1_lut_l_0_n_1_n.IN_WIDTH = 22;
defparam Uadd_1_lut_l_0_n_1_n.PIPE_DEPTH = 3;
wire [22:0] tree_1_pp_l_0_n_2_n;
sadd_lpm_cen Uadd_1_lut_l_0_n_2_n (.clk(clk), .gclk_en(clk_en), .ain(lut_1_bit_4_fill), .bin(lut_1_bit_5_fill), .res(tree_1_pp_l_0_n_2_n) );
defparam Uadd_1_lut_l_0_n_2_n.IN_WIDTH = 22;
defparam Uadd_1_lut_l_0_n_2_n.PIPE_DEPTH = 3;
wire [22:0] tree_1_pp_l_0_n_3_n;
sadd_lpm_cen Uadd_1_lut_l_0_n_3_n (.clk(clk), .gclk_en(clk_en), .ain(lut_1_bit_6_fill), .bin(lut_1_bit_7_fill), .res(tree_1_pp_l_0_n_3_n) );
defparam Uadd_1_lut_l_0_n_3_n.IN_WIDTH = 22;
defparam Uadd_1_lut_l_0_n_3_n.PIPE_DEPTH = 3;
wire [22:0] tree_1_pp_l_0_n_4_n;
sadd_lpm_cen Uadd_1_lut_l_0_n_4_n (.clk(clk), .gclk_en(clk_en), .ain(lut_1_bit_8_fill), .bin(lut_1_bit_9_fill), .res(tree_1_pp_l_0_n_4_n) );
defparam Uadd_1_lut_l_0_n_4_n.IN_WIDTH = 22;
defparam Uadd_1_lut_l_0_n_4_n.PIPE_DEPTH = 3;
wire [22:0] tree_1_pp_l_0_n_5_n;
sadd_lpm_cen Uadd_1_lut_l_0_n_5_n (.clk(clk), .gclk_en(clk_en), .ain(lut_1_bit_10_fill), .bin(lut_1_bit_11_fill), .res(tree_1_pp_l_0_n_5_n) );
defparam Uadd_1_lut_l_0_n_5_n.IN_WIDTH = 22;
defparam Uadd_1_lut_l_0_n_5_n.PIPE_DEPTH = 3;
wire [23:0] tree_1_pp_l_1_n_0_n;
sadd_lpm_cen Uadd_1_lut_l_1_n_0_n (.clk(clk), .gclk_en(clk_en), .ain(tree_1_pp_l_0_n_0_n), .bin(tree_1_pp_l_0_n_1_n), .res(tree_1_pp_l_1_n_0_n) );
defparam Uadd_1_lut_l_1_n_0_n.IN_WIDTH = 23;
defparam Uadd_1_lut_l_1_n_0_n.PIPE_DEPTH = 3;
wire [23:0] tree_1_pp_l_1_n_1_n;
sadd_lpm_cen Uadd_1_lut_l_1_n_1_n (.clk(clk), .gclk_en(clk_en), .ain(tree_1_pp_l_0_n_2_n), .bin(tree_1_pp_l_0_n_3_n), .res(tree_1_pp_l_1_n_1_n) );
defparam Uadd_1_lut_l_1_n_1_n.IN_WIDTH = 23;
defparam Uadd_1_lut_l_1_n_1_n.PIPE_DEPTH = 3;
wire [23:0] tree_1_pp_l_1_n_2_n;
sadd_lpm_cen Uadd_1_lut_l_1_n_2_n (.clk(clk), .gclk_en(clk_en), .ain(tree_1_pp_l_0_n_4_n), .bin(tree_1_pp_l_0_n_5_n), .res(tree_1_pp_l_1_n_2_n) );
defparam Uadd_1_lut_l_1_n_2_n.IN_WIDTH = 23;
defparam Uadd_1_lut_l_1_n_2_n.PIPE_DEPTH = 3;
wire [24:0] tree_1_pp_l_2_n_0_n;
sadd_lpm_cen Uadd_1_lut_l_2_n_0_n (.clk(clk), .gclk_en(clk_en), .ain(tree_1_pp_l_1_n_0_n), .bin(tree_1_pp_l_1_n_1_n), .res(tree_1_pp_l_2_n_0_n) );
defparam Uadd_1_lut_l_2_n_0_n.IN_WIDTH = 24;
defparam Uadd_1_lut_l_2_n_0_n.PIPE_DEPTH = 3;
wire [24:0] tree_1_pp_l_2_n_1_n;
sadd_lpm_cen Uadd_1_lut_l_2_n_1_n (.clk(clk), .gclk_en(clk_en), .ain(tree_1_pp_l_1_n_2_n), .bin(24'd0), .res(tree_1_pp_l_2_n_1_n) );
defparam Uadd_1_lut_l_2_n_1_n.IN_WIDTH = 24;
defparam Uadd_1_lut_l_2_n_1_n.PIPE_DEPTH = 3;
wire [25:0] tree_1_pp_l_3_n_0_n;
sadd_lpm_cen Uadd_1_lut_l_3_n_0_n (.clk(clk), .gclk_en(clk_en), .ain(tree_1_pp_l_2_n_0_n), .bin(tree_1_pp_l_2_n_1_n), .res(tree_1_pp_l_3_n_0_n) );
defparam Uadd_1_lut_l_3_n_0_n.IN_WIDTH = 25;
defparam Uadd_1_lut_l_3_n_0_n.PIPE_DEPTH = 3;
wire [25:0] lut_val_1_n;
assign lut_val_1_n=tree_1_pp_l_3_n_0_n;
// ---- partial product adder tree ----
wire [21:0] lut_2_bit_0_fill;
wire [21:0] lut_2_bit_1_fill;
wire [21:0] lut_2_bit_2_fill;
wire [21:0] lut_2_bit_3_fill;
wire [21:0] lut_2_bit_4_fill;
wire [21:0] lut_2_bit_5_fill;
wire [21:0] lut_2_bit_6_fill;
wire [21:0] lut_2_bit_7_fill;
wire [21:0] lut_2_bit_8_fill;
wire [21:0] lut_2_bit_9_fill;
wire [21:0] lut_2_bit_10_fill;
wire [21:0] lut_2_bit_11_fill;
assign lut_2_bit_0_fill = {lut_val_2_n_0_pp[10], lut_val_2_n_0_pp[10], lut_val_2_n_0_pp[10], lut_val_2_n_0_pp[10], lut_val_2_n_0_pp[10], lut_val_2_n_0_pp[10], lut_val_2_n_0_pp[10], lut_val_2_n_0_pp[10], lut_val_2_n_0_pp[10], lut_val_2_n_0_pp[10], lut_val_2_n_0_pp[10], lut_val_2_n_0_pp };
assign lut_2_bit_1_fill = {lut_val_2_n_1_pp[10], lut_val_2_n_1_pp[10], lut_val_2_n_1_pp[10], lut_val_2_n_1_pp[10], lut_val_2_n_1_pp[10], lut_val_2_n_1_pp[10], lut_val_2_n_1_pp[10], lut_val_2_n_1_pp[10], lut_val_2_n_1_pp[10], lut_val_2_n_1_pp[10], lut_val_2_n_1_pp, 1'd0 };
assign lut_2_bit_2_fill = {lut_val_2_n_2_pp[10], lut_val_2_n_2_pp[10], lut_val_2_n_2_pp[10], lut_val_2_n_2_pp[10], lut_val_2_n_2_pp[10], lut_val_2_n_2_pp[10], lut_val_2_n_2_pp[10], lut_val_2_n_2_pp[10], lut_val_2_n_2_pp[10], lut_val_2_n_2_pp, 2'd0 };
assign lut_2_bit_3_fill = {lut_val_2_n_3_pp[10], lut_val_2_n_3_pp[10], lut_val_2_n_3_pp[10], lut_val_2_n_3_pp[10], lut_val_2_n_3_pp[10], lut_val_2_n_3_pp[10], lut_val_2_n_3_pp[10], lut_val_2_n_3_pp[10], lut_val_2_n_3_pp, 3'd0 };
assign lut_2_bit_4_fill = {lut_val_2_n_4_pp[10], lut_val_2_n_4_pp[10], lut_val_2_n_4_pp[10], lut_val_2_n_4_pp[10], lut_val_2_n_4_pp[10], lut_val_2_n_4_pp[10], lut_val_2_n_4_pp[10], lut_val_2_n_4_pp, 4'd0 };
assign lut_2_bit_5_fill = {lut_val_2_n_5_pp[10], lut_val_2_n_5_pp[10], lut_val_2_n_5_pp[10], lut_val_2_n_5_pp[10], lut_val_2_n_5_pp[10], lut_val_2_n_5_pp[10], lut_val_2_n_5_pp, 5'd0 };
assign lut_2_bit_6_fill = {lut_val_2_n_6_pp[10], lut_val_2_n_6_pp[10], lut_val_2_n_6_pp[10], lut_val_2_n_6_pp[10], lut_val_2_n_6_pp[10], lut_val_2_n_6_pp, 6'd0 };
assign lut_2_bit_7_fill = {lut_val_2_n_7_pp[10], lut_val_2_n_7_pp[10], lut_val_2_n_7_pp[10], lut_val_2_n_7_pp[10], lut_val_2_n_7_pp, 7'd0 };
assign lut_2_bit_8_fill = {lut_val_2_n_8_pp[10], lut_val_2_n_8_pp[10], lut_val_2_n_8_pp[10], lut_val_2_n_8_pp, 8'd0 };
assign lut_2_bit_9_fill = {lut_val_2_n_9_pp[10], lut_val_2_n_9_pp[10], lut_val_2_n_9_pp, 9'd0 };
assign lut_2_bit_10_fill = {lut_val_2_n_10_pp[10], lut_val_2_n_10_pp, 10'd0 };
assign lut_2_bit_11_fill = { lut_val_2_n_11_pp, 11'd0 };
wire [22:0] tree_2_pp_l_0_n_0_n;
sadd_lpm_cen Uadd_2_lut_l_0_n_0_n (.clk(clk), .gclk_en(clk_en), .ain(lut_2_bit_0_fill), .bin(lut_2_bit_1_fill), .res(tree_2_pp_l_0_n_0_n) );
defparam Uadd_2_lut_l_0_n_0_n.IN_WIDTH = 22;
defparam Uadd_2_lut_l_0_n_0_n.PIPE_DEPTH = 3;
wire [22:0] tree_2_pp_l_0_n_1_n;
sadd_lpm_cen Uadd_2_lut_l_0_n_1_n (.clk(clk), .gclk_en(clk_en), .ain(lut_2_bit_2_fill), .bin(lut_2_bit_3_fill), .res(tree_2_pp_l_0_n_1_n) );
defparam Uadd_2_lut_l_0_n_1_n.IN_WIDTH = 22;
defparam Uadd_2_lut_l_0_n_1_n.PIPE_DEPTH = 3;
wire [22:0] tree_2_pp_l_0_n_2_n;
sadd_lpm_cen Uadd_2_lut_l_0_n_2_n (.clk(clk), .gclk_en(clk_en), .ain(lut_2_bit_4_fill), .bin(lut_2_bit_5_fill), .res(tree_2_pp_l_0_n_2_n) );
defparam Uadd_2_lut_l_0_n_2_n.IN_WIDTH = 22;
defparam Uadd_2_lut_l_0_n_2_n.PIPE_DEPTH = 3;
wire [22:0] tree_2_pp_l_0_n_3_n;
sadd_lpm_cen Uadd_2_lut_l_0_n_3_n (.clk(clk), .gclk_en(clk_en), .ain(lut_2_bit_6_fill), .bin(lut_2_bit_7_fill), .res(tree_2_pp_l_0_n_3_n) );
defparam Uadd_2_lut_l_0_n_3_n.IN_WIDTH = 22;
defparam Uadd_2_lut_l_0_n_3_n.PIPE_DEPTH = 3;
wire [22:0] tree_2_pp_l_0_n_4_n;
sadd_lpm_cen Uadd_2_lut_l_0_n_4_n (.clk(clk), .gclk_en(clk_en), .ain(lut_2_bit_8_fill), .bin(lut_2_bit_9_fill), .res(tree_2_pp_l_0_n_4_n) );
defparam Uadd_2_lut_l_0_n_4_n.IN_WIDTH = 22;
defparam Uadd_2_lut_l_0_n_4_n.PIPE_DEPTH = 3;
wire [22:0] tree_2_pp_l_0_n_5_n;
sadd_lpm_cen Uadd_2_lut_l_0_n_5_n (.clk(clk), .gclk_en(clk_en), .ain(lut_2_bit_10_fill), .bin(lut_2_bit_11_fill), .res(tree_2_pp_l_0_n_5_n) );
defparam Uadd_2_lut_l_0_n_5_n.IN_WIDTH = 22;
defparam Uadd_2_lut_l_0_n_5_n.PIPE_DEPTH = 3;
wire [23:0] tree_2_pp_l_1_n_0_n;
sadd_lpm_cen Uadd_2_lut_l_1_n_0_n (.clk(clk), .gclk_en(clk_en), .ain(tree_2_pp_l_0_n_0_n), .bin(tree_2_pp_l_0_n_1_n), .res(tree_2_pp_l_1_n_0_n) );
defparam Uadd_2_lut_l_1_n_0_n.IN_WIDTH = 23;
defparam Uadd_2_lut_l_1_n_0_n.PIPE_DEPTH = 3;
wire [23:0] tree_2_pp_l_1_n_1_n;
sadd_lpm_cen Uadd_2_lut_l_1_n_1_n (.clk(clk), .gclk_en(clk_en), .ain(tree_2_pp_l_0_n_2_n), .bin(tree_2_pp_l_0_n_3_n), .res(tree_2_pp_l_1_n_1_n) );
defparam Uadd_2_lut_l_1_n_1_n.IN_WIDTH = 23;
defparam Uadd_2_lut_l_1_n_1_n.PIPE_DEPTH = 3;
wire [23:0] tree_2_pp_l_1_n_2_n;
sadd_lpm_cen Uadd_2_lut_l_1_n_2_n (.clk(clk), .gclk_en(clk_en), .ain(tree_2_pp_l_0_n_4_n), .bin(tree_2_pp_l_0_n_5_n), .res(tree_2_pp_l_1_n_2_n) );
defparam Uadd_2_lut_l_1_n_2_n.IN_WIDTH = 23;
defparam Uadd_2_lut_l_1_n_2_n.PIPE_DEPTH = 3;
wire [24:0] tree_2_pp_l_2_n_0_n;
sadd_lpm_cen Uadd_2_lut_l_2_n_0_n (.clk(clk), .gclk_en(clk_en), .ain(tree_2_pp_l_1_n_0_n), .bin(tree_2_pp_l_1_n_1_n), .res(tree_2_pp_l_2_n_0_n) );
defparam Uadd_2_lut_l_2_n_0_n.IN_WIDTH = 24;
defparam Uadd_2_lut_l_2_n_0_n.PIPE_DEPTH = 3;
wire [24:0] tree_2_pp_l_2_n_1_n;
sadd_lpm_cen Uadd_2_lut_l_2_n_1_n (.clk(clk), .gclk_en(clk_en), .ain(tree_2_pp_l_1_n_2_n), .bin(24'd0), .res(tree_2_pp_l_2_n_1_n) );
defparam Uadd_2_lut_l_2_n_1_n.IN_WIDTH = 24;
defparam Uadd_2_lut_l_2_n_1_n.PIPE_DEPTH = 3;
wire [25:0] tree_2_pp_l_3_n_0_n;
sadd_lpm_cen Uadd_2_lut_l_3_n_0_n (.clk(clk), .gclk_en(clk_en), .ain(tree_2_pp_l_2_n_0_n), .bin(tree_2_pp_l_2_n_1_n), .res(tree_2_pp_l_3_n_0_n) );
defparam Uadd_2_lut_l_3_n_0_n.IN_WIDTH = 25;
defparam Uadd_2_lut_l_3_n_0_n.PIPE_DEPTH = 3;
wire [25:0] lut_val_2_n;
assign lut_val_2_n=tree_2_pp_l_3_n_0_n;
// ---- partial product adder tree ----
wire [21:0] lut_3_bit_0_fill;
wire [21:0] lut_3_bit_1_fill;
wire [21:0] lut_3_bit_2_fill;
wire [21:0] lut_3_bit_3_fill;
wire [21:0] lut_3_bit_4_fill;
wire [21:0] lut_3_bit_5_fill;
wire [21:0] lut_3_bit_6_fill;
wire [21:0] lut_3_bit_7_fill;
wire [21:0] lut_3_bit_8_fill;
wire [21:0] lut_3_bit_9_fill;
wire [21:0] lut_3_bit_10_fill;
wire [21:0] lut_3_bit_11_fill;
assign lut_3_bit_0_fill = {lut_val_3_n_0_pp[10], lut_val_3_n_0_pp[10], lut_val_3_n_0_pp[10], lut_val_3_n_0_pp[10], lut_val_3_n_0_pp[10], lut_val_3_n_0_pp[10], lut_val_3_n_0_pp[10], lut_val_3_n_0_pp[10], lut_val_3_n_0_pp[10], lut_val_3_n_0_pp[10], lut_val_3_n_0_pp[10], lut_val_3_n_0_pp };
assign lut_3_bit_1_fill = {lut_val_3_n_1_pp[10], lut_val_3_n_1_pp[10], lut_val_3_n_1_pp[10], lut_val_3_n_1_pp[10], lut_val_3_n_1_pp[10], lut_val_3_n_1_pp[10], lut_val_3_n_1_pp[10], lut_val_3_n_1_pp[10], lut_val_3_n_1_pp[10], lut_val_3_n_1_pp[10], lut_val_3_n_1_pp, 1'd0 };
assign lut_3_bit_2_fill = {lut_val_3_n_2_pp[10], lut_val_3_n_2_pp[10], lut_val_3_n_2_pp[10], lut_val_3_n_2_pp[10], lut_val_3_n_2_pp[10], lut_val_3_n_2_pp[10], lut_val_3_n_2_pp[10], lut_val_3_n_2_pp[10], lut_val_3_n_2_pp[10], lut_val_3_n_2_pp, 2'd0 };
assign lut_3_bit_3_fill = {lut_val_3_n_3_pp[10], lut_val_3_n_3_pp[10], lut_val_3_n_3_pp[10], lut_val_3_n_3_pp[10], lut_val_3_n_3_pp[10], lut_val_3_n_3_pp[10], lut_val_3_n_3_pp[10], lut_val_3_n_3_pp[10], lut_val_3_n_3_pp, 3'd0 };
assign lut_3_bit_4_fill = {lut_val_3_n_4_pp[10], lut_val_3_n_4_pp[10], lut_val_3_n_4_pp[10], lut_val_3_n_4_pp[10], lut_val_3_n_4_pp[10], lut_val_3_n_4_pp[10], lut_val_3_n_4_pp[10], lut_val_3_n_4_pp, 4'd0 };
assign lut_3_bit_5_fill = {lut_val_3_n_5_pp[10], lut_val_3_n_5_pp[10], lut_val_3_n_5_pp[10], lut_val_3_n_5_pp[10], lut_val_3_n_5_pp[10], lut_val_3_n_5_pp[10], lut_val_3_n_5_pp, 5'd0 };
assign lut_3_bit_6_fill = {lut_val_3_n_6_pp[10], lut_val_3_n_6_pp[10], lut_val_3_n_6_pp[10], lut_val_3_n_6_pp[10], lut_val_3_n_6_pp[10], lut_val_3_n_6_pp, 6'd0 };
assign lut_3_bit_7_fill = {lut_val_3_n_7_pp[10], lut_val_3_n_7_pp[10], lut_val_3_n_7_pp[10], lut_val_3_n_7_pp[10], lut_val_3_n_7_pp, 7'd0 };
assign lut_3_bit_8_fill = {lut_val_3_n_8_pp[10], lut_val_3_n_8_pp[10], lut_val_3_n_8_pp[10], lut_val_3_n_8_pp, 8'd0 };
assign lut_3_bit_9_fill = {lut_val_3_n_9_pp[10], lut_val_3_n_9_pp[10], lut_val_3_n_9_pp, 9'd0 };
assign lut_3_bit_10_fill = {lut_val_3_n_10_pp[10], lut_val_3_n_10_pp, 10'd0 };
assign lut_3_bit_11_fill = { lut_val_3_n_11_pp, 11'd0 };
wire [22:0] tree_3_pp_l_0_n_0_n;
sadd_lpm_cen Uadd_3_lut_l_0_n_0_n (.clk(clk), .gclk_en(clk_en), .ain(lut_3_bit_0_fill), .bin(lut_3_bit_1_fill), .res(tree_3_pp_l_0_n_0_n) );
defparam Uadd_3_lut_l_0_n_0_n.IN_WIDTH = 22;
defparam Uadd_3_lut_l_0_n_0_n.PIPE_DEPTH = 3;
wire [22:0] tree_3_pp_l_0_n_1_n;
sadd_lpm_cen Uadd_3_lut_l_0_n_1_n (.clk(clk), .gclk_en(clk_en), .ain(lut_3_bit_2_fill), .bin(lut_3_bit_3_fill), .res(tree_3_pp_l_0_n_1_n) );
defparam Uadd_3_lut_l_0_n_1_n.IN_WIDTH = 22;
defparam Uadd_3_lut_l_0_n_1_n.PIPE_DEPTH = 3;
wire [22:0] tree_3_pp_l_0_n_2_n;
sadd_lpm_cen Uadd_3_lut_l_0_n_2_n (.clk(clk), .gclk_en(clk_en), .ain(lut_3_bit_4_fill), .bin(lut_3_bit_5_fill), .res(tree_3_pp_l_0_n_2_n) );
defparam Uadd_3_lut_l_0_n_2_n.IN_WIDTH = 22;
defparam Uadd_3_lut_l_0_n_2_n.PIPE_DEPTH = 3;
wire [22:0] tree_3_pp_l_0_n_3_n;
sadd_lpm_cen Uadd_3_lut_l_0_n_3_n (.clk(clk), .gclk_en(clk_en), .ain(lut_3_bit_6_fill), .bin(lut_3_bit_7_fill), .res(tree_3_pp_l_0_n_3_n) );
defparam Uadd_3_lut_l_0_n_3_n.IN_WIDTH = 22;
defparam Uadd_3_lut_l_0_n_3_n.PIPE_DEPTH = 3;
wire [22:0] tree_3_pp_l_0_n_4_n;
sadd_lpm_cen Uadd_3_lut_l_0_n_4_n (.clk(clk), .gclk_en(clk_en), .ain(lut_3_bit_8_fill), .bin(lut_3_bit_9_fill), .res(tree_3_pp_l_0_n_4_n) );
defparam Uadd_3_lut_l_0_n_4_n.IN_WIDTH = 22;
defparam Uadd_3_lut_l_0_n_4_n.PIPE_DEPTH = 3;
wire [22:0] tree_3_pp_l_0_n_5_n;
sadd_lpm_cen Uadd_3_lut_l_0_n_5_n (.clk(clk), .gclk_en(clk_en), .ain(lut_3_bit_10_fill), .bin(lut_3_bit_11_fill), .res(tree_3_pp_l_0_n_5_n) );
defparam Uadd_3_lut_l_0_n_5_n.IN_WIDTH = 22;
defparam Uadd_3_lut_l_0_n_5_n.PIPE_DEPTH = 3;
wire [23:0] tree_3_pp_l_1_n_0_n;
sadd_lpm_cen Uadd_3_lut_l_1_n_0_n (.clk(clk), .gclk_en(clk_en), .ain(tree_3_pp_l_0_n_0_n), .bin(tree_3_pp_l_0_n_1_n), .res(tree_3_pp_l_1_n_0_n) );
defparam Uadd_3_lut_l_1_n_0_n.IN_WIDTH = 23;
defparam Uadd_3_lut_l_1_n_0_n.PIPE_DEPTH = 3;
wire [23:0] tree_3_pp_l_1_n_1_n;
sadd_lpm_cen Uadd_3_lut_l_1_n_1_n (.clk(clk), .gclk_en(clk_en), .ain(tree_3_pp_l_0_n_2_n), .bin(tree_3_pp_l_0_n_3_n), .res(tree_3_pp_l_1_n_1_n) );
defparam Uadd_3_lut_l_1_n_1_n.IN_WIDTH = 23;
defparam Uadd_3_lut_l_1_n_1_n.PIPE_DEPTH = 3;
wire [23:0] tree_3_pp_l_1_n_2_n;
sadd_lpm_cen Uadd_3_lut_l_1_n_2_n (.clk(clk), .gclk_en(clk_en), .ain(tree_3_pp_l_0_n_4_n), .bin(tree_3_pp_l_0_n_5_n), .res(tree_3_pp_l_1_n_2_n) );
defparam Uadd_3_lut_l_1_n_2_n.IN_WIDTH = 23;
defparam Uadd_3_lut_l_1_n_2_n.PIPE_DEPTH = 3;
wire [24:0] tree_3_pp_l_2_n_0_n;
sadd_lpm_cen Uadd_3_lut_l_2_n_0_n (.clk(clk), .gclk_en(clk_en), .ain(tree_3_pp_l_1_n_0_n), .bin(tree_3_pp_l_1_n_1_n), .res(tree_3_pp_l_2_n_0_n) );
defparam Uadd_3_lut_l_2_n_0_n.IN_WIDTH = 24;
defparam Uadd_3_lut_l_2_n_0_n.PIPE_DEPTH = 3;
wire [24:0] tree_3_pp_l_2_n_1_n;
sadd_lpm_cen Uadd_3_lut_l_2_n_1_n (.clk(clk), .gclk_en(clk_en), .ain(tree_3_pp_l_1_n_2_n), .bin(24'd0), .res(tree_3_pp_l_2_n_1_n) );
defparam Uadd_3_lut_l_2_n_1_n.IN_WIDTH = 24;
defparam Uadd_3_lut_l_2_n_1_n.PIPE_DEPTH = 3;
wire [25:0] tree_3_pp_l_3_n_0_n;
sadd_lpm_cen Uadd_3_lut_l_3_n_0_n (.clk(clk), .gclk_en(clk_en), .ain(tree_3_pp_l_2_n_0_n), .bin(tree_3_pp_l_2_n_1_n), .res(tree_3_pp_l_3_n_0_n) );
defparam Uadd_3_lut_l_3_n_0_n.IN_WIDTH = 25;
defparam Uadd_3_lut_l_3_n_0_n.PIPE_DEPTH = 3;
wire [25:0] lut_val_3_n;
assign lut_val_3_n=tree_3_pp_l_3_n_0_n;
// ---- final adder tree ----
wire [26:0] fin_atree_l_0_n_0_n;
sadd_lpm_cen Uadd_cen_l_0_n_0_n (.clk(clk), .gclk_en(clk_en), .ain(lut_val_0_n), .bin(lut_val_1_n), .res(fin_atree_l_0_n_0_n) );
defparam Uadd_cen_l_0_n_0_n.IN_WIDTH = 26;
defparam Uadd_cen_l_0_n_0_n.PIPE_DEPTH = 3;
wire [26:0] fin_atree_l_0_n_1_n;
sadd_lpm_cen Uadd_cen_l_0_n_1_n (.clk(clk), .gclk_en(clk_en), .ain(lut_val_2_n), .bin(lut_val_3_n), .res(fin_atree_l_0_n_1_n) );
defparam Uadd_cen_l_0_n_1_n.IN_WIDTH = 26;
defparam Uadd_cen_l_0_n_1_n.PIPE_DEPTH = 3;
wire [27:0] fin_atree_l_1_n_0_n;
sadd_lpm_cen Uadd_cen_l_1_n_0_n (.clk(clk), .gclk_en(clk_en), .ain(fin_atree_l_0_n_0_n), .bin(fin_atree_l_0_n_1_n), .res(fin_atree_l_1_n_0_n) );
defparam Uadd_cen_l_1_n_0_n.IN_WIDTH = 27;
defparam Uadd_cen_l_1_n_0_n.PIPE_DEPTH = 3;
wire [27:0] mac_res;
assign mac_res=fin_atree_l_1_n_0_n;
wire [27:0] atree_res;
mac_tl Umtl (.clk(clk),
.data_in(mac_res),
.data_out(atree_res));
defparam Umtl.DATA_WIDTH = 28;
// ---- Adder Tree Complete ----
wire [23:0] fir_int_res;
assign fir_int_res = atree_res [23:0];
// ---- Limiting Precision ----
wire [23:0]fir_int_res_fill;
assign fir_int_res_fill = fir_int_res[23 :0];
parameter TOT_WIDTH = ACCUM_WIDTH;
assign fir_result = fir_int_res_fill[TOT_WIDTH-MSB_RM-1:LSB_RM];
wire pre_rdy;
assign rdy_to_ld = pre_rdy;
assign done = done_int;
par_ctrl Uctrl(.rst(rst),
.clk(clk),
.clk_en(clk_en),
.done(done_int),
.rdy_int(rdy_int),
.rdy_to_ld(pre_rdy));
defparam Uctrl.REG_LEN = 21;
defparam Uctrl.REG_BIT = 5;
defparam Uctrl.CH_WIDTH =0;
defparam Uctrl.NUM_CH =1;
endmodule
|
// -*- Mode: Verilog -*-
// Filename : wb_riscv_soc_top.v
// Description : Wishbone RiscV SoC Top Level
// Author : Philip Tracton
// Created On : Tue Dec 6 21:14:31 2016
// Last Modified By: Philip Tracton
// Last Modified On: Tue Dec 6 21:14:31 2016
// Update Count : 0
// Status : Unknown, Use with caution!
module wb_riscv_soc_top (/*AUTOARG*/
// Outputs
tx_i,
// Inputs
clk_i, rst_i, rx_i
) ;
parameter ROM_FILE = "";
input clk_i;
input rst_i;
input rx_i;
output tx_i;
//
// Wires
//
wire wb_clk_i;
wire wb_rst_i;
wire wb_clk = wb_clk_i;
wire wb_rst = wb_rst_i;
`include "bus_matrix.vh"
//
// Clock and Reset Control
//
system_controller sys_con(
// Outputs
.wb_clk_o(wb_clk_i),
.wb_rst_o(wb_rst_i),
// Inputs
.clk_i(clk_i),
.rst_i(rst_i)
) ;
//
// Wishbone RiscV VScale CPU
//
wire [23:0] interrupts = 'b0;
// assign wb_s2m_dwmb_err = 0;
//assign wb_s2m_iwmb_err = 0;
wb_vscale riscv_cpu(
.clk(wb_clk_i),
.rst(wb_rst_i),
.ext_interrupts(interrupts),
.iwbm_adr_o(wb_m2s_iwmb_adr),
.iwbm_stb_o(wb_m2s_iwmb_stb),
.iwbm_cyc_o(wb_m2s_iwmb_cyc),
.iwbm_sel_o(wb_m2s_iwmb_sel),
.iwbm_we_o (wb_m2s_iwmb_we),
.iwbm_cti_o(wb_m2s_iwmb_cti),
.iwbm_bte_o(wb_m2s_iwmb_bte),
.iwbm_dat_o(wb_m2s_iwmb_dat),
.iwbm_err_i(wb_s2m_iwmb_err),
.iwbm_ack_i(wb_s2m_iwmb_ack),
.iwbm_dat_i(wb_s2m_iwmb_dat),
.iwbm_rty_i(wb_s2m_iwmb_rty),
.dwbm_adr_o(wb_m2s_dwmb_adr),
.dwbm_stb_o(wb_m2s_dwmb_stb),
.dwbm_cyc_o(wb_m2s_dwmb_cyc),
.dwbm_sel_o(wb_m2s_dwmb_sel),
.dwbm_we_o (wb_m2s_dwmb_we),
.dwbm_cti_o(wb_m2s_dwmb_cti),
.dwbm_bte_o(wb_m2s_dwmb_bte),
.dwbm_dat_o(wb_m2s_dwmb_dat),
.dwbm_err_i(wb_s2m_dwmb_err),
.dwbm_ack_i(wb_s2m_dwmb_ack),
.dwbm_dat_i(wb_s2m_dwmb_dat),
.dwbm_rty_i(wb_s2m_dwmb_rty)
);
//
// System RAM
//
`include "verilog_utils.vh"
assign wb_s2m_ram_rty = 0;
wb_ram #(.depth(1024)) ram(
.wb_clk_i(wb_clk_i),
.wb_rst_i(wb_rst_i),
.wb_adr_i(wb_m2s_ram_adr),
.wb_dat_i(wb_m2s_ram_dat),
.wb_sel_i(wb_m2s_ram_sel),
.wb_we_i(wb_m2s_ram_we),
.wb_bte_i(wb_m2s_ram_bte),
.wb_cti_i(wb_m2s_ram_cti),
.wb_cyc_i(wb_m2s_ram_cyc),
.wb_stb_i(wb_m2s_ram_stb),
.wb_ack_o(wb_s2m_ram_ack),
.wb_err_o(wb_s2m_ram_err),
.wb_dat_o(wb_s2m_ram_dat)
);
//
// System ROM
//
assign wb_s2m_rom_rty = 0;
wb_ram #( .depth(4096)) rom(
.wb_clk_i(wb_clk_i),
.wb_rst_i(wb_rst_i),
.wb_adr_i(wb_m2s_rom_adr),
.wb_dat_i(wb_m2s_rom_dat),
.wb_sel_i(wb_m2s_rom_sel),
.wb_we_i(wb_m2s_rom_we),
.wb_bte_i(wb_m2s_rom_bte),
.wb_cti_i(wb_m2s_rom_cti),
.wb_cyc_i(wb_m2s_rom_cyc),
.wb_stb_i(wb_m2s_rom_stb),
.wb_ack_o(wb_s2m_rom_ack),
.wb_err_o(wb_s2m_rom_err),
.wb_dat_o(wb_s2m_rom_dat)
);
//
// UART
//
assign wb_s2m_uart_err = 0;
assign wb_s2m_uart_rty = 0;
uart_wb uart(
.clk(wb_clk_i),
.wb_rst_i(wb_rst_i),
.wb_we_i(wb_m2s_uart_we),
.wb_stb_i(wb_m2s_uart_stb),
.wb_cyc_i(wb_m2s_uart_cyc),
.wb_ack_o(wb_s2m_uart_ack),
.wb_adr_i(wb_m2s_uart_adr),
.wb_adr_int(),
.wb_dat_i(wb_m2s_uart_dat),
.wb_dat_o(wb_s2m_uart_dat),
.wb_dat8_i(wb_m2s_uart_dat[7:0]),
.wb_dat8_o(),
.wb_dat32_o(),
.wb_sel_i(wb_m2s_uart_sel),
.we_o(),
.re_o() // Write and read enable output for the core
);
endmodule // wb_riscv_soc_top
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_dwidth_converter:2.1
// IP Revision: 8
(* X_CORE_INFO = "axi_dwidth_converter_v2_1_8_top,Vivado 2016.1" *)
(* CHECK_LICENSE_TYPE = "design_1_auto_us_1,axi_dwidth_converter_v2_1_8_top,{}" *)
(* CORE_GENERATION_INFO = "design_1_auto_us_1,axi_dwidth_converter_v2_1_8_top,{x_ipProduct=Vivado 2016.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_dwidth_converter,x_ipVersion=2.1,x_ipCoreRevision=8,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_AXI_PROTOCOL=0,C_S_AXI_ID_WIDTH=1,C_SUPPORTS_ID=0,C_AXI_ADDR_WIDTH=32,C_S_AXI_DATA_WIDTH=32,C_M_AXI_DATA_WIDTH=64,C_AXI_SUPPORTS_WRITE=1,C_AXI_SUPPORTS_READ=0,C_FIFO_MODE=0,C_S_AXI_ACLK_RATIO=1,C_M_AXI_ACLK_RATIO=2,C_AXI_IS_ACLK_ASYNC=0,C_MAX_SPLIT_BEATS=16,C_PACK\
ING_LEVEL=1,C_SYNCHRONIZER_STAGE=3}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_1_auto_us_1 (
s_axi_aclk,
s_axi_aresetn,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awregion,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awregion,
m_axi_awqos,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 SI_CLK CLK" *)
input wire s_axi_aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 SI_RST RST" *)
input wire s_axi_aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
input wire [7 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
input wire [2 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
input wire [1 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
input wire [0 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
input wire [3 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREGION" *)
input wire [3 : 0] s_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
input wire [3 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
input wire s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
output wire s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
input wire s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
input wire s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
output wire s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
output wire s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
input wire s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output wire [31 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *)
output wire [7 : 0] m_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *)
output wire [2 : 0] m_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *)
output wire [1 : 0] m_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *)
output wire [0 : 0] m_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *)
output wire [3 : 0] m_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREGION" *)
output wire [3 : 0] m_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *)
output wire [3 : 0] m_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output wire m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input wire m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [63 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
output wire [7 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *)
output wire m_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output wire m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input wire m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input wire m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output wire m_axi_bready;
axi_dwidth_converter_v2_1_8_top #(
.C_FAMILY("zynq"),
.C_AXI_PROTOCOL(0),
.C_S_AXI_ID_WIDTH(1),
.C_SUPPORTS_ID(0),
.C_AXI_ADDR_WIDTH(32),
.C_S_AXI_DATA_WIDTH(32),
.C_M_AXI_DATA_WIDTH(64),
.C_AXI_SUPPORTS_WRITE(1),
.C_AXI_SUPPORTS_READ(0),
.C_FIFO_MODE(0),
.C_S_AXI_ACLK_RATIO(1),
.C_M_AXI_ACLK_RATIO(2),
.C_AXI_IS_ACLK_ASYNC(0),
.C_MAX_SPLIT_BEATS(16),
.C_PACKING_LEVEL(1),
.C_SYNCHRONIZER_STAGE(3)
) inst (
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_awid(1'H0),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awregion(s_axi_awregion),
.s_axi_awqos(s_axi_awqos),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(),
.s_axi_bresp(s_axi_bresp),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(1'H0),
.s_axi_araddr(32'H00000000),
.s_axi_arlen(8'H00),
.s_axi_arsize(3'H0),
.s_axi_arburst(2'H1),
.s_axi_arlock(1'H0),
.s_axi_arcache(4'H0),
.s_axi_arprot(3'H0),
.s_axi_arregion(4'H0),
.s_axi_arqos(4'H0),
.s_axi_arvalid(1'H0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_rvalid(),
.s_axi_rready(1'H0),
.m_axi_aclk(1'H0),
.m_axi_aresetn(1'H0),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(m_axi_awlen),
.m_axi_awsize(m_axi_awsize),
.m_axi_awburst(m_axi_awburst),
.m_axi_awlock(m_axi_awlock),
.m_axi_awcache(m_axi_awcache),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(m_axi_awregion),
.m_axi_awqos(m_axi_awqos),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(m_axi_wlast),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bresp(m_axi_bresp),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_araddr(),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(),
.m_axi_arregion(),
.m_axi_arqos(),
.m_axi_arvalid(),
.m_axi_arready(1'H0),
.m_axi_rdata(64'H0000000000000000),
.m_axi_rresp(2'H0),
.m_axi_rlast(1'H1),
.m_axi_rvalid(1'H0),
.m_axi_rready()
);
endmodule
|
module ARM_CU_TestBench;
parameter sim_time = 750*2; // Num of Cycles * 2
wire [17:0] signals;
wire IR_CU, RFLOAD, PCLOAD, SRLOAD, SRENABLED, ALUSTORE, MFA, WORD_BYTE, READ_WRITE, IRLOAD, MBRLOAD, MBRSTORE, MARLOAD;
wire [4:0] opcode;
wire [3:0] CU;
reg [31:0] IR;
reg [3:0] SR;
reg MFC , Reset , Clk ;
//ControlUnit (output reg IR_CU, RFLOAD, PCLOAD, SRLOAD, SRENABLED, ALUSTORE, MFA, WORD_BYTE,READ_WRITE,IRLOAD,MBRLOAD,MBRSTORE,MARLOAD,output reg[4:0] opcode, output[3:0] CU, input MFC, Reset,Clk);
ControlUnit cu(IR_CU, RFLOAD, PCLOAD, SRLOAD, SRENABLED, ALUSTORE, MFA, WORD_BYTE, READ_WRITE, IRLOAD, MBRLOAD, MBRSTORE, MARLOAD,opcode,CU,MFC,Reset,Clk,IR,SR);
initial fork
MFC = 0; Reset=1 ; Clk=0 ;
#1 MFC = 1;#1 Reset=0 ;
join
always
#1 Clk = ~Clk;
initial #sim_time $finish;
initial begin
$dumpfile("ARM_CU_TestBench.vcd");
$dumpvars(0,ARM_CU_TestBench);
$display(" Test Results" );
$monitor("IR_CU=%d RFLOAD=%d PCLOAD=%d SRLOAD=%d SRENABLED=%d ALUSTORE=%d MFA=%d WORD_BYTE=%d READ_WRITE=%d IRLOAD=%d MBRLOAD=%d MBRSTORE=%d MARLOAD=%d opcode=%d CU=%d MFC=%d Reset=%d Clk=%d",IR_CU, RFLOAD, PCLOAD, SRLOAD, SRENABLED, ALUSTORE, MFA, WORD_BYTE,READ_WRITE,IRLOAD,MBRLOAD,MBRSTORE,MARLOAD, opcode, CU, MFC, Reset,Clk);
end
endmodule
//iverilog controlunit.v ARM_CU_TestBench.v
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DFXBP_BEHAVIORAL_V
`define SKY130_FD_SC_MS__DFXBP_BEHAVIORAL_V
/**
* dfxbp: Delay flop, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_ms__udp_dff_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ms__dfxbp (
Q ,
Q_N,
CLK,
D
);
// Module ports
output Q ;
output Q_N;
input CLK;
input D ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
reg notifier ;
wire D_delayed ;
wire CLK_delayed;
wire awake ;
// Name Output Other arguments
sky130_fd_sc_ms__udp_dff$P_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__DFXBP_BEHAVIORAL_V
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sat Nov 19 19:35:58 2016
/////////////////////////////////////////////////////////////
module FPU_PIPELINED_FPADDSUB_W32_EW8_SW23_SWR26_EWR5 ( clk, rst, beg_OP,
Data_X, Data_Y, add_subt, busy, overflow_flag, underflow_flag,
zero_flag, ready, final_result_ieee );
input [31:0] Data_X;
input [31:0] Data_Y;
output [31:0] final_result_ieee;
input clk, rst, beg_OP, add_subt;
output busy, overflow_flag, underflow_flag, zero_flag, ready;
wire n1801, Shift_reg_FLAGS_7_6, intAS, SIGN_FLAG_EXP, OP_FLAG_EXP,
ZERO_FLAG_EXP, SIGN_FLAG_SHT1, OP_FLAG_SHT1, ZERO_FLAG_SHT1,
left_right_SHT2, SIGN_FLAG_SHT2, OP_FLAG_SHT2, ZERO_FLAG_SHT2,
SIGN_FLAG_SHT1SHT2, ZERO_FLAG_SHT1SHT2, SIGN_FLAG_NRM, ZERO_FLAG_NRM,
SIGN_FLAG_SFG, OP_FLAG_SFG, ZERO_FLAG_SFG,
inst_FSM_INPUT_ENABLE_state_next_1_, n463, n464, n465, n466, n467,
n468, n469, n470, n471, n472, n473, n474, n475, n476, n477, n478,
n479, n480, n481, n482, n483, n484, n485, n486, n487, n488, n489,
n490, n491, n492, n493, n494, n495, n496, n497, n498, n499, n500,
n501, n502, n503, n504, n505, n506, n507, n508, n509, n510, n511,
n512, n513, n514, n515, n516, n517, n518, n519, n520, n521, n522,
n523, n524, n525, n526, n527, n528, n529, n530, n531, n532, n533,
n534, n535, n536, n537, n538, n539, n540, n541, n542, n543, n544,
n545, n546, n547, n548, n549, n551, n552, n553, n554, n555, n556,
n557, n558, n559, n560, n561, n562, n563, n564, n565, n566, n567,
n568, n569, n570, n571, n572, n573, n574, n575, n576, n577, n578,
n579, n580, n581, n582, n583, n584, n585, n586, n587, n588, n589,
n590, n591, n592, n593, n594, n595, n596, n597, n598, n599, n600,
n601, n602, n603, n604, n605, n606, n607, n608, n609, n610, n611,
n612, n613, n614, n615, n616, n617, n618, n619, n620, n621, n622,
n623, n624, n625, n626, n627, n628, n629, n630, n631, n632, n633,
n634, n635, n636, n637, n638, n639, n640, n641, n642, n643, n644,
n645, n646, n647, n648, n649, n650, n651, n652, n653, n654, n655,
n656, n657, n658, n659, n660, n661, n662, n663, n664, n665, n666,
n667, n668, n669, n670, n671, n672, n673, n674, n675, n676, n677,
n678, n679, n680, n681, n682, n683, n684, n685, n686, n687, n688,
n689, n690, n691, n692, n693, n694, n695, n696, n697, n698, n699,
n700, n701, n702, n703, n704, n705, n706, n707, n708, n709, n710,
n711, n712, n713, n714, n715, n716, n717, n718, n719, n720, n721,
n722, n723, n724, n725, n726, n727, n728, n729, n730, n731, n732,
n733, n734, n735, n736, n737, n738, n739, n740, n741, n742, n743,
n744, n745, n746, n747, n748, n749, n750, n751, n752, n753, n754,
n755, n756, n757, n758, n759, n760, n761, n762, n763, n764, n765,
n766, n767, n769, n770, n771, n772, n773, n774, n775, n776, n777,
n778, n779, n780, n781, n782, n783, n784, n785, n786, n787, n788,
n789, n790, n791, n792, n793, n794, n795, n796, n797, n798, n799,
n800, n801, n802, n803, n804, n805, n806, n807, n808, n809, n810,
n811, n812, n813, n814, n815, n816, n817, n818, n819, n820, n821,
n822, n823, n824, n825, n826, n827, n828, n829, n830, n831, n832,
n833, n834, n835, n836, n837, n838, n839, n840, n841, n842, n843,
n844, n845, n846, n847, n848, n849, n850, n851, n852, n853, n854,
n855, n856, n857, n858, n859, n860, n861, n862, n863, n864, n865,
n866, n867, n868, n869, n870, n871, DP_OP_15J43_123_3594_n8,
DP_OP_15J43_123_3594_n7, DP_OP_15J43_123_3594_n6,
DP_OP_15J43_123_3594_n5, DP_OP_15J43_123_3594_n4, n873, n874, n875,
n876, n877, n878, n879, n880, n881, n882, n883, n884, n885, n886,
n887, n888, n889, n890, n891, n892, n893, n894, n895, n896, n897,
n898, n899, n900, n901, n902, n903, n904, n905, n906, n907, n908,
n909, n910, n911, n912, n913, n914, n915, n916, n917, n918, n919,
n920, n921, n922, n923, n924, n925, n926, n927, n928, n929, n930,
n931, n932, n933, n934, n935, n936, n937, n938, n939, n940, n941,
n942, n943, n944, n945, n946, n947, n948, n949, n950, n951, n952,
n953, n954, n955, n956, n957, n958, n959, n960, n961, n962, n963,
n964, n965, n966, n967, n968, n969, n970, n971, n972, n973, n974,
n975, n976, n977, n978, n979, n980, n981, n982, n983, n984, n985,
n986, n987, n988, n989, n990, n991, n992, n993, n994, n995, n996,
n997, n998, n999, n1000, n1001, n1002, n1003, n1004, n1005, n1006,
n1007, n1008, n1009, n1010, n1011, n1012, n1013, n1014, n1015, n1016,
n1017, n1018, n1019, n1020, n1021, n1022, n1023, n1024, n1025, n1026,
n1027, n1028, n1029, n1030, n1031, n1032, n1033, n1034, n1035, n1036,
n1037, n1038, n1039, n1040, n1041, n1042, n1043, n1044, n1045, n1046,
n1047, n1048, n1049, n1050, n1051, n1052, n1053, n1054, n1055, n1056,
n1057, n1058, n1059, n1060, n1061, n1062, n1063, n1064, n1065, n1066,
n1067, n1068, n1069, n1070, n1071, n1072, n1073, n1074, n1075, n1076,
n1077, n1078, n1079, n1080, n1081, n1082, n1083, n1084, n1085, n1086,
n1087, n1088, n1089, n1090, n1091, n1092, n1093, n1094, n1095, n1096,
n1097, n1098, n1099, n1100, n1101, n1102, n1103, n1104, n1105, n1106,
n1107, n1108, n1109, n1110, n1111, n1112, n1113, n1114, n1115, n1116,
n1117, n1118, n1119, n1120, n1121, n1122, n1123, n1124, n1125, n1126,
n1127, n1128, n1129, n1130, n1131, n1132, n1133, n1134, n1135, n1136,
n1137, n1138, n1139, n1140, n1141, n1142, n1143, n1144, n1145, n1146,
n1147, n1148, n1149, n1150, n1151, n1152, n1153, n1154, n1155, n1156,
n1157, n1158, n1159, n1160, n1161, n1162, n1163, n1164, n1165, n1166,
n1167, n1168, n1169, n1170, n1171, n1172, n1173, n1174, n1175, n1176,
n1177, n1178, n1179, n1180, n1181, n1182, n1183, n1184, n1185, n1186,
n1187, n1188, n1189, n1190, n1191, n1192, n1193, n1194, n1195, n1196,
n1197, n1198, n1199, n1200, n1201, n1202, n1203, n1204, n1205, n1206,
n1207, n1208, n1209, n1210, n1211, n1212, n1213, n1214, n1215, n1216,
n1217, n1218, n1219, n1220, n1221, n1222, n1223, n1224, n1225, n1226,
n1227, n1228, n1229, n1230, n1231, n1232, n1233, n1234, n1235, n1236,
n1237, n1238, n1239, n1240, n1241, n1242, n1243, n1244, n1245, n1246,
n1247, n1248, n1249, n1250, n1251, n1252, n1253, n1254, n1255, n1256,
n1257, n1258, n1259, n1260, n1261, n1262, n1263, n1264, n1265, n1266,
n1267, n1268, n1269, n1270, n1271, n1273, n1274, n1275, n1276, n1277,
n1278, n1279, n1280, n1281, n1282, n1283, n1284, n1285, n1286, n1287,
n1288, n1289, n1290, n1291, n1292, n1293, n1294, n1295, n1296, n1297,
n1298, n1299, n1300, n1301, n1302, n1303, n1304, n1305, n1306, n1307,
n1308, n1309, n1310, n1311, n1312, n1313, n1314, n1315, n1316, n1317,
n1318, n1319, n1320, n1321, n1322, n1323, n1324, n1325, n1326, n1327,
n1328, n1329, n1330, n1331, n1332, n1333, n1334, n1335, n1336, n1337,
n1338, n1339, n1340, n1341, n1342, n1343, n1344, n1345, n1346, n1347,
n1348, n1349, n1350, n1351, n1352, n1353, n1354, n1355, n1356, n1357,
n1358, n1359, n1360, n1361, n1362, n1363, n1364, n1365, n1366, n1367,
n1368, n1369, n1370, n1371, n1372, n1373, n1374, n1375, n1376, n1377,
n1378, n1379, n1380, n1381, n1382, n1383, n1384, n1385, n1386, n1387,
n1388, n1389, n1390, n1391, n1392, n1393, n1394, n1395, n1396, n1397,
n1398, n1399, n1400, n1401, n1402, n1403, n1404, n1405, n1406, n1407,
n1408, n1409, n1410, n1411, n1412, n1413, n1414, n1415, n1416, n1417,
n1418, n1419, n1420, n1421, n1422, n1423, n1424, n1425, n1426, n1427,
n1428, n1429, n1430, n1431, n1432, n1433, n1434, n1435, n1436, n1437,
n1438, n1439, n1440, n1441, n1442, n1443, n1444, n1445, n1446, n1447,
n1448, n1449, n1450, n1451, n1452, n1453, n1454, n1455, n1456, n1457,
n1458, n1459, n1460, n1461, n1462, n1463, n1464, n1465, n1466, n1467,
n1468, n1469, n1470, n1471, n1472, n1473, n1474, n1475, n1476, n1477,
n1478, n1479, n1480, n1481, n1482, n1483, n1484, n1485, n1486, n1487,
n1488, n1489, n1490, n1491, n1492, n1493, n1494, n1495, n1496, n1497,
n1498, n1500, n1501, n1502, n1503, n1504, n1505, n1506, n1507, n1508,
n1509, n1510, n1511, n1512, n1513, n1514, n1515, n1516, n1517, n1518,
n1519, n1520, n1521, n1522, n1523, n1524, n1525, n1526, n1527, n1528,
n1529, n1530, n1531, n1532, n1533, n1534, n1535, n1536, n1537, n1538,
n1539, n1540, n1541, n1542, n1543, n1544, n1545, n1546, n1547, n1548,
n1549, n1550, n1551, n1552, n1553, n1554, n1555, n1556, n1557, n1558,
n1559, n1560, n1561, n1562, n1563, n1564, n1565, n1566, n1567, n1568,
n1569, n1570, n1571, n1572, n1573, n1574, n1575, n1576, n1577, n1578,
n1579, n1580, n1581, n1582, n1583, n1584, n1585, n1586, n1587, n1588,
n1589, n1590, n1591, n1592, n1593, n1594, n1595, n1596, n1597, n1598,
n1599, n1600, n1601, n1602, n1603, n1604, n1605, n1606, n1607, n1608,
n1609, n1610, n1611, n1612, n1613, n1614, n1615, n1616, n1617, n1618,
n1619, n1620, n1621, n1622, n1623, n1624, n1625, n1626, n1627, n1628,
n1629, n1630, n1631, n1632, n1633, n1634, n1635, n1636, n1637, n1638,
n1639, n1640, n1641, n1642, n1643, n1644, n1645, n1646, n1647, n1648,
n1649, n1650, n1651, n1652, n1653, n1654, n1655, n1656, n1657, n1658,
n1659, n1660, n1661, n1662, n1663, n1664, n1665, n1666, n1667, n1668,
n1669, n1670, n1671, n1672, n1673, n1674, n1675, n1676, n1677, n1678,
n1679, n1680, n1681, n1682, n1683, n1684, n1685, n1686, n1687, n1688,
n1689, n1690, n1691, n1692, n1693, n1694, n1695, n1696, n1697, n1698,
n1699, n1700, n1701, n1702, n1703, n1704, n1705, n1706, n1707, n1708,
n1709, n1710, n1711, n1712, n1713, n1714, n1715, n1716, n1717, n1718,
n1719, n1720, n1721, n1722, n1723, n1724, n1725, n1726, n1727, n1728,
n1729, n1730, n1731, n1732, n1733, n1734, n1735, n1736, n1737, n1738,
n1739, n1740, n1741, n1742, n1743, n1744, n1745, n1746, n1747, n1748,
n1749, n1750, n1751, n1752, n1753, n1754, n1755, n1756, n1757, n1758,
n1759, n1760, n1761, n1762, n1763, n1764, n1765, n1766, n1767, n1768,
n1769, n1770, n1771, n1772, n1773, n1774, n1775, n1776, n1777, n1778,
n1779, n1780, n1781, n1782, n1783, n1784, n1785, n1786, n1787, n1788,
n1789, n1790, n1791, n1792, n1793, n1794, n1795, n1796, n1797, n1798,
n1800;
wire [3:0] Shift_reg_FLAGS_7;
wire [31:0] intDX_EWSW;
wire [31:0] intDY_EWSW;
wire [30:0] DMP_EXP_EWSW;
wire [27:0] DmP_EXP_EWSW;
wire [30:0] DMP_SHT1_EWSW;
wire [22:0] DmP_mant_SHT1_SW;
wire [4:0] Shift_amount_SHT1_EWR;
wire [25:0] Raw_mant_NRM_SWR;
wire [25:0] Data_array_SWR;
wire [30:0] DMP_SHT2_EWSW;
wire [4:2] shift_value_SHT2_EWR;
wire [7:0] DMP_exp_NRM2_EW;
wire [7:0] DMP_exp_NRM_EW;
wire [4:0] LZD_output_NRM2_EW;
wire [4:1] exp_rslt_NRM2_EW1;
wire [30:0] DMP_SFG;
wire [25:0] DmP_mant_SFG_SWR;
wire [2:0] inst_FSM_INPUT_ENABLE_state_reg;
DFFRXLTS INPUT_STAGE_FLAGS_Q_reg_0_ ( .D(n830), .CK(clk), .RN(n1762), .Q(
intAS) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_2_ ( .D(n764), .CK(clk), .RN(n1768),
.Q(Shift_amount_SHT1_EWR[2]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_3_ ( .D(n763), .CK(clk), .RN(n1768),
.Q(Shift_amount_SHT1_EWR[3]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_4_ ( .D(n762), .CK(clk), .RN(n1768),
.Q(Shift_amount_SHT1_EWR[4]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_0_ ( .D(n753), .CK(clk), .RN(n1771), .Q(
DMP_EXP_EWSW[0]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_1_ ( .D(n752), .CK(clk), .RN(n1068), .Q(
DMP_EXP_EWSW[1]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_2_ ( .D(n751), .CK(clk), .RN(n1770), .Q(
DMP_EXP_EWSW[2]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_3_ ( .D(n750), .CK(clk), .RN(n1769), .Q(
DMP_EXP_EWSW[3]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_4_ ( .D(n749), .CK(clk), .RN(n1071), .Q(
DMP_EXP_EWSW[4]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_5_ ( .D(n748), .CK(clk), .RN(n1070), .Q(
DMP_EXP_EWSW[5]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_6_ ( .D(n747), .CK(clk), .RN(n1068), .Q(
DMP_EXP_EWSW[6]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_7_ ( .D(n746), .CK(clk), .RN(n1072), .Q(
DMP_EXP_EWSW[7]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_8_ ( .D(n745), .CK(clk), .RN(n1774), .Q(
DMP_EXP_EWSW[8]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_9_ ( .D(n744), .CK(clk), .RN(n1773), .Q(
DMP_EXP_EWSW[9]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_10_ ( .D(n743), .CK(clk), .RN(n1771), .Q(
DMP_EXP_EWSW[10]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_11_ ( .D(n742), .CK(clk), .RN(n1069), .Q(
DMP_EXP_EWSW[11]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_12_ ( .D(n741), .CK(clk), .RN(n1770), .Q(
DMP_EXP_EWSW[12]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_13_ ( .D(n740), .CK(clk), .RN(n1769), .Q(
DMP_EXP_EWSW[13]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_14_ ( .D(n739), .CK(clk), .RN(n1071), .Q(
DMP_EXP_EWSW[14]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_15_ ( .D(n738), .CK(clk), .RN(n1070), .Q(
DMP_EXP_EWSW[15]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_16_ ( .D(n737), .CK(clk), .RN(n1068), .Q(
DMP_EXP_EWSW[16]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_17_ ( .D(n736), .CK(clk), .RN(n1072), .Q(
DMP_EXP_EWSW[17]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_18_ ( .D(n735), .CK(clk), .RN(n1774), .Q(
DMP_EXP_EWSW[18]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_19_ ( .D(n734), .CK(clk), .RN(n1773), .Q(
DMP_EXP_EWSW[19]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_20_ ( .D(n733), .CK(clk), .RN(n1771), .Q(
DMP_EXP_EWSW[20]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_21_ ( .D(n732), .CK(clk), .RN(n1070), .Q(
DMP_EXP_EWSW[21]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_22_ ( .D(n731), .CK(clk), .RN(n1770), .Q(
DMP_EXP_EWSW[22]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_28_ ( .D(n725), .CK(clk), .RN(n1769), .Q(
DMP_EXP_EWSW[28]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_29_ ( .D(n724), .CK(clk), .RN(n1071), .Q(
DMP_EXP_EWSW[29]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_30_ ( .D(n723), .CK(clk), .RN(n1772), .Q(
DMP_EXP_EWSW[30]) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_1_ ( .D(n722), .CK(clk), .RN(n1772), .Q(
OP_FLAG_EXP) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_0_ ( .D(n721), .CK(clk), .RN(n1772), .Q(
ZERO_FLAG_EXP) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_2_ ( .D(n720), .CK(clk), .RN(n1772), .Q(
SIGN_FLAG_EXP) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_0_ ( .D(n719), .CK(clk), .RN(n1772), .Q(
DMP_SHT1_EWSW[0]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_0_ ( .D(n718), .CK(clk), .RN(n1772), .Q(
DMP_SHT2_EWSW[0]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_1_ ( .D(n716), .CK(clk), .RN(n1772), .Q(
DMP_SHT1_EWSW[1]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_1_ ( .D(n715), .CK(clk), .RN(n1772), .Q(
DMP_SHT2_EWSW[1]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_2_ ( .D(n713), .CK(clk), .RN(n1070), .Q(
DMP_SHT1_EWSW[2]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_2_ ( .D(n712), .CK(clk), .RN(n1068), .Q(
DMP_SHT2_EWSW[2]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_3_ ( .D(n710), .CK(clk), .RN(n1072), .Q(
DMP_SHT1_EWSW[3]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_3_ ( .D(n709), .CK(clk), .RN(n1774), .Q(
DMP_SHT2_EWSW[3]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_4_ ( .D(n707), .CK(clk), .RN(n1773), .Q(
DMP_SHT1_EWSW[4]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_4_ ( .D(n706), .CK(clk), .RN(n1771), .Q(
DMP_SHT2_EWSW[4]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_5_ ( .D(n704), .CK(clk), .RN(n1770), .Q(
DMP_SHT1_EWSW[5]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_5_ ( .D(n703), .CK(clk), .RN(n1769), .Q(
DMP_SHT2_EWSW[5]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_6_ ( .D(n701), .CK(clk), .RN(n1071), .Q(
DMP_SHT1_EWSW[6]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_6_ ( .D(n700), .CK(clk), .RN(n1070), .Q(
DMP_SHT2_EWSW[6]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_7_ ( .D(n698), .CK(clk), .RN(n1068), .Q(
DMP_SHT1_EWSW[7]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_7_ ( .D(n697), .CK(clk), .RN(n1072), .Q(
DMP_SHT2_EWSW[7]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_8_ ( .D(n695), .CK(clk), .RN(n1774), .Q(
DMP_SHT1_EWSW[8]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_8_ ( .D(n694), .CK(clk), .RN(n1773), .Q(
DMP_SHT2_EWSW[8]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_9_ ( .D(n692), .CK(clk), .RN(n1775), .Q(
DMP_SHT1_EWSW[9]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_9_ ( .D(n691), .CK(clk), .RN(n1775), .Q(
DMP_SHT2_EWSW[9]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_10_ ( .D(n689), .CK(clk), .RN(n1775), .Q(
DMP_SHT1_EWSW[10]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_10_ ( .D(n688), .CK(clk), .RN(n1775), .Q(
DMP_SHT2_EWSW[10]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_11_ ( .D(n686), .CK(clk), .RN(n1775), .Q(
DMP_SHT1_EWSW[11]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_11_ ( .D(n685), .CK(clk), .RN(n1775), .Q(
DMP_SHT2_EWSW[11]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_12_ ( .D(n683), .CK(clk), .RN(n1775), .Q(
DMP_SHT1_EWSW[12]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_12_ ( .D(n682), .CK(clk), .RN(n1775), .Q(
DMP_SHT2_EWSW[12]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_13_ ( .D(n680), .CK(clk), .RN(n1775), .Q(
DMP_SHT1_EWSW[13]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_13_ ( .D(n679), .CK(clk), .RN(n1775), .Q(
DMP_SHT2_EWSW[13]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_14_ ( .D(n677), .CK(clk), .RN(n1776), .Q(
DMP_SHT1_EWSW[14]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_14_ ( .D(n676), .CK(clk), .RN(n1776), .Q(
DMP_SHT2_EWSW[14]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_15_ ( .D(n674), .CK(clk), .RN(n1776), .Q(
DMP_SHT1_EWSW[15]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_15_ ( .D(n673), .CK(clk), .RN(n1776), .Q(
DMP_SHT2_EWSW[15]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_16_ ( .D(n671), .CK(clk), .RN(n1776), .Q(
DMP_SHT1_EWSW[16]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_16_ ( .D(n670), .CK(clk), .RN(n1776), .Q(
DMP_SHT2_EWSW[16]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_17_ ( .D(n668), .CK(clk), .RN(n1776), .Q(
DMP_SHT1_EWSW[17]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_17_ ( .D(n667), .CK(clk), .RN(n1776), .Q(
DMP_SHT2_EWSW[17]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_18_ ( .D(n665), .CK(clk), .RN(n1776), .Q(
DMP_SHT1_EWSW[18]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_18_ ( .D(n664), .CK(clk), .RN(n1776), .Q(
DMP_SHT2_EWSW[18]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_19_ ( .D(n662), .CK(clk), .RN(n1777), .Q(
DMP_SHT1_EWSW[19]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_19_ ( .D(n661), .CK(clk), .RN(n1777), .Q(
DMP_SHT2_EWSW[19]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_20_ ( .D(n659), .CK(clk), .RN(n1777), .Q(
DMP_SHT1_EWSW[20]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_20_ ( .D(n658), .CK(clk), .RN(n1777), .Q(
DMP_SHT2_EWSW[20]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_21_ ( .D(n656), .CK(clk), .RN(n1777), .Q(
DMP_SHT1_EWSW[21]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_21_ ( .D(n655), .CK(clk), .RN(n1777), .Q(
DMP_SHT2_EWSW[21]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_22_ ( .D(n653), .CK(clk), .RN(n1777), .Q(
DMP_SHT1_EWSW[22]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_22_ ( .D(n652), .CK(clk), .RN(n1777), .Q(
DMP_SHT2_EWSW[22]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_23_ ( .D(n650), .CK(clk), .RN(n1777), .Q(
DMP_SHT1_EWSW[23]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_23_ ( .D(n649), .CK(clk), .RN(n1777), .Q(
DMP_SHT2_EWSW[23]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_23_ ( .D(n648), .CK(clk), .RN(n1778), .Q(
DMP_SFG[23]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_0_ ( .D(n647), .CK(clk), .RN(n1778), .Q(
DMP_exp_NRM_EW[0]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_24_ ( .D(n645), .CK(clk), .RN(n1778), .Q(
DMP_SHT1_EWSW[24]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_24_ ( .D(n644), .CK(clk), .RN(n1778), .Q(
DMP_SHT2_EWSW[24]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_24_ ( .D(n643), .CK(clk), .RN(n1778), .Q(
DMP_SFG[24]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_1_ ( .D(n642), .CK(clk), .RN(n1778), .Q(
DMP_exp_NRM_EW[1]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_25_ ( .D(n640), .CK(clk), .RN(n1778), .Q(
DMP_SHT1_EWSW[25]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_25_ ( .D(n639), .CK(clk), .RN(n1778), .Q(
DMP_SHT2_EWSW[25]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_25_ ( .D(n638), .CK(clk), .RN(n1778), .Q(
DMP_SFG[25]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_2_ ( .D(n637), .CK(clk), .RN(n1778), .Q(
DMP_exp_NRM_EW[2]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_26_ ( .D(n635), .CK(clk), .RN(n1779), .Q(
DMP_SHT1_EWSW[26]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_26_ ( .D(n634), .CK(clk), .RN(n1779), .Q(
DMP_SHT2_EWSW[26]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_26_ ( .D(n633), .CK(clk), .RN(n1779), .Q(
DMP_SFG[26]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_3_ ( .D(n632), .CK(clk), .RN(n1779), .Q(
DMP_exp_NRM_EW[3]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_27_ ( .D(n630), .CK(clk), .RN(n1779), .Q(
DMP_SHT1_EWSW[27]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_27_ ( .D(n629), .CK(clk), .RN(n1779), .Q(
DMP_SHT2_EWSW[27]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_27_ ( .D(n628), .CK(clk), .RN(n1779), .Q(
DMP_SFG[27]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_4_ ( .D(n627), .CK(clk), .RN(n1779), .Q(
DMP_exp_NRM_EW[4]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_28_ ( .D(n625), .CK(clk), .RN(n1779), .Q(
DMP_SHT1_EWSW[28]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_28_ ( .D(n624), .CK(clk), .RN(n1779), .Q(
DMP_SHT2_EWSW[28]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_28_ ( .D(n623), .CK(clk), .RN(n1780), .Q(
DMP_SFG[28]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_5_ ( .D(n622), .CK(clk), .RN(n1780), .Q(
DMP_exp_NRM_EW[5]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_29_ ( .D(n620), .CK(clk), .RN(n1780), .Q(
DMP_SHT1_EWSW[29]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_29_ ( .D(n619), .CK(clk), .RN(n1780), .Q(
DMP_SHT2_EWSW[29]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_29_ ( .D(n618), .CK(clk), .RN(n1780), .Q(
DMP_SFG[29]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_6_ ( .D(n617), .CK(clk), .RN(n1780), .Q(
DMP_exp_NRM_EW[6]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_30_ ( .D(n615), .CK(clk), .RN(n1780), .Q(
DMP_SHT1_EWSW[30]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_30_ ( .D(n614), .CK(clk), .RN(n1780), .Q(
DMP_SHT2_EWSW[30]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_30_ ( .D(n613), .CK(clk), .RN(n1780), .Q(
DMP_SFG[30]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_7_ ( .D(n612), .CK(clk), .RN(n1780), .Q(
DMP_exp_NRM_EW[7]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_0_ ( .D(n610), .CK(clk), .RN(n1781), .Q(
DmP_EXP_EWSW[0]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_1_ ( .D(n608), .CK(clk), .RN(n1781), .Q(
DmP_EXP_EWSW[1]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_2_ ( .D(n606), .CK(clk), .RN(n1781), .Q(
DmP_EXP_EWSW[2]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_3_ ( .D(n604), .CK(clk), .RN(n1781), .Q(
DmP_EXP_EWSW[3]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_4_ ( .D(n602), .CK(clk), .RN(n1781), .Q(
DmP_EXP_EWSW[4]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_5_ ( .D(n600), .CK(clk), .RN(n1782), .Q(
DmP_EXP_EWSW[5]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_6_ ( .D(n598), .CK(clk), .RN(n1782), .Q(
DmP_EXP_EWSW[6]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_7_ ( .D(n596), .CK(clk), .RN(n1782), .Q(
DmP_EXP_EWSW[7]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_8_ ( .D(n594), .CK(clk), .RN(n1782), .Q(
DmP_EXP_EWSW[8]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_9_ ( .D(n592), .CK(clk), .RN(n1782), .Q(
DmP_EXP_EWSW[9]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_10_ ( .D(n590), .CK(clk), .RN(n1783), .Q(
DmP_EXP_EWSW[10]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_11_ ( .D(n588), .CK(clk), .RN(n1783), .Q(
DmP_EXP_EWSW[11]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_12_ ( .D(n586), .CK(clk), .RN(n1783), .Q(
DmP_EXP_EWSW[12]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_13_ ( .D(n584), .CK(clk), .RN(n1783), .Q(
DmP_EXP_EWSW[13]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_14_ ( .D(n582), .CK(clk), .RN(n1783), .Q(
DmP_EXP_EWSW[14]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_15_ ( .D(n580), .CK(clk), .RN(n1784), .Q(
DmP_EXP_EWSW[15]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_16_ ( .D(n578), .CK(clk), .RN(n1784), .Q(
DmP_EXP_EWSW[16]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_17_ ( .D(n576), .CK(clk), .RN(n1784), .Q(
DmP_EXP_EWSW[17]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_18_ ( .D(n574), .CK(clk), .RN(n1784), .Q(
DmP_EXP_EWSW[18]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_19_ ( .D(n572), .CK(clk), .RN(n1784), .Q(
DmP_EXP_EWSW[19]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_20_ ( .D(n570), .CK(clk), .RN(n1785), .Q(
DmP_EXP_EWSW[20]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_21_ ( .D(n568), .CK(clk), .RN(n1785), .Q(
DmP_EXP_EWSW[21]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_22_ ( .D(n566), .CK(clk), .RN(n1785), .Q(
DmP_EXP_EWSW[22]) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_0_ ( .D(n557), .CK(clk), .RN(n1786), .Q(
ZERO_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_0_ ( .D(n556), .CK(clk), .RN(n1786), .Q(
ZERO_FLAG_SHT2) );
DFFRXLTS SGF_STAGE_FLAGS_Q_reg_0_ ( .D(n555), .CK(clk), .RN(n1786), .Q(
ZERO_FLAG_SFG) );
DFFRXLTS NRM_STAGE_FLAGS_Q_reg_0_ ( .D(n554), .CK(clk), .RN(n1786), .Q(
ZERO_FLAG_NRM) );
DFFRXLTS SFT2FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(n553), .CK(clk), .RN(n1786), .Q(
ZERO_FLAG_SHT1SHT2) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_1_ ( .D(n551), .CK(clk), .RN(n1786), .Q(
OP_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_1_ ( .D(n1754), .CK(clk), .RN(n1798), .Q(
OP_FLAG_SHT2) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_2_ ( .D(n548), .CK(clk), .RN(n1786), .Q(
SIGN_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_2_ ( .D(n547), .CK(clk), .RN(n1787), .Q(
SIGN_FLAG_SHT2) );
DFFRXLTS SGF_STAGE_FLAGS_Q_reg_2_ ( .D(n546), .CK(clk), .RN(n1787), .Q(
SIGN_FLAG_SFG) );
DFFRXLTS NRM_STAGE_FLAGS_Q_reg_1_ ( .D(n545), .CK(clk), .RN(n1787), .Q(
SIGN_FLAG_NRM) );
DFFRXLTS SFT2FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n544), .CK(clk), .RN(n1787), .Q(
SIGN_FLAG_SHT1SHT2) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_15_ ( .D(n527), .CK(clk), .RN(n1794), .Q(
Raw_mant_NRM_SWR[15]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_17_ ( .D(n525), .CK(clk), .RN(n1794), .Q(
Raw_mant_NRM_SWR[17]), .QN(n1707) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_18_ ( .D(n524), .CK(clk), .RN(n1794), .Q(
Raw_mant_NRM_SWR[18]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_11_ ( .D(n516), .CK(clk), .RN(n1793), .Q(
LZD_output_NRM2_EW[3]), .QN(n1699) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_10_ ( .D(n514), .CK(clk), .RN(n1793), .Q(
LZD_output_NRM2_EW[2]), .QN(n1701) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_9_ ( .D(n513), .CK(clk), .RN(n1792), .Q(
LZD_output_NRM2_EW[1]), .QN(n1700) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_12_ ( .D(n512), .CK(clk), .RN(n1793), .Q(
LZD_output_NRM2_EW[4]), .QN(n1706) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_0_ ( .D(n488), .CK(clk), .RN(n1790), .Q(
DmP_mant_SFG_SWR[0]), .QN(n920) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_1_ ( .D(n487), .CK(clk), .RN(n1790), .Q(
DmP_mant_SFG_SWR[1]), .QN(n919) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_4_ ( .D(n484), .CK(clk), .RN(n1791), .Q(
DmP_mant_SFG_SWR[4]), .QN(n1737) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_7_ ( .D(n481), .CK(clk), .RN(n1791), .Q(
DmP_mant_SFG_SWR[7]), .QN(n1753) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_8_ ( .D(n480), .CK(clk), .RN(n1791), .Q(
DmP_mant_SFG_SWR[8]), .QN(n1736) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_9_ ( .D(n479), .CK(clk), .RN(n1791), .Q(
DmP_mant_SFG_SWR[9]), .QN(n1739) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_10_ ( .D(n478), .CK(clk), .RN(n1797), .Q(
DmP_mant_SFG_SWR[10]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_11_ ( .D(n477), .CK(clk), .RN(n1797), .Q(
DmP_mant_SFG_SWR[11]) );
DFFRX2TS inst_ShiftRegister_Q_reg_2_ ( .D(n865), .CK(clk), .RN(n1798), .Q(
Shift_reg_FLAGS_7[2]), .QN(n1684) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_24_ ( .D(n838), .CK(clk), .RN(n1761),
.Q(intDX_EWSW[24]), .QN(n1745) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_6_ ( .D(n536), .CK(clk), .RN(n1787), .Q(
Raw_mant_NRM_SWR[6]), .QN(n1741) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_3_ ( .D(n539), .CK(clk), .RN(n1787), .Q(
Raw_mant_NRM_SWR[3]), .QN(n1730) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_9_ ( .D(n533), .CK(clk), .RN(n1788), .Q(
Raw_mant_NRM_SWR[9]), .QN(n1729) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_18_ ( .D(n810), .CK(clk), .RN(n1764),
.Q(intDY_EWSW[18]), .QN(n1727) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_30_ ( .D(n798), .CK(clk), .RN(n1765),
.Q(intDY_EWSW[30]), .QN(n1725) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_23_ ( .D(n805), .CK(clk), .RN(n1764),
.Q(intDY_EWSW[23]), .QN(n1724) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_26_ ( .D(n802), .CK(clk), .RN(n1765),
.Q(intDY_EWSW[26]), .QN(n1722) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_20_ ( .D(n808), .CK(clk), .RN(n1764),
.Q(intDY_EWSW[20]), .QN(n1721) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_14_ ( .D(n814), .CK(clk), .RN(n1763),
.Q(intDY_EWSW[14]), .QN(n1719) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_12_ ( .D(n816), .CK(clk), .RN(n1763),
.Q(intDY_EWSW[12]), .QN(n1718) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_8_ ( .D(n820), .CK(clk), .RN(n1763), .Q(
intDY_EWSW[8]), .QN(n1715) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_21_ ( .D(n807), .CK(clk), .RN(n1764),
.Q(intDY_EWSW[21]), .QN(n1714) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_13_ ( .D(n815), .CK(clk), .RN(n1763),
.Q(intDY_EWSW[13]), .QN(n1713) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_17_ ( .D(n811), .CK(clk), .RN(n1764),
.Q(intDY_EWSW[17]), .QN(n1711) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_25_ ( .D(n803), .CK(clk), .RN(n1764),
.Q(intDY_EWSW[25]), .QN(n1709) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_11_ ( .D(n817), .CK(clk), .RN(n1763),
.Q(intDY_EWSW[11]), .QN(n1697) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_8_ ( .D(n534), .CK(clk), .RN(n1788), .Q(
Raw_mant_NRM_SWR[8]), .QN(n1695) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_6_ ( .D(n856), .CK(clk), .RN(n1759), .Q(
intDX_EWSW[6]), .QN(n1693) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_16_ ( .D(n846), .CK(clk), .RN(n1760),
.Q(intDX_EWSW[16]), .QN(n1692) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_5_ ( .D(n857), .CK(clk), .RN(n1759), .Q(
intDX_EWSW[5]), .QN(n1685) );
DFFRX2TS inst_ShiftRegister_Q_reg_5_ ( .D(n868), .CK(clk), .RN(n1758), .Q(
n1670), .QN(n1752) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_25_ ( .D(n837), .CK(clk), .RN(n1761),
.Q(intDX_EWSW[25]), .QN(n1682) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_29_ ( .D(n799), .CK(clk), .RN(n1765),
.Q(intDY_EWSW[29]), .QN(n1679) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_22_ ( .D(n806), .CK(clk), .RN(n1764),
.Q(intDY_EWSW[22]), .QN(n1678) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_15_ ( .D(n813), .CK(clk), .RN(n1763),
.Q(intDY_EWSW[15]), .QN(n1677) );
DFFRX2TS inst_FSM_INPUT_ENABLE_state_reg_reg_1_ ( .D(
inst_FSM_INPUT_ENABLE_state_next_1_), .CK(clk), .RN(n1758), .Q(
inst_FSM_INPUT_ENABLE_state_reg[1]), .QN(n1674) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_7_ ( .D(n855), .CK(clk), .RN(n1759), .Q(
intDX_EWSW[7]), .QN(n1672) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_4_ ( .D(n858), .CK(clk), .RN(n1759), .Q(
intDX_EWSW[4]), .QN(n1671) );
DFFRXLTS Ready_reg_Q_reg_0_ ( .D(Shift_reg_FLAGS_7[0]), .CK(clk), .RN(n1762),
.Q(ready) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n559), .CK(clk), .RN(n1786), .Q(
underflow_flag) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(n552), .CK(clk), .RN(n1786), .Q(
zero_flag) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_14_ ( .D(n504), .CK(clk), .RN(n1789), .Q(
final_result_ieee[14]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_15_ ( .D(n502), .CK(clk), .RN(n1789), .Q(
final_result_ieee[15]) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(n558), .CK(clk), .RN(n1791), .Q(
overflow_flag) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_30_ ( .D(n754), .CK(clk), .RN(n1792), .Q(
final_result_ieee[30]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_31_ ( .D(n543), .CK(clk), .RN(n1791), .Q(
final_result_ieee[31]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_23_ ( .D(n761), .CK(clk), .RN(n1792), .Q(
final_result_ieee[23]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_24_ ( .D(n760), .CK(clk), .RN(n1792), .Q(
final_result_ieee[24]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_25_ ( .D(n759), .CK(clk), .RN(n1792), .Q(
final_result_ieee[25]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_26_ ( .D(n758), .CK(clk), .RN(n1792), .Q(
final_result_ieee[26]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_27_ ( .D(n757), .CK(clk), .RN(n1792), .Q(
final_result_ieee[27]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_28_ ( .D(n756), .CK(clk), .RN(n1792), .Q(
final_result_ieee[28]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_29_ ( .D(n755), .CK(clk), .RN(n1792), .Q(
final_result_ieee[29]) );
DFFRX2TS inst_ShiftRegister_Q_reg_4_ ( .D(n867), .CK(clk), .RN(n1758), .Q(
n1801), .QN(n1755) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_3_ ( .D(n825), .CK(clk), .RN(n1762), .Q(
intDY_EWSW[3]), .QN(n1710) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_8_ ( .D(n693), .CK(clk), .RN(n1798), .Q(
DMP_SFG[8]) );
DFFRHQX1TS SGF_STAGE_FLAGS_Q_reg_1_ ( .D(n549), .CK(clk), .RN(n1798), .Q(
OP_FLAG_SFG) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_14_ ( .D(n528), .CK(clk), .RN(n1794), .Q(
Raw_mant_NRM_SWR[14]), .QN(n1696) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_1_ ( .D(n827), .CK(clk), .RN(n1762), .Q(
intDY_EWSW[1]), .QN(n1800) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_21_ ( .D(n521), .CK(clk), .RN(n1795), .Q(
Raw_mant_NRM_SWR[21]), .QN(n1708) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_17_ ( .D(n498), .CK(clk), .RN(n1789), .Q(
final_result_ieee[17]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_8_ ( .D(n507), .CK(clk), .RN(n1788), .Q(
final_result_ieee[8]) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_27_ ( .D(n801), .CK(clk), .RN(n1765),
.Q(intDY_EWSW[27]), .QN(n1726) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_28_ ( .D(n834), .CK(clk), .RN(n1761),
.Q(intDX_EWSW[28]), .QN(n1694) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_8_ ( .D(n779), .CK(clk), .RN(n1767), .Q(
Data_array_SWR[8]), .QN(n1757) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_3_ ( .D(n859), .CK(clk), .RN(n1759), .Q(
intDX_EWSW[3]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_15_ ( .D(n847), .CK(clk), .RN(n1760),
.Q(intDX_EWSW[15]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_23_ ( .D(n839), .CK(clk), .RN(n1761),
.Q(intDX_EWSW[23]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_21_ ( .D(n841), .CK(clk), .RN(n1761),
.Q(intDX_EWSW[21]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_13_ ( .D(n849), .CK(clk), .RN(n1760),
.Q(intDX_EWSW[13]) );
DFFRX2TS SHT2_STAGE_SHFTVARS1_Q_reg_4_ ( .D(n767), .CK(clk), .RN(n1768), .Q(
shift_value_SHT2_EWR[4]), .QN(n875) );
DFFRX2TS inst_ShiftRegister_Q_reg_0_ ( .D(n863), .CK(clk), .RN(n1758), .Q(
Shift_reg_FLAGS_7[0]), .QN(n1738) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_22_ ( .D(n793), .CK(clk), .RN(n1766), .Q(
Data_array_SWR[22]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_17_ ( .D(n845), .CK(clk), .RN(n1760),
.Q(intDX_EWSW[17]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_24_ ( .D(n795), .CK(clk), .RN(n1765), .Q(
Data_array_SWR[24]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_8_ ( .D(n854), .CK(clk), .RN(n1759), .Q(
intDX_EWSW[8]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_11_ ( .D(n851), .CK(clk), .RN(n1760),
.Q(intDX_EWSW[11]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_25_ ( .D(n796), .CK(clk), .RN(n1765), .Q(
Data_array_SWR[25]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_1_ ( .D(n861), .CK(clk), .RN(n1759), .Q(
intDX_EWSW[1]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_9_ ( .D(n853), .CK(clk), .RN(n1759), .Q(
intDX_EWSW[9]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_12_ ( .D(n530), .CK(clk), .RN(n1788), .Q(
Raw_mant_NRM_SWR[12]) );
DFFRX2TS SHT2_STAGE_SHFTVARS1_Q_reg_2_ ( .D(n770), .CK(clk), .RN(n1765), .Q(
shift_value_SHT2_EWR[2]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_18_ ( .D(n844), .CK(clk), .RN(n1760),
.Q(intDX_EWSW[18]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_23_ ( .D(n794), .CK(clk), .RN(n1766), .Q(
Data_array_SWR[23]), .QN(n1742) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_29_ ( .D(n833), .CK(clk), .RN(n1761),
.Q(intDX_EWSW[29]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_15_ ( .D(n786), .CK(clk), .RN(n1766), .Q(
Data_array_SWR[15]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_13_ ( .D(n784), .CK(clk), .RN(n1767), .Q(
Data_array_SWR[13]) );
DFFRX2TS inst_FSM_INPUT_ENABLE_state_reg_reg_2_ ( .D(n871), .CK(clk), .RN(
n1758), .Q(inst_FSM_INPUT_ENABLE_state_reg[2]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_19_ ( .D(n843), .CK(clk), .RN(n1760),
.Q(intDX_EWSW[19]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_27_ ( .D(n835), .CK(clk), .RN(n1761),
.Q(intDX_EWSW[27]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_4_ ( .D(n538), .CK(clk), .RN(n1787), .Q(
Raw_mant_NRM_SWR[4]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_14_ ( .D(n785), .CK(clk), .RN(n1766), .Q(
Data_array_SWR[14]), .QN(n1744) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_17_ ( .D(n666), .CK(clk), .RN(n1796), .Q(
DMP_SFG[17]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_6_ ( .D(n777), .CK(clk), .RN(n1767), .Q(
Data_array_SWR[6]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_7_ ( .D(n778), .CK(clk), .RN(n1767), .Q(
Data_array_SWR[7]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_4_ ( .D(n775), .CK(clk), .RN(n1767), .Q(
Data_array_SWR[4]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_5_ ( .D(n776), .CK(clk), .RN(n1767), .Q(
Data_array_SWR[5]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_1_ ( .D(n714), .CK(clk), .RN(n1772), .Q(
DMP_SFG[1]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_14_ ( .D(n675), .CK(clk), .RN(n1796), .Q(
DMP_SFG[14]) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_31_ ( .D(n831), .CK(clk), .RN(n1762),
.Q(intDX_EWSW[31]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_6_ ( .D(n699), .CK(clk), .RN(n1068), .Q(
DMP_SFG[6]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_4_ ( .D(n705), .CK(clk), .RN(n1070), .Q(
DMP_SFG[4]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_2_ ( .D(n711), .CK(clk), .RN(n1068), .Q(
DMP_SFG[2]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_16_ ( .D(n669), .CK(clk), .RN(n1796), .Q(
DMP_SFG[16]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_15_ ( .D(n672), .CK(clk), .RN(n1796), .Q(
DMP_SFG[15]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_11_ ( .D(n684), .CK(clk), .RN(n1798), .Q(
DMP_SFG[11]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_6_ ( .D(n482), .CK(clk), .RN(n1791), .QN(
n1735) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_20_ ( .D(n569), .CK(clk), .RN(n1785), .Q(
DmP_mant_SHT1_SW[20]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_17_ ( .D(n575), .CK(clk), .RN(n1784), .Q(
DmP_mant_SHT1_SW[17]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_16_ ( .D(n577), .CK(clk), .RN(n1784), .Q(
DmP_mant_SHT1_SW[16]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_7_ ( .D(n595), .CK(clk), .RN(n1782), .Q(
DmP_mant_SHT1_SW[7]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_3_ ( .D(n603), .CK(clk), .RN(n1781), .Q(
DmP_mant_SHT1_SW[3]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_21_ ( .D(n567), .CK(clk), .RN(n1785), .Q(
DmP_mant_SHT1_SW[21]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_8_ ( .D(n593), .CK(clk), .RN(n1782), .Q(
DmP_mant_SHT1_SW[8]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_13_ ( .D(n583), .CK(clk), .RN(n1783), .Q(
DmP_mant_SHT1_SW[13]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_4_ ( .D(n601), .CK(clk), .RN(n1781), .Q(
DmP_mant_SHT1_SW[4]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_14_ ( .D(n581), .CK(clk), .RN(n1783), .Q(
DmP_mant_SHT1_SW[14]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_18_ ( .D(n573), .CK(clk), .RN(n1784), .Q(
DmP_mant_SHT1_SW[18]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_10_ ( .D(n589), .CK(clk), .RN(n1783), .Q(
DmP_mant_SHT1_SW[10]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_15_ ( .D(n579), .CK(clk), .RN(n1784), .Q(
DmP_mant_SHT1_SW[15]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_6_ ( .D(n597), .CK(clk), .RN(n1782), .Q(
DmP_mant_SHT1_SW[6]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_2_ ( .D(n605), .CK(clk), .RN(n1781), .Q(
DmP_mant_SHT1_SW[2]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_0_ ( .D(n609), .CK(clk), .RN(n1781), .Q(
DmP_mant_SHT1_SW[0]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_5_ ( .D(n599), .CK(clk), .RN(n1782), .Q(
DmP_mant_SHT1_SW[5]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_1_ ( .D(n607), .CK(clk), .RN(n1781), .Q(
DmP_mant_SHT1_SW[1]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_26_ ( .D(n727), .CK(clk), .RN(n1068), .Q(
DMP_EXP_EWSW[26]), .QN(n1683) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_24_ ( .D(n729), .CK(clk), .RN(n1770), .Q(
DMP_EXP_EWSW[24]), .QN(n1681) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_7_ ( .D(n696), .CK(clk), .RN(n1774), .Q(
DMP_SFG[7]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_5_ ( .D(n702), .CK(clk), .RN(n1773), .Q(
DMP_SFG[5]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_3_ ( .D(n708), .CK(clk), .RN(n1072), .Q(
DMP_SFG[3]) );
DFFRX1TS SHT1_STAGE_sft_amount_Q_reg_0_ ( .D(n766), .CK(clk), .RN(n1768),
.Q(Shift_amount_SHT1_EWR[0]) );
DFFRX1TS SHT1_STAGE_sft_amount_Q_reg_1_ ( .D(n765), .CK(clk), .RN(n1768),
.Q(Shift_amount_SHT1_EWR[1]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_4_ ( .D(n626), .CK(clk), .RN(n1793), .Q(
DMP_exp_NRM2_EW[4]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_3_ ( .D(n631), .CK(clk), .RN(n1793), .Q(
DMP_exp_NRM2_EW[3]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_2_ ( .D(n636), .CK(clk), .RN(n1793), .Q(
DMP_exp_NRM2_EW[2]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_1_ ( .D(n641), .CK(clk), .RN(n1793), .Q(
DMP_exp_NRM2_EW[1]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_13_ ( .D(n678), .CK(clk), .RN(n1798), .Q(
DMP_SFG[13]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_12_ ( .D(n681), .CK(clk), .RN(n1798), .Q(
DMP_SFG[12]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_21_ ( .D(n654), .CK(clk), .RN(n1797), .Q(
DMP_SFG[21]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_19_ ( .D(n660), .CK(clk), .RN(n1797), .Q(
DMP_SFG[19]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_22_ ( .D(n651), .CK(clk), .RN(n1797), .Q(
DMP_SFG[22]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_20_ ( .D(n657), .CK(clk), .RN(n1797), .Q(
DMP_SFG[20]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_18_ ( .D(n663), .CK(clk), .RN(n1797), .Q(
DMP_SFG[18]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_26_ ( .D(n561), .CK(clk), .RN(n1785), .Q(
DmP_EXP_EWSW[26]), .QN(n881) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_12_ ( .D(n476), .CK(clk), .RN(n1797), .Q(
DmP_mant_SFG_SWR[12]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_0_ ( .D(n717), .CK(clk), .RN(n1772), .Q(
DMP_SFG[0]), .QN(n879) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_31_ ( .D(n797), .CK(clk), .RN(n1765),
.Q(intDY_EWSW[31]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_15_ ( .D(n473), .CK(clk), .RN(n1798), .Q(
DmP_mant_SFG_SWR[15]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_14_ ( .D(n474), .CK(clk), .RN(n1797), .Q(
DmP_mant_SFG_SWR[14]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_25_ ( .D(n463), .CK(clk), .RN(n1796), .Q(
DmP_mant_SFG_SWR[25]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_24_ ( .D(n464), .CK(clk), .RN(n1796), .Q(
DmP_mant_SFG_SWR[24]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_23_ ( .D(n465), .CK(clk), .RN(n1796), .Q(
DmP_mant_SFG_SWR[23]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_22_ ( .D(n466), .CK(clk), .RN(n1796), .Q(
DmP_mant_SFG_SWR[22]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_21_ ( .D(n467), .CK(clk), .RN(n1796), .Q(
DmP_mant_SFG_SWR[21]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_20_ ( .D(n468), .CK(clk), .RN(n1796), .Q(
DmP_mant_SFG_SWR[20]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_19_ ( .D(n469), .CK(clk), .RN(n1795), .Q(
DmP_mant_SFG_SWR[19]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_18_ ( .D(n470), .CK(clk), .RN(n1795), .Q(
DmP_mant_SFG_SWR[18]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_17_ ( .D(n471), .CK(clk), .RN(n1795), .Q(
DmP_mant_SFG_SWR[17]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_16_ ( .D(n472), .CK(clk), .RN(n1795), .Q(
DmP_mant_SFG_SWR[16]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_12_ ( .D(n850), .CK(clk), .RN(n1760),
.Q(intDX_EWSW[12]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_20_ ( .D(n842), .CK(clk), .RN(n1760),
.Q(intDX_EWSW[20]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_14_ ( .D(n848), .CK(clk), .RN(n1760),
.Q(intDX_EWSW[14]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_22_ ( .D(n840), .CK(clk), .RN(n1761),
.Q(intDX_EWSW[22]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_2_ ( .D(n860), .CK(clk), .RN(n1759), .Q(
intDX_EWSW[2]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_30_ ( .D(n832), .CK(clk), .RN(n1761),
.Q(intDX_EWSW[30]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_10_ ( .D(n852), .CK(clk), .RN(n1759),
.Q(intDX_EWSW[10]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_0_ ( .D(n862), .CK(clk), .RN(n1758), .Q(
intDX_EWSW[0]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_9_ ( .D(n780), .CK(clk), .RN(n1767), .Q(
Data_array_SWR[9]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_12_ ( .D(n783), .CK(clk), .RN(n1767), .Q(
Data_array_SWR[12]), .QN(n1743) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_11_ ( .D(n782), .CK(clk), .RN(n1767), .Q(
Data_array_SWR[11]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_21_ ( .D(n792), .CK(clk), .RN(n1766), .Q(
Data_array_SWR[21]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_19_ ( .D(n790), .CK(clk), .RN(n1766), .Q(
Data_array_SWR[19]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_18_ ( .D(n789), .CK(clk), .RN(n1766), .Q(
Data_array_SWR[18]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_16_ ( .D(n787), .CK(clk), .RN(n1766), .Q(
Data_array_SWR[16]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_20_ ( .D(n791), .CK(clk), .RN(n1766), .Q(
Data_array_SWR[20]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_10_ ( .D(n781), .CK(clk), .RN(n1767), .Q(
Data_array_SWR[10]), .QN(n1751) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_12_ ( .D(n585), .CK(clk), .RN(n1783), .Q(
DmP_mant_SHT1_SW[12]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_22_ ( .D(n565), .CK(clk), .RN(n1785), .Q(
DmP_mant_SHT1_SW[22]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_27_ ( .D(n726), .CK(clk), .RN(n1769), .Q(
DMP_EXP_EWSW[27]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_25_ ( .D(n728), .CK(clk), .RN(n1071), .Q(
DMP_EXP_EWSW[25]), .QN(n913) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_9_ ( .D(n591), .CK(clk), .RN(n1782), .Q(
DmP_mant_SHT1_SW[9]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_11_ ( .D(n587), .CK(clk), .RN(n1783), .Q(
DmP_mant_SHT1_SW[11]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_19_ ( .D(n571), .CK(clk), .RN(n1784), .Q(
DmP_mant_SHT1_SW[19]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_23_ ( .D(n564), .CK(clk), .RN(n1785), .Q(
DmP_EXP_EWSW[23]), .QN(n914) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_24_ ( .D(n563), .CK(clk), .RN(n1785), .Q(
DmP_EXP_EWSW[24]), .QN(n880) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_3_ ( .D(n774), .CK(clk), .RN(n1768), .Q(
Data_array_SWR[3]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_2_ ( .D(n773), .CK(clk), .RN(n1768), .Q(
Data_array_SWR[2]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_1_ ( .D(n772), .CK(clk), .RN(n1768), .Q(
Data_array_SWR[1]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_27_ ( .D(n560), .CK(clk), .RN(n1786), .Q(
DmP_EXP_EWSW[27]) );
DFFRX1TS inst_ShiftRegister_Q_reg_3_ ( .D(n866), .CK(clk), .RN(n1758), .Q(
Shift_reg_FLAGS_7[3]), .QN(n882) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_25_ ( .D(n562), .CK(clk), .RN(n1785), .Q(
DmP_EXP_EWSW[25]), .QN(n1746) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_0_ ( .D(n771), .CK(clk), .RN(n1768), .Q(
Data_array_SWR[0]) );
DFFRX1TS SHT2_STAGE_SHFTVARS2_Q_reg_1_ ( .D(n829), .CK(clk), .RN(n1762), .Q(
left_right_SHT2), .QN(n1756) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_8_ ( .D(n515), .CK(clk), .RN(n1792), .Q(
LZD_output_NRM2_EW[0]), .QN(n874) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_16_ ( .D(n526), .CK(clk), .RN(n1794), .Q(
Raw_mant_NRM_SWR[16]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_19_ ( .D(n523), .CK(clk), .RN(n1795), .Q(
Raw_mant_NRM_SWR[19]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_20_ ( .D(n522), .CK(clk), .RN(n1795), .Q(
Raw_mant_NRM_SWR[20]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_22_ ( .D(n520), .CK(clk), .RN(n1795), .Q(
Raw_mant_NRM_SWR[22]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_23_ ( .D(n519), .CK(clk), .RN(n1795), .Q(
Raw_mant_NRM_SWR[23]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_24_ ( .D(n518), .CK(clk), .RN(n1795), .Q(
Raw_mant_NRM_SWR[24]) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_13_ ( .D(n529), .CK(clk), .RN(n1788), .Q(
Raw_mant_NRM_SWR[13]), .QN(n1740) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_11_ ( .D(n531), .CK(clk), .RN(n1788), .Q(
Raw_mant_NRM_SWR[11]), .QN(n1668) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_7_ ( .D(n505), .CK(clk), .RN(n1789), .Q(
final_result_ieee[7]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_6_ ( .D(n503), .CK(clk), .RN(n1789), .Q(
final_result_ieee[6]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_5_ ( .D(n501), .CK(clk), .RN(n1789), .Q(
final_result_ieee[5]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_16_ ( .D(n500), .CK(clk), .RN(n1789), .Q(
final_result_ieee[16]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_4_ ( .D(n499), .CK(clk), .RN(n1789), .Q(
final_result_ieee[4]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_3_ ( .D(n497), .CK(clk), .RN(n1789), .Q(
final_result_ieee[3]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_18_ ( .D(n496), .CK(clk), .RN(n1790), .Q(
final_result_ieee[18]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_2_ ( .D(n495), .CK(clk), .RN(n1790), .Q(
final_result_ieee[2]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_19_ ( .D(n494), .CK(clk), .RN(n1790), .Q(
final_result_ieee[19]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_1_ ( .D(n493), .CK(clk), .RN(n1790), .Q(
final_result_ieee[1]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_0_ ( .D(n492), .CK(clk), .RN(n1790), .Q(
final_result_ieee[0]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_20_ ( .D(n491), .CK(clk), .RN(n1790), .Q(
final_result_ieee[20]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_21_ ( .D(n490), .CK(clk), .RN(n1790), .Q(
final_result_ieee[21]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_22_ ( .D(n489), .CK(clk), .RN(n1790), .Q(
final_result_ieee[22]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_11_ ( .D(n510), .CK(clk), .RN(n1788), .Q(
final_result_ieee[11]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_9_ ( .D(n509), .CK(clk), .RN(n1788), .Q(
final_result_ieee[9]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_12_ ( .D(n508), .CK(clk), .RN(n1788), .Q(
final_result_ieee[12]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_13_ ( .D(n506), .CK(clk), .RN(n1789), .Q(
final_result_ieee[13]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_10_ ( .D(n511), .CK(clk), .RN(n1788), .Q(
final_result_ieee[10]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_10_ ( .D(n687), .CK(clk), .RN(n1798), .Q(
DMP_SFG[10]), .QN(n1747) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_7_ ( .D(n611), .CK(clk), .RN(n1794), .Q(
DMP_exp_NRM2_EW[7]), .QN(n1734) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_6_ ( .D(n616), .CK(clk), .RN(n1793), .Q(
DMP_exp_NRM2_EW[6]), .QN(n1728) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_5_ ( .D(n621), .CK(clk), .RN(n1793), .Q(
DMP_exp_NRM2_EW[5]), .QN(n1705) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_0_ ( .D(n646), .CK(clk), .RN(n1793), .Q(
DMP_exp_NRM2_EW[0]), .QN(n1698) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_1_ ( .D(n541), .CK(clk), .RN(n1794), .Q(
Raw_mant_NRM_SWR[1]), .QN(n1748) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_0_ ( .D(n542), .CK(clk), .RN(n1794), .Q(
Raw_mant_NRM_SWR[0]), .QN(n1673) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_2_ ( .D(n540), .CK(clk), .RN(n1787), .Q(
Raw_mant_NRM_SWR[2]), .QN(n1687) );
DFFRX1TS inst_FSM_INPUT_ENABLE_state_reg_reg_0_ ( .D(n870), .CK(clk), .RN(
n1758), .Q(inst_FSM_INPUT_ENABLE_state_reg[0]), .QN(n1704) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_5_ ( .D(n537), .CK(clk), .RN(n1787), .Q(
Raw_mant_NRM_SWR[5]), .QN(n1690) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_9_ ( .D(n690), .CK(clk), .RN(n1798), .Q(
DMP_SFG[9]), .QN(n1749) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_10_ ( .D(n532), .CK(clk), .RN(n1794), .Q(
Raw_mant_NRM_SWR[10]), .QN(n1686) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_7_ ( .D(n535), .CK(clk), .RN(n1787), .Q(
Raw_mant_NRM_SWR[7]), .QN(n1691) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_24_ ( .D(n804), .CK(clk), .RN(n1764),
.Q(intDY_EWSW[24]), .QN(n1669) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_28_ ( .D(n800), .CK(clk), .RN(n1765),
.Q(intDY_EWSW[28]), .QN(n1723) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_7_ ( .D(n821), .CK(clk), .RN(n1763), .Q(
intDY_EWSW[7]), .QN(n1703) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_26_ ( .D(n836), .CK(clk), .RN(n1761),
.Q(intDX_EWSW[26]), .QN(n1750) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_19_ ( .D(n809), .CK(clk), .RN(n1764),
.Q(intDY_EWSW[19]), .QN(n1680) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_10_ ( .D(n818), .CK(clk), .RN(n1763),
.Q(intDY_EWSW[10]), .QN(n1688) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_0_ ( .D(n828), .CK(clk), .RN(n1762), .Q(
intDY_EWSW[0]), .QN(n1676) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_9_ ( .D(n819), .CK(clk), .RN(n1763), .Q(
intDY_EWSW[9]), .QN(n1712) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_2_ ( .D(n826), .CK(clk), .RN(n1762), .Q(
intDY_EWSW[2]), .QN(n1716) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_16_ ( .D(n812), .CK(clk), .RN(n1764),
.Q(intDY_EWSW[16]), .QN(n1720) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_6_ ( .D(n822), .CK(clk), .RN(n1763), .Q(
intDY_EWSW[6]), .QN(n1702) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_4_ ( .D(n824), .CK(clk), .RN(n1762), .Q(
intDY_EWSW[4]), .QN(n1717) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_5_ ( .D(n823), .CK(clk), .RN(n1762), .Q(
intDY_EWSW[5]), .QN(n1675) );
DFFRX1TS SHT2_STAGE_SHFTVARS1_Q_reg_3_ ( .D(n769), .CK(clk), .RN(n1765), .Q(
shift_value_SHT2_EWR[3]), .QN(n1689) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_2_ ( .D(n486), .CK(clk), .RN(n1791), .Q(
DmP_mant_SFG_SWR[2]), .QN(n1732) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_3_ ( .D(n485), .CK(clk), .RN(n1791), .Q(
DmP_mant_SFG_SWR[3]), .QN(n1731) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_5_ ( .D(n483), .CK(clk), .RN(n1791), .Q(
DmP_mant_SFG_SWR[5]), .QN(n1733) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_23_ ( .D(n730), .CK(clk), .RN(n1771), .Q(
DMP_EXP_EWSW[23]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_13_ ( .D(n475), .CK(clk), .RN(n1797), .Q(
DmP_mant_SFG_SWR[13]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_25_ ( .D(n517), .CK(clk), .RN(n1794), .Q(
Raw_mant_NRM_SWR[25]) );
CMPR32X2TS DP_OP_15J43_123_3594_U8 ( .A(n1700), .B(DMP_exp_NRM2_EW[1]), .C(
DP_OP_15J43_123_3594_n8), .CO(DP_OP_15J43_123_3594_n7), .S(
exp_rslt_NRM2_EW1[1]) );
CMPR32X2TS DP_OP_15J43_123_3594_U7 ( .A(n1701), .B(DMP_exp_NRM2_EW[2]), .C(
DP_OP_15J43_123_3594_n7), .CO(DP_OP_15J43_123_3594_n6), .S(
exp_rslt_NRM2_EW1[2]) );
CMPR32X2TS DP_OP_15J43_123_3594_U6 ( .A(n1699), .B(DMP_exp_NRM2_EW[3]), .C(
DP_OP_15J43_123_3594_n6), .CO(DP_OP_15J43_123_3594_n5), .S(
exp_rslt_NRM2_EW1[3]) );
DFFRX4TS inst_ShiftRegister_Q_reg_1_ ( .D(n864), .CK(clk), .RN(n1758), .Q(
Shift_reg_FLAGS_7[1]), .QN(n876) );
CMPR32X2TS DP_OP_15J43_123_3594_U5 ( .A(n1706), .B(DMP_exp_NRM2_EW[4]), .C(
DP_OP_15J43_123_3594_n5), .CO(DP_OP_15J43_123_3594_n4), .S(
exp_rslt_NRM2_EW1[4]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_17_ ( .D(n788), .CK(clk), .RN(n1766), .Q(
Data_array_SWR[17]) );
DFFRX4TS inst_ShiftRegister_Q_reg_6_ ( .D(n869), .CK(clk), .RN(n1758), .Q(
Shift_reg_FLAGS_7_6), .QN(n915) );
INVX2TS U897 ( .A(n1634), .Y(n1646) );
OA22X1TS U898 ( .A0(n1690), .A1(n1345), .B0(n1302), .B1(n902), .Y(n1303) );
AOI222X4TS U899 ( .A0(Data_array_SWR[23]), .A1(n888), .B0(Data_array_SWR[19]), .B1(n891), .C0(Data_array_SWR[15]), .C1(n996), .Y(n1367) );
BUFX3TS U900 ( .A(n1285), .Y(n1255) );
INVX2TS U901 ( .A(n906), .Y(n907) );
INVX2TS U902 ( .A(n1345), .Y(n1352) );
AOI222X4TS U903 ( .A0(Raw_mant_NRM_SWR[7]), .A1(n905), .B0(n910), .B1(
DmP_mant_SHT1_SW[16]), .C0(n1309), .C1(DmP_mant_SHT1_SW[17]), .Y(n1299) );
AOI222X4TS U904 ( .A0(Raw_mant_NRM_SWR[3]), .A1(n904), .B0(n911), .B1(
DmP_mant_SHT1_SW[20]), .C0(n1335), .C1(DmP_mant_SHT1_SW[21]), .Y(n1293) );
AND2X2TS U905 ( .A(beg_OP), .B(n1465), .Y(n1470) );
INVX2TS U906 ( .A(n1490), .Y(n905) );
NAND2X2TS U907 ( .A(n990), .B(n989), .Y(n991) );
NAND2X1TS U908 ( .A(n1728), .B(n1007), .Y(n1011) );
NAND2X1TS U909 ( .A(n976), .B(n975), .Y(n990) );
BUFX3TS U910 ( .A(Shift_reg_FLAGS_7_6), .Y(n1532) );
NAND2X1TS U911 ( .A(n972), .B(n971), .Y(n976) );
NAND2X1TS U912 ( .A(n1705), .B(n1002), .Y(n1006) );
CMPR32X2TS U913 ( .A(n1420), .B(DMP_SFG[12]), .C(n1419), .CO(n1411), .S(
n1421) );
CMPR32X2TS U914 ( .A(n1622), .B(DMP_SFG[11]), .C(n1214), .CO(n1419) );
NOR3X1TS U915 ( .A(Raw_mant_NRM_SWR[17]), .B(Raw_mant_NRM_SWR[15]), .C(
Raw_mant_NRM_SWR[16]), .Y(n1436) );
OAI21XLTS U916 ( .A0(intDX_EWSW[3]), .A1(n1710), .B0(intDX_EWSW[2]), .Y(n945) );
OAI211XLTS U917 ( .A0(n1710), .A1(intDX_EWSW[3]), .B0(n944), .C0(n943), .Y(
n947) );
NOR2XLTS U918 ( .A(n960), .B(intDY_EWSW[16]), .Y(n961) );
OAI21XLTS U919 ( .A0(intDX_EWSW[23]), .A1(n1724), .B0(intDX_EWSW[22]), .Y(
n966) );
OAI21XLTS U920 ( .A0(Raw_mant_NRM_SWR[25]), .A1(n1043), .B0(n1042), .Y(n1044) );
AOI31XLTS U921 ( .A0(n1045), .A1(Raw_mant_NRM_SWR[16]), .A2(n1707), .B0(
n1044), .Y(n1046) );
NOR2XLTS U922 ( .A(Raw_mant_NRM_SWR[21]), .B(Raw_mant_NRM_SWR[20]), .Y(n1024) );
OR2X1TS U923 ( .A(n897), .B(n1065), .Y(n878) );
NAND2X2TS U924 ( .A(n1037), .B(n1668), .Y(n1047) );
INVX2TS U925 ( .A(n1488), .Y(n883) );
CLKINVX3TS U926 ( .A(n1543), .Y(n1182) );
OAI21XLTS U927 ( .A0(n1668), .A1(n1490), .B0(n1484), .Y(n1485) );
CLKINVX3TS U928 ( .A(Shift_reg_FLAGS_7[2]), .Y(n1433) );
CLKINVX3TS U929 ( .A(n1281), .Y(n1531) );
CLKINVX3TS U930 ( .A(n1285), .Y(n1533) );
OAI211XLTS U931 ( .A0(n1342), .A1(n908), .B0(n1341), .C0(n1340), .Y(n788) );
OAI211XLTS U932 ( .A0(n1203), .A1(n1495), .B0(n1202), .C0(n1201), .Y(n772)
);
OAI21XLTS U933 ( .A0(n1296), .A1(n902), .B0(n1235), .Y(n789) );
OAI21XLTS U934 ( .A0(n1184), .A1(n1638), .B0(n1174), .Y(n469) );
OAI211XLTS U935 ( .A0(n1318), .A1(n908), .B0(n1314), .C0(n1313), .Y(n775) );
OAI211XLTS U936 ( .A0(n1500), .A1(n875), .B0(n1435), .C0(n1160), .Y(n767) );
OAI211XLTS U937 ( .A0(n1128), .A1(n1137), .B0(n1534), .C0(n1127), .Y(n755)
);
OAI21XLTS U938 ( .A0(n1697), .A1(n1231), .B0(n1207), .Y(n588) );
OAI21XLTS U939 ( .A0(n1679), .A1(n1533), .B0(n1254), .Y(n724) );
OAI21XLTS U940 ( .A0(n1716), .A1(n1253), .B0(n1249), .Y(n751) );
AOI2BB2X1TS U941 ( .B0(Raw_mant_NRM_SWR[15]), .B1(n1352), .A0N(n1348), .A1N(
n902), .Y(n1330) );
INVX4TS U942 ( .A(n885), .Y(n886) );
AOI2BB1X1TS U943 ( .A0N(Shift_reg_FLAGS_7[1]), .A1N(LZD_output_NRM2_EW[3]),
.B0(n1502), .Y(n516) );
NAND4X1TS U944 ( .A(n1442), .B(n1441), .C(n1440), .D(n1448), .Y(n1443) );
OAI211X1TS U945 ( .A0(n1451), .A1(n1450), .B0(n1449), .C0(n1448), .Y(n1452)
);
NOR2X2TS U946 ( .A(n1292), .B(n899), .Y(n1454) );
XNOR2X1TS U947 ( .A(n1224), .B(n1223), .Y(n1226) );
CLKMX2X2TS U948 ( .A(n1396), .B(Raw_mant_NRM_SWR[24]), .S0(n1433), .Y(n518)
);
CLKMX2X2TS U949 ( .A(n1393), .B(Raw_mant_NRM_SWR[23]), .S0(n1433), .Y(n519)
);
AO22X1TS U950 ( .A0(n1634), .A1(n1631), .B0(final_result_ieee[8]), .B1(n1738), .Y(n507) );
AO22X1TS U951 ( .A0(final_result_ieee[10]), .A1(n1632), .B0(n1634), .B1(
n1627), .Y(n511) );
AO22X1TS U952 ( .A0(n1634), .A1(n1633), .B0(final_result_ieee[13]), .B1(
n1632), .Y(n506) );
AO22X1TS U953 ( .A0(n1634), .A1(n1630), .B0(final_result_ieee[12]), .B1(
n1632), .Y(n508) );
AO22X1TS U954 ( .A0(n1634), .A1(n1628), .B0(final_result_ieee[11]), .B1(
n1632), .Y(n510) );
AO22X1TS U955 ( .A0(n1456), .A1(n1455), .B0(final_result_ieee[30]), .B1(
n1463), .Y(n754) );
AO22X1TS U956 ( .A0(n1634), .A1(n1629), .B0(final_result_ieee[9]), .B1(n1632), .Y(n509) );
BUFX4TS U957 ( .A(n1189), .Y(n1285) );
AND2X2TS U958 ( .A(n1734), .B(n1012), .Y(n1013) );
AND2X2TS U959 ( .A(n1455), .B(n1010), .Y(n916) );
NOR2X6TS U960 ( .A(Raw_mant_NRM_SWR[12]), .B(n1047), .Y(n1444) );
OAI21X1TS U961 ( .A0(n1557), .A1(n1570), .B0(n1556), .Y(n1559) );
OAI21X1TS U962 ( .A0(n1569), .A1(n1555), .B0(n1570), .Y(n1556) );
INVX1TS U963 ( .A(n1121), .Y(n1123) );
NAND2X2TS U964 ( .A(n1437), .B(n1436), .Y(n1029) );
NAND2BX1TS U965 ( .AN(n1596), .B(n1595), .Y(n1597) );
NOR2X1TS U966 ( .A(n1403), .B(n1405), .Y(n1398) );
INVX4TS U967 ( .A(n897), .Y(n1652) );
INVX4TS U968 ( .A(n1543), .Y(n1661) );
OAI21X1TS U969 ( .A0(n1460), .A1(n995), .B0(n1458), .Y(n870) );
INVX4TS U970 ( .A(n1426), .Y(n1222) );
INVX4TS U971 ( .A(n1426), .Y(n1561) );
NOR2X1TS U972 ( .A(n922), .B(intDY_EWSW[10]), .Y(n923) );
NOR2X1TS U973 ( .A(n977), .B(intDY_EWSW[24]), .Y(n978) );
INVX1TS U974 ( .A(n1436), .Y(n1438) );
AOI211X1TS U975 ( .A0(intDY_EWSW[28]), .A1(n1694), .B0(n985), .C0(n983), .Y(
n987) );
NOR2X1TS U976 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(
inst_FSM_INPUT_ENABLE_state_reg[1]), .Y(n1358) );
OAI21X1TS U977 ( .A0(intDX_EWSW[21]), .A1(n1714), .B0(intDX_EWSW[20]), .Y(
n959) );
OAI21X1TS U978 ( .A0(n1687), .A1(n1345), .B0(n1289), .Y(n793) );
OAI21X1TS U979 ( .A0(n1483), .A1(n901), .B0(n1240), .Y(n792) );
OAI21X1TS U980 ( .A0(n1486), .A1(n1495), .B0(n1301), .Y(n787) );
OAI211X1TS U981 ( .A0(n1353), .A1(n901), .B0(n1325), .C0(n1324), .Y(n777) );
OAI211X1TS U982 ( .A0(n1339), .A1(n908), .B0(n1304), .C0(n1303), .Y(n790) );
OAI211X1TS U983 ( .A0(n1322), .A1(n901), .B0(n1321), .C0(n1320), .Y(n774) );
OAI211X1TS U984 ( .A0(n1332), .A1(n902), .B0(n1328), .C0(n1327), .Y(n778) );
OAI211X1TS U985 ( .A0(n1348), .A1(n908), .B0(n1347), .C0(n1346), .Y(n782) );
OAI21X1TS U986 ( .A0(n1296), .A1(n1495), .B0(n1295), .Y(n791) );
OAI211X1TS U987 ( .A0(n1338), .A1(n908), .B0(n1337), .C0(n1336), .Y(n786) );
OAI211X1TS U988 ( .A0(n1344), .A1(n1495), .B0(n1334), .C0(n1333), .Y(n784)
);
NOR2X2TS U989 ( .A(n1292), .B(n883), .Y(n1343) );
OAI21X1TS U990 ( .A0(n1696), .A1(n883), .B0(n1350), .Y(n1351) );
BUFX3TS U991 ( .A(n1050), .Y(n1345) );
OAI21X1TS U992 ( .A0(n1740), .A1(n1490), .B0(n1489), .Y(n1491) );
AOI222X1TS U993 ( .A0(Raw_mant_NRM_SWR[4]), .A1(n904), .B0(n910), .B1(
DmP_mant_SHT1_SW[19]), .C0(n1309), .C1(DmP_mant_SHT1_SW[20]), .Y(n1302) );
NAND3X1TS U994 ( .A(n1155), .B(n1447), .C(Raw_mant_NRM_SWR[1]), .Y(n1440) );
OAI21X1TS U995 ( .A0(n1675), .A1(n1253), .B0(n1251), .Y(n748) );
OAI21X1TS U996 ( .A0(n1702), .A1(n1253), .B0(n1250), .Y(n747) );
OAI21X1TS U997 ( .A0(n1717), .A1(n1253), .B0(n1252), .Y(n749) );
OAI21X1TS U998 ( .A0(n1718), .A1(n1275), .B0(n1263), .Y(n741) );
OAI21X1TS U999 ( .A0(n1677), .A1(n1275), .B0(n993), .Y(n738) );
OAI21X1TS U1000 ( .A0(n1697), .A1(n1275), .B0(n1266), .Y(n742) );
OAI21X1TS U1001 ( .A0(n1715), .A1(n1275), .B0(n1265), .Y(n745) );
OAI21X1TS U1002 ( .A0(n1676), .A1(n1280), .B0(n1269), .Y(n753) );
OAI21X1TS U1003 ( .A0(n1720), .A1(n1275), .B0(n1268), .Y(n737) );
OAI21X1TS U1004 ( .A0(n1688), .A1(n1231), .B0(n1205), .Y(n590) );
OAI21X1TS U1005 ( .A0(n1711), .A1(n1280), .B0(n1264), .Y(n736) );
OAI21X1TS U1006 ( .A0(n1721), .A1(n1280), .B0(n1277), .Y(n733) );
OAI21X1TS U1007 ( .A0(n1726), .A1(n1280), .B0(n1260), .Y(n726) );
OAI21X1TS U1008 ( .A0(n1678), .A1(n1280), .B0(n1276), .Y(n731) );
OAI21X1TS U1009 ( .A0(n1710), .A1(n1253), .B0(n994), .Y(n750) );
OAI21X1TS U1010 ( .A0(n1800), .A1(n1533), .B0(n1248), .Y(n752) );
OAI21X1TS U1011 ( .A0(n1723), .A1(n1533), .B0(n1247), .Y(n725) );
OAI21X1TS U1012 ( .A0(n1711), .A1(n1231), .B0(n1185), .Y(n576) );
OAI21X1TS U1013 ( .A0(n1721), .A1(n1531), .B0(n1282), .Y(n570) );
OAI21X1TS U1014 ( .A0(n1680), .A1(n1531), .B0(n1286), .Y(n572) );
OAI21X1TS U1015 ( .A0(n1678), .A1(n1531), .B0(n1283), .Y(n566) );
OAI21X1TS U1016 ( .A0(n1720), .A1(n1231), .B0(n1188), .Y(n578) );
OAI21X1TS U1017 ( .A0(n1714), .A1(n1531), .B0(n1284), .Y(n568) );
OAI21X1TS U1018 ( .A0(n1726), .A1(n1231), .B0(n1196), .Y(n560) );
OAI211X1TS U1019 ( .A0(n1125), .A1(n1137), .B0(n1534), .C0(n1124), .Y(n759)
);
OAI211X1TS U1020 ( .A0(n1133), .A1(n1137), .B0(n1534), .C0(n1132), .Y(n761)
);
OAI211X1TS U1021 ( .A0(n1135), .A1(n1137), .B0(n1534), .C0(n1134), .Y(n758)
);
OAI211X1TS U1022 ( .A0(n1138), .A1(n1137), .B0(n1534), .C0(n1136), .Y(n760)
);
OAI21X1TS U1023 ( .A0(n1702), .A1(n1211), .B0(n1190), .Y(n598) );
OAI211X1TS U1024 ( .A0(n1123), .A1(n1137), .B0(n1534), .C0(n1122), .Y(n756)
);
OAI21X1TS U1025 ( .A0(n1800), .A1(n1211), .B0(n1194), .Y(n608) );
OAI21X1TS U1026 ( .A0(n1717), .A1(n1211), .B0(n1191), .Y(n602) );
OAI21X1TS U1027 ( .A0(n1675), .A1(n1211), .B0(n1192), .Y(n600) );
OAI21X1TS U1028 ( .A0(n1245), .A1(n1514), .B0(n1242), .Y(n1243) );
INVX1TS U1029 ( .A(n1457), .Y(n1456) );
OAI211X1TS U1030 ( .A0(n1130), .A1(n1137), .B0(n1534), .C0(n1129), .Y(n757)
);
OAI21X1TS U1031 ( .A0(n1716), .A1(n1211), .B0(n1193), .Y(n606) );
INVX1TS U1032 ( .A(n1259), .Y(n1242) );
INVX1TS U1033 ( .A(n1574), .Y(n1577) );
NOR2X1TS U1034 ( .A(n1618), .B(n1747), .Y(n1621) );
INVX1TS U1035 ( .A(n1600), .Y(n1602) );
INVX1TS U1036 ( .A(n1591), .Y(n1594) );
INVX1TS U1037 ( .A(n1126), .Y(n1128) );
NAND2BX1TS U1038 ( .AN(n1126), .B(n1005), .Y(n1008) );
OAI21X1TS U1039 ( .A0(n1164), .A1(n1184), .B0(n1163), .Y(n465) );
OAI21X1TS U1040 ( .A0(n1184), .A1(n1635), .B0(n1120), .Y(n472) );
AOI222X1TS U1041 ( .A0(n1139), .A1(n1652), .B0(Data_array_SWR[8]), .B1(n893),
.C0(n1001), .C1(n1642), .Y(n1663) );
AOI222X1TS U1042 ( .A0(n1644), .A1(n1756), .B0(n893), .B1(Data_array_SWR[4]),
.C0(n1643), .C1(n1642), .Y(n1657) );
AOI222X1TS U1043 ( .A0(n1640), .A1(n896), .B0(n893), .B1(Data_array_SWR[5]),
.C0(n1639), .C1(n1642), .Y(n1658) );
AOI222X1TS U1044 ( .A0(n1181), .A1(n1756), .B0(Data_array_SWR[7]), .B1(n893),
.C0(n1180), .C1(n1642), .Y(n1660) );
OAI21X1TS U1045 ( .A0(n1376), .A1(n1379), .B0(n1380), .Y(n1220) );
OAI21X1TS U1046 ( .A0(n1150), .A1(n1184), .B0(n1149), .Y(n463) );
NOR2X1TS U1047 ( .A(n1375), .B(n1379), .Y(n1221) );
OAI21X1TS U1048 ( .A0(n958), .A1(n957), .B0(n956), .Y(n972) );
NOR2X1TS U1049 ( .A(n1004), .B(n1121), .Y(n1005) );
NAND4BX1TS U1050 ( .AN(exp_rslt_NRM2_EW1[4]), .B(n1003), .C(n1135), .D(n1125), .Y(n1004) );
NOR2X1TS U1051 ( .A(n1614), .B(n1610), .Y(n1605) );
AOI32X1TS U1052 ( .A0(Shift_amount_SHT1_EWR[2]), .A1(n1500), .A2(n1496),
.B0(shift_value_SHT2_EWR[2]), .B1(n1238), .Y(n1498) );
AOI222X1TS U1053 ( .A0(n1173), .A1(n1756), .B0(Data_array_SWR[6]), .B1(n893),
.C0(n1172), .C1(n1642), .Y(n1659) );
AOI21X1TS U1054 ( .A0(n1397), .A1(n918), .B0(n1218), .Y(n1376) );
NOR2X1TS U1055 ( .A(n1576), .B(n1586), .Y(n1425) );
AO22XLTS U1056 ( .A0(n1473), .A1(add_subt), .B0(n1471), .B1(intAS), .Y(n830)
);
AOI222X1TS U1057 ( .A0(n1119), .A1(n896), .B0(Data_array_SWR[9]), .B1(n893),
.C0(n1118), .C1(n1642), .Y(n1666) );
OR2X2TS U1058 ( .A(n1652), .B(n1065), .Y(n873) );
AOI2BB2X1TS U1059 ( .B0(n988), .B1(n987), .A0N(n986), .A1N(n985), .Y(n989)
);
OR2X2TS U1060 ( .A(n898), .B(Shift_amount_SHT1_EWR[0]), .Y(n1052) );
CLKBUFX3TS U1061 ( .A(n996), .Y(n889) );
INVX2TS U1062 ( .A(n1543), .Y(n1184) );
NOR2X1TS U1063 ( .A(n1131), .B(exp_rslt_NRM2_EW1[1]), .Y(n1003) );
INVX2TS U1064 ( .A(n1517), .Y(n1664) );
OAI211X1TS U1065 ( .A0(intDX_EWSW[8]), .A1(n1715), .B0(n937), .C0(n936), .Y(
n938) );
INVX2TS U1066 ( .A(n997), .Y(n891) );
NAND2BX1TS U1067 ( .AN(n1025), .B(n1024), .Y(n1028) );
NOR2X4TS U1068 ( .A(shift_value_SHT2_EWR[4]), .B(n1000), .Y(n996) );
NAND3X1TS U1069 ( .A(n1722), .B(n979), .C(intDX_EWSW[26]), .Y(n981) );
OAI211X2TS U1070 ( .A0(intDX_EWSW[20]), .A1(n1721), .B0(n970), .C0(n954),
.Y(n965) );
INVX3TS U1071 ( .A(n1426), .Y(n1550) );
OAI211X2TS U1072 ( .A0(intDX_EWSW[12]), .A1(n1718), .B0(n933), .C0(n924),
.Y(n935) );
OAI21X1TS U1073 ( .A0(intDX_EWSW[15]), .A1(n1677), .B0(intDX_EWSW[14]), .Y(
n929) );
INVX3TS U1074 ( .A(n1755), .Y(busy) );
NAND2BX1TS U1075 ( .AN(intDX_EWSW[21]), .B(intDY_EWSW[21]), .Y(n954) );
NAND2BX1TS U1076 ( .AN(intDX_EWSW[27]), .B(intDY_EWSW[27]), .Y(n979) );
NAND2BX1TS U1077 ( .AN(intDX_EWSW[19]), .B(intDY_EWSW[19]), .Y(n962) );
NAND2BX1TS U1078 ( .AN(intDX_EWSW[24]), .B(intDY_EWSW[24]), .Y(n973) );
NAND2BX1TS U1079 ( .AN(intDY_EWSW[27]), .B(intDX_EWSW[27]), .Y(n980) );
NAND3X1TS U1080 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n1674), .C(
n1704), .Y(n1458) );
NAND2BX1TS U1081 ( .AN(intDX_EWSW[13]), .B(intDY_EWSW[13]), .Y(n924) );
NAND2BX1TS U1082 ( .AN(intDX_EWSW[9]), .B(intDY_EWSW[9]), .Y(n937) );
NAND3X1TS U1083 ( .A(shift_value_SHT2_EWR[2]), .B(n875), .C(
shift_value_SHT2_EWR[3]), .Y(n877) );
OR3X1TS U1084 ( .A(shift_value_SHT2_EWR[4]), .B(shift_value_SHT2_EWR[2]),
.C(n1689), .Y(n997) );
ADDFHX2TS U1085 ( .A(n1412), .B(DMP_SFG[13]), .CI(n1411), .CO(n1417), .S(
n1413) );
NOR2X4TS U1086 ( .A(n1022), .B(n1026), .Y(n1445) );
NAND2X6TS U1087 ( .A(n1030), .B(n1691), .Y(n1151) );
NOR3X6TS U1088 ( .A(Raw_mant_NRM_SWR[8]), .B(Raw_mant_NRM_SWR[9]), .C(n1153),
.Y(n1030) );
NOR2X8TS U1089 ( .A(Raw_mant_NRM_SWR[6]), .B(n1151), .Y(n1446) );
AND2X4TS U1090 ( .A(n1532), .B(n991), .Y(n1259) );
BUFX3TS U1091 ( .A(n1259), .Y(n1273) );
INVX2TS U1092 ( .A(n1255), .Y(n1280) );
NAND3XLTS U1093 ( .A(n1715), .B(n937), .C(intDX_EWSW[8]), .Y(n925) );
NAND2BXLTS U1094 ( .AN(intDY_EWSW[9]), .B(intDX_EWSW[9]), .Y(n926) );
NAND2BXLTS U1095 ( .AN(intDX_EWSW[2]), .B(intDY_EWSW[2]), .Y(n943) );
INVX2TS U1096 ( .A(n934), .Y(n958) );
NOR2BX1TS U1097 ( .AN(n953), .B(n952), .Y(n957) );
NOR2BX1TS U1098 ( .AN(n939), .B(n938), .Y(n953) );
OAI32X1TS U1099 ( .A0(n951), .A1(n950), .A2(n949), .B0(n948), .B1(n950), .Y(
n952) );
NOR2BX1TS U1100 ( .AN(n955), .B(n960), .Y(n956) );
AOI211X2TS U1101 ( .A0(Raw_mant_NRM_SWR[6]), .A1(n1049), .B0(n1453), .C0(
n1048), .Y(n1051) );
NOR2X1TS U1102 ( .A(n1696), .B(n1029), .Y(n1041) );
NOR2XLTS U1103 ( .A(Raw_mant_NRM_SWR[17]), .B(Raw_mant_NRM_SWR[16]), .Y(
n1023) );
INVX2TS U1104 ( .A(n1490), .Y(n904) );
AND4X1TS U1105 ( .A(n1126), .B(n1121), .C(exp_rslt_NRM2_EW1[4]), .D(n1009),
.Y(n1010) );
NOR2XLTS U1106 ( .A(n1426), .B(n1739), .Y(n1428) );
NAND2X1TS U1107 ( .A(Raw_mant_NRM_SWR[12]), .B(n1037), .Y(n1441) );
AO21XLTS U1108 ( .A0(n1668), .A1(n1740), .B0(n1439), .Y(n1448) );
INVX2TS U1109 ( .A(n1399), .Y(n1218) );
NAND2X1TS U1110 ( .A(n1398), .B(n918), .Y(n1375) );
AOI222X1TS U1111 ( .A0(Raw_mant_NRM_SWR[6]), .A1(n905), .B0(n910), .B1(
DmP_mant_SHT1_SW[17]), .C0(n1349), .C1(DmP_mant_SHT1_SW[18]), .Y(n1339) );
AOI222X1TS U1112 ( .A0(Raw_mant_NRM_SWR[21]), .A1(n905), .B0(n910), .B1(
DmP_mant_SHT1_SW[2]), .C0(n1335), .C1(DmP_mant_SHT1_SW[3]), .Y(n1318)
);
AOI222X1TS U1113 ( .A0(Raw_mant_NRM_SWR[16]), .A1(n904), .B0(n910), .B1(
DmP_mant_SHT1_SW[7]), .C0(n1335), .C1(DmP_mant_SHT1_SW[8]), .Y(n1332)
);
AOI222X1TS U1114 ( .A0(Raw_mant_NRM_SWR[8]), .A1(n905), .B0(n910), .B1(
DmP_mant_SHT1_SW[15]), .C0(n1335), .C1(DmP_mant_SHT1_SW[16]), .Y(n1342) );
AOI222X1TS U1115 ( .A0(Raw_mant_NRM_SWR[17]), .A1(n904), .B0(n911), .B1(
DmP_mant_SHT1_SW[6]), .C0(n1335), .C1(DmP_mant_SHT1_SW[7]), .Y(n1353)
);
AO21XLTS U1116 ( .A0(n1553), .A1(DMP_SFG[1]), .B0(n1551), .Y(n1552) );
NOR2X4TS U1117 ( .A(n917), .B(n1457), .Y(n1634) );
INVX2TS U1118 ( .A(n1604), .Y(n1603) );
INVX2TS U1119 ( .A(n1376), .Y(n1377) );
INVX2TS U1120 ( .A(n1259), .Y(n1231) );
INVX2TS U1121 ( .A(n1259), .Y(n1211) );
NAND4XLTS U1122 ( .A(n1112), .B(n1111), .C(n1110), .D(n1109), .Y(n1113) );
NAND4XLTS U1123 ( .A(n1104), .B(n1103), .C(n1102), .D(n1101), .Y(n1114) );
NAND4XLTS U1124 ( .A(n1088), .B(n1087), .C(n1086), .D(n1085), .Y(n1116) );
INVX2TS U1125 ( .A(n1255), .Y(n1275) );
BUFX3TS U1126 ( .A(n1259), .Y(n1281) );
AO22XLTS U1127 ( .A0(n1468), .A1(Data_X[10]), .B0(n1467), .B1(intDX_EWSW[10]), .Y(n852) );
AO22XLTS U1128 ( .A0(n1469), .A1(Data_X[30]), .B0(n1471), .B1(intDX_EWSW[30]), .Y(n832) );
AO22XLTS U1129 ( .A0(n1468), .A1(Data_X[22]), .B0(n1479), .B1(intDX_EWSW[22]), .Y(n840) );
AO22XLTS U1130 ( .A0(n1470), .A1(Data_X[14]), .B0(n1467), .B1(intDX_EWSW[14]), .Y(n848) );
AO22XLTS U1131 ( .A0(n1469), .A1(Data_X[20]), .B0(n1479), .B1(intDX_EWSW[20]), .Y(n842) );
AO22XLTS U1132 ( .A0(n1468), .A1(Data_X[12]), .B0(n1467), .B1(intDX_EWSW[12]), .Y(n850) );
OAI21XLTS U1133 ( .A0(n1724), .A1(n1280), .B0(n1258), .Y(n730) );
AO22XLTS U1134 ( .A0(n1469), .A1(Data_X[31]), .B0(n1471), .B1(intDX_EWSW[31]), .Y(n831) );
AO22XLTS U1135 ( .A0(n1468), .A1(Data_X[19]), .B0(n1479), .B1(intDX_EWSW[19]), .Y(n843) );
AO22XLTS U1136 ( .A0(n1480), .A1(Data_X[18]), .B0(n1479), .B1(intDX_EWSW[18]), .Y(n844) );
AO22XLTS U1137 ( .A0(n1469), .A1(Data_X[9]), .B0(n1467), .B1(intDX_EWSW[9]),
.Y(n853) );
AO22XLTS U1138 ( .A0(n1468), .A1(Data_X[11]), .B0(n1467), .B1(intDX_EWSW[11]), .Y(n851) );
AO22XLTS U1139 ( .A0(n1469), .A1(Data_X[8]), .B0(n1467), .B1(intDX_EWSW[8]),
.Y(n854) );
AO22XLTS U1140 ( .A0(n1468), .A1(Data_X[17]), .B0(n1479), .B1(intDX_EWSW[17]), .Y(n845) );
AO22XLTS U1141 ( .A0(n1468), .A1(Data_X[13]), .B0(n1467), .B1(intDX_EWSW[13]), .Y(n849) );
AO22XLTS U1142 ( .A0(n1469), .A1(Data_X[21]), .B0(n1479), .B1(intDX_EWSW[21]), .Y(n841) );
AO22XLTS U1143 ( .A0(n1468), .A1(Data_X[15]), .B0(n1479), .B1(intDX_EWSW[15]), .Y(n847) );
AO22XLTS U1144 ( .A0(n1468), .A1(Data_X[28]), .B0(n1471), .B1(intDX_EWSW[28]), .Y(n834) );
AO22XLTS U1145 ( .A0(n1472), .A1(intDY_EWSW[5]), .B0(n1475), .B1(Data_Y[5]),
.Y(n823) );
AO22XLTS U1146 ( .A0(n1472), .A1(intDY_EWSW[4]), .B0(n1475), .B1(Data_Y[4]),
.Y(n824) );
AO22XLTS U1147 ( .A0(n1472), .A1(intDY_EWSW[6]), .B0(n1475), .B1(Data_Y[6]),
.Y(n822) );
AO22XLTS U1148 ( .A0(n1474), .A1(intDY_EWSW[16]), .B0(n1477), .B1(Data_Y[16]), .Y(n812) );
AO22XLTS U1149 ( .A0(n1472), .A1(intDY_EWSW[2]), .B0(n1475), .B1(Data_Y[2]),
.Y(n826) );
AO22XLTS U1150 ( .A0(n1472), .A1(intDY_EWSW[9]), .B0(n1476), .B1(Data_Y[9]),
.Y(n819) );
AO22XLTS U1151 ( .A0(n1472), .A1(intDY_EWSW[0]), .B0(n1476), .B1(Data_Y[0]),
.Y(n828) );
AO22XLTS U1152 ( .A0(n1472), .A1(intDY_EWSW[1]), .B0(n1475), .B1(Data_Y[1]),
.Y(n827) );
AO22XLTS U1153 ( .A0(n1472), .A1(intDY_EWSW[10]), .B0(n1476), .B1(Data_Y[10]), .Y(n818) );
AO22XLTS U1154 ( .A0(n1474), .A1(intDY_EWSW[19]), .B0(n1477), .B1(Data_Y[19]), .Y(n809) );
AO22XLTS U1155 ( .A0(n1471), .A1(intDY_EWSW[7]), .B0(n1475), .B1(Data_Y[7]),
.Y(n821) );
AO22XLTS U1156 ( .A0(n1478), .A1(intDY_EWSW[28]), .B0(n1473), .B1(Data_Y[28]), .Y(n800) );
AO22XLTS U1157 ( .A0(n1472), .A1(intDY_EWSW[3]), .B0(n1475), .B1(Data_Y[3]),
.Y(n825) );
AO22XLTS U1158 ( .A0(n1469), .A1(Data_X[7]), .B0(n1467), .B1(intDX_EWSW[7]),
.Y(n855) );
AO22XLTS U1159 ( .A0(n1474), .A1(intDY_EWSW[15]), .B0(n1477), .B1(Data_Y[15]), .Y(n813) );
AO22XLTS U1160 ( .A0(n1478), .A1(intDY_EWSW[22]), .B0(n1476), .B1(Data_Y[22]), .Y(n806) );
AO22XLTS U1161 ( .A0(n1476), .A1(Data_X[5]), .B0(n1467), .B1(intDX_EWSW[5]),
.Y(n857) );
AO22XLTS U1162 ( .A0(n1468), .A1(Data_X[16]), .B0(n1479), .B1(intDX_EWSW[16]), .Y(n846) );
AO22XLTS U1163 ( .A0(n1476), .A1(Data_X[6]), .B0(n1467), .B1(intDX_EWSW[6]),
.Y(n856) );
AO22XLTS U1164 ( .A0(n1474), .A1(intDY_EWSW[11]), .B0(n1476), .B1(Data_Y[11]), .Y(n817) );
AO22XLTS U1165 ( .A0(n1474), .A1(intDY_EWSW[17]), .B0(n1477), .B1(Data_Y[17]), .Y(n811) );
AO22XLTS U1166 ( .A0(n1474), .A1(intDY_EWSW[13]), .B0(n1477), .B1(Data_Y[13]), .Y(n815) );
AO22XLTS U1167 ( .A0(n1478), .A1(intDY_EWSW[21]), .B0(n1475), .B1(Data_Y[21]), .Y(n807) );
AO22XLTS U1168 ( .A0(n1472), .A1(intDY_EWSW[8]), .B0(n1476), .B1(Data_Y[8]),
.Y(n820) );
AO22XLTS U1169 ( .A0(n1474), .A1(intDY_EWSW[12]), .B0(n1475), .B1(Data_Y[12]), .Y(n816) );
AO22XLTS U1170 ( .A0(n1474), .A1(intDY_EWSW[14]), .B0(n1477), .B1(Data_Y[14]), .Y(n814) );
AO22XLTS U1171 ( .A0(n1474), .A1(intDY_EWSW[20]), .B0(n1475), .B1(Data_Y[20]), .Y(n808) );
AO22XLTS U1172 ( .A0(n1478), .A1(intDY_EWSW[30]), .B0(n1477), .B1(Data_Y[30]), .Y(n798) );
AO22XLTS U1173 ( .A0(n1474), .A1(intDY_EWSW[18]), .B0(n1477), .B1(Data_Y[18]), .Y(n810) );
OAI2BB2XLTS U1174 ( .B0(n928), .B1(n935), .A0N(n927), .A1N(n936), .Y(n931)
);
AOI222X1TS U1175 ( .A0(intDY_EWSW[4]), .A1(n1671), .B0(n947), .B1(n946),
.C0(intDY_EWSW[5]), .C1(n1685), .Y(n949) );
AOI2BB2XLTS U1176 ( .B0(intDX_EWSW[3]), .B1(n1710), .A0N(intDY_EWSW[2]),
.A1N(n945), .Y(n946) );
INVX2TS U1177 ( .A(n935), .Y(n939) );
AOI2BB1XLTS U1178 ( .A0N(n1040), .A1N(Raw_mant_NRM_SWR[23]), .B0(
Raw_mant_NRM_SWR[24]), .Y(n1043) );
CLKAND2X2TS U1179 ( .A(n1169), .B(shift_value_SHT2_EWR[4]), .Y(n1019) );
AOI22X1TS U1180 ( .A0(Data_array_SWR[21]), .A1(n1169), .B0(
Data_array_SWR[25]), .B1(n1170), .Y(n1177) );
NAND2X1TS U1181 ( .A(n1169), .B(n875), .Y(n1065) );
INVX2TS U1182 ( .A(n974), .Y(n975) );
INVX2TS U1183 ( .A(n1490), .Y(n903) );
CLKAND2X2TS U1184 ( .A(DMP_SFG[8]), .B(n1601), .Y(n1212) );
NOR4X2TS U1185 ( .A(n1041), .B(n1035), .C(n1158), .D(n1034), .Y(n1292) );
NOR2X1TS U1186 ( .A(n1215), .B(DMP_SFG[14]), .Y(n1403) );
NAND4XLTS U1187 ( .A(n1096), .B(n1095), .C(n1094), .D(n1093), .Y(n1115) );
CLKBUFX2TS U1188 ( .A(n1648), .Y(n1517) );
AOI222X1TS U1189 ( .A0(Raw_mant_NRM_SWR[20]), .A1(n904), .B0(n911), .B1(
DmP_mant_SHT1_SW[3]), .C0(n1335), .C1(DmP_mant_SHT1_SW[4]), .Y(n1322)
);
INVX2TS U1190 ( .A(n1460), .Y(n1459) );
OAI21XLTS U1191 ( .A0(n1673), .A1(n1156), .B0(n1440), .Y(n1157) );
NOR2XLTS U1192 ( .A(Raw_mant_NRM_SWR[8]), .B(Raw_mant_NRM_SWR[9]), .Y(n1154)
);
INVX2TS U1193 ( .A(n1445), .Y(n1450) );
AOI21X1TS U1194 ( .A0(n1417), .A1(n1221), .B0(n1220), .Y(n1385) );
OAI21X1TS U1195 ( .A0(n1405), .A1(n1414), .B0(n1406), .Y(n1397) );
INVX2TS U1196 ( .A(n1414), .Y(n1404) );
NAND2X1TS U1197 ( .A(n1215), .B(DMP_SFG[14]), .Y(n1414) );
INVX2TS U1198 ( .A(n1403), .Y(n1415) );
BUFX3TS U1199 ( .A(n1648), .Y(n1543) );
INVX2TS U1200 ( .A(n1517), .Y(n1542) );
AO21XLTS U1201 ( .A0(LZD_output_NRM2_EW[0]), .A1(n1496), .B0(n884), .Y(n515)
);
AO22XLTS U1202 ( .A0(n1464), .A1(busy), .B0(n1462), .B1(Shift_reg_FLAGS_7[3]), .Y(n866) );
AO22XLTS U1203 ( .A0(n1538), .A1(DmP_EXP_EWSW[19]), .B0(n1535), .B1(
DmP_mant_SHT1_SW[19]), .Y(n571) );
AO22XLTS U1204 ( .A0(n1670), .A1(DmP_EXP_EWSW[11]), .B0(n1530), .B1(
DmP_mant_SHT1_SW[11]), .Y(n587) );
AO22XLTS U1205 ( .A0(n1670), .A1(DmP_EXP_EWSW[9]), .B0(n1530), .B1(
DmP_mant_SHT1_SW[9]), .Y(n591) );
AO22XLTS U1206 ( .A0(n1538), .A1(DmP_EXP_EWSW[22]), .B0(n1535), .B1(
DmP_mant_SHT1_SW[22]), .Y(n565) );
AO22XLTS U1207 ( .A0(n1670), .A1(DmP_EXP_EWSW[12]), .B0(n1530), .B1(
DmP_mant_SHT1_SW[12]), .Y(n585) );
OAI211XLTS U1208 ( .A0(n1332), .A1(n1495), .B0(n1331), .C0(n1330), .Y(n780)
);
AO22XLTS U1209 ( .A0(n1480), .A1(Data_X[0]), .B0(n1466), .B1(intDX_EWSW[0]),
.Y(n862) );
AO22XLTS U1210 ( .A0(n1480), .A1(Data_X[2]), .B0(n1466), .B1(intDX_EWSW[2]),
.Y(n860) );
MX2X1TS U1211 ( .A(n1630), .B(DmP_mant_SFG_SWR[14]), .S0(n1661), .Y(n474) );
MX2X1TS U1212 ( .A(n1633), .B(DmP_mant_SFG_SWR[15]), .S0(n1661), .Y(n473) );
AO22XLTS U1213 ( .A0(n1480), .A1(Data_Y[31]), .B0(n1479), .B1(intDY_EWSW[31]), .Y(n797) );
AO22XLTS U1214 ( .A0(n1517), .A1(DMP_SHT2_EWSW[0]), .B0(n1515), .B1(
DMP_SFG[0]), .Y(n717) );
MX2X1TS U1215 ( .A(n1627), .B(DmP_mant_SFG_SWR[12]), .S0(n1661), .Y(n476) );
MX2X1TS U1216 ( .A(n1628), .B(DmP_mant_SFG_SWR[13]), .S0(n1661), .Y(n475) );
MX2X1TS U1217 ( .A(DMP_SFG[18]), .B(DMP_SHT2_EWSW[18]), .S0(n1525), .Y(n663)
);
MX2X1TS U1218 ( .A(DMP_SFG[20]), .B(DMP_SHT2_EWSW[20]), .S0(n1543), .Y(n657)
);
MX2X1TS U1219 ( .A(DMP_SFG[22]), .B(DMP_SHT2_EWSW[22]), .S0(n1648), .Y(n651)
);
MX2X1TS U1220 ( .A(DMP_SFG[19]), .B(DMP_SHT2_EWSW[19]), .S0(n1525), .Y(n660)
);
MX2X1TS U1221 ( .A(DMP_SFG[21]), .B(DMP_SHT2_EWSW[21]), .S0(n1543), .Y(n654)
);
MX2X1TS U1222 ( .A(DMP_SFG[12]), .B(DMP_SHT2_EWSW[12]), .S0(n1648), .Y(n681)
);
MX2X1TS U1223 ( .A(DMP_SFG[13]), .B(DMP_SHT2_EWSW[13]), .S0(n1648), .Y(n678)
);
MX2X1TS U1224 ( .A(DMP_exp_NRM2_EW[1]), .B(DMP_exp_NRM_EW[1]), .S0(n898),
.Y(n641) );
MX2X1TS U1225 ( .A(DMP_exp_NRM2_EW[2]), .B(DMP_exp_NRM_EW[2]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n636) );
MX2X1TS U1226 ( .A(DMP_exp_NRM2_EW[3]), .B(DMP_exp_NRM_EW[3]), .S0(n898),
.Y(n631) );
MX2X1TS U1227 ( .A(DMP_exp_NRM2_EW[4]), .B(DMP_exp_NRM_EW[4]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n626) );
AO22XLTS U1228 ( .A0(n1512), .A1(n1507), .B0(n1537), .B1(
Shift_amount_SHT1_EWR[1]), .Y(n765) );
AOI2BB2XLTS U1229 ( .B0(n1538), .B1(n1503), .A0N(Shift_amount_SHT1_EWR[0]),
.A1N(n1512), .Y(n766) );
AO22XLTS U1230 ( .A0(n1525), .A1(DMP_SHT2_EWSW[3]), .B0(n1515), .B1(
DMP_SFG[3]), .Y(n708) );
AO22XLTS U1231 ( .A0(n1536), .A1(DMP_SHT2_EWSW[5]), .B0(n1515), .B1(
DMP_SFG[5]), .Y(n702) );
AO22XLTS U1232 ( .A0(n1536), .A1(DMP_SHT2_EWSW[7]), .B0(n1542), .B1(
DMP_SFG[7]), .Y(n696) );
AO22XLTS U1233 ( .A0(n1528), .A1(DmP_EXP_EWSW[1]), .B0(n1529), .B1(
DmP_mant_SHT1_SW[1]), .Y(n607) );
AO22XLTS U1234 ( .A0(n1528), .A1(DmP_EXP_EWSW[5]), .B0(n1529), .B1(
DmP_mant_SHT1_SW[5]), .Y(n599) );
AO22XLTS U1235 ( .A0(n1528), .A1(DmP_EXP_EWSW[0]), .B0(n1529), .B1(
DmP_mant_SHT1_SW[0]), .Y(n609) );
AO22XLTS U1236 ( .A0(n1528), .A1(DmP_EXP_EWSW[2]), .B0(n1529), .B1(
DmP_mant_SHT1_SW[2]), .Y(n605) );
AO22XLTS U1237 ( .A0(n1670), .A1(DmP_EXP_EWSW[6]), .B0(n1529), .B1(
DmP_mant_SHT1_SW[6]), .Y(n597) );
AO22XLTS U1238 ( .A0(n1670), .A1(DmP_EXP_EWSW[15]), .B0(n1530), .B1(
DmP_mant_SHT1_SW[15]), .Y(n579) );
AO22XLTS U1239 ( .A0(n1670), .A1(DmP_EXP_EWSW[10]), .B0(n1530), .B1(
DmP_mant_SHT1_SW[10]), .Y(n589) );
AO22XLTS U1240 ( .A0(n1538), .A1(DmP_EXP_EWSW[18]), .B0(n1530), .B1(
DmP_mant_SHT1_SW[18]), .Y(n573) );
AO22XLTS U1241 ( .A0(n1670), .A1(DmP_EXP_EWSW[14]), .B0(n1530), .B1(
DmP_mant_SHT1_SW[14]), .Y(n581) );
AO22XLTS U1242 ( .A0(n1528), .A1(DmP_EXP_EWSW[4]), .B0(n1529), .B1(
DmP_mant_SHT1_SW[4]), .Y(n601) );
AO22XLTS U1243 ( .A0(n1670), .A1(DmP_EXP_EWSW[13]), .B0(n1530), .B1(
DmP_mant_SHT1_SW[13]), .Y(n583) );
AO22XLTS U1244 ( .A0(n1670), .A1(DmP_EXP_EWSW[8]), .B0(n1529), .B1(
DmP_mant_SHT1_SW[8]), .Y(n593) );
AO22XLTS U1245 ( .A0(n1538), .A1(DmP_EXP_EWSW[21]), .B0(n1535), .B1(
DmP_mant_SHT1_SW[21]), .Y(n567) );
AO22XLTS U1246 ( .A0(n1528), .A1(DmP_EXP_EWSW[3]), .B0(n1529), .B1(
DmP_mant_SHT1_SW[3]), .Y(n603) );
AO22XLTS U1247 ( .A0(n1670), .A1(DmP_EXP_EWSW[7]), .B0(n1529), .B1(
DmP_mant_SHT1_SW[7]), .Y(n595) );
AO22XLTS U1248 ( .A0(n1538), .A1(DmP_EXP_EWSW[16]), .B0(n1530), .B1(
DmP_mant_SHT1_SW[16]), .Y(n577) );
AO22XLTS U1249 ( .A0(n1538), .A1(DmP_EXP_EWSW[17]), .B0(n1530), .B1(
DmP_mant_SHT1_SW[17]), .Y(n575) );
AO22XLTS U1250 ( .A0(n1538), .A1(DmP_EXP_EWSW[20]), .B0(n1535), .B1(
DmP_mant_SHT1_SW[20]), .Y(n569) );
MX2X1TS U1251 ( .A(DMP_SFG[11]), .B(DMP_SHT2_EWSW[11]), .S0(n1648), .Y(n684)
);
MX2X1TS U1252 ( .A(DMP_SFG[15]), .B(DMP_SHT2_EWSW[15]), .S0(n1517), .Y(n672)
);
MX2X1TS U1253 ( .A(DMP_SFG[16]), .B(DMP_SHT2_EWSW[16]), .S0(n1525), .Y(n669)
);
AO22XLTS U1254 ( .A0(n1664), .A1(DMP_SFG[2]), .B0(n1525), .B1(
DMP_SHT2_EWSW[2]), .Y(n711) );
AO22XLTS U1255 ( .A0(n1664), .A1(DMP_SFG[4]), .B0(n1525), .B1(
DMP_SHT2_EWSW[4]), .Y(n705) );
AO22XLTS U1256 ( .A0(n1664), .A1(DMP_SFG[6]), .B0(n1525), .B1(
DMP_SHT2_EWSW[6]), .Y(n699) );
MX2X1TS U1257 ( .A(DMP_SFG[14]), .B(DMP_SHT2_EWSW[14]), .S0(n1648), .Y(n675)
);
AO22XLTS U1258 ( .A0(n1525), .A1(DMP_SHT2_EWSW[1]), .B0(n1515), .B1(
DMP_SFG[1]), .Y(n714) );
MX2X1TS U1259 ( .A(DMP_SFG[17]), .B(DMP_SHT2_EWSW[17]), .S0(n1525), .Y(n666)
);
AOI2BB2XLTS U1260 ( .B0(n1626), .B1(n1559), .A0N(Raw_mant_NRM_SWR[4]), .A1N(
n1558), .Y(n538) );
AO22XLTS U1261 ( .A0(n1469), .A1(Data_X[27]), .B0(n1471), .B1(intDX_EWSW[27]), .Y(n835) );
AO22XLTS U1262 ( .A0(n1469), .A1(Data_X[29]), .B0(n1471), .B1(intDX_EWSW[29]), .Y(n833) );
AOI2BB2XLTS U1263 ( .B0(n1626), .B1(n1617), .A0N(Raw_mant_NRM_SWR[12]),
.A1N(Shift_reg_FLAGS_7[2]), .Y(n530) );
AO22XLTS U1264 ( .A0(n1480), .A1(Data_X[1]), .B0(n1466), .B1(intDX_EWSW[1]),
.Y(n861) );
NAND3XLTS U1265 ( .A(busy), .B(Shift_amount_SHT1_EWR[4]), .C(n899), .Y(n1160) );
AO22XLTS U1266 ( .A0(n1469), .A1(Data_X[23]), .B0(n1479), .B1(intDX_EWSW[23]), .Y(n839) );
AO22XLTS U1267 ( .A0(n1480), .A1(Data_X[3]), .B0(n1466), .B1(intDX_EWSW[3]),
.Y(n859) );
AO22XLTS U1268 ( .A0(n1478), .A1(intDY_EWSW[27]), .B0(n1470), .B1(Data_Y[27]), .Y(n801) );
OAI2BB1X1TS U1269 ( .A0N(n1626), .A1N(n1226), .B0(n1225), .Y(n517) );
MX2X1TS U1270 ( .A(n1374), .B(Raw_mant_NRM_SWR[21]), .S0(n1433), .Y(n521) );
AO22XLTS U1271 ( .A0(n1471), .A1(intDX_EWSW[26]), .B0(n1476), .B1(Data_X[26]), .Y(n836) );
AO22XLTS U1272 ( .A0(n1478), .A1(intDY_EWSW[24]), .B0(n1473), .B1(Data_Y[24]), .Y(n804) );
AO21XLTS U1273 ( .A0(n1577), .A1(n1576), .B0(n1585), .Y(n1581) );
MX2X1TS U1274 ( .A(DMP_SFG[9]), .B(DMP_SHT2_EWSW[9]), .S0(n1543), .Y(n690)
);
NAND2BXLTS U1275 ( .AN(n1568), .B(n1566), .Y(n1563) );
AO21XLTS U1276 ( .A0(n1570), .A1(n1567), .B0(n1569), .Y(n1564) );
MX2X1TS U1277 ( .A(n1421), .B(Raw_mant_NRM_SWR[14]), .S0(n1527), .Y(n528) );
AOI2BB2XLTS U1278 ( .B0(beg_OP), .B1(n1674), .A0N(n1674), .A1N(
inst_FSM_INPUT_ENABLE_state_reg[2]), .Y(n995) );
AO21XLTS U1279 ( .A0(n1545), .A1(n879), .B0(n1553), .Y(n1546) );
MX2X1TS U1280 ( .A(DMP_exp_NRM2_EW[0]), .B(DMP_exp_NRM_EW[0]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n646) );
MX2X1TS U1281 ( .A(DMP_exp_NRM2_EW[5]), .B(DMP_exp_NRM_EW[5]), .S0(n898),
.Y(n621) );
MX2X1TS U1282 ( .A(DMP_exp_NRM2_EW[6]), .B(DMP_exp_NRM_EW[6]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n616) );
MX2X1TS U1283 ( .A(DMP_exp_NRM2_EW[7]), .B(DMP_exp_NRM_EW[7]), .S0(n898),
.Y(n611) );
MX2X1TS U1284 ( .A(OP_FLAG_SFG), .B(OP_FLAG_SHT2), .S0(n1543), .Y(n549) );
MX2X1TS U1285 ( .A(DMP_SFG[8]), .B(DMP_SHT2_EWSW[8]), .S0(n1543), .Y(n693)
);
MX2X1TS U1286 ( .A(DMP_SFG[10]), .B(DMP_SHT2_EWSW[10]), .S0(n1543), .Y(n687)
);
AO22XLTS U1287 ( .A0(Shift_reg_FLAGS_7[0]), .A1(ZERO_FLAG_SHT1SHT2), .B0(
n1632), .B1(zero_flag), .Y(n552) );
AO22XLTS U1288 ( .A0(n1480), .A1(Data_X[4]), .B0(n1466), .B1(intDX_EWSW[4]),
.Y(n858) );
AO22XLTS U1289 ( .A0(n1478), .A1(intDY_EWSW[29]), .B0(n1477), .B1(Data_Y[29]), .Y(n799) );
AO22XLTS U1290 ( .A0(n1471), .A1(intDX_EWSW[25]), .B0(n1476), .B1(Data_X[25]), .Y(n837) );
AO22XLTS U1291 ( .A0(n1478), .A1(intDY_EWSW[25]), .B0(n1473), .B1(Data_Y[25]), .Y(n803) );
AO22XLTS U1292 ( .A0(n1478), .A1(intDY_EWSW[26]), .B0(n1473), .B1(Data_Y[26]), .Y(n802) );
AO22XLTS U1293 ( .A0(n1478), .A1(intDY_EWSW[23]), .B0(n1473), .B1(Data_Y[23]), .Y(n805) );
AO21XLTS U1294 ( .A0(n1594), .A1(n1593), .B0(n1592), .Y(n1598) );
AO22XLTS U1295 ( .A0(n1471), .A1(intDX_EWSW[24]), .B0(n1477), .B1(Data_X[24]), .Y(n838) );
MX2X1TS U1296 ( .A(n1629), .B(DmP_mant_SFG_SWR[11]), .S0(n1661), .Y(n477) );
MX2X1TS U1297 ( .A(n1631), .B(DmP_mant_SFG_SWR[10]), .S0(n1661), .Y(n478) );
AO21XLTS U1298 ( .A0(LZD_output_NRM2_EW[1]), .A1(n1496), .B0(n1454), .Y(n513) );
MX2X1TS U1299 ( .A(n1390), .B(Raw_mant_NRM_SWR[22]), .S0(n1433), .Y(n520) );
MX2X1TS U1300 ( .A(n1387), .B(Raw_mant_NRM_SWR[20]), .S0(n1433), .Y(n522) );
MX2X1TS U1301 ( .A(n1384), .B(Raw_mant_NRM_SWR[19]), .S0(n1433), .Y(n523) );
NAND2X1TS U1302 ( .A(n1381), .B(n1380), .Y(n1382) );
AOI21X1TS U1303 ( .A0(n1417), .A1(n1378), .B0(n1377), .Y(n1383) );
MX2X1TS U1304 ( .A(n1402), .B(Raw_mant_NRM_SWR[18]), .S0(n1433), .Y(n524) );
XOR2X1TS U1305 ( .A(n1401), .B(n1400), .Y(n1402) );
NAND2X1TS U1306 ( .A(n918), .B(n1399), .Y(n1400) );
AOI21X1TS U1307 ( .A0(n1417), .A1(n1398), .B0(n1397), .Y(n1401) );
MX2X1TS U1308 ( .A(n1410), .B(Raw_mant_NRM_SWR[17]), .S0(n1684), .Y(n525) );
XOR2X1TS U1309 ( .A(n1409), .B(n1408), .Y(n1410) );
NAND2X1TS U1310 ( .A(n1407), .B(n1406), .Y(n1408) );
AOI21X1TS U1311 ( .A0(n1417), .A1(n1415), .B0(n1404), .Y(n1409) );
MX2X1TS U1312 ( .A(n1418), .B(Raw_mant_NRM_SWR[16]), .S0(n1684), .Y(n526) );
XNOR2X1TS U1313 ( .A(n1417), .B(n1416), .Y(n1418) );
NAND2X1TS U1314 ( .A(n1415), .B(n1414), .Y(n1416) );
MX2X1TS U1315 ( .A(n1413), .B(Raw_mant_NRM_SWR[15]), .S0(n1684), .Y(n527) );
AO22XLTS U1316 ( .A0(n898), .A1(SIGN_FLAG_NRM), .B0(n1496), .B1(
SIGN_FLAG_SHT1SHT2), .Y(n544) );
AO22XLTS U1317 ( .A0(n1626), .A1(SIGN_FLAG_SFG), .B0(n1607), .B1(
SIGN_FLAG_NRM), .Y(n545) );
AO22XLTS U1318 ( .A0(n1543), .A1(SIGN_FLAG_SHT2), .B0(n1542), .B1(
SIGN_FLAG_SFG), .Y(n546) );
AO22XLTS U1319 ( .A0(n1801), .A1(SIGN_FLAG_SHT1), .B0(n1541), .B1(
SIGN_FLAG_SHT2), .Y(n547) );
AO22XLTS U1320 ( .A0(n1540), .A1(SIGN_FLAG_EXP), .B0(n1539), .B1(
SIGN_FLAG_SHT1), .Y(n548) );
AO22XLTS U1321 ( .A0(n1801), .A1(OP_FLAG_SHT1), .B0(OP_FLAG_SHT2), .B1(n1755), .Y(n1754) );
AO22XLTS U1322 ( .A0(n1538), .A1(OP_FLAG_EXP), .B0(n1537), .B1(OP_FLAG_SHT1),
.Y(n551) );
AO22XLTS U1323 ( .A0(n898), .A1(ZERO_FLAG_NRM), .B0(n1496), .B1(
ZERO_FLAG_SHT1SHT2), .Y(n553) );
AO22XLTS U1324 ( .A0(n1558), .A1(ZERO_FLAG_SFG), .B0(n1607), .B1(
ZERO_FLAG_NRM), .Y(n554) );
AO22XLTS U1325 ( .A0(n1536), .A1(ZERO_FLAG_SHT2), .B0(n1542), .B1(
ZERO_FLAG_SFG), .Y(n555) );
AO22XLTS U1326 ( .A0(n1801), .A1(ZERO_FLAG_SHT1), .B0(n1541), .B1(
ZERO_FLAG_SHT2), .Y(n556) );
AO22XLTS U1327 ( .A0(n1538), .A1(ZERO_FLAG_EXP), .B0(n1535), .B1(
ZERO_FLAG_SHT1), .Y(n557) );
OAI21XLTS U1328 ( .A0(n1727), .A1(n1231), .B0(n1204), .Y(n574) );
OAI21XLTS U1329 ( .A0(n1677), .A1(n1231), .B0(n1230), .Y(n580) );
OAI21XLTS U1330 ( .A0(n1719), .A1(n1231), .B0(n1206), .Y(n582) );
OAI21XLTS U1331 ( .A0(n1713), .A1(n1231), .B0(n1228), .Y(n584) );
OAI21XLTS U1332 ( .A0(n1718), .A1(n1231), .B0(n1208), .Y(n586) );
OAI21XLTS U1333 ( .A0(n1712), .A1(n1211), .B0(n1210), .Y(n592) );
OAI21XLTS U1334 ( .A0(n1715), .A1(n1211), .B0(n1209), .Y(n594) );
OAI21XLTS U1335 ( .A0(n1703), .A1(n1211), .B0(n1197), .Y(n596) );
OAI21XLTS U1336 ( .A0(n1710), .A1(n1211), .B0(n1195), .Y(n604) );
AO22XLTS U1337 ( .A0(n1558), .A1(DMP_SFG[30]), .B0(n1607), .B1(
DMP_exp_NRM_EW[7]), .Y(n612) );
AO22XLTS U1338 ( .A0(n1536), .A1(DMP_SHT2_EWSW[30]), .B0(n1542), .B1(
DMP_SFG[30]), .Y(n613) );
AO22XLTS U1339 ( .A0(n1801), .A1(DMP_SHT1_EWSW[30]), .B0(n1541), .B1(
DMP_SHT2_EWSW[30]), .Y(n614) );
AO22XLTS U1340 ( .A0(n1528), .A1(DMP_EXP_EWSW[30]), .B0(n1529), .B1(
DMP_SHT1_EWSW[30]), .Y(n615) );
AO22XLTS U1341 ( .A0(n1558), .A1(DMP_SFG[29]), .B0(n1607), .B1(
DMP_exp_NRM_EW[6]), .Y(n617) );
AO22XLTS U1342 ( .A0(n1536), .A1(DMP_SHT2_EWSW[29]), .B0(n1542), .B1(
DMP_SFG[29]), .Y(n618) );
AO22XLTS U1343 ( .A0(n1801), .A1(DMP_SHT1_EWSW[29]), .B0(n1541), .B1(
DMP_SHT2_EWSW[29]), .Y(n619) );
AO22XLTS U1344 ( .A0(n1528), .A1(DMP_EXP_EWSW[29]), .B0(n1539), .B1(
DMP_SHT1_EWSW[29]), .Y(n620) );
AO22XLTS U1345 ( .A0(n1558), .A1(DMP_SFG[28]), .B0(n1527), .B1(
DMP_exp_NRM_EW[5]), .Y(n622) );
AO22XLTS U1346 ( .A0(n1536), .A1(DMP_SHT2_EWSW[28]), .B0(n1542), .B1(
DMP_SFG[28]), .Y(n623) );
AO22XLTS U1347 ( .A0(n1801), .A1(DMP_SHT1_EWSW[28]), .B0(n1541), .B1(
DMP_SHT2_EWSW[28]), .Y(n624) );
AO22XLTS U1348 ( .A0(n1528), .A1(DMP_EXP_EWSW[28]), .B0(n1539), .B1(
DMP_SHT1_EWSW[28]), .Y(n625) );
AO22XLTS U1349 ( .A0(n1558), .A1(DMP_SFG[27]), .B0(n1607), .B1(
DMP_exp_NRM_EW[4]), .Y(n627) );
AO22XLTS U1350 ( .A0(n1536), .A1(DMP_SHT2_EWSW[27]), .B0(n1542), .B1(
DMP_SFG[27]), .Y(n628) );
AO22XLTS U1351 ( .A0(n1801), .A1(DMP_SHT1_EWSW[27]), .B0(n1541), .B1(
DMP_SHT2_EWSW[27]), .Y(n629) );
AO22XLTS U1352 ( .A0(n1528), .A1(DMP_EXP_EWSW[27]), .B0(n1539), .B1(
DMP_SHT1_EWSW[27]), .Y(n630) );
AO22XLTS U1353 ( .A0(n1558), .A1(DMP_SFG[26]), .B0(n1607), .B1(
DMP_exp_NRM_EW[3]), .Y(n632) );
AO22XLTS U1354 ( .A0(n1536), .A1(DMP_SHT2_EWSW[26]), .B0(n1542), .B1(
DMP_SFG[26]), .Y(n633) );
AO22XLTS U1355 ( .A0(n1526), .A1(DMP_SHT1_EWSW[26]), .B0(n1541), .B1(
DMP_SHT2_EWSW[26]), .Y(n634) );
AO22XLTS U1356 ( .A0(n1540), .A1(DMP_EXP_EWSW[26]), .B0(n1539), .B1(
DMP_SHT1_EWSW[26]), .Y(n635) );
AO22XLTS U1357 ( .A0(n1558), .A1(DMP_SFG[25]), .B0(n1527), .B1(
DMP_exp_NRM_EW[2]), .Y(n637) );
AO22XLTS U1358 ( .A0(n1525), .A1(DMP_SHT2_EWSW[25]), .B0(n1664), .B1(
DMP_SFG[25]), .Y(n638) );
AO22XLTS U1359 ( .A0(n1524), .A1(DMP_SHT1_EWSW[25]), .B0(n1541), .B1(
DMP_SHT2_EWSW[25]), .Y(n639) );
AO22XLTS U1360 ( .A0(n1540), .A1(DMP_EXP_EWSW[25]), .B0(n1539), .B1(
DMP_SHT1_EWSW[25]), .Y(n640) );
AO22XLTS U1361 ( .A0(n1558), .A1(DMP_SFG[24]), .B0(n1527), .B1(
DMP_exp_NRM_EW[1]), .Y(n642) );
AO22XLTS U1362 ( .A0(n1536), .A1(DMP_SHT2_EWSW[24]), .B0(n1542), .B1(
DMP_SFG[24]), .Y(n643) );
AO22XLTS U1363 ( .A0(n1526), .A1(DMP_SHT1_EWSW[24]), .B0(n1541), .B1(
DMP_SHT2_EWSW[24]), .Y(n644) );
AO22XLTS U1364 ( .A0(n1540), .A1(DMP_EXP_EWSW[24]), .B0(n1539), .B1(
DMP_SHT1_EWSW[24]), .Y(n645) );
AO22XLTS U1365 ( .A0(n1558), .A1(DMP_SFG[23]), .B0(n1527), .B1(
DMP_exp_NRM_EW[0]), .Y(n647) );
AO22XLTS U1366 ( .A0(n1536), .A1(DMP_SHT2_EWSW[23]), .B0(n1542), .B1(
DMP_SFG[23]), .Y(n648) );
AO22XLTS U1367 ( .A0(n1526), .A1(DMP_SHT1_EWSW[23]), .B0(n1522), .B1(
DMP_SHT2_EWSW[23]), .Y(n649) );
AO22XLTS U1368 ( .A0(n1540), .A1(DMP_EXP_EWSW[23]), .B0(n1539), .B1(
DMP_SHT1_EWSW[23]), .Y(n650) );
AO22XLTS U1369 ( .A0(n1526), .A1(DMP_SHT1_EWSW[22]), .B0(n1522), .B1(
DMP_SHT2_EWSW[22]), .Y(n652) );
AO22XLTS U1370 ( .A0(n1540), .A1(DMP_EXP_EWSW[22]), .B0(n1539), .B1(
DMP_SHT1_EWSW[22]), .Y(n653) );
AO22XLTS U1371 ( .A0(n1526), .A1(DMP_SHT1_EWSW[21]), .B0(n1522), .B1(
DMP_SHT2_EWSW[21]), .Y(n655) );
AO22XLTS U1372 ( .A0(n1540), .A1(DMP_EXP_EWSW[21]), .B0(n1539), .B1(
DMP_SHT1_EWSW[21]), .Y(n656) );
AO22XLTS U1373 ( .A0(n1526), .A1(DMP_SHT1_EWSW[20]), .B0(n1522), .B1(
DMP_SHT2_EWSW[20]), .Y(n658) );
AO22XLTS U1374 ( .A0(n1540), .A1(DMP_EXP_EWSW[20]), .B0(n1521), .B1(
DMP_SHT1_EWSW[20]), .Y(n659) );
AO22XLTS U1375 ( .A0(n1526), .A1(DMP_SHT1_EWSW[19]), .B0(n1522), .B1(
DMP_SHT2_EWSW[19]), .Y(n661) );
AO22XLTS U1376 ( .A0(n1540), .A1(DMP_EXP_EWSW[19]), .B0(n1521), .B1(
DMP_SHT1_EWSW[19]), .Y(n662) );
AO22XLTS U1377 ( .A0(n1526), .A1(DMP_SHT1_EWSW[18]), .B0(n1522), .B1(
DMP_SHT2_EWSW[18]), .Y(n664) );
AO22XLTS U1378 ( .A0(n1540), .A1(DMP_EXP_EWSW[18]), .B0(n1521), .B1(
DMP_SHT1_EWSW[18]), .Y(n665) );
AO22XLTS U1379 ( .A0(n1526), .A1(DMP_SHT1_EWSW[17]), .B0(n1522), .B1(
DMP_SHT2_EWSW[17]), .Y(n667) );
AO22XLTS U1380 ( .A0(n1520), .A1(DMP_EXP_EWSW[17]), .B0(n1521), .B1(
DMP_SHT1_EWSW[17]), .Y(n668) );
AO22XLTS U1381 ( .A0(n1526), .A1(DMP_SHT1_EWSW[16]), .B0(n1522), .B1(
DMP_SHT2_EWSW[16]), .Y(n670) );
AO22XLTS U1382 ( .A0(n1520), .A1(DMP_EXP_EWSW[16]), .B0(n1521), .B1(
DMP_SHT1_EWSW[16]), .Y(n671) );
AO22XLTS U1383 ( .A0(n1524), .A1(DMP_SHT1_EWSW[15]), .B0(n1522), .B1(
DMP_SHT2_EWSW[15]), .Y(n673) );
AO22XLTS U1384 ( .A0(n1520), .A1(DMP_EXP_EWSW[15]), .B0(n1521), .B1(
DMP_SHT1_EWSW[15]), .Y(n674) );
AO22XLTS U1385 ( .A0(n1524), .A1(DMP_SHT1_EWSW[14]), .B0(n1522), .B1(
DMP_SHT2_EWSW[14]), .Y(n676) );
AO22XLTS U1386 ( .A0(n1520), .A1(DMP_EXP_EWSW[14]), .B0(n1521), .B1(
DMP_SHT1_EWSW[14]), .Y(n677) );
AO22XLTS U1387 ( .A0(n1524), .A1(DMP_SHT1_EWSW[13]), .B0(n1519), .B1(
DMP_SHT2_EWSW[13]), .Y(n679) );
AO22XLTS U1388 ( .A0(n1520), .A1(DMP_EXP_EWSW[13]), .B0(n1521), .B1(
DMP_SHT1_EWSW[13]), .Y(n680) );
AO22XLTS U1389 ( .A0(n1524), .A1(DMP_SHT1_EWSW[12]), .B0(n1519), .B1(
DMP_SHT2_EWSW[12]), .Y(n682) );
AO22XLTS U1390 ( .A0(n1520), .A1(DMP_EXP_EWSW[12]), .B0(n1521), .B1(
DMP_SHT1_EWSW[12]), .Y(n683) );
AO22XLTS U1391 ( .A0(n1524), .A1(DMP_SHT1_EWSW[11]), .B0(n1519), .B1(
DMP_SHT2_EWSW[11]), .Y(n685) );
AO22XLTS U1392 ( .A0(n1520), .A1(DMP_EXP_EWSW[11]), .B0(n1521), .B1(
DMP_SHT1_EWSW[11]), .Y(n686) );
AO22XLTS U1393 ( .A0(n1524), .A1(DMP_SHT1_EWSW[10]), .B0(n1519), .B1(
DMP_SHT2_EWSW[10]), .Y(n688) );
AO22XLTS U1394 ( .A0(n1520), .A1(DMP_EXP_EWSW[10]), .B0(n1518), .B1(
DMP_SHT1_EWSW[10]), .Y(n689) );
AO22XLTS U1395 ( .A0(n1524), .A1(DMP_SHT1_EWSW[9]), .B0(n1519), .B1(
DMP_SHT2_EWSW[9]), .Y(n691) );
AO22XLTS U1396 ( .A0(n1520), .A1(DMP_EXP_EWSW[9]), .B0(n1518), .B1(
DMP_SHT1_EWSW[9]), .Y(n692) );
AO22XLTS U1397 ( .A0(n1524), .A1(DMP_SHT1_EWSW[8]), .B0(n1519), .B1(
DMP_SHT2_EWSW[8]), .Y(n694) );
AO22XLTS U1398 ( .A0(n1520), .A1(DMP_EXP_EWSW[8]), .B0(n1518), .B1(
DMP_SHT1_EWSW[8]), .Y(n695) );
AO22XLTS U1399 ( .A0(n1524), .A1(DMP_SHT1_EWSW[7]), .B0(n1519), .B1(
DMP_SHT2_EWSW[7]), .Y(n697) );
AO22XLTS U1400 ( .A0(n1516), .A1(DMP_EXP_EWSW[7]), .B0(n1518), .B1(
DMP_SHT1_EWSW[7]), .Y(n698) );
AO22XLTS U1401 ( .A0(busy), .A1(DMP_SHT1_EWSW[6]), .B0(n1519), .B1(
DMP_SHT2_EWSW[6]), .Y(n700) );
AO22XLTS U1402 ( .A0(n1516), .A1(DMP_EXP_EWSW[6]), .B0(n1518), .B1(
DMP_SHT1_EWSW[6]), .Y(n701) );
AO22XLTS U1403 ( .A0(busy), .A1(DMP_SHT1_EWSW[5]), .B0(n1519), .B1(
DMP_SHT2_EWSW[5]), .Y(n703) );
AO22XLTS U1404 ( .A0(n1516), .A1(DMP_EXP_EWSW[5]), .B0(n1518), .B1(
DMP_SHT1_EWSW[5]), .Y(n704) );
AO22XLTS U1405 ( .A0(busy), .A1(DMP_SHT1_EWSW[4]), .B0(n1519), .B1(
DMP_SHT2_EWSW[4]), .Y(n706) );
AO22XLTS U1406 ( .A0(n1516), .A1(DMP_EXP_EWSW[4]), .B0(n1518), .B1(
DMP_SHT1_EWSW[4]), .Y(n707) );
AO22XLTS U1407 ( .A0(busy), .A1(DMP_SHT1_EWSW[3]), .B0(n1755), .B1(
DMP_SHT2_EWSW[3]), .Y(n709) );
AO22XLTS U1408 ( .A0(n1516), .A1(DMP_EXP_EWSW[3]), .B0(n1518), .B1(
DMP_SHT1_EWSW[3]), .Y(n710) );
AO22XLTS U1409 ( .A0(busy), .A1(DMP_SHT1_EWSW[2]), .B0(n1755), .B1(
DMP_SHT2_EWSW[2]), .Y(n712) );
AO22XLTS U1410 ( .A0(n1516), .A1(DMP_EXP_EWSW[2]), .B0(n1518), .B1(
DMP_SHT1_EWSW[2]), .Y(n713) );
AO22XLTS U1411 ( .A0(busy), .A1(DMP_SHT1_EWSW[1]), .B0(n1755), .B1(
DMP_SHT2_EWSW[1]), .Y(n715) );
AO22XLTS U1412 ( .A0(n1516), .A1(DMP_EXP_EWSW[1]), .B0(n1518), .B1(
DMP_SHT1_EWSW[1]), .Y(n716) );
AO22XLTS U1413 ( .A0(busy), .A1(DMP_SHT1_EWSW[0]), .B0(n1755), .B1(
DMP_SHT2_EWSW[0]), .Y(n718) );
AO22XLTS U1414 ( .A0(n1516), .A1(DMP_EXP_EWSW[0]), .B0(n1752), .B1(
DMP_SHT1_EWSW[0]), .Y(n719) );
AO22XLTS U1415 ( .A0(n1246), .A1(n1513), .B0(ZERO_FLAG_EXP), .B1(n1514), .Y(
n721) );
AO21XLTS U1416 ( .A0(OP_FLAG_EXP), .A1(n1514), .B0(n1513), .Y(n722) );
OAI21XLTS U1417 ( .A0(n1725), .A1(n1280), .B0(n1257), .Y(n723) );
OAI21XLTS U1418 ( .A0(n1714), .A1(n1280), .B0(n1279), .Y(n732) );
OAI21XLTS U1419 ( .A0(n1680), .A1(n1280), .B0(n1270), .Y(n734) );
OAI21XLTS U1420 ( .A0(n1727), .A1(n1280), .B0(n1261), .Y(n735) );
OAI21XLTS U1421 ( .A0(n1719), .A1(n1275), .B0(n1262), .Y(n739) );
OAI21XLTS U1422 ( .A0(n1713), .A1(n1275), .B0(n992), .Y(n740) );
OAI21XLTS U1423 ( .A0(n1688), .A1(n1275), .B0(n1274), .Y(n743) );
OAI21XLTS U1424 ( .A0(n1712), .A1(n1275), .B0(n1271), .Y(n744) );
OAI21XLTS U1425 ( .A0(n1703), .A1(n1275), .B0(n1267), .Y(n746) );
AO22XLTS U1426 ( .A0(n1516), .A1(n1081), .B0(n1752), .B1(
Shift_amount_SHT1_EWR[4]), .Y(n762) );
AO22XLTS U1427 ( .A0(n1516), .A1(n1076), .B0(n1752), .B1(
Shift_amount_SHT1_EWR[3]), .Y(n763) );
AO22XLTS U1428 ( .A0(n1512), .A1(n1511), .B0(n1752), .B1(
Shift_amount_SHT1_EWR[2]), .Y(n764) );
AO22XLTS U1429 ( .A0(n1462), .A1(n1532), .B0(n1464), .B1(n1465), .Y(n869) );
NOR2X2TS U1430 ( .A(n1051), .B(n899), .Y(n1488) );
INVX2TS U1431 ( .A(n1343), .Y(n885) );
NAND2X4TS U1432 ( .A(n898), .B(n1051), .Y(n1490) );
NAND2X4TS U1433 ( .A(n1198), .B(n1500), .Y(n1495) );
INVX2TS U1434 ( .A(Shift_reg_FLAGS_7[1]), .Y(n1496) );
BUFX3TS U1435 ( .A(left_right_SHT2), .Y(n1371) );
CLKINVX3TS U1436 ( .A(rst), .Y(n1069) );
CLKINVX6TS U1437 ( .A(n883), .Y(n884) );
INVX2TS U1438 ( .A(n877), .Y(n887) );
INVX2TS U1439 ( .A(n877), .Y(n888) );
INVX2TS U1440 ( .A(n997), .Y(n890) );
INVX2TS U1441 ( .A(n878), .Y(n892) );
INVX2TS U1442 ( .A(n878), .Y(n893) );
INVX2TS U1443 ( .A(n873), .Y(n894) );
INVX2TS U1444 ( .A(n873), .Y(n895) );
INVX2TS U1445 ( .A(n1371), .Y(n896) );
INVX2TS U1446 ( .A(n896), .Y(n897) );
INVX2TS U1447 ( .A(n1496), .Y(n898) );
INVX2TS U1448 ( .A(Shift_reg_FLAGS_7[1]), .Y(n899) );
INVX2TS U1449 ( .A(n1312), .Y(n900) );
INVX2TS U1450 ( .A(n1312), .Y(n901) );
INVX2TS U1451 ( .A(n1312), .Y(n902) );
INVX2TS U1452 ( .A(n1495), .Y(n906) );
INVX2TS U1453 ( .A(n906), .Y(n908) );
INVX2TS U1454 ( .A(n1052), .Y(n909) );
INVX2TS U1455 ( .A(n1052), .Y(n910) );
INVX2TS U1456 ( .A(n1052), .Y(n911) );
OAI211XLTS U1457 ( .A0(n1318), .A1(n902), .B0(n1317), .C0(n1316), .Y(n773)
);
BUFX3TS U1458 ( .A(n1069), .Y(n1068) );
CLKBUFX3TS U1459 ( .A(n1069), .Y(n1070) );
OAI21X2TS U1460 ( .A0(n1550), .A1(n1736), .B0(n1429), .Y(n1583) );
AOI222X1TS U1461 ( .A0(n1173), .A1(n1371), .B0(Data_array_SWR[6]), .B1(n895),
.C0(n1172), .C1(n1179), .Y(n1638) );
AOI222X1TS U1462 ( .A0(n1181), .A1(n897), .B0(Data_array_SWR[7]), .B1(n895),
.C0(n1180), .C1(n1179), .Y(n1637) );
AOI222X1TS U1463 ( .A0(n1644), .A1(left_right_SHT2), .B0(Data_array_SWR[4]),
.B1(n895), .C0(n1643), .C1(n1179), .Y(n1647) );
AOI222X1TS U1464 ( .A0(n1640), .A1(n1371), .B0(Data_array_SWR[5]), .B1(n895),
.C0(n1639), .C1(n1179), .Y(n1641) );
AOI222X1TS U1465 ( .A0(n1119), .A1(n1371), .B0(Data_array_SWR[9]), .B1(n895),
.C0(n1118), .C1(n1179), .Y(n1635) );
NOR2X4TS U1466 ( .A(shift_value_SHT2_EWR[4]), .B(n897), .Y(n1179) );
OAI21X2TS U1467 ( .A0(n1550), .A1(n1737), .B0(n1549), .Y(n1554) );
AOI222X1TS U1468 ( .A0(Raw_mant_NRM_SWR[12]), .A1(n903), .B0(n910), .B1(
DmP_mant_SHT1_SW[11]), .C0(n1335), .C1(DmP_mant_SHT1_SW[12]), .Y(n1344) );
AOI222X1TS U1469 ( .A0(Raw_mant_NRM_SWR[14]), .A1(n905), .B0(n911), .B1(
DmP_mant_SHT1_SW[9]), .C0(n1335), .C1(DmP_mant_SHT1_SW[10]), .Y(n1348)
);
AOI222X4TS U1470 ( .A0(Data_array_SWR[24]), .A1(n888), .B0(
Data_array_SWR[20]), .B1(n891), .C0(Data_array_SWR[16]), .C1(n996),
.Y(n1364) );
AOI222X4TS U1471 ( .A0(Data_array_SWR[24]), .A1(n1016), .B0(
Data_array_SWR[20]), .B1(n1170), .C0(Data_array_SWR[16]), .C1(n1169),
.Y(n1148) );
AOI222X4TS U1472 ( .A0(Data_array_SWR[21]), .A1(n1170), .B0(
Data_array_SWR[17]), .B1(n1169), .C0(Data_array_SWR[25]), .C1(n1016),
.Y(n1141) );
AOI222X4TS U1473 ( .A0(Data_array_SWR[21]), .A1(n891), .B0(
Data_array_SWR[17]), .B1(n996), .C0(Data_array_SWR[25]), .C1(n888),
.Y(n1363) );
AOI222X4TS U1474 ( .A0(Data_array_SWR[14]), .A1(n996), .B0(
Data_array_SWR[22]), .B1(n888), .C0(Data_array_SWR[18]), .C1(n891),
.Y(n1370) );
AOI221X1TS U1475 ( .A0(n1688), .A1(intDX_EWSW[10]), .B0(intDX_EWSW[11]),
.B1(n1697), .C0(n1098), .Y(n1103) );
AOI221X1TS U1476 ( .A0(intDX_EWSW[30]), .A1(n1725), .B0(intDX_EWSW[29]),
.B1(n1679), .C0(n984), .Y(n986) );
AOI221X1TS U1477 ( .A0(n1725), .A1(intDX_EWSW[30]), .B0(intDX_EWSW[17]),
.B1(n1711), .C0(n1089), .Y(n1096) );
NOR2X1TS U1478 ( .A(n1725), .B(intDX_EWSW[30]), .Y(n985) );
AOI221X1TS U1479 ( .A0(n1716), .A1(intDX_EWSW[2]), .B0(intDX_EWSW[3]), .B1(
n1710), .C0(n1106), .Y(n1111) );
AOI221X1TS U1480 ( .A0(n1678), .A1(intDX_EWSW[22]), .B0(intDX_EWSW[23]),
.B1(n1724), .C0(n1092), .Y(n1093) );
AOI221X1TS U1481 ( .A0(n1719), .A1(intDX_EWSW[14]), .B0(intDX_EWSW[15]),
.B1(n1677), .C0(n1100), .Y(n1101) );
AOI221X1TS U1482 ( .A0(n1721), .A1(intDX_EWSW[20]), .B0(intDX_EWSW[21]),
.B1(n1714), .C0(n1091), .Y(n1094) );
AOI221X1TS U1483 ( .A0(n1718), .A1(intDX_EWSW[12]), .B0(intDX_EWSW[13]),
.B1(n1713), .C0(n1099), .Y(n1102) );
INVX2TS U1484 ( .A(n1634), .Y(n912) );
OAI21XLTS U1485 ( .A0(n1184), .A1(n1636), .B0(n1144), .Y(n471) );
OAI21XLTS U1486 ( .A0(n1184), .A1(n1637), .B0(n1183), .Y(n470) );
OAI21XLTS U1487 ( .A0(n1184), .A1(n1641), .B0(n1171), .Y(n468) );
OAI21XLTS U1488 ( .A0(n1184), .A1(n1647), .B0(n1178), .Y(n467) );
OAI21XLTS U1489 ( .A0(n1166), .A1(n1184), .B0(n1165), .Y(n466) );
OAI21XLTS U1490 ( .A0(n1162), .A1(n1184), .B0(n1161), .Y(n464) );
XOR2X1TS U1491 ( .A(n1222), .B(DmP_mant_SFG_SWR[13]), .Y(n1622) );
OAI31XLTS U1492 ( .A0(n1246), .A1(n1245), .A2(n1533), .B0(n1244), .Y(n720)
);
NOR2X2TS U1493 ( .A(n914), .B(DMP_EXP_EWSW[23]), .Y(n1506) );
AOI21X2TS U1494 ( .A0(Shift_amount_SHT1_EWR[1]), .A1(n876), .B0(n1454), .Y(
n1198) );
XNOR2X2TS U1495 ( .A(DMP_exp_NRM2_EW[0]), .B(n874), .Y(n1131) );
BUFX3TS U1496 ( .A(n1069), .Y(n1072) );
NOR2X2TS U1497 ( .A(n1562), .B(DMP_SFG[3]), .Y(n1568) );
NOR2X2TS U1498 ( .A(n1423), .B(DMP_SFG[5]), .Y(n1586) );
NOR2X2TS U1499 ( .A(n1430), .B(DMP_SFG[7]), .Y(n1596) );
AOI222X1TS U1500 ( .A0(Raw_mant_NRM_SWR[10]), .A1(n903), .B0(
DmP_mant_SHT1_SW[14]), .B1(n1349), .C0(n909), .C1(DmP_mant_SHT1_SW[13]), .Y(n1338) );
OAI21X2TS U1501 ( .A0(n1561), .A1(n1735), .B0(n1422), .Y(n1575) );
NAND2X1TS U1502 ( .A(n1216), .B(DMP_SFG[15]), .Y(n1406) );
NAND2X1TS U1503 ( .A(n1217), .B(DMP_SFG[16]), .Y(n1399) );
NOR2X2TS U1504 ( .A(n1554), .B(DMP_SFG[2]), .Y(n1569) );
OAI21XLTS U1505 ( .A0(n1241), .A1(intDX_EWSW[31]), .B0(n1532), .Y(n1117) );
NOR2X2TS U1506 ( .A(n1219), .B(DMP_SFG[17]), .Y(n1379) );
NAND2X1TS U1507 ( .A(n1219), .B(DMP_SFG[17]), .Y(n1380) );
NOR2X1TS U1508 ( .A(Raw_mant_NRM_SWR[4]), .B(Raw_mant_NRM_SWR[5]), .Y(n1152)
);
AOI221X1TS U1509 ( .A0(n1727), .A1(intDX_EWSW[18]), .B0(intDX_EWSW[19]),
.B1(n1680), .C0(n1090), .Y(n1095) );
AOI32X1TS U1510 ( .A0(n1727), .A1(n962), .A2(intDX_EWSW[18]), .B0(
intDX_EWSW[19]), .B1(n1680), .Y(n963) );
NOR2X1TS U1511 ( .A(n1679), .B(intDX_EWSW[29]), .Y(n983) );
NAND2X1TS U1512 ( .A(shift_value_SHT2_EWR[2]), .B(n1689), .Y(n1000) );
OAI2BB2XLTS U1513 ( .B0(intDY_EWSW[0]), .B1(n942), .A0N(intDX_EWSW[1]),
.A1N(n1800), .Y(n944) );
NOR2XLTS U1514 ( .A(n1697), .B(intDX_EWSW[11]), .Y(n922) );
NOR2X1TS U1515 ( .A(n1711), .B(intDX_EWSW[17]), .Y(n960) );
NOR2X4TS U1516 ( .A(shift_value_SHT2_EWR[4]), .B(n1652), .Y(n1642) );
OAI21XLTS U1517 ( .A0(intDX_EWSW[13]), .A1(n1713), .B0(intDX_EWSW[12]), .Y(
n921) );
OA22X1TS U1518 ( .A0(n1678), .A1(intDX_EWSW[22]), .B0(n1724), .B1(
intDX_EWSW[23]), .Y(n970) );
OA22X1TS U1519 ( .A0(n1719), .A1(intDX_EWSW[14]), .B0(n1677), .B1(
intDX_EWSW[15]), .Y(n933) );
CLKBUFX2TS U1520 ( .A(n1309), .Y(n1349) );
INVX2TS U1521 ( .A(OP_FLAG_SFG), .Y(n1426) );
NOR2X2TS U1522 ( .A(n1008), .B(n1455), .Y(n917) );
OR2X2TS U1523 ( .A(n1217), .B(DMP_SFG[16]), .Y(n918) );
OAI21XLTS U1524 ( .A0(intDX_EWSW[1]), .A1(n1800), .B0(intDX_EWSW[0]), .Y(
n942) );
NOR2X2TS U1525 ( .A(n1216), .B(DMP_SFG[15]), .Y(n1405) );
NAND2X1TS U1526 ( .A(n1698), .B(LZD_output_NRM2_EW[0]), .Y(
DP_OP_15J43_123_3594_n8) );
INVX2TS U1527 ( .A(n1375), .Y(n1378) );
OAI21XLTS U1528 ( .A0(DmP_EXP_EWSW[25]), .A1(n913), .B0(n1508), .Y(n1509) );
INVX2TS U1529 ( .A(n1500), .Y(n1329) );
NAND2X1TS U1530 ( .A(n1292), .B(n1488), .Y(n1050) );
NOR2XLTS U1531 ( .A(n917), .B(SIGN_FLAG_SHT1SHT2), .Y(n1357) );
INVX2TS U1532 ( .A(n1480), .Y(n1478) );
XOR2X1TS U1533 ( .A(n1383), .B(n1382), .Y(n1384) );
BUFX3TS U1534 ( .A(n1470), .Y(n1473) );
BUFX3TS U1535 ( .A(n1470), .Y(n1480) );
OAI2BB2XLTS U1536 ( .B0(n1663), .B1(n1646), .A0N(final_result_ieee[6]),
.A1N(n1137), .Y(n503) );
OAI21XLTS U1537 ( .A0(n1676), .A1(n1211), .B0(n1186), .Y(n610) );
OAI211XLTS U1538 ( .A0(n1322), .A1(n908), .B0(n1308), .C0(n1307), .Y(n776)
);
OAI2BB2XLTS U1539 ( .B0(intDY_EWSW[12]), .B1(n921), .A0N(intDX_EWSW[13]),
.A1N(n1713), .Y(n932) );
AOI22X1TS U1540 ( .A0(intDX_EWSW[11]), .A1(n1697), .B0(intDX_EWSW[10]), .B1(
n923), .Y(n928) );
AOI21X1TS U1541 ( .A0(n926), .A1(n925), .B0(n935), .Y(n927) );
OAI22X1TS U1542 ( .A0(n1688), .A1(intDX_EWSW[10]), .B0(n1697), .B1(
intDX_EWSW[11]), .Y(n1098) );
INVX2TS U1543 ( .A(n1098), .Y(n936) );
OAI2BB2XLTS U1544 ( .B0(intDY_EWSW[14]), .B1(n929), .A0N(intDX_EWSW[15]),
.A1N(n1677), .Y(n930) );
AOI211X1TS U1545 ( .A0(n933), .A1(n932), .B0(n931), .C0(n930), .Y(n934) );
OAI2BB1X1TS U1546 ( .A0N(n1685), .A1N(intDY_EWSW[5]), .B0(intDX_EWSW[4]),
.Y(n940) );
OAI22X1TS U1547 ( .A0(intDY_EWSW[4]), .A1(n940), .B0(n1685), .B1(
intDY_EWSW[5]), .Y(n951) );
OAI2BB1X1TS U1548 ( .A0N(n1672), .A1N(intDY_EWSW[7]), .B0(intDX_EWSW[6]),
.Y(n941) );
OAI22X1TS U1549 ( .A0(intDY_EWSW[6]), .A1(n941), .B0(n1672), .B1(
intDY_EWSW[7]), .Y(n950) );
AOI22X1TS U1550 ( .A0(intDY_EWSW[7]), .A1(n1672), .B0(intDY_EWSW[6]), .B1(
n1693), .Y(n948) );
OAI21X2TS U1551 ( .A0(intDX_EWSW[18]), .A1(n1727), .B0(n962), .Y(n1090) );
AOI211X1TS U1552 ( .A0(intDY_EWSW[16]), .A1(n1692), .B0(n965), .C0(n1090),
.Y(n955) );
OAI2BB2XLTS U1553 ( .B0(intDY_EWSW[20]), .B1(n959), .A0N(intDX_EWSW[21]),
.A1N(n1714), .Y(n969) );
AOI22X1TS U1554 ( .A0(intDX_EWSW[17]), .A1(n1711), .B0(intDX_EWSW[16]), .B1(
n961), .Y(n964) );
OAI32X1TS U1555 ( .A0(n1090), .A1(n965), .A2(n964), .B0(n963), .B1(n965),
.Y(n968) );
OAI2BB2XLTS U1556 ( .B0(intDY_EWSW[22]), .B1(n966), .A0N(intDX_EWSW[23]),
.A1N(n1724), .Y(n967) );
AOI211X1TS U1557 ( .A0(n970), .A1(n969), .B0(n968), .C0(n967), .Y(n971) );
OAI21X2TS U1558 ( .A0(intDX_EWSW[26]), .A1(n1722), .B0(n979), .Y(n1083) );
NOR2X1TS U1559 ( .A(n1709), .B(intDX_EWSW[25]), .Y(n977) );
NAND4BBX1TS U1560 ( .AN(n1083), .BN(n977), .C(n987), .D(n973), .Y(n974) );
AOI22X1TS U1561 ( .A0(intDX_EWSW[25]), .A1(n1709), .B0(intDX_EWSW[24]), .B1(
n978), .Y(n982) );
OAI211X1TS U1562 ( .A0(n982), .A1(n1083), .B0(n981), .C0(n980), .Y(n988) );
NOR3X1TS U1563 ( .A(n1694), .B(n983), .C(intDY_EWSW[28]), .Y(n984) );
INVX2TS U1564 ( .A(n1532), .Y(n1187) );
BUFX3TS U1565 ( .A(n1187), .Y(n1514) );
NOR2X4TS U1566 ( .A(n991), .B(n1514), .Y(n1189) );
AOI22X1TS U1567 ( .A0(intDX_EWSW[13]), .A1(n1259), .B0(DMP_EXP_EWSW[13]),
.B1(n915), .Y(n992) );
AOI22X1TS U1568 ( .A0(intDX_EWSW[15]), .A1(n1259), .B0(DMP_EXP_EWSW[15]),
.B1(n915), .Y(n993) );
INVX2TS U1569 ( .A(n1255), .Y(n1253) );
AOI22X1TS U1570 ( .A0(intDX_EWSW[3]), .A1(n1273), .B0(DMP_EXP_EWSW[3]), .B1(
n1514), .Y(n994) );
NOR2X2TS U1571 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n1704), .Y(n1460) );
AOI22X1TS U1572 ( .A0(Data_array_SWR[12]), .A1(n889), .B0(Data_array_SWR[16]), .B1(n890), .Y(n999) );
NOR2X4TS U1573 ( .A(shift_value_SHT2_EWR[2]), .B(shift_value_SHT2_EWR[3]),
.Y(n1169) );
AOI22X1TS U1574 ( .A0(Data_array_SWR[24]), .A1(n1019), .B0(
Data_array_SWR[20]), .B1(n887), .Y(n998) );
NAND2X1TS U1575 ( .A(n999), .B(n998), .Y(n1139) );
INVX2TS U1576 ( .A(n1000), .Y(n1170) );
NOR2X1TS U1577 ( .A(shift_value_SHT2_EWR[2]), .B(n1689), .Y(n1016) );
INVX2TS U1578 ( .A(n1141), .Y(n1001) );
INVX2TS U1579 ( .A(DP_OP_15J43_123_3594_n4), .Y(n1002) );
XNOR2X2TS U1580 ( .A(DMP_exp_NRM2_EW[6]), .B(n1006), .Y(n1126) );
INVX2TS U1581 ( .A(exp_rslt_NRM2_EW1[3]), .Y(n1135) );
INVX2TS U1582 ( .A(exp_rslt_NRM2_EW1[2]), .Y(n1125) );
XNOR2X2TS U1583 ( .A(DMP_exp_NRM2_EW[5]), .B(DP_OP_15J43_123_3594_n4), .Y(
n1121) );
INVX2TS U1584 ( .A(n1006), .Y(n1007) );
XNOR2X2TS U1585 ( .A(DMP_exp_NRM2_EW[7]), .B(n1011), .Y(n1455) );
AND4X1TS U1586 ( .A(exp_rslt_NRM2_EW1[3]), .B(exp_rslt_NRM2_EW1[2]), .C(
n1131), .D(exp_rslt_NRM2_EW1[1]), .Y(n1009) );
INVX2TS U1587 ( .A(n1011), .Y(n1012) );
OAI2BB1X2TS U1588 ( .A0N(n916), .A1N(n1013), .B0(Shift_reg_FLAGS_7[0]), .Y(
n1457) );
INVX2TS U1589 ( .A(Shift_reg_FLAGS_7[0]), .Y(n1645) );
BUFX3TS U1590 ( .A(n1645), .Y(n1137) );
AOI22X1TS U1591 ( .A0(Data_array_SWR[17]), .A1(n890), .B0(Data_array_SWR[13]), .B1(n996), .Y(n1015) );
AOI22X1TS U1592 ( .A0(Data_array_SWR[21]), .A1(n887), .B0(Data_array_SWR[25]), .B1(n1019), .Y(n1014) );
NAND2X1TS U1593 ( .A(n1015), .B(n1014), .Y(n1119) );
INVX2TS U1594 ( .A(n1148), .Y(n1118) );
OAI2BB2XLTS U1595 ( .B0(n1666), .B1(n1646), .A0N(final_result_ieee[7]),
.A1N(n1137), .Y(n505) );
AOI22X1TS U1596 ( .A0(Data_array_SWR[14]), .A1(n890), .B0(Data_array_SWR[10]), .B1(n996), .Y(n1018) );
AOI22X1TS U1597 ( .A0(Data_array_SWR[22]), .A1(n1019), .B0(
Data_array_SWR[18]), .B1(n888), .Y(n1017) );
NAND2X1TS U1598 ( .A(n1018), .B(n1017), .Y(n1173) );
AOI22X1TS U1599 ( .A0(Data_array_SWR[23]), .A1(n1170), .B0(
Data_array_SWR[19]), .B1(n1169), .Y(n1061) );
INVX2TS U1600 ( .A(n1061), .Y(n1172) );
OAI2BB2XLTS U1601 ( .B0(n1659), .B1(n1646), .A0N(final_result_ieee[4]),
.A1N(n1738), .Y(n499) );
AOI22X1TS U1602 ( .A0(Data_array_SWR[15]), .A1(n891), .B0(Data_array_SWR[11]), .B1(n889), .Y(n1021) );
AOI22X1TS U1603 ( .A0(Data_array_SWR[23]), .A1(n1019), .B0(
Data_array_SWR[19]), .B1(n888), .Y(n1020) );
NAND2X1TS U1604 ( .A(n1021), .B(n1020), .Y(n1181) );
AOI22X1TS U1605 ( .A0(Data_array_SWR[22]), .A1(n1170), .B0(
Data_array_SWR[18]), .B1(n1169), .Y(n1064) );
INVX2TS U1606 ( .A(n1064), .Y(n1180) );
OAI2BB2XLTS U1607 ( .B0(n1660), .B1(n1646), .A0N(final_result_ieee[5]),
.A1N(n1645), .Y(n501) );
NOR2X2TS U1608 ( .A(Raw_mant_NRM_SWR[23]), .B(Raw_mant_NRM_SWR[22]), .Y(
n1027) );
INVX2TS U1609 ( .A(n1027), .Y(n1022) );
OR2X2TS U1610 ( .A(Raw_mant_NRM_SWR[25]), .B(Raw_mant_NRM_SWR[24]), .Y(n1026) );
NOR3X2TS U1611 ( .A(Raw_mant_NRM_SWR[21]), .B(Raw_mant_NRM_SWR[19]), .C(
Raw_mant_NRM_SWR[20]), .Y(n1451) );
NAND2X4TS U1612 ( .A(n1445), .B(n1451), .Y(n1032) );
NOR2X4TS U1613 ( .A(Raw_mant_NRM_SWR[18]), .B(n1032), .Y(n1437) );
AOI21X1TS U1614 ( .A0(Raw_mant_NRM_SWR[15]), .A1(n1023), .B0(
Raw_mant_NRM_SWR[19]), .Y(n1025) );
AOI21X1TS U1615 ( .A0(n1028), .A1(n1027), .B0(n1026), .Y(n1035) );
NOR2X1TS U1616 ( .A(Raw_mant_NRM_SWR[3]), .B(Raw_mant_NRM_SWR[2]), .Y(n1155)
);
OR2X4TS U1617 ( .A(n1029), .B(Raw_mant_NRM_SWR[14]), .Y(n1439) );
NOR2X6TS U1618 ( .A(Raw_mant_NRM_SWR[13]), .B(n1439), .Y(n1037) );
NAND2X4TS U1619 ( .A(n1444), .B(n1686), .Y(n1153) );
NAND2X4TS U1620 ( .A(n1446), .B(n1152), .Y(n1156) );
OAI21X1TS U1621 ( .A0(Raw_mant_NRM_SWR[6]), .A1(Raw_mant_NRM_SWR[7]), .B0(
n1030), .Y(n1031) );
OAI21X4TS U1622 ( .A0(n1155), .A1(n1156), .B0(n1031), .Y(n1158) );
INVX2TS U1623 ( .A(n1037), .Y(n1033) );
INVX2TS U1624 ( .A(n1032), .Y(n1045) );
AOI22X1TS U1625 ( .A0(Raw_mant_NRM_SWR[18]), .A1(n1045), .B0(n1444), .B1(
Raw_mant_NRM_SWR[10]), .Y(n1039) );
OAI31X1TS U1626 ( .A0(Raw_mant_NRM_SWR[12]), .A1(n1668), .A2(n1033), .B0(
n1039), .Y(n1034) );
INVX2TS U1627 ( .A(n1151), .Y(n1049) );
OAI32X1TS U1628 ( .A0(Raw_mant_NRM_SWR[3]), .A1(Raw_mant_NRM_SWR[1]), .A2(
n1673), .B0(n1687), .B1(Raw_mant_NRM_SWR[3]), .Y(n1036) );
OAI211X1TS U1629 ( .A0(Raw_mant_NRM_SWR[4]), .A1(n1036), .B0(n1446), .C0(
n1690), .Y(n1038) );
NAND3X2TS U1630 ( .A(n1039), .B(n1038), .C(n1441), .Y(n1453) );
AOI21X1TS U1631 ( .A0(n1708), .A1(Raw_mant_NRM_SWR[20]), .B0(
Raw_mant_NRM_SWR[22]), .Y(n1040) );
INVX2TS U1632 ( .A(n1041), .Y(n1042) );
OAI31X1TS U1633 ( .A0(Raw_mant_NRM_SWR[9]), .A1(n1047), .A2(n1695), .B0(
n1046), .Y(n1048) );
INVX2TS U1634 ( .A(n1801), .Y(n1523) );
NAND2X4TS U1635 ( .A(n899), .B(n1523), .Y(n1500) );
AOI22X1TS U1636 ( .A0(n1352), .A1(Raw_mant_NRM_SWR[24]), .B0(n1329), .B1(
Data_array_SWR[0]), .Y(n1056) );
CLKBUFX2TS U1637 ( .A(n1329), .Y(n1238) );
BUFX3TS U1638 ( .A(n1238), .Y(n1355) );
NOR2X4TS U1639 ( .A(n1355), .B(n1198), .Y(n1312) );
NOR2BX1TS U1640 ( .AN(Shift_amount_SHT1_EWR[0]), .B(Shift_reg_FLAGS_7[1]),
.Y(n1487) );
BUFX3TS U1641 ( .A(n1487), .Y(n1309) );
BUFX3TS U1642 ( .A(n1349), .Y(n1335) );
AOI22X1TS U1643 ( .A0(Raw_mant_NRM_SWR[22]), .A1(n884), .B0(n1335), .B1(
DmP_mant_SHT1_SW[1]), .Y(n1054) );
AOI22X1TS U1644 ( .A0(Raw_mant_NRM_SWR[23]), .A1(n903), .B0(n909), .B1(
DmP_mant_SHT1_SW[0]), .Y(n1053) );
NAND2X1TS U1645 ( .A(n1054), .B(n1053), .Y(n1315) );
AOI22X1TS U1646 ( .A0(n1312), .A1(n1315), .B0(Raw_mant_NRM_SWR[25]), .B1(
n905), .Y(n1055) );
NAND2X1TS U1647 ( .A(n1056), .B(n1055), .Y(n771) );
OAI21XLTS U1648 ( .A0(n1801), .A1(n896), .B0(n899), .Y(n829) );
AOI22X1TS U1649 ( .A0(Data_array_SWR[13]), .A1(n888), .B0(Data_array_SWR[9]),
.B1(n890), .Y(n1058) );
INVX2TS U1650 ( .A(n1065), .Y(n1145) );
AOI22X1TS U1651 ( .A0(Data_array_SWR[5]), .A1(n889), .B0(Data_array_SWR[1]),
.B1(n1145), .Y(n1057) );
OAI211X1TS U1652 ( .A0(n1141), .A1(n875), .B0(n1058), .C0(n1057), .Y(n1651)
);
AOI22X1TS U1653 ( .A0(Data_array_SWR[24]), .A1(n893), .B0(n1371), .B1(n1651),
.Y(n1162) );
OAI2BB2XLTS U1654 ( .B0(n1162), .B1(n1646), .A0N(final_result_ieee[22]),
.A1N(n1137), .Y(n489) );
AOI22X1TS U1655 ( .A0(Data_array_SWR[15]), .A1(n887), .B0(Data_array_SWR[11]), .B1(n890), .Y(n1060) );
AOI22X1TS U1656 ( .A0(Data_array_SWR[7]), .A1(n889), .B0(Data_array_SWR[3]),
.B1(n1145), .Y(n1059) );
OAI211X1TS U1657 ( .A0(n1061), .A1(n875), .B0(n1060), .C0(n1059), .Y(n1067)
);
AOI22X1TS U1658 ( .A0(Data_array_SWR[22]), .A1(n892), .B0(n1371), .B1(n1067),
.Y(n1166) );
BUFX3TS U1659 ( .A(n1645), .Y(n1632) );
OAI2BB2XLTS U1660 ( .B0(n1166), .B1(n1646), .A0N(final_result_ieee[20]),
.A1N(n1632), .Y(n491) );
AOI22X1TS U1661 ( .A0(Data_array_SWR[14]), .A1(n887), .B0(Data_array_SWR[10]), .B1(n890), .Y(n1063) );
AOI22X1TS U1662 ( .A0(Data_array_SWR[6]), .A1(n889), .B0(Data_array_SWR[2]),
.B1(n1145), .Y(n1062) );
OAI211X1TS U1663 ( .A0(n1064), .A1(n875), .B0(n1063), .C0(n1062), .Y(n1066)
);
AOI22X1TS U1664 ( .A0(Data_array_SWR[23]), .A1(n892), .B0(n1371), .B1(n1066),
.Y(n1164) );
OAI2BB2XLTS U1665 ( .B0(n1164), .B1(n1646), .A0N(final_result_ieee[21]),
.A1N(n1632), .Y(n490) );
AOI22X1TS U1666 ( .A0(Data_array_SWR[23]), .A1(n895), .B0(n1652), .B1(n1066),
.Y(n1654) );
OAI2BB2XLTS U1667 ( .B0(n1654), .B1(n1646), .A0N(final_result_ieee[0]),
.A1N(n1632), .Y(n492) );
AOI22X1TS U1668 ( .A0(Data_array_SWR[22]), .A1(n895), .B0(n1652), .B1(n1067),
.Y(n1655) );
OAI2BB2XLTS U1669 ( .B0(n1655), .B1(n1646), .A0N(final_result_ieee[1]),
.A1N(n1632), .Y(n493) );
BUFX3TS U1670 ( .A(n1771), .Y(n1776) );
BUFX3TS U1671 ( .A(n1072), .Y(n1777) );
BUFX3TS U1672 ( .A(n1769), .Y(n1778) );
BUFX3TS U1673 ( .A(n1770), .Y(n1779) );
BUFX3TS U1674 ( .A(n1773), .Y(n1780) );
BUFX3TS U1675 ( .A(n1072), .Y(n1782) );
BUFX3TS U1676 ( .A(n1769), .Y(n1783) );
BUFX3TS U1677 ( .A(n1770), .Y(n1784) );
BUFX3TS U1678 ( .A(n1773), .Y(n1785) );
BUFX3TS U1679 ( .A(n1774), .Y(n1766) );
CLKBUFX2TS U1680 ( .A(n1069), .Y(n1071) );
BUFX3TS U1681 ( .A(n1769), .Y(n1768) );
BUFX3TS U1682 ( .A(n1069), .Y(n1769) );
BUFX3TS U1683 ( .A(n1069), .Y(n1770) );
BUFX3TS U1684 ( .A(n1069), .Y(n1771) );
BUFX3TS U1685 ( .A(n1770), .Y(n1772) );
BUFX3TS U1686 ( .A(n1069), .Y(n1773) );
BUFX3TS U1687 ( .A(n1069), .Y(n1774) );
BUFX3TS U1688 ( .A(n1771), .Y(n1775) );
BUFX3TS U1689 ( .A(n1774), .Y(n1781) );
BUFX3TS U1690 ( .A(n1773), .Y(n1767) );
BUFX3TS U1691 ( .A(n1070), .Y(n1760) );
BUFX3TS U1692 ( .A(n1774), .Y(n1796) );
BUFX3TS U1693 ( .A(n1771), .Y(n1761) );
BUFX3TS U1694 ( .A(n1072), .Y(n1759) );
BUFX3TS U1695 ( .A(n1771), .Y(n1786) );
BUFX3TS U1696 ( .A(n1072), .Y(n1797) );
BUFX3TS U1697 ( .A(n1770), .Y(n1787) );
BUFX3TS U1698 ( .A(n1072), .Y(n1765) );
BUFX3TS U1699 ( .A(n1773), .Y(n1790) );
BUFX3TS U1700 ( .A(n1774), .Y(n1789) );
BUFX3TS U1701 ( .A(n1769), .Y(n1762) );
BUFX3TS U1702 ( .A(n1771), .Y(n1791) );
BUFX3TS U1703 ( .A(n1068), .Y(n1794) );
BUFX3TS U1704 ( .A(n1068), .Y(n1788) );
BUFX3TS U1705 ( .A(n1770), .Y(n1758) );
BUFX3TS U1706 ( .A(n1773), .Y(n1764) );
BUFX3TS U1707 ( .A(n1070), .Y(n1792) );
BUFX3TS U1708 ( .A(n1070), .Y(n1793) );
BUFX3TS U1709 ( .A(n1071), .Y(n1798) );
BUFX3TS U1710 ( .A(n1774), .Y(n1763) );
BUFX3TS U1711 ( .A(n1769), .Y(n1795) );
MXI2X1TS U1712 ( .A(DmP_mant_SFG_SWR[0]), .B(n920), .S0(n1550), .Y(n1073) );
CLKBUFX2TS U1713 ( .A(Shift_reg_FLAGS_7[2]), .Y(n1609) );
MXI2X1TS U1714 ( .A(n1673), .B(n1073), .S0(n1609), .Y(n542) );
MXI2X1TS U1715 ( .A(DmP_mant_SFG_SWR[1]), .B(n919), .S0(n1550), .Y(n1074) );
MXI2X1TS U1716 ( .A(n1748), .B(n1074), .S0(n1609), .Y(n541) );
CLKBUFX2TS U1717 ( .A(n1752), .Y(n1537) );
INVX2TS U1718 ( .A(n1537), .Y(n1516) );
NAND2X1TS U1719 ( .A(DmP_EXP_EWSW[25]), .B(n913), .Y(n1508) );
NOR2X1TS U1720 ( .A(n880), .B(DMP_EXP_EWSW[24]), .Y(n1504) );
OAI22X1TS U1721 ( .A0(n1506), .A1(n1504), .B0(DmP_EXP_EWSW[24]), .B1(n1681),
.Y(n1510) );
AOI22X1TS U1722 ( .A0(DMP_EXP_EWSW[25]), .A1(n1746), .B0(n1508), .B1(n1510),
.Y(n1077) );
NOR2X1TS U1723 ( .A(n881), .B(DMP_EXP_EWSW[26]), .Y(n1078) );
AOI21X1TS U1724 ( .A0(DMP_EXP_EWSW[26]), .A1(n881), .B0(n1078), .Y(n1075) );
XNOR2X1TS U1725 ( .A(n1077), .B(n1075), .Y(n1076) );
OAI22X1TS U1726 ( .A0(n1078), .A1(n1077), .B0(DmP_EXP_EWSW[26]), .B1(n1683),
.Y(n1080) );
XNOR2X1TS U1727 ( .A(DmP_EXP_EWSW[27]), .B(DMP_EXP_EWSW[27]), .Y(n1079) );
XOR2X1TS U1728 ( .A(n1080), .B(n1079), .Y(n1081) );
OAI22X1TS U1729 ( .A0(n1800), .A1(intDX_EWSW[1]), .B0(n1709), .B1(
intDX_EWSW[25]), .Y(n1082) );
AOI221X1TS U1730 ( .A0(n1800), .A1(intDX_EWSW[1]), .B0(intDX_EWSW[25]), .B1(
n1709), .C0(n1082), .Y(n1088) );
AOI221X1TS U1731 ( .A0(n1722), .A1(intDX_EWSW[26]), .B0(intDX_EWSW[27]),
.B1(n1726), .C0(n1083), .Y(n1087) );
OAI22X1TS U1732 ( .A0(n1723), .A1(intDX_EWSW[28]), .B0(n1679), .B1(
intDX_EWSW[29]), .Y(n1084) );
AOI221X1TS U1733 ( .A0(n1723), .A1(intDX_EWSW[28]), .B0(intDX_EWSW[29]),
.B1(n1679), .C0(n1084), .Y(n1086) );
AOI2BB2XLTS U1734 ( .B0(intDX_EWSW[7]), .B1(n1703), .A0N(n1703), .A1N(
intDX_EWSW[7]), .Y(n1085) );
OAI22X1TS U1735 ( .A0(n1725), .A1(intDX_EWSW[30]), .B0(n1711), .B1(
intDX_EWSW[17]), .Y(n1089) );
OAI22X1TS U1736 ( .A0(n1721), .A1(intDX_EWSW[20]), .B0(n1714), .B1(
intDX_EWSW[21]), .Y(n1091) );
OAI22X1TS U1737 ( .A0(n1678), .A1(intDX_EWSW[22]), .B0(n1724), .B1(
intDX_EWSW[23]), .Y(n1092) );
OAI22X1TS U1738 ( .A0(n1669), .A1(intDX_EWSW[24]), .B0(n1712), .B1(
intDX_EWSW[9]), .Y(n1097) );
AOI221X1TS U1739 ( .A0(n1669), .A1(intDX_EWSW[24]), .B0(intDX_EWSW[9]), .B1(
n1712), .C0(n1097), .Y(n1104) );
OAI22X1TS U1740 ( .A0(n1718), .A1(intDX_EWSW[12]), .B0(n1713), .B1(
intDX_EWSW[13]), .Y(n1099) );
OAI22X1TS U1741 ( .A0(n1719), .A1(intDX_EWSW[14]), .B0(n1677), .B1(
intDX_EWSW[15]), .Y(n1100) );
OAI22X1TS U1742 ( .A0(n1720), .A1(intDX_EWSW[16]), .B0(n1676), .B1(
intDX_EWSW[0]), .Y(n1105) );
AOI221X1TS U1743 ( .A0(n1720), .A1(intDX_EWSW[16]), .B0(intDX_EWSW[0]), .B1(
n1676), .C0(n1105), .Y(n1112) );
OAI22X1TS U1744 ( .A0(n1716), .A1(intDX_EWSW[2]), .B0(n1710), .B1(
intDX_EWSW[3]), .Y(n1106) );
OAI22X1TS U1745 ( .A0(n1717), .A1(intDX_EWSW[4]), .B0(n1675), .B1(
intDX_EWSW[5]), .Y(n1107) );
AOI221X1TS U1746 ( .A0(n1717), .A1(intDX_EWSW[4]), .B0(intDX_EWSW[5]), .B1(
n1675), .C0(n1107), .Y(n1110) );
OAI22X1TS U1747 ( .A0(n1715), .A1(intDX_EWSW[8]), .B0(n1702), .B1(
intDX_EWSW[6]), .Y(n1108) );
AOI221X1TS U1748 ( .A0(n1715), .A1(intDX_EWSW[8]), .B0(intDX_EWSW[6]), .B1(
n1702), .C0(n1108), .Y(n1109) );
NOR4X1TS U1749 ( .A(n1116), .B(n1115), .C(n1114), .D(n1113), .Y(n1246) );
CLKXOR2X2TS U1750 ( .A(intDY_EWSW[31]), .B(intAS), .Y(n1241) );
AOI21X1TS U1751 ( .A0(n1241), .A1(intDX_EWSW[31]), .B0(n1117), .Y(n1513) );
NOR2X4TS U1752 ( .A(n882), .B(Shift_reg_FLAGS_7[0]), .Y(n1648) );
NAND2X1TS U1753 ( .A(n1182), .B(DmP_mant_SFG_SWR[16]), .Y(n1120) );
NAND2X2TS U1754 ( .A(n917), .B(Shift_reg_FLAGS_7[0]), .Y(n1534) );
BUFX3TS U1755 ( .A(n1645), .Y(n1463) );
NAND2X1TS U1756 ( .A(n1463), .B(final_result_ieee[28]), .Y(n1122) );
NAND2X1TS U1757 ( .A(n1463), .B(final_result_ieee[25]), .Y(n1124) );
NAND2X1TS U1758 ( .A(n1463), .B(final_result_ieee[29]), .Y(n1127) );
INVX2TS U1759 ( .A(exp_rslt_NRM2_EW1[4]), .Y(n1130) );
NAND2X1TS U1760 ( .A(n1463), .B(final_result_ieee[27]), .Y(n1129) );
INVX2TS U1761 ( .A(n1131), .Y(n1133) );
NAND2X1TS U1762 ( .A(n1463), .B(final_result_ieee[23]), .Y(n1132) );
NAND2X1TS U1763 ( .A(n1463), .B(final_result_ieee[26]), .Y(n1134) );
INVX2TS U1764 ( .A(exp_rslt_NRM2_EW1[1]), .Y(n1138) );
NAND2X1TS U1765 ( .A(n1463), .B(final_result_ieee[24]), .Y(n1136) );
INVX2TS U1766 ( .A(n1139), .Y(n1142) );
INVX2TS U1767 ( .A(n1179), .Y(n1140) );
OAI222X1TS U1768 ( .A0(n1142), .A1(n1756), .B0(n1757), .B1(n873), .C0(n1141),
.C1(n1140), .Y(n1143) );
INVX2TS U1769 ( .A(n1143), .Y(n1636) );
NAND2X1TS U1770 ( .A(n1182), .B(DmP_mant_SFG_SWR[17]), .Y(n1144) );
AOI22X1TS U1771 ( .A0(Data_array_SWR[12]), .A1(n888), .B0(Data_array_SWR[8]),
.B1(n891), .Y(n1147) );
AOI22X1TS U1772 ( .A0(Data_array_SWR[4]), .A1(n996), .B0(Data_array_SWR[0]),
.B1(n1145), .Y(n1146) );
OAI211X1TS U1773 ( .A0(n1148), .A1(n875), .B0(n1147), .C0(n1146), .Y(n1649)
);
AOI22X1TS U1774 ( .A0(Data_array_SWR[25]), .A1(n893), .B0(n1371), .B1(n1649),
.Y(n1150) );
NAND2X1TS U1775 ( .A(n1182), .B(DmP_mant_SFG_SWR[25]), .Y(n1149) );
OAI22X1TS U1776 ( .A0(n1154), .A1(n1153), .B0(n1152), .B1(n1151), .Y(n1159)
);
INVX2TS U1777 ( .A(n1156), .Y(n1447) );
OAI31X1TS U1778 ( .A0(n1159), .A1(n1158), .A2(n1157), .B0(
Shift_reg_FLAGS_7[1]), .Y(n1435) );
NAND2X1TS U1779 ( .A(n1182), .B(DmP_mant_SFG_SWR[24]), .Y(n1161) );
NAND2X1TS U1780 ( .A(n1182), .B(DmP_mant_SFG_SWR[23]), .Y(n1163) );
NAND2X1TS U1781 ( .A(n1182), .B(DmP_mant_SFG_SWR[22]), .Y(n1165) );
AOI22X1TS U1782 ( .A0(Data_array_SWR[13]), .A1(n890), .B0(Data_array_SWR[9]),
.B1(n889), .Y(n1168) );
NAND2X1TS U1783 ( .A(Data_array_SWR[17]), .B(n887), .Y(n1167) );
OAI211X1TS U1784 ( .A0(n1177), .A1(n875), .B0(n1168), .C0(n1167), .Y(n1640)
);
AO22X1TS U1785 ( .A0(Data_array_SWR[24]), .A1(n1170), .B0(Data_array_SWR[20]), .B1(n1169), .Y(n1639) );
NAND2X1TS U1786 ( .A(n1182), .B(DmP_mant_SFG_SWR[20]), .Y(n1171) );
NAND2X1TS U1787 ( .A(n1182), .B(DmP_mant_SFG_SWR[19]), .Y(n1174) );
AOI22X1TS U1788 ( .A0(Data_array_SWR[12]), .A1(n891), .B0(Data_array_SWR[8]),
.B1(n889), .Y(n1176) );
AOI22X1TS U1789 ( .A0(Data_array_SWR[16]), .A1(n887), .B0(
shift_value_SHT2_EWR[4]), .B1(n1639), .Y(n1175) );
NAND2X1TS U1790 ( .A(n1176), .B(n1175), .Y(n1644) );
INVX2TS U1791 ( .A(n1177), .Y(n1643) );
NAND2X1TS U1792 ( .A(n1182), .B(DmP_mant_SFG_SWR[21]), .Y(n1178) );
NAND2X1TS U1793 ( .A(n1182), .B(DmP_mant_SFG_SWR[18]), .Y(n1183) );
BUFX3TS U1794 ( .A(n1187), .Y(n1461) );
AOI22X1TS U1795 ( .A0(intDX_EWSW[17]), .A1(n1285), .B0(DmP_EXP_EWSW[17]),
.B1(n1461), .Y(n1185) );
BUFX3TS U1796 ( .A(n1514), .Y(n1256) );
AOI22X1TS U1797 ( .A0(intDX_EWSW[0]), .A1(n1285), .B0(DmP_EXP_EWSW[0]), .B1(
n1256), .Y(n1186) );
BUFX3TS U1798 ( .A(n1187), .Y(n1227) );
AOI22X1TS U1799 ( .A0(intDX_EWSW[16]), .A1(n1285), .B0(DmP_EXP_EWSW[16]),
.B1(n1227), .Y(n1188) );
AOI22X1TS U1800 ( .A0(intDX_EWSW[6]), .A1(n1189), .B0(DmP_EXP_EWSW[6]), .B1(
n1256), .Y(n1190) );
AOI22X1TS U1801 ( .A0(intDX_EWSW[4]), .A1(n1189), .B0(DmP_EXP_EWSW[4]), .B1(
n1256), .Y(n1191) );
AOI22X1TS U1802 ( .A0(intDX_EWSW[5]), .A1(n1189), .B0(DmP_EXP_EWSW[5]), .B1(
n1227), .Y(n1192) );
AOI22X1TS U1803 ( .A0(intDX_EWSW[2]), .A1(n1189), .B0(DmP_EXP_EWSW[2]), .B1(
n1256), .Y(n1193) );
AOI22X1TS U1804 ( .A0(intDX_EWSW[1]), .A1(n1189), .B0(DmP_EXP_EWSW[1]), .B1(
n1256), .Y(n1194) );
AOI22X1TS U1805 ( .A0(intDX_EWSW[3]), .A1(n1255), .B0(DmP_EXP_EWSW[3]), .B1(
n1256), .Y(n1195) );
AOI22X1TS U1806 ( .A0(DmP_EXP_EWSW[27]), .A1(n1461), .B0(intDX_EWSW[27]),
.B1(n1189), .Y(n1196) );
BUFX3TS U1807 ( .A(n1285), .Y(n1229) );
AOI22X1TS U1808 ( .A0(intDX_EWSW[7]), .A1(n1229), .B0(DmP_EXP_EWSW[7]), .B1(
n1227), .Y(n1197) );
AOI22X1TS U1809 ( .A0(n905), .A1(Raw_mant_NRM_SWR[24]), .B0(
DmP_mant_SHT1_SW[0]), .B1(n1349), .Y(n1203) );
AOI22X1TS U1810 ( .A0(Raw_mant_NRM_SWR[21]), .A1(n884), .B0(n1309), .B1(
DmP_mant_SHT1_SW[2]), .Y(n1200) );
AOI22X1TS U1811 ( .A0(Raw_mant_NRM_SWR[22]), .A1(n903), .B0(n909), .B1(
DmP_mant_SHT1_SW[1]), .Y(n1199) );
NAND2X1TS U1812 ( .A(n1200), .B(n1199), .Y(n1319) );
AOI22X1TS U1813 ( .A0(n1329), .A1(Data_array_SWR[1]), .B0(n1312), .B1(n1319),
.Y(n1202) );
NAND2X1TS U1814 ( .A(Raw_mant_NRM_SWR[23]), .B(n1352), .Y(n1201) );
AOI22X1TS U1815 ( .A0(intDX_EWSW[18]), .A1(n1229), .B0(DmP_EXP_EWSW[18]),
.B1(n1227), .Y(n1204) );
AOI22X1TS U1816 ( .A0(intDX_EWSW[10]), .A1(n1229), .B0(DmP_EXP_EWSW[10]),
.B1(n1256), .Y(n1205) );
AOI22X1TS U1817 ( .A0(intDX_EWSW[14]), .A1(n1229), .B0(DmP_EXP_EWSW[14]),
.B1(n1227), .Y(n1206) );
AOI22X1TS U1818 ( .A0(intDX_EWSW[11]), .A1(n1229), .B0(DmP_EXP_EWSW[11]),
.B1(n1227), .Y(n1207) );
AOI22X1TS U1819 ( .A0(intDX_EWSW[12]), .A1(n1229), .B0(DmP_EXP_EWSW[12]),
.B1(n1227), .Y(n1208) );
AOI22X1TS U1820 ( .A0(intDX_EWSW[8]), .A1(n1229), .B0(DmP_EXP_EWSW[8]), .B1(
n1227), .Y(n1209) );
AOI22X1TS U1821 ( .A0(intDX_EWSW[9]), .A1(n1229), .B0(DmP_EXP_EWSW[9]), .B1(
n1227), .Y(n1210) );
BUFX3TS U1822 ( .A(Shift_reg_FLAGS_7[2]), .Y(n1626) );
XOR2X1TS U1823 ( .A(n1561), .B(DmP_mant_SFG_SWR[24]), .Y(n1395) );
XOR2X1TS U1824 ( .A(n1222), .B(DmP_mant_SFG_SWR[23]), .Y(n1392) );
XOR2X1TS U1825 ( .A(n1222), .B(DmP_mant_SFG_SWR[22]), .Y(n1389) );
XOR2X1TS U1826 ( .A(n1222), .B(DmP_mant_SFG_SWR[21]), .Y(n1373) );
XOR2X1TS U1827 ( .A(n1222), .B(DmP_mant_SFG_SWR[20]), .Y(n1386) );
XOR2X1TS U1828 ( .A(OP_FLAG_SFG), .B(DmP_mant_SFG_SWR[15]), .Y(n1412) );
XOR2X1TS U1829 ( .A(n1222), .B(DmP_mant_SFG_SWR[14]), .Y(n1420) );
CLKXOR2X2TS U1830 ( .A(n1222), .B(DmP_mant_SFG_SWR[12]), .Y(n1620) );
CLKXOR2X2TS U1831 ( .A(n1222), .B(DmP_mant_SFG_SWR[11]), .Y(n1604) );
CLKXOR2X2TS U1832 ( .A(n1222), .B(DmP_mant_SFG_SWR[10]), .Y(n1601) );
CMPR32X2TS U1833 ( .A(n1604), .B(DMP_SFG[9]), .C(n1212), .CO(n1213) );
CMPR32X2TS U1834 ( .A(n1620), .B(DMP_SFG[10]), .C(n1213), .CO(n1214) );
XOR2X1TS U1835 ( .A(n1561), .B(DmP_mant_SFG_SWR[16]), .Y(n1215) );
XOR2X1TS U1836 ( .A(n1561), .B(DmP_mant_SFG_SWR[17]), .Y(n1216) );
XOR2X1TS U1837 ( .A(n1561), .B(DmP_mant_SFG_SWR[18]), .Y(n1217) );
XOR2X1TS U1838 ( .A(n1561), .B(DmP_mant_SFG_SWR[19]), .Y(n1219) );
XOR2X1TS U1839 ( .A(n1222), .B(DmP_mant_SFG_SWR[25]), .Y(n1223) );
NAND2X1TS U1840 ( .A(n1433), .B(Raw_mant_NRM_SWR[25]), .Y(n1225) );
AOI22X1TS U1841 ( .A0(intDX_EWSW[13]), .A1(n1229), .B0(DmP_EXP_EWSW[13]),
.B1(n1227), .Y(n1228) );
AOI22X1TS U1842 ( .A0(intDX_EWSW[15]), .A1(n1229), .B0(DmP_EXP_EWSW[15]),
.B1(n1461), .Y(n1230) );
AOI22X1TS U1843 ( .A0(Raw_mant_NRM_SWR[4]), .A1(n884), .B0(n1309), .B1(
DmP_mant_SHT1_SW[19]), .Y(n1232) );
OAI21X1TS U1844 ( .A0(n1690), .A1(n1490), .B0(n1232), .Y(n1233) );
AOI21X1TS U1845 ( .A0(n911), .A1(DmP_mant_SHT1_SW[18]), .B0(n1233), .Y(n1296) );
OAI22X1TS U1846 ( .A0(n1299), .A1(n907), .B0(n1741), .B1(n1345), .Y(n1234)
);
AOI21X1TS U1847 ( .A0(n1355), .A1(Data_array_SWR[18]), .B0(n1234), .Y(n1235)
);
AOI22X1TS U1848 ( .A0(n909), .A1(DmP_mant_SHT1_SW[21]), .B0(n1309), .B1(
DmP_mant_SHT1_SW[22]), .Y(n1236) );
OAI21X1TS U1849 ( .A0(n1748), .A1(n883), .B0(n1236), .Y(n1237) );
AOI21X1TS U1850 ( .A0(Raw_mant_NRM_SWR[2]), .A1(n905), .B0(n1237), .Y(n1483)
);
OAI22X1TS U1851 ( .A0(n1302), .A1(n907), .B0(n1730), .B1(n1345), .Y(n1239)
);
AOI21X1TS U1852 ( .A0(n1238), .A1(Data_array_SWR[21]), .B0(n1239), .Y(n1240)
);
INVX2TS U1853 ( .A(n1241), .Y(n1245) );
AOI22X1TS U1854 ( .A0(intDX_EWSW[31]), .A1(n1243), .B0(SIGN_FLAG_EXP), .B1(
n1256), .Y(n1244) );
BUFX3TS U1855 ( .A(n1187), .Y(n1278) );
AOI22X1TS U1856 ( .A0(intDX_EWSW[28]), .A1(n1281), .B0(DMP_EXP_EWSW[28]),
.B1(n1278), .Y(n1247) );
AOI22X1TS U1857 ( .A0(intDX_EWSW[1]), .A1(n1273), .B0(DMP_EXP_EWSW[1]), .B1(
n1514), .Y(n1248) );
AOI22X1TS U1858 ( .A0(intDX_EWSW[2]), .A1(n1273), .B0(DMP_EXP_EWSW[2]), .B1(
n1514), .Y(n1249) );
AOI22X1TS U1859 ( .A0(intDX_EWSW[6]), .A1(n1273), .B0(DMP_EXP_EWSW[6]), .B1(
n915), .Y(n1250) );
AOI22X1TS U1860 ( .A0(intDX_EWSW[5]), .A1(n1273), .B0(DMP_EXP_EWSW[5]), .B1(
n915), .Y(n1251) );
AOI22X1TS U1861 ( .A0(intDX_EWSW[4]), .A1(n1259), .B0(DMP_EXP_EWSW[4]), .B1(
n915), .Y(n1252) );
AOI22X1TS U1862 ( .A0(intDX_EWSW[29]), .A1(n1281), .B0(DMP_EXP_EWSW[29]),
.B1(n1256), .Y(n1254) );
AOI22X1TS U1863 ( .A0(intDX_EWSW[30]), .A1(n1281), .B0(DMP_EXP_EWSW[30]),
.B1(n1256), .Y(n1257) );
AOI22X1TS U1864 ( .A0(DMP_EXP_EWSW[23]), .A1(n1461), .B0(intDX_EWSW[23]),
.B1(n1273), .Y(n1258) );
CLKBUFX2TS U1865 ( .A(n1259), .Y(n1290) );
AOI22X1TS U1866 ( .A0(DMP_EXP_EWSW[27]), .A1(n1461), .B0(intDX_EWSW[27]),
.B1(n1290), .Y(n1260) );
AOI22X1TS U1867 ( .A0(intDX_EWSW[18]), .A1(n1281), .B0(DMP_EXP_EWSW[18]),
.B1(n1278), .Y(n1261) );
AOI22X1TS U1868 ( .A0(intDX_EWSW[14]), .A1(n1290), .B0(DMP_EXP_EWSW[14]),
.B1(n1278), .Y(n1262) );
AOI22X1TS U1869 ( .A0(intDX_EWSW[12]), .A1(n1290), .B0(DMP_EXP_EWSW[12]),
.B1(n915), .Y(n1263) );
AOI22X1TS U1870 ( .A0(intDX_EWSW[17]), .A1(n1281), .B0(DMP_EXP_EWSW[17]),
.B1(n1278), .Y(n1264) );
AOI22X1TS U1871 ( .A0(intDX_EWSW[8]), .A1(n1273), .B0(DMP_EXP_EWSW[8]), .B1(
n915), .Y(n1265) );
AOI22X1TS U1872 ( .A0(intDX_EWSW[11]), .A1(n1290), .B0(DMP_EXP_EWSW[11]),
.B1(n1278), .Y(n1266) );
AOI22X1TS U1873 ( .A0(intDX_EWSW[7]), .A1(n1273), .B0(DMP_EXP_EWSW[7]), .B1(
n915), .Y(n1267) );
AOI22X1TS U1874 ( .A0(intDX_EWSW[16]), .A1(n1259), .B0(DMP_EXP_EWSW[16]),
.B1(n1278), .Y(n1268) );
AOI22X1TS U1875 ( .A0(intDX_EWSW[0]), .A1(n1281), .B0(DMP_EXP_EWSW[0]), .B1(
n1514), .Y(n1269) );
AOI22X1TS U1876 ( .A0(intDX_EWSW[19]), .A1(n1290), .B0(DMP_EXP_EWSW[19]),
.B1(n1278), .Y(n1270) );
AOI22X1TS U1877 ( .A0(intDX_EWSW[9]), .A1(n1273), .B0(DMP_EXP_EWSW[9]), .B1(
n915), .Y(n1271) );
AOI22X1TS U1878 ( .A0(intDX_EWSW[10]), .A1(n1273), .B0(DMP_EXP_EWSW[10]),
.B1(n915), .Y(n1274) );
AOI22X1TS U1879 ( .A0(intDX_EWSW[22]), .A1(n1281), .B0(DMP_EXP_EWSW[22]),
.B1(n1278), .Y(n1276) );
AOI22X1TS U1880 ( .A0(intDX_EWSW[20]), .A1(n1281), .B0(DMP_EXP_EWSW[20]),
.B1(n1278), .Y(n1277) );
AOI22X1TS U1881 ( .A0(intDX_EWSW[21]), .A1(n1281), .B0(DMP_EXP_EWSW[21]),
.B1(n1278), .Y(n1279) );
AOI22X1TS U1882 ( .A0(intDX_EWSW[20]), .A1(n1285), .B0(DmP_EXP_EWSW[20]),
.B1(n1461), .Y(n1282) );
AOI22X1TS U1883 ( .A0(intDX_EWSW[22]), .A1(n1285), .B0(DmP_EXP_EWSW[22]),
.B1(n1461), .Y(n1283) );
AOI22X1TS U1884 ( .A0(intDX_EWSW[21]), .A1(n1285), .B0(DmP_EXP_EWSW[21]),
.B1(n1461), .Y(n1284) );
AOI22X1TS U1885 ( .A0(intDX_EWSW[19]), .A1(n1285), .B0(DmP_EXP_EWSW[19]),
.B1(n1461), .Y(n1286) );
OAI22X1TS U1886 ( .A0(n1748), .A1(n1490), .B0(n1673), .B1(n883), .Y(n1287)
);
AOI211X1TS U1887 ( .A0(DmP_mant_SHT1_SW[22]), .A1(n1496), .B0(n1309), .C0(
n1287), .Y(n1481) );
OAI22X1TS U1888 ( .A0(n1481), .A1(n901), .B0(n1293), .B1(n907), .Y(n1288) );
AOI21X1TS U1889 ( .A0(n1238), .A1(Data_array_SWR[22]), .B0(n1288), .Y(n1289)
);
AOI222X1TS U1890 ( .A0(n1189), .A1(intDX_EWSW[23]), .B0(DmP_EXP_EWSW[23]),
.B1(n1514), .C0(intDY_EWSW[23]), .C1(n1290), .Y(n1291) );
INVX2TS U1891 ( .A(n1291), .Y(n564) );
OAI22X1TS U1892 ( .A0(n1293), .A1(n901), .B0(n1687), .B1(n885), .Y(n1294) );
AOI21X1TS U1893 ( .A0(n1355), .A1(Data_array_SWR[20]), .B0(n1294), .Y(n1295)
);
AOI22X1TS U1894 ( .A0(Raw_mant_NRM_SWR[8]), .A1(n884), .B0(
DmP_mant_SHT1_SW[15]), .B1(n1335), .Y(n1297) );
OAI21X1TS U1895 ( .A0(n1729), .A1(n1490), .B0(n1297), .Y(n1298) );
AOI21X1TS U1896 ( .A0(DmP_mant_SHT1_SW[14]), .A1(n911), .B0(n1298), .Y(n1486) );
OAI22X1TS U1897 ( .A0(n1299), .A1(n900), .B0(n1741), .B1(n885), .Y(n1300) );
AOI21X1TS U1898 ( .A0(n1355), .A1(Data_array_SWR[16]), .B0(n1300), .Y(n1301)
);
AOI22X1TS U1899 ( .A0(n1355), .A1(Data_array_SWR[19]), .B0(
Raw_mant_NRM_SWR[3]), .B1(n886), .Y(n1304) );
AOI22X1TS U1900 ( .A0(Raw_mant_NRM_SWR[17]), .A1(n884), .B0(n1309), .B1(
DmP_mant_SHT1_SW[6]), .Y(n1306) );
AOI22X1TS U1901 ( .A0(Raw_mant_NRM_SWR[18]), .A1(n903), .B0(n909), .B1(
DmP_mant_SHT1_SW[5]), .Y(n1305) );
NAND2X1TS U1902 ( .A(n1306), .B(n1305), .Y(n1326) );
AOI22X1TS U1903 ( .A0(n1329), .A1(Data_array_SWR[5]), .B0(n1312), .B1(n1326),
.Y(n1308) );
NAND2X1TS U1904 ( .A(Raw_mant_NRM_SWR[19]), .B(n1352), .Y(n1307) );
AOI22X1TS U1905 ( .A0(Raw_mant_NRM_SWR[18]), .A1(n884), .B0(n1309), .B1(
DmP_mant_SHT1_SW[5]), .Y(n1311) );
AOI22X1TS U1906 ( .A0(Raw_mant_NRM_SWR[19]), .A1(n903), .B0(n909), .B1(
DmP_mant_SHT1_SW[4]), .Y(n1310) );
NAND2X1TS U1907 ( .A(n1311), .B(n1310), .Y(n1323) );
AOI22X1TS U1908 ( .A0(n1329), .A1(Data_array_SWR[4]), .B0(n1312), .B1(n1323),
.Y(n1314) );
NAND2X1TS U1909 ( .A(Raw_mant_NRM_SWR[20]), .B(n1352), .Y(n1313) );
AOI22X1TS U1910 ( .A0(n1329), .A1(Data_array_SWR[2]), .B0(n906), .B1(n1315),
.Y(n1317) );
NAND2X1TS U1911 ( .A(Raw_mant_NRM_SWR[20]), .B(n886), .Y(n1316) );
AOI22X1TS U1912 ( .A0(n1329), .A1(Data_array_SWR[3]), .B0(n906), .B1(n1319),
.Y(n1321) );
NAND2X1TS U1913 ( .A(Raw_mant_NRM_SWR[19]), .B(n886), .Y(n1320) );
AOI22X1TS U1914 ( .A0(n1355), .A1(Data_array_SWR[6]), .B0(n906), .B1(n1323),
.Y(n1325) );
NAND2X1TS U1915 ( .A(Raw_mant_NRM_SWR[16]), .B(n886), .Y(n1324) );
AOI22X1TS U1916 ( .A0(n1329), .A1(Data_array_SWR[7]), .B0(n906), .B1(n1326),
.Y(n1328) );
NAND2X1TS U1917 ( .A(Raw_mant_NRM_SWR[15]), .B(n886), .Y(n1327) );
AOI22X1TS U1918 ( .A0(n1329), .A1(Data_array_SWR[9]), .B0(
Raw_mant_NRM_SWR[13]), .B1(n886), .Y(n1331) );
AOI22X1TS U1919 ( .A0(n1355), .A1(Data_array_SWR[13]), .B0(
Raw_mant_NRM_SWR[9]), .B1(n1343), .Y(n1334) );
OA22X1TS U1920 ( .A0(n1668), .A1(n1345), .B0(n1338), .B1(n900), .Y(n1333) );
AOI22X1TS U1921 ( .A0(n1355), .A1(Data_array_SWR[15]), .B0(
Raw_mant_NRM_SWR[7]), .B1(n1343), .Y(n1337) );
OA22X1TS U1922 ( .A0(n1729), .A1(n1345), .B0(n1342), .B1(n900), .Y(n1336) );
AOI22X1TS U1923 ( .A0(n1355), .A1(Data_array_SWR[17]), .B0(
Raw_mant_NRM_SWR[5]), .B1(n886), .Y(n1341) );
OA22X1TS U1924 ( .A0(n1691), .A1(n1345), .B0(n1339), .B1(n902), .Y(n1340) );
AOI22X1TS U1925 ( .A0(n1238), .A1(Data_array_SWR[11]), .B0(
Raw_mant_NRM_SWR[11]), .B1(n886), .Y(n1347) );
OA22X1TS U1926 ( .A0(n1740), .A1(n1345), .B0(n1344), .B1(n900), .Y(n1346) );
AOI22X1TS U1927 ( .A0(n909), .A1(DmP_mant_SHT1_SW[8]), .B0(n1349), .B1(
DmP_mant_SHT1_SW[9]), .Y(n1350) );
AOI21X1TS U1928 ( .A0(Raw_mant_NRM_SWR[15]), .A1(n904), .B0(n1351), .Y(n1494) );
OAI2BB2XLTS U1929 ( .B0(n1353), .B1(n907), .A0N(Raw_mant_NRM_SWR[16]), .A1N(
n1352), .Y(n1354) );
AOI21X1TS U1930 ( .A0(n1355), .A1(Data_array_SWR[8]), .B0(n1354), .Y(n1356)
);
OAI21X1TS U1931 ( .A0(n1494), .A1(n902), .B0(n1356), .Y(n779) );
OAI2BB2XLTS U1932 ( .B0(n1357), .B1(n1457), .A0N(final_result_ieee[31]),
.A1N(n1463), .Y(n543) );
AOI32X4TS U1933 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
inst_FSM_INPUT_ENABLE_state_reg[0]), .A2(
inst_FSM_INPUT_ENABLE_state_reg[2]), .B0(n1358), .B1(n1704), .Y(n1464)
);
MXI2X1TS U1934 ( .A(n1433), .B(n882), .S0(n1464), .Y(n865) );
AOI22X1TS U1935 ( .A0(Data_array_SWR[23]), .A1(n891), .B0(Data_array_SWR[19]), .B1(n996), .Y(n1369) );
AOI22X1TS U1936 ( .A0(Data_array_SWR[10]), .A1(n894), .B0(Data_array_SWR[15]), .B1(n892), .Y(n1359) );
OAI221X1TS U1937 ( .A0(n1371), .A1(n1369), .B0(n1652), .B1(n1370), .C0(n1359), .Y(n1633) );
AOI22X1TS U1938 ( .A0(Data_array_SWR[22]), .A1(n891), .B0(Data_array_SWR[18]), .B1(n996), .Y(n1366) );
AOI22X1TS U1939 ( .A0(Data_array_SWR[14]), .A1(n892), .B0(Data_array_SWR[11]), .B1(n894), .Y(n1360) );
OAI221X1TS U1940 ( .A0(n897), .A1(n1366), .B0(n1652), .B1(n1367), .C0(n1360),
.Y(n1630) );
AOI22X1TS U1941 ( .A0(Data_array_SWR[12]), .A1(n894), .B0(Data_array_SWR[13]), .B1(n892), .Y(n1361) );
OAI221X1TS U1942 ( .A0(n1371), .A1(n1363), .B0(n1652), .B1(n1364), .C0(n1361), .Y(n1628) );
AOI22X1TS U1943 ( .A0(Data_array_SWR[12]), .A1(n892), .B0(Data_array_SWR[13]), .B1(n894), .Y(n1362) );
OAI221X1TS U1944 ( .A0(n897), .A1(n1364), .B0(n1652), .B1(n1363), .C0(n1362),
.Y(n1627) );
AOI22X1TS U1945 ( .A0(Data_array_SWR[14]), .A1(n894), .B0(Data_array_SWR[11]), .B1(n892), .Y(n1365) );
OAI221X1TS U1946 ( .A0(n897), .A1(n1367), .B0(n1652), .B1(n1366), .C0(n1365),
.Y(n1629) );
AOI22X1TS U1947 ( .A0(Data_array_SWR[10]), .A1(n892), .B0(Data_array_SWR[15]), .B1(n894), .Y(n1368) );
OAI221X1TS U1948 ( .A0(n897), .A1(n1370), .B0(n896), .B1(n1369), .C0(n1368),
.Y(n1631) );
BUFX3TS U1949 ( .A(n1648), .Y(n1525) );
AFHCONX2TS U1950 ( .A(DMP_SFG[19]), .B(n1373), .CI(n1372), .CON(n1388), .S(
n1374) );
INVX2TS U1951 ( .A(n1379), .Y(n1381) );
AFHCINX2TS U1952 ( .CIN(n1385), .B(n1386), .A(DMP_SFG[18]), .S(n1387), .CO(
n1372) );
AFHCINX2TS U1953 ( .CIN(n1388), .B(n1389), .A(DMP_SFG[20]), .S(n1390), .CO(
n1391) );
AFHCONX2TS U1954 ( .A(DMP_SFG[21]), .B(n1392), .CI(n1391), .CON(n1394), .S(
n1393) );
AFHCINX2TS U1955 ( .CIN(n1394), .B(n1395), .A(DMP_SFG[22]), .S(n1396), .CO(
n1224) );
INVX2TS U1956 ( .A(n1405), .Y(n1407) );
INVX2TS U1957 ( .A(n1609), .Y(n1527) );
XNOR2X1TS U1958 ( .A(n1601), .B(DMP_SFG[8]), .Y(n1431) );
INVX2TS U1959 ( .A(n1431), .Y(n1432) );
NAND2X1TS U1960 ( .A(n1550), .B(n1735), .Y(n1422) );
NAND2X1TS U1961 ( .A(n1575), .B(DMP_SFG[4]), .Y(n1576) );
XOR2X1TS U1962 ( .A(n1561), .B(DmP_mant_SFG_SWR[7]), .Y(n1423) );
NAND2X1TS U1963 ( .A(n1423), .B(DMP_SFG[5]), .Y(n1578) );
INVX2TS U1964 ( .A(n1578), .Y(n1424) );
NOR2X1TS U1965 ( .A(n1425), .B(n1424), .Y(n1584) );
INVX2TS U1966 ( .A(DmP_mant_SFG_SWR[9]), .Y(n1665) );
NOR2BX1TS U1967 ( .AN(n1665), .B(n1561), .Y(n1427) );
NOR2X1TS U1968 ( .A(n1428), .B(n1427), .Y(n1430) );
INVX2TS U1969 ( .A(DmP_mant_SFG_SWR[8]), .Y(n1662) );
NAND2X1TS U1970 ( .A(n1550), .B(n1662), .Y(n1429) );
NOR2X1TS U1971 ( .A(n1583), .B(DMP_SFG[6]), .Y(n1592) );
NAND2X1TS U1972 ( .A(n1583), .B(DMP_SFG[6]), .Y(n1593) );
NAND2X1TS U1973 ( .A(n1430), .B(DMP_SFG[7]), .Y(n1595) );
OA21XLTS U1974 ( .A0(n1596), .A1(n1593), .B0(n1595), .Y(n1613) );
OAI31X1TS U1975 ( .A0(n1584), .A1(n1596), .A2(n1592), .B0(n1613), .Y(n1600)
);
MXI2X1TS U1976 ( .A(n1432), .B(n1431), .S0(n1600), .Y(n1434) );
MXI2X1TS U1977 ( .A(n1434), .B(n1686), .S0(n1433), .Y(n532) );
OAI2BB1X1TS U1978 ( .A0N(LZD_output_NRM2_EW[4]), .A1N(n899), .B0(n1435), .Y(
n512) );
OAI32X1TS U1979 ( .A0(n1496), .A1(Raw_mant_NRM_SWR[14]), .A2(n1438), .B0(
n1437), .B1(n899), .Y(n1442) );
AOI21X1TS U1980 ( .A0(n1444), .A1(Raw_mant_NRM_SWR[10]), .B0(n1443), .Y(
n1502) );
AOI22X1TS U1981 ( .A0(Raw_mant_NRM_SWR[3]), .A1(n1447), .B0(n1446), .B1(
Raw_mant_NRM_SWR[5]), .Y(n1449) );
OAI21X1TS U1982 ( .A0(n1453), .A1(n1452), .B0(n898), .Y(n1497) );
OAI2BB1X1TS U1983 ( .A0N(LZD_output_NRM2_EW[2]), .A1N(n1496), .B0(n1497),
.Y(n514) );
OA21XLTS U1984 ( .A0(Shift_reg_FLAGS_7[0]), .A1(overflow_flag), .B0(n1457),
.Y(n558) );
AOI22X1TS U1985 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
inst_FSM_INPUT_ENABLE_state_reg[0]), .B0(n1459), .B1(n1674), .Y(
inst_FSM_INPUT_ENABLE_state_next_1_) );
NAND2X1TS U1986 ( .A(n1459), .B(n1458), .Y(n871) );
INVX2TS U1987 ( .A(n1464), .Y(n1462) );
AOI22X1TS U1988 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(n1460), .B0(
inst_FSM_INPUT_ENABLE_state_reg[2]), .B1(n1674), .Y(n1465) );
BUFX3TS U1989 ( .A(n1752), .Y(n1535) );
AOI22X1TS U1990 ( .A0(n1464), .A1(n1461), .B0(n1535), .B1(n1462), .Y(n868)
);
AOI22X1TS U1991 ( .A0(n1464), .A1(n1535), .B0(n1755), .B1(n1462), .Y(n867)
);
AOI22X1TS U1992 ( .A0(n1464), .A1(n1684), .B0(n1496), .B1(n1462), .Y(n864)
);
AOI22X1TS U1993 ( .A0(n1464), .A1(n899), .B0(n1463), .B1(n1462), .Y(n863) );
INVX2TS U1994 ( .A(n1470), .Y(n1466) );
BUFX3TS U1995 ( .A(n1470), .Y(n1476) );
INVX2TS U1996 ( .A(n1480), .Y(n1467) );
BUFX3TS U1997 ( .A(n1470), .Y(n1469) );
BUFX3TS U1998 ( .A(n1473), .Y(n1468) );
INVX2TS U1999 ( .A(n1480), .Y(n1479) );
INVX2TS U2000 ( .A(n1473), .Y(n1471) );
BUFX3TS U2001 ( .A(n1470), .Y(n1477) );
INVX2TS U2002 ( .A(n1473), .Y(n1472) );
BUFX3TS U2003 ( .A(n1470), .Y(n1475) );
INVX2TS U2004 ( .A(n1473), .Y(n1474) );
AOI21X1TS U2005 ( .A0(n904), .A1(Raw_mant_NRM_SWR[0]), .B0(n911), .Y(n1482)
);
OAI2BB2XLTS U2006 ( .B0(n1482), .B1(n908), .A0N(n1238), .A1N(
Data_array_SWR[25]), .Y(n796) );
OAI2BB2XLTS U2007 ( .B0(n1481), .B1(n908), .A0N(n1238), .A1N(
Data_array_SWR[24]), .Y(n795) );
OAI222X1TS U2008 ( .A0(n1742), .A1(n1500), .B0(n1495), .B1(n1483), .C0(n902),
.C1(n1482), .Y(n794) );
AOI22X1TS U2009 ( .A0(Raw_mant_NRM_SWR[10]), .A1(n884), .B0(n1309), .B1(
DmP_mant_SHT1_SW[13]), .Y(n1484) );
AOI21X1TS U2010 ( .A0(n911), .A1(DmP_mant_SHT1_SW[12]), .B0(n1485), .Y(n1492) );
OAI222X1TS U2011 ( .A0(n1500), .A1(n1744), .B0(n908), .B1(n1492), .C0(n901),
.C1(n1486), .Y(n785) );
AOI22X1TS U2012 ( .A0(Raw_mant_NRM_SWR[12]), .A1(n1488), .B0(n1487), .B1(
DmP_mant_SHT1_SW[11]), .Y(n1489) );
AOI21X1TS U2013 ( .A0(n910), .A1(DmP_mant_SHT1_SW[10]), .B0(n1491), .Y(n1493) );
OAI222X1TS U2014 ( .A0(n1743), .A1(n1500), .B0(n1495), .B1(n1493), .C0(n901),
.C1(n1492), .Y(n783) );
OAI222X1TS U2015 ( .A0(n1751), .A1(n1500), .B0(n1495), .B1(n1494), .C0(n902),
.C1(n1493), .Y(n781) );
NAND2X1TS U2016 ( .A(n1498), .B(n1497), .Y(n770) );
AOI21X1TS U2017 ( .A0(busy), .A1(Shift_amount_SHT1_EWR[3]), .B0(
Shift_reg_FLAGS_7[1]), .Y(n1501) );
OAI22X1TS U2018 ( .A0(n1502), .A1(n1501), .B0(n1500), .B1(n1689), .Y(n769)
);
INVX2TS U2019 ( .A(n1535), .Y(n1538) );
AOI21X1TS U2020 ( .A0(DMP_EXP_EWSW[23]), .A1(n914), .B0(n1506), .Y(n1503) );
INVX2TS U2021 ( .A(n1537), .Y(n1512) );
AOI21X1TS U2022 ( .A0(DMP_EXP_EWSW[24]), .A1(n880), .B0(n1504), .Y(n1505) );
XNOR2X1TS U2023 ( .A(n1506), .B(n1505), .Y(n1507) );
XNOR2X1TS U2024 ( .A(n1510), .B(n1509), .Y(n1511) );
OAI222X1TS U2025 ( .A0(n1531), .A1(n1745), .B0(n1681), .B1(n1532), .C0(n1669), .C1(n1533), .Y(n729) );
OAI222X1TS U2026 ( .A0(n1531), .A1(n1682), .B0(n913), .B1(n1532), .C0(n1709),
.C1(n1533), .Y(n728) );
OAI222X1TS U2027 ( .A0(n1531), .A1(n1750), .B0(n1683), .B1(n1532), .C0(n1722), .C1(n1533), .Y(n727) );
INVX2TS U2028 ( .A(n1517), .Y(n1515) );
BUFX3TS U2029 ( .A(n1752), .Y(n1518) );
BUFX3TS U2030 ( .A(n1523), .Y(n1519) );
BUFX3TS U2031 ( .A(n1648), .Y(n1536) );
INVX2TS U2032 ( .A(n1755), .Y(n1524) );
INVX2TS U2033 ( .A(n1537), .Y(n1520) );
BUFX3TS U2034 ( .A(n1752), .Y(n1521) );
BUFX3TS U2035 ( .A(n1523), .Y(n1522) );
INVX2TS U2036 ( .A(n1755), .Y(n1526) );
INVX2TS U2037 ( .A(n1752), .Y(n1540) );
BUFX3TS U2038 ( .A(n1752), .Y(n1539) );
BUFX3TS U2039 ( .A(Shift_reg_FLAGS_7[2]), .Y(n1558) );
BUFX3TS U2040 ( .A(n1523), .Y(n1541) );
INVX2TS U2041 ( .A(Shift_reg_FLAGS_7[2]), .Y(n1607) );
INVX2TS U2042 ( .A(n1535), .Y(n1528) );
BUFX3TS U2043 ( .A(n1537), .Y(n1529) );
BUFX3TS U2044 ( .A(n1535), .Y(n1530) );
OAI222X1TS U2045 ( .A0(n1533), .A1(n1745), .B0(n880), .B1(n1532), .C0(n1669),
.C1(n1531), .Y(n563) );
OAI222X1TS U2046 ( .A0(n1533), .A1(n1682), .B0(n1746), .B1(n1532), .C0(n1709), .C1(n1531), .Y(n562) );
OAI222X1TS U2047 ( .A0(n1533), .A1(n1750), .B0(n881), .B1(n1532), .C0(n1722),
.C1(n1531), .Y(n561) );
OAI2BB1X1TS U2048 ( .A0N(underflow_flag), .A1N(n1738), .B0(n1534), .Y(n559)
);
NAND2X1TS U2049 ( .A(n1550), .B(DmP_mant_SFG_SWR[2]), .Y(n1544) );
OAI21X1TS U2050 ( .A0(n1550), .A1(DmP_mant_SFG_SWR[2]), .B0(n1544), .Y(n1545) );
NOR2X2TS U2051 ( .A(n1545), .B(n879), .Y(n1553) );
AOI22X1TS U2052 ( .A0(n1626), .A1(n1546), .B0(n1687), .B1(n1684), .Y(n540)
);
MXI2X1TS U2053 ( .A(n1731), .B(DmP_mant_SFG_SWR[3]), .S0(n1550), .Y(n1551)
);
XNOR2X1TS U2054 ( .A(n1551), .B(DMP_SFG[1]), .Y(n1547) );
XOR2X1TS U2055 ( .A(n1547), .B(n1553), .Y(n1548) );
AOI22X1TS U2056 ( .A0(n1626), .A1(n1548), .B0(n1730), .B1(n1684), .Y(n539)
);
INVX2TS U2057 ( .A(DmP_mant_SFG_SWR[4]), .Y(n1656) );
NAND2X1TS U2058 ( .A(n1550), .B(n1656), .Y(n1549) );
XNOR2X1TS U2059 ( .A(n1554), .B(DMP_SFG[2]), .Y(n1557) );
OAI21X2TS U2060 ( .A0(n1553), .A1(DMP_SFG[1]), .B0(n1552), .Y(n1570) );
NAND2X1TS U2061 ( .A(n1554), .B(DMP_SFG[2]), .Y(n1567) );
INVX2TS U2062 ( .A(n1567), .Y(n1555) );
NOR2BX1TS U2063 ( .AN(n1733), .B(n1561), .Y(n1560) );
AOI21X1TS U2064 ( .A0(n1561), .A1(DmP_mant_SFG_SWR[5]), .B0(n1560), .Y(n1562) );
NAND2X1TS U2065 ( .A(n1562), .B(DMP_SFG[3]), .Y(n1566) );
XNOR2X1TS U2066 ( .A(n1564), .B(n1563), .Y(n1565) );
AOI22X1TS U2067 ( .A0(n1626), .A1(n1565), .B0(n1690), .B1(n1684), .Y(n537)
);
XNOR2X1TS U2068 ( .A(n1575), .B(DMP_SFG[4]), .Y(n1571) );
INVX2TS U2069 ( .A(n1571), .Y(n1572) );
OA21XLTS U2070 ( .A0(n1567), .A1(n1568), .B0(n1566), .Y(n1587) );
OAI31X1TS U2071 ( .A0(n1570), .A1(n1569), .A2(n1568), .B0(n1587), .Y(n1574)
);
MXI2X1TS U2072 ( .A(n1572), .B(n1571), .S0(n1574), .Y(n1573) );
AOI22X1TS U2073 ( .A0(n1626), .A1(n1573), .B0(n1741), .B1(n1607), .Y(n536)
);
NOR2X1TS U2074 ( .A(n1575), .B(DMP_SFG[4]), .Y(n1585) );
INVX2TS U2075 ( .A(n1586), .Y(n1579) );
NAND2X1TS U2076 ( .A(n1579), .B(n1578), .Y(n1580) );
XNOR2X1TS U2077 ( .A(n1581), .B(n1580), .Y(n1582) );
AOI22X1TS U2078 ( .A0(n1626), .A1(n1582), .B0(n1691), .B1(n1607), .Y(n535)
);
XNOR2X1TS U2079 ( .A(n1583), .B(DMP_SFG[6]), .Y(n1588) );
INVX2TS U2080 ( .A(n1588), .Y(n1589) );
OAI31X1TS U2081 ( .A0(n1587), .A1(n1586), .A2(n1585), .B0(n1584), .Y(n1591)
);
MXI2X1TS U2082 ( .A(n1589), .B(n1588), .S0(n1591), .Y(n1590) );
AOI22X1TS U2083 ( .A0(n1609), .A1(n1590), .B0(n1695), .B1(n1607), .Y(n534)
);
XNOR2X1TS U2084 ( .A(n1598), .B(n1597), .Y(n1599) );
AOI22X1TS U2085 ( .A0(Shift_reg_FLAGS_7[2]), .A1(n1599), .B0(n1729), .B1(
n1684), .Y(n533) );
NAND2X1TS U2086 ( .A(n1601), .B(DMP_SFG[8]), .Y(n1612) );
NOR2X1TS U2087 ( .A(n1601), .B(DMP_SFG[8]), .Y(n1611) );
AOI21X1TS U2088 ( .A0(n1602), .A1(n1612), .B0(n1611), .Y(n1606) );
NOR2X1TS U2089 ( .A(n1603), .B(n1749), .Y(n1614) );
NOR2X1TS U2090 ( .A(n1604), .B(DMP_SFG[9]), .Y(n1610) );
XNOR2X1TS U2091 ( .A(n1606), .B(n1605), .Y(n1608) );
AOI22X1TS U2092 ( .A0(n1609), .A1(n1608), .B0(n1668), .B1(n1607), .Y(n531)
);
AOI211X1TS U2093 ( .A0(n1613), .A1(n1612), .B0(n1611), .C0(n1610), .Y(n1615)
);
NOR2X2TS U2094 ( .A(n1615), .B(n1614), .Y(n1618) );
XOR2X1TS U2095 ( .A(n1620), .B(n1747), .Y(n1616) );
XNOR2X1TS U2096 ( .A(n1618), .B(n1616), .Y(n1617) );
INVX2TS U2097 ( .A(n1618), .Y(n1619) );
OAI22X1TS U2098 ( .A0(n1621), .A1(n1620), .B0(DMP_SFG[10]), .B1(n1619), .Y(
n1624) );
XOR2X1TS U2099 ( .A(n1622), .B(DMP_SFG[11]), .Y(n1623) );
XOR2X1TS U2100 ( .A(n1624), .B(n1623), .Y(n1625) );
AOI22X1TS U2101 ( .A0(n1626), .A1(n1625), .B0(n1740), .B1(n1684), .Y(n529)
);
OAI2BB2XLTS U2102 ( .B0(n1635), .B1(n912), .A0N(final_result_ieee[14]),
.A1N(n1738), .Y(n504) );
OAI2BB2XLTS U2103 ( .B0(n1636), .B1(n912), .A0N(final_result_ieee[15]),
.A1N(n1738), .Y(n502) );
OAI2BB2XLTS U2104 ( .B0(n1637), .B1(n1646), .A0N(final_result_ieee[16]),
.A1N(n1645), .Y(n500) );
OAI2BB2XLTS U2105 ( .B0(n1638), .B1(n912), .A0N(final_result_ieee[17]),
.A1N(n1645), .Y(n498) );
OAI2BB2XLTS U2106 ( .B0(n1658), .B1(n912), .A0N(final_result_ieee[3]), .A1N(
n1738), .Y(n497) );
OAI2BB2XLTS U2107 ( .B0(n1641), .B1(n912), .A0N(final_result_ieee[18]),
.A1N(n1645), .Y(n496) );
OAI2BB2XLTS U2108 ( .B0(n1657), .B1(n912), .A0N(final_result_ieee[2]), .A1N(
n1738), .Y(n495) );
OAI2BB2XLTS U2109 ( .B0(n1647), .B1(n912), .A0N(final_result_ieee[19]),
.A1N(n1645), .Y(n494) );
BUFX3TS U2110 ( .A(n1648), .Y(n1667) );
AOI22X1TS U2111 ( .A0(Data_array_SWR[25]), .A1(n895), .B0(n896), .B1(n1649),
.Y(n1650) );
AOI22X1TS U2112 ( .A0(n1667), .A1(n1650), .B0(n920), .B1(n1664), .Y(n488) );
AOI22X1TS U2113 ( .A0(Data_array_SWR[24]), .A1(n895), .B0(n896), .B1(n1651),
.Y(n1653) );
AOI22X1TS U2114 ( .A0(n1667), .A1(n1653), .B0(n919), .B1(n1664), .Y(n487) );
AOI22X1TS U2115 ( .A0(n1667), .A1(n1654), .B0(n1732), .B1(n1664), .Y(n486)
);
AOI22X1TS U2116 ( .A0(n1667), .A1(n1655), .B0(n1731), .B1(n1664), .Y(n485)
);
AOI22X1TS U2117 ( .A0(n1667), .A1(n1657), .B0(n1656), .B1(n1664), .Y(n484)
);
AOI22X1TS U2118 ( .A0(n1667), .A1(n1658), .B0(n1733), .B1(n1661), .Y(n483)
);
AOI22X1TS U2119 ( .A0(n1667), .A1(n1659), .B0(n1735), .B1(n1661), .Y(n482)
);
AOI22X1TS U2120 ( .A0(n1667), .A1(n1660), .B0(n1753), .B1(n1661), .Y(n481)
);
AOI22X1TS U2121 ( .A0(n1667), .A1(n1663), .B0(n1662), .B1(n1661), .Y(n480)
);
AOI22X1TS U2122 ( .A0(n1667), .A1(n1666), .B0(n1665), .B1(n1664), .Y(n479)
);
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_ASIC_fpadd_approx_syn_constraints_clk10.tcl_GeArN16R2P4_syn.sdf");
endmodule
|
// Accellera Standard V2.5 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2010. All rights reserved.
wire [width-1:0] test_expr_i = ~test_expr;
wire [width-1:0] test_expr_i_1 = test_expr_i - {{width-1{1'b0}},1'b1};
wire inactive_val=(inactive==`OVL_ALL_ONES)?1'b1:1'b0;
`ifdef OVL_ASSERT_ON
always @(posedge clk) begin
if (`OVL_RESET_SIGNAL != 1'b0) begin
if ((test_expr ^ test_expr)=={width{1'b0}}) begin
// OK, test_expr contains no X/Z.
if ((inactive>`OVL_ALL_ONES) || (test_expr!={width{inactive_val}})) begin
if (( test_expr_i == {width{1'b0}}) ||
((test_expr_i & test_expr_i_1) != {width{1'b0}})) begin
ovl_error_t(`OVL_FIRE_2STATE,"Test expression contains more or less than 1 deasserted bits");
end
end
end
else begin
`ifdef OVL_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
//Do nothing
`else
ovl_error_t(`OVL_FIRE_XCHECK,"test_expr contains X or Z");
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
end
end
end // always
`endif // OVL_ASSERT_ON
`ifdef OVL_COVER_ON
reg [width-1:0] prev_test_expr;
reg [width-1:0] one_colds_checked;
reg [width-1:0] prev_one_colds_checked;
`ifdef OVL_SYNTHESIS
`else
initial begin
one_colds_checked = {width{1'b0}};
prev_one_colds_checked = {width{1'b0}};
end
`endif
always @(posedge clk) begin
if (`OVL_RESET_SIGNAL != 1'b0) begin
if (coverage_level != `OVL_COVER_NONE) begin
if (test_expr != prev_test_expr) begin
if (OVL_COVER_SANITY_ON) begin //sanity coverage
ovl_cover_t("test_expr_change covered");
end //sanity coverage
if (OVL_COVER_CORNER_ON) begin //corner coverage
if (inactive == `OVL_ALL_ZEROS) begin
if (test_expr == {width{inactive_val}}) begin
ovl_cover_t("test_expr_all_zeros covered");
end
end
if (inactive == `OVL_ALL_ONES) begin
if (test_expr == {width{inactive_val}}) begin
ovl_cover_t("test_expr_all_ones covered");
end
end
end //corner coverage
end //test_expr != prev_test_expr
prev_test_expr <= test_expr;
if (OVL_COVER_CORNER_ON) begin //corner coverage2
if ((test_expr ^ test_expr)=={width{1'b0}}) begin
if ((inactive>`OVL_ALL_ONES) || (test_expr!={width{inactive_val}})) begin
if (!((test_expr_i == {width{1'b0}}) ||
(test_expr_i & test_expr_i_1) != {width{1'b0}})) begin
one_colds_checked <= one_colds_checked | (~test_expr);
end
end
end
prev_one_colds_checked <= one_colds_checked;
if ( (prev_one_colds_checked != one_colds_checked) &&
(one_colds_checked == {width{1'b1}}) ) begin
ovl_cover_t("all_one_colds_checked covered");
end
end //corner coverage2
end // OVL_COVER_NONE
end
else begin
`ifdef OVL_INIT_REG
prev_test_expr <= {width{1'b0}};
one_colds_checked <= {width{1'b0}};
prev_one_colds_checked <= {width{1'b0}};
`endif
end
end // always
`endif // OVL_COVER_ON
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__AND4_BLACKBOX_V
`define SKY130_FD_SC_HD__AND4_BLACKBOX_V
/**
* and4: 4-input AND.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__and4 (
X,
A,
B,
C,
D
);
output X;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__AND4_BLACKBOX_V
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Wed May 31 20:17:05 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/ZyboIP/examples/dma_example/dma_example.srcs/sources_1/bd/system/ip/system_auto_pc_0/system_auto_pc_0_stub.v
// Design : system_auto_pc_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "axi_protocol_converter_v2_1_11_axi_protocol_converter,Vivado 2016.4" *)
module system_auto_pc_0(aclk, aresetn, s_axi_awid, s_axi_awaddr,
s_axi_awlen, s_axi_awsize, s_axi_awburst, s_axi_awlock, s_axi_awcache, s_axi_awprot,
s_axi_awqos, s_axi_awvalid, s_axi_awready, s_axi_wid, s_axi_wdata, s_axi_wstrb, s_axi_wlast,
s_axi_wvalid, s_axi_wready, s_axi_bid, s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_arid,
s_axi_araddr, s_axi_arlen, s_axi_arsize, s_axi_arburst, s_axi_arlock, s_axi_arcache,
s_axi_arprot, s_axi_arqos, s_axi_arvalid, s_axi_arready, s_axi_rid, s_axi_rdata, s_axi_rresp,
s_axi_rlast, s_axi_rvalid, s_axi_rready, m_axi_awaddr, m_axi_awprot, m_axi_awvalid,
m_axi_awready, m_axi_wdata, m_axi_wstrb, m_axi_wvalid, m_axi_wready, m_axi_bresp,
m_axi_bvalid, m_axi_bready, m_axi_araddr, m_axi_arprot, m_axi_arvalid, m_axi_arready,
m_axi_rdata, m_axi_rresp, m_axi_rvalid, m_axi_rready)
/* synthesis syn_black_box black_box_pad_pin="aclk,aresetn,s_axi_awid[11:0],s_axi_awaddr[31:0],s_axi_awlen[3:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[1:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awqos[3:0],s_axi_awvalid,s_axi_awready,s_axi_wid[11:0],s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bid[11:0],s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_arid[11:0],s_axi_araddr[31:0],s_axi_arlen[3:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[1:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arqos[3:0],s_axi_arvalid,s_axi_arready,s_axi_rid[11:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_awaddr[31:0],m_axi_awprot[2:0],m_axi_awvalid,m_axi_awready,m_axi_wdata[31:0],m_axi_wstrb[3:0],m_axi_wvalid,m_axi_wready,m_axi_bresp[1:0],m_axi_bvalid,m_axi_bready,m_axi_araddr[31:0],m_axi_arprot[2:0],m_axi_arvalid,m_axi_arready,m_axi_rdata[31:0],m_axi_rresp[1:0],m_axi_rvalid,m_axi_rready" */;
input aclk;
input aresetn;
input [11:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [3:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [1:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awqos;
input s_axi_awvalid;
output s_axi_awready;
input [11:0]s_axi_wid;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [11:0]s_axi_bid;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [11:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [3:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [1:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arqos;
input s_axi_arvalid;
output s_axi_arready;
output [11:0]s_axi_rid;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
output [31:0]m_axi_awaddr;
output [2:0]m_axi_awprot;
output m_axi_awvalid;
input m_axi_awready;
output [31:0]m_axi_wdata;
output [3:0]m_axi_wstrb;
output m_axi_wvalid;
input m_axi_wready;
input [1:0]m_axi_bresp;
input m_axi_bvalid;
output m_axi_bready;
output [31:0]m_axi_araddr;
output [2:0]m_axi_arprot;
output m_axi_arvalid;
input m_axi_arready;
input [31:0]m_axi_rdata;
input [1:0]m_axi_rresp;
input m_axi_rvalid;
output m_axi_rready;
endmodule
|
`include "core.h"
`default_nettype none
module pipeline_control(
input wire iCLOCK,
input wire inRESET,
input wire iRESET_SYNC,
//Core Internal Event
output wire oEVENT_HOLD,
output wire oEVENT_START,
output wire oEVENT_IRQ_FRONT2BACK,
output wire oEVENT_IRQ_BACK2FRONT,
output wire oEVENT_CACHE_ERASE,
output wire oEVENT_TLB_ERASE,
output wire oEVENT_END, //Set Register
//Core Internal Event - Set System Register
output wire oEVENT_SETREG_PCR_SET,
output wire oEVENT_SETREG_PPCR_SET,
output wire oEVENT_SETREG_SPR_SET,
output wire oEVENT_SETREG_FI0R_SET,
output wire oEVENT_SETREG_FI1R_SET,
output wire [31:0] oEVENT_SETREG_PCR,
output wire [31:0] oEVENT_SETREG_PPCR,
output wire [31:0] oEVENT_SETREG_SPR,
output wire [31:0] oEVENT_SETREG_FI0R,
output wire [31:0] oEVENT_SETREG_FI1R,
//System Register - Input
input wire [31:0] iSYSREG_SPR,
input wire [31:0] iSYSREG_TIDR,
input wire [31:0] iSYSREG_TISR,
input wire [31:0] iSYSREG_PSR,
input wire [31:0] iSYSREG_PCR,
input wire [31:0] iSYSREG_PPSR,
input wire [31:0] iSYSREG_PPCR,
input wire [31:0] iSYSREG_IDTR,
//Interrupt Lock
input wire iINTERRUPT_LOCK,
//IO Port
output wire oLDST_USE,
output wire oLDST_REQ,
input wire iLDST_BUSY,
output wire [1:0] oLDST_ORDER, //00=Byte Order 01=2Byte Order 10= Word Order 11= None
output wire oLDST_RW, //0=Read 1=Write
output wire [13:0] oLDST_ASID,
output wire [1:0] oLDST_MMUMOD,
output wire [31:0] oLDST_PDT,
output wire [31:0] oLDST_ADDR,
output wire [31:0] oLDST_DATA,
input wire iLDST_REQ,
input wire [31:0] iLDST_DATA,
//Interrupt Configlation Table for GCI
output wire oIO_IRQ_CONFIG_TABLE_REQ,
output wire [5:0] oIO_IRQ_CONFIG_TABLE_ENTRY,
output wire oIO_IRQ_CONFIG_TABLE_FLAG_MASK,
output wire oIO_IRQ_CONFIG_TABLE_FLAG_VALID,
output wire [1:0] oIO_IRQ_CONFIG_TABLE_FLAG_LEVEL,
//Interrupt Configlation Table for Interrupt Controler
output wire oICT_REQ,
output wire [5:0] oICT_ENTRY,
output wire oICT_CONF_MASK,
output wire oICT_CONF_VALID,
output wire [1:0] oICT_CONF_LEVEL,
//External Exception
input wire iEXCEPT_IRQ_REQ,
input wire [6:0] iEXCEPT_IRQ_NUM,
input wire [31:0] iEXCEPT_IRQ_FI0R,
input wire [31:0] iEXCEPT_IRQ_FI1R,
output wire oEXCEPT_IRQ_ACK,
output wire oEXCEPT_IRQ_BUSY,
//Execute
input wire [31:0] iEXE_JUMP_ADDR, //Common Jump Addres
input wire iEXE_BRANCH_VALID,
input wire iEXE_IDTS_VALID,
input wire iEXE_IB_VALID,
input wire iEXE_RELOAD_VALID
);
//Interrupt - Call
wire irq_call_finished;
wire [31:0] irq_call_hundler;
wire irq_call_spr_valid;
wire [31:0] irq_call_spr;
//Interrupt Return
wire irq_return_finished;
wire irq_return_spr_valid;
wire [31:0] irq_return_spr;
//IDT Read & Set
wire idt_read_finished;
/****************************************************************************************************
State
****************************************************************************************************/
localparam L_PARAM_IDLE = 3'h0;
localparam L_PARAM_ALU_JUMP_IRQ_CALL = 3'h1;
localparam L_PARAM_ALU_JUMP = 3'h2;
localparam L_PARAM_IRQ_CALL = 3'h3;
localparam L_PARAM_IRQ_RETURN = 3'h4;
localparam L_PARAM_IDT_SET = 3'h5; //IDTS Instruction
localparam L_PARAM_RELOAD = 3'h6;
reg [2:0] state;
reg [2:0] b_state;
//Start Condition
wire alu_jump_irq_call_start_condition = (b_state == L_PARAM_IDLE) && ((iEXCEPT_IRQ_REQ && !iINTERRUPT_LOCK && iSYSREG_PSR[2]) && iEXE_BRANCH_VALID);
wire alu_jump_start_condition = (b_state == L_PARAM_IDLE) && iEXE_BRANCH_VALID;
wire irq_call_start_condition = (b_state == L_PARAM_IDLE) && iEXCEPT_IRQ_REQ && !iINTERRUPT_LOCK && iSYSREG_PSR[2];
wire irq_return_start_condition = (b_state == L_PARAM_IDLE) && iEXE_IB_VALID;
wire idt_set_start_condition = (b_state == L_PARAM_IDLE) && iEXE_IDTS_VALID;
wire reload_start_condition = (b_state == L_PARAM_IDLE) && iEXE_RELOAD_VALID;
//Stop Condition
wire alu_jump_irq_call_finish_condition = (b_state == L_PARAM_ALU_JUMP_IRQ_CALL) && irq_call_finished;
wire alu_jump_finish_condition = (b_state == L_PARAM_ALU_JUMP);
wire irq_call_finish_condition = (b_state == L_PARAM_IRQ_CALL) && irq_call_finished;
wire irq_return_finish_condition = (b_state == L_PARAM_IRQ_RETURN) && irq_return_finished;
wire idt_set_finish_condition = (b_state == L_PARAM_IDT_SET) && idt_read_finished;
wire reload_finish_condition = (b_state == L_PARAM_RELOAD);
always@*begin
case(b_state)
L_PARAM_IDLE:
begin
//Core Jump Instruction and Interrupt
if(alu_jump_irq_call_start_condition)begin
state = L_PARAM_ALU_JUMP_IRQ_CALL;
end
//Interrupt
else if(irq_call_start_condition)begin
state = L_PARAM_IRQ_CALL;
end
//Core Jump Instruction
else if(alu_jump_start_condition)begin
state = L_PARAM_ALU_JUMP;
end
//Page Directory Table Set
//else if(iEXCEPT_PDTS && iSYSREG_PSR[1:0] != 2'h0)begin
else if(reload_start_condition)begin
state = L_PARAM_RELOAD; //MMU Mode or PDRT Change, so nessesary instruction reload.
end
//IDT Set Instruction
else if(idt_set_start_condition)begin
state = L_PARAM_IDT_SET;
end
//Interrupt Return Instruction
else if(irq_return_start_condition)begin
state = L_PARAM_IRQ_RETURN;
end
else begin
state = b_state;
end
end
L_PARAM_ALU_JUMP_IRQ_CALL:
begin
if(alu_jump_irq_call_finish_condition)begin
state = L_PARAM_IDLE;
end
else begin
state = b_state;
end
end
L_PARAM_ALU_JUMP:
begin
if(alu_jump_finish_condition)begin
state = L_PARAM_IDLE;
end
else begin
state = b_state;
end
end
L_PARAM_IRQ_CALL:
begin
if(irq_call_finish_condition)begin
state = L_PARAM_IDLE;
end
else begin
state = b_state;
end
end
L_PARAM_IRQ_RETURN:
begin
if(irq_return_finish_condition)begin
state = L_PARAM_IDLE;
end
else begin
state = b_state;
end
end
L_PARAM_IDT_SET:
begin
if(idt_set_finish_condition)begin
state = L_PARAM_IDLE;
end
else begin
state = b_state;
end
end
L_PARAM_RELOAD:
begin
if(reload_finish_condition)begin
state = L_PARAM_IDLE;
end
else begin
state = b_state;
end
end
default:
begin
state = b_state;
end
endcase
end
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_state <= L_PARAM_IDLE;
end
else if(iRESET_SYNC)begin
b_state <= L_PARAM_IDLE;
end
else begin
b_state <= state;
end
end
/****************************************************************************************************
Interrupt Controller
****************************************************************************************************/
reg b_irq_ack;
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_irq_ack <= 1'b0;
end
else if(iRESET_SYNC)begin
b_irq_ack <= 1'b0;
end
else begin
if(alu_jump_irq_call_finish_condition || irq_call_finish_condition)begin
b_irq_ack <= 1'b1;
end
else begin
b_irq_ack <= 1'b0;
end
end
end
assign oEXCEPT_IRQ_ACK = b_irq_ack;
assign oEXCEPT_IRQ_BUSY = 1'b0;
/****************************************************************************************************
Interrupt Call
****************************************************************************************************/
wire irq_call_ldst_use;
wire irq_call_ldst_req;
wire [1:0] irq_call_ldst_order;
wire irq_call_ldst_rw;
wire [13:0] irq_call_ldst_asid;
wire [1:0] irq_call_ldst_mmumod;
wire [31:0] irq_call_ldst_pdt;
wire [31:0] irq_call_ldst_addr;
wire [31:0] irq_call_ldst_data;
pipeline_control_irq_call IRQ_CALL(
.iCLOCK(iCLOCK),
.inRESET(inRESET),
.iRESET_SYNC(iRESET_SYNC),
//System Register
.iSYSREG_IDTR(iSYSREG_IDTR),
.iSYSREG_PSR(iSYSREG_PSR),
.iSYSREG_SPR(iSYSREG_SPR),
.iSYSREG_TISR(iSYSREG_TISR),
.iSYSREG_TIDR(iSYSREG_TIDR),
//Request
.iIRQ_START(alu_jump_irq_call_start_condition || irq_call_start_condition),
.iIRQ_NUM(iEXCEPT_IRQ_NUM),
//Finish
.oFINISH(irq_call_finished),
.oFINISH_HUNDLER(irq_call_hundler),
.oFINISH_SPR_VALID(irq_call_spr_valid),
.oFINISH_SPR(irq_call_spr),
//Load Store
.oLDST_USE(irq_call_ldst_use),
.oLDST_REQ(irq_call_ldst_req),
.iLDST_BUSY(iLDST_BUSY),
.oLDST_ORDER(irq_call_ldst_order), //00=Byte Order 01=2Byte Order 10= Word Order 11= None
.oLDST_RW(irq_call_ldst_rw), //0=Read 1=Write
.oLDST_ASID(irq_call_ldst_asid),
.oLDST_MMUMOD(irq_call_ldst_mmumod),
.oLDST_PDT(irq_call_ldst_pdt),
.oLDST_ADDR(irq_call_ldst_addr),
.oLDST_DATA(irq_call_ldst_data),
.iLDST_REQ(iLDST_REQ),
.iLDST_DATA(iLDST_DATA)
);
/****************************************************************************************************
Interrupt Return
****************************************************************************************************/
wire irq_return_ldst_use;
wire irq_return_ldst_req;
wire [1:0] irq_return_ldst_order;
wire irq_return_ldst_rw;
wire [13:0] irq_return_ldst_asid;
wire [1:0] irq_return_ldst_mmumod;
wire [31:0] irq_return_ldst_pdt;
wire [31:0] irq_return_ldst_addr;
wire [31:0] irq_return_ldst_data;
pipeline_control_irq_return IRQ_RETURN(
.iCLOCK(iCLOCK),
.inRESET(inRESET),
.iRESET_SYNC(iRESET_SYNC),
//System Register
.iSYSREG_PPSR(iSYSREG_PPSR),
.iSYSREG_SPR(iSYSREG_SPR),
.iSYSREG_TISR(iSYSREG_TISR),
.iSYSREG_TIDR(iSYSREG_TIDR),
//Request
.iRETURN_START(irq_return_start_condition),
//Finish
.oFINISH(irq_return_finished),
.oFINISH_SPR_VALID(irq_return_spr_valid),
.oFINISH_SPR(irq_return_spr),
//Load Store
.oLDST_USE(irq_return_ldst_use),
.oLDST_REQ(irq_return_ldst_req),
.iLDST_BUSY(iLDST_BUSY),
.oLDST_ORDER(irq_return_ldst_order), //00=Byte Order 01=2Byte Order 10= Word Order 11= None
.oLDST_RW(irq_return_ldst_rw), //0=Read 1=Write
.oLDST_ASID(irq_return_ldst_asid),
.oLDST_MMUMOD(irq_return_ldst_mmumod),
.oLDST_PDT(irq_return_ldst_pdt),
.oLDST_ADDR(irq_return_ldst_addr),
.oLDST_DATA(irq_return_ldst_data),
.iLDST_REQ(iLDST_REQ),
.iLDST_DATA(iLDST_DATA)
);
/****************************************************************************************************
IDT Read & Set
****************************************************************************************************/
wire idt_read_ldst_use;
wire idt_read_ldst_req;
wire [1:0] idt_read_ldst_order;
wire idt_read_ldst_rw;
wire [13:0] idt_read_ldst_asid;
wire [1:0] idt_read_ldst_mmumod;
wire [31:0] idt_read_ldst_pdt;
wire [31:0] idt_read_ldst_addr;
wire [31:0] idt_read_ldst_data;
pipeline_control_idt_read IDT_READ(
.iCLOCK(iCLOCK),
.inRESET(inRESET),
.iRESET_SYNC(iRESET_SYNC),
//System Register
.iSYSREG_IDTR(iSYSREG_IDTR),
//Request
.iRD_START(idt_set_start_condition),
.oRD_FINISH(idt_read_finished),
//Load Store
.oLDST_USE(idt_read_ldst_use),
.oLDST_REQ(idt_read_ldst_req),
.iLDST_BUSY(iLDST_BUSY),
.oLDST_ORDER(idt_read_ldst_order), //00=Byte Order 01=2Byte Order 10= Word Order 11= None
.oLDST_RW(idt_read_ldst_rw), //0=Read 1=Write
.oLDST_ASID(idt_read_ldst_asid),
.oLDST_MMUMOD(idt_read_ldst_mmumod),
.oLDST_PDT(idt_read_ldst_pdt),
.oLDST_ADDR(idt_read_ldst_addr),
.oLDST_DATA(idt_read_ldst_data),
.iLDST_REQ(iLDST_REQ),
.iLDST_DATA(iLDST_DATA),
//IRQ_CONFIG_TABLE
.oIRQ_CONF_TABLE_REQ(oIO_IRQ_CONFIG_TABLE_REQ),
.oIRQ_CONF_TABLE_ENTRY(oIO_IRQ_CONFIG_TABLE_ENTRY),
.oIRQ_CONF_TABLE_FLAG_MASK(oIO_IRQ_CONFIG_TABLE_FLAG_MASK),
.oIRQ_CONF_TABLE_FLAG_VALID(oIO_IRQ_CONFIG_TABLE_FLAG_VALID),
.oIRQ_CONF_TABLE_FLAG_LEVEL(oIO_IRQ_CONFIG_TABLE_FLAG_LEVEL),
//Interrupt Configlation Table
.oICT_REQ(oICT_REQ),
.oICT_ENTRY(oICT_ENTRY),
.oICT_CONF_MASK(oICT_CONF_MASK),
.oICT_CONF_VALID(oICT_CONF_VALID),
.oICT_CONF_LEVEL(oICT_CONF_LEVEL)
);
/****************************************************************************************************
Load Store Pipe
****************************************************************************************************/
reg [1:0] ldst_pipe_order;
reg ldst_pipe_rw;
reg [13:0] ldst_pipe_asid;
reg [1:0] ldst_pipe_mmumod;
reg [31:0] ldst_pipe_pdt;
reg [31:0] ldst_pipe_addr;
reg [31:0] ldst_pipe_data;
always@*begin
if(idt_read_ldst_use)begin
ldst_pipe_order = idt_read_ldst_order;
ldst_pipe_rw = idt_read_ldst_rw;
ldst_pipe_asid = idt_read_ldst_asid;
ldst_pipe_mmumod = idt_read_ldst_mmumod;
ldst_pipe_pdt = idt_read_ldst_pdt;
ldst_pipe_addr = idt_read_ldst_addr;
ldst_pipe_data = idt_read_ldst_data;
end
else if(irq_call_ldst_use)begin
ldst_pipe_order = irq_call_ldst_order;
ldst_pipe_rw = irq_call_ldst_rw;
ldst_pipe_asid = irq_call_ldst_asid;
ldst_pipe_mmumod = irq_call_ldst_mmumod;
ldst_pipe_pdt = irq_call_ldst_pdt;
ldst_pipe_addr = irq_call_ldst_addr;
ldst_pipe_data = irq_call_ldst_data;
end
else if(irq_return_ldst_use)begin
ldst_pipe_order = irq_return_ldst_order;
ldst_pipe_rw = irq_return_ldst_rw;
ldst_pipe_asid = irq_return_ldst_asid;
ldst_pipe_mmumod = irq_return_ldst_mmumod;
ldst_pipe_pdt = irq_return_ldst_pdt;
ldst_pipe_addr = irq_return_ldst_addr;
ldst_pipe_data = irq_return_ldst_addr;
end
else begin
ldst_pipe_order = 2'h0;
ldst_pipe_rw = 1'b0;
ldst_pipe_asid = 14'h0;
ldst_pipe_mmumod = 2'h0;
ldst_pipe_pdt = 32'h0;
ldst_pipe_addr = 32'h0;
ldst_pipe_data = 32'h0;
end
end
assign oLDST_USE = idt_read_ldst_use || irq_call_ldst_use || irq_return_ldst_use;
assign oLDST_REQ = idt_read_ldst_req || irq_call_ldst_req || irq_return_ldst_req;
assign oLDST_ORDER = ldst_pipe_order;
assign oLDST_RW = ldst_pipe_rw;
assign oLDST_ASID = ldst_pipe_asid;
assign oLDST_MMUMOD = ldst_pipe_mmumod;
assign oLDST_PDT = ldst_pipe_pdt;
assign oLDST_ADDR = ldst_pipe_addr;
assign oLDST_DATA = ldst_pipe_data;
/****************************************************************************************************
System - Register Set
****************************************************************************************************/
//PCR(for JUMP)
reg b_sysreg_set_pcr_valid;
reg [31:0] b_sysreg_set_pcr;
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_sysreg_set_pcr_valid <= 1'b0;
b_sysreg_set_pcr <= 32'h0;
end
else if(iRESET_SYNC)begin
b_sysreg_set_pcr_valid <= 1'b0;
b_sysreg_set_pcr <= 32'h0;
end
else begin
if(alu_jump_start_condition || reload_start_condition || idt_set_start_condition)begin
b_sysreg_set_pcr_valid <= 1'b1;
b_sysreg_set_pcr <= iEXE_JUMP_ADDR;
end
else if(alu_jump_irq_call_finish_condition || irq_call_finish_condition)begin
b_sysreg_set_pcr_valid <= 1'b1;
b_sysreg_set_pcr <= irq_call_hundler;
end
else if(irq_return_start_condition)begin
b_sysreg_set_pcr_valid <= 1'b1;
b_sysreg_set_pcr <= iSYSREG_PPCR;
end
else if(b_state == L_PARAM_IDLE)begin
b_sysreg_set_pcr_valid <= 1'b0;
b_sysreg_set_pcr <= 32'h0;
end
end
end
assign oEVENT_SETREG_PCR_SET = b_sysreg_set_pcr_valid;
assign oEVENT_SETREG_PCR = b_sysreg_set_pcr;
//PPCR
reg b_sysreg_set_ppcr_valid;
reg [31:0] b_sysreg_set_ppcr;
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_sysreg_set_ppcr_valid <= 1'b0;
b_sysreg_set_ppcr <= 32'h0;
end
else if(iRESET_SYNC)begin
b_sysreg_set_ppcr_valid <= 1'b0;
b_sysreg_set_ppcr <= 32'h0;
end
else begin
b_sysreg_set_ppcr_valid <= alu_jump_irq_call_finish_condition || irq_call_finish_condition;
b_sysreg_set_ppcr <= /*iEXE_JUMP_ADDR;*/iSYSREG_PCR;
end
end
assign oEVENT_SETREG_PPCR_SET = b_sysreg_set_ppcr_valid;
assign oEVENT_SETREG_PPCR = b_sysreg_set_ppcr; //Always PCR(Dispatch module) is True Date? like after jump true data?
//SPR
reg b_sysreg_set_spr_valid;
reg [31:0] b_sysreg_set_spr;
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_sysreg_set_spr_valid <= 1'b0;
b_sysreg_set_spr <= 32'h0;
end
else if(iRESET_SYNC)begin
b_sysreg_set_spr_valid <= 1'b0;
b_sysreg_set_spr <= 32'h0;
end
else begin
b_sysreg_set_spr_valid <= irq_call_spr_valid || irq_return_spr_valid;
b_sysreg_set_spr <= (irq_call_spr_valid)? irq_call_spr : irq_return_spr;
end
end
assign oEVENT_SETREG_SPR_SET = b_sysreg_set_spr_valid;
assign oEVENT_SETREG_SPR = b_sysreg_set_spr;
//FI0R
reg b_sysreg_set_fi0r_valid;
reg [31:0] b_sysreg_set_fi0r;
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_sysreg_set_fi0r_valid <= 1'b0;
b_sysreg_set_fi0r <= 32'h0;
end
else if(b_state == L_PARAM_IDLE || iRESET_SYNC)begin
b_sysreg_set_fi0r_valid <= 1'b0;
b_sysreg_set_fi0r <= 32'h0;
end
else begin
if(alu_jump_irq_call_start_condition || irq_call_start_condition)begin
b_sysreg_set_fi0r_valid <= 1'b1;
b_sysreg_set_fi0r <= iEXCEPT_IRQ_FI0R;
end
end
end
assign oEVENT_SETREG_FI0R_SET = b_sysreg_set_fi0r_valid;
assign oEVENT_SETREG_FI0R = b_sysreg_set_fi0r;
//FI1R
reg b_sysreg_set_fi1r_valid;
reg [31:0] b_sysreg_set_fi1r;
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_sysreg_set_fi1r_valid <= 1'b0;
b_sysreg_set_fi1r <= 32'h0;
end
else if(b_state == L_PARAM_IDLE || iRESET_SYNC)begin
b_sysreg_set_fi1r_valid <= 1'b0;
b_sysreg_set_fi1r <= 32'h0;
end
else begin
if(alu_jump_irq_call_start_condition || irq_call_start_condition)begin
b_sysreg_set_fi1r_valid <= 1'b1;
b_sysreg_set_fi1r <= iEXCEPT_IRQ_FI1R;
end
end
end
assign oEVENT_SETREG_FI1R_SET = b_sysreg_set_fi1r_valid;
assign oEVENT_SETREG_FI1R = b_sysreg_set_fi1r;
/****************************************************************************************************
Assign
****************************************************************************************************/
assign oEVENT_CACHE_ERASE = 1'b0;
assign oEVENT_TLB_ERASE = 1'b0;
/****************************************************************************************************
Pipeline Control - Timing
****************************************************************************************************/
reg b_event_hold /* synthesis syn_maxfan = 250 */; //Altera QuartusII Synthesis Option : Max fanout
reg b_event_start /* synthesis syn_maxfan = 250 */; //Altera QuartusII Synthesis Option : Max fanout
reg b_event_irq_front2back /* synthesis syn_maxfan = 250 */; //Altera QuartusII Synthesis Option : Max fanout
reg b_event_irq_back2front /* synthesis syn_maxfan = 250 */; //Altera QuartusII Synthesis Option : Max fanout
reg b_event_end /* synthesis syn_maxfan = 250 */; //Altera QuartusII Synthesis Option : Max fanout
assign oEVENT_HOLD = b_event_hold;
assign oEVENT_START = b_event_start;
assign oEVENT_IRQ_FRONT2BACK = b_event_irq_front2back;
assign oEVENT_IRQ_BACK2FRONT = b_event_irq_back2front;
assign oEVENT_END = b_event_end;
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_event_hold <= 1'b0;
end
else if(iRESET_SYNC)begin
b_event_hold <= 1'b0;
end
else begin
case(b_state)
L_PARAM_IDLE:
begin
b_event_hold <= (state != L_PARAM_IDLE);
end
default:
begin
b_event_hold <= b_event_hold;
end
endcase
end
end
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_event_start <= 1'b0;
end
else if(iRESET_SYNC)begin
b_event_start <= 1'b0;
end
else begin
if(b_state == L_PARAM_IDLE)begin
b_event_start = (state != L_PARAM_IDLE);
end
else begin
b_event_start <= 1'b0;
end
end
end
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_event_irq_front2back <= 1'b0;
end
else if(iRESET_SYNC)begin
b_event_irq_front2back <= 1'b0;
end
else begin
case(b_state)
L_PARAM_IDLE:
begin
//Interrupt
if(irq_call_start_condition || alu_jump_irq_call_start_condition)begin
b_event_irq_front2back <= 1'b1;
end
else begin
b_event_irq_front2back <= 1'b0;
end
end
default:
begin
b_event_irq_front2back <= 1'b0;
end
endcase
end
end
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_event_irq_back2front <= 1'b0;
end
else if(iRESET_SYNC)begin
b_event_irq_back2front <= 1'b0;
end
else begin
case(b_state)
L_PARAM_IDLE:
begin
//Interrupt Return Instruction
if(irq_return_start_condition)begin
b_event_irq_back2front <= 1'b1;
end
else begin
b_event_irq_back2front <= 1'b0;
end
end
default:
begin
b_event_irq_back2front <= 1'b0;
end
endcase
end
end
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_event_end <= 1'b0;
end
else if(iRESET_SYNC)begin
b_event_end <= 1'b0;
end
else begin
b_event_end <= alu_jump_irq_call_finish_condition || alu_jump_finish_condition || irq_call_finish_condition || irq_return_finish_condition || idt_set_finish_condition || reload_finish_condition;
end
end
endmodule
`default_nettype wire
|
// Copyright 2017 Google Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
// This is a template file for designs based on the xc9500xl_44_breakout project.
module xc9500(
// Left pins
inout wire p34, // GTS2
inout wire p35,
inout wire p36, // GTS1
inout wire p37,
inout wire p38,
inout wire p39,
inout wire p40,
inout wire p41,
inout wire p42,
inout wire p43, // GCK1
inout wire p44, // GCK2
inout wire p1, // GCK3
inout wire p2,
inout wire p3,
inout wire p5,
inout wire p6,
inout wire p7,
inout wire p8,
// Right pins
inout wire p12,
inout wire p13,
inout wire p14,
inout wire p16,
inout wire p18,
inout wire p19,
inout wire p20,
inout wire p21,
inout wire p22,
inout wire p23,
inout wire p27,
inout wire p28,
inout wire p29,
inout wire p30,
inout wire p31,
inout wire p32,
inout wire p33 // GSR
);
// dummy statement so the template will build; remove this
assign p33 = 1'b1;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DECAP_FUNCTIONAL_V
`define SKY130_FD_SC_HVL__DECAP_FUNCTIONAL_V
/**
* decap: Decoupling capacitance filler.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__decap ();
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DECAP_FUNCTIONAL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLYMETAL6S2S_TB_V
`define SKY130_FD_SC_HS__DLYMETAL6S2S_TB_V
/**
* dlymetal6s2s: 6-inverter delay with output from 2nd stage on
* horizontal route.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__dlymetal6s2s.v"
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VPWR = 1'b0;
#80 A = 1'b1;
#100 VGND = 1'b1;
#120 VPWR = 1'b1;
#140 A = 1'b0;
#160 VGND = 1'b0;
#180 VPWR = 1'b0;
#200 VPWR = 1'b1;
#220 VGND = 1'b1;
#240 A = 1'b1;
#260 VPWR = 1'bx;
#280 VGND = 1'bx;
#300 A = 1'bx;
end
sky130_fd_sc_hs__dlymetal6s2s dut (.A(A), .VPWR(VPWR), .VGND(VGND), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLYMETAL6S2S_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O21BAI_PP_SYMBOL_V
`define SKY130_FD_SC_LP__O21BAI_PP_SYMBOL_V
/**
* o21bai: 2-input OR into first input of 2-input NAND, 2nd iput
* inverted.
*
* Y = !((A1 | A2) & !B1_N)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__o21bai (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1_N,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__O21BAI_PP_SYMBOL_V
|
(** * Basics: Functional Programming in Coq *)
(*
[Admitted] is Coq's "escape hatch" that says accept this definition
without proof. We use it to mark the 'holes' in the development
that should be completed as part of your homework exercises. In
practice, [Admitted] is useful when you're incrementally developing
large proofs. *)
Definition admit {T: Type} : T. Admitted.
(* ###################################################################### *)
(** * Introduction *)
(** The functional programming style brings programming closer to
simple, everyday mathematics: If a procedure or method has no side
effects, then pretty much all you need to understand about it is
how it maps inputs to outputs -- that is, you can think of it as
just a concrete method for computing a mathematical function.
This is one sense of the word "functional" in "functional
programming." The direct connection between programs and simple
mathematical objects supports both formal proofs of correctness
and sound informal reasoning about program behavior.
The other sense in which functional programming is "functional" is
that it emphasizes the use of functions (or methods) as
_first-class_ values -- i.e., values that can be passed as
arguments to other functions, returned as results, stored in data
structures, etc. The recognition that functions can be treated as
data in this way enables a host of useful and powerful idioms.
Other common features of functional languages include _algebraic
data types_ and _pattern matching_, which make it easy to construct
and manipulate rich data structures, and sophisticated
_polymorphic type systems_ that support abstraction and code
reuse. Coq shares all of these features.
The first half of this chapter introduces the most essential
elements of Coq's functional programming language. The second
half introduces some basic _tactics_ that can be used to prove
simple properties of Coq programs.
*)
(* ###################################################################### *)
(** * Enumerated Types *)
(** One unusual aspect of Coq is that its set of built-in
features is _extremely_ small. For example, instead of providing
the usual palette of atomic data types (booleans, integers,
strings, etc.), Coq offers an extremely powerful mechanism for
defining new data types from scratch -- so powerful that all these
familiar types arise as instances.
Naturally, the Coq distribution comes with an extensive standard
library providing definitions of booleans, numbers, and many
common data structures like lists and hash tables. But there is
nothing magic or primitive about these library definitions: they
are ordinary user code. To illustrate this, we will explicitly
recapitulate all the definitions we need in this course, rather
than just getting them implicitly from the library.
To see how this mechanism works, let's start with a very simple
example. *)
(* ###################################################################### *)
(** ** Days of the Week *)
(** The following declaration tells Coq that we are defining
a new set of data values -- a _type_. *)
Inductive day : Type :=
| monday : day
| tuesday : day
| wednesday : day
| thursday : day
| friday : day
| saturday : day
| sunday : day.
(** The type is called [day], and its members are [monday],
[tuesday], etc. The second and following lines of the definition
can be read "[monday] is a [day], [tuesday] is a [day], etc."
Having defined [day], we can write functions that operate on
days. *)
Definition next_weekday (d:day) : day :=
match d with
| monday => tuesday
| tuesday => wednesday
| wednesday => thursday
| thursday => friday
| friday => monday
| saturday => monday
| sunday => monday
end.
(** One thing to note is that the argument and return types of
this function are explicitly declared. Like most functional
programming languages, Coq can often figure out these types for
itself when they are not given explicitly -- i.e., it performs
some _type inference_ -- but we'll always include them to make
reading easier. *)
(** Having defined a function, we should check that it works on
some examples. There are actually three different ways to do this
in Coq.
First, we can use the command [Eval compute] to evaluate a
compound expression involving [next_weekday]. *)
Eval compute in (next_weekday friday).
(* ==> monday : day *)
Eval compute in (next_weekday (next_weekday saturday)).
(* ==> tuesday : day *)
(** If you have a computer handy, this would be an excellent
moment to fire up the Coq interpreter under your favorite IDE --
either CoqIde or Proof General -- and try this for yourself. Load
this file ([Basics.v]) from the book's accompanying Coq sources,
find the above example, submit it to Coq, and observe the
result. *)
(** The keyword [compute] tells Coq precisely how to
evaluate the expression we give it. For the moment, [compute] is
the only one we'll need; later on we'll see some alternatives that
are sometimes useful. *)
(** Second, we can record what we _expect_ the result to be in
the form of a Coq example: *)
Example test_next_weekday:
(next_weekday (next_weekday saturday)) = tuesday.
(** This declaration does two things: it makes an
assertion (that the second weekday after [saturday] is [tuesday]),
and it gives the assertion a name that can be used to refer to it
later. *)
(** Having made the assertion, we can also ask Coq to verify it,
like this: *)
Proof. simpl. reflexivity. Qed.
(** The details are not important for now (we'll come back to
them in a bit), but essentially this can be read as "The assertion
we've just made can be proved by observing that both sides of the
equality evaluate to the same thing, after some simplification." *)
(** Third, we can ask Coq to _extract_, from our [Definition], a
program in some other, more conventional, programming
language (OCaml, Scheme, or Haskell) with a high-performance
compiler. This facility is very interesting, since it gives us a
way to construct _fully certified_ programs in mainstream
languages. Indeed, this is one of the main uses for which Coq was
developed. We'll come back to this topic in later chapters. More
information can also be found in the Coq'Art book by Bertot and
Casteran, as well as the Coq reference manual. *)
(* ###################################################################### *)
(** ** Booleans *)
(** In a similar way, we can define the standard type [bool] of
booleans, with members [true] and [false]. *)
Inductive bool : Type :=
| true : bool
| false : bool.
(** Although we are rolling our own booleans here for the sake
of building up everything from scratch, Coq does, of course,
provide a default implementation of the booleans in its standard
library, together with a multitude of useful functions and
lemmas. (Take a look at [Coq.Init.Datatypes] in the Coq library
documentation if you're interested.) Whenever possible, we'll
name our own definitions and theorems so that they exactly
coincide with the ones in the standard library. *)
(** Functions over booleans can be defined in the same way as
above: *)
Definition negb (b:bool) : bool :=
match b with
| true => false
| false => true
end.
Definition andb (b1:bool) (b2:bool) : bool :=
match b1 with
| true => b2
| false => false
end.
Definition orb (b1:bool) (b2:bool) : bool :=
match b1 with
| true => true
| false => b2
end.
(** The last two illustrate the syntax for multi-argument
function definitions. *)
(** The following four "unit tests" constitute a complete
specification -- a truth table -- for the [orb] function: *)
Example test_orb1: (orb true false) = true.
Proof. reflexivity. Qed.
Example test_orb2: (orb false false) = false.
Proof. reflexivity. Qed.
Example test_orb3: (orb false true) = true.
Proof. reflexivity. Qed.
Example test_orb4: (orb true true) = true.
Proof. reflexivity. Qed.
(** (Note that we've dropped the [simpl] in the proofs. It's not
actually needed because [reflexivity] automatically performs
simplification.) *)
(** _A note on notation_: In .v files, we use square brackets to
delimit fragments of Coq code within comments; this convention,
also used by the [coqdoc] documentation tool, keeps them visually
separate from the surrounding text. In the html version of the
files, these pieces of text appear in a [different font]. *)
(** The values [Admitted] and [admit] can be used to fill
a hole in an incomplete definition or proof. We'll use them in the
following exercises. In general, your job in the exercises is
to replace [admit] or [Admitted] with real definitions or proofs. *)
(** **** Exercise: 1 star (nandb) *)
(** Complete the definition of the following function, then make
sure that the [Example] assertions below can each be verified by
Coq. *)
(** This function should return [true] if either or both of
its inputs are [false]. *)
Definition nandb (b1:bool) (b2:bool) : bool :=
match (b1, b2) with
| (false, _) => true
| (_, false) => true
| (_, _) => false
end.
Example test_nandb2: (nandb false false) = true.
Proof. reflexivity. Qed.
Example test_nandb3: (nandb false true) = true.
Proof. reflexivity. Qed.
Example test_nandb4: (nandb true true) = false.
Proof. reflexivity. Qed.
(** [] *)
(** **** Exercise: 1 star (andb3) *)
(** Do the same for the [andb3] function below. This function should
return [true] when all of its inputs are [true], and [false]
otherwise. *)
Definition andb3 (b1:bool) (b2:bool) (b3:bool) : bool :=
match (b1, b2, b3) with
| (true, true, true) => true
| _ => false
end.
Example test_andb31: (andb3 true true true) = true.
Proof. reflexivity. Qed.
Example test_andb32: (andb3 false true true) = false.
Proof. reflexivity. Qed.
Example test_andb33: (andb3 true false true) = false.
Proof. reflexivity. Qed.
Example test_andb34: (andb3 true true false) = false.
Proof. reflexivity. Qed.
(** [] *)
(* ###################################################################### *)
(** ** Function Types *)
(** The [Check] command causes Coq to print the type of an
expression. For example, the type of [negb true] is [bool]. *)
Check true.
(* ===> true : bool *)
Check (negb true).
(* ===> negb true : bool *)
(** Functions like [negb] itself are also data values, just like
[true] and [false]. Their types are called _function types_, and
they are written with arrows. *)
Check negb.
(* ===> negb : bool -> bool *)
(** The type of [negb], written [bool -> bool] and pronounced
"[bool] arrow [bool]," can be read, "Given an input of type
[bool], this function produces an output of type [bool]."
Similarly, the type of [andb], written [bool -> bool -> bool], can
be read, "Given two inputs, both of type [bool], this function
produces an output of type [bool]." *)
(* ###################################################################### *)
(** ** Numbers *)
(** _Technical digression_: Coq provides a fairly sophisticated
_module system_, to aid in organizing large developments. In this
course we won't need most of its features, but one is useful: If
we enclose a collection of declarations between [Module X] and
[End X] markers, then, in the remainder of the file after the
[End], these definitions will be referred to by names like [X.foo]
instead of just [foo]. Here, we use this feature to introduce the
definition of the type [nat] in an inner module so that it does
not shadow the one from the standard library. *)
Module Playground1.
(** The types we have defined so far are examples of "enumerated
types": their definitions explicitly enumerate a finite set of
elements. A more interesting way of defining a type is to give a
collection of "inductive rules" describing its elements. For
example, we can define the natural numbers as follows: *)
Inductive nat : Type :=
| O : nat
| S : nat -> nat.
(** The clauses of this definition can be read:
- [O] is a natural number (note that this is the letter "[O]," not
the numeral "[0]").
- [S] is a "constructor" that takes a natural number and yields
another one -- that is, if [n] is a natural number, then [S n]
is too.
Let's look at this in a little more detail.
Every inductively defined set ([day], [nat], [bool], etc.) is
actually a set of _expressions_. The definition of [nat] says how
expressions in the set [nat] can be constructed:
- the expression [O] belongs to the set [nat];
- if [n] is an expression belonging to the set [nat], then [S n]
is also an expression belonging to the set [nat]; and
- expressions formed in these two ways are the only ones belonging
to the set [nat].
The same rules apply for our definitions of [day] and [bool]. The
annotations we used for their constructors are analogous to the
one for the [O] constructor, and indicate that each of those
constructors doesn't take any arguments. *)
(** These three conditions are the precise force of the
[Inductive] declaration. They imply that the expression [O], the
expression [S O], the expression [S (S O)], the expression
[S (S (S O))], and so on all belong to the set [nat], while other
expressions like [true], [andb true false], and [S (S false)] do
not.
We can write simple functions that pattern match on natural
numbers just as we did above -- for example, the predecessor
function: *)
Definition pred (n : nat) : nat :=
match n with
| O => O
| S n' => n'
end.
(** The second branch can be read: "if [n] has the form [S n']
for some [n'], then return [n']." *)
End Playground1.
Definition minustwo (n : nat) : nat :=
match n with
| O => O
| S O => O
| S (S n') => n'
end.
(** Because natural numbers are such a pervasive form of data,
Coq provides a tiny bit of built-in magic for parsing and printing
them: ordinary arabic numerals can be used as an alternative to
the "unary" notation defined by the constructors [S] and [O]. Coq
prints numbers in arabic form by default: *)
Check (S (S (S (S O)))).
Eval compute in (minustwo 4).
(** The constructor [S] has the type [nat -> nat], just like the
functions [minustwo] and [pred]: *)
Check S.
Check pred.
Check minustwo.
(** These are all things that can be applied to a number to yield a
number. However, there is a fundamental difference: functions
like [pred] and [minustwo] come with _computation rules_ -- e.g.,
the definition of [pred] says that [pred 2] can be simplified to
[1] -- while the definition of [S] has no such behavior attached.
Although it is like a function in the sense that it can be applied
to an argument, it does not _do_ anything at all! *)
(** For most function definitions over numbers, pure pattern
matching is not enough: we also need recursion. For example, to
check that a number [n] is even, we may need to recursively check
whether [n-2] is even. To write such functions, we use the
keyword [Fixpoint]. *)
Fixpoint evenb (n:nat) : bool :=
match n with
| O => true
| S O => false
| S (S n') => evenb n'
end.
(** We can define [oddb] by a similar [Fixpoint] declaration, but here
is a simpler definition that will be a bit easier to work with: *)
Definition oddb (n:nat) : bool := negb (evenb n).
Example test_oddb1: (oddb (S O)) = true.
Proof. reflexivity. Qed.
Example test_oddb2: (oddb (S (S (S (S O))))) = false.
Proof. reflexivity. Qed.
(** Naturally, we can also define multi-argument functions by
recursion. (Once again, we use a module to avoid polluting the
namespace.) *)
Module Playground2.
Fixpoint plus (n : nat) (m : nat) : nat :=
match n with
| O => m
| S n' => S (plus n' m)
end.
(** Adding three to two now gives us five, as we'd expect. *)
Eval compute in (plus (S (S (S O))) (S (S O))).
(** The simplification that Coq performs to reach this conclusion can
be visualized as follows: *)
(* [plus (S (S (S O))) (S (S O))]
==> [S (plus (S (S O)) (S (S O)))] by the second clause of the [match]
==> [S (S (plus (S O) (S (S O))))] by the second clause of the [match]
==> [S (S (S (plus O (S (S O)))))] by the second clause of the [match]
==> [S (S (S (S (S O))))] by the first clause of the [match]
*)
(** As a notational convenience, if two or more arguments have
the same type, they can be written together. In the following
definition, [(n m : nat)] means just the same as if we had written
[(n : nat) (m : nat)]. *)
Fixpoint mult (n m : nat) : nat :=
match n with
| O => O
| S n' => plus m (mult n' m)
end.
Example test_mult1: (mult 3 3) = 9.
Proof. reflexivity. Qed.
(** You can match two expressions at once by putting a comma
between them: *)
Fixpoint minus (n m:nat) : nat :=
match n, m with
| O , _ => O
| S _ , O => n
| S n', S m' => minus n' m'
end.
(** The _ in the first line is a _wildcard pattern_. Writing _ in a
pattern is the same as writing some variable that doesn't get used
on the right-hand side. This avoids the need to invent a bogus
variable name. *)
End Playground2.
Fixpoint exp (base power : nat) : nat :=
match power with
| O => S O
| S p => mult base (exp base p)
end.
(** **** Exercise: 1 star (factorial) *)
(** Recall the standard factorial function:
<<
factorial(0) = 1
factorial(n) = n * factorial(n-1) (if n>0)
>>
Translate this into Coq. *)
Fixpoint factorial (n:nat) : nat :=
match n with
| O => S O
| S n' => mult (S n') (factorial n')
end.
Example test_factorial1: (factorial 3) = 6.
Proof. reflexivity. Qed.
Example test_factorial2: (factorial 5) = (mult 10 12).
Proof. reflexivity. Qed.
(** [] *)
(** We can make numerical expressions a little easier to read and
write by introducing "notations" for addition, multiplication, and
subtraction. *)
Notation "x + y" := (plus x y)
(at level 50, left associativity)
: nat_scope.
Notation "x - y" := (minus x y)
(at level 50, left associativity)
: nat_scope.
Notation "x * y" := (mult x y)
(at level 40, left associativity)
: nat_scope.
Check ((0 + 1) + 1).
(** (The [level], [associativity], and [nat_scope] annotations
control how these notations are treated by Coq's parser. The
details are not important, but interested readers can refer to the
"More on Notation" subsection in the "Advanced Material" section at
the end of this chapter.) *)
(** Note that these do not change the definitions we've already
made: they are simply instructions to the Coq parser to accept [x
+ y] in place of [plus x y] and, conversely, to the Coq
pretty-printer to display [plus x y] as [x + y]. *)
(** When we say that Coq comes with nothing built-in, we really
mean it: even equality testing for numbers is a user-defined
operation! *)
(** The [beq_nat] function tests [nat]ural numbers for [eq]uality,
yielding a [b]oolean. Note the use of nested [match]es (we could
also have used a simultaneous match, as we did in [minus].) *)
Fixpoint beq_nat (n m : nat) : bool :=
match n with
| O => match m with
| O => true
| S m' => false
end
| S n' => match m with
| O => false
| S m' => beq_nat n' m'
end
end.
(** Similarly, the [ble_nat] function tests [nat]ural numbers for
[l]ess-or-[e]qual, yielding a [b]oolean. *)
Fixpoint ble_nat (n m : nat) : bool :=
match n with
| O => true
| S n' =>
match m with
| O => false
| S m' => ble_nat n' m'
end
end.
Example test_ble_nat1: (ble_nat 2 2) = true.
Proof. reflexivity. Qed.
Example test_ble_nat2: (ble_nat 2 4) = true.
Proof. reflexivity. Qed.
Example test_ble_nat3: (ble_nat 4 2) = false.
Proof. reflexivity. Qed.
(** **** Exercise: 2 stars (blt_nat) *)
(** The [blt_nat] function tests [nat]ural numbers for [l]ess-[t]han,
yielding a [b]oolean. Instead of making up a new [Fixpoint] for
this one, define it in terms of a previously defined function. *)
Definition blt_nat (n m : nat) : bool :=
match m with
| O => false
| (S m') => ble_nat n m'
end.
Example test_blt_nat1: (blt_nat 2 2) = false.
Proof. reflexivity. Qed.
Example test_blt_nat2: (blt_nat 2 4) = true.
Proof. reflexivity. Qed.
Example test_blt_nat3: (blt_nat 4 2) = false.
Proof. reflexivity. Qed.
(** [] *)
(* ###################################################################### *)
(** * Proof by Simplification *)
(** Now that we've defined a few datatypes and functions, let's
turn to the question of how to state and prove properties of their
behavior. Actually, in a sense, we've already started doing this:
each [Example] in the previous sections makes a precise claim
about the behavior of some function on some particular inputs.
The proofs of these claims were always the same: use [reflexivity]
to check that both sides of the [=] simplify to identical values.
(By the way, it will be useful later to know that
[reflexivity] actually does somewhat more simplification than [simpl]
does -- for example, it tries "unfolding" defined terms, replacing them with
their right-hand sides. The reason for this difference is that,
when reflexivity succeeds, the whole goal is finished and we don't
need to look at whatever expanded expressions [reflexivity] has
found; by contrast, [simpl] is used in situations where we may
have to read and understand the new goal, so we would not want it
blindly expanding definitions.)
The same sort of "proof by simplification" can be used to prove
more interesting properties as well. For example, the fact that
[0] is a "neutral element" for [+] on the left can be proved
just by observing that [0 + n] reduces to [n] no matter what
[n] is, a fact that can be read directly off the definition of [plus].*)
Theorem plus_O_n : forall n : nat, 0 + n = n.
Proof.
intros n. reflexivity. Qed.
(** (_Note_: You may notice that the above statement looks
different in the original source file and the final html output. In Coq
files, we write the [forall] universal quantifier using the
"_forall_" reserved identifier. This gets printed as an
upside-down "A", the familiar symbol used in logic.) *)
(** The form of this theorem and proof are almost exactly the
same as the examples above; there are just a few differences.
First, we've used the keyword [Theorem] instead of
[Example]. Indeed, the difference is purely a matter of
style; the keywords [Example] and [Theorem] (and a few others,
including [Lemma], [Fact], and [Remark]) mean exactly the same
thing to Coq.
Secondly, we've added the quantifier [forall n:nat], so that our
theorem talks about _all_ natural numbers [n]. In order to prove
theorems of this form, we need to to be able to reason by
_assuming_ the existence of an arbitrary natural number [n]. This
is achieved in the proof by [intros n], which moves the quantifier
from the goal to a "context" of current assumptions. In effect, we
start the proof by saying "OK, suppose [n] is some arbitrary number."
The keywords [intros], [simpl], and [reflexivity] are examples of
_tactics_. A tactic is a command that is used between [Proof] and
[Qed] to tell Coq how it should check the correctness of some
claim we are making. We will see several more tactics in the rest
of this lecture, and yet more in future lectures. *)
(** We could try to prove a similar theorem about [plus] *)
Theorem plus_n_O : forall n, n + 0 = n.
(** However, unlike the previous proof, [simpl] doesn't do anything in
this case *)
Proof.
simpl. (* Doesn't do anything! *)
Abort.
(** (Can you explain why this happens? Step through both proofs with
Coq and notice how the goal and context change.) *)
Theorem plus_1_l : forall n:nat, 1 + n = S n.
Proof.
intros n. reflexivity. Qed.
Theorem mult_0_l : forall n:nat, 0 * n = 0.
Proof.
intros n. reflexivity. Qed.
(** The [_l] suffix in the names of these theorems is
pronounced "on the left." *)
(* ###################################################################### *)
(** * Proof by Rewriting *)
(** Here is a slightly more interesting theorem: *)
Theorem plus_id_example : forall n m:nat,
n = m ->
n + n = m + m.
(** Instead of making a completely universal claim about all numbers
[n] and [m], this theorem talks about a more specialized property
that only holds when [n = m]. The arrow symbol is pronounced
"implies."
As before, we need to be able to reason by assuming the existence
of some numbers [n] and [m]. We also need to assume the hypothesis
[n = m]. The [intros] tactic will serve to move all three of these
from the goal into assumptions in the current context.
Since [n] and [m] are arbitrary numbers, we can't just use
simplification to prove this theorem. Instead, we prove it by
observing that, if we are assuming [n = m], then we can replace
[n] with [m] in the goal statement and obtain an equality with the
same expression on both sides. The tactic that tells Coq to
perform this replacement is called [rewrite]. *)
Proof.
intros n m. (* move both quantifiers into the context *)
intros H. (* move the hypothesis into the context *)
rewrite -> H. (* Rewrite the goal using the hypothesis *)
reflexivity. Qed.
(** The first line of the proof moves the universally quantified
variables [n] and [m] into the context. The second moves the
hypothesis [n = m] into the context and gives it the (arbitrary)
name [H]. The third tells Coq to rewrite the current goal ([n + n
= m + m]) by replacing the left side of the equality hypothesis
[H] with the right side.
(The arrow symbol in the [rewrite] has nothing to do with
implication: it tells Coq to apply the rewrite from left to right.
To rewrite from right to left, you can use [rewrite <-]. Try
making this change in the above proof and see what difference it
makes in Coq's behavior.) *)
(** **** Exercise: 1 star (plus_id_exercise) *)
(** Remove "[Admitted.]" and fill in the proof. *)
Theorem plus_id_exercise : forall n m o : nat,
n = m -> m = o -> n + m = m + o.
Proof.
intros.
rewrite -> H.
rewrite <- H0.
reflexivity.
Qed.
(** As we've seen in earlier examples, the [Admitted] command
tells Coq that we want to skip trying to prove this theorem and
just accept it as a given. This can be useful for developing
longer proofs, since we can state subsidiary facts that we believe
will be useful for making some larger argument, use [Admitted] to
accept them on faith for the moment, and continue thinking about
the larger argument until we are sure it makes sense; then we can
go back and fill in the proofs we skipped. Be careful, though:
every time you say [Admitted] (or [admit]) you are leaving a door
open for total nonsense to enter Coq's nice, rigorous, formally
checked world! *)
(** We can also use the [rewrite] tactic with a previously proved
theorem instead of a hypothesis from the context. *)
Theorem mult_0_plus : forall n m : nat,
(0 + n) * m = n * m.
Proof.
intros n m.
rewrite -> plus_O_n.
reflexivity. Qed.
(** **** Exercise: 2 stars (mult_S_1) *)
Theorem mult_S_1 : forall n m : nat,
m = S n ->
m * (1 + n) = m * m.
Proof.
intros.
rewrite -> H.
simpl.
reflexivity.
Qed.
(** [] *)
(* ###################################################################### *)
(** * Proof by Case Analysis *)
(** Of course, not everything can be proved by simple
calculation: In general, unknown, hypothetical values (arbitrary
numbers, booleans, lists, etc.) can block the calculation.
For example, if we try to prove the following fact using the
[simpl] tactic as above, we get stuck. *)
Theorem plus_1_neq_0_firsttry : forall n : nat,
beq_nat (n + 1) 0 = false.
Proof.
intros n.
simpl. (* does nothing! *)
Abort.
(** The reason for this is that the definitions of both
[beq_nat] and [+] begin by performing a [match] on their first
argument. But here, the first argument to [+] is the unknown
number [n] and the argument to [beq_nat] is the compound
expression [n + 1]; neither can be simplified.
What we need is to be able to consider the possible forms of [n]
separately. If [n] is [O], then we can calculate the final result
of [beq_nat (n + 1) 0] and check that it is, indeed, [false].
And if [n = S n'] for some [n'], then, although we don't know
exactly what number [n + 1] yields, we can calculate that, at
least, it will begin with one [S], and this is enough to calculate
that, again, [beq_nat (n + 1) 0] will yield [false].
The tactic that tells Coq to consider, separately, the cases where
[n = O] and where [n = S n'] is called [destruct]. *)
Theorem plus_1_neq_0 : forall n : nat,
beq_nat (n + 1) 0 = false.
Proof.
intros n. destruct n as [| n'].
reflexivity.
reflexivity. Qed.
(** The [destruct] generates _two_ subgoals, which we must then
prove, separately, in order to get Coq to accept the theorem as
proved. (No special command is needed for moving from one subgoal
to the other. When the first subgoal has been proved, it just
disappears and we are left with the other "in focus.") In this
proof, each of the subgoals is easily proved by a single use of
[reflexivity].
The annotation "[as [| n']]" is called an _intro pattern_. It
tells Coq what variable names to introduce in each subgoal. In
general, what goes between the square brackets is a _list_ of
lists of names, separated by [|]. Here, the first component is
empty, since the [O] constructor is nullary (it doesn't carry any
data). The second component gives a single name, [n'], since [S]
is a unary constructor.
The [destruct] tactic can be used with any inductively defined
datatype. For example, we use it here to prove that boolean
negation is involutive -- i.e., that negation is its own
inverse. *)
Theorem negb_involutive : forall b : bool,
negb (negb b) = b.
Proof.
intros b. destruct b.
reflexivity.
reflexivity. Qed.
(** Note that the [destruct] here has no [as] clause because
none of the subcases of the [destruct] need to bind any variables,
so there is no need to specify any names. (We could also have
written [as [|]], or [as []].) In fact, we can omit the [as]
clause from _any_ [destruct] and Coq will fill in variable names
automatically. Although this is convenient, it is arguably bad
style, since Coq often makes confusing choices of names when left
to its own devices. *)
(** **** Exercise: 1 star (zero_nbeq_plus_1) *)
Theorem zero_nbeq_plus_1 : forall n : nat,
beq_nat 0 (n + 1) = false.
Proof.
intros. destruct n as [|n].
reflexivity.
reflexivity.
Qed.
(** [] *)
(* ###################################################################### *)
(** * More Exercises *)
(** **** Exercise: 2 stars (boolean_functions) *)
(** Use the tactics you have learned so far to prove the following
theorem about boolean functions. *)
Theorem identity_fn_applied_twice :
forall (f : bool -> bool),
(forall (x : bool), f x = x) ->
forall (b : bool), f (f b) = b.
Proof.
intros.
destruct b.
rewrite -> H.
rewrite -> H.
reflexivity.
rewrite <- H.
rewrite <- H.
reflexivity.
Qed.
(** Now state and prove a theorem [negation_fn_applied_twice] similar
to the previous one but where the second hypothesis says that the
function [f] has the property that [f x = negb x].*)
Theorem negation_fn_applied_twice :
forall (f : bool -> bool),
(forall (x : bool), f x = negb x) ->
forall (b : bool), f (f b) = b.
Proof.
intros.
destruct b.
rewrite -> H.
rewrite -> H.
rewrite negb_involutive.
reflexivity.
rewrite -> H.
rewrite -> H.
rewrite negb_involutive.
reflexivity.
Qed.
(** [] *)
(** **** Exercise: 2 stars (andb_eq_orb) *)
(** Prove the following theorem. (You may want to first prove a
subsidiary lemma or two. Alternatively, remember that you do
not have to introduce all hypotheses at the same time.) *)
Theorem andb_eq_orb :
forall (b c : bool),
(andb b c = orb b c) ->
b = c.
Proof.
intros b c.
destruct b.
destruct c.
reflexivity.
simpl.
intros.
rewrite -> H.
reflexivity.
destruct c.
simpl.
intros.
rewrite -> H.
reflexivity.
simpl.
reflexivity.
Qed.
(** [] *)
(** **** Exercise: 3 stars (binary) *)
(** Consider a different, more efficient representation of natural
numbers using a binary rather than unary system. That is, instead
of saying that each natural number is either zero or the successor
of a natural number, we can say that each binary number is either
- zero,
- twice a binary number, or
- one more than twice a binary number.
(a) First, write an inductive definition of the type [bin]
corresponding to this description of binary numbers.
(Hint: Recall that the definition of [nat] from class,
Inductive nat : Type :=
| O : nat
| S : nat -> nat.
says nothing about what [O] and [S] "mean." It just says "[O] is
in the set called [nat], and if [n] is in the set then so is [S
n]." The interpretation of [O] as zero and [S] as successor/plus
one comes from the way that we _use_ [nat] values, by writing
functions to do things with them, proving things about them, and
so on. Your definition of [bin] should be correspondingly simple;
it is the functions you will write next that will give it
mathematical meaning.)
(b) Next, write an increment function [incr] for binary numbers,
and a function [bin_to_nat] to convert binary numbers to unary numbers.
(c) Write five unit tests [test_bin_incr1], [test_bin_incr2], etc.
for your increment and binary-to-unary functions. Notice that
incrementing a binary number and then converting it to unary
should yield the same result as first converting it to unary and
then incrementing.
*)
Inductive bin : Type :=
| BO : bin
| D : bin -> bin
| A : bin -> bin.
Fixpoint incr (b : bin) : bin :=
match b with
| BO => A BO
| D b' => A b'
| A b' => D (incr b')
end.
Fixpoint bin_to_nat (n : bin) : nat :=
match n with
| BO => 0
| (D n') => mult (S (S 0)) (bin_to_nat n')
| (A n') => S (mult (S (S 0)) (bin_to_nat n'))
end.
Example test_bin_incr1: (bin_to_nat (D (D (A BO)))) = 4.
Proof. reflexivity. Qed.
Example test_bin_incr2: (bin_to_nat (incr (D (D (A BO))))) = 5.
Proof. reflexivity. Qed.
Example test_bin_incr3: 1 + (bin_to_nat (D (D (A BO)))) = 5.
Proof. reflexivity. Qed.
(* FILL IN HERE *)
(** [] *)
(* ###################################################################### *)
(** * More on Notation (Advanced) *)
(** In general, sections marked Advanced are not needed to follow the
rest of the book, except possibly other Advanced sections. On a
first reading, you might want to skim these sections so that you
know what's there for future reference. *)
Notation "x + y" := (plus x y)
(at level 50, left associativity)
: nat_scope.
Notation "x * y" := (mult x y)
(at level 40, left associativity)
: nat_scope.
(** For each notation-symbol in Coq we can specify its _precedence level_
and its _associativity_. The precedence level n can be specified by the
keywords [at level n] and it is helpful to disambiguate
expressions containing different symbols. The associativity is helpful
to disambiguate expressions containing more occurrences of the same
symbol. For example, the parameters specified above for [+] and [*]
say that the expression [1+2*3*4] is a shorthand for the expression
[(1+((2*3)*4))]. Coq uses precedence levels from 0 to 100, and
_left_, _right_, or _no_ associativity.
Each notation-symbol in Coq is also active in a _notation scope_.
Coq tries to guess what scope you mean, so when you write [S(O*O)]
it guesses [nat_scope], but when you write the cartesian
product (tuple) type [bool*bool] it guesses [type_scope].
Occasionally you have to help it out with percent-notation by
writing [(x*y)%nat], and sometimes in Coq's feedback to you it
will use [%nat] to indicate what scope a notation is in.
Notation scopes also apply to numeral notation (3,4,5, etc.), so you
may sometimes see [0%nat] which means [O], or [0%Z] which means the
Integer zero.
*)
(** * [Fixpoint] and Structural Recursion (Advanced) *)
Fixpoint plus' (n : nat) (m : nat) : nat :=
match n with
| O => m
| S n' => S (plus' n' m)
end.
(** When Coq checks this definition, it notes that [plus'] is
"decreasing on 1st argument." What this means is that we are
performing a _structural recursion_ over the argument [n] -- i.e.,
that we make recursive calls only on strictly smaller values of
[n]. This implies that all calls to [plus'] will eventually
terminate. Coq demands that some argument of _every_ [Fixpoint]
definition is "decreasing".
This requirement is a fundamental feature of Coq's design: In
particular, it guarantees that every function that can be defined
in Coq will terminate on all inputs. However, because Coq's
"decreasing analysis" is not very sophisticated, it is sometimes
necessary to write functions in slightly unnatural ways. *)
(** **** Exercise: 2 stars, optional (decreasing) *)
(** To get a concrete sense of this, find a way to write a sensible
[Fixpoint] definition (of a simple function on numbers, say) that
_does_ terminate on all inputs, but that Coq will reject because
of this restriction. *)
(* FILL IN HERE *)
(** [] *)
(** $Date: 2014-12-31 15:31:47 -0500 (Wed, 31 Dec 2014) $ *)
|
`default_nettype none
module fib
#(
parameter N_IN = 7,
parameter N_OUT = 90
)
(
input wire rst_n,
input wire clk,
input wire req,
input wire [N_IN-1:0] n,
output reg ack,
output reg [N_OUT-1:0] result
);
localparam
INIT = 2'b00,
WAIT_REQ = 2'b01,
CALC = 2'b10,
WAIT_REQ_FALL = 2'b11;
reg [1:0] state;
reg [N_IN-1:0] n_reg;
reg [N_OUT-1:0] n_m1;
reg [N_OUT-1:0] n_m2;
reg [N_IN-1:0] cnt;
always @(posedge clk or negedge rst_n) begin
if(~rst_n) begin
state <= INIT;
n_reg <= 0;
n_m1 <= 0;
n_m2 <= 0;
cnt <= 0;
ack <= 0;
result <= 0;
end else begin
case(state)
INIT :begin
state <= #1 WAIT_REQ;
end
WAIT_REQ :begin
if( req) begin
state <= #1 CALC;
n_reg <= #1 n;
n_m1 <= #1 1;
n_m2 <= #1 0;
cnt <= #1 0;
ack <= #1 0;
result <= #1 0;
end
end
CALC :begin
if(cnt == (n_reg-1)) begin
state <= #1 WAIT_REQ_FALL;
result <= #1 n_m1;
end else begin
n_m1 <= #1 n_m1 + n_m2;
n_m2 <= #1 n_m1;
cnt <= #1 cnt + 1;
end
end
WAIT_REQ_FALL:begin
if(~req)
state <= #1 WAIT_REQ;
ack <= #1 1;
end
default :begin
state <= 2'bxx;
end
endcase
end
end
endmodule
`default_nettype wire
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SDFRTP_4_V
`define SKY130_FD_SC_HDLL__SDFRTP_4_V
/**
* sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
* single output.
*
* Verilog wrapper for sdfrtp with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__sdfrtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__sdfrtp_4 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__sdfrtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__sdfrtp_4 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__sdfrtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.RESET_B(RESET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SDFRTP_4_V
|
`timescale 1ns / 1ps
`include "defs.vh"
// In a simulation reset comes from the testbench and clk_to_mem_out has to be connected
// to the SPI memory model in the testbench.
// In hardware, if the FPGA SPI boot memory is used, the memory clock has to be connected
// via STARTUPE2 and end_of_startup can be used as a reset.
module top (
input CLK_100M,
output reg [1:0] status_led,
`ifndef __SYNTHESIS__
output clk_to_mem_out,
input rst,
`endif
inout [3:0] DQio,
output S
);
wire clk_to_mem, clk;
wire end_of_startup;
`ifndef __SYNTHESIS__
assign clk_to_mem_out = clk_to_mem;
`else
wire rst = ~end_of_startup;
`endif
wire [7:0] readout;
wire busy;
wire error;
reg trigger;
reg quad_mode;
reg [7:0] cmd;
reg [(3+256)*8-1:0] data_send;
reg [4:0] state;
clk_for_spi clk_spi_inst (
.clk_in1(CLK_100M), // input clk_in1, 100 MHz
.clk_out1(clk), // output clk_out1, 40 MHz, 0 deg
.clk_out2(clk_to_mem), // output clk_out2, 40 MHz, 180 deg
.reset(rst)
);
STARTUPE2 #(
.PROG_USR("FALSE"),
.SIM_CCLK_FREQ(10.0)
) STARTUPE2_inst (
.CFGCLK(),
.CFGMCLK(),
.EOS(end_of_startup),
.PREQ(),
.CLK(1'b0),
.GSR(1'b0),
.GTS(1'b0),
.KEYCLEARB(1'b0),
.PACK(1'b0),
.USRCCLKO(clk_to_mem),
.USRCCLKTS(1'b0),
.USRDONEO(1'b1),
.USRDONETS(1'b1)
);
qspi_mem_controller mc(
.clk(clk),
.reset(rst),
.S(S),
.DQio(DQio),
.trigger(trigger),
.quad_mode(quad_mode),
.cmd(cmd),
.data_send(data_send),
.readout(readout),
.busy(busy),
.error(error)
);
always @(posedge clk) begin
if (rst) begin
trigger <= 0;
state <= 0;
status_led <= 0;
quad_mode <= 0;
end else begin
case(state)
0: begin
if (!busy)
state <= state+1;
end
1: begin // read memory ID to test the communication
cmd <= `CMD_RDID;
trigger <= 1;
state <= state+1;
end
2: begin
if (trigger)
trigger <= 0;
else if (!busy) begin
$display("mem id: %x", readout);
if (readout == `JEDEC_ID) begin // verify the memory ID read
status_led[1] <= 1;
// enable quad IO
cmd <= `CMD_WRVECR;
data_send[7:0] <= 8'b010_01_111; // quad protocol, hold/accelerator disabled, default drive strength
trigger <= 1;
state <= state+1;
end else begin
status_led[0] <= 1; // memory ID is wrong, error, finish
end
end
end
3: begin
if (trigger) begin
trigger <= 0;
end else if (!busy) begin
quad_mode <= 1;
cmd <= `CMD_WREN;
trigger <= 1;
state <= state+1;
end
end
4: begin
if (trigger)
trigger <= 0;
else if (!busy) begin
cmd <= `CMD_PP;
// 3 bytes of address, then random data
data_send <= {24'hA30000, 2048'h01020304057372f04a39e4d37746533f26c5e18660ac4f512a18faef74279aae5f886745368ff4bdc0505deeb822c1c2a0ac568c4c11b41a9f62f93492cdbdb2a2b57f16c173a319879b8e45baee122f7c5821445ae1ad29f7e2655ac509ca8b450d453638de42e853adb1fbbcc9bac5f7f35b16346431aa0ac6f4865abaa74859cdf4d94c46b40efabe211621515d5dc2d383debab44cdbd57c41b37c34d6466f15cf7e36b481e104bf0367d7f7393fe2e62f489e8c9f6c522ec842789e8b6d251d35cb938664fda91a44de72227f9d748dacc21bc0e5ad5df3458e8f3b023e4e53cb4b266d0fb495aaeae3a56f04f9a1117409992975c4b4a5a88048edee5d};
trigger <= 1;
state <= state+1;
end
end
5: begin
trigger <= 0;
if (!busy && !trigger) begin
status_led[0] <= 1;
status_led[1] <= ~error;
end
end
default:
state <= state+1;
endcase
end
end
endmodule
|
//-----------------------------------------------------------------------------
// (c) Copyright 2012 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
// Filename: axi_traffic_gen_v2_0_7_basic_n_full_top.v
// Version : v1.0
// Description: Top level module for VIVADO.
// Verilog-Standard:verilog-2001
//---------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_traffic_gen_v2_0_7_basic_n_full_top
#(
parameter C_FAMILY = "virtex7" ,
parameter C_BASEADDR = 32'hffffffff,
parameter C_HIGHADDR = 32'h00000000,
parameter C_ZERO_INVALID = 1 ,
parameter C_IS_AXI4 = 1 ,
parameter C_IS_COHERENT = 0 ,
parameter C_IS_AFI = 0 ,
parameter C_NO_EXCL = 0 ,
parameter C_S_AXI_DATA_WIDTH = 32 ,
parameter C_S_AXI_AWUSER_WIDTH = 8 ,
parameter C_S_AXI_ARUSER_WIDTH = 8 ,
parameter C_S_AXI_ID_WIDTH = 1 ,
parameter C_M_AXI_THREAD_ID_WIDTH = 1 ,
parameter C_M_AXI_DATA_WIDTH = 32 ,
parameter C_M_AXI_AWUSER_WIDTH = 8 ,
parameter C_M_AXI_ARUSER_WIDTH = 8 ,
parameter C_ATG_AXI4LITE = 0 ,
parameter C_ATG_BASIC_AXI4 = 0 ,
parameter C_ATG_REPEAT_TYPE = 0 , //0-One-shit,1-Repititive
parameter C_ATG_HLTP_MODE = 0 , //0-Custom,1-High Level Traffic.
parameter C_ATG_STATIC = 0 ,
parameter C_ATG_SLAVE_ONLY = 0 ,
parameter C_ATG_SYSTEM_INIT = 0 ,
parameter C_ATG_STREAMING = 0 ,
parameter C_RAMINIT_CMDRAM0_F = "NONE" ,
parameter C_RAMINIT_CMDRAM1_F = "NONE" ,
parameter C_RAMINIT_CMDRAM2_F = "NONE" ,
parameter C_RAMINIT_CMDRAM3_F = "NONE" ,
parameter C_RAMINIT_SRAM0_F = "NONE" ,
parameter C_RAMINIT_PARAMRAM0_F = "NONE" ,
parameter C_RAMINIT_ADDRRAM0_F = "NONE" ,
parameter C_M_AXI_ADDR_WIDTH = 32 ,
parameter C_REPEAT_COUNT = 254
) (
input s_axi_aclk ,
input s_axi_aresetn ,
input core_global_start ,
input core_global_stop ,
input [C_S_AXI_ID_WIDTH-1:0] awid_s ,
input [31:0] awaddr_s ,
input [7:0] awlen_s ,
input [2:0] awsize_s ,
input [1:0] awburst_s ,
input [0:0] awlock_s ,
input [3:0] awcache_s ,
input [2:0] awprot_s ,
input [3:0] awqos_s ,
input [C_S_AXI_AWUSER_WIDTH-1:0] awuser_s ,
input awvalid_s ,
output awready_s ,
input wlast_s ,
input [C_S_AXI_DATA_WIDTH-1:0] wdata_s ,
input [C_S_AXI_DATA_WIDTH/8-1:0] wstrb_s ,
input wvalid_s ,
output wready_s ,
output [C_S_AXI_ID_WIDTH-1:0] bid_s ,
output [1:0] bresp_s ,
output bvalid_s ,
input bready_s ,
input [C_S_AXI_ID_WIDTH-1:0] arid_s ,
input [31:0] araddr_s ,
input [7:0] arlen_s ,
input [2:0] arsize_s ,
input [1:0] arburst_s ,
input [0:0] arlock_s ,
input [3:0] arcache_s ,
input [2:0] arprot_s ,
input [3:0] arqos_s ,
input [C_S_AXI_ARUSER_WIDTH-1:0] aruser_s ,
input arvalid_s ,
output arready_s ,
output [C_S_AXI_ID_WIDTH-1:0] rid_s ,
output rlast_s ,
output [C_S_AXI_DATA_WIDTH-1:0] rdata_s ,
output [1:0] rresp_s ,
output rvalid_s ,
input rready_s ,
output [C_M_AXI_THREAD_ID_WIDTH-1:0] awid_m ,
output [C_M_AXI_ADDR_WIDTH-1:0] awaddr_m ,
output [7:0] awlen_m ,
output [2:0] awsize_m ,
output [1:0] awburst_m ,
output [0:0] awlock_m ,
output [3:0] awcache_m ,
output [2:0] awprot_m ,
output [3:0] awqos_m ,
output [C_M_AXI_AWUSER_WIDTH-1:0] awuser_m ,
output awvalid_m ,
input awready_m ,
output wlast_m ,
output [C_M_AXI_DATA_WIDTH-1:0] wdata_m ,
output [C_M_AXI_DATA_WIDTH/8-1:0] wstrb_m ,
output wvalid_m ,
input wready_m ,
input [C_M_AXI_THREAD_ID_WIDTH-1:0] bid_m ,
input [1:0] bresp_m ,
input bvalid_m ,
output bready_m ,
output [C_M_AXI_THREAD_ID_WIDTH-1:0] arid_m ,
output [C_M_AXI_ADDR_WIDTH-1:0] araddr_m ,
output [7:0] arlen_m ,
output [2:0] arsize_m ,
output [1:0] arburst_m ,
output [0:0] arlock_m ,
output [3:0] arcache_m ,
output [2:0] arprot_m ,
output [3:0] arqos_m ,
output [C_M_AXI_ARUSER_WIDTH-1:0] aruser_m ,
output arvalid_m ,
input arready_m ,
input [C_M_AXI_THREAD_ID_WIDTH-1:0] rid_m ,
input rlast_m ,
input [C_M_AXI_DATA_WIDTH-1:0] rdata_m ,
input [1:0] rresp_m ,
input rvalid_m ,
output rready_m ,
output irq_out ,
output err_out ,
output [24:0] dbg_out ,
output [2:0] dbg_out_ext ,
input global_test_en_l
);
/* hierarchy structure
slave
|_ slave write
|_ slave read
master
|_ master write
|_ master read
ram
|_ command ram
|_ shared ram (master/slave)
|_ param ram
axi_traffic_gen_v2_0_7_registers and debug modules
|_axi_traffic_gen_v2_0_7_registers
|_axi_traffic_gen_v2_0_7_debug_capture
*/
wire reg1_disallow_excl ;
wire reg1_sgl_slv_wr ;
wire reg1_wrs_block_rds ;
wire [15:0] err_new_slv ;
wire [15:0] wr_reg_decode ;
wire [31:0] wr_reg_data ;
wire [71:0] slv_ex_info0_ff ;
wire [71:0] slv_ex_info1_ff ;
wire slv_ex_new_valid0 ;
wire slv_ex_new_valid1 ;
wire [15:0] ar_agen_addr ;
wire [C_S_AXI_DATA_WIDTH-1:0] slvram_rd_out ;
wire [63:0] sram_rd_data_a ;
wire [10:0] slvram_waddr_ff ;
wire [7:0] slvram_we_ff ;
wire [63:0] slvram_write_data_ff ;
wire [15:0] aw_agen_addr ;
wire aw_agen_valid ;
wire [15:0] cmdram_we ;
wire [63:0] slvram_wr_data ;
wire awfifo_valid ;
wire wfifo_valid ;
wire [71:0] awfifo_out ;
wire [C_S_AXI_DATA_WIDTH*9/8+1-1:0] wfifo_out ;
wire reg1_sgl_slv_rd ;
wire [15:0] rd_reg_decode ;
wire [31:0] rd_reg_data_raw ;
wire slv_ex_valid0_ff ;
wire slv_ex_valid1_ff ;
wire [15:0] ar_agen0_addr ;
wire ar_agen0_valid ;
wire arfifo_valid ;
wire [71:0] arfifo_out ;
wire [127:0] cmd_out_mr_i ;
wire reg0_m_enable_ff ;
wire reg0_loop_en_ff ;
wire [9:0] reg0_mw_ptr_ff ;
wire reg0_m_enable_cmdram_mrw ;
wire reg0_m_enable_cmdram_mrw_ff ;
wire reg0_m_enable_3ff ;
wire mw_done_ff ;
wire b_resp_unexp_ff ;
wire b_resp_bad_ff ;
wire [9:0] reg0_mw_ptr_update ;
wire param_cmdw_delayop_valid ;
wire [23:0] param_cmdw_count ;
wire param_cmdw_repeatfixedop_valid;
wire param_cmdw_disable_submitincr ;
wire [127:0] cmd_out_mw ;
wire cmdram_mw_regslice_id_stable ;
wire [C_M_AXI_DATA_WIDTH-1:0] mram_out ;
wire [15:0] maw_agen_addr ;
wire [8:0] mrd_complete_ptr_ff ;
wire [15:0] Maw_fifow_dbgout ;
wire [9:0] maw_ptr_new_ff ;
wire [9:0] maw_ptr_new_2ff ;
wire maw_fifo_push_ff ;
wire cmdram_mr_regslice_id_stable ;
wire [127:0] cmd_out_mr ;
wire param_cmdr_delayop_valid ;
wire [23:0] param_cmdr_count ;
wire param_cmdr_repeatfixedop_valid;
wire param_cmdr_disable_submitincr ;
wire [10:0] mram_waddr_ff ;
wire [C_M_AXI_DATA_WIDTH/8-1:0] mram_we_ff ;
wire [C_M_AXI_DATA_WIDTH-1:0] mram_write_data_ff ;
wire [9:0] reg0_mr_ptr_ff ;
wire mr_done_ff ;
wire mr_fifo_out_resp_bad ;
wire mr_bad_last_ff ;
wire mr_unexp ;
wire [9:0] reg0_mr_ptr_update ;
wire [8:0] mwr_complete_ptr_ff ;
wire [9:0] mar_ptr_new_ff ;
wire [9:0] mar_ptr_new_2ff ;
wire mar_fifo_push_ff ;
wire [23:0] param_cmdr_submitcnt_ff ;
wire [23:0] param_cmdw_submitcnt_ff ;
wire [127:0] cmd_out_mw_regslice ;
wire [127:0] cmd_out_mr_regslice ;
wire [127:0] cmd_out_mw_regslice_ff ;
wire [127:0] cmd_out_mr_regslice_ff ;
wire rddec6_valid_ff ;
wire [71:0] slv_ex_info1 ;
wire slv_ex_toggle_ff ;
wire maw_fifow_notfull ;
wire [9:0] reg0_mr_ptr ;
wire [9:0] reg0_mw_ptr ;
wire maw_delay_ok_ff ;
wire maw_cnt_do_dec ;
wire maw_fifo_notfull ;
wire [3:0] mawtrk_free ;
wire maw_fifo0_notfull ;
wire maw_fifo1_notfull ;
wire maw_fifo2_notfull ;
wire maw_fifo3_notfull ;
wire maw_block_push_ff ;
wire b_resp_bad ;
wire b_complete_ff ;
wire [9:0] maw_ptr_new ;
wire maw_fifow_push ;
wire mar_complete_doinc ;
wire mar_done ;
wire mr_done ;
wire mw_done ;
wire maw_fifo0_user_disableincr ;
wire maw_disableincr ;
wire maw_disableincr_ff ;
wire [7:0] reg0_rev ;
wire maw_fifo1_pop ;
wire maw_agen_done ;
wire mw_fifo_valid ;
wire mw_fifo_pop ;
wire mw_fifo_notfull ;
wire maw_fifow_pop ;
wire maw_fifow_valid ;
wire maw_done ;
wire maw_valid ;
wire maw_fifo_push ;
wire [8:0] maw_complete_depth ;
wire [8:0] mwr_complete_ptr ;
wire [15:0] maw_complete_next2 ;
wire [15:0] maw_complete_vec_ff ;
wire maw_complete_doinc ;
wire [15:0] maw_complete_inc_exp ;
wire maw_agen_valid ;
wire mar_param_disableincr_ff ;
wire [31:0] addrram_rd_out ;
axi_traffic_gen_v2_0_7_s_w_channel # (
.C_BASEADDR (C_BASEADDR ),
.C_HIGHADDR (C_HIGHADDR ),
.C_S_AXI_ID_WIDTH (C_S_AXI_ID_WIDTH ),
.C_S_AXI_DATA_WIDTH (C_S_AXI_DATA_WIDTH ),
.C_S_AXI_AWUSER_WIDTH(C_S_AXI_AWUSER_WIDTH),
.C_ZERO_INVALID (C_ZERO_INVALID ),
.C_NO_EXCL (C_NO_EXCL ),
.C_ATG_BASIC_AXI4 (C_ATG_BASIC_AXI4 ),
.C_ATG_AXI4LITE (C_ATG_AXI4LITE )
) slv_wr (
.Clk (s_axi_aclk ),
.rst_l (s_axi_aresetn ),
.awid_s (awid_s ),
.awaddr_s (awaddr_s ),
.awlen_s (awlen_s ),
.awsize_s (awsize_s ),
.awburst_s (awburst_s ),
.awlock_s (awlock_s ),
.awcache_s (awcache_s ),
.awprot_s (awprot_s ),
.awqos_s (awqos_s ),
.awuser_s (awuser_s ),
.awvalid_s (awvalid_s ),
.awready_s (awready_s ),
.wlast_s (wlast_s ),
.wdata_s (wdata_s ),
.wstrb_s (wstrb_s ),
.wvalid_s (wvalid_s ),
.wready_s (wready_s ),
.bid_s (bid_s ),
.bresp_s (bresp_s ),
.bvalid_s (bvalid_s ),
.bready_s (bready_s ),
.reg1_disallow_excl (reg1_disallow_excl ),
.reg1_sgl_slv_wr (reg1_sgl_slv_wr ),
.reg1_wrs_block_rds (reg1_wrs_block_rds ),
.err_new_slv (err_new_slv ),
.wr_reg_decode (wr_reg_decode ),
.wr_reg_data (wr_reg_data ),
.slv_ex_info0_ff (slv_ex_info0_ff ),
.slv_ex_valid0_ff (slv_ex_valid0_ff ),
.slv_ex_info1_ff (slv_ex_info1_ff ),
.slv_ex_valid1_ff (slv_ex_valid1_ff ),
.slv_ex_new_valid0 (slv_ex_new_valid0 ),
.slv_ex_new_valid1 (slv_ex_new_valid1 ),
.ar_agen_addr (ar_agen_addr ),
.slvram_rd_out (slvram_rd_out ),
.sram_rd_data_a (sram_rd_data_a ),
.slvram_waddr_ff (slvram_waddr_ff ),
.slvram_we_ff (slvram_we_ff ),
.slvram_write_data_ff (slvram_write_data_ff ),
.aw_agen_addr (aw_agen_addr ),
.aw_agen_valid_out (aw_agen_valid ),
.cmdram_we (cmdram_we ),
.slvram_wr_data (slvram_wr_data ),
.awfifo_valid (awfifo_valid ),
.awfifo_out (awfifo_out ),
.wfifo_valid (wfifo_valid ),
.wfifo_out (wfifo_out )
);
axi_traffic_gen_v2_0_7_s_r_channel #
(
.C_BASEADDR (C_BASEADDR ),
.C_HIGHADDR (C_HIGHADDR ),
.C_ZERO_INVALID (C_ZERO_INVALID ),
.C_NO_EXCL (C_NO_EXCL ),
.C_S_AXI_ID_WIDTH (C_S_AXI_ID_WIDTH ),
.C_S_AXI_ARUSER_WIDTH (C_S_AXI_ARUSER_WIDTH ),
.C_S_AXI_DATA_WIDTH (C_S_AXI_DATA_WIDTH ),
.C_ATG_BASIC_AXI4 (C_ATG_BASIC_AXI4 ),
.C_ATG_AXI4LITE (C_ATG_AXI4LITE )
) slv_rd (
.Clk (s_axi_aclk ),
.rst_l (s_axi_aresetn ),
.arid_s (arid_s ),
.araddr_s (araddr_s ),
.arlen_s (arlen_s ),
.arsize_s (arsize_s ),
.arburst_s (arburst_s ),
.arlock_s (arlock_s ),
.arcache_s (arcache_s ),
.arprot_s (arprot_s ),
.arqos_s (arqos_s ),
.aruser_s (aruser_s ),
.arvalid_s (arvalid_s ),
.arready_s (arready_s ),
.rid_s (rid_s ),
.rlast_s (rlast_s ),
.rdata_s (rdata_s ),
.rresp_s (rresp_s ),
.rvalid_s (rvalid_s ),
.rready_s (rready_s ),
.reg1_sgl_slv_rd (reg1_sgl_slv_rd ),
.rd_reg_decode (rd_reg_decode ),
.rd_reg_data_raw (rd_reg_data_raw ),
.reg1_disallow_excl (reg1_disallow_excl ),
.rddec6_valid_ff (rddec6_valid_ff ),
.slv_ex_info0_ff (slv_ex_info0_ff ),
.slv_ex_valid0_ff (slv_ex_valid0_ff ),
.slv_ex_info1_ff (slv_ex_info1_ff ),
.slv_ex_info1 (slv_ex_info1 ),
.slv_ex_valid1_ff (slv_ex_valid1_ff ),
.slv_ex_toggle_ff (slv_ex_toggle_ff ),
.slv_ex_new_valid0 (slv_ex_new_valid0 ),
.slv_ex_new_valid1 (slv_ex_new_valid1 ),
.ar_agen_addr (ar_agen_addr ),
.slvram_rd_out (slvram_rd_out ),
.ar_agen0_addr (ar_agen0_addr ),
.ar_agen0_valid_out (ar_agen0_valid ),
.addrram_rd_out (addrram_rd_out ),
.arfifo_valid (arfifo_valid ),
.arfifo_out (arfifo_out ),
.cmd_out_mr_i (cmd_out_mr_i )
);
wire extn_param_cmdw_delayop_valid ;
wire [23:0] extn_param_cmdw_count ;
wire extn_param_cmdw_repeatfixedop_valid;
wire extn_param_cmdw_disable_submitincr ;
wire [127:0] extn_cmd_out_mw ;
wire [31:0] extn_cmd_out_mw_ext ;
wire [31:0] cmd_out_mw_ext ;
wire [31:0] prm_out_mw ;
generate if(C_ATG_BASIC_AXI4 == 1) begin : ATG_PARARAM_MW_YES
assign extn_param_cmdw_delayop_valid = 1'b0 ;
assign extn_param_cmdw_count = 24'h0 ;
assign extn_param_cmdw_repeatfixedop_valid= 1'b0 ;
assign extn_param_cmdw_disable_submitincr = 1'b0 ;
assign extn_cmd_out_mw = cmd_out_mw_regslice_ff ;
assign param_cmdr_submitcnt_ff = 24'h0 ;
assign param_cmdw_submitcnt_ff = 24'h0 ;
end
endgenerate
generate if(C_ATG_BASIC_AXI4 == 0) begin : ATG_PARARAM_MW_NO
assign extn_param_cmdw_delayop_valid = param_cmdw_delayop_valid ;
assign extn_param_cmdw_count = param_cmdw_count ;
assign extn_param_cmdw_repeatfixedop_valid= param_cmdw_repeatfixedop_valid;
assign extn_param_cmdw_disable_submitincr = param_cmdw_disable_submitincr ;
assign extn_cmd_out_mw = cmd_out_mw ;
end
endgenerate
axi_traffic_gen_v2_0_7_m_w_channel #(
.C_M_AXI_THREAD_ID_WIDTH (C_M_AXI_THREAD_ID_WIDTH ),
.C_ZERO_INVALID (C_ZERO_INVALID ),
.C_M_AXI_AWUSER_WIDTH (C_M_AXI_AWUSER_WIDTH ),
.C_M_AXI_DATA_WIDTH (C_M_AXI_DATA_WIDTH ),
.C_M_AXI_ADDR_WIDTH (C_M_AXI_ADDR_WIDTH ),
.C_ATG_BASIC_AXI4 (C_ATG_BASIC_AXI4 ),
.C_ATG_AXI4LITE (C_ATG_AXI4LITE )
) mst_wr (
.Clk (s_axi_aclk ),
.rst_l (s_axi_aresetn ),
.awid_m (awid_m ),
.awaddr_m (awaddr_m ),
.awlen_m (awlen_m ),
.awsize_m (awsize_m ),
.awburst_m (awburst_m ),
.awlock_m (awlock_m ),
.awcache_m (awcache_m ),
.awprot_m (awprot_m ),
.awqos_m (awqos_m ),
.awuser_m (awuser_m ),
.awvalid_m (awvalid_m ),
.awready_m (awready_m ),
.wlast_m (wlast_m ),
.wdata_m (wdata_m ),
.wstrb_m (wstrb_m ),
.wvalid_m (wvalid_m ),
.wready_m (wready_m ),
.bid_m (bid_m ),
.bresp_m (bresp_m ),
.bvalid_m (bvalid_m ),
.bready_m (bready_m ),
.reg0_m_enable_ff (reg0_m_enable_ff ),
.reg0_mw_ptr_ff (reg0_mw_ptr_ff ),
.reg0_m_enable_cmdram_mrw (reg0_m_enable_cmdram_mrw ),
.reg0_m_enable_cmdram_mrw_ff (reg0_m_enable_cmdram_mrw_ff ),
.reg0_m_enable_3ff (reg0_m_enable_3ff ),
.reg0_loop_en_ff (reg0_loop_en_ff ),
.mw_done_ff (mw_done_ff ),
.b_resp_unexp_ff (b_resp_unexp_ff ),
.b_resp_bad_ff (b_resp_bad_ff ),
.reg0_mw_ptr_update (reg0_mw_ptr_update ),
.param_cmdw_delayop_valid (extn_param_cmdw_delayop_valid ),
.param_cmdw_count (extn_param_cmdw_count ),
.param_cmdw_repeatfixedop_valid(extn_param_cmdw_repeatfixedop_valid ),
.param_cmdw_disable_submitincr (extn_param_cmdw_disable_submitincr ),
.cmd_out_mw (extn_cmd_out_mw ),
.cmd_out_mw_ext (extn_cmd_out_mw_ext ),
.cmdram_mw_regslice_id_stable (cmdram_mw_regslice_id_stable ),
.mram_out (mram_out ),
.maw_agen_addr (maw_agen_addr ),
.mwr_complete_ptr_ff ( mwr_complete_ptr_ff ),
.mrd_complete_ptr_ff (mrd_complete_ptr_ff ),
.Maw_fifow_dbgout (Maw_fifow_dbgout ),
.maw_ptr_new_ff (maw_ptr_new_ff ),
.maw_ptr_new_2ff (maw_ptr_new_2ff ),
.maw_fifo_push_ff (maw_fifo_push_ff ),
.maw_fifow_notfull ( maw_fifow_notfull ),
.maw_delay_ok_ff ( maw_delay_ok_ff ),
.maw_cnt_do_dec ( maw_cnt_do_dec ),
.maw_fifo_notfull ( maw_fifo_notfull ),
.mawtrk_free ( mawtrk_free ),
.maw_fifo0_notfull ( maw_fifo0_notfull ),
.maw_fifo1_notfull ( maw_fifo1_notfull ),
.maw_fifo2_notfull ( maw_fifo2_notfull ),
.maw_fifo3_notfull ( maw_fifo3_notfull ),
.maw_block_push_ff ( maw_block_push_ff ),
.b_resp_bad ( b_resp_bad ),
.b_complete_ff ( b_complete_ff ),
.maw_ptr_new ( maw_ptr_new ),
.maw_fifow_push ( maw_fifow_push ),
.mw_done ( mw_done ),
.maw_fifo0_user_disableincr ( maw_fifo0_user_disableincr ),
.maw_disableincr ( maw_disableincr ),
.maw_disableincr_ff ( maw_disableincr_ff ),
.maw_fifo1_pop ( maw_fifo1_pop ),
.maw_fifo0_pop ( maw_fifo0_pop ),
.maw_agen_done ( maw_agen_done ),
.mw_fifo_valid ( mw_fifo_valid ),
.mw_fifo_pop ( mw_fifo_pop ),
.mw_fifo_notfull ( mw_fifo_notfull ),
.maw_fifow_pop ( maw_fifow_pop ),
.maw_fifow_valid ( maw_fifow_valid ),
.maw_done ( maw_done ),
.mrd_done ( mr_done ),
.maw_valid ( maw_valid ),
.maw_fifo_push ( maw_fifo_push ),
.maw_depend_ok ( maw_depend_ok ),
.maw_complete_depth (maw_complete_depth ),
.mwr_complete_ptr ( mwr_complete_ptr ),
.maw_complete_next2 ( maw_complete_next2 ),
.maw_complete_vec_ff ( maw_complete_vec_ff ),
.maw_complete_doinc ( maw_complete_doinc ),
.maw_complete_inc_exp ( maw_complete_inc_exp ),
.maw_agen_valid ( maw_agen_valid )
);
wire [127:0] extn_cmd_out_mr ;
wire extn_param_cmdr_delayop_valid ;
wire [23:0] extn_param_cmdr_count ;
wire extn_param_cmdr_repeatfixedop_valid;
wire extn_param_cmdr_disable_submitincr ;
wire [31:0] extn_cmd_out_mr_ext ;
wire [31:0] cmd_out_mr_ext ;
wire [31:0] prm_out_mr ;
generate if(C_ATG_BASIC_AXI4 == 0) begin : ATG_PARARAM_MR_YES
assign extn_cmd_out_mr = cmd_out_mr ;
assign extn_param_cmdr_delayop_valid = param_cmdr_delayop_valid ;
assign extn_param_cmdr_count = param_cmdr_count ;
assign extn_param_cmdr_repeatfixedop_valid= param_cmdr_repeatfixedop_valid ;
assign extn_param_cmdr_disable_submitincr = param_cmdr_disable_submitincr ;
end
endgenerate
generate if(C_ATG_BASIC_AXI4 == 1) begin : ATG_PARARAM_MR_NO
assign extn_cmd_out_mr = cmd_out_mr_regslice_ff;
assign extn_param_cmdr_delayop_valid = 1'b0 ;
assign extn_param_cmdr_count = 24'h0 ;
assign extn_param_cmdr_repeatfixedop_valid= 1'b0 ;
assign extn_param_cmdr_disable_submitincr = 1'b0 ;
end
endgenerate
axi_traffic_gen_v2_0_7_m_r_channel # (
.C_M_AXI_THREAD_ID_WIDTH (C_M_AXI_THREAD_ID_WIDTH ),
.C_M_AXI_ARUSER_WIDTH (C_M_AXI_ARUSER_WIDTH ),
.C_ZERO_INVALID (C_ZERO_INVALID ),
.C_M_AXI_DATA_WIDTH (C_M_AXI_DATA_WIDTH ),
.C_M_AXI_ADDR_WIDTH (C_M_AXI_ADDR_WIDTH ),
.C_ATG_BASIC_AXI4 (C_ATG_BASIC_AXI4 ),
.C_ATG_AXI4LITE (C_ATG_AXI4LITE )
) mst_rd (
.Clk (s_axi_aclk ),
.rst_l (s_axi_aresetn ),
.arid_m ( arid_m ),
.araddr_m ( araddr_m ),
.arlen_m ( arlen_m ),
.arsize_m ( arsize_m ),
.arburst_m ( arburst_m ),
.arlock_m ( arlock_m ),
.arcache_m ( arcache_m ),
.arprot_m ( arprot_m ),
.arqos_m ( arqos_m ),
.aruser_m ( aruser_m ),
.arvalid_m ( arvalid_m ),
.arready_m ( arready_m ),
.rid_m ( rid_m ),
.rlast_m ( rlast_m ),
.rdata_m ( rdata_m ),
.rresp_m ( rresp_m ),
.rvalid_m ( rvalid_m ),
.rready_m ( rready_m ),
.cmdram_mr_regslice_id_stable ( cmdram_mr_regslice_id_stable ),
.cmd_out_mr ( extn_cmd_out_mr ),
.cmd_out_mr_ext ( extn_cmd_out_mr_ext ),
.param_cmdr_delayop_valid ( extn_param_cmdr_delayop_valid ),
.param_cmdr_count ( extn_param_cmdr_count ),
.param_cmdr_repeatfixedop_valid( extn_param_cmdr_repeatfixedop_valid ),
.param_cmdr_disable_submitincr ( extn_param_cmdr_disable_submitincr ),
.mram_waddr_ff ( mram_waddr_ff ),
.mram_we_ff ( mram_we_ff ),
.mram_write_data_ff ( mram_write_data_ff ),
.reg0_m_enable_ff ( reg0_m_enable_ff ),
.reg0_mr_ptr_ff ( reg0_mr_ptr_ff ),
.reg0_m_enable_cmdram_mrw_ff ( reg0_m_enable_cmdram_mrw_ff ),
.reg0_m_enable_cmdram_mrw ( reg0_m_enable_cmdram_mrw ),
.reg0_m_enable_3ff ( reg0_m_enable_3ff ),
.reg0_loop_en_ff ( reg0_loop_en_ff ),
.mr_done_ff ( mr_done_ff ),
.mr_fifo_out_resp_bad ( mr_fifo_out_resp_bad ),
.mr_bad_last_ff ( mr_bad_last_ff ),
.mr_unexp ( mr_unexp ),
.reg0_mr_ptr_update ( reg0_mr_ptr_update ),
.mwr_complete_ptr_ff ( mwr_complete_ptr_ff ),
.mrd_complete_ptr_ff (mrd_complete_ptr_ff ),
.mar_ptr_new_ff ( mar_ptr_new_ff ),
.mar_ptr_new_2ff ( mar_ptr_new_2ff ),
.mar_fifo_push_ff ( mar_fifo_push_ff ),
.mar_complete_doinc ( mar_complete_doinc ),
.mar_done ( mar_done ),
.mr_done ( mr_done ),
.mwr_done ( mw_done ),
.mar_param_disableincr_ff ( mar_param_disableincr_ff ),
.mar_fifo_push ( mar_fifo_push )
);
axi_traffic_gen_v2_0_7_cmdram_wrap # (
.C_FAMILY (C_FAMILY ),
.C_ATG_BASIC_AXI4 (C_ATG_BASIC_AXI4 ),
.C_M_AXI_DATA_WIDTH (C_M_AXI_DATA_WIDTH ),
.C_RAMINIT_CMDRAM0_F (C_RAMINIT_CMDRAM0_F ),
.C_RAMINIT_CMDRAM1_F (C_RAMINIT_CMDRAM1_F ),
.C_RAMINIT_CMDRAM2_F (C_RAMINIT_CMDRAM2_F ),
.C_RAMINIT_CMDRAM3_F (C_RAMINIT_CMDRAM3_F )
) cmd_blk (
.Clk (s_axi_aclk ),
.rst_l (s_axi_aresetn ),
.cmdram_we (cmdram_we ),
.aw_agen_addr (aw_agen_addr ),
.reg0_m_enable_ff (reg0_m_enable_ff ),
.reg0_mw_ptr_update (reg0_mw_ptr_update ),
.reg0_mr_ptr_update (reg0_mr_ptr_update ),
.mar_ptr_new_ff (mar_ptr_new_ff ),
.ar_agen0_addr (ar_agen0_addr ),
.slvram_wr_data (slvram_wr_data ),
.arfifo_valid (arfifo_valid ),
.arfifo_out (arfifo_out ),
.param_cmdr_submitcnt_ff (param_cmdr_submitcnt_ff ),
.param_cmdw_submitcnt_ff (param_cmdw_submitcnt_ff ),
.maw_ptr_new_ff (maw_ptr_new_ff ),
.cmd_out_mr_i (cmd_out_mr_i ),
.cmdram_mr_regslice_id_stable(cmdram_mr_regslice_id_stable ),
.cmd_out_mw_regslice (cmd_out_mw_regslice ),
.cmd_out_mr_regslice (cmd_out_mr_regslice ),
.cmd_out_mw_regslice_ff (cmd_out_mw_regslice_ff ),
.cmd_out_mr_regslice_ff (cmd_out_mr_regslice_ff ),
.cmdram_mw_regslice_id_stable(cmdram_mw_regslice_id_stable )
);
axi_traffic_gen_v2_0_7_sharedram_wrap # (
.C_FAMILY (C_FAMILY ),
.C_S_AXI_DATA_WIDTH (C_S_AXI_DATA_WIDTH ),
.C_M_AXI_DATA_WIDTH (C_M_AXI_DATA_WIDTH ),
.C_RAMINIT_SRAM0_F (C_RAMINIT_SRAM0_F )
) sharedram_blk (
.Clk (s_axi_aclk ),
.rst_l (s_axi_aresetn ),
.mram_waddr_ff (mram_waddr_ff ),
.mram_we_ff (mram_we_ff ),
.mram_write_data_ff (mram_write_data_ff ),
.mram_out (mram_out ),
.maw_agen_addr (maw_agen_addr ),
.slvram_waddr_ff (slvram_waddr_ff ),
.slvram_we_ff (slvram_we_ff ),
.slvram_write_data_ff (slvram_write_data_ff ),
.sram_rd_data_a (sram_rd_data_a ),
.ar_agen_addr (ar_agen_addr )
);
generate if(C_ATG_BASIC_AXI4 == 0 && C_M_AXI_ADDR_WIDTH == 32) begin : ATG_PARARAM_INST_YES
axi_traffic_gen_v2_0_7_paramram_wrap # (
.C_FAMILY (C_FAMILY ),
.C_RAMINIT_PARAMRAM0_F (C_RAMINIT_PARAMRAM0_F ),
.C_S_AXI_DATA_WIDTH (C_S_AXI_DATA_WIDTH ),
.C_M_AXI_DATA_WIDTH (C_M_AXI_DATA_WIDTH ),
.C_M_AXI_ADDR_WIDTH (C_M_AXI_ADDR_WIDTH ),
.C_REPEAT_COUNT (C_REPEAT_COUNT ),
.C_ATG_BASIC_AXI4 (C_ATG_BASIC_AXI4 )
) paramram_blk (
.Clk (s_axi_aclk ),
.rst_l (s_axi_aresetn ),
.awfifo_valid (awfifo_valid ),
.awfifo_out (awfifo_out ),
.wfifo_valid (wfifo_valid ),
.wfifo_out (wfifo_out ),
.cmd_out_mr_regslice (cmd_out_mr_regslice ),
.cmd_out_mr_regslice_ff (cmd_out_mr_regslice_ff ),
.cmd_out_mw_regslice (cmd_out_mw_regslice ),
.cmd_out_mw_regslice_ff (cmd_out_mw_regslice_ff ),
.param_cmdw_submitcnt_ff (param_cmdw_submitcnt_ff ),
.param_cmdr_submitcnt_ff (param_cmdr_submitcnt_ff ),
.cmd_out_mr (cmd_out_mr ),
.mar_fifo_push_ff (mar_fifo_push_ff ),
.mar_ptr_new_ff (mar_ptr_new_ff ),
.mar_ptr_new_2ff (mar_ptr_new_2ff ),
.param_cmdr_delayop_valid (param_cmdr_delayop_valid ),
.param_cmdr_count (param_cmdr_count ),
.param_cmdr_repeatfixedop_valid(param_cmdr_repeatfixedop_valid ),
.param_cmdr_disable_submitincr (param_cmdr_disable_submitincr ),
.cmd_out_mw (cmd_out_mw ),
.maw_fifo_push_ff (maw_fifo_push_ff ),
.maw_ptr_new_ff (maw_ptr_new_ff ),
.maw_ptr_new_2ff (maw_ptr_new_2ff ),
.param_cmdw_delayop_valid (param_cmdw_delayop_valid ),
.param_cmdw_count (param_cmdw_count ),
.param_cmdw_repeatfixedop_valid(param_cmdw_repeatfixedop_valid ),
.param_cmdw_disable_submitincr (param_cmdw_disable_submitincr )
);
end
endgenerate
generate if(C_ATG_BASIC_AXI4 == 1 && C_M_AXI_ADDR_WIDTH > 32) begin : EXT_ADDR_BASIC_INST
assign extn_cmd_out_mw_ext = cmd_out_mw_ext;
assign extn_cmd_out_mr_ext = cmd_out_mr_ext;
end
endgenerate
generate if(C_ATG_BASIC_AXI4 == 0 && C_M_AXI_ADDR_WIDTH > 32) begin : ATG_PARARAM_64_INST_YES
axi_traffic_gen_v2_0_7_paramram_64_wrap # (
.C_FAMILY (C_FAMILY ),
.C_RAMINIT_PARAMRAM0_F (C_RAMINIT_PARAMRAM0_F ),
.C_S_AXI_DATA_WIDTH (C_S_AXI_DATA_WIDTH ),
.C_M_AXI_DATA_WIDTH (C_M_AXI_DATA_WIDTH ),
.C_M_AXI_ADDR_WIDTH (C_M_AXI_ADDR_WIDTH ),
.C_REPEAT_COUNT (C_REPEAT_COUNT ),
.C_ATG_BASIC_AXI4 (C_ATG_BASIC_AXI4 )
) paramram_blk (
.Clk (s_axi_aclk ),
.rst_l (s_axi_aresetn ),
.awfifo_valid (awfifo_valid ),
.awfifo_out (awfifo_out ),
.wfifo_valid (wfifo_valid ),
.wfifo_out (wfifo_out ),
.cmd_out_mr_regslice (cmd_out_mr_regslice ),
.cmd_out_mr_regslice_ff (cmd_out_mr_regslice_ff ),
.cmd_out_mw_regslice (cmd_out_mw_regslice ),
.cmd_out_mw_regslice_ff (cmd_out_mw_regslice_ff ),
.param_cmdw_submitcnt_ff (param_cmdw_submitcnt_ff ),
.param_cmdr_submitcnt_ff (param_cmdr_submitcnt_ff ),
.cmd_out_mr (cmd_out_mr ),
.adr_out_mr (cmd_out_mr_ext ),
.adr_out_mw (cmd_out_mw_ext ),
.prm_out_mr (prm_out_mr ),
.prm_out_mw (prm_out_mw ),
.mar_fifo_push_ff (mar_fifo_push_ff ),
.mar_ptr_new_ff (mar_ptr_new_ff ),
.mar_ptr_new_2ff (mar_ptr_new_2ff ),
.param_cmdr_delayop_valid (param_cmdr_delayop_valid ),
.param_cmdr_count (param_cmdr_count ),
.param_cmdr_repeatfixedop_valid(param_cmdr_repeatfixedop_valid ),
.param_cmdr_disable_submitincr (param_cmdr_disable_submitincr ),
.cmd_out_mw (cmd_out_mw ),
.maw_fifo_push_ff (maw_fifo_push_ff ),
.maw_ptr_new_ff (maw_ptr_new_ff ),
.maw_ptr_new_2ff (maw_ptr_new_2ff ),
.param_cmdw_delayop_valid (param_cmdw_delayop_valid ),
.param_cmdw_count (param_cmdw_count ),
.param_cmdw_repeatfixedop_valid(param_cmdw_repeatfixedop_valid ),
.param_cmdw_disable_submitincr (param_cmdw_disable_submitincr )
);
assign extn_cmd_out_mw_ext = prm_out_mw;
assign extn_cmd_out_mr_ext = prm_out_mr;
end
endgenerate
generate if(C_M_AXI_ADDR_WIDTH > 32) begin : ATG_ADDRRAM_INST_YES
axi_traffic_gen_v2_0_7_addrram_wrap # (
.C_FAMILY (C_FAMILY ),
.C_RAMINIT_ADDRRAM0_F (C_RAMINIT_ADDRRAM0_F ),
.C_S_AXI_DATA_WIDTH (C_S_AXI_DATA_WIDTH ),
.C_M_AXI_DATA_WIDTH (C_M_AXI_DATA_WIDTH ),
.C_M_AXI_ADDR_WIDTH (C_M_AXI_ADDR_WIDTH ),
.C_ATG_BASIC_AXI4 (C_ATG_BASIC_AXI4 )
) addrram_blk (
.Clk (s_axi_aclk ),
.rst_l (s_axi_aresetn ),
.ar_agen_addr (ar_agen0_addr ),
.ar_agen_valid (ar_agen0_valid ),
.aw_agen_addr (aw_agen_addr ),
.aw_agen_valid (aw_agen_valid ),
.wfifo_valid (wfifo_valid ),
.wfifo_out (wfifo_out ),
.rd_ext_addr (addrram_rd_out ),
.mr_ext_addr (cmd_out_mr_ext ),
.mw_ext_addr (cmd_out_mw_ext ),
.mar_ptr_new_ff (mar_ptr_new_ff ),
.maw_ptr_new_ff (maw_ptr_new_ff )
);
end
endgenerate
generate if(C_M_AXI_ADDR_WIDTH == 32) begin : ATG_ADDRRAM_INST_NO
assign extn_cmd_out_mr_ext = 32'h00000000;
assign extn_cmd_out_mw_ext = 32'h00000000;
end
endgenerate
axi_traffic_gen_v2_0_7_registers # (
.C_IS_COHERENT (C_IS_COHERENT ),
.C_IS_AFI (C_IS_AFI ),
.C_M_AXI_DATA_WIDTH (C_M_AXI_DATA_WIDTH ),
.C_IS_AXI4 (C_IS_AXI4 ),
.C_S_AXI_DATA_WIDTH (C_S_AXI_DATA_WIDTH ),
.C_M_AXI_THREAD_ID_WIDTH(C_M_AXI_THREAD_ID_WIDTH),
.C_S_AXI_ID_WIDTH (C_S_AXI_ID_WIDTH ),
.C_ATG_BASIC_AXI4 (C_ATG_BASIC_AXI4 ),
.C_ATG_REPEAT_TYPE (C_ATG_REPEAT_TYPE ),
.C_ATG_HLTP_MODE (C_ATG_HLTP_MODE ),
.C_ATG_STATIC (C_ATG_STATIC ),
.C_ATG_SLAVE_ONLY (C_ATG_SLAVE_ONLY ),
.C_ATG_SYSTEM_INIT (C_ATG_SYSTEM_INIT ),
.C_ATG_STREAMING (C_ATG_STREAMING )
) reg_blk (
.Clk (s_axi_aclk ),
.rst_l (s_axi_aresetn ),
.core_global_start (core_global_start ),
.core_global_stop (core_global_stop ),
.wr_reg_decode (wr_reg_decode ),
.wr_reg_data (wr_reg_data ),
.reg0_mr_ptr_update (reg0_mr_ptr_update ),
.reg0_mw_ptr_update (reg0_mw_ptr_update ),
.mr_done_ff (mr_done_ff ),
.mw_done_ff (mw_done_ff ),
.rddec6_valid_ff (rddec6_valid_ff ),
.err_new_slv (err_new_slv ),
.rd_reg_decode (rd_reg_decode ),
.rd_reg_data_raw (rd_reg_data_raw ),
.slv_ex_info0_ff (slv_ex_info0_ff ),
.slv_ex_info1_ff (slv_ex_info1_ff ),
.slv_ex_info1 (slv_ex_info1 ),
.slv_ex_valid0_ff (slv_ex_valid0_ff ),
.slv_ex_valid1_ff (slv_ex_valid1_ff ),
.slv_ex_toggle_ff (slv_ex_toggle_ff ),
.b_resp_unexp_ff (b_resp_unexp_ff ),
.b_resp_bad_ff (b_resp_bad_ff ),
.mr_unexp (mr_unexp ),
.mr_fifo_out_resp_bad (mr_fifo_out_resp_bad ),
.mr_bad_last_ff (mr_bad_last_ff ),
.reg1_disallow_excl (reg1_disallow_excl ),
.reg1_sgl_slv_wr (reg1_sgl_slv_wr ),
.reg1_wrs_block_rds (reg1_wrs_block_rds ),
.reg1_sgl_slv_rd (reg1_sgl_slv_rd ),
.reg0_mw_ptr_ff (reg0_mw_ptr_ff ),
.reg0_m_enable_cmdram_mrw (reg0_m_enable_cmdram_mrw ),
.reg0_m_enable_cmdram_mrw_ff(reg0_m_enable_cmdram_mrw_ff ),
.reg0_m_enable_ff (reg0_m_enable_ff ),
.reg0_m_enable_3ff (reg0_m_enable_3ff ),
.reg0_loop_en_ff (reg0_loop_en_ff ),
.reg0_mr_ptr_ff (reg0_mr_ptr_ff ),
.err_out (err_out ),
.irq_out (irq_out ),
.reg0_mr_ptr ( reg0_mr_ptr ),
.reg0_mw_ptr ( reg0_mw_ptr ),
.reg0_rev ( reg0_rev )
);
//NOTE:
// global_test_en_l is not used.
assign dbg_out = 24'h0;
assign dbg_out_ext = 3'b000;
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_ad9739a (
// dac interface
dac_clk_in_p,
dac_clk_in_n,
dac_clk_out_p,
dac_clk_out_n,
dac_data_out_a_p,
dac_data_out_a_n,
dac_data_out_b_p,
dac_data_out_b_n,
// dma interface
dac_div_clk,
dac_valid,
dac_enable,
dac_ddata,
dac_dovf,
dac_dunf,
// axi interface
s_axi_aclk,
s_axi_aresetn,
s_axi_awvalid,
s_axi_awaddr,
s_axi_awready,
s_axi_wvalid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wready,
s_axi_bvalid,
s_axi_bresp,
s_axi_bready,
s_axi_arvalid,
s_axi_araddr,
s_axi_arready,
s_axi_rvalid,
s_axi_rdata,
s_axi_rresp,
s_axi_rready);
// parameters
parameter PCORE_ID = 0;
parameter PCORE_DEVICE_TYPE = 0;
parameter PCORE_SERDES_DDR_N = 1;
parameter PCORE_MMCM_BUFIO_N = 1;
parameter PCORE_DAC_DP_DISABLE = 0;
parameter PCORE_IODELAY_GROUP = "dev_if_delay_group";
// dac interface
input dac_clk_in_p;
input dac_clk_in_n;
output dac_clk_out_p;
output dac_clk_out_n;
output [ 13:0] dac_data_out_a_p;
output [ 13:0] dac_data_out_a_n;
output [ 13:0] dac_data_out_b_p;
output [ 13:0] dac_data_out_b_n;
// dma interface
output dac_div_clk;
output dac_valid;
output dac_enable;
input [255:0] dac_ddata;
input dac_dovf;
input dac_dunf;
// axi interface
input s_axi_aclk;
input s_axi_aresetn;
input s_axi_awvalid;
input [ 31:0] s_axi_awaddr;
output s_axi_awready;
input s_axi_wvalid;
input [ 31:0] s_axi_wdata;
input [ 3:0] s_axi_wstrb;
output s_axi_wready;
output s_axi_bvalid;
output [ 1:0] s_axi_bresp;
input s_axi_bready;
input s_axi_arvalid;
input [ 31:0] s_axi_araddr;
output s_axi_arready;
output s_axi_rvalid;
output [ 31:0] s_axi_rdata;
output [ 1:0] s_axi_rresp;
input s_axi_rready;
// internal clocks and resets
wire dac_rst;
wire up_clk;
wire up_rstn;
// internal signals
wire [ 15:0] dac_data_00_s;
wire [ 15:0] dac_data_01_s;
wire [ 15:0] dac_data_02_s;
wire [ 15:0] dac_data_03_s;
wire [ 15:0] dac_data_04_s;
wire [ 15:0] dac_data_05_s;
wire [ 15:0] dac_data_06_s;
wire [ 15:0] dac_data_07_s;
wire [ 15:0] dac_data_08_s;
wire [ 15:0] dac_data_09_s;
wire [ 15:0] dac_data_10_s;
wire [ 15:0] dac_data_11_s;
wire [ 15:0] dac_data_12_s;
wire [ 15:0] dac_data_13_s;
wire [ 15:0] dac_data_14_s;
wire [ 15:0] dac_data_15_s;
wire dac_status_s;
wire up_wreq_s;
wire [ 13:0] up_waddr_s;
wire [ 31:0] up_wdata_s;
wire up_wack_s;
wire up_rreq_s;
wire [ 13:0] up_raddr_s;
wire [ 31:0] up_rdata_s;
wire up_rack_s;
// signal name changes
assign up_clk = s_axi_aclk;
assign up_rstn = s_axi_aresetn;
// device interface
axi_ad9739a_if #(.PCORE_DEVICE_TYPE (PCORE_DEVICE_TYPE)) i_if (
.dac_clk_in_p (dac_clk_in_p),
.dac_clk_in_n (dac_clk_in_n),
.dac_clk_out_p (dac_clk_out_p),
.dac_clk_out_n (dac_clk_out_n),
.dac_data_out_a_p (dac_data_out_a_p),
.dac_data_out_a_n (dac_data_out_a_n),
.dac_data_out_b_p (dac_data_out_b_p),
.dac_data_out_b_n (dac_data_out_b_n),
.dac_rst (dac_rst),
.dac_clk (),
.dac_div_clk (dac_div_clk),
.dac_status (dac_status_s),
.dac_data_00 (dac_data_00_s),
.dac_data_01 (dac_data_01_s),
.dac_data_02 (dac_data_02_s),
.dac_data_03 (dac_data_03_s),
.dac_data_04 (dac_data_04_s),
.dac_data_05 (dac_data_05_s),
.dac_data_06 (dac_data_06_s),
.dac_data_07 (dac_data_07_s),
.dac_data_08 (dac_data_08_s),
.dac_data_09 (dac_data_09_s),
.dac_data_10 (dac_data_10_s),
.dac_data_11 (dac_data_11_s),
.dac_data_12 (dac_data_12_s),
.dac_data_13 (dac_data_13_s),
.dac_data_14 (dac_data_14_s),
.dac_data_15 (dac_data_15_s));
// core
axi_ad9739a_core #(.PCORE_ID(PCORE_ID), .DP_DISABLE(PCORE_DAC_DP_DISABLE)) i_core (
.dac_div_clk (dac_div_clk),
.dac_rst (dac_rst),
.dac_data_00 (dac_data_00_s),
.dac_data_01 (dac_data_01_s),
.dac_data_02 (dac_data_02_s),
.dac_data_03 (dac_data_03_s),
.dac_data_04 (dac_data_04_s),
.dac_data_05 (dac_data_05_s),
.dac_data_06 (dac_data_06_s),
.dac_data_07 (dac_data_07_s),
.dac_data_08 (dac_data_08_s),
.dac_data_09 (dac_data_09_s),
.dac_data_10 (dac_data_10_s),
.dac_data_11 (dac_data_11_s),
.dac_data_12 (dac_data_12_s),
.dac_data_13 (dac_data_13_s),
.dac_data_14 (dac_data_14_s),
.dac_data_15 (dac_data_15_s),
.dac_status (dac_status_s),
.dac_valid (dac_valid),
.dac_enable (dac_enable),
.dac_ddata (dac_ddata),
.dac_dovf (dac_dovf),
.dac_dunf (dac_dunf),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s),
.up_rack (up_rack_s));
// up bus interface
up_axi i_up_axi (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_axi_awvalid (s_axi_awvalid),
.up_axi_awaddr (s_axi_awaddr),
.up_axi_awready (s_axi_awready),
.up_axi_wvalid (s_axi_wvalid),
.up_axi_wdata (s_axi_wdata),
.up_axi_wstrb (s_axi_wstrb),
.up_axi_wready (s_axi_wready),
.up_axi_bvalid (s_axi_bvalid),
.up_axi_bresp (s_axi_bresp),
.up_axi_bready (s_axi_bready),
.up_axi_arvalid (s_axi_arvalid),
.up_axi_araddr (s_axi_araddr),
.up_axi_arready (s_axi_arready),
.up_axi_rvalid (s_axi_rvalid),
.up_axi_rresp (s_axi_rresp),
.up_axi_rdata (s_axi_rdata),
.up_axi_rready (s_axi_rready),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s),
.up_rack (up_rack_s));
endmodule
// ***************************************************************************
// ***************************************************************************
|
module sequence_detector_fsm(data_out, state, reset, data_in, clk);
output data_out;
output reg [2:0] state; // Matching progress.
input reset, data_in, clk;
// For data_out.
parameter FOUND = 1'b1,
NOT_FOUND = 1'b0;
// For state.
parameter S0 = 3'd0,
S1 = 3'd1,
S2 = 3'd2,
S3 = 3'd3,
S4 = 3'd4,
S5 = 3'd5,
S6 = 3'd6;
reg this_data_in;
reg [2:0] next_state;
// Update state.
always @(posedge clk or posedge reset) begin
if (reset) begin
state <= S0;
this_data_in <= 1'b0;
end else begin
state <= next_state;
this_data_in <= data_in;
end
end
// Calculate data_out.
assign data_out = (state == S6 ? FOUND : NOT_FOUND);
// Calculate next state.
always @(state, this_data_in) begin
case (state)
S0: next_state = (this_data_in ? S1 : S0);
S1: next_state = (this_data_in ? S1 : S2);
S2: next_state = (this_data_in ? S3 : S0);
S3: next_state = (this_data_in ? S1 : S4);
S4: next_state = (this_data_in ? S5 : S0);
S5: next_state = (this_data_in ? S6 : S4);
S6: next_state = (this_data_in ? S1 : S2);
default: next_state = S0;
endcase
end
endmodule
|
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