text
stringlengths 938
1.05M
|
|---|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2005 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description : Xilinx Unified Simulation Library Component
// / / Dual Data Rate Output D Flip-Flop
// /___/ /\ Filename : ODDR.v
// \ \ / \
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 03/11/05 - Added LOC parameter, removed GSR ports and initialized outputs.
// 05/29/07 - Added wire declaration for internal signals
// 04/17/08 - CR 468871 Negative SetupHold fix
// 05/12/08 - CR 455447 add XON MSGON property to support async reg
// 12/03/08 - CR 498674 added pulldown on R/S.
// 07/28/09 - CR 527698 According to holistic, CE has to be high for both rise/fall CLK
// - If CE is low on the rising edge, it has an effect of no change in the falling CLK.
// 06/23/10 - CR 566394 Removed extra recrem checks
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 04/13/12 - CR 591320 fixed SU/H checks in OPPOSITE edge mode.
// 10/22/14 - Added #1 to $finish (CR 808642).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module ODDR (Q, C, CE, D1, D2, R, S);
output Q;
input C;
input CE;
input D1;
input D2;
input R;
input S;
parameter DDR_CLK_EDGE = "OPPOSITE_EDGE";
parameter INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_D1_INVERTED = 1'b0;
parameter [0:0] IS_D2_INVERTED = 1'b0;
parameter SRTYPE = "SYNC";
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
parameter MSGON = "TRUE";
parameter XON = "TRUE";
`endif
localparam MODULE_NAME = "ODDR";
pulldown P1 (R);
pulldown P2 (S);
reg q_out = INIT, qd2_posedge_int;
`ifdef XIL_TIMING
reg notifier;
wire notifierx;
`endif
tri0 GSR = glbl.GSR;
wire c_in,delay_c;
wire ce_in,delay_ce;
wire d1_in,delay_d1;
wire d2_in,delay_d2;
wire gsr_in;
wire r_in,delay_r;
wire s_in,delay_s;
assign gsr_in = GSR;
assign Q = q_out;
`ifdef XIL_TIMING
wire nr, ns, ngsr;
wire ce_c_enable, d_c_enable, r_c_enable, s_c_enable;
wire ce_c_enable1, d1_c_enable1, d2_c_enable1, d2_c_enable2, r_c_enable1, s_c_enable1;
not (nr, R);
not (ns, S);
not (ngsr, GSR);
and (ce_c_enable, ngsr, nr, ns);
and (d_c_enable, ngsr, nr, ns, CE);
and (s_c_enable, ngsr, nr);
assign notifierx = (XON == "FALSE") ? 1'bx : notifier;
assign ce_c_enable1 = (MSGON =="FALSE") ? 1'b0 : ce_c_enable;
assign d1_c_enable1 = (MSGON =="FALSE") ? 1'b0 : d_c_enable;
assign d2_c_enable1 = ((MSGON =="FALSE") && (DDR_CLK_EDGE == "OPPOSITE_EDGE")) ? 1'b0 : d_c_enable; // SAME_EDGE case, D2 to posedge C
assign d2_c_enable2 = ((MSGON =="FALSE") && (DDR_CLK_EDGE == "SAME_EDGE")) ? 1'b0 : d_c_enable; // OPPOSITE_EDGE case, D2 to negedge C
assign r_c_enable1 = (MSGON =="FALSE") ? 1'b0 : ngsr;
assign s_c_enable1 = (MSGON =="FALSE") ? 1'b0 : s_c_enable;
`endif
initial begin
if ((INIT != 0) && (INIT != 1)) begin
$display("Attribute Syntax Error : The attribute INIT on %s instance %m is set to %d. Legal values for this attribute are 0 or 1.", MODULE_NAME, INIT);
#1 $finish;
end
if ((DDR_CLK_EDGE != "OPPOSITE_EDGE") && (DDR_CLK_EDGE != "SAME_EDGE")) begin
$display("Attribute Syntax Error : The attribute DDR_CLK_EDGE on %s instance %m is set to %s. Legal values for this attribute are OPPOSITE_EDGE or SAME_EDGE.", MODULE_NAME, DDR_CLK_EDGE);
#1 $finish;
end
if ((SRTYPE != "ASYNC") && (SRTYPE != "SYNC")) begin
$display("Attribute Syntax Error : The attribute SRTYPE on %s instance %m is set to %s. Legal values for this attribute are ASYNC or SYNC.", MODULE_NAME, SRTYPE);
#1 $finish;
end
end // initial begin
always @(gsr_in or r_in or s_in) begin
if (gsr_in == 1'b1) begin
assign q_out = INIT;
assign qd2_posedge_int = INIT;
end
else if (gsr_in == 1'b0) begin
if (r_in == 1'b1 && SRTYPE == "ASYNC") begin
assign q_out = 1'b0;
assign qd2_posedge_int = 1'b0;
end
else if (r_in == 1'b0 && s_in == 1'b1 && SRTYPE == "ASYNC") begin
assign q_out = 1'b1;
assign qd2_posedge_int = 1'b1;
end
else if ((r_in == 1'b1 || s_in == 1'b1) && SRTYPE == "SYNC") begin
deassign q_out;
deassign qd2_posedge_int;
end
else if (r_in == 1'b0 && s_in == 1'b0) begin
deassign q_out;
deassign qd2_posedge_int;
end
end // if (gsr_in == 1'b0)
end // always @ (gsr_in or r_in or s_in)
always @(posedge c_in) begin
if (r_in == 1'b1) begin
q_out <= 1'b0;
qd2_posedge_int <= 1'b0;
end
else if (r_in == 1'b0 && s_in == 1'b1) begin
q_out <= 1'b1;
qd2_posedge_int <= 1'b1;
end
else if (ce_in == 1'b1 && r_in == 1'b0 && s_in == 1'b0) begin
q_out <= d1_in;
qd2_posedge_int <= d2_in;
end
// CR 527698
else if (ce_in == 1'b0 && r_in == 1'b0 && s_in == 1'b0) begin
qd2_posedge_int <= q_out;
end
end // always @ (posedge c_in)
always @(negedge c_in) begin
if (r_in == 1'b1)
q_out <= 1'b0;
else if (r_in == 1'b0 && s_in == 1'b1)
q_out <= 1'b1;
else if (ce_in == 1'b1 && r_in == 1'b0 && s_in == 1'b0) begin
if (DDR_CLK_EDGE == "SAME_EDGE")
q_out <= qd2_posedge_int;
else if (DDR_CLK_EDGE == "OPPOSITE_EDGE")
q_out <= d2_in;
end
end // always @ (negedge c_in)
`ifndef XIL_TIMING
assign delay_c = C;
assign delay_ce = CE;
assign delay_d1 = D1;
assign delay_d2 = D2;
assign delay_r = R;
assign delay_s = S;
`endif
assign c_in = IS_C_INVERTED ^ delay_c;
assign ce_in = delay_ce;
assign d1_in = IS_D1_INVERTED ^ delay_d1;
assign d2_in = IS_D2_INVERTED ^ delay_d2;
assign r_in = delay_r;
assign s_in = delay_s;
//*** Timing Checks Start here
`ifdef XIL_TIMING
wire c_en_n;
wire c_en_p;
wire ce_c_enable1_n,d1_c_enable1_n,d2_c_enable2_n,r_c_enable1_n,s_c_enable1_n;
wire ce_c_enable1_p,d1_c_enable1_p,d2_c_enable2_p,r_c_enable1_p,s_c_enable1_p;
assign c_en_n = IS_C_INVERTED;
assign c_en_p = ~IS_C_INVERTED;
assign ce_c_enable1_n = ce_c_enable1 && c_en_n;
assign ce_c_enable1_p = ce_c_enable1 && c_en_p;
assign d1_c_enable1_n = d1_c_enable1 && c_en_n;
assign d1_c_enable1_p = d1_c_enable1 && c_en_p;
assign d2_c_enable2_n = d2_c_enable2 && c_en_n;
assign d2_c_enable2_p = d2_c_enable2 && c_en_p;
assign r_c_enable1_n = r_c_enable1 && c_en_n;
assign r_c_enable1_p = r_c_enable1 && c_en_p;
assign s_c_enable1_p = s_c_enable1 && c_en_p;
assign s_c_enable1_n = s_c_enable1 && c_en_n;
always @(notifierx) begin
q_out <= 1'bx;
end
`endif
specify
(C => Q) = (100:100:100, 100:100:100);
(posedge R => (Q +: 0)) = (0:0:0, 0:0:0);
(posedge S => (Q +: 0)) = (0:0:0, 0:0:0);
`ifdef XIL_TIMING
(R => Q) = (0:0:0, 0:0:0);
(S => Q) = (0:0:0, 0:0:0);
$period (negedge C, 0:0:0, notifier);
$period (posedge C, 0:0:0, notifier);
$recrem (negedge R, negedge C, 0:0:0, 0:0:0, notifier,c_en_n,c_en_n);
$recrem (negedge R, posedge C, 0:0:0, 0:0:0, notifier,c_en_p,c_en_p);
$recrem (negedge S, negedge C, 0:0:0, 0:0:0, notifier,c_en_n,c_en_n);
$recrem (negedge S, posedge C, 0:0:0, 0:0:0, notifier,c_en_p,c_en_p);
$recrem ( posedge R, negedge C, 0:0:0, 0:0:0, notifier,c_en_n,c_en_n);
$recrem ( posedge R, posedge C, 0:0:0, 0:0:0, notifier,c_en_p,c_en_p);
$recrem ( posedge S, negedge C, 0:0:0, 0:0:0, notifier,c_en_n,c_en_n);
$recrem ( posedge S, posedge C, 0:0:0, 0:0:0, notifier,c_en_p,c_en_p);
$setuphold (negedge C, negedge CE &&& (ce_c_enable1_n!=0), 0:0:0, 0:0:0, notifier, , , delay_c, delay_ce);
$setuphold (negedge C, negedge D1 &&& (d1_c_enable1_n!=0), 0:0:0, 0:0:0, notifier, , , delay_c, delay_d1);
$setuphold (negedge C, negedge D2 &&& (d2_c_enable2_n!=0), 0:0:0, 0:0:0, notifier, , , delay_c, delay_d2);
$setuphold (negedge C, negedge R &&& (r_c_enable1_n!=0), 0:0:0, 0:0:0, notifier, , , delay_c, delay_r);
$setuphold (negedge C, negedge S &&& (r_c_enable1_n!=0), 0:0:0, 0:0:0, notifier, , , delay_c, delay_s);
$setuphold (negedge C, posedge CE &&& (ce_c_enable1_n!=0), 0:0:0, 0:0:0, notifier, , , delay_c, delay_ce);
$setuphold (negedge C, posedge D1 &&& (d1_c_enable1_n!=0), 0:0:0, 0:0:0, notifier, , , delay_c, delay_d1);
$setuphold (negedge C, posedge D2 &&& (d2_c_enable2_n!=0), 0:0:0, 0:0:0, notifier, , , delay_c, delay_d2);
$setuphold (negedge C, posedge R &&& (r_c_enable1_n!=0), 0:0:0, 0:0:0, notifier, , , delay_c, delay_r);
$setuphold (negedge C, posedge S &&& (r_c_enable1_n!=0), 0:0:0, 0:0:0, notifier, , , delay_c, delay_s);
$setuphold (posedge C, negedge CE &&& (ce_c_enable1_p!=0), 0:0:0, 0:0:0, notifier, , , delay_c, delay_ce);
$setuphold (posedge C, negedge D1 &&& (d1_c_enable1_p!=0), 0:0:0, 0:0:0, notifier, , , delay_c, delay_d1);
$setuphold (posedge C, negedge D2 &&& (d2_c_enable2_p!=0), 0:0:0, 0:0:0, notifier, , , delay_c, delay_d2);
$setuphold (posedge C, negedge R &&& (r_c_enable1_p!=0), 0:0:0, 0:0:0, notifier, , , delay_c, delay_r);
$setuphold (posedge C, negedge S &&& (r_c_enable1_p!=0), 0:0:0, 0:0:0, notifier, , , delay_c, delay_s);
$setuphold (posedge C, posedge CE &&& (ce_c_enable1_p!=0), 0:0:0, 0:0:0, notifier, , , delay_c, delay_ce);
$setuphold (posedge C, posedge D1 &&& (d1_c_enable1_p!=0), 0:0:0, 0:0:0, notifier, , , delay_c, delay_d1);
$setuphold (posedge C, posedge D2 &&& (d2_c_enable2_p!=0), 0:0:0, 0:0:0, notifier, , , delay_c, delay_d2);
$setuphold (posedge C, posedge R &&& (r_c_enable1_p!=0), 0:0:0, 0:0:0, notifier, , , delay_c, delay_r);
$setuphold (posedge C, posedge S &&& (r_c_enable1_p!=0), 0:0:0, 0:0:0, notifier, , , delay_c, delay_s);
$width (negedge C, 0:0:0, 0, notifier);
$width (negedge R, 0:0:0, 0, notifier);
$width (negedge S, 0:0:0, 0, notifier);
$width (posedge C, 0:0:0, 0, notifier);
$width (posedge R, 0:0:0, 0, notifier);
$width (posedge S, 0:0:0, 0, notifier);
`endif
specparam PATHPULSE$ = 0;
endspecify
endmodule // ODDR
`endcelldefine
|
// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: raminout2.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module raminout2 (
address_a,
address_b,
clock,
data_a,
data_b,
wren_a,
wren_b,
q_a,
q_b);
input [9:0] address_a;
input [9:0] address_b;
input clock;
input [31:0] data_a;
input [31:0] data_b;
input wren_a;
input wren_b;
output [31:0] q_a;
output [31:0] q_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri0 wren_a;
tri0 wren_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [31:0] sub_wire0;
wire [31:0] sub_wire1;
wire [31:0] q_a = sub_wire0[31:0];
wire [31:0] q_b = sub_wire1[31:0];
altsyncram altsyncram_component (
.clock0 (clock),
.wren_a (wren_a),
.address_b (address_b),
.data_b (data_b),
.wren_b (wren_b),
.address_a (address_a),
.data_a (data_a),
.q_a (sub_wire0),
.q_b (sub_wire1),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.eccstatus (),
.rden_a (1'b1),
.rden_b (1'b1));
defparam
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.indata_reg_b = "CLOCK0",
altsyncram_component.init_file = "./MIF/memtest.mif",
altsyncram_component.intended_device_family = "Cyclone II",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 1024,
altsyncram_component.numwords_b = 1024,
altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.outdata_reg_b = "CLOCK0",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.widthad_a = 10,
altsyncram_component.widthad_b = 10,
altsyncram_component.width_a = 32,
altsyncram_component.width_b = 32,
altsyncram_component.width_byteena_a = 1,
altsyncram_component.width_byteena_b = 1,
altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "32768"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "./MIF/memtest.mif"
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: REGrren NUMERIC "0"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "32"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: INIT_FILE STRING "./MIF/memtest.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "1024"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "10"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: USED_PORT: address_a 0 0 10 0 INPUT NODEFVAL "address_a[9..0]"
// Retrieval info: USED_PORT: address_b 0 0 10 0 INPUT NODEFVAL "address_b[9..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data_a 0 0 32 0 INPUT NODEFVAL "data_a[31..0]"
// Retrieval info: USED_PORT: data_b 0 0 32 0 INPUT NODEFVAL "data_b[31..0]"
// Retrieval info: USED_PORT: q_a 0 0 32 0 OUTPUT NODEFVAL "q_a[31..0]"
// Retrieval info: USED_PORT: q_b 0 0 32 0 OUTPUT NODEFVAL "q_b[31..0]"
// Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a"
// Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b"
// Retrieval info: CONNECT: @address_a 0 0 10 0 address_a 0 0 10 0
// Retrieval info: CONNECT: @address_b 0 0 10 0 address_b 0 0 10 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 32 0 data_a 0 0 32 0
// Retrieval info: CONNECT: @data_b 0 0 32 0 data_b 0 0 32 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
// Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
// Retrieval info: CONNECT: q_a 0 0 32 0 @q_a 0 0 32 0
// Retrieval info: CONNECT: q_b 0 0 32 0 @q_b 0 0 32 0
// Retrieval info: GEN_FILE: TYPE_NORMAL raminout2.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL raminout2.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL raminout2.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL raminout2.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL raminout2_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL raminout2_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
module testbench ();
parameter ROM_FILE = "DivDivDiv.x";
reg [31:0] addr_write;
reg [31:0] din;
reg enable;
reg rw_write;
reg [2:0] access_size;
wire stall;
reg test_mode;
// General
reg clk;
reg [4:0] stall_count = 0;
reg [4:0] init_dst;
reg [31:0] init_dval;
reg init_rf_we;
// Bypass
wire [31:0] aluSrc1Bypass;
wire [31:0] aluSrc2Bypass;
wire [31:0] dmemDataBypass;
// Memory
wire [31:0] addr;
wire [31:0] mem_dout;
wire mem_busy;
wire [2:0] mem_access_size;
wire rw;
wire mem_enable;
// Fetch
wire [31:0] fetch_pc;
wire fetch_rw;
wire [2:0] fetch_access_size;
wire fetch_enable;
wire fetch_j;
// Decode
wire [5:0] decode_instbits;
wire [5:0] decode_src1;
wire [5:0] decode_src2;
wire [4:0] decode_dst;
wire [15:0] decode_imm;
wire [4:0] decode_funct;
wire [25:0] decode_addr;
wire decode_b_ctrl;
wire [2:0] decode_dmem_func;
wire [2:0] decode_wb_func;
wire [1:0] decode_j;
reg [31:0] decode_pc;
reg [31:0] decode_isn;
// Reg file
wire rf_we;
wire [31:0] rf_dval;
wire [4:0] rf_d;
wire [31:0] rf_s1val;
wire [31:0] rf_s2val;
// ALU
reg [31:0] alu_pc;
reg [31:0] alu_s1val;
reg [31:0] alu_s2val;
reg [4:0] alu_funct;
reg [15:0] alu_imm;
reg [25:0] alu_addr;
reg [2:0] alu_dmem_func;
reg [2:0] alu_wb_func;
reg [4:0] alu_dst;
reg [4:0] alu_src1;
reg [4:0] alu_src2;
wire [31:0] alu_res;
reg [31:0] alu_isn;
reg alu_b_ctrl;
reg [1:0] alu_j;
wire [31:0] alu_a;
wire [31:0] alu_b;
wire [31:0] alu_br_tgt;
wire [31:0] alu_sx;
wire alu_z;
wire [31:0] alu_j_tgt;
assign alu_a = aluSrc1Bypass;
assign alu_br_tgt = (alu_pc + 4) + (alu_sx << 2);
assign alu_sx = {{16{alu_imm[15]}}, {alu_imm[15:0]}};
assign alu_j_tgt = (alu_j == 1) ? ((alu_pc & 32'hf000_0000) | (alu_addr << 2)): alu_s2val;
// Mux the sign-extension and register file branches for the ALU B input
assign alu_b = (alu_b_ctrl == 1 ? alu_sx : aluSrc2Bypass);
// DATA
wire [31:0] data_addr;
wire [31:0] data_din;
wire [31:0] data_dout;
wire data_busy;
wire [2:0] data_access_size;
wire data_rw;
wire data_enable;
reg [31:0] data_pc;
reg [4:0] data_dst;
reg [31:0] data_res;
reg [31:0] data_s2;
reg [4:0] data_src2_reg;
reg [31:0] data_isn;
reg [31:0] data_br_tgt;
reg [2:0] data_mem_func; // Bit 0 = enable / !disable, Bit 1 = w / !r, Bit 2 = byte / !word
reg [2:0] data_wb_func;
assign data_rw = data_mem_func[1] ? 1 : 0;
assign data_access_size = data_wb_func[2] ? 'b101 : data_mem_func[2] ? 3'b100 : 3'b000;
assign data_enable = data_mem_func[0] ? 1 : 0;
assign data_din = dmemDataBypass; // Data value = Source 2 operand from ALU stage
assign data_addr = data_res; // Data address == ALU result
// Writeback
reg [4:0] write_dst;
wire [31:0] write_dval;
reg [31:0] write_res;
wire [31:0] write_dout;
wire write_rf_we;
reg [2:0] write_func;
assign write_dval = write_func[1] ? write_res : write_dout;
assign write_rf_we = write_func[0];
assign write_dout = data_dout;
// Bypass
// Bypass ALU input if the data memory stage has more recent data
// Note we don't have to check what the data memory is doing at this point since we will stall if the data memory is doing something
assign aluSrc1Bypass = (alu_src1 == data_dst && data_dst != 0 && data_mem_func[0] == 0) ? data_res : (alu_src1 == data_dst && data_dst != 0 && data_mem_func[0] == 1) ? data_dout : (alu_src1 == write_dst && write_dst != 0 ? write_dval : alu_s1val);
assign aluSrc2Bypass = (alu_src2 == data_dst && data_dst != 0 && data_mem_func[0] == 0) ? data_res : (alu_src2 == data_dst && data_dst != 0 && data_mem_func[0] == 1) ? data_dout : (alu_src2 == write_dst && write_dst != 0 ? write_dval : alu_s2val);
assign dmemDataBypass = (data_src2_reg == write_dst && write_dst != 0) ? write_dval : data_s2;
mips_memory2 #(ROM_FILE) test_memory(.clk(clk),
.addr(addr),
.din(din),
.dout(mem_dout),
.access_size(mem_access_size),
.rw(rw),
.busy(mem_busy),
.enable(mem_enable));
fetch fetch_unit(.clk(clk),
.busy(mem_busy),
.stall(stall),
.pc(fetch_pc),
.rw(fetch_rw),
.access_size(fetch_access_size),
.enable(fetch_enable),
.j_addr(alu_j_tgt),
.jump(fetch_j),
.br_addr(alu_br_tgt),
.branch(alu_z));
decode decode_unit(.clk(clk),
.insn(decode_isn),
.pc(decode_pc),
.instbits(decode_instbits),
.imm(decode_imm),
.funct(decode_funct),
.addr(decode_addr),
.src1(decode_src1),
.src2(decode_src2),
.dst(decode_dst),
.b_ctrl(decode_b_ctrl),
.dmem_func(decode_dmem_func),
.wb_func(decode_wb_func),
.j(decode_j));
register_file reg_file(.clk(clk),
.we(rf_we),
.dval(rf_dval),
.s1(decode_src1),
.s2(decode_src2),
.d(rf_d),
.s1val(rf_s1val),
.s2val(rf_s2val),
.pc(decode_pc));
alu mips_alu(.a_input(alu_a),
.b_input(alu_b),
.funct(alu_funct),
.res(alu_res),
.z(alu_z));
data_memory2 #(ROM_FILE) data_memory(.clk(clk),
.addr(data_addr),
.din(data_din),
.dout(data_dout),
.access_size(data_access_size),
.rw(data_rw),
.busy(data_busy),
.enable(data_enable));
assign addr = fetch_pc;
assign mem_access_size = fetch_access_size;
assign rw = fetch_rw;
assign mem_enable = fetch_enable;
assign rf_d = write_dst;
assign rf_dval = write_dval;
assign rf_we = write_rf_we;
assign fetch_j = (alu_j != 0);
// If insn in front of us is reading from data memory AND writing back to a register AND we're using that register AND next instruction isn't a store
// OR
// If waiting for a jump or a branch
// ( memory operation is load ) AND (( FD Src1 == DX Dst ) OR (( FD Src2 == DX Dst ) AND (FD Mem Op != STORE)
assign stall = (((alu_dmem_func[0] == 1 && alu_dmem_func[1] == 0) && ((decode_src1 == alu_dst) || ((decode_src2 == alu_dst) && decode_dmem_func[1] != 1))) | (alu_j != 0) | alu_z == 1) ? 1 : 0;
initial
begin
clk = 1'b0;
enable = 1'b1;
addr_write = 32'h8001_fffc;
din = 32'b0000_0000;
rw_write = 1'b1;
access_size = 2'b00;
test_mode = 0;
init_dval = 0;
init_dst = 0;
init_rf_we = 0;
alu_j = 0;
write_func = 0;
write_dst = 0;
data_dst = 0;
data_wb_func = 0;
alu_dst = 0;
alu_wb_func = 0;
alu_src1 = 0;
alu_src2 = 0;
data_mem_func = 0;
data_src2_reg = 0;
end
always @(posedge clk)
begin
// Only dispatch one instruction every 5 cycles
// M/W
write_dst = data_dst;
write_func = data_wb_func;
write_res = data_res;
// X/M
data_res = alu_res;
data_s2 = aluSrc2Bypass;
data_isn = alu_isn;
data_pc = alu_pc;
data_br_tgt = alu_br_tgt;
data_mem_func = alu_dmem_func;
data_dst = alu_dst;
data_wb_func = alu_wb_func;
data_src2_reg = alu_src2;
// D/X
if(stall == 0)
begin
alu_pc = decode_pc;
alu_s1val = rf_s1val;
alu_s2val = rf_s2val;
alu_b_ctrl = decode_b_ctrl;
alu_funct = decode_funct;
alu_isn = decode_isn;
alu_imm = decode_imm;
alu_addr = decode_addr;
alu_dmem_func = decode_dmem_func;
alu_dst = decode_dst;
alu_wb_func = decode_wb_func;
alu_j = decode_j;
alu_src1 = decode_src1;
alu_src2 = decode_src2;
end
else
begin
alu_pc = decode_pc;
alu_s1val = 0;
alu_s2val = 0;
alu_b_ctrl = 0;
alu_funct = 0;
alu_isn = 0;
alu_imm = 0;
alu_addr = 0;
alu_dmem_func = 0;
alu_dst = 0;
alu_wb_func = 0;
alu_j = 0;
alu_src1 = 0;
alu_src2 = 0;
end
if(stall == 0)
begin
// F/D
decode_pc = addr;
decode_isn = mem_dout;
end
end
always @(negedge clk)
begin
if(alu_z == 1)
begin
$display("Branch target is %h", alu_br_tgt);
end
if(alu_j != 0)
begin
$display("Jump target is %h", alu_j_tgt);
end
end
always
#5 clk = !clk;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 13:07:09 11/04/2015
// Design Name:
// Module Name: KeyBoardControler
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module KeyBoardControler(
input wire clk,
input wire PS2C,
input wire PS2D,
input wire InteAccept,
output reg[15:0] scanCode,
output reg KeyBoardInte
);
/*
reg clk;
reg PS2C;
reg PS2D;
wire InteAccept;
reg en;
assign InteAccept = KeyBoardInte & en;
initial begin
clk = 0;
PS2C = 0;
PS2D = 0;
en = 0;
#12000
en = 1;
end
//always@(posedge clk) begin
// InteAccept <= KeyBoardInte;
//end
always #10 begin
clk = ~clk;
end
always #200 begin
PS2C = ~PS2C;
end
always #330 begin
PS2D = ~PS2D;
end
*/
reg[7:0] buffer[15:0];
reg[3:0] put,get;
reg[3:0] state;
reg[22:0] count;
reg PS2Cf,PS2Df;
reg [7:0] ps2c_filter,ps2d_filter;
reg [10:0] shift1,shift2;
reg new;
initial begin
put<=0;
get<=0;
ps2c_filter<=0;
ps2d_filter<=0;
PS2Cf<=1;
PS2Df<=1;
shift1 <= 0;
shift2 <= 0;
state <= 0;
count <= 0;
new <= 0;
KeyBoardInte <= 0;
end
always @(posedge clk) begin
//¶ÔʱÖÓÏߺÍÊý¾ÝÏß½øÐйýÂË
ps2c_filter[7]<=PS2C;
ps2c_filter[6:0]<=ps2c_filter[7:1];
ps2d_filter[7]<=PS2D;
ps2d_filter[6:0]<=ps2d_filter[7:1];
if(ps2c_filter == 8'b11111111)
PS2Cf<=1;
else begin
if(ps2c_filter == 8'b00000000)
PS2Cf<=0;
end
if(ps2d_filter == 8'b11111111)
PS2Df<=1;
else begin
if(ps2d_filter == 8'b00000000)
PS2Df<=0;
end
if(PS2Df) begin
count <= count + 1;
end
else begin
count <= 1;
end
if(state == 10) begin
new <= 1;
end
if((state == 0) && new) begin
if(put != get-1) begin
buffer[put] <= shift1[8:1];
put <= put+1;
new <= 0;
end
end
if((get == put) | InteAccept) begin
KeyBoardInte <= 0;
end
else begin
if(KeyBoardInte == 0) begin
scanCode <= buffer[get];
KeyBoardInte <= 1;
end
end
if(InteAccept & (get != put)) begin
get <= get + 1;
end
end
wire rst;
assign rst = (count == 0);
//ÒÆλ¼Ä´æÆ÷£¬ÓÃÒÔ¸ù¾ÝPS2µÄʱÖӼǼPS2µÄɨÃèÂë
always @(negedge PS2Cf or posedge rst) begin
if(rst) begin
state <= 0;
end
else begin
shift1<={PS2Df,shift1[10:1]};
shift2<={shift1[0],shift2[10:1]};//ÏÈ·¢Ë͸ß×Ö½Ú£¬ÔÙ·¢Ë͵Í×Ö½Ú
if(state == 0 && PS2Df == 0) begin
state <= 1;
end
else if(state == 10) begin
state <= 0;
end
else begin
state <= state + 1;
end
end
end
endmodule
|
`default_nettype none
//////////////////////////////////////////////////////////////////////////////////
//
// Company: University of Bonn
// Engineer: John Bieling
//
// Sample implementation of jTDC using Spartan6 on
// ELB VFB6 board with LVDS inputs
//
//////////////////////////////////////////////////////////////////////////////////
module jTDCv6 (
inout wire [31:0] D_INT,
input wire [15:0] A_INT,
input wire WRITE_INT,
input wire READ_INT,
output wire DTACK_INT,
input wire CLK,
inout wire SCL_General,
inout wire SDA_General,
output wire [7:0] USER_LED,
input wire [7:0] Pushbutton,
input wire [1:0] Differential_IN,
inout wire [73:0] FPGA_SPARE,
input wire [3:0] NIM_IN,
output wire [3:0] NIM_OUT,
inout wire [73:0] MEZ_A,
inout wire [73:0] MEZ_B,
inout wire [73:0] MEZ_C,
input wire [5:0] ID_A,
input wire [5:0] ID_B,
input wire [5:0] ID_C);
//-----------------------------------------------------------------------------
//-- Basic Setup --------------------------------------------------------------
//-----------------------------------------------------------------------------
parameter fw = 8'h22;
parameter resolution = 2; //readout every second carry step
parameter bits = 96; //empirical value for resolution=2 on VFB6
parameter encodedbits = 9; //includes hit bit
parameter fifocounts = 15; //max event size: (fifocounts+1)*1024-150;
parameter tdc_channels = 98; //number of tdc channels (max 100, see mapping below)
parameter scaler_channels = 98; //number of scaler channels
genvar i;
//-----------------------------------------------------------------------------
//-- IO cards Setup for VFB6 board --------------------------------------------
//-----------------------------------------------------------------------------
wire [31:0] LVDS_A_IN;
wire [31:0] LVDS_B_IN;
wire [31:0] LVDS_C_IN;
mez_lvds_in lvds_a_in (.MEZ(MEZ_A[73:0]),.data(LVDS_A_IN));
mez_lvds_in lvds_b_in (.MEZ(MEZ_B[73:0]),.data(LVDS_B_IN));
mez_lvds_in lvds_c_in (.MEZ(MEZ_C[73:0]),.data(LVDS_C_IN));
//-----------------------------------------------------------------------------
//-- CLK Setup for Spartan6 ---------------------------------------------------
//-----------------------------------------------------------------------------
wire CLKBUS;
wire CLK200;
wire CLK400;
pll_vfb6_400 PLL_TDC (
.CLKIN(CLK),
.CLK1(CLKBUS),
.CLK2(CLK200),
.CLK4(CLK400));
//---------------------------------------------------------------------------------
//-- VME-BUS Setup for VFB6 board (res. addr: h0000, h0004, h0008, h0010, h0014) --
//---------------------------------------------------------------------------------
wire [31:0] statusregister;
wire [31:0] databus;
wire [15:0] addressbus;
wire readsignal;
wire writesignal;
assign statusregister [7:0] = 8'b00000001; //-- Firmware version
assign statusregister [13:8] = 6'b000001; //-- Firmware type
//-- For REV B boards
assign statusregister [19:14] = ID_A; //-- Board type Mezzanine_A
assign statusregister [25:20] = ID_B; //-- Board type Mezzanine_B
assign statusregister [31:26] = ID_C; //-- Board type Mezzanine_C
bus_interface_vfb6 BUS_INT (
.board_databus(D_INT),
.board_address(A_INT),
.board_read(READ_INT),
.board_write(WRITE_INT),
.board_dtack(DTACK_INT),
.CLK(CLKBUS),
.statusregister(statusregister),
.internal_databus(databus),
.internal_address(addressbus),
.internal_read(readsignal),
.internal_write(writesignal));
//-----------------------------------------------------------------------------
//-- I2C Setup for VFB6 board (res. addr: h0030, h0034, h0038, h003C, h0040) --
//-- not needed for actual jTDC, just an additional feature of the VFB6 --
//-----------------------------------------------------------------------------
i2c_interface I2C_INT (
.databus(databus),
.addressbus(addressbus),
.CLK(CLKBUS),
.writesignal(writesignal),
.readsignal(readsignal),
.SCL_General(SCL_General),
.SDA_General(SDA_General));
//-----------------------------------------------------------------------------
//-- VME Control Register A ---------------------------------------------------
//-----------------------------------------------------------------------------
(* KEEP = "true" *) wire [31:0] config_register_A;
rw_register #(.myaddress(16'h0020)) VME_CONFIG_REGISTER_A (
.databus(databus),
.addressbus(addressbus),
.readsignal(readsignal),
.writesignal(writesignal),
.CLK(CLKBUS),
.registerbits(config_register_A));
wire [4:0] geoid = config_register_A[4:0];
wire dutycycle = config_register_A[5];
wire edgechoice = config_register_A[6];
wire tdc_trigger_select = config_register_A[7];
wire [23:0] clock_limit = config_register_A[31:8];
//-----------------------------------------------------------------------------
//-- VME Control Register B ---------------------------------------------------
//-----------------------------------------------------------------------------
(* KEEP = "TRUE" *) wire [31:0] config_register_B;
rw_register #(.myaddress(16'h0028)) VME_CONFIG_REGISTER_B (
.databus(databus),
.addressbus(addressbus),
.writesignal(writesignal),
.readsignal(readsignal),
.CLK(CLKBUS),
.registerbits(config_register_B));
wire [8:0] busyshift = config_register_B[8:0];
wire stop_counting_on_busy = config_register_B[9];
wire [4:0] busyextend = config_register_B[15:11];
wire [3:0] hightime = config_register_B[19:16];
wire [3:0] deadtime = config_register_B[23:20];
wire [2:0] trigger_group_0 = config_register_B[26:24];
wire [2:0] trigger_group_1 = config_register_B[29:27];
wire disable_external_latch = config_register_B[30];
wire fake_mode = config_register_B[31];
//-----------------------------------------------------------------------------
//-- VME Trigger Register -----------------------------------------------------
//-----------------------------------------------------------------------------
wire [7:0] iFW = fw;
wire [7:0] iCH = tdc_channels;
wire [7:0] iBIT = encodedbits-1; //the hit-bit is not pushed into the fifo
wire [7:0] iM = 8'h34;
wire [31:0] trigger_register_wire;
toggle_register #(.myaddress(16'h0024)) VME_TRIGGER_REGISTER (
.databus(databus),
.addressbus(addressbus),
.writesignal(writesignal),
.readsignal(readsignal),
.CLK(CLKBUS),
.info({iCH,iBIT,iM,iFW}),
.registerbits(trigger_register_wire));
//cross clock domain
reg [31:0] trigger_register;
always@(posedge CLK200)
begin
trigger_register <= trigger_register_wire;
end
//-- toggle bit 0: tdc_reset, make tdc_reset multiple cycles long
wire tdc_reset_start = trigger_register[0];
reg [3:0] tdc_reset_counter = 4'b0000;
reg tdc_reset;
reg tdc_reset_buffer;
always@(posedge CLKBUS)
begin
tdc_reset <= tdc_reset_buffer;
if (tdc_reset_counter == 4'b0000)
begin
tdc_reset_buffer <= 1'b0;
if (tdc_reset_start == 1'b1) tdc_reset_counter <= 4'b1111;
end else begin
tdc_reset_buffer <= 1'b1;
tdc_reset_counter <= tdc_reset_counter - 1;
end
end
//-- toggle bit 1: vme_counter_reset
wire vme_counter_reset;
datapipe #(.data_width(1),.pipe_steps(2)) counter_reset_pipe (
.data(trigger_register[1]),
.piped_data(vme_counter_reset),
.CLK(CLK200));
//-- toggle bit 2: vme_counter_latch
wire vme_counter_latch;
datapipe #(.data_width(1),.pipe_steps(1)) counter_latch_pipe (
.data(trigger_register[2]),
.piped_data(vme_counter_latch),
.CLK(CLK200));
//-- toggle bit 3: output_reset
wire output_reset = trigger_register[3];
//-- toggle bit 6: generate fake data input for busyshift measurement
wire fake_data;
signal_clipper fake_data_clip ( .sig(trigger_register[6]), .CLK(CLK200), .clipped_sig(fake_data));
//-----------------------------------------------------------------------------
//-- Enable Register ----------------------------------------------------------
//-----------------------------------------------------------------------------
(* KEEP = "TRUE" *) wire [95:0] enable_register;
rw_register #(.myaddress(16'h2000)) VME_ENABLE_REGISTER_A (
.databus(databus),
.addressbus(addressbus),
.writesignal(writesignal),
.readsignal(readsignal),
.CLK(CLKBUS),
.registerbits(enable_register[31:0]));
rw_register #(.myaddress(16'h2004)) VME_ENABLE_REGISTER_B (
.databus(databus),
.addressbus(addressbus),
.writesignal(writesignal),
.readsignal(readsignal),
.CLK(CLKBUS),
.registerbits(enable_register[63:32]));
rw_register #(.myaddress(16'h2008)) VME_ENABLE_REGISTER_C (
.databus(databus),
.addressbus(addressbus),
.writesignal(writesignal),
.readsignal(readsignal),
.CLK(CLKBUS),
.registerbits(enable_register[95:64]));
//-----------------------------------------------------------------------------
//-- Busy & Latch -------------------------------------------------------------
//-----------------------------------------------------------------------------
wire raw_busy;
wire latch;
reg busy;
reg counter_latch;
reg counter_reset;
//the leading edge of the "busy & latch" signal is the actual latch, which is used only to latch the input scaler
//while the "busy & latch" signal is asserted, the input scaler will not count (if stop_counting_on_busy is set)
leading_edge_extractor LATCH_EXTRACTOR (.sig(NIM_IN[0]), .CLK(CLK200), .unclipped_extend(busyextend), .clipped_sig(latch), .unclipped_sig(raw_busy) );
always@(posedge CLK200)
begin
busy <= stop_counting_on_busy & raw_busy;
counter_latch <= vme_counter_latch | (latch & ~disable_external_latch);
counter_reset <= vme_counter_reset;
end
//-----------------------------------------------------------------------------
//-- Map Inputs To 100 TDC Channels -------------------------------------------
//-----------------------------------------------------------------------------
wire [99:0] tdc_enable;
wire [99:0] tdc_channel;
assign tdc_channel[0] = NIM_IN[0];
assign tdc_enable[0] = 1'b1;
assign tdc_enable[96:1] = enable_register[95:0];
assign tdc_channel[32:1] = (edgechoice == 1'b0) ? LVDS_A_IN[31:0] : ~LVDS_A_IN[31:0];
assign tdc_channel[64:33] = (edgechoice == 1'b0) ? LVDS_B_IN[31:0] : ~LVDS_B_IN[31:0];
assign tdc_channel[96:65] = (edgechoice == 1'b0) ? LVDS_C_IN[31:0] : ~LVDS_C_IN[31:0];
assign tdc_channel[97] = NIM_IN[2];
assign tdc_enable[97] = 1'b1;
//-----------------------------------------------------------------------------
//-- Sampling -----------------------------------------------------------------
//-----------------------------------------------------------------------------
wire [99:0] tdc_hits;
wire [tdc_channels-1:0] scaler_hits;
wire [tdc_channels*encodedbits-1:0] tdc_data_codes;
generate
for (i=0; i < tdc_channels; i=i+1) begin : INPUTSTAGE
wire [bits-1:0] sample;
carry_sampler_spartan6 #(.bits(bits),.resolution(resolution)) SAMPLER (
.d(~tdc_channel[i]),
.q(sample),
.CLK(CLK400));
wire scaler;
encode_96bit_pattern #(.encodedbits(encodedbits)) ENCODE (
.edgechoice(1'b1), //sending the signal inverted into the chain gives better results
.d(sample),
.enable(tdc_enable[i]),
.CLK400(CLK400),
.CLK200(CLK200),
.code(tdc_data_codes[(i+1)*encodedbits-1:i*encodedbits]),
.tdc_hit(tdc_hits[i]),
.scaler_hit(scaler));
//fake scaler hit for busyshift determination
reg scaler_buffer;
if (i==1) begin
always@(posedge CLK200)
begin
if (fake_mode == 1'b1) begin
scaler_buffer <= fake_data;
end else begin
scaler_buffer <= scaler;
end
end
end else begin
always@(posedge CLK200)
begin
scaler_buffer <= scaler;
end
end
assign scaler_hits[i] = scaler_buffer;
end
endgenerate
//unused channels
assign tdc_hits[99:tdc_channels] = 'b0;
//-----------------------------------------------------------------------------
//-- Generate Trigger Outputs -------------------------------------------------
//-----------------------------------------------------------------------------
wire [95:0] trigger_hits;
wire [23:0] trigger_first_or;
//only use LVDS hits (data channels) for trigger output
assign trigger_hits[95:0] = tdc_hits[96:1];
generate
for (i=0; i < 24; i=i+1) begin : TRIGGER_ORHITS
assign trigger_first_or[i] = |trigger_hits[i*4+3:i*4];
end
endgenerate
reg [23:0] trigger_out_0;
reg [5:0] trigger_out_1;
reg trigger_out_A;
reg trigger_out_B;
reg trigger_out_C;
reg [2:0] trigger_choice_0;
reg [2:0] trigger_choice_1;
reg [1:0] trigger_out;
always@(posedge CLK200)
begin
// generate trigger output signal
trigger_out_0 <= trigger_first_or;
trigger_out_1[0] <= |trigger_out_0[ 3: 0]; //A
trigger_out_1[1] <= |trigger_out_0[ 7: 4]; //A
trigger_out_1[2] <= |trigger_out_0[11: 8]; //B
trigger_out_1[3] <= |trigger_out_0[15:12]; //B
trigger_out_1[4] <= |trigger_out_0[19:16]; //C
trigger_out_1[5] <= |trigger_out_0[23:20]; //C
trigger_out_A <= |trigger_out_1[1:0];
trigger_out_B <= |trigger_out_1[3:2];
trigger_out_C <= |trigger_out_1[5:4];
if (trigger_group_0[0] == 1'b1) trigger_choice_0[0] <= trigger_out_A; else trigger_choice_0[0] <= 1'b0;
if (trigger_group_0[1] == 1'b1) trigger_choice_0[1] <= trigger_out_B; else trigger_choice_0[1] <= 1'b0;
if (trigger_group_0[2] == 1'b1) trigger_choice_0[2] <= trigger_out_C; else trigger_choice_0[2] <= 1'b0;
if (trigger_group_1[0] == 1'b1) trigger_choice_1[0] <= trigger_out_A; else trigger_choice_1[0] <= 1'b0;
if (trigger_group_1[1] == 1'b1) trigger_choice_1[1] <= trigger_out_B; else trigger_choice_1[1] <= 1'b0;
if (trigger_group_1[2] == 1'b1) trigger_choice_1[2] <= trigger_out_C; else trigger_choice_1[2] <= 1'b0;
trigger_out[0] <= |trigger_choice_0;
trigger_out[1] <= |trigger_choice_1;
end
//-----------------------------------------------------------------------------
//-- jTDC ---------------------------------------------------------------------
//-----------------------------------------------------------------------------
wire data_fifo_readrequest;
wire event_fifo_readrequest;
wire [31:0] data_fifo_value;
wire [31:0] event_fifo_value;
jTDC_core #(.tdc_channels(tdc_channels), .encodedbits(encodedbits), .fifocounts(fifocounts)) jTDC (
.tdc_hits(tdc_hits),
.tdc_data_codes(tdc_data_codes),
.tdc_trigger_select(tdc_trigger_select),
.tdc_reset(tdc_reset),
.clock_limit(clock_limit),
.geoid(geoid),
.iBIT(iBIT),
.CLK200(CLK200),
.CLKBUS(CLKBUS),
.event_fifo_readrequest(event_fifo_readrequest),
.data_fifo_readrequest(data_fifo_readrequest),
.event_fifo_value(event_fifo_value),
.data_fifo_value(data_fifo_value) );
readonly_register_with_readtrigger #(.myaddress(16'h8888)) EVENT_FIFO_READOUT (
.databus(databus),
.addressbus(addressbus),
.readsignal(readsignal),
.readtrigger(event_fifo_readrequest),
.CLK(CLKBUS),
.registerbits(event_fifo_value));
readonly_register_with_readtrigger #(.myaddress(16'h4444)) DATA_FIFO_READOUT (
.databus(databus),
.addressbus(addressbus),
.readsignal(readsignal),
.readtrigger(data_fifo_readrequest),
.CLK(CLKBUS),
.registerbits(data_fifo_value));
//-----------------------------------------------------------------------------
//-- SCALER -------------------------------------------------------------------
//-----------------------------------------------------------------------------
generate
if (scaler_channels > 0)
begin
//to reduce routing of the global addressbus, I implemented an internal
//128 addr mux for the input scaler. They will use only one external addr,
//each read request to the clock_counter_reg resets the scaler_addr and
//each read request to the input_counter_reg increments the scaler_addr
//furthermore, the input_counter_reg can be addressed by 128 consecutive
//addresses (addressbus is masked), so the external readout can be performed
//as usual, the input scalers just need to be read out in order
wire scaler_readout_addr_reset;
wire scaler_readout_addr_next;
reg [6:0] scaler_readout_addr;
wire [31:0] scaler_readout_pipe_addr;
wor [31:0] muxed_counts;
//busyshift
wire [127:0] shifted_hits;
BRAMSHIFT_512 #(.shift_bitsize(9),.width(4),.input_pipe_steps(1),.output_pipe_steps(1)) BRAM_BUSYSHIFT (
.d({'b0,scaler_hits}),
.q(shifted_hits),
.CLK(CLK200), .shift(busyshift));
//input counter
for (i=0; i < 128; i=i+1) begin : INPUT_HITS_COUNTER
if (i<scaler_channels && i<tdc_channels) begin
//take sample[0] (re-inverted) for dutycycle measurement
(* KEEP = "true" *) wire dutyline = ~INPUTSTAGE[i].sample[0];
reg busycount;
reg busycount_0;
reg busycount_1;
reg input_buffer;
always@(posedge CLK200) begin
input_buffer <= dutyline;
busycount_0 <= shifted_hits[i] && ~busy;
busycount_1 <= busycount_0;
if (dutycycle == 1'b0) busycount <= busycount_1;
else busycount <= input_buffer;
end
wire [31:0] input_counts;
dsp_multioption_counter #(.clip_count(0)) INPUT_COUNTER (
.countClock(CLK200),
.count(busycount),
.reset(counter_reset),
.countout(input_counts));
wire [31:0] input_latched_counts;
datalatch #(.latch_pipe_steps(1)) INPUT_COUNTER_DATALATCH (
.CLK(CLK200),
.latch(counter_latch),
.data(input_counts),
.latched_data(input_latched_counts));
//use the scaler_readout_addr to mux the correct counter to the readout register
//since the source data is latched, the ucf constraint CROSSCLOCK is giving this mux 50ns to settle
assign muxed_counts = (scaler_readout_addr == i) ? input_latched_counts : 32'b0;
end
end
//referenz clock counter (to be able to calculate rates)
wire [31:0] pureclkcounts;
dsp_multioption_counter #(.clip_count(0)) PURE_CLOCK_COUNTER (
.countClock(CLK200),
.count(!busy),
.reset(counter_reset),
.countout(pureclkcounts));
wire [31:0] clklatch;
datalatch #(.latch_pipe_steps(1)) CLOCK_COUNTER_DATALATCH (
.CLK(CLK200),
.latch(counter_latch),
.data(pureclkcounts),
.latched_data(clklatch));
//read of this register resets the scaler_readout_addr
readonly_register_with_readtrigger #(.myaddress(16'h0044)) CLOCK_COUNTER_READOUT (
.databus(databus),
.addressbus(addressbus),
.readsignal(readsignal),
.readtrigger(scaler_readout_addr_reset),
.CLK(CLKBUS),
.registerbits(clklatch));
//increment scaler_readout_addr on the negedge of next (=read)
//to keep the muxed value stable during read
dsp_multioption_counter #(.clip_count(1),.clip_reset(1)) SCALER_READOUT_ADDR_INC (
.countClock(CLKBUS),
.count(~scaler_readout_addr_next),
.reset(scaler_readout_addr_reset),
.countout(scaler_readout_pipe_addr));
reg [31:0] muxed_counts_pipe;
always@(posedge CLKBUS) begin
muxed_counts_pipe <= muxed_counts;
scaler_readout_addr <= scaler_readout_pipe_addr[6:0];
end
//each read of this register increments the scaler_readout_addr
readonly_register_with_readtrigger #(.myaddress(16'h4000)) INPUT_COUNTER_READOUT (
.databus(databus),
.addressbus({addressbus[15:9],9'b0}), //from these 9 bits only 7 are usable
.readsignal(readsignal),
.readtrigger(scaler_readout_addr_next),
.CLK(CLKBUS),
.registerbits(muxed_counts_pipe));
end
endgenerate
//-----------------------------------------------------------------------------
//-- NIM Outputs --------------------------------------------------------------
//-----------------------------------------------------------------------------
wire [1:0] trigger_output;
output_shaper TRIGGER_SHAPER_0 (
.d(trigger_out[0]),
.hightime(hightime),
.deadtime(deadtime),
.CLK(CLK200),
.pulse(trigger_output[0]),
.reset(output_reset));
output_shaper TRIGGER_SHAPER_1 (
.d(trigger_out[1]),
.hightime(hightime),
.deadtime(deadtime),
.CLK(CLK200),
.pulse(trigger_output[1]),
.reset(output_reset));
assign NIM_OUT[0] = 0;
assign NIM_OUT[1] = trigger_output[0]; //trigger out A
assign NIM_OUT[2] = 0;
assign NIM_OUT[3] = trigger_output[1]; //trigger out B
assign FPGA_SPARE = 0;
assign USER_LED = 0;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NOR2_1_V
`define SKY130_FD_SC_LP__NOR2_1_V
/**
* nor2: 2-input NOR.
*
* Verilog wrapper for nor2 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__nor2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nor2_1 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__nor2 base (
.Y(Y),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nor2_1 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__nor2 base (
.Y(Y),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__NOR2_1_V
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: dram_async_pad.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module dram_async_pad(/*AUTOARG*/
// Outputs
bso,
// Inouts
pad,
// Inputs
vrefcode, vdd_h, update_dr, shift_dr,
mode_ctrl, hiz_n, data, clock_dr, cbu, cbd, bsi
);
//////////////////////////////////////////////////////////////////////////
// INPUTS
//////////////////////////////////////////////////////////////////////////
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input bsi; // To sstl_pad of dram_sstl_pad.v
input [8:1] cbd; // To sstl_pad of dram_sstl_pad.v
input [8:1] cbu; // To sstl_pad of dram_sstl_pad.v
input clock_dr; // To sstl_pad of dram_sstl_pad.v
input data; // To ctl_edgelogic of dram_ctl_edgelogic.v
input hiz_n; // To sstl_pad of dram_sstl_pad.v
input mode_ctrl; // To sstl_pad of dram_sstl_pad.v
input shift_dr; // To sstl_pad of dram_sstl_pad.v
input update_dr; // To sstl_pad of dram_sstl_pad.v
input vdd_h; // To sstl_pad of dram_sstl_pad.v
input [7:0] vrefcode; // To sstl_pad of dram_sstl_pad.v
// End of automatics
//////////////////////////////////////////////////////////////////////////
// INOUTPUTS
//////////////////////////////////////////////////////////////////////////
inout pad;
//////////////////////////////////////////////////////////////////////////
// OUTPUTS
//////////////////////////////////////////////////////////////////////////
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output bso; // From sstl_pad of dram_sstl_pad.v
// End of automatics
//////////////////////////////////////////////////////////////////////////
// CODE
//////////////////////////////////////////////////////////////////////////
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire to_pad; // From ctl_edgelogic of dram_ctl_edgelogic.v
// End of automatics
// INSTANTIATING PAD LOGIC
dram_async_edgelogic async_edgelogic(/*AUTOINST*/
// Outputs
.to_pad(to_pad),
// Inputs
.data (data));
// SSTL LOGIC
/*dram_sstl_pad AUTO_TEMPLATE(
.pad (pad),
.oe (1'b1),
.to_core (),
.odt_enable_mask (1'b1),
.data_in (to_pad));
*/
dram_sstl_pad sstl_pad(/*AUTOINST*/
// Outputs
.bso (bso),
.to_core (), // Templated
// Inouts
.pad (pad), // Templated
// Inputs
.bsi (bsi),
.cbd (cbd[8:1]),
.cbu (cbu[8:1]),
.clock_dr (clock_dr),
.data_in (to_pad), // Templated
.hiz_n (hiz_n),
.mode_ctrl (mode_ctrl),
.odt_enable_mask (1'b1), // Templated
.oe (1'b1), // Templated
.shift_dr (shift_dr),
.update_dr (update_dr),
.vdd_h (vdd_h),
.vrefcode (vrefcode[7:0]));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S18_PP_SYMBOL_V
`define SKY130_FD_SC_HD__CLKDLYBUF4S18_PP_SYMBOL_V
/**
* clkdlybuf4s18: Clock Delay Buffer 4-stage 0.18um length inner stage
* gates.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__clkdlybuf4s18 (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__CLKDLYBUF4S18_PP_SYMBOL_V
|
/////////////////////////////////
// bsg_nonsynth_dramsim3_map.v //
/////////////////////////////////
`include "bsg_defines.v"
module bsg_nonsynth_dramsim3_map
import bsg_dramsim3_pkg::*;
#(parameter `BSG_INV_PARAM(channel_addr_width_p)
, parameter `BSG_INV_PARAM(data_width_p)
, parameter `BSG_INV_PARAM(num_channels_p)
, parameter `BSG_INV_PARAM(num_columns_p)
, parameter `BSG_INV_PARAM(num_rows_p)
, parameter `BSG_INV_PARAM(num_ba_p)
, parameter `BSG_INV_PARAM(num_bg_p)
, parameter `BSG_INV_PARAM(num_ranks_p)
, parameter `BSG_INV_PARAM(address_mapping_p)
, parameter `BSG_INV_PARAM(channel_select_p)
, parameter debug_p=0
, parameter lg_num_channels_lp=$clog2(num_channels_p)
, parameter lg_num_columns_lp=$clog2(num_columns_p)
, parameter lg_num_rows_lp=$clog2(num_rows_p)
, parameter lg_num_ba_lp=$clog2(num_ba_p)
, parameter lg_num_bg_lp=$clog2(num_bg_p)
, parameter lg_num_ranks_lp=$clog2(num_ranks_p)
, parameter data_mask_width_lp=(data_width_p>>3)
, parameter byte_offset_width_lp=`BSG_SAFE_CLOG2(data_width_p>>3)
, parameter addr_width_lp=lg_num_channels_lp+channel_addr_width_p
)
(
input logic [channel_addr_width_p-1:0] ch_addr_i
, output logic [addr_width_lp-1:0] mem_addr_o
);
localparam co_pos_lp = byte_offset_width_lp;
localparam ba_pos_lp = co_pos_lp + lg_num_columns_lp;
localparam bg_pos_lp = ba_pos_lp + lg_num_ba_lp;
localparam ra_pos_lp = bg_pos_lp + lg_num_bg_lp;
localparam ro_pos_lp = ra_pos_lp + lg_num_ranks_lp;
if (address_mapping_p == e_ro_ra_bg_ba_co_ch) begin
assign mem_addr_o
= {
ch_addr_i[channel_addr_width_p-1:byte_offset_width_lp],
{lg_num_channels_lp!=0{`BSG_MAX(lg_num_channels_lp, 1)'(channel_select_p)}},
{byte_offset_width_lp{1'b0}}
};
end
else if (address_mapping_p == e_ro_ra_bg_ba_ch_co) begin
assign mem_addr_o
= {
ch_addr_i[channel_addr_width_p-1:lg_num_columns_lp+byte_offset_width_lp],
{lg_num_channels_lp!=0{`BSG_MAX(lg_num_channels_lp, 1)'(channel_select_p)}},
ch_addr_i[lg_num_columns_lp+byte_offset_width_lp-1:byte_offset_width_lp],
{byte_offset_width_lp{1'b0}}
};
end
else if (address_mapping_p == e_ro_ch_ra_ba_bg_co) begin
assign mem_addr_o
= {
ch_addr_i[ro_pos_lp+:lg_num_rows_lp],
{lg_num_channels_lp!=0{`BSG_MAX(lg_num_channels_lp, 1)'(channel_select_p)}},
{lg_num_ranks_lp!=0{ch_addr_i[ra_pos_lp+:`BSG_MAX(lg_num_ranks_lp, 1)]}},
{lg_num_ba_lp!=0{ch_addr_i[ba_pos_lp+:`BSG_MAX(lg_num_ba_lp, 1)]}},
{lg_num_bg_lp!=0{ch_addr_i[bg_pos_lp+:`BSG_MAX(lg_num_bg_lp, 1)]}},
ch_addr_i[co_pos_lp+:lg_num_columns_lp],
{byte_offset_width_lp{1'b0}}
};
end
endmodule // bsg_nonsynth_dramsim3_map
`BSG_ABSTRACT_MODULE(bsg_nonsynth_dramsim3_map)
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module FIFO_image_filter_img_2_data_stream_0_V_shiftReg (
clk,
data,
ce,
a,
q);
parameter DATA_WIDTH = 32'd8;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 32'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg[DATA_WIDTH-1:0] SRL_SIG [0:DEPTH-1];
integer i;
always @ (posedge clk)
begin
if (ce)
begin
for (i=0;i<DEPTH-1;i=i+1)
SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
module FIFO_image_filter_img_2_data_stream_0_V (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din);
parameter MEM_STYLE = "auto";
parameter DATA_WIDTH = 32'd8;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 32'd2;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output[DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input[DATA_WIDTH - 1:0] if_din;
wire[ADDR_WIDTH - 1:0] shiftReg_addr ;
wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
reg[ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH+1){1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @ (posedge clk) begin
if (reset == 1'b1)
begin
mOutPtr <= ~{ADDR_WIDTH+1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr -1;
if (mOutPtr == 0)
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr +1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH-2)
internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
FIFO_image_filter_img_2_data_stream_0_V_shiftReg
#(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH))
U_FIFO_image_filter_img_2_data_stream_0_V_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q));
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLYGATE4SD3_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__DLYGATE4SD3_BEHAVIORAL_PP_V
/**
* dlygate4sd3: Delay Buffer 4-stage 0.50um length inner stage gates.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__dlygate4sd3 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLYGATE4SD3_BEHAVIORAL_PP_V
|
/////////////////////////////////////////////////////////////////////
//// ////
//// Non-restoring unsigned divider ////
//// ////
//// Author: Richard Herveille ////
//// [email protected] ////
//// www.asics.ws ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002 Richard Herveille ////
//// [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: div_uu.v,v 1.3 2003-09-17 13:08:53 rherveille Exp $
//
// $Date: 2003-09-17 13:08:53 $
// $Revision: 1.3 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.2 2002/10/31 13:54:58 rherveille
// Fixed a bug in the remainder output of div_su.v
//
// Revision 1.1.1.1 2002/10/29 20:29:10 rherveille
//
//
//
//synopsys translate_off
`include "timescale.v"
//synopsys translate_on
module div_uu(clk, ena, z, d, q, s, div0, ovf);
//
// parameters
//
parameter z_width = 16;
parameter d_width = z_width /2;
//
// inputs & outputs
//
input clk; // system clock
input ena; // clock enable
input [z_width -1:0] z; // divident
input [d_width -1:0] d; // divisor
output [d_width -1:0] q; // quotient
output [d_width -1:0] s; // remainder
output div0;
output ovf;
reg [d_width-1:0] q;
reg [d_width-1:0] s;
reg div0;
reg ovf;
//
// functions
//
function [z_width:0] gen_s;
input [z_width:0] si;
input [z_width:0] di;
begin
if(si[z_width])
gen_s = {si[z_width-1:0], 1'b0} + di;
else
gen_s = {si[z_width-1:0], 1'b0} - di;
end
endfunction
function [d_width-1:0] gen_q;
input [d_width-1:0] qi;
input [z_width:0] si;
begin
gen_q = {qi[d_width-2:0], ~si[z_width]};
end
endfunction
function [d_width-1:0] assign_s;
input [z_width:0] si;
input [z_width:0] di;
reg [z_width:0] tmp;
begin
if(si[z_width])
tmp = si + di;
else
tmp = si;
assign_s = tmp[z_width-1:z_width-d_width];
end
endfunction
//
// variables
//
reg [d_width-1:0] q_pipe [d_width-1:0];
reg [z_width:0] s_pipe [d_width:0];
reg [z_width:0] d_pipe [d_width:0];
reg [d_width:0] div0_pipe, ovf_pipe;
//
// perform parameter checks
//
// synopsys translate_off
initial
begin
if(d_width !== z_width / 2)
$display("div.v parameter error (d_width != z_width/2).");
end
// synopsys translate_on
integer n0, n1, n2, n3;
// generate divisor (d) pipe
always @(d)
d_pipe[0] <= {1'b0, d, {(z_width-d_width){1'b0}} };
always @(posedge clk)
if(ena)
for(n0=1; n0 <= d_width; n0=n0+1)
d_pipe[n0] <= #1 d_pipe[n0-1];
// generate internal remainder pipe
always @(z)
s_pipe[0] <= z;
always @(posedge clk)
if(ena)
for(n1=1; n1 <= d_width; n1=n1+1)
s_pipe[n1] <= #1 gen_s(s_pipe[n1-1], d_pipe[n1-1]);
// generate quotient pipe
always @(posedge clk)
q_pipe[0] <= #1 0;
always @(posedge clk)
if(ena)
for(n2=1; n2 < d_width; n2=n2+1)
q_pipe[n2] <= #1 gen_q(q_pipe[n2-1], s_pipe[n2]);
// flags (divide_by_zero, overflow)
always @(z or d)
begin
ovf_pipe[0] <= !(z[z_width-1:d_width] < d);
div0_pipe[0] <= ~|d;
end
always @(posedge clk)
if(ena)
for(n3=1; n3 <= d_width; n3=n3+1)
begin
ovf_pipe[n3] <= #1 ovf_pipe[n3-1];
div0_pipe[n3] <= #1 div0_pipe[n3-1];
end
// assign outputs
always @(posedge clk)
if(ena)
ovf <= #1 ovf_pipe[d_width];
always @(posedge clk)
if(ena)
div0 <= #1 div0_pipe[d_width];
always @(posedge clk)
if(ena)
q <= #1 gen_q(q_pipe[d_width-1], s_pipe[d_width]);
always @(posedge clk)
if(ena)
s <= #1 assign_s(s_pipe[d_width], d_pipe[d_width]);
endmodule
|
module NIOSCar(
//////////// CLOCK //////////
CLOCK_50,
//////////// LED //////////
LED,
//////////// KEY //////////
KEY,
//////////// SW //////////
SW,
//////////// SDRAM //////////
DRAM_ADDR,
DRAM_BA,
DRAM_CAS_N,
DRAM_CKE,
DRAM_CLK,
DRAM_CS_N,
DRAM_DQ,
DRAM_DQM,
DRAM_RAS_N,
DRAM_WE_N,
//////////// ADC //////////
ADC_CS_N,
ADC_SADDR,
ADC_SCLK,
ADC_SDAT,
//////////// U0 //////////
U0_F,
U0_T,
//////////// U1 //////////
U1_F,
U1_T,
//////////// U2 //////////
U2_F,
U2_T,
//////////// U3 //////////
U3_F,
U3_T,
//////////// U4 //////////
U4_F,
U4_T,
//////////// U5 //////////
U5_F,
U5_T,
//////////// pwm0 //////////
PWM0Ch0,
PWM0Ch1,
//////////// pwm1 //////////
PWM1Ch0,
PWM1Ch1,
//////////// pwm2 //////////
PWM2Ch0,
PWM2Ch1,
//////////// pwm3 //////////
PWM3Ch0,
PWM3Ch1,
//////////// INPUT//////////
PIO1,
//////////// endcoder0 //////////
Encoder0,
//////////// endcoder1 //////////
Encoder1,
//////////// PIO //////////
GPIO_0,
//////////// uart //////////
// 115200, data bit:8, stop bit: 1, Parity: none
tx_out,
rx_in
);
//=======================================================
// PARAMETER declarations
//=======================================================
//=======================================================
// PORT declarations
//=======================================================
//////////// CLOCK //////////
input CLOCK_50;
//////////// LED //////////
output [7:0] LED;
//////////// KEY //////////
input [1:0] KEY;
//////////// PIO1 //////////
input [3:0] PIO1;
//////////// SW //////////
input [3:0] SW;
//////////// SDRAM //////////
output [12:0] DRAM_ADDR;
output [1:0] DRAM_BA;
output DRAM_CAS_N;
output DRAM_CKE;
output DRAM_CLK;
output DRAM_CS_N;
inout [15:0] DRAM_DQ;
output [1:0] DRAM_DQM;
output DRAM_RAS_N;
output DRAM_WE_N;
////////////// EPCS //////////
//output EPCS_ASDO;
//input EPCS_DATA0;
//output EPCS_DCLK;
//output EPCS_NCSO;
////////////// Accelerometer and EEPROM //////////
//output G_SENSOR_CS_N;
//input G_SENSOR_INT;
//output I2C_SCLK;
//inout I2C_SDAT;
//////////// ADC //////////
output ADC_CS_N;
output ADC_SADDR;
output ADC_SCLK;
input ADC_SDAT;
//////////// U0 //////////
input U0_F;
output U0_T;
//////////// U1 //////////
input U1_F;
output U1_T;
//////////// U2 //////////
input U2_F;
output U2_T;
//////////// U3 //////////
input U3_F;
output U3_T;
//////////// U4 //////////
input U4_F;
output U4_T;
//////////// U5 //////////
input U5_F;
output U5_T;
//////////// pwm0 //////////
output PWM0Ch0;
output PWM0Ch1;
//////////// pwm1 //////////
output PWM1Ch0;
output PWM1Ch1;
//////////// pwm2 //////////
output PWM2Ch0;
output PWM2Ch1;
//////////// pwm3 //////////
output PWM3Ch0;
output PWM3Ch1;
//////////// endcoder0 //////////
input [1:0] Encoder0;
//////////// endcoder1 //////////
input [1:0] Encoder1;
//////////// endcoder1 //////////
output [7:0] GPIO_0;
//////////// uart //////////
// 115200, data bit:8, stop bit: 1, Parity: none
output tx_out;
input rx_in;
////////////// 2x13 GPIO Header //////////
//inout [12:0] GPIO_2;
//input [2:0] GPIO_2_IN;
//
////////////// GPIO_0, GPIO_0 connect to GPIO Default //////////
//inout [33:0] GPIO_0;
//input [1:0] GPIO_0_IN;
//
////////////// GPIO_1, GPIO_1 connect to GPIO Default //////////
//inout [33:0] GPIO_1;
//input [1:0] GPIO_1_IN;
////=======================================================
//// REG/WIRE declarations
////=======================================================
//wire reset_n;
//wire select_i2c_clk;
//wire i2c_clk;
//wire spi_clk;
//=======================================================
// Structural coding
//=======================================================
assign reset_n = 1'b1;
NIOS_Sys u0(
.led_external_connection_export (LED), // led_external_connection.export
.sdram_wire_addr (DRAM_ADDR), // sdram_wire.addr
.sdram_wire_ba (DRAM_BA), // .ba
.sdram_wire_cas_n (DRAM_CAS_N), // .cas_n
.sdram_wire_cke (DRAM_CKE), // .cke
.sdram_wire_cs_n (DRAM_CS_N), // .cs_n
.sdram_wire_dq (DRAM_DQ), // .dq
.sdram_wire_dqm (DRAM_DQM), // .dqm
.sdram_wire_ras_n (DRAM_RAS_N), // .ras_n
.sdram_wire_we_n (DRAM_WE_N), // .we_n
.key_external_connection_export (KEY), // key_external_connection.export
.sw_external_connection_export (SW), // sw_external_connection.export
.reset_reset_n (reset_n), // reset.reset_n
.altpll_0_c1_clk (DRAM_CLK), // altpll_0_c1.clk
.clk_clk (CLOCK_50),
.ultrasound0_conduit_end_feedback_in (U0_F), // ultrasound0_conduit_end.feedback_in
.ultrasound0_conduit_end_trigger_out (U0_T), // .trigger_out
.ultrasound1_conduit_end_feedback_in (U1_F), // ultrasound1_conduit_end.feedback_in
.ultrasound1_conduit_end_trigger_out (U1_T), // .trigger_out
.adc_spi_read_conduit_end_OUT (ADC_SADDR), // adc_spi_read_conduit_end.OUT
.adc_spi_read_conduit_end_IN (ADC_SDAT), // .IN
.adc_spi_read_conduit_end_CS_n (ADC_CS_N), // .CS_n
.adc_spi_read_conduit_end_CLK (ADC_SCLK), // .CLK
.pwm0_conduit_end_pwm1 (PWM0Ch0), // pwm0_conduit_end.pwm1
.pwm0_conduit_end_pwm2 (PWM0Ch1), // .pwm2
.pwm1_conduit_end_pwm1 (PWM1Ch0), // pwm1_conduit_end.pwm1
.pwm1_conduit_end_pwm2 (PWM1Ch1), // .pwm2
.encoder0_conduit_end_export (Encoder0), // encoder0_conduit_end.export
.encoder1_conduit_end_export (Encoder1), // encoder1_conduit_end.export
.pio_0_external_connection_export (GPIO_0), // pio_0_external_connection.export
.uart_0_external_connection_rxd (rx_in), // uart_0_external_connection.rxd
.uart_0_external_connection_txd (tx_out), // .txd
.ultrasound2_conduit_end_feedback_in (U2_F), // ultrasound2_conduit_end.feedback_in
.ultrasound2_conduit_end_trigger_out (U2_T), // .trigger_out
.ultrasound3_conduit_end_feedback_in (U3_F), // ultrasound3_conduit_end.feedback_in
.ultrasound3_conduit_end_trigger_out (U3_T), // .trigger_out
.ultrasound5_conduit_end_feedback_in (U5_F), // ultrasound5_conduit_end.feedback_in
.ultrasound5_conduit_end_trigger_out (U5_T), // .trigger_out
.pwm2_conduit_end_pwm1 (PWM2Ch0), // pwm2_conduit_end.pwm1
.pwm2_conduit_end_pwm2 (PWM2Ch1), // .pwm2
.pwm3_conduit_end_pwm1 (PWM3Ch0), // pwm3_conduit_end.pwm1
.pwm3_conduit_end_pwm2 (PWM3Ch1), // .pwm2
.ultrasound4_conduit_end_feedback_in (U4_F), // ultrasound4_conduit_end.feedback_in
.ultrasound4_conduit_end_trigger_out (U4_T), //
.pio_1_external_connection_export(PIO1)
);
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Wed May 24 17:28:31 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top system_vga_buffer_1_0 -prefix
// system_vga_buffer_1_0_ system_vga_buffer_1_0_stub.v
// Design : system_vga_buffer_1_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "vga_buffer,Vivado 2016.4" *)
module system_vga_buffer_1_0(clk_w, clk_r, wen, x_addr_w, y_addr_w, x_addr_r,
y_addr_r, data_w, data_r)
/* synthesis syn_black_box black_box_pad_pin="clk_w,clk_r,wen,x_addr_w[9:0],y_addr_w[9:0],x_addr_r[9:0],y_addr_r[9:0],data_w[23:0],data_r[23:0]" */;
input clk_w;
input clk_r;
input wen;
input [9:0]x_addr_w;
input [9:0]y_addr_w;
input [9:0]x_addr_r;
input [9:0]y_addr_r;
input [23:0]data_w;
output [23:0]data_r;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__ISOLATCH_BLACKBOX_V
`define SKY130_FD_SC_LP__ISOLATCH_BLACKBOX_V
/**
* isolatch: ????.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__isolatch (
Q ,
D ,
SLEEP_B
);
output Q ;
input D ;
input SLEEP_B;
// Voltage supply signals
supply1 KAPWR;
supply1 VPWR ;
supply0 VGND ;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__ISOLATCH_BLACKBOX_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLXBP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__DLXBP_FUNCTIONAL_PP_V
/**
* dlxbp: Delay latch, non-inverted enable, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_p_pp_pg_n/sky130_fd_sc_lp__udp_dlatch_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_lp__dlxbp (
Q ,
Q_N ,
D ,
GATE,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input D ;
input GATE;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire GATE_delayed;
wire D_delayed ;
// Delay Name Output Other arguments
sky130_fd_sc_lp__udp_dlatch$P_pp$PG$N `UNIT_DELAY dlatch0 (buf_Q , D, GATE, , VPWR, VGND);
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLXBP_FUNCTIONAL_PP_V
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: fifo.v
// Megafunction Name(s):
// scfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 15.1.0 Build 185 10/21/2015 SJ Lite Edition
// ************************************************************
//Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus Prime License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module fifo (
clock,
data,
rdreq,
wrreq,
empty,
full,
q,
usedw);
input clock;
input [15:0] data;
input rdreq;
input wrreq;
output empty;
output full;
output [15:0] q;
output [7:0] usedw;
wire sub_wire0;
wire sub_wire1;
wire [15:0] sub_wire2;
wire [7:0] sub_wire3;
wire empty = sub_wire0;
wire full = sub_wire1;
wire [15:0] q = sub_wire2[15:0];
wire [7:0] usedw = sub_wire3[7:0];
scfifo scfifo_component (
.clock (clock),
.data (data),
.rdreq (rdreq),
.wrreq (wrreq),
.empty (sub_wire0),
.full (sub_wire1),
.q (sub_wire2),
.usedw (sub_wire3),
.aclr (),
.almost_empty (),
.almost_full (),
.eccstatus (),
.sclr ());
defparam
scfifo_component.add_ram_output_register = "OFF",
scfifo_component.intended_device_family = "Cyclone V",
scfifo_component.lpm_numwords = 256,
scfifo_component.lpm_showahead = "ON",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 16,
scfifo_component.lpm_widthu = 8,
scfifo_component.overflow_checking = "ON",
scfifo_component.underflow_checking = "ON",
scfifo_component.use_eab = "ON";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "256"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "16"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "16"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "8"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]"
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL "full"
// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: usedw 0 0 8 0 OUTPUT NODEFVAL "usedw[7..0]"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
// Retrieval info: CONNECT: usedw 0 0 8 0 @usedw 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__AND2B_SYMBOL_V
`define SKY130_FD_SC_LS__AND2B_SYMBOL_V
/**
* and2b: 2-input AND, first input inverted.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__and2b (
//# {{data|Data Signals}}
input A_N,
input B ,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__AND2B_SYMBOL_V
|
module automatic_events3();
reg [1:0] Source;
initial begin
Source[0] = 1'b0;
forever begin
#20 Source[0] = 1'b1;
#20 Source[0] = 1'b0;
end
end
initial begin
Source[1] = 1'b0;
#15;
forever begin
#10 Source[1] = 1'bx;
#10 Source[1] = 1'b1;
#10 Source[1] = 1'bx;
#10 Source[1] = 1'b0;
end
end
task automatic ReportPosEdge0;
begin
@(posedge Source[0]);
$display("Time %4t : Source[0] rise", $time);
end
endtask
task automatic ReportNegEdge0;
begin
@(negedge Source[0]);
$display("Time %4t : Source[0] fall", $time);
end
endtask
task automatic ReportAnyEdge0;
time t;
begin
@(Source[0]) t = $time;
#1 $display("Time %4t : Source[0] edge", t);
end
endtask
task automatic ReportPosEdge1;
begin
@(posedge Source[1]);
$display("Time %4t : Source[1] rise", $time);
end
endtask
task automatic ReportNegEdge1;
begin
@(negedge Source[1]);
$display("Time %4t : Source[1] fall", $time);
end
endtask
task automatic ReportAnyEdge1;
time t;
begin
@(Source[1]) t = $time;
#1 $display("Time %4t : Source[1] edge", t);
end
endtask
initial begin
#1;
fork
repeat(2) ReportPosEdge0;
repeat(2) ReportNegEdge0;
repeat(4) ReportAnyEdge0;
repeat(4) ReportPosEdge1;
repeat(4) ReportNegEdge1;
repeat(8) ReportAnyEdge1;
join
$finish;
end
endmodule
|
//////////////////////////////////////////////////////////////////
// //
// Erasure computation and hard error correction controller. //
// //
// Description //
// This module is able to correct one hard error in case two //
// errors were produced in the same word. //
// With this module, the EDC device will be able to correct //
// up to two failures meanwhile at least one of them is a hard //
// error (i.e. it is not able to correct two soft errors). //
// //
// Author(s): //
// - Jorge Bellon Castro, [email protected] //
// - Carlos Diaz Suarez, [email protected] //
// //
//////////////////////////////////////////////////////////////////
// //
// Copyright (C) 2010 Authors and OPENCORES.ORG //
// //
// This source file may be used and distributed without //
// restriction provided that this copyright statement is not //
// removed from the file and that any derivative work contains //
// the original copyright notice and the associated disclaimer. //
// //
// This source file is free software; you can redistribute it //
// and/or modify it under the terms of the GNU Lesser General //
// Public License as published by the Free Software Foundation; //
// either version 2.1 of the License, or (at your option) any //
// later version. //
// //
// This source is distributed in the hope that it will be //
// useful, but WITHOUT ANY WARRANTY; without even the implied //
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
// PURPOSE. See the GNU Lesser General Public License for more //
// details. //
// //
// You should have received a copy of the GNU Lesser General //
// Public License along with this source; if not, download it //
// from http://www.opencores.org/lgpl.shtml //
// //
//////////////////////////////////////////////////////////////////
module edc_erasure (
input i_clk,
input i_rst, // (from bus) reset signal
input i_sel, // (from bus) select signal
input i_we, // (from bus) write enabled
input i_err, // (from corrector) error detected
input i_ue, // (from corrector) uncorrected error signal
input [31:0] i_addr,// (from bus)
input [31:0] i_bus_data,// (from bus)
input [31:0] i_mem_data,// (from data mem)
input i_mem_ack, // ( AND(data mem ack, ecc mem ack) )
output reg [31:0] o_bus_data,//(to bus)
output reg [31:0] o_mem_data,//(to data mem)
output reg o_mem_sel, //(to data mem)
output reg o_mem_we, //(to data mem)
output reg [7:0] o_mem_ecc, // maybe unused
output reg o_err, //(to bus)
output reg o_ack //(to bus)
);
parameter SIZE = 4;
parameter IDLE = 4'd0;
parameter WRITE = 4'd1;
parameter READ = 4'd2;
parameter WRITE_COMPLEMENT = 4'd3;
parameter WRITE_COMPLEMENT_DONE = 4'd4;// we need another step to bring o_mem_sel down and up again
parameter READ_COMPLEMENT = 4'd5;
parameter READ_COMPLEMENT_DONE = 4'd6;// we need another step to bring o_mem_sel down and up again
parameter WRITE_CORRECTED = 4'd7;
parameter WRITE_DONE = 4'd8;
parameter READ_DONE = 4'd9;
parameter ERROR = 4'd10;
//--------- Internal variables ---------
reg [SIZE-1:0] current_state;
wire [SIZE-1:0] next_state;
//--------- Code starts here ---------
assign next_state = fsm_function(current_state, i_sel, o_mem_sel, i_we, i_mem_ack, i_err, i_ue);
//--------- State combinational logic ---------
function [SIZE-1:0] fsm_function;
input [SIZE-1:0] state;
input i_start;
input i_done;
input i_we;
input i_ack;
input i_err;
input i_ue;
case(state)
// 0
IDLE: if (i_start == 1'b1) begin
if (i_we == 1'b1) begin
fsm_function = WRITE;
end else begin
fsm_function = READ;
end
end else begin
fsm_function = IDLE;
end
// 1
WRITE: if (i_ack == 1'b1) begin
fsm_function = WRITE_DONE;// go back to idle when finished
end else begin // still waiting for memory...
fsm_function = WRITE;
end
// 2
READ: if (i_ack == 1'b1) begin
if (i_ue == 1'b0) begin// meanwhile no errors... go back to idle
fsm_function = READ_DONE;
end else begin
fsm_function = WRITE_COMPLEMENT;
end
end else begin // still waiting...
fsm_function = READ;
end
// 3
WRITE_COMPLEMENT: if (i_ack == 1'b1) begin
fsm_function = WRITE_COMPLEMENT_DONE;
end else begin // still waiting...
fsm_function = WRITE_COMPLEMENT;
end
// 4
WRITE_COMPLEMENT_DONE: if (i_done == 1'b0 ) begin
fsm_function = READ_COMPLEMENT;
end else begin
fsm_function = WRITE_COMPLEMENT_DONE;
end
// 5
READ_COMPLEMENT: if (i_ack == 1'b1) begin
if (i_ue == 1'b1) begin
fsm_function = ERROR;// uncorrectable error
end else begin
fsm_function = READ_COMPLEMENT_DONE;
end
end else begin // still waiting...
fsm_function = READ_COMPLEMENT;
end
// 6
READ_COMPLEMENT_DONE: if (i_done == 1'b0 ) begin
fsm_function = WRITE_CORRECTED;
end else begin
fsm_function = READ_COMPLEMENT_DONE;
end
// 7
WRITE_CORRECTED: if (i_ack == 1'b1) begin
fsm_function = READ_DONE;
end else begin // still waiting...
fsm_function = WRITE_CORRECTED;
end
// 8
WRITE_DONE:
fsm_function = IDLE;
// 9
READ_DONE:
fsm_function = IDLE;
// 10
ERROR:
fsm_function = ERROR; // hangs until controller is reset
default:
fsm_function = IDLE;
endcase
endfunction
//--------- Sequential logic ---------
always @ (posedge i_clk)
begin : FSM_SEQ
if(i_rst == 1'b1) begin
current_state <= IDLE;
end else begin
current_state <= next_state;
end
end
//--------- Output logic ---------
//
//reg [31:0] o_bus_data,//(to bus)
//reg [31:0] o_mem_data,//(to data mem)
//reg o_mem_sel, //(to data mem)
//wire o_mem_we, //(to data mem)
//reg [7:0] o_mem_ecc, // maybe unused
//reg o_err, //(to bus)
//reg o_ack //(to bus)
reg [31:0] word;
always @ (posedge i_clk)
begin : OUTPUT_LOGIC
if (i_rst == 1'b1) begin
o_bus_data <= 'b0;
o_mem_data <= 'b0;
o_mem_sel <= 'b0;
o_mem_we <= 'b0;
o_mem_ecc <= 'b0;
o_err <= 'b0;
o_ack <= 'b0;
end else begin
case(current_state)
IDLE: begin
o_err <= 'b0;
end
WRITE: begin
o_ack <= 'b0;
o_mem_sel <= 1'b1;
o_mem_we <= 1'b1;
o_mem_data <= i_bus_data;
end
READ: begin
o_ack <= 'b0;
o_mem_sel <= 1'b1;
o_mem_we <= 1'b0;
word <= i_mem_data;// save data in a temp register
end
WRITE_COMPLEMENT: begin
o_mem_sel <= 1'b1;
o_mem_we <= 1'b1;
o_mem_data <= ~word;// write the complement of the data in memory
//o_mem_ecc = ~ecc;// our parity check matrix ECC doesnt change with complemented words
end
WRITE_COMPLEMENT_DONE: begin
o_mem_sel = 1'b0;
end
READ_COMPLEMENT: begin
o_mem_sel <= 1'b1;
o_mem_we <= 1'b0;
word <= ~i_mem_data;// write the complement of the data in memory
//ecc_compl <= ~i_mem_ecc;// our parity check matrix ECC doesnt change with complemented words
end
READ_COMPLEMENT_DONE: begin
o_mem_sel = 1'b0;
end
WRITE_CORRECTED: begin
o_mem_sel <= 1'b1;
o_mem_we <= 1'b1;
o_mem_data <= word;
end
WRITE_DONE: begin
o_mem_sel = 1'b0;
end
READ_DONE: begin
o_mem_sel = 1'b0;
o_bus_data <= word;
o_ack <= 1'b1;
end
endcase
end
end // End Of Block OUTPUT_LOGIC
endmodule
|
`include "Definition.v"
`include "ProcessProperty.v"
// 1. input and output should be combined together into inout
// 2. look up table should be research more elaborate skill
module CTC
(
input Clock,
input Reset,
input[ `size_char - 1 : 0 ]R,
input[ `size_char - 1 : 0 ]G,
input[ `size_char - 1 : 0 ]B,
output[ `size_char - 1 : 0 ]R_out,
output[ `size_char - 1 : 0 ]G_out,
output[ `size_char - 1 : 0 ]B_out
);
// scale rgb
reg[ `size_int - 1 : 0 ]ScaleR;
reg[ `size_int - 1 : 0 ]ScaleG;
reg[ `size_int - 1 : 0 ]ScaleB;
reg[ `size_int - 1 : 0 ]ScaleRTemp;
reg[ `size_int - 1 : 0 ]ScaleGTemp;
reg[ `size_int - 1 : 0 ]ScaleBTemp;
// counter
integer PixelCount;
// CTC
reg[ `size_int - 1 : 0 ]WBR;
reg[ `size_int - 1 : 0 ]WBG;
reg[ `size_int - 1 : 0 ]WBB;
reg[ `size_int - 1 : 0 ]RFactor;
reg[ `size_int - 1 : 0 ]BFactor;
reg[ `size_int + `size_int - 1 : 0 ]RLongTotal;
reg[ `size_int + `size_int - 1 : 0 ]GLongTotal;
reg[ `size_int + `size_int - 1 : 0 ]BLongTotal;
reg[ `size_int - 1 : 0 ]RTotal;
reg[ `size_int - 1 : 0 ]GTotal;
reg[ `size_int - 1 : 0 ]BTotal;
// divider usage
reg[ `size_int - 1 : 0 ]GRIndex;
reg[ `size_int - 1 : 0 ]GBIndex;
reg[ 1 : 0 ]State;
reg[ 1 : 0 ]NextState;
// state declaration
parameter InitialState = 0; // initialization
parameter WBFactorState = 1; // calculate white balance factor
parameter ProcessState = 2;
// sequential state register
always@( posedge Clock )
begin
if( Reset == 1 )
State = InitialState;
else
State = NextState;
end
////////////////
// read raw data
always@( posedge Clock )
begin
ScaleR = R << `ScaleBit;
ScaleG = G << `ScaleBit;
ScaleB = B << `ScaleBit;
end
// next state and outputs, combinational always block
always@( posedge Clock )
begin
case( State )
/////////////////
// initialization
InitialState :
begin
RLongTotal = 0;
GLongTotal = 0;
BLongTotal = 0;
PixelCount = 0;
NextState = WBFactorState;
end
/////////////////////////////////
// calculate white balance factor
WBFactorState :
begin
if( PixelCount == `SumPixel )
begin
NextState = ProcessState;
PixelCount = 0;
end
else
begin
PixelCount = PixelCount + 1;
RLongTotal = RLongTotal + ScaleR;
GLongTotal = GLongTotal + ScaleG;
BLongTotal = BLongTotal + ScaleB;
RTotal = RLongTotal >> `ScaleHalfBit;
GTotal = GLongTotal >> `ScaleHalfBit;
BTotal = BLongTotal >> `ScaleHalfBit;
// GR ratio, scale = 16
GRIndex = Divider( GTotal, RTotal >> `ScaleHalfBit );
// GB ratio, scale = 16
GBIndex = Divider( GTotal, BTotal >> `ScaleHalfBit );
if( ( GRIndex >= 16 ) && ( GRIndex <= 40 ) )
GRIndex = GRIndex - 16;
else if( GRIndex < 16 )
GRIndex = 0;
else
GRIndex = 23;
if( ( GBIndex >= 16 ) && ( GBIndex <= 40 ) )
GBIndex = GBIndex - 16;
else if( GBIndex < 16 )
GBIndex = 0;
else
GBIndex = 23;
LUTCTCFactor( GRIndex * 24 + GBIndex, RFactor, BFactor );
// RFactor = ( RFactor * `WBRCorrection ) >> `ScaleBit;
// BFactor = ( BFactor * `WBBCorrection ) >> `ScaleBit;
end
end
endcase
end
assign R_out = WBR >> `ScaleBit;
assign G_out = WBG >> `ScaleBit;
assign B_out = WBB >> `ScaleBit;
//////////////////////////////////////////////////////////////////
function[ `size_int - 1 : 0 ]Divider
(
input[ `size_int - 1 : 0 ]Dividend,
input[ `size_int - 1 : 0 ]Divisor
);
// counter
integer i;
reg[ `size_int - 1 : 0 ]Quotient; // Quotient
reg[ `size_int - 1 : 0 ]Remainder; // Remainder
reg[ `size_int : 0 ]Partial;
reg[ `size_int - 1 : 0 ]div;
begin
Quotient = Dividend;
div = Divisor;
Partial = { `size_int'h00, 1'b0 };
for( i = 0; i < `size_int; i = i + 1 )
begin
Partial = { Partial[ `size_int - 1 : 0 ], Quotient[ `size_int - 1 ] };
Quotient = { Quotient[ `size_int - 2 : 0 ], 1'b0 };
Partial = Partial + { ~{ 1'b0, div } + 1'b1 }; // subtraction
if( Partial[ `size_int ] == 1'b0 )
Quotient[ 0 ] = 1'b1;
else
begin
Partial = Partial + div;
Quotient[ 0 ] = 1'b0;
end
end
Remainder = Partial[ `size_int - 1 : 0 ];
//to round up or down
if( Remainder * 10 >= Divisor * 5 )
Divider = Quotient + 1;
else
Divider = Quotient;
end
endfunction
// ratio = 1.0 ~ 2.5
// scale = 16
// ratio * 16 = 16 ~ 40
// every layer size = 40 - 16 = 24
// every step : ( 2.5 - 1.0 ) / 24 = 0.0625
// it needed to be modified
task LUTCTCFactor
(
input[ `size_int - 1 : 0 ]Index,
output[ `size_int - 1 : 0 ]RFactor,
output[ `size_int - 1 : 0 ]BFactor
);
begin
case( Index )
0 : begin RFactor = 417; BFactor = 414; end // GR = 1.00, GB = 1.00
1 : begin RFactor = 405; BFactor = 427; end // GR = 1.00, GB = 1.06
2 : begin RFactor = 394; BFactor = 440; end // GR = 1.00, GB = 1.12
3 : begin RFactor = 383; BFactor = 452; end // GR = 1.00, GB = 1.19
4 : begin RFactor = 373; BFactor = 464; end // GR = 1.00, GB = 1.25
5 : begin RFactor = 364; BFactor = 476; end // GR = 1.00, GB = 1.31
6 : begin RFactor = 356; BFactor = 487; end // GR = 1.00, GB = 1.38
7 : begin RFactor = 348; BFactor = 498; end // GR = 1.00, GB = 1.44
8 : begin RFactor = 341; BFactor = 509; end // GR = 1.00, GB = 1.50
9 : begin RFactor = 334; BFactor = 520; end // GR = 1.00, GB = 1.56
10 : begin RFactor = 327; BFactor = 530; end // GR = 1.00, GB = 1.62
11 : begin RFactor = 321; BFactor = 540; end // GR = 1.00, GB = 1.69
12 : begin RFactor = 315; BFactor = 551; end // GR = 1.00, GB = 1.75
13 : begin RFactor = 310; BFactor = 560; end // GR = 1.00, GB = 1.81
14 : begin RFactor = 305; BFactor = 570; end // GR = 1.00, GB = 1.88
15 : begin RFactor = 300; BFactor = 580; end // GR = 1.00, GB = 1.94
16 : begin RFactor = 295; BFactor = 589; end // GR = 1.00, GB = 2.00
17 : begin RFactor = 291; BFactor = 599; end // GR = 1.00, GB = 2.06
18 : begin RFactor = 286; BFactor = 608; end // GR = 1.00, GB = 2.12
19 : begin RFactor = 282; BFactor = 617; end // GR = 1.00, GB = 2.19
20 : begin RFactor = 278; BFactor = 626; end // GR = 1.00, GB = 2.25
21 : begin RFactor = 274; BFactor = 634; end // GR = 1.00, GB = 2.31
22 : begin RFactor = 271; BFactor = 643; end // GR = 1.00, GB = 2.38
23 : begin RFactor = 267; BFactor = 652; end // GR = 1.00, GB = 2.44
24 : begin RFactor = 430; BFactor = 402; end // GR = 1.06, GB = 1.00
25 : begin RFactor = 417; BFactor = 414; end // GR = 1.06, GB = 1.06
26 : begin RFactor = 405; BFactor = 427; end // GR = 1.06, GB = 1.12
27 : begin RFactor = 395; BFactor = 438; end // GR = 1.06, GB = 1.19
28 : begin RFactor = 385; BFactor = 450; end // GR = 1.06, GB = 1.25
29 : begin RFactor = 375; BFactor = 461; end // GR = 1.06, GB = 1.31
30 : begin RFactor = 367; BFactor = 472; end // GR = 1.06, GB = 1.38
31 : begin RFactor = 359; BFactor = 483; end // GR = 1.06, GB = 1.44
32 : begin RFactor = 351; BFactor = 494; end // GR = 1.06, GB = 1.50
33 : begin RFactor = 344; BFactor = 504; end // GR = 1.06, GB = 1.56
34 : begin RFactor = 337; BFactor = 514; end // GR = 1.06, GB = 1.62
35 : begin RFactor = 331; BFactor = 524; end // GR = 1.06, GB = 1.69
36 : begin RFactor = 325; BFactor = 534; end // GR = 1.06, GB = 1.75
37 : begin RFactor = 319; BFactor = 544; end // GR = 1.06, GB = 1.81
38 : begin RFactor = 314; BFactor = 553; end // GR = 1.06, GB = 1.88
39 : begin RFactor = 309; BFactor = 562; end // GR = 1.06, GB = 1.94
40 : begin RFactor = 304; BFactor = 572; end // GR = 1.06, GB = 2.00
41 : begin RFactor = 299; BFactor = 581; end // GR = 1.06, GB = 2.06
42 : begin RFactor = 295; BFactor = 590; end // GR = 1.06, GB = 2.12
43 : begin RFactor = 291; BFactor = 598; end // GR = 1.06, GB = 2.19
44 : begin RFactor = 287; BFactor = 607; end // GR = 1.06, GB = 2.25
45 : begin RFactor = 283; BFactor = 615; end // GR = 1.06, GB = 2.31
46 : begin RFactor = 279; BFactor = 624; end // GR = 1.06, GB = 2.38
47 : begin RFactor = 275; BFactor = 632; end // GR = 1.06, GB = 2.44
48 : begin RFactor = 442; BFactor = 390; end // GR = 1.12, GB = 1.00
49 : begin RFactor = 429; BFactor = 403; end // GR = 1.12, GB = 1.06
50 : begin RFactor = 417; BFactor = 415; end // GR = 1.12, GB = 1.12
51 : begin RFactor = 406; BFactor = 426; end // GR = 1.12, GB = 1.19
52 : begin RFactor = 396; BFactor = 437; end // GR = 1.12, GB = 1.25
53 : begin RFactor = 386; BFactor = 448; end // GR = 1.12, GB = 1.31
54 : begin RFactor = 377; BFactor = 459; end // GR = 1.12, GB = 1.38
55 : begin RFactor = 369; BFactor = 470; end // GR = 1.12, GB = 1.44
56 : begin RFactor = 361; BFactor = 480; end // GR = 1.12, GB = 1.50
57 : begin RFactor = 354; BFactor = 490; end // GR = 1.12, GB = 1.56
58 : begin RFactor = 347; BFactor = 500; end // GR = 1.12, GB = 1.62
59 : begin RFactor = 340; BFactor = 510; end // GR = 1.12, GB = 1.69
60 : begin RFactor = 334; BFactor = 519; end // GR = 1.12, GB = 1.75
61 : begin RFactor = 328; BFactor = 528; end // GR = 1.12, GB = 1.81
62 : begin RFactor = 323; BFactor = 538; end // GR = 1.12, GB = 1.88
63 : begin RFactor = 318; BFactor = 547; end // GR = 1.12, GB = 1.94
64 : begin RFactor = 313; BFactor = 555; end // GR = 1.12, GB = 2.00
65 : begin RFactor = 308; BFactor = 564; end // GR = 1.12, GB = 2.06
66 : begin RFactor = 303; BFactor = 573; end // GR = 1.12, GB = 2.12
67 : begin RFactor = 299; BFactor = 581; end // GR = 1.12, GB = 2.19
68 : begin RFactor = 295; BFactor = 590; end // GR = 1.12, GB = 2.25
69 : begin RFactor = 291; BFactor = 598; end // GR = 1.12, GB = 2.31
70 : begin RFactor = 287; BFactor = 606; end // GR = 1.12, GB = 2.38
71 : begin RFactor = 283; BFactor = 614; end // GR = 1.12, GB = 2.44
72 : begin RFactor = 454; BFactor = 380; end // GR = 1.19, GB = 1.00
73 : begin RFactor = 441; BFactor = 392; end // GR = 1.19, GB = 1.06
74 : begin RFactor = 428; BFactor = 403; end // GR = 1.19, GB = 1.12
75 : begin RFactor = 417; BFactor = 415; end // GR = 1.19, GB = 1.19
76 : begin RFactor = 406; BFactor = 426; end // GR = 1.19, GB = 1.25
77 : begin RFactor = 396; BFactor = 436; end // GR = 1.19, GB = 1.31
78 : begin RFactor = 387; BFactor = 447; end // GR = 1.19, GB = 1.38
79 : begin RFactor = 379; BFactor = 457; end // GR = 1.19, GB = 1.44
80 : begin RFactor = 371; BFactor = 467; end // GR = 1.19, GB = 1.50
81 : begin RFactor = 363; BFactor = 477; end // GR = 1.19, GB = 1.56
82 : begin RFactor = 356; BFactor = 486; end // GR = 1.19, GB = 1.62
83 : begin RFactor = 350; BFactor = 496; end // GR = 1.19, GB = 1.69
84 : begin RFactor = 343; BFactor = 505; end // GR = 1.19, GB = 1.75
85 : begin RFactor = 337; BFactor = 514; end // GR = 1.19, GB = 1.81
86 : begin RFactor = 332; BFactor = 523; end // GR = 1.19, GB = 1.88
87 : begin RFactor = 326; BFactor = 532; end // GR = 1.19, GB = 1.94
88 : begin RFactor = 321; BFactor = 541; end // GR = 1.19, GB = 2.00
89 : begin RFactor = 316; BFactor = 549; end // GR = 1.19, GB = 2.06
90 : begin RFactor = 312; BFactor = 558; end // GR = 1.19, GB = 2.12
91 : begin RFactor = 307; BFactor = 566; end // GR = 1.19, GB = 2.19
92 : begin RFactor = 303; BFactor = 574; end // GR = 1.19, GB = 2.25
93 : begin RFactor = 299; BFactor = 582; end // GR = 1.19, GB = 2.31
94 : begin RFactor = 295; BFactor = 590; end // GR = 1.19, GB = 2.38
95 : begin RFactor = 291; BFactor = 598; end // GR = 1.19, GB = 2.44
96 : begin RFactor = 466; BFactor = 370; end // GR = 1.25, GB = 1.00
97 : begin RFactor = 452; BFactor = 382; end // GR = 1.25, GB = 1.06
98 : begin RFactor = 439; BFactor = 393; end // GR = 1.25, GB = 1.12
99 : begin RFactor = 428; BFactor = 404; end // GR = 1.25, GB = 1.19
100 : begin RFactor = 417; BFactor = 415; end // GR = 1.25, GB = 1.25
101 : begin RFactor = 407; BFactor = 425; end // GR = 1.25, GB = 1.31
102 : begin RFactor = 397; BFactor = 436; end // GR = 1.25, GB = 1.38
103 : begin RFactor = 389; BFactor = 445; end // GR = 1.25, GB = 1.44
104 : begin RFactor = 380; BFactor = 455; end // GR = 1.25, GB = 1.50
105 : begin RFactor = 373; BFactor = 465; end // GR = 1.25, GB = 1.56
106 : begin RFactor = 365; BFactor = 474; end // GR = 1.25, GB = 1.62
107 : begin RFactor = 359; BFactor = 483; end // GR = 1.25, GB = 1.69
108 : begin RFactor = 352; BFactor = 492; end // GR = 1.25, GB = 1.75
109 : begin RFactor = 346; BFactor = 501; end // GR = 1.25, GB = 1.81
110 : begin RFactor = 340; BFactor = 510; end // GR = 1.25, GB = 1.88
111 : begin RFactor = 335; BFactor = 519; end // GR = 1.25, GB = 1.94
112 : begin RFactor = 329; BFactor = 527; end // GR = 1.25, GB = 2.00
113 : begin RFactor = 324; BFactor = 535; end // GR = 1.25, GB = 2.06
114 : begin RFactor = 319; BFactor = 543; end // GR = 1.25, GB = 2.12
115 : begin RFactor = 315; BFactor = 552; end // GR = 1.25, GB = 2.19
116 : begin RFactor = 310; BFactor = 559; end // GR = 1.25, GB = 2.25
117 : begin RFactor = 306; BFactor = 567; end // GR = 1.25, GB = 2.31
118 : begin RFactor = 302; BFactor = 575; end // GR = 1.25, GB = 2.38
119 : begin RFactor = 298; BFactor = 583; end // GR = 1.25, GB = 2.44
120 : begin RFactor = 477; BFactor = 361; end // GR = 1.31, GB = 1.00
121 : begin RFactor = 463; BFactor = 373; end // GR = 1.31, GB = 1.06
122 : begin RFactor = 450; BFactor = 384; end // GR = 1.31, GB = 1.12
123 : begin RFactor = 438; BFactor = 394; end // GR = 1.31, GB = 1.19
124 : begin RFactor = 427; BFactor = 405; end // GR = 1.31, GB = 1.25
125 : begin RFactor = 417; BFactor = 415; end // GR = 1.31, GB = 1.31
126 : begin RFactor = 407; BFactor = 425; end // GR = 1.31, GB = 1.38
127 : begin RFactor = 398; BFactor = 435; end // GR = 1.31, GB = 1.44
128 : begin RFactor = 390; BFactor = 444; end // GR = 1.31, GB = 1.50
129 : begin RFactor = 382; BFactor = 454; end // GR = 1.31, GB = 1.56
130 : begin RFactor = 374; BFactor = 463; end // GR = 1.31, GB = 1.62
131 : begin RFactor = 367; BFactor = 472; end // GR = 1.31, GB = 1.69
132 : begin RFactor = 361; BFactor = 480; end // GR = 1.31, GB = 1.75
133 : begin RFactor = 354; BFactor = 489; end // GR = 1.31, GB = 1.81
134 : begin RFactor = 348; BFactor = 498; end // GR = 1.31, GB = 1.88
135 : begin RFactor = 343; BFactor = 506; end // GR = 1.31, GB = 1.94
136 : begin RFactor = 337; BFactor = 514; end // GR = 1.31, GB = 2.00
137 : begin RFactor = 332; BFactor = 522; end // GR = 1.31, GB = 2.06
138 : begin RFactor = 327; BFactor = 530; end // GR = 1.31, GB = 2.12
139 : begin RFactor = 323; BFactor = 538; end // GR = 1.31, GB = 2.19
140 : begin RFactor = 318; BFactor = 546; end // GR = 1.31, GB = 2.25
141 : begin RFactor = 314; BFactor = 554; end // GR = 1.31, GB = 2.31
142 : begin RFactor = 310; BFactor = 561; end // GR = 1.31, GB = 2.38
143 : begin RFactor = 306; BFactor = 569; end // GR = 1.31, GB = 2.44
144 : begin RFactor = 488; BFactor = 353; end // GR = 1.38, GB = 1.00
145 : begin RFactor = 474; BFactor = 364; end // GR = 1.38, GB = 1.06
146 : begin RFactor = 460; BFactor = 375; end // GR = 1.38, GB = 1.12
147 : begin RFactor = 448; BFactor = 385; end // GR = 1.38, GB = 1.19
148 : begin RFactor = 437; BFactor = 396; end // GR = 1.38, GB = 1.25
149 : begin RFactor = 426; BFactor = 406; end // GR = 1.38, GB = 1.31
150 : begin RFactor = 416; BFactor = 415; end // GR = 1.38, GB = 1.38
151 : begin RFactor = 407; BFactor = 425; end // GR = 1.38, GB = 1.44
152 : begin RFactor = 399; BFactor = 434; end // GR = 1.38, GB = 1.50
153 : begin RFactor = 391; BFactor = 443; end // GR = 1.38, GB = 1.56
154 : begin RFactor = 383; BFactor = 452; end // GR = 1.38, GB = 1.62
155 : begin RFactor = 376; BFactor = 461; end // GR = 1.38, GB = 1.69
156 : begin RFactor = 369; BFactor = 469; end // GR = 1.38, GB = 1.75
157 : begin RFactor = 363; BFactor = 478; end // GR = 1.38, GB = 1.81
158 : begin RFactor = 356; BFactor = 486; end // GR = 1.38, GB = 1.88
159 : begin RFactor = 351; BFactor = 494; end // GR = 1.38, GB = 1.94
160 : begin RFactor = 345; BFactor = 502; end // GR = 1.38, GB = 2.00
161 : begin RFactor = 340; BFactor = 510; end // GR = 1.38, GB = 2.06
162 : begin RFactor = 335; BFactor = 518; end // GR = 1.38, GB = 2.12
163 : begin RFactor = 330; BFactor = 526; end // GR = 1.38, GB = 2.19
164 : begin RFactor = 325; BFactor = 533; end // GR = 1.38, GB = 2.25
165 : begin RFactor = 321; BFactor = 541; end // GR = 1.38, GB = 2.31
166 : begin RFactor = 317; BFactor = 548; end // GR = 1.38, GB = 2.38
167 : begin RFactor = 313; BFactor = 556; end // GR = 1.38, GB = 2.44
168 : begin RFactor = 499; BFactor = 345; end // GR = 1.44, GB = 1.00
169 : begin RFactor = 484; BFactor = 356; end // GR = 1.44, GB = 1.06
170 : begin RFactor = 471; BFactor = 367; end // GR = 1.44, GB = 1.12
171 : begin RFactor = 458; BFactor = 377; end // GR = 1.44, GB = 1.19
172 : begin RFactor = 446; BFactor = 387; end // GR = 1.44, GB = 1.25
173 : begin RFactor = 436; BFactor = 397; end // GR = 1.44, GB = 1.31
174 : begin RFactor = 426; BFactor = 406; end // GR = 1.44, GB = 1.38
175 : begin RFactor = 416; BFactor = 415; end // GR = 1.44, GB = 1.44
176 : begin RFactor = 407; BFactor = 424; end // GR = 1.44, GB = 1.50
177 : begin RFactor = 399; BFactor = 433; end // GR = 1.44, GB = 1.56
178 : begin RFactor = 391; BFactor = 442; end // GR = 1.44, GB = 1.62
179 : begin RFactor = 384; BFactor = 451; end // GR = 1.44, GB = 1.69
180 : begin RFactor = 377; BFactor = 459; end // GR = 1.44, GB = 1.75
181 : begin RFactor = 371; BFactor = 467; end // GR = 1.44, GB = 1.81
182 : begin RFactor = 364; BFactor = 476; end // GR = 1.44, GB = 1.88
183 : begin RFactor = 358; BFactor = 484; end // GR = 1.44, GB = 1.94
184 : begin RFactor = 353; BFactor = 491; end // GR = 1.44, GB = 2.00
185 : begin RFactor = 347; BFactor = 499; end // GR = 1.44, GB = 2.06
186 : begin RFactor = 342; BFactor = 507; end // GR = 1.44, GB = 2.12
187 : begin RFactor = 337; BFactor = 514; end // GR = 1.44, GB = 2.19
188 : begin RFactor = 333; BFactor = 522; end // GR = 1.44, GB = 2.25
189 : begin RFactor = 328; BFactor = 529; end // GR = 1.44, GB = 2.31
190 : begin RFactor = 324; BFactor = 536; end // GR = 1.44, GB = 2.38
191 : begin RFactor = 320; BFactor = 543; end // GR = 1.44, GB = 2.44
192 : begin RFactor = 510; BFactor = 338; end // GR = 1.50, GB = 1.00
193 : begin RFactor = 494; BFactor = 349; end // GR = 1.50, GB = 1.06
194 : begin RFactor = 481; BFactor = 359; end // GR = 1.50, GB = 1.12
195 : begin RFactor = 468; BFactor = 369; end // GR = 1.50, GB = 1.19
196 : begin RFactor = 456; BFactor = 379; end // GR = 1.50, GB = 1.25
197 : begin RFactor = 445; BFactor = 388; end // GR = 1.50, GB = 1.31
198 : begin RFactor = 435; BFactor = 398; end // GR = 1.50, GB = 1.38
199 : begin RFactor = 425; BFactor = 407; end // GR = 1.50, GB = 1.44
200 : begin RFactor = 416; BFactor = 416; end // GR = 1.50, GB = 1.50
201 : begin RFactor = 408; BFactor = 424; end // GR = 1.50, GB = 1.56
202 : begin RFactor = 400; BFactor = 433; end // GR = 1.50, GB = 1.62
203 : begin RFactor = 392; BFactor = 441; end // GR = 1.50, GB = 1.69
204 : begin RFactor = 385; BFactor = 449; end // GR = 1.50, GB = 1.75
205 : begin RFactor = 378; BFactor = 458; end // GR = 1.50, GB = 1.81
206 : begin RFactor = 372; BFactor = 465; end // GR = 1.50, GB = 1.88
207 : begin RFactor = 366; BFactor = 473; end // GR = 1.50, GB = 1.94
208 : begin RFactor = 360; BFactor = 481; end // GR = 1.50, GB = 2.00
209 : begin RFactor = 355; BFactor = 489; end // GR = 1.50, GB = 2.06
210 : begin RFactor = 350; BFactor = 496; end // GR = 1.50, GB = 2.12
211 : begin RFactor = 344; BFactor = 503; end // GR = 1.50, GB = 2.19
212 : begin RFactor = 340; BFactor = 511; end // GR = 1.50, GB = 2.25
213 : begin RFactor = 335; BFactor = 518; end // GR = 1.50, GB = 2.31
214 : begin RFactor = 331; BFactor = 525; end // GR = 1.50, GB = 2.38
215 : begin RFactor = 326; BFactor = 532; end // GR = 1.50, GB = 2.44
216 : begin RFactor = 520; BFactor = 331; end // GR = 1.56, GB = 1.00
217 : begin RFactor = 505; BFactor = 342; end // GR = 1.56, GB = 1.06
218 : begin RFactor = 490; BFactor = 352; end // GR = 1.56, GB = 1.12
219 : begin RFactor = 477; BFactor = 362; end // GR = 1.56, GB = 1.19
220 : begin RFactor = 465; BFactor = 371; end // GR = 1.56, GB = 1.25
221 : begin RFactor = 454; BFactor = 380; end // GR = 1.56, GB = 1.31
222 : begin RFactor = 443; BFactor = 390; end // GR = 1.56, GB = 1.38
223 : begin RFactor = 434; BFactor = 398; end // GR = 1.56, GB = 1.44
224 : begin RFactor = 425; BFactor = 407; end // GR = 1.56, GB = 1.50
225 : begin RFactor = 416; BFactor = 416; end // GR = 1.56, GB = 1.56
226 : begin RFactor = 408; BFactor = 424; end // GR = 1.56, GB = 1.62
227 : begin RFactor = 400; BFactor = 432; end // GR = 1.56, GB = 1.69
228 : begin RFactor = 393; BFactor = 440; end // GR = 1.56, GB = 1.75
229 : begin RFactor = 386; BFactor = 448; end // GR = 1.56, GB = 1.81
230 : begin RFactor = 380; BFactor = 456; end // GR = 1.56, GB = 1.88
231 : begin RFactor = 373; BFactor = 464; end // GR = 1.56, GB = 1.94
232 : begin RFactor = 368; BFactor = 471; end // GR = 1.56, GB = 2.00
233 : begin RFactor = 362; BFactor = 479; end // GR = 1.56, GB = 2.06
234 : begin RFactor = 357; BFactor = 486; end // GR = 1.56, GB = 2.12
235 : begin RFactor = 351; BFactor = 493; end // GR = 1.56, GB = 2.19
236 : begin RFactor = 347; BFactor = 500; end // GR = 1.56, GB = 2.25
237 : begin RFactor = 342; BFactor = 507; end // GR = 1.56, GB = 2.31
238 : begin RFactor = 337; BFactor = 514; end // GR = 1.56, GB = 2.38
239 : begin RFactor = 333; BFactor = 521; end // GR = 1.56, GB = 2.44
240 : begin RFactor = 530; BFactor = 325; end // GR = 1.62, GB = 1.00
241 : begin RFactor = 514; BFactor = 335; end // GR = 1.62, GB = 1.06
242 : begin RFactor = 500; BFactor = 345; end // GR = 1.62, GB = 1.12
243 : begin RFactor = 486; BFactor = 354; end // GR = 1.62, GB = 1.19
244 : begin RFactor = 474; BFactor = 364; end // GR = 1.62, GB = 1.25
245 : begin RFactor = 463; BFactor = 373; end // GR = 1.62, GB = 1.31
246 : begin RFactor = 452; BFactor = 382; end // GR = 1.62, GB = 1.38
247 : begin RFactor = 442; BFactor = 391; end // GR = 1.62, GB = 1.44
248 : begin RFactor = 433; BFactor = 399; end // GR = 1.62, GB = 1.50
249 : begin RFactor = 424; BFactor = 408; end // GR = 1.62, GB = 1.56
250 : begin RFactor = 416; BFactor = 416; end // GR = 1.62, GB = 1.62
251 : begin RFactor = 408; BFactor = 424; end // GR = 1.62, GB = 1.69
252 : begin RFactor = 401; BFactor = 432; end // GR = 1.62, GB = 1.75
253 : begin RFactor = 394; BFactor = 440; end // GR = 1.62, GB = 1.81
254 : begin RFactor = 387; BFactor = 447; end // GR = 1.62, GB = 1.88
255 : begin RFactor = 381; BFactor = 455; end // GR = 1.62, GB = 1.94
256 : begin RFactor = 375; BFactor = 462; end // GR = 1.62, GB = 2.00
257 : begin RFactor = 369; BFactor = 469; end // GR = 1.62, GB = 2.06
258 : begin RFactor = 364; BFactor = 477; end // GR = 1.62, GB = 2.12
259 : begin RFactor = 358; BFactor = 484; end // GR = 1.62, GB = 2.19
260 : begin RFactor = 353; BFactor = 491; end // GR = 1.62, GB = 2.25
261 : begin RFactor = 348; BFactor = 498; end // GR = 1.62, GB = 2.31
262 : begin RFactor = 344; BFactor = 504; end // GR = 1.62, GB = 2.38
263 : begin RFactor = 339; BFactor = 511; end // GR = 1.62, GB = 2.44
264 : begin RFactor = 540; BFactor = 319; end // GR = 1.69, GB = 1.00
265 : begin RFactor = 524; BFactor = 329; end // GR = 1.69, GB = 1.06
266 : begin RFactor = 509; BFactor = 338; end // GR = 1.69, GB = 1.12
267 : begin RFactor = 496; BFactor = 348; end // GR = 1.69, GB = 1.19
268 : begin RFactor = 483; BFactor = 357; end // GR = 1.69, GB = 1.25
269 : begin RFactor = 471; BFactor = 366; end // GR = 1.69, GB = 1.31
270 : begin RFactor = 461; BFactor = 375; end // GR = 1.69, GB = 1.38
271 : begin RFactor = 450; BFactor = 383; end // GR = 1.69, GB = 1.44
272 : begin RFactor = 441; BFactor = 392; end // GR = 1.69, GB = 1.50
273 : begin RFactor = 432; BFactor = 400; end // GR = 1.69, GB = 1.56
274 : begin RFactor = 424; BFactor = 408; end // GR = 1.69, GB = 1.62
275 : begin RFactor = 416; BFactor = 416; end // GR = 1.69, GB = 1.69
276 : begin RFactor = 408; BFactor = 424; end // GR = 1.69, GB = 1.75
277 : begin RFactor = 401; BFactor = 431; end // GR = 1.69, GB = 1.81
278 : begin RFactor = 394; BFactor = 439; end // GR = 1.69, GB = 1.88
279 : begin RFactor = 388; BFactor = 446; end // GR = 1.69, GB = 1.94
280 : begin RFactor = 382; BFactor = 453; end // GR = 1.69, GB = 2.00
281 : begin RFactor = 376; BFactor = 461; end // GR = 1.69, GB = 2.06
282 : begin RFactor = 370; BFactor = 468; end // GR = 1.69, GB = 2.12
283 : begin RFactor = 365; BFactor = 475; end // GR = 1.69, GB = 2.19
284 : begin RFactor = 360; BFactor = 481; end // GR = 1.69, GB = 2.25
285 : begin RFactor = 355; BFactor = 488; end // GR = 1.69, GB = 2.31
286 : begin RFactor = 350; BFactor = 495; end // GR = 1.69, GB = 2.38
287 : begin RFactor = 346; BFactor = 501; end // GR = 1.69, GB = 2.44
288 : begin RFactor = 550; BFactor = 313; end // GR = 1.75, GB = 1.00
289 : begin RFactor = 533; BFactor = 323; end // GR = 1.75, GB = 1.06
290 : begin RFactor = 518; BFactor = 332; end // GR = 1.75, GB = 1.12
291 : begin RFactor = 505; BFactor = 342; end // GR = 1.75, GB = 1.19
292 : begin RFactor = 492; BFactor = 351; end // GR = 1.75, GB = 1.25
293 : begin RFactor = 480; BFactor = 359; end // GR = 1.75, GB = 1.31
294 : begin RFactor = 469; BFactor = 368; end // GR = 1.75, GB = 1.38
295 : begin RFactor = 459; BFactor = 376; end // GR = 1.75, GB = 1.44
296 : begin RFactor = 449; BFactor = 385; end // GR = 1.75, GB = 1.50
297 : begin RFactor = 440; BFactor = 393; end // GR = 1.75, GB = 1.56
298 : begin RFactor = 431; BFactor = 401; end // GR = 1.75, GB = 1.62
299 : begin RFactor = 423; BFactor = 408; end // GR = 1.75, GB = 1.69
300 : begin RFactor = 416; BFactor = 416; end // GR = 1.75, GB = 1.75
301 : begin RFactor = 408; BFactor = 424; end // GR = 1.75, GB = 1.81
302 : begin RFactor = 401; BFactor = 431; end // GR = 1.75, GB = 1.88
303 : begin RFactor = 395; BFactor = 438; end // GR = 1.75, GB = 1.94
304 : begin RFactor = 389; BFactor = 445; end // GR = 1.75, GB = 2.00
305 : begin RFactor = 383; BFactor = 452; end // GR = 1.75, GB = 2.06
306 : begin RFactor = 377; BFactor = 459; end // GR = 1.75, GB = 2.12
307 : begin RFactor = 372; BFactor = 466; end // GR = 1.75, GB = 2.19
308 : begin RFactor = 366; BFactor = 473; end // GR = 1.75, GB = 2.25
309 : begin RFactor = 361; BFactor = 479; end // GR = 1.75, GB = 2.31
310 : begin RFactor = 357; BFactor = 486; end // GR = 1.75, GB = 2.38
311 : begin RFactor = 352; BFactor = 492; end // GR = 1.75, GB = 2.44
312 : begin RFactor = 559; BFactor = 308; end // GR = 1.81, GB = 1.00
313 : begin RFactor = 543; BFactor = 317; end // GR = 1.81, GB = 1.06
314 : begin RFactor = 527; BFactor = 327; end // GR = 1.81, GB = 1.12
315 : begin RFactor = 513; BFactor = 336; end // GR = 1.81, GB = 1.19
316 : begin RFactor = 500; BFactor = 344; end // GR = 1.81, GB = 1.25
317 : begin RFactor = 488; BFactor = 353; end // GR = 1.81, GB = 1.31
318 : begin RFactor = 477; BFactor = 362; end // GR = 1.81, GB = 1.38
319 : begin RFactor = 467; BFactor = 370; end // GR = 1.81, GB = 1.44
320 : begin RFactor = 457; BFactor = 378; end // GR = 1.81, GB = 1.50
321 : begin RFactor = 447; BFactor = 386; end // GR = 1.81, GB = 1.56
322 : begin RFactor = 439; BFactor = 394; end // GR = 1.81, GB = 1.62
323 : begin RFactor = 431; BFactor = 401; end // GR = 1.81, GB = 1.69
324 : begin RFactor = 423; BFactor = 409; end // GR = 1.81, GB = 1.75
325 : begin RFactor = 415; BFactor = 416; end // GR = 1.81, GB = 1.81
326 : begin RFactor = 408; BFactor = 423; end // GR = 1.81, GB = 1.88
327 : begin RFactor = 402; BFactor = 431; end // GR = 1.81, GB = 1.94
328 : begin RFactor = 395; BFactor = 438; end // GR = 1.81, GB = 2.00
329 : begin RFactor = 389; BFactor = 444; end // GR = 1.81, GB = 2.06
330 : begin RFactor = 384; BFactor = 451; end // GR = 1.81, GB = 2.12
331 : begin RFactor = 378; BFactor = 458; end // GR = 1.81, GB = 2.19
332 : begin RFactor = 373; BFactor = 465; end // GR = 1.81, GB = 2.25
333 : begin RFactor = 368; BFactor = 471; end // GR = 1.81, GB = 2.31
334 : begin RFactor = 363; BFactor = 478; end // GR = 1.81, GB = 2.38
335 : begin RFactor = 358; BFactor = 484; end // GR = 1.81, GB = 2.44
336 : begin RFactor = 569; BFactor = 302; end // GR = 1.88, GB = 1.00
337 : begin RFactor = 552; BFactor = 312; end // GR = 1.88, GB = 1.06
338 : begin RFactor = 536; BFactor = 321; end // GR = 1.88, GB = 1.12
339 : begin RFactor = 522; BFactor = 330; end // GR = 1.88, GB = 1.19
340 : begin RFactor = 509; BFactor = 339; end // GR = 1.88, GB = 1.25
341 : begin RFactor = 497; BFactor = 347; end // GR = 1.88, GB = 1.31
342 : begin RFactor = 485; BFactor = 356; end // GR = 1.88, GB = 1.38
343 : begin RFactor = 474; BFactor = 364; end // GR = 1.88, GB = 1.44
344 : begin RFactor = 464; BFactor = 372; end // GR = 1.88, GB = 1.50
345 : begin RFactor = 455; BFactor = 379; end // GR = 1.88, GB = 1.56
346 : begin RFactor = 446; BFactor = 387; end // GR = 1.88, GB = 1.62
347 : begin RFactor = 438; BFactor = 395; end // GR = 1.88, GB = 1.69
348 : begin RFactor = 430; BFactor = 402; end // GR = 1.88, GB = 1.75
349 : begin RFactor = 422; BFactor = 409; end // GR = 1.88, GB = 1.81
350 : begin RFactor = 415; BFactor = 416; end // GR = 1.88, GB = 1.88
351 : begin RFactor = 409; BFactor = 423; end // GR = 1.88, GB = 1.94
352 : begin RFactor = 402; BFactor = 430; end // GR = 1.88, GB = 2.00
353 : begin RFactor = 396; BFactor = 437; end // GR = 1.88, GB = 2.06
354 : begin RFactor = 390; BFactor = 444; end // GR = 1.88, GB = 2.12
355 : begin RFactor = 384; BFactor = 450; end // GR = 1.88, GB = 2.19
356 : begin RFactor = 379; BFactor = 457; end // GR = 1.88, GB = 2.25
357 : begin RFactor = 374; BFactor = 463; end // GR = 1.88, GB = 2.31
358 : begin RFactor = 369; BFactor = 469; end // GR = 1.88, GB = 2.38
359 : begin RFactor = 364; BFactor = 476; end // GR = 1.88, GB = 2.44
360 : begin RFactor = 578; BFactor = 297; end // GR = 1.94, GB = 1.00
361 : begin RFactor = 561; BFactor = 307; end // GR = 1.94, GB = 1.06
362 : begin RFactor = 545; BFactor = 316; end // GR = 1.94, GB = 1.12
363 : begin RFactor = 531; BFactor = 325; end // GR = 1.94, GB = 1.19
364 : begin RFactor = 517; BFactor = 333; end // GR = 1.94, GB = 1.25
365 : begin RFactor = 505; BFactor = 342; end // GR = 1.94, GB = 1.31
366 : begin RFactor = 493; BFactor = 350; end // GR = 1.94, GB = 1.38
367 : begin RFactor = 482; BFactor = 358; end // GR = 1.94, GB = 1.44
368 : begin RFactor = 472; BFactor = 366; end // GR = 1.94, GB = 1.50
369 : begin RFactor = 462; BFactor = 373; end // GR = 1.94, GB = 1.56
370 : begin RFactor = 453; BFactor = 381; end // GR = 1.94, GB = 1.62
371 : begin RFactor = 445; BFactor = 388; end // GR = 1.94, GB = 1.69
372 : begin RFactor = 437; BFactor = 395; end // GR = 1.94, GB = 1.75
373 : begin RFactor = 429; BFactor = 403; end // GR = 1.94, GB = 1.81
374 : begin RFactor = 422; BFactor = 410; end // GR = 1.94, GB = 1.88
375 : begin RFactor = 415; BFactor = 416; end // GR = 1.94, GB = 1.94
376 : begin RFactor = 409; BFactor = 423; end // GR = 1.94, GB = 2.00
377 : begin RFactor = 402; BFactor = 430; end // GR = 1.94, GB = 2.06
378 : begin RFactor = 396; BFactor = 436; end // GR = 1.94, GB = 2.12
379 : begin RFactor = 391; BFactor = 443; end // GR = 1.94, GB = 2.19
380 : begin RFactor = 385; BFactor = 449; end // GR = 1.94, GB = 2.25
381 : begin RFactor = 380; BFactor = 456; end // GR = 1.94, GB = 2.31
382 : begin RFactor = 375; BFactor = 462; end // GR = 1.94, GB = 2.38
383 : begin RFactor = 370; BFactor = 468; end // GR = 1.94, GB = 2.44
384 : begin RFactor = 587; BFactor = 293; end // GR = 2.00, GB = 1.00
385 : begin RFactor = 570; BFactor = 302; end // GR = 2.00, GB = 1.06
386 : begin RFactor = 554; BFactor = 311; end // GR = 2.00, GB = 1.12
387 : begin RFactor = 539; BFactor = 319; end // GR = 2.00, GB = 1.19
388 : begin RFactor = 525; BFactor = 328; end // GR = 2.00, GB = 1.25
389 : begin RFactor = 513; BFactor = 336; end // GR = 2.00, GB = 1.31
390 : begin RFactor = 501; BFactor = 344; end // GR = 2.00, GB = 1.38
391 : begin RFactor = 490; BFactor = 352; end // GR = 2.00, GB = 1.44
392 : begin RFactor = 479; BFactor = 360; end // GR = 2.00, GB = 1.50
393 : begin RFactor = 470; BFactor = 367; end // GR = 2.00, GB = 1.56
394 : begin RFactor = 461; BFactor = 375; end // GR = 2.00, GB = 1.62
395 : begin RFactor = 452; BFactor = 382; end // GR = 2.00, GB = 1.69
396 : begin RFactor = 444; BFactor = 389; end // GR = 2.00, GB = 1.75
397 : begin RFactor = 436; BFactor = 396; end // GR = 2.00, GB = 1.81
398 : begin RFactor = 429; BFactor = 403; end // GR = 2.00, GB = 1.88
399 : begin RFactor = 422; BFactor = 410; end // GR = 2.00, GB = 1.94
400 : begin RFactor = 415; BFactor = 417; end // GR = 2.00, GB = 2.00
401 : begin RFactor = 409; BFactor = 423; end // GR = 2.00, GB = 2.06
402 : begin RFactor = 403; BFactor = 430; end // GR = 2.00, GB = 2.12
403 : begin RFactor = 397; BFactor = 436; end // GR = 2.00, GB = 2.19
404 : begin RFactor = 391; BFactor = 442; end // GR = 2.00, GB = 2.25
405 : begin RFactor = 386; BFactor = 448; end // GR = 2.00, GB = 2.31
406 : begin RFactor = 381; BFactor = 455; end // GR = 2.00, GB = 2.38
407 : begin RFactor = 376; BFactor = 461; end // GR = 2.00, GB = 2.44
408 : begin RFactor = 596; BFactor = 288; end // GR = 2.06, GB = 1.00
409 : begin RFactor = 578; BFactor = 297; end // GR = 2.06, GB = 1.06
410 : begin RFactor = 562; BFactor = 306; end // GR = 2.06, GB = 1.12
411 : begin RFactor = 547; BFactor = 315; end // GR = 2.06, GB = 1.19
412 : begin RFactor = 533; BFactor = 323; end // GR = 2.06, GB = 1.25
413 : begin RFactor = 520; BFactor = 331; end // GR = 2.06, GB = 1.31
414 : begin RFactor = 508; BFactor = 339; end // GR = 2.06, GB = 1.38
415 : begin RFactor = 497; BFactor = 347; end // GR = 2.06, GB = 1.44
416 : begin RFactor = 487; BFactor = 354; end // GR = 2.06, GB = 1.50
417 : begin RFactor = 477; BFactor = 362; end // GR = 2.06, GB = 1.56
418 : begin RFactor = 468; BFactor = 369; end // GR = 2.06, GB = 1.62
419 : begin RFactor = 459; BFactor = 376; end // GR = 2.06, GB = 1.69
420 : begin RFactor = 451; BFactor = 383; end // GR = 2.06, GB = 1.75
421 : begin RFactor = 443; BFactor = 390; end // GR = 2.06, GB = 1.81
422 : begin RFactor = 435; BFactor = 397; end // GR = 2.06, GB = 1.88
423 : begin RFactor = 428; BFactor = 404; end // GR = 2.06, GB = 1.94
424 : begin RFactor = 421; BFactor = 410; end // GR = 2.06, GB = 2.00
425 : begin RFactor = 415; BFactor = 417; end // GR = 2.06, GB = 2.06
426 : begin RFactor = 409; BFactor = 423; end // GR = 2.06, GB = 2.12
427 : begin RFactor = 403; BFactor = 429; end // GR = 2.06, GB = 2.19
428 : begin RFactor = 397; BFactor = 435; end // GR = 2.06, GB = 2.25
429 : begin RFactor = 392; BFactor = 442; end // GR = 2.06, GB = 2.31
430 : begin RFactor = 387; BFactor = 448; end // GR = 2.06, GB = 2.38
431 : begin RFactor = 382; BFactor = 454; end // GR = 2.06, GB = 2.44
432 : begin RFactor = 605; BFactor = 284; end // GR = 2.12, GB = 1.00
433 : begin RFactor = 587; BFactor = 293; end // GR = 2.12, GB = 1.06
434 : begin RFactor = 570; BFactor = 302; end // GR = 2.12, GB = 1.12
435 : begin RFactor = 555; BFactor = 310; end // GR = 2.12, GB = 1.19
436 : begin RFactor = 541; BFactor = 318; end // GR = 2.12, GB = 1.25
437 : begin RFactor = 528; BFactor = 326; end // GR = 2.12, GB = 1.31
438 : begin RFactor = 516; BFactor = 334; end // GR = 2.12, GB = 1.38
439 : begin RFactor = 505; BFactor = 342; end // GR = 2.12, GB = 1.44
440 : begin RFactor = 494; BFactor = 349; end // GR = 2.12, GB = 1.50
441 : begin RFactor = 484; BFactor = 356; end // GR = 2.12, GB = 1.56
442 : begin RFactor = 475; BFactor = 364; end // GR = 2.12, GB = 1.62
443 : begin RFactor = 466; BFactor = 371; end // GR = 2.12, GB = 1.69
444 : begin RFactor = 457; BFactor = 378; end // GR = 2.12, GB = 1.75
445 : begin RFactor = 449; BFactor = 384; end // GR = 2.12, GB = 1.81
446 : begin RFactor = 442; BFactor = 391; end // GR = 2.12, GB = 1.88
447 : begin RFactor = 435; BFactor = 398; end // GR = 2.12, GB = 1.94
448 : begin RFactor = 428; BFactor = 404; end // GR = 2.12, GB = 2.00
449 : begin RFactor = 421; BFactor = 410; end // GR = 2.12, GB = 2.06
450 : begin RFactor = 415; BFactor = 417; end // GR = 2.12, GB = 2.12
451 : begin RFactor = 409; BFactor = 423; end // GR = 2.12, GB = 2.19
452 : begin RFactor = 403; BFactor = 429; end // GR = 2.12, GB = 2.25
453 : begin RFactor = 398; BFactor = 435; end // GR = 2.12, GB = 2.31
454 : begin RFactor = 392; BFactor = 441; end // GR = 2.12, GB = 2.38
455 : begin RFactor = 387; BFactor = 447; end // GR = 2.12, GB = 2.44
456 : begin RFactor = 614; BFactor = 280; end // GR = 2.19, GB = 1.00
457 : begin RFactor = 595; BFactor = 289; end // GR = 2.19, GB = 1.06
458 : begin RFactor = 579; BFactor = 297; end // GR = 2.19, GB = 1.12
459 : begin RFactor = 563; BFactor = 305; end // GR = 2.19, GB = 1.19
460 : begin RFactor = 549; BFactor = 314; end // GR = 2.19, GB = 1.25
461 : begin RFactor = 536; BFactor = 321; end // GR = 2.19, GB = 1.31
462 : begin RFactor = 523; BFactor = 329; end // GR = 2.19, GB = 1.38
463 : begin RFactor = 512; BFactor = 337; end // GR = 2.19, GB = 1.44
464 : begin RFactor = 501; BFactor = 344; end // GR = 2.19, GB = 1.50
465 : begin RFactor = 491; BFactor = 351; end // GR = 2.19, GB = 1.56
466 : begin RFactor = 481; BFactor = 358; end // GR = 2.19, GB = 1.62
467 : begin RFactor = 472; BFactor = 365; end // GR = 2.19, GB = 1.69
468 : begin RFactor = 464; BFactor = 372; end // GR = 2.19, GB = 1.75
469 : begin RFactor = 456; BFactor = 379; end // GR = 2.19, GB = 1.81
470 : begin RFactor = 448; BFactor = 385; end // GR = 2.19, GB = 1.88
471 : begin RFactor = 441; BFactor = 392; end // GR = 2.19, GB = 1.94
472 : begin RFactor = 434; BFactor = 398; end // GR = 2.19, GB = 2.00
473 : begin RFactor = 427; BFactor = 405; end // GR = 2.19, GB = 2.06
474 : begin RFactor = 421; BFactor = 411; end // GR = 2.19, GB = 2.12
475 : begin RFactor = 415; BFactor = 417; end // GR = 2.19, GB = 2.19
476 : begin RFactor = 409; BFactor = 423; end // GR = 2.19, GB = 2.25
477 : begin RFactor = 403; BFactor = 429; end // GR = 2.19, GB = 2.31
478 : begin RFactor = 398; BFactor = 435; end // GR = 2.19, GB = 2.38
479 : begin RFactor = 393; BFactor = 440; end // GR = 2.19, GB = 2.44
480 : begin RFactor = 622; BFactor = 276; end // GR = 2.25, GB = 1.00
481 : begin RFactor = 604; BFactor = 285; end // GR = 2.25, GB = 1.06
482 : begin RFactor = 587; BFactor = 293; end // GR = 2.25, GB = 1.12
483 : begin RFactor = 571; BFactor = 301; end // GR = 2.25, GB = 1.19
484 : begin RFactor = 557; BFactor = 309; end // GR = 2.25, GB = 1.25
485 : begin RFactor = 543; BFactor = 317; end // GR = 2.25, GB = 1.31
486 : begin RFactor = 531; BFactor = 325; end // GR = 2.25, GB = 1.38
487 : begin RFactor = 519; BFactor = 332; end // GR = 2.25, GB = 1.44
488 : begin RFactor = 508; BFactor = 339; end // GR = 2.25, GB = 1.50
489 : begin RFactor = 498; BFactor = 346; end // GR = 2.25, GB = 1.56
490 : begin RFactor = 488; BFactor = 353; end // GR = 2.25, GB = 1.62
491 : begin RFactor = 479; BFactor = 360; end // GR = 2.25, GB = 1.69
492 : begin RFactor = 470; BFactor = 367; end // GR = 2.25, GB = 1.75
493 : begin RFactor = 462; BFactor = 373; end // GR = 2.25, GB = 1.81
494 : begin RFactor = 454; BFactor = 380; end // GR = 2.25, GB = 1.88
495 : begin RFactor = 447; BFactor = 386; end // GR = 2.25, GB = 1.94
496 : begin RFactor = 440; BFactor = 393; end // GR = 2.25, GB = 2.00
497 : begin RFactor = 433; BFactor = 399; end // GR = 2.25, GB = 2.06
498 : begin RFactor = 427; BFactor = 405; end // GR = 2.25, GB = 2.12
499 : begin RFactor = 421; BFactor = 411; end // GR = 2.25, GB = 2.19
500 : begin RFactor = 415; BFactor = 417; end // GR = 2.25, GB = 2.25
501 : begin RFactor = 409; BFactor = 423; end // GR = 2.25, GB = 2.31
502 : begin RFactor = 404; BFactor = 429; end // GR = 2.25, GB = 2.38
503 : begin RFactor = 398; BFactor = 434; end // GR = 2.25, GB = 2.44
504 : begin RFactor = 631; BFactor = 272; end // GR = 2.31, GB = 1.00
505 : begin RFactor = 612; BFactor = 281; end // GR = 2.31, GB = 1.06
506 : begin RFactor = 595; BFactor = 289; end // GR = 2.31, GB = 1.12
507 : begin RFactor = 579; BFactor = 297; end // GR = 2.31, GB = 1.19
508 : begin RFactor = 564; BFactor = 305; end // GR = 2.31, GB = 1.25
509 : begin RFactor = 551; BFactor = 313; end // GR = 2.31, GB = 1.31
510 : begin RFactor = 538; BFactor = 320; end // GR = 2.31, GB = 1.38
511 : begin RFactor = 526; BFactor = 327; end // GR = 2.31, GB = 1.44
512 : begin RFactor = 515; BFactor = 335; end // GR = 2.31, GB = 1.50
513 : begin RFactor = 505; BFactor = 342; end // GR = 2.31, GB = 1.56
514 : begin RFactor = 495; BFactor = 348; end // GR = 2.31, GB = 1.62
515 : begin RFactor = 485; BFactor = 355; end // GR = 2.31, GB = 1.69
516 : begin RFactor = 477; BFactor = 362; end // GR = 2.31, GB = 1.75
517 : begin RFactor = 468; BFactor = 368; end // GR = 2.31, GB = 1.81
518 : begin RFactor = 461; BFactor = 375; end // GR = 2.31, GB = 1.88
519 : begin RFactor = 453; BFactor = 381; end // GR = 2.31, GB = 1.94
520 : begin RFactor = 446; BFactor = 387; end // GR = 2.31, GB = 2.00
521 : begin RFactor = 439; BFactor = 393; end // GR = 2.31, GB = 2.06
522 : begin RFactor = 433; BFactor = 399; end // GR = 2.31, GB = 2.12
523 : begin RFactor = 426; BFactor = 405; end // GR = 2.31, GB = 2.19
524 : begin RFactor = 420; BFactor = 411; end // GR = 2.31, GB = 2.25
525 : begin RFactor = 415; BFactor = 417; end // GR = 2.31, GB = 2.31
526 : begin RFactor = 409; BFactor = 423; end // GR = 2.31, GB = 2.38
527 : begin RFactor = 404; BFactor = 428; end // GR = 2.31, GB = 2.44
528 : begin RFactor = 639; BFactor = 269; end // GR = 2.38, GB = 1.00
529 : begin RFactor = 620; BFactor = 277; end // GR = 2.38, GB = 1.06
530 : begin RFactor = 603; BFactor = 285; end // GR = 2.38, GB = 1.12
531 : begin RFactor = 586; BFactor = 293; end // GR = 2.38, GB = 1.19
532 : begin RFactor = 572; BFactor = 301; end // GR = 2.38, GB = 1.25
533 : begin RFactor = 558; BFactor = 308; end // GR = 2.38, GB = 1.31
534 : begin RFactor = 545; BFactor = 316; end // GR = 2.38, GB = 1.38
535 : begin RFactor = 533; BFactor = 323; end // GR = 2.38, GB = 1.44
536 : begin RFactor = 522; BFactor = 330; end // GR = 2.38, GB = 1.50
537 : begin RFactor = 511; BFactor = 337; end // GR = 2.38, GB = 1.56
538 : begin RFactor = 501; BFactor = 344; end // GR = 2.38, GB = 1.62
539 : begin RFactor = 492; BFactor = 351; end // GR = 2.38, GB = 1.69
540 : begin RFactor = 483; BFactor = 357; end // GR = 2.38, GB = 1.75
541 : begin RFactor = 475; BFactor = 364; end // GR = 2.38, GB = 1.81
542 : begin RFactor = 467; BFactor = 370; end // GR = 2.38, GB = 1.88
543 : begin RFactor = 459; BFactor = 376; end // GR = 2.38, GB = 1.94
544 : begin RFactor = 452; BFactor = 382; end // GR = 2.38, GB = 2.00
545 : begin RFactor = 445; BFactor = 388; end // GR = 2.38, GB = 2.06
546 : begin RFactor = 438; BFactor = 394; end // GR = 2.38, GB = 2.12
547 : begin RFactor = 432; BFactor = 400; end // GR = 2.38, GB = 2.19
548 : begin RFactor = 426; BFactor = 406; end // GR = 2.38, GB = 2.25
549 : begin RFactor = 420; BFactor = 411; end // GR = 2.38, GB = 2.31
550 : begin RFactor = 415; BFactor = 417; end // GR = 2.38, GB = 2.38
551 : begin RFactor = 409; BFactor = 423; end // GR = 2.38, GB = 2.44
552 : begin RFactor = 647; BFactor = 265; end // GR = 2.44, GB = 1.00
553 : begin RFactor = 628; BFactor = 273; end // GR = 2.44, GB = 1.06
554 : begin RFactor = 610; BFactor = 281; end // GR = 2.44, GB = 1.12
555 : begin RFactor = 594; BFactor = 289; end // GR = 2.44, GB = 1.19
556 : begin RFactor = 579; BFactor = 297; end // GR = 2.44, GB = 1.25
557 : begin RFactor = 565; BFactor = 304; end // GR = 2.44, GB = 1.31
558 : begin RFactor = 552; BFactor = 312; end // GR = 2.44, GB = 1.38
559 : begin RFactor = 540; BFactor = 319; end // GR = 2.44, GB = 1.44
560 : begin RFactor = 528; BFactor = 326; end // GR = 2.44, GB = 1.50
561 : begin RFactor = 518; BFactor = 333; end // GR = 2.44, GB = 1.56
562 : begin RFactor = 508; BFactor = 339; end // GR = 2.44, GB = 1.62
563 : begin RFactor = 498; BFactor = 346; end // GR = 2.44, GB = 1.69
564 : begin RFactor = 489; BFactor = 352; end // GR = 2.44, GB = 1.75
565 : begin RFactor = 481; BFactor = 359; end // GR = 2.44, GB = 1.81
566 : begin RFactor = 473; BFactor = 365; end // GR = 2.44, GB = 1.88
567 : begin RFactor = 465; BFactor = 371; end // GR = 2.44, GB = 1.94
568 : begin RFactor = 458; BFactor = 377; end // GR = 2.44, GB = 2.00
569 : begin RFactor = 451; BFactor = 383; end // GR = 2.44, GB = 2.06
570 : begin RFactor = 444; BFactor = 389; end // GR = 2.44, GB = 2.12
571 : begin RFactor = 438; BFactor = 395; end // GR = 2.44, GB = 2.19
572 : begin RFactor = 431; BFactor = 401; end // GR = 2.44, GB = 2.25
573 : begin RFactor = 426; BFactor = 406; end // GR = 2.44, GB = 2.31
574 : begin RFactor = 420; BFactor = 412; end // GR = 2.44, GB = 2.38
575 : begin RFactor = 414; BFactor = 417; end // GR = 2.44, GB = 2.44
endcase
end
endtask
endmodule
module CTC_testbench;
// Signal declaration
reg Clock;
reg Reset;
reg[ `size_char - 1 : 0 ]R;
reg[ `size_char - 1 : 0 ]G;
reg[ `size_char - 1 : 0 ]B;
wire[ `size_char - 1 : 0 ]R_out;
wire[ `size_char - 1 : 0 ]G_out;
wire[ `size_char - 1 : 0 ]B_out;
reg[ `size_char - 1 : 0 ]RBlock[ 0 : `SumPixel - 1 ];
reg[ `size_char - 1 : 0 ]GBlock[ 0 : `SumPixel - 1 ];
reg[ `size_char - 1 : 0 ]BBlock[ 0 : `SumPixel - 1 ];
integer i;
integer RFile;
integer GFile;
integer BFile;
CTC CTC_test
(
Clock,
Reset,
R,
G,
B,
R_out,
G_out,
B_out
);
initial
begin
#2
begin
// open test data file
$readmemh( "data/IM000565_RAW_20x15R.dat", RBlock );
$readmemh( "data/IM000565_RAW_20x15G.dat", GBlock );
$readmemh( "data/IM000565_RAW_20x15B.dat", BBlock );
RFile = $fopen( "data/R.dat" );
GFile = $fopen( "data/G.dat" );
BFile = $fopen( "data/B.dat" );
// $readmemh( "data/IM000565_RAW_320x240R.dat", RBlock );
// $readmemh( "data/IM000565_RAW_320x240G.dat", GBlock );
// $readmemh( "data/IM000565_RAW_320x240B.dat", BBlock );
Reset = 1;
end
//#2 Reset = 0;
// Apply Stimulus in order to
for( i = 0; i < `SumPixel; i = i + 1 )
begin
#2
begin
Reset = 0;
R = RBlock[ i ];
G = GBlock[ i ];
B = BBlock[ i ];
end
end
$fclose( RFile );
$fclose( GFile );
$fclose( BFile );
#100000 $stop;
#100000 $finish;
end
initial Clock = 0;
always #1 Clock = ~Clock; //Toggle Clock
endmodule
|
Require Import Omega.
Require Import List.
Require Import StructTact.StructTactics.
Require Import StructTact.FilterMap.
Require Import InfSeqExt.infseq.
Require Import InfSeqExt.classical.
Require Import Chord.InfSeqTactics.
Require Import Chord.Chord.
Require Import Chord.LabeledLemmas.
(** This shouldn't live here but I'm not sure where it should live *)
Lemma nat_strong_ind :
forall (P : nat -> Prop),
(forall n, (forall m, m < n -> P m) -> P n) ->
forall n, P n.
Proof.
intros P Himp.
intros.
(* generalize induction hypothesis *)
cut (forall m, m < n -> P m); [now auto|].
induction n.
- easy.
- firstorder.
Qed.
Section Measure.
Variable measure : global_state -> nat.
Notation "| gst |" := (measure gst) (at level 50).
Definition measure_bounded (n : nat) : infseq occurrence -> Prop :=
always (now (fun o => |occ_gst o| <= n)).
Definition measure_nonincreasing (o o' : occurrence) : Prop :=
|occ_gst o'| <= |occ_gst o|.
Definition measure_decreasing (o o' : occurrence) : Prop :=
|occ_gst o'| < |occ_gst o|.
Definition measure_zero (o : occurrence) : Prop :=
|occ_gst o| = 0.
Definition zero_or_eventually_decreasing : infseq occurrence -> Prop :=
now measure_zero \/_
eventually (consecutive measure_decreasing).
Lemma measure_nonincreasing_stays_zero :
forall o o',
measure_nonincreasing o o' ->
measure_zero o ->
measure_zero o'.
Proof.
unfold measure_nonincreasing, measure_zero.
intros.
omega.
Qed.
Lemma measure_zero_stays_zero :
forall ex,
always (consecutive measure_nonincreasing) ex ->
now measure_zero ex ->
always (now measure_zero) ex.
Proof.
cofix c.
intros.
constructor; auto.
do 2 destruct ex; simpl in *.
apply c.
- eauto using always_invar.
- inv_prop always.
unfold consecutive in *.
simpl.
eauto using measure_nonincreasing_stays_zero.
Qed.
Lemma measure_bounded_hd_elim :
forall m n ex,
measure_bounded n ex ->
|occ_gst (hd ex)| = m ->
m <= n.
Proof.
intros; destruct ex.
now inv_prop measure_bounded.
Qed.
Lemma measure_bounded_monotonic :
forall m n ex,
m <= n ->
measure_bounded m ex ->
measure_bounded n ex.
Proof.
cofix c.
intros.
constructor; destruct ex as [o [o' ex]]; simpl in *.
- inv_prop measure_bounded; simpl in *.
omega.
- eapply c; eauto.
eapply always_invar; eauto.
Qed.
(** If the measure never increases and you can bound the measure of the first
state, you can bound the entire sequence. *)
Lemma nonincreasing_preserves_bound :
forall ex,
always (consecutive measure_nonincreasing) ex ->
forall n,
|occ_gst (hd ex)| <= n ->
measure_bounded n ex.
Proof.
cofix c.
constructor; destruct ex as [o [o' ex]]; simpl in *; [omega|].
eapply c.
- eauto using always_invar.
- inv_prop measure_nonincreasing.
unfold measure_nonincreasing in *.
simpl in *.
omega.
Qed.
(** If the measure never increases, you can bound the entire sequence by the
measure of the first state. *)
Lemma nonincreasing_global :
forall ex,
always (consecutive measure_nonincreasing) ex ->
forall n,
|occ_gst (hd ex)| = n ->
measure_bounded n ex.
Proof.
auto using Nat.eq_le_incl, nonincreasing_preserves_bound.
Qed.
(** If the measure never increases and drops infinitely often, then it will
eventually be less than its initial value (provided the initial value is
nonzero). *)
Lemma measure_drops :
forall ex,
always (consecutive measure_nonincreasing) ex ->
zero_or_eventually_decreasing ex ->
forall n,
|occ_gst (hd ex)| = S n ->
eventually (now (fun o => |occ_gst o| < S n)) ex.
Proof.
intros.
unfold zero_or_eventually_decreasing in *.
find_copy_apply_lem_hyp nonincreasing_global; auto.
invc H0.
- destruct ex.
simpl in *.
congruence.
- match goal with
| H : eventually (consecutive measure_decreasing) _ |- _ =>
induction H
end.
+ destruct s as [o [o' s]].
apply E_next; apply E0.
unfold measure_decreasing in *.
simpl in *; omega.
+ simpl.
destruct s as [o s].
destruct (lt_dec (|occ_gst o|) (|occ_gst x|)).
* apply E_next; apply E0.
simpl in *; omega.
* assert (|occ_gst o| = |occ_gst x|).
{
find_apply_lem_hyp not_lt.
apply Nat.le_antisymm; auto.
inv_prop (always (consecutive measure_nonincreasing)).
unfold measure_nonincreasing in *.
auto.
}
apply E_next.
simpl in *.
repeat find_rewrite.
eapply IHeventually; eauto;
try eapply always_invar; eauto.
Qed.
Lemma less_than_Sn_bounded_n :
forall n ex,
always (consecutive measure_nonincreasing) ex ->
now (fun occ => |occ_gst occ| < S n) ex ->
measure_bounded n ex.
Proof.
intros.
remember (|occ_gst (hd ex)|) as m.
eapply measure_bounded_monotonic;
[|eauto using nonincreasing_global].
destruct ex; simpl in *; omega.
Qed.
Lemma measure_bound_drops :
forall n ex,
measure_bounded (S n) ex ->
always (consecutive measure_nonincreasing) ex ->
zero_or_eventually_decreasing ex ->
eventually (measure_bounded n) ex.
Proof.
intros.
destruct ex as [o ex].
destruct (|occ_gst o|) eqn:?H.
- apply E0.
eapply measure_bounded_monotonic with (m:=0); [omega|].
eapply nonincreasing_global; eauto.
- find_copy_eapply_lem_hyp nonincreasing_global; eauto.
eapply eventually_monotonic_simple.
{
intros; eapply (measure_bounded_monotonic n0 n); eauto.
apply le_S_n.
eapply measure_bounded_hd_elim; eauto.
}
eapply eventually_monotonic; try eapply less_than_Sn_bounded_n; eauto using always_invar.
eapply measure_drops; eauto.
Qed.
Lemma measure_bounded_zero :
forall ex,
measure_bounded 0 ex ->
always (now measure_zero) ex.
Proof.
cofix c.
intros; constructor.
- inv_prop measure_bounded.
destruct ex; simpl in *.
unfold measure_zero; omega.
- destruct ex.
simpl in *.
apply c.
eapply always_invar; eauto.
Qed.
(** TODO(ryan) move to infseq *)
Lemma eventually_idempotent :
forall T (P : infseq T -> Prop) ex,
eventually (eventually P) ex ->
eventually P ex.
Proof.
intros T P ex H_ee.
induction H_ee.
- assumption.
- now apply E_next.
Qed.
(* Lemma decreasing_inf_often_or_zero_invar_when_nonincreasing : *)
(* forall o ex, *)
(* always (consecutive measure_nonincreasing) (Cons o ex) -> *)
(* zero_or_eventually_decreasing (Cons o ex) -> *)
(* zero_or_eventually_decreasing ex. *)
(* Proof. *)
(* unfold zero_or_eventually_decreasing. *)
(* intros. *)
(* inv_prop or_tl. *)
(* - left. *)
(* find_apply_lem_hyp measure_zero_stays_zero; auto. *)
(* find_apply_lem_hyp always_invar. *)
(* now inv_prop always. *)
(* - right; eapply inf_often_invar; eauto. *)
(* Qed. *)
Lemma measure_decreasing_to_zero' :
forall n ex,
always (consecutive measure_nonincreasing) ex ->
always zero_or_eventually_decreasing ex ->
measure_bounded n ex ->
eventually (now measure_zero) ex.
Proof.
intros n.
induction n using nat_strong_ind.
destruct n; subst_max.
- intros.
apply E0.
find_apply_lem_hyp measure_bounded_zero.
inv_prop always.
assumption.
- intros.
destruct ex.
find_copy_apply_lem_hyp measure_bound_drops;
auto;
try now apply always_now.
pose proof (H n).
forwards.
omega.
specialize (H4 H5); clear H5.
eapply eventually_idempotent.
lift_eventually H4.
+ unfold and_tl; intros; break_and_goal; break_and;
eauto using always_invar.
+ split; auto.
Qed.
Lemma measure_decreasing_to_zero :
forall ex,
always zero_or_eventually_decreasing ex ->
always (consecutive measure_nonincreasing) ex ->
continuously (now measure_zero) ex.
Proof.
intros.
remember (|occ_gst (hd ex)|) as n.
find_copy_eapply_lem_hyp nonincreasing_global; auto.
find_copy_eapply_lem_hyp measure_decreasing_to_zero'; eauto.
lift_eventually measure_zero_stays_zero.
eauto using always_invar.
Qed.
(* TODO(ryan) move to infseq *)
Lemma eventually_and_tl_comm :
forall T (P Q : infseq T -> Prop) s,
eventually (P /\_ Q) s ->
eventually (Q /\_ P) s.
Proof.
intros until 0.
apply eventually_monotonic_simple.
intros.
now rewrite and_tl_comm.
Qed.
(* TODO(ryan) move to infseq *)
Lemma always_and_tl_comm :
forall T (P Q : infseq T -> Prop) s,
always (P /\_ Q) s ->
always (Q /\_ P) s.
Proof.
intros until 0.
apply always_monotonic.
intros.
now rewrite and_tl_comm.
Qed.
Definition measure_x x occ := |occ_gst occ| = x.
Set Bullet Behavior "Strict Subproofs".
Require Import Classical.
Lemma always_or_eventually :
forall T P (s : infseq T),
always P s \/ eventually (not_tl P) s.
Proof.
intros.
destruct (classic (always P s)); eauto using not_always_eventually_not.
Qed.
Lemma eventually_exists :
forall T A (P : A -> T -> Prop) (s : infseq T),
eventually (now (fun o => exists x, P x o)) s ->
exists x,
eventually (now (fun o => P x o)) s.
Proof.
intros.
induction H.
- destruct s. simpl in *.
break_exists_exists.
apply E0. simpl. auto.
- break_exists_exists.
apply E_next. auto.
Qed.
Lemma eventually_exists' :
forall T A (P : A -> infseq T -> Prop) (s : infseq T),
eventually (fun s => exists x, P x s) s ->
exists x,
eventually (P x) s.
Proof.
intros.
induction H.
- break_exists_exists.
eauto using E0.
- break_exists_exists. eauto using E_next.
Qed.
Lemma eventually_pure_and :
forall T (Q : Prop) (P : T -> Prop) (s : infseq T),
eventually (now (fun o => Q /\ P o)) s ->
Q /\ eventually (now P) s.
Proof.
induction 1.
- destruct s; simpl in *; intuition.
eauto using E0.
- intuition. eauto using E_next.
Qed.
Lemma measure_nonincreasing_eventually_stable' :
forall n ex,
(now (measure_x n) ex) ->
always (consecutive measure_nonincreasing) ex ->
exists x,
continuously (now (measure_x x)) ex.
Proof.
induction n using nat_strong_ind.
intros.
destruct (always_or_eventually _ (now (measure_x n)) ex).
- eauto using always_continuously.
- find_copy_eapply_lem_hyp nonincreasing_preserves_bound; eauto.
assert (|occ_gst (hd ex)| = n).
{
unfold now in *. break_match; repeat find_rewrite; simpl; auto.
}
repeat find_rewrite.
assert (exists m, m < n /\ eventually (now (measure_x m)) ex).
{
unfold measure_bounded in *.
find_eapply_lem_hyp cumul_eventually_always; eauto.
assert (eventually (now (fun o => exists m, m < n /\ measure_x m o)) ex).
{
eapply eventually_monotonic_simple; [|eauto].
intros.
unfold now; break_match. subst.
exists (|occ_gst o|). unfold measure_x. intuition.
unfold and_tl,not_tl in *. intuition. simpl in *.
unfold measure_x in *.
omega.
}
find_apply_lem_hyp eventually_exists.
break_exists_exists.
eauto using eventually_pure_and.
}
break_exists. intuition.
match goal with
| H : eventually (now _) _ |- _ =>
eapply eventually_monotonic with
(J := (always (consecutive measure_nonincreasing)))
(Q := (fun ex => exists x, continuously (now (measure_x x)) ex))
in H
end; eauto using always_invar.
find_apply_lem_hyp eventually_exists'.
break_exists_exists.
unfold continuously in *.
eauto using eventually_idempotent.
Qed.
Lemma measure_nonincreasing_eventually_stable :
forall ex,
always (consecutive measure_nonincreasing) ex ->
exists x,
continuously (now (measure_x x)) ex.
Proof.
intros.
assert (now (measure_x (|occ_gst (hd ex)|)) ex).
{ unfold measure_x. destruct ex; simpl; auto. }
eauto using measure_nonincreasing_eventually_stable'.
Qed.
End Measure.
Section LocalMeasure.
Variable local_measure : addr -> global_state -> nat.
Notation "| h 'in' gst |" := (local_measure h gst) (at level 50).
Definition sum (l : list nat) :=
fold_left Nat.add l 0.
Definition max (l : list nat) :=
fold_left Nat.max l 0.
Lemma fold_left_acc_comm :
forall a l,
fold_left Nat.add l a = a + fold_left Nat.add l 0.
Proof.
intros.
generalize a.
induction l; [auto|].
simpl.
intros.
rewrite IHl; symmetry; rewrite IHl.
auto with arith.
Qed.
Lemma fold_left_max_comm :
forall a l,
fold_left Nat.max l a = Nat.max a (fold_left Nat.max l 0).
Proof.
intros.
generalize a.
induction l; intros.
- simpl; zify; omega.
- simpl.
rewrite IHl; symmetry; rewrite IHl.
zify; omega.
Qed.
Lemma sum_cons :
forall n l,
sum (n :: l) = n + sum l.
Proof.
unfold sum.
intros; simpl.
now rewrite fold_left_acc_comm.
Qed.
Lemma max_cons_le :
forall n l,
n <= max (n :: l).
Proof.
intros. generalize n; clear n.
induction l; intros; simpl in *; auto.
unfold max in *. simpl in *.
eapply le_trans; [eapply Nat.le_max_l|]; eauto.
Qed.
Lemma max_cons_cases :
forall n l,
max (n :: l) = n /\
max l <= n \/
max (n :: l) = max l /\
n <= max l.
Proof.
intros. unfold max.
repeat (rewrite fold_symmetric; eauto using Max.max_assoc, Max.max_comm).
simpl.
match goal with
| |- context [Nat.max ?n ?m] =>
destruct (Nat.max_spec n m)
end; intuition.
Qed.
Lemma sum_app :
forall l l',
sum (l ++ l') = sum l + sum l'.
Proof.
unfold sum.
intros; simpl.
now rewrite fold_left_app, fold_left_acc_comm.
Qed.
Lemma sum_disjoint :
forall xs x ys,
sum (xs ++ x :: ys) = sum xs + x + sum ys.
Proof.
intros.
now rewrite sum_app, sum_cons, Nat.add_assoc.
Qed.
Lemma sum_map_mono :
forall X (f g : X -> nat) l,
(forall x, In x l -> f x <= g x) ->
sum (map f l) <= sum (map g l).
Proof.
intros.
induction l; [auto|].
rewrite !map_cons, !sum_cons.
apply Nat.add_le_mono; auto with datatypes.
Qed.
Lemma max_map_mono :
forall X (f g : X -> nat) l,
(forall x, In x l -> f x <= g x) ->
max (map f l) <= max (map g l).
Proof.
intros.
induction l; [auto|].
forwards. eauto with datatypes. concludes.
pose proof (max_cons_le (g a) (map g l)).
assert (f a <= g a) by eauto with datatypes.
pose proof (max_cons_cases (f a) (map f l)).
pose proof (max_cons_cases (g a) (map g l)).
rewrite !map_cons.
intuition omega.
Qed.
(* TODO(ryan) move to structtact *)
Theorem list_strong_ind :
forall A (P : list A -> Prop),
(forall l, (forall l', length l' < length l -> P l') ->
P l) ->
forall l0 : list A, P l0.
Proof.
intros.
apply H.
induction l0; simpl;
firstorder using Nat.nlt_0_r, lt_n_Sm_le, lt_le_trans.
Qed.
Lemma fold_max_const_is_const :
forall l c,
(forall x, In x l -> x = c) ->
fold_left Nat.max l c = c.
Proof.
unfold max.
induction l; intros.
- cbn in *; omega.
- replace a with c; [|symmetry; auto with datatypes].
simpl.
rewrite Max.max_idempotent.
eauto with datatypes.
Qed.
Lemma max_nonempty_const_is_const :
forall l c,
(forall x, In x l -> x = c) ->
length l > 0 ->
max l = c.
Proof.
unfold max.
intros.
destruct l as [|a l].
- cbn in *; omega.
- replace a with c; [|symmetry; auto with datatypes].
cbn; apply fold_max_const_is_const; auto with datatypes.
Qed.
Lemma max_map_bound :
forall X (f : X -> nat) b l,
(forall x, In x l -> f x <= b) ->
max (map f l) <= b.
Proof.
intros.
destruct l as [| h l].
- auto with arith.
- replace b with (max (map (fun _ => b) (h :: l)));
auto using max_map_mono.
eapply max_nonempty_const_is_const; simpl; auto with arith.
intros.
break_or_hyp; [congruence|].
find_apply_lem_hyp in_map_iff.
break_exists; break_and; congruence.
Qed.
Lemma sum_of_nats_bounds_addends :
forall l n,
sum l = n ->
forall x,
In x l ->
x <= n.
Proof.
unfold sum.
intro l.
induction l using list_strong_ind; destruct l.
- easy.
- intros.
find_apply_lem_hyp in_inv; break_or_hyp.
+ simpl.
rewrite fold_left_acc_comm.
omega.
+ simpl. rewrite fold_left_acc_comm.
assert (x <= fold_left Nat.add l 0).
{ assert (H_len: length l < length (n :: l)) by auto.
apply (H l H_len); auto.
}
omega.
Qed.
Lemma sum_of_nats_zero_means_all_zero :
forall l,
sum l = 0 ->
forall x,
In x l ->
x = 0.
Proof.
intros.
symmetry.
apply le_n_0_eq.
eapply sum_of_nats_bounds_addends; eauto.
Qed.
Lemma max_of_nats_bounds_list :
forall l n,
max l = n ->
forall x,
In x l ->
x <= n.
Proof.
unfold max.
induction l using list_strong_ind; destruct l as [|a l].
- easy.
- intros.
find_apply_lem_hyp in_inv; break_or_hyp.
+ simpl.
rewrite fold_left_max_comm.
zify; omega.
+ assert (x <= fold_left Nat.max l 0)
by firstorder.
simpl. rewrite fold_left_max_comm.
zify; omega.
Qed.
Lemma max_of_nats_zero_means_zero :
forall l,
max l = 0 ->
forall x,
In x l ->
x = 0.
Proof.
intros.
symmetry.
apply le_n_0_eq.
eapply max_of_nats_bounds_list; eauto.
Qed.
Lemma sum_of_zeros_is_zero :
forall l,
Forall (fun n => n = 0) l ->
sum l = 0.
Proof.
intros.
induction l; auto.
inv_prop Forall; auto.
Qed.
Lemma sum_nonzero_implies_addend_nonzero :
forall l,
sum l > 0 ->
exists x,
In x l /\
x > 0.
Proof.
induction l as [|hd rest].
- cbn.
intros; omega.
- intros; rewrite sum_cons in *.
destruct hd eqn:?H.
+ firstorder.
+ exists hd; firstorder.
Qed.
Definition global_measure (gst : global_state) : nat :=
sum (map (fun h => |h in gst|) (active_nodes gst)).
Notation "| gst |" := (global_measure gst) (at level 50).
Definition max_measure (gst : global_state) : nat :=
max (map (fun h => |h in gst|) (active_nodes gst)).
Lemma max_measure_bounds_measures :
forall gst e,
max_measure gst = e ->
forall h,
In h (active_nodes gst) ->
|h in gst| <= e.
Proof.
intros.
unfold max_measure in *.
eapply max_of_nats_bounds_list; eauto.
rewrite in_map_iff.
eauto.
Qed.
Definition max_measure_nonzero_eventually_all_locals_below (ex : infseq occurrence) : Prop :=
forall err,
max_measure (occ_gst (hd ex)) = S err ->
forall h,
In h (active_nodes (occ_gst (hd ex))) ->
eventually (now (fun o => |h in occ_gst o| <= err)) ex.
Definition some_local_measure_drops (ex : infseq occurrence) :=
exists h,
In h (active_nodes (occ_gst (hd ex))) /\
eventually (consecutive (measure_decreasing (local_measure h))) ex.
Definition local_measure_nonincreasing (h : addr) : infseq occurrence -> Prop :=
consecutive (measure_nonincreasing (local_measure h)).
Definition local_measures_nonincreasing (ex : infseq occurrence) : Prop :=
forall h,
In h (active_nodes (occ_gst (hd ex))) ->
local_measure_nonincreasing h ex.
Lemma map_Forall_comm :
forall (X Y : Type) (f : X -> Y) P l,
Forall P (map f l) <-> Forall (fun x => P (f x)) l.
Proof.
intros; split; intro;
induction l; constructor;
inv_prop Forall;
eauto.
Qed.
Lemma local_all_zero_global_zero :
forall gst,
Forall (fun h => |h in gst| = 0) (active_nodes gst) <-> |gst| = 0.
Proof.
intros; split; intro.
- apply sum_of_zeros_is_zero.
now apply map_Forall_comm.
- apply Forall_forall.
intros.
eapply sum_of_nats_zero_means_all_zero; eauto.
change (|x in gst|) with ((fun y => |y in gst|) x).
now apply in_map.
Qed.
Lemma measure_mono :
forall gst gst',
nodes gst' = nodes gst ->
failed_nodes gst' = failed_nodes gst ->
(forall h, In h (active_nodes gst) -> |h in gst| <= |h in gst'|) ->
|gst| <= |gst'|.
Proof.
intros.
unfold global_measure, active_nodes in *.
repeat find_rewrite.
now apply sum_map_mono.
Qed.
Lemma local_nonincreasing_causes_global_nonincreasing :
forall ex,
lb_execution ex ->
local_measures_nonincreasing ex ->
consecutive (measure_nonincreasing global_measure) ex.
Proof.
unfold local_measures_nonincreasing, local_measure_nonincreasing, measure_nonincreasing.
intros.
destruct ex as [o [o' ex]]; simpl.
inv_prop lb_execution.
find_copy_apply_lem_hyp labeled_step_dynamic_preserves_active_nodes.
eapply measure_mono; repeat find_rewrite;
eauto using labeled_step_dynamic_preserves_nodes, labeled_step_dynamic_preserves_failed_nodes.
intros; unfold active_nodes in *.
repeat find_reverse_rewrite; simpl in *; eauto.
Qed.
Lemma max_measure_mono :
forall gst gst',
nodes gst' = nodes gst ->
failed_nodes gst' = failed_nodes gst ->
(forall h, In h (active_nodes gst) -> |h in gst| <= |h in gst'|) ->
max_measure gst <= max_measure gst'.
Proof.
intros.
unfold max_measure, active_nodes in *.
repeat find_rewrite.
now apply max_map_mono.
Qed.
Lemma local_nonincreasing_causes_max_nonincreasing :
forall ex,
lb_execution ex ->
local_measures_nonincreasing ex ->
consecutive (measure_nonincreasing max_measure) ex.
Proof.
unfold local_measures_nonincreasing, local_measure_nonincreasing, measure_nonincreasing.
intros.
destruct ex as [o [o' ex]]; simpl.
inv_prop lb_execution.
find_copy_apply_lem_hyp labeled_step_dynamic_preserves_active_nodes.
eapply max_measure_mono; repeat find_rewrite;
eauto using labeled_step_dynamic_preserves_nodes, labeled_step_dynamic_preserves_failed_nodes.
intros; unfold active_nodes in *.
repeat find_reverse_rewrite; simpl in *; eauto.
Qed.
Lemma local_always_nonincreasing_causes_max_always_nonincreasing :
forall ex,
lb_execution ex ->
always local_measures_nonincreasing ex ->
always (consecutive (measure_nonincreasing max_measure)) ex.
Proof.
cofix c; intros; constructor; destruct ex.
- apply local_nonincreasing_causes_max_nonincreasing; eauto.
apply always_now'; eauto.
- apply c; eauto using always_invar, lb_execution_invar.
Qed.
Lemma local_dropping_makes_global_drop :
forall h o o',
active_nodes (occ_gst o) = active_nodes (occ_gst o') ->
(forall h', In h' (active_nodes (occ_gst o)) ->
measure_nonincreasing (local_measure h') o o') ->
In h (active_nodes (occ_gst o)) ->
measure_decreasing (local_measure h) o o' ->
measure_decreasing global_measure o o'.
Proof.
unfold measure_decreasing, measure_nonincreasing, global_measure.
intros.
find_apply_lem_hyp in_split; break_exists.
repeat find_rewrite.
rewrite !map_app, !map_cons, !sum_disjoint.
apply Nat.add_lt_le_mono;
try apply Nat.add_le_lt_mono;
assumption || apply sum_map_mono; auto with datatypes.
Qed.
Lemma local_dropping_makes_global_drop_ex :
forall h ex,
lb_execution ex ->
always local_measures_nonincreasing ex ->
In h (active_nodes (occ_gst (hd ex))) ->
consecutive (measure_decreasing (local_measure h)) ex ->
consecutive (measure_decreasing global_measure) ex.
Proof.
intros.
destruct ex as [o [o' ex]].
inv_prop lb_execution.
inv_prop always.
eapply local_dropping_makes_global_drop;
eauto using labeled_step_dynamic_preserves_active_nodes.
Qed.
Definition nonzero_error_causes_measure_drop (ex : infseq occurrence) :=
|occ_gst (hd ex)| > 0 ->
some_local_measure_drops ex.
Lemma local_measure_causes_eventual_drop :
forall ex,
lb_execution ex ->
always local_measures_nonincreasing ex ->
nonzero_error_causes_measure_drop ex ->
zero_or_eventually_decreasing global_measure ex.
Proof.
intros.
destruct (|occ_gst (hd ex)|) as [| err] eqn:?H;
[left|right].
- destruct ex; assumption.
- pose proof (gt_Sn_O err); repeat find_reverse_rewrite.
assert (some_local_measure_drops ex) by auto.
unfold some_local_measure_drops in *; break_exists_name h; break_and.
lift_eventually (local_dropping_makes_global_drop_ex h);
firstorder using lb_execution_invar, always_invar.
inv_prop lb_execution; simpl.
find_copy_apply_lem_hyp labeled_step_dynamic_preserves_active_nodes.
now repeat find_reverse_rewrite.
Qed.
Lemma local_measure_always_causes_eventual_drop :
forall ex,
lb_execution ex ->
always local_measures_nonincreasing ex ->
always nonzero_error_causes_measure_drop ex ->
always (zero_or_eventually_decreasing global_measure) ex.
Proof.
intros.
lift_always local_measure_causes_eventual_drop.
repeat apply always_and_tl;
eauto using always_always, always_inv, lb_execution_invar.
Qed.
Lemma local_measure_causes_measure_zero :
forall ex,
lb_execution ex ->
always local_measures_nonincreasing ex ->
always nonzero_error_causes_measure_drop ex ->
continuously (now (measure_zero global_measure)) ex.
Proof.
intros.
eapply measure_decreasing_to_zero.
- now apply local_measure_always_causes_eventual_drop.
- lift_always local_nonincreasing_causes_global_nonincreasing.
apply always_and_tl; eauto using always_inv, lb_execution_invar.
Qed.
(* TODO(ryan) move to infseq *)
Lemma continuously_forall_list_comm :
forall (A B : Type) (P : A -> infseq B -> Prop) l ex,
(forall x, In x l -> (continuously (P x) ex)) ->
continuously (fun ex' => forall x, In x l -> P x ex') ex.
Proof.
induction l as [| a l].
- intros.
apply E0.
eapply always_monotonic; try eapply always_true; intros.
exfalso; auto.
- intros.
pose proof (IHl ex).
forwards. auto with datatypes. concludes.
assert (continuously (P a) ex)
by auto with datatypes.
cut (continuously ((fun ex' => forall x, In x l -> P x ex') /\_ P a) ex).
{
apply continuously_monotonic.
intros.
unfold and_tl in *; break_and.
find_apply_lem_hyp in_inv; break_or_hyp; auto.
}
apply continuously_and_tl; eauto.
Qed.
Lemma always_forall_list_comm :
forall (A B : Type) (P : A -> infseq B -> Prop) ex l,
(forall x, In x l -> (always (P x) ex)) ->
always (fun ex' => forall x, In x l -> P x ex') ex.
Proof.
intros.
generalize dependent l.
induction l as [| a l].
- intros; eapply always_monotonic; try eapply always_true; intros.
exfalso; auto.
- intros.
forward IHl. eauto with datatypes. concludes.
assert (always (P a) ex)
by auto with datatypes.
cut (always ((fun ex' => forall x, In x l -> P x ex') /\_ P a) ex).
{
apply always_monotonic.
intros.
unfold and_tl in *; break_and.
find_apply_lem_hyp in_inv; break_or_hyp; auto.
}
apply always_and_tl; eauto.
Qed.
Lemma measure_eventually_bounded_continuously_bounded :
forall ex h n,
always (local_measure_nonincreasing h) ex ->
eventually (fun ex' => |h in occ_gst (hd ex')| <= n) ex ->
continuously (fun ex' => |h in occ_gst (hd ex') | <= n) ex.
Proof.
intros.
induction H0.
- apply E0.
apply nonincreasing_preserves_bound in H0; eauto.
unfold measure_bounded in *.
eapply always_monotonic; eauto.
intros [o s']; auto.
- apply E_next.
unfold continuously in *.
find_apply_lem_hyp always_Cons; tauto.
Qed.
Lemma all_measures_nonincreasing_always_each_nonincreasing :
forall (ex : infseq occurrence) (h : addr),
lb_execution ex ->
In h (active_nodes (occ_gst (hd ex))) ->
always local_measures_nonincreasing ex ->
always (consecutive (measure_nonincreasing (local_measure h))) ex.
Proof.
cofix c; intros; constructor; destruct ex.
- find_apply_lem_hyp always_Cons; break_and.
unfold local_measures_nonincreasing, local_measure_nonincreasing in *.
auto.
- simpl. apply c; eauto using lb_execution_invar, always_invar.
inv_prop lb_execution.
erewrite <- labeled_step_dynamic_preserves_active_nodes; eauto.
Qed.
Lemma local_drops_below_bound :
forall ex h n,
lb_execution ex ->
In h (active_nodes (occ_gst (hd ex))) ->
always local_measures_nonincreasing ex ->
|h in (occ_gst (hd ex))| <= S n ->
eventually (consecutive (measure_decreasing (local_measure h))) ex ->
continuously (fun ex' => |h in (occ_gst (hd ex'))| <= n) ex.
Proof.
intros.
assert (always (consecutive (measure_nonincreasing (local_measure h))) ex)
by eauto using all_measures_nonincreasing_always_each_nonincreasing.
eapply measure_eventually_bounded_continuously_bounded; auto.
destruct (|h in (occ_gst (hd ex))|) as [|k] eqn:?.
- fold (measure_zero (local_measure h) (hd ex)) in *.
destruct ex.
change (measure_zero (local_measure h) (hd (Cons o ex)))
with (now (measure_zero (local_measure h)) (Cons o ex)) in *.
apply E0.
invcs_prop measure_zero.
omega.
- cut (eventually (fun ex' => |h in occ_gst (hd ex')| < S k) ex).
{
apply eventually_monotonic_simple.
intros; omega.
}
cut (eventually (measure_bounded (local_measure h) k) ex).
{
apply eventually_monotonic_simple.
unfold measure_bounded.
intros. destruct s.
find_apply_lem_hyp always_Cons; break_and.
cbn in *.
omega.
}
eapply measure_bound_drops; firstorder.
eapply less_than_Sn_bounded_n; auto.
destruct ex; simpl in *; omega.
Qed.
Lemma always_bound_on_local_measures_bounds_max :
forall n ex,
lb_execution ex ->
always
(fun ex' =>
forall h,
In h (active_nodes (occ_gst (hd ex))) ->
|h in occ_gst (hd ex')| <= n)
ex ->
always (fun ex' => max_measure (occ_gst (hd ex')) <= n) ex.
Proof.
intros.
remember (active_nodes (occ_gst (hd ex))) as l.
find_copy_apply_lem_hyp (active_nodes_always_identical l ex); eauto.
generalize dependent ex.
cofix c. intros.
constructor; destruct ex.
- unfold max_measure.
repeat find_apply_lem_hyp always_Cons; break_and.
eapply max_map_bound.
now repeat find_reverse_rewrite.
- repeat find_apply_lem_hyp always_Cons; break_and.
apply c; cbn; eauto using lb_execution_invar.
now find_eapply_lem_hyp always_now'.
Qed.
Lemma continuously_bound_on_local_measures_bounds_max :
forall n ex,
lb_execution ex ->
continuously
(fun ex' =>
forall h,
In h (active_nodes (occ_gst (hd ex))) ->
|h in occ_gst (hd ex')| <= n)
ex ->
continuously (fun ex' => max_measure (occ_gst (hd ex')) <= n) ex.
Proof.
intros.
remember (active_nodes (occ_gst (hd ex))) as l.
find_copy_apply_lem_hyp (active_nodes_always_identical (active_nodes (occ_gst (hd ex))) ex); eauto.
match goal with
| H: continuously _ _ |- _ => induction H
end.
- apply E0.
apply always_bound_on_local_measures_bounds_max; eauto.
now replace (active_nodes (occ_gst (hd s))) with l.
- apply E_next.
apply IHeventually; eauto using lb_execution_invar, always_invar, active_nodes_always_identical.
destruct s.
repeat (find_apply_lem_hyp always_Cons; break_and).
cbn in *.
congruence.
Qed.
Lemma continuously_bound_on_local_measures_max_measure_bounded :
forall n ex,
lb_execution ex ->
continuously
(fun ex' =>
forall h,
In h (active_nodes (occ_gst (hd ex))) ->
|h in occ_gst (hd ex')| <= n)
ex ->
eventually (measure_bounded max_measure n) ex.
Proof.
intros.
cut (continuously (fun ex' => max_measure (occ_gst (hd ex')) <= n) ex).
{
unfold measure_bounded.
eapply continuously_monotonic.
intros.
destruct s; auto.
}
find_apply_lem_hyp continuously_bound_on_local_measures_bounds_max; auto.
Qed.
Lemma max_measure_continuously_decreasing_bound :
forall ex n,
lb_execution ex ->
always local_measures_nonincreasing ex ->
always max_measure_nonzero_eventually_all_locals_below ex ->
max_measure (occ_gst (hd ex)) = S n ->
eventually (measure_bounded max_measure n) ex.
Proof.
intros.
apply continuously_bound_on_local_measures_max_measure_bounded; auto.
apply continuously_forall_list_comm; intros.
apply measure_eventually_bounded_continuously_bounded;
eauto using all_measures_nonincreasing_always_each_nonincreasing.
find_apply_lem_hyp always_now'.
apply_prop_hyp max_measure_nonzero_eventually_all_locals_below max_measure.
eauto.
apply_prop_hyp eventually In.
eapply eventually_monotonic_simple; eauto.
intros [o s]; auto.
Qed.
Theorem local_measure_causes_max_measure_zero :
forall ex,
lb_execution ex ->
always local_measures_nonincreasing ex ->
always max_measure_nonzero_eventually_all_locals_below ex ->
continuously (now (measure_zero max_measure)) ex.
Proof.
intros.
destruct ex.
remember (max_measure (occ_gst o)) as n eqn:Hmax; symmetry in Hmax.
generalize dependent o.
generalize dependent ex.
induction n using nat_strong_ind; destruct n; intros.
- apply E0.
apply measure_zero_stays_zero; eauto using local_always_nonincreasing_causes_max_always_nonincreasing.
- find_copy_eapply_lem_hyp max_measure_continuously_decreasing_bound; eauto.
induction 0.
+ destruct s as [o' s].
remember (max_measure (occ_gst o')) as k eqn:Hk; symmetry in Hk.
eapply H; try eapply Hk; auto with arith.
unfold measure_bounded in *.
find_apply_lem_hyp always_Cons; break_and.
simpl in *.
omega.
+ apply E_next, IHeventually;
eauto using lb_execution_invar, always_invar.
Qed.
Lemma and_tl_always_P :
forall T (P Q : infseq T -> Prop) ex,
always (P /\_ Q) ex ->
always P ex.
Proof.
intros T P Q.
cofix c; intros.
constructor; destruct ex.
- invc_prop and_tl.
firstorder.
- simpl.
apply c.
eauto using always_invar.
Qed.
Lemma always_and_tl_eq :
forall T (P Q : infseq T -> Prop) ex,
always (P /\_ Q) ex <-> (always P /\_ always Q) ex.
Proof.
split; intros.
- split; eapply and_tl_always_P; eauto using always_and_tl_comm.
- inv_prop and_tl; eapply always_and_tl; eauto.
Qed.
Lemma always_continuously_and_tl :
forall T (P Q : infseq T -> Prop) s,
continuously (P /\_ Q) s ->
eventually (always P /\_ always Q) s.
Proof.
intros.
unfold continuously in *.
eapply eventually_monotonic_simple; [|eauto].
intros.
now apply always_and_tl_eq.
Qed.
Lemma local_measure_causes_measure_zero_continuosly :
forall ex,
lb_execution ex ->
continuously local_measures_nonincreasing ex ->
continuously nonzero_error_causes_measure_drop ex ->
continuously (now (measure_zero global_measure)) ex.
Proof.
intros.
pose proof local_measure_causes_measure_zero.
prep_always_monotonic.
apply eventually_idempotent.
eapply eventually_monotonic_simple; eauto.
match goal with
| |- eventually (always ?P /\_ always ?Q /\_ ?R) ex =>
cut (continuously (P /\_ Q /\_ R) ex)
end.
- intros.
find_apply_lem_hyp always_continuously_and_tl.
eapply eventually_monotonic_simple; [|eauto].
firstorder.
+ eapply always_and_tl_eq.
apply always_and_tl_comm.
eauto.
+ find_apply_lem_hyp always_and_tl_eq; inv_prop and_tl.
inv_prop lb_execution; auto.
- repeat apply continuously_and_tl; auto.
apply always_continuously.
apply always_inv;
eauto using lb_execution_invar.
Qed.
End LocalMeasure.
|
`timescale 1ns / 1ps
module controler_tb();
reg power, start_pause, weight_ch, mode_ch, clk_src;
wire power_light;
wire start_pause_light, water_in_light, washing_light, rinsing_light, dewatering_light, water_out_light;
wire [7:0]anodes, cnodes;
wire [2:0]weight_ch_light;
wire [2:0]state;
wire alarm;
parameter TIME = 1000, DELAY = 10;
controler #(32,0) CONTROLER (.power(power),
.start_pause(start_pause),
.weight_ch(weight_ch),
.mode_ch(mode_ch),
.clk_src(clk_src),
.start_pause_light(start_pause_light),
.weight_ch_light(weight_ch_light),
.water_in_light(water_in_light),
.washing_light(washing_light),
.rinsing_light(rinsing_light),
.dewatering_light(dewatering_light),
.water_out_light(water_out_light),
.power_light(power_light),
.state(state),
.alarm(alarm),
.anodes(anodes),
.cnodes(cnodes)
);
initial begin
power = 0;
clk_src = 0;
start_pause = 0;
weight_ch = 0;
mode_ch = 0;
#TIME $finish;
end
always begin
#(DELAY/10) clk_src = ~clk_src;
end
always begin
#(2*DELAY) mode_ch = 1;
#(2*DELAY) weight_ch = 1; mode_ch = 0; // cann't change when machine isn't turn on
#(2*DELAY) power = 1; weight_ch = 0;
#(2*DELAY) mode_ch = 1; weight_ch = 1;
#(DELAY/10) mode_ch = 0; weight_ch = 0;
#(2*DELAY) start_pause = 1;
#(2*DELAY) mode_ch = 1; weight_ch = 1; // cann't change when machine is start
#((2*DELAY)/10) mode_ch = 0; weight_ch = 0;
#(2*DELAY) start_pause = 0;
#(2*DELAY) mode_ch = 1; weight_ch = 1; // change when machine is pause
#(DELAY/10) mode_ch = 0; weight_ch = 0;
#(2*DELAY) start_pause = 1; // start in new mode
#(2*DELAY) start_pause = 0;
#(5*DELAY) start_pause = 1; // test start_pause
#(73*DELAY) ;
end
endmodule
|
// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_MATLAB_Function_block.v
// Created: 2014-09-08 14:12:04
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: controllerHdl_MATLAB_Function_block
// Source Path: controllerHdl/Field_Oriented_Control/Open_Loop_Control/Sin_Cos/Mark_Extract_Bits/MATLAB Function
// Hierarchy Level: 6
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module controllerHdl_MATLAB_Function_block
(
u,
y
);
input [17:0] u; // ufix18
output [8:0] y; // ufix9
wire [8:0] y1; // ufix9_E9
//MATLAB Function 'Open_Loop_Control/Sin_Cos/Mark_Extract_Bits/MATLAB Function': '<S37>:1'
// Non-tunable mask parameter
//'<S37>:1:8'
//'<S37>:1:10'
assign y1 = u[17:9];
//'<S37>:1:14'
assign y = y1;
endmodule // controllerHdl_MATLAB_Function_block
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
module read_cycle_tb;
reg RESET;
reg CLK14M;
wire CLK;
reg AS20;
reg DS20;
reg RW20;
reg [31:0] A;
reg [31:0] D_OUT;
reg [1:0] SIZ;
wire [1:0] DSACK;
wire RAMOE;
wire [1:0] RAS;
wire [3:0] CAS;
wire [31:0] D = RW20 ? {32{1'bz}} : D_OUT;
`include "common.vinc"
// Instantiate the Unit Under Test (UUT)
ramcpld uut (
.CLKCPU(CLK),
.RESET(RESET),
.AS20(AS20),
.DS20(DS20),
.RW20(RW20),
.DSACK(DSACK),
.PUNT (PUNT),
.SIZ(SIZ),
.A(A[23:0]),
.D (D[31:24]),
.IDEINT ( 1'b0 ),
.RAMOE (RAMOE),
.CAS (CAS),
.RAS (RAS),
.RAM_MUX(RAM_MUX)
);
integer i;
initial begin
$dumpfile("read_cycle.vcd");
$dumpvars(0, read_cycle_tb);
RESET = 1;
#10;
// Initialize Inputs
CLK14M = 0;
RESET = 0;
// Wait 100 ns for global reset to finish
#142;
RESET = 1;
#142;
SIZ = 2'b10;
// autoconfig the devices.
write(32'h00E8004a, 32'h9_0000000);
write(32'h00E80048, 32'hE_0000000);
write(32'h00E8004a, 32'h0_0000000);
write(32'h00E80048, 32'h2_0000000);
busidle();
for( i = 32'h200000; i < 32'h00210000; i++ ) begin
read(i);
busidle();
end
#1000000;
$finish;
end
assign CLK = CLK14M;
always begin
#71; CLK14M = ~CLK14M;
end
PULLUP PUNT_pullup (
.O(PUNT) // Pullup output (connect directly to top-level port)
);
PULLUP DSACK0_pullup (
.O(DSACK[0])
);
PULLUP DSACK1_pullup (
.O(DSACK[1])
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NOR4_FUNCTIONAL_V
`define SKY130_FD_SC_MS__NOR4_FUNCTIONAL_V
/**
* nor4: 4-input NOR.
*
* Y = !(A | B | C | D)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__nor4 (
Y,
A,
B,
C,
D
);
// Module ports
output Y;
input A;
input B;
input C;
input D;
// Local signals
wire nor0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out_Y, A, B, C, D );
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__NOR4_FUNCTIONAL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__AND3_2_V
`define SKY130_FD_SC_LP__AND3_2_V
/**
* and3: 3-input AND.
*
* Verilog wrapper for and3 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__and3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__and3_2 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__and3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__and3_2 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__and3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__AND3_2_V
|
/* -------------------------------------------------------------------------------
* (C)2007 Robert Mullins
* Computer Architecture Group, Computer Laboratory
* University of Cambridge, UK.
* -------------------------------------------------------------------------------
*
* Physical-Channel (Channel-level) Flow-Control
* ============================================
*
*
* Credit Counter Optimization (for credit-based flow-control)
* ===========================
*
* optimized_credit_counter = 0 | 1
*
* Set to '1' to move credit counter logic to start of next clock cycle.
* Remove add/sub from critical path.
*
* To move add/sub logic we buffer the last credit rec. and the any
* flit sent on the output.
*
*/
module LAG_pl_fc_out (flits_valid,
channel_cntrl_in,
pl_status, // pl_status[pl]=1 if blocked (fifo is full)
pl_empty, // pl_empty[pl]=1 if PL fifo is empty (credits=init_credits)
pl_credits,
clk, rst_n);
parameter num_pls = 4;
parameter init_credits = 4;
parameter optimized_credit_counter = 1;
// +1 as has to hold 'init_credits' value
parameter counter_bits = clogb2(init_credits+1);
input [num_pls-1:0] flits_valid;
input [num_pls-1:0] channel_cntrl_in;
output logic [num_pls-1:0] pl_status;
output [num_pls-1:0] pl_empty;
output [num_pls-1:0][counter_bits-1:0] pl_credits;
input clk, rst_n;
logic [num_pls-1:0][counter_bits-1:0] counter;
logic [num_pls-1:0] inc, dec;
// buffer credit and flit pl id.'s so we can move counter in credit counter optimization
logic [num_pls-1:0] last_flits_valid;
logic [num_pls-1:0] last_credits;
logic [num_pls-1:0][counter_bits-1:0] counter_current;
logic [num_pls-1:0] pl_empty;
genvar i;
// fsm states
parameter stop=1'b0, go=1'b1;
logic [num_pls-1:0] current_state, next_state;
generate
if (optimized_credit_counter) begin
// ***********************************
// optimized credit-counter (moves counter logic off critical path)
// ***********************************
always@(posedge clk) begin
last_credits <= channel_cntrl_in;
last_flits_valid <= flits_valid;
// $display ("empty=%b", pl_empty);
end
assign pl_credits = counter_current;
for (i=0; i<num_pls; i++) begin:perpl1
always_comb begin:addsub
if (inc[i] && !dec[i])
counter_current[i]=counter[i]+1;
else if (dec[i] && !inc[i])
counter_current[i]=counter[i]-1;
else
counter_current[i]=counter[i];
end
always@(posedge clk) begin
if (!rst_n) begin
counter[i]<=init_credits;
pl_empty[i]<='1;
end else begin
counter[i]<=counter_current[i];
if ((counter_current[i]==0) ||
((counter_current[i]==1) && flits_valid[i]) &&
!(channel_cntrl_in[i])) begin
pl_status[i] <= 1'b1;
pl_empty[i] <= 1'b0;
end else begin
pl_status[i] <= 1'b0;
pl_empty[i] <= (counter_current[i]==init_credits);
end
end // else: !if(!rst_n)
end // always@ (posedge clk)
assign inc[i] = last_credits[i];
assign dec[i] = last_flits_valid[i];
end
end else begin
assign pl_credits = counter;
// ***********************************
// unoptimized credit-counter
// ***********************************
for (i=0; i<num_pls; i++) begin:perpl
always@(posedge clk) begin
if (!rst_n) begin
counter[i]<=init_credits;
end else begin
if (inc[i] && !dec[i]) begin
assert (counter[i]!=init_credits) else $fatal;
counter[i]<=counter[i]+1;
end
if (dec[i] && !inc[i]) begin
assert (counter[i]!=0) else $fatal;
counter[i]<=counter[i]-1;
end
end // else: !if(!rst_n)
end
// received credit for PL i?
assign inc[i]= channel_cntrl_in[i];
// flit sent, one less credit
assign dec[i] = flits_valid[i];
// if counter==0, PL is blocked
assign pl_status[i]=(counter[i]==0);
// if counter==init_credits, PL buffer is empty
assign pl_empty[i]=(counter[i]==init_credits);
end // block: perpl
end
endgenerate
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
// Date : Mon Sep 18 12:52:54 2017
// Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ fifo_generator_0_stub.v
// Design : fifo_generator_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7k325tffg676-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "fifo_generator_v13_1_2,Vivado 2016.3" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(rst, wr_clk, rd_clk, din, wr_en, rd_en, dout, full,
almost_full, empty, almost_empty, rd_data_count, wr_data_count, prog_full, prog_empty)
/* synthesis syn_black_box black_box_pad_pin="rst,wr_clk,rd_clk,din[63:0],wr_en,rd_en,dout[63:0],full,almost_full,empty,almost_empty,rd_data_count[9:0],wr_data_count[9:0],prog_full,prog_empty" */;
input rst;
input wr_clk;
input rd_clk;
input [63:0]din;
input wr_en;
input rd_en;
output [63:0]dout;
output full;
output almost_full;
output empty;
output almost_empty;
output [9:0]rd_data_count;
output [9:0]wr_data_count;
output prog_full;
output prog_empty;
endmodule
|
(************************************************************************)
(* * The Coq Proof Assistant / The Coq Development Team *)
(* v * INRIA, CNRS and contributors - Copyright 1999-2018 *)
(* <O___,, * (see CREDITS file for the list of authors) *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(* * (see LICENSE file for the text of the license) *)
(************************************************************************)
(* This file is (C) Copyright 2006-2015 Microsoft Corporation and Inria. *)
Require Import Bool. (* For bool_scope delimiter 'bool'. *)
Require Import ssrmatching.
Declare ML Module "ssreflect_plugin".
(******************************************************************************)
(* This file is the Gallina part of the ssreflect plugin implementation. *)
(* Files that use the ssreflect plugin should always Require ssreflect and *)
(* either Import ssreflect or Import ssreflect.SsrSyntax. *)
(* Part of the contents of this file is technical and will only interest *)
(* advanced developers; in addition the following are defined: *)
(* [the str of v by f] == the Canonical s : str such that f s = v. *)
(* [the str of v] == the Canonical s : str that coerces to v. *)
(* argumentType c == the T such that c : forall x : T, P x. *)
(* returnType c == the R such that c : T -> R. *)
(* {type of c for s} == P s where c : forall x : T, P x. *)
(* phantom T v == singleton type with inhabitant Phantom T v. *)
(* phant T == singleton type with inhabitant Phant v. *)
(* =^~ r == the converse of rewriting rule r (e.g., in a *)
(* rewrite multirule). *)
(* unkeyed t == t, but treated as an unkeyed matching pattern by *)
(* the ssreflect matching algorithm. *)
(* nosimpl t == t, but on the right-hand side of Definition C := *)
(* nosimpl disables expansion of C by /=. *)
(* locked t == t, but locked t is not convertible to t. *)
(* locked_with k t == t, but not convertible to t or locked_with k' t *)
(* unless k = k' (with k : unit). Coq type-checking *)
(* will be much more efficient if locked_with with a *)
(* bespoke k is used for sealed definitions. *)
(* unlockable v == interface for sealed constant definitions of v. *)
(* Unlockable def == the unlockable that registers def : C = v. *)
(* [unlockable of C] == a clone for C of the canonical unlockable for the *)
(* definition of C (e.g., if it uses locked_with). *)
(* [unlockable fun C] == [unlockable of C] with the expansion forced to be *)
(* an explicit lambda expression. *)
(* -> The usage pattern for ADT operations is: *)
(* Definition foo_def x1 .. xn := big_foo_expression. *)
(* Fact foo_key : unit. Proof. by []. Qed. *)
(* Definition foo := locked_with foo_key foo_def. *)
(* Canonical foo_unlockable := [unlockable fun foo]. *)
(* This minimizes the comparison overhead for foo, while still allowing *)
(* rewrite unlock to expose big_foo_expression. *)
(* More information about these definitions and their use can be found in the *)
(* ssreflect manual, and in specific comments below. *)
(******************************************************************************)
Set Implicit Arguments.
Unset Strict Implicit.
Unset Printing Implicit Defensive.
Module SsrSyntax.
(* Declare Ssr keywords: 'is' 'of' '//' '/=' and '//='. We also declare the *)
(* parsing level 8, as a workaround for a notation grammar factoring problem. *)
(* Arguments of application-style notations (at level 10) should be declared *)
(* at level 8 rather than 9 or the camlp5 grammar will not factor properly. *)
Reserved Notation "(* x 'is' y 'of' z 'isn't' // /= //= *)" (at level 8).
Reserved Notation "(* 69 *)" (at level 69).
(* Non ambiguous keyword to check if the SsrSyntax module is imported *)
Reserved Notation "(* Use to test if 'SsrSyntax_is_Imported' *)" (at level 8).
Reserved Notation "<hidden n >" (at level 200).
Reserved Notation "T (* n *)" (at level 200, format "T (* n *)").
End SsrSyntax.
Export SsrMatchingSyntax.
Export SsrSyntax.
(* Make the general "if" into a notation, so that we can override it below. *)
(* The notations are "only parsing" because the Coq decompiler will not *)
(* recognize the expansion of the boolean if; using the default printer *)
(* avoids a spurrious trailing %GEN_IF. *)
Delimit Scope general_if_scope with GEN_IF.
Notation "'if' c 'then' v1 'else' v2" :=
(if c then v1 else v2)
(at level 200, c, v1, v2 at level 200, only parsing) : general_if_scope.
Notation "'if' c 'return' t 'then' v1 'else' v2" :=
(if c return t then v1 else v2)
(at level 200, c, t, v1, v2 at level 200, only parsing) : general_if_scope.
Notation "'if' c 'as' x 'return' t 'then' v1 'else' v2" :=
(if c as x return t then v1 else v2)
(at level 200, c, t, v1, v2 at level 200, x ident, only parsing)
: general_if_scope.
(* Force boolean interpretation of simple if expressions. *)
Delimit Scope boolean_if_scope with BOOL_IF.
Notation "'if' c 'return' t 'then' v1 'else' v2" :=
(if c%bool is true in bool return t then v1 else v2) : boolean_if_scope.
Notation "'if' c 'then' v1 'else' v2" :=
(if c%bool is true in bool return _ then v1 else v2) : boolean_if_scope.
Notation "'if' c 'as' x 'return' t 'then' v1 'else' v2" :=
(if c%bool is true as x in bool return t then v1 else v2) : boolean_if_scope.
Open Scope boolean_if_scope.
(* To allow a wider variety of notations without reserving a large number of *)
(* of identifiers, the ssreflect library systematically uses "forms" to *)
(* enclose complex mixfix syntax. A "form" is simply a mixfix expression *)
(* enclosed in square brackets and introduced by a keyword: *)
(* [keyword ... ] *)
(* Because the keyword follows a bracket it does not need to be reserved. *)
(* Non-ssreflect libraries that do not respect the form syntax (e.g., the Coq *)
(* Lists library) should be loaded before ssreflect so that their notations *)
(* do not mask all ssreflect forms. *)
Delimit Scope form_scope with FORM.
Open Scope form_scope.
(* Allow overloading of the cast (x : T) syntax, put whitespace around the *)
(* ":" symbol to avoid lexical clashes (and for consistency with the parsing *)
(* precedence of the notation, which binds less tightly than application), *)
(* and put printing boxes that print the type of a long definition on a *)
(* separate line rather than force-fit it at the right margin. *)
Notation "x : T" := (x : T)
(at level 100, right associativity,
format "'[hv' x '/ ' : T ']'") : core_scope.
(* Allow the casual use of notations like nat * nat for explicit Type *)
(* declarations. Note that (nat * nat : Type) is NOT equivalent to *)
(* (nat * nat)%type, whose inferred type is legacy type "Set". *)
Notation "T : 'Type'" := (T%type : Type)
(at level 100, only parsing) : core_scope.
(* Allow similarly Prop annotation for, e.g., rewrite multirules. *)
Notation "P : 'Prop'" := (P%type : Prop)
(at level 100, only parsing) : core_scope.
(* Constants for abstract: and [: name ] intro pattern *)
Definition abstract_lock := unit.
Definition abstract_key := tt.
Definition abstract (statement : Type) (id : nat) (lock : abstract_lock) :=
let: tt := lock in statement.
Notation "<hidden n >" := (abstract _ n _).
Notation "T (* n *)" := (abstract T n abstract_key).
(* Constants for tactic-views *)
Inductive external_view : Type := tactic_view of Type.
(* Syntax for referring to canonical structures: *)
(* [the struct_type of proj_val by proj_fun] *)
(* This form denotes the Canonical instance s of the Structure type *)
(* struct_type whose proj_fun projection is proj_val, i.e., such that *)
(* proj_fun s = proj_val. *)
(* Typically proj_fun will be A record field accessors of struct_type, but *)
(* this need not be the case; it can be, for instance, a field of a record *)
(* type to which struct_type coerces; proj_val will likewise be coerced to *)
(* the return type of proj_fun. In all but the simplest cases, proj_fun *)
(* should be eta-expanded to allow for the insertion of implicit arguments. *)
(* In the common case where proj_fun itself is a coercion, the "by" part *)
(* can be omitted entirely; in this case it is inferred by casting s to the *)
(* inferred type of proj_val. Obviously the latter can be fixed by using an *)
(* explicit cast on proj_val, and it is highly recommended to do so when the *)
(* return type intended for proj_fun is "Type", as the type inferred for *)
(* proj_val may vary because of sort polymorphism (it could be Set or Prop). *)
(* Note when using the [the _ of _] form to generate a substructure from a *)
(* telescopes-style canonical hierarchy (implementing inheritance with *)
(* coercions), one should always project or coerce the value to the BASE *)
(* structure, because Coq will only find a Canonical derived structure for *)
(* the Canonical base structure -- not for a base structure that is specific *)
(* to proj_value. *)
Module TheCanonical.
CoInductive put vT sT (v1 v2 : vT) (s : sT) := Put.
Definition get vT sT v s (p : @put vT sT v v s) := let: Put _ _ _ := p in s.
Definition get_by vT sT of sT -> vT := @get vT sT.
End TheCanonical.
Import TheCanonical. (* Note: no export. *)
Local Arguments get_by _%type_scope _%type_scope _ _ _ _.
Notation "[ 'the' sT 'of' v 'by' f ]" :=
(@get_by _ sT f _ _ ((fun v' (s : sT) => Put v' (f s) s) v _))
(at level 0, only parsing) : form_scope.
Notation "[ 'the' sT 'of' v ]" := (get ((fun s : sT => Put v (*coerce*)s s) _))
(at level 0, only parsing) : form_scope.
(* The following are "format only" versions of the above notations. Since Coq *)
(* doesn't provide this facility, we fake it by splitting the "the" keyword. *)
(* We need to do this to prevent the formatter from being be thrown off by *)
(* application collapsing, coercion insertion and beta reduction in the right *)
(* hand side of the notations above. *)
Notation "[ 'th' 'e' sT 'of' v 'by' f ]" := (@get_by _ sT f v _ _)
(at level 0, format "[ 'th' 'e' sT 'of' v 'by' f ]") : form_scope.
Notation "[ 'th' 'e' sT 'of' v ]" := (@get _ sT v _ _)
(at level 0, format "[ 'th' 'e' sT 'of' v ]") : form_scope.
(* We would like to recognize
Notation "[ 'th' 'e' sT 'of' v : 'Type' ]" := (@get Type sT v _ _)
(at level 0, format "[ 'th' 'e' sT 'of' v : 'Type' ]") : form_scope.
*)
(* Helper notation for canonical structure inheritance support. *)
(* This is a workaround for the poor interaction between delta reduction and *)
(* canonical projections in Coq's unification algorithm, by which transparent *)
(* definitions hide canonical instances, i.e., in *)
(* Canonical a_type_struct := @Struct a_type ... *)
(* Definition my_type := a_type. *)
(* my_type doesn't effectively inherit the struct structure from a_type. Our *)
(* solution is to redeclare the instance as follows *)
(* Canonical my_type_struct := Eval hnf in [struct of my_type]. *)
(* The special notation [str of _] must be defined for each Strucure "str" *)
(* with constructor "Str", typically as follows *)
(* Definition clone_str s := *)
(* let: Str _ x y ... z := s return {type of Str for s} -> str in *)
(* fun k => k _ x y ... z. *)
(* Notation "[ 'str' 'of' T 'for' s ]" := (@clone_str s (@Str T)) *)
(* (at level 0, format "[ 'str' 'of' T 'for' s ]") : form_scope. *)
(* Notation "[ 'str' 'of' T ]" := (repack_str (fun x => @Str T x)) *)
(* (at level 0, format "[ 'str' 'of' T ]") : form_scope. *)
(* The notation for the match return predicate is defined below; the eta *)
(* expansion in the second form serves both to distinguish it from the first *)
(* and to avoid the delta reduction problem. *)
(* There are several variations on the notation and the definition of the *)
(* the "clone" function, for telescopes, mixin classes, and join (multiple *)
(* inheritance) classes. We describe a different idiom for clones in ssrfun; *)
(* it uses phantom types (see below) and static unification; see fintype and *)
(* ssralg for examples. *)
Definition argumentType T P & forall x : T, P x := T.
Definition dependentReturnType T P & forall x : T, P x := P.
Definition returnType aT rT & aT -> rT := rT.
Notation "{ 'type' 'of' c 'for' s }" := (dependentReturnType c s)
(at level 0, format "{ 'type' 'of' c 'for' s }") : type_scope.
(* A generic "phantom" type (actually, a unit type with a phantom parameter). *)
(* This type can be used for type definitions that require some Structure *)
(* on one of their parameters, to allow Coq to infer said structure so it *)
(* does not have to be supplied explicitly or via the "[the _ of _]" notation *)
(* (the latter interacts poorly with other Notation). *)
(* The definition of a (co)inductive type with a parameter p : p_type, that *)
(* needs to use the operations of a structure *)
(* Structure p_str : Type := p_Str {p_repr :> p_type; p_op : p_repr -> ...} *)
(* should be given as *)
(* Inductive indt_type (p : p_str) := Indt ... . *)
(* Definition indt_of (p : p_str) & phantom p_type p := indt_type p. *)
(* Notation "{ 'indt' p }" := (indt_of (Phantom p)). *)
(* Definition indt p x y ... z : {indt p} := @Indt p x y ... z. *)
(* Notation "[ 'indt' x y ... z ]" := (indt x y ... z). *)
(* That is, the concrete type and its constructor should be shadowed by *)
(* definitions that use a phantom argument to infer and display the true *)
(* value of p (in practice, the "indt" constructor often performs additional *)
(* functions, like "locking" the representation -- see below). *)
(* We also define a simpler version ("phant" / "Phant") of phantom for the *)
(* common case where p_type is Type. *)
CoInductive phantom T (p : T) := Phantom.
Arguments phantom : clear implicits.
Arguments Phantom : clear implicits.
CoInductive phant (p : Type) := Phant.
(* Internal tagging used by the implementation of the ssreflect elim. *)
Definition protect_term (A : Type) (x : A) : A := x.
(* The ssreflect idiom for a non-keyed pattern: *)
(* - unkeyed t wiil match any subterm that unifies with t, regardless of *)
(* whether it displays the same head symbol as t. *)
(* - unkeyed t a b will match any application of a term f unifying with t, *)
(* to two arguments unifying with with a and b, repectively, regardless of *)
(* apparent head symbols. *)
(* - unkeyed x where x is a variable will match any subterm with the same *)
(* type as x (when x would raise the 'indeterminate pattern' error). *)
Notation unkeyed x := (let flex := x in flex).
(* Ssreflect converse rewrite rule rule idiom. *)
Definition ssr_converse R (r : R) := (Logic.I, r).
Notation "=^~ r" := (ssr_converse r) (at level 100) : form_scope.
(* Term tagging (user-level). *)
(* The ssreflect library uses four strengths of term tagging to restrict *)
(* convertibility during type checking: *)
(* nosimpl t simplifies to t EXCEPT in a definition; more precisely, given *)
(* Definition foo := nosimpl bar, foo (or foo t') will NOT be expanded by *)
(* the /= and //= switches unless it is in a forcing context (e.g., in *)
(* match foo t' with ... end, foo t' will be reduced if this allows the *)
(* match to be reduced). Note that nosimpl bar is simply notation for a *)
(* a term that beta-iota reduces to bar; hence rewrite /foo will replace *)
(* foo by bar, and rewrite -/foo will replace bar by foo. *)
(* CAVEAT: nosimpl should not be used inside a Section, because the end of *)
(* section "cooking" removes the iota redex. *)
(* locked t is provably equal to t, but is not convertible to t; 'locked' *)
(* provides support for selective rewriting, via the lock t : t = locked t *)
(* Lemma, and the ssreflect unlock tactic. *)
(* locked_with k t is equal but not convertible to t, much like locked t, *)
(* but supports explicit tagging with a value k : unit. This is used to *)
(* mitigate a flaw in the term comparison heuristic of the Coq kernel, *)
(* which treats all terms of the form locked t as equal and conpares their *)
(* arguments recursively, leading to an exponential blowup of comparison. *)
(* For this reason locked_with should be used rather than locked when *)
(* defining ADT operations. The unlock tactic does not support locked_with *)
(* but the unlock rewrite rule does, via the unlockable interface. *)
(* we also use Module Type ascription to create truly opaque constants, *)
(* because simple expansion of constants to reveal an unreducible term *)
(* doubles the time complexity of a negative comparison. Such opaque *)
(* constants can be expanded generically with the unlock rewrite rule. *)
(* See the definition of card and subset in fintype for examples of this. *)
Notation nosimpl t := (let: tt := tt in t).
Lemma master_key : unit. Proof. exact tt. Qed.
Definition locked A := let: tt := master_key in fun x : A => x.
Lemma lock A x : x = locked x :> A. Proof. unlock; reflexivity. Qed.
(* Needed for locked predicates, in particular for eqType's. *)
Lemma not_locked_false_eq_true : locked false <> true.
Proof. unlock; discriminate. Qed.
(* The basic closing tactic "done". *)
Ltac done :=
trivial; hnf; intros; solve
[ do ![solve [trivial | apply: sym_equal; trivial]
| discriminate | contradiction | split]
| case not_locked_false_eq_true; assumption
| match goal with H : ~ _ |- _ => solve [case H; trivial] end ].
(* Quicker done tactic not including split, syntax: /0/ *)
Ltac ssrdone0 :=
trivial; hnf; intros; solve
[ do ![solve [trivial | apply: sym_equal; trivial]
| discriminate | contradiction ]
| case not_locked_false_eq_true; assumption
| match goal with H : ~ _ |- _ => solve [case H; trivial] end ].
(* To unlock opaque constants. *)
Structure unlockable T v := Unlockable {unlocked : T; _ : unlocked = v}.
Lemma unlock T x C : @unlocked T x C = x. Proof. by case: C. Qed.
Notation "[ 'unlockable' 'of' C ]" := (@Unlockable _ _ C (unlock _))
(at level 0, format "[ 'unlockable' 'of' C ]") : form_scope.
Notation "[ 'unlockable' 'fun' C ]" := (@Unlockable _ (fun _ => _) C (unlock _))
(at level 0, format "[ 'unlockable' 'fun' C ]") : form_scope.
(* Generic keyed constant locking. *)
(* The argument order ensures that k is always compared before T. *)
Definition locked_with k := let: tt := k in fun T x => x : T.
(* This can be used as a cheap alternative to cloning the unlockable instance *)
(* below, but with caution as unkeyed matching can be expensive. *)
Lemma locked_withE T k x : unkeyed (locked_with k x) = x :> T.
Proof. by case: k. Qed.
(* Intensionaly, this instance will not apply to locked u. *)
Canonical locked_with_unlockable T k x :=
@Unlockable T x (locked_with k x) (locked_withE k x).
(* More accurate variant of unlock, and safer alternative to locked_withE. *)
Lemma unlock_with T k x : unlocked (locked_with_unlockable k x) = x :> T.
Proof. exact: unlock. Qed.
(* The internal lemmas for the have tactics. *)
Definition ssr_have Plemma Pgoal (step : Plemma) rest : Pgoal := rest step.
Arguments ssr_have Plemma [Pgoal].
Definition ssr_have_let Pgoal Plemma step
(rest : let x : Plemma := step in Pgoal) : Pgoal := rest.
Arguments ssr_have_let [Pgoal].
Definition ssr_suff Plemma Pgoal step (rest : Plemma) : Pgoal := step rest.
Arguments ssr_suff Plemma [Pgoal].
Definition ssr_wlog := ssr_suff.
Arguments ssr_wlog Plemma [Pgoal].
(* Internal N-ary congruence lemmas for the congr tactic. *)
Fixpoint nary_congruence_statement (n : nat)
: (forall B, (B -> B -> Prop) -> Prop) -> Prop :=
match n with
| O => fun k => forall B, k B (fun x1 x2 : B => x1 = x2)
| S n' =>
let k' A B e (f1 f2 : A -> B) :=
forall x1 x2, x1 = x2 -> (e (f1 x1) (f2 x2) : Prop) in
fun k => forall A, nary_congruence_statement n' (fun B e => k _ (k' A B e))
end.
Lemma nary_congruence n (k := fun B e => forall y : B, (e y y : Prop)) :
nary_congruence_statement n k.
Proof.
have: k _ _ := _; rewrite {1}/k.
elim: n k => [|n IHn] k k_P /= A; first exact: k_P.
by apply: IHn => B e He; apply: k_P => f x1 x2 <-.
Qed.
Lemma ssr_congr_arrow Plemma Pgoal : Plemma = Pgoal -> Plemma -> Pgoal.
Proof. by move->. Qed.
Arguments ssr_congr_arrow : clear implicits.
(* View lemmas that don't use reflection. *)
Section ApplyIff.
Variables P Q : Prop.
Hypothesis eqPQ : P <-> Q.
Lemma iffLR : P -> Q. Proof. by case: eqPQ. Qed.
Lemma iffRL : Q -> P. Proof. by case: eqPQ. Qed.
Lemma iffLRn : ~P -> ~Q. Proof. by move=> nP tQ; case: nP; case: eqPQ tQ. Qed.
Lemma iffRLn : ~Q -> ~P. Proof. by move=> nQ tP; case: nQ; case: eqPQ tP. Qed.
End ApplyIff.
Hint View for move/ iffLRn|2 iffRLn|2 iffLR|2 iffRL|2.
Hint View for apply/ iffRLn|2 iffLRn|2 iffRL|2 iffLR|2.
(* To focus non-ssreflect tactics on a subterm, eg vm_compute. *)
(* Usage: *)
(* elim/abstract_context: (pattern) => G defG. *)
(* vm_compute; rewrite {}defG {G}. *)
(* Note that vm_cast are not stored in the proof term *)
(* for reductions occuring in the context, hence *)
(* set here := pattern; vm_compute in (value of here) *)
(* blows up at Qed time. *)
Lemma abstract_context T (P : T -> Type) x :
(forall Q, Q = P -> Q x) -> P x.
Proof. by move=> /(_ P); apply. Qed.
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module fmcjesdadc1_spi (
spi_csn,
spi_clk,
spi_mosi,
spi_miso,
spi_sdio);
// parameters
localparam FMC27X_CPLD = 8'h00;
localparam FMC27X_AD9517 = 8'h84;
localparam FMC27X_AD9250_0 = 8'h80;
localparam FMC27X_AD9250_1 = 8'h81;
localparam FMC27X_AD9129_0 = 8'h82;
localparam FMC27X_AD9129_1 = 8'h83;
// 4-wire
input spi_csn;
input spi_clk;
input spi_mosi;
output spi_miso;
// 3-wire
inout spi_sdio;
// internal registers
reg [ 7:0] spi_devid = 'd0;
reg [ 5:0] spi_count = 'd0;
reg spi_rd_wr_n = 'd0;
reg spi_enable = 'd0;
// internal signals
wire spi_enable_s;
// check on rising edge and change on falling edge
assign spi_enable_s = spi_enable & ~spi_csn;
always @(posedge spi_clk or posedge spi_csn) begin
if (spi_csn == 1'b1) begin
spi_count <= 6'd0;
spi_devid <= 8'd0;
spi_rd_wr_n <= 1'd0;
end else begin
spi_count <= spi_count + 1'b1;
if (spi_count <= 6'd7) begin
spi_devid <= {spi_devid[6:0], spi_mosi};
end
if (spi_count == 6'd8) begin
spi_rd_wr_n <= spi_mosi;
end
end
end
always @(negedge spi_clk or posedge spi_csn) begin
if (spi_csn == 1'b1) begin
spi_enable <= 1'b0;
end else begin
if (((spi_count == 6'd16) && (spi_devid == FMC27X_CPLD)) ||
((spi_count == 6'd16) && (spi_devid == FMC27X_AD9129_0)) ||
((spi_count == 6'd16) && (spi_devid == FMC27X_AD9129_1)) ||
((spi_count == 6'd24) && (spi_devid == FMC27X_AD9517)) ||
((spi_count == 6'd24) && (spi_devid == FMC27X_AD9250_0)) ||
((spi_count == 6'd24) && (spi_devid == FMC27X_AD9250_1))) begin
spi_enable <= spi_rd_wr_n;
end
end
end
assign spi_miso = spi_sdio;
assign spi_sdio = (spi_enable_s == 1'b1) ? 1'bz : spi_mosi;
endmodule
// ***************************************************************************
// ***************************************************************************
|
//-------------------------------------------------------------------
//
// COPYRIGHT (C) 2011, VIPcore Group, Fudan University
//
// THIS FILE MAY NOT BE MODIFIED OR REDISTRIBUTED WITHOUT THE
// EXPRESSED WRITTEN CONSENT OF VIPcore Group
//
// VIPcore : http://soc.fudan.edu.cn/vip
// IP Owner : Yibo FAN
// Contact : [email protected]
//-------------------------------------------------------------------
// Filename : ram_2p.v
// Author : Yibo FAN
// Created : 2012-04-01
// Description : Dual Port Ram Model
//
// $Id$
//-------------------------------------------------------------------
`include "enc_defines.v"
module ram_2p (
clka ,
cena_i ,
oena_i ,
wena_i ,
addra_i ,
dataa_o ,
dataa_i ,
clkb ,
cenb_i ,
oenb_i ,
wenb_i ,
addrb_i ,
datab_o ,
datab_i
);
// ********************************************
//
// Parameter DECLARATION
//
// ********************************************
parameter Word_Width=32;
parameter Addr_Width=8;
// ********************************************
//
// Input/Output DECLARATION
//
// ********************************************
// A port
input clka; // clock input
input cena_i; // chip enable, low active
input oena_i; // data output enable, low active
input wena_i; // write enable, low active
input [Addr_Width-1:0] addra_i; // address input
input [Word_Width-1:0] dataa_i; // data input
output [Word_Width-1:0] dataa_o; // data output
// B Port
input clkb; // clock input
input cenb_i; // chip enable, low active
input oenb_i; // data output enable, low active
input wenb_i; // write enable, low active
input [Addr_Width-1:0] addrb_i; // address input
input [Word_Width-1:0] datab_i; // data input
output [Word_Width-1:0] datab_o; // data output
// ********************************************
//
// Register DECLARATION
//
// ********************************************
reg [Word_Width-1:0] mem_array[(1<<Addr_Width)-1:0];
// ********************************************
//
// Wire DECLARATION
//
// ********************************************
reg [Word_Width-1:0] dataa_r;
reg [Word_Width-1:0] datab_r;
// ********************************************
//
// Logic DECLARATION
//
// ********************************************
// -- A Port --//
always @(posedge clka) begin
if(!cena_i && !wena_i)
mem_array[addra_i] <= dataa_i;
end
always @(posedge clka) begin
if (!cena_i && wena_i)
dataa_r <= mem_array[addra_i];
else
dataa_r <= 'bx;
end
assign dataa_o = oena_i ? 'bz : dataa_r;
// -- B Port --//
always @(posedge clkb) begin
if(!cenb_i && !wenb_i)
mem_array[addrb_i] <= datab_i;
end
always @(posedge clkb) begin
if (!cenb_i && wenb_i)
datab_r <= mem_array[addrb_i];
else
datab_r <= 'bx;
end
assign datab_o = oenb_i ? 'bz : datab_r;
endmodule
|
/*
* Copyright 2018-2022 F4PGA Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
module top
(
input wire clk,
output wire ser_tx,
input wire ser_rx,
input wire [15:0] sw,
output wire [15:0] led
);
// ============================================================================
reg rst = 1;
reg rst1 = 1;
reg rst2 = 1;
reg rst3 = 1;
assign led[0] = rst;
assign led[13:1] = sw[13:1];
assign led[14] = ^sw;
assign led[15] = ser_rx;
always @(posedge clk) begin
rst3 <= 0;
rst2 <= rst3;
rst1 <= rst2;
rst <= rst1;
end
// ============================================================================
//
scalable_proc #
(
.NUM_PROCESSING_UNITS (1),
.UART_PRESCALER ((100000000) / (500000))
)
scalable_proc
(
.CLK (clk),
.RST (rst),
.UART_TX (ser_tx),
.UART_RX (ser_rx)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SDFXBP_1_V
`define SKY130_FD_SC_LS__SDFXBP_1_V
/**
* sdfxbp: Scan delay flop, non-inverted clock, complementary outputs.
*
* Verilog wrapper for sdfxbp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__sdfxbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__sdfxbp_1 (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__sdfxbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__sdfxbp_1 (
Q ,
Q_N,
CLK,
D ,
SCD,
SCE
);
output Q ;
output Q_N;
input CLK;
input D ;
input SCD;
input SCE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__sdfxbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__SDFXBP_1_V
|
// hps_sdram.v
// This file was auto-generated from altera_mem_if_hps_emif_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 14.0 200 at 2015.04.26.20:40:26
`timescale 1 ps / 1 ps
module hps_sdram (
input wire pll_ref_clk, // pll_ref_clk.clk
input wire global_reset_n, // global_reset.reset_n
input wire soft_reset_n, // soft_reset.reset_n
output wire [14:0] mem_a, // memory.mem_a
output wire [2:0] mem_ba, // .mem_ba
output wire [0:0] mem_ck, // .mem_ck
output wire [0:0] mem_ck_n, // .mem_ck_n
output wire [0:0] mem_cke, // .mem_cke
output wire [0:0] mem_cs_n, // .mem_cs_n
output wire [3:0] mem_dm, // .mem_dm
output wire [0:0] mem_ras_n, // .mem_ras_n
output wire [0:0] mem_cas_n, // .mem_cas_n
output wire [0:0] mem_we_n, // .mem_we_n
output wire mem_reset_n, // .mem_reset_n
inout wire [31:0] mem_dq, // .mem_dq
inout wire [3:0] mem_dqs, // .mem_dqs
inout wire [3:0] mem_dqs_n, // .mem_dqs_n
output wire [0:0] mem_odt, // .mem_odt
input wire oct_rzqin // oct.rzqin
);
wire pll_afi_clk_clk; // pll:afi_clk -> [c0:afi_clk, p0:afi_clk]
wire pll_afi_half_clk_clk; // pll:afi_half_clk -> [c0:afi_half_clk, p0:afi_half_clk]
wire [3:0] p0_afi_afi_wlat; // p0:afi_wlat -> c0:afi_wlat
wire [0:0] p0_afi_afi_rdata_valid; // p0:afi_rdata_valid -> c0:afi_rdata_valid
wire p0_afi_afi_cal_success; // p0:afi_cal_success -> c0:afi_cal_success
wire [4:0] p0_afi_afi_rlat; // p0:afi_rlat -> c0:afi_rlat
wire [79:0] p0_afi_afi_rdata; // p0:afi_rdata -> c0:afi_rdata
wire p0_afi_afi_cal_fail; // p0:afi_cal_fail -> c0:afi_cal_fail
wire p0_afi_reset_reset; // p0:afi_reset_n -> c0:afi_reset_n
wire [1:0] c0_afi_afi_cs_n; // c0:afi_cs_n -> p0:afi_cs_n
wire [1:0] c0_afi_afi_cke; // c0:afi_cke -> p0:afi_cke
wire [0:0] c0_afi_afi_ras_n; // c0:afi_ras_n -> p0:afi_ras_n
wire [0:0] c0_afi_afi_mem_clk_disable; // c0:afi_mem_clk_disable -> p0:afi_mem_clk_disable
wire [9:0] c0_afi_afi_dm; // c0:afi_dm -> p0:afi_dm
wire [1:0] c0_afi_afi_odt; // c0:afi_odt -> p0:afi_odt
wire [19:0] c0_afi_afi_addr; // c0:afi_addr -> p0:afi_addr
wire [4:0] c0_afi_afi_rdata_en_full; // c0:afi_rdata_en_full -> p0:afi_rdata_en_full
wire [0:0] c0_afi_afi_we_n; // c0:afi_we_n -> p0:afi_we_n
wire [2:0] c0_afi_afi_ba; // c0:afi_ba -> p0:afi_ba
wire [79:0] c0_afi_afi_wdata; // c0:afi_wdata -> p0:afi_wdata
wire [4:0] c0_afi_afi_rdata_en; // c0:afi_rdata_en -> p0:afi_rdata_en
wire [0:0] c0_afi_afi_rst_n; // c0:afi_rst_n -> p0:afi_rst_n
wire [0:0] c0_afi_afi_cas_n; // c0:afi_cas_n -> p0:afi_cas_n
wire [4:0] c0_afi_afi_wdata_valid; // c0:afi_wdata_valid -> p0:afi_wdata_valid
wire [4:0] c0_afi_afi_dqs_burst; // c0:afi_dqs_burst -> p0:afi_dqs_burst
wire [7:0] c0_hard_phy_cfg_cfg_addlat; // c0:cfg_addlat -> p0:cfg_addlat
wire [7:0] c0_hard_phy_cfg_cfg_rowaddrwidth; // c0:cfg_rowaddrwidth -> p0:cfg_rowaddrwidth
wire [7:0] c0_hard_phy_cfg_cfg_csaddrwidth; // c0:cfg_csaddrwidth -> p0:cfg_csaddrwidth
wire [7:0] c0_hard_phy_cfg_cfg_devicewidth; // c0:cfg_devicewidth -> p0:cfg_devicewidth
wire [7:0] c0_hard_phy_cfg_cfg_interfacewidth; // c0:cfg_interfacewidth -> p0:cfg_interfacewidth
wire [7:0] c0_hard_phy_cfg_cfg_tcl; // c0:cfg_tcl -> p0:cfg_tcl
wire [7:0] c0_hard_phy_cfg_cfg_coladdrwidth; // c0:cfg_coladdrwidth -> p0:cfg_coladdrwidth
wire [15:0] c0_hard_phy_cfg_cfg_trefi; // c0:cfg_trefi -> p0:cfg_trefi
wire [23:0] c0_hard_phy_cfg_cfg_dramconfig; // c0:cfg_dramconfig -> p0:cfg_dramconfig
wire [7:0] c0_hard_phy_cfg_cfg_caswrlat; // c0:cfg_caswrlat -> p0:cfg_caswrlat
wire [7:0] c0_hard_phy_cfg_cfg_trfc; // c0:cfg_trfc -> p0:cfg_trfc
wire [7:0] c0_hard_phy_cfg_cfg_bankaddrwidth; // c0:cfg_bankaddrwidth -> p0:cfg_bankaddrwidth
wire [7:0] c0_hard_phy_cfg_cfg_twr; // c0:cfg_twr -> p0:cfg_twr
wire [7:0] c0_hard_phy_cfg_cfg_tmrd; // c0:cfg_tmrd -> p0:cfg_tmrd
wire p0_ctl_clk_clk; // p0:ctl_clk -> c0:ctl_clk
wire p0_ctl_reset_reset; // p0:ctl_reset_n -> c0:ctl_reset_n
wire p0_io_int_io_intaficalsuccess; // p0:io_intaficalsuccess -> c0:io_intaficalsuccess
wire p0_io_int_io_intaficalfail; // p0:io_intaficalfail -> c0:io_intaficalfail
wire [15:0] oct_oct_sharing_parallelterminationcontrol; // oct:parallelterminationcontrol -> p0:parallelterminationcontrol
wire [15:0] oct_oct_sharing_seriesterminationcontrol; // oct:seriesterminationcontrol -> p0:seriesterminationcontrol
wire pll_pll_sharing_pll_mem_phy_clk; // pll:pll_mem_phy_clk -> p0:pll_mem_phy_clk
wire pll_pll_sharing_pll_avl_clk; // pll:pll_avl_clk -> p0:pll_avl_clk
wire pll_pll_sharing_pll_avl_phy_clk; // pll:pll_avl_phy_clk -> p0:pll_avl_phy_clk
wire pll_pll_sharing_afi_phy_clk; // pll:afi_phy_clk -> p0:afi_phy_clk
wire pll_pll_sharing_pll_config_clk; // pll:pll_config_clk -> p0:pll_config_clk
wire pll_pll_sharing_pll_addr_cmd_clk; // pll:pll_addr_cmd_clk -> p0:pll_addr_cmd_clk
wire pll_pll_sharing_pll_mem_clk; // pll:pll_mem_clk -> p0:pll_mem_clk
wire pll_pll_sharing_pll_locked; // pll:pll_locked -> p0:pll_locked
wire pll_pll_sharing_pll_write_clk_pre_phy_clk; // pll:pll_write_clk_pre_phy_clk -> p0:pll_write_clk_pre_phy_clk
wire pll_pll_sharing_pll_write_clk; // pll:pll_write_clk -> p0:pll_write_clk
wire p0_dll_clk_clk; // p0:dll_clk -> dll:clk
wire p0_dll_sharing_dll_pll_locked; // p0:dll_pll_locked -> dll:dll_pll_locked
wire [6:0] dll_dll_sharing_dll_delayctrl; // dll:dll_delayctrl -> p0:dll_delayctrl
hps_sdram_pll pll (
.global_reset_n (global_reset_n), // global_reset.reset_n
.pll_ref_clk (pll_ref_clk), // pll_ref_clk.clk
.afi_clk (pll_afi_clk_clk), // afi_clk.clk
.afi_half_clk (pll_afi_half_clk_clk), // afi_half_clk.clk
.pll_mem_clk (pll_pll_sharing_pll_mem_clk), // pll_sharing.pll_mem_clk
.pll_write_clk (pll_pll_sharing_pll_write_clk), // .pll_write_clk
.pll_locked (pll_pll_sharing_pll_locked), // .pll_locked
.pll_write_clk_pre_phy_clk (pll_pll_sharing_pll_write_clk_pre_phy_clk), // .pll_write_clk_pre_phy_clk
.pll_addr_cmd_clk (pll_pll_sharing_pll_addr_cmd_clk), // .pll_addr_cmd_clk
.pll_avl_clk (pll_pll_sharing_pll_avl_clk), // .pll_avl_clk
.pll_config_clk (pll_pll_sharing_pll_config_clk), // .pll_config_clk
.pll_mem_phy_clk (pll_pll_sharing_pll_mem_phy_clk), // .pll_mem_phy_clk
.afi_phy_clk (pll_pll_sharing_afi_phy_clk), // .afi_phy_clk
.pll_avl_phy_clk (pll_pll_sharing_pll_avl_phy_clk) // .pll_avl_phy_clk
);
hps_sdram_p0 p0 (
.global_reset_n (global_reset_n), // global_reset.reset_n
.soft_reset_n (soft_reset_n), // soft_reset.reset_n
.afi_reset_n (p0_afi_reset_reset), // afi_reset.reset_n
.afi_reset_export_n (), // afi_reset_export.reset_n
.ctl_reset_n (p0_ctl_reset_reset), // ctl_reset.reset_n
.afi_clk (pll_afi_clk_clk), // afi_clk.clk
.afi_half_clk (pll_afi_half_clk_clk), // afi_half_clk.clk
.ctl_clk (p0_ctl_clk_clk), // ctl_clk.clk
.avl_clk (), // avl_clk.clk
.avl_reset_n (), // avl_reset.reset_n
.scc_clk (), // scc_clk.clk
.scc_reset_n (), // scc_reset.reset_n
.avl_address (), // avl.address
.avl_write (), // .write
.avl_writedata (), // .writedata
.avl_read (), // .read
.avl_readdata (), // .readdata
.avl_waitrequest (), // .waitrequest
.dll_clk (p0_dll_clk_clk), // dll_clk.clk
.afi_addr (c0_afi_afi_addr), // afi.afi_addr
.afi_ba (c0_afi_afi_ba), // .afi_ba
.afi_cke (c0_afi_afi_cke), // .afi_cke
.afi_cs_n (c0_afi_afi_cs_n), // .afi_cs_n
.afi_ras_n (c0_afi_afi_ras_n), // .afi_ras_n
.afi_we_n (c0_afi_afi_we_n), // .afi_we_n
.afi_cas_n (c0_afi_afi_cas_n), // .afi_cas_n
.afi_rst_n (c0_afi_afi_rst_n), // .afi_rst_n
.afi_odt (c0_afi_afi_odt), // .afi_odt
.afi_dqs_burst (c0_afi_afi_dqs_burst), // .afi_dqs_burst
.afi_wdata_valid (c0_afi_afi_wdata_valid), // .afi_wdata_valid
.afi_wdata (c0_afi_afi_wdata), // .afi_wdata
.afi_dm (c0_afi_afi_dm), // .afi_dm
.afi_rdata (p0_afi_afi_rdata), // .afi_rdata
.afi_rdata_en (c0_afi_afi_rdata_en), // .afi_rdata_en
.afi_rdata_en_full (c0_afi_afi_rdata_en_full), // .afi_rdata_en_full
.afi_rdata_valid (p0_afi_afi_rdata_valid), // .afi_rdata_valid
.afi_wlat (p0_afi_afi_wlat), // .afi_wlat
.afi_rlat (p0_afi_afi_rlat), // .afi_rlat
.afi_cal_success (p0_afi_afi_cal_success), // .afi_cal_success
.afi_cal_fail (p0_afi_afi_cal_fail), // .afi_cal_fail
.scc_data (), // scc.scc_data
.scc_dqs_ena (), // .scc_dqs_ena
.scc_dqs_io_ena (), // .scc_dqs_io_ena
.scc_dq_ena (), // .scc_dq_ena
.scc_dm_ena (), // .scc_dm_ena
.capture_strobe_tracking (), // .capture_strobe_tracking
.scc_upd (), // .scc_upd
.cfg_addlat (c0_hard_phy_cfg_cfg_addlat), // hard_phy_cfg.cfg_addlat
.cfg_bankaddrwidth (c0_hard_phy_cfg_cfg_bankaddrwidth), // .cfg_bankaddrwidth
.cfg_caswrlat (c0_hard_phy_cfg_cfg_caswrlat), // .cfg_caswrlat
.cfg_coladdrwidth (c0_hard_phy_cfg_cfg_coladdrwidth), // .cfg_coladdrwidth
.cfg_csaddrwidth (c0_hard_phy_cfg_cfg_csaddrwidth), // .cfg_csaddrwidth
.cfg_devicewidth (c0_hard_phy_cfg_cfg_devicewidth), // .cfg_devicewidth
.cfg_dramconfig (c0_hard_phy_cfg_cfg_dramconfig), // .cfg_dramconfig
.cfg_interfacewidth (c0_hard_phy_cfg_cfg_interfacewidth), // .cfg_interfacewidth
.cfg_rowaddrwidth (c0_hard_phy_cfg_cfg_rowaddrwidth), // .cfg_rowaddrwidth
.cfg_tcl (c0_hard_phy_cfg_cfg_tcl), // .cfg_tcl
.cfg_tmrd (c0_hard_phy_cfg_cfg_tmrd), // .cfg_tmrd
.cfg_trefi (c0_hard_phy_cfg_cfg_trefi), // .cfg_trefi
.cfg_trfc (c0_hard_phy_cfg_cfg_trfc), // .cfg_trfc
.cfg_twr (c0_hard_phy_cfg_cfg_twr), // .cfg_twr
.afi_mem_clk_disable (c0_afi_afi_mem_clk_disable), // afi_mem_clk_disable.afi_mem_clk_disable
.pll_mem_clk (pll_pll_sharing_pll_mem_clk), // pll_sharing.pll_mem_clk
.pll_write_clk (pll_pll_sharing_pll_write_clk), // .pll_write_clk
.pll_locked (pll_pll_sharing_pll_locked), // .pll_locked
.pll_write_clk_pre_phy_clk (pll_pll_sharing_pll_write_clk_pre_phy_clk), // .pll_write_clk_pre_phy_clk
.pll_addr_cmd_clk (pll_pll_sharing_pll_addr_cmd_clk), // .pll_addr_cmd_clk
.pll_avl_clk (pll_pll_sharing_pll_avl_clk), // .pll_avl_clk
.pll_config_clk (pll_pll_sharing_pll_config_clk), // .pll_config_clk
.pll_mem_phy_clk (pll_pll_sharing_pll_mem_phy_clk), // .pll_mem_phy_clk
.afi_phy_clk (pll_pll_sharing_afi_phy_clk), // .afi_phy_clk
.pll_avl_phy_clk (pll_pll_sharing_pll_avl_phy_clk), // .pll_avl_phy_clk
.dll_pll_locked (p0_dll_sharing_dll_pll_locked), // dll_sharing.dll_pll_locked
.dll_delayctrl (dll_dll_sharing_dll_delayctrl), // .dll_delayctrl
.seriesterminationcontrol (oct_oct_sharing_seriesterminationcontrol), // oct_sharing.seriesterminationcontrol
.parallelterminationcontrol (oct_oct_sharing_parallelterminationcontrol), // .parallelterminationcontrol
.mem_a (mem_a), // memory.mem_a
.mem_ba (mem_ba), // .mem_ba
.mem_ck (mem_ck), // .mem_ck
.mem_ck_n (mem_ck_n), // .mem_ck_n
.mem_cke (mem_cke), // .mem_cke
.mem_cs_n (mem_cs_n), // .mem_cs_n
.mem_dm (mem_dm), // .mem_dm
.mem_ras_n (mem_ras_n), // .mem_ras_n
.mem_cas_n (mem_cas_n), // .mem_cas_n
.mem_we_n (mem_we_n), // .mem_we_n
.mem_reset_n (mem_reset_n), // .mem_reset_n
.mem_dq (mem_dq), // .mem_dq
.mem_dqs (mem_dqs), // .mem_dqs
.mem_dqs_n (mem_dqs_n), // .mem_dqs_n
.mem_odt (mem_odt), // .mem_odt
.io_intaficalfail (p0_io_int_io_intaficalfail), // io_int.io_intaficalfail
.io_intaficalsuccess (p0_io_int_io_intaficalsuccess), // .io_intaficalsuccess
.csr_soft_reset_req (1'b0), // (terminated)
.io_intaddrdout (64'b0000000000000000000000000000000000000000000000000000000000000000), // (terminated)
.io_intbadout (12'b000000000000), // (terminated)
.io_intcasndout (4'b0000), // (terminated)
.io_intckdout (4'b0000), // (terminated)
.io_intckedout (8'b00000000), // (terminated)
.io_intckndout (4'b0000), // (terminated)
.io_intcsndout (8'b00000000), // (terminated)
.io_intdmdout (20'b00000000000000000000), // (terminated)
.io_intdqdin (), // (terminated)
.io_intdqdout (180'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), // (terminated)
.io_intdqoe (90'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), // (terminated)
.io_intdqsbdout (20'b00000000000000000000), // (terminated)
.io_intdqsboe (10'b0000000000), // (terminated)
.io_intdqsdout (20'b00000000000000000000), // (terminated)
.io_intdqslogicdqsena (10'b0000000000), // (terminated)
.io_intdqslogicfiforeset (5'b00000), // (terminated)
.io_intdqslogicincrdataen (10'b0000000000), // (terminated)
.io_intdqslogicincwrptr (10'b0000000000), // (terminated)
.io_intdqslogicoct (10'b0000000000), // (terminated)
.io_intdqslogicrdatavalid (), // (terminated)
.io_intdqslogicreadlatency (25'b0000000000000000000000000), // (terminated)
.io_intdqsoe (10'b0000000000), // (terminated)
.io_intodtdout (8'b00000000), // (terminated)
.io_intrasndout (4'b0000), // (terminated)
.io_intresetndout (4'b0000), // (terminated)
.io_intwendout (4'b0000), // (terminated)
.io_intafirlat (), // (terminated)
.io_intafiwlat () // (terminated)
);
altera_mem_if_hhp_qseq_synth_top #(
.MEM_IF_DM_WIDTH (4),
.MEM_IF_DQS_WIDTH (4),
.MEM_IF_CS_WIDTH (1),
.MEM_IF_DQ_WIDTH (32)
) seq (
);
altera_mem_if_hard_memory_controller_top_cyclonev #(
.MEM_IF_DQS_WIDTH (4),
.MEM_IF_CS_WIDTH (1),
.MEM_IF_CHIP_BITS (1),
.MEM_IF_CLK_PAIR_COUNT (1),
.CSR_ADDR_WIDTH (10),
.CSR_DATA_WIDTH (8),
.CSR_BE_WIDTH (1),
.AVL_ADDR_WIDTH (27),
.AVL_DATA_WIDTH (64),
.AVL_SIZE_WIDTH (3),
.AVL_DATA_WIDTH_PORT_0 (1),
.AVL_ADDR_WIDTH_PORT_0 (1),
.AVL_NUM_SYMBOLS_PORT_0 (1),
.LSB_WFIFO_PORT_0 (5),
.MSB_WFIFO_PORT_0 (5),
.LSB_RFIFO_PORT_0 (5),
.MSB_RFIFO_PORT_0 (5),
.AVL_DATA_WIDTH_PORT_1 (1),
.AVL_ADDR_WIDTH_PORT_1 (1),
.AVL_NUM_SYMBOLS_PORT_1 (1),
.LSB_WFIFO_PORT_1 (5),
.MSB_WFIFO_PORT_1 (5),
.LSB_RFIFO_PORT_1 (5),
.MSB_RFIFO_PORT_1 (5),
.AVL_DATA_WIDTH_PORT_2 (1),
.AVL_ADDR_WIDTH_PORT_2 (1),
.AVL_NUM_SYMBOLS_PORT_2 (1),
.LSB_WFIFO_PORT_2 (5),
.MSB_WFIFO_PORT_2 (5),
.LSB_RFIFO_PORT_2 (5),
.MSB_RFIFO_PORT_2 (5),
.AVL_DATA_WIDTH_PORT_3 (1),
.AVL_ADDR_WIDTH_PORT_3 (1),
.AVL_NUM_SYMBOLS_PORT_3 (1),
.LSB_WFIFO_PORT_3 (5),
.MSB_WFIFO_PORT_3 (5),
.LSB_RFIFO_PORT_3 (5),
.MSB_RFIFO_PORT_3 (5),
.AVL_DATA_WIDTH_PORT_4 (1),
.AVL_ADDR_WIDTH_PORT_4 (1),
.AVL_NUM_SYMBOLS_PORT_4 (1),
.LSB_WFIFO_PORT_4 (5),
.MSB_WFIFO_PORT_4 (5),
.LSB_RFIFO_PORT_4 (5),
.MSB_RFIFO_PORT_4 (5),
.AVL_DATA_WIDTH_PORT_5 (1),
.AVL_ADDR_WIDTH_PORT_5 (1),
.AVL_NUM_SYMBOLS_PORT_5 (1),
.LSB_WFIFO_PORT_5 (5),
.MSB_WFIFO_PORT_5 (5),
.LSB_RFIFO_PORT_5 (5),
.MSB_RFIFO_PORT_5 (5),
.ENUM_ATTR_COUNTER_ONE_RESET ("DISABLED"),
.ENUM_ATTR_COUNTER_ZERO_RESET ("DISABLED"),
.ENUM_ATTR_STATIC_CONFIG_VALID ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_0 ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_1 ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_2 ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_3 ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_4 ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_5 ("DISABLED"),
.ENUM_CAL_REQ ("DISABLED"),
.ENUM_CFG_BURST_LENGTH ("BL_8"),
.ENUM_CFG_INTERFACE_WIDTH ("DWIDTH_32"),
.ENUM_CFG_SELF_RFSH_EXIT_CYCLES ("SELF_RFSH_EXIT_CYCLES_512"),
.ENUM_CFG_STARVE_LIMIT ("STARVE_LIMIT_10"),
.ENUM_CFG_TYPE ("DDR3"),
.ENUM_CLOCK_OFF_0 ("DISABLED"),
.ENUM_CLOCK_OFF_1 ("DISABLED"),
.ENUM_CLOCK_OFF_2 ("DISABLED"),
.ENUM_CLOCK_OFF_3 ("DISABLED"),
.ENUM_CLOCK_OFF_4 ("DISABLED"),
.ENUM_CLOCK_OFF_5 ("DISABLED"),
.ENUM_CLR_INTR ("NO_CLR_INTR"),
.ENUM_CMD_PORT_IN_USE_0 ("FALSE"),
.ENUM_CMD_PORT_IN_USE_1 ("FALSE"),
.ENUM_CMD_PORT_IN_USE_2 ("FALSE"),
.ENUM_CMD_PORT_IN_USE_3 ("FALSE"),
.ENUM_CMD_PORT_IN_USE_4 ("FALSE"),
.ENUM_CMD_PORT_IN_USE_5 ("FALSE"),
.ENUM_CPORT0_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT0_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT0_TYPE ("DISABLE"),
.ENUM_CPORT0_WFIFO_MAP ("FIFO_0"),
.ENUM_CPORT1_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT1_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT1_TYPE ("DISABLE"),
.ENUM_CPORT1_WFIFO_MAP ("FIFO_0"),
.ENUM_CPORT2_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT2_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT2_TYPE ("DISABLE"),
.ENUM_CPORT2_WFIFO_MAP ("FIFO_0"),
.ENUM_CPORT3_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT3_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT3_TYPE ("DISABLE"),
.ENUM_CPORT3_WFIFO_MAP ("FIFO_0"),
.ENUM_CPORT4_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT4_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT4_TYPE ("DISABLE"),
.ENUM_CPORT4_WFIFO_MAP ("FIFO_0"),
.ENUM_CPORT5_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT5_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT5_TYPE ("DISABLE"),
.ENUM_CPORT5_WFIFO_MAP ("FIFO_0"),
.ENUM_CTL_ADDR_ORDER ("CHIP_ROW_BANK_COL"),
.ENUM_CTL_ECC_ENABLED ("CTL_ECC_DISABLED"),
.ENUM_CTL_ECC_RMW_ENABLED ("CTL_ECC_RMW_DISABLED"),
.ENUM_CTL_REGDIMM_ENABLED ("REGDIMM_DISABLED"),
.ENUM_CTL_USR_REFRESH ("CTL_USR_REFRESH_DISABLED"),
.ENUM_CTRL_WIDTH ("DATA_WIDTH_64_BIT"),
.ENUM_DELAY_BONDING ("BONDING_LATENCY_0"),
.ENUM_DFX_BYPASS_ENABLE ("DFX_BYPASS_DISABLED"),
.ENUM_DISABLE_MERGING ("MERGING_ENABLED"),
.ENUM_ECC_DQ_WIDTH ("ECC_DQ_WIDTH_0"),
.ENUM_ENABLE_ATPG ("DISABLED"),
.ENUM_ENABLE_BONDING_0 ("DISABLED"),
.ENUM_ENABLE_BONDING_1 ("DISABLED"),
.ENUM_ENABLE_BONDING_2 ("DISABLED"),
.ENUM_ENABLE_BONDING_3 ("DISABLED"),
.ENUM_ENABLE_BONDING_4 ("DISABLED"),
.ENUM_ENABLE_BONDING_5 ("DISABLED"),
.ENUM_ENABLE_BONDING_WRAPBACK ("DISABLED"),
.ENUM_ENABLE_DQS_TRACKING ("ENABLED"),
.ENUM_ENABLE_ECC_CODE_OVERWRITES ("DISABLED"),
.ENUM_ENABLE_FAST_EXIT_PPD ("DISABLED"),
.ENUM_ENABLE_INTR ("DISABLED"),
.ENUM_ENABLE_NO_DM ("DISABLED"),
.ENUM_ENABLE_PIPELINEGLOBAL ("DISABLED"),
.ENUM_GANGED_ARF ("DISABLED"),
.ENUM_GEN_DBE ("GEN_DBE_DISABLED"),
.ENUM_GEN_SBE ("GEN_SBE_DISABLED"),
.ENUM_INC_SYNC ("FIFO_SET_2"),
.ENUM_LOCAL_IF_CS_WIDTH ("ADDR_WIDTH_0"),
.ENUM_MASK_CORR_DROPPED_INTR ("DISABLED"),
.ENUM_MASK_DBE_INTR ("DISABLED"),
.ENUM_MASK_SBE_INTR ("DISABLED"),
.ENUM_MEM_IF_AL ("AL_0"),
.ENUM_MEM_IF_BANKADDR_WIDTH ("ADDR_WIDTH_3"),
.ENUM_MEM_IF_BURSTLENGTH ("MEM_IF_BURSTLENGTH_8"),
.ENUM_MEM_IF_COLADDR_WIDTH ("ADDR_WIDTH_10"),
.ENUM_MEM_IF_CS_PER_RANK ("MEM_IF_CS_PER_RANK_1"),
.ENUM_MEM_IF_CS_WIDTH ("MEM_IF_CS_WIDTH_1"),
.ENUM_MEM_IF_DQ_PER_CHIP ("MEM_IF_DQ_PER_CHIP_8"),
.ENUM_MEM_IF_DQS_WIDTH ("DQS_WIDTH_4"),
.ENUM_MEM_IF_DWIDTH ("MEM_IF_DWIDTH_32"),
.ENUM_MEM_IF_MEMTYPE ("DDR3_SDRAM"),
.ENUM_MEM_IF_ROWADDR_WIDTH ("ADDR_WIDTH_15"),
.ENUM_MEM_IF_SPEEDBIN ("DDR3_1600_8_8_8"),
.ENUM_MEM_IF_TCCD ("TCCD_4"),
.ENUM_MEM_IF_TCL ("TCL_7"),
.ENUM_MEM_IF_TCWL ("TCWL_6"),
.ENUM_MEM_IF_TFAW ("TFAW_12"),
.ENUM_MEM_IF_TMRD ("TMRD_4"),
.ENUM_MEM_IF_TRAS ("TRAS_14"),
.ENUM_MEM_IF_TRC ("TRC_20"),
.ENUM_MEM_IF_TRCD ("TRCD_6"),
.ENUM_MEM_IF_TRP ("TRP_6"),
.ENUM_MEM_IF_TRRD ("TRRD_4"),
.ENUM_MEM_IF_TRTP ("TRTP_4"),
.ENUM_MEM_IF_TWR ("TWR_6"),
.ENUM_MEM_IF_TWTR ("TWTR_4"),
.ENUM_MMR_CFG_MEM_BL ("MP_BL_8"),
.ENUM_OUTPUT_REGD ("DISABLED"),
.ENUM_PDN_EXIT_CYCLES ("SLOW_EXIT"),
.ENUM_PORT0_WIDTH ("PORT_32_BIT"),
.ENUM_PORT1_WIDTH ("PORT_32_BIT"),
.ENUM_PORT2_WIDTH ("PORT_32_BIT"),
.ENUM_PORT3_WIDTH ("PORT_32_BIT"),
.ENUM_PORT4_WIDTH ("PORT_32_BIT"),
.ENUM_PORT5_WIDTH ("PORT_32_BIT"),
.ENUM_PRIORITY_0_0 ("WEIGHT_0"),
.ENUM_PRIORITY_0_1 ("WEIGHT_0"),
.ENUM_PRIORITY_0_2 ("WEIGHT_0"),
.ENUM_PRIORITY_0_3 ("WEIGHT_0"),
.ENUM_PRIORITY_0_4 ("WEIGHT_0"),
.ENUM_PRIORITY_0_5 ("WEIGHT_0"),
.ENUM_PRIORITY_1_0 ("WEIGHT_0"),
.ENUM_PRIORITY_1_1 ("WEIGHT_0"),
.ENUM_PRIORITY_1_2 ("WEIGHT_0"),
.ENUM_PRIORITY_1_3 ("WEIGHT_0"),
.ENUM_PRIORITY_1_4 ("WEIGHT_0"),
.ENUM_PRIORITY_1_5 ("WEIGHT_0"),
.ENUM_PRIORITY_2_0 ("WEIGHT_0"),
.ENUM_PRIORITY_2_1 ("WEIGHT_0"),
.ENUM_PRIORITY_2_2 ("WEIGHT_0"),
.ENUM_PRIORITY_2_3 ("WEIGHT_0"),
.ENUM_PRIORITY_2_4 ("WEIGHT_0"),
.ENUM_PRIORITY_2_5 ("WEIGHT_0"),
.ENUM_PRIORITY_3_0 ("WEIGHT_0"),
.ENUM_PRIORITY_3_1 ("WEIGHT_0"),
.ENUM_PRIORITY_3_2 ("WEIGHT_0"),
.ENUM_PRIORITY_3_3 ("WEIGHT_0"),
.ENUM_PRIORITY_3_4 ("WEIGHT_0"),
.ENUM_PRIORITY_3_5 ("WEIGHT_0"),
.ENUM_PRIORITY_4_0 ("WEIGHT_0"),
.ENUM_PRIORITY_4_1 ("WEIGHT_0"),
.ENUM_PRIORITY_4_2 ("WEIGHT_0"),
.ENUM_PRIORITY_4_3 ("WEIGHT_0"),
.ENUM_PRIORITY_4_4 ("WEIGHT_0"),
.ENUM_PRIORITY_4_5 ("WEIGHT_0"),
.ENUM_PRIORITY_5_0 ("WEIGHT_0"),
.ENUM_PRIORITY_5_1 ("WEIGHT_0"),
.ENUM_PRIORITY_5_2 ("WEIGHT_0"),
.ENUM_PRIORITY_5_3 ("WEIGHT_0"),
.ENUM_PRIORITY_5_4 ("WEIGHT_0"),
.ENUM_PRIORITY_5_5 ("WEIGHT_0"),
.ENUM_PRIORITY_6_0 ("WEIGHT_0"),
.ENUM_PRIORITY_6_1 ("WEIGHT_0"),
.ENUM_PRIORITY_6_2 ("WEIGHT_0"),
.ENUM_PRIORITY_6_3 ("WEIGHT_0"),
.ENUM_PRIORITY_6_4 ("WEIGHT_0"),
.ENUM_PRIORITY_6_5 ("WEIGHT_0"),
.ENUM_PRIORITY_7_0 ("WEIGHT_0"),
.ENUM_PRIORITY_7_1 ("WEIGHT_0"),
.ENUM_PRIORITY_7_2 ("WEIGHT_0"),
.ENUM_PRIORITY_7_3 ("WEIGHT_0"),
.ENUM_PRIORITY_7_4 ("WEIGHT_0"),
.ENUM_PRIORITY_7_5 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_0 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_1 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_2 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_3 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_4 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_5 ("WEIGHT_0"),
.ENUM_RCFG_USER_PRIORITY_0 ("PRIORITY_1"),
.ENUM_RCFG_USER_PRIORITY_1 ("PRIORITY_1"),
.ENUM_RCFG_USER_PRIORITY_2 ("PRIORITY_1"),
.ENUM_RCFG_USER_PRIORITY_3 ("PRIORITY_1"),
.ENUM_RCFG_USER_PRIORITY_4 ("PRIORITY_1"),
.ENUM_RCFG_USER_PRIORITY_5 ("PRIORITY_1"),
.ENUM_RD_DWIDTH_0 ("DWIDTH_0"),
.ENUM_RD_DWIDTH_1 ("DWIDTH_0"),
.ENUM_RD_DWIDTH_2 ("DWIDTH_0"),
.ENUM_RD_DWIDTH_3 ("DWIDTH_0"),
.ENUM_RD_DWIDTH_4 ("DWIDTH_0"),
.ENUM_RD_DWIDTH_5 ("DWIDTH_0"),
.ENUM_RD_FIFO_IN_USE_0 ("FALSE"),
.ENUM_RD_FIFO_IN_USE_1 ("FALSE"),
.ENUM_RD_FIFO_IN_USE_2 ("FALSE"),
.ENUM_RD_FIFO_IN_USE_3 ("FALSE"),
.ENUM_RD_PORT_INFO_0 ("USE_NO"),
.ENUM_RD_PORT_INFO_1 ("USE_NO"),
.ENUM_RD_PORT_INFO_2 ("USE_NO"),
.ENUM_RD_PORT_INFO_3 ("USE_NO"),
.ENUM_RD_PORT_INFO_4 ("USE_NO"),
.ENUM_RD_PORT_INFO_5 ("USE_NO"),
.ENUM_READ_ODT_CHIP ("ODT_DISABLED"),
.ENUM_REORDER_DATA ("DATA_REORDERING"),
.ENUM_RFIFO0_CPORT_MAP ("CMD_PORT_0"),
.ENUM_RFIFO1_CPORT_MAP ("CMD_PORT_0"),
.ENUM_RFIFO2_CPORT_MAP ("CMD_PORT_0"),
.ENUM_RFIFO3_CPORT_MAP ("CMD_PORT_0"),
.ENUM_SINGLE_READY_0 ("CONCATENATE_RDY"),
.ENUM_SINGLE_READY_1 ("CONCATENATE_RDY"),
.ENUM_SINGLE_READY_2 ("CONCATENATE_RDY"),
.ENUM_SINGLE_READY_3 ("CONCATENATE_RDY"),
.ENUM_STATIC_WEIGHT_0 ("WEIGHT_0"),
.ENUM_STATIC_WEIGHT_1 ("WEIGHT_0"),
.ENUM_STATIC_WEIGHT_2 ("WEIGHT_0"),
.ENUM_STATIC_WEIGHT_3 ("WEIGHT_0"),
.ENUM_STATIC_WEIGHT_4 ("WEIGHT_0"),
.ENUM_STATIC_WEIGHT_5 ("WEIGHT_0"),
.ENUM_SYNC_MODE_0 ("ASYNCHRONOUS"),
.ENUM_SYNC_MODE_1 ("ASYNCHRONOUS"),
.ENUM_SYNC_MODE_2 ("ASYNCHRONOUS"),
.ENUM_SYNC_MODE_3 ("ASYNCHRONOUS"),
.ENUM_SYNC_MODE_4 ("ASYNCHRONOUS"),
.ENUM_SYNC_MODE_5 ("ASYNCHRONOUS"),
.ENUM_TEST_MODE ("NORMAL_MODE"),
.ENUM_THLD_JAR1_0 ("THRESHOLD_32"),
.ENUM_THLD_JAR1_1 ("THRESHOLD_32"),
.ENUM_THLD_JAR1_2 ("THRESHOLD_32"),
.ENUM_THLD_JAR1_3 ("THRESHOLD_32"),
.ENUM_THLD_JAR1_4 ("THRESHOLD_32"),
.ENUM_THLD_JAR1_5 ("THRESHOLD_32"),
.ENUM_THLD_JAR2_0 ("THRESHOLD_16"),
.ENUM_THLD_JAR2_1 ("THRESHOLD_16"),
.ENUM_THLD_JAR2_2 ("THRESHOLD_16"),
.ENUM_THLD_JAR2_3 ("THRESHOLD_16"),
.ENUM_THLD_JAR2_4 ("THRESHOLD_16"),
.ENUM_THLD_JAR2_5 ("THRESHOLD_16"),
.ENUM_USE_ALMOST_EMPTY_0 ("EMPTY"),
.ENUM_USE_ALMOST_EMPTY_1 ("EMPTY"),
.ENUM_USE_ALMOST_EMPTY_2 ("EMPTY"),
.ENUM_USE_ALMOST_EMPTY_3 ("EMPTY"),
.ENUM_USER_ECC_EN ("DISABLE"),
.ENUM_USER_PRIORITY_0 ("PRIORITY_1"),
.ENUM_USER_PRIORITY_1 ("PRIORITY_1"),
.ENUM_USER_PRIORITY_2 ("PRIORITY_1"),
.ENUM_USER_PRIORITY_3 ("PRIORITY_1"),
.ENUM_USER_PRIORITY_4 ("PRIORITY_1"),
.ENUM_USER_PRIORITY_5 ("PRIORITY_1"),
.ENUM_WFIFO0_CPORT_MAP ("CMD_PORT_0"),
.ENUM_WFIFO0_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_WFIFO1_CPORT_MAP ("CMD_PORT_0"),
.ENUM_WFIFO1_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_WFIFO2_CPORT_MAP ("CMD_PORT_0"),
.ENUM_WFIFO2_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_WFIFO3_CPORT_MAP ("CMD_PORT_0"),
.ENUM_WFIFO3_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_WR_DWIDTH_0 ("DWIDTH_0"),
.ENUM_WR_DWIDTH_1 ("DWIDTH_0"),
.ENUM_WR_DWIDTH_2 ("DWIDTH_0"),
.ENUM_WR_DWIDTH_3 ("DWIDTH_0"),
.ENUM_WR_DWIDTH_4 ("DWIDTH_0"),
.ENUM_WR_DWIDTH_5 ("DWIDTH_0"),
.ENUM_WR_FIFO_IN_USE_0 ("FALSE"),
.ENUM_WR_FIFO_IN_USE_1 ("FALSE"),
.ENUM_WR_FIFO_IN_USE_2 ("FALSE"),
.ENUM_WR_FIFO_IN_USE_3 ("FALSE"),
.ENUM_WR_PORT_INFO_0 ("USE_NO"),
.ENUM_WR_PORT_INFO_1 ("USE_NO"),
.ENUM_WR_PORT_INFO_2 ("USE_NO"),
.ENUM_WR_PORT_INFO_3 ("USE_NO"),
.ENUM_WR_PORT_INFO_4 ("USE_NO"),
.ENUM_WR_PORT_INFO_5 ("USE_NO"),
.ENUM_WRITE_ODT_CHIP ("WRITE_CHIP0_ODT0_CHIP1"),
.INTG_MEM_AUTO_PD_CYCLES (0),
.INTG_CYC_TO_RLD_JARS_0 (1),
.INTG_CYC_TO_RLD_JARS_1 (1),
.INTG_CYC_TO_RLD_JARS_2 (1),
.INTG_CYC_TO_RLD_JARS_3 (1),
.INTG_CYC_TO_RLD_JARS_4 (1),
.INTG_CYC_TO_RLD_JARS_5 (1),
.INTG_EXTRA_CTL_CLK_ACT_TO_ACT (0),
.INTG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK (0),
.INTG_EXTRA_CTL_CLK_ACT_TO_PCH (0),
.INTG_EXTRA_CTL_CLK_ACT_TO_RDWR (0),
.INTG_EXTRA_CTL_CLK_ARF_PERIOD (0),
.INTG_EXTRA_CTL_CLK_ARF_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT (0),
.INTG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_PCH_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_PDN_PERIOD (0),
.INTG_EXTRA_CTL_CLK_PDN_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_RD_AP_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_RD_TO_PCH (0),
.INTG_EXTRA_CTL_CLK_RD_TO_RD (0),
.INTG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP (0),
.INTG_EXTRA_CTL_CLK_RD_TO_WR (2),
.INTG_EXTRA_CTL_CLK_RD_TO_WR_BC (2),
.INTG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP (2),
.INTG_EXTRA_CTL_CLK_SRF_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL (0),
.INTG_EXTRA_CTL_CLK_WR_AP_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_WR_TO_PCH (0),
.INTG_EXTRA_CTL_CLK_WR_TO_RD (3),
.INTG_EXTRA_CTL_CLK_WR_TO_RD_BC (3),
.INTG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP (3),
.INTG_EXTRA_CTL_CLK_WR_TO_WR (0),
.INTG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP (0),
.INTG_MEM_IF_TREFI (3120),
.INTG_MEM_IF_TRFC (104),
.INTG_RCFG_SUM_WT_PRIORITY_0 (0),
.INTG_RCFG_SUM_WT_PRIORITY_1 (0),
.INTG_RCFG_SUM_WT_PRIORITY_2 (0),
.INTG_RCFG_SUM_WT_PRIORITY_3 (0),
.INTG_RCFG_SUM_WT_PRIORITY_4 (0),
.INTG_RCFG_SUM_WT_PRIORITY_5 (0),
.INTG_RCFG_SUM_WT_PRIORITY_6 (0),
.INTG_RCFG_SUM_WT_PRIORITY_7 (0),
.INTG_SUM_WT_PRIORITY_0 (0),
.INTG_SUM_WT_PRIORITY_1 (0),
.INTG_SUM_WT_PRIORITY_2 (0),
.INTG_SUM_WT_PRIORITY_3 (0),
.INTG_SUM_WT_PRIORITY_4 (0),
.INTG_SUM_WT_PRIORITY_5 (0),
.INTG_SUM_WT_PRIORITY_6 (0),
.INTG_SUM_WT_PRIORITY_7 (0),
.INTG_POWER_SAVING_EXIT_CYCLES (5),
.INTG_MEM_CLK_ENTRY_CYCLES (10),
.ENUM_ENABLE_BURST_INTERRUPT ("DISABLED"),
.ENUM_ENABLE_BURST_TERMINATE ("DISABLED"),
.AFI_RATE_RATIO (1),
.AFI_ADDR_WIDTH (15),
.AFI_BANKADDR_WIDTH (3),
.AFI_CONTROL_WIDTH (1),
.AFI_CS_WIDTH (1),
.AFI_DM_WIDTH (8),
.AFI_DQ_WIDTH (64),
.AFI_ODT_WIDTH (1),
.AFI_WRITE_DQS_WIDTH (4),
.AFI_RLAT_WIDTH (6),
.AFI_WLAT_WIDTH (6),
.HARD_PHY (1)
) c0 (
.afi_clk (pll_afi_clk_clk), // afi_clk.clk
.afi_reset_n (p0_afi_reset_reset), // afi_reset.reset_n
.ctl_reset_n (p0_ctl_reset_reset), // ctl_reset.reset_n
.afi_half_clk (pll_afi_half_clk_clk), // afi_half_clk.clk
.ctl_clk (p0_ctl_clk_clk), // ctl_clk.clk
.local_init_done (), // status.local_init_done
.local_cal_success (), // .local_cal_success
.local_cal_fail (), // .local_cal_fail
.afi_addr (c0_afi_afi_addr), // afi.afi_addr
.afi_ba (c0_afi_afi_ba), // .afi_ba
.afi_cke (c0_afi_afi_cke), // .afi_cke
.afi_cs_n (c0_afi_afi_cs_n), // .afi_cs_n
.afi_ras_n (c0_afi_afi_ras_n), // .afi_ras_n
.afi_we_n (c0_afi_afi_we_n), // .afi_we_n
.afi_cas_n (c0_afi_afi_cas_n), // .afi_cas_n
.afi_rst_n (c0_afi_afi_rst_n), // .afi_rst_n
.afi_odt (c0_afi_afi_odt), // .afi_odt
.afi_mem_clk_disable (c0_afi_afi_mem_clk_disable), // .afi_mem_clk_disable
.afi_init_req (), // .afi_init_req
.afi_cal_req (), // .afi_cal_req
.afi_seq_busy (), // .afi_seq_busy
.afi_ctl_refresh_done (), // .afi_ctl_refresh_done
.afi_ctl_long_idle (), // .afi_ctl_long_idle
.afi_dqs_burst (c0_afi_afi_dqs_burst), // .afi_dqs_burst
.afi_wdata_valid (c0_afi_afi_wdata_valid), // .afi_wdata_valid
.afi_wdata (c0_afi_afi_wdata), // .afi_wdata
.afi_dm (c0_afi_afi_dm), // .afi_dm
.afi_rdata (p0_afi_afi_rdata), // .afi_rdata
.afi_rdata_en (c0_afi_afi_rdata_en), // .afi_rdata_en
.afi_rdata_en_full (c0_afi_afi_rdata_en_full), // .afi_rdata_en_full
.afi_rdata_valid (p0_afi_afi_rdata_valid), // .afi_rdata_valid
.afi_wlat (p0_afi_afi_wlat), // .afi_wlat
.afi_rlat (p0_afi_afi_rlat), // .afi_rlat
.afi_cal_success (p0_afi_afi_cal_success), // .afi_cal_success
.afi_cal_fail (p0_afi_afi_cal_fail), // .afi_cal_fail
.cfg_addlat (c0_hard_phy_cfg_cfg_addlat), // hard_phy_cfg.cfg_addlat
.cfg_bankaddrwidth (c0_hard_phy_cfg_cfg_bankaddrwidth), // .cfg_bankaddrwidth
.cfg_caswrlat (c0_hard_phy_cfg_cfg_caswrlat), // .cfg_caswrlat
.cfg_coladdrwidth (c0_hard_phy_cfg_cfg_coladdrwidth), // .cfg_coladdrwidth
.cfg_csaddrwidth (c0_hard_phy_cfg_cfg_csaddrwidth), // .cfg_csaddrwidth
.cfg_devicewidth (c0_hard_phy_cfg_cfg_devicewidth), // .cfg_devicewidth
.cfg_dramconfig (c0_hard_phy_cfg_cfg_dramconfig), // .cfg_dramconfig
.cfg_interfacewidth (c0_hard_phy_cfg_cfg_interfacewidth), // .cfg_interfacewidth
.cfg_rowaddrwidth (c0_hard_phy_cfg_cfg_rowaddrwidth), // .cfg_rowaddrwidth
.cfg_tcl (c0_hard_phy_cfg_cfg_tcl), // .cfg_tcl
.cfg_tmrd (c0_hard_phy_cfg_cfg_tmrd), // .cfg_tmrd
.cfg_trefi (c0_hard_phy_cfg_cfg_trefi), // .cfg_trefi
.cfg_trfc (c0_hard_phy_cfg_cfg_trfc), // .cfg_trfc
.cfg_twr (c0_hard_phy_cfg_cfg_twr), // .cfg_twr
.io_intaficalfail (p0_io_int_io_intaficalfail), // io_int.io_intaficalfail
.io_intaficalsuccess (p0_io_int_io_intaficalsuccess), // .io_intaficalsuccess
.mp_cmd_clk_0 (1'b0), // (terminated)
.mp_cmd_reset_n_0 (1'b1), // (terminated)
.mp_cmd_clk_1 (1'b0), // (terminated)
.mp_cmd_reset_n_1 (1'b1), // (terminated)
.mp_cmd_clk_2 (1'b0), // (terminated)
.mp_cmd_reset_n_2 (1'b1), // (terminated)
.mp_cmd_clk_3 (1'b0), // (terminated)
.mp_cmd_reset_n_3 (1'b1), // (terminated)
.mp_cmd_clk_4 (1'b0), // (terminated)
.mp_cmd_reset_n_4 (1'b1), // (terminated)
.mp_cmd_clk_5 (1'b0), // (terminated)
.mp_cmd_reset_n_5 (1'b1), // (terminated)
.mp_rfifo_clk_0 (1'b0), // (terminated)
.mp_rfifo_reset_n_0 (1'b1), // (terminated)
.mp_wfifo_clk_0 (1'b0), // (terminated)
.mp_wfifo_reset_n_0 (1'b1), // (terminated)
.mp_rfifo_clk_1 (1'b0), // (terminated)
.mp_rfifo_reset_n_1 (1'b1), // (terminated)
.mp_wfifo_clk_1 (1'b0), // (terminated)
.mp_wfifo_reset_n_1 (1'b1), // (terminated)
.mp_rfifo_clk_2 (1'b0), // (terminated)
.mp_rfifo_reset_n_2 (1'b1), // (terminated)
.mp_wfifo_clk_2 (1'b0), // (terminated)
.mp_wfifo_reset_n_2 (1'b1), // (terminated)
.mp_rfifo_clk_3 (1'b0), // (terminated)
.mp_rfifo_reset_n_3 (1'b1), // (terminated)
.mp_wfifo_clk_3 (1'b0), // (terminated)
.mp_wfifo_reset_n_3 (1'b1), // (terminated)
.csr_clk (1'b0), // (terminated)
.csr_reset_n (1'b1), // (terminated)
.avl_ready_0 (), // (terminated)
.avl_burstbegin_0 (1'b0), // (terminated)
.avl_addr_0 (1'b0), // (terminated)
.avl_rdata_valid_0 (), // (terminated)
.avl_rdata_0 (), // (terminated)
.avl_wdata_0 (1'b0), // (terminated)
.avl_be_0 (1'b0), // (terminated)
.avl_read_req_0 (1'b0), // (terminated)
.avl_write_req_0 (1'b0), // (terminated)
.avl_size_0 (3'b000), // (terminated)
.avl_ready_1 (), // (terminated)
.avl_burstbegin_1 (1'b0), // (terminated)
.avl_addr_1 (1'b0), // (terminated)
.avl_rdata_valid_1 (), // (terminated)
.avl_rdata_1 (), // (terminated)
.avl_wdata_1 (1'b0), // (terminated)
.avl_be_1 (1'b0), // (terminated)
.avl_read_req_1 (1'b0), // (terminated)
.avl_write_req_1 (1'b0), // (terminated)
.avl_size_1 (3'b000), // (terminated)
.avl_ready_2 (), // (terminated)
.avl_burstbegin_2 (1'b0), // (terminated)
.avl_addr_2 (1'b0), // (terminated)
.avl_rdata_valid_2 (), // (terminated)
.avl_rdata_2 (), // (terminated)
.avl_wdata_2 (1'b0), // (terminated)
.avl_be_2 (1'b0), // (terminated)
.avl_read_req_2 (1'b0), // (terminated)
.avl_write_req_2 (1'b0), // (terminated)
.avl_size_2 (3'b000), // (terminated)
.avl_ready_3 (), // (terminated)
.avl_burstbegin_3 (1'b0), // (terminated)
.avl_addr_3 (1'b0), // (terminated)
.avl_rdata_valid_3 (), // (terminated)
.avl_rdata_3 (), // (terminated)
.avl_wdata_3 (1'b0), // (terminated)
.avl_be_3 (1'b0), // (terminated)
.avl_read_req_3 (1'b0), // (terminated)
.avl_write_req_3 (1'b0), // (terminated)
.avl_size_3 (3'b000), // (terminated)
.avl_ready_4 (), // (terminated)
.avl_burstbegin_4 (1'b0), // (terminated)
.avl_addr_4 (1'b0), // (terminated)
.avl_rdata_valid_4 (), // (terminated)
.avl_rdata_4 (), // (terminated)
.avl_wdata_4 (1'b0), // (terminated)
.avl_be_4 (1'b0), // (terminated)
.avl_read_req_4 (1'b0), // (terminated)
.avl_write_req_4 (1'b0), // (terminated)
.avl_size_4 (3'b000), // (terminated)
.avl_ready_5 (), // (terminated)
.avl_burstbegin_5 (1'b0), // (terminated)
.avl_addr_5 (1'b0), // (terminated)
.avl_rdata_valid_5 (), // (terminated)
.avl_rdata_5 (), // (terminated)
.avl_wdata_5 (1'b0), // (terminated)
.avl_be_5 (1'b0), // (terminated)
.avl_read_req_5 (1'b0), // (terminated)
.avl_write_req_5 (1'b0), // (terminated)
.avl_size_5 (3'b000), // (terminated)
.csr_write_req (1'b0), // (terminated)
.csr_read_req (1'b0), // (terminated)
.csr_waitrequest (), // (terminated)
.csr_addr (10'b0000000000), // (terminated)
.csr_be (1'b0), // (terminated)
.csr_wdata (8'b00000000), // (terminated)
.csr_rdata (), // (terminated)
.csr_rdata_valid (), // (terminated)
.local_multicast (1'b0), // (terminated)
.local_refresh_req (1'b0), // (terminated)
.local_refresh_chip (1'b0), // (terminated)
.local_refresh_ack (), // (terminated)
.local_self_rfsh_req (1'b0), // (terminated)
.local_self_rfsh_chip (1'b0), // (terminated)
.local_self_rfsh_ack (), // (terminated)
.local_deep_powerdn_req (1'b0), // (terminated)
.local_deep_powerdn_chip (1'b0), // (terminated)
.local_deep_powerdn_ack (), // (terminated)
.local_powerdn_ack (), // (terminated)
.local_priority (1'b0), // (terminated)
.bonding_in_1 (4'b0000), // (terminated)
.bonding_in_2 (6'b000000), // (terminated)
.bonding_in_3 (6'b000000), // (terminated)
.bonding_out_1 (), // (terminated)
.bonding_out_2 (), // (terminated)
.bonding_out_3 () // (terminated)
);
altera_mem_if_oct_cyclonev #(
.OCT_TERM_CONTROL_WIDTH (16)
) oct (
.oct_rzqin (oct_rzqin), // oct.rzqin
.seriesterminationcontrol (oct_oct_sharing_seriesterminationcontrol), // oct_sharing.seriesterminationcontrol
.parallelterminationcontrol (oct_oct_sharing_parallelterminationcontrol) // .parallelterminationcontrol
);
altera_mem_if_dll_cyclonev #(
.DLL_DELAY_CTRL_WIDTH (7),
.DLL_OFFSET_CTRL_WIDTH (6),
.DELAY_BUFFER_MODE ("HIGH"),
.DELAY_CHAIN_LENGTH (8),
.DLL_INPUT_FREQUENCY_PS_STR ("2500 ps")
) dll (
.clk (p0_dll_clk_clk), // clk.clk
.dll_pll_locked (p0_dll_sharing_dll_pll_locked), // dll_sharing.dll_pll_locked
.dll_delayctrl (dll_dll_sharing_dll_delayctrl) // .dll_delayctrl
);
endmodule
|
//
///////////////////////////////////////////////////////////////////////////////////////////
// Copyright © 2010-2013, Xilinx, Inc.
// This file contains confidential and proprietary information of Xilinx, Inc. and is
// protected under U.S. and international copyright and other intellectual property laws.
///////////////////////////////////////////////////////////////////////////////////////////
//
// Disclaimer:
// This disclaimer is not a license and does not grant any rights to the materials
// distributed herewith. Except as otherwise provided in a valid license issued to
// you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE
// MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY
// DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
// INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT,
// OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable
// (whether in contract or tort, including negligence, or under any other theory
// of liability) for any loss or damage of any kind or nature related to, arising
// under or in connection with these materials, including for any direct, or any
// indirect, special, incidental, or consequential loss or damage (including loss
// of data, profits, goodwill, or any type of loss or damage suffered as a result
// of any action brought by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-safe, or for use in any
// application requiring fail-safe performance, such as life-support or safety
// devices or systems, Class III medical devices, nuclear facilities, applications
// related to the deployment of airbags, or any other applications that could lead
// to death, personal injury, or severe property or environmental damage
// (individually and collectively, "Critical Applications"). Customer assumes the
// sole risk and liability of any use of Xilinx products in Critical Applications,
// subject only to applicable laws and regulations governing limitations on product
// liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
//
///////////////////////////////////////////////////////////////////////////////////////////
//
ROM_form.v
Production template for a 4K program for KCPSM6 in a 7-Series device using
2 x RAMB36E1 primitives.
Nick Sawyer (Xilinx Ltd)
Ken Chapman (Xilinx Ltd)
5th August 2011 - First Release
14th March 2013 - Unused address inputs on BRAMs connected High to reflect
descriptions UG473.
This is a verilog template file for the KCPSM6 assembler.
This verilog file is not valid as input directly into a synthesis or a simulation tool.
The assembler will read this template and insert the information required to complete
the definition of program ROM and write it out to a new '.v' file that is ready for
synthesis and simulation.
This template can be modified to define alternative memory definitions. However, you are
responsible for ensuring the template is correct as the assembler does not perform any
checking of the verilog.
The assembler identifies all text enclosed by {} characters, and replaces these
character strings. All templates should include these {} character strings for
the assembler to work correctly.
The next line is used to determine where the template actually starts.
{begin template}
//
///////////////////////////////////////////////////////////////////////////////////////////
// Copyright © 2010-2013, Xilinx, Inc.
// This file contains confidential and proprietary information of Xilinx, Inc. and is
// protected under U.S. and international copyright and other intellectual property laws.
///////////////////////////////////////////////////////////////////////////////////////////
//
// Disclaimer:
// This disclaimer is not a license and does not grant any rights to the materials
// distributed herewith. Except as otherwise provided in a valid license issued to
// you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE
// MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY
// DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
// INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT,
// OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable
// (whether in contract or tort, including negligence, or under any other theory
// of liability) for any loss or damage of any kind or nature related to, arising
// under or in connection with these materials, including for any direct, or any
// indirect, special, incidental, or consequential loss or damage (including loss
// of data, profits, goodwill, or any type of loss or damage suffered as a result
// of any action brought by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-safe, or for use in any
// application requiring fail-safe performance, such as life-support or safety
// devices or systems, Class III medical devices, nuclear facilities, applications
// related to the deployment of airbags, or any other applications that could lead
// to death, personal injury, or severe property or environmental damage
// (individually and collectively, "Critical Applications"). Customer assumes the
// sole risk and liability of any use of Xilinx products in Critical Applications,
// subject only to applicable laws and regulations governing limitations on product
// liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
//
///////////////////////////////////////////////////////////////////////////////////////////
//
//
// Production definition of a 4K program for KCPSM6 in a 7-Series device using
// 2 x RAMB36E1 primitives.
//
//
// Program defined by '{psmname}.psm'.
//
// Generated by KCPSM6 Assembler: {timestamp}.
//
// Assembler used ROM_form template: ROM_form_7S_4K_14March13.v
//
//
module {name} (
input [11:0] address,
output [17:0] instruction,
input enable,
input clk);
//
//
wire [15:0] address_a;
wire [35:0] data_in_a;
wire [35:0] data_out_a_l;
wire [35:0] data_out_a_h;
wire [15:0] address_b;
wire [35:0] data_in_b_l;
wire [35:0] data_out_b_l;
wire [35:0] data_in_b_h;
wire [35:0] data_out_b_h;
wire enable_b;
wire clk_b;
wire [7:0] we_b;
//
//
assign address_a = {1'b1, address[11:0], 3'b111};
assign instruction = {data_out_a_h[32], data_out_a_h[7:0], data_out_a_l[32], data_out_a_l[7:0]};
assign data_in_a = 36'b000000000000000000000000000000000000;
//
assign address_b = 16'b1111111111111111;
assign data_in_b_l = {3'h0, data_out_b_l[32], 24'b000000000000000000000000, data_out_b_l[7:0]};
assign data_in_b_h = {3'h0, data_out_b_h[32], 24'b000000000000000000000000, data_out_b_h[7:0]};
assign enable_b = 1'b0;
assign we_b = 8'h00;
assign clk_b = 1'b0;
//
RAMB36E1 # ( .READ_WIDTH_A (9),
.WRITE_WIDTH_A (9),
.DOA_REG (0),
.INIT_A (36'h000000000),
.RSTREG_PRIORITY_A ("REGCE"),
.SRVAL_A (36'h000000000),
.WRITE_MODE_A ("WRITE_FIRST"),
.READ_WIDTH_B (9),
.WRITE_WIDTH_B (9),
.DOB_REG (0),
.INIT_B (36'h000000000),
.RSTREG_PRIORITY_B ("REGCE"),
.SRVAL_B (36'h000000000),
.WRITE_MODE_B ("WRITE_FIRST"),
.INIT_FILE ("NONE"),
.SIM_COLLISION_CHECK ("ALL"),
.RAM_MODE ("TDP"),
.RDADDR_COLLISION_HWCONFIG ("DELAYED_WRITE"),
.EN_ECC_READ ("FALSE"),
.EN_ECC_WRITE ("FALSE"),
.RAM_EXTENSION_A ("NONE"),
.RAM_EXTENSION_B ("NONE"),
.SIM_DEVICE ("7SERIES"),
.INIT_00 (256'h{[8:0]_INIT_00}),
.INIT_01 (256'h{[8:0]_INIT_01}),
.INIT_02 (256'h{[8:0]_INIT_02}),
.INIT_03 (256'h{[8:0]_INIT_03}),
.INIT_04 (256'h{[8:0]_INIT_04}),
.INIT_05 (256'h{[8:0]_INIT_05}),
.INIT_06 (256'h{[8:0]_INIT_06}),
.INIT_07 (256'h{[8:0]_INIT_07}),
.INIT_08 (256'h{[8:0]_INIT_08}),
.INIT_09 (256'h{[8:0]_INIT_09}),
.INIT_0A (256'h{[8:0]_INIT_0A}),
.INIT_0B (256'h{[8:0]_INIT_0B}),
.INIT_0C (256'h{[8:0]_INIT_0C}),
.INIT_0D (256'h{[8:0]_INIT_0D}),
.INIT_0E (256'h{[8:0]_INIT_0E}),
.INIT_0F (256'h{[8:0]_INIT_0F}),
.INIT_10 (256'h{[8:0]_INIT_10}),
.INIT_11 (256'h{[8:0]_INIT_11}),
.INIT_12 (256'h{[8:0]_INIT_12}),
.INIT_13 (256'h{[8:0]_INIT_13}),
.INIT_14 (256'h{[8:0]_INIT_14}),
.INIT_15 (256'h{[8:0]_INIT_15}),
.INIT_16 (256'h{[8:0]_INIT_16}),
.INIT_17 (256'h{[8:0]_INIT_17}),
.INIT_18 (256'h{[8:0]_INIT_18}),
.INIT_19 (256'h{[8:0]_INIT_19}),
.INIT_1A (256'h{[8:0]_INIT_1A}),
.INIT_1B (256'h{[8:0]_INIT_1B}),
.INIT_1C (256'h{[8:0]_INIT_1C}),
.INIT_1D (256'h{[8:0]_INIT_1D}),
.INIT_1E (256'h{[8:0]_INIT_1E}),
.INIT_1F (256'h{[8:0]_INIT_1F}),
.INIT_20 (256'h{[8:0]_INIT_20}),
.INIT_21 (256'h{[8:0]_INIT_21}),
.INIT_22 (256'h{[8:0]_INIT_22}),
.INIT_23 (256'h{[8:0]_INIT_23}),
.INIT_24 (256'h{[8:0]_INIT_24}),
.INIT_25 (256'h{[8:0]_INIT_25}),
.INIT_26 (256'h{[8:0]_INIT_26}),
.INIT_27 (256'h{[8:0]_INIT_27}),
.INIT_28 (256'h{[8:0]_INIT_28}),
.INIT_29 (256'h{[8:0]_INIT_29}),
.INIT_2A (256'h{[8:0]_INIT_2A}),
.INIT_2B (256'h{[8:0]_INIT_2B}),
.INIT_2C (256'h{[8:0]_INIT_2C}),
.INIT_2D (256'h{[8:0]_INIT_2D}),
.INIT_2E (256'h{[8:0]_INIT_2E}),
.INIT_2F (256'h{[8:0]_INIT_2F}),
.INIT_30 (256'h{[8:0]_INIT_30}),
.INIT_31 (256'h{[8:0]_INIT_31}),
.INIT_32 (256'h{[8:0]_INIT_32}),
.INIT_33 (256'h{[8:0]_INIT_33}),
.INIT_34 (256'h{[8:0]_INIT_34}),
.INIT_35 (256'h{[8:0]_INIT_35}),
.INIT_36 (256'h{[8:0]_INIT_36}),
.INIT_37 (256'h{[8:0]_INIT_37}),
.INIT_38 (256'h{[8:0]_INIT_38}),
.INIT_39 (256'h{[8:0]_INIT_39}),
.INIT_3A (256'h{[8:0]_INIT_3A}),
.INIT_3B (256'h{[8:0]_INIT_3B}),
.INIT_3C (256'h{[8:0]_INIT_3C}),
.INIT_3D (256'h{[8:0]_INIT_3D}),
.INIT_3E (256'h{[8:0]_INIT_3E}),
.INIT_3F (256'h{[8:0]_INIT_3F}),
.INIT_40 (256'h{[8:0]_INIT_40}),
.INIT_41 (256'h{[8:0]_INIT_41}),
.INIT_42 (256'h{[8:0]_INIT_42}),
.INIT_43 (256'h{[8:0]_INIT_43}),
.INIT_44 (256'h{[8:0]_INIT_44}),
.INIT_45 (256'h{[8:0]_INIT_45}),
.INIT_46 (256'h{[8:0]_INIT_46}),
.INIT_47 (256'h{[8:0]_INIT_47}),
.INIT_48 (256'h{[8:0]_INIT_48}),
.INIT_49 (256'h{[8:0]_INIT_49}),
.INIT_4A (256'h{[8:0]_INIT_4A}),
.INIT_4B (256'h{[8:0]_INIT_4B}),
.INIT_4C (256'h{[8:0]_INIT_4C}),
.INIT_4D (256'h{[8:0]_INIT_4D}),
.INIT_4E (256'h{[8:0]_INIT_4E}),
.INIT_4F (256'h{[8:0]_INIT_4F}),
.INIT_50 (256'h{[8:0]_INIT_50}),
.INIT_51 (256'h{[8:0]_INIT_51}),
.INIT_52 (256'h{[8:0]_INIT_52}),
.INIT_53 (256'h{[8:0]_INIT_53}),
.INIT_54 (256'h{[8:0]_INIT_54}),
.INIT_55 (256'h{[8:0]_INIT_55}),
.INIT_56 (256'h{[8:0]_INIT_56}),
.INIT_57 (256'h{[8:0]_INIT_57}),
.INIT_58 (256'h{[8:0]_INIT_58}),
.INIT_59 (256'h{[8:0]_INIT_59}),
.INIT_5A (256'h{[8:0]_INIT_5A}),
.INIT_5B (256'h{[8:0]_INIT_5B}),
.INIT_5C (256'h{[8:0]_INIT_5C}),
.INIT_5D (256'h{[8:0]_INIT_5D}),
.INIT_5E (256'h{[8:0]_INIT_5E}),
.INIT_5F (256'h{[8:0]_INIT_5F}),
.INIT_60 (256'h{[8:0]_INIT_60}),
.INIT_61 (256'h{[8:0]_INIT_61}),
.INIT_62 (256'h{[8:0]_INIT_62}),
.INIT_63 (256'h{[8:0]_INIT_63}),
.INIT_64 (256'h{[8:0]_INIT_64}),
.INIT_65 (256'h{[8:0]_INIT_65}),
.INIT_66 (256'h{[8:0]_INIT_66}),
.INIT_67 (256'h{[8:0]_INIT_67}),
.INIT_68 (256'h{[8:0]_INIT_68}),
.INIT_69 (256'h{[8:0]_INIT_69}),
.INIT_6A (256'h{[8:0]_INIT_6A}),
.INIT_6B (256'h{[8:0]_INIT_6B}),
.INIT_6C (256'h{[8:0]_INIT_6C}),
.INIT_6D (256'h{[8:0]_INIT_6D}),
.INIT_6E (256'h{[8:0]_INIT_6E}),
.INIT_6F (256'h{[8:0]_INIT_6F}),
.INIT_70 (256'h{[8:0]_INIT_70}),
.INIT_71 (256'h{[8:0]_INIT_71}),
.INIT_72 (256'h{[8:0]_INIT_72}),
.INIT_73 (256'h{[8:0]_INIT_73}),
.INIT_74 (256'h{[8:0]_INIT_74}),
.INIT_75 (256'h{[8:0]_INIT_75}),
.INIT_76 (256'h{[8:0]_INIT_76}),
.INIT_77 (256'h{[8:0]_INIT_77}),
.INIT_78 (256'h{[8:0]_INIT_78}),
.INIT_79 (256'h{[8:0]_INIT_79}),
.INIT_7A (256'h{[8:0]_INIT_7A}),
.INIT_7B (256'h{[8:0]_INIT_7B}),
.INIT_7C (256'h{[8:0]_INIT_7C}),
.INIT_7D (256'h{[8:0]_INIT_7D}),
.INIT_7E (256'h{[8:0]_INIT_7E}),
.INIT_7F (256'h{[8:0]_INIT_7F}),
.INITP_00 (256'h{[8:0]_INITP_00}),
.INITP_01 (256'h{[8:0]_INITP_01}),
.INITP_02 (256'h{[8:0]_INITP_02}),
.INITP_03 (256'h{[8:0]_INITP_03}),
.INITP_04 (256'h{[8:0]_INITP_04}),
.INITP_05 (256'h{[8:0]_INITP_05}),
.INITP_06 (256'h{[8:0]_INITP_06}),
.INITP_07 (256'h{[8:0]_INITP_07}),
.INITP_08 (256'h{[8:0]_INITP_08}),
.INITP_09 (256'h{[8:0]_INITP_09}),
.INITP_0A (256'h{[8:0]_INITP_0A}),
.INITP_0B (256'h{[8:0]_INITP_0B}),
.INITP_0C (256'h{[8:0]_INITP_0C}),
.INITP_0D (256'h{[8:0]_INITP_0D}),
.INITP_0E (256'h{[8:0]_INITP_0E}),
.INITP_0F (256'h{[8:0]_INITP_0F}))
kcpsm6_rom_l(.ADDRARDADDR (address_a),
.ENARDEN (enable),
.CLKARDCLK (clk),
.DOADO (data_out_a_l[31:0]),
.DOPADOP (data_out_a_l[35:32]),
.DIADI (data_in_a[31:0]),
.DIPADIP (data_in_a[35:32]),
.WEA (4'h0),
.REGCEAREGCE (1'b0),
.RSTRAMARSTRAM (1'b0),
.RSTREGARSTREG (1'b0),
.ADDRBWRADDR (address_b),
.ENBWREN (enable_b),
.CLKBWRCLK (clk_b),
.DOBDO (data_out_b_l[31:0]),
.DOPBDOP (data_out_b_l[35:32]),
.DIBDI (data_in_b_l[31:0]),
.DIPBDIP (data_in_b_l[35:32]),
.WEBWE (we_b),
.REGCEB (1'b0),
.RSTRAMB (1'b0),
.RSTREGB (1'b0),
.CASCADEINA (1'b0),
.CASCADEINB (1'b0),
.CASCADEOUTA (),
.CASCADEOUTB (),
.DBITERR (),
.ECCPARITY (),
.RDADDRECC (),
.SBITERR (),
.INJECTDBITERR (1'b0),
.INJECTSBITERR (1'b0));
//
RAMB36E1 # ( .READ_WIDTH_A (9),
.WRITE_WIDTH_A (9),
.DOA_REG (0),
.INIT_A (36'h000000000),
.RSTREG_PRIORITY_A ("REGCE"),
.SRVAL_A (36'h000000000),
.WRITE_MODE_A ("WRITE_FIRST"),
.READ_WIDTH_B (9),
.WRITE_WIDTH_B (9),
.DOB_REG (0),
.INIT_B (36'h000000000),
.RSTREG_PRIORITY_B ("REGCE"),
.SRVAL_B (36'h000000000),
.WRITE_MODE_B ("WRITE_FIRST"),
.INIT_FILE ("NONE"),
.SIM_COLLISION_CHECK ("ALL"),
.RAM_MODE ("TDP"),
.RDADDR_COLLISION_HWCONFIG ("DELAYED_WRITE"),
.EN_ECC_READ ("FALSE"),
.EN_ECC_WRITE ("FALSE"),
.RAM_EXTENSION_A ("NONE"),
.RAM_EXTENSION_B ("NONE"),
.SIM_DEVICE ("7SERIES"),
.INIT_00 (256'h{[17:9]_INIT_00}),
.INIT_01 (256'h{[17:9]_INIT_01}),
.INIT_02 (256'h{[17:9]_INIT_02}),
.INIT_03 (256'h{[17:9]_INIT_03}),
.INIT_04 (256'h{[17:9]_INIT_04}),
.INIT_05 (256'h{[17:9]_INIT_05}),
.INIT_06 (256'h{[17:9]_INIT_06}),
.INIT_07 (256'h{[17:9]_INIT_07}),
.INIT_08 (256'h{[17:9]_INIT_08}),
.INIT_09 (256'h{[17:9]_INIT_09}),
.INIT_0A (256'h{[17:9]_INIT_0A}),
.INIT_0B (256'h{[17:9]_INIT_0B}),
.INIT_0C (256'h{[17:9]_INIT_0C}),
.INIT_0D (256'h{[17:9]_INIT_0D}),
.INIT_0E (256'h{[17:9]_INIT_0E}),
.INIT_0F (256'h{[17:9]_INIT_0F}),
.INIT_10 (256'h{[17:9]_INIT_10}),
.INIT_11 (256'h{[17:9]_INIT_11}),
.INIT_12 (256'h{[17:9]_INIT_12}),
.INIT_13 (256'h{[17:9]_INIT_13}),
.INIT_14 (256'h{[17:9]_INIT_14}),
.INIT_15 (256'h{[17:9]_INIT_15}),
.INIT_16 (256'h{[17:9]_INIT_16}),
.INIT_17 (256'h{[17:9]_INIT_17}),
.INIT_18 (256'h{[17:9]_INIT_18}),
.INIT_19 (256'h{[17:9]_INIT_19}),
.INIT_1A (256'h{[17:9]_INIT_1A}),
.INIT_1B (256'h{[17:9]_INIT_1B}),
.INIT_1C (256'h{[17:9]_INIT_1C}),
.INIT_1D (256'h{[17:9]_INIT_1D}),
.INIT_1E (256'h{[17:9]_INIT_1E}),
.INIT_1F (256'h{[17:9]_INIT_1F}),
.INIT_20 (256'h{[17:9]_INIT_20}),
.INIT_21 (256'h{[17:9]_INIT_21}),
.INIT_22 (256'h{[17:9]_INIT_22}),
.INIT_23 (256'h{[17:9]_INIT_23}),
.INIT_24 (256'h{[17:9]_INIT_24}),
.INIT_25 (256'h{[17:9]_INIT_25}),
.INIT_26 (256'h{[17:9]_INIT_26}),
.INIT_27 (256'h{[17:9]_INIT_27}),
.INIT_28 (256'h{[17:9]_INIT_28}),
.INIT_29 (256'h{[17:9]_INIT_29}),
.INIT_2A (256'h{[17:9]_INIT_2A}),
.INIT_2B (256'h{[17:9]_INIT_2B}),
.INIT_2C (256'h{[17:9]_INIT_2C}),
.INIT_2D (256'h{[17:9]_INIT_2D}),
.INIT_2E (256'h{[17:9]_INIT_2E}),
.INIT_2F (256'h{[17:9]_INIT_2F}),
.INIT_30 (256'h{[17:9]_INIT_30}),
.INIT_31 (256'h{[17:9]_INIT_31}),
.INIT_32 (256'h{[17:9]_INIT_32}),
.INIT_33 (256'h{[17:9]_INIT_33}),
.INIT_34 (256'h{[17:9]_INIT_34}),
.INIT_35 (256'h{[17:9]_INIT_35}),
.INIT_36 (256'h{[17:9]_INIT_36}),
.INIT_37 (256'h{[17:9]_INIT_37}),
.INIT_38 (256'h{[17:9]_INIT_38}),
.INIT_39 (256'h{[17:9]_INIT_39}),
.INIT_3A (256'h{[17:9]_INIT_3A}),
.INIT_3B (256'h{[17:9]_INIT_3B}),
.INIT_3C (256'h{[17:9]_INIT_3C}),
.INIT_3D (256'h{[17:9]_INIT_3D}),
.INIT_3E (256'h{[17:9]_INIT_3E}),
.INIT_3F (256'h{[17:9]_INIT_3F}),
.INIT_40 (256'h{[17:9]_INIT_40}),
.INIT_41 (256'h{[17:9]_INIT_41}),
.INIT_42 (256'h{[17:9]_INIT_42}),
.INIT_43 (256'h{[17:9]_INIT_43}),
.INIT_44 (256'h{[17:9]_INIT_44}),
.INIT_45 (256'h{[17:9]_INIT_45}),
.INIT_46 (256'h{[17:9]_INIT_46}),
.INIT_47 (256'h{[17:9]_INIT_47}),
.INIT_48 (256'h{[17:9]_INIT_48}),
.INIT_49 (256'h{[17:9]_INIT_49}),
.INIT_4A (256'h{[17:9]_INIT_4A}),
.INIT_4B (256'h{[17:9]_INIT_4B}),
.INIT_4C (256'h{[17:9]_INIT_4C}),
.INIT_4D (256'h{[17:9]_INIT_4D}),
.INIT_4E (256'h{[17:9]_INIT_4E}),
.INIT_4F (256'h{[17:9]_INIT_4F}),
.INIT_50 (256'h{[17:9]_INIT_50}),
.INIT_51 (256'h{[17:9]_INIT_51}),
.INIT_52 (256'h{[17:9]_INIT_52}),
.INIT_53 (256'h{[17:9]_INIT_53}),
.INIT_54 (256'h{[17:9]_INIT_54}),
.INIT_55 (256'h{[17:9]_INIT_55}),
.INIT_56 (256'h{[17:9]_INIT_56}),
.INIT_57 (256'h{[17:9]_INIT_57}),
.INIT_58 (256'h{[17:9]_INIT_58}),
.INIT_59 (256'h{[17:9]_INIT_59}),
.INIT_5A (256'h{[17:9]_INIT_5A}),
.INIT_5B (256'h{[17:9]_INIT_5B}),
.INIT_5C (256'h{[17:9]_INIT_5C}),
.INIT_5D (256'h{[17:9]_INIT_5D}),
.INIT_5E (256'h{[17:9]_INIT_5E}),
.INIT_5F (256'h{[17:9]_INIT_5F}),
.INIT_60 (256'h{[17:9]_INIT_60}),
.INIT_61 (256'h{[17:9]_INIT_61}),
.INIT_62 (256'h{[17:9]_INIT_62}),
.INIT_63 (256'h{[17:9]_INIT_63}),
.INIT_64 (256'h{[17:9]_INIT_64}),
.INIT_65 (256'h{[17:9]_INIT_65}),
.INIT_66 (256'h{[17:9]_INIT_66}),
.INIT_67 (256'h{[17:9]_INIT_67}),
.INIT_68 (256'h{[17:9]_INIT_68}),
.INIT_69 (256'h{[17:9]_INIT_69}),
.INIT_6A (256'h{[17:9]_INIT_6A}),
.INIT_6B (256'h{[17:9]_INIT_6B}),
.INIT_6C (256'h{[17:9]_INIT_6C}),
.INIT_6D (256'h{[17:9]_INIT_6D}),
.INIT_6E (256'h{[17:9]_INIT_6E}),
.INIT_6F (256'h{[17:9]_INIT_6F}),
.INIT_70 (256'h{[17:9]_INIT_70}),
.INIT_71 (256'h{[17:9]_INIT_71}),
.INIT_72 (256'h{[17:9]_INIT_72}),
.INIT_73 (256'h{[17:9]_INIT_73}),
.INIT_74 (256'h{[17:9]_INIT_74}),
.INIT_75 (256'h{[17:9]_INIT_75}),
.INIT_76 (256'h{[17:9]_INIT_76}),
.INIT_77 (256'h{[17:9]_INIT_77}),
.INIT_78 (256'h{[17:9]_INIT_78}),
.INIT_79 (256'h{[17:9]_INIT_79}),
.INIT_7A (256'h{[17:9]_INIT_7A}),
.INIT_7B (256'h{[17:9]_INIT_7B}),
.INIT_7C (256'h{[17:9]_INIT_7C}),
.INIT_7D (256'h{[17:9]_INIT_7D}),
.INIT_7E (256'h{[17:9]_INIT_7E}),
.INIT_7F (256'h{[17:9]_INIT_7F}),
.INITP_00 (256'h{[17:9]_INITP_00}),
.INITP_01 (256'h{[17:9]_INITP_01}),
.INITP_02 (256'h{[17:9]_INITP_02}),
.INITP_03 (256'h{[17:9]_INITP_03}),
.INITP_04 (256'h{[17:9]_INITP_04}),
.INITP_05 (256'h{[17:9]_INITP_05}),
.INITP_06 (256'h{[17:9]_INITP_06}),
.INITP_07 (256'h{[17:9]_INITP_07}),
.INITP_08 (256'h{[17:9]_INITP_08}),
.INITP_09 (256'h{[17:9]_INITP_09}),
.INITP_0A (256'h{[17:9]_INITP_0A}),
.INITP_0B (256'h{[17:9]_INITP_0B}),
.INITP_0C (256'h{[17:9]_INITP_0C}),
.INITP_0D (256'h{[17:9]_INITP_0D}),
.INITP_0E (256'h{[17:9]_INITP_0E}),
.INITP_0F (256'h{[17:9]_INITP_0F}))
kcpsm6_rom_h(.ADDRARDADDR (address_a),
.ENARDEN (enable),
.CLKARDCLK (clk),
.DOADO (data_out_a_h[31:0]),
.DOPADOP (data_out_a_h[35:32]),
.DIADI (data_in_a[31:0]),
.DIPADIP (data_in_a[35:32]),
.WEA (4'h0),
.REGCEAREGCE (1'b0),
.RSTRAMARSTRAM (1'b0),
.RSTREGARSTREG (1'b0),
.ADDRBWRADDR (address_b),
.ENBWREN (enable_b),
.CLKBWRCLK (clk_b),
.DOBDO (data_out_b_h[31:0]),
.DOPBDOP (data_out_b_h[35:32]),
.DIBDI (data_in_b_h[31:0]),
.DIPBDIP (data_in_b_h[35:32]),
.WEBWE (we_b),
.REGCEB (1'b0),
.RSTRAMB (1'b0),
.RSTREGB (1'b0),
.CASCADEINA (1'b0),
.CASCADEINB (1'b0),
.CASCADEOUTA (),
.CASCADEOUTB (),
.DBITERR (),
.ECCPARITY (),
.RDADDRECC (),
.SBITERR (),
.INJECTDBITERR (1'b0),
.INJECTSBITERR (1'b0));
//
endmodule
//
////////////////////////////////////////////////////////////////////////////////////
//
// END OF FILE {name}.v
//
////////////////////////////////////////////////////////////////////////////////////
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLYGATE4SD3_FUNCTIONAL_V
`define SKY130_FD_SC_MS__DLYGATE4SD3_FUNCTIONAL_V
/**
* dlygate4sd3: Delay Buffer 4-stage 0.50um length inner stage gates.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__dlygate4sd3 (
X,
A
);
// Module ports
output X;
input A;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLYGATE4SD3_FUNCTIONAL_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:36:45 11/07/2015
// Design Name:
// Module Name: keyboard_for_ace
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module keyboard_for_ace(
input wire clk,
input wire clkps2,
input wire dataps2,
input wire [7:0] rows,
output wire [4:0] columns,
output reg kbd_reset,
output reg kbd_nmi,
output reg kbd_mreset
);
initial begin
kbd_reset = 1'b1;
kbd_nmi = 1'b1;
kbd_mreset = 1'b1;
end
`include "mapa_teclado_es.vh"
wire new_key_aval;
wire [7:0] scancode;
wire is_released;
wire is_extended;
reg shift_pressed = 1'b0;
reg ctrl_pressed = 1'b0;
reg alt_pressed = 1'b0;
ps2_port ps2_kbd (
.clk(clk), // se recomienda 1 MHz <= clk <= 600 MHz
.enable_rcv(1'b1), // habilitar la maquina de estados de recepcion
.ps2clk_ext(clkps2),
.ps2data_ext(dataps2),
.kb_interrupt(new_key_aval), // a 1 durante 1 clk para indicar nueva tecla recibida
.scancode(scancode), // make o breakcode de la tecla
.released(is_released), // soltada=1, pulsada=0
.extended(is_extended) // extendida=1, no extendida=0
);
reg [4:0] matrix[0:7]; // 40-key matrix keyboard
initial begin
matrix[0] = 5'b11111; // C X Z SS CS
matrix[1] = 5'b11111; // G F D S A
matrix[2] = 5'b11111; // T R E W Q
matrix[3] = 5'b11111; // 5 4 3 2 1
matrix[4] = 5'b11111; // 6 7 8 9 0
matrix[5] = 5'b11111; // Y U I O P
matrix[6] = 5'b11111; // H J K L ENT
matrix[7] = 5'b11111; // V B N M SP
end
assign columns = (matrix[0] | { {8{rows[0]}} }) &
(matrix[1] | { {8{rows[1]}} }) &
(matrix[2] | { {8{rows[2]}} }) &
(matrix[3] | { {8{rows[3]}} }) &
(matrix[4] | { {8{rows[4]}} }) &
(matrix[5] | { {8{rows[5]}} }) &
(matrix[6] | { {8{rows[6]}} }) &
(matrix[7] | { {8{rows[7]}} });
always @(posedge clk) begin
if (new_key_aval == 1'b1) begin
case (scancode)
// Special and control keys
`KEY_LSHIFT,
`KEY_RSHIFT:
shift_pressed <= ~is_released;
`KEY_LCTRL,
`KEY_RCTRL:
begin
ctrl_pressed <= ~is_released;
if (is_extended)
matrix[0][1] <= is_released; // Right control = Symbol shift
else
matrix[0][0] <= is_released; // Left control = Caps shift
end
`KEY_LALT:
alt_pressed <= ~is_released;
`KEY_KPPUNTO:
if (ctrl_pressed && alt_pressed) begin
kbd_reset <= is_released;
if (is_released == 1'b0) begin
matrix[0] <= 5'b11111; // C X Z SS CS
matrix[1] <= 5'b11111; // G F D S A
matrix[2] <= 5'b11111; // T R E W Q
matrix[3] <= 5'b11111; // 5 4 3 2 1
matrix[4] <= 5'b11111; // 6 7 8 9 0
matrix[5] <= 5'b11111; // Y U I O P
matrix[6] <= 5'b11111; // H J K L ENT
matrix[7] <= 5'b11111; // V B N M SP
end
end
`KEY_F5:
if (ctrl_pressed && alt_pressed)
kbd_nmi <= is_released;
`KEY_ENTER:
matrix[6][0] <= is_released;
`KEY_ESC:
begin
matrix[0][0] <= is_released;
matrix[7][0] <= is_released;
end
`KEY_BKSP:
if (ctrl_pressed && alt_pressed) begin
kbd_mreset <= is_released;
end
else begin
matrix[0][0] <= is_released;
matrix[4][0] <= is_released;
end
`KEY_CPSLK:
begin
matrix[0][0] <= is_released;
matrix[3][1] <= is_released; // CAPS LOCK
end
`KEY_F2:
begin
matrix[0][0] <= is_released;
matrix[3][0] <= is_released; // EDIT
end
// Digits and puntuaction marks inside digits
`KEY_1:
begin
if (alt_pressed) begin
matrix[0][1] <= is_released;
matrix[1][1] <= is_released; // |
end
else if (shift_pressed) begin
matrix[0][1] <= is_released;
matrix[3][0] <= is_released; // !
end
else
matrix[3][0] <= is_released;
end
`KEY_2:
begin
if (alt_pressed) begin
matrix[0][1] <= is_released;
matrix[3][1] <= is_released; // @
end
else if (shift_pressed) begin
matrix[0][1] <= is_released;
matrix[5][0] <= is_released; // "
end
else
matrix[3][1] <= is_released;
end
`KEY_3:
begin
if (!shift_pressed)
matrix[3][2] <= is_released;
else begin
matrix[0][1] <= is_released;
matrix[3][2] <= is_released; // #
end
end
`KEY_4:
begin
if (shift_pressed) begin
matrix[0][1] <= is_released;
matrix[3][3] <= is_released; // $
end
else if (ctrl_pressed) begin
matrix[0][0] <= is_released;
matrix[3][3] <= is_released; // INV VIDEO
end
else
matrix[3][3] <= is_released;
end
`KEY_5:
begin
if (!shift_pressed)
matrix[3][4] <= is_released;
else begin
matrix[0][1] <= is_released;
matrix[3][4] <= is_released; // %
end
end
`KEY_6:
begin
if (!shift_pressed)
matrix[4][4] <= is_released;
else begin
matrix[0][1] <= is_released;
matrix[4][4] <= is_released; // &
end
end
`KEY_7:
begin
if (!shift_pressed)
matrix[4][3] <= is_released;
else begin
matrix[0][1] <= is_released;
matrix[7][4] <= is_released; // /
end
end
`KEY_8:
begin
if (!shift_pressed)
matrix[4][2] <= is_released;
else begin
matrix[0][1] <= is_released;
matrix[4][2] <= is_released; // (
end
end
`KEY_9:
begin
if (shift_pressed) begin
matrix[0][1] <= is_released;
matrix[4][1] <= is_released; // )
end
else if (ctrl_pressed) begin
matrix[0][0] <= is_released;
matrix[4][1] <= is_released;
end
else
matrix[4][1] <= is_released;
end
`KEY_0:
begin
if (!shift_pressed)
matrix[4][0] <= is_released;
else begin
matrix[0][1] <= is_released;
matrix[6][1] <= is_released; // =
end
end
// Alphabetic characters
`KEY_Z:
begin
matrix[0][2] <= is_released;
if (shift_pressed)
matrix[0][0] <= is_released;
end
`KEY_X:
begin
matrix[0][3] <= is_released;
if (shift_pressed)
matrix[0][0] <= is_released;
end
`KEY_C:
begin
matrix[0][4] <= is_released;
if (shift_pressed)
matrix[0][0] <= is_released;
end
`KEY_A:
begin
matrix[1][0] <= is_released;
if (shift_pressed)
matrix[0][0] <= is_released;
end
`KEY_S:
begin
matrix[1][1] <= is_released;
if (shift_pressed)
matrix[0][0] <= is_released;
end
`KEY_D:
begin
matrix[1][2] <= is_released;
if (shift_pressed)
matrix[0][0] <= is_released;
end
`KEY_F:
begin
matrix[1][3] <= is_released;
if (shift_pressed)
matrix[0][0] <= is_released;
end
`KEY_G:
begin
matrix[1][4] <= is_released;
if (shift_pressed)
matrix[0][0] <= is_released;
end
`KEY_Q:
begin
matrix[2][0] <= is_released;
if (shift_pressed)
matrix[0][0] <= is_released;
end
`KEY_W:
begin
matrix[2][1] <= is_released;
if (shift_pressed)
matrix[0][0] <= is_released;
end
`KEY_E:
begin
matrix[2][2] <= is_released;
if (shift_pressed)
matrix[0][0] <= is_released;
end
`KEY_R:
begin
matrix[2][3] <= is_released;
if (shift_pressed)
matrix[0][0] <= is_released;
end
`KEY_T:
begin
matrix[2][4] <= is_released;
if (shift_pressed)
matrix[0][0] <= is_released;
end
`KEY_P:
begin
matrix[5][0] <= is_released;
if (shift_pressed)
matrix[0][0] <= is_released;
end
`KEY_O:
begin
matrix[5][1] <= is_released;
if (shift_pressed)
matrix[0][0] <= is_released;
end
`KEY_I:
begin
matrix[5][2] <= is_released;
if (shift_pressed)
matrix[0][0] <= is_released;
end
`KEY_U:
begin
matrix[5][3] <= is_released;
if (shift_pressed)
matrix[0][0] <= is_released;
end
`KEY_Y:
begin
matrix[5][4] <= is_released;
if (shift_pressed)
matrix[0][0] <= is_released;
end
`KEY_L:
begin
matrix[6][1] <= is_released;
if (shift_pressed)
matrix[0][0] <= is_released;
end
`KEY_K:
begin
matrix[6][2] <= is_released;
if (shift_pressed)
matrix[0][0] <= is_released;
end
`KEY_J:
begin
matrix[6][3] <= is_released;
if (shift_pressed)
matrix[0][0] <= is_released;
end
`KEY_H:
begin
matrix[6][4] <= is_released;
if (shift_pressed)
matrix[0][0] <= is_released;
end
`KEY_M:
begin
matrix[7][1] <= is_released;
if (shift_pressed)
matrix[0][0] <= is_released;
end
`KEY_N:
begin
matrix[7][2] <= is_released;
if (shift_pressed)
matrix[0][0] <= is_released;
end
`KEY_B:
begin
matrix[7][3] <= is_released;
if (shift_pressed)
matrix[0][0] <= is_released;
end
`KEY_V:
begin
matrix[7][4] <= is_released;
if (shift_pressed)
matrix[0][0] <= is_released;
end
// Symbols
`KEY_APOS:
begin
matrix[0][1] <= is_released;
if (!shift_pressed)
matrix[4][3] <= is_released;
else
matrix[0][4] <= is_released; // ?
end
`KEY_CORCHA:
begin
matrix[0][1] <= is_released;
if (alt_pressed || shift_pressed)
matrix[5][4] <= is_released; // [
else
matrix[6][4] <= is_released; // ^
end
`KEY_CORCHC:
begin
matrix[0][1] <= is_released;
if (shift_pressed)
matrix[7][3] <= is_released; // *
else if (alt_pressed)
matrix[5][3] <= is_released; // ]
else
matrix[6][2] <= is_released; // +
end
`KEY_LLAVA:
begin
matrix[0][1] <= is_released;
if (alt_pressed || shift_pressed)
matrix[1][3] <= is_released; // {
else
matrix[0][3] <= is_released; // pound
end
`KEY_LLAVC:
begin
matrix[0][1] <= is_released;
if (alt_pressed || shift_pressed)
matrix[1][4] <= is_released; // }
else
matrix[5][2] <= is_released; // copyright
end
`KEY_COMA:
begin
matrix[0][1] <= is_released;
if (!shift_pressed)
matrix[7][2] <= is_released;
else
matrix[5][1] <= is_released; // ;
end
`KEY_PUNTO:
begin
matrix[0][1] <= is_released;
if (!shift_pressed)
matrix[7][1] <= is_released;
else
matrix[0][2] <= is_released; // :
end
`KEY_MENOS:
begin
matrix[0][1] <= is_released;
if (!shift_pressed)
matrix[6][3] <= is_released; //
else
matrix[4][0] <= is_released; // _
end
`KEY_LT:
begin
matrix[0][1] <= is_released;
if (!shift_pressed)
matrix[2][3] <= is_released; // <
else
matrix[2][4] <= is_released; // >
end
`KEY_BL:
begin
matrix[0][1] <= is_released;
matrix[1][2] <= is_released; // \
end
`KEY_SPACE:
matrix[7][0] <= is_released;
// Cursor keys
`KEY_UP:
begin
matrix[0][0] <= is_released;
matrix[4][4] <= is_released;
end
`KEY_DOWN:
begin
matrix[0][0] <= is_released;
matrix[4][3] <= is_released;
end
`KEY_LEFT:
begin
matrix[0][0] <= is_released;
matrix[3][4] <= is_released;
end
`KEY_RIGHT:
begin
matrix[0][0] <= is_released;
matrix[4][2] <= is_released;
end
endcase
end
end
endmodule
|
/******************************************************************************
* License Agreement *
* *
* Copyright (c) 1991-2013 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Any megafunction design, and related net list (encrypted or decrypted), *
* support information, device programming or simulation file, and any other *
* associated documentation or information provided by Altera or a partner *
* under Altera's Megafunction Partnership Program may be used only to *
* program PLD devices (but not masked PLD devices) from Altera. Any other *
* use of such megafunction design, net list, support information, device *
* programming or simulation file, or any other related documentation or *
* information is prohibited for any other purpose, including, but not *
* limited to modification, reverse engineering, de-compiling, or use with *
* any other silicon devices, unless such use is explicitly licensed under *
* a separate agreement with Altera or a megafunction partner. Title to *
* the intellectual property, including patents, copyrights, trademarks, *
* trade secrets, or maskworks, embodied in any such megafunction design, *
* net list, support information, device programming or simulation file, or *
* any other related documentation or information provided by Altera or a *
* megafunction partner, remains with Altera, the megafunction partner, or *
* their respective licensors. No other licenses, including any licenses *
* needed under any third party's intellectual property, are provided herein.*
* Copying or modifying any file, or portion thereof, to which this notice *
* is attached violates this copyright. *
* *
* THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
* IN THIS FILE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/******************************************************************************
* *
* This module is a buffer that holds characters to be displayed on a *
* VGA or LCD screen. *
* *
******************************************************************************/
module soc_system_vga_char_buffer (
// Inputs
clk,
reset,
ctrl_address,
ctrl_byteenable,
ctrl_chipselect,
ctrl_read,
ctrl_write,
ctrl_writedata,
buf_address,
buf_byteenable,
buf_chipselect,
buf_read,
buf_write,
buf_writedata,
stream_ready,
// Bidirectionals
// Outputs
ctrl_readdata,
buf_readdata,
buf_waitrequest,
stream_data,
stream_startofpacket,
stream_endofpacket,
stream_empty,
stream_valid
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter DW = 8;
parameter ENLARGE_CHAR = 0;
parameter AW = 13;
parameter BUFFER_SIZE = 8192;
parameter PIXELS = 640;
parameter LINES = 480;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input ctrl_address;
input [ 3: 0] ctrl_byteenable;
input ctrl_chipselect;
input ctrl_read;
input ctrl_write;
input [31: 0] ctrl_writedata;
input [(AW-1): 0] buf_address;
input buf_byteenable;
input buf_chipselect;
input buf_read;
input buf_write;
input [ 7: 0] buf_writedata;
input stream_ready;
// Bidirectionals
// Outputs
output reg [31: 0] ctrl_readdata;
output reg [ 7: 0] buf_readdata;
output buf_waitrequest;
output [39: 0] stream_data;
output stream_startofpacket;
output stream_endofpacket;
output [ 1: 0] stream_empty;
output stream_valid;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
//localparam NUMBER_OF_BITS_FOR_X_COORD = 10;
//localparam NUMBER_OF_BITS_FOR_Y_COORD = 9;
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire [DW: 1] char_data_to_buffer;
wire [DW: 1] char_data_from_buffer;
wire [AW: 1] cur_char_position;
wire [15: 0] cur_char_for_display;
wire cur_char_data;
wire [ 9: 0] char_red;
wire [ 9: 0] char_green;
wire [ 9: 0] char_blue;
// Internal Registers
reg [31: 0] control_reg;
reg [ 1: 0] delayed_buf_waitrequest;
reg clear_screen;
reg [ 9: 0] x_position;
reg [ 8: 0] y_position;
reg [ 5: 0] delayed_x_position;
reg [ 5: 0] delayed_y_position;
reg [ 3: 0] delayed_startofpacket;
reg [ 3: 0] delayed_endofpacket;
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
always @(posedge clk)
begin
if (reset)
ctrl_readdata <= 32'h00000000;
else if (ctrl_chipselect & ctrl_read & ctrl_address)
ctrl_readdata <= {16'd60, 16'd80};
else if (ctrl_chipselect & ctrl_read)
ctrl_readdata <= control_reg;
end
always @(posedge clk)
begin
if (reset)
buf_readdata <= 8'h00;
else if (buf_chipselect & buf_read)
buf_readdata <= {1'b0, char_data_from_buffer[7:1]};
end
// Internal Registers
always @(posedge clk)
begin
if (reset)
control_reg <= 32'h00010000;
else if (ctrl_chipselect & ctrl_write & ~ctrl_address)
begin
if (ctrl_byteenable[0])
control_reg[ 7: 0] <= ctrl_writedata[ 7: 0];
if (ctrl_byteenable[1])
control_reg[15: 8] <= ctrl_writedata[15: 8];
if (ctrl_byteenable[2])
control_reg[23:16] <= ctrl_writedata[23:16];
if (ctrl_byteenable[3])
control_reg[31:24] <= ctrl_writedata[31:24];
end
else if (clear_screen & stream_ready &
(x_position == (PIXELS - 1)) && (y_position == (LINES - 1)))
control_reg[16] <= 1'b0;
end
always @(posedge clk)
begin
if (reset)
delayed_buf_waitrequest <= 2'h0;
else if (buf_chipselect & buf_read)
delayed_buf_waitrequest <= {delayed_buf_waitrequest[0], 1'b1};
else
delayed_buf_waitrequest <= 2'h0;
end
always @(posedge clk)
begin
if (reset)
clear_screen <= 1'b1;
else if (~(control_reg[16]))
clear_screen <= 1'b0;
else if ((x_position == 10'h000) && (y_position == 9'h000))
clear_screen <= 1'b1;
end
always @(posedge clk)
begin
if (reset)
x_position <= 10'h000;
else if (stream_ready)
begin
if (x_position == (PIXELS - 1))
x_position <= 10'h000;
else
x_position <= x_position + 10'h001;
end
end
always @(posedge clk)
begin
if (reset)
y_position <= 9'h000;
else if (stream_ready && (x_position == (PIXELS - 1)))
begin
if (y_position == (LINES - 1))
y_position <= 9'h000;
else
y_position <= y_position + 9'h001;
end
end
always @(posedge clk)
begin
if (reset)
begin
delayed_x_position <= 6'h00;
delayed_y_position <= 6'h00;
end
else if (stream_ready)
begin
delayed_x_position <= {delayed_x_position[2:0],
x_position[(ENLARGE_CHAR+2):ENLARGE_CHAR]};
delayed_y_position <= {delayed_y_position[2:0],
y_position[(ENLARGE_CHAR+2):ENLARGE_CHAR]};
end
end
always @(posedge clk)
begin
if (reset)
delayed_startofpacket <= 4'h0;
else if (stream_ready)
begin
delayed_startofpacket[3:1] <= delayed_startofpacket[2:0];
if ((x_position == 10'h000) && (y_position == 9'h000))
delayed_startofpacket[0] <= 1'b1;
else
delayed_startofpacket[0] <= 1'b0;
end
end
always @(posedge clk)
begin
if (reset)
delayed_endofpacket <= 4'h0;
else if (stream_ready)
begin
delayed_endofpacket[3:1] <= delayed_endofpacket[2:0];
if ((x_position == (PIXELS - 1)) && (y_position == (LINES - 1)))
delayed_endofpacket[0] <= 1'b1;
else
delayed_endofpacket[0] <= 1'b0;
end
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign buf_waitrequest =
(buf_chipselect & buf_read) & ~delayed_buf_waitrequest[1];
assign stream_data[39:30] = {10{cur_char_data}};
assign stream_data[29: 0] = {char_red, char_green, char_blue};
assign stream_startofpacket = delayed_startofpacket[3];
assign stream_endofpacket = delayed_endofpacket[3];
assign stream_empty = 2'h0;
assign stream_valid = 1'b1;
// Internal Assignments
assign char_data_to_buffer = {control_reg[(DW-8):0], buf_writedata[6:0]};
assign cur_char_position =
{y_position[8:(3 + ENLARGE_CHAR)], x_position[9:(3 + ENLARGE_CHAR)]};
assign char_red = {10{cur_char_data}};
assign char_green = {10{cur_char_data}};
assign char_blue = {10{cur_char_data}};
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altsyncram Char_Buffer_Memory (
// Inputs
.clock0 (clk),
.address_a (buf_address),
.wren_a (buf_byteenable & buf_chipselect & buf_write),
.data_a (char_data_to_buffer),
.clock1 (clk),
.clocken1 (stream_ready),
.address_b (cur_char_position),
.wren_b (clear_screen),
.data_b ({{(DW - 7){1'b0}}, 7'h20}),
// Bidirectionals
// Outputs
.q_a (char_data_from_buffer),
.q_b (cur_char_for_display),
// Unused
.rden_b (1'b1),
.aclr0 (1'b0),
.aclr1 (1'b0),
.clocken0 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.byteena_a (1'b1),
.byteena_b (1'b1),
.rden_a (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0)
);
defparam
Char_Buffer_Memory.init_file = "UNUSED",
Char_Buffer_Memory.intended_device_family = "Cyclone II",
Char_Buffer_Memory.lpm_type = "altsyncram",
Char_Buffer_Memory.operation_mode = "BIDIR_DUAL_PORT",
Char_Buffer_Memory.read_during_write_mode_mixed_ports = "DONT_CARE",
Char_Buffer_Memory.power_up_uninitialized = "FALSE",
Char_Buffer_Memory.address_reg_b = "CLOCK1",
Char_Buffer_Memory.indata_reg_b = "CLOCK1",
Char_Buffer_Memory.wrcontrol_wraddress_reg_b = "CLOCK1",
Char_Buffer_Memory.clock_enable_input_a = "BYPASS",
Char_Buffer_Memory.clock_enable_input_b = "NORMAL",
Char_Buffer_Memory.clock_enable_output_a = "BYPASS",
Char_Buffer_Memory.clock_enable_output_b = "NORMAL",
Char_Buffer_Memory.numwords_a = BUFFER_SIZE,
Char_Buffer_Memory.numwords_b = BUFFER_SIZE,
Char_Buffer_Memory.outdata_aclr_a = "NONE",
Char_Buffer_Memory.outdata_aclr_b = "NONE",
Char_Buffer_Memory.outdata_reg_a = "CLOCK0",
Char_Buffer_Memory.outdata_reg_b = "CLOCK1",
Char_Buffer_Memory.widthad_a = AW,
Char_Buffer_Memory.widthad_b = AW,
Char_Buffer_Memory.width_a = DW,
Char_Buffer_Memory.width_b = DW,
Char_Buffer_Memory.width_byteena_a = 1,
Char_Buffer_Memory.width_byteena_b = 1;
altera_up_video_128_character_rom Character_Rom (
// Inputs
.clk (clk),
.clk_en (stream_ready),
.character (cur_char_for_display[ 6: 0]),
.x_coordinate (delayed_x_position[ 5: 3]),
.y_coordinate (delayed_y_position[ 5: 3]),
// Bidirectionals
// Outputs
.character_data (cur_char_data)
);
endmodule
|
//
///////////////////////////////////////////////////////////////////////////////////////////
// Copyright © 2010-2011, Xilinx, Inc.
// This file contains confidential and proprietary information of Xilinx, Inc. and is
// protected under U.S. and international copyright and other intellectual property laws.
///////////////////////////////////////////////////////////////////////////////////////////
//
// Disclaimer:
// This disclaimer is not a license and does not grant any rights to the materials
// distributed herewith. Except as otherwise provided in a valid license issued to
// you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE
// MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY
// DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
// INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT,
// OR FITNESS FOR ANY PARTICULAR PURPOSE; and [2] Xilinx shall not be liable
// (whether in contract or tort, including negligence, or under any other theory
// of liability) for any loss or damage of any kind or nature related to, arising
// under or in connection with these materials, including for any direct, or any
// indirect, special, incidental, or consequential loss or damage (including loss
// of data, profits, goodwill, or any type of loss or damage suffered as a result
// of any action brought by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-safe, or for use in any
// application requiring fail-safe performance, such as life-support or safety
// devices or systems, Class III medical devices, nuclear facilities, applications
// related to the deployment of airbags, or any other applications that could lead
// to death, personal injury, or severe property or environmental damage
// (individually and collectively, "Critical Applications"). Customer assumes the
// sole risk and liability of any use of Xilinx products in Critical Applications,
// subject only to applicable laws and regulations governing limitations on product
// liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
//
///////////////////////////////////////////////////////////////////////////////////////////
//
//
///////////////////////////////////////////////////////////////////////////////////////////
//
// *** PLEASE NOTE THIS IS NOT A COMPLETE DESIGN ***
//
// This file contains sections of Verilog code intended to be helpful reference when using
// a KCPSM6 (PicoBlaze) processor in a Spartan-6 or Virtex-6 design. Please refer to the
// documentation provided with PicoBlaze.
//
// Nick Sawyer and Ken Chapman - Xilinx - 4th March 2011
//
///////////////////////////////////////////////////////////////////////////////////////////
// Signals
///////////////////////////////////////////////////////////////////////////////////////////
//
//
// Signals for connection of KCPSM6 and Program Memory.
//
// NOTE: In Verilog a 'reg' must be used when a signal is used in a process and a 'wire'
// must be used when using a simple assignment. This means that you may need to
// change the definition for the 'interrupt', 'kcpsm6_sleep' and 'kcpsm6_reset'
// depending on how you use them in your design. For example, if you don't use
// interrupt then you will probably tie it to '0' and this will require a 'wire'.
//
//
wire [11:0] address;
wire [17:0] instruction;
wire bram_enable;
wire [7:0] port_id;
wire [7:0] out_port;
reg [7:0] in_port;
wire write_strobe;
wire k_write_strobe;
wire read_strobe;
reg interrupt; //See note above
wire interrupt_ack;
wire kcpsm6_sleep; //See note above
reg kcpsm6_reset; //See note above
//
// Some additional signals are required if your system also needs to reset KCPSM6.
//
wire cpu_reset;
wire rdl;
//
// When interrupt is to be used then the recommended circuit included below requires
// the following signal to represent the request made from your system.
//
wire int_request;
//
///////////////////////////////////////////////////////////////////////////////////////////
// Circuit Descriptions
///////////////////////////////////////////////////////////////////////////////////////////
//
//
/////////////////////////////////////////////////////////////////////////////////////////
// Instantiate KCPSM6 and connect to Program Memory
/////////////////////////////////////////////////////////////////////////////////////////
//
// The KCPSM6 parameters can be defined as required but the default values are shown below
// and these would be adequate for most designs.
//
kcpsm6 #(
.interrupt_vector (12'h3FF),
.scratch_pad_memory_size(64),
.hwbuild (8'h00))
processor (
.address (address),
.instruction (instruction),
.bram_enable (bram_enable),
.port_id (port_id),
.write_strobe (write_strobe),
.k_write_strobe (k_write_strobe),
.out_port (out_port),
.read_strobe (read_strobe),
.in_port (in_port),
.interrupt (interrupt),
.interrupt_ack (interrupt_ack),
.reset (kcpsm6_reset),
.sleep (kcpsm6_sleep),
.clk (clk));
//
// In many designs (especially your first) interrupt and sleep are not used.
// Tie these inputs Low until you need them.
//
assign kcpsm6_sleep = 1'b0;
assign interrupt = 1'b0;
//
// The default Program Memory recommended for development.
//
// The generics should be set to define the family, program size and enable the JTAG
// Loader. As described in the documentation the initial recommended values are.
// 'S6', '1' and '1' for a Spartan-6 design.
// 'V6', '2' and '1' for a Virtex-6 design.
// Note that all 12-bits of the address are connected regardless of the program size
// specified by the generic. Within the program memory only the appropriate address bits
// will be used (e.g. 10 bits for 1K memory). This means it that you only need to modify
// the generic when changing the size of your program.
//
// When JTAG Loader updates the contents of the program memory KCPSM6 should be reset
// so that the new program executes from address zero. The Reset During Load port 'rdl'
// is therefore connected to the reset input of KCPSM6.
//
<your_program> #(
.C_FAMILY ("V6"), //Family 'S6' or 'V6'
.C_RAM_SIZE_KWORDS (2), //Program size '1', '2' or '4'
.C_JTAG_LOADER_ENABLE (1)) //Include JTAG Loader when set to '1'
program_rom ( //Name to match your PSM file
.rdl (kcpsm6_reset),
.enable (bram_enable),
.address (address),
.instruction (instruction),
.clk (clk));
//
// If your design also needs to be able to reset KCPSM6 the arrangement below should be
// used to 'OR' your signal with 'rdl' from the program memory.
//
<your_program> #(
.C_FAMILY ("V6"), //Family 'S6' or 'V6'
.C_RAM_SIZE_KWORDS (2), //Program size '1', '2' or '4'
.C_JTAG_LOADER_ENABLE (1)) //Include JTAG Loader when set to 1'b1
program_rom ( //Name to match your PSM file
.rdl (rdl),
.enable (bram_enable),
.address (address),
.instruction (instruction),
.clk (clk));
assign kcpsm6_reset = cpu_reset | rdl;
//
/////////////////////////////////////////////////////////////////////////////////////////
// Example of General Purose I/O Ports.
/////////////////////////////////////////////////////////////////////////////////////////
//
// The following code corresponds with the circuit diagram shown on page 72 of the
// KCPSM6 Guide and includes additional advice and recommendations.
//
//
//
/////////////////////////////////////////////////////////////////////////////////////////
// General Purpose Input Ports.
/////////////////////////////////////////////////////////////////////////////////////////
//
//
// The inputs connect via a pipelined multiplexer. For optimum implementation, the input
// selection control of the multiplexer is limited to only those signals of 'port_id'
// that are necessary. In this case, only 2-bits are required to identify each of
// four input ports to be read by KCPSM6.
//
// Note that 'read_strobe' only needs to be used when whatever supplying information to
// KPPSM6 needs to know when that information has been read. For example, when reading
// a FIFO a read signal would need to be generated when that port is read such that the
// FIFO would know to present the next oldest information.
//
always @ (posedge clk)
begin
case (port_id[1:0])
// Read input_port_a at port address 00 hex
2'b00 : in_port <= input_port_a;
// Read input_port_b at port address 01 hex
2'b01 : in_port <= input_port_b;
// Read input_port_c at port address 02 hex
2'b10 : in_port <= input_port_c;
// Read input_port_d at port address 03 hex
2'b11 : in_port <= input_port_d;
// To ensure minimum logic implementation when defining a multiplexer always
// use don't care for any of the unused cases (although there are none in this
// example).
default : in_port <= 8'bXXXXXXXX ;
endcase
end
//
/////////////////////////////////////////////////////////////////////////////////////////
// General Purpose Output Ports
/////////////////////////////////////////////////////////////////////////////////////////
//
//
// Output ports must capture the value presented on the 'out_port' based on the value of
// 'port_id' when 'write_strobe' is High.
//
// For an optimum implementation the allocation of output ports should be made in a way
// that means that the decoding of 'port_id' is minimised. Whilst there is nothing
// logically wrong with decoding all 8-bits of 'port_id' it does result in a function
// that can not fit into a single 6-input look up table (LUT6) and requires all signals
// to be routed which impacts size, performance and power consumption of your design.
// So unless you really have a lot of output ports it is best practice to use 'one-hot'
// allocation of addresses as used below or to limit the number of 'port_id' bits to
// be decoded to the number required to cover the ports.
//
// Code examples in which the port address is 04 hex.
//
// Best practice in which one-hot allocation only requires a single bit to be tested.
// Supports up to 8 output ports with each allocated a different bit of 'port_id'.
//
// if (port_id[2] == 1'b1) output_port_x <= out_port;
//
//
// Limited decode in which 5-bits of 'port_id' are used to identify up to 32 ports and
// the decode logic can still fit within a LUT6 (the 'write_strobe' requiring the 6th
// input to complete the decode).
//
// if (port_id[4:0] == 5'b00100) output_port_x <= out_port;
//
//
// The 'generic' code may be the easiest to write with the minimum of thought but will
// result in two LUT6 being used to implement each decoder. This will also impact
// performance and power. This is not generally a problem and hence it is reasonable to
// consider this as over attention to detail but good design practice will often bring
// rewards in the long term. When a large design struggles to fit into a given device
// and/or meet timing closure then it is often the result of many small details rather
// that one big cause. PicoBlaze is extremely efficient so it would be a shame to
// spoil that efficiency with unnecessarily large and slow peripheral logic.
//
// if port_id = X"04" then output_port_x <= out_port;
//
always @ (posedge clk)
begin
// 'write_strobe' is used to qualify all writes to general output ports.
if (write_strobe == 1'b1) begin
// Write to output_port_w at port address 01 hex
if (port_id[0] == 1'b1) begin
output_port_w <= out_port;
end
// Write to output_port_x at port address 02 hex
if (port_id[1] == 1'b1) begin
output_port_x <= out_port;
end
// Write to output_port_y at port address 04 hex
if (port_id[2] == 1'b1) begin
output_port_y <= out_port;
end
// Write to output_port_z at port address 08 hex
if (port_id[3] == 1'b1) begin
output_port_z <= out_port;
end
end
end
//
/////////////////////////////////////////////////////////////////////////////////////////
// Constant-Optimised Output Ports
/////////////////////////////////////////////////////////////////////////////////////////
//
//
// Implementation of the Constant-Optimised Output Ports should follow the same basic
// concepts as General Output Ports but remember that only the lower 4-bits of 'port_id'
// are used and that 'k_write_strobe' is used as the qualifier.
//
always @ (posedge clk)
begin
// 'k_write_strobe' is used to qualify all writes to constant output ports.
if (k_write_strobe == 1'b1) begin
// Write to output_port_k at port address 01 hex
if (port_id[0] == 1'b1) begin
output_port_k <= out_port;
end
// Write to output_port_c at port address 02 hex
if (port_id[1] == 1'b1) begin
output_port_c <= out_port;
end
end
end
//
/////////////////////////////////////////////////////////////////////////////////////////
// Recommended 'closed loop' interrupt interface (when required).
/////////////////////////////////////////////////////////////////////////////////////////
//
// Interrupt becomes active when 'int_request' is observed and then remains active until
// acknowledged by KCPSM6. Please see description and waveforms in documentation.
//
always @ (posedge clk)
begin
if (interrupt_ack == 1'b1) begin
interrupt <= 1'b0;
end
else if (int_request == 1'b1) begin
interrupt <= 1'b1;
end
else begin
interrupt <= interrupt;
end
end
//
/////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////////////////
//
// END OF FILE kcpsm6_design_template.v
//
///////////////////////////////////////////////////////////////////////////////////////////
|
/*
* Copyright 2013-2016 Colin Weltin-Wu ([email protected])
* UC San Diego Integrated Signal Processing Group
*
* Licensed under GNU General Public License 3.0 or later.
* Some rights reserved. See LICENSE.
*
* spi_map.v
* This file is auto-generated by the make_spi.py script from the spi
* register map.
*/
module spi_map(
// Inputs
i_rstb, i_spi_active, vi_data_rx, i_rx_valid, vi_byte_num,
// Read-only inputs
// INSERT_RO
// Write-only outputs
// INSERT_WO
// Registered outputs
// INSERT_RW
// Outputs
vio_data_spi);
// Global reset
input i_rstb;
// Data from SPI interface
input i_spi_active;
input [7:0] vi_data_rx;
input i_rx_valid;
input [2:0] vi_byte_num;
// Data to SPI interface
inout [7:0] vio_data_spi;
// Static registered outputs (rw)
// INSERT_RW_DECLARATION
// Shadow register read-only inputs (ro)
// INSERT_RO_DECLARATION
// Pulsed write-only outputs (wo)
// INSERT_WO_DECLARATION
// Latched data to be sent back
reg [7:0] r_data_to_send;
/*
* Create a local reset signal that is used for state machine registers
*/
wire active = i_rstb && i_spi_active;
/*
* Latch in the opcode, which is byte 0 of the data
* If reading from the map, drive the data bus to the SPI during byte 2
* Latch in the address, which is byte 1 of the data
*/
reg [7:0] rv_opcode;
reg r_read_map;
reg r_write_map;
reg [7:0] rv_addr;
always @( posedge i_rx_valid or negedge active ) begin : opcode_fsm
if ( !active ) begin
rv_opcode <= 0;
r_read_map <= 0;
r_write_map <= 0;
rv_addr <= 0;
end else begin
// Load opcode
if ( 0 == vi_byte_num )
rv_opcode <= vi_data_rx;
// Load address
if ( 1 == vi_byte_num )
rv_addr <= vi_data_rx;
// Determine what to do after address is received
if ( 1 == vi_byte_num ) begin
if ( 32 == rv_opcode )
r_write_map <= 1;
else
r_write_map <= 0;
if ( 48 == rv_opcode )
r_read_map <= 1;
else
r_read_map <= 0;
end
end // else: !if( !active )
end // block: opcode_fsm
/*
* All the registered fields are written in this section.
*/
always @( posedge i_rx_valid or negedge i_rstb ) begin
if ( !i_rstb ) begin
// INSERT_RESET_REGS
end else begin
// INSERT_WRITE_REGS
end
end
/*
* All the write-only outputs which are passed through are in this section.
*/
// INSERT_PULSE_DECLARATION
always @( posedge i_rx_valid or negedge active ) begin
if ( !active ) begin
// INSERT_PULSE_RESET
end else begin
if (( 2 == vi_byte_num ) && (r_write_map )) begin
// INSERT_PULSE_REG
end
end
end
// INSERT_WRITE_WIRES
/*
* All the reading is handled here, both from registered fields and shadowed data.
*/
// Combinationl logic that indicates from which register data is being read
// INSERT_READ_WIRES
// Data is read on rising edge of second rx_valid pulse (byte 1)
always @( posedge i_rx_valid or negedge active ) begin
if ( !active ) begin
r_data_to_send <= 0;
end else begin
// INSERT_READ_REGS
end
end
/*
* Only drive the bus when reading from the map, during byte 2.
*/
assign vio_data_spi = r_read_map ? r_data_to_send : 8'bz;
endmodule // spi_map
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLXTN_BLACKBOX_V
`define SKY130_FD_SC_HS__DLXTN_BLACKBOX_V
/**
* dlxtn: Delay latch, inverted enable, single output.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__dlxtn (
Q ,
D ,
GATE_N
);
output Q ;
input D ;
input GATE_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLXTN_BLACKBOX_V
|
/*
* Copyright 2018-2022 F4PGA Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
// UART transmitter.
module UART_TX(
input rst, clk, baud_edge, data_ready,
input [7:0] data,
output reg tx, data_accepted
);
localparam START = (1 << 0), DATA = (1 << 1), END = (1 << 2);
reg [7:0] data_reg;
reg [2:0] data_counter;
reg [3:0] state;
initial begin
tx <= 1;
data_accepted <= 0;
end
always @(posedge clk) begin
if(rst) begin
state <= END;
tx <= 1;
data_accepted <= 0;
end else if(baud_edge) begin
case(state)
START: begin
tx <= 0;
data_counter <= 0;
state <= DATA;
end
DATA: begin
tx <= data_reg[data_counter];
if(data_counter != 7) begin
data_counter <= data_counter + 1;
end else begin
state <= END;
data_counter <= 0;
end
end
END: begin
tx <= 1;
if(data_ready) begin
data_accepted <= 1;
data_reg <= data;
state <= START;
end
end
default: begin
tx <= 1;
state <= END;
end
endcase
end else begin
data_accepted <= 0;
end
end
endmodule
|
`timescale 1ns / 100ps
/*
* The GPIA_DWORD module describes a 64-bit collection of GPIA_BITs. Each
* octet of bits can be independently masked by its own stb_i input.
*/
module GPIA_DWORD(
input clk_i,
input res_i,
input [1:0] mode_i,
input [63:0] d_i,
input [7:0] stb_i,
output [63:0] q_o
);
GPIA_BYTE byte0(
.clk_i(clk_i),
.res_i(res_i),
.mode_i(mode_i),
.d_i(d_i[7:0]),
.stb_i(stb_i[0]),
.q_o(q_o[7:0])
);
GPIA_BYTE byte1(
.clk_i(clk_i),
.res_i(res_i),
.mode_i(mode_i),
.d_i(d_i[15:8]),
.stb_i(stb_i[1]),
.q_o(q_o[15:8])
);
GPIA_BYTE byte2(
.clk_i(clk_i),
.res_i(res_i),
.mode_i(mode_i),
.d_i(d_i[23:16]),
.stb_i(stb_i[2]),
.q_o(q_o[23:16])
);
GPIA_BYTE byte3(
.clk_i(clk_i),
.res_i(res_i),
.mode_i(mode_i),
.d_i(d_i[31:24]),
.stb_i(stb_i[3]),
.q_o(q_o[31:24])
);
GPIA_BYTE byte4(
.clk_i(clk_i),
.res_i(res_i),
.mode_i(mode_i),
.d_i(d_i[39:32]),
.stb_i(stb_i[4]),
.q_o(q_o[39:32])
);
GPIA_BYTE byte5(
.clk_i(clk_i),
.res_i(res_i),
.mode_i(mode_i),
.d_i(d_i[47:40]),
.stb_i(stb_i[5]),
.q_o(q_o[47:40])
);
GPIA_BYTE byte6(
.clk_i(clk_i),
.res_i(res_i),
.mode_i(mode_i),
.d_i(d_i[55:48]),
.stb_i(stb_i[6]),
.q_o(q_o[55:48])
);
GPIA_BYTE byte7(
.clk_i(clk_i),
.res_i(res_i),
.mode_i(mode_i),
.d_i(d_i[63:56]),
.stb_i(stb_i[7]),
.q_o(q_o[63:56])
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__UDP_MUX_2TO1_TB_V
`define SKY130_FD_SC_LS__UDP_MUX_2TO1_TB_V
/**
* udp_mux_2to1: Two to one multiplexer
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__udp_mux_2to1.v"
module top();
// Inputs are registered
reg A0;
reg A1;
reg S;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A0 = 1'bX;
A1 = 1'bX;
S = 1'bX;
#20 A0 = 1'b0;
#40 A1 = 1'b0;
#60 S = 1'b0;
#80 A0 = 1'b1;
#100 A1 = 1'b1;
#120 S = 1'b1;
#140 A0 = 1'b0;
#160 A1 = 1'b0;
#180 S = 1'b0;
#200 S = 1'b1;
#220 A1 = 1'b1;
#240 A0 = 1'b1;
#260 S = 1'bx;
#280 A1 = 1'bx;
#300 A0 = 1'bx;
end
sky130_fd_sc_ls__udp_mux_2to1 dut (.A0(A0), .A1(A1), .S(S), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__UDP_MUX_2TO1_TB_V
|
`timescale 1ns/10ps
(* FASM_PARAMS="INV.BA1=XAS1;INV.BA2=XAS2;INV.BB1=XBS1;INV.BB2=XBS2" *)
(* MODEL_NAME="T_FRAG" *) // This is intentional!
(* whitebox *)
module B_FRAG (TBS, XAB, XSL, XA1, XA2, XB1, XB2, XZ);
// This is assumed to be connected to const1 in the techmap
input wire TBS;
input wire XAB;
input wire XSL;
input wire XA1;
input wire XA2;
input wire XB1;
input wire XB2;
// These timings differ whether an input inverter is on or off. To model
// this in VPR it would require a different pb_type for each combination
// of inverter configurations! So here we take the worst timing. See
// bels.json for where these are taken from.
(* DELAY_CONST_TBS="{iopath_TBS_CZ}" *)
(* DELAY_CONST_XAB="{iopath_BAB_CZ}" *)
(* DELAY_CONST_XSL="{iopath_BSL_CZ}" *)
(* DELAY_CONST_XA1="{iopath_BA1_CZ}" *)
(* DELAY_CONST_XA2="{iopath_BA2_CZ}" *)
(* DELAY_CONST_XB1="{iopath_BB1_CZ}" *)
(* DELAY_CONST_XB2="{iopath_BB2_CZ}" *)
output wire XZ;
specify
(TBS => XZ) = (0,0);
(XAB => XZ) = (0,0);
(XSL => XZ) = (0,0);
(XA1 => XZ) = (0,0);
(XA2 => XZ) = (0,0);
(XB1 => XZ) = (0,0);
(XB2 => XZ) = (0,0);
endspecify
// Control parameters
parameter [0:0] XAS1 = 1'b0;
parameter [0:0] XAS2 = 1'b0;
parameter [0:0] XBS1 = 1'b0;
parameter [0:0] XBS2 = 1'b0;
// Input routing inverters
wire XAP1 = (XAS1) ? ~XA1 : XA1;
wire XAP2 = (XAS2) ? ~XA2 : XA2;
wire XBP1 = (XBS1) ? ~XB1 : XB1;
wire XBP2 = (XBS2) ? ~XB2 : XB2;
// 1st mux stage
wire XAI = XSL ? XAP2 : XAP1;
wire XBI = XSL ? XBP2 : XBP1;
// 2nd mux stage
wire XZI = XAB ? XBI : XAI;
// 3rd mux stage. Note that this is fake purely to make the VPR work with
// the actual FPGA architecture. It is assumed that TBI is always routed
// to const1 co physically CZ is always connected to the bottom of the
// C_FRAG.
assign XZ = TBS ? XZI : 1'b0;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A311O_1_V
`define SKY130_FD_SC_HD__A311O_1_V
/**
* a311o: 3-input AND into first input of 3-input OR.
*
* X = ((A1 & A2 & A3) | B1 | C1)
*
* Verilog wrapper for a311o with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__a311o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a311o_1 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a311o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a311o_1 (
X ,
A1,
A2,
A3,
B1,
C1
);
output X ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a311o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__A311O_1_V
|
`timescale 1ns / 10ps
module tb_core;
//--------------------------------------------------------------
parameter C_IRQV_SZ = 32;
wire clk;
reg fclk;
wire reset;
reg [1:0] reset_pipe;
wire sleeping;
// hardware interrupt generator
reg [11:0] intr_counter_q;
reg intr_extern;
wire ireqready;
wire ireqvalid;
wire [31:0] ireqaddr;
wire irspready;
wire irspvalid;
wire irsprerr;
wire [31:0] irspdata;
wire dreqready;
wire dreqvalid;
wire dreqdvalid;
wire [31:0] dreqaddr;
wire [31:0] dreqdata;
wire drspready;
wire drspvalid;
wire [31:0] drspdata;
wire mit_en;
wire mit_commit;
wire [31:0] mit_pc;
wire [31:0] mit_ins;
wire [31:0] mit_regs2_data;
wire [31:0] mit_alu_dout;
wire [1:0] mit_mode;
wire mit_trap;
wire [31:0] mit_trap_cause;
wire [31:0] mit_trap_entry_addr;
wire [31:0] mit_trap_rtn_addr;
`ifdef RV_ASSERTS_ON
wire [31:0] rom_data;
`endif
//--------------------------------------------------------------
parameter C_TIMEOUT = 0;
//--------------------------------------------------------------
// general setup
//--------------------------------------------------------------
initial
begin
$display("********************************************************");
$dumpfile("wave.lxt");
$dumpvars(0, tb_core);
$display("******************* SIMULATION START *******************");
$display();
$display();
if (C_TIMEOUT) begin
#(C_TIMEOUT*1000);
$display();
$display();
$display("******************* FAIL - TIMEOUT *******************");
$display("Time = %0tus.", $time/100000);
$fatal();
end
end
//--------------------------------------------------------------
// generate a clock
//--------------------------------------------------------------
assign clk = fclk | sleeping;
//
initial begin
fclk = 1'b0;
reset_pipe = 2'b0;
end
//
always begin
#10ns;
fclk = ~fclk;
end
//--------------------------------------------------------------
// generate a reset
//--------------------------------------------------------------
assign reset = ~reset_pipe[0];
//
initial begin
reset_pipe = 2'b0;
end
//
always @ (posedge clk) begin
reset_pipe <= { 1'b1, reset_pipe[1] };
end
//--------------------------------------------------------------
// hardware interrupt generator
//--------------------------------------------------------------
always @ (posedge fclk or posedge reset) begin
if (reset) begin
intr_counter_q <= 12'b0;
intr_extern <= 1'b0;
end else begin
if ((dreqvalid & dreqvalid == 1'b1) && (dreqaddr == 32'h00000004)) begin
// for some reason using addr 0 causes the compiler to insert an ebreak
intr_counter_q <= 12'b0;
intr_extern <= 1'b0;
end else if (intr_counter_q == 1024) begin//{ 12 {1'b1} }) begin
intr_extern <= 1'b1;
end else begin
intr_counter_q <= intr_counter_q + 1;
end
end
end
//--------------------------------------------------------------
// merlin core
//--------------------------------------------------------------
merlin
`ifndef GATES
#(
.C_WORD_RESET_VECTOR (30'b0)
)
`endif
i_merlin (
// global
.clk_i (clk),
.fclk_i (fclk),
.reset_i (reset),
// core status
.sleeping_o (sleeping),
// hardware interrupt interface
.irqm_extern_i (intr_extern),
.irqm_softw_i (1'b0),
.irqm_timer_i (1'b0),
.irqs_extern_i (1'b0),
// instruction port
.ireqready_i (ireqready),
.ireqvalid_o (ireqvalid),
.ireqhpl_o (),
.ireqaddr_o (ireqaddr),
.irspready_o (irspready),
.irspvalid_i (irspvalid),
.irsprerr_i (irsprerr),
.irspdata_i (irspdata),
// data port
.dreqready_i (dreqready),
.dreqvalid_o (dreqvalid),
.dreqsize_o (),
.dreqwrite_o (dreqdvalid),
.dreqhpl_o (),
.dreqaddr_o (dreqaddr),
.dreqdata_o (dreqdata),
.drspready_o (drspready),
.drspvalid_i (drspvalid),
.drsprerr_i (1'b0),
.drspwerr_i (1'b0),
.drspdata_i (drspdata),
// instruction trace port
.mit_en_o (mit_en),
.mit_commit_o (mit_commit),
.mit_pc_o (mit_pc),
.mit_ins_o (mit_ins),
.mit_regs2_data_o (mit_regs2_data),
.mit_alu_dout_o (mit_alu_dout),
.mit_mode_o (mit_mode),
.mit_trap_o (mit_trap),
.mit_trap_cause_o (mit_trap_cause),
.mit_trap_entry_addr_o (mit_trap_entry_addr),
.mit_trap_rtn_addr_o (mit_trap_rtn_addr)
// debug interface
// TODO - debug interface
);
//--------------------------------------------------------------
// core tracer
//--------------------------------------------------------------
merlin_rv32ic_trace_logger i_merlin_rv32ic_trace_logger (
// global
.clk_i (clk),
.reset_i (reset),
// tracer interface
.ex_stage_en_i (mit_en),
.execute_commit_i (mit_commit),
.ins_addr_i (mit_pc),
.ins_value_i (mit_ins),
.regs2_data_i (mit_regs2_data),
.alu_dout_i (mit_alu_dout),
.csr_mode_i (mit_mode),
.csr_jump_to_trap_i (mit_trap),
.csr_trap_cause_i (mit_trap_cause),
.csr_trap_entry_addr_i (mit_trap_entry_addr),
.csr_trap_rtn_addr_i (mit_trap_rtn_addr)
);
//--------------------------------------------------------------
// boot rom
//--------------------------------------------------------------
boot_rom i_boot_rom
(
// global
.clk (clk),
.reset (reset),
// instruction port
.treqready (ireqready),
.treqvalid (ireqvalid),
.treqpriv (2'b0),
.treqaddr (ireqaddr),
.trspready (irspready),
.trspvalid (irspvalid),
.trsprerr (irsprerr),
.trspdata (irspdata)
);
//--------------------------------------------------------------
// sram
//--------------------------------------------------------------
ssram i_ssram
(
// global
.clk_i (clk),
.clk_en_i (1'b1),
.reset_i (reset),
//
.treqready_o (dreqready),
.treqvalid_i (dreqvalid),
.treqdvalid_i (dreqdvalid),
.treqaddr_i (dreqaddr),
.treqdata_i (dreqdata),
.trspready_i (drspready),
.trspvalid_o (drspvalid),
.trspdata_o (drspdata)
);
//--------------------------------------------------------------
// assersions
//--------------------------------------------------------------
`ifdef RV_ASSERTS_ON
assign rom_data[ 7: 0] = i_boot_rom.mem[i_merlin.pfu_ids_pc + 0];
assign rom_data[15: 8] = i_boot_rom.mem[i_merlin.pfu_ids_pc + 1];
assign rom_data[23:16] = i_boot_rom.mem[i_merlin.pfu_ids_pc + 2];
assign rom_data[31:24] = i_boot_rom.mem[i_merlin.pfu_ids_pc + 3];
always @ (posedge clk or posedge reset) begin
if (reset) begin
end else begin
if (i_merlin.pfu_ids_dav == 1'b1) begin
if (i_merlin.pfu_ids_ins != rom_data) begin
$display("ERROR: PFU data output missmatch, Got 0x%08X, Expected 0x%08X.", i_merlin.pfu_ids_ins, rom_data);
end
end
end
end
`endif
endmodule
|
// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\Count_Up_Down.v
// Created: 2014-09-08 14:12:09
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: Count_Up_Down
// Source Path: controllerPeripheralHdlAdi/Encoder_Peripheral_Hardware_Specification/Debounce_A/Count_Up_Down
// Hierarchy Level: 3
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module Count_Up_Down
(
CLK_IN,
reset,
enb,
u,
count_debounce,
y
);
input CLK_IN;
input reset;
input enb;
input u;
input [7:0] count_debounce; // uint8
output y;
reg u_n1;
reg [7:0] count; // uint8
reg y_reg;
reg u_n1_next;
reg [7:0] count_next; // uint8
reg y_reg_next;
reg [8:0] add_temp_1; // ufix9
always @(posedge CLK_IN)
begin : libDebounce_c2_Count_Up_Down_process
if (reset == 1'b1) begin
u_n1 <= 1'b0;
count <= 8'd0;
y_reg <= 1'b0;
end
else if (enb) begin
u_n1 <= u_n1_next;
count <= count_next;
y_reg <= y_reg_next;
end
end
always @(u, u_n1, count, count_debounce, y_reg) begin
count_next = count;
y_reg_next = y_reg;
//Gateway: Debounce/Count_Up_Down
//During: Debounce/Count_Up_Down
//Entry Internal: Debounce/Count_Up_Down
//Transition: '<S10>:27'
if (u == u_n1) begin
//Transition: '<S10>:4'
//Transition: '<S10>:6'
if (count >= count_debounce) begin
//Transition: '<S10>:8'
//Transition: '<S10>:10'
y_reg_next = u;
//Transition: '<S10>:16'
end
else begin
//Transition: '<S10>:12'
add_temp_1 = count + 1;
if (add_temp_1[8] != 1'b0) begin
count_next = 8'b11111111;
end
else begin
count_next = add_temp_1[7:0];
end
end
//Transition: '<S10>:15'
end
else begin
//Transition: '<S10>:14'
count_next = 8'd0;
end
//Transition: '<S10>:18'
u_n1_next = u;
end
assign y = y_reg_next;
endmodule // Count_Up_Down
|
module handshake(error, clk, req, ack, reset);
output reg error;
input clk, req, ack, reset;
reg [2:0] state;
initial
begin
state = 3'b000;
error = 1'b0;
end
always @(posedge clk)
begin
case (state)
3'b000:
begin
if (~req && ~ack)
state = 3'b000;
else if (req && ~ack)
state = 3'b001;
else
begin
state = 3'b100;
error = 1'b1;
end
end
3'b001:
begin
if (req && ~ack)
state = 3'b001;
else if (req && ack)
state = 3'b010;
else
begin
state = 3'b100;
error = 1'b1;
end
end
3'b010:
begin
if (req && ack)
state = 3'b010;
else if (~req && ack)
state = 3'b011;
else
begin
state = 3'b100;
error = 1'b1;
end
end
3'b011:
begin
if (~req && ack)
state = 3'b011;
else if (~req && ~ack)
state = 3'b000;
else
begin
state = 3'b100;
error = 1'b1;
end
end
3'b100:
begin
if (reset)
begin
state = 3'b000;
error = 1'b0;
end
end
default:
begin
state = 3'b100;
error = 1'b1;
end
endcase
end
endmodule
|
`timescale 1ns / 1ps
`default_nettype none
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:18:53 06/03/2015
// Design Name:
// Module Name: ps2_keyb
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module ps2_keyb(
input wire clk,
inout wire clkps2,
inout wire dataps2,
//---------------------------------
input wire [7:0] rows,
output wire [4:0] cols,
output wire [4:0] joy,
output wire rst_out_n,
output wire nmi_out_n,
output wire mrst_out_n,
output wire [4:0] user_toggles,
output reg video_output_change,
//---------------------------------
input wire [7:0] zxuno_addr,
input wire zxuno_regrd,
input wire zxuno_regwr,
input wire regaddr_changed,
input wire [7:0] din,
output wire [7:0] keymap_dout,
output wire oe_n_keymap,
output wire [7:0] scancode_dout,
output wire oe_n_scancode,
output reg [7:0] kbstatus_dout,
output wire oe_n_kbstatus
);
parameter SCANCODE = 8'h04;
parameter KBSTATUS = 8'h05;
parameter KEYMAP = 8'h07;
wire master_reset, user_reset, user_nmi;
assign mrst_out_n = ~master_reset;
assign rst_out_n = ~user_reset;
assign nmi_out_n = ~user_nmi;
assign oe_n_keymap = ~(zxuno_addr == KEYMAP && zxuno_regrd == 1'b1);
assign oe_n_scancode = ~(zxuno_addr == SCANCODE && zxuno_regrd == 1'b1);
assign oe_n_kbstatus = ~(zxuno_addr == KBSTATUS && zxuno_regrd == 1'b1);
wire [7:0] kbcode;
wire ps2busy;
wire kberror;
wire nueva_tecla;
wire no_hay_teclas_pulsadas;
wire extended;
wire released;
assign scancode_dout = kbcode;
/*
| BSY | x | x | x | ERR | RLS | EXT | PEN |
*/
reg reading_kbstatus = 1'b0;
initial video_output_change = 1'b0;
always @(posedge clk) begin
kbstatus_dout[7:1] <= {ps2busy, 3'b000, kberror, released, extended};
if (nueva_tecla == 1'b1) begin
kbstatus_dout[0] <= 1'b1;
if (kbcode == 8'h7E && released == 1'b0 && extended == 1'b0) // SCRLock to change between RGB and VGA 60Hz
video_output_change <= 1'b1;
else
video_output_change <= 1'b0;
end
if (oe_n_kbstatus == 1'b0)
reading_kbstatus <= 1'b1;
else if (reading_kbstatus == 1'b1) begin
kbstatus_dout[0] <= 1'b0;
reading_kbstatus <= 1'b0;
end
if (video_output_change == 1'b1)
video_output_change <= 1'b0;
end
ps2_port lectura_de_teclado (
.clk(clk),
.enable_rcv(~ps2busy),
.kb_or_mouse(1'b0),
.ps2clk_ext(clkps2),
.ps2data_ext(dataps2),
.kb_interrupt(nueva_tecla),
.scancode(kbcode),
.released(released),
.extended(extended)
);
keyboard_pressed_status teclado_limpio (
.clk(clk),
.rst(1'b0),
.scan_received(nueva_tecla),
.scancode(kbcode),
.extended(extended),
.released(released),
.kbclean(no_hay_teclas_pulsadas)
);
scancode_to_speccy traductor (
.clk(clk),
.rst(1'b0),
.scan_received(nueva_tecla),
.scan(kbcode),
.extended(extended),
.released(released),
.kbclean(no_hay_teclas_pulsadas),
.sp_row(rows),
.sp_col(cols),
.joyup(joy[3]),
.joydown(joy[2]),
.joyleft(joy[1]),
.joyright(joy[0]),
.joyfire(joy[4]),
.master_reset(master_reset),
.user_reset(user_reset),
.user_nmi(user_nmi),
.user_toggles(user_toggles),
.din(din),
.dout(keymap_dout),
.cpuwrite(zxuno_addr == KEYMAP && zxuno_regwr == 1'b1),
.cpuread(zxuno_addr == KEYMAP && zxuno_regrd == 1'b1),
.rewind(regaddr_changed == 1'b1 && zxuno_addr == KEYMAP)
);
ps2_host_to_kb escritura_a_teclado (
.clk(clk),
.ps2clk_ext(clkps2),
.ps2data_ext(dataps2),
.data(din),
.dataload(zxuno_addr == SCANCODE && zxuno_regwr== 1'b1),
.ps2busy(ps2busy),
.ps2error(kberror)
);
endmodule
|
`timescale 1ns / 1ps
module TX
#( parameter stateA = 'b00001,
parameter stateB = 'b00010,
parameter stateC = 'b00100,
parameter stateD = 'b01000,
parameter stateE = 'b10000)
(input clk,
input baud_rate,
input [7:0]d_in,
input tx_start,
output reg tx,
output reg tx_done);
reg [4:0] state = stateA;
reg [4:0] next_state = stateA;
reg tick_enable = 0;
integer count = 0;
reg rst_count = 1;
integer bit_count = 0;
reg [7:0] d_aux;
always@(posedge clk)
begin
state=next_state;
end
always@(posedge clk)
begin
case(state)
stateA:
if(tx_start == 1) next_state = stateB;
else next_state = stateA;
stateB:
if(bit_count == 1) next_state = stateC;
else next_state = stateB;
stateC:
if(bit_count == 9) next_state = stateD;
else next_state = stateC;
stateD:
if(bit_count == 10) next_state = stateE;
else next_state = stateD;
stateE:
if(tx_done == 1) next_state = stateA;
else next_state = stateE;
endcase
end
always@(posedge clk)
begin
case(state)
stateA:
begin
tx = 1;
tx_done = 1;
rst_count = 0;
tick_enable = 0;
end
stateB:
begin
tx_done = 0;
rst_count = 1;
tick_enable = 1;
if(count == 16)
begin
tx = 0;
d_aux = d_in;
bit_count = bit_count + 1;
rst_count = 0;
end
end
stateC:
begin
rst_count = 1;
if(count == 16)
begin
tx = d_aux[0];
d_aux = d_aux >> 1;
bit_count = bit_count + 1;
rst_count = 0;
end
end
stateD:
begin
rst_count = 1;
if(count == 16)
begin
tx = 1;
bit_count = bit_count + 1;
rst_count = 0;
end
end
stateE:
begin
if(count == 16)
begin
bit_count = 0;
tx_done = 1;
end
end
endcase
end
always@(posedge baud_rate or negedge rst_count)
begin
if(rst_count == 0) count = 0;
else
begin
if(tick_enable == 1)count = count + 1;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NOR2B_BLACKBOX_V
`define SKY130_FD_SC_HDLL__NOR2B_BLACKBOX_V
/**
* nor2b: 2-input NOR, first input inverted.
*
* Y = !(A | B | C | !D)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__nor2b (
Y ,
A ,
B_N
);
output Y ;
input A ;
input B_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NOR2B_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NOR2_1_V
`define SKY130_FD_SC_HD__NOR2_1_V
/**
* nor2: 2-input NOR.
*
* Verilog wrapper for nor2 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__nor2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__nor2_1 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__nor2 base (
.Y(Y),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__nor2_1 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__nor2 base (
.Y(Y),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__NOR2_1_V
|
// AUTOGEN
module iobus_4_connect(
// unused
input wire clk,
input wire reset,
// Master
input wire m_iob_poweron,
input wire m_iob_reset,
input wire m_datao_clear,
input wire m_datao_set,
input wire m_cono_clear,
input wire m_cono_set,
input wire m_iob_fm_datai,
input wire m_iob_fm_status,
input wire m_rdi_pulse,
input wire [3:9] m_ios,
input wire [0:35] m_iob_write,
output wire [1:7] m_pi_req,
output wire [0:35] m_iob_read,
output wire m_dr_split,
output wire m_rdi_data,
// Slave 0
output wire s0_iob_poweron,
output wire s0_iob_reset,
output wire s0_datao_clear,
output wire s0_datao_set,
output wire s0_cono_clear,
output wire s0_cono_set,
output wire s0_iob_fm_datai,
output wire s0_iob_fm_status,
output wire s0_rdi_pulse,
output wire [3:9] s0_ios,
output wire [0:35] s0_iob_write,
input wire [1:7] s0_pi_req,
input wire [0:35] s0_iob_read,
input wire s0_dr_split,
input wire s0_rdi_data,
// Slave 1
output wire s1_iob_poweron,
output wire s1_iob_reset,
output wire s1_datao_clear,
output wire s1_datao_set,
output wire s1_cono_clear,
output wire s1_cono_set,
output wire s1_iob_fm_datai,
output wire s1_iob_fm_status,
output wire s1_rdi_pulse,
output wire [3:9] s1_ios,
output wire [0:35] s1_iob_write,
input wire [1:7] s1_pi_req,
input wire [0:35] s1_iob_read,
input wire s1_dr_split,
input wire s1_rdi_data,
// Slave 2
output wire s2_iob_poweron,
output wire s2_iob_reset,
output wire s2_datao_clear,
output wire s2_datao_set,
output wire s2_cono_clear,
output wire s2_cono_set,
output wire s2_iob_fm_datai,
output wire s2_iob_fm_status,
output wire s2_rdi_pulse,
output wire [3:9] s2_ios,
output wire [0:35] s2_iob_write,
input wire [1:7] s2_pi_req,
input wire [0:35] s2_iob_read,
input wire s2_dr_split,
input wire s2_rdi_data,
// Slave 3
output wire s3_iob_poweron,
output wire s3_iob_reset,
output wire s3_datao_clear,
output wire s3_datao_set,
output wire s3_cono_clear,
output wire s3_cono_set,
output wire s3_iob_fm_datai,
output wire s3_iob_fm_status,
output wire s3_rdi_pulse,
output wire [3:9] s3_ios,
output wire [0:35] s3_iob_write,
input wire [1:7] s3_pi_req,
input wire [0:35] s3_iob_read,
input wire s3_dr_split,
input wire s3_rdi_data
);
assign m_pi_req = 0 | s0_pi_req | s1_pi_req | s2_pi_req | s3_pi_req;
assign m_iob_read = m_iob_write | s0_iob_read | s1_iob_read | s2_iob_read | s3_iob_read;
assign m_dr_split = 0 | s0_dr_split | s1_dr_split | s2_dr_split | s3_dr_split;
assign m_rdi_data = 0 | s0_rdi_data | s1_rdi_data | s2_rdi_data | s3_rdi_data;
assign s0_iob_poweron = m_iob_poweron;
assign s0_iob_reset = m_iob_reset;
assign s0_datao_clear = m_datao_clear;
assign s0_datao_set = m_datao_set;
assign s0_cono_clear = m_cono_clear;
assign s0_cono_set = m_cono_set;
assign s0_iob_fm_datai = m_iob_fm_datai;
assign s0_iob_fm_status = m_iob_fm_status;
assign s0_rdi_pulse = m_rdi_pulse;
assign s0_ios = m_ios;
assign s0_iob_write = m_iob_write;
assign s1_iob_poweron = m_iob_poweron;
assign s1_iob_reset = m_iob_reset;
assign s1_datao_clear = m_datao_clear;
assign s1_datao_set = m_datao_set;
assign s1_cono_clear = m_cono_clear;
assign s1_cono_set = m_cono_set;
assign s1_iob_fm_datai = m_iob_fm_datai;
assign s1_iob_fm_status = m_iob_fm_status;
assign s1_rdi_pulse = m_rdi_pulse;
assign s1_ios = m_ios;
assign s1_iob_write = m_iob_write;
assign s2_iob_poweron = m_iob_poweron;
assign s2_iob_reset = m_iob_reset;
assign s2_datao_clear = m_datao_clear;
assign s2_datao_set = m_datao_set;
assign s2_cono_clear = m_cono_clear;
assign s2_cono_set = m_cono_set;
assign s2_iob_fm_datai = m_iob_fm_datai;
assign s2_iob_fm_status = m_iob_fm_status;
assign s2_rdi_pulse = m_rdi_pulse;
assign s2_ios = m_ios;
assign s2_iob_write = m_iob_write;
assign s3_iob_poweron = m_iob_poweron;
assign s3_iob_reset = m_iob_reset;
assign s3_datao_clear = m_datao_clear;
assign s3_datao_set = m_datao_set;
assign s3_cono_clear = m_cono_clear;
assign s3_cono_set = m_cono_set;
assign s3_iob_fm_datai = m_iob_fm_datai;
assign s3_iob_fm_status = m_iob_fm_status;
assign s3_rdi_pulse = m_rdi_pulse;
assign s3_ios = m_ios;
assign s3_iob_write = m_iob_write;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__NAND2_SYMBOL_V
`define SKY130_FD_SC_HVL__NAND2_SYMBOL_V
/**
* nand2: 2-input NAND.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__nand2 (
//# {{data|Data Signals}}
input A,
input B,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__NAND2_SYMBOL_V
|
module CapBoardDecoder(clk,swIn,enable,tuningCode,boardOut);
//CapBoardDecoder - module for CPLD controlling state on Cap Board - decodes
//global tuning configuration state by comparing the global number to the
//board address. Handles 4 IDs per board.
//Ted Golfinopoulos, v1.0 begun on 7 September 2011
//Ted Golfinopoulos, v2.0 on 13 October 2011 - trigger on enable level rather than
// enable edge - get rid of issue wherein
// code bits get interpreted internally as
// enable edges (circuit only, not in simulations).
//NOTE: Default type is WIRE (NET variety type)
input clk; //Needed clock because there is cross-talk in the CPLD and bounce on signals.
reg [3:0] clkCnt; //Counter for clock.
reg [3:0] clkCntAddr; //Counter for timing how long address switch state has been stable.
//swIn: Contains binary number corresponding to switches holding board address.
//When switches are ON, state is LOW. So inversion is necessary.
//Also, there are four unique IDs per board:
//addr, addr+1, addr+2, and addr+3
//Original design plans for around 20 boards, but there are only 6 switches
//per board, so need to multiply the board number by a scale number, the
//number of unique IDs per board.
//So address number must process swIn by first INVERTing and then
//multiplying the number.
input [5:0] swIn;
//21 May 2012 - add hysterisis to address to see if it fixes trip problem (i.e. address being modified eroneously during operation).
reg [5:0] swInPrevious;
reg [5:0] swInStable;
reg [6:0] addr;
//enable: when this bit is high, it is okay to change the tuning state.
//It is set by the master controller and makes sure output is stable first.
//Make a register.
input enable;
//tuningCode: Holds binary number corresponding to global tuning number.
//Compare to this number to determine which IDs to turn on.
input [6:0] tuningCode;
//boardOut: This holds the state of the board - each bit corresponds to
//one of the board ID cap switches. ON means switch in corresponding cap ID.
//boardState: register to hold board output in procedural blocks.
output [3:0] boardOut;
reg [3:0] boardState;
//Parameterize the number of capacitor levels per board. That is, there
//are numIDsPerBoard levels for serial or parallel caps.
parameter numIDsPerBoard=4;
parameter waitBit=2; //enable must be on until clkCnt[waitBit] goes high. 2 clock cycles at 4 MHz causes intermittent turn-on with the wrong trigger bit. 4 clock cycles seems to be enough to eliminate false turn-on.
parameter ADDR_WAIT=4'b1111;
initial begin
#0;
clkCnt = 3'b0; //Initialize clock counter.
boardState = 4'b0; //Initialize so that all capacitors are off - baseload, only.
addr=7'b0000001; //Initialize so that all capacitors are off - baseload, only.
end
//DECODE TUNING CODE AND UPDATE BOARD STATE:
//When the ENABLE bit has a rising edge, sample the tuning number
//and trigger an update in state.
always @(posedge clk) begin
//enable must be on for certain number of consecutive clock cycles.
if (enable==1'b1) clkCnt=clkCnt+3'b1; //Increment counter.
else clkCnt=3'b0; //Else, zero out clkCnt.
//Update state condition: enable has been asserted for a sufficient amount of time,
//as measured on counter.
if(clkCnt[waitBit]==1'b1 && enable==1'b1) begin
//#4 Simulate delay
boardState = {tuningCode>=(addr+7'b11),
tuningCode>=(addr+7'b10),
tuningCode>=(addr+7'b01),
tuningCode>=(addr+7'b00)};
clkCnt = 3'b0; //Refresh clock counter.
end
end
//Force address to hold new state for some time before changing.
always @(posedge clk) begin
//If the switch state changes, start a counter. The counter is incremented
//every clock cycle that the current switch state has the same value as the
//changed-to state that initiated the counter. Once the counter has reached
//a threshold value, the switch state is assumed stable, and the register
//used to calculate the address is updated.
//Note that initially, the board won't know its address.
if(swInPrevious != swIn) begin
swInPrevious=swIn; //Start tracking new switch state.
clkCntAddr=1'b0; //Zero counter.
end else if(swInPrevious == swIn && clkCntAddr < ADDR_WAIT) begin
clkCntAddr=clkCntAddr+1'b1; //Increment timer since switch state hasn't changed.
end else begin
swInStable=swInPrevious; //Update stable switch state
end
//Process switch input to derive useful board address.
//Remember: addr is bitwise-inverted because a HIGH on the switch corresponds to
//the switch being in the OFF state.
addr=((~swInStable) - 1'b1)*numIDsPerBoard+1'b1;
//addr=3'b101; //Lock for Board #2 to see if this fixes trip.
//addr=1'b1; //Lock for Board #1 to see if this fixes trip in Board #1.
end
//Set board state output from register to net (wires).
assign boardOut=boardState;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__CLKDLYBUF4S15_2_V
`define SKY130_FD_SC_LP__CLKDLYBUF4S15_2_V
/**
* clkdlybuf4s15: Clock Delay Buffer 4-stage 0.15um length inner stage
* gates.
*
* Verilog wrapper for clkdlybuf4s15 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__clkdlybuf4s15.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__clkdlybuf4s15_2 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__clkdlybuf4s15 base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__clkdlybuf4s15_2 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__clkdlybuf4s15 base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__CLKDLYBUF4S15_2_V
|
/**
\file "inverters-syntax-err.v"
Chain a bunch of inverters between VPI/VCS and prsim, shoelacing.
$Id: inverters.v,v 1.3 2010/04/06 00:08:35 fang Exp $
Thanks to Ilya Ganusov for contributing this test.
*/
`timescale 1ns/1ps
`include "clkgen.v"
module timeunit;
initial $timeformat(-9,1," ns",9);
endmodule
module TOP;
wire in;
reg out0, out1, out2, out3, out;
clk_gen #(.HALF_PERIOD(1)) clk(in);
// prsim stuff
initial
begin
// @haco@ inverters.haco-c
$prsim("inverters.haco-c");
$prsim_cmd("echo $start of simulation");
$prsim_cmd("get in0 X"); // bad command
// should fail stop
$to_prsim("TOP.in", "in0");
$to_prsim("TOP.out0", "in1");
$to_prsim("TOP.out1", "in2");
$to_prsim("TOP.out2", "in3");
$to_prsim("TOP.out3", "in4");
$from_prsim("out0","TOP.out0");
$from_prsim("out1","TOP.out1");
$from_prsim("out2","TOP.out2");
$from_prsim("out3","TOP.out3");
$from_prsim("out4","TOP.out");
end
initial #45 $finish;
always @(in)
begin
$display("at time %7.3f, observed in %b", $realtime,in);
end
always @(out)
begin
$display("at time %7.3f, observed out = %b", $realtime,out);
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DECAPKAPWR_BLACKBOX_V
`define SKY130_FD_SC_LP__DECAPKAPWR_BLACKBOX_V
/**
* decapkapwr: Decoupling capacitance filler on keep-alive rail.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__decapkapwr ();
// Voltage supply signals
supply1 KAPWR;
supply1 VPWR ;
supply0 VGND ;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DECAPKAPWR_BLACKBOX_V
|
/*
* Copyright (c) 2015-2016 The Ultiparc Project. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
/*
* Testbench for programmable interval timer
*/
`include "common.vh"
`include "ocp_const.vh"
`ifndef TRACE_FILE
`define TRACE_FILE "trace.vcd"
`endif
module tb_interval_timer();
localparam HCLK = 5;
localparam PCLK = 2*HCLK; /* Clock period */
/* Timer Registers */
localparam [`ADDR_WIDTH-1:0] CTRLREG = 32'h000; /* Control register */
localparam [`ADDR_WIDTH-1:0] CNTRREG = 32'h004; /* Counter register */
localparam [`ADDR_WIDTH-1:0] CURRREG = 32'h008; /* Current counter */
reg clk;
reg nrst;
reg [`ADDR_WIDTH-1:0] MAddr;
reg [2:0] MCmd;
reg [`DATA_WIDTH-1:0] MData;
reg [`BEN_WIDTH-1:0] MByteEn;
wire SCmdAccept;
wire [`DATA_WIDTH-1:0] SData;
wire [1:0] SResp;
wire intr;
always
#HCLK clk = !clk;
/* Issue bus read transaction */
task bus_read;
input [`ADDR_WIDTH-1:0] addr;
begin
@(posedge clk)
begin
MAddr <= addr;
MByteEn <= 4'hf;
MCmd <= `OCP_CMD_READ;
end
@(posedge clk)
begin
MAddr <= 0;
MByteEn <= 4'h0;
MCmd <= `OCP_CMD_IDLE;
end
end
endtask
/* Issue bus write transaction */
task bus_write;
input [`ADDR_WIDTH-1:0] addr;
input [`DATA_WIDTH-1:0] data;
begin
@(posedge clk)
begin
MAddr <= addr;
MData <= data;
MByteEn <= 4'hf;
MCmd <= `OCP_CMD_WRITE;
end
@(posedge clk)
begin
MAddr <= 0;
MData <= 0;
MByteEn <= 4'h0;
MCmd <= `OCP_CMD_IDLE;
end
end
endtask
initial
begin
/* Set tracing */
$dumpfile(`TRACE_FILE);
$dumpvars(0, tb_interval_timer);
clk = 1;
nrst = 0;
MAddr = 0;
MData = 0;
MByteEn = 0;
MCmd = 0;
#(10*PCLK) nrst = 1;
#(2*PCLK)
/* Set counter value */
bus_write(CNTRREG, 32'h10);
/* Start: enable = 1, reload = 1, imask = 1 */
bus_write(CTRLREG, 32'h7);
/* Read control register */
bus_read(CTRLREG);
/* Read counter register */
bus_read(CNTRREG);
/* Read current count (1) */
bus_read(CURRREG);
/* Read current count (2) */
bus_read(CURRREG);
#(40*PCLK)
/* Update counter value */
bus_write(CNTRREG, 32'h4);
#(20*PCLK)
/* Start: enable = 1, reload = 0, imask = 0 */
bus_write(CTRLREG, 32'h1);
/* Update counter value */
bus_write(CNTRREG, 32'h8);
#500 $finish;
end
/* Instantiate timer */
interval_timer timer(
.clk(clk),
.nrst(nrst),
.i_MAddr(MAddr),
.i_MCmd(MCmd),
.i_MData(MData),
.i_MByteEn(MByteEn),
.o_SCmdAccept(SCmdAccept),
.o_SData(SData),
.o_SResp(SResp),
.o_intr(intr)
);
endmodule /* tb_interval_timer */
|
`timescale 1 us / 1 us
`include "../source/RAM2.v"
module testRAM;
reg[15:0] addr;
reg clk;
reg rst;
reg we;
reg re;
reg[15:0] wdata;
wire[15:0] rdata;
wire ready;
RAM2 mem (
.rst (rst),
.clk (clk),
.we (we),
.re (re),
.addr (addr),
.wdata (wdata),
.rdata (rdata),
.ready (ready)
);
always
#5 clk = !clk;
initial begin
$dumpfile ("../test.vcd");
$dumpvars;
end
initial begin
$display ("\t\ttime,\tclk,\taddr,\twdata,\trdata,\twe");
$monitor ( "%d,\t%b,\t%4h,\t%2h,\t%2h,\t%b",
$time, clk, addr, wdata, rdata, we);
end
initial begin
rst = 1;
clk = 0;
we = 0;
re = 0;
addr = 16'h0000;
wdata = 16'h0000;
#10 rst = 0; re = 1;
#20 wdata = 16'h1212; we = 1; re = 0;
#10 we = 0;
#10 addr = 16'h0001; re = 1;
#20 wdata = 16'h3434; we = 1; re = 0;
#10 we = 0;
#10 addr = 16'hABCD; re = 1;
#20 wdata = 16'h5656; we = 1; re = 0;
#10 we = 0;
#10 addr = 16'h0000; re = 1;
#20 addr = 16'h0001; re = 1;
#20 addr = 16'hABCD; re = 1;
#20 re = 0;
#10 rst = 1;
#10 $finish;
end
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
sys_rst,
sys_clk_p,
sys_clk_n,
uart_sin,
uart_sout,
ddr3_addr,
ddr3_ba,
ddr3_cas_n,
ddr3_ck_n,
ddr3_ck_p,
ddr3_cke,
ddr3_cs_n,
ddr3_dm,
ddr3_dq,
ddr3_dqs_n,
ddr3_dqs_p,
ddr3_odt,
ddr3_ras_n,
ddr3_reset_n,
ddr3_we_n,
linear_flash_addr,
linear_flash_adv_ldn,
linear_flash_ce_n,
linear_flash_oen,
linear_flash_wen,
linear_flash_dq_io,
sgmii_rxp,
sgmii_rxn,
sgmii_txp,
sgmii_txn,
phy_rstn,
mgt_clk_p,
mgt_clk_n,
mdio_mdc,
mdio_mdio,
fan_pwm,
gpio_lcd,
gpio_bd,
iic_rstn,
iic_scl,
iic_sda,
rx_clk_in_p,
rx_clk_in_n,
rx_frame_in_p,
rx_frame_in_n,
rx_data_in_p,
rx_data_in_n,
tx_clk_out_p,
tx_clk_out_n,
tx_frame_out_p,
tx_frame_out_n,
tx_data_out_p,
tx_data_out_n,
txnrx,
enable,
gpio_resetb,
gpio_sync,
gpio_en_agc,
gpio_ctl,
gpio_status,
spi_csn_0,
spi_clk,
spi_mosi,
spi_miso
);
input sys_rst;
input sys_clk_p;
input sys_clk_n;
input uart_sin;
output uart_sout;
output [13:0] ddr3_addr;
output [ 2:0] ddr3_ba;
output ddr3_cas_n;
output [ 0:0] ddr3_ck_n;
output [ 0:0] ddr3_ck_p;
output [ 0:0] ddr3_cke;
output [ 0:0] ddr3_cs_n;
output [ 7:0] ddr3_dm;
inout [63:0] ddr3_dq;
inout [ 7:0] ddr3_dqs_n;
inout [ 7:0] ddr3_dqs_p;
output [ 0:0] ddr3_odt;
output ddr3_ras_n;
output ddr3_reset_n;
output ddr3_we_n;
input sgmii_rxp;
input sgmii_rxn;
output sgmii_txp;
output sgmii_txn;
output phy_rstn;
input mgt_clk_p;
input mgt_clk_n;
output mdio_mdc;
inout mdio_mdio;
output fan_pwm;
output [26:1] linear_flash_addr;
output linear_flash_adv_ldn;
output linear_flash_ce_n;
output linear_flash_oen;
output linear_flash_wen;
inout [15:0] linear_flash_dq_io;
inout [ 6:0] gpio_lcd;
inout [20:0] gpio_bd;
output iic_rstn;
inout iic_scl;
inout iic_sda;
input rx_clk_in_p;
input rx_clk_in_n;
input rx_frame_in_p;
input rx_frame_in_n;
input [ 5:0] rx_data_in_p;
input [ 5:0] rx_data_in_n;
output tx_clk_out_p;
output tx_clk_out_n;
output tx_frame_out_p;
output tx_frame_out_n;
output [ 5:0] tx_data_out_p;
output [ 5:0] tx_data_out_n;
output txnrx;
output enable;
inout gpio_resetb;
inout gpio_sync;
inout gpio_en_agc;
inout [ 3:0] gpio_ctl;
inout [ 7:0] gpio_status;
output spi_csn_0;
output spi_clk;
output spi_mosi;
input spi_miso;
// internal signals
wire [63:0] gpio_i;
wire [63:0] gpio_o;
wire [63:0] gpio_t;
wire [ 7:0] spi_csn;
wire spi_clk;
wire spi_mosi;
wire spi_miso;
wire tdd_enable_s;
wire gpio_enable;
wire gpio_txnrx;
wire enable_s;
wire txnrx_s;
// default logic
assign fan_pwm = 1'b1;
assign iic_rstn = 1'b1;
assign spi_csn_0 = spi_csn[0];
assign enable = (tdd_enable_s == 1'b1) ? enable_s : gpio_enable;
assign txnrx = (tdd_enable_s == 1'b1) ? txnrx_s : gpio_txnrx;
// instantiations
ad_iobuf #(.DATA_WIDTH(17)) i_iobuf (
.dio_t (gpio_t[48:32]),
.dio_i (gpio_o[48:32]),
.dio_o (gpio_i[48:32]),
.dio_p ({ gpio_txnrx,
gpio_enable,
gpio_resetb,
gpio_sync,
gpio_en_agc,
gpio_ctl,
gpio_status}));
ad_iobuf #(.DATA_WIDTH(21)) i_iobuf_sw_led (
.dio_t (gpio_t[20:0]),
.dio_i (gpio_o[20:0]),
.dio_o (gpio_i[20:0]),
.dio_p (gpio_bd));
system_wrapper i_system_wrapper (
.ddr3_addr (ddr3_addr),
.ddr3_ba (ddr3_ba),
.ddr3_cas_n (ddr3_cas_n),
.ddr3_ck_n (ddr3_ck_n),
.ddr3_ck_p (ddr3_ck_p),
.ddr3_cke (ddr3_cke),
.ddr3_cs_n (ddr3_cs_n),
.ddr3_dm (ddr3_dm),
.ddr3_dq (ddr3_dq),
.ddr3_dqs_n (ddr3_dqs_n),
.ddr3_dqs_p (ddr3_dqs_p),
.ddr3_odt (ddr3_odt),
.ddr3_ras_n (ddr3_ras_n),
.ddr3_reset_n (ddr3_reset_n),
.ddr3_we_n (ddr3_we_n),
.linear_flash_addr (linear_flash_addr),
.linear_flash_adv_ldn (linear_flash_adv_ldn),
.linear_flash_ce_n (linear_flash_ce_n),
.linear_flash_oen (linear_flash_oen),
.linear_flash_wen (linear_flash_wen),
.linear_flash_dq_io(linear_flash_dq_io),
.gpio_lcd_tri_io (gpio_lcd),
.gpio0_o (gpio_o[31:0]),
.gpio0_t (gpio_t[31:0]),
.gpio0_i (gpio_i[31:0]),
.gpio1_o (gpio_o[63:32]),
.gpio1_t (gpio_t[63:32]),
.gpio1_i (gpio_i[63:32]),
.iic_main_scl_io (iic_scl),
.iic_main_sda_io (iic_sda),
.mb_intr_06 (1'b0),
.mb_intr_07 (1'b0),
.mb_intr_08 (1'b0),
.mb_intr_14 (1'b0),
.mb_intr_15 (1'b0),
.mdio_mdc (mdio_mdc),
.mdio_mdio_io (mdio_mdio),
.mgt_clk_clk_n (mgt_clk_n),
.mgt_clk_clk_p (mgt_clk_p),
.phy_rstn (phy_rstn),
.phy_sd (1'b1),
.sgmii_rxn (sgmii_rxn),
.sgmii_rxp (sgmii_rxp),
.sgmii_txn (sgmii_txn),
.sgmii_txp (sgmii_txp),
.sys_clk_n (sys_clk_n),
.sys_clk_p (sys_clk_p),
.sys_rst (sys_rst),
.spi_clk_i (spi_clk),
.spi_clk_o (spi_clk),
.spi_csn_i (spi_csn),
.spi_csn_o (spi_csn),
.spi_sdi_i (spi_miso),
.spi_sdo_i (spi_mosi),
.spi_sdo_o (spi_mosi),
.rx_clk_in_n (rx_clk_in_n),
.rx_clk_in_p (rx_clk_in_p),
.rx_data_in_n (rx_data_in_n),
.rx_data_in_p (rx_data_in_p),
.rx_frame_in_n (rx_frame_in_n),
.rx_frame_in_p (rx_frame_in_p),
.tx_clk_out_n (tx_clk_out_n),
.tx_clk_out_p (tx_clk_out_p),
.tx_data_out_n (tx_data_out_n),
.tx_data_out_p (tx_data_out_p),
.tx_frame_out_n (tx_frame_out_n),
.tx_frame_out_p (tx_frame_out_p),
.uart_sin (uart_sin),
.uart_sout (uart_sout),
.enable (enable_s),
.txnrx (txnrx_s),
.tdd_enable (tdd_enable_s));
endmodule
// ***************************************************************************
// ***************************************************************************
|
//==================================================================================================
// Filename : tb_core.v
// Created On : 2014-10-02 18:20:53
// Last Modified : 2015-05-31 21:26:13
// Revision : 0.1
// Author : Angel Terrones
// Company : Universidad Simón Bolívar
// Email : [email protected]
//
// Description : Core testbench.
//==================================================================================================
`include "musb_defines.v"
`timescale 1ns / 100ps
`define cycle 20
`define MEM_ADDR_WIDTH 12
module tb_core;
//--------------------------------------------------------------------------
// wires
//--------------------------------------------------------------------------
wire clk_core;
wire clk_bus;
wire rst;
wire [31:0] dport_address;
wire [31:0] dport_data_i;
wire [31:0] dport_data_o;
wire dport_enable;
wire [3:0] dport_wr;
wire dport_ready;
wire dport_error;
wire [31:0] iport_address;
wire [31:0] iport_data_i;
wire iport_enable;
wire [3:0] iport_wr;
wire iport_ready;
wire iport_error;
wire halted;
//--------------------------------------------------------------------------
// Assigns
//--------------------------------------------------------------------------
assign iport_error = 1'b0; // No errors
assign dport_error = 1'b0; // No errors
//--------------------------------------------------------------------------
// MIPS CORE
//--------------------------------------------------------------------------
musb_core #(
.ENABLE_HW_MULT ( 1 ),
.ENABLE_HW_DIV ( 1 ),
.ENABLE_HW_CLO_Z ( 1 )
)
core(
// Outputs
.halted ( halted ),
.iport_address ( iport_address[31:0] ),
.iport_wr ( iport_wr[3:0] ),
.iport_enable ( iport_enable ),
.dport_address ( dport_address[31:0] ),
.dport_data_o ( dport_data_o[31:0] ),
.dport_wr ( dport_wr[3:0] ),
.dport_enable ( dport_enable ),
// Inputs
.clk ( clk_core ),
.rst_i ( rst ),
.interrupts ( 5'b0 ), // No external interrupts.
.nmi ( 1'b0 ), // No external interrupts.
.iport_data_i ( iport_data_i[31:0] ),
.iport_ready ( iport_ready ),
.dport_data_i ( dport_data_i[31:0] ),
.dport_ready ( dport_ready ),
.iport_error ( iport_error ),
.dport_error ( dport_error )
);
//--------------------------------------------------------------------------
// Instruction/Data Memory
// Port A = Instruccion
// Port B = Data
//--------------------------------------------------------------------------
memory #(
.addr_size( `MEM_ADDR_WIDTH ) // Memory size
)
memory0(
.clk ( clk_bus ),
.rst ( rst ),
.a_addr ( iport_address[2 +: `MEM_ADDR_WIDTH] ), // instruction port
.a_din ( 32'hB00B_B00B ),
.a_wr ( iport_wr[3:0] ),
.a_enable ( iport_enable ),
.a_dout ( iport_data_i[31:0] ),
.a_ready ( iport_ready ),
.b_addr ( dport_address[2 +: `MEM_ADDR_WIDTH] ), // data port
.b_din ( dport_data_o[31:0] ),
.b_wr ( dport_wr[3:0] ),
.b_enable ( dport_enable ),
.b_dout ( dport_data_i[31:0] ),
.b_ready ( dport_ready )
);
//--------------------------------------------------------------------------
// Monitor
//--------------------------------------------------------------------------
musb_monitor #(
.CORE("core")
)
monitor0(
.halt ( halted ),
.if_stall ( core.if_stall ),
.if_flush ( core.if_exception_flush ),
.id_stall ( core.id_stall ),
.id_flush ( core.id_exception_flush ),
.ex_stall ( core.ex_stall ),
.ex_flush ( core.ex_exception_flush ),
.mem_stall ( core.mem_stall ),
.mem_flush ( core.mem_exception_flush ),
.wb_stall ( core.wb_stall ),
.mem_exception_pc ( core.mem_exception_pc ),
.id_instruction ( core.id_instruction ),
.wb_gpr_wa ( core.wb_gpr_wa ),
.wb_gpr_wd ( core.wb_gpr_wd ),
.wb_gpr_we ( core.wb_gpr_we ),
.mem_address ( core.mem_alu_result ),
.mem_data ( core.mem_mem_store_data ),
.if_exception_ready ( core.musb_cpzero0.if_exception_ready ),
.id_exception_ready ( core.musb_cpzero0.id_exception_ready ),
.ex_exception_ready ( core.musb_cpzero0.ex_exception_ready ),
.mem_exception_ready ( core.musb_cpzero0.mem_exception_ready ),
.clk_core ( clk_core ),
.clk_bus ( clk_bus ),
.rst ( rst )
);
endmodule
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title : VGA Top Level
// File : vga.v
// Author : Frank Bruno
// Created : 11-Jun-2002
// RCS File : $Source:$
// Status : $Id:$
//
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
//
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
// hif - Host interface module
// crtc - CRT controller module
// attr - Attribute controller module
// memiftoplevel - memory controller module
// graph_top - Graphic controller module
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ns / 10 ps
module vga
(
input [22:0] t_haddr, // 23 bit address lines from Host
input [3:0] t_byte_en_n, // Byte enable signals
input t_mem_io_n, // 1 - Mem, 0 - IO.
input t_hrd_hwr_n, // 1 - read, 0 - write
input t_hreset_n, // reset signal coming from Host
input t_mem_clk, // memory clock
input t_svga_sel, // Valid address (MEM or IO) decoded
input t_crt_clk, // Main crt clock
input t_sense_n, // It indicates a CRT is connected.
input svga_ack, // Accepted memory access
input t_data_ready_n, // Data ready
input [31:0] t_hdata_in, // Input data from host
input [31:0] m_t_mem_data_in, // Input data from memory
input vga_en, // Signal to disable CRT and REF Req
input mem_ready, // MC is ready
output [31:0] t_hdata_out,
output [31:0] m_t_mem_data_out,
output c_t_clk_sel, // CRT clock select
output c_t_cblank_n, // composite blank to ramdac
output c_t_hsync, // HSYNC to ramdac
output c_t_vsync, // Vsync to ramdac
output h_t_ready_n, // Ready for next cycle
output [7:0] a_t_pix_data, // Pixel data to Ramdac
output [20:3] m_t_mem_addr, // Address to memory
output [7:0] m_t_mwe_n, // Byte enables to memory
output m_t_svga_req, // Request memory
output [5:0] g_t_ctl_bits,
output m_mrd_mwr_n
);
wire pre_load;
wire a_ready_n;
wire c_ready_n;
wire g_ready_n;
wire m_ready_n;
wire g_mem_ready_n;
wire h_hrd_hwr_n;
wire h_mem_io_n;
wire [22:0] h_mem_addr;
wire [15:0] h_io_addr;
wire h_io_16;
wire h_io_8;
wire h_dec_3bx;
wire h_dec_3cx;
wire h_dec_3dx;
wire h_iord;
wire h_iowr;
wire h_svga_sel;
wire h_hclk;
wire m_sr01_b0;
wire m_sr01_b2;
wire m_sr01_b3;
wire m_sr01_b4;
wire m_sr01_b5;
wire a_ar10_b0;
wire a_ar10_b5;
wire a_ar10_b6;
wire a_arx_b5;
wire a_is01_b5;
wire a_is01_b4;
wire m_dec_sr00_sr06;
wire m_dec_sr07;
wire a_ar13_b3;
wire a_ar13_b2;
wire a_ar13_b1;
wire a_ar13_b0;
wire c_cr24_rd;
wire c_cr26_rd;
wire c_9dot;
wire c_mis_3c2_b5;
wire c_misc_b0;
wire c_misc_b1;
wire c_cr0b_b5;
wire c_cr0b_b6;
wire c_cr0a_b5;
wire c_cr14_b6;
wire c_cr17_b0;
wire c_cr17_b1;
wire c_cr17_b5;
wire c_cr17_b6;
wire c_dec_3ba_or_3da;
wire c_gr_ext_en;
wire c_vert_blank;
wire c_ahde;
wire c_crt_line_end;
wire c_dclk_en;
wire c_crt_ff_read;
wire c_shift_ld;
wire c_shift_ld_pulse;
wire c_shift_clk;
wire c_pre_vde;
wire c_split_screen_pulse;
wire c_vde;
wire c_vdisp_end;
wire c_attr_de;
wire c_uln_on;
wire c_cursory;
wire [4:0] c_slc_op;
wire c_row_end;
wire c_cr0c_f13_22_hit;
wire [36:0] m_att_data;
wire m_sr04_b3;
wire g_gr05_b5;
wire g_gr05_b6;
wire h_memrd;
wire [31:0] g_graph_data_in;
wire [31:0] g_graph_data_out;
wire [3:0] g_plane_sel;
wire g_memwr;
wire g_gr06_b0;
wire g_gr05_b4;
wire m_cpu_ff_full;
wire m_sr00_b0;
wire m_sr01_b1;
wire [3:0] m_sr02_b;
wire [2:0] m_sr0x_b;
wire m_chain4;
wire m_extend_mem;
wire m_odd_even;
wire m_planar;
wire g_gr06_b1;
wire [15:0] h_io_dbus;
wire [7:0] g_int_crt22_data;
wire m_memrd_ready_n;
wire [7:0] fin_plane_sel;
wire [19:0] val_mrdwr_addr;
wire m_cpurd_state1;
wire g_cpult_state1;
wire g_lt_hwr_cmd;
wire m_crt_abort;
wire m_soft_rst_n;
wire g_cpu_data_done;
wire g_cpu_cycle_done;
wire [31:0] h_mem_dbus_in;
wire [31:0] h_mem_dbus_out;
wire cpu_rd_gnt;
wire [3:0] h_byte_en_n;
wire mem_mod_rd_en_hb;
wire mem_mod_rd_en_lb;
wire crt_mod_rd_en_hb;
wire crt_mod_rd_en_lb;
wire attr_mod_rd_en;
wire gra_mod_rd_en;
wire attr_mod_rd_en_lb;
wire attr_mod_rd_en_hb;
// point to points from the h_io_dbus
// From attribute controller
wire [7:0] a_reg_ar10;
wire [7:0] a_reg_ar11;
wire [7:0] a_reg_ar12;
wire [7:0] a_reg_ar13;
wire [7:0] a_reg_ar14;
wire [5:0] a_dport_out;
wire [7:0] a_attr_index;
wire [7:0] a_cr24_26_dbus;
wire [7:0] c_reg_ht; // Horizontal total
wire [7:0] c_reg_hde; //Horizontal Display End
wire [7:0] c_reg_hbs; //Horizontal Blanking Start
wire [7:0] c_reg_hbe; //Horizontal Blanking End
wire [7:0] c_reg_hss; //Horizontal Sync Start
wire [7:0] c_reg_hse; //Horizontal Sync End
wire [7:0] c_reg_cr06;
wire [7:0] c_reg_cr07;
wire [7:0] c_reg_cr10;
wire [7:0] c_reg_cr11;
wire [7:0] c_reg_cr12;
wire [7:0] c_reg_cr15;
wire [7:0] c_reg_cr16;
wire [7:0] c_reg_cr18;
wire [7:0] c_crtc_index; // crtc index register
wire [7:0] c_ext_index; // extension index register
wire [7:0] c_reg_ins0;
wire [7:0] c_reg_ins1;
wire [7:0] c_reg_fcr;
wire [7:0] c_reg_cr17;
wire [7:0] c_reg_cr08;
wire [7:0] c_reg_cr09;
wire [7:0] c_reg_cr0a;
wire [7:0] c_reg_cr0b;
wire [7:0] c_reg_cr14;
wire [7:0] c_reg_misc;
wire [7:0] m_index_qout;
wire [7:0] m_reg_sr0_qout;
wire [7:0] m_reg_sr1_qout;
wire [7:0] m_reg_sr2_qout;
wire [7:0] m_reg_sr3_qout;
wire [7:0] m_reg_sr4_qout;
wire [7:0] m_reg_cr0c_qout;
wire [7:0] m_reg_cr0d_qout;
wire [7:0] m_reg_cr0e_qout;
wire [7:0] m_reg_cr0f_qout;
wire [7:0] m_reg_cr13_qout;
wire [7:0] g_reg_gr0;
wire [7:0] g_reg_gr1;
wire [7:0] g_reg_gr2;
wire [7:0] g_reg_gr3;
wire [7:0] g_reg_gr4;
wire [7:0] g_reg_gr5;
wire [7:0] g_reg_gr6;
wire [7:0] g_reg_gr7;
wire [7:0] g_reg_gr8;
wire color_256_mode; // inidcates mode 13
wire g_memrd;
wire m_cpurd_s0;
wire [10:0] vcount;
hif KH
(
.mem_mod_rd_en_hb (mem_mod_rd_en_hb),
.mem_mod_rd_en_lb (mem_mod_rd_en_lb),
.crt_mod_rd_en_hb (crt_mod_rd_en_hb),
.crt_mod_rd_en_lb (crt_mod_rd_en_lb),
.attr_mod_rd_en_lb (attr_mod_rd_en_lb),
.attr_mod_rd_en_hb (attr_mod_rd_en_hb),
.gra_mod_rd_en (gra_mod_rd_en),
.t_haddr (t_haddr),
.t_byte_en_n (t_byte_en_n),
.t_mem_io_n (t_mem_io_n),
.t_hrd_hwr_n (t_hrd_hwr_n),
.t_hreset_n (t_hreset_n),
.t_mem_clk (t_mem_clk),
.t_svga_sel (t_svga_sel),
.a_ready_n (a_ready_n),
.c_ready_n (c_ready_n),
.g_ready_n (g_ready_n),
.m_ready_n (m_ready_n),
.g_mem_ready_n (g_mem_ready_n),
.m_cpurd_state1 (m_cpurd_state1),
.g_cpult_state1 (g_cpult_state1),
.g_lt_hwr_cmd (g_lt_hwr_cmd),
.t_hdata_in (t_hdata_in),
.h_mem_dbus_in (h_mem_dbus_in),
// register inputs from the given modules
.a_reg_ar10 (a_reg_ar10),
.a_reg_ar11 (a_reg_ar11),
.a_reg_ar12 (a_reg_ar12),
.a_reg_ar13 (a_reg_ar13),
.a_reg_ar14 (a_reg_ar14),
.a_dport_out (a_dport_out),
.a_attr_index (a_attr_index),
.a_cr24_26_dbus (a_cr24_26_dbus),
.c_reg_ht (c_reg_ht), // Horizontal total
.c_reg_hde (c_reg_hde), //Horizontal Display End
.c_reg_hbs (c_reg_hbs), //Horizontal Blanking Start
.c_reg_hbe (c_reg_hbe), //Horizontal Blanking End
.c_reg_hss (c_reg_hss), //Horizontal Sync Start
.c_reg_hse (c_reg_hse), //Horizontal Sync End
.c_reg_cr06 (c_reg_cr06),
.c_reg_cr07 (c_reg_cr07),
.c_reg_cr10 (c_reg_cr10),
.c_reg_cr11 (c_reg_cr11),
.c_reg_cr12 (c_reg_cr12),
.c_reg_cr15 (c_reg_cr15),
.c_reg_cr16 (c_reg_cr16),
.c_reg_cr18 (c_reg_cr18),
.c_crtc_index (c_crtc_index),
.c_ext_index (c_ext_index),
.c_reg_ins0 (c_reg_ins0),
.c_reg_ins1 (c_reg_ins1),
.c_reg_fcr (c_reg_fcr),
.c_reg_cr17 (c_reg_cr17),
.c_reg_cr08 (c_reg_cr08),
.c_reg_cr09 (c_reg_cr09),
.c_reg_cr0a (c_reg_cr0a),
.c_reg_cr0b (c_reg_cr0b),
.c_reg_cr14 (c_reg_cr14),
.c_reg_misc (c_reg_misc),
.g_int_crt22_data (g_int_crt22_data),
.m_index_qout (m_index_qout),
.m_reg_sr0_qout (m_reg_sr0_qout),
.m_reg_sr1_qout (m_reg_sr1_qout),
.m_reg_sr2_qout (m_reg_sr2_qout),
.m_reg_sr3_qout (m_reg_sr3_qout),
.m_reg_sr4_qout (m_reg_sr4_qout),
.m_reg_cr0c_qout (m_reg_cr0c_qout),
.m_reg_cr0d_qout (m_reg_cr0d_qout),
.m_reg_cr0e_qout (m_reg_cr0e_qout),
.m_reg_cr0f_qout (m_reg_cr0f_qout),
.m_reg_cr13_qout (m_reg_cr13_qout),
.g_reg_gr0 (g_reg_gr0),
.g_reg_gr1 (g_reg_gr1),
.g_reg_gr2 (g_reg_gr2),
.g_reg_gr3 (g_reg_gr3),
.g_reg_gr4 (g_reg_gr4),
.g_reg_gr5 (g_reg_gr5),
.g_reg_gr6 (g_reg_gr6),
.g_reg_gr7 (g_reg_gr7),
.g_reg_gr8 (g_reg_gr8),
.h_io_dbus (h_io_dbus),
.t_hdata_out (t_hdata_out),
.h_mem_dbus_out (h_mem_dbus_out),
.h_hrd_hwr_n (h_hrd_hwr_n),
.h_mem_io_n (h_mem_io_n),
.h_t_ready_n (h_t_ready_n),
.h_mem_addr (h_mem_addr),
.h_io_addr (h_io_addr),
.h_io_16 (h_io_16),
.h_io_8 (h_io_8),
.h_dec_3bx (h_dec_3bx),
.h_dec_3cx (h_dec_3cx),
.h_dec_3dx (h_dec_3dx),
.h_iord (h_iord),
.h_iowr (h_iowr),
.h_byte_en_n (h_byte_en_n),
.h_svga_sel (h_svga_sel)
);
crtc KC
(
.h_io_addr (h_io_addr),
.h_dec_3bx (h_dec_3bx),
.h_dec_3cx (h_dec_3cx),
.h_dec_3dx (h_dec_3dx),
.h_io_16 (h_io_16),
.h_io_8 (h_io_8),
.h_reset_n (t_hreset_n),
.h_iord (h_iord),
.h_iowr (h_iowr),
.h_hclk (t_mem_clk),
.t_crt_clk (t_crt_clk),
.m_sr01_b0 (m_sr01_b0),
.m_sr01_b2 (m_sr01_b2),
.m_sr01_b3 (m_sr01_b3),
.m_sr01_b4 (m_sr01_b4),
.m_sr01_b5 (m_sr01_b5),
.a_ar10_b0 (a_ar10_b0),
.a_ar10_b5 (a_ar10_b5),
.a_ar10_b6 (a_ar10_b6),
.t_sense_n (t_sense_n),
.a_arx_b5 (a_arx_b5),
.a_is01_b5 (a_is01_b5),
.a_is01_b4 (a_is01_b4),
.m_dec_sr00_sr06 (m_dec_sr00_sr06),
.m_dec_sr07 (m_dec_sr07),
.m_soft_rst_n (m_soft_rst_n),
.a_ar13_b3 (a_ar13_b3),
.a_ar13_b2 (a_ar13_b2),
.a_ar13_b1 (a_ar13_b1),
.a_ar13_b0 (a_ar13_b0),
.h_io_dbus (h_io_dbus), // now only the input
.vga_en (vga_en),
.c_reg_ht (c_reg_ht), // Horizontal total
.c_reg_hde (c_reg_hde), //Horizontal Display End
.c_reg_hbs (c_reg_hbs), //Horizontal Blanking Start
.c_reg_hbe (c_reg_hbe), //Horizontal Blanking End
.c_reg_hss (c_reg_hss), //Horizontal Sync Start
.c_reg_hse (c_reg_hse), //Horizontal Sync End
.c_reg_cr06 (c_reg_cr06),
.c_reg_cr07 (c_reg_cr07),
.c_reg_cr10 (c_reg_cr10),
.c_reg_cr11 (c_reg_cr11),
.c_reg_cr12 (c_reg_cr12),
.c_reg_cr15 (c_reg_cr15),
.c_reg_cr16 (c_reg_cr16),
.c_reg_cr18 (c_reg_cr18),
.c_crtc_index (c_crtc_index),
.c_ext_index (c_ext_index),
.c_reg_ins0 (c_reg_ins0),
.c_reg_ins1 (c_reg_ins1),
.c_reg_fcr (c_reg_fcr),
.c_reg_cr17 (c_reg_cr17),
.c_reg_cr08 (c_reg_cr08),
.c_reg_cr09 (c_reg_cr09),
.c_reg_cr0a (c_reg_cr0a),
.c_reg_cr0b (c_reg_cr0b),
.c_reg_cr14 (c_reg_cr14),
.c_reg_misc (c_reg_misc),
.c_cr24_rd (c_cr24_rd),
.c_cr26_rd (c_cr26_rd),
.c_9dot (c_9dot),
.c_mis_3c2_b5 (c_mis_3c2_b5),
.c_misc_b0 (c_misc_b0),
.c_cr0b_b5 (c_cr0b_b5),
.c_cr0b_b6 (c_cr0b_b6),
.c_cr0a_b5 (c_cr0a_b5),
.c_cr14_b6 (c_cr14_b6),
.c_cr17_b0 (c_cr17_b0),
.c_cr17_b1 (c_cr17_b1),
.c_cr17_b5 (c_cr17_b5),
.c_cr17_b6 (c_cr17_b6),
.c_gr_ext_en (c_gr_ext_en),
.c_ext_index_b (),
.c_dec_3ba_or_3da (c_dec_3ba_or_3da),
.c_vert_blank (c_vert_blank),
.c_ready_n (c_ready_n),
.c_t_clk_sel (c_t_clk_sel),
.c_ahde (c_ahde),
.c_t_cblank_n (c_t_cblank_n),
.c_crt_line_end (c_crt_line_end),
.c_dclk_en (c_dclk_en),
.c_crt_ff_read (c_crt_ff_read),
.c_shift_ld (c_shift_ld),
.c_shift_ld_pulse (c_shift_ld_pulse),
.c_t_hsync (c_t_hsync),
.c_shift_clk (c_shift_clk),
.c_pre_vde (c_pre_vde),
.c_split_screen_pulse (c_split_screen_pulse),
.c_vde (c_vde),
.c_vdisp_end (c_vdisp_end),
.c_t_vsync (c_t_vsync),
.c_attr_de (c_attr_de),
.c_uln_on (c_uln_on),
.c_cursory (c_cursory),
.c_slc_op (c_slc_op),
.c_row_end (c_row_end),
.c_cr0c_f13_22_hit (c_cr0c_f13_22_hit),
.c_misc_b1 (c_misc_b1),
.crt_mod_rd_en_hb (crt_mod_rd_en_hb),
.crt_mod_rd_en_lb (crt_mod_rd_en_lb),
.pre_load (pre_load),
.vcount (vcount)
);
attr KA
(
.h_reset_n (t_hreset_n),
.h_io_addr (h_io_addr),
.h_dec_3cx (h_dec_3cx),
.h_iowr (h_iowr),
.h_iord (h_iord),
.h_hclk (t_mem_clk),
.c_shift_ld (c_shift_ld),
.c_shift_ld_pulse (c_shift_ld_pulse),
.c_shift_clk (c_shift_clk),
.c_dclk_en (c_dclk_en),
.c_9dot (c_9dot),
.m_att_data (m_att_data),
.m_sr04_b3 (m_sr04_b3),
.c_cr24_rd (c_cr24_rd),
.c_cr26_rd (c_cr26_rd),
.c_attr_de (c_attr_de),
.c_t_vsync (c_t_vsync),
.c_dec_3ba_or_3da (c_dec_3ba_or_3da),
.c_cr0b_b5 (c_cr0b_b5),
.c_cr0b_b6 (c_cr0b_b6),
.c_cr0a_b5 (c_cr0a_b5),
.g_gr05_b5 (g_gr05_b5),
.g_gr05_b6 (g_gr05_b6),
.t_crt_clk (t_crt_clk),
.h_io_16 (h_io_16),
.h_io_dbus (h_io_dbus),
.pre_load (pre_load),
.reg_ar10 (a_reg_ar10),
.reg_ar11 (a_reg_ar11),
.reg_ar12 (a_reg_ar12),
.reg_ar13 (a_reg_ar13),
.reg_ar14 (a_reg_ar14),
.dport_out (a_dport_out),
.attr_index (a_attr_index),
.cr24_26_dbus (a_cr24_26_dbus),
.a_ready_n (a_ready_n),
.a_ar10_b6 (a_ar10_b6),
.a_ar10_b5 (a_ar10_b5),
.a_ar10_b0 (a_ar10_b0),
.a_ar13_b3 (a_ar13_b3),
.a_ar13_b2 (a_ar13_b2),
.a_ar13_b1 (a_ar13_b1),
.a_ar13_b0 (a_ar13_b0),
.a_arx_b5 (a_arx_b5),
.a_is01_b5 (a_is01_b5),
.a_is01_b4 (a_is01_b4),
.a_t_pix_data (a_t_pix_data),
.attr_mod_rd_en_lb (attr_mod_rd_en_lb),
.attr_mod_rd_en_hb (attr_mod_rd_en_hb),
.color_256_mode (color_256_mode)
);
memif_toplevel KM
(
.t_data_ready_n (t_data_ready_n),
.t_mem_clk (t_mem_clk),
.t_crt_clk (t_crt_clk),
.svga_ack (svga_ack),
.c_misc_b1 (c_misc_b1),
.c_split_screen_pulse (c_split_screen_pulse),
.c_vde (c_vde),
.c_pre_vde (c_pre_vde),
.c_row_end (c_row_end),
.c_cr17_b0 (c_cr17_b0),
.c_cr17_b1 (c_cr17_b1),
.c_cr17_b5 (c_cr17_b5),
.c_cr17_b6 (c_cr17_b6),
.c_cr14_b6 (c_cr14_b6),
.c_slc_op (c_slc_op),
.c_crt_line_end (c_crt_line_end),
.c_dclk_en (c_dclk_en),
.c_vdisp_end (c_vdisp_end),
.c_crt_ff_read (c_crt_ff_read),
.c_vert_blank (c_vert_blank),
.c_cursory (c_cursory),
.c_uln_on (c_uln_on),
.c_cr0c_f13_22_hit (c_cr0c_f13_22_hit),
.g_memrd (g_memrd),
.h_reset_n (t_hreset_n),
.h_iord (h_iord),
.h_iowr (h_iowr),
.h_io_16 (h_io_16),
.h_io_addr (h_io_addr),
.h_svga_sel (h_svga_sel),
.val_mrdwr_addr (val_mrdwr_addr),
.fin_plane_sel (fin_plane_sel),
.g_graph_data_in (g_graph_data_in),
.g_graph_data_out (g_graph_data_out),
.g_plane_sel (g_plane_sel),
.g_memwr (g_memwr),
.g_gr06_b0 (g_gr06_b0),
.g_gr05_b4 (g_gr05_b4),
.g_cpu_cycle_done (g_cpu_cycle_done),
.g_cpu_data_done (g_cpu_data_done),
.h_io_dbus (h_io_dbus),
.color_mode (c_misc_b0),
.c_crtc_index (c_crtc_index[5:0]),
.c_ext_index (c_ext_index),
.c_hde (c_reg_hde),
.color_256_mode (color_256_mode),
.vga_en (vga_en),
.mem_ready (mem_ready),
.memif_index_qout (m_index_qout),
.reg_sr0_qout (m_reg_sr0_qout),
.reg_sr1_qout (m_reg_sr1_qout),
.reg_sr2_qout (m_reg_sr2_qout),
.reg_sr3_qout (m_reg_sr3_qout),
.reg_sr4_qout (m_reg_sr4_qout),
.reg_cr0c_qout (m_reg_cr0c_qout), // screen start address high
.reg_cr0d_qout (m_reg_cr0d_qout),
.reg_cr0e_qout (m_reg_cr0e_qout),
.reg_cr0f_qout (m_reg_cr0f_qout),
.reg_cr13_qout (m_reg_cr13_qout),
.m_t_mem_addr (m_t_mem_addr),
.m_t_mem_data_in (m_t_mem_data_in),
.m_t_mem_data_out (m_t_mem_data_out),
.m_t_mwe_n (m_t_mwe_n),
.m_t_svga_req (m_t_svga_req),
.m_att_data (m_att_data),
.m_cpu_ff_full (m_cpu_ff_full),
.m_sr00_b0 (m_sr00_b0),
.m_sr01_b1 (m_sr01_b1),
.m_sr02_b (m_sr02_b),
.m_sr04_b3 (m_sr04_b3),
.m_sr01_b4 (m_sr01_b4),
.m_sr01_b3 (m_sr01_b3),
.m_sr01_b2 (m_sr01_b2),
.m_sr01_b0 (m_sr01_b0),
.m_sr01_b5 (m_sr01_b5),
.m_chain4 (m_chain4),
.m_extend_mem (m_extend_mem),
.m_odd_even (m_odd_even),
.m_planar (m_planar),
.m_ready_n (m_ready_n),
.m_dec_sr00_sr06 (m_dec_sr00_sr06),
.m_dec_sr07 (m_dec_sr07),
.m_memrd_ready_n (m_memrd_ready_n),
.m_cpurd_state1 (m_cpurd_state1),
.m_mrd_mwr_n (m_mrd_mwr_n),
.m_soft_rst_n (m_soft_rst_n),
.m_cpurd_s0 (m_cpurd_s0),
.cpu_rd_gnt (cpu_rd_gnt),
.mem_mod_rd_en_hb (mem_mod_rd_en_hb),
.mem_mod_rd_en_lb (mem_mod_rd_en_lb)
);
graph_top KG
(
.t_mem_io_n (t_mem_io_n),
.t_svga_sel (t_svga_sel),
.cpu_rd_gnt (cpu_rd_gnt),
.h_reset_n (t_hreset_n),
.t_mem_clk (t_mem_clk),
.t_data_ready_n (t_data_ready_n),
.svga_ack (svga_ack),
.h_svga_sel (h_svga_sel),
.h_hrd_hwr_n (h_hrd_hwr_n),
.h_mem_io_n (h_mem_io_n),
.h_byte_en_n (h_byte_en_n),
.m_cpurd_s0 (m_cpurd_s0),
.m_cpu_ff_full (m_cpu_ff_full),
.m_chain4 (m_chain4),
.m_odd_even (m_odd_even),
.m_planar (m_planar),
.m_memrd_ready_n (m_memrd_ready_n),
.h_mem_addr (h_mem_addr),
.c_mis_3c2_b5 (c_mis_3c2_b5),
.h_iord (h_iord),
.h_iowr (h_iowr),
.h_io_16 (h_io_16),
.h_dec_3cx (h_dec_3cx),
.h_io_addr (h_io_addr),
.h_io_dbus (h_io_dbus[15:8]),
.c_misc_b0 (c_misc_b0),
.c_misc_b1 (c_misc_b1),
.c_gr_ext_en (c_gr_ext_en),
.c_ext_index (c_ext_index),
.m_sr04_b3 (m_sr04_b3),
.m_ready_n (m_ready_n),
.m_sr02_b (m_sr02_b),
// outputs
.g_reg_gr0 (g_reg_gr0),
.g_reg_gr1 (g_reg_gr1),
.g_reg_gr2 (g_reg_gr2),
.g_reg_gr3 (g_reg_gr3),
.g_reg_gr4 (g_reg_gr4),
.g_reg_gr5 (g_reg_gr5),
.g_reg_gr6 (g_reg_gr6),
.g_reg_gr7 (g_reg_gr7),
.g_reg_gr8 (g_reg_gr8),
.g_mem_ready_n (g_mem_ready_n),
.g_memwr (g_memwr),
.g_gr05_b5 (g_gr05_b5),
.g_gr05_b6 (g_gr05_b6),
.g_gr05_b4 (g_gr05_b4),
.g_gr06_b0 (g_gr06_b0),
.g_gr06_b1 (g_gr06_b1),
.g_ready_n (g_ready_n),
.g_t_ctl_bit (g_t_ctl_bits),
.h_mem_dbus_in (h_mem_dbus_in),
.h_mem_dbus_out (h_mem_dbus_out),
.g_graph_data_in (g_graph_data_in),
.g_graph_data_out (g_graph_data_out),
.g_int_crt22_data (g_int_crt22_data),
.g_memrd (g_memrd),
.val_mrdwr_addr (val_mrdwr_addr),
.fin_plane_sel (fin_plane_sel),
.g_lt_hwr_cmd (g_lt_hwr_cmd),
.g_cpult_state1 (g_cpult_state1),
.g_cpu_data_done (g_cpu_data_done),
.g_cpu_cycle_done (g_cpu_cycle_done),
.gra_mod_rd_en (gra_mod_rd_en)
);
endmodule
|
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: nuny_new2.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.1 Build 166 11/26/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module nuny_new2 (
address,
clock,
q);
input [14:0] address;
input clock;
output [11:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [11:0] sub_wire0;
wire [11:0] q = sub_wire0[11:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({12{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "../sprites-new/nuny_new2.mif",
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 32768,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.widthad_a = 15,
altsyncram_component.width_a = 12,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "../sprites-new/nuny_new2.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "32768"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "15"
// Retrieval info: PRIVATE: WidthData NUMERIC "12"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "../sprites-new/nuny_new2.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "32768"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "15"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 15 0 INPUT NODEFVAL "address[14..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
// Retrieval info: CONNECT: @address_a 0 0 15 0 address 0 0 15 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 12 0 @q_a 0 0 12 0
// Retrieval info: GEN_FILE: TYPE_NORMAL nuny_new2.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL nuny_new2.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL nuny_new2.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL nuny_new2.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL nuny_new2_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL nuny_new2_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__EINVN_SYMBOL_V
`define SKY130_FD_SC_HD__EINVN_SYMBOL_V
/**
* einvn: Tri-state inverter, negative enable.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__einvn (
//# {{data|Data Signals}}
input A ,
output Z ,
//# {{control|Control Signals}}
input TE_B
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__EINVN_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A222OI_PP_SYMBOL_V
`define SKY130_FD_SC_MS__A222OI_PP_SYMBOL_V
/**
* a222oi: 2-input AND into all inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | (C1 & C2))
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__a222oi (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
input B2 ,
input C1 ,
input C2 ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__A222OI_PP_SYMBOL_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 06.10.2017 09:04:37
// Design Name:
// Module Name: bankregister_tb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module bankregister_tb;
reg [5:0] RegLe1;
reg [5:0] RegLe2;
reg [5:0] RegEscr;
reg EscrReg;
reg clk;
reg [31:0] datain;
wire [31:0] data1;
wire [31:0] data2;
reg reset;
bankregister uut(
.RegLe1(RegLe1),
.RegLe2(RegLe2),
.RegEscr(RegEscr),
.EscrReg(EscrReg),
.clk(clk),
.datain(datain),
.data1(data1),
.data2(data2),
.reset(reset)
);
always
begin
clk = 1'b1;
#50;
clk = 1'b0;
#50;
end
initial begin
reset = 1'b1;
#100;
reset = 1'b0;
RegLe1 = 6'b000000;
RegLe2 = 6'b000001;
RegEscr = 6'b000000;
EscrReg = 1'b0;
datain = 32'b00000000_00000000_00000000_00000000;
#100;
RegLe1 = 6'b000000;
RegLe2 = 6'b000001;
RegEscr = 6'b000010;
EscrReg = 1'b1;
datain = 32'b00000000_00000000_00000000_10000101;
#100;
RegLe1 = 6'b000010;
RegLe2 = 6'b000001;
RegEscr = 6'b000000;
EscrReg = 1'b0;
datain = 32'b00000000_00000000_00000000_00000001;
#100;
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 18:33:23 06/15/2014
// Design Name:
// Module Name: bin_to_decimal
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module bin_to_decimal(
input [15:0] B,
output reg [19:0] bcdout
);
reg [35:0] z;
integer i;
always @(*)
begin
for(i = 0; i <= 35; i = i+1)
z[i] = 0;
z[18:3] = B; // shift b 3 places left
//for(i = 0; i <= 12; i = i+1)
repeat(13)
begin
if(z[19:16] > 4)
z[19:16] = z[19:16] + 3;
if(z[23:20] > 4)
z[23:20] = z[23:20] + 3;
if(z[27:24] > 4)
z[27:24] = z[27:24] + 3;
if(z[31:28] > 4)
z[31:28] = z[31:28] + 3;
if(z[35:32] > 4)
z[35:32] = z[35:32] + 3;
z[35:1] = z[34:0];
//z[34:2] = z[33:1];
end
bcdout = z[35:16];//20 bits
end
endmodule
|
`timescale 1ns / 1ps
module ball(
input [9:0] paddle_x,
//input [9:0] paddle_y,
input reset,
input start,
input clk,
input clk_50mh,
output [9:0] x_out,
output [9:0] y_out,
output erase_enable,
output [5:0] e_pos,
output reg [2:0] play_sound1,
//output reg play_sound2,
output reg [1:0] active_data
);
parameter
SCREEN_W = 640,
SCREEN_H = 480,
BALL_SIZE = 7,
BLOCK_SPACING_X = 10'd40,
BLOCK_SPACING_Y = 10'd20,
FIRST_ROW_Y = 10'd40,
SECOND_ROW_Y = 10'd90,
THIRD_ROW_Y = 10'd140,
FOURTH_ROW_Y = 10'd190,
FIFTH_ROW_Y = 10'd240,
BLOCK_WIDTH = 10'd80,
BLOCK_HEIGHT = 10'd30;
reg [9:0] ball_x;
reg [9:0] ball_y;
reg signed [9:0] ball_dx;
reg signed [9:0] ball_dy;
assign x_out = ball_x;
assign y_out = ball_y;
reg erase_e;
reg [5:0] erase_pos;
reg [5:0] address;
reg win;
//reg p_sound //assign play_sound1 = p_sound;
reg [1:0] active [24:0];
reg [9:0] temp1;
reg [9:0] temp2;
reg [5:0] i;
reg start_movement;
//reg [5:0] j;
assign e_pos = erase_pos;
assign erase_enable = erase_e;
always @ (posedge clk_50mh) begin
end
always @ (posedge clk) begin
erase_e = 0;
if(start)
start_movement = 1;
if(!start_movement)begin
ball_x = paddle_x + BALL_SIZE + 10'd40;
end
if(start_movement)begin
if((ball_x) <= 0 || ball_x >= SCREEN_W - BALL_SIZE) //screen boundaries check
begin
ball_dx = ball_dx * -1;
end
if(ball_y <= 1) //screen boundaries check
begin
play_sound1 = 3'b001;
ball_dy = ball_dy * -1;
//erase_e = 1;
end
if(ball_y > SCREEN_H - BALL_SIZE) //screen boundaries check
begin
play_sound1 = 3'b100;
ball_dy = 0;
//erase_e = 1;
end
address = address + 10'd1;
if(address >= 10'd10)
address = 10'd0;
/*if (ball_y >= FIFTH_ROW_Y)
address = 10'd19;
else if (ball_y >= FOURTH_ROW_Y && (address > 19))
address = 10'd14;
else if (ball_y >= THIRD_ROW_Y && (address > 14))
address = 10'd9;
else if (ball_y >= SECOND_ROW_Y && (address > 9))
address = 10'd5;
else if (ball_y >= 0 &&( (address > 4)))
address = 10'd0;*/
if (address<5) begin
temp1 = FIRST_ROW_Y;
temp2 = BLOCK_SPACING_X + (BLOCK_WIDTH + BLOCK_SPACING_X) *address;
end
else if (address < 10) begin
temp1 = SECOND_ROW_Y;
temp2 = BLOCK_SPACING_X + (BLOCK_WIDTH + BLOCK_SPACING_X) *(address-5);
end
/*else if (address < 15) begin
temp1 = THIRD_ROW_Y;
temp2 = BLOCK_SPACING_X + (BLOCK_WIDTH + BLOCK_SPACING_X) *(address-10);
end
else if (address < 20) begin
temp1 = FOURTH_ROW_Y;
temp2 = BLOCK_SPACING_X + (BLOCK_WIDTH + BLOCK_SPACING_X) *(address-15);
end
else if (address < 25) begin
temp1 = FIFTH_ROW_Y;
temp2 = BLOCK_SPACING_X + (BLOCK_WIDTH + BLOCK_SPACING_X) *(address-20);
end*/
if(active[address] < 3) begin
if(
(ball_y >= temp1 && ball_y <= (temp1 + BLOCK_HEIGHT) ) &&
(( (ball_x + BALL_SIZE) >= (temp2) && (ball_x - BALL_SIZE) <= temp2 )
||
( (ball_x + BALL_SIZE) >= (temp2 + BLOCK_WIDTH) && (ball_x - BALL_SIZE) <= (temp2 + BLOCK_WIDTH) )
)
) begin
erase_e = 1;
erase_pos = address;
ball_dx = ball_dx * -1;
active[address] = active[address] + 1;
play_sound1 = active[address];
active_data = active[address];
end
else if ( (ball_x >= temp2 && ball_x <= (temp2 + BLOCK_WIDTH)) &&
(( (ball_y + BALL_SIZE) >= (temp1) && (ball_y - BALL_SIZE) <= temp1 ) ||
( (ball_y + BALL_SIZE) >= (temp1 + BLOCK_HEIGHT) && (ball_y - BALL_SIZE) <= (temp1 + BLOCK_HEIGHT) )
))
begin
erase_e = 1;
erase_pos = address;
ball_dy = ball_dy * -1;
active[address] = active[address] + 1;
play_sound1 = active[address];
active_data = active[address];
end
end
if (address<5) begin
temp1 = THIRD_ROW_Y;
temp2 = BLOCK_SPACING_X + (BLOCK_WIDTH + BLOCK_SPACING_X) *(address);
end
else if (address < 10) begin
temp1 = FOURTH_ROW_Y;
temp2 = BLOCK_SPACING_X + (BLOCK_WIDTH + BLOCK_SPACING_X) *(address-5);
end
if(active[address + 10'd10] < 3) begin
if(
(ball_y >= temp1 && ball_y <= (temp1 + BLOCK_HEIGHT) ) &&
(( (ball_x + BALL_SIZE) >= (temp2) && (ball_x - BALL_SIZE) <= temp2 )
||
( (ball_x + BALL_SIZE) >= (temp2 + BLOCK_WIDTH) && (ball_x - BALL_SIZE) <= (temp2 + BLOCK_WIDTH) )
)
) begin
erase_e = 1;
erase_pos = address + 10'd10;
ball_dx = ball_dx * -1;
active[address + 10'd10] = active[address + 10'd10] + 1;
play_sound1 = active[address + 10'd10];
active_data = active[address + 10'd10];
end
else if ( (ball_x >= temp2 && ball_x <= (temp2 + BLOCK_WIDTH)) &&
(( (ball_y + BALL_SIZE) >= (temp1) && (ball_y - BALL_SIZE) <= temp1 ) ||
( (ball_y + BALL_SIZE) >= (temp1 + BLOCK_HEIGHT) && (ball_y - BALL_SIZE) <= (temp1 + BLOCK_HEIGHT) )
))
begin
erase_e = 1;
erase_pos = address + 10'd10;
ball_dy = ball_dy * -1;
active[address + 10'd10] = active[address + 10'd10] + 1;
play_sound1 = active[address + 10'd10];
active_data = active[address + 10'd10];
end
end
win = 1;
for (i = 0; i < 20; i = i + 1) begin
if (active[i] < 3)
win = 0;
end
//p_sound = erase_e;
//play_sound2 = 0;
if( ball_dy > 0 && (ball_x > paddle_x && ball_x < (paddle_x + 100)) && ( ( (ball_y + BALL_SIZE) >= 10'd439 && (ball_y - BALL_SIZE) < 10'd440) ) ) //paddle collision
begin
ball_dy = ball_dy * -1;
play_sound1 = 3'b100;
if ((ball_x < paddle_x + 25 || ball_x > paddle_x + 75) && (ball_dx == 1 || ball_dx == -1)) begin
ball_dx = ball_dx * 2;
end
else if (ball_dx == 2) begin
ball_dx = 1;
end
else if (ball_dx == -2) begin
ball_dx = -1;
end
end
if (win) begin
ball_dx = 10'd0;
ball_dy = 10'd0;
end
ball_x = ball_x + ball_dx;
ball_y = ball_y + ball_dy;
end
if(reset)begin
ball_x = 10'd270;
ball_y = 10'd440 - BALL_SIZE;
ball_dx = -10'd1;
ball_dy = -10'd1;
start_movement = 0;
for (i = 0; i < 20; i = i + 1) begin
active[i] = 0;
end
end
end
endmodule
|
//
// Generated by Bluespec Compiler, version 2021.07 (build 4cac6eb)
//
//
// Ports:
// Name I/O size props
// RDY_server_reset_request_put O 1 reg
// RDY_server_reset_response_get O 1
// read_rs1 O 64
// read_rs1_port2 O 64
// read_rs2 O 64
// CLK I 1 clock
// RST_N I 1 reset
// read_rs1_rs1 I 5
// read_rs1_port2_rs1 I 5
// read_rs2_rs2 I 5
// write_rd_rd I 5
// write_rd_rd_val I 64 reg
// EN_server_reset_request_put I 1
// EN_server_reset_response_get I 1
// EN_write_rd I 1
//
// Combinational paths from inputs to outputs:
// read_rs1_rs1 -> read_rs1
// read_rs1_port2_rs1 -> read_rs1_port2
// read_rs2_rs2 -> read_rs2
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkGPR_RegFile(CLK,
RST_N,
EN_server_reset_request_put,
RDY_server_reset_request_put,
EN_server_reset_response_get,
RDY_server_reset_response_get,
read_rs1_rs1,
read_rs1,
read_rs1_port2_rs1,
read_rs1_port2,
read_rs2_rs2,
read_rs2,
write_rd_rd,
write_rd_rd_val,
EN_write_rd);
input CLK;
input RST_N;
// action method server_reset_request_put
input EN_server_reset_request_put;
output RDY_server_reset_request_put;
// action method server_reset_response_get
input EN_server_reset_response_get;
output RDY_server_reset_response_get;
// value method read_rs1
input [4 : 0] read_rs1_rs1;
output [63 : 0] read_rs1;
// value method read_rs1_port2
input [4 : 0] read_rs1_port2_rs1;
output [63 : 0] read_rs1_port2;
// value method read_rs2
input [4 : 0] read_rs2_rs2;
output [63 : 0] read_rs2;
// action method write_rd
input [4 : 0] write_rd_rd;
input [63 : 0] write_rd_rd_val;
input EN_write_rd;
// signals for module outputs
wire [63 : 0] read_rs1, read_rs1_port2, read_rs2;
wire RDY_server_reset_request_put, RDY_server_reset_response_get;
// register rg_state
reg [1 : 0] rg_state;
reg [1 : 0] rg_state$D_IN;
wire rg_state$EN;
// ports of submodule f_reset_rsps
wire f_reset_rsps$CLR,
f_reset_rsps$DEQ,
f_reset_rsps$EMPTY_N,
f_reset_rsps$ENQ,
f_reset_rsps$FULL_N;
// ports of submodule regfile
wire [63 : 0] regfile$D_IN,
regfile$D_OUT_1,
regfile$D_OUT_2,
regfile$D_OUT_3;
wire [4 : 0] regfile$ADDR_1,
regfile$ADDR_2,
regfile$ADDR_3,
regfile$ADDR_4,
regfile$ADDR_5,
regfile$ADDR_IN;
wire regfile$WE;
// rule scheduling signals
wire CAN_FIRE_RL_rl_reset_loop,
CAN_FIRE_RL_rl_reset_start,
CAN_FIRE_server_reset_request_put,
CAN_FIRE_server_reset_response_get,
CAN_FIRE_write_rd,
WILL_FIRE_RL_rl_reset_loop,
WILL_FIRE_RL_rl_reset_start,
WILL_FIRE_server_reset_request_put,
WILL_FIRE_server_reset_response_get,
WILL_FIRE_write_rd;
// action method server_reset_request_put
assign RDY_server_reset_request_put = f_reset_rsps$FULL_N ;
assign CAN_FIRE_server_reset_request_put = f_reset_rsps$FULL_N ;
assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ;
// action method server_reset_response_get
assign RDY_server_reset_response_get =
rg_state == 2'd2 && f_reset_rsps$EMPTY_N ;
assign CAN_FIRE_server_reset_response_get =
rg_state == 2'd2 && f_reset_rsps$EMPTY_N ;
assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ;
// value method read_rs1
assign read_rs1 = (read_rs1_rs1 == 5'd0) ? 64'd0 : regfile$D_OUT_3 ;
// value method read_rs1_port2
assign read_rs1_port2 =
(read_rs1_port2_rs1 == 5'd0) ? 64'd0 : regfile$D_OUT_2 ;
// value method read_rs2
assign read_rs2 = (read_rs2_rs2 == 5'd0) ? 64'd0 : regfile$D_OUT_1 ;
// action method write_rd
assign CAN_FIRE_write_rd = 1'd1 ;
assign WILL_FIRE_write_rd = EN_write_rd ;
// submodule f_reset_rsps
FIFO20 #(.guarded(1'd1)) f_reset_rsps(.RST(RST_N),
.CLK(CLK),
.ENQ(f_reset_rsps$ENQ),
.DEQ(f_reset_rsps$DEQ),
.CLR(f_reset_rsps$CLR),
.FULL_N(f_reset_rsps$FULL_N),
.EMPTY_N(f_reset_rsps$EMPTY_N));
// submodule regfile
RegFile #(.addr_width(32'd5),
.data_width(32'd64),
.lo(5'h0),
.hi(5'd31)) regfile(.CLK(CLK),
.ADDR_1(regfile$ADDR_1),
.ADDR_2(regfile$ADDR_2),
.ADDR_3(regfile$ADDR_3),
.ADDR_4(regfile$ADDR_4),
.ADDR_5(regfile$ADDR_5),
.ADDR_IN(regfile$ADDR_IN),
.D_IN(regfile$D_IN),
.WE(regfile$WE),
.D_OUT_1(regfile$D_OUT_1),
.D_OUT_2(regfile$D_OUT_2),
.D_OUT_3(regfile$D_OUT_3),
.D_OUT_4(),
.D_OUT_5());
// rule RL_rl_reset_start
assign CAN_FIRE_RL_rl_reset_start = rg_state == 2'd0 ;
assign WILL_FIRE_RL_rl_reset_start = rg_state == 2'd0 ;
// rule RL_rl_reset_loop
assign CAN_FIRE_RL_rl_reset_loop = rg_state == 2'd1 ;
assign WILL_FIRE_RL_rl_reset_loop = rg_state == 2'd1 ;
// register rg_state
always@(EN_server_reset_request_put or
WILL_FIRE_RL_rl_reset_loop or WILL_FIRE_RL_rl_reset_start)
case (1'b1)
EN_server_reset_request_put: rg_state$D_IN = 2'd0;
WILL_FIRE_RL_rl_reset_loop: rg_state$D_IN = 2'd2;
WILL_FIRE_RL_rl_reset_start: rg_state$D_IN = 2'd1;
default: rg_state$D_IN = 2'b10 /* unspecified value */ ;
endcase
assign rg_state$EN =
EN_server_reset_request_put || WILL_FIRE_RL_rl_reset_start ||
WILL_FIRE_RL_rl_reset_loop ;
// submodule f_reset_rsps
assign f_reset_rsps$ENQ = EN_server_reset_request_put ;
assign f_reset_rsps$DEQ = EN_server_reset_response_get ;
assign f_reset_rsps$CLR = 1'b0 ;
// submodule regfile
assign regfile$ADDR_1 = read_rs2_rs2 ;
assign regfile$ADDR_2 = read_rs1_port2_rs1 ;
assign regfile$ADDR_3 = read_rs1_rs1 ;
assign regfile$ADDR_4 = 5'h0 ;
assign regfile$ADDR_5 = 5'h0 ;
assign regfile$ADDR_IN = write_rd_rd ;
assign regfile$D_IN = write_rd_rd_val ;
assign regfile$WE = EN_write_rd && write_rd_rd != 5'd0 ;
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
rg_state <= `BSV_ASSIGNMENT_DELAY 2'd0;
end
else
begin
if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN;
end
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
rg_state = 2'h2;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
endmodule // mkGPR_RegFile
|
// megafunction wizard: %LPM_FIFO+%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: fifo_144x128.v
// Megafunction Name(s):
// scfifo
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 5.1 Build 176 10/26/2005 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2005 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module fifo_144x128 (
aclr,
clock,
data,
rdreq,
wrreq,
empty,
full,
q,
usedw);
input aclr;
input clock;
input [143:0] data;
input rdreq;
input wrreq;
output empty;
output full;
output [143:0] q;
output [6:0] usedw;
wire [6:0] sub_wire0;
wire sub_wire1;
wire [143:0] sub_wire2;
wire sub_wire3;
wire [6:0] usedw = sub_wire0[6:0];
wire empty = sub_wire1;
wire [143:0] q = sub_wire2[143:0];
wire full = sub_wire3;
scfifo scfifo_component (
.rdreq (rdreq),
.aclr (aclr),
.clock (clock),
.wrreq (wrreq),
.data (data),
.usedw (sub_wire0),
.empty (sub_wire1),
.q (sub_wire2),
.full (sub_wire3)
// synopsys translate_off
,
.almost_empty (),
.sclr (),
.almost_full ()
// synopsys translate_on
);
defparam
scfifo_component.add_ram_output_register = "ON",
scfifo_component.intended_device_family = "Cyclone II",
scfifo_component.lpm_numwords = 128,
scfifo_component.lpm_showahead = "OFF",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 144,
scfifo_component.lpm_widthu = 7,
scfifo_component.overflow_checking = "ON",
scfifo_component.underflow_checking = "ON",
scfifo_component.use_eab = "ON";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "1"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "128"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "144"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "ON"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "128"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "144"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "7"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: data 0 0 144 0 INPUT NODEFVAL data[143..0]
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty
// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL full
// Retrieval info: USED_PORT: q 0 0 144 0 OUTPUT NODEFVAL q[143..0]
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
// Retrieval info: USED_PORT: usedw 0 0 7 0 OUTPUT NODEFVAL usedw[6..0]
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
// Retrieval info: CONNECT: @data 0 0 144 0 data 0 0 144 0
// Retrieval info: CONNECT: q 0 0 144 0 @q 0 0 144 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: usedw 0 0 7 0 @usedw 0 0 7 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_144x128.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_144x128.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_144x128.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_144x128.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_144x128_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_144x128_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_144x128_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_144x128_wave*.jpg FALSE
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A31O_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__A31O_FUNCTIONAL_PP_V
/**
* a31o: 3-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__a31o (
VPWR,
VGND,
X ,
A1 ,
A2 ,
A3 ,
B1
);
// Module ports
input VPWR;
input VGND;
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
// Local signals
wire B1 and0_out ;
wire or0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
and and0 (and0_out , A3, A1, A2 );
or or0 (or0_out_X , and0_out, B1 );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__A31O_FUNCTIONAL_PP_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__AND3B_PP_SYMBOL_V
`define SKY130_FD_SC_MS__AND3B_PP_SYMBOL_V
/**
* and3b: 3-input AND, first input inverted.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__and3b (
//# {{data|Data Signals}}
input A_N ,
input B ,
input C ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__AND3B_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__BUFINV_TB_V
`define SKY130_FD_SC_HD__BUFINV_TB_V
/**
* bufinv: Buffer followed by inverter.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__bufinv.v"
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 A = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 A = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 A = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_hd__bufinv dut (.A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__BUFINV_TB_V
|
//
// Generated by Bluespec Compiler, version 2021.07 (build 4cac6eb)
//
//
// Ports:
// Name I/O size props
// RDY_reset O 1 const
// RDY_predict_req O 1
// predict_rsp O 64
// RDY_bp_train O 1 const
// CLK I 1 clock
// RST_N I 1 reset
// predict_req_pc I 64 reg
// predict_rsp_is_i32_not_i16 I 1
// predict_rsp_instr I 32
// bp_train_pc I 64
// bp_train_is_i32_not_i16 I 1
// bp_train_instr I 32
// bp_train_cf_info I 195
// EN_reset I 1
// EN_predict_req I 1
// EN_bp_train I 1
//
// Combinational paths from inputs to outputs:
// (predict_rsp_is_i32_not_i16, predict_rsp_instr) -> predict_rsp
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkBranch_Predictor(CLK,
RST_N,
EN_reset,
RDY_reset,
predict_req_pc,
EN_predict_req,
RDY_predict_req,
predict_rsp_is_i32_not_i16,
predict_rsp_instr,
predict_rsp,
bp_train_pc,
bp_train_is_i32_not_i16,
bp_train_instr,
bp_train_cf_info,
EN_bp_train,
RDY_bp_train);
input CLK;
input RST_N;
// action method reset
input EN_reset;
output RDY_reset;
// action method predict_req
input [63 : 0] predict_req_pc;
input EN_predict_req;
output RDY_predict_req;
// value method predict_rsp
input predict_rsp_is_i32_not_i16;
input [31 : 0] predict_rsp_instr;
output [63 : 0] predict_rsp;
// action method bp_train
input [63 : 0] bp_train_pc;
input bp_train_is_i32_not_i16;
input [31 : 0] bp_train_instr;
input [194 : 0] bp_train_cf_info;
input EN_bp_train;
output RDY_bp_train;
// signals for module outputs
wire [63 : 0] predict_rsp;
wire RDY_bp_train, RDY_predict_req, RDY_reset;
// register rg_index
reg [8 : 0] rg_index;
wire [8 : 0] rg_index$D_IN;
wire rg_index$EN;
// register rg_pc
reg [63 : 0] rg_pc;
wire [63 : 0] rg_pc$D_IN;
wire rg_pc$EN;
// register rg_ras
reg [1023 : 0] rg_ras;
wire [1023 : 0] rg_ras$D_IN;
wire rg_ras$EN;
// register rg_resetting
reg rg_resetting;
wire rg_resetting$D_IN, rg_resetting$EN;
// ports of submodule btb_bramcore2
wire [117 : 0] btb_bramcore2$DIA, btb_bramcore2$DIB, btb_bramcore2$DOA;
wire [8 : 0] btb_bramcore2$ADDRA, btb_bramcore2$ADDRB;
wire btb_bramcore2$ENA,
btb_bramcore2$ENB,
btb_bramcore2$WEA,
btb_bramcore2$WEB;
// ports of submodule rf_btb_fsms
wire [8 : 0] rf_btb_fsms$ADDR_1,
rf_btb_fsms$ADDR_2,
rf_btb_fsms$ADDR_3,
rf_btb_fsms$ADDR_4,
rf_btb_fsms$ADDR_5,
rf_btb_fsms$ADDR_IN;
wire [1 : 0] rf_btb_fsms$D_IN, rf_btb_fsms$D_OUT_1;
wire rf_btb_fsms$WE;
// rule scheduling signals
wire CAN_FIRE_RL_rl_reset,
CAN_FIRE_bp_train,
CAN_FIRE_predict_req,
CAN_FIRE_reset,
WILL_FIRE_RL_rl_reset,
WILL_FIRE_bp_train,
WILL_FIRE_predict_req,
WILL_FIRE_reset;
// inputs to muxes for submodule ports
reg [1 : 0] MUX_rf_btb_fsms$upd_2__VAL_1;
wire [117 : 0] MUX_btb_bramcore2$b_put_3__VAL_1;
wire [8 : 0] MUX_rg_index$write_1__VAL_2;
wire MUX_btb_bramcore2$b_put_1__SEL_1;
// remaining internal signals
reg [63 : 0] _theResult_____1_fst__h7498,
_theResult_____1_fst__h7542,
pred_PC__h7403;
reg [1 : 0] _theResult_____1_snd__h7499, _theResult_____1_snd__h7543;
wire [1023 : 0] IF_IF_bp_train_is_i32_not_i16_THEN_NOT_bp_trai_ETC___d208,
IF_IF_bp_train_is_i32_not_i16_THEN_NOT_bp_trai_ETC___d210;
wire [959 : 0] IF_IF_bp_train_is_i32_not_i16_THEN_NOT_bp_trai_ETC___d204;
wire [63 : 0] _theResult_____1__h2383,
_theResult_____1_fst__h7431,
_theResult____h2382,
pred_pc__h3338,
pred_pc__h3340,
ret_pc___1__h4093,
ret_pc__h4055;
wire [1 : 0] _theResult_____1_snd__h7432;
wire IF_bp_train_is_i32_not_i16_OR_bp_train_instr_B_ETC___d173,
IF_bp_train_is_i32_not_i16_OR_bp_train_instr_B_ETC___d176,
IF_bp_train_is_i32_not_i16_OR_bp_train_instr_B_ETC___d197,
IF_bp_train_is_i32_not_i16_THEN_NOT_bp_train_i_ETC___d189,
IF_bp_train_is_i32_not_i16_THEN_NOT_bp_train_i_ETC___d190,
IF_bp_train_is_i32_not_i16_THEN_NOT_bp_train_i_ETC___d199,
IF_bp_train_is_i32_not_i16_THEN_bp_train_instr_ETC___d148,
IF_bp_train_is_i32_not_i16_THEN_bp_train_instr_ETC___d149,
IF_bp_train_is_i32_not_i16_THEN_bp_train_instr_ETC___d157,
IF_predict_rsp_is_i32_not_i16_OR_predict_rsp_i_ETC___d68,
IF_predict_rsp_is_i32_not_i16_OR_predict_rsp_i_ETC___d83,
IF_predict_rsp_is_i32_not_i16_THEN_NOT_predict_ETC___d50,
IF_predict_rsp_is_i32_not_i16_THEN_NOT_predict_ETC___d51,
IF_predict_rsp_is_i32_not_i16_THEN_predict_rsp_ETC___d78,
IF_predict_rsp_is_i32_not_i16_THEN_predict_rsp_ETC___d86,
NOT_bp_train_instr_BITS_11_TO_7_16_EQ_bp_train_ETC___d194,
NOT_bp_train_instr_BITS_15_TO_12_13_EQ_0b1000__ETC___d125,
NOT_bp_train_instr_BITS_15_TO_12_13_EQ_0b1001__ETC___d130,
NOT_predict_rsp_instr_BITS_11_TO_7_8_EQ_predic_ETC___d80,
bp_train_instr_BITS_15_TO_12_13_EQ_0b1000_14_A_ETC___d153,
bp_train_instr_BITS_15_TO_12_13_EQ_0b1000_14_A_ETC___d196,
bp_train_instr_BITS_15_TO_12_13_EQ_0b1000_14_O_ETC___d168,
bp_train_instr_BITS_15_TO_12_13_EQ_0b1001_26_A_ETC___d144,
predict_rsp_instr_BITS_15_TO_12_6_EQ_0b1000_7__ETC___d26,
predict_rsp_instr_BITS_15_TO_12_6_EQ_0b1000_7__ETC___d82,
predict_rsp_instr_BITS_15_TO_12_6_EQ_0b1001_7__ETC___d30;
// action method reset
assign RDY_reset = 1'd1 ;
assign CAN_FIRE_reset = 1'd1 ;
assign WILL_FIRE_reset = EN_reset ;
// action method predict_req
assign RDY_predict_req = !rg_resetting ;
assign CAN_FIRE_predict_req = !rg_resetting ;
assign WILL_FIRE_predict_req = EN_predict_req ;
// value method predict_rsp
assign predict_rsp =
(_theResult_____1__h2383 == 64'hFFFFFFFFFFFFFFFF) ?
pred_pc__h3340 :
_theResult_____1__h2383 ;
// action method bp_train
assign RDY_bp_train = 1'd1 ;
assign CAN_FIRE_bp_train = 1'd1 ;
assign WILL_FIRE_bp_train = EN_bp_train ;
// submodule btb_bramcore2
BRAM2 #(.PIPELINED(1'd0),
.ADDR_WIDTH(32'd9),
.DATA_WIDTH(32'd118),
.MEMSIZE(10'd512)) btb_bramcore2(.CLKA(CLK),
.CLKB(CLK),
.ADDRA(btb_bramcore2$ADDRA),
.ADDRB(btb_bramcore2$ADDRB),
.DIA(btb_bramcore2$DIA),
.DIB(btb_bramcore2$DIB),
.WEA(btb_bramcore2$WEA),
.WEB(btb_bramcore2$WEB),
.ENA(btb_bramcore2$ENA),
.ENB(btb_bramcore2$ENB),
.DOA(btb_bramcore2$DOA),
.DOB());
// submodule rf_btb_fsms
RegFile #(.addr_width(32'd9),
.data_width(32'd2),
.lo(9'h0),
.hi(9'd511)) rf_btb_fsms(.CLK(CLK),
.ADDR_1(rf_btb_fsms$ADDR_1),
.ADDR_2(rf_btb_fsms$ADDR_2),
.ADDR_3(rf_btb_fsms$ADDR_3),
.ADDR_4(rf_btb_fsms$ADDR_4),
.ADDR_5(rf_btb_fsms$ADDR_5),
.ADDR_IN(rf_btb_fsms$ADDR_IN),
.D_IN(rf_btb_fsms$D_IN),
.WE(rf_btb_fsms$WE),
.D_OUT_1(rf_btb_fsms$D_OUT_1),
.D_OUT_2(),
.D_OUT_3(),
.D_OUT_4(),
.D_OUT_5());
// rule RL_rl_reset
assign CAN_FIRE_RL_rl_reset = rg_resetting ;
assign WILL_FIRE_RL_rl_reset = rg_resetting && !EN_bp_train ;
// inputs to muxes for submodule ports
assign MUX_btb_bramcore2$b_put_1__SEL_1 =
EN_bp_train && pred_PC__h7403 != 64'hFFFFFFFFFFFFFFFF ;
assign MUX_btb_bramcore2$b_put_3__VAL_1 =
{ 1'd1, bp_train_cf_info[192:139], pred_PC__h7403[63:1] } ;
always@(bp_train_cf_info or
rf_btb_fsms$D_OUT_1 or _theResult_____1_snd__h7432)
begin
case (bp_train_cf_info[194:193])
2'd0: MUX_rf_btb_fsms$upd_2__VAL_1 = _theResult_____1_snd__h7432;
2'd1, 2'd2: MUX_rf_btb_fsms$upd_2__VAL_1 = 2'b11;
2'd3: MUX_rf_btb_fsms$upd_2__VAL_1 = rf_btb_fsms$D_OUT_1;
endcase
end
assign MUX_rg_index$write_1__VAL_2 = rg_index + 9'd1 ;
// register rg_index
assign rg_index$D_IN = EN_reset ? 9'd0 : MUX_rg_index$write_1__VAL_2 ;
assign rg_index$EN = WILL_FIRE_RL_rl_reset || EN_reset ;
// register rg_pc
assign rg_pc$D_IN = predict_req_pc ;
assign rg_pc$EN = EN_predict_req ;
// register rg_ras
assign rg_ras$D_IN =
(IF_bp_train_is_i32_not_i16_THEN_bp_train_instr_ETC___d149 ||
IF_bp_train_is_i32_not_i16_THEN_bp_train_instr_ETC___d157 &&
IF_bp_train_is_i32_not_i16_THEN_bp_train_instr_ETC___d148 &&
(IF_bp_train_is_i32_not_i16_OR_bp_train_instr_B_ETC___d173 ||
IF_bp_train_is_i32_not_i16_OR_bp_train_instr_B_ETC___d176)) ?
IF_IF_bp_train_is_i32_not_i16_THEN_NOT_bp_trai_ETC___d208 :
IF_IF_bp_train_is_i32_not_i16_THEN_NOT_bp_trai_ETC___d210 ;
assign rg_ras$EN = EN_bp_train ;
// register rg_resetting
assign rg_resetting$D_IN = EN_reset ;
assign rg_resetting$EN =
WILL_FIRE_RL_rl_reset && rg_index == 9'd511 || EN_reset ;
// submodule btb_bramcore2
assign btb_bramcore2$ADDRA = predict_req_pc[9:1] ;
assign btb_bramcore2$ADDRB =
MUX_btb_bramcore2$b_put_1__SEL_1 ?
bp_train_cf_info[138:130] :
rg_index ;
assign btb_bramcore2$DIA =
118'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
assign btb_bramcore2$DIB =
MUX_btb_bramcore2$b_put_1__SEL_1 ?
MUX_btb_bramcore2$b_put_3__VAL_1 :
118'd0 ;
assign btb_bramcore2$WEA = 1'd0 ;
assign btb_bramcore2$WEB = 1'd1 ;
assign btb_bramcore2$ENA = EN_predict_req ;
assign btb_bramcore2$ENB =
EN_bp_train && pred_PC__h7403 != 64'hFFFFFFFFFFFFFFFF ||
WILL_FIRE_RL_rl_reset ;
// submodule rf_btb_fsms
assign rf_btb_fsms$ADDR_1 = bp_train_cf_info[138:130] ;
assign rf_btb_fsms$ADDR_2 = 9'h0 ;
assign rf_btb_fsms$ADDR_3 = 9'h0 ;
assign rf_btb_fsms$ADDR_4 = 9'h0 ;
assign rf_btb_fsms$ADDR_5 = 9'h0 ;
assign rf_btb_fsms$ADDR_IN =
MUX_btb_bramcore2$b_put_1__SEL_1 ?
bp_train_cf_info[138:130] :
rg_index ;
assign rf_btb_fsms$D_IN =
MUX_btb_bramcore2$b_put_1__SEL_1 ?
MUX_rf_btb_fsms$upd_2__VAL_1 :
2'b0 ;
assign rf_btb_fsms$WE =
EN_bp_train && pred_PC__h7403 != 64'hFFFFFFFFFFFFFFFF ||
WILL_FIRE_RL_rl_reset ;
// remaining internal signals
assign IF_IF_bp_train_is_i32_not_i16_THEN_NOT_bp_trai_ETC___d204 =
(IF_bp_train_is_i32_not_i16_THEN_NOT_bp_train_i_ETC___d190 &&
IF_bp_train_is_i32_not_i16_THEN_bp_train_instr_ETC___d157 &&
IF_bp_train_is_i32_not_i16_THEN_NOT_bp_train_i_ETC___d199) ?
rg_ras[1023:64] :
rg_ras[959:0] ;
assign IF_IF_bp_train_is_i32_not_i16_THEN_NOT_bp_trai_ETC___d208 =
{ IF_IF_bp_train_is_i32_not_i16_THEN_NOT_bp_trai_ETC___d204,
bp_train_is_i32_not_i16 ? ret_pc__h4055 : ret_pc___1__h4093 } ;
assign IF_IF_bp_train_is_i32_not_i16_THEN_NOT_bp_trai_ETC___d210 =
(IF_bp_train_is_i32_not_i16_THEN_NOT_bp_train_i_ETC___d190 &&
IF_bp_train_is_i32_not_i16_THEN_bp_train_instr_ETC___d157 &&
IF_bp_train_is_i32_not_i16_THEN_NOT_bp_train_i_ETC___d199) ?
{ 64'hFFFFFFFFFFFFFFFF, rg_ras[1023:64] } :
rg_ras ;
assign IF_bp_train_is_i32_not_i16_OR_bp_train_instr_B_ETC___d173 =
(bp_train_is_i32_not_i16 ||
bp_train_instr[15:13] == 3'b101 &&
bp_train_instr[1:0] == 2'b01) ?
bp_train_instr[19:15] != 5'd1 &&
bp_train_instr[19:15] != 5'd5 :
(bp_train_instr_BITS_15_TO_12_13_EQ_0b1000_14_O_ETC___d168 ?
bp_train_instr[11:7] != 5'd1 &&
bp_train_instr[11:7] != 5'd5 :
bp_train_instr[19:15] != 5'd1 &&
bp_train_instr[19:15] != 5'd5) ;
assign IF_bp_train_is_i32_not_i16_OR_bp_train_instr_B_ETC___d176 =
(bp_train_is_i32_not_i16 ||
bp_train_instr[15:13] == 3'b101 &&
bp_train_instr[1:0] == 2'b01) ?
bp_train_instr[19:15] == 5'd1 ||
bp_train_instr[19:15] == 5'd5 :
(bp_train_instr_BITS_15_TO_12_13_EQ_0b1000_14_O_ETC___d168 ?
bp_train_instr[11:7] == 5'd1 ||
bp_train_instr[11:7] == 5'd5 :
bp_train_instr[19:15] == 5'd1 ||
bp_train_instr[19:15] == 5'd5) ;
assign IF_bp_train_is_i32_not_i16_OR_bp_train_instr_B_ETC___d197 =
(bp_train_is_i32_not_i16 ||
bp_train_instr[15:13] == 3'b101 &&
bp_train_instr[1:0] == 2'b01) ?
NOT_bp_train_instr_BITS_11_TO_7_16_EQ_bp_train_ETC___d194 :
bp_train_instr_BITS_15_TO_12_13_EQ_0b1000_14_A_ETC___d196 ;
assign IF_bp_train_is_i32_not_i16_THEN_NOT_bp_train_i_ETC___d189 =
bp_train_is_i32_not_i16 ?
bp_train_instr[11:7] != 5'd1 && bp_train_instr[11:7] != 5'd5 :
bp_train_instr[15:13] == 3'b101 &&
bp_train_instr[1:0] == 2'b01 ||
bp_train_instr_BITS_15_TO_12_13_EQ_0b1000_14_A_ETC___d153 ||
NOT_bp_train_instr_BITS_15_TO_12_13_EQ_0b1001__ETC___d130 &&
bp_train_instr[11:7] != 5'd1 &&
bp_train_instr[11:7] != 5'd5 ;
assign IF_bp_train_is_i32_not_i16_THEN_NOT_bp_train_i_ETC___d190 =
(bp_train_is_i32_not_i16 ?
bp_train_instr[6:0] != 7'b1101111 :
(bp_train_instr[15:13] != 3'b101 ||
bp_train_instr[1:0] != 2'b01) &&
(bp_train_instr_BITS_15_TO_12_13_EQ_0b1000_14_A_ETC___d153 ||
bp_train_instr_BITS_15_TO_12_13_EQ_0b1001_26_A_ETC___d144 ||
bp_train_instr[6:0] != 7'b1101111)) ||
IF_bp_train_is_i32_not_i16_THEN_NOT_bp_train_i_ETC___d189 ;
assign IF_bp_train_is_i32_not_i16_THEN_NOT_bp_train_i_ETC___d199 =
IF_bp_train_is_i32_not_i16_THEN_NOT_bp_train_i_ETC___d189 &&
IF_bp_train_is_i32_not_i16_OR_bp_train_instr_B_ETC___d176 ||
IF_bp_train_is_i32_not_i16_THEN_bp_train_instr_ETC___d148 &&
IF_bp_train_is_i32_not_i16_OR_bp_train_instr_B_ETC___d176 &&
IF_bp_train_is_i32_not_i16_OR_bp_train_instr_B_ETC___d197 ;
assign IF_bp_train_is_i32_not_i16_THEN_bp_train_instr_ETC___d148 =
bp_train_is_i32_not_i16 ?
bp_train_instr[11:7] == 5'd1 || bp_train_instr[11:7] == 5'd5 :
(bp_train_instr[15:13] != 3'b101 ||
bp_train_instr[1:0] != 2'b01) &&
NOT_bp_train_instr_BITS_15_TO_12_13_EQ_0b1000__ETC___d125 &&
(bp_train_instr_BITS_15_TO_12_13_EQ_0b1001_26_A_ETC___d144 ||
bp_train_instr[11:7] == 5'd1 ||
bp_train_instr[11:7] == 5'd5) ;
assign IF_bp_train_is_i32_not_i16_THEN_bp_train_instr_ETC___d149 =
(bp_train_is_i32_not_i16 ?
bp_train_instr[6:0] == 7'b1101111 :
bp_train_instr[15:13] == 3'b101 &&
bp_train_instr[1:0] == 2'b01 ||
NOT_bp_train_instr_BITS_15_TO_12_13_EQ_0b1000__ETC___d125 &&
NOT_bp_train_instr_BITS_15_TO_12_13_EQ_0b1001__ETC___d130 &&
bp_train_instr[6:0] == 7'b1101111) &&
IF_bp_train_is_i32_not_i16_THEN_bp_train_instr_ETC___d148 ;
assign IF_bp_train_is_i32_not_i16_THEN_bp_train_instr_ETC___d157 =
bp_train_is_i32_not_i16 ?
bp_train_instr[6:0] == 7'b1100111 :
(bp_train_instr[15:13] != 3'b101 ||
bp_train_instr[1:0] != 2'b01) &&
(bp_train_instr_BITS_15_TO_12_13_EQ_0b1000_14_A_ETC___d153 ||
bp_train_instr_BITS_15_TO_12_13_EQ_0b1001_26_A_ETC___d144 ||
bp_train_instr[6:0] == 7'b1100111) ;
assign IF_predict_rsp_is_i32_not_i16_OR_predict_rsp_i_ETC___d68 =
(predict_rsp_is_i32_not_i16 ||
predict_rsp_instr[15:13] == 3'b101 &&
predict_rsp_instr[1:0] == 2'b01) ?
predict_rsp_instr[19:15] == 5'd1 ||
predict_rsp_instr[19:15] == 5'd5 :
(((predict_rsp_instr[15:12] == 4'b1000 ||
predict_rsp_instr[15:12] == 4'b1001) &&
predict_rsp_instr[11:7] != 5'd0 &&
predict_rsp_instr[6:2] == 5'd0 &&
predict_rsp_instr[1:0] == 2'b10) ?
predict_rsp_instr[11:7] == 5'd1 ||
predict_rsp_instr[11:7] == 5'd5 :
predict_rsp_instr[19:15] == 5'd1 ||
predict_rsp_instr[19:15] == 5'd5) ;
assign IF_predict_rsp_is_i32_not_i16_OR_predict_rsp_i_ETC___d83 =
(predict_rsp_is_i32_not_i16 ||
predict_rsp_instr[15:13] == 3'b101 &&
predict_rsp_instr[1:0] == 2'b01) ?
NOT_predict_rsp_instr_BITS_11_TO_7_8_EQ_predic_ETC___d80 :
predict_rsp_instr_BITS_15_TO_12_6_EQ_0b1000_7__ETC___d82 ;
assign IF_predict_rsp_is_i32_not_i16_THEN_NOT_predict_ETC___d50 =
predict_rsp_is_i32_not_i16 ?
predict_rsp_instr[11:7] != 5'd1 &&
predict_rsp_instr[11:7] != 5'd5 :
predict_rsp_instr[15:13] == 3'b101 &&
predict_rsp_instr[1:0] == 2'b01 ||
predict_rsp_instr_BITS_15_TO_12_6_EQ_0b1000_7__ETC___d26 ||
(predict_rsp_instr[15:12] != 4'b1001 ||
predict_rsp_instr[11:7] == 5'd0 ||
predict_rsp_instr[6:2] != 5'd0 ||
predict_rsp_instr[1:0] != 2'b10) &&
predict_rsp_instr[11:7] != 5'd1 &&
predict_rsp_instr[11:7] != 5'd5 ;
assign IF_predict_rsp_is_i32_not_i16_THEN_NOT_predict_ETC___d51 =
(predict_rsp_is_i32_not_i16 ?
predict_rsp_instr[6:0] != 7'b1101111 :
(predict_rsp_instr[15:13] != 3'b101 ||
predict_rsp_instr[1:0] != 2'b01) &&
(predict_rsp_instr_BITS_15_TO_12_6_EQ_0b1000_7__ETC___d26 ||
predict_rsp_instr_BITS_15_TO_12_6_EQ_0b1001_7__ETC___d30 ||
predict_rsp_instr[6:0] != 7'b1101111)) ||
IF_predict_rsp_is_i32_not_i16_THEN_NOT_predict_ETC___d50 ;
assign IF_predict_rsp_is_i32_not_i16_THEN_predict_rsp_ETC___d78 =
(predict_rsp_is_i32_not_i16 ?
predict_rsp_instr[11:7] == 5'd1 ||
predict_rsp_instr[11:7] == 5'd5 :
(predict_rsp_instr[15:13] != 3'b101 ||
predict_rsp_instr[1:0] != 2'b01) &&
(predict_rsp_instr[15:12] != 4'b1000 ||
predict_rsp_instr[11:7] == 5'd0 ||
predict_rsp_instr[6:2] != 5'd0 ||
predict_rsp_instr[1:0] != 2'b10) &&
(predict_rsp_instr_BITS_15_TO_12_6_EQ_0b1001_7__ETC___d30 ||
predict_rsp_instr[11:7] == 5'd1 ||
predict_rsp_instr[11:7] == 5'd5)) &&
IF_predict_rsp_is_i32_not_i16_OR_predict_rsp_i_ETC___d68 ;
assign IF_predict_rsp_is_i32_not_i16_THEN_predict_rsp_ETC___d86 =
(predict_rsp_is_i32_not_i16 ?
predict_rsp_instr[6:0] == 7'b1100111 :
(predict_rsp_instr[15:13] != 3'b101 ||
predict_rsp_instr[1:0] != 2'b01) &&
(predict_rsp_instr_BITS_15_TO_12_6_EQ_0b1000_7__ETC___d26 ||
predict_rsp_instr_BITS_15_TO_12_6_EQ_0b1001_7__ETC___d30 ||
predict_rsp_instr[6:0] == 7'b1100111)) &&
(IF_predict_rsp_is_i32_not_i16_THEN_NOT_predict_ETC___d50 &&
IF_predict_rsp_is_i32_not_i16_OR_predict_rsp_i_ETC___d68 ||
IF_predict_rsp_is_i32_not_i16_THEN_predict_rsp_ETC___d78 &&
IF_predict_rsp_is_i32_not_i16_OR_predict_rsp_i_ETC___d83) ;
assign NOT_bp_train_instr_BITS_11_TO_7_16_EQ_bp_train_ETC___d194 =
bp_train_instr[11:7] != bp_train_instr[19:15] ;
assign NOT_bp_train_instr_BITS_15_TO_12_13_EQ_0b1000__ETC___d125 =
bp_train_instr[15:12] != 4'b1000 ||
bp_train_instr[11:7] == 5'd0 ||
bp_train_instr[6:2] != 5'd0 ||
bp_train_instr[1:0] != 2'b10 ;
assign NOT_bp_train_instr_BITS_15_TO_12_13_EQ_0b1001__ETC___d130 =
bp_train_instr[15:12] != 4'b1001 ||
bp_train_instr[11:7] == 5'd0 ||
bp_train_instr[6:2] != 5'd0 ||
bp_train_instr[1:0] != 2'b10 ;
assign NOT_predict_rsp_instr_BITS_11_TO_7_8_EQ_predic_ETC___d80 =
predict_rsp_instr[11:7] != predict_rsp_instr[19:15] ;
assign _theResult_____1__h2383 =
(_theResult____h2382 == 64'hFFFFFFFFFFFFFFFF &&
btb_bramcore2$DOA[117] &&
btb_bramcore2$DOA[116:63] == rg_pc[63:10]) ?
pred_pc__h3338 :
_theResult____h2382 ;
assign _theResult_____1_fst__h7431 =
bp_train_cf_info[128] ?
_theResult_____1_fst__h7498 :
_theResult_____1_fst__h7542 ;
assign _theResult_____1_snd__h7432 =
bp_train_cf_info[128] ?
_theResult_____1_snd__h7499 :
_theResult_____1_snd__h7543 ;
assign _theResult____h2382 =
(IF_predict_rsp_is_i32_not_i16_THEN_NOT_predict_ETC___d51 &&
IF_predict_rsp_is_i32_not_i16_THEN_predict_rsp_ETC___d86) ?
rg_ras[63:0] :
64'hFFFFFFFFFFFFFFFF ;
assign bp_train_instr_BITS_15_TO_12_13_EQ_0b1000_14_A_ETC___d153 =
bp_train_instr[15:12] == 4'b1000 &&
bp_train_instr[11:7] != 5'd0 &&
bp_train_instr[6:2] == 5'd0 &&
bp_train_instr[1:0] == 2'b10 ;
assign bp_train_instr_BITS_15_TO_12_13_EQ_0b1000_14_A_ETC___d196 =
bp_train_instr_BITS_15_TO_12_13_EQ_0b1000_14_A_ETC___d153 ||
(bp_train_instr_BITS_15_TO_12_13_EQ_0b1001_26_A_ETC___d144 ?
bp_train_instr[11:7] != 5'd1 :
NOT_bp_train_instr_BITS_11_TO_7_16_EQ_bp_train_ETC___d194) ;
assign bp_train_instr_BITS_15_TO_12_13_EQ_0b1000_14_O_ETC___d168 =
(bp_train_instr[15:12] == 4'b1000 ||
bp_train_instr[15:12] == 4'b1001) &&
bp_train_instr[11:7] != 5'd0 &&
bp_train_instr[6:2] == 5'd0 &&
bp_train_instr[1:0] == 2'b10 ;
assign bp_train_instr_BITS_15_TO_12_13_EQ_0b1001_26_A_ETC___d144 =
bp_train_instr[15:12] == 4'b1001 &&
bp_train_instr[11:7] != 5'd0 &&
bp_train_instr[6:2] == 5'd0 &&
bp_train_instr[1:0] == 2'b10 ;
assign pred_pc__h3338 = { btb_bramcore2$DOA[62:0], 1'b0 } ;
assign pred_pc__h3340 =
rg_pc + (predict_rsp_is_i32_not_i16 ? 64'd4 : 64'd2) ;
assign predict_rsp_instr_BITS_15_TO_12_6_EQ_0b1000_7__ETC___d26 =
predict_rsp_instr[15:12] == 4'b1000 &&
predict_rsp_instr[11:7] != 5'd0 &&
predict_rsp_instr[6:2] == 5'd0 &&
predict_rsp_instr[1:0] == 2'b10 ;
assign predict_rsp_instr_BITS_15_TO_12_6_EQ_0b1000_7__ETC___d82 =
predict_rsp_instr_BITS_15_TO_12_6_EQ_0b1000_7__ETC___d26 ||
(predict_rsp_instr_BITS_15_TO_12_6_EQ_0b1001_7__ETC___d30 ?
predict_rsp_instr[11:7] != 5'd1 :
NOT_predict_rsp_instr_BITS_11_TO_7_8_EQ_predic_ETC___d80) ;
assign predict_rsp_instr_BITS_15_TO_12_6_EQ_0b1001_7__ETC___d30 =
predict_rsp_instr[15:12] == 4'b1001 &&
predict_rsp_instr[11:7] != 5'd0 &&
predict_rsp_instr[6:2] == 5'd0 &&
predict_rsp_instr[1:0] == 2'b10 ;
assign ret_pc___1__h4093 = bp_train_pc + 64'd2 ;
assign ret_pc__h4055 = bp_train_pc + 64'd4 ;
always@(rf_btb_fsms$D_OUT_1 or bp_train_cf_info)
begin
case (rf_btb_fsms$D_OUT_1)
2'b0: _theResult_____1_fst__h7498 = bp_train_cf_info[127:64];
2'b01, 2'b10, 2'b11:
_theResult_____1_fst__h7498 = bp_train_cf_info[63:0];
endcase
end
always@(rf_btb_fsms$D_OUT_1 or bp_train_cf_info)
begin
case (rf_btb_fsms$D_OUT_1)
2'b0, 2'b01, 2'b10:
_theResult_____1_fst__h7542 = bp_train_cf_info[127:64];
2'b11: _theResult_____1_fst__h7542 = bp_train_cf_info[63:0];
endcase
end
always@(bp_train_cf_info or _theResult_____1_fst__h7431)
begin
case (bp_train_cf_info[194:193])
2'd0: pred_PC__h7403 = _theResult_____1_fst__h7431;
2'd1, 2'd2: pred_PC__h7403 = bp_train_cf_info[63:0];
2'd3: pred_PC__h7403 = 64'hFFFFFFFFFFFFFFFF;
endcase
end
always@(rf_btb_fsms$D_OUT_1)
begin
case (rf_btb_fsms$D_OUT_1)
2'b0: _theResult_____1_snd__h7499 = 2'b01;
2'b01: _theResult_____1_snd__h7499 = 2'b10;
2'b10, 2'b11: _theResult_____1_snd__h7499 = 2'b11;
endcase
end
always@(rf_btb_fsms$D_OUT_1)
begin
case (rf_btb_fsms$D_OUT_1)
2'b0, 2'b01: _theResult_____1_snd__h7543 = 2'b0;
2'b10: _theResult_____1_snd__h7543 = 2'b01;
2'b11: _theResult_____1_snd__h7543 = 2'b10;
endcase
end
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
rg_index <= `BSV_ASSIGNMENT_DELAY 9'd0;
rg_ras <= `BSV_ASSIGNMENT_DELAY
1024'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF;
rg_resetting <= `BSV_ASSIGNMENT_DELAY 1'd1;
end
else
begin
if (rg_index$EN) rg_index <= `BSV_ASSIGNMENT_DELAY rg_index$D_IN;
if (rg_ras$EN) rg_ras <= `BSV_ASSIGNMENT_DELAY rg_ras$D_IN;
if (rg_resetting$EN)
rg_resetting <= `BSV_ASSIGNMENT_DELAY rg_resetting$D_IN;
end
if (rg_pc$EN) rg_pc <= `BSV_ASSIGNMENT_DELAY rg_pc$D_IN;
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
rg_index = 9'h0AA;
rg_pc = 64'hAAAAAAAAAAAAAAAA;
rg_ras =
1024'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
rg_resetting = 1'h0;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
endmodule // mkBranch_Predictor
|
`timescale 1ns / 1ps
/*
-- Module Name: DES Sbox 2
-- Description: Sbox 2 del algoritmo DES
-- Dependencies: -- none
-- Parameters: -- none
-- Original Author: Héctor Cabrera
-- Current Author:
-- Notas:
-- History:
-- Creacion 05 de Junio 2015
*/
module des_sbox2
(
// -- inputs ------------------------------------------------- >>>>>
input wire [0:5] right_xor_key_segment_din,
// -- outputs ------------------------------------------------ >>>>>
output reg [0:3] sbox_dout
);
always @(*)
case ({right_xor_key_segment_din[0], right_xor_key_segment_din[5]})
2'b00:
case (right_xor_key_segment_din[1:4])
4'd0: sbox_dout = 4'd15;
4'd1: sbox_dout = 4'd1;
4'd2: sbox_dout = 4'd8;
4'd3: sbox_dout = 4'd14;
4'd4: sbox_dout = 4'd6;
4'd5: sbox_dout = 4'd11;
4'd6: sbox_dout = 4'd3;
4'd7: sbox_dout = 4'd4;
4'd8: sbox_dout = 4'd9;
4'd9: sbox_dout = 4'd7;
4'd10: sbox_dout = 4'd2;
4'd11: sbox_dout = 4'd13;
4'd12: sbox_dout = 4'd12;
4'd13: sbox_dout = 4'd0;
4'd14: sbox_dout = 4'd5;
4'd15: sbox_dout = 4'd10;
endcase
2'b01:
case (right_xor_key_segment_din[1:4])
4'd0: sbox_dout = 4'd3;
4'd1: sbox_dout = 4'd13;
4'd2: sbox_dout = 4'd4;
4'd3: sbox_dout = 4'd7;
4'd4: sbox_dout = 4'd15;
4'd5: sbox_dout = 4'd2;
4'd6: sbox_dout = 4'd8;
4'd7: sbox_dout = 4'd14;
4'd8: sbox_dout = 4'd12;
4'd9: sbox_dout = 4'd0;
4'd10: sbox_dout = 4'd1;
4'd11: sbox_dout = 4'd10;
4'd12: sbox_dout = 4'd6;
4'd13: sbox_dout = 4'd9;
4'd14: sbox_dout = 4'd11;
4'd15: sbox_dout = 4'd5;
endcase
2'b10:
case (right_xor_key_segment_din[1:4])
4'd0: sbox_dout = 4'd0;
4'd1: sbox_dout = 4'd14;
4'd2: sbox_dout = 4'd7;
4'd3: sbox_dout = 4'd11;
4'd4: sbox_dout = 4'd10;
4'd5: sbox_dout = 4'd4;
4'd6: sbox_dout = 4'd13;
4'd7: sbox_dout = 4'd1;
4'd8: sbox_dout = 4'd5;
4'd9: sbox_dout = 4'd8;
4'd10: sbox_dout = 4'd12;
4'd11: sbox_dout = 4'd6;
4'd12: sbox_dout = 4'd9;
4'd13: sbox_dout = 4'd3;
4'd14: sbox_dout = 4'd2;
4'd15: sbox_dout = 4'd15;
endcase
2'b11:
case (right_xor_key_segment_din[1:4])
4'd0: sbox_dout = 4'd13;
4'd1: sbox_dout = 4'd8;
4'd2: sbox_dout = 4'd10;
4'd3: sbox_dout = 4'd1;
4'd4: sbox_dout = 4'd3;
4'd5: sbox_dout = 4'd15;
4'd6: sbox_dout = 4'd4;
4'd7: sbox_dout = 4'd2;
4'd8: sbox_dout = 4'd11;
4'd9: sbox_dout = 4'd6;
4'd10: sbox_dout = 4'd7;
4'd11: sbox_dout = 4'd12;
4'd12: sbox_dout = 4'd0;
4'd13: sbox_dout = 4'd5;
4'd14: sbox_dout = 4'd14;
4'd15: sbox_dout = 4'd9;
endcase
endcase // right_xor_key_segment_din[0], right_xor_key_segment_din[5]
endmodule
/* -- Plantilla de Instancia ------------------------------------- >>>>>
des_sbox2 sbox2
(
// -- inputs ------------------------------------------------- >>>>>
.right_xor_key_segment_din (right_xor_key_segment),
// -- outputs ------------------------------------------------ >>>>>
sbox_dout (sbox_dout)
);
*/
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__MUX2_TB_V
`define SKY130_FD_SC_HD__MUX2_TB_V
/**
* mux2: 2-input multiplexer.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__mux2.v"
module top();
// Inputs are registered
reg A0;
reg A1;
reg S;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A0 = 1'bX;
A1 = 1'bX;
S = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A0 = 1'b0;
#40 A1 = 1'b0;
#60 S = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A0 = 1'b1;
#180 A1 = 1'b1;
#200 S = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A0 = 1'b0;
#320 A1 = 1'b0;
#340 S = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 S = 1'b1;
#540 A1 = 1'b1;
#560 A0 = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 S = 1'bx;
#680 A1 = 1'bx;
#700 A0 = 1'bx;
end
sky130_fd_sc_hd__mux2 dut (.A0(A0), .A1(A1), .S(S), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__MUX2_TB_V
|
// megafunction wizard: %ALTPLL%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: Vga_clock.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module Vga_clock (
inclk0,
c0);
input inclk0;
output c0;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "25.174999"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "25.17500000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "Vga_clock.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "2000"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1007"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: GEN_FILE: TYPE_NORMAL Vga_clock.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL Vga_clock.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL Vga_clock.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Vga_clock.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Vga_clock.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Vga_clock_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Vga_clock_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__OR3_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__OR3_FUNCTIONAL_PP_V
/**
* or3: 3-input OR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__or3 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out_X , B, A, C );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__OR3_FUNCTIONAL_PP_V
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_protocol_converter:2.1
// IP Revision: 14
(* X_CORE_INFO = "axi_protocol_converter_v2_1_14_axi_protocol_converter,Vivado 2017.3" *)
(* CHECK_LICENSE_TYPE = "led_controller_design_auto_pc_0,axi_protocol_converter_v2_1_14_axi_protocol_converter,{}" *)
(* CORE_GENERATION_INFO = "led_controller_design_auto_pc_0,axi_protocol_converter_v2_1_14_axi_protocol_converter,{x_ipProduct=Vivado 2017.3,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_protocol_converter,x_ipVersion=2.1,x_ipCoreRevision=14,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_M_AXI_PROTOCOL=2,C_S_AXI_PROTOCOL=1,C_IGNORE_ID=0,C_AXI_ID_WIDTH=12,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=32,C_AXI_SUPPORTS_WRITE=1,C_AXI_SUPPORTS_READ=1,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=\
1,C_AXI_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_TRANSLATION_MODE=2}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module led_controller_design_auto_pc_0 (
aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awprot,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arprot,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN led_controller_design_processing_system7_0_0_FCLK_CLK0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
input wire aclk;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, TYPE INTERCONNECT" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
input wire [11 : 0] s_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
input wire [3 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
input wire [2 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
input wire [1 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
input wire [1 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
input wire [3 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
input wire [3 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
input wire s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
output wire s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WID" *)
input wire [11 : 0] s_axi_wid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
input wire s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
input wire s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
output wire s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
output wire [11 : 0] s_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
output wire s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
input wire s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
input wire [11 : 0] s_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
input wire [3 : 0] s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
input wire [2 : 0] s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
input wire [1 : 0] s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
input wire [1 : 0] s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
input wire [3 : 0] s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
input wire [3 : 0] s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
input wire s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
output wire s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
output wire [11 : 0] s_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
output wire [31 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
output wire s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
output wire s_axi_rvalid;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 100000000, ID_WIDTH 12, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 16, PHASE 0.000, CLK_DOMAIN led_controller_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
input wire s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output wire [31 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output wire m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input wire m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [31 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
output wire [3 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output wire m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input wire m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input wire m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output wire m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
output wire [31 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
output wire [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
output wire m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
input wire m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
input wire [31 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input wire m_axi_rvalid;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN led_controller_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output wire m_axi_rready;
axi_protocol_converter_v2_1_14_axi_protocol_converter #(
.C_FAMILY("zynq"),
.C_M_AXI_PROTOCOL(2),
.C_S_AXI_PROTOCOL(1),
.C_IGNORE_ID(0),
.C_AXI_ID_WIDTH(12),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(32),
.C_AXI_SUPPORTS_WRITE(1),
.C_AXI_SUPPORTS_READ(1),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_TRANSLATION_MODE(2)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(s_axi_awid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awregion(4'H0),
.s_axi_awqos(s_axi_awqos),
.s_axi_awuser(1'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(s_axi_wid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wuser(1'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(s_axi_bid),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(s_axi_arid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arregion(4'H0),
.s_axi_arqos(s_axi_arqos),
.s_axi_aruser(1'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(s_axi_rid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(),
.m_axi_awqos(),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(12'H000),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(),
.m_axi_arqos(),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(12'H000),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(1'H1),
.m_axi_ruser(1'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NAND2B_TB_V
`define SKY130_FD_SC_MS__NAND2B_TB_V
/**
* nand2b: 2-input NAND, first input inverted.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__nand2b.v"
module top();
// Inputs are registered
reg A_N;
reg B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A_N = 1'bX;
B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A_N = 1'b0;
#40 B = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A_N = 1'b1;
#160 B = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A_N = 1'b0;
#280 B = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 B = 1'b1;
#480 A_N = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 B = 1'bx;
#600 A_N = 1'bx;
end
sky130_fd_sc_ms__nand2b dut (.A_N(A_N), .B(B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__NAND2B_TB_V
|
/*
Copyright (c) 2016 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Parametrizable combinatorial parallel LFSR/CRC
*/
module lfsr #
(
// width of LFSR
parameter LFSR_WIDTH = 31,
// LFSR polynomial
parameter LFSR_POLY = 31'h10000001,
// LFSR configuration: "GALOIS", "FIBONACCI"
parameter LFSR_CONFIG = "FIBONACCI",
// LFSR feed forward enable
parameter LFSR_FEED_FORWARD = 0,
// bit-reverse input and output
parameter REVERSE = 0,
// width of data input
parameter DATA_WIDTH = 8,
// implementation style: "AUTO", "LOOP", "REDUCTION"
parameter STYLE = "AUTO"
)
(
input wire [DATA_WIDTH-1:0] data_in,
input wire [LFSR_WIDTH-1:0] state_in,
output wire [DATA_WIDTH-1:0] data_out,
output wire [LFSR_WIDTH-1:0] state_out
);
/*
Fully parametrizable combinatorial parallel LFSR/CRC module. Implements an unrolled LFSR
next state computation, shifting DATA_WIDTH bits per pass through the module. Input data
is XORed with LFSR feedback path, tie data_in to zero if this is not required.
Works in two parts: statically computes a set of bit masks, then uses these bit masks to
select bits for XORing to compute the next state.
Ports:
data_in
Data bits to be shifted through the LFSR (DATA_WIDTH bits)
state_in
LFSR/CRC current state input (LFSR_WIDTH bits)
data_out
Data bits shifted out of LFSR (DATA_WIDTH bits)
state_out
LFSR/CRC next state output (LFSR_WIDTH bits)
Parameters:
LFSR_WIDTH
Specify width of LFSR/CRC register
LFSR_POLY
Specify the LFSR/CRC polynomial in hex format. For example, the polynomial
x^32 + x^26 + x^23 + x^22 + x^16 + x^12 + x^11 + x^10 + x^8 + x^7 + x^5 + x^4 + x^2 + x + 1
would be represented as
32'h04c11db7
Note that the largest term (x^32) is suppressed. This term is generated automatically based
on LFSR_WIDTH.
LFSR_CONFIG
Specify the LFSR configuration, either Fibonacci or Galois. Fibonacci is generally used
for linear-feedback shift registers (LFSR) for pseudorandom binary sequence (PRBS) generators,
scramblers, and descrambers, while Galois is generally used for cyclic redundancy check
generators and checkers.
Fibonacci style (example for 64b66b scrambler, 0x8000000001)
DIN (LSB first)
|
V
(+)<---------------------------(+)<-----------------------------.
| ^ |
| .----. .----. .----. | .----. .----. .----. |
+->| 0 |->| 1 |->...->| 38 |-+->| 39 |->...->| 56 |->| 57 |--'
| '----' '----' '----' '----' '----' '----'
V
DOUT
Galois style (example for CRC16, 0x8005)
,-------------------+-------------------------+----------(+)<-- DIN (MSB first)
| | | ^
| .----. .----. V .----. .----. V .----. |
`->| 0 |->| 1 |->(+)->| 2 |->...->| 14 |->(+)->| 15 |--+---> DOUT
'----' '----' '----' '----' '----'
LFSR_FEED_FORWARD
Generate feed forward instead of feed back LFSR. Enable this for PRBS checking and self-
synchronous descrambling.
Fibonacci feed-forward style (example for 64b66b descrambler, 0x8000000001)
DIN (LSB first)
|
| .----. .----. .----. .----. .----. .----.
+->| 0 |->| 1 |->...->| 38 |-+->| 39 |->...->| 56 |->| 57 |--.
| '----' '----' '----' | '----' '----' '----' |
| V |
(+)<---------------------------(+)------------------------------'
|
V
DOUT
Galois feed-forward style
,-------------------+-------------------------+------------+--- DIN (MSB first)
| | | |
| .----. .----. V .----. .----. V .----. V
`->| 0 |->| 1 |->(+)->| 2 |->...->| 14 |->(+)->| 15 |->(+)-> DOUT
'----' '----' '----' '----' '----'
REVERSE
Bit-reverse LFSR input and output. Shifts MSB first by default, set REVERSE for LSB first.
DATA_WIDTH
Specify width of input and output data bus. The module will perform one shift per input
data bit, so if the input data bus is not required tie data_in to zero and set DATA_WIDTH
to the required number of shifts per clock cycle.
STYLE
Specify implementation style. Can be "AUTO", "LOOP", or "REDUCTION". When "AUTO"
is selected, implemenation will be "LOOP" or "REDUCTION" based on synthesis translate
directives. "REDUCTION" and "LOOP" are functionally identical, however they simulate
and synthesize differently. "REDUCTION" is implemented with a loop over a Verilog
reduction operator. "LOOP" is implemented as a doubly-nested loop with no reduction
operator. "REDUCTION" is very fast for simulation in iverilog and synthesizes well in
Quartus but synthesizes poorly in ISE, likely due to large inferred XOR gates causing
problems with the optimizer. "LOOP" synthesizes will in both ISE and Quartus. "AUTO"
will default to "REDUCTION" when simulating and "LOOP" for synthesizers that obey
synthesis translate directives.
Settings for common LFSR/CRC implementations:
Name Configuration Length Polynomial Initial value Notes
CRC32 Galois, bit-reverse 32 32'h04c11db7 32'hffffffff Ethernet FCS; invert final output
PRBS6 Fibonacci 6 6'h21 any
PRBS7 Fibonacci 7 7'h41 any
PRBS9 Fibonacci 9 9'h021 any ITU V.52
PRBS10 Fibonacci 10 10'h081 any ITU
PRBS11 Fibonacci 11 11'h201 any ITU O.152
PRBS15 Fibonacci, inverted 15 15'h4001 any ITU O.152
PRBS17 Fibonacci 17 17'h04001 any
PRBS20 Fibonacci 20 20'h00009 any ITU V.57
PRBS23 Fibonacci, inverted 23 23'h040001 any ITU O.151
PRBS29 Fibonacci, inverted 29 29'h08000001 any
PRBS31 Fibonacci, inverted 31 31'h10000001 any
64b66b Fibonacci, bit-reverse 58 58'h8000000001 any 10G Ethernet
128b130b Galois, bit-reverse 23 23'h210125 any PCIe gen 3
*/
reg [LFSR_WIDTH-1:0] lfsr_mask_state[LFSR_WIDTH-1:0];
reg [DATA_WIDTH-1:0] lfsr_mask_data[LFSR_WIDTH-1:0];
reg [LFSR_WIDTH-1:0] output_mask_state[DATA_WIDTH-1:0];
reg [DATA_WIDTH-1:0] output_mask_data[DATA_WIDTH-1:0];
reg [LFSR_WIDTH-1:0] state_val = 0;
reg [DATA_WIDTH-1:0] data_val = 0;
integer i, j, k;
initial begin
// init bit masks
for (i = 0; i < LFSR_WIDTH; i = i + 1) begin
lfsr_mask_state[i] = {LFSR_WIDTH{1'b0}};
lfsr_mask_state[i][i] = 1'b1;
lfsr_mask_data[i] = {DATA_WIDTH{1'b0}};
end
for (i = 0; i < DATA_WIDTH; i = i + 1) begin
output_mask_state[i] = {LFSR_WIDTH{1'b0}};
if (i < LFSR_WIDTH) begin
output_mask_state[i][i] = 1'b1;
end
output_mask_data[i] = {DATA_WIDTH{1'b0}};
end
// simulate shift register
if (LFSR_CONFIG == "FIBONACCI") begin
// Fibonacci configuration
for (i = DATA_WIDTH-1; i >= 0; i = i - 1) begin
// determine shift in value
// current value in last FF, XOR with input data bit (MSB first)
state_val = lfsr_mask_state[LFSR_WIDTH-1];
data_val = lfsr_mask_data[LFSR_WIDTH-1];
data_val = data_val ^ (1 << i);
// add XOR inputs from correct indicies
for (j = 1; j < LFSR_WIDTH; j = j + 1) begin
if (LFSR_POLY & (1 << j)) begin
state_val = lfsr_mask_state[j-1] ^ state_val;
data_val = lfsr_mask_data[j-1] ^ data_val;
end
end
// shift
for (j = LFSR_WIDTH-1; j > 0; j = j - 1) begin
lfsr_mask_state[j] = lfsr_mask_state[j-1];
lfsr_mask_data[j] = lfsr_mask_data[j-1];
end
for (j = DATA_WIDTH-1; j > 0; j = j - 1) begin
output_mask_state[j] = output_mask_state[j-1];
output_mask_data[j] = output_mask_data[j-1];
end
output_mask_state[0] = state_val;
output_mask_data[0] = data_val;
if (LFSR_FEED_FORWARD) begin
// only shift in new input data
state_val = {LFSR_WIDTH{1'b0}};
data_val = 1 << i;
end
lfsr_mask_state[0] = state_val;
lfsr_mask_data[0] = data_val;
end
end else if (LFSR_CONFIG == "GALOIS") begin
// Galois configuration
for (i = DATA_WIDTH-1; i >= 0; i = i - 1) begin
// determine shift in value
// current value in last FF, XOR with input data bit (MSB first)
state_val = lfsr_mask_state[LFSR_WIDTH-1];
data_val = lfsr_mask_data[LFSR_WIDTH-1];
data_val = data_val ^ (1 << i);
// shift
for (j = LFSR_WIDTH-1; j > 0; j = j - 1) begin
lfsr_mask_state[j] = lfsr_mask_state[j-1];
lfsr_mask_data[j] = lfsr_mask_data[j-1];
end
for (j = DATA_WIDTH-1; j > 0; j = j - 1) begin
output_mask_state[j] = output_mask_state[j-1];
output_mask_data[j] = output_mask_data[j-1];
end
output_mask_state[0] = state_val;
output_mask_data[0] = data_val;
if (LFSR_FEED_FORWARD) begin
// only shift in new input data
state_val = {LFSR_WIDTH{1'b0}};
data_val = 1 << i;
end
lfsr_mask_state[0] = state_val;
lfsr_mask_data[0] = data_val;
// add XOR inputs at correct indicies
for (j = 1; j < LFSR_WIDTH; j = j + 1) begin
if (LFSR_POLY & (1 << j)) begin
lfsr_mask_state[j] = lfsr_mask_state[j] ^ state_val;
lfsr_mask_data[j] = lfsr_mask_data[j] ^ data_val;
end
end
end
end else begin
$error("Error: unknown configuration setting!");
$finish;
end
// reverse bits if selected
if (REVERSE) begin
// reverse order
for (i = 0; i < LFSR_WIDTH/2; i = i + 1) begin
state_val = lfsr_mask_state[i];
data_val = lfsr_mask_data[i];
lfsr_mask_state[i] = lfsr_mask_state[LFSR_WIDTH-i-1];
lfsr_mask_data[i] = lfsr_mask_data[LFSR_WIDTH-i-1];
lfsr_mask_state[LFSR_WIDTH-i-1] = state_val;
lfsr_mask_data[LFSR_WIDTH-i-1] = data_val;
end
for (i = 0; i < DATA_WIDTH/2; i = i + 1) begin
state_val = output_mask_state[i];
data_val = output_mask_data[i];
output_mask_state[i] = output_mask_state[DATA_WIDTH-i-1];
output_mask_data[i] = output_mask_data[DATA_WIDTH-i-1];
output_mask_state[DATA_WIDTH-i-1] = state_val;
output_mask_data[DATA_WIDTH-i-1] = data_val;
end
// reverse bits
for (i = 0; i < LFSR_WIDTH; i = i + 1) begin
state_val = 0;
for (j = 0; j < LFSR_WIDTH; j = j + 1) begin
state_val[j] = lfsr_mask_state[i][LFSR_WIDTH-j-1];
end
lfsr_mask_state[i] = state_val;
data_val = 0;
for (j = 0; j < DATA_WIDTH; j = j + 1) begin
data_val[j] = lfsr_mask_data[i][DATA_WIDTH-j-1];
end
lfsr_mask_data[i] = data_val;
end
for (i = 0; i < DATA_WIDTH; i = i + 1) begin
state_val = 0;
for (j = 0; j < LFSR_WIDTH; j = j + 1) begin
state_val[j] = output_mask_state[i][LFSR_WIDTH-j-1];
end
output_mask_state[i] = state_val;
data_val = 0;
for (j = 0; j < DATA_WIDTH; j = j + 1) begin
data_val[j] = output_mask_data[i][DATA_WIDTH-j-1];
end
output_mask_data[i] = data_val;
end
end
// for (i = 0; i < LFSR_WIDTH; i = i + 1) begin
// $display("%b %b", lfsr_mask_state[i], lfsr_mask_data[i]);
// end
end
// synthesis translate_off
`define SIMULATION
// synthesis translate_on
`ifdef SIMULATION
// "AUTO" style is "REDUCTION" for faster simulation
parameter STYLE_INT = (STYLE == "AUTO") ? "REDUCTION" : STYLE;
`else
// "AUTO" style is "LOOP" for better synthesis result
parameter STYLE_INT = (STYLE == "AUTO") ? "LOOP" : STYLE;
`endif
genvar n;
generate
if (STYLE_INT == "REDUCTION") begin
// use Verilog reduction operator
// fast in iverilog
// significantly larger than generated code with ISE (inferred wide XORs may be tripping up optimizer)
// slightly smaller than generated code with Quartus
// --> better for simulation
for (n = 0; n < LFSR_WIDTH; n = n + 1) begin : loop1
assign state_out[n] = ^{(state_in & lfsr_mask_state[n]), (data_in & lfsr_mask_data[n])};
end
for (n = 0; n < DATA_WIDTH; n = n + 1) begin : loop2
assign data_out[n] = ^{(state_in & output_mask_state[n]), (data_in & output_mask_data[n])};
end
end else if (STYLE_INT == "LOOP") begin
// use nested loops
// very slow in iverilog
// slightly smaller than generated code with ISE
// same size as generated code with Quartus
// --> better for synthesis
reg [LFSR_WIDTH-1:0] state_out_reg = 0;
reg [DATA_WIDTH-1:0] data_out_reg = 0;
assign state_out = state_out_reg;
assign data_out = data_out_reg;
always @* begin
for (i = 0; i < LFSR_WIDTH; i = i + 1) begin
state_out_reg[i] = 0;
for (j = 0; j < LFSR_WIDTH; j = j + 1) begin
if (lfsr_mask_state[i][j]) begin
state_out_reg[i] = state_out_reg[i] ^ state_in[j];
end
end
for (j = 0; j < DATA_WIDTH; j = j + 1) begin
if (lfsr_mask_data[i][j]) begin
state_out_reg[i] = state_out_reg[i] ^ data_in[j];
end
end
end
for (i = 0; i < DATA_WIDTH; i = i + 1) begin
data_out_reg[i] = 0;
for (j = 0; j < LFSR_WIDTH; j = j + 1) begin
if (output_mask_state[i][j]) begin
data_out_reg[i] = data_out_reg[i] ^ state_in[j];
end
end
for (j = 0; j < DATA_WIDTH; j = j + 1) begin
if (output_mask_data[i][j]) begin
data_out_reg[i] = data_out_reg[i] ^ data_in[j];
end
end
end
end
end else begin
initial begin
$error("Error: unknown style setting!");
$finish;
end
end
endgenerate
endmodule
|
// =============================================================================
// COPYRIGHT NOTICE
// Copyright 2006 (c) Lattice Semiconductor Corporation
// ALL RIGHTS RESERVED
// This confidential and proprietary software may be used only as authorised by
// a licensing agreement from Lattice Semiconductor Corporation.
// The entire notice above must be reproduced on all authorized copies and
// copies may only be made to the extent permitted by a licensing agreement from
// Lattice Semiconductor Corporation.
//
// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
// 5555 NE Moore Court 408-826-6000 (other locations)
// Hillsboro, OR 97124 web : http://www.latticesemi.com/
// U.S.A email: [email protected]
// =============================================================================/
// FILE DETAILS
// Project : LatticeMico32
// File : TYPEB.v
// Description:
// This is one of the two types of cells that are used to create ER1/ER2
// register bits.
// Dependencies : None
// Version : 6.1.17
// Modified typeb module to remove redundant DATA_OUT port.
// Version : 7.0SP2, 3.0
// : No Change
// Version : 3.1
// : No Change
// =============================================================================
module TYPEB
(
input CLK,
input RESET_N,
input CLKEN,
input TDI,
output TDO,
input DATA_IN,
input CAPTURE_DR
);
reg tdoInt;
always @ (negedge CLK or negedge RESET_N)
begin
if (RESET_N== 1'b0)
tdoInt <= 1'b0;
else if (CLK == 1'b0)
if (CLKEN==1'b1)
if (CAPTURE_DR==1'b0)
tdoInt <= TDI;
else
tdoInt <= DATA_IN;
end
assign TDO = tdoInt;
endmodule
|
//
// LogicProbe.v -- on-chip logic probe with trace memory and read-out facility
//
`timescale 1ns/1ns
module LogicProbe(clock, reset, trigger, sample, channels, serial_out);
input clock;
input reset;
input trigger;
input sample;
input [127:0] channels;
output serial_out;
wire full;
reg [12:0] rdaddr;
wire [7:0] data;
reg write;
wire ready;
reg done;
reg state;
LogicProbe_sampler
sampler(clock, reset, trigger, sample, channels, full, rdaddr, data);
LogicProbe_xmtbuf
xmtbuf(clock, reset, write, ready, data, serial_out);
always @(posedge clock) begin
if (reset == 1) begin
rdaddr <= 13'd0;
write <= 0;
done <= 0;
state <= 0;
end else begin
if (full == 1 && done == 0) begin
if (state == 0) begin
if (ready == 1) begin
state <= 1;
write <= 1;
end
end else begin
if (rdaddr == 13'd8191) begin
done <= 1;
end
state <= 0;
write <= 0;
rdaddr <= rdaddr + 1;
end
end
end
end
endmodule
module LogicProbe_sampler(clock, reset, trigger, sample,
data_in, full, rdaddr, data_out);
input clock;
input reset;
input trigger;
input sample;
input [127:0] data_in;
output reg full;
input [12:0] rdaddr;
output reg [7:0] data_out;
reg [31:0] mem3[0:511];
reg [31:0] mem2[0:511];
reg [31:0] mem1[0:511];
reg [31:0] mem0[0:511];
reg [8:0] wraddr;
wire [8:0] addr;
reg [31:0] data3;
reg [31:0] data2;
reg [31:0] data1;
reg [31:0] data0;
reg [3:0] muxctrl;
reg triggered;
// addr for trace memory
// full == 0 means data capture
// full == 1 means data readout
assign addr = (full == 0) ? wraddr: rdaddr[12:4];
// pipeline register for output mux control: necessary
// because the trace memory has one clock delay too
always @(posedge clock) begin
muxctrl <= rdaddr[3:0];
end
// output multiplexer
always @(*) begin
case (muxctrl)
4'h0: data_out = data3[31:24];
4'h1: data_out = data3[23:16];
4'h2: data_out = data3[15: 8];
4'h3: data_out = data3[ 7: 0];
4'h4: data_out = data2[31:24];
4'h5: data_out = data2[23:16];
4'h6: data_out = data2[15: 8];
4'h7: data_out = data2[ 7: 0];
4'h8: data_out = data1[31:24];
4'h9: data_out = data1[23:16];
4'hA: data_out = data1[15: 8];
4'hB: data_out = data1[ 7: 0];
4'hC: data_out = data0[31:24];
4'hD: data_out = data0[23:16];
4'hE: data_out = data0[15: 8];
4'hF: data_out = data0[ 7: 0];
endcase
end
// trace memory
always @(posedge clock) begin
if (full == 0) begin
mem3[addr] <= data_in[127:96];
mem2[addr] <= data_in[ 95:64];
mem1[addr] <= data_in[ 63:32];
mem0[addr] <= data_in[ 31: 0];
end
data3 <= mem3[addr];
data2 <= mem2[addr];
data1 <= mem1[addr];
data0 <= mem0[addr];
end
// state machine which fills trace memory after trigger occurred
// it takes one sample per clock tick, but only when sample == 1
always @(posedge clock) begin
if (reset == 1) begin
wraddr <= 9'd0;
triggered <= 0;
full <= 0;
end else begin
if (triggered == 1) begin
// capture data, but only when sample == 1
if (sample == 1) begin
if (wraddr == 9'd511) begin
// last sample, memory is full
full <= 1;
end else begin
wraddr <= wraddr + 1;
end
end
end else begin
// wait for trigger, possibly capture first sample
if (trigger == 1) begin
triggered <= 1;
if (sample == 1) begin
wraddr <= wraddr + 1;
end
end
end
end
end
endmodule
module LogicProbe_xmtbuf(clock, reset, write, ready, data_in, serial_out);
input clock;
input reset;
input write;
output reg ready;
input [7:0] data_in;
output serial_out;
reg [1:0] state;
reg [7:0] data_hold;
reg load;
wire empty;
LogicProbe_xmt xmt(clock, reset, load, empty, data_hold, serial_out);
always @(posedge clock) begin
if (reset == 1) begin
state <= 2'b00;
ready <= 1;
load <= 0;
end else begin
case (state)
2'b00:
begin
if (write == 1) begin
state <= 2'b01;
data_hold <= data_in;
ready <= 0;
load <= 1;
end
end
2'b01:
begin
state <= 2'b10;
ready <= 1;
load <= 0;
end
2'b10:
begin
if (empty == 1 && write == 0) begin
state <= 2'b00;
ready <= 1;
load <= 0;
end else
if (empty == 1 && write == 1) begin
state <= 2'b01;
data_hold <= data_in;
ready <= 0;
load <= 1;
end else
if (empty == 0 && write == 1) begin
state <= 2'b11;
data_hold <= data_in;
ready <= 0;
load <= 0;
end
end
2'b11:
begin
if (empty == 1) begin
state <= 2'b01;
ready <= 0;
load <= 1;
end
end
endcase
end
end
endmodule
module LogicProbe_xmt(clock, reset, load, empty, parallel_in, serial_out);
input clock;
input reset;
input load;
output reg empty;
input [7:0] parallel_in;
output serial_out;
reg [3:0] state;
reg [8:0] shift;
reg [10:0] count;
assign serial_out = shift[0];
always @(posedge clock) begin
if (reset == 1) begin
state <= 4'h0;
shift <= 9'b111111111;
empty <= 1;
end else begin
if (state == 4'h0) begin
if (load == 1) begin
state <= 4'h1;
shift <= { parallel_in, 1'b0 };
count <= 1302;
empty <= 0;
end
end else
if (state == 4'hb) begin
state <= 4'h0;
empty <= 1;
end else begin
if (count == 0) begin
state <= state + 1;
shift[8:0] <= { 1'b1, shift[8:1] };
count <= 1302;
end else begin
count <= count - 1;
end
end
end
end
endmodule
|
/*
* pll.v: Simulates the pll of the xilinx 7 series. This is used by the
* frontend files "plle2_base.v" and "plle2_adv.v"
* author: Till Mahlburg
* year: 2019-2020
* organization: Universität Leipzig
* license: ISC
*
*/
`timescale 1 ns / 1 ps
/* A reference for the interface can be found in Xilinx UG953 page 503ff */
module pll #(
/* not implemented */
parameter BANDWIDTH = "OPTIMIZED",
parameter CLKFBOUT_MULT_F = 5.0,
parameter CLKFBOUT_PHASE = 0.0,
/* need to be set */
parameter CLKIN1_PERIOD = 0.0,
parameter CLKIN2_PERIOD = 0.0,
parameter CLKOUT0_DIVIDE_F = 1.0,
parameter CLKOUT1_DIVIDE = 1,
parameter CLKOUT2_DIVIDE = 1,
parameter CLKOUT3_DIVIDE = 1,
parameter CLKOUT4_DIVIDE = 1,
parameter CLKOUT5_DIVIDE = 1,
parameter CLKOUT6_DIVIDE = 1,
parameter CLKOUT0_DUTY_CYCLE = 0.5,
parameter CLKOUT1_DUTY_CYCLE = 0.5,
parameter CLKOUT2_DUTY_CYCLE = 0.5,
parameter CLKOUT3_DUTY_CYCLE = 0.5,
parameter CLKOUT4_DUTY_CYCLE = 0.5,
parameter CLKOUT5_DUTY_CYCLE = 0.5,
parameter CLKOUT6_DUTY_CYCLE = 0.5,
parameter CLKOUT0_PHASE = 0.0,
parameter CLKOUT1_PHASE = 0.0,
parameter CLKOUT2_PHASE = 0.0,
parameter CLKOUT3_PHASE = 0.0,
parameter CLKOUT4_PHASE = 0.0,
parameter CLKOUT5_PHASE = 0.0,
parameter CLKOUT6_PHASE = 0.0,
parameter CLKOUT4_CASCADE = "FALSE",
parameter DIVCLK_DIVIDE = 1,
/* not implemented */
parameter REF_JITTER1 = 0.010,
parameter REF_JITTER2 = 0.010,
parameter STARTUP_WAIT = "FALSE",
parameter COMPENSATION = "ZHOLD",
/* this is additional, optional information for determining the
* correct hardware limits. By default it uses the most restrictive
* model */
parameter FPGA_TYPE = "ARTIX",
parameter SPEED_GRADE = "-1",
/* just for internal use */
parameter MODULE_TYPE = "PLLE2_BASE")(
output CLKOUT0,
output CLKOUT0B,
output CLKOUT1,
output CLKOUT1B,
output CLKOUT2,
output CLKOUT2B,
output CLKOUT3,
output CLKOUT3B,
output CLKOUT4,
output CLKOUT5,
output CLKOUT6,
/* PLL feedback output. */
output CLKFBOUT,
output CLKFBOUTB,
output LOCKED,
input CLKIN1,
input CLKIN2,
/* Select input clk. 1 for CLKIN1, 0 for CLKIN2 */
input CLKINSEL,
/* PLL feedback input. Is ignored in this implementation, but should be connected to CLKFBOUT for internal feedback. */
input CLKFBIN,
/* Used to power down instatiated but unused PLLs */
input PWRDWN,
input RST,
/* Dynamic reconfiguration ports */
/* register address to write to or read from */
input [6:0] DADDR,
/* reference clk */
input DCLK,
/* enable dynamic reconfiguration (read only) */
input DEN,
/* enable writing */
input DWE,
/* what to write */
input [15:0] DI,
/* read values */
output [15:0] DO,
/* ready flag for next operation */
output DRDY);
/* assign inverted outputs */
assign CLKOUT0B = ~CLKOUT0;
assign CLKOUT1B = ~CLKOUT1;
assign CLKOUT2B = ~CLKOUT2;
assign CLKOUT3B = ~CLKOUT3;
assign CLKFBOUTB = ~CLKFBOUT;
/* gets assigned to the chosen CLKIN */
reg clkin;
wire [31:0] clkin_period_length_1000;
/* internal values */
reg [31:0] CLKOUT_DIVIDE_INT_1000[0:6];
reg [31:0] CLKOUT_DUTY_CYCLE_INT_1000[0:6];
reg signed [31:0] CLKOUT_PHASE_INT_1000[0:6];
reg [31:0] CLKFBOUT_MULT_F_INT_1000;
reg signed [31:0] CLKFBOUT_PHASE_INT_1000;
reg [31:0] DIVCLK_DIVIDE_INT;
wire CLKOUT_INT[0:6];
assign CLKOUT0 = CLKOUT_INT[0];
assign CLKOUT1 = CLKOUT_INT[1];
assign CLKOUT2 = CLKOUT_INT[2];
assign CLKOUT3 = CLKOUT_INT[3];
assign CLKOUT4 = CLKOUT_INT[4];
assign CLKOUT5 = CLKOUT_INT[5];
assign CLKOUT6 = CLKOUT_INT[6];
/* Used to determine the period length of the divided CLK */
period_count #(
.RESOLUTION(0.01))
period_count (
.RST(RST),
.PWRDWN(PWRDWN),
.clk(clkin),
.period_length_1000(clkin_period_length_1000));
wire period_stable;
/* Used to delay the output of the period until it's stable */
period_check period_check (
.RST(RST),
.PWRDWN(PWRDWN),
.clk(clkin),
.period_length((clkin_period_length_1000 / 1000.0)),
.period_stable(period_stable));
wire out[0:6];
wire [31:0] out_period_length_1000[0:6];
wire lock[0:6];
/* frequency generators */
genvar i;
generate
for (i = 0; i <= 6; i = i + 1) begin : fg
freq_gen fg (
.M_1000(CLKFBOUT_MULT_F_INT_1000),
.D(DIVCLK_DIVIDE_INT),
.O_1000(CLKOUT_DIVIDE_INT_1000[i]),
.RST(RST),
.PWRDWN(PWRDWN),
.period_stable(period_stable),
.ref_period_1000((clkin_period_length_1000)),
.clk(clkin),
.out(out[i]),
.out_period_length_1000(out_period_length_1000[i]));
end
endgenerate
/* phase shift */
generate
for (i = 0; i <= 6; i = i + 1) begin : ps
phase_shift ps (
.RST(RST),
.PWRDWN(PWRDWN),
.clk(out[i]),
.shift_1000(CLKOUT_PHASE_INT_1000[i] + CLKFBOUT_PHASE_INT_1000),
.duty_cycle(CLKOUT_DUTY_CYCLE_INT_1000[i] / 10),
.clk_period_1000(out_period_length_1000[i]),
.lock(lock[i]),
.clk_shifted(CLKOUT_INT[i]));
end
endgenerate
wire fb_out;
wire [31:0] fb_out_period_length_1000;
wire fb_lock;
/* CLKOUTFB */
freq_gen fb_fg (
.M_1000(CLKFBOUT_MULT_F_INT_1000),
.D(DIVCLK_DIVIDE_INT),
.O_1000(1000.0),
.RST(RST),
.PWRDWN(PWRDWN),
.period_stable(period_stable),
.ref_period_1000((clkin_period_length_1000)),
.clk(clkin),
.out(fb_out),
.out_period_length_1000(fb_out_period_length_1000));
phase_shift fb_ps (
.RST(RST),
.PWRDWN(PWRDWN),
.clk(fb_out),
.shift_1000(CLKFBOUT_PHASE_INT_1000),
.clk_period_1000(fb_out_period_length_1000),
.duty_cycle(50),
.lock(fb_lock),
.clk_shifted(CLKFBOUT));
/* dynamically set values */
wire [31:0] CLKOUT_DIVIDE_DYN[0:6];
wire [31:0] CLKOUT_DUTY_CYCLE_DYN_1000[0:6];
wire signed [31:0] CLKOUT_PHASE_DYN[0:6];
wire [31:0] CLKFBOUT_MULT_F_DYN_1000;
wire signed [31:0] CLKFBOUT_PHASE_DYN;
wire [31:0] DIVCLK_DIVIDE_DYN;
/* reconfiguration */
dyn_reconf dyn_reconf (
.RST(RST),
.PWRDWN(PWRDWN),
.vco_period_1000(fb_out_period_length_1000),
.DADDR(DADDR),
.DCLK(DCLK),
.DEN(DEN),
.DWE(DWE),
.DI(DI),
.DO(DO),
.DRDY(DRDY),
.CLKOUT0_DIVIDE(CLKOUT_DIVIDE_DYN[0]),
.CLKOUT0_DUTY_CYCLE_1000(CLKOUT_DUTY_CYCLE_DYN_1000[0]),
.CLKOUT0_PHASE(CLKOUT_PHASE_DYN[0]),
.CLKOUT1_DIVIDE(CLKOUT_DIVIDE_DYN[1]),
.CLKOUT1_DUTY_CYCLE_1000(CLKOUT_DUTY_CYCLE_DYN_1000[1]),
.CLKOUT1_PHASE(CLKOUT_PHASE_DYN[1]),
.CLKOUT2_DIVIDE(CLKOUT_DIVIDE_DYN[2]),
.CLKOUT2_DUTY_CYCLE_1000(CLKOUT_DUTY_CYCLE_DYN_1000[2]),
.CLKOUT2_PHASE(CLKOUT_PHASE_DYN[2]),
.CLKOUT3_DIVIDE(CLKOUT_DIVIDE_DYN[3]),
.CLKOUT3_DUTY_CYCLE_1000(CLKOUT_DUTY_CYCLE_DYN_1000[3]),
.CLKOUT3_PHASE(CLKOUT_PHASE_DYN[3]),
.CLKOUT4_DIVIDE(CLKOUT_DIVIDE_DYN[4]),
.CLKOUT4_DUTY_CYCLE_1000(CLKOUT_DUTY_CYCLE_DYN_1000[4]),
.CLKOUT4_PHASE(CLKOUT_PHASE_DYN[4]),
.CLKOUT5_DIVIDE(CLKOUT_DIVIDE_DYN[5]),
.CLKOUT5_DUTY_CYCLE_1000(CLKOUT_DUTY_CYCLE_DYN_1000[5]),
.CLKOUT5_PHASE(CLKOUT_PHASE_DYN[5]),
.CLKOUT6_DIVIDE(CLKOUT_DIVIDE_DYN[6]),
.CLKOUT6_DUTY_CYCLE_1000(CLKOUT_DUTY_CYCLE_DYN_1000[6]),
.CLKOUT6_PHASE(CLKOUT_PHASE_DYN[6]),
.CLKFBOUT_MULT_F_1000(CLKFBOUT_MULT_F_DYN_1000),
.CLKFBOUT_PHASE(CLKFBOUT_PHASE_DYN),
.DIVCLK_DIVIDE(DIVCLK_DIVIDE_DYN));
/* lock detection using the lock information given by the phase shift modules */
assign LOCKED = lock[0] & lock[1] & lock[2] & lock[3] & lock[4] & lock[5] & lock[6] & fb_lock;
/* set clkin to the correct CLKIN */
always @* begin
if (CLKINSEL === 1'b1) begin
clkin = CLKIN1;
end else if (CLKINSEL === 1'b0) begin
clkin = CLKIN2;
end
end
integer k;
/* set the internal values to the dynamically set */
always @* begin
for (k = 0; k <= 6; k = k + 1) begin
if (CLKOUT_DIVIDE_DYN[k] != 0)
CLKOUT_DIVIDE_INT_1000[k] = CLKOUT_DIVIDE_DYN[k] * 1000;
if (CLKOUT_DUTY_CYCLE_DYN_1000[k] != 0)
CLKOUT_DUTY_CYCLE_INT_1000[k] = CLKOUT_DUTY_CYCLE_DYN_1000[k];
if (CLKOUT_PHASE_DYN[k] != 0)
CLKOUT_PHASE_INT_1000[k] = CLKOUT_PHASE_DYN[k] * 1000;
end
if (CLKFBOUT_MULT_F_DYN_1000 != 0)
CLKFBOUT_MULT_F_INT_1000 = CLKFBOUT_MULT_F_DYN_1000;
if (CLKFBOUT_PHASE_DYN != 0)
CLKFBOUT_PHASE_INT_1000 = CLKFBOUT_PHASE_DYN * 1000;
if (DIVCLK_DIVIDE_DYN != 0)
DIVCLK_DIVIDE_INT = DIVCLK_DIVIDE_DYN;
end
/* assign initial values */
integer vco_min;
integer vco_max;
initial begin
CLKOUT_DIVIDE_INT_1000[0] = CLKOUT0_DIVIDE_F * 1000;
CLKOUT_DIVIDE_INT_1000[1] = CLKOUT1_DIVIDE * 1000;
CLKOUT_DIVIDE_INT_1000[2] = CLKOUT2_DIVIDE * 1000;
CLKOUT_DIVIDE_INT_1000[3] = CLKOUT3_DIVIDE * 1000;
if (CLKOUT4_CASCADE == "FALSE") begin
CLKOUT_DIVIDE_INT_1000[4] = CLKOUT4_DIVIDE * 1000;
CLKOUT_DIVIDE_INT_1000[6] = CLKOUT6_DIVIDE * 1000;
end else if (CLKOUT4_CASCADE == "TRUE") begin
CLKOUT_DIVIDE_INT_1000[4] = CLKOUT4_DIVIDE * CLKOUT6_DIVIDE * 1000;
CLKOUT_DIVIDE_INT_1000[6] = 1000;
end
CLKOUT_DIVIDE_INT_1000[5] = CLKOUT5_DIVIDE * 1000;
CLKOUT_DUTY_CYCLE_INT_1000[0] = CLKOUT0_DUTY_CYCLE * 1000;
CLKOUT_DUTY_CYCLE_INT_1000[1] = CLKOUT1_DUTY_CYCLE * 1000;
CLKOUT_DUTY_CYCLE_INT_1000[2] = CLKOUT2_DUTY_CYCLE * 1000;
CLKOUT_DUTY_CYCLE_INT_1000[3] = CLKOUT3_DUTY_CYCLE * 1000;
CLKOUT_DUTY_CYCLE_INT_1000[4] = CLKOUT4_DUTY_CYCLE * 1000;
CLKOUT_DUTY_CYCLE_INT_1000[5] = CLKOUT5_DUTY_CYCLE * 1000;
CLKOUT_DUTY_CYCLE_INT_1000[6] = CLKOUT6_DUTY_CYCLE * 1000;
CLKOUT_PHASE_INT_1000[0] = CLKOUT0_PHASE * 1000;
CLKOUT_PHASE_INT_1000[1] = CLKOUT1_PHASE * 1000;
CLKOUT_PHASE_INT_1000[2] = CLKOUT2_PHASE * 1000;
CLKOUT_PHASE_INT_1000[3] = CLKOUT3_PHASE * 1000;
CLKOUT_PHASE_INT_1000[4] = CLKOUT4_PHASE * 1000;
CLKOUT_PHASE_INT_1000[5] = CLKOUT5_PHASE * 1000;
CLKOUT_PHASE_INT_1000[6] = CLKOUT6_PHASE * 1000;
CLKFBOUT_MULT_F_INT_1000 = CLKFBOUT_MULT_F * 1000;
CLKFBOUT_PHASE_INT_1000 = CLKFBOUT_PHASE * 1000;
DIVCLK_DIVIDE_INT = DIVCLK_DIVIDE;
/* set up limits correctly */
case (FPGA_TYPE)
"ARTIX":
case (SPEED_GRADE)
"-3": if (MODULE_TYPE == "PLLE2_ADV" || MODULE_TYPE == "PLLE2_BASE") begin
vco_min = 800;
vco_max = 2133;
end else if (MODULE_TYPE == "MMCME2_BASE") begin
vco_min = 600;
vco_max = 1600;
end
"-2": if (MODULE_TYPE == "PLLE2_ADV" || MODULE_TYPE == "PLLE2_BASE") begin
vco_min = 800;
vco_max = 1866;
end else if (MODULE_TYPE == "MMCME2_BASE") begin
vco_min = 600;
vco_max = 1440;
end
"-1", "-1LI", "-2LE": if (MODULE_TYPE == "PLLE2_ADV" || MODULE_TYPE == "PLLE2_BASE") begin
vco_min = 800;
vco_max = 1600;
end else if (MODULE_TYPE == "MMCME2_BASE") begin
vco_min = 600;
vco_max = 1200;
end
default: begin
$display("The speed grade given is not valid. Please choose one of the following: -3, -2, -2LE, -1, -1LI");
$display("Exiting simulation...");
$finish;
end
endcase
"KINTEX":
case (SPEED_GRADE)
"-3": if (MODULE_TYPE == "PLLE2_ADV" || MODULE_TYPE == "PLLE2_BASE") begin
vco_min = 800;
vco_max = 2133;
end else if (MODULE_TYPE == "MMCME2_BASE") begin
vco_min = 600;
vco_max = 1600;
end
"-2", "-2LI": if (MODULE_TYPE == "PLLE2_ADV" || MODULE_TYPE == "PLLE2_BASE") begin
vco_min = 800;
vco_max = 1866;
end else if (MODULE_TYPE == "MMCME2_BASE") begin
vco_min = 600;
vco_max = 1440;
end
"-1", "-1M", "-1LM", "-1Q", "-2LE": if (MODULE_TYPE == "PLLE2_ADV" || MODULE_TYPE == "PLLE2_BASE") begin
vco_min = 800;
vco_max = 1600;
end else if (MODULE_TYPE == "MMCME2_BASE") begin
vco_min = 600;
vco_max = 1200;
end
default: begin
$display("The speed grade given is not valid. Please choose one of the following: -3, -2, -2LI, -2LE, -1, -1M, -1LM, -1Q");
$display("Exiting simulation...");
$finish;
end
endcase
"VIRTEX":
case (SPEED_GRADE)
"-3": if (MODULE_TYPE == "PLLE2_ADV" || MODULE_TYPE == "PLLE2_BASE") begin
vco_min = 800;
vco_max = 2133;
end else if (MODULE_TYPE == "MMCME2_BASE") begin
vco_min = 600;
vco_max = 1600;
end
"-2", "-2L", "-2LG": if (MODULE_TYPE == "PLLE2_ADV" || MODULE_TYPE == "PLLE2_BASE") begin
vco_min = 800;
vco_max = 1833;
end else if (MODULE_TYPE == "MMCME2_BASE") begin
vco_min = 600;
vco_max = 1440;
end
"-1", "-1M": if (MODULE_TYPE == "PLLE2_ADV" || MODULE_TYPE == "PLLE2_BASE") begin
vco_min = 800;
vco_max = 1600;
end else if (MODULE_TYPE == "MMCME2_BASE") begin
vco_min = 600;
vco_max = 1200;
end
default: begin
$display("The speed grade given is not valid. Please choose one of the following: -3, -2, -2L, -2LG, -1, -1M");
$display("Exiting simulation...");
$finish;
end
endcase
default: begin
$display("The FPGA type given is not recognized. Please choose one of the following: ARTIX, VIRTEX, KINTEX");
$display("Exiting simulation...");
$finish;
end
endcase
end
integer l;
reg invalid = 1'b0;
/* check values for validity */
always @(*) begin
/* the same for each version of the pll/mmcm */
if (!(BANDWIDTH == "OPTIMIZED" || BANDWIDTH == "HIGH" || BANDWIDTH == "LOW")) begin
$display("BANDWIDTH doesn't match any of its allowed inputs.");
invalid = 1'b1;
end else if (CLKIN1_PERIOD < 0.000 || CLKIN1_PERIOD > 52.631) begin
$display("CLKIN1_PERIOD is not in the allowed range (0 - 52.631).");
invalid = 1'b1;
end else if (CLKIN2_PERIOD < 0.000 || CLKIN2_PERIOD > 52.631) begin
$display("CLKIN2_PERIOD is not in the allowed range (0 - 52.631).");
invalid = 1'b1;
end else if (CLKFBOUT_PHASE_INT_1000 < -360000 || CLKFBOUT_PHASE_INT_1000 > 360000) begin
$display("CLKFBOUT_PHASE is not in the allowed range (-360-360).");
invalid = 1'b1;
end else if (DIVCLK_DIVIDE_INT < 1 || DIVCLK_DIVIDE_INT > 56) begin
$display("DIVCLK_DIVIDE is not in the allowed range (1-56).");
invalid = 1'b1;
end else if (REF_JITTER1 < 0.000 || REF_JITTER1 > 0.999) begin
$display("REF_JITTER1 is not in the allowed range (0.000 - 0.999).");
invalid = 1'b1;
end else if (REF_JITTER2 < 0.000 || REF_JITTER2 > 0.999) begin
$display("REF_JITTER2 is not in the allowed range (0.000 - 0.999).");
invalid = 1'b1;
end else if (!(STARTUP_WAIT == "FALSE" || STARTUP_WAIT == "TRUE")) begin
$display("STARTUP_WAIT doesn't match any of its allowed inputs");
invalid = 1'b1;
end else if (!(COMPENSATION == "ZHOLD" || COMPENSATION == "BUF_IN" || COMPENSATION == "EXTERNAL" || COMPENSATION == "INTERNAL")) begin
$display("COMPENSATION doesn't match any of its allowed inputs");
invalid = 1'b1;
end else if (!(CLKOUT4_CASCADE == "TRUE" || CLKOUT4_CASCADE == "FALSE")) begin
$display("CLKOUT4_CASCADE doesn't match any of its allowed inputs");
invalid = 1'b1;
end
for (l = 0; l <= 6; l = l + 1) begin
if (l != 0) begin
if ((CLKOUT_DIVIDE_INT_1000[l] / 1000.0) < 1 || (CLKOUT_DIVIDE_INT_1000[l] / 1000.0) > 128 || ((((CLKOUT_DIVIDE_INT_1000[l] / 1000.0) - $floor((CLKOUT_DIVIDE_INT_1000[l] / 1000.0)) > 0.001)))) begin
$display("CLKOUT%0d_DIVIDE is not in the allowed range (1-128) or it is a floating point number", l);
invalid = 1'b1;
end
end
if (CLKOUT_DUTY_CYCLE_INT_1000[l] < 1 || CLKOUT_DUTY_CYCLE_INT_1000[l] > 999) begin
$display("CLKOUT%0d_DUTY_CYCLE is not in the allowed range(0.001-0.999)", l);
invalid = 1'b1;
end else if (CLKOUT_PHASE_INT_1000[l] < -360000 || CLKOUT_PHASE_INT_1000[l] > 360000) begin
$display("CLKOUT%0d_PHASE is not in the allowed range(-360.000-360.000)", l);
invalid = 1'b1;
end
end
/* different on pll and mmcm */
if (MODULE_TYPE == "PLLE2_BASE" || MODULE_TYPE == "PLLE2_ADV") begin
if (CLKFBOUT_MULT_F_INT_1000 < 2000 || CLKFBOUT_MULT_F_INT_1000 > 64000 || ((CLKFBOUT_MULT_F_INT_1000 / 1000.0) - $floor((CLKFBOUT_MULT_F_INT_1000 / 1000.0)) > 0.001)) begin
$display("CLKFBOUT_MULT is not in the allowed range (2-64) or a floating point number.");
invalid = 1'b1;
end else if ((CLKOUT_DIVIDE_INT_1000[0] / 1000.0) < 1 || (CLKOUT_DIVIDE_INT_1000[0] / 1000.0) > 128 || (((CLKOUT_DIVIDE_INT_1000[0] / 1000.0) - $floor((CLKOUT_DIVIDE_INT_1000[0] / 1000.0)) > 0.001))) begin
$display("CLKOUT0_DIVIDE is not in the allowed range (1-128) or it is a floating point number");
invalid = 1'b1;
end
end else if (MODULE_TYPE == "MMCME2_BASE") begin
if (CLKFBOUT_MULT_F_INT_1000 < 2000 || CLKFBOUT_MULT_F_INT_1000 > 64000) begin
$display("CLKFBOUT_MULT_F is not in the allowed range (2.000-64.000)");
invalid = 1'b1;
end else if (CLKOUT_DIVIDE_INT_1000[0] < 1000 || CLKOUT_DIVIDE_INT_1000[0] > 128000) begin
$display("CLKOUT0_DIVIDE_F is not in the allowed range(2.000-64.000)");
invalid = 1'b1;
end
end
if (CLKINSEL == 1 && ((CLKFBOUT_MULT_F_INT_1000 / (CLKIN1_PERIOD * 1.0 * DIVCLK_DIVIDE)) < vco_min || (CLKFBOUT_MULT_F_INT_1000 / (CLKIN1_PERIOD * 1.0 * DIVCLK_DIVIDE_INT)) > vco_max)) begin
$display("The calculated VCO frequency is not in the allowed range (%0d-%0d). Change either CLKFBOUT_MULT_F, CLKIN1_PERIOD or DIVCLK_DIVIDE to an appropiate value.", vco_min, vco_max);
$display("To calculate the VCO frequency use this formula: (CLKFBOUT_MULT_F * 1000) / (CLKIN1_PERIOD * DIVCLK_DIVIDE).");
$display("Currently the value is %0f.", (CLKFBOUT_MULT_F_INT_1000 / (CLKIN1_PERIOD * 1.0 * DIVCLK_DIVIDE_INT)));
invalid = 1'b1;
end else if (CLKINSEL == 0 && ((CLKFBOUT_MULT_F_INT_1000 / (CLKIN2_PERIOD * 1.0 * DIVCLK_DIVIDE)) < vco_min || (CLKFBOUT_MULT_F_INT_1000 / (CLKIN2_PERIOD * 1.0 * DIVCLK_DIVIDE_INT)) > vco_max)) begin
$display("The calculated VCO frequency is not in the allowed range (%0d-%0d). Change either CLKFBOUT_MULT_F, CLKIN2_PERIOD or DIVCLK_DIVIDE to an appropiate value.", vco_min, vco_max);
$display("To calculate the VCO frequency use this formula: (CLKFBOUT_MULT_F * 1000) / (CLKIN2_PERIOD * DIVCLK_DIVIDE).");
$display("Currently the value is %0f.", (CLKFBOUT_MULT_F_INT_1000 / (CLKIN2_PERIOD * 1.0 * DIVCLK_DIVIDE_INT)));
invalid = 1'b1;
end
/* NOTE: delete this to simulate even if there are invalid values */
if (invalid) begin
$display("Exiting simulation...");
$finish;
end
end
endmodule
|
// ledtest_hps_0.v
// This file was auto-generated from altera_hps_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 17.0 595
`timescale 1 ps / 1 ps
module ledtest_hps_0 #(
parameter F2S_Width = 0,
parameter S2F_Width = 0
) (
output wire h2f_rst_n, // h2f_reset.reset_n
input wire h2f_lw_axi_clk, // h2f_lw_axi_clock.clk
output wire [11:0] h2f_lw_AWID, // h2f_lw_axi_master.awid
output wire [20:0] h2f_lw_AWADDR, // .awaddr
output wire [3:0] h2f_lw_AWLEN, // .awlen
output wire [2:0] h2f_lw_AWSIZE, // .awsize
output wire [1:0] h2f_lw_AWBURST, // .awburst
output wire [1:0] h2f_lw_AWLOCK, // .awlock
output wire [3:0] h2f_lw_AWCACHE, // .awcache
output wire [2:0] h2f_lw_AWPROT, // .awprot
output wire h2f_lw_AWVALID, // .awvalid
input wire h2f_lw_AWREADY, // .awready
output wire [11:0] h2f_lw_WID, // .wid
output wire [31:0] h2f_lw_WDATA, // .wdata
output wire [3:0] h2f_lw_WSTRB, // .wstrb
output wire h2f_lw_WLAST, // .wlast
output wire h2f_lw_WVALID, // .wvalid
input wire h2f_lw_WREADY, // .wready
input wire [11:0] h2f_lw_BID, // .bid
input wire [1:0] h2f_lw_BRESP, // .bresp
input wire h2f_lw_BVALID, // .bvalid
output wire h2f_lw_BREADY, // .bready
output wire [11:0] h2f_lw_ARID, // .arid
output wire [20:0] h2f_lw_ARADDR, // .araddr
output wire [3:0] h2f_lw_ARLEN, // .arlen
output wire [2:0] h2f_lw_ARSIZE, // .arsize
output wire [1:0] h2f_lw_ARBURST, // .arburst
output wire [1:0] h2f_lw_ARLOCK, // .arlock
output wire [3:0] h2f_lw_ARCACHE, // .arcache
output wire [2:0] h2f_lw_ARPROT, // .arprot
output wire h2f_lw_ARVALID, // .arvalid
input wire h2f_lw_ARREADY, // .arready
input wire [11:0] h2f_lw_RID, // .rid
input wire [31:0] h2f_lw_RDATA, // .rdata
input wire [1:0] h2f_lw_RRESP, // .rresp
input wire h2f_lw_RLAST, // .rlast
input wire h2f_lw_RVALID, // .rvalid
output wire h2f_lw_RREADY, // .rready
output wire [14:0] mem_a, // memory.mem_a
output wire [2:0] mem_ba, // .mem_ba
output wire mem_ck, // .mem_ck
output wire mem_ck_n, // .mem_ck_n
output wire mem_cke, // .mem_cke
output wire mem_cs_n, // .mem_cs_n
output wire mem_ras_n, // .mem_ras_n
output wire mem_cas_n, // .mem_cas_n
output wire mem_we_n, // .mem_we_n
output wire mem_reset_n, // .mem_reset_n
inout wire [31:0] mem_dq, // .mem_dq
inout wire [3:0] mem_dqs, // .mem_dqs
inout wire [3:0] mem_dqs_n, // .mem_dqs_n
output wire mem_odt, // .mem_odt
output wire [3:0] mem_dm, // .mem_dm
input wire oct_rzqin, // .oct_rzqin
output wire hps_io_emac1_inst_TX_CLK, // hps_io.hps_io_emac1_inst_TX_CLK
output wire hps_io_emac1_inst_TXD0, // .hps_io_emac1_inst_TXD0
output wire hps_io_emac1_inst_TXD1, // .hps_io_emac1_inst_TXD1
output wire hps_io_emac1_inst_TXD2, // .hps_io_emac1_inst_TXD2
output wire hps_io_emac1_inst_TXD3, // .hps_io_emac1_inst_TXD3
input wire hps_io_emac1_inst_RXD0, // .hps_io_emac1_inst_RXD0
inout wire hps_io_emac1_inst_MDIO, // .hps_io_emac1_inst_MDIO
output wire hps_io_emac1_inst_MDC, // .hps_io_emac1_inst_MDC
input wire hps_io_emac1_inst_RX_CTL, // .hps_io_emac1_inst_RX_CTL
output wire hps_io_emac1_inst_TX_CTL, // .hps_io_emac1_inst_TX_CTL
input wire hps_io_emac1_inst_RX_CLK, // .hps_io_emac1_inst_RX_CLK
input wire hps_io_emac1_inst_RXD1, // .hps_io_emac1_inst_RXD1
input wire hps_io_emac1_inst_RXD2, // .hps_io_emac1_inst_RXD2
input wire hps_io_emac1_inst_RXD3 // .hps_io_emac1_inst_RXD3
);
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (F2S_Width != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
f2s_width_check ( .error(1'b1) );
end
if (S2F_Width != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
s2f_width_check ( .error(1'b1) );
end
endgenerate
ledtest_hps_0_fpga_interfaces fpga_interfaces (
.h2f_rst_n (h2f_rst_n), // h2f_reset.reset_n
.h2f_lw_axi_clk (h2f_lw_axi_clk), // h2f_lw_axi_clock.clk
.h2f_lw_AWID (h2f_lw_AWID), // h2f_lw_axi_master.awid
.h2f_lw_AWADDR (h2f_lw_AWADDR), // .awaddr
.h2f_lw_AWLEN (h2f_lw_AWLEN), // .awlen
.h2f_lw_AWSIZE (h2f_lw_AWSIZE), // .awsize
.h2f_lw_AWBURST (h2f_lw_AWBURST), // .awburst
.h2f_lw_AWLOCK (h2f_lw_AWLOCK), // .awlock
.h2f_lw_AWCACHE (h2f_lw_AWCACHE), // .awcache
.h2f_lw_AWPROT (h2f_lw_AWPROT), // .awprot
.h2f_lw_AWVALID (h2f_lw_AWVALID), // .awvalid
.h2f_lw_AWREADY (h2f_lw_AWREADY), // .awready
.h2f_lw_WID (h2f_lw_WID), // .wid
.h2f_lw_WDATA (h2f_lw_WDATA), // .wdata
.h2f_lw_WSTRB (h2f_lw_WSTRB), // .wstrb
.h2f_lw_WLAST (h2f_lw_WLAST), // .wlast
.h2f_lw_WVALID (h2f_lw_WVALID), // .wvalid
.h2f_lw_WREADY (h2f_lw_WREADY), // .wready
.h2f_lw_BID (h2f_lw_BID), // .bid
.h2f_lw_BRESP (h2f_lw_BRESP), // .bresp
.h2f_lw_BVALID (h2f_lw_BVALID), // .bvalid
.h2f_lw_BREADY (h2f_lw_BREADY), // .bready
.h2f_lw_ARID (h2f_lw_ARID), // .arid
.h2f_lw_ARADDR (h2f_lw_ARADDR), // .araddr
.h2f_lw_ARLEN (h2f_lw_ARLEN), // .arlen
.h2f_lw_ARSIZE (h2f_lw_ARSIZE), // .arsize
.h2f_lw_ARBURST (h2f_lw_ARBURST), // .arburst
.h2f_lw_ARLOCK (h2f_lw_ARLOCK), // .arlock
.h2f_lw_ARCACHE (h2f_lw_ARCACHE), // .arcache
.h2f_lw_ARPROT (h2f_lw_ARPROT), // .arprot
.h2f_lw_ARVALID (h2f_lw_ARVALID), // .arvalid
.h2f_lw_ARREADY (h2f_lw_ARREADY), // .arready
.h2f_lw_RID (h2f_lw_RID), // .rid
.h2f_lw_RDATA (h2f_lw_RDATA), // .rdata
.h2f_lw_RRESP (h2f_lw_RRESP), // .rresp
.h2f_lw_RLAST (h2f_lw_RLAST), // .rlast
.h2f_lw_RVALID (h2f_lw_RVALID), // .rvalid
.h2f_lw_RREADY (h2f_lw_RREADY) // .rready
);
ledtest_hps_0_hps_io hps_io (
.mem_a (mem_a), // memory.mem_a
.mem_ba (mem_ba), // .mem_ba
.mem_ck (mem_ck), // .mem_ck
.mem_ck_n (mem_ck_n), // .mem_ck_n
.mem_cke (mem_cke), // .mem_cke
.mem_cs_n (mem_cs_n), // .mem_cs_n
.mem_ras_n (mem_ras_n), // .mem_ras_n
.mem_cas_n (mem_cas_n), // .mem_cas_n
.mem_we_n (mem_we_n), // .mem_we_n
.mem_reset_n (mem_reset_n), // .mem_reset_n
.mem_dq (mem_dq), // .mem_dq
.mem_dqs (mem_dqs), // .mem_dqs
.mem_dqs_n (mem_dqs_n), // .mem_dqs_n
.mem_odt (mem_odt), // .mem_odt
.mem_dm (mem_dm), // .mem_dm
.oct_rzqin (oct_rzqin), // .oct_rzqin
.hps_io_emac1_inst_TX_CLK (hps_io_emac1_inst_TX_CLK), // hps_io.hps_io_emac1_inst_TX_CLK
.hps_io_emac1_inst_TXD0 (hps_io_emac1_inst_TXD0), // .hps_io_emac1_inst_TXD0
.hps_io_emac1_inst_TXD1 (hps_io_emac1_inst_TXD1), // .hps_io_emac1_inst_TXD1
.hps_io_emac1_inst_TXD2 (hps_io_emac1_inst_TXD2), // .hps_io_emac1_inst_TXD2
.hps_io_emac1_inst_TXD3 (hps_io_emac1_inst_TXD3), // .hps_io_emac1_inst_TXD3
.hps_io_emac1_inst_RXD0 (hps_io_emac1_inst_RXD0), // .hps_io_emac1_inst_RXD0
.hps_io_emac1_inst_MDIO (hps_io_emac1_inst_MDIO), // .hps_io_emac1_inst_MDIO
.hps_io_emac1_inst_MDC (hps_io_emac1_inst_MDC), // .hps_io_emac1_inst_MDC
.hps_io_emac1_inst_RX_CTL (hps_io_emac1_inst_RX_CTL), // .hps_io_emac1_inst_RX_CTL
.hps_io_emac1_inst_TX_CTL (hps_io_emac1_inst_TX_CTL), // .hps_io_emac1_inst_TX_CTL
.hps_io_emac1_inst_RX_CLK (hps_io_emac1_inst_RX_CLK), // .hps_io_emac1_inst_RX_CLK
.hps_io_emac1_inst_RXD1 (hps_io_emac1_inst_RXD1), // .hps_io_emac1_inst_RXD1
.hps_io_emac1_inst_RXD2 (hps_io_emac1_inst_RXD2), // .hps_io_emac1_inst_RXD2
.hps_io_emac1_inst_RXD3 (hps_io_emac1_inst_RXD3) // .hps_io_emac1_inst_RXD3
);
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: terminator.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module terminator (/*AUTOARG*/
// Inputs
TERM
);
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
inout TERM; // From cluster_header0 of cluster_header.v
endmodule
|
`timescale 1ns/10ps
module hps_design_PLL(
// interface 'refclk'
input wire refclk,
// interface 'reset'
input wire rst,
// interface 'outclk0'
output wire outclk_0,
// interface 'outclk1'
output wire outclk_1,
// interface 'locked'
output wire locked
);
altera_pll #(
.fractional_vco_multiplier("false"),
.reference_clock_frequency("100.0 MHz"),
.operation_mode("direct"),
.number_of_clocks(2),
.output_clock_frequency0("100.000000 MHz"),
.phase_shift0("0 ps"),
.duty_cycle0(50),
.output_clock_frequency1("100.000000 MHz"),
.phase_shift1("0 ps"),
.duty_cycle1(50),
.output_clock_frequency2("0 MHz"),
.phase_shift2("0 ps"),
.duty_cycle2(50),
.output_clock_frequency3("0 MHz"),
.phase_shift3("0 ps"),
.duty_cycle3(50),
.output_clock_frequency4("0 MHz"),
.phase_shift4("0 ps"),
.duty_cycle4(50),
.output_clock_frequency5("0 MHz"),
.phase_shift5("0 ps"),
.duty_cycle5(50),
.output_clock_frequency6("0 MHz"),
.phase_shift6("0 ps"),
.duty_cycle6(50),
.output_clock_frequency7("0 MHz"),
.phase_shift7("0 ps"),
.duty_cycle7(50),
.output_clock_frequency8("0 MHz"),
.phase_shift8("0 ps"),
.duty_cycle8(50),
.output_clock_frequency9("0 MHz"),
.phase_shift9("0 ps"),
.duty_cycle9(50),
.output_clock_frequency10("0 MHz"),
.phase_shift10("0 ps"),
.duty_cycle10(50),
.output_clock_frequency11("0 MHz"),
.phase_shift11("0 ps"),
.duty_cycle11(50),
.output_clock_frequency12("0 MHz"),
.phase_shift12("0 ps"),
.duty_cycle12(50),
.output_clock_frequency13("0 MHz"),
.phase_shift13("0 ps"),
.duty_cycle13(50),
.output_clock_frequency14("0 MHz"),
.phase_shift14("0 ps"),
.duty_cycle14(50),
.output_clock_frequency15("0 MHz"),
.phase_shift15("0 ps"),
.duty_cycle15(50),
.output_clock_frequency16("0 MHz"),
.phase_shift16("0 ps"),
.duty_cycle16(50),
.output_clock_frequency17("0 MHz"),
.phase_shift17("0 ps"),
.duty_cycle17(50),
.pll_type("General"),
.pll_subtype("General")
) altera_pll_i (
.rst (rst),
.outclk ({outclk_1, outclk_0}),
.locked (locked),
.fboutclk ( ),
.fbclk (1'b0),
.refclk (refclk)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__EINVN_BEHAVIORAL_V
`define SKY130_FD_SC_HD__EINVN_BEHAVIORAL_V
/**
* einvn: Tri-state inverter, negative enable.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__einvn (
Z ,
A ,
TE_B
);
// Module ports
output Z ;
input A ;
input TE_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Name Output Other arguments
notif0 notif00 (Z , A, TE_B );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__EINVN_BEHAVIORAL_V
|
/*
* Copyright (c) 2011-2012 Travis Geiselbrecht
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files
* (the "Software"), to deal in the Software without restriction,
* including without limitation the rights to use, copy, modify, merge,
* publish, distribute, sublicense, and/or sell copies of the Software,
* and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
module top
(
//////////////////// Clock Input ////////////////////
CLOCK_24, // 24 MHz
CLOCK_27, // 27 MHz
CLOCK_50, // 50 MHz
EXT_CLOCK, // External Clock
//////////////////// Push Button ////////////////////
KEY, // Pushbutton[3:0]
//////////////////// DPDT Switch ////////////////////
SW, // Toggle Switch[9:0]
//////////////////// 7-SEG Dispaly ////////////////////
HEX0, // Seven Segment Digit 0
HEX1, // Seven Segment Digit 1
HEX2, // Seven Segment Digit 2
HEX3, // Seven Segment Digit 3
//////////////////////// LED ////////////////////////
LEDG, // LED Green[7:0]
LEDR, // LED Red[9:0]
//////////////////////// UART ////////////////////////
UART_TXD, // UART Transmitter
UART_RXD, // UART Receiver
///////////////////// SDRAM Interface ////////////////
DRAM_DQ, // SDRAM Data bus 16 Bits
DRAM_ADDR, // SDRAM Address bus 12 Bits
DRAM_LDQM, // SDRAM Low-byte Data Mask
DRAM_UDQM, // SDRAM High-byte Data Mask
DRAM_WE_N, // SDRAM Write Enable
DRAM_CAS_N, // SDRAM Column Address Strobe
DRAM_RAS_N, // SDRAM Row Address Strobe
DRAM_CS_N, // SDRAM Chip Select
DRAM_BA_0, // SDRAM Bank Address 0
DRAM_BA_1, // SDRAM Bank Address 0
DRAM_CLK, // SDRAM Clock
DRAM_CKE, // SDRAM Clock Enable
//////////////////// Flash Interface ////////////////
FL_DQ, // FLASH Data bus 8 Bits
FL_ADDR, // FLASH Address bus 22 Bits
FL_WE_N, // FLASH Write Enable
FL_RST_N, // FLASH Reset
FL_OE_N, // FLASH Output Enable
FL_CE_N, // FLASH Chip Enable
//////////////////// SRAM Interface ////////////////
SRAM_DQ, // SRAM Data bus 16 Bits
SRAM_ADDR, // SRAM Address bus 18 Bits
SRAM_UB_N, // SRAM High-byte Data Mask
SRAM_LB_N, // SRAM Low-byte Data Mask
SRAM_WE_N, // SRAM Write Enable
SRAM_CE_N, // SRAM Chip Enable
SRAM_OE_N, // SRAM Output Enable
//////////////////// SD_Card Interface ////////////////
SD_DAT, // SD Card Data
SD_DAT3, // SD Card Data 3
SD_CMD, // SD Card Command Signal
SD_CLK, // SD Card Clock
//////////////////// USB JTAG link ////////////////////
TDI, // CPLD -> FPGA (data in)
TCK, // CPLD -> FPGA (clk)
TCS, // CPLD -> FPGA (CS)
TDO, // FPGA -> CPLD (data out)
//////////////////// I2C ////////////////////////////
I2C_SDAT, // I2C Data
I2C_SCLK, // I2C Clock
//////////////////// PS2 ////////////////////////////
PS2_DAT, // PS2 Data
PS2_CLK, // PS2 Clock
//////////////////// VGA ////////////////////////////
VGA_HS, // VGA H_SYNC
VGA_VS, // VGA V_SYNC
VGA_R, // VGA Red[3:0]
VGA_G, // VGA Green[3:0]
VGA_B, // VGA Blue[3:0]
//////////////// Audio CODEC ////////////////////////
AUD_ADCLRCK, // Audio CODEC ADC LR Clock
AUD_ADCDAT, // Audio CODEC ADC Data
AUD_DACLRCK, // Audio CODEC DAC LR Clock
AUD_DACDAT, // Audio CODEC DAC Data
AUD_BCLK, // Audio CODEC Bit-Stream Clock
AUD_XCK, // Audio CODEC Chip Clock
//////////////////// GPIO ////////////////////////////
GPIO_0, // GPIO Connection 0
GPIO_1 // GPIO Connection 1
);
//////////////////////// Clock Input ////////////////////////
input [1:0] CLOCK_24; // 24 MHz
input [1:0] CLOCK_27; // 27 MHz
input CLOCK_50; // 50 MHz
input EXT_CLOCK; // External Clock
//////////////////////// Push Button ////////////////////////
input [3:0] KEY; // Pushbutton[3:0]
//////////////////////// DPDT Switch ////////////////////////
input [9:0] SW; // Toggle Switch[9:0]
//////////////////////// 7-SEG Dispaly ////////////////////////
output [6:0] HEX0; // Seven Segment Digit 0
output [6:0] HEX1; // Seven Segment Digit 1
output [6:0] HEX2; // Seven Segment Digit 2
output [6:0] HEX3; // Seven Segment Digit 3
//////////////////////////// LED ////////////////////////////
output [7:0] LEDG; // LED Green[7:0]
output [9:0] LEDR; // LED Red[9:0]
//////////////////////////// UART ////////////////////////////
output UART_TXD; // UART Transmitter
input UART_RXD; // UART Receiver
/////////////////////// SDRAM Interface ////////////////////////
inout [15:0] DRAM_DQ; // SDRAM Data bus 16 Bits
output [11:0] DRAM_ADDR; // SDRAM Address bus 12 Bits
output DRAM_LDQM; // SDRAM Low-byte Data Mask
output DRAM_UDQM; // SDRAM High-byte Data Mask
output DRAM_WE_N; // SDRAM Write Enable
output DRAM_CAS_N; // SDRAM Column Address Strobe
output DRAM_RAS_N; // SDRAM Row Address Strobe
output DRAM_CS_N; // SDRAM Chip Select
output DRAM_BA_0; // SDRAM Bank Address 0
output DRAM_BA_1; // SDRAM Bank Address 0
output DRAM_CLK; // SDRAM Clock
output DRAM_CKE; // SDRAM Clock Enable
//////////////////////// Flash Interface ////////////////////////
inout [7:0] FL_DQ; // FLASH Data bus 8 Bits
output [21:0] FL_ADDR; // FLASH Address bus 22 Bits
output FL_WE_N; // FLASH Write Enable
output FL_RST_N; // FLASH Reset
output FL_OE_N; // FLASH Output Enable
output FL_CE_N; // FLASH Chip Enable
//////////////////////// SRAM Interface ////////////////////////
inout [15:0] SRAM_DQ; // SRAM Data bus 16 Bits
output [17:0] SRAM_ADDR; // SRAM Address bus 18 Bits
output SRAM_UB_N; // SRAM High-byte Data Mask
output SRAM_LB_N; // SRAM Low-byte Data Mask
output SRAM_WE_N; // SRAM Write Enable
output SRAM_CE_N; // SRAM Chip Enable
output SRAM_OE_N; // SRAM Output Enable
//////////////////// SD Card Interface ////////////////////////
inout SD_DAT; // SD Card Data
inout SD_DAT3; // SD Card Data 3
inout SD_CMD; // SD Card Command Signal
output SD_CLK; // SD Card Clock
//////////////////////// I2C ////////////////////////////////
inout I2C_SDAT; // I2C Data
output I2C_SCLK; // I2C Clock
//////////////////////// PS2 ////////////////////////////////
input PS2_DAT; // PS2 Data
input PS2_CLK; // PS2 Clock
//////////////////// USB JTAG link ////////////////////////////
input TDI; // CPLD -> FPGA (data in)
input TCK; // CPLD -> FPGA (clk)
input TCS; // CPLD -> FPGA (CS)
output TDO; // FPGA -> CPLD (data out)
//////////////////////// VGA ////////////////////////////
output VGA_HS; // VGA H_SYNC
output VGA_VS; // VGA V_SYNC
output [3:0] VGA_R; // VGA Red[3:0]
output [3:0] VGA_G; // VGA Green[3:0]
output [3:0] VGA_B; // VGA Blue[3:0]
//////////////////// Audio CODEC ////////////////////////////
output AUD_ADCLRCK; // Audio CODEC ADC LR Clock
input AUD_ADCDAT; // Audio CODEC ADC Data
output AUD_DACLRCK; // Audio CODEC DAC LR Clock
output AUD_DACDAT; // Audio CODEC DAC Data
inout AUD_BCLK; // Audio CODEC Bit-Stream Clock
output AUD_XCK; // Audio CODEC Chip Clock
//////////////////////// GPIO ////////////////////////////////
input [35:0] GPIO_0; // GPIO Connection 0
inout [35:0] GPIO_1; // GPIO Connection 1
///////////////////////////////////////////////////////////////////
//assign GPIO_1 = GPIO_0;
// run a 1mhz clock
reg[6:0] div;
initial begin
div <= 0;
end
always @(posedge CLOCK_24[0])
begin
div = div + 1;
end
wire slowclk = CLOCK_24[0]; //div[4];
/*
reg slowclk;
always @(negedge KEY[0])
begin
slowclk <= ~slowclk;
end
*/
/* instantiate the cpu */
wire cpu_re;
wire cpu_we;
reg rst;
wire [29:0] memaddr;
wire [31:0] rmemdata;
wire [31:0] wmemdata;
wire [31:0] cpudebugout;
//assign rst = KEY[0];
initial
rst <= 0;
cpu cpu0(
.clk(slowclk),
.rst(rst),
.mem_re(cpu_re),
.mem_we(cpu_we),
.memaddr(memaddr),
.rmemdata(rmemdata),
.wmemdata(wmemdata),
.debugout(cpudebugout)
);
/* main memory */
wire mem_re = cpu_re && (memaddr[29] == 0);
wire mem_we = cpu_we && (memaddr[29] == 0);
syncmem mem0(
.clk(slowclk),
.re(mem_re),
.we(mem_we),
.addr(memaddr),
.rdata(rmemdata),
.wdata(wmemdata)
);
/* uart */
wire uart_re = cpu_re && (memaddr[29:14] == 16'b1000000000000000);
wire uart_we = cpu_we && (memaddr[29:14] == 16'b1000000000000000);
uart uart0(
.clk(slowclk),
.rst(rst),
.hwtx(UART_TXD),
.hwrx(UART_RXD),
.addr(memaddr[0]),
.re(uart_re),
.we(uart_we),
.wdata(wmemdata),
.rdata(rmemdata),
// .rxchar(0),
// .rxvalid(),
);
/* debug register */
wire debuglatch_we = cpu_we && (memaddr[29:14] == 16'b1000000000000001);
reg[31:0] debuglatch;
always @(posedge slowclk) begin
if (debuglatch_we) begin
debuglatch <= wmemdata;
end
end
//`define WITH_SRAM
`ifdef WITH_SRAM
assign SRAM_UB_N = 0;
assign SRAM_LB_N = 0;
wire read_sync;
wire write_sync;
integer addr;
reg [1:0] retest;
always @(negedge slowclk) begin
retest <= retest + 1;
end
always @(posedge read_sync or posedge write_sync) begin
addr <= addr + 1;
end
sramcontroller sram(
.clk(slowclk),
.addr(addr),
.indata(0),
.re(retest[1]),
.we(retest[0]),
.read_sync(read_sync),
.write_sync(write_sync),
.memclk(memclk),
.sram_addr(SRAM_ADDR),
.sram_data(SRAM_DQ),
.sram_ce(SRAM_CE_N),
.sram_re(SRAM_OE_N),
.sram_we(SRAM_WE_N)
);
`endif
reg[15:0] debugreg;
always @(SW[9] or SW[8] or SW[7] or memaddr or rmemdata or debuglatch)
begin
if (SW[9]) begin
debugreg = rmemdata[31:16];
end else if (SW[8]) begin
debugreg = rmemdata[15:0];
end else if (SW[7]) begin
debugreg = memaddr[29:16];
end else if (SW[1]) begin
debugreg = debuglatch[31:16];
end else if (SW[0]) begin
debugreg = debuglatch[15:0];
end else begin
debugreg = memaddr[15:0];
end
end
/* debug info */
seven_segment seg0(debugreg[3:0], HEX0);
seven_segment seg1(debugreg[7:4], HEX1);
seven_segment seg2(debugreg[11:8], HEX2);
seven_segment seg3(debugreg[15:12], HEX3);
assign LEDG[0] = rst;
assign LEDG[1] = slowclk;
assign LEDG[2] = mem_re;
assign LEDG[3] = mem_we;
//assign GPIO_1[0] = slowclk;
//assign GPIO_1[1] = mem_re;
//assign GPIO_1[2] = mem_we;
//assign GPIO_1[7:3] = memaddr[4:0];
//assign GPIO_1[15:8] = wmemdata[7:0];
//assign GPIO_1[8] = memclk;
//assign GPIO_1[9] = read_sync;
//assign GPIO_1[10] = write_sync;
//assign GPIO_1[11] = SRAM_CE_N;
//assign GPIO_1[12] = SRAM_OE_N;
//assign GPIO_1[15:13] = SRAM_ADDR[2:0];
assign GPIO_1[0] = UART_TXD;
assign GPIO_1[1] = UART_RXD;
endmodule
module syncmem(
input clk,
input re,
input we,
input [29:0] addr,
output reg [31:0] rdata,
input [31:0] wdata
);
reg [31:0] mem [0:4096];
initial begin
$readmemh("../test/test2.asm.hex", mem);
end
always @(posedge clk) begin
if (re)
rdata <= mem[addr];
else
rdata <= 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
if (we)
mem[addr] <= wdata;
end
endmodule
|
/*
###############################################################################
# pyrpl - DSP servo controller for quantum optics with the RedPitaya
# Copyright (C) 2014-2016 Leonhard Neuhaus ([email protected])
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
###############################################################################
*/
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 13.12.2015 18:56:43
// Design Name:
// Module Name: saturate
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 13.12.2015 18:04:09
// Design Name:
// Module Name: product_sat
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module red_pitaya_saturate
#( parameter BITS_IN = 50,
parameter BITS_OUT = 20,
parameter SHIFT = 10
)
(
input signed [BITS_IN-1:0] input_i,
output signed [BITS_OUT-1:0] output_o,
output overflow
);
assign {output_o,overflow} = ( {input_i[BITS_IN-1],|input_i[BITS_IN-2:SHIFT+BITS_OUT-1]} ==2'b01) ?
{{1'b0,{BITS_OUT-1{1'b1}}},1'b1} : //positive overflow
( {input_i[BITS_IN-1],&input_i[BITS_IN-2:SHIFT+BITS_OUT-1]} == 2'b10) ?
{{1'b1,{BITS_OUT-1{1'b0}}},1'b1} : //negative overflow
{input_i[SHIFT+BITS_OUT-1:SHIFT],1'b0} ; //correct value
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: pcx2mb.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
/***************************************************************************
* pcx2mb.v: An interface file to connect the PCX interface of the SPARC
* core with the MicroBlaze FSL FIFO.
*
* NOTE: Pipeline stages from SPARC point of view are
* PQ Initial Request
* PA Data sent for request.
* PX Grant returned, Request sent to cache
* PX2 Data sent to cache
*
* $Id: pcx2mb.v,v 1.9 2007/07/20 20:17:38 tt147840 Exp $
***************************************************************************/
// Global header file includes
// Local header file includes
`include "ccx2mb.h"
module pcx2mb (
// Outputs
pcx_spc_grant_px,
pcx_fsl_m_control,
pcx_fsl_m_data,
pcx_fsl_m_write,
// Inputs
rclk,
reset_l,
spc_pcx_data_pa,
spc_pcx_atom_pq,
spc_pcx_req_pq,
fsl_pcx_m_full
);
`ifdef PCX2MB_5_BIT_REQ
parameter PCX_REQ_WIDTH = 5;
`else
parameter PCX_REQ_WIDTH = 2;
`endif
parameter PCX_GEAR_RATIO = (((`PCX_WIDTH+PCX_REQ_WIDTH)/`FSL_D_WIDTH)+1);
parameter PCX_FSL_EXTRA_BITS = (`FSL_D_WIDTH * PCX_GEAR_RATIO) -
(`PCX_WIDTH+PCX_REQ_WIDTH+1);
//=============================================
// Outputs
// SPARC/PCX interface
output [4:0] pcx_spc_grant_px;
// PCX/FSL interface
output pcx_fsl_m_control;
output [`FSL_D_WIDTH-1:0] pcx_fsl_m_data;
output pcx_fsl_m_write;
//=============================================
// Inputs
input rclk;
input reset_l;
// SPARC/PCX interface
input [`PCX_WIDTH-1:0] spc_pcx_data_pa;
input spc_pcx_atom_pq;
input [4:0] spc_pcx_req_pq;
// PCX/FSL interface
input fsl_pcx_m_full;
//=============================================
// Wire definitions for outputs
// SPARC/PCX interface
wire [4:0] pcx_spc_grant_px;
// PCX/FSL interface
wire pcx_fsl_m_control;
wire [`FSL_D_WIDTH-1:0] pcx_fsl_m_data;
wire pcx_fsl_m_write;
wire any_req_pq;
wire any_req_pa;
reg any_req_px;
wire [4:0] req_dest_pq;
reg [4:0] req_dest_pa_raw;
wire [4:0] req_dest_pa;
reg [4:0] req_dest_px;
reg req_atom_pa;
reg req_atom_px;
wire [4:0] request_mask_pa;
// PCX has 5 different request lines for 5 different destinations.
// The core may send up to three transactions per destination. The third
// transaction for a given destination is sent speculatively. It must be
// dropped if the grant for the first transaction is not available on the
// cycle that the third transaction is requested. The counters below
// enforce this.
pcx2mb_link_ctr dest_ctr_0 (
.request_mask_pa(request_mask_pa[0]),
.rclk(rclk),
.reset_l(reset_l),
.pcx_req_pa(req_dest_pa[0]),
.pcx_req_px(req_dest_px[0]),
.pcx_atom_px(req_atom_px),
.pcx_grant_px(pcx_spc_grant_px[0])
);
pcx2mb_link_ctr dest_ctr_1 (
.request_mask_pa(request_mask_pa[1]),
.rclk(rclk),
.reset_l(reset_l),
.pcx_req_pa(req_dest_pa[1]),
.pcx_req_px(req_dest_px[1]),
.pcx_atom_px(req_atom_px),
.pcx_grant_px(pcx_spc_grant_px[1])
);
pcx2mb_link_ctr dest_ctr_2 (
.request_mask_pa(request_mask_pa[2]),
.rclk(rclk),
.reset_l(reset_l),
.pcx_req_pa(req_dest_pa[2]),
.pcx_req_px(req_dest_px[2]),
.pcx_atom_px(req_atom_px),
.pcx_grant_px(pcx_spc_grant_px[2])
);
pcx2mb_link_ctr dest_ctr_3 (
.request_mask_pa(request_mask_pa[3]),
.rclk(rclk),
.reset_l(reset_l),
.pcx_req_pa(req_dest_pa[3]),
.pcx_req_px(req_dest_px[3]),
.pcx_atom_px(req_atom_px),
.pcx_grant_px(pcx_spc_grant_px[3])
);
pcx2mb_link_ctr dest_ctr_4 (
.request_mask_pa(request_mask_pa[4]),
.rclk(rclk),
.reset_l(reset_l),
.pcx_req_pa(req_dest_pa[4]),
.pcx_req_px(req_dest_px[4]),
.pcx_atom_px(req_atom_px),
.pcx_grant_px(pcx_spc_grant_px[4])
);
// This block routes to only 1 destination, so OR together the bits for
// request
assign any_req_pq = | (spc_pcx_req_pq &
~(request_mask_pa & ~pcx_spc_grant_px));
assign req_dest_pq = spc_pcx_req_pq;
assign req_dest_pa = req_dest_pa_raw & ~request_mask_pa;
assign any_req_pa = | req_dest_pa;
always @ (posedge rclk) begin
req_dest_pa_raw <= req_dest_pq;
req_atom_pa <= spc_pcx_atom_pq;
any_req_px <= any_req_pa;
req_dest_px <= req_dest_pa;
req_atom_px <= req_atom_pa;
end
// Variable definitions for the transaction entries
wire [`PCX_WIDTH+PCX_REQ_WIDTH:0] entry2_data;
wire entry2_active;
wire [4:0] entry2_dest;
wire entry2_atom;
assign entry2_atom = entry2_data[`PCX_WIDTH];
wire [`PCX_WIDTH+PCX_REQ_WIDTH:0] entry3_data;
wire entry3_active;
wire [4:0] entry3_dest;
wire [`PCX_WIDTH+PCX_REQ_WIDTH:0] entry4_data;
wire entry4_active;
wire [4:0] entry4_dest;
wire [`PCX_WIDTH+PCX_REQ_WIDTH:0] entry5_data;
wire entry5_active;
wire [4:0] entry5_dest;
wire [`PCX_WIDTH+PCX_REQ_WIDTH:0] entry6_data;
wire entry6_active;
wire [4:0] entry6_dest;
wire [`PCX_WIDTH+PCX_REQ_WIDTH:0] entry7_data;
wire entry7_active;
wire [4:0] entry7_dest;
wire [`PCX_WIDTH+PCX_REQ_WIDTH:0] entry8_data;
wire entry8_active;
wire [4:0] entry8_dest;
wire [`PCX_WIDTH+PCX_REQ_WIDTH:0] entry9_data;
wire entry9_active;
wire [4:0] entry9_dest;
wire [`PCX_WIDTH+PCX_REQ_WIDTH:0] entry10_data;
wire entry10_active;
wire [4:0] entry10_dest;
// The first entry is also a shift register.
reg [PCX_GEAR_RATIO*`FSL_D_WIDTH-1:0] entry1;
wire entry1_active;
reg entry1_active_d1;
reg [4:0] entry1_dest;
wire load_data;
wire shift_data;
// Instantiate 10 copies of a pcx entry register
// Entry 2
pcx2mb_entry #(PCX_REQ_WIDTH) i_entry2 (
.rclk(rclk),
.reset_l(reset_l),
.any_req_pa(any_req_pa),
.spc_pcx_data_pa(spc_pcx_data_pa),
.req_dest_pa(req_dest_pa),
.req_atom_pa(req_atom_pa),
.any_req_px(any_req_px),
.req_dest_px(req_dest_px),
.req_atom_px(req_atom_px),
.load_data(load_data),
.prev_data(entry3_data),
.prev_active(entry3_active),
.prev_dest(entry3_dest),
.next_active(entry1_active & entry1_active_d1),
// Output signals
.e_data(entry2_data),
.e_active(entry2_active),
.e_dest(entry2_dest)
);
// Entry 3
pcx2mb_entry #(PCX_REQ_WIDTH) i_entry3 (
.rclk(rclk),
.reset_l(reset_l),
.any_req_pa(any_req_pa),
.spc_pcx_data_pa(spc_pcx_data_pa),
.req_dest_pa(req_dest_pa),
.req_atom_pa(req_atom_pa),
.any_req_px(any_req_px),
.req_dest_px(req_dest_px),
.req_atom_px(req_atom_px),
.load_data(load_data),
.prev_data(entry4_data),
.prev_active(entry4_active),
.prev_dest(entry4_dest),
.next_active(entry2_active),
// Output signals
.e_data(entry3_data),
.e_active(entry3_active),
.e_dest(entry3_dest)
);
// Entry 4
pcx2mb_entry #(PCX_REQ_WIDTH) i_entry4 (
.rclk(rclk),
.reset_l(reset_l),
.any_req_pa(any_req_pa),
.spc_pcx_data_pa(spc_pcx_data_pa),
.req_dest_pa(req_dest_pa),
.req_atom_pa(req_atom_pa),
.any_req_px(any_req_px),
.req_dest_px(req_dest_px),
.req_atom_px(req_atom_px),
.load_data(load_data),
.prev_data(entry5_data),
.prev_active(entry5_active),
.prev_dest(entry5_dest),
.next_active(entry3_active),
// Output signals
.e_data(entry4_data),
.e_active(entry4_active),
.e_dest(entry4_dest)
);
// Entry 5
pcx2mb_entry #(PCX_REQ_WIDTH) i_entry5 (
.rclk(rclk),
.reset_l(reset_l),
.any_req_pa(any_req_pa),
.spc_pcx_data_pa(spc_pcx_data_pa),
.req_dest_pa(req_dest_pa),
.req_atom_pa(req_atom_pa),
.any_req_px(any_req_px),
.req_dest_px(req_dest_px),
.req_atom_px(req_atom_px),
.load_data(load_data),
.prev_data(entry6_data),
.prev_active(entry6_active),
.prev_dest(entry6_dest),
.next_active(entry4_active),
// Output signals
.e_data(entry5_data),
.e_active(entry5_active),
.e_dest(entry5_dest)
);
// Entry 6
pcx2mb_entry #(PCX_REQ_WIDTH) i_entry6 (
.rclk(rclk),
.reset_l(reset_l),
.any_req_pa(any_req_pa),
.spc_pcx_data_pa(spc_pcx_data_pa),
.req_dest_pa(req_dest_pa),
.req_atom_pa(req_atom_pa),
.any_req_px(any_req_px),
.req_dest_px(req_dest_px),
.req_atom_px(req_atom_px),
.load_data(load_data),
.prev_data(entry7_data),
.prev_active(entry7_active),
.prev_dest(entry7_dest),
.next_active(entry5_active),
// Output signals
.e_data(entry6_data),
.e_active(entry6_active),
.e_dest(entry6_dest)
);
// Entry 7
pcx2mb_entry #(PCX_REQ_WIDTH) i_entry7 (
.rclk(rclk),
.reset_l(reset_l),
.any_req_pa(any_req_pa),
.spc_pcx_data_pa(spc_pcx_data_pa),
.req_dest_pa(req_dest_pa),
.req_atom_pa(req_atom_pa),
.any_req_px(any_req_px),
.req_dest_px(req_dest_px),
.req_atom_px(req_atom_px),
.load_data(load_data),
.prev_data(entry8_data),
.prev_active(entry8_active),
.prev_dest(entry8_dest),
.next_active(entry6_active),
// Output signals
.e_data(entry7_data),
.e_active(entry7_active),
.e_dest(entry7_dest)
);
// Entry 8
pcx2mb_entry #(PCX_REQ_WIDTH) i_entry8 (
.rclk(rclk),
.reset_l(reset_l),
.any_req_pa(any_req_pa),
.spc_pcx_data_pa(spc_pcx_data_pa),
.req_dest_pa(req_dest_pa),
.req_atom_pa(req_atom_pa),
.any_req_px(any_req_px),
.req_dest_px(req_dest_px),
.req_atom_px(req_atom_px),
.load_data(load_data),
.prev_data(entry9_data),
.prev_active(entry9_active),
.prev_dest(entry9_dest),
.next_active(entry7_active),
// Output signals
.e_data(entry8_data),
.e_active(entry8_active),
.e_dest(entry8_dest)
);
// Entry 9
pcx2mb_entry #(PCX_REQ_WIDTH) i_entry9 (
.rclk(rclk),
.reset_l(reset_l),
.any_req_pa(any_req_pa),
.spc_pcx_data_pa(spc_pcx_data_pa),
.req_dest_pa(req_dest_pa),
.req_atom_pa(req_atom_pa),
.any_req_px(any_req_px),
.req_dest_px(req_dest_px),
.req_atom_px(req_atom_px),
.load_data(load_data),
.prev_data(entry10_data),
.prev_active(entry10_active),
.prev_dest(entry10_dest),
.next_active(entry8_active),
// Output signals
.e_data(entry9_data),
.e_active(entry9_active),
.e_dest(entry9_dest)
);
// Entry 10
pcx2mb_entry #(PCX_REQ_WIDTH) i_entry10 (
.rclk(rclk),
.reset_l(reset_l),
.any_req_pa(any_req_pa),
.spc_pcx_data_pa(spc_pcx_data_pa),
.req_dest_pa(req_dest_pa),
.req_atom_pa(req_atom_pa),
.any_req_px(any_req_px),
.req_dest_px(req_dest_px),
.req_atom_px(req_atom_px),
.load_data(load_data),
.prev_data({`PCX_WIDTH+PCX_REQ_WIDTH+1{1'b0}}),
.prev_active(1'b0),
.prev_dest(5'b00000),
.next_active(entry9_active),
// Output signals
.e_data(entry10_data),
.e_active(entry10_active),
.e_dest(entry10_dest)
);
// State machine to control the shifting out of the data.
pcx2mb_sm shft_state (
.load_data(load_data),
.shift_data(shift_data),
.entry1_active(entry1_active),
.pcx_fsl_m_control(pcx_fsl_m_control),
.pcx_fsl_m_write(pcx_fsl_m_write),
.pcx_spc_grant_px(pcx_spc_grant_px),
.rclk(rclk),
.reset_l(reset_l),
.any_req_pq(any_req_pq),
.any_req_pa(any_req_pa),
.spc_pcx_atom_pq(spc_pcx_atom_pq),
.entry1_dest(entry1_dest),
.entry2_active(entry2_active),
.entry2_atom(entry2_atom),
.fsl_pcx_m_full(fsl_pcx_m_full)
);
// Define a shift register to shift data out into the narrower FSL bus
always @(posedge rclk) begin
if (!reset_l) begin
entry1 <= {PCX_GEAR_RATIO*`FSL_D_WIDTH{1'b0}};
entry1_dest <= 5'b00000;
end
else if (shift_data) begin
entry1 <= entry1 << `FSL_D_WIDTH;
entry1_dest <= entry1_dest;
end
else if (load_data && entry2_active) begin
entry1 <= { {PCX_FSL_EXTRA_BITS{1'b0}},entry2_data};
entry1_dest <= entry2_dest;
end
else if (load_data) begin
`ifdef PCX2MB_5_BIT_REQ
entry1 <= { {PCX_FSL_EXTRA_BITS{1'b0}},
req_dest_pa[4:0], req_atom_pa, spc_pcx_data_pa};
`else
entry1 <= { {PCX_FSL_EXTRA_BITS{1'b0}}, req_dest_pa[4],
(|req_dest_pa[3:0]), req_atom_pa, spc_pcx_data_pa};
`endif
entry1_dest <= req_dest_pa;
end
else begin
entry1 <= entry1;
entry1_dest <= entry1_dest;
end
end
always @(posedge rclk) begin
entry1_active_d1 <= entry1_active;
end
// Output Data
assign pcx_fsl_m_data = entry1[PCX_GEAR_RATIO*`FSL_D_WIDTH-1:(PCX_GEAR_RATIO-1)*`FSL_D_WIDTH];
endmodule
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2013 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file blk_mem_gen_paramReg.v when simulating
// the core, blk_mem_gen_paramReg. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module blk_mem_gen_paramReg(
clka,
wea,
addra,
dina,
douta,
clkb,
web,
addrb,
dinb,
doutb
);
input clka;
input [0 : 0] wea;
input [7 : 0] addra;
input [31 : 0] dina;
output [31 : 0] douta;
input clkb;
input [0 : 0] web;
input [7 : 0] addrb;
input [31 : 0] dinb;
output [31 : 0] doutb;
// synthesis translate_off
BLK_MEM_GEN_V6_2 #(
.C_ADDRA_WIDTH(8),
.C_ADDRB_WIDTH(8),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(1),
.C_DISABLE_WARN_BHV_RANGE(1),
.C_FAMILY("virtex5"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(2),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(255),
.C_READ_DEPTH_B(255),
.C_READ_WIDTH_A(32),
.C_READ_WIDTH_B(32),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(255),
.C_WRITE_DEPTH_B(255),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(32),
.C_WRITE_WIDTH_B(32),
.C_XDEVICEFAMILY("virtex5")
)
inst (
.CLKA(clka),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.DOUTA(douta),
.CLKB(clkb),
.WEB(web),
.ADDRB(addrb),
.DINB(dinb),
.DOUTB(doutb),
.RSTA(),
.ENA(),
.REGCEA(),
.RSTB(),
.ENB(),
.REGCEB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
/* This file is part of JT51.
JT51 is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JT51 is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JT51. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 27-10-2016
*/
module jt51_reg(
input rst,
input clk,
input cen, // P1
input [7:0] din,
input up_rl,
input up_kc,
input up_kf,
input up_pms,
input up_dt1,
input up_tl,
input up_ks,
input up_amsen,
input up_dt2,
input up_d1l,
input up_keyon,
input [1:0] op, // operator to update
input [2:0] ch, // channel to update
input csm,
input overflow_A,
output [1:0] rl_I,
output [2:0] fb_II,
output [2:0] con_I,
output [6:0] kc_I,
output [5:0] kf_I,
output [2:0] pms_I,
output [1:0] ams_VII,
output [2:0] dt1_II,
output [3:0] mul_VI,
output [6:0] tl_VII,
output [1:0] ks_III,
output amsen_VII,
output [4:0] arate_II,
output [4:0] rate1_II,
output [4:0] rate2_II,
output [3:0] rrate_II,
output [1:0] dt2_I,
output [3:0] d1l_I,
output keyon_II,
// Pipeline order
output reg zero,
output reg half,
output [4:0] cycles,
output reg m1_enters,
output reg m2_enters,
output reg c1_enters,
output reg c2_enters,
// Operator
output use_prevprev1,
output use_internal_x,
output use_internal_y,
output use_prev2,
output use_prev1,
output [1:0] cur_op,
output reg op31_no,
output reg op31_acc
);
reg kon, koff;
reg [1:0] csm_state;
reg [4:0] csm_cnt;
// wire csm_kon = csm_state[0];
// wire csm_koff = csm_state[1];
always @(*) begin
m1_enters = cur_op == 2'b00;
m2_enters = cur_op == 2'b01;
c1_enters = cur_op == 2'b10;
c2_enters = cur_op == 2'b11;
end
`ifdef SIMULATION
wire up = up_rl | up_kc | up_kf | up_pms | up_dt1 | up_tl |
up_ks | up_amsen | up_dt2 | up_d1l | up_keyon;
`endif
reg [4:0] cur;
always @(posedge clk) if(cen) begin
op31_no <= cur == 5'o10;
op31_acc <= cur == 5'o16;
end
assign cur_op = cur[4:3];
assign cycles = cur;
wire [4:0] req_I = { op, ch };
wire [4:0] req_II = req_I + 5'd1;
wire [4:0] req_III = req_II + 5'd1;
wire [4:0] req_IV = req_III + 5'd1;
wire [4:0] req_V = req_IV + 5'd1;
wire [4:0] req_VI = req_V + 5'd1;
wire [4:0] req_VII = req_VI + 5'd1;
wire update_op_I = cur == req_I;
wire update_op_II = cur == req_II;
wire update_op_III = cur == req_III;
// wire update_op_IV = cur == req_IV;
// wire update_op_V = cur == req_V;
wire update_op_VI = cur == req_VI;
wire update_op_VII = cur == req_VII;
wire up_rl_ch = up_rl & update_op_I;
wire up_fb_ch = up_rl & update_op_II;
wire up_con_ch = up_rl & update_op_I;
wire up_kc_ch = up_kc & update_op_I;
wire up_kf_ch = up_kf & update_op_I;
wire up_pms_ch = up_pms & update_op_I;
wire up_ams_ch = up_pms & update_op_VII;
wire up_dt1_op = up_dt1 & update_op_II; // DT1, MUL
wire up_mul_op = up_dt1 & update_op_VI; // DT1, MUL
wire up_tl_op = up_tl & update_op_VII;
wire up_ks_op = up_ks & update_op_III; // KS, AR
wire up_amsen_op= up_amsen & update_op_VII; // AMS-EN, D1R
wire up_dt2_op = up_dt2 & update_op_I; // DT2, D2R
wire up_d1l_op = up_d1l & update_op_I; // D1L, RR
wire up_ar_op = up_ks & update_op_II; // KS, AR
wire up_d1r_op = up_amsen & update_op_II; // AMS-EN, D1R
wire up_d2r_op = up_dt2 & update_op_II; // DT2, D2R
wire up_rr_op = up_d1l & update_op_II; // D1L, RR
wire [4:0] next = cur+5'd1;
always @(posedge clk, posedge rst) begin : up_counter
if( rst ) begin
cur <= 5'h0;
zero <= 1'b0;
half <= 1'b0;
end
else if(cen) begin
cur <= next;
zero <= next== 5'd0;
half <= next[3:0] == 4'd0;
end
end
wire [2:0] cur_ch = cur[2:0];
wire [3:0] keyon_op = din[6:3];
wire [2:0] keyon_ch = din[2:0];
jt51_kon u_kon (
.rst (rst ),
.clk (clk ),
.cen (cen ),
.keyon_op (keyon_op ),
.keyon_ch (keyon_ch ),
.cur_op (cur_op ),
.cur_ch (cur_ch ),
.up_keyon (up_keyon ),
.csm (csm ),
.overflow_A(overflow_A),
.keyon_II (keyon_II )
);
jt51_mod u_mod(
.alg_I ( con_I ),
.m1_enters ( m1_enters ),
.m2_enters ( m2_enters ),
.c1_enters ( c1_enters ),
.c2_enters ( c2_enters ),
.use_prevprev1 ( use_prevprev1 ),
.use_internal_x( use_internal_x ),
.use_internal_y( use_internal_y ),
.use_prev2 ( use_prev2 ),
.use_prev1 ( use_prev1 )
);
jt51_csr_op u_csr_op(
.rst ( rst ),
.clk ( clk ),
.cen ( cen ), // P1
.din ( din ),
.up_dt1_op ( up_dt1_op ),
.up_mul_op ( up_mul_op ),
.up_tl_op ( up_tl_op ),
.up_ks_op ( up_ks_op ),
.up_amsen_op ( up_amsen_op ),
.up_dt2_op ( up_dt2_op ),
.up_d1l_op ( up_d1l_op ),
.up_ar_op ( up_ar_op ),
.up_d1r_op ( up_d1r_op ),
.up_d2r_op ( up_d2r_op ),
.up_rr_op ( up_rr_op ),
.dt1 ( dt1_II ),
.mul ( mul_VI ),
.tl ( tl_VII ),
.ks ( ks_III ),
.amsen ( amsen_VII ),
.dt2 ( dt2_I ),
.d1l ( d1l_I ),
.arate ( arate_II ),
.rate1 ( rate1_II ),
.rate2 ( rate2_II ),
.rrate ( rrate_II )
);
jt51_csr_ch u_csr_ch(
.rst ( rst ),
.clk ( clk ),
.cen ( cen ),
.din ( din ),
.up_rl_ch ( up_rl_ch ),
.up_fb_ch ( up_fb_ch ),
.up_con_ch ( up_con_ch ),
.up_kc_ch ( up_kc_ch ),
.up_kf_ch ( up_kf_ch ),
.up_ams_ch ( up_ams_ch ),
.up_pms_ch ( up_pms_ch ),
.rl ( rl_I ),
.fb ( fb_II ),
.con ( con_I ),
.kc ( kc_I ),
.kf ( kf_I ),
.ams ( ams_VII ),
.pms ( pms_I )
);
//////////////////// Debug
`ifdef JT51_DEBUG
`ifdef SIMULATION
/* verilator lint_off PINMISSING */
wire [4:0] cnt_aux;
sep32_cnt u_sep32_cnt (.clk(clk), .cen(cen), .zero(zero), .cnt(cnt_aux));
sep32 #(.width(7),.stg(1)) sep_tl(
.clk ( clk ),
.cen ( cen ),
.mixed ( tl_VII ),
.cnt ( cnt_aux )
);
sep32 #(.width(5),.stg(1)) sep_ar(
.clk ( clk ),
.cen ( cen ),
.mixed ( arate_II ),
.cnt ( cnt_aux )
);
sep32 #(.width(4),.stg(1)) sep_d1l(
.clk ( clk ),
.cen ( cen ),
.mixed ( d1l_I ),
.cnt ( cnt_aux )
);
sep32 #(.width(4),.stg(1)) sep_rr(
.clk ( clk ),
.cen ( cen ),
.mixed ( rrate_II ),
.cnt ( cnt_aux )
);
sep32 #(.width(1),.stg(1)) sep_amsen(
.clk ( clk ),
.cen ( cen ),
.mixed ( amsen_VII ),
.cnt ( cnt_aux )
);
/* verilator lint_on PINMISSING */
`endif
`endif
endmodule
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of inst_t_e
//
// Generated
// by: wig
// on: Mon Apr 10 13:26:55 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../bitsplice.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: inst_t_e.v,v 1.2 2006/06/22 07:20:00 wig Exp $
// $Date: 2006/06/22 07:20:00 $
// $Log: inst_t_e.v,v $
// Revision 1.2 2006/06/22 07:20:00 wig
// Updated testcases and extended MixTest.pl to also verify number of created files.
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.79 2006/03/17 09:18:31 wig Exp
//
// Generator: mix_0.pl Revision: 1.44 , [email protected]
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of inst_t_e
//
// No user `defines in this module
module inst_t_e
//
// Generated module inst_t
//
(
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
wire test1;
wire [127:0] unsplice_a1_no3;
wire [127:0] unsplice_a2_all128;
wire [127:0] unsplice_a3_up100;
wire [127:0] unsplice_a4_mid100;
wire [127:0] unsplice_a5_midp100;
wire [127:0] unsplice_bad_a;
wire [127:0] unsplice_bad_b;
wire [31:0] widemerge_a1;
wire [31:0] widesig;
wire widesig_r_0;
wire widesig_r_1;
wire widesig_r_10;
wire widesig_r_11;
wire widesig_r_12;
wire widesig_r_13;
wire widesig_r_14;
wire widesig_r_15;
wire widesig_r_16;
wire widesig_r_17;
wire widesig_r_18;
wire widesig_r_19;
wire widesig_r_2;
wire widesig_r_20;
wire widesig_r_21;
wire widesig_r_22;
wire widesig_r_23;
wire widesig_r_24;
wire widesig_r_25;
wire widesig_r_26;
wire widesig_r_27;
wire widesig_r_28;
wire widesig_r_29;
wire widesig_r_3;
wire widesig_r_30;
wire widesig_r_4;
wire widesig_r_5;
wire widesig_r_6;
wire widesig_r_7;
wire widesig_r_8;
wire widesig_r_9;
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
// Generated Instance Port Map for inst_a
inst_a_e inst_a (
.p_mix_test1_go(test1), // Use internally test1
.unsplice_a1_no3(unsplice_a1_no3), // leaves 3 unconnected
.unsplice_a2_all128(unsplice_a2_all128), // full 128 bit port
.unsplice_a3_up100(unsplice_a3_up100), // connect 100 bits from 0
.unsplice_a4_mid100(unsplice_a4_mid100), // connect mid 100 bits
.unsplice_a5_midp100(unsplice_a5_midp100), // connect mid 100 bits
.unsplice_bad_a(unsplice_bad_a),
.unsplice_bad_b(unsplice_bad_b), // # conflict
.widemerge_a1(widemerge_a1),
.widesig_o(widesig),
.widesig_r_0(widesig_r_0),
.widesig_r_1(widesig_r_1),
.widesig_r_10(widesig_r_10),
.widesig_r_11(widesig_r_11),
.widesig_r_12(widesig_r_12),
.widesig_r_13(widesig_r_13),
.widesig_r_14(widesig_r_14),
.widesig_r_15(widesig_r_15),
.widesig_r_16(widesig_r_16),
.widesig_r_17(widesig_r_17),
.widesig_r_18(widesig_r_18),
.widesig_r_19(widesig_r_19),
.widesig_r_2(widesig_r_2),
.widesig_r_20(widesig_r_20),
.widesig_r_21(widesig_r_21),
.widesig_r_22(widesig_r_22),
.widesig_r_23(widesig_r_23),
.widesig_r_24(widesig_r_24),
.widesig_r_25(widesig_r_25),
.widesig_r_26(widesig_r_26),
.widesig_r_27(widesig_r_27),
.widesig_r_28(widesig_r_28),
.widesig_r_29(widesig_r_29),
.widesig_r_3(widesig_r_3),
.widesig_r_30(widesig_r_30),
.widesig_r_4(widesig_r_4),
.widesig_r_5(widesig_r_5),
.widesig_r_6(widesig_r_6),
.widesig_r_7(widesig_r_7),
.widesig_r_8(widesig_r_8),
.widesig_r_9(widesig_r_9)
);
// End of Generated Instance Port Map for inst_a
// Generated Instance Port Map for inst_b
inst_b_e inst_b (
.port_b_1(test1) // Use internally test1
);
// End of Generated Instance Port Map for inst_b
// Generated Instance Port Map for inst_c
inst_c_e inst_c (
);
// End of Generated Instance Port Map for inst_c
// Generated Instance Port Map for inst_d
inst_d_e inst_d (
);
// End of Generated Instance Port Map for inst_d
// Generated Instance Port Map for inst_e
inst_e_e inst_e (
.p_mix_unsplice_a1_no3_125_0_gi(unsplice_a1_no3[125:0]), // leaves 3 unconnected
.p_mix_unsplice_a1_no3_127_127_gi(unsplice_a1_no3[127]), // leaves 3 unconnected
.p_mix_unsplice_a2_all128_127_0_gi(unsplice_a2_all128), // full 128 bit port
.p_mix_unsplice_a3_up100_100_0_gi(unsplice_a3_up100[100:0]), // connect 100 bits from 0
.p_mix_unsplice_a4_mid100_99_2_gi(unsplice_a4_mid100[99:2]), // connect mid 100 bits
.p_mix_unsplice_a5_midp100_99_2_gi(unsplice_a5_midp100[99:2]), // connect mid 100 bits
.p_mix_unsplice_bad_a_1_1_gi(unsplice_bad_a[1]),
.p_mix_unsplice_bad_b_1_0_gi(unsplice_bad_b[1:0]), // # conflict
.p_mix_widemerge_a1_31_0_gi(widemerge_a1),
.p_mix_widesig_r_0_gi(widesig_r_0),
.p_mix_widesig_r_10_gi(widesig_r_10),
.p_mix_widesig_r_11_gi(widesig_r_11),
.p_mix_widesig_r_12_gi(widesig_r_12),
.p_mix_widesig_r_13_gi(widesig_r_13),
.p_mix_widesig_r_14_gi(widesig_r_14),
.p_mix_widesig_r_15_gi(widesig_r_15),
.p_mix_widesig_r_16_gi(widesig_r_16),
.p_mix_widesig_r_17_gi(widesig_r_17),
.p_mix_widesig_r_18_gi(widesig_r_18),
.p_mix_widesig_r_19_gi(widesig_r_19),
.p_mix_widesig_r_1_gi(widesig_r_1),
.p_mix_widesig_r_20_gi(widesig_r_20),
.p_mix_widesig_r_21_gi(widesig_r_21),
.p_mix_widesig_r_22_gi(widesig_r_22),
.p_mix_widesig_r_23_gi(widesig_r_23),
.p_mix_widesig_r_24_gi(widesig_r_24),
.p_mix_widesig_r_25_gi(widesig_r_25),
.p_mix_widesig_r_26_gi(widesig_r_26),
.p_mix_widesig_r_27_gi(widesig_r_27),
.p_mix_widesig_r_28_gi(widesig_r_28),
.p_mix_widesig_r_29_gi(widesig_r_29),
.p_mix_widesig_r_2_gi(widesig_r_2),
.p_mix_widesig_r_30_gi(widesig_r_30),
.p_mix_widesig_r_3_gi(widesig_r_3),
.p_mix_widesig_r_4_gi(widesig_r_4),
.p_mix_widesig_r_5_gi(widesig_r_5),
.p_mix_widesig_r_6_gi(widesig_r_6),
.p_mix_widesig_r_7_gi(widesig_r_7),
.p_mix_widesig_r_8_gi(widesig_r_8),
.p_mix_widesig_r_9_gi(widesig_r_9),
.widesig_i(widesig)
);
// End of Generated Instance Port Map for inst_e
endmodule
//
// End of Generated Module rtl of inst_t_e
//
//
//!End of Module/s
// --------------------------------------------------------------
|
// This file is the testbench for D_memory.v
module memory_tb;
parameter ASIZE=16;
parameter DSIZE=16;
reg clk;
reg rst;
reg cs;
reg wen;
reg [ASIZE-1:0] address;
reg [DSIZE-1:0] data_in;
reg [3:0] fileid;
wire [DSIZE-1:0] data_out;
`define TEST_LIMIT 20
memory m0 (
.clk(clk),
.rst(rst),
.cs(cs),
.wen(wen),
.addr(address),
.data_in(data_in),
.fileid(fileid),
.data_out(data_out)
);
integer i;
// generate the clk
always #5 clk = ~clk;
initial
begin
clk = 0; rst = 0; fileid = 0;
wen = 1; //active low (disabled)
cs = 0; //active high -- enabled during cycle asking for read or write to register a request
data_in=16'hFFFF;
address = 0;
#10 rst = 1;
#10 rst = 0;
//wait for end of initialization
//first read at correct rate
//apply an address, wait 3 cycles, and the data should return
for (i = 0; i < 20; i = i + 1)
begin
cs = 1;
$write("%0dns: Data[%h] = ",$time,address);
#10 cs = 0;
#20 address = address + 1;
$write("%h\n", data_out);
end
address = 0;
wen = 0;
#50;
//now write at the correct rate
//apply an address, wait 3 cycles, and the data is written
for(i=0; i < `TEST_LIMIT; i = i + 1)
begin
cs = 1;
$write("%0dns: Write Data %h to Address %h\n",$time, data_in, address);
#10 cs = 0;
#20 address = address +1;
data_in = data_in -1;
end
//re-read those addresses at the correct rate
address = 0;
wen =1 ;
#50;
for (i = 0; i < `TEST_LIMIT; i = i + 1)
begin
cs = 1;
$write("%0dns: Data[%h] = ",$time,address);
#10 cs = 0;
#20 address = address + 1;
$write("%h\n", data_out);
end
address = 0;
#50;
//now, demonstrate that reading at the wrong rate doesn't actually read all of the data
for (i = 0; i < `TEST_LIMIT; i = i + 1)
begin
cs = 1;
$write("%0dns: Data[%h] = ",$time,address);
#10 address = address + 1;
$write("%h\n", data_out);
end
address = 0;
data_in = 16'h00FF;
cs = 0;
//and that writing at the wrong rate doesn't actually write all the data
#50;
wen = 0;
for (i = 0; i < `TEST_LIMIT; i = i + 1)
begin
cs = 1;
$write("%0dns: Write Data %h to Address %h\n",$time, data_in, address);
#10 address = address + 1;
data_in = data_in - 1;
end
cs = 0;
#50;
address = 0;
wen = 1;
//and one final reading at the correct rate to see what happened.
for (i = 0; i < `TEST_LIMIT; i = i + 1)
begin
cs = 1;
$write("%0dns: Data[%h] = ",$time,address);
#10 cs = 0;
#20 address = address + 1;
$write("%h\n", data_out);
end
#100 $finish;
end
endmodule // end of testbench module
|
/*
* Copyright 2012, Homer Hsing <[email protected]>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
`timescale 1ns / 1ps
`define P 20
`define M 503 // M is the degree of the irreducible polynomial
`define WIDTH (2*`M-1) // width for a GF(3^M) element
`define WIDTH_D0 (1008-1)
module test_pe;
// Inputs
reg clk;
reg reset;
reg [10:0] ctrl;
reg [`WIDTH_D0:0] d0;
reg [`WIDTH:0] d1;
reg [`WIDTH:0] d2;
reg [`WIDTH:0] wish;
// Outputs
wire [`WIDTH:0] out;
// Instantiate the Unit Under Test (UUT)
PE uut (
.clk(clk),
.reset(reset),
.ctrl(ctrl),
.d0(d0),
.d1(d1),
.d2(d2),
.out(out)
);
initial begin
// Initialize Inputs
clk = 0;
reset = 0;
ctrl = 0;
d0 = 0;
d1 = 0;
d2 = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
// test mult
d0 = 1006'h1119248464094a51549514585519508512555548915458194454a95a5a6550224816556284a5412965419544014a511556aa55955144aa5699655618601a19691a6691682455451456154a4585906a8615595595560656a15511545a9029959510158140619554a45a96a199aa69010216541569025125a4999591561495;
d1 = 1006'h1a55960985561659551851556895049209954912568a591559455151a6a96614a415025691809658645a12a415a665241565a565896195925a558154045551590a9610255981a119295065a605955445a165985126506828941554156694564a29585611655965010115198aa64986559214641456656425290954464964;
d2 = d1;
wish = 1006'h296690698528561902a89185a6682428590645221996249986180602212996548298118549a161545666651980291a9806a99a9911a2044444908214800aaa04402a2209496440aa11991aa5949a0152899416598196510996a5a50629996aa68a4a9150058552196045aa42209094906684805604282410248094120a61;
@(negedge clk);
reset=1;#`P reset=0;
ctrl=11'b11111_000000; #`P;
ctrl=11'b00000_111111; #(168*`P);
check;
// test cubic
d0 = {6'b10101, 1002'd0};
d1 = 1006'h1119248464094a51549514585519508512555548915458194454a95a5a6550224816556284a5412965419544014a511556aa55955144aa5699655618601a19691a6691682455451456154a4585906a8615595595560656a15511545a9029959510158140619554a45a96a199aa69010216541569025125a4999591561495;
d2 = d1;
wish = 1006'h25025a210a560a450298548062454110aa9458192245809a45964889a65a258440598a41411492199a15615080a4159911826049059a691598688804a991996924864959490519956855484104849a08904919aa59886a56859269504516a0aa604a49215a25a129458a6944aa5495981061589105441842001a50899565;
@(negedge clk);
reset=1;#`P reset=0;
ctrl=11'b11111_000000; #`P;
ctrl=1; #(`P);
check;
// test add
d0 = {6'b000101, 1002'd0};
d1 = 1006'h1119248464094a51549514585519508512555548915458194454a95a5a6550224816556284a5412965419544014a511556aa55955144aa5699655618601a19691a6691682455451456154a4585906a8615595595560656a15511545a9029959510158140619554a45a96a199aa69010216541569025125a4999591561495;
d2 = 1006'h1a55960985561659551851556895049209954912568a591559455151a6a96614a415025691809658645a12a415a665241565a565896195925a558154045551590a9610255981a119295065a605955445a165985126506828941554156694564a29585611655965010115198aa64986559214641456656425290954464964;
wish = 1006'h28628a81295051aaa9a165a181a25454182a925a2412a52291990aa80112860620285485556514459998a4281621860968100a0a1aa54025248a146064606a861509a151411626214065a0288a65820886822126495682992926a8600681281009611451962289a558a88a5451a68454a568494155865999869225995109;
@(negedge clk);
reset=1;#`P reset=0;
ctrl=11'b11111_000000; #`P;
ctrl=11'b10001; #(`P);
check;
// test sub
d0 = {6'b001001, 1002'd0};
d1 = 1006'h1119248464094a51549514585519508512555548915458194454a95a5a6550224816556284a5412965419544014a511556aa55955144aa5699655618601a19691a6691682455451456154a4585906a8615595595560656a15511545a9029959510158140619554a45a96a199aa69010216541569025125a4999591561495;
d2 = 1006'h1a55960985561659551851556895049209954912568a591559455151a6a96614a415025691809658645a12a415a665241565a565896195925a558154045551590a9610255981a119295065a605955445a165985126506828941554156694564a29585611655965010115198aa64986559214641456656425290954464964;
wish = 1006'h0684518aa2a664040289860629445826158018694a9902042a125809a488291a940156182625aa9101268690289428214145a060941615844210958468858810109081469a94940a69851592800a16416424894460a62a85810800456955425a26896a62084822a65981941204204aa94440a155a8288182a09849109a61;
@(negedge clk);
reset=1;#`P reset=0;
ctrl=11'b11111_000000; #`P;
ctrl=11'b10001; #(`P);
check;
$display("Good!");
$finish;
end
initial #100 forever #(`P/2) clk = ~clk;
task check;
begin
if (out !== wish)
begin $display("E %h %h", out, wish); $finish; end
end
endtask
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A221OI_PP_SYMBOL_V
`define SKY130_FD_SC_LS__A221OI_PP_SYMBOL_V
/**
* a221oi: 2-input AND into first two inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | C1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__a221oi (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
input B2 ,
input C1 ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__A221OI_PP_SYMBOL_V
|
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.