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// Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2015.2 (lin64) Build 1266856 Fri Jun 26 16:35:25 MDT 2015
// Date : Mon Nov 30 13:52:22 2015
// Host : centennial.andrew.cmu.edu running 64-bit Red Hat Enterprise Linux Server release 7.2 (Maipo)
// Command : write_verilog -force -mode synth_stub
// /afs/ece.cmu.edu/usr/rmrobert/Private/18545/Atari7800/Atari7900/Atari7900.srcs/sources_1/ip/DIGDUG_ROM_1/DIGDUG_ROM_stub.v
// Design : DIGDUG_ROM
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "blk_mem_gen_v8_2,Vivado 2015.2" *)
module DIGDUG_ROM(clka, addra, douta)
/* synthesis syn_black_box black_box_pad_pin="clka,addra[13:0],douta[7:0]" */;
input clka;
input [13:0]addra;
output [7:0]douta;
endmodule
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// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: sparc_ifu_errdp.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Module Name: sparc_ifu_errdp
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
`include "lsu.h"
`include "ifu.h"
module sparc_ifu_errdp(/*AUTOARG*/
// Outputs
so, ifu_lsu_ldxa_data_w2, erb_dtu_imask, erd_erc_tlbt_pe_s1,
erd_erc_tlbd_pe_s1, erd_erc_tagpe_s1, erd_erc_nirpe_s1,
erd_erc_fetpe_s1, erd_erc_tte_pgsz,
// Inputs
rclk, se, si, erb_reset, itlb_rd_tte_data, itlb_rd_tte_tag,
itlb_ifq_paddr_s, wsel_fdp_fetdata_s1, wsel_fdp_topdata_s1,
wsel_erb_asidata_s, ict_itlb_tags_f, icv_itlb_valid_f,
lsu_ifu_err_addr, spu_ifu_err_addr_w2, fdp_erb_pc_f,
exu_ifu_err_reg_m, exu_ifu_err_synd_m, ffu_ifu_err_reg_w2,
ffu_ifu_err_synd_w2, tlu_itlb_rw_index_g, erc_erd_pgsz_b0,
erc_erd_pgsz_b1, erc_erd_erren_asidata, erc_erd_errstat_asidata,
erc_erd_errinj_asidata, ifq_erb_asidata_i2, ifq_erb_wrtag_f,
ifq_erb_wrindex_f, erc_erd_asiway_s1_l, fcl_erb_itlbrd_data_s,
erc_erd_ld_imask, erc_erd_asisrc_sel_icd_s_l,
erc_erd_asisrc_sel_misc_s_l, erc_erd_asisrc_sel_err_s_l,
erc_erd_asisrc_sel_itlb_s_l, erc_erd_errasi_sel_en_l,
erc_erd_errasi_sel_stat_l, erc_erd_errasi_sel_inj_l,
erc_erd_errasi_sel_addr_l, erc_erd_miscasi_sel_ict_l,
erc_erd_miscasi_sel_imask_l, erc_erd_miscasi_sel_other_l,
erc_erd_asi_thr_l, erc_erd_eadr0_sel_irf_l,
erc_erd_eadr0_sel_itlb_l, erc_erd_eadr0_sel_frf_l,
erc_erd_eadr0_sel_lsu_l, erc_erd_eadr1_sel_pcd1_l,
erc_erd_eadr1_sel_l1pa_l, erc_erd_eadr1_sel_l2pa_l,
erc_erd_eadr1_sel_other_l, erc_erd_eadr2_sel_mx1_l,
erc_erd_eadr2_sel_wrt_l, erc_erd_eadr2_sel_mx0_l,
erc_erd_eadr2_sel_old_l
);
input rclk,
se,
si,
erb_reset;
input [42:0] itlb_rd_tte_data; // this is in s1
input [58:0] itlb_rd_tte_tag; // this is in s1
input [39:10] itlb_ifq_paddr_s;
input [33:0] wsel_fdp_fetdata_s1,
wsel_fdp_topdata_s1;
input [33:0] wsel_erb_asidata_s;
input [`IC_TAG_ALL_HI:0] ict_itlb_tags_f;
input [3:0] icv_itlb_valid_f;
input [47:4] lsu_ifu_err_addr;
input [39:4] spu_ifu_err_addr_w2;
input [47:0] fdp_erb_pc_f;
input [7:0] exu_ifu_err_reg_m;
input [7:0] exu_ifu_err_synd_m;
input [5:0] ffu_ifu_err_reg_w2;
input [13:0] ffu_ifu_err_synd_w2;
input [5:0] tlu_itlb_rw_index_g;
input erc_erd_pgsz_b0,
erc_erd_pgsz_b1;
input [1:0] erc_erd_erren_asidata;
input [22:0] erc_erd_errstat_asidata;
input [31:0] erc_erd_errinj_asidata;
input [47:0] ifq_erb_asidata_i2;
input [`IC_TAG_SZ-1:0] ifq_erb_wrtag_f;
input [`IC_IDX_HI:4] ifq_erb_wrindex_f;
// mux selects
input [3:0] erc_erd_asiway_s1_l;
input fcl_erb_itlbrd_data_s;
input erc_erd_ld_imask;
input erc_erd_asisrc_sel_icd_s_l,
erc_erd_asisrc_sel_misc_s_l,
erc_erd_asisrc_sel_err_s_l,
erc_erd_asisrc_sel_itlb_s_l;
input erc_erd_errasi_sel_en_l,
erc_erd_errasi_sel_stat_l,
erc_erd_errasi_sel_inj_l,
erc_erd_errasi_sel_addr_l;
input erc_erd_miscasi_sel_ict_l,
erc_erd_miscasi_sel_imask_l,
erc_erd_miscasi_sel_other_l;
input [3:0] erc_erd_asi_thr_l;
input [3:0] erc_erd_eadr0_sel_irf_l,
erc_erd_eadr0_sel_itlb_l,
erc_erd_eadr0_sel_frf_l,
erc_erd_eadr0_sel_lsu_l;
input [3:0] erc_erd_eadr1_sel_pcd1_l,
erc_erd_eadr1_sel_l1pa_l,
erc_erd_eadr1_sel_l2pa_l,
erc_erd_eadr1_sel_other_l;
input [3:0] erc_erd_eadr2_sel_mx1_l,
erc_erd_eadr2_sel_wrt_l,
erc_erd_eadr2_sel_mx0_l,
erc_erd_eadr2_sel_old_l;
output so;
output [63:0] ifu_lsu_ldxa_data_w2;
output [38:0] erb_dtu_imask;
// output [9:0] erb_ifq_paddr_s;
output [1:0] erd_erc_tlbt_pe_s1,
erd_erc_tlbd_pe_s1;
output [3:0] erd_erc_tagpe_s1;
output erd_erc_nirpe_s1,
erd_erc_fetpe_s1;
output [2:0] erd_erc_tte_pgsz;
//
// local signals
//
wire [47:4] lsu_err_addr;
wire [`IC_TAG_ALL_HI:0] ictags_s1;
wire [3:0] icv_data_s1;
wire [31:0] tag_asi_data;
wire [47:4] t0_eadr_mx0_out,
t1_eadr_mx0_out,
t2_eadr_mx0_out,
t3_eadr_mx0_out,
t0_eadr_mx1_out,
t1_eadr_mx1_out,
t2_eadr_mx1_out,
t3_eadr_mx1_out;
wire [47:4] t0_err_addr_nxt,
t0_err_addr,
t1_err_addr_nxt,
t1_err_addr,
t2_err_addr_nxt,
t2_err_addr,
t3_err_addr_nxt,
t3_err_addr;
wire [47:4] err_addr_asidata;
wire [63:0] formatted_tte_data,
formatted_tte_tag,
tlb_asi_data,
misc_asi_data,
err_asi_data,
ldxa_data_s,
ldxa_data_d;
wire [39:4] paddr_s1,
paddr_d1;
wire [39:4] ifet_addr_f;
wire [47:0] pc_s1;
wire [47:4] pc_d1;
wire [7:0] irfaddr_w,
irfsynd_w;
wire irfaddr_4_w;
wire [5:0] itlb_asi_index;
wire [38:0] imask_next;
wire clk;
//
// Code Begins Here
//
assign clk = rclk;
//-------------
// Tags
//-------------
dff_s #(`IC_TAG_ALL) tags_reg(.din (ict_itlb_tags_f),
.q (ictags_s1),
.clk (clk),
.se (se), .si(), .so());
dff_s #(4) vbits_reg(.din (icv_itlb_valid_f[3:0]),
.q (icv_data_s1),
.clk (clk), .se(se), .si(), .so());
// check parity
sparc_ifu_par32 tag_par0(.in ({3'b0, ictags_s1[`IC_TAG_SZ:0]}),
.out (erd_erc_tagpe_s1[0]));
sparc_ifu_par32 tag_par1(.in ({3'b0, ictags_s1[((2*`IC_TAG_SZ) + 1):(`IC_TAG_SZ+1)]}),
.out (erd_erc_tagpe_s1[1]));
sparc_ifu_par32 tag_par2(.in ({3'b0, ictags_s1[((3*`IC_TAG_SZ) + 2):(2*(`IC_TAG_SZ)+2)]}),
.out (erd_erc_tagpe_s1[2]));
sparc_ifu_par32 tag_par3(.in ({3'b0, ictags_s1[((4*`IC_TAG_SZ) + 3):(3*(`IC_TAG_SZ)+3)]}),
.out (erd_erc_tagpe_s1[3]));
dp_mux4ds #(32) asitag_mux(.dout (tag_asi_data[31:0]),
.in0 ({icv_data_s1[0], 1'b0, ictags_s1[28], 1'b0, ictags_s1[27:0]}),
.in1 ({icv_data_s1[1], 1'b0, ictags_s1[57], 1'b0, ictags_s1[56:29]}),
.in2 ({icv_data_s1[2], 1'b0, ictags_s1[86], 1'b0, ictags_s1[85:58]}),
.in3 ({icv_data_s1[3], 1'b0, ictags_s1[115], 1'b0, ictags_s1[114:87]}),
.sel0_l (erc_erd_asiway_s1_l[0]),
.sel1_l (erc_erd_asiway_s1_l[1]),
.sel2_l (erc_erd_asiway_s1_l[2]),
.sel3_l (erc_erd_asiway_s1_l[3]));
//------------------
// Data
//------------------
// parity check on instruction
// This may have to be done in the next stage (at least partially)
sparc_ifu_par34 nir_par(.in (wsel_fdp_topdata_s1[33:0]),
.out (erd_erc_nirpe_s1));
sparc_ifu_par34 inst_par(.in (wsel_fdp_fetdata_s1[33:0]),
.out (erd_erc_fetpe_s1));
//----------------------------------------------------------------------
// TLB read data
//----------------------------------------------------------------------
//`ifdef SPARC_HPV_EN
// don't include v(26) and u(24) bits in parity
sparc_ifu_par32 tt_tag_par0(.in ({itlb_rd_tte_tag[33:27],
itlb_rd_tte_tag[25],
itlb_rd_tte_tag[23:0]}),
.out (erd_erc_tlbt_pe_s1[0]));
//`else
// // don't include v(28) and u(26) bits in parity
// sparc_ifu_par32 tt_tag_par0(.in ({itlb_rd_tte_tag[33:29],
// itlb_rd_tte_tag[27],
// itlb_rd_tte_tag[25:0]}),
// .out (erd_erc_tlbt_pe_s1[0]));
//`endif // !`ifdef SPARC_HPV_EN
sparc_ifu_par32 tt_tag_par1(.in ({7'b0, itlb_rd_tte_tag[58:34]}),
.out (erd_erc_tlbt_pe_s1[1]));
sparc_ifu_par32 tt_data_par0(.in (itlb_rd_tte_data[31:0]),
.out (erd_erc_tlbd_pe_s1[0]));
sparc_ifu_par16 tt_data_par1(.in ({5'b0, itlb_rd_tte_data[42:32]}),
.out (erd_erc_tlbd_pe_s1[1]));
// assign erd_erc_tte_lock_s1 = itlb_rd_tte_data[`STLB_DATA_L];
//`ifdef SPARC_HPV_EN
assign erd_erc_tte_pgsz[2:0] = {itlb_rd_tte_data[`STLB_DATA_27_22_SEL],
itlb_rd_tte_data[`STLB_DATA_21_16_SEL],
itlb_rd_tte_data[`STLB_DATA_15_13_SEL]};
assign formatted_tte_tag[63:0] =
{
// `ifdef SUN4V_TAG_RD
// implement this!
itlb_rd_tte_tag[58:55],
// `else
// {4{itlb_rd_tte_tag[53]}}, // 4b
// `endif
itlb_rd_tte_tag[`STLB_TAG_PARITY], // Parity 1b
itlb_rd_tte_tag[`STLB_TAG_VA_27_22_V], // mxsel2 - b27:22 vld 1b
itlb_rd_tte_tag[`STLB_TAG_VA_21_16_V], // mxsel1 - b21:16 vld 1b
itlb_rd_tte_tag[`STLB_TAG_VA_15_13_V], // mxsel0 - b15:13 vld 1b
{8{itlb_rd_tte_tag[53]}}, // 8b
itlb_rd_tte_tag[`STLB_TAG_VA_47_28_HI:`STLB_TAG_VA_47_28_LO], // 20b
itlb_rd_tte_tag[`STLB_TAG_VA_27_22_HI:`STLB_TAG_VA_27_22_LO], // 6b
itlb_rd_tte_tag[`STLB_TAG_VA_21_16_HI:`STLB_TAG_VA_21_16_LO], // 6b
itlb_rd_tte_tag[`STLB_TAG_VA_15_13_HI:`STLB_TAG_VA_15_13_LO], // 3b
itlb_rd_tte_tag[`STLB_TAG_CTXT_12_0_HI:`STLB_TAG_CTXT_12_0_LO]// 13b
} ;
//`else
// assign erd_erc_tte_pgsz[2:0] = {itlb_rd_tte_data[`STLB_DATA_21_19_SEL],
// itlb_rd_tte_data[`STLB_DATA_18_16_SEL],
// itlb_rd_tte_data[`STLB_DATA_15_13_SEL]};
//
// assign formatted_tte_tag[63:0] =
// {
// {16{itlb_rd_tte_tag[54]}}, // 16b
// itlb_rd_tte_tag[`STLB_TAG_VA_47_22_HI:`STLB_TAG_VA_47_22_LO], // 26b
// itlb_rd_tte_tag[`STLB_TAG_VA_21_20_HI:`STLB_TAG_VA_21_20_LO], // 3b
// itlb_rd_tte_tag[`STLB_TAG_VA_19],
// itlb_rd_tte_tag[`STLB_TAG_VA_18_17_HI:`STLB_TAG_VA_18_17_LO], // 3b
// itlb_rd_tte_tag[`STLB_TAG_VA_16],
// itlb_rd_tte_tag[`STLB_TAG_VA_15_14_HI:`STLB_TAG_VA_15_14_LO], // 3b
// itlb_rd_tte_tag[`STLB_TAG_VA_13],
// itlb_rd_tte_tag[`STLB_TAG_CTXT_12_7_HI:`STLB_TAG_CTXT_12_7_LO],//13b
// itlb_rd_tte_tag[`STLB_TAG_CTXT_6_0_HI:`STLB_TAG_CTXT_6_0_LO]
// } ;
//`endif // !`ifdef SPARC_HPV_EN
//`ifdef SPARC_HPV_EN
assign formatted_tte_data[63:0] =
{
itlb_rd_tte_tag[`STLB_TAG_V], // V (1b)
erc_erd_pgsz_b1, // pg SZ msb 4m or 512k
erc_erd_pgsz_b0, // pg sz lsb 4m or 64k
itlb_rd_tte_data[`STLB_DATA_NFO], // NFO (1b)
itlb_rd_tte_data[`STLB_DATA_IE], // IE (1b)
10'b0, // soft2
itlb_rd_tte_data[`STLB_DATA_27_22_SEL], // pgsz b2
itlb_rd_tte_tag[`STLB_TAG_U],
itlb_rd_tte_data[`STLB_DATA_PARITY], // Parity (1b)
itlb_rd_tte_data[`STLB_DATA_27_22_SEL], // mxsel2_l (1b)
itlb_rd_tte_data[`STLB_DATA_21_16_SEL], // mxsel1_l (1b)
itlb_rd_tte_data[`STLB_DATA_15_13_SEL], // mxsel0_l (1b)
2'b0, // unused diag 2b
1'b0, // ?? PA (28b)
itlb_rd_tte_data[`STLB_DATA_PA_39_28_HI:`STLB_DATA_PA_39_28_LO],
itlb_rd_tte_data[`STLB_DATA_PA_27_22_HI:`STLB_DATA_PA_27_22_LO],
itlb_rd_tte_data[`STLB_DATA_PA_21_16_HI:`STLB_DATA_PA_21_16_LO],
itlb_rd_tte_data[`STLB_DATA_PA_15_13_HI:`STLB_DATA_PA_15_13_LO],
6'b0, // ?? 12-7 (6b)
itlb_rd_tte_data[`STLB_DATA_L], // L (1b)
itlb_rd_tte_data[`STLB_DATA_CP], // CP (1b)
itlb_rd_tte_data[`STLB_DATA_CV], // CV (1b)
itlb_rd_tte_data[`STLB_DATA_E], // E (1b)
itlb_rd_tte_data[`STLB_DATA_P], // P (1b)
itlb_rd_tte_data[`STLB_DATA_W], // W (1b)
1'b0
} ;
//`else // !`ifdef SPARC_HPV_EN
//
// assign formatted_tte_data[63:0] =
// {
// itlb_rd_tte_tag[`STLB_TAG_V], // V (1b)
// erc_erd_pgsz_b1, // pg SZ msb 4m or 512k
// erc_erd_pgsz_b0, // pg sz lsb 4m or 64k
// itlb_rd_tte_data[`STLB_DATA_NFO], // NFO (1b)
// itlb_rd_tte_data[`STLB_DATA_IE], // IE (1b)
// 9'b0, // soft2 58-42 (17b)
// 8'b0, // diag 8b
// itlb_rd_tte_tag[`STLB_TAG_U], // U (1b)
// 1'b0, // ?? PA (28b)
// itlb_rd_tte_data[`STLB_DATA_PA_39_22_HI:`STLB_DATA_PA_39_22_LO],
// itlb_rd_tte_data[`STLB_DATA_PA_21_19_HI:`STLB_DATA_PA_21_19_LO],
// itlb_rd_tte_data[`STLB_DATA_PA_18_16_HI:`STLB_DATA_PA_18_16_LO],
// itlb_rd_tte_data[`STLB_DATA_PA_15_13_HI:`STLB_DATA_PA_15_13_LO],
// 6'b0, // ?? 12-7 (6b)
// itlb_rd_tte_data[`STLB_DATA_L], // L (1b)
// itlb_rd_tte_data[`STLB_DATA_CP], // CP (1b)
// itlb_rd_tte_data[`STLB_DATA_CV], // CV (1b)
// itlb_rd_tte_data[`STLB_DATA_E], // E (1b)
// itlb_rd_tte_data[`STLB_DATA_P], // P (1b)
// itlb_rd_tte_data[`STLB_DATA_W], // W (1b)
// itlb_rd_tte_data[`STLB_DATA_G] // G (1b)
// } ;
//`endif // !`ifdef SPARC_HPV_EN
// mux in all asi values
dp_mux2es #(64) itlbrd_mux(.dout (tlb_asi_data[63:0]),
.in0 (formatted_tte_tag[63:0]),
.in1 (formatted_tte_data[63:0]),
.sel (fcl_erb_itlbrd_data_s));
dp_mux4ds #(64) err_mux(.dout (err_asi_data[63:0]),
.in0 ({62'b0, erc_erd_erren_asidata}),
.in1 ({32'b0, erc_erd_errstat_asidata, 9'b0}),
.in2 ({32'b0, erc_erd_errinj_asidata}),
.in3 ({16'b0, err_addr_asidata, 4'b0}),
.sel0_l (erc_erd_errasi_sel_en_l),
.sel1_l (erc_erd_errasi_sel_stat_l),
.sel2_l (erc_erd_errasi_sel_inj_l),
.sel3_l (erc_erd_errasi_sel_addr_l));
dp_mux3ds #(64) misc_asi_mux(.dout (misc_asi_data[63:0]),
.in0 ({29'b0,
tag_asi_data[31:28],
3'b0,
tag_asi_data[27:0]}),
.in1 ({25'b0, erb_dtu_imask}),
.in2 (64'b0),
.sel0_l (erc_erd_miscasi_sel_ict_l),
.sel1_l (erc_erd_miscasi_sel_imask_l),
.sel2_l (erc_erd_miscasi_sel_other_l));
// Final asi data
// May need to add a flop to this mux output before sending it to the LSU
dp_mux4ds #(64) final_asi_mux(.dout (ldxa_data_s),
.in0 (tlb_asi_data[63:0]),
.in1 (err_asi_data),
.in2 (misc_asi_data),
.in3 ({30'b0,
wsel_erb_asidata_s[0],
wsel_erb_asidata_s[33:1]}),
.sel0_l (erc_erd_asisrc_sel_itlb_s_l),
.sel1_l (erc_erd_asisrc_sel_err_s_l),
.sel2_l (erc_erd_asisrc_sel_misc_s_l),
.sel3_l (erc_erd_asisrc_sel_icd_s_l));
dff_s #(64) ldxa_reg(.din (ldxa_data_s),
.q (ldxa_data_d),
.clk (clk), .se(se), .si(), .so());
assign ifu_lsu_ldxa_data_w2 = ldxa_data_d;
//----------------------------------------
// Error Address
//----------------------------------------
assign ifet_addr_f = {ifq_erb_wrtag_f[`IC_TAG_SZ-1:0],
ifq_erb_wrindex_f[`IC_IDX_HI:4]};
// pc of latest access
dff_s #(48) pcs1_reg(.din (fdp_erb_pc_f[47:0]),
.q (pc_s1[47:0]),
.clk (clk), .se(se), .si(), .so());
// Physical address
assign paddr_s1[39:10] = itlb_ifq_paddr_s[39:10];
assign paddr_s1[9:4] = pc_s1[9:4];
dff_s #(36) padd_reg(.din (paddr_s1[39:4]),
.q (paddr_d1[39:4]),
.clk (clk), .se(se), .si(), .so());
// assign erb_ifq_paddr_s[9:0] = pc_s1[9:0];
// stage PC one more cycle
dff_s #(44) pcd1_reg(.din (pc_s1[47:4]),
.q (pc_d1[47:4]),
.clk (clk), .se(se), .si(), .so());
// IRF address
dff_s #(16) irf_reg(.din ({exu_ifu_err_reg_m[7:0],
exu_ifu_err_synd_m[7:0]}),
.q ({irfaddr_w[7:5],
irfaddr_4_w,
irfaddr_w[3:0],
irfsynd_w[7:0]}),
.clk (clk), .se(se), .si(), .so());
// fix for bug 5594
// nand2 + xnor
assign irfaddr_w[4] = irfaddr_4_w ^ (irfaddr_w[5] & irfaddr_w[3]);
// itlb asi address
dff_s #(6) itlbidx_reg(.din (tlu_itlb_rw_index_g),
.q (itlb_asi_index),
.clk (clk), .se(se), .si(), .so());
// lsu error address
dff_s #(44) lsadr_reg(.din (lsu_ifu_err_addr),
.q (lsu_err_addr),
.clk (clk), .se(se), .si(), .so());
// mux in the different error addresses
// thread 0
dp_mux4ds #(44) t0_eadr_mx0(.dout (t0_eadr_mx0_out),
.in0 ({24'b0, irfsynd_w[7:0], 4'b0, irfaddr_w[7:0]}),
.in1 ({38'b0, itlb_asi_index}),
.in2 ({17'b0, ffu_ifu_err_synd_w2[13:7],
1'b0, ffu_ifu_err_synd_w2[6:0],
6'b0, ffu_ifu_err_reg_w2[5:0]}),
.in3 (lsu_err_addr),
.sel0_l (erc_erd_eadr0_sel_irf_l[0]),
.sel1_l (erc_erd_eadr0_sel_itlb_l[0]),
.sel2_l (erc_erd_eadr0_sel_frf_l[0]),
.sel3_l (erc_erd_eadr0_sel_lsu_l[0]));
dp_mux4ds #(44) t0_eadr_mx1(.dout (t0_eadr_mx1_out),
.in0 (pc_d1[47:4]),
.in1 ({8'b0, paddr_d1[39:4]}),
.in2 ({8'b0, ifet_addr_f}),
.in3 ({8'b0, spu_ifu_err_addr_w2[39:4]}),
.sel0_l (erc_erd_eadr1_sel_pcd1_l[0]),
.sel1_l (erc_erd_eadr1_sel_l1pa_l[0]),
.sel2_l (erc_erd_eadr1_sel_l2pa_l[0]),
.sel3_l (erc_erd_eadr1_sel_other_l[0]));
dp_mux4ds #(44) t0_eadr_mx2(.dout (t0_err_addr_nxt),
.in0 (t0_eadr_mx0_out),
.in1 (t0_eadr_mx1_out),
.in2 (ifq_erb_asidata_i2[47:4]),
.in3 (t0_err_addr),
.sel0_l (erc_erd_eadr2_sel_mx0_l[0]),
.sel1_l (erc_erd_eadr2_sel_mx1_l[0]),
.sel2_l (erc_erd_eadr2_sel_wrt_l[0]),
.sel3_l (erc_erd_eadr2_sel_old_l[0]));
dff_s #(44) t0_eadr_reg(.din (t0_err_addr_nxt),
.q (t0_err_addr),
.clk (clk), .se(se), .si(), .so());
`ifdef FPGA_SYN_1THREAD
assign err_addr_asidata = t0_err_addr;
`else
// thread 1
dp_mux4ds #(44) t1_eadr_mx0(.dout (t1_eadr_mx0_out),
.in0 ({24'b0, irfsynd_w[7:0], 4'b0, irfaddr_w[7:0]}),
.in1 ({38'b0, itlb_asi_index}),
.in2 ({17'b0, ffu_ifu_err_synd_w2[13:7],
1'b0, ffu_ifu_err_synd_w2[6:0],
6'b0, ffu_ifu_err_reg_w2[5:0]}),
.in3 (lsu_err_addr),
.sel0_l (erc_erd_eadr0_sel_irf_l[1]),
.sel1_l (erc_erd_eadr0_sel_itlb_l[1]),
.sel2_l (erc_erd_eadr0_sel_frf_l[1]),
.sel3_l (erc_erd_eadr0_sel_lsu_l[1]));
dp_mux4ds #(44) t1_eadr_mx1(.dout (t1_eadr_mx1_out),
.in0 (pc_d1[47:4]),
.in1 ({8'b0, paddr_d1[39:4]}),
.in2 ({8'b0, ifet_addr_f}),
.in3 ({8'b0, spu_ifu_err_addr_w2[39:4]}),
// .in3 ({44'b0}),
.sel0_l (erc_erd_eadr1_sel_pcd1_l[1]),
.sel1_l (erc_erd_eadr1_sel_l1pa_l[1]),
.sel2_l (erc_erd_eadr1_sel_l2pa_l[1]),
.sel3_l (erc_erd_eadr1_sel_other_l[1]));
dp_mux4ds #(44) t1_eadr_mx2(.dout (t1_err_addr_nxt),
.in0 (t1_eadr_mx0_out),
.in1 (t1_eadr_mx1_out),
.in2 (ifq_erb_asidata_i2[47:4]),
.in3 (t1_err_addr),
.sel0_l (erc_erd_eadr2_sel_mx0_l[1]),
.sel1_l (erc_erd_eadr2_sel_mx1_l[1]),
.sel2_l (erc_erd_eadr2_sel_wrt_l[1]),
.sel3_l (erc_erd_eadr2_sel_old_l[1]));
dff_s #(44) t1_eadr_reg(.din (t1_err_addr_nxt),
.q (t1_err_addr),
.clk (clk), .se(se), .si(), .so());
// thread 2
dp_mux4ds #(44) t2_eadr_mx0(.dout (t2_eadr_mx0_out),
.in0 ({24'b0, irfsynd_w[7:0], 4'b0, irfaddr_w[7:0]}),
.in1 ({38'b0, itlb_asi_index}),
.in2 ({17'b0, ffu_ifu_err_synd_w2[13:7],
1'b0, ffu_ifu_err_synd_w2[6:0],
6'b0, ffu_ifu_err_reg_w2[5:0]}),
.in3 (lsu_err_addr),
.sel0_l (erc_erd_eadr0_sel_irf_l[2]),
.sel1_l (erc_erd_eadr0_sel_itlb_l[2]),
.sel2_l (erc_erd_eadr0_sel_frf_l[2]),
.sel3_l (erc_erd_eadr0_sel_lsu_l[2]));
dp_mux4ds #(44) t2_eadr_mx1(.dout (t2_eadr_mx1_out),
.in0 (pc_d1[47:4]),
.in1 ({8'b0, paddr_d1[39:4]}),
.in2 ({8'b0, ifet_addr_f}),
.in3 ({8'b0, spu_ifu_err_addr_w2[39:4]}),
// .in3 ({44'b0}),
.sel0_l (erc_erd_eadr1_sel_pcd1_l[2]),
.sel1_l (erc_erd_eadr1_sel_l1pa_l[2]),
.sel2_l (erc_erd_eadr1_sel_l2pa_l[2]),
.sel3_l (erc_erd_eadr1_sel_other_l[2]));
dp_mux4ds #(44) t2_eadr_mx2(.dout (t2_err_addr_nxt),
.in0 (t2_eadr_mx0_out),
.in1 (t2_eadr_mx1_out),
.in2 (ifq_erb_asidata_i2[47:4]),
.in3 (t2_err_addr),
.sel0_l (erc_erd_eadr2_sel_mx0_l[2]),
.sel1_l (erc_erd_eadr2_sel_mx1_l[2]),
.sel2_l (erc_erd_eadr2_sel_wrt_l[2]),
.sel3_l (erc_erd_eadr2_sel_old_l[2]));
dff_s #(44) t2_eadr_reg(.din (t2_err_addr_nxt),
.q (t2_err_addr),
.clk (clk), .se(se), .si(), .so());
// thread 3
dp_mux4ds #(44) t3_eadr_mx0(.dout (t3_eadr_mx0_out),
.in0 ({24'b0, irfsynd_w[7:0], 4'b0, irfaddr_w[7:0]}),
.in1 ({38'b0, itlb_asi_index}),
.in2 ({17'b0, ffu_ifu_err_synd_w2[13:7],
1'b0, ffu_ifu_err_synd_w2[6:0],
6'b0, ffu_ifu_err_reg_w2[5:0]}),
.in3 (lsu_err_addr),
.sel0_l (erc_erd_eadr0_sel_irf_l[3]),
.sel1_l (erc_erd_eadr0_sel_itlb_l[3]),
.sel2_l (erc_erd_eadr0_sel_frf_l[3]),
.sel3_l (erc_erd_eadr0_sel_lsu_l[3]));
dp_mux4ds #(44) t3_eadr_mx1(.dout (t3_eadr_mx1_out),
.in0 (pc_d1[47:4]),
.in1 ({8'b0, paddr_d1[39:4]}),
.in2 ({8'b0, ifet_addr_f}),
.in3 ({8'b0, spu_ifu_err_addr_w2[39:4]}),
// .in3 ({44'b0}),
.sel0_l (erc_erd_eadr1_sel_pcd1_l[3]),
.sel1_l (erc_erd_eadr1_sel_l1pa_l[3]),
.sel2_l (erc_erd_eadr1_sel_l2pa_l[3]),
.sel3_l (erc_erd_eadr1_sel_other_l[3]));
dp_mux4ds #(44) t3_eadr_mx2(.dout (t3_err_addr_nxt),
.in0 (t3_eadr_mx0_out),
.in1 (t3_eadr_mx1_out),
.in2 (ifq_erb_asidata_i2[47:4]),
.in3 (t3_err_addr),
.sel0_l (erc_erd_eadr2_sel_mx0_l[3]),
.sel1_l (erc_erd_eadr2_sel_mx1_l[3]),
.sel2_l (erc_erd_eadr2_sel_wrt_l[3]),
.sel3_l (erc_erd_eadr2_sel_old_l[3]));
dff_s #(44) t3_eadr_reg(.din (t3_err_addr_nxt),
.q (t3_err_addr),
.clk (clk), .se(se), .si(), .so());
// asi read
dp_mux4ds #(44) asi_eadr_mx(.dout (err_addr_asidata),
.in0 (t0_err_addr),
.in1 (t1_err_addr),
.in2 (t2_err_addr),
.in3 (t3_err_addr),
.sel0_l (erc_erd_asi_thr_l[0]),
.sel1_l (erc_erd_asi_thr_l[1]),
.sel2_l (erc_erd_asi_thr_l[2]),
.sel3_l (erc_erd_asi_thr_l[3]));
`endif
// Instruction Mask
dp_mux2es #(39) imask_en_mux(.dout (imask_next),
.in0 (erb_dtu_imask),
.in1 (ifq_erb_asidata_i2[38:0]),
.sel (erc_erd_ld_imask));
// need to reset top 7 bits only
dffr_s #(39) imask_reg(.din (imask_next),
.q (erb_dtu_imask),
.rst (erb_reset),
.clk (clk), .se(se), .si(), .so());
sink #(4) s0(.in (pc_s1[3:0]));
endmodule // sparc_ifu_erb
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: jbi_ncio_mto_slice.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
/////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
`include "sys.h" // system level definition file which contains the
// time scale definition
module jbi_ncio_mto_slice(/*AUTOARG*/
// Outputs
timeout_err,
// Inputs
clk, timeout_wrap, int_rst_l, int_vld
);
input clk;
input timeout_wrap;
input int_rst_l;
input int_vld;
output timeout_err;
////////////////////////////////////////////////////////////////////////
// Interface signal type declarations
////////////////////////////////////////////////////////////////////////
wire timeout_err;
////////////////////////////////////////////////////////////////////////
// Local signal declarations
////////////////////////////////////////////////////////////////////////
wire vld;
wire timeout;
wire next_vld;
wire next_timeout;
wire vld_rst_l;
wire timeout_rst_l;
//
// Code start here
//
assign vld_rst_l = int_rst_l;
assign next_vld = int_vld | vld;
assign timeout_rst_l = int_rst_l;
assign next_timeout = vld & (timeout_wrap | timeout);
assign timeout_err = vld & timeout_wrap & timeout;
//*******************************************************************************
// DFFRL Instantiations
//*******************************************************************************
dffrl_ns #(1) u_dffrl_vld
(.din(next_vld),
.clk(clk),
.rst_l(vld_rst_l),
.q(vld)
);
dffrl_ns #(1) u_dffrl_timeout
(.din(next_timeout),
.clk(clk),
.rst_l(timeout_rst_l),
.q(timeout)
);
endmodule
|
Require Export Iron.Language.SimpleRef.SubstExpExp.
Require Import Iron.Language.SimpleRef.Preservation.
Require Import Iron.Language.SimpleRef.Ty.
Require Export Iron.Language.SimpleRef.Step.
Require Export Iron.Language.SimpleRef.Exp.
(********************************************************************)
(** Big Step Evaluation *)
(* This is also called 'Natural Semantics'.
It provides a relation between the expression to be reduced
and its final value. *)
Inductive EVAL : heap -> exp -> heap -> exp -> Prop :=
| EvDone
: forall h v2
, value v2
-> wfH h
-> EVAL h v2 h v2
| EvLamApp
: forall h0 h1 h2 h3 x1 t11 x12 x2 v2 v3
, EVAL h0 x1 h1 (XLam t11 x12)
-> EVAL h1 x2 h2 v2
-> EVAL h2 (substX 0 v2 x12) h3 v3
-> EVAL h0 (XApp x1 x2) h3 v3
(* Heap operations *)
| EvNewRef
: forall h0 x1 h1 v1
, EVAL h0 x1 h1 v1 (* evaluate new heap value *)
-> EVAL h0 (XNewRef x1) (* push that value onto the heap *)
(v1 <: h1) (XLoc (length h1))
| EvReadRef
: forall h0 x1 h1 v2 l
, EVAL h0 x1 h1 (XLoc l) (* evaluate heap location *)
-> get l h1 = Some v2 (* lookup up that location from the heap *)
-> EVAL h0 (XReadRef x1)
h1 v2
| EvWriteRef
: forall h0 x1 h1 x2 v2 h2 l
, EVAL h0 x1 h1 (XLoc l) (* evaluate heap location *)
-> EVAL h1 x2 h2 v2 (* evaluate argument to a value *)
-> EVAL h0 (XWriteRef x1 x2)
(update l v2 h2) xUnit. (* update heap with that value*)
Hint Constructors EVAL.
(* Invert all hypothesis that are compound eval statements *)
Ltac inverts_eval :=
repeat
(match goal with
| [ H: EVAL _ (XLoc _) _ _ |- _ ] => inverts H
| [ H: EVAL _ (XCon _) _ _ |- _ ] => inverts H
| [ H: EVAL _ (XLam _ _) _ _ |- _ ] => inverts H
| [ H: EVAL _ (XApp _ _) _ _ |- _ ] => inverts H
| [ H: EVAL _ (XNewRef _) _ _ |- _ ] => inverts H
| [ H: EVAL _ (XReadRef _) _ _ |- _ ] => inverts H
| [ H: EVAL _ (XWriteRef _ _) _ _ |- _ ] => inverts H
end).
Lemma eval_value_eq
: forall h0 v0 h1 v1
, value v0
-> EVAL h0 v0 h1 v1
-> h1 = h0 /\ v1 = v0.
Proof.
intros.
destruct v0; inverts_eval; nope; eauto.
Qed.
(* A terminating big-step evaluation always produces a wnf,
and preserves the wellformedness of the heap.
The fact that the evaluation terminated is implied by the fact
that we have a finite proof of EVAL to pass to this lemma. *)
Lemma eval_produces_wfH_value
: forall h0 x1 h1 v1
, EVAL h0 x1 h1 v1
-> wfH h1 /\ value v1.
Proof.
intros. induction H; rip; try burn.
inverts H1; eauto.
eapply Forall_update; eauto.
eapply Forall_update; eauto.
unfold xUnit. auto.
Qed.
(* A terminating big-step evaluation produces a well formed heap. *)
Lemma eval_produces_wfH
: forall h0 x1 h1 v1
, EVAL h0 x1 h1 v1
-> wfH h1.
Proof.
intros. lets D: eval_produces_wfH_value H. burn.
Qed.
Hint Resolve eval_produces_wfH.
(* A terminating big-step evaluation produces a value. *)
Lemma eval_produces_value
: forall h0 x1 h1 v1
, EVAL h0 x1 h1 v1
-> value v1.
Proof.
intros. lets D: eval_produces_wfH_value H. burn.
Qed.
Hint Resolve eval_produces_value.
(********************************************************************)
(** * Big to Small steps *)
(* Flatten out a big-step evaluation into a list of individual
machine steps.
Proof:
This is tedious but straightforward. We assert each of the
intermediate STEPS to get the intermediate values, then use
preservation to show the results have the same type as before.
Once we've got a STEPS for each of the hyps of the EVAL we're
we're flattening, join them all together with an EsAppend,
stating the contexts we're performing the reductions in.
*)
Lemma steps_of_eval
: forall se h0 h1 x1 t1 x2
, wfH h0 -> TYPEH se h0
-> TYPE nil se x1 t1
-> EVAL h0 x1 h1 x2
-> STEPS h0 x1 h1 x2.
Proof.
intros se h0 h1 x1 t1 v2 HTW HTH HT HE. gen se t1.
(* Induction over the form of (EVAL x1 x2) *)
induction HE; intros.
Case "EvDone".
apply EsNone.
(* Function Application **********)
Case "EvLamApp".
inverts_type.
rename H3 into Tx1.
rename H5 into Tx2.
(* evaluate function *)
have Sx1: (STEPS h0 x1 h1 (XLam t11 x12)).
clear IHHE1.
lets Rx1: preservation_steps HTH Tx1 Sx1.
destruct Rx1 as [se1]. rip.
inverts keep H2.
(* evaluate arg *)
have (TYPE nil se1 x2 t0).
have Sx2: (STEPS h1 x2 h2 v2).
clear IHHE2.
lets Rx1: preservation_steps se1 h1 x2 t0 h2.
lets Rx1': Rx1 v2.
clear Rx1. rip.
destruct Rx1' as [se2]. rip.
(* perform substitution *)
have (TYPE nil se2 (substX 0 v2 x12) t1)
by burn using subst_exp_exp.
have (STEPS h2 (substX 0 v2 x12) h3 v3).
lets Rx2: preservation_steps se2 h2 (substX 0 v2 x12) t1 h3.
lets Rx2': Rx2 v3.
clear Rx2. rip.
destruct Rx2' as [se3]. rip.
eapply EsAppend.
lets D: steps_context XcApp1.
eapply D. eauto.
eapply EsAppend.
lets D: steps_context XcApp2.
have WL: (wnfX (XLam t0 x12)).
eauto. eapply D. eauto.
eapply EsAppend; eauto.
(* Create a new Reference *******)
Case "EvNewRef".
inverts_type.
rename H2 into Tx1.
(* evaluate argument *)
have Sx1: (STEPS h0 x1 h1 v1).
clear IHHE.
lets Rx1: preservation_steps HTH Tx1 Sx1.
destruct Rx1 as [se1]. rip.
eapply EsAppend.
lets D: steps_context XcNewRef.
eapply D. eauto.
eapply EsStep. eauto.
(* Read a reference ************)
Case "EvReadRef".
inverts_type.
rename H3 into Tx1.
(* evaluate argument to a location *)
have Sx1: (STEPS h0 x1 h1 (XLoc l)).
clear IHHE.
lets Rx1: preservation_steps HTH Tx1 Sx1.
destruct Rx1 as [se1]. rip.
eapply EsAppend.
lets D: steps_context XcReadRef.
eapply D. eauto.
eapply EsStep. eauto.
(* Write a reference **********)
Case "EvWriteRef".
inverts_type.
rename H3 into Tx1.
rename H5 into Tx2.
(* evaluate first argument to a location *)
have Sx1: (STEPS h0 x1 h1 (XLoc l)).
clear IHHE1.
lets Rx1: preservation_steps HTH Tx1 Sx1.
destruct Rx1 as [se1]. rip.
(* evaluate second argument to a value *)
have Sx2: (STEPS h1 x2 h2 v2).
clear IHHE2.
have Tx2': (TYPE nil se1 x2 tData).
lets Rx2: preservation_steps H Tx2' Sx2.
destruct Rx2 as [se2]. rip.
eapply EsAppend.
lets D: steps_context XcWriteRef1.
eapply D. eapply Sx1.
eapply EsAppend.
lets D: steps_context XcWriteRef2.
have (value (XLoc l)). eauto.
eapply D. eapply Sx2.
eauto.
Qed.
(********************************************************************)
(** * Small to Big steps *)
(** Convert a list of individual machine steps to a big-step
evaluation. The main part of this is the expansion lemma, which
we use to build up the overall big-step evaluation one small-step
at a time. The other lemmas are used to feed it small-steps.
*)
(* Given an existing big-step evalution, we can produce a new one
that does an extra step before returning the original value.
*)
Lemma eval_expansion
: forall se h1 x1 t1 h2 x2 h3 v3
, wfH h1 -> TYPEH se h1
-> TYPE nil se x1 t1
-> STEP h1 x1 h2 x2 -> EVAL h2 x2 h3 v3
-> EVAL h1 x1 h3 v3.
Proof.
intros se h1 x1 t1 h2 x2 h3 v3 HW HTH HT HS HE.
gen se t1 h3 v3.
(* Induction over the form of (STEP x1 x2) *)
induction HS; intros.
Case "context".
destruct H; eauto; inverts_type.
SCase "XcApp".
inverts_eval. nope. eauto.
inverts_eval. nope.
assert (h1 = h' /\ XLam t11 x12 = v1).
eapply eval_value_eq; eauto. rip.
eapply EvLamApp. eauto. eauto.
eauto.
SCase "XcNewRef".
inverts_eval; burn.
SCase "XcReadRef".
inverts_eval; burn.
SCase "XcWriteRef".
inverts_eval; burn.
inverts_eval. nope.
assert (h1 = h' /\ XLoc l0 = v1).
eapply eval_value_eq; eauto. rip.
eauto.
Case "XApp".
inverts_type.
eapply EvLamApp; eauto.
have (value (XLam t0 x12)). burn.
Case "XNewRef".
assert (h3 = v1 <: h /\ v3 = XLoc (length h)).
eapply eval_value_eq; eauto. burn. rip.
Case "XReadRef".
have (value v).
assert (h3 = h /\ v3 = v).
eapply eval_value_eq; eauto. rip.
eapply EvReadRef; eauto.
eapply EvDone; burn.
Case "XWriteRef".
assert (h3 = update l v2 h /\ v3 = xUnit).
eapply eval_value_eq; eauto.
unfold xUnit; burn.
rip.
eapply EvWriteRef.
eapply EvDone; burn.
inverts HE.
inverts_type.
have (value v2).
assert (exists xData, get l h = Some xData).
eauto using (@Forall2_get_get_right exp).
eauto.
Qed.
(* Convert a list of small steps to a big-step evaluation. *)
Lemma eval_of_stepsl
: forall se h1 x1 t1 h2 v2
, wfH h1 -> TYPEH se h1
-> TYPE nil se x1 t1
-> STEPSL h1 x1 h2 v2 -> value v2
-> EVAL h1 x1 h2 v2.
Proof.
intros. gen se.
induction H2; intros.
Case "EslNone".
apply EvDone; auto.
Case "EslCons".
eapply eval_expansion; eauto.
lets D: preservation H1 H4 H0.
dest D. rip.
have (wfH h2) by burn using step_preserves_wfH.
burn.
Qed.
(* Convert a multi-step evaluation to a big-step evaluation.
We use stepsl_of_steps to flatten out the append constructors
in the multi-step evaluation, leaving a list of individual
small-steps. *)
Lemma eval_of_steps
: forall se h1 x1 t1 h2 v2
, wfH h1 -> TYPEH se h1
-> TYPE nil se x1 t1
-> STEPS h1 x1 h2 v2 -> value v2
-> EVAL h1 x1 h2 v2.
Proof.
intros.
eapply eval_of_stepsl; eauto.
apply stepsl_of_steps; auto.
Qed.
|
// File ../../vhdl/src/decoder.vhd translated with vhd2vl v2.5 VHDL to Verilog RTL translator
// vhd2vl settings:
// * Verilog Module Declaration Style: 2001
// vhd2vl is Free (libre) Software:
// Copyright (C) 2001 Vincenzo Liguori - Ocean Logic Pty Ltd
// http://www.ocean-logic.com
// Modifications Copyright (C) 2006 Mark Gonzales - PMC Sierra Inc
// Modifications (C) 2010 Shankar Giri
// Modifications Copyright (C) 2002, 2005, 2008-2010, 2015 Larry Doolittle - LBNL
// http://doolittle.icarus.com/~larry/vhd2vl/
//
// vhd2vl comes with ABSOLUTELY NO WARRANTY. Always check the resulting
// Verilog for correctness, ideally with a formal verification tool.
//
// You are welcome to redistribute vhd2vl under certain conditions.
// See the license (GPLv2) file included with the source for details.
// The result of translation follows. Its copyright status should be
// considered unchanged from the original VHDL.
// no timescale needed
`include "cpu_constants.vh"
`timescale 1ns/1ps
module decoder(
input wire clk,
input wire en,
input wire [15:0] instruction,
output wire [7:0] alu_control,
output wire [2:0] rD_sel,
output wire [2:0] rS_sel,
output wire [15:0] immediate,
output wire en_immediate,
output wire next_word,
output reg en_mem,
output reg mem_displacement,
output reg mem_byte,
output reg lr_is_input,
output reg [3:0] condition
);
reg [7:0] s_alu_control;
reg [2:0] s_rD_sel;
reg [2:0] s_rS_sel;
reg [15:0] s_immediate;
reg s_en_imm;
reg s_next_word;
wire [7:0] opcode;
assign opcode = instruction[15:8];
assign alu_control = s_alu_control;
assign rD_sel = s_rD_sel;
assign rS_sel = s_rS_sel;
assign immediate = s_immediate;
assign en_immediate = s_en_imm;
assign next_word = s_next_word;
always @(posedge clk) begin : P1
if(en == 1'b 1) begin
if((((opcode)) <= ((`OPC_MOVB_R7)) && ((opcode)) >= ((`OPC_MOVB_R0)))) begin
s_en_imm <= 1'b 1;
s_alu_control <= `OPC_MOV;
s_next_word <= 1'b 0;
s_immediate <= {8'h 00,instruction[7:0]};
case(opcode)
`OPC_MOVB_R0 : begin
s_rD_sel <= 3'b 000;
end
`OPC_MOVB_R1 : begin
s_rD_sel <= 3'b 001;
end
`OPC_MOVB_R2 : begin
s_rD_sel <= 3'b 010;
end
`OPC_MOVB_R3 : begin
s_rD_sel <= 3'b 011;
end
`OPC_MOVB_R4 : begin
s_rD_sel <= 3'b 100;
end
`OPC_MOVB_R5 : begin
s_rD_sel <= 3'b 101;
end
`OPC_MOVB_R6 : begin
s_rD_sel <= 3'b 110;
end
`OPC_MOVB_R7 : begin
s_rD_sel <= 3'b 111;
end
default : begin
end
endcase
end
else begin
s_alu_control <= {1'b 0,opcode[6:0]};
s_en_imm <= instruction[15];
s_next_word <= instruction[15];
s_rD_sel <= instruction[2:0];
s_immediate <= 16'h 0000;
if(opcode == `OPC_PUSH || opcode == `OPC_POP ||
opcode == `OPC_PUSHI || opcode == `OPC_PUSHLR) begin
s_rS_sel <= ~instruction[5:3];
//Stack pointer
end
else begin
s_rS_sel <= instruction[5:3];
end
end
if(opcode == `OPC_ST || opcode == `OPC_LD || opcode == `OPC_LDI ||
opcode == `OPC_STI || opcode == `OPC_PUSH || opcode == `OPC_PUSHI ||
opcode == `OPC_POP || opcode == `OPC_PUSHLR) begin
en_mem <= 1'b 1;
if(opcode == `OPC_ST || opcode == `OPC_LD ||
opcode == `OPC_LDI || opcode == `OPC_STI)
mem_byte <= instruction[7];
else
mem_byte <= 0;
end
else begin
mem_byte <= 1'b 0;
en_mem <= 1'b 0;
end
if(opcode == `OPC_LDI || opcode == `OPC_STI) begin
mem_displacement <= instruction[6];
end
else begin
mem_displacement <= 1'b 0;
end
if(opcode == `OPC_SPEC || opcode == `OPC_PUSHLR)
lr_is_input <= 1;
else
lr_is_input <= 0;
if(opcode == `OPC_JMP || opcode == `OPC_JMPI ||
opcode == `OPC_SET || opcode == `OPC_CALL ||
opcode == `OPC_CALLI ) begin
condition <= instruction[6:3];
end
else begin
condition <= 4'b 0000;
end
end
end
`ifdef FORMAL
assume property(en == 1);
reg [15:0] instr_prev = 0;
reg [7:0] opcode_prev = 0;
initial begin
assume(s_alu_control == 0);
assume(s_en_imm == 0);
assume(s_immediate == 0);
assume(opcode_prev == 0);
assume(s_next_word == 0);
end
always @(posedge clk) begin
instr_prev <= instruction;
opcode_prev <= opcode;
if(opcode_prev == `OPC_ADD) begin
assert(s_en_imm == 0);
assert(s_alu_control == `OPC_ADD);
end
if(opcode_prev[7] == 1) begin
assert(s_en_imm == 1);
assert(s_next_word == 1);
end
else if(opcode_prev >= `OPC_MOVB_R0 && opcode_prev <= `OPC_MOVB_R7) begin
assert(s_en_imm == 1);
assert(s_next_word == 0);
end
else if(opcode_prev[7] == 0) begin
assert(s_en_imm == 0);
assert(s_next_word == 0);
end
end
`endif
`ifdef FORMAL
initial begin
assume(instruction == 0);
assume(s_rD_sel == 0);
assume(s_rS_sel == 0);
end
always @(posedge clk) begin
if($initstate) begin
assume($past(instruction) == 0);
assume($past(opcode) == 0);
end
else begin
if($past(opcode) & 8'h80)
assert(s_next_word == 1);
else
assert(s_next_word == 0);
if($past(opcode) >= `OPC_MOVB_R0 && opcode_prev <= `OPC_MOVB_R7) begin
assert(s_next_word == 0);
assert(s_en_imm == 1);
assert(s_rD_sel == ($past(opcode) - `OPC_MOVB_R0 & 3'b111));
assert(s_immediate == ($past(instruction) & 8'hff));
end
else begin
assert(s_alu_control == ($past(opcode) & 8'h7f));
assert(s_rD_sel == ($past(instruction) & 3'b111));
if($past(opcode) != `OPC_PUSH && $past(opcode) != `OPC_POP &&
$past(opcode) != `OPC_PUSHI && $past(opcode) != `OPC_PUSHLR)
assert(s_rS_sel == (($past(instruction) & 6'b111000) >> 3));
else
assert(s_rS_sel == 3'b111);
end
if($past(opcode) == `OPC_SPEC) begin
assert (lr_is_input == 1);
end
end
end
`endif
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A2BB2O_BEHAVIORAL_V
`define SKY130_FD_SC_LP__A2BB2O_BEHAVIORAL_V
/**
* a2bb2o: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input OR.
*
* X = ((!A1 & !A2) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__a2bb2o (
X ,
A1_N,
A2_N,
B1 ,
B2
);
// Module ports
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out ;
wire nor0_out ;
wire or0_out_X;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
nor nor0 (nor0_out , A1_N, A2_N );
or or0 (or0_out_X, nor0_out, and0_out);
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__A2BB2O_BEHAVIORAL_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2016/06/06 20:23:23
// Design Name:
// Module Name: Mealy_FSM_ROM
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Mealy_FSM_ROM(
input clk,
input reset,
input x,
output reg [2:0] count
);
reg [2:0] state, nextState;
reg [5:0] ROM [0:11];
parameter s0 = 0, s1 = 1, s2 = 2, s3 = 3, s4 = 4, s5 = 5;
// set up ROM
initial begin
$readmemb("/home/sabertazimi/gitrepo/hust-lab/verilog/lab5/Mealy_FSM_ROM/Mealy_FSM_ROM.srcs/sources_1/new/Mealy_FSM_ROM.dat", ROM, 0, 11);
end
// update state
always @(posedge clk or posedge reset) begin
if (reset) state <= s1;
else state <= nextState;
end
/*
* compute nextState and output(count) with ROM
*/
/*
* address = (state * 2 + x + (!clk & !reset)) % 12
* !clk & !reset : handle little bug
* mod 12 : handle address overflow
*
* data = {nextState, count}
*
* ROM[(state * 2 + x + (!clk & !reset)) % 12] = {nextState, count}
*/
/*
* s0 x = 0: 000010
* s0 x = 1: 001000
* s1 x = 0: 001000
* s1 x = 0: 010001
* s2 x = 0: 010001
* s2 x = 0: 011011
* s3 x = 0: 011011
* s3 x = 0: 100101
* s4 x = 0: 100101
* s4 x = 0: 101111
* s5 x = 0: 101111
* s5 x = 0: 000010
*/
always @(x or state) begin
{nextState, count} <= ROM[(state * 2 + x + (!clk & !reset)) % 12];
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__UDP_DLATCH_P_TB_V
`define SKY130_FD_SC_HDLL__UDP_DLATCH_P_TB_V
/**
* udp_dlatch$P: D-latch, gated standard drive / active high
* (Q output UDP)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__udp_dlatch_p.v"
module top();
// Inputs are registered
reg D;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
#20 D = 1'b0;
#40 D = 1'b1;
#60 D = 1'b0;
#80 D = 1'b1;
#100 D = 1'bx;
end
// Create a clock
reg GATE;
initial
begin
GATE = 1'b0;
end
always
begin
#5 GATE = ~GATE;
end
sky130_fd_sc_hdll__udp_dlatch$P dut (.D(D), .Q(Q), .GATE(GATE));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__UDP_DLATCH_P_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O32A_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__O32A_PP_BLACKBOX_V
/**
* o32a: 3-input OR and 2-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & (B1 | B2))
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__o32a (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__O32A_PP_BLACKBOX_V
|
/*The mutex module*/
module mutex #(
parameter ADDRESS_WIDTH=31,
parameter DATA_WIDTH=32,
parameter MAX_K_VALUES
) (
input clk,
input reset,
output wire grant_accum,
output wire grant_compute,
input [31:0] accum_key, //the key that accumulate is planning to acquire
input [31:0] locked_accum_key, //key that is locked by accumulate
input [31:0] compute_key, //the key that compute(update/fill) is planning to acquire
input [MAX_K_VALUES*DATA_WIDTH-1:0] locked_sort_keys, //keys that are locked by compute (update/fill)
input [31:0] locked_compute_key,
output wire accum_key_locked, //status signal to compute indicating accumulate has locked the key
output wire compute_key_locked, //status signal to accumulate indicating compute has locked the key
input wire [MAX_K_VALUES-1:0] mask_reg
);
wire [MAX_K_VALUES-1:0] is_equal;
reg grant_counter;
//grant signals
assign grant_accum = grant_counter;
assign grant_compute = ~grant_counter;
//status signals
assign compute_key_locked = (compute_key==locked_accum_key)?1'b1:1'b0;
assign accum_key_locked = |is_equal||(accum_key==locked_compute_key); //we must ask the accum to hold until both FILL and UPDATE modules have released the hold on the key
genvar i;
generate
for(i=0;i<MAX_K_VALUES;i=i+1) begin:equal
assign is_equal[i] = mask_reg[i] & ((accum_key==locked_sort_keys[DATA_WIDTH*(i+1)-1:DATA_WIDTH*i])?1'b1:1'b0);
end
endgenerate
/*The mutex grant signal - must be acquired before setting/checking the mutex*/
always@(posedge clk)
begin
if(reset) begin
grant_counter <= 0;
end
else begin
grant_counter <= ~grant_counter;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__INV_2_V
`define SKY130_FD_SC_LS__INV_2_V
/**
* inv: Inverter.
*
* Verilog wrapper for inv with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__inv.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__inv_2 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__inv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__inv_2 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__inv base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__INV_2_V
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
// Date : Tue Oct 17 19:51:15 2017
// Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ip_design_auto_pc_0_stub.v
// Design : ip_design_auto_pc_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "axi_protocol_converter_v2_1_14_axi_protocol_converter,Vivado 2017.3" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(aclk, aresetn, s_axi_awid, s_axi_awaddr,
s_axi_awlen, s_axi_awsize, s_axi_awburst, s_axi_awlock, s_axi_awcache, s_axi_awprot,
s_axi_awqos, s_axi_awvalid, s_axi_awready, s_axi_wid, s_axi_wdata, s_axi_wstrb, s_axi_wlast,
s_axi_wvalid, s_axi_wready, s_axi_bid, s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_arid,
s_axi_araddr, s_axi_arlen, s_axi_arsize, s_axi_arburst, s_axi_arlock, s_axi_arcache,
s_axi_arprot, s_axi_arqos, s_axi_arvalid, s_axi_arready, s_axi_rid, s_axi_rdata, s_axi_rresp,
s_axi_rlast, s_axi_rvalid, s_axi_rready, m_axi_awaddr, m_axi_awprot, m_axi_awvalid,
m_axi_awready, m_axi_wdata, m_axi_wstrb, m_axi_wvalid, m_axi_wready, m_axi_bresp,
m_axi_bvalid, m_axi_bready, m_axi_araddr, m_axi_arprot, m_axi_arvalid, m_axi_arready,
m_axi_rdata, m_axi_rresp, m_axi_rvalid, m_axi_rready)
/* synthesis syn_black_box black_box_pad_pin="aclk,aresetn,s_axi_awid[11:0],s_axi_awaddr[31:0],s_axi_awlen[3:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[1:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awqos[3:0],s_axi_awvalid,s_axi_awready,s_axi_wid[11:0],s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bid[11:0],s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_arid[11:0],s_axi_araddr[31:0],s_axi_arlen[3:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[1:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arqos[3:0],s_axi_arvalid,s_axi_arready,s_axi_rid[11:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_awaddr[31:0],m_axi_awprot[2:0],m_axi_awvalid,m_axi_awready,m_axi_wdata[31:0],m_axi_wstrb[3:0],m_axi_wvalid,m_axi_wready,m_axi_bresp[1:0],m_axi_bvalid,m_axi_bready,m_axi_araddr[31:0],m_axi_arprot[2:0],m_axi_arvalid,m_axi_arready,m_axi_rdata[31:0],m_axi_rresp[1:0],m_axi_rvalid,m_axi_rready" */;
input aclk;
input aresetn;
input [11:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [3:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [1:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awqos;
input s_axi_awvalid;
output s_axi_awready;
input [11:0]s_axi_wid;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [11:0]s_axi_bid;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [11:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [3:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [1:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arqos;
input s_axi_arvalid;
output s_axi_arready;
output [11:0]s_axi_rid;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
output [31:0]m_axi_awaddr;
output [2:0]m_axi_awprot;
output m_axi_awvalid;
input m_axi_awready;
output [31:0]m_axi_wdata;
output [3:0]m_axi_wstrb;
output m_axi_wvalid;
input m_axi_wready;
input [1:0]m_axi_bresp;
input m_axi_bvalid;
output m_axi_bready;
output [31:0]m_axi_araddr;
output [2:0]m_axi_arprot;
output m_axi_arvalid;
input m_axi_arready;
input [31:0]m_axi_rdata;
input [1:0]m_axi_rresp;
input m_axi_rvalid;
output m_axi_rready;
endmodule
|
// (C) 1992-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//
// Top level load/store unit
//
// Attributes of load/store units
// Coalesced: Accesses to neighbouring memory locations are grouped together
// to improve efficiency and efficiently utilize memory bandwidth.
// Hazard-Safe:The LSU is not susceptable to data hazards.
// Ordered: The LSU requires accesses to be in-order to properly coalesce.
// Pipeline: The LSU can handle multiple requests at a time without
// stalling. Improves throughput.
//
// Supports the following memory access patterns:
// Simple - STYLE="SIMPLE"
// Coalesced: No, Ordered: N/A, Hazard-Safe: Yes, Pipelined, No
// Simple un-pipelined memory access. Low throughput.
// Pipelined - STYLE="PIPELINED"
// Coalesced: No, Ordered: N/A, Hazard-Safe: Yes, Pipelined: Yes
// Requests are submitted as soon as they are received.
// Pipelined access to memory so multiple requests can be
// in flight at a time.
// Enabled - STYLE="ENABLED"
// Coalesced: No, Ordered: N/A, Hazard-Safe: Yes, Pipelined: Yes
// Requests are submitted as soon as they are received.
// Pipelined access to memory so multiple requests can be
// in flight at a time. Stalls freeze the pipeline (incl. memory).
// Currently only used in enable clusters.
// Coalesced - STYLE="BASIC-COALESCED"
// "basic" Coalesced: Yes, Ordered: Yes, Hazard-Safe: Yes, Pipelined: Yes
// Requests are submitted as soon as possible to memory, stalled
// requests are coalesced with neighbouring requests if they
// access the same page of memory.
// Coalesced - STYLE="BURST-COALESCED"
// "burst" Coalesced: Yes, Ordered: Yes, Hazard-Safe: Yes, Pipelined: Yes
// Requests are buffered until the biggest possible burst can
// be made.
// Streaming - STYLE="STREAMING"
// Coalesced: Yes, Ordered: Yes, Hazard-Safe: No, Pipelined: ?
// A FIFO is instantiated which burst reads large blocks from
// memory to keep the FIFO full of valid data. This block can
// only be used if accesses are in-order, and addresses can be
// simply calculated from (base_address + n * word_width). The
// block has no built-in hazard protection.
// Prefetching - STYLE="PREFETCHING"
// Coalesced: No, Ordered: Yes, Hazard-Safe: No, Pipelined: ?
// A FIFO is instantiated which burst reads large blocks from
// memory to keep the FIFO full of valid data based on the
// previous address and assuming contiguous reads.
// Non-contiguos reads are supported, but a penalty is incurred
// to flush and refill the FIFO.
// Atomic - STYLE="ATOMIC-PIPELINED"
//"pipelined"
// Coalesced: No, Ordered: N/A, Hazard-Safe: Yes, Pipelined: Yes
// Atomic: Yes
// Requests are submitted as soon as they are received.
// Pipelined access to memory so multiple requests can be
// in flight at a time.
// Response is returned as soon as read is complete,
// write is issued subsequently by the atomic module at the end
// of arbitration.
// altera message_off 10036
module lsu_top
(
clock, clock2x, resetn, stream_base_addr, stream_size, stream_reset, i_atomic_op, o_stall,
i_valid, i_address, i_writedata, i_cmpdata, i_predicate, i_bitwiseor, i_stall, o_valid, o_readdata, avm_address,
avm_enable, avm_read, avm_readdata, avm_write, avm_writeack, avm_writedata, avm_byteenable,
avm_waitrequest, avm_readdatavalid, avm_burstcount,
o_active,
o_input_fifo_depth,
o_writeack,
i_byteenable,
flush,
// profile signals
profile_bw, profile_bw_incr,
profile_total_ivalid,
profile_total_req,
profile_i_stall_count,
profile_o_stall_count,
profile_avm_readwrite_count,
profile_avm_burstcount_total, profile_avm_burstcount_total_incr,
profile_req_cache_hit_count,
profile_extra_unaligned_reqs,
profile_avm_stall
);
/*************
* Parameters *
*************/
parameter STYLE="PIPELINED"; // The LSU style to use (see style list above)
parameter AWIDTH=32; // Address width (32-bits for Avalon)
parameter ATOMIC_WIDTH=6; // Width of operation operation indices
parameter WIDTH_BYTES=4; // Width of the request (bytes)
parameter MWIDTH_BYTES=32; // Width of the global memory bus (bytes)
parameter WRITEDATAWIDTH_BYTES=32; // Width of the readdata/writedata signals,
// may be larger than MWIDTH_BYTES for atomics
parameter ALIGNMENT_BYTES=2; // Request address alignment (bytes)
parameter READ=1; // Read or write?
parameter ATOMIC=0; // Atomic?
parameter BURSTCOUNT_WIDTH=6;// Determines max burst size
// Why two latencies? E.g. A streaming unit prefetches data, its latency to
// the kernel is very low because data is for the most part ready and waiting.
// But the lsu needs to know how much data to buffer to hide the latency to
// memory, hence the memory side latency.
parameter KERNEL_SIDE_MEM_LATENCY=1; // Effective Latency in cycles as seen by the kernel pipeline
parameter MEMORY_SIDE_MEM_LATENCY=1; // Latency in cycles between LSU and memory
parameter USE_WRITE_ACK=0; // Enable the write-acknowledge signal
parameter USECACHING=0;
parameter USE_BYTE_EN=0;
parameter CACHESIZE=1024;
parameter PROFILE_ADDR_TOGGLE=0;
parameter USEINPUTFIFO=1; // FIXME specific to lsu_pipelined
parameter USEOUTPUTFIFO=1; // FIXME specific to lsu_pipelined
parameter FORCE_NOP_SUPPORT=0; // Stall free pipeline doesn't want the NOP fifo
parameter HIGH_FMAX=1; // Enable optimizations for high Fmax
parameter INTENDED_DEVICE_FAMILY = "Stratix V";
// Profiling
parameter ACL_PROFILE=0; // Set to 1 to enable stall/valid profiling
parameter ACL_PROFILE_INCREMENT_WIDTH=32;
// Verilog readability and parsing only - no functional purpose
parameter ADDRSPACE=0;
// Local memory parameters
parameter ENABLE_BANKED_MEMORY=0;// Flag enables address permutation for banked local memory config
parameter ABITS_PER_LMEM_BANK=0; // Used when permuting lmem address bits to stride across banks
parameter NUMBER_BANKS=1; // Number of memory banks - used in address permutation (1-disable)
parameter LMEM_ADDR_PERMUTATION_STYLE=0; // Type of address permutation (currently unused)
// Parameter limitations:
// AWIDTH: Only tested with 32-bit addresses
// WIDTH_BYTES: Must be a power of two
// MWIDTH_BYTES: Must be a power of 2 >= WIDTH_BYTES
// ALIGNMENT_BYTES: Must be a power of 2 satisfying,
// WIDTH_BYTES <= ALIGNMENT_BYTES <= MWIDTH_BYTES
//
// The width and alignment restrictions ensure we never try to read a word
// that strides across two "pages" (MWIDTH sized words)
// TODO: Convert these back into localparams when the back-end supports it
parameter WIDTH=8*WIDTH_BYTES; // Width in bits
parameter MWIDTH=8*MWIDTH_BYTES; // Width in bits
parameter WRITEDATAWIDTH=8*WRITEDATAWIDTH_BYTES; // Width in bits
localparam ALIGNMENT_ABITS=$clog2(ALIGNMENT_BYTES); // Address bits to ignore
localparam LSU_CAPACITY=256; // Maximum number of 'in-flight' load/store operations
localparam WIDE_LSU = (WIDTH > MWIDTH);
// Performance monitor signals
parameter INPUTFIFO_USEDW_MAXBITS=8;
// LSU unit properties
localparam ATOMIC_PIPELINED_LSU=(STYLE=="ATOMIC-PIPELINED");
localparam PIPELINED_LSU=( (STYLE=="PIPELINED") || (STYLE=="BASIC-COALESCED") || (STYLE=="BURST-COALESCED") || (STYLE=="BURST-NON-ALIGNED") );
localparam SUPPORTS_NOP= (STYLE=="STREAMING") || (STYLE=="SEMI-STREAMING") || (STYLE=="BURST-NON-ALIGNED") || (STYLE=="BURST-COALESCED") || (STYLE=="PREFETCHING") || (FORCE_NOP_SUPPORT==1);
localparam SUPPORTS_BURSTS=( (STYLE=="STREAMING") || (STYLE=="BURST-COALESCED") || (STYLE=="SEMI-STREAMING") || (STYLE=="BURST-NON-ALIGNED") || (STYLE=="PREFETCHING"));
/********
* Ports *
********/
// Standard global signals
input clock;
input clock2x;
input resetn;
input flush;
// Streaming interface signals
input [AWIDTH-1:0] stream_base_addr;
input [31:0] stream_size;
input stream_reset;
// Atomic interface
input [WIDTH-1:0] i_cmpdata; // only used by atomic_cmpxchg
input [ATOMIC_WIDTH-1:0] i_atomic_op;
// Upstream interface
output o_stall;
input i_valid;
input [AWIDTH-1:0] i_address;
input [WIDTH-1:0] i_writedata;
input i_predicate;
input [AWIDTH-1:0] i_bitwiseor;
input [WIDTH_BYTES-1:0] i_byteenable;
// Downstream interface
input i_stall;
output o_valid;
output [WIDTH-1:0] o_readdata;
// Avalon interface
output [AWIDTH-1:0] avm_address;
output avm_enable;
output avm_read;
input [WRITEDATAWIDTH-1:0] avm_readdata;
output avm_write;
input avm_writeack;
output o_writeack;
output [WRITEDATAWIDTH-1:0] avm_writedata;
output [WRITEDATAWIDTH_BYTES-1:0] avm_byteenable;
input avm_waitrequest;
input avm_readdatavalid;
output [BURSTCOUNT_WIDTH-1:0] avm_burstcount;
output reg o_active;
// For profiling/performance monitor
output [INPUTFIFO_USEDW_MAXBITS-1:0] o_input_fifo_depth;
// Profiler Signals
output logic profile_bw;
output logic [ACL_PROFILE_INCREMENT_WIDTH-1:0] profile_bw_incr;
output logic profile_total_ivalid;
output logic profile_total_req;
output logic profile_i_stall_count;
output logic profile_o_stall_count;
output logic profile_avm_readwrite_count;
output logic profile_avm_burstcount_total;
output logic [ACL_PROFILE_INCREMENT_WIDTH-1:0] profile_avm_burstcount_total_incr;
output logic profile_req_cache_hit_count;
output logic profile_extra_unaligned_reqs;
output logic profile_avm_stall;
// help timing; reduce the high fanout of global reset from iface
reg [1:0] sync_rstn_MS /* synthesis syn_preserve = 1 */ ;
wire sync_rstn;
assign sync_rstn = sync_rstn_MS[1];
always @(posedge clock or negedge resetn) begin
if(!resetn) sync_rstn_MS <= 2'b00;
else sync_rstn_MS <= {sync_rstn_MS[0], 1'b1};
end
generate
if(WIDE_LSU) begin
//break transaction into multiple cycles
lsu_wide_wrapper lsu_wide (
.clock(clock),
.clock2x(clock2x),
.resetn(sync_rstn),
.flush(flush),
.stream_base_addr(stream_base_addr),
.stream_size(stream_size),
.stream_reset(stream_reset),
.o_stall(o_stall),
.i_valid(i_valid),
.i_address(i_address),
.i_writedata(i_writedata),
.i_cmpdata(i_cmpdata),
.i_predicate(i_predicate),
.i_bitwiseor(i_bitwiseor),
.i_byteenable(i_byteenable),
.i_stall(i_stall),
.o_valid(o_valid),
.o_readdata(o_readdata),
.o_input_fifo_depth(o_input_fifo_depth),
.o_writeack(o_writeack),
.i_atomic_op(i_atomic_op),
.o_active(o_active),
.avm_address(avm_address),
.avm_enable(avm_enable),
.avm_read(avm_read),
.avm_readdata(avm_readdata),
.avm_write(avm_write),
.avm_writeack(avm_writeack),
.avm_burstcount(avm_burstcount),
.avm_writedata(avm_writedata),
.avm_byteenable(avm_byteenable),
.avm_waitrequest(avm_waitrequest),
.avm_readdatavalid(avm_readdatavalid),
.profile_req_cache_hit_count(profile_req_cache_hit_count),
.profile_extra_unaligned_reqs(profile_extra_unaligned_reqs)
);
defparam lsu_wide.STYLE = STYLE;
defparam lsu_wide.AWIDTH = AWIDTH;
defparam lsu_wide.ATOMIC_WIDTH = ATOMIC_WIDTH;
defparam lsu_wide.WIDTH_BYTES = WIDTH_BYTES;
defparam lsu_wide.MWIDTH_BYTES = MWIDTH_BYTES;
defparam lsu_wide.WRITEDATAWIDTH_BYTES = WRITEDATAWIDTH_BYTES;
defparam lsu_wide.ALIGNMENT_BYTES = ALIGNMENT_BYTES;
defparam lsu_wide.READ = READ;
defparam lsu_wide.ATOMIC = ATOMIC;
defparam lsu_wide.BURSTCOUNT_WIDTH = BURSTCOUNT_WIDTH;
defparam lsu_wide.KERNEL_SIDE_MEM_LATENCY = KERNEL_SIDE_MEM_LATENCY;
defparam lsu_wide.MEMORY_SIDE_MEM_LATENCY = MEMORY_SIDE_MEM_LATENCY;
defparam lsu_wide.USE_WRITE_ACK = USE_WRITE_ACK;
defparam lsu_wide.USECACHING = USECACHING;
defparam lsu_wide.USE_BYTE_EN = USE_BYTE_EN;
defparam lsu_wide.CACHESIZE = CACHESIZE;
defparam lsu_wide.PROFILE_ADDR_TOGGLE = PROFILE_ADDR_TOGGLE;
defparam lsu_wide.USEINPUTFIFO = USEINPUTFIFO;
defparam lsu_wide.USEOUTPUTFIFO = USEOUTPUTFIFO;
defparam lsu_wide.FORCE_NOP_SUPPORT = FORCE_NOP_SUPPORT;
defparam lsu_wide.HIGH_FMAX = HIGH_FMAX;
defparam lsu_wide.ACL_PROFILE = ACL_PROFILE;
defparam lsu_wide.ACL_PROFILE_INCREMENT_WIDTH = ACL_PROFILE_INCREMENT_WIDTH;
defparam lsu_wide.ENABLE_BANKED_MEMORY = ENABLE_BANKED_MEMORY;
defparam lsu_wide.ABITS_PER_LMEM_BANK = ABITS_PER_LMEM_BANK;
defparam lsu_wide.NUMBER_BANKS = NUMBER_BANKS;
defparam lsu_wide.WIDTH = WIDTH;
defparam lsu_wide.MWIDTH = MWIDTH;
defparam lsu_wide.WRITEDATAWIDTH = WRITEDATAWIDTH;
defparam lsu_wide.INPUTFIFO_USEDW_MAXBITS = INPUTFIFO_USEDW_MAXBITS;
defparam lsu_wide.LMEM_ADDR_PERMUTATION_STYLE = LMEM_ADDR_PERMUTATION_STYLE;
defparam lsu_wide.ADDRSPACE = ADDRSPACE;
//the wrapped LSU doesnt interface directly with the avalon master, so profiling here is more accurate for avm signals
//two signals generated directly by the LSU need to be passed in
if(ACL_PROFILE==1)
begin
// keep track of write bursts
reg [BURSTCOUNT_WIDTH-1:0] profile_remaining_writeburst_count;
wire active_write_burst;
assign active_write_burst = (profile_remaining_writeburst_count != {BURSTCOUNT_WIDTH{1'b0}});
always@(posedge clock or negedge sync_rstn)
if (!sync_rstn)
profile_remaining_writeburst_count <= {BURSTCOUNT_WIDTH{1'b0}};
else if(avm_write & ~avm_waitrequest & ~active_write_burst)
// start of a new write burst
profile_remaining_writeburst_count <= avm_burstcount - 1;
else if(~avm_waitrequest & active_write_burst)
// count down one burst
profile_remaining_writeburst_count <= profile_remaining_writeburst_count - 1;
assign profile_bw = (READ==1) ? avm_readdatavalid : (avm_write & ~avm_waitrequest);
assign profile_bw_incr = MWIDTH_BYTES;
assign profile_total_ivalid = (i_valid & ~o_stall);
assign profile_total_req = (i_valid & ~i_predicate & ~o_stall);
assign profile_i_stall_count = (i_stall & o_valid);
assign profile_o_stall_count = (o_stall & i_valid);
assign profile_avm_readwrite_count = ((avm_read | avm_write) & ~avm_waitrequest & ~active_write_burst);
assign profile_avm_burstcount_total = ((avm_read | avm_write) & ~avm_waitrequest & ~active_write_burst);
assign profile_avm_burstcount_total_incr = avm_burstcount;
assign profile_avm_stall = ((avm_read | avm_write) & avm_waitrequest);
end
else begin
assign profile_bw = 1'b0;
assign profile_bw_incr = {ACL_PROFILE_INCREMENT_WIDTH{1'b0}};
assign profile_total_ivalid = 1'b0;
assign profile_total_req = 1'b0;
assign profile_i_stall_count = 1'b0;
assign profile_o_stall_count = 1'b0;
assign profile_avm_readwrite_count = 1'b0;
assign profile_avm_burstcount_total = 1'b0;
assign profile_avm_burstcount_total_incr = {ACL_PROFILE_INCREMENT_WIDTH{1'b0}};
assign profile_avm_stall = 1'b0;
end
end
else begin
wire lsu_active;
// For handling dependents of this lsu
assign o_writeack = avm_writeack;
// If this is a banked local memory LSU, then permute address bits so that
// consective words in memory are in different banks. Do this by
// taking the k lowest bits of the word-address and shifting them to the top
// of the aggregate local memory address width.
//
// The permuted address is organized as:
// { ( High order bits untouched ),
// ( Bank select bits ),
// ( Word address bits within a bank ),
// ( Byte select within a word ) }
// Not all fields are present in all configs (some configs don't bank,
// others don't have any depth to banks so no word select bits).
// Note that ABITS_PER_LMEM_BANK includes bits for the within-bank word select, the
// within-word byte select, and the pipelined workgroup select bits.
function [AWIDTH-1:0] permute_addr ( input [AWIDTH-1:0] addr);
if (ENABLE_BANKED_MEMORY==1)
begin
// Build up the permuted address segment by segment. Simplifies working
// around msim "reverse bit select" errors inside generate branches that
// aren't active.
automatic int base_bit = 0;
// Parameters must be defined before logic
localparam BITS_IN_BYTE_SELECT = $clog2(MWIDTH_BYTES);
localparam WORD_SELECT_BITS = ( ABITS_PER_LMEM_BANK - BITS_IN_BYTE_SELECT );
localparam BANK_HAS_DEPTH = (ENABLE_BANKED_MEMORY==1) ? (WORD_SELECT_BITS > 0) : 0;
localparam WORD_SELECT_BITS_HACKED = BANK_HAS_DEPTH ? WORD_SELECT_BITS : 1; // System integrator adds address bit when no depth
localparam BANK_SELECT_BITS = (ENABLE_BANKED_MEMORY==1) ? $clog2(NUMBER_BANKS) : 0; // Bank select bits in address permutation
localparam BANK_SELECT_BITS_HACKED = BANK_SELECT_BITS ? BANK_SELECT_BITS : 1; // Prevents synthesis error in VCS and NCSIM
permute_addr = addr; // Start with original address. Then we modify the required bits.
// 1. Byte address within a word - jump over these bits without modification
base_bit += BITS_IN_BYTE_SELECT;
// 2. Word address within a bank
if ( BANK_HAS_DEPTH ) begin
permute_addr[ base_bit +: WORD_SELECT_BITS_HACKED ] = addr[ (BANK_SELECT_BITS + BITS_IN_BYTE_SELECT) +: WORD_SELECT_BITS_HACKED ];
end
else // Else single word memory bank
begin
// System integrator makes all banks have an address bit to avoid 0-width signals in the interconnect IP.
// Here we force that address bit to zero for functional correctness.
permute_addr[ base_bit +: WORD_SELECT_BITS_HACKED ] = 1'b0;
end
base_bit += WORD_SELECT_BITS_HACKED;
// 3. Hoist bank select bits if we have multiple banks
if (BANK_SELECT_BITS>0) begin
permute_addr[ base_bit +: BANK_SELECT_BITS_HACKED ] = addr[ BITS_IN_BYTE_SELECT +: BANK_SELECT_BITS_HACKED ];
end
end
else // Else don't permute the address
begin
permute_addr= addr;
end
endfunction
wire [AWIDTH-1:0] avm_address_raw;
assign avm_address=permute_addr(avm_address_raw);
/***************
* Architecture *
***************/
// Tie off the unused read/write signals
// atomics dont have unused signals
if(ATOMIC==0) begin
if(READ==1)
begin
assign avm_write = 1'b0;
//assign avm_writedata = {MWIDTH{1'bx}};
assign avm_writedata = {MWIDTH{1'b0}}; // make writedata 0 because it is used by atomics
end
else // WRITE
begin
assign avm_read = 1'b0;
end
end
else begin //ATOMIC
assign avm_write = 1'b0;
end
// Write acknowledge support: If WRITEACK is not to be supported, than assume
// that a write is fully completed as soon as it is accepted by the fabric.
// Otherwise, wait for the writeack signal to return.
wire lsu_writeack;
if(USE_WRITE_ACK==1)
begin
assign lsu_writeack = avm_writeack;
end
else
begin
assign lsu_writeack = avm_write && !avm_waitrequest;
end
// NOP support: The least-significant address bit indicates if this is a NOP
// instruction (i.e. we do not wish a read/write to be performed).
// Appropriately adjust the valid and stall inputs to the core LSU block to
// ensure NOP instructions are not executed and preserve their ordering with
// other threads.
wire lsu_i_valid;
wire lsu_o_valid;
wire lsu_i_stall;
wire lsu_o_stall;
wire [AWIDTH-1:0] address;
wire nop;
if(SUPPORTS_NOP)
begin
// Module intrinsicly supports NOP operations, just pass them on through
assign lsu_i_valid = i_valid;
assign lsu_i_stall = i_stall;
assign o_valid = lsu_o_valid;
assign o_stall = lsu_o_stall;
assign address = i_address | i_bitwiseor;
end
else if(PIPELINED_LSU || ATOMIC_PIPELINED_LSU)
begin
// No built-in NOP support. Pipelined LSUs without NOP support need us to
// build a fifo along side the core LSU to track NOP instructions
wire nop_fifo_empty;
wire nop_fifo_full;
wire nop_next;
assign nop = i_predicate;
assign address = i_address | i_bitwiseor;
// Store the NOP status flags along side the core LSU
// Assume (TODO eliminate this assumption?) that KERNEL_SIDE_MEM_LATENCY is the max
// number of simultaneous requests in flight for the LSU. The NOP FIFO will
// will be sized to KERNEL_SIDE_MEM_LATENCY+1 to prevent stalls when the LSU is
// full.
//
// For smaller latency values, use registers to implement the FIFO.
if(KERNEL_SIDE_MEM_LATENCY <= 64)
begin
acl_ll_fifo #(
.WIDTH(1),
.DEPTH(KERNEL_SIDE_MEM_LATENCY+1)
) nop_fifo (
.clk(clock),
.reset(~sync_rstn),
.data_in(nop),
.write(i_valid && !o_stall),
.data_out(nop_next),
.read(o_valid && !i_stall),
.full(nop_fifo_full),
.empty(nop_fifo_empty)
);
end
else
begin
scfifo #(
.add_ram_output_register( "OFF" ),
.intended_device_family( "Stratix IV" ),
.lpm_numwords( KERNEL_SIDE_MEM_LATENCY+1 ),
.lpm_showahead( "ON" ),
.lpm_type( "scfifo" ),
.lpm_width( 1 ),
.lpm_widthu( $clog2(KERNEL_SIDE_MEM_LATENCY+1) ),
.overflow_checking( "OFF" ),
.underflow_checking( "OFF" )
) nop_fifo (
.clock(clock),
.data(nop),
.rdreq(o_valid && !i_stall),
.wrreq(i_valid && !o_stall),
.empty(nop_fifo_empty),
.full(nop_fifo_full),
.q(nop_next),
.aclr(!sync_rstn),
.almost_full(),
.almost_empty(),
.usedw(),
.sclr()
);
end
// Logic to prevent NOP instructions from entering the core
assign lsu_i_valid = !nop && i_valid && !nop_fifo_full;
assign lsu_i_stall = nop_fifo_empty || nop_next || i_stall;
// Logic to generate the valid bit for NOP instructions that have bypassed
// the LSU. The instructions must be kept in order so they are consistant
// with data propagating through pipelines outside of the LSU.
assign o_valid = (lsu_o_valid || nop_next) && !nop_fifo_empty;
assign o_stall = nop_fifo_full || lsu_o_stall;
end
else
begin
// An unpipelined LSU will only have one active request at a time. We just
// need to track whether there is a pending request in the LSU core and
// appropriately bypass the core with NOP requests while preserving the
// thread ordering. (A NOP passes straight through to the downstream
// block, unless there is a pending request in the block, in which case
// we stall until the request is complete).
reg pending;
always@(posedge clock or negedge sync_rstn)
begin
if(sync_rstn == 1'b0)
pending <= 1'b0;
else
pending <= pending ? ((lsu_i_valid && !lsu_o_stall) || !(lsu_o_valid && !lsu_i_stall)) :
((lsu_i_valid && !lsu_o_stall) && !(lsu_o_valid && !lsu_i_stall));
end
assign nop = i_predicate;
assign address = i_address | i_bitwiseor;
assign lsu_i_valid = i_valid && !nop;
assign lsu_i_stall = i_stall;
assign o_valid = lsu_o_valid || (!pending && i_valid && nop);
assign o_stall = lsu_o_stall || (pending && nop);
end
// Styles with no burst support require burstcount=1
if(!SUPPORTS_BURSTS)
begin
assign avm_burstcount = 1;
end
// Profiling signals.
wire req_cache_hit_count;
wire extra_unaligned_reqs;
// initialize
if(STYLE!="BURST-NON-ALIGNED")
assign extra_unaligned_reqs = 1'b0;
if(READ==0 || (STYLE!="BURST-COALESCED" && STYLE!="BURST-NON-ALIGNED" && STYLE!="SEMI-STREAMING"))
assign req_cache_hit_count = 1'b0;
// Generate different architectures based on the STYLE parameter
////////////////
// Simple LSU //
////////////////
if(STYLE=="SIMPLE")
begin
if(READ == 1)
begin
lsu_simple_read #(
.AWIDTH(AWIDTH),
.WIDTH_BYTES(WIDTH_BYTES),
.MWIDTH_BYTES(MWIDTH_BYTES),
.ALIGNMENT_ABITS(ALIGNMENT_ABITS),
.HIGH_FMAX(HIGH_FMAX)
) simple_read (
.clk(clock),
.reset(!sync_rstn),
.o_stall(lsu_o_stall),
.i_valid(lsu_i_valid),
.i_address(address),
.i_stall(lsu_i_stall),
.o_valid(lsu_o_valid),
.o_active(lsu_active),
.o_readdata(o_readdata),
.avm_address(avm_address_raw),
.avm_read(avm_read),
.avm_readdata(avm_readdata),
.avm_waitrequest(avm_waitrequest),
.avm_byteenable(avm_byteenable),
.avm_readdatavalid(avm_readdatavalid)
);
end
else
begin
lsu_simple_write #(
.AWIDTH(AWIDTH),
.WIDTH_BYTES(WIDTH_BYTES),
.MWIDTH_BYTES(MWIDTH_BYTES),
.USE_BYTE_EN(USE_BYTE_EN),
.ALIGNMENT_ABITS(ALIGNMENT_ABITS)
) simple_write (
.clk(clock),
.reset(!sync_rstn),
.o_stall(lsu_o_stall),
.i_valid(lsu_i_valid),
.i_address(address),
.i_writedata(i_writedata),
.i_stall(lsu_i_stall),
.o_valid(lsu_o_valid),
.i_byteenable(i_byteenable),
.o_active(lsu_active),
.avm_address(avm_address_raw),
.avm_write(avm_write),
.avm_writeack(lsu_writeack),
.avm_writedata(avm_writedata),
.avm_byteenable(avm_byteenable),
.avm_waitrequest(avm_waitrequest)
);
end
assign avm_enable = 1'b1;
end
///////////////
// Pipelined //
///////////////
else if(STYLE=="PIPELINED")
begin
wire sub_o_stall;
if(USEINPUTFIFO == 0) begin : GEN_0
assign lsu_o_stall = sub_o_stall & !i_predicate;
end
else begin : GEN_1
assign lsu_o_stall = sub_o_stall;
end
if(READ == 1)
begin
lsu_pipelined_read #(
.KERNEL_SIDE_MEM_LATENCY(KERNEL_SIDE_MEM_LATENCY),
.AWIDTH(AWIDTH),
.WIDTH_BYTES(WIDTH_BYTES),
.MWIDTH_BYTES(MWIDTH_BYTES),
.ALIGNMENT_ABITS(ALIGNMENT_ABITS),
.USEINPUTFIFO(USEINPUTFIFO),
.USEOUTPUTFIFO(USEOUTPUTFIFO)
) pipelined_read (
.clk(clock),
.reset(!sync_rstn),
.o_stall(sub_o_stall),
.i_valid(lsu_i_valid),
.i_address(address),
.i_stall(lsu_i_stall),
.o_valid(lsu_o_valid),
.o_readdata(o_readdata),
.o_input_fifo_depth(o_input_fifo_depth),
.o_active(lsu_active),
.avm_address(avm_address_raw),
.avm_read(avm_read),
.avm_readdata(avm_readdata),
.avm_waitrequest(avm_waitrequest),
.avm_byteenable(avm_byteenable),
.avm_readdatavalid(avm_readdatavalid)
);
end
else
begin
lsu_pipelined_write #(
.KERNEL_SIDE_MEM_LATENCY(KERNEL_SIDE_MEM_LATENCY),
.AWIDTH(AWIDTH),
.WIDTH_BYTES(WIDTH_BYTES),
.MWIDTH_BYTES(MWIDTH_BYTES),
.USE_BYTE_EN(USE_BYTE_EN),
.ALIGNMENT_ABITS(ALIGNMENT_ABITS),
.USEINPUTFIFO(USEINPUTFIFO)
) pipelined_write (
.clk(clock),
.reset(!sync_rstn),
.o_stall(sub_o_stall),
.i_valid(lsu_i_valid),
.i_address(address),
.i_byteenable(i_byteenable),
.i_writedata(i_writedata),
.i_stall(lsu_i_stall),
.o_valid(lsu_o_valid),
.o_input_fifo_depth(o_input_fifo_depth),
.o_active(lsu_active),
.avm_address(avm_address_raw),
.avm_write(avm_write),
.avm_writeack(lsu_writeack),
.avm_writedata(avm_writedata),
.avm_byteenable(avm_byteenable),
.avm_waitrequest(avm_waitrequest)
);
assign o_readdata = 'bx;
end
assign avm_enable = 1'b1;
end
///////////////
// Enabled //
///////////////
else if(STYLE=="ENABLED")
begin
wire sub_o_stall;
assign lsu_o_stall = sub_o_stall & !i_predicate;
if(READ == 1)
begin
lsu_enabled_read #(
.KERNEL_SIDE_MEM_LATENCY(KERNEL_SIDE_MEM_LATENCY),
.AWIDTH(AWIDTH),
.WIDTH_BYTES(WIDTH_BYTES),
.MWIDTH_BYTES(MWIDTH_BYTES),
.ALIGNMENT_ABITS(ALIGNMENT_ABITS)
) enabled_read (
.clk(clock),
.reset(!sync_rstn),
.o_stall(sub_o_stall),
.i_valid(lsu_i_valid),
.i_address(address),
.i_stall(lsu_i_stall),
.o_valid(lsu_o_valid),
.o_readdata(o_readdata),
.o_active(lsu_active),
.avm_address(avm_address_raw),
.avm_enable(avm_enable),
.avm_read(avm_read),
.avm_readdata(avm_readdata),
.avm_waitrequest(avm_waitrequest),
.avm_byteenable(avm_byteenable),
.avm_readdatavalid(avm_readdatavalid)
);
end
else
begin
lsu_enabled_write #(
.AWIDTH(AWIDTH),
.WIDTH_BYTES(WIDTH_BYTES),
.MWIDTH_BYTES(MWIDTH_BYTES),
.USE_BYTE_EN(USE_BYTE_EN),
.ALIGNMENT_ABITS(ALIGNMENT_ABITS)
) enabled_write (
.clk(clock),
.reset(!sync_rstn),
.o_stall(sub_o_stall),
.i_valid(lsu_i_valid),
.i_address(address),
.i_byteenable(i_byteenable),
.i_writedata(i_writedata),
.i_stall(lsu_i_stall),
.o_valid(lsu_o_valid),
.o_active(lsu_active),
.avm_address(avm_address_raw),
.avm_enable(avm_enable),
.avm_write(avm_write),
.avm_writeack(lsu_writeack),
.avm_writedata(avm_writedata),
.avm_byteenable(avm_byteenable),
.avm_waitrequest(avm_waitrequest)
);
assign o_readdata = 'bx;
end
end
//////////////////////
// Atomic Pipelined //
//////////////////////
else if(STYLE=="ATOMIC-PIPELINED")
begin
lsu_atomic_pipelined #(
.KERNEL_SIDE_MEM_LATENCY(KERNEL_SIDE_MEM_LATENCY),
.AWIDTH(AWIDTH),
.WIDTH_BYTES(WIDTH_BYTES),
.MWIDTH_BYTES(MWIDTH_BYTES),
.WRITEDATAWIDTH_BYTES(WRITEDATAWIDTH_BYTES),
.ALIGNMENT_ABITS(ALIGNMENT_ABITS),
.USEINPUTFIFO(USEINPUTFIFO),
.USEOUTPUTFIFO(USEOUTPUTFIFO),
.ATOMIC_WIDTH(ATOMIC_WIDTH)
) atomic_pipelined (
.clk(clock),
.reset(!sync_rstn),
.o_stall(lsu_o_stall),
.i_valid(lsu_i_valid),
.i_address(address),
.i_stall(lsu_i_stall),
.o_valid(lsu_o_valid),
.o_readdata(o_readdata),
.o_input_fifo_depth(o_input_fifo_depth),
.o_active(lsu_active),
.avm_address(avm_address_raw),
.avm_read(avm_read),
.avm_readdata(avm_readdata),
.avm_waitrequest(avm_waitrequest),
.avm_byteenable(avm_byteenable),
.avm_readdatavalid(avm_readdatavalid),
.i_atomic_op(i_atomic_op),
.i_writedata(i_writedata),
.i_cmpdata(i_cmpdata),
.avm_writeack(lsu_writeack),
.avm_writedata(avm_writedata)
);
assign avm_enable = 1'b1;
end
/////////////////////
// Basic Coalesced //
/////////////////////
else if(STYLE=="BASIC-COALESCED")
begin
if(READ == 1)
begin
lsu_basic_coalesced_read #(
.KERNEL_SIDE_MEM_LATENCY(KERNEL_SIDE_MEM_LATENCY),
.AWIDTH(AWIDTH),
.WIDTH_BYTES(WIDTH_BYTES),
.MWIDTH_BYTES(MWIDTH_BYTES),
.ALIGNMENT_ABITS(ALIGNMENT_ABITS)
) basic_coalesced_read (
.clk(clock),
.reset(!sync_rstn),
.o_stall(lsu_o_stall),
.i_valid(lsu_i_valid),
.i_address(address),
.i_stall(lsu_i_stall),
.o_valid(lsu_o_valid),
.o_readdata(o_readdata),
.avm_address(avm_address_raw),
.avm_read(avm_read),
.avm_readdata(avm_readdata),
.avm_waitrequest(avm_waitrequest),
.avm_byteenable(avm_byteenable),
.avm_readdatavalid(avm_readdatavalid)
);
end
else
begin
lsu_basic_coalesced_write #(
.KERNEL_SIDE_MEM_LATENCY(KERNEL_SIDE_MEM_LATENCY),
.AWIDTH(AWIDTH),
.WIDTH_BYTES(WIDTH_BYTES),
.USE_BYTE_EN(USE_BYTE_EN),
.MWIDTH_BYTES(MWIDTH_BYTES),
.ALIGNMENT_ABITS(ALIGNMENT_ABITS)
) basic_coalesced_write (
.clk(clock),
.reset(!sync_rstn),
.o_stall(lsu_o_stall),
.i_valid(lsu_i_valid),
.i_address(address),
.i_writedata(i_writedata),
.i_byteenable(i_byteenable),
.i_stall(lsu_i_stall),
.o_valid(lsu_o_valid),
.o_active(lsu_active),
.avm_address(avm_address_raw),
.avm_write(avm_write),
.avm_writeack(lsu_writeack),
.avm_writedata(avm_writedata),
.avm_byteenable(avm_byteenable),
.avm_waitrequest(avm_waitrequest)
);
end
assign avm_enable = 1'b1;
end
/////////////////////
// Burst Coalesced //
/////////////////////
else if(STYLE=="BURST-COALESCED")
begin
if(READ == 1)
begin
lsu_bursting_read #(
.KERNEL_SIDE_MEM_LATENCY(KERNEL_SIDE_MEM_LATENCY),
.MEMORY_SIDE_MEM_LATENCY(MEMORY_SIDE_MEM_LATENCY),
.AWIDTH(AWIDTH),
.WIDTH_BYTES(WIDTH_BYTES),
.MWIDTH_BYTES(MWIDTH_BYTES),
.ALIGNMENT_ABITS(ALIGNMENT_ABITS),
.BURSTCOUNT_WIDTH(BURSTCOUNT_WIDTH),
.USECACHING(USECACHING),
.HIGH_FMAX(HIGH_FMAX),
.ACL_PROFILE(ACL_PROFILE),
.CACHE_SIZE_N(CACHESIZE),
.INTENDED_DEVICE_FAMILY(INTENDED_DEVICE_FAMILY)
) bursting_read (
.clk(clock),
.clk2x(clock2x),
.reset(!sync_rstn),
.flush(flush),
.i_nop(i_predicate),
.o_stall(lsu_o_stall),
.i_valid(lsu_i_valid),
.i_address(address),
.i_stall(lsu_i_stall),
.o_valid(lsu_o_valid),
.o_readdata(o_readdata),
.o_active(lsu_active),
.avm_address(avm_address_raw),
.avm_read(avm_read),
.avm_readdata(avm_readdata),
.avm_waitrequest(avm_waitrequest),
.avm_byteenable(avm_byteenable),
.avm_burstcount(avm_burstcount),
.avm_readdatavalid(avm_readdatavalid),
.req_cache_hit_count(req_cache_hit_count)
);
end
else
begin
// Non-writeack stores are similar to streaming, where the pipeline
// needs only few threads which just drop off data, and internally the
// LSU must account for arbitration contention and other delays.
if ((USE_WRITE_ACK == 1) || (USE_WRITE_ACK == 0))
begin
lsu_bursting_write #(
.KERNEL_SIDE_MEM_LATENCY(KERNEL_SIDE_MEM_LATENCY),
.MEMORY_SIDE_MEM_LATENCY(MEMORY_SIDE_MEM_LATENCY),
.AWIDTH(AWIDTH),
.WIDTH_BYTES(WIDTH_BYTES),
.MWIDTH_BYTES(MWIDTH_BYTES),
.ALIGNMENT_ABITS(ALIGNMENT_ABITS),
.BURSTCOUNT_WIDTH(BURSTCOUNT_WIDTH),
.USE_WRITE_ACK(USE_WRITE_ACK),
.USE_BYTE_EN(USE_BYTE_EN),
.HIGH_FMAX(HIGH_FMAX)
) bursting_write (
.clk(clock),
.clk2x(clock2x),
.reset(!sync_rstn),
.o_stall(lsu_o_stall),
.i_valid(lsu_i_valid),
.i_nop(i_predicate),
.i_address(address),
.i_writedata(i_writedata),
.i_stall(lsu_i_stall),
.o_valid(lsu_o_valid),
.o_active(lsu_active),
.i_byteenable(i_byteenable),
.avm_address(avm_address_raw),
.avm_write(avm_write),
.avm_writeack(lsu_writeack),
.avm_writedata(avm_writedata),
.avm_byteenable(avm_byteenable),
.avm_burstcount(avm_burstcount),
.avm_waitrequest(avm_waitrequest)
);
end
else
begin
acl_aligned_burst_coalesced_lsu #(
.KERNEL_SIDE_MEM_LATENCY(KERNEL_SIDE_MEM_LATENCY),
.MEMORY_SIDE_MEM_LATENCY(MEMORY_SIDE_MEM_LATENCY),
.AWIDTH(AWIDTH),
.WIDTH_BYTES(WIDTH_BYTES),
.MWIDTH_BYTES(MWIDTH_BYTES),
.ALIGNMENT_ABITS(ALIGNMENT_ABITS),
.BURSTCOUNT_WIDTH(BURSTCOUNT_WIDTH),
.USE_WRITE_ACK(USE_WRITE_ACK),
.USE_BYTE_EN(USE_BYTE_EN),
.HIGH_FMAX(HIGH_FMAX),
.INTENDED_DEVICE_FAMILY(INTENDED_DEVICE_FAMILY)
) bursting_write (
.clock(clock),
.clock2x(clock2x),
.resetn(sync_rstn),
.o_stall(lsu_o_stall),
.i_valid(lsu_i_valid),
.i_predicate(i_predicate),
.i_address(address),
.i_writedata(i_writedata),
.i_stall(lsu_i_stall),
.o_valid(lsu_o_valid),
.o_active(lsu_active),
.i_byteenable(i_byteenable),
.avm_address(avm_address_raw),
.avm_write(avm_write),
.avm_writeack(lsu_writeack),
.avm_writedata(avm_writedata),
.avm_byteenable(avm_byteenable),
.avm_burstcount(avm_burstcount),
.avm_waitrequest(avm_waitrequest)
);
end
end
assign avm_enable = 1'b1;
end
/////////////////////////////////
// Burst Coalesced Non Aligned //
/////////////////////////////////
else if(STYLE=="BURST-NON-ALIGNED")
begin
if(READ == 1)
begin
lsu_bursting_read #(
.KERNEL_SIDE_MEM_LATENCY(KERNEL_SIDE_MEM_LATENCY),
.MEMORY_SIDE_MEM_LATENCY(MEMORY_SIDE_MEM_LATENCY),
.AWIDTH(AWIDTH),
.WIDTH_BYTES(WIDTH_BYTES),
.MWIDTH_BYTES(MWIDTH_BYTES),
.ALIGNMENT_ABITS(ALIGNMENT_ABITS),
.BURSTCOUNT_WIDTH(BURSTCOUNT_WIDTH),
.USECACHING(USECACHING),
.CACHE_SIZE_N(CACHESIZE),
.HIGH_FMAX(HIGH_FMAX),
.ACL_PROFILE(ACL_PROFILE),
.UNALIGNED(1),
.INTENDED_DEVICE_FAMILY(INTENDED_DEVICE_FAMILY)
) bursting_non_aligned_read (
.clk(clock),
.clk2x(clock2x),
.reset(!sync_rstn),
.flush(flush),
.o_stall(lsu_o_stall),
.i_valid(lsu_i_valid),
.i_address(address),
.i_nop(i_predicate),
.i_stall(lsu_i_stall),
.o_valid(lsu_o_valid),
.o_readdata(o_readdata),
.o_active(lsu_active),
.avm_address(avm_address_raw),
.avm_read(avm_read),
.avm_readdata(avm_readdata),
.avm_waitrequest(avm_waitrequest),
.avm_byteenable(avm_byteenable),
.avm_burstcount(avm_burstcount),
.avm_readdatavalid(avm_readdatavalid),
.extra_unaligned_reqs(extra_unaligned_reqs),
.req_cache_hit_count(req_cache_hit_count)
);
end
else
begin
lsu_non_aligned_write #(
.KERNEL_SIDE_MEM_LATENCY(KERNEL_SIDE_MEM_LATENCY),
.MEMORY_SIDE_MEM_LATENCY(MEMORY_SIDE_MEM_LATENCY),
.AWIDTH(AWIDTH),
.WIDTH_BYTES(WIDTH_BYTES),
.MWIDTH_BYTES(MWIDTH_BYTES),
.ALIGNMENT_ABITS(ALIGNMENT_ABITS),
.BURSTCOUNT_WIDTH(BURSTCOUNT_WIDTH),
.USE_WRITE_ACK(USE_WRITE_ACK),
.USE_BYTE_EN(USE_BYTE_EN),
.HIGH_FMAX(HIGH_FMAX),
.ACL_PROFILE(ACL_PROFILE)
) bursting_non_aligned_write (
.clk(clock),
.clk2x(clock2x),
.reset(!sync_rstn),
.o_stall(lsu_o_stall),
.i_valid(lsu_i_valid),
.i_address(address),
.i_nop(i_predicate),
.i_writedata(i_writedata),
.i_stall(lsu_i_stall),
.o_valid(lsu_o_valid),
.o_active(lsu_active),
.i_byteenable(i_byteenable),
.avm_address(avm_address_raw),
.avm_write(avm_write),
.avm_writeack(lsu_writeack),
.avm_writedata(avm_writedata),
.avm_byteenable(avm_byteenable),
.avm_burstcount(avm_burstcount),
.avm_waitrequest(avm_waitrequest),
.extra_unaligned_reqs(extra_unaligned_reqs)
);
end
assign avm_enable = 1'b1;
end
///////////////
// Streaming //
///////////////
else if(STYLE=="STREAMING")
begin
if(READ==1)
begin
lsu_streaming_read #(
.KERNEL_SIDE_MEM_LATENCY(KERNEL_SIDE_MEM_LATENCY),
.MEMORY_SIDE_MEM_LATENCY(MEMORY_SIDE_MEM_LATENCY),
.AWIDTH(AWIDTH),
.WIDTH_BYTES(WIDTH_BYTES),
.MWIDTH_BYTES(MWIDTH_BYTES),
.ALIGNMENT_ABITS(ALIGNMENT_ABITS),
.BURSTCOUNT_WIDTH(BURSTCOUNT_WIDTH)
) streaming_read (
.clk(clock),
.reset(!sync_rstn),
.o_stall(lsu_o_stall),
.i_valid(lsu_i_valid),
.i_stall(lsu_i_stall),
.o_valid(lsu_o_valid),
.o_readdata(o_readdata),
.o_active(lsu_active),
.i_nop(i_predicate),
.base_address(stream_base_addr),
.size(stream_size),
.avm_address(avm_address_raw),
.avm_burstcount(avm_burstcount),
.avm_read(avm_read),
.avm_readdata(avm_readdata),
.avm_waitrequest(avm_waitrequest),
.avm_byteenable(avm_byteenable),
.avm_readdatavalid(avm_readdatavalid)
);
end
else
begin
lsu_streaming_write #(
.KERNEL_SIDE_MEM_LATENCY(KERNEL_SIDE_MEM_LATENCY),
.MEMORY_SIDE_MEM_LATENCY(MEMORY_SIDE_MEM_LATENCY),
.AWIDTH(AWIDTH),
.WIDTH_BYTES(WIDTH_BYTES),
.MWIDTH_BYTES(MWIDTH_BYTES),
.ALIGNMENT_ABITS(ALIGNMENT_ABITS),
.BURSTCOUNT_WIDTH(BURSTCOUNT_WIDTH),
.USE_BYTE_EN(USE_BYTE_EN)
) streaming_write (
.clk(clock),
.reset(!sync_rstn),
.o_stall(lsu_o_stall),
.i_valid(lsu_i_valid),
.i_stall(lsu_i_stall),
.o_valid(lsu_o_valid),
.o_active(lsu_active),
.i_byteenable(i_byteenable),
.i_writedata(i_writedata),
.i_nop(i_predicate),
.base_address(stream_base_addr),
.size(stream_size),
.avm_address(avm_address_raw),
.avm_burstcount(avm_burstcount),
.avm_write(avm_write),
.avm_writeack(lsu_writeack),
.avm_writedata(avm_writedata),
.avm_byteenable(avm_byteenable),
.avm_waitrequest(avm_waitrequest)
);
end
assign avm_enable = 1'b1;
end
////////////////////
// SEMI-Streaming //
////////////////////
else if(STYLE=="SEMI-STREAMING")
begin
if(READ==1)
begin
lsu_read_cache #(
.KERNEL_SIDE_MEM_LATENCY(KERNEL_SIDE_MEM_LATENCY),
.AWIDTH(AWIDTH),
.WIDTH_BYTES(WIDTH_BYTES),
.MWIDTH_BYTES(MWIDTH_BYTES),
.ALIGNMENT_ABITS(ALIGNMENT_ABITS),
.BURSTCOUNT_WIDTH(BURSTCOUNT_WIDTH),
.ACL_PROFILE(ACL_PROFILE),
.REQUESTED_SIZE(CACHESIZE)
) read_cache (
.clk(clock),
.reset(!sync_rstn),
.flush(flush),
.o_stall(lsu_o_stall),
.i_valid(lsu_i_valid),
.i_address(address),
.i_stall(lsu_i_stall),
.o_valid(lsu_o_valid),
.o_readdata(o_readdata),
.o_active(lsu_active),
.i_nop(i_predicate),
.avm_address(avm_address_raw),
.avm_burstcount(avm_burstcount),
.avm_read(avm_read),
.avm_readdata(avm_readdata),
.avm_waitrequest(avm_waitrequest),
.avm_byteenable(avm_byteenable),
.avm_readdatavalid(avm_readdatavalid),
.req_cache_hit_count(req_cache_hit_count)
);
end
assign avm_enable = 1'b1;
end
/////////////////
// Prefetching //
/////////////////
else if(STYLE=="PREFETCHING")
begin
if(READ==1)
begin
lsu_streaming_prefetch_read #(
.KERNEL_SIDE_MEM_LATENCY(KERNEL_SIDE_MEM_LATENCY),
.MEMORY_SIDE_MEM_LATENCY(MEMORY_SIDE_MEM_LATENCY),
.AWIDTH(AWIDTH),
.WIDTH_BYTES(WIDTH_BYTES),
.MWIDTH_BYTES(MWIDTH_BYTES),
.ALIGNMENT_ABITS(ALIGNMENT_ABITS),
.BURSTCOUNT_WIDTH(BURSTCOUNT_WIDTH)
) streaming_prefetch_read (
.clk(clock),
.reset(!sync_rstn),
.flush(flush),
.o_stall(lsu_o_stall),
.i_valid(lsu_i_valid),
.i_stall(lsu_i_stall),
.o_valid(lsu_o_valid),
.o_readdata(o_readdata),
.o_active(lsu_active),
.i_nop(i_predicate),
.i_address(address),
.avm_address(avm_address_raw),
.avm_burstcount(avm_burstcount),
.avm_read(avm_read),
.avm_readdata(avm_readdata),
.avm_waitrequest(avm_waitrequest),
.avm_byteenable(avm_byteenable),
.avm_readdatavalid(avm_readdatavalid)
);
end
else
begin
// Use Burst Coalesced Non Aligned for Writes in Prefetching style
lsu_non_aligned_write #(
.KERNEL_SIDE_MEM_LATENCY(KERNEL_SIDE_MEM_LATENCY),
.MEMORY_SIDE_MEM_LATENCY(MEMORY_SIDE_MEM_LATENCY),
.AWIDTH(AWIDTH),
.WIDTH_BYTES(WIDTH_BYTES),
.MWIDTH_BYTES(MWIDTH_BYTES),
.ALIGNMENT_ABITS(ALIGNMENT_ABITS),
.BURSTCOUNT_WIDTH(BURSTCOUNT_WIDTH),
.USE_WRITE_ACK(USE_WRITE_ACK),
.USE_BYTE_EN(USE_BYTE_EN),
.HIGH_FMAX(HIGH_FMAX),
.ACL_PROFILE(ACL_PROFILE)
) bursting_non_aligned_write (
.clk(clock),
.clk2x(clock2x),
.reset(!sync_rstn),
.o_stall(lsu_o_stall),
.i_valid(lsu_i_valid),
.i_address(address),
.i_nop(i_predicate),
.i_writedata(i_writedata),
.i_stall(lsu_i_stall),
.o_valid(lsu_o_valid),
.o_active(lsu_active),
.i_byteenable(i_byteenable),
.avm_address(avm_address_raw),
.avm_write(avm_write),
.avm_writeack(lsu_writeack),
.avm_writedata(avm_writedata),
.avm_byteenable(avm_byteenable),
.avm_burstcount(avm_burstcount),
.avm_waitrequest(avm_waitrequest),
.extra_unaligned_reqs(extra_unaligned_reqs)
);
end
assign avm_enable = 1'b1;
end
always@(posedge clock or negedge sync_rstn)
if (!sync_rstn)
o_active <= 1'b0;
else
o_active <= lsu_active;
// Profile the valids and stalls of the LSU
if(ACL_PROFILE==1)
begin
// keep track of write bursts
reg [BURSTCOUNT_WIDTH-1:0] profile_remaining_writeburst_count;
wire active_write_burst;
assign active_write_burst = (profile_remaining_writeburst_count != {BURSTCOUNT_WIDTH{1'b0}});
always@(posedge clock or negedge sync_rstn)
if (!sync_rstn)
profile_remaining_writeburst_count <= {BURSTCOUNT_WIDTH{1'b0}};
else if(avm_write & ~avm_waitrequest & ~active_write_burst)
// start of a new write burst
profile_remaining_writeburst_count <= avm_burstcount - 1;
else if(~avm_waitrequest & active_write_burst)
// count down one burst
profile_remaining_writeburst_count <= profile_remaining_writeburst_count - 1;
assign profile_bw = ((READ==1) ? avm_readdatavalid : (avm_write & ~avm_waitrequest)) & avm_enable;
assign profile_bw_incr = MWIDTH_BYTES;
assign profile_total_ivalid = (i_valid & ~o_stall);
assign profile_total_req = (i_valid & ~i_predicate & ~o_stall);
assign profile_i_stall_count = (i_stall & o_valid);
assign profile_o_stall_count = (o_stall & i_valid);
assign profile_avm_readwrite_count = ((avm_read | avm_write) & ~avm_waitrequest & ~active_write_burst & avm_enable);
assign profile_avm_burstcount_total = ((avm_read | avm_write) & ~avm_waitrequest & ~active_write_burst & avm_enable);
assign profile_avm_burstcount_total_incr = avm_burstcount;
assign profile_req_cache_hit_count = req_cache_hit_count;
assign profile_extra_unaligned_reqs = extra_unaligned_reqs;
assign profile_avm_stall = ((avm_read | avm_write) & avm_waitrequest & avm_enable);
end
else begin
assign profile_bw = 1'b0;
assign profile_bw_incr = {ACL_PROFILE_INCREMENT_WIDTH{1'b0}};
assign profile_total_ivalid = 1'b0;
assign profile_total_req = 1'b0;
assign profile_i_stall_count = 1'b0;
assign profile_o_stall_count = 1'b0;
assign profile_avm_readwrite_count = 1'b0;
assign profile_avm_burstcount_total = 1'b0;
assign profile_avm_burstcount_total_incr = {ACL_PROFILE_INCREMENT_WIDTH{1'b0}};
assign profile_req_cache_hit_count = 1'b0;
assign profile_extra_unaligned_reqs = 1'b0;
assign profile_avm_stall = 1'b0;
end
// synthesis translate_off
// Profiling data - for simulation only
reg [31:0] bw_kernel;
reg [31:0] bw_avalon;
// Measure Bandwidth on Avalon signals
always@(posedge clock or negedge sync_rstn)
begin
if (!sync_rstn)
bw_avalon <= 0;
else
if (READ==1 && avm_readdatavalid)
bw_avalon <= bw_avalon + MWIDTH_BYTES;
else if (READ==0 && avm_write && ~avm_waitrequest)
bw_avalon <= bw_avalon + MWIDTH_BYTES;
end
// Measure Bandwidth on kernel signals
always@(posedge clock or negedge sync_rstn)
begin
if (!sync_rstn)
bw_kernel <= 0;
else if (i_valid && !o_stall && ~nop)
bw_kernel <= bw_kernel + WIDTH_BYTES;
end
// synthesis translate_on
if(PROFILE_ADDR_TOGGLE==1 && STYLE!="SIMPLE")
begin
localparam COUNTERWIDTH=12;
// We currently assume AWIDTH is always 32, but we really need to set this to
// a tight lower bound to avoid wasting area here.
logic [COUNTERWIDTH-1:0] togglerate[AWIDTH-ALIGNMENT_ABITS+1];
acl_toggle_detect
#(.WIDTH(AWIDTH-ALIGNMENT_ABITS), .COUNTERWIDTH(COUNTERWIDTH)) atd (
.clk(clock),
.resetn(sync_rstn),
.valid(i_valid && ~o_stall && ~nop),
.value({i_address >> ALIGNMENT_ABITS,{ALIGNMENT_ABITS{1'b0}}}),
.count(togglerate));
acl_debug_mem #(.WIDTH(COUNTERWIDTH), .SIZE(AWIDTH-ALIGNMENT_ABITS+1)) dbg_mem (
.clk(clock),
.resetn(sync_rstn),
.write(i_valid && ~o_stall && ~nop),
.data(togglerate));
end
end
endgenerate
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O2111AI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__O2111AI_FUNCTIONAL_PP_V
/**
* o2111ai: 2-input OR into first input of 4-input NAND.
*
* Y = !((A1 | A2) & B1 & C1 & D1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__o2111ai (
VPWR,
VGND,
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
D1
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
// Local signals
wire C1 or0_out ;
wire nand0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y , C1, B1, D1, or0_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__O2111AI_FUNCTIONAL_PP_V
|
/*================================================
Thomas Gorham
ECE 441 Spring 2017
Project 2 - bcd_ctr
Description: This module implements a 3-digit
bcd counter with async reset and enable inputs.
It is intended to be controlled by a state machine
that manages inputs from the lfsr and pushbuttons
================================================*/
`timescale 100 ns / 1 ns
module bcd_ctr(clk, en, ar, dig1, dig2, dig3);
/*======================================
Parameters
======================================*/
/*======================================
Input/Output Declaration
======================================*/
input clk, ar, en;
output reg [3:0] dig1, dig2, dig3;
/*======================================
Internal wires/registers
======================================*/
wire dig1_carry, dig2_carry, dig3_carry;
/*======================================
Asynchronous Logic
======================================*/
assign dig1_carry = (dig1 == 4'd9); // Flag to indicate when to inc dig2
assign dig2_carry = dig1_carry&(dig2 == 4'd9); // Indicates when to inc dig3
assign dig3_carry = dig2_carry&(dig3 == 4'd9); // Indicates when timer should freeze
/*======================================
Synchronous Logic
======================================*/
always @ (posedge clk or negedge ar)
begin
if(~ar) // If ar is brought low, (or is low on a clk posedge)
begin
// Reset the current count
dig1 <= 4'd0;
dig2 <= 4'd0;
dig3 <= 4'd0;
end else if(~dig3_carry&en) // Only run the counter if en high and not at 999
begin
if(dig2_carry) // If dig2 and dig1 are 9's
begin
dig3 <= dig3 + 1; // Increment dig3
dig2 <= 0; // Reset the lower digits
dig1 <= 0;
end else if(dig1_carry) // If dig1 is a 9
begin
dig2 <= dig2 + 1; // Increment dig2
dig1 <= 0; // Reset lower digits
end else // If no carry-magic had to occur
begin
dig1 <= dig1 + 1; // Count normally
end
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLXTP_SYMBOL_V
`define SKY130_FD_SC_HD__DLXTP_SYMBOL_V
/**
* dlxtp: Delay latch, non-inverted enable, single output.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__dlxtp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{clocks|Clocking}}
input GATE
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLXTP_SYMBOL_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:58:40 05/12/2015
// Design Name:
// Module Name: ME_WB
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module ME_WB(
clk,rst,stall,
me_memdata, me_td, me_WREG,
wb_memdata, wb_td, wb_WREG
);
input clk,rst,stall;
input wire [31:0] me_memdata;
input wire [4:0] me_td;
input wire me_WREG;
output reg [31:0] wb_memdata;
output reg [4:0] wb_td;
output reg wb_WREG;
always @(posedge clk or posedge rst)
begin
if(rst)
begin
wb_memdata <= 0;
wb_td <= 0;
wb_WREG <= 0;
end
else if(stall)
begin
wb_memdata <= 0;
wb_td <= 0;
wb_WREG <= 0;
end
else
begin
wb_memdata <= me_memdata;
wb_td <= me_td;
wb_WREG <= me_WREG;
end
end
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2009-2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : V5-Block Plus for PCI Express
// File : xilinx_pci_exp_ep.v
//
// Description: PCI Express Endpoint Core example design top level wrapper.
//
//------------------------------------------------------------------------------
module xilinx_pci_exp_ep
(
// PCI Express Fabric Interface
pci_exp_txp,
pci_exp_txn,
pci_exp_rxp,
pci_exp_rxn,
// System (SYS) Interface
sys_clk_p,
sys_clk_n,
sys_reset_n,
refclkout
);//synthesis syn_noclockbuf=1
//-------------------------------------------------------
// 1. PCI Express Fabric Interface
//-------------------------------------------------------
// Tx
output [(1 - 1):0] pci_exp_txp;
output [(1 - 1):0] pci_exp_txn;
// Rx
input [(1 - 1):0] pci_exp_rxp;
input [(1 - 1):0] pci_exp_rxn;
//-------------------------------------------------------
// 4. System (SYS) Interface
//-------------------------------------------------------
input sys_clk_p;
input sys_clk_n;
input sys_reset_n;
output refclkout;
//-------------------------------------------------------
// Local Wires
//-------------------------------------------------------
wire sys_clk_c;
wire sys_reset_n_c;
wire trn_clk_c;//synthesis attribute max_fanout of trn_clk_c is "100000"
wire trn_reset_n_c;
wire trn_lnk_up_n_c;
wire cfg_trn_pending_n_c;
wire [(64 - 1):0] cfg_dsn_n_c;
wire trn_tsof_n_c;
wire trn_teof_n_c;
wire trn_tsrc_rdy_n_c;
wire trn_tdst_rdy_n_c;
wire trn_tsrc_dsc_n_c;
wire trn_terrfwd_n_c;
wire trn_tdst_dsc_n_c;
wire [(64 - 1):0] trn_td_c;
wire [7:0] trn_trem_n_c;
wire [( 4 -1 ):0] trn_tbuf_av_c;
wire trn_rsof_n_c;
wire trn_reof_n_c;
wire trn_rsrc_rdy_n_c;
wire trn_rsrc_dsc_n_c;
wire trn_rdst_rdy_n_c;
wire trn_rerrfwd_n_c;
wire trn_rnp_ok_n_c;
wire [(64 - 1):0] trn_rd_c;
wire [7:0] trn_rrem_n_c;
wire [6:0] trn_rbar_hit_n_c;
wire [7:0] trn_rfc_nph_av_c;
wire [11:0] trn_rfc_npd_av_c;
wire [7:0] trn_rfc_ph_av_c;
wire [11:0] trn_rfc_pd_av_c;
wire trn_rcpl_streaming_n_c;
wire [31:0] cfg_do_c;
wire [31:0] cfg_di_c;
wire [9:0] cfg_dwaddr_c;
wire [3:0] cfg_byte_en_n_c;
wire [47:0] cfg_err_tlp_cpl_header_c;
wire cfg_wr_en_n_c;
wire cfg_rd_en_n_c;
wire cfg_rd_wr_done_n_c;
wire cfg_err_cor_n_c;
wire cfg_err_ur_n_c;
wire cfg_err_cpl_rdy_n_c;
wire cfg_err_ecrc_n_c;
wire cfg_err_cpl_timeout_n_c;
wire cfg_err_cpl_abort_n_c;
wire cfg_err_cpl_unexpect_n_c;
wire cfg_err_posted_n_c;
wire cfg_err_locked_n_c;
wire cfg_interrupt_n_c;
wire cfg_interrupt_rdy_n_c;
wire cfg_interrupt_assert_n_c;
wire [7 : 0] cfg_interrupt_di_c;
wire [7 : 0] cfg_interrupt_do_c;
wire [2 : 0] cfg_interrupt_mmenable_c;
wire cfg_interrupt_msienable_c;
wire cfg_turnoff_ok_n_c;
wire cfg_to_turnoff_n;
wire cfg_pm_wake_n_c;
wire [2:0] cfg_pcie_link_state_n_c;
wire [7:0] cfg_bus_number_c;
wire [4:0] cfg_device_number_c;
wire [2:0] cfg_function_number_c;
wire [15:0] cfg_status_c;
wire [15:0] cfg_command_c;
wire [15:0] cfg_dstatus_c;
wire [15:0] cfg_dcommand_c;
wire [15:0] cfg_lstatus_c;
wire [15:0] cfg_lcommand_c;
//-------------------------------------------------------
// Virtex5-FX Global Clock Buffer
//-------------------------------------------------------
IBUFDS refclk_ibuf (.O(sys_clk_c), .I(sys_clk_p), .IB(sys_clk_n)); // 100 MHz
//-------------------------------------------------------
// System Reset Input Pad Instance
//-------------------------------------------------------
IBUF sys_reset_n_ibuf (.O(sys_reset_n_c), .I(sys_reset_n));
//-------------------------------------------------------
// Endpoint Implementation Application
//-------------------------------------------------------
pci_exp_64b_app app (
//
// Transaction ( TRN ) Interface
//
.trn_clk( trn_clk_c ), // I
.trn_reset_n( trn_reset_n_c ), // I
.trn_lnk_up_n( trn_lnk_up_n_c ), // I
// Tx Local-Link
.trn_td( trn_td_c ), // O [63/31:0]
.trn_trem( trn_trem_n_c ), // O [7:0]
.trn_tsof_n( trn_tsof_n_c ), // O
.trn_teof_n( trn_teof_n_c ), // O
.trn_tsrc_rdy_n( trn_tsrc_rdy_n_c ), // O
.trn_tsrc_dsc_n( trn_tsrc_dsc_n_c ), // O
.trn_tdst_rdy_n( trn_tdst_rdy_n_c ), // I
.trn_tdst_dsc_n( trn_tdst_dsc_n_c ), // I
.trn_terrfwd_n( trn_terrfwd_n_c ), // O
.trn_tbuf_av( trn_tbuf_av_c ), // I [4/3:0]
// Rx Local-Link
.trn_rd( trn_rd_c ), // I [63/31:0]
.trn_rrem( trn_rrem_n_c ), // I [7:0]
.trn_rsof_n( trn_rsof_n_c ), // I
.trn_reof_n( trn_reof_n_c ), // I
.trn_rsrc_rdy_n( trn_rsrc_rdy_n_c ), // I
.trn_rsrc_dsc_n( trn_rsrc_dsc_n_c ), // I
.trn_rdst_rdy_n( trn_rdst_rdy_n_c ), // O
.trn_rerrfwd_n( trn_rerrfwd_n_c ), // I
.trn_rnp_ok_n( trn_rnp_ok_n_c ), // O
.trn_rbar_hit_n( trn_rbar_hit_n_c ), // I [6:0]
.trn_rfc_npd_av( trn_rfc_npd_av_c ), // I [11:0]
.trn_rfc_nph_av( trn_rfc_nph_av_c ), // I [7:0]
.trn_rfc_pd_av( trn_rfc_pd_av_c ), // I [11:0]
.trn_rfc_ph_av( trn_rfc_ph_av_c ), // I [7:0]
.trn_rcpl_streaming_n( trn_rcpl_streaming_n_c ), // O
//
// Host ( CFG ) Interface
//
.cfg_do( cfg_do_c ), // I [31:0]
.cfg_rd_wr_done_n( cfg_rd_wr_done_n_c ), // I
.cfg_di( cfg_di_c ), // O [31:0]
.cfg_byte_en_n( cfg_byte_en_n_c ), // O
.cfg_dwaddr( cfg_dwaddr_c ), // O
.cfg_wr_en_n( cfg_wr_en_n_c ), // O
.cfg_rd_en_n( cfg_rd_en_n_c ), // O
.cfg_err_cor_n( cfg_err_cor_n_c ), // O
.cfg_err_ur_n( cfg_err_ur_n_c ), // O
.cfg_err_cpl_rdy_n( cfg_err_cpl_rdy_n_c ), // I
.cfg_err_ecrc_n( cfg_err_ecrc_n_c ), // O
.cfg_err_cpl_timeout_n( cfg_err_cpl_timeout_n_c ), // O
.cfg_err_cpl_abort_n( cfg_err_cpl_abort_n_c ), // O
.cfg_err_cpl_unexpect_n( cfg_err_cpl_unexpect_n_c ), // O
.cfg_err_posted_n( cfg_err_posted_n_c ), // O
.cfg_err_tlp_cpl_header( cfg_err_tlp_cpl_header_c ), // O [47:0]
.cfg_interrupt_n( cfg_interrupt_n_c ), // O
.cfg_interrupt_rdy_n( cfg_interrupt_rdy_n_c ), // I
.cfg_interrupt_assert_n(cfg_interrupt_assert_n_c), // O
.cfg_interrupt_di(cfg_interrupt_di_c), // O [7:0]
.cfg_interrupt_do(cfg_interrupt_do_c), // I [7:0]
.cfg_interrupt_mmenable(cfg_interrupt_mmenable_c), // I [2:0]
.cfg_interrupt_msienable(cfg_interrupt_msienable_c), // I
.cfg_to_turnoff_n( cfg_to_turnoff_n_c ), // I
.cfg_pm_wake_n( cfg_pm_wake_n_c ), // O
.cfg_pcie_link_state_n( cfg_pcie_link_state_n_c ), // I [2:0]
.cfg_trn_pending_n( cfg_trn_pending_n_c ), // O
.cfg_dsn( cfg_dsn_n_c), // O [63:0]
.cfg_bus_number( cfg_bus_number_c ), // I [7:0]
.cfg_device_number( cfg_device_number_c ), // I [4:0]
.cfg_function_number( cfg_function_number_c ), // I [2:0]
.cfg_status( cfg_status_c ), // I [15:0]
.cfg_command( cfg_command_c ), // I [15:0]
.cfg_dstatus( cfg_dstatus_c ), // I [15:0]
.cfg_dcommand( cfg_dcommand_c ), // I [15:0]
.cfg_lstatus( cfg_lstatus_c ), // I [15:0]
.cfg_lcommand( cfg_lcommand_c ) // I [15:0]
);
endpoint_blk_plus_v1_14 ep (
//
// PCI Express Fabric Interface
//
.pci_exp_txp( pci_exp_txp ), // O [7/3/0:0]
.pci_exp_txn( pci_exp_txn ), // O [7/3/0:0]
.pci_exp_rxp( pci_exp_rxp ), // O [7/3/0:0]
.pci_exp_rxn( pci_exp_rxn ), // O [7/3/0:0]
//
// System ( SYS ) Interface
//
.sys_clk( sys_clk_c ), // I
.sys_reset_n( sys_reset_n_c ), // I
.refclkout( refclkout ), // O
//
// Transaction ( TRN ) Interface
//
.trn_clk( trn_clk_c ), // O
.trn_reset_n( trn_reset_n_c ), // O
.trn_lnk_up_n( trn_lnk_up_n_c ), // O
// Tx Local-Link
.trn_td( trn_td_c ), // I [63/31:0]
.trn_trem_n( trn_trem_n_c ), // I [7:0]
.trn_tsof_n( trn_tsof_n_c ), // I
.trn_teof_n( trn_teof_n_c ), // I
.trn_tsrc_rdy_n( trn_tsrc_rdy_n_c ), // I
.trn_tsrc_dsc_n( trn_tsrc_dsc_n_c ), // I
.trn_tdst_rdy_n( trn_tdst_rdy_n_c ), // O
.trn_tdst_dsc_n( trn_tdst_dsc_n_c ), // O
.trn_terrfwd_n( trn_terrfwd_n_c ), // I
.trn_tbuf_av( trn_tbuf_av_c ), // O [4/3:0]
// Rx Local-Link
.trn_rd( trn_rd_c ), // O [63/31:0]
.trn_rrem_n( trn_rrem_n_c ), // O [7:0]
.trn_rsof_n( trn_rsof_n_c ), // O
.trn_reof_n( trn_reof_n_c ), // O
.trn_rsrc_rdy_n( trn_rsrc_rdy_n_c ), // O
.trn_rsrc_dsc_n( trn_rsrc_dsc_n_c ), // O
.trn_rdst_rdy_n( trn_rdst_rdy_n_c ), // I
.trn_rerrfwd_n( trn_rerrfwd_n_c ), // O
.trn_rnp_ok_n( trn_rnp_ok_n_c ), // I
.trn_rbar_hit_n( trn_rbar_hit_n_c ), // O [6:0]
.trn_rfc_nph_av( trn_rfc_nph_av_c ), // O [11:0]
.trn_rfc_npd_av( trn_rfc_npd_av_c ), // O [7:0]
.trn_rfc_ph_av( trn_rfc_ph_av_c ), // O [11:0]
.trn_rfc_pd_av( trn_rfc_pd_av_c ), // O [7:0]
.trn_rcpl_streaming_n( trn_rcpl_streaming_n_c ), // I
//
// Host ( CFG ) Interface
//
.cfg_do( cfg_do_c ), // O [31:0]
.cfg_rd_wr_done_n( cfg_rd_wr_done_n_c ), // O
.cfg_di( cfg_di_c ), // I [31:0]
.cfg_byte_en_n( cfg_byte_en_n_c ), // I [3:0]
.cfg_dwaddr( cfg_dwaddr_c ), // I [9:0]
.cfg_wr_en_n( cfg_wr_en_n_c ), // I
.cfg_rd_en_n( cfg_rd_en_n_c ), // I
.cfg_err_cor_n( cfg_err_cor_n_c ), // I
.cfg_err_ur_n( cfg_err_ur_n_c ), // I
.cfg_err_cpl_rdy_n( cfg_err_cpl_rdy_n_c ), // O
.cfg_err_ecrc_n( cfg_err_ecrc_n_c ), // I
.cfg_err_cpl_timeout_n( cfg_err_cpl_timeout_n_c ), // I
.cfg_err_cpl_abort_n( cfg_err_cpl_abort_n_c ), // I
.cfg_err_cpl_unexpect_n( cfg_err_cpl_unexpect_n_c ), // I
.cfg_err_posted_n( cfg_err_posted_n_c ), // I
.cfg_err_tlp_cpl_header( cfg_err_tlp_cpl_header_c ), // I [47:0]
.cfg_err_locked_n( 1'b1 ), // I
.cfg_interrupt_n( cfg_interrupt_n_c ), // I
.cfg_interrupt_rdy_n( cfg_interrupt_rdy_n_c ), // O
.cfg_interrupt_assert_n(cfg_interrupt_assert_n_c), // I
.cfg_interrupt_di(cfg_interrupt_di_c), // I [7:0]
.cfg_interrupt_do(cfg_interrupt_do_c), // O [7:0]
.cfg_interrupt_mmenable(cfg_interrupt_mmenable_c), // O [2:0]
.cfg_interrupt_msienable(cfg_interrupt_msienable_c), // O
.cfg_to_turnoff_n( cfg_to_turnoff_n_c ), // I
.cfg_pm_wake_n( cfg_pm_wake_n_c ), // I
.cfg_pcie_link_state_n( cfg_pcie_link_state_n_c ), // O [2:0]
.cfg_trn_pending_n( cfg_trn_pending_n_c ), // I
.cfg_bus_number( cfg_bus_number_c ), // O [7:0]
.cfg_device_number( cfg_device_number_c ), // O [4:0]
.cfg_function_number( cfg_function_number_c ), // O [2:0]
.cfg_status( cfg_status_c ), // O [15:0]
.cfg_command( cfg_command_c ), // O [15:0]
.cfg_dstatus( cfg_dstatus_c ), // O [15:0]
.cfg_dcommand( cfg_dcommand_c ), // O [15:0]
.cfg_lstatus( cfg_lstatus_c ), // O [15:0]
.cfg_lcommand( cfg_lcommand_c ), // O [15:0]
.cfg_dsn( cfg_dsn_n_c), // I [63:0]
// The following is used for simulation only. Setting
// the following core input to 1 will result in a fast
// train simulation to happen. This bit should not be set
// during synthesis or the core may not operate properly.
`ifdef SIMULATION
.fast_train_simulation_only(1'b1)
`else
.fast_train_simulation_only(1'b0)
`endif
);
endmodule // XILINX_PCI_EXP_EP
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__FA_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__FA_FUNCTIONAL_PP_V
/**
* fa: Full adder.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__fa (
VPWR,
VGND,
COUT,
SUM ,
A ,
B ,
CIN
);
// Module ports
input VPWR;
input VGND;
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
// Local signals
wire CIN or0_out ;
wire CIN and0_out ;
wire CIN and1_out ;
wire csi_opt_276, nor0_out ;
wire csi_opt_276, nor1_out ;
wire or1_out_COUT ;
wire u_vpwr_vgnd0_out_COUT;
wire and2_out ;
wire or2_out_SUM ;
wire u_vpwr_vgnd1_out_SUM ;
// Name Output Other arguments
or or0 (or0_out , CIN, B );
and and0 (and0_out , or0_out, A );
and and1 (and1_out , B, CIN );
or or1 (or1_out_COUT , and1_out, and0_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_COUT, or1_out_COUT, VPWR, VGND);
buf buf0 (COUT , u_vpwr_vgnd0_out_COUT );
and and2 (and2_out , CIN, A, B );
nor nor0 (nor0_out , A, or0_out );
nor nor1 (nor1_out , nor0_out, COUT );
or or2 (or2_out_SUM , nor1_out, and2_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd1 (u_vpwr_vgnd1_out_SUM , or2_out_SUM, VPWR, VGND );
buf buf1 (SUM , u_vpwr_vgnd1_out_SUM );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__FA_FUNCTIONAL_PP_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__AND4_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__AND4_FUNCTIONAL_PP_V
/**
* and4: 4-input AND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__and4 (
VPWR,
VGND,
X ,
A ,
B ,
C ,
D
);
// Module ports
input VPWR;
input VGND;
output X ;
input A ;
input B ;
input C ;
input D ;
// Local signals
wire and0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
and and0 (and0_out_X , A, B, C, D );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__AND4_FUNCTIONAL_PP_V
|
module ibex_id_stage (
clk_i,
rst_ni,
test_en_i,
fetch_enable_i,
ctrl_busy_o,
illegal_insn_o,
instr_valid_i,
instr_new_i,
instr_rdata_i,
instr_rdata_alu_i,
instr_rdata_c_i,
instr_is_compressed_i,
instr_req_o,
instr_valid_clear_o,
id_in_ready_o,
branch_decision_i,
pc_set_o,
pc_mux_o,
exc_pc_mux_o,
exc_cause_o,
illegal_c_insn_i,
instr_fetch_err_i,
pc_id_i,
ex_valid_i,
lsu_valid_i,
alu_operator_ex_o,
alu_operand_a_ex_o,
alu_operand_b_ex_o,
jt_mux_sel_ex_o,
bt_operand_imm_o,
mult_en_ex_o,
div_en_ex_o,
multdiv_sel_ex_o,
multdiv_operator_ex_o,
multdiv_signed_mode_ex_o,
multdiv_operand_a_ex_o,
multdiv_operand_b_ex_o,
csr_access_o,
csr_op_o,
csr_save_if_o,
csr_save_id_o,
csr_restore_mret_id_o,
csr_restore_dret_id_o,
csr_save_cause_o,
csr_mtval_o,
priv_mode_i,
csr_mstatus_tw_i,
illegal_csr_insn_i,
data_req_ex_o,
data_we_ex_o,
data_type_ex_o,
data_sign_ext_ex_o,
data_wdata_ex_o,
lsu_addr_incr_req_i,
lsu_addr_last_i,
csr_mstatus_mie_i,
irq_pending_i,
irqs_i,
irq_nm_i,
nmi_mode_o,
lsu_load_err_i,
lsu_store_err_i,
debug_mode_o,
debug_cause_o,
debug_csr_save_o,
debug_req_i,
debug_single_step_i,
debug_ebreakm_i,
debug_ebreaku_i,
trigger_match_i,
regfile_wdata_lsu_i,
regfile_wdata_ex_i,
csr_rdata_i,
perf_jump_o,
perf_branch_o,
perf_tbranch_o,
instr_ret_o,
instr_ret_compressed_o
);
localparam [0:0] IDLE = 0;
localparam [0:0] WAIT_MULTICYCLE = 1;
parameter RV32E = 0;
parameter RV32M = 1;
parameter BranchTargetALU = 0;
input wire clk_i;
input wire rst_ni;
input wire test_en_i;
input wire fetch_enable_i;
output wire ctrl_busy_o;
output wire illegal_insn_o;
input wire instr_valid_i;
input wire instr_new_i;
input wire [31:0] instr_rdata_i;
input wire [31:0] instr_rdata_alu_i;
input wire [15:0] instr_rdata_c_i;
input wire instr_is_compressed_i;
output wire instr_req_o;
output wire instr_valid_clear_o;
output wire id_in_ready_o;
input wire branch_decision_i;
output wire pc_set_o;
output wire [2:0] pc_mux_o;
output wire [1:0] exc_pc_mux_o;
output wire [5:0] exc_cause_o;
input wire illegal_c_insn_i;
input wire instr_fetch_err_i;
input wire [31:0] pc_id_i;
input wire ex_valid_i;
input wire lsu_valid_i;
output wire [4:0] alu_operator_ex_o;
output wire [31:0] alu_operand_a_ex_o;
output wire [31:0] alu_operand_b_ex_o;
output wire [0:0] jt_mux_sel_ex_o;
output wire [11:0] bt_operand_imm_o;
output wire mult_en_ex_o;
output wire div_en_ex_o;
output wire multdiv_sel_ex_o;
output wire [1:0] multdiv_operator_ex_o;
output wire [1:0] multdiv_signed_mode_ex_o;
output wire [31:0] multdiv_operand_a_ex_o;
output wire [31:0] multdiv_operand_b_ex_o;
output wire csr_access_o;
output wire [1:0] csr_op_o;
output wire csr_save_if_o;
output wire csr_save_id_o;
output wire csr_restore_mret_id_o;
output wire csr_restore_dret_id_o;
output wire csr_save_cause_o;
output wire [31:0] csr_mtval_o;
input wire [1:0] priv_mode_i;
input wire csr_mstatus_tw_i;
input wire illegal_csr_insn_i;
output wire data_req_ex_o;
output wire data_we_ex_o;
output wire [1:0] data_type_ex_o;
output wire data_sign_ext_ex_o;
output wire [31:0] data_wdata_ex_o;
input wire lsu_addr_incr_req_i;
input wire [31:0] lsu_addr_last_i;
input wire csr_mstatus_mie_i;
input wire irq_pending_i;
input wire [17:0] irqs_i;
input wire irq_nm_i;
output wire nmi_mode_o;
input wire lsu_load_err_i;
input wire lsu_store_err_i;
output wire debug_mode_o;
output wire [2:0] debug_cause_o;
output wire debug_csr_save_o;
input wire debug_req_i;
input wire debug_single_step_i;
input wire debug_ebreakm_i;
input wire debug_ebreaku_i;
input wire trigger_match_i;
input wire [31:0] regfile_wdata_lsu_i;
input wire [31:0] regfile_wdata_ex_i;
input wire [31:0] csr_rdata_i;
output wire perf_jump_o;
output reg perf_branch_o;
output wire perf_tbranch_o;
output reg instr_ret_o;
output wire instr_ret_compressed_o;
parameter [31:0] PMP_MAX_REGIONS = 16;
parameter [31:0] PMP_CFG_W = 8;
parameter [31:0] PMP_I = 0;
parameter [31:0] PMP_D = 1;
parameter [11:0] CSR_OFF_PMP_CFG = 12'h3A0;
parameter [11:0] CSR_OFF_PMP_ADDR = 12'h3B0;
parameter [31:0] CSR_MSTATUS_MIE_BIT = 3;
parameter [31:0] CSR_MSTATUS_MPIE_BIT = 7;
parameter [31:0] CSR_MSTATUS_MPP_BIT_LOW = 11;
parameter [31:0] CSR_MSTATUS_MPP_BIT_HIGH = 12;
parameter [31:0] CSR_MSTATUS_MPRV_BIT = 17;
parameter [31:0] CSR_MSTATUS_TW_BIT = 21;
parameter [31:0] CSR_MSIX_BIT = 3;
parameter [31:0] CSR_MTIX_BIT = 7;
parameter [31:0] CSR_MEIX_BIT = 11;
parameter [31:0] CSR_MFIX_BIT_LOW = 16;
parameter [31:0] CSR_MFIX_BIT_HIGH = 30;
localparam [0:0] IMM_A_Z = 0;
localparam [0:0] JT_ALU = 0;
localparam [0:0] OP_B_REG_B = 0;
localparam [1:0] CSR_OP_READ = 0;
localparam [1:0] EXC_PC_EXC = 0;
localparam [1:0] MD_OP_MULL = 0;
localparam [1:0] OP_A_REG_A = 0;
localparam [1:0] RF_WD_LSU = 0;
localparam [2:0] IMM_B_I = 0;
localparam [2:0] PC_BOOT = 0;
localparam [4:0] ALU_ADD = 0;
localparam [0:0] IMM_A_ZERO = 1;
localparam [0:0] JT_BT_ALU = 1;
localparam [0:0] OP_B_IMM = 1;
localparam [1:0] CSR_OP_WRITE = 1;
localparam [1:0] EXC_PC_IRQ = 1;
localparam [1:0] MD_OP_MULH = 1;
localparam [1:0] OP_A_FWD = 1;
localparam [1:0] RF_WD_EX = 1;
localparam [2:0] IMM_B_S = 1;
localparam [2:0] PC_JUMP = 1;
localparam [4:0] ALU_SUB = 1;
localparam [4:0] ALU_GE = 10;
localparam [4:0] ALU_GEU = 11;
localparam [4:0] ALU_EQ = 12;
localparam [11:0] CSR_MSTATUS = 12'h300;
localparam [11:0] CSR_MISA = 12'h301;
localparam [11:0] CSR_MIE = 12'h304;
localparam [11:0] CSR_MTVEC = 12'h305;
localparam [11:0] CSR_MCOUNTINHIBIT = 12'h320;
localparam [11:0] CSR_MHPMEVENT3 = 12'h323;
localparam [11:0] CSR_MHPMEVENT4 = 12'h324;
localparam [11:0] CSR_MHPMEVENT5 = 12'h325;
localparam [11:0] CSR_MHPMEVENT6 = 12'h326;
localparam [11:0] CSR_MHPMEVENT7 = 12'h327;
localparam [11:0] CSR_MHPMEVENT8 = 12'h328;
localparam [11:0] CSR_MHPMEVENT9 = 12'h329;
localparam [11:0] CSR_MHPMEVENT10 = 12'h32A;
localparam [11:0] CSR_MHPMEVENT11 = 12'h32B;
localparam [11:0] CSR_MHPMEVENT12 = 12'h32C;
localparam [11:0] CSR_MHPMEVENT13 = 12'h32D;
localparam [11:0] CSR_MHPMEVENT14 = 12'h32E;
localparam [11:0] CSR_MHPMEVENT15 = 12'h32F;
localparam [11:0] CSR_MHPMEVENT16 = 12'h330;
localparam [11:0] CSR_MHPMEVENT17 = 12'h331;
localparam [11:0] CSR_MHPMEVENT18 = 12'h332;
localparam [11:0] CSR_MHPMEVENT19 = 12'h333;
localparam [11:0] CSR_MHPMEVENT20 = 12'h334;
localparam [11:0] CSR_MHPMEVENT21 = 12'h335;
localparam [11:0] CSR_MHPMEVENT22 = 12'h336;
localparam [11:0] CSR_MHPMEVENT23 = 12'h337;
localparam [11:0] CSR_MHPMEVENT24 = 12'h338;
localparam [11:0] CSR_MHPMEVENT25 = 12'h339;
localparam [11:0] CSR_MHPMEVENT26 = 12'h33A;
localparam [11:0] CSR_MHPMEVENT27 = 12'h33B;
localparam [11:0] CSR_MHPMEVENT28 = 12'h33C;
localparam [11:0] CSR_MHPMEVENT29 = 12'h33D;
localparam [11:0] CSR_MHPMEVENT30 = 12'h33E;
localparam [11:0] CSR_MHPMEVENT31 = 12'h33F;
localparam [11:0] CSR_MSCRATCH = 12'h340;
localparam [11:0] CSR_MEPC = 12'h341;
localparam [11:0] CSR_MCAUSE = 12'h342;
localparam [11:0] CSR_MTVAL = 12'h343;
localparam [11:0] CSR_MIP = 12'h344;
localparam [11:0] CSR_PMPCFG0 = 12'h3A0;
localparam [11:0] CSR_PMPCFG1 = 12'h3A1;
localparam [11:0] CSR_PMPCFG2 = 12'h3A2;
localparam [11:0] CSR_PMPCFG3 = 12'h3A3;
localparam [11:0] CSR_PMPADDR0 = 12'h3B0;
localparam [11:0] CSR_PMPADDR1 = 12'h3B1;
localparam [11:0] CSR_PMPADDR2 = 12'h3B2;
localparam [11:0] CSR_PMPADDR3 = 12'h3B3;
localparam [11:0] CSR_PMPADDR4 = 12'h3B4;
localparam [11:0] CSR_PMPADDR5 = 12'h3B5;
localparam [11:0] CSR_PMPADDR6 = 12'h3B6;
localparam [11:0] CSR_PMPADDR7 = 12'h3B7;
localparam [11:0] CSR_PMPADDR8 = 12'h3B8;
localparam [11:0] CSR_PMPADDR9 = 12'h3B9;
localparam [11:0] CSR_PMPADDR10 = 12'h3BA;
localparam [11:0] CSR_PMPADDR11 = 12'h3BB;
localparam [11:0] CSR_PMPADDR12 = 12'h3BC;
localparam [11:0] CSR_PMPADDR13 = 12'h3BD;
localparam [11:0] CSR_PMPADDR14 = 12'h3BE;
localparam [11:0] CSR_PMPADDR15 = 12'h3BF;
localparam [11:0] CSR_TSELECT = 12'h7A0;
localparam [11:0] CSR_TDATA1 = 12'h7A1;
localparam [11:0] CSR_TDATA2 = 12'h7A2;
localparam [11:0] CSR_TDATA3 = 12'h7A3;
localparam [11:0] CSR_MCONTEXT = 12'h7A8;
localparam [11:0] CSR_SCONTEXT = 12'h7AA;
localparam [11:0] CSR_DCSR = 12'h7b0;
localparam [11:0] CSR_DPC = 12'h7b1;
localparam [11:0] CSR_DSCRATCH0 = 12'h7b2;
localparam [11:0] CSR_DSCRATCH1 = 12'h7b3;
localparam [11:0] CSR_MCYCLE = 12'hB00;
localparam [11:0] CSR_MINSTRET = 12'hB02;
localparam [11:0] CSR_MHPMCOUNTER3 = 12'hB03;
localparam [11:0] CSR_MHPMCOUNTER4 = 12'hB04;
localparam [11:0] CSR_MHPMCOUNTER5 = 12'hB05;
localparam [11:0] CSR_MHPMCOUNTER6 = 12'hB06;
localparam [11:0] CSR_MHPMCOUNTER7 = 12'hB07;
localparam [11:0] CSR_MHPMCOUNTER8 = 12'hB08;
localparam [11:0] CSR_MHPMCOUNTER9 = 12'hB09;
localparam [11:0] CSR_MHPMCOUNTER10 = 12'hB0A;
localparam [11:0] CSR_MHPMCOUNTER11 = 12'hB0B;
localparam [11:0] CSR_MHPMCOUNTER12 = 12'hB0C;
localparam [11:0] CSR_MHPMCOUNTER13 = 12'hB0D;
localparam [11:0] CSR_MHPMCOUNTER14 = 12'hB0E;
localparam [11:0] CSR_MHPMCOUNTER15 = 12'hB0F;
localparam [11:0] CSR_MHPMCOUNTER16 = 12'hB10;
localparam [11:0] CSR_MHPMCOUNTER17 = 12'hB11;
localparam [11:0] CSR_MHPMCOUNTER18 = 12'hB12;
localparam [11:0] CSR_MHPMCOUNTER19 = 12'hB13;
localparam [11:0] CSR_MHPMCOUNTER20 = 12'hB14;
localparam [11:0] CSR_MHPMCOUNTER21 = 12'hB15;
localparam [11:0] CSR_MHPMCOUNTER22 = 12'hB16;
localparam [11:0] CSR_MHPMCOUNTER23 = 12'hB17;
localparam [11:0] CSR_MHPMCOUNTER24 = 12'hB18;
localparam [11:0] CSR_MHPMCOUNTER25 = 12'hB19;
localparam [11:0] CSR_MHPMCOUNTER26 = 12'hB1A;
localparam [11:0] CSR_MHPMCOUNTER27 = 12'hB1B;
localparam [11:0] CSR_MHPMCOUNTER28 = 12'hB1C;
localparam [11:0] CSR_MHPMCOUNTER29 = 12'hB1D;
localparam [11:0] CSR_MHPMCOUNTER30 = 12'hB1E;
localparam [11:0] CSR_MHPMCOUNTER31 = 12'hB1F;
localparam [11:0] CSR_MCYCLEH = 12'hB80;
localparam [11:0] CSR_MINSTRETH = 12'hB82;
localparam [11:0] CSR_MHPMCOUNTER3H = 12'hB83;
localparam [11:0] CSR_MHPMCOUNTER4H = 12'hB84;
localparam [11:0] CSR_MHPMCOUNTER5H = 12'hB85;
localparam [11:0] CSR_MHPMCOUNTER6H = 12'hB86;
localparam [11:0] CSR_MHPMCOUNTER7H = 12'hB87;
localparam [11:0] CSR_MHPMCOUNTER8H = 12'hB88;
localparam [11:0] CSR_MHPMCOUNTER9H = 12'hB89;
localparam [11:0] CSR_MHPMCOUNTER10H = 12'hB8A;
localparam [11:0] CSR_MHPMCOUNTER11H = 12'hB8B;
localparam [11:0] CSR_MHPMCOUNTER12H = 12'hB8C;
localparam [11:0] CSR_MHPMCOUNTER13H = 12'hB8D;
localparam [11:0] CSR_MHPMCOUNTER14H = 12'hB8E;
localparam [11:0] CSR_MHPMCOUNTER15H = 12'hB8F;
localparam [11:0] CSR_MHPMCOUNTER16H = 12'hB90;
localparam [11:0] CSR_MHPMCOUNTER17H = 12'hB91;
localparam [11:0] CSR_MHPMCOUNTER18H = 12'hB92;
localparam [11:0] CSR_MHPMCOUNTER19H = 12'hB93;
localparam [11:0] CSR_MHPMCOUNTER20H = 12'hB94;
localparam [11:0] CSR_MHPMCOUNTER21H = 12'hB95;
localparam [11:0] CSR_MHPMCOUNTER22H = 12'hB96;
localparam [11:0] CSR_MHPMCOUNTER23H = 12'hB97;
localparam [11:0] CSR_MHPMCOUNTER24H = 12'hB98;
localparam [11:0] CSR_MHPMCOUNTER25H = 12'hB99;
localparam [11:0] CSR_MHPMCOUNTER26H = 12'hB9A;
localparam [11:0] CSR_MHPMCOUNTER27H = 12'hB9B;
localparam [11:0] CSR_MHPMCOUNTER28H = 12'hB9C;
localparam [11:0] CSR_MHPMCOUNTER29H = 12'hB9D;
localparam [11:0] CSR_MHPMCOUNTER30H = 12'hB9E;
localparam [11:0] CSR_MHPMCOUNTER31H = 12'hB9F;
localparam [11:0] CSR_MHARTID = 12'hF14;
localparam [4:0] ALU_NE = 13;
localparam [4:0] ALU_SLT = 14;
localparam [4:0] ALU_SLTU = 15;
localparam [1:0] CSR_OP_SET = 2;
localparam [1:0] EXC_PC_DBD = 2;
localparam [1:0] MD_OP_DIV = 2;
localparam [1:0] OP_A_CURRPC = 2;
localparam [1:0] RF_WD_CSR = 2;
localparam [2:0] IMM_B_B = 2;
localparam [2:0] PC_EXC = 2;
localparam [4:0] ALU_XOR = 2;
localparam [1:0] PMP_ACC_EXEC = 2'b00;
localparam [1:0] PMP_MODE_OFF = 2'b00;
localparam [1:0] PRIV_LVL_U = 2'b00;
localparam [1:0] PMP_ACC_WRITE = 2'b01;
localparam [1:0] PMP_MODE_TOR = 2'b01;
localparam [1:0] PRIV_LVL_S = 2'b01;
localparam [1:0] PMP_ACC_READ = 2'b10;
localparam [1:0] PMP_MODE_NA4 = 2'b10;
localparam [1:0] PRIV_LVL_H = 2'b10;
localparam [1:0] PMP_MODE_NAPOT = 2'b11;
localparam [1:0] PRIV_LVL_M = 2'b11;
localparam [1:0] CSR_OP_CLEAR = 3;
localparam [1:0] EXC_PC_DBG_EXC = 3;
localparam [1:0] MD_OP_REM = 3;
localparam [1:0] OP_A_IMM = 3;
localparam [2:0] IMM_B_U = 3;
localparam [2:0] PC_ERET = 3;
localparam [4:0] ALU_OR = 3;
localparam [2:0] DBG_CAUSE_NONE = 3'h0;
localparam [2:0] DBG_CAUSE_EBREAK = 3'h1;
localparam [2:0] DBG_CAUSE_TRIGGER = 3'h2;
localparam [2:0] DBG_CAUSE_HALTREQ = 3'h3;
localparam [2:0] DBG_CAUSE_STEP = 3'h4;
localparam [2:0] IMM_B_J = 4;
localparam [2:0] PC_DRET = 4;
localparam [4:0] ALU_AND = 4;
localparam [3:0] XDEBUGVER_NO = 4'd0;
localparam [3:0] XDEBUGVER_NONSTD = 4'd15;
localparam [3:0] XDEBUGVER_STD = 4'd4;
localparam [2:0] IMM_B_INCR_PC = 5;
localparam [4:0] ALU_SRA = 5;
localparam [2:0] IMM_B_INCR_ADDR = 6;
localparam [4:0] ALU_SRL = 6;
localparam [4:0] ALU_SLL = 7;
localparam [6:0] OPCODE_LOAD = 7'h03;
localparam [6:0] OPCODE_MISC_MEM = 7'h0f;
localparam [6:0] OPCODE_OP_IMM = 7'h13;
localparam [6:0] OPCODE_AUIPC = 7'h17;
localparam [6:0] OPCODE_STORE = 7'h23;
localparam [6:0] OPCODE_OP = 7'h33;
localparam [6:0] OPCODE_LUI = 7'h37;
localparam [6:0] OPCODE_BRANCH = 7'h63;
localparam [6:0] OPCODE_JALR = 7'h67;
localparam [6:0] OPCODE_JAL = 7'h6f;
localparam [6:0] OPCODE_SYSTEM = 7'h73;
localparam [4:0] ALU_LT = 8;
localparam [4:0] ALU_LTU = 9;
localparam [5:0] EXC_CAUSE_INSN_ADDR_MISA = {1'b0, 5'd00};
localparam [5:0] EXC_CAUSE_INSTR_ACCESS_FAULT = {1'b0, 5'd01};
localparam [5:0] EXC_CAUSE_ILLEGAL_INSN = {1'b0, 5'd02};
localparam [5:0] EXC_CAUSE_BREAKPOINT = {1'b0, 5'd03};
localparam [5:0] EXC_CAUSE_LOAD_ACCESS_FAULT = {1'b0, 5'd05};
localparam [5:0] EXC_CAUSE_STORE_ACCESS_FAULT = {1'b0, 5'd07};
localparam [5:0] EXC_CAUSE_ECALL_UMODE = {1'b0, 5'd08};
localparam [5:0] EXC_CAUSE_ECALL_MMODE = {1'b0, 5'd11};
localparam [5:0] EXC_CAUSE_IRQ_SOFTWARE_M = {1'b1, 5'd03};
localparam [5:0] EXC_CAUSE_IRQ_TIMER_M = {1'b1, 5'd07};
localparam [5:0] EXC_CAUSE_IRQ_EXTERNAL_M = {1'b1, 5'd11};
localparam [5:0] EXC_CAUSE_IRQ_NM = {1'b1, 5'd31};
wire illegal_insn_dec;
wire ebrk_insn;
wire mret_insn_dec;
wire dret_insn_dec;
wire ecall_insn_dec;
wire wfi_insn_dec;
wire branch_in_dec;
wire branch_set;
reg branch_set_d;
wire jump_in_dec;
wire jump_set;
wire instr_executing;
wire instr_multicycle;
reg instr_multicycle_done_n;
reg instr_multicycle_done_q;
reg stall_lsu;
reg stall_multdiv;
reg stall_branch;
reg stall_jump;
wire [31:0] imm_i_type;
wire [31:0] imm_s_type;
wire [31:0] imm_b_type;
wire [31:0] imm_u_type;
wire [31:0] imm_j_type;
wire [31:0] zimm_rs1_type;
wire [31:0] imm_a;
reg [31:0] imm_b;
wire [4:0] regfile_raddr_a;
wire [4:0] regfile_raddr_b;
wire [4:0] regfile_waddr;
wire [31:0] regfile_rdata_a;
wire [31:0] regfile_rdata_b;
reg [31:0] regfile_wdata;
wire [1:0] regfile_wdata_sel;
wire regfile_we;
reg regfile_we_wb;
wire regfile_we_dec;
wire [4:0] alu_operator;
wire [1:0] alu_op_a_mux_sel;
wire [1:0] alu_op_a_mux_sel_dec;
wire [0:0] alu_op_b_mux_sel;
wire [0:0] alu_op_b_mux_sel_dec;
wire [0:0] imm_a_mux_sel;
wire [2:0] imm_b_mux_sel;
wire [2:0] imm_b_mux_sel_dec;
wire mult_en_id;
wire mult_en_dec;
wire div_en_id;
wire div_en_dec;
wire multdiv_sel_dec;
wire multdiv_en_dec;
wire [1:0] multdiv_operator;
wire [1:0] multdiv_signed_mode;
wire data_we_id;
wire [1:0] data_type_id;
wire data_sign_ext_id;
wire data_req_id;
wire data_req_dec;
wire csr_pipe_flush;
reg [31:0] alu_operand_a;
wire [31:0] alu_operand_b;
assign alu_op_a_mux_sel = (lsu_addr_incr_req_i ? OP_A_FWD : alu_op_a_mux_sel_dec);
assign alu_op_b_mux_sel = (lsu_addr_incr_req_i ? OP_B_IMM : alu_op_b_mux_sel_dec);
assign imm_b_mux_sel = (lsu_addr_incr_req_i ? IMM_B_INCR_ADDR : imm_b_mux_sel_dec);
assign imm_a = ((imm_a_mux_sel == IMM_A_Z) ? zimm_rs1_type : 1'sb0);
always @(*) begin : alu_operand_a_mux
case (alu_op_a_mux_sel)
OP_A_REG_A: alu_operand_a = regfile_rdata_a;
OP_A_FWD: alu_operand_a = lsu_addr_last_i;
OP_A_CURRPC: alu_operand_a = pc_id_i;
OP_A_IMM: alu_operand_a = imm_a;
default: alu_operand_a = pc_id_i;
endcase
end
always @(*) begin : immediate_b_mux
case (imm_b_mux_sel)
IMM_B_I: imm_b = imm_i_type;
IMM_B_S: imm_b = imm_s_type;
IMM_B_B: imm_b = imm_b_type;
IMM_B_U: imm_b = imm_u_type;
IMM_B_J: imm_b = imm_j_type;
IMM_B_INCR_PC: imm_b = (instr_is_compressed_i ? 32'h2 : 32'h4);
IMM_B_INCR_ADDR: imm_b = 32'h4;
default: imm_b = 32'h4;
endcase
end
assign alu_operand_b = ((alu_op_b_mux_sel == OP_B_IMM) ? imm_b : regfile_rdata_b);
assign regfile_we = ((illegal_csr_insn_i || !instr_executing) ? 1'b0 : ((data_req_dec || multdiv_en_dec) ? regfile_we_wb : regfile_we_dec));
always @(*) begin : regfile_wdata_mux
case (regfile_wdata_sel)
RF_WD_EX: regfile_wdata = regfile_wdata_ex_i;
RF_WD_LSU: regfile_wdata = regfile_wdata_lsu_i;
RF_WD_CSR: regfile_wdata = csr_rdata_i;
default: regfile_wdata = regfile_wdata_ex_i;
endcase
end
ibex_register_file #(.RV32E(RV32E)) registers_i(
.clk_i(clk_i),
.rst_ni(rst_ni),
.test_en_i(test_en_i),
.raddr_a_i(regfile_raddr_a),
.rdata_a_o(regfile_rdata_a),
.raddr_b_i(regfile_raddr_b),
.rdata_b_o(regfile_rdata_b),
.waddr_a_i(regfile_waddr),
.wdata_a_i(regfile_wdata),
.we_a_i(regfile_we)
);
ibex_decoder #(
.RV32E(RV32E),
.RV32M(RV32M),
.BranchTargetALU(BranchTargetALU)
) decoder_i(
.clk_i(clk_i),
.rst_ni(rst_ni),
.illegal_insn_o(illegal_insn_dec),
.ebrk_insn_o(ebrk_insn),
.mret_insn_o(mret_insn_dec),
.dret_insn_o(dret_insn_dec),
.ecall_insn_o(ecall_insn_dec),
.wfi_insn_o(wfi_insn_dec),
.jump_set_o(jump_set),
.instr_new_i(instr_new_i),
.instr_rdata_i(instr_rdata_i),
.instr_rdata_alu_i(instr_rdata_alu_i),
.illegal_c_insn_i(illegal_c_insn_i),
.imm_a_mux_sel_o(imm_a_mux_sel),
.imm_b_mux_sel_o(imm_b_mux_sel_dec),
.jt_mux_sel_o(jt_mux_sel_ex_o),
.imm_i_type_o(imm_i_type),
.imm_s_type_o(imm_s_type),
.imm_b_type_o(imm_b_type),
.imm_u_type_o(imm_u_type),
.imm_j_type_o(imm_j_type),
.zimm_rs1_type_o(zimm_rs1_type),
.regfile_wdata_sel_o(regfile_wdata_sel),
.regfile_we_o(regfile_we_dec),
.regfile_raddr_a_o(regfile_raddr_a),
.regfile_raddr_b_o(regfile_raddr_b),
.regfile_waddr_o(regfile_waddr),
.alu_operator_o(alu_operator),
.alu_op_a_mux_sel_o(alu_op_a_mux_sel_dec),
.alu_op_b_mux_sel_o(alu_op_b_mux_sel_dec),
.mult_en_o(mult_en_dec),
.div_en_o(div_en_dec),
.multdiv_sel_o(multdiv_sel_dec),
.multdiv_operator_o(multdiv_operator),
.multdiv_signed_mode_o(multdiv_signed_mode),
.csr_access_o(csr_access_o),
.csr_op_o(csr_op_o),
.csr_pipe_flush_o(csr_pipe_flush),
.data_req_o(data_req_dec),
.data_we_o(data_we_id),
.data_type_o(data_type_id),
.data_sign_extension_o(data_sign_ext_id),
.jump_in_dec_o(jump_in_dec),
.branch_in_dec_o(branch_in_dec)
);
assign illegal_insn_o = (instr_valid_i & (illegal_insn_dec | illegal_csr_insn_i));
ibex_controller controller_i(
.clk_i(clk_i),
.rst_ni(rst_ni),
.fetch_enable_i(fetch_enable_i),
.ctrl_busy_o(ctrl_busy_o),
.illegal_insn_i(illegal_insn_o),
.ecall_insn_i(ecall_insn_dec),
.mret_insn_i(mret_insn_dec),
.dret_insn_i(dret_insn_dec),
.wfi_insn_i(wfi_insn_dec),
.ebrk_insn_i(ebrk_insn),
.csr_pipe_flush_i(csr_pipe_flush),
.instr_valid_i(instr_valid_i),
.instr_i(instr_rdata_i),
.instr_compressed_i(instr_rdata_c_i),
.instr_is_compressed_i(instr_is_compressed_i),
.instr_fetch_err_i(instr_fetch_err_i),
.pc_id_i(pc_id_i),
.instr_valid_clear_o(instr_valid_clear_o),
.id_in_ready_o(id_in_ready_o),
.instr_req_o(instr_req_o),
.pc_set_o(pc_set_o),
.pc_mux_o(pc_mux_o),
.exc_pc_mux_o(exc_pc_mux_o),
.exc_cause_o(exc_cause_o),
.lsu_addr_last_i(lsu_addr_last_i),
.load_err_i(lsu_load_err_i),
.store_err_i(lsu_store_err_i),
.branch_set_i(branch_set),
.jump_set_i(jump_set),
.csr_mstatus_mie_i(csr_mstatus_mie_i),
.irq_pending_i(irq_pending_i),
.irqs_i(irqs_i),
.irq_nm_i(irq_nm_i),
.nmi_mode_o(nmi_mode_o),
.csr_save_if_o(csr_save_if_o),
.csr_save_id_o(csr_save_id_o),
.csr_restore_mret_id_o(csr_restore_mret_id_o),
.csr_restore_dret_id_o(csr_restore_dret_id_o),
.csr_save_cause_o(csr_save_cause_o),
.csr_mtval_o(csr_mtval_o),
.priv_mode_i(priv_mode_i),
.csr_mstatus_tw_i(csr_mstatus_tw_i),
.debug_mode_o(debug_mode_o),
.debug_cause_o(debug_cause_o),
.debug_csr_save_o(debug_csr_save_o),
.debug_req_i(debug_req_i),
.debug_single_step_i(debug_single_step_i),
.debug_ebreakm_i(debug_ebreakm_i),
.debug_ebreaku_i(debug_ebreaku_i),
.trigger_match_i(trigger_match_i),
.stall_lsu_i(stall_lsu),
.stall_multdiv_i(stall_multdiv),
.stall_jump_i(stall_jump),
.stall_branch_i(stall_branch),
.perf_jump_o(perf_jump_o),
.perf_tbranch_o(perf_tbranch_o)
);
assign multdiv_en_dec = (mult_en_dec | div_en_dec);
assign instr_multicycle = (((data_req_dec | multdiv_en_dec) | branch_in_dec) | jump_in_dec);
assign instr_executing = ((instr_new_i | (instr_multicycle & ~instr_multicycle_done_q)) & ~instr_fetch_err_i);
assign data_req_id = (instr_executing ? data_req_dec : 1'b0);
assign mult_en_id = (instr_executing ? mult_en_dec : 1'b0);
assign div_en_id = (instr_executing ? div_en_dec : 1'b0);
assign data_req_ex_o = data_req_id;
assign data_we_ex_o = data_we_id;
assign data_type_ex_o = data_type_id;
assign data_sign_ext_ex_o = data_sign_ext_id;
assign data_wdata_ex_o = regfile_rdata_b;
assign alu_operator_ex_o = alu_operator;
assign alu_operand_a_ex_o = alu_operand_a;
assign alu_operand_b_ex_o = alu_operand_b;
generate
if (BranchTargetALU) begin : g_bt_operand_imm
assign bt_operand_imm_o = imm_b_type[12:1];
end
else begin : g_no_bt_operand_imm
assign bt_operand_imm_o = 1'sb0;
end
endgenerate
assign mult_en_ex_o = mult_en_id;
assign div_en_ex_o = div_en_id;
assign multdiv_sel_ex_o = multdiv_sel_dec;
assign multdiv_operator_ex_o = multdiv_operator;
assign multdiv_signed_mode_ex_o = multdiv_signed_mode;
assign multdiv_operand_a_ex_o = regfile_rdata_a;
assign multdiv_operand_b_ex_o = regfile_rdata_b;
reg [0:0] id_wb_fsm_cs;
reg [0:0] id_wb_fsm_ns;
generate
if (BranchTargetALU) begin : g_branch_set_direct
assign branch_set = branch_set_d;
end
else begin : g_branch_set_flopped
reg branch_set_q;
always @(posedge clk_i or negedge rst_ni)
if (!rst_ni)
branch_set_q <= 1'b0;
else
branch_set_q <= branch_set_d;
assign branch_set = branch_set_q;
end
endgenerate
always @(posedge clk_i or negedge rst_ni) begin : id_wb_pipeline_reg
if (!rst_ni) begin
id_wb_fsm_cs <= IDLE;
instr_multicycle_done_q <= 1'b0;
end
else begin
id_wb_fsm_cs <= id_wb_fsm_ns;
instr_multicycle_done_q <= instr_multicycle_done_n;
end
end
always @(*) begin : id_wb_fsm
id_wb_fsm_ns = id_wb_fsm_cs;
instr_multicycle_done_n = instr_multicycle_done_q;
regfile_we_wb = 1'b0;
stall_lsu = 1'b0;
stall_multdiv = 1'b0;
stall_jump = 1'b0;
stall_branch = 1'b0;
branch_set_d = 1'b0;
perf_branch_o = 1'b0;
instr_ret_o = 1'b0;
case (id_wb_fsm_cs)
IDLE:
if ((instr_new_i & ~instr_fetch_err_i))
case (1'b1)
data_req_dec: begin
id_wb_fsm_ns = WAIT_MULTICYCLE;
stall_lsu = 1'b1;
instr_multicycle_done_n = 1'b0;
end
multdiv_en_dec: begin
id_wb_fsm_ns = WAIT_MULTICYCLE;
stall_multdiv = 1'b1;
instr_multicycle_done_n = 1'b0;
end
branch_in_dec: begin
id_wb_fsm_ns = (branch_decision_i ? WAIT_MULTICYCLE : IDLE);
stall_branch = branch_decision_i;
instr_multicycle_done_n = ~branch_decision_i;
branch_set_d = branch_decision_i;
perf_branch_o = 1'b1;
instr_ret_o = ~branch_decision_i;
end
jump_in_dec: begin
id_wb_fsm_ns = WAIT_MULTICYCLE;
stall_jump = 1'b1;
instr_multicycle_done_n = 1'b0;
end
default: begin
instr_multicycle_done_n = 1'b0;
instr_ret_o = 1'b1;
end
endcase
WAIT_MULTICYCLE:
if (((data_req_dec & lsu_valid_i) | (~data_req_dec & ex_valid_i))) begin
id_wb_fsm_ns = IDLE;
instr_multicycle_done_n = 1'b1;
regfile_we_wb = (regfile_we_dec & ~lsu_load_err_i);
instr_ret_o = 1'b1;
end
else begin
stall_lsu = data_req_dec;
stall_multdiv = multdiv_en_dec;
stall_branch = branch_in_dec;
stall_jump = jump_in_dec;
end
default: id_wb_fsm_ns = IDLE;
endcase
end
assign instr_ret_compressed_o = (instr_ret_o & instr_is_compressed_i);
endmodule
|
module Processor(input clock,
input clear);
// PC register
wire[31:0] pc_in;
wire[31:0] pc_out;
PcRegister pc_register(
clock,
clear,
pc_in,
pc_out);
// Instruction memory
wire[31:0] instruction_memory_address;
wire[31:0] instruction_memory_instr;
InstructionMemory instruction_memory(
clock,
clear,
instruction_memory_address,
instruction_memory_instr);
// Connections for instruction memory
assign instruction_memory_address = pc_out;
// Adder4
wire[31:0] adder4_in;
wire[31:0] adder4_out;
Adder4 adder4(adder4_in,
adder4_out);
// Connections for Adder4
assign adder4_in = pc_out;
// PC MUX
wire[31:0] pc_mux_in0;
wire[31:0] pc_mux_in1;
wire[31:0] pc_mux_out;
wire pc_mux_sel;
Mux32Bit2To1 pc_mux(pc_mux_in0,
pc_mux_in1,
pc_mux_sel,
pc_mux_out);
// Connections for PC MUX
assign pc_in = pc_mux_out;
assign pc_mux_in0 = adder4_out;
// Register file MUX
wire[4:0] register_file_mux_in0;
wire[4:0] register_file_mux_in1;
wire[4:0] register_file_mux_out;
wire register_file_mux_sel;
Mux5Bit2To1 register_file_mux(
register_file_mux_in0,
register_file_mux_in1,
register_file_mux_sel,
register_file_mux_out);
// Connections for register file MUX
assign register_file_mux_in0 = instruction_memory_instr[20:16];
assign register_file_mux_in1 = instruction_memory_instr[15:11];
// Register file
wire[4:0] register_file_read_index1;
wire[31:0] register_file_read_data1;
wire[4:0] register_file_read_index2;
wire[31:0] register_file_read_data2;
wire register_file_write;
wire[4:0] register_file_write_index;
wire[31:0] register_file_write_data;
RegisterFile register_file(
clock,
clear,
register_file_read_index1,
register_file_read_data1,
register_file_read_index2,
register_file_read_data2,
register_file_write,
register_file_write_index,
register_file_write_data);
// Connections for register file
assign register_file_read_index1 = instruction_memory_instr[25:21];
assign register_file_read_index2 = instruction_memory_instr[20:16];
assign register_file_write_index = register_file_mux_out;
// ALU MUX
wire[31:0] alu_mux_in0;
wire[31:0] alu_mux_in1;
wire[31:0] alu_mux_out;
wire alu_mux_sel;
Mux32Bit2To1 alu_mux(
alu_mux_in0,
alu_mux_in1,
alu_mux_sel,
alu_mux_out);
// Connections for ALU MUX
assign alu_mux_in0 = register_file_read_data2;
// ALU
wire[31:0] alu_op1;
wire[31:0] alu_op2;
wire[2:0] alu_f;
wire[31:0] alu_result;
wire alu_zero;
Alu alu(alu_op1,
alu_op2,
alu_f,
alu_result,
alu_zero);
// Connections for ALU
assign alu_op1 = register_file_read_data1;
assign alu_op2 = alu_mux_out;
// Data memory
wire[31:0] data_memory_address;
wire data_memory_write;
wire[31:0] data_memory_write_data;
wire[31:0] data_memory_read_data;
DataMemory data_memory(
clock,
clear,
data_memory_address,
data_memory_write,
data_memory_write_data,
data_memory_read_data);
// Connections for data memory
assign data_memory_address = alu_result;
assign data_memory_write_data = register_file_read_data2;
// Data memory MUX
wire[31:0] data_memory_mux_in0;
wire[31:0] data_memory_mux_in1;
wire data_memory_mux_sel;
wire[31:0] data_memory_mux_out;
Mux32Bit2To1 data_memory_mux(
data_memory_mux_in0,
data_memory_mux_in1,
data_memory_mux_sel,
data_memory_mux_out);
// Connections for data memory MUX
assign data_memory_mux_in0 = alu_result;
assign data_memory_mux_in1 = data_memory_read_data;
assign register_file_write_data = data_memory_mux_out;
// SignExtend
wire[15:0] sign_extend_in;
wire[31:0] sign_extend_out;
SignExtend sign_extend(
sign_extend_in,
sign_extend_out);
// Connections for SignExtend
assign sign_extend_in = instruction_memory_instr[15:0];
assign alu_mux_in1 = sign_extend_out;
// ShiftLeft
wire[31:0] shift_left_in;
wire[31:0] shift_left_out;
ShiftLeft shift_left(
shift_left_in,
shift_left_out);
// Connections for ShiftLeft
assign shift_left_in = sign_extend_out;
// Adder
wire[31:0] adder_op1;
wire[31:0] adder_op2;
wire[31:0] adder_result;
Adder adder(adder_op1,
adder_op2,
adder_result);
// Connections for adder
assign adder_op1 = shift_left_out;
assign adder_op2 = adder4_out;
assign pc_mux_in1 = adder_result;
// And gate
wire and_gate_in1;
wire and_gate_in2;
wire and_gate_out;
and and_gate(and_gate_out,
and_gate_in1,
and_gate_in2);
// Connections for and gate
assign and_gate_in2 = alu_zero;
assign pc_mux_sel = and_gate_out;
// Control unit
wire[5:0] control_unit_opcode;
wire[5:0] control_unit_funct;
wire control_unit_reg_dst;
wire control_unit_reg_write;
wire control_unit_alu_src;
wire[2:0] control_unit_alu_op;
wire control_unit_branch;
wire control_unit_mem_write;
wire control_unit_mem_to_reg;
ControlUnit control_unit(
control_unit_opcode,
control_unit_funct,
control_unit_reg_dst,
control_unit_reg_write,
control_unit_alu_src,
control_unit_alu_op,
control_unit_branch,
control_unit_mem_write,
control_unit_mem_to_reg);
// Connections for control unit
assign control_unit_opcode = instruction_memory_instr[31:26];
assign control_unit_funct = instruction_memory_instr[5:0];
assign register_file_mux_sel = control_unit_reg_dst;
assign register_file_write = control_unit_reg_write;
assign alu_mux_sel = control_unit_alu_src;
assign alu_f = control_unit_alu_op;
assign and_gate_in1 = control_unit_branch;
assign data_memory_write = control_unit_mem_write;
assign data_memory_mux_sel = control_unit_mem_to_reg;
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: cpx_datacx2_ff.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
`include "sys.h" // system level definition file which contains the
// time scale definition
`include "iop.h"
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
module cpx_datacx2_ff(/*AUTOARG*/
// Outputs
cpx_spc_data_cx2, cpx_spc_data_rdy_cx2, so,
// Inputs
cpx_spc_data_cx_l, cpx_spc_data_rdy_cx, rclk, si, se
);
output [`CPX_WIDTH-1:0] cpx_spc_data_cx2;
output cpx_spc_data_rdy_cx2;
output so;
input [`CPX_WIDTH-1:0] cpx_spc_data_cx_l;
input cpx_spc_data_rdy_cx;
input rclk;
input si;
input se;
wire [`CPX_WIDTH-1:0] cpx_spc_data_cx2_l;
dff_s #(`CPX_WIDTH) dff_ccx_data_spc(
.din (cpx_spc_data_cx_l[`CPX_WIDTH-1:0]),
.q (cpx_spc_data_cx2_l[`CPX_WIDTH-1:0]),
.clk (rclk),
.se (1'b0),
.si (`CPX_WIDTH'd0),
.so ());
assign cpx_spc_data_cx2 = ~cpx_spc_data_cx2_l;
dff_s #(1) dff_ccx_datardy_spc(
.din (cpx_spc_data_rdy_cx),
.q (cpx_spc_data_rdy_cx2),
.clk (rclk),
.se (1'b0),
.si (1'd0),
.so ());
endmodule // cpx_grant_ff
|
// file: atom_clocks.v
//
// (c) Copyright 2008 - 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// CLK_OUT1 32.000 0.000 50.0 281.657 187.995
// CLK_OUT2 25.000 0.000 50.0 296.005 187.995
// CLK_OUT3 16.000 0.000 50.0 323.291 187.995
//
//----------------------------------------------------------------------------
// Input Clock Input Freq (MHz) Input Jitter (UI)
//----------------------------------------------------------------------------
// primary 50.000 0.010
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "atom_clocks,clk_wiz_v1_8,{component_name=atom_clocks,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=PLL_BASE,num_out_clk=3,clkin1_period=20.0,clkin2_period=20.0,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}" *)
module atom_clocks
(// Clock in ports
input CLK_IN1,
// Clock out ports
output CLK_OUT1,
output CLK_OUT2,
output CLK_OUT3
);
// Input buffering
//------------------------------------
IBUFG clkin1_buf
(.O (clkin1),
.I (CLK_IN1));
// Clocking primitive
//------------------------------------
// Instantiation of the PLL primitive
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire [15:0] do_unused;
wire drdy_unused;
wire locked_unused;
wire clkfbout;
wire clkfbout_buf;
wire clkout3_unused;
wire clkout4_unused;
wire clkout5_unused;
PLL_BASE
#(.BANDWIDTH ("OPTIMIZED"),
.CLK_FEEDBACK ("CLKFBOUT"),
.COMPENSATION ("SYSTEM_SYNCHRONOUS"),
.DIVCLK_DIVIDE (1),
.CLKFBOUT_MULT (16),
.CLKFBOUT_PHASE (0.000),
.CLKOUT0_DIVIDE (25),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT1_DIVIDE (32),
.CLKOUT1_PHASE (0.000),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKOUT2_DIVIDE (50),
.CLKOUT2_PHASE (0.000),
.CLKOUT2_DUTY_CYCLE (0.500),
.CLKIN_PERIOD (20.0),
.REF_JITTER (0.010))
pll_base_inst
// Output clocks
(.CLKFBOUT (clkfbout),
.CLKOUT0 (clkout0),
.CLKOUT1 (clkout1),
.CLKOUT2 (clkout2),
.CLKOUT3 (clkout3_unused),
.CLKOUT4 (clkout4_unused),
.CLKOUT5 (clkout5_unused),
.LOCKED (locked_unused),
.RST (1'b0),
// Input clock control
.CLKFBIN (clkfbout_buf),
.CLKIN (clkin1));
// Output buffering
//-----------------------------------
BUFG clkf_buf
(.O (clkfbout_buf),
.I (clkfbout));
BUFG clkout1_buf
(.O (CLK_OUT1),
.I (clkout0));
BUFG clkout2_buf
(.O (CLK_OUT2),
.I (clkout1));
BUFG clkout3_buf
(.O (CLK_OUT3),
.I (clkout2));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NOR4B_TB_V
`define SKY130_FD_SC_LS__NOR4B_TB_V
/**
* nor4b: 4-input NOR, first input inverted.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__nor4b.v"
module top();
// Inputs are registered
reg A;
reg B;
reg C;
reg D_N;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C = 1'bX;
D_N = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 D_N = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A = 1'b1;
#200 B = 1'b1;
#220 C = 1'b1;
#240 D_N = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A = 1'b0;
#360 B = 1'b0;
#380 C = 1'b0;
#400 D_N = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 D_N = 1'b1;
#600 C = 1'b1;
#620 B = 1'b1;
#640 A = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 D_N = 1'bx;
#760 C = 1'bx;
#780 B = 1'bx;
#800 A = 1'bx;
end
sky130_fd_sc_ls__nor4b dut (.A(A), .B(B), .C(C), .D_N(D_N), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__NOR4B_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__BUF_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__BUF_PP_BLACKBOX_V
/**
* buf: Buffer.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__buf (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__BUF_PP_BLACKBOX_V
|
// Copyright (c) 2000-2009 Bluespec, Inc.
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision: 24080 $
// $Date: 2011-05-18 19:32:52 +0000 (Wed, 18 May 2011) $
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
module RWire(WGET, WHAS, WVAL, WSET);
parameter width = 1;
input [width - 1 : 0] WVAL;
input WSET;
output [width - 1 : 0] WGET;
output WHAS;
assign WGET = WVAL;
assign WHAS = WSET;
endmodule
|
/*
* I2S shift in function. Data interface is a FIFO. FIFO is assumed to be dual-clock.
* There will be no writes if not enabled.
* New values will be written to FIFO only when fifo_ready. If enabled, but not ready,
* the last data sample will be dropped.
*/
module i2s_shift_in (
input clk, // Master clock, should be synchronous with bclk/lrclk
input reset_n, // Asynchronous reset
output reg [31:0] fifo_right_data, // Fifo interface, right channel
output reg [31:0] fifo_left_data, // Fifo interface, left channel
input fifo_ready, // Fifo ready (not full)
output reg fifo_write, // Fifo write strobe, write only when l+r received
input enable, // Software enable
input bclk, // I2S bclk
input lrclk, // I2S lrclk (word clock)
input data_in // Data in from ADC
);
// bclk edge
reg bclk_delayed;
always @(posedge clk or negedge reset_n)
begin
if (~reset_n)
begin
bclk_delayed <= 0;
end
else
begin
bclk_delayed <= bclk;
end
end
wire bclk_rising_edge = bclk & ~bclk_delayed;
wire bclk_falling_edge = ~bclk & bclk_delayed;
// lrclk edges
reg lrclk_delayed;
always @(posedge clk or negedge reset_n)
begin
if (~reset_n)
begin
lrclk_delayed <= 0;
end
else
begin
lrclk_delayed <= lrclk;
end
end
wire lrclk_rising_edge = lrclk & ~lrclk_delayed;
wire lrclk_falling_edge = ~lrclk & lrclk_delayed;
// I2S is one bclk delayed, so detect falling egde of first (complete) bclk after each lrclk edge
reg [1:0] first_bclk_falling_after_lrclk_rising_r;
always @(posedge clk or negedge reset_n)
begin
if (~reset_n)
begin
first_bclk_falling_after_lrclk_rising_r <= 0;
end
else
begin
if (lrclk_rising_edge)
first_bclk_falling_after_lrclk_rising_r <= 2'b01;
else if (first_bclk_falling_after_lrclk_rising_r == 2'b01 && bclk_rising_edge)
first_bclk_falling_after_lrclk_rising_r <= 2'b10;
else if (first_bclk_falling_after_lrclk_rising_r == 2'b10 && bclk_falling_edge)
first_bclk_falling_after_lrclk_rising_r <= 2'b11;
else if (first_bclk_falling_after_lrclk_rising_r == 2'b11)
first_bclk_falling_after_lrclk_rising_r <= 2'b00;
end
end
wire first_bclk_falling_after_lrclk_rising = first_bclk_falling_after_lrclk_rising_r == 2'b11;
reg [1:0] first_bclk_falling_after_lrclk_falling_r;
always @(posedge clk or negedge reset_n)
begin
if (~reset_n)
begin
first_bclk_falling_after_lrclk_falling_r <= 0;
end
else
begin
if (lrclk_falling_edge)
first_bclk_falling_after_lrclk_falling_r <= 2'b01;
else if (first_bclk_falling_after_lrclk_falling_r == 2'b01 && bclk_rising_edge)
first_bclk_falling_after_lrclk_falling_r <= 2'b10;
else if (first_bclk_falling_after_lrclk_falling_r == 2'b10 && bclk_falling_edge)
first_bclk_falling_after_lrclk_falling_r <= 2'b11;
else if (first_bclk_falling_after_lrclk_falling_r == 2'b11)
first_bclk_falling_after_lrclk_falling_r <= 2'b00;
end
end
wire first_bclk_falling_after_lrclk_falling = first_bclk_falling_after_lrclk_falling_r == 2'b11;
// shift-register
reg [31:0] shift_register;
always @(posedge clk or negedge reset_n)
begin
if (~reset_n)
begin
shift_register <= 0;
end
else
begin
if (~enable)
shift_register <= 0;
else if (bclk_rising_edge)
shift_register <= {shift_register[30:0], data_in};
end
end
// Load output register
always @(posedge clk or negedge reset_n)
begin
if (~reset_n)
begin
fifo_right_data <= 0;
fifo_left_data <= 0;
end
else
begin
if (~enable)
begin
fifo_right_data <= 0;
fifo_left_data <= 0;
end
else if (first_bclk_falling_after_lrclk_rising)
fifo_left_data <= shift_register;
else if (first_bclk_falling_after_lrclk_falling)
fifo_right_data <= shift_register;
end
end
// fifo write strobe, one clock after right channel has been loaded to output register
always @(posedge clk or negedge reset_n)
begin
if (~reset_n)
begin
fifo_write <= 0;
end
else
begin
if (~enable | ~fifo_ready)
fifo_write <= 0;
else
fifo_write <= first_bclk_falling_after_lrclk_falling;
end
end
endmodule
|
`timescale 1 ns / 1 ps
module intermediator(
input reset,
input clk,
input valid0,
input [63:0] value0,
input [9:0] row0,
input valid1,
input [63:0] value1,
input [9:0] row1,
output store,
output [63:0] store_value,
output add,
output [63:0] add0,
output [63:0] add1,
output [9:0] add_row,
input flush
);
reg [2:0] ctl0_stg0, ctl0_stg1, ctl0_stg2, ctl0_stg3, ctl0_stg4;
reg [2:0] ctl1_stg0, ctl1_stg1, ctl1_stg2, ctl1_stg3, ctl1_stg4;
reg ctl_com_stg0, ctl_com_stg1, ctl_com_stg2, ctl_com_stg3, ctl_com_stg4;
reg [63:0] value0_stg0, value0_stg1, value0_stg2, value0_stg3, value0_stg4;
reg [9:0] row0_stg0, row0_stg1, row0_stg2, row0_stg3, row0_stg4;
reg [63:0] value1_stg0, value1_stg1, value1_stg2, value1_stg3, value1_stg4;
reg [9:0] row1_stg0, row1_stg1, row1_stg2, row1_stg3, row1_stg4;
reg [9:0] lur, har;
reg [31:0] waiter;
reg [1:0] waiter_state;
`define IDLE 0
`define START 1
`define STEADY 2
`define FINISH 3
reg store_ready;
reg r_store;
reg [63:0] r_store_value;
reg r_add;
reg [63:0] r_add0;
reg [63:0] r_add1;
reg [63:0] r_add_row;
wire [63:0] ram_value0, ram_value1;
//OPTIONAL: reduce latency by getting values later.
always @(posedge clk) begin
if(reset) begin
ctl0_stg0 <= 0;
ctl1_stg0 <= 0;
ctl_com_stg0 <= 0;
end else begin
ctl0_stg0 <= {2'H0, valid0};
ctl1_stg0 <= {2'H0, valid1};
ctl_com_stg0 <= 0;
end
value0_stg0 <= value0;
row0_stg0 <= row0;
value1_stg0 <= value1;
row1_stg0 <= row1;
end
always @(posedge clk) begin
ctl0_stg1 <= ctl0_stg0;
ctl1_stg1 <= ctl1_stg0;
ctl_com_stg1 <= (row1_stg0 == row0_stg0) && ctl0_stg0[0] && ctl1_stg0[0];
value0_stg1 <= value0_stg0;
row0_stg1 <= row0_stg0;
value1_stg1 <= value1_stg0;
row1_stg1 <= row1_stg0;
end
always @(posedge clk) begin
ctl0_stg2 <= ctl0_stg1;
ctl1_stg2 <= ctl1_stg1;
if(ctl_com_stg1) begin
ctl0_stg2[1:0] <= 0;
ctl1_stg2[1:0] <= 0;
end
ctl_com_stg2 <= ctl_com_stg1;
value0_stg2 <= value0_stg1;
row0_stg2 <= row0_stg1;
value1_stg2 <= value1_stg1;
row1_stg2 <= row1_stg1;
if(store_ready) begin
if(!(ctl0_stg1[0])) begin
ctl0_stg2[2] <= 1;
row0_stg2 <= lur;
end else if(!ctl1_stg1[0]) begin
ctl1_stg2[2] <= 1;
row1_stg2 <= lur;
end
end
end
//TODO: add state: IDLE, Start, Steady, Finish
//waiter logic
always @(posedge clk) begin
if(reset) begin
lur <= 0;
har <= 0;
waiter <= 0;
waiter_state <= `IDLE;
store_ready <= 0;
end else begin
store_ready <= 0;
har <= {row0_stg0[9:4] + 1, 4'H0};
if(har[4] == row0_stg0[4]) begin
if(har[4])
waiter[31:16] <= 0;
else
waiter[15:0] <= 0;
end
case(waiter_state)
`IDLE: begin
if(ctl0_stg0[0]) begin
waiter_state <= `START;
lur <= {row0_stg0[9:4], 4'H0};
end
waiter <= 0;
end
`START: begin
if(lur[9:4] + 6'H3 == har[9:4])
waiter_state <= `STEADY;
if(flush)
waiter_state <= `FINISH;
end
`STEADY: begin
if(lur[9:4] + 6'H3 != har[9:4])begin
store_ready <= 1;
end
if(flush)
waiter_state <= `FINISH;
end
`FINISH: begin
store_ready <= 1;
if(lur == har)
waiter_state <= `IDLE;
end
endcase
if((!ctl0_stg1[0] || !ctl1_stg1[0]) && store_ready)
lur <= lur + 1;
if(ctl0_stg2[0]) begin
waiter[row0_stg2[4:0]] <= ~waiter[row0_stg2[4:0]];
end
if(ctl1_stg2[0])
waiter[row1_stg2[4:0]] <= ~waiter[row1_stg2[4:0]];
end
end
wire occupied0, occupied1;
assign occupied0 = waiter[row0_stg2[4:0]];
assign occupied1 = waiter[row1_stg2[4:0]];
always @(posedge clk) begin
ctl0_stg3 <= ctl0_stg2;
ctl1_stg3 <= ctl1_stg2;
ctl0_stg3[1] <= ctl0_stg2[0] && !occupied0;
ctl1_stg3[1] <= ctl1_stg2[0] && !occupied1;
ctl_com_stg3 <= ctl_com_stg2;
value0_stg3 <= value0_stg2;
row0_stg3 <= row0_stg2;
value1_stg3 <= value1_stg2;
row1_stg3 <= row1_stg2;
end
block_ram_64x1024 ram(
.clka(clk),
.wea(ctl0_stg3[1]),
.addra(row0_stg3),
.dina(value0_stg3),
.douta(ram_value0),
.clkb(clk),
.web(ctl1_stg3[1]),
.addrb(row1_stg3),
.dinb(value1_stg3),
.doutb(ram_value1));
always @(posedge clk) begin
ctl0_stg4 <= ctl0_stg3;
ctl1_stg4 <= ctl1_stg3;
ctl_com_stg4 <= ctl_com_stg3;
value0_stg4 <= value0_stg3;
row0_stg4 <= row0_stg3;
value1_stg4 <= value1_stg3;
row1_stg4 <= row1_stg3;
end
wire overflow_fifo_rd;
reg overflow_fifo_rd1;
wire overflow_fifo_empty, overflow_fifo_full;
wire [9:0] overflow_fifo_row;
wire [63:0] overflow_fifo_value0;
wire [63:0] overflow_fifo_value1;
assign overflow_fifo_rd = (ctl0_stg3[1:0] != 2'H1) && !ctl_com_stg3 && !overflow_fifo_empty;
always @(posedge clk) begin
overflow_fifo_rd1 <= overflow_fifo_rd;
end
fifo_138x16_shift overflow_fifo(
.clk(clk),
.srst(reset),
.din({row1_stg4, value1_stg4, ram_value1}),
.wr_en((ctl1_stg4[1:0] == 2'H1)),
.rd_en(overflow_fifo_rd),
.dout({overflow_fifo_row, overflow_fifo_value0, overflow_fifo_value1}),
.full(overflow_fifo_full),
.empty(overflow_fifo_empty));
always @(posedge clk) begin
r_add <= 0;
r_add0 <= 0;
r_add1 <= 0;
r_add_row <= 0;
if(ctl_com_stg4) begin
r_add <= 1;
r_add0 <= value0_stg4;
r_add1 <= value1_stg4;
r_add_row <= row0_stg4;
end else if(ctl0_stg4[1:0] == 2'H1) begin
r_add <= 1;
r_add0 <= value0_stg4;
r_add1 <= ram_value0;
r_add_row <= row0_stg4;
end else if(overflow_fifo_rd1) begin
r_add <= 1;
r_add0 <= overflow_fifo_value0;
r_add1 <= overflow_fifo_value1;
r_add_row <= overflow_fifo_row;
end
end
assign add = r_add;
assign add0 = r_add0;
assign add1 = r_add1;
assign add_row = r_add_row;
always @(posedge clk) begin
r_store <= 0;
r_store_value <= 0;
if(reset)
r_store <= 0;
if(ctl0_stg4[2]) begin
r_store <= 1;
r_store_value <= ram_value0;
end else if(ctl1_stg4[2]) begin
r_store <= 1;
r_store_value <= ram_value1;
end
end
assign store = r_store;
assign store_value = r_store_value;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_DLATCH_PR_PP_PKG_S_BLACKBOX_V
`define SKY130_FD_SC_HS__UDP_DLATCH_PR_PP_PKG_S_BLACKBOX_V
/**
* udp_dlatch$PR_pp$PKG$s: D-latch, gated clear direct / gate active
* high (Q output UDP)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__udp_dlatch$PR_pp$PKG$s (
Q ,
D ,
GATE ,
RESET ,
SLEEP_B,
KAPWR ,
VGND ,
VPWR
);
output Q ;
input D ;
input GATE ;
input RESET ;
input SLEEP_B;
input KAPWR ;
input VGND ;
input VPWR ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_DLATCH_PR_PP_PKG_S_BLACKBOX_V
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: sparc_ffu_dp.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
///////////////////////////////////////////////////////////////////////
/*
// Module Name: sparc_ffu_dp
// Description: This is the ffu datapath. It stores the 2 128 bit operands
// and the result (puts result in the 1st source to save space).
*/
`include "iop.h"
module sparc_ffu_dp (/*AUTOARG*/
// Outputs
so, dp_frf_data, ffu_lsu_data, dp_vis_rs1_data, dp_vis_rs2_data,
dp_ctl_rs2_sign, dp_ctl_fsr_fcc, dp_ctl_fsr_rnd, dp_ctl_fsr_tem,
dp_ctl_fsr_aexc, dp_ctl_fsr_cexc, dp_ctl_ld_fcc,
dp_ctl_gsr_mask_e, dp_ctl_gsr_scale_e, dp_ctl_synd_out_low,
dp_ctl_synd_out_high,
// Inputs
rclk, se, si, ctl_dp_rst_l, frf_dp_data, cpx_fpu_data,
lsu_ffu_ld_data, vis_dp_rd_data, ctl_dp_wsr_data_w2, ctl_dp_sign,
ctl_dp_exc_w2, ctl_dp_fcc_w2, ctl_dp_ftt_w2, ctl_dp_noshift64_frf,
ctl_dp_shift_frf_right, ctl_dp_shift_frf_left,
ctl_dp_zero_low32_frf, ctl_dp_output_sel_rs1,
ctl_dp_output_sel_rs2, ctl_dp_output_sel_frf,
ctl_dp_output_sel_fsr, ctl_dp_noflip_lsu, ctl_dp_flip_lsu,
ctl_dp_noflip_fpu, ctl_dp_flip_fpu, ctl_dp_rs2_frf_read,
ctl_dp_rs2_sel_vis, ctl_dp_rs2_sel_fpu_lsu, ctl_dp_rs2_keep_data,
ctl_dp_rd_ecc, ctl_dp_fp_thr, ctl_dp_fsr_sel_old,
ctl_dp_fsr_sel_ld, ctl_dp_fsr_sel_fpu, ctl_dp_gsr_wsr_w2,
ctl_dp_thr_e, ctl_dp_new_rs1, ctl_dp_ecc_sel_frf
) ;
input rclk;
input se;
input si;
input ctl_dp_rst_l;
input [77:0] frf_dp_data;
input [63:0] cpx_fpu_data;
input [63:0] lsu_ffu_ld_data;
input [63:0] vis_dp_rd_data;
input [36:0] ctl_dp_wsr_data_w2;
input [1:0] ctl_dp_sign; // sign after abs or neg
input [9:0] ctl_dp_exc_w2;
input [7:0] ctl_dp_fcc_w2;
input [2:0] ctl_dp_ftt_w2;
// mux selects
input ctl_dp_noshift64_frf; // choose output from FRF
input ctl_dp_shift_frf_right;
input ctl_dp_shift_frf_left;
input ctl_dp_zero_low32_frf;
input ctl_dp_output_sel_rs1; // choose output to lsu
input ctl_dp_output_sel_rs2;
input ctl_dp_output_sel_frf;
input ctl_dp_output_sel_fsr;
input ctl_dp_noflip_lsu;// inputs from lsu and fpu
input ctl_dp_flip_lsu;
input ctl_dp_noflip_fpu;
input ctl_dp_flip_fpu;
input ctl_dp_rs2_frf_read; // choose r2
input ctl_dp_rs2_sel_vis;
input ctl_dp_rs2_sel_fpu_lsu;
input ctl_dp_rs2_keep_data;
input ctl_dp_rd_ecc;
input [3:0] ctl_dp_fp_thr;
input [3:0] ctl_dp_fsr_sel_old, // choose what to update FSR with
ctl_dp_fsr_sel_ld,
ctl_dp_fsr_sel_fpu;
input [3:0] ctl_dp_gsr_wsr_w2;
input [3:0] ctl_dp_thr_e;
// rs1 selects
input ctl_dp_new_rs1;
// 2:1 mux selects
input ctl_dp_ecc_sel_frf;
// outputs
output so;
output [63:0] dp_frf_data;
output [63:0] ffu_lsu_data;
output [63:0] dp_vis_rs1_data;
output [63:0] dp_vis_rs2_data;
output [1:0] dp_ctl_rs2_sign; // sign for rs2
output [7:0] dp_ctl_fsr_fcc;
output [1:0] dp_ctl_fsr_rnd;
output [4:0] dp_ctl_fsr_tem;
output [4:0] dp_ctl_fsr_aexc;
output [4:0] dp_ctl_fsr_cexc;
output [7:0] dp_ctl_ld_fcc;
output [31:0] dp_ctl_gsr_mask_e;
output [4:0] dp_ctl_gsr_scale_e;
output [6:0] dp_ctl_synd_out_low; // signals for ecc errors
output [6:0] dp_ctl_synd_out_high;
wire clk;
wire reset;
// local signals
wire [63:0] fpu_ffu_data;
wire [63:0] lsu_ffu_ld_data_d1;
wire [63:0] rs2_rd_data; // stores both the rs2 and rd data
wire [63:0] rs2_rd_data_next;
wire [63:0] write_data; // needed since block loads are pipelined
wire [63:0] rs2_data_changed;
wire [63:0] local_rd_data;
wire [63:0] rs1_data;
wire [63:0] rs1_data_next;
wire [63:0] shifted_frf_data;
wire [63:0] new_frf_data;
wire [63:0] lsu_fpu_data;
wire [63:0] frf_data_in;
wire [6:0] synd_in_low; // input ecc for lower word
wire [6:0] synd_in_h; // input ecc for upper word
wire [63:0] corr_data_next;
wire [63:0] corr_data;
wire [63:0] ecc_data_in;
wire [27:0] current_fsr,
t0_fsr,
t1_fsr,
t2_fsr,
t3_fsr;
wire [27:0] t0_fsr_nxt,
t1_fsr_nxt,
t2_fsr_nxt,
t3_fsr_nxt;
wire [27:0] t0_ldfsr_data,
t0_fpufsr_data;
wire [27:0] t1_ldfsr_data,
t1_fpufsr_data;
wire [27:0] t2_ldfsr_data,
t2_fpufsr_data;
wire [27:0] t3_ldfsr_data,
t3_fpufsr_data;
wire [36:0] gsr_e;
wire [36:0] t0_gsr;
wire [36:0] t0_gsr_nxt;
wire [36:0] t1_gsr;
wire [36:0] t1_gsr_nxt;
wire [36:0] t2_gsr;
wire [36:0] t2_gsr_nxt;
wire [36:0] t3_gsr;
wire [36:0] t3_gsr_nxt;
assign reset = ~ctl_dp_rst_l;
assign clk= rclk;
dff_s #(64) cpx_reg(.din(cpx_fpu_data[63:0]),
.q (fpu_ffu_data[63:0]),
.clk (clk), .se(se), .si(), .so());
// flop for lsu data. the data is flopped in ffu, but the vld is flopped in the lsu.
// This is for timing reasons on the valid bit and Sanjay didn't want to redo the
// lsu dp for the data portion
dff_s #(64) lsu_data_dff(.din(lsu_ffu_ld_data[63:0]), .clk(clk), .q(lsu_ffu_ld_data_d1[63:0]),
.se(se), .si(), .so());
assign dp_ctl_ld_fcc[7:0] = {lsu_ffu_ld_data_d1[37:32], lsu_ffu_ld_data_d1[11:10]};
///////////////////////////////////////////////
// Input from FRF (shift as needed for singles)
// The data needs to be shifted around because these are 64 bit reads but
// the required data might be in either the upper or lower 32 bits for
// singles. If it is a double then the data is left alone.
// If it is a single move and the source and target have the same alignment
// then no change happens. If it is a single move and the source and target
// have different alignments the operands get moved into place for the write.
// If it is data that will be sent to the lsu the data is moved into the lower
// 32 bits. If the data will be sent to the fpu the data is moved to the upper
// 32 bits (if not there already)
///////////////////////////////////////////////
assign frf_data_in[63:32] = frf_dp_data[70:39];
assign frf_data_in[31:0] = frf_dp_data[31:0];
mux3ds #(64) frf_input_mux(.dout(shifted_frf_data[63:0]),
.in0(frf_data_in[63:0]),
.in1({32'b0, frf_data_in[63:32]}),
.in2({frf_data_in[31:0], 32'b0}),
.sel0(ctl_dp_noshift64_frf),
.sel1(ctl_dp_shift_frf_right),
.sel2(ctl_dp_shift_frf_left));
assign new_frf_data[63:32] = shifted_frf_data[63:32];
assign new_frf_data[31:0] = shifted_frf_data[31:0] & {32{~ctl_dp_zero_low32_frf}};
mux4ds #(64) lsu_fpu_input_mux(.dout(lsu_fpu_data[63:0]),
.in0(lsu_ffu_ld_data_d1[63:0]),
.in1({lsu_ffu_ld_data_d1[31:0], 32'b0}),
.in2(fpu_ffu_data[63:0]),
.in3({32'b0, fpu_ffu_data[63:32]}),
.sel0(ctl_dp_noflip_lsu),
.sel1(ctl_dp_flip_lsu),
.sel2(ctl_dp_noflip_fpu),
.sel3(ctl_dp_flip_fpu));
// Data to FRF
dp_buffer #(64) frf_out_buf(.in(write_data[63:0]), .dout (dp_frf_data[63:0]));
// Data to LSU
// Mux for lsu data between two sets of data and the direct
// frf output for stores
mux4ds #(64) output_mux(.dout (ffu_lsu_data[63:0]),
.in0 (rs2_rd_data[63:0]),
.in1 (rs1_data[63:0]),
.in2 (shifted_frf_data[63:0]),
.in3 ({26'b0, current_fsr[27:20], 2'b0, current_fsr[19:15], 6'b0, current_fsr[14:12], 2'b0, current_fsr[11:0]}),
.sel0 (ctl_dp_output_sel_rs2),
.sel1 (ctl_dp_output_sel_rs1),
.sel2 (ctl_dp_output_sel_frf),
.sel3 (ctl_dp_output_sel_fsr));
// RS2 can take value from frf (with modification to sign), from lsu
// or keep value
// The modification to the sign bits allows for FABS and FNEG
assign dp_ctl_rs2_sign[1:0] = {new_frf_data[63], new_frf_data[31]};
assign rs2_data_changed[63:0] = {ctl_dp_sign[1], new_frf_data[62:32],
ctl_dp_sign[0], new_frf_data[30:0]};
dp_mux2es #(64) local_rd_mux(.dout(local_rd_data[63:0]),
.in0(rs2_data_changed[63:0]),
.in1(corr_data[63:0]),
.sel(ctl_dp_rd_ecc));
mux4ds #(64) rs2_rd_mux(.dout (rs2_rd_data_next[63:0]),
.in0 (local_rd_data[63:0]),
.in1 (vis_dp_rd_data[63:0]),
.in2 (lsu_fpu_data[63:0]),
.in3 (rs2_rd_data[63:0]),
.sel0 (ctl_dp_rs2_frf_read),
.sel1 (ctl_dp_rs2_sel_vis),
.sel2 (ctl_dp_rs2_sel_fpu_lsu),
.sel3 (ctl_dp_rs2_keep_data));
dff_s #(64) rs2_rd_dff(.din (rs2_rd_data_next[63:0]),
.q (rs2_rd_data[63:0]),
.clk (clk), .se(se), .si(), .so());
assign dp_vis_rs2_data[63:0] = rs2_rd_data[63:0];
dff_s #(64) write_data_dff(.din(rs2_rd_data[63:0]),
.q(write_data[63:0]),
.clk(clk), .se(se), .si(), .so());
////////////////////////////////////////////////////////
// RS1
////////////////////////////////////////////////////////
// RS1 next either takes value from frf or keeps value
dp_mux2es #(64) rs1_mux(.dout (rs1_data_next[63:0]),
.in0 (rs1_data[63:0]),
.in1 (new_frf_data[63:0]),
.sel (ctl_dp_new_rs1));
dff_s #(64) rs1_dff(.din (rs1_data_next[63:0]),
.q (rs1_data[63:0]),
.clk (clk), .se(se), .si(), .so());
assign dp_vis_rs1_data[63:0] = rs1_data[63:0];
/////////////////////////////////////////////////////////
// FSR
/////////////////////////////////////////////////////////
// FSR takes data from load
// fsr is set by ldfsr, ldxfsr, or any fpu operation
assign t0_ldfsr_data[27:0] = {ctl_dp_fcc_w2[7:2], // fcc3,2,1
lsu_ffu_ld_data_d1[31:30], // RND mode
//2'b0, // rsvd
lsu_ffu_ld_data_d1[27:23], // TEM
//6'b0, // NS, rsvd, ver
t0_fsr[14:12], // ftt
//2'b0, // qne, rsvd
lsu_ffu_ld_data_d1[11:0]}; // fcc0, aexc, cexc
assign t0_fpufsr_data[27:0] = {ctl_dp_fcc_w2[7:2],
t0_fsr[21:20], // rnd
t0_fsr[19:15], // TEM
ctl_dp_ftt_w2[2:0], // ftt
ctl_dp_fcc_w2[1:0],
ctl_dp_exc_w2[9:0]};
assign t1_ldfsr_data[27:0] = {ctl_dp_fcc_w2[7:2], // fcc3,2,1
lsu_ffu_ld_data_d1[31:30], // RND mode
//2'b0, // rsvd
lsu_ffu_ld_data_d1[27:23], // TEM
//6'b0, // NS, rsvd, ver
t1_fsr[14:12], // ftt
//2'b0, // qne, rsvd
lsu_ffu_ld_data_d1[11:0]}; // fcc0, aexc, cexc
assign t1_fpufsr_data[27:0] = {ctl_dp_fcc_w2[7:2],
t1_fsr[21:20], // rnd
t1_fsr[19:15], // TEM
ctl_dp_ftt_w2[2:0], // ftt
ctl_dp_fcc_w2[1:0],
ctl_dp_exc_w2[9:0]};
assign t2_ldfsr_data[27:0] = {ctl_dp_fcc_w2[7:2], // fcc3,2,1
lsu_ffu_ld_data_d1[31:30], // RND mode
//2'b0, // rsvd
lsu_ffu_ld_data_d1[27:23], // TEM
//6'b0, // NS, rsvd, ver
t2_fsr[14:12], // ftt
//2'b0, // qne, rsvd
lsu_ffu_ld_data_d1[11:0]}; // fcc0, aexc, cexc
assign t2_fpufsr_data[27:0] = {ctl_dp_fcc_w2[7:2],
t2_fsr[21:20], // rnd
t2_fsr[19:15], // TEM
ctl_dp_ftt_w2[2:0], // ftt
ctl_dp_fcc_w2[1:0],
ctl_dp_exc_w2[9:0]};
assign t3_ldfsr_data[27:0] = {ctl_dp_fcc_w2[7:2], // fcc3,2,1
lsu_ffu_ld_data_d1[31:30], // RND mode
//2'b0, // rsvd
lsu_ffu_ld_data_d1[27:23], // TEM
//6'b0, // NS, rsvd, ver
t3_fsr[14:12], // ftt
//2'b0, // qne, rsvd
lsu_ffu_ld_data_d1[11:0]}; // fcc0, aexc, cexc
assign t3_fpufsr_data[27:0] = {ctl_dp_fcc_w2[7:2],
t3_fsr[21:20], // rnd
t3_fsr[19:15], // TEM
ctl_dp_ftt_w2[2:0], // ftt
ctl_dp_fcc_w2[1:0],
ctl_dp_exc_w2[9:0]};
`ifdef FPGA_SYN_1THREAD
mux3ds #28 fsr0_mux(.dout (t0_fsr_nxt[27:0]),
.in0 (t0_fsr[27:0]),
.in1 (t0_ldfsr_data[27:0]),
.in2 (t0_fpufsr_data[27:0]),
.sel0 (ctl_dp_fsr_sel_old[0]),
.sel1 (ctl_dp_fsr_sel_ld[0]),
.sel2 (ctl_dp_fsr_sel_fpu[0]));
// FSR registers
// need only 28 flops for FSR since rest are always 0
dffr_s #28 fsr0_reg(.din (t0_fsr_nxt[27:0]),
.q (t0_fsr[27:0]),
.rst(reset),
.clk (clk), .se(se), .si(), .so());
assign current_fsr[27:0] = t0_fsr[27:0];
`else
mux3ds #28 fsr0_mux(.dout (t0_fsr_nxt[27:0]),
.in0 (t0_fsr[27:0]),
.in1 (t0_ldfsr_data[27:0]),
.in2 (t0_fpufsr_data[27:0]),
.sel0 (ctl_dp_fsr_sel_old[0]),
.sel1 (ctl_dp_fsr_sel_ld[0]),
.sel2 (ctl_dp_fsr_sel_fpu[0]));
mux3ds #28 fsr1_mux(.dout (t1_fsr_nxt[27:0]),
.in0 (t1_fsr[27:0]),
.in1 (t1_ldfsr_data[27:0]),
.in2 (t1_fpufsr_data[27:0]),
.sel0 (ctl_dp_fsr_sel_old[1]),
.sel1 (ctl_dp_fsr_sel_ld[1]),
.sel2 (ctl_dp_fsr_sel_fpu[1]));
mux3ds #28 fsr2_mux(.dout (t2_fsr_nxt[27:0]),
.in0 (t2_fsr[27:0]),
.in1 (t2_ldfsr_data[27:0]),
.in2 (t2_fpufsr_data[27:0]),
.sel0 (ctl_dp_fsr_sel_old[2]),
.sel1 (ctl_dp_fsr_sel_ld[2]),
.sel2 (ctl_dp_fsr_sel_fpu[2]));
mux3ds #28 fsr3_mux(.dout (t3_fsr_nxt[27:0]),
.in0 (t3_fsr[27:0]),
.in1 (t3_ldfsr_data[27:0]),
.in2 (t3_fpufsr_data[27:0]),
.sel0 (ctl_dp_fsr_sel_old[3]),
.sel1 (ctl_dp_fsr_sel_ld[3]),
.sel2 (ctl_dp_fsr_sel_fpu[3]));
// FSR registers
// need only 28 flops for FSR since rest are always 0
dffr_s #28 fsr0_reg(.din (t0_fsr_nxt[27:0]),
.q (t0_fsr[27:0]),
.rst(reset),
.clk (clk), .se(se), .si(), .so());
dffr_s #28 fsr1_reg(.din (t1_fsr_nxt[27:0]),
.q (t1_fsr[27:0]),
.rst(reset),
.clk (clk), .se(se), .si(), .so());
dffr_s #28 fsr2_reg(.din (t2_fsr_nxt[27:0]),
.q (t2_fsr[27:0]),
.rst(reset),
.clk (clk), .se(se), .si(), .so());
dffr_s #28 fsr3_reg(.din (t3_fsr_nxt[27:0]),
.q (t3_fsr[27:0]),
.rst(reset),
.clk (clk), .se(se), .si(), .so());
// Current FSR
mux4ds #28 curr_fsr_mux(.dout (current_fsr[27:0]),
.in0 (t0_fsr[27:0]),
.in1 (t1_fsr[27:0]),
.in2 (t2_fsr[27:0]),
.in3 (t3_fsr[27:0]),
.sel0 (ctl_dp_fp_thr[0]),
.sel1 (ctl_dp_fp_thr[1]),
.sel2 (ctl_dp_fp_thr[2]),
.sel3 (ctl_dp_fp_thr[3]));
`endif // !`ifdef FPGA_SYN_1THREAD
assign dp_ctl_fsr_fcc = {current_fsr[27:22], current_fsr[11:10]};
assign dp_ctl_fsr_rnd = current_fsr[21:20];
assign dp_ctl_fsr_tem = current_fsr[19:15];
assign dp_ctl_fsr_aexc = current_fsr[9:5];
assign dp_ctl_fsr_cexc = current_fsr[4:0];
////////////////////////////////////////////////////////////
// ECC generation and correction
////////////////////////////////////////////////////////////
dp_mux2es #(64) ecc_mux(.dout(ecc_data_in[63:0]),
.in0(rs2_rd_data[63:0]),
.in1({frf_dp_data[70:39], frf_dp_data[31:0]}),
.sel(ctl_dp_ecc_sel_frf));
assign synd_in_low[6:0] = {7{ctl_dp_ecc_sel_frf}} & frf_dp_data[38:32];
assign synd_in_h[6:0] = {7{ctl_dp_ecc_sel_frf}} & frf_dp_data[77:71];
zzecc_sctag_ecc39 ecccor_low(.din(ecc_data_in[31:0]),
.parity(synd_in_low[6:0]),
.dout(corr_data_next[31:0]),
.pflag(dp_ctl_synd_out_low[6]),
.cflag(dp_ctl_synd_out_low[5:0]));
zzecc_sctag_ecc39 ecccor_high(.din(ecc_data_in[63:32]),
.parity(synd_in_h[6:0]),
.dout(corr_data_next[63:32]),
.pflag(dp_ctl_synd_out_high[6]),
.cflag(dp_ctl_synd_out_high[5:0]));
dff_s #(64) ecc_corr_data(.din(corr_data_next[63:0]), .q(corr_data[63:0]),
.clk(clk), .se(se), .si(), .so());
////////////////////////////////////////////////
// GSR Storage
////////////////////////////////////////////////
// GSR registers
// need only 37 flops for GSR since rest are always 0
// and the align and rnd fields are in the ctl block
`ifdef FPGA_SYN_1THREAD
dffr_s #37 gsr0_reg(.din (t0_gsr_nxt[36:0]),
.q (t0_gsr[36:0]),
.rst(reset),
.clk (clk), .se(se), .si(), .so());
assign t0_gsr_nxt[36:0] = t0_gsr[36:0];
assign gsr_e[36:0] = t0_gsr[36:0];
`else
dffr_s #37 gsr0_reg(.din (t0_gsr_nxt[36:0]),
.q (t0_gsr[36:0]),
.rst(reset),
.clk (clk), .se(se), .si(), .so());
dffr_s #37 gsr1_reg(.din (t1_gsr_nxt[36:0]),
.q (t1_gsr[36:0]),
.rst(reset),
.clk (clk), .se(se), .si(), .so());
dffr_s #37 gsr2_reg(.din (t2_gsr_nxt[36:0]),
.q (t2_gsr[36:0]),
.rst(reset),
.clk (clk), .se(se), .si(), .so());
dffr_s #37 gsr3_reg(.din (t3_gsr_nxt[36:0]),
.q (t3_gsr[36:0]),
.rst(reset),
.clk (clk), .se(se), .si(), .so());
dp_mux2es #(37) gsr0_mux(.dout(t0_gsr_nxt[36:0]),
.in0(t0_gsr[36:0]),
.in1(ctl_dp_wsr_data_w2[36:0]),
.sel(ctl_dp_gsr_wsr_w2[0]));
dp_mux2es #(37) gsr1_mux(.dout(t1_gsr_nxt[36:0]),
.in0(t1_gsr[36:0]),
.in1(ctl_dp_wsr_data_w2[36:0]),
.sel(ctl_dp_gsr_wsr_w2[1]));
dp_mux2es #(37) gsr2_mux(.dout(t2_gsr_nxt[36:0]),
.in0(t2_gsr[36:0]),
.in1(ctl_dp_wsr_data_w2[36:0]),
.sel(ctl_dp_gsr_wsr_w2[2]));
dp_mux2es #(37) gsr3_mux(.dout(t3_gsr_nxt[36:0]),
.in0(t3_gsr[36:0]),
.in1(ctl_dp_wsr_data_w2[36:0]),
.sel(ctl_dp_gsr_wsr_w2[3]));
// GSR_E
mux4ds #37 curr_gsr_mux(.dout (gsr_e[36:0]),
.in0 (t0_gsr[36:0]),
.in1 (t1_gsr[36:0]),
.in2 (t2_gsr[36:0]),
.in3 (t3_gsr[36:0]),
.sel0 (ctl_dp_thr_e[0]),
.sel1 (ctl_dp_thr_e[1]),
.sel2 (ctl_dp_thr_e[2]),
.sel3 (ctl_dp_thr_e[3]));
`endif // !`ifdef FPGA_SYN_1THREAD
assign dp_ctl_gsr_scale_e[4:0] = gsr_e[4:0];
assign dp_ctl_gsr_mask_e[31:0] = gsr_e[36:5];
endmodule // sparc_ffu_dp
|
//////////////////////////////////////////////////////////////////////
//// ////
//// Generic Single-Port Synchronous RAM ////
//// ////
//// This file is part of memory library available from ////
//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////
//// ////
//// Description ////
//// This block is a wrapper with common single-port ////
//// synchronous memory interface for different ////
//// types of ASIC and FPGA RAMs. Beside universal memory ////
//// interface it also provides behavioral model of generic ////
//// single-port synchronous RAM. ////
//// It should be used in all OPENCORES designs that want to be ////
//// portable accross different target technologies and ////
//// independent of target memory. ////
//// ////
//// Supported ASIC RAMs are: ////
//// - Artisan Single-Port Sync RAM ////
//// - Avant! Two-Port Sync RAM (*) ////
//// - Virage Single-Port Sync RAM ////
//// - Virtual Silicon Single-Port Sync RAM ////
//// ////
//// Supported FPGA RAMs are: ////
//// - Xilinx Virtex RAMB16 ////
//// - Xilinx Virtex RAMB4 ////
//// - Altera LPM ////
//// ////
//// To Do: ////
//// - xilinx rams need external tri-state logic ////
//// - fix avant! two-port ram ////
//// - add additional RAMs ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_spram_64x24.v,v $
// Revision 1.1 2006-12-21 16:46:58 vak
// Initial revision imported from
// http://www.opencores.org/cvsget.cgi/or1k/orp/orp_soc/rtl/verilog.
//
// Revision 1.9 2005/10/19 11:37:56 jcastillo
// Added support for RAMB16 Xilinx4/Spartan3 primitives
//
// Revision 1.8 2004/06/08 18:15:32 lampret
// Changed behavior of the simulation generic models
//
// Revision 1.7 2004/04/05 08:29:57 lampret
// Merged branch_qmem into main tree.
//
// Revision 1.3.4.1 2003/12/09 11:46:48 simons
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
//
// Revision 1.3 2003/04/07 01:19:07 lampret
// Added Altera LPM RAMs. Changed generic RAM output when OE inactive.
//
// Revision 1.2 2002/10/17 20:04:41 lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.8 2001/11/02 18:57:14 lampret
// Modified virtual silicon instantiations.
//
// Revision 1.7 2001/10/22 19:39:56 lampret
// Fixed parameters in generic sprams.
//
// Revision 1.6 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.5 2001/10/14 13:12:09 lampret
// MP3 version.
//
// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
// no message
//
// Revision 1.1 2001/08/09 13:39:33 lampret
// Major clean-up.
//
// Revision 1.2 2001/07/30 05:38:02 lampret
// Adding empty directories required by HDL coding guidelines
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
module or1200_spram_64x24(
`ifdef OR1200_BIST
// RAM BIST
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, addr, di, doq
);
//
// Default address and data buses width
//
parameter aw = 6;
parameter dw = 24;
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
//
// Generic synchronous single-port RAM interface
//
input clk; // Clock
input rst; // Reset
input ce; // Chip enable input
input we; // Write enable input
input oe; // Output enable input
input [aw-1:0] addr; // address bus inputs
input [dw-1:0] di; // input data bus
output [dw-1:0] doq; // output data bus
//
// Internal wires and registers
//
`ifdef OR1200_XILINX_RAMB4
wire [7:0] unconnected;
`else
`ifdef OR1200_XILINX_RAMB16
wire [7:0] unconnected;
`endif // !OR1200_XILINX_RAMB16
`endif // !OR1200_XILINX_RAMB4
`ifdef OR1200_ARTISAN_SSP
`else
`ifdef OR1200_VIRTUALSILICON_SSP
`else
`ifdef OR1200_BIST
assign mbist_so_o = mbist_si_i;
`endif
`endif
`endif
`ifdef OR1200_ARTISAN_SSP
//
// Instantiation of ASIC memory:
//
// Artisan Synchronous Single-Port RAM (ra1sh)
//
`ifdef UNUSED
art_hssp_64x24 #(dw, 1<<aw, aw) artisan_ssp(
`else
`ifdef OR1200_BIST
art_hssp_64x24_bist artisan_ssp(
`else
art_hssp_64x24 artisan_ssp(
`endif
`endif
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CLK(clk),
.CEN(~ce),
.WEN(~we),
.A(addr),
.D(di),
.OEN(~oe),
.Q(doq)
);
`else
`ifdef OR1200_AVANT_ATP
//
// Instantiation of ASIC memory:
//
// Avant! Asynchronous Two-Port RAM
//
avant_atp avant_atp(
.web(~we),
.reb(),
.oeb(~oe),
.rcsb(),
.wcsb(),
.ra(addr),
.wa(addr),
.di(di),
.doq(doq)
);
`else
`ifdef OR1200_VIRAGE_SSP
//
// Instantiation of ASIC memory:
//
// Virage Synchronous 1-port R/W RAM
//
virage_ssp virage_ssp(
.clk(clk),
.adr(addr),
.d(di),
.we(we),
.oe(oe),
.me(ce),
.q(doq)
);
`else
`ifdef OR1200_VIRTUALSILICON_SSP
//
// Instantiation of ASIC memory:
//
// Virtual Silicon Single-Port Synchronous SRAM
//
`ifdef UNUSED
vs_hdsp_64x24 #(1<<aw, aw-1, dw-1) vs_ssp(
`else
`ifdef OR1200_BIST
vs_hdsp_64x24_bist vs_ssp(
`else
vs_hdsp_64x24 vs_ssp(
`endif
`endif
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CK(clk),
.ADR(addr),
.DI(di),
.WEN(~we),
.CEN(~ce),
.OEN(~oe),
.DOUT(doq)
);
`else
`ifdef OR1200_XILINX_RAMB4
//
// Instantiation of FPGA memory:
//
// Virtex/Spartan2
//
//
// Block 0
//
RAMB4_S16 ramb4_s16_0(
.CLK(clk),
.RST(rst),
.ADDR({2'b00, addr}),
.DI(di[15:0]),
.EN(ce),
.WE(we),
.DO(doq[15:0])
);
//
// Block 1
//
RAMB4_S16 ramb4_s16_1(
.CLK(clk),
.RST(rst),
.ADDR({2'b00, addr}),
.DI({8'h00, di[23:16]}),
.EN(ce),
.WE(we),
.DO({unconnected, doq[23:16]})
);
`else
`ifdef OR1200_XILINX_RAMB16
//
// Instantiation of FPGA memory:
//
// Virtex4/Spartan3E
//
// Added By Nir Mor
//
RAMB16_S36 ramb16_s36(
.CLK(clk),
.SSR(rst),
.ADDR({3'b000, addr}),
.DI({8'h00,di}),
.DIP(4'h0),
.EN(ce),
.WE(we),
.DO({unconnected, doq}),
.DOP()
);
`else
`ifdef OR1200_ALTERA_LPM
//
// Instantiation of FPGA memory:
//
// Altera LPM
//
// Added By Jamil Khatib
//
wire wr;
assign wr = ce & we;
initial $display("Using Altera LPM.");
lpm_ram_dq lpm_ram_dq_component (
.address(addr),
.inclock(clk),
.outclock(clk),
.data(di),
.we(wr),
.q(doq)
);
defparam lpm_ram_dq_component.lpm_width = dw,
lpm_ram_dq_component.lpm_widthad = aw,
lpm_ram_dq_component.lpm_indata = "REGISTERED",
lpm_ram_dq_component.lpm_address_control = "REGISTERED",
lpm_ram_dq_component.lpm_outdata = "UNREGISTERED",
lpm_ram_dq_component.lpm_hint = "USE_EAB=ON";
// examplar attribute lpm_ram_dq_component NOOPT TRUE
`else
//
// Generic single-port synchronous RAM model
//
//
// Generic RAM's registers and wires
//
reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content
reg [aw-1:0] addr_reg; // RAM address register
//
// Data output drivers
//
assign doq = (oe) ? mem[addr_reg] : {dw{1'b0}};
//
// RAM address register
//
always @(posedge clk or posedge rst)
if (rst)
addr_reg <= #1 {aw{1'b0}};
else if (ce)
addr_reg <= #1 addr;
//
// RAM write
//
always @(posedge clk)
if (ce && we)
mem[addr] <= #1 di;
`endif // !OR1200_ALTERA_LPM
`endif // !OR1200_XILINX_RAMB16
`endif // !OR1200_XILINX_RAMB4
`endif // !OR1200_VIRTUALSILICON_SSP
`endif // !OR1200_VIRAGE_SSP
`endif // !OR1200_AVANT_ATP
`endif // !OR1200_ARTISAN_SSP
endmodule
|
//
// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17)
//
//
//
//
// Ports:
// Name I/O size props
// RDY_reset O 1
// RDY_set_verbosity O 1 const
// v_from_masters_0_awready O 1 reg
// v_from_masters_0_wready O 1 reg
// v_from_masters_0_bvalid O 1 reg
// v_from_masters_0_bid O 4 reg
// v_from_masters_0_bresp O 2 reg
// v_from_masters_0_arready O 1 reg
// v_from_masters_0_rvalid O 1 reg
// v_from_masters_0_rid O 4 reg
// v_from_masters_0_rdata O 64 reg
// v_from_masters_0_rresp O 2 reg
// v_from_masters_0_rlast O 1 reg
// v_from_masters_1_awready O 1 reg
// v_from_masters_1_wready O 1 reg
// v_from_masters_1_bvalid O 1 reg
// v_from_masters_1_bid O 4 reg
// v_from_masters_1_bresp O 2 reg
// v_from_masters_1_arready O 1 reg
// v_from_masters_1_rvalid O 1 reg
// v_from_masters_1_rid O 4 reg
// v_from_masters_1_rdata O 64 reg
// v_from_masters_1_rresp O 2 reg
// v_from_masters_1_rlast O 1 reg
// v_to_slaves_0_awvalid O 1 reg
// v_to_slaves_0_awid O 4 reg
// v_to_slaves_0_awaddr O 64 reg
// v_to_slaves_0_awlen O 8 reg
// v_to_slaves_0_awsize O 3 reg
// v_to_slaves_0_awburst O 2 reg
// v_to_slaves_0_awlock O 1 reg
// v_to_slaves_0_awcache O 4 reg
// v_to_slaves_0_awprot O 3 reg
// v_to_slaves_0_awqos O 4 reg
// v_to_slaves_0_awregion O 4 reg
// v_to_slaves_0_wvalid O 1 reg
// v_to_slaves_0_wdata O 64 reg
// v_to_slaves_0_wstrb O 8 reg
// v_to_slaves_0_wlast O 1 reg
// v_to_slaves_0_bready O 1 reg
// v_to_slaves_0_arvalid O 1 reg
// v_to_slaves_0_arid O 4 reg
// v_to_slaves_0_araddr O 64 reg
// v_to_slaves_0_arlen O 8 reg
// v_to_slaves_0_arsize O 3 reg
// v_to_slaves_0_arburst O 2 reg
// v_to_slaves_0_arlock O 1 reg
// v_to_slaves_0_arcache O 4 reg
// v_to_slaves_0_arprot O 3 reg
// v_to_slaves_0_arqos O 4 reg
// v_to_slaves_0_arregion O 4 reg
// v_to_slaves_0_rready O 1 reg
// v_to_slaves_1_awvalid O 1 reg
// v_to_slaves_1_awid O 4 reg
// v_to_slaves_1_awaddr O 64 reg
// v_to_slaves_1_awlen O 8 reg
// v_to_slaves_1_awsize O 3 reg
// v_to_slaves_1_awburst O 2 reg
// v_to_slaves_1_awlock O 1 reg
// v_to_slaves_1_awcache O 4 reg
// v_to_slaves_1_awprot O 3 reg
// v_to_slaves_1_awqos O 4 reg
// v_to_slaves_1_awregion O 4 reg
// v_to_slaves_1_wvalid O 1 reg
// v_to_slaves_1_wdata O 64 reg
// v_to_slaves_1_wstrb O 8 reg
// v_to_slaves_1_wlast O 1 reg
// v_to_slaves_1_bready O 1 reg
// v_to_slaves_1_arvalid O 1 reg
// v_to_slaves_1_arid O 4 reg
// v_to_slaves_1_araddr O 64 reg
// v_to_slaves_1_arlen O 8 reg
// v_to_slaves_1_arsize O 3 reg
// v_to_slaves_1_arburst O 2 reg
// v_to_slaves_1_arlock O 1 reg
// v_to_slaves_1_arcache O 4 reg
// v_to_slaves_1_arprot O 3 reg
// v_to_slaves_1_arqos O 4 reg
// v_to_slaves_1_arregion O 4 reg
// v_to_slaves_1_rready O 1 reg
// v_to_slaves_2_awvalid O 1 reg
// v_to_slaves_2_awid O 4 reg
// v_to_slaves_2_awaddr O 64 reg
// v_to_slaves_2_awlen O 8 reg
// v_to_slaves_2_awsize O 3 reg
// v_to_slaves_2_awburst O 2 reg
// v_to_slaves_2_awlock O 1 reg
// v_to_slaves_2_awcache O 4 reg
// v_to_slaves_2_awprot O 3 reg
// v_to_slaves_2_awqos O 4 reg
// v_to_slaves_2_awregion O 4 reg
// v_to_slaves_2_wvalid O 1 reg
// v_to_slaves_2_wdata O 64 reg
// v_to_slaves_2_wstrb O 8 reg
// v_to_slaves_2_wlast O 1 reg
// v_to_slaves_2_bready O 1 reg
// v_to_slaves_2_arvalid O 1 reg
// v_to_slaves_2_arid O 4 reg
// v_to_slaves_2_araddr O 64 reg
// v_to_slaves_2_arlen O 8 reg
// v_to_slaves_2_arsize O 3 reg
// v_to_slaves_2_arburst O 2 reg
// v_to_slaves_2_arlock O 1 reg
// v_to_slaves_2_arcache O 4 reg
// v_to_slaves_2_arprot O 3 reg
// v_to_slaves_2_arqos O 4 reg
// v_to_slaves_2_arregion O 4 reg
// v_to_slaves_2_rready O 1 reg
// CLK I 1 clock
// RST_N I 1 reset
// set_verbosity_verbosity I 4 reg
// v_from_masters_0_awvalid I 1
// v_from_masters_0_awid I 4 reg
// v_from_masters_0_awaddr I 64 reg
// v_from_masters_0_awlen I 8 reg
// v_from_masters_0_awsize I 3 reg
// v_from_masters_0_awburst I 2 reg
// v_from_masters_0_awlock I 1 reg
// v_from_masters_0_awcache I 4 reg
// v_from_masters_0_awprot I 3 reg
// v_from_masters_0_awqos I 4 reg
// v_from_masters_0_awregion I 4 reg
// v_from_masters_0_wvalid I 1
// v_from_masters_0_wdata I 64 reg
// v_from_masters_0_wstrb I 8 reg
// v_from_masters_0_wlast I 1 reg
// v_from_masters_0_bready I 1
// v_from_masters_0_arvalid I 1
// v_from_masters_0_arid I 4 reg
// v_from_masters_0_araddr I 64 reg
// v_from_masters_0_arlen I 8 reg
// v_from_masters_0_arsize I 3 reg
// v_from_masters_0_arburst I 2 reg
// v_from_masters_0_arlock I 1 reg
// v_from_masters_0_arcache I 4 reg
// v_from_masters_0_arprot I 3 reg
// v_from_masters_0_arqos I 4 reg
// v_from_masters_0_arregion I 4 reg
// v_from_masters_0_rready I 1
// v_from_masters_1_awvalid I 1
// v_from_masters_1_awid I 4 reg
// v_from_masters_1_awaddr I 64 reg
// v_from_masters_1_awlen I 8 reg
// v_from_masters_1_awsize I 3 reg
// v_from_masters_1_awburst I 2 reg
// v_from_masters_1_awlock I 1 reg
// v_from_masters_1_awcache I 4 reg
// v_from_masters_1_awprot I 3 reg
// v_from_masters_1_awqos I 4 reg
// v_from_masters_1_awregion I 4 reg
// v_from_masters_1_wvalid I 1
// v_from_masters_1_wdata I 64 reg
// v_from_masters_1_wstrb I 8 reg
// v_from_masters_1_wlast I 1 reg
// v_from_masters_1_bready I 1
// v_from_masters_1_arvalid I 1
// v_from_masters_1_arid I 4 reg
// v_from_masters_1_araddr I 64 reg
// v_from_masters_1_arlen I 8 reg
// v_from_masters_1_arsize I 3 reg
// v_from_masters_1_arburst I 2 reg
// v_from_masters_1_arlock I 1 reg
// v_from_masters_1_arcache I 4 reg
// v_from_masters_1_arprot I 3 reg
// v_from_masters_1_arqos I 4 reg
// v_from_masters_1_arregion I 4 reg
// v_from_masters_1_rready I 1
// v_to_slaves_0_awready I 1
// v_to_slaves_0_wready I 1
// v_to_slaves_0_bvalid I 1
// v_to_slaves_0_bid I 4 reg
// v_to_slaves_0_bresp I 2 reg
// v_to_slaves_0_arready I 1
// v_to_slaves_0_rvalid I 1
// v_to_slaves_0_rid I 4 reg
// v_to_slaves_0_rdata I 64 reg
// v_to_slaves_0_rresp I 2 reg
// v_to_slaves_0_rlast I 1 reg
// v_to_slaves_1_awready I 1
// v_to_slaves_1_wready I 1
// v_to_slaves_1_bvalid I 1
// v_to_slaves_1_bid I 4 reg
// v_to_slaves_1_bresp I 2 reg
// v_to_slaves_1_arready I 1
// v_to_slaves_1_rvalid I 1
// v_to_slaves_1_rid I 4 reg
// v_to_slaves_1_rdata I 64 reg
// v_to_slaves_1_rresp I 2 reg
// v_to_slaves_1_rlast I 1 reg
// v_to_slaves_2_awready I 1
// v_to_slaves_2_wready I 1
// v_to_slaves_2_bvalid I 1
// v_to_slaves_2_bid I 4 reg
// v_to_slaves_2_bresp I 2 reg
// v_to_slaves_2_arready I 1
// v_to_slaves_2_rvalid I 1
// v_to_slaves_2_rid I 4 reg
// v_to_slaves_2_rdata I 64 reg
// v_to_slaves_2_rresp I 2 reg
// v_to_slaves_2_rlast I 1 reg
// EN_reset I 1
// EN_set_verbosity I 1
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkFabric_AXI4(CLK,
RST_N,
EN_reset,
RDY_reset,
set_verbosity_verbosity,
EN_set_verbosity,
RDY_set_verbosity,
v_from_masters_0_awvalid,
v_from_masters_0_awid,
v_from_masters_0_awaddr,
v_from_masters_0_awlen,
v_from_masters_0_awsize,
v_from_masters_0_awburst,
v_from_masters_0_awlock,
v_from_masters_0_awcache,
v_from_masters_0_awprot,
v_from_masters_0_awqos,
v_from_masters_0_awregion,
v_from_masters_0_awready,
v_from_masters_0_wvalid,
v_from_masters_0_wdata,
v_from_masters_0_wstrb,
v_from_masters_0_wlast,
v_from_masters_0_wready,
v_from_masters_0_bvalid,
v_from_masters_0_bid,
v_from_masters_0_bresp,
v_from_masters_0_bready,
v_from_masters_0_arvalid,
v_from_masters_0_arid,
v_from_masters_0_araddr,
v_from_masters_0_arlen,
v_from_masters_0_arsize,
v_from_masters_0_arburst,
v_from_masters_0_arlock,
v_from_masters_0_arcache,
v_from_masters_0_arprot,
v_from_masters_0_arqos,
v_from_masters_0_arregion,
v_from_masters_0_arready,
v_from_masters_0_rvalid,
v_from_masters_0_rid,
v_from_masters_0_rdata,
v_from_masters_0_rresp,
v_from_masters_0_rlast,
v_from_masters_0_rready,
v_from_masters_1_awvalid,
v_from_masters_1_awid,
v_from_masters_1_awaddr,
v_from_masters_1_awlen,
v_from_masters_1_awsize,
v_from_masters_1_awburst,
v_from_masters_1_awlock,
v_from_masters_1_awcache,
v_from_masters_1_awprot,
v_from_masters_1_awqos,
v_from_masters_1_awregion,
v_from_masters_1_awready,
v_from_masters_1_wvalid,
v_from_masters_1_wdata,
v_from_masters_1_wstrb,
v_from_masters_1_wlast,
v_from_masters_1_wready,
v_from_masters_1_bvalid,
v_from_masters_1_bid,
v_from_masters_1_bresp,
v_from_masters_1_bready,
v_from_masters_1_arvalid,
v_from_masters_1_arid,
v_from_masters_1_araddr,
v_from_masters_1_arlen,
v_from_masters_1_arsize,
v_from_masters_1_arburst,
v_from_masters_1_arlock,
v_from_masters_1_arcache,
v_from_masters_1_arprot,
v_from_masters_1_arqos,
v_from_masters_1_arregion,
v_from_masters_1_arready,
v_from_masters_1_rvalid,
v_from_masters_1_rid,
v_from_masters_1_rdata,
v_from_masters_1_rresp,
v_from_masters_1_rlast,
v_from_masters_1_rready,
v_to_slaves_0_awvalid,
v_to_slaves_0_awid,
v_to_slaves_0_awaddr,
v_to_slaves_0_awlen,
v_to_slaves_0_awsize,
v_to_slaves_0_awburst,
v_to_slaves_0_awlock,
v_to_slaves_0_awcache,
v_to_slaves_0_awprot,
v_to_slaves_0_awqos,
v_to_slaves_0_awregion,
v_to_slaves_0_awready,
v_to_slaves_0_wvalid,
v_to_slaves_0_wdata,
v_to_slaves_0_wstrb,
v_to_slaves_0_wlast,
v_to_slaves_0_wready,
v_to_slaves_0_bvalid,
v_to_slaves_0_bid,
v_to_slaves_0_bresp,
v_to_slaves_0_bready,
v_to_slaves_0_arvalid,
v_to_slaves_0_arid,
v_to_slaves_0_araddr,
v_to_slaves_0_arlen,
v_to_slaves_0_arsize,
v_to_slaves_0_arburst,
v_to_slaves_0_arlock,
v_to_slaves_0_arcache,
v_to_slaves_0_arprot,
v_to_slaves_0_arqos,
v_to_slaves_0_arregion,
v_to_slaves_0_arready,
v_to_slaves_0_rvalid,
v_to_slaves_0_rid,
v_to_slaves_0_rdata,
v_to_slaves_0_rresp,
v_to_slaves_0_rlast,
v_to_slaves_0_rready,
v_to_slaves_1_awvalid,
v_to_slaves_1_awid,
v_to_slaves_1_awaddr,
v_to_slaves_1_awlen,
v_to_slaves_1_awsize,
v_to_slaves_1_awburst,
v_to_slaves_1_awlock,
v_to_slaves_1_awcache,
v_to_slaves_1_awprot,
v_to_slaves_1_awqos,
v_to_slaves_1_awregion,
v_to_slaves_1_awready,
v_to_slaves_1_wvalid,
v_to_slaves_1_wdata,
v_to_slaves_1_wstrb,
v_to_slaves_1_wlast,
v_to_slaves_1_wready,
v_to_slaves_1_bvalid,
v_to_slaves_1_bid,
v_to_slaves_1_bresp,
v_to_slaves_1_bready,
v_to_slaves_1_arvalid,
v_to_slaves_1_arid,
v_to_slaves_1_araddr,
v_to_slaves_1_arlen,
v_to_slaves_1_arsize,
v_to_slaves_1_arburst,
v_to_slaves_1_arlock,
v_to_slaves_1_arcache,
v_to_slaves_1_arprot,
v_to_slaves_1_arqos,
v_to_slaves_1_arregion,
v_to_slaves_1_arready,
v_to_slaves_1_rvalid,
v_to_slaves_1_rid,
v_to_slaves_1_rdata,
v_to_slaves_1_rresp,
v_to_slaves_1_rlast,
v_to_slaves_1_rready,
v_to_slaves_2_awvalid,
v_to_slaves_2_awid,
v_to_slaves_2_awaddr,
v_to_slaves_2_awlen,
v_to_slaves_2_awsize,
v_to_slaves_2_awburst,
v_to_slaves_2_awlock,
v_to_slaves_2_awcache,
v_to_slaves_2_awprot,
v_to_slaves_2_awqos,
v_to_slaves_2_awregion,
v_to_slaves_2_awready,
v_to_slaves_2_wvalid,
v_to_slaves_2_wdata,
v_to_slaves_2_wstrb,
v_to_slaves_2_wlast,
v_to_slaves_2_wready,
v_to_slaves_2_bvalid,
v_to_slaves_2_bid,
v_to_slaves_2_bresp,
v_to_slaves_2_bready,
v_to_slaves_2_arvalid,
v_to_slaves_2_arid,
v_to_slaves_2_araddr,
v_to_slaves_2_arlen,
v_to_slaves_2_arsize,
v_to_slaves_2_arburst,
v_to_slaves_2_arlock,
v_to_slaves_2_arcache,
v_to_slaves_2_arprot,
v_to_slaves_2_arqos,
v_to_slaves_2_arregion,
v_to_slaves_2_arready,
v_to_slaves_2_rvalid,
v_to_slaves_2_rid,
v_to_slaves_2_rdata,
v_to_slaves_2_rresp,
v_to_slaves_2_rlast,
v_to_slaves_2_rready);
input CLK;
input RST_N;
// action method reset
input EN_reset;
output RDY_reset;
// action method set_verbosity
input [3 : 0] set_verbosity_verbosity;
input EN_set_verbosity;
output RDY_set_verbosity;
// action method v_from_masters_0_m_awvalid
input v_from_masters_0_awvalid;
input [3 : 0] v_from_masters_0_awid;
input [63 : 0] v_from_masters_0_awaddr;
input [7 : 0] v_from_masters_0_awlen;
input [2 : 0] v_from_masters_0_awsize;
input [1 : 0] v_from_masters_0_awburst;
input v_from_masters_0_awlock;
input [3 : 0] v_from_masters_0_awcache;
input [2 : 0] v_from_masters_0_awprot;
input [3 : 0] v_from_masters_0_awqos;
input [3 : 0] v_from_masters_0_awregion;
// value method v_from_masters_0_m_awready
output v_from_masters_0_awready;
// action method v_from_masters_0_m_wvalid
input v_from_masters_0_wvalid;
input [63 : 0] v_from_masters_0_wdata;
input [7 : 0] v_from_masters_0_wstrb;
input v_from_masters_0_wlast;
// value method v_from_masters_0_m_wready
output v_from_masters_0_wready;
// value method v_from_masters_0_m_bvalid
output v_from_masters_0_bvalid;
// value method v_from_masters_0_m_bid
output [3 : 0] v_from_masters_0_bid;
// value method v_from_masters_0_m_bresp
output [1 : 0] v_from_masters_0_bresp;
// value method v_from_masters_0_m_buser
// action method v_from_masters_0_m_bready
input v_from_masters_0_bready;
// action method v_from_masters_0_m_arvalid
input v_from_masters_0_arvalid;
input [3 : 0] v_from_masters_0_arid;
input [63 : 0] v_from_masters_0_araddr;
input [7 : 0] v_from_masters_0_arlen;
input [2 : 0] v_from_masters_0_arsize;
input [1 : 0] v_from_masters_0_arburst;
input v_from_masters_0_arlock;
input [3 : 0] v_from_masters_0_arcache;
input [2 : 0] v_from_masters_0_arprot;
input [3 : 0] v_from_masters_0_arqos;
input [3 : 0] v_from_masters_0_arregion;
// value method v_from_masters_0_m_arready
output v_from_masters_0_arready;
// value method v_from_masters_0_m_rvalid
output v_from_masters_0_rvalid;
// value method v_from_masters_0_m_rid
output [3 : 0] v_from_masters_0_rid;
// value method v_from_masters_0_m_rdata
output [63 : 0] v_from_masters_0_rdata;
// value method v_from_masters_0_m_rresp
output [1 : 0] v_from_masters_0_rresp;
// value method v_from_masters_0_m_rlast
output v_from_masters_0_rlast;
// value method v_from_masters_0_m_ruser
// action method v_from_masters_0_m_rready
input v_from_masters_0_rready;
// action method v_from_masters_1_m_awvalid
input v_from_masters_1_awvalid;
input [3 : 0] v_from_masters_1_awid;
input [63 : 0] v_from_masters_1_awaddr;
input [7 : 0] v_from_masters_1_awlen;
input [2 : 0] v_from_masters_1_awsize;
input [1 : 0] v_from_masters_1_awburst;
input v_from_masters_1_awlock;
input [3 : 0] v_from_masters_1_awcache;
input [2 : 0] v_from_masters_1_awprot;
input [3 : 0] v_from_masters_1_awqos;
input [3 : 0] v_from_masters_1_awregion;
// value method v_from_masters_1_m_awready
output v_from_masters_1_awready;
// action method v_from_masters_1_m_wvalid
input v_from_masters_1_wvalid;
input [63 : 0] v_from_masters_1_wdata;
input [7 : 0] v_from_masters_1_wstrb;
input v_from_masters_1_wlast;
// value method v_from_masters_1_m_wready
output v_from_masters_1_wready;
// value method v_from_masters_1_m_bvalid
output v_from_masters_1_bvalid;
// value method v_from_masters_1_m_bid
output [3 : 0] v_from_masters_1_bid;
// value method v_from_masters_1_m_bresp
output [1 : 0] v_from_masters_1_bresp;
// value method v_from_masters_1_m_buser
// action method v_from_masters_1_m_bready
input v_from_masters_1_bready;
// action method v_from_masters_1_m_arvalid
input v_from_masters_1_arvalid;
input [3 : 0] v_from_masters_1_arid;
input [63 : 0] v_from_masters_1_araddr;
input [7 : 0] v_from_masters_1_arlen;
input [2 : 0] v_from_masters_1_arsize;
input [1 : 0] v_from_masters_1_arburst;
input v_from_masters_1_arlock;
input [3 : 0] v_from_masters_1_arcache;
input [2 : 0] v_from_masters_1_arprot;
input [3 : 0] v_from_masters_1_arqos;
input [3 : 0] v_from_masters_1_arregion;
// value method v_from_masters_1_m_arready
output v_from_masters_1_arready;
// value method v_from_masters_1_m_rvalid
output v_from_masters_1_rvalid;
// value method v_from_masters_1_m_rid
output [3 : 0] v_from_masters_1_rid;
// value method v_from_masters_1_m_rdata
output [63 : 0] v_from_masters_1_rdata;
// value method v_from_masters_1_m_rresp
output [1 : 0] v_from_masters_1_rresp;
// value method v_from_masters_1_m_rlast
output v_from_masters_1_rlast;
// value method v_from_masters_1_m_ruser
// action method v_from_masters_1_m_rready
input v_from_masters_1_rready;
// value method v_to_slaves_0_m_awvalid
output v_to_slaves_0_awvalid;
// value method v_to_slaves_0_m_awid
output [3 : 0] v_to_slaves_0_awid;
// value method v_to_slaves_0_m_awaddr
output [63 : 0] v_to_slaves_0_awaddr;
// value method v_to_slaves_0_m_awlen
output [7 : 0] v_to_slaves_0_awlen;
// value method v_to_slaves_0_m_awsize
output [2 : 0] v_to_slaves_0_awsize;
// value method v_to_slaves_0_m_awburst
output [1 : 0] v_to_slaves_0_awburst;
// value method v_to_slaves_0_m_awlock
output v_to_slaves_0_awlock;
// value method v_to_slaves_0_m_awcache
output [3 : 0] v_to_slaves_0_awcache;
// value method v_to_slaves_0_m_awprot
output [2 : 0] v_to_slaves_0_awprot;
// value method v_to_slaves_0_m_awqos
output [3 : 0] v_to_slaves_0_awqos;
// value method v_to_slaves_0_m_awregion
output [3 : 0] v_to_slaves_0_awregion;
// value method v_to_slaves_0_m_awuser
// action method v_to_slaves_0_m_awready
input v_to_slaves_0_awready;
// value method v_to_slaves_0_m_wvalid
output v_to_slaves_0_wvalid;
// value method v_to_slaves_0_m_wdata
output [63 : 0] v_to_slaves_0_wdata;
// value method v_to_slaves_0_m_wstrb
output [7 : 0] v_to_slaves_0_wstrb;
// value method v_to_slaves_0_m_wlast
output v_to_slaves_0_wlast;
// value method v_to_slaves_0_m_wuser
// action method v_to_slaves_0_m_wready
input v_to_slaves_0_wready;
// action method v_to_slaves_0_m_bvalid
input v_to_slaves_0_bvalid;
input [3 : 0] v_to_slaves_0_bid;
input [1 : 0] v_to_slaves_0_bresp;
// value method v_to_slaves_0_m_bready
output v_to_slaves_0_bready;
// value method v_to_slaves_0_m_arvalid
output v_to_slaves_0_arvalid;
// value method v_to_slaves_0_m_arid
output [3 : 0] v_to_slaves_0_arid;
// value method v_to_slaves_0_m_araddr
output [63 : 0] v_to_slaves_0_araddr;
// value method v_to_slaves_0_m_arlen
output [7 : 0] v_to_slaves_0_arlen;
// value method v_to_slaves_0_m_arsize
output [2 : 0] v_to_slaves_0_arsize;
// value method v_to_slaves_0_m_arburst
output [1 : 0] v_to_slaves_0_arburst;
// value method v_to_slaves_0_m_arlock
output v_to_slaves_0_arlock;
// value method v_to_slaves_0_m_arcache
output [3 : 0] v_to_slaves_0_arcache;
// value method v_to_slaves_0_m_arprot
output [2 : 0] v_to_slaves_0_arprot;
// value method v_to_slaves_0_m_arqos
output [3 : 0] v_to_slaves_0_arqos;
// value method v_to_slaves_0_m_arregion
output [3 : 0] v_to_slaves_0_arregion;
// value method v_to_slaves_0_m_aruser
// action method v_to_slaves_0_m_arready
input v_to_slaves_0_arready;
// action method v_to_slaves_0_m_rvalid
input v_to_slaves_0_rvalid;
input [3 : 0] v_to_slaves_0_rid;
input [63 : 0] v_to_slaves_0_rdata;
input [1 : 0] v_to_slaves_0_rresp;
input v_to_slaves_0_rlast;
// value method v_to_slaves_0_m_rready
output v_to_slaves_0_rready;
// value method v_to_slaves_1_m_awvalid
output v_to_slaves_1_awvalid;
// value method v_to_slaves_1_m_awid
output [3 : 0] v_to_slaves_1_awid;
// value method v_to_slaves_1_m_awaddr
output [63 : 0] v_to_slaves_1_awaddr;
// value method v_to_slaves_1_m_awlen
output [7 : 0] v_to_slaves_1_awlen;
// value method v_to_slaves_1_m_awsize
output [2 : 0] v_to_slaves_1_awsize;
// value method v_to_slaves_1_m_awburst
output [1 : 0] v_to_slaves_1_awburst;
// value method v_to_slaves_1_m_awlock
output v_to_slaves_1_awlock;
// value method v_to_slaves_1_m_awcache
output [3 : 0] v_to_slaves_1_awcache;
// value method v_to_slaves_1_m_awprot
output [2 : 0] v_to_slaves_1_awprot;
// value method v_to_slaves_1_m_awqos
output [3 : 0] v_to_slaves_1_awqos;
// value method v_to_slaves_1_m_awregion
output [3 : 0] v_to_slaves_1_awregion;
// value method v_to_slaves_1_m_awuser
// action method v_to_slaves_1_m_awready
input v_to_slaves_1_awready;
// value method v_to_slaves_1_m_wvalid
output v_to_slaves_1_wvalid;
// value method v_to_slaves_1_m_wdata
output [63 : 0] v_to_slaves_1_wdata;
// value method v_to_slaves_1_m_wstrb
output [7 : 0] v_to_slaves_1_wstrb;
// value method v_to_slaves_1_m_wlast
output v_to_slaves_1_wlast;
// value method v_to_slaves_1_m_wuser
// action method v_to_slaves_1_m_wready
input v_to_slaves_1_wready;
// action method v_to_slaves_1_m_bvalid
input v_to_slaves_1_bvalid;
input [3 : 0] v_to_slaves_1_bid;
input [1 : 0] v_to_slaves_1_bresp;
// value method v_to_slaves_1_m_bready
output v_to_slaves_1_bready;
// value method v_to_slaves_1_m_arvalid
output v_to_slaves_1_arvalid;
// value method v_to_slaves_1_m_arid
output [3 : 0] v_to_slaves_1_arid;
// value method v_to_slaves_1_m_araddr
output [63 : 0] v_to_slaves_1_araddr;
// value method v_to_slaves_1_m_arlen
output [7 : 0] v_to_slaves_1_arlen;
// value method v_to_slaves_1_m_arsize
output [2 : 0] v_to_slaves_1_arsize;
// value method v_to_slaves_1_m_arburst
output [1 : 0] v_to_slaves_1_arburst;
// value method v_to_slaves_1_m_arlock
output v_to_slaves_1_arlock;
// value method v_to_slaves_1_m_arcache
output [3 : 0] v_to_slaves_1_arcache;
// value method v_to_slaves_1_m_arprot
output [2 : 0] v_to_slaves_1_arprot;
// value method v_to_slaves_1_m_arqos
output [3 : 0] v_to_slaves_1_arqos;
// value method v_to_slaves_1_m_arregion
output [3 : 0] v_to_slaves_1_arregion;
// value method v_to_slaves_1_m_aruser
// action method v_to_slaves_1_m_arready
input v_to_slaves_1_arready;
// action method v_to_slaves_1_m_rvalid
input v_to_slaves_1_rvalid;
input [3 : 0] v_to_slaves_1_rid;
input [63 : 0] v_to_slaves_1_rdata;
input [1 : 0] v_to_slaves_1_rresp;
input v_to_slaves_1_rlast;
// value method v_to_slaves_1_m_rready
output v_to_slaves_1_rready;
// value method v_to_slaves_2_m_awvalid
output v_to_slaves_2_awvalid;
// value method v_to_slaves_2_m_awid
output [3 : 0] v_to_slaves_2_awid;
// value method v_to_slaves_2_m_awaddr
output [63 : 0] v_to_slaves_2_awaddr;
// value method v_to_slaves_2_m_awlen
output [7 : 0] v_to_slaves_2_awlen;
// value method v_to_slaves_2_m_awsize
output [2 : 0] v_to_slaves_2_awsize;
// value method v_to_slaves_2_m_awburst
output [1 : 0] v_to_slaves_2_awburst;
// value method v_to_slaves_2_m_awlock
output v_to_slaves_2_awlock;
// value method v_to_slaves_2_m_awcache
output [3 : 0] v_to_slaves_2_awcache;
// value method v_to_slaves_2_m_awprot
output [2 : 0] v_to_slaves_2_awprot;
// value method v_to_slaves_2_m_awqos
output [3 : 0] v_to_slaves_2_awqos;
// value method v_to_slaves_2_m_awregion
output [3 : 0] v_to_slaves_2_awregion;
// value method v_to_slaves_2_m_awuser
// action method v_to_slaves_2_m_awready
input v_to_slaves_2_awready;
// value method v_to_slaves_2_m_wvalid
output v_to_slaves_2_wvalid;
// value method v_to_slaves_2_m_wdata
output [63 : 0] v_to_slaves_2_wdata;
// value method v_to_slaves_2_m_wstrb
output [7 : 0] v_to_slaves_2_wstrb;
// value method v_to_slaves_2_m_wlast
output v_to_slaves_2_wlast;
// value method v_to_slaves_2_m_wuser
// action method v_to_slaves_2_m_wready
input v_to_slaves_2_wready;
// action method v_to_slaves_2_m_bvalid
input v_to_slaves_2_bvalid;
input [3 : 0] v_to_slaves_2_bid;
input [1 : 0] v_to_slaves_2_bresp;
// value method v_to_slaves_2_m_bready
output v_to_slaves_2_bready;
// value method v_to_slaves_2_m_arvalid
output v_to_slaves_2_arvalid;
// value method v_to_slaves_2_m_arid
output [3 : 0] v_to_slaves_2_arid;
// value method v_to_slaves_2_m_araddr
output [63 : 0] v_to_slaves_2_araddr;
// value method v_to_slaves_2_m_arlen
output [7 : 0] v_to_slaves_2_arlen;
// value method v_to_slaves_2_m_arsize
output [2 : 0] v_to_slaves_2_arsize;
// value method v_to_slaves_2_m_arburst
output [1 : 0] v_to_slaves_2_arburst;
// value method v_to_slaves_2_m_arlock
output v_to_slaves_2_arlock;
// value method v_to_slaves_2_m_arcache
output [3 : 0] v_to_slaves_2_arcache;
// value method v_to_slaves_2_m_arprot
output [2 : 0] v_to_slaves_2_arprot;
// value method v_to_slaves_2_m_arqos
output [3 : 0] v_to_slaves_2_arqos;
// value method v_to_slaves_2_m_arregion
output [3 : 0] v_to_slaves_2_arregion;
// value method v_to_slaves_2_m_aruser
// action method v_to_slaves_2_m_arready
input v_to_slaves_2_arready;
// action method v_to_slaves_2_m_rvalid
input v_to_slaves_2_rvalid;
input [3 : 0] v_to_slaves_2_rid;
input [63 : 0] v_to_slaves_2_rdata;
input [1 : 0] v_to_slaves_2_rresp;
input v_to_slaves_2_rlast;
// value method v_to_slaves_2_m_rready
output v_to_slaves_2_rready;
// signals for module outputs
wire [63 : 0] v_from_masters_0_rdata,
v_from_masters_1_rdata,
v_to_slaves_0_araddr,
v_to_slaves_0_awaddr,
v_to_slaves_0_wdata,
v_to_slaves_1_araddr,
v_to_slaves_1_awaddr,
v_to_slaves_1_wdata,
v_to_slaves_2_araddr,
v_to_slaves_2_awaddr,
v_to_slaves_2_wdata;
wire [7 : 0] v_to_slaves_0_arlen,
v_to_slaves_0_awlen,
v_to_slaves_0_wstrb,
v_to_slaves_1_arlen,
v_to_slaves_1_awlen,
v_to_slaves_1_wstrb,
v_to_slaves_2_arlen,
v_to_slaves_2_awlen,
v_to_slaves_2_wstrb;
wire [3 : 0] v_from_masters_0_bid,
v_from_masters_0_rid,
v_from_masters_1_bid,
v_from_masters_1_rid,
v_to_slaves_0_arcache,
v_to_slaves_0_arid,
v_to_slaves_0_arqos,
v_to_slaves_0_arregion,
v_to_slaves_0_awcache,
v_to_slaves_0_awid,
v_to_slaves_0_awqos,
v_to_slaves_0_awregion,
v_to_slaves_1_arcache,
v_to_slaves_1_arid,
v_to_slaves_1_arqos,
v_to_slaves_1_arregion,
v_to_slaves_1_awcache,
v_to_slaves_1_awid,
v_to_slaves_1_awqos,
v_to_slaves_1_awregion,
v_to_slaves_2_arcache,
v_to_slaves_2_arid,
v_to_slaves_2_arqos,
v_to_slaves_2_arregion,
v_to_slaves_2_awcache,
v_to_slaves_2_awid,
v_to_slaves_2_awqos,
v_to_slaves_2_awregion;
wire [2 : 0] v_to_slaves_0_arprot,
v_to_slaves_0_arsize,
v_to_slaves_0_awprot,
v_to_slaves_0_awsize,
v_to_slaves_1_arprot,
v_to_slaves_1_arsize,
v_to_slaves_1_awprot,
v_to_slaves_1_awsize,
v_to_slaves_2_arprot,
v_to_slaves_2_arsize,
v_to_slaves_2_awprot,
v_to_slaves_2_awsize;
wire [1 : 0] v_from_masters_0_bresp,
v_from_masters_0_rresp,
v_from_masters_1_bresp,
v_from_masters_1_rresp,
v_to_slaves_0_arburst,
v_to_slaves_0_awburst,
v_to_slaves_1_arburst,
v_to_slaves_1_awburst,
v_to_slaves_2_arburst,
v_to_slaves_2_awburst;
wire RDY_reset,
RDY_set_verbosity,
v_from_masters_0_arready,
v_from_masters_0_awready,
v_from_masters_0_bvalid,
v_from_masters_0_rlast,
v_from_masters_0_rvalid,
v_from_masters_0_wready,
v_from_masters_1_arready,
v_from_masters_1_awready,
v_from_masters_1_bvalid,
v_from_masters_1_rlast,
v_from_masters_1_rvalid,
v_from_masters_1_wready,
v_to_slaves_0_arlock,
v_to_slaves_0_arvalid,
v_to_slaves_0_awlock,
v_to_slaves_0_awvalid,
v_to_slaves_0_bready,
v_to_slaves_0_rready,
v_to_slaves_0_wlast,
v_to_slaves_0_wvalid,
v_to_slaves_1_arlock,
v_to_slaves_1_arvalid,
v_to_slaves_1_awlock,
v_to_slaves_1_awvalid,
v_to_slaves_1_bready,
v_to_slaves_1_rready,
v_to_slaves_1_wlast,
v_to_slaves_1_wvalid,
v_to_slaves_2_arlock,
v_to_slaves_2_arvalid,
v_to_slaves_2_awlock,
v_to_slaves_2_awvalid,
v_to_slaves_2_bready,
v_to_slaves_2_rready,
v_to_slaves_2_wlast,
v_to_slaves_2_wvalid;
// register fabric_cfg_verbosity
reg [3 : 0] fabric_cfg_verbosity;
wire [3 : 0] fabric_cfg_verbosity$D_IN;
wire fabric_cfg_verbosity$EN;
// register fabric_rg_reset
reg fabric_rg_reset;
wire fabric_rg_reset$D_IN, fabric_rg_reset$EN;
// register fabric_v_rg_r_beat_count_0
reg [7 : 0] fabric_v_rg_r_beat_count_0;
reg [7 : 0] fabric_v_rg_r_beat_count_0$D_IN;
wire fabric_v_rg_r_beat_count_0$EN;
// register fabric_v_rg_r_beat_count_1
reg [7 : 0] fabric_v_rg_r_beat_count_1;
reg [7 : 0] fabric_v_rg_r_beat_count_1$D_IN;
wire fabric_v_rg_r_beat_count_1$EN;
// register fabric_v_rg_r_beat_count_2
reg [7 : 0] fabric_v_rg_r_beat_count_2;
reg [7 : 0] fabric_v_rg_r_beat_count_2$D_IN;
wire fabric_v_rg_r_beat_count_2$EN;
// register fabric_v_rg_r_err_beat_count_0
reg [7 : 0] fabric_v_rg_r_err_beat_count_0;
wire [7 : 0] fabric_v_rg_r_err_beat_count_0$D_IN;
wire fabric_v_rg_r_err_beat_count_0$EN;
// register fabric_v_rg_r_err_beat_count_1
reg [7 : 0] fabric_v_rg_r_err_beat_count_1;
wire [7 : 0] fabric_v_rg_r_err_beat_count_1$D_IN;
wire fabric_v_rg_r_err_beat_count_1$EN;
// register fabric_v_rg_wd_beat_count_0
reg [7 : 0] fabric_v_rg_wd_beat_count_0;
wire [7 : 0] fabric_v_rg_wd_beat_count_0$D_IN;
wire fabric_v_rg_wd_beat_count_0$EN;
// register fabric_v_rg_wd_beat_count_1
reg [7 : 0] fabric_v_rg_wd_beat_count_1;
wire [7 : 0] fabric_v_rg_wd_beat_count_1$D_IN;
wire fabric_v_rg_wd_beat_count_1$EN;
// ports of submodule fabric_v_f_rd_err_info_0
wire [11 : 0] fabric_v_f_rd_err_info_0$D_IN, fabric_v_f_rd_err_info_0$D_OUT;
wire fabric_v_f_rd_err_info_0$CLR,
fabric_v_f_rd_err_info_0$DEQ,
fabric_v_f_rd_err_info_0$EMPTY_N,
fabric_v_f_rd_err_info_0$ENQ,
fabric_v_f_rd_err_info_0$FULL_N;
// ports of submodule fabric_v_f_rd_err_info_1
wire [11 : 0] fabric_v_f_rd_err_info_1$D_IN, fabric_v_f_rd_err_info_1$D_OUT;
wire fabric_v_f_rd_err_info_1$CLR,
fabric_v_f_rd_err_info_1$DEQ,
fabric_v_f_rd_err_info_1$EMPTY_N,
fabric_v_f_rd_err_info_1$ENQ,
fabric_v_f_rd_err_info_1$FULL_N;
// ports of submodule fabric_v_f_rd_mis_0
wire [8 : 0] fabric_v_f_rd_mis_0$D_IN, fabric_v_f_rd_mis_0$D_OUT;
wire fabric_v_f_rd_mis_0$CLR,
fabric_v_f_rd_mis_0$DEQ,
fabric_v_f_rd_mis_0$EMPTY_N,
fabric_v_f_rd_mis_0$ENQ,
fabric_v_f_rd_mis_0$FULL_N;
// ports of submodule fabric_v_f_rd_mis_1
wire [8 : 0] fabric_v_f_rd_mis_1$D_IN, fabric_v_f_rd_mis_1$D_OUT;
wire fabric_v_f_rd_mis_1$CLR,
fabric_v_f_rd_mis_1$DEQ,
fabric_v_f_rd_mis_1$EMPTY_N,
fabric_v_f_rd_mis_1$ENQ,
fabric_v_f_rd_mis_1$FULL_N;
// ports of submodule fabric_v_f_rd_mis_2
wire [8 : 0] fabric_v_f_rd_mis_2$D_IN, fabric_v_f_rd_mis_2$D_OUT;
wire fabric_v_f_rd_mis_2$CLR,
fabric_v_f_rd_mis_2$DEQ,
fabric_v_f_rd_mis_2$EMPTY_N,
fabric_v_f_rd_mis_2$ENQ,
fabric_v_f_rd_mis_2$FULL_N;
// ports of submodule fabric_v_f_rd_sjs_0
reg [1 : 0] fabric_v_f_rd_sjs_0$D_IN;
wire [1 : 0] fabric_v_f_rd_sjs_0$D_OUT;
wire fabric_v_f_rd_sjs_0$CLR,
fabric_v_f_rd_sjs_0$DEQ,
fabric_v_f_rd_sjs_0$EMPTY_N,
fabric_v_f_rd_sjs_0$ENQ,
fabric_v_f_rd_sjs_0$FULL_N;
// ports of submodule fabric_v_f_rd_sjs_1
reg [1 : 0] fabric_v_f_rd_sjs_1$D_IN;
wire [1 : 0] fabric_v_f_rd_sjs_1$D_OUT;
wire fabric_v_f_rd_sjs_1$CLR,
fabric_v_f_rd_sjs_1$DEQ,
fabric_v_f_rd_sjs_1$EMPTY_N,
fabric_v_f_rd_sjs_1$ENQ,
fabric_v_f_rd_sjs_1$FULL_N;
// ports of submodule fabric_v_f_wd_tasks_0
reg [9 : 0] fabric_v_f_wd_tasks_0$D_IN;
wire [9 : 0] fabric_v_f_wd_tasks_0$D_OUT;
wire fabric_v_f_wd_tasks_0$CLR,
fabric_v_f_wd_tasks_0$DEQ,
fabric_v_f_wd_tasks_0$EMPTY_N,
fabric_v_f_wd_tasks_0$ENQ,
fabric_v_f_wd_tasks_0$FULL_N;
// ports of submodule fabric_v_f_wd_tasks_1
reg [9 : 0] fabric_v_f_wd_tasks_1$D_IN;
wire [9 : 0] fabric_v_f_wd_tasks_1$D_OUT;
wire fabric_v_f_wd_tasks_1$CLR,
fabric_v_f_wd_tasks_1$DEQ,
fabric_v_f_wd_tasks_1$EMPTY_N,
fabric_v_f_wd_tasks_1$ENQ,
fabric_v_f_wd_tasks_1$FULL_N;
// ports of submodule fabric_v_f_wr_err_info_0
wire [3 : 0] fabric_v_f_wr_err_info_0$D_IN, fabric_v_f_wr_err_info_0$D_OUT;
wire fabric_v_f_wr_err_info_0$CLR,
fabric_v_f_wr_err_info_0$DEQ,
fabric_v_f_wr_err_info_0$EMPTY_N,
fabric_v_f_wr_err_info_0$ENQ,
fabric_v_f_wr_err_info_0$FULL_N;
// ports of submodule fabric_v_f_wr_err_info_1
wire [3 : 0] fabric_v_f_wr_err_info_1$D_IN, fabric_v_f_wr_err_info_1$D_OUT;
wire fabric_v_f_wr_err_info_1$CLR,
fabric_v_f_wr_err_info_1$DEQ,
fabric_v_f_wr_err_info_1$EMPTY_N,
fabric_v_f_wr_err_info_1$ENQ,
fabric_v_f_wr_err_info_1$FULL_N;
// ports of submodule fabric_v_f_wr_mis_0
wire fabric_v_f_wr_mis_0$CLR,
fabric_v_f_wr_mis_0$DEQ,
fabric_v_f_wr_mis_0$D_IN,
fabric_v_f_wr_mis_0$D_OUT,
fabric_v_f_wr_mis_0$EMPTY_N,
fabric_v_f_wr_mis_0$ENQ,
fabric_v_f_wr_mis_0$FULL_N;
// ports of submodule fabric_v_f_wr_mis_1
wire fabric_v_f_wr_mis_1$CLR,
fabric_v_f_wr_mis_1$DEQ,
fabric_v_f_wr_mis_1$D_IN,
fabric_v_f_wr_mis_1$D_OUT,
fabric_v_f_wr_mis_1$EMPTY_N,
fabric_v_f_wr_mis_1$ENQ,
fabric_v_f_wr_mis_1$FULL_N;
// ports of submodule fabric_v_f_wr_mis_2
wire fabric_v_f_wr_mis_2$CLR,
fabric_v_f_wr_mis_2$DEQ,
fabric_v_f_wr_mis_2$D_IN,
fabric_v_f_wr_mis_2$D_OUT,
fabric_v_f_wr_mis_2$EMPTY_N,
fabric_v_f_wr_mis_2$ENQ,
fabric_v_f_wr_mis_2$FULL_N;
// ports of submodule fabric_v_f_wr_sjs_0
reg [1 : 0] fabric_v_f_wr_sjs_0$D_IN;
wire [1 : 0] fabric_v_f_wr_sjs_0$D_OUT;
wire fabric_v_f_wr_sjs_0$CLR,
fabric_v_f_wr_sjs_0$DEQ,
fabric_v_f_wr_sjs_0$EMPTY_N,
fabric_v_f_wr_sjs_0$ENQ,
fabric_v_f_wr_sjs_0$FULL_N;
// ports of submodule fabric_v_f_wr_sjs_1
reg [1 : 0] fabric_v_f_wr_sjs_1$D_IN;
wire [1 : 0] fabric_v_f_wr_sjs_1$D_OUT;
wire fabric_v_f_wr_sjs_1$CLR,
fabric_v_f_wr_sjs_1$DEQ,
fabric_v_f_wr_sjs_1$EMPTY_N,
fabric_v_f_wr_sjs_1$ENQ,
fabric_v_f_wr_sjs_1$FULL_N;
// ports of submodule fabric_xactors_from_masters_0_f_rd_addr
wire [96 : 0] fabric_xactors_from_masters_0_f_rd_addr$D_IN,
fabric_xactors_from_masters_0_f_rd_addr$D_OUT;
wire fabric_xactors_from_masters_0_f_rd_addr$CLR,
fabric_xactors_from_masters_0_f_rd_addr$DEQ,
fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N,
fabric_xactors_from_masters_0_f_rd_addr$ENQ,
fabric_xactors_from_masters_0_f_rd_addr$FULL_N;
// ports of submodule fabric_xactors_from_masters_0_f_rd_data
reg [70 : 0] fabric_xactors_from_masters_0_f_rd_data$D_IN;
wire [70 : 0] fabric_xactors_from_masters_0_f_rd_data$D_OUT;
wire fabric_xactors_from_masters_0_f_rd_data$CLR,
fabric_xactors_from_masters_0_f_rd_data$DEQ,
fabric_xactors_from_masters_0_f_rd_data$EMPTY_N,
fabric_xactors_from_masters_0_f_rd_data$ENQ,
fabric_xactors_from_masters_0_f_rd_data$FULL_N;
// ports of submodule fabric_xactors_from_masters_0_f_wr_addr
wire [96 : 0] fabric_xactors_from_masters_0_f_wr_addr$D_IN,
fabric_xactors_from_masters_0_f_wr_addr$D_OUT;
wire fabric_xactors_from_masters_0_f_wr_addr$CLR,
fabric_xactors_from_masters_0_f_wr_addr$DEQ,
fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N,
fabric_xactors_from_masters_0_f_wr_addr$ENQ,
fabric_xactors_from_masters_0_f_wr_addr$FULL_N;
// ports of submodule fabric_xactors_from_masters_0_f_wr_data
wire [72 : 0] fabric_xactors_from_masters_0_f_wr_data$D_IN,
fabric_xactors_from_masters_0_f_wr_data$D_OUT;
wire fabric_xactors_from_masters_0_f_wr_data$CLR,
fabric_xactors_from_masters_0_f_wr_data$DEQ,
fabric_xactors_from_masters_0_f_wr_data$EMPTY_N,
fabric_xactors_from_masters_0_f_wr_data$ENQ,
fabric_xactors_from_masters_0_f_wr_data$FULL_N;
// ports of submodule fabric_xactors_from_masters_0_f_wr_resp
reg [5 : 0] fabric_xactors_from_masters_0_f_wr_resp$D_IN;
wire [5 : 0] fabric_xactors_from_masters_0_f_wr_resp$D_OUT;
wire fabric_xactors_from_masters_0_f_wr_resp$CLR,
fabric_xactors_from_masters_0_f_wr_resp$DEQ,
fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N,
fabric_xactors_from_masters_0_f_wr_resp$ENQ,
fabric_xactors_from_masters_0_f_wr_resp$FULL_N;
// ports of submodule fabric_xactors_from_masters_1_f_rd_addr
wire [96 : 0] fabric_xactors_from_masters_1_f_rd_addr$D_IN,
fabric_xactors_from_masters_1_f_rd_addr$D_OUT;
wire fabric_xactors_from_masters_1_f_rd_addr$CLR,
fabric_xactors_from_masters_1_f_rd_addr$DEQ,
fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N,
fabric_xactors_from_masters_1_f_rd_addr$ENQ,
fabric_xactors_from_masters_1_f_rd_addr$FULL_N;
// ports of submodule fabric_xactors_from_masters_1_f_rd_data
reg [70 : 0] fabric_xactors_from_masters_1_f_rd_data$D_IN;
wire [70 : 0] fabric_xactors_from_masters_1_f_rd_data$D_OUT;
wire fabric_xactors_from_masters_1_f_rd_data$CLR,
fabric_xactors_from_masters_1_f_rd_data$DEQ,
fabric_xactors_from_masters_1_f_rd_data$EMPTY_N,
fabric_xactors_from_masters_1_f_rd_data$ENQ,
fabric_xactors_from_masters_1_f_rd_data$FULL_N;
// ports of submodule fabric_xactors_from_masters_1_f_wr_addr
wire [96 : 0] fabric_xactors_from_masters_1_f_wr_addr$D_IN,
fabric_xactors_from_masters_1_f_wr_addr$D_OUT;
wire fabric_xactors_from_masters_1_f_wr_addr$CLR,
fabric_xactors_from_masters_1_f_wr_addr$DEQ,
fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N,
fabric_xactors_from_masters_1_f_wr_addr$ENQ,
fabric_xactors_from_masters_1_f_wr_addr$FULL_N;
// ports of submodule fabric_xactors_from_masters_1_f_wr_data
wire [72 : 0] fabric_xactors_from_masters_1_f_wr_data$D_IN,
fabric_xactors_from_masters_1_f_wr_data$D_OUT;
wire fabric_xactors_from_masters_1_f_wr_data$CLR,
fabric_xactors_from_masters_1_f_wr_data$DEQ,
fabric_xactors_from_masters_1_f_wr_data$EMPTY_N,
fabric_xactors_from_masters_1_f_wr_data$ENQ,
fabric_xactors_from_masters_1_f_wr_data$FULL_N;
// ports of submodule fabric_xactors_from_masters_1_f_wr_resp
reg [5 : 0] fabric_xactors_from_masters_1_f_wr_resp$D_IN;
wire [5 : 0] fabric_xactors_from_masters_1_f_wr_resp$D_OUT;
wire fabric_xactors_from_masters_1_f_wr_resp$CLR,
fabric_xactors_from_masters_1_f_wr_resp$DEQ,
fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N,
fabric_xactors_from_masters_1_f_wr_resp$ENQ,
fabric_xactors_from_masters_1_f_wr_resp$FULL_N;
// ports of submodule fabric_xactors_to_slaves_0_f_rd_addr
wire [96 : 0] fabric_xactors_to_slaves_0_f_rd_addr$D_IN,
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT;
wire fabric_xactors_to_slaves_0_f_rd_addr$CLR,
fabric_xactors_to_slaves_0_f_rd_addr$DEQ,
fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N,
fabric_xactors_to_slaves_0_f_rd_addr$ENQ,
fabric_xactors_to_slaves_0_f_rd_addr$FULL_N;
// ports of submodule fabric_xactors_to_slaves_0_f_rd_data
wire [70 : 0] fabric_xactors_to_slaves_0_f_rd_data$D_IN,
fabric_xactors_to_slaves_0_f_rd_data$D_OUT;
wire fabric_xactors_to_slaves_0_f_rd_data$CLR,
fabric_xactors_to_slaves_0_f_rd_data$DEQ,
fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N,
fabric_xactors_to_slaves_0_f_rd_data$ENQ,
fabric_xactors_to_slaves_0_f_rd_data$FULL_N;
// ports of submodule fabric_xactors_to_slaves_0_f_wr_addr
wire [96 : 0] fabric_xactors_to_slaves_0_f_wr_addr$D_IN,
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT;
wire fabric_xactors_to_slaves_0_f_wr_addr$CLR,
fabric_xactors_to_slaves_0_f_wr_addr$DEQ,
fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N,
fabric_xactors_to_slaves_0_f_wr_addr$ENQ,
fabric_xactors_to_slaves_0_f_wr_addr$FULL_N;
// ports of submodule fabric_xactors_to_slaves_0_f_wr_data
wire [72 : 0] fabric_xactors_to_slaves_0_f_wr_data$D_IN,
fabric_xactors_to_slaves_0_f_wr_data$D_OUT;
wire fabric_xactors_to_slaves_0_f_wr_data$CLR,
fabric_xactors_to_slaves_0_f_wr_data$DEQ,
fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N,
fabric_xactors_to_slaves_0_f_wr_data$ENQ,
fabric_xactors_to_slaves_0_f_wr_data$FULL_N;
// ports of submodule fabric_xactors_to_slaves_0_f_wr_resp
wire [5 : 0] fabric_xactors_to_slaves_0_f_wr_resp$D_IN,
fabric_xactors_to_slaves_0_f_wr_resp$D_OUT;
wire fabric_xactors_to_slaves_0_f_wr_resp$CLR,
fabric_xactors_to_slaves_0_f_wr_resp$DEQ,
fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N,
fabric_xactors_to_slaves_0_f_wr_resp$ENQ,
fabric_xactors_to_slaves_0_f_wr_resp$FULL_N;
// ports of submodule fabric_xactors_to_slaves_1_f_rd_addr
wire [96 : 0] fabric_xactors_to_slaves_1_f_rd_addr$D_IN,
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT;
wire fabric_xactors_to_slaves_1_f_rd_addr$CLR,
fabric_xactors_to_slaves_1_f_rd_addr$DEQ,
fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N,
fabric_xactors_to_slaves_1_f_rd_addr$ENQ,
fabric_xactors_to_slaves_1_f_rd_addr$FULL_N;
// ports of submodule fabric_xactors_to_slaves_1_f_rd_data
wire [70 : 0] fabric_xactors_to_slaves_1_f_rd_data$D_IN,
fabric_xactors_to_slaves_1_f_rd_data$D_OUT;
wire fabric_xactors_to_slaves_1_f_rd_data$CLR,
fabric_xactors_to_slaves_1_f_rd_data$DEQ,
fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N,
fabric_xactors_to_slaves_1_f_rd_data$ENQ,
fabric_xactors_to_slaves_1_f_rd_data$FULL_N;
// ports of submodule fabric_xactors_to_slaves_1_f_wr_addr
wire [96 : 0] fabric_xactors_to_slaves_1_f_wr_addr$D_IN,
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT;
wire fabric_xactors_to_slaves_1_f_wr_addr$CLR,
fabric_xactors_to_slaves_1_f_wr_addr$DEQ,
fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N,
fabric_xactors_to_slaves_1_f_wr_addr$ENQ,
fabric_xactors_to_slaves_1_f_wr_addr$FULL_N;
// ports of submodule fabric_xactors_to_slaves_1_f_wr_data
wire [72 : 0] fabric_xactors_to_slaves_1_f_wr_data$D_IN,
fabric_xactors_to_slaves_1_f_wr_data$D_OUT;
wire fabric_xactors_to_slaves_1_f_wr_data$CLR,
fabric_xactors_to_slaves_1_f_wr_data$DEQ,
fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N,
fabric_xactors_to_slaves_1_f_wr_data$ENQ,
fabric_xactors_to_slaves_1_f_wr_data$FULL_N;
// ports of submodule fabric_xactors_to_slaves_1_f_wr_resp
wire [5 : 0] fabric_xactors_to_slaves_1_f_wr_resp$D_IN,
fabric_xactors_to_slaves_1_f_wr_resp$D_OUT;
wire fabric_xactors_to_slaves_1_f_wr_resp$CLR,
fabric_xactors_to_slaves_1_f_wr_resp$DEQ,
fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N,
fabric_xactors_to_slaves_1_f_wr_resp$ENQ,
fabric_xactors_to_slaves_1_f_wr_resp$FULL_N;
// ports of submodule fabric_xactors_to_slaves_2_f_rd_addr
wire [96 : 0] fabric_xactors_to_slaves_2_f_rd_addr$D_IN,
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT;
wire fabric_xactors_to_slaves_2_f_rd_addr$CLR,
fabric_xactors_to_slaves_2_f_rd_addr$DEQ,
fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N,
fabric_xactors_to_slaves_2_f_rd_addr$ENQ,
fabric_xactors_to_slaves_2_f_rd_addr$FULL_N;
// ports of submodule fabric_xactors_to_slaves_2_f_rd_data
wire [70 : 0] fabric_xactors_to_slaves_2_f_rd_data$D_IN,
fabric_xactors_to_slaves_2_f_rd_data$D_OUT;
wire fabric_xactors_to_slaves_2_f_rd_data$CLR,
fabric_xactors_to_slaves_2_f_rd_data$DEQ,
fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N,
fabric_xactors_to_slaves_2_f_rd_data$ENQ,
fabric_xactors_to_slaves_2_f_rd_data$FULL_N;
// ports of submodule fabric_xactors_to_slaves_2_f_wr_addr
wire [96 : 0] fabric_xactors_to_slaves_2_f_wr_addr$D_IN,
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT;
wire fabric_xactors_to_slaves_2_f_wr_addr$CLR,
fabric_xactors_to_slaves_2_f_wr_addr$DEQ,
fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N,
fabric_xactors_to_slaves_2_f_wr_addr$ENQ,
fabric_xactors_to_slaves_2_f_wr_addr$FULL_N;
// ports of submodule fabric_xactors_to_slaves_2_f_wr_data
wire [72 : 0] fabric_xactors_to_slaves_2_f_wr_data$D_IN,
fabric_xactors_to_slaves_2_f_wr_data$D_OUT;
wire fabric_xactors_to_slaves_2_f_wr_data$CLR,
fabric_xactors_to_slaves_2_f_wr_data$DEQ,
fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N,
fabric_xactors_to_slaves_2_f_wr_data$ENQ,
fabric_xactors_to_slaves_2_f_wr_data$FULL_N;
// ports of submodule fabric_xactors_to_slaves_2_f_wr_resp
wire [5 : 0] fabric_xactors_to_slaves_2_f_wr_resp$D_IN,
fabric_xactors_to_slaves_2_f_wr_resp$D_OUT;
wire fabric_xactors_to_slaves_2_f_wr_resp$CLR,
fabric_xactors_to_slaves_2_f_wr_resp$DEQ,
fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N,
fabric_xactors_to_slaves_2_f_wr_resp$ENQ,
fabric_xactors_to_slaves_2_f_wr_resp$FULL_N;
// ports of submodule soc_map
wire [63 : 0] soc_map$m_boot_rom_addr_base,
soc_map$m_boot_rom_addr_lim,
soc_map$m_is_IO_addr_addr,
soc_map$m_is_mem_addr_addr,
soc_map$m_is_near_mem_IO_addr_addr,
soc_map$m_mem0_controller_addr_base,
soc_map$m_mem0_controller_addr_lim,
soc_map$m_uart0_addr_base,
soc_map$m_uart0_addr_lim;
// rule scheduling signals
wire CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master,
CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1,
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master,
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1,
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2,
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3,
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4,
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5,
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave,
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1,
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2,
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3,
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4,
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5,
CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave,
CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1,
CAN_FIRE_RL_fabric_rl_reset,
CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master,
CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1,
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master,
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1,
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2,
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3,
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4,
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5,
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave,
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1,
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2,
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3,
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4,
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5,
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data,
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1,
CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave,
CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1,
CAN_FIRE_reset,
CAN_FIRE_set_verbosity,
CAN_FIRE_v_from_masters_0_m_arvalid,
CAN_FIRE_v_from_masters_0_m_awvalid,
CAN_FIRE_v_from_masters_0_m_bready,
CAN_FIRE_v_from_masters_0_m_rready,
CAN_FIRE_v_from_masters_0_m_wvalid,
CAN_FIRE_v_from_masters_1_m_arvalid,
CAN_FIRE_v_from_masters_1_m_awvalid,
CAN_FIRE_v_from_masters_1_m_bready,
CAN_FIRE_v_from_masters_1_m_rready,
CAN_FIRE_v_from_masters_1_m_wvalid,
CAN_FIRE_v_to_slaves_0_m_arready,
CAN_FIRE_v_to_slaves_0_m_awready,
CAN_FIRE_v_to_slaves_0_m_bvalid,
CAN_FIRE_v_to_slaves_0_m_rvalid,
CAN_FIRE_v_to_slaves_0_m_wready,
CAN_FIRE_v_to_slaves_1_m_arready,
CAN_FIRE_v_to_slaves_1_m_awready,
CAN_FIRE_v_to_slaves_1_m_bvalid,
CAN_FIRE_v_to_slaves_1_m_rvalid,
CAN_FIRE_v_to_slaves_1_m_wready,
CAN_FIRE_v_to_slaves_2_m_arready,
CAN_FIRE_v_to_slaves_2_m_awready,
CAN_FIRE_v_to_slaves_2_m_bvalid,
CAN_FIRE_v_to_slaves_2_m_rvalid,
CAN_FIRE_v_to_slaves_2_m_wready,
WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master,
WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1,
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master,
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1,
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2,
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3,
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4,
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5,
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave,
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1,
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2,
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3,
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4,
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5,
WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave,
WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1,
WILL_FIRE_RL_fabric_rl_reset,
WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master,
WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1,
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master,
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1,
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2,
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3,
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4,
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5,
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave,
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1,
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2,
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3,
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4,
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5,
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data,
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1,
WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave,
WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1,
WILL_FIRE_reset,
WILL_FIRE_set_verbosity,
WILL_FIRE_v_from_masters_0_m_arvalid,
WILL_FIRE_v_from_masters_0_m_awvalid,
WILL_FIRE_v_from_masters_0_m_bready,
WILL_FIRE_v_from_masters_0_m_rready,
WILL_FIRE_v_from_masters_0_m_wvalid,
WILL_FIRE_v_from_masters_1_m_arvalid,
WILL_FIRE_v_from_masters_1_m_awvalid,
WILL_FIRE_v_from_masters_1_m_bready,
WILL_FIRE_v_from_masters_1_m_rready,
WILL_FIRE_v_from_masters_1_m_wvalid,
WILL_FIRE_v_to_slaves_0_m_arready,
WILL_FIRE_v_to_slaves_0_m_awready,
WILL_FIRE_v_to_slaves_0_m_bvalid,
WILL_FIRE_v_to_slaves_0_m_rvalid,
WILL_FIRE_v_to_slaves_0_m_wready,
WILL_FIRE_v_to_slaves_1_m_arready,
WILL_FIRE_v_to_slaves_1_m_awready,
WILL_FIRE_v_to_slaves_1_m_bvalid,
WILL_FIRE_v_to_slaves_1_m_rvalid,
WILL_FIRE_v_to_slaves_1_m_wready,
WILL_FIRE_v_to_slaves_2_m_arready,
WILL_FIRE_v_to_slaves_2_m_awready,
WILL_FIRE_v_to_slaves_2_m_bvalid,
WILL_FIRE_v_to_slaves_2_m_rvalid,
WILL_FIRE_v_to_slaves_2_m_wready;
// inputs to muxes for submodule ports
wire [70 : 0] MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1,
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2,
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3,
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4,
MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4;
wire [9 : 0] MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1,
MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2,
MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3,
MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_4,
MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1,
MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2,
MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3,
MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_4;
wire [8 : 0] MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1,
MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2;
wire [7 : 0] MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2,
MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2,
MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2,
MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2,
MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2;
wire [5 : 0] MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4,
MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4;
wire MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1,
MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1,
MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1;
// declarations used by system tasks
// synopsys translate_off
reg [31 : 0] v__h8721;
reg [31 : 0] v__h9121;
reg [31 : 0] v__h9521;
reg [31 : 0] v__h9991;
reg [31 : 0] v__h10385;
reg [31 : 0] v__h10779;
reg [31 : 0] v__h11161;
reg [31 : 0] v__h11499;
reg [31 : 0] v__h11982;
reg [31 : 0] v__h12445;
reg [31 : 0] v__h12820;
reg [31 : 0] v__h13112;
reg [31 : 0] v__h13404;
reg [31 : 0] v__h13707;
reg [31 : 0] v__h13973;
reg [31 : 0] v__h14239;
reg [31 : 0] v__h14503;
reg [31 : 0] v__h14729;
reg [31 : 0] v__h15183;
reg [31 : 0] v__h15564;
reg [31 : 0] v__h15945;
reg [31 : 0] v__h16387;
reg [31 : 0] v__h16744;
reg [31 : 0] v__h17101;
reg [31 : 0] v__h17452;
reg [31 : 0] v__h17753;
reg [31 : 0] v__h18161;
reg [31 : 0] v__h18412;
reg [31 : 0] v__h18787;
reg [31 : 0] v__h19028;
reg [31 : 0] v__h19403;
reg [31 : 0] v__h19644;
reg [31 : 0] v__h20006;
reg [31 : 0] v__h20257;
reg [31 : 0] v__h20587;
reg [31 : 0] v__h20828;
reg [31 : 0] v__h21158;
reg [31 : 0] v__h21399;
reg [31 : 0] v__h21912;
reg [31 : 0] v__h22313;
reg [31 : 0] v__h5717;
reg [31 : 0] v__h5711;
reg [31 : 0] v__h8715;
reg [31 : 0] v__h9115;
reg [31 : 0] v__h9515;
reg [31 : 0] v__h9985;
reg [31 : 0] v__h10379;
reg [31 : 0] v__h10773;
reg [31 : 0] v__h11155;
reg [31 : 0] v__h11493;
reg [31 : 0] v__h11976;
reg [31 : 0] v__h12439;
reg [31 : 0] v__h12814;
reg [31 : 0] v__h13106;
reg [31 : 0] v__h13398;
reg [31 : 0] v__h13701;
reg [31 : 0] v__h13967;
reg [31 : 0] v__h14233;
reg [31 : 0] v__h14497;
reg [31 : 0] v__h14723;
reg [31 : 0] v__h15177;
reg [31 : 0] v__h15558;
reg [31 : 0] v__h15939;
reg [31 : 0] v__h16381;
reg [31 : 0] v__h16738;
reg [31 : 0] v__h17095;
reg [31 : 0] v__h17446;
reg [31 : 0] v__h17747;
reg [31 : 0] v__h18155;
reg [31 : 0] v__h18406;
reg [31 : 0] v__h18781;
reg [31 : 0] v__h19022;
reg [31 : 0] v__h19397;
reg [31 : 0] v__h19638;
reg [31 : 0] v__h20000;
reg [31 : 0] v__h20251;
reg [31 : 0] v__h20581;
reg [31 : 0] v__h20822;
reg [31 : 0] v__h21152;
reg [31 : 0] v__h21393;
reg [31 : 0] v__h21906;
reg [31 : 0] v__h22307;
// synopsys translate_on
// remaining internal signals
reg CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1,
CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2;
wire [7 : 0] x__h11887,
x__h12350,
x__h18298,
x__h18924,
x__h19540,
x__h21844,
x__h22245;
wire [1 : 0] IF_fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_ETC___d496,
IF_fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_ETC___d535,
IF_fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_ETC___d574,
IF_soc_map_m_mem0_controller_addr_base__6_ULE__ETC___d102,
IF_soc_map_m_mem0_controller_addr_base__6_ULE__ETC___d338,
IF_soc_map_m_mem0_controller_addr_base__6_ULE__ETC___d37,
IF_soc_map_m_mem0_controller_addr_base__6_ULE__ETC___d394,
x1_avValue_rresp__h18276,
x1_avValue_rresp__h18902,
x1_avValue_rresp__h19518;
wire NOT_soc_map_m_mem0_controller_addr_base__6_ULE_ETC___d148,
NOT_soc_map_m_mem0_controller_addr_base__6_ULE_ETC___d167,
NOT_soc_map_m_mem0_controller_addr_base__6_ULE_ETC___d437,
NOT_soc_map_m_mem0_controller_addr_base__6_ULE_ETC___d455,
_dor1fabric_v_f_rd_mis_0$EN_deq,
_dor1fabric_v_f_rd_mis_1$EN_deq,
_dor1fabric_v_f_rd_mis_2$EN_deq,
fabric_v_f_wd_tasks_0_i_notEmpty__73_AND_fabri_ETC___d182,
fabric_v_f_wd_tasks_1_i_notEmpty__01_AND_fabri_ETC___d207,
fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d469,
fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d509,
fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d548,
fabric_v_rg_r_err_beat_count_0_18_EQ_fabric_v__ETC___d620,
fabric_v_rg_r_err_beat_count_1_36_EQ_fabric_v__ETC___d638,
fabric_v_rg_wd_beat_count_0_88_EQ_fabric_v_f_w_ETC___d190,
fabric_v_rg_wd_beat_count_1_13_EQ_fabric_v_f_w_ETC___d215,
fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d326,
fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d329,
fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d332,
fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d21,
fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d26,
fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d31,
fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d382,
fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d385,
fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d388,
fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d90,
fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d93,
fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d96,
soc_map_m_boot_rom_addr_base__3_ULE_fabric_xac_ETC___d24,
soc_map_m_boot_rom_addr_base__3_ULE_fabric_xac_ETC___d328,
soc_map_m_boot_rom_addr_base__3_ULE_fabric_xac_ETC___d384,
soc_map_m_boot_rom_addr_base__3_ULE_fabric_xac_ETC___d92,
soc_map_m_mem0_controller_addr_base__6_ULE_fab_ETC___d19,
soc_map_m_mem0_controller_addr_base__6_ULE_fab_ETC___d325,
soc_map_m_mem0_controller_addr_base__6_ULE_fab_ETC___d335,
soc_map_m_mem0_controller_addr_base__6_ULE_fab_ETC___d34,
soc_map_m_mem0_controller_addr_base__6_ULE_fab_ETC___d381,
soc_map_m_mem0_controller_addr_base__6_ULE_fab_ETC___d391,
soc_map_m_mem0_controller_addr_base__6_ULE_fab_ETC___d89,
soc_map_m_mem0_controller_addr_base__6_ULE_fab_ETC___d99,
soc_map_m_uart0_addr_base__8_ULE_fabric_xactor_ETC___d29,
soc_map_m_uart0_addr_base__8_ULE_fabric_xactor_ETC___d331,
soc_map_m_uart0_addr_base__8_ULE_fabric_xactor_ETC___d387,
soc_map_m_uart0_addr_base__8_ULE_fabric_xactor_ETC___d95;
// action method reset
assign RDY_reset = !fabric_rg_reset ;
assign CAN_FIRE_reset = !fabric_rg_reset ;
assign WILL_FIRE_reset = EN_reset ;
// action method set_verbosity
assign RDY_set_verbosity = 1'd1 ;
assign CAN_FIRE_set_verbosity = 1'd1 ;
assign WILL_FIRE_set_verbosity = EN_set_verbosity ;
// action method v_from_masters_0_m_awvalid
assign CAN_FIRE_v_from_masters_0_m_awvalid = 1'd1 ;
assign WILL_FIRE_v_from_masters_0_m_awvalid = 1'd1 ;
// value method v_from_masters_0_m_awready
assign v_from_masters_0_awready =
fabric_xactors_from_masters_0_f_wr_addr$FULL_N ;
// action method v_from_masters_0_m_wvalid
assign CAN_FIRE_v_from_masters_0_m_wvalid = 1'd1 ;
assign WILL_FIRE_v_from_masters_0_m_wvalid = 1'd1 ;
// value method v_from_masters_0_m_wready
assign v_from_masters_0_wready =
fabric_xactors_from_masters_0_f_wr_data$FULL_N ;
// value method v_from_masters_0_m_bvalid
assign v_from_masters_0_bvalid =
fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N ;
// value method v_from_masters_0_m_bid
assign v_from_masters_0_bid =
fabric_xactors_from_masters_0_f_wr_resp$D_OUT[5:2] ;
// value method v_from_masters_0_m_bresp
assign v_from_masters_0_bresp =
fabric_xactors_from_masters_0_f_wr_resp$D_OUT[1:0] ;
// action method v_from_masters_0_m_bready
assign CAN_FIRE_v_from_masters_0_m_bready = 1'd1 ;
assign WILL_FIRE_v_from_masters_0_m_bready = 1'd1 ;
// action method v_from_masters_0_m_arvalid
assign CAN_FIRE_v_from_masters_0_m_arvalid = 1'd1 ;
assign WILL_FIRE_v_from_masters_0_m_arvalid = 1'd1 ;
// value method v_from_masters_0_m_arready
assign v_from_masters_0_arready =
fabric_xactors_from_masters_0_f_rd_addr$FULL_N ;
// value method v_from_masters_0_m_rvalid
assign v_from_masters_0_rvalid =
fabric_xactors_from_masters_0_f_rd_data$EMPTY_N ;
// value method v_from_masters_0_m_rid
assign v_from_masters_0_rid =
fabric_xactors_from_masters_0_f_rd_data$D_OUT[70:67] ;
// value method v_from_masters_0_m_rdata
assign v_from_masters_0_rdata =
fabric_xactors_from_masters_0_f_rd_data$D_OUT[66:3] ;
// value method v_from_masters_0_m_rresp
assign v_from_masters_0_rresp =
fabric_xactors_from_masters_0_f_rd_data$D_OUT[2:1] ;
// value method v_from_masters_0_m_rlast
assign v_from_masters_0_rlast =
fabric_xactors_from_masters_0_f_rd_data$D_OUT[0] ;
// action method v_from_masters_0_m_rready
assign CAN_FIRE_v_from_masters_0_m_rready = 1'd1 ;
assign WILL_FIRE_v_from_masters_0_m_rready = 1'd1 ;
// action method v_from_masters_1_m_awvalid
assign CAN_FIRE_v_from_masters_1_m_awvalid = 1'd1 ;
assign WILL_FIRE_v_from_masters_1_m_awvalid = 1'd1 ;
// value method v_from_masters_1_m_awready
assign v_from_masters_1_awready =
fabric_xactors_from_masters_1_f_wr_addr$FULL_N ;
// action method v_from_masters_1_m_wvalid
assign CAN_FIRE_v_from_masters_1_m_wvalid = 1'd1 ;
assign WILL_FIRE_v_from_masters_1_m_wvalid = 1'd1 ;
// value method v_from_masters_1_m_wready
assign v_from_masters_1_wready =
fabric_xactors_from_masters_1_f_wr_data$FULL_N ;
// value method v_from_masters_1_m_bvalid
assign v_from_masters_1_bvalid =
fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N ;
// value method v_from_masters_1_m_bid
assign v_from_masters_1_bid =
fabric_xactors_from_masters_1_f_wr_resp$D_OUT[5:2] ;
// value method v_from_masters_1_m_bresp
assign v_from_masters_1_bresp =
fabric_xactors_from_masters_1_f_wr_resp$D_OUT[1:0] ;
// action method v_from_masters_1_m_bready
assign CAN_FIRE_v_from_masters_1_m_bready = 1'd1 ;
assign WILL_FIRE_v_from_masters_1_m_bready = 1'd1 ;
// action method v_from_masters_1_m_arvalid
assign CAN_FIRE_v_from_masters_1_m_arvalid = 1'd1 ;
assign WILL_FIRE_v_from_masters_1_m_arvalid = 1'd1 ;
// value method v_from_masters_1_m_arready
assign v_from_masters_1_arready =
fabric_xactors_from_masters_1_f_rd_addr$FULL_N ;
// value method v_from_masters_1_m_rvalid
assign v_from_masters_1_rvalid =
fabric_xactors_from_masters_1_f_rd_data$EMPTY_N ;
// value method v_from_masters_1_m_rid
assign v_from_masters_1_rid =
fabric_xactors_from_masters_1_f_rd_data$D_OUT[70:67] ;
// value method v_from_masters_1_m_rdata
assign v_from_masters_1_rdata =
fabric_xactors_from_masters_1_f_rd_data$D_OUT[66:3] ;
// value method v_from_masters_1_m_rresp
assign v_from_masters_1_rresp =
fabric_xactors_from_masters_1_f_rd_data$D_OUT[2:1] ;
// value method v_from_masters_1_m_rlast
assign v_from_masters_1_rlast =
fabric_xactors_from_masters_1_f_rd_data$D_OUT[0] ;
// action method v_from_masters_1_m_rready
assign CAN_FIRE_v_from_masters_1_m_rready = 1'd1 ;
assign WILL_FIRE_v_from_masters_1_m_rready = 1'd1 ;
// value method v_to_slaves_0_m_awvalid
assign v_to_slaves_0_awvalid =
fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N ;
// value method v_to_slaves_0_m_awid
assign v_to_slaves_0_awid =
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[96:93] ;
// value method v_to_slaves_0_m_awaddr
assign v_to_slaves_0_awaddr =
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[92:29] ;
// value method v_to_slaves_0_m_awlen
assign v_to_slaves_0_awlen =
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[28:21] ;
// value method v_to_slaves_0_m_awsize
assign v_to_slaves_0_awsize =
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[20:18] ;
// value method v_to_slaves_0_m_awburst
assign v_to_slaves_0_awburst =
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[17:16] ;
// value method v_to_slaves_0_m_awlock
assign v_to_slaves_0_awlock =
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[15] ;
// value method v_to_slaves_0_m_awcache
assign v_to_slaves_0_awcache =
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[14:11] ;
// value method v_to_slaves_0_m_awprot
assign v_to_slaves_0_awprot =
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[10:8] ;
// value method v_to_slaves_0_m_awqos
assign v_to_slaves_0_awqos =
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[7:4] ;
// value method v_to_slaves_0_m_awregion
assign v_to_slaves_0_awregion =
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[3:0] ;
// action method v_to_slaves_0_m_awready
assign CAN_FIRE_v_to_slaves_0_m_awready = 1'd1 ;
assign WILL_FIRE_v_to_slaves_0_m_awready = 1'd1 ;
// value method v_to_slaves_0_m_wvalid
assign v_to_slaves_0_wvalid = fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N ;
// value method v_to_slaves_0_m_wdata
assign v_to_slaves_0_wdata =
fabric_xactors_to_slaves_0_f_wr_data$D_OUT[72:9] ;
// value method v_to_slaves_0_m_wstrb
assign v_to_slaves_0_wstrb =
fabric_xactors_to_slaves_0_f_wr_data$D_OUT[8:1] ;
// value method v_to_slaves_0_m_wlast
assign v_to_slaves_0_wlast = fabric_xactors_to_slaves_0_f_wr_data$D_OUT[0] ;
// action method v_to_slaves_0_m_wready
assign CAN_FIRE_v_to_slaves_0_m_wready = 1'd1 ;
assign WILL_FIRE_v_to_slaves_0_m_wready = 1'd1 ;
// action method v_to_slaves_0_m_bvalid
assign CAN_FIRE_v_to_slaves_0_m_bvalid = 1'd1 ;
assign WILL_FIRE_v_to_slaves_0_m_bvalid = 1'd1 ;
// value method v_to_slaves_0_m_bready
assign v_to_slaves_0_bready = fabric_xactors_to_slaves_0_f_wr_resp$FULL_N ;
// value method v_to_slaves_0_m_arvalid
assign v_to_slaves_0_arvalid =
fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N ;
// value method v_to_slaves_0_m_arid
assign v_to_slaves_0_arid =
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[96:93] ;
// value method v_to_slaves_0_m_araddr
assign v_to_slaves_0_araddr =
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[92:29] ;
// value method v_to_slaves_0_m_arlen
assign v_to_slaves_0_arlen =
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[28:21] ;
// value method v_to_slaves_0_m_arsize
assign v_to_slaves_0_arsize =
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[20:18] ;
// value method v_to_slaves_0_m_arburst
assign v_to_slaves_0_arburst =
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[17:16] ;
// value method v_to_slaves_0_m_arlock
assign v_to_slaves_0_arlock =
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[15] ;
// value method v_to_slaves_0_m_arcache
assign v_to_slaves_0_arcache =
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[14:11] ;
// value method v_to_slaves_0_m_arprot
assign v_to_slaves_0_arprot =
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[10:8] ;
// value method v_to_slaves_0_m_arqos
assign v_to_slaves_0_arqos =
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[7:4] ;
// value method v_to_slaves_0_m_arregion
assign v_to_slaves_0_arregion =
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[3:0] ;
// action method v_to_slaves_0_m_arready
assign CAN_FIRE_v_to_slaves_0_m_arready = 1'd1 ;
assign WILL_FIRE_v_to_slaves_0_m_arready = 1'd1 ;
// action method v_to_slaves_0_m_rvalid
assign CAN_FIRE_v_to_slaves_0_m_rvalid = 1'd1 ;
assign WILL_FIRE_v_to_slaves_0_m_rvalid = 1'd1 ;
// value method v_to_slaves_0_m_rready
assign v_to_slaves_0_rready = fabric_xactors_to_slaves_0_f_rd_data$FULL_N ;
// value method v_to_slaves_1_m_awvalid
assign v_to_slaves_1_awvalid =
fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N ;
// value method v_to_slaves_1_m_awid
assign v_to_slaves_1_awid =
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[96:93] ;
// value method v_to_slaves_1_m_awaddr
assign v_to_slaves_1_awaddr =
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[92:29] ;
// value method v_to_slaves_1_m_awlen
assign v_to_slaves_1_awlen =
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[28:21] ;
// value method v_to_slaves_1_m_awsize
assign v_to_slaves_1_awsize =
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[20:18] ;
// value method v_to_slaves_1_m_awburst
assign v_to_slaves_1_awburst =
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[17:16] ;
// value method v_to_slaves_1_m_awlock
assign v_to_slaves_1_awlock =
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[15] ;
// value method v_to_slaves_1_m_awcache
assign v_to_slaves_1_awcache =
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[14:11] ;
// value method v_to_slaves_1_m_awprot
assign v_to_slaves_1_awprot =
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[10:8] ;
// value method v_to_slaves_1_m_awqos
assign v_to_slaves_1_awqos =
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[7:4] ;
// value method v_to_slaves_1_m_awregion
assign v_to_slaves_1_awregion =
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[3:0] ;
// action method v_to_slaves_1_m_awready
assign CAN_FIRE_v_to_slaves_1_m_awready = 1'd1 ;
assign WILL_FIRE_v_to_slaves_1_m_awready = 1'd1 ;
// value method v_to_slaves_1_m_wvalid
assign v_to_slaves_1_wvalid = fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N ;
// value method v_to_slaves_1_m_wdata
assign v_to_slaves_1_wdata =
fabric_xactors_to_slaves_1_f_wr_data$D_OUT[72:9] ;
// value method v_to_slaves_1_m_wstrb
assign v_to_slaves_1_wstrb =
fabric_xactors_to_slaves_1_f_wr_data$D_OUT[8:1] ;
// value method v_to_slaves_1_m_wlast
assign v_to_slaves_1_wlast = fabric_xactors_to_slaves_1_f_wr_data$D_OUT[0] ;
// action method v_to_slaves_1_m_wready
assign CAN_FIRE_v_to_slaves_1_m_wready = 1'd1 ;
assign WILL_FIRE_v_to_slaves_1_m_wready = 1'd1 ;
// action method v_to_slaves_1_m_bvalid
assign CAN_FIRE_v_to_slaves_1_m_bvalid = 1'd1 ;
assign WILL_FIRE_v_to_slaves_1_m_bvalid = 1'd1 ;
// value method v_to_slaves_1_m_bready
assign v_to_slaves_1_bready = fabric_xactors_to_slaves_1_f_wr_resp$FULL_N ;
// value method v_to_slaves_1_m_arvalid
assign v_to_slaves_1_arvalid =
fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N ;
// value method v_to_slaves_1_m_arid
assign v_to_slaves_1_arid =
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[96:93] ;
// value method v_to_slaves_1_m_araddr
assign v_to_slaves_1_araddr =
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[92:29] ;
// value method v_to_slaves_1_m_arlen
assign v_to_slaves_1_arlen =
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[28:21] ;
// value method v_to_slaves_1_m_arsize
assign v_to_slaves_1_arsize =
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[20:18] ;
// value method v_to_slaves_1_m_arburst
assign v_to_slaves_1_arburst =
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[17:16] ;
// value method v_to_slaves_1_m_arlock
assign v_to_slaves_1_arlock =
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[15] ;
// value method v_to_slaves_1_m_arcache
assign v_to_slaves_1_arcache =
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[14:11] ;
// value method v_to_slaves_1_m_arprot
assign v_to_slaves_1_arprot =
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[10:8] ;
// value method v_to_slaves_1_m_arqos
assign v_to_slaves_1_arqos =
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[7:4] ;
// value method v_to_slaves_1_m_arregion
assign v_to_slaves_1_arregion =
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[3:0] ;
// action method v_to_slaves_1_m_arready
assign CAN_FIRE_v_to_slaves_1_m_arready = 1'd1 ;
assign WILL_FIRE_v_to_slaves_1_m_arready = 1'd1 ;
// action method v_to_slaves_1_m_rvalid
assign CAN_FIRE_v_to_slaves_1_m_rvalid = 1'd1 ;
assign WILL_FIRE_v_to_slaves_1_m_rvalid = 1'd1 ;
// value method v_to_slaves_1_m_rready
assign v_to_slaves_1_rready = fabric_xactors_to_slaves_1_f_rd_data$FULL_N ;
// value method v_to_slaves_2_m_awvalid
assign v_to_slaves_2_awvalid =
fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N ;
// value method v_to_slaves_2_m_awid
assign v_to_slaves_2_awid =
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[96:93] ;
// value method v_to_slaves_2_m_awaddr
assign v_to_slaves_2_awaddr =
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[92:29] ;
// value method v_to_slaves_2_m_awlen
assign v_to_slaves_2_awlen =
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[28:21] ;
// value method v_to_slaves_2_m_awsize
assign v_to_slaves_2_awsize =
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[20:18] ;
// value method v_to_slaves_2_m_awburst
assign v_to_slaves_2_awburst =
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[17:16] ;
// value method v_to_slaves_2_m_awlock
assign v_to_slaves_2_awlock =
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[15] ;
// value method v_to_slaves_2_m_awcache
assign v_to_slaves_2_awcache =
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[14:11] ;
// value method v_to_slaves_2_m_awprot
assign v_to_slaves_2_awprot =
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[10:8] ;
// value method v_to_slaves_2_m_awqos
assign v_to_slaves_2_awqos =
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[7:4] ;
// value method v_to_slaves_2_m_awregion
assign v_to_slaves_2_awregion =
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[3:0] ;
// action method v_to_slaves_2_m_awready
assign CAN_FIRE_v_to_slaves_2_m_awready = 1'd1 ;
assign WILL_FIRE_v_to_slaves_2_m_awready = 1'd1 ;
// value method v_to_slaves_2_m_wvalid
assign v_to_slaves_2_wvalid = fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N ;
// value method v_to_slaves_2_m_wdata
assign v_to_slaves_2_wdata =
fabric_xactors_to_slaves_2_f_wr_data$D_OUT[72:9] ;
// value method v_to_slaves_2_m_wstrb
assign v_to_slaves_2_wstrb =
fabric_xactors_to_slaves_2_f_wr_data$D_OUT[8:1] ;
// value method v_to_slaves_2_m_wlast
assign v_to_slaves_2_wlast = fabric_xactors_to_slaves_2_f_wr_data$D_OUT[0] ;
// action method v_to_slaves_2_m_wready
assign CAN_FIRE_v_to_slaves_2_m_wready = 1'd1 ;
assign WILL_FIRE_v_to_slaves_2_m_wready = 1'd1 ;
// action method v_to_slaves_2_m_bvalid
assign CAN_FIRE_v_to_slaves_2_m_bvalid = 1'd1 ;
assign WILL_FIRE_v_to_slaves_2_m_bvalid = 1'd1 ;
// value method v_to_slaves_2_m_bready
assign v_to_slaves_2_bready = fabric_xactors_to_slaves_2_f_wr_resp$FULL_N ;
// value method v_to_slaves_2_m_arvalid
assign v_to_slaves_2_arvalid =
fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N ;
// value method v_to_slaves_2_m_arid
assign v_to_slaves_2_arid =
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[96:93] ;
// value method v_to_slaves_2_m_araddr
assign v_to_slaves_2_araddr =
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[92:29] ;
// value method v_to_slaves_2_m_arlen
assign v_to_slaves_2_arlen =
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[28:21] ;
// value method v_to_slaves_2_m_arsize
assign v_to_slaves_2_arsize =
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[20:18] ;
// value method v_to_slaves_2_m_arburst
assign v_to_slaves_2_arburst =
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[17:16] ;
// value method v_to_slaves_2_m_arlock
assign v_to_slaves_2_arlock =
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[15] ;
// value method v_to_slaves_2_m_arcache
assign v_to_slaves_2_arcache =
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[14:11] ;
// value method v_to_slaves_2_m_arprot
assign v_to_slaves_2_arprot =
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[10:8] ;
// value method v_to_slaves_2_m_arqos
assign v_to_slaves_2_arqos =
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[7:4] ;
// value method v_to_slaves_2_m_arregion
assign v_to_slaves_2_arregion =
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[3:0] ;
// action method v_to_slaves_2_m_arready
assign CAN_FIRE_v_to_slaves_2_m_arready = 1'd1 ;
assign WILL_FIRE_v_to_slaves_2_m_arready = 1'd1 ;
// action method v_to_slaves_2_m_rvalid
assign CAN_FIRE_v_to_slaves_2_m_rvalid = 1'd1 ;
assign WILL_FIRE_v_to_slaves_2_m_rvalid = 1'd1 ;
// value method v_to_slaves_2_m_rready
assign v_to_slaves_2_rready = fabric_xactors_to_slaves_2_f_rd_data$FULL_N ;
// submodule fabric_v_f_rd_err_info_0
SizedFIFO #(.p1width(32'd12),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(32'd1)) fabric_v_f_rd_err_info_0(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_rd_err_info_0$D_IN),
.ENQ(fabric_v_f_rd_err_info_0$ENQ),
.DEQ(fabric_v_f_rd_err_info_0$DEQ),
.CLR(fabric_v_f_rd_err_info_0$CLR),
.D_OUT(fabric_v_f_rd_err_info_0$D_OUT),
.FULL_N(fabric_v_f_rd_err_info_0$FULL_N),
.EMPTY_N(fabric_v_f_rd_err_info_0$EMPTY_N));
// submodule fabric_v_f_rd_err_info_1
SizedFIFO #(.p1width(32'd12),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(32'd1)) fabric_v_f_rd_err_info_1(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_rd_err_info_1$D_IN),
.ENQ(fabric_v_f_rd_err_info_1$ENQ),
.DEQ(fabric_v_f_rd_err_info_1$DEQ),
.CLR(fabric_v_f_rd_err_info_1$CLR),
.D_OUT(fabric_v_f_rd_err_info_1$D_OUT),
.FULL_N(fabric_v_f_rd_err_info_1$FULL_N),
.EMPTY_N(fabric_v_f_rd_err_info_1$EMPTY_N));
// submodule fabric_v_f_rd_mis_0
SizedFIFO #(.p1width(32'd9),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(32'd1)) fabric_v_f_rd_mis_0(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_rd_mis_0$D_IN),
.ENQ(fabric_v_f_rd_mis_0$ENQ),
.DEQ(fabric_v_f_rd_mis_0$DEQ),
.CLR(fabric_v_f_rd_mis_0$CLR),
.D_OUT(fabric_v_f_rd_mis_0$D_OUT),
.FULL_N(fabric_v_f_rd_mis_0$FULL_N),
.EMPTY_N(fabric_v_f_rd_mis_0$EMPTY_N));
// submodule fabric_v_f_rd_mis_1
SizedFIFO #(.p1width(32'd9),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(32'd1)) fabric_v_f_rd_mis_1(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_rd_mis_1$D_IN),
.ENQ(fabric_v_f_rd_mis_1$ENQ),
.DEQ(fabric_v_f_rd_mis_1$DEQ),
.CLR(fabric_v_f_rd_mis_1$CLR),
.D_OUT(fabric_v_f_rd_mis_1$D_OUT),
.FULL_N(fabric_v_f_rd_mis_1$FULL_N),
.EMPTY_N(fabric_v_f_rd_mis_1$EMPTY_N));
// submodule fabric_v_f_rd_mis_2
SizedFIFO #(.p1width(32'd9),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(32'd1)) fabric_v_f_rd_mis_2(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_rd_mis_2$D_IN),
.ENQ(fabric_v_f_rd_mis_2$ENQ),
.DEQ(fabric_v_f_rd_mis_2$DEQ),
.CLR(fabric_v_f_rd_mis_2$CLR),
.D_OUT(fabric_v_f_rd_mis_2$D_OUT),
.FULL_N(fabric_v_f_rd_mis_2$FULL_N),
.EMPTY_N(fabric_v_f_rd_mis_2$EMPTY_N));
// submodule fabric_v_f_rd_sjs_0
SizedFIFO #(.p1width(32'd2),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(32'd1)) fabric_v_f_rd_sjs_0(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_rd_sjs_0$D_IN),
.ENQ(fabric_v_f_rd_sjs_0$ENQ),
.DEQ(fabric_v_f_rd_sjs_0$DEQ),
.CLR(fabric_v_f_rd_sjs_0$CLR),
.D_OUT(fabric_v_f_rd_sjs_0$D_OUT),
.FULL_N(fabric_v_f_rd_sjs_0$FULL_N),
.EMPTY_N(fabric_v_f_rd_sjs_0$EMPTY_N));
// submodule fabric_v_f_rd_sjs_1
SizedFIFO #(.p1width(32'd2),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(32'd1)) fabric_v_f_rd_sjs_1(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_rd_sjs_1$D_IN),
.ENQ(fabric_v_f_rd_sjs_1$ENQ),
.DEQ(fabric_v_f_rd_sjs_1$DEQ),
.CLR(fabric_v_f_rd_sjs_1$CLR),
.D_OUT(fabric_v_f_rd_sjs_1$D_OUT),
.FULL_N(fabric_v_f_rd_sjs_1$FULL_N),
.EMPTY_N(fabric_v_f_rd_sjs_1$EMPTY_N));
// submodule fabric_v_f_wd_tasks_0
FIFO2 #(.width(32'd10), .guarded(32'd1)) fabric_v_f_wd_tasks_0(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_wd_tasks_0$D_IN),
.ENQ(fabric_v_f_wd_tasks_0$ENQ),
.DEQ(fabric_v_f_wd_tasks_0$DEQ),
.CLR(fabric_v_f_wd_tasks_0$CLR),
.D_OUT(fabric_v_f_wd_tasks_0$D_OUT),
.FULL_N(fabric_v_f_wd_tasks_0$FULL_N),
.EMPTY_N(fabric_v_f_wd_tasks_0$EMPTY_N));
// submodule fabric_v_f_wd_tasks_1
FIFO2 #(.width(32'd10), .guarded(32'd1)) fabric_v_f_wd_tasks_1(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_wd_tasks_1$D_IN),
.ENQ(fabric_v_f_wd_tasks_1$ENQ),
.DEQ(fabric_v_f_wd_tasks_1$DEQ),
.CLR(fabric_v_f_wd_tasks_1$CLR),
.D_OUT(fabric_v_f_wd_tasks_1$D_OUT),
.FULL_N(fabric_v_f_wd_tasks_1$FULL_N),
.EMPTY_N(fabric_v_f_wd_tasks_1$EMPTY_N));
// submodule fabric_v_f_wr_err_info_0
SizedFIFO #(.p1width(32'd4),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(32'd1)) fabric_v_f_wr_err_info_0(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_wr_err_info_0$D_IN),
.ENQ(fabric_v_f_wr_err_info_0$ENQ),
.DEQ(fabric_v_f_wr_err_info_0$DEQ),
.CLR(fabric_v_f_wr_err_info_0$CLR),
.D_OUT(fabric_v_f_wr_err_info_0$D_OUT),
.FULL_N(fabric_v_f_wr_err_info_0$FULL_N),
.EMPTY_N(fabric_v_f_wr_err_info_0$EMPTY_N));
// submodule fabric_v_f_wr_err_info_1
SizedFIFO #(.p1width(32'd4),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(32'd1)) fabric_v_f_wr_err_info_1(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_wr_err_info_1$D_IN),
.ENQ(fabric_v_f_wr_err_info_1$ENQ),
.DEQ(fabric_v_f_wr_err_info_1$DEQ),
.CLR(fabric_v_f_wr_err_info_1$CLR),
.D_OUT(fabric_v_f_wr_err_info_1$D_OUT),
.FULL_N(fabric_v_f_wr_err_info_1$FULL_N),
.EMPTY_N(fabric_v_f_wr_err_info_1$EMPTY_N));
// submodule fabric_v_f_wr_mis_0
SizedFIFO #(.p1width(32'd1),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(32'd1)) fabric_v_f_wr_mis_0(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_wr_mis_0$D_IN),
.ENQ(fabric_v_f_wr_mis_0$ENQ),
.DEQ(fabric_v_f_wr_mis_0$DEQ),
.CLR(fabric_v_f_wr_mis_0$CLR),
.D_OUT(fabric_v_f_wr_mis_0$D_OUT),
.FULL_N(fabric_v_f_wr_mis_0$FULL_N),
.EMPTY_N(fabric_v_f_wr_mis_0$EMPTY_N));
// submodule fabric_v_f_wr_mis_1
SizedFIFO #(.p1width(32'd1),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(32'd1)) fabric_v_f_wr_mis_1(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_wr_mis_1$D_IN),
.ENQ(fabric_v_f_wr_mis_1$ENQ),
.DEQ(fabric_v_f_wr_mis_1$DEQ),
.CLR(fabric_v_f_wr_mis_1$CLR),
.D_OUT(fabric_v_f_wr_mis_1$D_OUT),
.FULL_N(fabric_v_f_wr_mis_1$FULL_N),
.EMPTY_N(fabric_v_f_wr_mis_1$EMPTY_N));
// submodule fabric_v_f_wr_mis_2
SizedFIFO #(.p1width(32'd1),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(32'd1)) fabric_v_f_wr_mis_2(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_wr_mis_2$D_IN),
.ENQ(fabric_v_f_wr_mis_2$ENQ),
.DEQ(fabric_v_f_wr_mis_2$DEQ),
.CLR(fabric_v_f_wr_mis_2$CLR),
.D_OUT(fabric_v_f_wr_mis_2$D_OUT),
.FULL_N(fabric_v_f_wr_mis_2$FULL_N),
.EMPTY_N(fabric_v_f_wr_mis_2$EMPTY_N));
// submodule fabric_v_f_wr_sjs_0
SizedFIFO #(.p1width(32'd2),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(32'd1)) fabric_v_f_wr_sjs_0(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_wr_sjs_0$D_IN),
.ENQ(fabric_v_f_wr_sjs_0$ENQ),
.DEQ(fabric_v_f_wr_sjs_0$DEQ),
.CLR(fabric_v_f_wr_sjs_0$CLR),
.D_OUT(fabric_v_f_wr_sjs_0$D_OUT),
.FULL_N(fabric_v_f_wr_sjs_0$FULL_N),
.EMPTY_N(fabric_v_f_wr_sjs_0$EMPTY_N));
// submodule fabric_v_f_wr_sjs_1
SizedFIFO #(.p1width(32'd2),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(32'd1)) fabric_v_f_wr_sjs_1(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_wr_sjs_1$D_IN),
.ENQ(fabric_v_f_wr_sjs_1$ENQ),
.DEQ(fabric_v_f_wr_sjs_1$DEQ),
.CLR(fabric_v_f_wr_sjs_1$CLR),
.D_OUT(fabric_v_f_wr_sjs_1$D_OUT),
.FULL_N(fabric_v_f_wr_sjs_1$FULL_N),
.EMPTY_N(fabric_v_f_wr_sjs_1$EMPTY_N));
// submodule fabric_xactors_from_masters_0_f_rd_addr
FIFO2 #(.width(32'd97),
.guarded(32'd1)) fabric_xactors_from_masters_0_f_rd_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_from_masters_0_f_rd_addr$D_IN),
.ENQ(fabric_xactors_from_masters_0_f_rd_addr$ENQ),
.DEQ(fabric_xactors_from_masters_0_f_rd_addr$DEQ),
.CLR(fabric_xactors_from_masters_0_f_rd_addr$CLR),
.D_OUT(fabric_xactors_from_masters_0_f_rd_addr$D_OUT),
.FULL_N(fabric_xactors_from_masters_0_f_rd_addr$FULL_N),
.EMPTY_N(fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N));
// submodule fabric_xactors_from_masters_0_f_rd_data
FIFO2 #(.width(32'd71),
.guarded(32'd1)) fabric_xactors_from_masters_0_f_rd_data(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_from_masters_0_f_rd_data$D_IN),
.ENQ(fabric_xactors_from_masters_0_f_rd_data$ENQ),
.DEQ(fabric_xactors_from_masters_0_f_rd_data$DEQ),
.CLR(fabric_xactors_from_masters_0_f_rd_data$CLR),
.D_OUT(fabric_xactors_from_masters_0_f_rd_data$D_OUT),
.FULL_N(fabric_xactors_from_masters_0_f_rd_data$FULL_N),
.EMPTY_N(fabric_xactors_from_masters_0_f_rd_data$EMPTY_N));
// submodule fabric_xactors_from_masters_0_f_wr_addr
FIFO2 #(.width(32'd97),
.guarded(32'd1)) fabric_xactors_from_masters_0_f_wr_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_from_masters_0_f_wr_addr$D_IN),
.ENQ(fabric_xactors_from_masters_0_f_wr_addr$ENQ),
.DEQ(fabric_xactors_from_masters_0_f_wr_addr$DEQ),
.CLR(fabric_xactors_from_masters_0_f_wr_addr$CLR),
.D_OUT(fabric_xactors_from_masters_0_f_wr_addr$D_OUT),
.FULL_N(fabric_xactors_from_masters_0_f_wr_addr$FULL_N),
.EMPTY_N(fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N));
// submodule fabric_xactors_from_masters_0_f_wr_data
FIFO2 #(.width(32'd73),
.guarded(32'd1)) fabric_xactors_from_masters_0_f_wr_data(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_from_masters_0_f_wr_data$D_IN),
.ENQ(fabric_xactors_from_masters_0_f_wr_data$ENQ),
.DEQ(fabric_xactors_from_masters_0_f_wr_data$DEQ),
.CLR(fabric_xactors_from_masters_0_f_wr_data$CLR),
.D_OUT(fabric_xactors_from_masters_0_f_wr_data$D_OUT),
.FULL_N(fabric_xactors_from_masters_0_f_wr_data$FULL_N),
.EMPTY_N(fabric_xactors_from_masters_0_f_wr_data$EMPTY_N));
// submodule fabric_xactors_from_masters_0_f_wr_resp
FIFO2 #(.width(32'd6),
.guarded(32'd1)) fabric_xactors_from_masters_0_f_wr_resp(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_from_masters_0_f_wr_resp$D_IN),
.ENQ(fabric_xactors_from_masters_0_f_wr_resp$ENQ),
.DEQ(fabric_xactors_from_masters_0_f_wr_resp$DEQ),
.CLR(fabric_xactors_from_masters_0_f_wr_resp$CLR),
.D_OUT(fabric_xactors_from_masters_0_f_wr_resp$D_OUT),
.FULL_N(fabric_xactors_from_masters_0_f_wr_resp$FULL_N),
.EMPTY_N(fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N));
// submodule fabric_xactors_from_masters_1_f_rd_addr
FIFO2 #(.width(32'd97),
.guarded(32'd1)) fabric_xactors_from_masters_1_f_rd_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_from_masters_1_f_rd_addr$D_IN),
.ENQ(fabric_xactors_from_masters_1_f_rd_addr$ENQ),
.DEQ(fabric_xactors_from_masters_1_f_rd_addr$DEQ),
.CLR(fabric_xactors_from_masters_1_f_rd_addr$CLR),
.D_OUT(fabric_xactors_from_masters_1_f_rd_addr$D_OUT),
.FULL_N(fabric_xactors_from_masters_1_f_rd_addr$FULL_N),
.EMPTY_N(fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N));
// submodule fabric_xactors_from_masters_1_f_rd_data
FIFO2 #(.width(32'd71),
.guarded(32'd1)) fabric_xactors_from_masters_1_f_rd_data(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_from_masters_1_f_rd_data$D_IN),
.ENQ(fabric_xactors_from_masters_1_f_rd_data$ENQ),
.DEQ(fabric_xactors_from_masters_1_f_rd_data$DEQ),
.CLR(fabric_xactors_from_masters_1_f_rd_data$CLR),
.D_OUT(fabric_xactors_from_masters_1_f_rd_data$D_OUT),
.FULL_N(fabric_xactors_from_masters_1_f_rd_data$FULL_N),
.EMPTY_N(fabric_xactors_from_masters_1_f_rd_data$EMPTY_N));
// submodule fabric_xactors_from_masters_1_f_wr_addr
FIFO2 #(.width(32'd97),
.guarded(32'd1)) fabric_xactors_from_masters_1_f_wr_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_from_masters_1_f_wr_addr$D_IN),
.ENQ(fabric_xactors_from_masters_1_f_wr_addr$ENQ),
.DEQ(fabric_xactors_from_masters_1_f_wr_addr$DEQ),
.CLR(fabric_xactors_from_masters_1_f_wr_addr$CLR),
.D_OUT(fabric_xactors_from_masters_1_f_wr_addr$D_OUT),
.FULL_N(fabric_xactors_from_masters_1_f_wr_addr$FULL_N),
.EMPTY_N(fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N));
// submodule fabric_xactors_from_masters_1_f_wr_data
FIFO2 #(.width(32'd73),
.guarded(32'd1)) fabric_xactors_from_masters_1_f_wr_data(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_from_masters_1_f_wr_data$D_IN),
.ENQ(fabric_xactors_from_masters_1_f_wr_data$ENQ),
.DEQ(fabric_xactors_from_masters_1_f_wr_data$DEQ),
.CLR(fabric_xactors_from_masters_1_f_wr_data$CLR),
.D_OUT(fabric_xactors_from_masters_1_f_wr_data$D_OUT),
.FULL_N(fabric_xactors_from_masters_1_f_wr_data$FULL_N),
.EMPTY_N(fabric_xactors_from_masters_1_f_wr_data$EMPTY_N));
// submodule fabric_xactors_from_masters_1_f_wr_resp
FIFO2 #(.width(32'd6),
.guarded(32'd1)) fabric_xactors_from_masters_1_f_wr_resp(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_from_masters_1_f_wr_resp$D_IN),
.ENQ(fabric_xactors_from_masters_1_f_wr_resp$ENQ),
.DEQ(fabric_xactors_from_masters_1_f_wr_resp$DEQ),
.CLR(fabric_xactors_from_masters_1_f_wr_resp$CLR),
.D_OUT(fabric_xactors_from_masters_1_f_wr_resp$D_OUT),
.FULL_N(fabric_xactors_from_masters_1_f_wr_resp$FULL_N),
.EMPTY_N(fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N));
// submodule fabric_xactors_to_slaves_0_f_rd_addr
FIFO2 #(.width(32'd97),
.guarded(32'd1)) fabric_xactors_to_slaves_0_f_rd_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_0_f_rd_addr$D_IN),
.ENQ(fabric_xactors_to_slaves_0_f_rd_addr$ENQ),
.DEQ(fabric_xactors_to_slaves_0_f_rd_addr$DEQ),
.CLR(fabric_xactors_to_slaves_0_f_rd_addr$CLR),
.D_OUT(fabric_xactors_to_slaves_0_f_rd_addr$D_OUT),
.FULL_N(fabric_xactors_to_slaves_0_f_rd_addr$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N));
// submodule fabric_xactors_to_slaves_0_f_rd_data
FIFO2 #(.width(32'd71),
.guarded(32'd1)) fabric_xactors_to_slaves_0_f_rd_data(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_0_f_rd_data$D_IN),
.ENQ(fabric_xactors_to_slaves_0_f_rd_data$ENQ),
.DEQ(fabric_xactors_to_slaves_0_f_rd_data$DEQ),
.CLR(fabric_xactors_to_slaves_0_f_rd_data$CLR),
.D_OUT(fabric_xactors_to_slaves_0_f_rd_data$D_OUT),
.FULL_N(fabric_xactors_to_slaves_0_f_rd_data$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N));
// submodule fabric_xactors_to_slaves_0_f_wr_addr
FIFO2 #(.width(32'd97),
.guarded(32'd1)) fabric_xactors_to_slaves_0_f_wr_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_0_f_wr_addr$D_IN),
.ENQ(fabric_xactors_to_slaves_0_f_wr_addr$ENQ),
.DEQ(fabric_xactors_to_slaves_0_f_wr_addr$DEQ),
.CLR(fabric_xactors_to_slaves_0_f_wr_addr$CLR),
.D_OUT(fabric_xactors_to_slaves_0_f_wr_addr$D_OUT),
.FULL_N(fabric_xactors_to_slaves_0_f_wr_addr$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N));
// submodule fabric_xactors_to_slaves_0_f_wr_data
FIFO2 #(.width(32'd73),
.guarded(32'd1)) fabric_xactors_to_slaves_0_f_wr_data(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_0_f_wr_data$D_IN),
.ENQ(fabric_xactors_to_slaves_0_f_wr_data$ENQ),
.DEQ(fabric_xactors_to_slaves_0_f_wr_data$DEQ),
.CLR(fabric_xactors_to_slaves_0_f_wr_data$CLR),
.D_OUT(fabric_xactors_to_slaves_0_f_wr_data$D_OUT),
.FULL_N(fabric_xactors_to_slaves_0_f_wr_data$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N));
// submodule fabric_xactors_to_slaves_0_f_wr_resp
FIFO2 #(.width(32'd6),
.guarded(32'd1)) fabric_xactors_to_slaves_0_f_wr_resp(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_0_f_wr_resp$D_IN),
.ENQ(fabric_xactors_to_slaves_0_f_wr_resp$ENQ),
.DEQ(fabric_xactors_to_slaves_0_f_wr_resp$DEQ),
.CLR(fabric_xactors_to_slaves_0_f_wr_resp$CLR),
.D_OUT(fabric_xactors_to_slaves_0_f_wr_resp$D_OUT),
.FULL_N(fabric_xactors_to_slaves_0_f_wr_resp$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N));
// submodule fabric_xactors_to_slaves_1_f_rd_addr
FIFO2 #(.width(32'd97),
.guarded(32'd1)) fabric_xactors_to_slaves_1_f_rd_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_1_f_rd_addr$D_IN),
.ENQ(fabric_xactors_to_slaves_1_f_rd_addr$ENQ),
.DEQ(fabric_xactors_to_slaves_1_f_rd_addr$DEQ),
.CLR(fabric_xactors_to_slaves_1_f_rd_addr$CLR),
.D_OUT(fabric_xactors_to_slaves_1_f_rd_addr$D_OUT),
.FULL_N(fabric_xactors_to_slaves_1_f_rd_addr$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N));
// submodule fabric_xactors_to_slaves_1_f_rd_data
FIFO2 #(.width(32'd71),
.guarded(32'd1)) fabric_xactors_to_slaves_1_f_rd_data(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_1_f_rd_data$D_IN),
.ENQ(fabric_xactors_to_slaves_1_f_rd_data$ENQ),
.DEQ(fabric_xactors_to_slaves_1_f_rd_data$DEQ),
.CLR(fabric_xactors_to_slaves_1_f_rd_data$CLR),
.D_OUT(fabric_xactors_to_slaves_1_f_rd_data$D_OUT),
.FULL_N(fabric_xactors_to_slaves_1_f_rd_data$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N));
// submodule fabric_xactors_to_slaves_1_f_wr_addr
FIFO2 #(.width(32'd97),
.guarded(32'd1)) fabric_xactors_to_slaves_1_f_wr_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_1_f_wr_addr$D_IN),
.ENQ(fabric_xactors_to_slaves_1_f_wr_addr$ENQ),
.DEQ(fabric_xactors_to_slaves_1_f_wr_addr$DEQ),
.CLR(fabric_xactors_to_slaves_1_f_wr_addr$CLR),
.D_OUT(fabric_xactors_to_slaves_1_f_wr_addr$D_OUT),
.FULL_N(fabric_xactors_to_slaves_1_f_wr_addr$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N));
// submodule fabric_xactors_to_slaves_1_f_wr_data
FIFO2 #(.width(32'd73),
.guarded(32'd1)) fabric_xactors_to_slaves_1_f_wr_data(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_1_f_wr_data$D_IN),
.ENQ(fabric_xactors_to_slaves_1_f_wr_data$ENQ),
.DEQ(fabric_xactors_to_slaves_1_f_wr_data$DEQ),
.CLR(fabric_xactors_to_slaves_1_f_wr_data$CLR),
.D_OUT(fabric_xactors_to_slaves_1_f_wr_data$D_OUT),
.FULL_N(fabric_xactors_to_slaves_1_f_wr_data$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N));
// submodule fabric_xactors_to_slaves_1_f_wr_resp
FIFO2 #(.width(32'd6),
.guarded(32'd1)) fabric_xactors_to_slaves_1_f_wr_resp(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_1_f_wr_resp$D_IN),
.ENQ(fabric_xactors_to_slaves_1_f_wr_resp$ENQ),
.DEQ(fabric_xactors_to_slaves_1_f_wr_resp$DEQ),
.CLR(fabric_xactors_to_slaves_1_f_wr_resp$CLR),
.D_OUT(fabric_xactors_to_slaves_1_f_wr_resp$D_OUT),
.FULL_N(fabric_xactors_to_slaves_1_f_wr_resp$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N));
// submodule fabric_xactors_to_slaves_2_f_rd_addr
FIFO2 #(.width(32'd97),
.guarded(32'd1)) fabric_xactors_to_slaves_2_f_rd_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_2_f_rd_addr$D_IN),
.ENQ(fabric_xactors_to_slaves_2_f_rd_addr$ENQ),
.DEQ(fabric_xactors_to_slaves_2_f_rd_addr$DEQ),
.CLR(fabric_xactors_to_slaves_2_f_rd_addr$CLR),
.D_OUT(fabric_xactors_to_slaves_2_f_rd_addr$D_OUT),
.FULL_N(fabric_xactors_to_slaves_2_f_rd_addr$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N));
// submodule fabric_xactors_to_slaves_2_f_rd_data
FIFO2 #(.width(32'd71),
.guarded(32'd1)) fabric_xactors_to_slaves_2_f_rd_data(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_2_f_rd_data$D_IN),
.ENQ(fabric_xactors_to_slaves_2_f_rd_data$ENQ),
.DEQ(fabric_xactors_to_slaves_2_f_rd_data$DEQ),
.CLR(fabric_xactors_to_slaves_2_f_rd_data$CLR),
.D_OUT(fabric_xactors_to_slaves_2_f_rd_data$D_OUT),
.FULL_N(fabric_xactors_to_slaves_2_f_rd_data$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N));
// submodule fabric_xactors_to_slaves_2_f_wr_addr
FIFO2 #(.width(32'd97),
.guarded(32'd1)) fabric_xactors_to_slaves_2_f_wr_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_2_f_wr_addr$D_IN),
.ENQ(fabric_xactors_to_slaves_2_f_wr_addr$ENQ),
.DEQ(fabric_xactors_to_slaves_2_f_wr_addr$DEQ),
.CLR(fabric_xactors_to_slaves_2_f_wr_addr$CLR),
.D_OUT(fabric_xactors_to_slaves_2_f_wr_addr$D_OUT),
.FULL_N(fabric_xactors_to_slaves_2_f_wr_addr$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N));
// submodule fabric_xactors_to_slaves_2_f_wr_data
FIFO2 #(.width(32'd73),
.guarded(32'd1)) fabric_xactors_to_slaves_2_f_wr_data(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_2_f_wr_data$D_IN),
.ENQ(fabric_xactors_to_slaves_2_f_wr_data$ENQ),
.DEQ(fabric_xactors_to_slaves_2_f_wr_data$DEQ),
.CLR(fabric_xactors_to_slaves_2_f_wr_data$CLR),
.D_OUT(fabric_xactors_to_slaves_2_f_wr_data$D_OUT),
.FULL_N(fabric_xactors_to_slaves_2_f_wr_data$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N));
// submodule fabric_xactors_to_slaves_2_f_wr_resp
FIFO2 #(.width(32'd6),
.guarded(32'd1)) fabric_xactors_to_slaves_2_f_wr_resp(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_2_f_wr_resp$D_IN),
.ENQ(fabric_xactors_to_slaves_2_f_wr_resp$ENQ),
.DEQ(fabric_xactors_to_slaves_2_f_wr_resp$DEQ),
.CLR(fabric_xactors_to_slaves_2_f_wr_resp$CLR),
.D_OUT(fabric_xactors_to_slaves_2_f_wr_resp$D_OUT),
.FULL_N(fabric_xactors_to_slaves_2_f_wr_resp$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N));
// submodule soc_map
mkSoC_Map soc_map(.CLK(CLK),
.RST_N(RST_N),
.m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr),
.m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr),
.m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr),
.m_near_mem_io_addr_base(),
.m_near_mem_io_addr_size(),
.m_near_mem_io_addr_lim(),
.m_plic_addr_base(),
.m_plic_addr_size(),
.m_plic_addr_lim(),
.m_uart0_addr_base(soc_map$m_uart0_addr_base),
.m_uart0_addr_size(),
.m_uart0_addr_lim(soc_map$m_uart0_addr_lim),
.m_boot_rom_addr_base(soc_map$m_boot_rom_addr_base),
.m_boot_rom_addr_size(),
.m_boot_rom_addr_lim(soc_map$m_boot_rom_addr_lim),
.m_mem0_controller_addr_base(soc_map$m_mem0_controller_addr_base),
.m_mem0_controller_addr_size(),
.m_mem0_controller_addr_lim(soc_map$m_mem0_controller_addr_lim),
.m_tcm_addr_base(),
.m_tcm_addr_size(),
.m_tcm_addr_lim(),
.m_is_mem_addr(),
.m_is_IO_addr(),
.m_is_near_mem_IO_addr(),
.m_pc_reset_value(),
.m_mtvec_reset_value(),
.m_nmivec_reset_value());
// rule RL_fabric_rl_wr_xaction_master_to_slave
assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave =
fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N &&
fabric_xactors_to_slaves_0_f_wr_addr$FULL_N &&
fabric_v_f_wd_tasks_0$FULL_N &&
fabric_v_f_wr_mis_0$FULL_N &&
fabric_v_f_wr_sjs_0$FULL_N &&
soc_map_m_mem0_controller_addr_base__6_ULE_fab_ETC___d34 &&
IF_soc_map_m_mem0_controller_addr_base__6_ULE__ETC___d37 ==
2'd0 ;
assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave =
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ;
// rule RL_fabric_rl_wr_xaction_master_to_slave_1
assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 =
fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N &&
fabric_v_f_wd_tasks_0$FULL_N &&
fabric_v_f_wr_sjs_0$FULL_N &&
fabric_xactors_to_slaves_1_f_wr_addr$FULL_N &&
fabric_v_f_wr_mis_1$FULL_N &&
soc_map_m_mem0_controller_addr_base__6_ULE_fab_ETC___d34 &&
IF_soc_map_m_mem0_controller_addr_base__6_ULE__ETC___d37 ==
2'd1 ;
assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 =
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ;
// rule RL_fabric_rl_wr_xaction_master_to_slave_2
assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 =
fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N &&
fabric_v_f_wd_tasks_0$FULL_N &&
fabric_v_f_wr_sjs_0$FULL_N &&
fabric_xactors_to_slaves_2_f_wr_addr$FULL_N &&
fabric_v_f_wr_mis_2$FULL_N &&
soc_map_m_mem0_controller_addr_base__6_ULE_fab_ETC___d34 &&
IF_soc_map_m_mem0_controller_addr_base__6_ULE__ETC___d37 ==
2'd2 ;
assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 =
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ;
// rule RL_fabric_rl_wr_xaction_master_to_slave_3
assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 =
fabric_xactors_to_slaves_0_f_wr_addr$FULL_N &&
fabric_v_f_wr_mis_0$FULL_N &&
fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N &&
fabric_v_f_wd_tasks_1$FULL_N &&
fabric_v_f_wr_sjs_1$FULL_N &&
soc_map_m_mem0_controller_addr_base__6_ULE_fab_ETC___d99 &&
IF_soc_map_m_mem0_controller_addr_base__6_ULE__ETC___d102 ==
2'd0 ;
assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 =
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
!WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ;
// rule RL_fabric_rl_wr_xaction_master_to_slave_4
assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 =
fabric_xactors_to_slaves_1_f_wr_addr$FULL_N &&
fabric_v_f_wr_mis_1$FULL_N &&
fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N &&
fabric_v_f_wd_tasks_1$FULL_N &&
fabric_v_f_wr_sjs_1$FULL_N &&
soc_map_m_mem0_controller_addr_base__6_ULE_fab_ETC___d99 &&
IF_soc_map_m_mem0_controller_addr_base__6_ULE__ETC___d102 ==
2'd1 ;
assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 =
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
!WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ;
// rule RL_fabric_rl_wr_xaction_master_to_slave_5
assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 =
fabric_xactors_to_slaves_2_f_wr_addr$FULL_N &&
fabric_v_f_wr_mis_2$FULL_N &&
fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N &&
fabric_v_f_wd_tasks_1$FULL_N &&
fabric_v_f_wr_sjs_1$FULL_N &&
soc_map_m_mem0_controller_addr_base__6_ULE_fab_ETC___d99 &&
IF_soc_map_m_mem0_controller_addr_base__6_ULE__ETC___d102 ==
2'd2 ;
assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 =
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
!WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ;
// rule RL_fabric_rl_wr_xaction_no_such_slave
assign CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave =
fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N &&
fabric_v_f_wd_tasks_0$FULL_N &&
fabric_v_f_wr_sjs_0$FULL_N &&
fabric_v_f_wr_err_info_0$FULL_N &&
NOT_soc_map_m_mem0_controller_addr_base__6_ULE_ETC___d148 ;
assign WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave =
CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ;
// rule RL_fabric_rl_wr_xaction_no_such_slave_1
assign CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 =
fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N &&
fabric_v_f_wd_tasks_1$FULL_N &&
fabric_v_f_wr_sjs_1$FULL_N &&
fabric_v_f_wr_err_info_1$FULL_N &&
NOT_soc_map_m_mem0_controller_addr_base__6_ULE_ETC___d167 ;
assign WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 =
CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ;
// rule RL_fabric_rl_wr_xaction_master_to_slave_data
assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data =
fabric_xactors_from_masters_0_f_wr_data$EMPTY_N &&
fabric_v_f_wd_tasks_0_i_notEmpty__73_AND_fabri_ETC___d182 ;
assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data =
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data ;
// rule RL_fabric_rl_wr_xaction_master_to_slave_data_1
assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 =
fabric_xactors_from_masters_1_f_wr_data$EMPTY_N &&
fabric_v_f_wd_tasks_1_i_notEmpty__01_AND_fabri_ETC___d207 ;
assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 =
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
!WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data ;
// rule RL_fabric_rl_wr_resp_slave_to_master
assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master =
fabric_v_f_wr_mis_0$EMPTY_N && fabric_v_f_wr_sjs_0$EMPTY_N &&
fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N &&
fabric_xactors_from_masters_0_f_wr_resp$FULL_N &&
!fabric_v_f_wr_mis_0$D_OUT &&
fabric_v_f_wr_sjs_0$D_OUT == 2'd0 ;
assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master =
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master ;
// rule RL_fabric_rl_wr_resp_slave_to_master_1
assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 =
fabric_v_f_wr_sjs_0$EMPTY_N &&
fabric_xactors_from_masters_0_f_wr_resp$FULL_N &&
fabric_v_f_wr_mis_1$EMPTY_N &&
fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N &&
!fabric_v_f_wr_mis_1$D_OUT &&
fabric_v_f_wr_sjs_0$D_OUT == 2'd1 ;
assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 =
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ;
// rule RL_fabric_rl_wr_resp_slave_to_master_2
assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 =
fabric_v_f_wr_sjs_0$EMPTY_N &&
fabric_xactors_from_masters_0_f_wr_resp$FULL_N &&
fabric_v_f_wr_mis_2$EMPTY_N &&
fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N &&
!fabric_v_f_wr_mis_2$D_OUT &&
fabric_v_f_wr_sjs_0$D_OUT == 2'd2 ;
assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 =
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ;
// rule RL_fabric_rl_wr_resp_slave_to_master_3
assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 =
fabric_v_f_wr_mis_0$EMPTY_N &&
fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N &&
fabric_v_f_wr_sjs_1$EMPTY_N &&
fabric_xactors_from_masters_1_f_wr_resp$FULL_N &&
fabric_v_f_wr_mis_0$D_OUT &&
fabric_v_f_wr_sjs_1$D_OUT == 2'd0 ;
assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 =
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 ;
// rule RL_fabric_rl_wr_resp_slave_to_master_4
assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 =
fabric_v_f_wr_mis_1$EMPTY_N &&
fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N &&
fabric_v_f_wr_sjs_1$EMPTY_N &&
fabric_xactors_from_masters_1_f_wr_resp$FULL_N &&
fabric_v_f_wr_mis_1$D_OUT &&
fabric_v_f_wr_sjs_1$D_OUT == 2'd1 ;
assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 =
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 ;
// rule RL_fabric_rl_wr_resp_slave_to_master_5
assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 =
fabric_v_f_wr_mis_2$EMPTY_N &&
fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N &&
fabric_v_f_wr_sjs_1$EMPTY_N &&
fabric_xactors_from_masters_1_f_wr_resp$FULL_N &&
fabric_v_f_wr_mis_2$D_OUT &&
fabric_v_f_wr_sjs_1$D_OUT == 2'd2 ;
assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 =
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 ;
// rule RL_fabric_rl_wr_resp_err_to_master
assign CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master =
fabric_v_f_wr_sjs_0$EMPTY_N &&
fabric_xactors_from_masters_0_f_wr_resp$FULL_N &&
fabric_v_f_wr_err_info_0$EMPTY_N &&
fabric_v_f_wr_sjs_0$D_OUT == 2'd3 ;
assign WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master =
CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master ;
// rule RL_fabric_rl_wr_resp_err_to_master_1
assign CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 =
fabric_v_f_wr_sjs_1$EMPTY_N &&
fabric_xactors_from_masters_1_f_wr_resp$FULL_N &&
fabric_v_f_wr_err_info_1$EMPTY_N &&
fabric_v_f_wr_sjs_1$D_OUT == 2'd3 ;
assign WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 =
CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ;
// rule RL_fabric_rl_rd_xaction_master_to_slave
assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave =
fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N &&
fabric_xactors_to_slaves_0_f_rd_addr$FULL_N &&
fabric_v_f_rd_mis_0$FULL_N &&
fabric_v_f_rd_sjs_0$FULL_N &&
soc_map_m_mem0_controller_addr_base__6_ULE_fab_ETC___d335 &&
IF_soc_map_m_mem0_controller_addr_base__6_ULE__ETC___d338 ==
2'd0 ;
assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave =
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ;
// rule RL_fabric_rl_rd_xaction_master_to_slave_1
assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 =
fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N &&
fabric_v_f_rd_sjs_0$FULL_N &&
fabric_xactors_to_slaves_1_f_rd_addr$FULL_N &&
fabric_v_f_rd_mis_1$FULL_N &&
soc_map_m_mem0_controller_addr_base__6_ULE_fab_ETC___d335 &&
IF_soc_map_m_mem0_controller_addr_base__6_ULE__ETC___d338 ==
2'd1 ;
assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 =
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ;
// rule RL_fabric_rl_rd_xaction_master_to_slave_2
assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 =
fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N &&
fabric_v_f_rd_sjs_0$FULL_N &&
fabric_xactors_to_slaves_2_f_rd_addr$FULL_N &&
fabric_v_f_rd_mis_2$FULL_N &&
soc_map_m_mem0_controller_addr_base__6_ULE_fab_ETC___d335 &&
IF_soc_map_m_mem0_controller_addr_base__6_ULE__ETC___d338 ==
2'd2 ;
assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 =
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ;
// rule RL_fabric_rl_rd_xaction_master_to_slave_3
assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 =
fabric_xactors_to_slaves_0_f_rd_addr$FULL_N &&
fabric_v_f_rd_mis_0$FULL_N &&
fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N &&
fabric_v_f_rd_sjs_1$FULL_N &&
soc_map_m_mem0_controller_addr_base__6_ULE_fab_ETC___d391 &&
IF_soc_map_m_mem0_controller_addr_base__6_ULE__ETC___d394 ==
2'd0 ;
assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 =
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
!WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ;
// rule RL_fabric_rl_rd_xaction_master_to_slave_4
assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 =
fabric_xactors_to_slaves_1_f_rd_addr$FULL_N &&
fabric_v_f_rd_mis_1$FULL_N &&
fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N &&
fabric_v_f_rd_sjs_1$FULL_N &&
soc_map_m_mem0_controller_addr_base__6_ULE_fab_ETC___d391 &&
IF_soc_map_m_mem0_controller_addr_base__6_ULE__ETC___d394 ==
2'd1 ;
assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 =
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
!WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ;
// rule RL_fabric_rl_rd_xaction_master_to_slave_5
assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 =
fabric_xactors_to_slaves_2_f_rd_addr$FULL_N &&
fabric_v_f_rd_mis_2$FULL_N &&
fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N &&
fabric_v_f_rd_sjs_1$FULL_N &&
soc_map_m_mem0_controller_addr_base__6_ULE_fab_ETC___d391 &&
IF_soc_map_m_mem0_controller_addr_base__6_ULE__ETC___d394 ==
2'd2 ;
assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 =
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
!WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ;
// rule RL_fabric_rl_rd_xaction_no_such_slave
assign CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave =
fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N &&
fabric_v_f_rd_sjs_0$FULL_N &&
fabric_v_f_rd_err_info_0$FULL_N &&
NOT_soc_map_m_mem0_controller_addr_base__6_ULE_ETC___d437 ;
assign WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave =
CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave ;
// rule RL_fabric_rl_rd_xaction_no_such_slave_1
assign CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 =
fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N &&
fabric_v_f_rd_sjs_1$FULL_N &&
fabric_v_f_rd_err_info_1$FULL_N &&
NOT_soc_map_m_mem0_controller_addr_base__6_ULE_ETC___d455 ;
assign WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 =
CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 ;
// rule RL_fabric_rl_rd_resp_slave_to_master
assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master =
fabric_v_f_rd_mis_0$EMPTY_N &&
fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N &&
fabric_xactors_from_masters_0_f_rd_data$FULL_N &&
(fabric_v_f_rd_mis_0$D_OUT[8] || fabric_v_f_rd_sjs_0$EMPTY_N) &&
(!fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d469 ||
fabric_v_f_rd_sjs_0$EMPTY_N) &&
!fabric_v_f_rd_mis_0$D_OUT[8] &&
fabric_v_f_rd_sjs_0$D_OUT == 2'd0 ;
assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master =
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master ;
// rule RL_fabric_rl_rd_resp_slave_to_master_1
assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 =
fabric_xactors_from_masters_0_f_rd_data$FULL_N &&
fabric_v_f_rd_mis_1$EMPTY_N &&
fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N &&
(fabric_v_f_rd_mis_1$D_OUT[8] || fabric_v_f_rd_sjs_0$EMPTY_N) &&
(!fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d509 ||
fabric_v_f_rd_sjs_0$EMPTY_N) &&
!fabric_v_f_rd_mis_1$D_OUT[8] &&
fabric_v_f_rd_sjs_0$D_OUT == 2'd1 ;
assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 =
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ;
// rule RL_fabric_rl_rd_resp_slave_to_master_2
assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 =
fabric_xactors_from_masters_0_f_rd_data$FULL_N &&
fabric_v_f_rd_mis_2$EMPTY_N &&
fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N &&
(fabric_v_f_rd_mis_2$D_OUT[8] || fabric_v_f_rd_sjs_0$EMPTY_N) &&
(!fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d548 ||
fabric_v_f_rd_sjs_0$EMPTY_N) &&
!fabric_v_f_rd_mis_2$D_OUT[8] &&
fabric_v_f_rd_sjs_0$D_OUT == 2'd2 ;
assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 =
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ;
// rule RL_fabric_rl_rd_resp_slave_to_master_3
assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 =
fabric_v_f_rd_mis_0$EMPTY_N &&
fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N &&
fabric_xactors_from_masters_1_f_rd_data$FULL_N &&
fabric_v_f_rd_sjs_1$EMPTY_N &&
fabric_v_f_rd_mis_0$D_OUT[8] &&
fabric_v_f_rd_sjs_1$D_OUT == 2'd0 ;
assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 =
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 ;
// rule RL_fabric_rl_rd_resp_slave_to_master_4
assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 =
fabric_v_f_rd_mis_1$EMPTY_N &&
fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N &&
fabric_xactors_from_masters_1_f_rd_data$FULL_N &&
fabric_v_f_rd_sjs_1$EMPTY_N &&
fabric_v_f_rd_mis_1$D_OUT[8] &&
fabric_v_f_rd_sjs_1$D_OUT == 2'd1 ;
assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 =
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 ;
// rule RL_fabric_rl_rd_resp_slave_to_master_5
assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 =
fabric_v_f_rd_mis_2$EMPTY_N &&
fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N &&
fabric_xactors_from_masters_1_f_rd_data$FULL_N &&
fabric_v_f_rd_sjs_1$EMPTY_N &&
fabric_v_f_rd_mis_2$D_OUT[8] &&
fabric_v_f_rd_sjs_1$D_OUT == 2'd2 ;
assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 =
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 ;
// rule RL_fabric_rl_rd_resp_err_to_master
assign CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master =
fabric_v_f_rd_sjs_0$EMPTY_N &&
fabric_xactors_from_masters_0_f_rd_data$FULL_N &&
fabric_v_f_rd_err_info_0$EMPTY_N &&
fabric_v_f_rd_sjs_0$D_OUT == 2'd3 ;
assign WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master =
CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master ;
// rule RL_fabric_rl_rd_resp_err_to_master_1
assign CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 =
fabric_v_f_rd_sjs_1$EMPTY_N &&
fabric_xactors_from_masters_1_f_rd_data$FULL_N &&
fabric_v_f_rd_err_info_1$EMPTY_N &&
fabric_v_f_rd_sjs_1$D_OUT == 2'd3 ;
assign WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 =
CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ;
// rule RL_fabric_rl_reset
assign CAN_FIRE_RL_fabric_rl_reset = fabric_rg_reset ;
assign WILL_FIRE_RL_fabric_rl_reset = fabric_rg_reset ;
// inputs to muxes for submodule ports
assign MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1 =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd0 ;
assign MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1 =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd1 ;
assign MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1 =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd2 ;
assign MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 =
{ 1'd0, fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21] } ;
assign MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 =
{ 1'd1, fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21] } ;
assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1 =
{ 2'd0, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ;
assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2 =
{ 2'd1, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ;
assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3 =
{ 2'd2, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ;
assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_4 =
{ 2'd3, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ;
assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1 =
{ 2'd0, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ;
assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2 =
{ 2'd1, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ;
assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3 =
{ 2'd2, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ;
assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_4 =
{ 2'd3, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ;
assign MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2 =
fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d469 ?
8'd0 :
x__h18298 ;
assign MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2 =
fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d509 ?
8'd0 :
x__h18924 ;
assign MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2 =
fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d548 ?
8'd0 :
x__h19540 ;
assign MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2 =
fabric_v_rg_wd_beat_count_0_88_EQ_fabric_v_f_w_ETC___d190 ?
8'd0 :
x__h11887 ;
assign MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2 =
fabric_v_rg_wd_beat_count_1_13_EQ_fabric_v_f_w_ETC___d215 ?
8'd0 :
x__h12350 ;
assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 =
{ fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:3],
IF_fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_ETC___d496,
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0] } ;
assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 =
{ fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:3],
IF_fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_ETC___d535,
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0] } ;
assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 =
{ fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:3],
IF_fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_ETC___d574,
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0] } ;
assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4 =
{ fabric_v_f_rd_err_info_0$D_OUT[3:0],
66'd3,
fabric_v_rg_r_err_beat_count_0_18_EQ_fabric_v__ETC___d620 } ;
assign MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4 =
{ fabric_v_f_wr_err_info_0$D_OUT, 2'd3 } ;
assign MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4 =
{ fabric_v_f_rd_err_info_1$D_OUT[3:0],
66'd3,
fabric_v_rg_r_err_beat_count_1_36_EQ_fabric_v__ETC___d638 } ;
assign MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4 =
{ fabric_v_f_wr_err_info_1$D_OUT, 2'd3 } ;
// register fabric_cfg_verbosity
assign fabric_cfg_verbosity$D_IN = set_verbosity_verbosity ;
assign fabric_cfg_verbosity$EN = EN_set_verbosity ;
// register fabric_rg_reset
assign fabric_rg_reset$D_IN = !fabric_rg_reset ;
assign fabric_rg_reset$EN = fabric_rg_reset || EN_reset ;
// register fabric_v_rg_r_beat_count_0
always@(fabric_rg_reset or
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 or
MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2 or
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master)
case (1'b1)
fabric_rg_reset: fabric_v_rg_r_beat_count_0$D_IN = 8'd0;
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3:
fabric_v_rg_r_beat_count_0$D_IN =
MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2;
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master:
fabric_v_rg_r_beat_count_0$D_IN =
MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2;
default: fabric_v_rg_r_beat_count_0$D_IN =
8'b10101010 /* unspecified value */ ;
endcase
assign fabric_v_rg_r_beat_count_0$EN =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master ||
fabric_rg_reset ;
// register fabric_v_rg_r_beat_count_1
always@(fabric_rg_reset or
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 or
MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2 or
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1)
case (1'b1)
fabric_rg_reset: fabric_v_rg_r_beat_count_1$D_IN = 8'd0;
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4:
fabric_v_rg_r_beat_count_1$D_IN =
MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2;
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1:
fabric_v_rg_r_beat_count_1$D_IN =
MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2;
default: fabric_v_rg_r_beat_count_1$D_IN =
8'b10101010 /* unspecified value */ ;
endcase
assign fabric_v_rg_r_beat_count_1$EN =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ||
fabric_rg_reset ;
// register fabric_v_rg_r_beat_count_2
always@(fabric_rg_reset or
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 or
MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2 or
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2)
case (1'b1)
fabric_rg_reset: fabric_v_rg_r_beat_count_2$D_IN = 8'd0;
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5:
fabric_v_rg_r_beat_count_2$D_IN =
MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2;
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2:
fabric_v_rg_r_beat_count_2$D_IN =
MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2;
default: fabric_v_rg_r_beat_count_2$D_IN =
8'b10101010 /* unspecified value */ ;
endcase
assign fabric_v_rg_r_beat_count_2$EN =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ||
fabric_rg_reset ;
// register fabric_v_rg_r_err_beat_count_0
assign fabric_v_rg_r_err_beat_count_0$D_IN =
fabric_v_rg_r_err_beat_count_0_18_EQ_fabric_v__ETC___d620 ?
8'd0 :
x__h21844 ;
assign fabric_v_rg_r_err_beat_count_0$EN =
CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master ;
// register fabric_v_rg_r_err_beat_count_1
assign fabric_v_rg_r_err_beat_count_1$D_IN =
fabric_v_rg_r_err_beat_count_1_36_EQ_fabric_v__ETC___d638 ?
8'd0 :
x__h22245 ;
assign fabric_v_rg_r_err_beat_count_1$EN =
CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ;
// register fabric_v_rg_wd_beat_count_0
assign fabric_v_rg_wd_beat_count_0$D_IN =
fabric_rg_reset ?
8'd0 :
MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2 ;
assign fabric_v_rg_wd_beat_count_0$EN =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data ||
fabric_rg_reset ;
// register fabric_v_rg_wd_beat_count_1
assign fabric_v_rg_wd_beat_count_1$D_IN =
fabric_rg_reset ?
8'd0 :
MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2 ;
assign fabric_v_rg_wd_beat_count_1$EN =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 ||
fabric_rg_reset ;
// submodule fabric_v_f_rd_err_info_0
assign fabric_v_f_rd_err_info_0$D_IN =
{ fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21],
fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93] } ;
assign fabric_v_f_rd_err_info_0$ENQ =
CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave ;
assign fabric_v_f_rd_err_info_0$DEQ =
WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_v_rg_r_err_beat_count_0_18_EQ_fabric_v__ETC___d620 ;
assign fabric_v_f_rd_err_info_0$CLR = fabric_rg_reset ;
// submodule fabric_v_f_rd_err_info_1
assign fabric_v_f_rd_err_info_1$D_IN =
{ fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21],
fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93] } ;
assign fabric_v_f_rd_err_info_1$ENQ =
CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 ;
assign fabric_v_f_rd_err_info_1$DEQ =
WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_v_rg_r_err_beat_count_1_36_EQ_fabric_v__ETC___d638 ;
assign fabric_v_f_rd_err_info_1$CLR = fabric_rg_reset ;
// submodule fabric_v_f_rd_mis_0
assign fabric_v_f_rd_mis_0$D_IN =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ?
MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 :
MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ;
assign fabric_v_f_rd_mis_0$ENQ =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 ;
assign fabric_v_f_rd_mis_0$DEQ =
_dor1fabric_v_f_rd_mis_0$EN_deq &&
fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d469 ;
assign fabric_v_f_rd_mis_0$CLR = fabric_rg_reset ;
// submodule fabric_v_f_rd_mis_1
assign fabric_v_f_rd_mis_1$D_IN =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ?
MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 :
MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ;
assign fabric_v_f_rd_mis_1$ENQ =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 ;
assign fabric_v_f_rd_mis_1$DEQ =
_dor1fabric_v_f_rd_mis_1$EN_deq &&
fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d509 ;
assign fabric_v_f_rd_mis_1$CLR = fabric_rg_reset ;
// submodule fabric_v_f_rd_mis_2
assign fabric_v_f_rd_mis_2$D_IN =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ?
MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 :
MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ;
assign fabric_v_f_rd_mis_2$ENQ =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 ;
assign fabric_v_f_rd_mis_2$DEQ =
_dor1fabric_v_f_rd_mis_2$EN_deq &&
fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d548 ;
assign fabric_v_f_rd_mis_2$CLR = fabric_rg_reset ;
// submodule fabric_v_f_rd_sjs_0
always@(WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave or
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 or
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 or
WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave:
fabric_v_f_rd_sjs_0$D_IN = 2'd0;
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1:
fabric_v_f_rd_sjs_0$D_IN = 2'd1;
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2:
fabric_v_f_rd_sjs_0$D_IN = 2'd2;
WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave:
fabric_v_f_rd_sjs_0$D_IN = 2'd3;
default: fabric_v_f_rd_sjs_0$D_IN = 2'b10 /* unspecified value */ ;
endcase
end
assign fabric_v_f_rd_sjs_0$ENQ =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ||
WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave ;
assign fabric_v_f_rd_sjs_0$DEQ =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d469 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d509 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d548 ||
WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_v_rg_r_err_beat_count_0_18_EQ_fabric_v__ETC___d620 ;
assign fabric_v_f_rd_sjs_0$CLR = fabric_rg_reset ;
// submodule fabric_v_f_rd_sjs_1
always@(WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 or
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 or
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 or
WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3:
fabric_v_f_rd_sjs_1$D_IN = 2'd0;
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4:
fabric_v_f_rd_sjs_1$D_IN = 2'd1;
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5:
fabric_v_f_rd_sjs_1$D_IN = 2'd2;
WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1:
fabric_v_f_rd_sjs_1$D_IN = 2'd3;
default: fabric_v_f_rd_sjs_1$D_IN = 2'b10 /* unspecified value */ ;
endcase
end
assign fabric_v_f_rd_sjs_1$ENQ =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 ||
WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 ;
assign fabric_v_f_rd_sjs_1$DEQ =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d469 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d509 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d548 ||
WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_v_rg_r_err_beat_count_1_36_EQ_fabric_v__ETC___d638 ;
assign fabric_v_f_rd_sjs_1$CLR = fabric_rg_reset ;
// submodule fabric_v_f_wd_tasks_0
always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave or
MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1 or
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 or
MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2 or
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 or
MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3 or
WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave or
MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_4)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave:
fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1;
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1:
fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2;
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2:
fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3;
WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave:
fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_4;
default: fabric_v_f_wd_tasks_0$D_IN =
10'b1010101010 /* unspecified value */ ;
endcase
end
assign fabric_v_f_wd_tasks_0$ENQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ;
assign fabric_v_f_wd_tasks_0$DEQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_88_EQ_fabric_v_f_w_ETC___d190 ;
assign fabric_v_f_wd_tasks_0$CLR = fabric_rg_reset ;
// submodule fabric_v_f_wd_tasks_1
always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 or
MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1 or
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 or
MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2 or
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 or
MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3 or
WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 or
MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_4)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3:
fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1;
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4:
fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2;
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5:
fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3;
WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1:
fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_4;
default: fabric_v_f_wd_tasks_1$D_IN =
10'b1010101010 /* unspecified value */ ;
endcase
end
assign fabric_v_f_wd_tasks_1$ENQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ;
assign fabric_v_f_wd_tasks_1$DEQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_rg_wd_beat_count_1_13_EQ_fabric_v_f_w_ETC___d215 ;
assign fabric_v_f_wd_tasks_1$CLR = fabric_rg_reset ;
// submodule fabric_v_f_wr_err_info_0
assign fabric_v_f_wr_err_info_0$D_IN =
fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93] ;
assign fabric_v_f_wr_err_info_0$ENQ =
CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ;
assign fabric_v_f_wr_err_info_0$DEQ =
CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master ;
assign fabric_v_f_wr_err_info_0$CLR = fabric_rg_reset ;
// submodule fabric_v_f_wr_err_info_1
assign fabric_v_f_wr_err_info_1$D_IN =
fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93] ;
assign fabric_v_f_wr_err_info_1$ENQ =
CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ;
assign fabric_v_f_wr_err_info_1$DEQ =
CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ;
assign fabric_v_f_wr_err_info_1$CLR = fabric_rg_reset ;
// submodule fabric_v_f_wr_mis_0
assign fabric_v_f_wr_mis_0$D_IN =
!WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ;
assign fabric_v_f_wr_mis_0$ENQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ;
assign fabric_v_f_wr_mis_0$DEQ =
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ;
assign fabric_v_f_wr_mis_0$CLR = fabric_rg_reset ;
// submodule fabric_v_f_wr_mis_1
assign fabric_v_f_wr_mis_1$D_IN =
!WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ;
assign fabric_v_f_wr_mis_1$ENQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 ;
assign fabric_v_f_wr_mis_1$DEQ =
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ;
assign fabric_v_f_wr_mis_1$CLR = fabric_rg_reset ;
// submodule fabric_v_f_wr_mis_2
assign fabric_v_f_wr_mis_2$D_IN =
!WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ;
assign fabric_v_f_wr_mis_2$ENQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ;
assign fabric_v_f_wr_mis_2$DEQ =
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ;
assign fabric_v_f_wr_mis_2$CLR = fabric_rg_reset ;
// submodule fabric_v_f_wr_sjs_0
always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave or
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 or
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 or
WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave:
fabric_v_f_wr_sjs_0$D_IN = 2'd0;
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1:
fabric_v_f_wr_sjs_0$D_IN = 2'd1;
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2:
fabric_v_f_wr_sjs_0$D_IN = 2'd2;
WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave:
fabric_v_f_wr_sjs_0$D_IN = 2'd3;
default: fabric_v_f_wr_sjs_0$D_IN = 2'b10 /* unspecified value */ ;
endcase
end
assign fabric_v_f_wr_sjs_0$ENQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ;
assign fabric_v_f_wr_sjs_0$DEQ =
WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ;
assign fabric_v_f_wr_sjs_0$CLR = fabric_rg_reset ;
// submodule fabric_v_f_wr_sjs_1
always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 or
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 or
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 or
WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3:
fabric_v_f_wr_sjs_1$D_IN = 2'd0;
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4:
fabric_v_f_wr_sjs_1$D_IN = 2'd1;
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5:
fabric_v_f_wr_sjs_1$D_IN = 2'd2;
WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1:
fabric_v_f_wr_sjs_1$D_IN = 2'd3;
default: fabric_v_f_wr_sjs_1$D_IN = 2'b10 /* unspecified value */ ;
endcase
end
assign fabric_v_f_wr_sjs_1$ENQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ;
assign fabric_v_f_wr_sjs_1$DEQ =
WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 ;
assign fabric_v_f_wr_sjs_1$CLR = fabric_rg_reset ;
// submodule fabric_xactors_from_masters_0_f_rd_addr
assign fabric_xactors_from_masters_0_f_rd_addr$D_IN =
{ v_from_masters_0_arid,
v_from_masters_0_araddr,
v_from_masters_0_arlen,
v_from_masters_0_arsize,
v_from_masters_0_arburst,
v_from_masters_0_arlock,
v_from_masters_0_arcache,
v_from_masters_0_arprot,
v_from_masters_0_arqos,
v_from_masters_0_arregion } ;
assign fabric_xactors_from_masters_0_f_rd_addr$ENQ =
v_from_masters_0_arvalid &&
fabric_xactors_from_masters_0_f_rd_addr$FULL_N ;
assign fabric_xactors_from_masters_0_f_rd_addr$DEQ =
WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ;
assign fabric_xactors_from_masters_0_f_rd_addr$CLR = fabric_rg_reset ;
// submodule fabric_xactors_from_masters_0_f_rd_data
always@(WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master or
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 or
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 or
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 or
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 or
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 or
WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master or
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master:
fabric_xactors_from_masters_0_f_rd_data$D_IN =
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1;
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1:
fabric_xactors_from_masters_0_f_rd_data$D_IN =
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2;
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2:
fabric_xactors_from_masters_0_f_rd_data$D_IN =
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3;
WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master:
fabric_xactors_from_masters_0_f_rd_data$D_IN =
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4;
default: fabric_xactors_from_masters_0_f_rd_data$D_IN =
71'h2AAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign fabric_xactors_from_masters_0_f_rd_data$ENQ =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ||
WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master ;
assign fabric_xactors_from_masters_0_f_rd_data$DEQ =
v_from_masters_0_rready &&
fabric_xactors_from_masters_0_f_rd_data$EMPTY_N ;
assign fabric_xactors_from_masters_0_f_rd_data$CLR = fabric_rg_reset ;
// submodule fabric_xactors_from_masters_0_f_wr_addr
assign fabric_xactors_from_masters_0_f_wr_addr$D_IN =
{ v_from_masters_0_awid,
v_from_masters_0_awaddr,
v_from_masters_0_awlen,
v_from_masters_0_awsize,
v_from_masters_0_awburst,
v_from_masters_0_awlock,
v_from_masters_0_awcache,
v_from_masters_0_awprot,
v_from_masters_0_awqos,
v_from_masters_0_awregion } ;
assign fabric_xactors_from_masters_0_f_wr_addr$ENQ =
v_from_masters_0_awvalid &&
fabric_xactors_from_masters_0_f_wr_addr$FULL_N ;
assign fabric_xactors_from_masters_0_f_wr_addr$DEQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ;
assign fabric_xactors_from_masters_0_f_wr_addr$CLR = fabric_rg_reset ;
// submodule fabric_xactors_from_masters_0_f_wr_data
assign fabric_xactors_from_masters_0_f_wr_data$D_IN =
{ v_from_masters_0_wdata,
v_from_masters_0_wstrb,
v_from_masters_0_wlast } ;
assign fabric_xactors_from_masters_0_f_wr_data$ENQ =
v_from_masters_0_wvalid &&
fabric_xactors_from_masters_0_f_wr_data$FULL_N ;
assign fabric_xactors_from_masters_0_f_wr_data$DEQ =
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data ;
assign fabric_xactors_from_masters_0_f_wr_data$CLR = fabric_rg_reset ;
// submodule fabric_xactors_from_masters_0_f_wr_resp
always@(WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 or
fabric_xactors_to_slaves_1_f_wr_resp$D_OUT or
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master or
fabric_xactors_to_slaves_0_f_wr_resp$D_OUT or
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 or
fabric_xactors_to_slaves_2_f_wr_resp$D_OUT or
WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master or
MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1:
fabric_xactors_from_masters_0_f_wr_resp$D_IN =
fabric_xactors_to_slaves_1_f_wr_resp$D_OUT;
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master:
fabric_xactors_from_masters_0_f_wr_resp$D_IN =
fabric_xactors_to_slaves_0_f_wr_resp$D_OUT;
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2:
fabric_xactors_from_masters_0_f_wr_resp$D_IN =
fabric_xactors_to_slaves_2_f_wr_resp$D_OUT;
WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master:
fabric_xactors_from_masters_0_f_wr_resp$D_IN =
MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4;
default: fabric_xactors_from_masters_0_f_wr_resp$D_IN =
6'b101010 /* unspecified value */ ;
endcase
end
assign fabric_xactors_from_masters_0_f_wr_resp$ENQ =
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ||
WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master ;
assign fabric_xactors_from_masters_0_f_wr_resp$DEQ =
v_from_masters_0_bready &&
fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N ;
assign fabric_xactors_from_masters_0_f_wr_resp$CLR = fabric_rg_reset ;
// submodule fabric_xactors_from_masters_1_f_rd_addr
assign fabric_xactors_from_masters_1_f_rd_addr$D_IN =
{ v_from_masters_1_arid,
v_from_masters_1_araddr,
v_from_masters_1_arlen,
v_from_masters_1_arsize,
v_from_masters_1_arburst,
v_from_masters_1_arlock,
v_from_masters_1_arcache,
v_from_masters_1_arprot,
v_from_masters_1_arqos,
v_from_masters_1_arregion } ;
assign fabric_xactors_from_masters_1_f_rd_addr$ENQ =
v_from_masters_1_arvalid &&
fabric_xactors_from_masters_1_f_rd_addr$FULL_N ;
assign fabric_xactors_from_masters_1_f_rd_addr$DEQ =
WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 ;
assign fabric_xactors_from_masters_1_f_rd_addr$CLR = fabric_rg_reset ;
// submodule fabric_xactors_from_masters_1_f_rd_data
always@(WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 or
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 or
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 or
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 or
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 or
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 or
WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 or
MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3:
fabric_xactors_from_masters_1_f_rd_data$D_IN =
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1;
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4:
fabric_xactors_from_masters_1_f_rd_data$D_IN =
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2;
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5:
fabric_xactors_from_masters_1_f_rd_data$D_IN =
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3;
WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1:
fabric_xactors_from_masters_1_f_rd_data$D_IN =
MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4;
default: fabric_xactors_from_masters_1_f_rd_data$D_IN =
71'h2AAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign fabric_xactors_from_masters_1_f_rd_data$ENQ =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 ||
WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ;
assign fabric_xactors_from_masters_1_f_rd_data$DEQ =
v_from_masters_1_rready &&
fabric_xactors_from_masters_1_f_rd_data$EMPTY_N ;
assign fabric_xactors_from_masters_1_f_rd_data$CLR = fabric_rg_reset ;
// submodule fabric_xactors_from_masters_1_f_wr_addr
assign fabric_xactors_from_masters_1_f_wr_addr$D_IN =
{ v_from_masters_1_awid,
v_from_masters_1_awaddr,
v_from_masters_1_awlen,
v_from_masters_1_awsize,
v_from_masters_1_awburst,
v_from_masters_1_awlock,
v_from_masters_1_awcache,
v_from_masters_1_awprot,
v_from_masters_1_awqos,
v_from_masters_1_awregion } ;
assign fabric_xactors_from_masters_1_f_wr_addr$ENQ =
v_from_masters_1_awvalid &&
fabric_xactors_from_masters_1_f_wr_addr$FULL_N ;
assign fabric_xactors_from_masters_1_f_wr_addr$DEQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ;
assign fabric_xactors_from_masters_1_f_wr_addr$CLR = fabric_rg_reset ;
// submodule fabric_xactors_from_masters_1_f_wr_data
assign fabric_xactors_from_masters_1_f_wr_data$D_IN =
{ v_from_masters_1_wdata,
v_from_masters_1_wstrb,
v_from_masters_1_wlast } ;
assign fabric_xactors_from_masters_1_f_wr_data$ENQ =
v_from_masters_1_wvalid &&
fabric_xactors_from_masters_1_f_wr_data$FULL_N ;
assign fabric_xactors_from_masters_1_f_wr_data$DEQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 ;
assign fabric_xactors_from_masters_1_f_wr_data$CLR = fabric_rg_reset ;
// submodule fabric_xactors_from_masters_1_f_wr_resp
always@(WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 or
fabric_xactors_to_slaves_1_f_wr_resp$D_OUT or
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 or
fabric_xactors_to_slaves_0_f_wr_resp$D_OUT or
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 or
fabric_xactors_to_slaves_2_f_wr_resp$D_OUT or
WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 or
MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4:
fabric_xactors_from_masters_1_f_wr_resp$D_IN =
fabric_xactors_to_slaves_1_f_wr_resp$D_OUT;
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3:
fabric_xactors_from_masters_1_f_wr_resp$D_IN =
fabric_xactors_to_slaves_0_f_wr_resp$D_OUT;
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5:
fabric_xactors_from_masters_1_f_wr_resp$D_IN =
fabric_xactors_to_slaves_2_f_wr_resp$D_OUT;
WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1:
fabric_xactors_from_masters_1_f_wr_resp$D_IN =
MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4;
default: fabric_xactors_from_masters_1_f_wr_resp$D_IN =
6'b101010 /* unspecified value */ ;
endcase
end
assign fabric_xactors_from_masters_1_f_wr_resp$ENQ =
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 ||
WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ;
assign fabric_xactors_from_masters_1_f_wr_resp$DEQ =
v_from_masters_1_bready &&
fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N ;
assign fabric_xactors_from_masters_1_f_wr_resp$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_0_f_rd_addr
assign fabric_xactors_to_slaves_0_f_rd_addr$D_IN =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ?
fabric_xactors_from_masters_0_f_rd_addr$D_OUT :
fabric_xactors_from_masters_1_f_rd_addr$D_OUT ;
assign fabric_xactors_to_slaves_0_f_rd_addr$ENQ =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 ;
assign fabric_xactors_to_slaves_0_f_rd_addr$DEQ =
fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N &&
v_to_slaves_0_arready ;
assign fabric_xactors_to_slaves_0_f_rd_addr$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_0_f_rd_data
assign fabric_xactors_to_slaves_0_f_rd_data$D_IN =
{ v_to_slaves_0_rid,
v_to_slaves_0_rdata,
v_to_slaves_0_rresp,
v_to_slaves_0_rlast } ;
assign fabric_xactors_to_slaves_0_f_rd_data$ENQ =
v_to_slaves_0_rvalid &&
fabric_xactors_to_slaves_0_f_rd_data$FULL_N ;
assign fabric_xactors_to_slaves_0_f_rd_data$DEQ =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master ;
assign fabric_xactors_to_slaves_0_f_rd_data$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_0_f_wr_addr
assign fabric_xactors_to_slaves_0_f_wr_addr$D_IN =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ?
fabric_xactors_from_masters_0_f_wr_addr$D_OUT :
fabric_xactors_from_masters_1_f_wr_addr$D_OUT ;
assign fabric_xactors_to_slaves_0_f_wr_addr$ENQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ;
assign fabric_xactors_to_slaves_0_f_wr_addr$DEQ =
fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N &&
v_to_slaves_0_awready ;
assign fabric_xactors_to_slaves_0_f_wr_addr$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_0_f_wr_data
assign fabric_xactors_to_slaves_0_f_wr_data$D_IN =
MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1 ?
fabric_xactors_from_masters_0_f_wr_data$D_OUT :
fabric_xactors_from_masters_1_f_wr_data$D_OUT ;
assign fabric_xactors_to_slaves_0_f_wr_data$ENQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd0 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd0 ;
assign fabric_xactors_to_slaves_0_f_wr_data$DEQ =
fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N &&
v_to_slaves_0_wready ;
assign fabric_xactors_to_slaves_0_f_wr_data$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_0_f_wr_resp
assign fabric_xactors_to_slaves_0_f_wr_resp$D_IN =
{ v_to_slaves_0_bid, v_to_slaves_0_bresp } ;
assign fabric_xactors_to_slaves_0_f_wr_resp$ENQ =
v_to_slaves_0_bvalid &&
fabric_xactors_to_slaves_0_f_wr_resp$FULL_N ;
assign fabric_xactors_to_slaves_0_f_wr_resp$DEQ =
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ;
assign fabric_xactors_to_slaves_0_f_wr_resp$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_1_f_rd_addr
assign fabric_xactors_to_slaves_1_f_rd_addr$D_IN =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ?
fabric_xactors_from_masters_0_f_rd_addr$D_OUT :
fabric_xactors_from_masters_1_f_rd_addr$D_OUT ;
assign fabric_xactors_to_slaves_1_f_rd_addr$ENQ =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 ;
assign fabric_xactors_to_slaves_1_f_rd_addr$DEQ =
fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N &&
v_to_slaves_1_arready ;
assign fabric_xactors_to_slaves_1_f_rd_addr$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_1_f_rd_data
assign fabric_xactors_to_slaves_1_f_rd_data$D_IN =
{ v_to_slaves_1_rid,
v_to_slaves_1_rdata,
v_to_slaves_1_rresp,
v_to_slaves_1_rlast } ;
assign fabric_xactors_to_slaves_1_f_rd_data$ENQ =
v_to_slaves_1_rvalid &&
fabric_xactors_to_slaves_1_f_rd_data$FULL_N ;
assign fabric_xactors_to_slaves_1_f_rd_data$DEQ =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ;
assign fabric_xactors_to_slaves_1_f_rd_data$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_1_f_wr_addr
assign fabric_xactors_to_slaves_1_f_wr_addr$D_IN =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ?
fabric_xactors_from_masters_0_f_wr_addr$D_OUT :
fabric_xactors_from_masters_1_f_wr_addr$D_OUT ;
assign fabric_xactors_to_slaves_1_f_wr_addr$ENQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 ;
assign fabric_xactors_to_slaves_1_f_wr_addr$DEQ =
fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N &&
v_to_slaves_1_awready ;
assign fabric_xactors_to_slaves_1_f_wr_addr$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_1_f_wr_data
assign fabric_xactors_to_slaves_1_f_wr_data$D_IN =
MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1 ?
fabric_xactors_from_masters_0_f_wr_data$D_OUT :
fabric_xactors_from_masters_1_f_wr_data$D_OUT ;
assign fabric_xactors_to_slaves_1_f_wr_data$ENQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd1 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd1 ;
assign fabric_xactors_to_slaves_1_f_wr_data$DEQ =
fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N &&
v_to_slaves_1_wready ;
assign fabric_xactors_to_slaves_1_f_wr_data$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_1_f_wr_resp
assign fabric_xactors_to_slaves_1_f_wr_resp$D_IN =
{ v_to_slaves_1_bid, v_to_slaves_1_bresp } ;
assign fabric_xactors_to_slaves_1_f_wr_resp$ENQ =
v_to_slaves_1_bvalid &&
fabric_xactors_to_slaves_1_f_wr_resp$FULL_N ;
assign fabric_xactors_to_slaves_1_f_wr_resp$DEQ =
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ;
assign fabric_xactors_to_slaves_1_f_wr_resp$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_2_f_rd_addr
assign fabric_xactors_to_slaves_2_f_rd_addr$D_IN =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ?
fabric_xactors_from_masters_0_f_rd_addr$D_OUT :
fabric_xactors_from_masters_1_f_rd_addr$D_OUT ;
assign fabric_xactors_to_slaves_2_f_rd_addr$ENQ =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 ;
assign fabric_xactors_to_slaves_2_f_rd_addr$DEQ =
fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N &&
v_to_slaves_2_arready ;
assign fabric_xactors_to_slaves_2_f_rd_addr$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_2_f_rd_data
assign fabric_xactors_to_slaves_2_f_rd_data$D_IN =
{ v_to_slaves_2_rid,
v_to_slaves_2_rdata,
v_to_slaves_2_rresp,
v_to_slaves_2_rlast } ;
assign fabric_xactors_to_slaves_2_f_rd_data$ENQ =
v_to_slaves_2_rvalid &&
fabric_xactors_to_slaves_2_f_rd_data$FULL_N ;
assign fabric_xactors_to_slaves_2_f_rd_data$DEQ =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ;
assign fabric_xactors_to_slaves_2_f_rd_data$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_2_f_wr_addr
assign fabric_xactors_to_slaves_2_f_wr_addr$D_IN =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ?
fabric_xactors_from_masters_0_f_wr_addr$D_OUT :
fabric_xactors_from_masters_1_f_wr_addr$D_OUT ;
assign fabric_xactors_to_slaves_2_f_wr_addr$ENQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ;
assign fabric_xactors_to_slaves_2_f_wr_addr$DEQ =
fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N &&
v_to_slaves_2_awready ;
assign fabric_xactors_to_slaves_2_f_wr_addr$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_2_f_wr_data
assign fabric_xactors_to_slaves_2_f_wr_data$D_IN =
MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1 ?
fabric_xactors_from_masters_0_f_wr_data$D_OUT :
fabric_xactors_from_masters_1_f_wr_data$D_OUT ;
assign fabric_xactors_to_slaves_2_f_wr_data$ENQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd2 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd2 ;
assign fabric_xactors_to_slaves_2_f_wr_data$DEQ =
fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N &&
v_to_slaves_2_wready ;
assign fabric_xactors_to_slaves_2_f_wr_data$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_2_f_wr_resp
assign fabric_xactors_to_slaves_2_f_wr_resp$D_IN =
{ v_to_slaves_2_bid, v_to_slaves_2_bresp } ;
assign fabric_xactors_to_slaves_2_f_wr_resp$ENQ =
v_to_slaves_2_bvalid &&
fabric_xactors_to_slaves_2_f_wr_resp$FULL_N ;
assign fabric_xactors_to_slaves_2_f_wr_resp$DEQ =
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ;
assign fabric_xactors_to_slaves_2_f_wr_resp$CLR = fabric_rg_reset ;
// submodule soc_map
assign soc_map$m_is_IO_addr_addr = 64'h0 ;
assign soc_map$m_is_mem_addr_addr = 64'h0 ;
assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ;
// remaining internal signals
assign IF_fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_ETC___d496 =
fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d469 ?
x1_avValue_rresp__h18276 :
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] ;
assign IF_fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_ETC___d535 =
fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d509 ?
x1_avValue_rresp__h18902 :
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] ;
assign IF_fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_ETC___d574 =
fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d548 ?
x1_avValue_rresp__h19518 :
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] ;
assign IF_soc_map_m_mem0_controller_addr_base__6_ULE__ETC___d102 =
(soc_map_m_mem0_controller_addr_base__6_ULE_fab_ETC___d89 &&
fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d90) ?
2'd1 :
((soc_map_m_boot_rom_addr_base__3_ULE_fabric_xac_ETC___d92 &&
fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d93) ?
2'd0 :
2'd2) ;
assign IF_soc_map_m_mem0_controller_addr_base__6_ULE__ETC___d338 =
(soc_map_m_mem0_controller_addr_base__6_ULE_fab_ETC___d325 &&
fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d326) ?
2'd1 :
((soc_map_m_boot_rom_addr_base__3_ULE_fabric_xac_ETC___d328 &&
fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d329) ?
2'd0 :
2'd2) ;
assign IF_soc_map_m_mem0_controller_addr_base__6_ULE__ETC___d37 =
(soc_map_m_mem0_controller_addr_base__6_ULE_fab_ETC___d19 &&
fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d21) ?
2'd1 :
((soc_map_m_boot_rom_addr_base__3_ULE_fabric_xac_ETC___d24 &&
fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d26) ?
2'd0 :
2'd2) ;
assign IF_soc_map_m_mem0_controller_addr_base__6_ULE__ETC___d394 =
(soc_map_m_mem0_controller_addr_base__6_ULE_fab_ETC___d381 &&
fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d382) ?
2'd1 :
((soc_map_m_boot_rom_addr_base__3_ULE_fabric_xac_ETC___d384 &&
fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d385) ?
2'd0 :
2'd2) ;
assign NOT_soc_map_m_mem0_controller_addr_base__6_ULE_ETC___d148 =
(!soc_map_m_mem0_controller_addr_base__6_ULE_fab_ETC___d19 ||
!fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d21) &&
(!soc_map_m_boot_rom_addr_base__3_ULE_fabric_xac_ETC___d24 ||
!fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d26) &&
(!soc_map_m_uart0_addr_base__8_ULE_fabric_xactor_ETC___d29 ||
!fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d31) ;
assign NOT_soc_map_m_mem0_controller_addr_base__6_ULE_ETC___d167 =
(!soc_map_m_mem0_controller_addr_base__6_ULE_fab_ETC___d89 ||
!fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d90) &&
(!soc_map_m_boot_rom_addr_base__3_ULE_fabric_xac_ETC___d92 ||
!fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d93) &&
(!soc_map_m_uart0_addr_base__8_ULE_fabric_xactor_ETC___d95 ||
!fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d96) ;
assign NOT_soc_map_m_mem0_controller_addr_base__6_ULE_ETC___d437 =
(!soc_map_m_mem0_controller_addr_base__6_ULE_fab_ETC___d325 ||
!fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d326) &&
(!soc_map_m_boot_rom_addr_base__3_ULE_fabric_xac_ETC___d328 ||
!fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d329) &&
(!soc_map_m_uart0_addr_base__8_ULE_fabric_xactor_ETC___d331 ||
!fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d332) ;
assign NOT_soc_map_m_mem0_controller_addr_base__6_ULE_ETC___d455 =
(!soc_map_m_mem0_controller_addr_base__6_ULE_fab_ETC___d381 ||
!fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d382) &&
(!soc_map_m_boot_rom_addr_base__3_ULE_fabric_xac_ETC___d384 ||
!fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d385) &&
(!soc_map_m_uart0_addr_base__8_ULE_fabric_xactor_ETC___d387 ||
!fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d388) ;
assign _dor1fabric_v_f_rd_mis_0$EN_deq =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master ;
assign _dor1fabric_v_f_rd_mis_1$EN_deq =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ;
assign _dor1fabric_v_f_rd_mis_2$EN_deq =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ;
assign fabric_v_f_wd_tasks_0_i_notEmpty__73_AND_fabri_ETC___d182 =
fabric_v_f_wd_tasks_0$EMPTY_N &&
CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 ;
assign fabric_v_f_wd_tasks_1_i_notEmpty__01_AND_fabri_ETC___d207 =
fabric_v_f_wd_tasks_1$EMPTY_N &&
CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 ;
assign fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d469 =
fabric_v_rg_r_beat_count_0 == fabric_v_f_rd_mis_0$D_OUT[7:0] ;
assign fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d509 =
fabric_v_rg_r_beat_count_1 == fabric_v_f_rd_mis_1$D_OUT[7:0] ;
assign fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d548 =
fabric_v_rg_r_beat_count_2 == fabric_v_f_rd_mis_2$D_OUT[7:0] ;
assign fabric_v_rg_r_err_beat_count_0_18_EQ_fabric_v__ETC___d620 =
fabric_v_rg_r_err_beat_count_0 ==
fabric_v_f_rd_err_info_0$D_OUT[11:4] ;
assign fabric_v_rg_r_err_beat_count_1_36_EQ_fabric_v__ETC___d638 =
fabric_v_rg_r_err_beat_count_1 ==
fabric_v_f_rd_err_info_1$D_OUT[11:4] ;
assign fabric_v_rg_wd_beat_count_0_88_EQ_fabric_v_f_w_ETC___d190 =
fabric_v_rg_wd_beat_count_0 == fabric_v_f_wd_tasks_0$D_OUT[7:0] ;
assign fabric_v_rg_wd_beat_count_1_13_EQ_fabric_v_f_w_ETC___d215 =
fabric_v_rg_wd_beat_count_1 == fabric_v_f_wd_tasks_1$D_OUT[7:0] ;
assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d326 =
fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] <
soc_map$m_mem0_controller_addr_lim ;
assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d329 =
fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] <
soc_map$m_boot_rom_addr_lim ;
assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d332 =
fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] <
soc_map$m_uart0_addr_lim ;
assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d21 =
fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] <
soc_map$m_mem0_controller_addr_lim ;
assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d26 =
fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] <
soc_map$m_boot_rom_addr_lim ;
assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d31 =
fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] <
soc_map$m_uart0_addr_lim ;
assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d382 =
fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] <
soc_map$m_mem0_controller_addr_lim ;
assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d385 =
fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] <
soc_map$m_boot_rom_addr_lim ;
assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d388 =
fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] <
soc_map$m_uart0_addr_lim ;
assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d90 =
fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] <
soc_map$m_mem0_controller_addr_lim ;
assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d93 =
fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] <
soc_map$m_boot_rom_addr_lim ;
assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d96 =
fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] <
soc_map$m_uart0_addr_lim ;
assign soc_map_m_boot_rom_addr_base__3_ULE_fabric_xac_ETC___d24 =
soc_map$m_boot_rom_addr_base <=
fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] ;
assign soc_map_m_boot_rom_addr_base__3_ULE_fabric_xac_ETC___d328 =
soc_map$m_boot_rom_addr_base <=
fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] ;
assign soc_map_m_boot_rom_addr_base__3_ULE_fabric_xac_ETC___d384 =
soc_map$m_boot_rom_addr_base <=
fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] ;
assign soc_map_m_boot_rom_addr_base__3_ULE_fabric_xac_ETC___d92 =
soc_map$m_boot_rom_addr_base <=
fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] ;
assign soc_map_m_mem0_controller_addr_base__6_ULE_fab_ETC___d19 =
soc_map$m_mem0_controller_addr_base <=
fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] ;
assign soc_map_m_mem0_controller_addr_base__6_ULE_fab_ETC___d325 =
soc_map$m_mem0_controller_addr_base <=
fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] ;
assign soc_map_m_mem0_controller_addr_base__6_ULE_fab_ETC___d335 =
soc_map_m_mem0_controller_addr_base__6_ULE_fab_ETC___d325 &&
fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d326 ||
soc_map_m_boot_rom_addr_base__3_ULE_fabric_xac_ETC___d328 &&
fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d329 ||
soc_map_m_uart0_addr_base__8_ULE_fabric_xactor_ETC___d331 &&
fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d332 ;
assign soc_map_m_mem0_controller_addr_base__6_ULE_fab_ETC___d34 =
soc_map_m_mem0_controller_addr_base__6_ULE_fab_ETC___d19 &&
fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d21 ||
soc_map_m_boot_rom_addr_base__3_ULE_fabric_xac_ETC___d24 &&
fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d26 ||
soc_map_m_uart0_addr_base__8_ULE_fabric_xactor_ETC___d29 &&
fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d31 ;
assign soc_map_m_mem0_controller_addr_base__6_ULE_fab_ETC___d381 =
soc_map$m_mem0_controller_addr_base <=
fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] ;
assign soc_map_m_mem0_controller_addr_base__6_ULE_fab_ETC___d391 =
soc_map_m_mem0_controller_addr_base__6_ULE_fab_ETC___d381 &&
fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d382 ||
soc_map_m_boot_rom_addr_base__3_ULE_fabric_xac_ETC___d384 &&
fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d385 ||
soc_map_m_uart0_addr_base__8_ULE_fabric_xactor_ETC___d387 &&
fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d388 ;
assign soc_map_m_mem0_controller_addr_base__6_ULE_fab_ETC___d89 =
soc_map$m_mem0_controller_addr_base <=
fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] ;
assign soc_map_m_mem0_controller_addr_base__6_ULE_fab_ETC___d99 =
soc_map_m_mem0_controller_addr_base__6_ULE_fab_ETC___d89 &&
fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d90 ||
soc_map_m_boot_rom_addr_base__3_ULE_fabric_xac_ETC___d92 &&
fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d93 ||
soc_map_m_uart0_addr_base__8_ULE_fabric_xactor_ETC___d95 &&
fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d96 ;
assign soc_map_m_uart0_addr_base__8_ULE_fabric_xactor_ETC___d29 =
soc_map$m_uart0_addr_base <=
fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] ;
assign soc_map_m_uart0_addr_base__8_ULE_fabric_xactor_ETC___d331 =
soc_map$m_uart0_addr_base <=
fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] ;
assign soc_map_m_uart0_addr_base__8_ULE_fabric_xactor_ETC___d387 =
soc_map$m_uart0_addr_base <=
fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] ;
assign soc_map_m_uart0_addr_base__8_ULE_fabric_xactor_ETC___d95 =
soc_map$m_uart0_addr_base <=
fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] ;
assign x1_avValue_rresp__h18276 =
(fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) ?
2'b10 :
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] ;
assign x1_avValue_rresp__h18902 =
(fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) ?
2'b10 :
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] ;
assign x1_avValue_rresp__h19518 =
(fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) ?
2'b10 :
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] ;
assign x__h11887 = fabric_v_rg_wd_beat_count_0 + 8'd1 ;
assign x__h12350 = fabric_v_rg_wd_beat_count_1 + 8'd1 ;
assign x__h18298 = fabric_v_rg_r_beat_count_0 + 8'd1 ;
assign x__h18924 = fabric_v_rg_r_beat_count_1 + 8'd1 ;
assign x__h19540 = fabric_v_rg_r_beat_count_2 + 8'd1 ;
assign x__h21844 = fabric_v_rg_r_err_beat_count_0 + 8'd1 ;
assign x__h22245 = fabric_v_rg_r_err_beat_count_1 + 8'd1 ;
always@(fabric_v_f_wd_tasks_0$D_OUT or
fabric_xactors_to_slaves_0_f_wr_data$FULL_N or
fabric_xactors_to_slaves_1_f_wr_data$FULL_N or
fabric_xactors_to_slaves_2_f_wr_data$FULL_N)
begin
case (fabric_v_f_wd_tasks_0$D_OUT[9:8])
2'd0:
CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 =
fabric_xactors_to_slaves_0_f_wr_data$FULL_N;
2'd1:
CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 =
fabric_xactors_to_slaves_1_f_wr_data$FULL_N;
2'd2:
CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 =
fabric_xactors_to_slaves_2_f_wr_data$FULL_N;
2'd3: CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = 1'd1;
endcase
end
always@(fabric_v_f_wd_tasks_1$D_OUT or
fabric_xactors_to_slaves_0_f_wr_data$FULL_N or
fabric_xactors_to_slaves_1_f_wr_data$FULL_N or
fabric_xactors_to_slaves_2_f_wr_data$FULL_N)
begin
case (fabric_v_f_wd_tasks_1$D_OUT[9:8])
2'd0:
CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 =
fabric_xactors_to_slaves_0_f_wr_data$FULL_N;
2'd1:
CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 =
fabric_xactors_to_slaves_1_f_wr_data$FULL_N;
2'd2:
CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 =
fabric_xactors_to_slaves_2_f_wr_data$FULL_N;
2'd3: CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = 1'd1;
endcase
end
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
fabric_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0;
fabric_rg_reset <= `BSV_ASSIGNMENT_DELAY 1'd1;
fabric_v_rg_r_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0;
fabric_v_rg_r_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0;
fabric_v_rg_r_beat_count_2 <= `BSV_ASSIGNMENT_DELAY 8'd0;
fabric_v_rg_r_err_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0;
fabric_v_rg_r_err_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0;
fabric_v_rg_wd_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0;
fabric_v_rg_wd_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0;
end
else
begin
if (fabric_cfg_verbosity$EN)
fabric_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY
fabric_cfg_verbosity$D_IN;
if (fabric_rg_reset$EN)
fabric_rg_reset <= `BSV_ASSIGNMENT_DELAY fabric_rg_reset$D_IN;
if (fabric_v_rg_r_beat_count_0$EN)
fabric_v_rg_r_beat_count_0 <= `BSV_ASSIGNMENT_DELAY
fabric_v_rg_r_beat_count_0$D_IN;
if (fabric_v_rg_r_beat_count_1$EN)
fabric_v_rg_r_beat_count_1 <= `BSV_ASSIGNMENT_DELAY
fabric_v_rg_r_beat_count_1$D_IN;
if (fabric_v_rg_r_beat_count_2$EN)
fabric_v_rg_r_beat_count_2 <= `BSV_ASSIGNMENT_DELAY
fabric_v_rg_r_beat_count_2$D_IN;
if (fabric_v_rg_r_err_beat_count_0$EN)
fabric_v_rg_r_err_beat_count_0 <= `BSV_ASSIGNMENT_DELAY
fabric_v_rg_r_err_beat_count_0$D_IN;
if (fabric_v_rg_r_err_beat_count_1$EN)
fabric_v_rg_r_err_beat_count_1 <= `BSV_ASSIGNMENT_DELAY
fabric_v_rg_r_err_beat_count_1$D_IN;
if (fabric_v_rg_wd_beat_count_0$EN)
fabric_v_rg_wd_beat_count_0 <= `BSV_ASSIGNMENT_DELAY
fabric_v_rg_wd_beat_count_0$D_IN;
if (fabric_v_rg_wd_beat_count_1$EN)
fabric_v_rg_wd_beat_count_1 <= `BSV_ASSIGNMENT_DELAY
fabric_v_rg_wd_beat_count_1$D_IN;
end
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
fabric_cfg_verbosity = 4'hA;
fabric_rg_reset = 1'h0;
fabric_v_rg_r_beat_count_0 = 8'hAA;
fabric_v_rg_r_beat_count_1 = 8'hAA;
fabric_v_rg_r_beat_count_2 = 8'hAA;
fabric_v_rg_r_err_beat_count_0 = 8'hAA;
fabric_v_rg_r_err_beat_count_1 = 8'hAA;
fabric_v_rg_wd_beat_count_0 = 8'hAA;
fabric_v_rg_wd_beat_count_1 = 8'hAA;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge CLK)
begin
#0;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
begin
v__h8721 = $stime;
#0;
end
v__h8715 = v__h8721 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d",
v__h8715,
$signed(32'd0),
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Addr { ", "awid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awaddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h9121 = $stime;
#0;
end
v__h9115 = v__h9121 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d",
v__h9115,
$signed(32'd0),
$signed(32'd1));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Addr { ", "awid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awaddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h9521 = $stime;
#0;
end
v__h9515 = v__h9521 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d",
v__h9515,
$signed(32'd0),
$signed(32'd2));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Addr { ", "awid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awaddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h9991 = $stime;
#0;
end
v__h9985 = v__h9991 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d",
v__h9985,
$signed(32'd1),
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Addr { ", "awid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awaddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h10385 = $stime;
#0;
end
v__h10379 = v__h10385 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d",
v__h10379,
$signed(32'd1),
$signed(32'd1));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Addr { ", "awid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awaddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h10779 = $stime;
#0;
end
v__h10773 = v__h10779 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d",
v__h10773,
$signed(32'd1),
$signed(32'd2));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Addr { ", "awid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awaddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
begin
v__h11161 = $stime;
#0;
end
v__h11155 = v__h11161 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_xaction_no_such_slave: m%0d -> ?",
v__h11155,
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Addr { ", "awid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awaddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h11499 = $stime;
#0;
end
v__h11493 = v__h11499 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_xaction_no_such_slave: m%0d -> ?",
v__h11493,
$signed(32'd1));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Addr { ", "awid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awaddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_88_EQ_fabric_v_f_w_ETC___d190 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
begin
v__h11982 = $stime;
#0;
end
v__h11976 = v__h11982 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_88_EQ_fabric_v_f_w_ETC___d190 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$display("%0d: %m.rl_wr_xaction_master_to_slave_data: ERROR: m%0d -> s%0d",
v__h11976,
$signed(32'd0),
fabric_v_f_wd_tasks_0$D_OUT[9:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_88_EQ_fabric_v_f_w_ETC___d190 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$display(" WLAST not set on final data beat (awlen = %0d)",
fabric_v_f_wd_tasks_0$D_OUT[7:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_88_EQ_fabric_v_f_w_ETC___d190 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_88_EQ_fabric_v_f_w_ETC___d190 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write("AXI4_Wr_Data { ", "wdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_88_EQ_fabric_v_f_w_ETC___d190 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[72:9]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_88_EQ_fabric_v_f_w_ETC___d190 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write(", ", "wstrb: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_88_EQ_fabric_v_f_w_ETC___d190 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[8:1]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_88_EQ_fabric_v_f_w_ETC___d190 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write(", ", "wlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_88_EQ_fabric_v_f_w_ETC___d190 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_88_EQ_fabric_v_f_w_ETC___d190 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write(", ", "wuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_88_EQ_fabric_v_f_w_ETC___d190 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_88_EQ_fabric_v_f_w_ETC___d190 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_rg_wd_beat_count_1_13_EQ_fabric_v_f_w_ETC___d215 &&
!fabric_xactors_from_masters_1_f_wr_data$D_OUT[0])
begin
v__h12445 = $stime;
#0;
end
v__h12439 = v__h12445 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_rg_wd_beat_count_1_13_EQ_fabric_v_f_w_ETC___d215 &&
!fabric_xactors_from_masters_1_f_wr_data$D_OUT[0])
$display("%0d: %m.rl_wr_xaction_master_to_slave_data: ERROR: m%0d -> s%0d",
v__h12439,
$signed(32'd1),
fabric_v_f_wd_tasks_1$D_OUT[9:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_rg_wd_beat_count_1_13_EQ_fabric_v_f_w_ETC___d215 &&
!fabric_xactors_from_masters_1_f_wr_data$D_OUT[0])
$display(" WLAST not set on final data beat (awlen = %0d)",
fabric_v_f_wd_tasks_1$D_OUT[7:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_rg_wd_beat_count_1_13_EQ_fabric_v_f_w_ETC___d215 &&
!fabric_xactors_from_masters_1_f_wr_data$D_OUT[0])
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_rg_wd_beat_count_1_13_EQ_fabric_v_f_w_ETC___d215 &&
!fabric_xactors_from_masters_1_f_wr_data$D_OUT[0])
$write("AXI4_Wr_Data { ", "wdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_rg_wd_beat_count_1_13_EQ_fabric_v_f_w_ETC___d215 &&
!fabric_xactors_from_masters_1_f_wr_data$D_OUT[0])
$write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[72:9]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_rg_wd_beat_count_1_13_EQ_fabric_v_f_w_ETC___d215 &&
!fabric_xactors_from_masters_1_f_wr_data$D_OUT[0])
$write(", ", "wstrb: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_rg_wd_beat_count_1_13_EQ_fabric_v_f_w_ETC___d215 &&
!fabric_xactors_from_masters_1_f_wr_data$D_OUT[0])
$write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[8:1]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_rg_wd_beat_count_1_13_EQ_fabric_v_f_w_ETC___d215 &&
!fabric_xactors_from_masters_1_f_wr_data$D_OUT[0])
$write(", ", "wlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_rg_wd_beat_count_1_13_EQ_fabric_v_f_w_ETC___d215 &&
!fabric_xactors_from_masters_1_f_wr_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_rg_wd_beat_count_1_13_EQ_fabric_v_f_w_ETC___d215 &&
!fabric_xactors_from_masters_1_f_wr_data$D_OUT[0])
$write(", ", "wuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_rg_wd_beat_count_1_13_EQ_fabric_v_f_w_ETC___d215 &&
!fabric_xactors_from_masters_1_f_wr_data$D_OUT[0])
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_rg_wd_beat_count_1_13_EQ_fabric_v_f_w_ETC___d215 &&
!fabric_xactors_from_masters_1_f_wr_data$D_OUT[0])
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
begin
v__h12820 = $stime;
#0;
end
v__h12814 = v__h12820 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d",
v__h12814,
$signed(32'd0),
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Resp { ", "bid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[5:2]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "bresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[1:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "buser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h13112 = $stime;
#0;
end
v__h13106 = v__h13112 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d",
v__h13106,
$signed(32'd0),
$signed(32'd1));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Resp { ", "bid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[5:2]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "bresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[1:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "buser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h13404 = $stime;
#0;
end
v__h13398 = v__h13404 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d",
v__h13398,
$signed(32'd0),
$signed(32'd2));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Resp { ", "bid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[5:2]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "bresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[1:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "buser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h13707 = $stime;
#0;
end
v__h13701 = v__h13707 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d",
v__h13701,
$signed(32'd1),
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Resp { ", "bid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[5:2]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "bresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[1:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "buser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h13973 = $stime;
#0;
end
v__h13967 = v__h13973 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d",
v__h13967,
$signed(32'd1),
$signed(32'd1));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Resp { ", "bid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[5:2]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "bresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[1:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "buser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h14239 = $stime;
#0;
end
v__h14233 = v__h14239 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d",
v__h14233,
$signed(32'd1),
$signed(32'd2));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Resp { ", "bid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[5:2]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "bresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[1:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "buser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
begin
v__h14503 = $stime;
#0;
end
v__h14497 = v__h14503 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_resp_err_to_master: m%0d <- err",
v__h14497,
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Resp { ", "bid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_v_f_wr_err_info_0$D_OUT);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "bresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 2'b11);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "buser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h14729 = $stime;
#0;
end
v__h14723 = v__h14729 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_resp_err_to_master: m%0d <- err",
v__h14723,
$signed(32'd1));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Resp { ", "bid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_v_f_wr_err_info_1$D_OUT);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "bresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 2'b11);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "buser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
begin
v__h15183 = $stime;
#0;
end
v__h15177 = v__h15183 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d",
v__h15177,
$signed(32'd0),
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Addr { ", "arid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "araddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "aruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h15564 = $stime;
#0;
end
v__h15558 = v__h15564 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d",
v__h15558,
$signed(32'd0),
$signed(32'd1));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Addr { ", "arid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "araddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "aruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h15945 = $stime;
#0;
end
v__h15939 = v__h15945 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d",
v__h15939,
$signed(32'd0),
$signed(32'd2));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Addr { ", "arid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "araddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "aruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h16387 = $stime;
#0;
end
v__h16381 = v__h16387 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d",
v__h16381,
$signed(32'd1),
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Addr { ", "arid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "araddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "aruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h16744 = $stime;
#0;
end
v__h16738 = v__h16744 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d",
v__h16738,
$signed(32'd1),
$signed(32'd1));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Addr { ", "arid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "araddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "aruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h17101 = $stime;
#0;
end
v__h17095 = v__h17101 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d",
v__h17095,
$signed(32'd1),
$signed(32'd2));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Addr { ", "arid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "araddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "aruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
begin
v__h17452 = $stime;
#0;
end
v__h17446 = v__h17452 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_xaction_no_such_slave: m%0d -> ?",
v__h17446,
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Addr { ", "arid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "araddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "aruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h17753 = $stime;
#0;
end
v__h17747 = v__h17753 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_xaction_no_such_slave: m%0d -> ?",
v__h17747,
$signed(32'd1));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Addr { ", "arid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "araddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "aruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d469 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
begin
v__h18161 = $stime;
#0;
end
v__h18155 = v__h18161 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d469 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d",
v__h18155,
$signed(32'd0),
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d469 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$display(" RLAST not set on final data beat (arlen = %0d)",
fabric_v_f_rd_mis_0$D_OUT[7:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d469 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d469 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d469 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d469 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d469 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d469 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d469 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("'h%h", 2'b10);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d469 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d469 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d469 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d469 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d469 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
begin
v__h18412 = $stime;
#0;
end
v__h18406 = v__h18412 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d",
v__h18406,
$signed(32'd0),
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(" r: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h",
IF_fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_ETC___d496);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d509 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
begin
v__h18787 = $stime;
#0;
end
v__h18781 = v__h18787 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d509 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d",
v__h18781,
$signed(32'd0),
$signed(32'd1));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d509 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$display(" RLAST not set on final data beat (arlen = %0d)",
fabric_v_f_rd_mis_1$D_OUT[7:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d509 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d509 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d509 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d509 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d509 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d509 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d509 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("'h%h", 2'b10);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d509 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d509 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d509 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d509 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d509 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h19028 = $stime;
#0;
end
v__h19022 = v__h19028 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d",
v__h19022,
$signed(32'd0),
$signed(32'd1));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(" r: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h",
IF_fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_ETC___d535);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d548 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
begin
v__h19403 = $stime;
#0;
end
v__h19397 = v__h19403 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d548 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d",
v__h19397,
$signed(32'd0),
$signed(32'd2));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d548 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$display(" RLAST not set on final data beat (arlen = %0d)",
fabric_v_f_rd_mis_2$D_OUT[7:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d548 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d548 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d548 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d548 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d548 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d548 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d548 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("'h%h", 2'b10);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d548 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d548 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d548 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d548 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d548 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h19644 = $stime;
#0;
end
v__h19638 = v__h19644 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d",
v__h19638,
$signed(32'd0),
$signed(32'd2));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write(" r: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h",
IF_fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_ETC___d574);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d469 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
begin
v__h20006 = $stime;
#0;
end
v__h20000 = v__h20006 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d469 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d",
v__h20000,
$signed(32'd1),
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d469 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$display(" RLAST not set on final data beat (arlen = %0d)",
fabric_v_f_rd_mis_0$D_OUT[7:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d469 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d469 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d469 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d469 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d469 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d469 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d469 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("'h%h", 2'b10);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d469 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d469 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d469 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d469 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d469 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h20257 = $stime;
#0;
end
v__h20251 = v__h20257 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d",
v__h20251,
$signed(32'd1),
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write(" r: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h",
IF_fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_ETC___d496);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d509 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
begin
v__h20587 = $stime;
#0;
end
v__h20581 = v__h20587 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d509 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d",
v__h20581,
$signed(32'd1),
$signed(32'd1));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d509 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$display(" RLAST not set on final data beat (arlen = %0d)",
fabric_v_f_rd_mis_1$D_OUT[7:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d509 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d509 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d509 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d509 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d509 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d509 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d509 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("'h%h", 2'b10);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d509 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d509 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d509 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d509 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d509 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h20828 = $stime;
#0;
end
v__h20822 = v__h20828 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d",
v__h20822,
$signed(32'd1),
$signed(32'd1));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write(" r: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h",
IF_fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_ETC___d535);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d548 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
begin
v__h21158 = $stime;
#0;
end
v__h21152 = v__h21158 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d548 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d",
v__h21152,
$signed(32'd1),
$signed(32'd2));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d548 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$display(" RLAST not set on final data beat (arlen = %0d)",
fabric_v_f_rd_mis_2$D_OUT[7:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d548 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d548 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d548 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d548 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d548 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d548 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d548 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("'h%h", 2'b10);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d548 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d548 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d548 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d548 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d548 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h21399 = $stime;
#0;
end
v__h21393 = v__h21399 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d",
v__h21393,
$signed(32'd1),
$signed(32'd2));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write(" r: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h",
IF_fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_ETC___d574);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
begin
v__h21912 = $stime;
#0;
end
v__h21906 = v__h21912 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_resp_err_to_master: m%0d <- err",
v__h21906,
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(" r: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_v_f_rd_err_info_0$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 64'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 2'b11);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0 &&
fabric_v_rg_r_err_beat_count_0_18_EQ_fabric_v__ETC___d620)
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0 &&
!fabric_v_rg_r_err_beat_count_0_18_EQ_fabric_v__ETC___d620)
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h22313 = $stime;
#0;
end
v__h22307 = v__h22313 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_resp_err_to_master: m%0d <- err",
v__h22307,
$signed(32'd1));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(" r: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_v_f_rd_err_info_1$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 64'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 2'b11);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0 &&
fabric_v_rg_r_err_beat_count_1_36_EQ_fabric_v__ETC___d638)
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0 &&
!fabric_v_rg_r_err_beat_count_1_36_EQ_fabric_v__ETC___d638)
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (fabric_rg_reset && fabric_cfg_verbosity != 4'd0)
begin
v__h5717 = $stime;
#0;
end
v__h5711 = v__h5717 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (fabric_rg_reset && fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_reset", v__h5711);
end
// synopsys translate_on
endmodule // mkFabric_AXI4
|
//wb_i2s.v
/*
Distributed under the MIT license.
Copyright (c) 2011 Dave McCoy ([email protected])
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/*
Self Defining Bus (SDB)
Set the Vendor ID (Hexidecimal 64-bit Number)
SDB_VENDOR_ID:0x800000000000C594
Set the Device ID (Hexcidecimal 32-bit Number)
SDB_DEVICE_ID:0x0000000A
Set the version of the Core XX.XXX.XXX Example: 01.000.000
SDB_CORE_VERSION:00.000.001
Set the Device Name: (19 UNICODE characters)
SDB_NAME:wb_i2s
Set the class of the device (16 bits) Set as 0
SDB_ABI_CLASS:0
Set the ABI Major Version: (8-bits)
SDB_ABI_VERSION_MAJOR:0x0C
Set the ABI Minor Version (8-bits)
SDB_ABI_VERSION_MINOR:0x01
Set the Module URL (63 Unicode Characters)
SDB_MODULE_URL:http://www.example.com
Set the date of module YYYY/MM/DD
SDB_DATE:2015/01/07
Device is executable (True/False)
SDB_EXECUTABLE:True
Device is readable (True/False)
SDB_READABLE:True
Device is writeable (True/False)
SDB_WRITEABLE:True
Device Size: Number of Registers
SDB_SIZE:8
*/
`define DEFAULT_MEMORY_TIMEOUT 300
`include "project_defines.v"
`include "i2s_defines.v"
`timescale 1 ns/1 ps
`define DEFAULT_CLOCK_DIVISOR (`CLOCK_RATE / (`AUDIO_RATE * `AUDIO_BITS * `AUDIO_CHANNELS)) / 2
module wb_i2s (
input clk,
input rst,
//wishbone slave signals
input i_wbs_we,
input i_wbs_stb,
input i_wbs_cyc,
input [3:0] i_wbs_sel,
input [31:0] i_wbs_adr,
input [31:0] i_wbs_dat,
output reg [31:0] o_wbs_dat,
output reg o_wbs_ack,
output reg o_wbs_int,
//master control signal for memory arbitration
output mem_o_we,
output mem_o_stb,
output mem_o_cyc,
output [3:0] mem_o_sel,
output [31:0] mem_o_adr,
output [31:0] mem_o_dat,
input [31:0] mem_i_dat,
input mem_i_ack,
input mem_i_int,
//status
output writer_starved,
//i2s signals
output phy_mclock,
output phy_clock,
output phy_data,
output phy_lr,
output [31:0] debug
);
localparam REG_CONTROL = 32'h00000000;
localparam REG_STATUS = 32'h00000001;
localparam REG_CLOCK_RATE = 32'h00000002;
localparam REG_CLOCK_DIVIDER = 32'h00000003;
localparam REG_MEM_0_BASE = 32'h00000004;
localparam REG_MEM_0_SIZE = 32'h00000005;
localparam REG_MEM_1_BASE = 32'h00000006;
localparam REG_MEM_1_SIZE = 32'h00000007;
//control bit definition
localparam CONTROL_ENABLE = 0;
localparam CONTROL_ENABLE_INTERRUPT = 1;
localparam CONTROL_POST_FIFO_WAVE = 2;
localparam CONTROL_PRE_FIFO_WAVE = 3;
//status bit definition
localparam STATUS_MEMORY_0_EMPTY = 0;
localparam STATUS_MEMORY_1_EMPTY = 1;
//Reg/Wire
wire timeout_elapsed;
reg timeout_enable;
reg [31:0] timeout_count;
reg [31:0] timeout_value;
reg enable_mem_read;
reg memory_data_strobe;
reg enable_strobe;
reg [31:0] control;
wire [31:0] status;
reg [31:0] clock_divider = 1;
reg [23:0] request_count;
reg memory_ready;
reg active_bank;
//Mem 2 PPFIFO
reg [31:0] r_memory_0_base;
reg [31:0] r_memory_0_size;
wire [31:0] w_memory_0_count;
reg r_memory_0_new_data;
wire w_memory_0_empty;
wire [31:0] w_default_mem_0_base;
reg [31:0] r_memory_1_base;
reg [31:0] r_memory_1_size;
wire [31:0] w_memory_1_count;
reg r_memory_1_new_data;
wire w_memory_1_empty;
wire [31:0] w_default_mem_1_base;
wire w_read_finished;
//control
wire enable;
wire enable_interrupt;
wire post_fifo_wave_en;
wire pre_fifo_wave_en;
//status
wire [23:0] wfifo_size;
reg [23:0] write_count;
reg [23:0] memory_write_count;
reg [23:0] memory_write_size;
wire [1:0] wfifo_ready;
wire [1:0] wfifo_activate;
wire wfifo_strobe;
wire [31:0] wfifo_data;
reg [3:0] state;
i2s_controller controller (
.rst (rst ),
.clk (clk ),
.enable (enable ),
.post_fifo_wave_en (post_fifo_wave_en ),
.clock_divider (clock_divider ),
.wfifo_size (wfifo_size ),
.wfifo_ready (wfifo_ready ),
.wfifo_activate (wfifo_activate ),
.wfifo_strobe (wfifo_strobe ),
.wfifo_data (wfifo_data ),
.i2s_mclock (phy_mclock ),
.i2s_clock (phy_clock ),
.i2s_data (phy_data ),
.i2s_lr (phy_lr )
);
wb_mem_2_ppfifo m2p(
.clk (clk ),
.rst (rst ),
.debug (debug ),
//Control
.i_enable (enable ),
.i_memory_0_base (r_memory_0_base ),
.i_memory_0_size (r_memory_0_size ),
.o_memory_0_count (w_memory_0_count ),
.i_memory_0_new_data (r_memory_0_new_data ),
.o_memory_0_empty (w_memory_0_empty ),
.o_default_mem_0_base (w_default_mem_0_base ),
.i_memory_1_base (r_memory_1_base ),
.i_memory_1_size (r_memory_1_size ),
.o_memory_1_count (w_memory_1_count ),
.i_memory_1_new_data (r_memory_1_new_data ),
.o_memory_1_empty (w_memory_1_empty ),
.o_default_mem_1_base (w_default_mem_1_base ),
.o_read_finished (w_read_finished ),
//master control signal for memory arbitration
.o_mem_we (mem_o_we ),
.o_mem_stb (mem_o_stb ),
.o_mem_cyc (mem_o_cyc ),
.o_mem_sel (mem_o_sel ),
.o_mem_adr (mem_o_adr ),
.o_mem_dat (mem_o_dat ),
.i_mem_dat (mem_i_dat ),
.i_mem_ack (mem_i_ack ),
.i_mem_int (mem_i_int ),
//Ping Pong FIFO Interface
.i_ppfifo_rdy (wfifo_ready ),
.o_ppfifo_act (wfifo_activate ),
.i_ppfifo_size (wfifo_size ),
.o_ppfifo_stb (wfifo_strobe ),
.o_ppfifo_data (wfifo_data )
);
//Asynchronous Logic
assign enable = control[CONTROL_ENABLE];
assign enable_interrupt = control[CONTROL_ENABLE_INTERRUPT];
assign post_fifo_wave_en = control[CONTROL_POST_FIFO_WAVE];
assign pre_fifo_wave_en = control[CONTROL_PRE_FIFO_WAVE];
assign status[STATUS_MEMORY_0_EMPTY] = w_memory_0_empty;
assign status[STATUS_MEMORY_1_EMPTY] = w_memory_1_empty;
assign status[31:2] = 0;
//assign debug[1:0] = wfifo_ready;
//assign debug[3:2] = wfifo_activate;
//assign debug[4] = wfifo_strobe;
//assign debug[5] = wfifo_data[31];
//assign debug[31:16] = wfifo_data[23:8];
//blocks
always @ (posedge clk) begin
if (rst) begin
o_wbs_dat <= 32'h0;
o_wbs_ack <= 0;
timeout_enable <= 0;
timeout_value <= `DEFAULT_MEMORY_TIMEOUT;
control <= 0;
//Default base, user can change this from the API
r_memory_0_base <= w_default_mem_0_base;
r_memory_1_base <= w_default_mem_1_base;
//Nothing in the memory initially
r_memory_0_size <= 0;
r_memory_1_size <= 0;
r_memory_0_new_data <= 0;
r_memory_1_new_data <= 0;
clock_divider <= `DEFAULT_CLOCK_DIVISOR;
end
else begin
r_memory_0_new_data <= 0;
r_memory_1_new_data <= 0;
//when the master acks our ack, then put our ack down
if (o_wbs_ack & ~ i_wbs_stb)begin
o_wbs_ack <= 0;
end
if (i_wbs_stb & i_wbs_cyc) begin
//master is requesting somethign
if (i_wbs_we) begin
//write request
case (i_wbs_adr)
REG_CONTROL: begin
control <= i_wbs_dat;
if (i_wbs_dat[CONTROL_ENABLE]) begin
$display ("-----------------------------------------------------------");
$display ("WB_I2S: Core Enable");
$display ("-----------------------------------------------------------");
end
end
REG_CLOCK_DIVIDER: begin
clock_divider <= i_wbs_dat;
end
REG_MEM_0_BASE: begin
r_memory_0_base <= i_wbs_dat;
end
REG_MEM_0_SIZE: begin
r_memory_0_size <= i_wbs_dat;
if (i_wbs_dat > 0) begin
r_memory_0_new_data <= 1;
end
end
REG_MEM_1_BASE: begin
r_memory_1_base <= i_wbs_dat;
end
REG_MEM_1_SIZE: begin
r_memory_1_size <= i_wbs_dat;
if (i_wbs_dat > 0) begin
r_memory_1_new_data <= 1;
end
end
default: begin
end
endcase
end
else begin
//read request
case (i_wbs_adr)
REG_CONTROL: begin
o_wbs_dat <= control;
end
REG_STATUS: begin
o_wbs_dat <= status;
end
REG_CLOCK_RATE: begin
o_wbs_dat <= `CLOCK_RATE;
end
REG_CLOCK_DIVIDER: begin
o_wbs_dat <= clock_divider;
end
REG_MEM_0_BASE: begin
o_wbs_dat <= r_memory_0_base;
end
REG_MEM_0_SIZE: begin
o_wbs_dat <= w_memory_0_count;
end
REG_MEM_1_BASE: begin
o_wbs_dat <= r_memory_1_base;
end
REG_MEM_1_SIZE: begin
o_wbs_dat <= w_memory_1_count;
end
//add as many ADDR_X you need here
default: begin
o_wbs_dat <= 32'h00;
end
endcase
end
o_wbs_ack <= 1;
end
end
end
//initerrupt controller
always @ (posedge clk) begin
if (rst) begin
o_wbs_int <= 0;
end
else if (enable) begin
if (!w_memory_0_empty && !w_memory_1_empty) begin
o_wbs_int <= 0;
end
if (i_wbs_stb) begin
//de-assert the interrupt on wbs transactions so I can launch another
//interrupt when the wbs is de-asserted
o_wbs_int <= 0;
end
else if (w_memory_0_empty || w_memory_1_empty) begin
o_wbs_int <= 1;
end
end
else begin
//if we're not enable de-assert interrupt
o_wbs_int <= 0;
end
end
always @ (posedge clk) begin
if (wfifo_strobe) begin
$display ("\tI2S MEM CONTROLLER: Wrote: %h: Request: %h", wfifo_data, wfifo_size);
end
end
endmodule
|
module Sdram_Control_4Port(
// HOST Side
REF_CLK,
RESET_N,
CLK,
// FIFO Write Side 1
WR1_DATA,
WR1,
WR1_ADDR,
WR1_MAX_ADDR,
WR1_LENGTH,
WR1_LOAD,
WR1_CLK,
WR1_FULL,
WR1_USE,
// FIFO Write Side 2
WR2_DATA,
WR2,
WR2_ADDR,
WR2_MAX_ADDR,
WR2_LENGTH,
WR2_LOAD,
WR2_CLK,
WR2_FULL,
WR2_USE,
// FIFO Read Side 1
RD1_DATA,
RD1,
RD1_ADDR,
RD1_MAX_ADDR,
RD1_LENGTH,
RD1_LOAD,
RD1_CLK,
RD1_EMPTY,
RD1_USE,
// FIFO Read Side 2
RD2_DATA,
RD2,
RD2_ADDR,
RD2_MAX_ADDR,
RD2_LENGTH,
RD2_LOAD,
RD2_CLK,
RD2_EMPTY,
RD2_USE,
// SDRAM Side
SA,
BA,
CS_N,
CKE,
RAS_N,
CAS_N,
WE_N,
DQ,
DQM,
SDR_CLK,
CLK_18
);
`include "Sdram_Params.h"
// HOST Side
input REF_CLK; //System Clock
input RESET_N; //System Reset
// FIFO Write Side 1
input [`DSIZE-1:0] WR1_DATA; //Data input
input WR1; //Write Request
input [`ASIZE-1:0] WR1_ADDR; //Write start address
input [`ASIZE-1:0] WR1_MAX_ADDR; //Write max address
input [8:0] WR1_LENGTH; //Write length
input WR1_LOAD; //Write register load & fifo clear
input WR1_CLK; //Write fifo clock
output WR1_FULL; //Write fifo full
output [15:0] WR1_USE; //Write fifo usedw
// FIFO Write Side 2
input [`DSIZE-1:0] WR2_DATA; //Data input
input WR2; //Write Request
input [`ASIZE-1:0] WR2_ADDR; //Write start address
input [`ASIZE-1:0] WR2_MAX_ADDR; //Write max address
input [8:0] WR2_LENGTH; //Write length
input WR2_LOAD; //Write register load & fifo clear
input WR2_CLK; //Write fifo clock
output WR2_FULL; //Write fifo full
output [15:0] WR2_USE; //Write fifo usedw
// FIFO Read Side 1
output [`DSIZE-1:0] RD1_DATA; //Data output
input RD1; //Read Request
input [`ASIZE-1:0] RD1_ADDR; //Read start address
input [`ASIZE-1:0] RD1_MAX_ADDR; //Read max address
input [8:0] RD1_LENGTH; //Read length
input RD1_LOAD; //Read register load & fifo clear
input RD1_CLK; //Read fifo clock
output RD1_EMPTY; //Read fifo empty
output [15:0] RD1_USE; //Read fifo usedw
// FIFO Read Side 2
output [`DSIZE-1:0] RD2_DATA; //Data output
input RD2; //Read Request
input [`ASIZE-1:0] RD2_ADDR; //Read start address
input [`ASIZE-1:0] RD2_MAX_ADDR; //Read max address
input [8:0] RD2_LENGTH; //Read length
input RD2_LOAD; //Read register load & fifo clear
input RD2_CLK; //Read fifo clock
output RD2_EMPTY; //Read fifo empty
output [15:0] RD2_USE; //Read fifo usedw
// SDRAM Side
output [11:0] SA; //SDRAM address output
output [1:0] BA; //SDRAM bank address
output [1:0] CS_N; //SDRAM Chip Selects
output CKE; //SDRAM clock enable
output RAS_N; //SDRAM Row address Strobe
output CAS_N; //SDRAM Column address Strobe
output WE_N; //SDRAM write enable
inout [`DSIZE-1:0] DQ; //SDRAM data bus
output [`DSIZE/8-1:0] DQM; //SDRAM data mask lines
output SDR_CLK; //SDRAM clock
// Internal Registers/Wires
// Controller
reg [`ASIZE-1:0] mADDR; //Internal address
reg [8:0] mLENGTH; //Internal length
reg [`ASIZE-1:0] rWR1_ADDR; //Register write address
reg [`ASIZE-1:0] rWR2_ADDR; //Register write address
reg [`ASIZE-1:0] rRD1_ADDR; //Register read address
reg [`ASIZE-1:0] rRD2_ADDR; //Register read address
reg [1:0] WR_MASK; //Write port active mask
reg [1:0] RD_MASK; //Read port active mask
reg mWR_DONE; //Flag write done, 1 pulse SDR_CLK
reg mRD_DONE; //Flag read done, 1 pulse SDR_CLK
reg mWR,Pre_WR; //Internal WR edge capture
reg mRD,Pre_RD; //Internal RD edge capture
reg [9:0] ST; //Controller status
reg [1:0] CMD; //Controller command
reg PM_STOP; //Flag page mode stop
reg PM_DONE; //Flag page mode done
reg Read; //Flag read active
reg Write; //Flag write active
reg [`DSIZE-1:0] mDATAOUT; //Controller Data output
wire [`DSIZE-1:0] mDATAIN; //Controller Data input
wire [`DSIZE-1:0] mDATAIN1; //Controller Data input 1
wire [`DSIZE-1:0] mDATAIN2; //Controller Data input 2
wire CMDACK; //Controller command acknowledgement
// DRAM Control
reg [`DSIZE/8-1:0] DQM; //SDRAM data mask lines
reg [11:0] SA; //SDRAM address output
reg [1:0] BA; //SDRAM bank address
reg [1:0] CS_N; //SDRAM Chip Selects
reg CKE; //SDRAM clock enable
reg RAS_N; //SDRAM Row address Strobe
reg CAS_N; //SDRAM Column address Strobe
reg WE_N; //SDRAM write enable
wire [`DSIZE-1:0] DQOUT; //SDRAM data out link
wire [`DSIZE/8-1:0] IDQM; //SDRAM data mask lines
wire [11:0] ISA; //SDRAM address output
wire [1:0] IBA; //SDRAM bank address
wire [1:0] ICS_N; //SDRAM Chip Selects
wire ICKE; //SDRAM clock enable
wire IRAS_N; //SDRAM Row address Strobe
wire ICAS_N; //SDRAM Column address Strobe
wire IWE_N; //SDRAM write enable
// FIFO Control
reg OUT_VALID; //Output data request to read side fifo
reg IN_REQ; //Input data request to write side fifo
wire [15:0] write_side_fifo_rusedw1;
wire [15:0] read_side_fifo_wusedw1;
wire [15:0] write_side_fifo_rusedw2;
wire [15:0] read_side_fifo_wusedw2;
// DRAM Internal Control
wire [`ASIZE-1:0] saddr;
wire load_mode;
wire nop;
wire reada;
wire writea;
wire refresh;
wire precharge;
wire oe;
wire ref_ack;
wire ref_req;
wire init_req;
wire cm_ack;
wire active;
output CLK;
output wire CLK_18;
Sdram_PLL sdram_pll1 (
.inclk0(REF_CLK),
.c0(CLK),
.c1(SDR_CLK),
.c2(CLK_18)
);
control_interface control1 (
.CLK(CLK),
.RESET_N(RESET_N),
.CMD(CMD),
.ADDR(mADDR),
.REF_ACK(ref_ack),
.CM_ACK(cm_ack),
.NOP(nop),
.READA(reada),
.WRITEA(writea),
.REFRESH(refresh),
.PRECHARGE(precharge),
.LOAD_MODE(load_mode),
.SADDR(saddr),
.REF_REQ(ref_req),
.INIT_REQ(init_req),
.CMD_ACK(CMDACK)
);
command command1(
.CLK(CLK),
.RESET_N(RESET_N),
.SADDR(saddr),
.NOP(nop),
.READA(reada),
.WRITEA(writea),
.REFRESH(refresh),
.LOAD_MODE(load_mode),
.PRECHARGE(precharge),
.REF_REQ(ref_req),
.INIT_REQ(init_req),
.REF_ACK(ref_ack),
.CM_ACK(cm_ack),
.OE(oe),
.PM_STOP(PM_STOP),
.PM_DONE(PM_DONE),
.SA(ISA),
.BA(IBA),
.CS_N(ICS_N),
.CKE(ICKE),
.RAS_N(IRAS_N),
.CAS_N(ICAS_N),
.WE_N(IWE_N)
);
sdr_data_path data_path1(
.CLK(CLK),
.RESET_N(RESET_N),
.DATAIN(mDATAIN),
.DM(2'b00),
.DQOUT(DQOUT),
.DQM(IDQM)
);
Sdram_WR_FIFO write_fifo1(
.data(WR1_DATA),
.wrreq(WR1),
.wrclk(WR1_CLK),
.aclr(WR1_LOAD),
.rdreq(IN_REQ&WR_MASK[0]),
.rdclk(CLK),
.q(mDATAIN1),
.wrfull(WR1_FULL),
.wrusedw(WR1_USE),
.rdusedw(write_side_fifo_rusedw1)
);
Sdram_WR_FIFO write_fifo2(
.data(WR2_DATA),
.wrreq(WR2),
.wrclk(WR2_CLK),
.aclr(WR2_LOAD),
.rdreq(IN_REQ&WR_MASK[1]),
.rdclk(CLK),
.q(mDATAIN2),
.wrfull(WR2_FULL),
.wrusedw(WR2_USE),
.rdusedw(write_side_fifo_rusedw2)
);
assign mDATAIN = (WR_MASK[0]) ? mDATAIN1 :
mDATAIN2 ;
Sdram_RD_FIFO read_fifo1(
.data(mDATAOUT),
.wrreq(OUT_VALID&RD_MASK[0]),
.wrclk(CLK),
.aclr(RD1_LOAD),
.rdreq(RD1),
.rdclk(RD1_CLK),
.q(RD1_DATA),
.wrusedw(read_side_fifo_wusedw1),
.rdempty(RD1_EMPTY),
.rdusedw(RD1_USE)
);
Sdram_RD_FIFO read_fifo2(
.data(mDATAOUT),
.wrreq(OUT_VALID&RD_MASK[1]),
.wrclk(CLK),
.aclr(RD2_LOAD),
.rdreq(RD2),
.rdclk(RD2_CLK),
.q(RD2_DATA),
.wrusedw(read_side_fifo_wusedw2),
.rdempty(RD2_EMPTY),
.rdusedw(RD2_USE)
);
always @(posedge CLK)
begin
SA <= (ST==SC_CL+mLENGTH) ? 12'h200 : ISA;
BA <= IBA;
CS_N <= ICS_N;
CKE <= ICKE;
RAS_N <= (ST==SC_CL+mLENGTH) ? 1'b0 : IRAS_N;
CAS_N <= (ST==SC_CL+mLENGTH) ? 1'b1 : ICAS_N;
WE_N <= (ST==SC_CL+mLENGTH) ? 1'b0 : IWE_N;
PM_STOP <= (ST==SC_CL+mLENGTH) ? 1'b1 : 1'b0;
PM_DONE <= (ST==SC_CL+SC_RCD+mLENGTH+2) ? 1'b1 : 1'b0;
DQM <= ( active && (ST>=SC_CL) ) ? ( ((ST==SC_CL+mLENGTH) && Write)? 2'b11 : 2'b00 ) : 2'b11 ;
mDATAOUT<= DQ;
end
assign DQ = oe ? DQOUT : `DSIZE'hzzzz;
assign active = Read | Write;
always@(posedge CLK or negedge RESET_N)
begin
if(RESET_N==0)
begin
CMD <= 0;
ST <= 0;
Pre_RD <= 0;
Pre_WR <= 0;
Read <= 0;
Write <= 0;
OUT_VALID <= 0;
IN_REQ <= 0;
mWR_DONE <= 0;
mRD_DONE <= 0;
end
else
begin
Pre_RD <= mRD;
Pre_WR <= mWR;
case(ST)
0: begin
if({Pre_RD,mRD}==2'b01)
begin
Read <= 1;
Write <= 0;
CMD <= 2'b01;
ST <= 1;
end
else if({Pre_WR,mWR}==2'b01)
begin
Read <= 0;
Write <= 1;
CMD <= 2'b10;
ST <= 1;
end
end
1: begin
if(CMDACK==1)
begin
CMD<=2'b00;
ST<=2;
end
end
default:
begin
if(ST!=SC_CL+SC_RCD+mLENGTH+1)
ST<=ST+1;
else
ST<=0;
end
endcase
if(Read)
begin
if(ST==SC_CL+SC_RCD+1)
OUT_VALID <= 1;
else if(ST==SC_CL+SC_RCD+mLENGTH+1)
begin
OUT_VALID <= 0;
Read <= 0;
mRD_DONE <= 1;
end
end
else
mRD_DONE <= 0;
if(Write)
begin
if(ST==SC_CL-1)
IN_REQ <= 1;
else if(ST==SC_CL+mLENGTH-1)
IN_REQ <= 0;
else if(ST==SC_CL+SC_RCD+mLENGTH)
begin
Write <= 0;
mWR_DONE<= 1;
end
end
else
mWR_DONE<= 0;
end
end
// Internal Address & Length Control
always@(posedge CLK or negedge RESET_N)
begin
if(!RESET_N)
begin
rWR1_ADDR <= WR1_ADDR;
rWR2_ADDR <= WR2_ADDR;
rRD1_ADDR <= RD1_ADDR;
rRD2_ADDR <= RD2_ADDR;
end
else
begin
// Write Side 1
if(WR1_LOAD)
rWR1_ADDR <= WR1_ADDR;
else if(mWR_DONE&WR_MASK[0])
begin
if(rWR1_ADDR<WR1_MAX_ADDR-WR1_LENGTH)
rWR1_ADDR <= rWR1_ADDR+WR1_LENGTH;
else
rWR1_ADDR <= WR1_ADDR;
end
// Write Side 2
if(WR2_LOAD)
rWR2_ADDR <= WR2_ADDR;
else if(mWR_DONE&WR_MASK[1])
begin
if(rWR2_ADDR<WR2_MAX_ADDR-WR2_LENGTH)
rWR2_ADDR <= rWR2_ADDR+WR2_LENGTH;
else
rWR2_ADDR <= WR2_ADDR;
end
// Read Side 1
if(RD1_LOAD)
rRD1_ADDR <= RD1_ADDR;
else if(mRD_DONE&RD_MASK[0])
begin
if(rRD1_ADDR<RD1_MAX_ADDR-RD1_LENGTH)
rRD1_ADDR <= rRD1_ADDR+RD1_LENGTH;
else
rRD1_ADDR <= RD1_ADDR;
end
// Read Side 2
if(RD2_LOAD)
rRD2_ADDR <= RD2_ADDR;
else if(mRD_DONE&RD_MASK[1])
begin
if(rRD2_ADDR<RD2_MAX_ADDR-RD2_LENGTH)
rRD2_ADDR <= rRD2_ADDR+RD2_LENGTH;
else
rRD2_ADDR <= RD2_ADDR;
end
end
end
// Auto Read/Write Control
always@(posedge CLK or negedge RESET_N)
begin
if(!RESET_N)
begin
mWR <= 0;
mRD <= 0;
mADDR <= 0;
mLENGTH <= 0;
WR_MASK <= 0;
RD_MASK <= 0;
end
else
begin
if( (mWR==0) && (mRD==0) && (ST==0) &&
(WR_MASK==0) && (RD_MASK==0) &&
(WR1_LOAD==0) && (RD1_LOAD==0) &&
(WR2_LOAD==0) && (RD2_LOAD==0) )
begin
// Read Side 1
if( (read_side_fifo_wusedw1 < RD1_LENGTH) )
begin
mADDR <= rRD1_ADDR;
mLENGTH <= RD1_LENGTH;
WR_MASK <= 2'b00;
RD_MASK <= 2'b01;
mWR <= 0;
mRD <= 1;
end
// Read Side 2
else if( (read_side_fifo_wusedw2 < RD2_LENGTH) )
begin
mADDR <= rRD2_ADDR;
mLENGTH <= RD2_LENGTH;
WR_MASK <= 2'b00;
RD_MASK <= 2'b10;
mWR <= 0;
mRD <= 1;
end
// Write Side 1
else if( (write_side_fifo_rusedw1 >= WR1_LENGTH) && (WR1_LENGTH!=0) )
begin
mADDR <= rWR1_ADDR;
mLENGTH <= WR1_LENGTH;
WR_MASK <= 2'b01;
RD_MASK <= 2'b00;
mWR <= 1;
mRD <= 0;
end
// Write Side 2
else if( (write_side_fifo_rusedw2 >= WR2_LENGTH) && (WR2_LENGTH!=0) )
begin
mADDR <= rWR2_ADDR;
mLENGTH <= WR2_LENGTH;
WR_MASK <= 2'b10;
RD_MASK <= 2'b00;
mWR <= 1;
mRD <= 0;
end
end
if(mWR_DONE)
begin
WR_MASK <= 0;
mWR <= 0;
end
if(mRD_DONE)
begin
RD_MASK <= 0;
mRD <= 0;
end
end
end
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Mon Feb 13 12:47:50 2017
// Host : WK117 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// C:/Users/aholzer/Documents/new/Arty-BSD/src/bd/system/ip/system_axi_gpio_led_0/system_axi_gpio_led_0_sim_netlist.v
// Design : system_axi_gpio_led_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7a35ticsg324-1L
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "system_axi_gpio_led_0,axi_gpio,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "axi_gpio,Vivado 2016.4" *)
(* NotValidForBitStream *)
module system_axi_gpio_led_0
(s_axi_aclk,
s_axi_aresetn,
s_axi_awaddr,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rvalid,
s_axi_rready,
gpio_io_i,
gpio_io_o,
gpio_io_t,
gpio2_io_i,
gpio2_io_o,
gpio2_io_t);
(* x_interface_info = "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK" *) input s_axi_aclk;
(* x_interface_info = "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST" *) input s_axi_aresetn;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *) input [8:0]s_axi_awaddr;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *) input s_axi_awvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *) output s_axi_awready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *) input [31:0]s_axi_wdata;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *) input [3:0]s_axi_wstrb;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *) input s_axi_wvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *) output s_axi_wready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *) output [1:0]s_axi_bresp;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *) output s_axi_bvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *) input s_axi_bready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *) input [8:0]s_axi_araddr;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *) input s_axi_arvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *) output s_axi_arready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *) output [31:0]s_axi_rdata;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *) output [1:0]s_axi_rresp;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *) output s_axi_rvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *) input s_axi_rready;
(* x_interface_info = "xilinx.com:interface:gpio:1.0 GPIO TRI_I" *) input [3:0]gpio_io_i;
(* x_interface_info = "xilinx.com:interface:gpio:1.0 GPIO TRI_O" *) output [3:0]gpio_io_o;
(* x_interface_info = "xilinx.com:interface:gpio:1.0 GPIO TRI_T" *) output [3:0]gpio_io_t;
(* x_interface_info = "xilinx.com:interface:gpio:1.0 GPIO2 TRI_I" *) input [11:0]gpio2_io_i;
(* x_interface_info = "xilinx.com:interface:gpio:1.0 GPIO2 TRI_O" *) output [11:0]gpio2_io_o;
(* x_interface_info = "xilinx.com:interface:gpio:1.0 GPIO2 TRI_T" *) output [11:0]gpio2_io_t;
wire [11:0]gpio2_io_i;
wire [11:0]gpio2_io_o;
wire [11:0]gpio2_io_t;
wire [3:0]gpio_io_i;
wire [3:0]gpio_io_o;
wire [3:0]gpio_io_t;
wire s_axi_aclk;
wire [8:0]s_axi_araddr;
wire s_axi_aresetn;
wire s_axi_arready;
wire s_axi_arvalid;
wire [8:0]s_axi_awaddr;
wire s_axi_awready;
wire s_axi_awvalid;
wire s_axi_bready;
wire [1:0]s_axi_bresp;
wire s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire s_axi_rready;
wire [1:0]s_axi_rresp;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire s_axi_wready;
wire [3:0]s_axi_wstrb;
wire s_axi_wvalid;
wire NLW_U0_ip2intc_irpt_UNCONNECTED;
(* C_ALL_INPUTS = "0" *)
(* C_ALL_INPUTS_2 = "0" *)
(* C_ALL_OUTPUTS = "0" *)
(* C_ALL_OUTPUTS_2 = "0" *)
(* C_DOUT_DEFAULT = "0" *)
(* C_DOUT_DEFAULT_2 = "0" *)
(* C_FAMILY = "artix7" *)
(* C_GPIO2_WIDTH = "12" *)
(* C_GPIO_WIDTH = "4" *)
(* C_INTERRUPT_PRESENT = "0" *)
(* C_IS_DUAL = "1" *)
(* C_S_AXI_ADDR_WIDTH = "9" *)
(* C_S_AXI_DATA_WIDTH = "32" *)
(* C_TRI_DEFAULT = "-1" *)
(* C_TRI_DEFAULT_2 = "-1" *)
(* downgradeipidentifiedwarnings = "yes" *)
(* ip_group = "LOGICORE" *)
system_axi_gpio_led_0_axi_gpio U0
(.gpio2_io_i(gpio2_io_i),
.gpio2_io_o(gpio2_io_o),
.gpio2_io_t(gpio2_io_t),
.gpio_io_i(gpio_io_i),
.gpio_io_o(gpio_io_o),
.gpio_io_t(gpio_io_t),
.ip2intc_irpt(NLW_U0_ip2intc_irpt_UNCONNECTED),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr(s_axi_araddr),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awready(s_axi_awready),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(s_axi_bresp),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(s_axi_rresp),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wready(s_axi_wready),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wvalid(s_axi_wvalid));
endmodule
(* ORIG_REF_NAME = "GPIO_Core" *)
module system_axi_gpio_led_0_GPIO_Core
(GPIO2_DBus_i,
GPIO_DBus_i,
GPIO_xferAck_i,
gpio_xferAck_Reg,
ip2bus_rdack_i,
ip2bus_wrack_i_D1_reg,
gpio_io_o,
gpio_io_t,
gpio2_io_o,
gpio2_io_t,
Q,
\Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28]_0 ,
Read_Reg_Rst,
Read_Reg2_In,
s_axi_aclk,
Read_Reg_In,
SS,
bus2ip_rnw,
bus2ip_cs,
gpio_io_i,
gpio2_io_i,
E,
D,
bus2ip_rnw_i_reg,
bus2ip_rnw_i_reg_0,
bus2ip_rnw_i_reg_1);
output [11:0]GPIO2_DBus_i;
output [3:0]GPIO_DBus_i;
output GPIO_xferAck_i;
output gpio_xferAck_Reg;
output ip2bus_rdack_i;
output ip2bus_wrack_i_D1_reg;
output [3:0]gpio_io_o;
output [3:0]gpio_io_t;
output [11:0]gpio2_io_o;
output [11:0]gpio2_io_t;
output [11:0]Q;
output [3:0]\Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28]_0 ;
input Read_Reg_Rst;
input [0:11]Read_Reg2_In;
input s_axi_aclk;
input [0:3]Read_Reg_In;
input [0:0]SS;
input bus2ip_rnw;
input bus2ip_cs;
input [3:0]gpio_io_i;
input [11:0]gpio2_io_i;
input [0:0]E;
input [11:0]D;
input [0:0]bus2ip_rnw_i_reg;
input [0:0]bus2ip_rnw_i_reg_0;
input [0:0]bus2ip_rnw_i_reg_1;
wire [11:0]D;
wire [3:0]\Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28]_0 ;
wire [0:0]E;
wire [11:0]GPIO2_DBus_i;
wire [3:0]GPIO_DBus_i;
wire GPIO_xferAck_i;
wire [11:0]Q;
wire [0:11]Read_Reg2_In;
wire [0:3]Read_Reg_In;
wire Read_Reg_Rst;
wire [0:0]SS;
wire bus2ip_cs;
wire bus2ip_rnw;
wire [0:0]bus2ip_rnw_i_reg;
wire [0:0]bus2ip_rnw_i_reg_0;
wire [0:0]bus2ip_rnw_i_reg_1;
wire [11:0]gpio2_io_i;
wire [0:11]gpio2_io_i_d2;
wire [11:0]gpio2_io_o;
wire [11:0]gpio2_io_t;
wire [3:0]gpio_io_i;
wire [0:3]gpio_io_i_d2;
wire [3:0]gpio_io_o;
wire [3:0]gpio_io_t;
wire gpio_xferAck_Reg;
wire iGPIO_xferAck;
wire ip2bus_rdack_i;
wire ip2bus_wrack_i_D1_reg;
wire s_axi_aclk;
system_axi_gpio_led_0_cdc_sync \Dual.INPUT_DOUBLE_REGS4
(.gpio_io_i(gpio_io_i),
.s_axi_aclk(s_axi_aclk),
.scndry_vect_out({gpio_io_i_d2[0],gpio_io_i_d2[1],gpio_io_i_d2[2],gpio_io_i_d2[3]}));
system_axi_gpio_led_0_cdc_sync__parameterized0 \Dual.INPUT_DOUBLE_REGS5
(.gpio2_io_i(gpio2_io_i),
.s_axi_aclk(s_axi_aclk),
.scndry_vect_out({gpio2_io_i_d2[0],gpio2_io_i_d2[1],gpio2_io_i_d2[2],gpio2_io_i_d2[3],gpio2_io_i_d2[4],gpio2_io_i_d2[5],gpio2_io_i_d2[6],gpio2_io_i_d2[7],gpio2_io_i_d2[8],gpio2_io_i_d2[9],gpio2_io_i_d2[10],gpio2_io_i_d2[11]}));
FDRE \Dual.READ_REG2_GEN[0].GPIO2_DBus_i_reg[20]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Read_Reg2_In[0]),
.Q(GPIO2_DBus_i[11]),
.R(Read_Reg_Rst));
FDRE \Dual.READ_REG2_GEN[10].GPIO2_DBus_i_reg[30]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Read_Reg2_In[10]),
.Q(GPIO2_DBus_i[1]),
.R(Read_Reg_Rst));
FDRE \Dual.READ_REG2_GEN[11].GPIO2_DBus_i_reg[31]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Read_Reg2_In[11]),
.Q(GPIO2_DBus_i[0]),
.R(Read_Reg_Rst));
FDRE \Dual.READ_REG2_GEN[1].GPIO2_DBus_i_reg[21]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Read_Reg2_In[1]),
.Q(GPIO2_DBus_i[10]),
.R(Read_Reg_Rst));
FDRE \Dual.READ_REG2_GEN[2].GPIO2_DBus_i_reg[22]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Read_Reg2_In[2]),
.Q(GPIO2_DBus_i[9]),
.R(Read_Reg_Rst));
FDRE \Dual.READ_REG2_GEN[3].GPIO2_DBus_i_reg[23]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Read_Reg2_In[3]),
.Q(GPIO2_DBus_i[8]),
.R(Read_Reg_Rst));
FDRE \Dual.READ_REG2_GEN[4].GPIO2_DBus_i_reg[24]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Read_Reg2_In[4]),
.Q(GPIO2_DBus_i[7]),
.R(Read_Reg_Rst));
FDRE \Dual.READ_REG2_GEN[5].GPIO2_DBus_i_reg[25]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Read_Reg2_In[5]),
.Q(GPIO2_DBus_i[6]),
.R(Read_Reg_Rst));
FDRE \Dual.READ_REG2_GEN[6].GPIO2_DBus_i_reg[26]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Read_Reg2_In[6]),
.Q(GPIO2_DBus_i[5]),
.R(Read_Reg_Rst));
FDRE \Dual.READ_REG2_GEN[7].GPIO2_DBus_i_reg[27]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Read_Reg2_In[7]),
.Q(GPIO2_DBus_i[4]),
.R(Read_Reg_Rst));
FDRE \Dual.READ_REG2_GEN[8].GPIO2_DBus_i_reg[28]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Read_Reg2_In[8]),
.Q(GPIO2_DBus_i[3]),
.R(Read_Reg_Rst));
FDRE \Dual.READ_REG2_GEN[9].GPIO2_DBus_i_reg[29]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Read_Reg2_In[9]),
.Q(GPIO2_DBus_i[2]),
.R(Read_Reg_Rst));
FDRE \Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Read_Reg_In[0]),
.Q(GPIO_DBus_i[3]),
.R(Read_Reg_Rst));
FDRE \Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[29]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Read_Reg_In[1]),
.Q(GPIO_DBus_i[2]),
.R(Read_Reg_Rst));
FDRE \Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[30]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Read_Reg_In[2]),
.Q(GPIO_DBus_i[1]),
.R(Read_Reg_Rst));
FDRE \Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[31]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Read_Reg_In[3]),
.Q(GPIO_DBus_i[0]),
.R(Read_Reg_Rst));
FDRE \Dual.gpio2_Data_In_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio2_io_i_d2[0]),
.Q(Q[11]),
.R(1'b0));
FDRE \Dual.gpio2_Data_In_reg[10]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio2_io_i_d2[10]),
.Q(Q[1]),
.R(1'b0));
FDRE \Dual.gpio2_Data_In_reg[11]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio2_io_i_d2[11]),
.Q(Q[0]),
.R(1'b0));
FDRE \Dual.gpio2_Data_In_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio2_io_i_d2[1]),
.Q(Q[10]),
.R(1'b0));
FDRE \Dual.gpio2_Data_In_reg[2]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio2_io_i_d2[2]),
.Q(Q[9]),
.R(1'b0));
FDRE \Dual.gpio2_Data_In_reg[3]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio2_io_i_d2[3]),
.Q(Q[8]),
.R(1'b0));
FDRE \Dual.gpio2_Data_In_reg[4]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio2_io_i_d2[4]),
.Q(Q[7]),
.R(1'b0));
FDRE \Dual.gpio2_Data_In_reg[5]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio2_io_i_d2[5]),
.Q(Q[6]),
.R(1'b0));
FDRE \Dual.gpio2_Data_In_reg[6]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio2_io_i_d2[6]),
.Q(Q[5]),
.R(1'b0));
FDRE \Dual.gpio2_Data_In_reg[7]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio2_io_i_d2[7]),
.Q(Q[4]),
.R(1'b0));
FDRE \Dual.gpio2_Data_In_reg[8]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio2_io_i_d2[8]),
.Q(Q[3]),
.R(1'b0));
FDRE \Dual.gpio2_Data_In_reg[9]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio2_io_i_d2[9]),
.Q(Q[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Dual.gpio2_Data_Out_reg[0]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg_0),
.D(D[11]),
.Q(gpio2_io_o[11]),
.R(SS));
FDRE #(
.INIT(1'b0))
\Dual.gpio2_Data_Out_reg[10]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg_0),
.D(D[1]),
.Q(gpio2_io_o[1]),
.R(SS));
FDRE #(
.INIT(1'b0))
\Dual.gpio2_Data_Out_reg[11]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg_0),
.D(D[0]),
.Q(gpio2_io_o[0]),
.R(SS));
FDRE #(
.INIT(1'b0))
\Dual.gpio2_Data_Out_reg[1]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg_0),
.D(D[10]),
.Q(gpio2_io_o[10]),
.R(SS));
FDRE #(
.INIT(1'b0))
\Dual.gpio2_Data_Out_reg[2]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg_0),
.D(D[9]),
.Q(gpio2_io_o[9]),
.R(SS));
FDRE #(
.INIT(1'b0))
\Dual.gpio2_Data_Out_reg[3]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg_0),
.D(D[8]),
.Q(gpio2_io_o[8]),
.R(SS));
FDRE #(
.INIT(1'b0))
\Dual.gpio2_Data_Out_reg[4]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg_0),
.D(D[7]),
.Q(gpio2_io_o[7]),
.R(SS));
FDRE #(
.INIT(1'b0))
\Dual.gpio2_Data_Out_reg[5]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg_0),
.D(D[6]),
.Q(gpio2_io_o[6]),
.R(SS));
FDRE #(
.INIT(1'b0))
\Dual.gpio2_Data_Out_reg[6]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg_0),
.D(D[5]),
.Q(gpio2_io_o[5]),
.R(SS));
FDRE #(
.INIT(1'b0))
\Dual.gpio2_Data_Out_reg[7]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg_0),
.D(D[4]),
.Q(gpio2_io_o[4]),
.R(SS));
FDRE #(
.INIT(1'b0))
\Dual.gpio2_Data_Out_reg[8]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg_0),
.D(D[3]),
.Q(gpio2_io_o[3]),
.R(SS));
FDRE #(
.INIT(1'b0))
\Dual.gpio2_Data_Out_reg[9]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg_0),
.D(D[2]),
.Q(gpio2_io_o[2]),
.R(SS));
FDSE #(
.INIT(1'b1))
\Dual.gpio2_OE_reg[0]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg_1),
.D(D[11]),
.Q(gpio2_io_t[11]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Dual.gpio2_OE_reg[10]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg_1),
.D(D[1]),
.Q(gpio2_io_t[1]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Dual.gpio2_OE_reg[11]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg_1),
.D(D[0]),
.Q(gpio2_io_t[0]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Dual.gpio2_OE_reg[1]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg_1),
.D(D[10]),
.Q(gpio2_io_t[10]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Dual.gpio2_OE_reg[2]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg_1),
.D(D[9]),
.Q(gpio2_io_t[9]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Dual.gpio2_OE_reg[3]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg_1),
.D(D[8]),
.Q(gpio2_io_t[8]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Dual.gpio2_OE_reg[4]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg_1),
.D(D[7]),
.Q(gpio2_io_t[7]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Dual.gpio2_OE_reg[5]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg_1),
.D(D[6]),
.Q(gpio2_io_t[6]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Dual.gpio2_OE_reg[6]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg_1),
.D(D[5]),
.Q(gpio2_io_t[5]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Dual.gpio2_OE_reg[7]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg_1),
.D(D[4]),
.Q(gpio2_io_t[4]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Dual.gpio2_OE_reg[8]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg_1),
.D(D[3]),
.Q(gpio2_io_t[3]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Dual.gpio2_OE_reg[9]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg_1),
.D(D[2]),
.Q(gpio2_io_t[2]),
.S(SS));
FDRE \Dual.gpio_Data_In_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i_d2[0]),
.Q(\Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28]_0 [3]),
.R(1'b0));
FDRE \Dual.gpio_Data_In_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i_d2[1]),
.Q(\Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28]_0 [2]),
.R(1'b0));
FDRE \Dual.gpio_Data_In_reg[2]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i_d2[2]),
.Q(\Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28]_0 [1]),
.R(1'b0));
FDRE \Dual.gpio_Data_In_reg[3]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i_d2[3]),
.Q(\Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28]_0 [0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Dual.gpio_Data_Out_reg[0]
(.C(s_axi_aclk),
.CE(E),
.D(D[11]),
.Q(gpio_io_o[3]),
.R(SS));
FDRE #(
.INIT(1'b0))
\Dual.gpio_Data_Out_reg[1]
(.C(s_axi_aclk),
.CE(E),
.D(D[10]),
.Q(gpio_io_o[2]),
.R(SS));
FDRE #(
.INIT(1'b0))
\Dual.gpio_Data_Out_reg[2]
(.C(s_axi_aclk),
.CE(E),
.D(D[9]),
.Q(gpio_io_o[1]),
.R(SS));
FDRE #(
.INIT(1'b0))
\Dual.gpio_Data_Out_reg[3]
(.C(s_axi_aclk),
.CE(E),
.D(D[8]),
.Q(gpio_io_o[0]),
.R(SS));
FDSE #(
.INIT(1'b1))
\Dual.gpio_OE_reg[0]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg),
.D(D[11]),
.Q(gpio_io_t[3]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Dual.gpio_OE_reg[1]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg),
.D(D[10]),
.Q(gpio_io_t[2]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Dual.gpio_OE_reg[2]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg),
.D(D[9]),
.Q(gpio_io_t[1]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Dual.gpio_OE_reg[3]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg),
.D(D[8]),
.Q(gpio_io_t[0]),
.S(SS));
FDRE gpio_xferAck_Reg_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(GPIO_xferAck_i),
.Q(gpio_xferAck_Reg),
.R(SS));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT3 #(
.INIT(8'h04))
iGPIO_xferAck_i_1
(.I0(GPIO_xferAck_i),
.I1(bus2ip_cs),
.I2(gpio_xferAck_Reg),
.O(iGPIO_xferAck));
FDRE iGPIO_xferAck_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(iGPIO_xferAck),
.Q(GPIO_xferAck_i),
.R(SS));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT2 #(
.INIT(4'h8))
ip2bus_rdack_i_D1_i_1
(.I0(GPIO_xferAck_i),
.I1(bus2ip_rnw),
.O(ip2bus_rdack_i));
LUT2 #(
.INIT(4'h2))
ip2bus_wrack_i_D1_i_1
(.I0(GPIO_xferAck_i),
.I1(bus2ip_rnw),
.O(ip2bus_wrack_i_D1_reg));
endmodule
(* ORIG_REF_NAME = "address_decoder" *)
module system_axi_gpio_led_0_address_decoder
(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ,
s_axi_arready,
s_axi_wready,
D,
\ip2bus_data_i_D1_reg[20] ,
Read_Reg_In,
E,
\Dual.gpio_Data_Out_reg[0] ,
Read_Reg2_In,
\Dual.gpio2_OE_reg[0] ,
\Dual.gpio2_Data_Out_reg[0] ,
Read_Reg_Rst,
s_axi_aclk,
Q,
is_read,
ip2bus_rdack_i_D1,
is_write_reg,
ip2bus_wrack_i_D1,
\bus2ip_addr_i_reg[8] ,
s_axi_wdata,
GPIO2_DBus_i,
bus2ip_rnw_i_reg,
GPIO_DBus_i,
gpio_io_t,
\Dual.gpio_Data_In_reg[0] ,
rst_reg,
gpio2_io_t,
\Dual.gpio2_Data_In_reg[0] ,
gpio_xferAck_Reg,
GPIO_xferAck_i,
start2,
s_axi_aresetn);
output \MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ;
output s_axi_arready;
output s_axi_wready;
output [11:0]D;
output [11:0]\ip2bus_data_i_D1_reg[20] ;
output [0:3]Read_Reg_In;
output [0:0]E;
output [0:0]\Dual.gpio_Data_Out_reg[0] ;
output [0:11]Read_Reg2_In;
output [0:0]\Dual.gpio2_OE_reg[0] ;
output [0:0]\Dual.gpio2_Data_Out_reg[0] ;
output Read_Reg_Rst;
input s_axi_aclk;
input [3:0]Q;
input is_read;
input ip2bus_rdack_i_D1;
input is_write_reg;
input ip2bus_wrack_i_D1;
input [2:0]\bus2ip_addr_i_reg[8] ;
input [11:0]s_axi_wdata;
input [11:0]GPIO2_DBus_i;
input bus2ip_rnw_i_reg;
input [3:0]GPIO_DBus_i;
input [3:0]gpio_io_t;
input [3:0]\Dual.gpio_Data_In_reg[0] ;
input rst_reg;
input [11:0]gpio2_io_t;
input [11:0]\Dual.gpio2_Data_In_reg[0] ;
input gpio_xferAck_Reg;
input GPIO_xferAck_i;
input start2;
input s_axi_aresetn;
wire [11:0]D;
wire [11:0]\Dual.gpio2_Data_In_reg[0] ;
wire [0:0]\Dual.gpio2_Data_Out_reg[0] ;
wire [0:0]\Dual.gpio2_OE_reg[0] ;
wire [3:0]\Dual.gpio_Data_In_reg[0] ;
wire [0:0]\Dual.gpio_Data_Out_reg[0] ;
wire [0:0]E;
wire [11:0]GPIO2_DBus_i;
wire [3:0]GPIO_DBus_i;
wire GPIO_xferAck_i;
wire \MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0 ;
wire \MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ;
wire [3:0]Q;
wire [0:11]Read_Reg2_In;
wire [0:3]Read_Reg_In;
wire Read_Reg_Rst;
wire [2:0]\bus2ip_addr_i_reg[8] ;
wire bus2ip_rnw_i_reg;
wire [11:0]gpio2_io_t;
wire [3:0]gpio_io_t;
wire gpio_xferAck_Reg;
wire [11:0]\ip2bus_data_i_D1_reg[20] ;
wire ip2bus_rdack_i_D1;
wire ip2bus_wrack_i_D1;
wire is_read;
wire is_write_reg;
wire rst_reg;
wire s_axi_aclk;
wire s_axi_aresetn;
wire s_axi_arready;
wire [11:0]s_axi_wdata;
wire s_axi_wready;
wire start2;
LUT6 #(
.INIT(64'h0A0000000C000000))
\Dual.READ_REG2_GEN[0].GPIO2_DBus_i[20]_i_1
(.I0(gpio2_io_t[11]),
.I1(\Dual.gpio2_Data_In_reg[0] [11]),
.I2(\bus2ip_addr_i_reg[8] [2]),
.I3(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I4(\bus2ip_addr_i_reg[8] [1]),
.I5(\bus2ip_addr_i_reg[8] [0]),
.O(Read_Reg2_In[0]));
LUT6 #(
.INIT(64'h0A0000000C000000))
\Dual.READ_REG2_GEN[10].GPIO2_DBus_i[30]_i_1
(.I0(gpio2_io_t[1]),
.I1(\Dual.gpio2_Data_In_reg[0] [1]),
.I2(\bus2ip_addr_i_reg[8] [2]),
.I3(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I4(\bus2ip_addr_i_reg[8] [1]),
.I5(\bus2ip_addr_i_reg[8] [0]),
.O(Read_Reg2_In[10]));
LUT4 #(
.INIT(16'hFFDF))
\Dual.READ_REG2_GEN[11].GPIO2_DBus_i[31]_i_1
(.I0(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I1(gpio_xferAck_Reg),
.I2(bus2ip_rnw_i_reg),
.I3(GPIO_xferAck_i),
.O(Read_Reg_Rst));
LUT6 #(
.INIT(64'h0A0000000C000000))
\Dual.READ_REG2_GEN[11].GPIO2_DBus_i[31]_i_2
(.I0(gpio2_io_t[0]),
.I1(\Dual.gpio2_Data_In_reg[0] [0]),
.I2(\bus2ip_addr_i_reg[8] [2]),
.I3(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I4(\bus2ip_addr_i_reg[8] [1]),
.I5(\bus2ip_addr_i_reg[8] [0]),
.O(Read_Reg2_In[11]));
LUT6 #(
.INIT(64'h0A0000000C000000))
\Dual.READ_REG2_GEN[1].GPIO2_DBus_i[21]_i_1
(.I0(gpio2_io_t[10]),
.I1(\Dual.gpio2_Data_In_reg[0] [10]),
.I2(\bus2ip_addr_i_reg[8] [2]),
.I3(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I4(\bus2ip_addr_i_reg[8] [1]),
.I5(\bus2ip_addr_i_reg[8] [0]),
.O(Read_Reg2_In[1]));
LUT6 #(
.INIT(64'h0A0000000C000000))
\Dual.READ_REG2_GEN[2].GPIO2_DBus_i[22]_i_1
(.I0(gpio2_io_t[9]),
.I1(\Dual.gpio2_Data_In_reg[0] [9]),
.I2(\bus2ip_addr_i_reg[8] [2]),
.I3(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I4(\bus2ip_addr_i_reg[8] [1]),
.I5(\bus2ip_addr_i_reg[8] [0]),
.O(Read_Reg2_In[2]));
LUT6 #(
.INIT(64'h0A0000000C000000))
\Dual.READ_REG2_GEN[3].GPIO2_DBus_i[23]_i_1
(.I0(gpio2_io_t[8]),
.I1(\Dual.gpio2_Data_In_reg[0] [8]),
.I2(\bus2ip_addr_i_reg[8] [2]),
.I3(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I4(\bus2ip_addr_i_reg[8] [1]),
.I5(\bus2ip_addr_i_reg[8] [0]),
.O(Read_Reg2_In[3]));
LUT6 #(
.INIT(64'h0A0000000C000000))
\Dual.READ_REG2_GEN[4].GPIO2_DBus_i[24]_i_1
(.I0(gpio2_io_t[7]),
.I1(\Dual.gpio2_Data_In_reg[0] [7]),
.I2(\bus2ip_addr_i_reg[8] [2]),
.I3(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I4(\bus2ip_addr_i_reg[8] [1]),
.I5(\bus2ip_addr_i_reg[8] [0]),
.O(Read_Reg2_In[4]));
LUT6 #(
.INIT(64'h0A0000000C000000))
\Dual.READ_REG2_GEN[5].GPIO2_DBus_i[25]_i_1
(.I0(gpio2_io_t[6]),
.I1(\Dual.gpio2_Data_In_reg[0] [6]),
.I2(\bus2ip_addr_i_reg[8] [2]),
.I3(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I4(\bus2ip_addr_i_reg[8] [1]),
.I5(\bus2ip_addr_i_reg[8] [0]),
.O(Read_Reg2_In[5]));
LUT6 #(
.INIT(64'h0A0000000C000000))
\Dual.READ_REG2_GEN[6].GPIO2_DBus_i[26]_i_1
(.I0(gpio2_io_t[5]),
.I1(\Dual.gpio2_Data_In_reg[0] [5]),
.I2(\bus2ip_addr_i_reg[8] [2]),
.I3(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I4(\bus2ip_addr_i_reg[8] [1]),
.I5(\bus2ip_addr_i_reg[8] [0]),
.O(Read_Reg2_In[6]));
LUT6 #(
.INIT(64'h0A0000000C000000))
\Dual.READ_REG2_GEN[7].GPIO2_DBus_i[27]_i_1
(.I0(gpio2_io_t[4]),
.I1(\Dual.gpio2_Data_In_reg[0] [4]),
.I2(\bus2ip_addr_i_reg[8] [2]),
.I3(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I4(\bus2ip_addr_i_reg[8] [1]),
.I5(\bus2ip_addr_i_reg[8] [0]),
.O(Read_Reg2_In[7]));
LUT6 #(
.INIT(64'h0A0000000C000000))
\Dual.READ_REG2_GEN[8].GPIO2_DBus_i[28]_i_1
(.I0(gpio2_io_t[3]),
.I1(\Dual.gpio2_Data_In_reg[0] [3]),
.I2(\bus2ip_addr_i_reg[8] [2]),
.I3(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I4(\bus2ip_addr_i_reg[8] [1]),
.I5(\bus2ip_addr_i_reg[8] [0]),
.O(Read_Reg2_In[8]));
LUT6 #(
.INIT(64'h0A0000000C000000))
\Dual.READ_REG2_GEN[9].GPIO2_DBus_i[29]_i_1
(.I0(gpio2_io_t[2]),
.I1(\Dual.gpio2_Data_In_reg[0] [2]),
.I2(\bus2ip_addr_i_reg[8] [2]),
.I3(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I4(\bus2ip_addr_i_reg[8] [1]),
.I5(\bus2ip_addr_i_reg[8] [0]),
.O(Read_Reg2_In[9]));
LUT6 #(
.INIT(64'h000A0000000C0000))
\Dual.READ_REG_GEN[0].GPIO_DBus_i[28]_i_1
(.I0(gpio_io_t[3]),
.I1(\Dual.gpio_Data_In_reg[0] [3]),
.I2(\bus2ip_addr_i_reg[8] [2]),
.I3(\bus2ip_addr_i_reg[8] [1]),
.I4(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I5(\bus2ip_addr_i_reg[8] [0]),
.O(Read_Reg_In[0]));
LUT6 #(
.INIT(64'h000A0000000C0000))
\Dual.READ_REG_GEN[1].GPIO_DBus_i[29]_i_1
(.I0(gpio_io_t[2]),
.I1(\Dual.gpio_Data_In_reg[0] [2]),
.I2(\bus2ip_addr_i_reg[8] [2]),
.I3(\bus2ip_addr_i_reg[8] [1]),
.I4(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I5(\bus2ip_addr_i_reg[8] [0]),
.O(Read_Reg_In[1]));
LUT6 #(
.INIT(64'h000A0000000C0000))
\Dual.READ_REG_GEN[2].GPIO_DBus_i[30]_i_1
(.I0(gpio_io_t[1]),
.I1(\Dual.gpio_Data_In_reg[0] [1]),
.I2(\bus2ip_addr_i_reg[8] [2]),
.I3(\bus2ip_addr_i_reg[8] [1]),
.I4(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I5(\bus2ip_addr_i_reg[8] [0]),
.O(Read_Reg_In[2]));
LUT6 #(
.INIT(64'h000A0000000C0000))
\Dual.READ_REG_GEN[3].GPIO_DBus_i[31]_i_1
(.I0(gpio_io_t[0]),
.I1(\Dual.gpio_Data_In_reg[0] [0]),
.I2(\bus2ip_addr_i_reg[8] [2]),
.I3(\bus2ip_addr_i_reg[8] [1]),
.I4(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I5(\bus2ip_addr_i_reg[8] [0]),
.O(Read_Reg_In[3]));
LUT6 #(
.INIT(64'hFFFFFFFF00001000))
\Dual.gpio2_Data_Out[0]_i_1
(.I0(bus2ip_rnw_i_reg),
.I1(\bus2ip_addr_i_reg[8] [2]),
.I2(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I3(\bus2ip_addr_i_reg[8] [1]),
.I4(\bus2ip_addr_i_reg[8] [0]),
.I5(rst_reg),
.O(\Dual.gpio2_Data_Out_reg[0] ));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT3 #(
.INIT(8'hD0))
\Dual.gpio2_Data_Out[10]_i_1
(.I0(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I1(\bus2ip_addr_i_reg[8] [1]),
.I2(s_axi_wdata[1]),
.O(D[1]));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT3 #(
.INIT(8'hD0))
\Dual.gpio2_Data_Out[11]_i_1
(.I0(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I1(\bus2ip_addr_i_reg[8] [1]),
.I2(s_axi_wdata[0]),
.O(D[0]));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT3 #(
.INIT(8'hD0))
\Dual.gpio2_Data_Out[4]_i_1
(.I0(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I1(\bus2ip_addr_i_reg[8] [1]),
.I2(s_axi_wdata[7]),
.O(D[7]));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT3 #(
.INIT(8'hD0))
\Dual.gpio2_Data_Out[5]_i_1
(.I0(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I1(\bus2ip_addr_i_reg[8] [1]),
.I2(s_axi_wdata[6]),
.O(D[6]));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT3 #(
.INIT(8'hD0))
\Dual.gpio2_Data_Out[6]_i_1
(.I0(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I1(\bus2ip_addr_i_reg[8] [1]),
.I2(s_axi_wdata[5]),
.O(D[5]));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT3 #(
.INIT(8'hD0))
\Dual.gpio2_Data_Out[7]_i_1
(.I0(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I1(\bus2ip_addr_i_reg[8] [1]),
.I2(s_axi_wdata[4]),
.O(D[4]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT3 #(
.INIT(8'hD0))
\Dual.gpio2_Data_Out[8]_i_1
(.I0(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I1(\bus2ip_addr_i_reg[8] [1]),
.I2(s_axi_wdata[3]),
.O(D[3]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT3 #(
.INIT(8'hD0))
\Dual.gpio2_Data_Out[9]_i_1
(.I0(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I1(\bus2ip_addr_i_reg[8] [1]),
.I2(s_axi_wdata[2]),
.O(D[2]));
LUT6 #(
.INIT(64'hFFFFFFFF10000000))
\Dual.gpio2_OE[0]_i_1
(.I0(bus2ip_rnw_i_reg),
.I1(\bus2ip_addr_i_reg[8] [2]),
.I2(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I3(\bus2ip_addr_i_reg[8] [1]),
.I4(\bus2ip_addr_i_reg[8] [0]),
.I5(rst_reg),
.O(\Dual.gpio2_OE_reg[0] ));
LUT6 #(
.INIT(64'hFFFFFFFF00000100))
\Dual.gpio_Data_Out[0]_i_1
(.I0(bus2ip_rnw_i_reg),
.I1(\bus2ip_addr_i_reg[8] [2]),
.I2(\bus2ip_addr_i_reg[8] [1]),
.I3(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I4(\bus2ip_addr_i_reg[8] [0]),
.I5(rst_reg),
.O(\Dual.gpio_Data_Out_reg[0] ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT4 #(
.INIT(16'hBA8A))
\Dual.gpio_Data_Out[0]_i_2
(.I0(s_axi_wdata[11]),
.I1(\bus2ip_addr_i_reg[8] [1]),
.I2(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I3(s_axi_wdata[3]),
.O(D[11]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT4 #(
.INIT(16'hBA8A))
\Dual.gpio_Data_Out[1]_i_1
(.I0(s_axi_wdata[10]),
.I1(\bus2ip_addr_i_reg[8] [1]),
.I2(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I3(s_axi_wdata[2]),
.O(D[10]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'hBA8A))
\Dual.gpio_Data_Out[2]_i_1
(.I0(s_axi_wdata[9]),
.I1(\bus2ip_addr_i_reg[8] [1]),
.I2(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I3(s_axi_wdata[1]),
.O(D[9]));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT4 #(
.INIT(16'hBA8A))
\Dual.gpio_Data_Out[3]_i_1
(.I0(s_axi_wdata[8]),
.I1(\bus2ip_addr_i_reg[8] [1]),
.I2(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I3(s_axi_wdata[0]),
.O(D[8]));
LUT6 #(
.INIT(64'hFFFFFFFF00040000))
\Dual.gpio_OE[0]_i_1
(.I0(bus2ip_rnw_i_reg),
.I1(\bus2ip_addr_i_reg[8] [0]),
.I2(\bus2ip_addr_i_reg[8] [2]),
.I3(\bus2ip_addr_i_reg[8] [1]),
.I4(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I5(rst_reg),
.O(E));
LUT5 #(
.INIT(32'h000E0000))
\MEM_DECODE_GEN[0].cs_out_i[0]_i_1
(.I0(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I1(start2),
.I2(s_axi_wready),
.I3(s_axi_arready),
.I4(s_axi_aresetn),
.O(\MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0 ));
FDRE \MEM_DECODE_GEN[0].cs_out_i_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0 ),
.Q(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.R(1'b0));
LUT5 #(
.INIT(32'hFFF70000))
\ip2bus_data_i_D1[20]_i_1
(.I0(bus2ip_rnw_i_reg),
.I1(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I2(\bus2ip_addr_i_reg[8] [1]),
.I3(\bus2ip_addr_i_reg[8] [2]),
.I4(GPIO2_DBus_i[11]),
.O(\ip2bus_data_i_D1_reg[20] [11]));
LUT5 #(
.INIT(32'hFFF70000))
\ip2bus_data_i_D1[21]_i_1
(.I0(bus2ip_rnw_i_reg),
.I1(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I2(\bus2ip_addr_i_reg[8] [1]),
.I3(\bus2ip_addr_i_reg[8] [2]),
.I4(GPIO2_DBus_i[10]),
.O(\ip2bus_data_i_D1_reg[20] [10]));
LUT5 #(
.INIT(32'hFFF70000))
\ip2bus_data_i_D1[22]_i_1
(.I0(bus2ip_rnw_i_reg),
.I1(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I2(\bus2ip_addr_i_reg[8] [1]),
.I3(\bus2ip_addr_i_reg[8] [2]),
.I4(GPIO2_DBus_i[9]),
.O(\ip2bus_data_i_D1_reg[20] [9]));
LUT5 #(
.INIT(32'hFFF70000))
\ip2bus_data_i_D1[23]_i_1
(.I0(bus2ip_rnw_i_reg),
.I1(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I2(\bus2ip_addr_i_reg[8] [1]),
.I3(\bus2ip_addr_i_reg[8] [2]),
.I4(GPIO2_DBus_i[8]),
.O(\ip2bus_data_i_D1_reg[20] [8]));
LUT5 #(
.INIT(32'hFFF70000))
\ip2bus_data_i_D1[24]_i_1
(.I0(bus2ip_rnw_i_reg),
.I1(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I2(\bus2ip_addr_i_reg[8] [1]),
.I3(\bus2ip_addr_i_reg[8] [2]),
.I4(GPIO2_DBus_i[7]),
.O(\ip2bus_data_i_D1_reg[20] [7]));
LUT5 #(
.INIT(32'hFFF70000))
\ip2bus_data_i_D1[25]_i_1
(.I0(bus2ip_rnw_i_reg),
.I1(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I2(\bus2ip_addr_i_reg[8] [1]),
.I3(\bus2ip_addr_i_reg[8] [2]),
.I4(GPIO2_DBus_i[6]),
.O(\ip2bus_data_i_D1_reg[20] [6]));
LUT5 #(
.INIT(32'hFFF70000))
\ip2bus_data_i_D1[26]_i_1
(.I0(bus2ip_rnw_i_reg),
.I1(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I2(\bus2ip_addr_i_reg[8] [1]),
.I3(\bus2ip_addr_i_reg[8] [2]),
.I4(GPIO2_DBus_i[5]),
.O(\ip2bus_data_i_D1_reg[20] [5]));
LUT5 #(
.INIT(32'hFFF70000))
\ip2bus_data_i_D1[27]_i_1
(.I0(bus2ip_rnw_i_reg),
.I1(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I2(\bus2ip_addr_i_reg[8] [1]),
.I3(\bus2ip_addr_i_reg[8] [2]),
.I4(GPIO2_DBus_i[4]),
.O(\ip2bus_data_i_D1_reg[20] [4]));
LUT6 #(
.INIT(64'hABAAAAAAA8AAAAAA))
\ip2bus_data_i_D1[28]_i_1
(.I0(GPIO2_DBus_i[3]),
.I1(\bus2ip_addr_i_reg[8] [2]),
.I2(\bus2ip_addr_i_reg[8] [1]),
.I3(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I4(bus2ip_rnw_i_reg),
.I5(GPIO_DBus_i[3]),
.O(\ip2bus_data_i_D1_reg[20] [3]));
LUT6 #(
.INIT(64'hABAAAAAAA8AAAAAA))
\ip2bus_data_i_D1[29]_i_1
(.I0(GPIO2_DBus_i[2]),
.I1(\bus2ip_addr_i_reg[8] [2]),
.I2(\bus2ip_addr_i_reg[8] [1]),
.I3(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I4(bus2ip_rnw_i_reg),
.I5(GPIO_DBus_i[2]),
.O(\ip2bus_data_i_D1_reg[20] [2]));
LUT6 #(
.INIT(64'hABAAAAAAA8AAAAAA))
\ip2bus_data_i_D1[30]_i_1
(.I0(GPIO2_DBus_i[1]),
.I1(\bus2ip_addr_i_reg[8] [2]),
.I2(\bus2ip_addr_i_reg[8] [1]),
.I3(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I4(bus2ip_rnw_i_reg),
.I5(GPIO_DBus_i[1]),
.O(\ip2bus_data_i_D1_reg[20] [1]));
LUT6 #(
.INIT(64'hABAAAAAAA8AAAAAA))
\ip2bus_data_i_D1[31]_i_1
(.I0(GPIO2_DBus_i[0]),
.I1(\bus2ip_addr_i_reg[8] [2]),
.I2(\bus2ip_addr_i_reg[8] [1]),
.I3(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I4(bus2ip_rnw_i_reg),
.I5(GPIO_DBus_i[0]),
.O(\ip2bus_data_i_D1_reg[20] [0]));
LUT6 #(
.INIT(64'hFFFFFFFF00020000))
s_axi_arready_INST_0
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[1]),
.I3(Q[0]),
.I4(is_read),
.I5(ip2bus_rdack_i_D1),
.O(s_axi_arready));
LUT6 #(
.INIT(64'hFFFFFFFF00020000))
s_axi_wready_INST_0
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[1]),
.I3(Q[0]),
.I4(is_write_reg),
.I5(ip2bus_wrack_i_D1),
.O(s_axi_wready));
endmodule
(* C_ALL_INPUTS = "0" *) (* C_ALL_INPUTS_2 = "0" *) (* C_ALL_OUTPUTS = "0" *)
(* C_ALL_OUTPUTS_2 = "0" *) (* C_DOUT_DEFAULT = "0" *) (* C_DOUT_DEFAULT_2 = "0" *)
(* C_FAMILY = "artix7" *) (* C_GPIO2_WIDTH = "12" *) (* C_GPIO_WIDTH = "4" *)
(* C_INTERRUPT_PRESENT = "0" *) (* C_IS_DUAL = "1" *) (* C_S_AXI_ADDR_WIDTH = "9" *)
(* C_S_AXI_DATA_WIDTH = "32" *) (* C_TRI_DEFAULT = "-1" *) (* C_TRI_DEFAULT_2 = "-1" *)
(* ORIG_REF_NAME = "axi_gpio" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_group = "LOGICORE" *)
module system_axi_gpio_led_0_axi_gpio
(s_axi_aclk,
s_axi_aresetn,
s_axi_awaddr,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rvalid,
s_axi_rready,
ip2intc_irpt,
gpio_io_i,
gpio_io_o,
gpio_io_t,
gpio2_io_i,
gpio2_io_o,
gpio2_io_t);
(* max_fanout = "10000" *) (* sigis = "Clk" *) input s_axi_aclk;
(* max_fanout = "10000" *) (* sigis = "Rst" *) input s_axi_aresetn;
input [8:0]s_axi_awaddr;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wvalid;
output s_axi_wready;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [8:0]s_axi_araddr;
input s_axi_arvalid;
output s_axi_arready;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rvalid;
input s_axi_rready;
(* sigis = "INTR_LEVEL_HIGH" *) output ip2intc_irpt;
input [3:0]gpio_io_i;
output [3:0]gpio_io_o;
output [3:0]gpio_io_t;
input [11:0]gpio2_io_i;
output [11:0]gpio2_io_o;
output [11:0]gpio2_io_t;
wire \<const0> ;
wire AXI_LITE_IPIF_I_n_11;
wire AXI_LITE_IPIF_I_n_12;
wire AXI_LITE_IPIF_I_n_13;
wire AXI_LITE_IPIF_I_n_14;
wire AXI_LITE_IPIF_I_n_15;
wire AXI_LITE_IPIF_I_n_16;
wire AXI_LITE_IPIF_I_n_17;
wire AXI_LITE_IPIF_I_n_18;
wire AXI_LITE_IPIF_I_n_35;
wire AXI_LITE_IPIF_I_n_36;
wire AXI_LITE_IPIF_I_n_49;
wire AXI_LITE_IPIF_I_n_50;
wire [20:31]GPIO2_DBus_i;
wire [11:0]GPIO_DBus;
wire [28:31]GPIO_DBus_i;
wire GPIO_xferAck_i;
wire [0:11]Read_Reg2_In;
wire [0:3]Read_Reg_In;
wire Read_Reg_Rst;
wire bus2ip_cs;
wire bus2ip_reset;
wire bus2ip_rnw;
wire [0:11]gpio2_Data_In;
wire [11:0]gpio2_io_i;
wire [11:0]gpio2_io_o;
wire [11:0]gpio2_io_t;
wire [0:3]gpio_Data_In;
wire gpio_core_1_n_19;
wire [3:0]gpio_io_i;
wire [3:0]gpio_io_o;
wire [3:0]gpio_io_t;
wire gpio_xferAck_Reg;
wire [11:0]ip2bus_data_i_D1;
wire ip2bus_rdack_i;
wire ip2bus_rdack_i_D1;
wire ip2bus_wrack_i_D1;
wire [3:0]p_0_out;
(* MAX_FANOUT = "10000" *) (* RTL_MAX_FANOUT = "found" *) (* sigis = "Clk" *) wire s_axi_aclk;
wire [8:0]s_axi_araddr;
(* MAX_FANOUT = "10000" *) (* RTL_MAX_FANOUT = "found" *) (* sigis = "Rst" *) wire s_axi_aresetn;
wire s_axi_arready;
wire s_axi_arvalid;
wire [8:0]s_axi_awaddr;
wire s_axi_awvalid;
wire s_axi_bready;
wire s_axi_bvalid;
wire [11:0]\^s_axi_rdata ;
wire s_axi_rready;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire s_axi_wready;
wire s_axi_wvalid;
assign ip2intc_irpt = \<const0> ;
assign s_axi_awready = s_axi_wready;
assign s_axi_bresp[1] = \<const0> ;
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_rdata[31] = \<const0> ;
assign s_axi_rdata[30] = \<const0> ;
assign s_axi_rdata[29] = \<const0> ;
assign s_axi_rdata[28] = \<const0> ;
assign s_axi_rdata[27] = \<const0> ;
assign s_axi_rdata[26] = \<const0> ;
assign s_axi_rdata[25] = \<const0> ;
assign s_axi_rdata[24] = \<const0> ;
assign s_axi_rdata[23] = \<const0> ;
assign s_axi_rdata[22] = \<const0> ;
assign s_axi_rdata[21] = \<const0> ;
assign s_axi_rdata[20] = \<const0> ;
assign s_axi_rdata[19] = \<const0> ;
assign s_axi_rdata[18] = \<const0> ;
assign s_axi_rdata[17] = \<const0> ;
assign s_axi_rdata[16] = \<const0> ;
assign s_axi_rdata[15] = \<const0> ;
assign s_axi_rdata[14] = \<const0> ;
assign s_axi_rdata[13] = \<const0> ;
assign s_axi_rdata[12] = \<const0> ;
assign s_axi_rdata[11:0] = \^s_axi_rdata [11:0];
assign s_axi_rresp[1] = \<const0> ;
assign s_axi_rresp[0] = \<const0> ;
system_axi_gpio_led_0_axi_lite_ipif AXI_LITE_IPIF_I
(.D({p_0_out,AXI_LITE_IPIF_I_n_11,AXI_LITE_IPIF_I_n_12,AXI_LITE_IPIF_I_n_13,AXI_LITE_IPIF_I_n_14,AXI_LITE_IPIF_I_n_15,AXI_LITE_IPIF_I_n_16,AXI_LITE_IPIF_I_n_17,AXI_LITE_IPIF_I_n_18}),
.\Dual.gpio2_Data_In_reg[0] ({gpio2_Data_In[0],gpio2_Data_In[1],gpio2_Data_In[2],gpio2_Data_In[3],gpio2_Data_In[4],gpio2_Data_In[5],gpio2_Data_In[6],gpio2_Data_In[7],gpio2_Data_In[8],gpio2_Data_In[9],gpio2_Data_In[10],gpio2_Data_In[11]}),
.\Dual.gpio2_Data_Out_reg[0] (AXI_LITE_IPIF_I_n_50),
.\Dual.gpio2_OE_reg[0] (AXI_LITE_IPIF_I_n_49),
.\Dual.gpio_Data_Out_reg[0] (AXI_LITE_IPIF_I_n_36),
.E(AXI_LITE_IPIF_I_n_35),
.GPIO2_DBus_i({GPIO2_DBus_i[20],GPIO2_DBus_i[21],GPIO2_DBus_i[22],GPIO2_DBus_i[23],GPIO2_DBus_i[24],GPIO2_DBus_i[25],GPIO2_DBus_i[26],GPIO2_DBus_i[27],GPIO2_DBus_i[28],GPIO2_DBus_i[29],GPIO2_DBus_i[30],GPIO2_DBus_i[31]}),
.GPIO_DBus_i({GPIO_DBus_i[28],GPIO_DBus_i[29],GPIO_DBus_i[30],GPIO_DBus_i[31]}),
.GPIO_xferAck_i(GPIO_xferAck_i),
.Q({gpio_Data_In[0],gpio_Data_In[1],gpio_Data_In[2],gpio_Data_In[3]}),
.Read_Reg2_In(Read_Reg2_In),
.Read_Reg_In(Read_Reg_In),
.Read_Reg_Rst(Read_Reg_Rst),
.bus2ip_cs(bus2ip_cs),
.bus2ip_reset(bus2ip_reset),
.bus2ip_rnw(bus2ip_rnw),
.gpio2_io_t(gpio2_io_t),
.gpio_io_t(gpio_io_t),
.gpio_xferAck_Reg(gpio_xferAck_Reg),
.\ip2bus_data_i_D1_reg[20] (GPIO_DBus),
.\ip2bus_data_i_D1_reg[20]_0 (ip2bus_data_i_D1),
.ip2bus_rdack_i_D1(ip2bus_rdack_i_D1),
.ip2bus_wrack_i_D1(ip2bus_wrack_i_D1),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr({s_axi_araddr[8],s_axi_araddr[3:2]}),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr({s_axi_awaddr[8],s_axi_awaddr[3:2]}),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(\^s_axi_rdata ),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata[11:0]),
.s_axi_wready(s_axi_wready),
.s_axi_wvalid(s_axi_wvalid));
GND GND
(.G(\<const0> ));
system_axi_gpio_led_0_GPIO_Core gpio_core_1
(.D({p_0_out,AXI_LITE_IPIF_I_n_11,AXI_LITE_IPIF_I_n_12,AXI_LITE_IPIF_I_n_13,AXI_LITE_IPIF_I_n_14,AXI_LITE_IPIF_I_n_15,AXI_LITE_IPIF_I_n_16,AXI_LITE_IPIF_I_n_17,AXI_LITE_IPIF_I_n_18}),
.\Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28]_0 ({gpio_Data_In[0],gpio_Data_In[1],gpio_Data_In[2],gpio_Data_In[3]}),
.E(AXI_LITE_IPIF_I_n_36),
.GPIO2_DBus_i({GPIO2_DBus_i[20],GPIO2_DBus_i[21],GPIO2_DBus_i[22],GPIO2_DBus_i[23],GPIO2_DBus_i[24],GPIO2_DBus_i[25],GPIO2_DBus_i[26],GPIO2_DBus_i[27],GPIO2_DBus_i[28],GPIO2_DBus_i[29],GPIO2_DBus_i[30],GPIO2_DBus_i[31]}),
.GPIO_DBus_i({GPIO_DBus_i[28],GPIO_DBus_i[29],GPIO_DBus_i[30],GPIO_DBus_i[31]}),
.GPIO_xferAck_i(GPIO_xferAck_i),
.Q({gpio2_Data_In[0],gpio2_Data_In[1],gpio2_Data_In[2],gpio2_Data_In[3],gpio2_Data_In[4],gpio2_Data_In[5],gpio2_Data_In[6],gpio2_Data_In[7],gpio2_Data_In[8],gpio2_Data_In[9],gpio2_Data_In[10],gpio2_Data_In[11]}),
.Read_Reg2_In(Read_Reg2_In),
.Read_Reg_In(Read_Reg_In),
.Read_Reg_Rst(Read_Reg_Rst),
.SS(bus2ip_reset),
.bus2ip_cs(bus2ip_cs),
.bus2ip_rnw(bus2ip_rnw),
.bus2ip_rnw_i_reg(AXI_LITE_IPIF_I_n_35),
.bus2ip_rnw_i_reg_0(AXI_LITE_IPIF_I_n_50),
.bus2ip_rnw_i_reg_1(AXI_LITE_IPIF_I_n_49),
.gpio2_io_i(gpio2_io_i),
.gpio2_io_o(gpio2_io_o),
.gpio2_io_t(gpio2_io_t),
.gpio_io_i(gpio_io_i),
.gpio_io_o(gpio_io_o),
.gpio_io_t(gpio_io_t),
.gpio_xferAck_Reg(gpio_xferAck_Reg),
.ip2bus_rdack_i(ip2bus_rdack_i),
.ip2bus_wrack_i_D1_reg(gpio_core_1_n_19),
.s_axi_aclk(s_axi_aclk));
FDRE \ip2bus_data_i_D1_reg[20]
(.C(s_axi_aclk),
.CE(1'b1),
.D(GPIO_DBus[11]),
.Q(ip2bus_data_i_D1[11]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[21]
(.C(s_axi_aclk),
.CE(1'b1),
.D(GPIO_DBus[10]),
.Q(ip2bus_data_i_D1[10]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[22]
(.C(s_axi_aclk),
.CE(1'b1),
.D(GPIO_DBus[9]),
.Q(ip2bus_data_i_D1[9]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[23]
(.C(s_axi_aclk),
.CE(1'b1),
.D(GPIO_DBus[8]),
.Q(ip2bus_data_i_D1[8]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[24]
(.C(s_axi_aclk),
.CE(1'b1),
.D(GPIO_DBus[7]),
.Q(ip2bus_data_i_D1[7]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[25]
(.C(s_axi_aclk),
.CE(1'b1),
.D(GPIO_DBus[6]),
.Q(ip2bus_data_i_D1[6]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[26]
(.C(s_axi_aclk),
.CE(1'b1),
.D(GPIO_DBus[5]),
.Q(ip2bus_data_i_D1[5]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[27]
(.C(s_axi_aclk),
.CE(1'b1),
.D(GPIO_DBus[4]),
.Q(ip2bus_data_i_D1[4]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[28]
(.C(s_axi_aclk),
.CE(1'b1),
.D(GPIO_DBus[3]),
.Q(ip2bus_data_i_D1[3]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[29]
(.C(s_axi_aclk),
.CE(1'b1),
.D(GPIO_DBus[2]),
.Q(ip2bus_data_i_D1[2]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[30]
(.C(s_axi_aclk),
.CE(1'b1),
.D(GPIO_DBus[1]),
.Q(ip2bus_data_i_D1[1]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[31]
(.C(s_axi_aclk),
.CE(1'b1),
.D(GPIO_DBus[0]),
.Q(ip2bus_data_i_D1[0]),
.R(bus2ip_reset));
FDRE ip2bus_rdack_i_D1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_rdack_i),
.Q(ip2bus_rdack_i_D1),
.R(bus2ip_reset));
FDRE ip2bus_wrack_i_D1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_core_1_n_19),
.Q(ip2bus_wrack_i_D1),
.R(bus2ip_reset));
endmodule
(* ORIG_REF_NAME = "axi_lite_ipif" *)
module system_axi_gpio_led_0_axi_lite_ipif
(bus2ip_reset,
bus2ip_rnw,
bus2ip_cs,
s_axi_rvalid,
s_axi_bvalid,
s_axi_arready,
s_axi_wready,
D,
\ip2bus_data_i_D1_reg[20] ,
Read_Reg_In,
E,
\Dual.gpio_Data_Out_reg[0] ,
Read_Reg2_In,
\Dual.gpio2_OE_reg[0] ,
\Dual.gpio2_Data_Out_reg[0] ,
Read_Reg_Rst,
s_axi_rdata,
s_axi_aclk,
s_axi_arvalid,
ip2bus_rdack_i_D1,
ip2bus_wrack_i_D1,
s_axi_bready,
s_axi_rready,
s_axi_awaddr,
s_axi_araddr,
s_axi_awvalid,
s_axi_wvalid,
s_axi_wdata,
GPIO2_DBus_i,
GPIO_DBus_i,
gpio_io_t,
Q,
gpio2_io_t,
\Dual.gpio2_Data_In_reg[0] ,
s_axi_aresetn,
gpio_xferAck_Reg,
GPIO_xferAck_i,
\ip2bus_data_i_D1_reg[20]_0 );
output bus2ip_reset;
output bus2ip_rnw;
output bus2ip_cs;
output s_axi_rvalid;
output s_axi_bvalid;
output s_axi_arready;
output s_axi_wready;
output [11:0]D;
output [11:0]\ip2bus_data_i_D1_reg[20] ;
output [0:3]Read_Reg_In;
output [0:0]E;
output [0:0]\Dual.gpio_Data_Out_reg[0] ;
output [0:11]Read_Reg2_In;
output [0:0]\Dual.gpio2_OE_reg[0] ;
output [0:0]\Dual.gpio2_Data_Out_reg[0] ;
output Read_Reg_Rst;
output [11:0]s_axi_rdata;
input s_axi_aclk;
input s_axi_arvalid;
input ip2bus_rdack_i_D1;
input ip2bus_wrack_i_D1;
input s_axi_bready;
input s_axi_rready;
input [2:0]s_axi_awaddr;
input [2:0]s_axi_araddr;
input s_axi_awvalid;
input s_axi_wvalid;
input [11:0]s_axi_wdata;
input [11:0]GPIO2_DBus_i;
input [3:0]GPIO_DBus_i;
input [3:0]gpio_io_t;
input [3:0]Q;
input [11:0]gpio2_io_t;
input [11:0]\Dual.gpio2_Data_In_reg[0] ;
input s_axi_aresetn;
input gpio_xferAck_Reg;
input GPIO_xferAck_i;
input [11:0]\ip2bus_data_i_D1_reg[20]_0 ;
wire [11:0]D;
wire [11:0]\Dual.gpio2_Data_In_reg[0] ;
wire [0:0]\Dual.gpio2_Data_Out_reg[0] ;
wire [0:0]\Dual.gpio2_OE_reg[0] ;
wire [0:0]\Dual.gpio_Data_Out_reg[0] ;
wire [0:0]E;
wire [11:0]GPIO2_DBus_i;
wire [3:0]GPIO_DBus_i;
wire GPIO_xferAck_i;
wire [3:0]Q;
wire [0:11]Read_Reg2_In;
wire [0:3]Read_Reg_In;
wire Read_Reg_Rst;
wire bus2ip_cs;
wire bus2ip_reset;
wire bus2ip_rnw;
wire [11:0]gpio2_io_t;
wire [3:0]gpio_io_t;
wire gpio_xferAck_Reg;
wire [11:0]\ip2bus_data_i_D1_reg[20] ;
wire [11:0]\ip2bus_data_i_D1_reg[20]_0 ;
wire ip2bus_rdack_i_D1;
wire ip2bus_wrack_i_D1;
wire s_axi_aclk;
wire [2:0]s_axi_araddr;
wire s_axi_aresetn;
wire s_axi_arready;
wire s_axi_arvalid;
wire [2:0]s_axi_awaddr;
wire s_axi_awvalid;
wire s_axi_bready;
wire s_axi_bvalid;
wire [11:0]s_axi_rdata;
wire s_axi_rready;
wire s_axi_rvalid;
wire [11:0]s_axi_wdata;
wire s_axi_wready;
wire s_axi_wvalid;
system_axi_gpio_led_0_slave_attachment I_SLAVE_ATTACHMENT
(.D(D),
.\Dual.gpio2_Data_In_reg[0] (\Dual.gpio2_Data_In_reg[0] ),
.\Dual.gpio2_Data_Out_reg[0] (\Dual.gpio2_Data_Out_reg[0] ),
.\Dual.gpio2_OE_reg[0] (\Dual.gpio2_OE_reg[0] ),
.\Dual.gpio_Data_Out_reg[0] (\Dual.gpio_Data_Out_reg[0] ),
.E(E),
.GPIO2_DBus_i(GPIO2_DBus_i),
.GPIO_DBus_i(GPIO_DBus_i),
.GPIO_xferAck_i(GPIO_xferAck_i),
.\MEM_DECODE_GEN[0].cs_out_i_reg[0] (bus2ip_cs),
.Q(Q),
.Read_Reg2_In(Read_Reg2_In),
.Read_Reg_In(Read_Reg_In),
.Read_Reg_Rst(Read_Reg_Rst),
.bus2ip_rnw_i_reg_0(bus2ip_reset),
.gpio2_io_t(gpio2_io_t),
.gpio_io_t(gpio_io_t),
.gpio_xferAck_Reg(gpio_xferAck_Reg),
.\ip2bus_data_i_D1_reg[20] (\ip2bus_data_i_D1_reg[20] ),
.\ip2bus_data_i_D1_reg[20]_0 (\ip2bus_data_i_D1_reg[20]_0 ),
.\ip2bus_data_i_D1_reg[31] (bus2ip_rnw),
.ip2bus_rdack_i_D1(ip2bus_rdack_i_D1),
.ip2bus_wrack_i_D1(ip2bus_wrack_i_D1),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr(s_axi_araddr),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wready(s_axi_wready),
.s_axi_wvalid(s_axi_wvalid));
endmodule
(* ORIG_REF_NAME = "cdc_sync" *)
module system_axi_gpio_led_0_cdc_sync
(scndry_vect_out,
gpio_io_i,
s_axi_aclk);
output [3:0]scndry_vect_out;
input [3:0]gpio_io_i;
input s_axi_aclk;
wire [3:0]gpio_io_i;
wire s_axi_aclk;
wire s_level_out_bus_d1_cdc_to_0;
wire s_level_out_bus_d1_cdc_to_1;
wire s_level_out_bus_d1_cdc_to_2;
wire s_level_out_bus_d1_cdc_to_3;
wire s_level_out_bus_d2_0;
wire s_level_out_bus_d2_1;
wire s_level_out_bus_d2_2;
wire s_level_out_bus_d2_3;
wire s_level_out_bus_d3_0;
wire s_level_out_bus_d3_1;
wire s_level_out_bus_d3_2;
wire s_level_out_bus_d3_3;
wire [3:0]scndry_vect_out;
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_0),
.Q(s_level_out_bus_d2_0),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_1),
.Q(s_level_out_bus_d2_1),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_2),
.Q(s_level_out_bus_d2_2),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_3),
.Q(s_level_out_bus_d2_3),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_0),
.Q(s_level_out_bus_d3_0),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_1),
.Q(s_level_out_bus_d3_1),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_2),
.Q(s_level_out_bus_d3_2),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_3),
.Q(s_level_out_bus_d3_3),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_0),
.Q(scndry_vect_out[0]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_1),
.Q(scndry_vect_out[1]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_2),
.Q(scndry_vect_out[2]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_3),
.Q(scndry_vect_out[3]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i[0]),
.Q(s_level_out_bus_d1_cdc_to_0),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i[1]),
.Q(s_level_out_bus_d1_cdc_to_1),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i[2]),
.Q(s_level_out_bus_d1_cdc_to_2),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i[3]),
.Q(s_level_out_bus_d1_cdc_to_3),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "cdc_sync" *)
module system_axi_gpio_led_0_cdc_sync__parameterized0
(scndry_vect_out,
gpio2_io_i,
s_axi_aclk);
output [11:0]scndry_vect_out;
input [11:0]gpio2_io_i;
input s_axi_aclk;
wire [11:0]gpio2_io_i;
wire s_axi_aclk;
wire s_level_out_bus_d1_cdc_to_0;
wire s_level_out_bus_d1_cdc_to_1;
wire s_level_out_bus_d1_cdc_to_10;
wire s_level_out_bus_d1_cdc_to_11;
wire s_level_out_bus_d1_cdc_to_2;
wire s_level_out_bus_d1_cdc_to_3;
wire s_level_out_bus_d1_cdc_to_4;
wire s_level_out_bus_d1_cdc_to_5;
wire s_level_out_bus_d1_cdc_to_6;
wire s_level_out_bus_d1_cdc_to_7;
wire s_level_out_bus_d1_cdc_to_8;
wire s_level_out_bus_d1_cdc_to_9;
wire s_level_out_bus_d2_0;
wire s_level_out_bus_d2_1;
wire s_level_out_bus_d2_10;
wire s_level_out_bus_d2_11;
wire s_level_out_bus_d2_2;
wire s_level_out_bus_d2_3;
wire s_level_out_bus_d2_4;
wire s_level_out_bus_d2_5;
wire s_level_out_bus_d2_6;
wire s_level_out_bus_d2_7;
wire s_level_out_bus_d2_8;
wire s_level_out_bus_d2_9;
wire s_level_out_bus_d3_0;
wire s_level_out_bus_d3_1;
wire s_level_out_bus_d3_10;
wire s_level_out_bus_d3_11;
wire s_level_out_bus_d3_2;
wire s_level_out_bus_d3_3;
wire s_level_out_bus_d3_4;
wire s_level_out_bus_d3_5;
wire s_level_out_bus_d3_6;
wire s_level_out_bus_d3_7;
wire s_level_out_bus_d3_8;
wire s_level_out_bus_d3_9;
wire [11:0]scndry_vect_out;
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_0),
.Q(s_level_out_bus_d2_0),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_10),
.Q(s_level_out_bus_d2_10),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_11),
.Q(s_level_out_bus_d2_11),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_1),
.Q(s_level_out_bus_d2_1),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_2),
.Q(s_level_out_bus_d2_2),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_3),
.Q(s_level_out_bus_d2_3),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_4),
.Q(s_level_out_bus_d2_4),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_5),
.Q(s_level_out_bus_d2_5),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_6),
.Q(s_level_out_bus_d2_6),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_7),
.Q(s_level_out_bus_d2_7),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_8),
.Q(s_level_out_bus_d2_8),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_9),
.Q(s_level_out_bus_d2_9),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_0),
.Q(s_level_out_bus_d3_0),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_10),
.Q(s_level_out_bus_d3_10),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_11),
.Q(s_level_out_bus_d3_11),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_1),
.Q(s_level_out_bus_d3_1),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_2),
.Q(s_level_out_bus_d3_2),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_3),
.Q(s_level_out_bus_d3_3),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_4),
.Q(s_level_out_bus_d3_4),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_5),
.Q(s_level_out_bus_d3_5),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_6),
.Q(s_level_out_bus_d3_6),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_7),
.Q(s_level_out_bus_d3_7),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_8),
.Q(s_level_out_bus_d3_8),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_9),
.Q(s_level_out_bus_d3_9),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_0),
.Q(scndry_vect_out[0]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_10),
.Q(scndry_vect_out[10]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_11),
.Q(scndry_vect_out[11]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_1),
.Q(scndry_vect_out[1]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_2),
.Q(scndry_vect_out[2]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_3),
.Q(scndry_vect_out[3]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_4),
.Q(scndry_vect_out[4]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_5),
.Q(scndry_vect_out[5]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_6),
.Q(scndry_vect_out[6]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_7),
.Q(scndry_vect_out[7]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_8),
.Q(scndry_vect_out[8]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_9),
.Q(scndry_vect_out[9]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio2_io_i[0]),
.Q(s_level_out_bus_d1_cdc_to_0),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[10].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio2_io_i[10]),
.Q(s_level_out_bus_d1_cdc_to_10),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[11].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio2_io_i[11]),
.Q(s_level_out_bus_d1_cdc_to_11),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio2_io_i[1]),
.Q(s_level_out_bus_d1_cdc_to_1),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio2_io_i[2]),
.Q(s_level_out_bus_d1_cdc_to_2),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio2_io_i[3]),
.Q(s_level_out_bus_d1_cdc_to_3),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio2_io_i[4]),
.Q(s_level_out_bus_d1_cdc_to_4),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[5].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio2_io_i[5]),
.Q(s_level_out_bus_d1_cdc_to_5),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[6].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio2_io_i[6]),
.Q(s_level_out_bus_d1_cdc_to_6),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[7].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio2_io_i[7]),
.Q(s_level_out_bus_d1_cdc_to_7),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[8].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio2_io_i[8]),
.Q(s_level_out_bus_d1_cdc_to_8),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[9].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio2_io_i[9]),
.Q(s_level_out_bus_d1_cdc_to_9),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "slave_attachment" *)
module system_axi_gpio_led_0_slave_attachment
(bus2ip_rnw_i_reg_0,
\ip2bus_data_i_D1_reg[31] ,
\MEM_DECODE_GEN[0].cs_out_i_reg[0] ,
s_axi_rvalid,
s_axi_bvalid,
s_axi_arready,
s_axi_wready,
D,
\ip2bus_data_i_D1_reg[20] ,
Read_Reg_In,
E,
\Dual.gpio_Data_Out_reg[0] ,
Read_Reg2_In,
\Dual.gpio2_OE_reg[0] ,
\Dual.gpio2_Data_Out_reg[0] ,
Read_Reg_Rst,
s_axi_rdata,
s_axi_aclk,
s_axi_arvalid,
ip2bus_rdack_i_D1,
ip2bus_wrack_i_D1,
s_axi_bready,
s_axi_rready,
s_axi_awaddr,
s_axi_araddr,
s_axi_awvalid,
s_axi_wvalid,
s_axi_wdata,
GPIO2_DBus_i,
GPIO_DBus_i,
gpio_io_t,
Q,
gpio2_io_t,
\Dual.gpio2_Data_In_reg[0] ,
s_axi_aresetn,
gpio_xferAck_Reg,
GPIO_xferAck_i,
\ip2bus_data_i_D1_reg[20]_0 );
output bus2ip_rnw_i_reg_0;
output \ip2bus_data_i_D1_reg[31] ;
output \MEM_DECODE_GEN[0].cs_out_i_reg[0] ;
output s_axi_rvalid;
output s_axi_bvalid;
output s_axi_arready;
output s_axi_wready;
output [11:0]D;
output [11:0]\ip2bus_data_i_D1_reg[20] ;
output [0:3]Read_Reg_In;
output [0:0]E;
output [0:0]\Dual.gpio_Data_Out_reg[0] ;
output [0:11]Read_Reg2_In;
output [0:0]\Dual.gpio2_OE_reg[0] ;
output [0:0]\Dual.gpio2_Data_Out_reg[0] ;
output Read_Reg_Rst;
output [11:0]s_axi_rdata;
input s_axi_aclk;
input s_axi_arvalid;
input ip2bus_rdack_i_D1;
input ip2bus_wrack_i_D1;
input s_axi_bready;
input s_axi_rready;
input [2:0]s_axi_awaddr;
input [2:0]s_axi_araddr;
input s_axi_awvalid;
input s_axi_wvalid;
input [11:0]s_axi_wdata;
input [11:0]GPIO2_DBus_i;
input [3:0]GPIO_DBus_i;
input [3:0]gpio_io_t;
input [3:0]Q;
input [11:0]gpio2_io_t;
input [11:0]\Dual.gpio2_Data_In_reg[0] ;
input s_axi_aresetn;
input gpio_xferAck_Reg;
input GPIO_xferAck_i;
input [11:0]\ip2bus_data_i_D1_reg[20]_0 ;
wire [11:0]D;
wire [11:0]\Dual.gpio2_Data_In_reg[0] ;
wire [0:0]\Dual.gpio2_Data_Out_reg[0] ;
wire [0:0]\Dual.gpio2_OE_reg[0] ;
wire [0:0]\Dual.gpio_Data_Out_reg[0] ;
wire [0:0]E;
wire [11:0]GPIO2_DBus_i;
wire [3:0]GPIO_DBus_i;
wire GPIO_xferAck_i;
wire [3:0]\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 ;
wire \MEM_DECODE_GEN[0].cs_out_i_reg[0] ;
wire [3:0]Q;
wire [0:11]Read_Reg2_In;
wire [0:3]Read_Reg_In;
wire Read_Reg_Rst;
wire [0:6]bus2ip_addr;
wire \bus2ip_addr_i[2]_i_1_n_0 ;
wire \bus2ip_addr_i[3]_i_1_n_0 ;
wire \bus2ip_addr_i[8]_i_1_n_0 ;
wire bus2ip_rnw_i06_out;
wire bus2ip_rnw_i_reg_0;
wire clear;
wire [11:0]gpio2_io_t;
wire [3:0]gpio_io_t;
wire gpio_xferAck_Reg;
wire [11:0]\ip2bus_data_i_D1_reg[20] ;
wire [11:0]\ip2bus_data_i_D1_reg[20]_0 ;
wire \ip2bus_data_i_D1_reg[31] ;
wire ip2bus_rdack_i_D1;
wire ip2bus_wrack_i_D1;
wire is_read;
wire is_read_i_1_n_0;
wire is_write;
wire is_write_i_1_n_0;
wire is_write_reg_n_0;
wire p_1_in;
wire [3:0]plusOp;
wire s_axi_aclk;
wire [2:0]s_axi_araddr;
wire s_axi_aresetn;
wire s_axi_arready;
wire s_axi_arvalid;
wire [2:0]s_axi_awaddr;
wire s_axi_awvalid;
wire s_axi_bready;
wire s_axi_bvalid;
wire s_axi_bvalid_i_i_1_n_0;
wire [11:0]s_axi_rdata;
wire s_axi_rdata_i;
wire s_axi_rready;
wire s_axi_rvalid;
wire s_axi_rvalid_i_i_1_n_0;
wire [11:0]s_axi_wdata;
wire s_axi_wready;
wire s_axi_wvalid;
wire start2;
wire start2_i_1_n_0;
wire [1:0]state;
wire \state[0]_i_1_n_0 ;
wire \state[1]_i_1_n_0 ;
wire \state[1]_i_2_n_0 ;
wire \state[1]_i_3_n_0 ;
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT1 #(
.INIT(2'h1))
\INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.O(plusOp[0]));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT2 #(
.INIT(4'h6))
\INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
.O(plusOp[1]));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT3 #(
.INIT(8'h78))
\INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
.I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]),
.O(plusOp[2]));
LUT2 #(
.INIT(4'h9))
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1
(.I0(state[1]),
.I1(state[0]),
.O(clear));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT4 #(
.INIT(16'h7F80))
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]),
.I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
.I3(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [3]),
.O(plusOp[3]));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(plusOp[0]),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.R(clear));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(plusOp[1]),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
.R(clear));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[2]
(.C(s_axi_aclk),
.CE(1'b1),
.D(plusOp[2]),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]),
.R(clear));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]
(.C(s_axi_aclk),
.CE(1'b1),
.D(plusOp[3]),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [3]),
.R(clear));
system_axi_gpio_led_0_address_decoder I_DECODER
(.D(D),
.\Dual.gpio2_Data_In_reg[0] (\Dual.gpio2_Data_In_reg[0] ),
.\Dual.gpio2_Data_Out_reg[0] (\Dual.gpio2_Data_Out_reg[0] ),
.\Dual.gpio2_OE_reg[0] (\Dual.gpio2_OE_reg[0] ),
.\Dual.gpio_Data_In_reg[0] (Q),
.\Dual.gpio_Data_Out_reg[0] (\Dual.gpio_Data_Out_reg[0] ),
.E(E),
.GPIO2_DBus_i(GPIO2_DBus_i),
.GPIO_DBus_i(GPIO_DBus_i),
.GPIO_xferAck_i(GPIO_xferAck_i),
.\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 (\MEM_DECODE_GEN[0].cs_out_i_reg[0] ),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 ),
.Read_Reg2_In(Read_Reg2_In),
.Read_Reg_In(Read_Reg_In),
.Read_Reg_Rst(Read_Reg_Rst),
.\bus2ip_addr_i_reg[8] ({bus2ip_addr[0],bus2ip_addr[5],bus2ip_addr[6]}),
.bus2ip_rnw_i_reg(\ip2bus_data_i_D1_reg[31] ),
.gpio2_io_t(gpio2_io_t),
.gpio_io_t(gpio_io_t),
.gpio_xferAck_Reg(gpio_xferAck_Reg),
.\ip2bus_data_i_D1_reg[20] (\ip2bus_data_i_D1_reg[20] ),
.ip2bus_rdack_i_D1(ip2bus_rdack_i_D1),
.ip2bus_wrack_i_D1(ip2bus_wrack_i_D1),
.is_read(is_read),
.is_write_reg(is_write_reg_n_0),
.rst_reg(bus2ip_rnw_i_reg_0),
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arready(s_axi_arready),
.s_axi_wdata(s_axi_wdata),
.s_axi_wready(s_axi_wready),
.start2(start2));
LUT5 #(
.INIT(32'hABAAA8AA))
\bus2ip_addr_i[2]_i_1
(.I0(s_axi_awaddr[0]),
.I1(state[1]),
.I2(state[0]),
.I3(s_axi_arvalid),
.I4(s_axi_araddr[0]),
.O(\bus2ip_addr_i[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT5 #(
.INIT(32'hABAAA8AA))
\bus2ip_addr_i[3]_i_1
(.I0(s_axi_awaddr[1]),
.I1(state[1]),
.I2(state[0]),
.I3(s_axi_arvalid),
.I4(s_axi_araddr[1]),
.O(\bus2ip_addr_i[3]_i_1_n_0 ));
LUT5 #(
.INIT(32'hABAAA8AA))
\bus2ip_addr_i[8]_i_1
(.I0(s_axi_awaddr[2]),
.I1(state[1]),
.I2(state[0]),
.I3(s_axi_arvalid),
.I4(s_axi_araddr[2]),
.O(\bus2ip_addr_i[8]_i_1_n_0 ));
FDRE \bus2ip_addr_i_reg[2]
(.C(s_axi_aclk),
.CE(start2_i_1_n_0),
.D(\bus2ip_addr_i[2]_i_1_n_0 ),
.Q(bus2ip_addr[6]),
.R(bus2ip_rnw_i_reg_0));
FDRE \bus2ip_addr_i_reg[3]
(.C(s_axi_aclk),
.CE(start2_i_1_n_0),
.D(\bus2ip_addr_i[3]_i_1_n_0 ),
.Q(bus2ip_addr[5]),
.R(bus2ip_rnw_i_reg_0));
FDRE \bus2ip_addr_i_reg[8]
(.C(s_axi_aclk),
.CE(start2_i_1_n_0),
.D(\bus2ip_addr_i[8]_i_1_n_0 ),
.Q(bus2ip_addr[0]),
.R(bus2ip_rnw_i_reg_0));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT3 #(
.INIT(8'h02))
bus2ip_rnw_i_i_1
(.I0(s_axi_arvalid),
.I1(state[0]),
.I2(state[1]),
.O(bus2ip_rnw_i06_out));
FDRE bus2ip_rnw_i_reg
(.C(s_axi_aclk),
.CE(start2_i_1_n_0),
.D(bus2ip_rnw_i06_out),
.Q(\ip2bus_data_i_D1_reg[31] ),
.R(bus2ip_rnw_i_reg_0));
LUT5 #(
.INIT(32'h3FFA000A))
is_read_i_1
(.I0(s_axi_arvalid),
.I1(\state[1]_i_2_n_0 ),
.I2(state[1]),
.I3(state[0]),
.I4(is_read),
.O(is_read_i_1_n_0));
FDRE is_read_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(is_read_i_1_n_0),
.Q(is_read),
.R(bus2ip_rnw_i_reg_0));
LUT6 #(
.INIT(64'h1000FFFF10000000))
is_write_i_1
(.I0(state[1]),
.I1(s_axi_arvalid),
.I2(s_axi_wvalid),
.I3(s_axi_awvalid),
.I4(is_write),
.I5(is_write_reg_n_0),
.O(is_write_i_1_n_0));
LUT6 #(
.INIT(64'hF88800000000FFFF))
is_write_i_2
(.I0(s_axi_bready),
.I1(s_axi_bvalid),
.I2(s_axi_rready),
.I3(s_axi_rvalid),
.I4(state[1]),
.I5(state[0]),
.O(is_write));
FDRE is_write_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(is_write_i_1_n_0),
.Q(is_write_reg_n_0),
.R(bus2ip_rnw_i_reg_0));
LUT1 #(
.INIT(2'h1))
rst_i_1
(.I0(s_axi_aresetn),
.O(p_1_in));
FDRE rst_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(p_1_in),
.Q(bus2ip_rnw_i_reg_0),
.R(1'b0));
LUT5 #(
.INIT(32'h08FF0808))
s_axi_bvalid_i_i_1
(.I0(s_axi_wready),
.I1(state[1]),
.I2(state[0]),
.I3(s_axi_bready),
.I4(s_axi_bvalid),
.O(s_axi_bvalid_i_i_1_n_0));
FDRE #(
.INIT(1'b0))
s_axi_bvalid_i_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_axi_bvalid_i_i_1_n_0),
.Q(s_axi_bvalid),
.R(bus2ip_rnw_i_reg_0));
LUT2 #(
.INIT(4'h2))
\s_axi_rdata_i[11]_i_1
(.I0(state[0]),
.I1(state[1]),
.O(s_axi_rdata_i));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[0]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(\ip2bus_data_i_D1_reg[20]_0 [0]),
.Q(s_axi_rdata[0]),
.R(bus2ip_rnw_i_reg_0));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[10]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(\ip2bus_data_i_D1_reg[20]_0 [10]),
.Q(s_axi_rdata[10]),
.R(bus2ip_rnw_i_reg_0));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[11]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(\ip2bus_data_i_D1_reg[20]_0 [11]),
.Q(s_axi_rdata[11]),
.R(bus2ip_rnw_i_reg_0));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[1]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(\ip2bus_data_i_D1_reg[20]_0 [1]),
.Q(s_axi_rdata[1]),
.R(bus2ip_rnw_i_reg_0));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[2]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(\ip2bus_data_i_D1_reg[20]_0 [2]),
.Q(s_axi_rdata[2]),
.R(bus2ip_rnw_i_reg_0));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[3]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(\ip2bus_data_i_D1_reg[20]_0 [3]),
.Q(s_axi_rdata[3]),
.R(bus2ip_rnw_i_reg_0));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[4]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(\ip2bus_data_i_D1_reg[20]_0 [4]),
.Q(s_axi_rdata[4]),
.R(bus2ip_rnw_i_reg_0));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[5]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(\ip2bus_data_i_D1_reg[20]_0 [5]),
.Q(s_axi_rdata[5]),
.R(bus2ip_rnw_i_reg_0));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[6]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(\ip2bus_data_i_D1_reg[20]_0 [6]),
.Q(s_axi_rdata[6]),
.R(bus2ip_rnw_i_reg_0));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[7]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(\ip2bus_data_i_D1_reg[20]_0 [7]),
.Q(s_axi_rdata[7]),
.R(bus2ip_rnw_i_reg_0));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[8]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(\ip2bus_data_i_D1_reg[20]_0 [8]),
.Q(s_axi_rdata[8]),
.R(bus2ip_rnw_i_reg_0));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[9]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(\ip2bus_data_i_D1_reg[20]_0 [9]),
.Q(s_axi_rdata[9]),
.R(bus2ip_rnw_i_reg_0));
LUT5 #(
.INIT(32'h08FF0808))
s_axi_rvalid_i_i_1
(.I0(s_axi_arready),
.I1(state[0]),
.I2(state[1]),
.I3(s_axi_rready),
.I4(s_axi_rvalid),
.O(s_axi_rvalid_i_i_1_n_0));
FDRE #(
.INIT(1'b0))
s_axi_rvalid_i_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_axi_rvalid_i_i_1_n_0),
.Q(s_axi_rvalid),
.R(bus2ip_rnw_i_reg_0));
LUT5 #(
.INIT(32'h000000F8))
start2_i_1
(.I0(s_axi_awvalid),
.I1(s_axi_wvalid),
.I2(s_axi_arvalid),
.I3(state[0]),
.I4(state[1]),
.O(start2_i_1_n_0));
FDRE start2_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(start2_i_1_n_0),
.Q(start2),
.R(bus2ip_rnw_i_reg_0));
LUT5 #(
.INIT(32'h0FFFAACC))
\state[0]_i_1
(.I0(s_axi_wready),
.I1(s_axi_arvalid),
.I2(\state[1]_i_2_n_0 ),
.I3(state[1]),
.I4(state[0]),
.O(\state[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'h2E2E2E2ECCCCFFCC))
\state[1]_i_1
(.I0(s_axi_arready),
.I1(state[1]),
.I2(\state[1]_i_2_n_0 ),
.I3(\state[1]_i_3_n_0 ),
.I4(s_axi_arvalid),
.I5(state[0]),
.O(\state[1]_i_1_n_0 ));
LUT4 #(
.INIT(16'hF888))
\state[1]_i_2
(.I0(s_axi_bready),
.I1(s_axi_bvalid),
.I2(s_axi_rready),
.I3(s_axi_rvalid),
.O(\state[1]_i_2_n_0 ));
LUT2 #(
.INIT(4'h8))
\state[1]_i_3
(.I0(s_axi_awvalid),
.I1(s_axi_wvalid),
.O(\state[1]_i_3_n_0 ));
FDRE \state_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\state[0]_i_1_n_0 ),
.Q(state[0]),
.R(bus2ip_rnw_i_reg_0));
FDRE \state_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\state[1]_i_1_n_0 ),
.Q(state[1]),
.R(bus2ip_rnw_i_reg_0));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
`timescale 1ns/1ps
module Control(PCSrc,RegDst,RegWr,ALUSrc1,ALUSrc2,ALUFun,Sign,
MemWr,MemRd,MemToReg,EXTOp,LUOp,Instruction,IRQ,supervisor);
output reg [2:0]PCSrc;
output reg [1:0]RegDst;
output reg RegWr;
output reg ALUSrc1;
output reg ALUSrc2;
output reg [5:0]ALUFun;
output reg Sign;
output reg MemWr;
output reg MemRd;
output reg [1:0]MemToReg;
output reg EXTOp;
output reg LUOp;
input [31:0]Instruction;
input IRQ;
input supervisor;
always@(*)
begin
if(IRQ & (~supervisor)) //interrupt
begin
PCSrc <= 3'b100;
RegDst <= 2'b11;
RegWr <= 1;
MemWr <= 0;
MemRd <= 0;
MemToReg <= 2'b11;
end
else
begin
case(Instruction[31:26])
6'h23: //lw
begin
PCSrc <= 3'b000;
RegDst <= 2'b01;
RegWr <= 1;
ALUSrc1 <= 0;
ALUSrc2 <= 1;
ALUFun <= 6'b000000;
Sign <= 1;
MemWr <= 0;
MemRd <= 1;
MemToReg <= 2'b01;
EXTOp <= 1;
LUOp <= 0;
end
6'h2b: //sw
begin
PCSrc <= 3'b000;
RegWr <= 0;
ALUSrc1 <= 0;
ALUSrc2 <= 1;
ALUFun <= 6'b000000;
Sign <= 1;
MemWr <= 1;
MemRd <= 0;
EXTOp <= 1;
LUOp <= 0;
end
6'h0f:
begin
case(Instruction[25:21])
5'h00: //lui
begin
PCSrc <= 3'b000;
RegDst <= 2'b01;
RegWr <= 1;
ALUSrc1 <= 0;
ALUSrc2 <= 1;
ALUFun <= 6'b000000;
Sign <= 1;
MemWr <= 0;
MemRd <= 0;
MemToReg <= 2'b00;
LUOp <= 1;
end
default: //XADR
begin
PCSrc <= 3'b101;
RegDst <= 2'b11;
RegWr <= 1;
MemWr <= 0;
MemRd <= 0;
MemToReg <= 2'b10;
end
endcase
end
6'h08: //addi
begin
PCSrc <= 3'b000;
RegDst <= 2'b01;
RegWr <= 1;
ALUSrc1 <= 0;
ALUSrc2 <= 1;
ALUFun <= 6'b000000;
Sign <= 1;
MemWr <= 0;
MemRd <= 0;
MemToReg <= 2'b00;
EXTOp <= 1;
LUOp <= 0;
end
6'h09: //addiu
begin
PCSrc <= 3'b000;
RegDst <= 2'b01;
RegWr <= 1;
ALUSrc1 <= 0;
ALUSrc2 <= 1;
ALUFun <= 6'b000000;
Sign <= 1;
MemWr <= 0;
MemRd <= 0;
MemToReg <= 2'b00;
EXTOp <= 1;
LUOp <= 0;
end
6'h0c: //andi
begin
PCSrc <= 3'b000;
RegDst <= 2'b01;
RegWr <= 1;
ALUSrc1 <= 0;
ALUSrc2 <= 1;
ALUFun <= 6'b011000;
Sign <= 0;
MemWr <= 0;
MemRd <= 0;
MemToReg <= 2'b00;
EXTOp <= 0;
LUOp <= 0;
end
6'h0a: //slti
begin
PCSrc <= 3'b000;
RegDst <= 2'b01;
RegWr <= 1;
ALUSrc1 <= 0;
ALUSrc2 <= 1;
ALUFun <= 6'b110101;
Sign <= 1;
MemWr <= 0;
MemRd <= 0;
MemToReg <= 2'b00;
EXTOp <= 1;
LUOp <= 0;
end
6'h0b: //sltiu
begin
PCSrc <= 3'b000;
RegDst <= 2'b01;
RegWr <= 1;
ALUSrc1 <= 0;
ALUSrc2 <= 1;
ALUFun <= 6'b110101;
Sign <= 0;
MemWr <= 0;
MemRd <= 0;
MemToReg <= 2'b00;
EXTOp <= 0;
LUOp <= 0;
end
6'h02: //j
begin
PCSrc <= 3'b010;
RegWr <= 0;
MemWr <= 0;
MemRd <= 0;
end
6'h03: //jal
begin
PCSrc <= 3'b010;
RegDst <= 2'b10;
RegWr <= 1;
MemWr <= 0;
MemRd <= 0;
MemToReg <= 2'b10;
end
6'h04: //beq
begin
PCSrc <= 3'b001;
RegWr <= 0;
ALUFun <= 6'b110011;
ALUSrc1 <= 0;
ALUSrc2 <= 0;
MemWr <= 0;
MemRd <= 0;
end
6'h05: //bne
begin
PCSrc <= 3'b001;
RegWr <= 0;
ALUFun <= 6'b110001;
ALUSrc1 <= 0;
ALUSrc2 <= 0;
MemWr <= 0;
MemRd <= 0;
end
6'h06:
begin
case(Instruction[20:16])
5'h00: //blez
begin
PCSrc <= 3'b001;
RegWr <= 0;
ALUFun <= 6'b111101;
ALUSrc1 <= 0;
ALUSrc2 <= 0;
MemWr <= 0;
MemRd <= 0;
end
default: //XADR
begin
PCSrc <= 3'b101;
RegDst <= 2'b11;
RegWr <= 1;
MemWr <= 0;
MemRd <= 0;
MemToReg <= 2'b10;
end
endcase
end
6'h07:
begin
case(Instruction[20:16])
5'h00: //bgtz
begin
PCSrc <= 3'b001;
RegWr <= 0;
ALUFun <= 6'b111111;
ALUSrc1 <= 0;
ALUSrc2 <= 0;
MemWr <= 0;
MemRd <= 0;
end
default: //XADR
begin
PCSrc <= 3'b101;
RegDst <= 2'b11;
RegWr <= 1;
MemWr <= 0;
MemRd <= 0;
MemToReg <= 2'b10;
end
endcase
end
6'h01:
begin
case(Instruction[20:16])
5'h01: //bgez
begin
PCSrc <= 3'b001;
RegWr <= 0;
ALUFun <= 6'b111001;
ALUSrc1 <= 0;
ALUSrc2 <= 0;
MemWr <= 0;
MemRd <= 0;
end
default: //XADR
begin
PCSrc <= 3'b101;
RegDst <= 2'b11;
RegWr <= 1;
MemWr <= 0;
MemRd <= 0;
MemToReg <= 2'b10;
end
endcase
end
6'h00:
begin
case(Instruction[5:0])
6'h20:
begin
case(Instruction[10:6])
5'h00: //add
begin
PCSrc <= 3'b000;
RegDst <= 2'b00;
RegWr <= 1;
ALUSrc1 <= 0;
ALUSrc2 <= 0;
ALUFun <= 6'b000000;
Sign <= 1;
MemWr <= 0;
MemRd <= 0;
MemToReg <= 2'b00;
end
default: //XADR
begin
PCSrc <= 3'b101;
RegDst <= 2'b11;
RegWr <= 1;
MemWr <= 0;
MemRd <= 0;
MemToReg <= 2'b10;
end
endcase
end
6'h21:
begin
case(Instruction[10:6])
5'h00: //addu
begin
PCSrc <= 3'b000;
RegDst <= 2'b00;
RegWr <= 1;
ALUSrc1 <= 0;
ALUSrc2 <= 0;
ALUFun <= 6'b000000;
Sign <= 1;
MemWr <= 0;
MemRd <= 0;
MemToReg <= 2'b00;
end
default: //XADR
begin
PCSrc <= 3'b101;
RegDst <= 2'b11;
RegWr <= 1;
MemWr <= 0;
MemRd <= 0;
MemToReg <= 2'b10;
end
endcase
end
6'h22:
begin
case(Instruction[10:6])
5'h00: //sub
begin
PCSrc <= 3'b000;
RegDst <= 2'b00;
RegWr <= 1;
ALUSrc1 <= 0;
ALUSrc2 <= 0;
ALUFun <= 6'b000001;
Sign <= 1;
MemWr <= 0;
MemRd <= 0;
MemToReg <= 2'b00;
end
default: //XADR
begin
PCSrc <= 3'b101;
RegDst <= 2'b11;
RegWr <= 1;
MemWr <= 0;
MemRd <= 0;
MemToReg <= 2'b10;
end
endcase
end
6'h23:
begin
case(Instruction[10:6])
5'h00: //subu
begin
PCSrc <= 3'b000;
RegDst <= 2'b00;
RegWr <= 1;
ALUSrc1 <= 0;
ALUSrc2 <= 0;
ALUFun <= 6'b000001;
Sign <= 0;
MemWr <= 0;
MemRd <= 0;
MemToReg <= 2'b00;
end
default: //XADR
begin
PCSrc <= 3'b101;
RegDst <= 2'b11;
RegWr <= 1;
MemWr <= 0;
MemRd <= 0;
MemToReg <= 2'b10;
end
endcase
end
6'h24:
begin
case(Instruction[10:6])
5'h00: //and
begin
PCSrc <= 3'b000;
RegDst <= 2'b00;
RegWr <= 1;
ALUSrc1 <= 0;
ALUSrc2 <= 0;
ALUFun <= 6'b011000;
Sign <= 0;
MemWr <= 0;
MemRd <= 0;
MemToReg <= 2'b00;
end
default: //XADR
begin
PCSrc <= 3'b101;
RegDst <= 2'b11;
RegWr <= 1;
MemWr <= 0;
MemRd <= 0;
MemToReg <= 2'b10;
end
endcase
end
6'h25:
begin
case(Instruction[10:6])
5'h00: //or
begin
PCSrc <= 3'b000;
RegDst <= 2'b00;
RegWr <= 1;
ALUSrc1 <= 0;
ALUSrc2 <= 0;
ALUFun <= 6'b011110;
Sign <= 0;
MemWr <= 0;
MemRd <= 0;
MemToReg <= 2'b00;
end
default: //XADR
begin
PCSrc <= 3'b101;
RegDst <= 2'b11;
RegWr <= 1;
MemWr <= 0;
MemRd <= 0;
MemToReg <= 2'b10;
end
endcase
end
6'h26:
begin
case(Instruction[10:6])
5'h00: //xor
begin
PCSrc <= 3'b000;
RegDst <= 2'b00;
RegWr <= 1;
ALUSrc1 <= 0;
ALUSrc2 <= 0;
ALUFun <= 6'b010110;
Sign <= 0;
MemWr <= 0;
MemRd <= 0;
MemToReg <= 2'b00;
end
default: //XADR
begin
PCSrc <= 3'b101;
RegDst <= 2'b11;
RegWr <= 1;
MemWr <= 0;
MemRd <= 0;
MemToReg <= 2'b10;
end
endcase
end
6'h27:
begin
case(Instruction[10:6])
5'h00: //nor
begin
PCSrc <= 3'b000;
RegDst <= 2'b00;
RegWr <= 1;
ALUSrc1 <= 0;
ALUSrc2 <= 0;
ALUFun <= 6'b010001;
Sign <= 0;
MemWr <= 0;
MemRd <= 0;
MemToReg <= 2'b00;
end
default: //XADR
begin
PCSrc <= 3'b101;
RegDst <= 2'b11;
RegWr <= 1;
MemWr <= 0;
MemRd <= 0;
MemToReg <= 2'b10;
end
endcase
end
6'h00: //sll
begin
PCSrc <= 3'b000;
RegDst <= 2'b00;
RegWr <= 1;
ALUSrc1 <= 1;
ALUSrc2 <= 0;
ALUFun <= 6'b100000;
Sign <= 0;
MemWr <= 0;
MemRd <= 0;
MemToReg <= 2'b00;
end
6'h02: //srl
begin
PCSrc <= 3'b000;
RegDst <= 2'b00;
RegWr <= 1;
ALUSrc1 <= 1;
ALUSrc2 <= 0;
ALUFun <= 6'b100001;
Sign <= 0;
MemWr <= 0;
MemRd <= 0;
MemToReg <= 2'b00;
end
6'h03: //sra
begin
PCSrc <= 3'b000;
RegDst <= 2'b00;
RegWr <= 1;
ALUSrc1 <= 1;
ALUSrc2 <= 0;
ALUFun <= 6'b100011;
Sign <= 0;
MemWr <= 0;
MemRd <= 0;
MemToReg <= 2'b00;
end
6'h2a:
begin
case(Instruction[10:6])
5'h00: //slt
begin
PCSrc <= 3'b000;
RegDst <= 2'b00;
RegWr <= 1;
ALUSrc1 <= 0;
ALUSrc2 <= 0;
ALUFun <= 6'b110101;
Sign <= 0;
MemWr <= 0;
MemRd <= 0;
MemToReg <= 2'b00;
end
default: //XADR
begin
PCSrc <= 3'b101;
RegDst <= 2'b11;
RegWr <= 1;
MemWr <= 0;
MemRd <= 0;
MemToReg <= 2'b10;
end
endcase
end
6'h2b:
begin
case(Instruction[10:6])
5'h00: //sltu
begin
PCSrc <= 3'b000;
RegDst <= 2'b00;
RegWr <= 1;
ALUSrc1 <= 0;
ALUSrc2 <= 0;
ALUFun <= 6'b110101;
Sign <= 0;
MemWr <= 0;
MemRd <= 0;
MemToReg <= 2'b00;
end
default: //XADR
begin
PCSrc <= 3'b101;
RegDst <= 2'b11;
RegWr <= 1;
MemWr <= 0;
MemRd <= 0;
MemToReg <= 2'b10;
end
endcase
end
6'h08:
begin
case(Instruction[20:6])
15'h0: //jr
begin
PCSrc <= 3'b011;
RegWr <= 0;
MemWr <= 0;
MemRd <= 0;
end
default: //XADR
begin
PCSrc <= 3'b101;
RegDst <= 2'b11;
RegWr <= 1;
MemWr <= 0;
MemRd <= 0;
MemToReg <= 2'b10;
end
endcase
end
6'h09:
begin
if((Instruction[10:6] == 0) && (Instruction[15:11] == 0))
//jalr
begin
PCSrc <= 3'b011;
RegDst <= 2'b00;
RegWr <= 1;
MemWr <= 0;
MemRd <= 0;
MemToReg <= 2'b10;
end
else //XADR
begin
PCSrc <= 3'b101;
RegDst <= 2'b11;
RegWr <= 1;
MemWr <= 0;
MemRd <= 0;
MemToReg <= 2'b10;
end
end
default: //XADR
begin
PCSrc <= 3'b101;
RegDst <= 2'b11;
RegWr <= 1;
MemWr <= 0;
MemRd <= 0;
MemToReg <= 2'b10;
end
endcase
end
default: //XADR
begin
PCSrc <= 3'b101;
RegDst <= 2'b11;
RegWr <= 1;
MemWr <= 0;
MemRd <= 0;
MemToReg <= 2'b10;
end
endcase
end
end
endmodule
|
//////////////////////////////////////////////////////////////////
// //
// Barrel Shifter for Amber 2 Core //
// //
// The design is optimized for Altera family of FPGAs, //
// and it can be used directly or adapted other N-to-1 LUT //
// FPGA platforms. //
// //
// This file is part of the Amber project //
// http://www.opencores.org/project,amber //
// //
// Description //
// Provides 32-bit shifts LSL, LSR, ASR and ROR //
// //
// Author(s): //
// - Dmitry Tarnyagin, [email protected] //
// //
//////////////////////////////////////////////////////////////////
// //
// Copyright (C) 2010-2013 Authors and OPENCORES.ORG //
// //
// This source file may be used and distributed without //
// restriction provided that this copyright statement is not //
// removed from the file and that any derivative work contains //
// the original copyright notice and the associated disclaimer. //
// //
// This source file is free software; you can redistribute it //
// and/or modify it under the terms of the GNU Lesser General //
// Public License as published by the Free Software Foundation; //
// either version 2.1 of the License, or (at your option) any //
// later version. //
// //
// This source is distributed in the hope that it will be //
// useful, but WITHOUT ANY WARRANTY; without even the implied //
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
// PURPOSE. See the GNU Lesser General Public License for more //
// details. //
// //
// You should have received a copy of the GNU Lesser General //
// Public License along with this source; if not, download it //
// from http://www.opencores.org/lgpl.shtml //
// //
//////////////////////////////////////////////////////////////////
module a23_barrel_shift_fpga (
input [31:0] i_in,
input i_carry_in,
input [7:0] i_shift_amount, // uses 8 LSBs of Rs, or a 5 bit immediate constant
input i_shift_imm_zero, // high when immediate shift value of zero selected
input [1:0] i_function,
output [31:0] o_out,
output o_carry_out
);
`include "a23_localparams.vh"
wire [31:0] rot_prod; // Input rotated by the shift amount
wire [1:0] lsl_out; // LSL: {carry, bit_31}
wire [1:0] lsr_out; // LSR: {carry, bit_31}
wire [1:0] asr_out; // ASR: {carry, bit_31}
wire [1:0] ror_out; // ROR: {carry, bit_31}
reg [32:0] lsl_mask; // Left-hand mask
reg [32:0] lsr_mask; // Right-hand mask
reg [15:0] low_mask; // Mask calculation helper
reg [4:0] shift_amount; // Shift amount for the low-level shifter
reg [2:0] lsl_selector; // Left shift {shift_32, shift_over, shift_amount[4]}
reg [2:0] lsr_selector; // Right shift {shift_32, shift_over, shift_amount[4]}
reg [3:0] low_selector; // {shift_amount[3:0]}
reg shift_nzero; // Amount is not zero
reg shift_over; // Amount is 32 or higher
reg shift_32; // Amount is exactly 32
reg asr_sign; // Sign for ASR shift
reg direction; // Shift direction
wire [31:0] p_r; // 1 bit rotated rot_prod
wire [31:0] p_l; // Alias for the rot_prod
// Implementation details:
// Design is based on masking of rotated input by a left- and right- hand masks.
// Rotated product calculation requires 5 levels of combinational logic, and masks
// must be ready before the product is ready. In fact masks require just 3 to 4 levels
// of logic cells using 4-to-1/2x3-to-1 Altera.
always @*
begin
shift_32 = i_shift_amount == 32;
shift_over = |i_shift_amount[7:5];
shift_nzero = |i_shift_amount[7:0];
shift_amount = i_shift_amount[4:0];
if (i_shift_imm_zero) begin
if (i_function == LSR || i_function == ASR) begin
// The form of the shift field which might be
// expected to correspond to LSR #0 is used
// to encode LSR #32, which has a zero result
// with bit 31 of Rm as the carry output.
shift_nzero = 1'b1;
shift_over = 1'b1;
// Redundant and can be optimized out
// shift_32 = 1'b1;
end else if (i_function == ROR) begin
// RXR, (ROR w/ imm 0)
shift_amount[0] = 1'b1;
shift_nzero = 1'b1;
end
end
// LSB sub-selector calculation. Usually it is taken
// directly from the shift_amount, but ROR requires
// no masking at all.
case (i_function)
LSL: low_selector = shift_amount[3:0];
LSR: low_selector = shift_amount[3:0];
ASR: low_selector = shift_amount[3:0];
ROR: low_selector = 4'b0000;
endcase
// Left-hand MSB sub-selector calculation. Opaque for every function but LSL.
case (i_function)
LSL: lsl_selector = {shift_32, shift_over, shift_amount[4]};
LSR: lsl_selector = 3'b0_1_0; // Opaque mask selector
ASR: lsl_selector = 3'b0_1_0; // Opaque mask selector
ROR: lsl_selector = 3'b0_1_0; // Opaque mask selector
endcase
// Right-hand MSB sub-selector calculation. Opaque for LSL, transparent for ROR.
case (i_function)
LSL: lsr_selector = 3'b0_1_0; // Opaque mask selector
LSR: lsr_selector = {shift_32, shift_over, shift_amount[4]};
ASR: lsr_selector = {shift_32, shift_over, shift_amount[4]};
ROR: lsr_selector = 3'b0_0_0; // Transparent mask selector
endcase
// Direction
case (i_function)
LSL: direction = 1'b0; // Left shift
LSR: direction = 1'b1; // Right shift
ASR: direction = 1'b1; // Right shift
ROR: direction = 1'b1; // Right shift
endcase
// Sign for ASR shift
asr_sign = 1'b0;
if (i_function == ASR && i_in[31])
asr_sign = 1'b1;
end
// Generic rotate. Theoretical cost: 32x5 4-to-1 LUTs.
// Practically a bit higher due to high fanout of "direction".
generate
genvar i, j;
for (i = 0; i < 5; i = i + 1)
begin : netgen
wire [31:0] in;
reg [31:0] out;
for (j = 0; j < 32; j = j + 1)
begin : net
always @*
out[j] = in[j] & (~shift_amount[i] ^ direction) |
in[wrap(j, i)] & (shift_amount[i] ^ direction);
end
end
// Order is reverted with respect to volatile shift_amount[0]
assign netgen[4].in = i_in;
for (i = 1; i < 5; i = i + 1)
begin : router
assign netgen[i-1].in = netgen[i].out;
end
endgenerate
// Aliasing
assign rot_prod = netgen[0].out;
// Submask calculated from LSB sub-selector.
// Cost: 16 4-to-1 LUTs.
always @*
case (low_selector) // synthesis full_case parallel_case
4'b0000: low_mask = 16'hffff;
4'b0001: low_mask = 16'hfffe;
4'b0010: low_mask = 16'hfffc;
4'b0011: low_mask = 16'hfff8;
4'b0100: low_mask = 16'hfff0;
4'b0101: low_mask = 16'hffe0;
4'b0110: low_mask = 16'hffc0;
4'b0111: low_mask = 16'hff80;
4'b1000: low_mask = 16'hff00;
4'b1001: low_mask = 16'hfe00;
4'b1010: low_mask = 16'hfc00;
4'b1011: low_mask = 16'hf800;
4'b1100: low_mask = 16'hf000;
4'b1101: low_mask = 16'he000;
4'b1110: low_mask = 16'hc000;
4'b1111: low_mask = 16'h8000;
endcase
// Left-hand mask calculation.
// Cost: 33 4-to-1 LUTs.
always @*
casez (lsl_selector) // synthesis full_case parallel_case
7'b1??: lsl_mask = 33'h_1_0000_0000;
7'b01?: lsl_mask = 33'h_0_0000_0000;
7'b001: lsl_mask = { 1'h_1, low_mask, 16'h_0000};
7'b000: lsl_mask = {17'h_1_ffff, low_mask};
endcase
// Right-hand mask calculation.
// Cost: 33 4-to-1 LUTs.
always @*
casez (lsr_selector) // synthesis full_case parallel_case
7'b1??: lsr_mask = 33'h_1_0000_0000;
7'b01?: lsr_mask = 33'h_0_0000_0000;
7'b000: lsr_mask = { 1'h_1, bit_swap(low_mask), 16'h_ffff};
7'b001: lsr_mask = {17'h_1_0000, bit_swap(low_mask)};
endcase
// Alias: right-rotated
assign p_r = {rot_prod[30:0], rot_prod[31]};
// Alias: left-rotated
assign p_l = rot_prod[31:0];
// ROR MSB, handling special cases
assign ror_out[0] = i_shift_imm_zero ? i_carry_in :
p_r[31];
// ROR carry, handling special cases
assign ror_out[1] = i_shift_imm_zero ? i_in[0] :
shift_nzero ? p_r[31] :
i_carry_in;
// LSL MSB
assign lsl_out[0] = p_l[31] & lsl_mask[31];
// LSL carry, handling special cases
assign lsl_out[1] = shift_nzero ? p_l[0] & lsl_mask[32]:
i_carry_in;
// LSR MSB
assign lsr_out[0] = p_r[31] & lsr_mask[31];
// LSR carry, handling special cases
assign lsr_out[1] = i_shift_imm_zero ? i_in[31] :
shift_nzero ? p_r[31] & lsr_mask[32]:
i_carry_in;
// ASR MSB
assign asr_out[0] = i_in[31] ? i_in[31] :
p_r[31] & lsr_mask[31] ;
// LSR carry, handling special cases
assign asr_out[1] = shift_over ? i_in[31] :
shift_nzero ? p_r[31] :
i_carry_in;
// Carry and MSB are calculated as above
assign {o_carry_out, o_out[31]} = i_function == LSL ? lsl_out :
i_function == LSR ? lsr_out :
i_function == ASR ? asr_out :
ror_out ;
// And the rest of result is the masked rotated input.
assign o_out[30:0] = (p_l[30:0] & lsl_mask[30:0]) |
(p_r[30:0] & lsr_mask[30:0]) |
(~lsr_mask[30:0] & {31{asr_sign}});
// Rotate: calculate bit pos for level "level" and offset "pos"
function [4:0] wrap;
input integer pos;
input integer level;
integer out;
begin
out = pos - (1 << level);
wrap = out[4:0];
end
endfunction
// Swap bits in the input 16-bit value
function [15:0] bit_swap;
input [15:0] value;
integer i;
begin
for (i = 0; i < 16; i = i + 1)
bit_swap[i] = value[15 - i];
end
endfunction
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 23:44:06 07/28/2013
// Design Name:
// Module Name: SimpleQuadratureCounter
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module BBot_SimpleQuadratureCounter(
input clock,
input reset_l,
input A,
input B,
output [31:0] CurrentCount,
output Direction
);
reg BPrevious;
reg APrevious;
reg ACurrent;
reg BCurrent;
reg[31:0] Count;
reg[31:0] CountOutput;
reg Dir;
reg DirectionOutput;
always @(posedge clock) begin
if (reset_l == 1'b0)
begin
Count[31:0] <= 32'h80000000;
end
else
begin
if( (APrevious != A) || (BPrevious != B))
begin
//Every time A or B changes evaluate this XOR
//If the result is 1 we count up if it's 0 we count down
if (A ^ BPrevious)
begin
Count <= Count + 1'b1;
Dir <= 1'b1;
end
else begin
Count <= Count - 1'b1;
Dir <= 1'b0;
end
end
end
end
always @(negedge clock) begin
//On the negedge of clock set the previous values and
//send the count out the door
APrevious <= A;
BPrevious <= B;
CountOutput <= Count;
DirectionOutput <= Dir;
end
assign CurrentCount = CountOutput;
assign Direction = DirectionOutput;
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: jbi_ncio_mrqq_buf.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
/////////////////////////////////////////////////////////////////////////
/*
//
// Description: Write Decomposition Queue Buffer
// Top level Module: jbi_ncio_mrqq_buf
// Where Instantiated: jbi_ncio
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
`include "sys.h" // system level definition file which contains the
// time scale definition
`include "jbi.h"
module jbi_ncio_mrqq_buf(/*AUTOARG*/
// Outputs
mrqq_rdata,
// Inputs
clk, arst_l, hold, rst_tri_en, mrqq_wr_en, mrqq_rd_en, mrqq_waddr,
mrqq_raddr, mrqq_wdata
);
input clk;
input arst_l;
input hold;
input rst_tri_en;
input mrqq_wr_en;
input mrqq_rd_en;
input [`JBI_MRQQ_ADDR_WIDTH-1:0] mrqq_waddr;
input [`JBI_MRQQ_ADDR_WIDTH-1:0] mrqq_raddr;
input [`JBI_MRQQ_WIDTH-1:0] mrqq_wdata;
output [`JBI_MRQQ_WIDTH-1:0] mrqq_rdata;
////////////////////////////////////////////////////////////////////////
// Interface signal type declarations
////////////////////////////////////////////////////////////////////////
wire [`JBI_MRQQ_WIDTH-1:0] mrqq_rdata;
////////////////////////////////////////////////////////////////////////
// Local signal declarations
////////////////////////////////////////////////////////////////////////
wire [160-`JBI_MRQQ_WIDTH-1:0] dangle;
//
// Code start here
//
jbi_1r1w_16x160 u_mrqq_buf
(// outputs
.dout ( {dangle,
mrqq_rdata} ),
// read inputs
.rdclk (clk),
.read_en (mrqq_rd_en),
.rd_adr (mrqq_raddr),
// write inputs
.wrclk (clk),
.wr_en (mrqq_wr_en),
.wr_adr (mrqq_waddr),
.din ( { {160-`JBI_MRQQ_WIDTH{1'b0}}, mrqq_wdata }),
// other inputs
.rst_l (arst_l),
.hold (hold),
.testmux_sel (1'b1), // always want data from FF
.rst_tri_en (rst_tri_en)
);
endmodule
// Local Variables:
// verilog-library-directories:("." "../../../common/mem/rtl/")
// verilog-auto-sense-defines-constant:t
// End:
|
module control (clk, cEnter, cEne, cDelete, cCounter, cNum, new, reset, complete, enter, delete, add, load, addEnhe, change, virgul, changeVirgul);
input clk;
input enter;
input virgul;
input cEne, cEnter;
input cDelete;
input cCounter;
input new;
input reset;
input cNum;
output reg complete;
output reg delete;
output reg add;
output reg load;
output reg addEnhe;
output reg change;
output reg changeVirgul;
reg [2:0] next_state;
parameter init=3'b000, new_data=3'b001, Add=3'b010, Delete=3'b011, ChangeVirgul=3'b100, AddEnhe=3'b101, Enter=3'b110, effect=3'b111;
always @( negedge clk )
begin
if (reset) next_state<=init;
else
case (next_state)
init: next_state<=new_data;
new_data: begin
if (cNum==1'b1 & enter==1'b1) next_state<=effect;
else if(cEnter==1'b1) next_state<=Enter;
else if((new==1'b0 | cCounter==1'b1) | (cNum==1'b0 & enter==1'b1)) next_state<=new_data;
else if (virgul==1'b1 & cEne==0) next_state<=ChangeVirgul;
else if((cDelete==1'b1 | (cEne==1'b1 & virgul==1'b1))) next_state<=Delete;
else next_state<=Add;
end
Add: next_state<=new_data;
Delete: begin
if (cEne==1'b1 & virgul==1) next_state<=AddEnhe;
else next_state<=new_data;
end
AddEnhe: next_state<=new_data;
Enter: next_state<=new_data;
effect: next_state<=init;
default: next_state<=new_data;
endcase
end
always @( next_state or cEne or virgul)
begin
case (next_state)
init: begin
complete=1'b0;
delete=1'b0;
add=1'b0;
load=1'b1;
addEnhe=1'b0;
change=1'b0;
changeVirgul=1'b0;
end
new_data: begin
complete=1'b0;
delete=1'b0;
add=1'b0;
load=1'b0;
addEnhe=1'b0;
change=1'b0;
changeVirgul=1'b0;
end
Add: begin
complete=1'b0;
delete=1'b0;
add=1'b1;
load=1'b0;
addEnhe=1'b0;
change=1'b1;
changeVirgul=1'b0;
end
Delete: begin
complete=1'b0;
delete=1'b1;
add=1'b0;
load=1'b0;
addEnhe=1'b0;
change=1'b1;
changeVirgul=1'b0;
end
ChangeVirgul: begin
complete=1'b0;
delete=1'b0;
add=1'b1;
load=1'b0;
addEnhe=1'b0;
change=1'b1;
changeVirgul=1'b1;
end
AddEnhe: begin
complete=1'b0;
delete=1'b0;
add=1'b1;
load=1'b0;
addEnhe=1'b1;
change=1'b1;
changeVirgul=1'b0;
end
Enter: begin
complete=1'b0;
delete=1'b0;
add=1'b0;
load=1'b0;
addEnhe=1'b0;
change=1'b1;
changeVirgul=1'b0;
end
effect: begin
complete=1'b1;
delete=1'b0;
add=1'b1;
load=1'b0;
addEnhe=1'b0;
change=1'b1;
changeVirgul=1'b0;
end
default: begin
complete=1'b0;
delete=1'b0;
add=1'b0;
load=1'b0;
addEnhe=1'b0;
change=1'b0;
changeVirgul=1'b0;
end
endcase
end
endmodule
|
/* lab3_part3.v - Master Slave D latch
*
* Copyright (c) 2014, Artem Tovbin <arty99 at gmail dot com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
+--------------------------------------+
| +------+ Qm +------+ |
D --+-----+D Q+--------------+D Q+---+-- Q
| | | | | |
| ~ | _| | _| | _
Clk -+-+--- Clk Q| +--Clk Q+---+-- Q
| | +------+ | +------+ |
| | | |
| +-----------------------+ |
| |
+--------------------------------------+
+-------------+
|D Q > Qnext|
|0 X F 0 |
|1 X F 1 |
+-------------+
*/
module lab3_part3 (SW, LEDR, LEDG);
input [1:0] SW;
output [1:0] LEDR, LEDG;
assign LEDR = SW;
wire Q;
MSDF F0(SW[1],SW[0],LEDG[0]);
endmodule
module MSDF(Clk, D, Q);
input Clk, D;
output Q;
wire Qm;
Dflop D0 (~Clk, D, Qm);
Dflop D1 (Clk, Qm, Q);
endmodule
module Dflop (Clk, D, Q);
input Clk, D;
output Q;
wire S, R;
assign S = D;
assign R = ~D;
wire R_g, S_g, Qa, Qb /* synthesis keep */;
/* S_g truth table
+--+---+----+
| D|Clk|S_g |
| 0| 0 | 1 |
| 0| 1 | 1 |
| 1| 0 | 1 |
| 1| 1 | 0 |
+--+---+----+
*/
assign S_g = S & Clk;
/* R_g truth table
+--+---+----+
| D|Clk|R_g |
| 0| 0 | 1 |
| 0| 1 | 0 |
| 1| 0 | 1 |
| 1| 1 | 1 |
+--+---+----+
*/
assign R_g = R & Clk;
assign Qa = ~(R_g | Qb);
assign Qb = ~(S_g | Qa);
assign Q = Qa;
endmodule
|
(** * Poly: Polymorphism and Higher-Order Functions *)
(** In this chapter we continue our development of basic
concepts of functional programming. The critical new ideas are
_polymorphism_ (abstracting functions over the types of the data
they manipulate) and _higher-order functions_ (treating functions
as data).
*)
Require Export Lists.
(* ###################################################### *)
(** * Polymorphism *)
(* ###################################################### *)
(** ** Polymorphic Lists *)
(** For the last couple of chapters, we've been working just
with lists of numbers. Obviously, interesting programs also need
to be able to manipulate lists with elements from other types --
lists of strings, lists of booleans, lists of lists, etc. We
_could_ just define a new inductive datatype for each of these,
for example... *)
Inductive boollist : Type :=
| bool_nil : boollist
| bool_cons : bool -> boollist -> boollist.
(** ... but this would quickly become tedious, partly because we
have to make up different constructor names for each datatype, but
mostly because we would also need to define new versions of all
our list manipulating functions ([length], [rev], etc.) for each
new datatype definition. *)
(** *** *)
(** To avoid all this repetition, Coq supports _polymorphic_
inductive type definitions. For example, here is a _polymorphic
list_ datatype. *)
Inductive list (X:Type) : Type :=
| nil : list X
| cons : X -> list X -> list X.
(** This is exactly like the definition of [natlist] from the
previous chapter, except that the [nat] argument to the [cons]
constructor has been replaced by an arbitrary type [X], a binding
for [X] has been added to the header, and the occurrences of
[natlist] in the types of the constructors have been replaced by
[list X]. (We can re-use the constructor names [nil] and [cons]
because the earlier definition of [natlist] was inside of a
[Module] definition that is now out of scope.) *)
(** What sort of thing is [list] itself? One good way to think
about it is that [list] is a _function_ from [Type]s to
[Inductive] definitions; or, to put it another way, [list] is a
function from [Type]s to [Type]s. For any particular type [X],
the type [list X] is an [Inductive]ly defined set of lists whose
elements are things of type [X]. *)
(** With this definition, when we use the constructors [nil] and
[cons] to build lists, we need to tell Coq the type of the
elements in the lists we are building -- that is, [nil] and [cons]
are now _polymorphic constructors_. Observe the types of these
constructors: *)
Check nil.
(* ===> nil : forall X : Type, list X *)
Check cons.
(* ===> cons : forall X : Type, X -> list X -> list X *)
(** The "[forall X]" in these types can be read as an additional
argument to the constructors that determines the expected types of
the arguments that follow. When [nil] and [cons] are used, these
arguments are supplied in the same way as the others. For
example, the list containing [2] and [1] is written like this: *)
Check (cons nat 2 (cons nat 1 (nil nat))).
(** (We've gone back to writing [nil] and [cons] explicitly here
because we haven't yet defined the [ [] ] and [::] notations for
the new version of lists. We'll do that in a bit.) *)
(** We can now go back and make polymorphic (or "generic")
versions of all the list-processing functions that we wrote
before. Here is [length], for example: *)
(** *** *)
Fixpoint length (X:Type) (l:list X) : nat :=
match l with
| nil => 0
| cons h t => S (length X t)
end.
(** Note that the uses of [nil] and [cons] in [match] patterns
do not require any type annotations: Coq already knows that the list
[l] contains elements of type [X], so there's no reason to include
[X] in the pattern. (More precisely, the type [X] is a parameter
of the whole definition of [list], not of the individual
constructors. We'll come back to this point later.)
As with [nil] and [cons], we can use [length] by applying it first
to a type and then to its list argument: *)
Example test_length1 :
length nat (cons nat 1 (cons nat 2 (nil nat))) = 2.
Proof. reflexivity. Qed.
(** To use our length with other kinds of lists, we simply
instantiate it with an appropriate type parameter: *)
Example test_length2 :
length bool (cons bool true (nil bool)) = 1.
Proof. reflexivity. Qed.
(** *** *)
(** Let's close this subsection by re-implementing a few other
standard list functions on our new polymorphic lists: *)
Fixpoint app (X : Type) (l1 l2 : list X)
: (list X) :=
match l1 with
| nil => l2
| cons h t => cons X h (app X t l2)
end.
Fixpoint snoc (X:Type) (l:list X) (v:X) : (list X) :=
match l with
| nil => cons X v (nil X)
| cons h t => cons X h (snoc X t v)
end.
Fixpoint rev (X:Type) (l:list X) : list X :=
match l with
| nil => nil X
| cons h t => snoc X (rev X t) h
end.
Example test_rev1 :
rev nat (cons nat 1 (cons nat 2 (nil nat)))
= (cons nat 2 (cons nat 1 (nil nat))).
Proof. reflexivity. Qed.
Example test_rev2:
rev bool (nil bool) = nil bool.
Proof. reflexivity. Qed.
Module MumbleBaz.
(** **** Exercise: 2 stars (mumble_grumble) *)
(** Consider the following two inductively defined types. *)
Inductive mumble : Type :=
| a : mumble
| b : mumble -> nat -> mumble
| c : mumble.
Inductive grumble (X:Type) : Type :=
| d : mumble -> grumble X
| e : X -> grumble X.
(** Which of the following are well-typed elements of [grumble X] for
some type [X]?
- [d (b a 5)]
X - [d mumble (b a 5)]
- [d bool (b a 5)]
X - [e bool true]
X - [e mumble (b c 0)]
- [e bool (b c 0)]
- [c]
[] *)
(** **** Exercise: 2 stars (baz_num_elts) *)
(** Consider the following inductive definition: *)
Inductive baz : Type :=
| x : baz -> baz
| y : baz -> bool -> baz.
(** How _many_ elements does the type [baz] have?
None.
[] *)
End MumbleBaz.
(* ###################################################### *)
(** *** Type Annotation Inference *)
(** Let's write the definition of [app] again, but this time we won't
specify the types of any of the arguments. Will Coq still accept
it? *)
Fixpoint app' X l1 l2 : list X :=
match l1 with
| nil => l2
| cons h t => cons X h (app' X t l2)
end.
(** Indeed it will. Let's see what type Coq has assigned to [app']: *)
Check app'.
(* ===> forall X : Type, list X -> list X -> list X *)
Check app.
(* ===> forall X : Type, list X -> list X -> list X *)
(** It has exactly the same type type as [app]. Coq was able to
use a process called _type inference_ to deduce what the types of
[X], [l1], and [l2] must be, based on how they are used. For
example, since [X] is used as an argument to [cons], it must be a
[Type], since [cons] expects a [Type] as its first argument;
matching [l1] with [nil] and [cons] means it must be a [list]; and
so on.
This powerful facility means we don't always have to write
explicit type annotations everywhere, although explicit type
annotations are still quite useful as documentation and sanity
checks. You should try to find a balance in your own code between
too many type annotations (so many that they clutter and distract)
and too few (which forces readers to perform type inference in
their heads in order to understand your code). *)
(* ###################################################### *)
(** *** Type Argument Synthesis *)
(** Whenever we use a polymorphic function, we need to pass it
one or more types in addition to its other arguments. For
example, the recursive call in the body of the [length] function
above must pass along the type [X]. But just like providing
explicit type annotations everywhere, this is heavy and verbose.
Since the second argument to [length] is a list of [X]s, it seems
entirely obvious that the first argument can only be [X] -- why
should we have to write it explicitly?
Fortunately, Coq permits us to avoid this kind of redundancy. In
place of any type argument we can write the "implicit argument"
[_], which can be read as "Please figure out for yourself what
type belongs here." More precisely, when Coq encounters a [_], it
will attempt to _unify_ all locally available information -- the
type of the function being applied, the types of the other
arguments, and the type expected by the context in which the
application appears -- to determine what concrete type should
replace the [_].
This may sound similar to type annotation inference -- and,
indeed, the two procedures rely on the same underlying mechanisms.
Instead of simply omitting the types of some arguments to a
function, like
app' X l1 l2 : list X :=
we can also replace the types with [_], like
app' (X : _) (l1 l2 : _) : list X :=
which tells Coq to attempt to infer the missing information, just
as with argument synthesis.
Using implicit arguments, the [length] function can be written
like this: *)
Fixpoint length' (X:Type) (l:list X) : nat :=
match l with
| nil => 0
| cons h t => S (length' _ t)
end.
(** In this instance, we don't save much by writing [_] instead of
[X]. But in many cases the difference can be significant. For
example, suppose we want to write down a list containing the
numbers [1], [2], and [3]. Instead of writing this... *)
Definition list123 :=
cons nat 1 (cons nat 2 (cons nat 3 (nil nat))).
(** ...we can use argument synthesis to write this: *)
Definition list123' := cons _ 1 (cons _ 2 (cons _ 3 (nil _))).
(* ###################################################### *)
(** *** Implicit Arguments *)
(** If fact, we can go further. To avoid having to sprinkle [_]'s
throughout our programs, we can tell Coq _always_ to infer the
type argument(s) of a given function. The [Arguments] directive
specifies the name of the function or constructor, and then lists
its argument names, with curly braces around any arguments to be
treated as implicit.
*)
Arguments nil {X}.
Arguments cons {X} _ _. (* use underscore for argument position that has no name *)
Arguments length {X} l.
Arguments app {X} l1 l2.
Arguments rev {X} l.
Arguments snoc {X} l v.
(* note: no _ arguments required... *)
Definition list123'' := cons 1 (cons 2 (cons 3 nil)).
Check (length list123'').
(** *** *)
(** Alternatively, we can declare an argument to be implicit while
defining the function itself, by surrounding the argument in curly
braces. For example: *)
Fixpoint length'' {X:Type} (l:list X) : nat :=
match l with
| nil => 0
| cons h t => S (length'' t)
end.
(** (Note that we didn't even have to provide a type argument to
the recursive call to [length'']; indeed, it is invalid to provide
one.) We will use this style whenever possible, although we will
continue to use use explicit [Argument] declarations for
[Inductive] constructors. *)
(** *** *)
(** One small problem with declaring arguments [Implicit] is
that, occasionally, Coq does not have enough local information to
determine a type argument; in such cases, we need to tell Coq that
we want to give the argument explicitly this time, even though
we've globally declared it to be [Implicit]. For example, suppose we
write this: *)
(* Definition mynil := nil. *)
(** If we uncomment this definition, Coq will give us an error,
because it doesn't know what type argument to supply to [nil]. We
can help it by providing an explicit type declaration (so that Coq
has more information available when it gets to the "application"
of [nil]): *)
Definition mynil : list nat := nil.
(** Alternatively, we can force the implicit arguments to be explicit by
prefixing the function name with [@]. *)
Check @nil.
Definition mynil' := @nil nat.
(** *** *)
(** Using argument synthesis and implicit arguments, we can
define convenient notation for lists, as before. Since we have
made the constructor type arguments implicit, Coq will know to
automatically infer these when we use the notations. *)
Notation "x :: y" := (cons x y)
(at level 60, right associativity).
Notation "[ ]" := nil.
Notation "[ x ; .. ; y ]" := (cons x .. (cons y []) ..).
Notation "x ++ y" := (app x y)
(at level 60, right associativity).
(** Now lists can be written just the way we'd hope: *)
Definition list123''' := [1; 2; 3].
Check ([3 + 4] ++ nil).
(* ###################################################### *)
(** *** Exercises: Polymorphic Lists *)
(** **** Exercise: 2 stars, optional (poly_exercises) *)
(** Here are a few simple exercises, just like ones in the [Lists]
chapter, for practice with polymorphism. Fill in the definitions
and complete the proofs below. *)
Fixpoint repeat {X : Type} (n : X) (count : nat) : list X :=
match count with
| O => nil
| S x => n :: repeat n x
end.
Example test_repeat1:
repeat true 2 = cons true (cons true nil).
Proof. reflexivity. Qed.
Theorem nil_app : forall X:Type, forall l:list X,
app [] l = l.
Proof.
intros. reflexivity. Qed.
Theorem rev_snoc : forall X : Type,
forall v : X,
forall s : list X,
rev (snoc s v) = v :: (rev s).
Proof.
intros. induction s as [| x xs].
Case "nil".
reflexivity.
Case "cons".
simpl. rewrite IHxs. reflexivity. Qed.
Theorem rev_involutive : forall X : Type, forall l : list X,
rev (rev l) = l.
Proof.
intros. induction l as [| x xs].
Case "nil".
reflexivity.
Case "cons".
simpl. rewrite rev_snoc. rewrite IHxs. reflexivity. Qed.
Theorem snoc_with_append : forall X : Type,
forall l1 l2 : list X,
forall v : X,
snoc (l1 ++ l2) v = l1 ++ (snoc l2 v).
Proof.
intros. induction l1 as [| x xs].
Case "nil".
reflexivity.
Case "cons".
simpl. rewrite IHxs. reflexivity. Qed.
(** [] *)
(* ###################################################### *)
(** ** Polymorphic Pairs *)
(** Following the same pattern, the type definition we gave in
the last chapter for pairs of numbers can be generalized to
_polymorphic pairs_ (or _products_): *)
Inductive prod (X Y : Type) : Type :=
pair : X -> Y -> prod X Y.
Arguments pair {X} {Y} _ _.
(** As with lists, we make the type arguments implicit and define the
familiar concrete notation. *)
Notation "( x , y )" := (pair x y).
(** We can also use the [Notation] mechanism to define the standard
notation for pair _types_: *)
Notation "X * Y" := (prod X Y) : type_scope.
(** (The annotation [: type_scope] tells Coq that this abbreviation
should be used when parsing types. This avoids a clash with the
multiplication symbol.) *)
(** *** *)
(** A note of caution: it is easy at first to get [(x,y)] and
[X*Y] confused. Remember that [(x,y)] is a _value_ built from two
other values; [X*Y] is a _type_ built from two other types. If
[x] has type [X] and [y] has type [Y], then [(x,y)] has type
[X*Y]. *)
(** The first and second projection functions now look pretty
much as they would in any functional programming language. *)
Definition fst {X Y : Type} (p : X * Y) : X :=
match p with (x,y) => x end.
Definition snd {X Y : Type} (p : X * Y) : Y :=
match p with (x,y) => y end.
(** The following function takes two lists and combines them
into a list of pairs. In many functional programming languages,
it is called [zip]. We call it [combine] for consistency with
Coq's standard library. *)
(** Note that the pair notation can be used both in expressions and in
patterns... *)
Fixpoint combine {X Y : Type} (lx : list X) (ly : list Y)
: list (X*Y) :=
match (lx,ly) with
| ([],_) => []
| (_,[]) => []
| (x::tx, y::ty) => (x,y) :: (combine tx ty)
end.
(** **** Exercise: 1 star, optional (combine_checks) *)
(** Try answering the following questions on paper and
checking your answers in coq:
- What is the type of [combine] (i.e., what does [Check
@combine] print?)
- What does
Eval compute in (combine [1;2] [false;false;true;true]).
print? []
*)
(** **** Exercise: 2 stars (split) *)
(** The function [split] is the right inverse of combine: it takes a
list of pairs and returns a pair of lists. In many functional
programing languages, this function is called [unzip].
Uncomment the material below and fill in the definition of
[split]. Make sure it passes the given unit tests. *)
Fixpoint split
{X Y : Type} (l : list (X*Y))
: (list X) * (list Y) :=
match l with
| nil => (nil, nil)
| cons (x, y) x0 =>
match split x0 with
| (xs, ys) => (x :: xs, y :: ys)
end
end.
Example test_split:
split [(1,false);(2,false)] = ([1;2],[false;false]).
Proof. reflexivity. Qed.
(** [] *)
(* ###################################################### *)
(** ** Polymorphic Options *)
(** One last polymorphic type for now: _polymorphic options_.
The type declaration generalizes the one for [natoption] in the
previous chapter: *)
Inductive option (X:Type) : Type :=
| Some : X -> option X
| None : option X.
Arguments Some {X} _.
Arguments None {X}.
(** *** *)
(** We can now rewrite the [index] function so that it works
with any type of lists. *)
Fixpoint index {X : Type} (n : nat)
(l : list X) : option X :=
match l with
| [] => None
| a :: l' => if beq_nat n O then Some a else index (pred n) l'
end.
Example test_index1 : index 0 [4;5;6;7] = Some 4.
Proof. reflexivity. Qed.
Example test_index2 : index 1 [[1];[2]] = Some [2].
Proof. reflexivity. Qed.
Example test_index3 : index 2 [true] = None.
Proof. reflexivity. Qed.
(** **** Exercise: 1 star, optional (hd_opt_poly) *)
(** Complete the definition of a polymorphic version of the
[hd_opt] function from the last chapter. Be sure that it
passes the unit tests below. *)
Definition hd_opt {X : Type} (l : list X) : option X :=
match l with
| nil => None
| cons x x0 => Some x
end.
(** Once again, to force the implicit arguments to be explicit,
we can use [@] before the name of the function. *)
Check @hd_opt.
Example test_hd_opt1 : hd_opt [1;2] = Some 1.
Proof. reflexivity. Qed.
Example test_hd_opt2 : hd_opt [[1];[2]] = Some [1].
Proof. reflexivity. Qed.
(** [] *)
(* ###################################################### *)
(** * Functions as Data *)
(* ###################################################### *)
(** ** Higher-Order Functions *)
(** Like many other modern programming languages -- including
all _functional languages_ (ML, Haskell, Scheme, etc.) -- Coq
treats functions as first-class citizens, allowing functions to be
passed as arguments to other functions, returned as results,
stored in data structures, etc.
Functions that manipulate other functions are often called
_higher-order_ functions. Here's a simple one: *)
Definition doit3times {X:Type} (f:X->X) (n:X) : X :=
f (f (f n)).
(** The argument [f] here is itself a function (from [X] to
[X]); the body of [doit3times] applies [f] three times to some
value [n]. *)
Check @doit3times.
(* ===> doit3times : forall X : Type, (X -> X) -> X -> X *)
Example test_doit3times: doit3times minustwo 9 = 3.
Proof. reflexivity. Qed.
Example test_doit3times': doit3times negb true = false.
Proof. reflexivity. Qed.
(* ###################################################### *)
(** ** Partial Application *)
(** In fact, the multiple-argument functions we have already
seen are also examples of passing functions as data. To see why,
recall the type of [plus]. *)
Check plus.
(* ==> nat -> nat -> nat *)
(** Each [->] in this expression is actually a _binary_ operator
on types. (This is the same as saying that Coq primitively
supports only one-argument functions -- do you see why?) This
operator is _right-associative_, so the type of [plus] is really a
shorthand for [nat -> (nat -> nat)] -- i.e., it can be read as
saying that "[plus] is a one-argument function that takes a [nat]
and returns a one-argument function that takes another [nat] and
returns a [nat]." In the examples above, we have always applied
[plus] to both of its arguments at once, but if we like we can
supply just the first. This is called _partial application_. *)
Definition plus3 := plus 3.
Check plus3.
Example test_plus3 : plus3 4 = 7.
Proof. reflexivity. Qed.
Example test_plus3' : doit3times plus3 0 = 9.
Proof. reflexivity. Qed.
Example test_plus3'' : doit3times (plus 3) 0 = 9.
Proof. reflexivity. Qed.
(* ###################################################### *)
(** ** Digression: Currying *)
(** **** Exercise: 2 stars, advanced (currying) *)
(** In Coq, a function [f : A -> B -> C] really has the type [A
-> (B -> C)]. That is, if you give [f] a value of type [A], it
will give you function [f' : B -> C]. If you then give [f'] a
value of type [B], it will return a value of type [C]. This
allows for partial application, as in [plus3]. Processing a list
of arguments with functions that return functions is called
_currying_, in honor of the logician Haskell Curry.
Conversely, we can reinterpret the type [A -> B -> C] as [(A *
B) -> C]. This is called _uncurrying_. With an uncurried binary
function, both arguments must be given at once as a pair; there is
no partial application. *)
(** We can define currying as follows: *)
Definition prod_curry {X Y Z : Type}
(f : X * Y -> Z) (x : X) (y : Y) : Z := f (x, y).
(** As an exercise, define its inverse, [prod_uncurry]. Then prove
the theorems below to show that the two are inverses. *)
Definition prod_uncurry {X Y Z : Type}
(f : X -> Y -> Z) (p : X * Y) : Z :=
f (fst p) (snd p).
(** (Thought exercise: before running these commands, can you
calculate the types of [prod_curry] and [prod_uncurry]?) *)
Check @prod_curry.
Check @prod_uncurry.
Theorem uncurry_curry : forall (X Y Z : Type) (f : X -> Y -> Z) x y,
prod_curry (prod_uncurry f) x y = f x y.
Proof.
intros. compute. reflexivity. Qed.
Theorem curry_uncurry : forall (X Y Z : Type)
(f : (X * Y) -> Z) (p : X * Y),
prod_uncurry (prod_curry f) p = f p.
Proof.
intros. destruct p. reflexivity. Qed.
(** [] *)
(* ###################################################### *)
(** ** Filter *)
(** Here is a useful higher-order function, which takes a list
of [X]s and a _predicate_ on [X] (a function from [X] to [bool])
and "filters" the list, returning a new list containing just those
elements for which the predicate returns [true]. *)
Fixpoint filter {X:Type} (test: X->bool) (l:list X)
: (list X) :=
match l with
| [] => []
| h :: t => if test h then h :: (filter test t)
else filter test t
end.
(** For example, if we apply [filter] to the predicate [evenb]
and a list of numbers [l], it returns a list containing just the
even members of [l]. *)
Example test_filter1: filter evenb [1;2;3;4] = [2;4].
Proof. reflexivity. Qed.
(** *** *)
Definition length_is_1 {X : Type} (l : list X) : bool :=
beq_nat (length l) 1.
Example test_filter2:
filter length_is_1
[ [1; 2]; [3]; [4]; [5;6;7]; []; [8] ]
= [ [3]; [4]; [8] ].
Proof. reflexivity. Qed.
(** *** *)
(** We can use [filter] to give a concise version of the
[countoddmembers] function from the [Lists] chapter. *)
Definition countoddmembers' (l:list nat) : nat :=
length (filter oddb l).
Example test_countoddmembers'1: countoddmembers' [1;0;3;1;4;5] = 4.
Proof. reflexivity. Qed.
Example test_countoddmembers'2: countoddmembers' [0;2;4] = 0.
Proof. reflexivity. Qed.
Example test_countoddmembers'3: countoddmembers' nil = 0.
Proof. reflexivity. Qed.
(* ###################################################### *)
(** ** Anonymous Functions *)
(** It is a little annoying to be forced to define the function
[length_is_1] and give it a name just to be able to pass it as an
argument to [filter], since we will probably never use it again.
Moreover, this is not an isolated example. When using
higher-order functions, we often want to pass as arguments
"one-off" functions that we will never use again; having to give
each of these functions a name would be tedious.
Fortunately, there is a better way. It is also possible to
construct a function "on the fly" without declaring it at the top
level or giving it a name; this is analogous to the notation we've
been using for writing down constant lists, natural numbers, and
so on. *)
Example test_anon_fun':
doit3times (fun n => n * n) 2 = 256.
Proof. reflexivity. Qed.
(** Here is the motivating example from before, rewritten to use
an anonymous function. *)
Example test_filter2':
filter (fun l => beq_nat (length l) 1)
[ [1; 2]; [3]; [4]; [5;6;7]; []; [8] ]
= [ [3]; [4]; [8] ].
Proof. reflexivity. Qed.
(** **** Exercise: 2 stars (filter_even_gt7) *)
(** Use [filter] (instead of [Fixpoint]) to write a Coq function
[filter_even_gt7] that takes a list of natural numbers as input
and returns a list of just those that are even and greater than
7. *)
Definition filter_even_gt7 (l : list nat) : list nat :=
filter (fun x => andb (evenb x) (blt_nat 7 x)) l.
Example test_filter_even_gt7_1 :
filter_even_gt7 [1;2;6;9;10;3;12;8] = [10;12;8].
Proof. reflexivity. Qed.
Example test_filter_even_gt7_2 :
filter_even_gt7 [5;2;6;19;129] = [].
Proof. reflexivity. Qed.
(** [] *)
(** **** Exercise: 3 stars (partition) *)
(** Use [filter] to write a Coq function [partition]:
partition : forall X : Type,
(X -> bool) -> list X -> list X * list X
Given a set [X], a test function of type [X -> bool] and a [list
X], [partition] should return a pair of lists. The first member of
the pair is the sublist of the original list containing the
elements that satisfy the test, and the second is the sublist
containing those that fail the test. The order of elements in the
two sublists should be the same as their order in the original
list.
*)
Definition partition {X : Type} (test : X -> bool) (l : list X)
: list X * list X :=
(filter (fun x => test x) l, filter (fun x => negb (test x)) l).
Example test_partition1: partition oddb [1;2;3;4;5] = ([1;3;5], [2;4]).
Proof. reflexivity. Qed.
Example test_partition2: partition (fun x => false) [5;9;0] = ([], [5;9;0]).
Proof. reflexivity. Qed.
(** [] *)
(* ###################################################### *)
(** ** Map *)
(** Another handy higher-order function is called [map]. *)
Fixpoint map {X Y:Type} (f:X->Y) (l:list X)
: (list Y) :=
match l with
| [] => []
| h :: t => (f h) :: (map f t)
end.
(** *** *)
(** It takes a function [f] and a list [ l = [n1, n2, n3, ...] ]
and returns the list [ [f n1, f n2, f n3,...] ], where [f] has
been applied to each element of [l] in turn. For example: *)
Example test_map1: map (plus 3) [2;0;2] = [5;3;5].
Proof. reflexivity. Qed.
(** The element types of the input and output lists need not be
the same ([map] takes _two_ type arguments, [X] and [Y]). This
version of [map] can thus be applied to a list of numbers and a
function from numbers to booleans to yield a list of booleans: *)
Example test_map2: map oddb [2;1;2;5] = [false;true;false;true].
Proof. reflexivity. Qed.
(** It can even be applied to a list of numbers and
a function from numbers to _lists_ of booleans to
yield a list of lists of booleans: *)
Example test_map3:
map (fun n => [evenb n;oddb n]) [2;1;2;5]
= [[true;false];[false;true];[true;false];[false;true]].
Proof. reflexivity. Qed.
(** ** Map for options *)
(** **** Exercise: 3 stars (map_rev) *)
(** Show that [map] and [rev] commute. You may need to define an
auxiliary lemma. *)
Theorem map_snoc : forall (X Y : Type) (f : X -> Y) (x : X) (xs : list X),
map f (snoc xs x) = snoc (map f xs) (f x).
Proof.
intros. induction xs as [| y ys].
Case "nil".
reflexivity.
Case "snoc".
simpl. rewrite IHys. reflexivity. Qed.
Theorem map_rev : forall (X Y : Type) (f : X -> Y) (l : list X),
map f (rev l) = rev (map f l).
Proof.
intros. induction l as [| x xs].
Case "nil".
reflexivity.
Case "cons".
simpl. rewrite <- IHxs. rewrite map_snoc. reflexivity. Qed.
(** [] *)
(** **** Exercise: 2 stars (flat_map) *)
(** The function [map] maps a [list X] to a [list Y] using a function
of type [X -> Y]. We can define a similar function, [flat_map],
which maps a [list X] to a [list Y] using a function [f] of type
[X -> list Y]. Your definition should work by 'flattening' the
results of [f], like so:
flat_map (fun n => [n;n+1;n+2]) [1;5;10]
= [1; 2; 3; 5; 6; 7; 10; 11; 12].
*)
Fixpoint flat_map {X Y:Type} (f:X -> list Y) (l:list X)
: (list Y) :=
match l with
| nil => nil
| cons x x0 => f x ++ flat_map f x0
end.
Example test_flat_map1:
flat_map (fun n => [n;n;n]) [1;5;4]
= [1; 1; 1; 5; 5; 5; 4; 4; 4].
Proof. reflexivity. Qed.
(** [] *)
(** Lists are not the only inductive type that we can write a
[map] function for. Here is the definition of [map] for the
[option] type: *)
Definition option_map {X Y : Type} (f : X -> Y) (xo : option X)
: option Y :=
match xo with
| None => None
| Some x => Some (f x)
end.
(** **** Exercise: 2 stars, optional (implicit_args) *)
(** The definitions and uses of [filter] and [map] use implicit
arguments in many places. Replace the curly braces around the
implicit arguments with parentheses, and then fill in explicit
type parameters where necessary and use Coq to check that you've
done so correctly. (This exercise is not to be turned in; it is
probably easiest to do it on a _copy_ of this file that you can
throw away afterwards.) [] *)
(* ###################################################### *)
(** ** Fold *)
(** An even more powerful higher-order function is called
[fold]. This function is the inspiration for the "[reduce]"
operation that lies at the heart of Google's map/reduce
distributed programming framework. *)
Fixpoint fold {X Y:Type} (f: X->Y->Y) (l:list X) (b:Y) : Y :=
match l with
| nil => b
| h :: t => f h (fold f t b)
end.
(** *** *)
(** Intuitively, the behavior of the [fold] operation is to
insert a given binary operator [f] between every pair of elements
in a given list. For example, [ fold plus [1;2;3;4] ] intuitively
means [1+2+3+4]. To make this precise, we also need a "starting
element" that serves as the initial second input to [f]. So, for
example,
fold plus [1;2;3;4] 0
yields
1 + (2 + (3 + (4 + 0))).
Here are some more examples:
*)
Check (fold andb).
(* ===> fold andb : list bool -> bool -> bool *)
Example fold_example1 : fold mult [1;2;3;4] 1 = 24.
Proof. reflexivity. Qed.
Example fold_example2 : fold andb [true;true;false;true] true = false.
Proof. reflexivity. Qed.
Example fold_example3 : fold app [[1];[];[2;3];[4]] [] = [1;2;3;4].
Proof. reflexivity. Qed.
(** **** Exercise: 1 star, advanced (fold_types_different) *)
(** Observe that the type of [fold] is parameterized by _two_ type
variables, [X] and [Y], and the parameter [f] is a binary operator
that takes an [X] and a [Y] and returns a [Y]. Can you think of a
situation where it would be useful for [X] and [Y] to be
different? *)
(* ###################################################### *)
(** ** Functions For Constructing Functions *)
(** Most of the higher-order functions we have talked about so
far take functions as _arguments_. Now let's look at some
examples involving _returning_ functions as the results of other
functions.
To begin, here is a function that takes a value [x] (drawn from
some type [X]) and returns a function from [nat] to [X] that
yields [x] whenever it is called, ignoring its [nat] argument. *)
Definition constfun {X: Type} (x: X) : nat->X :=
fun (k:nat) => x.
Definition ftrue := constfun true.
Example constfun_example1 : ftrue 0 = true.
Proof. reflexivity. Qed.
Example constfun_example2 : (constfun 5) 99 = 5.
Proof. reflexivity. Qed.
(** *** *)
(** Similarly, but a bit more interestingly, here is a function
that takes a function [f] from numbers to some type [X], a number
[k], and a value [x], and constructs a function that behaves
exactly like [f] except that, when called with the argument [k],
it returns [x]. *)
Definition override {X: Type} (f: nat->X) (k:nat) (x:X) : nat->X:=
fun (k':nat) => if beq_nat k k' then x else f k'.
(** For example, we can apply [override] twice to obtain a
function from numbers to booleans that returns [false] on [1] and
[3] and returns [true] on all other arguments. *)
Definition fmostlytrue := override (override ftrue 1 false) 3 false.
(** *** *)
Example override_example1 : fmostlytrue 0 = true.
Proof. reflexivity. Qed.
Example override_example2 : fmostlytrue 1 = false.
Proof. reflexivity. Qed.
Example override_example3 : fmostlytrue 2 = true.
Proof. reflexivity. Qed.
Example override_example4 : fmostlytrue 3 = false.
Proof. reflexivity. Qed.
(** *** *)
(** **** Exercise: 1 star (override_example) *)
(** Before starting to work on the following proof, make sure you
understand exactly what the theorem is saying and can paraphrase
it in your own words. The proof itself is straightforward. *)
Theorem override_example : forall (b:bool),
(override (constfun b) 3 true) 2 = b.
Proof.
intros. compute. reflexivity. Qed.
(** [] *)
(** We'll use function overriding heavily in parts of the rest of the
course, and we will end up needing to know quite a bit about its
properties. To prove these properties, though, we need to know
about a few more of Coq's tactics; developing these is the main
topic of the next chapter. For now, though, let's introduce just
one very useful tactic that will also help us with proving
properties of some of the other functions we have introduced in
this chapter. *)
(* ###################################################### *)
(* ###################################################### *)
(** * The [unfold] Tactic *)
(** Sometimes, a proof will get stuck because Coq doesn't
automatically expand a function call into its definition. (This
is a feature, not a bug: if Coq automatically expanded everything
possible, our proof goals would quickly become enormous -- hard to
read and slow for Coq to manipulate!) *)
Theorem unfold_example_bad : forall m n,
3 + n = m ->
plus3 n + 1 = m + 1.
Proof.
intros m n H.
(* At this point, we'd like to do [rewrite -> H], since
[plus3 n] is definitionally equal to [3 + n]. However,
Coq doesn't automatically expand [plus3 n] to its
definition. *)
Abort.
(** The [unfold] tactic can be used to explicitly replace a
defined name by the right-hand side of its definition. *)
Theorem unfold_example : forall m n,
3 + n = m ->
plus3 n + 1 = m + 1.
Proof.
intros m n H.
unfold plus3.
rewrite -> H.
reflexivity. Qed.
(** Now we can prove a first property of [override]: If we
override a function at some argument [k] and then look up [k], we
get back the overridden value. *)
Theorem override_eq : forall {X:Type} x k (f:nat->X),
(override f k x) k = x.
Proof.
intros X x k f.
unfold override.
rewrite <- beq_nat_refl.
reflexivity. Qed.
(** This proof was straightforward, but note that it requires
[unfold] to expand the definition of [override]. *)
(** **** Exercise: 2 stars (override_neq) *)
Theorem override_neq : forall (X:Type) x1 x2 k1 k2 (f : nat->X),
f k1 = x1 ->
beq_nat k2 k1 = false ->
(override f k2 x2) k1 = x1.
Proof.
intros. unfold override. rewrite H0. rewrite H. reflexivity. Qed.
(** [] *)
(** As the inverse of [unfold], Coq also provides a tactic
[fold], which can be used to "unexpand" a definition. It is used
much less often. *)
(* ##################################################### *)
(** * Additional Exercises *)
(** **** Exercise: 2 stars (fold_length) *)
(** Many common functions on lists can be implemented in terms of
[fold]. For example, here is an alternative definition of [length]: *)
Definition fold_length {X : Type} (l : list X) : nat :=
fold (fun _ n => S n) l 0.
Example test_fold_length1 : fold_length [4;7;0] = 3.
Proof. reflexivity. Qed.
(** Prove the correctness of [fold_length]. *)
Theorem fold_length_correct : forall X (l : list X),
fold_length l = length l.
Proof.
intros. induction l as [| x xs].
Case "nil".
reflexivity.
Case "cons".
simpl. rewrite <- IHxs. reflexivity. Qed.
(** [] *)
(** **** Exercise: 3 stars (fold_map) *)
(** We can also define [map] in terms of [fold]. Finish [fold_map]
below. *)
Definition fold_map {X Y:Type} (f : X -> Y) (l : list X) : list Y :=
fold (fun x r => f x :: r) l [].
(** Write down a theorem in Coq stating that [fold_map] is correct,
and prove it. *)
Theorem fold_map_correct : forall {X Y:Type} (f : X -> Y) (l : list X),
map f l = fold_map f l.
Proof.
intros. induction l as [| x xs].
Case "nil".
reflexivity.
Case "cons".
simpl. rewrite IHxs. reflexivity. Qed.
(** [] *)
(* $Date: 2013-09-26 14:40:26 -0400 (Thu, 26 Sep 2013) $ *)
Definition id {X} (a : X) : X := a.
Definition compose {A B C}
(f : B -> C) (g : A -> B) (x : A) : C := f (g x).
Notation "f ∘ g" := (compose f g) (at level 60, right associativity).
Theorem comp_left_identity : forall {X Y} (f : X -> Y),
id ∘ f = f.
Proof.
intros. reflexivity. Qed.
Theorem comp_right_identity : forall {X Y} (f : X -> Y),
f ∘ id = f.
Proof.
intros. reflexivity. Qed.
Class Functor (F : Type -> Type) := {
fmap : forall {X Y}, (X -> Y) -> F X -> F Y;
functor_law_1 : forall {X} (x : F X), fmap (@id X) x = @id (F X) x;
functor_law_2 : forall {X Y Z} (x : F X) (f : Y -> Z) (g : X -> Y),
(fmap f ∘ fmap g) x = fmap (f ∘ g) x
}.
Global Instance List_Functor : Functor list := {
fmap := @map
}.
Proof.
(* functor_law_1 *)
intros. induction x as [| x'].
Case "x = nil". reflexivity.
Case "x = cons". simpl. rewrite IHx. reflexivity.
(* functor_law_2 *)
intros. induction x as [| x'].
Case "x = nil". reflexivity.
Case "x = cons".
unfold compose. unfold compose in IHx.
simpl. rewrite IHx. reflexivity. Qed.
Inductive Yoneda (F : Type -> Type) X : Type :=
| Embed : forall {Y}, F Y -> (Y -> X) -> Yoneda F X.
Definition lift_yoneda (F : Type -> Type) X (a : F X)
: Yoneda F X := Embed F X a id.
Definition lower_yoneda (F : Type -> Type) (f_dict : Functor F)
X (a : Yoneda F X) : F X :=
match a with | Embed F x f => fmap f x end.
Theorem eq_remove_Embed : forall (F : Type -> Type) X Y (f : Y -> X) (n m : F Y),
n = m -> Embed F X n f = Embed F X m f.
Proof.
intros. inversion H. reflexivity. Qed.
Definition yoneda_map {F : Type -> Type} {X Y}
(f : X -> Y) (x : Yoneda F X) : Yoneda F Y :=
match x with
| Embed X y g => Embed F Y y (f ∘ g)
end.
Global Instance Yoneda_Functor (F : Type -> Type) : Functor (Yoneda F) := {
fmap := @yoneda_map F
}.
Proof.
(* functor_law_1 *)
intros. unfold yoneda_map. destruct x.
rewrite comp_left_identity. reflexivity.
(* functor_law_2 *)
intros. compute. destruct x. reflexivity. Qed.
Class Isomorphism X Y := {
to : X -> Y; from : Y -> X;
iso_to : forall (x : X), from (to x) = x;
iso_from : forall (y : Y), to (from y) = y
}.
Notation "X ≅ Y" := (Isomorphism X Y) (at level 50) : type_scope.
Hypothesis yoneda_refl : forall (F : Type -> Type) (f_dict : Functor F)
X Y (f : Y -> X) (x : F Y),
Embed F X (fmap f x) id = Embed F X x f.
Global Instance Yoneda_Lemma (F : Type -> Type) (f_dict : Functor F) X
: F X ≅ Yoneda F X := {
to := lift_yoneda F X;
from := lower_yoneda F f_dict X
}.
Proof.
intros. compute. apply functor_law_1.
intros. unfold lower_yoneda. destruct y. unfold lift_yoneda.
apply yoneda_refl. Qed.
Inductive Source (M : Type -> Type) X : Type :=
| ASource : (forall {R}, R -> (R -> X -> M R) -> M R) -> Source M X.
Definition source_map {M : Type -> Type} {X Y}
(f : X -> Y) (x : Source M X) : Source M Y :=
match x with
| ASource await =>
ASource M Y (fun R z yield => await R z (fun r y => yield r (f y)))
end.
Global Instance Source_Functor (M : Type -> Type) (X : Type)
: Functor (Source M) := {
fmap := @source_map M
}.
Proof.
intros. compute. destruct x. reflexivity.
intros. compute. destruct x. reflexivity. Qed.
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Virtex-6 Integrated Block for PCI Express
// File : trn_tx_128.v
// Version : 1.7
`timescale 1ps/1ps
// TRNTCFGREQN asserts to when user is throttled. # pipeline stages needed
// to buffer data so single cycle tlps do not overflow transmitter
//-time it takes from detecting indicated TRNTBUFAV limit to when
// trn_tdst_rdy_n_o
// deasserts for the user is 2 4ns cycles
//-2 4ns cycles = 4 2ns cycles, which is how many cycles of data are in flight
//-TRNTDSTRDYN deasserts when TRNBUFAV reaches 1
//-we cannot have TRNTBUFAV reach 1 before trn_tdst_rdy_n_o deasserts, so the
// TRNTBUFAV value limit should be 5
`define TBUF_LIMIT 5
`define TBUF_LIMIT_REG 6
`define FIFO_DLY 1
module trn_tx_128 #(
parameter TCQ = 100
) (
input user_clk, // 125mhz div2
input block_clk, // 250 to Block
input rst_n_250,
input rst_n_500,
input [1:0] cfgpmcsrpowerstate,
output [5:0] trn_tbuf_av_o,
output trn_tdst_rdy_n_o,
output trn_terr_drop_n_o,
input trn_tecrc_gen_n_i,
input [127:0] trn_td_i,
input trn_terr_fwd_n_i,
input [1:0] trn_trem_n_i,
input trn_tsof_n_i,
input trn_teof_n_i,
input trn_tsrc_dsc_n_i,
input trn_tsrc_rdy_n_i,
input trn_tstr_n_i,
input [5:0] TRNTBUFAV_i,
input TRNTCFGREQN_i,
input TRNTDSTRDYN_i,
input TRNTERRDROPN_i,
output TRNTCFGGNTN_o,
output [63:0] TRNTD_o,
output TRNTECRCGENN_o,
output TRNTERRFWDN_o,
output TRNTREMN_o,
output TRNTSOFN_o,
output TRNTEOFN_o,
output TRNTSRCDSCN_o,
output TRNTSRCRDYN_o,
output TRNTSTRN_o
);
parameter [1:0] USER_TLP = 0;
parameter [1:0] INT_TLP = 1;
wire [63:0] trn_td_i_spry_new;
wire trn_tecrc_gen_n_i_spry_new;
wire trn_terr_fwd_n_i_spry_new;
wire trn_trem_n_i_spry_new;
wire trn_tsof_n_i_spry_new;
wire trn_teof_n_i_spry_new;
wire trn_tsrc_dsc_n_i_spry_new;
wire trn_tsrc_rdy_n_i_spry_new;
wire trn_tstr_n_i_spry_new;
wire TRNTCFGGNTN_o_srl;
wire [63:0] trn_td_i_srl;
wire trn_tecrc_gen_n_i_srl;
wire trn_terr_fwd_n_i_srl;
wire trn_trem_n_i_srl;
wire trn_tsof_n_i_srl;
wire trn_teof_n_i_srl;
wire trn_tsrc_dsc_n_i_srl;
wire trn_tsrc_rdy_n_i_srl;
wire trn_tstr_n_i_srl;
wire TRNTERRDROPN_i_250;
reg [1:0] reg_state;
wire [1:0] state;
wire conditions_met;
reg conditions_met_reg;
reg conditions_met_reg_d;
wire [(64+9-1):0] srl_input;
wire [(64+9-1):0] srl_output;
reg in_a_pkt;
reg in_a_pkt_500;
wire in_a_pkt_wire_250;
wire in_a_pkt_wire_500;
reg in_a_multi_pkt;
reg in_a_multi_pkt_reg_500;
reg in_a_multi_pkt_reg_500_d;
reg in_a_multi_pkt_reg_250;
reg one_cycle_pkt;
reg toggle;
reg toggle_500;
reg [127:0] trn_td_i_reg;
reg trn_tsof_n_i_reg;
reg trn_teof_n_i_reg;
reg trn_tsrc_dsc_n_i_reg;
reg trn_tsrc_rdy_n_i_reg;
reg [1:0] trn_trem_n_i_reg;
reg trn_tstr_n_i_reg;
reg trn_tecrc_gen_n_i_reg = 1;
reg trn_terr_fwd_n_i_reg;
reg [127:0] trn_td_i_reg_500;
reg trn_tsof_n_i_reg_500;
reg trn_teof_n_i_reg_500;
reg trn_tsrc_dsc_n_i_reg_500;
reg trn_tsrc_rdy_n_i_reg_500;
reg [1:0] trn_trem_n_i_reg_500;
reg trn_tstr_n_i_reg_500;
reg trn_tecrc_gen_n_i_reg_500;
reg trn_terr_fwd_n_i_reg_500;
reg trn_tdst_rdy_n_int_reg_500;
reg TRNTCFGGNTN_int;
reg trn_tdst_rdy_n_int;
reg trn_tdst_rdy_n_int_reg;
reg TRNTCFGGNTN_o_reg;
reg TRNTCFGGNTN_o_reg_d;
reg [5:0] TRNTBUFAV_i_reg;
reg TRNTCFGREQN_i_reg;
reg TRNTDSTRDYN_i_reg;
reg TRNTERRDROPN_i_reg;
reg TRNTERRDROPN_i_reg_d;
reg GNT_set;
integer i;
reg [(64+9-1):0] shift [(`FIFO_DLY-1):0]; // pipeline `FIFO_DLY-1
assign TRNTCFGGNTN_o = TRNTCFGGNTN_o_srl;
assign TRNTECRCGENN_o = trn_tecrc_gen_n_i_srl;
assign TRNTERRFWDN_o = trn_terr_fwd_n_i_srl;
assign TRNTD_o = trn_td_i_srl;
assign TRNTSOFN_o = trn_tsof_n_i_srl;
assign TRNTEOFN_o = trn_teof_n_i_srl;
assign TRNTSRCDSCN_o = trn_tsrc_dsc_n_i_srl | trn_teof_n_i_srl;
assign TRNTSRCRDYN_o = trn_tsrc_rdy_n_i_srl;
assign TRNTREMN_o = trn_trem_n_i_srl;
assign TRNTSTRN_o = trn_tstr_n_i_srl;
assign trn_tbuf_av_o = TRNTBUFAV_i_reg;
assign TRNTERRDROPN_i_250 = TRNTERRDROPN_i_reg & TRNTERRDROPN_i;
assign trn_terr_drop_n_o = TRNTERRDROPN_i_reg_d;
//------------------------------------------------------------------
// register mostly inputs @ 250
//------------------------------------------------------------------
always @(posedge user_clk)
begin
if (~rst_n_250)
begin
trn_td_i_reg <= #TCQ 128'b0;
trn_tsof_n_i_reg <= #TCQ 1'b1;
trn_teof_n_i_reg <= #TCQ 1'b1;
trn_tsrc_dsc_n_i_reg <= #TCQ 1'b1;
trn_tsrc_rdy_n_i_reg <= #TCQ 1'b1;
trn_trem_n_i_reg <= #TCQ 2'h3;
trn_tstr_n_i_reg <= #TCQ 1'b1;
trn_tecrc_gen_n_i_reg <= #TCQ 1'b1;
trn_terr_fwd_n_i_reg <= #TCQ 1'b1;
TRNTBUFAV_i_reg <= #TCQ 6'b0; // convert 500-250
TRNTCFGREQN_i_reg <= #TCQ 1'b1; // convert 500-250
TRNTDSTRDYN_i_reg <= #TCQ 1'b1; // convert 500-250
in_a_multi_pkt_reg_250 <= #TCQ 0;
trn_tdst_rdy_n_int_reg <= #TCQ 1;
TRNTERRDROPN_i_reg_d <= #TCQ 1;
end else begin
if (~trn_tdst_rdy_n_o)
begin
trn_tsof_n_i_reg <= #TCQ trn_tsof_n_i;
trn_teof_n_i_reg <= #TCQ trn_teof_n_i;
trn_tsrc_rdy_n_i_reg <= #TCQ trn_tsrc_rdy_n_i;
end else begin
trn_tsof_n_i_reg <= #TCQ 1'b1;
trn_teof_n_i_reg <= #TCQ 1'b1;
trn_tsrc_rdy_n_i_reg <= #TCQ 1'b1;
end
trn_td_i_reg <= #TCQ trn_td_i;
trn_trem_n_i_reg <= #TCQ trn_trem_n_i;
trn_tstr_n_i_reg <= #TCQ trn_tstr_n_i;
trn_tecrc_gen_n_i_reg <= #TCQ trn_tecrc_gen_n_i;
trn_terr_fwd_n_i_reg <= #TCQ trn_terr_fwd_n_i;
trn_tsrc_dsc_n_i_reg <= #TCQ trn_tsrc_dsc_n_i;
TRNTBUFAV_i_reg <= #TCQ TRNTBUFAV_i;
TRNTCFGREQN_i_reg <= #TCQ TRNTCFGREQN_i;
TRNTDSTRDYN_i_reg <= #TCQ TRNTDSTRDYN_i;
in_a_multi_pkt_reg_250 <= #TCQ in_a_multi_pkt;
trn_tdst_rdy_n_int_reg <= #TCQ trn_tdst_rdy_n_int;
TRNTERRDROPN_i_reg_d <= #TCQ TRNTERRDROPN_i_250;
end
end
//------------------------------------------------------------------
// register signals to SRL @ 500
//------------------------------------------------------------------
always @(posedge block_clk)
begin
if(~rst_n_500)
begin
trn_td_i_reg_500 <= #TCQ 128'b0;
trn_tsof_n_i_reg_500 <= #TCQ 1'b1;
trn_teof_n_i_reg_500 <= #TCQ 1'b1;
trn_tsrc_dsc_n_i_reg_500 <= #TCQ 1'b1;
trn_tsrc_rdy_n_i_reg_500 <= #TCQ 1'b1;
trn_trem_n_i_reg_500 <= #TCQ 1'b1;
trn_tstr_n_i_reg_500 <= #TCQ 1'b1;
trn_tecrc_gen_n_i_reg_500 <= #TCQ 1'b1;
trn_terr_fwd_n_i_reg_500 <= #TCQ 1'b1;
trn_tdst_rdy_n_int_reg_500 <= #TCQ 1'b1;
in_a_multi_pkt_reg_500 <= #TCQ 1'b0;
in_a_multi_pkt_reg_500_d <= #TCQ 1'b0;
TRNTCFGGNTN_o_reg <= #TCQ 1'b1; // convert 250-500
TRNTCFGGNTN_o_reg_d <= #TCQ 1'b1; // convert 250-500
TRNTERRDROPN_i_reg <= #TCQ 1'b1;
in_a_pkt_500 <= #TCQ 1'b0;
end else begin
trn_td_i_reg_500 <= #TCQ trn_td_i_reg;
trn_tsof_n_i_reg_500 <= #TCQ trn_tsof_n_i_reg;
trn_teof_n_i_reg_500 <= #TCQ trn_teof_n_i_reg;
trn_tsrc_dsc_n_i_reg_500 <= #TCQ trn_tsrc_dsc_n_i_reg;
trn_tsrc_rdy_n_i_reg_500 <= #TCQ trn_tsrc_rdy_n_i_reg;
trn_trem_n_i_reg_500 <= #TCQ trn_trem_n_i_reg;
trn_tstr_n_i_reg_500 <= #TCQ trn_tstr_n_i_reg;
trn_tecrc_gen_n_i_reg_500 <= #TCQ trn_tecrc_gen_n_i_reg;
trn_terr_fwd_n_i_reg_500 <= #TCQ trn_terr_fwd_n_i_reg;
trn_tdst_rdy_n_int_reg_500 <= #TCQ trn_tdst_rdy_n_int_reg;
in_a_multi_pkt_reg_500 <= #TCQ in_a_multi_pkt;
in_a_multi_pkt_reg_500_d <= #TCQ in_a_multi_pkt_reg_500;
TRNTCFGGNTN_o_reg <= #TCQ TRNTCFGGNTN_int;
TRNTCFGGNTN_o_reg_d <= #TCQ TRNTCFGGNTN_o_reg;
TRNTERRDROPN_i_reg <= #TCQ TRNTERRDROPN_i;
in_a_pkt_500 <= #TCQ in_a_pkt_wire_500;
end
end
assign #TCQ conditions_met = ((TRNTBUFAV_i_reg > `TBUF_LIMIT) & // 250
TRNTCFGREQN_i_reg & ~TRNTDSTRDYN_i_reg & // 250 250
(cfgpmcsrpowerstate == 2'd0) ); // 250
always @(posedge user_clk)
begin
if (~rst_n_250) begin
conditions_met_reg <= #TCQ 1'b0;
conditions_met_reg_d <= #TCQ 1'b0;
end else begin
conditions_met_reg <= #TCQ (TRNTBUFAV_i > `TBUF_LIMIT_REG); // 250
conditions_met_reg_d <= ((conditions_met_reg) &
TRNTCFGREQN_i & ~TRNTDSTRDYN_i & // 250 250
(cfgpmcsrpowerstate == 2'd0) ); // 250
end
end
//------------------------------------------------------------------
// 250
//------------------------------------------------------------------
always @(posedge user_clk)
begin
if (~rst_n_250) begin
one_cycle_pkt <= #TCQ 0;
in_a_multi_pkt <= #TCQ 0;
in_a_pkt <= #TCQ 0;
end else begin
if ( ~trn_tsof_n_i & ~trn_tsrc_rdy_n_i & ~trn_tdst_rdy_n_o)
begin
if (~trn_teof_n_i)
begin
one_cycle_pkt <= #TCQ 1;
in_a_multi_pkt <= #TCQ 0;
end else begin
one_cycle_pkt <= #TCQ 0;
in_a_multi_pkt <= #TCQ 1;
end
in_a_pkt <= #TCQ 1;
end else if (~trn_teof_n_i & ~trn_tsrc_rdy_n_i & ~trn_tdst_rdy_n_o)
begin
one_cycle_pkt <= #TCQ 0;
in_a_multi_pkt <= #TCQ 0;
in_a_pkt <= #TCQ 0;
end
else if (one_cycle_pkt)
begin
one_cycle_pkt <= #TCQ 0;
in_a_pkt <= #TCQ 0;
end
end
end
assign in_a_pkt_wire_250 = in_a_pkt | in_a_multi_pkt_reg_250 |
~trn_tsof_n_i & ~trn_tsrc_rdy_n_i & ~trn_tdst_rdy_n_int;
assign in_a_pkt_wire_500 = in_a_pkt |
(trn_trem_n_i_reg[1] ? in_a_multi_pkt_reg_500 : in_a_multi_pkt_reg_500_d);
//---------------------------------------------------------------------
// FSM to throttle user for TRNTCFGREQN and assert TRNTCFGGNTN
//---------------------------------------------------------------------
always @(posedge user_clk)
begin
if (~rst_n_250)
begin
reg_state = 0;
end else begin
case (state)
USER_TLP: begin // 0
if (in_a_pkt_wire_250) begin
if (!TRNTCFGREQN_i_reg && !trn_teof_n_i && !trn_tsrc_rdy_n_i)
reg_state = INT_TLP;
else if (!conditions_met && !trn_teof_n_i && !trn_tsrc_rdy_n_i)
reg_state = USER_TLP;
else
reg_state = USER_TLP;
end else begin
if (!TRNTCFGREQN_i_reg)
reg_state = INT_TLP;
else
reg_state = USER_TLP;
end
end
INT_TLP: begin // 1
if (TRNTCFGREQN_i_reg)
reg_state = USER_TLP;
else
reg_state = INT_TLP;
end
endcase
end
end
//---------------------------------------------------------------------
// output(tdst_rdy) logic
//---------------------------------------------------------------------
always @(posedge user_clk)
begin
if (~rst_n_250) begin
TRNTCFGGNTN_int <= #TCQ 1;
trn_tdst_rdy_n_int <= #TCQ 1;
end else begin
case (state)
USER_TLP: begin // 0
TRNTCFGGNTN_int <= #TCQ 1;
GNT_set <= #TCQ 0;
if (in_a_pkt_wire_250) begin
if (!TRNTCFGREQN_i_reg && !trn_teof_n_i && !trn_tsrc_rdy_n_i)
trn_tdst_rdy_n_int <= #TCQ 1;
else if ((!conditions_met && !trn_teof_n_i && !trn_tsrc_rdy_n_i) ||
(!conditions_met && trn_tdst_rdy_n_int))
trn_tdst_rdy_n_int <= #TCQ 1;
else
trn_tdst_rdy_n_int <= #TCQ 0;
end else begin
if (!TRNTCFGREQN_i_reg)
trn_tdst_rdy_n_int <= #TCQ 1;
else if (!conditions_met)
trn_tdst_rdy_n_int <= #TCQ 1;
else
trn_tdst_rdy_n_int <= #TCQ 0;
end
end
INT_TLP: begin // 1
if (~GNT_set) begin
TRNTCFGGNTN_int <= #TCQ 0;
GNT_set <= #TCQ 1;
end else begin
TRNTCFGGNTN_int <= #TCQ 1;
end
trn_tdst_rdy_n_int <= #TCQ 1;
end
endcase
end
end
assign #TCQ state = reg_state;
// this is so trn_tdst_rdy_n_o does not deasserts in middle of a packet
assign trn_tdst_rdy_n_o = trn_tdst_rdy_n_int |
(~conditions_met_reg_d & ~in_a_pkt_wire_250);
//----------------------------------------------------------------------
// Sprayer @ 500
//----------------------------------------------------------------------
always @(posedge block_clk)
begin
if (~rst_n_500)
begin
toggle <= #TCQ 1;
toggle_500 <= #TCQ 1;
end else begin
if (in_a_pkt_wire_500)
toggle <= #TCQ ~toggle;
else
toggle <= #TCQ 1;
toggle_500 <= #TCQ toggle;
end
end
assign trn_td_i_spry_new = toggle_500 ? trn_td_i_reg_500[127:64] : trn_td_i_reg_500[63:0];
assign trn_tsof_n_i_spry_new = toggle_500 ? trn_tsof_n_i_reg_500 : 1'b1;
// toggle upper upper lower lower
// remn[1] upper lower upper lower
// remn[0] upper lower upper lower
// eof 1 1 eof
assign trn_teof_n_i_spry_new = (toggle_500 ^~ trn_trem_n_i_reg_500[1]) ? trn_teof_n_i_reg_500 : 1'b1;
assign trn_tsrc_rdy_n_i_spry_new = ~in_a_pkt_500 | trn_tdst_rdy_n_int_reg_500 |
trn_tsrc_rdy_n_i_reg_500;
assign trn_tsrc_dsc_n_i_spry_new = trn_tsrc_dsc_n_i_reg_500;
assign trn_trem_n_i_spry_new = trn_trem_n_i_reg_500[0];
assign trn_tstr_n_i_spry_new = trn_tstr_n_i_reg_500;
assign trn_tecrc_gen_n_i_spry_new = trn_tecrc_gen_n_i_reg_500;
assign trn_terr_fwd_n_i_spry_new = trn_terr_fwd_n_i_reg_500;
assign #TCQ srl_input = {
TRNTCFGGNTN_o_reg_d, trn_td_i_spry_new,
trn_tsof_n_i_spry_new, trn_teof_n_i_spry_new,
trn_tsrc_dsc_n_i_spry_new, trn_tsrc_rdy_n_i_spry_new,
trn_trem_n_i_spry_new, trn_tstr_n_i_spry_new,
trn_tecrc_gen_n_i_spry_new, trn_terr_fwd_n_i_spry_new};
//----------------------------------------------------------------------
// SRL Pipeline
generate
always @(posedge block_clk)
begin
for (i=(`FIFO_DLY-1); i>0; i=i-1)
shift[i] <= #TCQ shift[i-1];
shift[0] <= #TCQ srl_input;
end
endgenerate
assign srl_output = shift[(`FIFO_DLY-1)]; // `FIFO_DLY-1
assign TRNTCFGGNTN_o_srl = TRNTCFGGNTN_o_reg_d;
assign trn_td_i_srl = srl_output[71:8];
assign trn_tsof_n_i_srl = srl_output[7];
assign trn_teof_n_i_srl = srl_output[6];
assign trn_tsrc_dsc_n_i_srl = srl_output[5];
assign trn_tsrc_rdy_n_i_srl = srl_output[4];
assign trn_trem_n_i_srl = srl_output[3];
assign trn_tstr_n_i_srl = srl_output[2];
assign trn_tecrc_gen_n_i_srl = srl_output[1];
assign trn_terr_fwd_n_i_srl = srl_output[0];
endmodule
|
// (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:processing_system7_bfm:2.0
// IP Revision: 1
`timescale 1ns/1ps
module system_processing_system7_0_0 (
M_AXI_GP0_ARVALID,
M_AXI_GP0_AWVALID,
M_AXI_GP0_BREADY,
M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST,
M_AXI_GP0_WVALID,
M_AXI_GP0_ARID,
M_AXI_GP0_AWID,
M_AXI_GP0_WID,
M_AXI_GP0_ARBURST,
M_AXI_GP0_ARLOCK,
M_AXI_GP0_ARSIZE,
M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK,
M_AXI_GP0_AWSIZE,
M_AXI_GP0_ARPROT,
M_AXI_GP0_AWPROT,
M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR,
M_AXI_GP0_WDATA,
M_AXI_GP0_ARCACHE,
M_AXI_GP0_ARLEN,
M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE,
M_AXI_GP0_AWLEN,
M_AXI_GP0_AWQOS,
M_AXI_GP0_WSTRB,
M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY,
M_AXI_GP0_AWREADY,
M_AXI_GP0_BVALID,
M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID,
M_AXI_GP0_WREADY,
M_AXI_GP0_BID,
M_AXI_GP0_RID,
M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP,
M_AXI_GP0_RDATA,
FCLK_CLK0,
FCLK_RESET0_N,
MIO,
DDR_CAS_n,
DDR_CKE,
DDR_Clk_n,
DDR_Clk,
DDR_CS_n,
DDR_DRSTB,
DDR_ODT,
DDR_RAS_n,
DDR_WEB,
DDR_BankAddr,
DDR_Addr,
DDR_VRN,
DDR_VRP,
DDR_DM,
DDR_DQ,
DDR_DQS_n,
DDR_DQS,
PS_SRSTB,
PS_CLK,
PS_PORB
);
output M_AXI_GP0_ARVALID;
output M_AXI_GP0_AWVALID;
output M_AXI_GP0_BREADY;
output M_AXI_GP0_RREADY;
output M_AXI_GP0_WLAST;
output M_AXI_GP0_WVALID;
output [11 : 0] M_AXI_GP0_ARID;
output [11 : 0] M_AXI_GP0_AWID;
output [11 : 0] M_AXI_GP0_WID;
output [1 : 0] M_AXI_GP0_ARBURST;
output [1 : 0] M_AXI_GP0_ARLOCK;
output [2 : 0] M_AXI_GP0_ARSIZE;
output [1 : 0] M_AXI_GP0_AWBURST;
output [1 : 0] M_AXI_GP0_AWLOCK;
output [2 : 0] M_AXI_GP0_AWSIZE;
output [2 : 0] M_AXI_GP0_ARPROT;
output [2 : 0] M_AXI_GP0_AWPROT;
output [31 : 0] M_AXI_GP0_ARADDR;
output [31 : 0] M_AXI_GP0_AWADDR;
output [31 : 0] M_AXI_GP0_WDATA;
output [3 : 0] M_AXI_GP0_ARCACHE;
output [3 : 0] M_AXI_GP0_ARLEN;
output [3 : 0] M_AXI_GP0_ARQOS;
output [3 : 0] M_AXI_GP0_AWCACHE;
output [3 : 0] M_AXI_GP0_AWLEN;
output [3 : 0] M_AXI_GP0_AWQOS;
output [3 : 0] M_AXI_GP0_WSTRB;
input M_AXI_GP0_ACLK;
input M_AXI_GP0_ARREADY;
input M_AXI_GP0_AWREADY;
input M_AXI_GP0_BVALID;
input M_AXI_GP0_RLAST;
input M_AXI_GP0_RVALID;
input M_AXI_GP0_WREADY;
input [11 : 0] M_AXI_GP0_BID;
input [11 : 0] M_AXI_GP0_RID;
input [1 : 0] M_AXI_GP0_BRESP;
input [1 : 0] M_AXI_GP0_RRESP;
input [31 : 0] M_AXI_GP0_RDATA;
output FCLK_CLK0;
output FCLK_RESET0_N;
input [53 : 0] MIO;
input DDR_CAS_n;
input DDR_CKE;
input DDR_Clk_n;
input DDR_Clk;
input DDR_CS_n;
input DDR_DRSTB;
input DDR_ODT;
input DDR_RAS_n;
input DDR_WEB;
input [2 : 0] DDR_BankAddr;
input [14 : 0] DDR_Addr;
input DDR_VRN;
input DDR_VRP;
input [3 : 0] DDR_DM;
input [31 : 0] DDR_DQ;
input [3 : 0] DDR_DQS_n;
input [3 : 0] DDR_DQS;
input PS_SRSTB;
input PS_CLK;
input PS_PORB;
processing_system7_bfm_v2_0_processing_system7_bfm #(
.C_USE_M_AXI_GP0(1),
.C_USE_M_AXI_GP1(0),
.C_USE_S_AXI_ACP(0),
.C_USE_S_AXI_GP0(0),
.C_USE_S_AXI_GP1(0),
.C_USE_S_AXI_HP0(0),
.C_USE_S_AXI_HP1(0),
.C_USE_S_AXI_HP2(0),
.C_USE_S_AXI_HP3(0),
.C_S_AXI_HP0_DATA_WIDTH(64),
.C_S_AXI_HP1_DATA_WIDTH(64),
.C_S_AXI_HP2_DATA_WIDTH(64),
.C_S_AXI_HP3_DATA_WIDTH(64),
.C_HIGH_OCM_EN(0),
.C_FCLK_CLK0_FREQ(100.0),
.C_FCLK_CLK1_FREQ(150.0),
.C_FCLK_CLK2_FREQ(50.0),
.C_FCLK_CLK3_FREQ(50.0),
.C_M_AXI_GP0_ENABLE_STATIC_REMAP(0),
.C_M_AXI_GP1_ENABLE_STATIC_REMAP(0),
.C_M_AXI_GP0_THREAD_ID_WIDTH (12),
.C_M_AXI_GP1_THREAD_ID_WIDTH (12)
) inst (
.M_AXI_GP0_ARVALID(M_AXI_GP0_ARVALID),
.M_AXI_GP0_AWVALID(M_AXI_GP0_AWVALID),
.M_AXI_GP0_BREADY(M_AXI_GP0_BREADY),
.M_AXI_GP0_RREADY(M_AXI_GP0_RREADY),
.M_AXI_GP0_WLAST(M_AXI_GP0_WLAST),
.M_AXI_GP0_WVALID(M_AXI_GP0_WVALID),
.M_AXI_GP0_ARID(M_AXI_GP0_ARID),
.M_AXI_GP0_AWID(M_AXI_GP0_AWID),
.M_AXI_GP0_WID(M_AXI_GP0_WID),
.M_AXI_GP0_ARBURST(M_AXI_GP0_ARBURST),
.M_AXI_GP0_ARLOCK(M_AXI_GP0_ARLOCK),
.M_AXI_GP0_ARSIZE(M_AXI_GP0_ARSIZE),
.M_AXI_GP0_AWBURST(M_AXI_GP0_AWBURST),
.M_AXI_GP0_AWLOCK(M_AXI_GP0_AWLOCK),
.M_AXI_GP0_AWSIZE(M_AXI_GP0_AWSIZE),
.M_AXI_GP0_ARPROT(M_AXI_GP0_ARPROT),
.M_AXI_GP0_AWPROT(M_AXI_GP0_AWPROT),
.M_AXI_GP0_ARADDR(M_AXI_GP0_ARADDR),
.M_AXI_GP0_AWADDR(M_AXI_GP0_AWADDR),
.M_AXI_GP0_WDATA(M_AXI_GP0_WDATA),
.M_AXI_GP0_ARCACHE(M_AXI_GP0_ARCACHE),
.M_AXI_GP0_ARLEN(M_AXI_GP0_ARLEN),
.M_AXI_GP0_ARQOS(M_AXI_GP0_ARQOS),
.M_AXI_GP0_AWCACHE(M_AXI_GP0_AWCACHE),
.M_AXI_GP0_AWLEN(M_AXI_GP0_AWLEN),
.M_AXI_GP0_AWQOS(M_AXI_GP0_AWQOS),
.M_AXI_GP0_WSTRB(M_AXI_GP0_WSTRB),
.M_AXI_GP0_ACLK(M_AXI_GP0_ACLK),
.M_AXI_GP0_ARREADY(M_AXI_GP0_ARREADY),
.M_AXI_GP0_AWREADY(M_AXI_GP0_AWREADY),
.M_AXI_GP0_BVALID(M_AXI_GP0_BVALID),
.M_AXI_GP0_RLAST(M_AXI_GP0_RLAST),
.M_AXI_GP0_RVALID(M_AXI_GP0_RVALID),
.M_AXI_GP0_WREADY(M_AXI_GP0_WREADY),
.M_AXI_GP0_BID(M_AXI_GP0_BID),
.M_AXI_GP0_RID(M_AXI_GP0_RID),
.M_AXI_GP0_BRESP(M_AXI_GP0_BRESP),
.M_AXI_GP0_RRESP(M_AXI_GP0_RRESP),
.M_AXI_GP0_RDATA(M_AXI_GP0_RDATA),
.M_AXI_GP1_ARVALID(),
.M_AXI_GP1_AWVALID(),
.M_AXI_GP1_BREADY(),
.M_AXI_GP1_RREADY(),
.M_AXI_GP1_WLAST(),
.M_AXI_GP1_WVALID(),
.M_AXI_GP1_ARID(),
.M_AXI_GP1_AWID(),
.M_AXI_GP1_WID(),
.M_AXI_GP1_ARBURST(),
.M_AXI_GP1_ARLOCK(),
.M_AXI_GP1_ARSIZE(),
.M_AXI_GP1_AWBURST(),
.M_AXI_GP1_AWLOCK(),
.M_AXI_GP1_AWSIZE(),
.M_AXI_GP1_ARPROT(),
.M_AXI_GP1_AWPROT(),
.M_AXI_GP1_ARADDR(),
.M_AXI_GP1_AWADDR(),
.M_AXI_GP1_WDATA(),
.M_AXI_GP1_ARCACHE(),
.M_AXI_GP1_ARLEN(),
.M_AXI_GP1_ARQOS(),
.M_AXI_GP1_AWCACHE(),
.M_AXI_GP1_AWLEN(),
.M_AXI_GP1_AWQOS(),
.M_AXI_GP1_WSTRB(),
.M_AXI_GP1_ACLK(1'B0),
.M_AXI_GP1_ARREADY(1'B0),
.M_AXI_GP1_AWREADY(1'B0),
.M_AXI_GP1_BVALID(1'B0),
.M_AXI_GP1_RLAST(1'B0),
.M_AXI_GP1_RVALID(1'B0),
.M_AXI_GP1_WREADY(1'B0),
.M_AXI_GP1_BID(12'B0),
.M_AXI_GP1_RID(12'B0),
.M_AXI_GP1_BRESP(2'B0),
.M_AXI_GP1_RRESP(2'B0),
.M_AXI_GP1_RDATA(32'B0),
.S_AXI_GP0_ARREADY(),
.S_AXI_GP0_AWREADY(),
.S_AXI_GP0_BVALID(),
.S_AXI_GP0_RLAST(),
.S_AXI_GP0_RVALID(),
.S_AXI_GP0_WREADY(),
.S_AXI_GP0_BRESP(),
.S_AXI_GP0_RRESP(),
.S_AXI_GP0_RDATA(),
.S_AXI_GP0_BID(),
.S_AXI_GP0_RID(),
.S_AXI_GP0_ACLK(1'B0),
.S_AXI_GP0_ARVALID(1'B0),
.S_AXI_GP0_AWVALID(1'B0),
.S_AXI_GP0_BREADY(1'B0),
.S_AXI_GP0_RREADY(1'B0),
.S_AXI_GP0_WLAST(1'B0),
.S_AXI_GP0_WVALID(1'B0),
.S_AXI_GP0_ARBURST(2'B0),
.S_AXI_GP0_ARLOCK(2'B0),
.S_AXI_GP0_ARSIZE(3'B0),
.S_AXI_GP0_AWBURST(2'B0),
.S_AXI_GP0_AWLOCK(2'B0),
.S_AXI_GP0_AWSIZE(3'B0),
.S_AXI_GP0_ARPROT(3'B0),
.S_AXI_GP0_AWPROT(3'B0),
.S_AXI_GP0_ARADDR(32'B0),
.S_AXI_GP0_AWADDR(32'B0),
.S_AXI_GP0_WDATA(32'B0),
.S_AXI_GP0_ARCACHE(4'B0),
.S_AXI_GP0_ARLEN(4'B0),
.S_AXI_GP0_ARQOS(4'B0),
.S_AXI_GP0_AWCACHE(4'B0),
.S_AXI_GP0_AWLEN(4'B0),
.S_AXI_GP0_AWQOS(4'B0),
.S_AXI_GP0_WSTRB(4'B0),
.S_AXI_GP0_ARID(6'B0),
.S_AXI_GP0_AWID(6'B0),
.S_AXI_GP0_WID(6'B0),
.S_AXI_GP1_ARREADY(),
.S_AXI_GP1_AWREADY(),
.S_AXI_GP1_BVALID(),
.S_AXI_GP1_RLAST(),
.S_AXI_GP1_RVALID(),
.S_AXI_GP1_WREADY(),
.S_AXI_GP1_BRESP(),
.S_AXI_GP1_RRESP(),
.S_AXI_GP1_RDATA(),
.S_AXI_GP1_BID(),
.S_AXI_GP1_RID(),
.S_AXI_GP1_ACLK(1'B0),
.S_AXI_GP1_ARVALID(1'B0),
.S_AXI_GP1_AWVALID(1'B0),
.S_AXI_GP1_BREADY(1'B0),
.S_AXI_GP1_RREADY(1'B0),
.S_AXI_GP1_WLAST(1'B0),
.S_AXI_GP1_WVALID(1'B0),
.S_AXI_GP1_ARBURST(2'B0),
.S_AXI_GP1_ARLOCK(2'B0),
.S_AXI_GP1_ARSIZE(3'B0),
.S_AXI_GP1_AWBURST(2'B0),
.S_AXI_GP1_AWLOCK(2'B0),
.S_AXI_GP1_AWSIZE(3'B0),
.S_AXI_GP1_ARPROT(3'B0),
.S_AXI_GP1_AWPROT(3'B0),
.S_AXI_GP1_ARADDR(32'B0),
.S_AXI_GP1_AWADDR(32'B0),
.S_AXI_GP1_WDATA(32'B0),
.S_AXI_GP1_ARCACHE(4'B0),
.S_AXI_GP1_ARLEN(4'B0),
.S_AXI_GP1_ARQOS(4'B0),
.S_AXI_GP1_AWCACHE(4'B0),
.S_AXI_GP1_AWLEN(4'B0),
.S_AXI_GP1_AWQOS(4'B0),
.S_AXI_GP1_WSTRB(4'B0),
.S_AXI_GP1_ARID(6'B0),
.S_AXI_GP1_AWID(6'B0),
.S_AXI_GP1_WID(6'B0),
.S_AXI_ACP_ARREADY(),
.S_AXI_ACP_AWREADY(),
.S_AXI_ACP_BVALID(),
.S_AXI_ACP_RLAST(),
.S_AXI_ACP_RVALID(),
.S_AXI_ACP_WREADY(),
.S_AXI_ACP_BRESP(),
.S_AXI_ACP_RRESP(),
.S_AXI_ACP_BID(),
.S_AXI_ACP_RID(),
.S_AXI_ACP_RDATA(),
.S_AXI_ACP_ACLK(1'B0),
.S_AXI_ACP_ARVALID(1'B0),
.S_AXI_ACP_AWVALID(1'B0),
.S_AXI_ACP_BREADY(1'B0),
.S_AXI_ACP_RREADY(1'B0),
.S_AXI_ACP_WLAST(1'B0),
.S_AXI_ACP_WVALID(1'B0),
.S_AXI_ACP_ARID(3'B0),
.S_AXI_ACP_ARPROT(3'B0),
.S_AXI_ACP_AWID(3'B0),
.S_AXI_ACP_AWPROT(3'B0),
.S_AXI_ACP_WID(3'B0),
.S_AXI_ACP_ARADDR(32'B0),
.S_AXI_ACP_AWADDR(32'B0),
.S_AXI_ACP_ARCACHE(4'B0),
.S_AXI_ACP_ARLEN(4'B0),
.S_AXI_ACP_ARQOS(4'B0),
.S_AXI_ACP_AWCACHE(4'B0),
.S_AXI_ACP_AWLEN(4'B0),
.S_AXI_ACP_AWQOS(4'B0),
.S_AXI_ACP_ARBURST(2'B0),
.S_AXI_ACP_ARLOCK(2'B0),
.S_AXI_ACP_ARSIZE(3'B0),
.S_AXI_ACP_AWBURST(2'B0),
.S_AXI_ACP_AWLOCK(2'B0),
.S_AXI_ACP_AWSIZE(3'B0),
.S_AXI_ACP_ARUSER(5'B0),
.S_AXI_ACP_AWUSER(5'B0),
.S_AXI_ACP_WDATA(64'B0),
.S_AXI_ACP_WSTRB(8'B0),
.S_AXI_HP0_ARREADY(),
.S_AXI_HP0_AWREADY(),
.S_AXI_HP0_BVALID(),
.S_AXI_HP0_RLAST(),
.S_AXI_HP0_RVALID(),
.S_AXI_HP0_WREADY(),
.S_AXI_HP0_BRESP(),
.S_AXI_HP0_RRESP(),
.S_AXI_HP0_BID(),
.S_AXI_HP0_RID(),
.S_AXI_HP0_RDATA(),
.S_AXI_HP0_ACLK(1'B0),
.S_AXI_HP0_ARVALID(1'B0),
.S_AXI_HP0_AWVALID(1'B0),
.S_AXI_HP0_BREADY(1'B0),
.S_AXI_HP0_RREADY(1'B0),
.S_AXI_HP0_WLAST(1'B0),
.S_AXI_HP0_WVALID(1'B0),
.S_AXI_HP0_ARBURST(2'B0),
.S_AXI_HP0_ARLOCK(2'B0),
.S_AXI_HP0_ARSIZE(3'B0),
.S_AXI_HP0_AWBURST(2'B0),
.S_AXI_HP0_AWLOCK(2'B0),
.S_AXI_HP0_AWSIZE(3'B0),
.S_AXI_HP0_ARPROT(3'B0),
.S_AXI_HP0_AWPROT(3'B0),
.S_AXI_HP0_ARADDR(32'B0),
.S_AXI_HP0_AWADDR(32'B0),
.S_AXI_HP0_ARCACHE(4'B0),
.S_AXI_HP0_ARLEN(4'B0),
.S_AXI_HP0_ARQOS(4'B0),
.S_AXI_HP0_AWCACHE(4'B0),
.S_AXI_HP0_AWLEN(4'B0),
.S_AXI_HP0_AWQOS(4'B0),
.S_AXI_HP0_ARID(6'B0),
.S_AXI_HP0_AWID(6'B0),
.S_AXI_HP0_WID(6'B0),
.S_AXI_HP0_WDATA(64'B0),
.S_AXI_HP0_WSTRB(8'B0),
.S_AXI_HP1_ARREADY(),
.S_AXI_HP1_AWREADY(),
.S_AXI_HP1_BVALID(),
.S_AXI_HP1_RLAST(),
.S_AXI_HP1_RVALID(),
.S_AXI_HP1_WREADY(),
.S_AXI_HP1_BRESP(),
.S_AXI_HP1_RRESP(),
.S_AXI_HP1_BID(),
.S_AXI_HP1_RID(),
.S_AXI_HP1_RDATA(),
.S_AXI_HP1_ACLK(1'B0),
.S_AXI_HP1_ARVALID(1'B0),
.S_AXI_HP1_AWVALID(1'B0),
.S_AXI_HP1_BREADY(1'B0),
.S_AXI_HP1_RREADY(1'B0),
.S_AXI_HP1_WLAST(1'B0),
.S_AXI_HP1_WVALID(1'B0),
.S_AXI_HP1_ARBURST(2'B0),
.S_AXI_HP1_ARLOCK(2'B0),
.S_AXI_HP1_ARSIZE(3'B0),
.S_AXI_HP1_AWBURST(2'B0),
.S_AXI_HP1_AWLOCK(2'B0),
.S_AXI_HP1_AWSIZE(3'B0),
.S_AXI_HP1_ARPROT(3'B0),
.S_AXI_HP1_AWPROT(3'B0),
.S_AXI_HP1_ARADDR(32'B0),
.S_AXI_HP1_AWADDR(32'B0),
.S_AXI_HP1_ARCACHE(4'B0),
.S_AXI_HP1_ARLEN(4'B0),
.S_AXI_HP1_ARQOS(4'B0),
.S_AXI_HP1_AWCACHE(4'B0),
.S_AXI_HP1_AWLEN(4'B0),
.S_AXI_HP1_AWQOS(4'B0),
.S_AXI_HP1_ARID(6'B0),
.S_AXI_HP1_AWID(6'B0),
.S_AXI_HP1_WID(6'B0),
.S_AXI_HP1_WDATA(64'B0),
.S_AXI_HP1_WSTRB(8'B0),
.S_AXI_HP2_ARREADY(),
.S_AXI_HP2_AWREADY(),
.S_AXI_HP2_BVALID(),
.S_AXI_HP2_RLAST(),
.S_AXI_HP2_RVALID(),
.S_AXI_HP2_WREADY(),
.S_AXI_HP2_BRESP(),
.S_AXI_HP2_RRESP(),
.S_AXI_HP2_BID(),
.S_AXI_HP2_RID(),
.S_AXI_HP2_RDATA(),
.S_AXI_HP2_ACLK(1'B0),
.S_AXI_HP2_ARVALID(1'B0),
.S_AXI_HP2_AWVALID(1'B0),
.S_AXI_HP2_BREADY(1'B0),
.S_AXI_HP2_RREADY(1'B0),
.S_AXI_HP2_WLAST(1'B0),
.S_AXI_HP2_WVALID(1'B0),
.S_AXI_HP2_ARBURST(2'B0),
.S_AXI_HP2_ARLOCK(2'B0),
.S_AXI_HP2_ARSIZE(3'B0),
.S_AXI_HP2_AWBURST(2'B0),
.S_AXI_HP2_AWLOCK(2'B0),
.S_AXI_HP2_AWSIZE(3'B0),
.S_AXI_HP2_ARPROT(3'B0),
.S_AXI_HP2_AWPROT(3'B0),
.S_AXI_HP2_ARADDR(32'B0),
.S_AXI_HP2_AWADDR(32'B0),
.S_AXI_HP2_ARCACHE(4'B0),
.S_AXI_HP2_ARLEN(4'B0),
.S_AXI_HP2_ARQOS(4'B0),
.S_AXI_HP2_AWCACHE(4'B0),
.S_AXI_HP2_AWLEN(4'B0),
.S_AXI_HP2_AWQOS(4'B0),
.S_AXI_HP2_ARID(6'B0),
.S_AXI_HP2_AWID(6'B0),
.S_AXI_HP2_WID(6'B0),
.S_AXI_HP2_WDATA(64'B0),
.S_AXI_HP2_WSTRB(8'B0),
.S_AXI_HP3_ARREADY(),
.S_AXI_HP3_AWREADY(),
.S_AXI_HP3_BVALID(),
.S_AXI_HP3_RLAST(),
.S_AXI_HP3_RVALID(),
.S_AXI_HP3_WREADY(),
.S_AXI_HP3_BRESP(),
.S_AXI_HP3_RRESP(),
.S_AXI_HP3_BID(),
.S_AXI_HP3_RID(),
.S_AXI_HP3_RDATA(),
.S_AXI_HP3_ACLK(1'B0),
.S_AXI_HP3_ARVALID(1'B0),
.S_AXI_HP3_AWVALID(1'B0),
.S_AXI_HP3_BREADY(1'B0),
.S_AXI_HP3_RREADY(1'B0),
.S_AXI_HP3_WLAST(1'B0),
.S_AXI_HP3_WVALID(1'B0),
.S_AXI_HP3_ARBURST(2'B0),
.S_AXI_HP3_ARLOCK(2'B0),
.S_AXI_HP3_ARSIZE(3'B0),
.S_AXI_HP3_AWBURST(2'B0),
.S_AXI_HP3_AWLOCK(2'B0),
.S_AXI_HP3_AWSIZE(3'B0),
.S_AXI_HP3_ARPROT(3'B0),
.S_AXI_HP3_AWPROT(3'B0),
.S_AXI_HP3_ARADDR(32'B0),
.S_AXI_HP3_AWADDR(32'B0),
.S_AXI_HP3_ARCACHE(4'B0),
.S_AXI_HP3_ARLEN(4'B0),
.S_AXI_HP3_ARQOS(4'B0),
.S_AXI_HP3_AWCACHE(4'B0),
.S_AXI_HP3_AWLEN(4'B0),
.S_AXI_HP3_AWQOS(4'B0),
.S_AXI_HP3_ARID(6'B0),
.S_AXI_HP3_AWID(6'B0),
.S_AXI_HP3_WID(6'B0),
.S_AXI_HP3_WDATA(64'B0),
.S_AXI_HP3_WSTRB(8'B0),
.FCLK_CLK0(FCLK_CLK0),
.FCLK_CLK1(),
.FCLK_CLK2(),
.FCLK_CLK3(),
.FCLK_RESET0_N(FCLK_RESET0_N),
.FCLK_RESET1_N(),
.FCLK_RESET2_N(),
.FCLK_RESET3_N(),
.IRQ_F2P(16'B0),
.PS_SRSTB(PS_SRSTB),
.PS_CLK(PS_CLK),
.PS_PORB(PS_PORB)
);
endmodule
|
`timescale 1ns / 1ps
/*
Copyright (C) 2016-2017, Stephen J. Leary
All rights reserved.
This file is part of TF530 (Terrible Fire 030 Accelerator).
TF530 is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
TF530 is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with TF530. If not, see <http://www.gnu.org/licenses/>.
*/
module tf530_ram(
input CLKCPU,
input RESET,
input A0,
input A1,
input [8:2] AB,
input [23:12] A,
inout [7:0] D,
input [1:0] SIZ,
input IDEINT,
input IDEWAIT,
output INT2,
input AS20,
input RW20,
input DS20,
// cache and burst control
input CBREQ,
output CBACK,
output CIIN,
output STERM,
// 32 bit internal cycle.
// i.e. assert OVR
output INTCYCLE,
// spare / debug
output SPARE,
// ram chip control
output [3:0] RAMCS,
output RAMOE
);
reg AS20_D = 1'b1;
reg DS20_D = 1'b1;
reg STERM_D = 1'b1;
wire BUS_CYCLE = (~DS20_D | DS20);
reg configured = 'b0;
reg shutup = 'b0;
reg [7:0] data_out = 'h00;
reg [7:0] base = 'h40;
wire GAYLE_INT2;
wire [7:0] GAYLE_DOUT;
//
wire IDE_ACCESS = (A[23:15] != {8'hDA, 1'b0}) | DS20 | AS20;
// $DE0000 or $DA8000 (Ignores A18)
wire GAYLE_REGS = (A[23:15] != {8'hDA, 1'b1});
wire GAYLE_ID= (A[23:15] != {8'hDE, 1'b0});
wire GAYLE_ACCESS = (GAYLE_ID & GAYLE_REGS) | DS20 | AS20;
wire GAYLE_READ = (GAYLE_ACCESS | ~RW20);
gayle GAYLE(
.CLKCPU ( CLKCPU ),
.RESET ( RESET ),
.CS ( GAYLE_ACCESS ),
.DS ( DS20 ),
.RW ( RW20 ),
.A18 ( A[18] ),
.A ( {1,b0, A[13:12]}),
.IDE_INT( IDEINT ),
.INT2 ( GAYLE_INT2 ),
.DIN ( D ),
.DOUT ( GAYLE_DOUT )
);
// 0xE80000
wire Z2_ACCESS = ({A[23:16]} != {8'hE8}) | AS20 | DS20 | shutup | configured;
wire Z2_READ = (Z2_ACCESS | ~RW20);
wire Z2_WRITE = (Z2_ACCESS | RW20);
wire RAM_ACCESS = ({A[23:21]} != {base[7:5]}) | AS20 | DS20 | ~configured;
wire [6:0] zaddr = {AB[7:2],A1};
always @(posedge CLKCPU) begin
AS20_D <= AS20;
DS20_D <= DS20;
STERM_D <= INTCYCLE | ~STERM_D;
if (RESET == 1'b0) begin
configured <= 1'b0;
shutup <= 1'b0;
STERM_D <= 1'b1;
end else begin
if (Z2_WRITE === 1'b0) begin
case (zaddr)
'h24: begin
base[7:4] <= D[7:4];
configured <= 1'b1;
end
'h25: base[3:0] <= D[7:4];
'h26: shutup <= 1'b1;
endcase
end
data_out <= 8'hff;
// the Gayle/Gary ID shift register.
if (Z2_READ == 1'b0) begin
// zorro config ROM
case (zaddr)
'h00: data_out[7:4] <= 4'he;
'h01: data_out[7:4] <= 4'h6;
'h02: data_out[7:4] <= 4'h7;
'h03: data_out[7:4] <= 4'h7;
'h04: data_out[7:4] <= 4'h7;
'h08: data_out[7:4] <= 4'he;
'h09: data_out[7:4] <= 4'hc;
'h0a: data_out[7:4] <= 4'h2;
'h0b: data_out[7:4] <= 4'h7;
'h10: data_out[7:4] <= 4'hc;
'h12: data_out[7:4] <= 4'hc;
'h13: data_out[7:4] <= 4'h6;
endcase
end else if (GAYLE_READ == 1'b0) begin
data_out <= GAYLE_DOUT;
end
end
end
wire RAMCS3n = A1 | A0; //
wire RAMCS2n = (~SIZ[1] & SIZ[0] & ~A0) | A1;
wire RAMCS1n = (SIZ[1] & ~SIZ[0] & ~A1 & ~A0) | (~SIZ[1] & SIZ[0] & ~A1) |(A1 & A0);
wire RAMCS0n = (~SIZ[1] & SIZ[0] & ~A1 ) | (~SIZ[1] & SIZ[0] & ~A0 ) | (SIZ[1] & ~A1 & ~A0 ) | (SIZ[1] & ~SIZ[0] & ~A1 );
// disable all the RAM.
assign RAMOE = RAM_ACCESS;
assign RAMCS = {RAMCS3n | RAM_ACCESS, RAMCS2n | RAM_ACCESS, RAMCS1n | RAM_ACCESS , RAMCS0n | RAM_ACCESS};
assign INTCYCLE = RAM_ACCESS & GAYLE_ACCESS;
// disable all burst control.
assign STERM = STERM_D;
assign CBACK = 1'b1; //STERM_D | CBREQ;
// cache the sram.
assign CIIN = 1'b0; //~RAM_ACCESS;
assign INT2 = GAYLE_INT2 ? 1'b0 : 1'bz;
assign D = Z2_READ & GAYLE_READ ? 8'bzzzzzzzz : data_out;
endmodule
|
//--------------------------------------------------------------------------------
// sampler.vhd
//
// Copyright (C) 2006 Michael Poppitz
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
//
//--------------------------------------------------------------------------------
//
// Details: http://www.sump.org/projects/analyzer/
//
// Produces samples from input applying a programmable divider to the clock.
// Sampling rate can be calculated by:
//
// r = f / (d + 1)
//
// Where r is the sampling rate, f is the clock frequency and d is the value
// programmed into the divider register.
//
// As of version 0.6 sampling on an extClock_mode clock is also supported. If extclock_mode
// is set '1', the extClock_mode clock will be used to sample data. (Divider is
// ignored for this.)
//
//--------------------------------------------------------------------------------
//
// 12/29/2010 - Verilog Version + cleanups created by Ian Davis (IED) - mygizmos.org
//
`timescale 1ns/100ps
module sampler (
clock, extClock_mode,
wrDivider, config_data,
validIn, dataIn,
// outputs
validOut, dataOut, ready50);
input clock; // internal clock
input extClock_mode; // clock selection
input wrDivider; // write divider register
input [23:0] config_data; // configuration data
input validIn; // dataIn is valid
input [31:0] dataIn; // 32 input channels
output validOut; // new sample ready
output [31:0] dataOut; // sampled data
output ready50;
parameter TRUE = 1'b1;
parameter FALSE = 1'b0;
//
// Registers...
//
reg validOut, next_validOut;
reg [31:0] dataOut, next_dataOut;
reg ready50, next_ready50; // low rate sample signal with 50% duty cycle
reg [23:0] divider, next_divider;
reg [23:0] counter, next_counter; // Made counter decrementing. Better synth.
wire counter_zero = ~|counter;
//
// Generate slow sample reference...
//
initial
begin
divider = 0;
counter = 0;
validOut = 0;
dataOut = 0;
end
always @ (posedge clock)
begin
divider = next_divider;
counter = next_counter;
validOut = next_validOut;
dataOut = next_dataOut;
end
always @*
begin
#1;
next_divider = divider;
next_counter = counter;
next_validOut = FALSE;
next_dataOut = dataOut;
if (extClock_mode)
begin
next_validOut = validIn;
next_dataOut = dataIn;
end
else if (validIn && counter_zero)
begin
next_validOut = TRUE;
next_dataOut = dataIn;
end
//
// Manage counter divider for internal clock sampling mode...
//
if (wrDivider)
begin
next_divider = config_data[23:0];
next_counter = next_divider;
next_validOut = FALSE; // reset
end
else if (validIn)
if (counter_zero)
next_counter = divider;
else next_counter = counter-1'b1;
end
//
// Generate ready50 50% duty cycle sample signal...
//
always @(posedge clock)
begin
ready50 = next_ready50;
end
always @*
begin
#1;
next_ready50 = ready50;
if (wrDivider)
next_ready50 = FALSE; // reset
else if (counter_zero)
next_ready50 = TRUE;
else if (counter == divider[23:1])
next_ready50 = FALSE;
end
endmodule
|
/*
* lzw - Simple, Logarithmic Right Shift
* Copyright (C) 2015 Sean Ryan Moore
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
`ifdef INC_RIGHT_SHIFT
`else
`define INC_RIGHT_SHIFT
`timescale 1 ns / 100 ps
module RightShift(
ovalue,
ivalue,
amount
);
parameter LOGWORD=0;
localparam WORD=(1<<LOGWORD);
output reg [WORD-1:0] ovalue; // shifted value
input [WORD-1:0] ivalue; // original value
input [LOGWORD-1:0] amount; // amount by which to shift right
reg [WORD-1:0] rank [LOGWORD+1-1:0]; // intermediate shifts; +1 is aliased to ivalue
always @(*) begin
rank[LOGWORD] <= ivalue;
end
genvar i;
genvar j;
generate
for(i=0; i<LOGWORD; i=i+1) begin : i_right_shift // iterates over logarithmically-spaced ranks
always @(*) begin
if(amount[i]) begin
rank[i] <= rank[i+1][WORD-1:(1<<i)];
end
else begin
rank[i] <= rank[i+1];
end
end
end
endgenerate
always @(*) begin
ovalue <= rank[0];
end
endmodule
`endif
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of inst_t_e
//
// Generated
// by: wig
// on: Mon Jun 26 08:25:04 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../../generic.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: inst_t_e.v,v 1.3 2006/06/26 08:39:43 wig Exp $
// $Date: 2006/06/26 08:39:43 $
// $Log: inst_t_e.v,v $
// Revision 1.3 2006/06/26 08:39:43 wig
// Update more testcases (up to generic)
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
//
// Generator: mix_0.pl Revision: 1.46 , [email protected]
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of inst_t_e
//
// No `defines in this module
module inst_t_e
//
// Generated Module inst_t
//
(
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
// Generated Instance Port Map for inst_a
inst_a_e inst_a (
);
// End of Generated Instance Port Map for inst_a
// Generated Instance Port Map for inst_e
inst_e_e inst_e (
);
// End of Generated Instance Port Map for inst_e
endmodule
//
// End of Generated Module rtl of inst_t_e
//
//
//!End of Module/s
// --------------------------------------------------------------
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NAND2_SYMBOL_V
`define SKY130_FD_SC_MS__NAND2_SYMBOL_V
/**
* nand2: 2-input NAND.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__nand2 (
//# {{data|Data Signals}}
input A,
input B,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__NAND2_SYMBOL_V
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : col_mach.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// The column machine manages the dq bus. Since there is a single DQ
// bus, and the column part of the DRAM is tightly coupled to this DQ
// bus, conceptually, the DQ bus and all of the column hardware in
// a multi rank DRAM array are managed as a single unit.
//
//
// The column machine does not "enforce" the column timing directly.
// It generates information and sends it to the bank machines. If the
// bank machines incorrectly make a request, the column machine will
// simply overwrite the existing request with the new request even
// if this would result in a timing or protocol violation.
//
// The column machine
// hosts the block that controls read and write data transfer
// to and from the dq bus.
//
// And if configured, there is provision for tracking the address
// of a command as it moves through the column pipeline. This
// address will be logged for detected ECC errors.
`timescale 1 ps / 1 ps
module mig_7series_v2_0_col_mach #
(
parameter TCQ = 100,
parameter BANK_WIDTH = 3,
parameter BURST_MODE = "8",
parameter COL_WIDTH = 12,
parameter CS_WIDTH = 4,
parameter DATA_BUF_ADDR_WIDTH = 8,
parameter DATA_BUF_OFFSET_WIDTH = 1,
parameter DELAY_WR_DATA_CNTRL = 0,
parameter DQS_WIDTH = 8,
parameter DRAM_TYPE = "DDR3",
parameter EARLY_WR_DATA_ADDR = "OFF",
parameter ECC = "OFF",
parameter MC_ERR_ADDR_WIDTH = 31,
parameter nCK_PER_CLK = 2,
parameter nPHY_WRLAT = 0,
parameter RANK_WIDTH = 2,
parameter ROW_WIDTH = 16
)
(/*AUTOARG*/
// Outputs
dq_busy_data, wr_data_offset, mc_wrdata_en, wr_data_en,
wr_data_addr, rd_rmw, ecc_err_addr, ecc_status_valid, wr_ecc_buf, rd_data_end,
rd_data_addr, rd_data_offset, rd_data_en, col_read_fifo_empty,
// Inputs
clk, rst, sent_col, col_size, col_wr_data_buf_addr,
phy_rddata_valid, col_periodic_rd, col_data_buf_addr, col_rmw,
col_rd_wr, col_ra, col_ba, col_row, col_a
);
input clk;
input rst;
input sent_col;
input col_rd_wr;
output reg dq_busy_data = 1'b0;
// The following generates a column command disable based mostly on the type
// of DRAM and the fabric to DRAM CK ratio.
generate
if ((nCK_PER_CLK == 1) && ((BURST_MODE == "8") || (DRAM_TYPE == "DDR3")))
begin : three_bumps
reg [1:0] granted_col_d_r;
wire [1:0] granted_col_d_ns = {sent_col, granted_col_d_r[1]};
always @(posedge clk) granted_col_d_r <= #TCQ granted_col_d_ns;
always @(/*AS*/granted_col_d_r or sent_col)
dq_busy_data = sent_col || |granted_col_d_r;
end
if (((nCK_PER_CLK == 2) && ((BURST_MODE == "8") || (DRAM_TYPE == "DDR3")))
|| ((nCK_PER_CLK == 1) && ((BURST_MODE == "4") || (DRAM_TYPE == "DDR2"))))
begin : one_bump
always @(/*AS*/sent_col) dq_busy_data = sent_col;
end
endgenerate
// This generates a data offset based on fabric clock to DRAM CK ratio and
// the size bit. Note that this is different that the dq_busy_data signal
// generated above.
reg [1:0] offset_r = 2'b0;
reg [1:0] offset_ns = 2'b0;
input col_size;
wire data_end;
generate
if(nCK_PER_CLK == 4) begin : data_valid_4_1
// For 4:1 mode all data is transfered in a single beat so the default
// values of 0 for offset_r/offset_ns suffice - just tie off data_end
assign data_end = 1'b1;
end
else begin
if(DATA_BUF_OFFSET_WIDTH == 2) begin : data_valid_1_1
always @(col_size or offset_r or rst or sent_col) begin
if (rst) offset_ns = 2'b0;
else begin
offset_ns = offset_r;
if (sent_col) offset_ns = 2'b1;
else if (|offset_r && (offset_r != {col_size, 1'b1}))
offset_ns = offset_r + 2'b1;
else offset_ns = 2'b0;
end
end
always @(posedge clk) offset_r <= #TCQ offset_ns;
assign data_end = col_size ? (offset_r == 2'b11) : offset_r[0];
end
else begin : data_valid_2_1
always @(col_size or rst or sent_col)
offset_ns[0] = rst ? 1'b0 : sent_col && col_size;
always @(posedge clk) offset_r[0] <= #TCQ offset_ns[0];
assign data_end = col_size ? offset_r[0] : 1'b1;
end
end
endgenerate
reg [DATA_BUF_OFFSET_WIDTH-1:0] offset_r1 = {DATA_BUF_OFFSET_WIDTH{1'b0}};
reg [DATA_BUF_OFFSET_WIDTH-1:0] offset_r2 = {DATA_BUF_OFFSET_WIDTH{1'b0}};
reg col_rd_wr_r1;
reg col_rd_wr_r2;
generate
if ((nPHY_WRLAT >= 1) || (DELAY_WR_DATA_CNTRL == 1)) begin : offset_pipe_0
always @(posedge clk) offset_r1 <=
#TCQ offset_r[DATA_BUF_OFFSET_WIDTH-1:0];
always @(posedge clk) col_rd_wr_r1 <= #TCQ col_rd_wr;
end
if(nPHY_WRLAT == 2) begin : offset_pipe_1
always @(posedge clk) offset_r2 <=
#TCQ offset_r1[DATA_BUF_OFFSET_WIDTH-1:0];
always @(posedge clk) col_rd_wr_r2 <= #TCQ col_rd_wr_r1;
end
endgenerate
output wire [DATA_BUF_OFFSET_WIDTH-1:0] wr_data_offset;
assign wr_data_offset = (DELAY_WR_DATA_CNTRL == 1)
? offset_r1[DATA_BUF_OFFSET_WIDTH-1:0]
: (EARLY_WR_DATA_ADDR == "OFF")
? offset_r[DATA_BUF_OFFSET_WIDTH-1:0]
: offset_ns[DATA_BUF_OFFSET_WIDTH-1:0];
reg sent_col_r1;
reg sent_col_r2;
always @(posedge clk) sent_col_r1 <= #TCQ sent_col;
always @(posedge clk) sent_col_r2 <= #TCQ sent_col_r1;
wire wrdata_en = (nPHY_WRLAT == 0) ?
(sent_col || |offset_r) & ~col_rd_wr :
(nPHY_WRLAT == 1) ?
(sent_col_r1 || |offset_r1) & ~col_rd_wr_r1 :
//(nPHY_WRLAT >= 2) ?
(sent_col_r2 || |offset_r2) & ~col_rd_wr_r2;
output wire mc_wrdata_en;
assign mc_wrdata_en = wrdata_en;
output wire wr_data_en;
assign wr_data_en = (DELAY_WR_DATA_CNTRL == 1)
? ((sent_col_r1 || |offset_r1) && ~col_rd_wr_r1)
: ((sent_col || |offset_r) && ~col_rd_wr);
input [DATA_BUF_ADDR_WIDTH-1:0] col_wr_data_buf_addr;
output wire [DATA_BUF_ADDR_WIDTH-1:0] wr_data_addr;
generate
if (DELAY_WR_DATA_CNTRL == 1) begin : delay_wr_data_cntrl_eq_1
reg [DATA_BUF_ADDR_WIDTH-1:0] col_wr_data_buf_addr_r;
always @(posedge clk) col_wr_data_buf_addr_r <=
#TCQ col_wr_data_buf_addr;
assign wr_data_addr = col_wr_data_buf_addr_r;
end
else begin : delay_wr_data_cntrl_ne_1
assign wr_data_addr = col_wr_data_buf_addr;
end
endgenerate
// CAS-RD to mc_rddata_en
wire read_data_valid = (sent_col || |offset_r) && col_rd_wr;
function integer clogb2 (input integer size); // ceiling logb2
begin
size = size - 1;
for (clogb2=1; size>1; clogb2=clogb2+1)
size = size >> 1;
end
endfunction // clogb2
// Implement FIFO that records reads as they are sent to the DRAM.
// When phy_rddata_valid is returned some unknown time later, the
// FIFO output is used to control how the data is interpreted.
input phy_rddata_valid;
output wire rd_rmw;
output reg [MC_ERR_ADDR_WIDTH-1:0] ecc_err_addr;
output reg ecc_status_valid;
output reg wr_ecc_buf;
output reg rd_data_end;
output reg [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr;
output reg [DATA_BUF_OFFSET_WIDTH-1:0] rd_data_offset;
output reg rd_data_en /* synthesis syn_maxfan = 10 */;
output col_read_fifo_empty;
input col_periodic_rd;
input [DATA_BUF_ADDR_WIDTH-1:0] col_data_buf_addr;
input col_rmw;
input [RANK_WIDTH-1:0] col_ra;
input [BANK_WIDTH-1:0] col_ba;
input [ROW_WIDTH-1:0] col_row;
input [ROW_WIDTH-1:0] col_a;
// Real column address (skip A10/AP and A12/BC#). The maximum width is 12;
// the width will be tailored for the target DRAM downstream.
wire [11:0] col_a_full;
// Minimum row width is 12; take remaining 11 bits after omitting A10/AP
assign col_a_full[10:0] = {col_a[11], col_a[9:0]};
// Get the 12th bit when row address width accommodates it; omit A12/BC#
generate
if (ROW_WIDTH >= 14) begin : COL_A_FULL_11_1
assign col_a_full[11] = col_a[13];
end else begin : COL_A_FULL_11_0
assign col_a_full[11] = 0;
end
endgenerate
// Extract only the width of the target DRAM
wire [COL_WIDTH-1:0] col_a_extracted = col_a_full[COL_WIDTH-1:0];
localparam MC_ERR_LINE_WIDTH = MC_ERR_ADDR_WIDTH-DATA_BUF_OFFSET_WIDTH;
localparam FIFO_WIDTH = 1 /*data_end*/ +
1 /*periodic_rd*/ +
DATA_BUF_ADDR_WIDTH +
DATA_BUF_OFFSET_WIDTH +
((ECC == "OFF") ? 0 : 1+MC_ERR_LINE_WIDTH);
localparam FULL_RAM_CNT = (FIFO_WIDTH/6);
localparam REMAINDER = FIFO_WIDTH % 6;
localparam RAM_CNT = FULL_RAM_CNT + ((REMAINDER == 0 ) ? 0 : 1);
localparam RAM_WIDTH = (RAM_CNT*6);
generate
begin : read_fifo
wire [MC_ERR_LINE_WIDTH:0] ecc_line;
if (CS_WIDTH == 1)
assign ecc_line = {col_rmw, col_ba, col_row, col_a_extracted};
else
assign ecc_line = {col_rmw,
col_ra,
col_ba,
col_row,
col_a_extracted};
wire [FIFO_WIDTH-1:0] real_fifo_data;
if (ECC == "OFF")
assign real_fifo_data = {data_end,
col_periodic_rd,
col_data_buf_addr,
offset_r[DATA_BUF_OFFSET_WIDTH-1:0]};
else
assign real_fifo_data = {data_end,
col_periodic_rd,
col_data_buf_addr,
offset_r[DATA_BUF_OFFSET_WIDTH-1:0],
ecc_line};
wire [RAM_WIDTH-1:0] fifo_in_data;
if (REMAINDER == 0)
assign fifo_in_data = real_fifo_data;
else
assign fifo_in_data = {{6-REMAINDER{1'b0}}, real_fifo_data};
wire [RAM_WIDTH-1:0] fifo_out_data_ns;
reg [4:0] head_r;
wire [4:0] head_ns = rst ? 5'b0 : read_data_valid
? (head_r + 5'b1)
: head_r;
always @(posedge clk) head_r <= #TCQ head_ns;
reg [4:0] tail_r;
wire [4:0] tail_ns = rst ? 5'b0 : phy_rddata_valid
? (tail_r + 5'b1)
: tail_r;
always @(posedge clk) tail_r <= #TCQ tail_ns;
assign col_read_fifo_empty = head_r == tail_r ? 1'b1 : 1'b0;
genvar i;
for (i=0; i<RAM_CNT; i=i+1) begin : fifo_ram
RAM32M
#(.INIT_A(64'h0000000000000000),
.INIT_B(64'h0000000000000000),
.INIT_C(64'h0000000000000000),
.INIT_D(64'h0000000000000000)
) RAM32M0 (
.DOA(fifo_out_data_ns[((i*6)+4)+:2]),
.DOB(fifo_out_data_ns[((i*6)+2)+:2]),
.DOC(fifo_out_data_ns[((i*6)+0)+:2]),
.DOD(),
.DIA(fifo_in_data[((i*6)+4)+:2]),
.DIB(fifo_in_data[((i*6)+2)+:2]),
.DIC(fifo_in_data[((i*6)+0)+:2]),
.DID(2'b0),
.ADDRA(tail_ns),
.ADDRB(tail_ns),
.ADDRC(tail_ns),
.ADDRD(head_r),
.WE(1'b1),
.WCLK(clk)
);
end // block: fifo_ram
reg [RAM_WIDTH-1:0] fifo_out_data_r;
always @(posedge clk) fifo_out_data_r <= #TCQ fifo_out_data_ns;
// When ECC is ON, most of the FIFO output is delayed
// by one state.
if (ECC == "OFF") begin
reg periodic_rd;
always @(/*AS*/phy_rddata_valid or fifo_out_data_r) begin
{rd_data_end,
periodic_rd,
rd_data_addr,
rd_data_offset} = fifo_out_data_r[FIFO_WIDTH-1:0];
ecc_err_addr = {MC_ERR_ADDR_WIDTH{1'b0}};
rd_data_en = phy_rddata_valid && ~periodic_rd;
ecc_status_valid = 1'b0;
wr_ecc_buf = 1'b0;
end
assign rd_rmw = 1'b0;
end
else begin
wire rd_data_end_ns;
wire periodic_rd;
wire [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr_ns;
wire [DATA_BUF_OFFSET_WIDTH-1:0] rd_data_offset_ns;
wire [MC_ERR_ADDR_WIDTH-1:0] ecc_err_addr_ns;
assign {rd_data_end_ns,
periodic_rd,
rd_data_addr_ns,
rd_data_offset_ns,
rd_rmw,
ecc_err_addr_ns[DATA_BUF_OFFSET_WIDTH+:MC_ERR_LINE_WIDTH]} =
{fifo_out_data_r[FIFO_WIDTH-1:0]};
assign ecc_err_addr_ns[0+:DATA_BUF_OFFSET_WIDTH] = rd_data_offset_ns;
always @(posedge clk) rd_data_end <= #TCQ rd_data_end_ns;
always @(posedge clk) rd_data_addr <= #TCQ rd_data_addr_ns;
always @(posedge clk) rd_data_offset <= #TCQ rd_data_offset_ns;
always @(posedge clk) ecc_err_addr <= #TCQ ecc_err_addr_ns;
wire rd_data_en_ns = phy_rddata_valid && ~(periodic_rd || rd_rmw);
always @(posedge clk) rd_data_en <= rd_data_en_ns;
wire ecc_status_valid_ns = phy_rddata_valid && ~periodic_rd;
always @(posedge clk) ecc_status_valid <= #TCQ ecc_status_valid_ns;
wire wr_ecc_buf_ns = phy_rddata_valid && ~periodic_rd && rd_rmw;
always @(posedge clk) wr_ecc_buf <= #TCQ wr_ecc_buf_ns;
end
end
endgenerate
endmodule
|
// niosii.v
// Generated using ACDS version 15.1 185
`timescale 1 ps / 1 ps
module niosii (
input wire clk_clk, // clk.clk
output wire [1:0] ip_pwm_dir, // ip_pwm.dir
output wire [1:0] ip_pwm_out, // .out
output wire [7:0] pio_0_external_connection_export, // pio_0_external_connection.export
input wire reset_reset_n, // reset.reset_n
input wire uart_0_rxd, // uart_0.rxd
output wire uart_0_txd // .txd
);
wire altpll_0_c0_clk; // altpll_0:c0 -> [irq_mapper:clk, irq_synchronizer:sender_clk, irq_synchronizer_001:sender_clk, irq_synchronizer_002:sender_clk, jtag_uart_0:clk, mm_interconnect_0:altpll_0_c0_clk, nios2_gen2_0:clk, onchip_memory2_0:clk, rst_controller_002:clk]
wire altpll_0_c1_clk; // altpll_0:c1 -> [ip_pwm_0:clock_clk, irq_synchronizer:receiver_clk, mm_interconnect_0:altpll_0_c1_clk, pio_0:clk, rst_controller_001:clk, uart_0:clk]
wire altpll_0_c2_clk; // altpll_0:c2 -> [irq_synchronizer_001:receiver_clk, irq_synchronizer_002:receiver_clk, mm_interconnect_0:altpll_0_c2_clk, rst_controller_003:clk, timer_ms:clk, timer_us:clk]
wire [31:0] nios2_gen2_0_data_master_readdata; // mm_interconnect_0:nios2_gen2_0_data_master_readdata -> nios2_gen2_0:d_readdata
wire nios2_gen2_0_data_master_waitrequest; // mm_interconnect_0:nios2_gen2_0_data_master_waitrequest -> nios2_gen2_0:d_waitrequest
wire nios2_gen2_0_data_master_debugaccess; // nios2_gen2_0:debug_mem_slave_debugaccess_to_roms -> mm_interconnect_0:nios2_gen2_0_data_master_debugaccess
wire [17:0] nios2_gen2_0_data_master_address; // nios2_gen2_0:d_address -> mm_interconnect_0:nios2_gen2_0_data_master_address
wire [3:0] nios2_gen2_0_data_master_byteenable; // nios2_gen2_0:d_byteenable -> mm_interconnect_0:nios2_gen2_0_data_master_byteenable
wire nios2_gen2_0_data_master_read; // nios2_gen2_0:d_read -> mm_interconnect_0:nios2_gen2_0_data_master_read
wire nios2_gen2_0_data_master_write; // nios2_gen2_0:d_write -> mm_interconnect_0:nios2_gen2_0_data_master_write
wire [31:0] nios2_gen2_0_data_master_writedata; // nios2_gen2_0:d_writedata -> mm_interconnect_0:nios2_gen2_0_data_master_writedata
wire [31:0] nios2_gen2_0_instruction_master_readdata; // mm_interconnect_0:nios2_gen2_0_instruction_master_readdata -> nios2_gen2_0:i_readdata
wire nios2_gen2_0_instruction_master_waitrequest; // mm_interconnect_0:nios2_gen2_0_instruction_master_waitrequest -> nios2_gen2_0:i_waitrequest
wire [17:0] nios2_gen2_0_instruction_master_address; // nios2_gen2_0:i_address -> mm_interconnect_0:nios2_gen2_0_instruction_master_address
wire nios2_gen2_0_instruction_master_read; // nios2_gen2_0:i_read -> mm_interconnect_0:nios2_gen2_0_instruction_master_read
wire mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_chipselect; // mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_chipselect -> jtag_uart_0:av_chipselect
wire [31:0] mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_readdata; // jtag_uart_0:av_readdata -> mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_readdata
wire mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_waitrequest; // jtag_uart_0:av_waitrequest -> mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_waitrequest
wire [0:0] mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_address; // mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_address -> jtag_uart_0:av_address
wire mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_read; // mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_read -> jtag_uart_0:av_read_n
wire mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_write; // mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_write -> jtag_uart_0:av_write_n
wire [31:0] mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_writedata; // mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_writedata -> jtag_uart_0:av_writedata
wire [31:0] mm_interconnect_0_ip_pwm_0_avs_s0_readdata; // ip_pwm_0:avs_s0_readdata -> mm_interconnect_0:ip_pwm_0_avs_s0_readdata
wire mm_interconnect_0_ip_pwm_0_avs_s0_waitrequest; // ip_pwm_0:avs_s0_waitrequest -> mm_interconnect_0:ip_pwm_0_avs_s0_waitrequest
wire [7:0] mm_interconnect_0_ip_pwm_0_avs_s0_address; // mm_interconnect_0:ip_pwm_0_avs_s0_address -> ip_pwm_0:avs_s0_address
wire mm_interconnect_0_ip_pwm_0_avs_s0_read; // mm_interconnect_0:ip_pwm_0_avs_s0_read -> ip_pwm_0:avs_s0_read
wire mm_interconnect_0_ip_pwm_0_avs_s0_write; // mm_interconnect_0:ip_pwm_0_avs_s0_write -> ip_pwm_0:avs_s0_write
wire [31:0] mm_interconnect_0_ip_pwm_0_avs_s0_writedata; // mm_interconnect_0:ip_pwm_0_avs_s0_writedata -> ip_pwm_0:avs_s0_writedata
wire [31:0] mm_interconnect_0_nios2_gen2_0_debug_mem_slave_readdata; // nios2_gen2_0:debug_mem_slave_readdata -> mm_interconnect_0:nios2_gen2_0_debug_mem_slave_readdata
wire mm_interconnect_0_nios2_gen2_0_debug_mem_slave_waitrequest; // nios2_gen2_0:debug_mem_slave_waitrequest -> mm_interconnect_0:nios2_gen2_0_debug_mem_slave_waitrequest
wire mm_interconnect_0_nios2_gen2_0_debug_mem_slave_debugaccess; // mm_interconnect_0:nios2_gen2_0_debug_mem_slave_debugaccess -> nios2_gen2_0:debug_mem_slave_debugaccess
wire [8:0] mm_interconnect_0_nios2_gen2_0_debug_mem_slave_address; // mm_interconnect_0:nios2_gen2_0_debug_mem_slave_address -> nios2_gen2_0:debug_mem_slave_address
wire mm_interconnect_0_nios2_gen2_0_debug_mem_slave_read; // mm_interconnect_0:nios2_gen2_0_debug_mem_slave_read -> nios2_gen2_0:debug_mem_slave_read
wire [3:0] mm_interconnect_0_nios2_gen2_0_debug_mem_slave_byteenable; // mm_interconnect_0:nios2_gen2_0_debug_mem_slave_byteenable -> nios2_gen2_0:debug_mem_slave_byteenable
wire mm_interconnect_0_nios2_gen2_0_debug_mem_slave_write; // mm_interconnect_0:nios2_gen2_0_debug_mem_slave_write -> nios2_gen2_0:debug_mem_slave_write
wire [31:0] mm_interconnect_0_nios2_gen2_0_debug_mem_slave_writedata; // mm_interconnect_0:nios2_gen2_0_debug_mem_slave_writedata -> nios2_gen2_0:debug_mem_slave_writedata
wire [31:0] mm_interconnect_0_altpll_0_pll_slave_readdata; // altpll_0:readdata -> mm_interconnect_0:altpll_0_pll_slave_readdata
wire [1:0] mm_interconnect_0_altpll_0_pll_slave_address; // mm_interconnect_0:altpll_0_pll_slave_address -> altpll_0:address
wire mm_interconnect_0_altpll_0_pll_slave_read; // mm_interconnect_0:altpll_0_pll_slave_read -> altpll_0:read
wire mm_interconnect_0_altpll_0_pll_slave_write; // mm_interconnect_0:altpll_0_pll_slave_write -> altpll_0:write
wire [31:0] mm_interconnect_0_altpll_0_pll_slave_writedata; // mm_interconnect_0:altpll_0_pll_slave_writedata -> altpll_0:writedata
wire mm_interconnect_0_onchip_memory2_0_s1_chipselect; // mm_interconnect_0:onchip_memory2_0_s1_chipselect -> onchip_memory2_0:chipselect
wire [31:0] mm_interconnect_0_onchip_memory2_0_s1_readdata; // onchip_memory2_0:readdata -> mm_interconnect_0:onchip_memory2_0_s1_readdata
wire [13:0] mm_interconnect_0_onchip_memory2_0_s1_address; // mm_interconnect_0:onchip_memory2_0_s1_address -> onchip_memory2_0:address
wire [3:0] mm_interconnect_0_onchip_memory2_0_s1_byteenable; // mm_interconnect_0:onchip_memory2_0_s1_byteenable -> onchip_memory2_0:byteenable
wire mm_interconnect_0_onchip_memory2_0_s1_write; // mm_interconnect_0:onchip_memory2_0_s1_write -> onchip_memory2_0:write
wire [31:0] mm_interconnect_0_onchip_memory2_0_s1_writedata; // mm_interconnect_0:onchip_memory2_0_s1_writedata -> onchip_memory2_0:writedata
wire mm_interconnect_0_onchip_memory2_0_s1_clken; // mm_interconnect_0:onchip_memory2_0_s1_clken -> onchip_memory2_0:clken
wire mm_interconnect_0_pio_0_s1_chipselect; // mm_interconnect_0:pio_0_s1_chipselect -> pio_0:chipselect
wire [31:0] mm_interconnect_0_pio_0_s1_readdata; // pio_0:readdata -> mm_interconnect_0:pio_0_s1_readdata
wire [1:0] mm_interconnect_0_pio_0_s1_address; // mm_interconnect_0:pio_0_s1_address -> pio_0:address
wire mm_interconnect_0_pio_0_s1_write; // mm_interconnect_0:pio_0_s1_write -> pio_0:write_n
wire [31:0] mm_interconnect_0_pio_0_s1_writedata; // mm_interconnect_0:pio_0_s1_writedata -> pio_0:writedata
wire mm_interconnect_0_uart_0_s1_chipselect; // mm_interconnect_0:uart_0_s1_chipselect -> uart_0:chipselect
wire [15:0] mm_interconnect_0_uart_0_s1_readdata; // uart_0:readdata -> mm_interconnect_0:uart_0_s1_readdata
wire [2:0] mm_interconnect_0_uart_0_s1_address; // mm_interconnect_0:uart_0_s1_address -> uart_0:address
wire mm_interconnect_0_uart_0_s1_read; // mm_interconnect_0:uart_0_s1_read -> uart_0:read_n
wire mm_interconnect_0_uart_0_s1_begintransfer; // mm_interconnect_0:uart_0_s1_begintransfer -> uart_0:begintransfer
wire mm_interconnect_0_uart_0_s1_write; // mm_interconnect_0:uart_0_s1_write -> uart_0:write_n
wire [15:0] mm_interconnect_0_uart_0_s1_writedata; // mm_interconnect_0:uart_0_s1_writedata -> uart_0:writedata
wire mm_interconnect_0_timer_us_s1_chipselect; // mm_interconnect_0:timer_us_s1_chipselect -> timer_us:chipselect
wire [15:0] mm_interconnect_0_timer_us_s1_readdata; // timer_us:readdata -> mm_interconnect_0:timer_us_s1_readdata
wire [2:0] mm_interconnect_0_timer_us_s1_address; // mm_interconnect_0:timer_us_s1_address -> timer_us:address
wire mm_interconnect_0_timer_us_s1_write; // mm_interconnect_0:timer_us_s1_write -> timer_us:write_n
wire [15:0] mm_interconnect_0_timer_us_s1_writedata; // mm_interconnect_0:timer_us_s1_writedata -> timer_us:writedata
wire mm_interconnect_0_timer_ms_s1_chipselect; // mm_interconnect_0:timer_ms_s1_chipselect -> timer_ms:chipselect
wire [15:0] mm_interconnect_0_timer_ms_s1_readdata; // timer_ms:readdata -> mm_interconnect_0:timer_ms_s1_readdata
wire [2:0] mm_interconnect_0_timer_ms_s1_address; // mm_interconnect_0:timer_ms_s1_address -> timer_ms:address
wire mm_interconnect_0_timer_ms_s1_write; // mm_interconnect_0:timer_ms_s1_write -> timer_ms:write_n
wire [15:0] mm_interconnect_0_timer_ms_s1_writedata; // mm_interconnect_0:timer_ms_s1_writedata -> timer_ms:writedata
wire irq_mapper_receiver0_irq; // jtag_uart_0:av_irq -> irq_mapper:receiver0_irq
wire [31:0] nios2_gen2_0_irq_irq; // irq_mapper:sender_irq -> nios2_gen2_0:irq
wire irq_mapper_receiver1_irq; // irq_synchronizer:sender_irq -> irq_mapper:receiver1_irq
wire [0:0] irq_synchronizer_receiver_irq; // uart_0:irq -> irq_synchronizer:receiver_irq
wire irq_mapper_receiver2_irq; // irq_synchronizer_001:sender_irq -> irq_mapper:receiver2_irq
wire [0:0] irq_synchronizer_001_receiver_irq; // timer_us:irq -> irq_synchronizer_001:receiver_irq
wire irq_mapper_receiver3_irq; // irq_synchronizer_002:sender_irq -> irq_mapper:receiver3_irq
wire [0:0] irq_synchronizer_002_receiver_irq; // timer_ms:irq -> irq_synchronizer_002:receiver_irq
wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [altpll_0:reset, mm_interconnect_0:altpll_0_inclk_interface_reset_reset_bridge_in_reset_reset]
wire rst_controller_001_reset_out_reset; // rst_controller_001:reset_out -> [ip_pwm_0:reset_reset, irq_synchronizer:receiver_reset, mm_interconnect_0:ip_pwm_0_reset_reset_bridge_in_reset_reset, pio_0:reset_n, uart_0:reset_n]
wire rst_controller_002_reset_out_reset; // rst_controller_002:reset_out -> [irq_mapper:reset, irq_synchronizer:sender_reset, irq_synchronizer_001:sender_reset, irq_synchronizer_002:sender_reset, jtag_uart_0:rst_n, mm_interconnect_0:nios2_gen2_0_reset_reset_bridge_in_reset_reset, nios2_gen2_0:reset_n, onchip_memory2_0:reset, rst_translator:in_reset]
wire rst_controller_002_reset_out_reset_req; // rst_controller_002:reset_req -> [nios2_gen2_0:reset_req, onchip_memory2_0:reset_req, rst_translator:reset_req_in]
wire rst_controller_003_reset_out_reset; // rst_controller_003:reset_out -> [irq_synchronizer_001:receiver_reset, irq_synchronizer_002:receiver_reset, mm_interconnect_0:timer_us_reset_reset_bridge_in_reset_reset, timer_ms:reset_n, timer_us:reset_n]
niosii_altpll_0 altpll_0 (
.clk (clk_clk), // inclk_interface.clk
.reset (rst_controller_reset_out_reset), // inclk_interface_reset.reset
.read (mm_interconnect_0_altpll_0_pll_slave_read), // pll_slave.read
.write (mm_interconnect_0_altpll_0_pll_slave_write), // .write
.address (mm_interconnect_0_altpll_0_pll_slave_address), // .address
.readdata (mm_interconnect_0_altpll_0_pll_slave_readdata), // .readdata
.writedata (mm_interconnect_0_altpll_0_pll_slave_writedata), // .writedata
.c0 (altpll_0_c0_clk), // c0.clk
.c1 (altpll_0_c1_clk), // c1.clk
.c2 (altpll_0_c2_clk), // c2.clk
.areset (), // areset_conduit.export
.locked (), // locked_conduit.export
.phasedone () // phasedone_conduit.export
);
ip_pwm_top ip_pwm_0 (
.avs_s0_address (mm_interconnect_0_ip_pwm_0_avs_s0_address), // avs_s0.address
.avs_s0_read (mm_interconnect_0_ip_pwm_0_avs_s0_read), // .read
.avs_s0_readdata (mm_interconnect_0_ip_pwm_0_avs_s0_readdata), // .readdata
.avs_s0_write (mm_interconnect_0_ip_pwm_0_avs_s0_write), // .write
.avs_s0_writedata (mm_interconnect_0_ip_pwm_0_avs_s0_writedata), // .writedata
.avs_s0_waitrequest (mm_interconnect_0_ip_pwm_0_avs_s0_waitrequest), // .waitrequest
.clock_clk (altpll_0_c1_clk), // clock.clk
.reset_reset (rst_controller_001_reset_out_reset), // reset.reset
.pwm_dir (ip_pwm_dir), // pwm.dir
.pwm_out (ip_pwm_out) // .out
);
niosii_jtag_uart_0 jtag_uart_0 (
.clk (altpll_0_c0_clk), // clk.clk
.rst_n (~rst_controller_002_reset_out_reset), // reset.reset_n
.av_chipselect (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_chipselect), // avalon_jtag_slave.chipselect
.av_address (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_address), // .address
.av_read_n (~mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_read), // .read_n
.av_readdata (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_readdata), // .readdata
.av_write_n (~mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_write), // .write_n
.av_writedata (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_writedata), // .writedata
.av_waitrequest (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_waitrequest), // .waitrequest
.av_irq (irq_mapper_receiver0_irq) // irq.irq
);
niosii_nios2_gen2_0 nios2_gen2_0 (
.clk (altpll_0_c0_clk), // clk.clk
.reset_n (~rst_controller_002_reset_out_reset), // reset.reset_n
.reset_req (rst_controller_002_reset_out_reset_req), // .reset_req
.d_address (nios2_gen2_0_data_master_address), // data_master.address
.d_byteenable (nios2_gen2_0_data_master_byteenable), // .byteenable
.d_read (nios2_gen2_0_data_master_read), // .read
.d_readdata (nios2_gen2_0_data_master_readdata), // .readdata
.d_waitrequest (nios2_gen2_0_data_master_waitrequest), // .waitrequest
.d_write (nios2_gen2_0_data_master_write), // .write
.d_writedata (nios2_gen2_0_data_master_writedata), // .writedata
.debug_mem_slave_debugaccess_to_roms (nios2_gen2_0_data_master_debugaccess), // .debugaccess
.i_address (nios2_gen2_0_instruction_master_address), // instruction_master.address
.i_read (nios2_gen2_0_instruction_master_read), // .read
.i_readdata (nios2_gen2_0_instruction_master_readdata), // .readdata
.i_waitrequest (nios2_gen2_0_instruction_master_waitrequest), // .waitrequest
.irq (nios2_gen2_0_irq_irq), // irq.irq
.debug_reset_request (), // debug_reset_request.reset
.debug_mem_slave_address (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_address), // debug_mem_slave.address
.debug_mem_slave_byteenable (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_byteenable), // .byteenable
.debug_mem_slave_debugaccess (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_debugaccess), // .debugaccess
.debug_mem_slave_read (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_read), // .read
.debug_mem_slave_readdata (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_readdata), // .readdata
.debug_mem_slave_waitrequest (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_waitrequest), // .waitrequest
.debug_mem_slave_write (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_write), // .write
.debug_mem_slave_writedata (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_writedata), // .writedata
.dummy_ci_port () // custom_instruction_master.readra
);
niosii_onchip_memory2_0 onchip_memory2_0 (
.clk (altpll_0_c0_clk), // clk1.clk
.address (mm_interconnect_0_onchip_memory2_0_s1_address), // s1.address
.clken (mm_interconnect_0_onchip_memory2_0_s1_clken), // .clken
.chipselect (mm_interconnect_0_onchip_memory2_0_s1_chipselect), // .chipselect
.write (mm_interconnect_0_onchip_memory2_0_s1_write), // .write
.readdata (mm_interconnect_0_onchip_memory2_0_s1_readdata), // .readdata
.writedata (mm_interconnect_0_onchip_memory2_0_s1_writedata), // .writedata
.byteenable (mm_interconnect_0_onchip_memory2_0_s1_byteenable), // .byteenable
.reset (rst_controller_002_reset_out_reset), // reset1.reset
.reset_req (rst_controller_002_reset_out_reset_req) // .reset_req
);
niosii_pio_0 pio_0 (
.clk (altpll_0_c1_clk), // clk.clk
.reset_n (~rst_controller_001_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_pio_0_s1_address), // s1.address
.write_n (~mm_interconnect_0_pio_0_s1_write), // .write_n
.writedata (mm_interconnect_0_pio_0_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_pio_0_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_pio_0_s1_readdata), // .readdata
.out_port (pio_0_external_connection_export) // external_connection.export
);
niosii_timer_ms timer_ms (
.clk (altpll_0_c2_clk), // clk.clk
.reset_n (~rst_controller_003_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_timer_ms_s1_address), // s1.address
.writedata (mm_interconnect_0_timer_ms_s1_writedata), // .writedata
.readdata (mm_interconnect_0_timer_ms_s1_readdata), // .readdata
.chipselect (mm_interconnect_0_timer_ms_s1_chipselect), // .chipselect
.write_n (~mm_interconnect_0_timer_ms_s1_write), // .write_n
.irq (irq_synchronizer_002_receiver_irq) // irq.irq
);
niosii_timer_us timer_us (
.clk (altpll_0_c2_clk), // clk.clk
.reset_n (~rst_controller_003_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_timer_us_s1_address), // s1.address
.writedata (mm_interconnect_0_timer_us_s1_writedata), // .writedata
.readdata (mm_interconnect_0_timer_us_s1_readdata), // .readdata
.chipselect (mm_interconnect_0_timer_us_s1_chipselect), // .chipselect
.write_n (~mm_interconnect_0_timer_us_s1_write), // .write_n
.irq (irq_synchronizer_001_receiver_irq) // irq.irq
);
niosii_uart_0 uart_0 (
.clk (altpll_0_c1_clk), // clk.clk
.reset_n (~rst_controller_001_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_uart_0_s1_address), // s1.address
.begintransfer (mm_interconnect_0_uart_0_s1_begintransfer), // .begintransfer
.chipselect (mm_interconnect_0_uart_0_s1_chipselect), // .chipselect
.read_n (~mm_interconnect_0_uart_0_s1_read), // .read_n
.write_n (~mm_interconnect_0_uart_0_s1_write), // .write_n
.writedata (mm_interconnect_0_uart_0_s1_writedata), // .writedata
.readdata (mm_interconnect_0_uart_0_s1_readdata), // .readdata
.dataavailable (), // .dataavailable
.readyfordata (), // .readyfordata
.rxd (uart_0_rxd), // external_connection.export
.txd (uart_0_txd), // .export
.irq (irq_synchronizer_receiver_irq) // irq.irq
);
niosii_mm_interconnect_0 mm_interconnect_0 (
.altpll_0_c0_clk (altpll_0_c0_clk), // altpll_0_c0.clk
.altpll_0_c1_clk (altpll_0_c1_clk), // altpll_0_c1.clk
.altpll_0_c2_clk (altpll_0_c2_clk), // altpll_0_c2.clk
.clk_0_clk_clk (clk_clk), // clk_0_clk.clk
.altpll_0_inclk_interface_reset_reset_bridge_in_reset_reset (rst_controller_reset_out_reset), // altpll_0_inclk_interface_reset_reset_bridge_in_reset.reset
.ip_pwm_0_reset_reset_bridge_in_reset_reset (rst_controller_001_reset_out_reset), // ip_pwm_0_reset_reset_bridge_in_reset.reset
.nios2_gen2_0_reset_reset_bridge_in_reset_reset (rst_controller_002_reset_out_reset), // nios2_gen2_0_reset_reset_bridge_in_reset.reset
.timer_us_reset_reset_bridge_in_reset_reset (rst_controller_003_reset_out_reset), // timer_us_reset_reset_bridge_in_reset.reset
.nios2_gen2_0_data_master_address (nios2_gen2_0_data_master_address), // nios2_gen2_0_data_master.address
.nios2_gen2_0_data_master_waitrequest (nios2_gen2_0_data_master_waitrequest), // .waitrequest
.nios2_gen2_0_data_master_byteenable (nios2_gen2_0_data_master_byteenable), // .byteenable
.nios2_gen2_0_data_master_read (nios2_gen2_0_data_master_read), // .read
.nios2_gen2_0_data_master_readdata (nios2_gen2_0_data_master_readdata), // .readdata
.nios2_gen2_0_data_master_write (nios2_gen2_0_data_master_write), // .write
.nios2_gen2_0_data_master_writedata (nios2_gen2_0_data_master_writedata), // .writedata
.nios2_gen2_0_data_master_debugaccess (nios2_gen2_0_data_master_debugaccess), // .debugaccess
.nios2_gen2_0_instruction_master_address (nios2_gen2_0_instruction_master_address), // nios2_gen2_0_instruction_master.address
.nios2_gen2_0_instruction_master_waitrequest (nios2_gen2_0_instruction_master_waitrequest), // .waitrequest
.nios2_gen2_0_instruction_master_read (nios2_gen2_0_instruction_master_read), // .read
.nios2_gen2_0_instruction_master_readdata (nios2_gen2_0_instruction_master_readdata), // .readdata
.altpll_0_pll_slave_address (mm_interconnect_0_altpll_0_pll_slave_address), // altpll_0_pll_slave.address
.altpll_0_pll_slave_write (mm_interconnect_0_altpll_0_pll_slave_write), // .write
.altpll_0_pll_slave_read (mm_interconnect_0_altpll_0_pll_slave_read), // .read
.altpll_0_pll_slave_readdata (mm_interconnect_0_altpll_0_pll_slave_readdata), // .readdata
.altpll_0_pll_slave_writedata (mm_interconnect_0_altpll_0_pll_slave_writedata), // .writedata
.ip_pwm_0_avs_s0_address (mm_interconnect_0_ip_pwm_0_avs_s0_address), // ip_pwm_0_avs_s0.address
.ip_pwm_0_avs_s0_write (mm_interconnect_0_ip_pwm_0_avs_s0_write), // .write
.ip_pwm_0_avs_s0_read (mm_interconnect_0_ip_pwm_0_avs_s0_read), // .read
.ip_pwm_0_avs_s0_readdata (mm_interconnect_0_ip_pwm_0_avs_s0_readdata), // .readdata
.ip_pwm_0_avs_s0_writedata (mm_interconnect_0_ip_pwm_0_avs_s0_writedata), // .writedata
.ip_pwm_0_avs_s0_waitrequest (mm_interconnect_0_ip_pwm_0_avs_s0_waitrequest), // .waitrequest
.jtag_uart_0_avalon_jtag_slave_address (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_address), // jtag_uart_0_avalon_jtag_slave.address
.jtag_uart_0_avalon_jtag_slave_write (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_write), // .write
.jtag_uart_0_avalon_jtag_slave_read (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_read), // .read
.jtag_uart_0_avalon_jtag_slave_readdata (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_readdata), // .readdata
.jtag_uart_0_avalon_jtag_slave_writedata (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_writedata), // .writedata
.jtag_uart_0_avalon_jtag_slave_waitrequest (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_waitrequest), // .waitrequest
.jtag_uart_0_avalon_jtag_slave_chipselect (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_chipselect), // .chipselect
.nios2_gen2_0_debug_mem_slave_address (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_address), // nios2_gen2_0_debug_mem_slave.address
.nios2_gen2_0_debug_mem_slave_write (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_write), // .write
.nios2_gen2_0_debug_mem_slave_read (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_read), // .read
.nios2_gen2_0_debug_mem_slave_readdata (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_readdata), // .readdata
.nios2_gen2_0_debug_mem_slave_writedata (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_writedata), // .writedata
.nios2_gen2_0_debug_mem_slave_byteenable (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_byteenable), // .byteenable
.nios2_gen2_0_debug_mem_slave_waitrequest (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_waitrequest), // .waitrequest
.nios2_gen2_0_debug_mem_slave_debugaccess (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_debugaccess), // .debugaccess
.onchip_memory2_0_s1_address (mm_interconnect_0_onchip_memory2_0_s1_address), // onchip_memory2_0_s1.address
.onchip_memory2_0_s1_write (mm_interconnect_0_onchip_memory2_0_s1_write), // .write
.onchip_memory2_0_s1_readdata (mm_interconnect_0_onchip_memory2_0_s1_readdata), // .readdata
.onchip_memory2_0_s1_writedata (mm_interconnect_0_onchip_memory2_0_s1_writedata), // .writedata
.onchip_memory2_0_s1_byteenable (mm_interconnect_0_onchip_memory2_0_s1_byteenable), // .byteenable
.onchip_memory2_0_s1_chipselect (mm_interconnect_0_onchip_memory2_0_s1_chipselect), // .chipselect
.onchip_memory2_0_s1_clken (mm_interconnect_0_onchip_memory2_0_s1_clken), // .clken
.pio_0_s1_address (mm_interconnect_0_pio_0_s1_address), // pio_0_s1.address
.pio_0_s1_write (mm_interconnect_0_pio_0_s1_write), // .write
.pio_0_s1_readdata (mm_interconnect_0_pio_0_s1_readdata), // .readdata
.pio_0_s1_writedata (mm_interconnect_0_pio_0_s1_writedata), // .writedata
.pio_0_s1_chipselect (mm_interconnect_0_pio_0_s1_chipselect), // .chipselect
.timer_ms_s1_address (mm_interconnect_0_timer_ms_s1_address), // timer_ms_s1.address
.timer_ms_s1_write (mm_interconnect_0_timer_ms_s1_write), // .write
.timer_ms_s1_readdata (mm_interconnect_0_timer_ms_s1_readdata), // .readdata
.timer_ms_s1_writedata (mm_interconnect_0_timer_ms_s1_writedata), // .writedata
.timer_ms_s1_chipselect (mm_interconnect_0_timer_ms_s1_chipselect), // .chipselect
.timer_us_s1_address (mm_interconnect_0_timer_us_s1_address), // timer_us_s1.address
.timer_us_s1_write (mm_interconnect_0_timer_us_s1_write), // .write
.timer_us_s1_readdata (mm_interconnect_0_timer_us_s1_readdata), // .readdata
.timer_us_s1_writedata (mm_interconnect_0_timer_us_s1_writedata), // .writedata
.timer_us_s1_chipselect (mm_interconnect_0_timer_us_s1_chipselect), // .chipselect
.uart_0_s1_address (mm_interconnect_0_uart_0_s1_address), // uart_0_s1.address
.uart_0_s1_write (mm_interconnect_0_uart_0_s1_write), // .write
.uart_0_s1_read (mm_interconnect_0_uart_0_s1_read), // .read
.uart_0_s1_readdata (mm_interconnect_0_uart_0_s1_readdata), // .readdata
.uart_0_s1_writedata (mm_interconnect_0_uart_0_s1_writedata), // .writedata
.uart_0_s1_begintransfer (mm_interconnect_0_uart_0_s1_begintransfer), // .begintransfer
.uart_0_s1_chipselect (mm_interconnect_0_uart_0_s1_chipselect) // .chipselect
);
niosii_irq_mapper irq_mapper (
.clk (altpll_0_c0_clk), // clk.clk
.reset (rst_controller_002_reset_out_reset), // clk_reset.reset
.receiver0_irq (irq_mapper_receiver0_irq), // receiver0.irq
.receiver1_irq (irq_mapper_receiver1_irq), // receiver1.irq
.receiver2_irq (irq_mapper_receiver2_irq), // receiver2.irq
.receiver3_irq (irq_mapper_receiver3_irq), // receiver3.irq
.sender_irq (nios2_gen2_0_irq_irq) // sender.irq
);
altera_irq_clock_crosser #(
.IRQ_WIDTH (1)
) irq_synchronizer (
.receiver_clk (altpll_0_c1_clk), // receiver_clk.clk
.sender_clk (altpll_0_c0_clk), // sender_clk.clk
.receiver_reset (rst_controller_001_reset_out_reset), // receiver_clk_reset.reset
.sender_reset (rst_controller_002_reset_out_reset), // sender_clk_reset.reset
.receiver_irq (irq_synchronizer_receiver_irq), // receiver.irq
.sender_irq (irq_mapper_receiver1_irq) // sender.irq
);
altera_irq_clock_crosser #(
.IRQ_WIDTH (1)
) irq_synchronizer_001 (
.receiver_clk (altpll_0_c2_clk), // receiver_clk.clk
.sender_clk (altpll_0_c0_clk), // sender_clk.clk
.receiver_reset (rst_controller_003_reset_out_reset), // receiver_clk_reset.reset
.sender_reset (rst_controller_002_reset_out_reset), // sender_clk_reset.reset
.receiver_irq (irq_synchronizer_001_receiver_irq), // receiver.irq
.sender_irq (irq_mapper_receiver2_irq) // sender.irq
);
altera_irq_clock_crosser #(
.IRQ_WIDTH (1)
) irq_synchronizer_002 (
.receiver_clk (altpll_0_c2_clk), // receiver_clk.clk
.sender_clk (altpll_0_c0_clk), // sender_clk.clk
.receiver_reset (rst_controller_003_reset_out_reset), // receiver_clk_reset.reset
.sender_reset (rst_controller_002_reset_out_reset), // sender_clk_reset.reset
.receiver_irq (irq_synchronizer_002_receiver_irq), // receiver.irq
.sender_irq (irq_mapper_receiver3_irq) // sender.irq
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller (
.reset_in0 (~reset_reset_n), // reset_in0.reset
.clk (clk_clk), // clk.clk
.reset_out (rst_controller_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller_001 (
.reset_in0 (~reset_reset_n), // reset_in0.reset
.clk (altpll_0_c1_clk), // clk.clk
.reset_out (rst_controller_001_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (1),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller_002 (
.reset_in0 (~reset_reset_n), // reset_in0.reset
.clk (altpll_0_c0_clk), // clk.clk
.reset_out (rst_controller_002_reset_out_reset), // reset_out.reset
.reset_req (rst_controller_002_reset_out_reset_req), // .reset_req
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller_003 (
.reset_in0 (~reset_reset_n), // reset_in0.reset
.clk (altpll_0_c2_clk), // clk.clk
.reset_out (rst_controller_003_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
endmodule
|
//
// Generated by Bluespec Compiler, version 2013.01.beta1 (build 30202, 2013-01-08)
//
// On Tue Jan 22 07:12:41 EST 2013
//
//
// Ports:
// Name I/O size props
// host_request_get O 8 reg
// RDY_host_request_get O 1 reg
// RDY_host_response_put O 1 reg
// CLK I 1 clock
// RST_N I 1 reset
// host_response_put I 8 reg
// EN_host_response_put I 1
// EN_host_request_get I 1
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkSimIO(CLK,
RST_N,
EN_host_request_get,
host_request_get,
RDY_host_request_get,
host_response_put,
EN_host_response_put,
RDY_host_response_put);
input CLK;
input RST_N;
// actionvalue method host_request_get
input EN_host_request_get;
output [7 : 0] host_request_get;
output RDY_host_request_get;
// action method host_response_put
input [7 : 0] host_response_put;
input EN_host_response_put;
output RDY_host_response_put;
// signals for module outputs
wire [7 : 0] host_request_get;
wire RDY_host_request_get, RDY_host_response_put;
// inlined wires
wire [15 : 0] dcpCredit_acc_v1$wget,
dcpCredit_acc_v2$wget,
spinCredit_acc_v1$wget,
spinCredit_acc_v2$wget;
wire dcpCredit_acc_v1$whas,
dcpCredit_acc_v2$whas,
spinCredit_acc_v1$whas,
spinCredit_acc_v2$whas;
// register cp2hByteCount
reg [31 : 0] cp2hByteCount;
wire [31 : 0] cp2hByteCount$D_IN;
wire cp2hByteCount$EN;
// register dcpCredit_value
reg [15 : 0] dcpCredit_value;
wire [15 : 0] dcpCredit_value$D_IN;
wire dcpCredit_value$EN;
// register doTerminate
reg doTerminate;
wire doTerminate$D_IN, doTerminate$EN;
// register h2cpByteCount
reg [31 : 0] h2cpByteCount;
wire [31 : 0] h2cpByteCount$D_IN;
wire h2cpByteCount$EN;
// register h2ioByteCount
reg [31 : 0] h2ioByteCount;
wire [31 : 0] h2ioByteCount$D_IN;
wire h2ioByteCount$EN;
// register ioOpcode
reg [7 : 0] ioOpcode;
wire [7 : 0] ioOpcode$D_IN;
wire ioOpcode$EN;
// register isOpcode
reg isOpcode;
wire isOpcode$D_IN, isOpcode$EN;
// register r_hdl
reg [32 : 0] r_hdl;
wire [32 : 0] r_hdl$D_IN;
wire r_hdl$EN;
// register s_hdl
reg [32 : 0] s_hdl;
wire [32 : 0] s_hdl$D_IN;
wire s_hdl$EN;
// register spinCredit_value
reg [15 : 0] spinCredit_value;
wire [15 : 0] spinCredit_value$D_IN;
wire spinCredit_value$EN;
// register w_hdl
reg [32 : 0] w_hdl;
wire [32 : 0] w_hdl$D_IN;
wire w_hdl$EN;
// ports of submodule reqF
wire [7 : 0] reqF$D_IN, reqF$D_OUT;
wire reqF$CLR, reqF$DEQ, reqF$EMPTY_N, reqF$ENQ, reqF$FULL_N;
// ports of submodule respF
wire [7 : 0] respF$D_IN, respF$D_OUT;
wire respF$CLR, respF$DEQ, respF$EMPTY_N, respF$ENQ, respF$FULL_N;
// rule scheduling signals
wire WILL_FIRE_RL_do_r_char,
WILL_FIRE_RL_do_r_open,
WILL_FIRE_RL_do_s_char,
WILL_FIRE_RL_do_s_open,
WILL_FIRE_RL_do_w_char;
// inputs to muxes for submodule ports
wire [32 : 0] MUX_r_hdl$write_1__VAL_2, MUX_s_hdl$write_1__VAL_2;
wire [15 : 0] MUX_dcpCredit_value$write_1__VAL_2,
MUX_spinCredit_value$write_1__VAL_2;
wire MUX_r_hdl$write_1__SEL_1, MUX_s_hdl$write_1__SEL_1;
// remaining internal signals
reg [63 : 0] v__h1534,
v__h1822,
v__h2056,
v__h2264,
v__h2612,
v__h2635,
v__h2839,
v__h3347,
v__h3388,
v__h3431,
v__h3474;
reg [31 : 0] TASK_fopen___d24,
TASK_fopen___d31,
TASK_fopen___d38,
b__h2103,
b__h2688;
wire [15 : 0] b__h1081, b__h824;
// actionvalue method host_request_get
assign host_request_get = reqF$D_OUT ;
assign RDY_host_request_get = reqF$EMPTY_N ;
// action method host_response_put
assign RDY_host_response_put = respF$FULL_N ;
// submodule reqF
FIFO2 #(.width(32'd8), .guarded(32'd1)) reqF(.RST(RST_N),
.CLK(CLK),
.D_IN(reqF$D_IN),
.ENQ(reqF$ENQ),
.DEQ(reqF$DEQ),
.CLR(reqF$CLR),
.D_OUT(reqF$D_OUT),
.FULL_N(reqF$FULL_N),
.EMPTY_N(reqF$EMPTY_N));
// submodule respF
FIFO2 #(.width(32'd8), .guarded(32'd1)) respF(.RST(RST_N),
.CLK(CLK),
.D_IN(respF$D_IN),
.ENQ(respF$ENQ),
.DEQ(respF$DEQ),
.CLR(respF$CLR),
.D_OUT(respF$D_OUT),
.FULL_N(respF$FULL_N),
.EMPTY_N(respF$EMPTY_N));
// rule RL_do_r_open
assign WILL_FIRE_RL_do_r_open = !r_hdl[32] && s_hdl[32] ;
// rule RL_do_s_char
assign WILL_FIRE_RL_do_s_char = s_hdl[32] && spinCredit_value == 16'd0 ;
// rule RL_do_r_char
assign WILL_FIRE_RL_do_r_char =
reqF$FULL_N && r_hdl[32] &&
(dcpCredit_value ^ 16'h8000) > 16'd32768 ;
// rule RL_do_w_char
assign WILL_FIRE_RL_do_w_char = respF$EMPTY_N && w_hdl[32] ;
// rule RL_do_s_open
assign WILL_FIRE_RL_do_s_open = !s_hdl[32] && w_hdl[32] ;
// inputs to muxes for submodule ports
assign MUX_r_hdl$write_1__SEL_1 =
WILL_FIRE_RL_do_r_char && b__h2688 == 32'hFFFFFFFF ;
assign MUX_s_hdl$write_1__SEL_1 =
WILL_FIRE_RL_do_s_char && b__h2103 == 32'hFFFFFFFF ;
assign MUX_dcpCredit_value$write_1__VAL_2 =
dcpCredit_value + (dcpCredit_acc_v1$whas ? b__h1081 : 16'd0) +
(dcpCredit_acc_v2$whas ? 16'd65535 : 16'd0) ;
assign MUX_r_hdl$write_1__VAL_2 = { 1'd1, TASK_fopen___d38 } ;
assign MUX_s_hdl$write_1__VAL_2 = { 1'd1, TASK_fopen___d31 } ;
assign MUX_spinCredit_value$write_1__VAL_2 =
spinCredit_value + (spinCredit_acc_v1$whas ? b__h824 : 16'd0) +
(spinCredit_acc_v2$whas ? 16'd65535 : 16'd0) ;
// inlined wires
assign spinCredit_acc_v1$wget = b__h824 ;
assign spinCredit_acc_v1$whas =
WILL_FIRE_RL_do_s_char && b__h2103 != 32'hFFFFFFFF &&
!isOpcode &&
ioOpcode == 8'd0 ;
assign spinCredit_acc_v2$wget = 16'd65535 ;
assign spinCredit_acc_v2$whas = (spinCredit_value ^ 16'h8000) > 16'd32768 ;
assign dcpCredit_acc_v1$wget = b__h824 ;
assign dcpCredit_acc_v1$whas =
WILL_FIRE_RL_do_s_char && b__h2103 != 32'hFFFFFFFF &&
!isOpcode &&
ioOpcode == 8'd1 ;
assign dcpCredit_acc_v2$wget = 16'd65535 ;
assign dcpCredit_acc_v2$whas =
WILL_FIRE_RL_do_r_char && b__h2688 != 32'hFFFFFFFF ;
// register cp2hByteCount
assign cp2hByteCount$D_IN = cp2hByteCount + 32'd1 ;
assign cp2hByteCount$EN = WILL_FIRE_RL_do_w_char ;
// register dcpCredit_value
assign dcpCredit_value$D_IN =
WILL_FIRE_RL_do_s_open ?
16'd0 :
MUX_dcpCredit_value$write_1__VAL_2 ;
assign dcpCredit_value$EN = 1'b1 ;
// register doTerminate
assign doTerminate$D_IN = 1'd1 ;
assign doTerminate$EN =
WILL_FIRE_RL_do_s_char && b__h2103 != 32'hFFFFFFFF &&
!isOpcode &&
ioOpcode == 8'd255 ;
// register h2cpByteCount
assign h2cpByteCount$D_IN = h2cpByteCount + 32'd1 ;
assign h2cpByteCount$EN = dcpCredit_acc_v2$whas ;
// register h2ioByteCount
assign h2ioByteCount$D_IN = h2ioByteCount + 32'd1 ;
assign h2ioByteCount$EN =
WILL_FIRE_RL_do_s_char && b__h2103 != 32'hFFFFFFFF ;
// register ioOpcode
assign ioOpcode$D_IN = b__h2103[7:0] ;
assign ioOpcode$EN =
WILL_FIRE_RL_do_s_char && b__h2103 != 32'hFFFFFFFF && isOpcode ;
// register isOpcode
assign isOpcode$D_IN = !isOpcode ;
assign isOpcode$EN = WILL_FIRE_RL_do_s_char && b__h2103 != 32'hFFFFFFFF ;
// register r_hdl
assign r_hdl$D_IN =
MUX_r_hdl$write_1__SEL_1 ?
33'h0AAAAAAAA :
MUX_r_hdl$write_1__VAL_2 ;
assign r_hdl$EN =
WILL_FIRE_RL_do_r_char && b__h2688 == 32'hFFFFFFFF ||
WILL_FIRE_RL_do_r_open ;
// register s_hdl
assign s_hdl$D_IN =
MUX_s_hdl$write_1__SEL_1 ?
33'h0AAAAAAAA :
MUX_s_hdl$write_1__VAL_2 ;
assign s_hdl$EN =
WILL_FIRE_RL_do_s_char && b__h2103 == 32'hFFFFFFFF ||
WILL_FIRE_RL_do_s_open ;
// register spinCredit_value
assign spinCredit_value$D_IN =
WILL_FIRE_RL_do_s_open ?
16'd2 :
MUX_spinCredit_value$write_1__VAL_2 ;
assign spinCredit_value$EN = 1'b1 ;
// register w_hdl
assign w_hdl$D_IN = { 1'd1, TASK_fopen___d24 } ;
assign w_hdl$EN = !w_hdl[32] ;
// submodule reqF
assign reqF$D_IN = b__h2688[7:0] ;
assign reqF$ENQ = dcpCredit_acc_v2$whas ;
assign reqF$DEQ = EN_host_request_get ;
assign reqF$CLR = 1'b0 ;
// submodule respF
assign respF$D_IN = host_response_put ;
assign respF$ENQ = EN_host_response_put ;
assign respF$DEQ = WILL_FIRE_RL_do_w_char ;
assign respF$CLR = 1'b0 ;
// remaining internal signals
assign b__h1081 = b__h824 ;
assign b__h824 = { 8'd0, b__h2103[7:0] } ;
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
cp2hByteCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
dcpCredit_value <= `BSV_ASSIGNMENT_DELAY 16'd0;
doTerminate <= `BSV_ASSIGNMENT_DELAY 1'd0;
h2cpByteCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
h2ioByteCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
isOpcode <= `BSV_ASSIGNMENT_DELAY 1'd1;
r_hdl <= `BSV_ASSIGNMENT_DELAY 33'h0AAAAAAAA;
s_hdl <= `BSV_ASSIGNMENT_DELAY 33'h0AAAAAAAA;
spinCredit_value <= `BSV_ASSIGNMENT_DELAY 16'd0;
w_hdl <= `BSV_ASSIGNMENT_DELAY 33'h0AAAAAAAA;
end
else
begin
if (cp2hByteCount$EN)
cp2hByteCount <= `BSV_ASSIGNMENT_DELAY cp2hByteCount$D_IN;
if (dcpCredit_value$EN)
dcpCredit_value <= `BSV_ASSIGNMENT_DELAY dcpCredit_value$D_IN;
if (doTerminate$EN)
doTerminate <= `BSV_ASSIGNMENT_DELAY doTerminate$D_IN;
if (h2cpByteCount$EN)
h2cpByteCount <= `BSV_ASSIGNMENT_DELAY h2cpByteCount$D_IN;
if (h2ioByteCount$EN)
h2ioByteCount <= `BSV_ASSIGNMENT_DELAY h2ioByteCount$D_IN;
if (isOpcode$EN) isOpcode <= `BSV_ASSIGNMENT_DELAY isOpcode$D_IN;
if (r_hdl$EN) r_hdl <= `BSV_ASSIGNMENT_DELAY r_hdl$D_IN;
if (s_hdl$EN) s_hdl <= `BSV_ASSIGNMENT_DELAY s_hdl$D_IN;
if (spinCredit_value$EN)
spinCredit_value <= `BSV_ASSIGNMENT_DELAY spinCredit_value$D_IN;
if (w_hdl$EN) w_hdl <= `BSV_ASSIGNMENT_DELAY w_hdl$D_IN;
end
if (ioOpcode$EN) ioOpcode <= `BSV_ASSIGNMENT_DELAY ioOpcode$D_IN;
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
cp2hByteCount = 32'hAAAAAAAA;
dcpCredit_value = 16'hAAAA;
doTerminate = 1'h0;
h2cpByteCount = 32'hAAAAAAAA;
h2ioByteCount = 32'hAAAAAAAA;
ioOpcode = 8'hAA;
isOpcode = 1'h0;
r_hdl = 33'h0AAAAAAAA;
s_hdl = 33'h0AAAAAAAA;
spinCredit_value = 16'hAAAA;
w_hdl = 33'h0AAAAAAAA;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge CLK)
begin
#0;
if (RST_N != `BSV_RESET_VALUE)
if (!w_hdl[32])
begin
TASK_fopen___d24 = $fopen("/tmp/OpenCPI0_Resp", "w");
#0;
end
if (RST_N != `BSV_RESET_VALUE)
if (!w_hdl[32])
begin
v__h1534 = $time;
#0;
end
if (RST_N != `BSV_RESET_VALUE)
if (!w_hdl[32]) $display("[%0d]: do_w_open called", v__h1534);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_do_r_open)
begin
TASK_fopen___d38 = $fopen("/tmp/OpenCPI0_Req", "r");
#0;
end
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_do_r_open)
begin
v__h2056 = $time;
#0;
end
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_do_r_open)
$display("[%0d]: do_r_open called", v__h2056);
if (RST_N != `BSV_RESET_VALUE)
if (doTerminate)
begin
v__h3347 = $time;
#0;
end
if (RST_N != `BSV_RESET_VALUE)
if (doTerminate)
$display("[%0d]: doTerminate called by IOCTL channel", v__h3347);
if (RST_N != `BSV_RESET_VALUE)
if (doTerminate)
begin
v__h3388 = $time;
#0;
end
if (RST_N != `BSV_RESET_VALUE)
if (doTerminate)
$display("[%0d]: IOCTL Bytes Read :%0d", v__h3388, h2ioByteCount);
if (RST_N != `BSV_RESET_VALUE)
if (doTerminate)
begin
v__h3431 = $time;
#0;
end
if (RST_N != `BSV_RESET_VALUE)
if (doTerminate)
$display("[%0d]: DCP Bytes Read :%0d", v__h3431, h2cpByteCount);
if (RST_N != `BSV_RESET_VALUE)
if (doTerminate)
begin
v__h3474 = $time;
#0;
end
if (RST_N != `BSV_RESET_VALUE)
if (doTerminate)
$display("[%0d]: DCP Bytes Written :%0d", v__h3474, cp2hByteCount);
if (RST_N != `BSV_RESET_VALUE) if (doTerminate) $finish(32'd1);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_do_s_char)
begin
b__h2103 = $fgetc(s_hdl[31:0]);
#0;
end
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_do_s_char && b__h2103 == 32'hFFFFFFFF)
begin
v__h2264 = $time;
#0;
end
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_do_s_char && b__h2103 == 32'hFFFFFFFF)
$display("[%0d]: do_s_char IOCTL fgetc returned -1 after %0d Bytes",
v__h2264,
h2ioByteCount);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_do_s_char && b__h2103 == 32'hFFFFFFFF)
$fclose(s_hdl[31:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_do_s_char && b__h2103 != 32'hFFFFFFFF && !isOpcode &&
ioOpcode == 8'd253)
$dumpoff;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_do_s_char && b__h2103 != 32'hFFFFFFFF && !isOpcode &&
ioOpcode == 8'd253)
begin
v__h2612 = $time;
#0;
end
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_do_s_char && b__h2103 != 32'hFFFFFFFF && !isOpcode &&
ioOpcode == 8'd253)
$display("[%0d]: dumpoff called", v__h2612);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_do_s_char && b__h2103 != 32'hFFFFFFFF && !isOpcode &&
ioOpcode == 8'd254)
$dumpon;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_do_s_char && b__h2103 != 32'hFFFFFFFF && !isOpcode &&
ioOpcode == 8'd254)
begin
v__h2635 = $time;
#0;
end
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_do_s_char && b__h2103 != 32'hFFFFFFFF && !isOpcode &&
ioOpcode == 8'd254)
$display("[%0d]: dumpon called", v__h2635);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_do_r_char)
begin
b__h2688 = $fgetc(r_hdl[31:0]);
#0;
end
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_do_r_char && b__h2688 == 32'hFFFFFFFF)
begin
v__h2839 = $time;
#0;
end
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_do_r_char && b__h2688 == 32'hFFFFFFFF)
$display("[%0d]: do_r_char DCP fgetc returned -1 after %0d Bytes",
v__h2839,
h2cpByteCount);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_do_r_char && b__h2688 == 32'hFFFFFFFF)
$fclose(r_hdl[31:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_do_w_char) $fwrite(w_hdl[31:0], "%c", respF$D_OUT);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_do_w_char) $fflush(w_hdl[31:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_do_s_open)
begin
TASK_fopen___d31 = $fopen("/tmp/OpenCPI0_IOCtl", "r");
#0;
end
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_do_s_open)
begin
v__h1822 = $time;
#0;
end
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_do_s_open)
$display("[%0d]: do_s_open called", v__h1822);
end
// synopsys translate_on
endmodule // mkSimIO
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLRTN_1_V
`define SKY130_FD_SC_LS__DLRTN_1_V
/**
* dlrtn: Delay latch, inverted reset, inverted enable, single output.
*
* Verilog wrapper for dlrtn with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__dlrtn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__dlrtn_1 (
Q ,
RESET_B,
D ,
GATE_N ,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input RESET_B;
input D ;
input GATE_N ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_ls__dlrtn base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE_N(GATE_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__dlrtn_1 (
Q ,
RESET_B,
D ,
GATE_N
);
output Q ;
input RESET_B;
input D ;
input GATE_N ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__dlrtn base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE_N(GATE_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLRTN_1_V
|
(************************************************************************)
(* * The Coq Proof Assistant / The Coq Development Team *)
(* v * INRIA, CNRS and contributors - Copyright 1999-2018 *)
(* <O___,, * (see CREDITS file for the list of authors) *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(* * (see LICENSE file for the text of the license) *)
(************************************************************************)
(* This file is (C) Copyright 2006-2015 Microsoft Corporation and Inria. *)
(** #<style> .doc { font-family: monospace; white-space: pre; } </style># **)
Require Bool.
Require Import ssreflect ssrfun.
(**
A theory of boolean predicates and operators. A large part of this file is
concerned with boolean reflection.
Definitions and notations:
is_true b == the coercion of b : bool to Prop (:= b = true).
This is just input and displayed as `b''.
reflect P b == the reflection inductive predicate, asserting
that the logical proposition P : prop with the
formula b : bool. Lemmas asserting reflect P b
are often referred to as "views".
iffP, appP, sameP, rwP :: lemmas for direct manipulation of reflection
views: iffP is used to prove reflection from
logical equivalence, appP to compose views, and
sameP and rwP to perform boolean and setoid
rewriting.
elimT :: coercion reflect >-> Funclass, which allows the
direct application of `reflect' views to
boolean assertions.
decidable P <-> P is effectively decidable (:= {P} + {~ P}.
contra, contraL, ... :: contraposition lemmas.
altP my_viewP :: natural alternative for reflection; given
lemma myviewP: reflect my_Prop my_formula,
have #[#myP | not_myP#]# := altP my_viewP.
generates two subgoals, in which my_formula has
been replaced by true and false, resp., with
new assumptions myP : my_Prop and
not_myP: ~~ my_formula.
Caveat: my_formula must be an APPLICATION, not
a variable, constant, let-in, etc. (due to the
poor behaviour of dependent index matching).
boolP my_formula :: boolean disjunction, equivalent to
altP (idP my_formula) but circumventing the
dependent index capture issue; destructing
boolP my_formula generates two subgoals with
assumtions my_formula and ~~ myformula. As
with altP, my_formula must be an application.
\unless C, P <-> we can assume property P when a something that
holds under condition C (such as C itself).
:= forall G : Prop, (C -> G) -> (P -> G) -> G.
This is just C \/ P or rather its impredicative
encoding, whose usage better fits the above
description: given a lemma UCP whose conclusion
is \unless C, P we can assume P by writing:
wlog hP: / P by apply/UCP; (prove C -> goal).
or even apply: UCP id _ => hP if the goal is C.
classically P <-> we can assume P when proving is_true b.
:= forall b : bool, (P -> b) -> b.
This is equivalent to ~ (~ P) when P : Prop.
implies P Q == wrapper variant type that coerces to P -> Q and
can be used as a P -> Q view unambigously.
Useful to avoid spurious insertion of <-> views
when Q is a conjunction of foralls, as in Lemma
all_and2 below; conversely, avoids confusion in
apply views for impredicative properties, such
as \unless C, P. Also supports contrapositives.
a && b == the boolean conjunction of a and b.
a || b == the boolean disjunction of a and b.
a ==> b == the boolean implication of b by a.
~~ a == the boolean negation of a.
a (+) b == the boolean exclusive or (or sum) of a and b.
#[# /\ P1 , P2 & P3 #]# == multiway logical conjunction, up to 5 terms.
#[# \/ P1 , P2 | P3 #]# == multiway logical disjunction, up to 4 terms.
#[#&& a, b, c & d#]# == iterated, right associative boolean conjunction
with arbitrary arity.
#[#|| a, b, c | d#]# == iterated, right associative boolean disjunction
with arbitrary arity.
#[#==> a, b, c => d#]# == iterated, right associative boolean implication
with arbitrary arity.
and3P, ... == specific reflection lemmas for iterated
connectives.
andTb, orbAC, ... == systematic names for boolean connective
properties (see suffix conventions below).
prop_congr == a tactic to move a boolean equality from
its coerced form in Prop to the equality
in bool.
bool_congr == resolution tactic for blindly weeding out
like terms from boolean equalities (can fail).
This file provides a theory of boolean predicates and relations:
pred T == the type of bool predicates (:= T -> bool).
simpl_pred T == the type of simplifying bool predicates, using
the simpl_fun from ssrfun.v.
rel T == the type of bool relations.
:= T -> pred T or T -> T -> bool.
simpl_rel T == type of simplifying relations.
predType == the generic predicate interface, supported for
for lists and sets.
pred_class == a coercion class for the predType projection to
pred; declaring a coercion to pred_class is an
alternative way of equipping a type with a
predType structure, which interoperates better
with coercion subtyping. This is used, e.g.,
for finite sets, so that finite groups inherit
the membership operation by coercing to sets.
If P is a predicate the proposition "x satisfies P" can be written
applicatively as (P x), or using an explicit connective as (x \in P); in
the latter case we say that P is a "collective" predicate. We use A, B
rather than P, Q for collective predicates:
x \in A == x satisfies the (collective) predicate A.
x \notin A == x doesn't satisfy the (collective) predicate A.
The pred T type can be used as a generic predicate type for either kind,
but the two kinds of predicates should not be confused. When a "generic"
pred T value of one type needs to be passed as the other the following
conversions should be used explicitly:
SimplPred P == a (simplifying) applicative equivalent of P.
mem A == an applicative equivalent of A:
mem A x simplifies to x \in A.
Alternatively one can use the syntax for explicit simplifying predicates
and relations (in the following x is bound in E):
#[#pred x | E#]# == simplifying (see ssrfun) predicate x => E.
#[#pred x : T | E#]# == predicate x => E, with a cast on the argument.
#[#pred : T | P#]# == constant predicate P on type T.
#[#pred x | E1 & E2#]# == #[#pred x | E1 && E2#]#; an x : T cast is allowed.
#[#pred x in A#]# == #[#pred x | x in A#]#.
#[#pred x in A | E#]# == #[#pred x | x in A & E#]#.
#[#pred x in A | E1 & E2#]# == #[#pred x in A | E1 && E2#]#.
#[#predU A & B#]# == union of two collective predicates A and B.
#[#predI A & B#]# == intersection of collective predicates A and B.
#[#predD A & B#]# == difference of collective predicates A and B.
#[#predC A#]# == complement of the collective predicate A.
#[#preim f of A#]# == preimage under f of the collective predicate A.
predU P Q, ... == union, etc of applicative predicates.
pred0 == the empty predicate.
predT == the total (always true) predicate.
if T : predArgType, then T coerces to predT.
{: T} == T cast to predArgType (e.g., {: bool * nat})
In the following, x and y are bound in E:
#[#rel x y | E#]# == simplifying relation x, y => E.
#[#rel x y : T | E#]# == simplifying relation with arguments cast.
#[#rel x y in A & B | E#]# == #[#rel x y | #[#&& x \in A, y \in B & E#]# #]#.
#[#rel x y in A & B#]# == #[#rel x y | (x \in A) && (y \in B) #]#.
#[#rel x y in A | E#]# == #[#rel x y in A & A | E#]#.
#[#rel x y in A#]# == #[#rel x y in A & A#]#.
relU R S == union of relations R and S.
Explicit values of type pred T (i.e., lamdba terms) should always be used
applicatively, while values of collection types implementing the predType
interface, such as sequences or sets should always be used as collective
predicates. Defined constants and functions of type pred T or simpl_pred T
as well as the explicit simpl_pred T values described below, can generally
be used either way. Note however that x \in A will not auto-simplify when
A is an explicit simpl_pred T value; the generic simplification rule inE
must be used (when A : pred T, the unfold_in rule can be used). Constants
of type pred T with an explicit simpl_pred value do not auto-simplify when
used applicatively, but can still be expanded with inE. This behavior can
be controlled as follows:
Let A : collective_pred T := #[#pred x | ... #]#.
The collective_pred T type is just an alias for pred T, but this cast
stops rewrite inE from expanding the definition of A, thus treating A
into an abstract collection (unfold_in or in_collective can be used to
expand manually).
Let A : applicative_pred T := #[#pred x | ... #]#.
This cast causes inE to turn x \in A into the applicative A x form;
A will then have to unfolded explicitly with the /A rule. This will
also apply to any definition that reduces to A (e.g., Let B := A).
Canonical A_app_pred := ApplicativePred A.
This declaration, given after definition of A, similarly causes inE to
turn x \in A into A x, but in addition allows the app_predE rule to
turn A x back into x \in A; it can be used for any definition of type
pred T, which makes it especially useful for ambivalent predicates
as the relational transitive closure connect, that are used in both
applicative and collective styles.
Purely for aesthetics, we provide a subtype of collective predicates:
qualifier q T == a pred T pretty-printing wrapper. An A : qualifier q T
coerces to pred_class and thus behaves as a collective
predicate, but x \in A and x \notin A are displayed as:
x \is A and x \isn't A when q = 0,
x \is a A and x \isn't a A when q = 1,
x \is an A and x \isn't an A when q = 2, respectively.
#[#qualify x | P#]# := Qualifier 0 (fun x => P), constructor for the above.
#[#qualify x : T | P#]#, #[#qualify a x | P#]#, #[#qualify an X | P#]#, etc.
variants of the above with type constraints and different
values of q.
We provide an internal interface to support attaching properties (such as
being multiplicative) to predicates:
pred_key p == phantom type that will serve as a support for properties
to be attached to p : pred_class; instances should be
created with Fact/Qed so as to be opaque.
KeyedPred k_p == an instance of the interface structure that attaches
(k_p : pred_key P) to P; the structure projection is a
coercion to pred_class.
KeyedQualifier k_q == an instance of the interface structure that attaches
(k_q : pred_key q) to (q : qualifier n T).
DefaultPredKey p == a default value for pred_key p; the vernacular command
Import DefaultKeying attaches this key to all predicates
that are not explicitly keyed.
Keys can be used to attach properties to predicates, qualifiers and
generic nouns in a way that allows them to be used transparently. The key
projection of a predicate property structure such as unsignedPred should
be a pred_key, not a pred, and corresponding lemmas will have the form
Lemma rpredN R S (oppS : @opprPred R S) (kS : keyed_pred oppS) :
{mono -%%R: x / x \in kS}.
Because x \in kS will be displayed as x \in S (or x \is S, etc), the
canonical instance of opprPred will not normally be exposed (it will also
be erased by /= simplification). In addition each predicate structure
should have a DefaultPredKey Canonical instance that simply issues the
property as a proof obligation (which can be caught by the Prop-irrelevant
feature of the ssreflect plugin).
Some properties of predicates and relations:
A =i B <-> A and B are extensionally equivalent.
{subset A <= B} <-> A is a (collective) subpredicate of B.
subpred P Q <-> P is an (applicative) subpredicate or Q.
subrel R S <-> R is a subrelation of S.
In the following R is in rel T:
reflexive R <-> R is reflexive.
irreflexive R <-> R is irreflexive.
symmetric R <-> R (in rel T) is symmetric (equation).
pre_symmetric R <-> R is symmetric (implication).
antisymmetric R <-> R is antisymmetric.
total R <-> R is total.
transitive R <-> R is transitive.
left_transitive R <-> R is a congruence on its left hand side.
right_transitive R <-> R is a congruence on its right hand side.
equivalence_rel R <-> R is an equivalence relation.
Localization of (Prop) predicates; if P1 is convertible to forall x, Qx,
P2 to forall x y, Qxy and P3 to forall x y z, Qxyz :
{for y, P1} <-> Qx{y / x}.
{in A, P1} <-> forall x, x \in A -> Qx.
{in A1 & A2, P2} <-> forall x y, x \in A1 -> y \in A2 -> Qxy.
{in A &, P2} <-> forall x y, x \in A -> y \in A -> Qxy.
{in A1 & A2 & A3, Q3} <-> forall x y z,
x \in A1 -> y \in A2 -> z \in A3 -> Qxyz.
{in A1 & A2 &, Q3} == {in A1 & A2 & A2, Q3}.
{in A1 && A3, Q3} == {in A1 & A1 & A3, Q3}.
{in A &&, Q3} == {in A & A & A, Q3}.
{in A, bijective f} == f has a right inverse in A.
{on C, P1} == forall x, (f x) \in C -> Qx
when P1 is also convertible to Pf f.
{on C &, P2} == forall x y, f x \in C -> f y \in C -> Qxy
when P2 is also convertible to Pf f.
{on C, P1' & g} == forall x, (f x) \in cd -> Qx
when P1' is convertible to Pf f
and P1' g is convertible to forall x, Qx.
{on C, bijective f} == f has a right inverse on C.
This file extends the lemma name suffix conventions of ssrfun as follows:
A -- associativity, as in andbA : associative andb.
AC -- right commutativity.
ACA -- self-interchange (inner commutativity), e.g.,
orbACA : (a || b) || (c || d) = (a || c) || (b || d).
b -- a boolean argument, as in andbb : idempotent andb.
C -- commutativity, as in andbC : commutative andb,
or predicate complement, as in predC.
CA -- left commutativity.
D -- predicate difference, as in predD.
E -- elimination, as in negbFE : ~~ b = false -> b.
F or f -- boolean false, as in andbF : b && false = false.
I -- left/right injectivity, as in addbI : right_injective addb,
or predicate intersection, as in predI.
l -- a left-hand operation, as andb_orl : left_distributive andb orb.
N or n -- boolean negation, as in andbN : a && (~~ a) = false.
P -- a characteristic property, often a reflection lemma, as in
andP : reflect (a /\ b) (a && b).
r -- a right-hand operation, as orb_andr : rightt_distributive orb andb.
T or t -- boolean truth, as in andbT: right_id true andb.
U -- predicate union, as in predU.
W -- weakening, as in in1W : {in D, forall x, P} -> forall x, P. **)
Set Implicit Arguments.
Unset Strict Implicit.
Unset Printing Implicit Defensive.
Set Warnings "-projection-no-head-constant".
Notation reflect := Bool.reflect.
Notation ReflectT := Bool.ReflectT.
Notation ReflectF := Bool.ReflectF.
Reserved Notation "~~ b" (at level 35, right associativity).
Reserved Notation "b ==> c" (at level 55, right associativity).
Reserved Notation "b1 (+) b2" (at level 50, left associativity).
Reserved Notation "x \in A"
(at level 70, format "'[hv' x '/ ' \in A ']'", no associativity).
Reserved Notation "x \notin A"
(at level 70, format "'[hv' x '/ ' \notin A ']'", no associativity).
Reserved Notation "p1 =i p2"
(at level 70, format "'[hv' p1 '/ ' =i p2 ']'", no associativity).
(**
We introduce a number of n-ary "list-style" notations that share a common
format, namely
#[#op arg1, arg2, ... last_separator last_arg#]#
This usually denotes a right-associative applications of op, e.g.,
#[#&& a, b, c & d#]# denotes a && (b && (c && d))
The last_separator must be a non-operator token. Here we use &, | or =>;
our default is &, but we try to match the intended meaning of op. The
separator is a workaround for limitations of the parsing engine; the same
limitations mean the separator cannot be omitted even when last_arg can.
The Notation declarations are complicated by the separate treatment for
some fixed arities (binary for bool operators, and all arities for Prop
operators).
We also use the square brackets in comprehension-style notations
#[#type var separator expr#]#
where "type" is the type of the comprehension (e.g., pred) and "separator"
is | or => . It is important that in other notations a leading square
bracket #[# is always followed by an operator symbol or a fixed identifier. **)
Reserved Notation "[ /\ P1 & P2 ]" (at level 0, only parsing).
Reserved Notation "[ /\ P1 , P2 & P3 ]" (at level 0, format
"'[hv' [ /\ '[' P1 , '/' P2 ']' '/ ' & P3 ] ']'").
Reserved Notation "[ /\ P1 , P2 , P3 & P4 ]" (at level 0, format
"'[hv' [ /\ '[' P1 , '/' P2 , '/' P3 ']' '/ ' & P4 ] ']'").
Reserved Notation "[ /\ P1 , P2 , P3 , P4 & P5 ]" (at level 0, format
"'[hv' [ /\ '[' P1 , '/' P2 , '/' P3 , '/' P4 ']' '/ ' & P5 ] ']'").
Reserved Notation "[ \/ P1 | P2 ]" (at level 0, only parsing).
Reserved Notation "[ \/ P1 , P2 | P3 ]" (at level 0, format
"'[hv' [ \/ '[' P1 , '/' P2 ']' '/ ' | P3 ] ']'").
Reserved Notation "[ \/ P1 , P2 , P3 | P4 ]" (at level 0, format
"'[hv' [ \/ '[' P1 , '/' P2 , '/' P3 ']' '/ ' | P4 ] ']'").
Reserved Notation "[ && b1 & c ]" (at level 0, only parsing).
Reserved Notation "[ && b1 , b2 , .. , bn & c ]" (at level 0, format
"'[hv' [ && '[' b1 , '/' b2 , '/' .. , '/' bn ']' '/ ' & c ] ']'").
Reserved Notation "[ || b1 | c ]" (at level 0, only parsing).
Reserved Notation "[ || b1 , b2 , .. , bn | c ]" (at level 0, format
"'[hv' [ || '[' b1 , '/' b2 , '/' .. , '/' bn ']' '/ ' | c ] ']'").
Reserved Notation "[ ==> b1 => c ]" (at level 0, only parsing).
Reserved Notation "[ ==> b1 , b2 , .. , bn => c ]" (at level 0, format
"'[hv' [ ==> '[' b1 , '/' b2 , '/' .. , '/' bn ']' '/' => c ] ']'").
Reserved Notation "[ 'pred' : T => E ]" (at level 0, format
"'[hv' [ 'pred' : T => '/ ' E ] ']'").
Reserved Notation "[ 'pred' x => E ]" (at level 0, x at level 8, format
"'[hv' [ 'pred' x => '/ ' E ] ']'").
Reserved Notation "[ 'pred' x : T => E ]" (at level 0, x at level 8, format
"'[hv' [ 'pred' x : T => '/ ' E ] ']'").
Reserved Notation "[ 'rel' x y => E ]" (at level 0, x, y at level 8, format
"'[hv' [ 'rel' x y => '/ ' E ] ']'").
Reserved Notation "[ 'rel' x y : T => E ]" (at level 0, x, y at level 8, format
"'[hv' [ 'rel' x y : T => '/ ' E ] ']'").
(** Shorter delimiter **)
Delimit Scope bool_scope with B.
Open Scope bool_scope.
(** An alternative to xorb that behaves somewhat better wrt simplification. **)
Definition addb b := if b then negb else id.
(** Notation for && and || is declared in Init.Datatypes. **)
Notation "~~ b" := (negb b) : bool_scope.
Notation "b ==> c" := (implb b c) : bool_scope.
Notation "b1 (+) b2" := (addb b1 b2) : bool_scope.
(** Constant is_true b := b = true is defined in Init.Datatypes. **)
Coercion is_true : bool >-> Sortclass. (* Prop *)
Lemma prop_congr : forall b b' : bool, b = b' -> b = b' :> Prop.
Proof. by move=> b b' ->. Qed.
Ltac prop_congr := apply: prop_congr.
(** Lemmas for trivial. **)
Lemma is_true_true : true. Proof. by []. Qed.
Lemma not_false_is_true : ~ false. Proof. by []. Qed.
Lemma is_true_locked_true : locked true. Proof. by unlock. Qed.
Hint Resolve is_true_true not_false_is_true is_true_locked_true : core.
(** Shorter names. **)
Definition isT := is_true_true.
Definition notF := not_false_is_true.
(** Negation lemmas. **)
(**
We generally take NEGATION as the standard form of a false condition:
negative boolean hypotheses should be of the form ~~ b, rather than ~ b or
b = false, as much as possible. **)
Lemma negbT b : b = false -> ~~ b. Proof. by case: b. Qed.
Lemma negbTE b : ~~ b -> b = false. Proof. by case: b. Qed.
Lemma negbF b : (b : bool) -> ~~ b = false. Proof. by case: b. Qed.
Lemma negbFE b : ~~ b = false -> b. Proof. by case: b. Qed.
Lemma negbK : involutive negb. Proof. by case. Qed.
Lemma negbNE b : ~~ ~~ b -> b. Proof. by case: b. Qed.
Lemma negb_inj : injective negb. Proof. exact: can_inj negbK. Qed.
Lemma negbLR b c : b = ~~ c -> ~~ b = c. Proof. exact: canLR negbK. Qed.
Lemma negbRL b c : ~~ b = c -> b = ~~ c. Proof. exact: canRL negbK. Qed.
Lemma contra (c b : bool) : (c -> b) -> ~~ b -> ~~ c.
Proof. by case: b => //; case: c. Qed.
Definition contraNN := contra.
Lemma contraL (c b : bool) : (c -> ~~ b) -> b -> ~~ c.
Proof. by case: b => //; case: c. Qed.
Definition contraTN := contraL.
Lemma contraR (c b : bool) : (~~ c -> b) -> ~~ b -> c.
Proof. by case: b => //; case: c. Qed.
Definition contraNT := contraR.
Lemma contraLR (c b : bool) : (~~ c -> ~~ b) -> b -> c.
Proof. by case: b => //; case: c. Qed.
Definition contraTT := contraLR.
Lemma contraT b : (~~ b -> false) -> b. Proof. by case: b => // ->. Qed.
Lemma wlog_neg b : (~~ b -> b) -> b. Proof. by case: b => // ->. Qed.
Lemma contraFT (c b : bool) : (~~ c -> b) -> b = false -> c.
Proof. by move/contraR=> notb_c /negbT. Qed.
Lemma contraFN (c b : bool) : (c -> b) -> b = false -> ~~ c.
Proof. by move/contra=> notb_notc /negbT. Qed.
Lemma contraTF (c b : bool) : (c -> ~~ b) -> b -> c = false.
Proof. by move/contraL=> b_notc /b_notc/negbTE. Qed.
Lemma contraNF (c b : bool) : (c -> b) -> ~~ b -> c = false.
Proof. by move/contra=> notb_notc /notb_notc/negbTE. Qed.
Lemma contraFF (c b : bool) : (c -> b) -> b = false -> c = false.
Proof. by move/contraFN=> bF_notc /bF_notc/negbTE. Qed.
(**
Coercion of sum-style datatypes into bool, which makes it possible
to use ssr's boolean if rather than Coq's "generic" if. **)
Coercion isSome T (u : option T) := if u is Some _ then true else false.
Coercion is_inl A B (u : A + B) := if u is inl _ then true else false.
Coercion is_left A B (u : {A} + {B}) := if u is left _ then true else false.
Coercion is_inleft A B (u : A + {B}) := if u is inleft _ then true else false.
Prenex Implicits isSome is_inl is_left is_inleft.
Definition decidable P := {P} + {~ P}.
(**
Lemmas for ifs with large conditions, which allow reasoning about the
condition without repeating it inside the proof (the latter IS
preferable when the condition is short).
Usage :
if the goal contains (if cond then ...) = ...
case: ifP => Hcond.
generates two subgoal, with the assumption Hcond : cond = true/false
Rewrite if_same eliminates redundant ifs
Rewrite (fun_if f) moves a function f inside an if
Rewrite if_arg moves an argument inside a function-valued if **)
Section BoolIf.
Variables (A B : Type) (x : A) (f : A -> B) (b : bool) (vT vF : A).
Variant if_spec (not_b : Prop) : bool -> A -> Set :=
| IfSpecTrue of b : if_spec not_b true vT
| IfSpecFalse of not_b : if_spec not_b false vF.
Lemma ifP : if_spec (b = false) b (if b then vT else vF).
Proof. by case def_b: b; constructor. Qed.
Lemma ifPn : if_spec (~~ b) b (if b then vT else vF).
Proof. by case def_b: b; constructor; rewrite ?def_b. Qed.
Lemma ifT : b -> (if b then vT else vF) = vT. Proof. by move->. Qed.
Lemma ifF : b = false -> (if b then vT else vF) = vF. Proof. by move->. Qed.
Lemma ifN : ~~ b -> (if b then vT else vF) = vF. Proof. by move/negbTE->. Qed.
Lemma if_same : (if b then vT else vT) = vT.
Proof. by case b. Qed.
Lemma if_neg : (if ~~ b then vT else vF) = if b then vF else vT.
Proof. by case b. Qed.
Lemma fun_if : f (if b then vT else vF) = if b then f vT else f vF.
Proof. by case b. Qed.
Lemma if_arg (fT fF : A -> B) :
(if b then fT else fF) x = if b then fT x else fF x.
Proof. by case b. Qed.
(** Turning a boolean "if" form into an application. **)
Definition if_expr := if b then vT else vF.
Lemma ifE : (if b then vT else vF) = if_expr. Proof. by []. Qed.
End BoolIf.
(** Core (internal) reflection lemmas, used for the three kinds of views. **)
Section ReflectCore.
Variables (P Q : Prop) (b c : bool).
Hypothesis Hb : reflect P b.
Lemma introNTF : (if c then ~ P else P) -> ~~ b = c.
Proof. by case c; case Hb. Qed.
Lemma introTF : (if c then P else ~ P) -> b = c.
Proof. by case c; case Hb. Qed.
Lemma elimNTF : ~~ b = c -> if c then ~ P else P.
Proof. by move <-; case Hb. Qed.
Lemma elimTF : b = c -> if c then P else ~ P.
Proof. by move <-; case Hb. Qed.
Lemma equivPif : (Q -> P) -> (P -> Q) -> if b then Q else ~ Q.
Proof. by case Hb; auto. Qed.
Lemma xorPif : Q \/ P -> ~ (Q /\ P) -> if b then ~ Q else Q.
Proof. by case Hb => [? _ H ? | ? H _]; case: H. Qed.
End ReflectCore.
(** Internal negated reflection lemmas **)
Section ReflectNegCore.
Variables (P Q : Prop) (b c : bool).
Hypothesis Hb : reflect P (~~ b).
Lemma introTFn : (if c then ~ P else P) -> b = c.
Proof. by move/(introNTF Hb) <-; case b. Qed.
Lemma elimTFn : b = c -> if c then ~ P else P.
Proof. by move <-; apply: (elimNTF Hb); case b. Qed.
Lemma equivPifn : (Q -> P) -> (P -> Q) -> if b then ~ Q else Q.
Proof. by rewrite -if_neg; apply: equivPif. Qed.
Lemma xorPifn : Q \/ P -> ~ (Q /\ P) -> if b then Q else ~ Q.
Proof. by rewrite -if_neg; apply: xorPif. Qed.
End ReflectNegCore.
(** User-oriented reflection lemmas **)
Section Reflect.
Variables (P Q : Prop) (b b' c : bool).
Hypotheses (Pb : reflect P b) (Pb' : reflect P (~~ b')).
Lemma introT : P -> b. Proof. exact: introTF true _. Qed.
Lemma introF : ~ P -> b = false. Proof. exact: introTF false _. Qed.
Lemma introN : ~ P -> ~~ b. Proof. exact: introNTF true _. Qed.
Lemma introNf : P -> ~~ b = false. Proof. exact: introNTF false _. Qed.
Lemma introTn : ~ P -> b'. Proof. exact: introTFn true _. Qed.
Lemma introFn : P -> b' = false. Proof. exact: introTFn false _. Qed.
Lemma elimT : b -> P. Proof. exact: elimTF true _. Qed.
Lemma elimF : b = false -> ~ P. Proof. exact: elimTF false _. Qed.
Lemma elimN : ~~ b -> ~P. Proof. exact: elimNTF true _. Qed.
Lemma elimNf : ~~ b = false -> P. Proof. exact: elimNTF false _. Qed.
Lemma elimTn : b' -> ~ P. Proof. exact: elimTFn true _. Qed.
Lemma elimFn : b' = false -> P. Proof. exact: elimTFn false _. Qed.
Lemma introP : (b -> Q) -> (~~ b -> ~ Q) -> reflect Q b.
Proof. by case b; constructor; auto. Qed.
Lemma iffP : (P -> Q) -> (Q -> P) -> reflect Q b.
Proof. by case: Pb; constructor; auto. Qed.
Lemma equivP : (P <-> Q) -> reflect Q b.
Proof. by case; apply: iffP. Qed.
Lemma sumboolP (decQ : decidable Q) : reflect Q decQ.
Proof. by case: decQ; constructor. Qed.
Lemma appP : reflect Q b -> P -> Q.
Proof. by move=> Qb; move/introT; case: Qb. Qed.
Lemma sameP : reflect P c -> b = c.
Proof. by case; [apply: introT | apply: introF]. Qed.
Lemma decPcases : if b then P else ~ P. Proof. by case Pb. Qed.
Definition decP : decidable P. by case: b decPcases; [left | right]. Defined.
Lemma rwP : P <-> b. Proof. by split; [apply: introT | apply: elimT]. Qed.
Lemma rwP2 : reflect Q b -> (P <-> Q).
Proof. by move=> Qb; split=> ?; [apply: appP | apply: elimT; case: Qb]. Qed.
(** Predicate family to reflect excluded middle in bool. **)
Variant alt_spec : bool -> Type :=
| AltTrue of P : alt_spec true
| AltFalse of ~~ b : alt_spec false.
Lemma altP : alt_spec b.
Proof. by case def_b: b / Pb; constructor; rewrite ?def_b. Qed.
End Reflect.
Hint View for move/ elimTF|3 elimNTF|3 elimTFn|3 introT|2 introTn|2 introN|2.
Hint View for apply/ introTF|3 introNTF|3 introTFn|3 elimT|2 elimTn|2 elimN|2.
Hint View for apply// equivPif|3 xorPif|3 equivPifn|3 xorPifn|3.
(** Allow the direct application of a reflection lemma to a boolean assertion. **)
Coercion elimT : reflect >-> Funclass.
#[universes(template)]
Variant implies P Q := Implies of P -> Q.
Lemma impliesP P Q : implies P Q -> P -> Q. Proof. by case. Qed.
Lemma impliesPn (P Q : Prop) : implies P Q -> ~ Q -> ~ P.
Proof. by case=> iP ? /iP. Qed.
Coercion impliesP : implies >-> Funclass.
Hint View for move/ impliesPn|2 impliesP|2.
Hint View for apply/ impliesPn|2 impliesP|2.
(** Impredicative or, which can emulate a classical not-implies. **)
Definition unless condition property : Prop :=
forall goal : Prop, (condition -> goal) -> (property -> goal) -> goal.
Notation "\unless C , P" := (unless C P)
(at level 200, C at level 100,
format "'[' \unless C , '/ ' P ']'") : type_scope.
Lemma unlessL C P : implies C (\unless C, P).
Proof. by split=> hC G /(_ hC). Qed.
Lemma unlessR C P : implies P (\unless C, P).
Proof. by split=> hP G _ /(_ hP). Qed.
Lemma unless_sym C P : implies (\unless C, P) (\unless P, C).
Proof. by split; apply; [apply/unlessR | apply/unlessL]. Qed.
Lemma unlessP (C P : Prop) : (\unless C, P) <-> C \/ P.
Proof. by split=> [|[/unlessL | /unlessR]]; apply; [left | right]. Qed.
Lemma bind_unless C P {Q} : implies (\unless C, P) (\unless (\unless C, Q), P).
Proof. by split; apply=> [hC|hP]; [apply/unlessL/unlessL | apply/unlessR]. Qed.
Lemma unless_contra b C : implies (~~ b -> C) (\unless C, b).
Proof. by split; case: b => [_ | hC]; [apply/unlessR | apply/unlessL/hC]. Qed.
(**
Classical reasoning becomes directly accessible for any bool subgoal.
Note that we cannot use "unless" here for lack of universe polymorphism. **)
Definition classically P : Prop := forall b : bool, (P -> b) -> b.
Lemma classicP (P : Prop) : classically P <-> ~ ~ P.
Proof.
split=> [cP nP | nnP [] // nP]; last by case nnP; move/nP.
by have: P -> false; [move/nP | move/cP].
Qed.
Lemma classicW P : P -> classically P. Proof. by move=> hP _ ->. Qed.
Lemma classic_bind P Q : (P -> classically Q) -> classically P -> classically Q.
Proof. by move=> iPQ cP b /iPQ-/cP. Qed.
Lemma classic_EM P : classically (decidable P).
Proof.
by case=> // undecP; apply/undecP; right=> notP; apply/notF/undecP; left.
Qed.
Lemma classic_pick T P : classically ({x : T | P x} + (forall x, ~ P x)).
Proof.
case=> // undecP; apply/undecP; right=> x Px.
by apply/notF/undecP; left; exists x.
Qed.
Lemma classic_imply P Q : (P -> classically Q) -> classically (P -> Q).
Proof.
move=> iPQ []// notPQ; apply/notPQ=> /iPQ-cQ.
by case: notF; apply: cQ => hQ; apply: notPQ.
Qed.
(**
List notations for wider connectives; the Prop connectives have a fixed
width so as to avoid iterated destruction (we go up to width 5 for /\, and
width 4 for or). The bool connectives have arbitrary widths, but denote
expressions that associate to the RIGHT. This is consistent with the right
associativity of list expressions and thus more convenient in most proofs. **)
Inductive and3 (P1 P2 P3 : Prop) : Prop := And3 of P1 & P2 & P3.
Inductive and4 (P1 P2 P3 P4 : Prop) : Prop := And4 of P1 & P2 & P3 & P4.
Inductive and5 (P1 P2 P3 P4 P5 : Prop) : Prop :=
And5 of P1 & P2 & P3 & P4 & P5.
Inductive or3 (P1 P2 P3 : Prop) : Prop := Or31 of P1 | Or32 of P2 | Or33 of P3.
Inductive or4 (P1 P2 P3 P4 : Prop) : Prop :=
Or41 of P1 | Or42 of P2 | Or43 of P3 | Or44 of P4.
Notation "[ /\ P1 & P2 ]" := (and P1 P2) (only parsing) : type_scope.
Notation "[ /\ P1 , P2 & P3 ]" := (and3 P1 P2 P3) : type_scope.
Notation "[ /\ P1 , P2 , P3 & P4 ]" := (and4 P1 P2 P3 P4) : type_scope.
Notation "[ /\ P1 , P2 , P3 , P4 & P5 ]" := (and5 P1 P2 P3 P4 P5) : type_scope.
Notation "[ \/ P1 | P2 ]" := (or P1 P2) (only parsing) : type_scope.
Notation "[ \/ P1 , P2 | P3 ]" := (or3 P1 P2 P3) : type_scope.
Notation "[ \/ P1 , P2 , P3 | P4 ]" := (or4 P1 P2 P3 P4) : type_scope.
Notation "[ && b1 & c ]" := (b1 && c) (only parsing) : bool_scope.
Notation "[ && b1 , b2 , .. , bn & c ]" := (b1 && (b2 && .. (bn && c) .. ))
: bool_scope.
Notation "[ || b1 | c ]" := (b1 || c) (only parsing) : bool_scope.
Notation "[ || b1 , b2 , .. , bn | c ]" := (b1 || (b2 || .. (bn || c) .. ))
: bool_scope.
Notation "[ ==> b1 , b2 , .. , bn => c ]" :=
(b1 ==> (b2 ==> .. (bn ==> c) .. )) : bool_scope.
Notation "[ ==> b1 => c ]" := (b1 ==> c) (only parsing) : bool_scope.
Section AllAnd.
Variables (T : Type) (P1 P2 P3 P4 P5 : T -> Prop).
Local Notation a P := (forall x, P x).
Lemma all_and2 : implies (forall x, [/\ P1 x & P2 x]) [/\ a P1 & a P2].
Proof. by split=> haveP; split=> x; case: (haveP x). Qed.
Lemma all_and3 : implies (forall x, [/\ P1 x, P2 x & P3 x])
[/\ a P1, a P2 & a P3].
Proof. by split=> haveP; split=> x; case: (haveP x). Qed.
Lemma all_and4 : implies (forall x, [/\ P1 x, P2 x, P3 x & P4 x])
[/\ a P1, a P2, a P3 & a P4].
Proof. by split=> haveP; split=> x; case: (haveP x). Qed.
Lemma all_and5 : implies (forall x, [/\ P1 x, P2 x, P3 x, P4 x & P5 x])
[/\ a P1, a P2, a P3, a P4 & a P5].
Proof. by split=> haveP; split=> x; case: (haveP x). Qed.
End AllAnd.
Arguments all_and2 {T P1 P2}.
Arguments all_and3 {T P1 P2 P3}.
Arguments all_and4 {T P1 P2 P3 P4}.
Arguments all_and5 {T P1 P2 P3 P4 P5}.
Lemma pair_andP P Q : P /\ Q <-> P * Q. Proof. by split; case. Qed.
Section ReflectConnectives.
Variable b1 b2 b3 b4 b5 : bool.
Lemma idP : reflect b1 b1.
Proof. by case b1; constructor. Qed.
Lemma boolP : alt_spec b1 b1 b1.
Proof. exact: (altP idP). Qed.
Lemma idPn : reflect (~~ b1) (~~ b1).
Proof. by case b1; constructor. Qed.
Lemma negP : reflect (~ b1) (~~ b1).
Proof. by case b1; constructor; auto. Qed.
Lemma negPn : reflect b1 (~~ ~~ b1).
Proof. by case b1; constructor. Qed.
Lemma negPf : reflect (b1 = false) (~~ b1).
Proof. by case b1; constructor. Qed.
Lemma andP : reflect (b1 /\ b2) (b1 && b2).
Proof. by case b1; case b2; constructor=> //; case. Qed.
Lemma and3P : reflect [/\ b1, b2 & b3] [&& b1, b2 & b3].
Proof. by case b1; case b2; case b3; constructor; try by case. Qed.
Lemma and4P : reflect [/\ b1, b2, b3 & b4] [&& b1, b2, b3 & b4].
Proof. by case b1; case b2; case b3; case b4; constructor; try by case. Qed.
Lemma and5P : reflect [/\ b1, b2, b3, b4 & b5] [&& b1, b2, b3, b4 & b5].
Proof.
by case b1; case b2; case b3; case b4; case b5; constructor; try by case.
Qed.
Lemma orP : reflect (b1 \/ b2) (b1 || b2).
Proof. by case b1; case b2; constructor; auto; case. Qed.
Lemma or3P : reflect [\/ b1, b2 | b3] [|| b1, b2 | b3].
Proof.
case b1; first by constructor; constructor 1.
case b2; first by constructor; constructor 2.
case b3; first by constructor; constructor 3.
by constructor; case.
Qed.
Lemma or4P : reflect [\/ b1, b2, b3 | b4] [|| b1, b2, b3 | b4].
Proof.
case b1; first by constructor; constructor 1.
case b2; first by constructor; constructor 2.
case b3; first by constructor; constructor 3.
case b4; first by constructor; constructor 4.
by constructor; case.
Qed.
Lemma nandP : reflect (~~ b1 \/ ~~ b2) (~~ (b1 && b2)).
Proof. by case b1; case b2; constructor; auto; case; auto. Qed.
Lemma norP : reflect (~~ b1 /\ ~~ b2) (~~ (b1 || b2)).
Proof. by case b1; case b2; constructor; auto; case; auto. Qed.
Lemma implyP : reflect (b1 -> b2) (b1 ==> b2).
Proof. by case b1; case b2; constructor; auto. Qed.
End ReflectConnectives.
Arguments idP [b1].
Arguments idPn [b1].
Arguments negP [b1].
Arguments negPn [b1].
Arguments negPf [b1].
Arguments andP [b1 b2].
Arguments and3P [b1 b2 b3].
Arguments and4P [b1 b2 b3 b4].
Arguments and5P [b1 b2 b3 b4 b5].
Arguments orP [b1 b2].
Arguments or3P [b1 b2 b3].
Arguments or4P [b1 b2 b3 b4].
Arguments nandP [b1 b2].
Arguments norP [b1 b2].
Arguments implyP [b1 b2].
Prenex Implicits idP idPn negP negPn negPf.
Prenex Implicits andP and3P and4P and5P orP or3P or4P nandP norP implyP.
(** Shorter, more systematic names for the boolean connectives laws. **)
Lemma andTb : left_id true andb. Proof. by []. Qed.
Lemma andFb : left_zero false andb. Proof. by []. Qed.
Lemma andbT : right_id true andb. Proof. by case. Qed.
Lemma andbF : right_zero false andb. Proof. by case. Qed.
Lemma andbb : idempotent andb. Proof. by case. Qed.
Lemma andbC : commutative andb. Proof. by do 2!case. Qed.
Lemma andbA : associative andb. Proof. by do 3!case. Qed.
Lemma andbCA : left_commutative andb. Proof. by do 3!case. Qed.
Lemma andbAC : right_commutative andb. Proof. by do 3!case. Qed.
Lemma andbACA : interchange andb andb. Proof. by do 4!case. Qed.
Lemma orTb : forall b, true || b. Proof. by []. Qed.
Lemma orFb : left_id false orb. Proof. by []. Qed.
Lemma orbT : forall b, b || true. Proof. by case. Qed.
Lemma orbF : right_id false orb. Proof. by case. Qed.
Lemma orbb : idempotent orb. Proof. by case. Qed.
Lemma orbC : commutative orb. Proof. by do 2!case. Qed.
Lemma orbA : associative orb. Proof. by do 3!case. Qed.
Lemma orbCA : left_commutative orb. Proof. by do 3!case. Qed.
Lemma orbAC : right_commutative orb. Proof. by do 3!case. Qed.
Lemma orbACA : interchange orb orb. Proof. by do 4!case. Qed.
Lemma andbN b : b && ~~ b = false. Proof. by case: b. Qed.
Lemma andNb b : ~~ b && b = false. Proof. by case: b. Qed.
Lemma orbN b : b || ~~ b = true. Proof. by case: b. Qed.
Lemma orNb b : ~~ b || b = true. Proof. by case: b. Qed.
Lemma andb_orl : left_distributive andb orb. Proof. by do 3!case. Qed.
Lemma andb_orr : right_distributive andb orb. Proof. by do 3!case. Qed.
Lemma orb_andl : left_distributive orb andb. Proof. by do 3!case. Qed.
Lemma orb_andr : right_distributive orb andb. Proof. by do 3!case. Qed.
Lemma andb_idl (a b : bool) : (b -> a) -> a && b = b.
Proof. by case: a; case: b => // ->. Qed.
Lemma andb_idr (a b : bool) : (a -> b) -> a && b = a.
Proof. by case: a; case: b => // ->. Qed.
Lemma andb_id2l (a b c : bool) : (a -> b = c) -> a && b = a && c.
Proof. by case: a; case: b; case: c => // ->. Qed.
Lemma andb_id2r (a b c : bool) : (b -> a = c) -> a && b = c && b.
Proof. by case: a; case: b; case: c => // ->. Qed.
Lemma orb_idl (a b : bool) : (a -> b) -> a || b = b.
Proof. by case: a; case: b => // ->. Qed.
Lemma orb_idr (a b : bool) : (b -> a) -> a || b = a.
Proof. by case: a; case: b => // ->. Qed.
Lemma orb_id2l (a b c : bool) : (~~ a -> b = c) -> a || b = a || c.
Proof. by case: a; case: b; case: c => // ->. Qed.
Lemma orb_id2r (a b c : bool) : (~~ b -> a = c) -> a || b = c || b.
Proof. by case: a; case: b; case: c => // ->. Qed.
Lemma negb_and (a b : bool) : ~~ (a && b) = ~~ a || ~~ b.
Proof. by case: a; case: b. Qed.
Lemma negb_or (a b : bool) : ~~ (a || b) = ~~ a && ~~ b.
Proof. by case: a; case: b. Qed.
(** Pseudo-cancellation -- i.e, absorbtion **)
Lemma andbK a b : a && b || a = a. Proof. by case: a; case: b. Qed.
Lemma andKb a b : a || b && a = a. Proof. by case: a; case: b. Qed.
Lemma orbK a b : (a || b) && a = a. Proof. by case: a; case: b. Qed.
Lemma orKb a b : a && (b || a) = a. Proof. by case: a; case: b. Qed.
(** Imply **)
Lemma implybT b : b ==> true. Proof. by case: b. Qed.
Lemma implybF b : (b ==> false) = ~~ b. Proof. by case: b. Qed.
Lemma implyFb b : false ==> b. Proof. by []. Qed.
Lemma implyTb b : (true ==> b) = b. Proof. by []. Qed.
Lemma implybb b : b ==> b. Proof. by case: b. Qed.
Lemma negb_imply a b : ~~ (a ==> b) = a && ~~ b.
Proof. by case: a; case: b. Qed.
Lemma implybE a b : (a ==> b) = ~~ a || b.
Proof. by case: a; case: b. Qed.
Lemma implyNb a b : (~~ a ==> b) = a || b.
Proof. by case: a; case: b. Qed.
Lemma implybN a b : (a ==> ~~ b) = (b ==> ~~ a).
Proof. by case: a; case: b. Qed.
Lemma implybNN a b : (~~ a ==> ~~ b) = b ==> a.
Proof. by case: a; case: b. Qed.
Lemma implyb_idl (a b : bool) : (~~ a -> b) -> (a ==> b) = b.
Proof. by case: a; case: b => // ->. Qed.
Lemma implyb_idr (a b : bool) : (b -> ~~ a) -> (a ==> b) = ~~ a.
Proof. by case: a; case: b => // ->. Qed.
Lemma implyb_id2l (a b c : bool) : (a -> b = c) -> (a ==> b) = (a ==> c).
Proof. by case: a; case: b; case: c => // ->. Qed.
(** Addition (xor) **)
Lemma addFb : left_id false addb. Proof. by []. Qed.
Lemma addbF : right_id false addb. Proof. by case. Qed.
Lemma addbb : self_inverse false addb. Proof. by case. Qed.
Lemma addbC : commutative addb. Proof. by do 2!case. Qed.
Lemma addbA : associative addb. Proof. by do 3!case. Qed.
Lemma addbCA : left_commutative addb. Proof. by do 3!case. Qed.
Lemma addbAC : right_commutative addb. Proof. by do 3!case. Qed.
Lemma addbACA : interchange addb addb. Proof. by do 4!case. Qed.
Lemma andb_addl : left_distributive andb addb. Proof. by do 3!case. Qed.
Lemma andb_addr : right_distributive andb addb. Proof. by do 3!case. Qed.
Lemma addKb : left_loop id addb. Proof. by do 2!case. Qed.
Lemma addbK : right_loop id addb. Proof. by do 2!case. Qed.
Lemma addIb : left_injective addb. Proof. by do 3!case. Qed.
Lemma addbI : right_injective addb. Proof. by do 3!case. Qed.
Lemma addTb b : true (+) b = ~~ b. Proof. by []. Qed.
Lemma addbT b : b (+) true = ~~ b. Proof. by case: b. Qed.
Lemma addbN a b : a (+) ~~ b = ~~ (a (+) b).
Proof. by case: a; case: b. Qed.
Lemma addNb a b : ~~ a (+) b = ~~ (a (+) b).
Proof. by case: a; case: b. Qed.
Lemma addbP a b : reflect (~~ a = b) (a (+) b).
Proof. by case: a; case: b; constructor. Qed.
Arguments addbP [a b].
(**
Resolution tactic for blindly weeding out common terms from boolean
equalities. When faced with a goal of the form (andb/orb/addb b1 b2) = b3
they will try to locate b1 in b3 and remove it. This can fail! **)
Ltac bool_congr :=
match goal with
| |- (?X1 && ?X2 = ?X3) => first
[ symmetry; rewrite -1?(andbC X1) -?(andbCA X1); congr 1 (andb X1); symmetry
| case: (X1); [ rewrite ?andTb ?andbT // | by rewrite ?andbF /= ] ]
| |- (?X1 || ?X2 = ?X3) => first
[ symmetry; rewrite -1?(orbC X1) -?(orbCA X1); congr 1 (orb X1); symmetry
| case: (X1); [ by rewrite ?orbT //= | rewrite ?orFb ?orbF ] ]
| |- (?X1 (+) ?X2 = ?X3) =>
symmetry; rewrite -1?(addbC X1) -?(addbCA X1); congr 1 (addb X1); symmetry
| |- (~~ ?X1 = ?X2) => congr 1 negb
end.
(**
Predicates, i.e., packaged functions to bool.
- pred T, the basic type for predicates over a type T, is simply an alias
for T -> bool.
We actually distinguish two kinds of predicates, which we call applicative
and collective, based on the syntax used to test them at some x in T:
- For an applicative predicate P, one uses prefix syntax:
P x
Also, most operations on applicative predicates use prefix syntax as
well (e.g., predI P Q).
- For a collective predicate A, one uses infix syntax:
x \in A
and all operations on collective predicates use infix syntax as well
(e.g., #[#predI A & B#]#).
There are only two kinds of applicative predicates:
- pred T, the alias for T -> bool mentioned above
- simpl_pred T, an alias for simpl_fun T bool with a coercion to pred T
that auto-simplifies on application (see ssrfun).
On the other hand, the set of collective predicate types is open-ended via
- predType T, a Structure that can be used to put Canonical collective
predicate interpretation on other types, such as lists, tuples,
finite sets, etc.
Indeed, we define such interpretations for applicative predicate types,
which can therefore also be used with the infix syntax, e.g.,
x \in predI P Q
Moreover these infix forms are convertible to their prefix counterpart
(e.g., predI P Q x which in turn simplifies to P x && Q x). The converse
is not true, however; collective predicate types cannot, in general, be
general, be used applicatively, because of the "uniform inheritance"
restriction on implicit coercions.
However, we do define an explicit generic coercion
- mem : forall (pT : predType), pT -> mem_pred T
where mem_pred T is a variant of simpl_pred T that preserves the infix
syntax, i.e., mem A x auto-simplifies to x \in A.
Indeed, the infix "collective" operators are notation for a prefix
operator with arguments of type mem_pred T or pred T, applied to coerced
collective predicates, e.g.,
Notation "x \in A" := (in_mem x (mem A)).
This prevents the variability in the predicate type from interfering with
the application of generic lemmas. Moreover this also makes it much easier
to define generic lemmas, because the simplest type -- pred T -- can be
used as the type of generic collective predicates, provided one takes care
not to use it applicatively; this avoids the burden of having to declare a
different predicate type for each predicate parameter of each section or
lemma.
This trick is made possible by the fact that the constructor of the
mem_pred T type aligns the unification process, forcing a generic
"collective" predicate A : pred T to unify with the actual collective B,
which mem has coerced to pred T via an internal, hidden implicit coercion,
supplied by the predType structure for B. Users should take care not to
inadvertently "strip" (mem B) down to the coerced B, since this will
expose the internal coercion: Coq will display a term B x that cannot be
typed as such. The topredE lemma can be used to restore the x \in B
syntax in this case. While -topredE can conversely be used to change
x \in P into P x, it is safer to use the inE and memE lemmas instead, as
they do not run the risk of exposing internal coercions. As a consequence
it is better to explicitly cast a generic applicative pred T to simpl_pred
using the SimplPred constructor, when it is used as a collective predicate
(see, e.g., Lemma eq_big in bigop).
We also sometimes "instantiate" the predType structure by defining a
coercion to the sort of the predPredType structure. This works better for
types such as {set T} that have subtypes that coerce to them, since the
same coercion will be inserted by the application of mem. It also lets us
turn any Type aT : predArgType into the total predicate over that type,
i.e., fun _: aT => true. This allows us to write, e.g., ##|'I_n| for the
cardinal of the (finite) type of integers less than n.
Collective predicates have a specific extensional equality,
- A =i B,
while applicative predicates use the extensional equality of functions,
- P =1 Q
The two forms are convertible, however.
We lift boolean operations to predicates, defining:
- predU (union), predI (intersection), predC (complement),
predD (difference), and preim (preimage, i.e., composition)
For each operation we define three forms, typically:
- predU : pred T -> pred T -> simpl_pred T
- #[#predU A & B#]#, a Notation for predU (mem A) (mem B)
- xpredU, a Notation for the lambda-expression inside predU,
which is mostly useful as an argument of =1, since it exposes the head
head constant of the expression to the ssreflect matching algorithm.
The syntax for the preimage of a collective predicate A is
- #[#preim f of A#]#
Finally, the generic syntax for defining a simpl_pred T is
- #[#pred x : T | P(x) #]#, #[#pred x | P(x) #]#, #[#pred x in A | P(x) #]#, etc.
We also support boolean relations, but only the applicative form, with
types
- rel T, an alias for T -> pred T
- simpl_rel T, an auto-simplifying version, and syntax
#[#rel x y | P(x,y) #]#, #[#rel x y in A & B | P(x,y) #]#, etc.
The notation #[#rel of fA#]# can be used to coerce a function returning a
collective predicate to one returning pred T.
Finally, note that there is specific support for ambivalent predicates
that can work in either style, as per this file's head descriptor. **)
Definition pred T := T -> bool.
Identity Coercion fun_of_pred : pred >-> Funclass.
Definition rel T := T -> pred T.
Identity Coercion fun_of_rel : rel >-> Funclass.
Notation xpred0 := (fun _ => false).
Notation xpredT := (fun _ => true).
Notation xpredI := (fun (p1 p2 : pred _) x => p1 x && p2 x).
Notation xpredU := (fun (p1 p2 : pred _) x => p1 x || p2 x).
Notation xpredC := (fun (p : pred _) x => ~~ p x).
Notation xpredD := (fun (p1 p2 : pred _) x => ~~ p2 x && p1 x).
Notation xpreim := (fun f (p : pred _) x => p (f x)).
Notation xrelU := (fun (r1 r2 : rel _) x y => r1 x y || r2 x y).
Section Predicates.
Variables T : Type.
Definition subpred (p1 p2 : pred T) := forall x, p1 x -> p2 x.
Definition subrel (r1 r2 : rel T) := forall x y, r1 x y -> r2 x y.
Definition simpl_pred := simpl_fun T bool.
Definition applicative_pred := pred T.
Definition collective_pred := pred T.
Definition SimplPred (p : pred T) : simpl_pred := SimplFun p.
Coercion pred_of_simpl (p : simpl_pred) : pred T := fun_of_simpl p.
Coercion applicative_pred_of_simpl (p : simpl_pred) : applicative_pred :=
fun_of_simpl p.
Coercion collective_pred_of_simpl (p : simpl_pred) : collective_pred :=
fun x => (let: SimplFun f := p in fun _ => f x) x.
(**
Note: applicative_of_simpl is convertible to pred_of_simpl, while
collective_of_simpl is not. **)
Definition pred0 := SimplPred xpred0.
Definition predT := SimplPred xpredT.
Definition predI p1 p2 := SimplPred (xpredI p1 p2).
Definition predU p1 p2 := SimplPred (xpredU p1 p2).
Definition predC p := SimplPred (xpredC p).
Definition predD p1 p2 := SimplPred (xpredD p1 p2).
Definition preim rT f (d : pred rT) := SimplPred (xpreim f d).
Definition simpl_rel := simpl_fun T (pred T).
Definition SimplRel (r : rel T) : simpl_rel := [fun x => r x].
Coercion rel_of_simpl_rel (r : simpl_rel) : rel T := fun x y => r x y.
Definition relU r1 r2 := SimplRel (xrelU r1 r2).
Lemma subrelUl r1 r2 : subrel r1 (relU r1 r2).
Proof. by move=> *; apply/orP; left. Qed.
Lemma subrelUr r1 r2 : subrel r2 (relU r1 r2).
Proof. by move=> *; apply/orP; right. Qed.
#[universes(template)]
Variant mem_pred := Mem of pred T.
Definition isMem pT topred mem := mem = (fun p : pT => Mem [eta topred p]).
#[universes(template)]
Structure predType := PredType {
pred_sort :> Type;
topred : pred_sort -> pred T;
_ : {mem | isMem topred mem}
}.
Definition mkPredType pT toP := PredType (exist (@isMem pT toP) _ (erefl _)).
Canonical predPredType := Eval hnf in @mkPredType (pred T) id.
Canonical simplPredType := Eval hnf in mkPredType pred_of_simpl.
Canonical boolfunPredType := Eval hnf in @mkPredType (T -> bool) id.
Coercion pred_of_mem mp : pred_sort predPredType := let: Mem p := mp in [eta p].
Canonical memPredType := Eval hnf in mkPredType pred_of_mem.
Definition clone_pred U :=
fun pT & pred_sort pT -> U =>
fun a mP (pT' := @PredType U a mP) & phant_id pT' pT => pT'.
End Predicates.
Arguments pred0 [T].
Arguments predT [T].
Prenex Implicits pred0 predT predI predU predC predD preim relU.
Notation "[ 'pred' : T | E ]" := (SimplPred (fun _ : T => E%B))
(at level 0, format "[ 'pred' : T | E ]") : fun_scope.
Notation "[ 'pred' x | E ]" := (SimplPred (fun x => E%B))
(at level 0, x ident, format "[ 'pred' x | E ]") : fun_scope.
Notation "[ 'pred' x | E1 & E2 ]" := [pred x | E1 && E2 ]
(at level 0, x ident, format "[ 'pred' x | E1 & E2 ]") : fun_scope.
Notation "[ 'pred' x : T | E ]" := (SimplPred (fun x : T => E%B))
(at level 0, x ident, only parsing) : fun_scope.
Notation "[ 'pred' x : T | E1 & E2 ]" := [pred x : T | E1 && E2 ]
(at level 0, x ident, only parsing) : fun_scope.
Notation "[ 'rel' x y | E ]" := (SimplRel (fun x y => E%B))
(at level 0, x ident, y ident, format "[ 'rel' x y | E ]") : fun_scope.
Notation "[ 'rel' x y : T | E ]" := (SimplRel (fun x y : T => E%B))
(at level 0, x ident, y ident, only parsing) : fun_scope.
Notation "[ 'predType' 'of' T ]" := (@clone_pred _ T _ id _ _ id)
(at level 0, format "[ 'predType' 'of' T ]") : form_scope.
(**
This redundant coercion lets us "inherit" the simpl_predType canonical
instance by declaring a coercion to simpl_pred. This hack is the only way
to put a predType structure on a predArgType. We use simpl_pred rather
than pred to ensure that /= removes the identity coercion. Note that the
coercion will never be used directly for simpl_pred, since the canonical
instance should always be resolved. **)
Notation pred_class := (pred_sort (predPredType _)).
Coercion sort_of_simpl_pred T (p : simpl_pred T) : pred_class := p : pred T.
(**
This lets us use some types as a synonym for their universal predicate.
Unfortunately, this won't work for existing types like bool, unless we
redefine bool, true, false and all bool ops. **)
Definition predArgType := Type.
Bind Scope type_scope with predArgType.
Identity Coercion sort_of_predArgType : predArgType >-> Sortclass.
Coercion pred_of_argType (T : predArgType) : simpl_pred T := predT.
Notation "{ : T }" := (T%type : predArgType)
(at level 0, format "{ : T }") : type_scope.
(**
These must be defined outside a Section because "cooking" kills the
nosimpl tag. **)
Definition mem T (pT : predType T) : pT -> mem_pred T :=
nosimpl (let: @PredType _ _ _ (exist _ mem _) := pT return pT -> _ in mem).
Definition in_mem T x mp := nosimpl pred_of_mem T mp x.
Prenex Implicits mem.
Coercion pred_of_mem_pred T mp := [pred x : T | in_mem x mp].
Definition eq_mem T p1 p2 := forall x : T, in_mem x p1 = in_mem x p2.
Definition sub_mem T p1 p2 := forall x : T, in_mem x p1 -> in_mem x p2.
Typeclasses Opaque eq_mem.
Lemma sub_refl T (p : mem_pred T) : sub_mem p p. Proof. by []. Qed.
Arguments sub_refl {T p}.
Notation "x \in A" := (in_mem x (mem A)) : bool_scope.
Notation "x \in A" := (in_mem x (mem A)) : bool_scope.
Notation "x \notin A" := (~~ (x \in A)) : bool_scope.
Notation "A =i B" := (eq_mem (mem A) (mem B)) : type_scope.
Notation "{ 'subset' A <= B }" := (sub_mem (mem A) (mem B))
(at level 0, A, B at level 69,
format "{ '[hv' 'subset' A '/ ' <= B ']' }") : type_scope.
Notation "[ 'mem' A ]" := (pred_of_simpl (pred_of_mem_pred (mem A)))
(at level 0, only parsing) : fun_scope.
Notation "[ 'rel' 'of' fA ]" := (fun x => [mem (fA x)])
(at level 0, format "[ 'rel' 'of' fA ]") : fun_scope.
Notation "[ 'predI' A & B ]" := (predI [mem A] [mem B])
(at level 0, format "[ 'predI' A & B ]") : fun_scope.
Notation "[ 'predU' A & B ]" := (predU [mem A] [mem B])
(at level 0, format "[ 'predU' A & B ]") : fun_scope.
Notation "[ 'predD' A & B ]" := (predD [mem A] [mem B])
(at level 0, format "[ 'predD' A & B ]") : fun_scope.
Notation "[ 'predC' A ]" := (predC [mem A])
(at level 0, format "[ 'predC' A ]") : fun_scope.
Notation "[ 'preim' f 'of' A ]" := (preim f [mem A])
(at level 0, format "[ 'preim' f 'of' A ]") : fun_scope.
Notation "[ 'pred' x 'in' A ]" := [pred x | x \in A]
(at level 0, x ident, format "[ 'pred' x 'in' A ]") : fun_scope.
Notation "[ 'pred' x 'in' A | E ]" := [pred x | x \in A & E]
(at level 0, x ident, format "[ 'pred' x 'in' A | E ]") : fun_scope.
Notation "[ 'pred' x 'in' A | E1 & E2 ]" := [pred x | x \in A & E1 && E2 ]
(at level 0, x ident,
format "[ 'pred' x 'in' A | E1 & E2 ]") : fun_scope.
Notation "[ 'rel' x y 'in' A & B | E ]" :=
[rel x y | (x \in A) && (y \in B) && E]
(at level 0, x ident, y ident,
format "[ 'rel' x y 'in' A & B | E ]") : fun_scope.
Notation "[ 'rel' x y 'in' A & B ]" := [rel x y | (x \in A) && (y \in B)]
(at level 0, x ident, y ident,
format "[ 'rel' x y 'in' A & B ]") : fun_scope.
Notation "[ 'rel' x y 'in' A | E ]" := [rel x y in A & A | E]
(at level 0, x ident, y ident,
format "[ 'rel' x y 'in' A | E ]") : fun_scope.
Notation "[ 'rel' x y 'in' A ]" := [rel x y in A & A]
(at level 0, x ident, y ident,
format "[ 'rel' x y 'in' A ]") : fun_scope.
Section simpl_mem.
Variables (T : Type) (pT : predType T).
Implicit Types (x : T) (p : pred T) (sp : simpl_pred T) (pp : pT).
(**
Bespoke structures that provide fine-grained control over matching the
various forms of the \in predicate; note in particular the different forms
of hoisting that are used. We had to work around several bugs in the
implementation of unification, notably improper expansion of telescope
projections and overwriting of a variable assignment by a later
unification (probably due to conversion cache cross-talk). **)
#[universes(template)]
Structure manifest_applicative_pred p := ManifestApplicativePred {
manifest_applicative_pred_value :> pred T;
_ : manifest_applicative_pred_value = p
}.
Definition ApplicativePred p := ManifestApplicativePred (erefl p).
Canonical applicative_pred_applicative sp :=
ApplicativePred (applicative_pred_of_simpl sp).
#[universes(template)]
Structure manifest_simpl_pred p := ManifestSimplPred {
manifest_simpl_pred_value :> simpl_pred T;
_ : manifest_simpl_pred_value = SimplPred p
}.
Canonical expose_simpl_pred p := ManifestSimplPred (erefl (SimplPred p)).
#[universes(template)]
Structure manifest_mem_pred p := ManifestMemPred {
manifest_mem_pred_value :> mem_pred T;
_ : manifest_mem_pred_value= Mem [eta p]
}.
Canonical expose_mem_pred p := @ManifestMemPred p _ (erefl _).
#[universes(template)]
Structure applicative_mem_pred p :=
ApplicativeMemPred {applicative_mem_pred_value :> manifest_mem_pred p}.
Canonical check_applicative_mem_pred p (ap : manifest_applicative_pred p) mp :=
@ApplicativeMemPred ap mp.
Lemma mem_topred (pp : pT) : mem (topred pp) = mem pp.
Proof. by rewrite /mem; case: pT pp => T1 app1 [mem1 /= ->]. Qed.
Lemma topredE x (pp : pT) : topred pp x = (x \in pp).
Proof. by rewrite -mem_topred. Qed.
Lemma app_predE x p (ap : manifest_applicative_pred p) : ap x = (x \in p).
Proof. by case: ap => _ /= ->. Qed.
Lemma in_applicative x p (amp : applicative_mem_pred p) : in_mem x amp = p x.
Proof. by case: amp => [[_ /= ->]]. Qed.
Lemma in_collective x p (msp : manifest_simpl_pred p) :
(x \in collective_pred_of_simpl msp) = p x.
Proof. by case: msp => _ /= ->. Qed.
Lemma in_simpl x p (msp : manifest_simpl_pred p) :
in_mem x (Mem [eta fun_of_simpl (msp : simpl_pred T)]) = p x.
Proof. by case: msp => _ /= ->. Qed.
(**
Because of the explicit eta expansion in the left-hand side, this lemma
should only be used in a right-to-left direction. The 8.3 hack allowing
partial right-to-left use does not work with the improved expansion
heuristics in 8.4. **)
Lemma unfold_in x p : (x \in ([eta p] : pred T)) = p x.
Proof. by []. Qed.
Lemma simpl_predE p : SimplPred p =1 p.
Proof. by []. Qed.
Definition inE := (in_applicative, in_simpl, simpl_predE). (* to be extended *)
Lemma mem_simpl sp : mem sp = sp :> pred T.
Proof. by []. Qed.
Definition memE := mem_simpl. (* could be extended *)
Lemma mem_mem (pp : pT) : (mem (mem pp) = mem pp) * (mem [mem pp] = mem pp).
Proof. by rewrite -mem_topred. Qed.
End simpl_mem.
(** Qualifiers and keyed predicates. **)
#[universes(template)]
Variant qualifier (q : nat) T := Qualifier of predPredType T.
Coercion has_quality n T (q : qualifier n T) : pred_class :=
fun x => let: Qualifier _ p := q in p x.
Arguments has_quality n [T].
Lemma qualifE n T p x : (x \in @Qualifier n T p) = p x. Proof. by []. Qed.
Notation "x \is A" := (x \in has_quality 0 A)
(at level 70, no associativity,
format "'[hv' x '/ ' \is A ']'") : bool_scope.
Notation "x \is 'a' A" := (x \in has_quality 1 A)
(at level 70, no associativity,
format "'[hv' x '/ ' \is 'a' A ']'") : bool_scope.
Notation "x \is 'an' A" := (x \in has_quality 2 A)
(at level 70, no associativity,
format "'[hv' x '/ ' \is 'an' A ']'") : bool_scope.
Notation "x \isn't A" := (x \notin has_quality 0 A)
(at level 70, no associativity,
format "'[hv' x '/ ' \isn't A ']'") : bool_scope.
Notation "x \isn't 'a' A" := (x \notin has_quality 1 A)
(at level 70, no associativity,
format "'[hv' x '/ ' \isn't 'a' A ']'") : bool_scope.
Notation "x \isn't 'an' A" := (x \notin has_quality 2 A)
(at level 70, no associativity,
format "'[hv' x '/ ' \isn't 'an' A ']'") : bool_scope.
Notation "[ 'qualify' x | P ]" := (Qualifier 0 (fun x => P%B))
(at level 0, x at level 99,
format "'[hv' [ 'qualify' x | '/ ' P ] ']'") : form_scope.
Notation "[ 'qualify' x : T | P ]" := (Qualifier 0 (fun x : T => P%B))
(at level 0, x at level 99, only parsing) : form_scope.
Notation "[ 'qualify' 'a' x | P ]" := (Qualifier 1 (fun x => P%B))
(at level 0, x at level 99,
format "'[hv' [ 'qualify' 'a' x | '/ ' P ] ']'") : form_scope.
Notation "[ 'qualify' 'a' x : T | P ]" := (Qualifier 1 (fun x : T => P%B))
(at level 0, x at level 99, only parsing) : form_scope.
Notation "[ 'qualify' 'an' x | P ]" := (Qualifier 2 (fun x => P%B))
(at level 0, x at level 99,
format "'[hv' [ 'qualify' 'an' x | '/ ' P ] ']'") : form_scope.
Notation "[ 'qualify' 'an' x : T | P ]" := (Qualifier 2 (fun x : T => P%B))
(at level 0, x at level 99, only parsing) : form_scope.
(** Keyed predicates: support for property-bearing predicate interfaces. **)
Section KeyPred.
Variable T : Type.
#[universes(template)]
Variant pred_key (p : predPredType T) := DefaultPredKey.
Variable p : predPredType T.
#[universes(template)]
Structure keyed_pred (k : pred_key p) :=
PackKeyedPred {unkey_pred :> pred_class; _ : unkey_pred =i p}.
Variable k : pred_key p.
Definition KeyedPred := @PackKeyedPred k p (frefl _).
Variable k_p : keyed_pred k.
Lemma keyed_predE : k_p =i p. Proof. by case: k_p. Qed.
(**
Instances that strip the mem cast; the first one has "pred_of_mem" as its
projection head value, while the second has "pred_of_simpl". The latter
has the side benefit of preempting accidental misdeclarations.
Note: pred_of_mem is the registered mem >-> pred_class coercion, while
simpl_of_mem; pred_of_simpl is the mem >-> pred >=> Funclass coercion. We
must write down the coercions explicitly as the Canonical head constant
computation does not strip casts !! **)
Canonical keyed_mem :=
@PackKeyedPred k (pred_of_mem (mem k_p)) keyed_predE.
Canonical keyed_mem_simpl :=
@PackKeyedPred k (pred_of_simpl (mem k_p)) keyed_predE.
End KeyPred.
Notation "x \i 'n' S" := (x \in @unkey_pred _ S _ _)
(at level 70, format "'[hv' x '/ ' \i 'n' S ']'") : bool_scope.
Section KeyedQualifier.
Variables (T : Type) (n : nat) (q : qualifier n T).
#[universes(template)]
Structure keyed_qualifier (k : pred_key q) :=
PackKeyedQualifier {unkey_qualifier; _ : unkey_qualifier = q}.
Definition KeyedQualifier k := PackKeyedQualifier k (erefl q).
Variables (k : pred_key q) (k_q : keyed_qualifier k).
Fact keyed_qualifier_suproof : unkey_qualifier k_q =i q.
Proof. by case: k_q => /= _ ->. Qed.
Canonical keyed_qualifier_keyed := PackKeyedPred k keyed_qualifier_suproof.
End KeyedQualifier.
Notation "x \i 's' A" := (x \i n has_quality 0 A)
(at level 70, format "'[hv' x '/ ' \i 's' A ']'") : bool_scope.
Notation "x \i 's' 'a' A" := (x \i n has_quality 1 A)
(at level 70, format "'[hv' x '/ ' \i 's' 'a' A ']'") : bool_scope.
Notation "x \i 's' 'an' A" := (x \i n has_quality 2 A)
(at level 70, format "'[hv' x '/ ' \i 's' 'an' A ']'") : bool_scope.
Module DefaultKeying.
Canonical default_keyed_pred T p := KeyedPred (@DefaultPredKey T p).
Canonical default_keyed_qualifier T n (q : qualifier n T) :=
KeyedQualifier (DefaultPredKey q).
End DefaultKeying.
(** Skolemizing with conditions. **)
Lemma all_tag_cond_dep I T (C : pred I) U :
(forall x, T x) -> (forall x, C x -> {y : T x & U x y}) ->
{f : forall x, T x & forall x, C x -> U x (f x)}.
Proof.
move=> f0 fP; apply: all_tag (fun x y => C x -> U x y) _ => x.
by case Cx: (C x); [case/fP: Cx => y; exists y | exists (f0 x)].
Qed.
Lemma all_tag_cond I T (C : pred I) U :
T -> (forall x, C x -> {y : T & U x y}) ->
{f : I -> T & forall x, C x -> U x (f x)}.
Proof. by move=> y0; apply: all_tag_cond_dep. Qed.
Lemma all_sig_cond_dep I T (C : pred I) P :
(forall x, T x) -> (forall x, C x -> {y : T x | P x y}) ->
{f : forall x, T x | forall x, C x -> P x (f x)}.
Proof. by move=> f0 /(all_tag_cond_dep f0)[f]; exists f. Qed.
Lemma all_sig_cond I T (C : pred I) P :
T -> (forall x, C x -> {y : T | P x y}) ->
{f : I -> T | forall x, C x -> P x (f x)}.
Proof. by move=> y0; apply: all_sig_cond_dep. Qed.
Section RelationProperties.
(**
Caveat: reflexive should not be used to state lemmas, as auto and trivial
will not expand the constant. **)
Variable T : Type.
Variable R : rel T.
Definition total := forall x y, R x y || R y x.
Definition transitive := forall y x z, R x y -> R y z -> R x z.
Definition symmetric := forall x y, R x y = R y x.
Definition antisymmetric := forall x y, R x y && R y x -> x = y.
Definition pre_symmetric := forall x y, R x y -> R y x.
Lemma symmetric_from_pre : pre_symmetric -> symmetric.
Proof. by move=> symR x y; apply/idP/idP; apply: symR. Qed.
Definition reflexive := forall x, R x x.
Definition irreflexive := forall x, R x x = false.
Definition left_transitive := forall x y, R x y -> R x =1 R y.
Definition right_transitive := forall x y, R x y -> R^~ x =1 R^~ y.
Section PER.
Hypotheses (symR : symmetric) (trR : transitive).
Lemma sym_left_transitive : left_transitive.
Proof. by move=> x y Rxy z; apply/idP/idP; apply: trR; rewrite // symR. Qed.
Lemma sym_right_transitive : right_transitive.
Proof. by move=> x y /sym_left_transitive Rxy z; rewrite !(symR z) Rxy. Qed.
End PER.
(**
We define the equivalence property with prenex quantification so that it
can be localized using the {in ..., ..} form defined below. **)
Definition equivalence_rel := forall x y z, R z z * (R x y -> R x z = R y z).
Lemma equivalence_relP : equivalence_rel <-> reflexive /\ left_transitive.
Proof.
split=> [eqiR | [Rxx trR] x y z]; last by split=> [|/trR->].
by split=> [x | x y Rxy z]; [rewrite (eqiR x x x) | rewrite (eqiR x y z)].
Qed.
End RelationProperties.
Lemma rev_trans T (R : rel T) : transitive R -> transitive (fun x y => R y x).
Proof. by move=> trR x y z Ryx Rzy; apply: trR Rzy Ryx. Qed.
(** Property localization **)
Local Notation "{ 'all1' P }" := (forall x, P x : Prop) (at level 0).
Local Notation "{ 'all2' P }" := (forall x y, P x y : Prop) (at level 0).
Local Notation "{ 'all3' P }" := (forall x y z, P x y z: Prop) (at level 0).
Local Notation ph := (phantom _).
Section LocalProperties.
Variables T1 T2 T3 : Type.
Variables (d1 : mem_pred T1) (d2 : mem_pred T2) (d3 : mem_pred T3).
Local Notation ph := (phantom Prop).
Definition prop_for (x : T1) P & ph {all1 P} := P x.
Lemma forE x P phP : @prop_for x P phP = P x. Proof. by []. Qed.
Definition prop_in1 P & ph {all1 P} :=
forall x, in_mem x d1 -> P x.
Definition prop_in11 P & ph {all2 P} :=
forall x y, in_mem x d1 -> in_mem y d2 -> P x y.
Definition prop_in2 P & ph {all2 P} :=
forall x y, in_mem x d1 -> in_mem y d1 -> P x y.
Definition prop_in111 P & ph {all3 P} :=
forall x y z, in_mem x d1 -> in_mem y d2 -> in_mem z d3 -> P x y z.
Definition prop_in12 P & ph {all3 P} :=
forall x y z, in_mem x d1 -> in_mem y d2 -> in_mem z d2 -> P x y z.
Definition prop_in21 P & ph {all3 P} :=
forall x y z, in_mem x d1 -> in_mem y d1 -> in_mem z d2 -> P x y z.
Definition prop_in3 P & ph {all3 P} :=
forall x y z, in_mem x d1 -> in_mem y d1 -> in_mem z d1 -> P x y z.
Variable f : T1 -> T2.
Definition prop_on1 Pf P & phantom T3 (Pf f) & ph {all1 P} :=
forall x, in_mem (f x) d2 -> P x.
Definition prop_on2 Pf P & phantom T3 (Pf f) & ph {all2 P} :=
forall x y, in_mem (f x) d2 -> in_mem (f y) d2 -> P x y.
End LocalProperties.
Definition inPhantom := Phantom Prop.
Definition onPhantom T P (x : T) := Phantom Prop (P x).
Definition bijective_in aT rT (d : mem_pred aT) (f : aT -> rT) :=
exists2 g, prop_in1 d (inPhantom (cancel f g))
& prop_on1 d (Phantom _ (cancel g)) (onPhantom (cancel g) f).
Definition bijective_on aT rT (cd : mem_pred rT) (f : aT -> rT) :=
exists2 g, prop_on1 cd (Phantom _ (cancel f)) (onPhantom (cancel f) g)
& prop_in1 cd (inPhantom (cancel g f)).
Notation "{ 'for' x , P }" :=
(prop_for x (inPhantom P))
(at level 0, format "{ 'for' x , P }") : type_scope.
Notation "{ 'in' d , P }" :=
(prop_in1 (mem d) (inPhantom P))
(at level 0, format "{ 'in' d , P }") : type_scope.
Notation "{ 'in' d1 & d2 , P }" :=
(prop_in11 (mem d1) (mem d2) (inPhantom P))
(at level 0, format "{ 'in' d1 & d2 , P }") : type_scope.
Notation "{ 'in' d & , P }" :=
(prop_in2 (mem d) (inPhantom P))
(at level 0, format "{ 'in' d & , P }") : type_scope.
Notation "{ 'in' d1 & d2 & d3 , P }" :=
(prop_in111 (mem d1) (mem d2) (mem d3) (inPhantom P))
(at level 0, format "{ 'in' d1 & d2 & d3 , P }") : type_scope.
Notation "{ 'in' d1 & & d3 , P }" :=
(prop_in21 (mem d1) (mem d3) (inPhantom P))
(at level 0, format "{ 'in' d1 & & d3 , P }") : type_scope.
Notation "{ 'in' d1 & d2 & , P }" :=
(prop_in12 (mem d1) (mem d2) (inPhantom P))
(at level 0, format "{ 'in' d1 & d2 & , P }") : type_scope.
Notation "{ 'in' d & & , P }" :=
(prop_in3 (mem d) (inPhantom P))
(at level 0, format "{ 'in' d & & , P }") : type_scope.
Notation "{ 'on' cd , P }" :=
(prop_on1 (mem cd) (inPhantom P) (inPhantom P))
(at level 0, format "{ 'on' cd , P }") : type_scope.
Notation "{ 'on' cd & , P }" :=
(prop_on2 (mem cd) (inPhantom P) (inPhantom P))
(at level 0, format "{ 'on' cd & , P }") : type_scope.
Local Arguments onPhantom {_%type_scope} _ _.
Notation "{ 'on' cd , P & g }" :=
(prop_on1 (mem cd) (Phantom (_ -> Prop) P) (onPhantom P g))
(at level 0, format "{ 'on' cd , P & g }") : type_scope.
Notation "{ 'in' d , 'bijective' f }" := (bijective_in (mem d) f)
(at level 0, f at level 8,
format "{ 'in' d , 'bijective' f }") : type_scope.
Notation "{ 'on' cd , 'bijective' f }" := (bijective_on (mem cd) f)
(at level 0, f at level 8,
format "{ 'on' cd , 'bijective' f }") : type_scope.
(**
Weakening and monotonicity lemmas for localized predicates.
Note that using these lemmas in backward reasoning will force expansion of
the predicate definition, as Coq needs to expose the quantifier to apply
these lemmas. We define a few specialized variants to avoid this for some
of the ssrfun predicates. **)
Section LocalGlobal.
Variables T1 T2 T3 : predArgType.
Variables (D1 : pred T1) (D2 : pred T2) (D3 : pred T3).
Variables (d1 d1' : mem_pred T1) (d2 d2' : mem_pred T2) (d3 d3' : mem_pred T3).
Variables (f f' : T1 -> T2) (g : T2 -> T1) (h : T3).
Variables (P1 : T1 -> Prop) (P2 : T1 -> T2 -> Prop).
Variable P3 : T1 -> T2 -> T3 -> Prop.
Variable Q1 : (T1 -> T2) -> T1 -> Prop.
Variable Q1l : (T1 -> T2) -> T3 -> T1 -> Prop.
Variable Q2 : (T1 -> T2) -> T1 -> T1 -> Prop.
Hypothesis sub1 : sub_mem d1 d1'.
Hypothesis sub2 : sub_mem d2 d2'.
Hypothesis sub3 : sub_mem d3 d3'.
Lemma in1W : {all1 P1} -> {in D1, {all1 P1}}.
Proof. by move=> ? ?. Qed.
Lemma in2W : {all2 P2} -> {in D1 & D2, {all2 P2}}.
Proof. by move=> ? ?. Qed.
Lemma in3W : {all3 P3} -> {in D1 & D2 & D3, {all3 P3}}.
Proof. by move=> ? ?. Qed.
Lemma in1T : {in T1, {all1 P1}} -> {all1 P1}.
Proof. by move=> ? ?; auto. Qed.
Lemma in2T : {in T1 & T2, {all2 P2}} -> {all2 P2}.
Proof. by move=> ? ?; auto. Qed.
Lemma in3T : {in T1 & T2 & T3, {all3 P3}} -> {all3 P3}.
Proof. by move=> ? ?; auto. Qed.
Lemma sub_in1 (Ph : ph {all1 P1}) : prop_in1 d1' Ph -> prop_in1 d1 Ph.
Proof. by move=> allP x /sub1; apply: allP. Qed.
Lemma sub_in11 (Ph : ph {all2 P2}) : prop_in11 d1' d2' Ph -> prop_in11 d1 d2 Ph.
Proof. by move=> allP x1 x2 /sub1 d1x1 /sub2; apply: allP. Qed.
Lemma sub_in111 (Ph : ph {all3 P3}) :
prop_in111 d1' d2' d3' Ph -> prop_in111 d1 d2 d3 Ph.
Proof. by move=> allP x1 x2 x3 /sub1 d1x1 /sub2 d2x2 /sub3; apply: allP. Qed.
Let allQ1 f'' := {all1 Q1 f''}.
Let allQ1l f'' h' := {all1 Q1l f'' h'}.
Let allQ2 f'' := {all2 Q2 f''}.
Lemma on1W : allQ1 f -> {on D2, allQ1 f}. Proof. by move=> ? ?. Qed.
Lemma on1lW : allQ1l f h -> {on D2, allQ1l f & h}. Proof. by move=> ? ?. Qed.
Lemma on2W : allQ2 f -> {on D2 &, allQ2 f}. Proof. by move=> ? ?. Qed.
Lemma on1T : {on T2, allQ1 f} -> allQ1 f. Proof. by move=> ? ?; auto. Qed.
Lemma on1lT : {on T2, allQ1l f & h} -> allQ1l f h.
Proof. by move=> ? ?; auto. Qed.
Lemma on2T : {on T2 &, allQ2 f} -> allQ2 f.
Proof. by move=> ? ?; auto. Qed.
Lemma subon1 (Phf : ph (allQ1 f)) (Ph : ph (allQ1 f)) :
prop_on1 d2' Phf Ph -> prop_on1 d2 Phf Ph.
Proof. by move=> allQ x /sub2; apply: allQ. Qed.
Lemma subon1l (Phf : ph (allQ1l f)) (Ph : ph (allQ1l f h)) :
prop_on1 d2' Phf Ph -> prop_on1 d2 Phf Ph.
Proof. by move=> allQ x /sub2; apply: allQ. Qed.
Lemma subon2 (Phf : ph (allQ2 f)) (Ph : ph (allQ2 f)) :
prop_on2 d2' Phf Ph -> prop_on2 d2 Phf Ph.
Proof. by move=> allQ x y /sub2=> d2fx /sub2; apply: allQ. Qed.
Lemma can_in_inj : {in D1, cancel f g} -> {in D1 &, injective f}.
Proof. by move=> fK x y /fK{2}<- /fK{2}<- ->. Qed.
Lemma canLR_in x y : {in D1, cancel f g} -> y \in D1 -> x = f y -> g x = y.
Proof. by move=> fK D1y ->; rewrite fK. Qed.
Lemma canRL_in x y : {in D1, cancel f g} -> x \in D1 -> f x = y -> x = g y.
Proof. by move=> fK D1x <-; rewrite fK. Qed.
Lemma on_can_inj : {on D2, cancel f & g} -> {on D2 &, injective f}.
Proof. by move=> fK x y /fK{2}<- /fK{2}<- ->. Qed.
Lemma canLR_on x y : {on D2, cancel f & g} -> f y \in D2 -> x = f y -> g x = y.
Proof. by move=> fK D2fy ->; rewrite fK. Qed.
Lemma canRL_on x y : {on D2, cancel f & g} -> f x \in D2 -> f x = y -> x = g y.
Proof. by move=> fK D2fx <-; rewrite fK. Qed.
Lemma inW_bij : bijective f -> {in D1, bijective f}.
Proof. by case=> g' fK g'K; exists g' => * ? *; auto. Qed.
Lemma onW_bij : bijective f -> {on D2, bijective f}.
Proof. by case=> g' fK g'K; exists g' => * ? *; auto. Qed.
Lemma inT_bij : {in T1, bijective f} -> bijective f.
Proof. by case=> g' fK g'K; exists g' => * ? *; auto. Qed.
Lemma onT_bij : {on T2, bijective f} -> bijective f.
Proof. by case=> g' fK g'K; exists g' => * ? *; auto. Qed.
Lemma sub_in_bij (D1' : pred T1) :
{subset D1 <= D1'} -> {in D1', bijective f} -> {in D1, bijective f}.
Proof.
by move=> subD [g' fK g'K]; exists g' => x; move/subD; [apply: fK | apply: g'K].
Qed.
Lemma subon_bij (D2' : pred T2) :
{subset D2 <= D2'} -> {on D2', bijective f} -> {on D2, bijective f}.
Proof.
by move=> subD [g' fK g'K]; exists g' => x; move/subD; [apply: fK | apply: g'K].
Qed.
End LocalGlobal.
Lemma sub_in2 T d d' (P : T -> T -> Prop) :
sub_mem d d' -> forall Ph : ph {all2 P}, prop_in2 d' Ph -> prop_in2 d Ph.
Proof. by move=> /= sub_dd'; apply: sub_in11. Qed.
Lemma sub_in3 T d d' (P : T -> T -> T -> Prop) :
sub_mem d d' -> forall Ph : ph {all3 P}, prop_in3 d' Ph -> prop_in3 d Ph.
Proof. by move=> /= sub_dd'; apply: sub_in111. Qed.
Lemma sub_in12 T1 T d1 d1' d d' (P : T1 -> T -> T -> Prop) :
sub_mem d1 d1' -> sub_mem d d' ->
forall Ph : ph {all3 P}, prop_in12 d1' d' Ph -> prop_in12 d1 d Ph.
Proof. by move=> /= sub1 sub; apply: sub_in111. Qed.
Lemma sub_in21 T T3 d d' d3 d3' (P : T -> T -> T3 -> Prop) :
sub_mem d d' -> sub_mem d3 d3' ->
forall Ph : ph {all3 P}, prop_in21 d' d3' Ph -> prop_in21 d d3 Ph.
Proof. by move=> /= sub sub3; apply: sub_in111. Qed.
Lemma equivalence_relP_in T (R : rel T) (A : pred T) :
{in A & &, equivalence_rel R}
<-> {in A, reflexive R} /\ {in A &, forall x y, R x y -> {in A, R x =1 R y}}.
Proof.
split=> [eqiR | [Rxx trR] x y z *]; last by split=> [|/trR-> //]; apply: Rxx.
by split=> [x Ax|x y Ax Ay Rxy z Az]; [rewrite (eqiR x x) | rewrite (eqiR x y)].
Qed.
Section MonoHomoMorphismTheory.
Variables (aT rT sT : Type) (f : aT -> rT) (g : rT -> aT).
Variables (aP : pred aT) (rP : pred rT) (aR : rel aT) (rR : rel rT).
Lemma monoW : {mono f : x / aP x >-> rP x} -> {homo f : x / aP x >-> rP x}.
Proof. by move=> hf x ax; rewrite hf. Qed.
Lemma mono2W :
{mono f : x y / aR x y >-> rR x y} -> {homo f : x y / aR x y >-> rR x y}.
Proof. by move=> hf x y axy; rewrite hf. Qed.
Hypothesis fgK : cancel g f.
Lemma homoRL :
{homo f : x y / aR x y >-> rR x y} -> forall x y, aR (g x) y -> rR x (f y).
Proof. by move=> Hf x y /Hf; rewrite fgK. Qed.
Lemma homoLR :
{homo f : x y / aR x y >-> rR x y} -> forall x y, aR x (g y) -> rR (f x) y.
Proof. by move=> Hf x y /Hf; rewrite fgK. Qed.
Lemma homo_mono :
{homo f : x y / aR x y >-> rR x y} -> {homo g : x y / rR x y >-> aR x y} ->
{mono g : x y / rR x y >-> aR x y}.
Proof.
move=> mf mg x y; case: (boolP (rR _ _))=> [/mg //|].
by apply: contraNF=> /mf; rewrite !fgK.
Qed.
Lemma monoLR :
{mono f : x y / aR x y >-> rR x y} -> forall x y, rR (f x) y = aR x (g y).
Proof. by move=> mf x y; rewrite -{1}[y]fgK mf. Qed.
Lemma monoRL :
{mono f : x y / aR x y >-> rR x y} -> forall x y, rR x (f y) = aR (g x) y.
Proof. by move=> mf x y; rewrite -{1}[x]fgK mf. Qed.
Lemma can_mono :
{mono f : x y / aR x y >-> rR x y} -> {mono g : x y / rR x y >-> aR x y}.
Proof. by move=> mf x y /=; rewrite -mf !fgK. Qed.
End MonoHomoMorphismTheory.
Section MonoHomoMorphismTheory_in.
Variables (aT rT sT : predArgType) (f : aT -> rT) (g : rT -> aT).
Variable (aD : pred aT).
Variable (aP : pred aT) (rP : pred rT) (aR : rel aT) (rR : rel rT).
Notation rD := [pred x | g x \in aD].
Lemma monoW_in :
{in aD &, {mono f : x y / aR x y >-> rR x y}} ->
{in aD &, {homo f : x y / aR x y >-> rR x y}}.
Proof. by move=> hf x y hx hy axy; rewrite hf. Qed.
Lemma mono2W_in :
{in aD, {mono f : x / aP x >-> rP x}} ->
{in aD, {homo f : x / aP x >-> rP x}}.
Proof. by move=> hf x hx ax; rewrite hf. Qed.
Hypothesis fgK_on : {on aD, cancel g & f}.
Lemma homoRL_in :
{in aD &, {homo f : x y / aR x y >-> rR x y}} ->
{in rD & aD, forall x y, aR (g x) y -> rR x (f y)}.
Proof. by move=> Hf x y hx hy /Hf; rewrite fgK_on //; apply. Qed.
Lemma homoLR_in :
{in aD &, {homo f : x y / aR x y >-> rR x y}} ->
{in aD & rD, forall x y, aR x (g y) -> rR (f x) y}.
Proof. by move=> Hf x y hx hy /Hf; rewrite fgK_on //; apply. Qed.
Lemma homo_mono_in :
{in aD &, {homo f : x y / aR x y >-> rR x y}} ->
{in rD &, {homo g : x y / rR x y >-> aR x y}} ->
{in rD &, {mono g : x y / rR x y >-> aR x y}}.
Proof.
move=> mf mg x y hx hy; case: (boolP (rR _ _))=> [/mg //|]; first exact.
by apply: contraNF=> /mf; rewrite !fgK_on //; apply.
Qed.
Lemma monoLR_in :
{in aD &, {mono f : x y / aR x y >-> rR x y}} ->
{in aD & rD, forall x y, rR (f x) y = aR x (g y)}.
Proof. by move=> mf x y hx hy; rewrite -{1}[y]fgK_on // mf. Qed.
Lemma monoRL_in :
{in aD &, {mono f : x y / aR x y >-> rR x y}} ->
{in rD & aD, forall x y, rR x (f y) = aR (g x) y}.
Proof. by move=> mf x y hx hy; rewrite -{1}[x]fgK_on // mf. Qed.
Lemma can_mono_in :
{in aD &, {mono f : x y / aR x y >-> rR x y}} ->
{in rD &, {mono g : x y / rR x y >-> aR x y}}.
Proof. by move=> mf x y hx hy /=; rewrite -mf // !fgK_on. Qed.
End MonoHomoMorphismTheory_in.
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__DFSTP_SYMBOL_V
`define SKY130_FD_SC_HDLL__DFSTP_SYMBOL_V
/**
* dfstp: Delay flop, inverted set, single output.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__dfstp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input SET_B,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__DFSTP_SYMBOL_V
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_crossbar:2.1
// IP Revision: 8
(* X_CORE_INFO = "axi_crossbar_v2_1_8_axi_crossbar,Vivado 2015.4" *)
(* CHECK_LICENSE_TYPE = "zc702_xbar_1,axi_crossbar_v2_1_8_axi_crossbar,{}" *)
(* CORE_GENERATION_INFO = "zc702_xbar_1,axi_crossbar_v2_1_8_axi_crossbar,{x_ipProduct=Vivado 2015.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_crossbar,x_ipVersion=2.1,x_ipCoreRevision=8,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_NUM_SLAVE_SLOTS=2,C_NUM_MASTER_SLOTS=1,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_PROTOCOL=0,C_NUM_ADDR_RANGES=3,C_M_AXI_BASE_ADDR=0x00000000fc00000000000000e00000000000000000000000,C_M_AXI_ADDR_WIDTH=0x00000018000000160000001f,C_S_AXI_BASE_ID=0x0000000100000000,C_S_AXI_THREAD_ID_WIDTH=0x0000000000000000,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_M_AXI_WRITE_CONNECTIVITY=0x00000003,C_M_AXI_READ_CONNECTIVITY=0x00000003,C_R_REGISTER=0,C_S_AXI_SINGLE_THREAD=0x0000000000000000,C_S_AXI_WRITE_ACCEPTANCE=0x0000000400000004,C_S_AXI_READ_ACCEPTANCE=0x0000000400000004,C_M_AXI_WRITE_ISSUING=0x00000008,C_M_AXI_READ_ISSUING=0x00000008,C_S_AXI_ARB_PRIORITY=0x0000000000000000,C_M_AXI_SECURE=0x00000000,C_CONNECTIVITY_MODE=1}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module zc702_xbar_1 (
aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awid,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awregion,
m_axi_awqos,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wvalid,
m_axi_wready,
m_axi_bid,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_arid,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arregion,
m_axi_arqos,
m_axi_arvalid,
m_axi_arready,
m_axi_rid,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLKIF CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RSTIF RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI AWID [0:0] [1:1]" *)
input wire [1 : 0] s_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 S01_AXI AWADDR [31:0] [63:32]" *)
input wire [63 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWLEN [7:0] [7:0], xilinx.com:interface:aximm:1.0 S01_AXI AWLEN [7:0] [15:8]" *)
input wire [15 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWSIZE [2:0] [2:0], xilinx.com:interface:aximm:1.0 S01_AXI AWSIZE [2:0] [5:3]" *)
input wire [5 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWBURST [1:0] [1:0], xilinx.com:interface:aximm:1.0 S01_AXI AWBURST [1:0] [3:2]" *)
input wire [3 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWLOCK [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI AWLOCK [0:0] [1:1]" *)
input wire [1 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWCACHE [3:0] [3:0], xilinx.com:interface:aximm:1.0 S01_AXI AWCACHE [3:0] [7:4]" *)
input wire [7 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 S01_AXI AWPROT [2:0] [5:3]" *)
input wire [5 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWQOS [3:0] [3:0], xilinx.com:interface:aximm:1.0 S01_AXI AWQOS [3:0] [7:4]" *)
input wire [7 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI AWVALID [0:0] [1:1]" *)
input wire [1 : 0] s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI AWREADY [0:0] [1:1]" *)
output wire [1 : 0] s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WDATA [63:0] [63:0], xilinx.com:interface:aximm:1.0 S01_AXI WDATA [63:0] [127:64]" *)
input wire [127 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB [7:0] [7:0], xilinx.com:interface:aximm:1.0 S01_AXI WSTRB [7:0] [15:8]" *)
input wire [15 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WLAST [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI WLAST [0:0] [1:1]" *)
input wire [1 : 0] s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI WVALID [0:0] [1:1]" *)
input wire [1 : 0] s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI WREADY [0:0] [1:1]" *)
output wire [1 : 0] s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI BID [0:0] [1:1]" *)
output wire [1 : 0] s_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 S01_AXI BRESP [1:0] [3:2]" *)
output wire [3 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI BVALID [0:0] [1:1]" *)
output wire [1 : 0] s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI BREADY [0:0] [1:1]" *)
input wire [1 : 0] s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI ARID [0:0] [1:1]" *)
input wire [1 : 0] s_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 S01_AXI ARADDR [31:0] [63:32]" *)
input wire [63 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARLEN [7:0] [7:0], xilinx.com:interface:aximm:1.0 S01_AXI ARLEN [7:0] [15:8]" *)
input wire [15 : 0] s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARSIZE [2:0] [2:0], xilinx.com:interface:aximm:1.0 S01_AXI ARSIZE [2:0] [5:3]" *)
input wire [5 : 0] s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARBURST [1:0] [1:0], xilinx.com:interface:aximm:1.0 S01_AXI ARBURST [1:0] [3:2]" *)
input wire [3 : 0] s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARLOCK [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI ARLOCK [0:0] [1:1]" *)
input wire [1 : 0] s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARCACHE [3:0] [3:0], xilinx.com:interface:aximm:1.0 S01_AXI ARCACHE [3:0] [7:4]" *)
input wire [7 : 0] s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 S01_AXI ARPROT [2:0] [5:3]" *)
input wire [5 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARQOS [3:0] [3:0], xilinx.com:interface:aximm:1.0 S01_AXI ARQOS [3:0] [7:4]" *)
input wire [7 : 0] s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI ARVALID [0:0] [1:1]" *)
input wire [1 : 0] s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI ARREADY [0:0] [1:1]" *)
output wire [1 : 0] s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI RID [0:0] [1:1]" *)
output wire [1 : 0] s_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RDATA [63:0] [63:0], xilinx.com:interface:aximm:1.0 S01_AXI RDATA [63:0] [127:64]" *)
output wire [127 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 S01_AXI RRESP [1:0] [3:2]" *)
output wire [3 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RLAST [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI RLAST [0:0] [1:1]" *)
output wire [1 : 0] s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI RVALID [0:0] [1:1]" *)
output wire [1 : 0] s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI RREADY [0:0] [1:1]" *)
input wire [1 : 0] s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWID" *)
output wire [0 : 0] m_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWADDR" *)
output wire [31 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWLEN" *)
output wire [7 : 0] m_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWSIZE" *)
output wire [2 : 0] m_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWBURST" *)
output wire [1 : 0] m_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWLOCK" *)
output wire [0 : 0] m_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWCACHE" *)
output wire [3 : 0] m_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWREGION" *)
output wire [3 : 0] m_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWQOS" *)
output wire [3 : 0] m_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWVALID" *)
output wire [0 : 0] m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWREADY" *)
input wire [0 : 0] m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WDATA" *)
output wire [63 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WSTRB" *)
output wire [7 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WLAST" *)
output wire [0 : 0] m_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WVALID" *)
output wire [0 : 0] m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WREADY" *)
input wire [0 : 0] m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BID" *)
input wire [0 : 0] m_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BVALID" *)
input wire [0 : 0] m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BREADY" *)
output wire [0 : 0] m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARID" *)
output wire [0 : 0] m_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARADDR" *)
output wire [31 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARLEN" *)
output wire [7 : 0] m_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARSIZE" *)
output wire [2 : 0] m_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARBURST" *)
output wire [1 : 0] m_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARLOCK" *)
output wire [0 : 0] m_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARCACHE" *)
output wire [3 : 0] m_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARPROT" *)
output wire [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARREGION" *)
output wire [3 : 0] m_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARQOS" *)
output wire [3 : 0] m_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARVALID" *)
output wire [0 : 0] m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARREADY" *)
input wire [0 : 0] m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RID" *)
input wire [0 : 0] m_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RDATA" *)
input wire [63 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RRESP" *)
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RLAST" *)
input wire [0 : 0] m_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RVALID" *)
input wire [0 : 0] m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RREADY" *)
output wire [0 : 0] m_axi_rready;
axi_crossbar_v2_1_8_axi_crossbar #(
.C_FAMILY("zynq"),
.C_NUM_SLAVE_SLOTS(2),
.C_NUM_MASTER_SLOTS(1),
.C_AXI_ID_WIDTH(1),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(64),
.C_AXI_PROTOCOL(0),
.C_NUM_ADDR_RANGES(3),
.C_M_AXI_BASE_ADDR(192'H00000000fc00000000000000e00000000000000000000000),
.C_M_AXI_ADDR_WIDTH(96'H00000018000000160000001f),
.C_S_AXI_BASE_ID(64'H0000000100000000),
.C_S_AXI_THREAD_ID_WIDTH(64'H0000000000000000),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_M_AXI_WRITE_CONNECTIVITY(32'H00000003),
.C_M_AXI_READ_CONNECTIVITY(32'H00000003),
.C_R_REGISTER(0),
.C_S_AXI_SINGLE_THREAD(64'H0000000000000000),
.C_S_AXI_WRITE_ACCEPTANCE(64'H0000000400000004),
.C_S_AXI_READ_ACCEPTANCE(64'H0000000400000004),
.C_M_AXI_WRITE_ISSUING(32'H00000008),
.C_M_AXI_READ_ISSUING(32'H00000008),
.C_S_AXI_ARB_PRIORITY(64'H0000000000000000),
.C_M_AXI_SECURE(32'H00000000),
.C_CONNECTIVITY_MODE(1)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(s_axi_awid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awqos(s_axi_awqos),
.s_axi_awuser(2'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(2'H0),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wuser(2'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(s_axi_bid),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(s_axi_arid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arqos(s_axi_arqos),
.s_axi_aruser(2'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(s_axi_rid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(m_axi_awid),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(m_axi_awlen),
.m_axi_awsize(m_axi_awsize),
.m_axi_awburst(m_axi_awburst),
.m_axi_awlock(m_axi_awlock),
.m_axi_awcache(m_axi_awcache),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(m_axi_awregion),
.m_axi_awqos(m_axi_awqos),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(m_axi_wlast),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(m_axi_bid),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(m_axi_arid),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(m_axi_arlen),
.m_axi_arsize(m_axi_arsize),
.m_axi_arburst(m_axi_arburst),
.m_axi_arlock(m_axi_arlock),
.m_axi_arcache(m_axi_arcache),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(m_axi_arregion),
.m_axi_arqos(m_axi_arqos),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(m_axi_rid),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(m_axi_rlast),
.m_axi_ruser(1'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
//Legal Notice: (C)2017 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module system1_nios2_gen2_0_cpu_test_bench (
// inputs:
D_iw,
D_iw_op,
D_iw_opx,
D_valid,
E_valid,
F_pcb,
F_valid,
R_ctrl_ld,
R_ctrl_ld_non_io,
R_dst_regnum,
R_wr_dst_reg,
W_valid,
W_vinst,
W_wr_data,
av_ld_data_aligned_unfiltered,
clk,
d_address,
d_byteenable,
d_read,
d_write,
i_address,
i_read,
i_readdata,
i_waitrequest,
reset_n,
// outputs:
av_ld_data_aligned_filtered,
test_has_ended
)
;
output [ 31: 0] av_ld_data_aligned_filtered;
output test_has_ended;
input [ 31: 0] D_iw;
input [ 5: 0] D_iw_op;
input [ 5: 0] D_iw_opx;
input D_valid;
input E_valid;
input [ 20: 0] F_pcb;
input F_valid;
input R_ctrl_ld;
input R_ctrl_ld_non_io;
input [ 4: 0] R_dst_regnum;
input R_wr_dst_reg;
input W_valid;
input [ 71: 0] W_vinst;
input [ 31: 0] W_wr_data;
input [ 31: 0] av_ld_data_aligned_unfiltered;
input clk;
input [ 20: 0] d_address;
input [ 3: 0] d_byteenable;
input d_read;
input d_write;
input [ 20: 0] i_address;
input i_read;
input [ 31: 0] i_readdata;
input i_waitrequest;
input reset_n;
wire D_is_opx_inst;
wire D_op_add;
wire D_op_addi;
wire D_op_and;
wire D_op_andhi;
wire D_op_andi;
wire D_op_beq;
wire D_op_bge;
wire D_op_bgeu;
wire D_op_blt;
wire D_op_bltu;
wire D_op_bne;
wire D_op_br;
wire D_op_break;
wire D_op_bret;
wire D_op_call;
wire D_op_callr;
wire D_op_cmpeq;
wire D_op_cmpeqi;
wire D_op_cmpge;
wire D_op_cmpgei;
wire D_op_cmpgeu;
wire D_op_cmpgeui;
wire D_op_cmplt;
wire D_op_cmplti;
wire D_op_cmpltu;
wire D_op_cmpltui;
wire D_op_cmpne;
wire D_op_cmpnei;
wire D_op_crst;
wire D_op_custom;
wire D_op_div;
wire D_op_divu;
wire D_op_eret;
wire D_op_flushd;
wire D_op_flushda;
wire D_op_flushi;
wire D_op_flushp;
wire D_op_hbreak;
wire D_op_initd;
wire D_op_initda;
wire D_op_initi;
wire D_op_intr;
wire D_op_jmp;
wire D_op_jmpi;
wire D_op_ldb;
wire D_op_ldbio;
wire D_op_ldbu;
wire D_op_ldbuio;
wire D_op_ldh;
wire D_op_ldhio;
wire D_op_ldhu;
wire D_op_ldhuio;
wire D_op_ldl;
wire D_op_ldw;
wire D_op_ldwio;
wire D_op_mul;
wire D_op_muli;
wire D_op_mulxss;
wire D_op_mulxsu;
wire D_op_mulxuu;
wire D_op_nextpc;
wire D_op_nor;
wire D_op_op_rsv02;
wire D_op_op_rsv09;
wire D_op_op_rsv10;
wire D_op_op_rsv17;
wire D_op_op_rsv18;
wire D_op_op_rsv25;
wire D_op_op_rsv26;
wire D_op_op_rsv33;
wire D_op_op_rsv34;
wire D_op_op_rsv41;
wire D_op_op_rsv42;
wire D_op_op_rsv49;
wire D_op_op_rsv57;
wire D_op_op_rsv61;
wire D_op_op_rsv62;
wire D_op_op_rsv63;
wire D_op_opx_rsv00;
wire D_op_opx_rsv10;
wire D_op_opx_rsv15;
wire D_op_opx_rsv17;
wire D_op_opx_rsv21;
wire D_op_opx_rsv25;
wire D_op_opx_rsv33;
wire D_op_opx_rsv34;
wire D_op_opx_rsv35;
wire D_op_opx_rsv42;
wire D_op_opx_rsv43;
wire D_op_opx_rsv44;
wire D_op_opx_rsv47;
wire D_op_opx_rsv50;
wire D_op_opx_rsv51;
wire D_op_opx_rsv55;
wire D_op_opx_rsv56;
wire D_op_opx_rsv60;
wire D_op_opx_rsv63;
wire D_op_or;
wire D_op_orhi;
wire D_op_ori;
wire D_op_rdctl;
wire D_op_rdprs;
wire D_op_ret;
wire D_op_rol;
wire D_op_roli;
wire D_op_ror;
wire D_op_sll;
wire D_op_slli;
wire D_op_sra;
wire D_op_srai;
wire D_op_srl;
wire D_op_srli;
wire D_op_stb;
wire D_op_stbio;
wire D_op_stc;
wire D_op_sth;
wire D_op_sthio;
wire D_op_stw;
wire D_op_stwio;
wire D_op_sub;
wire D_op_sync;
wire D_op_trap;
wire D_op_wrctl;
wire D_op_wrprs;
wire D_op_xor;
wire D_op_xorhi;
wire D_op_xori;
wire [ 31: 0] av_ld_data_aligned_filtered;
wire av_ld_data_aligned_unfiltered_0_is_x;
wire av_ld_data_aligned_unfiltered_10_is_x;
wire av_ld_data_aligned_unfiltered_11_is_x;
wire av_ld_data_aligned_unfiltered_12_is_x;
wire av_ld_data_aligned_unfiltered_13_is_x;
wire av_ld_data_aligned_unfiltered_14_is_x;
wire av_ld_data_aligned_unfiltered_15_is_x;
wire av_ld_data_aligned_unfiltered_16_is_x;
wire av_ld_data_aligned_unfiltered_17_is_x;
wire av_ld_data_aligned_unfiltered_18_is_x;
wire av_ld_data_aligned_unfiltered_19_is_x;
wire av_ld_data_aligned_unfiltered_1_is_x;
wire av_ld_data_aligned_unfiltered_20_is_x;
wire av_ld_data_aligned_unfiltered_21_is_x;
wire av_ld_data_aligned_unfiltered_22_is_x;
wire av_ld_data_aligned_unfiltered_23_is_x;
wire av_ld_data_aligned_unfiltered_24_is_x;
wire av_ld_data_aligned_unfiltered_25_is_x;
wire av_ld_data_aligned_unfiltered_26_is_x;
wire av_ld_data_aligned_unfiltered_27_is_x;
wire av_ld_data_aligned_unfiltered_28_is_x;
wire av_ld_data_aligned_unfiltered_29_is_x;
wire av_ld_data_aligned_unfiltered_2_is_x;
wire av_ld_data_aligned_unfiltered_30_is_x;
wire av_ld_data_aligned_unfiltered_31_is_x;
wire av_ld_data_aligned_unfiltered_3_is_x;
wire av_ld_data_aligned_unfiltered_4_is_x;
wire av_ld_data_aligned_unfiltered_5_is_x;
wire av_ld_data_aligned_unfiltered_6_is_x;
wire av_ld_data_aligned_unfiltered_7_is_x;
wire av_ld_data_aligned_unfiltered_8_is_x;
wire av_ld_data_aligned_unfiltered_9_is_x;
wire test_has_ended;
assign D_op_call = D_iw_op == 0;
assign D_op_jmpi = D_iw_op == 1;
assign D_op_op_rsv02 = D_iw_op == 2;
assign D_op_ldbu = D_iw_op == 3;
assign D_op_addi = D_iw_op == 4;
assign D_op_stb = D_iw_op == 5;
assign D_op_br = D_iw_op == 6;
assign D_op_ldb = D_iw_op == 7;
assign D_op_cmpgei = D_iw_op == 8;
assign D_op_op_rsv09 = D_iw_op == 9;
assign D_op_op_rsv10 = D_iw_op == 10;
assign D_op_ldhu = D_iw_op == 11;
assign D_op_andi = D_iw_op == 12;
assign D_op_sth = D_iw_op == 13;
assign D_op_bge = D_iw_op == 14;
assign D_op_ldh = D_iw_op == 15;
assign D_op_cmplti = D_iw_op == 16;
assign D_op_op_rsv17 = D_iw_op == 17;
assign D_op_op_rsv18 = D_iw_op == 18;
assign D_op_initda = D_iw_op == 19;
assign D_op_ori = D_iw_op == 20;
assign D_op_stw = D_iw_op == 21;
assign D_op_blt = D_iw_op == 22;
assign D_op_ldw = D_iw_op == 23;
assign D_op_cmpnei = D_iw_op == 24;
assign D_op_op_rsv25 = D_iw_op == 25;
assign D_op_op_rsv26 = D_iw_op == 26;
assign D_op_flushda = D_iw_op == 27;
assign D_op_xori = D_iw_op == 28;
assign D_op_stc = D_iw_op == 29;
assign D_op_bne = D_iw_op == 30;
assign D_op_ldl = D_iw_op == 31;
assign D_op_cmpeqi = D_iw_op == 32;
assign D_op_op_rsv33 = D_iw_op == 33;
assign D_op_op_rsv34 = D_iw_op == 34;
assign D_op_ldbuio = D_iw_op == 35;
assign D_op_muli = D_iw_op == 36;
assign D_op_stbio = D_iw_op == 37;
assign D_op_beq = D_iw_op == 38;
assign D_op_ldbio = D_iw_op == 39;
assign D_op_cmpgeui = D_iw_op == 40;
assign D_op_op_rsv41 = D_iw_op == 41;
assign D_op_op_rsv42 = D_iw_op == 42;
assign D_op_ldhuio = D_iw_op == 43;
assign D_op_andhi = D_iw_op == 44;
assign D_op_sthio = D_iw_op == 45;
assign D_op_bgeu = D_iw_op == 46;
assign D_op_ldhio = D_iw_op == 47;
assign D_op_cmpltui = D_iw_op == 48;
assign D_op_op_rsv49 = D_iw_op == 49;
assign D_op_custom = D_iw_op == 50;
assign D_op_initd = D_iw_op == 51;
assign D_op_orhi = D_iw_op == 52;
assign D_op_stwio = D_iw_op == 53;
assign D_op_bltu = D_iw_op == 54;
assign D_op_ldwio = D_iw_op == 55;
assign D_op_rdprs = D_iw_op == 56;
assign D_op_op_rsv57 = D_iw_op == 57;
assign D_op_flushd = D_iw_op == 59;
assign D_op_xorhi = D_iw_op == 60;
assign D_op_op_rsv61 = D_iw_op == 61;
assign D_op_op_rsv62 = D_iw_op == 62;
assign D_op_op_rsv63 = D_iw_op == 63;
assign D_op_opx_rsv00 = (D_iw_opx == 0) & D_is_opx_inst;
assign D_op_eret = (D_iw_opx == 1) & D_is_opx_inst;
assign D_op_roli = (D_iw_opx == 2) & D_is_opx_inst;
assign D_op_rol = (D_iw_opx == 3) & D_is_opx_inst;
assign D_op_flushp = (D_iw_opx == 4) & D_is_opx_inst;
assign D_op_ret = (D_iw_opx == 5) & D_is_opx_inst;
assign D_op_nor = (D_iw_opx == 6) & D_is_opx_inst;
assign D_op_mulxuu = (D_iw_opx == 7) & D_is_opx_inst;
assign D_op_cmpge = (D_iw_opx == 8) & D_is_opx_inst;
assign D_op_bret = (D_iw_opx == 9) & D_is_opx_inst;
assign D_op_opx_rsv10 = (D_iw_opx == 10) & D_is_opx_inst;
assign D_op_ror = (D_iw_opx == 11) & D_is_opx_inst;
assign D_op_flushi = (D_iw_opx == 12) & D_is_opx_inst;
assign D_op_jmp = (D_iw_opx == 13) & D_is_opx_inst;
assign D_op_and = (D_iw_opx == 14) & D_is_opx_inst;
assign D_op_opx_rsv15 = (D_iw_opx == 15) & D_is_opx_inst;
assign D_op_cmplt = (D_iw_opx == 16) & D_is_opx_inst;
assign D_op_opx_rsv17 = (D_iw_opx == 17) & D_is_opx_inst;
assign D_op_slli = (D_iw_opx == 18) & D_is_opx_inst;
assign D_op_sll = (D_iw_opx == 19) & D_is_opx_inst;
assign D_op_wrprs = (D_iw_opx == 20) & D_is_opx_inst;
assign D_op_opx_rsv21 = (D_iw_opx == 21) & D_is_opx_inst;
assign D_op_or = (D_iw_opx == 22) & D_is_opx_inst;
assign D_op_mulxsu = (D_iw_opx == 23) & D_is_opx_inst;
assign D_op_cmpne = (D_iw_opx == 24) & D_is_opx_inst;
assign D_op_opx_rsv25 = (D_iw_opx == 25) & D_is_opx_inst;
assign D_op_srli = (D_iw_opx == 26) & D_is_opx_inst;
assign D_op_srl = (D_iw_opx == 27) & D_is_opx_inst;
assign D_op_nextpc = (D_iw_opx == 28) & D_is_opx_inst;
assign D_op_callr = (D_iw_opx == 29) & D_is_opx_inst;
assign D_op_xor = (D_iw_opx == 30) & D_is_opx_inst;
assign D_op_mulxss = (D_iw_opx == 31) & D_is_opx_inst;
assign D_op_cmpeq = (D_iw_opx == 32) & D_is_opx_inst;
assign D_op_opx_rsv33 = (D_iw_opx == 33) & D_is_opx_inst;
assign D_op_opx_rsv34 = (D_iw_opx == 34) & D_is_opx_inst;
assign D_op_opx_rsv35 = (D_iw_opx == 35) & D_is_opx_inst;
assign D_op_divu = (D_iw_opx == 36) & D_is_opx_inst;
assign D_op_div = (D_iw_opx == 37) & D_is_opx_inst;
assign D_op_rdctl = (D_iw_opx == 38) & D_is_opx_inst;
assign D_op_mul = (D_iw_opx == 39) & D_is_opx_inst;
assign D_op_cmpgeu = (D_iw_opx == 40) & D_is_opx_inst;
assign D_op_initi = (D_iw_opx == 41) & D_is_opx_inst;
assign D_op_opx_rsv42 = (D_iw_opx == 42) & D_is_opx_inst;
assign D_op_opx_rsv43 = (D_iw_opx == 43) & D_is_opx_inst;
assign D_op_opx_rsv44 = (D_iw_opx == 44) & D_is_opx_inst;
assign D_op_trap = (D_iw_opx == 45) & D_is_opx_inst;
assign D_op_wrctl = (D_iw_opx == 46) & D_is_opx_inst;
assign D_op_opx_rsv47 = (D_iw_opx == 47) & D_is_opx_inst;
assign D_op_cmpltu = (D_iw_opx == 48) & D_is_opx_inst;
assign D_op_add = (D_iw_opx == 49) & D_is_opx_inst;
assign D_op_opx_rsv50 = (D_iw_opx == 50) & D_is_opx_inst;
assign D_op_opx_rsv51 = (D_iw_opx == 51) & D_is_opx_inst;
assign D_op_break = (D_iw_opx == 52) & D_is_opx_inst;
assign D_op_hbreak = (D_iw_opx == 53) & D_is_opx_inst;
assign D_op_sync = (D_iw_opx == 54) & D_is_opx_inst;
assign D_op_opx_rsv55 = (D_iw_opx == 55) & D_is_opx_inst;
assign D_op_opx_rsv56 = (D_iw_opx == 56) & D_is_opx_inst;
assign D_op_sub = (D_iw_opx == 57) & D_is_opx_inst;
assign D_op_srai = (D_iw_opx == 58) & D_is_opx_inst;
assign D_op_sra = (D_iw_opx == 59) & D_is_opx_inst;
assign D_op_opx_rsv60 = (D_iw_opx == 60) & D_is_opx_inst;
assign D_op_intr = (D_iw_opx == 61) & D_is_opx_inst;
assign D_op_crst = (D_iw_opx == 62) & D_is_opx_inst;
assign D_op_opx_rsv63 = (D_iw_opx == 63) & D_is_opx_inst;
assign D_is_opx_inst = D_iw_op == 58;
assign test_has_ended = 1'b0;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//Clearing 'X' data bits
assign av_ld_data_aligned_unfiltered_0_is_x = ^(av_ld_data_aligned_unfiltered[0]) === 1'bx;
assign av_ld_data_aligned_filtered[0] = (av_ld_data_aligned_unfiltered_0_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[0];
assign av_ld_data_aligned_unfiltered_1_is_x = ^(av_ld_data_aligned_unfiltered[1]) === 1'bx;
assign av_ld_data_aligned_filtered[1] = (av_ld_data_aligned_unfiltered_1_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[1];
assign av_ld_data_aligned_unfiltered_2_is_x = ^(av_ld_data_aligned_unfiltered[2]) === 1'bx;
assign av_ld_data_aligned_filtered[2] = (av_ld_data_aligned_unfiltered_2_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[2];
assign av_ld_data_aligned_unfiltered_3_is_x = ^(av_ld_data_aligned_unfiltered[3]) === 1'bx;
assign av_ld_data_aligned_filtered[3] = (av_ld_data_aligned_unfiltered_3_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[3];
assign av_ld_data_aligned_unfiltered_4_is_x = ^(av_ld_data_aligned_unfiltered[4]) === 1'bx;
assign av_ld_data_aligned_filtered[4] = (av_ld_data_aligned_unfiltered_4_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[4];
assign av_ld_data_aligned_unfiltered_5_is_x = ^(av_ld_data_aligned_unfiltered[5]) === 1'bx;
assign av_ld_data_aligned_filtered[5] = (av_ld_data_aligned_unfiltered_5_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[5];
assign av_ld_data_aligned_unfiltered_6_is_x = ^(av_ld_data_aligned_unfiltered[6]) === 1'bx;
assign av_ld_data_aligned_filtered[6] = (av_ld_data_aligned_unfiltered_6_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[6];
assign av_ld_data_aligned_unfiltered_7_is_x = ^(av_ld_data_aligned_unfiltered[7]) === 1'bx;
assign av_ld_data_aligned_filtered[7] = (av_ld_data_aligned_unfiltered_7_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[7];
assign av_ld_data_aligned_unfiltered_8_is_x = ^(av_ld_data_aligned_unfiltered[8]) === 1'bx;
assign av_ld_data_aligned_filtered[8] = (av_ld_data_aligned_unfiltered_8_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[8];
assign av_ld_data_aligned_unfiltered_9_is_x = ^(av_ld_data_aligned_unfiltered[9]) === 1'bx;
assign av_ld_data_aligned_filtered[9] = (av_ld_data_aligned_unfiltered_9_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[9];
assign av_ld_data_aligned_unfiltered_10_is_x = ^(av_ld_data_aligned_unfiltered[10]) === 1'bx;
assign av_ld_data_aligned_filtered[10] = (av_ld_data_aligned_unfiltered_10_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[10];
assign av_ld_data_aligned_unfiltered_11_is_x = ^(av_ld_data_aligned_unfiltered[11]) === 1'bx;
assign av_ld_data_aligned_filtered[11] = (av_ld_data_aligned_unfiltered_11_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[11];
assign av_ld_data_aligned_unfiltered_12_is_x = ^(av_ld_data_aligned_unfiltered[12]) === 1'bx;
assign av_ld_data_aligned_filtered[12] = (av_ld_data_aligned_unfiltered_12_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[12];
assign av_ld_data_aligned_unfiltered_13_is_x = ^(av_ld_data_aligned_unfiltered[13]) === 1'bx;
assign av_ld_data_aligned_filtered[13] = (av_ld_data_aligned_unfiltered_13_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[13];
assign av_ld_data_aligned_unfiltered_14_is_x = ^(av_ld_data_aligned_unfiltered[14]) === 1'bx;
assign av_ld_data_aligned_filtered[14] = (av_ld_data_aligned_unfiltered_14_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[14];
assign av_ld_data_aligned_unfiltered_15_is_x = ^(av_ld_data_aligned_unfiltered[15]) === 1'bx;
assign av_ld_data_aligned_filtered[15] = (av_ld_data_aligned_unfiltered_15_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[15];
assign av_ld_data_aligned_unfiltered_16_is_x = ^(av_ld_data_aligned_unfiltered[16]) === 1'bx;
assign av_ld_data_aligned_filtered[16] = (av_ld_data_aligned_unfiltered_16_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[16];
assign av_ld_data_aligned_unfiltered_17_is_x = ^(av_ld_data_aligned_unfiltered[17]) === 1'bx;
assign av_ld_data_aligned_filtered[17] = (av_ld_data_aligned_unfiltered_17_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[17];
assign av_ld_data_aligned_unfiltered_18_is_x = ^(av_ld_data_aligned_unfiltered[18]) === 1'bx;
assign av_ld_data_aligned_filtered[18] = (av_ld_data_aligned_unfiltered_18_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[18];
assign av_ld_data_aligned_unfiltered_19_is_x = ^(av_ld_data_aligned_unfiltered[19]) === 1'bx;
assign av_ld_data_aligned_filtered[19] = (av_ld_data_aligned_unfiltered_19_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[19];
assign av_ld_data_aligned_unfiltered_20_is_x = ^(av_ld_data_aligned_unfiltered[20]) === 1'bx;
assign av_ld_data_aligned_filtered[20] = (av_ld_data_aligned_unfiltered_20_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[20];
assign av_ld_data_aligned_unfiltered_21_is_x = ^(av_ld_data_aligned_unfiltered[21]) === 1'bx;
assign av_ld_data_aligned_filtered[21] = (av_ld_data_aligned_unfiltered_21_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[21];
assign av_ld_data_aligned_unfiltered_22_is_x = ^(av_ld_data_aligned_unfiltered[22]) === 1'bx;
assign av_ld_data_aligned_filtered[22] = (av_ld_data_aligned_unfiltered_22_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[22];
assign av_ld_data_aligned_unfiltered_23_is_x = ^(av_ld_data_aligned_unfiltered[23]) === 1'bx;
assign av_ld_data_aligned_filtered[23] = (av_ld_data_aligned_unfiltered_23_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[23];
assign av_ld_data_aligned_unfiltered_24_is_x = ^(av_ld_data_aligned_unfiltered[24]) === 1'bx;
assign av_ld_data_aligned_filtered[24] = (av_ld_data_aligned_unfiltered_24_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[24];
assign av_ld_data_aligned_unfiltered_25_is_x = ^(av_ld_data_aligned_unfiltered[25]) === 1'bx;
assign av_ld_data_aligned_filtered[25] = (av_ld_data_aligned_unfiltered_25_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[25];
assign av_ld_data_aligned_unfiltered_26_is_x = ^(av_ld_data_aligned_unfiltered[26]) === 1'bx;
assign av_ld_data_aligned_filtered[26] = (av_ld_data_aligned_unfiltered_26_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[26];
assign av_ld_data_aligned_unfiltered_27_is_x = ^(av_ld_data_aligned_unfiltered[27]) === 1'bx;
assign av_ld_data_aligned_filtered[27] = (av_ld_data_aligned_unfiltered_27_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[27];
assign av_ld_data_aligned_unfiltered_28_is_x = ^(av_ld_data_aligned_unfiltered[28]) === 1'bx;
assign av_ld_data_aligned_filtered[28] = (av_ld_data_aligned_unfiltered_28_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[28];
assign av_ld_data_aligned_unfiltered_29_is_x = ^(av_ld_data_aligned_unfiltered[29]) === 1'bx;
assign av_ld_data_aligned_filtered[29] = (av_ld_data_aligned_unfiltered_29_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[29];
assign av_ld_data_aligned_unfiltered_30_is_x = ^(av_ld_data_aligned_unfiltered[30]) === 1'bx;
assign av_ld_data_aligned_filtered[30] = (av_ld_data_aligned_unfiltered_30_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[30];
assign av_ld_data_aligned_unfiltered_31_is_x = ^(av_ld_data_aligned_unfiltered[31]) === 1'bx;
assign av_ld_data_aligned_filtered[31] = (av_ld_data_aligned_unfiltered_31_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[31];
always @(posedge clk)
begin
if (reset_n)
if (^(F_valid) === 1'bx)
begin
$write("%0d ns: ERROR: system1_nios2_gen2_0_cpu_test_bench/F_valid is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(D_valid) === 1'bx)
begin
$write("%0d ns: ERROR: system1_nios2_gen2_0_cpu_test_bench/D_valid is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(E_valid) === 1'bx)
begin
$write("%0d ns: ERROR: system1_nios2_gen2_0_cpu_test_bench/E_valid is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(W_valid) === 1'bx)
begin
$write("%0d ns: ERROR: system1_nios2_gen2_0_cpu_test_bench/W_valid is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_valid)
if (^(R_wr_dst_reg) === 1'bx)
begin
$write("%0d ns: ERROR: system1_nios2_gen2_0_cpu_test_bench/R_wr_dst_reg is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_valid & R_wr_dst_reg)
if (^(W_wr_data) === 1'bx)
begin
$write("%0d ns: ERROR: system1_nios2_gen2_0_cpu_test_bench/W_wr_data is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_valid & R_wr_dst_reg)
if (^(R_dst_regnum) === 1'bx)
begin
$write("%0d ns: ERROR: system1_nios2_gen2_0_cpu_test_bench/R_dst_regnum is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(d_write) === 1'bx)
begin
$write("%0d ns: ERROR: system1_nios2_gen2_0_cpu_test_bench/d_write is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (d_write)
if (^(d_byteenable) === 1'bx)
begin
$write("%0d ns: ERROR: system1_nios2_gen2_0_cpu_test_bench/d_byteenable is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (d_write | d_read)
if (^(d_address) === 1'bx)
begin
$write("%0d ns: ERROR: system1_nios2_gen2_0_cpu_test_bench/d_address is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(d_read) === 1'bx)
begin
$write("%0d ns: ERROR: system1_nios2_gen2_0_cpu_test_bench/d_read is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(i_read) === 1'bx)
begin
$write("%0d ns: ERROR: system1_nios2_gen2_0_cpu_test_bench/i_read is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (i_read)
if (^(i_address) === 1'bx)
begin
$write("%0d ns: ERROR: system1_nios2_gen2_0_cpu_test_bench/i_address is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (i_read & ~i_waitrequest)
if (^(i_readdata) === 1'bx)
begin
$write("%0d ns: ERROR: system1_nios2_gen2_0_cpu_test_bench/i_readdata is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_valid & R_ctrl_ld)
if (^(av_ld_data_aligned_unfiltered) === 1'bx)
begin
$write("%0d ns: WARNING: system1_nios2_gen2_0_cpu_test_bench/av_ld_data_aligned_unfiltered is 'x'\n", $time);
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_valid & R_wr_dst_reg)
if (^(W_wr_data) === 1'bx)
begin
$write("%0d ns: WARNING: system1_nios2_gen2_0_cpu_test_bench/W_wr_data is 'x'\n", $time);
end
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
//
// assign av_ld_data_aligned_filtered = av_ld_data_aligned_unfiltered;
//
//synthesis read_comments_as_HDL off
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLYGATE4SD3_BLACKBOX_V
`define SKY130_FD_SC_HD__DLYGATE4SD3_BLACKBOX_V
/**
* dlygate4sd3: Delay Buffer 4-stage 0.50um length inner stage gates.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__dlygate4sd3 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLYGATE4SD3_BLACKBOX_V
|
//Legal Notice: (C)2017 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_design_timer_0 (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
irq,
readdata
)
;
output irq;
output [ 15: 0] readdata;
input [ 2: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 15: 0] writedata;
wire clk_en;
wire control_interrupt_enable;
reg control_register;
wire control_wr_strobe;
reg counter_is_running;
wire counter_is_zero;
wire [ 24: 0] counter_load_value;
reg delayed_unxcounter_is_zeroxx0;
wire do_start_counter;
wire do_stop_counter;
reg force_reload;
reg [ 24: 0] internal_counter;
wire irq;
wire period_h_wr_strobe;
wire period_l_wr_strobe;
wire [ 15: 0] read_mux_out;
reg [ 15: 0] readdata;
wire status_wr_strobe;
wire timeout_event;
reg timeout_occurred;
assign clk_en = 1;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
internal_counter <= 25'h1312CFF;
else if (counter_is_running || force_reload)
if (counter_is_zero || force_reload)
internal_counter <= counter_load_value;
else
internal_counter <= internal_counter - 1;
end
assign counter_is_zero = internal_counter == 0;
assign counter_load_value = 25'h1312CFF;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
force_reload <= 0;
else if (clk_en)
force_reload <= period_h_wr_strobe || period_l_wr_strobe;
end
assign do_start_counter = 1;
assign do_stop_counter = 0;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
counter_is_running <= 1'b0;
else if (clk_en)
if (do_start_counter)
counter_is_running <= -1;
else if (do_stop_counter)
counter_is_running <= 0;
end
//delayed_unxcounter_is_zeroxx0, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
delayed_unxcounter_is_zeroxx0 <= 0;
else if (clk_en)
delayed_unxcounter_is_zeroxx0 <= counter_is_zero;
end
assign timeout_event = (counter_is_zero) & ~(delayed_unxcounter_is_zeroxx0);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
timeout_occurred <= 0;
else if (clk_en)
if (status_wr_strobe)
timeout_occurred <= 0;
else if (timeout_event)
timeout_occurred <= -1;
end
assign irq = timeout_occurred && control_interrupt_enable;
//s1, which is an e_avalon_slave
assign read_mux_out = ({16 {(address == 1)}} & control_register) |
({16 {(address == 0)}} & {counter_is_running,
timeout_occurred});
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= read_mux_out;
end
assign period_l_wr_strobe = chipselect && ~write_n && (address == 2);
assign period_h_wr_strobe = chipselect && ~write_n && (address == 3);
assign control_wr_strobe = chipselect && ~write_n && (address == 1);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
control_register <= 0;
else if (control_wr_strobe)
control_register <= writedata[0];
end
assign control_interrupt_enable = control_register;
assign status_wr_strobe = chipselect && ~write_n && (address == 0);
endmodule
|
// megafunction wizard: %LPM_DIVIDE%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: lpm_divide
// ============================================================
// File Name: DIV.v
// Megafunction Name(s):
// lpm_divide
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 6.0 Build 202 06/20/2006 SP 1 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2006 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module DIV (
aclr,
clock,
denom,
numer,
quotient,
remain);
input aclr;
input clock;
input [3:0] denom;
input [9:0] numer;
output [9:0] quotient;
output [3:0] remain;
wire [9:0] sub_wire0;
wire [3:0] sub_wire1;
wire [9:0] quotient = sub_wire0[9:0];
wire [3:0] remain = sub_wire1[3:0];
lpm_divide lpm_divide_component (
.denom (denom),
.aclr (aclr),
.clock (clock),
.numer (numer),
.quotient (sub_wire0),
.remain (sub_wire1),
.clken (1'b1));
defparam
lpm_divide_component.lpm_drepresentation = "UNSIGNED",
lpm_divide_component.lpm_hint = "LPM_REMAINDERPOSITIVE=TRUE",
lpm_divide_component.lpm_nrepresentation = "UNSIGNED",
lpm_divide_component.lpm_pipeline = 1,
lpm_divide_component.lpm_type = "LPM_DIVIDE",
lpm_divide_component.lpm_widthd = 4,
lpm_divide_component.lpm_widthn = 10;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: PRIVATE_LPM_REMAINDERPOSITIVE STRING "TRUE"
// Retrieval info: PRIVATE: PRIVATE_MAXIMIZE_SPEED NUMERIC "-1"
// Retrieval info: PRIVATE: USING_PIPELINE NUMERIC "1"
// Retrieval info: PRIVATE: VERSION_NUMBER NUMERIC "2"
// Retrieval info: CONSTANT: LPM_DREPRESENTATION STRING "UNSIGNED"
// Retrieval info: CONSTANT: LPM_HINT STRING "LPM_REMAINDERPOSITIVE=TRUE"
// Retrieval info: CONSTANT: LPM_NREPRESENTATION STRING "UNSIGNED"
// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "1"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_DIVIDE"
// Retrieval info: CONSTANT: LPM_WIDTHD NUMERIC "4"
// Retrieval info: CONSTANT: LPM_WIDTHN NUMERIC "10"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: denom 0 0 4 0 INPUT NODEFVAL denom[3..0]
// Retrieval info: USED_PORT: numer 0 0 10 0 INPUT NODEFVAL numer[9..0]
// Retrieval info: USED_PORT: quotient 0 0 10 0 OUTPUT NODEFVAL quotient[9..0]
// Retrieval info: USED_PORT: remain 0 0 4 0 OUTPUT NODEFVAL remain[3..0]
// Retrieval info: CONNECT: @numer 0 0 10 0 numer 0 0 10 0
// Retrieval info: CONNECT: @denom 0 0 4 0 denom 0 0 4 0
// Retrieval info: CONNECT: quotient 0 0 10 0 @quotient 0 0 10 0
// Retrieval info: CONNECT: remain 0 0 4 0 @remain 0 0 4 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL DIV.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL DIV.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL DIV.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL DIV.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL DIV_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL DIV_bb.v FALSE
|
//======================================================================
//
// blake2.v
// --------
// Top level wrapper for the blake2 hash function core providing
// a simple memory like interface with 32 bit data access.
//
//
// Author: Joachim Strömbergson
// Copyright (c) 2014, Secworks Sweden AB
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module blake2(
// Clock and reset.
input wire clk,
input wire reset_n,
// Control.
input wire cs,
input wire we,
// Data ports.
input wire [7 : 0] address,
input wire [31 : 0] write_data,
output wire [31 : 0] read_data
);
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
localparam ADDR_NAME0 = 8'h00;
localparam ADDR_NAME1 = 8'h01;
localparam ADDR_VERSION = 8'h02;
localparam ADDR_CTRL = 8'h08;
localparam CTRL_INIT_BIT = 0;
localparam CTRL_NEXT_BIT = 1;
localparam CTRL_FINAL_BIT = 2;
localparam ADDR_STATUS = 8'h09;
localparam STATUS_READY_BIT = 0;
localparam ADDR_BLOCK_W00 = 8'h10;
localparam ADDR_BLOCK_W31 = 8'h2f;
localparam ADDR_DIGEST0 = 8'h80;
localparam ADDR_DIGEST15 = 8'h8f;
localparam CORE_NAME0 = 32'h626c616b; // "blak"
localparam CORE_NAME1 = 32'h65322020; // "e2 "
localparam CORE_VERSION = 32'h302e3130; // "0.10"
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
reg init_reg;
reg init_new;
reg next_reg;
reg next_new;
reg final_reg;
reg final_new;
reg ready_reg;
reg digest_valid_reg;
reg [31 : 0] block_mem [0 : 31];
reg block_mem_we;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
wire [7 : 0] core_key_len;
wire [7 : 0] core_digest_len;
wire core_ready;
wire [1023 : 0] core_block;
wire [511 : 0] core_digest;
wire core_digest_valid;
reg [31 : 0] tmp_read_data;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign core_key_len = 8'h0;
assign core_digest_len = 8'h0;
assign core_block = {block_mem[00], block_mem[01], block_mem[02], block_mem[03],
block_mem[04], block_mem[05], block_mem[06], block_mem[07],
block_mem[08], block_mem[09], block_mem[10], block_mem[11],
block_mem[12], block_mem[13], block_mem[14], block_mem[15],
block_mem[16], block_mem[17], block_mem[18], block_mem[19],
block_mem[20], block_mem[21], block_mem[22], block_mem[23],
block_mem[24], block_mem[25], block_mem[26], block_mem[27],
block_mem[28], block_mem[29], block_mem[30], block_mem[31]};
assign read_data = tmp_read_data;
//----------------------------------------------------------------
// core instantiation.
//----------------------------------------------------------------
blake2_core core (
.clk(clk),
.reset_n(reset_n),
.init(init_reg),
.next_block(next_reg),
.final_block(final_reg),
.key_len(core_key_len),
.digest_len(core_digest_len),
.block(core_block),
.ready(core_ready),
.digest(core_digest),
.digest_valid(core_digest_valid)
);
//----------------------------------------------------------------
// reg_update
//----------------------------------------------------------------
always @ (posedge clk)
begin : reg_update
integer i;
if (!reset_n)
begin
for (i = 0 ; i < 32 ; i = i + 1)
block_mem[i] <= 32'h0;
init_reg <= 1'h0;
next_reg <= 1'h0;
ready_reg <= 1'h0;
digest_valid_reg <= 1'h0;
end
else
begin
init_reg <= init_new;
next_reg <= next_new;
final_reg <= final_new;
ready_reg <= core_ready;
digest_valid_reg <= core_digest_valid;
if (block_mem_we)
block_mem[address[4 : 0]] <= write_data;
end
end // reg_update
//----------------------------------------------------------------
// Address decoder logic.
//----------------------------------------------------------------
always @*
begin : addr_decoder
init_new = 1'h0;
next_new = 1'h0;
final_new = 1'h0;
block_mem_we = 1'h0;
tmp_read_data = 32'h0;
if (cs)
begin
if (we)
begin
if (address == ADDR_CTRL)
begin
init_new = write_data[CTRL_INIT_BIT];
next_new = write_data[CTRL_NEXT_BIT];
final_new = write_data[CTRL_FINAL_BIT];
end
if ((address >= ADDR_BLOCK_W00) && (address <= ADDR_BLOCK_W31))
begin
block_mem_we = 1;
end
end // if (we)
else
begin
if ((address >= ADDR_DIGEST0) && (address <= ADDR_DIGEST15))
tmp_read_data = core_digest[(15 - (address - ADDR_DIGEST0)) * 32 +: 32];
case (address)
ADDR_NAME0:
tmp_read_data = CORE_NAME0;
ADDR_NAME1:
tmp_read_data = CORE_NAME1;
ADDR_VERSION:
tmp_read_data = CORE_VERSION;
ADDR_CTRL:
tmp_read_data = {29'h0, final_reg, next_reg, init_reg};
ADDR_STATUS:
tmp_read_data = {30'h0, digest_valid_reg, ready_reg};
default:
begin
end
endcase // case (address)
end
end
end // addr_decoder
endmodule // blake2
//======================================================================
// EOF blake2.v
//======================================================================
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__AND2B_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__AND2B_PP_BLACKBOX_V
/**
* and2b: 2-input AND, first input inverted.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__and2b (
X ,
A_N ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__AND2B_PP_BLACKBOX_V
|
`timescale 1 ns / 100 ps
module uart_tx_tb ();
reg clock;
reg [7:0] read_data;
reg read_clock_enable;
reg reset; /* active low */
wire ready; /* ready to read new data */
wire tx;
wire uart_clock;
uart_tx #(.CLOCK_FREQ(2_400), .BAUD_RATE(1_200))
UART (
.reset(reset),
.clock(clock),
.read_data(read_data),
.read_clock_enable(read_clock_enable),
.tx(tx),
.ready(ready),
.uart_clock(uart_clock));
always
#2 clock = ~clock;
initial begin
#5000 $finish;
end
initial begin
$dumpfile ("uart_tx_tb.vcd");
$dumpvars (0, uart_tx_tb);
clock = 0;
reset = 0;
read_data = 8'hb7;
read_clock_enable = 1;
#10
if (ready == 'b1) begin
$display("ready in reset is high. Expected: low");
$stop;
end
#2
read_clock_enable = 0;
#20 reset = 1;
#2;
#2;
#2;
reset = 1;
#500;
if (ready == 'b0) begin
$display("ready after reset is low. Expected: high");
$stop;
end
#2;
read_clock_enable = 1;
@(negedge ready);
read_clock_enable = 0;
#2000;
$finish;
end
endmodule
|
//*******************************************************************************************
//Author: Yejoong Kim, Ye-sheng Kuo
//Last Modified: Aug 23 2017
//Description: (Testbench) MBus Node Control for Master Layer
//Update History: Apr 08 2013 - Added glitch reset (Ye-sheng Kuo)
// May 25 2015 - Added double latch for DIN (Ye-sheng Kuo, Yejoong Kim)
// May 21 2016 - Updated for MBus r03 (Yejoong Kim)
// Added "BUS_SWITCH_ROLE: DOUT=1" in "case (bus_state_neg)"
// Changed module name:
// lname_mbus_master_ctrl -> lname_mbus_master_node_ctrl
// Added MBus Watchdog Counter
// Dec 16 2016 - Updated for MBus r04 (Yejoong Kim)
// Added MBus Flag (MSG_INTERRUPTED)
// May 24 2017 - Updated for MBus r04p1 (Yejoong Kim)
// Added FORCE_IDLE_WHEN_DONE to fix DIN sync issue between
// master layer and member layer at the end of message
// that requires a reply.
// Changed some variable names to be consistent with lname_mbus_master_node_ctrl.v
// THRESHOLD -> NUM_BITS_THRESHOLD
// threshold_cnt -> num_bits_threshold_cnt
// next_threshold_cnt -> next_num_bits_threshold_cnt
// Aug 23 2017 - Checked for mbus_testbench
//*******************************************************************************************
`include "include/mbus_def_testbench.v"
module mbus_master_node_ctrl_testbench (
//Input
input CLK_EXT,
input RESETn,
input CIN,
input DIN,
input [`MBUSTB_BITS_WD_WIDTH-1:0] NUM_BITS_THRESHOLD,
//Output
output COUT,
output reg DOUT,
// FSM Configuration
input FORCE_IDLE_WHEN_DONE
);
`include "include/mbus_func_testbench.v"
parameter BUS_IDLE = 0;
parameter BUS_WAIT_START = 3;
parameter BUS_START = 4;
parameter BUS_ARBITRATE = 1;
parameter BUS_PRIO = 2;
parameter BUS_ACTIVE = 5;
parameter BUS_INTERRUPT = 7;
parameter BUS_SWITCH_ROLE = 6;
parameter BUS_CONTROL0 = 8;
parameter BUS_CONTROL1 = 9;
parameter BUS_BACK_TO_IDLE = 10;
parameter NUM_OF_BUS_STATE = 11;
parameter START_CYCLES = 10;
parameter GUARD_BAND_NUM_CYCLES = 20;
parameter BUS_INTERRUPT_COUNTER = 6;
reg [log2(START_CYCLES-1)-1:0] start_cycle_cnt, next_start_cycle_cnt;
reg [log2(NUM_OF_BUS_STATE-1)-1:0] bus_state, next_bus_state, bus_state_neg;
reg [log2(BUS_INTERRUPT_COUNTER-1)-1:0] bus_interrupt_cnt, next_bus_interrupt_cnt;
reg clk_en, next_clk_en;
reg clkin_sampled;
reg [2:0] din_sampled_neg, din_sampled_pos;
reg [`MBUSTB_BITS_WD_WIDTH-1:0] num_bits_threshold_cnt, next_num_bits_threshold_cnt;
reg din_dly_1, din_dly_2;
// DIN double-latch
always @(posedge CLK_EXT or negedge RESETn) begin
if (~RESETn) begin
din_dly_1 <= `MBUSTB_SD 1'b1;
din_dly_2 <= `MBUSTB_SD 1'b1;
end
else if (FORCE_IDLE_WHEN_DONE) begin
if ((bus_state == BUS_IDLE) | (bus_state == BUS_WAIT_START)) begin
din_dly_1 <= `MBUSTB_SD DIN;
din_dly_2 <= `MBUSTB_SD din_dly_1;
end
else begin
din_dly_1 <= `MBUSTB_SD 1'b1;
din_dly_2 <= `MBUSTB_SD 1'b1;
end
end
else begin
din_dly_1 <= `MBUSTB_SD DIN;
din_dly_2 <= `MBUSTB_SD din_dly_1;
end
end
wire [1:0] CONTROL_BITS = `MBUSTB_CONTROL_SEQ; // EOM?, ~ACK?
always @ (posedge CLK_EXT or negedge RESETn) begin
if (~RESETn) begin
bus_state <= `MBUSTB_SD BUS_IDLE;
start_cycle_cnt <= `MBUSTB_SD START_CYCLES - 1'b1;
clk_en <= `MBUSTB_SD 0;
bus_interrupt_cnt <= `MBUSTB_SD BUS_INTERRUPT_COUNTER - 1'b1;
num_bits_threshold_cnt <= `MBUSTB_SD 0;
end
else begin
bus_state <= `MBUSTB_SD next_bus_state;
start_cycle_cnt <= `MBUSTB_SD next_start_cycle_cnt;
clk_en <= `MBUSTB_SD next_clk_en;
bus_interrupt_cnt <= `MBUSTB_SD next_bus_interrupt_cnt;
num_bits_threshold_cnt <= `MBUSTB_SD next_num_bits_threshold_cnt;
end
end
always @* begin
next_bus_state = bus_state;
next_start_cycle_cnt = start_cycle_cnt;
next_clk_en = clk_en;
next_bus_interrupt_cnt = bus_interrupt_cnt;
next_num_bits_threshold_cnt = num_bits_threshold_cnt;
case (bus_state)
BUS_IDLE: begin
if (~din_dly_2) next_bus_state = BUS_WAIT_START;
next_start_cycle_cnt = START_CYCLES - 1'b1;
end
BUS_WAIT_START: begin
next_num_bits_threshold_cnt = 0;
if (start_cycle_cnt) next_start_cycle_cnt = start_cycle_cnt - 1'b1;
else begin
if (~din_dly_2) begin
next_clk_en = 1;
next_bus_state = BUS_START;
end
else next_bus_state = BUS_IDLE;
end
end
BUS_START: next_bus_state = BUS_ARBITRATE;
BUS_ARBITRATE: begin
next_bus_state = BUS_PRIO;
if (DIN) next_num_bits_threshold_cnt = NUM_BITS_THRESHOLD; // Glitch, reset bus immediately
end
BUS_PRIO: next_bus_state = BUS_ACTIVE;
BUS_ACTIVE: begin
if ((num_bits_threshold_cnt<NUM_BITS_THRESHOLD)&&(~clkin_sampled))
next_num_bits_threshold_cnt = num_bits_threshold_cnt + 1'b1;
else begin
next_clk_en = 0;
next_bus_state = BUS_INTERRUPT;
end
next_bus_interrupt_cnt = BUS_INTERRUPT_COUNTER - 1'b1;
end
BUS_INTERRUPT: begin
if (bus_interrupt_cnt) next_bus_interrupt_cnt = bus_interrupt_cnt - 1'b1;
else begin
if ({din_sampled_neg, din_sampled_pos}==6'b111_000) begin
next_bus_state = BUS_SWITCH_ROLE;
next_clk_en = 1;
end
end
end
BUS_SWITCH_ROLE: next_bus_state = BUS_CONTROL0;
BUS_CONTROL0: next_bus_state = BUS_CONTROL1;
BUS_CONTROL1: next_bus_state = BUS_BACK_TO_IDLE;
BUS_BACK_TO_IDLE: begin
if (FORCE_IDLE_WHEN_DONE) begin
next_bus_state = BUS_IDLE;
next_clk_en = 0;
end
else begin
if (~DIN) begin
next_bus_state = BUS_WAIT_START;
next_start_cycle_cnt = 1;
end
else begin
next_bus_state = BUS_IDLE;
end
next_clk_en = 0;
end
end
endcase
end
always @ (negedge CLK_EXT or negedge RESETn) begin
if (~RESETn) begin
din_sampled_neg <= `MBUSTB_SD 0;
bus_state_neg <= `MBUSTB_SD BUS_IDLE;
end
else begin
if (bus_state==BUS_INTERRUPT) din_sampled_neg <= `MBUSTB_SD {din_sampled_neg[1:0], DIN};
bus_state_neg <= `MBUSTB_SD bus_state;
end
end
always @ (posedge CLK_EXT or negedge RESETn) begin
if (~RESETn) begin
din_sampled_pos <= `MBUSTB_SD 0;
clkin_sampled <= `MBUSTB_SD 0;
end
else begin
if (bus_state==BUS_INTERRUPT) din_sampled_pos <= `MBUSTB_SD {din_sampled_pos[1:0], DIN};
clkin_sampled <= `MBUSTB_SD CIN;
end
end
assign COUT = (clk_en)? CLK_EXT : 1'b1;
always @* begin
DOUT = DIN;
case (bus_state_neg)
BUS_IDLE: DOUT = 1;
BUS_WAIT_START: DOUT = 1;
BUS_START: DOUT = 1;
BUS_INTERRUPT: DOUT = CLK_EXT;
BUS_SWITCH_ROLE: DOUT = 1;
BUS_CONTROL0: if (num_bits_threshold_cnt==NUM_BITS_THRESHOLD) DOUT = (~CONTROL_BITS[1]);
BUS_BACK_TO_IDLE: DOUT = 1;
endcase
end
endmodule // lname_mbus_master_node_ctrl
|
/*
Distributed under the MIT license.
Copyright (c) 2015 Dave McCoy ([email protected])
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/*
* Author: David McCoy ([email protected])
* Description:
* Manages buffers for ingress transactions (Data sent from the host to FPGA)
* When the FPGA requests data from the host computer it makes a:
* Memory Read Request
* The request contains a tag and the count of dwords to receive (Among other
* things) The state machine that requests the data lets this cotnroller
* manage the actual tag and memory relationship. This controller follows the
* tag and through the following steps:
* * When the host says it has data available
* * The PCIE Control request to the host computer
* * The PCIE Ingress that receives data from the host and stores it into a
* local buffer
* * Buffer manager telling this controller that a FIFO has pulle the data
*
* Changes:
* 4/30/2016: Initial Commit
*/
//2048 / 4
//`define DWORD_COUNT 10'h0200
module ingress_buffer_manager #(
parameter BUFFER_WIDTH = 12, //4096
parameter MAX_REQ_WIDTH = 9
)(
input clk,
input rst,
//Host
//input i_hst_buf_size, //Size of buffer on host machine (Probably not needed now but in future version it will be important)
input i_hst_buf_rdy_stb, //Strobe in the status of the buffer
input [1:0] i_hst_buf_rdy, //Reads in status of the buffer
output reg o_hst_buf_fin_stb, //Strobe to tell the PCIE Control FIFO we're done with buffer(s)
output reg [1:0] o_hst_buf_fin, //Signals go high indicating that a buffer is finished
//PCIE Control
input i_ctr_en, //PCIE Controller enables this state machine when starting a write
input i_ctr_mem_rd_req_stb, //Strobe that commits a portion of the buffer
input i_ctr_dat_fin, //Asserted when the controller will not request more data
output reg o_ctr_tag_rdy, //Tell the controller that the tag is ready
output [7:0] o_ctr_tag, //Provide a tag for the PCIE Control to use
output [9:0] o_ctr_dword_size, //Provide the size of the packet
output [11:0] o_ctr_start_addr, //Provide the starting address (on host computer for this read)
output reg o_ctr_buf_sel, //Tell the PCIE controller what buffer we plan to use
output o_ctr_idle, //Tell the PCIE Control there are no outstanding transactions
//PCIE Ingress
input i_ing_cplt_stb, //Detect
input [9:0] i_ing_cplt_pkt_cnt, //Number of dwords in this read
input [7:0] i_ing_cplt_tag, //Tag that refereneces
input [6:0] i_ing_cplt_lwr_addr, //Lower address when complete is broken up into multple packets
//Buffer Builder
output [12:0] o_bld_mem_addr, //Address of where to start writing data
output reg [1:0] o_bld_buf_en, //Tell Buffer Builder the FIFO can read the block data
input i_bld_buf_fin, //Buffer Builder reported FIFO has read everything
output [15:0] o_dbg_tag_en,
output [15:0] o_dbg_tag_ingress_fin,
output reg o_dbg_reenable_stb, //If this is strobed, it indicates that the enable was set high a second time (shouldn't happend)
output reg o_dbg_reenable_nzero_stb //If the host responded a bit then this will be greater than zero
);
//local parameters
localparam IDLE = 4'h0;
localparam WAIT_FOR_COMPLETION = 4'h1;
localparam FINISHED = 4'h2;
localparam WAIT_FOR_HOST = 4'h1;
localparam CTRL_TAGS_INTERFACE = 4'h2;
localparam WAIT_FOR_FINISH = 4'h3;
localparam BB_SEND_DATA_0 = 4'h1;
localparam BB_SEND_DATA_1 = 4'h2;
localparam MAX_REQ_SIZE = 2 ** MAX_REQ_WIDTH;
localparam BUFFER_SIZE = 2 ** BUFFER_WIDTH;
localparam BIT_FIELD_WIDTH = 2 ** (BUFFER_WIDTH - MAX_REQ_WIDTH);
localparam DWORD_COUNT = MAX_REQ_SIZE / 4;
localparam NUM_TAGS = (BUFFER_SIZE / MAX_REQ_SIZE) * 2;
localparam BUF0_POS = 0;
localparam BUF1_POS = (NUM_TAGS / 2);
localparam TAG0_BITFIELD = (2 ** BUF1_POS) - 1;
localparam TAG1_BITFIELD = TAG0_BITFIELD << (BUF1_POS);
//registes/wires
reg [3:0] gen_state;
reg [3:0] rcv_state;
reg r_delay_stb;
reg [1:0] r_buf_status;
reg [1:0] r_hst_buf_rdy_cnt;
reg [3:0] r_tag_rdy_pos;
reg [NUM_TAGS - 1:0] r_tag_sm_en;
wire [1:0] w_tag_sm_idle;
reg [NUM_TAGS - 1:0] r_tag_sm_fin;
wire [7:0] w_tag_map_min[1:0];
wire [7:0] w_tag_map_max[1:0];
wire [NUM_TAGS - 1:0] w_tag_bitfield[1:0];
wire [1:0] w_tag_ingress_done;
wire [15:0] w_tmp_bf = BIT_FIELD_WIDTH;
wire [15:0] w_tmp_ttl_width = MAX_REQ_SIZE;
wire [15:0] w_tmp_buf_width = BUFFER_SIZE;
wire [7:0] w_max_tags = NUM_TAGS;
wire [7:0] w_tag_map0;
wire [7:0] w_tag_map1;
wire [NUM_TAGS - 1:0] w_tag_bitfield0;
wire [NUM_TAGS - 1:0] w_tag_bitfield1;
//Tag State
reg [3:0] tag_state[0:NUM_TAGS];
reg [11:0] r_byte_cnt[0:NUM_TAGS];
wire [11:0] byte_cnt0;
wire [11:0] byte_cnt1;
wire [11:0] byte_cnt2;
wire [11:0] byte_cnt3;
wire [11:0] byte_cnt4;
wire [11:0] byte_cnt5;
wire [11:0] byte_cnt6;
wire [11:0] byte_cnt7;
wire [11:0] byte_cnt8;
wire [11:0] byte_cnt9;
wire [11:0] byte_cnt10;
wire [11:0] byte_cnt11;
wire [11:0] byte_cnt12;
wire [11:0] byte_cnt13;
wire [11:0] byte_cnt14;
wire [11:0] byte_cnt15;
// DEBUG SIGNALS
wire [3:0] tag_state0;
wire [3:0] tag_state1;
wire [3:0] tag_state2;
wire [3:0] tag_state3;
wire [3:0] tag_state4;
wire [3:0] tag_state5;
wire [3:0] tag_state6;
wire [3:0] tag_state7;
wire [3:0] tag_state8;
wire [3:0] tag_state9;
wire [3:0] tag_state10;
wire [3:0] tag_state11;
wire [3:0] tag_state12;
wire [3:0] tag_state13;
wire [3:0] tag_state14;
wire [3:0] tag_state15;
// END DEBUG SIGNALS
//submodules
//asynchronous logic
assign o_ctr_tag = r_tag_rdy_pos;
assign w_tag_map0 = w_tag_map_min[0];
assign w_tag_map1 = w_tag_map_min[1];
assign w_tag_map_min[0] = BUF0_POS;
assign w_tag_map_min[1] = BUF1_POS;
assign w_tag_map_max[0] = BUF0_POS + ((NUM_TAGS / 2) - 1);
assign w_tag_map_max[1] = BUF1_POS + ((NUM_TAGS / 2) - 1);
assign o_ctr_start_addr = o_ctr_tag << MAX_REQ_WIDTH;
assign w_tag_bitfield[0] = TAG0_BITFIELD;
assign w_tag_bitfield[1] = TAG1_BITFIELD;
assign w_tag_bitfield0 = w_tag_bitfield[0];
assign w_tag_bitfield1 = w_tag_bitfield[1];
assign w_tag_sm_idle[0] = ((r_tag_sm_en & w_tag_bitfield[0]) == 0);
assign w_tag_sm_idle[1] = ((r_tag_sm_en & w_tag_bitfield[1]) == 0);
assign w_tag_ingress_done[0] = i_ctr_dat_fin ? ((r_tag_sm_fin & w_tag_bitfield[0]) == (r_tag_sm_en & w_tag_bitfield[0]) &&
((r_tag_sm_en & w_tag_bitfield[0]) > 0)):
((r_tag_sm_fin & w_tag_bitfield[0]) == (r_tag_sm_en & w_tag_bitfield[0]) &&
((r_tag_sm_en & w_tag_bitfield[0]) == w_tag_bitfield[0]));
assign w_tag_ingress_done[1] = i_ctr_dat_fin ? ((r_tag_sm_fin & w_tag_bitfield[1]) == (r_tag_sm_en & w_tag_bitfield[1]) &&
((r_tag_sm_en & w_tag_bitfield[1]) > 0)):
((r_tag_sm_fin & w_tag_bitfield[1]) == (r_tag_sm_en & w_tag_bitfield[1]) &&
((r_tag_sm_en & w_tag_bitfield[1]) == w_tag_bitfield[1]));
//Set the output block memory start address
assign o_bld_mem_addr = (i_ing_cplt_tag << (MAX_REQ_WIDTH - 2)) + r_byte_cnt[i_ing_cplt_tag][11:2];
assign o_ctr_dword_size = DWORD_COUNT;
assign o_ctr_idle = (r_tag_sm_en == 0);
// DEBUG SIGNALS
assign tag_state0 = tag_state[0];
assign tag_state1 = tag_state[1];
assign tag_state2 = tag_state[2];
assign tag_state3 = tag_state[3];
assign tag_state4 = tag_state[4];
assign tag_state5 = tag_state[5];
assign tag_state6 = tag_state[6];
assign tag_state7 = tag_state[7];
assign tag_state8 = tag_state[8];
assign tag_state9 = tag_state[9];
assign tag_state10 = tag_state[10];
assign tag_state11 = tag_state[11];
assign tag_state12 = tag_state[12];
assign tag_state13 = tag_state[13];
assign tag_state14 = tag_state[14];
assign tag_state15 = tag_state[15];
assign byte_cnt0 = r_byte_cnt[0];
assign byte_cnt1 = r_byte_cnt[1];
assign byte_cnt2 = r_byte_cnt[2];
assign byte_cnt3 = r_byte_cnt[3];
assign byte_cnt4 = r_byte_cnt[4];
assign byte_cnt5 = r_byte_cnt[5];
assign byte_cnt6 = r_byte_cnt[6];
assign byte_cnt7 = r_byte_cnt[7];
assign byte_cnt8 = r_byte_cnt[8];
assign byte_cnt9 = r_byte_cnt[9];
assign byte_cnt10 = r_byte_cnt[10];
assign byte_cnt11 = r_byte_cnt[11];
assign byte_cnt12 = r_byte_cnt[12];
assign byte_cnt13 = r_byte_cnt[13];
assign byte_cnt14 = r_byte_cnt[14];
assign byte_cnt15 = r_byte_cnt[15];
assign o_dbg_tag_en = r_tag_sm_en;
assign o_dbg_tag_ingress_fin = r_tag_sm_fin;
// END DEBUG SIGNALS
//synchronous logic
//Four stage management
//Host: Sends buffer ready status
// Problems: I need to distinguish between the first and second packet
//PCIE Control: Activates tag
//PCIE Ingress: Detect Incomming Tag associated completion header provides address for writing data to buffer
//Buffer Builder: When the tags have written all the data, the PPFIFO needs to read a block, then block is done
//Buffer State Machine
integer x;
always @ (posedge clk) begin
//De-assert Strobes
o_hst_buf_fin_stb <= 0;
o_bld_buf_en <= 0;
o_hst_buf_fin <= 2'b00;
r_delay_stb <= 0;
o_dbg_reenable_stb <= 0;
o_dbg_reenable_nzero_stb <= 0;
if (rst || !i_ctr_en) begin
r_tag_rdy_pos <= 0;
r_tag_sm_en <= 0;
o_ctr_buf_sel <= 0;
o_ctr_tag_rdy <= 0;
r_hst_buf_rdy_cnt <= 0;
r_buf_status <= 0;
gen_state <= IDLE;
rcv_state <= IDLE;
end
else begin
case (gen_state)
IDLE: begin
o_hst_buf_fin_stb <= 1;
gen_state <= WAIT_FOR_HOST;
end
WAIT_FOR_HOST: begin
//Wait for the host to update buffers
if (!i_hst_buf_rdy_stb && !r_delay_stb && (r_hst_buf_rdy_cnt > 0)) begin
//Uncomment the line below and comment out the line above for normal operation, otherwise in debug mode (auto buffer swithc)
//Non Debug (These should be uncommented in the future)
o_ctr_buf_sel <= r_buf_status[0];
r_buf_status[0] <= r_buf_status[1];
r_tag_rdy_pos <= w_tag_map_min[r_buf_status[0]];
//De-assert the enables
r_hst_buf_rdy_cnt <= r_hst_buf_rdy_cnt - 1;
gen_state <= CTRL_TAGS_INTERFACE;
end
end
CTRL_TAGS_INTERFACE: begin
//Tell the controller that we are ready
o_ctr_tag_rdy <= 1;
if (i_ctr_mem_rd_req_stb) begin
//Controller has committed to a tag
//Enable Tag State Machine
if (r_tag_sm_en[r_tag_rdy_pos]) begin
o_dbg_reenable_stb <= 1;
if (r_byte_cnt[r_tag_rdy_pos] > 0) begin
o_dbg_reenable_nzero_stb <= 1;
end
end
r_tag_sm_en[r_tag_rdy_pos] <= 1;
if (r_tag_rdy_pos < w_tag_map_max[o_ctr_buf_sel]) begin
r_tag_rdy_pos <= r_tag_rdy_pos + 1;
end
else begin
gen_state <= WAIT_FOR_FINISH;
//gen_state <= WAIT_FOR_HOST;
o_ctr_tag_rdy <= 0;
end
end
end
WAIT_FOR_FINISH: begin
if (o_hst_buf_fin_stb) begin
gen_state <= WAIT_FOR_HOST;
end
end
default: begin
gen_state <= IDLE;
end
endcase
/* PCIE Ingress and Buffer Builder Controller */
case (rcv_state)
IDLE: begin
if (w_tag_ingress_done[0]) begin
//All tags for buffer 0 reported in done
rcv_state <= BB_SEND_DATA_0;
end
else if (w_tag_ingress_done[1]) begin
//All tags for buffer 1 reported in done
rcv_state <= BB_SEND_DATA_1;
end
end
BB_SEND_DATA_0: begin
//Send out all data from buffer 0, wait for the buffer builder to finish
o_bld_buf_en[0] <= 1;
if (i_bld_buf_fin) begin
o_hst_buf_fin[0] <= 1;
o_hst_buf_fin_stb <= 1;
r_tag_sm_en <= r_tag_sm_en & ~TAG0_BITFIELD;
rcv_state <= IDLE;
end
end
BB_SEND_DATA_1: begin
//Send out all data from buffer 1, wait for the buffer builder to finish
o_bld_buf_en[1] <= 1;
if (i_bld_buf_fin) begin
o_hst_buf_fin[1] <= 1;
o_hst_buf_fin_stb <= 1;
r_tag_sm_en <= r_tag_sm_en & ~TAG1_BITFIELD;
rcv_state <= IDLE;
end
end
default: begin
rcv_state <= IDLE;
end
endcase
//Change Incomming Strobes to enables
if (i_hst_buf_rdy_stb && (i_hst_buf_rdy > 0)) begin
r_buf_status[r_hst_buf_rdy_cnt] <= i_hst_buf_rdy[1];
r_hst_buf_rdy_cnt <= r_hst_buf_rdy_cnt + 1;
r_delay_stb <= 1;
end
end
end
//Tag State Machine
genvar i;
generate
for (i = 0; i < NUM_TAGS; i = i + 1) begin : tag_sm
always @ (posedge clk) begin
r_tag_sm_fin[i] <= 0;
if (rst || !i_ctr_en) begin
tag_state[i] <= IDLE;
r_tag_sm_fin[i] <= 0;
r_byte_cnt[i] <= 0;
end
else begin
case (tag_state[i])
IDLE: begin
r_byte_cnt[i] <= 0;
if (r_tag_sm_en[i]) begin
tag_state[i] <= WAIT_FOR_COMPLETION;
end
end
WAIT_FOR_COMPLETION: begin
if (i_ing_cplt_stb && (i_ing_cplt_tag == i)) begin
r_byte_cnt[i] <= r_byte_cnt[i] + {i_ing_cplt_pkt_cnt, 2'b00};
end
if (r_byte_cnt[i] >= MAX_REQ_SIZE) begin
tag_state[i] <= FINISHED;
end
end
FINISHED: begin
r_tag_sm_fin[i] <= 1;
if (!r_tag_sm_en[i]) begin
tag_state[i] <= IDLE;
end
end
endcase
end
end
end
endgenerate
endmodule
|
`include "define.v"
module memory( clk, rst, wen, addr, data_in, fileid, data_out);
parameter ASIZE=16;
parameter DSIZE=16;
input clk;
input rst;
input wen;
input [ASIZE-1:0] addr; // address input
input [DSIZE-1:0] data_in; // data input
input [3:0] fileid;
output [DSIZE-1:0] data_out; // data output
reg [DSIZE-1:0] memory [0:2**ASIZE-1];
reg [8*`MAX_LINE_LENGTH:0] line; /* Line of text read from file */
integer fin, i, c, r;
reg [ASIZE-1:0] t_addr;
reg [DSIZE-1:0] t_data;
reg [ASIZE-1:0] addr_r;
assign data_out = memory[addr_r];
always @(posedge clk)
begin
if(rst)
begin
addr_r <=0;
case(fileid)
0: fin = $fopen("imem_test0.txt","r");
1: fin = $fopen("imem_test1.txt","r");
2: fin = $fopen("imem_test2.txt","r");
3: fin = $fopen("imem_test3.txt","r");
4: fin = $fopen("imem_test4.txt","r");
5: fin = $fopen("imem_test5.txt","r");
6: fin = $fopen("imem_test6.txt","r");
7: fin = $fopen("imem_test7.txt","r");
8: fin = $fopen("dmem_test0.txt","r");
9: fin = $fopen("dmem_test1.txt","r");
10: fin = $fopen("dmem_test2.txt","r");
11: fin = $fopen("dmem_test3.txt","r");
12: fin = $fopen("dmem_test4.txt","r");
13: fin = $fopen("dmem_test5.txt","r");
14: fin = $fopen("dmem_test6.txt","r");
15: fin = $fopen("dmem_test7.txt","r");
endcase
$write("Opening Fileid %d\n", fileid);
//First, initialize everything to 0
for (i = 0; i < 2 ** ASIZE; i = i + 1)
begin
memory[i] = 16'h0000;
end
//Now read in the input file
while(!$feof(fin)) begin
c = $fgetc(fin);
// check for comment
if (c == "/" | c == "#" | c == "%")
r = $fgets(line, fin);
else
begin
// Push the character back to the file then read the next time
r = $ungetc(c, fin);
r = $fscanf(fin, "%h %h",t_addr, t_data);
memory[t_addr]=t_data;
end
end
$fclose(fin);
end
else
begin
addr_r <= addr;
if (!wen)
begin // active-low write enable
memory[addr] <= data_in;
end
end
end
endmodule
|
module execute( clk, reset, ALUOut, ALUOp,fromPlusOneMem, fromRFOut1, fromRFOut2, RASelectInput, CCRWrite, CCR_Write_from_wb,CCRWriteValue,
CCRWriteValue_from_wb, fromSImm6, ExMux1Select, ExMux2Select,
RAOut, CCR,IR,SignalA,SignalB,SignalC,SignalG,SignalI,SignalJ,SignalK,SignalX,SignalY,
mem_wb_op,mem_wb_regA,mem_wb_regB,mem_wb_regC,ex_mem_op,ex_mem_regA,ex_mem_regB,ex_mem_regC,
regread_ex_op,regread_ex_regA,regread_ex_regB,regread_ex_regC,mem_wb_CCR_write,ex_mem_CCR_write,r7,rf);
parameter ADD = 6'b000000;
parameter NDU = 6'b001000;
parameter ADC = 6'b000010;
parameter ADZ = 6'b000001;
parameter ADI = 4'b0001;
parameter NDC = 6'b001010;
parameter NDZ = 6'b001001;
output [15:0] RAOut, ALUOut;
output [ 1:0] CCR;
output r7,rf;
output reg CCRWrite;//send to pipeline register
output [ 1:0] CCRWriteValue;//send to pipeline register
input CCR_Write_from_wb;
input [15:0] fromPlusOneMem, fromRFOut1, fromRFOut2, fromSImm6;
input [15:0] SignalA,SignalB,SignalC,SignalG,SignalI,SignalJ,SignalK;
input [1:0] SignalX,SignalY;
input [1:0] CCRWriteValue_from_wb;
input clk, reset, RASelectInput, ALUOp, ExMux1Select, ExMux2Select;
input [15:0]IR;
//inputs required for forwarding
input [2:0] mem_wb_regA,mem_wb_regB,mem_wb_regC,ex_mem_regA,ex_mem_regB,ex_mem_regC,regread_ex_regA,regread_ex_regB,regread_ex_regC;
input [5:0]mem_wb_op,ex_mem_op,regread_ex_op;
input ex_mem_CCR_write;
//
wire [15:0] ALUIn1, ALUIn2, ExMux1Out, ExMux2Out;
wire[1:0] CCRMux_out;//CCRMux_out[1] = zero, CCRMux_out[0] = carry
wire[1:0] CCR_muxSelect;
wire [ 2:0] ExMux3Select, ExMux4Select; // These come from the forwarding unit. Do this.
wire ALUZero, ALUCarry;
wire [5:0]ALU_op;//to check whether we must write to CCR or not
assign ALU_op = {IR[15:12],IR[1:0]};
mux2x4 CCR_mux(.data0(CCR),.data1(SignalX),.data2(SignalY),.data3(2'b0),.selectInput(CCR_muxSelect),.out(CCRMux_out));
mux16x2 RAMux(.data0(fromPlusOneMem), .data1(fromRFOut1), .selectInput(RASelectInput), .out(RAOut));
mux16x2 ExMux1(.data0(fromRFOut1), .data1(fromSImm6), .selectInput(ExMux1Select), .out(ExMux1Out));//for input 1 of ALU
mux16x2 ExMux2(.data0(fromRFOut2), .data1(fromSImm6), .selectInput(ExMux2Select), .out(ExMux2Out));//for input 2 of ALU
mux16x8 ExMux3(.data0(ExMux1Out), .data1(SignalA), .data2(SignalB), .data3(SignalC), .data4(SignalG), .data5(SignalI), .data6(SignalJ), .data7(SignalK), .selectInput(ExMux3Select), .out(ALUIn1));
mux16x8 ExMux4(.data0(ExMux2Out), .data1(SignalA), .data2(SignalB), .data3(SignalC), .data4(SignalG), .data5(SignalI), .data6(SignalJ), .data7(SignalK), .selectInput(ExMux4Select), .out(ALUIn2));
register2 CCRReg(.clk(clk), .out(CCR), .in(CCRWriteValue_from_wb), .write(CCR_Write_from_wb), .reset(reset));
alu me(.in1(ALUIn1), .in2(ALUIn2), .op(ALUOp), .out(ALUOut), .zero(ALUZero), .carry(ALUCarry));
forward_ex_stage f_ex(.mem_wb_op(mem_wb_op),.mem_wb_regA(mem_wb_regA),.mem_wb_regB(mem_wb_regB),.mem_wb_regC(mem_wb_regC),.ex_mem_op(ex_mem_op),.ex_mem_regA(ex_mem_regA),.ex_mem_regB(ex_mem_regB),.ex_mem_regC(ex_mem_regC),.regread_ex_op(regread_ex_op),.regread_ex_regA(regread_ex_regA),.regread_ex_regB(regread_ex_regB),
.regread_ex_regC(regread_ex_regC),.F1(ExMux3Select),.F2(ExMux4Select),.FCCR(CCR_muxSelect),.mem_wb_CCR_write(CCR_Write_from_wb),.ex_mem_CCR_write(ex_mem_CCR_write).rf(rf),.r7(r7));
assign CCRWriteValue = {ALUZero, ALUCarry};
always @(*)
begin
if(ALU_op==ADD||ALU_op==ADI||ALU_op==NDU)
CCRWrite=1'b0;
else if((ALU_op==ADC||ALU_op==NDC)&& (CCRMux_out[0]==1'b1))//previous carry set or not
CCRWrite=1'b0;
else if((ALU_op==ADZ||ALU_op==NDZ) &&(CCRMux_out[1]==1'b1)) //previous zero flag set or not
CCRWrite=1'b0;
else
CCRWrite=1'b1;
end
endmodule
module alu(in1, in2, op, out, zero, carry);
output [15:0] out;
output zero, carry;
input [15:0] in1, in2;
input op;
wire [15:0] outAdd, outNand;
wire carryAdd;
nor n1(zero,out[0],out[1],out[2],out[3],out[4],out[5],out[6],out[7],out[8],out[9],out[10],out[11],out[12],out[13],out[14],out[15]);
mux16x2 m1(outAdd, outNand, op, out);
adder16 add1(.in1(in1), .in2(in2), .out(outAdd), .carry(carryAdd));
nand16 nand1(.in1(in1), .in2(in2), .out(outNand));
assign carry = (op==0)?carryAdd:1'b0;
endmodule
module mux16x8(data0, data1, data2, data3, data4, data5, data6, data7, selectInput, out); // 8-16bit-input mux
output reg [15:0] out;
input [15:0] data0, data1, data2, data3, data4, data5, data6, data7;
input [2:0] selectInput;
always@(data0 or data1 or data2 or data3 or data4 or data5 or data6 or data7 or selectInput) begin
case(selectInput)
0: out = data0;
1: out = data1;
2: out = data2;
3: out = data3;
4: out = data4;
5: out = data5;
6: out = data6;
7: out = data7;
endcase
end
endmodule
module mux2x4(data0, data1, data2, data3,selectInput,out);
output reg[1:0] out;
input [1:0] data0, data1, data2, data3;
input [1:0] selectInput;
always@(data0 or data1 or data2 or data3 or selectInput) begin
case(selectInput)
0: out = data0;
1: out = data1;
2: out = data2;
3: out = data3;
endcase
end
endmodule
module mux16x4(data0, data1, data2, data3, selectInput, out); // 4-16bit-input mux
output reg [15:0] out;
input [15:0] data0, data1, data2, data3;
input [1:0] selectInput;
always@(data0 or data1 or data2 or data3 or selectInput) begin
case(selectInput)
0: out = data0;
1: out = data1;
2: out = data2;
3: out = data3;
endcase
end
endmodule
module mux16x2(data0, data1, selectInput, out); // 2-16bit-input mux
output reg [15:0] out;
input [15:0] data0, data1;
input selectInput;
always@(data0 or data1 or selectInput) begin
case(selectInput)
0: out = data0;
1: out = data1;
endcase
end
endmodule
module adder16(in1, in2 , out, carry); // Implements a full 16-bit adder
output [15:0] out;
output carry;
input [15:0] in1, in2;
wire [16:0] outTemp;
assign outTemp = in1 + in2;
assign out = outTemp[15:0];
assign carry = outTemp[16];
endmodule
module nand16(in1, in2, out); // Implements bitwise NAND for two 16-bit numbers
input [15:0] in1, in2;
output [15:0] out;
assign out = ~(in1 & in2);
endmodule
module register16(clk, out, in, write, reset); // Negedge-triggered flipflop register with active-low write signal and reset
output reg [15:0] out;
input [15:0] in;
input clk, write, reset;
always@(posedge clk) begin
if(reset==0) begin
out = 16'b0;
end
else if(write == 1'b0) begin
out = in;
end
end
endmodule
module register3(clk, out, in, write, reset); // Negedge-triggered flipflop register with active-low write signal and reset
output reg [2:0] out;
input [2:0] in;
input clk, write, reset;
always@(posedge clk) begin
if(reset==0) begin
out = 3'b0;
end
else if(write == 1'b0) begin
out = in;
end
end
endmodule
module register2(clk, out, in, write, reset); // Negedge-triggered flipflop register with active-low write signal and reset
output reg [1:0] out;
input [1:0] in;
input clk, write, reset;
always@(posedge clk) begin
if(reset==0) begin
out = 2'b0;
end
else if(write == 1'b0) begin
out = in;
end
end
endmodule
module register1(clk, out, in, write, reset); // Negedge-triggered flipflop register with active-low write signal and reset
output reg out;
input in;
input clk, write, reset;
always@(posedge clk) begin
if(reset==0) begin
out = 1'b0;
end
else if(write == 1'b0) begin
out = in;
end
end
endmodule
module forward_ex_stage(mem_wb_op,mem_wb_regA,mem_wb_regB,mem_wb_regC,ex_mem_op,ex_mem_regA,ex_mem_regB,ex_mem_regC,regread_ex_op,regread_ex_regA,regread_ex_regB,
regread_ex_regC,F1,F2,FCCR,mem_wb_CCR_write,ex_mem_CCR_write,writer7,writerf);
parameter ADD = 6'b000000;
parameter NDU = 6'b001000;
parameter ADC = 6'b000010;
parameter ADZ = 6'b000001;
parameter ADI = 4'b0001;
parameter NDC = 6'b001010;
parameter NDZ = 6'b001001;
parameter LHI = 4'b0011;
parameter LW = 4'b0100;
parameter SW = 4'b0101;
parameter LM = 4'b0110;
parameter SM = 4'b0111;
parameter BEQ = 4'b1100;
parameter JAL = 4'b1000;
parameter JLR = 4'b1001;
input [2:0] mem_wb_regA,mem_wb_regB,mem_wb_regC,ex_mem_regA,ex_mem_regB,ex_mem_regC,regread_ex_regA,regread_ex_regB,regread_ex_regC;
input [5:0]mem_wb_op,ex_mem_op,regread_ex_op;
input mem_wb_CCR_write,ex_mem_CCR_write;
output reg [2:0]F1,F2;
output reg [1:0]FCCR;
output reg rf,r7;
always @ (*)
begin
if(regread_ex_op==ADD||regread_ex_op==NDU||regread_ex_op==ADC||regread_ex_op==ADZ||regread_ex_op[5:2]==ADI||regread_ex_op==NDC||regread_ex_op==NDZ)
begin // for operators
if((regread_ex_regA==ex_mem_regC)&&(ex_mem_op==ADD||ex_mem_op==NDU||ex_mem_op==ADC||ex_mem_op==ADZ
||ex_mem_op==NDC||ex_mem_op==NDZ)&&(ex_mem_CCR_write==1'b0))
F1 = 3'b1;//a
else if((regread_ex_regA==ex_mem_regA)&&(ex_mem_op[5:2]==LHI))
F1 = 3'd5;//i
else if((regread_ex_regA==mem_wb_regC)&&(mem_wb_op==ADD||mem_wb_op==NDU||mem_wb_op==ADC
||mem_wb_op==ADZ||mem_wb_op==NDC
||mem_wb_op==NDZ)&&(mem_wb_CCR_write==1'b0))
F1 = 3'd2;//b
else if((regread_ex_regA==mem_wb_regA)&&(mem_wb_op[5:2]==LHI))
F1 = 3'd6;//j
else if((regread_ex_regA == mem_wb_regA)&&(mem_wb_op[5:2] ==LW||mem_wb_op[5:2] ==LM))//wait till praveen completes LM to verify
F1 = 3'd3; //forwarded from memory
else if((regread_ex_regA == mem_wb_regA)&&(mem_wb_op[5:2] == JAL))
F1 = 3'd7; //forwarded PC+1
else if((regread_ex_regA == ex_mem_regB)&&(ex_mem_op[5:2]==ADI)
&&(ex_mem_CCR_write==1'b0))
F1 = 3'b1;//a
else if((regread_ex_regA == ex_mem_regB)&&(mem_wb_op[5:2]==ADI)
&&(mem_wb_CCR_write==1'b0))
F1 = 3'd2;//b
else //no hazard, given the current instruction is op
F1 = 3'b0;
end // for operators
/* else if(regread_ex_op[5:2]==LM) //wrong
begin
if((regread_ex_regA == ex_mem_regC)&&(ex_mem_op==ADD||ex_mem_op==NDU
||ex_mem_op==ADC||ex_mem_op==ADZ
||ex_mem_op==NDC||ex_mem_op==NDZ)&&(ex_mem_CCR_write==1'b0))
F1 = 3'b1;//a
else if((regread_ex_regA == mem_wb_regC)&&(mem_wb_op==ADD||mem_wb_op==NDU||mem_wb_op==ADC
||mem_wb_op==ADZ||mem_wb_op==NDC
||mem_wb_op==NDZ)&&(mem_wb_CCR_write==1'b0))
F1 = 3'd2;//b
else if((regread_ex_regA==ex_mem_regA)&&(ex_mem_op==LHI))
F1 = 3'd5;//i
else if((regread_ex_regA==mem_wb_regA)&&(mem_wb_op==LHI))
F1 = 3'd6;//j
else if((regread_ex_regA == mem_wb_regA)&&(mem_wb_op[5:2]==LW||mem_wb_op[5:2]==LM))
F1 = 3'd3;
else if((regread_ex_regA == mem_wb_regA)&& (mem_wb_op[5:2] ==JAL))
F1 = 3'd7;//k -> PC+1
else
F1 = 3'b0; //no hazards,given current instruction is LM
end */
else
F1 = 3'b0;
end
always @ (*)
begin
if(regread_ex_op==ADD||regread_ex_op==NDU||regread_ex_op==ADC||regread_ex_op==ADZ||regread_ex_op==NDC||regread_ex_op==NDZ)//NO ADI as ADI has only regA
begin // for operators
if((regread_ex_regB==ex_mem_regC)&&(ex_mem_op==ADD||ex_mem_op==NDU||ex_mem_op==ADC||ex_mem_op==ADZ
||ex_mem_op==NDC||ex_mem_op==NDZ)&&(ex_mem_CCR_write==1'b0))
F2 = 3'b1;//a
else if((regread_ex_regB==ex_mem_regC)&&(mem_wb_op==ADD||mem_wb_op==NDU||mem_wb_op==ADC
||mem_wb_op==ADZ||mem_wb_op==NDC
||mem_wb_op==NDZ)&&(mem_wb_CCR_write==1'b0))
F2 = 3'd2;//b
else if((regread_ex_regB==ex_mem_regA)&&(ex_mem_op[5:2]==LHI))
F2 = 3'd5;//i
else if((regread_ex_regB==mem_wb_regA)&&(mem_wb_op[5:2]==LHI))
F2 = 3'd6;//j
else if((regread_ex_regB == mem_wb_regA)&&(mem_wb_op[5:2] ==LW||mem_wb_op[5:2] ==LM))//wait till praveen completes LM to verify
F2 = 3'd3; //forwarded from memory
else if((regread_ex_regB == mem_wb_regA)&&(mem_wb_op[5:2] == JAL))
F2 = 3'd7; //forwarded PC+1
else if((regread_ex_regB == ex_mem_regB)&&(ex_mem_op[5:2]==ADI)&&(ex_mem_CCR_write==1'b0))
F2 = 3'b1;//a
else if((regread_ex_regB == ex_mem_regB)&&(mem_wb_op[5:2]==ADI)&&(mem_wb_CCR_write==1'b0))
F2 = 3'd2;//b
else
F2 = 3'd0;//no hazards when current instruction is op
end // for operators
else if(regread_ex_op[5:2]==LW)
begin
if((regread_ex_regB == ex_mem_regC)&&(ex_mem_op==ADD||ex_mem_op==NDU||ex_mem_op==ADC||ex_mem_op==ADZ
||ex_mem_op==NDC||ex_mem_op==NDZ)&&(ex_mem_CCR_write==1'b0))
F2 = 3'b1;//a
else if((regread_ex_regB == ex_mem_regC)&&(mem_wb_op==ADD||mem_wb_op==NDU||mem_wb_op==ADC
||mem_wb_op==ADZ||mem_wb_op==NDC
||mem_wb_op==NDZ)&&(mem_wb_CCR_write==1'b0))
F2 = 3'd2;//b
else if((regread_ex_regB==ex_mem_regA)&&(ex_mem_op==LHI))
F2 = 3'd5;//i
else if((regread_ex_regB==mem_wb_regA)&&(mem_wb_op==LHI))
F2 = 3'd6;//j
else if((regread_ex_regB == mem_wb_regA)&&(mem_wb_op[5:2]==LW||mem_wb_op[5:2]==LM))
F2 = 3'd3;
else if((regread_ex_regB == mem_wb_regA)&& (mem_wb_op[5:2] ==JAL))
F2 = 3'd7;//k -> PC+1
else
F2 = 3'b0; //no hazards,given current instruction is LW
end
else if(regread_ex_op[5:2]==SW)
begin
if((regread_ex_regB == ex_mem_regC)&&(ex_mem_op==ADD||ex_mem_op==NDU||ex_mem_op==ADC||ex_mem_op==ADZ
||ex_mem_op==NDC||ex_mem_op==NDZ)&&(ex_mem_CCR_write==1'b0))
F2 = 3'b1;//a
else if((regread_ex_regB == mem_wb_regC)&&(mem_wb_op==ADD||mem_wb_op==NDU||mem_wb_op==ADC
||mem_wb_op==ADZ||mem_wb_op==NDC
||mem_wb_op==NDZ)&&(mem_wb_CCR_write==1'b0))
F2 = 3'd2;//b
else if((regread_ex_regB==ex_mem_regA)&&(ex_mem_op==LHI))
F2 = 3'd5;//i
else if((regread_ex_regB==mem_wb_regA)&&(mem_wb_op==LHI))
F2 = 3'd6;//j
else if((regread_ex_regB == mem_wb_regA)&& (mem_wb_op[5:2] ==JAL))
F2 = 3'd7;//k -> PC+1
else if((regread_ex_regB == mem_wb_regA)&&(mem_wb_op[5:2] ==LW||mem_wb_op[5:2] ==LM))//wait till praveen completes LM to verify
F2 = 3'd3; //forwarded from memory
else
F2 = 3'd0;
end
else
F2 = 3'b0;
end
always @(*)
begin
if(regread_ex_op==ADC||regread_ex_op==ADZ||regread_ex_op==NDC||regread_ex_op==NDZ)
begin
if((ex_mem_op==ADD||ex_mem_op==NDU||ex_mem_op==ADC||ex_mem_op==ADZ||ex_mem_op[5:2]==ADI||ex_mem_op==NDC||ex_mem_op==NDZ)&&(ex_mem_CCR_write==1'b0))//if the current op is conditional on CCR, CCR needs to be forwarded
begin
FCCR = 2'b1;
if(regread_ex_regC==3'b111)
begin
writer7=1'b0;
writerf=1'b1;
end
else
writer7=1'b1;
writerf=1'b0;
end
else if((mem_wb_op==ADD||mem_wb_op==NDU||mem_wb_op==ADC||mem_wb_op==ADZ||mem_wb_op[5:2]==ADI||mem_wb_op==NDC||mem_wb_op==NDZ)&&(mem_wb_CCR_write==1'b0))
begin
FCCR = 2'd2;
if(regread_ex_regC==3'b111)
begin
writer7=1'b0;
writerf=1'b1;
end
else
begin
writer7=1'b1;
writerf=1'b0;
end
end
else if((regread_ex_op==ADZ||regread_ex_op==NDZ)&&(ex_mem_op==LW)&&(ex_mem_CCR_write==1'b0))
begin
FCCR = 2'b1;
if(regread_ex_regC==3'b111)
begin
writer7=1'b0;
writerf=1'b1;
end
else
begin
writer7=1'b1;
writerf=1'b0;
end
end
else if((regread_ex_op==ADZ||regread_ex_op==NDZ)&&(mem_wb_op==LW)&&(mem_wb_CCR_write==1'b0))
begin
FCCR = 2'd2;
if(regread_ex_regC==3'b111)
begin
writer7=1'b0;
writerf=1'b1;
end
else
begin
writer7=1'b1;
writerf=1'b0;
end
end
else
begin
FCCR = 2'b0;
if(regread_ex_regC==3'b111)
begin
writer7=1'b0;
writerf=1'b1;
end
else
begin
writer7=1'b1;
writerf=1'b0;
end
end
else if(regread_ex_op==ADC||regread_ex_op==NDU)
begin
FCCR = 2'b0;
if(regread_ex_regC==3'b111)
begin
writer7=1'b0;
writerf=1'b1;
end
else
begin
writer7=1'b1;
writerf=1'b0;
end
end//unconditional operations
else if(regread_ex_op==LW||regread_ex_op==LM||regread_ex_op==LHI)
begin
FCCR = 2'b0;
if(regread_ex_regA==3'b111)
begin
writer7=1'b0;
writerf=1'b1;
end
else
begin
writer7=1'b1;
writerf=1'b0;
end
end//load operations
else if(regread_ex_op==JAL||regread_ex_op==JLR)
begin
FCCR=2'b0;
writer7=1'b1;
writerf=1'b0;
end//jump operations, which modiy registers
else
begin
FCCR=1'b0;
writer7=1'b1;
writerf=1'b1;
end
end
endmodule
|
//*****************************************************************************
//(c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : qdr_rld_phy_read_stage2_cal.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Nov 10 2008
// \___\/\___\
//
//Device: 7 Series
//Design: QDRII+ SRAM / RLDRAM II SDRAM
//
//Purpose:
// This module
// 1. Sets the latency for fixed latency mode.
// 2. Matches latency across multiple memories.
// 3. Determines the amount of latency delay required to generate the valids.
//
//Revision History: 4/27/2013 Fixed "error_adj_latency" such that if target PHY_LATENCY is
// less than measured latency will cause calibration not complete in FIXED_LATENCY_MODE = 1.
// 4/29/2013 Increased the pi_edge_adv_wait_cnt bus width .
////////////////////////////////////////////////////////////////////////////////
`timescale 1ps/1ps
module mig_7series_v2_0_qdr_rld_phy_read_stage2_cal #
(
parameter BURST_LEN = 4, // Burst Length
parameter MEM_TYPE = "QDR2PLUS",
parameter nCK_PER_CLK = 2,
parameter DATA_WIDTH = 72, // Total data width across all memories
parameter BW_WIDTH = 8,
parameter N_DATA_LANES = 4, // Number of memory devices - for v7 should reflect no. of byte lanes
parameter BYTE_LANE_WIDTH = 9, // Width of each memory - needs to now reflect widht of the byte group.
parameter FIXED_LATENCY_MODE = 0, // 0 = minimum latency mode, 1 = fixed latency mode
parameter PHY_LATENCY = 16, // Indicates the desired latency for fixed latency mode
parameter TCQ = 100 // Register delay
)
(
// System Signals
input clk, // main system half freq clk
input rst_clk, // reset syncrhonized to clk
input edge_adv_cal_start, // Start edge adv cal
input [3:0] dbg_byte_sel,
output reg edge_adv_cal_done, // indicates all the byte lanes are now aligned to rising edge of clk_div
input cal_stage2_start, // indicates latency calibration has begun
output reg cal_done, // indicates overall calibration is complete
// Write Interface
input [nCK_PER_CLK-1:0] int_rd_cmd_n, // read command(s) - only bit 0 is used for BL4
// DCB Interface
input [nCK_PER_CLK*DATA_WIDTH-1:0] iserdes_rd,
input [nCK_PER_CLK*DATA_WIDTH-1:0] iserdes_fd,
output reg [N_DATA_LANES-1:0] phase_valid,
output reg [N_DATA_LANES-1:0] inc_latency = 0, // indicates latency through a DCB to be increased
// Valid Generator Interface
output reg [4:0] valid_latency, // amount to delay read command
output reg pi_edge_adv,
output reg bitslip,
output reg [2:0] byte_cnt,
output reg max_lat_done_r, // delayed version of max_lat_done
// Chipscope/Debug and Error
output reg [N_DATA_LANES-1:0] error_max_latency, // mem_latency counter has maxed out
output reg error_adj_latency, // target PHY_LATENCY is invalid
output [127:0] dbg_stage2_cal // general debug port
);
//Looking for a single rd command to generate our rd_valid
//Even if more read commands are sent to memory the phy is responsible to
//make sure it sends the expected pattern to this module to make sure we can
//figure out the data valid
localparam DIV2_RD_CMD_PATTERN = ((MEM_TYPE == "QDR2PLUS") && (BURST_LEN == 2)) ? 2'b00 : 2'b10 ;
localparam DIV4_RD_CMD_PATTERN = 4'b1110;
localparam RD_CMD_PATTERN = (nCK_PER_CLK == 2) ? DIV2_RD_CMD_PATTERN :
DIV4_RD_CMD_PATTERN;
//Wait time in clock cycles
//Max of 31 supported, else you need to expand register bits
localparam START_WAIT_TIME = (nCK_PER_CLK == 2) ? 3 : 12;
localparam PATTERN_2 = 9'h022;
localparam PATTERN_3 = 9'h133;
localparam PATTERN_5 = 9'h155;
localparam PATTERN_6 = 9'h066;
localparam PATTERN_9 = 9'h199;
localparam PATTERN_A = 9'h0AA;
localparam PATTERN_C = 9'h0CC;
localparam PATTERN_D = 9'h1DD;
// stage2 - R0_F0_R1_F1 : A-5-0-F pattern
localparam [DATA_WIDTH*4-1:0] LAT_CAL_DATA = { {BW_WIDTH{PATTERN_A}},{BW_WIDTH{PATTERN_5}},
{DATA_WIDTH{1'b0}},{DATA_WIDTH{1'b1}}};
localparam [DATA_WIDTH*4-1:0] LAT_CAL_DATA2 = { {DATA_WIDTH/9{PATTERN_9}},
{DATA_WIDTH/9{PATTERN_6}},
{DATA_WIDTH/9{PATTERN_D}},
{DATA_WIDTH/9{PATTERN_2}}};
// Wires and Regs
wire bl8_rd_cmd_int; // inidicates any BL8 rd_cmd
wire bl4_rd_cmd_int; // inidicates any BL4 rd_cmd
wire bl2_rd_cmd_int; // indicates any BL2 rd_cmd
reg bl8_rd_cmd_int_r; // delayed version of bl8_rd_cmd_int
reg bl8_rd_cmd_int_r2; // delayed version of bl8_rd_cmd_r
reg bl4_rd_cmd_int_r; // delayed version of bl4_rd_cmd_int
reg bl2_rd_cmd_int_r; // delayed version of bl2_rd_cmd_int
wire rd_cmd; // indicates rd_cmd for latency calibration
wire lat_measure_done; // indicates latency measurement is complete
wire en_mem_cntr; // memory counter enable
wire start_lat_adj; // indicates that latency adjustment can begin
reg en_mem_latency; // memory latency counter enable
reg [4:0] latency_cntr [N_DATA_LANES-1:0]; // counter indicating the latency for each memory in the inteface
reg [4:0] latency_cntr_r [N_DATA_LANES-1:0];
wire [DATA_WIDTH-1:0] rd0; // rising data 0 for all memories
wire [DATA_WIDTH-1:0] fd0; // falling data 0 for all memories
wire [DATA_WIDTH-1:0] rd1; // rising data 1 for all memories
wire [DATA_WIDTH-1:0] fd1; // falling data 1 for all memories
wire [DATA_WIDTH-1:0] rd2; // rising data 2 for all memories
wire [DATA_WIDTH-1:0] fd2; // falling data 2 for all memories
wire [DATA_WIDTH-1:0] rd3; // rising data 3 for all memories
wire [DATA_WIDTH-1:0] fd3; // falling data 3 for all memories
reg [DATA_WIDTH-1:0] rd1_r; // rising data 0 for all memories
reg [DATA_WIDTH-1:0] fd1_r; // rising data 0 for all memories
wire [DATA_WIDTH-1:0] rd0_lat; // rising data 0 latency cal training pattern
wire [DATA_WIDTH-1:0] fd0_lat; // falling data 0 latency cal training pattern
wire [DATA_WIDTH-1:0] rd1_lat; // rising data 1 latency cal training pattern
wire [DATA_WIDTH-1:0] fd1_lat; // falling data 1 latency cal training pattern
wire [DATA_WIDTH-1:0] rd2_lat; // rising data 2 latency cal training pattern
wire [DATA_WIDTH-1:0] fd2_lat; // falling data 2 latency cal training pattern
wire [DATA_WIDTH-1:0] rd3_lat; // rising data 3 latency cal training pattern
wire [DATA_WIDTH-1:0] fd3_lat; // falling data 3 latency cal training pattern
reg [N_DATA_LANES-1:0] rd0_vld; // indicates rd0 matches respective training pattern
reg [N_DATA_LANES-1:0] fd0_vld; // indicates fd0 matches respective training pattern
reg [N_DATA_LANES-1:0] rd1_vld; // indicates rd1 matches respective training pattern
reg [N_DATA_LANES-1:0] fd1_vld; // indicates fd1 matches respective training pattern
reg [N_DATA_LANES-1:0] rd2_vld; // indicates rd2 matches respective training pattern
reg [N_DATA_LANES-1:0] fd2_vld; // indicates fd2 matches respective training pattern
reg [N_DATA_LANES-1:0] rd3_vld; // indicates rd3 matches respective training pattern
reg [N_DATA_LANES-1:0] fd3_vld; // indicates fd3 matches respective training pattern
reg [N_DATA_LANES-1:0] rd0_bslip_vld; // indicates bitslip data matches respective training pattern
reg [N_DATA_LANES-1:0] fd0_bslip_vld; // indicates bitslip data matches respective training pattern
reg [N_DATA_LANES-1:0] rd1_bslip_vld; // indicates bitslip data matches respective training pattern
reg [N_DATA_LANES-1:0] fd1_bslip_vld; // indicates bitslip data matches respective training pattern
wire [N_DATA_LANES-1:0] phase_vld_check;
wire [N_DATA_LANES-1:0] phase_vld;
wire [N_DATA_LANES-1:0] phase_bslip_vld;
reg [N_DATA_LANES-1:0] phase_bslip_vld_chk;
reg [BW_WIDTH-1 :0] phase_error;
reg [3:0] pi_edge_adv_wait_cnt;
reg [4:0] mem_latency [N_DATA_LANES-1:0]; // register indicating the measured latency for each memory
reg [N_DATA_LANES-1:0] latency_measured; // indicates that the latency has been measured for each memory
reg [4:0] mem_cntr; // indicates which memory is being operated on
reg mem_cntr_done; // indicates mem_cntr has cycled through all memories
reg [4:0] max_latency; // maximum measured latency
reg max_lat_done; // indicates maximum latency measurement is done
reg [4:0] mem_lat_adj [N_DATA_LANES-1:0]; // amount latency needs incremented
reg [N_DATA_LANES-1:0] lat_adj_done; // indicates latency adjustment is done
reg inc_byte_cnt;
reg clkdiv_phase_cal_done_r;
reg clkdiv_phase_cal_done_2r;
reg clkdiv_phase_cal_done_3r;
reg clkdiv_phase_cal_done_4r;
reg clkdiv_phase_cal_done_5r;
reg clkdiv_phase_cal_done; // clkdiv alignment done
reg cal_stage2_done;
reg edge_adv_cal_start_r;
reg edge_adv_cal_start_r2;
reg [4:0] cal_stage2_cnt;
reg [4:0] start_cnt;
wire [4:0] latency_cntr_0;
wire [4:0] latency_cntr_1;
wire [4:0] mem_latency_0;
wire [4:0] mem_latency_1;
wire [4:0] mem_lat_adj_0;
wire [4:0] mem_lat_adj_1;
assign latency_cntr_0 = latency_cntr[0];
assign latency_cntr_1 = latency_cntr[1];
assign mem_latency_0 = mem_latency[0];
assign mem_latency_1 = mem_latency[1];
assign mem_lat_adj_0 = mem_lat_adj[0];
assign mem_lat_adj_1 = mem_lat_adj[1];
//Generic start signal
always @(posedge clk) begin
if (rst_clk) begin
edge_adv_cal_start_r <= #TCQ 0;
end else if (start_cnt == (START_WAIT_TIME-1)) begin
edge_adv_cal_start_r <= #TCQ 1;
end else begin
edge_adv_cal_start_r <= #TCQ edge_adv_cal_start_r;
end
end
//Extra register since we want to give our comparison one chance to do a check
//before we decide what to do. Comparison starts with edge_adv_cal_start_r
//while checking the result begins a cycle later
always @(posedge clk) begin
if (rst_clk)
edge_adv_cal_start_r2 <= #TCQ 0;
else
edge_adv_cal_start_r2 <= #TCQ edge_adv_cal_start_r;
end
//Create a counter so we don't start bitslipping the data too soon before
//valid data is to be on the bus
always @(posedge clk) begin
if (rst_clk) begin
start_cnt <= #TCQ 0;
end else if (edge_adv_cal_start && start_cnt != START_WAIT_TIME) begin
start_cnt <= #TCQ start_cnt + 1;
end else
start_cnt <= #TCQ start_cnt;
end
// Create rd_cmd for BL8, BL4 and BL2. BL8/BL4 only uses one bit for incoming
// rd_cmd's. Since this stage of calibration can't start until stage 1 is
// complete, mask off all incoming rd_cmd's until stage 2 begins. There can
// be rd_cmd's from the stage 1 calibration just after stage 2 starts. These
// will be masked off by looking for the rising edge of rd_cmd.
assign bl8_rd_cmd_int = (BURST_LEN == 8) && (int_rd_cmd_n == RD_CMD_PATTERN);
assign bl4_rd_cmd_int = (BURST_LEN == 4) && (int_rd_cmd_n == RD_CMD_PATTERN);
assign bl2_rd_cmd_int = (BURST_LEN == 2) && (int_rd_cmd_n == RD_CMD_PATTERN);
always @(posedge clk) begin
if (rst_clk) begin
bl8_rd_cmd_int_r <= #TCQ 0;
bl8_rd_cmd_int_r2 <= #TCQ 0;
end else begin
bl8_rd_cmd_int_r <= #TCQ bl8_rd_cmd_int;
bl8_rd_cmd_int_r2 <= #TCQ bl8_rd_cmd_int_r;
end
end
always @(posedge clk) begin
if (rst_clk)
bl4_rd_cmd_int_r <= #TCQ 0;
else
bl4_rd_cmd_int_r <= #TCQ bl4_rd_cmd_int;
end
always @(posedge clk) begin
if (rst_clk)
bl2_rd_cmd_int_r <= #TCQ 0;
else
bl2_rd_cmd_int_r <= #TCQ bl2_rd_cmd_int;
end
//generate the rd_cmd flag
generate
if (BURST_LEN == 8) begin: BL8_RD_CMD
assign rd_cmd = bl8_rd_cmd_int && !bl8_rd_cmd_int_r &&
!bl8_rd_cmd_int_r2 && cal_stage2_start && !cal_stage2_done;
end else if (BURST_LEN == 4) begin : BL4_RD_CMD
assign rd_cmd = bl4_rd_cmd_int && !bl4_rd_cmd_int_r &&
cal_stage2_start && !cal_stage2_done;
end else if (BURST_LEN == 2) begin : BL2_RD_CMD
assign rd_cmd = bl2_rd_cmd_int && !bl2_rd_cmd_int_r &&
cal_stage2_start && !cal_stage2_done;
end
endgenerate
always @ (posedge clk) begin
if (rst_clk) begin
cal_stage2_cnt <= 0;
end else if (edge_adv_cal_done && (cal_stage2_cnt != 5'h1F) ) begin
cal_stage2_cnt <= cal_stage2_cnt + 1;
end
end
// Create an enable for the latency counter. Enable it whenver the
// appropriate rd_cmd is seen from the initialization logic in the write
// interface. Since only one rd_cmd is issued during this phase, it can
// remain enabled after asserted for the first time.
always @(posedge clk) begin
if (rst_clk)
en_mem_latency <= #TCQ 0;
else if (cal_stage2_done)
en_mem_latency <= #TCQ 0;
else if (rd_cmd ) // rd_cmd is active only when cal_stage2_start has started..
en_mem_latency <= #TCQ 1;
end
assign rd0 = iserdes_rd[DATA_WIDTH-1:0];
assign fd0 = iserdes_fd[DATA_WIDTH-1:0];
assign rd1 = iserdes_rd[2*DATA_WIDTH-1:DATA_WIDTH];
assign fd1 = iserdes_fd[2*DATA_WIDTH-1:DATA_WIDTH];
generate
if (nCK_PER_CLK == 4) begin : gen_rd_div4
assign rd2 = iserdes_rd[3*DATA_WIDTH-1:2*DATA_WIDTH];
assign fd2 = iserdes_fd[3*DATA_WIDTH-1:2*DATA_WIDTH];
assign rd3 = iserdes_rd[4*DATA_WIDTH-1:3*DATA_WIDTH];
assign fd3 = iserdes_fd[4*DATA_WIDTH-1:3*DATA_WIDTH];
end
endgenerate
// For each memory in the interface, determine the latency from the time the
// rd_cmd is issued until the expected read back data is received. This
// determines the latency of the system.
genvar nd_i;
generate
// check for each byte lane
for (nd_i=0; nd_i < DATA_WIDTH/9; nd_i=nd_i+1) begin : mem_lat_inst
// Count the number of cycles from the time that the rd_cmd is seen. This
// will be used to determine how long for the read data to be returned and
// hence the read latency. If latency_cntr counter maxes out, issue an
// error. This is either because the latency of the read is higher than
// the design can handle or because the latency calibration readback data
// of AA's was never correctly received. The latency counter begins
// counting from 1 since there is an additional cycle of latency in the
// read path not accounted for by this read command from the
// initialization logic.
always @(posedge clk) begin
if (rst_clk) begin
latency_cntr[nd_i] <= #TCQ 1;
error_max_latency[nd_i] <= #TCQ 0;
end else if (latency_cntr[nd_i] == 5'h1F) begin
latency_cntr[nd_i] <= #TCQ 5'h1F;
if (!latency_measured[nd_i])
error_max_latency[nd_i] <= #TCQ 1;
else
error_max_latency[nd_i] <= #TCQ 0;
end else if (en_mem_latency || rd_cmd) begin
latency_cntr[nd_i] <= #TCQ latency_cntr[nd_i] + 1'b1;
error_max_latency[nd_i] <= #TCQ 0;
end
end
// Break apart the read_data bus into the various rising and falling data
// groups for each memory. The read_data bus is constructed as follows:
// read_data = {rd0, fd0, rd1, fd1}
// rd0 = {rd0[n], ..., rd0[1], rd0[0]}
// fd0 = {fd0[n], ..., fd0[1], fd0[0]}
// rd1 = {rd1[n], ..., rd1[1], rd1[0]}
// fd1 = {fd1[n], ..., fd1[1], fd1[0]}
// assign rd0[nd_i*BYTE_LANE_WIDTH+:BYTE_LANE_WIDTH] =
// read_data[(nd_i*BYTE_LANE_WIDTH+BYTE_LANE_WIDTH*N_DATA_LANES*0)+:BYTE_LANE_WIDTH];
// assign fd0[nd_i*BYTE_LANE_WIDTH+:BYTE_LANE_WIDTH] =
// read_data[(nd_i*BYTE_LANE_WIDTH+BYTE_LANE_WIDTH*N_DATA_LANES*1)+:BYTE_LANE_WIDTH];
// assign rd1[nd_i*BYTE_LANE_WIDTH+:BYTE_LANE_WIDTH] =
// read_data[(nd_i*BYTE_LANE_WIDTH+BYTE_LANE_WIDTH*N_DATA_LANES*2)+:BYTE_LANE_WIDTH];
// assign fd1[nd_i*BYTE_LANE_WIDTH+:BYTE_LANE_WIDTH] =
// read_data[(nd_i*BYTE_LANE_WIDTH+BYTE_LANE_WIDTH*N_DATA_LANES*3)+:BYTE_LANE_WIDTH];
// Pull off the respective LAT_CAL_DATA for each group of data.
assign rd0_lat[nd_i*BYTE_LANE_WIDTH+:BYTE_LANE_WIDTH] =
LAT_CAL_DATA[(nd_i*BYTE_LANE_WIDTH+BYTE_LANE_WIDTH*N_DATA_LANES*3)+:BYTE_LANE_WIDTH];
assign fd0_lat[nd_i*BYTE_LANE_WIDTH+:BYTE_LANE_WIDTH] =
LAT_CAL_DATA[(nd_i*BYTE_LANE_WIDTH+BYTE_LANE_WIDTH*N_DATA_LANES*2)+:BYTE_LANE_WIDTH];
assign rd1_lat[nd_i*BYTE_LANE_WIDTH+:BYTE_LANE_WIDTH] =
LAT_CAL_DATA[(nd_i*BYTE_LANE_WIDTH+BYTE_LANE_WIDTH*N_DATA_LANES*1)+:BYTE_LANE_WIDTH];
assign fd1_lat[nd_i*BYTE_LANE_WIDTH+:BYTE_LANE_WIDTH] =
LAT_CAL_DATA[(nd_i*BYTE_LANE_WIDTH+BYTE_LANE_WIDTH*N_DATA_LANES*0)+:BYTE_LANE_WIDTH];
//Seperate data pattern used for DIV4 mode
assign rd2_lat[nd_i*BYTE_LANE_WIDTH+:BYTE_LANE_WIDTH] =
LAT_CAL_DATA2[(nd_i*BYTE_LANE_WIDTH+BYTE_LANE_WIDTH*N_DATA_LANES*3)+:BYTE_LANE_WIDTH];
assign fd2_lat[nd_i*BYTE_LANE_WIDTH+:BYTE_LANE_WIDTH] =
LAT_CAL_DATA2[(nd_i*BYTE_LANE_WIDTH+BYTE_LANE_WIDTH*N_DATA_LANES*2)+:BYTE_LANE_WIDTH];
assign rd3_lat[nd_i*BYTE_LANE_WIDTH+:BYTE_LANE_WIDTH] =
LAT_CAL_DATA2[(nd_i*BYTE_LANE_WIDTH+BYTE_LANE_WIDTH*N_DATA_LANES*1)+:BYTE_LANE_WIDTH];
assign fd3_lat[nd_i*BYTE_LANE_WIDTH+:BYTE_LANE_WIDTH] =
LAT_CAL_DATA2[(nd_i*BYTE_LANE_WIDTH+BYTE_LANE_WIDTH*N_DATA_LANES*0)+:BYTE_LANE_WIDTH];
//**************************************************************************************************
//added for v7 - to check for bitslip valid?
always @ (posedge clk) begin
rd1_r[nd_i*BYTE_LANE_WIDTH+:BYTE_LANE_WIDTH] <= rd1[nd_i*BYTE_LANE_WIDTH+:BYTE_LANE_WIDTH] ;
fd1_r[nd_i*BYTE_LANE_WIDTH+:BYTE_LANE_WIDTH] <= fd1[nd_i*BYTE_LANE_WIDTH+:BYTE_LANE_WIDTH] ;
end
//*********************************************************************************************************************************8
// Indicate if the data for each memory matches the respective LAT_CAL_DATA.
// check for R0-F0-R1-F1 alignment in the same clkdiv cycle
always @(posedge clk)
begin
if (rst_clk)
begin
rd0_vld[nd_i] <= #TCQ 'b0;
fd0_vld[nd_i] <= #TCQ 'b0;
rd1_vld[nd_i] <= #TCQ 'b0;
fd1_vld[nd_i] <= #TCQ 'b0;
rd2_vld[nd_i] <= #TCQ 'b0;
fd2_vld[nd_i] <= #TCQ 'b0;
rd3_vld[nd_i] <= #TCQ 'b0;
fd3_vld[nd_i] <= #TCQ 'b0;
end else
begin
rd0_vld[nd_i] <= #TCQ (rd0[nd_i*BYTE_LANE_WIDTH+:BYTE_LANE_WIDTH] ==
rd0_lat[nd_i*BYTE_LANE_WIDTH+:BYTE_LANE_WIDTH]);
fd0_vld[nd_i] <= #TCQ (fd0[nd_i*BYTE_LANE_WIDTH+:BYTE_LANE_WIDTH] ==
fd0_lat[nd_i*BYTE_LANE_WIDTH+:BYTE_LANE_WIDTH]);
rd1_vld[nd_i] <= #TCQ (rd1[nd_i*BYTE_LANE_WIDTH+:BYTE_LANE_WIDTH] ==
rd1_lat[nd_i*BYTE_LANE_WIDTH+:BYTE_LANE_WIDTH]);
fd1_vld[nd_i] <= #TCQ (fd1[nd_i*BYTE_LANE_WIDTH+:BYTE_LANE_WIDTH] ==
fd1_lat[nd_i*BYTE_LANE_WIDTH+:BYTE_LANE_WIDTH]);
rd2_vld[nd_i] <= #TCQ (rd2[nd_i*BYTE_LANE_WIDTH+:BYTE_LANE_WIDTH] ==
rd2_lat[nd_i*BYTE_LANE_WIDTH+:BYTE_LANE_WIDTH]);
fd2_vld[nd_i] <= #TCQ (fd2[nd_i*BYTE_LANE_WIDTH+:BYTE_LANE_WIDTH] ==
fd2_lat[nd_i*BYTE_LANE_WIDTH+:BYTE_LANE_WIDTH]);
rd3_vld[nd_i] <= #TCQ (rd3[nd_i*BYTE_LANE_WIDTH+:BYTE_LANE_WIDTH] ==
rd3_lat[nd_i*BYTE_LANE_WIDTH+:BYTE_LANE_WIDTH]);
fd3_vld[nd_i] <= #TCQ (fd3[nd_i*BYTE_LANE_WIDTH+:BYTE_LANE_WIDTH] ==
fd3_lat[nd_i*BYTE_LANE_WIDTH+:BYTE_LANE_WIDTH]);
end
end
//assign data_vld[nd_i] = edge_adv_cal_start_r && rd0_vld[nd_i] && fd0_vld[nd_i] && rd1_vld[nd_i] && fd1_vld[nd_i];
assign phase_vld[nd_i] = (nCK_PER_CLK == 2) ? (edge_adv_cal_start_r && rd0_vld[nd_i] && fd0_vld[nd_i] && rd1_vld[nd_i] && fd1_vld[nd_i]) :
(edge_adv_cal_start_r && rd0_vld[nd_i] && fd0_vld[nd_i] && rd1_vld[nd_i] && fd1_vld[nd_i]
&& rd2_vld[nd_i] && fd2_vld[nd_i] && rd3_vld[nd_i] && fd3_vld[nd_i]);
////////////////////////////////////////////////////////////////////////////////
// added for v7 - to check for phase alignment to clkdiv edge.
////////////////////////////////////////////////////////////////////////////////
// Indicate if the data for each memory matches the respective LAT_CAL_DATA.
// check for x-x-R0-F0/R1-F1-x-x alignment across two clkdiv cycles
always @(posedge clk)
begin
if (rst_clk)
begin
rd0_bslip_vld[nd_i] <= #TCQ 'b0;
fd0_bslip_vld[nd_i] <= #TCQ 'b0;
rd1_bslip_vld[nd_i] <= #TCQ 'b0;
fd1_bslip_vld[nd_i] <= #TCQ 'b0;
end else begin
rd0_bslip_vld[nd_i] <= #TCQ (rd1_r[nd_i*BYTE_LANE_WIDTH+:BYTE_LANE_WIDTH] ==
rd0_lat[nd_i*BYTE_LANE_WIDTH+:BYTE_LANE_WIDTH]);
fd0_bslip_vld[nd_i] <= #TCQ (fd1_r[nd_i*BYTE_LANE_WIDTH+:BYTE_LANE_WIDTH] ==
fd0_lat[nd_i*BYTE_LANE_WIDTH+:BYTE_LANE_WIDTH]);
rd1_bslip_vld[nd_i] <= #TCQ (rd0[nd_i*BYTE_LANE_WIDTH+:BYTE_LANE_WIDTH] ==
rd1_lat[nd_i*BYTE_LANE_WIDTH+:BYTE_LANE_WIDTH]);
fd1_bslip_vld[nd_i] <= #TCQ (fd0[nd_i*BYTE_LANE_WIDTH+:BYTE_LANE_WIDTH] ==
fd1_lat[nd_i*BYTE_LANE_WIDTH+:BYTE_LANE_WIDTH]);
end
end
assign phase_bslip_vld[nd_i] = (edge_adv_cal_start_r && rd0_bslip_vld[nd_i] && fd0_bslip_vld[nd_i] && rd1_bslip_vld[nd_i] && fd1_bslip_vld[nd_i]);
// check if either condition is true for nCK_PER_CLK == 2, for others
// rather than check them all we bitslip then check after
assign phase_vld_check[nd_i] = (nCK_PER_CLK == 2) ?
phase_vld[nd_i] || phase_bslip_vld[nd_i] :
phase_vld[nd_i];
// check to make sure all data lanes phases have been checked. Then phase_bslip_vld_chk for corresponding data lanes are updated if pi_edge_adv needs
// to be asserted for that particular byte lane.
always @ (posedge clk) begin
if (rst_clk) begin
phase_bslip_vld_chk[nd_i] <= #TCQ 0;
//when all data byte lanes have their phases checked - clkdiv_phase_cal_done_r is high.
end else if (clkdiv_phase_cal_done_r) begin
phase_bslip_vld_chk[nd_i] <= #TCQ phase_bslip_vld[nd_i];
end
end
/////////////////////////////////////////////////////////////////////////////////////////
// Capture the current latency count when the received data
// (LAT_CAL_DATA) is seen. Also indicate that the latency has been
// measured for this memory.
always @(posedge clk) begin
if (rst_clk) begin
mem_latency[nd_i] <= #TCQ 0;
latency_measured[nd_i] <= #TCQ 0;
end else if (en_mem_latency && rd0_vld[nd_i] && fd0_vld[nd_i] &&
rd1_vld[nd_i] && fd1_vld[nd_i]) begin
if (nCK_PER_CLK == 2 ||
(nCK_PER_CLK == 4 &&
rd2_vld[nd_i] && fd2_vld[nd_i] &&
rd3_vld[nd_i] && fd3_vld[nd_i])) begin
mem_latency[nd_i] <= #TCQ latency_cntr_r[nd_i] ;
latency_measured[nd_i] <= #TCQ 1;
end
end
end
always @(posedge clk) begin
if (rst_clk)
latency_cntr_r[nd_i] <= #TCQ 0;
else
latency_cntr_r[nd_i] <= #TCQ latency_cntr[nd_i];
end
end //end mem_lat_inst
endgenerate
// read data alignment to the posedge of iclkdiv is done when all the read data (R0,F0,R1,F1) pattern are as expected.
always @ (posedge clk) begin
if (rst_clk) begin
clkdiv_phase_cal_done <= #TCQ 0;
clkdiv_phase_cal_done_r <= #TCQ 0;
clkdiv_phase_cal_done_2r <= #TCQ 0;
clkdiv_phase_cal_done_3r <= #TCQ 0;
clkdiv_phase_cal_done_4r <= #TCQ 0;
clkdiv_phase_cal_done_5r <= #TCQ 0;
end else begin
clkdiv_phase_cal_done <= #TCQ &phase_vld_check;
clkdiv_phase_cal_done_r <= #TCQ clkdiv_phase_cal_done;
clkdiv_phase_cal_done_2r <= #TCQ clkdiv_phase_cal_done_r;
clkdiv_phase_cal_done_3r <= #TCQ clkdiv_phase_cal_done_2r;
clkdiv_phase_cal_done_4r <= #TCQ clkdiv_phase_cal_done_3r;
clkdiv_phase_cal_done_5r <= #TCQ clkdiv_phase_cal_done_4r;
end
end
// counter to check for phase alignment per byte group
always @ (posedge clk) begin
if (rst_clk) begin
byte_cnt <= #TCQ 0;
end else if (inc_byte_cnt) begin
byte_cnt <= byte_cnt +1;
end
end
// need to assert edge_adv for corresponding phaser_ins where the first rise data aligns to the negedge of clkdiv.
// phase_vld refers to the case where edge_adv does not need to be asserted, phase_bslip_vld refers
// to the condition where edge_adv needs to be asserted for that byte group.
always @ (posedge clk) begin
if (rst_clk) begin
pi_edge_adv <= #TCQ 0;
bitslip <= #TCQ 0;
phase_error <= #TCQ 0;
pi_edge_adv_wait_cnt <= #TCQ 0;
inc_byte_cnt <= #TCQ 0;
end else begin
if (nCK_PER_CLK == 2) begin
if ((clkdiv_phase_cal_done_5r) && (!edge_adv_cal_done)) begin
if (phase_bslip_vld_chk[byte_cnt] == 1'b1 &&
pi_edge_adv_wait_cnt == 4'b0000) begin
pi_edge_adv <= #TCQ 1;
phase_error <= #TCQ 0;
pi_edge_adv_wait_cnt <= #TCQ 4'b1111;
inc_byte_cnt <= #TCQ 0;
end else if (phase_bslip_vld_chk[byte_cnt] == 1'b0 &&
pi_edge_adv_wait_cnt == 4'b0000) begin
pi_edge_adv <= #TCQ 0;
phase_error <= #TCQ 0;
pi_edge_adv_wait_cnt <= #TCQ 4'b1111;
inc_byte_cnt <= #TCQ 0;
end else if (pi_edge_adv_wait_cnt == 4'b0010) begin
pi_edge_adv <= #TCQ 0;
phase_error <= #TCQ 0;
pi_edge_adv_wait_cnt <= #TCQ pi_edge_adv_wait_cnt -1 ;
inc_byte_cnt <= #TCQ 1;
end else begin
pi_edge_adv <= #TCQ 0;
phase_error <= #TCQ 0;
pi_edge_adv_wait_cnt <= #TCQ pi_edge_adv_wait_cnt -1 ;
inc_byte_cnt <= #TCQ 0;
end
end //end of (clkdiv_phase_cal_done_5r) && (!edge_adv_cal_done)
end else begin //nCK_PER_CLK == 4
//Even though we don't use the edge_adv signal we use the same
//counter
if (edge_adv_cal_start_r2 && (!edge_adv_cal_done)) begin
if (phase_vld_check[byte_cnt] == 1'b1 &&
pi_edge_adv_wait_cnt == 4'b0000) begin
bitslip <= #TCQ 0;
phase_error <= #TCQ 0;
pi_edge_adv_wait_cnt <= #TCQ 4'b1111;
inc_byte_cnt <= #TCQ 1;
end else if (phase_vld_check[byte_cnt] == 1'b0 &&
pi_edge_adv_wait_cnt == 4'b0000) begin
bitslip <= #TCQ 1;
phase_error <= #TCQ 0;
pi_edge_adv_wait_cnt <= #TCQ 4'b1111;
inc_byte_cnt <= #TCQ 0;
end else if (pi_edge_adv_wait_cnt == 4'b0010) begin
bitslip <= #TCQ 0;
phase_error <= #TCQ 0;
pi_edge_adv_wait_cnt <= #TCQ pi_edge_adv_wait_cnt -1 ;
inc_byte_cnt <= #TCQ 0;
end else begin
bitslip <= #TCQ 0;
phase_error <= #TCQ 0;
pi_edge_adv_wait_cnt <= #TCQ pi_edge_adv_wait_cnt -1 ;
inc_byte_cnt <= #TCQ 0;
end
end
end //end of //nCK_PER_CLK == 4
end //end of else
end //end of always
always @ (posedge clk) begin
if (rst_clk)
edge_adv_cal_done <= #TCQ 0;
else if (&(phase_vld))
edge_adv_cal_done <= #TCQ 1;
end
//****************************************************************************************************
// second half of the stage2 calibration : determining max latency of the system
//****************************************************************************************************
// Determine the maximum latency
generate
if (N_DATA_LANES == 1) begin : max_lat_inst_dev1
// With only one device, the maximum latency of the system is simply the
// the latency determined previously.
always @(posedge clk) begin
if (rst_clk)
max_latency <= #TCQ 0;
else if (latency_measured[0])
max_latency <= #TCQ mem_latency[0];
end
always @(posedge clk) begin
if (rst_clk)
max_lat_done <= #TCQ 0;
else if (latency_measured[0])
max_lat_done <= #TCQ 1;
end
end else begin : max_lat_inst
assign lat_measure_done = &latency_measured;
assign en_mem_cntr = (lat_measure_done && !mem_cntr_done);
// Counter that cycles through each memory which will be used to determine
// the largest latency in the system. It only starts counting after the
// latency has been measured for each device. Also indicates when all
// devices have been cycled through.
always @(posedge clk) begin
if (rst_clk) begin
mem_cntr <= #TCQ 0;
mem_cntr_done <= #TCQ 0;
end else if ((mem_cntr == (N_DATA_LANES - 1)) && lat_measure_done
&& !mem_cntr_done) begin
mem_cntr <= #TCQ mem_cntr;
mem_cntr_done <= #TCQ 1;
end else if (en_mem_cntr) begin
mem_cntr <= #TCQ mem_cntr + 1'b1;
mem_cntr_done <= #TCQ mem_cntr_done;
end
end
// As the counter for each memory device increments, the latency of that
// device is compared against the value in the max_latency register. If it
// is larger than the stored value, it replaces the max_latency value.
// This repeats for each device until the maximum latency is found.
always @(posedge clk) begin
if (rst_clk) begin
max_latency <= #TCQ 0;
end else if ((mem_latency[mem_cntr] > max_latency)
&& !mem_cntr_done) begin
max_latency <= #TCQ mem_latency[mem_cntr];
end
end
// Indicate when maximum latency measurement is complete.
always @(posedge clk) begin
if (rst_clk)
max_lat_done <= #TCQ 0;
else
max_lat_done <= #TCQ mem_cntr_done;
end
end
endgenerate
// Adjust the latency. For FIXED_LATENCY_MODE=1, the latency of each memory
// must be increased to the target PHY_LATENCY value. For
// FIXED_LATENCY_MODE=0, the latency of each memory is increased to the max
// latency of any of the memories.
genvar nd_j;
generate
if ((N_DATA_LANES > 1) || (FIXED_LATENCY_MODE == 1)) begin : adj_lat_inst
// Determine when max_lat_done is first asserted. This will be used to
// initiate the latency adjustment sequence.
always @(posedge clk) begin
if (rst_clk)
max_lat_done_r <= #TCQ 0;
else
max_lat_done_r <= #TCQ max_lat_done;
end
assign start_lat_adj = max_lat_done && !max_lat_done_r;
for (nd_j=0; nd_j < N_DATA_LANES; nd_j=nd_j+1) begin : inc_lat_inst
// Adjust the latency as required for each memory. For
// FIXED_LATENCY_MODE=0, the latency for each memory must be adjusted
// to the maximum latency previously found within the system. For
// FIXED_LATENCY_MODE=1, the latency for every memory will be adjusted
// to the latency determined by the PHY_LATENCY parameter. Latency
// adjustments are made by asserting the inc_latency signal
// independently for each memory. For every cycle inc_latency is
// asserted, the latency will be increased by one.
always @(posedge clk) begin
if (rst_clk) begin
inc_latency[nd_j] <= #TCQ 0;
mem_lat_adj[nd_j] <= #TCQ 0;
lat_adj_done[nd_j] <= #TCQ 0;
end else if (start_lat_adj) begin
if (FIXED_LATENCY_MODE == 0) begin
inc_latency[nd_j] <= #TCQ 0;
mem_lat_adj[nd_j] <= #TCQ max_latency - mem_latency[nd_j];
lat_adj_done[nd_j] <= #TCQ 0;
end else begin
inc_latency[nd_j] <= #TCQ 0;
mem_lat_adj[nd_j] <= #TCQ PHY_LATENCY - mem_latency[nd_j];
lat_adj_done[nd_j] <= #TCQ 0;
end
end else if (max_lat_done_r) begin
if (mem_lat_adj[nd_j] == 0) begin
inc_latency[nd_j] <= #TCQ 0;
mem_lat_adj[nd_j] <= #TCQ 0;
lat_adj_done[nd_j] <= #TCQ 1;
end else begin
inc_latency[nd_j] <= #TCQ |mem_lat_adj[nd_j];
mem_lat_adj[nd_j] <= #TCQ mem_lat_adj[nd_j] - 1'b1;
lat_adj_done[nd_j] <= #TCQ 0;
end
end
end
end
// Issue an error if in FIXED_LATENCY_MODE=1 and the target PHY_LATENCY
// is less than what the system can safely provide.
always @(posedge clk) begin
if (rst_clk)
error_adj_latency <= #TCQ 0;
else if ((FIXED_LATENCY_MODE == 1) && start_lat_adj) begin
if (PHY_LATENCY < max_latency)
error_adj_latency <= #TCQ 1;
end
end
// Signal that stage 2 calibration is complete once the latencies have
// been adjusted.
always @(posedge clk) begin
if (rst_clk)
cal_stage2_done <= #TCQ 0;
else if (error_adj_latency)
cal_stage2_done <= #TCQ 0;
else
cal_stage2_done <= #TCQ |lat_adj_done;
end
end else begin : adj_lat_inst_dev1
// Since no latency adjustments are required for single memory interface
// with FIXED_LATENCY_MODE=0, calibration can be signaled as soon as
// max_lat_done is asserted
always @(posedge clk) begin
if (rst_clk)
cal_stage2_done <= #TCQ 0;
else
cal_stage2_done <= #TCQ max_lat_done;
end
// Tie off error_adj_latency signal
always @(posedge clk) begin
error_adj_latency <= #TCQ 0;
end
end
endgenerate
// The final step is to indicate to the vld_gen logic how much to delay
// incoming rd_cmd's by in order to align them with the read data. This
// latency to the vld_gen logic is set to either the max_latency - 3
// FIXED_LATENCY_MODE=0) or PHY_LATENCY - 3 (FIXED_LATENCY_MODE=1). The
// minus 3 is to account for the extra cycles out of the vld_gen logic.
always @(posedge clk) begin
if (rst_clk)
valid_latency <= #TCQ 0;
else if (cal_stage2_done)
valid_latency <= #TCQ valid_latency;
else if (FIXED_LATENCY_MODE == 0)
valid_latency <= #TCQ max_latency - 2'h3;
else
valid_latency <= #TCQ PHY_LATENCY - 2'h3;
end
//Register phase valid results and output for use by write calibration
always @(posedge clk) begin
if (rst_clk)
phase_valid <= #TCQ 'b0;
else
phase_valid <= #TCQ phase_vld_check;
end
// Indicate overall calibration is complete once stage 2 calibration is done
// and each phase detector has completed calibration.
always @(posedge clk) begin
if (rst_clk)
cal_done <= #TCQ 0;
else
cal_done <= #TCQ cal_stage2_done;
end
// Assign debug signals
assign dbg_stage2_cal[0] = en_mem_latency;
assign dbg_stage2_cal[5:1] = mem_latency[dbg_byte_sel]; // latency value for each byte lane
assign dbg_stage2_cal[6] = rd_cmd;
assign dbg_stage2_cal[7] = latency_measured[0];
assign dbg_stage2_cal[8] = bl4_rd_cmd_int;
assign dbg_stage2_cal[9] = bl4_rd_cmd_int_r;
assign dbg_stage2_cal[10] = edge_adv_cal_start;
assign dbg_stage2_cal[11] = rd0_vld[dbg_byte_sel];
assign dbg_stage2_cal[12] = fd0_vld[dbg_byte_sel];
assign dbg_stage2_cal[13] = rd1_vld[dbg_byte_sel];
assign dbg_stage2_cal[14] = fd1_vld[dbg_byte_sel];
assign dbg_stage2_cal[15] = phase_vld[dbg_byte_sel];
assign dbg_stage2_cal[16] = rd0_bslip_vld[dbg_byte_sel];
assign dbg_stage2_cal[17] = fd0_bslip_vld[dbg_byte_sel];
assign dbg_stage2_cal[18] = rd1_bslip_vld[dbg_byte_sel];
assign dbg_stage2_cal[19] = fd1_bslip_vld[dbg_byte_sel];
assign dbg_stage2_cal[20] = phase_bslip_vld[dbg_byte_sel];
assign dbg_stage2_cal[21] = clkdiv_phase_cal_done_4r;
assign dbg_stage2_cal[22] = pi_edge_adv;
assign dbg_stage2_cal[25:23] = byte_cnt[2:0];
assign dbg_stage2_cal[26] = inc_byte_cnt;
assign dbg_stage2_cal[30:27] = pi_edge_adv_wait_cnt[3:0];
assign dbg_stage2_cal[31] = rd2_vld[dbg_byte_sel];
assign dbg_stage2_cal[32] = fd2_vld[dbg_byte_sel];
assign dbg_stage2_cal[33] = rd3_vld[dbg_byte_sel];
assign dbg_stage2_cal[34] = fd3_vld[dbg_byte_sel];
assign dbg_stage2_cal[35] = latency_measured[1];
assign dbg_stage2_cal[36] = (N_DATA_LANES > 2) ? latency_measured[2] : 1'b0;
assign dbg_stage2_cal[37] = (N_DATA_LANES > 2) ? latency_measured[3] : 1'b0;
assign dbg_stage2_cal[38] = error_adj_latency;
assign dbg_stage2_cal[39] = error_max_latency[dbg_byte_sel];
assign dbg_stage2_cal[40] = lat_adj_done[dbg_byte_sel];
assign dbg_stage2_cal[76:41] = {rd0[dbg_byte_sel*BYTE_LANE_WIDTH+:BYTE_LANE_WIDTH], rd1[dbg_byte_sel*BYTE_LANE_WIDTH+:BYTE_LANE_WIDTH], rd2[dbg_byte_sel*BYTE_LANE_WIDTH+:BYTE_LANE_WIDTH], rd3[dbg_byte_sel*BYTE_LANE_WIDTH+:BYTE_LANE_WIDTH]};
assign dbg_stage2_cal[112:77] = {fd0[dbg_byte_sel*BYTE_LANE_WIDTH+:BYTE_LANE_WIDTH], fd1[dbg_byte_sel*BYTE_LANE_WIDTH+:BYTE_LANE_WIDTH], fd2[dbg_byte_sel*BYTE_LANE_WIDTH+:BYTE_LANE_WIDTH], fd3[dbg_byte_sel*BYTE_LANE_WIDTH+:BYTE_LANE_WIDTH]};
assign dbg_stage2_cal[116:113] = inc_latency[dbg_byte_sel];
assign dbg_stage2_cal[127:117] = 'b0;
endmodule
|
// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: bram.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 18.1.0 Build 625 09/12/2018 SJ Lite Edition
// ************************************************************
//Copyright (C) 2018 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel FPGA IP License Agreement, or other applicable license
//agreement, including, without limitation, that your use is for
//the sole purpose of programming logic devices manufactured by
//Intel and sold by Intel or its authorized distributors. Please
//refer to the applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module bram (
address_a,
address_b,
clock,
data_a,
data_b,
wren_a,
wren_b,
q_a,
q_b);
input [4:0] address_a;
input [4:0] address_b;
input clock;
input [7:0] data_a;
input [7:0] data_b;
input wren_a;
input wren_b;
output [7:0] q_a;
output [7:0] q_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri0 wren_a;
tri0 wren_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [7:0] sub_wire0;
wire [7:0] sub_wire1;
wire [7:0] q_a = sub_wire0[7:0];
wire [7:0] q_b = sub_wire1[7:0];
altsyncram altsyncram_component (
.address_a (address_a),
.address_b (address_b),
.clock0 (clock),
.data_a (data_a),
.data_b (data_b),
.wren_a (wren_a),
.wren_b (wren_b),
.q_a (sub_wire0),
.q_b (sub_wire1),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.eccstatus (),
.rden_a (1'b1),
.rden_b (1'b1));
defparam
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.indata_reg_b = "CLOCK0",
altsyncram_component.intended_device_family = "Cyclone IV E",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 32,
altsyncram_component.numwords_b = 32,
altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.outdata_reg_b = "CLOCK0",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_WITH_NBE_READ",
altsyncram_component.read_during_write_mode_port_b = "NEW_DATA_WITH_NBE_READ",
altsyncram_component.widthad_a = 5,
altsyncram_component.widthad_b = 5,
altsyncram_component.width_a = 8,
altsyncram_component.width_b = 8,
altsyncram_component.width_byteena_a = 1,
altsyncram_component.width_byteena_b = 1,
altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "256"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "4"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "4"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: REGrren NUMERIC "0"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "32"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "32"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_WITH_NBE_READ"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_WITH_NBE_READ"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "5"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "5"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: USED_PORT: address_a 0 0 5 0 INPUT NODEFVAL "address_a[4..0]"
// Retrieval info: USED_PORT: address_b 0 0 5 0 INPUT NODEFVAL "address_b[4..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data_a 0 0 8 0 INPUT NODEFVAL "data_a[7..0]"
// Retrieval info: USED_PORT: data_b 0 0 8 0 INPUT NODEFVAL "data_b[7..0]"
// Retrieval info: USED_PORT: q_a 0 0 8 0 OUTPUT NODEFVAL "q_a[7..0]"
// Retrieval info: USED_PORT: q_b 0 0 8 0 OUTPUT NODEFVAL "q_b[7..0]"
// Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a"
// Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b"
// Retrieval info: CONNECT: @address_a 0 0 5 0 address_a 0 0 5 0
// Retrieval info: CONNECT: @address_b 0 0 5 0 address_b 0 0 5 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 8 0 data_a 0 0 8 0
// Retrieval info: CONNECT: @data_b 0 0 8 0 data_b 0 0 8 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
// Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
// Retrieval info: CONNECT: q_a 0 0 8 0 @q_a 0 0 8 0
// Retrieval info: CONNECT: q_b 0 0 8 0 @q_b 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL bram.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL bram.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bram.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bram.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bram_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL bram_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A21BO_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__A21BO_PP_BLACKBOX_V
/**
* a21bo: 2-input AND into first input of 2-input OR,
* 2nd input inverted.
*
* X = ((A1 & A2) | (!B1_N))
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__a21bo (
X ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__A21BO_PP_BLACKBOX_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__OR4B_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HDLL__OR4B_FUNCTIONAL_PP_V
/**
* or4b: 4-input OR, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__or4b (
X ,
A ,
B ,
C ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
not not0 (not0_out , D_N );
or or0 (or0_out_X , not0_out, C, B, A );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__OR4B_FUNCTIONAL_PP_V
|
//-------------------------------------------------------------------
//
// COPYRIGHT (C) 2014, VIPcore Group, Fudan University
//
// THIS FILE MAY NOT BE MODIFIED OR REDISTRIBUTED WITHOUT THE
// EXPRESSED WRITTEN CONSENT OF VIPcore Group
//
// VIPcore : http://soc.fudan.edu.cn/vip
// IP Owner : Yibo FAN
// Contact : [email protected]
//
//-------------------------------------------------------------------
//
// Filename : example.v
// Author : Huang Lei Lei
// Created : 2014-12-08
// Description : example for rtl
//
//-------------------------------------------------------------------
`define COST_WIDTH (`PIXEL_WIDTH+12)
`include "enc_defines.v"
module ime_decision (
// cost_i
cost_NxN_00_i ,
cost_NxN_01_i ,
cost_NxN_02_i ,
cost_NxN_03_i ,
cost_2NxN_0_i ,
cost_2NxN_1_i ,
cost_Nx2N_0_i ,
cost_Nx2N_1_i ,
cost_2Nx2N_i ,
// deci_o
partition_o ,
cost_best_o
);
//*** PARAMETER DECLARATION ****************************************************
//*** INPUT/OUTPUT DECLARATION *************************************************
// cost_i
input [`COST_WIDTH-1 : 0] cost_NxN_00_i ;
input [`COST_WIDTH-1 : 0] cost_NxN_01_i ;
input [`COST_WIDTH-1 : 0] cost_NxN_02_i ;
input [`COST_WIDTH-1 : 0] cost_NxN_03_i ;
input [`COST_WIDTH-1 : 0] cost_2NxN_0_i ;
input [`COST_WIDTH-1 : 0] cost_2NxN_1_i ;
input [`COST_WIDTH-1 : 0] cost_Nx2N_0_i ;
input [`COST_WIDTH-1 : 0] cost_Nx2N_1_i ;
input [`COST_WIDTH-1 : 0] cost_2Nx2N_i ;
// deci_o
output reg [1 : 0] partition_o ; // it's wire
output reg [`COST_WIDTH-1 : 0] cost_best_o ; // it's wire
//*** WIRE & REG DECLARATION ***************************************************
wire [`COST_WIDTH-1 : 0] cost_NxN_w ;
wire [`COST_WIDTH-1 : 0] cost_2NxN_w ;
wire [`COST_WIDTH-1 : 0] cost_Nx2N_w ;
wire [`COST_WIDTH-1 : 0] cost_2Nx2N_w ;
wire is_NxN_bt_Nx2N ;
wire is_2NxN_bt_2Nx2N ;
wire is_former_bt ;
//*** MAIN BODY ****************************************************************
assign cost_NxN_w = cost_NxN_00_i + cost_NxN_01_i + cost_NxN_02_i + cost_NxN_03_i ;
assign cost_Nx2N_w = cost_Nx2N_0_i + cost_Nx2N_1_i ;
assign cost_2NxN_w = cost_2NxN_0_i + cost_2NxN_1_i ;
assign cost_2Nx2N_w = cost_2Nx2N_i ;
assign is_NxN_bt_Nx2N = cost_NxN_w < cost_Nx2N_w ;
assign is_2NxN_bt_2Nx2N = cost_2NxN_w < cost_2Nx2N_w ;
assign is_former_bt = ( is_NxN_bt_Nx2N ? cost_NxN_w : cost_Nx2N_w )
< ( is_2NxN_bt_2Nx2N ? cost_2NxN_w : cost_2Nx2N_w );
always @(*) begin
casex( {is_former_bt, is_NxN_bt_Nx2N ,is_2NxN_bt_2Nx2N} )
3'b0x0 : begin partition_o = 2'b00 ; cost_best_o = cost_2Nx2N_w ; end
3'b0x1 : begin partition_o = 2'b01 ; cost_best_o = cost_2NxN_w ; end
3'b10x : begin partition_o = 2'b10 ; cost_best_o = cost_Nx2N_w ; end
3'b11x : begin partition_o = 2'b11 ; cost_best_o = cost_NxN_w ; end
default : begin partition_o = 2'b00 ; cost_best_o = cost_2Nx2N_w ; end
endcase
end
//*** DEBUG ********************************************************************
endmodule
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2014 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file fifo_rx.v when simulating
// the core, fifo_rx. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module fifo_rx(
clk,
srst,
din,
wr_en,
rd_en,
dout,
full,
empty
);
input clk;
input srst;
input [8 : 0] din;
input wr_en;
input rd_en;
output [8 : 0] dout;
output full;
output empty;
// synthesis translate_off
FIFO_GENERATOR_V9_3 #(
.C_ADD_NGC_CONSTRAINT(0),
.C_APPLICATION_TYPE_AXIS(0),
.C_APPLICATION_TYPE_RACH(0),
.C_APPLICATION_TYPE_RDCH(0),
.C_APPLICATION_TYPE_WACH(0),
.C_APPLICATION_TYPE_WDCH(0),
.C_APPLICATION_TYPE_WRCH(0),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_AXI_DATA_WIDTH(64),
.C_AXI_ID_WIDTH(4),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_TYPE(0),
.C_AXI_WUSER_WIDTH(1),
.C_AXIS_TDATA_WIDTH(64),
.C_AXIS_TDEST_WIDTH(4),
.C_AXIS_TID_WIDTH(8),
.C_AXIS_TKEEP_WIDTH(4),
.C_AXIS_TSTRB_WIDTH(4),
.C_AXIS_TUSER_WIDTH(4),
.C_AXIS_TYPE(0),
.C_COMMON_CLOCK(1),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(4),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH(9),
.C_DIN_WIDTH_AXIS(1),
.C_DIN_WIDTH_RACH(32),
.C_DIN_WIDTH_RDCH(64),
.C_DIN_WIDTH_WACH(32),
.C_DIN_WIDTH_WDCH(64),
.C_DIN_WIDTH_WRCH(2),
.C_DOUT_RST_VAL("0"),
.C_DOUT_WIDTH(9),
.C_ENABLE_RLOCS(0),
.C_ENABLE_RST_SYNC(1),
.C_ERROR_INJECTION_TYPE(0),
.C_ERROR_INJECTION_TYPE_AXIS(0),
.C_ERROR_INJECTION_TYPE_RACH(0),
.C_ERROR_INJECTION_TYPE_RDCH(0),
.C_ERROR_INJECTION_TYPE_WACH(0),
.C_ERROR_INJECTION_TYPE_WDCH(0),
.C_ERROR_INJECTION_TYPE_WRCH(0),
.C_FAMILY("spartan3"),
.C_FULL_FLAGS_RST_VAL(0),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(0),
.C_HAS_AXI_ARUSER(0),
.C_HAS_AXI_AWUSER(0),
.C_HAS_AXI_BUSER(0),
.C_HAS_AXI_RD_CHANNEL(0),
.C_HAS_AXI_RUSER(0),
.C_HAS_AXI_WR_CHANNEL(0),
.C_HAS_AXI_WUSER(0),
.C_HAS_AXIS_TDATA(0),
.C_HAS_AXIS_TDEST(0),
.C_HAS_AXIS_TID(0),
.C_HAS_AXIS_TKEEP(0),
.C_HAS_AXIS_TLAST(0),
.C_HAS_AXIS_TREADY(1),
.C_HAS_AXIS_TSTRB(0),
.C_HAS_AXIS_TUSER(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_DATA_COUNTS_AXIS(0),
.C_HAS_DATA_COUNTS_RACH(0),
.C_HAS_DATA_COUNTS_RDCH(0),
.C_HAS_DATA_COUNTS_WACH(0),
.C_HAS_DATA_COUNTS_WDCH(0),
.C_HAS_DATA_COUNTS_WRCH(0),
.C_HAS_INT_CLK(0),
.C_HAS_MASTER_CE(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_PROG_FLAGS_AXIS(0),
.C_HAS_PROG_FLAGS_RACH(0),
.C_HAS_PROG_FLAGS_RDCH(0),
.C_HAS_PROG_FLAGS_WACH(0),
.C_HAS_PROG_FLAGS_WDCH(0),
.C_HAS_PROG_FLAGS_WRCH(0),
.C_HAS_RD_DATA_COUNT(0),
.C_HAS_RD_RST(0),
.C_HAS_RST(0),
.C_HAS_SLAVE_CE(0),
.C_HAS_SRST(1),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(0),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(0),
.C_IMPLEMENTATION_TYPE_AXIS(1),
.C_IMPLEMENTATION_TYPE_RACH(1),
.C_IMPLEMENTATION_TYPE_RDCH(1),
.C_IMPLEMENTATION_TYPE_WACH(1),
.C_IMPLEMENTATION_TYPE_WDCH(1),
.C_IMPLEMENTATION_TYPE_WRCH(1),
.C_INIT_WR_PNTR_VAL(0),
.C_INTERFACE_TYPE(0),
.C_MEMORY_TYPE(1),
.C_MIF_FILE_NAME("BlankString"),
.C_MSGON_VAL(1),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(1),
.C_PRELOAD_REGS(0),
.C_PRIM_FIFO_TYPE("512x36"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(2),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(3),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_EMPTY_TYPE_AXIS(0),
.C_PROG_EMPTY_TYPE_RACH(0),
.C_PROG_EMPTY_TYPE_RDCH(0),
.C_PROG_EMPTY_TYPE_WACH(0),
.C_PROG_EMPTY_TYPE_WDCH(0),
.C_PROG_EMPTY_TYPE_WRCH(0),
.C_PROG_FULL_THRESH_ASSERT_VAL(14),
.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023),
.C_PROG_FULL_THRESH_NEGATE_VAL(13),
.C_PROG_FULL_TYPE(0),
.C_PROG_FULL_TYPE_AXIS(0),
.C_PROG_FULL_TYPE_RACH(0),
.C_PROG_FULL_TYPE_RDCH(0),
.C_PROG_FULL_TYPE_WACH(0),
.C_PROG_FULL_TYPE_WDCH(0),
.C_PROG_FULL_TYPE_WRCH(0),
.C_RACH_TYPE(0),
.C_RD_DATA_COUNT_WIDTH(4),
.C_RD_DEPTH(16),
.C_RD_FREQ(1),
.C_RD_PNTR_WIDTH(4),
.C_RDCH_TYPE(0),
.C_REG_SLICE_MODE_AXIS(0),
.C_REG_SLICE_MODE_RACH(0),
.C_REG_SLICE_MODE_RDCH(0),
.C_REG_SLICE_MODE_WACH(0),
.C_REG_SLICE_MODE_WDCH(0),
.C_REG_SLICE_MODE_WRCH(0),
.C_SYNCHRONIZER_STAGE(2),
.C_UNDERFLOW_LOW(0),
.C_USE_COMMON_OVERFLOW(0),
.C_USE_COMMON_UNDERFLOW(0),
.C_USE_DEFAULT_SETTINGS(0),
.C_USE_DOUT_RST(1),
.C_USE_ECC(0),
.C_USE_ECC_AXIS(0),
.C_USE_ECC_RACH(0),
.C_USE_ECC_RDCH(0),
.C_USE_ECC_WACH(0),
.C_USE_ECC_WDCH(0),
.C_USE_ECC_WRCH(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(0),
.C_VALID_LOW(0),
.C_WACH_TYPE(0),
.C_WDCH_TYPE(0),
.C_WR_ACK_LOW(0),
.C_WR_DATA_COUNT_WIDTH(4),
.C_WR_DEPTH(16),
.C_WR_DEPTH_AXIS(1024),
.C_WR_DEPTH_RACH(16),
.C_WR_DEPTH_RDCH(1024),
.C_WR_DEPTH_WACH(16),
.C_WR_DEPTH_WDCH(1024),
.C_WR_DEPTH_WRCH(16),
.C_WR_FREQ(1),
.C_WR_PNTR_WIDTH(4),
.C_WR_PNTR_WIDTH_AXIS(10),
.C_WR_PNTR_WIDTH_RACH(4),
.C_WR_PNTR_WIDTH_RDCH(10),
.C_WR_PNTR_WIDTH_WACH(4),
.C_WR_PNTR_WIDTH_WDCH(10),
.C_WR_PNTR_WIDTH_WRCH(4),
.C_WR_RESPONSE_LATENCY(1),
.C_WRCH_TYPE(0)
)
inst (
.CLK(clk),
.SRST(srst),
.DIN(din),
.WR_EN(wr_en),
.RD_EN(rd_en),
.DOUT(dout),
.FULL(full),
.EMPTY(empty),
.BACKUP(),
.BACKUP_MARKER(),
.RST(),
.WR_CLK(),
.WR_RST(),
.RD_CLK(),
.RD_RST(),
.PROG_EMPTY_THRESH(),
.PROG_EMPTY_THRESH_ASSERT(),
.PROG_EMPTY_THRESH_NEGATE(),
.PROG_FULL_THRESH(),
.PROG_FULL_THRESH_ASSERT(),
.PROG_FULL_THRESH_NEGATE(),
.INT_CLK(),
.INJECTDBITERR(),
.INJECTSBITERR(),
.ALMOST_FULL(),
.WR_ACK(),
.OVERFLOW(),
.ALMOST_EMPTY(),
.VALID(),
.UNDERFLOW(),
.DATA_COUNT(),
.RD_DATA_COUNT(),
.WR_DATA_COUNT(),
.PROG_FULL(),
.PROG_EMPTY(),
.SBITERR(),
.DBITERR(),
.M_ACLK(),
.S_ACLK(),
.S_ARESETN(),
.M_ACLK_EN(),
.S_ACLK_EN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWLOCK(),
.S_AXI_AWCACHE(),
.S_AXI_AWPROT(),
.S_AXI_AWQOS(),
.S_AXI_AWREGION(),
.S_AXI_AWUSER(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WID(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WUSER(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BUSER(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.M_AXI_AWID(),
.M_AXI_AWADDR(),
.M_AXI_AWLEN(),
.M_AXI_AWSIZE(),
.M_AXI_AWBURST(),
.M_AXI_AWLOCK(),
.M_AXI_AWCACHE(),
.M_AXI_AWPROT(),
.M_AXI_AWQOS(),
.M_AXI_AWREGION(),
.M_AXI_AWUSER(),
.M_AXI_AWVALID(),
.M_AXI_AWREADY(),
.M_AXI_WID(),
.M_AXI_WDATA(),
.M_AXI_WSTRB(),
.M_AXI_WLAST(),
.M_AXI_WUSER(),
.M_AXI_WVALID(),
.M_AXI_WREADY(),
.M_AXI_BID(),
.M_AXI_BRESP(),
.M_AXI_BUSER(),
.M_AXI_BVALID(),
.M_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARLOCK(),
.S_AXI_ARCACHE(),
.S_AXI_ARPROT(),
.S_AXI_ARQOS(),
.S_AXI_ARREGION(),
.S_AXI_ARUSER(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RUSER(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.M_AXI_ARID(),
.M_AXI_ARADDR(),
.M_AXI_ARLEN(),
.M_AXI_ARSIZE(),
.M_AXI_ARBURST(),
.M_AXI_ARLOCK(),
.M_AXI_ARCACHE(),
.M_AXI_ARPROT(),
.M_AXI_ARQOS(),
.M_AXI_ARREGION(),
.M_AXI_ARUSER(),
.M_AXI_ARVALID(),
.M_AXI_ARREADY(),
.M_AXI_RID(),
.M_AXI_RDATA(),
.M_AXI_RRESP(),
.M_AXI_RLAST(),
.M_AXI_RUSER(),
.M_AXI_RVALID(),
.M_AXI_RREADY(),
.S_AXIS_TVALID(),
.S_AXIS_TREADY(),
.S_AXIS_TDATA(),
.S_AXIS_TSTRB(),
.S_AXIS_TKEEP(),
.S_AXIS_TLAST(),
.S_AXIS_TID(),
.S_AXIS_TDEST(),
.S_AXIS_TUSER(),
.M_AXIS_TVALID(),
.M_AXIS_TREADY(),
.M_AXIS_TDATA(),
.M_AXIS_TSTRB(),
.M_AXIS_TKEEP(),
.M_AXIS_TLAST(),
.M_AXIS_TID(),
.M_AXIS_TDEST(),
.M_AXIS_TUSER(),
.AXI_AW_INJECTSBITERR(),
.AXI_AW_INJECTDBITERR(),
.AXI_AW_PROG_FULL_THRESH(),
.AXI_AW_PROG_EMPTY_THRESH(),
.AXI_AW_DATA_COUNT(),
.AXI_AW_WR_DATA_COUNT(),
.AXI_AW_RD_DATA_COUNT(),
.AXI_AW_SBITERR(),
.AXI_AW_DBITERR(),
.AXI_AW_OVERFLOW(),
.AXI_AW_UNDERFLOW(),
.AXI_AW_PROG_FULL(),
.AXI_AW_PROG_EMPTY(),
.AXI_W_INJECTSBITERR(),
.AXI_W_INJECTDBITERR(),
.AXI_W_PROG_FULL_THRESH(),
.AXI_W_PROG_EMPTY_THRESH(),
.AXI_W_DATA_COUNT(),
.AXI_W_WR_DATA_COUNT(),
.AXI_W_RD_DATA_COUNT(),
.AXI_W_SBITERR(),
.AXI_W_DBITERR(),
.AXI_W_OVERFLOW(),
.AXI_W_UNDERFLOW(),
.AXI_B_INJECTSBITERR(),
.AXI_W_PROG_FULL(),
.AXI_W_PROG_EMPTY(),
.AXI_B_INJECTDBITERR(),
.AXI_B_PROG_FULL_THRESH(),
.AXI_B_PROG_EMPTY_THRESH(),
.AXI_B_DATA_COUNT(),
.AXI_B_WR_DATA_COUNT(),
.AXI_B_RD_DATA_COUNT(),
.AXI_B_SBITERR(),
.AXI_B_DBITERR(),
.AXI_B_OVERFLOW(),
.AXI_B_UNDERFLOW(),
.AXI_AR_INJECTSBITERR(),
.AXI_B_PROG_FULL(),
.AXI_B_PROG_EMPTY(),
.AXI_AR_INJECTDBITERR(),
.AXI_AR_PROG_FULL_THRESH(),
.AXI_AR_PROG_EMPTY_THRESH(),
.AXI_AR_DATA_COUNT(),
.AXI_AR_WR_DATA_COUNT(),
.AXI_AR_RD_DATA_COUNT(),
.AXI_AR_SBITERR(),
.AXI_AR_DBITERR(),
.AXI_AR_OVERFLOW(),
.AXI_AR_UNDERFLOW(),
.AXI_AR_PROG_FULL(),
.AXI_AR_PROG_EMPTY(),
.AXI_R_INJECTSBITERR(),
.AXI_R_INJECTDBITERR(),
.AXI_R_PROG_FULL_THRESH(),
.AXI_R_PROG_EMPTY_THRESH(),
.AXI_R_DATA_COUNT(),
.AXI_R_WR_DATA_COUNT(),
.AXI_R_RD_DATA_COUNT(),
.AXI_R_SBITERR(),
.AXI_R_DBITERR(),
.AXI_R_OVERFLOW(),
.AXI_R_UNDERFLOW(),
.AXIS_INJECTSBITERR(),
.AXI_R_PROG_FULL(),
.AXI_R_PROG_EMPTY(),
.AXIS_INJECTDBITERR(),
.AXIS_PROG_FULL_THRESH(),
.AXIS_PROG_EMPTY_THRESH(),
.AXIS_DATA_COUNT(),
.AXIS_WR_DATA_COUNT(),
.AXIS_RD_DATA_COUNT(),
.AXIS_SBITERR(),
.AXIS_DBITERR(),
.AXIS_OVERFLOW(),
.AXIS_UNDERFLOW(),
.AXIS_PROG_FULL(),
.AXIS_PROG_EMPTY()
);
// synthesis translate_on
endmodule
|
// file: clk_divider_exdes.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// Clocking wizard example design
//----------------------------------------------------------------------------
// This example design instantiates the created clocking network, where each
// output clock drives a counter. The high bit of each counter is ported.
//----------------------------------------------------------------------------
`timescale 1ps/1ps
module clk_divider_exdes
#(
parameter TCQ = 100
)
(// Clock in ports
input CLK_IN1,
// Reset that only drives logic in example design
input COUNTER_RESET,
output [1:1] CLK_OUT,
// High bits of counters driven by clocks
output COUNT,
// Status and control signals
input RESET,
output LOCKED
);
// Parameters for the counters
//-------------------------------
// Counter width
localparam C_W = 16;
// When the clock goes out of lock, reset the counters
wire reset_int = !LOCKED || RESET || COUNTER_RESET;
reg rst_sync;
reg rst_sync_int;
reg rst_sync_int1;
reg rst_sync_int2;
// Declare the clocks and counter
wire clk_int;
wire clk_n;
wire clk;
reg [C_W-1:0] counter;
// Instantiation of the clocking network
//--------------------------------------
clk_divider clknetwork
(// Clock in ports
.CLK_IN1 (CLK_IN1),
// Clock out ports
.CLK_OUT1 (clk_int),
// Status and control signals
.RESET (RESET),
.LOCKED (LOCKED));
assign clk_n = ~clk;
ODDR2 clkout_oddr
(.Q (CLK_OUT[1]),
.C0 (clk),
.C1 (clk_n),
.CE (1'b1),
.D0 (1'b1),
.D1 (1'b0),
.R (1'b0),
.S (1'b0));
// Connect the output clocks to the design
//-----------------------------------------
assign clk = clk_int;
// Reset synchronizer
//-----------------------------------
always @(posedge reset_int or posedge clk) begin
if (reset_int) begin
rst_sync <= 1'b1;
rst_sync_int <= 1'b1;
rst_sync_int1 <= 1'b1;
rst_sync_int2 <= 1'b1;
end
else begin
rst_sync <= 1'b0;
rst_sync_int <= rst_sync;
rst_sync_int1 <= rst_sync_int;
rst_sync_int2 <= rst_sync_int1;
end
end
// Output clock sampling
//-----------------------------------
always @(posedge clk or posedge rst_sync_int2) begin
if (rst_sync_int2) begin
counter <= #TCQ { C_W { 1'b 0 } };
end else begin
counter <= #TCQ counter + 1'b 1;
end
end
// alias the high bit to the output
assign COUNT = counter[C_W-1];
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 26.09.2017 09:56:51
// Design Name:
// Module Name: ALU_tb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module alu32_tb();
reg [31:0] data1;
reg [31:0] data2;
reg [2:0] ctrl;
reg clk;
wire oCarry;
wire oZero;
wire [31:0]out;
alu32 uut(
.data1(data1),
.data2(data2),
.ctrl(ctrl),
.clk(clk),
.oCarry(oCarry),
.oZero(oZero),
.out(out)
);
always begin
#50 clk = 1'b1;
#50 clk = 1'b0;
end
initial begin
data1 = 32'b11111111_11111111_11111111_11111111;
data2 = 32'b11111111_11111111_11111111_11111111;
ctrl = 3'b000;//suma
#100;
data1 = 32'b11111111_11111111_11111111_11111111;
data2 = 32'b00000000_00000000_00000000_00000001;
ctrl = 3'b000;//suma
#100;//200
data1 = 32'b11111111_11111111_11111111_11111111;
data2 = 32'b11111111_11111111_11111111_11111111;
ctrl = 3'b001;//resta
#100; //300
data1 = 32'b11111111_11111111_11111111_11111111;
data2 = 32'b00000000_00000000_00000000_00000001;
ctrl = 3'b001;//resta
#100;//400
data1 = 32'b00000000_00000000_00000000_00000000;
data2 = 32'b00000000_00000000_00000000_00000000;
ctrl = 3'b001;//resta
#100; //500
data1 = 32'b11111111_11111111_11111111_11111111;
data2 = 32'b11111111_11111111_11111111_11111111;
ctrl = 3'b010;//and
#100; //600
data1 = 32'b11111111_11111111_11111111_11111111;
data2 = 32'b00000000_00001000_00000000_00000000;
ctrl = 3'b010;//and
#100;//700
data1 = 32'b11111111_11111111_11111111_11111111;
data2 = 32'b11111111_11111111_11111111_11111111;
ctrl = 3'b011;//xor
#100; //800
data1 = 32'b11111111_11111111_11111111_11111111;
data2 = 32'b00000000_00000000_00000000_00000000;
ctrl = 3'b011;//xor
#100; //900
data1 = 32'b11111111_11111111_11111111_11111111;
data2 = 32'b11111111_11111111_11111111_11111111;
ctrl = 3'b100;//or
#100; //1000
data1 = 32'b11111111_11111111_11111111_11111110;
data2 = 32'b00000000_00000000_00000000_00000000;
ctrl = 3'b100;//or
#100; //1100
end
endmodule
|
// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\Select_AB.v
// Created: 2014-09-08 14:12:09
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: Select_AB
// Source Path: controllerPeripheralHdlAdi/Encoder_Peripheral_Hardware_Specification/Select AB
// Hierarchy Level: 2
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module Select_AB
(
in_select,
in1,
in2,
A,
B
);
input in_select;
input in1;
input in2;
output A;
output B;
wire Switch_out1;
wire Switch1_out1;
// <S8>/Switch
assign Switch_out1 = (in_select == 1'b0 ? in2 :
in1);
assign A = Switch_out1;
// <S8>/Switch1
assign Switch1_out1 = (in_select == 1'b0 ? in1 :
in2);
assign B = Switch1_out1;
endmodule // Select_AB
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SDFXBP_FUNCTIONAL_V
`define SKY130_FD_SC_MS__SDFXBP_FUNCTIONAL_V
/**
* sdfxbp: Scan delay flop, non-inverted clock, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_ms__udp_mux_2to1.v"
`include "../../models/udp_dff_p/sky130_fd_sc_ms__udp_dff_p.v"
`celldefine
module sky130_fd_sc_ms__sdfxbp (
Q ,
Q_N,
CLK,
D ,
SCD,
SCE
);
// Module ports
output Q ;
output Q_N;
input CLK;
input D ;
input SCD;
input SCE;
// Local signals
wire buf_Q ;
wire mux_out;
// Delay Name Output Other arguments
sky130_fd_sc_ms__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_ms__udp_dff$P `UNIT_DELAY dff0 (buf_Q , mux_out, CLK );
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__SDFXBP_FUNCTIONAL_V
|
`timescale 1 ns / 1 ns
//////////////////////////////////////////////////////////////////////////////////
// Company: Rehkopf
// Engineer: Rehkopf
//
// Create Date: 01:13:46 05/09/2009
// Design Name:
// Module Name: main
// Project Name:
// Target Devices:
// Tool versions:
// Description: Master Control FSM
//
// Dependencies: address
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
`include "config.vh"
module main(
`ifdef MK2
/* Bus 1: PSRAM, 128Mbit, 16bit, 70ns */
output [22:0] ROM_ADDR,
output ROM_CE,
input MCU_OVR,
/* debug */
output p113_out,
`endif
`ifdef MK3
input SNES_CIC_CLK,
/* Bus 1: 2x PSRAM, 64Mbit, 16bit, 70ns */
output [21:0] ROM_ADDR,
output ROM_1CE,
output ROM_2CE,
output ROM_ZZ,
/* debug */
output PM6_out,
output PN6_out,
input PT5_in,
`endif
/* input clock */
input CLKIN,
/* SNES signals */
input [23:0] SNES_ADDR_IN,
input SNES_READ_IN,
input SNES_WRITE_IN,
input SNES_ROMSEL_IN,
inout [7:0] SNES_DATA,
input SNES_CPU_CLK_IN,
input SNES_REFRESH,
output SNES_IRQ,
output SNES_DATABUS_OE,
output SNES_DATABUS_DIR,
input SNES_SYSCLK,
input [7:0] SNES_PA_IN,
input SNES_PARD_IN,
input SNES_PAWR_IN,
/* SRAM signals */
inout [15:0] ROM_DATA,
output ROM_OE,
output ROM_WE,
output ROM_BHE,
output ROM_BLE,
/* Bus 2: SRAM, 4Mbit, 8bit, 45ns */
inout [7:0] RAM_DATA,
output [18:0] RAM_ADDR,
output RAM_OE,
output RAM_WE,
/* MCU signals */
input SPI_MOSI,
inout SPI_MISO,
input SPI_SS,
input SPI_SCK,
output MCU_RDY,
output DAC_MCLK,
output DAC_LRCK,
output DAC_SDOUT,
/* SD signals */
input [3:0] SD_DAT,
inout SD_CMD,
inout SD_CLK
);
wire CLK2;
wire dspx_dp_enable;
wire [7:0] spi_cmd_data;
wire [7:0] spi_param_data;
wire [7:0] spi_input_data;
wire [31:0] spi_byte_cnt;
wire [2:0] spi_bit_cnt;
wire [23:0] MCU_ADDR;
wire [2:0] MAPPER;
wire [23:0] SAVERAM_MASK;
wire [23:0] ROM_MASK;
wire [7:0] SD_DMA_SRAM_DATA;
wire [1:0] SD_DMA_TGT;
wire [10:0] SD_DMA_PARTIAL_START;
wire [10:0] SD_DMA_PARTIAL_END;
wire [10:0] dac_addr;
wire [2:0] dac_vol_select_out;
wire [8:0] dac_ptr_addr;
//wire [7:0] dac_volume;
wire [7:0] msu_volumerq_out;
wire [7:0] msu_status_out;
wire [31:0] msu_addressrq_out;
wire [15:0] msu_trackrq_out;
wire [13:0] msu_write_addr;
wire [13:0] msu_ptr_addr;
wire [7:0] MSU_SNES_DATA_IN;
wire [7:0] MSU_SNES_DATA_OUT;
wire [5:0] msu_status_reset_bits;
wire [5:0] msu_status_set_bits;
wire [9:0] GSU_PGM_ADDR;
wire [7:0] GSU_PGM_DATA;
wire [7:0] GSU_SNES_DATA_IN;
wire [7:0] GSU_SNES_DATA_OUT;
wire [15:0] featurebits;
wire feat_cmd_unlock = featurebits[5];
wire [23:0] MAPPED_SNES_ADDR;
wire ROM_ADDR0;
//wire [4:0] DBG_srtc_state;
//wire DBG_srtc_we_rising;
//wire [3:0] DBG_srtc_ptr;
//wire [5:0] DBG_srtc_we_sreg;
wire [13:0] DBG_msu_address;
wire DBG_msu_reg_oe_rising;
wire DBG_msu_reg_oe_falling;
wire DBG_msu_reg_we_rising;
wire [2:0] SD_DMA_DBG_clkcnt;
wire [10:0] SD_DMA_DBG_cyclecnt;
wire [15:0] dsp_feat;
wire [8:0] snescmd_addr_mcu;
wire [7:0] snescmd_data_out_mcu;
wire [7:0] snescmd_data_in_mcu;
// config
wire [7:0] reg_group;
wire [7:0] reg_index;
wire [7:0] reg_value;
wire [7:0] reg_invmask;
wire reg_we;
wire [7:0] reg_read;
// unit level configuration output
wire [7:0] gsu_config_data;
reg [7:0] SNES_PARDr = 8'b11111111;
reg [7:0] SNES_PAWRr = 8'b11111111;
reg [7:0] SNES_READr = 8'b11111111;
reg [7:0] SNES_WRITEr = 8'b11111111;
reg [7:0] SNES_CPU_CLKr = 8'b00000000;
reg [7:0] SNES_ROMSELr = 8'b11111111;
reg [23:0] SNES_ADDRr [6:0];
reg [7:0] SNES_PAr [6:0];
reg [7:0] SNES_DATAr [4:0];
reg SNES_DEADr = 1;
reg SNES_reset_strobe = 0;
reg free_strobe = 0;
reg ram_free_strobe = 0;
wire [23:0] SNES_ADDR = (SNES_ADDRr[5] & SNES_ADDRr[4]);
wire [7:0] SNES_PA = (SNES_PAr[5] & SNES_PAr[4]);
wire [7:0] SNES_DATA_IN = (SNES_DATAr[3] & SNES_DATAr[2]);
wire SNES_PARD_start = (SNES_PARDr[6:1] == 6'b111110);
// Sample PAWR data earlier on CPU accesses, later on DMA accesses...
wire SNES_PAWR_start = (SNES_PAWRr[6:1] == (({SNES_ADDR[22], SNES_ADDR[15:0]} == 17'h02100) ? 6'b111000 : 6'b100000));
wire SNES_PAWR_end = (SNES_PAWRr[6:1] == 6'b000001);
wire SNES_RD_start = (SNES_READr[6:1] == 6'b111110);
wire SNES_RD_end = (SNES_READr[6:1] == 6'b000001);
wire SNES_WR_end = (SNES_WRITEr[6:1] == 6'b000001);
wire SNES_cycle_start = (SNES_CPU_CLKr[6:1] == 6'b000001);
wire SNES_cycle_end = (SNES_CPU_CLKr[6:1] == 6'b111110);
wire SNES_WRITE = SNES_WRITEr[2] & SNES_WRITEr[1];
wire SNES_READ = SNES_READr[2] & SNES_READr[1];
wire SNES_CPU_CLK = SNES_CPU_CLKr[2] & SNES_CPU_CLKr[1];
wire SNES_PARD = SNES_PARDr[2] & SNES_PARDr[1];
wire SNES_PAWR = SNES_PAWRr[2] & SNES_PAWRr[1];
wire SNES_ROMSEL = (SNES_ROMSELr[5] & SNES_ROMSELr[4]);
reg [7:0] BUS_DATA;
always @(posedge CLK2) begin
if(~SNES_READ) BUS_DATA <= SNES_DATA;
else if(~SNES_WRITE) BUS_DATA <= SNES_DATA_IN;
end
wire free_slot = SNES_cycle_end | free_strobe;
wire ROM_HIT;
assign DCM_RST=0;
// gsu state
wire GSU_GO;
wire GSU_RON;
wire GSU_RAN;
wire IS_SAVERAM;
reg GSU_RONr; initial GSU_RONr = 0;
reg GSU_RANr; initial GSU_RANr = 0;
always @(posedge CLK2) begin
// synchronize to the SNES cycle to avoid reading partial interrupt vector
//if (SNES_WR_end | SNES_RD_end) begin
if (SNES_cycle_end) begin
GSU_RONr <= GSU_RON & GSU_GO;
GSU_RANr <= GSU_RAN & GSU_GO;
end
end
// Provide full bandwidth if snes is not accessing the bus.
always @(posedge CLK2) begin
if(GSU_RONr) free_strobe <= 1;
else if (SNES_cycle_start) free_strobe <= ~ROM_HIT | IS_SAVERAM;
else free_strobe <= 1'b0;
end
always @(posedge CLK2) begin
SNES_PARDr <= {SNES_PARDr[6:0], SNES_PARD_IN};
SNES_PAWRr <= {SNES_PAWRr[6:0], SNES_PAWR_IN};
SNES_READr <= {SNES_READr[6:0], SNES_READ_IN};
SNES_WRITEr <= {SNES_WRITEr[6:0], SNES_WRITE_IN};
SNES_CPU_CLKr <= {SNES_CPU_CLKr[6:0], SNES_CPU_CLK_IN};
SNES_ROMSELr <= {SNES_ROMSELr[6:0], SNES_ROMSEL_IN};
SNES_ADDRr[6] <= SNES_ADDRr[5];
SNES_ADDRr[5] <= SNES_ADDRr[4];
SNES_ADDRr[4] <= SNES_ADDRr[3];
SNES_ADDRr[3] <= SNES_ADDRr[2];
SNES_ADDRr[2] <= SNES_ADDRr[1];
SNES_ADDRr[1] <= SNES_ADDRr[0];
SNES_ADDRr[0] <= SNES_ADDR_IN;
SNES_PAr[6] <= SNES_PAr[5];
SNES_PAr[5] <= SNES_PAr[4];
SNES_PAr[4] <= SNES_PAr[3];
SNES_PAr[3] <= SNES_PAr[2];
SNES_PAr[2] <= SNES_PAr[1];
SNES_PAr[1] <= SNES_PAr[0];
SNES_PAr[0] <= SNES_PA_IN;
SNES_DATAr[4] <= SNES_DATAr[3];
SNES_DATAr[3] <= SNES_DATAr[2];
SNES_DATAr[2] <= SNES_DATAr[1];
SNES_DATAr[1] <= SNES_DATAr[0];
SNES_DATAr[0] <= SNES_DATA;
end
parameter ST_IDLE = 11'b00000000001;
parameter ST_MCU_RD_ADDR = 11'b00000000010;
parameter ST_MCU_RD_END = 11'b00000000100;
parameter ST_MCU_WR_ADDR = 11'b00000001000;
parameter ST_MCU_WR_END = 11'b00000010000;
parameter ST_GSU_ROM_RD_ADDR = 11'b00000100000;
parameter ST_GSU_ROM_RD_END = 11'b00001000000;
parameter ST_GSU_RAM_RD_ADDR = 11'b00010000000;
parameter ST_GSU_RAM_RD_END = 11'b00100000000;
parameter ST_GSU_RAM_WR_ADDR = 11'b01000000000;
parameter ST_GSU_RAM_WR_END = 11'b10000000000;
`ifdef MK2
parameter SNES_DEAD_TIMEOUT = 17'd85714; // 1ms
`endif
`ifdef MK3
parameter SNES_DEAD_TIMEOUT = 17'd85867; // 1ms
`endif
parameter ROM_CYCLE_LEN = 4'd7; // Increased from 6 due to tight timing on some sd2snes.
reg [10:0] STATE;
initial STATE = ST_IDLE;
//assign SRTC_SNES_DATA_IN = BUS_DATA[3:0];
assign MSU_SNES_DATA_IN = BUS_DATA;
assign GSU_SNES_DATA_IN = BUS_DATA;
sd_dma snes_sd_dma(
.CLK(CLK2),
.SD_DAT(SD_DAT),
.SD_CLK(SD_CLK),
.SD_DMA_EN(SD_DMA_EN),
.SD_DMA_STATUS(SD_DMA_STATUS),
.SD_DMA_SRAM_WE(SD_DMA_SRAM_WE),
.SD_DMA_SRAM_DATA(SD_DMA_SRAM_DATA),
.SD_DMA_NEXTADDR(SD_DMA_NEXTADDR),
.SD_DMA_PARTIAL(SD_DMA_PARTIAL),
.SD_DMA_PARTIAL_START(SD_DMA_PARTIAL_START),
.SD_DMA_PARTIAL_END(SD_DMA_PARTIAL_END),
.SD_DMA_START_MID_BLOCK(SD_DMA_START_MID_BLOCK),
.SD_DMA_END_MID_BLOCK(SD_DMA_END_MID_BLOCK),
.DBG_cyclecnt(SD_DMA_DBG_cyclecnt),
.DBG_clkcnt(SD_DMA_DBG_clkcnt)
);
wire SD_DMA_TO_ROM = (SD_DMA_STATUS && (SD_DMA_TGT == 2'b00));
dac snes_dac(
.clkin(CLK2),
.sysclk(SNES_SYSCLK),
.mclk_out(DAC_MCLK),
.lrck_out(DAC_LRCK),
.sdout(DAC_SDOUT),
.we(SD_DMA_TGT==2'b01 ? SD_DMA_SRAM_WE : 1'b1),
.pgm_address(dac_addr),
.pgm_data(SD_DMA_SRAM_DATA),
.DAC_STATUS(DAC_STATUS),
.volume(msu_volumerq_out),
.vol_latch(msu_volume_latch_out),
.vol_select(dac_vol_select_out),
.palmode(dac_palmode_out),
.play(dac_play),
.reset(dac_reset),
.dac_address_ext(dac_ptr_addr)
);
msu snes_msu (
.clkin(CLK2),
.enable(msu_enable),
.pgm_address(msu_write_addr),
.pgm_data(SD_DMA_SRAM_DATA),
.pgm_we(SD_DMA_TGT==2'b10 ? SD_DMA_SRAM_WE : 1'b1),
.reg_addr(SNES_ADDR[2:0]),
.reg_data_in(MSU_SNES_DATA_IN),
.reg_data_out(MSU_SNES_DATA_OUT),
.reg_oe_falling(SNES_RD_start),
.reg_oe_rising(SNES_RD_end),
.reg_we_rising(SNES_WR_end),
.status_out(msu_status_out),
.volume_out(msu_volumerq_out),
.volume_latch_out(msu_volume_latch_out),
.addr_out(msu_addressrq_out),
.track_out(msu_trackrq_out),
.status_reset_bits(msu_status_reset_bits),
.status_set_bits(msu_status_set_bits),
.status_reset_we(msu_status_reset_we),
.msu_address_ext(msu_ptr_addr),
.msu_address_ext_write(msu_addr_reset),
.DBG_msu_reg_oe_rising(DBG_msu_reg_oe_rising),
.DBG_msu_reg_oe_falling(DBG_msu_reg_oe_falling),
.DBG_msu_reg_we_rising(DBG_msu_reg_we_rising),
.DBG_msu_address(DBG_msu_address),
.DBG_msu_address_ext_write_rising(DBG_msu_address_ext_write_rising)
);
spi snes_spi(
.clk(CLK2),
.MOSI(SPI_MOSI),
.MISO(SPI_MISO),
.SSEL(SPI_SS),
.SCK(SPI_SCK),
.cmd_ready(spi_cmd_ready),
.param_ready(spi_param_ready),
.cmd_data(spi_cmd_data),
.param_data(spi_param_data),
.endmessage(spi_endmessage),
.startmessage(spi_startmessage),
.input_data(spi_input_data),
.byte_cnt(spi_byte_cnt),
.bit_cnt(spi_bit_cnt)
);
// GSU ROM access
reg [15:0] GSU_ROM_DINr;
wire [23:0] GSU_ROM_ADDR;
wire GSU_ROM_WORD;
reg [7:0] GSU_RAM_DINr;
wire [18:0] GSU_RAM_ADDR;
wire [7:0] GSU_RAM_DOUT;
wire GSU_RAM_WORD;
// GSU (superfx)
gsu snes_gsu (
.RST(SNES_reset_strobe),
.CLK(CLK2),
.SAVERAM_MASK(SAVERAM_MASK),
.ROM_MASK(ROM_MASK),
// MMIO interface
.ENABLE(gsu_enable),
.SNES_RD_start(SNES_RD_start),
.SNES_WR_start(SNES_WR_start),
.SNES_WR_end(SNES_WR_end),
.SNES_ADDR(SNES_ADDR[9:0]),
.DATA_IN(GSU_SNES_DATA_IN),
.DATA_ENABLE(gsu_data_enable),
.DATA_OUT(GSU_SNES_DATA_OUT),
// ROM interface
.ROM_BUS_RDY(GSU_ROM_RDY),
.ROM_BUS_RRQ(GSU_ROM_RRQ),
.ROM_BUS_WORD(GSU_ROM_WORD),
.ROM_BUS_ADDR(GSU_ROM_ADDR),
.ROM_BUS_RDDATA(GSU_ROM_DINr),
// RAM interface
.RAM_BUS_RDY(GSU_RAM_RDY),
.RAM_BUS_RRQ(GSU_RAM_RRQ),
.RAM_BUS_WRQ(GSU_RAM_WRQ),
.RAM_BUS_WORD(GSU_RAM_WORD),
.RAM_BUS_ADDR(GSU_RAM_ADDR),
.RAM_BUS_RDDATA(GSU_RAM_DINr),
.RAM_BUS_WRDATA(GSU_RAM_DOUT),
// ACTIVE interface
//.ACTIVE(GSU_ACTIVE),
.IRQ(GSU_IRQ),
.RON(GSU_RON),
.RAN(GSU_RAN),
.GO(GSU_GO),
.SPEED(dsp_feat[0]),
// State debug read interface
.PGM_ADDR(GSU_PGM_ADDR), // [9:0]
.PGM_DATA(GSU_PGM_DATA), // [7:0]
// config
.reg_group_in(reg_group),
.reg_index_in(reg_index),
.reg_value_in(reg_value),
.reg_invmask_in(reg_invmask),
.reg_we_in(reg_we),
.reg_read_in(reg_read),
.config_data_out(gsu_config_data),
.DBG(DBG_GSU)
);
reg [7:0] MCU_DINr;
reg [7:0] MCU_ROM_DINr;
reg [7:0] MCU_RAM_DINr;
wire [7:0] MCU_DOUT;
wire [31:0] cheat_pgm_data;
wire [7:0] cheat_data_out;
wire [2:0] cheat_pgm_idx;
mcu_cmd snes_mcu_cmd(
.clk(CLK2),
.snes_sysclk(SNES_SYSCLK),
.cmd_ready(spi_cmd_ready),
.param_ready(spi_param_ready),
.cmd_data(spi_cmd_data),
.param_data(spi_param_data),
.mcu_mapper(MAPPER),
.mcu_write(MCU_WRITE),
.mcu_data_in(MCU_DINr),
.mcu_data_out(MCU_DOUT),
.spi_byte_cnt(spi_byte_cnt),
.spi_bit_cnt(spi_bit_cnt),
.spi_data_out(spi_input_data),
.addr_out(MCU_ADDR),
.saveram_mask_out(SAVERAM_MASK),
.rom_mask_out(ROM_MASK),
.SD_DMA_EN(SD_DMA_EN),
.SD_DMA_STATUS(SD_DMA_STATUS),
.SD_DMA_NEXTADDR(SD_DMA_NEXTADDR),
.SD_DMA_SRAM_DATA(SD_DMA_SRAM_DATA),
.SD_DMA_SRAM_WE(SD_DMA_SRAM_WE),
.SD_DMA_TGT(SD_DMA_TGT),
.SD_DMA_PARTIAL(SD_DMA_PARTIAL),
.SD_DMA_PARTIAL_START(SD_DMA_PARTIAL_START),
.SD_DMA_PARTIAL_END(SD_DMA_PARTIAL_END),
.SD_DMA_START_MID_BLOCK(SD_DMA_START_MID_BLOCK),
.SD_DMA_END_MID_BLOCK(SD_DMA_END_MID_BLOCK),
.dac_addr_out(dac_addr),
.DAC_STATUS(DAC_STATUS),
.dac_play_out(dac_play),
.dac_reset_out(dac_reset),
.dac_vol_select_out(dac_vol_select_out),
.dac_palmode_out(dac_palmode_out),
.dac_ptr_out(dac_ptr_addr),
.msu_addr_out(msu_write_addr),
.MSU_STATUS(msu_status_out),
.msu_status_reset_out(msu_status_reset_bits),
.msu_status_set_out(msu_status_set_bits),
.msu_status_reset_we(msu_status_reset_we),
.msu_volumerq(msu_volumerq_out),
.msu_addressrq(msu_addressrq_out),
.msu_trackrq(msu_trackrq_out),
.msu_ptr_out(msu_ptr_addr),
.msu_reset_out(msu_addr_reset),
.gsu_addr_out(GSU_PGM_ADDR),
.gsu_data(GSU_PGM_DATA),
// config
.reg_group_out(reg_group),
.reg_index_out(reg_index),
.reg_value_out(reg_value),
.reg_invmask_out(reg_invmask),
.reg_we_out(reg_we),
.reg_read_out(reg_read),
// vv config data in vv
.gsu_config_data_in(gsu_config_data),
// ^^ config data in ^^
.featurebits_out(featurebits),
.mcu_rrq(MCU_RRQ),
.mcu_wrq(MCU_WRQ),
.mcu_rq_rdy(MCU_RDY),
.region_out(mcu_region),
.snescmd_addr_out(snescmd_addr_mcu),
.snescmd_we_out(snescmd_we_mcu),
.snescmd_data_out(snescmd_data_out_mcu),
.snescmd_data_in(snescmd_data_in_mcu),
.cheat_pgm_idx_out(cheat_pgm_idx),
.cheat_pgm_data_out(cheat_pgm_data),
.cheat_pgm_we_out(cheat_pgm_we),
.dsp_feat_out(dsp_feat)
);
address snes_addr(
.CLK(CLK2),
.MAPPER(MAPPER),
.featurebits(featurebits),
.SNES_ADDR(SNES_ADDR), // requested address from SNES
.SNES_PA(SNES_PA),
.SNES_ROMSEL(SNES_ROMSEL),
.ROM_ADDR(MAPPED_SNES_ADDR), // Address to request from SRAM (active low)
.ROM_HIT(ROM_HIT), // want to access RAM0
.IS_SAVERAM(IS_SAVERAM),
.IS_ROM(IS_ROM),
.IS_WRITABLE(IS_WRITABLE),
.SAVERAM_MASK(SAVERAM_MASK),
.ROM_MASK(ROM_MASK),
//MSU-1
.msu_enable(msu_enable),
//GSU
.gsu_enable(gsu_enable),
.r213f_enable(r213f_enable),
.r2100_hit(r2100_hit),
.snescmd_enable(snescmd_enable),
.nmicmd_enable(nmicmd_enable),
.return_vector_enable(return_vector_enable),
.branch1_enable(branch1_enable),
.branch2_enable(branch2_enable)
);
reg pad_latch = 0;
reg [4:0] pad_cnt = 0;
reg snes_ajr = 0;
cheat snes_cheat(
.clk(CLK2),
.SNES_ADDR(SNES_ADDR),
.SNES_PA(SNES_PA),
.SNES_DATA(SNES_DATA),
.SNES_reset_strobe(SNES_reset_strobe),
.SNES_wr_strobe(SNES_WR_end),
.SNES_rd_strobe(SNES_RD_start),
.snescmd_enable(snescmd_enable),
.nmicmd_enable(nmicmd_enable),
.return_vector_enable(return_vector_enable),
.branch1_enable(branch1_enable),
.branch2_enable(branch2_enable),
.pad_latch(pad_latch),
.snes_ajr(snes_ajr),
.SNES_cycle_start(SNES_cycle_start),
.pgm_idx(cheat_pgm_idx),
.pgm_we(cheat_pgm_we),
.pgm_in(cheat_pgm_data),
.gsu_vec_enable(ROM_HIT & ~IS_SAVERAM & GSU_RONr),
.data_out(cheat_data_out),
.cheat_hit(cheat_hit),
.snescmd_unlock(snescmd_unlock)
);
wire [7:0] snescmd_dout;
reg [7:0] r213fr;
reg r213f_forceread;
reg [2:0] r213f_delay;
reg [1:0] r213f_state;
initial r213fr = 8'h55;
initial r213f_forceread = 0;
initial r213f_state = 2'b01;
initial r213f_delay = 3'b000;
reg [7:0] r2100r = 0;
reg r2100_forcewrite = 0;
reg r2100_forcewrite_pre = 0;
wire [3:0] r2100_limit = featurebits[10:7];
wire [3:0] r2100_limited = (SNES_DATA[3:0] > r2100_limit) ? r2100_limit : SNES_DATA[3:0];
wire r2100_patch = featurebits[6];
wire r2100_enable = r2100_hit & (r2100_patch | ~(&r2100_limit));
wire snoop_4200_enable = {SNES_ADDR[22], SNES_ADDR[15:0]} == 17'h04200;
wire r4016_enable = {SNES_ADDR[22], SNES_ADDR[15:0]} == 17'h04016;
always @(posedge CLK2) begin
r2100_forcewrite <= r2100_forcewrite_pre;
end
always @(posedge CLK2) begin
if(SNES_WR_end & snoop_4200_enable) begin
snes_ajr <= SNES_DATA[0];
end
end
always @(posedge CLK2) begin
if(SNES_WR_end & r4016_enable) begin
pad_latch <= 1'b1;
pad_cnt <= 5'h0;
end
if(SNES_RD_start & r4016_enable) begin
pad_cnt <= pad_cnt + 1;
if(&pad_cnt[3:0]) begin
pad_latch <= 1'b0;
end
end
end
assign SNES_DATA = (r213f_enable & ~SNES_PARD & ~r213f_forceread) ? r213fr
:(r2100_enable & ~SNES_PAWR & r2100_forcewrite) ? r2100r
:((~SNES_READ ^ (r213f_forceread & r213f_enable & ~SNES_PARD))
& ~(r2100_enable & ~SNES_PAWR & ~r2100_forcewrite & ~IS_ROM & ~IS_WRITABLE))
? ( msu_enable ? MSU_SNES_DATA_OUT
: gsu_data_enable ? GSU_SNES_DATA_OUT // GSU MMIO read
: (cheat_hit & ~feat_cmd_unlock) ? cheat_data_out
: ((snescmd_unlock | feat_cmd_unlock) & snescmd_enable) ? snescmd_dout
: (ROM_HIT & IS_SAVERAM) ? RAM_DATA
: (ROM_HIT & ~IS_SAVERAM & GSU_RONr) ? (SNES_ADDR[0] ? 8'h01 : {4'h0, (SNES_ADDR[3] & SNES_ADDR[1]), (SNES_ADDR[2] & ~^{SNES_ADDR[3],SNES_ADDR[1]}), 1'b0, SNES_ADDR[0]}) // used for interrupt vectors
: (ROM_ADDR0 ? ROM_DATA[7:0] : ROM_DATA[15:8])
) : 8'bZ;
reg [3:0] ST_MEM_DELAYr;
// MCU
reg MCU_RD_PENDr = 0;
reg MCU_WR_PENDr = 0;
reg [23:0] ROM_ADDRr;
reg RQ_MCU_RDYr;
initial RQ_MCU_RDYr = 1'b1;
wire MCU_WE_HIT = |(STATE & ST_MCU_WR_ADDR);
wire MCU_WR_HIT = |(STATE & (ST_MCU_WR_ADDR | ST_MCU_WR_END));
wire MCU_RD_HIT = |(STATE & (ST_MCU_RD_ADDR | ST_MCU_RD_END));
wire MCU_HIT = MCU_WR_HIT | MCU_RD_HIT;
// GSU ROM
reg GSU_ROM_RD_PENDr; initial GSU_ROM_RD_PENDr = 0;
reg GSU_ROM_WR_PENDr; initial GSU_ROM_WR_PENDr = 0;
reg [23:0] GSU_ROM_ADDRr;
reg [15:0] GSU_ROM_DATAr;
reg GSU_ROM_WORDr;
reg RQ_GSU_ROM_RDYr; initial RQ_GSU_ROM_RDYr = 1;
assign GSU_ROM_RDY = RQ_GSU_ROM_RDYr;
wire GSU_ROM_HIT = |(STATE & ST_GSU_ROM_RD_ADDR);
`ifdef MK2
my_dcm snes_dcm(
.CLKIN(CLKIN),
.CLKFX(CLK2),
.LOCKED(DCM_LOCKED),
.RST(DCM_RST)
);
assign ROM_ADDR = (SD_DMA_TO_ROM) ? MCU_ADDR[23:1] : GSU_ROM_HIT ? GSU_ROM_ADDRr[23:1] : MCU_HIT ? ROM_ADDRr[23:1] : MAPPED_SNES_ADDR[23:1];
assign ROM_ADDR0 = (SD_DMA_TO_ROM) ? MCU_ADDR[0] : GSU_ROM_HIT ? GSU_ROM_ADDRr[0] : MCU_HIT ? ROM_ADDRr[0] : MAPPED_SNES_ADDR[0];
assign ROM_CE = 1'b0;
assign p113_out = 1'b0;
snescmd_buf snescmd (
.clka(CLK2), // input clka
.wea(SNES_WR_end & ((snescmd_unlock | feat_cmd_unlock) & snescmd_enable)), // input [0 : 0] wea
.addra(SNES_ADDR[8:0]), // input [8 : 0] addra
.dina(SNES_DATA), // input [7 : 0] dina
.douta(snescmd_dout), // output [7 : 0] douta
.clkb(CLK2), // input clkb
.web(snescmd_we_mcu), // input [0 : 0] web
.addrb(snescmd_addr_mcu), // input [8 : 0] addrb
.dinb(snescmd_data_out_mcu), // input [7 : 0] dinb
.doutb(snescmd_data_in_mcu) // output [7 : 0] doutb
);
`endif
`ifdef MK3
pll snes_pll(
.inclk0(CLKIN),
.c0(CLK2),
.locked(DCM_LOCKED),
.areset(DCM_RST)
);
wire ROM_ADDR22;
assign ROM_ADDR22 = (SD_DMA_TO_ROM) ? MCU_ADDR[1] : GSU_ROM_HIT ? GSU_ROM_ADDRr[1] : MCU_HIT ? ROM_ADDRr[1] : MAPPED_SNES_ADDR[1];
assign ROM_ADDR = (SD_DMA_TO_ROM) ? MCU_ADDR[23:2] : GSU_ROM_HIT ? GSU_ROM_ADDRr[23:2] : MCU_HIT ? ROM_ADDRr[23:2] : MAPPED_SNES_ADDR[23:2];
assign ROM_ADDR0 = (SD_DMA_TO_ROM) ? MCU_ADDR[0] : GSU_ROM_HIT ? GSU_ROM_ADDRr[0] : MCU_HIT ? ROM_ADDRr[0] : MAPPED_SNES_ADDR[0];
assign ROM_ZZ = 1'b1;
assign ROM_1CE = ROM_ADDR22;
assign ROM_2CE = ~ROM_ADDR22;
snescmd_buf snescmd (
.clock(CLK2), // input clka
.wren_a(SNES_WR_end & ((snescmd_unlock | feat_cmd_unlock) & snescmd_enable)), // input [0 : 0] wea
.address_a(SNES_ADDR[8:0]), // input [8 : 0] addra
.data_a(SNES_DATA), // input [7 : 0] dina
.q_a(snescmd_dout), // output [7 : 0] douta
.wren_b(snescmd_we_mcu), // input [0 : 0] web
.address_b(snescmd_addr_mcu), // input [8 : 0] addrb
.data_b(snescmd_data_out_mcu), // input [7 : 0] dinb
.q_b(snescmd_data_in_mcu) // output [7 : 0] doutb
);
`endif
// OE always active. Overridden by WE when needed.
assign ROM_OE = 1'b0;
reg[17:0] SNES_DEAD_CNTr;
initial SNES_DEAD_CNTr = 0;
reg ROM_ADDR0_r;
always @(posedge CLK2) ROM_ADDR0_r <= ROM_ADDR0;
always @(posedge CLK2) begin
if(MCU_RRQ && MCU_ADDR[23:19] != 5'b11100) begin
MCU_RD_PENDr <= 1'b1;
RQ_MCU_RDYr <= 1'b0;
ROM_ADDRr <= MCU_ADDR;
end else if(MCU_WRQ && MCU_ADDR[23:19] != 5'b11100) begin
MCU_WR_PENDr <= 1'b1;
RQ_MCU_RDYr <= 1'b0;
ROM_ADDRr <= MCU_ADDR;
end else if(STATE & (ST_MCU_RD_END | ST_MCU_WR_END)) begin
MCU_RD_PENDr <= 1'b0;
MCU_WR_PENDr <= 1'b0;
RQ_MCU_RDYr <= 1'b1;
end
end
always @(posedge CLK2) begin
if(GSU_ROM_RRQ) begin
GSU_ROM_RD_PENDr <= 1'b1;
RQ_GSU_ROM_RDYr <= 1'b0;
GSU_ROM_ADDRr <= GSU_ROM_ADDR;
GSU_ROM_WORDr <= GSU_ROM_WORD;
end else if(STATE & ST_GSU_ROM_RD_END) begin
GSU_ROM_RD_PENDr <= 1'b0;
RQ_GSU_ROM_RDYr <= 1'b1;
end
end
always @(posedge CLK2) begin
if(~SNES_CPU_CLKr[1]) SNES_DEAD_CNTr <= SNES_DEAD_CNTr + 1;
else SNES_DEAD_CNTr <= 17'h0;
end
always @(posedge CLK2) begin
SNES_reset_strobe <= 1'b0;
if(SNES_CPU_CLKr[1]) begin
SNES_DEADr <= 1'b0;
if(SNES_DEADr) SNES_reset_strobe <= 1'b1;
end
else if(SNES_DEAD_CNTr > SNES_DEAD_TIMEOUT) SNES_DEADr <= 1'b1;
end
always @(posedge CLK2) begin
if(SNES_DEADr & SNES_CPU_CLKr[1]) STATE <= ST_IDLE; // interrupt+restart an ongoing MCU access when the SNES comes alive
else
case(STATE)
ST_IDLE: begin
STATE <= ST_IDLE;
if(free_slot | SNES_DEADr) begin
if (GSU_ROM_RD_PENDr) begin
STATE <= ST_GSU_ROM_RD_ADDR;
ST_MEM_DELAYr <= ROM_CYCLE_LEN;
end
else if(MCU_RD_PENDr) begin
STATE <= ST_MCU_RD_ADDR;
ST_MEM_DELAYr <= ROM_CYCLE_LEN;
end
else if(MCU_WR_PENDr) begin
STATE <= ST_MCU_WR_ADDR;
ST_MEM_DELAYr <= ROM_CYCLE_LEN;
end
end
end
ST_MCU_RD_ADDR: begin
STATE <= ST_MCU_RD_ADDR;
ST_MEM_DELAYr <= ST_MEM_DELAYr - 1;
if(ST_MEM_DELAYr == 0) STATE <= ST_MCU_RD_END;
MCU_ROM_DINr <= (ROM_ADDR0 ? ROM_DATA[7:0] : ROM_DATA[15:8]);
end
ST_MCU_WR_ADDR: begin
STATE <= ST_MCU_WR_ADDR;
ST_MEM_DELAYr <= ST_MEM_DELAYr - 1;
if(ST_MEM_DELAYr == 0) STATE <= ST_MCU_WR_END;
end
ST_GSU_ROM_RD_ADDR: begin
STATE <= ST_GSU_ROM_RD_ADDR;
ST_MEM_DELAYr <= ST_MEM_DELAYr - 1;
if(ST_MEM_DELAYr == 0) STATE <= ST_GSU_ROM_RD_END;
GSU_ROM_DINr <= (ROM_ADDR0_r ? ROM_DATA[15:0] : {ROM_DATA[7:0],ROM_DATA[15:8]});
end
ST_MCU_RD_END, ST_MCU_WR_END, ST_GSU_ROM_RD_END, ST_GSU_RAM_RD_END, ST_GSU_RAM_WR_END: begin
STATE <= ST_IDLE;
end
endcase
end
always @(posedge CLK2) begin
if(SNES_cycle_end) r213f_forceread <= 1'b1;
else if(SNES_PARD_start & r213f_enable) begin
r213f_delay <= 3'b001;
r213f_state <= 2'b10;
end else if(r213f_state == 2'b10) begin
r213f_delay <= r213f_delay - 1;
if(r213f_delay == 3'b000) begin
r213f_forceread <= 1'b0;
r213f_state <= 2'b01;
r213fr <= {SNES_DATA[7:5], mcu_region, SNES_DATA[3:0]};
end
end
end
/*********************************
* R2100 patching (experimental) *
*********************************/
reg [3:0] r2100_bright = 0;
reg [3:0] r2100_bright_orig = 0;
always @(posedge CLK2) begin
if(SNES_cycle_end) r2100_forcewrite_pre <= 1'b0;
else if(SNES_PAWR_start & r2100_hit) begin
if(r2100_patch & SNES_DATA[7]) begin
// keep previous brightness during forced blanking so there is no DAC step
r2100_forcewrite_pre <= 1'b1;
r2100r <= {SNES_DATA[7], 3'b010, r2100_bright}; // 0xAx
end else if (r2100_patch && SNES_DATA == 8'h00 && r2100r[7]) begin
// extend forced blanking when game goes from blanking to brightness 0 (Star Fox top of screen)
r2100_forcewrite_pre <= 1'b1;
r2100r <= {1'b1, 3'b111, r2100_bright}; // 0xFx
end else if (r2100_patch && SNES_DATA[3:0] < 4'h8 && r2100_bright_orig > 4'hd) begin
// substitute big brightness changes with brightness 0 (so it is visible on 1CHIP)
r2100_forcewrite_pre <= 1'b1;
r2100r <= {SNES_DATA[7], 3'b011, 4'h0}; // 0x3x / 0xBx(!)
end else if (r2100_patch | ~(&r2100_limit)) begin
// save brightness, limit brightness
r2100_bright <= r2100_limited;
r2100_bright_orig <= SNES_DATA[3:0];
if (~(&r2100_limit) && SNES_DATA[3:0] > r2100_limit) begin
r2100_forcewrite_pre <= 1'b1;
r2100r <= {SNES_DATA[7], 3'b100, r2100_limited}; // 0x4x / 0xCx
end
end
end
end
reg MCU_WRITE_1;
always @(posedge CLK2) MCU_WRITE_1<= MCU_WRITE;
// odd addresses xxx1
assign ROM_DATA[7:0] = (ROM_ADDR0)
?(SD_DMA_TO_ROM ? (!MCU_WRITE_1 ? MCU_DOUT : 8'bZ)
: (ROM_HIT & ~IS_SAVERAM & ~SNES_WRITE & ~GSU_RONr) ? SNES_DATA
: MCU_WR_HIT ? MCU_DOUT : 8'bZ
)
:8'bZ;
// even addresses xxx0
assign ROM_DATA[15:8] = (ROM_ADDR0)
? 8'bZ
:(SD_DMA_TO_ROM ? (!MCU_WRITE_1 ? MCU_DOUT : 8'bZ)
: (ROM_HIT & ~IS_SAVERAM & ~SNES_WRITE & ~GSU_RONr) ? SNES_DATA
: MCU_WR_HIT ? MCU_DOUT
: 8'bZ
);
assign ROM_WE = SD_DMA_TO_ROM
?MCU_WRITE
: (ROM_HIT & IS_WRITABLE & ~IS_SAVERAM & SNES_CPU_CLK & ~GSU_RONr) ? SNES_WRITE
: MCU_WE_HIT ? 1'b0
: 1'b1;
assign ROM_BHE = ROM_ADDR0 && !(!SD_DMA_TO_ROM && GSU_ROM_HIT && GSU_ROM_WORDr);
assign ROM_BLE = !ROM_ADDR0 && !(!SD_DMA_TO_ROM && GSU_ROM_HIT && GSU_ROM_WORDr);
//--------------
// RAM Pipeline
//--------------
parameter ST_RAM_IDLE = 9'b000000001;
parameter ST_RAM_MCU_RD_ADDR = 9'b000000010;
parameter ST_RAM_MCU_RD_END = 9'b000000100;
parameter ST_RAM_MCU_WR_ADDR = 9'b000001000;
parameter ST_RAM_MCU_WR_END = 9'b000010000;
parameter ST_RAM_GSU_RD_ADDR = 9'b000100000;
parameter ST_RAM_GSU_RD_END = 9'b001000000;
parameter ST_RAM_GSU_WR_ADDR = 9'b010000000;
parameter ST_RAM_GSU_WR_END = 9'b100000000;
parameter RAM_CYCLE_LEN = 4'd5;
reg [8:0] RAM_STATE; initial RAM_STATE = ST_RAM_IDLE;
reg [3:0] ST_RAM_DELAYr;
wire ram_free_slot = SNES_cycle_end | ram_free_strobe;
// Provide full bandwidth if snes is not accessing the bus.
always @(posedge CLK2) begin
if(GSU_RANr) ram_free_strobe <= 1;
else if (SNES_cycle_start) ram_free_strobe <= ~ROM_HIT | ~IS_SAVERAM;
else ram_free_strobe <= 1'b0;
end
// MCU state machine
reg MCU_RAM_RD_PENDr = 0;
reg MCU_RAM_WR_PENDr = 0;
reg [18:0] RAM_ADDRr;
reg RQ_RAM_MCU_RDYr;
initial RQ_RAM_MCU_RDYr = 1'b1;
wire MCU_RAM_WE_HIT = |(RAM_STATE & ST_RAM_MCU_WR_ADDR);
wire MCU_RAM_WR_HIT = |(RAM_STATE & (ST_RAM_MCU_WR_ADDR | ST_RAM_MCU_WR_END));
wire MCU_RAM_RD_HIT = |(RAM_STATE & (ST_RAM_MCU_RD_ADDR | ST_RAM_MCU_RD_END));
wire MCU_RAM_HIT = MCU_RAM_WR_HIT | MCU_RAM_RD_HIT;
always @(posedge CLK2) begin
if(MCU_RRQ && MCU_ADDR[23:19] == 5'b11100) begin
MCU_RAM_RD_PENDr <= 1'b1;
RQ_RAM_MCU_RDYr <= 1'b0;
RAM_ADDRr <= MCU_ADDR;
end else if(MCU_WRQ && MCU_ADDR[23:19] == 5'b11100) begin
MCU_RAM_WR_PENDr <= 1'b1;
RQ_RAM_MCU_RDYr <= 1'b0;
RAM_ADDRr <= MCU_ADDR;
end else if(RAM_STATE & (ST_RAM_MCU_RD_END | ST_RAM_MCU_WR_END)) begin
MCU_RAM_RD_PENDr <= 1'b0;
MCU_RAM_WR_PENDr <= 1'b0;
RQ_RAM_MCU_RDYr <= 1'b1;
end
end
// GSU RAM
reg GSU_RAM_RD_PENDr; initial GSU_RAM_RD_PENDr = 0;
reg GSU_RAM_WR_PENDr; initial GSU_RAM_WR_PENDr = 0;
reg [18:0] GSU_RAM_ADDRr;
reg [7:0] GSU_RAM_DATAr;
reg GSU_RAM_WORDr;
reg RQ_GSU_RAM_RDYr; initial RQ_GSU_RAM_RDYr = 1;
assign GSU_RAM_RDY = RQ_GSU_RAM_RDYr;
wire GSU_RAM_WE_HIT = |(RAM_STATE & ST_RAM_GSU_WR_ADDR);
wire GSU_RAM_WR_HIT = |(RAM_STATE & (ST_RAM_GSU_WR_ADDR | ST_RAM_GSU_WR_END));
wire GSU_RAM_RD_HIT = |(RAM_STATE & (ST_RAM_GSU_RD_ADDR | ST_RAM_GSU_RD_END));
wire GSU_RAM_HIT = GSU_RAM_WR_HIT | GSU_RAM_RD_HIT;
always @(posedge CLK2) begin
if(GSU_RAM_RRQ) begin
GSU_RAM_RD_PENDr <= 1'b1;
RQ_GSU_RAM_RDYr <= 1'b0;
GSU_RAM_ADDRr <= GSU_RAM_ADDR;
GSU_RAM_WORDr <= GSU_RAM_WORD;
end else if(GSU_RAM_WRQ) begin
GSU_RAM_WR_PENDr <= 1'b1;
RQ_GSU_RAM_RDYr <= 1'b0;
GSU_RAM_ADDRr <= GSU_RAM_ADDR;
GSU_RAM_WORDr <= GSU_RAM_WORD;
GSU_RAM_DATAr <= GSU_RAM_DOUT;
end else if(RAM_STATE & (ST_RAM_GSU_RD_END | ST_RAM_GSU_WR_END)) begin
GSU_RAM_RD_PENDr <= 1'b0;
GSU_RAM_WR_PENDr <= 1'b0;
RQ_GSU_RAM_RDYr <= 1'b1;
end
end
// RAM state machine
always @(posedge CLK2) begin
if(SNES_DEADr & SNES_CPU_CLKr[1]) RAM_STATE <= ST_RAM_IDLE; // interrupt+restart an ongoing MCU access when the SNES comes alive
else
case(RAM_STATE)
ST_RAM_IDLE: begin
if(ram_free_slot | SNES_DEADr) begin
if (GSU_RAM_RD_PENDr) begin
RAM_STATE <= ST_RAM_GSU_RD_ADDR;
ST_RAM_DELAYr <= RAM_CYCLE_LEN;
end
else if (GSU_RAM_WR_PENDr) begin
RAM_STATE <= ST_RAM_GSU_WR_ADDR;
ST_RAM_DELAYr <= RAM_CYCLE_LEN;
end
else if(MCU_RAM_RD_PENDr) begin
RAM_STATE <= ST_RAM_MCU_RD_ADDR;
ST_RAM_DELAYr <= RAM_CYCLE_LEN;
end
else if(MCU_RAM_WR_PENDr) begin
RAM_STATE <= ST_RAM_MCU_WR_ADDR;
ST_RAM_DELAYr <= RAM_CYCLE_LEN;
end
end
end
ST_RAM_MCU_RD_ADDR: begin
ST_RAM_DELAYr <= ST_RAM_DELAYr - 1;
if(ST_RAM_DELAYr == 0) RAM_STATE <= ST_RAM_MCU_RD_END;
MCU_RAM_DINr <= RAM_DATA;
end
ST_RAM_MCU_WR_ADDR: begin
ST_RAM_DELAYr <= ST_RAM_DELAYr - 1;
if(ST_RAM_DELAYr == 0) RAM_STATE <= ST_RAM_MCU_WR_END;
end
ST_RAM_GSU_RD_ADDR: begin
ST_RAM_DELAYr <= ST_RAM_DELAYr - 1;
if(ST_RAM_DELAYr == 0) RAM_STATE <= ST_RAM_GSU_RD_END;
GSU_RAM_DINr <= RAM_DATA;
end
ST_RAM_GSU_WR_ADDR: begin
ST_RAM_DELAYr <= ST_RAM_DELAYr - 1;
if(ST_RAM_DELAYr == 0) RAM_STATE <= ST_RAM_GSU_WR_END;
end
ST_RAM_MCU_RD_END, ST_RAM_MCU_WR_END, ST_RAM_GSU_RD_END, ST_RAM_GSU_WR_END: begin
RAM_STATE <= ST_RAM_IDLE;
end
endcase
end
assign RAM_ADDR = GSU_RAM_HIT ? GSU_RAM_ADDRr[18:0] : MCU_RAM_HIT ? RAM_ADDRr[18:0] : MAPPED_SNES_ADDR[18:0];
assign RAM_DATA[7:0] = ( GSU_RAM_WR_HIT ? GSU_RAM_DATAr[7:0]
: (ROM_HIT & IS_SAVERAM & ~SNES_WRITE & ~GSU_RANr) ? SNES_DATA
: MCU_RAM_WR_HIT ? MCU_DOUT
: 8'bZ
);
assign RAM_WE = ( GSU_RAM_WE_HIT ? 1'b0
: (ROM_HIT & IS_SAVERAM & SNES_CPU_CLK & ~GSU_RANr) ? SNES_WRITE
: MCU_RAM_WE_HIT ? 1'b0
: 1'b1
);
assign RAM_OE = 1'b0;
always @(posedge CLK2) begin
// flop data based on source
if (STATE & ST_MCU_RD_END) begin
MCU_DINr <= MCU_ROM_DINr;
end
else if (RAM_STATE & ST_RAM_MCU_RD_END) begin
MCU_DINr <= MCU_RAM_DINr;
end
end
assign MCU_RDY = RQ_MCU_RDYr & RQ_RAM_MCU_RDYr;
//--------------
assign SNES_DATABUS_OE = msu_enable ? 1'b0 :
gsu_enable & ~(SNES_READ & SNES_WRITE) ? 1'b0 :
snescmd_enable ? (~(snescmd_unlock | feat_cmd_unlock) | (SNES_READ & SNES_WRITE)) :
(r213f_enable & !SNES_PARD) ? 1'b0 :
(r2100_enable & ~SNES_PAWR) ? 1'b0 :
snoop_4200_enable ? SNES_WRITE :
( (IS_ROM & SNES_ROMSEL)
| (!IS_ROM & !IS_SAVERAM & !IS_WRITABLE)
| (SNES_READ & SNES_WRITE)
);
/* data bus direction: 0 = SNES -> FPGA; 1 = FPGA -> SNES
* data bus is always SNES -> FPGA to avoid fighting except when:
* a) the SNES wants to read
* b) we want to force a value on the bus
*/
assign SNES_DATABUS_DIR = (~SNES_READ | (~SNES_PARD & (r213f_enable)))
? (1'b1 ^ (r213f_forceread & r213f_enable & ~SNES_PARD)
^ (r2100_enable & ~SNES_PAWR & ~r2100_forcewrite & ~IS_ROM & ~IS_WRITABLE))
: ((~SNES_PAWR & r2100_enable) ? r2100_forcewrite
: 1'b0);
assign SNES_IRQ = GSU_IRQ;
endmodule
|
// Copyright (c) 2000-2012 Bluespec, Inc.
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision: 29755 $
// $Date: 2012-10-22 13:58:12 +0000 (Mon, 22 Oct 2012) $
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
`ifdef BSV_ASYNC_RESET
`define BSV_ARESET_EDGE_META or `BSV_RESET_EDGE RST
`else
`define BSV_ARESET_EDGE_META
`endif
// N -bit counter with load, set and 2 increment
module Counter(CLK,
RST,
Q_OUT,
DATA_A, ADDA,
DATA_B, ADDB,
DATA_C, SETC,
DATA_F, SETF);
parameter width = 1;
parameter init = 0;
input CLK;
input RST;
input [width - 1 : 0] DATA_A;
input ADDA;
input [width - 1 : 0] DATA_B;
input ADDB;
input [width - 1 : 0] DATA_C;
input SETC;
input [width - 1 : 0] DATA_F;
input SETF;
output [width - 1 : 0] Q_OUT;
reg [width - 1 : 0] q_state ;
assign Q_OUT = q_state ;
always@(posedge CLK `BSV_ARESET_EDGE_META) begin
if (RST == `BSV_RESET_VALUE)
q_state <= `BSV_ASSIGNMENT_DELAY init;
else
begin
if ( SETF )
q_state <= `BSV_ASSIGNMENT_DELAY DATA_F ;
else
q_state <= `BSV_ASSIGNMENT_DELAY (SETC ? DATA_C : q_state ) + (ADDA ? DATA_A : {width {1'b0}}) + (ADDB ? DATA_B : {width {1'b0}} ) ;
end // else: !if(RST == `BSV_RESET_VALUE)
end // always@ (posedge CLK)
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
// synopsys translate_off
initial begin
q_state = {((width + 1)/2){2'b10}} ;
end
// synopsys translate_on
`endif // BSV_NO_INITIAL_BLOCKS
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__MUX2_1_V
`define SKY130_FD_SC_HDLL__MUX2_1_V
/**
* mux2: 2-input multiplexer.
*
* Verilog wrapper for mux2 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__mux2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__mux2_1 (
X ,
A0 ,
A1 ,
S ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A0 ;
input A1 ;
input S ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__mux2 base (
.X(X),
.A0(A0),
.A1(A1),
.S(S),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__mux2_1 (
X ,
A0,
A1,
S
);
output X ;
input A0;
input A1;
input S ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__mux2 base (
.X(X),
.A0(A0),
.A1(A1),
.S(S)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__MUX2_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O31A_1_V
`define SKY130_FD_SC_HD__O31A_1_V
/**
* o31a: 3-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & B1)
*
* Verilog wrapper for o31a with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__o31a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o31a_1 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__o31a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o31a_1 (
X ,
A1,
A2,
A3,
B1
);
output X ;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__o31a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__O31A_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NOR3_2_V
`define SKY130_FD_SC_HS__NOR3_2_V
/**
* nor3: 3-input NOR.
*
* Y = !(A | B | C | !D)
*
* Verilog wrapper for nor3 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__nor3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__nor3_2 (
Y ,
A ,
B ,
C ,
VPWR,
VGND
);
output Y ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
sky130_fd_sc_hs__nor3 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__nor3_2 (
Y,
A,
B,
C
);
output Y;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__nor3 base (
.Y(Y),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__NOR3_2_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:40:46 05/12/2015
// Design Name:
// Module Name: ID_EX
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module ID_EX(
clk,rst,stall,
id_a, id_b, id_td, id_d2, id_Aluc, id_WREG, id_WMEM, id_LW,id_instr,id_pc,
ex_a, ex_b, ex_td, ex_d2, ex_Aluc, ex_WREG, ex_WMEM, ex_LW,ex_instr,ex_pc
);
input clk,rst,stall;
input wire [31:0] id_a,id_b,id_d2,id_instr,id_pc;
input wire [4:0] id_td,id_Aluc;
input wire id_WREG,id_WMEM,id_LW;
output reg [31:0] ex_a,ex_b,ex_d2,ex_instr,ex_pc;
output reg [4:0] ex_td,ex_Aluc;
output reg ex_WREG,ex_WMEM,ex_LW;
always @(posedge clk or posedge rst)
begin
if(rst)
begin
ex_a <= 0;
ex_b <= 0;
ex_d2 <= 0;
ex_td <= 0;
ex_Aluc <= 0;
ex_WREG <= 0;
ex_WMEM <= 0;
ex_LW <= 0;
ex_instr<=32'b100000;
ex_pc<=32'b0;
end
else if(stall)
begin
ex_a <= 0;
ex_b <= 0;
ex_d2 <= 0;
ex_td <= 0;
ex_Aluc <= 0;
ex_WREG <= 0;
ex_WMEM <= 0;
ex_LW <= 0;
ex_instr<=32'b100000;
ex_pc <= id_pc;
end
else
begin
ex_a <= id_a;
ex_b <= id_b;
ex_d2 <= id_d2;
ex_td <= id_td;
ex_Aluc <= id_Aluc;
ex_WREG <= id_WREG;
ex_WMEM <= id_WMEM;
ex_LW <= id_LW;
ex_instr<=id_instr;
ex_pc <= id_pc;
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NOR4B_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__NOR4B_BEHAVIORAL_PP_V
/**
* nor4b: 4-input NOR, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__nor4b (
VPWR,
VGND,
Y ,
A ,
B ,
C ,
D_N
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A ;
input B ;
input C ;
input D_N ;
// Local signals
wire DN not0_out ;
wire nor0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
not not0 (not0_out , D_N );
nor nor0 (nor0_out_Y , A, B, C, not0_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__NOR4B_BEHAVIORAL_PP_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A21BOI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__A21BOI_BEHAVIORAL_PP_V
/**
* a21boi: 2-input AND into first input of 2-input NOR,
* 2nd input inverted.
*
* Y = !((A1 & A2) | (!B1_N))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__a21boi (
Y ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire b ;
wire and0_out ;
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (b , B1_N );
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out_Y , b, and0_out );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__A21BOI_BEHAVIORAL_PP_V
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2015.4
// Copyright (C) 2015 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module sparse_mm_mul_32s_32s_32_3_Mul3S_0(clk, ce, a, b, p);
input clk;
input ce;
input[32 - 1 : 0] a; // synthesis attribute keep a "true"
input[32 - 1 : 0] b; // synthesis attribute keep b "true"
output[32 - 1 : 0] p;
reg signed [32 - 1 : 0] a_reg0;
reg signed [32 - 1 : 0] b_reg0;
wire signed [32 - 1 : 0] tmp_product;
reg signed [32 - 1 : 0] buff0;
assign p = buff0;
assign tmp_product = a_reg0 * b_reg0;
always @ (posedge clk) begin
if (ce) begin
a_reg0 <= a;
b_reg0 <= b;
buff0 <= tmp_product;
end
end
endmodule
`timescale 1 ns / 1 ps
module sparse_mm_mul_32s_32s_32_3(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
sparse_mm_mul_32s_32s_32_3_Mul3S_0 sparse_mm_mul_32s_32s_32_3_Mul3S_0_U(
.clk( clk ),
.ce( ce ),
.a( din0 ),
.b( din1 ),
.p( dout ));
endmodule
|
/*****************************************************************************
* *
* Module: Altera_UP_Audio_In_Deserializer *
* Description: *
* This module read data from the Audio ADC on the Altera DE2 board. *
* *
*****************************************************************************/
module Altera_UP_Audio_In_Deserializer (
// Inputs
clk,
reset,
bit_clk_rising_edge,
bit_clk_falling_edge,
left_right_clk_rising_edge,
left_right_clk_falling_edge,
done_channel_sync,
serial_audio_in_data,
read_left_audio_data_en,
read_right_audio_data_en,
// Bidirectionals
// Outputs
left_audio_fifo_read_space,
right_audio_fifo_read_space,
left_channel_data,
right_channel_data
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter AUDIO_DATA_WIDTH = 32;
parameter BIT_COUNTER_INIT = 5'd31;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input bit_clk_rising_edge;
input bit_clk_falling_edge;
input left_right_clk_rising_edge;
input left_right_clk_falling_edge;
input done_channel_sync;
input serial_audio_in_data;
input read_left_audio_data_en;
input read_right_audio_data_en;
// Bidirectionals
// Outputs
output reg [7:0] left_audio_fifo_read_space;
output reg [7:0] right_audio_fifo_read_space;
output [AUDIO_DATA_WIDTH:1] left_channel_data;
output [AUDIO_DATA_WIDTH:1] right_channel_data;
/*****************************************************************************
* Internal wires and registers Declarations *
*****************************************************************************/
// Internal Wires
wire valid_audio_input;
wire left_channel_fifo_is_empty;
wire right_channel_fifo_is_empty;
wire left_channel_fifo_is_full;
wire right_channel_fifo_is_full;
wire [6:0] left_channel_fifo_used;
wire [6:0] right_channel_fifo_used;
// Internal Registers
reg [AUDIO_DATA_WIDTH:1] data_in_shift_reg;
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential logic *
*****************************************************************************/
always @(posedge clk)
begin
if (reset == 1'b1)
left_audio_fifo_read_space <= 8'h00;
else
begin
left_audio_fifo_read_space[7] <= left_channel_fifo_is_full;
left_audio_fifo_read_space[6:0] <= left_channel_fifo_used;
end
end
always @(posedge clk)
begin
if (reset == 1'b1)
right_audio_fifo_read_space <= 8'h00;
else
begin
right_audio_fifo_read_space[7] <= right_channel_fifo_is_full;
right_audio_fifo_read_space[6:0] <= right_channel_fifo_used;
end
end
always @(posedge clk)
begin
if (reset == 1'b1)
data_in_shift_reg <= {AUDIO_DATA_WIDTH{1'b0}};
else if (bit_clk_rising_edge & valid_audio_input)
data_in_shift_reg <=
{data_in_shift_reg[(AUDIO_DATA_WIDTH - 1):1],
serial_audio_in_data};
end
/*****************************************************************************
* Combinational logic *
*****************************************************************************/
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
Altera_UP_Audio_Bit_Counter Audio_Out_Bit_Counter (
// Inputs
.clk (clk),
.reset (reset),
.bit_clk_rising_edge (bit_clk_rising_edge),
.bit_clk_falling_edge (bit_clk_falling_edge),
.left_right_clk_rising_edge (left_right_clk_rising_edge),
.left_right_clk_falling_edge (left_right_clk_falling_edge),
// Bidirectionals
// Outputs
.counting (valid_audio_input)
);
defparam
Audio_Out_Bit_Counter.BIT_COUNTER_INIT = BIT_COUNTER_INIT;
Altera_UP_SYNC_FIFO Audio_In_Left_Channel_FIFO(
// Inputs
.clk (clk),
.reset (reset),
.write_en (left_right_clk_falling_edge & ~left_channel_fifo_is_full & done_channel_sync),
.write_data (data_in_shift_reg),
.read_en (read_left_audio_data_en & ~left_channel_fifo_is_empty),
// Bidirectionals
// Outputs
.fifo_is_empty (left_channel_fifo_is_empty),
.fifo_is_full (left_channel_fifo_is_full),
.words_used (left_channel_fifo_used),
.read_data (left_channel_data)
);
defparam
Audio_In_Left_Channel_FIFO.DATA_WIDTH = AUDIO_DATA_WIDTH,
Audio_In_Left_Channel_FIFO.DATA_DEPTH = 128,
Audio_In_Left_Channel_FIFO.ADDR_WIDTH = 7;
Altera_UP_SYNC_FIFO Audio_In_Right_Channel_FIFO(
// Inputs
.clk (clk),
.reset (reset),
.write_en (left_right_clk_rising_edge & ~right_channel_fifo_is_full & done_channel_sync),
.write_data (data_in_shift_reg),
.read_en (read_right_audio_data_en & ~right_channel_fifo_is_empty),
// Bidirectionals
// Outputs
.fifo_is_empty (right_channel_fifo_is_empty),
.fifo_is_full (right_channel_fifo_is_full),
.words_used (right_channel_fifo_used),
.read_data (right_channel_data)
);
defparam
Audio_In_Right_Channel_FIFO.DATA_WIDTH = AUDIO_DATA_WIDTH,
Audio_In_Right_Channel_FIFO.DATA_DEPTH = 128,
Audio_In_Right_Channel_FIFO.ADDR_WIDTH = 7;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O41AI_4_V
`define SKY130_FD_SC_HS__O41AI_4_V
/**
* o41ai: 4-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3 | A4) & B1)
*
* Verilog wrapper for o41ai with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__o41ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__o41ai_4 (
Y ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__o41ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__o41ai_4 (
Y ,
A1,
A2,
A3,
A4,
B1
);
output Y ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__o41ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__O41AI_4_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DECAP_4_V
`define SKY130_FD_SC_HVL__DECAP_4_V
/**
* decap: Decoupling capacitance filler.
*
* Verilog wrapper for decap with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__decap.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__decap_4 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__decap base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__decap_4 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__decap base ();
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DECAP_4_V
|
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.3 (lin64) Build 1034051 Fri Oct 3 16:31:15 MDT 2014
// Date : Sun Oct 25 15:46:29 2015
// Host : arthas-ubuntu running 64-bit Ubuntu 14.04.3 LTS
// Command : write_verilog -force -mode synth_stub
// /home/arthas/git/SHD/SHD.srcs/sources_1/ip/pcie3_7x_0/pcie3_7x_0_stub.v
// Design : pcie3_7x_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7vx690tffg1761-2
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "pcie3_7x_0_pcie_3_0_7vx,Vivado 2014.3" *)
module pcie3_7x_0(pci_exp_txn, pci_exp_txp, pci_exp_rxn, pci_exp_rxp, user_clk, user_reset, user_lnk_up, user_app_rdy, s_axis_rq_tlast, s_axis_rq_tdata, s_axis_rq_tuser, s_axis_rq_tkeep, s_axis_rq_tready, s_axis_rq_tvalid, m_axis_rc_tdata, m_axis_rc_tuser, m_axis_rc_tlast, m_axis_rc_tkeep, m_axis_rc_tvalid, m_axis_rc_tready, m_axis_cq_tdata, m_axis_cq_tuser, m_axis_cq_tlast, m_axis_cq_tkeep, m_axis_cq_tvalid, m_axis_cq_tready, s_axis_cc_tdata, s_axis_cc_tuser, s_axis_cc_tlast, s_axis_cc_tkeep, s_axis_cc_tvalid, s_axis_cc_tready, pcie_rq_seq_num, pcie_rq_seq_num_vld, pcie_rq_tag, pcie_rq_tag_vld, pcie_cq_np_req, pcie_cq_np_req_count, cfg_phy_link_down, cfg_phy_link_status, cfg_negotiated_width, cfg_current_speed, cfg_max_payload, cfg_max_read_req, cfg_function_status, cfg_function_power_state, cfg_vf_status, cfg_vf_power_state, cfg_link_power_state, cfg_err_cor_out, cfg_err_nonfatal_out, cfg_err_fatal_out, cfg_ltr_enable, cfg_ltssm_state, cfg_rcb_status, cfg_dpa_substate_change, cfg_obff_enable, cfg_pl_status_change, cfg_tph_requester_enable, cfg_tph_st_mode, cfg_vf_tph_requester_enable, cfg_vf_tph_st_mode, cfg_fc_ph, cfg_fc_pd, cfg_fc_nph, cfg_fc_npd, cfg_fc_cplh, cfg_fc_cpld, cfg_fc_sel, cfg_interrupt_int, cfg_interrupt_pending, cfg_interrupt_sent, cfg_interrupt_msi_enable, cfg_interrupt_msi_vf_enable, cfg_interrupt_msi_mmenable, cfg_interrupt_msi_mask_update, cfg_interrupt_msi_data, cfg_interrupt_msi_select, cfg_interrupt_msi_int, cfg_interrupt_msi_pending_status, cfg_interrupt_msi_sent, cfg_interrupt_msi_fail, cfg_interrupt_msi_attr, cfg_interrupt_msi_tph_present, cfg_interrupt_msi_tph_type, cfg_interrupt_msi_tph_st_tag, cfg_interrupt_msi_function_number, sys_clk, sys_reset)
/* synthesis syn_black_box black_box_pad_pin="pci_exp_txn[3:0],pci_exp_txp[3:0],pci_exp_rxn[3:0],pci_exp_rxp[3:0],user_clk,user_reset,user_lnk_up,user_app_rdy,s_axis_rq_tlast,s_axis_rq_tdata[127:0],s_axis_rq_tuser[59:0],s_axis_rq_tkeep[3:0],s_axis_rq_tready[3:0],s_axis_rq_tvalid,m_axis_rc_tdata[127:0],m_axis_rc_tuser[74:0],m_axis_rc_tlast,m_axis_rc_tkeep[3:0],m_axis_rc_tvalid,m_axis_rc_tready[21:0],m_axis_cq_tdata[127:0],m_axis_cq_tuser[84:0],m_axis_cq_tlast,m_axis_cq_tkeep[3:0],m_axis_cq_tvalid,m_axis_cq_tready[21:0],s_axis_cc_tdata[127:0],s_axis_cc_tuser[32:0],s_axis_cc_tlast,s_axis_cc_tkeep[3:0],s_axis_cc_tvalid,s_axis_cc_tready[3:0],pcie_rq_seq_num[3:0],pcie_rq_seq_num_vld,pcie_rq_tag[5:0],pcie_rq_tag_vld,pcie_cq_np_req,pcie_cq_np_req_count[5:0],cfg_phy_link_down,cfg_phy_link_status[1:0],cfg_negotiated_width[3:0],cfg_current_speed[2:0],cfg_max_payload[2:0],cfg_max_read_req[2:0],cfg_function_status[7:0],cfg_function_power_state[5:0],cfg_vf_status[11:0],cfg_vf_power_state[17:0],cfg_link_power_state[1:0],cfg_err_cor_out,cfg_err_nonfatal_out,cfg_err_fatal_out,cfg_ltr_enable,cfg_ltssm_state[5:0],cfg_rcb_status[1:0],cfg_dpa_substate_change[1:0],cfg_obff_enable[1:0],cfg_pl_status_change,cfg_tph_requester_enable[1:0],cfg_tph_st_mode[5:0],cfg_vf_tph_requester_enable[5:0],cfg_vf_tph_st_mode[17:0],cfg_fc_ph[7:0],cfg_fc_pd[11:0],cfg_fc_nph[7:0],cfg_fc_npd[11:0],cfg_fc_cplh[7:0],cfg_fc_cpld[11:0],cfg_fc_sel[2:0],cfg_interrupt_int[3:0],cfg_interrupt_pending[1:0],cfg_interrupt_sent,cfg_interrupt_msi_enable[1:0],cfg_interrupt_msi_vf_enable[5:0],cfg_interrupt_msi_mmenable[5:0],cfg_interrupt_msi_mask_update,cfg_interrupt_msi_data[31:0],cfg_interrupt_msi_select[3:0],cfg_interrupt_msi_int[31:0],cfg_interrupt_msi_pending_status[63:0],cfg_interrupt_msi_sent,cfg_interrupt_msi_fail,cfg_interrupt_msi_attr[2:0],cfg_interrupt_msi_tph_present,cfg_interrupt_msi_tph_type[1:0],cfg_interrupt_msi_tph_st_tag[8:0],cfg_interrupt_msi_function_number[2:0],sys_clk,sys_reset" */;
output [3:0]pci_exp_txn;
output [3:0]pci_exp_txp;
input [3:0]pci_exp_rxn;
input [3:0]pci_exp_rxp;
output user_clk;
output user_reset;
output user_lnk_up;
output user_app_rdy;
input s_axis_rq_tlast;
input [127:0]s_axis_rq_tdata;
input [59:0]s_axis_rq_tuser;
input [3:0]s_axis_rq_tkeep;
output [3:0]s_axis_rq_tready;
input s_axis_rq_tvalid;
output [127:0]m_axis_rc_tdata;
output [74:0]m_axis_rc_tuser;
output m_axis_rc_tlast;
output [3:0]m_axis_rc_tkeep;
output m_axis_rc_tvalid;
input [21:0]m_axis_rc_tready;
output [127:0]m_axis_cq_tdata;
output [84:0]m_axis_cq_tuser;
output m_axis_cq_tlast;
output [3:0]m_axis_cq_tkeep;
output m_axis_cq_tvalid;
input [21:0]m_axis_cq_tready;
input [127:0]s_axis_cc_tdata;
input [32:0]s_axis_cc_tuser;
input s_axis_cc_tlast;
input [3:0]s_axis_cc_tkeep;
input s_axis_cc_tvalid;
output [3:0]s_axis_cc_tready;
output [3:0]pcie_rq_seq_num;
output pcie_rq_seq_num_vld;
output [5:0]pcie_rq_tag;
output pcie_rq_tag_vld;
input pcie_cq_np_req;
output [5:0]pcie_cq_np_req_count;
output cfg_phy_link_down;
output [1:0]cfg_phy_link_status;
output [3:0]cfg_negotiated_width;
output [2:0]cfg_current_speed;
output [2:0]cfg_max_payload;
output [2:0]cfg_max_read_req;
output [7:0]cfg_function_status;
output [5:0]cfg_function_power_state;
output [11:0]cfg_vf_status;
output [17:0]cfg_vf_power_state;
output [1:0]cfg_link_power_state;
output cfg_err_cor_out;
output cfg_err_nonfatal_out;
output cfg_err_fatal_out;
output cfg_ltr_enable;
output [5:0]cfg_ltssm_state;
output [1:0]cfg_rcb_status;
output [1:0]cfg_dpa_substate_change;
output [1:0]cfg_obff_enable;
output cfg_pl_status_change;
output [1:0]cfg_tph_requester_enable;
output [5:0]cfg_tph_st_mode;
output [5:0]cfg_vf_tph_requester_enable;
output [17:0]cfg_vf_tph_st_mode;
output [7:0]cfg_fc_ph;
output [11:0]cfg_fc_pd;
output [7:0]cfg_fc_nph;
output [11:0]cfg_fc_npd;
output [7:0]cfg_fc_cplh;
output [11:0]cfg_fc_cpld;
input [2:0]cfg_fc_sel;
input [3:0]cfg_interrupt_int;
input [1:0]cfg_interrupt_pending;
output cfg_interrupt_sent;
output [1:0]cfg_interrupt_msi_enable;
output [5:0]cfg_interrupt_msi_vf_enable;
output [5:0]cfg_interrupt_msi_mmenable;
output cfg_interrupt_msi_mask_update;
output [31:0]cfg_interrupt_msi_data;
input [3:0]cfg_interrupt_msi_select;
input [31:0]cfg_interrupt_msi_int;
input [63:0]cfg_interrupt_msi_pending_status;
output cfg_interrupt_msi_sent;
output cfg_interrupt_msi_fail;
input [2:0]cfg_interrupt_msi_attr;
input cfg_interrupt_msi_tph_present;
input [1:0]cfg_interrupt_msi_tph_type;
input [8:0]cfg_interrupt_msi_tph_st_tag;
input [2:0]cfg_interrupt_msi_function_number;
input sys_clk;
input sys_reset;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DLRTP_FUNCTIONAL_V
`define SKY130_FD_SC_HVL__DLRTP_FUNCTIONAL_V
/**
* dlrtp: Delay latch, inverted reset, non-inverted enable,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_pr/sky130_fd_sc_hvl__udp_dlatch_pr.v"
`celldefine
module sky130_fd_sc_hvl__dlrtp (
Q ,
RESET_B,
D ,
GATE
);
// Module ports
output Q ;
input RESET_B;
input D ;
input GATE ;
// Local signals
wire RESET;
wire buf_Q;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_hvl__udp_dlatch$PR `UNIT_DELAY dlatch0 (buf_Q , D, GATE, RESET );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DLRTP_FUNCTIONAL_V
|
//-----------------------------------------------------------------
// FPGA Audio Project SoC IP
// V0.1
// Ultra-Embedded.com
// Copyright 2011 - 2012
//
// Email: [email protected]
//
// License: LGPL
//
// If you would like a version with a different license for use
// in commercial projects please contact the above email address
// for more details.
//-----------------------------------------------------------------
//
// Copyright (C) 2011 - 2012 Ultra-Embedded.com
//
// This source file may be used and distributed without
// restriction provided that this copyright statement is not
// removed from the file and that any derivative work contains
// the original copyright notice and the associated disclaimer.
//
// This source file is free software; you can redistribute it
// and/or modify it under the terms of the GNU Lesser General
// Public License as published by the Free Software Foundation;
// either version 2.1 of the License, or (at your option) any
// later version.
//
// This source is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
// PURPOSE. See the GNU Lesser General Public License for more
// details.
//
// You should have received a copy of the GNU Lesser General
// Public License along with this source; if not, write to the
// Free Software Foundation, Inc., 59 Temple Place, Suite 330,
// Boston, MA 02111-1307 USA
//-----------------------------------------------------------------
//-----------------------------------------------------------------
// Module
//-----------------------------------------------------------------
module asram16
(
clk_i,
data_o,
data_i,
address_i,
be_i,
wren_i
);
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
parameter [31:0] SIZE = 18;
//-----------------------------------------------------------------
// I/O
//-----------------------------------------------------------------
input clk_i;
output [15:0] data_o;
input [15:0] data_i;
input [(SIZE - 1):0] address_i;
input [1:0] be_i;
input wren_i;
//-----------------------------------------------------------------
// Registers
//-----------------------------------------------------------------
reg [7:0] ram_ub [((2<< (SIZE-1)) - 1):0];
reg [7:0] ram_lb [((2<< (SIZE-1)) - 1):0];
wire [15:0] data_o;
//-----------------------------------------------------------------
// Processes
//-----------------------------------------------------------------
always @ (posedge clk_i )
begin
if ((be_i[1] == 1'b0) && (wren_i == 1'b0))
begin
ram_ub[address_i] <= data_i[15:8];
end
if ((be_i[0] == 1'b0) && (wren_i == 1'b0))
begin
ram_lb[address_i] <= data_i[7:0];
end
end
//-------------------------------------------------------------------
// Combinatorial
//-------------------------------------------------------------------
assign data_o = { ram_ub[address_i], ram_lb[address_i] };
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__TAPVGND2_SYMBOL_V
`define SKY130_FD_SC_MS__TAPVGND2_SYMBOL_V
/**
* tapvgnd2: Tap cell with tap to ground, isolated power connection
* 2 rows down.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__tapvgnd2 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__TAPVGND2_SYMBOL_V
|
// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
// Date : Sun Sep 22 02:34:37 2019
// Host : varun-laptop running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zybo_zynq_design_processing_system7_0_0_stub.v
// Design : zybo_zynq_design_processing_system7_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2018.2" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(SDIO0_WP, TTC0_WAVE0_OUT, TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT, USB0_PORT_INDCTL, USB0_VBUS_PWRSELECT, USB0_VBUS_PWRFAULT,
M_AXI_GP0_ARVALID, M_AXI_GP0_AWVALID, M_AXI_GP0_BREADY, M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST, M_AXI_GP0_WVALID, M_AXI_GP0_ARID, M_AXI_GP0_AWID, M_AXI_GP0_WID,
M_AXI_GP0_ARBURST, M_AXI_GP0_ARLOCK, M_AXI_GP0_ARSIZE, M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK, M_AXI_GP0_AWSIZE, M_AXI_GP0_ARPROT, M_AXI_GP0_AWPROT, M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR, M_AXI_GP0_WDATA, M_AXI_GP0_ARCACHE, M_AXI_GP0_ARLEN, M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE, M_AXI_GP0_AWLEN, M_AXI_GP0_AWQOS, M_AXI_GP0_WSTRB, M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY, M_AXI_GP0_AWREADY, M_AXI_GP0_BVALID, M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID, M_AXI_GP0_WREADY, M_AXI_GP0_BID, M_AXI_GP0_RID, M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP, M_AXI_GP0_RDATA, IRQ_F2P, FCLK_CLK0, FCLK_RESET0_N, MIO, DDR_CAS_n, DDR_CKE,
DDR_Clk_n, DDR_Clk, DDR_CS_n, DDR_DRSTB, DDR_ODT, DDR_RAS_n, DDR_WEB, DDR_BankAddr, DDR_Addr,
DDR_VRN, DDR_VRP, DDR_DM, DDR_DQ, DDR_DQS_n, DDR_DQS, PS_SRSTB, PS_CLK, PS_PORB)
/* synthesis syn_black_box black_box_pad_pin="SDIO0_WP,TTC0_WAVE0_OUT,TTC0_WAVE1_OUT,TTC0_WAVE2_OUT,USB0_PORT_INDCTL[1:0],USB0_VBUS_PWRSELECT,USB0_VBUS_PWRFAULT,M_AXI_GP0_ARVALID,M_AXI_GP0_AWVALID,M_AXI_GP0_BREADY,M_AXI_GP0_RREADY,M_AXI_GP0_WLAST,M_AXI_GP0_WVALID,M_AXI_GP0_ARID[11:0],M_AXI_GP0_AWID[11:0],M_AXI_GP0_WID[11:0],M_AXI_GP0_ARBURST[1:0],M_AXI_GP0_ARLOCK[1:0],M_AXI_GP0_ARSIZE[2:0],M_AXI_GP0_AWBURST[1:0],M_AXI_GP0_AWLOCK[1:0],M_AXI_GP0_AWSIZE[2:0],M_AXI_GP0_ARPROT[2:0],M_AXI_GP0_AWPROT[2:0],M_AXI_GP0_ARADDR[31:0],M_AXI_GP0_AWADDR[31:0],M_AXI_GP0_WDATA[31:0],M_AXI_GP0_ARCACHE[3:0],M_AXI_GP0_ARLEN[3:0],M_AXI_GP0_ARQOS[3:0],M_AXI_GP0_AWCACHE[3:0],M_AXI_GP0_AWLEN[3:0],M_AXI_GP0_AWQOS[3:0],M_AXI_GP0_WSTRB[3:0],M_AXI_GP0_ACLK,M_AXI_GP0_ARREADY,M_AXI_GP0_AWREADY,M_AXI_GP0_BVALID,M_AXI_GP0_RLAST,M_AXI_GP0_RVALID,M_AXI_GP0_WREADY,M_AXI_GP0_BID[11:0],M_AXI_GP0_RID[11:0],M_AXI_GP0_BRESP[1:0],M_AXI_GP0_RRESP[1:0],M_AXI_GP0_RDATA[31:0],IRQ_F2P[0:0],FCLK_CLK0,FCLK_RESET0_N,MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB" */;
input SDIO0_WP;
output TTC0_WAVE0_OUT;
output TTC0_WAVE1_OUT;
output TTC0_WAVE2_OUT;
output [1:0]USB0_PORT_INDCTL;
output USB0_VBUS_PWRSELECT;
input USB0_VBUS_PWRFAULT;
output M_AXI_GP0_ARVALID;
output M_AXI_GP0_AWVALID;
output M_AXI_GP0_BREADY;
output M_AXI_GP0_RREADY;
output M_AXI_GP0_WLAST;
output M_AXI_GP0_WVALID;
output [11:0]M_AXI_GP0_ARID;
output [11:0]M_AXI_GP0_AWID;
output [11:0]M_AXI_GP0_WID;
output [1:0]M_AXI_GP0_ARBURST;
output [1:0]M_AXI_GP0_ARLOCK;
output [2:0]M_AXI_GP0_ARSIZE;
output [1:0]M_AXI_GP0_AWBURST;
output [1:0]M_AXI_GP0_AWLOCK;
output [2:0]M_AXI_GP0_AWSIZE;
output [2:0]M_AXI_GP0_ARPROT;
output [2:0]M_AXI_GP0_AWPROT;
output [31:0]M_AXI_GP0_ARADDR;
output [31:0]M_AXI_GP0_AWADDR;
output [31:0]M_AXI_GP0_WDATA;
output [3:0]M_AXI_GP0_ARCACHE;
output [3:0]M_AXI_GP0_ARLEN;
output [3:0]M_AXI_GP0_ARQOS;
output [3:0]M_AXI_GP0_AWCACHE;
output [3:0]M_AXI_GP0_AWLEN;
output [3:0]M_AXI_GP0_AWQOS;
output [3:0]M_AXI_GP0_WSTRB;
input M_AXI_GP0_ACLK;
input M_AXI_GP0_ARREADY;
input M_AXI_GP0_AWREADY;
input M_AXI_GP0_BVALID;
input M_AXI_GP0_RLAST;
input M_AXI_GP0_RVALID;
input M_AXI_GP0_WREADY;
input [11:0]M_AXI_GP0_BID;
input [11:0]M_AXI_GP0_RID;
input [1:0]M_AXI_GP0_BRESP;
input [1:0]M_AXI_GP0_RRESP;
input [31:0]M_AXI_GP0_RDATA;
input [0:0]IRQ_F2P;
output FCLK_CLK0;
output FCLK_RESET0_N;
inout [53:0]MIO;
inout DDR_CAS_n;
inout DDR_CKE;
inout DDR_Clk_n;
inout DDR_Clk;
inout DDR_CS_n;
inout DDR_DRSTB;
inout DDR_ODT;
inout DDR_RAS_n;
inout DDR_WEB;
inout [2:0]DDR_BankAddr;
inout [14:0]DDR_Addr;
inout DDR_VRN;
inout DDR_VRP;
inout [3:0]DDR_DM;
inout [31:0]DDR_DQ;
inout [3:0]DDR_DQS_n;
inout [3:0]DDR_DQS;
inout PS_SRSTB;
inout PS_CLK;
inout PS_PORB;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O21BA_BLACKBOX_V
`define SKY130_FD_SC_LS__O21BA_BLACKBOX_V
/**
* o21ba: 2-input OR into first input of 2-input AND,
* 2nd input inverted.
*
* X = ((A1 | A2) & !B1_N)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__o21ba (
X ,
A1 ,
A2 ,
B1_N
);
output X ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O21BA_BLACKBOX_V
|
// MBT 6/8/2016
//
// bsg_1_to_n_tagged
//
// this is intended to take one input and send it to
// one of several channels according to tag.
//
// see bsg_round_robin_n_to_1 for how the tags are assembled
// and for maintaining consistency between the two modules
//
// assumes a valid->yumi interface for input channel
// and valid/ready for output
//
// we do not include the data portion since it is just replicated
//
`include "bsg_defines.v"
module bsg_1_to_n_tagged #(
parameter `BSG_INV_PARAM(num_out_p)
,parameter tag_width_lp = `BSG_SAFE_CLOG2(num_out_p)
)
(input clk_i
, input reset_i
, input v_i
, input [tag_width_lp-1:0] tag_i
, output yumi_o
, output [num_out_p-1:0] v_o
, input [num_out_p-1:0] ready_i
// to downstream
);
wire unused0 = clk_i;
wire unused1 = reset_i;
if (num_out_p == 1)
begin : one
assign v_o = v_i;
assign yumi_o = ready_i & v_i;
end
else
begin: many
genvar i;
bsg_decode_with_v #(.num_out_p(num_out_p)) bdv
(.i(tag_i)
,.v_i(v_i)
,.o(v_o)
);
assign yumi_o = ready_i[tag_i] & v_i;
end
endmodule // bsg_1_to_n_tagged
`BSG_ABSTRACT_MODULE(bsg_1_to_n_tagged)
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__TAPVPWRVGND_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HDLL__TAPVPWRVGND_BEHAVIORAL_PP_V
/**
* tapvpwrvgnd: Substrate and well tap cell.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__tapvpwrvgnd (
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
input VPWR;
input VGND;
input VPB ;
input VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__TAPVPWRVGND_BEHAVIORAL_PP_V
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// This is the LVDS/DDR interface
`timescale 1ns/100ps
module cf_adc_wr (
// adc interface (clk, data, over-range)
adc_clk_in_p,
adc_clk_in_n,
adc_data_in_p,
adc_data_in_n,
adc_data_or_p,
adc_data_or_n,
// interface outputs
adc_clk,
adc_valid,
adc_data,
adc_or,
adc_pn_oos,
adc_pn_err,
// processor control signals
up_pn_type,
up_dmode,
up_delay_sel,
up_delay_rwn,
up_delay_addr,
up_delay_wdata,
// delay control signals
delay_clk,
delay_ack,
delay_rdata,
delay_locked,
// adc debug and monitor signals (for chipscope)
adc_mon_valid,
adc_mon_data);
// This parameter controls the buffer type based on the target device.
parameter C_CF_BUFTYPE = 0;
// adc interface (clk, data, over-range)
input adc_clk_in_p;
input adc_clk_in_n;
input [ 7:0] adc_data_in_p;
input [ 7:0] adc_data_in_n;
input adc_data_or_p;
input adc_data_or_n;
// interface outputs
output adc_clk;
output adc_valid;
output [63:0] adc_data;
output adc_or;
output adc_pn_oos;
output adc_pn_err;
// processor control signals
input up_pn_type;
input up_dmode;
input up_delay_sel;
input up_delay_rwn;
input [ 3:0] up_delay_addr;
input [ 4:0] up_delay_wdata;
// delay control signals
input delay_clk;
output delay_ack;
output [ 4:0] delay_rdata;
output delay_locked;
// adc debug and monitor signals (for chipscope)
output adc_mon_valid;
output [15:0] adc_mon_data;
reg [ 1:0] adc_count = 'd0;
reg adc_valid = 'd0;
reg [63:0] adc_data = 'd0;
wire [15:0] adc_data_if_s;
assign adc_mon_valid = 1'b1;
assign adc_mon_data = adc_data_if_s;
always @(posedge adc_clk) begin
adc_count <= adc_count + 1'b1;
adc_valid <= adc_count[0] & adc_count[1];
adc_data <= {adc_data_if_s, adc_data[63:16]};
end
// PN sequence monitor
cf_pnmon i_pnmon_a (
.adc_clk (adc_clk),
.adc_data (adc_data_if_s),
.adc_pn_oos (adc_pn_oos),
.adc_pn_err (adc_pn_err),
.up_pn_type (up_pn_type));
// ADC data interface
cf_adc_if #(.C_CF_BUFTYPE (C_CF_BUFTYPE)) i_adc_if (
.adc_clk_in_p (adc_clk_in_p),
.adc_clk_in_n (adc_clk_in_n),
.adc_data_in_p (adc_data_in_p),
.adc_data_in_n (adc_data_in_n),
.adc_data_or_p (adc_data_or_p),
.adc_data_or_n (adc_data_or_n),
.adc_clk (adc_clk),
.adc_data (adc_data_if_s),
.adc_or (adc_or),
.up_dmode (up_dmode),
.up_delay_sel (up_delay_sel),
.up_delay_rwn (up_delay_rwn),
.up_delay_addr (up_delay_addr),
.up_delay_wdata (up_delay_wdata),
.delay_clk (delay_clk),
.delay_ack (delay_ack),
.delay_rdata (delay_rdata),
.delay_locked (delay_locked));
endmodule
// ***************************************************************************
// ***************************************************************************
|
module station_management_tb ();
reg reset;
reg clock;
wire mdc;
reg mdi;
wire mdo;
reg mode;
reg begin_transaction;
reg [4:0] phy_address;
reg [4:0] reg_address;
reg [15:0] data_in;
wire [15:0] data_out;
station_management U_station_management
(
.reset(reset),
.clock(clock),
.mdc(mdc),
.mdi(mdi),
.mdo(mdo),
.mode(mode),
.begin_transaction(begin_transaction),
.phy_address(phy_address),
.reg_address(reg_address),
.data_in(data_in),
.data_out(data_out)
);
integer i;
initial
begin
$dumpfile("test.vcd");
$dumpvars(0,station_management_tb);
end
initial
begin
mdi = 0;
reset = 1;
clock = 1;
mode = 0;
begin_transaction = 0;
phy_address = 5'b00001;
reg_address = 5'b00010;
data_in = 16'hFEDC;
#20 reset = 0;
#20 begin_transaction = 1;
#10 begin_transaction = 0;
#490
for (i=0; i<16; i = i + 1)
begin
reading_bit((i%2)? 1'b1 : 1'b0);
end
mdi = 0;
#50
$finish();
end
always
#5 clock = ~clock;
task reading_bit;
input bit;
begin
mdi = bit;
@(posedge mdc);
end
endtask
task writing_bit;
begin
@(posedge mdc);
end
endtask
endmodule
|
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