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// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_clk_cl_sctag_cmp.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module bw_clk_cl_sctag_cmp (/*AUTOARG*/
// Outputs
dbginit_l, cluster_grst_l, rclk, so,
// Inputs
gclk, cluster_cken, arst_l, grst_l, adbginit_l, gdbginit_l, si,
se
);
input gclk;
input cluster_cken;
input arst_l;
input grst_l;
input adbginit_l;
input gdbginit_l;
output dbginit_l;
output cluster_grst_l;
output rclk;
input si;
input se;
output so;
cluster_header I0 (/*AUTOINST*/
// Outputs
.dbginit_l (dbginit_l),
.cluster_grst_l (cluster_grst_l),
.rclk (rclk),
.so (so),
// Inputs
.gclk (gclk),
.cluster_cken (cluster_cken),
.arst_l (arst_l),
.grst_l (grst_l),
.adbginit_l (adbginit_l),
.gdbginit_l (gdbginit_l),
.si (si),
.se (se));
endmodule
|
//-----------------------------------------------------------------
// RISC-V Top
// V0.6
// Ultra-Embedded.com
// Copyright 2014-2019
//
// [email protected]
//
// License: BSD
//-----------------------------------------------------------------
//
// Copyright (c) 2014, Ultra-Embedded.com
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer
// in the documentation and/or other materials provided with the
// distribution.
// - Neither the name of the author nor the names of its contributors
// may be used to endorse or promote products derived from this
// software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
// SUCH DAMAGE.
//-----------------------------------------------------------------
//-----------------------------------------------------------------
// Generated File
//-----------------------------------------------------------------
module riscv_tcm_top
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
#(
parameter BOOT_VECTOR = 32'h00002000
,parameter CORE_ID = 0
,parameter TCM_MEM_BASE = 0
,parameter MEM_CACHE_ADDR_MIN = 0
,parameter MEM_CACHE_ADDR_MAX = 32'hffffffff
)
//-----------------------------------------------------------------
// Ports
//-----------------------------------------------------------------
(
// Inputs
input clk_i
,input rst_i
,input rst_cpu_i
,input axi_i_awready_i
,input axi_i_wready_i
,input axi_i_bvalid_i
,input [ 1:0] axi_i_bresp_i
,input axi_i_arready_i
,input axi_i_rvalid_i
,input [ 31:0] axi_i_rdata_i
,input [ 1:0] axi_i_rresp_i
,input axi_t_awvalid_i
,input [ 31:0] axi_t_awaddr_i
,input [ 3:0] axi_t_awid_i
,input [ 7:0] axi_t_awlen_i
,input [ 1:0] axi_t_awburst_i
,input axi_t_wvalid_i
,input [ 31:0] axi_t_wdata_i
,input [ 3:0] axi_t_wstrb_i
,input axi_t_wlast_i
,input axi_t_bready_i
,input axi_t_arvalid_i
,input [ 31:0] axi_t_araddr_i
,input [ 3:0] axi_t_arid_i
,input [ 7:0] axi_t_arlen_i
,input [ 1:0] axi_t_arburst_i
,input axi_t_rready_i
,input [ 31:0] intr_i
// Outputs
,output axi_i_awvalid_o
,output [ 31:0] axi_i_awaddr_o
,output axi_i_wvalid_o
,output [ 31:0] axi_i_wdata_o
,output [ 3:0] axi_i_wstrb_o
,output axi_i_bready_o
,output axi_i_arvalid_o
,output [ 31:0] axi_i_araddr_o
,output axi_i_rready_o
,output axi_t_awready_o
,output axi_t_wready_o
,output axi_t_bvalid_o
,output [ 1:0] axi_t_bresp_o
,output [ 3:0] axi_t_bid_o
,output axi_t_arready_o
,output axi_t_rvalid_o
,output [ 31:0] axi_t_rdata_o
,output [ 1:0] axi_t_rresp_o
,output [ 3:0] axi_t_rid_o
,output axi_t_rlast_o
);
wire [ 31:0] ifetch_pc_w;
wire [ 31:0] dport_tcm_data_rd_w;
wire dport_tcm_cacheable_w;
wire dport_flush_w;
wire [ 3:0] dport_tcm_wr_w;
wire ifetch_rd_w;
wire dport_axi_accept_w;
wire dport_cacheable_w;
wire dport_tcm_flush_w;
wire [ 10:0] dport_resp_tag_w;
wire [ 10:0] dport_axi_resp_tag_w;
wire ifetch_accept_w;
wire [ 31:0] dport_data_rd_w;
wire dport_tcm_invalidate_w;
wire dport_ack_w;
wire [ 10:0] dport_axi_req_tag_w;
wire [ 31:0] dport_data_wr_w;
wire dport_invalidate_w;
wire [ 10:0] dport_tcm_req_tag_w;
wire [ 31:0] dport_tcm_addr_w;
wire dport_axi_error_w;
wire dport_tcm_ack_w;
wire dport_tcm_rd_w;
wire [ 10:0] dport_tcm_resp_tag_w;
wire dport_writeback_w;
wire [ 31:0] cpu_id_w = CORE_ID;
wire dport_rd_w;
wire dport_axi_ack_w;
wire dport_axi_rd_w;
wire [ 31:0] dport_axi_data_rd_w;
wire dport_axi_invalidate_w;
wire [ 31:0] boot_vector_w = BOOT_VECTOR;
wire [ 31:0] dport_addr_w;
wire ifetch_error_w;
wire [ 31:0] dport_tcm_data_wr_w;
wire ifetch_flush_w;
wire [ 31:0] dport_axi_addr_w;
wire dport_error_w;
wire dport_tcm_accept_w;
wire ifetch_invalidate_w;
wire dport_axi_writeback_w;
wire [ 3:0] dport_wr_w;
wire ifetch_valid_w;
wire [ 31:0] dport_axi_data_wr_w;
wire [ 10:0] dport_req_tag_w;
wire [ 31:0] ifetch_inst_w;
wire dport_axi_cacheable_w;
wire dport_tcm_writeback_w;
wire [ 3:0] dport_axi_wr_w;
wire dport_axi_flush_w;
wire dport_tcm_error_w;
wire dport_accept_w;
riscv_core
#(
.MEM_CACHE_ADDR_MIN(MEM_CACHE_ADDR_MIN)
,.MEM_CACHE_ADDR_MAX(MEM_CACHE_ADDR_MAX)
)
u_core
(
// Inputs
.clk_i(clk_i)
,.rst_i(rst_cpu_i)
,.mem_d_data_rd_i(dport_data_rd_w)
,.mem_d_accept_i(dport_accept_w)
,.mem_d_ack_i(dport_ack_w)
,.mem_d_error_i(dport_error_w)
,.mem_d_resp_tag_i(dport_resp_tag_w)
,.mem_i_accept_i(ifetch_accept_w)
,.mem_i_valid_i(ifetch_valid_w)
,.mem_i_error_i(ifetch_error_w)
,.mem_i_inst_i(ifetch_inst_w)
,.intr_i(intr_i[0:0])
,.reset_vector_i(boot_vector_w)
,.cpu_id_i(cpu_id_w)
// Outputs
,.mem_d_addr_o(dport_addr_w)
,.mem_d_data_wr_o(dport_data_wr_w)
,.mem_d_rd_o(dport_rd_w)
,.mem_d_wr_o(dport_wr_w)
,.mem_d_cacheable_o(dport_cacheable_w)
,.mem_d_req_tag_o(dport_req_tag_w)
,.mem_d_invalidate_o(dport_invalidate_w)
,.mem_d_writeback_o(dport_writeback_w)
,.mem_d_flush_o(dport_flush_w)
,.mem_i_rd_o(ifetch_rd_w)
,.mem_i_flush_o(ifetch_flush_w)
,.mem_i_invalidate_o(ifetch_invalidate_w)
,.mem_i_pc_o(ifetch_pc_w)
);
dport_mux
#(
.TCM_MEM_BASE(TCM_MEM_BASE)
)
u_dmux
(
// Inputs
.clk_i(clk_i)
,.rst_i(rst_i)
,.mem_addr_i(dport_addr_w)
,.mem_data_wr_i(dport_data_wr_w)
,.mem_rd_i(dport_rd_w)
,.mem_wr_i(dport_wr_w)
,.mem_cacheable_i(dport_cacheable_w)
,.mem_req_tag_i(dport_req_tag_w)
,.mem_invalidate_i(dport_invalidate_w)
,.mem_writeback_i(dport_writeback_w)
,.mem_flush_i(dport_flush_w)
,.mem_tcm_data_rd_i(dport_tcm_data_rd_w)
,.mem_tcm_accept_i(dport_tcm_accept_w)
,.mem_tcm_ack_i(dport_tcm_ack_w)
,.mem_tcm_error_i(dport_tcm_error_w)
,.mem_tcm_resp_tag_i(dport_tcm_resp_tag_w)
,.mem_ext_data_rd_i(dport_axi_data_rd_w)
,.mem_ext_accept_i(dport_axi_accept_w)
,.mem_ext_ack_i(dport_axi_ack_w)
,.mem_ext_error_i(dport_axi_error_w)
,.mem_ext_resp_tag_i(dport_axi_resp_tag_w)
// Outputs
,.mem_data_rd_o(dport_data_rd_w)
,.mem_accept_o(dport_accept_w)
,.mem_ack_o(dport_ack_w)
,.mem_error_o(dport_error_w)
,.mem_resp_tag_o(dport_resp_tag_w)
,.mem_tcm_addr_o(dport_tcm_addr_w)
,.mem_tcm_data_wr_o(dport_tcm_data_wr_w)
,.mem_tcm_rd_o(dport_tcm_rd_w)
,.mem_tcm_wr_o(dport_tcm_wr_w)
,.mem_tcm_cacheable_o(dport_tcm_cacheable_w)
,.mem_tcm_req_tag_o(dport_tcm_req_tag_w)
,.mem_tcm_invalidate_o(dport_tcm_invalidate_w)
,.mem_tcm_writeback_o(dport_tcm_writeback_w)
,.mem_tcm_flush_o(dport_tcm_flush_w)
,.mem_ext_addr_o(dport_axi_addr_w)
,.mem_ext_data_wr_o(dport_axi_data_wr_w)
,.mem_ext_rd_o(dport_axi_rd_w)
,.mem_ext_wr_o(dport_axi_wr_w)
,.mem_ext_cacheable_o(dport_axi_cacheable_w)
,.mem_ext_req_tag_o(dport_axi_req_tag_w)
,.mem_ext_invalidate_o(dport_axi_invalidate_w)
,.mem_ext_writeback_o(dport_axi_writeback_w)
,.mem_ext_flush_o(dport_axi_flush_w)
);
tcm_mem
u_tcm
(
// Inputs
.clk_i(clk_i)
,.rst_i(rst_i)
,.mem_i_rd_i(ifetch_rd_w)
,.mem_i_flush_i(ifetch_flush_w)
,.mem_i_invalidate_i(ifetch_invalidate_w)
,.mem_i_pc_i(ifetch_pc_w)
,.mem_d_addr_i(dport_tcm_addr_w)
,.mem_d_data_wr_i(dport_tcm_data_wr_w)
,.mem_d_rd_i(dport_tcm_rd_w)
,.mem_d_wr_i(dport_tcm_wr_w)
,.mem_d_cacheable_i(dport_tcm_cacheable_w)
,.mem_d_req_tag_i(dport_tcm_req_tag_w)
,.mem_d_invalidate_i(dport_tcm_invalidate_w)
,.mem_d_writeback_i(dport_tcm_writeback_w)
,.mem_d_flush_i(dport_tcm_flush_w)
,.axi_awvalid_i(axi_t_awvalid_i)
,.axi_awaddr_i(axi_t_awaddr_i)
,.axi_awid_i(axi_t_awid_i)
,.axi_awlen_i(axi_t_awlen_i)
,.axi_awburst_i(axi_t_awburst_i)
,.axi_wvalid_i(axi_t_wvalid_i)
,.axi_wdata_i(axi_t_wdata_i)
,.axi_wstrb_i(axi_t_wstrb_i)
,.axi_wlast_i(axi_t_wlast_i)
,.axi_bready_i(axi_t_bready_i)
,.axi_arvalid_i(axi_t_arvalid_i)
,.axi_araddr_i(axi_t_araddr_i)
,.axi_arid_i(axi_t_arid_i)
,.axi_arlen_i(axi_t_arlen_i)
,.axi_arburst_i(axi_t_arburst_i)
,.axi_rready_i(axi_t_rready_i)
// Outputs
,.mem_i_accept_o(ifetch_accept_w)
,.mem_i_valid_o(ifetch_valid_w)
,.mem_i_error_o(ifetch_error_w)
,.mem_i_inst_o(ifetch_inst_w)
,.mem_d_data_rd_o(dport_tcm_data_rd_w)
,.mem_d_accept_o(dport_tcm_accept_w)
,.mem_d_ack_o(dport_tcm_ack_w)
,.mem_d_error_o(dport_tcm_error_w)
,.mem_d_resp_tag_o(dport_tcm_resp_tag_w)
,.axi_awready_o(axi_t_awready_o)
,.axi_wready_o(axi_t_wready_o)
,.axi_bvalid_o(axi_t_bvalid_o)
,.axi_bresp_o(axi_t_bresp_o)
,.axi_bid_o(axi_t_bid_o)
,.axi_arready_o(axi_t_arready_o)
,.axi_rvalid_o(axi_t_rvalid_o)
,.axi_rdata_o(axi_t_rdata_o)
,.axi_rresp_o(axi_t_rresp_o)
,.axi_rid_o(axi_t_rid_o)
,.axi_rlast_o(axi_t_rlast_o)
);
dport_axi
u_axi
(
// Inputs
.clk_i(clk_i)
,.rst_i(rst_i)
,.mem_addr_i(dport_axi_addr_w)
,.mem_data_wr_i(dport_axi_data_wr_w)
,.mem_rd_i(dport_axi_rd_w)
,.mem_wr_i(dport_axi_wr_w)
,.mem_cacheable_i(dport_axi_cacheable_w)
,.mem_req_tag_i(dport_axi_req_tag_w)
,.mem_invalidate_i(dport_axi_invalidate_w)
,.mem_writeback_i(dport_axi_writeback_w)
,.mem_flush_i(dport_axi_flush_w)
,.axi_awready_i(axi_i_awready_i)
,.axi_wready_i(axi_i_wready_i)
,.axi_bvalid_i(axi_i_bvalid_i)
,.axi_bresp_i(axi_i_bresp_i)
,.axi_arready_i(axi_i_arready_i)
,.axi_rvalid_i(axi_i_rvalid_i)
,.axi_rdata_i(axi_i_rdata_i)
,.axi_rresp_i(axi_i_rresp_i)
// Outputs
,.mem_data_rd_o(dport_axi_data_rd_w)
,.mem_accept_o(dport_axi_accept_w)
,.mem_ack_o(dport_axi_ack_w)
,.mem_error_o(dport_axi_error_w)
,.mem_resp_tag_o(dport_axi_resp_tag_w)
,.axi_awvalid_o(axi_i_awvalid_o)
,.axi_awaddr_o(axi_i_awaddr_o)
,.axi_wvalid_o(axi_i_wvalid_o)
,.axi_wdata_o(axi_i_wdata_o)
,.axi_wstrb_o(axi_i_wstrb_o)
,.axi_bready_o(axi_i_bready_o)
,.axi_arvalid_o(axi_i_arvalid_o)
,.axi_araddr_o(axi_i_araddr_o)
,.axi_rready_o(axi_i_rready_o)
);
endmodule
|
// ============================================================
// File Name: VGAFrequency.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 16.0.0 Build 211 04/27/2016 SJ Lite Edition
// ************************************************************
//Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus Prime License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module VGAFrequency (
areset,
inclk0,
c0);
input areset;
input inclk0;
output c0;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [0:0] sub_wire2 = 1'h0;
wire [4:0] sub_wire3;
wire sub_wire0 = inclk0;
wire [1:0] sub_wire1 = {sub_wire2, sub_wire0};
wire [0:0] sub_wire4 = sub_wire3[0:0];
wire c0 = sub_wire4;
altpll altpll_component (
.areset (areset),
.inclk (sub_wire1),
.clk (sub_wire3),
.activeclock (),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.locked (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 25,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 54,
altpll_component.clk0_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 20000,
altpll_component.intended_device_family = "Cyclone IV E",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=VGAFrequency",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_USED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_UNUSED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_UNUSED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.width_clock = 5;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "7"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "108.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "108.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "VGAFrequency.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "25"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "54"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: GEN_FILE: TYPE_NORMAL VGAFrequency.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL VGAFrequency.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL VGAFrequency.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL VGAFrequency.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL VGAFrequency.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL VGAFrequency_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL VGAFrequency_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON
|
module hd_data_reader (
input clk,
input rst,
input enable,
output reg error,
input hd_read_from_host,
input [31:0] hd_data_from_host
);
//Registers/Wires
reg prev_enable;
wire posedge_enable;
reg [31:0] test_data;
//Submodules
//Asynchronous Logic
assign posedge_enable = (!prev_enable && enable);
//Synchronous Logic
always @ (posedge clk) begin
if (rst) begin
prev_enable <= 0;
error <= 0;
test_data <= 0;
end
else begin
prev_enable <= enable;
if (posedge_enable) begin
error <= 0;
test_data <= 0;
end
else begin
if (hd_read_from_host) begin
if (hd_data_from_host != test_data) begin
error <= 1;
end
test_data <= test_data + 1;
end
end
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__FILL_BLACKBOX_V
`define SKY130_FD_SC_HDLL__FILL_BLACKBOX_V
/**
* fill: Fill cell.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__fill ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__FILL_BLACKBOX_V
|
//Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2014.4 (lin64) Build 1071353 Tue Nov 18 16:47:07 MST 2014
//Date : Thu Mar 31 18:01:07 2016
//Host : lubuntu running 64-bit Ubuntu 15.04
//Command : generate_target design_1.bd
//Design : design_1
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module design_1
(AXI_En,
En,
FrameSize,
M_AXIS_tdata,
M_AXIS_tlast,
M_AXIS_tready,
M_AXIS_tstrb,
M_AXIS_tvalid,
S_AXIS_tdata,
S_AXIS_tlast,
S_AXIS_tready,
S_AXIS_tstrb,
S_AXIS_tvalid,
m_axis_aclk,
m_axis_aresetn);
input AXI_En;
input En;
input [7:0]FrameSize;
output [31:0]M_AXIS_tdata;
output M_AXIS_tlast;
input M_AXIS_tready;
output [3:0]M_AXIS_tstrb;
output M_AXIS_tvalid;
input [31:0]S_AXIS_tdata;
input S_AXIS_tlast;
output S_AXIS_tready;
input [3:0]S_AXIS_tstrb;
input S_AXIS_tvalid;
input m_axis_aclk;
input m_axis_aresetn;
wire AXI_En_1;
wire En_1;
wire [7:0]FrameSize_1;
wire [31:0]S_AXIS_1_TDATA;
wire S_AXIS_1_TLAST;
wire S_AXIS_1_TREADY;
wire [3:0]S_AXIS_1_TSTRB;
wire S_AXIS_1_TVALID;
wire m_axis_aclk_1;
wire m_axis_aresetn_1;
wire [31:0]sample_generator_0_M_AXIS_TDATA;
wire sample_generator_0_M_AXIS_TLAST;
wire sample_generator_0_M_AXIS_TREADY;
wire [3:0]sample_generator_0_M_AXIS_TSTRB;
wire sample_generator_0_M_AXIS_TVALID;
assign AXI_En_1 = AXI_En;
assign En_1 = En;
assign FrameSize_1 = FrameSize[7:0];
assign M_AXIS_tdata[31:0] = sample_generator_0_M_AXIS_TDATA;
assign M_AXIS_tlast = sample_generator_0_M_AXIS_TLAST;
assign M_AXIS_tstrb[3:0] = sample_generator_0_M_AXIS_TSTRB;
assign M_AXIS_tvalid = sample_generator_0_M_AXIS_TVALID;
assign S_AXIS_1_TDATA = S_AXIS_tdata[31:0];
assign S_AXIS_1_TLAST = S_AXIS_tlast;
assign S_AXIS_1_TSTRB = S_AXIS_tstrb[3:0];
assign S_AXIS_1_TVALID = S_AXIS_tvalid;
assign S_AXIS_tready = S_AXIS_1_TREADY;
assign m_axis_aclk_1 = m_axis_aclk;
assign m_axis_aresetn_1 = m_axis_aresetn;
assign sample_generator_0_M_AXIS_TREADY = M_AXIS_tready;
design_1_sample_generator_0_0 sample_generator_0
(.AXI_En(AXI_En_1),
.En(En_1),
.FrameSize(FrameSize_1),
.m_axis_aclk(m_axis_aclk_1),
.m_axis_aresetn(m_axis_aresetn_1),
.m_axis_tdata(sample_generator_0_M_AXIS_TDATA),
.m_axis_tlast(sample_generator_0_M_AXIS_TLAST),
.m_axis_tready(sample_generator_0_M_AXIS_TREADY),
.m_axis_tstrb(sample_generator_0_M_AXIS_TSTRB),
.m_axis_tvalid(sample_generator_0_M_AXIS_TVALID),
.s_axis_aclk(m_axis_aclk_1),
.s_axis_aresetn(m_axis_aresetn_1),
.s_axis_tdata(S_AXIS_1_TDATA),
.s_axis_tlast(S_AXIS_1_TLAST),
.s_axis_tready(S_AXIS_1_TREADY),
.s_axis_tstrb(S_AXIS_1_TSTRB),
.s_axis_tvalid(S_AXIS_1_TVALID));
endmodule
|
// Copyright (C) 2013 Simon Que
//
// This file is part of DuinoCube.
//
// DuinoCube is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// DuinoCube is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU Lesser General Public License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with DuinoCube. If not, see <http://www.gnu.org/licenses/>.
// Test bench for single register module.
module Register_Test;
reg clk; // System clock
reg reset; // System reset
reg en; // Access enable
reg byte_lo; // Low byte enable
reg byte_hi; // High byte enable
reg [15:0] data_in;
wire [15:0] data_out;
assign data = data_in;
Register register(.reset(reset),
.clk(clk),
.en(en),
.be({byte_hi, byte_lo}),
.d(data_in),
.q(data_out));
// Generate clock.
always
#1 clk = ~clk;
initial begin
clk = 0;
reset = 0;
byte_hi = 1;
byte_lo = 1;
en = 0;
// Reset
#5 reset = 1;
#1 reset = 0;
#4 data_in = 'hdead;
#4 data_in = 'hbeef;
#1 en = 1;
#4 data_in = 'hdead;
#4 data_in = 'hbeef;
#1 byte_lo = 1;
byte_hi = 0;
#4 data_in = 'hface;
#4 data_in = 'hcafe;
#1 byte_lo = 0;
byte_hi = 1;
#4 data_in = 'hf00d;
#4 data_in = 'hbead;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DFSTP_FUNCTIONAL_V
`define SKY130_FD_SC_MS__DFSTP_FUNCTIONAL_V
/**
* dfstp: Delay flop, inverted set, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_ps/sky130_fd_sc_ms__udp_dff_ps.v"
`celldefine
module sky130_fd_sc_ms__dfstp (
Q ,
CLK ,
D ,
SET_B
);
// Module ports
output Q ;
input CLK ;
input D ;
input SET_B;
// Local signals
wire buf_Q;
wire SET ;
// Delay Name Output Other arguments
not not0 (SET , SET_B );
sky130_fd_sc_ms__udp_dff$PS `UNIT_DELAY dff0 (buf_Q , D, CLK, SET );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__DFSTP_FUNCTIONAL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A211O_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__A211O_PP_BLACKBOX_V
/**
* a211o: 2-input AND into first input of 3-input OR.
*
* X = ((A1 & A2) | B1 | C1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__a211o (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__A211O_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A21O_6_V
`define SKY130_FD_SC_HDLL__A21O_6_V
/**
* a21o: 2-input AND into first input of 2-input OR.
*
* X = ((A1 & A2) | B1)
*
* Verilog wrapper for a21o with size of 6 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__a21o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__a21o_6 (
X ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__a21o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__a21o_6 (
X ,
A1,
A2,
B1
);
output X ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__a21o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A21O_6_V
|
module ALU (
input [31:0] in1, in2,
input [5:0] ALUFun,
input sign,
output reg [31:0] out
);
reg zero, overflow;
wire negative;
reg [31:0] out00, out01, out10, out11;
reg nega;
assign negative = sign&nega;
always @ (*) begin
case (ALUFun[0])
1'b0: begin
out00 = in1 + in2;
zero = (out00 == 1'b0)? 1'b1 : 1'b0;
overflow = (sign&(in1[31]&in2[31]) ^ (in1[30]&in2[30])) | (~sign&(in1[31]&in2[31]));
nega = out00[31];
end
1'b1: begin
out00 = in1 + ~in2 + 32'b1;
zero = (out00 == 1'b0)? 1'b1 : 1'b0;
overflow = (sign&(in1[31]&in2[31]) ^ (in1[30]&in2[30])) | (~sign&(in1[31]&in2[31]));
nega = out00[31];
end
default : out00 = 32'b0;
endcase
case (ALUFun[3:1])
3'b001: out11 = zero ? 32'b1 : 32'b0;
3'b000: out11 = zero ? 32'b0 : 32'b1;
3'b010: out11 = nega ? 32'b1 : 32'b0;
3'b110: out11 = (nega|zero) ? 32'b1 : 32'b0; // blez
3'b100: out11 = (~in1[31]) ? 32'b1 : 32'b0; // bgez
3'b111: out11 = (~in1[31]&~zero) ? 32'b1 : 32'b0; // bgtz
default : out11 = 32'b0;
endcase
case (ALUFun[3:0])
4'b1000: out01 = in1 & in2;
4'b1110: out01 = in1 | in2;
4'b0110: out01 = in1 ^ in2;
4'b0001: out01 = ~(in1 | in2);
4'b1010: out01 = in1;
default : out01 = 32'b0;
endcase
case (ALUFun[1:0])
2'b00: begin // sll
out10 = in2;
if (in1[4]) out10 = out10<<16;
if (in1[3]) out10 = out10<<8;
if (in1[2]) out10 = out10<<4;
if (in1[1]) out10 = out10<<2;
if (in1[0]) out10 = out10<<1;
end
2'b01: begin // srl
out10 = in2;
if (in1[4]) out10 = out10>>16;
if (in1[3]) out10 = out10>>8;
if (in1[2]) out10 = out10>>4;
if (in1[1]) out10 = out10>>2;
if (in1[0]) out10 = out10>>1;
end
2'b11: begin // sra
out10 = in2;
if (in1[4]) out10 = (out10>>16) | {{16{in2[31]}},{16{1'b0}}};
if (in1[3]) out10 = ((out10>>8) | {{8{in2[31]}},{24{1'b0}}});
if (in1[2]) out10 = (out10>>4) | {{4{in2[31]}},{28{1'b0}}};
if (in1[1]) out10 = (out10>>2) | {{2{in2[31]}},{30{1'b0}}};
if (in1[0]) out10 = (out10>>1) | {{1{in2[31]}},{31{1'b0}}};
end
default : out10 = 32'b0;
endcase
case(ALUFun[5:4])
2'b00: out = out00;
2'b01: out = out01;
2'b10: out = out10;
2'b11: out = out11;
default: out<= 32'b0;
endcase
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__AND3_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__AND3_BEHAVIORAL_V
/**
* and3: 3-input AND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__and3 (
X,
A,
B,
C
);
// Module ports
output X;
input A;
input B;
input C;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out_X;
// Name Output Other arguments
and and0 (and0_out_X, C, A, B );
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__AND3_BEHAVIORAL_V
|
`timescale 100 ps/100 ps
module circuit_under_test (
clk,
rst,
testVector,
resultVector,
injectionVector
);
input clk;
input rst;
input[18:0] testVector;
output[18:0] resultVector;
input[345:0] injectionVector;
IIR_Biquad_inj toplevel_instance (
.clk(clk),
.n_reset(rst),
.sample_trig(testVector[0]),
.X_in(testVector [18:1]),
.filter_done(resultVector[0]),
.Y_out(resultVector [18:1]),
.p_desc86_p_O_FDE(injectionVector[0]),
.p_desc87_p_O_FDE(injectionVector[1]),
.p_desc88_p_O_FDE(injectionVector[2]),
.p_desc89_p_O_FDE(injectionVector[3]),
.p_desc90_p_O_FDE(injectionVector[4]),
.p_desc91_p_O_FDE(injectionVector[5]),
.p_desc92_p_O_FDE(injectionVector[6]),
.p_desc93_p_O_FDE(injectionVector[7]),
.p_desc94_p_O_FDE(injectionVector[8]),
.p_desc95_p_O_FDE(injectionVector[9]),
.p_desc96_p_O_FDE(injectionVector[10]),
.p_desc97_p_O_FDE(injectionVector[11]),
.p_desc98_p_O_FDE(injectionVector[12]),
.p_desc99_p_O_FDE(injectionVector[13]),
.p_desc100_p_O_FDE(injectionVector[14]),
.p_desc101_p_O_FDE(injectionVector[15]),
.p_desc102_p_O_FDE(injectionVector[16]),
.p_desc103_p_O_FDE(injectionVector[17]),
.p_desc104_p_O_FDE(injectionVector[18]),
.p_desc105_p_O_FDE(injectionVector[19]),
.p_desc106_p_O_FDE(injectionVector[20]),
.p_desc107_p_O_FDE(injectionVector[21]),
.p_desc108_p_O_FDE(injectionVector[22]),
.p_desc109_p_O_FDE(injectionVector[23]),
.p_desc110_p_O_FDE(injectionVector[24]),
.p_desc111_p_O_FDE(injectionVector[25]),
.p_desc112_p_O_FDE(injectionVector[26]),
.p_desc113_p_O_FDE(injectionVector[27]),
.p_desc114_p_O_FDE(injectionVector[28]),
.p_desc115_p_O_FDE(injectionVector[29]),
.p_desc116_p_O_FDE(injectionVector[30]),
.p_desc117_p_O_FDE(injectionVector[31]),
.p_desc118_p_O_FDE(injectionVector[32]),
.p_desc119_p_O_FDE(injectionVector[33]),
.p_desc120_p_O_FDE(injectionVector[34]),
.p_desc121_p_O_FDE(injectionVector[35]),
.p_desc162_p_O_FDE(injectionVector[36]),
.p_desc163_p_O_FDE(injectionVector[37]),
.p_desc164_p_O_FDE(injectionVector[38]),
.p_desc165_p_O_FDE(injectionVector[39]),
.p_desc166_p_O_FDE(injectionVector[40]),
.p_desc167_p_O_FDE(injectionVector[41]),
.p_desc168_p_O_FDE(injectionVector[42]),
.p_desc169_p_O_FDE(injectionVector[43]),
.p_desc170_p_O_FDE(injectionVector[44]),
.p_desc171_p_O_FDE(injectionVector[45]),
.p_desc172_p_O_FDE(injectionVector[46]),
.p_desc173_p_O_FDE(injectionVector[47]),
.p_desc174_p_O_FDE(injectionVector[48]),
.p_desc175_p_O_FDE(injectionVector[49]),
.p_desc176_p_O_FDE(injectionVector[50]),
.p_desc177_p_O_FDE(injectionVector[51]),
.p_desc178_p_O_FDE(injectionVector[52]),
.p_desc179_p_O_FDE(injectionVector[53]),
.p_desc198_p_O_FDE(injectionVector[54]),
.p_desc199_p_O_FDE(injectionVector[55]),
.p_desc200_p_O_FDE(injectionVector[56]),
.p_desc201_p_O_FDE(injectionVector[57]),
.p_desc202_p_O_FDE(injectionVector[58]),
.p_desc203_p_O_FDE(injectionVector[59]),
.p_desc204_p_O_FDE(injectionVector[60]),
.p_desc205_p_O_FDE(injectionVector[61]),
.p_desc206_p_O_FDE(injectionVector[62]),
.p_desc207_p_O_FDE(injectionVector[63]),
.p_desc208_p_O_FDE(injectionVector[64]),
.p_desc209_p_O_FDE(injectionVector[65]),
.p_desc210_p_O_FDE(injectionVector[66]),
.p_desc211_p_O_FDE(injectionVector[67]),
.p_desc212_p_O_FDE(injectionVector[68]),
.p_desc213_p_O_FDE(injectionVector[69]),
.p_desc214_p_O_FDE(injectionVector[70]),
.p_desc215_p_O_FDE(injectionVector[71]),
.p_desc216_p_O_FDE(injectionVector[72]),
.p_desc217_p_O_FDE(injectionVector[73]),
.p_desc218_p_O_FDE(injectionVector[74]),
.p_desc219_p_O_FDE(injectionVector[75]),
.p_desc220_p_O_FDE(injectionVector[76]),
.p_desc221_p_O_FDE(injectionVector[77]),
.p_desc222_p_O_FDE(injectionVector[78]),
.p_desc223_p_O_FDE(injectionVector[79]),
.p_desc224_p_O_FDE(injectionVector[80]),
.p_desc225_p_O_FDE(injectionVector[81]),
.p_desc226_p_O_FDE(injectionVector[82]),
.p_desc227_p_O_FDE(injectionVector[83]),
.p_desc228_p_O_FDE(injectionVector[84]),
.p_desc229_p_O_FDE(injectionVector[85]),
.p_desc230_p_O_FDE(injectionVector[86]),
.p_desc231_p_O_FDE(injectionVector[87]),
.p_desc232_p_O_FDE(injectionVector[88]),
.p_desc233_p_O_FDE(injectionVector[89]),
.p_desc234_p_O_FDE(injectionVector[90]),
.p_desc235_p_O_FDE(injectionVector[91]),
.p_desc236_p_O_FDE(injectionVector[92]),
.p_desc237_p_O_FDE(injectionVector[93]),
.p_desc238_p_O_FDE(injectionVector[94]),
.p_desc239_p_O_FDE(injectionVector[95]),
.p_desc240_p_O_FDE(injectionVector[96]),
.p_desc241_p_O_FDE(injectionVector[97]),
.p_desc242_p_O_FDE(injectionVector[98]),
.p_desc243_p_O_FDE(injectionVector[99]),
.p_desc244_p_O_FDE(injectionVector[100]),
.p_desc245_p_O_FDE(injectionVector[101]),
.p_desc246_p_O_FDE(injectionVector[102]),
.p_desc247_p_O_FDE(injectionVector[103]),
.p_desc248_p_O_FDE(injectionVector[104]),
.p_desc249_p_O_FDE(injectionVector[105]),
.p_desc250_p_O_FDE(injectionVector[106]),
.p_desc251_p_O_FDE(injectionVector[107]),
.p_desc252_p_O_FDE(injectionVector[108]),
.p_desc253_p_O_FDE(injectionVector[109]),
.p_desc254_p_O_FDE(injectionVector[110]),
.p_desc255_p_O_FDE(injectionVector[111]),
.p_desc256_p_O_FDE(injectionVector[112]),
.p_desc257_p_O_FDE(injectionVector[113]),
.p_desc258_p_O_FDE(injectionVector[114]),
.p_desc259_p_O_FDE(injectionVector[115]),
.p_desc260_p_O_FDE(injectionVector[116]),
.p_desc261_p_O_FDE(injectionVector[117]),
.p_desc262_p_O_FDE(injectionVector[118]),
.p_desc263_p_O_FDE(injectionVector[119]),
.p_desc264_p_O_FDE(injectionVector[120]),
.p_desc334_p_O_FDC(injectionVector[121]),
.p_desc335_p_O_FDC(injectionVector[122]),
.p_desc336_p_O_FDC(injectionVector[123]),
.p_desc337_p_O_FDC(injectionVector[124]),
.p_state_reg_ret_5_Z_p_O_FDC(injectionVector[125]),
.p_state_reg_ret_Z_p_O_FDP(injectionVector[126]),
.p_state_reg_ret_1_Z_p_O_FDP(injectionVector[127]),
.p_state_reg_ret_2_Z_p_O_FDP(injectionVector[128]),
.p_state_reg_ret_4_Z_p_O_FDP(injectionVector[129]),
.p_desc180_p_O_FDCE(injectionVector[130]),
.p_desc181_p_O_FDCE(injectionVector[131]),
.p_desc182_p_O_FDCE(injectionVector[132]),
.p_desc183_p_O_FDCE(injectionVector[133]),
.p_desc184_p_O_FDCE(injectionVector[134]),
.p_desc185_p_O_FDCE(injectionVector[135]),
.p_desc186_p_O_FDCE(injectionVector[136]),
.p_desc187_p_O_FDCE(injectionVector[137]),
.p_desc188_p_O_FDCE(injectionVector[138]),
.p_desc189_p_O_FDCE(injectionVector[139]),
.p_desc190_p_O_FDCE(injectionVector[140]),
.p_desc191_p_O_FDCE(injectionVector[141]),
.p_desc192_p_O_FDCE(injectionVector[142]),
.p_desc193_p_O_FDCE(injectionVector[143]),
.p_desc194_p_O_FDCE(injectionVector[144]),
.p_desc195_p_O_FDCE(injectionVector[145]),
.p_desc196_p_O_FDCE(injectionVector[146]),
.p_desc197_p_O_FDCE(injectionVector[147]),
.p_desc265_p_O_FDCE(injectionVector[148]),
.p_desc266_p_O_FDCE(injectionVector[149]),
.p_desc267_p_O_FDCE(injectionVector[150]),
.p_desc268_p_O_FDCE(injectionVector[151]),
.p_desc269_p_O_FDCE(injectionVector[152]),
.p_desc270_p_O_FDCE(injectionVector[153]),
.p_desc271_p_O_FDCE(injectionVector[154]),
.p_desc272_p_O_FDCE(injectionVector[155]),
.p_desc273_p_O_FDCE(injectionVector[156]),
.p_desc274_p_O_FDCE(injectionVector[157]),
.p_desc275_p_O_FDCE(injectionVector[158]),
.p_desc276_p_O_FDCE(injectionVector[159]),
.p_desc277_p_O_FDCE(injectionVector[160]),
.p_desc278_p_O_FDCE(injectionVector[161]),
.p_desc279_p_O_FDCE(injectionVector[162]),
.p_desc280_p_O_FDCE(injectionVector[163]),
.p_desc281_p_O_FDCE(injectionVector[164]),
.p_desc282_p_O_FDCE(injectionVector[165]),
.p_desc283_p_O_FDCE(injectionVector[166]),
.p_desc284_p_O_FDCE(injectionVector[167]),
.p_desc285_p_O_FDCE(injectionVector[168]),
.p_desc286_p_O_FDCE(injectionVector[169]),
.p_desc287_p_O_FDCE(injectionVector[170]),
.p_desc288_p_O_FDCE(injectionVector[171]),
.p_desc289_p_O_FDCE(injectionVector[172]),
.p_desc290_p_O_FDCE(injectionVector[173]),
.p_desc291_p_O_FDCE(injectionVector[174]),
.p_desc292_p_O_FDCE(injectionVector[175]),
.p_desc293_p_O_FDCE(injectionVector[176]),
.p_desc294_p_O_FDCE(injectionVector[177]),
.p_desc295_p_O_FDCE(injectionVector[178]),
.p_desc296_p_O_FDCE(injectionVector[179]),
.p_desc297_p_O_FDCE(injectionVector[180]),
.p_desc298_p_O_FDCE(injectionVector[181]),
.p_desc299_p_O_FDCE(injectionVector[182]),
.p_desc300_p_O_FDCE(injectionVector[183]),
.p_desc301_p_O_FDCE(injectionVector[184]),
.p_desc302_p_O_FDCE(injectionVector[185]),
.p_desc303_p_O_FDCE(injectionVector[186]),
.p_desc304_p_O_FDCE(injectionVector[187]),
.p_desc305_p_O_FDCE(injectionVector[188]),
.p_desc306_p_O_FDCE(injectionVector[189]),
.p_desc307_p_O_FDCE(injectionVector[190]),
.p_desc308_p_O_FDCE(injectionVector[191]),
.p_desc309_p_O_FDCE(injectionVector[192]),
.p_desc310_p_O_FDCE(injectionVector[193]),
.p_desc311_p_O_FDCE(injectionVector[194]),
.p_desc312_p_O_FDCE(injectionVector[195]),
.p_desc313_p_O_FDCE(injectionVector[196]),
.p_desc314_p_O_FDCE(injectionVector[197]),
.p_desc315_p_O_FDCE(injectionVector[198]),
.p_desc316_p_O_FDCE(injectionVector[199]),
.p_desc317_p_O_FDCE(injectionVector[200]),
.p_desc318_p_O_FDCE(injectionVector[201]),
.p_desc319_p_O_FDCE(injectionVector[202]),
.p_desc320_p_O_FDCE(injectionVector[203]),
.p_desc321_p_O_FDCE(injectionVector[204]),
.p_desc322_p_O_FDCE(injectionVector[205]),
.p_desc323_p_O_FDCE(injectionVector[206]),
.p_desc324_p_O_FDCE(injectionVector[207]),
.p_desc325_p_O_FDCE(injectionVector[208]),
.p_desc326_p_O_FDCE(injectionVector[209]),
.p_desc327_p_O_FDCE(injectionVector[210]),
.p_desc328_p_O_FDCE(injectionVector[211]),
.p_desc329_p_O_FDCE(injectionVector[212]),
.p_desc330_p_O_FDCE(injectionVector[213]),
.p_desc331_p_O_FDCE(injectionVector[214]),
.p_desc332_p_O_FDCE(injectionVector[215]),
.p_desc333_p_O_FDCE(injectionVector[216]),
.p_desc338_p_O_FDCE(injectionVector[217]),
.p_ZFF_Y1_0_rep1_Z_p_O_FDCE(injectionVector[218]),
.p_desc339_p_O_FDCE(injectionVector[219]),
.p_ZFF_Y1_15_rep1_Z_p_O_FDCE(injectionVector[220]),
.p_desc340_p_O_FDCE(injectionVector[221]),
.p_ZFF_X0_7_rep1_Z_p_O_FDCE(injectionVector[222]),
.p_desc341_p_O_FDCE(injectionVector[223]),
.p_desc342_p_O_FDCE(injectionVector[224]),
.p_desc343_p_O_FDCE(injectionVector[225]),
.p_desc344_p_O_FDCE(injectionVector[226]),
.p_ZFF_Y1_16_rep1_Z_p_O_FDCE(injectionVector[227]),
.p_desc345_p_O_FDCE(injectionVector[228]),
.p_ZFF_X0_6_rep1_Z_p_O_FDCE(injectionVector[229]),
.p_desc346_p_O_FDCE(injectionVector[230]),
.p_desc347_p_O_FDCE(injectionVector[231]),
.p_ZFF_Y1_2_rep1_Z_p_O_FDCE(injectionVector[232]),
.p_desc348_p_O_FDCE(injectionVector[233]),
.p_desc349_p_O_FDCE(injectionVector[234]),
.p_ZFF_X0_10_rep1_Z_p_O_FDCE(injectionVector[235]),
.p_desc350_p_O_FDCE(injectionVector[236]),
.p_ZFF_X0_11_rep1_Z_p_O_FDCE(injectionVector[237]),
.p_desc351_p_O_FDCE(injectionVector[238]),
.p_ZFF_X0_12_rep1_Z_p_O_FDCE(injectionVector[239]),
.p_desc352_p_O_FDCE(injectionVector[240]),
.p_ZFF_X2_6_rep1_Z_p_O_FDCE(injectionVector[241]),
.p_desc353_p_O_FDCE(injectionVector[242]),
.p_ZFF_X0_4_rep1_Z_p_O_FDCE(injectionVector[243]),
.p_desc354_p_O_FDCE(injectionVector[244]),
.p_desc355_p_O_FDCE(injectionVector[245]),
.p_desc356_p_O_FDCE(injectionVector[246]),
.p_desc357_p_O_FDCE(injectionVector[247]),
.p_ZFF_X2_10_rep1_Z_p_O_FDCE(injectionVector[248]),
.p_desc358_p_O_FDCE(injectionVector[249]),
.p_ZFF_X0_2_rep1_Z_p_O_FDCE(injectionVector[250]),
.p_desc359_p_O_FDCE(injectionVector[251]),
.p_ZFF_X0_1_rep1_Z_p_O_FDCE(injectionVector[252]),
.p_desc360_p_O_FDCE(injectionVector[253]),
.p_ZFF_Y1_1_rep1_Z_p_O_FDCE(injectionVector[254]),
.p_desc361_p_O_FDCE(injectionVector[255]),
.p_desc362_p_O_FDCE(injectionVector[256]),
.p_desc363_p_O_FDCE(injectionVector[257]),
.p_desc364_p_O_FDCE(injectionVector[258]),
.p_ZFF_X2_2_rep1_Z_p_O_FDCE(injectionVector[259]),
.p_desc365_p_O_FDCE(injectionVector[260]),
.p_ZFF_X0_3_rep1_Z_p_O_FDCE(injectionVector[261]),
.p_desc366_p_O_FDCE(injectionVector[262]),
.p_desc367_p_O_FDCE(injectionVector[263]),
.p_ZFF_X2_3_rep1_Z_p_O_FDCE(injectionVector[264]),
.p_desc368_p_O_FDCE(injectionVector[265]),
.p_ZFF_Y1_4_rep1_Z_p_O_FDCE(injectionVector[266]),
.p_desc369_p_O_FDCE(injectionVector[267]),
.p_desc370_p_O_FDCE(injectionVector[268]),
.p_ZFF_Y1_3_rep1_Z_p_O_FDCE(injectionVector[269]),
.p_desc371_p_O_FDCE(injectionVector[270]),
.p_desc372_p_O_FDCE(injectionVector[271]),
.p_desc373_p_O_FDCE(injectionVector[272]),
.p_ZFF_Y1_5_rep1_Z_p_O_FDCE(injectionVector[273]),
.p_desc374_p_O_FDCE(injectionVector[274]),
.p_ZFF_X2_14_rep1_Z_p_O_FDCE(injectionVector[275]),
.p_desc375_p_O_FDCE(injectionVector[276]),
.p_ZFF_X0_14_rep1_Z_p_O_FDCE(injectionVector[277]),
.p_desc376_p_O_FDCE(injectionVector[278]),
.p_ZFF_X0_15_rep1_Z_p_O_FDCE(injectionVector[279]),
.p_desc377_p_O_FDCE(injectionVector[280]),
.p_ZFF_X2_15_rep1_Z_p_O_FDCE(injectionVector[281]),
.p_desc378_p_O_FDCE(injectionVector[282]),
.p_ZFF_Y1_6_rep1_Z_p_O_FDCE(injectionVector[283]),
.p_desc379_p_O_FDCE(injectionVector[284]),
.p_ZFF_Y1_13_rep1_Z_p_O_FDCE(injectionVector[285]),
.p_desc380_p_O_FDCE(injectionVector[286]),
.p_ZFF_Y1_7_rep1_Z_p_O_FDCE(injectionVector[287]),
.p_desc381_p_O_FDCE(injectionVector[288]),
.p_ZFF_Y1_14_rep1_Z_p_O_FDCE(injectionVector[289]),
.p_desc382_p_O_FDCE(injectionVector[290]),
.p_ZFF_X1_3_rep1_Z_p_O_FDCE(injectionVector[291]),
.p_desc383_p_O_FDCE(injectionVector[292]),
.p_ZFF_X1_0_rep1_Z_p_O_FDCE(injectionVector[293]),
.p_desc384_p_O_FDCE(injectionVector[294]),
.p_ZFF_Y1_9_rep1_Z_p_O_FDCE(injectionVector[295]),
.p_desc385_p_O_FDCE(injectionVector[296]),
.p_ZFF_X1_7_rep1_Z_p_O_FDCE(injectionVector[297]),
.p_desc386_p_O_FDCE(injectionVector[298]),
.p_ZFF_X1_4_rep1_Z_p_O_FDCE(injectionVector[299]),
.p_desc387_p_O_FDCE(injectionVector[300]),
.p_ZFF_X1_1_rep1_Z_p_O_FDCE(injectionVector[301]),
.p_desc388_p_O_FDCE(injectionVector[302]),
.p_ZFF_Y1_10_rep1_Z_p_O_FDCE(injectionVector[303]),
.p_desc389_p_O_FDCE(injectionVector[304]),
.p_ZFF_X1_8_rep1_Z_p_O_FDCE(injectionVector[305]),
.p_desc390_p_O_FDCE(injectionVector[306]),
.p_ZFF_X1_9_rep1_Z_p_O_FDCE(injectionVector[307]),
.p_desc391_p_O_FDCE(injectionVector[308]),
.p_ZFF_X1_11_rep1_Z_p_O_FDCE(injectionVector[309]),
.p_desc392_p_O_FDCE(injectionVector[310]),
.p_ZFF_X1_15_rep1_Z_p_O_FDCE(injectionVector[311]),
.p_desc393_p_O_FDCE(injectionVector[312]),
.p_ZFF_X1_2_rep1_Z_p_O_FDCE(injectionVector[313]),
.p_desc394_p_O_FDCE(injectionVector[314]),
.p_ZFF_Y1_12_rep1_Z_p_O_FDCE(injectionVector[315]),
.p_desc395_p_O_FDCE(injectionVector[316]),
.p_ZFF_X0_16_rep1_Z_p_O_FDCE(injectionVector[317]),
.p_desc396_p_O_FDCE(injectionVector[318]),
.p_desc397_p_O_FDCE(injectionVector[319]),
.p_ZFF_Y1_17_rep1_Z_p_O_FDCE(injectionVector[320]),
.p_desc398_p_O_FDCE(injectionVector[321]),
.p_ZFF_X1_5_rep1_Z_p_O_FDCE(injectionVector[322]),
.p_desc399_p_O_FDCE(injectionVector[323]),
.p_ZFF_Y1_8_rep1_Z_p_O_FDCE(injectionVector[324]),
.p_desc400_p_O_FDCE(injectionVector[325]),
.p_desc401_p_O_FDCE(injectionVector[326]),
.p_desc402_p_O_FDCE(injectionVector[327]),
.p_ZFF_X1_6_rep1_Z_p_O_FDCE(injectionVector[328]),
.p_desc403_p_O_FDCE(injectionVector[329]),
.p_ZFF_X1_12_rep1_Z_p_O_FDCE(injectionVector[330]),
.p_desc404_p_O_FDCE(injectionVector[331]),
.p_ZFF_X1_10_rep1_Z_p_O_FDCE(injectionVector[332]),
.p_desc405_p_O_FDCE(injectionVector[333]),
.p_ZFF_X1_13_rep1_Z_p_O_FDCE(injectionVector[334]),
.p_desc406_p_O_FDCE(injectionVector[335]),
.p_ZFF_Y1_11_rep1_Z_p_O_FDCE(injectionVector[336]),
.p_desc407_p_O_FDCE(injectionVector[337]),
.p_ZFF_Y2_8_rep1_Z_p_O_FDCE(injectionVector[338]),
.p_desc408_p_O_FDCE(injectionVector[339]),
.p_desc409_p_O_FDCE(injectionVector[340]),
.p_ZFF_Y2_6_rep1_Z_p_O_FDCE(injectionVector[341]),
.p_desc410_p_O_FDCE(injectionVector[342]),
.p_ZFF_Y2_7_rep1_Z_p_O_FDCE(injectionVector[343]),
.p_desc411_p_O_FDCE(injectionVector[344]),
.p_ZFF_Y2_14_rep1_Z_p_O_FDCE(injectionVector[345]));
endmodule
|
`include "gate.v"
module Not16(input[15:0] in, output[15:0] out);
Not g15(in[15], out[15]);
Not g14(in[14], out[14]);
Not g13(in[13], out[13]);
Not g12(in[12], out[12]);
Not g11(in[11], out[11]);
Not g10(in[10], out[10]);
Not g09(in[9], out[9]);
Not g08(in[8], out[8]);
Not g07(in[7], out[7]);
Not g06(in[6], out[6]);
Not g05(in[5], out[5]);
Not g04(in[4], out[4]);
Not g03(in[3], out[3]);
Not g02(in[2], out[2]);
Not g01(in[1], out[1]);
Not g00(in[0], out[0]);
endmodule
module And16(input[15:0] a, b, output[15:0] out);
And g15(a[15], b[15], out[15]);
And g14(a[14], b[14], out[14]);
And g13(a[13], b[13], out[13]);
And g12(a[12], b[12], out[12]);
And g11(a[11], b[11], out[11]);
And g10(a[10], b[10], out[10]);
And g09(a[9], b[9], out[9]);
And g08(a[8], b[8], out[8]);
And g07(a[7], b[7], out[7]);
And g06(a[6], b[6], out[6]);
And g05(a[5], b[5], out[5]);
And g04(a[4], b[4], out[4]);
And g03(a[3], b[3], out[3]);
And g02(a[2], b[2], out[2]);
And g01(a[1], b[1], out[1]);
And g00(a[0], b[0], out[0]);
endmodule
module Or16(input[15:0] a, b, output[15:0] out);
Or g15(a[15], b[15], out[15]);
Or g14(a[14], b[14], out[14]);
Or g13(a[13], b[13], out[13]);
Or g12(a[12], b[12], out[12]);
Or g11(a[11], b[11], out[11]);
Or g10(a[10], b[10], out[10]);
Or g09(a[9], b[9], out[9]);
Or g08(a[8], b[8], out[8]);
Or g07(a[7], b[7], out[7]);
Or g06(a[6], b[6], out[6]);
Or g05(a[5], b[5], out[5]);
Or g04(a[4], b[4], out[4]);
Or g03(a[3], b[3], out[3]);
Or g02(a[2], b[2], out[2]);
Or g01(a[1], b[1], out[1]);
Or g00(a[0], b[0], out[0]);
endmodule
|
// Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2015.1 (lin64) Build 1215546 Mon Apr 27 19:07:21 MDT 2015
// Date : Fri Sep 18 12:15:17 2015
// Host : parallella running 64-bit Ubuntu 14.04.3 LTS
// Command : write_verilog -force -mode synth_stub
// /home/aolofsson/Work_all/oh/xilibs/ip/fifo_async_104x32/fifo_async_104x32_stub.v
// Design : fifo_async_104x32
// Purpose : Stub declaration of top-level module interface
// Device : xc7z015clg485-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "fifo_generator_v12_0,Vivado 2015.1" *)
module fifo_async_104x32(wr_clk, wr_rst, rd_clk, rd_rst, din, wr_en, rd_en, dout, full, almost_full, empty, valid, prog_full)
/* synthesis syn_black_box black_box_pad_pin="wr_clk,wr_rst,rd_clk,rd_rst,din[103:0],wr_en,rd_en,dout[103:0],full,almost_full,empty,valid,prog_full" */;
input wr_clk;
input wr_rst;
input rd_clk;
input rd_rst;
input [103:0]din;
input wr_en;
input rd_en;
output [103:0]dout;
output full;
output almost_full;
output empty;
output valid;
output prog_full;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A221O_FUNCTIONAL_V
`define SKY130_FD_SC_LS__A221O_FUNCTIONAL_V
/**
* a221o: 2-input AND into first two inputs of 3-input OR.
*
* X = ((A1 & A2) | (B1 & B2) | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__a221o (
X ,
A1,
A2,
B1,
B2,
C1
);
// Module ports
output X ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Local signals
wire and0_out ;
wire and1_out ;
wire or0_out_X;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
and and1 (and1_out , A1, A2 );
or or0 (or0_out_X, and1_out, and0_out, C1);
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__A221O_FUNCTIONAL_V
|
//Legal Notice: (C)2019 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module wasca_uart_0_tx (
// inputs:
baud_divisor,
begintransfer,
clk,
clk_en,
do_force_break,
reset_n,
status_wr_strobe,
tx_data,
tx_wr_strobe,
// outputs:
tx_overrun,
tx_ready,
tx_shift_empty,
txd
)
;
output tx_overrun;
output tx_ready;
output tx_shift_empty;
output txd;
input [ 15: 0] baud_divisor;
input begintransfer;
input clk;
input clk_en;
input do_force_break;
input reset_n;
input status_wr_strobe;
input [ 7: 0] tx_data;
input tx_wr_strobe;
reg baud_clk_en;
reg [ 15: 0] baud_rate_counter;
wire baud_rate_counter_is_zero;
reg do_load_shifter;
wire do_shift;
reg pre_txd;
wire shift_done;
wire [ 10: 0] tx_load_val;
reg tx_overrun;
reg tx_ready;
reg tx_shift_empty;
wire tx_shift_reg_out;
wire [ 10: 0] tx_shift_register_contents;
wire tx_wr_strobe_onset;
reg txd;
wire [ 10: 0] unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_in;
reg [ 10: 0] unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out;
assign tx_wr_strobe_onset = tx_wr_strobe && begintransfer;
assign tx_load_val = {{1 {1'b1}},
~(^tx_data),
tx_data,
1'b0};
assign shift_done = ~(|tx_shift_register_contents);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
do_load_shifter <= 0;
else if (clk_en)
do_load_shifter <= (~tx_ready) && shift_done;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
tx_ready <= 1'b1;
else if (clk_en)
if (tx_wr_strobe_onset)
tx_ready <= 0;
else if (do_load_shifter)
tx_ready <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
tx_overrun <= 0;
else if (clk_en)
if (status_wr_strobe)
tx_overrun <= 0;
else if (~tx_ready && tx_wr_strobe_onset)
tx_overrun <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
tx_shift_empty <= 1'b1;
else if (clk_en)
tx_shift_empty <= tx_ready && shift_done;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
baud_rate_counter <= 0;
else if (clk_en)
if (baud_rate_counter_is_zero || do_load_shifter)
baud_rate_counter <= baud_divisor;
else
baud_rate_counter <= baud_rate_counter - 1;
end
assign baud_rate_counter_is_zero = baud_rate_counter == 0;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
baud_clk_en <= 0;
else if (clk_en)
baud_clk_en <= baud_rate_counter_is_zero;
end
assign do_shift = baud_clk_en &&
(~shift_done) &&
(~do_load_shifter);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
pre_txd <= 1;
else if (~shift_done)
pre_txd <= tx_shift_reg_out;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
txd <= 1;
else if (clk_en)
txd <= pre_txd & ~do_force_break;
end
//_reg, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out <= 0;
else if (clk_en)
unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out <= unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_in;
end
assign unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_in = (do_load_shifter)? tx_load_val :
(do_shift)? {1'b0,
unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[10 : 1]} :
unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out;
assign tx_shift_register_contents = unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out;
assign tx_shift_reg_out = unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[0];
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module wasca_uart_0_rx_stimulus_source (
// inputs:
baud_divisor,
clk,
clk_en,
reset_n,
rx_char_ready,
rxd,
// outputs:
source_rxd
)
;
output source_rxd;
input [ 15: 0] baud_divisor;
input clk;
input clk_en;
input reset_n;
input rx_char_ready;
input rxd;
reg [ 7: 0] d1_stim_data;
reg delayed_unxrx_char_readyxx0;
wire do_send_stim_data;
wire pickup_pulse;
wire source_rxd;
wire [ 7: 0] stim_data;
wire unused_empty;
wire unused_overrun;
wire unused_ready;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//stimulus_transmitter, which is an e_instance
wasca_uart_0_tx stimulus_transmitter
(
.baud_divisor (baud_divisor),
.begintransfer (do_send_stim_data),
.clk (clk),
.clk_en (clk_en),
.do_force_break (1'b0),
.reset_n (reset_n),
.status_wr_strobe (1'b0),
.tx_data (d1_stim_data),
.tx_overrun (unused_overrun),
.tx_ready (unused_ready),
.tx_shift_empty (unused_empty),
.tx_wr_strobe (1'b1),
.txd (source_rxd)
);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_stim_data <= 0;
else if (do_send_stim_data)
d1_stim_data <= stim_data;
end
assign stim_data = 8'b0;
//delayed_unxrx_char_readyxx0, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
delayed_unxrx_char_readyxx0 <= 0;
else if (clk_en)
delayed_unxrx_char_readyxx0 <= rx_char_ready;
end
assign pickup_pulse = ~(rx_char_ready) & (delayed_unxrx_char_readyxx0);
assign do_send_stim_data = (pickup_pulse || 1'b0) && 1'b0;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// assign source_rxd = rxd;
//synthesis read_comments_as_HDL off
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module wasca_uart_0_rx (
// inputs:
baud_divisor,
begintransfer,
clk,
clk_en,
reset_n,
rx_rd_strobe,
rxd,
status_wr_strobe,
// outputs:
break_detect,
framing_error,
parity_error,
rx_char_ready,
rx_data,
rx_overrun
)
;
output break_detect;
output framing_error;
output parity_error;
output rx_char_ready;
output [ 7: 0] rx_data;
output rx_overrun;
input [ 15: 0] baud_divisor;
input begintransfer;
input clk;
input clk_en;
input reset_n;
input rx_rd_strobe;
input rxd;
input status_wr_strobe;
reg baud_clk_en;
wire [ 15: 0] baud_load_value;
reg [ 15: 0] baud_rate_counter;
wire baud_rate_counter_is_zero;
reg break_detect;
wire correct_parity;
reg delayed_unxrx_in_processxx3;
reg delayed_unxsync_rxdxx1;
reg delayed_unxsync_rxdxx2;
reg do_start_rx;
reg framing_error;
wire got_new_char;
wire [ 14: 0] half_bit_cell_divisor;
wire is_break;
wire is_framing_error;
wire is_parity_error;
wire parity_bit;
reg parity_error;
wire [ 7: 0] raw_data_in;
reg rx_char_ready;
reg [ 7: 0] rx_data;
wire rx_in_process;
reg rx_overrun;
wire rx_rd_strobe_onset;
wire rxd_edge;
wire rxd_falling;
wire [ 10: 0] rxd_shift_reg;
wire sample_enable;
wire shift_reg_start_bit_n;
wire source_rxd;
wire stop_bit;
wire sync_rxd;
wire unused_start_bit;
wire [ 10: 0] unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_in;
reg [ 10: 0] unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out;
wasca_uart_0_rx_stimulus_source the_wasca_uart_0_rx_stimulus_source
(
.baud_divisor (baud_divisor),
.clk (clk),
.clk_en (clk_en),
.reset_n (reset_n),
.rx_char_ready (rx_char_ready),
.rxd (rxd),
.source_rxd (source_rxd)
);
altera_std_synchronizer the_altera_std_synchronizer
(
.clk (clk),
.din (source_rxd),
.dout (sync_rxd),
.reset_n (reset_n)
);
defparam the_altera_std_synchronizer.depth = 2;
//delayed_unxsync_rxdxx1, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
delayed_unxsync_rxdxx1 <= 0;
else if (clk_en)
delayed_unxsync_rxdxx1 <= sync_rxd;
end
assign rxd_falling = ~(sync_rxd) & (delayed_unxsync_rxdxx1);
//delayed_unxsync_rxdxx2, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
delayed_unxsync_rxdxx2 <= 0;
else if (clk_en)
delayed_unxsync_rxdxx2 <= sync_rxd;
end
assign rxd_edge = (sync_rxd) ^ (delayed_unxsync_rxdxx2);
assign rx_rd_strobe_onset = rx_rd_strobe && begintransfer;
assign half_bit_cell_divisor = baud_divisor[15 : 1];
assign baud_load_value = (rxd_edge)? half_bit_cell_divisor :
baud_divisor;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
baud_rate_counter <= 0;
else if (clk_en)
if (baud_rate_counter_is_zero || rxd_edge)
baud_rate_counter <= baud_load_value;
else
baud_rate_counter <= baud_rate_counter - 1;
end
assign baud_rate_counter_is_zero = baud_rate_counter == 0;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
baud_clk_en <= 0;
else if (clk_en)
if (rxd_edge)
baud_clk_en <= 0;
else
baud_clk_en <= baud_rate_counter_is_zero;
end
assign sample_enable = baud_clk_en && rx_in_process;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
do_start_rx <= 0;
else if (clk_en)
if (~rx_in_process && rxd_falling)
do_start_rx <= 1;
else
do_start_rx <= 0;
end
assign rx_in_process = shift_reg_start_bit_n;
assign {stop_bit,
parity_bit,
raw_data_in,
unused_start_bit} = rxd_shift_reg;
assign is_break = ~(|rxd_shift_reg);
assign is_framing_error = ~stop_bit && ~is_break;
//delayed_unxrx_in_processxx3, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
delayed_unxrx_in_processxx3 <= 0;
else if (clk_en)
delayed_unxrx_in_processxx3 <= rx_in_process;
end
assign got_new_char = ~(rx_in_process) & (delayed_unxrx_in_processxx3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
rx_data <= 0;
else if (got_new_char)
rx_data <= raw_data_in;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
framing_error <= 0;
else if (clk_en)
if (status_wr_strobe)
framing_error <= 0;
else if (got_new_char && is_framing_error)
framing_error <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
break_detect <= 0;
else if (clk_en)
if (status_wr_strobe)
break_detect <= 0;
else if (got_new_char && is_break)
break_detect <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
rx_overrun <= 0;
else if (clk_en)
if (status_wr_strobe)
rx_overrun <= 0;
else if (got_new_char && rx_char_ready)
rx_overrun <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
rx_char_ready <= 0;
else if (clk_en)
if (rx_rd_strobe_onset)
rx_char_ready <= 0;
else if (got_new_char)
rx_char_ready <= -1;
end
assign correct_parity = ~(^raw_data_in);
assign is_parity_error = (correct_parity != parity_bit) && ~is_break;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
parity_error <= 0;
else if (clk_en)
if (status_wr_strobe)
parity_error <= 0;
else if (got_new_char && is_parity_error)
parity_error <= -1;
end
//_reg, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out <= 0;
else if (clk_en)
unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out <= unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_in;
end
assign unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_in = (do_start_rx)? {11{1'b1}} :
(sample_enable)? {sync_rxd,
unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[10 : 1]} :
unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out;
assign rxd_shift_reg = unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out;
assign shift_reg_start_bit_n = unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[0];
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module wasca_uart_0_regs (
// inputs:
address,
break_detect,
chipselect,
clk,
clk_en,
framing_error,
parity_error,
read_n,
reset_n,
rx_char_ready,
rx_data,
rx_overrun,
tx_overrun,
tx_ready,
tx_shift_empty,
write_n,
writedata,
// outputs:
baud_divisor,
dataavailable,
do_force_break,
irq,
readdata,
readyfordata,
rx_rd_strobe,
status_wr_strobe,
tx_data,
tx_wr_strobe
)
;
output [ 15: 0] baud_divisor;
output dataavailable;
output do_force_break;
output irq;
output [ 15: 0] readdata;
output readyfordata;
output rx_rd_strobe;
output status_wr_strobe;
output [ 7: 0] tx_data;
output tx_wr_strobe;
input [ 2: 0] address;
input break_detect;
input chipselect;
input clk;
input clk_en;
input framing_error;
input parity_error;
input read_n;
input reset_n;
input rx_char_ready;
input [ 7: 0] rx_data;
input rx_overrun;
input tx_overrun;
input tx_ready;
input tx_shift_empty;
input write_n;
input [ 15: 0] writedata;
wire any_error;
reg [ 15: 0] baud_divisor;
reg [ 9: 0] control_reg;
wire control_wr_strobe;
wire cts_status_bit;
reg d1_rx_char_ready;
reg d1_tx_ready;
wire dataavailable;
wire dcts_status_bit;
reg delayed_unxtx_readyxx4;
wire [ 15: 0] divisor_constant;
wire divisor_wr_strobe;
wire do_force_break;
wire do_write_char;
wire eop_status_bit;
wire ie_any_error;
wire ie_break_detect;
wire ie_framing_error;
wire ie_parity_error;
wire ie_rx_char_ready;
wire ie_rx_overrun;
wire ie_tx_overrun;
wire ie_tx_ready;
wire ie_tx_shift_empty;
reg irq;
wire qualified_irq;
reg [ 15: 0] readdata;
wire readyfordata;
wire rx_rd_strobe;
wire [ 15: 0] selected_read_data;
wire [ 12: 0] status_reg;
wire status_wr_strobe;
reg [ 7: 0] tx_data;
wire tx_wr_strobe;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= selected_read_data;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
irq <= 0;
else if (clk_en)
irq <= qualified_irq;
end
assign rx_rd_strobe = chipselect && ~read_n && (address == 3'd0);
assign tx_wr_strobe = chipselect && ~write_n && (address == 3'd1);
assign status_wr_strobe = chipselect && ~write_n && (address == 3'd2);
assign control_wr_strobe = chipselect && ~write_n && (address == 3'd3);
assign divisor_wr_strobe = chipselect && ~write_n && (address == 3'd4);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
tx_data <= 0;
else if (tx_wr_strobe)
tx_data <= writedata[7 : 0];
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
control_reg <= 0;
else if (control_wr_strobe)
control_reg <= writedata[9 : 0];
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
baud_divisor <= divisor_constant;
else if (divisor_wr_strobe)
baud_divisor <= writedata[15 : 0];
end
assign cts_status_bit = 0;
assign dcts_status_bit = 0;
assign {do_force_break,
ie_any_error,
ie_rx_char_ready,
ie_tx_ready,
ie_tx_shift_empty,
ie_tx_overrun,
ie_rx_overrun,
ie_break_detect,
ie_framing_error,
ie_parity_error} = control_reg;
assign any_error = tx_overrun ||
rx_overrun ||
parity_error ||
framing_error ||
break_detect;
assign status_reg = {eop_status_bit,
cts_status_bit,
dcts_status_bit,
1'b0,
any_error,
rx_char_ready,
tx_ready,
tx_shift_empty,
tx_overrun,
rx_overrun,
break_detect,
framing_error,
parity_error};
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_rx_char_ready <= 0;
else if (clk_en)
d1_rx_char_ready <= rx_char_ready;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_tx_ready <= 0;
else if (clk_en)
d1_tx_ready <= tx_ready;
end
assign dataavailable = d1_rx_char_ready;
assign readyfordata = d1_tx_ready;
assign eop_status_bit = 1'b0;
assign selected_read_data = ({16 {(address == 3'd0)}} & rx_data) |
({16 {(address == 3'd1)}} & tx_data) |
({16 {(address == 3'd2)}} & status_reg) |
({16 {(address == 3'd3)}} & control_reg) |
({16 {(address == 3'd4)}} & baud_divisor);
assign qualified_irq = (ie_any_error && any_error ) ||
(ie_tx_shift_empty && tx_shift_empty ) ||
(ie_tx_overrun && tx_overrun ) ||
(ie_rx_overrun && rx_overrun ) ||
(ie_break_detect && break_detect ) ||
(ie_framing_error && framing_error ) ||
(ie_parity_error && parity_error ) ||
(ie_rx_char_ready && rx_char_ready ) ||
(ie_tx_ready && tx_ready );
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//delayed_unxtx_readyxx4, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
delayed_unxtx_readyxx4 <= 0;
else if (clk_en)
delayed_unxtx_readyxx4 <= tx_ready;
end
assign do_write_char = (tx_ready) & ~(delayed_unxtx_readyxx4);
always @(posedge clk)
begin
if (do_write_char)
$write("%c", tx_data);
end
assign divisor_constant = 4;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// assign divisor_constant = 980;
//synthesis read_comments_as_HDL off
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module wasca_uart_0 (
// inputs:
address,
begintransfer,
chipselect,
clk,
read_n,
reset_n,
rxd,
write_n,
writedata,
// outputs:
dataavailable,
irq,
readdata,
readyfordata,
txd
)
/* synthesis altera_attribute = "-name SYNCHRONIZER_IDENTIFICATION OFF" */ ;
output dataavailable;
output irq;
output [ 15: 0] readdata;
output readyfordata;
output txd;
input [ 2: 0] address;
input begintransfer;
input chipselect;
input clk;
input read_n;
input reset_n;
input rxd;
input write_n;
input [ 15: 0] writedata;
wire [ 15: 0] baud_divisor;
wire break_detect;
wire clk_en;
wire dataavailable;
wire do_force_break;
wire framing_error;
wire irq;
wire parity_error;
wire [ 15: 0] readdata;
wire readyfordata;
wire rx_char_ready;
wire [ 7: 0] rx_data;
wire rx_overrun;
wire rx_rd_strobe;
wire status_wr_strobe;
wire [ 7: 0] tx_data;
wire tx_overrun;
wire tx_ready;
wire tx_shift_empty;
wire tx_wr_strobe;
wire txd;
assign clk_en = 1;
wasca_uart_0_tx the_wasca_uart_0_tx
(
.baud_divisor (baud_divisor),
.begintransfer (begintransfer),
.clk (clk),
.clk_en (clk_en),
.do_force_break (do_force_break),
.reset_n (reset_n),
.status_wr_strobe (status_wr_strobe),
.tx_data (tx_data),
.tx_overrun (tx_overrun),
.tx_ready (tx_ready),
.tx_shift_empty (tx_shift_empty),
.tx_wr_strobe (tx_wr_strobe),
.txd (txd)
);
wasca_uart_0_rx the_wasca_uart_0_rx
(
.baud_divisor (baud_divisor),
.begintransfer (begintransfer),
.break_detect (break_detect),
.clk (clk),
.clk_en (clk_en),
.framing_error (framing_error),
.parity_error (parity_error),
.reset_n (reset_n),
.rx_char_ready (rx_char_ready),
.rx_data (rx_data),
.rx_overrun (rx_overrun),
.rx_rd_strobe (rx_rd_strobe),
.rxd (rxd),
.status_wr_strobe (status_wr_strobe)
);
wasca_uart_0_regs the_wasca_uart_0_regs
(
.address (address),
.baud_divisor (baud_divisor),
.break_detect (break_detect),
.chipselect (chipselect),
.clk (clk),
.clk_en (clk_en),
.dataavailable (dataavailable),
.do_force_break (do_force_break),
.framing_error (framing_error),
.irq (irq),
.parity_error (parity_error),
.read_n (read_n),
.readdata (readdata),
.readyfordata (readyfordata),
.reset_n (reset_n),
.rx_char_ready (rx_char_ready),
.rx_data (rx_data),
.rx_overrun (rx_overrun),
.rx_rd_strobe (rx_rd_strobe),
.status_wr_strobe (status_wr_strobe),
.tx_data (tx_data),
.tx_overrun (tx_overrun),
.tx_ready (tx_ready),
.tx_shift_empty (tx_shift_empty),
.tx_wr_strobe (tx_wr_strobe),
.write_n (write_n),
.writedata (writedata)
);
//s1, which is an e_avalon_slave
endmodule
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: fifo_69x256.v
// Megafunction Name(s):
// dcfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 7.2 Build 207 03/18/2008 SP 3 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2007 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module fifo_69x256 (
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrfull);
input [68:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [68:0] q;
output rdempty;
output wrfull;
wire sub_wire0;
wire sub_wire1;
wire [68:0] sub_wire2;
wire rdempty = sub_wire0;
wire wrfull = sub_wire1;
wire [68:0] q = sub_wire2[68:0];
dcfifo dcfifo_component (
.wrclk (wrclk),
.rdreq (rdreq),
.rdclk (rdclk),
.wrreq (wrreq),
.data (data),
.rdempty (sub_wire0),
.wrfull (sub_wire1),
.q (sub_wire2)
// synopsys translate_off
,
.aclr (),
.rdfull (),
.rdusedw (),
.wrempty (),
.wrusedw ()
// synopsys translate_on
);
defparam
dcfifo_component.intended_device_family = "Cyclone III",
dcfifo_component.lpm_numwords = 256,
dcfifo_component.lpm_showahead = "OFF",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 69,
dcfifo_component.lpm_widthu = 8,
dcfifo_component.overflow_checking = "OFF",
dcfifo_component.rdsync_delaypipe = 4,
dcfifo_component.underflow_checking = "OFF",
dcfifo_component.use_eab = "ON",
dcfifo_component.wrsync_delaypipe = 4;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "256"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "69"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "69"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "69"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "8"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: USED_PORT: data 0 0 69 0 INPUT NODEFVAL data[68..0]
// Retrieval info: USED_PORT: q 0 0 69 0 OUTPUT NODEFVAL q[68..0]
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
// Retrieval info: CONNECT: @data 0 0 69 0 data 0 0 69 0
// Retrieval info: CONNECT: q 0 0 69 0 @q 0 0 69 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_69x256.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_69x256.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_69x256.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_69x256.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_69x256_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_69x256_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_69x256_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_69x256_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
//Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2014.4 (lin64) Build 1071353 Tue Nov 18 16:47:07 MST 2014
//Date : Sun Apr 3 12:37:39 2016
//Host : ubuntu-desktop running 64-bit Ubuntu 14.04.4 LTS
//Command : generate_target design_1_wrapper.bd
//Design : design_1_wrapper
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module design_1_wrapper
(DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb);
inout [14:0]DDR_addr;
inout [2:0]DDR_ba;
inout DDR_cas_n;
inout DDR_ck_n;
inout DDR_ck_p;
inout DDR_cke;
inout DDR_cs_n;
inout [3:0]DDR_dm;
inout [31:0]DDR_dq;
inout [3:0]DDR_dqs_n;
inout [3:0]DDR_dqs_p;
inout DDR_odt;
inout DDR_ras_n;
inout DDR_reset_n;
inout DDR_we_n;
inout FIXED_IO_ddr_vrn;
inout FIXED_IO_ddr_vrp;
inout [53:0]FIXED_IO_mio;
inout FIXED_IO_ps_clk;
inout FIXED_IO_ps_porb;
inout FIXED_IO_ps_srstb;
wire [14:0]DDR_addr;
wire [2:0]DDR_ba;
wire DDR_cas_n;
wire DDR_ck_n;
wire DDR_ck_p;
wire DDR_cke;
wire DDR_cs_n;
wire [3:0]DDR_dm;
wire [31:0]DDR_dq;
wire [3:0]DDR_dqs_n;
wire [3:0]DDR_dqs_p;
wire DDR_odt;
wire DDR_ras_n;
wire DDR_reset_n;
wire DDR_we_n;
wire FIXED_IO_ddr_vrn;
wire FIXED_IO_ddr_vrp;
wire [53:0]FIXED_IO_mio;
wire FIXED_IO_ps_clk;
wire FIXED_IO_ps_porb;
wire FIXED_IO_ps_srstb;
design_1 design_1_i
(.DDR_addr(DDR_addr),
.DDR_ba(DDR_ba),
.DDR_cas_n(DDR_cas_n),
.DDR_ck_n(DDR_ck_n),
.DDR_ck_p(DDR_ck_p),
.DDR_cke(DDR_cke),
.DDR_cs_n(DDR_cs_n),
.DDR_dm(DDR_dm),
.DDR_dq(DDR_dq),
.DDR_dqs_n(DDR_dqs_n),
.DDR_dqs_p(DDR_dqs_p),
.DDR_odt(DDR_odt),
.DDR_ras_n(DDR_ras_n),
.DDR_reset_n(DDR_reset_n),
.DDR_we_n(DDR_we_n),
.FIXED_IO_ddr_vrn(FIXED_IO_ddr_vrn),
.FIXED_IO_ddr_vrp(FIXED_IO_ddr_vrp),
.FIXED_IO_mio(FIXED_IO_mio),
.FIXED_IO_ps_clk(FIXED_IO_ps_clk),
.FIXED_IO_ps_porb(FIXED_IO_ps_porb),
.FIXED_IO_ps_srstb(FIXED_IO_ps_srstb));
endmodule
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_protocol_converter:2.1
// IP Revision: 13
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module zqynq_lab_1_design_auto_pc_1 (
aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awregion,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arregion,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awprot,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arprot,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
input wire [11 : 0] s_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
input wire [7 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
input wire [2 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
input wire [1 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
input wire [0 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
input wire [3 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREGION" *)
input wire [3 : 0] s_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
input wire [3 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
input wire s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
output wire s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
input wire s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
input wire s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
output wire s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
output wire [11 : 0] s_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
output wire s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
input wire s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
input wire [11 : 0] s_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
input wire [7 : 0] s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
input wire [2 : 0] s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
input wire [1 : 0] s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
input wire [0 : 0] s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
input wire [3 : 0] s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREGION" *)
input wire [3 : 0] s_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
input wire [3 : 0] s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
input wire s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
output wire s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
output wire [11 : 0] s_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
output wire [31 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
output wire s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
output wire s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
input wire s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output wire [31 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output wire m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input wire m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [31 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
output wire [3 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output wire m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input wire m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input wire m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output wire m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
output wire [31 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
output wire [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
output wire m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
input wire m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
input wire [31 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input wire m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output wire m_axi_rready;
axi_protocol_converter_v2_1_13_axi_protocol_converter #(
.C_FAMILY("zynq"),
.C_M_AXI_PROTOCOL(2),
.C_S_AXI_PROTOCOL(0),
.C_IGNORE_ID(0),
.C_AXI_ID_WIDTH(12),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(32),
.C_AXI_SUPPORTS_WRITE(1),
.C_AXI_SUPPORTS_READ(1),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_TRANSLATION_MODE(2)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(s_axi_awid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awregion(s_axi_awregion),
.s_axi_awqos(s_axi_awqos),
.s_axi_awuser(1'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(12'H000),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wuser(1'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(s_axi_bid),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(s_axi_arid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arregion(s_axi_arregion),
.s_axi_arqos(s_axi_arqos),
.s_axi_aruser(1'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(s_axi_rid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(),
.m_axi_awqos(),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(12'H000),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(),
.m_axi_arqos(),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(12'H000),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(1'H1),
.m_axi_ruser(1'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A21BOI_BLACKBOX_V
`define SKY130_FD_SC_HS__A21BOI_BLACKBOX_V
/**
* a21boi: 2-input AND into first input of 2-input NOR,
* 2nd input inverted.
*
* Y = !((A1 & A2) | (!B1_N))
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__a21boi (
Y ,
A1 ,
A2 ,
B1_N
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A21BOI_BLACKBOX_V
|
// Remodified for the course: Application of FPGA by Prof. Chu and Prof. Chen
// Team mate: Wei cheng (³Ìΰ)
// Institution: Zhejiang University
// This module is designed for the course: Design of the digital system.
// Author: Pengwei Wu
// Teacher: Peiyong Zhang
// ״̬»úÄ£ÐͲÉÓÿα¾ËùÊöµÄÁ½¸ö״̬»úÀ´Íê³É¡£(ÆäʵҲ²»ËãÌرðµäÐ͵Ä״̬»úµÄ˵£©
// ´úÂëÃüÃû¹æÔò£ºÏ±ê½Ø¶Ïʽ¡£
// ´úÂëÃüÃû£º°´ÕÕSPARTAN-3AÊÖ²áÒý½Å¶¨ÒåʾÀýÎļþ£¨UCF-TEST)½øÐÐÃüÃû¡£
// Ò»ÇÐ×¢ÊÍÖÐûÓÐÌáµ½µÄÐÅÏ¢£¬»òÕßÊôÓÚ³£Ê¶ÐÔ֪ʶ£¬±ÈÈç¿ÉÒÔÔÚWIKIPEDIAÖÐÑ°ÕÒµ½¡£»òÕß¿ÉÒÔÔÚ¸½´øµÄPDFÎļþÖÐÕÒµ½¡£
// Èç¹ûÄã¿´µ½µÄ´úÂëÖÐûÓÐPDFÎļþ£¬Äã¿ÉÒÔÔÚÎÒµÄGITHUBÖ÷Ò³ÉÏÕÒµ½£ºÎÒµÄGITHUBÃû×ÖÊÇpwwu£¬»¶ÓFORK¡£
// You should not open this code in ISE
// chinese will not be supported
// ¼¸µã˵Ã÷£º´úÂë±¾ÉíÔÚÊä³öµÄʱºòʹÓÃÁËËø´æ¡£
module vga_sync
(
input wire clk, reset,
output wire hsync, vsync, video_on, p_tick,
// hysnc, vsync is the output sync signal
// ptick is used for other circuit such as the pixel generation circuit
output wire [9:0] pixel_x, pixel_y
// piexl_x and pixel_y output the counter of hsync and vsync
);
// constant declaration
// VGA 640-by-480 sync parameters
localparam HD = 640; // horizontal display area
localparam HF = 48 ; // h. front (left) border
localparam HB = 16 ; // h. back (right) border
localparam HR = 96 ; // h. retrace
localparam VD = 480; // vertical display area
localparam VF = 10; // v. front (top) border
localparam VB = 33; // v. back (bottom) border
localparam VR = 2; // v. retrace
// mod-2 counter
reg mod2_reg;
wire mod2_next;
// sync counters
reg [9:0] h_count_reg, h_count_next;
reg [9:0] v_count_reg, v_count_next;
// output buffer
reg v_sync_reg, h_sync_reg;
wire v_sync_next, h_sync_next;
// status signal
wire h_end, v_end, pixel_tick;
// First and foremost, let us make another clock.
// The clock information and any other information that can not be found in this document will be found in the pdf file
// converted from a md file.
// Or the information can be found in my Github pages: named ZJUPWWU
// mod-2 circuit to generate 25 MHz enable tick
assign mod2_next = ~mod2_reg;
assign pixel_tick = mod2_reg;
// clock finished
// state switch
always @(posedge clk, posedge reset)
if (reset)
begin
mod2_reg <= 1'b0;
v_count_reg <= 0;
h_count_reg <= 0;
v_sync_reg <= 1'b0;
h_sync_reg <= 1'b0;
end
else
// next is inputted to the state machine
begin
mod2_reg <= mod2_next;
v_count_reg <= v_count_next;
h_count_reg <= h_count_next;
v_sync_reg <= v_sync_next;
h_sync_reg <= h_sync_next;
end
// status signals
// end of horizontal counter (799)
// end of vertical counter (524)
assign h_end = (h_count_reg==(HD+HF+HB+HR-1));
assign v_end = (v_count_reg==(VD+VF+VB+VR-1));
// next-state logic of mod-800 horizontal sync counter
always @ (*)
if (pixel_tick) // 25 MHz pulse
if (h_end)
h_count_next = 0;
else
h_count_next = h_count_reg + 1;
else
h_count_next = h_count_reg;
// next-state logic of mod-525 vertical sync counter
always @ (*)
if (pixel_tick & h_end)
if (v_end)
v_count_next = 0;
else
v_count_next = v_count_reg + 1;
else
v_count_next = v_count_reg;
// horizontal and vertical sync, buffered to avoid glitch
// h_sync_next asserted between 656 and 751
assign h_sync_next = (h_count_reg>=(HD+HB) &&
h_count_reg<=(HD+HB+HR-1));
// vh_sync_next asserted between 490 and 491
assign v_sync_next = (v_count_reg>=(VD+VB) &&
v_count_reg<=(VD+VB+VR-1));
// video on/off
assign video_on = (h_count_reg<HD) && (v_count_reg<VD);
// output
assign hsync = h_sync_reg;
assign vsync = v_sync_reg;
assign pixel_x = h_count_reg;
assign pixel_y = v_count_reg;
assign p_tick = pixel_tick;
endmodule
|
//deps: alu.v, control.v, mem.v, pc_unit.v, register_unit.v, decoder.v, mmio.v, lr.v, dma_controller.v
`timescale 1ns/1ps
`include "cpu_constants.vh"
module core(input clk,input rst_n, output [7:0] LED, input rx, output tx,
output snd_out, output [3:0] snd_signals, input [3:0] switches,
output [31:0] dram_data_out,
output [23:0] dram_addr,
output dram_req_read,
output dram_req_write,
input [31:0] dram_data_in,
input dram_data_valid,
input dram_write_complete
);
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [15:0] SP_out; // From alu of alu.v
wire [7:0] alu_control; // From decoder of decoder.v
wire [3:0] condition; // From decoder of decoder.v
wire [`CONTROL_BIT_MAX:0] control_state; // From control of control.v
wire [15:0] data_out; // From mem of mem.v
wire en_mem; // From decoder of decoder.v
wire [3:0] flags_out; // From alu of alu.v
wire [15:0] immediate; // From decoder of decoder.v
wire mem_byte; // From decoder of decoder.v
wire [15:0] mem_data; // From alu of alu.v
wire mem_displacement; // From decoder of decoder.v
wire mem_wait; // From mem of mem.v
wire next_word; // From decoder of decoder.v
wire [15:0] alu_output; // From alu of alu.v
wire [15:0] pc_out; // From pc_unit of pc_unit.v
wire [2:0] rD_sel; // From decoder of decoder.v
wire [2:0] rS_sel; // From decoder of decoder.v
wire should_branch; // From alu of alu.v
wire alu_wr_en; // From alu of alu.v
wire en_immediate;
wire [15:0] rD_data;
wire [15:0] rS_data;
wire [15:0] pc_in;
wire [15:0] dec_immediate;
wire en_alu, en_pc, en_decoder, en_register;
wire [15:0] addr;
wire [15:0] mem_addr_out;
wire [15:0] rS_data_in, rD_data_in;
wire [15:0] data_in;
wire mem_enable, write_enable, byte_enable, byte_select;
wire mmio_enable;
wire reg_write_enable, rS_wr_en;
wire en;
wire rst;
wire [15:0] lr_in, lr_out;
wire lr_wr_en, alu_lr_wr_en;
wire lr_is_input, dec_lr_is_input;
wire [15:0] mmio_data_out;
wire mmio_serviced_read;
wire mmio_mem_wait;
wire mem_mem_wait;
wire [15:0] data_in2;
wire [15:0] addr2;
wire [15:0] data_out2;
wire write_enable2;
wire dma_status;
wire [1:0] pc_op;
reg [3:0] flags_in;
reg [15:0] instruction;
reg [15:0] mem_out_reg;
// End of automatics
alu alu(
// Outputs
.should_branch (should_branch),
.out (alu_output[15:0]),
.mem_data (mem_data[15:0]),
.write (alu_wr_en),
.flags_out (flags_out[3:0]),
.SP_out (SP_out[15:0]),
// Inputs
.clk (clk),
.en (en_alu),
.alu_control (alu_control[7:0]),
.en_imm (en_immediate),
.rD_data (rD_data[15:0]),
.rS_data (rS_data[15:0]),
.immediate (immediate[15:0]),
.condition (condition[3:0]),
.flags_in (flags_in[3:0]),
.mem_displacement (mem_displacement),
.lr_wr_en (alu_lr_wr_en));
control control(
// Outputs
.control_o (control_state[`CONTROL_BIT_MAX:0]),
.pc_op (pc_op[1:0]),
// Inputs
.clk (clk),
.en (en),
.rst (rst),
.en_mem (en_mem),
.mem_wait (mem_wait),
.should_branch (should_branch),
.imm (instruction[15]));
decoder decoder(
// Outputs
.alu_control (alu_control[7:0]),
.rD_sel (rD_sel[2:0]),
.rS_sel (rS_sel[2:0]),
.immediate (dec_immediate[15:0]),
.en_immediate (en_immediate),
.next_word (next_word),
.en_mem (en_mem),
.mem_displacement (mem_displacement),
.mem_byte (mem_byte),
.condition (condition[3:0]),
.lr_is_input (dec_lr_is_input),
// Inputs
.clk (clk),
.en (en_decoder),
.instruction (instruction[15:0]));
pc_unit pc_unit(
// Outputs
.pc_out (pc_out[15:0]),
// Inputs
.clk (clk),
.en (en_pc),
.rst (rst),
.pc_in (pc_in[15:0]),
.pc_op (pc_op[1:0]));
register_unit reg_unit(
// Outputs
.rD_data_out (rD_data[15:0]),
.rS_data_out (rS_data[15:0]),
// Inputs
.clk (clk),
.en (en_register),
.rst (rst),
.wr_en (reg_write_enable),
.rS_wr_en (rS_wr_en),
.rD_sel (rD_sel[2:0]),
.rS_sel (rS_sel[2:0]),
.rD_data_in (rD_data_in[15:0]),
.rS_data_in (rS_data_in[15:0]));
mem mem(
// Outputs
.data_out (data_out[15:0]),
.mem_wait (mem_mem_wait),
// Inputs
.clk (clk),
.rst (rst),
.en (mem_enable),
.write_enable (write_enable),
.byte_select (byte_select),
.byte_enable (byte_enable),
.addr (addr[15:0]),
.data_in (data_in[15:0]),
.write_enable2 (write_enable2),
.data_in2 (data_in2[15:0]),
.addr2 (addr2[15:0]),
.data_out2 (data_out2[15:0]));
//leds leds(
//.clk (clk),
//.en (en),
//.rst (rst),
//.wr_en (write_enable),
//.data (data_in[15:0]),
//.addr (addr[15:0]),
//.led_out (LED));
mmio mmio(
// Outputs
.data_out (mmio_data_out[15:0]),
.led_out (LED),
.serviced_read (mmio_serviced_read),
.tx (tx),
.snd_out (snd_out),
.snd_signals (snd_signals),
.mem_wait (mmio_mem_wait),
// Inputs
.clk (clk),
.rst (rst),
.en (mmio_enable),
.write_enable (write_enable),
.byte_select (byte_select),
.byte_enable (byte_enable),
.addr (addr[15:0]),
.data_in (data_in[15:0]),
.rx (rx),
.switches (switches),
.dma_status (dma_status));
dma_controller dma(
// Outputs
.ram_addr (addr2[15:0]),
.ram_data_out (data_in2[15:0]),
.ram_we (write_enable2),
.dma_status (dma_status),
// Inputs
.clk (clk),
.rst (rst),
.en (en),
.addr (addr[15:0]),
.data_in (data_in[15:0]),
.write_enable (write_enable),
.ram_data_in (data_out2[15:0]),
.dram_data_out (dram_data_out[31:0]),
.dram_addr (dram_addr[23:0]),
.dram_req_read (dram_req_read),
.dram_req_write (dram_req_write),
.dram_data_in (dram_data_in[31:0]),
.dram_data_valid (dram_data_valid),
.dram_write_complete (dram_write_complete)
);
lr lr(
// Outputs
.lr_out (lr_out[15:0]),
// Inputs
.clk (clk),
.rst (rst),
.wr_en (lr_wr_en),
.lr_in (lr_in[15:0]));
assign en_alu = control_state[`BIT_ALU];
assign en_decoder = control_state[`BIT_DECODE];
assign en_pc = control_state[`BIT_FETCH] | control_state[`BIT_REG_READ] | control_state[`BIT_REG_WR];
assign en_register = control_state[`BIT_REG_READ] | control_state[`BIT_REG_WR];
assign mem_enable = 1;
assign mmio_enable = control_state[`BIT_MEM];
assign write_enable = control_state[`BIT_MEM] &&
({1'b0,instruction[14:8]} == `OPC_ST ||
{1'b0,instruction[14:8]} == `OPC_PUSH ||
{1'b0,instruction[14:8]} == `OPC_PUSHLR);
assign reg_write_enable = control_state[`BIT_REG_WR] ? alu_wr_en : 0;
assign immediate = lr_is_input ? lr_out : (next_word ? data_out : dec_immediate);
assign rD_data_in = en_mem ? mem_out_reg : alu_output;
assign pc_in = alu_output;
assign mem_addr_out = control_state[`BIT_MEM]? alu_output : pc_out;
assign byte_select = mem_addr_out[0];
assign byte_enable = control_state[`BIT_MEM]? mem_byte : 0;
assign addr = {1'b0,mem_addr_out[15:1]};
assign rS_data_in = SP_out;
assign rS_wr_en = (instruction[14:8] == `OPC_PUSH ||
instruction[14:8] == `OPC_POP ||
instruction[14:8] == `OPC_PUSHLR)
&& control_state[`BIT_REG_WR]? 1 : 0;
assign data_in = mem_data;
assign en = rst_n; //! rst
assign rst = ~rst_n;
assign lr_in = pc_out;
assign lr_wr_en = control_state[`BIT_REG_WR] ? alu_lr_wr_en : 0;
assign lr_is_input = dec_lr_is_input && control_state[`BIT_ALU];
assign mem_wait = mem_mem_wait | mmio_mem_wait;
always @(posedge clk) begin
if (rst_n == 0)
flags_in <= 0;
else begin
if(control_state[`BIT_FETCH])
instruction <= data_out;
if(control_state[`BIT_DECODE])
flags_in <= flags_out;
end
end
always @(posedge clk) begin
mem_out_reg <= mmio_serviced_read ? mmio_data_out : data_out;
end
endmodule
|
(* Copyright (c) 2008-2012, Adam Chlipala
*
* This work is licensed under a
* Creative Commons Attribution-Noncommercial-No Derivative Works 3.0
* Unported License.
* The license text is available at:
* http://creativecommons.org/licenses/by-nc-nd/3.0/
*)
(* begin hide *)
Require Import List.
Require Import CpdtTactics.
Set Implicit Arguments.
(* Extra definitions to get coqdoc to choose the right fonts. *)
(* begin thide *)
Inductive unit := tt.
Inductive Empty_set := .
Inductive bool := true | false.
Inductive sum := .
Inductive prod := .
Inductive and := conj.
Inductive or := or_introl | or_intror.
Inductive ex := ex_intro.
Inductive eq := eq_refl.
Reset unit.
(* end thide *)
(* end hide *)
(** %\chapter{Inductive Predicates}% *)
(** The so-called %\index{Curry-Howard correspondence}``%#"#Curry-Howard correspondence#"#%''~\cite{Curry,Howard}% states a formal connection between functional programs and mathematical proofs. In the last chapter, we snuck in a first introduction to this subject in Coq. Witness the close similarity between the types [unit] and [True] from the standard library: *)
Print unit.
(** %\vspace{-.15in}%[[
Inductive unit : Set := tt : unit
]]
*)
Print True.
(** %\vspace{-.15in}%[[
Inductive True : Prop := I : True
]]
Recall that [unit] is the type with only one value, and [True] is the proposition that always holds. Despite this superficial difference between the two concepts, in both cases we can use the same inductive definition mechanism. The connection goes further than this. We see that we arrive at the definition of [True] by replacing [unit] by [True], [tt] by [I], and [Set] by [Prop]. The first two of these differences are superficial changes of names, while the third difference is the crucial one for separating programs from proofs. A term [T] of type [Set] is a type of programs, and a term of type [T] is a program. A term [T] of type [Prop] is a logical proposition, and its proofs are of type [T]. Chapter 12 goes into more detail about the theoretical differences between [Prop] and [Set]. For now, we will simply follow common intuitions about what a proof is.
The type [unit] has one value, [tt]. The type [True] has one proof, [I]. Why distinguish between these two types? Many people who have read about Curry-Howard in an abstract context but who have not put it to use in proof engineering answer that the two types in fact _should not_ be distinguished. There is a certain aesthetic appeal to this point of view, but I want to argue that it is best to treat Curry-Howard very loosely in practical proving. There are Coq-specific reasons for preferring the distinction, involving efficient compilation and avoidance of paradoxes in the presence of classical math, but I will argue that there is a more general principle that should lead us to avoid conflating programming and proving.
The essence of the argument is roughly this: to an engineer, not all functions of type [A -> B] are created equal, but all proofs of a proposition [P -> Q] are. This idea is known as%\index{proof irrelevance}% _proof irrelevance_, and its formalizations in logics prevent us from distinguishing between alternate proofs of the same proposition. Proof irrelevance is compatible with, but not derivable in, Gallina. Apart from this theoretical concern, I will argue that it is most effective to do engineering with Coq by employing different techniques for programs versus proofs. Most of this book is organized around that distinction, describing how to program, by applying standard functional programming techniques in the presence of dependent types; and how to prove, by writing custom Ltac decision procedures.
With that perspective in mind, this chapter is sort of a mirror image of the last chapter, introducing how to define predicates with inductive definitions. We will point out similarities in places, but much of the effective Coq user's bag of tricks is disjoint for predicates versus "datatypes." This chapter is also a covert introduction to dependent types, which are the foundation on which interesting inductive predicates are built, though we will rely on tactics to build dependently typed proof terms for us for now. A future chapter introduces more manual application of dependent types. *)
(** * Propositional Logic *)
(** Let us begin with a brief tour through the definitions of the connectives for propositional logic. We will work within a Coq section that provides us with a set of propositional variables. In Coq parlance, these are just variables of type [Prop]. *)
Section Propositional.
Variables P Q R : Prop.
(** In Coq, the most basic propositional connective is implication, written [->], which we have already used in almost every proof. Rather than being defined inductively, implication is built into Coq as the function type constructor.
We have also already seen the definition of [True]. For a demonstration of a lower-level way of establishing proofs of inductive predicates, we turn to this trivial theorem. *)
Theorem obvious : True.
(* begin thide *)
apply I.
(* end thide *)
Qed.
(** We may always use the [apply] tactic to take a proof step based on applying a particular constructor of the inductive predicate that we are trying to establish. Sometimes there is only one constructor that could possibly apply, in which case a shortcut is available:%\index{tactics!constructor}% *)
(* begin thide *)
Theorem obvious' : True.
constructor.
Qed.
(* end thide *)
(** There is also a predicate [False], which is the Curry-Howard mirror image of [Empty_set] from the last chapter. *)
Print False.
(** %\vspace{-.15in}%[[
Inductive False : Prop :=
]]
We can conclude anything from [False], doing case analysis on a proof of [False] in the same way we might do case analysis on, say, a natural number. Since there are no cases to consider, any such case analysis succeeds immediately in proving the goal. *)
Theorem False_imp : False -> 2 + 2 = 5.
(* begin thide *)
destruct 1.
(* end thide *)
Qed.
(** In a consistent context, we can never build a proof of [False]. In inconsistent contexts that appear in the courses of proofs, it is usually easiest to proceed by demonstrating the inconsistency with an explicit proof of [False]. *)
Theorem arith_neq : 2 + 2 = 5 -> 9 + 9 = 835.
(* begin thide *)
intro.
(** At this point, we have an inconsistent hypothesis [2 + 2 = 5], so the specific conclusion is not important. We use the %\index{tactics!elimtype}%[elimtype] tactic. For a full description of it, see the Coq manual. For our purposes, we only need the variant [elimtype False], which lets us replace any conclusion formula with [False], because any fact follows from an inconsistent context. *)
elimtype False.
(** [[
H : 2 + 2 = 5
============================
False
]]
For now, we will leave the details of this proof about arithmetic to [crush]. *)
crush.
(* end thide *)
Qed.
(** A related notion to [False] is logical negation. *)
(* begin hide *)
Definition foo := not.
(* end hide *)
Print not.
(** %\vspace{-.15in}% [[
not = fun A : Prop => A -> False
: Prop -> Prop
]]
We see that [not] is just shorthand for implication of [False]. We can use that fact explicitly in proofs. The syntax [~ P] %(written with a tilde in ASCII)% expands to [not P]. *)
Theorem arith_neq' : ~ (2 + 2 = 5).
(* begin thide *)
unfold not.
(** [[
============================
2 + 2 = 5 -> False
]]
*)
crush.
(* end thide *)
Qed.
(** We also have conjunction, which we introduced in the last chapter. *)
Print and.
(** %\vspace{-.15in}%[[
Inductive and (A : Prop) (B : Prop) : Prop := conj : A -> B -> A /\ B
]]
The interested reader can check that [and] has a Curry-Howard equivalent called %\index{Gallina terms!prod}%[prod], the type of pairs. However, it is generally most convenient to reason about conjunction using tactics. An explicit proof of commutativity of [and] illustrates the usual suspects for such tasks. The operator [/\] is an infix shorthand for [and]. *)
Theorem and_comm : P /\ Q -> Q /\ P.
(* begin thide *)
(** We start by case analysis on the proof of [P /\ Q]. *)
destruct 1.
(** [[
H : P
H0 : Q
============================
Q /\ P
]]
Every proof of a conjunction provides proofs for both conjuncts, so we get a single subgoal reflecting that. We can proceed by splitting this subgoal into a case for each conjunct of [Q /\ P].%\index{tactics!split}% *)
split.
(** [[
2 subgoals
H : P
H0 : Q
============================
Q
subgoal 2 is
P
]]
In each case, the conclusion is among our hypotheses, so the %\index{tactics!assumption}%[assumption] tactic finishes the process. *)
assumption.
assumption.
(* end thide *)
Qed.
(** Coq disjunction is called %\index{Gallina terms!or}%[or] and abbreviated with the infix operator [\/]. *)
Print or.
(** %\vspace{-.15in}%[[
Inductive or (A : Prop) (B : Prop) : Prop :=
or_introl : A -> A \/ B | or_intror : B -> A \/ B
]]
We see that there are two ways to prove a disjunction: prove the first disjunct or prove the second. The Curry-Howard analogue of this is the Coq %\index{Gallina terms!sum}%[sum] type. We can demonstrate the main tactics here with another proof of commutativity. *)
Theorem or_comm : P \/ Q -> Q \/ P.
(* begin thide *)
(** As in the proof for [and], we begin with case analysis, though this time we are met by two cases instead of one. *)
destruct 1.
(** [[
2 subgoals
H : P
============================
Q \/ P
subgoal 2 is
Q \/ P
]]
We can see that, in the first subgoal, we want to prove the disjunction by proving its second disjunct. The %\index{tactics!right}%[right] tactic telegraphs this intent. *)
right; assumption.
(** The second subgoal has a symmetric proof.%\index{tactics!left}%
[[
1 subgoal
H : Q
============================
Q \/ P
]]
*)
left; assumption.
(* end thide *)
Qed.
(* begin hide *)
(* In-class exercises *)
Theorem contra : P -> ~P -> R.
(* begin thide *)
unfold not.
intros.
elimtype False.
apply H0.
assumption.
(* end thide *)
Admitted.
Theorem and_assoc : (P /\ Q) /\ R -> P /\ (Q /\ R).
(* begin thide *)
intros.
destruct H.
destruct H.
split.
assumption.
split.
assumption.
assumption.
(* end thide *)
Admitted.
Theorem or_assoc : (P \/ Q) \/ R -> P \/ (Q \/ R).
(* begin thide *)
intros.
destruct H.
destruct H.
left.
assumption.
right.
left.
assumption.
right.
right.
assumption.
(* end thide *)
Admitted.
(* end hide *)
(** It would be a shame to have to plod manually through all proofs about propositional logic. Luckily, there is no need. One of the most basic Coq automation tactics is %\index{tactics!tauto}%[tauto], which is a complete decision procedure for constructive propositional logic. (More on what "constructive" means in the next section.) We can use [tauto] to dispatch all of the purely propositional theorems we have proved so far. *)
Theorem or_comm' : P \/ Q -> Q \/ P.
(* begin thide *)
tauto.
(* end thide *)
Qed.
(** Sometimes propositional reasoning forms important plumbing for the proof of a theorem, but we still need to apply some other smarts about, say, arithmetic. The tactic %\index{tactics!intuition}%[intuition] is a generalization of [tauto] that proves everything it can using propositional reasoning. When some further facts must be established to finish the proof, [intuition] uses propositional laws to simplify them as far as possible. Consider this example, which uses the list concatenation operator %\coqdocnotation{%#<tt>#++#</tt>#%}% from the standard library. *)
Theorem arith_comm : forall ls1 ls2 : list nat,
length ls1 = length ls2 \/ length ls1 + length ls2 = 6
-> length (ls1 ++ ls2) = 6 \/ length ls1 = length ls2.
(* begin thide *)
intuition.
(** A lot of the proof structure has been generated for us by [intuition], but the final proof depends on a fact about lists. The remaining subgoal hints at what cleverness we need to inject. *)
(** [[
ls1 : list nat
ls2 : list nat
H0 : length ls1 + length ls2 = 6
============================
length (ls1 ++ ls2) = 6 \/ length ls1 = length ls2
]]
We can see that we need a theorem about lengths of concatenated lists, which we proved last chapter and is also in the standard library. *)
rewrite app_length.
(** [[
ls1 : list nat
ls2 : list nat
H0 : length ls1 + length ls2 = 6
============================
length ls1 + length ls2 = 6 \/ length ls1 = length ls2
]]
Now the subgoal follows by purely propositional reasoning. That is, we could replace [length ls1 + length ls2 = 6] with [P] and [length ls1 = length ls2] with [Q] and arrive at a tautology of propositional logic. *)
tauto.
(* end thide *)
Qed.
(** The [intuition] tactic is one of the main bits of glue in the implementation of [crush], so, with a little help, we can get a short automated proof of the theorem. *)
(* begin thide *)
Theorem arith_comm' : forall ls1 ls2 : list nat,
length ls1 = length ls2 \/ length ls1 + length ls2 = 6
-> length (ls1 ++ ls2) = 6 \/ length ls1 = length ls2.
Hint Rewrite app_length.
crush.
Qed.
(* end thide *)
End Propositional.
(** Ending the section here has the same effect as always. Each of our propositional theorems becomes universally quantified over the propositional variables that we used. *)
(** * What Does It Mean to Be Constructive? *)
(** One potential point of confusion in the presentation so far is the distinction between [bool] and [Prop]. The datatype [bool] is built from two values [true] and [false], while [Prop] is a more primitive type that includes among its members [True] and [False]. Why not collapse these two concepts into one, and why must there be more than two states of mathematical truth, [True] and [False]?
The answer comes from the fact that Coq implements%\index{constructive logic}% _constructive_ or%\index{intuitionistic logic|see{constructive logic}}% _intuitionistic_ logic, in contrast to the%\index{classical logic}% _classical_ logic that you may be more familiar with. In constructive logic, classical tautologies like [~ ~ P -> P] and [P \/ ~ P] do not always hold. In general, we can only prove these tautologies when [P] is%\index{decidability}% _decidable_, in the sense of %\index{computability|see{decidability}}%computability theory. The Curry-Howard encoding that Coq uses for [or] allows us to extract either a proof of [P] or a proof of [~ P] from any proof of [P \/ ~ P]. Since our proofs are just functional programs which we can run, a general %\index{law of the excluded middle}%law of the excluded middle would give us a decision procedure for the halting problem, where the instantiations of [P] would be formulas like "this particular Turing machine halts."
A similar paradoxical situation would result if every proposition evaluated to either [True] or [False]. Evaluation in Coq is decidable, so we would be limiting ourselves to decidable propositions only.
Hence the distinction between [bool] and [Prop]. Programs of type [bool] are computational by construction; we can always run them to determine their results. Many [Prop]s are undecidable, and so we can write more expressive formulas with [Prop]s than with [bool]s, but the inevitable consequence is that we cannot simply "run a [Prop] to determine its truth."
Constructive logic lets us define all of the logical connectives in an aesthetically appealing way, with orthogonal inductive definitions. That is, each connective is defined independently using a simple, shared mechanism. Constructivity also enables a trick called%\index{program extraction}% _program extraction_, where we write programs by phrasing them as theorems to be proved. Since our proofs are just functional programs, we can extract executable programs from our final proofs, which we could not do as naturally with classical proofs.
We will see more about Coq's program extraction facility in a later chapter. However, I think it is worth interjecting another warning at this point, following up on the prior warning about taking the Curry-Howard correspondence too literally. It is possible to write programs by theorem-proving methods in Coq, but hardly anyone does it. It is almost always most useful to maintain the distinction between programs and proofs. If you write a program by proving a theorem, you are likely to run into algorithmic inefficiencies that you introduced in your proof to make it easier to prove. It is a shame to have to worry about such situations while proving tricky theorems, and it is a happy state of affairs that you almost certainly will not need to, with the ideal of extracting programs from proofs being confined mostly to theoretical studies. *)
(** * First-Order Logic *)
(** The %\index{Gallina terms!forall}%[forall] connective of first-order logic, which we have seen in many examples so far, is built into Coq. Getting ahead of ourselves a bit, we can see it as the dependent function type constructor. In fact, implication and universal quantification are just different syntactic shorthands for the same Coq mechanism. A formula [P -> Q] is equivalent to [forall x : P, Q], where [x] does not appear in [Q]. That is, the "real" type of the implication says "for every proof of [P], there exists a proof of [Q]."
%\index{existential quantification}\index{Gallina terms!exists}\index{Gallina terms!ex}%Existential quantification is defined in the standard library. *)
Print ex.
(** %\vspace{-.15in}%[[
Inductive ex (A : Type) (P : A -> Prop) : Prop :=
ex_intro : forall x : A, P x -> ex P
]]
(Note that here, as always, each [forall] quantifier has the largest possible scope, so that the type of [ex_intro] could also be written [forall x : A, (P x -> ex P)].)
The family [ex] is parameterized by the type [A] that we quantify over, and by a predicate [P] over [A]s. We prove an existential by exhibiting some [x] of type [A], along with a proof of [P x]. As usual, there are tactics that save us from worrying about the low-level details most of the time.
Here is an example of a theorem statement with existential quantification. We use the equality operator [=], which, depending on the settings in which they learned logic, different people will say either is or is not part of first-order logic. For our purposes, it is. *)
Theorem exist1 : exists x : nat, x + 1 = 2.
(* begin thide *)
(** remove printing exists *)
(** We can start this proof with a tactic %\index{tactics!exists}%[exists], which should not be confused with the formula constructor shorthand of the same name. %In the version of this document that you are reading, the reverse ``E'' appears instead of the text ``exists'' in formulas.% *)
exists 1.
(** The conclusion is replaced with a version using the existential witness that we announced.
[[
============================
1 + 1 = 2
]]
*)
reflexivity.
(* end thide *)
Qed.
(** printing exists $\exists$ *)
(** We can also use tactics to reason about existential hypotheses. *)
Theorem exist2 : forall n m : nat, (exists x : nat, n + x = m) -> n <= m.
(* begin thide *)
(** We start by case analysis on the proof of the existential fact. *)
destruct 1.
(** [[
n : nat
m : nat
x : nat
H : n + x = m
============================
n <= m
]]
The goal has been replaced by a form where there is a new free variable [x], and where we have a new hypothesis that the body of the existential holds with [x] substituted for the old bound variable. From here, the proof is just about arithmetic and is easy to automate. *)
crush.
(* end thide *)
Qed.
(* begin hide *)
(* In-class exercises *)
Theorem forall_exists_commute : forall (A B : Type) (P : A -> B -> Prop),
(exists x : A, forall y : B, P x y) -> (forall y : B, exists x : A, P x y).
(* begin thide *)
intros.
destruct H.
exists x.
apply H.
(* end thide *)
Admitted.
(* end hide *)
(** The tactic [intuition] has a first-order cousin called %\index{tactics!firstorder}%[firstorder], which proves many formulas when only first-order reasoning is needed, and it tries to perform first-order simplifications in any case. First-order reasoning is much harder than propositional reasoning, so [firstorder] is much more likely than [intuition] to get stuck in a way that makes it run for long enough to be useless. *)
(** * Predicates with Implicit Equality *)
(** We start our exploration of a more complicated class of predicates with a simple example: an alternative way of characterizing when a natural number is zero. *)
Inductive isZero : nat -> Prop :=
| IsZero : isZero 0.
Theorem isZero_zero : isZero 0.
(* begin thide *)
constructor.
(* end thide *)
Qed.
(** We can call [isZero] a%\index{judgment}% _judgment_, in the sense often used in the semantics of programming languages. Judgments are typically defined in the style of%\index{natural deduction}% _natural deduction_, where we write a number of%\index{inference rules}% _inference rules_ with premises appearing above a solid line and a conclusion appearing below the line. In this example, the sole constructor [IsZero] of [isZero] can be thought of as the single inference rule for deducing [isZero], with nothing above the line and [isZero 0] below it. The proof of [isZero_zero] demonstrates how we can apply an inference rule. (Readers not familiar with formal semantics should not worry about not following this paragraph!)
The definition of [isZero] differs in an important way from all of the other inductive definitions that we have seen in this and the previous chapter. Instead of writing just [Set] or [Prop] after the colon, here we write [nat -> Prop]. We saw examples of parameterized types like [list], but there the parameters appeared with names _before_ the colon. Every constructor of a parameterized inductive type must have a range type that uses the same parameter, whereas the form we use here enables us to choose different arguments to the type for different constructors.
For instance, our definition [isZero] makes the predicate provable only when the argument is [0]. We can see that the concept of equality is somehow implicit in the inductive definition mechanism. The way this is accomplished is similar to the way that logic variables are used in %\index{Prolog}%Prolog (but worry not if not familiar with Prolog), and it is a very powerful mechanism that forms a foundation for formalizing all of mathematics. In fact, though it is natural to think of inductive types as folding in the functionality of equality, in Coq, the true situation is reversed, with equality defined as just another inductive type!%\index{Gallina terms!eq}\index{Gallina terms!refl\_equal}% *)
Print eq.
(** %\vspace{-.15in}%[[
Inductive eq (A : Type) (x : A) : A -> Prop := eq_refl : x = x
]]
Behind the scenes, uses of infix [=] are expanded to instances of [eq]. We see that [eq] has both a parameter [x] that is fixed and an extra unnamed argument of the same type. The type of [eq] allows us to state any equalities, even those that are provably false. However, examining the type of equality's sole constructor [eq_refl], we see that we can only _prove_ equality when its two arguments are syntactically equal. This definition turns out to capture all of the basic properties of equality, and the equality-manipulating tactics that we have seen so far, like [reflexivity] and [rewrite], are implemented treating [eq] as just another inductive type with a well-chosen definition. Another way of stating that definition is: equality is defined as the least reflexive relation.
Returning to the example of [isZero], we can see how to work with hypotheses that use this predicate. *)
Theorem isZero_plus : forall n m : nat, isZero m -> n + m = n.
(* begin thide *)
(** We want to proceed by cases on the proof of the assumption about [isZero]. *)
destruct 1.
(** [[
n : nat
============================
n + 0 = n
]]
Since [isZero] has only one constructor, we are presented with only one subgoal. The argument [m] to [isZero] is replaced with that type's argument from the single constructor [IsZero]. From this point, the proof is trivial. *)
crush.
(* end thide *)
Qed.
(** Another example seems at first like it should admit an analogous proof, but in fact provides a demonstration of one of the most basic gotchas of Coq proving. *)
Theorem isZero_contra : isZero 1 -> False.
(* begin thide *)
(** Let us try a proof by cases on the assumption, as in the last proof. *)
destruct 1.
(** [[
============================
False
]]
It seems that case analysis has not helped us much at all! Our sole hypothesis disappears, leaving us, if anything, worse off than we were before. What went wrong? We have met an important restriction in tactics like [destruct] and [induction] when applied to types with arguments. If the arguments are not already free variables, they will be replaced by new free variables internally before doing the case analysis or induction. Since the argument [1] to [isZero] is replaced by a fresh variable, we lose the crucial fact that it is not equal to [0].
Why does Coq use this restriction? We will discuss the issue in detail in a future chapter, when we see the dependently typed programming techniques that would allow us to write this proof term manually. For now, we just say that the algorithmic problem of "logically complete case analysis" is undecidable when phrased in Coq's logic. A few tactics and design patterns that we will present in this chapter suffice in almost all cases. For the current example, what we want is a tactic called %\index{tactics!inversion}%[inversion], which corresponds to the concept of inversion that is frequently used with natural deduction proof systems. (Again, worry not if the semantics-oriented terminology from this last sentence is unfamiliar.) *)
Undo.
inversion 1.
(* end thide *)
Qed.
(** What does [inversion] do? Think of it as a version of [destruct] that does its best to take advantage of the structure of arguments to inductive types. In this case, [inversion] completed the proof immediately, because it was able to detect that we were using [isZero] with an impossible argument.
Sometimes using [destruct] when you should have used [inversion] can lead to confusing results. To illustrate, consider an alternate proof attempt for the last theorem. *)
Theorem isZero_contra' : isZero 1 -> 2 + 2 = 5.
destruct 1.
(** [[
============================
1 + 1 = 4
]]
What on earth happened here? Internally, [destruct] replaced [1] with a fresh variable, and, trying to be helpful, it also replaced the occurrence of [1] within the unary representation of each number in the goal. Then, within the [O] case of the proof, we replace the fresh variable with [O]. This has the net effect of decrementing each of these numbers. *)
Abort.
(** To see more clearly what is happening, we can consider the type of [isZero]'s induction principle. *)
Check isZero_ind.
(** %\vspace{-.15in}% [[
isZero_ind
: forall P : nat -> Prop, P 0 -> forall n : nat, isZero n -> P n
]]
In our last proof script, [destruct] chose to instantiate [P] as [fun n => S n + S n = S (S (S (S n)))]. You can verify for yourself that this specialization of the principle applies to the goal and that the hypothesis [P 0] then matches the subgoal we saw generated. If you are doing a proof and encounter a strange transmutation like this, there is a good chance that you should go back and replace a use of [destruct] with [inversion]. *)
(* begin hide *)
(* In-class exercises *)
(* EX: Define an inductive type capturing when a list has exactly two elements. Prove that your predicate does not hold of the empty list, and prove that, whenever it holds of a list, the length of that list is two. *)
(* begin thide *)
Section twoEls.
Variable A : Type.
Inductive twoEls : list A -> Prop :=
| TwoEls : forall x y, twoEls (x :: y :: nil).
Theorem twoEls_nil : twoEls nil -> False.
inversion 1.
Qed.
Theorem twoEls_two : forall ls, twoEls ls -> length ls = 2.
inversion 1.
reflexivity.
Qed.
End twoEls.
(* end thide *)
(* end hide *)
(** * Recursive Predicates *)
(** We have already seen all of the ingredients we need to build interesting recursive predicates, like this predicate capturing even-ness. *)
Inductive even : nat -> Prop :=
| EvenO : even O
| EvenSS : forall n, even n -> even (S (S n)).
(** Think of [even] as another judgment defined by natural deduction rules. The rule [EvenO] has nothing above the line and [even O] below the line, and [EvenSS] is a rule with [even n] above the line and [even (S (S n))] below.
The proof techniques of the last section are easily adapted. *)
Theorem even_0 : even 0.
(* begin thide *)
constructor.
(* end thide *)
Qed.
Theorem even_4 : even 4.
(* begin thide *)
constructor; constructor; constructor.
(* end thide *)
Qed.
(** It is not hard to see that sequences of constructor applications like the above can get tedious. We can avoid them using Coq's hint facility, with a new [Hint] variant that asks to consider all constructors of an inductive type during proof search. The tactic %\index{tactics!auto}%[auto] performs exhaustive proof search up to a fixed depth, considering only the proof steps we have registered as hints. *)
(* begin thide *)
Hint Constructors even.
Theorem even_4' : even 4.
auto.
Qed.
(* end thide *)
(** We may also use [inversion] with [even]. *)
Theorem even_1_contra : even 1 -> False.
(* begin thide *)
inversion 1.
(* end thide *)
Qed.
Theorem even_3_contra : even 3 -> False.
(* begin thide *)
inversion 1.
(** [[
H : even 3
n : nat
H1 : even 1
H0 : n = 1
============================
False
]]
The [inversion] tactic can be a little overzealous at times, as we can see here with the introduction of the unused variable [n] and an equality hypothesis about it. For more complicated predicates, though, adding such assumptions is critical to dealing with the undecidability of general inversion. More complex inductive definitions and theorems can cause [inversion] to generate equalities where neither side is a variable. *)
inversion H1.
(* end thide *)
Qed.
(** We can also do inductive proofs about [even]. *)
Theorem even_plus : forall n m, even n -> even m -> even (n + m).
(* begin thide *)
(** It seems a reasonable first choice to proceed by induction on [n]. *)
induction n; crush.
(** [[
n : nat
IHn : forall m : nat, even n -> even m -> even (n + m)
m : nat
H : even (S n)
H0 : even m
============================
even (S (n + m))
]]
We will need to use the hypotheses [H] and [H0] somehow. The most natural choice is to invert [H]. *)
inversion H.
(** [[
n : nat
IHn : forall m : nat, even n -> even m -> even (n + m)
m : nat
H : even (S n)
H0 : even m
n0 : nat
H2 : even n0
H1 : S n0 = n
============================
even (S (S n0 + m))
]]
Simplifying the conclusion brings us to a point where we can apply a constructor. *)
simpl.
(** [[
============================
even (S (S (n0 + m)))
]]
*)
constructor.
(** [[
============================
even (n0 + m)
]]
At this point, we would like to apply the inductive hypothesis, which is:
[[
IHn : forall m : nat, even n -> even m -> even (n + m)
]]
Unfortunately, the goal mentions [n0] where it would need to mention [n] to match [IHn]. We could keep looking for a way to finish this proof from here, but it turns out that we can make our lives much easier by changing our basic strategy. Instead of inducting on the structure of [n], we should induct _on the structure of one of the [even] proofs_. This technique is commonly called%\index{rule induction}% _rule induction_ in programming language semantics. In the setting of Coq, we have already seen how predicates are defined using the same inductive type mechanism as datatypes, so the fundamental unity of rule induction with "normal" induction is apparent.
Recall that tactics like [induction] and [destruct] may be passed numbers to refer to unnamed lefthand sides of implications in the conclusion, where the argument [n] refers to the [n]th such hypothesis. *)
Restart.
induction 1.
(** [[
m : nat
============================
even m -> even (0 + m)
]]
%\noindent \coqdockw{subgoal} 2 \coqdockw{is}:%#<tt>subgoal 2 is</tt>#
[[
even m -> even (S (S n) + m)
]]
The first case is easily discharged by [crush], based on the hint we added earlier to try the constructors of [even]. *)
crush.
(** Now we focus on the second case: *)
intro.
(** [[
m : nat
n : nat
H : even n
IHeven : even m -> even (n + m)
H0 : even m
============================
even (S (S n) + m)
]]
We simplify and apply a constructor, as in our last proof attempt. *)
simpl; constructor.
(** [[
============================
even (n + m)
]]
Now we have an exact match with our inductive hypothesis, and the remainder of the proof is trivial. *)
apply IHeven; assumption.
(** In fact, [crush] can handle all of the details of the proof once we declare the induction strategy. *)
Restart.
induction 1; crush.
(* end thide *)
Qed.
(** Induction on recursive predicates has similar pitfalls to those we encountered with inversion in the last section. *)
Theorem even_contra : forall n, even (S (n + n)) -> False.
(* begin thide *)
induction 1.
(** [[
n : nat
============================
False
]]
%\noindent \coqdockw{subgoal} 2 \coqdockw{is}:%#<tt>subgoal 2 is</tt>#
[[
False
]]
We are already sunk trying to prove the first subgoal, since the argument to [even] was replaced by a fresh variable internally. This time, we find it easier to prove this theorem by way of a lemma. Instead of trusting [induction] to replace expressions with fresh variables, we do it ourselves, explicitly adding the appropriate equalities as new assumptions. *)
Abort.
Lemma even_contra' : forall n', even n' -> forall n, n' = S (n + n) -> False.
induction 1; crush.
(** At this point, it is useful to consider all cases of [n] and [n0] being zero or nonzero. Only one of these cases has any trickiness to it. *)
destruct n; destruct n0; crush.
(** [[
n : nat
H : even (S n)
IHeven : forall n0 : nat, S n = S (n0 + n0) -> False
n0 : nat
H0 : S n = n0 + S n0
============================
False
]]
At this point it is useful to use a theorem from the standard library, which we also proved with a different name in the last chapter. We can search for a theorem that allows us to rewrite terms of the form [x + S y]. *)
SearchRewrite (_ + S _).
(** %\vspace{-.15in}%[[
plus_n_Sm : forall n m : nat, S (n + m) = n + S m
]]
*)
rewrite <- plus_n_Sm in H0.
(** The induction hypothesis lets us complete the proof, if we use a variant of [apply] that has a %\index{tactics!with}%[with] clause to give instantiations of quantified variables. *)
apply IHeven with n0; assumption.
(** As usual, we can rewrite the proof to avoid referencing any locally generated names, which makes our proof script more readable and more robust to changes in the theorem statement. We use the notation [<-] to request a hint that does right-to-left rewriting, just like we can with the [rewrite] tactic. *)
Restart.
Hint Rewrite <- plus_n_Sm.
induction 1; crush;
match goal with
| [ H : S ?N = ?N0 + ?N0 |- _ ] => destruct N; destruct N0
end; crush.
Qed.
(** We write the proof in a way that avoids the use of local variable or hypothesis names, using the %\index{tactics!match}%[match] tactic form to do pattern-matching on the goal. We use unification variables prefixed by question marks in the pattern, and we take advantage of the possibility to mention a unification variable twice in one pattern, to enforce equality between occurrences. The hint to rewrite with [plus_n_Sm] in a particular direction saves us from having to figure out the right place to apply that theorem.
The original theorem now follows trivially from our lemma, using a new tactic %\index{tactics!eauto}%[eauto], a fancier version of [auto] whose explanation we postpone to Chapter 13. *)
Theorem even_contra : forall n, even (S (n + n)) -> False.
intros; eapply even_contra'; eauto.
Qed.
(** We use a variant %\index{tactics!apply}%[eapply] of [apply] which has the same relationship to [apply] as [eauto] has to [auto]. An invocation of [apply] only succeeds if all arguments to the rule being used can be determined from the form of the goal, whereas [eapply] will introduce unification variables for undetermined arguments. In this case, [eauto] is able to determine the right values for those unification variables, using (unsurprisingly) a variant of the classic algorithm for _unification_ %\cite{unification}%.
By considering an alternate attempt at proving the lemma, we can see another common pitfall of inductive proofs in Coq. Imagine that we had tried to prove [even_contra'] with all of the [forall] quantifiers moved to the front of the lemma statement. *)
Lemma even_contra'' : forall n' n, even n' -> n' = S (n + n) -> False.
induction 1; crush;
match goal with
| [ H : S ?N = ?N0 + ?N0 |- _ ] => destruct N; destruct N0
end; crush.
(** One subgoal remains:
[[
n : nat
H : even (S (n + n))
IHeven : S (n + n) = S (S (S (n + n))) -> False
============================
False
]]
We are out of luck here. The inductive hypothesis is trivially true, since its assumption is false. In the version of this proof that succeeded, [IHeven] had an explicit quantification over [n]. This is because the quantification of [n] _appeared after the thing we are inducting on_ in the theorem statement. In general, quantified variables and hypotheses that appear before the induction object in the theorem statement stay fixed throughout the inductive proof. Variables and hypotheses that are quantified after the induction object may be varied explicitly in uses of inductive hypotheses. *)
Abort.
(** Why should Coq implement [induction] this way? One answer is that it avoids burdening this basic tactic with additional heuristic smarts, but that is not the whole picture. Imagine that [induction] analyzed dependencies among variables and reordered quantifiers to preserve as much freedom as possible in later uses of inductive hypotheses. This could make the inductive hypotheses more complex, which could in turn cause particular automation machinery to fail when it would have succeeded before. In general, we want to avoid quantifiers in our proofs whenever we can, and that goal is furthered by the refactoring that the [induction] tactic forces us to do. *)
(* end thide *)
(* begin hide *)
(* In-class exercises *)
(* EX: Define a type [prop] of simple Boolean formulas made up only of truth, falsehood, binary conjunction, and binary disjunction. Define an inductive predicate [holds] that captures when [prop]s are valid, and define a predicate [falseFree] that captures when a [prop] does not contain the "false" formula. Prove that every false-free [prop] is valid. *)
(* begin thide *)
Inductive prop : Set :=
| Tru : prop
| Fals : prop
| And : prop -> prop -> prop
| Or : prop -> prop -> prop.
Inductive holds : prop -> Prop :=
| HTru : holds Tru
| HAnd : forall p1 p2, holds p1 -> holds p2 -> holds (And p1 p2)
| HOr1 : forall p1 p2, holds p1 -> holds (Or p1 p2)
| HOr2 : forall p1 p2, holds p2 -> holds (Or p1 p2).
Inductive falseFree : prop -> Prop :=
| FFTru : falseFree Tru
| FFAnd : forall p1 p2, falseFree p1 -> falseFree p2 -> falseFree (And p1 p2)
| FFNot : forall p1 p2, falseFree p1 -> falseFree p2 -> falseFree (Or p1 p2).
Hint Constructors holds.
Theorem falseFree_holds : forall p, falseFree p -> holds p.
induction 1; crush.
Qed.
(* end thide *)
(* EX: Define an inductive type [prop'] that is the same as [prop] but omits the possibility for falsehood. Define a proposition [holds'] for [prop'] that is analogous to [holds]. Define a function [propify] for translating [prop']s to [prop]s. Prove that, for any [prop'] [p], if [propify p] is valid, then so is [p]. *)
(* begin thide *)
Inductive prop' : Set :=
| Tru' : prop'
| And' : prop' -> prop' -> prop'
| Or' : prop' -> prop' -> prop'.
Inductive holds' : prop' -> Prop :=
| HTru' : holds' Tru'
| HAnd' : forall p1 p2, holds' p1 -> holds' p2 -> holds' (And' p1 p2)
| HOr1' : forall p1 p2, holds' p1 -> holds' (Or' p1 p2)
| HOr2' : forall p1 p2, holds' p2 -> holds' (Or' p1 p2).
Fixpoint propify (p : prop') : prop :=
match p with
| Tru' => Tru
| And' p1 p2 => And (propify p1) (propify p2)
| Or' p1 p2 => Or (propify p1) (propify p2)
end.
Hint Constructors holds'.
Lemma propify_holds' : forall p', holds p' -> forall p, p' = propify p -> holds' p.
induction 1; crush; destruct p; crush.
Qed.
Theorem propify_holds : forall p, holds (propify p) -> holds' p.
intros; eapply propify_holds'; eauto.
Qed.
(* end thide *)
(* end hide *)
|
//======================================================================
//
// uart_core.v
// -----------
// A simple universal asynchronous receiver/transmitter (UART)
// interface. The interface contains 16 byte wide transmit and
// receivea buffers and can handle start and stop bits. But in
// general is rather simple. The primary purpose is as host
// interface for the coretest design. The core also has a
// loopback mode to allow testing of a serial link.
//
// Note that the UART has a separate API interface to allow
// a control core to change settings such as speed. But the core
// has default values to allow it to start operating directly
// after reset. No config should be needed.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2014, Secworks Sweden AB
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module uart_core(
input wire clk,
input wire reset_n,
// Configuration parameters
input wire [15 : 0] bit_rate,
input wire [3 : 0] data_bits,
input wire [1 : 0] stop_bits,
// External data interface
input wire rxd,
output wire txd,
// Internal receive interface.
output wire rxd_syn,
output [7 : 0] rxd_data,
input wire rxd_ack,
// Internal transmit interface.
input wire txd_syn,
input wire [7 : 0] txd_data,
output wire txd_ack
);
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
parameter ERX_IDLE = 0;
parameter ERX_START = 1;
parameter ERX_BITS = 2;
parameter ERX_STOP = 3;
parameter ERX_SYN = 4;
parameter ETX_IDLE = 0;
parameter ETX_ACK = 1;
parameter ETX_START = 2;
parameter ETX_BITS = 3;
parameter ETX_STOP = 4;
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
reg rxd_reg;
reg [7 : 0] rxd_byte_reg;
reg rxd_byte_we;
reg [4 : 0] rxd_bit_ctr_reg;
reg [4 : 0] rxd_bit_ctr_new;
reg rxd_bit_ctr_we;
reg rxd_bit_ctr_rst;
reg rxd_bit_ctr_inc;
reg [15 : 0] rxd_bitrate_ctr_reg;
reg [15 : 0] rxd_bitrate_ctr_new;
reg rxd_bitrate_ctr_we;
reg rxd_bitrate_ctr_rst;
reg rxd_bitrate_ctr_inc;
reg rxd_syn_reg;
reg rxd_syn_new;
reg rxd_syn_we;
reg [2 : 0] erx_ctrl_reg;
reg [2 : 0] erx_ctrl_new;
reg erx_ctrl_we;
reg txd_reg;
reg txd_new;
reg txd_we;
reg [7 : 0] txd_byte_reg;
reg [7 : 0] txd_byte_new;
reg txd_byte_we;
reg [4 : 0] txd_bit_ctr_reg;
reg [4 : 0] txd_bit_ctr_new;
reg txd_bit_ctr_we;
reg txd_bit_ctr_rst;
reg txd_bit_ctr_inc;
reg [15 : 0] txd_bitrate_ctr_reg;
reg [15 : 0] txd_bitrate_ctr_new;
reg txd_bitrate_ctr_we;
reg txd_bitrate_ctr_rst;
reg txd_bitrate_ctr_inc;
reg txd_ack_reg;
reg txd_ack_new;
reg txd_ack_we;
reg [2 : 0] etx_ctrl_reg;
reg [2 : 0] etx_ctrl_new;
reg etx_ctrl_we;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
wire [15 : 0] half_bit_rate;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign txd = txd_reg;
assign rxd_syn = rxd_syn_reg;
assign rxd_data = rxd_byte_reg;
assign txd_ack = txd_ack_reg;
assign half_bit_rate = {1'b0, bit_rate[15 : 1]};
//----------------------------------------------------------------
// reg_update
//
// Update functionality for all registers in the core.
// All registers are positive edge triggered with
// asynchronous active low reset.
//----------------------------------------------------------------
always @ (posedge clk or negedge reset_n)
begin: reg_update
if (!reset_n)
begin
rxd_reg <= 1'b0;
rxd_byte_reg <= 8'h0;
rxd_bit_ctr_reg <= 5'h0;
rxd_bitrate_ctr_reg <= 16'h0;
rxd_syn_reg <= 0;
erx_ctrl_reg <= ERX_IDLE;
txd_reg <= 1'b1;
txd_byte_reg <= 8'h0;
txd_bit_ctr_reg <= 5'h0;
txd_bitrate_ctr_reg <= 16'h0;
txd_ack_reg <= 1'b0;
etx_ctrl_reg <= ETX_IDLE;
end
else
begin
// We sample the rx input port every cycle.
rxd_reg <= rxd;
// We shift the rxd bit into msb.
if (rxd_byte_we)
begin
rxd_byte_reg <= {rxd_reg, rxd_byte_reg[7 : 1]};
end
if (rxd_bit_ctr_we)
begin
rxd_bit_ctr_reg <= rxd_bit_ctr_new;
end
if (rxd_bitrate_ctr_we)
begin
rxd_bitrate_ctr_reg <= rxd_bitrate_ctr_new;
end
if (rxd_syn_we)
begin
rxd_syn_reg <= rxd_syn_new;
end
if (erx_ctrl_we)
begin
erx_ctrl_reg <= erx_ctrl_new;
end
if (txd_we)
begin
txd_reg <= txd_new;
end
if (txd_byte_we)
begin
txd_byte_reg <= txd_byte_new;
end
if (txd_bit_ctr_we)
begin
txd_bit_ctr_reg <= txd_bit_ctr_new;
end
if (txd_bitrate_ctr_we)
begin
txd_bitrate_ctr_reg <= txd_bitrate_ctr_new;
end
if (txd_ack_we)
begin
txd_ack_reg <= txd_ack_new;
end
if (etx_ctrl_we)
begin
etx_ctrl_reg <= etx_ctrl_new;
end
end
end // reg_update
//----------------------------------------------------------------
// rxd_bit_ctr
//
// Bit counter for receiving data on the external
// serial interface.
//----------------------------------------------------------------
always @*
begin: rxd_bit_ctr
rxd_bit_ctr_new = 5'h0;
rxd_bit_ctr_we = 1'b0;
if (rxd_bit_ctr_rst)
begin
rxd_bit_ctr_new = 5'h0;
rxd_bit_ctr_we = 1'b1;
end
else if (rxd_bit_ctr_inc)
begin
rxd_bit_ctr_new = rxd_bit_ctr_reg + 4'b0001;
rxd_bit_ctr_we = 1'b1;
end
end // rxd_bit_ctr
//----------------------------------------------------------------
// rxd_bitrate_ctr
//
// Bitrate counter for receiving data on the external
// serial interface.
//----------------------------------------------------------------
always @*
begin: rxd_bitrate_ctr
rxd_bitrate_ctr_new = 16'h0;
rxd_bitrate_ctr_we = 1'b0;
if (rxd_bitrate_ctr_rst)
begin
rxd_bitrate_ctr_new = 16'h0;
rxd_bitrate_ctr_we = 1'b1;
end
else if (rxd_bitrate_ctr_inc)
begin
rxd_bitrate_ctr_new = rxd_bitrate_ctr_reg + 16'h0001;
rxd_bitrate_ctr_we = 1'b1;
end
end // rxd_bitrate_ctr
//----------------------------------------------------------------
// txd_bit_ctr
//
// Bit counter for transmitting data on the external
// serial interface.
//----------------------------------------------------------------
always @*
begin: txd_bit_ctr
txd_bit_ctr_new = 5'h0;
txd_bit_ctr_we = 1'b0;
if (txd_bit_ctr_rst)
begin
txd_bit_ctr_new = 5'h0;
txd_bit_ctr_we = 1'b1;
end
else if (txd_bit_ctr_inc)
begin
txd_bit_ctr_new = txd_bit_ctr_reg + 4'b0001;
txd_bit_ctr_we = 1'b1;
end
end // txd_bit_ctr
//----------------------------------------------------------------
// txd_bitrate_ctr
//
// Bitrate counter for transmitting data on the external
// serial interface.
//----------------------------------------------------------------
always @*
begin: txd_bitrate_ctr
txd_bitrate_ctr_new = 16'h0000;
txd_bitrate_ctr_we = 0;
if (txd_bitrate_ctr_rst)
begin
txd_bitrate_ctr_new = 16'h0000;
txd_bitrate_ctr_we = 1;
end
else if (txd_bitrate_ctr_inc)
begin
txd_bitrate_ctr_new = txd_bitrate_ctr_reg + 16'h0001;
txd_bitrate_ctr_we = 1;
end
end // txd_bitrate_ctr
//----------------------------------------------------------------
// external_rx_engine
//
// Logic that implements the receive engine towards
// the external interface. Detects incoming data, collects it,
// if required checks parity and store correct data into
// the rx buffer.
//----------------------------------------------------------------
always @*
begin: external_rx_engine
rxd_bit_ctr_rst = 0;
rxd_bit_ctr_inc = 0;
rxd_bitrate_ctr_rst = 0;
rxd_bitrate_ctr_inc = 0;
rxd_byte_we = 0;
rxd_syn_new = 0;
rxd_syn_we = 0;
erx_ctrl_new = ERX_IDLE;
erx_ctrl_we = 0;
case (erx_ctrl_reg)
ERX_IDLE:
begin
if (!rxd_reg)
begin
// Possible start bit detected.
rxd_bitrate_ctr_rst = 1;
erx_ctrl_new = ERX_START;
erx_ctrl_we = 1;
end
end
ERX_START:
begin
rxd_bitrate_ctr_inc = 1;
if (rxd_reg)
begin
// Just a glitch.
erx_ctrl_new = ERX_IDLE;
erx_ctrl_we = 1;
end
else
begin
if (rxd_bitrate_ctr_reg == half_bit_rate)
begin
// start bit assumed. We start sampling data.
rxd_bit_ctr_rst = 1;
rxd_bitrate_ctr_rst = 1;
erx_ctrl_new = ERX_BITS;
erx_ctrl_we = 1;
end
end
end
ERX_BITS:
begin
if (rxd_bitrate_ctr_reg < bit_rate)
begin
rxd_bitrate_ctr_inc = 1;
end
else
begin
rxd_byte_we = 1;
rxd_bit_ctr_inc = 1;
rxd_bitrate_ctr_rst = 1;
if (rxd_bit_ctr_reg == data_bits - 1)
begin
erx_ctrl_new = ERX_STOP;
erx_ctrl_we = 1;
end
end
end
ERX_STOP:
begin
rxd_bitrate_ctr_inc = 1;
if (rxd_bitrate_ctr_reg == bit_rate * stop_bits)
begin
rxd_syn_new = 1;
rxd_syn_we = 1;
erx_ctrl_new = ERX_SYN;
erx_ctrl_we = 1;
end
end
ERX_SYN:
begin
if (rxd_ack)
begin
rxd_syn_new = 0;
rxd_syn_we = 1;
erx_ctrl_new = ERX_IDLE;
erx_ctrl_we = 1;
end
end
default:
begin
end
endcase // case (erx_ctrl_reg)
end // external_rx_engine
//----------------------------------------------------------------
// external_tx_engine
//
// Logic that implements the transmit engine towards
// the external interface.
//----------------------------------------------------------------
always @*
begin: external_tx_engine
txd_new = 0;
txd_we = 0;
txd_byte_new = 0;
txd_byte_we = 0;
txd_bit_ctr_rst = 0;
txd_bit_ctr_inc = 0;
txd_bitrate_ctr_rst = 0;
txd_bitrate_ctr_inc = 0;
txd_ack_new = 0;
txd_ack_we = 0;
etx_ctrl_new = ETX_IDLE;
etx_ctrl_we = 0;
case (etx_ctrl_reg)
ETX_IDLE:
begin
txd_new = 1;
txd_we = 1;
if (txd_syn)
begin
txd_byte_new = txd_data;
txd_byte_we = 1;
txd_ack_new = 1;
txd_ack_we = 1;
txd_bitrate_ctr_rst = 1;
etx_ctrl_new = ETX_ACK;
etx_ctrl_we = 1;
end
end
ETX_ACK:
begin
if (!txd_syn)
begin
txd_new = 0;
txd_we = 1;
txd_ack_new = 0;
txd_ack_we = 1;
etx_ctrl_new = ETX_START;
etx_ctrl_we = 1;
end
end
ETX_START:
begin
if (txd_bitrate_ctr_reg == bit_rate)
begin
txd_bit_ctr_rst = 1;
etx_ctrl_new = ETX_BITS;
etx_ctrl_we = 1;
end
else
begin
txd_bitrate_ctr_inc = 1;
end
end
ETX_BITS:
begin
if (txd_bitrate_ctr_reg < bit_rate)
begin
txd_bitrate_ctr_inc = 1;
end
else
begin
txd_bitrate_ctr_rst = 1;
if (txd_bit_ctr_reg == data_bits)
begin
txd_new = 1;
txd_we = 1;
etx_ctrl_new = ETX_STOP;
etx_ctrl_we = 1;
end
else
begin
txd_new = txd_byte_reg[txd_bit_ctr_reg];
txd_we = 1;
txd_bit_ctr_inc = 1;
end
end
end
ETX_STOP:
begin
txd_bitrate_ctr_inc = 1;
if (txd_bitrate_ctr_reg == bit_rate * stop_bits)
begin
etx_ctrl_new = ETX_IDLE;
etx_ctrl_we = 1;
end
end
default:
begin
end
endcase // case (etx_ctrl_reg)
end // external_tx_engine
endmodule // uart
//======================================================================
// EOF uart.v
//======================================================================
|
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: pll.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.4 Build 182 03/12/2014 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module pll (
inclk0,
c0,
c1,
locked);
input inclk0;
output c0;
output c1;
output locked;
wire [4:0] sub_wire0;
wire sub_wire2;
wire [0:0] sub_wire6 = 1'h0;
wire [0:0] sub_wire3 = sub_wire0[0:0];
wire [1:1] sub_wire1 = sub_wire0[1:1];
wire c1 = sub_wire1;
wire locked = sub_wire2;
wire c0 = sub_wire3;
wire sub_wire4 = inclk0;
wire [1:0] sub_wire5 = {sub_wire6, sub_wire4};
altpll altpll_component (
.inclk (sub_wire5),
.clk (sub_wire0),
.locked (sub_wire2),
.activeclock (),
.areset (1'b0),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 9,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 32,
altpll_component.clk0_phase_shift = "0",
altpll_component.clk1_divide_by = 9,
altpll_component.clk1_duty_cycle = 50,
altpll_component.clk1_multiply_by = 32,
altpll_component.clk1_phase_shift = "-1736",
altpll_component.inclk0_input_frequency = 37037,
altpll_component.intended_device_family = "Cyclone III",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NO_COMPENSATION",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_UNUSED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_USED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_USED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.self_reset_on_loss_lock = "ON",
altpll_component.width_clock = 5;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "1"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "96.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "96.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "1"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "10000"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "0"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "50.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "96.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "96.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "-60.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "1"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "9"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "32"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "9"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "32"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "-1736"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NO_COMPENSATION"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "ON"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON
|
//lpm_divide CBX_SINGLE_OUTPUT_FILE="ON" LPM_DREPRESENTATION="UNSIGNED" LPM_HINT="MAXIMIZE_SPEED=6,LPM_REMAINDERPOSITIVE=TRUE" LPM_NREPRESENTATION="UNSIGNED" LPM_PIPELINE=5 LPM_TYPE="LPM_DIVIDE" LPM_WIDTHD=2 LPM_WIDTHN=64 clken clock denom numer quotient remain
//VERSION_BEGIN 16.0 cbx_mgl 2016:07:21:01:49:21:SJ cbx_stratixii 2016:07:21:01:48:16:SJ cbx_util_mgl 2016:07:21:01:48:16:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
// Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, the Altera Quartus Prime License Agreement,
// the Altera MegaCore Function License Agreement, or other
// applicable license agreement, including, without limitation,
// that your use is for the sole purpose of programming logic
// devices manufactured by Altera and sold by Altera or its
// authorized distributors. Please refer to the applicable
// agreement for further details.
//synthesis_resources = lpm_divide 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module mg2ko
(
clken,
clock,
denom,
numer,
quotient,
remain) /* synthesis synthesis_clearbox=1 */;
input clken;
input clock;
input [1:0] denom;
input [63:0] numer;
output [63:0] quotient;
output [1:0] remain;
wire [63:0] wire_mgl_prim1_quotient;
wire [1:0] wire_mgl_prim1_remain;
lpm_divide mgl_prim1
(
.clken(clken),
.clock(clock),
.denom(denom),
.numer(numer),
.quotient(wire_mgl_prim1_quotient),
.remain(wire_mgl_prim1_remain));
defparam
mgl_prim1.lpm_drepresentation = "UNSIGNED",
mgl_prim1.lpm_nrepresentation = "UNSIGNED",
mgl_prim1.lpm_pipeline = 5,
mgl_prim1.lpm_type = "LPM_DIVIDE",
mgl_prim1.lpm_widthd = 2,
mgl_prim1.lpm_widthn = 64,
mgl_prim1.lpm_hint = "MAXIMIZE_SPEED=6,LPM_REMAINDERPOSITIVE=TRUE";
assign
quotient = wire_mgl_prim1_quotient,
remain = wire_mgl_prim1_remain;
endmodule //mg2ko
//VALID FILE
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDFRBP_FUNCTIONAL_V
`define SKY130_FD_SC_HVL__SDFRBP_FUNCTIONAL_V
/**
* sdfrbp: Scan delay flop, inverted reset, non-inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_hvl__udp_mux_2to1.v"
`include "../../models/udp_dff_pr/sky130_fd_sc_hvl__udp_dff_pr.v"
`celldefine
module sky130_fd_sc_hvl__sdfrbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Local signals
wire buf_Q ;
wire RESET ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_hvl__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_hvl__udp_dff$PR `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, RESET);
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDFRBP_FUNCTIONAL_V
|
module Timer(clk_i, signal_i, second_o);
input clk_i;
input [2:0] signal_i;
output [31:0] second_o;
reg [31:0] counter;
reg [1:0] state;
reg [31:0] second;
assign second_o = second;
`define SSTOP 2'b00
`define SSTART 2'b01
`define SPAUSE 2'b10
initial begin
state = `SSTOP;
counter = 0;
second = 0;
end
`define K0 3'b100
`define K1 3'b101
`define K2 3'b110
`define K3 3'b111
// `define CLKRATE 32'd500000
`define CLKRATE 32'd25000
always@(negedge clk_i) begin
case (state)
`SSTOP: begin
case (signal_i)
`K3: begin
state <= `SSTART;
end
endcase
end
`SSTART: begin
if (counter == `CLKRATE) begin
counter <= 1;
second <= second + 1;
end else begin
counter <= counter + 1;
end
case (signal_i)
`K1: begin
state <= `SSTOP;
counter <= 0;
second <= 0;
end
`K3: begin
state <= `SPAUSE;
end
endcase
end
`SPAUSE: begin
case (signal_i)
`K1: begin
state <= `SSTOP;
counter <= 0;
second <= 0;
end
`K3: begin
state <= `SSTART;
end
endcase
end
endcase
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SEDFXBP_BEHAVIORAL_V
`define SKY130_FD_SC_LS__SEDFXBP_BEHAVIORAL_V
/**
* sedfxbp: Scan delay flop, data enable, non-inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_ls__udp_mux_2to1.v"
`include "../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_ls__udp_dff_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ls__sedfxbp (
Q ,
Q_N,
CLK,
D ,
DE ,
SCD,
SCE
);
// Module ports
output Q ;
output Q_N;
input CLK;
input D ;
input DE ;
input SCD;
input SCE;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
reg notifier ;
wire D_delayed ;
wire DE_delayed ;
wire SCD_delayed;
wire SCE_delayed;
wire CLK_delayed;
wire mux_out ;
wire de_d ;
wire awake ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
// Name Output Other arguments
sky130_fd_sc_ls__udp_mux_2to1 mux_2to10 (mux_out, de_d, SCD_delayed, SCE_delayed );
sky130_fd_sc_ls__udp_mux_2to1 mux_2to11 (de_d , buf_Q, D_delayed, DE_delayed );
sky130_fd_sc_ls__udp_dff$P_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond1 = ( awake && ( SCE_delayed === 1'b0 ) && ( DE_delayed === 1'b1 ) );
assign cond2 = ( awake && ( SCE_delayed === 1'b1 ) );
assign cond3 = ( awake && ( DE_delayed === 1'b1 ) && ( D_delayed !== SCD_delayed ) );
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__SEDFXBP_BEHAVIORAL_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: AGH UST
// Engineer: Wojciech Gredel, Hubert Górowski
//
// Create Date:
// Design Name:
// Module Name: MarioFontRom
// Project Name: DOS_Mario
// Target Devices: Basys3
// Tool versions: Vivado 2016.1
// Description:
// This module contains fonts
// - 8-by-16 (8-by-2^4) font
// - 20 characters (only necessary)
//
// Dependencies:
//
// Revision:
// Revision 0.01 - Module created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module MarioFontRom(
input wire [11:0] addr, // {char_code[7:0], char_line[3:0]}
output reg [7:0] char_line_pixels // pixels of the character line
);
// signal declaration
reg [7:0] data;
// body
always @(*)
char_line_pixels = data;
always @*
case (addr)
//code x00
12'h000: data = 8'b00000000; //
12'h001: data = 8'b00000000; // *****
12'h002: data = 8'b01111100; // ** **
12'h003: data = 8'b11000110; // ** **
12'h004: data = 8'b11000110; // ** ***
12'h005: data = 8'b11001110; // ** ****
12'h006: data = 8'b11011110; // **** **
12'h007: data = 8'b11110110; // *** **
12'h008: data = 8'b11100110; // ** **
12'h009: data = 8'b11000110; // ** **
12'h00a: data = 8'b11000110; // *****
12'h00b: data = 8'b01111100; //
12'h00c: data = 8'b00000000; //
12'h00d: data = 8'b00000000; //
12'h00e: data = 8'b00000000; //
12'h00f: data = 8'b00000000; //
//code x01
12'h010: data = 8'b00000000; //
12'h011: data = 8'b00000000; //
12'h012: data = 8'b00011000; //
12'h013: data = 8'b00111000; //
12'h014: data = 8'b01111000; // **
12'h015: data = 8'b00011000; // ***
12'h016: data = 8'b00011000; // ****
12'h017: data = 8'b00011000; // **
12'h018: data = 8'b00011000; // **
12'h019: data = 8'b00011000; // **
12'h01a: data = 8'b00011000; // **
12'h01b: data = 8'b00011000; // **
12'h01c: data = 8'b00011000; // **
12'h01d: data = 8'b00000000; // ******
12'h01e: data = 8'b00000000; //
12'h01f: data = 8'b00000000; //
//code x02
12'h020: data = 8'b00000000; //
12'h021: data = 8'b00000000; //
12'h022: data = 8'b01111100; // *****
12'h023: data = 8'b11000110; // ** **
12'h024: data = 8'b00000110; // **
12'h025: data = 8'b00001100; // **
12'h026: data = 8'b00011000; // **
12'h027: data = 8'b00110000; // **
12'h028: data = 8'b01100000; // **
12'h029: data = 8'b11000000; // **
12'h02a: data = 8'b11000110; // ** **
12'h02b: data = 8'b11111110; // *******
12'h02c: data = 8'b00000000; //
12'h02d: data = 8'b00000000; //
12'h02e: data = 8'b00000000; //
12'h02f: data = 8'b00000000; //
//code x03
12'h030: data = 8'b00000000; //
12'h031: data = 8'b00000000; //
12'h032: data = 8'b01111100; // *****
12'h033: data = 8'b11000110; // ** **
12'h034: data = 8'b00000110; // **
12'h035: data = 8'b00000110; // **
12'h036: data = 8'b00111100; // ****
12'h037: data = 8'b00000110; // **
12'h038: data = 8'b00000110; // **
12'h039: data = 8'b00000110; // **
12'h03a: data = 8'b11000110; // ** **
12'h03b: data = 8'b01111100; // *****
12'h03c: data = 8'b00000000; //
12'h03d: data = 8'b00000000; //
12'h03e: data = 8'b00000000; //
12'h03f: data = 8'b00000000; //
//code x04
12'h040: data = 8'b00000000; //
12'h041: data = 8'b00000000; //
12'h042: data = 8'b00001100; // **
12'h043: data = 8'b00011100; // ***
12'h044: data = 8'b00111100; // ****
12'h045: data = 8'b01101100; // ** **
12'h046: data = 8'b11001100; // ** **
12'h047: data = 8'b11111110; // *******
12'h048: data = 8'b00001100; // **
12'h049: data = 8'b00001100; // **
12'h04a: data = 8'b00001100; // **
12'h04b: data = 8'b00011110; // ****
12'h04c: data = 8'b00000000; //
12'h04d: data = 8'b00000000; //
12'h04e: data = 8'b00000000; //
12'h04f: data = 8'b00000000; //
//code x05
12'h050: data = 8'b00000000; //
12'h051: data = 8'b00000000; //
12'h052: data = 8'b11111110; // *******
12'h053: data = 8'b11000000; // **
12'h054: data = 8'b11000000; // **
12'h055: data = 8'b11000000; // **
12'h056: data = 8'b11111100; // ******
12'h057: data = 8'b00000110; // **
12'h058: data = 8'b00000110; // **
12'h059: data = 8'b00000110; // **
12'h05a: data = 8'b11000110; // ** **
12'h05b: data = 8'b01111100; // *****
12'h05c: data = 8'b00000000; //
12'h05d: data = 8'b00000000; //
12'h05e: data = 8'b00000000; //
12'h05f: data = 8'b00000000; //
//code x06
12'h060: data = 8'b00000000; //
12'h061: data = 8'b00000000; //
12'h062: data = 8'b00111000; // ***
12'h063: data = 8'b01100000; // **
12'h064: data = 8'b11000000; // **
12'h065: data = 8'b11000000; // **
12'h066: data = 8'b11111100; // ******
12'h067: data = 8'b11000110; // ** **
12'h068: data = 8'b11000110; // ** **
12'h069: data = 8'b11000110; // ** **
12'h06a: data = 8'b11000110; // ** **
12'h06b: data = 8'b01111100; // *****
12'h06c: data = 8'b00000000; //
12'h06d: data = 8'b00000000; //
12'h06e: data = 8'b00000000; //
12'h06f: data = 8'b00000000; //
//code x07
12'h070: data = 8'b00000000; //
12'h071: data = 8'b00000000; //
12'h072: data = 8'b11111110; // *******
12'h073: data = 8'b11000110; // ** **
12'h074: data = 8'b00000110; // **
12'h075: data = 8'b00000110; // **
12'h076: data = 8'b00001100; // **
12'h077: data = 8'b00011000; // **
12'h078: data = 8'b00110000; // **
12'h079: data = 8'b00110000; // **
12'h07a: data = 8'b00110000; // **
12'h07b: data = 8'b00110000; // **
12'h07c: data = 8'b00000000; //
12'h07d: data = 8'b00000000; //
12'h07e: data = 8'b00000000; //
12'h07f: data = 8'b00000000; //
//code x08
12'h080: data = 8'b00000000; //
12'h081: data = 8'b00000000; //
12'h082: data = 8'b01111100; // *****
12'h083: data = 8'b11000110; // ** **
12'h084: data = 8'b11000110; // ** **
12'h085: data = 8'b11000110; // ** **
12'h086: data = 8'b01111100; // *****
12'h087: data = 8'b11000110; // ** **
12'h088: data = 8'b11000110; // ** **
12'h089: data = 8'b11000110; // ** **
12'h08a: data = 8'b11000110; // ** **
12'h08b: data = 8'b01111100; // *****
12'h08c: data = 8'b00000000; //
12'h08d: data = 8'b00000000; //
12'h08e: data = 8'b00000000; //
12'h08f: data = 8'b00000000; //
//code x09
12'h090: data = 8'b00000000; //
12'h091: data = 8'b00000000; //
12'h092: data = 8'b01111100; // *****
12'h093: data = 8'b11000110; // ** **
12'h094: data = 8'b11000110; // ** **
12'h095: data = 8'b11000110; // ** **
12'h096: data = 8'b01111110; // ******
12'h097: data = 8'b00000110; // **
12'h098: data = 8'b00000110; // **
12'h099: data = 8'b00000110; // **
12'h09a: data = 8'b00001100; // **
12'h09b: data = 8'b01111000; // ****
12'h09c: data = 8'b00000000; //
12'h09d: data = 8'b00000000; //
12'h09e: data = 8'b00000000; //
12'h09f: data = 8'b00000000; //
//code x0a
12'h0a0: data = 8'b00000000; //
12'h0a1: data = 8'b00000000; //
12'h0a2: data = 8'b11000011; // ** **
12'h0a3: data = 8'b11100111; // *** ***
12'h0a4: data = 8'b11111111; // ********
12'h0a5: data = 8'b11111111; // ********
12'h0a6: data = 8'b11011011; // ** ** **
12'h0a7: data = 8'b11000011; // ** **
12'h0a8: data = 8'b11000011; // ** **
12'h0a9: data = 8'b11000011; // ** **
12'h0aa: data = 8'b11000011; // ** **
12'h0ab: data = 8'b11000011; // ** **
12'h0ac: data = 8'b00000000; //
12'h0ad: data = 8'b00000000; //
12'h0ae: data = 8'b00000000; //
12'h0af: data = 8'b00000000; //
//code x0b
12'h0b0: data = 8'b00000000; //
12'h0b1: data = 8'b00000000; //
12'h0b2: data = 8'b00010000; // *
12'h0b3: data = 8'b00111000; // ***
12'h0b4: data = 8'b01101100; // ** **
12'h0b5: data = 8'b11000110; // ** **
12'h0b6: data = 8'b11000110; // ** **
12'h0b7: data = 8'b11111110; // *******
12'h0b8: data = 8'b11000110; // ** **
12'h0b9: data = 8'b11000110; // ** **
12'h0ba: data = 8'b11000110; // ** **
12'h0bb: data = 8'b11000110; // ** **
12'h0bc: data = 8'b00000000; //
12'h0bd: data = 8'b00000000; //
12'h0be: data = 8'b00000000; //
12'h0bf: data = 8'b00000000; //
//code x0c
12'h0c0: data = 8'b00000000; //
12'h0c1: data = 8'b00000000; //
12'h0c2: data = 8'b11111100; // ******
12'h0c3: data = 8'b01100110; // ** **
12'h0c4: data = 8'b01100110; // ** **
12'h0c5: data = 8'b01100110; // ** **
12'h0c6: data = 8'b01111100; // *****
12'h0c7: data = 8'b01101100; // ** **
12'h0c8: data = 8'b01100110; // ** **
12'h0c9: data = 8'b01100110; // ** **
12'h0ca: data = 8'b01100110; // ** **
12'h0cb: data = 8'b11100110; // *** **
12'h0cc: data = 8'b00000000; //
12'h0cd: data = 8'b00000000; //
12'h0ce: data = 8'b00000000; //
12'h0cf: data = 8'b00000000; //
//code x0d
12'h0d0: data = 8'b00000000; //
12'h0d1: data = 8'b00000000; //
12'h0d2: data = 8'b00111100; // ****
12'h0d3: data = 8'b00011000; // **
12'h0d4: data = 8'b00011000; // **
12'h0d5: data = 8'b00011000; // **
12'h0d6: data = 8'b00011000; // **
12'h0d7: data = 8'b00011000; // **
12'h0d8: data = 8'b00011000; // **
12'h0d9: data = 8'b00011000; // **
12'h0da: data = 8'b00011000; // **
12'h0db: data = 8'b00111100; // ****
12'h0dc: data = 8'b00000000; //
12'h0dd: data = 8'b00000000; //
12'h0de: data = 8'b00000000; //
12'h0df: data = 8'b00000000; //
//code x0e
12'h0e0: data = 8'b00000000; //
12'h0e1: data = 8'b00000000; //
12'h0e2: data = 8'b01111100; // *****
12'h0e3: data = 8'b11000110; // ** **
12'h0e4: data = 8'b11000110; // ** **
12'h0e5: data = 8'b11000110; // ** **
12'h0e6: data = 8'b11000110; // ** **
12'h0e7: data = 8'b11000110; // ** **
12'h0e8: data = 8'b11000110; // ** **
12'h0e9: data = 8'b11000110; // ** **
12'h0ea: data = 8'b11000110; // ** **
12'h0eb: data = 8'b01111100; // *****
12'h0ec: data = 8'b00000000; //
12'h0ed: data = 8'b00000000; //
12'h0ee: data = 8'b00000000; //
12'h0ef: data = 8'b00000000; //
//code x0f
12'h0f0: data = 8'b00000000; //
12'h0f1: data = 8'b00000000; //
12'h0f2: data = 8'b00000000; //
12'h0f3: data = 8'b00000000; //
12'h0f4: data = 8'b00000000; //
12'h0f5: data = 8'b00000000; //
12'h0f6: data = 8'b00000000; //
12'h0f7: data = 8'b00000000; //
12'h0f8: data = 8'b00000000; //
12'h0f9: data = 8'b00000000; //
12'h0fa: data = 8'b00000000; //
12'h0fb: data = 8'b00000000; //
12'h0fc: data = 8'b00000000; //
12'h0fd: data = 8'b00000000; //
12'h0fe: data = 8'b00000000; //
12'h0ff: data = 8'b00000000; //
//code x10
12'h100: data = 8'b00000000; //
12'h101: data = 8'b00000000; //
12'h102: data = 8'b00000000; //
12'h103: data = 8'b00000000; //
12'h104: data = 8'b00000000; //
12'h105: data = 8'b11000011; // ** **
12'h106: data = 8'b01100110; // ** **
12'h107: data = 8'b00111100; // ****
12'h108: data = 8'b00011000; // **
12'h109: data = 8'b00111100; // ****
12'h10a: data = 8'b01100110; // ** **
12'h10b: data = 8'b11000011; // ** **
12'h10c: data = 8'b00000000; //
12'h10d: data = 8'b00000000; //
12'h10e: data = 8'b00000000; //
12'h10f: data = 8'b00000000; //
//code x11
12'h110: data = 8'b00000000; //
12'h111: data = 8'b00000000; //
12'h112: data = 8'b00000000; //
12'h113: data = 8'b00000000; //
12'h114: data = 8'b00111100; // ****
12'h115: data = 8'b00111100; // ****
12'h116: data = 8'b11111111; // ** **
12'h117: data = 8'b11111111; // ** **
12'h118: data = 8'b11111111; // ** **
12'h119: data = 8'b11111111; // ** **
12'h11a: data = 8'b00111100; // ****
12'h11b: data = 8'b00111100; // ****
12'h11c: data = 8'b00000000; //
12'h11d: data = 8'b00000000; //
12'h11e: data = 8'b00000000; //
12'h11f: data = 8'b00000000; //
//code x12
12'h120: data = 8'b00000000; //
12'h121: data = 8'b00000000; //
12'h122: data = 8'b11110000; // ****
12'h123: data = 8'b01100000; // **
12'h124: data = 8'b01100000; // **
12'h125: data = 8'b01100000; // **
12'h126: data = 8'b01100000; // **
12'h127: data = 8'b01100000; // **
12'h128: data = 8'b01100000; // **
12'h129: data = 8'b01100010; // ** *
12'h12a: data = 8'b01100110; // ** **
12'h12b: data = 8'b11111110; // *******
12'h12c: data = 8'b00000000; //
12'h12d: data = 8'b00000000; //
12'h12e: data = 8'b00000000; //
12'h12f: data = 8'b00000000; //
//code x13
12'h130: data = 8'b00000000; //
12'h131: data = 8'b00000000; //
12'h132: data = 8'b11111110; // *******
12'h133: data = 8'b01100110; // ** **
12'h134: data = 8'b01100010; // ** *
12'h135: data = 8'b01101000; // ** *
12'h136: data = 8'b01111000; // ****
12'h137: data = 8'b01111000; // ****
12'h138: data = 8'b01101000; // ** *
12'h139: data = 8'b01100010; // ** *
12'h13a: data = 8'b01100110; // ** **
12'h13b: data = 8'b11111110; // *******
12'h13c: data = 8'b00000000; //
12'h13d: data = 8'b00000000; //
12'h13e: data = 8'b00000000; //
12'h13f: data = 8'b00000000; //
//code x14
12'h140: data = 8'b00000000; //
12'h141: data = 8'b00000000; //
12'h142: data = 8'b11000011; // ** **
12'h143: data = 8'b11000011; // ** **
12'h144: data = 8'b11000011; // ** **
12'h145: data = 8'b11000011; // ** **
12'h146: data = 8'b11000011; // ** **
12'h147: data = 8'b11000011; // ** **
12'h148: data = 8'b11000011; // ** **
12'h149: data = 8'b01100110; // ** **
12'h14a: data = 8'b00111100; // ****
12'h14b: data = 8'b00011000; // **
12'h14c: data = 8'b00000000; //
12'h14d: data = 8'b00000000; //
12'h14e: data = 8'b00000000; //
12'h14f: data = 8'b00000000; //
default: data = 8'b00000000;
endcase
endmodule
|
// Copyright 2007 Altera Corporation. All rights reserved.
// Altera products are protected under numerous U.S. and foreign patents,
// maskwork rights, copyrights and other intellectual property laws.
//
// This reference design file, and your use thereof, is subject to and governed
// by the terms and conditions of the applicable Altera Reference Design
// License Agreement (either as signed by you or found at www.altera.com). By
// using this reference design file, you indicate your acceptance of such terms
// and conditions between you and Altera Corporation. In the event that you do
// not agree with such terms and conditions, you may not use the reference
// design file and please promptly destroy any copies you have made.
//
// This reference design file is being provided on an "as-is" basis and as an
// accommodation and therefore all warranties, representations or guarantees of
// any kind (whether express, implied or statutory) including, without
// limitation, warranties of merchantability, non-infringement, or fitness for
// a particular purpose, are specifically disclaimed. By making this reference
// design file available, Altera expressly does not recommend, suggest or
// require that this reference design file be used in combination with any
// other product not provided by Altera.
/////////////////////////////////////////////////////////////////////////////
// baeckler - 11-14-2006
module onehot_to_bin (onehot,bin);
parameter ONEHOT_WIDTH = 16;
parameter BIN_WIDTH = $clog2(ONEHOT_WIDTH-1);
input [ONEHOT_WIDTH-1:0] onehot;
output [BIN_WIDTH-1:0] bin;
genvar i,j;
generate
for (j=0; j<BIN_WIDTH; j=j+1)
begin : jl
wire [ONEHOT_WIDTH-1:0] tmp_mask;
for (i=0; i<ONEHOT_WIDTH; i=i+1)
begin : il
assign tmp_mask[i] = i[j];
end
assign bin[j] = |(tmp_mask & onehot);
end
endgenerate
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Wed Feb 08 00:48:16 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// c:/Zybo-Open-Source-Video-IP-Toolbox/video_processing_examples/affine_transform_demo/affine_transform_demo.srcs/sources_1/bd/system/ip/system_vga_sync_0_0/system_vga_sync_0_0_sim_netlist.v
// Design : system_vga_sync_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "system_vga_sync_0_0,vga_sync,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "vga_sync,Vivado 2016.4" *)
(* NotValidForBitStream *)
module system_vga_sync_0_0
(clk_25,
rst,
active,
hsync,
vsync,
xaddr,
yaddr);
input clk_25;
(* x_interface_info = "xilinx.com:signal:reset:1.0 rst RST" *) input rst;
output active;
output hsync;
output vsync;
output [9:0]xaddr;
output [9:0]yaddr;
wire active;
wire clk_25;
wire hsync;
wire rst;
wire vsync;
wire [9:0]xaddr;
wire [9:0]yaddr;
system_vga_sync_0_0_vga_sync U0
(.active(active),
.clk_25(clk_25),
.hsync(hsync),
.rst(rst),
.vsync(vsync),
.xaddr(xaddr),
.yaddr(yaddr));
endmodule
(* ORIG_REF_NAME = "vga_sync" *)
module system_vga_sync_0_0_vga_sync
(xaddr,
yaddr,
hsync,
vsync,
active,
clk_25,
rst);
output [9:0]xaddr;
output [9:0]yaddr;
output hsync;
output vsync;
output active;
input clk_25;
input rst;
wire active;
wire active_INST_0_i_1_n_0;
wire clk_25;
wire [9:0]h_count_next;
wire \h_count_reg[4]_i_1_n_0 ;
wire \h_count_reg[5]_i_2_n_0 ;
wire \h_count_reg[9]_i_2_n_0 ;
wire \h_count_reg[9]_i_3_n_0 ;
wire \h_count_reg[9]_i_4_n_0 ;
wire h_sync_next;
wire hsync;
wire [9:0]p_0_in;
wire rst;
wire sel;
wire \v_count_reg[3]_i_2_n_0 ;
wire \v_count_reg[6]_i_1_n_0 ;
wire \v_count_reg[9]_i_3_n_0 ;
wire \v_count_reg[9]_i_4_n_0 ;
wire \v_count_reg[9]_i_5_n_0 ;
wire v_sync_next;
wire vsync;
wire [9:0]xaddr;
wire [9:0]yaddr;
LUT5 #(
.INIT(32'h000002AA))
active_INST_0
(.I0(active_INST_0_i_1_n_0),
.I1(xaddr[8]),
.I2(xaddr[7]),
.I3(xaddr[9]),
.I4(yaddr[9]),
.O(active));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT4 #(
.INIT(16'h7FFF))
active_INST_0_i_1
(.I0(yaddr[6]),
.I1(yaddr[5]),
.I2(yaddr[7]),
.I3(yaddr[8]),
.O(active_INST_0_i_1_n_0));
LUT1 #(
.INIT(2'h1))
\h_count_reg[0]_i_1
(.I0(xaddr[0]),
.O(h_count_next[0]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT2 #(
.INIT(4'h6))
\h_count_reg[1]_i_1
(.I0(xaddr[0]),
.I1(xaddr[1]),
.O(h_count_next[1]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT3 #(
.INIT(8'h78))
\h_count_reg[2]_i_1
(.I0(xaddr[0]),
.I1(xaddr[1]),
.I2(xaddr[2]),
.O(h_count_next[2]));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT4 #(
.INIT(16'h6AAA))
\h_count_reg[3]_i_1
(.I0(xaddr[3]),
.I1(xaddr[0]),
.I2(xaddr[1]),
.I3(xaddr[2]),
.O(h_count_next[3]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'h6AAAAAAA))
\h_count_reg[4]_i_1
(.I0(xaddr[4]),
.I1(xaddr[2]),
.I2(xaddr[1]),
.I3(xaddr[0]),
.I4(xaddr[3]),
.O(\h_count_reg[4]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFF00000000FFBF))
\h_count_reg[5]_i_1
(.I0(xaddr[6]),
.I1(xaddr[8]),
.I2(xaddr[9]),
.I3(xaddr[7]),
.I4(\h_count_reg[5]_i_2_n_0 ),
.I5(xaddr[5]),
.O(h_count_next[5]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'h7FFFFFFF))
\h_count_reg[5]_i_2
(.I0(xaddr[2]),
.I1(xaddr[1]),
.I2(xaddr[0]),
.I3(xaddr[3]),
.I4(xaddr[4]),
.O(\h_count_reg[5]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'hAA6A))
\h_count_reg[6]_i_1
(.I0(xaddr[6]),
.I1(xaddr[4]),
.I2(xaddr[5]),
.I3(\h_count_reg[9]_i_3_n_0 ),
.O(h_count_next[6]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT5 #(
.INIT(32'h9AAAAAAA))
\h_count_reg[7]_i_1
(.I0(xaddr[7]),
.I1(\h_count_reg[9]_i_3_n_0 ),
.I2(xaddr[5]),
.I3(xaddr[4]),
.I4(xaddr[6]),
.O(h_count_next[7]));
LUT5 #(
.INIT(32'hFF0B00B0))
\h_count_reg[8]_i_1
(.I0(\h_count_reg[9]_i_2_n_0 ),
.I1(xaddr[4]),
.I2(\h_count_reg[9]_i_4_n_0 ),
.I3(\h_count_reg[9]_i_3_n_0 ),
.I4(xaddr[8]),
.O(h_count_next[8]));
LUT6 #(
.INIT(64'hF0FBFBFB0B000000))
\h_count_reg[9]_i_1
(.I0(\h_count_reg[9]_i_2_n_0 ),
.I1(xaddr[4]),
.I2(\h_count_reg[9]_i_3_n_0 ),
.I3(\h_count_reg[9]_i_4_n_0 ),
.I4(xaddr[8]),
.I5(xaddr[9]),
.O(h_count_next[9]));
LUT5 #(
.INIT(32'hFFFFEFFF))
\h_count_reg[9]_i_2
(.I0(xaddr[6]),
.I1(xaddr[5]),
.I2(xaddr[8]),
.I3(xaddr[9]),
.I4(xaddr[7]),
.O(\h_count_reg[9]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT4 #(
.INIT(16'h7FFF))
\h_count_reg[9]_i_3
(.I0(xaddr[3]),
.I1(xaddr[0]),
.I2(xaddr[1]),
.I3(xaddr[2]),
.O(\h_count_reg[9]_i_3_n_0 ));
LUT4 #(
.INIT(16'h8000))
\h_count_reg[9]_i_4
(.I0(xaddr[7]),
.I1(xaddr[6]),
.I2(xaddr[5]),
.I3(xaddr[4]),
.O(\h_count_reg[9]_i_4_n_0 ));
FDCE \h_count_reg_reg[0]
(.C(clk_25),
.CE(1'b1),
.CLR(rst),
.D(h_count_next[0]),
.Q(xaddr[0]));
FDCE \h_count_reg_reg[1]
(.C(clk_25),
.CE(1'b1),
.CLR(rst),
.D(h_count_next[1]),
.Q(xaddr[1]));
FDCE \h_count_reg_reg[2]
(.C(clk_25),
.CE(1'b1),
.CLR(rst),
.D(h_count_next[2]),
.Q(xaddr[2]));
FDCE \h_count_reg_reg[3]
(.C(clk_25),
.CE(1'b1),
.CLR(rst),
.D(h_count_next[3]),
.Q(xaddr[3]));
FDCE \h_count_reg_reg[4]
(.C(clk_25),
.CE(1'b1),
.CLR(rst),
.D(\h_count_reg[4]_i_1_n_0 ),
.Q(xaddr[4]));
FDCE \h_count_reg_reg[5]
(.C(clk_25),
.CE(1'b1),
.CLR(rst),
.D(h_count_next[5]),
.Q(xaddr[5]));
FDCE \h_count_reg_reg[6]
(.C(clk_25),
.CE(1'b1),
.CLR(rst),
.D(h_count_next[6]),
.Q(xaddr[6]));
FDCE \h_count_reg_reg[7]
(.C(clk_25),
.CE(1'b1),
.CLR(rst),
.D(h_count_next[7]),
.Q(xaddr[7]));
FDCE \h_count_reg_reg[8]
(.C(clk_25),
.CE(1'b1),
.CLR(rst),
.D(h_count_next[8]),
.Q(xaddr[8]));
FDCE \h_count_reg_reg[9]
(.C(clk_25),
.CE(1'b1),
.CLR(rst),
.D(h_count_next[9]),
.Q(xaddr[9]));
LUT6 #(
.INIT(64'h00002AA800000000))
h_sync_reg_i_1
(.I0(xaddr[7]),
.I1(xaddr[6]),
.I2(xaddr[5]),
.I3(xaddr[4]),
.I4(xaddr[8]),
.I5(xaddr[9]),
.O(h_sync_next));
FDPE #(
.INIT(1'b0))
h_sync_reg_reg
(.C(clk_25),
.CE(1'b1),
.D(h_sync_next),
.PRE(rst),
.Q(hsync));
LUT6 #(
.INIT(64'h5555555545555555))
\v_count_reg[0]_i_1
(.I0(yaddr[0]),
.I1(\v_count_reg[9]_i_4_n_0 ),
.I2(yaddr[9]),
.I3(yaddr[2]),
.I4(yaddr[3]),
.I5(yaddr[7]),
.O(p_0_in[0]));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT2 #(
.INIT(4'h6))
\v_count_reg[1]_i_1
(.I0(yaddr[0]),
.I1(yaddr[1]),
.O(p_0_in[1]));
LUT6 #(
.INIT(64'h55AA55AA45AA55AA))
\v_count_reg[2]_i_1
(.I0(\v_count_reg[3]_i_2_n_0 ),
.I1(\v_count_reg[9]_i_4_n_0 ),
.I2(yaddr[9]),
.I3(yaddr[2]),
.I4(yaddr[3]),
.I5(yaddr[7]),
.O(p_0_in[2]));
LUT6 #(
.INIT(64'h55FFAA0045FFAA00))
\v_count_reg[3]_i_1
(.I0(\v_count_reg[3]_i_2_n_0 ),
.I1(\v_count_reg[9]_i_4_n_0 ),
.I2(yaddr[9]),
.I3(yaddr[2]),
.I4(yaddr[3]),
.I5(yaddr[7]),
.O(p_0_in[3]));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT2 #(
.INIT(4'h8))
\v_count_reg[3]_i_2
(.I0(yaddr[0]),
.I1(yaddr[1]),
.O(\v_count_reg[3]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h6AAAAAAA))
\v_count_reg[4]_i_1
(.I0(yaddr[4]),
.I1(yaddr[2]),
.I2(yaddr[3]),
.I3(yaddr[0]),
.I4(yaddr[1]),
.O(p_0_in[4]));
LUT6 #(
.INIT(64'h6AAAAAAAAAAAAAAA))
\v_count_reg[5]_i_1
(.I0(yaddr[5]),
.I1(yaddr[1]),
.I2(yaddr[0]),
.I3(yaddr[3]),
.I4(yaddr[2]),
.I5(yaddr[4]),
.O(p_0_in[5]));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT3 #(
.INIT(8'h6A))
\v_count_reg[6]_i_1
(.I0(yaddr[6]),
.I1(\v_count_reg[9]_i_5_n_0 ),
.I2(yaddr[5]),
.O(\v_count_reg[6]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT4 #(
.INIT(16'h6AAA))
\v_count_reg[7]_i_1
(.I0(yaddr[7]),
.I1(yaddr[5]),
.I2(\v_count_reg[9]_i_5_n_0 ),
.I3(yaddr[6]),
.O(p_0_in[7]));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT5 #(
.INIT(32'h6AAAAAAA))
\v_count_reg[8]_i_1
(.I0(yaddr[8]),
.I1(yaddr[6]),
.I2(\v_count_reg[9]_i_5_n_0 ),
.I3(yaddr[5]),
.I4(yaddr[7]),
.O(p_0_in[8]));
LUT6 #(
.INIT(64'h0000000000001000))
\v_count_reg[9]_i_1
(.I0(xaddr[6]),
.I1(xaddr[5]),
.I2(xaddr[8]),
.I3(xaddr[9]),
.I4(xaddr[7]),
.I5(\h_count_reg[5]_i_2_n_0 ),
.O(sel));
LUT5 #(
.INIT(32'hD0D00DD0))
\v_count_reg[9]_i_2
(.I0(\v_count_reg[9]_i_3_n_0 ),
.I1(\v_count_reg[9]_i_4_n_0 ),
.I2(yaddr[9]),
.I3(\v_count_reg[9]_i_5_n_0 ),
.I4(active_INST_0_i_1_n_0),
.O(p_0_in[9]));
LUT4 #(
.INIT(16'h0080))
\v_count_reg[9]_i_3
(.I0(yaddr[9]),
.I1(yaddr[2]),
.I2(yaddr[3]),
.I3(yaddr[7]),
.O(\v_count_reg[9]_i_3_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\v_count_reg[9]_i_4
(.I0(yaddr[1]),
.I1(yaddr[0]),
.I2(yaddr[6]),
.I3(yaddr[8]),
.I4(yaddr[4]),
.I5(yaddr[5]),
.O(\v_count_reg[9]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h80000000))
\v_count_reg[9]_i_5
(.I0(yaddr[4]),
.I1(yaddr[2]),
.I2(yaddr[3]),
.I3(yaddr[0]),
.I4(yaddr[1]),
.O(\v_count_reg[9]_i_5_n_0 ));
FDCE \v_count_reg_reg[0]
(.C(clk_25),
.CE(sel),
.CLR(rst),
.D(p_0_in[0]),
.Q(yaddr[0]));
FDCE \v_count_reg_reg[1]
(.C(clk_25),
.CE(sel),
.CLR(rst),
.D(p_0_in[1]),
.Q(yaddr[1]));
FDCE \v_count_reg_reg[2]
(.C(clk_25),
.CE(sel),
.CLR(rst),
.D(p_0_in[2]),
.Q(yaddr[2]));
FDCE \v_count_reg_reg[3]
(.C(clk_25),
.CE(sel),
.CLR(rst),
.D(p_0_in[3]),
.Q(yaddr[3]));
FDCE \v_count_reg_reg[4]
(.C(clk_25),
.CE(sel),
.CLR(rst),
.D(p_0_in[4]),
.Q(yaddr[4]));
FDCE \v_count_reg_reg[5]
(.C(clk_25),
.CE(sel),
.CLR(rst),
.D(p_0_in[5]),
.Q(yaddr[5]));
FDCE \v_count_reg_reg[6]
(.C(clk_25),
.CE(sel),
.CLR(rst),
.D(\v_count_reg[6]_i_1_n_0 ),
.Q(yaddr[6]));
FDCE \v_count_reg_reg[7]
(.C(clk_25),
.CE(sel),
.CLR(rst),
.D(p_0_in[7]),
.Q(yaddr[7]));
FDCE \v_count_reg_reg[8]
(.C(clk_25),
.CE(sel),
.CLR(rst),
.D(p_0_in[8]),
.Q(yaddr[8]));
FDCE \v_count_reg_reg[9]
(.C(clk_25),
.CE(sel),
.CLR(rst),
.D(p_0_in[9]),
.Q(yaddr[9]));
LUT6 #(
.INIT(64'h0000000000040000))
v_sync_reg_i_1
(.I0(yaddr[9]),
.I1(yaddr[3]),
.I2(yaddr[4]),
.I3(yaddr[2]),
.I4(yaddr[1]),
.I5(active_INST_0_i_1_n_0),
.O(v_sync_next));
FDPE #(
.INIT(1'b0))
v_sync_reg_reg
(.C(clk_25),
.CE(1'b1),
.D(v_sync_next),
.PRE(rst),
.Q(vsync));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_io_dtl_bscan.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module bw_io_dtl_bscan(q_dn_mux_l ,rst_val_up ,mode_ctl ,serial_out ,
bsr_so ,bsr_si ,se ,q25_dn_pad_l ,q_up_pad ,update_dr ,out_type ,
q25_dn_mux_l ,bsr_data_to_core ,rcvr_data_to_bsr ,shift_dr ,up_open
,ps_select ,q_dn_pad_l ,sel_data_n ,bypass_enable ,q_up_mux ,
down_25 ,rst_val_dn ,clk ,serial_in ,hiz_l ,rst_io_l ,clock_dr ,
bypass_in );
output q_dn_mux_l ;
output serial_out ;
output bsr_so ;
output q25_dn_mux_l ;
output bsr_data_to_core ;
output sel_data_n ;
output q_up_mux ;
input rst_val_up ;
input mode_ctl ;
input bsr_si ;
input se ;
input q25_dn_pad_l ;
input q_up_pad ;
input update_dr ;
input out_type ;
input rcvr_data_to_bsr ;
input shift_dr ;
input up_open ;
input ps_select ;
input q_dn_pad_l ;
input bypass_enable ;
input down_25 ;
input rst_val_dn ;
input clk ;
input serial_in ;
input hiz_l ;
input rst_io_l ;
input clock_dr ;
input bypass_in ;
wire [1:0] doe ;
wire [1:0] tf ;
wire [2:0] q ;
wire net110 ;
wire net117 ;
wire net119 ;
wire net123 ;
wire bypass ;
wire net127 ;
wire sd_n ;
wire se_n ;
wire net137 ;
wire net140 ;
wire bsr_to_core ;
wire bso_n ;
wire se_in ;
bw_u1_inv_8x so_inv8x (
.z (bsr_so ),
.a (bso_n ) );
bw_io_dtl_flps three_flps (
.d ({rcvr_data_to_bsr ,doe[1:0] } ),
.q ({q } ),
.clk (clock_dr ),
.so (net110 ),
.si (bsr_si ),
.se (net117 ) );
bw_u1_inv_1x ud_inv1x (
.z (net137 ),
.a (update_dr ) );
bw_u1_inv_5x bc_inv5x (
.z (bsr_data_to_core ),
.a (net127 ) );
bw_u1_inv_1x ps_inv1 (
.z (bypass ),
.a (net140 ) );
bw_u1_inv_3x shfdr_inv3x (
.z (net117 ),
.a (sd_n ) );
bw_u1_nand2_1x ps_nand2 (
.z (net140 ),
.a (tf[1] ),
.b (bypass_enable ) );
bw_u1_inv_1x shfdr_inv1x (
.z (sd_n ),
.a (shift_dr ) );
bw_u1_inv_4x so_inv4x (
.z (bso_n ),
.a (net110 ) );
bw_io_dq_pscan pscan (
.serial_in (serial_in ),
.serial_out (serial_out ),
.bypass_in (bypass_in ),
.out_type (out_type ),
.clk (clk ),
.bypass (bypass ),
.ps_select (ps_select ),
.rcv_in (rcvr_data_to_bsr ) );
bw_u1_inv_2x bc_inv2x (
.z (net127 ),
.a (bsr_to_core ) );
bw_io_bs_fsdq_2x three_latches (
.q ({bsr_to_core ,tf[1:0] } ),
.d ({q } ),
.up_dr (net119 ) );
bw_io_dtl_bscl1 comb_lgc_1 (
.intest_oe (doe[0] ),
.intest_d (doe[1] ),
.q_dn_pad (q_dn_pad_l ),
.q25_dn_pad (q25_dn_pad_l ),
.q_up_pad (q_up_pad ) );
bw_io_dtl_bscl2 comb_lgc_2 (
.scan_mode (se_in ),
.mode_ctl (mode_ctl ),
.out_type (out_type ),
.rst_val_dn (rst_val_dn ),
.bscan_oe (tf[0] ),
.sel_data_n (sel_data_n ),
.q25_dn_mux_l (q25_dn_mux_l ),
.down_25 (down_25 ),
.rst_io_l (rst_io_l ),
.ps_select (ps_select ),
.q_dn_mux_l (q_dn_mux_l ),
.up_open (up_open ),
.bscan_d (tf[1] ),
.hiz_l (hiz_l ),
.q_up_mux (q_up_mux ),
.ps_data (serial_out ),
.rst_val_up (rst_val_up ) );
bw_u1_inv_2x se_inv2x (
.z (se_in ),
.a (se_n ) );
bw_u1_inv_3x ud_inv3x (
.z (net119 ),
.a (net123 ) );
bw_u1_inv_1x se_inv1x (
.z (se_n ),
.a (se ) );
bw_u1_inv_2x ud_inv2x (
.z (net123 ),
.a (net137 ) );
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Tue Jun 06 02:47:25 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/ZyboIP/examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ip/system_vga_feature_transform_0_0/system_vga_feature_transform_0_0_stub.v
// Design : system_vga_feature_transform_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "vga_feature_transform,Vivado 2016.4" *)
module system_vga_feature_transform_0_0(clk, clk_x2, rst, active, vsync, x_addr_0, y_addr_0,
hessian_0, x_addr_1, y_addr_1, hessian_1, rot_m00, rot_m01, rot_m10, rot_m11, t_x, t_y, state)
/* synthesis syn_black_box black_box_pad_pin="clk,clk_x2,rst,active,vsync,x_addr_0[9:0],y_addr_0[9:0],hessian_0[31:0],x_addr_1[9:0],y_addr_1[9:0],hessian_1[31:0],rot_m00[15:0],rot_m01[15:0],rot_m10[15:0],rot_m11[15:0],t_x[9:0],t_y[9:0],state[1:0]" */;
input clk;
input clk_x2;
input rst;
input active;
input vsync;
input [9:0]x_addr_0;
input [9:0]y_addr_0;
input [31:0]hessian_0;
input [9:0]x_addr_1;
input [9:0]y_addr_1;
input [31:0]hessian_1;
output [15:0]rot_m00;
output [15:0]rot_m01;
output [15:0]rot_m10;
output [15:0]rot_m11;
output [9:0]t_x;
output [9:0]t_y;
output [1:0]state;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__AND2B_TB_V
`define SKY130_FD_SC_HD__AND2B_TB_V
/**
* and2b: 2-input AND, first input inverted.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__and2b.v"
module top();
// Inputs are registered
reg A_N;
reg B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A_N = 1'bX;
B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A_N = 1'b0;
#40 B = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A_N = 1'b1;
#160 B = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A_N = 1'b0;
#280 B = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 B = 1'b1;
#480 A_N = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 B = 1'bx;
#600 A_N = 1'bx;
end
sky130_fd_sc_hd__and2b dut (.A_N(A_N), .B(B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__AND2B_TB_V
|
`include "constants.vh"
`default_nettype none
module ram_sync_1r1w #(
parameter BRAM_ADDR_WIDTH = `ADDR_LEN,
parameter BRAM_DATA_WIDTH = `DATA_LEN,
parameter DATA_DEPTH = 32
)
(
input wire clk,
input wire [BRAM_ADDR_WIDTH-1:0] raddr1,
output reg [BRAM_DATA_WIDTH-1:0] rdata1,
input wire [BRAM_ADDR_WIDTH-1:0] waddr,
input wire [BRAM_DATA_WIDTH-1:0] wdata,
input wire we
);
reg [BRAM_DATA_WIDTH-1:0] mem [0:DATA_DEPTH-1];
always @ (posedge clk) begin
rdata1 <= mem[raddr1];
if (we)
mem[waddr] <= wdata;
end
endmodule // ram_sync_1r1w
module ram_sync_2r1w #(
parameter BRAM_ADDR_WIDTH = `ADDR_LEN,
parameter BRAM_DATA_WIDTH = `DATA_LEN,
parameter DATA_DEPTH = 32
)
(
input wire clk,
input wire [BRAM_ADDR_WIDTH-1:0] raddr1,
input wire [BRAM_ADDR_WIDTH-1:0] raddr2,
output reg [BRAM_DATA_WIDTH-1:0] rdata1,
output reg [BRAM_DATA_WIDTH-1:0] rdata2,
input wire [BRAM_ADDR_WIDTH-1:0] waddr,
input wire [BRAM_DATA_WIDTH-1:0] wdata,
input wire we
);
reg [BRAM_DATA_WIDTH-1:0] mem [0:DATA_DEPTH-1];
always @ (posedge clk) begin
rdata1 <= mem[raddr1];
rdata2 <= mem[raddr2];
if (we)
mem[waddr] <= wdata;
end
endmodule // ram_sync_2r1w
module ram_sync_2r2w #(
parameter BRAM_ADDR_WIDTH = `ADDR_LEN,
parameter BRAM_DATA_WIDTH = `DATA_LEN,
parameter DATA_DEPTH = 32
)
(
input wire clk,
input wire [BRAM_ADDR_WIDTH-1:0] raddr1,
input wire [BRAM_ADDR_WIDTH-1:0] raddr2,
output reg [BRAM_DATA_WIDTH-1:0] rdata1,
output reg [BRAM_DATA_WIDTH-1:0] rdata2,
input wire [BRAM_ADDR_WIDTH-1:0] waddr1,
input wire [BRAM_ADDR_WIDTH-1:0] waddr2,
input wire [BRAM_DATA_WIDTH-1:0] wdata1,
input wire [BRAM_DATA_WIDTH-1:0] wdata2,
input wire we1,
input wire we2
);
reg [BRAM_DATA_WIDTH-1:0] mem [0:DATA_DEPTH-1];
always @ (posedge clk) begin
rdata1 <= mem[raddr1];
rdata2 <= mem[raddr2];
if (we1)
mem[waddr1] <= wdata1;
if (we2)
mem[waddr2] <= wdata2;
end
endmodule // ram_sync_2r2w
module ram_sync_4r1w #(
parameter BRAM_ADDR_WIDTH = `ADDR_LEN,
parameter BRAM_DATA_WIDTH = `DATA_LEN,
parameter DATA_DEPTH = 32
)
(
input wire clk,
input wire [BRAM_ADDR_WIDTH-1:0] raddr1,
input wire [BRAM_ADDR_WIDTH-1:0] raddr2,
input wire [BRAM_ADDR_WIDTH-1:0] raddr3,
input wire [BRAM_ADDR_WIDTH-1:0] raddr4,
output wire [BRAM_DATA_WIDTH-1:0] rdata1,
output wire [BRAM_DATA_WIDTH-1:0] rdata2,
output wire [BRAM_DATA_WIDTH-1:0] rdata3,
output wire [BRAM_DATA_WIDTH-1:0] rdata4,
input wire [BRAM_ADDR_WIDTH-1:0] waddr,
input wire [BRAM_DATA_WIDTH-1:0] wdata,
input wire we
);
ram_sync_2r1w
#(BRAM_ADDR_WIDTH, BRAM_DATA_WIDTH, DATA_DEPTH)
mem0(
.clk(clk),
.raddr1(raddr1),
.raddr2(raddr2),
.rdata1(rdata1),
.rdata2(rdata2),
.waddr(waddr),
.wdata(wdata),
.we(we)
);
ram_sync_2r1w
#(BRAM_ADDR_WIDTH, BRAM_DATA_WIDTH, DATA_DEPTH)
mem1(
.clk(clk),
.raddr1(raddr3),
.raddr2(raddr4),
.rdata1(rdata3),
.rdata2(rdata4),
.waddr(waddr),
.wdata(wdata),
.we(we)
);
endmodule // ram_sync_4r1w
module ram_sync_4r2w #(
parameter BRAM_ADDR_WIDTH = `ADDR_LEN,
parameter BRAM_DATA_WIDTH = `DATA_LEN,
parameter DATA_DEPTH = 32
)
(
input wire clk,
input wire [BRAM_ADDR_WIDTH-1:0] raddr1,
input wire [BRAM_ADDR_WIDTH-1:0] raddr2,
input wire [BRAM_ADDR_WIDTH-1:0] raddr3,
input wire [BRAM_ADDR_WIDTH-1:0] raddr4,
output wire [BRAM_DATA_WIDTH-1:0] rdata1,
output wire [BRAM_DATA_WIDTH-1:0] rdata2,
output wire [BRAM_DATA_WIDTH-1:0] rdata3,
output wire [BRAM_DATA_WIDTH-1:0] rdata4,
input wire [BRAM_ADDR_WIDTH-1:0] waddr1,
input wire [BRAM_ADDR_WIDTH-1:0] waddr2,
input wire [BRAM_DATA_WIDTH-1:0] wdata1,
input wire [BRAM_DATA_WIDTH-1:0] wdata2,
input wire we1,
input wire we2
);
ram_sync_2r2w
#(BRAM_ADDR_WIDTH, BRAM_DATA_WIDTH, DATA_DEPTH)
mem0(
.clk(clk),
.raddr1(raddr1),
.raddr2(raddr2),
.rdata1(rdata1),
.rdata2(rdata2),
.waddr1(waddr1),
.waddr2(waddr2),
.wdata1(wdata1),
.wdata2(wdata2),
.we1(we1),
.we2(we2)
);
ram_sync_2r2w
#(BRAM_ADDR_WIDTH, BRAM_DATA_WIDTH, DATA_DEPTH)
mem1(
.clk(clk),
.raddr1(raddr3),
.raddr2(raddr4),
.rdata1(rdata3),
.rdata2(rdata4),
.waddr1(waddr1),
.waddr2(waddr2),
.wdata1(wdata1),
.wdata2(wdata2),
.we1(we1),
.we2(we2)
);
endmodule // ram_sync_4r2w
module ram_sync_6r2w #(
parameter BRAM_ADDR_WIDTH = `ADDR_LEN,
parameter BRAM_DATA_WIDTH = `DATA_LEN,
parameter DATA_DEPTH = 32
)
(
input wire clk,
input wire [BRAM_ADDR_WIDTH-1:0] raddr1,
input wire [BRAM_ADDR_WIDTH-1:0] raddr2,
input wire [BRAM_ADDR_WIDTH-1:0] raddr3,
input wire [BRAM_ADDR_WIDTH-1:0] raddr4,
input wire [BRAM_ADDR_WIDTH-1:0] raddr5,
input wire [BRAM_ADDR_WIDTH-1:0] raddr6,
output wire [BRAM_DATA_WIDTH-1:0] rdata1,
output wire [BRAM_DATA_WIDTH-1:0] rdata2,
output wire [BRAM_DATA_WIDTH-1:0] rdata3,
output wire [BRAM_DATA_WIDTH-1:0] rdata4,
output wire [BRAM_DATA_WIDTH-1:0] rdata5,
output wire [BRAM_DATA_WIDTH-1:0] rdata6,
input wire [BRAM_ADDR_WIDTH-1:0] waddr1,
input wire [BRAM_ADDR_WIDTH-1:0] waddr2,
input wire [BRAM_DATA_WIDTH-1:0] wdata1,
input wire [BRAM_DATA_WIDTH-1:0] wdata2,
input wire we1,
input wire we2
);
ram_sync_2r2w
#(BRAM_ADDR_WIDTH, BRAM_DATA_WIDTH, DATA_DEPTH)
mem0(
.clk(clk),
.raddr1(raddr1),
.raddr2(raddr2),
.rdata1(rdata1),
.rdata2(rdata2),
.waddr1(waddr1),
.waddr2(waddr2),
.wdata1(wdata1),
.wdata2(wdata2),
.we1(we1),
.we2(we2)
);
ram_sync_2r2w
#(BRAM_ADDR_WIDTH, BRAM_DATA_WIDTH, DATA_DEPTH)
mem1(
.clk(clk),
.raddr1(raddr3),
.raddr2(raddr4),
.rdata1(rdata3),
.rdata2(rdata4),
.waddr1(waddr1),
.waddr2(waddr2),
.wdata1(wdata1),
.wdata2(wdata2),
.we1(we1),
.we2(we2)
);
ram_sync_2r2w
#(BRAM_ADDR_WIDTH, BRAM_DATA_WIDTH, DATA_DEPTH)
mem2(
.clk(clk),
.raddr1(raddr5),
.raddr2(raddr6),
.rdata1(rdata5),
.rdata2(rdata6),
.waddr1(waddr1),
.waddr2(waddr2),
.wdata1(wdata1),
.wdata2(wdata2),
.we1(we1),
.we2(we2)
);
endmodule // ram_sync_6r2w
`default_nettype wire
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O31AI_2_V
`define SKY130_FD_SC_MS__O31AI_2_V
/**
* o31ai: 3-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & B1)
*
* Verilog wrapper for o31ai with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__o31ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o31ai_2 (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__o31ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o31ai_2 (
Y ,
A1,
A2,
A3,
B1
);
output Y ;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__o31ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__O31AI_2_V
|
module test_RegWaitRW32(
//Avalon System control signal.
input rsi_MRST_reset, // reset_n from MCU GPIO
input csi_MCLK_clk,
//Avalon-MM Control.
input [31:0] avs_test_writedata,
output [31:0] avs_test_readdata,
input [5:0] avs_test_address,
input [3:0] avs_test_byteenable,
input avs_test_write,
input avs_test_read,
output avs_test_readdatavalid,
output avs_test_waitrequest
);
reg [31:0] out_data = 0;
reg [31:0] r_data = 0;
reg r_wait = 0;
reg [3:0] r_wait_cnt = 0;
reg r_valid = 0;
assign avs_test_readdata = out_data;
assign avs_test_waitrequest = r_wait;
assign avs_test_readdatavalid = r_valid;
always@(posedge csi_MCLK_clk or posedge rsi_MRST_reset)
begin
if(rsi_MRST_reset) begin
out_data <= 0;
r_data <= 0;
r_wait <= 0;
r_wait_cnt <= 0;
r_valid <= 0;
end
else begin
if(r_wait_cnt == 15) r_valid <= 1; else r_valid <= 0;
if(((r_wait_cnt > 0)&&(r_wait_cnt < 15))||(avs_test_read)||(avs_test_write)) r_wait <= 1; else r_wait <= 0;
if(avs_test_read) begin
r_wait_cnt <= r_wait_cnt + 1;
out_data <= r_data + avs_test_address;
end
else if(avs_test_write) begin
r_wait_cnt <= r_wait_cnt + 1;
case(avs_test_address)
0: begin
if(avs_test_byteenable[3]) r_data[31:24] <= avs_test_writedata[31:24];
if(avs_test_byteenable[2]) r_data[23:16] <= avs_test_writedata[23:16];
if(avs_test_byteenable[1]) r_data[15:8] <= avs_test_writedata[15:8];
if(avs_test_byteenable[0]) r_data[7:0] <= avs_test_writedata[7:0];
end
1: begin
if(avs_test_byteenable[3]) r_data[31:24] <= ~avs_test_writedata[31:24];
if(avs_test_byteenable[2]) r_data[23:16] <= ~avs_test_writedata[23:16];
if(avs_test_byteenable[1]) r_data[15:8] <= ~avs_test_writedata[15:8];
if(avs_test_byteenable[0]) r_data[7:0] <= ~avs_test_writedata[7:0];
end
default: begin
r_data <= 0;
end
endcase
end
else begin
if(r_wait_cnt > 0) r_wait_cnt <= r_wait_cnt + 1; else r_wait_cnt <= 0;
end
end
end
endmodule
|
// Name: WcaDownConverter.v
//
// Copyright(c) 2013 Loctronix Corporation
// http://www.loctronix.com
//
// This program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public License
// as published by the Free Software Foundation; either version 2
// of the License, or (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
// 12 bit DDC Decimator with half-band filter output.
module WcaDownConverter
(
input clock, // input Clock
input reset, // input reset
input enable, // input enable
input aclr, // clears state but not configuration.
input dstrobe_in, // input dstrobe_in
input wire [3:0] cfgflags, // input dynamic configuration mode.
input wire [23:0] iq_in, // input [23:0] diq_in
output wire [31:0] iq_out, // ouput [31:0] diq_out
output wire dstrobe_out, // ouput dstrobe_out
input wire [11:0] rbusCtrl, // Address and control lines(12 total) { addr[7:0], readEnable, writeEnable, dataStrobe, clkbus}
inout wire [7:0] rbusData // Tri-state I/O data.
);
parameter IF_FREQ_ADDR = 0;
parameter DECIM_RATE_ADDR = 1;
parameter MODE = 4'hF; //Dynamic configuration enabled by default.
//DDC Configuration Mode flags:
`define CORDIC_ENABLED 3'h1
`define CIC_ENABLED 3'h2
`define HBF_ENABLED 3'h4
`define DYNAMIC_CONFIG 4'h8
wire [11:0] icor_in = iq_in[11:0];
wire [11:0] qcor_in = iq_in[23:12];
wire [11:0] icic_in;
wire [11:0] qcic_in;
wire [15:0] ihb_in;
wire [15:0] qhb_in;
wire hbstrobe_in;
wire clearAll = reset | aclr;
//*****************************************************
// CORDIC Frequency Up/Down Conversion
//*****************************************************
generate if( (MODE & `CORDIC_ENABLED))
begin
wire [11:0] icor_out;
wire [11:0] qcor_out;
wire [31:0] phase;
//Generate Phase for frequency translation.
WcaPhaseGen #(IF_FREQ_ADDR, 32) phase_generator
(
.clock(clock), .reset(reset), .aclr(aclr), .enable(enable), .strobe(dstrobe_in),
.rbusCtrl(rbusCtrl), .rbusData(rbusData),
.phase(phase)
);
//Down conversion frequency must be in the 1Qn format (see cordic doc below). 2^n-1 = pi/2 and -2^n-1 = -pi/2
//The Cordic only supports values between this range so the phase accumulator must produce values within this range.
//We rotate quadrants and adjust phase to make work.
reg [11:0] X0;
reg [11:0] Y0;
reg [11:0] A0;
always @(posedge clock)
case({dstrobe_in, phase[31:30]})
3'b101 : //pi/2 to pi
begin
X0 <= #1 -qcor_in;
Y0 <= #1 icor_in;
A0 <= #1 phase[31:20] - 12'h400;
end
3'b110 : //-pi/2 to -pi
begin
X0 <= #1 qcor_in;
Y0 <= #1 -icor_in;
A0 <= #1 phase[31:20] + 12'h400;
end
3'b100: // 0 to pi/2
begin
X0 <= #1 icor_in;
Y0 <= #1 qcor_in;
A0 <= #1 phase [31:20];
end
3'b111: // 0 to -pi/2
begin
X0 <= #1 icor_in;
Y0 <= #1 qcor_in;
A0 <= #1 phase [31:20];
end
endcase
// CORDIC gain is about 1.64 and formulation requires that numbers have the format of 1Qn format
// where there are 1 sign bit plus 1 integer bits and n-1 fractional bits. For a 12 bit 2's complement number
// this means that n = 11: 1 sign bit, 1 integer bit, and 10 fractional. For 1Qn format, the maximum allowable
// range input is between -2^n-1 and 2^n-1; thus with 12 bits, the maximum range is -2^10 to 2^10 (-1024 to 1024).
// In a 12 bit system, -1024 = -1.0 and 1024 = 1.0. Converting between decimal and 1Qn is
//
// 1Qn = int(1024* float_val);
// float_val = 1Qn / 1024f;
//
// 2' Complement numbers need to be scaled to conform to this standard. If value magnitude in X and Y are > 1024 overflow
// can occur. This implementation does not scale the input so need to be careful.
//
WcaCordic12 #(12,12,0) cordic
(
.ngreset(1'b1), .clock(clock),.reset(clearAll), .strobeData( dstrobe_in),
.X0(X0), .Y0(Y0),.A0(A0),
.XN(icor_out), .YN(qcor_out), .AN()
);
//Enable dynamic selection of bypass if DYNAMIC_CONFIG ENABLED, otherwise hardwire.
wire bypassCordic = MODE[3] & cfgflags[0];
assign icic_in = (bypassCordic) ? icor_in : icor_out;
assign qcic_in = (bypassCordic) ? qcor_in : qcor_out;
end
else // bypass
begin
assign icic_in = icor_in;
assign qcic_in = qcor_in;
end
endgenerate
//*****************************************************
// CIC Decimator
//*****************************************************
wire [12:0] decim_rate;
wire newRateData;
//24bit Data Rate Configuration Register.
WcaWriteWordReg #(DECIM_RATE_ADDR) reg_decim_rate
(.reset(reset), .out( decim_rate), .nd(newRateData),
.rbusCtrl(rbusCtrl), .rbusData(rbusData) );
generate if(MODE & `CIC_ENABLED)
begin
wire [15:0] icic_out;
wire [15:0] qcic_out;
wire cic_strobe_out;
reg rnd;
//Synch the newRateData clock to a one pulse.
always @(posedge clock)
begin
if( reset) rnd <= 1'b0;
else rnd <= (~rnd & newRateData);
end
cic_decim cic_i (
.sclr(reset), // resets
.din(icic_in), // input [11 : 0] din
.nd(dstrobe_in), // input nd
.rate(decim_rate), // input [12 : 0] rate
.rate_we(rnd | aclr), // input rate_we
.clk(clock), // input clk
.dout(icic_out), // output [15 : 0] dout
.rdy(cic_strobe_out),// output rdy
.rfd()); // output rfd
cic_decim cic_q (
.sclr(reset), // resets
.din(qcic_in), // input [11 : 0] din
.nd(dstrobe_in), // input nd
.rate(decim_rate), // input [12 : 0] rate
.rate_we(rnd | aclr),// input rate_we
.clk(clock), // input clk
.dout(qcic_out), // output [15 : 0] dout
.rdy(), // output rdy
.rfd()); // output rfd
//Enable dynamic selection of bypass if DYNAMIC_CONFIG ENABLED, otherwise hardwire.
wire bypassCic = MODE[3] & cfgflags[1];
wire bypassCicStrobe = MODE[3] & cfgflags[2];
assign ihb_in = (bypassCic) ? {icic_in[11], icic_in[11], icic_in[11], icic_in[11], icic_in} : icic_out;
assign qhb_in = (bypassCic) ? {qcic_in[11], qcic_in[11], qcic_in[11], qcic_in[11], qcic_in} : qcic_out;
assign hbstrobe_in = (bypassCicStrobe) ? dstrobe_in : cic_strobe_out;
end
else
begin
assign ihb_in = {icic_in[11], icic_in[11], icic_in[11], icic_in[11], icic_in};
assign qhb_in = {qcic_in[11], qcic_in[11], qcic_in[11], qcic_in[11], qcic_in};
//Generate strobe given the rate provided by the user.
WcaDspStrobe lsdp_strobe_gen (
.clock(clock), .reset(clearAll), .enable(enable), .strobe_in(dstrobe_in),
.rate(decim_rate), .strobe_out(hbstrobe_in), .count( )
);
end
endgenerate
//*****************************************************
// Halfband filter
//*****************************************************
generate if((MODE & `HBF_ENABLED))
begin
wire [15:0] i_hb_out;
wire [15:0] q_hb_out;
wire dstrobe_hb_out;
//Implement strobe that tighens up when data is ready so we don't
//double clock.
/*
wire rdy;
reg hbstrobeout;
always @(posedge clock)
begin
if( reset) hbstrobeout <= 1'b0;
else hbstrobeout <= (rdy & ~hbstrobeout);
end
assign dstrobe_out = hbstrobeout;
*/
halfband_decim hb_i (
.clk(clock), // input clk
.sclr(clearAll),
.nd(hbstrobe_in), // input nd
.rfd(), // output rfd
.rdy(dstrobe_hb_out), // output rdy
.din(ihb_in), // input [15 : 0] din
.dout(i_hb_out)); // output [15 : 0] dout
halfband_decim hb_q(
.clk(clock), // input clk
.sclr(clearAll),
.nd(hbstrobe_in), // input nd
.rfd(), // output rfd
.rdy(), // output rdy
.din(qhb_in), // input [15 : 0] din
.dout(q_hb_out)); // output [15 : 0] dout
//Enable dynamic selection of bypass if DYNAMIC_CONFIG ENABLED, otherwise hardwire.
wire bypassHbf = MODE[3] & cfgflags[3];
assign iq_out[15:0] = (bypassHbf) ? ihb_in : i_hb_out ;
assign iq_out[31:16] = (bypassHbf) ? qhb_in : q_hb_out ;
assign dstrobe_out = (bypassHbf) ? hbstrobe_in : dstrobe_hb_out;
end
else
begin
assign iq_out[15:0] = ihb_in; //Map to high bits to preserve twos complement
assign iq_out[31:16] = qhb_in; //format.
assign dstrobe_out = hbstrobe_in;
end
endgenerate
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : board.v
// Version : 1.11
// Description: Top level testbench
//
//------------------------------------------------------------------------------
`timescale 1ns/1ns
`include "board_common.v"
`define SIMULATION
module board;
parameter REF_CLK_FREQ = 0; // 0 - 100 MHz, 1 - 125 MHz, 2 - 250 MHz
localparam REF_CLK_HALF_CYCLE = (REF_CLK_FREQ == 0) ? 5000 :
(REF_CLK_FREQ == 1) ? 4000 :
(REF_CLK_FREQ == 2) ? 2000 : 0;
integer i;
// System-level clock and reset
reg sys_rst_n;
wire ep_sys_clk;
wire rp_sys_clk;
//
// PCI-Express Serial Interconnect
//
wire [3:0] ep_pci_exp_txn;
wire [3:0] ep_pci_exp_txp;
wire [3:0] rp_pci_exp_txn;
wire [3:0] rp_pci_exp_txp;
//
// PCI-Express Endpoint Instance
//
xilinx_pcie_2_1_ep_7x # (
.PL_FAST_TRAIN("TRUE")
)
EP (
// SYS Inteface
.sys_clk_n(ep_sys_clk_n),
.sys_clk_p(ep_sys_clk_p),
.sys_rst_n(sys_rst_n),
`ifdef ENABLE_LEDS
// Misc signals
.led_0(),
.led_1(),
.led_2(),
`endif
// PCI-Express Interface
.pci_exp_txn(ep_pci_exp_txn),
.pci_exp_txp(ep_pci_exp_txp),
.pci_exp_rxn(rp_pci_exp_txn),
.pci_exp_rxp(rp_pci_exp_txp)
);
//
// PCI-Express Model Root Port Instance
//
xilinx_pcie_2_1_rport_7x # (
.REF_CLK_FREQ(0),
.PL_FAST_TRAIN("TRUE"),
.ALLOW_X8_GEN2("FALSE"),
.C_DATA_WIDTH(64),
.LINK_CAP_MAX_LINK_WIDTH(6'h04),
.DEVICE_ID(16'h7100),
.LINK_CAP_MAX_LINK_SPEED(4'h2),
.LINK_CTRL2_TARGET_LINK_SPEED(4'h2),
.DEV_CAP_MAX_PAYLOAD_SUPPORTED(3),
.TRN_DW("FALSE"),
.VC0_TX_LASTPACKET(30),
.VC0_RX_RAM_LIMIT(13'hFFF),
.VC0_CPL_INFINITE("TRUE"),
.VC0_TOTAL_CREDITS_PD(949),
.VC0_TOTAL_CREDITS_CD(973),
.USER_CLK_FREQ(3),
.USER_CLK2_DIV2("FALSE")
)
RP (
// SYS Inteface
.sys_clk(rp_sys_clk),
.sys_rst_n(sys_rst_n),
// PCI-Express Interface
.pci_exp_txn(rp_pci_exp_txn),
.pci_exp_txp(rp_pci_exp_txp),
.pci_exp_rxn(ep_pci_exp_txn),
.pci_exp_rxp(ep_pci_exp_txp)
);
sys_clk_gen # (
.halfcycle(REF_CLK_HALF_CYCLE),
.offset(0)
)
CLK_GEN_RP (
.sys_clk(rp_sys_clk)
);
sys_clk_gen_ds # (
.halfcycle(REF_CLK_HALF_CYCLE),
.offset(0)
)
CLK_GEN_EP (
.sys_clk_p(ep_sys_clk_p),
.sys_clk_n(ep_sys_clk_n)
);
initial begin
$display("[%t] : System Reset Asserted...", $realtime);
sys_rst_n = 1'b0;
for (i = 0; i < 500; i = i + 1) begin
@(posedge ep_sys_clk_p);
end
$display("[%t] : System Reset De-asserted...", $realtime);
sys_rst_n = 1'b1;
end
initial begin
if ($test$plusargs ("dump_all")) begin
`ifdef NCV // Cadence TRN dump
$recordsetup("design=board",
"compress",
"wrapsize=100M",
"version=1",
"run=1");
$recordvars();
`elsif VCS //Synopsys VPD dump
$vcdplusfile("board.vpd");
$vcdpluson;
$vcdplusglitchon;
$vcdplusflush;
`else
// Verilog VC dump
$dumpfile("board.vcd");
$dumpvars(0, board);
`endif
end
end
endmodule // BOARD
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of inst_eg_e
//
// Generated
// by: wig
// on: Mon Mar 22 13:27:59 2004
// cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: inst_eg_e.v,v 1.1 2004/04/06 10:50:55 wig Exp $
// $Date: 2004/04/06 10:50:55 $
// $Log: inst_eg_e.v,v $
// Revision 1.1 2004/04/06 10:50:55 wig
// Adding result/mde_tests
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.37 2003/12/23 13:25:21 abauer Exp
//
// Generator: mix_0.pl Revision: 1.26 , [email protected]
// (C) 2003 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of inst_eg_e
//
// No `defines in this module
module inst_eg_e
//
// Generated module inst_eg
//
(
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
endmodule
//
// End of Generated Module rtl of inst_eg_e
//
//
//!End of Module/s
// --------------------------------------------------------------
|
`define RegBankS8_NOP 4'h0
`define RegBankS8_RDO 4'h1
`define RegBankS8_LD0 4'h2
`define RegBankS8_LD1 4'h3
`define RegBankS8_LD2 4'h4
`define RegBankS8_LD3 4'h5
`define RegBankS8_LD4 4'h6
`define RegBankS8_LD5 4'h7
`define RegBankS8_LD6 4'h8
`define RegBankS8_LD7 4'h9
`define RegBankS8_State_Reset 2'h0
`define RegBankS8_State_Ready 2'h1
`define RegBankS8_State_Error 2'h2
module RegBankS8(clock,reset,inst,inst_en,out);
input wire clock;
input wire reset;
input wire [11:0] inst;
input wire inst_en;
output wire [7:0] out;
reg [1:0] s_State;
reg [2:0] s_OutSelect;
reg [7:0] s_Reg0;
reg [7:0] s_Reg1;
reg [7:0] s_Reg2;
reg [7:0] s_Reg3;
reg [7:0] s_Reg4;
reg [7:0] s_Reg5;
reg [7:0] s_Reg6;
reg [7:0] s_Reg7;
wire [7:0] i_Out;
wire [3:0] w_InstCode;
wire [7:0] w_InstImm;
wire [2:0] w_InstOutSelect;
reg [256*8-1:0] d_Input;
reg [256*8-1:0] d_State;
assign out = i_Out;
assign w_InstCode = inst[11:8];
assign w_InstImm = inst[7:0];
assign w_InstOutSelect = inst[2:0];
assign i_Out = s_OutSelect == 0 ? s_Reg0 :
s_OutSelect == 1 ? s_Reg1 :
s_OutSelect == 2 ? s_Reg2 :
s_OutSelect == 3 ? s_Reg3 :
s_OutSelect == 4 ? s_Reg4 :
s_OutSelect == 5 ? s_Reg5 :
s_OutSelect == 6 ? s_Reg6 :
s_Reg7;
always @ (posedge clock) begin
if (reset) begin
s_State <= `RegBankS8_State_Reset;
s_OutSelect <= 0;
s_Reg0 <= 0;
s_Reg1 <= 0;
s_Reg2 <= 0;
s_Reg3 <= 0;
s_Reg4 <= 0;
s_Reg5 <= 0;
s_Reg6 <= 0;
s_Reg7 <= 0;
end
else begin
case (s_State)
`RegBankS8_State_Reset: begin
s_State <= `RegBankS8_State_Ready;
s_OutSelect <= 0;
s_Reg0 <= 0;
s_Reg1 <= 0;
s_Reg2 <= 0;
s_Reg3 <= 0;
s_Reg4 <= 0;
s_Reg5 <= 0;
s_Reg6 <= 0;
s_Reg7 <= 0;
end
`RegBankS8_State_Ready: begin
if (inst_en) begin
case (w_InstCode)
`RegBankS8_NOP: begin
s_State <= `RegBankS8_State_Ready;
s_OutSelect <= s_OutSelect;
s_Reg0 <= s_Reg0;
s_Reg1 <= s_Reg1;
s_Reg2 <= s_Reg2;
s_Reg3 <= s_Reg3;
s_Reg4 <= s_Reg4;
s_Reg5 <= s_Reg5;
s_Reg6 <= s_Reg6;
s_Reg7 <= s_Reg7;
end
`RegBankS8_RDO: begin
s_State <= `RegBankS8_State_Ready;
s_OutSelect <= w_InstOutSelect;
s_Reg0 <= s_Reg0;
s_Reg1 <= s_Reg1;
s_Reg2 <= s_Reg2;
s_Reg3 <= s_Reg3;
s_Reg4 <= s_Reg4;
s_Reg5 <= s_Reg5;
s_Reg6 <= s_Reg6;
s_Reg7 <= s_Reg7;
end
`RegBankS8_LD0: begin
s_State <= `RegBankS8_State_Ready;
s_OutSelect <= s_OutSelect;
s_Reg0 <= w_InstImm;
s_Reg1 <= s_Reg1;
s_Reg2 <= s_Reg2;
s_Reg3 <= s_Reg3;
s_Reg4 <= s_Reg4;
s_Reg5 <= s_Reg5;
s_Reg6 <= s_Reg6;
s_Reg7 <= s_Reg7;
end
`RegBankS8_LD1: begin
s_State <= `RegBankS8_State_Ready;
s_OutSelect <= s_OutSelect;
s_Reg0 <= s_Reg0;
s_Reg1 <= w_InstImm;
s_Reg2 <= s_Reg2;
s_Reg3 <= s_Reg3;
s_Reg4 <= s_Reg4;
s_Reg5 <= s_Reg5;
s_Reg6 <= s_Reg6;
s_Reg7 <= s_Reg7;
end
`RegBankS8_LD2: begin
s_State <= `RegBankS8_State_Ready;
s_OutSelect <= s_OutSelect;
s_Reg0 <= s_Reg0;
s_Reg1 <= s_Reg1;
s_Reg2 <= w_InstImm;
s_Reg3 <= s_Reg3;
s_Reg4 <= s_Reg4;
s_Reg5 <= s_Reg5;
s_Reg6 <= s_Reg6;
s_Reg7 <= s_Reg7;
end
`RegBankS8_LD3: begin
s_State <= `RegBankS8_State_Ready;
s_OutSelect <= s_OutSelect;
s_Reg0 <= s_Reg0;
s_Reg1 <= s_Reg1;
s_Reg2 <= s_Reg2;
s_Reg3 <= w_InstImm;
s_Reg4 <= s_Reg4;
s_Reg5 <= s_Reg5;
s_Reg6 <= s_Reg6;
s_Reg7 <= s_Reg7;
end // case: `RegBankS8_LD3
`RegBankS8_LD4: begin
s_State <= `RegBankS8_State_Ready;
s_OutSelect <= s_OutSelect;
s_Reg0 <= s_Reg0;
s_Reg1 <= s_Reg1;
s_Reg2 <= s_Reg2;
s_Reg3 <= s_Reg3;
s_Reg4 <= w_InstImm;
s_Reg5 <= s_Reg5;
s_Reg6 <= s_Reg6;
s_Reg7 <= s_Reg7;
end // case: `RegBankS8_LD3
`RegBankS8_LD5: begin
s_State <= `RegBankS8_State_Ready;
s_OutSelect <= s_OutSelect;
s_Reg0 <= s_Reg0;
s_Reg1 <= s_Reg1;
s_Reg2 <= s_Reg2;
s_Reg3 <= s_Reg3;
s_Reg4 <= s_Reg4;
s_Reg5 <= w_InstImm;
s_Reg6 <= s_Reg6;
s_Reg7 <= s_Reg7;
end // case: `RegBankS8_LD3
`RegBankS8_LD6: begin
s_State <= `RegBankS8_State_Ready;
s_OutSelect <= s_OutSelect;
s_Reg0 <= s_Reg0;
s_Reg1 <= s_Reg1;
s_Reg2 <= s_Reg2;
s_Reg3 <= s_Reg3;
s_Reg4 <= s_Reg4;
s_Reg5 <= s_Reg5;
s_Reg6 <= w_InstImm;
s_Reg7 <= s_Reg7;
end // case: `RegBankS8_LD3
`RegBankS8_LD7: begin
s_State <= `RegBankS8_State_Ready;
s_OutSelect <= s_OutSelect;
s_Reg0 <= s_Reg0;
s_Reg1 <= s_Reg1;
s_Reg2 <= s_Reg2;
s_Reg3 <= s_Reg3;
s_Reg4 <= s_Reg4;
s_Reg5 <= s_Reg5;
s_Reg6 <= s_Reg6;
s_Reg7 <= w_InstImm;
end
default: begin
s_State <= `RegBankS8_State_Error;
s_OutSelect <= 0;
s_Reg0 <= 0;
s_Reg1 <= 0;
s_Reg2 <= 0;
s_Reg3 <= 0;
s_Reg4 <= 0;
s_Reg5 <= 0;
s_Reg6 <= 0;
s_Reg7 <= 0;
end
endcase // case (w_InstCode)
end // if (inst_en)
else begin
s_State <= `RegBankS8_State_Ready;
s_OutSelect <= s_OutSelect;
s_Reg0 <= s_Reg0;
s_Reg1 <= s_Reg1;
s_Reg2 <= s_Reg2;
s_Reg3 <= s_Reg3;
s_Reg4 <= s_Reg4;
s_Reg5 <= s_Reg5;
s_Reg6 <= s_Reg6;
s_Reg7 <= s_Reg7;
end // else: !if(inst_en)
end // case: `RegBankS8_State_Ready
`RegBankS8_State_Error: begin
s_State <= `RegBankS8_State_Error;
s_OutSelect <= 0;
s_Reg0 <= 0;
s_Reg1 <= 0;
s_Reg2 <= 0;
s_Reg3 <= 0;
s_Reg4 <= 0;
s_Reg5 <= 0;
s_Reg6 <= 0;
s_Reg7 <= 0;
end
default: begin
s_State <= `RegBankS8_State_Error;
s_OutSelect <= 0;
s_Reg0 <= 0;
s_Reg1 <= 0;
s_Reg2 <= 0;
s_Reg3 <= 0;
s_Reg4 <= 0;
s_Reg5 <= 0;
s_Reg6 <= 0;
s_Reg7 <= 0;
end
endcase // case (s_State)
end // else: !if(reset)
end // always @ (posedge clock)
`ifdef SIM
always @ * begin
if (inst_en) begin
case (w_InstCode)
`RegBankS8_NOP: begin
$sformat(d_Input,"EN NOP");
end
`RegBankS8_RDO: begin
$sformat(d_Input,"EN (RDO %1X)",w_InstOutSelect);
end
`RegBankS8_LD0: begin
$sformat(d_Input,"EN (LD0 %2X)",w_InstImm);
end
`RegBankS8_LD1: begin
$sformat(d_Input,"EN (LD1 %2X)",w_InstImm);
end
`RegBankS8_LD2: begin
$sformat(d_Input,"EN (LD2 %2X)",w_InstImm);
end
`RegBankS8_LD3: begin
$sformat(d_Input,"EN (LD3 %2X)",w_InstImm);
end
`RegBankS8_LD4: begin
$sformat(d_Input,"EN (LD4 %2X)",w_InstImm);
end
`RegBankS8_LD5: begin
$sformat(d_Input,"EN (LD5 %2X)",w_InstImm);
end
`RegBankS8_LD6: begin
$sformat(d_Input,"EN (LD6 %2X)",w_InstImm);
end
`RegBankS8_LD7: begin
$sformat(d_Input,"EN (LD7 %2X)",w_InstImm);
end
default: begin
$sformat(d_Input,"EN (? %2X)",w_InstImm);
end
endcase // case (w_InstCode)
end // if (inst_en)
else begin
$sformat(d_Input,"NN");
end // else: !if(inst_en)
end // always @ *
always @ * begin
case (s_State)
`RegBankS8_State_Reset: begin
$sformat(d_State,"X");
end
`RegBankS8_State_Ready: begin
$sformat(d_State,"R %1X %2X %2X %2X %2X %2X %2X %2X %2X",s_OutSelect,s_Reg0,s_Reg1,s_Reg2,s_Reg3,s_Reg4,s_Reg5,s_Reg6,s_Reg7);
end
`RegBankS8_State_Error: begin
$sformat(d_State,"E");
end
default: begin
$sformat(d_State,"?");
end
endcase // case (s_State)
end // always @ *
`endif // `ifdef SIM
endmodule // RegBankS8
|
`timescale 1ns/1ns
module usb_rx_sie
(input c,
input c_48,
input oe,
input vp,
input vm,
output [7:0] d,
output dv);
wire bit_d, bit_dv;
wire eop;
usb_rx_nrzi rx_nrzi_inst
(.c_48(c_48), .vp(vp), .vm(vm), .oe(oe), .d(bit_d), .dv(bit_dv), .eop(eop));
// todo: state machine to parse out the bytes and figure out when to
// expect crc16, etc., based on length of the inbound data stream
localparam ST_IDLE = 4'h0;
localparam ST_SYNC = 4'h1;
localparam ST_DATA = 4'h2;
localparam ST_EOP = 4'h3;
localparam ST_CHECK_CRC = 4'h4;
localparam ST_DRAIN = 4'h5; // drains the RX fifo out to busclk domain
localparam ST_DONE = 4'h6;
localparam ST_ERROR = 4'hf;
localparam SW=4, CW=5;
reg [CW+SW-1:0] ctrl;
wire [SW-1:0] state;
wire [SW-1:0] next_state = ctrl[SW+CW-1:CW];
r #(SW) state_r
(.c(c_48), .rst(oe), .en(1'b1), .d(next_state), .q(state));
wire [3:0] bit_cnt;
wire bit_cnt_rst;
r #(4) bit_cnt_r
(.c(c_48), .en(bit_dv), .rst(bit_cnt_rst), .d(bit_cnt+1'b1), .q(bit_cnt));
wire rx_byte_en = bit_dv;
wire [7:0] rx_byte;
r #(8) rx_byte_r
(.c(c_48), .en(rx_byte_en), .rst(1'b0),
.d({bit_d, rx_byte[7:1]}), .q(rx_byte));
wire [6:0] byte_cnt;
wire byte_cnt_en, byte_cnt_rst;
r #(7) byte_cnt_r
(.c(c_48), .en(byte_cnt_en), .rst(byte_cnt_rst),
.d(byte_cnt + 1'b1), .q(byte_cnt));
always @* begin
case (state)
ST_IDLE:
if (bit_dv) ctrl = { ST_SYNC , 5'b00000 };
else ctrl = { ST_IDLE , 5'b00001 };
ST_SYNC:
if (bit_cnt == 4'd8)
if (rx_byte == 8'h80 ) ctrl = { ST_DATA , 5'b00001 };
else ctrl = { ST_ERROR , 5'b00001 };
else ctrl = { ST_SYNC , 5'b00000 };
ST_DATA:
if (eop) ctrl = { ST_EOP , 5'b00001 };
else if (bit_cnt == 4'd8) ctrl = { ST_DATA , 5'b00011 };
else ctrl = { ST_DATA , 5'b00000 };
ST_EOP:
if (byte_cnt == 7'd0) ctrl = { ST_DONE , 5'b00000 }; // bad
else if (byte_cnt == 7'd1) ctrl = { ST_DRAIN , 5'b00100 }; // no crc
else ctrl = { ST_CHECK_CRC, 5'b00000 };
ST_CHECK_CRC: // TODO: actually check CRC
ctrl = { ST_DRAIN , 5'b00100 };
ST_DRAIN: ctrl = { ST_DONE , 5'b00000 };
ST_DONE: ctrl = { ST_IDLE , 5'b00000 };
ST_ERROR: ctrl = { ST_ERROR , 5'b00000 };
default: ctrl = { ST_IDLE , 5'b00000 };
endcase
end
assign bit_cnt_rst = ctrl[0];
wire fifo_wrreq = ctrl[1];
assign byte_cnt_en = ctrl[1];
assign byte_cnt_rst = state == ST_IDLE;
wire fifo_drain_start_48 = state == ST_DRAIN;
wire fifo_drain_start;
sync fifo_drain_start_sync_r
(.in(fifo_drain_start_48), .clk(c), .out(fifo_drain_start));
wire fifo_draining, fifo_rdempty;
r fifo_draining_r
(.c(c), .en(fifo_drain_start), .rst(fifo_rdempty),
.d(1'b1), .q(fifo_draining));
wire pkt_valid;
r pkt_valid_r
(.c(c_48), .en(ctrl[2]), .rst(state == ST_IDLE), .d(1'b1), .q(pkt_valid));
wire pkt_valid_s;
sync pkt_valid_sync_r(.in(pkt_valid), .clk(c), .out(pkt_valid_s));
wire pkt_valid_s_sticky;
r pkt_valid_s_sticky_r
(.c(c), .rst(fifo_rdempty), .en(pkt_valid_s),
.d(1'b1), .q(pkt_valid_s_sticky));
wire xclk_fifo_aclr;
sync xclk_fifo_aclr_sync_r
(.in(oe), .clk(c), .out(xclk_fifo_aclr));
wire [7:0] d_i;
dcfifo
#(.lpm_width(8), .lpm_widthu(7), .lpm_numwords(128), .lpm_showahead("ON"),
.use_eab("ON"), .intended_device_family("CYCLONE V")) xclk_fifo
(.wrclk(c_48), .data(rx_byte), .wrreq(fifo_wrreq),
.rdclk(c), .rdreq(fifo_draining & ~fifo_rdempty),
.q(d_i), .rdempty(fifo_rdempty),
.aclr(xclk_fifo_aclr)); //1'b0));
wire dv_i = pkt_valid_s_sticky & fifo_draining & ~fifo_rdempty;
// delay the output stream one clock to help timing
d1 dv_d1_r(.c(c), .d(dv_i), .q(dv));
d1 #(8) d_d1_r(.c(c), .d(d_i), .q(d));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A211O_4_V
`define SKY130_FD_SC_HS__A211O_4_V
/**
* a211o: 2-input AND into first input of 3-input OR.
*
* X = ((A1 & A2) | B1 | C1)
*
* Verilog wrapper for a211o with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__a211o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a211o_4 (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__a211o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a211o_4 (
X ,
A1,
A2,
B1,
C1
);
output X ;
input A1;
input A2;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__a211o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__A211O_4_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__O22A_FUNCTIONAL_V
`define SKY130_FD_SC_HVL__O22A_FUNCTIONAL_V
/**
* o22a: 2-input OR into both inputs of 2-input AND.
*
* X = ((A1 | A2) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__o22a (
X ,
A1,
A2,
B1,
B2
);
// Module ports
output X ;
input A1;
input A2;
input B1;
input B2;
// Local signals
wire or0_out ;
wire or1_out ;
wire and0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
or or1 (or1_out , B2, B1 );
and and0 (and0_out_X, or0_out, or1_out);
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__O22A_FUNCTIONAL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NAND4BB_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__NAND4BB_BEHAVIORAL_V
/**
* nand4bb: 4-input NAND, first two inputs inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__nand4bb (
Y ,
A_N,
B_N,
C ,
D
);
// Module ports
output Y ;
input A_N;
input B_N;
input C ;
input D ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nand0_out;
wire or0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out, D, C );
or or0 (or0_out_Y, B_N, A_N, nand0_out);
buf buf0 (Y , or0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NAND4BB_BEHAVIORAL_V
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : PCIEBus_axi_basic_rx_null_gen.v
// Version : 1.11
// //
// Description: //
// TRN to AXI RX null generator. Generates null packets for use in //
// discontinue situations. //
// //
// Notes: //
// Optional notes section. //
// //
// Hierarchical: //
// axi_basic_top //
// axi_basic_rx //
// axi_basic_rx_null_gen //
// //
//----------------------------------------------------------------------------//
`timescale 1ps/1ps
module PCIEBus_axi_basic_rx_null_gen # (
parameter C_DATA_WIDTH = 128, // RX/TX interface data width
parameter TCQ = 1, // Clock to Q time
// Do not override parameters below this line
parameter KEEP_WIDTH = C_DATA_WIDTH / 8 // KEEP width
) (
// AXI RX
//-----------
input [C_DATA_WIDTH-1:0] m_axis_rx_tdata, // RX data to user
input m_axis_rx_tvalid, // RX data is valid
input m_axis_rx_tready, // RX ready for data
input m_axis_rx_tlast, // RX data is last
input [21:0] m_axis_rx_tuser, // RX user signals
// Null Inputs
//-----------
output null_rx_tvalid, // NULL generated tvalid
output null_rx_tlast, // NULL generated tlast
output [KEEP_WIDTH-1:0] null_rx_tkeep, // NULL generated tkeep
output null_rdst_rdy, // NULL generated rdst_rdy
output reg [4:0] null_is_eof, // NULL generated is_eof
// System
//-----------
input user_clk, // user clock from block
input user_rst // user reset from block
);
localparam INTERFACE_WIDTH_DWORDS = (C_DATA_WIDTH == 128) ? 11'd4 :
(C_DATA_WIDTH == 64) ? 11'd2 : 11'd1;
//----------------------------------------------------------------------------//
// NULL packet generator state machine //
// This state machine shadows the AXI RX interface, tracking each packet as //
// it's passed to the AXI user. When a multi-cycle packet is detected, the //
// state machine automatically generates a "null" packet. In the event of a //
// discontinue, the RX pipeline can switch over to this null packet as //
// necessary. //
//----------------------------------------------------------------------------//
// State machine variables and states
localparam IDLE = 0;
localparam IN_PACKET = 1;
reg cur_state;
reg next_state;
// Signals for tracking a packet on the AXI interface
reg [11:0] reg_pkt_len_counter;
reg [11:0] pkt_len_counter;
wire [11:0] pkt_len_counter_dec;
wire pkt_done;
// Calculate packet fields, which are needed to determine total packet length.
wire [11:0] new_pkt_len;
wire [9:0] payload_len;
wire [1:0] packet_fmt;
wire packet_td;
reg [3:0] packet_overhead;
// Misc.
wire [KEEP_WIDTH-1:0] eof_tkeep;
wire straddle_sof;
wire eof;
// Create signals to detect sof and eof situations. These signals vary depending
// on data width.
assign eof = m_axis_rx_tuser[21];
generate
if(C_DATA_WIDTH == 128) begin : sof_eof_128
assign straddle_sof = (m_axis_rx_tuser[14:13] == 2'b11);
end
else begin : sof_eof_64_32
assign straddle_sof = 1'b0;
end
endgenerate
//----------------------------------------------------------------------------//
// Calculate the length of the packet being presented on the RX interface. To //
// do so, we need the relevent packet fields that impact total packet length. //
// These are: //
// - Header length: obtained from bit 1 of FMT field in 1st DWORD of header //
// - Payload length: obtained from LENGTH field in 1st DWORD of header //
// - TLP digest: obtained from TD field in 1st DWORD of header //
// - Current data: the number of bytes that have already been presented //
// on the data interface //
// //
// packet length = header + payload + tlp digest - # of DWORDS already //
// transmitted //
// //
// packet_overhead is where we calculate everything except payload. //
//----------------------------------------------------------------------------//
generate
if(C_DATA_WIDTH == 128) begin : len_calc_128
assign packet_fmt = straddle_sof ?
m_axis_rx_tdata[94:93] : m_axis_rx_tdata[30:29];
assign packet_td = straddle_sof ?
m_axis_rx_tdata[79] : m_axis_rx_tdata[15];
assign payload_len = packet_fmt[1] ?
(straddle_sof ? m_axis_rx_tdata[73:64] : m_axis_rx_tdata[9:0]) : 10'h0;
always @(*) begin
// In 128-bit mode, the amount of data currently on the interface
// depends on whether we're straddling or not. If so, 2 DWORDs have been
// seen. If not, 4 DWORDs.
case({packet_fmt[0], packet_td, straddle_sof})
// Header + TD - Data currently on interface
3'b0_0_0: packet_overhead = 4'd3 + 4'd0 - 4'd4;
3'b0_0_1: packet_overhead = 4'd3 + 4'd0 - 4'd2;
3'b0_1_0: packet_overhead = 4'd3 + 4'd1 - 4'd4;
3'b0_1_1: packet_overhead = 4'd3 + 4'd1 - 4'd2;
3'b1_0_0: packet_overhead = 4'd4 + 4'd0 - 4'd4;
3'b1_0_1: packet_overhead = 4'd4 + 4'd0 - 4'd2;
3'b1_1_0: packet_overhead = 4'd4 + 4'd1 - 4'd4;
3'b1_1_1: packet_overhead = 4'd4 + 4'd1 - 4'd2;
endcase
end
end
else if(C_DATA_WIDTH == 64) begin : len_calc_64
assign packet_fmt = m_axis_rx_tdata[30:29];
assign packet_td = m_axis_rx_tdata[15];
assign payload_len = packet_fmt[1] ? m_axis_rx_tdata[9:0] : 10'h0;
always @(*) begin
// 64-bit mode: no straddling, so always 2 DWORDs
case({packet_fmt[0], packet_td})
// Header + TD - Data currently on interface
2'b0_0: packet_overhead = 4'd3 + 4'd0 - 4'd2;
2'b0_1: packet_overhead = 4'd3 + 4'd1 - 4'd2;
2'b1_0: packet_overhead = 4'd4 + 4'd0 - 4'd2;
2'b1_1: packet_overhead = 4'd4 + 4'd1 - 4'd2;
endcase
end
end
else begin : len_calc_32
assign packet_fmt = m_axis_rx_tdata[30:29];
assign packet_td = m_axis_rx_tdata[15];
assign payload_len = packet_fmt[1] ? m_axis_rx_tdata[9:0] : 10'h0;
always @(*) begin
// 32-bit mode: no straddling, so always 1 DWORD
case({packet_fmt[0], packet_td})
// Header + TD - Data currently on interface
2'b0_0: packet_overhead = 4'd3 + 4'd0 - 4'd1;
2'b0_1: packet_overhead = 4'd3 + 4'd1 - 4'd1;
2'b1_0: packet_overhead = 4'd4 + 4'd0 - 4'd1;
2'b1_1: packet_overhead = 4'd4 + 4'd1 - 4'd1;
endcase
end
end
endgenerate
// Now calculate actual packet length, adding the packet overhead and the
// payload length. This is signed math, so sign-extend packet_overhead.
// NOTE: a payload length of zero means 1024 DW in the PCIe spec, but this
// behavior isn't supported in our block.
assign new_pkt_len =
{{9{packet_overhead[3]}}, packet_overhead[2:0]} + {2'b0, payload_len};
// Math signals needed in the state machine below. These are seperate wires to
// help ensure synthesis tools sre smart about optimizing them.
assign pkt_len_counter_dec = reg_pkt_len_counter - INTERFACE_WIDTH_DWORDS;
assign pkt_done = (reg_pkt_len_counter <= INTERFACE_WIDTH_DWORDS);
//----------------------------------------------------------------------------//
// Null generator Mealy state machine. Determine outputs based on: //
// 1) current st //
// 2) current inp //
//----------------------------------------------------------------------------//
always @(*) begin
case (cur_state)
// IDLE state: the interface is IDLE and we're waiting for a packet to
// start. If a packet starts, move to state IN_PACKET and begin tracking
// it as long as it's NOT a single cycle packet (indicated by assertion of
// eof at packet start)
IDLE: begin
if(m_axis_rx_tvalid && m_axis_rx_tready && !eof) begin
next_state = IN_PACKET;
end
else begin
next_state = IDLE;
end
pkt_len_counter = new_pkt_len;
end
// IN_PACKET: a mutli-cycle packet is in progress and we're tracking it. We
// are in lock-step with the AXI interface decrementing our packet length
// tracking reg, and waiting for the packet to finish.
//
// * If packet finished and a new one starts, this is a straddle situation.
// Next state is IN_PACKET (128-bit only).
// * If the current packet is done, next state is IDLE.
// * Otherwise, next state is IN_PACKET.
IN_PACKET: begin
// Straddle packet
if((C_DATA_WIDTH == 128) && straddle_sof && m_axis_rx_tvalid) begin
pkt_len_counter = new_pkt_len;
next_state = IN_PACKET;
end
// Current packet finished
else if(m_axis_rx_tready && pkt_done)
begin
pkt_len_counter = new_pkt_len;
next_state = IDLE;
end
// Packet in progress
else begin
if(m_axis_rx_tready) begin
// Not throttled
pkt_len_counter = pkt_len_counter_dec;
end
else begin
// Throttled
pkt_len_counter = reg_pkt_len_counter;
end
next_state = IN_PACKET;
end
end
default: begin
pkt_len_counter = reg_pkt_len_counter;
next_state = IDLE;
end
endcase
end
// Synchronous NULL packet generator state machine logic
always @(posedge user_clk) begin
if(user_rst) begin
cur_state <= #TCQ IDLE;
reg_pkt_len_counter <= #TCQ 12'h0;
end
else begin
cur_state <= #TCQ next_state;
reg_pkt_len_counter <= #TCQ pkt_len_counter;
end
end
// Generate tkeep/is_eof for an end-of-packet situation.
generate
if(C_DATA_WIDTH == 128) begin : strb_calc_128
always @(*) begin
// Assign null_is_eof depending on how many DWORDs are left in the
// packet.
case(pkt_len_counter)
10'd1: null_is_eof = 5'b10011;
10'd2: null_is_eof = 5'b10111;
10'd3: null_is_eof = 5'b11011;
10'd4: null_is_eof = 5'b11111;
default: null_is_eof = 5'b00011;
endcase
end
// tkeep not used in 128-bit interface
assign eof_tkeep = {KEEP_WIDTH{1'b0}};
end
else if(C_DATA_WIDTH == 64) begin : strb_calc_64
always @(*) begin
// Assign null_is_eof depending on how many DWORDs are left in the
// packet.
case(pkt_len_counter)
10'd1: null_is_eof = 5'b10011;
10'd2: null_is_eof = 5'b10111;
default: null_is_eof = 5'b00011;
endcase
end
// Assign tkeep to 0xFF or 0x0F depending on how many DWORDs are left in
// the current packet.
assign eof_tkeep = { ((pkt_len_counter == 12'd2) ? 4'hF:4'h0), 4'hF };
end
else begin : strb_calc_32
always @(*) begin
// is_eof is either on or off for 32-bit
if(pkt_len_counter == 12'd1) begin
null_is_eof = 5'b10011;
end
else begin
null_is_eof = 5'b00011;
end
end
// The entire DWORD is always valid in 32-bit mode, so tkeep is always 0xF
assign eof_tkeep = 4'hF;
end
endgenerate
// Finally, use everything we've generated to calculate our NULL outputs
assign null_rx_tvalid = 1'b1;
assign null_rx_tlast = (pkt_len_counter <= INTERFACE_WIDTH_DWORDS);
assign null_rx_tkeep = null_rx_tlast ? eof_tkeep : {KEEP_WIDTH{1'b1}};
assign null_rdst_rdy = null_rx_tlast;
endmodule
|
`timescale 1ns / 1ps
/*
Group Members: Kevin Ingram and Warren Seto
Lab Name: Traffic Light Controller (Lab 3)
Project Name: eng312_proj3
Design Name: Traffic_Test_A_eng312_proj3.v
Design Description: Verilog Test Bench to Implement Test A (3 AM)
*/
module Traffic_Test;
// Inputs
reg NS_VEHICLE_DETECT;
reg EW_VEHICLE_DETECT;
// Outputs
wire NS_RED;
wire NS_YELLOW;
wire NS_GREEN;
wire EW_RED;
wire EW_YELLOW;
wire EW_GREEN;
// Clock
reg clk;
// Counters
wire[4:0] count1;
wire[3:0] count2;
wire[1:0] count3;
// Counter Modules
nsCounter clock1(clk, count1); // Count a total of 32 seconds
ewCounter clock2(clk, count2); // Counts a total of 16 seconds
yellowCounter clock3(clk, count3); // Counts a total of 4 seconds
// Main Traffic Module
Traffic CORE (count1, count2, count3, NS_VEHICLE_DETECT, EW_VEHICLE_DETECT, NS_RED, NS_YELLOW, NS_GREEN, EW_RED, EW_YELLOW, EW_GREEN);
initial begin
clk = 0;
NS_VEHICLE_DETECT = 0;
EW_VEHICLE_DETECT = 0;
$display(" NS | EW ");
$display("R Y G R Y G ");
$monitor("%h %h %h %h %h %h", NS_RED, NS_YELLOW, NS_GREEN, EW_RED, EW_YELLOW, EW_GREEN);
#1000 $finish;
end
always begin
#1 clk = ~clk;
end
endmodule
|
// ledtest_hps_0_hps_io.v
// This file was auto-generated from altera_hps_io_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 17.0 595
`timescale 1 ps / 1 ps
module ledtest_hps_0_hps_io (
output wire [14:0] mem_a, // memory.mem_a
output wire [2:0] mem_ba, // .mem_ba
output wire mem_ck, // .mem_ck
output wire mem_ck_n, // .mem_ck_n
output wire mem_cke, // .mem_cke
output wire mem_cs_n, // .mem_cs_n
output wire mem_ras_n, // .mem_ras_n
output wire mem_cas_n, // .mem_cas_n
output wire mem_we_n, // .mem_we_n
output wire mem_reset_n, // .mem_reset_n
inout wire [31:0] mem_dq, // .mem_dq
inout wire [3:0] mem_dqs, // .mem_dqs
inout wire [3:0] mem_dqs_n, // .mem_dqs_n
output wire mem_odt, // .mem_odt
output wire [3:0] mem_dm, // .mem_dm
input wire oct_rzqin, // .oct_rzqin
output wire hps_io_emac1_inst_TX_CLK, // hps_io.hps_io_emac1_inst_TX_CLK
output wire hps_io_emac1_inst_TXD0, // .hps_io_emac1_inst_TXD0
output wire hps_io_emac1_inst_TXD1, // .hps_io_emac1_inst_TXD1
output wire hps_io_emac1_inst_TXD2, // .hps_io_emac1_inst_TXD2
output wire hps_io_emac1_inst_TXD3, // .hps_io_emac1_inst_TXD3
input wire hps_io_emac1_inst_RXD0, // .hps_io_emac1_inst_RXD0
inout wire hps_io_emac1_inst_MDIO, // .hps_io_emac1_inst_MDIO
output wire hps_io_emac1_inst_MDC, // .hps_io_emac1_inst_MDC
input wire hps_io_emac1_inst_RX_CTL, // .hps_io_emac1_inst_RX_CTL
output wire hps_io_emac1_inst_TX_CTL, // .hps_io_emac1_inst_TX_CTL
input wire hps_io_emac1_inst_RX_CLK, // .hps_io_emac1_inst_RX_CLK
input wire hps_io_emac1_inst_RXD1, // .hps_io_emac1_inst_RXD1
input wire hps_io_emac1_inst_RXD2, // .hps_io_emac1_inst_RXD2
input wire hps_io_emac1_inst_RXD3 // .hps_io_emac1_inst_RXD3
);
ledtest_hps_0_hps_io_border border (
.mem_a (mem_a), // memory.mem_a
.mem_ba (mem_ba), // .mem_ba
.mem_ck (mem_ck), // .mem_ck
.mem_ck_n (mem_ck_n), // .mem_ck_n
.mem_cke (mem_cke), // .mem_cke
.mem_cs_n (mem_cs_n), // .mem_cs_n
.mem_ras_n (mem_ras_n), // .mem_ras_n
.mem_cas_n (mem_cas_n), // .mem_cas_n
.mem_we_n (mem_we_n), // .mem_we_n
.mem_reset_n (mem_reset_n), // .mem_reset_n
.mem_dq (mem_dq), // .mem_dq
.mem_dqs (mem_dqs), // .mem_dqs
.mem_dqs_n (mem_dqs_n), // .mem_dqs_n
.mem_odt (mem_odt), // .mem_odt
.mem_dm (mem_dm), // .mem_dm
.oct_rzqin (oct_rzqin), // .oct_rzqin
.hps_io_emac1_inst_TX_CLK (hps_io_emac1_inst_TX_CLK), // hps_io.hps_io_emac1_inst_TX_CLK
.hps_io_emac1_inst_TXD0 (hps_io_emac1_inst_TXD0), // .hps_io_emac1_inst_TXD0
.hps_io_emac1_inst_TXD1 (hps_io_emac1_inst_TXD1), // .hps_io_emac1_inst_TXD1
.hps_io_emac1_inst_TXD2 (hps_io_emac1_inst_TXD2), // .hps_io_emac1_inst_TXD2
.hps_io_emac1_inst_TXD3 (hps_io_emac1_inst_TXD3), // .hps_io_emac1_inst_TXD3
.hps_io_emac1_inst_RXD0 (hps_io_emac1_inst_RXD0), // .hps_io_emac1_inst_RXD0
.hps_io_emac1_inst_MDIO (hps_io_emac1_inst_MDIO), // .hps_io_emac1_inst_MDIO
.hps_io_emac1_inst_MDC (hps_io_emac1_inst_MDC), // .hps_io_emac1_inst_MDC
.hps_io_emac1_inst_RX_CTL (hps_io_emac1_inst_RX_CTL), // .hps_io_emac1_inst_RX_CTL
.hps_io_emac1_inst_TX_CTL (hps_io_emac1_inst_TX_CTL), // .hps_io_emac1_inst_TX_CTL
.hps_io_emac1_inst_RX_CLK (hps_io_emac1_inst_RX_CLK), // .hps_io_emac1_inst_RX_CLK
.hps_io_emac1_inst_RXD1 (hps_io_emac1_inst_RXD1), // .hps_io_emac1_inst_RXD1
.hps_io_emac1_inst_RXD2 (hps_io_emac1_inst_RXD2), // .hps_io_emac1_inst_RXD2
.hps_io_emac1_inst_RXD3 (hps_io_emac1_inst_RXD3) // .hps_io_emac1_inst_RXD3
);
endmodule
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2013.4
// Copyright (C) 2013 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module zbroji_top (
aclk,
aresetn,
s_axi_HLS_ZBROJI_PERIPH_BUS_AWADDR,
s_axi_HLS_ZBROJI_PERIPH_BUS_AWVALID,
s_axi_HLS_ZBROJI_PERIPH_BUS_AWREADY,
s_axi_HLS_ZBROJI_PERIPH_BUS_WDATA,
s_axi_HLS_ZBROJI_PERIPH_BUS_WSTRB,
s_axi_HLS_ZBROJI_PERIPH_BUS_WVALID,
s_axi_HLS_ZBROJI_PERIPH_BUS_WREADY,
s_axi_HLS_ZBROJI_PERIPH_BUS_BRESP,
s_axi_HLS_ZBROJI_PERIPH_BUS_BVALID,
s_axi_HLS_ZBROJI_PERIPH_BUS_BREADY,
s_axi_HLS_ZBROJI_PERIPH_BUS_ARADDR,
s_axi_HLS_ZBROJI_PERIPH_BUS_ARVALID,
s_axi_HLS_ZBROJI_PERIPH_BUS_ARREADY,
s_axi_HLS_ZBROJI_PERIPH_BUS_RDATA,
s_axi_HLS_ZBROJI_PERIPH_BUS_RRESP,
s_axi_HLS_ZBROJI_PERIPH_BUS_RVALID,
s_axi_HLS_ZBROJI_PERIPH_BUS_RREADY,
interrupt
);
parameter C_S_AXI_HLS_ZBROJI_PERIPH_BUS_ADDR_WIDTH = 6;
parameter C_S_AXI_HLS_ZBROJI_PERIPH_BUS_DATA_WIDTH = 32;
input aclk ;
input aresetn ;
input [C_S_AXI_HLS_ZBROJI_PERIPH_BUS_ADDR_WIDTH - 1:0] s_axi_HLS_ZBROJI_PERIPH_BUS_AWADDR ;
input s_axi_HLS_ZBROJI_PERIPH_BUS_AWVALID ;
output s_axi_HLS_ZBROJI_PERIPH_BUS_AWREADY ;
input [C_S_AXI_HLS_ZBROJI_PERIPH_BUS_DATA_WIDTH - 1:0] s_axi_HLS_ZBROJI_PERIPH_BUS_WDATA ;
input [C_S_AXI_HLS_ZBROJI_PERIPH_BUS_DATA_WIDTH/8 - 1:0] s_axi_HLS_ZBROJI_PERIPH_BUS_WSTRB ;
input s_axi_HLS_ZBROJI_PERIPH_BUS_WVALID ;
output s_axi_HLS_ZBROJI_PERIPH_BUS_WREADY ;
output [2 - 1:0] s_axi_HLS_ZBROJI_PERIPH_BUS_BRESP ;
output s_axi_HLS_ZBROJI_PERIPH_BUS_BVALID ;
input s_axi_HLS_ZBROJI_PERIPH_BUS_BREADY ;
input [C_S_AXI_HLS_ZBROJI_PERIPH_BUS_ADDR_WIDTH - 1:0] s_axi_HLS_ZBROJI_PERIPH_BUS_ARADDR ;
input s_axi_HLS_ZBROJI_PERIPH_BUS_ARVALID ;
output s_axi_HLS_ZBROJI_PERIPH_BUS_ARREADY ;
output [C_S_AXI_HLS_ZBROJI_PERIPH_BUS_DATA_WIDTH - 1:0] s_axi_HLS_ZBROJI_PERIPH_BUS_RDATA ;
output [2 - 1:0] s_axi_HLS_ZBROJI_PERIPH_BUS_RRESP ;
output s_axi_HLS_ZBROJI_PERIPH_BUS_RVALID ;
input s_axi_HLS_ZBROJI_PERIPH_BUS_RREADY ;
output interrupt ;
wire aclk;
wire aresetn;
wire [C_S_AXI_HLS_ZBROJI_PERIPH_BUS_ADDR_WIDTH - 1:0] s_axi_HLS_ZBROJI_PERIPH_BUS_AWADDR;
wire s_axi_HLS_ZBROJI_PERIPH_BUS_AWVALID;
wire s_axi_HLS_ZBROJI_PERIPH_BUS_AWREADY;
wire [C_S_AXI_HLS_ZBROJI_PERIPH_BUS_DATA_WIDTH - 1:0] s_axi_HLS_ZBROJI_PERIPH_BUS_WDATA;
wire [C_S_AXI_HLS_ZBROJI_PERIPH_BUS_DATA_WIDTH/8 - 1:0] s_axi_HLS_ZBROJI_PERIPH_BUS_WSTRB;
wire s_axi_HLS_ZBROJI_PERIPH_BUS_WVALID;
wire s_axi_HLS_ZBROJI_PERIPH_BUS_WREADY;
wire [2 - 1:0] s_axi_HLS_ZBROJI_PERIPH_BUS_BRESP;
wire s_axi_HLS_ZBROJI_PERIPH_BUS_BVALID;
wire s_axi_HLS_ZBROJI_PERIPH_BUS_BREADY;
wire [C_S_AXI_HLS_ZBROJI_PERIPH_BUS_ADDR_WIDTH - 1:0] s_axi_HLS_ZBROJI_PERIPH_BUS_ARADDR;
wire s_axi_HLS_ZBROJI_PERIPH_BUS_ARVALID;
wire s_axi_HLS_ZBROJI_PERIPH_BUS_ARREADY;
wire [C_S_AXI_HLS_ZBROJI_PERIPH_BUS_DATA_WIDTH - 1:0] s_axi_HLS_ZBROJI_PERIPH_BUS_RDATA;
wire [2 - 1:0] s_axi_HLS_ZBROJI_PERIPH_BUS_RRESP;
wire s_axi_HLS_ZBROJI_PERIPH_BUS_RVALID;
wire s_axi_HLS_ZBROJI_PERIPH_BUS_RREADY;
wire interrupt;
wire [32 - 1:0] sig_zbroji_a;
wire [32 - 1:0] sig_zbroji_b;
wire sig_zbroji_ap_start;
wire sig_zbroji_ap_ready;
wire sig_zbroji_ap_done;
wire sig_zbroji_ap_idle;
wire [32 - 1:0] sig_zbroji_ap_return;
zbroji zbroji_U(
.a(sig_zbroji_a),
.b(sig_zbroji_b),
.ap_start(sig_zbroji_ap_start),
.ap_ready(sig_zbroji_ap_ready),
.ap_done(sig_zbroji_ap_done),
.ap_idle(sig_zbroji_ap_idle),
.ap_return(sig_zbroji_ap_return)
);
zbroji_HLS_ZBROJI_PERIPH_BUS_if #(
.C_ADDR_WIDTH(C_S_AXI_HLS_ZBROJI_PERIPH_BUS_ADDR_WIDTH),
.C_DATA_WIDTH(C_S_AXI_HLS_ZBROJI_PERIPH_BUS_DATA_WIDTH))
zbroji_HLS_ZBROJI_PERIPH_BUS_if_U(
.ACLK(aclk),
.ARESETN(aresetn),
.I_a(sig_zbroji_a),
.I_b(sig_zbroji_b),
.I_ap_start(sig_zbroji_ap_start),
.O_ap_ready(sig_zbroji_ap_ready),
.O_ap_done(sig_zbroji_ap_done),
.O_ap_idle(sig_zbroji_ap_idle),
.O_ap_return(sig_zbroji_ap_return),
.AWADDR(s_axi_HLS_ZBROJI_PERIPH_BUS_AWADDR),
.AWVALID(s_axi_HLS_ZBROJI_PERIPH_BUS_AWVALID),
.AWREADY(s_axi_HLS_ZBROJI_PERIPH_BUS_AWREADY),
.WDATA(s_axi_HLS_ZBROJI_PERIPH_BUS_WDATA),
.WSTRB(s_axi_HLS_ZBROJI_PERIPH_BUS_WSTRB),
.WVALID(s_axi_HLS_ZBROJI_PERIPH_BUS_WVALID),
.WREADY(s_axi_HLS_ZBROJI_PERIPH_BUS_WREADY),
.BRESP(s_axi_HLS_ZBROJI_PERIPH_BUS_BRESP),
.BVALID(s_axi_HLS_ZBROJI_PERIPH_BUS_BVALID),
.BREADY(s_axi_HLS_ZBROJI_PERIPH_BUS_BREADY),
.ARADDR(s_axi_HLS_ZBROJI_PERIPH_BUS_ARADDR),
.ARVALID(s_axi_HLS_ZBROJI_PERIPH_BUS_ARVALID),
.ARREADY(s_axi_HLS_ZBROJI_PERIPH_BUS_ARREADY),
.RDATA(s_axi_HLS_ZBROJI_PERIPH_BUS_RDATA),
.RRESP(s_axi_HLS_ZBROJI_PERIPH_BUS_RRESP),
.RVALID(s_axi_HLS_ZBROJI_PERIPH_BUS_RVALID),
.RREADY(s_axi_HLS_ZBROJI_PERIPH_BUS_RREADY),
.interrupt(interrupt));
endmodule
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2015.4
// Copyright (C) 2015 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1ns/1ps
module example_fadd_32ns_32ns_32_5_full_dsp
#(parameter
ID = 0,
NUM_STAGE = 5,
din0_WIDTH = 32,
din1_WIDTH = 32,
dout_WIDTH = 32
)(
input wire clk,
input wire reset,
input wire ce,
input wire [din0_WIDTH-1:0] din0,
input wire [din1_WIDTH-1:0] din1,
output wire [dout_WIDTH-1:0] dout
);
//------------------------Local signal-------------------
wire aclk;
wire aclken;
wire a_tvalid;
wire [31:0] a_tdata;
wire b_tvalid;
wire [31:0] b_tdata;
wire r_tvalid;
wire [31:0] r_tdata;
reg [din0_WIDTH-1:0] din0_buf1;
reg [din1_WIDTH-1:0] din1_buf1;
//------------------------Instantiation------------------
example_ap_fadd_3_full_dsp_32 example_ap_fadd_3_full_dsp_32_u (
.aclk ( aclk ),
.aclken ( aclken ),
.s_axis_a_tvalid ( a_tvalid ),
.s_axis_a_tdata ( a_tdata ),
.s_axis_b_tvalid ( b_tvalid ),
.s_axis_b_tdata ( b_tdata ),
.m_axis_result_tvalid ( r_tvalid ),
.m_axis_result_tdata ( r_tdata )
);
//------------------------Body---------------------------
assign aclk = clk;
assign aclken = ce;
assign a_tvalid = 1'b1;
assign a_tdata = din0_buf1==='bx ? 'b0 : din0_buf1;
assign b_tvalid = 1'b1;
assign b_tdata = din1_buf1==='bx ? 'b0 : din1_buf1;
assign dout = r_tdata;
always @(posedge clk) begin
if (ce) begin
din0_buf1 <= din0;
din1_buf1 <= din1;
end
end
endmodule
|
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: moon.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.1 Build 166 11/26/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module moon (
address,
clock,
q);
input [11:0] address;
input clock;
output [11:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [11:0] sub_wire0;
wire [11:0] q = sub_wire0[11:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({12{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "../sprites/moon.mif",
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 4096,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.widthad_a = 12,
altsyncram_component.width_a = 12,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "../sprites/moon.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "12"
// Retrieval info: PRIVATE: WidthData NUMERIC "12"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "../sprites/moon.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
// Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 12 0 @q_a 0 0 12 0
// Retrieval info: GEN_FILE: TYPE_NORMAL moon.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL moon.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL moon.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL moon.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL moon_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL moon_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 13:55:21 05/03/2016
// Design Name:
// Module Name: data_deal
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module data_deal(
clk,
rst_n,
data_in,
data_in_sign,
data_out,
data_out_sign,
data_valid,
data_ok
);
input clk;
input rst_n;
input [6:0] data_in;
input data_in_sign;
output [6:0] data_out;
output data_out_sign;
input data_valid;
output data_ok;
reg [6:0] data_reg;
reg [3:0] data_regnum;
reg data_ok;
reg [6:0] data_out;
reg data_out_sign;
always @(posedge clk or negedge rst_n)begin
if(!rst_n)begin
data_reg <= 7'h0;
data_regnum <= 4'h0;
data_ok <= 1'h0;
end
else if(data_regnum == 4'h8) begin
data_ok <= ((data_reg == 7'd28)||
(data_reg== 7'd36))?1'b1:1'b0;
end
else begin
data_regnum <= data_in_sign ? data_regnum + 1'b1 : data_regnum;
data_reg <= data_reg + (data_in_sign ? data_in : 7'h0);
end
end
always @(posedge clk or negedge rst_n)begin
if(!rst_n)begin
data_out_sign <= 1'b0;
data_out <= 'h0;
end
else if(data_regnum < 4'h7)begin
if(~data_out_sign & data_valid) data_out_sign <= 1'b1;
else data_out_sign <= 1'b0;
data_out <= ~data_out_sign & data_valid ? data_out + 1'b1 : data_out;
end
end
endmodule
|
//////////////////////////////////////////////////////////////////////////////////
//
// This file is part of the N64 RGB/YPbPr DAC project.
//
// Copyright (C) 2016-2018 by Peter Bartmann <[email protected]>
//
// N64 RGB/YPbPr DAC is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
//////////////////////////////////////////////////////////////////////////////////
//
// Company: Circuit-Board.de
// Engineer: borti4938
// (initial design file by Ikari_01)
//
// Module Name: n64rgbv2_top
// Project Name: N64 RGB DAC Mod
// Target Devices: several MaxII & MaxV devices
// Tool versions: Altera Quartus Prime
//
// Revision: 3.0
//
// Description:
//
// short description of N64s RGB and sync data demux
// -------------------------------------------------
//
// pulse shapes and their realtion to each other:
// VCLK (~50MHz, Numbers representing posedge count)
// ---. 3 .---. 0 .---. 1 .---. 2 .---. 3 .---
// |___| |___| |___| |___| |___|
// nDSYNC (~12.5MHz) .....
// -------. .-------------------.
// |_______| |_______
//
// more info: http://members.optusnet.com.au/eviltim/n64rgb/n64rgb.html
//
//
//////////////////////////////////////////////////////////////////////////////////
module n64rgbv2_top (
// N64 Video Input
VCLK,
nDSYNC,
D_i,
// Controller and Reset
nRST_io,
CTRL_i,
// Jumper
nSYNC_ON_GREEN,
n16bit_mode_t,
nVIDeBlur_t,
en_IGR_Rst_Func,
en_IGR_DeBl_16b_Func,
// Video output
nHSYNC,
nVSYNC,
nCSYNC,
nCLAMP,
R_o, // red data vector
G_o, // green data vector
B_o, // blue data vector
CLK_ADV712x,
nCSYNC_ADV712x,
nBLANK_ADV712x,
dummy_i
);
`include "vh/n64rgb_params.vh"
input VCLK;
input nDSYNC;
input [color_width-1:0] D_i;
inout nRST_io;
input CTRL_i;
input nSYNC_ON_GREEN;
input n16bit_mode_t;
input nVIDeBlur_t;
input en_IGR_Rst_Func;
input en_IGR_DeBl_16b_Func;
output reg nHSYNC;
output reg nVSYNC;
output reg nCSYNC;
output reg nCLAMP;
output reg [color_width:0] R_o;
output reg [color_width:0] G_o;
output reg [color_width:0] B_o;
output reg CLK_ADV712x;
output reg nCSYNC_ADV712x;
output reg nBLANK_ADV712x;
input [4:0] dummy_i;
// start of rtl
wire DRV_RST, n16bit_mode_o, nDeBlur_o;
wire nRST_int = nRST_io;
wire [3:0] vinfo_pass;
wire [`VDATA_FU_SLICE] vdata_r[0:1];
// housekeeping
// ============
n64rgb_hk hk_u(
.VCLK(VCLK),
.nRST(nRST_int),
.DRV_RST(DRV_RST),
.CTRL_i(CTRL_i),
.n64_480i(vinfo_pass[0]),
.n16bit_mode_t(n16bit_mode_t),
.nVIDeBlur_t(nVIDeBlur_t),
.en_IGR_Rst_Func(en_IGR_Rst_Func),
.en_IGR_DeBl_16b_Func(en_IGR_DeBl_16b_Func),
.n16bit_o(n16bit_mode_o),
.nDeBlur_o(nDeBlur_o)
);
// acquire vinfo
// =============
n64_vinfo_ext get_vinfo(
.VCLK(VCLK),
.nDSYNC(nDSYNC),
.Sync_pre(vdata_r[0][`VDATA_SY_SLICE]),
.Sync_cur(D_i[3:0]),
.vinfo_o(vinfo_pass)
);
// video data demux
// ================
n64_vdemux video_demux(
.VCLK(VCLK),
.nDSYNC(nDSYNC),
.D_i(D_i),
.demuxparams_i({vinfo_pass[3:1],nDeBlur_o,n16bit_mode_o}),
.vdata_r_0(vdata_r[0]),
.vdata_r_1(vdata_r[1])
);
// assign final outputs
// ====================
assign nRST_io = DRV_RST ? 1'b0 : 1'bz;
always @(*) begin
{nVSYNC,nCLAMP,nHSYNC,nCSYNC} <= vdata_r[1][`VDATA_SY_SLICE];
R_o <= {vdata_r[1][`VDATA_RE_SLICE],vdata_r[1][3*color_width-1]};
G_o <= {vdata_r[1][`VDATA_GR_SLICE],vdata_r[1][2*color_width-1]};
B_o <= {vdata_r[1][`VDATA_BL_SLICE],vdata_r[1][ color_width-1]};
CLK_ADV712x <= VCLK;
nCSYNC_ADV712x <= nSYNC_ON_GREEN ? 1'b0 : vdata_r[1][vdata_width-4];
nBLANK_ADV712x <= 1'b1;
end
endmodule
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.3
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1ns/1ps
module convolve_kernel_fbkb
#(parameter
ID = 1,
NUM_STAGE = 14,
din0_WIDTH = 32,
din1_WIDTH = 32,
dout_WIDTH = 32
)(
input wire clk,
input wire reset,
input wire ce,
input wire [din0_WIDTH-1:0] din0,
input wire [din1_WIDTH-1:0] din1,
output wire [dout_WIDTH-1:0] dout
);
//------------------------Local signal-------------------
wire aclk;
wire aclken;
wire a_tvalid;
wire [31:0] a_tdata;
wire b_tvalid;
wire [31:0] b_tdata;
wire r_tvalid;
wire [31:0] r_tdata;
reg [din0_WIDTH-1:0] din0_buf1;
reg [din1_WIDTH-1:0] din1_buf1;
reg ce_r;
wire [dout_WIDTH-1:0] dout_i;
reg [dout_WIDTH-1:0] dout_r;
//------------------------Instantiation------------------
convolve_kernel_ap_fadd_12_no_dsp_32 convolve_kernel_ap_fadd_12_no_dsp_32_u (
.aclk ( aclk ),
.aclken ( aclken ),
.s_axis_a_tvalid ( a_tvalid ),
.s_axis_a_tdata ( a_tdata ),
.s_axis_b_tvalid ( b_tvalid ),
.s_axis_b_tdata ( b_tdata ),
.m_axis_result_tvalid ( r_tvalid ),
.m_axis_result_tdata ( r_tdata )
);
//------------------------Body---------------------------
assign aclk = clk;
assign aclken = ce_r;
assign a_tvalid = 1'b1;
assign a_tdata = din0_buf1;
assign b_tvalid = 1'b1;
assign b_tdata = din1_buf1;
assign dout_i = r_tdata;
always @(posedge clk) begin
if (ce) begin
din0_buf1 <= din0;
din1_buf1 <= din1;
end
end
always @ (posedge clk) begin
ce_r <= ce;
end
always @ (posedge clk) begin
if (ce_r) begin
dout_r <= dout_i;
end
end
assign dout = ce_r?dout_i:dout_r;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__MUX2_1_V
`define SKY130_FD_SC_HD__MUX2_1_V
/**
* mux2: 2-input multiplexer.
*
* Verilog wrapper for mux2 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__mux2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__mux2_1 (
X ,
A0 ,
A1 ,
S ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A0 ;
input A1 ;
input S ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__mux2 base (
.X(X),
.A0(A0),
.A1(A1),
.S(S),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__mux2_1 (
X ,
A0,
A1,
S
);
output X ;
input A0;
input A1;
input S ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__mux2 base (
.X(X),
.A0(A0),
.A1(A1),
.S(S)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__MUX2_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__CONB_SYMBOL_V
`define SKY130_FD_SC_HVL__CONB_SYMBOL_V
/**
* conb: Constant value, low, high outputs.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__conb (
//# {{data|Data Signals}}
output HI,
output LO
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__CONB_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A311O_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__A311O_FUNCTIONAL_PP_V
/**
* a311o: 3-input AND into first input of 3-input OR.
*
* X = ((A1 & A2 & A3) | B1 | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__a311o (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out , A3, A1, A2 );
or or0 (or0_out_X , and0_out, C1, B1 );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__A311O_FUNCTIONAL_PP_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__XOR2_PP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__XOR2_PP_BLACKBOX_V
/**
* xor2: 2-input exclusive OR.
*
* X = A ^ B
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__xor2 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__XOR2_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NOR2_4_V
`define SKY130_FD_SC_MS__NOR2_4_V
/**
* nor2: 2-input NOR.
*
* Verilog wrapper for nor2 with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__nor2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__nor2_4 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__nor2 base (
.Y(Y),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__nor2_4 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__nor2 base (
.Y(Y),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__NOR2_4_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__TAPVPWRVGND_FUNCTIONAL_V
`define SKY130_FD_SC_LS__TAPVPWRVGND_FUNCTIONAL_V
/**
* tapvpwrvgnd: Substrate and well tap cell.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__tapvpwrvgnd ();
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__TAPVPWRVGND_FUNCTIONAL_V
|
// (sender) Each tile sends a packet to every tile.
// (receiver) The tile assert done_o, when it has received packets from everyone.
module test_tile
import test_pkg::*;
import bsg_noc_pkg::*;
#(parameter dims_p=2
, parameter x_cord_width_p=4
, parameter y_cord_width_p=3
, parameter num_tiles_x_p=16
, parameter num_tiles_y_p=8
, parameter data_width_p=32
, parameter ruche_factor_X_p=0
, parameter ruche_factor_Y_p=0
, parameter XY_order_p=1
, parameter dirs_lp=(dims_p*2)+1
, parameter link_sif_width_lp = `test_link_sif_width(data_width_p,x_cord_width_p,y_cord_width_p)
)
(
input clk_i
, input reset_i
, input [dirs_lp-1:W][link_sif_width_lp-1:0] link_i
, output [dirs_lp-1:W][link_sif_width_lp-1:0] link_o
, input [x_cord_width_p-1:0] my_x_i
, input [y_cord_width_p-1:0] my_y_i
, output logic done_o
);
typedef int fifo_els_arr_t[dirs_lp-1:0];
function fifo_els_arr_t get_fifo_els();
fifo_els_arr_t retval;
for (int i = 0; i < dirs_lp; i++) begin
retval[i] = 2;
end
return retval;
endfunction
localparam num_tiles_lp = num_tiles_x_p*num_tiles_y_p;
`declare_test_link_sif_s(data_width_p,x_cord_width_p,y_cord_width_p);
test_link_sif_s [dirs_lp-1:P] link_li;
test_link_sif_s [dirs_lp-1:P] link_lo;
assign link_li[dirs_lp-1:W] = link_i;
assign link_o = link_lo[dirs_lp-1:W];
test_packet_s packet_lo;
test_packet_s packet_li;
assign link_li[P].data = packet_li;
assign packet_lo = link_lo[P].data;
bsg_mesh_router_buffered #(
.width_p(`test_packet_width(data_width_p,x_cord_width_p,y_cord_width_p))
,.x_cord_width_p(x_cord_width_p)
,.y_cord_width_p(y_cord_width_p)
,.ruche_factor_X_p(ruche_factor_X_p)
,.ruche_factor_Y_p(ruche_factor_Y_p)
,.dims_p(dims_p)
,.fifo_els_p(get_fifo_els())
,.XY_order_p(XY_order_p)
) router (
.clk_i(clk_i)
,.reset_i(reset_i)
,.link_i(link_li)
,.link_o(link_lo)
,.my_x_i(my_x_i)
,.my_y_i(my_y_i)
);
wire [data_width_p-1:0] my_id = (data_width_p)'(my_x_i+(my_y_i*num_tiles_x_p));
// sender
logic [x_cord_width_p-1:0] curr_x_r, curr_x_n;
logic [y_cord_width_p-1:0] curr_y_r, curr_y_n;
integer send_count_r, send_count_n;
assign packet_li.x_cord = curr_x_r;
assign packet_li.y_cord = curr_y_r;
assign packet_li.data = my_id;
always_comb begin
send_count_n = send_count_r;
curr_x_n = curr_x_r;
curr_y_n = curr_y_r;
link_li[P].v = 1'b0;
if (send_count_r != num_tiles_lp) begin
link_li[P].v = 1'b1;
if (link_lo[P].ready_and_rev) begin
curr_x_n = (curr_x_r == num_tiles_x_p-1)
? '0
: (curr_x_r + 1);
curr_y_n = (curr_x_r == num_tiles_x_p-1)
? curr_y_r + 1
: curr_y_r;
send_count_n = send_count_r + 1;
end
end
else begin
link_li[P].v = 1'b0;
end
end
always_ff @ (posedge clk_i) begin
if (reset_i) begin
curr_x_r <= '0;
curr_y_r <= '0;
send_count_r <= '0;
end
else begin
curr_x_r <= curr_x_n;
curr_y_r <= curr_y_n;
send_count_r <= send_count_n;
end
end
// receiver
logic [num_tiles_lp-1:0] v_r, v_n;
assign link_li[P].ready_and_rev = 1'b1;
assign v_n = link_lo[P].v << packet_lo.data;
always_ff @ (posedge clk_i) begin
if (reset_i) begin
v_r <= '0;
end
else begin
for (integer i = 0; i < num_tiles_lp; i++) begin: l
if (v_n[i]) begin
v_r[i] <= 1'b1;
$display("(x,y)=(%2d,%2d) receiving id=%6d.", my_x_i, my_y_i, packet_lo.data);
end
end
// assert that packet arrived at correct dest.
if (link_lo[P].v) begin
assert((packet_lo.x_cord == my_x_i) & (packet_lo.y_cord == my_y_i)) else
$error("[BSG_ERROR] wrong packet (%0d, %0d) arrived at (%0d, %0d).",
packet_lo.x_cord, packet_lo.y_cord,
my_x_i, my_y_i
);
end
end
end
assign done_o = &v_r;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__EINVP_1_V
`define SKY130_FD_SC_LS__EINVP_1_V
/**
* einvp: Tri-state inverter, positive enable.
*
* Verilog wrapper for einvp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__einvp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__einvp_1 (
Z ,
A ,
TE ,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input A ;
input TE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__einvp base (
.Z(Z),
.A(A),
.TE(TE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__einvp_1 (
Z ,
A ,
TE
);
output Z ;
input A ;
input TE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__einvp base (
.Z(Z),
.A(A),
.TE(TE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__EINVP_1_V
|
(** * PE: Partial Evaluation *)
(* $Date: 2011-02-21 11:20:32 -0500 (Mon, 21 Feb 2011) $ *)
(* Chapter author/maintainer: Chung-chieh Shan *)
(** Equiv.v introduced constant folding as an example of a program
transformation and proved that it preserves the meaning of the
program. Constant folding operates on manifest constants such
as [ANum] expressions. For example, it simplifies the command
[Y ::= APlus (ANum 3) (ANum 1)] to the command [Y ::= ANum 4].
However, it does not propagate known constants along data flow.
For example, it does not simplify the sequence
[[
X ::= ANum 3; Y ::= APlus (AId X) (ANum 1)
]]
to
[[
X ::= ANum 3; Y ::= ANum 4
]]
because it forgets that [X] is [3] by the time it gets to [Y].
We naturally want to enhance constant folding so that it
propagates known constants and uses them to simplify programs.
Doing so constitutes a rudimentary form of _partial evaluation_.
As we will see, partial evaluation is so called because it is
like running a program, except only part of the program can be
evaluated because only part of the input to the program is known.
For example, we can only simplify the program
[[
X ::= ANum 3; Y ::= AMinus (APlus (AId X) (ANum 1)) (AId Y)
]]
to
[[
X ::= ANum 3; Y ::= AMinus (ANum 4) (AId Y)
]]
without knowing the initial value of [Y]. *)
Require Export Imp.
Require Import FunctionalExtensionality.
(* ####################################################### *)
(** * Generalizing Constant Folding *)
(** The starting point of partial evaluation is to represent our
partial knowledge about the state. For example, between the two
assignments above, the partial evaluator may know only that [X] is
[3] and nothing about any other variable. *)
(** ** Partial States *)
(** Conceptually speaking, we can think of such partial states as the
type [id -> option nat] (as opposed to the type [id -> nat] of
concrete, full states). However, in addition to looking up and
updating the values of individual variables in a partial state, we
may also want to compare two partial states to see if and where
they differ, to handle conditional control flow. It is not possible
to compare two arbitrary functions in this way, so we represent
partial states in a more concrete format: as a list of [id * nat]
pairs. *)
Definition pe_state := list (id * nat).
(** The idea is that a variable [id] appears in the list if and only
if we know its current [nat] value. The [pe_lookup] function thus
interprets this concrete representation. (If the same variable
[id] appears multiple times in the list, the first occurrence
wins, but we will define our partial evaluator to never construct
such a [pe_state].) *)
Fixpoint pe_lookup (pe_st : pe_state) (V:id) : option nat :=
match pe_st with
| [] => None
| (V',n')::pe_st => if beq_id V V' then Some n'
else pe_lookup pe_st V
end.
(** For example, [empty_pe_state] represents complete ignorance about
every variable -- the function that maps every [id] to [None]. *)
Definition empty_pe_state : pe_state := [].
(** More generally, if the [list] representing a [pe_state] does not
contain some [id], then that [pe_state] must map that [id] to
[None]. Before we prove this fact, we first define a useful
tactic for reasoning with [id] equality. The tactic
[[
compare V V' SCase
]]
means to reason by cases whether [beq_id V V'] is [true] or
[false]. In the case where [beq_id V V' = true], the tactic
substitutes [V] for [V'] throughout. *)
Tactic Notation "compare" ident(i) ident(j) ident(c) :=
let H := fresh "Heq" i j in
destruct (beq_id i j) as [|]eqn:H;
[ Case_aux c "equal"; symmetry in H; apply beq_id_eq in H; subst j
| Case_aux c "not equal" ].
Theorem pe_domain: forall pe_st V n,
pe_lookup pe_st V = Some n ->
true = existsb (beq_id V) (map (@fst _ _) pe_st).
Proof. intros pe_st V n H. induction pe_st as [| [V' n'] pe_st].
Case "[]". inversion H.
Case "::". simpl in H. simpl. compare V V' SCase; auto. Qed.
(** ** Arithmetic Expressions *)
(** Partial evaluation of [aexp] is straightforward -- it is basically
the same as constant folding, [fold_constants_aexp], except that
sometimes the partial state tells us the current value of a
variable and we can replace it by a constant expression. *)
Fixpoint pe_aexp (pe_st : pe_state) (a : aexp) : aexp :=
match a with
| ANum n => ANum n
| AId i => match pe_lookup pe_st i with (* <----- NEW *)
| Some n => ANum n
| None => AId i
end
| APlus a1 a2 =>
match (pe_aexp pe_st a1, pe_aexp pe_st a2) with
| (ANum n1, ANum n2) => ANum (n1 + n2)
| (a1', a2') => APlus a1' a2'
end
| AMinus a1 a2 =>
match (pe_aexp pe_st a1, pe_aexp pe_st a2) with
| (ANum n1, ANum n2) => ANum (n1 - n2)
| (a1', a2') => AMinus a1' a2'
end
| AMult a1 a2 =>
match (pe_aexp pe_st a1, pe_aexp pe_st a2) with
| (ANum n1, ANum n2) => ANum (n1 * n2)
| (a1', a2') => AMult a1' a2'
end
end.
(** This partial evaluator folds constants but does not apply the
associativity of addition. *)
Example test_pe_aexp1:
pe_aexp [(X,3)] (APlus (APlus (AId X) (ANum 1)) (AId Y))
= APlus (ANum 4) (AId Y).
Proof. reflexivity. Qed.
Example text_pe_aexp2:
pe_aexp [(Y,3)] (APlus (APlus (AId X) (ANum 1)) (AId Y))
= APlus (APlus (AId X) (ANum 1)) (ANum 3).
Proof. reflexivity. Qed.
(** Now, in what sense is [pe_aexp] correct? It is reasonable to
define the correctness of [pe_aexp] as follows: whenever a full
state [st:state] is _consistent_ with a partial state
[pe_st:pe_state] (in other words, every variable to which [pe_st]
assigns a value is assigned the same value by [st]), evaluating
[a] and evaluating [pe_aexp pe_st a] in [st] yields the same
result. This statement is indeed true. *)
Definition pe_consistent (st:state) (pe_st:pe_state) :=
forall V n, Some n = pe_lookup pe_st V -> st V = n.
Theorem pe_aexp_correct_weak: forall st pe_st, pe_consistent st pe_st ->
forall a, aeval st a = aeval st (pe_aexp pe_st a).
Proof. unfold pe_consistent. intros st pe_st H a.
aexp_cases (induction a) Case; simpl;
try reflexivity;
try (destruct (pe_aexp pe_st a1);
destruct (pe_aexp pe_st a2);
rewrite IHa1; rewrite IHa2; reflexivity).
(* Compared to fold_constants_aexp_sound,
the only interesting case is AId *)
Case "AId".
remember (pe_lookup pe_st i) as l. destruct l.
SCase "Some". rewrite H with (n:=n) by apply Heql. reflexivity.
SCase "None". reflexivity.
Qed.
(** However, we will soon want our partial evaluator to remove
assignments. For example, it will simplify
[[
X ::= ANum 3; Y ::= AMinus (AId X) (AId Y); X ::= ANum 4
]]
to just
[[
Y ::= AMinus (ANum 3) (AId Y); X ::= ANum 4
]]
by delaying the assignment to [X] until the end. To accomplish
this simplification, we need the result of partial evaluating
[[
pe_aexp [(X,3)] (AMinus (AId X) (AId Y))
]]
to be equal to [AMinus (ANum 3) (AId Y)] and _not_ the original
expression [AMinus (AId X) (AId Y)]. After all, it would be
incorrect, not just inefficient, to transform
[[
X ::= ANum 3; Y ::= AMinus (AId X) (AId Y); X ::= ANum 4
]]
to
[[
Y ::= AMinus (AId X) (AId Y); X ::= ANum 4
]]
even though the output expressions [AMinus (ANum 3) (AId Y)] and
[AMinus (AId X) (AId Y)] both satisfy the correctness criterion
that we just proved. Indeed, if we were to just define [pe_aexp
pe_st a = a] then the theorem [pe_aexp_correct'] would already
trivially hold.
Instead, we want to prove that the [pe_aexp] is correct in a
stronger sense: evaluating the expression produced by partial
evaluation ([aeval st (pe_aexp pe_st a)]) must not depend on those
parts of the full state [st] that are already specified in the
partial state [pe_st]. To be more precise, let us define a
function [pe_override], which updates [st] with the contents of
[pe_st]. In other words, [pe_override] carries out the
assignments listed in [pe_st] on top of [st]. *)
Fixpoint pe_override (st:state) (pe_st:pe_state) : state :=
match pe_st with
| [] => st
| (V,n)::pe_st => update (pe_override st pe_st) V n
end.
Example test_pe_override:
pe_override (update empty_state Y 1) [(X,3),(Z,2)]
= update (update (update empty_state Y 1) Z 2) X 3.
Proof. reflexivity. Qed.
(** Although [pe_override] operates on a concrete [list] representing
a [pe_state], its behavior is defined entirely by the [pe_lookup]
interpretation of the [pe_state]. *)
Theorem pe_override_correct: forall st pe_st V0,
pe_override st pe_st V0 =
match pe_lookup pe_st V0 with
| Some n => n
| None => st V0
end.
Proof. intros. induction pe_st as [| [V n] pe_st]. reflexivity.
simpl in *. unfold update. rewrite beq_id_sym.
compare V0 V Case; auto. Qed.
(** We can relate [pe_consistent] to [pe_override] in two ways.
First, overriding a state with a partial state always gives a
state that is consistent with the partial state. Second, if a
state is already consistent with a partial state, then overriding
the state with the partial state gives the same state. *)
Theorem pe_override_consistent: forall st pe_st,
pe_consistent (pe_override st pe_st) pe_st.
Proof. intros st pe_st V n H. rewrite pe_override_correct.
destruct (pe_lookup pe_st V); inversion H. reflexivity. Qed.
Theorem pe_consistent_override: forall st pe_st,
pe_consistent st pe_st -> forall V, st V = pe_override st pe_st V.
Proof. intros st pe_st H V. rewrite pe_override_correct.
remember (pe_lookup pe_st V) as l. destruct l; auto. Qed.
(** Now we can state and prove that [pe_aexp] is correct in the
stronger sense that will help us define the rest of the partial
evaluator.
Intuitively, running a program using partial evaluation is a
two-stage process. In the first, _static_ stage, we partially
evaluate the given program with respect to some partial state to
get a _residual_ program. In the second, _dynamic_ stage, we
evaluate the residual program with respect to the rest of the
state. This dynamic state provides values for those variables
that are unknown in the static (partial) state. Thus, the
residual program should be equivalent to _prepending_ the
assignments listed in the partial state to the original program. *)
Theorem pe_aexp_correct: forall (pe_st:pe_state) (a:aexp) (st:state),
aeval (pe_override st pe_st) a = aeval st (pe_aexp pe_st a).
Proof.
intros pe_st a st.
aexp_cases (induction a) Case; simpl;
try reflexivity;
try (destruct (pe_aexp pe_st a1);
destruct (pe_aexp pe_st a2);
rewrite IHa1; rewrite IHa2; reflexivity).
(* Compared to fold_constants_aexp_sound, the only
interesting case is AId. *)
rewrite pe_override_correct. destruct (pe_lookup pe_st i); reflexivity.
Qed.
(** ** Boolean Expressions *)
(** The partial evaluation of boolean expressions is similar. In
fact, it is entirely analogous to the constant folding of boolean
expressions, because our language has no boolean variables. *)
Fixpoint pe_bexp (pe_st : pe_state) (b : bexp) : bexp :=
match b with
| BTrue => BTrue
| BFalse => BFalse
| BEq a1 a2 =>
match (pe_aexp pe_st a1, pe_aexp pe_st a2) with
| (ANum n1, ANum n2) => if beq_nat n1 n2 then BTrue else BFalse
| (a1', a2') => BEq a1' a2'
end
| BLe a1 a2 =>
match (pe_aexp pe_st a1, pe_aexp pe_st a2) with
| (ANum n1, ANum n2) => if ble_nat n1 n2 then BTrue else BFalse
| (a1', a2') => BLe a1' a2'
end
| BNot b1 =>
match (pe_bexp pe_st b1) with
| BTrue => BFalse
| BFalse => BTrue
| b1' => BNot b1'
end
| BAnd b1 b2 =>
match (pe_bexp pe_st b1, pe_bexp pe_st b2) with
| (BTrue, BTrue) => BTrue
| (BTrue, BFalse) => BFalse
| (BFalse, BTrue) => BFalse
| (BFalse, BFalse) => BFalse
| (b1', b2') => BAnd b1' b2'
end
end.
Example test_pe_bexp1:
pe_bexp [(X,3)] (BNot (BLe (AId X) (ANum 3)))
= BFalse.
Proof. reflexivity. Qed.
Example test_pe_bexp2: forall b,
b = BNot (BLe (AId X) (APlus (AId X) (ANum 1))) ->
pe_bexp [] b = b.
Proof. intros b H. rewrite -> H. reflexivity. Qed.
(** The correctness of [pe_bexp] is analogous to the correctness of
[pe_aexp] above. *)
Theorem pe_bexp_correct: forall (pe_st:pe_state) (b:bexp) (st:state),
beval (pe_override st pe_st) b = beval st (pe_bexp pe_st b).
Proof.
intros pe_st b st.
bexp_cases (induction b) Case; simpl;
try reflexivity;
try (remember (pe_aexp pe_st a) as a';
remember (pe_aexp pe_st a0) as a0';
assert (Ha: aeval (pe_override st pe_st) a = aeval st a');
assert (Ha0: aeval (pe_override st pe_st) a0 = aeval st a0');
try (subst; apply pe_aexp_correct);
destruct a'; destruct a0'; rewrite Ha; rewrite Ha0;
simpl; try destruct (beq_nat n n0); try destruct (ble_nat n n0);
reflexivity);
try (destruct (pe_bexp pe_st b); rewrite IHb; reflexivity);
try (destruct (pe_bexp pe_st b1);
destruct (pe_bexp pe_st b2);
rewrite IHb1; rewrite IHb2; reflexivity).
Qed.
(* ####################################################### *)
(** * Partial Evaluation of Commands, Without Loops *)
(** What about the partial evaluation of commands? The analogy
between partial evaluation and full evaluation continues: Just as
full evaluation of a command turns an initial state into a final
state, partial evaluation of a command turns an initial partial
state into a final partial state. The difference is that, because
the state is partial, some parts of the command may not be
executable at the static stage. Therefore, just as [pe_aexp]
returns a residual [aexp] and [pe_bexp] returns a residual [bexp]
above, partially evaluating a command yields a residual command.
Another way in which our partial evaluator is similar to a full
evaluator is that it does not terminate on all commands. It is
not hard to build a partial evaluator that terminates on all
commands; what is hard is building a partial evaluator that
terminates on all commands yet automatically performs desired
optimizations such as unrolling loops. Often a partial evaluator
can be coaxed into terminating more often and performing more
optimizations by writing the source program differently so that
the separation between static and dynamic information becomes more
apparent. Such coaxing is the art of _binding-time improvement_.
The binding time of a variable tells when its value is known --
either "static", or "dynamic."
Anyway, for now we will just live with the fact that our partial
evaluator is not a total function from the source command and the
initial partial state to the residual command and the final
partial state. To model this non-termination, just as with the
full evaluation of commands, we use an inductively defined
relation. We write
[[
c1 / st || c1' / st'
]]
to mean that partially evaluating the source command [c1] in the
initial partial state [st] yields the residual command [c1'] and
the final partial state [st']. For example, we want something like
[[
(X ::= ANum 3 ; Y ::= AMult (AId Z) (APlus (AId X) (AId X)))
/ [] || (Y ::= AMult (AId Z) (ANum 6)) / [(X,3)]
]]
to hold. The assignment to [X] appears in the final partial state,
not the residual command. *)
(** ** Assignment *)
(** Let's start by considering how to partially evaluate an
assignment. The two assignments in the source program above needs
to be treated differently. The first assignment [X ::= ANum 3],
is _static_: its right-hand-side is a constant (more generally,
simplifies to a constant), so we should update our partial state
at [X] to [3] and produce no residual code. (Actually, we produce
a residual [SKIP].) The second assignment [Y ::= AMult (AId Z)
(APlus (AId X) (AId X))] is _dynamic_: its right-hand-side does
not simplify to a constant, so we should leave it in the residual
code and remove [Y], if present, from our partial state. To
implement these two cases, we define the functions [pe_add] and
[pe_remove]. Like [pe_override] above, these functions operate on
a concrete [list] representing a [pe_state], but the theorems
[pe_add_correct] and [pe_remove_correct] specify their behavior by
the [pe_lookup] interpretation of the [pe_state]. *)
Fixpoint pe_remove (pe_st:pe_state) (V:id) : pe_state :=
match pe_st with
| [] => []
| (V',n')::pe_st => if beq_id V V' then pe_remove pe_st V
else (V',n') :: pe_remove pe_st V
end.
Theorem pe_remove_correct: forall pe_st V V0,
pe_lookup (pe_remove pe_st V) V0
= if beq_id V V0 then None else pe_lookup pe_st V0.
Proof. intros pe_st V V0. induction pe_st as [| [V' n'] pe_st].
Case "[]". destruct (beq_id V V0); reflexivity.
Case "::". simpl. compare V V' SCase.
SCase "equal". rewrite IHpe_st.
replace (beq_id V0 V) with (beq_id V V0) by apply beq_id_sym.
destruct (beq_id V V0); reflexivity.
SCase "not equal". simpl. compare V0 V' SSCase.
SSCase "equal". rewrite HeqVV'. reflexivity.
SSCase "not equal". rewrite IHpe_st. reflexivity.
Qed.
Definition pe_add (pe_st:pe_state) (V:id) (n:nat) : pe_state :=
(V,n) :: pe_remove pe_st V.
Theorem pe_add_correct: forall pe_st V n V0,
pe_lookup (pe_add pe_st V n) V0
= if beq_id V V0 then Some n else pe_lookup pe_st V0.
Proof. intros pe_st V n V0. unfold pe_add. simpl. rewrite beq_id_sym.
compare V V0 Case.
Case "equal". reflexivity.
Case "not equal". rewrite pe_remove_correct. rewrite HeqVV0. reflexivity.
Qed.
(** We will use the two theorems below to show that our partial
evaluator correctly deals with dynamic assignments and static
assignments, respectively. *)
Theorem pe_override_update_remove: forall st pe_st V n,
update (pe_override st pe_st) V n =
pe_override (update st V n) (pe_remove pe_st V).
Proof. intros st pe_st V n. apply functional_extensionality. intros V0.
unfold update. rewrite !pe_override_correct. rewrite pe_remove_correct.
destruct (beq_id V V0); reflexivity. Qed.
Theorem pe_override_update_add: forall st pe_st V n,
update (pe_override st pe_st) V n =
pe_override st (pe_add pe_st V n).
Proof. intros st pe_st V n. apply functional_extensionality. intros V0.
unfold update. rewrite !pe_override_correct. rewrite pe_add_correct.
destruct (beq_id V V0); reflexivity. Qed.
(** ** Conditional *)
(** Trickier than assignments to partially evaluate is the
conditional, [IFB b1 THEN c1 ELSE c2 FI]. If [b1] simplifies to
[BTrue] or [BFalse] then it's easy: we know which branch will be
taken, so just take that branch. If [b1] does not simplify to a
constant, then we need to take both branches, and the final
partial state may differ between the two branches!
The following program illustrates the difficulty:
[[
X ::= ANum 3;
IFB BLe (AId Y) (ANum 4) THEN
Y ::= ANum 4;
IFB BEq (AId X) (AId Y) THEN Y ::= ANum 999 ELSE SKIP FI
ELSE SKIP FI
]]
Suppose the initial partial state is empty. We don't know
statically how [Y] compares to [4], so we must partially evaluate
both branches of the (outer) conditional. On the [THEN] branch,
we know that [Y] is set to [4] and can even use that knowledge to
simplify the code somewhat. On the [ELSE] branch, we still don't
know the exact value of [Y] at the end. What should the final
partial state and residual program be?
One way to handle such a dynamic conditional is to take the
intersection of the final partial states of the two branches. In
this example, we take the intersection of [(Y,4),(X,3)] and
[(X,3)], so the overall final partial state is [(X,3)]. To
compensate for forgetting that [Y] is [4], we need to add an
assignment [Y ::= ANum 4] to the end of the [THEN] branch. So,
the residual program will be something like
[[
SKIP;
IFB BLe (AId Y) (ANum 4) THEN
SKIP;
SKIP;
Y ::= ANum 4
ELSE SKIP FI
]]
Programming this case in Coq calls for several auxiliary
functions: we need to compute the intersection of two [pe_state]s
and turn their difference into sequences of assignments.
First, we show how to compute whether two [pe_state]s to disagree
at a given variable. In the theorem [pe_disagree_domain], we
prove that two [pe_state]s can only disagree at variables that
appear in at least one of them. *)
Definition pe_disagree_at (pe_st1 pe_st2 : pe_state) (V:id) : bool :=
match pe_lookup pe_st1 V, pe_lookup pe_st2 V with
| Some x, Some y => negb (beq_nat x y)
| None, None => false
| _, _ => true
end.
Lemma existsb_app: forall X (f:X->bool) l1 l2,
existsb f (l1 ++ l2) = orb (existsb f l1) (existsb f l2).
Proof. intros X f l1 l2. induction l1. reflexivity.
simpl. rewrite IHl1. rewrite orb_assoc. reflexivity. Qed.
Theorem pe_disagree_domain: forall (pe_st1 pe_st2 : pe_state) (V:id),
true = pe_disagree_at pe_st1 pe_st2 V ->
true = existsb (beq_id V) (map (@fst _ _) pe_st1 ++
map (@fst _ _) pe_st2).
Proof. unfold pe_disagree_at. intros pe_st1 pe_st2 V H.
rewrite existsb_app. symmetry. apply orb_true_intro.
remember (pe_lookup pe_st1 V) as lookup1.
destruct lookup1 as [n1|]. left. symmetry. apply pe_domain with n1. auto.
remember (pe_lookup pe_st2 V) as lookup2.
destruct lookup2 as [n2|]. right. symmetry. apply pe_domain with n2. auto.
inversion H. Qed.
(** We define the [pe_compare] function to list the variables where
two given [pe_state]s disagree. This list is exact, according to
the theorem [pe_compare_correct]: a variable appears on the list
if and only if the two given [pe_state]s disagree at that
variable. Furthermore, we use the [pe_unique] function to
eliminate duplicates from the list. *)
Fixpoint pe_unique (l : list id) : list id :=
match l with
| [] => []
| x::l => x :: filter (fun y => negb (beq_id x y)) (pe_unique l)
end.
Lemma existsb_beq_id_filter: forall V f l,
existsb (beq_id V) (filter f l) = andb (existsb (beq_id V) l) (f V).
Proof. intros V f l. induction l as [| h l].
Case "[]". reflexivity.
Case "h::l". simpl. remember (f h) as fh. destruct fh.
SCase "true = f h". simpl. rewrite IHl. compare V h SSCase.
rewrite <- Heqfh. reflexivity. reflexivity.
SCase "false = f h". rewrite IHl. compare V h SSCase.
rewrite <- Heqfh. rewrite !andb_false_r. reflexivity. reflexivity.
Qed.
Theorem pe_unique_correct: forall l x,
existsb (beq_id x) l = existsb (beq_id x) (pe_unique l).
Proof. intros l x. induction l as [| h t]. reflexivity.
simpl in *. compare x h Case.
Case "equal". reflexivity.
Case "not equal".
rewrite -> existsb_beq_id_filter, <- IHt, -> beq_id_sym, -> Heqxh,
-> andb_true_r. reflexivity. Qed.
Definition pe_compare (pe_st1 pe_st2 : pe_state) : list id :=
pe_unique (filter (pe_disagree_at pe_st1 pe_st2)
(map (@fst _ _) pe_st1 ++ map (@fst _ _) pe_st2)).
Theorem pe_compare_correct: forall pe_st1 pe_st2 V,
pe_lookup pe_st1 V = pe_lookup pe_st2 V <->
false = existsb (beq_id V) (pe_compare pe_st1 pe_st2).
Proof. intros pe_st1 pe_st2 V.
unfold pe_compare. rewrite <- pe_unique_correct, -> existsb_beq_id_filter.
split; intros Heq.
Case "->".
symmetry. apply andb_false_intro2. unfold pe_disagree_at. rewrite Heq.
destruct (pe_lookup pe_st2 V).
rewrite <- beq_nat_refl. reflexivity.
reflexivity.
Case "<-".
assert (Hagree: pe_disagree_at pe_st1 pe_st2 V = false).
SCase "Proof of assertion".
remember (pe_disagree_at pe_st1 pe_st2 V) as disagree.
destruct disagree; [| reflexivity].
rewrite -> andb_true_r, <- pe_disagree_domain in Heq.
inversion Heq.
apply Heqdisagree.
unfold pe_disagree_at in Hagree.
destruct (pe_lookup pe_st1 V) as [n1|];
destruct (pe_lookup pe_st2 V) as [n2|];
try reflexivity; try solve by inversion.
rewrite beq_nat_eq with n1 n2. reflexivity.
rewrite <- negb_involutive. rewrite Hagree. reflexivity. Qed.
(** The intersection of two partial states is the result of removing
from one of them all the variables where the two disagree. We
define the function [pe_removes], in terms of [pe_remove] above,
to perform such a removal of a whole list of variables at once.
The theorem [pe_compare_removes] testifies that the [pe_lookup]
interpretation of the result of this intersection operation is the
same no matter which of the two partial states we remove the
variables from. Because [pe_override] only depends on the
[pe_lookup] interpretation of partial states, [pe_override] also
does not care which of the two partial states we remove the
variables from; that theorem [pe_compare_override] is used in the
correctness proof shortly. *)
Fixpoint pe_removes (pe_st:pe_state) (ids : list id) : pe_state :=
match ids with
| [] => pe_st
| V::ids => pe_remove (pe_removes pe_st ids) V
end.
Theorem pe_removes_correct: forall pe_st ids V,
pe_lookup (pe_removes pe_st ids) V =
if existsb (beq_id V) ids then None else pe_lookup pe_st V.
Proof. intros pe_st ids V. induction ids as [| V' ids]. reflexivity.
simpl. rewrite pe_remove_correct. rewrite IHids.
replace (beq_id V' V) with (beq_id V V') by apply beq_id_sym.
destruct (beq_id V V'); destruct (existsb (beq_id V) ids); reflexivity.
Qed.
Theorem pe_compare_removes: forall pe_st1 pe_st2 V,
pe_lookup (pe_removes pe_st1 (pe_compare pe_st1 pe_st2)) V =
pe_lookup (pe_removes pe_st2 (pe_compare pe_st1 pe_st2)) V.
Proof. intros pe_st1 pe_st2 V. rewrite !pe_removes_correct.
remember (existsb (beq_id V) (pe_compare pe_st1 pe_st2)) as b.
destruct b. reflexivity.
apply pe_compare_correct in Heqb. apply Heqb. Qed.
Theorem pe_compare_override: forall pe_st1 pe_st2 st,
pe_override st (pe_removes pe_st1 (pe_compare pe_st1 pe_st2)) =
pe_override st (pe_removes pe_st2 (pe_compare pe_st1 pe_st2)).
Proof. intros. apply functional_extensionality. intros V.
rewrite !pe_override_correct. rewrite pe_compare_removes. reflexivity.
Qed.
(** Finally, we define an [assign] function to turn the difference
between two partial states into a sequence of assignment commands.
More precisely, [assign pe_st ids] generates an assignment command
for each variable listed in [ids]. *)
Fixpoint assign (pe_st : pe_state) (ids : list id) : com :=
match ids with
| [] => SKIP
| V::ids => match pe_lookup pe_st V with
| Some n => (assign pe_st ids; V ::= ANum n)
| None => assign pe_st ids
end
end.
(** The command generated by [assign] always terminates, because it is
just a sequence of assignments. The (total) function [assigned]
below computes the effect of the command on the (dynamic state).
The theorem [assign_removes] then confirms that the generated
assignments perfectly compensate for removing the variables from
the partial state. *)
Definition assigned (pe_st:pe_state) (ids : list id) (st:state) : state :=
fun V => match existsb (beq_id V) ids, pe_lookup pe_st V with
| true, Some n => n
| _, _ => st V
end.
Theorem assign_removes: forall pe_st ids st,
pe_override st pe_st =
pe_override (assigned pe_st ids st) (pe_removes pe_st ids).
Proof. intros pe_st ids st. apply functional_extensionality. intros V.
rewrite !pe_override_correct. rewrite pe_removes_correct. unfold assigned.
destruct (existsb (beq_id V)); destruct (pe_lookup pe_st V); reflexivity.
Qed.
Lemma ceval_extensionality: forall c st st1 st2,
c / st || st1 -> (forall V, st1 V = st2 V) -> c / st || st2.
Proof. intros c st st1 st2 H Heq.
apply functional_extensionality in Heq. rewrite <- Heq. apply H. Qed.
Theorem eval_assign: forall pe_st ids st,
assign pe_st ids / st || assigned pe_st ids st.
Proof. intros pe_st ids st. induction ids as [| V ids]; simpl.
Case "[]". eapply ceval_extensionality. apply E_Skip. reflexivity.
Case "V::ids".
remember (pe_lookup pe_st V) as lookup. destruct lookup.
SCase "Some". eapply E_Seq. apply IHids. unfold assigned. simpl.
eapply ceval_extensionality. apply E_Ass. simpl. reflexivity.
intros V0. unfold update. rewrite beq_id_sym. compare V0 V SSCase.
SSCase "equal". rewrite <- Heqlookup. reflexivity.
SSCase "not equal". reflexivity.
SCase "None". eapply ceval_extensionality. apply IHids.
unfold assigned. intros V0. simpl. compare V0 V SSCase.
SSCase "equal". rewrite <- Heqlookup.
destruct (existsb (beq_id V0) ids); reflexivity.
SSCase "not equal". reflexivity. Qed.
(** ** The Partial Evaluation Relation *)
(** At long last, we can define a partial evaluator for commands
without loops, as an inductive relation! The inequality
conditions in [PE_AssDynamic] and [PE_If] are just to keep the
partial evaluator deterministic; they are not required for
correctness. *)
Reserved Notation "c1 '/' st '||' c1' '/' st'"
(at level 40, st at level 39, c1' at level 39).
Inductive pe_com : com -> pe_state -> com -> pe_state -> Prop :=
| PE_Skip : forall pe_st,
SKIP / pe_st || SKIP / pe_st
| PE_AssStatic : forall pe_st a1 n1 l,
pe_aexp pe_st a1 = ANum n1 ->
(l ::= a1) / pe_st || SKIP / pe_add pe_st l n1
| PE_AssDynamic : forall pe_st a1 a1' l,
pe_aexp pe_st a1 = a1' ->
(forall n, a1' <> ANum n) ->
(l ::= a1) / pe_st || (l ::= a1') / pe_remove pe_st l
| PE_Seq : forall pe_st pe_st' pe_st'' c1 c2 c1' c2',
c1 / pe_st || c1' / pe_st' ->
c2 / pe_st' || c2' / pe_st'' ->
(c1 ; c2) / pe_st || (c1' ; c2') / pe_st''
| PE_IfTrue : forall pe_st pe_st' b1 c1 c2 c1',
pe_bexp pe_st b1 = BTrue ->
c1 / pe_st || c1' / pe_st' ->
(IFB b1 THEN c1 ELSE c2 FI) / pe_st || c1' / pe_st'
| PE_IfFalse : forall pe_st pe_st' b1 c1 c2 c2',
pe_bexp pe_st b1 = BFalse ->
c2 / pe_st || c2' / pe_st' ->
(IFB b1 THEN c1 ELSE c2 FI) / pe_st || c2' / pe_st'
| PE_If : forall pe_st pe_st1 pe_st2 b1 c1 c2 c1' c2',
pe_bexp pe_st b1 <> BTrue ->
pe_bexp pe_st b1 <> BFalse ->
c1 / pe_st || c1' / pe_st1 ->
c2 / pe_st || c2' / pe_st2 ->
(IFB b1 THEN c1 ELSE c2 FI) / pe_st
|| (IFB pe_bexp pe_st b1
THEN c1' ; assign pe_st1 (pe_compare pe_st1 pe_st2)
ELSE c2' ; assign pe_st2 (pe_compare pe_st1 pe_st2) FI)
/ pe_removes pe_st1 (pe_compare pe_st1 pe_st2)
where "c1 '/' st '||' c1' '/' st'" := (pe_com c1 st c1' st').
Tactic Notation "pe_com_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "PE_Skip"
| Case_aux c "PE_AssStatic" | Case_aux c "PE_AssDynamic"
| Case_aux c "PE_Seq"
| Case_aux c "PE_IfTrue" | Case_aux c "PE_IfFalse" | Case_aux c "PE_If" ].
Hint Constructors pe_com.
Hint Constructors ceval.
(** ** Examples *)
(** Below are some examples of using the partial evaluator. To make
the [pe_com] relation actually usable for automatic partial
evaluation, we would need to define more automation tactics in
Coq. That is not hard to do, but it is not needed here. *)
Example pe_example1:
(X ::= ANum 3 ; Y ::= AMult (AId Z) (APlus (AId X) (AId X)))
/ [] || (SKIP; Y ::= AMult (AId Z) (ANum 6)) / [(X,3)].
Proof. eapply PE_Seq. eapply PE_AssStatic. reflexivity.
eapply PE_AssDynamic. reflexivity. intros n H. inversion H. Qed.
Example pe_example2:
(X ::= ANum 3 ; IFB BLe (AId X) (ANum 4) THEN X ::= ANum 4 ELSE SKIP FI)
/ [] || (SKIP; SKIP) / [(X,4)].
Proof. eapply PE_Seq. eapply PE_AssStatic. reflexivity.
eapply PE_IfTrue. reflexivity.
eapply PE_AssStatic. reflexivity. Qed.
Example pe_example3:
(X ::= ANum 3;
IFB BLe (AId Y) (ANum 4) THEN
Y ::= ANum 4;
IFB BEq (AId X) (AId Y) THEN Y ::= ANum 999 ELSE SKIP FI
ELSE SKIP FI) / []
|| (SKIP;
IFB BLe (AId Y) (ANum 4) THEN
(SKIP; SKIP); (SKIP; Y ::= ANum 4)
ELSE SKIP; SKIP FI)
/ [(X,3)].
Proof. erewrite f_equal2 with (f := fun c st => _ / _ || c / st).
eapply PE_Seq. eapply PE_AssStatic. reflexivity.
eapply PE_If; intuition eauto; try solve by inversion.
econstructor. eapply PE_AssStatic. reflexivity.
eapply PE_IfFalse. reflexivity. econstructor.
reflexivity. reflexivity. Qed.
(** ** Correctness of Partial Evaluation *)
(** Finally let's prove that this partial evaluator is correct! *)
Reserved Notation "c' '/' pe_st' '/' st '||' st''"
(at level 40, pe_st' at level 39, st at level 39).
Inductive pe_ceval
(c':com) (pe_st':pe_state) (st:state) (st'':state) : Prop :=
| pe_ceval_intro : forall st',
c' / st || st' ->
pe_override st' pe_st' = st'' ->
c' / pe_st' / st || st''
where "c' '/' pe_st' '/' st '||' st''" := (pe_ceval c' pe_st' st st'').
Hint Constructors pe_ceval.
Theorem pe_com_complete:
forall c pe_st pe_st' c', c / pe_st || c' / pe_st' ->
forall st st'',
(c / pe_override st pe_st || st'') ->
(c' / pe_st' / st || st'').
Proof. intros c pe_st pe_st' c' Hpe.
pe_com_cases (induction Hpe) Case; intros st st'' Heval;
try (inversion Heval; subst;
try (rewrite -> pe_bexp_correct, -> H in *; solve by inversion);
[]);
eauto.
Case "PE_AssStatic". econstructor. econstructor.
rewrite -> pe_aexp_correct. rewrite <- pe_override_update_add.
rewrite -> H. reflexivity.
Case "PE_AssDynamic". econstructor. econstructor. reflexivity.
rewrite -> pe_aexp_correct. rewrite <- pe_override_update_remove.
reflexivity.
Case "PE_Seq".
edestruct IHHpe1. eassumption. subst.
edestruct IHHpe2. eassumption.
eauto.
Case "PE_If". inversion Heval; subst.
SCase "E'IfTrue". edestruct IHHpe1. eassumption.
econstructor. apply E_IfTrue. rewrite <- pe_bexp_correct. assumption.
eapply E_Seq. eassumption. apply eval_assign.
rewrite <- assign_removes. eassumption.
SCase "E_IfFalse". edestruct IHHpe2. eassumption.
econstructor. apply E_IfFalse. rewrite <- pe_bexp_correct. assumption.
eapply E_Seq. eassumption. apply eval_assign.
rewrite -> pe_compare_override.
rewrite <- assign_removes. eassumption.
Qed.
Theorem pe_com_sound:
forall c pe_st pe_st' c', c / pe_st || c' / pe_st' ->
forall st st'',
(c' / pe_st' / st || st'') ->
(c / pe_override st pe_st || st'').
Proof. intros c pe_st pe_st' c' Hpe.
pe_com_cases (induction Hpe) Case;
intros st st'' [st' Heval Heq];
try (inversion Heval; []; subst); auto.
Case "PE_AssStatic". rewrite <- pe_override_update_add. apply E_Ass.
rewrite -> pe_aexp_correct. rewrite -> H. reflexivity.
Case "PE_AssDynamic". rewrite <- pe_override_update_remove. apply E_Ass.
rewrite <- pe_aexp_correct. reflexivity.
Case "PE_Seq". eapply E_Seq; eauto.
Case "PE_IfTrue". apply E_IfTrue.
rewrite -> pe_bexp_correct. rewrite -> H. reflexivity. eauto.
Case "PE_IfFalse". apply E_IfFalse.
rewrite -> pe_bexp_correct. rewrite -> H. reflexivity. eauto.
Case "PE_If".
inversion Heval; subst; inversion H7;
(eapply ceval_deterministic in H8; [| apply eval_assign]); subst.
SCase "E_IfTrue".
apply E_IfTrue. rewrite -> pe_bexp_correct. assumption.
rewrite <- assign_removes. eauto.
SCase "E_IfFalse".
rewrite -> pe_compare_override.
apply E_IfFalse. rewrite -> pe_bexp_correct. assumption.
rewrite <- assign_removes. eauto.
Qed.
(** The main theorem. Thanks to David Menendez for this formulation! *)
Corollary pe_com_correct:
forall c pe_st pe_st' c', c / pe_st || c' / pe_st' ->
forall st st'',
(c / pe_override st pe_st || st'') <->
(c' / pe_st' / st || st'').
Proof. intros c pe_st pe_st' c' H st st''. split.
Case "->". apply pe_com_complete. apply H.
Case "<-". apply pe_com_sound. apply H.
Qed.
(* ####################################################### *)
(** * Partial Evaluation of Loops *)
(** It may seem straightforward at first glance to extend the partial
evaluation relation [pe_com] above to loops. Indeed, many loops
are easy to deal with. Considered this repeated-squaring loop,
for example:
[[
WHILE BLe (ANum 1) (AId X) DO
Y ::= AMult (AId Y) (AId Y);
X ::= AMinus (AId X) (ANum 1)
END
]]
If we know neither [X] nor [Y] statically, then the entire loop is
dynamic and the residual command should be the same. If we know
[X] but not [Y], then the loop can be unrolled all the way and the
residual command should be
[[
Y ::= AMult (AId Y) (AId Y);
Y ::= AMult (AId Y) (AId Y);
Y ::= AMult (AId Y) (AId Y)
]]
if [X] is initially [3] (and finally [0]). In general, a loop is
easy to partially evaluate if the final partial state of the loop
body is equal to the initial state, or if its guard condition is
static.
But there are other loops for which it is hard to express the
residual program we want in Imp. For example, take this program
for checking if [Y] is even or odd:
[[
X ::= ANum 0;
WHILE BLe (ANum 1) (AId Y) DO
Y ::= AMinus (AId Y) (ANum 1);
X ::= AMinus (ANum 1) (AId X)
END
]]
The value of [X] alternates between [0] and [1] during the loop.
Ideally, we would like to unroll this loop, not all the way but
_two-fold_, into something like
[[
WHILE BLe (ANum 1) (AId Y) DO
Y ::= AMinus (AId Y) (ANum 1);
IF BLe (ANum 1) (AId Y) THEN
Y ::= AMinus (AId Y) (ANum 1)
ELSE
X ::= ANum 1; EXIT
FI
END;
X ::= ANum 0
]]
Unfortunately, there is no [EXIT] command in Imp. Without
extending the range of control structures available in our
language, the best we can do is to repeat loop-guard tests or add
flag variables. Neither option is terribly attractive.
Still, as a digression, below is an attempt at performing partial
evaluation on Imp commands. We add one more command argument
[c''] to the [pe_com] relation, which keeps track of a loop to
roll up. *)
Module Loop.
Reserved Notation "c1 '/' st '||' c1' '/' st' '/' c''"
(at level 40, st at level 39, c1' at level 39, st' at level 39).
Inductive pe_com : com -> pe_state -> com -> pe_state -> com -> Prop :=
| PE_Skip : forall pe_st,
SKIP / pe_st || SKIP / pe_st / SKIP
| PE_AssStatic : forall pe_st a1 n1 l,
pe_aexp pe_st a1 = ANum n1 ->
(l ::= a1) / pe_st || SKIP / pe_add pe_st l n1 / SKIP
| PE_AssDynamic : forall pe_st a1 a1' l,
pe_aexp pe_st a1 = a1' ->
(forall n, a1' <> ANum n) ->
(l ::= a1) / pe_st || (l ::= a1') / pe_remove pe_st l / SKIP
| PE_Seq : forall pe_st pe_st' pe_st'' c1 c2 c1' c2' c'',
c1 / pe_st || c1' / pe_st' / SKIP ->
c2 / pe_st' || c2' / pe_st'' / c'' ->
(c1 ; c2) / pe_st || (c1' ; c2') / pe_st'' / c''
| PE_IfTrue : forall pe_st pe_st' b1 c1 c2 c1' c'',
pe_bexp pe_st b1 = BTrue ->
c1 / pe_st || c1' / pe_st' / c'' ->
(IFB b1 THEN c1 ELSE c2 FI) / pe_st || c1' / pe_st' / c''
| PE_IfFalse : forall pe_st pe_st' b1 c1 c2 c2' c'',
pe_bexp pe_st b1 = BFalse ->
c2 / pe_st || c2' / pe_st' / c'' ->
(IFB b1 THEN c1 ELSE c2 FI) / pe_st || c2' / pe_st' / c''
| PE_If : forall pe_st pe_st1 pe_st2 b1 c1 c2 c1' c2' c'',
pe_bexp pe_st b1 <> BTrue ->
pe_bexp pe_st b1 <> BFalse ->
c1 / pe_st || c1' / pe_st1 / c'' ->
c2 / pe_st || c2' / pe_st2 / c'' ->
(IFB b1 THEN c1 ELSE c2 FI) / pe_st
|| (IFB pe_bexp pe_st b1
THEN c1' ; assign pe_st1 (pe_compare pe_st1 pe_st2)
ELSE c2' ; assign pe_st2 (pe_compare pe_st1 pe_st2) FI)
/ pe_removes pe_st1 (pe_compare pe_st1 pe_st2)
/ c''
| PE_WhileEnd : forall pe_st b1 c1,
pe_bexp pe_st b1 = BFalse ->
(WHILE b1 DO c1 END) / pe_st || SKIP / pe_st / SKIP
| PE_WhileLoop : forall pe_st pe_st' pe_st'' b1 c1 c1' c2' c2'',
pe_bexp pe_st b1 = BTrue ->
c1 / pe_st || c1' / pe_st' / SKIP ->
(WHILE b1 DO c1 END) / pe_st' || c2' / pe_st'' / c2'' ->
pe_compare pe_st pe_st'' <> [] ->
(WHILE b1 DO c1 END) / pe_st || (c1';c2') / pe_st'' / c2''
| PE_While : forall pe_st pe_st' pe_st'' b1 c1 c1' c2' c2'',
pe_bexp pe_st b1 <> BFalse ->
pe_bexp pe_st b1 <> BTrue ->
c1 / pe_st || c1' / pe_st' / SKIP ->
(WHILE b1 DO c1 END) / pe_st' || c2' / pe_st'' / c2'' ->
pe_compare pe_st pe_st'' <> [] ->
(c2'' = SKIP \/ c2'' = WHILE b1 DO c1 END) ->
(WHILE b1 DO c1 END) / pe_st
|| (IFB pe_bexp pe_st b1
THEN c1'; c2'; assign pe_st'' (pe_compare pe_st pe_st'')
ELSE assign pe_st (pe_compare pe_st pe_st'') FI)
/ pe_removes pe_st (pe_compare pe_st pe_st'')
/ c2''
| PE_WhileFixedEnd : forall pe_st b1 c1,
pe_bexp pe_st b1 <> BFalse ->
(WHILE b1 DO c1 END) / pe_st || SKIP / pe_st / (WHILE b1 DO c1 END)
| PE_WhileFixedLoop : forall pe_st pe_st' pe_st'' b1 c1 c1' c2',
pe_bexp pe_st b1 = BTrue ->
c1 / pe_st || c1' / pe_st' / SKIP ->
(WHILE b1 DO c1 END) / pe_st'
|| c2' / pe_st'' / (WHILE b1 DO c1 END) ->
pe_compare pe_st pe_st'' = [] ->
(WHILE b1 DO c1 END) / pe_st
|| (WHILE BTrue DO SKIP END) / pe_st / SKIP
(* Because we have an infinite loop, we should actually
start to throw away the rest of the program:
(WHILE b1 DO c1 END) / pe_st
|| SKIP / pe_st / (WHILE BTrue DO SKIP END) *)
| PE_WhileFixed : forall pe_st pe_st' pe_st'' b1 c1 c1' c2',
pe_bexp pe_st b1 <> BFalse ->
pe_bexp pe_st b1 <> BTrue ->
c1 / pe_st || c1' / pe_st' / SKIP ->
(WHILE b1 DO c1 END) / pe_st'
|| c2' / pe_st'' / (WHILE b1 DO c1 END) ->
pe_compare pe_st pe_st'' = [] ->
(WHILE b1 DO c1 END) / pe_st
|| (WHILE pe_bexp pe_st b1 DO c1'; c2' END) / pe_st / SKIP
where "c1 '/' st '||' c1' '/' st' '/' c''" := (pe_com c1 st c1' st' c'').
Tactic Notation "pe_com_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "PE_Skip"
| Case_aux c "PE_AssStatic" | Case_aux c "PE_AssDynamic"
| Case_aux c "PE_Seq"
| Case_aux c "PE_IfTrue" | Case_aux c "PE_IfFalse" | Case_aux c "PE_If"
| Case_aux c "PE_WhileEnd" | Case_aux c "PE_WhileLoop"
| Case_aux c "PE_While" | Case_aux c "PE_WhileFixedEnd"
| Case_aux c "PE_WhileFixedLoop" | Case_aux c "PE_WhileFixed" ].
Hint Constructors pe_com.
(** ** Examples *)
Tactic Notation "step" constr(i) :=
(eapply i; intuition eauto; try solve by inversion);
repeat (try eapply PE_Seq;
try (eapply PE_AssStatic; simpl; reflexivity);
try (eapply PE_AssDynamic;
[ simpl; reflexivity
| intuition eauto; solve by inversion ])).
Definition square_loop: com :=
WHILE BLe (ANum 1) (AId X) DO
Y ::= AMult (AId Y) (AId Y);
X ::= AMinus (AId X) (ANum 1)
END.
Example pe_loop_example1:
square_loop / []
|| (WHILE BLe (ANum 1) (AId X) DO
(Y ::= AMult (AId Y) (AId Y);
X ::= AMinus (AId X) (ANum 1)); SKIP
END) / [] / SKIP.
Proof. erewrite f_equal2 with (f := fun c st => _ / _ || c / st / SKIP).
step PE_WhileFixed. step PE_WhileFixedEnd. reflexivity.
reflexivity. reflexivity. Qed.
Example pe_loop_example2:
(X ::= ANum 3; square_loop) / []
|| (SKIP;
(Y ::= AMult (AId Y) (AId Y); SKIP);
(Y ::= AMult (AId Y) (AId Y); SKIP);
(Y ::= AMult (AId Y) (AId Y); SKIP);
SKIP) / [(X,0)] / SKIP.
Proof. erewrite f_equal2 with (f := fun c st => _ / _ || c / st / SKIP).
eapply PE_Seq. eapply PE_AssStatic. reflexivity.
step PE_WhileLoop.
step PE_WhileLoop.
step PE_WhileLoop.
step PE_WhileEnd.
inversion H. inversion H. inversion H.
reflexivity. reflexivity. Qed.
Example pe_loop_example3:
(Z ::= ANum 3; subtract_slowly) / []
|| (SKIP;
IFB BNot (BEq (AId X) (ANum 0)) THEN
(SKIP; X ::= AMinus (AId X) (ANum 1));
IFB BNot (BEq (AId X) (ANum 0)) THEN
(SKIP; X ::= AMinus (AId X) (ANum 1));
IFB BNot (BEq (AId X) (ANum 0)) THEN
(SKIP; X ::= AMinus (AId X) (ANum 1));
WHILE BNot (BEq (AId X) (ANum 0)) DO
(SKIP; X ::= AMinus (AId X) (ANum 1)); SKIP
END;
SKIP; Z ::= ANum 0
ELSE SKIP; Z ::= ANum 1 FI; SKIP
ELSE SKIP; Z ::= ANum 2 FI; SKIP
ELSE SKIP; Z ::= ANum 3 FI) / [] / SKIP.
Proof. erewrite f_equal2 with (f := fun c st => _ / _ || c / st / SKIP).
eapply PE_Seq. eapply PE_AssStatic. reflexivity.
step PE_While.
step PE_While.
step PE_While.
step PE_WhileFixed.
step PE_WhileFixedEnd.
reflexivity. inversion H. inversion H. inversion H.
reflexivity. reflexivity. Qed.
Example pe_loop_example4:
(X ::= ANum 0;
WHILE BLe (AId X) (ANum 2) DO
X ::= AMinus (ANum 1) (AId X)
END) / [] || (SKIP; WHILE BTrue DO SKIP END) / [(X,0)] / SKIP.
Proof. erewrite f_equal2 with (f := fun c st => _ / _ || c / st / SKIP).
eapply PE_Seq. eapply PE_AssStatic. reflexivity.
step PE_WhileFixedLoop.
step PE_WhileLoop.
step PE_WhileFixedEnd.
inversion H. reflexivity. reflexivity. reflexivity. Qed.
(** ** Correctness *)
(** Because this partial evaluator can unroll a loop n-fold where n is
a (finite) integer greater than one, in order to show it correct
we need to perform induction not structurally on dynamic
evaluation but on the number of times dynamic evaluation enters a
loop body. *)
Reserved Notation "c1 '/' st '||' st' '#' n"
(at level 40, st at level 39, st' at level 39).
Inductive ceval_count : com -> state -> state -> nat -> Prop :=
| E'Skip : forall st,
SKIP / st || st # 0
| E'Ass : forall st a1 n l,
aeval st a1 = n ->
(l ::= a1) / st || (update st l n) # 0
| E'Seq : forall c1 c2 st st' st'' n1 n2,
c1 / st || st' # n1 ->
c2 / st' || st'' # n2 ->
(c1 ; c2) / st || st'' # (n1 + n2)
| E'IfTrue : forall st st' b1 c1 c2 n,
beval st b1 = true ->
c1 / st || st' # n ->
(IFB b1 THEN c1 ELSE c2 FI) / st || st' # n
| E'IfFalse : forall st st' b1 c1 c2 n,
beval st b1 = false ->
c2 / st || st' # n ->
(IFB b1 THEN c1 ELSE c2 FI) / st || st' # n
| E'WhileEnd : forall b1 st c1,
beval st b1 = false ->
(WHILE b1 DO c1 END) / st || st # 0
| E'WhileLoop : forall st st' st'' b1 c1 n1 n2,
beval st b1 = true ->
c1 / st || st' # n1 ->
(WHILE b1 DO c1 END) / st' || st'' # n2 ->
(WHILE b1 DO c1 END) / st || st'' # S (n1 + n2)
where "c1 '/' st '||' st' # n" := (ceval_count c1 st st' n).
Tactic Notation "ceval_count_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "E'Skip" | Case_aux c "E'Ass" | Case_aux c "E'Seq"
| Case_aux c "E'IfTrue" | Case_aux c "E'IfFalse"
| Case_aux c "E'WhileEnd" | Case_aux c "E'WhileLoop" ].
Hint Constructors ceval_count.
Theorem ceval_count_complete: forall c st st',
c / st || st' -> exists n, c / st || st' # n.
Proof. intros c st st' Heval.
induction Heval;
try inversion IHHeval1;
try inversion IHHeval2;
try inversion IHHeval;
eauto. Qed.
Theorem ceval_count_sound: forall c st st' n,
c / st || st' # n -> c / st || st'.
Proof. intros c st st' n Heval. induction Heval; eauto. Qed.
Theorem pe_compare_nil_lookup: forall pe_st1 pe_st2,
pe_compare pe_st1 pe_st2 = [] ->
forall V, pe_lookup pe_st1 V = pe_lookup pe_st2 V.
Proof. intros pe_st1 pe_st2 H V.
apply (pe_compare_correct pe_st1 pe_st2 V).
rewrite H. reflexivity. Qed.
Theorem pe_compare_nil_override: forall pe_st1 pe_st2,
pe_compare pe_st1 pe_st2 = [] ->
forall st, pe_override st pe_st1 = pe_override st pe_st2.
Proof. intros pe_st1 pe_st2 H st.
apply functional_extensionality. intros V.
rewrite !pe_override_correct.
apply pe_compare_nil_lookup with (V:=V) in H.
rewrite H. reflexivity. Qed.
Reserved Notation "c' '/' pe_st' '/' c'' '/' st '||' st'' '#' n"
(at level 40, pe_st' at level 39, c'' at level 39,
st at level 39, st'' at level 39).
Inductive pe_ceval_count (c':com) (pe_st':pe_state) (c'':com)
(st:state) (st'':state) (n:nat) : Prop :=
| pe_ceval_count_intro : forall st' n',
c' / st || st' ->
c'' / pe_override st' pe_st' || st'' # n' ->
n' <= n ->
c' / pe_st' / c'' / st || st'' # n
where "c' '/' pe_st' '/' c'' '/' st '||' st'' '#' n" :=
(pe_ceval_count c' pe_st' c'' st st'' n).
Hint Constructors pe_ceval_count.
Lemma pe_ceval_count_le: forall c' pe_st' c'' st st'' n n',
n' <= n ->
c' / pe_st' / c'' / st || st'' # n' ->
c' / pe_st' / c'' / st || st'' # n.
Proof. intros c' pe_st' c'' st st'' n n' Hle H. inversion H.
econstructor; try eassumption. omega. Qed.
Theorem pe_com_complete:
forall c pe_st pe_st' c' c'', c / pe_st || c' / pe_st' / c'' ->
forall st st'' n,
(c / pe_override st pe_st || st'' # n) ->
(c' / pe_st' / c'' / st || st'' # n).
Proof. intros c pe_st pe_st' c' c'' Hpe.
pe_com_cases (induction Hpe) Case; intros st st'' n Heval;
try (inversion Heval; subst;
try (rewrite -> pe_bexp_correct, -> H in *; solve by inversion);
[]);
eauto.
Case "PE_AssStatic". econstructor. econstructor.
rewrite -> pe_aexp_correct. rewrite <- pe_override_update_add.
rewrite -> H. apply E'Skip. auto.
Case "PE_AssDynamic". econstructor. econstructor. reflexivity.
rewrite -> pe_aexp_correct. rewrite <- pe_override_update_remove.
apply E'Skip. auto.
Case "PE_Seq".
edestruct IHHpe1 as [? ? ? Hskip ?]. eassumption.
inversion Hskip. subst.
edestruct IHHpe2. eassumption.
econstructor; eauto. omega.
Case "PE_If". inversion Heval; subst.
SCase "E'IfTrue". edestruct IHHpe1. eassumption.
econstructor. apply E_IfTrue. rewrite <- pe_bexp_correct. assumption.
eapply E_Seq. eassumption. apply eval_assign.
rewrite <- assign_removes. eassumption. eassumption.
SCase "E_IfFalse". edestruct IHHpe2. eassumption.
econstructor. apply E_IfFalse. rewrite <- pe_bexp_correct. assumption.
eapply E_Seq. eassumption. apply eval_assign.
rewrite -> pe_compare_override.
rewrite <- assign_removes. eassumption. eassumption.
Case "PE_WhileLoop".
edestruct IHHpe1 as [? ? ? Hskip ?]. eassumption.
inversion Hskip. subst.
edestruct IHHpe2. eassumption.
econstructor; eauto. omega.
Case "PE_While". inversion Heval; subst.
SCase "E_WhileEnd". econstructor. apply E_IfFalse.
rewrite <- pe_bexp_correct. assumption.
apply eval_assign.
rewrite <- assign_removes. inversion H2; subst; auto.
auto.
SCase "E_WhileLoop".
edestruct IHHpe1 as [? ? ? Hskip ?]. eassumption.
inversion Hskip. subst.
edestruct IHHpe2. eassumption.
econstructor. apply E_IfTrue.
rewrite <- pe_bexp_correct. assumption.
repeat eapply E_Seq; eauto. apply eval_assign.
rewrite -> pe_compare_override, <- assign_removes. eassumption.
omega.
Case "PE_WhileFixedLoop". apply ex_falso_quodlibet.
generalize dependent (S (n1 + n2)). intros n.
clear - Case H H0 IHHpe1 IHHpe2. generalize dependent st.
induction n using lt_wf_ind; intros st Heval. inversion Heval; subst.
SCase "E'WhileEnd". rewrite pe_bexp_correct, H in H7. inversion H7.
SCase "E'WhileLoop".
edestruct IHHpe1 as [? ? ? Hskip ?]. eassumption.
inversion Hskip. subst.
edestruct IHHpe2. eassumption.
rewrite <- (pe_compare_nil_override _ _ H0) in H7.
apply H1 in H7; [| omega]. inversion H7.
Case "PE_WhileFixed". generalize dependent st.
induction n using lt_wf_ind; intros st Heval. inversion Heval; subst.
SCase "E'WhileEnd". rewrite pe_bexp_correct in H8. eauto.
SCase "E'WhileLoop". rewrite pe_bexp_correct in H5.
edestruct IHHpe1 as [? ? ? Hskip ?]. eassumption.
inversion Hskip. subst.
edestruct IHHpe2. eassumption.
rewrite <- (pe_compare_nil_override _ _ H1) in H8.
apply H2 in H8; [| omega]. inversion H8.
econstructor; [ eapply E_WhileLoop; eauto | eassumption | omega].
Qed.
Theorem pe_com_sound:
forall c pe_st pe_st' c' c'', c / pe_st || c' / pe_st' / c'' ->
forall st st'' n,
(c' / pe_st' / c'' / st || st'' # n) ->
(c / pe_override st pe_st || st'').
Proof. intros c pe_st pe_st' c' c'' Hpe.
pe_com_cases (induction Hpe) Case;
intros st st'' n [st' n' Heval Heval' Hle];
try (inversion Heval; []; subst);
try (inversion Heval'; []; subst); eauto.
Case "PE_AssStatic". rewrite <- pe_override_update_add. apply E_Ass.
rewrite -> pe_aexp_correct. rewrite -> H. reflexivity.
Case "PE_AssDynamic". rewrite <- pe_override_update_remove. apply E_Ass.
rewrite <- pe_aexp_correct. reflexivity.
Case "PE_Seq". eapply E_Seq; eauto.
Case "PE_IfTrue". apply E_IfTrue.
rewrite -> pe_bexp_correct. rewrite -> H. reflexivity.
eapply IHHpe. eauto.
Case "PE_IfFalse". apply E_IfFalse.
rewrite -> pe_bexp_correct. rewrite -> H. reflexivity.
eapply IHHpe. eauto.
Case "PE_If". inversion Heval; subst; inversion H7; subst; clear H7.
SCase "E_IfTrue".
eapply ceval_deterministic in H8; [| apply eval_assign]. subst.
rewrite <- assign_removes in Heval'.
apply E_IfTrue. rewrite -> pe_bexp_correct. assumption.
eapply IHHpe1. eauto.
SCase "E_IfFalse".
eapply ceval_deterministic in H8; [| apply eval_assign]. subst.
rewrite -> pe_compare_override in Heval'.
rewrite <- assign_removes in Heval'.
apply E_IfFalse. rewrite -> pe_bexp_correct. assumption.
eapply IHHpe2. eauto.
Case "PE_WhileEnd". apply E_WhileEnd.
rewrite -> pe_bexp_correct. rewrite -> H. reflexivity.
Case "PE_WhileLoop". eapply E_WhileLoop.
rewrite -> pe_bexp_correct. rewrite -> H. reflexivity.
eapply IHHpe1. eauto. eapply IHHpe2. eauto.
Case "PE_While". inversion Heval; subst.
SCase "E_IfTrue".
inversion H9. subst. clear H9.
inversion H10. subst. clear H10.
eapply ceval_deterministic in H11; [| apply eval_assign]. subst.
rewrite -> pe_compare_override in Heval'.
rewrite <- assign_removes in Heval'.
eapply E_WhileLoop. rewrite -> pe_bexp_correct. assumption.
eapply IHHpe1. eauto.
eapply IHHpe2. eauto.
SCase "E_IfFalse". apply ceval_count_sound in Heval'.
eapply ceval_deterministic in H9; [| apply eval_assign]. subst.
rewrite <- assign_removes in Heval'.
inversion H2; subst.
SSCase "c2'' = SKIP". inversion Heval'. subst. apply E_WhileEnd.
rewrite -> pe_bexp_correct. assumption.
SSCase "c2'' = WHILE b1 DO c1 END". assumption.
Case "PE_WhileFixedEnd". eapply ceval_count_sound. apply Heval'.
Case "PE_WhileFixedLoop".
apply loop_never_stops in Heval. inversion Heval.
Case "PE_WhileFixed".
clear - Case H1 IHHpe1 IHHpe2 Heval.
remember (WHILE pe_bexp pe_st b1 DO c1'; c2' END) as c'.
ceval_cases (induction Heval) SCase;
inversion Heqc'; subst; clear Heqc'.
SCase "E_WhileEnd". apply E_WhileEnd.
rewrite pe_bexp_correct. assumption.
SCase "E_WhileLoop".
assert (IHHeval2' := IHHeval2 (refl_equal _)).
apply ceval_count_complete in IHHeval2'. inversion IHHeval2'.
clear IHHeval1 IHHeval2 IHHeval2'.
inversion Heval1. subst.
eapply E_WhileLoop. rewrite pe_bexp_correct. assumption. eauto.
eapply IHHpe2. econstructor. eassumption.
rewrite <- (pe_compare_nil_override _ _ H1). eassumption. apply le_n.
Qed.
Corollary pe_com_correct:
forall c pe_st pe_st' c', c / pe_st || c' / pe_st' / SKIP ->
forall st st'',
(c / pe_override st pe_st || st'') <->
(exists st', c' / st || st' /\ pe_override st' pe_st' = st'').
Proof. intros c pe_st pe_st' c' H st st''. split.
Case "->". intros Heval.
apply ceval_count_complete in Heval. inversion Heval as [n Heval'].
apply pe_com_complete with (st:=st) (st'':=st'') (n:=n) in H.
inversion H as [? ? ? Hskip ?]. inversion Hskip. subst. eauto.
assumption.
Case "<-". intros [st' [Heval Heq]]. subst st''.
eapply pe_com_sound in H. apply H.
econstructor. apply Heval. apply E'Skip. apply le_n.
Qed.
End Loop.
(* ####################################################### *)
(** * Partial Evaluation of Flowchart Programs *)
(** Instead of partially evaluating [WHILE] loops directly, the
standard approach to partially evaluating imperative programs is
to convert them into _flowcharts_. In other words, it turns out
that adding labels and jumps to our language makes it much easier
to partially evaluate. The result of partially evaluating a
flowchart is a residual flowchart. If we are lucky, the jumps in
the residual flowchart can be converted back to [WHILE] loops, but
that is not possible in general; we do not pursue it here. *)
(** ** Basic blocks *)
(** A flowchart is made of _basic blocks_, which we represent with the
inductive type [block]. A basic block is a sequence of
assignments (the constructor [Assign]), concluding with a
conditional jump (the constructor [If]) or an unconditional jump
(the constructor [Goto]). The destinations of the jumps are
specified by _labels_, which can be of any type. Therefore, we
parameterize the [block] type by the type of labels. *)
Inductive block (Label:Type) : Type :=
| Goto : Label -> block Label
| If : bexp -> Label -> Label -> block Label
| Assign : id -> aexp -> block Label -> block Label.
Tactic Notation "block_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "Goto" | Case_aux c "If" | Case_aux c "Assign" ].
Implicit Arguments Goto [[Label]].
Implicit Arguments If [[Label]].
Implicit Arguments Assign [[Label]].
(** We use the "even or odd" program, expressed above in Imp, as our
running example. Converting this program into a flowchart turns
out to require 4 labels, so we define the following type. *)
Inductive parity_label : Type :=
| entry : parity_label
| loop : parity_label
| body : parity_label
| done : parity_label.
(** The following [block] is the basic block found at the [body] label
of the example program. *)
Definition parity_body : block parity_label :=
Assign Y (AMinus (AId Y) (ANum 1))
(Assign X (AMinus (ANum 1) (AId X))
(Goto loop)).
(** To evaluate a basic block, given an initial state, is to compute
the final state and the label to jump to next. Because basic
blocks do not _contain_ loops or other control structures,
evaluation of basic blocks is a total function -- we don't need to
worry about non-termination. *)
Fixpoint keval {L:Type} (st:state) (k : block L) : state * L :=
match k with
| Goto l => (st, l)
| If b l1 l2 => (st, if beval st b then l1 else l2)
| Assign i a k => keval (update st i (aeval st a)) k
end.
Example keval_example:
keval empty_state parity_body
= (update (update empty_state Y 0) X 1, loop).
Proof. reflexivity. Qed.
(** ** Flowchart programs *)
(** A flowchart program is simply a lookup function that maps labels
to basic blocks. Actually, some labels are _halting states_ and
do not map to any basic block. So, more precisely, a flowchart
[program] whose labels are of type [L] is a function from [L] to
[option (block L)]. *)
Definition program (L:Type) : Type := L -> option (block L).
Definition parity : program parity_label := fun l =>
match l with
| entry => Some (Assign X (ANum 0) (Goto loop))
| loop => Some (If (BLe (ANum 1) (AId Y)) body done)
| body => Some parity_body
| done => None (* halt *)
end.
(** Unlike a basic block, a program may not terminate, so we model the
evaluation of programs by an inductive relation [peval] rather
than a recursive function. *)
Inductive peval {L:Type} (p : program L)
: state -> L -> state -> L -> Prop :=
| E_None: forall st l,
p l = None ->
peval p st l st l
| E_Some: forall st l k st' l' st'' l'',
p l = Some k ->
keval st k = (st', l') ->
peval p st' l' st'' l'' ->
peval p st l st'' l''.
Example parity_eval: peval parity empty_state entry empty_state done.
Proof. erewrite f_equal with (f := fun st => peval _ _ _ st _).
eapply E_Some. reflexivity. reflexivity.
eapply E_Some. reflexivity. reflexivity.
apply E_None. reflexivity.
apply functional_extensionality. intros i. rewrite update_same; auto.
Qed.
Tactic Notation "peval_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "E_None" | Case_aux c "E_Some" ].
(** ** Partial evaluation of basic blocks and flowchart programs *)
(** Partial evaluation changes the label type in a systematic way: if
the label type used to be [L], it becomes [pe_state * L]. So the
same label in the original program may be unfolded, or blown up,
into multiple labels by being paired with different partial
states. For example, the label [loop] in the [parity] program
will become two labels: [([(X,0)], loop)] and [([(X,1)], loop)].
This change of label type is reflected in the types of [pe_block]
and [pe_program] defined presently. *)
Fixpoint pe_block {L:Type} (pe_st:pe_state) (k : block L)
: block (pe_state * L) :=
match k with
| Goto l => Goto (pe_st, l)
| If b l1 l2 =>
match pe_bexp pe_st b with
| BTrue => Goto (pe_st, l1)
| BFalse => Goto (pe_st, l2)
| b' => If b' (pe_st, l1) (pe_st, l2)
end
| Assign i a k =>
match pe_aexp pe_st a with
| ANum n => pe_block (pe_add pe_st i n) k
| a' => Assign i a' (pe_block (pe_remove pe_st i) k)
end
end.
Example pe_block_example:
pe_block [(X,0)] parity_body
= Assign Y (AMinus (AId Y) (ANum 1)) (Goto ([(X,1)], loop)).
Proof. reflexivity. Qed.
Theorem pe_block_correct: forall (L:Type) st pe_st k st' pe_st' (l':L),
keval st (pe_block pe_st k) = (st', (pe_st', l')) ->
keval (pe_override st pe_st) k = (pe_override st' pe_st', l').
Proof. intros. generalize dependent pe_st. generalize dependent st.
block_cases (induction k as [l | b l1 l2 | i a k]) Case;
intros st pe_st H.
Case "Goto". inversion H; reflexivity.
Case "If".
replace (keval st (pe_block pe_st (If b l1 l2)))
with (keval st (If (pe_bexp pe_st b) (pe_st, l1) (pe_st, l2)))
in H by (simpl; destruct (pe_bexp pe_st b); reflexivity).
simpl in *. rewrite pe_bexp_correct.
destruct (beval st (pe_bexp pe_st b)); inversion H; reflexivity.
Case "Assign".
simpl in *. rewrite pe_aexp_correct.
destruct (pe_aexp pe_st a); simpl;
try solve [rewrite pe_override_update_add; apply IHk; apply H];
solve [rewrite pe_override_update_remove; apply IHk; apply H].
Qed.
Definition pe_program {L:Type} (p : program L)
: program (pe_state * L) :=
fun pe_l => match pe_l with (pe_st, l) =>
option_map (pe_block pe_st) (p l)
end.
Inductive pe_peval {L:Type} (p : program L)
(st:state) (pe_st:pe_state) (l:L) (st'o:state) (l':L) : Prop :=
| pe_peval_intro : forall st' pe_st',
peval (pe_program p) st (pe_st, l) st' (pe_st', l') ->
pe_override st' pe_st' = st'o ->
pe_peval p st pe_st l st'o l'.
Theorem pe_program_correct:
forall (L:Type) (p : program L) st pe_st l st'o l',
peval p (pe_override st pe_st) l st'o l' <->
pe_peval p st pe_st l st'o l'.
Proof. intros.
split; [Case "->" | Case "<-"].
Case "->". intros Heval.
remember (pe_override st pe_st) as sto.
generalize dependent pe_st. generalize dependent st.
peval_cases (induction Heval as
[ sto l Hlookup | sto l k st'o l' st''o l'' Hlookup Hkeval Heval ])
SCase; intros st pe_st Heqsto; subst sto.
SCase "E_None". eapply pe_peval_intro. apply E_None.
simpl. rewrite Hlookup. reflexivity. reflexivity.
SCase "E_Some".
remember (keval st (pe_block pe_st k)) as x.
destruct x as [st' [pe_st' l'_]].
symmetry in Heqx. erewrite pe_block_correct in Hkeval by apply Heqx.
inversion Hkeval. subst st'o l'_. clear Hkeval.
edestruct IHHeval. reflexivity. subst st''o. clear IHHeval.
eapply pe_peval_intro; [| reflexivity]. eapply E_Some; eauto.
simpl. rewrite Hlookup. reflexivity.
Case "<-". intros [st' pe_st' Heval Heqst'o].
remember (pe_st, l) as pe_st_l.
remember (pe_st', l') as pe_st'_l'.
generalize dependent pe_st. generalize dependent l.
peval_cases (induction Heval as
[ st [pe_st_ l_] Hlookup
| st [pe_st_ l_] pe_k st' [pe_st'_ l'_] st'' [pe_st'' l'']
Hlookup Hkeval Heval ])
SCase; intros l pe_st Heqpe_st_l;
inversion Heqpe_st_l; inversion Heqpe_st'_l'; repeat subst.
SCase "E_None". apply E_None. simpl in Hlookup.
destruct (p l'); [ solve [ inversion Hlookup ] | reflexivity ].
SCase "E_Some".
simpl in Hlookup. remember (p l) as k.
destruct k as [k|]; inversion Hlookup; subst.
eapply E_Some; eauto. apply pe_block_correct. apply Hkeval.
Qed.
|
/////////////////////////////////////////////////////////////////////////
// Copyright (c) 2008 Xilinx, Inc. All rights reserved.
//
// XILINX CONFIDENTIAL PROPERTY
// This document contains proprietary information which is
// protected by copyright. All rights are reserved. This notice
// refers to original work by Xilinx, Inc. which may be derivitive
// of other work distributed under license of the authors. In the
// case of derivitive work, nothing in this notice overrides the
// original author's license agreeement. Where applicable, the
// original license agreement is included in it's original
// unmodified form immediately below this header.
//
// Xilinx, Inc.
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
/////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's Data Cache top level ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// Instantiation of all IC blocks. ////
//// ////
//// To Do: ////
//// - make it smaller and faster ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_ic_top.v,v $
// Revision 1.1 2008/05/07 22:43:22 daughtry
// Initial Demo RTL check-in
//
// Revision 1.9 2004/04/05 08:29:57 lampret
// Merged branch_qmem into main tree.
//
// Revision 1.7.4.2 2003/12/09 11:46:48 simons
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
//
// Revision 1.7.4.1 2003/07/08 15:36:37 lampret
// Added embedded memory QMEM.
//
// Revision 1.7 2002/10/17 20:04:40 lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
// Revision 1.6 2002/03/29 15:16:55 lampret
// Some of the warnings fixed.
//
// Revision 1.5 2002/02/11 04:33:17 lampret
// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
//
// Revision 1.4 2002/02/01 19:56:54 lampret
// Fixed combinational loops.
//
// Revision 1.3 2002/01/28 01:16:00 lampret
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
//
// Revision 1.2 2002/01/14 06:18:22 lampret
// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.10 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from ic.v and ic.v. Fixed CR+LF.
//
// Revision 1.9 2001/10/14 13:12:09 lampret
// MP3 version.
//
// Revision 1.1.1.1 2001/10/06 10:18:35 igorm
// no message
//
// Revision 1.4 2001/08/13 03:36:20 lampret
// Added cfg regs. Moved all defines into one defines.v file. More cleanup.
//
// Revision 1.3 2001/08/09 13:39:33 lampret
// Major clean-up.
//
// Revision 1.2 2001/07/22 03:31:53 lampret
// Fixed RAM's oen bug. Cache bypass under development.
//
// Revision 1.1 2001/07/20 00:46:03 lampret
// Development version of RTL. Libraries are missing.
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
//
// Data cache
//
module or1200_ic_top(
// Rst, clk and clock control
clk, rst,
// External i/f
icbiu_dat_o, icbiu_adr_o, icbiu_cyc_o, icbiu_stb_o, icbiu_we_o, icbiu_sel_o, icbiu_cab_o,
icbiu_dat_i, icbiu_ack_i, icbiu_err_i,
// Internal i/f
ic_en,
icqmem_adr_i, icqmem_cycstb_i, icqmem_ci_i,
icqmem_sel_i, icqmem_tag_i,
icqmem_dat_o, icqmem_ack_o, icqmem_rty_o, icqmem_err_o, icqmem_tag_o,
`ifdef OR1200_BIST
// RAM BIST
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// SPRs
spr_cs, spr_write, spr_dat_i
);
parameter dw = `OR1200_OPERAND_WIDTH;
//
// I/O
//
//
// Clock and reset
//
input clk;
input rst;
//
// External I/F
//
output [dw-1:0] icbiu_dat_o;
output [31:0] icbiu_adr_o;
output icbiu_cyc_o;
output icbiu_stb_o;
output icbiu_we_o;
output [3:0] icbiu_sel_o;
output icbiu_cab_o;
input [dw-1:0] icbiu_dat_i;
input icbiu_ack_i;
input icbiu_err_i;
//
// Internal I/F
//
input ic_en;
input [31:0] icqmem_adr_i;
input icqmem_cycstb_i;
input icqmem_ci_i;
input [3:0] icqmem_sel_i;
input [3:0] icqmem_tag_i;
output [dw-1:0] icqmem_dat_o;
output icqmem_ack_o;
output icqmem_rty_o;
output icqmem_err_o;
output [3:0] icqmem_tag_o;
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
//
// SPR access
//
input spr_cs;
input spr_write;
input [31:0] spr_dat_i;
//
// Internal wires and regs
//
wire tag_v;
wire [`OR1200_ICTAG_W-2:0] tag;
wire [dw-1:0] to_icram;
wire [dw-1:0] from_icram;
wire [31:0] saved_addr;
wire [3:0] icram_we;
wire ictag_we;
wire [31:0] ic_addr;
wire icfsm_biu_read;
reg tagcomp_miss;
wire [`OR1200_ICINDXH:`OR1200_ICLS] ictag_addr;
wire ictag_en;
wire ictag_v;
wire ic_inv;
wire icfsm_first_hit_ack;
wire icfsm_first_miss_ack;
wire icfsm_first_miss_err;
wire icfsm_burst;
wire icfsm_tag_we;
`ifdef OR1200_BIST
//
// RAM BIST
//
wire mbist_ram_so;
wire mbist_tag_so;
wire mbist_ram_si = mbist_si_i;
wire mbist_tag_si = mbist_ram_so;
assign mbist_so_o = mbist_tag_so;
`endif
//
// Simple assignments
//
assign icbiu_adr_o = ic_addr;
assign ic_inv = spr_cs & spr_write;
assign ictag_we = icfsm_tag_we | ic_inv;
assign ictag_addr = ic_inv ? spr_dat_i[`OR1200_ICINDXH:`OR1200_ICLS] : ic_addr[`OR1200_ICINDXH:`OR1200_ICLS];
assign ictag_en = ic_inv | ic_en;
assign ictag_v = ~ic_inv;
//
// Data to BIU is from ICRAM when IC is enabled or from LSU when
// IC is disabled
//
///assign icbiu_dat_o = 32'h00000000;
assign icbiu_dat_o = icbiu_dat_i;
//
// Bypases of the IC when IC is disabled
//
assign icbiu_cyc_o = (ic_en) ? icfsm_biu_read : icqmem_cycstb_i;
assign icbiu_stb_o = (ic_en) ? icfsm_biu_read : icqmem_cycstb_i;
assign icbiu_we_o = 1'b0;
assign icbiu_sel_o = (ic_en & icfsm_biu_read) ? 4'b1111 : icqmem_sel_i;
assign icbiu_cab_o = (ic_en) ? icfsm_burst : 1'b0;
assign icqmem_rty_o = ~icqmem_ack_o & ~icqmem_err_o;
assign icqmem_tag_o = icqmem_err_o ? `OR1200_ITAG_BE : icqmem_tag_i;
//
// CPU normal and error termination
//
assign icqmem_ack_o = ic_en ? (icfsm_first_hit_ack | icfsm_first_miss_ack) : icbiu_ack_i;
assign icqmem_err_o = ic_en ? icfsm_first_miss_err : icbiu_err_i;
//
// Select between claddr generated by IC FSM and addr[3:2] generated by LSU
//
assign ic_addr = (icfsm_biu_read) ? saved_addr : icqmem_adr_i;
//
// Select between input data generated by LSU or by BIU
//
assign to_icram = icbiu_dat_i;
//
// Select between data generated by ICRAM or passed by BIU
//
assign icqmem_dat_o = icfsm_first_miss_ack | !ic_en ? icbiu_dat_i : from_icram;
//
// Tag comparison
//
always @(tag or saved_addr or tag_v) begin
if ((tag != saved_addr[31:`OR1200_ICTAGL]) || !tag_v)
tagcomp_miss = 1'b1;
else
tagcomp_miss = 1'b0;
end
//
// Instantiation of IC Finite State Machine
//
or1200_ic_fsm or1200_ic_fsm(
.clk(clk),
.rst(rst),
.ic_en(ic_en),
.icqmem_cycstb_i(icqmem_cycstb_i),
.icqmem_ci_i(icqmem_ci_i),
.tagcomp_miss(tagcomp_miss),
.biudata_valid(icbiu_ack_i),
.biudata_error(icbiu_err_i),
.start_addr(icqmem_adr_i),
.saved_addr(saved_addr),
.icram_we(icram_we),
.biu_read(icfsm_biu_read),
.first_hit_ack(icfsm_first_hit_ack),
.first_miss_ack(icfsm_first_miss_ack),
.first_miss_err(icfsm_first_miss_err),
.burst(icfsm_burst),
.tag_we(icfsm_tag_we)
);
//
// Instantiation of IC main memory
//
or1200_ic_ram or1200_ic_ram(
.clk(clk),
.rst(rst),
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_ram_si),
.mbist_so_o(mbist_ram_so),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.addr(ic_addr[`OR1200_ICINDXH:2]),
.en(ic_en),
.we(icram_we),
.datain(to_icram),
.dataout(from_icram)
);
//
// Instantiation of IC TAG memory
//
or1200_ic_tag or1200_ic_tag(
.clk(clk),
.rst(rst),
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_tag_si),
.mbist_so_o(mbist_tag_so),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.addr(ictag_addr),
.en(ictag_en),
.we(ictag_we),
.datain({ic_addr[31:`OR1200_ICTAGL], ictag_v}),
.tag_v(tag_v),
.tag(tag)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__CLKBUF_FUNCTIONAL_V
`define SKY130_FD_SC_HS__CLKBUF_FUNCTIONAL_V
/**
* clkbuf: Clock tree buffer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__clkbuf (
VPWR,
VGND,
X ,
A
);
// Module ports
input VPWR;
input VGND;
output X ;
input A ;
// Local signals
wire buf0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__CLKBUF_FUNCTIONAL_V
|
/////////////////////////////////////////////////////////////////////
//// ////
//// FIFO 4 entries deep ////
//// ////
//// Authors: Rudolf Usselmann, Richard Herveille ////
//// [email protected] [email protected] ////
//// ////
//// ////
//// Download from: http://www.opencores.org/projects/sasc ////
//// http://www.opencores.org/projects/simple_spi ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000-2002 Rudolf Usselmann, Richard Herveille ////
//// www.asics.ws ////
//// [email protected], [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: fifo4.v,v 1.1.1.1 2002-12-22 16:07:14 rherveille Exp $
//
// $Date: 2002-12-22 16:07:14 $
// $Revision: 1.1.1.1 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: not supported by cvs2svn $
//
// 4 entry deep fast fifo
module fifo4(clk, rst, clr, din, we, dout, re, full, empty);
parameter dw = 8; // data width
input clk, rst;
input clr;
input [dw:1] din;
input we; // write enable
output [dw:1] dout;
input re; // read enable
output full, empty;
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
reg [dw:1] mem[0:3];
reg [1:0] wp; // write pointer
reg [1:0] rp; // read pointer
wire [1:0] wp_p1; // write pointer + 1
wire [1:0] rp_p1; // read pointer + 1
wire full, empty;
reg gb;
////////////////////////////////////////////////////////////////////
//
// Misc Logic
//
always @(posedge clk or negedge rst)
if(!rst) wp <= #1 2'h0;
else
if(clr) wp <= #1 2'h0;
else
if(we) wp <= #1 wp_p1;
assign wp_p1 = wp + 2'h1;
always @(posedge clk or negedge rst)
if(!rst) rp <= #1 2'h0;
else
if(clr) rp <= #1 2'h0;
else
if(re) rp <= #1 rp_p1;
assign rp_p1 = rp + 2'h1;
// Fifo Output
assign dout = mem[ rp ];
// Fifo Input
always @(posedge clk)
if(we) mem[ wp ] <= #1 din;
// Status
assign empty = (wp == rp) & !gb;
assign full = (wp == rp) & gb;
// Guard Bit ...
always @(posedge clk)
if(!rst) gb <= #1 1'b0;
else
if(clr) gb <= #1 1'b0;
else
if((wp_p1 == rp) & we) gb <= #1 1'b1;
else
if(re) gb <= #1 1'b0;
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: cpx_buf_p1.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Description: datapath portion of CPX
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
`include "sys.h"
`include "iop.h"
module cpx_buf_p1(/*AUTOARG*/
// Outputs
scache0_cpx_req_bufp1_cq, scache0_cpx_atom_bufp1_cq,
cpx_scache0_grant_bufp1_ca_l, cpx_spc0_data_rdy_bufp1_cx,
cpx_spc1_data_rdy_bufp1_cx, cpx_spc2_data_rdy_bufp1_cx,
arbcp0_cpxdp_grant_bufp1_ca_l_0, arbcp0_cpxdp_q0_hold_bufp1_ca_0,
arbcp0_cpxdp_qsel0_bufp1_ca_l_0, arbcp0_cpxdp_qsel1_bufp1_ca_0,
arbcp0_cpxdp_shift_bufp1_cx_l_0, arbcp1_cpxdp_grant_bufp1_ca_l_0,
arbcp1_cpxdp_q0_hold_bufp1_ca_0, arbcp1_cpxdp_qsel0_bufp1_ca_l_0,
arbcp1_cpxdp_qsel1_bufp1_ca_0, arbcp1_cpxdp_shift_bufp1_cx_l_0,
arbcp2_cpxdp_grant_bufp1_ca_l_0, arbcp2_cpxdp_q0_hold_bufp1_ca_0,
arbcp2_cpxdp_qsel0_bufp1_ca_l_0, arbcp2_cpxdp_qsel1_bufp1_ca_0,
arbcp2_cpxdp_shift_bufp1_cx_l_0, arbcp3_cpxdp_grant_bufp1_ca_l_0,
arbcp3_cpxdp_q0_hold_bufp1_ca_0, arbcp3_cpxdp_qsel0_bufp1_ca_l_0,
arbcp3_cpxdp_qsel1_bufp1_ca_0, arbcp3_cpxdp_shift_bufp1_cx_l_0,
arbcp4_cpxdp_grant_bufp1_ca_l_0, arbcp4_cpxdp_q0_hold_bufp1_ca_0,
arbcp4_cpxdp_qsel0_bufp1_ca_l_0, arbcp4_cpxdp_qsel1_bufp1_ca_0,
arbcp4_cpxdp_shift_bufp1_cx_l_0, arbcp5_cpxdp_grant_bufp1_ca_l_0,
arbcp5_cpxdp_q0_hold_bufp1_ca_0, arbcp5_cpxdp_qsel0_bufp1_ca_l_0,
arbcp5_cpxdp_qsel1_bufp1_ca_0, arbcp5_cpxdp_shift_bufp1_cx_l_0,
arbcp6_cpxdp_grant_bufp1_ca_l_0, arbcp6_cpxdp_q0_hold_bufp1_ca_0,
arbcp6_cpxdp_qsel0_bufp1_ca_l_0, arbcp6_cpxdp_qsel1_bufp1_ca_0,
arbcp6_cpxdp_shift_bufp1_cx_l_0, arbcp7_cpxdp_grant_bufp1_ca_l_0,
arbcp7_cpxdp_q0_hold_bufp1_ca_0, arbcp7_cpxdp_qsel0_bufp1_ca_l_0,
arbcp7_cpxdp_qsel1_bufp1_ca_0, arbcp7_cpxdp_shift_bufp1_cx_l_0,
arbcp0_cpxdp_grant_bufp1_ca_l_1, arbcp0_cpxdp_q0_hold_bufp1_ca_1,
arbcp0_cpxdp_qsel0_bufp1_ca_l_1, arbcp0_cpxdp_qsel1_bufp1_ca_1,
arbcp0_cpxdp_shift_bufp1_cx_l_1, arbcp1_cpxdp_grant_bufp1_ca_l_1,
arbcp1_cpxdp_q0_hold_bufp1_ca_1, arbcp1_cpxdp_qsel0_bufp1_ca_l_1,
arbcp1_cpxdp_qsel1_bufp1_ca_1, arbcp1_cpxdp_shift_bufp1_cx_l_1,
arbcp2_cpxdp_grant_bufp1_ca_l_1, arbcp2_cpxdp_q0_hold_bufp1_ca_1,
arbcp2_cpxdp_qsel0_bufp1_ca_l_1, arbcp2_cpxdp_qsel1_bufp1_ca_1,
arbcp2_cpxdp_shift_bufp1_cx_l_1, arbcp3_cpxdp_grant_bufp1_ca_l_1,
arbcp3_cpxdp_q0_hold_bufp1_ca_1, arbcp3_cpxdp_qsel0_bufp1_ca_l_1,
arbcp3_cpxdp_qsel1_bufp1_ca_1, arbcp3_cpxdp_shift_bufp1_cx_l_1,
arbcp4_cpxdp_grant_bufp1_ca_l_1, arbcp4_cpxdp_q0_hold_bufp1_ca_1,
arbcp4_cpxdp_qsel0_bufp1_ca_l_1, arbcp4_cpxdp_qsel1_bufp1_ca_1,
arbcp4_cpxdp_shift_bufp1_cx_l_1, arbcp5_cpxdp_grant_bufp1_ca_l_1,
arbcp5_cpxdp_q0_hold_bufp1_ca_1, arbcp5_cpxdp_qsel0_bufp1_ca_l_1,
arbcp5_cpxdp_qsel1_bufp1_ca_1, arbcp5_cpxdp_shift_bufp1_cx_l_1,
arbcp6_cpxdp_grant_bufp1_ca_l_1, arbcp6_cpxdp_q0_hold_bufp1_ca_1,
arbcp6_cpxdp_qsel0_bufp1_ca_l_1, arbcp6_cpxdp_qsel1_bufp1_ca_1,
arbcp6_cpxdp_shift_bufp1_cx_l_1, arbcp7_cpxdp_grant_bufp1_ca_l_1,
arbcp7_cpxdp_q0_hold_bufp1_ca_1, arbcp7_cpxdp_qsel0_bufp1_ca_l_1,
arbcp7_cpxdp_qsel1_bufp1_ca_1, arbcp7_cpxdp_shift_bufp1_cx_l_1,
// Inputs
scache0_cpx_req_bufp0_cq, scache0_cpx_atom_bufp0_cq,
cpx_scache0_grant_ca, cpx_spc0_data_rdy_cx, cpx_spc1_data_rdy_cx,
cpx_spc2_data_rdy_cx, arbcp0_cpxdp_grant_arbbf_ca_0,
arbcp0_cpxdp_q0_hold_arbbf_ca_l_0, arbcp0_cpxdp_qsel0_arbbf_ca_0,
arbcp0_cpxdp_qsel1_arbbf_ca_l_0, arbcp0_cpxdp_shift_arbbf_cx_0,
arbcp1_cpxdp_grant_arbbf_ca_0, arbcp1_cpxdp_q0_hold_arbbf_ca_l_0,
arbcp1_cpxdp_qsel0_arbbf_ca_0, arbcp1_cpxdp_qsel1_arbbf_ca_l_0,
arbcp1_cpxdp_shift_arbbf_cx_0, arbcp2_cpxdp_grant_arbbf_ca_0,
arbcp2_cpxdp_q0_hold_arbbf_ca_l_0, arbcp2_cpxdp_qsel0_arbbf_ca_0,
arbcp2_cpxdp_qsel1_arbbf_ca_l_0, arbcp2_cpxdp_shift_arbbf_cx_0,
arbcp3_cpxdp_grant_arbbf_ca_0, arbcp3_cpxdp_q0_hold_arbbf_ca_l_0,
arbcp3_cpxdp_qsel0_arbbf_ca_0, arbcp3_cpxdp_qsel1_arbbf_ca_l_0,
arbcp3_cpxdp_shift_arbbf_cx_0, arbcp4_cpxdp_grant_arbbf_ca_0,
arbcp4_cpxdp_q0_hold_arbbf_ca_l_0, arbcp4_cpxdp_qsel0_arbbf_ca_0,
arbcp4_cpxdp_qsel1_arbbf_ca_l_0, arbcp4_cpxdp_shift_arbbf_cx_0,
arbcp5_cpxdp_grant_arbbf_ca_0, arbcp5_cpxdp_q0_hold_arbbf_ca_l_0,
arbcp5_cpxdp_qsel0_arbbf_ca_0, arbcp5_cpxdp_qsel1_arbbf_ca_l_0,
arbcp5_cpxdp_shift_arbbf_cx_0, arbcp6_cpxdp_grant_arbbf_ca_0,
arbcp6_cpxdp_q0_hold_arbbf_ca_l_0, arbcp6_cpxdp_qsel0_arbbf_ca_0,
arbcp6_cpxdp_qsel1_arbbf_ca_l_0, arbcp6_cpxdp_shift_arbbf_cx_0,
arbcp7_cpxdp_grant_arbbf_ca_0, arbcp7_cpxdp_q0_hold_arbbf_ca_l_0,
arbcp7_cpxdp_qsel0_arbbf_ca_0, arbcp7_cpxdp_qsel1_arbbf_ca_l_0,
arbcp7_cpxdp_shift_arbbf_cx_0, arbcp0_cpxdp_grant_arbbf_ca_1,
arbcp0_cpxdp_q0_hold_arbbf_ca_l_1, arbcp0_cpxdp_qsel0_arbbf_ca_1,
arbcp0_cpxdp_qsel1_arbbf_ca_l_1, arbcp0_cpxdp_shift_arbbf_cx_1,
arbcp1_cpxdp_grant_arbbf_ca_1, arbcp1_cpxdp_q0_hold_arbbf_ca_l_1,
arbcp1_cpxdp_qsel0_arbbf_ca_1, arbcp1_cpxdp_qsel1_arbbf_ca_l_1,
arbcp1_cpxdp_shift_arbbf_cx_1, arbcp2_cpxdp_grant_arbbf_ca_1,
arbcp2_cpxdp_q0_hold_arbbf_ca_l_1, arbcp2_cpxdp_qsel0_arbbf_ca_1,
arbcp2_cpxdp_qsel1_arbbf_ca_l_1, arbcp2_cpxdp_shift_arbbf_cx_1,
arbcp3_cpxdp_grant_arbbf_ca_1, arbcp3_cpxdp_q0_hold_arbbf_ca_l_1,
arbcp3_cpxdp_qsel0_arbbf_ca_1, arbcp3_cpxdp_qsel1_arbbf_ca_l_1,
arbcp3_cpxdp_shift_arbbf_cx_1, arbcp4_cpxdp_grant_arbbf_ca_1,
arbcp4_cpxdp_q0_hold_arbbf_ca_l_1, arbcp4_cpxdp_qsel0_arbbf_ca_1,
arbcp4_cpxdp_qsel1_arbbf_ca_l_1, arbcp4_cpxdp_shift_arbbf_cx_1,
arbcp5_cpxdp_grant_arbbf_ca_1, arbcp5_cpxdp_q0_hold_arbbf_ca_l_1,
arbcp5_cpxdp_qsel0_arbbf_ca_1, arbcp5_cpxdp_qsel1_arbbf_ca_l_1,
arbcp5_cpxdp_shift_arbbf_cx_1, arbcp6_cpxdp_grant_arbbf_ca_1,
arbcp6_cpxdp_q0_hold_arbbf_ca_l_1, arbcp6_cpxdp_qsel0_arbbf_ca_1,
arbcp6_cpxdp_qsel1_arbbf_ca_l_1, arbcp6_cpxdp_shift_arbbf_cx_1,
arbcp7_cpxdp_grant_arbbf_ca_1, arbcp7_cpxdp_q0_hold_arbbf_ca_l_1,
arbcp7_cpxdp_qsel0_arbbf_ca_1, arbcp7_cpxdp_qsel1_arbbf_ca_l_1,
arbcp7_cpxdp_shift_arbbf_cx_1
);
output [7:0] scache0_cpx_req_bufp1_cq ;
output scache0_cpx_atom_bufp1_cq ;
output [7:0] cpx_scache0_grant_bufp1_ca_l;
output cpx_spc0_data_rdy_bufp1_cx;
output cpx_spc1_data_rdy_bufp1_cx;
output cpx_spc2_data_rdy_bufp1_cx;
output arbcp0_cpxdp_grant_bufp1_ca_l_0 ;
output arbcp0_cpxdp_q0_hold_bufp1_ca_0 ;
output arbcp0_cpxdp_qsel0_bufp1_ca_l_0 ;
output arbcp0_cpxdp_qsel1_bufp1_ca_0 ;
output arbcp0_cpxdp_shift_bufp1_cx_l_0 ;
output arbcp1_cpxdp_grant_bufp1_ca_l_0 ;
output arbcp1_cpxdp_q0_hold_bufp1_ca_0 ;
output arbcp1_cpxdp_qsel0_bufp1_ca_l_0 ;
output arbcp1_cpxdp_qsel1_bufp1_ca_0 ;
output arbcp1_cpxdp_shift_bufp1_cx_l_0 ;
output arbcp2_cpxdp_grant_bufp1_ca_l_0 ;
output arbcp2_cpxdp_q0_hold_bufp1_ca_0 ;
output arbcp2_cpxdp_qsel0_bufp1_ca_l_0 ;
output arbcp2_cpxdp_qsel1_bufp1_ca_0 ;
output arbcp2_cpxdp_shift_bufp1_cx_l_0 ;
output arbcp3_cpxdp_grant_bufp1_ca_l_0 ;
output arbcp3_cpxdp_q0_hold_bufp1_ca_0 ;
output arbcp3_cpxdp_qsel0_bufp1_ca_l_0 ;
output arbcp3_cpxdp_qsel1_bufp1_ca_0 ;
output arbcp3_cpxdp_shift_bufp1_cx_l_0 ;
output arbcp4_cpxdp_grant_bufp1_ca_l_0 ;
output arbcp4_cpxdp_q0_hold_bufp1_ca_0 ;
output arbcp4_cpxdp_qsel0_bufp1_ca_l_0 ;
output arbcp4_cpxdp_qsel1_bufp1_ca_0 ;
output arbcp4_cpxdp_shift_bufp1_cx_l_0 ;
output arbcp5_cpxdp_grant_bufp1_ca_l_0 ;
output arbcp5_cpxdp_q0_hold_bufp1_ca_0 ;
output arbcp5_cpxdp_qsel0_bufp1_ca_l_0 ;
output arbcp5_cpxdp_qsel1_bufp1_ca_0 ;
output arbcp5_cpxdp_shift_bufp1_cx_l_0 ;
output arbcp6_cpxdp_grant_bufp1_ca_l_0 ;
output arbcp6_cpxdp_q0_hold_bufp1_ca_0 ;
output arbcp6_cpxdp_qsel0_bufp1_ca_l_0 ;
output arbcp6_cpxdp_qsel1_bufp1_ca_0 ;
output arbcp6_cpxdp_shift_bufp1_cx_l_0 ;
output arbcp7_cpxdp_grant_bufp1_ca_l_0 ;
output arbcp7_cpxdp_q0_hold_bufp1_ca_0 ;
output arbcp7_cpxdp_qsel0_bufp1_ca_l_0 ;
output arbcp7_cpxdp_qsel1_bufp1_ca_0 ;
output arbcp7_cpxdp_shift_bufp1_cx_l_0 ;
input [7:0] scache0_cpx_req_bufp0_cq;
input scache0_cpx_atom_bufp0_cq;
input [7:0] cpx_scache0_grant_ca;
input cpx_spc0_data_rdy_cx;
input cpx_spc1_data_rdy_cx;
input cpx_spc2_data_rdy_cx;
input arbcp0_cpxdp_grant_arbbf_ca_0;
input arbcp0_cpxdp_q0_hold_arbbf_ca_l_0;
input arbcp0_cpxdp_qsel0_arbbf_ca_0;
input arbcp0_cpxdp_qsel1_arbbf_ca_l_0;
input arbcp0_cpxdp_shift_arbbf_cx_0;
input arbcp1_cpxdp_grant_arbbf_ca_0;
input arbcp1_cpxdp_q0_hold_arbbf_ca_l_0;
input arbcp1_cpxdp_qsel0_arbbf_ca_0;
input arbcp1_cpxdp_qsel1_arbbf_ca_l_0;
input arbcp1_cpxdp_shift_arbbf_cx_0;
input arbcp2_cpxdp_grant_arbbf_ca_0;
input arbcp2_cpxdp_q0_hold_arbbf_ca_l_0;
input arbcp2_cpxdp_qsel0_arbbf_ca_0;
input arbcp2_cpxdp_qsel1_arbbf_ca_l_0;
input arbcp2_cpxdp_shift_arbbf_cx_0;
input arbcp3_cpxdp_grant_arbbf_ca_0;
input arbcp3_cpxdp_q0_hold_arbbf_ca_l_0;
input arbcp3_cpxdp_qsel0_arbbf_ca_0;
input arbcp3_cpxdp_qsel1_arbbf_ca_l_0;
input arbcp3_cpxdp_shift_arbbf_cx_0;
input arbcp4_cpxdp_grant_arbbf_ca_0;
input arbcp4_cpxdp_q0_hold_arbbf_ca_l_0;
input arbcp4_cpxdp_qsel0_arbbf_ca_0;
input arbcp4_cpxdp_qsel1_arbbf_ca_l_0;
input arbcp4_cpxdp_shift_arbbf_cx_0;
input arbcp5_cpxdp_grant_arbbf_ca_0;
input arbcp5_cpxdp_q0_hold_arbbf_ca_l_0;
input arbcp5_cpxdp_qsel0_arbbf_ca_0;
input arbcp5_cpxdp_qsel1_arbbf_ca_l_0;
input arbcp5_cpxdp_shift_arbbf_cx_0;
input arbcp6_cpxdp_grant_arbbf_ca_0;
input arbcp6_cpxdp_q0_hold_arbbf_ca_l_0;
input arbcp6_cpxdp_qsel0_arbbf_ca_0;
input arbcp6_cpxdp_qsel1_arbbf_ca_l_0;
input arbcp6_cpxdp_shift_arbbf_cx_0;
input arbcp7_cpxdp_grant_arbbf_ca_0;
input arbcp7_cpxdp_q0_hold_arbbf_ca_l_0;
input arbcp7_cpxdp_qsel0_arbbf_ca_0;
input arbcp7_cpxdp_qsel1_arbbf_ca_l_0;
input arbcp7_cpxdp_shift_arbbf_cx_0;
output arbcp0_cpxdp_grant_bufp1_ca_l_1 ;
output arbcp0_cpxdp_q0_hold_bufp1_ca_1 ;
output arbcp0_cpxdp_qsel0_bufp1_ca_l_1 ;
output arbcp0_cpxdp_qsel1_bufp1_ca_1 ;
output arbcp0_cpxdp_shift_bufp1_cx_l_1 ;
output arbcp1_cpxdp_grant_bufp1_ca_l_1 ;
output arbcp1_cpxdp_q0_hold_bufp1_ca_1 ;
output arbcp1_cpxdp_qsel0_bufp1_ca_l_1 ;
output arbcp1_cpxdp_qsel1_bufp1_ca_1 ;
output arbcp1_cpxdp_shift_bufp1_cx_l_1 ;
output arbcp2_cpxdp_grant_bufp1_ca_l_1 ;
output arbcp2_cpxdp_q0_hold_bufp1_ca_1 ;
output arbcp2_cpxdp_qsel0_bufp1_ca_l_1 ;
output arbcp2_cpxdp_qsel1_bufp1_ca_1 ;
output arbcp2_cpxdp_shift_bufp1_cx_l_1 ;
output arbcp3_cpxdp_grant_bufp1_ca_l_1 ;
output arbcp3_cpxdp_q0_hold_bufp1_ca_1 ;
output arbcp3_cpxdp_qsel0_bufp1_ca_l_1 ;
output arbcp3_cpxdp_qsel1_bufp1_ca_1 ;
output arbcp3_cpxdp_shift_bufp1_cx_l_1 ;
output arbcp4_cpxdp_grant_bufp1_ca_l_1 ;
output arbcp4_cpxdp_q0_hold_bufp1_ca_1 ;
output arbcp4_cpxdp_qsel0_bufp1_ca_l_1 ;
output arbcp4_cpxdp_qsel1_bufp1_ca_1 ;
output arbcp4_cpxdp_shift_bufp1_cx_l_1 ;
output arbcp5_cpxdp_grant_bufp1_ca_l_1 ;
output arbcp5_cpxdp_q0_hold_bufp1_ca_1 ;
output arbcp5_cpxdp_qsel0_bufp1_ca_l_1 ;
output arbcp5_cpxdp_qsel1_bufp1_ca_1 ;
output arbcp5_cpxdp_shift_bufp1_cx_l_1 ;
output arbcp6_cpxdp_grant_bufp1_ca_l_1 ;
output arbcp6_cpxdp_q0_hold_bufp1_ca_1 ;
output arbcp6_cpxdp_qsel0_bufp1_ca_l_1 ;
output arbcp6_cpxdp_qsel1_bufp1_ca_1 ;
output arbcp6_cpxdp_shift_bufp1_cx_l_1 ;
output arbcp7_cpxdp_grant_bufp1_ca_l_1 ;
output arbcp7_cpxdp_q0_hold_bufp1_ca_1 ;
output arbcp7_cpxdp_qsel0_bufp1_ca_l_1 ;
output arbcp7_cpxdp_qsel1_bufp1_ca_1 ;
output arbcp7_cpxdp_shift_bufp1_cx_l_1 ;
input arbcp0_cpxdp_grant_arbbf_ca_1;
input arbcp0_cpxdp_q0_hold_arbbf_ca_l_1;
input arbcp0_cpxdp_qsel0_arbbf_ca_1;
input arbcp0_cpxdp_qsel1_arbbf_ca_l_1;
input arbcp0_cpxdp_shift_arbbf_cx_1;
input arbcp1_cpxdp_grant_arbbf_ca_1;
input arbcp1_cpxdp_q0_hold_arbbf_ca_l_1;
input arbcp1_cpxdp_qsel0_arbbf_ca_1;
input arbcp1_cpxdp_qsel1_arbbf_ca_l_1;
input arbcp1_cpxdp_shift_arbbf_cx_1;
input arbcp2_cpxdp_grant_arbbf_ca_1;
input arbcp2_cpxdp_q0_hold_arbbf_ca_l_1;
input arbcp2_cpxdp_qsel0_arbbf_ca_1;
input arbcp2_cpxdp_qsel1_arbbf_ca_l_1;
input arbcp2_cpxdp_shift_arbbf_cx_1;
input arbcp3_cpxdp_grant_arbbf_ca_1;
input arbcp3_cpxdp_q0_hold_arbbf_ca_l_1;
input arbcp3_cpxdp_qsel0_arbbf_ca_1;
input arbcp3_cpxdp_qsel1_arbbf_ca_l_1;
input arbcp3_cpxdp_shift_arbbf_cx_1;
input arbcp4_cpxdp_grant_arbbf_ca_1;
input arbcp4_cpxdp_q0_hold_arbbf_ca_l_1;
input arbcp4_cpxdp_qsel0_arbbf_ca_1;
input arbcp4_cpxdp_qsel1_arbbf_ca_l_1;
input arbcp4_cpxdp_shift_arbbf_cx_1;
input arbcp5_cpxdp_grant_arbbf_ca_1;
input arbcp5_cpxdp_q0_hold_arbbf_ca_l_1;
input arbcp5_cpxdp_qsel0_arbbf_ca_1;
input arbcp5_cpxdp_qsel1_arbbf_ca_l_1;
input arbcp5_cpxdp_shift_arbbf_cx_1;
input arbcp6_cpxdp_grant_arbbf_ca_1;
input arbcp6_cpxdp_q0_hold_arbbf_ca_l_1;
input arbcp6_cpxdp_qsel0_arbbf_ca_1;
input arbcp6_cpxdp_qsel1_arbbf_ca_l_1;
input arbcp6_cpxdp_shift_arbbf_cx_1;
input arbcp7_cpxdp_grant_arbbf_ca_1;
input arbcp7_cpxdp_q0_hold_arbbf_ca_l_1;
input arbcp7_cpxdp_qsel0_arbbf_ca_1;
input arbcp7_cpxdp_qsel1_arbbf_ca_l_1;
input arbcp7_cpxdp_shift_arbbf_cx_1;
assign scache0_cpx_req_bufp1_cq[7:0] = scache0_cpx_req_bufp0_cq[7:0];
assign scache0_cpx_atom_bufp1_cq = scache0_cpx_atom_bufp0_cq;
assign cpx_scache0_grant_bufp1_ca_l = ~cpx_scache0_grant_ca;
assign cpx_spc0_data_rdy_bufp1_cx = cpx_spc0_data_rdy_cx;
assign cpx_spc1_data_rdy_bufp1_cx = cpx_spc1_data_rdy_cx;
assign cpx_spc2_data_rdy_bufp1_cx = cpx_spc2_data_rdy_cx;
assign arbcp0_cpxdp_grant_bufp1_ca_l_0 = ~ arbcp0_cpxdp_grant_arbbf_ca_0;
assign arbcp0_cpxdp_q0_hold_bufp1_ca_0 = ~ arbcp0_cpxdp_q0_hold_arbbf_ca_l_0;
assign arbcp0_cpxdp_qsel0_bufp1_ca_l_0 = ~ arbcp0_cpxdp_qsel0_arbbf_ca_0;
assign arbcp0_cpxdp_qsel1_bufp1_ca_0 = ~ arbcp0_cpxdp_qsel1_arbbf_ca_l_0;
assign arbcp0_cpxdp_shift_bufp1_cx_l_0 = ~ arbcp0_cpxdp_shift_arbbf_cx_0;
assign arbcp1_cpxdp_grant_bufp1_ca_l_0 = ~ arbcp1_cpxdp_grant_arbbf_ca_0;
assign arbcp1_cpxdp_q0_hold_bufp1_ca_0 = ~ arbcp1_cpxdp_q0_hold_arbbf_ca_l_0;
assign arbcp1_cpxdp_qsel0_bufp1_ca_l_0 = ~ arbcp1_cpxdp_qsel0_arbbf_ca_0;
assign arbcp1_cpxdp_qsel1_bufp1_ca_0 = ~ arbcp1_cpxdp_qsel1_arbbf_ca_l_0;
assign arbcp1_cpxdp_shift_bufp1_cx_l_0 = ~ arbcp1_cpxdp_shift_arbbf_cx_0;
assign arbcp2_cpxdp_grant_bufp1_ca_l_0 = ~ arbcp2_cpxdp_grant_arbbf_ca_0;
assign arbcp2_cpxdp_q0_hold_bufp1_ca_0 = ~ arbcp2_cpxdp_q0_hold_arbbf_ca_l_0;
assign arbcp2_cpxdp_qsel0_bufp1_ca_l_0 = ~ arbcp2_cpxdp_qsel0_arbbf_ca_0;
assign arbcp2_cpxdp_qsel1_bufp1_ca_0 = ~ arbcp2_cpxdp_qsel1_arbbf_ca_l_0;
assign arbcp2_cpxdp_shift_bufp1_cx_l_0 = ~ arbcp2_cpxdp_shift_arbbf_cx_0;
assign arbcp3_cpxdp_grant_bufp1_ca_l_0 = ~ arbcp3_cpxdp_grant_arbbf_ca_0;
assign arbcp3_cpxdp_q0_hold_bufp1_ca_0 = ~ arbcp3_cpxdp_q0_hold_arbbf_ca_l_0;
assign arbcp3_cpxdp_qsel0_bufp1_ca_l_0 = ~ arbcp3_cpxdp_qsel0_arbbf_ca_0;
assign arbcp3_cpxdp_qsel1_bufp1_ca_0 = ~ arbcp3_cpxdp_qsel1_arbbf_ca_l_0;
assign arbcp3_cpxdp_shift_bufp1_cx_l_0 = ~ arbcp3_cpxdp_shift_arbbf_cx_0;
assign arbcp4_cpxdp_grant_bufp1_ca_l_0 = ~ arbcp4_cpxdp_grant_arbbf_ca_0;
assign arbcp4_cpxdp_q0_hold_bufp1_ca_0 = ~ arbcp4_cpxdp_q0_hold_arbbf_ca_l_0;
assign arbcp4_cpxdp_qsel0_bufp1_ca_l_0 = ~ arbcp4_cpxdp_qsel0_arbbf_ca_0;
assign arbcp4_cpxdp_qsel1_bufp1_ca_0 = ~ arbcp4_cpxdp_qsel1_arbbf_ca_l_0;
assign arbcp4_cpxdp_shift_bufp1_cx_l_0 = ~ arbcp4_cpxdp_shift_arbbf_cx_0;
assign arbcp5_cpxdp_grant_bufp1_ca_l_0 = ~ arbcp5_cpxdp_grant_arbbf_ca_0;
assign arbcp5_cpxdp_q0_hold_bufp1_ca_0 = ~ arbcp5_cpxdp_q0_hold_arbbf_ca_l_0;
assign arbcp5_cpxdp_qsel0_bufp1_ca_l_0 = ~ arbcp5_cpxdp_qsel0_arbbf_ca_0;
assign arbcp5_cpxdp_qsel1_bufp1_ca_0 = ~ arbcp5_cpxdp_qsel1_arbbf_ca_l_0;
assign arbcp5_cpxdp_shift_bufp1_cx_l_0 = ~ arbcp5_cpxdp_shift_arbbf_cx_0;
assign arbcp6_cpxdp_grant_bufp1_ca_l_0 = ~ arbcp6_cpxdp_grant_arbbf_ca_0;
assign arbcp6_cpxdp_q0_hold_bufp1_ca_0 = ~ arbcp6_cpxdp_q0_hold_arbbf_ca_l_0;
assign arbcp6_cpxdp_qsel0_bufp1_ca_l_0 = ~ arbcp6_cpxdp_qsel0_arbbf_ca_0;
assign arbcp6_cpxdp_qsel1_bufp1_ca_0 = ~ arbcp6_cpxdp_qsel1_arbbf_ca_l_0;
assign arbcp6_cpxdp_shift_bufp1_cx_l_0 = ~ arbcp6_cpxdp_shift_arbbf_cx_0;
assign arbcp7_cpxdp_grant_bufp1_ca_l_0 = ~ arbcp7_cpxdp_grant_arbbf_ca_0;
assign arbcp7_cpxdp_q0_hold_bufp1_ca_0 = ~ arbcp7_cpxdp_q0_hold_arbbf_ca_l_0;
assign arbcp7_cpxdp_qsel0_bufp1_ca_l_0 = ~ arbcp7_cpxdp_qsel0_arbbf_ca_0;
assign arbcp7_cpxdp_qsel1_bufp1_ca_0 = ~ arbcp7_cpxdp_qsel1_arbbf_ca_l_0;
assign arbcp7_cpxdp_shift_bufp1_cx_l_0 = ~ arbcp7_cpxdp_shift_arbbf_cx_0;
assign arbcp0_cpxdp_grant_bufp1_ca_l_1 = ~ arbcp0_cpxdp_grant_arbbf_ca_1;
assign arbcp0_cpxdp_q0_hold_bufp1_ca_1 = ~ arbcp0_cpxdp_q0_hold_arbbf_ca_l_1;
assign arbcp0_cpxdp_qsel0_bufp1_ca_l_1 = ~ arbcp0_cpxdp_qsel0_arbbf_ca_1;
assign arbcp0_cpxdp_qsel1_bufp1_ca_1 = ~ arbcp0_cpxdp_qsel1_arbbf_ca_l_1;
assign arbcp0_cpxdp_shift_bufp1_cx_l_1 = ~ arbcp0_cpxdp_shift_arbbf_cx_1;
assign arbcp1_cpxdp_grant_bufp1_ca_l_1 = ~ arbcp1_cpxdp_grant_arbbf_ca_1;
assign arbcp1_cpxdp_q0_hold_bufp1_ca_1 = ~ arbcp1_cpxdp_q0_hold_arbbf_ca_l_1;
assign arbcp1_cpxdp_qsel0_bufp1_ca_l_1 = ~ arbcp1_cpxdp_qsel0_arbbf_ca_1;
assign arbcp1_cpxdp_qsel1_bufp1_ca_1 = ~ arbcp1_cpxdp_qsel1_arbbf_ca_l_1;
assign arbcp1_cpxdp_shift_bufp1_cx_l_1 = ~ arbcp1_cpxdp_shift_arbbf_cx_1;
assign arbcp2_cpxdp_grant_bufp1_ca_l_1 = ~ arbcp2_cpxdp_grant_arbbf_ca_1;
assign arbcp2_cpxdp_q0_hold_bufp1_ca_1 = ~ arbcp2_cpxdp_q0_hold_arbbf_ca_l_1;
assign arbcp2_cpxdp_qsel0_bufp1_ca_l_1 = ~ arbcp2_cpxdp_qsel0_arbbf_ca_1;
assign arbcp2_cpxdp_qsel1_bufp1_ca_1 = ~ arbcp2_cpxdp_qsel1_arbbf_ca_l_1;
assign arbcp2_cpxdp_shift_bufp1_cx_l_1 = ~ arbcp2_cpxdp_shift_arbbf_cx_1;
assign arbcp3_cpxdp_grant_bufp1_ca_l_1 = ~ arbcp3_cpxdp_grant_arbbf_ca_1;
assign arbcp3_cpxdp_q0_hold_bufp1_ca_1 = ~ arbcp3_cpxdp_q0_hold_arbbf_ca_l_1;
assign arbcp3_cpxdp_qsel0_bufp1_ca_l_1 = ~ arbcp3_cpxdp_qsel0_arbbf_ca_1;
assign arbcp3_cpxdp_qsel1_bufp1_ca_1 = ~ arbcp3_cpxdp_qsel1_arbbf_ca_l_1;
assign arbcp3_cpxdp_shift_bufp1_cx_l_1 = ~ arbcp3_cpxdp_shift_arbbf_cx_1;
assign arbcp4_cpxdp_grant_bufp1_ca_l_1 = ~ arbcp4_cpxdp_grant_arbbf_ca_1;
assign arbcp4_cpxdp_q0_hold_bufp1_ca_1 = ~ arbcp4_cpxdp_q0_hold_arbbf_ca_l_1;
assign arbcp4_cpxdp_qsel0_bufp1_ca_l_1 = ~ arbcp4_cpxdp_qsel0_arbbf_ca_1;
assign arbcp4_cpxdp_qsel1_bufp1_ca_1 = ~ arbcp4_cpxdp_qsel1_arbbf_ca_l_1;
assign arbcp4_cpxdp_shift_bufp1_cx_l_1 = ~ arbcp4_cpxdp_shift_arbbf_cx_1;
assign arbcp5_cpxdp_grant_bufp1_ca_l_1 = ~ arbcp5_cpxdp_grant_arbbf_ca_1;
assign arbcp5_cpxdp_q0_hold_bufp1_ca_1 = ~ arbcp5_cpxdp_q0_hold_arbbf_ca_l_1;
assign arbcp5_cpxdp_qsel0_bufp1_ca_l_1 = ~ arbcp5_cpxdp_qsel0_arbbf_ca_1;
assign arbcp5_cpxdp_qsel1_bufp1_ca_1 = ~ arbcp5_cpxdp_qsel1_arbbf_ca_l_1;
assign arbcp5_cpxdp_shift_bufp1_cx_l_1 = ~ arbcp5_cpxdp_shift_arbbf_cx_1;
assign arbcp6_cpxdp_grant_bufp1_ca_l_1 = ~ arbcp6_cpxdp_grant_arbbf_ca_1;
assign arbcp6_cpxdp_q0_hold_bufp1_ca_1 = ~ arbcp6_cpxdp_q0_hold_arbbf_ca_l_1;
assign arbcp6_cpxdp_qsel0_bufp1_ca_l_1 = ~ arbcp6_cpxdp_qsel0_arbbf_ca_1;
assign arbcp6_cpxdp_qsel1_bufp1_ca_1 = ~ arbcp6_cpxdp_qsel1_arbbf_ca_l_1;
assign arbcp6_cpxdp_shift_bufp1_cx_l_1 = ~ arbcp6_cpxdp_shift_arbbf_cx_1;
assign arbcp7_cpxdp_grant_bufp1_ca_l_1 = ~ arbcp7_cpxdp_grant_arbbf_ca_1;
assign arbcp7_cpxdp_q0_hold_bufp1_ca_1 = ~ arbcp7_cpxdp_q0_hold_arbbf_ca_l_1;
assign arbcp7_cpxdp_qsel0_bufp1_ca_l_1 = ~ arbcp7_cpxdp_qsel0_arbbf_ca_1;
assign arbcp7_cpxdp_qsel1_bufp1_ca_1 = ~ arbcp7_cpxdp_qsel1_arbbf_ca_l_1;
assign arbcp7_cpxdp_shift_bufp1_cx_l_1 = ~ arbcp7_cpxdp_shift_arbbf_cx_1;
endmodule
|
(* src = "../../verilog/max6682.v:133", top = 1 *)
module MAX6682 (
(* intersynth_port = "Reset_n_i", src = "../../verilog/max6682.v:135" *)
input Reset_n_i,
(* intersynth_port = "Clk_i", src = "../../verilog/max6682.v:137" *)
input Clk_i,
(* intersynth_conntype = "Bit", intersynth_port = "ReconfModuleIn_s", src = "../../verilog/max6682.v:139" *)
input Enable_i,
(* intersynth_conntype = "Bit", intersynth_port = "ReconfModuleIRQs_s", src = "../../verilog/max6682.v:141" *)
output CpuIntr_o,
(* intersynth_conntype = "Bit", intersynth_port = "Outputs_o", src = "../../verilog/max6682.v:143" *)
output MAX6682CS_n_o,
(* intersynth_conntype = "Byte", intersynth_port = "SPI_DataOut", src = "../../verilog/max6682.v:145" *)
input[7:0] SPI_Data_i,
(* intersynth_conntype = "Bit", intersynth_port = "SPI_Write", src = "../../verilog/max6682.v:147" *)
output SPI_Write_o,
(* intersynth_conntype = "Bit", intersynth_port = "SPI_ReadNext", src = "../../verilog/max6682.v:149" *)
output SPI_ReadNext_o,
(* intersynth_conntype = "Byte", intersynth_port = "SPI_DataIn", src = "../../verilog/max6682.v:151" *)
output[7:0] SPI_Data_o,
(* intersynth_conntype = "Bit", intersynth_port = "SPI_FIFOFull", src = "../../verilog/max6682.v:153" *)
input SPI_FIFOFull_i,
(* intersynth_conntype = "Bit", intersynth_port = "SPI_FIFOEmpty", src = "../../verilog/max6682.v:155" *)
input SPI_FIFOEmpty_i,
(* intersynth_conntype = "Bit", intersynth_port = "SPI_Transmission", src = "../../verilog/max6682.v:157" *)
input SPI_Transmission_i,
(* intersynth_conntype = "Word", intersynth_param = "PeriodCounterPresetH_i", src = "../../verilog/max6682.v:159" *)
input[15:0] PeriodCounterPresetH_i,
(* intersynth_conntype = "Word", intersynth_param = "PeriodCounterPresetL_i", src = "../../verilog/max6682.v:161" *)
input[15:0] PeriodCounterPresetL_i,
(* intersynth_conntype = "Word", intersynth_param = "SensorValue_o", src = "../../verilog/max6682.v:163" *)
output[15:0] SensorValue_o,
(* intersynth_conntype = "Word", intersynth_param = "Threshold_i", src = "../../verilog/max6682.v:165" *)
input[15:0] Threshold_i,
(* intersynth_conntype = "Bit", intersynth_port = "SPI_CPOL", src = "../../verilog/max6682.v:167" *)
output SPI_CPOL_o,
(* intersynth_conntype = "Bit", intersynth_port = "SPI_CPHA", src = "../../verilog/max6682.v:169" *)
output SPI_CPHA_o,
(* intersynth_conntype = "Bit", intersynth_port = "SPI_LSBFE", src = "../../verilog/max6682.v:171" *)
output SPI_LSBFE_o
);
(* src = "../../../../addsubcmp/verilog/addsubcmp_greater.v:8" *)
wire \$extract$\AddSubCmp_Greater_Direct$773.Carry_s ;
(* src = "../../../../addsubcmp/verilog/addsubcmp_greater.v:7" *)
wire [15:0] \$extract$\AddSubCmp_Greater_Direct$773.D_s ;
(* src = "../../../../addsubcmp/verilog/addsubcmp_greater.v:11" *)
wire \$extract$\AddSubCmp_Greater_Direct$773.Overflow_s ;
(* src = "../../../../addsubcmp/verilog/addsubcmp_greater.v:10" *)
wire \$extract$\AddSubCmp_Greater_Direct$773.Sign_s ;
(* src = "../../../../addsubcmp/verilog/addsubcmp_greater.v:9" *)
wire \$extract$\AddSubCmp_Greater_Direct$773.Zero_s ;
(* src = "../../../../counter32/verilog/counter32_rv1.v:12" *)
wire [15:0] \$extract$\Counter32_RV1_Timer$768.DH_s ;
(* src = "../../../../counter32/verilog/counter32_rv1.v:13" *)
wire [15:0] \$extract$\Counter32_RV1_Timer$768.DL_s ;
(* src = "../../../../counter32/verilog/counter32_rv1.v:14" *)
wire \$extract$\Counter32_RV1_Timer$768.Overflow_s ;
(* src = "../../verilog/max6682.v:323" *)
wire [15:0] AbsDiffResult;
(* src = "../../verilog/max6682.v:184" *)
wire [7:0] Byte0;
(* src = "../../verilog/max6682.v:185" *)
wire [7:0] Byte1;
(* src = "../../verilog/max6682.v:9" *)
wire \MAX6682_SPI_FSM_1.SPI_FSM_Done ;
(* src = "../../verilog/max6682.v:4" *)
wire \MAX6682_SPI_FSM_1.SPI_FSM_Start ;
(* src = "../../verilog/max6682.v:24" *)
wire \MAX6682_SPI_FSM_1.SPI_FSM_Wr0 ;
(* src = "../../verilog/max6682.v:23" *)
wire \MAX6682_SPI_FSM_1.SPI_FSM_Wr1 ;
(* src = "../../verilog/max6682.v:216" *)
wire SensorFSM_StoreNewValue;
(* src = "../../verilog/max6682.v:214" *)
wire SensorFSM_TimerEnable;
(* src = "../../verilog/max6682.v:212" *)
wire SensorFSM_TimerOvfl;
(* src = "../../verilog/max6682.v:213" *)
wire SensorFSM_TimerPreset;
(* src = "../../verilog/max6682.v:321" *)
wire [15:0] SensorValue;
wire TRFSM0_1_Out5_s;
wire TRFSM0_1_Out6_s;
wire TRFSM0_1_Out7_s;
wire TRFSM0_1_Out8_s;
wire TRFSM0_1_Out9_s;
wire TRFSM0_1_CfgMode_s;
wire TRFSM0_1_CfgClk_s;
wire TRFSM0_1_CfgShift_s;
wire TRFSM0_1_CfgDataIn_s;
wire TRFSM0_1_CfgDataOut_s;
wire TRFSM1_1_Out6_s;
wire TRFSM1_1_Out7_s;
wire TRFSM1_1_Out8_s;
wire TRFSM1_1_Out9_s;
wire TRFSM1_1_Out10_s;
wire TRFSM1_1_Out11_s;
wire TRFSM1_1_Out12_s;
wire TRFSM1_1_Out13_s;
wire TRFSM1_1_Out14_s;
wire TRFSM1_1_CfgMode_s;
wire TRFSM1_1_CfgClk_s;
wire TRFSM1_1_CfgShift_s;
wire TRFSM1_1_CfgDataIn_s;
wire TRFSM1_1_CfgDataOut_s;
AbsDiff \$extract$\AbsDiff$769 (
.A_i(SensorValue),
.B_i(SensorValue_o),
.D_o(AbsDiffResult)
);
(* src = "../../../../addsubcmp/verilog/addsubcmp_greater.v:13" *)
AddSubCmp \$extract$\AddSubCmp_Greater_Direct$773.ThisAddSubCmp (
.A_i(AbsDiffResult),
.AddOrSub_i(1'b1),
.B_i(Threshold_i),
.Carry_i(1'b0),
.Carry_o(\$extract$\AddSubCmp_Greater_Direct$773.Carry_s ),
.D_o(\$extract$\AddSubCmp_Greater_Direct$773.D_s ),
.Overflow_o(\$extract$\AddSubCmp_Greater_Direct$773.Overflow_s ),
.Sign_o(\$extract$\AddSubCmp_Greater_Direct$773.Sign_s ),
.Zero_o(\$extract$\AddSubCmp_Greater_Direct$773.Zero_s )
);
(* src = "../../../../byte2wordsel/verilog/byte2wordsel_11msb.v:10" *)
Byte2WordSel \$extract$\Byte2WordSel_11MSB_Direct$781.DUT (
.H_i(Byte1),
.L_i(Byte0),
.Mask_i(4'b1011),
.Shift_i(4'b0101),
.Y_o(SensorValue)
);
(* src = "../../../../counter32/verilog/counter32_rv1.v:19" *)
Counter32 \$extract$\Counter32_RV1_Timer$768.ThisCounter (
.Clk_i(Clk_i),
.DH_o(\$extract$\Counter32_RV1_Timer$768.DH_s ),
.DL_o(\$extract$\Counter32_RV1_Timer$768.DL_s ),
.Direction_i(1'b1),
.Enable_i(SensorFSM_TimerEnable),
.Overflow_o(\$extract$\Counter32_RV1_Timer$768.Overflow_s ),
.PresetValH_i(PeriodCounterPresetH_i),
.PresetValL_i(PeriodCounterPresetL_i),
.Preset_i(SensorFSM_TimerPreset),
.ResetSig_i(1'b0),
.Reset_n_i(Reset_n_i),
.Zero_o(SensorFSM_TimerOvfl)
);
WordRegister \$extract$\WordRegister$770 (
.Clk_i(Clk_i),
.D_i(SensorValue),
.Enable_i(SensorFSM_StoreNewValue),
.Q_o(SensorValue_o),
.Reset_n_i(Reset_n_i)
);
TRFSM0 TRFSM0_1 (
.Reset_n_i(Reset_n_i),
.Clk_i(Clk_i),
.In0_i(Enable_i),
.In1_i(\MAX6682_SPI_FSM_1.SPI_FSM_Done ),
.In2_i(SensorFSM_TimerOvfl),
.In3_i(\$extract$\AddSubCmp_Greater_Direct$773.Carry_s ),
.In4_i(\$extract$\AddSubCmp_Greater_Direct$773.Zero_s ),
.In5_i(1'b0),
.Out0_o(\MAX6682_SPI_FSM_1.SPI_FSM_Start ),
.Out1_o(SensorFSM_StoreNewValue),
.Out2_o(SensorFSM_TimerEnable),
.Out3_o(SensorFSM_TimerPreset),
.Out4_o(CpuIntr_o),
.Out5_o(TRFSM0_1_Out5_s),
.Out6_o(TRFSM0_1_Out6_s),
.Out7_o(TRFSM0_1_Out7_s),
.Out8_o(TRFSM0_1_Out8_s),
.Out9_o(TRFSM0_1_Out9_s),
.CfgMode_i(TRFSM0_1_CfgMode_s),
.CfgClk_i(TRFSM0_1_CfgClk_s),
.CfgShift_i(TRFSM0_1_CfgShift_s),
.CfgDataIn_i(TRFSM0_1_CfgDataIn_s),
.CfgDataOut_o(TRFSM0_1_CfgDataOut_s)
);
ByteRegister \$techmap\MAX6682_SPI_FSM_1.$extract$\ByteRegister$771 (
.Clk_i(Clk_i),
.D_i(SPI_Data_i),
.Enable_i(\MAX6682_SPI_FSM_1.SPI_FSM_Wr0 ),
.Q_o(Byte0),
.Reset_n_i(Reset_n_i)
);
ByteRegister \$techmap\MAX6682_SPI_FSM_1.$extract$\ByteRegister$772 (
.Clk_i(Clk_i),
.D_i(SPI_Data_i),
.Enable_i(\MAX6682_SPI_FSM_1.SPI_FSM_Wr1 ),
.Q_o(Byte1),
.Reset_n_i(Reset_n_i)
);
TRFSM1 TRFSM1_1 (
.Reset_n_i(Reset_n_i),
.Clk_i(Clk_i),
.In0_i(\MAX6682_SPI_FSM_1.SPI_FSM_Start ),
.In1_i(SPI_Transmission_i),
.In2_i(1'b0),
.In3_i(1'b0),
.In4_i(1'b0),
.In5_i(1'b0),
.In6_i(1'b0),
.In7_i(1'b0),
.In8_i(1'b0),
.In9_i(1'b0),
.Out0_o(\MAX6682_SPI_FSM_1.SPI_FSM_Wr0 ),
.Out1_o(\MAX6682_SPI_FSM_1.SPI_FSM_Done ),
.Out2_o(\MAX6682_SPI_FSM_1.SPI_FSM_Wr1 ),
.Out3_o(SPI_ReadNext_o),
.Out4_o(MAX6682CS_n_o),
.Out5_o(SPI_Write_o),
.Out6_o(TRFSM1_1_Out6_s),
.Out7_o(TRFSM1_1_Out7_s),
.Out8_o(TRFSM1_1_Out8_s),
.Out9_o(TRFSM1_1_Out9_s),
.Out10_o(TRFSM1_1_Out10_s),
.Out11_o(TRFSM1_1_Out11_s),
.Out12_o(TRFSM1_1_Out12_s),
.Out13_o(TRFSM1_1_Out13_s),
.Out14_o(TRFSM1_1_Out14_s),
.CfgMode_i(TRFSM1_1_CfgMode_s),
.CfgClk_i(TRFSM1_1_CfgClk_s),
.CfgShift_i(TRFSM1_1_CfgShift_s),
.CfgDataIn_i(TRFSM1_1_CfgDataIn_s),
.CfgDataOut_o(TRFSM1_1_CfgDataOut_s)
);
assign SPI_CPHA_o = 1'b0;
assign SPI_CPOL_o = 1'b0;
assign SPI_Data_o = 8'b00000000;
assign SPI_LSBFE_o = 1'b0;
assign TRFSM0_1_CfgMode_s = 1'b0;
assign TRFSM0_1_CfgClk_s = 1'b0;
assign TRFSM0_1_CfgShift_s = 1'b0;
assign TRFSM0_1_CfgDataIn_s = 1'b0;
assign TRFSM1_1_CfgMode_s = 1'b0;
assign TRFSM1_1_CfgClk_s = 1'b0;
assign TRFSM1_1_CfgShift_s = 1'b0;
assign TRFSM1_1_CfgDataIn_s = 1'b0;
endmodule
|
(* -*- coding: utf-8 -*- *)
(************************************************************************)
(* * The Coq Proof Assistant / The Coq Development Team *)
(* v * INRIA, CNRS and contributors - Copyright 1999-2019 *)
(* <O___,, * (see CREDITS file for the list of authors) *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(* * (see LICENSE file for the text of the license) *)
(************************************************************************)
(** * Typeclass-based relations, tactics and standard instances
This is the basic theory needed to formalize morphisms and setoids.
Author: Matthieu Sozeau
Institution: LRI, CNRS UMR 8623 - University Paris Sud
*)
Require Export Coq.Classes.Init.
Require Import Coq.Program.Basics.
Require Import Coq.Program.Tactics.
Require Import Coq.Relations.Relation_Definitions.
Generalizable Variables A B C D R S T U l eqA eqB eqC eqD.
(** We allow to unfold the [relation] definition while doing morphism search. *)
Section Defs.
Context {A : Type}.
(** We rebind relational properties in separate classes to be able to overload each proof. *)
Class Reflexive (R : relation A) :=
reflexivity : forall x : A, R x x.
Definition complement (R : relation A) : relation A := fun x y => R x y -> False.
(** Opaque for proof-search. *)
Typeclasses Opaque complement.
(** These are convertible. *)
Lemma complement_inverse R : complement (flip R) = flip (complement R).
Proof. reflexivity. Qed.
Class Irreflexive (R : relation A) :=
irreflexivity : Reflexive (complement R).
Class Symmetric (R : relation A) :=
symmetry : forall {x y}, R x y -> R y x.
Class Asymmetric (R : relation A) :=
asymmetry : forall {x y}, R x y -> R y x -> False.
Class Transitive (R : relation A) :=
transitivity : forall {x y z}, R x y -> R y z -> R x z.
(** Various combinations of reflexivity, symmetry and transitivity. *)
(** A [PreOrder] is both Reflexive and Transitive. *)
Class PreOrder (R : relation A) : Prop := {
PreOrder_Reflexive :> Reflexive R | 2 ;
PreOrder_Transitive :> Transitive R | 2 }.
(** A [StrictOrder] is both Irreflexive and Transitive. *)
Class StrictOrder (R : relation A) : Prop := {
StrictOrder_Irreflexive :> Irreflexive R ;
StrictOrder_Transitive :> Transitive R }.
(** By definition, a strict order is also asymmetric *)
Global Instance StrictOrder_Asymmetric `(StrictOrder R) : Asymmetric R.
Proof. firstorder. Qed.
(** A partial equivalence relation is Symmetric and Transitive. *)
Class PER (R : relation A) : Prop := {
PER_Symmetric :> Symmetric R | 3 ;
PER_Transitive :> Transitive R | 3 }.
(** Equivalence relations. *)
Class Equivalence (R : relation A) : Prop := {
Equivalence_Reflexive :> Reflexive R ;
Equivalence_Symmetric :> Symmetric R ;
Equivalence_Transitive :> Transitive R }.
(** An Equivalence is a PER plus reflexivity. *)
Global Instance Equivalence_PER {R} `(E:Equivalence R) : PER R | 10 :=
{ }.
(** An Equivalence is a PreOrder plus symmetry. *)
Global Instance Equivalence_PreOrder {R} `(E:Equivalence R) : PreOrder R | 10 :=
{ }.
(** We can now define antisymmetry w.r.t. an equivalence relation on the carrier. *)
Class Antisymmetric eqA `{equ : Equivalence eqA} (R : relation A) :=
antisymmetry : forall {x y}, R x y -> R y x -> eqA x y.
Class subrelation (R R' : relation A) : Prop :=
is_subrelation : forall {x y}, R x y -> R' x y.
(** Any symmetric relation is equal to its inverse. *)
Lemma subrelation_symmetric R `(Symmetric R) : subrelation (flip R) R.
Proof. hnf. intros. red in H0. apply symmetry. assumption. Qed.
Section flip.
Lemma flip_Reflexive `{Reflexive R} : Reflexive (flip R).
Proof. tauto. Qed.
Program Definition flip_Irreflexive `(Irreflexive R) : Irreflexive (flip R) :=
irreflexivity (R:=R).
Program Definition flip_Symmetric `(Symmetric R) : Symmetric (flip R) :=
fun x y H => symmetry (R:=R) H.
Program Definition flip_Asymmetric `(Asymmetric R) : Asymmetric (flip R) :=
fun x y H H' => asymmetry (R:=R) H H'.
Program Definition flip_Transitive `(Transitive R) : Transitive (flip R) :=
fun x y z H H' => transitivity (R:=R) H' H.
Program Definition flip_Antisymmetric `(Antisymmetric eqA R) :
Antisymmetric eqA (flip R).
Proof. firstorder. Qed.
(** Inversing the larger structures *)
Lemma flip_PreOrder `(PreOrder R) : PreOrder (flip R).
Proof. firstorder. Qed.
Lemma flip_StrictOrder `(StrictOrder R) : StrictOrder (flip R).
Proof. firstorder. Qed.
Lemma flip_PER `(PER R) : PER (flip R).
Proof. firstorder. Qed.
Lemma flip_Equivalence `(Equivalence R) : Equivalence (flip R).
Proof. firstorder. Qed.
End flip.
Section complement.
Definition complement_Irreflexive `(Reflexive R)
: Irreflexive (complement R).
Proof. firstorder. Qed.
Definition complement_Symmetric `(Symmetric R) : Symmetric (complement R).
Proof. firstorder. Qed.
End complement.
(** Rewrite relation on a given support: declares a relation as a rewrite
relation for use by the generalized rewriting tactic.
It helps choosing if a rewrite should be handled
by the generalized or the regular rewriting tactic using leibniz equality.
Users can declare an [RewriteRelation A RA] anywhere to declare default
relations. This is also done automatically by the [Declare Relation A RA]
commands. *)
Class RewriteRelation (RA : relation A).
(** Any [Equivalence] declared in the context is automatically considered
a rewrite relation. *)
Global Instance equivalence_rewrite_relation `(Equivalence eqA) : RewriteRelation eqA.
Defined.
(** Leibniz equality. *)
Section Leibniz.
Global Instance eq_Reflexive : Reflexive (@eq A) := @eq_refl A.
Global Instance eq_Symmetric : Symmetric (@eq A) := @eq_sym A.
Global Instance eq_Transitive : Transitive (@eq A) := @eq_trans A.
(** Leibinz equality [eq] is an equivalence relation.
The instance has low priority as it is always applicable
if only the type is constrained. *)
Global Program Instance eq_equivalence : Equivalence (@eq A) | 10.
End Leibniz.
End Defs.
(** Default rewrite relations handled by [setoid_rewrite]. *)
Instance: RewriteRelation impl.
Defined.
Instance: RewriteRelation iff.
Defined.
(** Hints to drive the typeclass resolution avoiding loops
due to the use of full unification. *)
Hint Extern 1 (Reflexive (complement _)) => class_apply @irreflexivity : typeclass_instances.
Hint Extern 3 (Symmetric (complement _)) => class_apply complement_Symmetric : typeclass_instances.
Hint Extern 3 (Irreflexive (complement _)) => class_apply complement_Irreflexive : typeclass_instances.
Hint Extern 3 (Reflexive (flip _)) => apply flip_Reflexive : typeclass_instances.
Hint Extern 3 (Irreflexive (flip _)) => class_apply flip_Irreflexive : typeclass_instances.
Hint Extern 3 (Symmetric (flip _)) => class_apply flip_Symmetric : typeclass_instances.
Hint Extern 3 (Asymmetric (flip _)) => class_apply flip_Asymmetric : typeclass_instances.
Hint Extern 3 (Antisymmetric (flip _)) => class_apply flip_Antisymmetric : typeclass_instances.
Hint Extern 3 (Transitive (flip _)) => class_apply flip_Transitive : typeclass_instances.
Hint Extern 3 (StrictOrder (flip _)) => class_apply flip_StrictOrder : typeclass_instances.
Hint Extern 3 (PreOrder (flip _)) => class_apply flip_PreOrder : typeclass_instances.
Hint Extern 4 (subrelation (flip _) _) =>
class_apply @subrelation_symmetric : typeclass_instances.
Arguments irreflexivity {A R Irreflexive} [x] _.
Arguments symmetry {A} {R} {_} [x] [y] _.
Arguments asymmetry {A} {R} {_} [x] [y] _ _.
Arguments transitivity {A} {R} {_} [x] [y] [z] _ _.
Arguments Antisymmetric A eqA {_} _.
Hint Resolve irreflexivity : ord.
Unset Implicit Arguments.
(** A HintDb for relations. *)
Ltac solve_relation :=
match goal with
| [ |- ?R ?x ?x ] => reflexivity
| [ H : ?R ?x ?y |- ?R ?y ?x ] => symmetry ; exact H
end.
Hint Extern 4 => solve_relation : relations.
(** We can already dualize all these properties. *)
(** * Standard instances. *)
Ltac reduce_hyp H :=
match type of H with
| context [ _ <-> _ ] => fail 1
| _ => red in H ; try reduce_hyp H
end.
Ltac reduce_goal :=
match goal with
| [ |- _ <-> _ ] => fail 1
| _ => red ; intros ; try reduce_goal
end.
Tactic Notation "reduce" "in" hyp(Hid) := reduce_hyp Hid.
Ltac reduce := reduce_goal.
Tactic Notation "apply" "*" constr(t) :=
first [ refine t | refine (t _) | refine (t _ _) | refine (t _ _ _) | refine (t _ _ _ _) |
refine (t _ _ _ _ _) | refine (t _ _ _ _ _ _) | refine (t _ _ _ _ _ _ _) ].
Ltac simpl_relation :=
unfold flip, impl, arrow ; try reduce ; program_simpl ;
try ( solve [ dintuition ]).
Local Obligation Tactic := simpl_relation.
(** Logical implication. *)
Program Instance impl_Reflexive : Reflexive impl.
Program Instance impl_Transitive : Transitive impl.
(** Logical equivalence. *)
Instance iff_Reflexive : Reflexive iff := iff_refl.
Instance iff_Symmetric : Symmetric iff := iff_sym.
Instance iff_Transitive : Transitive iff := iff_trans.
(** Logical equivalence [iff] is an equivalence relation. *)
Program Instance iff_equivalence : Equivalence iff.
(** We now develop a generalization of results on relations for arbitrary predicates.
The resulting theory can be applied to homogeneous binary relations but also to
arbitrary n-ary predicates. *)
Local Open Scope list_scope.
(** A compact representation of non-dependent arities, with the codomain singled-out. *)
(* Note, we do not use [list Type] because it imposes unnecessary universe constraints *)
Inductive Tlist : Type := Tnil : Tlist | Tcons : Type -> Tlist -> Tlist.
Local Infix "::" := Tcons.
Fixpoint arrows (l : Tlist) (r : Type) : Type :=
match l with
| Tnil => r
| A :: l' => A -> arrows l' r
end.
(** We can define abbreviations for operation and relation types based on [arrows]. *)
Definition unary_operation A := arrows (A::Tnil) A.
Definition binary_operation A := arrows (A::A::Tnil) A.
Definition ternary_operation A := arrows (A::A::A::Tnil) A.
(** We define n-ary [predicate]s as functions into [Prop]. *)
Notation predicate l := (arrows l Prop).
(** Unary predicates, or sets. *)
Definition unary_predicate A := predicate (A::Tnil).
(** Homogeneous binary relations, equivalent to [relation A]. *)
Definition binary_relation A := predicate (A::A::Tnil).
(** We can close a predicate by universal or existential quantification. *)
Fixpoint predicate_all (l : Tlist) : predicate l -> Prop :=
match l with
| Tnil => fun f => f
| A :: tl => fun f => forall x : A, predicate_all tl (f x)
end.
Fixpoint predicate_exists (l : Tlist) : predicate l -> Prop :=
match l with
| Tnil => fun f => f
| A :: tl => fun f => exists x : A, predicate_exists tl (f x)
end.
(** Pointwise extension of a binary operation on [T] to a binary operation
on functions whose codomain is [T].
For an operator on [Prop] this lifts the operator to a binary operation. *)
Fixpoint pointwise_extension {T : Type} (op : binary_operation T)
(l : Tlist) : binary_operation (arrows l T) :=
match l with
| Tnil => fun R R' => op R R'
| A :: tl => fun R R' =>
fun x => pointwise_extension op tl (R x) (R' x)
end.
(** Pointwise lifting, equivalent to doing [pointwise_extension] and closing using [predicate_all]. *)
Fixpoint pointwise_lifting (op : binary_relation Prop) (l : Tlist) : binary_relation (predicate l) :=
match l with
| Tnil => fun R R' => op R R'
| A :: tl => fun R R' =>
forall x, pointwise_lifting op tl (R x) (R' x)
end.
(** The n-ary equivalence relation, defined by lifting the 0-ary [iff] relation. *)
Definition predicate_equivalence {l : Tlist} : binary_relation (predicate l) :=
pointwise_lifting iff l.
(** The n-ary implication relation, defined by lifting the 0-ary [impl] relation. *)
Definition predicate_implication {l : Tlist} :=
pointwise_lifting impl l.
(** Notations for pointwise equivalence and implication of predicates. *)
Declare Scope predicate_scope.
Infix "<∙>" := predicate_equivalence (at level 95, no associativity) : predicate_scope.
Infix "-∙>" := predicate_implication (at level 70, right associativity) : predicate_scope.
Local Open Scope predicate_scope.
(** The pointwise liftings of conjunction and disjunctions.
Note that these are [binary_operation]s, building new relations out of old ones. *)
Definition predicate_intersection := pointwise_extension and.
Definition predicate_union := pointwise_extension or.
Infix "/∙\" := predicate_intersection (at level 80, right associativity) : predicate_scope.
Infix "\∙/" := predicate_union (at level 85, right associativity) : predicate_scope.
(** The always [True] and always [False] predicates. *)
Fixpoint true_predicate {l : Tlist} : predicate l :=
match l with
| Tnil => True
| A :: tl => fun _ => @true_predicate tl
end.
Fixpoint false_predicate {l : Tlist} : predicate l :=
match l with
| Tnil => False
| A :: tl => fun _ => @false_predicate tl
end.
Notation "∙⊤∙" := true_predicate : predicate_scope.
Notation "∙⊥∙" := false_predicate : predicate_scope.
(** Predicate equivalence is an equivalence, and predicate implication defines a preorder. *)
Program Instance predicate_equivalence_equivalence :
Equivalence (@predicate_equivalence l).
Next Obligation.
induction l ; firstorder.
Qed.
Next Obligation.
induction l ; firstorder.
Qed.
Next Obligation.
fold pointwise_lifting.
induction l.
- firstorder.
- intros. simpl in *. pose (IHl (x x0) (y x0) (z x0)).
firstorder.
Qed.
Program Instance predicate_implication_preorder :
PreOrder (@predicate_implication l).
Next Obligation.
induction l ; firstorder.
Qed.
Next Obligation.
induction l.
- firstorder.
- unfold predicate_implication in *. simpl in *.
intro. pose (IHl (x x0) (y x0) (z x0)). firstorder.
Qed.
(** We define the various operations which define the algebra on binary relations,
from the general ones. *)
Section Binary.
Context {A : Type}.
Definition relation_equivalence : relation (relation A) :=
@predicate_equivalence (_::_::Tnil).
Global Instance: RewriteRelation relation_equivalence.
Defined.
Definition relation_conjunction (R : relation A) (R' : relation A) : relation A :=
@predicate_intersection (A::A::Tnil) R R'.
Definition relation_disjunction (R : relation A) (R' : relation A) : relation A :=
@predicate_union (A::A::Tnil) R R'.
(** Relation equivalence is an equivalence, and subrelation defines a partial order. *)
Global Instance relation_equivalence_equivalence :
Equivalence relation_equivalence.
Proof. exact (@predicate_equivalence_equivalence (A::A::Tnil)). Qed.
Global Instance relation_implication_preorder : PreOrder (@subrelation A).
Proof. exact (@predicate_implication_preorder (A::A::Tnil)). Qed.
(** *** Partial Order.
A partial order is a preorder which is additionally antisymmetric.
We give an equivalent definition, up-to an equivalence relation
on the carrier. *)
Class PartialOrder eqA `{equ : Equivalence A eqA} R `{preo : PreOrder A R} :=
partial_order_equivalence : relation_equivalence eqA (relation_conjunction R (flip R)).
(** The equivalence proof is sufficient for proving that [R] must be a
morphism for equivalence (see Morphisms). It is also sufficient to
show that [R] is antisymmetric w.r.t. [eqA] *)
Global Instance partial_order_antisym `(PartialOrder eqA R) : Antisymmetric A eqA R.
Proof with auto.
reduce_goal.
pose proof partial_order_equivalence as poe. do 3 red in poe.
apply <- poe. firstorder.
Qed.
Lemma PartialOrder_inverse `(PartialOrder eqA R) : PartialOrder eqA (flip R).
Proof. firstorder. Qed.
End Binary.
Hint Extern 3 (PartialOrder (flip _)) => class_apply PartialOrder_inverse : typeclass_instances.
(** The partial order defined by subrelation and relation equivalence. *)
Program Instance subrelation_partial_order :
PartialOrder (@relation_equivalence A) subrelation.
Next Obligation.
Proof.
unfold relation_equivalence in *. compute; firstorder.
Qed.
Typeclasses Opaque arrows predicate_implication predicate_equivalence
relation_equivalence pointwise_lifting.
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__AND2_2_V
`define SKY130_FD_SC_HDLL__AND2_2_V
/**
* and2: 2-input AND.
*
* Verilog wrapper for and2 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__and2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__and2_2 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__and2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__and2_2 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__and2 base (
.X(X),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__AND2_2_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O21A_2_V
`define SKY130_FD_SC_HS__O21A_2_V
/**
* o21a: 2-input OR into first input of 2-input AND.
*
* X = ((A1 | A2) & B1)
*
* Verilog wrapper for o21a with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__o21a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__o21a_2 (
X ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__o21a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__o21a_2 (
X ,
A1,
A2,
B1
);
output X ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__o21a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__O21A_2_V
|
/* Ragul's FPGA Experiments 2020
* Tested with the EG4S20BG256 FPGA
* Learning to generate VGA signalz
*
* http://tinyvga.com/vga-timing/640x480@60Hz
* https://www.youtube.com/watch?v=4enWoVHCykI
* https://www.fpga4fun.com/PongGame.html
*
* ATTRIBUTE IF YOU END UP USING ANY OF MY WORK
*/
module top(
input wire CLK_24M,
input wire USR_BTN,
output wire [2:0]VGA_RGB,
output wire HSYNC,
output wire VSYNC
);
reg enVcnt;
reg [10:0] hzcount;
reg [10:0] vtcount;
reg RED;
reg BLU;
reg GRN;
initial begin
enVcnt <= 0;
hzcount <= 0;
vtcount <= 0;
end
always @(posedge CLK_24M) begin
if (hzcount < 799) begin
hzcount <= hzcount + 1'b1;
enVcnt <= 0;
end
else begin
hzcount <= 0;
enVcnt <= 1;
end
if (enVcnt == 1'b1) begin
if (vtcount < 524) begin
vtcount <= vtcount + 1'b1;
end
else begin
vtcount <= 0;
end
end
if (hzcount < 639 && vtcount < 479) begin
RED <= vtcount[(hzcount >> 6) % 11];
end
else begin
RED <= 0;
GRN <= 0;
BLU <= 0;
end
end
assign VGA_RGB[0] = RED;
assign VGA_RGB[1] = GRN;
assign VGA_RGB[2] = BLU;
assign HSYNC = (hzcount > 655 && hzcount < 751) ? 1'b1 : 1'b0;
assign VSYNC = (vtcount > 489 && vtcount < 491) ? 1'b1 : 1'b0;
endmodule
|
module controller(clk, ALUop, op, shift, opcode, readnum, writenum, loada, loadb, write, asel, bsel, loadc, loads, reset, loadpc, msel, mwrite, loadir, nsel, vsel );
input clk, reset;
input [1:0] ALUop, op, shift;
input [2:0] opcode, readnum, writenum;
output loada, loadb, write, asel, bsel, loadc, loads, loadpc, msel, mwrite, loadir;
output [1:0] nsel, vsel;
wire [4:0] currentState, nextState;
wire [2:0] opcode;
wire [1:0] operation;
reg [4:0] nextStateToBeUpdated;
reg [14:0] inputData;
//PC States
//Initial State
`define initiatePC 5'b00000
//loading intructions
`define loadPC 5'b00001
`define loadRAM 5'b00010
`define loadIR 5'b00011
//General
`define instrFirst 5'b00100
`define instrLast 5'b00101
//Instruction 2
`define putInB 5'b00110
`define aluMovOpAndPutInC 5'b00111
//ALU States
//Instruction 3
`define readRn 5'b01000
`define putInA 5'b01001
`define aluAddOpAndPutInC 5'b01010
//Instruction 5
`define aluAndOpAndPutInC 5'b01011
//Instruction 6
`define aluNotMovOpAndPutInC 5'b01100
//MEM States
//Instruction 7
`define aluMemLoadOpAndPutInC 5'b01101
`define loadReadAddress 5'b01110
//Instruction 8
`define aluMemStoreOpAndPutInC 5'b01111
`define readRd 5'b10000
//Operation Code
`define MOV 3'b110
`define ALU 3'b101
`define STR 3'b100
`define LDR 3'b011
`define opCodeNone 3'bxxx
//Operations
`define ADD 2'b00
`define CMP 2'b01
`define AND 2'b10
`define MVN 2'b11
`define operationNone 2'bxx
//Register choosing
`define RN 2'b00
`define RD 2'b01
`define RM 2'b10
//vsel to choose with data to let in for the registers
`define MDATA 2'b00
`define SXIMM8 2'b01
`define ZEROANDPC 2'b10
`define C 2'b11
//State Updates
//If reset, set program counter to 1
assign nextState= reset? `initiatePC: nextStateToBeUpdated;
//Update states based on clock
DFlipFlop #(5) StateUpdate(clk, nextState, currentState);
//All outputs needed for module instantiations
assign nsel= inputData[14:13];
assign vsel= inputData[12:11];
assign loada= inputData[10];
assign loadb= inputData[9];
assign write= inputData[8];
assign asel= inputData[7];
assign bsel= inputData[6];
assign loads= inputData[5];
assign loadc= inputData[4];
assign loadpc= inputData[3];
assign msel= inputData[2];
assign mwrite= inputData[1];
assign loadir= inputData[0];
//Specifications for what to do in each state
//Each state is separated by a rising clock update
//At start of each instruction, only loadir= 1, everything else is set to 0 from the instruction states
always @(*) begin
casex({currentState, opcode, op})
//Set everything to zero for initial or reset state
{`initiatePC, `opCodeNone, `operationNone}: inputData= 15'b000000000000000;
//----------
//INSTRUCTION COUNTER + RAM //Loading Instruction and Counter
//Load counter value
//loadPC= 1, else= 0 -> Clk //put all load values back into 0 when finished executing a command
{`loadPC, `opCodeNone, `operationNone}: inputData= 15'b000000000001000;
//load value into RAM
//loadPC= 0, else= before -> Clk
{`loadRAM, `opCodeNone, `operationNone}: inputData= {inputData[14:4], 1'b0, inputData[2:0]};
//load instruction
//loadir= 1, else= before -> Clk
{`loadIR, `opCodeNone, `operationNone}: inputData= {inputData[14:1], 1'b1};
//----------
//INSTRUCTION 1 //Write value of sximm8 into Rn register
//nsel= Rn Vsel= SXIMM8 write= 1 loadir= 0 -> Clk
{`instrFirst, `MOV, `AND}: inputData= {`RN, `SXIMM8, inputData[10:9], 1'b1, inputData[7:1], 1'b0};
//----------
//INSTRUCTION 2 //Write shifted value of Rm register into Rd register
//read value from RM register
//nsel= RM loadir= 0 (write already 0), else= before -> Clk
{`instrFirst, `MOV, `ADD}: inputData= {`RM, inputData[12:1], 1'b0};
//put specified reading value in B
//loadb= 1, else= before -> Clk
{`putInB, `MOV, `ADD}: inputData= {inputData[14:10], 1'b1, inputData[8:0]};
//Add A and Shifted B values and put into register C -> Clk
//bsel= 0 asel= 1 loadc= 1 loadb= 0, else= before -> Clk
{`aluMovOpAndPutInC, `MOV, `ADD}: inputData= {inputData[14:10], 1'b0, inputData[8], 2'b10, inputData[5], 1'b1, inputData[3:0]};
//Put value of C into Rd register
//nsel= `RD vsel= `C write= 1 loadc= 0, else= before -> Clk
{`instrLast, `MOV, `ADD}: inputData= {`RD, `C, inputData[10:9], 1'b1, inputData[7:5], 1'b0, inputData[3:0]};
//----------
//INSTRUCTION 3 //Add values of Rn and shifted Rm and put it in Rd
//read value from RM register
//nsel= RM loadir= 0 (write already 0), else= before -> Clk
{`instrFirst, `ALU, `ADD}: inputData= {`RM, inputData[12:1], 1'b0};
//put specified reading value in B
//loadb= 1, else= before -> Clk
{`putInB, `ALU, `ADD}: inputData= {inputData[14:10], 1'b1, inputData[8:0]};
//read value from RN register
//nsel= `Rn (write already 0) loadb= 0, else= begore -> Clk
{`readRn, `ALU, `ADD}: inputData= {`RN, inputData[12:10], 1'b0, inputData[8:0]};
//put specified reading value in A
//loadb= 0, loada= 1, else= before -> Clk
{`putInA, `ALU, `ADD}: inputData= {inputData[14:11], 2'b10, inputData[8:0]};
//do addition computations and load in register C
//asel= 0 bsel= 0 loadc= 1 loada= 0, else - before -> Clk
{`aluAddOpAndPutInC, `ALU, `ADD}: inputData= {inputData[14:11], 1'b0, inputData[9:8], 2'b00, inputData[5], 1'b1, inputData[3:0]};
//Put Value of C into Rd
//nsel= `RD vsel= `C write= 1 loadc= 0, else= before -> Clk
{`instrLast, `ALU, `ADD}: inputData= {`RD, `C, inputData[10:9], 1'b1, inputData[7:5], 1'b0, inputData[3:0]};
//----------
//INSTRUCTION 4 //Find the status output of Rn - Shifted Rm
//read the value of Rm
//nsel= RM loadir= 0 (write already 0), else= before -> Clk
{`instrFirst, `ALU, `CMP}: inputData= {`RM, inputData[12:1], 1'b0};
//put specified reading value in register B
//loadb= 1 loada= 0, else= before -> Clk
{`putInB, `ALU, `CMP}: inputData= {inputData[14:11], 2'b01, inputData[8:0]};
//read value from RN register
//nsel= `Rn (write already 0) loadb= 0, else= begore -> Clk
{`readRn, `ALU, `CMP}: inputData= {`RN, inputData[12:10], 1'b0, inputData[8:0]};
//put specified reading value in A
//loadb= 0, loada= 1, else= before -> Clk
{`putInA, `ALU, `CMP}: inputData= {inputData[14:11], 2'b10, inputData[8:0]};
//do subtraction computations and load in status
//asel= 0 bsel= 0 loada= 0 loads= 1, else - before -> Clk
{`instrLast, `ALU, `CMP}: inputData= {inputData[14:11], 1'b0, inputData[9:8], 3'b001, inputData[5:0]};
//----------
//INSTRUCTION 5 //Compute Rn ANDed with Shifted Rm and put it in Rd
//read value from RM register
//nsel= RM loadir= 0 (write already 0), else= before -> Clk
{`instrFirst, `ALU, `AND}: inputData= {`RM, inputData[12:1], 1'b0};
//put specified reading value in register B
//loadb= 1 loada= 0, else= before -> Clk
{`putInB, `ALU, `AND}: inputData= {inputData[14:11], 2'b01, inputData[8:0]};
//read value from RN register
//nsel= `Rn (write already 0) loadb= 0, else= begore -> Clk
{`readRn, `ALU, `AND}: inputData= {`RN, inputData[12:10], 1'b0, inputData[8:0]};
//put specified reading value in A
//loadb= 0, loada= 1, else= before -> Clk
{`putInA, `ALU, `AND}: inputData= {inputData[14:11], 2'b10, inputData[8:0]};
//AND values inside reg A and B and then load it into C
//bsel= 0 asel= 0 loada= 0 loadc= 1, else= before -> Clk
{`aluAndOpAndPutInC, `ALU, `AND}: inputData= {inputData[14:11], 1'b0, inputData[9:8], 2'b00, inputData[5], 1'b1, inputData[3:0]};
//Put Value of C into Rd
//nsel= `RD vsel= `C loadc= 0 write= 1, else= before -> Clk
{`instrLast, `ALU, `AND}: inputData= {`RD, `C, inputData[10:9], 1'b1, inputData[7:5], 1'b0, inputData[3:0]};
//----------
//INSTRUCTION 6 //Write NOTed shifted value of Rm register into Rd register
//read value from RM register
//nsel= RM loadir= 0 (write already 0), else= before -> Clk
{`instrFirst, `ALU, `MVN}: inputData= {`RM, inputData[12:1], 1'b0};
//put specified reading value in B
//loada= 0 loadb= 1, else= before -> Clk
{`putInB, `ALU, `MVN}: inputData= {inputData[14:11], 2'b01, inputData[8:0]};
//Add A and Shifted B values and put into register C -> Clk
//bsel= 0 asel= 1 loadb= 0 loadc= 1, else= before -> Clk
{`aluNotMovOpAndPutInC, `ALU, `MVN}: inputData= {inputData[14:10], 1'b0, inputData[8], 2'b10, inputData[5], 1'b1, inputData[3:0]};
//Put value of C into Rd register
//nsel= `RD vsel= `C loadc= 0 write= 1, else= before -> Clk
{`instrLast, `ALU, `MVN}: inputData= {`RD, `C, inputData[10:9], 1'b1, inputData[7:5], 1'b0, inputData[3:0]};
//----------
//INSTRUCTION 7 //load memory from address specified by Rn + imm5 nad put it into RD
//read value from RN register
//nsel= `Rn (write already 0) loadir= 0, else= begore -> Clk
{`instrFirst, `LDR, `ADD}: inputData= {`RN, inputData[12:1], 1'b0};
//put specified reading value in A
//loadb= 0, loada= 1, else= before -> Clk
{`putInA, `LDR, `ADD}: inputData= {inputData[14:11], 2'b10, inputData[8:0]};
//load computed effective address into C
//bsel= 1 asel= 0 loada= 0 loadc= 1, else= before -> Clk
{`aluMemLoadOpAndPutInC, `LDR, `ADD}: inputData= {inputData[14:11], 1'b0, inputData[9:8], 2'b01, inputData[5], 1'b1, inputData[3:0]};
//load address into Ram and put mdata from RAM output into register RD
//msel= 1 mwrite= 0 loadc = 0, else= before -> Clk
{`loadReadAddress, `LDR, `ADD}: inputData= {inputData[14:5], 1'b0, inputData[3], 2'b10, inputData[0]};
//Put mdata into register Rd
//nsel= `RD, vsel= `MDATA, write=1, else = before -> Clk
{`instrLast, `LDR, `ADD}: inputData= {`RD, `MDATA, inputData[10:9], 1'b1, inputData[7:0]};
//----------
//INSTRUCTION 8 //store value of register Rd into memory at address= sximm5+Rn
//read value from RN register
//nsel= `Rn (write already 0) loadir= 0, else= before -> Clk
{`instrFirst, `STR, `ADD}: inputData= {`RN, inputData[12:1], 1'b0};
//put specified reading value in A
//loadb= 0, loada= 1, else= before -> Clk
{`putInA, `STR, `ADD}: inputData= {inputData[14:11], 2'b10, inputData[8:0]};
//load computed effective address into C
//bsel= 1 asel= 0 loada=0 loadc= 1, else= before -> Clk
{`aluMemStoreOpAndPutInC, `STR, `ADD}: inputData= {inputData[14:11], 1'b0, inputData[9:8], 2'b01, inputData[5], 1'b1, inputData[3:0]};
//read value from RD register
//nsel= `RD loadc=0, else= before -> Clk
{`readRd, `STR, `ADD}: inputData= {`RD, inputData[12:5], 1'b0, inputData[3:0]};
//put specified reading value in B
//loada= 0 loadb= 1, else= before -> Clk
{`putInB, `STR, `ADD}: inputData= {inputData[14:11], 2'b01, inputData[8:0]};
//update value in B with address from C into RAM
//mwrite= 1 msel= 1 loadb = 0, else= before -> Clk
{`instrLast, `STR, `ADD}: inputData= {inputData[14:10], 1'b0, inputData[8:3], 2'b11, inputData[0]};
endcase
end
always @(*) begin
casex({currentState, opcode, op})
//Counters and first and last parts of instructions
//Set counter to zero for initial or reset state
{`initiatePC, `opCodeNone, `operationNone}: nextStateToBeUpdated= `loadRAM;
//Loading Instruction and Counter
{`loadPC, `opCodeNone, `operationNone}: nextStateToBeUpdated= `loadRAM;
{`loadRAM, `opCodeNone, `operationNone}: nextStateToBeUpdated= `loadIR;
//When instruction loaded, move into first part of instruction
{`loadIR, `opCodeNone, `operationNone}: nextStateToBeUpdated= `instrFirst;
//When last part of instruction executed, counter+1 to load next instruction
{`instrLast, `opCodeNone, `operationNone}: nextStateToBeUpdated= `loadPC;
//----------
//INSTRUCTION 1
{`instrFirst, `MOV, `AND}: nextStateToBeUpdated= `loadPC;
//----------
//INSTRUCTION 2
{`instrFirst, `MOV, `ADD}: nextStateToBeUpdated= `putInB;
{`putInB, `MOV, `ADD}: nextStateToBeUpdated= `aluMovOpAndPutInC;
{`aluMovOpAndPutInC, `MOV, `ADD}: nextStateToBeUpdated= `instrLast;
//----------
//INSTRUCTION 3
{`instrFirst, `ALU, `ADD}: nextStateToBeUpdated= `putInB;
{`putInB, `ALU, `ADD}: nextStateToBeUpdated= `readRn;
{`readRn, `ALU, `ADD}: nextStateToBeUpdated= `putInA;
{`putInA, `ALU, `ADD}: nextStateToBeUpdated= `aluAddOpAndPutInC;
{`aluAddOpAndPutInC, `ALU, `ADD}: nextStateToBeUpdated= `instrLast;
//----------
//INSTRUCTION 4 //Find the status output of Rn - Shifted Rm
{`instrFirst, `ALU, `CMP}: nextStateToBeUpdated= `putInB;
{`putInB, `ALU, `CMP}: nextStateToBeUpdated= `readRn;
{`readRn, `ALU, `CMP}: nextStateToBeUpdated= `putInA;
{`putInA, `ALU, `CMP}: nextStateToBeUpdated= `instrLast;
//----------
//INSTRUCTION 5 //Compute Rn ANDed with Shifted Rm and put it in Rd
{`instrFirst, `ALU, `AND}: nextStateToBeUpdated= `putInB;
{`putInB, `ALU, `AND}: nextStateToBeUpdated= `readRn;
{`readRn, `ALU, `AND}: nextStateToBeUpdated= `putInA;
{`putInA, `ALU, `AND}: nextStateToBeUpdated= `aluAndOpAndPutInC;
{`aluAndOpAndPutInC, `ALU, `AND}: nextStateToBeUpdated= `instrLast;
//----------
//INSTRUCTION 6 //Write NOTed shifted value of Rm register into Rd register
{`instrFirst, `ALU, `MVN}: nextStateToBeUpdated= `putInB;
{`putInB, `ALU, `MVN}: nextStateToBeUpdated= `aluNotMovOpAndPutInC;
{`aluNotMovOpAndPutInC, `ALU, `MVN}: nextStateToBeUpdated= `instrLast;
//----------
//INSTRUCTION 7 //load memory from address specified by Rn + imm5 nad put it into RD
{`instrFirst, `LDR, `ADD}: nextStateToBeUpdated= `putInA;
{`putInA, `LDR, `ADD}: nextStateToBeUpdated= `aluMemLoadOpAndPutInC;
{`aluMemLoadOpAndPutInC, `LDR, `ADD}: nextStateToBeUpdated= `loadReadAddress;
{`loadReadAddress, `LDR, `ADD}: nextStateToBeUpdated= `instrLast;
//----------
//INSTRUCTION 8 //store value of register Rd into memory at address= sximm5+Rn
{`instrFirst, `STR, `ADD}: nextStateToBeUpdated= `putInA;
{`putInA, `STR, `ADD}: nextStateToBeUpdated= `aluMemStoreOpAndPutInC;
{`aluMemStoreOpAndPutInC, `STR, `ADD}: nextStateToBeUpdated= `readRd;
{`readRd, `STR, `ADD}: nextStateToBeUpdated= `putInB;
{`putInB, `STR, `ADD}: nextStateToBeUpdated= `instrLast;
endcase
end
endmodule
|
//-----------------------------------------------------------------------------
// Copyright (C) 2014 iZsh <izsh at fail0verflow.com>
//
// This code is licensed to you under the terms of the GNU GPL, version 2 or,
// at your option, any later version. See the LICENSE.txt file for the text of
// the license.
//-----------------------------------------------------------------------------
// testbench for min_max_tracker
`include "min_max_tracker.v"
`define FIN "tb_tmp/data.filtered.gold"
`define FOUT_MIN "tb_tmp/data.min"
`define FOUT_MAX "tb_tmp/data.max"
module min_max_tracker_tb;
integer fin;
integer fout_min, fout_max;
integer r;
reg clk;
reg [7:0] adc_d;
wire [7:0] min;
wire [7:0] max;
initial
begin
clk = 0;
fin = $fopen(`FIN, "r");
if (!fin) begin
$display("ERROR: can't open the data file");
$finish;
end
fout_min = $fopen(`FOUT_MIN, "w+");
fout_max = $fopen(`FOUT_MAX, "w+");
if (!$feof(fin))
adc_d = $fgetc(fin); // read the first value
end
always
# 1 clk = !clk;
// input
initial
begin
while (!$feof(fin)) begin
@(negedge clk) adc_d <= $fgetc(fin);
end
if ($feof(fin))
begin
# 3 $fclose(fin);
$fclose(fout_min);
$fclose(fout_max);
$finish;
end
end
initial
begin
// $monitor("%d\t min: %x, max: %x", $time, min, max);
end
// output
always @(negedge clk)
if ($time > 2) begin
r = $fputc(min, fout_min);
r = $fputc(max, fout_max);
end
// module to test
min_max_tracker tracker(clk, adc_d, 8'd127, min, max);
endmodule
|
//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module NIOS_SYSTEMV3_NIOS_CPU_jtag_debug_module_tck (
// inputs:
MonDReg,
break_readreg,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
ir_in,
jtag_state_rti,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tck,
tdi,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
vs_cdr,
vs_sdr,
vs_uir,
// outputs:
ir_out,
jrst_n,
sr,
st_ready_test_idle,
tdo
)
;
output [ 1: 0] ir_out;
output jrst_n;
output [ 37: 0] sr;
output st_ready_test_idle;
output tdo;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input [ 1: 0] ir_in;
input jtag_state_rti;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tck;
input tdi;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
input vs_cdr;
input vs_sdr;
input vs_uir;
reg [ 2: 0] DRsize /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire debugack_sync;
reg [ 1: 0] ir_out;
wire jrst_n;
wire monitor_ready_sync;
reg [ 37: 0] sr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire st_ready_test_idle;
wire tdo;
wire unxcomplemented_resetxx1;
wire unxcomplemented_resetxx2;
always @(posedge tck)
begin
if (vs_cdr)
case (ir_in)
2'b00: begin
sr[35] <= debugack_sync;
sr[34] <= monitor_error;
sr[33] <= resetlatch;
sr[32 : 1] <= MonDReg;
sr[0] <= monitor_ready_sync;
end // 2'b00
2'b01: begin
sr[35 : 0] <= tracemem_trcdata;
sr[37] <= tracemem_tw;
sr[36] <= tracemem_on;
end // 2'b01
2'b10: begin
sr[37] <= trigger_state_1;
sr[36] <= dbrk_hit3_latch;
sr[35] <= dbrk_hit2_latch;
sr[34] <= dbrk_hit1_latch;
sr[33] <= dbrk_hit0_latch;
sr[32 : 1] <= break_readreg;
sr[0] <= trigbrktype;
end // 2'b10
2'b11: begin
sr[15 : 12] <= 1'b0;
sr[11 : 2] <= trc_im_addr;
sr[1] <= trc_wrap;
sr[0] <= trc_on;
end // 2'b11
endcase // ir_in
if (vs_sdr)
case (DRsize)
3'b000: begin
sr <= {tdi, sr[37 : 2], tdi};
end // 3'b000
3'b001: begin
sr <= {tdi, sr[37 : 9], tdi, sr[7 : 1]};
end // 3'b001
3'b010: begin
sr <= {tdi, sr[37 : 17], tdi, sr[15 : 1]};
end // 3'b010
3'b011: begin
sr <= {tdi, sr[37 : 33], tdi, sr[31 : 1]};
end // 3'b011
3'b100: begin
sr <= {tdi, sr[37], tdi, sr[35 : 1]};
end // 3'b100
3'b101: begin
sr <= {tdi, sr[37 : 1]};
end // 3'b101
default: begin
sr <= {tdi, sr[37 : 2], tdi};
end // default
endcase // DRsize
if (vs_uir)
case (ir_in)
2'b00: begin
DRsize <= 3'b100;
end // 2'b00
2'b01: begin
DRsize <= 3'b101;
end // 2'b01
2'b10: begin
DRsize <= 3'b101;
end // 2'b10
2'b11: begin
DRsize <= 3'b010;
end // 2'b11
endcase // ir_in
end
assign tdo = sr[0];
assign st_ready_test_idle = jtag_state_rti;
assign unxcomplemented_resetxx1 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer1
(
.clk (tck),
.din (debugack),
.dout (debugack_sync),
.reset_n (unxcomplemented_resetxx1)
);
defparam the_altera_std_synchronizer1.depth = 2;
assign unxcomplemented_resetxx2 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer2
(
.clk (tck),
.din (monitor_ready),
.dout (monitor_ready_sync),
.reset_n (unxcomplemented_resetxx2)
);
defparam the_altera_std_synchronizer2.depth = 2;
always @(posedge tck or negedge jrst_n)
begin
if (jrst_n == 0)
ir_out <= 2'b0;
else
ir_out <= {debugack_sync, monitor_ready_sync};
end
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign jrst_n = reset_n;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// assign jrst_n = 1;
//synthesis read_comments_as_HDL off
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O2BB2A_FUNCTIONAL_V
`define SKY130_FD_SC_HD__O2BB2A_FUNCTIONAL_V
/**
* o2bb2a: 2-input NAND and 2-input OR into 2-input AND.
*
* X = (!(A1 & A2) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__o2bb2a (
X ,
A1_N,
A2_N,
B1 ,
B2
);
// Module ports
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Local signals
wire nand0_out ;
wire or0_out ;
wire and0_out_X;
// Name Output Other arguments
nand nand0 (nand0_out , A2_N, A1_N );
or or0 (or0_out , B2, B1 );
and and0 (and0_out_X, nand0_out, or0_out);
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__O2BB2A_FUNCTIONAL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLYMETAL6S6S_SYMBOL_V
`define SKY130_FD_SC_MS__DLYMETAL6S6S_SYMBOL_V
/**
* dlymetal6s6s: 6-inverter delay with output from 6th inverter on
* horizontal route.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__dlymetal6s6s (
//# {{data|Data Signals}}
input A,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLYMETAL6S6S_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A31OI_FUNCTIONAL_V
`define SKY130_FD_SC_HS__A31OI_FUNCTIONAL_V
/**
* a31oi: 3-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__a31oi (
VPWR,
VGND,
Y ,
A1 ,
A2 ,
A3 ,
B1
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
// Local signals
wire B1 and0_out ;
wire nor0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A3, A1, A2 );
nor nor0 (nor0_out_Y , B1, and0_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__A31OI_FUNCTIONAL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SDFXTP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__SDFXTP_FUNCTIONAL_PP_V
/**
* sdfxtp: Scan delay flop, non-inverted clock, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_mux_2/sky130_fd_sc_hs__u_mux_2.v"
`include "../u_df_p_pg/sky130_fd_sc_hs__u_df_p_pg.v"
`celldefine
module sky130_fd_sc_hs__sdfxtp (
VPWR,
VGND,
Q ,
CLK ,
D ,
SCD ,
SCE
);
// Module ports
input VPWR;
input VGND;
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
// Local signals
wire buf_Q ;
wire mux_out;
// Delay Name Output Other arguments
sky130_fd_sc_hs__u_mux_2_1 u_mux_20 (mux_out, D, SCD, SCE );
sky130_fd_sc_hs__u_df_p_pg `UNIT_DELAY u_df_p_pg0 (buf_Q , mux_out, CLK, VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__SDFXTP_FUNCTIONAL_PP_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:37:34 05/31/2016
// Design Name:
// Module Name: Contador_ID
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Contador_ID(
input rst,
input [7:0] Cambio,
input got_data,
input clk,
output reg [(N-1):0] Cuenta
);
parameter N = 2;
parameter X = 2;
always @(posedge clk)
if (rst)
Cuenta <= 0;
else if (Cambio == 8'h7A && got_data)
begin
if (Cuenta == X)
Cuenta <= 0;
else
Cuenta <= Cuenta + 1'd1;
end
else if (Cambio == 8'h69 && got_data)
begin
if (Cuenta == 0)
Cuenta <= X;
else
Cuenta <= Cuenta - 1'd1;
end
else
Cuenta <= Cuenta;
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// This is the dac physical interface (drives samples from the low speed clock to the
// dac clock domain.
`timescale 1ns/100ps
module axi_ad9152_if (
// jesd interface
// tx_clk is (line-rate/40)
tx_clk,
tx_data,
// dac interface
dac_clk,
dac_rst,
dac_data_0_0,
dac_data_0_1,
dac_data_0_2,
dac_data_0_3,
dac_data_1_0,
dac_data_1_1,
dac_data_1_2,
dac_data_1_3);
// jesd interface
// tx_clk is (line-rate/40)
input tx_clk;
output [127:0] tx_data;
// dac interface
output dac_clk;
input dac_rst;
input [15:0] dac_data_0_0;
input [15:0] dac_data_0_1;
input [15:0] dac_data_0_2;
input [15:0] dac_data_0_3;
input [15:0] dac_data_1_0;
input [15:0] dac_data_1_1;
input [15:0] dac_data_1_2;
input [15:0] dac_data_1_3;
// internal registers
reg [127:0] tx_data = 'd0;
// reorder data for the jesd links
assign dac_clk = tx_clk;
always @(posedge dac_clk) begin
if (dac_rst == 1'b1) begin
tx_data <= 128'd0;
end else begin
tx_data[127:120] <= dac_data_1_3[ 7: 0];
tx_data[119:112] <= dac_data_1_2[ 7: 0];
tx_data[111:104] <= dac_data_1_1[ 7: 0];
tx_data[103: 96] <= dac_data_1_0[ 7: 0];
tx_data[ 95: 88] <= dac_data_1_3[15: 8];
tx_data[ 87: 80] <= dac_data_1_2[15: 8];
tx_data[ 79: 72] <= dac_data_1_1[15: 8];
tx_data[ 71: 64] <= dac_data_1_0[15: 8];
tx_data[ 63: 56] <= dac_data_0_3[ 7: 0];
tx_data[ 55: 48] <= dac_data_0_2[ 7: 0];
tx_data[ 47: 40] <= dac_data_0_1[ 7: 0];
tx_data[ 39: 32] <= dac_data_0_0[ 7: 0];
tx_data[ 31: 24] <= dac_data_0_3[15: 8];
tx_data[ 23: 16] <= dac_data_0_2[15: 8];
tx_data[ 15: 8] <= dac_data_0_1[15: 8];
tx_data[ 7: 0] <= dac_data_0_0[15: 8];
end
end
endmodule
// ***************************************************************************
// ***************************************************************************
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__OR2B_BLACKBOX_V
`define SKY130_FD_SC_HS__OR2B_BLACKBOX_V
/**
* or2b: 2-input OR, first input inverted.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__or2b (
X ,
A ,
B_N
);
output X ;
input A ;
input B_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__OR2B_BLACKBOX_V
|
/*
* HIFIFO: Harmon Instruments PCI Express to FIFO
* Copyright (C) 2014 Harmon Instruments, LLC
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/
*/
`timescale 1ns/1ps
module pcie_tx
(
input clock,
input reset,
input [15:0] pci_id,
// read completion (rc)
input [31:0] rc_dw2,
input [31:0] rc_data,
input rc_valid,
output reg rc_ready,
// read request (rr)
input rr_valid,
output reg rr_ready,
input [63:0] rr_addr,
input [7:0] rr_tag,
// write request (wr)
input wr_valid,
output wr_ready, // pulses 16 times in request of the next data value
input [63:0] wr_data,
input [63:0] wr_addr,
input wr_last,
// AXI stream to PCI Express core
input tx_tready,
output [63:0] tx_tdata,
output tx_1dw,
output tx_tlast,
output tx_tvalid
);
function [31:0] es; // endian swap
input [31:0] x;
es = {x[7:0], x[15:8], x[23:16], x[31:24]};
endfunction
reg [2:0] state = 0;
// FIFO input
wire fi_ready;
reg [65:0] fi_data;
reg fi_valid = 0;
// wr
reg [63:0] wr_data_next;
reg wr_is_32;
// rr
wire rr_is_32 = rr_addr[63:32] == 0;
reg rr_is_32_q;
assign wr_ready = (state == 5);
always @(posedge clock)
begin
if(reset)
state <= 5'd0;
else
case(state)
default: state <= ~fi_ready ? 3'd0 :
rc_valid ? 3'd1 :
rr_valid ? 3'd3 :
wr_valid ? 3'd5 : 3'd0;
1: state <= 3'd2;
2: state <= 3'd0;
3: state <= 3'd4;
4: state <= 3'd0;
5: state <= 3'd6;
6: state <= 3'd7;
7: state <= ~wr_last ? 3'd7 :
~fi_ready ? 3'd0 :
rc_valid ? 3'd1 :
rr_valid ? 3'd3 :
wr_valid ? 3'd5 : 3'd0;
endcase
fi_valid <= state != 0;
case(state)
// read completion (rc)
1: fi_data <= {2'b00, pci_id, 16'd4, 32'h4A000001}; // always 1 DW
2: fi_data <= {2'b01, es(rc_data), rc_dw2};
// read request (rr)
3: fi_data <= {2'b00, {pci_id, rr_tag[7:0], 8'hFF},
{2'd0, ~rr_is_32, 29'd128}};
4: fi_data <= {rr_is_32_q, 1'b1, rr_addr[31:0],
rr_is_32_q ? rr_addr[31:0] : rr_addr[63:32]};
// write request (wr)
5: begin
wr_is_32 <= wr_addr[63:32] == 0;
fi_data <= {2'b00, pci_id, 16'h00FF, 2'b01, wr_addr[63:32] != 0,
23'd0, 5'd16, 1'b0};
end
6: begin
fi_data <= {2'b00, wr_is_32 ?
{es(wr_data[31:0]), wr_addr[31:0]} :
{wr_addr[31:0], wr_addr[63:32]}};
end
7: begin
fi_data[65:64] <= wr_last ? {wr_is_32, 1'b1} : 2'b00;
fi_data[63:0] <= {2'b00, wr_is_32 ?
{es(wr_data[31:0]), es(wr_data_next[63:32])} :
{es(wr_data_next[63:32]),
es(wr_data_next[31:0])
}
};
end
default: fi_data <= 1'b0;
endcase
wr_data_next <= wr_data;
rr_ready <= (state == 3);
rr_is_32_q <= rr_is_32;
rc_ready <= (state == 1);
end
fwft_fifo #(.NBITS(66), .FULL_OFFSET(9'h1C0)) tx_fifo
(
.reset(reset),
.i_clock(clock),
.i_data(fi_data),
.i_valid(fi_valid),
.i_ready(fi_ready),
.o_clock(clock),
.o_read(tx_tready & tx_tvalid),
.o_data({tx_1dw, tx_tlast, tx_tdata}),
.o_valid(tx_tvalid),
.o_almost_empty()
);
endmodule
module rr_mux4
(
input clock,
input reset,
input [3:0] rri_valid,
output [3:0] rri_ready,
input [63:0] rri_addr_0,
input [63:0] rri_addr_1,
input [63:0] rri_addr_2,
input [63:0] rri_addr_3,
input [TAG-1:0] rri_tag_0,
input [TAG-1:0] rri_tag_1,
input [TAG-1:0] rri_tag_2,
input [TAG-1:0] rri_tag_3,
output reg rro_valid = 0,
input rro_ready,
output [63:0] rro_addr,
output reg [TAG-1:0] rro_tag
);
parameter TAG = 8;
parameter AMIN = 0; // lowest address bit to keep
reg [3:0] state = 0;
reg [63-AMIN:0] rro_addr_s;
assign rro_addr[63:AMIN] = rro_addr_s;
assign rro_addr[AMIN-1:0] = 0;
always @ (posedge clock)
begin
if(reset)
state <= 4'h0;
else
begin
casex(state)
4'h0: state <= state + (rri_valid[0] ? 4'd1 : 4'd4);
4'h4: state <= state + (rri_valid[1] ? 4'd1 : 4'd4);
4'h8: state <= state + (rri_valid[2] ? 4'd1 : 4'd4);
4'hC: state <= state + (rri_valid[3] ? 4'd1 : 4'd4);
4'bxx01: state <= state + rro_ready;
default: state <= state + 1'b1;
endcase
end
rro_valid <= (state[1:0] == 1) && ~rro_ready;
case(state[3:2])
0: rro_addr_s <= rri_addr_0[63:AMIN];
1: rro_addr_s <= rri_addr_1[63:AMIN];
2: rro_addr_s <= rri_addr_2[63:AMIN];
3: rro_addr_s <= rri_addr_3[63:AMIN];
endcase
case(state[3:2])
0: rro_tag <= rri_tag_0;
1: rro_tag <= rri_tag_1;
2: rro_tag <= rri_tag_2;
3: rro_tag <= rri_tag_3;
endcase
end
assign rri_ready[0] = state == 2;
assign rri_ready[1] = state == 6;
assign rri_ready[2] = state == 10;
assign rri_ready[3] = state == 14;
endmodule
module wr_mux
(
input clock,
input reset,
input [3:0] wri_valid,
output [3:0] wri_ready,
input [3:0] wri_last,
input [63:0] wri_addr_0,
input [63:0] wri_addr_1,
input [63:0] wri_addr_2,
input [63:0] wri_addr_3,
input [63:0] wri_data_0,
input [63:0] wri_data_1,
input [63:0] wri_data_2,
input [63:0] wri_data_3,
output wro_valid,
input wro_ready,
output [63:0] wro_addr,
output reg [63:0] wro_data,
output reg wro_last
);
reg [3:0] state = 0;
reg [60:0] wro_addr_s = 0;
assign wro_addr = {wro_addr_s, 3'd0};
assign wri_ready[0] = (state == 1) && wro_ready;
assign wri_ready[1] = (state == 5) && wro_ready;
assign wri_ready[2] = (state == 9) && wro_ready;
assign wri_ready[3] = (state == 13) && wro_ready;
assign wro_valid = (state[1:0] == 1);
always @ (posedge clock)
begin
if(reset)
state <= 4'h0;
else
begin
casex(state)
default: state <= wri_valid[0] ? 4'h1 :
wri_valid[1] ? 4'h5 :
wri_valid[2] ? 4'h9 :
wri_valid[3] ? 4'hD : 4'h0;
4'bxx01: state <= state + wro_ready;
4'h2: state <= ~wri_last[0] ? state :
wri_valid[1] ? 4'h5 :
wri_valid[2] ? 4'h9 :
wri_valid[3] ? 4'hD :
wri_valid[0] ? 4'h1 : 4'h0;
4'h6: state <= ~wri_last[1] ? state :
wri_valid[0] ? 4'h1 :
wri_valid[2] ? 4'h9 :
wri_valid[3] ? 4'hD :
wri_valid[1] ? 4'h5 : 4'h0;
4'hA: state <= ~wri_last[2] ? state :
wri_valid[3] ? 4'hD :
wri_valid[0] ? 4'h1 :
wri_valid[1] ? 4'h5 :
wri_valid[2] ? 4'h9 : 4'h0;
4'hE: state <= ~wri_last[3] ? state :
wri_valid[0] ? 4'h1 :
wri_valid[1] ? 4'h5 :
wri_valid[2] ? 4'h9 :
wri_valid[3] ? 4'hD : 4'h0;
endcase
end
case(state[3:2])
0: wro_addr_s <= wri_addr_0[63:3];
1: wro_addr_s <= wri_addr_1[63:3];
2: wro_addr_s <= wri_addr_2[63:3];
3: wro_addr_s <= wri_addr_3[63:3];
endcase
case(state[3:2])
0: wro_data <= wri_data_0;
1: wro_data <= wri_data_1;
2: wro_data <= wri_data_2;
3: wro_data <= wri_data_3;
endcase
case(state[3:2])
0: wro_last <= wri_last[0];
1: wro_last <= wri_last[1];
2: wro_last <= wri_last[2];
3: wro_last <= wri_last[3];
endcase
end
endmodule
module rr_mux
(
input clock,
input reset,
input [3:0] rri_valid,
output [3:0] rri_ready,
input [63:0] rri_addr_0,
input [63:0] rri_addr_1,
input [63:0] rri_addr_2,
input [63:0] rri_addr_3,
input [2:0] rri_tag_0,
input [2:0] rri_tag_1,
input [2:0] rri_tag_2,
input [2:0] rri_tag_3,
output rro_valid,
input rro_ready,
output [63:0] rro_addr,
output [7:0] rro_tag
);
wire [4:0] rro_tag_raw;
assign rro_tag = {3'b0, rro_tag_raw};
rr_mux4 #(.TAG(5), .AMIN(9)) rr_mux4_0
(.clock(clock),
.reset(reset),
.rri_valid(rri_valid[3:0]),
.rri_ready(rri_ready[3:0]),
.rri_addr_0(rri_addr_0),
.rri_addr_1(rri_addr_1),
.rri_addr_2(rri_addr_2),
.rri_addr_3(rri_addr_3),
.rri_tag_0({2'd0,rri_tag_0}),
.rri_tag_1({2'd1,rri_tag_1}),
.rri_tag_2({2'd2,rri_tag_2}),
.rri_tag_3({2'd3,rri_tag_3}),
.rro_valid(rro_valid),
.rro_ready(rro_ready),
.rro_addr(rro_addr),
.rro_tag(rro_tag_raw)
);
endmodule
|
module VGAController(
input iClk,
input inRst,
input [7:0] iR,
input [7:0] iG,
input [7:0] iB,
output [7:0] oR,
output [7:0] oG,
output [7:0] oB,
output oHSync,
output oVSync,
output oLineValid,
output oFrameValid
);
/*****************************************************************
* H timings
****************************************************************/
parameter H_SYNC_PULSE = 96;
parameter H_SYNC_BACK = 48;
parameter H_SYNC_DATA = 640;
parameter H_SYNC_FRONT = 16;
parameter H_SYNC_TOTAL = H_SYNC_FRONT + H_SYNC_PULSE + H_SYNC_BACK + H_SYNC_DATA;
/*****************************************************************
* V timings
****************************************************************/
parameter V_SYNC_PULSE = 2;
parameter V_SYNC_BACK = 36;
parameter V_SYNC_DATA = 480;
parameter V_SYNC_FRONT = 7;
parameter V_SYNC_TOTAL = V_SYNC_FRONT + V_SYNC_PULSE + V_SYNC_BACK + V_SYNC_DATA;
/*****************************************************************
* Data offsets
****************************************************************/
parameter H_START_DATA = H_SYNC_BACK + H_SYNC_PULSE + H_SYNC_FRONT;
parameter V_START_DATA = V_SYNC_BACK + V_SYNC_PULSE + V_SYNC_FRONT;
parameter H_STOP_DATA = H_START_DATA + H_SYNC_DATA;
parameter V_STOP_DATA = V_START_DATA + V_SYNC_DATA;
/*****************************************************************
* Sync pulses offsets
****************************************************************/
parameter H_START_PULSE = H_SYNC_FRONT;
parameter V_START_PULSE = V_SYNC_FRONT;
parameter H_STOP_PULSE = H_SYNC_FRONT + H_SYNC_PULSE;
parameter V_STOP_PULSE = V_SYNC_FRONT + V_SYNC_PULSE;
/*****************************************************************
* Internal schedule counters
****************************************************************/
reg [12:0] mHCounter = 0;
reg [12:0] mVCounter = 0;
/*****************************************************************
* Async assignments
****************************************************************/
assign oVSync = (mVCounter >= V_START_PULSE && mVCounter < V_STOP_PULSE && inRst ) ? 0 : 1;
assign oHSync = (mHCounter >= H_START_PULSE && mHCounter < H_STOP_PULSE && inRst ) ? 0 : 1;
assign oFrameValid = (mVCounter >= V_START_DATA && mVCounter < V_STOP_DATA && inRst ) ? 1 : 0;
assign oLineValid = (mHCounter >= H_START_DATA && mHCounter < H_STOP_DATA && oFrameValid) ? 1 : 0;
assign oR = (oLineValid && oFrameValid && inRst) ? iR : 0;
assign oG = (oLineValid && oFrameValid && inRst) ? iG : 0;
assign oB = (oLineValid && oFrameValid && inRst) ? iB : 0;
/*****************************************************************
* Pixel counter generator
****************************************************************/
always@(negedge iClk or negedge inRst)
begin
if(~inRst) mHCounter <= 0;
else
begin
if(mHCounter == (H_SYNC_TOTAL - 1)) mHCounter <= 0;
else mHCounter <= mHCounter + 1;
end
end
/*****************************************************************
* Line counter generator
****************************************************************/
always@(negedge iClk or negedge inRst)
begin
if(~inRst) mVCounter <= 0;
else
begin
if(mHCounter == (H_SYNC_TOTAL - 1))
begin
if(mVCounter == (V_SYNC_TOTAL - 1)) mVCounter <= 0;
else mVCounter <= mVCounter + 1;
end
else mVCounter <= mVCounter;
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SDFRTN_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__SDFRTN_BEHAVIORAL_PP_V
/**
* sdfrtn: Scan delay flop, inverted reset, inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_ls__udp_dff_pr_pp_pg_n.v"
`include "../../models/udp_mux_2to1/sky130_fd_sc_ls__udp_mux_2to1.v"
`celldefine
module sky130_fd_sc_ls__sdfrtn (
Q ,
CLK_N ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK_N ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
wire intclk ;
wire mux_out ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire RESET_B_delayed;
wire CLK_N_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire cond4 ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
not not1 (intclk , CLK_N_delayed );
sky130_fd_sc_ls__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_ls__udp_dff$PR_pp$PG$N dff0 (buf_Q , mux_out, intclk, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
assign cond4 = ( awake && ( RESET_B === 1'b1 ) );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__SDFRTN_BEHAVIORAL_PP_V
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
// Date : Wed Sep 20 21:12:07 2017
// Host : EffulgentTome running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top zqynq_lab_1_design_auto_pc_0 -prefix
// zqynq_lab_1_design_auto_pc_0_ zqynq_lab_1_design_auto_pc_2_sim_netlist.v
// Design : zqynq_lab_1_design_auto_pc_2
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* C_AXI_ADDR_WIDTH = "32" *) (* C_AXI_ARUSER_WIDTH = "1" *) (* C_AXI_AWUSER_WIDTH = "1" *)
(* C_AXI_BUSER_WIDTH = "1" *) (* C_AXI_DATA_WIDTH = "32" *) (* C_AXI_ID_WIDTH = "12" *)
(* C_AXI_RUSER_WIDTH = "1" *) (* C_AXI_SUPPORTS_READ = "1" *) (* C_AXI_SUPPORTS_USER_SIGNALS = "0" *)
(* C_AXI_SUPPORTS_WRITE = "1" *) (* C_AXI_WUSER_WIDTH = "1" *) (* C_FAMILY = "zynq" *)
(* C_IGNORE_ID = "0" *) (* C_M_AXI_PROTOCOL = "2" *) (* C_S_AXI_PROTOCOL = "0" *)
(* C_TRANSLATION_MODE = "2" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* P_AXI3 = "1" *)
(* P_AXI4 = "0" *) (* P_AXILITE = "2" *) (* P_AXILITE_SIZE = "3'b010" *)
(* P_CONVERSION = "2" *) (* P_DECERR = "2'b11" *) (* P_INCR = "2'b01" *)
(* P_PROTECTION = "1" *) (* P_SLVERR = "2'b10" *)
module zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter
(aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awregion,
s_axi_awqos,
s_axi_awuser,
s_axi_awvalid,
s_axi_awready,
s_axi_wid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wuser,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_buser,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arregion,
s_axi_arqos,
s_axi_aruser,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_ruser,
s_axi_rvalid,
s_axi_rready,
m_axi_awid,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awregion,
m_axi_awqos,
m_axi_awuser,
m_axi_awvalid,
m_axi_awready,
m_axi_wid,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wuser,
m_axi_wvalid,
m_axi_wready,
m_axi_bid,
m_axi_bresp,
m_axi_buser,
m_axi_bvalid,
m_axi_bready,
m_axi_arid,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arregion,
m_axi_arqos,
m_axi_aruser,
m_axi_arvalid,
m_axi_arready,
m_axi_rid,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_ruser,
m_axi_rvalid,
m_axi_rready);
input aclk;
input aresetn;
input [11:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [0:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awregion;
input [3:0]s_axi_awqos;
input [0:0]s_axi_awuser;
input s_axi_awvalid;
output s_axi_awready;
input [11:0]s_axi_wid;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wlast;
input [0:0]s_axi_wuser;
input s_axi_wvalid;
output s_axi_wready;
output [11:0]s_axi_bid;
output [1:0]s_axi_bresp;
output [0:0]s_axi_buser;
output s_axi_bvalid;
input s_axi_bready;
input [11:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [0:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arregion;
input [3:0]s_axi_arqos;
input [0:0]s_axi_aruser;
input s_axi_arvalid;
output s_axi_arready;
output [11:0]s_axi_rid;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output [0:0]s_axi_ruser;
output s_axi_rvalid;
input s_axi_rready;
output [11:0]m_axi_awid;
output [31:0]m_axi_awaddr;
output [7:0]m_axi_awlen;
output [2:0]m_axi_awsize;
output [1:0]m_axi_awburst;
output [0:0]m_axi_awlock;
output [3:0]m_axi_awcache;
output [2:0]m_axi_awprot;
output [3:0]m_axi_awregion;
output [3:0]m_axi_awqos;
output [0:0]m_axi_awuser;
output m_axi_awvalid;
input m_axi_awready;
output [11:0]m_axi_wid;
output [31:0]m_axi_wdata;
output [3:0]m_axi_wstrb;
output m_axi_wlast;
output [0:0]m_axi_wuser;
output m_axi_wvalid;
input m_axi_wready;
input [11:0]m_axi_bid;
input [1:0]m_axi_bresp;
input [0:0]m_axi_buser;
input m_axi_bvalid;
output m_axi_bready;
output [11:0]m_axi_arid;
output [31:0]m_axi_araddr;
output [7:0]m_axi_arlen;
output [2:0]m_axi_arsize;
output [1:0]m_axi_arburst;
output [0:0]m_axi_arlock;
output [3:0]m_axi_arcache;
output [2:0]m_axi_arprot;
output [3:0]m_axi_arregion;
output [3:0]m_axi_arqos;
output [0:0]m_axi_aruser;
output m_axi_arvalid;
input m_axi_arready;
input [11:0]m_axi_rid;
input [31:0]m_axi_rdata;
input [1:0]m_axi_rresp;
input m_axi_rlast;
input [0:0]m_axi_ruser;
input m_axi_rvalid;
output m_axi_rready;
wire \<const0> ;
wire \<const1> ;
wire aclk;
wire aresetn;
wire [31:0]m_axi_araddr;
wire [2:0]m_axi_arprot;
wire m_axi_arready;
wire m_axi_arvalid;
wire [31:0]m_axi_awaddr;
wire [2:0]m_axi_awprot;
wire m_axi_awready;
wire m_axi_awvalid;
wire m_axi_bready;
wire [1:0]m_axi_bresp;
wire m_axi_bvalid;
wire [31:0]m_axi_rdata;
wire m_axi_rready;
wire [1:0]m_axi_rresp;
wire m_axi_rvalid;
wire m_axi_wready;
wire [31:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [11:0]s_axi_arid;
wire [7:0]s_axi_arlen;
wire [2:0]s_axi_arprot;
wire s_axi_arready;
wire [2:0]s_axi_arsize;
wire s_axi_arvalid;
wire [31:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [11:0]s_axi_awid;
wire [7:0]s_axi_awlen;
wire [2:0]s_axi_awprot;
wire s_axi_awready;
wire [2:0]s_axi_awsize;
wire s_axi_awvalid;
wire [11:0]s_axi_bid;
wire s_axi_bready;
wire [1:0]s_axi_bresp;
wire s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire [11:0]s_axi_rid;
wire s_axi_rlast;
wire s_axi_rready;
wire [1:0]s_axi_rresp;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire [3:0]s_axi_wstrb;
wire s_axi_wvalid;
assign m_axi_arburst[1] = \<const0> ;
assign m_axi_arburst[0] = \<const1> ;
assign m_axi_arcache[3] = \<const0> ;
assign m_axi_arcache[2] = \<const0> ;
assign m_axi_arcache[1] = \<const0> ;
assign m_axi_arcache[0] = \<const0> ;
assign m_axi_arid[11] = \<const0> ;
assign m_axi_arid[10] = \<const0> ;
assign m_axi_arid[9] = \<const0> ;
assign m_axi_arid[8] = \<const0> ;
assign m_axi_arid[7] = \<const0> ;
assign m_axi_arid[6] = \<const0> ;
assign m_axi_arid[5] = \<const0> ;
assign m_axi_arid[4] = \<const0> ;
assign m_axi_arid[3] = \<const0> ;
assign m_axi_arid[2] = \<const0> ;
assign m_axi_arid[1] = \<const0> ;
assign m_axi_arid[0] = \<const0> ;
assign m_axi_arlen[7] = \<const0> ;
assign m_axi_arlen[6] = \<const0> ;
assign m_axi_arlen[5] = \<const0> ;
assign m_axi_arlen[4] = \<const0> ;
assign m_axi_arlen[3] = \<const0> ;
assign m_axi_arlen[2] = \<const0> ;
assign m_axi_arlen[1] = \<const0> ;
assign m_axi_arlen[0] = \<const0> ;
assign m_axi_arlock[0] = \<const0> ;
assign m_axi_arqos[3] = \<const0> ;
assign m_axi_arqos[2] = \<const0> ;
assign m_axi_arqos[1] = \<const0> ;
assign m_axi_arqos[0] = \<const0> ;
assign m_axi_arregion[3] = \<const0> ;
assign m_axi_arregion[2] = \<const0> ;
assign m_axi_arregion[1] = \<const0> ;
assign m_axi_arregion[0] = \<const0> ;
assign m_axi_arsize[2] = \<const0> ;
assign m_axi_arsize[1] = \<const1> ;
assign m_axi_arsize[0] = \<const0> ;
assign m_axi_aruser[0] = \<const0> ;
assign m_axi_awburst[1] = \<const0> ;
assign m_axi_awburst[0] = \<const1> ;
assign m_axi_awcache[3] = \<const0> ;
assign m_axi_awcache[2] = \<const0> ;
assign m_axi_awcache[1] = \<const0> ;
assign m_axi_awcache[0] = \<const0> ;
assign m_axi_awid[11] = \<const0> ;
assign m_axi_awid[10] = \<const0> ;
assign m_axi_awid[9] = \<const0> ;
assign m_axi_awid[8] = \<const0> ;
assign m_axi_awid[7] = \<const0> ;
assign m_axi_awid[6] = \<const0> ;
assign m_axi_awid[5] = \<const0> ;
assign m_axi_awid[4] = \<const0> ;
assign m_axi_awid[3] = \<const0> ;
assign m_axi_awid[2] = \<const0> ;
assign m_axi_awid[1] = \<const0> ;
assign m_axi_awid[0] = \<const0> ;
assign m_axi_awlen[7] = \<const0> ;
assign m_axi_awlen[6] = \<const0> ;
assign m_axi_awlen[5] = \<const0> ;
assign m_axi_awlen[4] = \<const0> ;
assign m_axi_awlen[3] = \<const0> ;
assign m_axi_awlen[2] = \<const0> ;
assign m_axi_awlen[1] = \<const0> ;
assign m_axi_awlen[0] = \<const0> ;
assign m_axi_awlock[0] = \<const0> ;
assign m_axi_awqos[3] = \<const0> ;
assign m_axi_awqos[2] = \<const0> ;
assign m_axi_awqos[1] = \<const0> ;
assign m_axi_awqos[0] = \<const0> ;
assign m_axi_awregion[3] = \<const0> ;
assign m_axi_awregion[2] = \<const0> ;
assign m_axi_awregion[1] = \<const0> ;
assign m_axi_awregion[0] = \<const0> ;
assign m_axi_awsize[2] = \<const0> ;
assign m_axi_awsize[1] = \<const1> ;
assign m_axi_awsize[0] = \<const0> ;
assign m_axi_awuser[0] = \<const0> ;
assign m_axi_wdata[31:0] = s_axi_wdata;
assign m_axi_wid[11] = \<const0> ;
assign m_axi_wid[10] = \<const0> ;
assign m_axi_wid[9] = \<const0> ;
assign m_axi_wid[8] = \<const0> ;
assign m_axi_wid[7] = \<const0> ;
assign m_axi_wid[6] = \<const0> ;
assign m_axi_wid[5] = \<const0> ;
assign m_axi_wid[4] = \<const0> ;
assign m_axi_wid[3] = \<const0> ;
assign m_axi_wid[2] = \<const0> ;
assign m_axi_wid[1] = \<const0> ;
assign m_axi_wid[0] = \<const0> ;
assign m_axi_wlast = \<const1> ;
assign m_axi_wstrb[3:0] = s_axi_wstrb;
assign m_axi_wuser[0] = \<const0> ;
assign m_axi_wvalid = s_axi_wvalid;
assign s_axi_buser[0] = \<const0> ;
assign s_axi_ruser[0] = \<const0> ;
assign s_axi_wready = m_axi_wready;
GND GND
(.G(\<const0> ));
VCC VCC
(.P(\<const1> ));
zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s \gen_axilite.gen_b2s_conv.axilite_b2s
(.Q({m_axi_awprot,m_axi_awaddr[31:12]}),
.aclk(aclk),
.aresetn(aresetn),
.in({m_axi_rresp,m_axi_rdata}),
.m_axi_araddr(m_axi_araddr[11:0]),
.\m_axi_arprot[2] ({m_axi_arprot,m_axi_araddr[31:12]}),
.m_axi_arready(m_axi_arready),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_awaddr(m_axi_awaddr[11:0]),
.m_axi_awready(m_axi_awready),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_bready(m_axi_bready),
.m_axi_bresp(m_axi_bresp),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_rready(m_axi_rready),
.m_axi_rvalid(m_axi_rvalid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arburst(s_axi_arburst),
.s_axi_arid(s_axi_arid),
.s_axi_arlen(s_axi_arlen),
.s_axi_arprot(s_axi_arprot),
.s_axi_arready(s_axi_arready),
.s_axi_arsize(s_axi_arsize[1:0]),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awburst(s_axi_awburst),
.s_axi_awid(s_axi_awid),
.s_axi_awlen(s_axi_awlen),
.s_axi_awprot(s_axi_awprot),
.s_axi_awready(s_axi_awready),
.s_axi_awsize(s_axi_awsize[1:0]),
.s_axi_awvalid(s_axi_awvalid),
.\s_axi_bid[11] ({s_axi_bid,s_axi_bresp}),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid),
.\s_axi_rid[11] ({s_axi_rid,s_axi_rlast,s_axi_rresp,s_axi_rdata}),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid));
endmodule
module zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s
(s_axi_rvalid,
s_axi_awready,
Q,
s_axi_arready,
\m_axi_arprot[2] ,
s_axi_bvalid,
\s_axi_bid[11] ,
\s_axi_rid[11] ,
m_axi_awvalid,
m_axi_bready,
m_axi_arvalid,
m_axi_rready,
m_axi_awaddr,
m_axi_araddr,
m_axi_awready,
m_axi_arready,
s_axi_rready,
s_axi_awvalid,
aclk,
in,
s_axi_awid,
s_axi_awlen,
s_axi_awburst,
s_axi_awsize,
s_axi_awprot,
s_axi_awaddr,
m_axi_bresp,
s_axi_arid,
s_axi_arlen,
s_axi_arburst,
s_axi_arsize,
s_axi_arprot,
s_axi_araddr,
m_axi_bvalid,
m_axi_rvalid,
s_axi_bready,
s_axi_arvalid,
aresetn);
output s_axi_rvalid;
output s_axi_awready;
output [22:0]Q;
output s_axi_arready;
output [22:0]\m_axi_arprot[2] ;
output s_axi_bvalid;
output [13:0]\s_axi_bid[11] ;
output [46:0]\s_axi_rid[11] ;
output m_axi_awvalid;
output m_axi_bready;
output m_axi_arvalid;
output m_axi_rready;
output [11:0]m_axi_awaddr;
output [11:0]m_axi_araddr;
input m_axi_awready;
input m_axi_arready;
input s_axi_rready;
input s_axi_awvalid;
input aclk;
input [33:0]in;
input [11:0]s_axi_awid;
input [7:0]s_axi_awlen;
input [1:0]s_axi_awburst;
input [1:0]s_axi_awsize;
input [2:0]s_axi_awprot;
input [31:0]s_axi_awaddr;
input [1:0]m_axi_bresp;
input [11:0]s_axi_arid;
input [7:0]s_axi_arlen;
input [1:0]s_axi_arburst;
input [1:0]s_axi_arsize;
input [2:0]s_axi_arprot;
input [31:0]s_axi_araddr;
input m_axi_bvalid;
input m_axi_rvalid;
input s_axi_bready;
input s_axi_arvalid;
input aresetn;
wire [11:4]C;
wire [22:0]Q;
wire \RD.ar_channel_0_n_10 ;
wire \RD.ar_channel_0_n_11 ;
wire \RD.ar_channel_0_n_47 ;
wire \RD.ar_channel_0_n_48 ;
wire \RD.ar_channel_0_n_49 ;
wire \RD.ar_channel_0_n_50 ;
wire \RD.ar_channel_0_n_8 ;
wire \RD.ar_channel_0_n_9 ;
wire \RD.r_channel_0_n_0 ;
wire \RD.r_channel_0_n_2 ;
wire SI_REG_n_134;
wire SI_REG_n_135;
wire SI_REG_n_136;
wire SI_REG_n_137;
wire SI_REG_n_138;
wire SI_REG_n_139;
wire SI_REG_n_140;
wire SI_REG_n_141;
wire SI_REG_n_142;
wire SI_REG_n_143;
wire SI_REG_n_144;
wire SI_REG_n_145;
wire SI_REG_n_146;
wire SI_REG_n_147;
wire SI_REG_n_148;
wire SI_REG_n_149;
wire SI_REG_n_150;
wire SI_REG_n_151;
wire SI_REG_n_158;
wire SI_REG_n_162;
wire SI_REG_n_163;
wire SI_REG_n_164;
wire SI_REG_n_165;
wire SI_REG_n_166;
wire SI_REG_n_167;
wire SI_REG_n_171;
wire SI_REG_n_175;
wire SI_REG_n_176;
wire SI_REG_n_177;
wire SI_REG_n_178;
wire SI_REG_n_179;
wire SI_REG_n_180;
wire SI_REG_n_181;
wire SI_REG_n_182;
wire SI_REG_n_183;
wire SI_REG_n_184;
wire SI_REG_n_185;
wire SI_REG_n_186;
wire SI_REG_n_187;
wire SI_REG_n_188;
wire SI_REG_n_189;
wire SI_REG_n_190;
wire SI_REG_n_191;
wire SI_REG_n_192;
wire SI_REG_n_193;
wire SI_REG_n_194;
wire SI_REG_n_195;
wire SI_REG_n_196;
wire SI_REG_n_20;
wire SI_REG_n_21;
wire SI_REG_n_22;
wire SI_REG_n_23;
wire SI_REG_n_29;
wire SI_REG_n_79;
wire SI_REG_n_80;
wire SI_REG_n_81;
wire SI_REG_n_82;
wire SI_REG_n_88;
wire \WR.aw_channel_0_n_10 ;
wire \WR.aw_channel_0_n_54 ;
wire \WR.aw_channel_0_n_55 ;
wire \WR.aw_channel_0_n_56 ;
wire \WR.aw_channel_0_n_57 ;
wire \WR.aw_channel_0_n_7 ;
wire \WR.aw_channel_0_n_9 ;
wire \WR.b_channel_0_n_1 ;
wire \WR.b_channel_0_n_2 ;
wire aclk;
wire [1:0]\ar_cmd_fsm_0/state ;
wire \ar_pipe/p_1_in ;
wire areset_d1;
wire areset_d1_i_1_n_0;
wire aresetn;
wire [1:0]\aw_cmd_fsm_0/state ;
wire \aw_pipe/p_1_in ;
wire [11:0]b_awid;
wire [7:0]b_awlen;
wire b_push;
wire [3:0]\cmd_translator_0/incr_cmd_0/axaddr_incr_reg ;
wire [3:0]\cmd_translator_0/incr_cmd_0/axaddr_incr_reg_5 ;
wire \cmd_translator_0/incr_cmd_0/sel_first ;
wire \cmd_translator_0/incr_cmd_0/sel_first_4 ;
wire [3:0]\cmd_translator_0/wrap_cmd_0/axaddr_offset ;
wire [3:0]\cmd_translator_0/wrap_cmd_0/axaddr_offset_0 ;
wire [3:0]\cmd_translator_0/wrap_cmd_0/axaddr_offset_r ;
wire [3:0]\cmd_translator_0/wrap_cmd_0/axaddr_offset_r_2 ;
wire [3:0]\cmd_translator_0/wrap_cmd_0/wrap_second_len ;
wire [3:0]\cmd_translator_0/wrap_cmd_0/wrap_second_len_1 ;
wire [3:0]\cmd_translator_0/wrap_cmd_0/wrap_second_len_r ;
wire [3:0]\cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3 ;
wire [33:0]in;
wire [11:0]m_axi_araddr;
wire [22:0]\m_axi_arprot[2] ;
wire m_axi_arready;
wire m_axi_arvalid;
wire [11:0]m_axi_awaddr;
wire m_axi_awready;
wire m_axi_awvalid;
wire m_axi_bready;
wire [1:0]m_axi_bresp;
wire m_axi_bvalid;
wire m_axi_rready;
wire m_axi_rvalid;
wire r_rlast;
wire [11:0]s_arid;
wire [11:0]s_arid_r;
wire [11:0]s_awid;
wire [31:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [11:0]s_axi_arid;
wire [7:0]s_axi_arlen;
wire [2:0]s_axi_arprot;
wire s_axi_arready;
wire [1:0]s_axi_arsize;
wire s_axi_arvalid;
wire [31:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [11:0]s_axi_awid;
wire [7:0]s_axi_awlen;
wire [2:0]s_axi_awprot;
wire s_axi_awready;
wire [1:0]s_axi_awsize;
wire s_axi_awvalid;
wire [13:0]\s_axi_bid[11] ;
wire s_axi_bready;
wire s_axi_bvalid;
wire [46:0]\s_axi_rid[11] ;
wire s_axi_rready;
wire s_axi_rvalid;
wire [11:0]si_rs_araddr;
wire [1:1]si_rs_arburst;
wire [3:0]si_rs_arlen;
wire [1:0]si_rs_arsize;
wire si_rs_arvalid;
wire [11:0]si_rs_awaddr;
wire [1:1]si_rs_awburst;
wire [3:0]si_rs_awlen;
wire [1:0]si_rs_awsize;
wire si_rs_awvalid;
wire [11:0]si_rs_bid;
wire si_rs_bready;
wire [1:0]si_rs_bresp;
wire si_rs_bvalid;
wire [31:0]si_rs_rdata;
wire [11:0]si_rs_rid;
wire si_rs_rlast;
wire si_rs_rready;
wire [1:0]si_rs_rresp;
wire [3:0]wrap_cnt;
zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_ar_channel \RD.ar_channel_0
(.CO(SI_REG_n_147),
.D({\cmd_translator_0/wrap_cmd_0/wrap_second_len [3:2],\cmd_translator_0/wrap_cmd_0/wrap_second_len [0]}),
.E(\ar_pipe/p_1_in ),
.O({SI_REG_n_148,SI_REG_n_149,SI_REG_n_150,SI_REG_n_151}),
.Q(\ar_cmd_fsm_0/state ),
.S({\RD.ar_channel_0_n_47 ,\RD.ar_channel_0_n_48 ,\RD.ar_channel_0_n_49 ,\RD.ar_channel_0_n_50 }),
.aclk(aclk),
.areset_d1(areset_d1),
.\axaddr_incr_reg[3] (\cmd_translator_0/incr_cmd_0/axaddr_incr_reg ),
.axaddr_offset(\cmd_translator_0/wrap_cmd_0/axaddr_offset [2:0]),
.\axaddr_offset_r_reg[3] (\cmd_translator_0/wrap_cmd_0/axaddr_offset [3]),
.\axaddr_offset_r_reg[3]_0 (\cmd_translator_0/wrap_cmd_0/axaddr_offset_r ),
.\cnt_read_reg[2]_rep__0 (\RD.r_channel_0_n_0 ),
.m_axi_araddr(m_axi_araddr),
.m_axi_arready(m_axi_arready),
.m_axi_arvalid(m_axi_arvalid),
.\m_payload_i_reg[0] (\RD.ar_channel_0_n_9 ),
.\m_payload_i_reg[0]_0 (\RD.ar_channel_0_n_10 ),
.\m_payload_i_reg[11] ({SI_REG_n_143,SI_REG_n_144,SI_REG_n_145,SI_REG_n_146}),
.\m_payload_i_reg[38] (SI_REG_n_196),
.\m_payload_i_reg[3] ({SI_REG_n_139,SI_REG_n_140,SI_REG_n_141,SI_REG_n_142}),
.\m_payload_i_reg[44] (SI_REG_n_171),
.\m_payload_i_reg[46] (SI_REG_n_177),
.\m_payload_i_reg[47] (SI_REG_n_175),
.\m_payload_i_reg[51] (SI_REG_n_176),
.\m_payload_i_reg[64] ({s_arid,SI_REG_n_79,SI_REG_n_80,SI_REG_n_81,SI_REG_n_82,si_rs_arlen,si_rs_arburst,SI_REG_n_88,si_rs_arsize,si_rs_araddr}),
.\m_payload_i_reg[6] (SI_REG_n_187),
.\m_payload_i_reg[6]_0 ({SI_REG_n_188,SI_REG_n_189,SI_REG_n_190,SI_REG_n_191,SI_REG_n_192,SI_REG_n_193,SI_REG_n_194}),
.\r_arid_r_reg[11] (s_arid_r),
.r_push_r_reg(\RD.ar_channel_0_n_11 ),
.r_rlast(r_rlast),
.sel_first(\cmd_translator_0/incr_cmd_0/sel_first ),
.si_rs_arvalid(si_rs_arvalid),
.\wrap_boundary_axaddr_r_reg[11] (\RD.ar_channel_0_n_8 ),
.wrap_second_len(\cmd_translator_0/wrap_cmd_0/wrap_second_len [1]),
.\wrap_second_len_r_reg[3] ({\cmd_translator_0/wrap_cmd_0/wrap_second_len_r [3:2],\cmd_translator_0/wrap_cmd_0/wrap_second_len_r [0]}),
.\wrap_second_len_r_reg[3]_0 ({SI_REG_n_165,SI_REG_n_166,SI_REG_n_167}));
zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_r_channel \RD.r_channel_0
(.D(s_arid_r),
.aclk(aclk),
.areset_d1(areset_d1),
.in(in),
.m_axi_rready(m_axi_rready),
.m_axi_rvalid(m_axi_rvalid),
.m_valid_i_reg(\RD.r_channel_0_n_2 ),
.out({si_rs_rresp,si_rs_rdata}),
.r_rlast(r_rlast),
.s_ready_i_reg(SI_REG_n_178),
.si_rs_rready(si_rs_rready),
.\skid_buffer_reg[46] ({si_rs_rid,si_rs_rlast}),
.\state_reg[1]_rep (\RD.r_channel_0_n_0 ),
.\state_reg[1]_rep_0 (\RD.ar_channel_0_n_11 ));
zqynq_lab_1_design_auto_pc_0_axi_register_slice_v2_1_13_axi_register_slice SI_REG
(.CO(SI_REG_n_134),
.D({wrap_cnt[3:2],wrap_cnt[0]}),
.E(\aw_pipe/p_1_in ),
.O({SI_REG_n_135,SI_REG_n_136,SI_REG_n_137,SI_REG_n_138}),
.Q({s_awid,SI_REG_n_20,SI_REG_n_21,SI_REG_n_22,SI_REG_n_23,si_rs_awlen,si_rs_awburst,SI_REG_n_29,si_rs_awsize,Q,si_rs_awaddr}),
.S({\WR.aw_channel_0_n_54 ,\WR.aw_channel_0_n_55 ,\WR.aw_channel_0_n_56 ,\WR.aw_channel_0_n_57 }),
.aclk(aclk),
.aresetn(aresetn),
.axaddr_incr_reg(\cmd_translator_0/incr_cmd_0/axaddr_incr_reg_5 ),
.\axaddr_incr_reg[11] (C),
.\axaddr_incr_reg[11]_0 ({SI_REG_n_143,SI_REG_n_144,SI_REG_n_145,SI_REG_n_146}),
.\axaddr_incr_reg[3] ({SI_REG_n_148,SI_REG_n_149,SI_REG_n_150,SI_REG_n_151}),
.\axaddr_incr_reg[3]_0 (\cmd_translator_0/incr_cmd_0/axaddr_incr_reg ),
.\axaddr_incr_reg[7] ({SI_REG_n_139,SI_REG_n_140,SI_REG_n_141,SI_REG_n_142}),
.\axaddr_incr_reg[7]_0 (SI_REG_n_147),
.axaddr_offset(\cmd_translator_0/wrap_cmd_0/axaddr_offset_0 [2:0]),
.axaddr_offset_0(\cmd_translator_0/wrap_cmd_0/axaddr_offset [2:0]),
.\axaddr_offset_r_reg[3] (SI_REG_n_179),
.\axaddr_offset_r_reg[3]_0 (SI_REG_n_187),
.\axaddr_offset_r_reg[3]_1 (\cmd_translator_0/wrap_cmd_0/axaddr_offset_0 [3]),
.\axaddr_offset_r_reg[3]_2 (\cmd_translator_0/wrap_cmd_0/axaddr_offset_r_2 ),
.\axaddr_offset_r_reg[3]_3 (\cmd_translator_0/wrap_cmd_0/axaddr_offset [3]),
.\axaddr_offset_r_reg[3]_4 (\cmd_translator_0/wrap_cmd_0/axaddr_offset_r ),
.\axlen_cnt_reg[3] (SI_REG_n_162),
.\axlen_cnt_reg[3]_0 (SI_REG_n_175),
.b_push(b_push),
.\cnt_read_reg[3]_rep__0 (SI_REG_n_178),
.\cnt_read_reg[4] ({si_rs_rresp,si_rs_rdata}),
.\cnt_read_reg[4]_rep__0 (\RD.r_channel_0_n_2 ),
.\m_axi_araddr[10] (SI_REG_n_196),
.\m_axi_awaddr[10] (SI_REG_n_195),
.\m_payload_i_reg[3] ({\RD.ar_channel_0_n_47 ,\RD.ar_channel_0_n_48 ,\RD.ar_channel_0_n_49 ,\RD.ar_channel_0_n_50 }),
.m_valid_i_reg(\ar_pipe/p_1_in ),
.next_pending_r_reg(SI_REG_n_163),
.next_pending_r_reg_0(SI_REG_n_164),
.next_pending_r_reg_1(SI_REG_n_176),
.next_pending_r_reg_2(SI_REG_n_177),
.out(si_rs_bid),
.r_push_r_reg({si_rs_rid,si_rs_rlast}),
.\s_arid_r_reg[11] ({s_arid,SI_REG_n_79,SI_REG_n_80,SI_REG_n_81,SI_REG_n_82,si_rs_arlen,si_rs_arburst,SI_REG_n_88,si_rs_arsize,\m_axi_arprot[2] ,si_rs_araddr}),
.s_axi_araddr(s_axi_araddr),
.s_axi_arburst(s_axi_arburst),
.s_axi_arid(s_axi_arid),
.s_axi_arlen(s_axi_arlen),
.s_axi_arprot(s_axi_arprot),
.s_axi_arready(s_axi_arready),
.s_axi_arsize(s_axi_arsize),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awburst(s_axi_awburst),
.s_axi_awid(s_axi_awid),
.s_axi_awlen(s_axi_awlen),
.s_axi_awprot(s_axi_awprot),
.s_axi_awready(s_axi_awready),
.s_axi_awsize(s_axi_awsize),
.s_axi_awvalid(s_axi_awvalid),
.\s_axi_bid[11] (\s_axi_bid[11] ),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid),
.\s_axi_rid[11] (\s_axi_rid[11] ),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid),
.\s_bresp_acc_reg[1] (si_rs_bresp),
.sel_first(\cmd_translator_0/incr_cmd_0/sel_first_4 ),
.sel_first_2(\cmd_translator_0/incr_cmd_0/sel_first ),
.si_rs_arvalid(si_rs_arvalid),
.si_rs_awvalid(si_rs_awvalid),
.si_rs_bready(si_rs_bready),
.si_rs_bvalid(si_rs_bvalid),
.si_rs_rready(si_rs_rready),
.\state_reg[0]_rep (\WR.aw_channel_0_n_10 ),
.\state_reg[0]_rep_0 (\RD.ar_channel_0_n_9 ),
.\state_reg[1] (\ar_cmd_fsm_0/state ),
.\state_reg[1]_0 (\aw_cmd_fsm_0/state ),
.\state_reg[1]_rep (\WR.aw_channel_0_n_9 ),
.\state_reg[1]_rep_0 (\WR.aw_channel_0_n_7 ),
.\state_reg[1]_rep_1 (\RD.ar_channel_0_n_8 ),
.\state_reg[1]_rep_2 (\RD.ar_channel_0_n_10 ),
.\wrap_boundary_axaddr_r_reg[6] ({SI_REG_n_180,SI_REG_n_181,SI_REG_n_182,SI_REG_n_183,SI_REG_n_184,SI_REG_n_185,SI_REG_n_186}),
.\wrap_boundary_axaddr_r_reg[6]_0 ({SI_REG_n_188,SI_REG_n_189,SI_REG_n_190,SI_REG_n_191,SI_REG_n_192,SI_REG_n_193,SI_REG_n_194}),
.\wrap_cnt_r_reg[3] (SI_REG_n_158),
.\wrap_cnt_r_reg[3]_0 ({SI_REG_n_165,SI_REG_n_166,SI_REG_n_167}),
.\wrap_cnt_r_reg[3]_1 (SI_REG_n_171),
.wrap_second_len(\cmd_translator_0/wrap_cmd_0/wrap_second_len_1 [1]),
.wrap_second_len_1(\cmd_translator_0/wrap_cmd_0/wrap_second_len [1]),
.\wrap_second_len_r_reg[3] ({\cmd_translator_0/wrap_cmd_0/wrap_second_len_1 [3:2],\cmd_translator_0/wrap_cmd_0/wrap_second_len_1 [0]}),
.\wrap_second_len_r_reg[3]_0 ({\cmd_translator_0/wrap_cmd_0/wrap_second_len [3:2],\cmd_translator_0/wrap_cmd_0/wrap_second_len [0]}),
.\wrap_second_len_r_reg[3]_1 ({\cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3 [3:2],\cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3 [0]}),
.\wrap_second_len_r_reg[3]_2 ({\cmd_translator_0/wrap_cmd_0/wrap_second_len_r [3:2],\cmd_translator_0/wrap_cmd_0/wrap_second_len_r [0]}));
zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_aw_channel \WR.aw_channel_0
(.CO(SI_REG_n_134),
.D(\cmd_translator_0/wrap_cmd_0/wrap_second_len_1 [1]),
.E(\aw_pipe/p_1_in ),
.O({SI_REG_n_135,SI_REG_n_136,SI_REG_n_137,SI_REG_n_138}),
.Q(\aw_cmd_fsm_0/state ),
.S({\WR.aw_channel_0_n_54 ,\WR.aw_channel_0_n_55 ,\WR.aw_channel_0_n_56 ,\WR.aw_channel_0_n_57 }),
.aclk(aclk),
.areset_d1(areset_d1),
.\axaddr_incr_reg[3] (\cmd_translator_0/incr_cmd_0/axaddr_incr_reg_5 ),
.\axaddr_offset_r_reg[3] (\cmd_translator_0/wrap_cmd_0/axaddr_offset_0 [3]),
.\axaddr_offset_r_reg[3]_0 (\cmd_translator_0/wrap_cmd_0/axaddr_offset_r_2 ),
.b_push(b_push),
.\cnt_read_reg[0]_rep__0 (\WR.b_channel_0_n_1 ),
.\cnt_read_reg[1]_rep__1 (\WR.b_channel_0_n_2 ),
.in({b_awid,b_awlen}),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awready(m_axi_awready),
.m_axi_awvalid(m_axi_awvalid),
.\m_payload_i_reg[11] (C),
.\m_payload_i_reg[35] (\cmd_translator_0/wrap_cmd_0/axaddr_offset_0 [2:0]),
.\m_payload_i_reg[38] (SI_REG_n_195),
.\m_payload_i_reg[44] (SI_REG_n_158),
.\m_payload_i_reg[46] (SI_REG_n_164),
.\m_payload_i_reg[47] (SI_REG_n_162),
.\m_payload_i_reg[48] (SI_REG_n_163),
.\m_payload_i_reg[64] ({s_awid,SI_REG_n_20,SI_REG_n_21,SI_REG_n_22,SI_REG_n_23,si_rs_awlen,si_rs_awburst,SI_REG_n_29,si_rs_awsize,si_rs_awaddr}),
.\m_payload_i_reg[6] (SI_REG_n_179),
.\m_payload_i_reg[6]_0 ({SI_REG_n_180,SI_REG_n_181,SI_REG_n_182,SI_REG_n_183,SI_REG_n_184,SI_REG_n_185,SI_REG_n_186}),
.sel_first(\cmd_translator_0/incr_cmd_0/sel_first_4 ),
.si_rs_awvalid(si_rs_awvalid),
.\state_reg[1]_rep (\WR.aw_channel_0_n_9 ),
.\state_reg[1]_rep_0 (\WR.aw_channel_0_n_10 ),
.\wrap_boundary_axaddr_r_reg[11] (\WR.aw_channel_0_n_7 ),
.\wrap_second_len_r_reg[3] ({\cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3 [3:2],\cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3 [0]}),
.\wrap_second_len_r_reg[3]_0 ({\cmd_translator_0/wrap_cmd_0/wrap_second_len_1 [3:2],\cmd_translator_0/wrap_cmd_0/wrap_second_len_1 [0]}),
.\wrap_second_len_r_reg[3]_1 ({wrap_cnt[3:2],wrap_cnt[0]}));
zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_b_channel \WR.b_channel_0
(.aclk(aclk),
.areset_d1(areset_d1),
.b_push(b_push),
.\cnt_read_reg[0]_rep__0 (\WR.b_channel_0_n_1 ),
.\cnt_read_reg[1]_rep__1 (\WR.b_channel_0_n_2 ),
.in({b_awid,b_awlen}),
.m_axi_bready(m_axi_bready),
.m_axi_bresp(m_axi_bresp),
.m_axi_bvalid(m_axi_bvalid),
.out(si_rs_bid),
.si_rs_bready(si_rs_bready),
.si_rs_bvalid(si_rs_bvalid),
.\skid_buffer_reg[1] (si_rs_bresp));
LUT1 #(
.INIT(2'h1))
areset_d1_i_1
(.I0(aresetn),
.O(areset_d1_i_1_n_0));
FDRE #(
.INIT(1'b0))
areset_d1_reg
(.C(aclk),
.CE(1'b1),
.D(areset_d1_i_1_n_0),
.Q(areset_d1),
.R(1'b0));
endmodule
module zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_ar_channel
(\axaddr_incr_reg[3] ,
sel_first,
Q,
wrap_second_len,
\wrap_boundary_axaddr_r_reg[11] ,
\m_payload_i_reg[0] ,
\m_payload_i_reg[0]_0 ,
r_push_r_reg,
\wrap_second_len_r_reg[3] ,
\axaddr_offset_r_reg[3] ,
\axaddr_offset_r_reg[3]_0 ,
m_axi_arvalid,
r_rlast,
E,
m_axi_araddr,
\r_arid_r_reg[11] ,
S,
aclk,
O,
\m_payload_i_reg[47] ,
si_rs_arvalid,
\m_payload_i_reg[44] ,
\m_payload_i_reg[64] ,
m_axi_arready,
CO,
\cnt_read_reg[2]_rep__0 ,
axaddr_offset,
\m_payload_i_reg[46] ,
\m_payload_i_reg[51] ,
areset_d1,
\m_payload_i_reg[6] ,
\m_payload_i_reg[3] ,
\m_payload_i_reg[11] ,
\m_payload_i_reg[38] ,
D,
\wrap_second_len_r_reg[3]_0 ,
\m_payload_i_reg[6]_0 );
output [3:0]\axaddr_incr_reg[3] ;
output sel_first;
output [1:0]Q;
output [0:0]wrap_second_len;
output \wrap_boundary_axaddr_r_reg[11] ;
output \m_payload_i_reg[0] ;
output \m_payload_i_reg[0]_0 ;
output r_push_r_reg;
output [2:0]\wrap_second_len_r_reg[3] ;
output [0:0]\axaddr_offset_r_reg[3] ;
output [3:0]\axaddr_offset_r_reg[3]_0 ;
output m_axi_arvalid;
output r_rlast;
output [0:0]E;
output [11:0]m_axi_araddr;
output [11:0]\r_arid_r_reg[11] ;
output [3:0]S;
input aclk;
input [3:0]O;
input \m_payload_i_reg[47] ;
input si_rs_arvalid;
input \m_payload_i_reg[44] ;
input [35:0]\m_payload_i_reg[64] ;
input m_axi_arready;
input [0:0]CO;
input \cnt_read_reg[2]_rep__0 ;
input [2:0]axaddr_offset;
input \m_payload_i_reg[46] ;
input \m_payload_i_reg[51] ;
input areset_d1;
input \m_payload_i_reg[6] ;
input [3:0]\m_payload_i_reg[3] ;
input [3:0]\m_payload_i_reg[11] ;
input \m_payload_i_reg[38] ;
input [2:0]D;
input [2:0]\wrap_second_len_r_reg[3]_0 ;
input [6:0]\m_payload_i_reg[6]_0 ;
wire [0:0]CO;
wire [2:0]D;
wire [0:0]E;
wire [3:0]O;
wire [1:0]Q;
wire [3:0]S;
wire aclk;
wire ar_cmd_fsm_0_n_0;
wire ar_cmd_fsm_0_n_12;
wire ar_cmd_fsm_0_n_15;
wire ar_cmd_fsm_0_n_16;
wire ar_cmd_fsm_0_n_17;
wire ar_cmd_fsm_0_n_20;
wire ar_cmd_fsm_0_n_21;
wire ar_cmd_fsm_0_n_3;
wire ar_cmd_fsm_0_n_8;
wire ar_cmd_fsm_0_n_9;
wire areset_d1;
wire [3:0]\axaddr_incr_reg[3] ;
wire [2:0]axaddr_offset;
wire [0:0]\axaddr_offset_r_reg[3] ;
wire [3:0]\axaddr_offset_r_reg[3]_0 ;
wire cmd_translator_0_n_0;
wire cmd_translator_0_n_10;
wire cmd_translator_0_n_11;
wire cmd_translator_0_n_13;
wire cmd_translator_0_n_2;
wire cmd_translator_0_n_8;
wire cmd_translator_0_n_9;
wire \cnt_read_reg[2]_rep__0 ;
wire incr_next_pending;
wire [11:0]m_axi_araddr;
wire m_axi_arready;
wire m_axi_arvalid;
wire \m_payload_i_reg[0] ;
wire \m_payload_i_reg[0]_0 ;
wire [3:0]\m_payload_i_reg[11] ;
wire \m_payload_i_reg[38] ;
wire [3:0]\m_payload_i_reg[3] ;
wire \m_payload_i_reg[44] ;
wire \m_payload_i_reg[46] ;
wire \m_payload_i_reg[47] ;
wire \m_payload_i_reg[51] ;
wire [35:0]\m_payload_i_reg[64] ;
wire \m_payload_i_reg[6] ;
wire [6:0]\m_payload_i_reg[6]_0 ;
wire [11:0]\r_arid_r_reg[11] ;
wire r_push_r_reg;
wire r_rlast;
wire sel_first;
wire sel_first_i;
wire si_rs_arvalid;
wire \wrap_boundary_axaddr_r_reg[11] ;
wire [1:1]\wrap_cmd_0/wrap_second_len_r ;
wire wrap_next_pending;
wire [0:0]wrap_second_len;
wire [2:0]\wrap_second_len_r_reg[3] ;
wire [2:0]\wrap_second_len_r_reg[3]_0 ;
zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_rd_cmd_fsm ar_cmd_fsm_0
(.D(ar_cmd_fsm_0_n_3),
.E(\wrap_boundary_axaddr_r_reg[11] ),
.Q(Q),
.aclk(aclk),
.areset_d1(areset_d1),
.\axaddr_incr_reg[11] (ar_cmd_fsm_0_n_17),
.axaddr_offset(axaddr_offset),
.\axaddr_offset_r_reg[3] (\axaddr_offset_r_reg[3] ),
.\axaddr_offset_r_reg[3]_0 (\axaddr_offset_r_reg[3]_0 [3]),
.\axaddr_wrap_reg[11] (ar_cmd_fsm_0_n_16),
.\axlen_cnt_reg[1] (ar_cmd_fsm_0_n_0),
.\axlen_cnt_reg[1]_0 ({ar_cmd_fsm_0_n_8,ar_cmd_fsm_0_n_9}),
.\axlen_cnt_reg[1]_1 ({cmd_translator_0_n_9,cmd_translator_0_n_10}),
.\axlen_cnt_reg[4] (cmd_translator_0_n_11),
.\cnt_read_reg[2]_rep__0 (\cnt_read_reg[2]_rep__0 ),
.incr_next_pending(incr_next_pending),
.m_axi_arready(m_axi_arready),
.m_axi_arvalid(m_axi_arvalid),
.\m_payload_i_reg[0] (\m_payload_i_reg[0]_0 ),
.\m_payload_i_reg[0]_0 (\m_payload_i_reg[0] ),
.\m_payload_i_reg[0]_1 (E),
.\m_payload_i_reg[44] (\m_payload_i_reg[44] ),
.\m_payload_i_reg[47] ({\m_payload_i_reg[64] [19],\m_payload_i_reg[64] [17:15]}),
.\m_payload_i_reg[51] (\m_payload_i_reg[51] ),
.\m_payload_i_reg[6] (\m_payload_i_reg[6] ),
.next_pending_r_reg(cmd_translator_0_n_0),
.r_push_r_reg(r_push_r_reg),
.s_axburst_eq0_reg(ar_cmd_fsm_0_n_12),
.s_axburst_eq1_reg(ar_cmd_fsm_0_n_15),
.s_axburst_eq1_reg_0(cmd_translator_0_n_13),
.sel_first_i(sel_first_i),
.sel_first_reg(ar_cmd_fsm_0_n_20),
.sel_first_reg_0(ar_cmd_fsm_0_n_21),
.sel_first_reg_1(cmd_translator_0_n_2),
.sel_first_reg_2(sel_first),
.sel_first_reg_3(cmd_translator_0_n_8),
.si_rs_arvalid(si_rs_arvalid),
.wrap_next_pending(wrap_next_pending),
.wrap_second_len(wrap_second_len),
.\wrap_second_len_r_reg[1] (\wrap_cmd_0/wrap_second_len_r ));
zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_cmd_translator_1 cmd_translator_0
(.CO(CO),
.D({ar_cmd_fsm_0_n_8,ar_cmd_fsm_0_n_9}),
.E(\wrap_boundary_axaddr_r_reg[11] ),
.O(O),
.Q({cmd_translator_0_n_9,cmd_translator_0_n_10}),
.S(S),
.aclk(aclk),
.\axaddr_incr_reg[11] (sel_first),
.\axaddr_incr_reg[3] (\axaddr_incr_reg[3] ),
.\axaddr_offset_r_reg[3] (\axaddr_offset_r_reg[3]_0 ),
.\axaddr_offset_r_reg[3]_0 ({\axaddr_offset_r_reg[3] ,axaddr_offset}),
.incr_next_pending(incr_next_pending),
.m_axi_araddr(m_axi_araddr),
.m_axi_arready(m_axi_arready),
.\m_payload_i_reg[11] (\m_payload_i_reg[11] ),
.\m_payload_i_reg[38] (\m_payload_i_reg[38] ),
.\m_payload_i_reg[39] (ar_cmd_fsm_0_n_12),
.\m_payload_i_reg[39]_0 (ar_cmd_fsm_0_n_15),
.\m_payload_i_reg[3] (\m_payload_i_reg[3] ),
.\m_payload_i_reg[46] (\m_payload_i_reg[46] ),
.\m_payload_i_reg[47] (\m_payload_i_reg[47] ),
.\m_payload_i_reg[51] (\m_payload_i_reg[64] [23:0]),
.\m_payload_i_reg[6] (\m_payload_i_reg[6]_0 ),
.m_valid_i_reg(ar_cmd_fsm_0_n_16),
.next_pending_r_reg(cmd_translator_0_n_0),
.next_pending_r_reg_0(cmd_translator_0_n_11),
.r_rlast(r_rlast),
.sel_first_i(sel_first_i),
.sel_first_reg_0(cmd_translator_0_n_2),
.sel_first_reg_1(cmd_translator_0_n_8),
.sel_first_reg_2(ar_cmd_fsm_0_n_17),
.sel_first_reg_3(ar_cmd_fsm_0_n_20),
.sel_first_reg_4(ar_cmd_fsm_0_n_21),
.si_rs_arvalid(si_rs_arvalid),
.\state_reg[0] (ar_cmd_fsm_0_n_0),
.\state_reg[0]_rep (cmd_translator_0_n_13),
.\state_reg[0]_rep_0 (\m_payload_i_reg[0] ),
.\state_reg[1] (Q),
.\state_reg[1]_rep (\m_payload_i_reg[0]_0 ),
.\state_reg[1]_rep_0 (r_push_r_reg),
.wrap_next_pending(wrap_next_pending),
.\wrap_second_len_r_reg[3] ({\wrap_second_len_r_reg[3] [2:1],\wrap_cmd_0/wrap_second_len_r ,\wrap_second_len_r_reg[3] [0]}),
.\wrap_second_len_r_reg[3]_0 ({D[2:1],wrap_second_len,D[0]}),
.\wrap_second_len_r_reg[3]_1 ({\wrap_second_len_r_reg[3]_0 [2:1],ar_cmd_fsm_0_n_3,\wrap_second_len_r_reg[3]_0 [0]}));
FDRE \s_arid_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [24]),
.Q(\r_arid_r_reg[11] [0]),
.R(1'b0));
FDRE \s_arid_r_reg[10]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [34]),
.Q(\r_arid_r_reg[11] [10]),
.R(1'b0));
FDRE \s_arid_r_reg[11]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [35]),
.Q(\r_arid_r_reg[11] [11]),
.R(1'b0));
FDRE \s_arid_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [25]),
.Q(\r_arid_r_reg[11] [1]),
.R(1'b0));
FDRE \s_arid_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [26]),
.Q(\r_arid_r_reg[11] [2]),
.R(1'b0));
FDRE \s_arid_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [27]),
.Q(\r_arid_r_reg[11] [3]),
.R(1'b0));
FDRE \s_arid_r_reg[4]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [28]),
.Q(\r_arid_r_reg[11] [4]),
.R(1'b0));
FDRE \s_arid_r_reg[5]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [29]),
.Q(\r_arid_r_reg[11] [5]),
.R(1'b0));
FDRE \s_arid_r_reg[6]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [30]),
.Q(\r_arid_r_reg[11] [6]),
.R(1'b0));
FDRE \s_arid_r_reg[7]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [31]),
.Q(\r_arid_r_reg[11] [7]),
.R(1'b0));
FDRE \s_arid_r_reg[8]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [32]),
.Q(\r_arid_r_reg[11] [8]),
.R(1'b0));
FDRE \s_arid_r_reg[9]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [33]),
.Q(\r_arid_r_reg[11] [9]),
.R(1'b0));
endmodule
module zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_aw_channel
(\axaddr_incr_reg[3] ,
sel_first,
Q,
\wrap_boundary_axaddr_r_reg[11] ,
D,
\state_reg[1]_rep ,
\state_reg[1]_rep_0 ,
\wrap_second_len_r_reg[3] ,
\axaddr_offset_r_reg[3] ,
b_push,
\axaddr_offset_r_reg[3]_0 ,
E,
m_axi_awvalid,
m_axi_awaddr,
in,
S,
aclk,
O,
\m_payload_i_reg[47] ,
si_rs_awvalid,
\m_payload_i_reg[64] ,
\m_payload_i_reg[44] ,
\cnt_read_reg[1]_rep__1 ,
\cnt_read_reg[0]_rep__0 ,
m_axi_awready,
CO,
\m_payload_i_reg[35] ,
\m_payload_i_reg[48] ,
areset_d1,
\m_payload_i_reg[46] ,
\m_payload_i_reg[6] ,
\m_payload_i_reg[11] ,
\m_payload_i_reg[38] ,
\wrap_second_len_r_reg[3]_0 ,
\wrap_second_len_r_reg[3]_1 ,
\m_payload_i_reg[6]_0 );
output [3:0]\axaddr_incr_reg[3] ;
output sel_first;
output [1:0]Q;
output \wrap_boundary_axaddr_r_reg[11] ;
output [0:0]D;
output \state_reg[1]_rep ;
output \state_reg[1]_rep_0 ;
output [2:0]\wrap_second_len_r_reg[3] ;
output [0:0]\axaddr_offset_r_reg[3] ;
output b_push;
output [3:0]\axaddr_offset_r_reg[3]_0 ;
output [0:0]E;
output m_axi_awvalid;
output [11:0]m_axi_awaddr;
output [19:0]in;
output [3:0]S;
input aclk;
input [3:0]O;
input \m_payload_i_reg[47] ;
input si_rs_awvalid;
input [35:0]\m_payload_i_reg[64] ;
input \m_payload_i_reg[44] ;
input \cnt_read_reg[1]_rep__1 ;
input \cnt_read_reg[0]_rep__0 ;
input m_axi_awready;
input [0:0]CO;
input [2:0]\m_payload_i_reg[35] ;
input \m_payload_i_reg[48] ;
input areset_d1;
input \m_payload_i_reg[46] ;
input \m_payload_i_reg[6] ;
input [7:0]\m_payload_i_reg[11] ;
input \m_payload_i_reg[38] ;
input [2:0]\wrap_second_len_r_reg[3]_0 ;
input [2:0]\wrap_second_len_r_reg[3]_1 ;
input [6:0]\m_payload_i_reg[6]_0 ;
wire [0:0]CO;
wire [0:0]D;
wire [0:0]E;
wire [3:0]O;
wire [1:0]Q;
wire [3:0]S;
wire aclk;
wire areset_d1;
wire aw_cmd_fsm_0_n_0;
wire aw_cmd_fsm_0_n_13;
wire aw_cmd_fsm_0_n_17;
wire aw_cmd_fsm_0_n_20;
wire aw_cmd_fsm_0_n_21;
wire aw_cmd_fsm_0_n_24;
wire aw_cmd_fsm_0_n_25;
wire aw_cmd_fsm_0_n_3;
wire [3:0]\axaddr_incr_reg[3] ;
wire [0:0]\axaddr_offset_r_reg[3] ;
wire [3:0]\axaddr_offset_r_reg[3]_0 ;
wire b_push;
wire cmd_translator_0_n_0;
wire cmd_translator_0_n_1;
wire cmd_translator_0_n_10;
wire cmd_translator_0_n_11;
wire cmd_translator_0_n_12;
wire cmd_translator_0_n_13;
wire cmd_translator_0_n_14;
wire cmd_translator_0_n_15;
wire cmd_translator_0_n_16;
wire cmd_translator_0_n_17;
wire cmd_translator_0_n_2;
wire cmd_translator_0_n_9;
wire \cnt_read_reg[0]_rep__0 ;
wire \cnt_read_reg[1]_rep__1 ;
wire [19:0]in;
wire incr_next_pending;
wire [11:0]m_axi_awaddr;
wire m_axi_awready;
wire m_axi_awvalid;
wire [7:0]\m_payload_i_reg[11] ;
wire [2:0]\m_payload_i_reg[35] ;
wire \m_payload_i_reg[38] ;
wire \m_payload_i_reg[44] ;
wire \m_payload_i_reg[46] ;
wire \m_payload_i_reg[47] ;
wire \m_payload_i_reg[48] ;
wire [35:0]\m_payload_i_reg[64] ;
wire \m_payload_i_reg[6] ;
wire [6:0]\m_payload_i_reg[6]_0 ;
wire next;
wire [5:0]p_1_in;
wire sel_first;
wire sel_first__0;
wire sel_first_i;
wire si_rs_awvalid;
wire \state_reg[1]_rep ;
wire \state_reg[1]_rep_0 ;
wire \wrap_boundary_axaddr_r_reg[11] ;
wire [1:1]\wrap_cmd_0/wrap_second_len_r ;
wire wrap_next_pending;
wire [2:0]\wrap_second_len_r_reg[3] ;
wire [2:0]\wrap_second_len_r_reg[3]_0 ;
wire [2:0]\wrap_second_len_r_reg[3]_1 ;
zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_wr_cmd_fsm aw_cmd_fsm_0
(.D(aw_cmd_fsm_0_n_3),
.E(\wrap_boundary_axaddr_r_reg[11] ),
.Q(Q),
.aclk(aclk),
.areset_d1(areset_d1),
.\axaddr_incr_reg[11] (aw_cmd_fsm_0_n_21),
.\axaddr_offset_r_reg[3] (\axaddr_offset_r_reg[3] ),
.\axaddr_offset_r_reg[3]_0 (\axaddr_offset_r_reg[3]_0 [3]),
.\axaddr_wrap_reg[0] (aw_cmd_fsm_0_n_20),
.\axlen_cnt_reg[2] (cmd_translator_0_n_16),
.\axlen_cnt_reg[3] (cmd_translator_0_n_15),
.\axlen_cnt_reg[3]_0 (cmd_translator_0_n_17),
.\axlen_cnt_reg[4] (aw_cmd_fsm_0_n_0),
.\axlen_cnt_reg[4]_0 (cmd_translator_0_n_13),
.\axlen_cnt_reg[5] ({p_1_in[5:4],p_1_in[1:0]}),
.\axlen_cnt_reg[5]_0 ({cmd_translator_0_n_9,cmd_translator_0_n_10,cmd_translator_0_n_11,cmd_translator_0_n_12}),
.\cnt_read_reg[0]_rep__0 (\cnt_read_reg[0]_rep__0 ),
.\cnt_read_reg[1]_rep__1 (\cnt_read_reg[1]_rep__1 ),
.incr_next_pending(incr_next_pending),
.m_axi_awready(m_axi_awready),
.m_axi_awvalid(m_axi_awvalid),
.\m_payload_i_reg[0] (b_push),
.\m_payload_i_reg[0]_0 (E),
.\m_payload_i_reg[35] (\m_payload_i_reg[35] ),
.\m_payload_i_reg[44] (\m_payload_i_reg[44] ),
.\m_payload_i_reg[46] (\m_payload_i_reg[46] ),
.\m_payload_i_reg[48] (\m_payload_i_reg[48] ),
.\m_payload_i_reg[49] ({\m_payload_i_reg[64] [21:19],\m_payload_i_reg[64] [17:15]}),
.\m_payload_i_reg[6] (\m_payload_i_reg[6] ),
.next(next),
.next_pending_r_reg(cmd_translator_0_n_0),
.next_pending_r_reg_0(cmd_translator_0_n_1),
.s_axburst_eq0_reg(aw_cmd_fsm_0_n_13),
.s_axburst_eq1_reg(aw_cmd_fsm_0_n_17),
.s_axburst_eq1_reg_0(cmd_translator_0_n_14),
.sel_first__0(sel_first__0),
.sel_first_i(sel_first_i),
.sel_first_reg(aw_cmd_fsm_0_n_24),
.sel_first_reg_0(aw_cmd_fsm_0_n_25),
.sel_first_reg_1(cmd_translator_0_n_2),
.sel_first_reg_2(sel_first),
.si_rs_awvalid(si_rs_awvalid),
.\state_reg[1]_rep_0 (\state_reg[1]_rep ),
.\state_reg[1]_rep_1 (\state_reg[1]_rep_0 ),
.wrap_next_pending(wrap_next_pending),
.\wrap_second_len_r_reg[1] (D),
.\wrap_second_len_r_reg[1]_0 (\wrap_cmd_0/wrap_second_len_r ));
zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_cmd_translator cmd_translator_0
(.CO(CO),
.D({p_1_in[5:4],p_1_in[1:0]}),
.E(\wrap_boundary_axaddr_r_reg[11] ),
.O(O),
.Q({cmd_translator_0_n_9,cmd_translator_0_n_10,cmd_translator_0_n_11,cmd_translator_0_n_12}),
.S(S),
.aclk(aclk),
.\axaddr_incr_reg[11] (sel_first),
.\axaddr_incr_reg[3] (\axaddr_incr_reg[3] ),
.\axaddr_offset_r_reg[3] (\axaddr_offset_r_reg[3]_0 ),
.\axaddr_offset_r_reg[3]_0 ({\axaddr_offset_r_reg[3] ,\m_payload_i_reg[35] }),
.\axlen_cnt_reg[4] (cmd_translator_0_n_17),
.\axlen_cnt_reg[7] (cmd_translator_0_n_13),
.incr_next_pending(incr_next_pending),
.m_axi_awaddr(m_axi_awaddr),
.\m_payload_i_reg[11] (\m_payload_i_reg[11] ),
.\m_payload_i_reg[38] (\m_payload_i_reg[38] ),
.\m_payload_i_reg[39] (aw_cmd_fsm_0_n_13),
.\m_payload_i_reg[39]_0 (aw_cmd_fsm_0_n_17),
.\m_payload_i_reg[47] (\m_payload_i_reg[47] ),
.\m_payload_i_reg[51] ({\m_payload_i_reg[64] [23:22],\m_payload_i_reg[64] [19:0]}),
.\m_payload_i_reg[6] (\m_payload_i_reg[6]_0 ),
.m_valid_i_reg(aw_cmd_fsm_0_n_20),
.next(next),
.next_pending_r_reg(cmd_translator_0_n_0),
.next_pending_r_reg_0(cmd_translator_0_n_1),
.next_pending_r_reg_1(cmd_translator_0_n_15),
.next_pending_r_reg_2(cmd_translator_0_n_16),
.sel_first__0(sel_first__0),
.sel_first_i(sel_first_i),
.sel_first_reg_0(cmd_translator_0_n_2),
.sel_first_reg_1(aw_cmd_fsm_0_n_21),
.sel_first_reg_2(aw_cmd_fsm_0_n_24),
.sel_first_reg_3(aw_cmd_fsm_0_n_25),
.\state_reg[0] (aw_cmd_fsm_0_n_0),
.\state_reg[0]_rep (b_push),
.\state_reg[1] (Q),
.\state_reg[1]_rep (cmd_translator_0_n_14),
.wrap_next_pending(wrap_next_pending),
.\wrap_second_len_r_reg[3] ({\wrap_second_len_r_reg[3] [2:1],\wrap_cmd_0/wrap_second_len_r ,\wrap_second_len_r_reg[3] [0]}),
.\wrap_second_len_r_reg[3]_0 ({\wrap_second_len_r_reg[3]_0 [2:1],D,\wrap_second_len_r_reg[3]_0 [0]}),
.\wrap_second_len_r_reg[3]_1 ({\wrap_second_len_r_reg[3]_1 [2:1],aw_cmd_fsm_0_n_3,\wrap_second_len_r_reg[3]_1 [0]}));
FDRE \s_awid_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [24]),
.Q(in[8]),
.R(1'b0));
FDRE \s_awid_r_reg[10]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [34]),
.Q(in[18]),
.R(1'b0));
FDRE \s_awid_r_reg[11]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [35]),
.Q(in[19]),
.R(1'b0));
FDRE \s_awid_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [25]),
.Q(in[9]),
.R(1'b0));
FDRE \s_awid_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [26]),
.Q(in[10]),
.R(1'b0));
FDRE \s_awid_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [27]),
.Q(in[11]),
.R(1'b0));
FDRE \s_awid_r_reg[4]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [28]),
.Q(in[12]),
.R(1'b0));
FDRE \s_awid_r_reg[5]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [29]),
.Q(in[13]),
.R(1'b0));
FDRE \s_awid_r_reg[6]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [30]),
.Q(in[14]),
.R(1'b0));
FDRE \s_awid_r_reg[7]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [31]),
.Q(in[15]),
.R(1'b0));
FDRE \s_awid_r_reg[8]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [32]),
.Q(in[16]),
.R(1'b0));
FDRE \s_awid_r_reg[9]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [33]),
.Q(in[17]),
.R(1'b0));
FDRE \s_awlen_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [16]),
.Q(in[0]),
.R(1'b0));
FDRE \s_awlen_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [17]),
.Q(in[1]),
.R(1'b0));
FDRE \s_awlen_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [18]),
.Q(in[2]),
.R(1'b0));
FDRE \s_awlen_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [19]),
.Q(in[3]),
.R(1'b0));
FDRE \s_awlen_r_reg[4]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [20]),
.Q(in[4]),
.R(1'b0));
FDRE \s_awlen_r_reg[5]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [21]),
.Q(in[5]),
.R(1'b0));
FDRE \s_awlen_r_reg[6]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [22]),
.Q(in[6]),
.R(1'b0));
FDRE \s_awlen_r_reg[7]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [23]),
.Q(in[7]),
.R(1'b0));
endmodule
module zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_b_channel
(si_rs_bvalid,
\cnt_read_reg[0]_rep__0 ,
\cnt_read_reg[1]_rep__1 ,
m_axi_bready,
out,
\skid_buffer_reg[1] ,
areset_d1,
aclk,
b_push,
si_rs_bready,
m_axi_bvalid,
in,
m_axi_bresp);
output si_rs_bvalid;
output \cnt_read_reg[0]_rep__0 ;
output \cnt_read_reg[1]_rep__1 ;
output m_axi_bready;
output [11:0]out;
output [1:0]\skid_buffer_reg[1] ;
input areset_d1;
input aclk;
input b_push;
input si_rs_bready;
input m_axi_bvalid;
input [19:0]in;
input [1:0]m_axi_bresp;
wire aclk;
wire areset_d1;
wire b_push;
wire bid_fifo_0_n_2;
wire bid_fifo_0_n_3;
wire bid_fifo_0_n_6;
wire \bresp_cnt[7]_i_3_n_0 ;
wire [7:0]bresp_cnt_reg__0;
wire bresp_push;
wire [1:0]cnt_read;
wire \cnt_read_reg[0]_rep__0 ;
wire \cnt_read_reg[1]_rep__1 ;
wire [19:0]in;
wire m_axi_bready;
wire [1:0]m_axi_bresp;
wire m_axi_bvalid;
wire mhandshake;
wire mhandshake_r;
wire [11:0]out;
wire [7:0]p_0_in;
wire s_bresp_acc0;
wire \s_bresp_acc[0]_i_1_n_0 ;
wire \s_bresp_acc[1]_i_1_n_0 ;
wire \s_bresp_acc_reg_n_0_[0] ;
wire \s_bresp_acc_reg_n_0_[1] ;
wire shandshake;
wire shandshake_r;
wire si_rs_bready;
wire si_rs_bvalid;
wire [1:0]\skid_buffer_reg[1] ;
zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_simple_fifo bid_fifo_0
(.D(bid_fifo_0_n_2),
.Q(cnt_read),
.SR(s_bresp_acc0),
.aclk(aclk),
.areset_d1(areset_d1),
.b_push(b_push),
.\bresp_cnt_reg[7] (bresp_cnt_reg__0),
.bvalid_i_reg(bid_fifo_0_n_6),
.bvalid_i_reg_0(si_rs_bvalid),
.\cnt_read_reg[0]_0 (bid_fifo_0_n_3),
.\cnt_read_reg[0]_rep__0_0 (\cnt_read_reg[0]_rep__0 ),
.\cnt_read_reg[1]_rep__1_0 (\cnt_read_reg[1]_rep__1 ),
.in(in),
.mhandshake_r(mhandshake_r),
.out(out),
.sel(bresp_push),
.shandshake_r(shandshake_r),
.si_rs_bready(si_rs_bready));
LUT1 #(
.INIT(2'h1))
\bresp_cnt[0]_i_1
(.I0(bresp_cnt_reg__0[0]),
.O(p_0_in[0]));
(* SOFT_HLUTNM = "soft_lutpair121" *)
LUT2 #(
.INIT(4'h6))
\bresp_cnt[1]_i_1
(.I0(bresp_cnt_reg__0[1]),
.I1(bresp_cnt_reg__0[0]),
.O(p_0_in[1]));
(* SOFT_HLUTNM = "soft_lutpair121" *)
LUT3 #(
.INIT(8'h6A))
\bresp_cnt[2]_i_1
(.I0(bresp_cnt_reg__0[2]),
.I1(bresp_cnt_reg__0[0]),
.I2(bresp_cnt_reg__0[1]),
.O(p_0_in[2]));
(* SOFT_HLUTNM = "soft_lutpair119" *)
LUT4 #(
.INIT(16'h6AAA))
\bresp_cnt[3]_i_1
(.I0(bresp_cnt_reg__0[3]),
.I1(bresp_cnt_reg__0[1]),
.I2(bresp_cnt_reg__0[0]),
.I3(bresp_cnt_reg__0[2]),
.O(p_0_in[3]));
(* SOFT_HLUTNM = "soft_lutpair119" *)
LUT5 #(
.INIT(32'h6AAAAAAA))
\bresp_cnt[4]_i_1
(.I0(bresp_cnt_reg__0[4]),
.I1(bresp_cnt_reg__0[2]),
.I2(bresp_cnt_reg__0[0]),
.I3(bresp_cnt_reg__0[1]),
.I4(bresp_cnt_reg__0[3]),
.O(p_0_in[4]));
LUT6 #(
.INIT(64'h6AAAAAAAAAAAAAAA))
\bresp_cnt[5]_i_1
(.I0(bresp_cnt_reg__0[5]),
.I1(bresp_cnt_reg__0[3]),
.I2(bresp_cnt_reg__0[1]),
.I3(bresp_cnt_reg__0[0]),
.I4(bresp_cnt_reg__0[2]),
.I5(bresp_cnt_reg__0[4]),
.O(p_0_in[5]));
(* SOFT_HLUTNM = "soft_lutpair120" *)
LUT2 #(
.INIT(4'h6))
\bresp_cnt[6]_i_1
(.I0(bresp_cnt_reg__0[6]),
.I1(\bresp_cnt[7]_i_3_n_0 ),
.O(p_0_in[6]));
(* SOFT_HLUTNM = "soft_lutpair120" *)
LUT3 #(
.INIT(8'h6A))
\bresp_cnt[7]_i_2
(.I0(bresp_cnt_reg__0[7]),
.I1(\bresp_cnt[7]_i_3_n_0 ),
.I2(bresp_cnt_reg__0[6]),
.O(p_0_in[7]));
LUT6 #(
.INIT(64'h8000000000000000))
\bresp_cnt[7]_i_3
(.I0(bresp_cnt_reg__0[5]),
.I1(bresp_cnt_reg__0[3]),
.I2(bresp_cnt_reg__0[1]),
.I3(bresp_cnt_reg__0[0]),
.I4(bresp_cnt_reg__0[2]),
.I5(bresp_cnt_reg__0[4]),
.O(\bresp_cnt[7]_i_3_n_0 ));
FDRE \bresp_cnt_reg[0]
(.C(aclk),
.CE(mhandshake_r),
.D(p_0_in[0]),
.Q(bresp_cnt_reg__0[0]),
.R(s_bresp_acc0));
FDRE \bresp_cnt_reg[1]
(.C(aclk),
.CE(mhandshake_r),
.D(p_0_in[1]),
.Q(bresp_cnt_reg__0[1]),
.R(s_bresp_acc0));
FDRE \bresp_cnt_reg[2]
(.C(aclk),
.CE(mhandshake_r),
.D(p_0_in[2]),
.Q(bresp_cnt_reg__0[2]),
.R(s_bresp_acc0));
FDRE \bresp_cnt_reg[3]
(.C(aclk),
.CE(mhandshake_r),
.D(p_0_in[3]),
.Q(bresp_cnt_reg__0[3]),
.R(s_bresp_acc0));
FDRE \bresp_cnt_reg[4]
(.C(aclk),
.CE(mhandshake_r),
.D(p_0_in[4]),
.Q(bresp_cnt_reg__0[4]),
.R(s_bresp_acc0));
FDRE \bresp_cnt_reg[5]
(.C(aclk),
.CE(mhandshake_r),
.D(p_0_in[5]),
.Q(bresp_cnt_reg__0[5]),
.R(s_bresp_acc0));
FDRE \bresp_cnt_reg[6]
(.C(aclk),
.CE(mhandshake_r),
.D(p_0_in[6]),
.Q(bresp_cnt_reg__0[6]),
.R(s_bresp_acc0));
FDRE \bresp_cnt_reg[7]
(.C(aclk),
.CE(mhandshake_r),
.D(p_0_in[7]),
.Q(bresp_cnt_reg__0[7]),
.R(s_bresp_acc0));
zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized0 bresp_fifo_0
(.D(bid_fifo_0_n_2),
.Q(cnt_read),
.aclk(aclk),
.areset_d1(areset_d1),
.\bresp_cnt_reg[3] (bid_fifo_0_n_3),
.in({\s_bresp_acc_reg_n_0_[1] ,\s_bresp_acc_reg_n_0_[0] }),
.m_axi_bready(m_axi_bready),
.m_axi_bvalid(m_axi_bvalid),
.mhandshake(mhandshake),
.mhandshake_r(mhandshake_r),
.sel(bresp_push),
.shandshake_r(shandshake_r),
.\skid_buffer_reg[1] (\skid_buffer_reg[1] ));
FDRE #(
.INIT(1'b0))
bvalid_i_reg
(.C(aclk),
.CE(1'b1),
.D(bid_fifo_0_n_6),
.Q(si_rs_bvalid),
.R(1'b0));
FDRE #(
.INIT(1'b0))
mhandshake_r_reg
(.C(aclk),
.CE(1'b1),
.D(mhandshake),
.Q(mhandshake_r),
.R(areset_d1));
LUT6 #(
.INIT(64'h00000000EACEAAAA))
\s_bresp_acc[0]_i_1
(.I0(\s_bresp_acc_reg_n_0_[0] ),
.I1(m_axi_bresp[0]),
.I2(m_axi_bresp[1]),
.I3(\s_bresp_acc_reg_n_0_[1] ),
.I4(mhandshake),
.I5(s_bresp_acc0),
.O(\s_bresp_acc[0]_i_1_n_0 ));
LUT4 #(
.INIT(16'h00EC))
\s_bresp_acc[1]_i_1
(.I0(m_axi_bresp[1]),
.I1(\s_bresp_acc_reg_n_0_[1] ),
.I2(mhandshake),
.I3(s_bresp_acc0),
.O(\s_bresp_acc[1]_i_1_n_0 ));
FDRE \s_bresp_acc_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\s_bresp_acc[0]_i_1_n_0 ),
.Q(\s_bresp_acc_reg_n_0_[0] ),
.R(1'b0));
FDRE \s_bresp_acc_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\s_bresp_acc[1]_i_1_n_0 ),
.Q(\s_bresp_acc_reg_n_0_[1] ),
.R(1'b0));
LUT2 #(
.INIT(4'h8))
shandshake_r_i_1
(.I0(si_rs_bvalid),
.I1(si_rs_bready),
.O(shandshake));
FDRE #(
.INIT(1'b0))
shandshake_r_reg
(.C(aclk),
.CE(1'b1),
.D(shandshake),
.Q(shandshake_r),
.R(areset_d1));
endmodule
module zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_cmd_translator
(next_pending_r_reg,
next_pending_r_reg_0,
sel_first_reg_0,
\axaddr_incr_reg[3] ,
\axaddr_incr_reg[11] ,
sel_first__0,
Q,
\axlen_cnt_reg[7] ,
\state_reg[1]_rep ,
next_pending_r_reg_1,
next_pending_r_reg_2,
\axlen_cnt_reg[4] ,
m_axi_awaddr,
\axaddr_offset_r_reg[3] ,
\wrap_second_len_r_reg[3] ,
S,
incr_next_pending,
aclk,
wrap_next_pending,
sel_first_i,
\m_payload_i_reg[39] ,
\m_payload_i_reg[39]_0 ,
sel_first_reg_1,
O,
sel_first_reg_2,
sel_first_reg_3,
\state_reg[0] ,
\m_payload_i_reg[47] ,
E,
\m_payload_i_reg[51] ,
CO,
D,
next,
\m_payload_i_reg[11] ,
\m_payload_i_reg[38] ,
m_valid_i_reg,
\axaddr_offset_r_reg[3]_0 ,
\wrap_second_len_r_reg[3]_0 ,
\wrap_second_len_r_reg[3]_1 ,
\m_payload_i_reg[6] ,
\state_reg[1] ,
\state_reg[0]_rep );
output next_pending_r_reg;
output next_pending_r_reg_0;
output sel_first_reg_0;
output [3:0]\axaddr_incr_reg[3] ;
output \axaddr_incr_reg[11] ;
output sel_first__0;
output [3:0]Q;
output \axlen_cnt_reg[7] ;
output \state_reg[1]_rep ;
output next_pending_r_reg_1;
output next_pending_r_reg_2;
output \axlen_cnt_reg[4] ;
output [11:0]m_axi_awaddr;
output [3:0]\axaddr_offset_r_reg[3] ;
output [3:0]\wrap_second_len_r_reg[3] ;
output [3:0]S;
input incr_next_pending;
input aclk;
input wrap_next_pending;
input sel_first_i;
input \m_payload_i_reg[39] ;
input \m_payload_i_reg[39]_0 ;
input sel_first_reg_1;
input [3:0]O;
input sel_first_reg_2;
input sel_first_reg_3;
input \state_reg[0] ;
input \m_payload_i_reg[47] ;
input [0:0]E;
input [21:0]\m_payload_i_reg[51] ;
input [0:0]CO;
input [3:0]D;
input next;
input [7:0]\m_payload_i_reg[11] ;
input \m_payload_i_reg[38] ;
input [0:0]m_valid_i_reg;
input [3:0]\axaddr_offset_r_reg[3]_0 ;
input [3:0]\wrap_second_len_r_reg[3]_0 ;
input [3:0]\wrap_second_len_r_reg[3]_1 ;
input [6:0]\m_payload_i_reg[6] ;
input [1:0]\state_reg[1] ;
input \state_reg[0]_rep ;
wire [0:0]CO;
wire [3:0]D;
wire [0:0]E;
wire [3:0]O;
wire [3:0]Q;
wire [3:0]S;
wire aclk;
wire [11:4]axaddr_incr_reg;
wire [3:0]\axaddr_incr_reg[3] ;
wire axaddr_incr_reg_11__s_net_1;
wire [3:0]\axaddr_offset_r_reg[3] ;
wire [3:0]\axaddr_offset_r_reg[3]_0 ;
wire \axlen_cnt_reg[4] ;
wire \axlen_cnt_reg[7] ;
wire incr_cmd_0_n_21;
wire incr_next_pending;
wire [11:0]m_axi_awaddr;
wire [7:0]\m_payload_i_reg[11] ;
wire \m_payload_i_reg[38] ;
wire \m_payload_i_reg[39] ;
wire \m_payload_i_reg[39]_0 ;
wire \m_payload_i_reg[47] ;
wire [21:0]\m_payload_i_reg[51] ;
wire [6:0]\m_payload_i_reg[6] ;
wire [0:0]m_valid_i_reg;
wire next;
wire next_pending_r_reg;
wire next_pending_r_reg_0;
wire next_pending_r_reg_1;
wire next_pending_r_reg_2;
wire s_axburst_eq0;
wire s_axburst_eq1;
wire sel_first__0;
wire sel_first_i;
wire sel_first_reg_0;
wire sel_first_reg_1;
wire sel_first_reg_2;
wire sel_first_reg_3;
wire \state_reg[0] ;
wire \state_reg[0]_rep ;
wire [1:0]\state_reg[1] ;
wire \state_reg[1]_rep ;
wire wrap_next_pending;
wire [3:0]\wrap_second_len_r_reg[3] ;
wire [3:0]\wrap_second_len_r_reg[3]_0 ;
wire [3:0]\wrap_second_len_r_reg[3]_1 ;
assign \axaddr_incr_reg[11] = axaddr_incr_reg_11__s_net_1;
zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_incr_cmd incr_cmd_0
(.CO(CO),
.D(D),
.E(E),
.O(O),
.Q(Q),
.S(S),
.aclk(aclk),
.axaddr_incr_reg(axaddr_incr_reg),
.\axaddr_incr_reg[11]_0 (axaddr_incr_reg_11__s_net_1),
.\axaddr_incr_reg[3]_0 (\axaddr_incr_reg[3] ),
.\axlen_cnt_reg[4]_0 (\axlen_cnt_reg[4] ),
.\axlen_cnt_reg[7]_0 (\axlen_cnt_reg[7] ),
.incr_next_pending(incr_next_pending),
.\m_axi_awaddr[1] (incr_cmd_0_n_21),
.\m_payload_i_reg[11] (\m_payload_i_reg[11] ),
.\m_payload_i_reg[47] (\m_payload_i_reg[47] ),
.\m_payload_i_reg[51] ({\m_payload_i_reg[51] [21:20],\m_payload_i_reg[51] [18],\m_payload_i_reg[51] [14:12],\m_payload_i_reg[51] [3:0]}),
.m_valid_i_reg(m_valid_i_reg),
.next_pending_r_reg_0(next_pending_r_reg),
.next_pending_r_reg_1(next_pending_r_reg_1),
.sel_first_reg_0(sel_first_reg_1),
.sel_first_reg_1(sel_first_reg_2),
.\state_reg[0] (\state_reg[0] ),
.\state_reg[0]_rep (\state_reg[0]_rep ),
.\state_reg[1] (\state_reg[1] ));
LUT3 #(
.INIT(8'hB8))
\memory_reg[3][0]_srl4_i_2
(.I0(s_axburst_eq1),
.I1(\m_payload_i_reg[51] [15]),
.I2(s_axburst_eq0),
.O(\state_reg[1]_rep ));
FDRE s_axburst_eq0_reg
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[39] ),
.Q(s_axburst_eq0),
.R(1'b0));
FDRE s_axburst_eq1_reg
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[39]_0 ),
.Q(s_axburst_eq1),
.R(1'b0));
FDRE sel_first_reg
(.C(aclk),
.CE(1'b1),
.D(sel_first_i),
.Q(sel_first_reg_0),
.R(1'b0));
zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_wrap_cmd wrap_cmd_0
(.E(E),
.aclk(aclk),
.axaddr_incr_reg(axaddr_incr_reg),
.\axaddr_incr_reg[3] ({\axaddr_incr_reg[3] [3:2],\axaddr_incr_reg[3] [0]}),
.\axaddr_offset_r_reg[3]_0 (\axaddr_offset_r_reg[3] ),
.\axaddr_offset_r_reg[3]_1 (\axaddr_offset_r_reg[3]_0 ),
.m_axi_awaddr(m_axi_awaddr),
.\m_payload_i_reg[38] (\m_payload_i_reg[38] ),
.\m_payload_i_reg[47] ({\m_payload_i_reg[51] [19:15],\m_payload_i_reg[51] [13:0]}),
.\m_payload_i_reg[6] (\m_payload_i_reg[6] ),
.m_valid_i_reg(m_valid_i_reg),
.next(next),
.next_pending_r_reg_0(next_pending_r_reg_0),
.next_pending_r_reg_1(next_pending_r_reg_2),
.sel_first_reg_0(sel_first__0),
.sel_first_reg_1(sel_first_reg_3),
.sel_first_reg_2(incr_cmd_0_n_21),
.wrap_next_pending(wrap_next_pending),
.\wrap_second_len_r_reg[3]_0 (\wrap_second_len_r_reg[3] ),
.\wrap_second_len_r_reg[3]_1 (\wrap_second_len_r_reg[3]_0 ),
.\wrap_second_len_r_reg[3]_2 (\wrap_second_len_r_reg[3]_1 ));
endmodule
(* ORIG_REF_NAME = "axi_protocol_converter_v2_1_13_b2s_cmd_translator" *)
module zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_cmd_translator_1
(next_pending_r_reg,
wrap_next_pending,
sel_first_reg_0,
\axaddr_incr_reg[3] ,
\axaddr_incr_reg[11] ,
sel_first_reg_1,
Q,
next_pending_r_reg_0,
r_rlast,
\state_reg[0]_rep ,
m_axi_araddr,
\axaddr_offset_r_reg[3] ,
\wrap_second_len_r_reg[3] ,
S,
incr_next_pending,
aclk,
sel_first_i,
\m_payload_i_reg[39] ,
\m_payload_i_reg[39]_0 ,
sel_first_reg_2,
O,
sel_first_reg_3,
sel_first_reg_4,
\state_reg[0] ,
\m_payload_i_reg[47] ,
E,
\m_payload_i_reg[51] ,
\state_reg[0]_rep_0 ,
si_rs_arvalid,
\state_reg[1]_rep ,
CO,
\m_payload_i_reg[46] ,
\state_reg[1]_rep_0 ,
\m_payload_i_reg[3] ,
\m_payload_i_reg[11] ,
\m_payload_i_reg[38] ,
m_valid_i_reg,
D,
\axaddr_offset_r_reg[3]_0 ,
\wrap_second_len_r_reg[3]_0 ,
\wrap_second_len_r_reg[3]_1 ,
\m_payload_i_reg[6] ,
\state_reg[1] ,
m_axi_arready);
output next_pending_r_reg;
output wrap_next_pending;
output sel_first_reg_0;
output [3:0]\axaddr_incr_reg[3] ;
output \axaddr_incr_reg[11] ;
output sel_first_reg_1;
output [1:0]Q;
output next_pending_r_reg_0;
output r_rlast;
output \state_reg[0]_rep ;
output [11:0]m_axi_araddr;
output [3:0]\axaddr_offset_r_reg[3] ;
output [3:0]\wrap_second_len_r_reg[3] ;
output [3:0]S;
input incr_next_pending;
input aclk;
input sel_first_i;
input \m_payload_i_reg[39] ;
input \m_payload_i_reg[39]_0 ;
input sel_first_reg_2;
input [3:0]O;
input sel_first_reg_3;
input sel_first_reg_4;
input \state_reg[0] ;
input \m_payload_i_reg[47] ;
input [0:0]E;
input [23:0]\m_payload_i_reg[51] ;
input \state_reg[0]_rep_0 ;
input si_rs_arvalid;
input \state_reg[1]_rep ;
input [0:0]CO;
input \m_payload_i_reg[46] ;
input \state_reg[1]_rep_0 ;
input [3:0]\m_payload_i_reg[3] ;
input [3:0]\m_payload_i_reg[11] ;
input \m_payload_i_reg[38] ;
input [0:0]m_valid_i_reg;
input [1:0]D;
input [3:0]\axaddr_offset_r_reg[3]_0 ;
input [3:0]\wrap_second_len_r_reg[3]_0 ;
input [3:0]\wrap_second_len_r_reg[3]_1 ;
input [6:0]\m_payload_i_reg[6] ;
input [1:0]\state_reg[1] ;
input m_axi_arready;
wire [0:0]CO;
wire [1:0]D;
wire [0:0]E;
wire [3:0]O;
wire [1:0]Q;
wire [3:0]S;
wire aclk;
wire [11:4]axaddr_incr_reg;
wire [3:0]\axaddr_incr_reg[3] ;
wire axaddr_incr_reg_11__s_net_1;
wire [3:0]\axaddr_offset_r_reg[3] ;
wire [3:0]\axaddr_offset_r_reg[3]_0 ;
wire incr_cmd_0_n_16;
wire incr_cmd_0_n_17;
wire incr_next_pending;
wire [11:0]m_axi_araddr;
wire m_axi_arready;
wire [3:0]\m_payload_i_reg[11] ;
wire \m_payload_i_reg[38] ;
wire \m_payload_i_reg[39] ;
wire \m_payload_i_reg[39]_0 ;
wire [3:0]\m_payload_i_reg[3] ;
wire \m_payload_i_reg[46] ;
wire \m_payload_i_reg[47] ;
wire [23:0]\m_payload_i_reg[51] ;
wire [6:0]\m_payload_i_reg[6] ;
wire [0:0]m_valid_i_reg;
wire next_pending_r_reg;
wire next_pending_r_reg_0;
wire r_rlast;
wire s_axburst_eq0;
wire s_axburst_eq1;
wire sel_first_i;
wire sel_first_reg_0;
wire sel_first_reg_1;
wire sel_first_reg_2;
wire sel_first_reg_3;
wire sel_first_reg_4;
wire si_rs_arvalid;
wire \state_reg[0] ;
wire \state_reg[0]_rep ;
wire \state_reg[0]_rep_0 ;
wire [1:0]\state_reg[1] ;
wire \state_reg[1]_rep ;
wire \state_reg[1]_rep_0 ;
wire wrap_next_pending;
wire [3:0]\wrap_second_len_r_reg[3] ;
wire [3:0]\wrap_second_len_r_reg[3]_0 ;
wire [3:0]\wrap_second_len_r_reg[3]_1 ;
assign \axaddr_incr_reg[11] = axaddr_incr_reg_11__s_net_1;
zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_incr_cmd_2 incr_cmd_0
(.CO(CO),
.D(D),
.E(E),
.O(O),
.Q(Q),
.S(S),
.aclk(aclk),
.\axaddr_incr_reg[11]_0 ({axaddr_incr_reg[11:6],axaddr_incr_reg[4]}),
.\axaddr_incr_reg[11]_1 (axaddr_incr_reg_11__s_net_1),
.\axaddr_incr_reg[3]_0 (\axaddr_incr_reg[3] ),
.incr_next_pending(incr_next_pending),
.\m_axi_araddr[2] (incr_cmd_0_n_17),
.\m_axi_araddr[5] (incr_cmd_0_n_16),
.m_axi_arready(m_axi_arready),
.\m_payload_i_reg[11] (\m_payload_i_reg[11] ),
.\m_payload_i_reg[3] (\m_payload_i_reg[3] ),
.\m_payload_i_reg[47] (\m_payload_i_reg[47] ),
.\m_payload_i_reg[51] ({\m_payload_i_reg[51] [23:20],\m_payload_i_reg[51] [18],\m_payload_i_reg[51] [14:12],\m_payload_i_reg[51] [5],\m_payload_i_reg[51] [3:0]}),
.m_valid_i_reg(m_valid_i_reg),
.next_pending_r_reg_0(next_pending_r_reg),
.next_pending_r_reg_1(next_pending_r_reg_0),
.sel_first_reg_0(sel_first_reg_2),
.sel_first_reg_1(sel_first_reg_3),
.\state_reg[0] (\state_reg[0] ),
.\state_reg[1] (\state_reg[1] ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT3 #(
.INIT(8'h1D))
r_rlast_r_i_1
(.I0(s_axburst_eq0),
.I1(\m_payload_i_reg[51] [15]),
.I2(s_axburst_eq1),
.O(r_rlast));
FDRE s_axburst_eq0_reg
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[39] ),
.Q(s_axburst_eq0),
.R(1'b0));
FDRE s_axburst_eq1_reg
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[39]_0 ),
.Q(s_axburst_eq1),
.R(1'b0));
FDRE sel_first_reg
(.C(aclk),
.CE(1'b1),
.D(sel_first_i),
.Q(sel_first_reg_0),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT3 #(
.INIT(8'hB8))
\state[1]_i_3
(.I0(s_axburst_eq1),
.I1(\m_payload_i_reg[51] [15]),
.I2(s_axburst_eq0),
.O(\state_reg[0]_rep ));
zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_wrap_cmd_3 wrap_cmd_0
(.E(E),
.aclk(aclk),
.\axaddr_incr_reg[11] ({axaddr_incr_reg[11:6],axaddr_incr_reg[4]}),
.\axaddr_incr_reg[3] ({\axaddr_incr_reg[3] [3],\axaddr_incr_reg[3] [1:0]}),
.\axaddr_offset_r_reg[3]_0 (\axaddr_offset_r_reg[3] ),
.\axaddr_offset_r_reg[3]_1 (\axaddr_offset_r_reg[3]_0 ),
.m_axi_araddr(m_axi_araddr),
.\m_payload_i_reg[38] (\m_payload_i_reg[38] ),
.\m_payload_i_reg[46] (\m_payload_i_reg[46] ),
.\m_payload_i_reg[47] ({\m_payload_i_reg[51] [19:15],\m_payload_i_reg[51] [13:0]}),
.\m_payload_i_reg[6] (\m_payload_i_reg[6] ),
.m_valid_i_reg(m_valid_i_reg),
.sel_first_reg_0(sel_first_reg_1),
.sel_first_reg_1(sel_first_reg_4),
.sel_first_reg_2(incr_cmd_0_n_16),
.sel_first_reg_3(incr_cmd_0_n_17),
.si_rs_arvalid(si_rs_arvalid),
.\state_reg[0]_rep (\state_reg[0]_rep_0 ),
.\state_reg[1]_rep (\state_reg[1]_rep ),
.\state_reg[1]_rep_0 (\state_reg[1]_rep_0 ),
.wrap_next_pending(wrap_next_pending),
.\wrap_second_len_r_reg[3]_0 (\wrap_second_len_r_reg[3] ),
.\wrap_second_len_r_reg[3]_1 (\wrap_second_len_r_reg[3]_0 ),
.\wrap_second_len_r_reg[3]_2 (\wrap_second_len_r_reg[3]_1 ));
endmodule
module zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_incr_cmd
(next_pending_r_reg_0,
\axaddr_incr_reg[3]_0 ,
axaddr_incr_reg,
\axaddr_incr_reg[11]_0 ,
Q,
\axlen_cnt_reg[7]_0 ,
next_pending_r_reg_1,
\axlen_cnt_reg[4]_0 ,
\m_axi_awaddr[1] ,
S,
incr_next_pending,
aclk,
sel_first_reg_0,
O,
sel_first_reg_1,
\state_reg[0] ,
\m_payload_i_reg[47] ,
CO,
E,
\m_payload_i_reg[51] ,
\m_payload_i_reg[11] ,
m_valid_i_reg,
D,
\state_reg[1] ,
\state_reg[0]_rep );
output next_pending_r_reg_0;
output [3:0]\axaddr_incr_reg[3]_0 ;
output [7:0]axaddr_incr_reg;
output \axaddr_incr_reg[11]_0 ;
output [3:0]Q;
output \axlen_cnt_reg[7]_0 ;
output next_pending_r_reg_1;
output \axlen_cnt_reg[4]_0 ;
output \m_axi_awaddr[1] ;
output [3:0]S;
input incr_next_pending;
input aclk;
input sel_first_reg_0;
input [3:0]O;
input sel_first_reg_1;
input \state_reg[0] ;
input \m_payload_i_reg[47] ;
input [0:0]CO;
input [0:0]E;
input [9:0]\m_payload_i_reg[51] ;
input [7:0]\m_payload_i_reg[11] ;
input [0:0]m_valid_i_reg;
input [3:0]D;
input [1:0]\state_reg[1] ;
input \state_reg[0]_rep ;
wire [0:0]CO;
wire [3:0]D;
wire [0:0]E;
wire [3:0]O;
wire [3:0]Q;
wire [3:0]S;
wire aclk;
wire \axaddr_incr[4]_i_2_n_0 ;
wire \axaddr_incr[4]_i_3_n_0 ;
wire \axaddr_incr[4]_i_4_n_0 ;
wire \axaddr_incr[4]_i_5_n_0 ;
wire \axaddr_incr[8]_i_2_n_0 ;
wire \axaddr_incr[8]_i_3_n_0 ;
wire \axaddr_incr[8]_i_4_n_0 ;
wire \axaddr_incr[8]_i_5_n_0 ;
wire [7:0]axaddr_incr_reg;
wire \axaddr_incr_reg[11]_0 ;
wire [3:0]\axaddr_incr_reg[3]_0 ;
wire \axaddr_incr_reg[4]_i_1_n_0 ;
wire \axaddr_incr_reg[4]_i_1_n_1 ;
wire \axaddr_incr_reg[4]_i_1_n_2 ;
wire \axaddr_incr_reg[4]_i_1_n_3 ;
wire \axaddr_incr_reg[4]_i_1_n_4 ;
wire \axaddr_incr_reg[4]_i_1_n_5 ;
wire \axaddr_incr_reg[4]_i_1_n_6 ;
wire \axaddr_incr_reg[4]_i_1_n_7 ;
wire \axaddr_incr_reg[8]_i_1_n_1 ;
wire \axaddr_incr_reg[8]_i_1_n_2 ;
wire \axaddr_incr_reg[8]_i_1_n_3 ;
wire \axaddr_incr_reg[8]_i_1_n_4 ;
wire \axaddr_incr_reg[8]_i_1_n_5 ;
wire \axaddr_incr_reg[8]_i_1_n_6 ;
wire \axaddr_incr_reg[8]_i_1_n_7 ;
wire \axlen_cnt[3]_i_1_n_0 ;
wire \axlen_cnt[7]_i_4_n_0 ;
wire \axlen_cnt_reg[4]_0 ;
wire \axlen_cnt_reg[7]_0 ;
wire \axlen_cnt_reg_n_0_[2] ;
wire \axlen_cnt_reg_n_0_[3] ;
wire \axlen_cnt_reg_n_0_[6] ;
wire \axlen_cnt_reg_n_0_[7] ;
wire incr_next_pending;
wire \m_axi_awaddr[1] ;
wire [7:0]\m_payload_i_reg[11] ;
wire \m_payload_i_reg[47] ;
wire [9:0]\m_payload_i_reg[51] ;
wire [0:0]m_valid_i_reg;
wire next_pending_r_reg_0;
wire next_pending_r_reg_1;
wire [7:2]p_1_in;
wire sel_first_reg_0;
wire sel_first_reg_1;
wire \state_reg[0] ;
wire \state_reg[0]_rep ;
wire [1:0]\state_reg[1] ;
wire [3:3]\NLW_axaddr_incr_reg[8]_i_1_CO_UNCONNECTED ;
LUT6 #(
.INIT(64'h559AAAAAAAAAAAAA))
\axaddr_incr[0]_i_15
(.I0(\m_payload_i_reg[51] [3]),
.I1(\state_reg[1] [0]),
.I2(\state_reg[1] [1]),
.I3(\state_reg[0]_rep ),
.I4(\m_payload_i_reg[51] [5]),
.I5(\m_payload_i_reg[51] [4]),
.O(S[3]));
LUT6 #(
.INIT(64'h0000AAAA559AAAAA))
\axaddr_incr[0]_i_16
(.I0(\m_payload_i_reg[51] [2]),
.I1(\state_reg[1] [0]),
.I2(\state_reg[1] [1]),
.I3(\state_reg[0]_rep ),
.I4(\m_payload_i_reg[51] [5]),
.I5(\m_payload_i_reg[51] [4]),
.O(S[2]));
LUT6 #(
.INIT(64'h00000000559AAAAA))
\axaddr_incr[0]_i_17
(.I0(\m_payload_i_reg[51] [1]),
.I1(\state_reg[1] [0]),
.I2(\state_reg[1] [1]),
.I3(\state_reg[0]_rep ),
.I4(\m_payload_i_reg[51] [4]),
.I5(\m_payload_i_reg[51] [5]),
.O(S[1]));
LUT6 #(
.INIT(64'h000000000000559A))
\axaddr_incr[0]_i_18
(.I0(\m_payload_i_reg[51] [0]),
.I1(\state_reg[1] [0]),
.I2(\state_reg[1] [1]),
.I3(\state_reg[0]_rep ),
.I4(\m_payload_i_reg[51] [5]),
.I5(\m_payload_i_reg[51] [4]),
.O(S[0]));
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[4]_i_2
(.I0(\m_payload_i_reg[11] [3]),
.I1(\axaddr_incr_reg[11]_0 ),
.I2(axaddr_incr_reg[3]),
.O(\axaddr_incr[4]_i_2_n_0 ));
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[4]_i_3
(.I0(\m_payload_i_reg[11] [2]),
.I1(\axaddr_incr_reg[11]_0 ),
.I2(axaddr_incr_reg[2]),
.O(\axaddr_incr[4]_i_3_n_0 ));
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[4]_i_4
(.I0(\m_payload_i_reg[11] [1]),
.I1(\axaddr_incr_reg[11]_0 ),
.I2(axaddr_incr_reg[1]),
.O(\axaddr_incr[4]_i_4_n_0 ));
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[4]_i_5
(.I0(\m_payload_i_reg[11] [0]),
.I1(\axaddr_incr_reg[11]_0 ),
.I2(axaddr_incr_reg[0]),
.O(\axaddr_incr[4]_i_5_n_0 ));
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[8]_i_2
(.I0(\m_payload_i_reg[11] [7]),
.I1(\axaddr_incr_reg[11]_0 ),
.I2(axaddr_incr_reg[7]),
.O(\axaddr_incr[8]_i_2_n_0 ));
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[8]_i_3
(.I0(\m_payload_i_reg[11] [6]),
.I1(\axaddr_incr_reg[11]_0 ),
.I2(axaddr_incr_reg[6]),
.O(\axaddr_incr[8]_i_3_n_0 ));
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[8]_i_4
(.I0(\m_payload_i_reg[11] [5]),
.I1(\axaddr_incr_reg[11]_0 ),
.I2(axaddr_incr_reg[5]),
.O(\axaddr_incr[8]_i_4_n_0 ));
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[8]_i_5
(.I0(\m_payload_i_reg[11] [4]),
.I1(\axaddr_incr_reg[11]_0 ),
.I2(axaddr_incr_reg[4]),
.O(\axaddr_incr[8]_i_5_n_0 ));
FDRE \axaddr_incr_reg[0]
(.C(aclk),
.CE(sel_first_reg_0),
.D(O[0]),
.Q(\axaddr_incr_reg[3]_0 [0]),
.R(1'b0));
FDRE \axaddr_incr_reg[10]
(.C(aclk),
.CE(sel_first_reg_0),
.D(\axaddr_incr_reg[8]_i_1_n_5 ),
.Q(axaddr_incr_reg[6]),
.R(1'b0));
FDRE \axaddr_incr_reg[11]
(.C(aclk),
.CE(sel_first_reg_0),
.D(\axaddr_incr_reg[8]_i_1_n_4 ),
.Q(axaddr_incr_reg[7]),
.R(1'b0));
FDRE \axaddr_incr_reg[1]
(.C(aclk),
.CE(sel_first_reg_0),
.D(O[1]),
.Q(\axaddr_incr_reg[3]_0 [1]),
.R(1'b0));
FDRE \axaddr_incr_reg[2]
(.C(aclk),
.CE(sel_first_reg_0),
.D(O[2]),
.Q(\axaddr_incr_reg[3]_0 [2]),
.R(1'b0));
FDRE \axaddr_incr_reg[3]
(.C(aclk),
.CE(sel_first_reg_0),
.D(O[3]),
.Q(\axaddr_incr_reg[3]_0 [3]),
.R(1'b0));
FDRE \axaddr_incr_reg[4]
(.C(aclk),
.CE(sel_first_reg_0),
.D(\axaddr_incr_reg[4]_i_1_n_7 ),
.Q(axaddr_incr_reg[0]),
.R(1'b0));
CARRY4 \axaddr_incr_reg[4]_i_1
(.CI(CO),
.CO({\axaddr_incr_reg[4]_i_1_n_0 ,\axaddr_incr_reg[4]_i_1_n_1 ,\axaddr_incr_reg[4]_i_1_n_2 ,\axaddr_incr_reg[4]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\axaddr_incr_reg[4]_i_1_n_4 ,\axaddr_incr_reg[4]_i_1_n_5 ,\axaddr_incr_reg[4]_i_1_n_6 ,\axaddr_incr_reg[4]_i_1_n_7 }),
.S({\axaddr_incr[4]_i_2_n_0 ,\axaddr_incr[4]_i_3_n_0 ,\axaddr_incr[4]_i_4_n_0 ,\axaddr_incr[4]_i_5_n_0 }));
FDRE \axaddr_incr_reg[5]
(.C(aclk),
.CE(sel_first_reg_0),
.D(\axaddr_incr_reg[4]_i_1_n_6 ),
.Q(axaddr_incr_reg[1]),
.R(1'b0));
FDRE \axaddr_incr_reg[6]
(.C(aclk),
.CE(sel_first_reg_0),
.D(\axaddr_incr_reg[4]_i_1_n_5 ),
.Q(axaddr_incr_reg[2]),
.R(1'b0));
FDRE \axaddr_incr_reg[7]
(.C(aclk),
.CE(sel_first_reg_0),
.D(\axaddr_incr_reg[4]_i_1_n_4 ),
.Q(axaddr_incr_reg[3]),
.R(1'b0));
FDRE \axaddr_incr_reg[8]
(.C(aclk),
.CE(sel_first_reg_0),
.D(\axaddr_incr_reg[8]_i_1_n_7 ),
.Q(axaddr_incr_reg[4]),
.R(1'b0));
CARRY4 \axaddr_incr_reg[8]_i_1
(.CI(\axaddr_incr_reg[4]_i_1_n_0 ),
.CO({\NLW_axaddr_incr_reg[8]_i_1_CO_UNCONNECTED [3],\axaddr_incr_reg[8]_i_1_n_1 ,\axaddr_incr_reg[8]_i_1_n_2 ,\axaddr_incr_reg[8]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\axaddr_incr_reg[8]_i_1_n_4 ,\axaddr_incr_reg[8]_i_1_n_5 ,\axaddr_incr_reg[8]_i_1_n_6 ,\axaddr_incr_reg[8]_i_1_n_7 }),
.S({\axaddr_incr[8]_i_2_n_0 ,\axaddr_incr[8]_i_3_n_0 ,\axaddr_incr[8]_i_4_n_0 ,\axaddr_incr[8]_i_5_n_0 }));
FDRE \axaddr_incr_reg[9]
(.C(aclk),
.CE(sel_first_reg_0),
.D(\axaddr_incr_reg[8]_i_1_n_6 ),
.Q(axaddr_incr_reg[5]),
.R(1'b0));
LUT6 #(
.INIT(64'hF8F8F88F88888888))
\axlen_cnt[2]_i_1
(.I0(E),
.I1(\m_payload_i_reg[51] [7]),
.I2(\axlen_cnt_reg_n_0_[2] ),
.I3(Q[0]),
.I4(Q[1]),
.I5(\state_reg[0] ),
.O(p_1_in[2]));
LUT6 #(
.INIT(64'hAAA90000FFFFFFFF))
\axlen_cnt[3]_i_1
(.I0(\axlen_cnt_reg_n_0_[3] ),
.I1(Q[1]),
.I2(Q[0]),
.I3(\axlen_cnt_reg_n_0_[2] ),
.I4(\state_reg[0] ),
.I5(\m_payload_i_reg[47] ),
.O(\axlen_cnt[3]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair113" *)
LUT4 #(
.INIT(16'hFFFE))
\axlen_cnt[4]_i_2
(.I0(\axlen_cnt_reg_n_0_[3] ),
.I1(Q[1]),
.I2(Q[0]),
.I3(\axlen_cnt_reg_n_0_[2] ),
.O(\axlen_cnt_reg[4]_0 ));
LUT6 #(
.INIT(64'hFFFFA900A900A900))
\axlen_cnt[6]_i_1
(.I0(\axlen_cnt_reg_n_0_[6] ),
.I1(\axlen_cnt_reg[7]_0 ),
.I2(Q[3]),
.I3(\state_reg[0] ),
.I4(E),
.I5(\m_payload_i_reg[51] [8]),
.O(p_1_in[6]));
LUT6 #(
.INIT(64'hFFFFA900A900A900))
\axlen_cnt[7]_i_2
(.I0(\axlen_cnt_reg_n_0_[7] ),
.I1(\axlen_cnt_reg[7]_0 ),
.I2(\axlen_cnt[7]_i_4_n_0 ),
.I3(\state_reg[0] ),
.I4(E),
.I5(\m_payload_i_reg[51] [9]),
.O(p_1_in[7]));
(* SOFT_HLUTNM = "soft_lutpair113" *)
LUT5 #(
.INIT(32'hFFFFFFFE))
\axlen_cnt[7]_i_3
(.I0(Q[2]),
.I1(\axlen_cnt_reg_n_0_[2] ),
.I2(Q[0]),
.I3(Q[1]),
.I4(\axlen_cnt_reg_n_0_[3] ),
.O(\axlen_cnt_reg[7]_0 ));
LUT2 #(
.INIT(4'hE))
\axlen_cnt[7]_i_4
(.I0(\axlen_cnt_reg_n_0_[6] ),
.I1(Q[3]),
.O(\axlen_cnt[7]_i_4_n_0 ));
FDRE \axlen_cnt_reg[0]
(.C(aclk),
.CE(m_valid_i_reg),
.D(D[0]),
.Q(Q[0]),
.R(1'b0));
FDRE \axlen_cnt_reg[1]
(.C(aclk),
.CE(m_valid_i_reg),
.D(D[1]),
.Q(Q[1]),
.R(1'b0));
FDRE \axlen_cnt_reg[2]
(.C(aclk),
.CE(m_valid_i_reg),
.D(p_1_in[2]),
.Q(\axlen_cnt_reg_n_0_[2] ),
.R(1'b0));
FDRE \axlen_cnt_reg[3]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[3]_i_1_n_0 ),
.Q(\axlen_cnt_reg_n_0_[3] ),
.R(1'b0));
FDRE \axlen_cnt_reg[4]
(.C(aclk),
.CE(m_valid_i_reg),
.D(D[2]),
.Q(Q[2]),
.R(1'b0));
FDRE \axlen_cnt_reg[5]
(.C(aclk),
.CE(m_valid_i_reg),
.D(D[3]),
.Q(Q[3]),
.R(1'b0));
FDRE \axlen_cnt_reg[6]
(.C(aclk),
.CE(m_valid_i_reg),
.D(p_1_in[6]),
.Q(\axlen_cnt_reg_n_0_[6] ),
.R(1'b0));
FDRE \axlen_cnt_reg[7]
(.C(aclk),
.CE(m_valid_i_reg),
.D(p_1_in[7]),
.Q(\axlen_cnt_reg_n_0_[7] ),
.R(1'b0));
LUT4 #(
.INIT(16'hEF40))
\m_axi_awaddr[1]_INST_0_i_1
(.I0(\axaddr_incr_reg[11]_0 ),
.I1(\axaddr_incr_reg[3]_0 [1]),
.I2(\m_payload_i_reg[51] [6]),
.I3(\m_payload_i_reg[51] [1]),
.O(\m_axi_awaddr[1] ));
LUT6 #(
.INIT(64'h0000000000000001))
next_pending_r_i_3
(.I0(\axlen_cnt_reg_n_0_[3] ),
.I1(\axlen_cnt_reg_n_0_[7] ),
.I2(Q[2]),
.I3(\axlen_cnt_reg_n_0_[2] ),
.I4(Q[1]),
.I5(\axlen_cnt[7]_i_4_n_0 ),
.O(next_pending_r_reg_1));
FDRE next_pending_r_reg
(.C(aclk),
.CE(1'b1),
.D(incr_next_pending),
.Q(next_pending_r_reg_0),
.R(1'b0));
FDRE sel_first_reg
(.C(aclk),
.CE(1'b1),
.D(sel_first_reg_1),
.Q(\axaddr_incr_reg[11]_0 ),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "axi_protocol_converter_v2_1_13_b2s_incr_cmd" *)
module zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_incr_cmd_2
(next_pending_r_reg_0,
\axaddr_incr_reg[3]_0 ,
\axaddr_incr_reg[11]_0 ,
\axaddr_incr_reg[11]_1 ,
Q,
next_pending_r_reg_1,
\m_axi_araddr[5] ,
\m_axi_araddr[2] ,
S,
incr_next_pending,
aclk,
sel_first_reg_0,
O,
sel_first_reg_1,
\state_reg[0] ,
\m_payload_i_reg[47] ,
CO,
E,
\m_payload_i_reg[51] ,
\m_payload_i_reg[3] ,
\m_payload_i_reg[11] ,
m_valid_i_reg,
D,
\state_reg[1] ,
m_axi_arready);
output next_pending_r_reg_0;
output [3:0]\axaddr_incr_reg[3]_0 ;
output [6:0]\axaddr_incr_reg[11]_0 ;
output \axaddr_incr_reg[11]_1 ;
output [1:0]Q;
output next_pending_r_reg_1;
output \m_axi_araddr[5] ;
output \m_axi_araddr[2] ;
output [3:0]S;
input incr_next_pending;
input aclk;
input sel_first_reg_0;
input [3:0]O;
input sel_first_reg_1;
input \state_reg[0] ;
input \m_payload_i_reg[47] ;
input [0:0]CO;
input [0:0]E;
input [12:0]\m_payload_i_reg[51] ;
input [3:0]\m_payload_i_reg[3] ;
input [3:0]\m_payload_i_reg[11] ;
input [0:0]m_valid_i_reg;
input [1:0]D;
input [1:0]\state_reg[1] ;
input m_axi_arready;
wire [0:0]CO;
wire [1:0]D;
wire [0:0]E;
wire [3:0]O;
wire [1:0]Q;
wire [3:0]S;
wire aclk;
wire \axaddr_incr[4]_i_2__0_n_0 ;
wire \axaddr_incr[4]_i_3__0_n_0 ;
wire \axaddr_incr[4]_i_4__0_n_0 ;
wire \axaddr_incr[4]_i_5__0_n_0 ;
wire \axaddr_incr[8]_i_2__0_n_0 ;
wire \axaddr_incr[8]_i_3__0_n_0 ;
wire \axaddr_incr[8]_i_4__0_n_0 ;
wire \axaddr_incr[8]_i_5__0_n_0 ;
wire [5:5]axaddr_incr_reg;
wire [6:0]\axaddr_incr_reg[11]_0 ;
wire \axaddr_incr_reg[11]_1 ;
wire [3:0]\axaddr_incr_reg[3]_0 ;
wire \axaddr_incr_reg[4]_i_1__0_n_0 ;
wire \axaddr_incr_reg[4]_i_1__0_n_1 ;
wire \axaddr_incr_reg[4]_i_1__0_n_2 ;
wire \axaddr_incr_reg[4]_i_1__0_n_3 ;
wire \axaddr_incr_reg[4]_i_1__0_n_4 ;
wire \axaddr_incr_reg[4]_i_1__0_n_5 ;
wire \axaddr_incr_reg[4]_i_1__0_n_6 ;
wire \axaddr_incr_reg[4]_i_1__0_n_7 ;
wire \axaddr_incr_reg[8]_i_1__0_n_1 ;
wire \axaddr_incr_reg[8]_i_1__0_n_2 ;
wire \axaddr_incr_reg[8]_i_1__0_n_3 ;
wire \axaddr_incr_reg[8]_i_1__0_n_4 ;
wire \axaddr_incr_reg[8]_i_1__0_n_5 ;
wire \axaddr_incr_reg[8]_i_1__0_n_6 ;
wire \axaddr_incr_reg[8]_i_1__0_n_7 ;
wire \axlen_cnt[2]_i_1__1_n_0 ;
wire \axlen_cnt[3]_i_1__1_n_0 ;
wire \axlen_cnt[4]_i_1__0_n_0 ;
wire \axlen_cnt[4]_i_2__0_n_0 ;
wire \axlen_cnt[5]_i_1__0_n_0 ;
wire \axlen_cnt[5]_i_2_n_0 ;
wire \axlen_cnt[6]_i_1__0_n_0 ;
wire \axlen_cnt[7]_i_2__0_n_0 ;
wire \axlen_cnt[7]_i_3__0_n_0 ;
wire \axlen_cnt_reg_n_0_[2] ;
wire \axlen_cnt_reg_n_0_[3] ;
wire \axlen_cnt_reg_n_0_[4] ;
wire \axlen_cnt_reg_n_0_[5] ;
wire \axlen_cnt_reg_n_0_[6] ;
wire \axlen_cnt_reg_n_0_[7] ;
wire incr_next_pending;
wire \m_axi_araddr[2] ;
wire \m_axi_araddr[5] ;
wire m_axi_arready;
wire [3:0]\m_payload_i_reg[11] ;
wire [3:0]\m_payload_i_reg[3] ;
wire \m_payload_i_reg[47] ;
wire [12:0]\m_payload_i_reg[51] ;
wire [0:0]m_valid_i_reg;
wire next_pending_r_i_4__0_n_0;
wire next_pending_r_reg_0;
wire next_pending_r_reg_1;
wire sel_first_reg_0;
wire sel_first_reg_1;
wire \state_reg[0] ;
wire [1:0]\state_reg[1] ;
wire [3:3]\NLW_axaddr_incr_reg[8]_i_1__0_CO_UNCONNECTED ;
LUT6 #(
.INIT(64'hAA6AAAAAAAAAAAAA))
\axaddr_incr[0]_i_15
(.I0(\m_payload_i_reg[51] [3]),
.I1(\m_payload_i_reg[51] [6]),
.I2(\m_payload_i_reg[51] [5]),
.I3(\state_reg[1] [1]),
.I4(\state_reg[1] [0]),
.I5(m_axi_arready),
.O(S[3]));
LUT6 #(
.INIT(64'h2A262A2A2A2A2A2A))
\axaddr_incr[0]_i_16
(.I0(\m_payload_i_reg[51] [2]),
.I1(\m_payload_i_reg[51] [6]),
.I2(\m_payload_i_reg[51] [5]),
.I3(\state_reg[1] [1]),
.I4(\state_reg[1] [0]),
.I5(m_axi_arready),
.O(S[2]));
LUT6 #(
.INIT(64'h0A060A0A0A0A0A0A))
\axaddr_incr[0]_i_17
(.I0(\m_payload_i_reg[51] [1]),
.I1(\m_payload_i_reg[51] [5]),
.I2(\m_payload_i_reg[51] [6]),
.I3(\state_reg[1] [1]),
.I4(\state_reg[1] [0]),
.I5(m_axi_arready),
.O(S[1]));
LUT6 #(
.INIT(64'h0201020202020202))
\axaddr_incr[0]_i_18
(.I0(\m_payload_i_reg[51] [0]),
.I1(\m_payload_i_reg[51] [6]),
.I2(\m_payload_i_reg[51] [5]),
.I3(\state_reg[1] [1]),
.I4(\state_reg[1] [0]),
.I5(m_axi_arready),
.O(S[0]));
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[4]_i_2__0
(.I0(\m_payload_i_reg[3] [3]),
.I1(\axaddr_incr_reg[11]_1 ),
.I2(\axaddr_incr_reg[11]_0 [2]),
.O(\axaddr_incr[4]_i_2__0_n_0 ));
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[4]_i_3__0
(.I0(\m_payload_i_reg[3] [2]),
.I1(\axaddr_incr_reg[11]_1 ),
.I2(\axaddr_incr_reg[11]_0 [1]),
.O(\axaddr_incr[4]_i_3__0_n_0 ));
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[4]_i_4__0
(.I0(\m_payload_i_reg[3] [1]),
.I1(\axaddr_incr_reg[11]_1 ),
.I2(axaddr_incr_reg),
.O(\axaddr_incr[4]_i_4__0_n_0 ));
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[4]_i_5__0
(.I0(\m_payload_i_reg[3] [0]),
.I1(\axaddr_incr_reg[11]_1 ),
.I2(\axaddr_incr_reg[11]_0 [0]),
.O(\axaddr_incr[4]_i_5__0_n_0 ));
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[8]_i_2__0
(.I0(\m_payload_i_reg[11] [3]),
.I1(\axaddr_incr_reg[11]_1 ),
.I2(\axaddr_incr_reg[11]_0 [6]),
.O(\axaddr_incr[8]_i_2__0_n_0 ));
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[8]_i_3__0
(.I0(\m_payload_i_reg[11] [2]),
.I1(\axaddr_incr_reg[11]_1 ),
.I2(\axaddr_incr_reg[11]_0 [5]),
.O(\axaddr_incr[8]_i_3__0_n_0 ));
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[8]_i_4__0
(.I0(\m_payload_i_reg[11] [1]),
.I1(\axaddr_incr_reg[11]_1 ),
.I2(\axaddr_incr_reg[11]_0 [4]),
.O(\axaddr_incr[8]_i_4__0_n_0 ));
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[8]_i_5__0
(.I0(\m_payload_i_reg[11] [0]),
.I1(\axaddr_incr_reg[11]_1 ),
.I2(\axaddr_incr_reg[11]_0 [3]),
.O(\axaddr_incr[8]_i_5__0_n_0 ));
FDRE \axaddr_incr_reg[0]
(.C(aclk),
.CE(sel_first_reg_0),
.D(O[0]),
.Q(\axaddr_incr_reg[3]_0 [0]),
.R(1'b0));
FDRE \axaddr_incr_reg[10]
(.C(aclk),
.CE(sel_first_reg_0),
.D(\axaddr_incr_reg[8]_i_1__0_n_5 ),
.Q(\axaddr_incr_reg[11]_0 [5]),
.R(1'b0));
FDRE \axaddr_incr_reg[11]
(.C(aclk),
.CE(sel_first_reg_0),
.D(\axaddr_incr_reg[8]_i_1__0_n_4 ),
.Q(\axaddr_incr_reg[11]_0 [6]),
.R(1'b0));
FDRE \axaddr_incr_reg[1]
(.C(aclk),
.CE(sel_first_reg_0),
.D(O[1]),
.Q(\axaddr_incr_reg[3]_0 [1]),
.R(1'b0));
FDRE \axaddr_incr_reg[2]
(.C(aclk),
.CE(sel_first_reg_0),
.D(O[2]),
.Q(\axaddr_incr_reg[3]_0 [2]),
.R(1'b0));
FDRE \axaddr_incr_reg[3]
(.C(aclk),
.CE(sel_first_reg_0),
.D(O[3]),
.Q(\axaddr_incr_reg[3]_0 [3]),
.R(1'b0));
FDRE \axaddr_incr_reg[4]
(.C(aclk),
.CE(sel_first_reg_0),
.D(\axaddr_incr_reg[4]_i_1__0_n_7 ),
.Q(\axaddr_incr_reg[11]_0 [0]),
.R(1'b0));
CARRY4 \axaddr_incr_reg[4]_i_1__0
(.CI(CO),
.CO({\axaddr_incr_reg[4]_i_1__0_n_0 ,\axaddr_incr_reg[4]_i_1__0_n_1 ,\axaddr_incr_reg[4]_i_1__0_n_2 ,\axaddr_incr_reg[4]_i_1__0_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\axaddr_incr_reg[4]_i_1__0_n_4 ,\axaddr_incr_reg[4]_i_1__0_n_5 ,\axaddr_incr_reg[4]_i_1__0_n_6 ,\axaddr_incr_reg[4]_i_1__0_n_7 }),
.S({\axaddr_incr[4]_i_2__0_n_0 ,\axaddr_incr[4]_i_3__0_n_0 ,\axaddr_incr[4]_i_4__0_n_0 ,\axaddr_incr[4]_i_5__0_n_0 }));
FDRE \axaddr_incr_reg[5]
(.C(aclk),
.CE(sel_first_reg_0),
.D(\axaddr_incr_reg[4]_i_1__0_n_6 ),
.Q(axaddr_incr_reg),
.R(1'b0));
FDRE \axaddr_incr_reg[6]
(.C(aclk),
.CE(sel_first_reg_0),
.D(\axaddr_incr_reg[4]_i_1__0_n_5 ),
.Q(\axaddr_incr_reg[11]_0 [1]),
.R(1'b0));
FDRE \axaddr_incr_reg[7]
(.C(aclk),
.CE(sel_first_reg_0),
.D(\axaddr_incr_reg[4]_i_1__0_n_4 ),
.Q(\axaddr_incr_reg[11]_0 [2]),
.R(1'b0));
FDRE \axaddr_incr_reg[8]
(.C(aclk),
.CE(sel_first_reg_0),
.D(\axaddr_incr_reg[8]_i_1__0_n_7 ),
.Q(\axaddr_incr_reg[11]_0 [3]),
.R(1'b0));
CARRY4 \axaddr_incr_reg[8]_i_1__0
(.CI(\axaddr_incr_reg[4]_i_1__0_n_0 ),
.CO({\NLW_axaddr_incr_reg[8]_i_1__0_CO_UNCONNECTED [3],\axaddr_incr_reg[8]_i_1__0_n_1 ,\axaddr_incr_reg[8]_i_1__0_n_2 ,\axaddr_incr_reg[8]_i_1__0_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\axaddr_incr_reg[8]_i_1__0_n_4 ,\axaddr_incr_reg[8]_i_1__0_n_5 ,\axaddr_incr_reg[8]_i_1__0_n_6 ,\axaddr_incr_reg[8]_i_1__0_n_7 }),
.S({\axaddr_incr[8]_i_2__0_n_0 ,\axaddr_incr[8]_i_3__0_n_0 ,\axaddr_incr[8]_i_4__0_n_0 ,\axaddr_incr[8]_i_5__0_n_0 }));
FDRE \axaddr_incr_reg[9]
(.C(aclk),
.CE(sel_first_reg_0),
.D(\axaddr_incr_reg[8]_i_1__0_n_6 ),
.Q(\axaddr_incr_reg[11]_0 [4]),
.R(1'b0));
LUT6 #(
.INIT(64'hF8F8F88F88888888))
\axlen_cnt[2]_i_1__1
(.I0(E),
.I1(\m_payload_i_reg[51] [8]),
.I2(\axlen_cnt_reg_n_0_[2] ),
.I3(Q[0]),
.I4(Q[1]),
.I5(\state_reg[0] ),
.O(\axlen_cnt[2]_i_1__1_n_0 ));
LUT6 #(
.INIT(64'hAAA90000FFFFFFFF))
\axlen_cnt[3]_i_1__1
(.I0(\axlen_cnt_reg_n_0_[3] ),
.I1(Q[1]),
.I2(Q[0]),
.I3(\axlen_cnt_reg_n_0_[2] ),
.I4(\state_reg[0] ),
.I5(\m_payload_i_reg[47] ),
.O(\axlen_cnt[3]_i_1__1_n_0 ));
LUT5 #(
.INIT(32'hFF909090))
\axlen_cnt[4]_i_1__0
(.I0(\axlen_cnt_reg_n_0_[4] ),
.I1(\axlen_cnt[4]_i_2__0_n_0 ),
.I2(\state_reg[0] ),
.I3(E),
.I4(\m_payload_i_reg[51] [9]),
.O(\axlen_cnt[4]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT4 #(
.INIT(16'hFFFE))
\axlen_cnt[4]_i_2__0
(.I0(\axlen_cnt_reg_n_0_[3] ),
.I1(Q[1]),
.I2(Q[0]),
.I3(\axlen_cnt_reg_n_0_[2] ),
.O(\axlen_cnt[4]_i_2__0_n_0 ));
LUT5 #(
.INIT(32'hFF909090))
\axlen_cnt[5]_i_1__0
(.I0(\axlen_cnt_reg_n_0_[5] ),
.I1(\axlen_cnt[5]_i_2_n_0 ),
.I2(\state_reg[0] ),
.I3(E),
.I4(\m_payload_i_reg[51] [10]),
.O(\axlen_cnt[5]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT5 #(
.INIT(32'hFFFFFFFE))
\axlen_cnt[5]_i_2
(.I0(\axlen_cnt_reg_n_0_[4] ),
.I1(\axlen_cnt_reg_n_0_[2] ),
.I2(Q[0]),
.I3(Q[1]),
.I4(\axlen_cnt_reg_n_0_[3] ),
.O(\axlen_cnt[5]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFF909090))
\axlen_cnt[6]_i_1__0
(.I0(\axlen_cnt_reg_n_0_[6] ),
.I1(\axlen_cnt[7]_i_3__0_n_0 ),
.I2(\state_reg[0] ),
.I3(E),
.I4(\m_payload_i_reg[51] [11]),
.O(\axlen_cnt[6]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'hF8F8F88F88888888))
\axlen_cnt[7]_i_2__0
(.I0(E),
.I1(\m_payload_i_reg[51] [12]),
.I2(\axlen_cnt_reg_n_0_[7] ),
.I3(\axlen_cnt[7]_i_3__0_n_0 ),
.I4(\axlen_cnt_reg_n_0_[6] ),
.I5(\state_reg[0] ),
.O(\axlen_cnt[7]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\axlen_cnt[7]_i_3__0
(.I0(\axlen_cnt_reg_n_0_[5] ),
.I1(\axlen_cnt_reg_n_0_[3] ),
.I2(Q[1]),
.I3(Q[0]),
.I4(\axlen_cnt_reg_n_0_[2] ),
.I5(\axlen_cnt_reg_n_0_[4] ),
.O(\axlen_cnt[7]_i_3__0_n_0 ));
FDRE \axlen_cnt_reg[0]
(.C(aclk),
.CE(m_valid_i_reg),
.D(D[0]),
.Q(Q[0]),
.R(1'b0));
FDRE \axlen_cnt_reg[1]
(.C(aclk),
.CE(m_valid_i_reg),
.D(D[1]),
.Q(Q[1]),
.R(1'b0));
FDRE \axlen_cnt_reg[2]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[2]_i_1__1_n_0 ),
.Q(\axlen_cnt_reg_n_0_[2] ),
.R(1'b0));
FDRE \axlen_cnt_reg[3]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[3]_i_1__1_n_0 ),
.Q(\axlen_cnt_reg_n_0_[3] ),
.R(1'b0));
FDRE \axlen_cnt_reg[4]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[4]_i_1__0_n_0 ),
.Q(\axlen_cnt_reg_n_0_[4] ),
.R(1'b0));
FDRE \axlen_cnt_reg[5]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[5]_i_1__0_n_0 ),
.Q(\axlen_cnt_reg_n_0_[5] ),
.R(1'b0));
FDRE \axlen_cnt_reg[6]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[6]_i_1__0_n_0 ),
.Q(\axlen_cnt_reg_n_0_[6] ),
.R(1'b0));
FDRE \axlen_cnt_reg[7]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[7]_i_2__0_n_0 ),
.Q(\axlen_cnt_reg_n_0_[7] ),
.R(1'b0));
LUT4 #(
.INIT(16'hEF40))
\m_axi_araddr[2]_INST_0_i_1
(.I0(\axaddr_incr_reg[11]_1 ),
.I1(\axaddr_incr_reg[3]_0 [2]),
.I2(\m_payload_i_reg[51] [7]),
.I3(\m_payload_i_reg[51] [2]),
.O(\m_axi_araddr[2] ));
LUT4 #(
.INIT(16'hEF40))
\m_axi_araddr[5]_INST_0_i_1
(.I0(\axaddr_incr_reg[11]_1 ),
.I1(axaddr_incr_reg),
.I2(\m_payload_i_reg[51] [7]),
.I3(\m_payload_i_reg[51] [4]),
.O(\m_axi_araddr[5] ));
LUT4 #(
.INIT(16'h0001))
next_pending_r_i_3__1
(.I0(\axlen_cnt_reg_n_0_[4] ),
.I1(\axlen_cnt_reg_n_0_[5] ),
.I2(\axlen_cnt_reg_n_0_[3] ),
.I3(next_pending_r_i_4__0_n_0),
.O(next_pending_r_reg_1));
LUT4 #(
.INIT(16'hFFFE))
next_pending_r_i_4__0
(.I0(Q[1]),
.I1(\axlen_cnt_reg_n_0_[2] ),
.I2(\axlen_cnt_reg_n_0_[6] ),
.I3(\axlen_cnt_reg_n_0_[7] ),
.O(next_pending_r_i_4__0_n_0));
FDRE next_pending_r_reg
(.C(aclk),
.CE(1'b1),
.D(incr_next_pending),
.Q(next_pending_r_reg_0),
.R(1'b0));
FDRE sel_first_reg
(.C(aclk),
.CE(1'b1),
.D(sel_first_reg_1),
.Q(\axaddr_incr_reg[11]_1 ),
.R(1'b0));
endmodule
module zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_r_channel
(\state_reg[1]_rep ,
m_axi_rready,
m_valid_i_reg,
out,
\skid_buffer_reg[46] ,
\state_reg[1]_rep_0 ,
aclk,
r_rlast,
s_ready_i_reg,
si_rs_rready,
m_axi_rvalid,
in,
areset_d1,
D);
output \state_reg[1]_rep ;
output m_axi_rready;
output m_valid_i_reg;
output [33:0]out;
output [12:0]\skid_buffer_reg[46] ;
input \state_reg[1]_rep_0 ;
input aclk;
input r_rlast;
input s_ready_i_reg;
input si_rs_rready;
input m_axi_rvalid;
input [33:0]in;
input areset_d1;
input [11:0]D;
wire [11:0]D;
wire aclk;
wire areset_d1;
wire [33:0]in;
wire m_axi_rready;
wire m_axi_rvalid;
wire m_valid_i_reg;
wire [33:0]out;
wire r_push_r;
wire r_rlast;
wire rd_data_fifo_0_n_0;
wire rd_data_fifo_0_n_2;
wire rd_data_fifo_0_n_3;
wire rd_data_fifo_0_n_5;
wire s_ready_i_reg;
wire si_rs_rready;
wire [12:0]\skid_buffer_reg[46] ;
wire \state_reg[1]_rep ;
wire \state_reg[1]_rep_0 ;
wire [12:0]trans_in;
wire transaction_fifo_0_n_1;
wire wr_en0;
FDRE \r_arid_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(D[0]),
.Q(trans_in[1]),
.R(1'b0));
FDRE \r_arid_r_reg[10]
(.C(aclk),
.CE(1'b1),
.D(D[10]),
.Q(trans_in[11]),
.R(1'b0));
FDRE \r_arid_r_reg[11]
(.C(aclk),
.CE(1'b1),
.D(D[11]),
.Q(trans_in[12]),
.R(1'b0));
FDRE \r_arid_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(D[1]),
.Q(trans_in[2]),
.R(1'b0));
FDRE \r_arid_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(D[2]),
.Q(trans_in[3]),
.R(1'b0));
FDRE \r_arid_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(D[3]),
.Q(trans_in[4]),
.R(1'b0));
FDRE \r_arid_r_reg[4]
(.C(aclk),
.CE(1'b1),
.D(D[4]),
.Q(trans_in[5]),
.R(1'b0));
FDRE \r_arid_r_reg[5]
(.C(aclk),
.CE(1'b1),
.D(D[5]),
.Q(trans_in[6]),
.R(1'b0));
FDRE \r_arid_r_reg[6]
(.C(aclk),
.CE(1'b1),
.D(D[6]),
.Q(trans_in[7]),
.R(1'b0));
FDRE \r_arid_r_reg[7]
(.C(aclk),
.CE(1'b1),
.D(D[7]),
.Q(trans_in[8]),
.R(1'b0));
FDRE \r_arid_r_reg[8]
(.C(aclk),
.CE(1'b1),
.D(D[8]),
.Q(trans_in[9]),
.R(1'b0));
FDRE \r_arid_r_reg[9]
(.C(aclk),
.CE(1'b1),
.D(D[9]),
.Q(trans_in[10]),
.R(1'b0));
FDRE r_push_r_reg
(.C(aclk),
.CE(1'b1),
.D(\state_reg[1]_rep_0 ),
.Q(r_push_r),
.R(1'b0));
FDRE r_rlast_r_reg
(.C(aclk),
.CE(1'b1),
.D(r_rlast),
.Q(trans_in[0]),
.R(1'b0));
zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized1 rd_data_fifo_0
(.aclk(aclk),
.areset_d1(areset_d1),
.\cnt_read_reg[3]_rep__2_0 (rd_data_fifo_0_n_0),
.\cnt_read_reg[4]_rep__0_0 (m_valid_i_reg),
.\cnt_read_reg[4]_rep__2_0 (rd_data_fifo_0_n_2),
.\cnt_read_reg[4]_rep__2_1 (rd_data_fifo_0_n_3),
.in(in),
.m_axi_rready(m_axi_rready),
.m_axi_rvalid(m_axi_rvalid),
.out(out),
.s_ready_i_reg(s_ready_i_reg),
.s_ready_i_reg_0(transaction_fifo_0_n_1),
.si_rs_rready(si_rs_rready),
.\state_reg[1]_rep (rd_data_fifo_0_n_5),
.wr_en0(wr_en0));
zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized2 transaction_fifo_0
(.aclk(aclk),
.areset_d1(areset_d1),
.\cnt_read_reg[0]_rep__2 (rd_data_fifo_0_n_5),
.\cnt_read_reg[0]_rep__2_0 (rd_data_fifo_0_n_3),
.\cnt_read_reg[3]_rep__2 (rd_data_fifo_0_n_0),
.\cnt_read_reg[4]_rep__2 (transaction_fifo_0_n_1),
.\cnt_read_reg[4]_rep__2_0 (rd_data_fifo_0_n_2),
.in(trans_in),
.m_valid_i_reg(m_valid_i_reg),
.r_push_r(r_push_r),
.s_ready_i_reg(s_ready_i_reg),
.si_rs_rready(si_rs_rready),
.\skid_buffer_reg[46] (\skid_buffer_reg[46] ),
.\state_reg[1]_rep (\state_reg[1]_rep ),
.wr_en0(wr_en0));
endmodule
module zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_rd_cmd_fsm
(\axlen_cnt_reg[1] ,
Q,
D,
wrap_second_len,
r_push_r_reg,
\m_payload_i_reg[0] ,
\m_payload_i_reg[0]_0 ,
\axlen_cnt_reg[1]_0 ,
E,
\axaddr_offset_r_reg[3] ,
s_axburst_eq0_reg,
sel_first_i,
incr_next_pending,
s_axburst_eq1_reg,
\axaddr_wrap_reg[11] ,
\axaddr_incr_reg[11] ,
m_axi_arvalid,
\m_payload_i_reg[0]_1 ,
sel_first_reg,
sel_first_reg_0,
si_rs_arvalid,
\axlen_cnt_reg[4] ,
\m_payload_i_reg[44] ,
m_axi_arready,
s_axburst_eq1_reg_0,
\cnt_read_reg[2]_rep__0 ,
\m_payload_i_reg[47] ,
\axlen_cnt_reg[1]_1 ,
\wrap_second_len_r_reg[1] ,
axaddr_offset,
wrap_next_pending,
\m_payload_i_reg[51] ,
next_pending_r_reg,
areset_d1,
sel_first_reg_1,
\axaddr_offset_r_reg[3]_0 ,
\m_payload_i_reg[6] ,
sel_first_reg_2,
sel_first_reg_3,
aclk);
output \axlen_cnt_reg[1] ;
output [1:0]Q;
output [0:0]D;
output [0:0]wrap_second_len;
output r_push_r_reg;
output \m_payload_i_reg[0] ;
output \m_payload_i_reg[0]_0 ;
output [1:0]\axlen_cnt_reg[1]_0 ;
output [0:0]E;
output [0:0]\axaddr_offset_r_reg[3] ;
output s_axburst_eq0_reg;
output sel_first_i;
output incr_next_pending;
output s_axburst_eq1_reg;
output [0:0]\axaddr_wrap_reg[11] ;
output \axaddr_incr_reg[11] ;
output m_axi_arvalid;
output [0:0]\m_payload_i_reg[0]_1 ;
output sel_first_reg;
output sel_first_reg_0;
input si_rs_arvalid;
input \axlen_cnt_reg[4] ;
input \m_payload_i_reg[44] ;
input m_axi_arready;
input s_axburst_eq1_reg_0;
input \cnt_read_reg[2]_rep__0 ;
input [3:0]\m_payload_i_reg[47] ;
input [1:0]\axlen_cnt_reg[1]_1 ;
input [0:0]\wrap_second_len_r_reg[1] ;
input [2:0]axaddr_offset;
input wrap_next_pending;
input \m_payload_i_reg[51] ;
input next_pending_r_reg;
input areset_d1;
input sel_first_reg_1;
input [0:0]\axaddr_offset_r_reg[3]_0 ;
input \m_payload_i_reg[6] ;
input sel_first_reg_2;
input sel_first_reg_3;
input aclk;
wire [0:0]D;
wire [0:0]E;
wire [1:0]Q;
wire aclk;
wire areset_d1;
wire \axaddr_incr_reg[11] ;
wire [2:0]axaddr_offset;
wire [0:0]\axaddr_offset_r_reg[3] ;
wire [0:0]\axaddr_offset_r_reg[3]_0 ;
wire [0:0]\axaddr_wrap_reg[11] ;
wire \axlen_cnt_reg[1] ;
wire [1:0]\axlen_cnt_reg[1]_0 ;
wire [1:0]\axlen_cnt_reg[1]_1 ;
wire \axlen_cnt_reg[4] ;
wire \cnt_read_reg[2]_rep__0 ;
wire incr_next_pending;
wire m_axi_arready;
wire m_axi_arvalid;
wire \m_payload_i_reg[0] ;
wire \m_payload_i_reg[0]_0 ;
wire [0:0]\m_payload_i_reg[0]_1 ;
wire \m_payload_i_reg[44] ;
wire [3:0]\m_payload_i_reg[47] ;
wire \m_payload_i_reg[51] ;
wire \m_payload_i_reg[6] ;
wire next_pending_r_reg;
wire [1:0]next_state;
wire r_push_r_reg;
wire s_axburst_eq0_reg;
wire s_axburst_eq1_reg;
wire s_axburst_eq1_reg_0;
wire sel_first_i;
wire sel_first_reg;
wire sel_first_reg_0;
wire sel_first_reg_1;
wire sel_first_reg_2;
wire sel_first_reg_3;
wire si_rs_arvalid;
wire wrap_next_pending;
wire [0:0]wrap_second_len;
wire [0:0]\wrap_second_len_r_reg[1] ;
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT4 #(
.INIT(16'hAAEA))
\axaddr_incr[0]_i_1__0
(.I0(sel_first_reg_2),
.I1(m_axi_arready),
.I2(\m_payload_i_reg[0]_0 ),
.I3(\m_payload_i_reg[0] ),
.O(\axaddr_incr_reg[11] ));
LUT6 #(
.INIT(64'hAAAAACAAAAAAA0AA))
\axaddr_offset_r[3]_i_1__0
(.I0(\axaddr_offset_r_reg[3]_0 ),
.I1(\m_payload_i_reg[47] [3]),
.I2(\m_payload_i_reg[0]_0 ),
.I3(si_rs_arvalid),
.I4(\m_payload_i_reg[0] ),
.I5(\m_payload_i_reg[6] ),
.O(\axaddr_offset_r_reg[3] ));
LUT6 #(
.INIT(64'h0400FFFF04000400))
\axlen_cnt[0]_i_1__1
(.I0(Q[1]),
.I1(si_rs_arvalid),
.I2(Q[0]),
.I3(\m_payload_i_reg[47] [1]),
.I4(\axlen_cnt_reg[1]_1 [0]),
.I5(\axlen_cnt_reg[1] ),
.O(\axlen_cnt_reg[1]_0 [0]));
LUT5 #(
.INIT(32'hF88F8888))
\axlen_cnt[1]_i_1__1
(.I0(E),
.I1(\m_payload_i_reg[47] [2]),
.I2(\axlen_cnt_reg[1]_1 [1]),
.I3(\axlen_cnt_reg[1]_1 [0]),
.I4(\axlen_cnt_reg[1] ),
.O(\axlen_cnt_reg[1]_0 [1]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'h00CA))
\axlen_cnt[7]_i_1__0
(.I0(si_rs_arvalid),
.I1(m_axi_arready),
.I2(\m_payload_i_reg[0]_0 ),
.I3(\m_payload_i_reg[0] ),
.O(\axaddr_wrap_reg[11] ));
LUT4 #(
.INIT(16'h00FB))
\axlen_cnt[7]_i_4__0
(.I0(Q[0]),
.I1(si_rs_arvalid),
.I2(Q[1]),
.I3(\axlen_cnt_reg[4] ),
.O(\axlen_cnt_reg[1] ));
LUT2 #(
.INIT(4'h2))
m_axi_arvalid_INST_0
(.I0(\m_payload_i_reg[0]_0 ),
.I1(\m_payload_i_reg[0] ),
.O(m_axi_arvalid));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT3 #(
.INIT(8'hD5))
\m_payload_i[31]_i_1__0
(.I0(si_rs_arvalid),
.I1(\m_payload_i_reg[0] ),
.I2(\m_payload_i_reg[0]_0 ),
.O(\m_payload_i_reg[0]_1 ));
LUT5 #(
.INIT(32'h8BBB8B88))
next_pending_r_i_1__2
(.I0(\m_payload_i_reg[51] ),
.I1(E),
.I2(\axlen_cnt_reg[4] ),
.I3(r_push_r_reg),
.I4(next_pending_r_reg),
.O(incr_next_pending));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT3 #(
.INIT(8'h40))
r_push_r_i_1
(.I0(\m_payload_i_reg[0] ),
.I1(\m_payload_i_reg[0]_0 ),
.I2(m_axi_arready),
.O(r_push_r_reg));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT4 #(
.INIT(16'hFB08))
s_axburst_eq0_i_1__0
(.I0(wrap_next_pending),
.I1(\m_payload_i_reg[47] [0]),
.I2(sel_first_i),
.I3(incr_next_pending),
.O(s_axburst_eq0_reg));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT4 #(
.INIT(16'hABA8))
s_axburst_eq1_i_1__0
(.I0(wrap_next_pending),
.I1(\m_payload_i_reg[47] [0]),
.I2(sel_first_i),
.I3(incr_next_pending),
.O(s_axburst_eq1_reg));
LUT6 #(
.INIT(64'hFCFFFFFFCCCECCCE))
sel_first_i_1__0
(.I0(si_rs_arvalid),
.I1(areset_d1),
.I2(\m_payload_i_reg[0] ),
.I3(\m_payload_i_reg[0]_0 ),
.I4(m_axi_arready),
.I5(sel_first_reg_1),
.O(sel_first_i));
LUT6 #(
.INIT(64'hFFFFFFFFC4C4CFCC))
sel_first_i_1__3
(.I0(m_axi_arready),
.I1(sel_first_reg_2),
.I2(Q[1]),
.I3(si_rs_arvalid),
.I4(Q[0]),
.I5(areset_d1),
.O(sel_first_reg));
LUT6 #(
.INIT(64'hFFFFFFFFC4C4CFCC))
sel_first_i_1__4
(.I0(m_axi_arready),
.I1(sel_first_reg_3),
.I2(Q[1]),
.I3(si_rs_arvalid),
.I4(Q[0]),
.I5(areset_d1),
.O(sel_first_reg_0));
LUT6 #(
.INIT(64'h003030303E3E3E3E))
\state[0]_i_1__0
(.I0(si_rs_arvalid),
.I1(Q[1]),
.I2(Q[0]),
.I3(m_axi_arready),
.I4(s_axburst_eq1_reg_0),
.I5(\cnt_read_reg[2]_rep__0 ),
.O(next_state[0]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h00AAB000))
\state[1]_i_1
(.I0(\cnt_read_reg[2]_rep__0 ),
.I1(s_axburst_eq1_reg_0),
.I2(m_axi_arready),
.I3(\m_payload_i_reg[0]_0 ),
.I4(\m_payload_i_reg[0] ),
.O(next_state[1]));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "state_reg[0]" *)
FDRE #(
.INIT(1'b0))
\state_reg[0]
(.C(aclk),
.CE(1'b1),
.D(next_state[0]),
.Q(Q[0]),
.R(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "state_reg[0]" *)
FDRE #(
.INIT(1'b0))
\state_reg[0]_rep
(.C(aclk),
.CE(1'b1),
.D(next_state[0]),
.Q(\m_payload_i_reg[0]_0 ),
.R(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "state_reg[1]" *)
FDRE #(
.INIT(1'b0))
\state_reg[1]
(.C(aclk),
.CE(1'b1),
.D(next_state[1]),
.Q(Q[1]),
.R(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "state_reg[1]" *)
FDRE #(
.INIT(1'b0))
\state_reg[1]_rep
(.C(aclk),
.CE(1'b1),
.D(next_state[1]),
.Q(\m_payload_i_reg[0] ),
.R(areset_d1));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT3 #(
.INIT(8'h04))
\wrap_boundary_axaddr_r[11]_i_1__0
(.I0(\m_payload_i_reg[0] ),
.I1(si_rs_arvalid),
.I2(\m_payload_i_reg[0]_0 ),
.O(E));
LUT2 #(
.INIT(4'h9))
\wrap_cnt_r[1]_i_1__0
(.I0(wrap_second_len),
.I1(\m_payload_i_reg[44] ),
.O(D));
LUT6 #(
.INIT(64'hFF0000FCAAAAAAAA))
\wrap_second_len_r[1]_i_1__0
(.I0(\wrap_second_len_r_reg[1] ),
.I1(axaddr_offset[2]),
.I2(\axaddr_offset_r_reg[3] ),
.I3(axaddr_offset[0]),
.I4(axaddr_offset[1]),
.I5(E),
.O(wrap_second_len));
endmodule
module zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_simple_fifo
(\cnt_read_reg[0]_rep__0_0 ,
\cnt_read_reg[1]_rep__1_0 ,
D,
\cnt_read_reg[0]_0 ,
sel,
SR,
bvalid_i_reg,
out,
b_push,
shandshake_r,
Q,
areset_d1,
\bresp_cnt_reg[7] ,
mhandshake_r,
bvalid_i_reg_0,
si_rs_bready,
in,
aclk);
output \cnt_read_reg[0]_rep__0_0 ;
output \cnt_read_reg[1]_rep__1_0 ;
output [0:0]D;
output \cnt_read_reg[0]_0 ;
output sel;
output [0:0]SR;
output bvalid_i_reg;
output [11:0]out;
input b_push;
input shandshake_r;
input [1:0]Q;
input areset_d1;
input [7:0]\bresp_cnt_reg[7] ;
input mhandshake_r;
input bvalid_i_reg_0;
input si_rs_bready;
input [19:0]in;
input aclk;
wire [0:0]D;
wire [1:0]Q;
wire [0:0]SR;
wire aclk;
wire areset_d1;
wire b_push;
wire [7:0]\bresp_cnt_reg[7] ;
wire bvalid_i_i_2_n_0;
wire bvalid_i_reg;
wire bvalid_i_reg_0;
wire [1:0]cnt_read;
wire \cnt_read[0]_i_1__2_n_0 ;
wire \cnt_read[1]_i_1_n_0 ;
wire \cnt_read_reg[0]_0 ;
wire \cnt_read_reg[0]_rep__0_0 ;
wire \cnt_read_reg[0]_rep_n_0 ;
wire \cnt_read_reg[1]_rep__0_n_0 ;
wire \cnt_read_reg[1]_rep__1_0 ;
wire \cnt_read_reg[1]_rep_n_0 ;
wire [19:0]in;
wire \memory_reg[3][0]_srl4_i_3_n_0 ;
wire \memory_reg[3][0]_srl4_i_4_n_0 ;
wire \memory_reg[3][0]_srl4_i_5_n_0 ;
wire \memory_reg[3][0]_srl4_i_6_n_0 ;
wire \memory_reg[3][0]_srl4_n_0 ;
wire \memory_reg[3][1]_srl4_n_0 ;
wire \memory_reg[3][2]_srl4_n_0 ;
wire \memory_reg[3][3]_srl4_n_0 ;
wire \memory_reg[3][4]_srl4_n_0 ;
wire \memory_reg[3][5]_srl4_n_0 ;
wire \memory_reg[3][6]_srl4_n_0 ;
wire \memory_reg[3][7]_srl4_n_0 ;
wire mhandshake_r;
wire [11:0]out;
wire sel;
wire shandshake_r;
wire si_rs_bready;
(* SOFT_HLUTNM = "soft_lutpair115" *)
LUT2 #(
.INIT(4'hB))
\bresp_cnt[7]_i_1
(.I0(areset_d1),
.I1(\cnt_read_reg[0]_0 ),
.O(SR));
(* SOFT_HLUTNM = "soft_lutpair115" *)
LUT4 #(
.INIT(16'h002A))
bvalid_i_i_1
(.I0(bvalid_i_i_2_n_0),
.I1(bvalid_i_reg_0),
.I2(si_rs_bready),
.I3(areset_d1),
.O(bvalid_i_reg));
LUT6 #(
.INIT(64'hFFFFFFFF00070707))
bvalid_i_i_2
(.I0(\cnt_read_reg[1]_rep__1_0 ),
.I1(\cnt_read_reg[0]_rep__0_0 ),
.I2(shandshake_r),
.I3(Q[1]),
.I4(Q[0]),
.I5(bvalid_i_reg_0),
.O(bvalid_i_i_2_n_0));
(* SOFT_HLUTNM = "soft_lutpair117" *)
LUT3 #(
.INIT(8'h69))
\cnt_read[0]_i_1
(.I0(\cnt_read_reg[0]_0 ),
.I1(shandshake_r),
.I2(Q[0]),
.O(D));
(* SOFT_HLUTNM = "soft_lutpair116" *)
LUT3 #(
.INIT(8'h96))
\cnt_read[0]_i_1__2
(.I0(\cnt_read_reg[0]_rep__0_0 ),
.I1(b_push),
.I2(shandshake_r),
.O(\cnt_read[0]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair116" *)
LUT4 #(
.INIT(16'hE718))
\cnt_read[1]_i_1
(.I0(\cnt_read_reg[0]_rep__0_0 ),
.I1(b_push),
.I2(shandshake_r),
.I3(\cnt_read_reg[1]_rep__1_0 ),
.O(\cnt_read[1]_i_1_n_0 ));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__2_n_0 ),
.Q(cnt_read[0]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__2_n_0 ),
.Q(\cnt_read_reg[0]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__2_n_0 ),
.Q(\cnt_read_reg[0]_rep__0_0 ),
.S(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1_n_0 ),
.Q(cnt_read[1]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1_n_0 ),
.Q(\cnt_read_reg[1]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1_n_0 ),
.Q(\cnt_read_reg[1]_rep__0_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]_rep__1
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1_n_0 ),
.Q(\cnt_read_reg[1]_rep__1_0 ),
.S(areset_d1));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][0]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][0]_srl4
(.A0(\cnt_read_reg[0]_rep_n_0 ),
.A1(\cnt_read_reg[1]_rep__0_n_0 ),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[0]),
.Q(\memory_reg[3][0]_srl4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair117" *)
LUT1 #(
.INIT(2'h1))
\memory_reg[3][0]_srl4_i_1__0
(.I0(\cnt_read_reg[0]_0 ),
.O(sel));
LUT6 #(
.INIT(64'hFFFEFFFFFFFFFFFE))
\memory_reg[3][0]_srl4_i_2__0
(.I0(\memory_reg[3][0]_srl4_i_3_n_0 ),
.I1(\memory_reg[3][0]_srl4_i_4_n_0 ),
.I2(\memory_reg[3][0]_srl4_i_5_n_0 ),
.I3(\memory_reg[3][0]_srl4_i_6_n_0 ),
.I4(\bresp_cnt_reg[7] [3]),
.I5(\memory_reg[3][3]_srl4_n_0 ),
.O(\cnt_read_reg[0]_0 ));
LUT6 #(
.INIT(64'h22F2FFFFFFFF22F2))
\memory_reg[3][0]_srl4_i_3
(.I0(\memory_reg[3][0]_srl4_n_0 ),
.I1(\bresp_cnt_reg[7] [0]),
.I2(\memory_reg[3][2]_srl4_n_0 ),
.I3(\bresp_cnt_reg[7] [2]),
.I4(\memory_reg[3][1]_srl4_n_0 ),
.I5(\bresp_cnt_reg[7] [1]),
.O(\memory_reg[3][0]_srl4_i_3_n_0 ));
LUT6 #(
.INIT(64'hF222FFFFFFFFF222))
\memory_reg[3][0]_srl4_i_4
(.I0(\bresp_cnt_reg[7] [5]),
.I1(\memory_reg[3][5]_srl4_n_0 ),
.I2(\cnt_read_reg[1]_rep__1_0 ),
.I3(\cnt_read_reg[0]_rep__0_0 ),
.I4(\bresp_cnt_reg[7] [7]),
.I5(\memory_reg[3][7]_srl4_n_0 ),
.O(\memory_reg[3][0]_srl4_i_4_n_0 ));
LUT6 #(
.INIT(64'h2FF22FF2FFFF2FF2))
\memory_reg[3][0]_srl4_i_5
(.I0(\bresp_cnt_reg[7] [2]),
.I1(\memory_reg[3][2]_srl4_n_0 ),
.I2(\memory_reg[3][4]_srl4_n_0 ),
.I3(\bresp_cnt_reg[7] [4]),
.I4(\bresp_cnt_reg[7] [0]),
.I5(\memory_reg[3][0]_srl4_n_0 ),
.O(\memory_reg[3][0]_srl4_i_5_n_0 ));
LUT5 #(
.INIT(32'h6F6FFF6F))
\memory_reg[3][0]_srl4_i_6
(.I0(\memory_reg[3][6]_srl4_n_0 ),
.I1(\bresp_cnt_reg[7] [6]),
.I2(mhandshake_r),
.I3(\memory_reg[3][5]_srl4_n_0 ),
.I4(\bresp_cnt_reg[7] [5]),
.O(\memory_reg[3][0]_srl4_i_6_n_0 ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][10]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][10]_srl4
(.A0(cnt_read[0]),
.A1(\cnt_read_reg[1]_rep_n_0 ),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[10]),
.Q(out[2]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][11]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][11]_srl4
(.A0(cnt_read[0]),
.A1(\cnt_read_reg[1]_rep_n_0 ),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[11]),
.Q(out[3]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][12]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][12]_srl4
(.A0(cnt_read[0]),
.A1(\cnt_read_reg[1]_rep_n_0 ),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[12]),
.Q(out[4]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][13]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][13]_srl4
(.A0(cnt_read[0]),
.A1(cnt_read[1]),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[13]),
.Q(out[5]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][14]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][14]_srl4
(.A0(cnt_read[0]),
.A1(cnt_read[1]),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[14]),
.Q(out[6]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][15]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][15]_srl4
(.A0(cnt_read[0]),
.A1(cnt_read[1]),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[15]),
.Q(out[7]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][16]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][16]_srl4
(.A0(cnt_read[0]),
.A1(cnt_read[1]),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[16]),
.Q(out[8]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][17]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][17]_srl4
(.A0(cnt_read[0]),
.A1(cnt_read[1]),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[17]),
.Q(out[9]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][18]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][18]_srl4
(.A0(cnt_read[0]),
.A1(cnt_read[1]),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[18]),
.Q(out[10]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][19]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][19]_srl4
(.A0(cnt_read[0]),
.A1(cnt_read[1]),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[19]),
.Q(out[11]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][1]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][1]_srl4
(.A0(\cnt_read_reg[0]_rep_n_0 ),
.A1(\cnt_read_reg[1]_rep__0_n_0 ),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[1]),
.Q(\memory_reg[3][1]_srl4_n_0 ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][2]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][2]_srl4
(.A0(\cnt_read_reg[0]_rep_n_0 ),
.A1(\cnt_read_reg[1]_rep__0_n_0 ),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[2]),
.Q(\memory_reg[3][2]_srl4_n_0 ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][3]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][3]_srl4
(.A0(\cnt_read_reg[0]_rep_n_0 ),
.A1(\cnt_read_reg[1]_rep__0_n_0 ),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[3]),
.Q(\memory_reg[3][3]_srl4_n_0 ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][4]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][4]_srl4
(.A0(\cnt_read_reg[0]_rep_n_0 ),
.A1(\cnt_read_reg[1]_rep__0_n_0 ),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[4]),
.Q(\memory_reg[3][4]_srl4_n_0 ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][5]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][5]_srl4
(.A0(\cnt_read_reg[0]_rep_n_0 ),
.A1(\cnt_read_reg[1]_rep__0_n_0 ),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[5]),
.Q(\memory_reg[3][5]_srl4_n_0 ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][6]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][6]_srl4
(.A0(\cnt_read_reg[0]_rep_n_0 ),
.A1(\cnt_read_reg[1]_rep_n_0 ),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[6]),
.Q(\memory_reg[3][6]_srl4_n_0 ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][7]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][7]_srl4
(.A0(\cnt_read_reg[0]_rep_n_0 ),
.A1(\cnt_read_reg[1]_rep_n_0 ),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[7]),
.Q(\memory_reg[3][7]_srl4_n_0 ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][8]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][8]_srl4
(.A0(\cnt_read_reg[0]_rep_n_0 ),
.A1(\cnt_read_reg[1]_rep_n_0 ),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[8]),
.Q(out[0]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][9]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][9]_srl4
(.A0(\cnt_read_reg[0]_rep_n_0 ),
.A1(\cnt_read_reg[1]_rep_n_0 ),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[9]),
.Q(out[1]));
endmodule
(* ORIG_REF_NAME = "axi_protocol_converter_v2_1_13_b2s_simple_fifo" *)
module zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized0
(mhandshake,
Q,
m_axi_bready,
\skid_buffer_reg[1] ,
m_axi_bvalid,
mhandshake_r,
shandshake_r,
\bresp_cnt_reg[3] ,
sel,
in,
aclk,
areset_d1,
D);
output mhandshake;
output [1:0]Q;
output m_axi_bready;
output [1:0]\skid_buffer_reg[1] ;
input m_axi_bvalid;
input mhandshake_r;
input shandshake_r;
input \bresp_cnt_reg[3] ;
input sel;
input [1:0]in;
input aclk;
input areset_d1;
input [0:0]D;
wire [0:0]D;
wire [1:0]Q;
wire aclk;
wire areset_d1;
wire \bresp_cnt_reg[3] ;
wire \cnt_read[1]_i_1__0_n_0 ;
wire [1:0]in;
wire m_axi_bready;
wire m_axi_bvalid;
wire mhandshake;
wire mhandshake_r;
wire sel;
wire shandshake_r;
wire [1:0]\skid_buffer_reg[1] ;
(* SOFT_HLUTNM = "soft_lutpair118" *)
LUT4 #(
.INIT(16'hA69A))
\cnt_read[1]_i_1__0
(.I0(Q[1]),
.I1(shandshake_r),
.I2(Q[0]),
.I3(\bresp_cnt_reg[3] ),
.O(\cnt_read[1]_i_1__0_n_0 ));
(* KEEP = "yes" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]
(.C(aclk),
.CE(1'b1),
.D(D),
.Q(Q[0]),
.S(areset_d1));
(* KEEP = "yes" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1__0_n_0 ),
.Q(Q[1]),
.S(areset_d1));
(* SOFT_HLUTNM = "soft_lutpair118" *)
LUT3 #(
.INIT(8'h08))
m_axi_bready_INST_0
(.I0(Q[1]),
.I1(Q[0]),
.I2(mhandshake_r),
.O(m_axi_bready));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3][0]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][0]_srl4
(.A0(Q[0]),
.A1(Q[1]),
.A2(1'b0),
.A3(1'b0),
.CE(sel),
.CLK(aclk),
.D(in[0]),
.Q(\skid_buffer_reg[1] [0]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3][1]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][1]_srl4
(.A0(Q[0]),
.A1(Q[1]),
.A2(1'b0),
.A3(1'b0),
.CE(sel),
.CLK(aclk),
.D(in[1]),
.Q(\skid_buffer_reg[1] [1]));
LUT4 #(
.INIT(16'h2000))
mhandshake_r_i_1
(.I0(m_axi_bvalid),
.I1(mhandshake_r),
.I2(Q[0]),
.I3(Q[1]),
.O(mhandshake));
endmodule
(* ORIG_REF_NAME = "axi_protocol_converter_v2_1_13_b2s_simple_fifo" *)
module zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized1
(\cnt_read_reg[3]_rep__2_0 ,
wr_en0,
\cnt_read_reg[4]_rep__2_0 ,
\cnt_read_reg[4]_rep__2_1 ,
m_axi_rready,
\state_reg[1]_rep ,
out,
s_ready_i_reg,
s_ready_i_reg_0,
si_rs_rready,
\cnt_read_reg[4]_rep__0_0 ,
m_axi_rvalid,
in,
aclk,
areset_d1);
output \cnt_read_reg[3]_rep__2_0 ;
output wr_en0;
output \cnt_read_reg[4]_rep__2_0 ;
output \cnt_read_reg[4]_rep__2_1 ;
output m_axi_rready;
output \state_reg[1]_rep ;
output [33:0]out;
input s_ready_i_reg;
input s_ready_i_reg_0;
input si_rs_rready;
input \cnt_read_reg[4]_rep__0_0 ;
input m_axi_rvalid;
input [33:0]in;
input aclk;
input areset_d1;
wire aclk;
wire areset_d1;
wire [4:0]cnt_read;
wire \cnt_read[0]_i_1__0_n_0 ;
wire \cnt_read[1]_i_1__2_n_0 ;
wire \cnt_read[2]_i_1_n_0 ;
wire \cnt_read[3]_i_1_n_0 ;
wire \cnt_read[4]_i_1_n_0 ;
wire \cnt_read[4]_i_2_n_0 ;
wire \cnt_read[4]_i_3_n_0 ;
wire \cnt_read_reg[0]_rep__0_n_0 ;
wire \cnt_read_reg[0]_rep__1_n_0 ;
wire \cnt_read_reg[0]_rep__2_n_0 ;
wire \cnt_read_reg[0]_rep_n_0 ;
wire \cnt_read_reg[1]_rep__0_n_0 ;
wire \cnt_read_reg[1]_rep__1_n_0 ;
wire \cnt_read_reg[1]_rep__2_n_0 ;
wire \cnt_read_reg[1]_rep_n_0 ;
wire \cnt_read_reg[2]_rep__0_n_0 ;
wire \cnt_read_reg[2]_rep__1_n_0 ;
wire \cnt_read_reg[2]_rep__2_n_0 ;
wire \cnt_read_reg[2]_rep_n_0 ;
wire \cnt_read_reg[3]_rep__0_n_0 ;
wire \cnt_read_reg[3]_rep__1_n_0 ;
wire \cnt_read_reg[3]_rep__2_0 ;
wire \cnt_read_reg[3]_rep_n_0 ;
wire \cnt_read_reg[4]_rep__0_0 ;
wire \cnt_read_reg[4]_rep__0_n_0 ;
wire \cnt_read_reg[4]_rep__1_n_0 ;
wire \cnt_read_reg[4]_rep__2_0 ;
wire \cnt_read_reg[4]_rep__2_1 ;
wire \cnt_read_reg[4]_rep_n_0 ;
wire [33:0]in;
wire m_axi_rready;
wire m_axi_rvalid;
wire [33:0]out;
wire s_ready_i_reg;
wire s_ready_i_reg_0;
wire si_rs_rready;
wire \state_reg[1]_rep ;
wire wr_en0;
wire \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][13]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][14]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][15]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][16]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][17]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][18]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][19]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][20]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][21]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][22]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][23]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][24]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][25]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][26]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][27]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][28]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][29]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][30]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][31]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][32]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][33]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED ;
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT3 #(
.INIT(8'h96))
\cnt_read[0]_i_1__0
(.I0(\cnt_read_reg[0]_rep__2_n_0 ),
.I1(s_ready_i_reg),
.I2(wr_en0),
.O(\cnt_read[0]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT4 #(
.INIT(16'hA96A))
\cnt_read[1]_i_1__2
(.I0(\cnt_read_reg[1]_rep__2_n_0 ),
.I1(\cnt_read_reg[0]_rep__2_n_0 ),
.I2(wr_en0),
.I3(s_ready_i_reg),
.O(\cnt_read[1]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT5 #(
.INIT(32'hA6AAAA9A))
\cnt_read[2]_i_1
(.I0(\cnt_read_reg[2]_rep__2_n_0 ),
.I1(\cnt_read_reg[1]_rep__2_n_0 ),
.I2(s_ready_i_reg),
.I3(wr_en0),
.I4(\cnt_read_reg[0]_rep__2_n_0 ),
.O(\cnt_read[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAAAAAAA96AAAAAAA))
\cnt_read[3]_i_1
(.I0(\cnt_read_reg[3]_rep__2_0 ),
.I1(\cnt_read_reg[2]_rep__2_n_0 ),
.I2(\cnt_read_reg[1]_rep__2_n_0 ),
.I3(\cnt_read_reg[0]_rep__2_n_0 ),
.I4(wr_en0),
.I5(s_ready_i_reg),
.O(\cnt_read[3]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAA55AAA6A6AAA6AA))
\cnt_read[4]_i_1
(.I0(\cnt_read_reg[4]_rep__2_0 ),
.I1(\cnt_read[4]_i_2_n_0 ),
.I2(\cnt_read[4]_i_3_n_0 ),
.I3(s_ready_i_reg_0),
.I4(\cnt_read_reg[4]_rep__2_1 ),
.I5(\cnt_read_reg[3]_rep__2_0 ),
.O(\cnt_read[4]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT2 #(
.INIT(4'h1))
\cnt_read[4]_i_2
(.I0(\cnt_read_reg[2]_rep__2_n_0 ),
.I1(\cnt_read_reg[1]_rep__2_n_0 ),
.O(\cnt_read[4]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT4 #(
.INIT(16'hFFFB))
\cnt_read[4]_i_3
(.I0(\cnt_read_reg[0]_rep__2_n_0 ),
.I1(si_rs_rready),
.I2(\cnt_read_reg[4]_rep__0_0 ),
.I3(wr_en0),
.O(\cnt_read[4]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT3 #(
.INIT(8'h80))
\cnt_read[4]_i_5
(.I0(\cnt_read_reg[0]_rep__2_n_0 ),
.I1(\cnt_read_reg[1]_rep__2_n_0 ),
.I2(\cnt_read_reg[2]_rep__2_n_0 ),
.O(\cnt_read_reg[4]_rep__2_1 ));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__0_n_0 ),
.Q(cnt_read[0]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__0_n_0 ),
.Q(\cnt_read_reg[0]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__0_n_0 ),
.Q(\cnt_read_reg[0]_rep__0_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]_rep__1
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__0_n_0 ),
.Q(\cnt_read_reg[0]_rep__1_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]_rep__2
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__0_n_0 ),
.Q(\cnt_read_reg[0]_rep__2_n_0 ),
.S(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1__2_n_0 ),
.Q(cnt_read[1]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1__2_n_0 ),
.Q(\cnt_read_reg[1]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1__2_n_0 ),
.Q(\cnt_read_reg[1]_rep__0_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]_rep__1
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1__2_n_0 ),
.Q(\cnt_read_reg[1]_rep__1_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]_rep__2
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1__2_n_0 ),
.Q(\cnt_read_reg[1]_rep__2_n_0 ),
.S(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[2]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[2]_i_1_n_0 ),
.Q(cnt_read[2]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[2]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[2]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[2]_i_1_n_0 ),
.Q(\cnt_read_reg[2]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[2]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[2]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[2]_i_1_n_0 ),
.Q(\cnt_read_reg[2]_rep__0_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[2]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[2]_rep__1
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[2]_i_1_n_0 ),
.Q(\cnt_read_reg[2]_rep__1_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[2]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[2]_rep__2
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[2]_i_1_n_0 ),
.Q(\cnt_read_reg[2]_rep__2_n_0 ),
.S(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[3]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[3]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[3]_i_1_n_0 ),
.Q(cnt_read[3]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[3]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[3]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[3]_i_1_n_0 ),
.Q(\cnt_read_reg[3]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[3]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[3]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[3]_i_1_n_0 ),
.Q(\cnt_read_reg[3]_rep__0_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[3]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[3]_rep__1
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[3]_i_1_n_0 ),
.Q(\cnt_read_reg[3]_rep__1_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[3]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[3]_rep__2
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[3]_i_1_n_0 ),
.Q(\cnt_read_reg[3]_rep__2_0 ),
.S(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[4]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[4]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[4]_i_1_n_0 ),
.Q(cnt_read[4]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[4]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[4]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[4]_i_1_n_0 ),
.Q(\cnt_read_reg[4]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[4]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[4]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[4]_i_1_n_0 ),
.Q(\cnt_read_reg[4]_rep__0_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[4]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[4]_rep__1
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[4]_i_1_n_0 ),
.Q(\cnt_read_reg[4]_rep__1_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[4]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[4]_rep__2
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[4]_i_1_n_0 ),
.Q(\cnt_read_reg[4]_rep__2_0 ),
.S(areset_d1));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT5 #(
.INIT(32'hF77F777F))
m_axi_rready_INST_0
(.I0(\cnt_read_reg[3]_rep__2_0 ),
.I1(\cnt_read_reg[4]_rep__2_0 ),
.I2(\cnt_read_reg[1]_rep__2_n_0 ),
.I3(\cnt_read_reg[2]_rep__2_n_0 ),
.I4(\cnt_read_reg[0]_rep__2_n_0 ),
.O(m_axi_rready));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][0]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][0]_srl32
(.A({\cnt_read_reg[4]_rep__1_n_0 ,\cnt_read_reg[3]_rep__1_n_0 ,\cnt_read_reg[2]_rep__1_n_0 ,\cnt_read_reg[1]_rep__1_n_0 ,\cnt_read_reg[0]_rep__1_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[0]),
.Q(out[0]),
.Q31(\NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED ));
LUT6 #(
.INIT(64'hAA2A2AAA2A2A2AAA))
\memory_reg[31][0]_srl32_i_1
(.I0(m_axi_rvalid),
.I1(\cnt_read_reg[3]_rep__2_0 ),
.I2(\cnt_read_reg[4]_rep__2_0 ),
.I3(\cnt_read_reg[1]_rep__2_n_0 ),
.I4(\cnt_read_reg[2]_rep__2_n_0 ),
.I5(\cnt_read_reg[0]_rep__2_n_0 ),
.O(wr_en0));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][10]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][10]_srl32
(.A({\cnt_read_reg[4]_rep__0_n_0 ,\cnt_read_reg[3]_rep__0_n_0 ,\cnt_read_reg[2]_rep__0_n_0 ,\cnt_read_reg[1]_rep__0_n_0 ,\cnt_read_reg[0]_rep__0_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[10]),
.Q(out[10]),
.Q31(\NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][11]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][11]_srl32
(.A({\cnt_read_reg[4]_rep__0_n_0 ,\cnt_read_reg[3]_rep__0_n_0 ,\cnt_read_reg[2]_rep__0_n_0 ,\cnt_read_reg[1]_rep__0_n_0 ,\cnt_read_reg[0]_rep__0_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[11]),
.Q(out[11]),
.Q31(\NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][12]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][12]_srl32
(.A({\cnt_read_reg[4]_rep__0_n_0 ,\cnt_read_reg[3]_rep__0_n_0 ,\cnt_read_reg[2]_rep__0_n_0 ,\cnt_read_reg[1]_rep__0_n_0 ,\cnt_read_reg[0]_rep__0_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[12]),
.Q(out[12]),
.Q31(\NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][13]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][13]_srl32
(.A({\cnt_read_reg[4]_rep__0_n_0 ,\cnt_read_reg[3]_rep__0_n_0 ,\cnt_read_reg[2]_rep__0_n_0 ,\cnt_read_reg[1]_rep__0_n_0 ,\cnt_read_reg[0]_rep__0_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[13]),
.Q(out[13]),
.Q31(\NLW_memory_reg[31][13]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][14]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][14]_srl32
(.A({\cnt_read_reg[4]_rep__0_n_0 ,\cnt_read_reg[3]_rep__0_n_0 ,\cnt_read_reg[2]_rep__0_n_0 ,\cnt_read_reg[1]_rep__0_n_0 ,\cnt_read_reg[0]_rep__0_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[14]),
.Q(out[14]),
.Q31(\NLW_memory_reg[31][14]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][15]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][15]_srl32
(.A({\cnt_read_reg[4]_rep__0_n_0 ,\cnt_read_reg[3]_rep__0_n_0 ,\cnt_read_reg[2]_rep__0_n_0 ,\cnt_read_reg[1]_rep__0_n_0 ,\cnt_read_reg[0]_rep__0_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[15]),
.Q(out[15]),
.Q31(\NLW_memory_reg[31][15]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][16]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][16]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[16]),
.Q(out[16]),
.Q31(\NLW_memory_reg[31][16]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][17]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][17]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[17]),
.Q(out[17]),
.Q31(\NLW_memory_reg[31][17]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][18]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][18]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[18]),
.Q(out[18]),
.Q31(\NLW_memory_reg[31][18]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][19]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][19]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[19]),
.Q(out[19]),
.Q31(\NLW_memory_reg[31][19]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][1]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][1]_srl32
(.A({\cnt_read_reg[4]_rep__1_n_0 ,\cnt_read_reg[3]_rep__1_n_0 ,\cnt_read_reg[2]_rep__1_n_0 ,\cnt_read_reg[1]_rep__1_n_0 ,\cnt_read_reg[0]_rep__1_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[1]),
.Q(out[1]),
.Q31(\NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][20]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][20]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[20]),
.Q(out[20]),
.Q31(\NLW_memory_reg[31][20]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][21]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][21]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[21]),
.Q(out[21]),
.Q31(\NLW_memory_reg[31][21]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][22]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][22]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[22]),
.Q(out[22]),
.Q31(\NLW_memory_reg[31][22]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][23]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][23]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[23]),
.Q(out[23]),
.Q31(\NLW_memory_reg[31][23]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][24]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][24]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[24]),
.Q(out[24]),
.Q31(\NLW_memory_reg[31][24]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][25]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][25]_srl32
(.A(cnt_read),
.CE(wr_en0),
.CLK(aclk),
.D(in[25]),
.Q(out[25]),
.Q31(\NLW_memory_reg[31][25]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][26]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][26]_srl32
(.A(cnt_read),
.CE(wr_en0),
.CLK(aclk),
.D(in[26]),
.Q(out[26]),
.Q31(\NLW_memory_reg[31][26]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][27]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][27]_srl32
(.A(cnt_read),
.CE(wr_en0),
.CLK(aclk),
.D(in[27]),
.Q(out[27]),
.Q31(\NLW_memory_reg[31][27]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][28]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][28]_srl32
(.A(cnt_read),
.CE(wr_en0),
.CLK(aclk),
.D(in[28]),
.Q(out[28]),
.Q31(\NLW_memory_reg[31][28]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][29]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][29]_srl32
(.A(cnt_read),
.CE(wr_en0),
.CLK(aclk),
.D(in[29]),
.Q(out[29]),
.Q31(\NLW_memory_reg[31][29]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][2]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][2]_srl32
(.A({\cnt_read_reg[4]_rep__1_n_0 ,\cnt_read_reg[3]_rep__1_n_0 ,\cnt_read_reg[2]_rep__1_n_0 ,\cnt_read_reg[1]_rep__1_n_0 ,\cnt_read_reg[0]_rep__1_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[2]),
.Q(out[2]),
.Q31(\NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][30]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][30]_srl32
(.A(cnt_read),
.CE(wr_en0),
.CLK(aclk),
.D(in[30]),
.Q(out[30]),
.Q31(\NLW_memory_reg[31][30]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][31]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][31]_srl32
(.A(cnt_read),
.CE(wr_en0),
.CLK(aclk),
.D(in[31]),
.Q(out[31]),
.Q31(\NLW_memory_reg[31][31]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][32]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][32]_srl32
(.A(cnt_read),
.CE(wr_en0),
.CLK(aclk),
.D(in[32]),
.Q(out[32]),
.Q31(\NLW_memory_reg[31][32]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][33]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][33]_srl32
(.A(cnt_read),
.CE(wr_en0),
.CLK(aclk),
.D(in[33]),
.Q(out[33]),
.Q31(\NLW_memory_reg[31][33]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][3]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][3]_srl32
(.A({\cnt_read_reg[4]_rep__1_n_0 ,\cnt_read_reg[3]_rep__1_n_0 ,\cnt_read_reg[2]_rep__1_n_0 ,\cnt_read_reg[1]_rep__1_n_0 ,\cnt_read_reg[0]_rep__1_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[3]),
.Q(out[3]),
.Q31(\NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][4]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][4]_srl32
(.A({\cnt_read_reg[4]_rep__1_n_0 ,\cnt_read_reg[3]_rep__1_n_0 ,\cnt_read_reg[2]_rep__1_n_0 ,\cnt_read_reg[1]_rep__1_n_0 ,\cnt_read_reg[0]_rep__1_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[4]),
.Q(out[4]),
.Q31(\NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][5]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][5]_srl32
(.A({\cnt_read_reg[4]_rep__1_n_0 ,\cnt_read_reg[3]_rep__1_n_0 ,\cnt_read_reg[2]_rep__1_n_0 ,\cnt_read_reg[1]_rep__1_n_0 ,\cnt_read_reg[0]_rep__1_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[5]),
.Q(out[5]),
.Q31(\NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][6]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][6]_srl32
(.A({\cnt_read_reg[4]_rep__1_n_0 ,\cnt_read_reg[3]_rep__1_n_0 ,\cnt_read_reg[2]_rep__1_n_0 ,\cnt_read_reg[1]_rep__1_n_0 ,\cnt_read_reg[0]_rep__1_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[6]),
.Q(out[6]),
.Q31(\NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][7]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][7]_srl32
(.A({\cnt_read_reg[4]_rep__0_n_0 ,\cnt_read_reg[3]_rep__0_n_0 ,\cnt_read_reg[2]_rep__0_n_0 ,\cnt_read_reg[1]_rep__0_n_0 ,\cnt_read_reg[0]_rep__0_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[7]),
.Q(out[7]),
.Q31(\NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][8]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][8]_srl32
(.A({\cnt_read_reg[4]_rep__0_n_0 ,\cnt_read_reg[3]_rep__0_n_0 ,\cnt_read_reg[2]_rep__0_n_0 ,\cnt_read_reg[1]_rep__0_n_0 ,\cnt_read_reg[0]_rep__0_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[8]),
.Q(out[8]),
.Q31(\NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][9]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][9]_srl32
(.A({\cnt_read_reg[4]_rep__0_n_0 ,\cnt_read_reg[3]_rep__0_n_0 ,\cnt_read_reg[2]_rep__0_n_0 ,\cnt_read_reg[1]_rep__0_n_0 ,\cnt_read_reg[0]_rep__0_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[9]),
.Q(out[9]),
.Q31(\NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT5 #(
.INIT(32'h7C000000))
\state[1]_i_4
(.I0(\cnt_read_reg[0]_rep__2_n_0 ),
.I1(\cnt_read_reg[2]_rep__2_n_0 ),
.I2(\cnt_read_reg[1]_rep__2_n_0 ),
.I3(\cnt_read_reg[4]_rep__2_0 ),
.I4(\cnt_read_reg[3]_rep__2_0 ),
.O(\state_reg[1]_rep ));
endmodule
(* ORIG_REF_NAME = "axi_protocol_converter_v2_1_13_b2s_simple_fifo" *)
module zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized2
(\state_reg[1]_rep ,
\cnt_read_reg[4]_rep__2 ,
m_valid_i_reg,
\skid_buffer_reg[46] ,
r_push_r,
s_ready_i_reg,
\cnt_read_reg[0]_rep__2 ,
si_rs_rready,
wr_en0,
\cnt_read_reg[4]_rep__2_0 ,
\cnt_read_reg[3]_rep__2 ,
\cnt_read_reg[0]_rep__2_0 ,
in,
aclk,
areset_d1);
output \state_reg[1]_rep ;
output \cnt_read_reg[4]_rep__2 ;
output m_valid_i_reg;
output [12:0]\skid_buffer_reg[46] ;
input r_push_r;
input s_ready_i_reg;
input \cnt_read_reg[0]_rep__2 ;
input si_rs_rready;
input wr_en0;
input \cnt_read_reg[4]_rep__2_0 ;
input \cnt_read_reg[3]_rep__2 ;
input \cnt_read_reg[0]_rep__2_0 ;
input [12:0]in;
input aclk;
input areset_d1;
wire aclk;
wire areset_d1;
wire [4:0]cnt_read;
wire \cnt_read[0]_i_1__1_n_0 ;
wire \cnt_read[1]_i_1__1_n_0 ;
wire \cnt_read[2]_i_1__0_n_0 ;
wire \cnt_read[3]_i_1__0_n_0 ;
wire \cnt_read[4]_i_1__0_n_0 ;
wire \cnt_read[4]_i_2__0_n_0 ;
wire \cnt_read[4]_i_3__0_n_0 ;
wire \cnt_read[4]_i_4__0_n_0 ;
wire \cnt_read[4]_i_5__0_n_0 ;
wire \cnt_read_reg[0]_rep__0_n_0 ;
wire \cnt_read_reg[0]_rep__2 ;
wire \cnt_read_reg[0]_rep__2_0 ;
wire \cnt_read_reg[0]_rep_n_0 ;
wire \cnt_read_reg[1]_rep__0_n_0 ;
wire \cnt_read_reg[1]_rep_n_0 ;
wire \cnt_read_reg[2]_rep__0_n_0 ;
wire \cnt_read_reg[2]_rep_n_0 ;
wire \cnt_read_reg[3]_rep__0_n_0 ;
wire \cnt_read_reg[3]_rep__2 ;
wire \cnt_read_reg[3]_rep_n_0 ;
wire \cnt_read_reg[4]_rep__0_n_0 ;
wire \cnt_read_reg[4]_rep__2 ;
wire \cnt_read_reg[4]_rep__2_0 ;
wire \cnt_read_reg[4]_rep_n_0 ;
wire [12:0]in;
wire m_valid_i_reg;
wire r_push_r;
wire s_ready_i_reg;
wire si_rs_rready;
wire [12:0]\skid_buffer_reg[46] ;
wire \state_reg[1]_rep ;
wire wr_en0;
wire \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED ;
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT3 #(
.INIT(8'h96))
\cnt_read[0]_i_1__1
(.I0(\cnt_read_reg[0]_rep__0_n_0 ),
.I1(s_ready_i_reg),
.I2(r_push_r),
.O(\cnt_read[0]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT4 #(
.INIT(16'hA69A))
\cnt_read[1]_i_1__1
(.I0(\cnt_read_reg[1]_rep__0_n_0 ),
.I1(\cnt_read_reg[0]_rep__0_n_0 ),
.I2(s_ready_i_reg),
.I3(r_push_r),
.O(\cnt_read[1]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT5 #(
.INIT(32'hAA6AA9AA))
\cnt_read[2]_i_1__0
(.I0(\cnt_read_reg[2]_rep__0_n_0 ),
.I1(\cnt_read_reg[1]_rep__0_n_0 ),
.I2(r_push_r),
.I3(s_ready_i_reg),
.I4(\cnt_read_reg[0]_rep__0_n_0 ),
.O(\cnt_read[2]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'hAAAA6AAAAAA9AAAA))
\cnt_read[3]_i_1__0
(.I0(\cnt_read_reg[3]_rep__0_n_0 ),
.I1(\cnt_read_reg[2]_rep__0_n_0 ),
.I2(\cnt_read_reg[1]_rep__0_n_0 ),
.I3(r_push_r),
.I4(s_ready_i_reg),
.I5(\cnt_read_reg[0]_rep__0_n_0 ),
.O(\cnt_read[3]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'h6A666A6AAA99AAAA))
\cnt_read[4]_i_1__0
(.I0(\cnt_read_reg[4]_rep__0_n_0 ),
.I1(\cnt_read[4]_i_2__0_n_0 ),
.I2(\cnt_read[4]_i_3__0_n_0 ),
.I3(\cnt_read[4]_i_4__0_n_0 ),
.I4(\cnt_read[4]_i_5__0_n_0 ),
.I5(\cnt_read_reg[3]_rep__0_n_0 ),
.O(\cnt_read[4]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT3 #(
.INIT(8'h8A))
\cnt_read[4]_i_2__0
(.I0(r_push_r),
.I1(m_valid_i_reg),
.I2(si_rs_rready),
.O(\cnt_read[4]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT3 #(
.INIT(8'h80))
\cnt_read[4]_i_3__0
(.I0(\cnt_read_reg[2]_rep__0_n_0 ),
.I1(\cnt_read_reg[1]_rep__0_n_0 ),
.I2(\cnt_read_reg[0]_rep__0_n_0 ),
.O(\cnt_read[4]_i_3__0_n_0 ));
LUT3 #(
.INIT(8'h4F))
\cnt_read[4]_i_4
(.I0(m_valid_i_reg),
.I1(si_rs_rready),
.I2(wr_en0),
.O(\cnt_read_reg[4]_rep__2 ));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT4 #(
.INIT(16'hFFFB))
\cnt_read[4]_i_4__0
(.I0(\cnt_read_reg[0]_rep__0_n_0 ),
.I1(si_rs_rready),
.I2(m_valid_i_reg),
.I3(r_push_r),
.O(\cnt_read[4]_i_4__0_n_0 ));
LUT2 #(
.INIT(4'h1))
\cnt_read[4]_i_5__0
(.I0(\cnt_read_reg[1]_rep__0_n_0 ),
.I1(\cnt_read_reg[2]_rep__0_n_0 ),
.O(\cnt_read[4]_i_5__0_n_0 ));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__1_n_0 ),
.Q(cnt_read[0]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__1_n_0 ),
.Q(\cnt_read_reg[0]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__1_n_0 ),
.Q(\cnt_read_reg[0]_rep__0_n_0 ),
.S(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1__1_n_0 ),
.Q(cnt_read[1]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1__1_n_0 ),
.Q(\cnt_read_reg[1]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1__1_n_0 ),
.Q(\cnt_read_reg[1]_rep__0_n_0 ),
.S(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[2]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[2]_i_1__0_n_0 ),
.Q(cnt_read[2]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[2]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[2]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[2]_i_1__0_n_0 ),
.Q(\cnt_read_reg[2]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[2]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[2]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[2]_i_1__0_n_0 ),
.Q(\cnt_read_reg[2]_rep__0_n_0 ),
.S(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[3]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[3]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[3]_i_1__0_n_0 ),
.Q(cnt_read[3]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[3]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[3]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[3]_i_1__0_n_0 ),
.Q(\cnt_read_reg[3]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[3]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[3]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[3]_i_1__0_n_0 ),
.Q(\cnt_read_reg[3]_rep__0_n_0 ),
.S(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[4]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[4]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[4]_i_1__0_n_0 ),
.Q(cnt_read[4]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[4]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[4]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[4]_i_1__0_n_0 ),
.Q(\cnt_read_reg[4]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[4]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[4]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[4]_i_1__0_n_0 ),
.Q(\cnt_read_reg[4]_rep__0_n_0 ),
.S(areset_d1));
LUT6 #(
.INIT(64'hFF80808080808080))
m_valid_i_i_2
(.I0(\cnt_read_reg[4]_rep__0_n_0 ),
.I1(\cnt_read_reg[3]_rep__0_n_0 ),
.I2(\cnt_read[4]_i_3__0_n_0 ),
.I3(\cnt_read_reg[4]_rep__2_0 ),
.I4(\cnt_read_reg[3]_rep__2 ),
.I5(\cnt_read_reg[0]_rep__2_0 ),
.O(m_valid_i_reg));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][0]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][0]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(r_push_r),
.CLK(aclk),
.D(in[0]),
.Q(\skid_buffer_reg[46] [0]),
.Q31(\NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][10]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][10]_srl32
(.A(cnt_read),
.CE(r_push_r),
.CLK(aclk),
.D(in[10]),
.Q(\skid_buffer_reg[46] [10]),
.Q31(\NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][11]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][11]_srl32
(.A(cnt_read),
.CE(r_push_r),
.CLK(aclk),
.D(in[11]),
.Q(\skid_buffer_reg[46] [11]),
.Q31(\NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][12]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][12]_srl32
(.A(cnt_read),
.CE(r_push_r),
.CLK(aclk),
.D(in[12]),
.Q(\skid_buffer_reg[46] [12]),
.Q31(\NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][1]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][1]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(r_push_r),
.CLK(aclk),
.D(in[1]),
.Q(\skid_buffer_reg[46] [1]),
.Q31(\NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][2]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][2]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(r_push_r),
.CLK(aclk),
.D(in[2]),
.Q(\skid_buffer_reg[46] [2]),
.Q31(\NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][3]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][3]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(r_push_r),
.CLK(aclk),
.D(in[3]),
.Q(\skid_buffer_reg[46] [3]),
.Q31(\NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][4]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][4]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(r_push_r),
.CLK(aclk),
.D(in[4]),
.Q(\skid_buffer_reg[46] [4]),
.Q31(\NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][5]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][5]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(r_push_r),
.CLK(aclk),
.D(in[5]),
.Q(\skid_buffer_reg[46] [5]),
.Q31(\NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][6]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][6]_srl32
(.A(cnt_read),
.CE(r_push_r),
.CLK(aclk),
.D(in[6]),
.Q(\skid_buffer_reg[46] [6]),
.Q31(\NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][7]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][7]_srl32
(.A(cnt_read),
.CE(r_push_r),
.CLK(aclk),
.D(in[7]),
.Q(\skid_buffer_reg[46] [7]),
.Q31(\NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][8]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][8]_srl32
(.A(cnt_read),
.CE(r_push_r),
.CLK(aclk),
.D(in[8]),
.Q(\skid_buffer_reg[46] [8]),
.Q31(\NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][9]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][9]_srl32
(.A(cnt_read),
.CE(r_push_r),
.CLK(aclk),
.D(in[9]),
.Q(\skid_buffer_reg[46] [9]),
.Q31(\NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED ));
LUT6 #(
.INIT(64'hBEFEAAAAAAAAAAAA))
\state[1]_i_2
(.I0(\cnt_read_reg[0]_rep__2 ),
.I1(\cnt_read_reg[2]_rep__0_n_0 ),
.I2(\cnt_read_reg[1]_rep__0_n_0 ),
.I3(\cnt_read_reg[0]_rep__0_n_0 ),
.I4(\cnt_read_reg[3]_rep__0_n_0 ),
.I5(\cnt_read_reg[4]_rep__0_n_0 ),
.O(\state_reg[1]_rep ));
endmodule
module zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_wr_cmd_fsm
(\axlen_cnt_reg[4] ,
Q,
D,
\wrap_second_len_r_reg[1] ,
\state_reg[1]_rep_0 ,
\state_reg[1]_rep_1 ,
\axlen_cnt_reg[5] ,
E,
\axaddr_offset_r_reg[3] ,
s_axburst_eq0_reg,
wrap_next_pending,
sel_first_i,
incr_next_pending,
s_axburst_eq1_reg,
next,
\m_payload_i_reg[0] ,
\axaddr_wrap_reg[0] ,
\axaddr_incr_reg[11] ,
\m_payload_i_reg[0]_0 ,
m_axi_awvalid,
sel_first_reg,
sel_first_reg_0,
si_rs_awvalid,
\axlen_cnt_reg[3] ,
\m_payload_i_reg[44] ,
s_axburst_eq1_reg_0,
\cnt_read_reg[1]_rep__1 ,
\cnt_read_reg[0]_rep__0 ,
m_axi_awready,
\m_payload_i_reg[49] ,
\axlen_cnt_reg[5]_0 ,
\axlen_cnt_reg[3]_0 ,
\axlen_cnt_reg[4]_0 ,
\wrap_second_len_r_reg[1]_0 ,
\m_payload_i_reg[35] ,
\m_payload_i_reg[48] ,
next_pending_r_reg,
areset_d1,
sel_first_reg_1,
\m_payload_i_reg[46] ,
\axlen_cnt_reg[2] ,
next_pending_r_reg_0,
\axaddr_offset_r_reg[3]_0 ,
\m_payload_i_reg[6] ,
sel_first_reg_2,
sel_first__0,
aclk);
output \axlen_cnt_reg[4] ;
output [1:0]Q;
output [0:0]D;
output [0:0]\wrap_second_len_r_reg[1] ;
output \state_reg[1]_rep_0 ;
output \state_reg[1]_rep_1 ;
output [3:0]\axlen_cnt_reg[5] ;
output [0:0]E;
output [0:0]\axaddr_offset_r_reg[3] ;
output s_axburst_eq0_reg;
output wrap_next_pending;
output sel_first_i;
output incr_next_pending;
output s_axburst_eq1_reg;
output next;
output \m_payload_i_reg[0] ;
output [0:0]\axaddr_wrap_reg[0] ;
output \axaddr_incr_reg[11] ;
output [0:0]\m_payload_i_reg[0]_0 ;
output m_axi_awvalid;
output sel_first_reg;
output sel_first_reg_0;
input si_rs_awvalid;
input \axlen_cnt_reg[3] ;
input \m_payload_i_reg[44] ;
input s_axburst_eq1_reg_0;
input \cnt_read_reg[1]_rep__1 ;
input \cnt_read_reg[0]_rep__0 ;
input m_axi_awready;
input [5:0]\m_payload_i_reg[49] ;
input [3:0]\axlen_cnt_reg[5]_0 ;
input \axlen_cnt_reg[3]_0 ;
input \axlen_cnt_reg[4]_0 ;
input [0:0]\wrap_second_len_r_reg[1]_0 ;
input [2:0]\m_payload_i_reg[35] ;
input \m_payload_i_reg[48] ;
input next_pending_r_reg;
input areset_d1;
input sel_first_reg_1;
input \m_payload_i_reg[46] ;
input \axlen_cnt_reg[2] ;
input next_pending_r_reg_0;
input [0:0]\axaddr_offset_r_reg[3]_0 ;
input \m_payload_i_reg[6] ;
input sel_first_reg_2;
input sel_first__0;
input aclk;
wire [0:0]D;
wire [0:0]E;
wire [1:0]Q;
wire aclk;
wire areset_d1;
wire \axaddr_incr_reg[11] ;
wire [0:0]\axaddr_offset_r_reg[3] ;
wire [0:0]\axaddr_offset_r_reg[3]_0 ;
wire [0:0]\axaddr_wrap_reg[0] ;
wire \axlen_cnt_reg[2] ;
wire \axlen_cnt_reg[3] ;
wire \axlen_cnt_reg[3]_0 ;
wire \axlen_cnt_reg[4] ;
wire \axlen_cnt_reg[4]_0 ;
wire [3:0]\axlen_cnt_reg[5] ;
wire [3:0]\axlen_cnt_reg[5]_0 ;
wire \cnt_read_reg[0]_rep__0 ;
wire \cnt_read_reg[1]_rep__1 ;
wire incr_next_pending;
wire m_axi_awready;
wire m_axi_awvalid;
wire \m_payload_i_reg[0] ;
wire [0:0]\m_payload_i_reg[0]_0 ;
wire [2:0]\m_payload_i_reg[35] ;
wire \m_payload_i_reg[44] ;
wire \m_payload_i_reg[46] ;
wire \m_payload_i_reg[48] ;
wire [5:0]\m_payload_i_reg[49] ;
wire \m_payload_i_reg[6] ;
wire next;
wire next_pending_r_reg;
wire next_pending_r_reg_0;
wire [0:0]next_state;
wire s_axburst_eq0_reg;
wire s_axburst_eq1_reg;
wire s_axburst_eq1_reg_0;
wire sel_first__0;
wire sel_first_i;
wire sel_first_reg;
wire sel_first_reg_0;
wire sel_first_reg_1;
wire sel_first_reg_2;
wire si_rs_awvalid;
wire \state[0]_i_2_n_0 ;
wire \state[1]_i_1__0_n_0 ;
wire \state_reg[1]_rep_0 ;
wire \state_reg[1]_rep_1 ;
wire wrap_next_pending;
wire [0:0]\wrap_second_len_r_reg[1] ;
wire [0:0]\wrap_second_len_r_reg[1]_0 ;
(* SOFT_HLUTNM = "soft_lutpair110" *)
LUT4 #(
.INIT(16'hEEFE))
\axaddr_incr[0]_i_1
(.I0(sel_first_reg_2),
.I1(\m_payload_i_reg[0] ),
.I2(\state_reg[1]_rep_0 ),
.I3(\state_reg[1]_rep_1 ),
.O(\axaddr_incr_reg[11] ));
LUT6 #(
.INIT(64'hAAAAACAAAAAAA0AA))
\axaddr_offset_r[3]_i_1
(.I0(\axaddr_offset_r_reg[3]_0 ),
.I1(\m_payload_i_reg[49] [3]),
.I2(\state_reg[1]_rep_1 ),
.I3(si_rs_awvalid),
.I4(\state_reg[1]_rep_0 ),
.I5(\m_payload_i_reg[6] ),
.O(\axaddr_offset_r_reg[3] ));
LUT6 #(
.INIT(64'h0400FFFF04000400))
\axlen_cnt[0]_i_1
(.I0(Q[1]),
.I1(si_rs_awvalid),
.I2(Q[0]),
.I3(\m_payload_i_reg[49] [1]),
.I4(\axlen_cnt_reg[5]_0 [0]),
.I5(\axlen_cnt_reg[4] ),
.O(\axlen_cnt_reg[5] [0]));
LUT5 #(
.INIT(32'hF88F8888))
\axlen_cnt[1]_i_1
(.I0(E),
.I1(\m_payload_i_reg[49] [2]),
.I2(\axlen_cnt_reg[5]_0 [1]),
.I3(\axlen_cnt_reg[5]_0 [0]),
.I4(\axlen_cnt_reg[4] ),
.O(\axlen_cnt_reg[5] [1]));
LUT5 #(
.INIT(32'hF88F8888))
\axlen_cnt[4]_i_1
(.I0(E),
.I1(\m_payload_i_reg[49] [4]),
.I2(\axlen_cnt_reg[5]_0 [2]),
.I3(\axlen_cnt_reg[3]_0 ),
.I4(\axlen_cnt_reg[4] ),
.O(\axlen_cnt_reg[5] [2]));
LUT5 #(
.INIT(32'hF88F8888))
\axlen_cnt[5]_i_1
(.I0(E),
.I1(\m_payload_i_reg[49] [5]),
.I2(\axlen_cnt_reg[5]_0 [3]),
.I3(\axlen_cnt_reg[4]_0 ),
.I4(\axlen_cnt_reg[4] ),
.O(\axlen_cnt_reg[5] [3]));
(* SOFT_HLUTNM = "soft_lutpair110" *)
LUT4 #(
.INIT(16'hCCFE))
\axlen_cnt[7]_i_1
(.I0(si_rs_awvalid),
.I1(\m_payload_i_reg[0] ),
.I2(\state_reg[1]_rep_0 ),
.I3(\state_reg[1]_rep_1 ),
.O(\axaddr_wrap_reg[0] ));
(* SOFT_HLUTNM = "soft_lutpair111" *)
LUT4 #(
.INIT(16'h00FB))
\axlen_cnt[7]_i_5
(.I0(Q[0]),
.I1(si_rs_awvalid),
.I2(Q[1]),
.I3(\axlen_cnt_reg[3] ),
.O(\axlen_cnt_reg[4] ));
(* SOFT_HLUTNM = "soft_lutpair112" *)
LUT2 #(
.INIT(4'h2))
m_axi_awvalid_INST_0
(.I0(\state_reg[1]_rep_1 ),
.I1(\state_reg[1]_rep_0 ),
.O(m_axi_awvalid));
LUT2 #(
.INIT(4'hB))
\m_payload_i[31]_i_1
(.I0(\m_payload_i_reg[0] ),
.I1(si_rs_awvalid),
.O(\m_payload_i_reg[0]_0 ));
LUT6 #(
.INIT(64'h88008888A800A8A8))
\memory_reg[3][0]_srl4_i_1
(.I0(\state_reg[1]_rep_1 ),
.I1(\state_reg[1]_rep_0 ),
.I2(m_axi_awready),
.I3(\cnt_read_reg[0]_rep__0 ),
.I4(\cnt_read_reg[1]_rep__1 ),
.I5(s_axburst_eq1_reg_0),
.O(\m_payload_i_reg[0] ));
LUT5 #(
.INIT(32'h8BBB8B88))
next_pending_r_i_1
(.I0(\m_payload_i_reg[48] ),
.I1(E),
.I2(\axlen_cnt_reg[3] ),
.I3(next),
.I4(next_pending_r_reg),
.O(incr_next_pending));
LUT5 #(
.INIT(32'h8BBB8B88))
next_pending_r_i_1__0
(.I0(\m_payload_i_reg[46] ),
.I1(E),
.I2(\axlen_cnt_reg[2] ),
.I3(next),
.I4(next_pending_r_reg_0),
.O(wrap_next_pending));
LUT6 #(
.INIT(64'hF3F35100FFFF0000))
next_pending_r_i_4
(.I0(s_axburst_eq1_reg_0),
.I1(\cnt_read_reg[1]_rep__1 ),
.I2(\cnt_read_reg[0]_rep__0 ),
.I3(m_axi_awready),
.I4(\state_reg[1]_rep_0 ),
.I5(\state_reg[1]_rep_1 ),
.O(next));
(* SOFT_HLUTNM = "soft_lutpair109" *)
LUT4 #(
.INIT(16'hFB08))
s_axburst_eq0_i_1
(.I0(wrap_next_pending),
.I1(\m_payload_i_reg[49] [0]),
.I2(sel_first_i),
.I3(incr_next_pending),
.O(s_axburst_eq0_reg));
(* SOFT_HLUTNM = "soft_lutpair109" *)
LUT4 #(
.INIT(16'hABA8))
s_axburst_eq1_i_1
(.I0(wrap_next_pending),
.I1(\m_payload_i_reg[49] [0]),
.I2(sel_first_i),
.I3(incr_next_pending),
.O(s_axburst_eq1_reg));
LUT6 #(
.INIT(64'hCCCEFCFFCCCECCCE))
sel_first_i_1
(.I0(si_rs_awvalid),
.I1(areset_d1),
.I2(\state_reg[1]_rep_1 ),
.I3(\state_reg[1]_rep_0 ),
.I4(\m_payload_i_reg[0] ),
.I5(sel_first_reg_1),
.O(sel_first_i));
LUT6 #(
.INIT(64'hFFFFFFFF44440F04))
sel_first_i_1__1
(.I0(\m_payload_i_reg[0] ),
.I1(sel_first_reg_2),
.I2(Q[1]),
.I3(si_rs_awvalid),
.I4(Q[0]),
.I5(areset_d1),
.O(sel_first_reg));
LUT6 #(
.INIT(64'hFFFFFFFF44440F04))
sel_first_i_1__2
(.I0(\m_payload_i_reg[0] ),
.I1(sel_first__0),
.I2(Q[1]),
.I3(si_rs_awvalid),
.I4(Q[0]),
.I5(areset_d1),
.O(sel_first_reg_0));
(* SOFT_HLUTNM = "soft_lutpair111" *)
LUT3 #(
.INIT(8'h2F))
\state[0]_i_1
(.I0(si_rs_awvalid),
.I1(Q[0]),
.I2(\state[0]_i_2_n_0 ),
.O(next_state));
LUT6 #(
.INIT(64'hFA08FAFA0F0F0F0F))
\state[0]_i_2
(.I0(m_axi_awready),
.I1(s_axburst_eq1_reg_0),
.I2(\state_reg[1]_rep_0 ),
.I3(\cnt_read_reg[0]_rep__0 ),
.I4(\cnt_read_reg[1]_rep__1 ),
.I5(\state_reg[1]_rep_1 ),
.O(\state[0]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0C0CAE0000000000))
\state[1]_i_1__0
(.I0(s_axburst_eq1_reg_0),
.I1(\cnt_read_reg[1]_rep__1 ),
.I2(\cnt_read_reg[0]_rep__0 ),
.I3(m_axi_awready),
.I4(\state_reg[1]_rep_0 ),
.I5(\state_reg[1]_rep_1 ),
.O(\state[1]_i_1__0_n_0 ));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "state_reg[0]" *)
FDRE #(
.INIT(1'b0))
\state_reg[0]
(.C(aclk),
.CE(1'b1),
.D(next_state),
.Q(Q[0]),
.R(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "state_reg[0]" *)
FDRE #(
.INIT(1'b0))
\state_reg[0]_rep
(.C(aclk),
.CE(1'b1),
.D(next_state),
.Q(\state_reg[1]_rep_1 ),
.R(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "state_reg[1]" *)
FDRE #(
.INIT(1'b0))
\state_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\state[1]_i_1__0_n_0 ),
.Q(Q[1]),
.R(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "state_reg[1]" *)
FDRE #(
.INIT(1'b0))
\state_reg[1]_rep
(.C(aclk),
.CE(1'b1),
.D(\state[1]_i_1__0_n_0 ),
.Q(\state_reg[1]_rep_0 ),
.R(areset_d1));
(* SOFT_HLUTNM = "soft_lutpair112" *)
LUT3 #(
.INIT(8'h04))
\wrap_boundary_axaddr_r[11]_i_1
(.I0(\state_reg[1]_rep_0 ),
.I1(si_rs_awvalid),
.I2(\state_reg[1]_rep_1 ),
.O(E));
LUT2 #(
.INIT(4'h9))
\wrap_cnt_r[1]_i_1
(.I0(\wrap_second_len_r_reg[1] ),
.I1(\m_payload_i_reg[44] ),
.O(D));
LUT6 #(
.INIT(64'hFF0000FCAAAAAAAA))
\wrap_second_len_r[1]_i_1
(.I0(\wrap_second_len_r_reg[1]_0 ),
.I1(\m_payload_i_reg[35] [2]),
.I2(\axaddr_offset_r_reg[3] ),
.I3(\m_payload_i_reg[35] [0]),
.I4(\m_payload_i_reg[35] [1]),
.I5(E),
.O(\wrap_second_len_r_reg[1] ));
endmodule
module zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_wrap_cmd
(next_pending_r_reg_0,
sel_first_reg_0,
next_pending_r_reg_1,
m_axi_awaddr,
\axaddr_offset_r_reg[3]_0 ,
\wrap_second_len_r_reg[3]_0 ,
wrap_next_pending,
aclk,
sel_first_reg_1,
E,
\m_payload_i_reg[47] ,
next,
axaddr_incr_reg,
\m_payload_i_reg[38] ,
\axaddr_incr_reg[3] ,
sel_first_reg_2,
\axaddr_offset_r_reg[3]_1 ,
\wrap_second_len_r_reg[3]_1 ,
m_valid_i_reg,
\wrap_second_len_r_reg[3]_2 ,
\m_payload_i_reg[6] );
output next_pending_r_reg_0;
output sel_first_reg_0;
output next_pending_r_reg_1;
output [11:0]m_axi_awaddr;
output [3:0]\axaddr_offset_r_reg[3]_0 ;
output [3:0]\wrap_second_len_r_reg[3]_0 ;
input wrap_next_pending;
input aclk;
input sel_first_reg_1;
input [0:0]E;
input [18:0]\m_payload_i_reg[47] ;
input next;
input [7:0]axaddr_incr_reg;
input \m_payload_i_reg[38] ;
input [2:0]\axaddr_incr_reg[3] ;
input sel_first_reg_2;
input [3:0]\axaddr_offset_r_reg[3]_1 ;
input [3:0]\wrap_second_len_r_reg[3]_1 ;
input [0:0]m_valid_i_reg;
input [3:0]\wrap_second_len_r_reg[3]_2 ;
input [6:0]\m_payload_i_reg[6] ;
wire [0:0]E;
wire aclk;
wire [7:0]axaddr_incr_reg;
wire [2:0]\axaddr_incr_reg[3] ;
wire [3:0]\axaddr_offset_r_reg[3]_0 ;
wire [3:0]\axaddr_offset_r_reg[3]_1 ;
wire [11:0]axaddr_wrap;
wire [11:0]axaddr_wrap0;
wire \axaddr_wrap[0]_i_1_n_0 ;
wire \axaddr_wrap[10]_i_1_n_0 ;
wire \axaddr_wrap[11]_i_1_n_0 ;
wire \axaddr_wrap[11]_i_2_n_0 ;
wire \axaddr_wrap[11]_i_4_n_0 ;
wire \axaddr_wrap[11]_i_5_n_0 ;
wire \axaddr_wrap[11]_i_6_n_0 ;
wire \axaddr_wrap[11]_i_7_n_0 ;
wire \axaddr_wrap[11]_i_8_n_0 ;
wire \axaddr_wrap[1]_i_1_n_0 ;
wire \axaddr_wrap[2]_i_1_n_0 ;
wire \axaddr_wrap[3]_i_1_n_0 ;
wire \axaddr_wrap[3]_i_3_n_0 ;
wire \axaddr_wrap[3]_i_4_n_0 ;
wire \axaddr_wrap[3]_i_5_n_0 ;
wire \axaddr_wrap[3]_i_6_n_0 ;
wire \axaddr_wrap[4]_i_1_n_0 ;
wire \axaddr_wrap[5]_i_1_n_0 ;
wire \axaddr_wrap[6]_i_1_n_0 ;
wire \axaddr_wrap[7]_i_1_n_0 ;
wire \axaddr_wrap[7]_i_3_n_0 ;
wire \axaddr_wrap[7]_i_4_n_0 ;
wire \axaddr_wrap[7]_i_5_n_0 ;
wire \axaddr_wrap[7]_i_6_n_0 ;
wire \axaddr_wrap[8]_i_1_n_0 ;
wire \axaddr_wrap[9]_i_1_n_0 ;
wire \axaddr_wrap_reg[11]_i_3_n_1 ;
wire \axaddr_wrap_reg[11]_i_3_n_2 ;
wire \axaddr_wrap_reg[11]_i_3_n_3 ;
wire \axaddr_wrap_reg[3]_i_2_n_0 ;
wire \axaddr_wrap_reg[3]_i_2_n_1 ;
wire \axaddr_wrap_reg[3]_i_2_n_2 ;
wire \axaddr_wrap_reg[3]_i_2_n_3 ;
wire \axaddr_wrap_reg[7]_i_2_n_0 ;
wire \axaddr_wrap_reg[7]_i_2_n_1 ;
wire \axaddr_wrap_reg[7]_i_2_n_2 ;
wire \axaddr_wrap_reg[7]_i_2_n_3 ;
wire \axlen_cnt[0]_i_1__0_n_0 ;
wire \axlen_cnt[1]_i_1__0_n_0 ;
wire \axlen_cnt[2]_i_1__0_n_0 ;
wire \axlen_cnt[3]_i_1__0_n_0 ;
wire \axlen_cnt_reg_n_0_[0] ;
wire \axlen_cnt_reg_n_0_[1] ;
wire \axlen_cnt_reg_n_0_[2] ;
wire \axlen_cnt_reg_n_0_[3] ;
wire [11:0]m_axi_awaddr;
wire \m_payload_i_reg[38] ;
wire [18:0]\m_payload_i_reg[47] ;
wire [6:0]\m_payload_i_reg[6] ;
wire [0:0]m_valid_i_reg;
wire next;
wire next_pending_r_reg_0;
wire next_pending_r_reg_1;
wire sel_first_reg_0;
wire sel_first_reg_1;
wire sel_first_reg_2;
wire [11:0]wrap_boundary_axaddr_r;
wire [3:0]wrap_cnt_r;
wire wrap_next_pending;
wire [3:0]\wrap_second_len_r_reg[3]_0 ;
wire [3:0]\wrap_second_len_r_reg[3]_1 ;
wire [3:0]\wrap_second_len_r_reg[3]_2 ;
wire [3:3]\NLW_axaddr_wrap_reg[11]_i_3_CO_UNCONNECTED ;
FDRE \axaddr_offset_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\axaddr_offset_r_reg[3]_1 [0]),
.Q(\axaddr_offset_r_reg[3]_0 [0]),
.R(1'b0));
FDRE \axaddr_offset_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\axaddr_offset_r_reg[3]_1 [1]),
.Q(\axaddr_offset_r_reg[3]_0 [1]),
.R(1'b0));
FDRE \axaddr_offset_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\axaddr_offset_r_reg[3]_1 [2]),
.Q(\axaddr_offset_r_reg[3]_0 [2]),
.R(1'b0));
FDRE \axaddr_offset_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(\axaddr_offset_r_reg[3]_1 [3]),
.Q(\axaddr_offset_r_reg[3]_0 [3]),
.R(1'b0));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[0]_i_1
(.I0(wrap_boundary_axaddr_r[0]),
.I1(\axaddr_wrap[11]_i_2_n_0 ),
.I2(axaddr_wrap0[0]),
.I3(next),
.I4(\m_payload_i_reg[47] [0]),
.O(\axaddr_wrap[0]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[10]_i_1
(.I0(wrap_boundary_axaddr_r[10]),
.I1(\axaddr_wrap[11]_i_2_n_0 ),
.I2(axaddr_wrap0[10]),
.I3(next),
.I4(\m_payload_i_reg[47] [10]),
.O(\axaddr_wrap[10]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[11]_i_1
(.I0(wrap_boundary_axaddr_r[11]),
.I1(\axaddr_wrap[11]_i_2_n_0 ),
.I2(axaddr_wrap0[11]),
.I3(next),
.I4(\m_payload_i_reg[47] [11]),
.O(\axaddr_wrap[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair114" *)
LUT3 #(
.INIT(8'h41))
\axaddr_wrap[11]_i_2
(.I0(\axaddr_wrap[11]_i_4_n_0 ),
.I1(wrap_cnt_r[3]),
.I2(\axlen_cnt_reg_n_0_[3] ),
.O(\axaddr_wrap[11]_i_2_n_0 ));
LUT6 #(
.INIT(64'h6FF6FFFFFFFF6FF6))
\axaddr_wrap[11]_i_4
(.I0(wrap_cnt_r[0]),
.I1(\axlen_cnt_reg_n_0_[0] ),
.I2(\axlen_cnt_reg_n_0_[2] ),
.I3(wrap_cnt_r[2]),
.I4(\axlen_cnt_reg_n_0_[1] ),
.I5(wrap_cnt_r[1]),
.O(\axaddr_wrap[11]_i_4_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_wrap[11]_i_5
(.I0(axaddr_wrap[11]),
.O(\axaddr_wrap[11]_i_5_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_wrap[11]_i_6
(.I0(axaddr_wrap[10]),
.O(\axaddr_wrap[11]_i_6_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_wrap[11]_i_7
(.I0(axaddr_wrap[9]),
.O(\axaddr_wrap[11]_i_7_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_wrap[11]_i_8
(.I0(axaddr_wrap[8]),
.O(\axaddr_wrap[11]_i_8_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[1]_i_1
(.I0(wrap_boundary_axaddr_r[1]),
.I1(\axaddr_wrap[11]_i_2_n_0 ),
.I2(axaddr_wrap0[1]),
.I3(next),
.I4(\m_payload_i_reg[47] [1]),
.O(\axaddr_wrap[1]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[2]_i_1
(.I0(wrap_boundary_axaddr_r[2]),
.I1(\axaddr_wrap[11]_i_2_n_0 ),
.I2(axaddr_wrap0[2]),
.I3(next),
.I4(\m_payload_i_reg[47] [2]),
.O(\axaddr_wrap[2]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[3]_i_1
(.I0(wrap_boundary_axaddr_r[3]),
.I1(\axaddr_wrap[11]_i_2_n_0 ),
.I2(axaddr_wrap0[3]),
.I3(next),
.I4(\m_payload_i_reg[47] [3]),
.O(\axaddr_wrap[3]_i_1_n_0 ));
LUT3 #(
.INIT(8'h6A))
\axaddr_wrap[3]_i_3
(.I0(axaddr_wrap[3]),
.I1(\m_payload_i_reg[47] [12]),
.I2(\m_payload_i_reg[47] [13]),
.O(\axaddr_wrap[3]_i_3_n_0 ));
LUT3 #(
.INIT(8'h9A))
\axaddr_wrap[3]_i_4
(.I0(axaddr_wrap[2]),
.I1(\m_payload_i_reg[47] [12]),
.I2(\m_payload_i_reg[47] [13]),
.O(\axaddr_wrap[3]_i_4_n_0 ));
LUT3 #(
.INIT(8'h9A))
\axaddr_wrap[3]_i_5
(.I0(axaddr_wrap[1]),
.I1(\m_payload_i_reg[47] [13]),
.I2(\m_payload_i_reg[47] [12]),
.O(\axaddr_wrap[3]_i_5_n_0 ));
LUT3 #(
.INIT(8'hA9))
\axaddr_wrap[3]_i_6
(.I0(axaddr_wrap[0]),
.I1(\m_payload_i_reg[47] [12]),
.I2(\m_payload_i_reg[47] [13]),
.O(\axaddr_wrap[3]_i_6_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[4]_i_1
(.I0(wrap_boundary_axaddr_r[4]),
.I1(\axaddr_wrap[11]_i_2_n_0 ),
.I2(axaddr_wrap0[4]),
.I3(next),
.I4(\m_payload_i_reg[47] [4]),
.O(\axaddr_wrap[4]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[5]_i_1
(.I0(wrap_boundary_axaddr_r[5]),
.I1(\axaddr_wrap[11]_i_2_n_0 ),
.I2(axaddr_wrap0[5]),
.I3(next),
.I4(\m_payload_i_reg[47] [5]),
.O(\axaddr_wrap[5]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[6]_i_1
(.I0(wrap_boundary_axaddr_r[6]),
.I1(\axaddr_wrap[11]_i_2_n_0 ),
.I2(axaddr_wrap0[6]),
.I3(next),
.I4(\m_payload_i_reg[47] [6]),
.O(\axaddr_wrap[6]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[7]_i_1
(.I0(wrap_boundary_axaddr_r[7]),
.I1(\axaddr_wrap[11]_i_2_n_0 ),
.I2(axaddr_wrap0[7]),
.I3(next),
.I4(\m_payload_i_reg[47] [7]),
.O(\axaddr_wrap[7]_i_1_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_wrap[7]_i_3
(.I0(axaddr_wrap[7]),
.O(\axaddr_wrap[7]_i_3_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_wrap[7]_i_4
(.I0(axaddr_wrap[6]),
.O(\axaddr_wrap[7]_i_4_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_wrap[7]_i_5
(.I0(axaddr_wrap[5]),
.O(\axaddr_wrap[7]_i_5_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_wrap[7]_i_6
(.I0(axaddr_wrap[4]),
.O(\axaddr_wrap[7]_i_6_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[8]_i_1
(.I0(wrap_boundary_axaddr_r[8]),
.I1(\axaddr_wrap[11]_i_2_n_0 ),
.I2(axaddr_wrap0[8]),
.I3(next),
.I4(\m_payload_i_reg[47] [8]),
.O(\axaddr_wrap[8]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[9]_i_1
(.I0(wrap_boundary_axaddr_r[9]),
.I1(\axaddr_wrap[11]_i_2_n_0 ),
.I2(axaddr_wrap0[9]),
.I3(next),
.I4(\m_payload_i_reg[47] [9]),
.O(\axaddr_wrap[9]_i_1_n_0 ));
FDRE \axaddr_wrap_reg[0]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[0]_i_1_n_0 ),
.Q(axaddr_wrap[0]),
.R(1'b0));
FDRE \axaddr_wrap_reg[10]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[10]_i_1_n_0 ),
.Q(axaddr_wrap[10]),
.R(1'b0));
FDRE \axaddr_wrap_reg[11]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[11]_i_1_n_0 ),
.Q(axaddr_wrap[11]),
.R(1'b0));
CARRY4 \axaddr_wrap_reg[11]_i_3
(.CI(\axaddr_wrap_reg[7]_i_2_n_0 ),
.CO({\NLW_axaddr_wrap_reg[11]_i_3_CO_UNCONNECTED [3],\axaddr_wrap_reg[11]_i_3_n_1 ,\axaddr_wrap_reg[11]_i_3_n_2 ,\axaddr_wrap_reg[11]_i_3_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(axaddr_wrap0[11:8]),
.S({\axaddr_wrap[11]_i_5_n_0 ,\axaddr_wrap[11]_i_6_n_0 ,\axaddr_wrap[11]_i_7_n_0 ,\axaddr_wrap[11]_i_8_n_0 }));
FDRE \axaddr_wrap_reg[1]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[1]_i_1_n_0 ),
.Q(axaddr_wrap[1]),
.R(1'b0));
FDRE \axaddr_wrap_reg[2]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[2]_i_1_n_0 ),
.Q(axaddr_wrap[2]),
.R(1'b0));
FDRE \axaddr_wrap_reg[3]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[3]_i_1_n_0 ),
.Q(axaddr_wrap[3]),
.R(1'b0));
CARRY4 \axaddr_wrap_reg[3]_i_2
(.CI(1'b0),
.CO({\axaddr_wrap_reg[3]_i_2_n_0 ,\axaddr_wrap_reg[3]_i_2_n_1 ,\axaddr_wrap_reg[3]_i_2_n_2 ,\axaddr_wrap_reg[3]_i_2_n_3 }),
.CYINIT(1'b0),
.DI(axaddr_wrap[3:0]),
.O(axaddr_wrap0[3:0]),
.S({\axaddr_wrap[3]_i_3_n_0 ,\axaddr_wrap[3]_i_4_n_0 ,\axaddr_wrap[3]_i_5_n_0 ,\axaddr_wrap[3]_i_6_n_0 }));
FDRE \axaddr_wrap_reg[4]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[4]_i_1_n_0 ),
.Q(axaddr_wrap[4]),
.R(1'b0));
FDRE \axaddr_wrap_reg[5]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[5]_i_1_n_0 ),
.Q(axaddr_wrap[5]),
.R(1'b0));
FDRE \axaddr_wrap_reg[6]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[6]_i_1_n_0 ),
.Q(axaddr_wrap[6]),
.R(1'b0));
FDRE \axaddr_wrap_reg[7]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[7]_i_1_n_0 ),
.Q(axaddr_wrap[7]),
.R(1'b0));
CARRY4 \axaddr_wrap_reg[7]_i_2
(.CI(\axaddr_wrap_reg[3]_i_2_n_0 ),
.CO({\axaddr_wrap_reg[7]_i_2_n_0 ,\axaddr_wrap_reg[7]_i_2_n_1 ,\axaddr_wrap_reg[7]_i_2_n_2 ,\axaddr_wrap_reg[7]_i_2_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(axaddr_wrap0[7:4]),
.S({\axaddr_wrap[7]_i_3_n_0 ,\axaddr_wrap[7]_i_4_n_0 ,\axaddr_wrap[7]_i_5_n_0 ,\axaddr_wrap[7]_i_6_n_0 }));
FDRE \axaddr_wrap_reg[8]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[8]_i_1_n_0 ),
.Q(axaddr_wrap[8]),
.R(1'b0));
FDRE \axaddr_wrap_reg[9]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[9]_i_1_n_0 ),
.Q(axaddr_wrap[9]),
.R(1'b0));
LUT6 #(
.INIT(64'hA3A3A3A3A3A3A3A0))
\axlen_cnt[0]_i_1__0
(.I0(\m_payload_i_reg[47] [15]),
.I1(\axlen_cnt_reg_n_0_[0] ),
.I2(E),
.I3(\axlen_cnt_reg_n_0_[3] ),
.I4(\axlen_cnt_reg_n_0_[1] ),
.I5(\axlen_cnt_reg_n_0_[2] ),
.O(\axlen_cnt[0]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'hFFFF999800009998))
\axlen_cnt[1]_i_1__0
(.I0(\axlen_cnt_reg_n_0_[1] ),
.I1(\axlen_cnt_reg_n_0_[0] ),
.I2(\axlen_cnt_reg_n_0_[3] ),
.I3(\axlen_cnt_reg_n_0_[2] ),
.I4(E),
.I5(\m_payload_i_reg[47] [16]),
.O(\axlen_cnt[1]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'hFFFFA9A80000A9A8))
\axlen_cnt[2]_i_1__0
(.I0(\axlen_cnt_reg_n_0_[2] ),
.I1(\axlen_cnt_reg_n_0_[0] ),
.I2(\axlen_cnt_reg_n_0_[1] ),
.I3(\axlen_cnt_reg_n_0_[3] ),
.I4(E),
.I5(\m_payload_i_reg[47] [17]),
.O(\axlen_cnt[2]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'hFFFFAAA80000AAA8))
\axlen_cnt[3]_i_1__0
(.I0(\axlen_cnt_reg_n_0_[3] ),
.I1(\axlen_cnt_reg_n_0_[2] ),
.I2(\axlen_cnt_reg_n_0_[1] ),
.I3(\axlen_cnt_reg_n_0_[0] ),
.I4(E),
.I5(\m_payload_i_reg[47] [18]),
.O(\axlen_cnt[3]_i_1__0_n_0 ));
FDRE \axlen_cnt_reg[0]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[0]_i_1__0_n_0 ),
.Q(\axlen_cnt_reg_n_0_[0] ),
.R(1'b0));
FDRE \axlen_cnt_reg[1]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[1]_i_1__0_n_0 ),
.Q(\axlen_cnt_reg_n_0_[1] ),
.R(1'b0));
FDRE \axlen_cnt_reg[2]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[2]_i_1__0_n_0 ),
.Q(\axlen_cnt_reg_n_0_[2] ),
.R(1'b0));
FDRE \axlen_cnt_reg[3]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[3]_i_1__0_n_0 ),
.Q(\axlen_cnt_reg_n_0_[3] ),
.R(1'b0));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_awaddr[0]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[0]),
.I2(\m_payload_i_reg[47] [14]),
.I3(\axaddr_incr_reg[3] [0]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [0]),
.O(m_axi_awaddr[0]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_awaddr[10]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[10]),
.I2(\m_payload_i_reg[47] [14]),
.I3(axaddr_incr_reg[6]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [10]),
.O(m_axi_awaddr[10]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_awaddr[11]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[11]),
.I2(\m_payload_i_reg[47] [14]),
.I3(axaddr_incr_reg[7]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [11]),
.O(m_axi_awaddr[11]));
LUT5 #(
.INIT(32'hB8FFB800))
\m_axi_awaddr[1]_INST_0
(.I0(\m_payload_i_reg[47] [1]),
.I1(sel_first_reg_0),
.I2(axaddr_wrap[1]),
.I3(\m_payload_i_reg[47] [14]),
.I4(sel_first_reg_2),
.O(m_axi_awaddr[1]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_awaddr[2]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[2]),
.I2(\m_payload_i_reg[47] [14]),
.I3(\axaddr_incr_reg[3] [1]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [2]),
.O(m_axi_awaddr[2]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_awaddr[3]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[3]),
.I2(\m_payload_i_reg[47] [14]),
.I3(\axaddr_incr_reg[3] [2]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [3]),
.O(m_axi_awaddr[3]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_awaddr[4]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[4]),
.I2(\m_payload_i_reg[47] [14]),
.I3(axaddr_incr_reg[0]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [4]),
.O(m_axi_awaddr[4]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_awaddr[5]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[5]),
.I2(\m_payload_i_reg[47] [14]),
.I3(axaddr_incr_reg[1]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [5]),
.O(m_axi_awaddr[5]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_awaddr[6]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[6]),
.I2(\m_payload_i_reg[47] [14]),
.I3(axaddr_incr_reg[2]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [6]),
.O(m_axi_awaddr[6]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_awaddr[7]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[7]),
.I2(\m_payload_i_reg[47] [14]),
.I3(axaddr_incr_reg[3]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [7]),
.O(m_axi_awaddr[7]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_awaddr[8]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[8]),
.I2(\m_payload_i_reg[47] [14]),
.I3(axaddr_incr_reg[4]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [8]),
.O(m_axi_awaddr[8]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_awaddr[9]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[9]),
.I2(\m_payload_i_reg[47] [14]),
.I3(axaddr_incr_reg[5]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [9]),
.O(m_axi_awaddr[9]));
(* SOFT_HLUTNM = "soft_lutpair114" *)
LUT3 #(
.INIT(8'h01))
next_pending_r_i_3__0
(.I0(\axlen_cnt_reg_n_0_[2] ),
.I1(\axlen_cnt_reg_n_0_[1] ),
.I2(\axlen_cnt_reg_n_0_[3] ),
.O(next_pending_r_reg_1));
FDRE next_pending_r_reg
(.C(aclk),
.CE(1'b1),
.D(wrap_next_pending),
.Q(next_pending_r_reg_0),
.R(1'b0));
FDRE sel_first_reg
(.C(aclk),
.CE(1'b1),
.D(sel_first_reg_1),
.Q(sel_first_reg_0),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[0]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [0]),
.Q(wrap_boundary_axaddr_r[0]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[10]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[47] [10]),
.Q(wrap_boundary_axaddr_r[10]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[11]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[47] [11]),
.Q(wrap_boundary_axaddr_r[11]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[1]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [1]),
.Q(wrap_boundary_axaddr_r[1]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[2]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [2]),
.Q(wrap_boundary_axaddr_r[2]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[3]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [3]),
.Q(wrap_boundary_axaddr_r[3]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[4]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [4]),
.Q(wrap_boundary_axaddr_r[4]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[5]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [5]),
.Q(wrap_boundary_axaddr_r[5]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[6]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [6]),
.Q(wrap_boundary_axaddr_r[6]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[7]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[47] [7]),
.Q(wrap_boundary_axaddr_r[7]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[8]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[47] [8]),
.Q(wrap_boundary_axaddr_r[8]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[9]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[47] [9]),
.Q(wrap_boundary_axaddr_r[9]),
.R(1'b0));
FDRE \wrap_cnt_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_2 [0]),
.Q(wrap_cnt_r[0]),
.R(1'b0));
FDRE \wrap_cnt_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_2 [1]),
.Q(wrap_cnt_r[1]),
.R(1'b0));
FDRE \wrap_cnt_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_2 [2]),
.Q(wrap_cnt_r[2]),
.R(1'b0));
FDRE \wrap_cnt_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_2 [3]),
.Q(wrap_cnt_r[3]),
.R(1'b0));
FDRE \wrap_second_len_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_1 [0]),
.Q(\wrap_second_len_r_reg[3]_0 [0]),
.R(1'b0));
FDRE \wrap_second_len_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_1 [1]),
.Q(\wrap_second_len_r_reg[3]_0 [1]),
.R(1'b0));
FDRE \wrap_second_len_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_1 [2]),
.Q(\wrap_second_len_r_reg[3]_0 [2]),
.R(1'b0));
FDRE \wrap_second_len_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_1 [3]),
.Q(\wrap_second_len_r_reg[3]_0 [3]),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "axi_protocol_converter_v2_1_13_b2s_wrap_cmd" *)
module zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_wrap_cmd_3
(wrap_next_pending,
sel_first_reg_0,
m_axi_araddr,
\axaddr_offset_r_reg[3]_0 ,
\wrap_second_len_r_reg[3]_0 ,
aclk,
sel_first_reg_1,
E,
\m_payload_i_reg[47] ,
\state_reg[0]_rep ,
si_rs_arvalid,
\state_reg[1]_rep ,
\m_payload_i_reg[46] ,
\state_reg[1]_rep_0 ,
\axaddr_incr_reg[11] ,
\m_payload_i_reg[38] ,
\axaddr_incr_reg[3] ,
sel_first_reg_2,
sel_first_reg_3,
\axaddr_offset_r_reg[3]_1 ,
\wrap_second_len_r_reg[3]_1 ,
m_valid_i_reg,
\wrap_second_len_r_reg[3]_2 ,
\m_payload_i_reg[6] );
output wrap_next_pending;
output sel_first_reg_0;
output [11:0]m_axi_araddr;
output [3:0]\axaddr_offset_r_reg[3]_0 ;
output [3:0]\wrap_second_len_r_reg[3]_0 ;
input aclk;
input sel_first_reg_1;
input [0:0]E;
input [18:0]\m_payload_i_reg[47] ;
input \state_reg[0]_rep ;
input si_rs_arvalid;
input \state_reg[1]_rep ;
input \m_payload_i_reg[46] ;
input \state_reg[1]_rep_0 ;
input [6:0]\axaddr_incr_reg[11] ;
input \m_payload_i_reg[38] ;
input [2:0]\axaddr_incr_reg[3] ;
input sel_first_reg_2;
input sel_first_reg_3;
input [3:0]\axaddr_offset_r_reg[3]_1 ;
input [3:0]\wrap_second_len_r_reg[3]_1 ;
input [0:0]m_valid_i_reg;
input [3:0]\wrap_second_len_r_reg[3]_2 ;
input [6:0]\m_payload_i_reg[6] ;
wire [0:0]E;
wire aclk;
wire [6:0]\axaddr_incr_reg[11] ;
wire [2:0]\axaddr_incr_reg[3] ;
wire [3:0]\axaddr_offset_r_reg[3]_0 ;
wire [3:0]\axaddr_offset_r_reg[3]_1 ;
wire \axaddr_wrap[0]_i_1__0_n_0 ;
wire \axaddr_wrap[10]_i_1__0_n_0 ;
wire \axaddr_wrap[11]_i_1__0_n_0 ;
wire \axaddr_wrap[11]_i_2__0_n_0 ;
wire \axaddr_wrap[11]_i_4__0_n_0 ;
wire \axaddr_wrap[11]_i_5__0_n_0 ;
wire \axaddr_wrap[11]_i_6__0_n_0 ;
wire \axaddr_wrap[11]_i_7__0_n_0 ;
wire \axaddr_wrap[11]_i_8__0_n_0 ;
wire \axaddr_wrap[1]_i_1__0_n_0 ;
wire \axaddr_wrap[2]_i_1__0_n_0 ;
wire \axaddr_wrap[3]_i_1__0_n_0 ;
wire \axaddr_wrap[3]_i_3_n_0 ;
wire \axaddr_wrap[3]_i_4_n_0 ;
wire \axaddr_wrap[3]_i_5_n_0 ;
wire \axaddr_wrap[3]_i_6_n_0 ;
wire \axaddr_wrap[4]_i_1__0_n_0 ;
wire \axaddr_wrap[5]_i_1__0_n_0 ;
wire \axaddr_wrap[6]_i_1__0_n_0 ;
wire \axaddr_wrap[7]_i_1__0_n_0 ;
wire \axaddr_wrap[7]_i_3__0_n_0 ;
wire \axaddr_wrap[7]_i_4__0_n_0 ;
wire \axaddr_wrap[7]_i_5__0_n_0 ;
wire \axaddr_wrap[7]_i_6__0_n_0 ;
wire \axaddr_wrap[8]_i_1__0_n_0 ;
wire \axaddr_wrap[9]_i_1__0_n_0 ;
wire \axaddr_wrap_reg[11]_i_3__0_n_1 ;
wire \axaddr_wrap_reg[11]_i_3__0_n_2 ;
wire \axaddr_wrap_reg[11]_i_3__0_n_3 ;
wire \axaddr_wrap_reg[11]_i_3__0_n_4 ;
wire \axaddr_wrap_reg[11]_i_3__0_n_5 ;
wire \axaddr_wrap_reg[11]_i_3__0_n_6 ;
wire \axaddr_wrap_reg[11]_i_3__0_n_7 ;
wire \axaddr_wrap_reg[3]_i_2__0_n_0 ;
wire \axaddr_wrap_reg[3]_i_2__0_n_1 ;
wire \axaddr_wrap_reg[3]_i_2__0_n_2 ;
wire \axaddr_wrap_reg[3]_i_2__0_n_3 ;
wire \axaddr_wrap_reg[3]_i_2__0_n_4 ;
wire \axaddr_wrap_reg[3]_i_2__0_n_5 ;
wire \axaddr_wrap_reg[3]_i_2__0_n_6 ;
wire \axaddr_wrap_reg[3]_i_2__0_n_7 ;
wire \axaddr_wrap_reg[7]_i_2__0_n_0 ;
wire \axaddr_wrap_reg[7]_i_2__0_n_1 ;
wire \axaddr_wrap_reg[7]_i_2__0_n_2 ;
wire \axaddr_wrap_reg[7]_i_2__0_n_3 ;
wire \axaddr_wrap_reg[7]_i_2__0_n_4 ;
wire \axaddr_wrap_reg[7]_i_2__0_n_5 ;
wire \axaddr_wrap_reg[7]_i_2__0_n_6 ;
wire \axaddr_wrap_reg[7]_i_2__0_n_7 ;
wire \axaddr_wrap_reg_n_0_[0] ;
wire \axaddr_wrap_reg_n_0_[10] ;
wire \axaddr_wrap_reg_n_0_[11] ;
wire \axaddr_wrap_reg_n_0_[1] ;
wire \axaddr_wrap_reg_n_0_[2] ;
wire \axaddr_wrap_reg_n_0_[3] ;
wire \axaddr_wrap_reg_n_0_[4] ;
wire \axaddr_wrap_reg_n_0_[5] ;
wire \axaddr_wrap_reg_n_0_[6] ;
wire \axaddr_wrap_reg_n_0_[7] ;
wire \axaddr_wrap_reg_n_0_[8] ;
wire \axaddr_wrap_reg_n_0_[9] ;
wire \axlen_cnt[0]_i_1__2_n_0 ;
wire \axlen_cnt[1]_i_1__2_n_0 ;
wire \axlen_cnt[2]_i_1__2_n_0 ;
wire \axlen_cnt[3]_i_1__2_n_0 ;
wire \axlen_cnt_reg_n_0_[0] ;
wire \axlen_cnt_reg_n_0_[1] ;
wire \axlen_cnt_reg_n_0_[2] ;
wire \axlen_cnt_reg_n_0_[3] ;
wire [11:0]m_axi_araddr;
wire \m_payload_i_reg[38] ;
wire \m_payload_i_reg[46] ;
wire [18:0]\m_payload_i_reg[47] ;
wire [6:0]\m_payload_i_reg[6] ;
wire [0:0]m_valid_i_reg;
wire next_pending_r_i_3__2_n_0;
wire next_pending_r_reg_n_0;
wire sel_first_reg_0;
wire sel_first_reg_1;
wire sel_first_reg_2;
wire sel_first_reg_3;
wire si_rs_arvalid;
wire \state_reg[0]_rep ;
wire \state_reg[1]_rep ;
wire \state_reg[1]_rep_0 ;
wire \wrap_boundary_axaddr_r_reg_n_0_[0] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[10] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[11] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[1] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[2] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[3] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[4] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[5] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[6] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[7] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[8] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[9] ;
wire \wrap_cnt_r_reg_n_0_[0] ;
wire \wrap_cnt_r_reg_n_0_[1] ;
wire \wrap_cnt_r_reg_n_0_[2] ;
wire \wrap_cnt_r_reg_n_0_[3] ;
wire wrap_next_pending;
wire [3:0]\wrap_second_len_r_reg[3]_0 ;
wire [3:0]\wrap_second_len_r_reg[3]_1 ;
wire [3:0]\wrap_second_len_r_reg[3]_2 ;
wire [3:3]\NLW_axaddr_wrap_reg[11]_i_3__0_CO_UNCONNECTED ;
FDRE \axaddr_offset_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\axaddr_offset_r_reg[3]_1 [0]),
.Q(\axaddr_offset_r_reg[3]_0 [0]),
.R(1'b0));
FDRE \axaddr_offset_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\axaddr_offset_r_reg[3]_1 [1]),
.Q(\axaddr_offset_r_reg[3]_0 [1]),
.R(1'b0));
FDRE \axaddr_offset_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\axaddr_offset_r_reg[3]_1 [2]),
.Q(\axaddr_offset_r_reg[3]_0 [2]),
.R(1'b0));
FDRE \axaddr_offset_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(\axaddr_offset_r_reg[3]_1 [3]),
.Q(\axaddr_offset_r_reg[3]_0 [3]),
.R(1'b0));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[0]_i_1__0
(.I0(\wrap_boundary_axaddr_r_reg_n_0_[0] ),
.I1(\axaddr_wrap[11]_i_2__0_n_0 ),
.I2(\axaddr_wrap_reg[3]_i_2__0_n_7 ),
.I3(\state_reg[1]_rep_0 ),
.I4(\m_payload_i_reg[47] [0]),
.O(\axaddr_wrap[0]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[10]_i_1__0
(.I0(\wrap_boundary_axaddr_r_reg_n_0_[10] ),
.I1(\axaddr_wrap[11]_i_2__0_n_0 ),
.I2(\axaddr_wrap_reg[11]_i_3__0_n_5 ),
.I3(\state_reg[1]_rep_0 ),
.I4(\m_payload_i_reg[47] [10]),
.O(\axaddr_wrap[10]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[11]_i_1__0
(.I0(\wrap_boundary_axaddr_r_reg_n_0_[11] ),
.I1(\axaddr_wrap[11]_i_2__0_n_0 ),
.I2(\axaddr_wrap_reg[11]_i_3__0_n_4 ),
.I3(\state_reg[1]_rep_0 ),
.I4(\m_payload_i_reg[47] [11]),
.O(\axaddr_wrap[11]_i_1__0_n_0 ));
LUT3 #(
.INIT(8'h41))
\axaddr_wrap[11]_i_2__0
(.I0(\axaddr_wrap[11]_i_4__0_n_0 ),
.I1(\wrap_cnt_r_reg_n_0_[3] ),
.I2(\axlen_cnt_reg_n_0_[3] ),
.O(\axaddr_wrap[11]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'h6FF6FFFFFFFF6FF6))
\axaddr_wrap[11]_i_4__0
(.I0(\wrap_cnt_r_reg_n_0_[0] ),
.I1(\axlen_cnt_reg_n_0_[0] ),
.I2(\axlen_cnt_reg_n_0_[1] ),
.I3(\wrap_cnt_r_reg_n_0_[1] ),
.I4(\axlen_cnt_reg_n_0_[2] ),
.I5(\wrap_cnt_r_reg_n_0_[2] ),
.O(\axaddr_wrap[11]_i_4__0_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_wrap[11]_i_5__0
(.I0(\axaddr_wrap_reg_n_0_[11] ),
.O(\axaddr_wrap[11]_i_5__0_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_wrap[11]_i_6__0
(.I0(\axaddr_wrap_reg_n_0_[10] ),
.O(\axaddr_wrap[11]_i_6__0_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_wrap[11]_i_7__0
(.I0(\axaddr_wrap_reg_n_0_[9] ),
.O(\axaddr_wrap[11]_i_7__0_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_wrap[11]_i_8__0
(.I0(\axaddr_wrap_reg_n_0_[8] ),
.O(\axaddr_wrap[11]_i_8__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[1]_i_1__0
(.I0(\wrap_boundary_axaddr_r_reg_n_0_[1] ),
.I1(\axaddr_wrap[11]_i_2__0_n_0 ),
.I2(\axaddr_wrap_reg[3]_i_2__0_n_6 ),
.I3(\state_reg[1]_rep_0 ),
.I4(\m_payload_i_reg[47] [1]),
.O(\axaddr_wrap[1]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[2]_i_1__0
(.I0(\wrap_boundary_axaddr_r_reg_n_0_[2] ),
.I1(\axaddr_wrap[11]_i_2__0_n_0 ),
.I2(\axaddr_wrap_reg[3]_i_2__0_n_5 ),
.I3(\state_reg[1]_rep_0 ),
.I4(\m_payload_i_reg[47] [2]),
.O(\axaddr_wrap[2]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[3]_i_1__0
(.I0(\wrap_boundary_axaddr_r_reg_n_0_[3] ),
.I1(\axaddr_wrap[11]_i_2__0_n_0 ),
.I2(\axaddr_wrap_reg[3]_i_2__0_n_4 ),
.I3(\state_reg[1]_rep_0 ),
.I4(\m_payload_i_reg[47] [3]),
.O(\axaddr_wrap[3]_i_1__0_n_0 ));
LUT3 #(
.INIT(8'h6A))
\axaddr_wrap[3]_i_3
(.I0(\axaddr_wrap_reg_n_0_[3] ),
.I1(\m_payload_i_reg[47] [12]),
.I2(\m_payload_i_reg[47] [13]),
.O(\axaddr_wrap[3]_i_3_n_0 ));
LUT3 #(
.INIT(8'h9A))
\axaddr_wrap[3]_i_4
(.I0(\axaddr_wrap_reg_n_0_[2] ),
.I1(\m_payload_i_reg[47] [12]),
.I2(\m_payload_i_reg[47] [13]),
.O(\axaddr_wrap[3]_i_4_n_0 ));
LUT3 #(
.INIT(8'h9A))
\axaddr_wrap[3]_i_5
(.I0(\axaddr_wrap_reg_n_0_[1] ),
.I1(\m_payload_i_reg[47] [13]),
.I2(\m_payload_i_reg[47] [12]),
.O(\axaddr_wrap[3]_i_5_n_0 ));
LUT3 #(
.INIT(8'hA9))
\axaddr_wrap[3]_i_6
(.I0(\axaddr_wrap_reg_n_0_[0] ),
.I1(\m_payload_i_reg[47] [12]),
.I2(\m_payload_i_reg[47] [13]),
.O(\axaddr_wrap[3]_i_6_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[4]_i_1__0
(.I0(\wrap_boundary_axaddr_r_reg_n_0_[4] ),
.I1(\axaddr_wrap[11]_i_2__0_n_0 ),
.I2(\axaddr_wrap_reg[7]_i_2__0_n_7 ),
.I3(\state_reg[1]_rep_0 ),
.I4(\m_payload_i_reg[47] [4]),
.O(\axaddr_wrap[4]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[5]_i_1__0
(.I0(\wrap_boundary_axaddr_r_reg_n_0_[5] ),
.I1(\axaddr_wrap[11]_i_2__0_n_0 ),
.I2(\axaddr_wrap_reg[7]_i_2__0_n_6 ),
.I3(\state_reg[1]_rep_0 ),
.I4(\m_payload_i_reg[47] [5]),
.O(\axaddr_wrap[5]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[6]_i_1__0
(.I0(\wrap_boundary_axaddr_r_reg_n_0_[6] ),
.I1(\axaddr_wrap[11]_i_2__0_n_0 ),
.I2(\axaddr_wrap_reg[7]_i_2__0_n_5 ),
.I3(\state_reg[1]_rep_0 ),
.I4(\m_payload_i_reg[47] [6]),
.O(\axaddr_wrap[6]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[7]_i_1__0
(.I0(\wrap_boundary_axaddr_r_reg_n_0_[7] ),
.I1(\axaddr_wrap[11]_i_2__0_n_0 ),
.I2(\axaddr_wrap_reg[7]_i_2__0_n_4 ),
.I3(\state_reg[1]_rep_0 ),
.I4(\m_payload_i_reg[47] [7]),
.O(\axaddr_wrap[7]_i_1__0_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_wrap[7]_i_3__0
(.I0(\axaddr_wrap_reg_n_0_[7] ),
.O(\axaddr_wrap[7]_i_3__0_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_wrap[7]_i_4__0
(.I0(\axaddr_wrap_reg_n_0_[6] ),
.O(\axaddr_wrap[7]_i_4__0_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_wrap[7]_i_5__0
(.I0(\axaddr_wrap_reg_n_0_[5] ),
.O(\axaddr_wrap[7]_i_5__0_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_wrap[7]_i_6__0
(.I0(\axaddr_wrap_reg_n_0_[4] ),
.O(\axaddr_wrap[7]_i_6__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[8]_i_1__0
(.I0(\wrap_boundary_axaddr_r_reg_n_0_[8] ),
.I1(\axaddr_wrap[11]_i_2__0_n_0 ),
.I2(\axaddr_wrap_reg[11]_i_3__0_n_7 ),
.I3(\state_reg[1]_rep_0 ),
.I4(\m_payload_i_reg[47] [8]),
.O(\axaddr_wrap[8]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[9]_i_1__0
(.I0(\wrap_boundary_axaddr_r_reg_n_0_[9] ),
.I1(\axaddr_wrap[11]_i_2__0_n_0 ),
.I2(\axaddr_wrap_reg[11]_i_3__0_n_6 ),
.I3(\state_reg[1]_rep_0 ),
.I4(\m_payload_i_reg[47] [9]),
.O(\axaddr_wrap[9]_i_1__0_n_0 ));
FDRE \axaddr_wrap_reg[0]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[0]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[0] ),
.R(1'b0));
FDRE \axaddr_wrap_reg[10]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[10]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[10] ),
.R(1'b0));
FDRE \axaddr_wrap_reg[11]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[11]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[11] ),
.R(1'b0));
CARRY4 \axaddr_wrap_reg[11]_i_3__0
(.CI(\axaddr_wrap_reg[7]_i_2__0_n_0 ),
.CO({\NLW_axaddr_wrap_reg[11]_i_3__0_CO_UNCONNECTED [3],\axaddr_wrap_reg[11]_i_3__0_n_1 ,\axaddr_wrap_reg[11]_i_3__0_n_2 ,\axaddr_wrap_reg[11]_i_3__0_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\axaddr_wrap_reg[11]_i_3__0_n_4 ,\axaddr_wrap_reg[11]_i_3__0_n_5 ,\axaddr_wrap_reg[11]_i_3__0_n_6 ,\axaddr_wrap_reg[11]_i_3__0_n_7 }),
.S({\axaddr_wrap[11]_i_5__0_n_0 ,\axaddr_wrap[11]_i_6__0_n_0 ,\axaddr_wrap[11]_i_7__0_n_0 ,\axaddr_wrap[11]_i_8__0_n_0 }));
FDRE \axaddr_wrap_reg[1]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[1]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[1] ),
.R(1'b0));
FDRE \axaddr_wrap_reg[2]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[2]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[2] ),
.R(1'b0));
FDRE \axaddr_wrap_reg[3]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[3]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[3] ),
.R(1'b0));
CARRY4 \axaddr_wrap_reg[3]_i_2__0
(.CI(1'b0),
.CO({\axaddr_wrap_reg[3]_i_2__0_n_0 ,\axaddr_wrap_reg[3]_i_2__0_n_1 ,\axaddr_wrap_reg[3]_i_2__0_n_2 ,\axaddr_wrap_reg[3]_i_2__0_n_3 }),
.CYINIT(1'b0),
.DI({\axaddr_wrap_reg_n_0_[3] ,\axaddr_wrap_reg_n_0_[2] ,\axaddr_wrap_reg_n_0_[1] ,\axaddr_wrap_reg_n_0_[0] }),
.O({\axaddr_wrap_reg[3]_i_2__0_n_4 ,\axaddr_wrap_reg[3]_i_2__0_n_5 ,\axaddr_wrap_reg[3]_i_2__0_n_6 ,\axaddr_wrap_reg[3]_i_2__0_n_7 }),
.S({\axaddr_wrap[3]_i_3_n_0 ,\axaddr_wrap[3]_i_4_n_0 ,\axaddr_wrap[3]_i_5_n_0 ,\axaddr_wrap[3]_i_6_n_0 }));
FDRE \axaddr_wrap_reg[4]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[4]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[4] ),
.R(1'b0));
FDRE \axaddr_wrap_reg[5]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[5]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[5] ),
.R(1'b0));
FDRE \axaddr_wrap_reg[6]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[6]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[6] ),
.R(1'b0));
FDRE \axaddr_wrap_reg[7]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[7]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[7] ),
.R(1'b0));
CARRY4 \axaddr_wrap_reg[7]_i_2__0
(.CI(\axaddr_wrap_reg[3]_i_2__0_n_0 ),
.CO({\axaddr_wrap_reg[7]_i_2__0_n_0 ,\axaddr_wrap_reg[7]_i_2__0_n_1 ,\axaddr_wrap_reg[7]_i_2__0_n_2 ,\axaddr_wrap_reg[7]_i_2__0_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\axaddr_wrap_reg[7]_i_2__0_n_4 ,\axaddr_wrap_reg[7]_i_2__0_n_5 ,\axaddr_wrap_reg[7]_i_2__0_n_6 ,\axaddr_wrap_reg[7]_i_2__0_n_7 }),
.S({\axaddr_wrap[7]_i_3__0_n_0 ,\axaddr_wrap[7]_i_4__0_n_0 ,\axaddr_wrap[7]_i_5__0_n_0 ,\axaddr_wrap[7]_i_6__0_n_0 }));
FDRE \axaddr_wrap_reg[8]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[8]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[8] ),
.R(1'b0));
FDRE \axaddr_wrap_reg[9]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[9]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[9] ),
.R(1'b0));
LUT6 #(
.INIT(64'hA3A3A3A3A3A3A3A0))
\axlen_cnt[0]_i_1__2
(.I0(\m_payload_i_reg[47] [15]),
.I1(\axlen_cnt_reg_n_0_[0] ),
.I2(E),
.I3(\axlen_cnt_reg_n_0_[3] ),
.I4(\axlen_cnt_reg_n_0_[2] ),
.I5(\axlen_cnt_reg_n_0_[1] ),
.O(\axlen_cnt[0]_i_1__2_n_0 ));
LUT6 #(
.INIT(64'hFFFF999800009998))
\axlen_cnt[1]_i_1__2
(.I0(\axlen_cnt_reg_n_0_[1] ),
.I1(\axlen_cnt_reg_n_0_[0] ),
.I2(\axlen_cnt_reg_n_0_[3] ),
.I3(\axlen_cnt_reg_n_0_[2] ),
.I4(E),
.I5(\m_payload_i_reg[47] [16]),
.O(\axlen_cnt[1]_i_1__2_n_0 ));
LUT6 #(
.INIT(64'hFFFFA9A80000A9A8))
\axlen_cnt[2]_i_1__2
(.I0(\axlen_cnt_reg_n_0_[2] ),
.I1(\axlen_cnt_reg_n_0_[0] ),
.I2(\axlen_cnt_reg_n_0_[1] ),
.I3(\axlen_cnt_reg_n_0_[3] ),
.I4(E),
.I5(\m_payload_i_reg[47] [17]),
.O(\axlen_cnt[2]_i_1__2_n_0 ));
LUT6 #(
.INIT(64'hFFFFAAA80000AAA8))
\axlen_cnt[3]_i_1__2
(.I0(\axlen_cnt_reg_n_0_[3] ),
.I1(\axlen_cnt_reg_n_0_[2] ),
.I2(\axlen_cnt_reg_n_0_[1] ),
.I3(\axlen_cnt_reg_n_0_[0] ),
.I4(E),
.I5(\m_payload_i_reg[47] [18]),
.O(\axlen_cnt[3]_i_1__2_n_0 ));
FDRE \axlen_cnt_reg[0]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[0]_i_1__2_n_0 ),
.Q(\axlen_cnt_reg_n_0_[0] ),
.R(1'b0));
FDRE \axlen_cnt_reg[1]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[1]_i_1__2_n_0 ),
.Q(\axlen_cnt_reg_n_0_[1] ),
.R(1'b0));
FDRE \axlen_cnt_reg[2]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[2]_i_1__2_n_0 ),
.Q(\axlen_cnt_reg_n_0_[2] ),
.R(1'b0));
FDRE \axlen_cnt_reg[3]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[3]_i_1__2_n_0 ),
.Q(\axlen_cnt_reg_n_0_[3] ),
.R(1'b0));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_araddr[0]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[0] ),
.I2(\m_payload_i_reg[47] [14]),
.I3(\axaddr_incr_reg[3] [0]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [0]),
.O(m_axi_araddr[0]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_araddr[10]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[10] ),
.I2(\m_payload_i_reg[47] [14]),
.I3(\axaddr_incr_reg[11] [5]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [10]),
.O(m_axi_araddr[10]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_araddr[11]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[11] ),
.I2(\m_payload_i_reg[47] [14]),
.I3(\axaddr_incr_reg[11] [6]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [11]),
.O(m_axi_araddr[11]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_araddr[1]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[1] ),
.I2(\m_payload_i_reg[47] [14]),
.I3(\axaddr_incr_reg[3] [1]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [1]),
.O(m_axi_araddr[1]));
LUT5 #(
.INIT(32'hB8FFB800))
\m_axi_araddr[2]_INST_0
(.I0(\m_payload_i_reg[47] [2]),
.I1(sel_first_reg_0),
.I2(\axaddr_wrap_reg_n_0_[2] ),
.I3(\m_payload_i_reg[47] [14]),
.I4(sel_first_reg_3),
.O(m_axi_araddr[2]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_araddr[3]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[3] ),
.I2(\m_payload_i_reg[47] [14]),
.I3(\axaddr_incr_reg[3] [2]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [3]),
.O(m_axi_araddr[3]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_araddr[4]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[4] ),
.I2(\m_payload_i_reg[47] [14]),
.I3(\axaddr_incr_reg[11] [0]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [4]),
.O(m_axi_araddr[4]));
LUT5 #(
.INIT(32'hB8FFB800))
\m_axi_araddr[5]_INST_0
(.I0(\m_payload_i_reg[47] [5]),
.I1(sel_first_reg_0),
.I2(\axaddr_wrap_reg_n_0_[5] ),
.I3(\m_payload_i_reg[47] [14]),
.I4(sel_first_reg_2),
.O(m_axi_araddr[5]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_araddr[6]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[6] ),
.I2(\m_payload_i_reg[47] [14]),
.I3(\axaddr_incr_reg[11] [1]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [6]),
.O(m_axi_araddr[6]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_araddr[7]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[7] ),
.I2(\m_payload_i_reg[47] [14]),
.I3(\axaddr_incr_reg[11] [2]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [7]),
.O(m_axi_araddr[7]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_araddr[8]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[8] ),
.I2(\m_payload_i_reg[47] [14]),
.I3(\axaddr_incr_reg[11] [3]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [8]),
.O(m_axi_araddr[8]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_araddr[9]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[9] ),
.I2(\m_payload_i_reg[47] [14]),
.I3(\axaddr_incr_reg[11] [4]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [9]),
.O(m_axi_araddr[9]));
LUT5 #(
.INIT(32'hFD55FC0C))
next_pending_r_i_1__1
(.I0(\m_payload_i_reg[46] ),
.I1(next_pending_r_reg_n_0),
.I2(\state_reg[1]_rep_0 ),
.I3(next_pending_r_i_3__2_n_0),
.I4(E),
.O(wrap_next_pending));
LUT6 #(
.INIT(64'hFBFBFBFBFBFBFB00))
next_pending_r_i_3__2
(.I0(\state_reg[0]_rep ),
.I1(si_rs_arvalid),
.I2(\state_reg[1]_rep ),
.I3(\axlen_cnt_reg_n_0_[3] ),
.I4(\axlen_cnt_reg_n_0_[2] ),
.I5(\axlen_cnt_reg_n_0_[1] ),
.O(next_pending_r_i_3__2_n_0));
FDRE next_pending_r_reg
(.C(aclk),
.CE(1'b1),
.D(wrap_next_pending),
.Q(next_pending_r_reg_n_0),
.R(1'b0));
FDRE sel_first_reg
(.C(aclk),
.CE(1'b1),
.D(sel_first_reg_1),
.Q(sel_first_reg_0),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[0]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [0]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[0] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[10]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[47] [10]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[10] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[11]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[47] [11]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[11] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[1]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [1]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[1] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[2]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [2]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[2] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[3]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [3]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[3] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[4]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [4]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[4] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[5]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [5]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[5] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[6]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [6]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[6] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[7]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[47] [7]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[7] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[8]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[47] [8]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[8] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[9]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[47] [9]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[9] ),
.R(1'b0));
FDRE \wrap_cnt_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_2 [0]),
.Q(\wrap_cnt_r_reg_n_0_[0] ),
.R(1'b0));
FDRE \wrap_cnt_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_2 [1]),
.Q(\wrap_cnt_r_reg_n_0_[1] ),
.R(1'b0));
FDRE \wrap_cnt_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_2 [2]),
.Q(\wrap_cnt_r_reg_n_0_[2] ),
.R(1'b0));
FDRE \wrap_cnt_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_2 [3]),
.Q(\wrap_cnt_r_reg_n_0_[3] ),
.R(1'b0));
FDRE \wrap_second_len_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_1 [0]),
.Q(\wrap_second_len_r_reg[3]_0 [0]),
.R(1'b0));
FDRE \wrap_second_len_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_1 [1]),
.Q(\wrap_second_len_r_reg[3]_0 [1]),
.R(1'b0));
FDRE \wrap_second_len_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_1 [2]),
.Q(\wrap_second_len_r_reg[3]_0 [2]),
.R(1'b0));
FDRE \wrap_second_len_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_1 [3]),
.Q(\wrap_second_len_r_reg[3]_0 [3]),
.R(1'b0));
endmodule
module zqynq_lab_1_design_auto_pc_0_axi_register_slice_v2_1_13_axi_register_slice
(s_axi_awready,
s_axi_arready,
si_rs_awvalid,
s_axi_bvalid,
si_rs_bready,
si_rs_arvalid,
s_axi_rvalid,
si_rs_rready,
Q,
\s_arid_r_reg[11] ,
\axaddr_incr_reg[11] ,
CO,
O,
\axaddr_incr_reg[7] ,
\axaddr_incr_reg[11]_0 ,
\axaddr_incr_reg[7]_0 ,
\axaddr_incr_reg[3] ,
D,
\wrap_second_len_r_reg[3] ,
\wrap_cnt_r_reg[3] ,
axaddr_offset,
\axlen_cnt_reg[3] ,
next_pending_r_reg,
next_pending_r_reg_0,
\wrap_cnt_r_reg[3]_0 ,
\wrap_second_len_r_reg[3]_0 ,
\wrap_cnt_r_reg[3]_1 ,
axaddr_offset_0,
\axlen_cnt_reg[3]_0 ,
next_pending_r_reg_1,
next_pending_r_reg_2,
\cnt_read_reg[3]_rep__0 ,
\axaddr_offset_r_reg[3] ,
\wrap_boundary_axaddr_r_reg[6] ,
\axaddr_offset_r_reg[3]_0 ,
\wrap_boundary_axaddr_r_reg[6]_0 ,
\m_axi_awaddr[10] ,
\m_axi_araddr[10] ,
\s_axi_bid[11] ,
\s_axi_rid[11] ,
aclk,
aresetn,
\state_reg[0]_rep ,
\state_reg[1]_rep ,
\state_reg[1] ,
\cnt_read_reg[4]_rep__0 ,
s_axi_rready,
b_push,
s_axi_awvalid,
S,
\m_payload_i_reg[3] ,
\wrap_second_len_r_reg[3]_1 ,
\state_reg[1]_0 ,
wrap_second_len,
\axaddr_offset_r_reg[3]_1 ,
\state_reg[1]_rep_0 ,
\axaddr_offset_r_reg[3]_2 ,
\wrap_second_len_r_reg[3]_2 ,
wrap_second_len_1,
\axaddr_offset_r_reg[3]_3 ,
\state_reg[1]_rep_1 ,
\axaddr_offset_r_reg[3]_4 ,
\state_reg[0]_rep_0 ,
\state_reg[1]_rep_2 ,
sel_first,
sel_first_2,
si_rs_bvalid,
s_axi_bready,
s_axi_arvalid,
s_axi_awid,
s_axi_awlen,
s_axi_awburst,
s_axi_awsize,
s_axi_awprot,
s_axi_awaddr,
s_axi_arid,
s_axi_arlen,
s_axi_arburst,
s_axi_arsize,
s_axi_arprot,
s_axi_araddr,
out,
\s_bresp_acc_reg[1] ,
r_push_r_reg,
\cnt_read_reg[4] ,
axaddr_incr_reg,
\axaddr_incr_reg[3]_0 ,
E,
m_valid_i_reg);
output s_axi_awready;
output s_axi_arready;
output si_rs_awvalid;
output s_axi_bvalid;
output si_rs_bready;
output si_rs_arvalid;
output s_axi_rvalid;
output si_rs_rready;
output [58:0]Q;
output [58:0]\s_arid_r_reg[11] ;
output [7:0]\axaddr_incr_reg[11] ;
output [0:0]CO;
output [3:0]O;
output [3:0]\axaddr_incr_reg[7] ;
output [3:0]\axaddr_incr_reg[11]_0 ;
output [0:0]\axaddr_incr_reg[7]_0 ;
output [3:0]\axaddr_incr_reg[3] ;
output [2:0]D;
output [2:0]\wrap_second_len_r_reg[3] ;
output \wrap_cnt_r_reg[3] ;
output [2:0]axaddr_offset;
output \axlen_cnt_reg[3] ;
output next_pending_r_reg;
output next_pending_r_reg_0;
output [2:0]\wrap_cnt_r_reg[3]_0 ;
output [2:0]\wrap_second_len_r_reg[3]_0 ;
output \wrap_cnt_r_reg[3]_1 ;
output [2:0]axaddr_offset_0;
output \axlen_cnt_reg[3]_0 ;
output next_pending_r_reg_1;
output next_pending_r_reg_2;
output \cnt_read_reg[3]_rep__0 ;
output \axaddr_offset_r_reg[3] ;
output [6:0]\wrap_boundary_axaddr_r_reg[6] ;
output \axaddr_offset_r_reg[3]_0 ;
output [6:0]\wrap_boundary_axaddr_r_reg[6]_0 ;
output \m_axi_awaddr[10] ;
output \m_axi_araddr[10] ;
output [13:0]\s_axi_bid[11] ;
output [46:0]\s_axi_rid[11] ;
input aclk;
input aresetn;
input \state_reg[0]_rep ;
input \state_reg[1]_rep ;
input [1:0]\state_reg[1] ;
input \cnt_read_reg[4]_rep__0 ;
input s_axi_rready;
input b_push;
input s_axi_awvalid;
input [3:0]S;
input [3:0]\m_payload_i_reg[3] ;
input [2:0]\wrap_second_len_r_reg[3]_1 ;
input [1:0]\state_reg[1]_0 ;
input [0:0]wrap_second_len;
input [0:0]\axaddr_offset_r_reg[3]_1 ;
input \state_reg[1]_rep_0 ;
input [3:0]\axaddr_offset_r_reg[3]_2 ;
input [2:0]\wrap_second_len_r_reg[3]_2 ;
input [0:0]wrap_second_len_1;
input [0:0]\axaddr_offset_r_reg[3]_3 ;
input \state_reg[1]_rep_1 ;
input [3:0]\axaddr_offset_r_reg[3]_4 ;
input \state_reg[0]_rep_0 ;
input \state_reg[1]_rep_2 ;
input sel_first;
input sel_first_2;
input si_rs_bvalid;
input s_axi_bready;
input s_axi_arvalid;
input [11:0]s_axi_awid;
input [7:0]s_axi_awlen;
input [1:0]s_axi_awburst;
input [1:0]s_axi_awsize;
input [2:0]s_axi_awprot;
input [31:0]s_axi_awaddr;
input [11:0]s_axi_arid;
input [7:0]s_axi_arlen;
input [1:0]s_axi_arburst;
input [1:0]s_axi_arsize;
input [2:0]s_axi_arprot;
input [31:0]s_axi_araddr;
input [11:0]out;
input [1:0]\s_bresp_acc_reg[1] ;
input [12:0]r_push_r_reg;
input [33:0]\cnt_read_reg[4] ;
input [3:0]axaddr_incr_reg;
input [3:0]\axaddr_incr_reg[3]_0 ;
input [0:0]E;
input [0:0]m_valid_i_reg;
wire [0:0]CO;
wire [2:0]D;
wire [0:0]E;
wire [3:0]O;
wire [58:0]Q;
wire [3:0]S;
wire aclk;
wire ar_pipe_n_2;
wire aresetn;
wire aw_pipe_n_1;
wire aw_pipe_n_97;
wire [3:0]axaddr_incr_reg;
wire [7:0]\axaddr_incr_reg[11] ;
wire [3:0]\axaddr_incr_reg[11]_0 ;
wire [3:0]\axaddr_incr_reg[3] ;
wire [3:0]\axaddr_incr_reg[3]_0 ;
wire [3:0]\axaddr_incr_reg[7] ;
wire [0:0]\axaddr_incr_reg[7]_0 ;
wire [2:0]axaddr_offset;
wire [2:0]axaddr_offset_0;
wire \axaddr_offset_r_reg[3] ;
wire \axaddr_offset_r_reg[3]_0 ;
wire [0:0]\axaddr_offset_r_reg[3]_1 ;
wire [3:0]\axaddr_offset_r_reg[3]_2 ;
wire [0:0]\axaddr_offset_r_reg[3]_3 ;
wire [3:0]\axaddr_offset_r_reg[3]_4 ;
wire \axlen_cnt_reg[3] ;
wire \axlen_cnt_reg[3]_0 ;
wire b_push;
wire \cnt_read_reg[3]_rep__0 ;
wire [33:0]\cnt_read_reg[4] ;
wire \cnt_read_reg[4]_rep__0 ;
wire \m_axi_araddr[10] ;
wire \m_axi_awaddr[10] ;
wire [3:0]\m_payload_i_reg[3] ;
wire [0:0]m_valid_i_reg;
wire next_pending_r_reg;
wire next_pending_r_reg_0;
wire next_pending_r_reg_1;
wire next_pending_r_reg_2;
wire [11:0]out;
wire [12:0]r_push_r_reg;
wire [58:0]\s_arid_r_reg[11] ;
wire [31:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [11:0]s_axi_arid;
wire [7:0]s_axi_arlen;
wire [2:0]s_axi_arprot;
wire s_axi_arready;
wire [1:0]s_axi_arsize;
wire s_axi_arvalid;
wire [31:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [11:0]s_axi_awid;
wire [7:0]s_axi_awlen;
wire [2:0]s_axi_awprot;
wire s_axi_awready;
wire [1:0]s_axi_awsize;
wire s_axi_awvalid;
wire [13:0]\s_axi_bid[11] ;
wire s_axi_bready;
wire s_axi_bvalid;
wire [46:0]\s_axi_rid[11] ;
wire s_axi_rready;
wire s_axi_rvalid;
wire [1:0]\s_bresp_acc_reg[1] ;
wire sel_first;
wire sel_first_2;
wire si_rs_arvalid;
wire si_rs_awvalid;
wire si_rs_bready;
wire si_rs_bvalid;
wire si_rs_rready;
wire \state_reg[0]_rep ;
wire \state_reg[0]_rep_0 ;
wire [1:0]\state_reg[1] ;
wire [1:0]\state_reg[1]_0 ;
wire \state_reg[1]_rep ;
wire \state_reg[1]_rep_0 ;
wire \state_reg[1]_rep_1 ;
wire \state_reg[1]_rep_2 ;
wire [6:0]\wrap_boundary_axaddr_r_reg[6] ;
wire [6:0]\wrap_boundary_axaddr_r_reg[6]_0 ;
wire \wrap_cnt_r_reg[3] ;
wire [2:0]\wrap_cnt_r_reg[3]_0 ;
wire \wrap_cnt_r_reg[3]_1 ;
wire [0:0]wrap_second_len;
wire [0:0]wrap_second_len_1;
wire [2:0]\wrap_second_len_r_reg[3] ;
wire [2:0]\wrap_second_len_r_reg[3]_0 ;
wire [2:0]\wrap_second_len_r_reg[3]_1 ;
wire [2:0]\wrap_second_len_r_reg[3]_2 ;
zqynq_lab_1_design_auto_pc_0_axi_register_slice_v2_1_13_axic_register_slice ar_pipe
(.Q(\s_arid_r_reg[11] ),
.aclk(aclk),
.\aresetn_d_reg[0] (aw_pipe_n_1),
.\aresetn_d_reg[0]_0 (aw_pipe_n_97),
.\axaddr_incr_reg[11] (\axaddr_incr_reg[11]_0 ),
.\axaddr_incr_reg[3] (\axaddr_incr_reg[3] ),
.\axaddr_incr_reg[3]_0 (\axaddr_incr_reg[3]_0 ),
.\axaddr_incr_reg[7] (\axaddr_incr_reg[7] ),
.\axaddr_incr_reg[7]_0 (\axaddr_incr_reg[7]_0 ),
.\axaddr_offset_r_reg[0] (axaddr_offset_0[0]),
.\axaddr_offset_r_reg[1] (axaddr_offset_0[1]),
.\axaddr_offset_r_reg[2] (axaddr_offset_0[2]),
.\axaddr_offset_r_reg[3] (\axaddr_offset_r_reg[3]_0 ),
.\axaddr_offset_r_reg[3]_0 (\axaddr_offset_r_reg[3]_3 ),
.\axaddr_offset_r_reg[3]_1 (\axaddr_offset_r_reg[3]_4 ),
.\axlen_cnt_reg[3] (\axlen_cnt_reg[3]_0 ),
.\m_axi_araddr[10] (\m_axi_araddr[10] ),
.\m_payload_i_reg[3]_0 (\m_payload_i_reg[3] ),
.m_valid_i_reg_0(ar_pipe_n_2),
.m_valid_i_reg_1(m_valid_i_reg),
.next_pending_r_reg(next_pending_r_reg_1),
.next_pending_r_reg_0(next_pending_r_reg_2),
.s_axi_araddr(s_axi_araddr),
.s_axi_arburst(s_axi_arburst),
.s_axi_arid(s_axi_arid),
.s_axi_arlen(s_axi_arlen),
.s_axi_arprot(s_axi_arprot),
.s_axi_arready(s_axi_arready),
.s_axi_arsize(s_axi_arsize),
.s_axi_arvalid(s_axi_arvalid),
.s_ready_i_reg_0(si_rs_arvalid),
.sel_first_2(sel_first_2),
.\state_reg[0]_rep (\state_reg[0]_rep_0 ),
.\state_reg[1] (\state_reg[1] ),
.\state_reg[1]_rep (\state_reg[1]_rep_1 ),
.\state_reg[1]_rep_0 (\state_reg[1]_rep_2 ),
.\wrap_boundary_axaddr_r_reg[6] (\wrap_boundary_axaddr_r_reg[6]_0 ),
.\wrap_cnt_r_reg[3] (\wrap_cnt_r_reg[3]_0 ),
.\wrap_cnt_r_reg[3]_0 (\wrap_cnt_r_reg[3]_1 ),
.wrap_second_len_1(wrap_second_len_1),
.\wrap_second_len_r_reg[3] (\wrap_second_len_r_reg[3]_0 ),
.\wrap_second_len_r_reg[3]_0 (\wrap_second_len_r_reg[3]_2 ));
zqynq_lab_1_design_auto_pc_0_axi_register_slice_v2_1_13_axic_register_slice_0 aw_pipe
(.CO(CO),
.D(D),
.E(E),
.O(O),
.Q(Q),
.S(S),
.aclk(aclk),
.aresetn(aresetn),
.\aresetn_d_reg[1]_inv (aw_pipe_n_97),
.\aresetn_d_reg[1]_inv_0 (ar_pipe_n_2),
.axaddr_incr_reg(axaddr_incr_reg),
.\axaddr_incr_reg[11] (\axaddr_incr_reg[11] ),
.\axaddr_offset_r_reg[0] (axaddr_offset[0]),
.\axaddr_offset_r_reg[1] (axaddr_offset[1]),
.\axaddr_offset_r_reg[2] (axaddr_offset[2]),
.\axaddr_offset_r_reg[3] (\axaddr_offset_r_reg[3] ),
.\axaddr_offset_r_reg[3]_0 (\axaddr_offset_r_reg[3]_1 ),
.\axaddr_offset_r_reg[3]_1 (\axaddr_offset_r_reg[3]_2 ),
.\axlen_cnt_reg[3] (\axlen_cnt_reg[3] ),
.b_push(b_push),
.\m_axi_awaddr[10] (\m_axi_awaddr[10] ),
.m_valid_i_reg_0(si_rs_awvalid),
.next_pending_r_reg(next_pending_r_reg),
.next_pending_r_reg_0(next_pending_r_reg_0),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awburst(s_axi_awburst),
.s_axi_awid(s_axi_awid),
.s_axi_awlen(s_axi_awlen),
.s_axi_awprot(s_axi_awprot),
.s_axi_awready(s_axi_awready),
.s_axi_awsize(s_axi_awsize),
.s_axi_awvalid(s_axi_awvalid),
.s_ready_i_reg_0(aw_pipe_n_1),
.sel_first(sel_first),
.\state_reg[0]_rep (\state_reg[0]_rep ),
.\state_reg[1] (\state_reg[1]_0 ),
.\state_reg[1]_rep (\state_reg[1]_rep ),
.\state_reg[1]_rep_0 (\state_reg[1]_rep_0 ),
.\wrap_boundary_axaddr_r_reg[6] (\wrap_boundary_axaddr_r_reg[6] ),
.\wrap_cnt_r_reg[3] (\wrap_cnt_r_reg[3] ),
.wrap_second_len(wrap_second_len),
.\wrap_second_len_r_reg[3] (\wrap_second_len_r_reg[3] ),
.\wrap_second_len_r_reg[3]_0 (\wrap_second_len_r_reg[3]_1 ));
zqynq_lab_1_design_auto_pc_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1 b_pipe
(.aclk(aclk),
.\aresetn_d_reg[0] (aw_pipe_n_1),
.\aresetn_d_reg[1]_inv (ar_pipe_n_2),
.out(out),
.\s_axi_bid[11] (\s_axi_bid[11] ),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid),
.\s_bresp_acc_reg[1] (\s_bresp_acc_reg[1] ),
.si_rs_bvalid(si_rs_bvalid),
.\skid_buffer_reg[0]_0 (si_rs_bready));
zqynq_lab_1_design_auto_pc_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2 r_pipe
(.aclk(aclk),
.\aresetn_d_reg[0] (aw_pipe_n_1),
.\aresetn_d_reg[1]_inv (ar_pipe_n_2),
.\cnt_read_reg[3]_rep__0 (\cnt_read_reg[3]_rep__0 ),
.\cnt_read_reg[4] (\cnt_read_reg[4] ),
.\cnt_read_reg[4]_rep__0 (\cnt_read_reg[4]_rep__0 ),
.r_push_r_reg(r_push_r_reg),
.\s_axi_rid[11] (\s_axi_rid[11] ),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid),
.\skid_buffer_reg[0]_0 (si_rs_rready));
endmodule
module zqynq_lab_1_design_auto_pc_0_axi_register_slice_v2_1_13_axic_register_slice
(s_axi_arready,
s_ready_i_reg_0,
m_valid_i_reg_0,
Q,
\axaddr_incr_reg[7] ,
\axaddr_incr_reg[11] ,
\axaddr_incr_reg[7]_0 ,
\axaddr_incr_reg[3] ,
\wrap_cnt_r_reg[3] ,
\wrap_second_len_r_reg[3] ,
\wrap_cnt_r_reg[3]_0 ,
\axaddr_offset_r_reg[1] ,
\axaddr_offset_r_reg[0] ,
\axaddr_offset_r_reg[2] ,
\axlen_cnt_reg[3] ,
next_pending_r_reg,
next_pending_r_reg_0,
\axaddr_offset_r_reg[3] ,
\wrap_boundary_axaddr_r_reg[6] ,
\m_axi_araddr[10] ,
\aresetn_d_reg[0] ,
aclk,
\aresetn_d_reg[0]_0 ,
\state_reg[1] ,
\m_payload_i_reg[3]_0 ,
\wrap_second_len_r_reg[3]_0 ,
wrap_second_len_1,
\axaddr_offset_r_reg[3]_0 ,
\state_reg[1]_rep ,
\axaddr_offset_r_reg[3]_1 ,
\state_reg[0]_rep ,
\state_reg[1]_rep_0 ,
sel_first_2,
s_axi_arvalid,
s_axi_arid,
s_axi_arlen,
s_axi_arburst,
s_axi_arsize,
s_axi_arprot,
s_axi_araddr,
\axaddr_incr_reg[3]_0 ,
m_valid_i_reg_1);
output s_axi_arready;
output s_ready_i_reg_0;
output m_valid_i_reg_0;
output [58:0]Q;
output [3:0]\axaddr_incr_reg[7] ;
output [3:0]\axaddr_incr_reg[11] ;
output [0:0]\axaddr_incr_reg[7]_0 ;
output [3:0]\axaddr_incr_reg[3] ;
output [2:0]\wrap_cnt_r_reg[3] ;
output [2:0]\wrap_second_len_r_reg[3] ;
output \wrap_cnt_r_reg[3]_0 ;
output \axaddr_offset_r_reg[1] ;
output \axaddr_offset_r_reg[0] ;
output \axaddr_offset_r_reg[2] ;
output \axlen_cnt_reg[3] ;
output next_pending_r_reg;
output next_pending_r_reg_0;
output \axaddr_offset_r_reg[3] ;
output [6:0]\wrap_boundary_axaddr_r_reg[6] ;
output \m_axi_araddr[10] ;
input \aresetn_d_reg[0] ;
input aclk;
input \aresetn_d_reg[0]_0 ;
input [1:0]\state_reg[1] ;
input [3:0]\m_payload_i_reg[3]_0 ;
input [2:0]\wrap_second_len_r_reg[3]_0 ;
input [0:0]wrap_second_len_1;
input [0:0]\axaddr_offset_r_reg[3]_0 ;
input \state_reg[1]_rep ;
input [3:0]\axaddr_offset_r_reg[3]_1 ;
input \state_reg[0]_rep ;
input \state_reg[1]_rep_0 ;
input sel_first_2;
input s_axi_arvalid;
input [11:0]s_axi_arid;
input [7:0]s_axi_arlen;
input [1:0]s_axi_arburst;
input [1:0]s_axi_arsize;
input [2:0]s_axi_arprot;
input [31:0]s_axi_araddr;
input [3:0]\axaddr_incr_reg[3]_0 ;
input [0:0]m_valid_i_reg_1;
wire [58:0]Q;
wire aclk;
wire \aresetn_d_reg[0] ;
wire \aresetn_d_reg[0]_0 ;
wire \axaddr_incr[0]_i_10__0_n_0 ;
wire \axaddr_incr[0]_i_12__0_n_0 ;
wire \axaddr_incr[0]_i_13__0_n_0 ;
wire \axaddr_incr[0]_i_14__0_n_0 ;
wire \axaddr_incr[0]_i_3__0_n_0 ;
wire \axaddr_incr[0]_i_4__0_n_0 ;
wire \axaddr_incr[0]_i_5__0_n_0 ;
wire \axaddr_incr[0]_i_6__0_n_0 ;
wire \axaddr_incr[0]_i_7__0_n_0 ;
wire \axaddr_incr[0]_i_8__0_n_0 ;
wire \axaddr_incr[0]_i_9__0_n_0 ;
wire \axaddr_incr[4]_i_10__0_n_0 ;
wire \axaddr_incr[4]_i_7__0_n_0 ;
wire \axaddr_incr[4]_i_8__0_n_0 ;
wire \axaddr_incr[4]_i_9__0_n_0 ;
wire \axaddr_incr[8]_i_10__0_n_0 ;
wire \axaddr_incr[8]_i_7__0_n_0 ;
wire \axaddr_incr[8]_i_8__0_n_0 ;
wire \axaddr_incr[8]_i_9__0_n_0 ;
wire \axaddr_incr_reg[0]_i_11__0_n_0 ;
wire \axaddr_incr_reg[0]_i_11__0_n_1 ;
wire \axaddr_incr_reg[0]_i_11__0_n_2 ;
wire \axaddr_incr_reg[0]_i_11__0_n_3 ;
wire \axaddr_incr_reg[0]_i_11__0_n_4 ;
wire \axaddr_incr_reg[0]_i_11__0_n_5 ;
wire \axaddr_incr_reg[0]_i_11__0_n_6 ;
wire \axaddr_incr_reg[0]_i_11__0_n_7 ;
wire \axaddr_incr_reg[0]_i_2__0_n_1 ;
wire \axaddr_incr_reg[0]_i_2__0_n_2 ;
wire \axaddr_incr_reg[0]_i_2__0_n_3 ;
wire [3:0]\axaddr_incr_reg[11] ;
wire [3:0]\axaddr_incr_reg[3] ;
wire [3:0]\axaddr_incr_reg[3]_0 ;
wire \axaddr_incr_reg[4]_i_6__0_n_0 ;
wire \axaddr_incr_reg[4]_i_6__0_n_1 ;
wire \axaddr_incr_reg[4]_i_6__0_n_2 ;
wire \axaddr_incr_reg[4]_i_6__0_n_3 ;
wire [3:0]\axaddr_incr_reg[7] ;
wire [0:0]\axaddr_incr_reg[7]_0 ;
wire \axaddr_incr_reg[8]_i_6__0_n_1 ;
wire \axaddr_incr_reg[8]_i_6__0_n_2 ;
wire \axaddr_incr_reg[8]_i_6__0_n_3 ;
wire \axaddr_offset_r[0]_i_2__0_n_0 ;
wire \axaddr_offset_r[1]_i_2__0_n_0 ;
wire \axaddr_offset_r[2]_i_2__0_n_0 ;
wire \axaddr_offset_r[2]_i_3__0_n_0 ;
wire \axaddr_offset_r_reg[0] ;
wire \axaddr_offset_r_reg[1] ;
wire \axaddr_offset_r_reg[2] ;
wire \axaddr_offset_r_reg[3] ;
wire [0:0]\axaddr_offset_r_reg[3]_0 ;
wire [3:0]\axaddr_offset_r_reg[3]_1 ;
wire \axlen_cnt_reg[3] ;
wire \m_axi_araddr[10] ;
wire \m_payload_i[0]_i_1__0_n_0 ;
wire \m_payload_i[10]_i_1__0_n_0 ;
wire \m_payload_i[11]_i_1__0_n_0 ;
wire \m_payload_i[12]_i_1__0_n_0 ;
wire \m_payload_i[13]_i_1__1_n_0 ;
wire \m_payload_i[14]_i_1__0_n_0 ;
wire \m_payload_i[15]_i_1__0_n_0 ;
wire \m_payload_i[16]_i_1__0_n_0 ;
wire \m_payload_i[17]_i_1__0_n_0 ;
wire \m_payload_i[18]_i_1__0_n_0 ;
wire \m_payload_i[19]_i_1__0_n_0 ;
wire \m_payload_i[1]_i_1__0_n_0 ;
wire \m_payload_i[20]_i_1__0_n_0 ;
wire \m_payload_i[21]_i_1__0_n_0 ;
wire \m_payload_i[22]_i_1__0_n_0 ;
wire \m_payload_i[23]_i_1__0_n_0 ;
wire \m_payload_i[24]_i_1__0_n_0 ;
wire \m_payload_i[25]_i_1__0_n_0 ;
wire \m_payload_i[26]_i_1__0_n_0 ;
wire \m_payload_i[27]_i_1__0_n_0 ;
wire \m_payload_i[28]_i_1__0_n_0 ;
wire \m_payload_i[29]_i_1__0_n_0 ;
wire \m_payload_i[2]_i_1__0_n_0 ;
wire \m_payload_i[30]_i_1__0_n_0 ;
wire \m_payload_i[31]_i_2__0_n_0 ;
wire \m_payload_i[32]_i_1__0_n_0 ;
wire \m_payload_i[33]_i_1__0_n_0 ;
wire \m_payload_i[34]_i_1__0_n_0 ;
wire \m_payload_i[35]_i_1__0_n_0 ;
wire \m_payload_i[36]_i_1__0_n_0 ;
wire \m_payload_i[38]_i_1__0_n_0 ;
wire \m_payload_i[39]_i_1__0_n_0 ;
wire \m_payload_i[3]_i_1__0_n_0 ;
wire \m_payload_i[44]_i_1__0_n_0 ;
wire \m_payload_i[45]_i_1__0_n_0 ;
wire \m_payload_i[46]_i_1__1_n_0 ;
wire \m_payload_i[47]_i_1__0_n_0 ;
wire \m_payload_i[48]_i_1__0_n_0 ;
wire \m_payload_i[49]_i_1__0_n_0 ;
wire \m_payload_i[4]_i_1__0_n_0 ;
wire \m_payload_i[50]_i_1__0_n_0 ;
wire \m_payload_i[51]_i_1__0_n_0 ;
wire \m_payload_i[53]_i_1__0_n_0 ;
wire \m_payload_i[54]_i_1__0_n_0 ;
wire \m_payload_i[55]_i_1__0_n_0 ;
wire \m_payload_i[56]_i_1__0_n_0 ;
wire \m_payload_i[57]_i_1__0_n_0 ;
wire \m_payload_i[58]_i_1__0_n_0 ;
wire \m_payload_i[59]_i_1__0_n_0 ;
wire \m_payload_i[5]_i_1__0_n_0 ;
wire \m_payload_i[60]_i_1__0_n_0 ;
wire \m_payload_i[61]_i_1__0_n_0 ;
wire \m_payload_i[62]_i_1__0_n_0 ;
wire \m_payload_i[63]_i_1__0_n_0 ;
wire \m_payload_i[64]_i_1__0_n_0 ;
wire \m_payload_i[6]_i_1__0_n_0 ;
wire \m_payload_i[7]_i_1__0_n_0 ;
wire \m_payload_i[8]_i_1__0_n_0 ;
wire \m_payload_i[9]_i_1__0_n_0 ;
wire [3:0]\m_payload_i_reg[3]_0 ;
wire m_valid_i0;
wire m_valid_i_reg_0;
wire [0:0]m_valid_i_reg_1;
wire next_pending_r_reg;
wire next_pending_r_reg_0;
wire [31:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [11:0]s_axi_arid;
wire [7:0]s_axi_arlen;
wire [2:0]s_axi_arprot;
wire s_axi_arready;
wire [1:0]s_axi_arsize;
wire s_axi_arvalid;
wire s_ready_i0;
wire s_ready_i_reg_0;
wire sel_first_2;
wire \skid_buffer_reg_n_0_[0] ;
wire \skid_buffer_reg_n_0_[10] ;
wire \skid_buffer_reg_n_0_[11] ;
wire \skid_buffer_reg_n_0_[12] ;
wire \skid_buffer_reg_n_0_[13] ;
wire \skid_buffer_reg_n_0_[14] ;
wire \skid_buffer_reg_n_0_[15] ;
wire \skid_buffer_reg_n_0_[16] ;
wire \skid_buffer_reg_n_0_[17] ;
wire \skid_buffer_reg_n_0_[18] ;
wire \skid_buffer_reg_n_0_[19] ;
wire \skid_buffer_reg_n_0_[1] ;
wire \skid_buffer_reg_n_0_[20] ;
wire \skid_buffer_reg_n_0_[21] ;
wire \skid_buffer_reg_n_0_[22] ;
wire \skid_buffer_reg_n_0_[23] ;
wire \skid_buffer_reg_n_0_[24] ;
wire \skid_buffer_reg_n_0_[25] ;
wire \skid_buffer_reg_n_0_[26] ;
wire \skid_buffer_reg_n_0_[27] ;
wire \skid_buffer_reg_n_0_[28] ;
wire \skid_buffer_reg_n_0_[29] ;
wire \skid_buffer_reg_n_0_[2] ;
wire \skid_buffer_reg_n_0_[30] ;
wire \skid_buffer_reg_n_0_[31] ;
wire \skid_buffer_reg_n_0_[32] ;
wire \skid_buffer_reg_n_0_[33] ;
wire \skid_buffer_reg_n_0_[34] ;
wire \skid_buffer_reg_n_0_[35] ;
wire \skid_buffer_reg_n_0_[36] ;
wire \skid_buffer_reg_n_0_[38] ;
wire \skid_buffer_reg_n_0_[39] ;
wire \skid_buffer_reg_n_0_[3] ;
wire \skid_buffer_reg_n_0_[44] ;
wire \skid_buffer_reg_n_0_[45] ;
wire \skid_buffer_reg_n_0_[46] ;
wire \skid_buffer_reg_n_0_[47] ;
wire \skid_buffer_reg_n_0_[48] ;
wire \skid_buffer_reg_n_0_[49] ;
wire \skid_buffer_reg_n_0_[4] ;
wire \skid_buffer_reg_n_0_[50] ;
wire \skid_buffer_reg_n_0_[51] ;
wire \skid_buffer_reg_n_0_[53] ;
wire \skid_buffer_reg_n_0_[54] ;
wire \skid_buffer_reg_n_0_[55] ;
wire \skid_buffer_reg_n_0_[56] ;
wire \skid_buffer_reg_n_0_[57] ;
wire \skid_buffer_reg_n_0_[58] ;
wire \skid_buffer_reg_n_0_[59] ;
wire \skid_buffer_reg_n_0_[5] ;
wire \skid_buffer_reg_n_0_[60] ;
wire \skid_buffer_reg_n_0_[61] ;
wire \skid_buffer_reg_n_0_[62] ;
wire \skid_buffer_reg_n_0_[63] ;
wire \skid_buffer_reg_n_0_[64] ;
wire \skid_buffer_reg_n_0_[6] ;
wire \skid_buffer_reg_n_0_[7] ;
wire \skid_buffer_reg_n_0_[8] ;
wire \skid_buffer_reg_n_0_[9] ;
wire \state_reg[0]_rep ;
wire [1:0]\state_reg[1] ;
wire \state_reg[1]_rep ;
wire \state_reg[1]_rep_0 ;
wire \wrap_boundary_axaddr_r[3]_i_2__0_n_0 ;
wire [6:0]\wrap_boundary_axaddr_r_reg[6] ;
wire \wrap_cnt_r[3]_i_3__0_n_0 ;
wire [2:0]\wrap_cnt_r_reg[3] ;
wire \wrap_cnt_r_reg[3]_0 ;
wire [0:0]wrap_second_len_1;
wire \wrap_second_len_r[0]_i_2__0_n_0 ;
wire \wrap_second_len_r[0]_i_3__0_n_0 ;
wire \wrap_second_len_r[0]_i_4__0_n_0 ;
wire \wrap_second_len_r[3]_i_2__0_n_0 ;
wire [2:0]\wrap_second_len_r_reg[3] ;
wire [2:0]\wrap_second_len_r_reg[3]_0 ;
wire [3:3]\NLW_axaddr_incr_reg[8]_i_6__0_CO_UNCONNECTED ;
FDRE #(
.INIT(1'b1))
\aresetn_d_reg[1]_inv
(.C(aclk),
.CE(1'b1),
.D(\aresetn_d_reg[0]_0 ),
.Q(m_valid_i_reg_0),
.R(1'b0));
LUT5 #(
.INIT(32'hFFE100E1))
\axaddr_incr[0]_i_10__0
(.I0(Q[36]),
.I1(Q[35]),
.I2(\axaddr_incr_reg[3]_0 [0]),
.I3(sel_first_2),
.I4(\axaddr_incr_reg[0]_i_11__0_n_7 ),
.O(\axaddr_incr[0]_i_10__0_n_0 ));
LUT3 #(
.INIT(8'h2A))
\axaddr_incr[0]_i_12__0
(.I0(Q[2]),
.I1(Q[35]),
.I2(Q[36]),
.O(\axaddr_incr[0]_i_12__0_n_0 ));
LUT2 #(
.INIT(4'h2))
\axaddr_incr[0]_i_13__0
(.I0(Q[1]),
.I1(Q[36]),
.O(\axaddr_incr[0]_i_13__0_n_0 ));
LUT3 #(
.INIT(8'h02))
\axaddr_incr[0]_i_14__0
(.I0(Q[0]),
.I1(Q[35]),
.I2(Q[36]),
.O(\axaddr_incr[0]_i_14__0_n_0 ));
LUT3 #(
.INIT(8'h08))
\axaddr_incr[0]_i_3__0
(.I0(Q[35]),
.I1(Q[36]),
.I2(sel_first_2),
.O(\axaddr_incr[0]_i_3__0_n_0 ));
LUT3 #(
.INIT(8'h04))
\axaddr_incr[0]_i_4__0
(.I0(Q[35]),
.I1(Q[36]),
.I2(sel_first_2),
.O(\axaddr_incr[0]_i_4__0_n_0 ));
LUT3 #(
.INIT(8'h04))
\axaddr_incr[0]_i_5__0
(.I0(Q[36]),
.I1(Q[35]),
.I2(sel_first_2),
.O(\axaddr_incr[0]_i_5__0_n_0 ));
LUT3 #(
.INIT(8'h01))
\axaddr_incr[0]_i_6__0
(.I0(Q[35]),
.I1(Q[36]),
.I2(sel_first_2),
.O(\axaddr_incr[0]_i_6__0_n_0 ));
LUT5 #(
.INIT(32'hFF780078))
\axaddr_incr[0]_i_7__0
(.I0(Q[36]),
.I1(Q[35]),
.I2(\axaddr_incr_reg[3]_0 [3]),
.I3(sel_first_2),
.I4(\axaddr_incr_reg[0]_i_11__0_n_4 ),
.O(\axaddr_incr[0]_i_7__0_n_0 ));
LUT5 #(
.INIT(32'hFFD200D2))
\axaddr_incr[0]_i_8__0
(.I0(Q[36]),
.I1(Q[35]),
.I2(\axaddr_incr_reg[3]_0 [2]),
.I3(sel_first_2),
.I4(\axaddr_incr_reg[0]_i_11__0_n_5 ),
.O(\axaddr_incr[0]_i_8__0_n_0 ));
LUT5 #(
.INIT(32'hFFD200D2))
\axaddr_incr[0]_i_9__0
(.I0(Q[35]),
.I1(Q[36]),
.I2(\axaddr_incr_reg[3]_0 [1]),
.I3(sel_first_2),
.I4(\axaddr_incr_reg[0]_i_11__0_n_6 ),
.O(\axaddr_incr[0]_i_9__0_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_incr[4]_i_10__0
(.I0(Q[4]),
.O(\axaddr_incr[4]_i_10__0_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_incr[4]_i_7__0
(.I0(Q[7]),
.O(\axaddr_incr[4]_i_7__0_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_incr[4]_i_8__0
(.I0(Q[6]),
.O(\axaddr_incr[4]_i_8__0_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_incr[4]_i_9__0
(.I0(Q[5]),
.O(\axaddr_incr[4]_i_9__0_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_incr[8]_i_10__0
(.I0(Q[8]),
.O(\axaddr_incr[8]_i_10__0_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_incr[8]_i_7__0
(.I0(Q[11]),
.O(\axaddr_incr[8]_i_7__0_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_incr[8]_i_8__0
(.I0(Q[10]),
.O(\axaddr_incr[8]_i_8__0_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_incr[8]_i_9__0
(.I0(Q[9]),
.O(\axaddr_incr[8]_i_9__0_n_0 ));
CARRY4 \axaddr_incr_reg[0]_i_11__0
(.CI(1'b0),
.CO({\axaddr_incr_reg[0]_i_11__0_n_0 ,\axaddr_incr_reg[0]_i_11__0_n_1 ,\axaddr_incr_reg[0]_i_11__0_n_2 ,\axaddr_incr_reg[0]_i_11__0_n_3 }),
.CYINIT(1'b0),
.DI({Q[3],\axaddr_incr[0]_i_12__0_n_0 ,\axaddr_incr[0]_i_13__0_n_0 ,\axaddr_incr[0]_i_14__0_n_0 }),
.O({\axaddr_incr_reg[0]_i_11__0_n_4 ,\axaddr_incr_reg[0]_i_11__0_n_5 ,\axaddr_incr_reg[0]_i_11__0_n_6 ,\axaddr_incr_reg[0]_i_11__0_n_7 }),
.S(\m_payload_i_reg[3]_0 ));
CARRY4 \axaddr_incr_reg[0]_i_2__0
(.CI(1'b0),
.CO({\axaddr_incr_reg[7]_0 ,\axaddr_incr_reg[0]_i_2__0_n_1 ,\axaddr_incr_reg[0]_i_2__0_n_2 ,\axaddr_incr_reg[0]_i_2__0_n_3 }),
.CYINIT(1'b0),
.DI({\axaddr_incr[0]_i_3__0_n_0 ,\axaddr_incr[0]_i_4__0_n_0 ,\axaddr_incr[0]_i_5__0_n_0 ,\axaddr_incr[0]_i_6__0_n_0 }),
.O(\axaddr_incr_reg[3] ),
.S({\axaddr_incr[0]_i_7__0_n_0 ,\axaddr_incr[0]_i_8__0_n_0 ,\axaddr_incr[0]_i_9__0_n_0 ,\axaddr_incr[0]_i_10__0_n_0 }));
CARRY4 \axaddr_incr_reg[4]_i_6__0
(.CI(\axaddr_incr_reg[0]_i_11__0_n_0 ),
.CO({\axaddr_incr_reg[4]_i_6__0_n_0 ,\axaddr_incr_reg[4]_i_6__0_n_1 ,\axaddr_incr_reg[4]_i_6__0_n_2 ,\axaddr_incr_reg[4]_i_6__0_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\axaddr_incr_reg[7] ),
.S({\axaddr_incr[4]_i_7__0_n_0 ,\axaddr_incr[4]_i_8__0_n_0 ,\axaddr_incr[4]_i_9__0_n_0 ,\axaddr_incr[4]_i_10__0_n_0 }));
CARRY4 \axaddr_incr_reg[8]_i_6__0
(.CI(\axaddr_incr_reg[4]_i_6__0_n_0 ),
.CO({\NLW_axaddr_incr_reg[8]_i_6__0_CO_UNCONNECTED [3],\axaddr_incr_reg[8]_i_6__0_n_1 ,\axaddr_incr_reg[8]_i_6__0_n_2 ,\axaddr_incr_reg[8]_i_6__0_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\axaddr_incr_reg[11] ),
.S({\axaddr_incr[8]_i_7__0_n_0 ,\axaddr_incr[8]_i_8__0_n_0 ,\axaddr_incr[8]_i_9__0_n_0 ,\axaddr_incr[8]_i_10__0_n_0 }));
LUT6 #(
.INIT(64'hF0F0F0F0F088F0F0))
\axaddr_offset_r[0]_i_1__0
(.I0(\axaddr_offset_r[0]_i_2__0_n_0 ),
.I1(Q[39]),
.I2(\axaddr_offset_r_reg[3]_1 [0]),
.I3(\state_reg[1] [1]),
.I4(s_ready_i_reg_0),
.I5(\state_reg[1] [0]),
.O(\axaddr_offset_r_reg[0] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\axaddr_offset_r[0]_i_2__0
(.I0(Q[3]),
.I1(Q[1]),
.I2(Q[35]),
.I3(Q[2]),
.I4(Q[36]),
.I5(Q[0]),
.O(\axaddr_offset_r[0]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'hAC00FFFFAC000000))
\axaddr_offset_r[1]_i_1__0
(.I0(\axaddr_offset_r[2]_i_3__0_n_0 ),
.I1(\axaddr_offset_r[1]_i_2__0_n_0 ),
.I2(Q[35]),
.I3(Q[40]),
.I4(\state_reg[1]_rep ),
.I5(\axaddr_offset_r_reg[3]_1 [1]),
.O(\axaddr_offset_r_reg[1] ));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_offset_r[1]_i_2__0
(.I0(Q[3]),
.I1(Q[36]),
.I2(Q[1]),
.O(\axaddr_offset_r[1]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'hAC00FFFFAC000000))
\axaddr_offset_r[2]_i_1__0
(.I0(\axaddr_offset_r[2]_i_2__0_n_0 ),
.I1(\axaddr_offset_r[2]_i_3__0_n_0 ),
.I2(Q[35]),
.I3(Q[41]),
.I4(\state_reg[1]_rep ),
.I5(\axaddr_offset_r_reg[3]_1 [2]),
.O(\axaddr_offset_r_reg[2] ));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_offset_r[2]_i_2__0
(.I0(Q[5]),
.I1(Q[36]),
.I2(Q[3]),
.O(\axaddr_offset_r[2]_i_2__0_n_0 ));
LUT3 #(
.INIT(8'hB8))
\axaddr_offset_r[2]_i_3__0
(.I0(Q[4]),
.I1(Q[36]),
.I2(Q[2]),
.O(\axaddr_offset_r[2]_i_3__0_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\axaddr_offset_r[3]_i_2__0
(.I0(Q[6]),
.I1(Q[4]),
.I2(Q[35]),
.I3(Q[5]),
.I4(Q[36]),
.I5(Q[3]),
.O(\axaddr_offset_r_reg[3] ));
LUT4 #(
.INIT(16'hFFDF))
\axlen_cnt[3]_i_2__0
(.I0(Q[42]),
.I1(\state_reg[0]_rep ),
.I2(s_ready_i_reg_0),
.I3(\state_reg[1]_rep_0 ),
.O(\axlen_cnt_reg[3] ));
LUT2 #(
.INIT(4'h2))
\m_axi_araddr[11]_INST_0_i_1
(.I0(Q[37]),
.I1(sel_first_2),
.O(\m_axi_araddr[10] ));
LUT3 #(
.INIT(8'hB8))
\m_payload_i[0]_i_1__0
(.I0(s_axi_araddr[0]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[0] ),
.O(\m_payload_i[0]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair40" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[10]_i_1__0
(.I0(s_axi_araddr[10]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[10] ),
.O(\m_payload_i[10]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair39" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[11]_i_1__0
(.I0(s_axi_araddr[11]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[11] ),
.O(\m_payload_i[11]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair39" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[12]_i_1__0
(.I0(s_axi_araddr[12]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[12] ),
.O(\m_payload_i[12]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair38" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[13]_i_1__1
(.I0(s_axi_araddr[13]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[13] ),
.O(\m_payload_i[13]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair38" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[14]_i_1__0
(.I0(s_axi_araddr[14]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[14] ),
.O(\m_payload_i[14]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair37" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[15]_i_1__0
(.I0(s_axi_araddr[15]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[15] ),
.O(\m_payload_i[15]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair37" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[16]_i_1__0
(.I0(s_axi_araddr[16]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[16] ),
.O(\m_payload_i[16]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair36" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[17]_i_1__0
(.I0(s_axi_araddr[17]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[17] ),
.O(\m_payload_i[17]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair36" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[18]_i_1__0
(.I0(s_axi_araddr[18]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[18] ),
.O(\m_payload_i[18]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair35" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[19]_i_1__0
(.I0(s_axi_araddr[19]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[19] ),
.O(\m_payload_i[19]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair44" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[1]_i_1__0
(.I0(s_axi_araddr[1]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[1] ),
.O(\m_payload_i[1]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair35" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[20]_i_1__0
(.I0(s_axi_araddr[20]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[20] ),
.O(\m_payload_i[20]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair34" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[21]_i_1__0
(.I0(s_axi_araddr[21]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[21] ),
.O(\m_payload_i[21]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair34" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[22]_i_1__0
(.I0(s_axi_araddr[22]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[22] ),
.O(\m_payload_i[22]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[23]_i_1__0
(.I0(s_axi_araddr[23]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[23] ),
.O(\m_payload_i[23]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[24]_i_1__0
(.I0(s_axi_araddr[24]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[24] ),
.O(\m_payload_i[24]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[25]_i_1__0
(.I0(s_axi_araddr[25]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[25] ),
.O(\m_payload_i[25]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[26]_i_1__0
(.I0(s_axi_araddr[26]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[26] ),
.O(\m_payload_i[26]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[27]_i_1__0
(.I0(s_axi_araddr[27]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[27] ),
.O(\m_payload_i[27]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[28]_i_1__0
(.I0(s_axi_araddr[28]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[28] ),
.O(\m_payload_i[28]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[29]_i_1__0
(.I0(s_axi_araddr[29]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[29] ),
.O(\m_payload_i[29]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair44" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[2]_i_1__0
(.I0(s_axi_araddr[2]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[2] ),
.O(\m_payload_i[2]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[30]_i_1__0
(.I0(s_axi_araddr[30]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[30] ),
.O(\m_payload_i[30]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[31]_i_2__0
(.I0(s_axi_araddr[31]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[31] ),
.O(\m_payload_i[31]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[32]_i_1__0
(.I0(s_axi_arprot[0]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[32] ),
.O(\m_payload_i[32]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[33]_i_1__0
(.I0(s_axi_arprot[1]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[33] ),
.O(\m_payload_i[33]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[34]_i_1__0
(.I0(s_axi_arprot[2]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[34] ),
.O(\m_payload_i[34]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[35]_i_1__0
(.I0(s_axi_arsize[0]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[35] ),
.O(\m_payload_i[35]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[36]_i_1__0
(.I0(s_axi_arsize[1]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[36] ),
.O(\m_payload_i[36]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[38]_i_1__0
(.I0(s_axi_arburst[0]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[38] ),
.O(\m_payload_i[38]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[39]_i_1__0
(.I0(s_axi_arburst[1]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[39] ),
.O(\m_payload_i[39]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair43" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[3]_i_1__0
(.I0(s_axi_araddr[3]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[3] ),
.O(\m_payload_i[3]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[44]_i_1__0
(.I0(s_axi_arlen[0]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[44] ),
.O(\m_payload_i[44]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[45]_i_1__0
(.I0(s_axi_arlen[1]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[45] ),
.O(\m_payload_i[45]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[46]_i_1__1
(.I0(s_axi_arlen[2]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[46] ),
.O(\m_payload_i[46]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[47]_i_1__0
(.I0(s_axi_arlen[3]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[47] ),
.O(\m_payload_i[47]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[48]_i_1__0
(.I0(s_axi_arlen[4]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[48] ),
.O(\m_payload_i[48]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[49]_i_1__0
(.I0(s_axi_arlen[5]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[49] ),
.O(\m_payload_i[49]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair43" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[4]_i_1__0
(.I0(s_axi_araddr[4]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[4] ),
.O(\m_payload_i[4]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[50]_i_1__0
(.I0(s_axi_arlen[6]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[50] ),
.O(\m_payload_i[50]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[51]_i_1__0
(.I0(s_axi_arlen[7]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[51] ),
.O(\m_payload_i[51]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[53]_i_1__0
(.I0(s_axi_arid[0]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[53] ),
.O(\m_payload_i[53]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[54]_i_1__0
(.I0(s_axi_arid[1]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[54] ),
.O(\m_payload_i[54]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[55]_i_1__0
(.I0(s_axi_arid[2]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[55] ),
.O(\m_payload_i[55]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[56]_i_1__0
(.I0(s_axi_arid[3]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[56] ),
.O(\m_payload_i[56]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[57]_i_1__0
(.I0(s_axi_arid[4]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[57] ),
.O(\m_payload_i[57]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[58]_i_1__0
(.I0(s_axi_arid[5]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[58] ),
.O(\m_payload_i[58]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[59]_i_1__0
(.I0(s_axi_arid[6]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[59] ),
.O(\m_payload_i[59]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair42" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[5]_i_1__0
(.I0(s_axi_araddr[5]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[5] ),
.O(\m_payload_i[5]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[60]_i_1__0
(.I0(s_axi_arid[7]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[60] ),
.O(\m_payload_i[60]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[61]_i_1__0
(.I0(s_axi_arid[8]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[61] ),
.O(\m_payload_i[61]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[62]_i_1__0
(.I0(s_axi_arid[9]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[62] ),
.O(\m_payload_i[62]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[63]_i_1__0
(.I0(s_axi_arid[10]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[63] ),
.O(\m_payload_i[63]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[64]_i_1__0
(.I0(s_axi_arid[11]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[64] ),
.O(\m_payload_i[64]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair42" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[6]_i_1__0
(.I0(s_axi_araddr[6]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[6] ),
.O(\m_payload_i[6]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair41" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[7]_i_1__0
(.I0(s_axi_araddr[7]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[7] ),
.O(\m_payload_i[7]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair41" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[8]_i_1__0
(.I0(s_axi_araddr[8]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[8] ),
.O(\m_payload_i[8]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair40" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[9]_i_1__0
(.I0(s_axi_araddr[9]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[9] ),
.O(\m_payload_i[9]_i_1__0_n_0 ));
FDRE \m_payload_i_reg[0]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[0]_i_1__0_n_0 ),
.Q(Q[0]),
.R(1'b0));
FDRE \m_payload_i_reg[10]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[10]_i_1__0_n_0 ),
.Q(Q[10]),
.R(1'b0));
FDRE \m_payload_i_reg[11]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[11]_i_1__0_n_0 ),
.Q(Q[11]),
.R(1'b0));
FDRE \m_payload_i_reg[12]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[12]_i_1__0_n_0 ),
.Q(Q[12]),
.R(1'b0));
FDRE \m_payload_i_reg[13]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[13]_i_1__1_n_0 ),
.Q(Q[13]),
.R(1'b0));
FDRE \m_payload_i_reg[14]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[14]_i_1__0_n_0 ),
.Q(Q[14]),
.R(1'b0));
FDRE \m_payload_i_reg[15]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[15]_i_1__0_n_0 ),
.Q(Q[15]),
.R(1'b0));
FDRE \m_payload_i_reg[16]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[16]_i_1__0_n_0 ),
.Q(Q[16]),
.R(1'b0));
FDRE \m_payload_i_reg[17]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[17]_i_1__0_n_0 ),
.Q(Q[17]),
.R(1'b0));
FDRE \m_payload_i_reg[18]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[18]_i_1__0_n_0 ),
.Q(Q[18]),
.R(1'b0));
FDRE \m_payload_i_reg[19]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[19]_i_1__0_n_0 ),
.Q(Q[19]),
.R(1'b0));
FDRE \m_payload_i_reg[1]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[1]_i_1__0_n_0 ),
.Q(Q[1]),
.R(1'b0));
FDRE \m_payload_i_reg[20]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[20]_i_1__0_n_0 ),
.Q(Q[20]),
.R(1'b0));
FDRE \m_payload_i_reg[21]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[21]_i_1__0_n_0 ),
.Q(Q[21]),
.R(1'b0));
FDRE \m_payload_i_reg[22]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[22]_i_1__0_n_0 ),
.Q(Q[22]),
.R(1'b0));
FDRE \m_payload_i_reg[23]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[23]_i_1__0_n_0 ),
.Q(Q[23]),
.R(1'b0));
FDRE \m_payload_i_reg[24]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[24]_i_1__0_n_0 ),
.Q(Q[24]),
.R(1'b0));
FDRE \m_payload_i_reg[25]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[25]_i_1__0_n_0 ),
.Q(Q[25]),
.R(1'b0));
FDRE \m_payload_i_reg[26]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[26]_i_1__0_n_0 ),
.Q(Q[26]),
.R(1'b0));
FDRE \m_payload_i_reg[27]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[27]_i_1__0_n_0 ),
.Q(Q[27]),
.R(1'b0));
FDRE \m_payload_i_reg[28]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[28]_i_1__0_n_0 ),
.Q(Q[28]),
.R(1'b0));
FDRE \m_payload_i_reg[29]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[29]_i_1__0_n_0 ),
.Q(Q[29]),
.R(1'b0));
FDRE \m_payload_i_reg[2]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[2]_i_1__0_n_0 ),
.Q(Q[2]),
.R(1'b0));
FDRE \m_payload_i_reg[30]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[30]_i_1__0_n_0 ),
.Q(Q[30]),
.R(1'b0));
FDRE \m_payload_i_reg[31]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[31]_i_2__0_n_0 ),
.Q(Q[31]),
.R(1'b0));
FDRE \m_payload_i_reg[32]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[32]_i_1__0_n_0 ),
.Q(Q[32]),
.R(1'b0));
FDRE \m_payload_i_reg[33]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[33]_i_1__0_n_0 ),
.Q(Q[33]),
.R(1'b0));
FDRE \m_payload_i_reg[34]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[34]_i_1__0_n_0 ),
.Q(Q[34]),
.R(1'b0));
FDRE \m_payload_i_reg[35]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[35]_i_1__0_n_0 ),
.Q(Q[35]),
.R(1'b0));
FDRE \m_payload_i_reg[36]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[36]_i_1__0_n_0 ),
.Q(Q[36]),
.R(1'b0));
FDRE \m_payload_i_reg[38]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[38]_i_1__0_n_0 ),
.Q(Q[37]),
.R(1'b0));
FDRE \m_payload_i_reg[39]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[39]_i_1__0_n_0 ),
.Q(Q[38]),
.R(1'b0));
FDRE \m_payload_i_reg[3]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[3]_i_1__0_n_0 ),
.Q(Q[3]),
.R(1'b0));
FDRE \m_payload_i_reg[44]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[44]_i_1__0_n_0 ),
.Q(Q[39]),
.R(1'b0));
FDRE \m_payload_i_reg[45]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[45]_i_1__0_n_0 ),
.Q(Q[40]),
.R(1'b0));
FDRE \m_payload_i_reg[46]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[46]_i_1__1_n_0 ),
.Q(Q[41]),
.R(1'b0));
FDRE \m_payload_i_reg[47]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[47]_i_1__0_n_0 ),
.Q(Q[42]),
.R(1'b0));
FDRE \m_payload_i_reg[48]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[48]_i_1__0_n_0 ),
.Q(Q[43]),
.R(1'b0));
FDRE \m_payload_i_reg[49]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[49]_i_1__0_n_0 ),
.Q(Q[44]),
.R(1'b0));
FDRE \m_payload_i_reg[4]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[4]_i_1__0_n_0 ),
.Q(Q[4]),
.R(1'b0));
FDRE \m_payload_i_reg[50]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[50]_i_1__0_n_0 ),
.Q(Q[45]),
.R(1'b0));
FDRE \m_payload_i_reg[51]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[51]_i_1__0_n_0 ),
.Q(Q[46]),
.R(1'b0));
FDRE \m_payload_i_reg[53]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[53]_i_1__0_n_0 ),
.Q(Q[47]),
.R(1'b0));
FDRE \m_payload_i_reg[54]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[54]_i_1__0_n_0 ),
.Q(Q[48]),
.R(1'b0));
FDRE \m_payload_i_reg[55]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[55]_i_1__0_n_0 ),
.Q(Q[49]),
.R(1'b0));
FDRE \m_payload_i_reg[56]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[56]_i_1__0_n_0 ),
.Q(Q[50]),
.R(1'b0));
FDRE \m_payload_i_reg[57]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[57]_i_1__0_n_0 ),
.Q(Q[51]),
.R(1'b0));
FDRE \m_payload_i_reg[58]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[58]_i_1__0_n_0 ),
.Q(Q[52]),
.R(1'b0));
FDRE \m_payload_i_reg[59]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[59]_i_1__0_n_0 ),
.Q(Q[53]),
.R(1'b0));
FDRE \m_payload_i_reg[5]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[5]_i_1__0_n_0 ),
.Q(Q[5]),
.R(1'b0));
FDRE \m_payload_i_reg[60]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[60]_i_1__0_n_0 ),
.Q(Q[54]),
.R(1'b0));
FDRE \m_payload_i_reg[61]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[61]_i_1__0_n_0 ),
.Q(Q[55]),
.R(1'b0));
FDRE \m_payload_i_reg[62]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[62]_i_1__0_n_0 ),
.Q(Q[56]),
.R(1'b0));
FDRE \m_payload_i_reg[63]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[63]_i_1__0_n_0 ),
.Q(Q[57]),
.R(1'b0));
FDRE \m_payload_i_reg[64]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[64]_i_1__0_n_0 ),
.Q(Q[58]),
.R(1'b0));
FDRE \m_payload_i_reg[6]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[6]_i_1__0_n_0 ),
.Q(Q[6]),
.R(1'b0));
FDRE \m_payload_i_reg[7]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[7]_i_1__0_n_0 ),
.Q(Q[7]),
.R(1'b0));
FDRE \m_payload_i_reg[8]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[8]_i_1__0_n_0 ),
.Q(Q[8]),
.R(1'b0));
FDRE \m_payload_i_reg[9]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[9]_i_1__0_n_0 ),
.Q(Q[9]),
.R(1'b0));
LUT5 #(
.INIT(32'hBFFFBBBB))
m_valid_i_i_1__0
(.I0(s_axi_arvalid),
.I1(s_axi_arready),
.I2(\state_reg[0]_rep ),
.I3(\state_reg[1]_rep_0 ),
.I4(s_ready_i_reg_0),
.O(m_valid_i0));
FDRE #(
.INIT(1'b0))
m_valid_i_reg
(.C(aclk),
.CE(1'b1),
.D(m_valid_i0),
.Q(s_ready_i_reg_0),
.R(m_valid_i_reg_0));
LUT5 #(
.INIT(32'hFFFFFFFD))
next_pending_r_i_2__1
(.I0(next_pending_r_reg_0),
.I1(Q[46]),
.I2(Q[44]),
.I3(Q[45]),
.I4(Q[43]),
.O(next_pending_r_reg));
LUT4 #(
.INIT(16'h0001))
next_pending_r_i_2__2
(.I0(Q[41]),
.I1(Q[39]),
.I2(Q[40]),
.I3(Q[42]),
.O(next_pending_r_reg_0));
LUT5 #(
.INIT(32'hF444FFFF))
s_ready_i_i_1__0
(.I0(s_axi_arvalid),
.I1(s_axi_arready),
.I2(\state_reg[0]_rep ),
.I3(\state_reg[1]_rep_0 ),
.I4(s_ready_i_reg_0),
.O(s_ready_i0));
FDRE #(
.INIT(1'b0))
s_ready_i_reg
(.C(aclk),
.CE(1'b1),
.D(s_ready_i0),
.Q(s_axi_arready),
.R(\aresetn_d_reg[0] ));
FDRE \skid_buffer_reg[0]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[0]),
.Q(\skid_buffer_reg_n_0_[0] ),
.R(1'b0));
FDRE \skid_buffer_reg[10]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[10]),
.Q(\skid_buffer_reg_n_0_[10] ),
.R(1'b0));
FDRE \skid_buffer_reg[11]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[11]),
.Q(\skid_buffer_reg_n_0_[11] ),
.R(1'b0));
FDRE \skid_buffer_reg[12]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[12]),
.Q(\skid_buffer_reg_n_0_[12] ),
.R(1'b0));
FDRE \skid_buffer_reg[13]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[13]),
.Q(\skid_buffer_reg_n_0_[13] ),
.R(1'b0));
FDRE \skid_buffer_reg[14]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[14]),
.Q(\skid_buffer_reg_n_0_[14] ),
.R(1'b0));
FDRE \skid_buffer_reg[15]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[15]),
.Q(\skid_buffer_reg_n_0_[15] ),
.R(1'b0));
FDRE \skid_buffer_reg[16]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[16]),
.Q(\skid_buffer_reg_n_0_[16] ),
.R(1'b0));
FDRE \skid_buffer_reg[17]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[17]),
.Q(\skid_buffer_reg_n_0_[17] ),
.R(1'b0));
FDRE \skid_buffer_reg[18]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[18]),
.Q(\skid_buffer_reg_n_0_[18] ),
.R(1'b0));
FDRE \skid_buffer_reg[19]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[19]),
.Q(\skid_buffer_reg_n_0_[19] ),
.R(1'b0));
FDRE \skid_buffer_reg[1]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[1]),
.Q(\skid_buffer_reg_n_0_[1] ),
.R(1'b0));
FDRE \skid_buffer_reg[20]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[20]),
.Q(\skid_buffer_reg_n_0_[20] ),
.R(1'b0));
FDRE \skid_buffer_reg[21]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[21]),
.Q(\skid_buffer_reg_n_0_[21] ),
.R(1'b0));
FDRE \skid_buffer_reg[22]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[22]),
.Q(\skid_buffer_reg_n_0_[22] ),
.R(1'b0));
FDRE \skid_buffer_reg[23]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[23]),
.Q(\skid_buffer_reg_n_0_[23] ),
.R(1'b0));
FDRE \skid_buffer_reg[24]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[24]),
.Q(\skid_buffer_reg_n_0_[24] ),
.R(1'b0));
FDRE \skid_buffer_reg[25]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[25]),
.Q(\skid_buffer_reg_n_0_[25] ),
.R(1'b0));
FDRE \skid_buffer_reg[26]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[26]),
.Q(\skid_buffer_reg_n_0_[26] ),
.R(1'b0));
FDRE \skid_buffer_reg[27]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[27]),
.Q(\skid_buffer_reg_n_0_[27] ),
.R(1'b0));
FDRE \skid_buffer_reg[28]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[28]),
.Q(\skid_buffer_reg_n_0_[28] ),
.R(1'b0));
FDRE \skid_buffer_reg[29]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[29]),
.Q(\skid_buffer_reg_n_0_[29] ),
.R(1'b0));
FDRE \skid_buffer_reg[2]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[2]),
.Q(\skid_buffer_reg_n_0_[2] ),
.R(1'b0));
FDRE \skid_buffer_reg[30]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[30]),
.Q(\skid_buffer_reg_n_0_[30] ),
.R(1'b0));
FDRE \skid_buffer_reg[31]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[31]),
.Q(\skid_buffer_reg_n_0_[31] ),
.R(1'b0));
FDRE \skid_buffer_reg[32]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arprot[0]),
.Q(\skid_buffer_reg_n_0_[32] ),
.R(1'b0));
FDRE \skid_buffer_reg[33]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arprot[1]),
.Q(\skid_buffer_reg_n_0_[33] ),
.R(1'b0));
FDRE \skid_buffer_reg[34]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arprot[2]),
.Q(\skid_buffer_reg_n_0_[34] ),
.R(1'b0));
FDRE \skid_buffer_reg[35]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arsize[0]),
.Q(\skid_buffer_reg_n_0_[35] ),
.R(1'b0));
FDRE \skid_buffer_reg[36]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arsize[1]),
.Q(\skid_buffer_reg_n_0_[36] ),
.R(1'b0));
FDRE \skid_buffer_reg[38]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arburst[0]),
.Q(\skid_buffer_reg_n_0_[38] ),
.R(1'b0));
FDRE \skid_buffer_reg[39]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arburst[1]),
.Q(\skid_buffer_reg_n_0_[39] ),
.R(1'b0));
FDRE \skid_buffer_reg[3]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[3]),
.Q(\skid_buffer_reg_n_0_[3] ),
.R(1'b0));
FDRE \skid_buffer_reg[44]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arlen[0]),
.Q(\skid_buffer_reg_n_0_[44] ),
.R(1'b0));
FDRE \skid_buffer_reg[45]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arlen[1]),
.Q(\skid_buffer_reg_n_0_[45] ),
.R(1'b0));
FDRE \skid_buffer_reg[46]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arlen[2]),
.Q(\skid_buffer_reg_n_0_[46] ),
.R(1'b0));
FDRE \skid_buffer_reg[47]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arlen[3]),
.Q(\skid_buffer_reg_n_0_[47] ),
.R(1'b0));
FDRE \skid_buffer_reg[48]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arlen[4]),
.Q(\skid_buffer_reg_n_0_[48] ),
.R(1'b0));
FDRE \skid_buffer_reg[49]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arlen[5]),
.Q(\skid_buffer_reg_n_0_[49] ),
.R(1'b0));
FDRE \skid_buffer_reg[4]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[4]),
.Q(\skid_buffer_reg_n_0_[4] ),
.R(1'b0));
FDRE \skid_buffer_reg[50]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arlen[6]),
.Q(\skid_buffer_reg_n_0_[50] ),
.R(1'b0));
FDRE \skid_buffer_reg[51]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arlen[7]),
.Q(\skid_buffer_reg_n_0_[51] ),
.R(1'b0));
FDRE \skid_buffer_reg[53]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[0]),
.Q(\skid_buffer_reg_n_0_[53] ),
.R(1'b0));
FDRE \skid_buffer_reg[54]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[1]),
.Q(\skid_buffer_reg_n_0_[54] ),
.R(1'b0));
FDRE \skid_buffer_reg[55]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[2]),
.Q(\skid_buffer_reg_n_0_[55] ),
.R(1'b0));
FDRE \skid_buffer_reg[56]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[3]),
.Q(\skid_buffer_reg_n_0_[56] ),
.R(1'b0));
FDRE \skid_buffer_reg[57]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[4]),
.Q(\skid_buffer_reg_n_0_[57] ),
.R(1'b0));
FDRE \skid_buffer_reg[58]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[5]),
.Q(\skid_buffer_reg_n_0_[58] ),
.R(1'b0));
FDRE \skid_buffer_reg[59]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[6]),
.Q(\skid_buffer_reg_n_0_[59] ),
.R(1'b0));
FDRE \skid_buffer_reg[5]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[5]),
.Q(\skid_buffer_reg_n_0_[5] ),
.R(1'b0));
FDRE \skid_buffer_reg[60]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[7]),
.Q(\skid_buffer_reg_n_0_[60] ),
.R(1'b0));
FDRE \skid_buffer_reg[61]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[8]),
.Q(\skid_buffer_reg_n_0_[61] ),
.R(1'b0));
FDRE \skid_buffer_reg[62]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[9]),
.Q(\skid_buffer_reg_n_0_[62] ),
.R(1'b0));
FDRE \skid_buffer_reg[63]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[10]),
.Q(\skid_buffer_reg_n_0_[63] ),
.R(1'b0));
FDRE \skid_buffer_reg[64]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[11]),
.Q(\skid_buffer_reg_n_0_[64] ),
.R(1'b0));
FDRE \skid_buffer_reg[6]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[6]),
.Q(\skid_buffer_reg_n_0_[6] ),
.R(1'b0));
FDRE \skid_buffer_reg[7]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[7]),
.Q(\skid_buffer_reg_n_0_[7] ),
.R(1'b0));
FDRE \skid_buffer_reg[8]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[8]),
.Q(\skid_buffer_reg_n_0_[8] ),
.R(1'b0));
FDRE \skid_buffer_reg[9]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[9]),
.Q(\skid_buffer_reg_n_0_[9] ),
.R(1'b0));
LUT4 #(
.INIT(16'hAA8A))
\wrap_boundary_axaddr_r[0]_i_1__0
(.I0(Q[0]),
.I1(Q[36]),
.I2(Q[39]),
.I3(Q[35]),
.O(\wrap_boundary_axaddr_r_reg[6] [0]));
LUT5 #(
.INIT(32'h8A888AAA))
\wrap_boundary_axaddr_r[1]_i_1__0
(.I0(Q[1]),
.I1(Q[36]),
.I2(Q[39]),
.I3(Q[35]),
.I4(Q[40]),
.O(\wrap_boundary_axaddr_r_reg[6] [1]));
LUT6 #(
.INIT(64'hA0A0202AAAAA202A))
\wrap_boundary_axaddr_r[2]_i_1__0
(.I0(Q[2]),
.I1(Q[40]),
.I2(Q[35]),
.I3(Q[41]),
.I4(Q[36]),
.I5(Q[39]),
.O(\wrap_boundary_axaddr_r_reg[6] [2]));
LUT6 #(
.INIT(64'h020202A2A2A202A2))
\wrap_boundary_axaddr_r[3]_i_1__0
(.I0(Q[3]),
.I1(\wrap_boundary_axaddr_r[3]_i_2__0_n_0 ),
.I2(Q[36]),
.I3(Q[40]),
.I4(Q[35]),
.I5(Q[39]),
.O(\wrap_boundary_axaddr_r_reg[6] [3]));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT3 #(
.INIT(8'hB8))
\wrap_boundary_axaddr_r[3]_i_2__0
(.I0(Q[41]),
.I1(Q[35]),
.I2(Q[42]),
.O(\wrap_boundary_axaddr_r[3]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'h002A882A222AAA2A))
\wrap_boundary_axaddr_r[4]_i_1__0
(.I0(Q[4]),
.I1(Q[35]),
.I2(Q[42]),
.I3(Q[36]),
.I4(Q[40]),
.I5(Q[41]),
.O(\wrap_boundary_axaddr_r_reg[6] [4]));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT5 #(
.INIT(32'h2A222AAA))
\wrap_boundary_axaddr_r[5]_i_1__0
(.I0(Q[5]),
.I1(Q[36]),
.I2(Q[41]),
.I3(Q[35]),
.I4(Q[42]),
.O(\wrap_boundary_axaddr_r_reg[6] [5]));
LUT4 #(
.INIT(16'h2AAA))
\wrap_boundary_axaddr_r[6]_i_1__0
(.I0(Q[6]),
.I1(Q[36]),
.I2(Q[42]),
.I3(Q[35]),
.O(\wrap_boundary_axaddr_r_reg[6] [6]));
LUT6 #(
.INIT(64'hBBBBBABBCCCCC0CC))
\wrap_cnt_r[0]_i_1__0
(.I0(\wrap_second_len_r[0]_i_2__0_n_0 ),
.I1(\wrap_second_len_r_reg[3]_0 [0]),
.I2(\state_reg[1] [0]),
.I3(s_ready_i_reg_0),
.I4(\state_reg[1] [1]),
.I5(\wrap_second_len_r[0]_i_3__0_n_0 ),
.O(\wrap_cnt_r_reg[3] [0]));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT3 #(
.INIT(8'h9A))
\wrap_cnt_r[2]_i_1__0
(.I0(\wrap_second_len_r_reg[3] [1]),
.I1(\wrap_cnt_r_reg[3]_0 ),
.I2(wrap_second_len_1),
.O(\wrap_cnt_r_reg[3] [1]));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT4 #(
.INIT(16'hA6AA))
\wrap_cnt_r[3]_i_1__0
(.I0(\wrap_second_len_r_reg[3] [2]),
.I1(wrap_second_len_1),
.I2(\wrap_cnt_r_reg[3]_0 ),
.I3(\wrap_second_len_r_reg[3] [1]),
.O(\wrap_cnt_r_reg[3] [2]));
LUT5 #(
.INIT(32'hAAAAAAAB))
\wrap_cnt_r[3]_i_2__0
(.I0(\wrap_cnt_r[3]_i_3__0_n_0 ),
.I1(\axaddr_offset_r_reg[1] ),
.I2(\axaddr_offset_r_reg[0] ),
.I3(\axaddr_offset_r_reg[3]_0 ),
.I4(\axaddr_offset_r_reg[2] ),
.O(\wrap_cnt_r_reg[3]_0 ));
LUT6 #(
.INIT(64'h0F0F0F0F0F880F0F))
\wrap_cnt_r[3]_i_3__0
(.I0(\axaddr_offset_r[0]_i_2__0_n_0 ),
.I1(Q[39]),
.I2(\wrap_second_len_r_reg[3]_0 [0]),
.I3(\state_reg[1] [1]),
.I4(s_ready_i_reg_0),
.I5(\state_reg[1] [0]),
.O(\wrap_cnt_r[3]_i_3__0_n_0 ));
LUT6 #(
.INIT(64'h4444454444444044))
\wrap_second_len_r[0]_i_1__0
(.I0(\wrap_second_len_r[0]_i_2__0_n_0 ),
.I1(\wrap_second_len_r_reg[3]_0 [0]),
.I2(\state_reg[1] [0]),
.I3(s_ready_i_reg_0),
.I4(\state_reg[1] [1]),
.I5(\wrap_second_len_r[0]_i_3__0_n_0 ),
.O(\wrap_second_len_r_reg[3] [0]));
LUT6 #(
.INIT(64'hAAAAA8080000A808))
\wrap_second_len_r[0]_i_2__0
(.I0(\wrap_second_len_r[0]_i_4__0_n_0 ),
.I1(Q[0]),
.I2(Q[36]),
.I3(Q[2]),
.I4(Q[35]),
.I5(\axaddr_offset_r[1]_i_2__0_n_0 ),
.O(\wrap_second_len_r[0]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFBA))
\wrap_second_len_r[0]_i_3__0
(.I0(\axaddr_offset_r_reg[2] ),
.I1(\state_reg[1]_rep ),
.I2(\axaddr_offset_r_reg[3]_1 [3]),
.I3(\wrap_second_len_r[3]_i_2__0_n_0 ),
.I4(\axaddr_offset_r_reg[0] ),
.I5(\axaddr_offset_r_reg[1] ),
.O(\wrap_second_len_r[0]_i_3__0_n_0 ));
LUT4 #(
.INIT(16'h0020))
\wrap_second_len_r[0]_i_4__0
(.I0(Q[39]),
.I1(\state_reg[1] [0]),
.I2(s_ready_i_reg_0),
.I3(\state_reg[1] [1]),
.O(\wrap_second_len_r[0]_i_4__0_n_0 ));
LUT6 #(
.INIT(64'hEE10FFFFEE100000))
\wrap_second_len_r[2]_i_1__0
(.I0(\axaddr_offset_r_reg[1] ),
.I1(\axaddr_offset_r_reg[0] ),
.I2(\axaddr_offset_r_reg[3]_0 ),
.I3(\axaddr_offset_r_reg[2] ),
.I4(\state_reg[1]_rep ),
.I5(\wrap_second_len_r_reg[3]_0 [1]),
.O(\wrap_second_len_r_reg[3] [1]));
LUT6 #(
.INIT(64'hFFFFFFF444444444))
\wrap_second_len_r[3]_i_1__0
(.I0(\state_reg[1]_rep ),
.I1(\wrap_second_len_r_reg[3]_0 [2]),
.I2(\axaddr_offset_r_reg[0] ),
.I3(\axaddr_offset_r_reg[1] ),
.I4(\axaddr_offset_r_reg[2] ),
.I5(\wrap_second_len_r[3]_i_2__0_n_0 ),
.O(\wrap_second_len_r_reg[3] [2]));
LUT6 #(
.INIT(64'h00000000EEE222E2))
\wrap_second_len_r[3]_i_2__0
(.I0(\axaddr_offset_r[2]_i_2__0_n_0 ),
.I1(Q[35]),
.I2(Q[4]),
.I3(Q[36]),
.I4(Q[6]),
.I5(\axlen_cnt_reg[3] ),
.O(\wrap_second_len_r[3]_i_2__0_n_0 ));
endmodule
(* ORIG_REF_NAME = "axi_register_slice_v2_1_13_axic_register_slice" *)
module zqynq_lab_1_design_auto_pc_0_axi_register_slice_v2_1_13_axic_register_slice_0
(s_axi_awready,
s_ready_i_reg_0,
m_valid_i_reg_0,
Q,
\axaddr_incr_reg[11] ,
CO,
O,
D,
\wrap_second_len_r_reg[3] ,
\wrap_cnt_r_reg[3] ,
\axaddr_offset_r_reg[1] ,
\axaddr_offset_r_reg[0] ,
\axaddr_offset_r_reg[2] ,
\axlen_cnt_reg[3] ,
next_pending_r_reg,
next_pending_r_reg_0,
\axaddr_offset_r_reg[3] ,
\wrap_boundary_axaddr_r_reg[6] ,
\m_axi_awaddr[10] ,
\aresetn_d_reg[1]_inv ,
aclk,
\aresetn_d_reg[1]_inv_0 ,
aresetn,
\state_reg[0]_rep ,
\state_reg[1]_rep ,
b_push,
s_axi_awvalid,
S,
\wrap_second_len_r_reg[3]_0 ,
\state_reg[1] ,
wrap_second_len,
\axaddr_offset_r_reg[3]_0 ,
\state_reg[1]_rep_0 ,
\axaddr_offset_r_reg[3]_1 ,
sel_first,
s_axi_awid,
s_axi_awlen,
s_axi_awburst,
s_axi_awsize,
s_axi_awprot,
s_axi_awaddr,
axaddr_incr_reg,
E);
output s_axi_awready;
output s_ready_i_reg_0;
output m_valid_i_reg_0;
output [58:0]Q;
output [7:0]\axaddr_incr_reg[11] ;
output [0:0]CO;
output [3:0]O;
output [2:0]D;
output [2:0]\wrap_second_len_r_reg[3] ;
output \wrap_cnt_r_reg[3] ;
output \axaddr_offset_r_reg[1] ;
output \axaddr_offset_r_reg[0] ;
output \axaddr_offset_r_reg[2] ;
output \axlen_cnt_reg[3] ;
output next_pending_r_reg;
output next_pending_r_reg_0;
output \axaddr_offset_r_reg[3] ;
output [6:0]\wrap_boundary_axaddr_r_reg[6] ;
output \m_axi_awaddr[10] ;
output \aresetn_d_reg[1]_inv ;
input aclk;
input \aresetn_d_reg[1]_inv_0 ;
input aresetn;
input \state_reg[0]_rep ;
input \state_reg[1]_rep ;
input b_push;
input s_axi_awvalid;
input [3:0]S;
input [2:0]\wrap_second_len_r_reg[3]_0 ;
input [1:0]\state_reg[1] ;
input [0:0]wrap_second_len;
input [0:0]\axaddr_offset_r_reg[3]_0 ;
input \state_reg[1]_rep_0 ;
input [3:0]\axaddr_offset_r_reg[3]_1 ;
input sel_first;
input [11:0]s_axi_awid;
input [7:0]s_axi_awlen;
input [1:0]s_axi_awburst;
input [1:0]s_axi_awsize;
input [2:0]s_axi_awprot;
input [31:0]s_axi_awaddr;
input [3:0]axaddr_incr_reg;
input [0:0]E;
wire [3:0]C;
wire [0:0]CO;
wire [2:0]D;
wire [0:0]E;
wire [3:0]O;
wire [58:0]Q;
wire [3:0]S;
wire aclk;
wire aresetn;
wire \aresetn_d_reg[1]_inv ;
wire \aresetn_d_reg[1]_inv_0 ;
wire \aresetn_d_reg_n_0_[0] ;
wire \axaddr_incr[0]_i_10_n_0 ;
wire \axaddr_incr[0]_i_12_n_0 ;
wire \axaddr_incr[0]_i_13_n_0 ;
wire \axaddr_incr[0]_i_14_n_0 ;
wire \axaddr_incr[0]_i_3_n_0 ;
wire \axaddr_incr[0]_i_4_n_0 ;
wire \axaddr_incr[0]_i_5_n_0 ;
wire \axaddr_incr[0]_i_6_n_0 ;
wire \axaddr_incr[0]_i_7_n_0 ;
wire \axaddr_incr[0]_i_8_n_0 ;
wire \axaddr_incr[0]_i_9_n_0 ;
wire \axaddr_incr[4]_i_10_n_0 ;
wire \axaddr_incr[4]_i_7_n_0 ;
wire \axaddr_incr[4]_i_8_n_0 ;
wire \axaddr_incr[4]_i_9_n_0 ;
wire \axaddr_incr[8]_i_10_n_0 ;
wire \axaddr_incr[8]_i_7_n_0 ;
wire \axaddr_incr[8]_i_8_n_0 ;
wire \axaddr_incr[8]_i_9_n_0 ;
wire [3:0]axaddr_incr_reg;
wire \axaddr_incr_reg[0]_i_11_n_0 ;
wire \axaddr_incr_reg[0]_i_11_n_1 ;
wire \axaddr_incr_reg[0]_i_11_n_2 ;
wire \axaddr_incr_reg[0]_i_11_n_3 ;
wire \axaddr_incr_reg[0]_i_2_n_1 ;
wire \axaddr_incr_reg[0]_i_2_n_2 ;
wire \axaddr_incr_reg[0]_i_2_n_3 ;
wire [7:0]\axaddr_incr_reg[11] ;
wire \axaddr_incr_reg[4]_i_6_n_0 ;
wire \axaddr_incr_reg[4]_i_6_n_1 ;
wire \axaddr_incr_reg[4]_i_6_n_2 ;
wire \axaddr_incr_reg[4]_i_6_n_3 ;
wire \axaddr_incr_reg[8]_i_6_n_1 ;
wire \axaddr_incr_reg[8]_i_6_n_2 ;
wire \axaddr_incr_reg[8]_i_6_n_3 ;
wire \axaddr_offset_r[0]_i_2_n_0 ;
wire \axaddr_offset_r[1]_i_2_n_0 ;
wire \axaddr_offset_r[2]_i_2_n_0 ;
wire \axaddr_offset_r[2]_i_3_n_0 ;
wire \axaddr_offset_r_reg[0] ;
wire \axaddr_offset_r_reg[1] ;
wire \axaddr_offset_r_reg[2] ;
wire \axaddr_offset_r_reg[3] ;
wire [0:0]\axaddr_offset_r_reg[3]_0 ;
wire [3:0]\axaddr_offset_r_reg[3]_1 ;
wire \axlen_cnt_reg[3] ;
wire b_push;
wire \m_axi_awaddr[10] ;
wire m_valid_i0;
wire m_valid_i_reg_0;
wire next_pending_r_reg;
wire next_pending_r_reg_0;
wire [31:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [11:0]s_axi_awid;
wire [7:0]s_axi_awlen;
wire [2:0]s_axi_awprot;
wire s_axi_awready;
wire [1:0]s_axi_awsize;
wire s_axi_awvalid;
wire s_ready_i0;
wire s_ready_i_reg_0;
wire sel_first;
wire [64:0]skid_buffer;
wire \skid_buffer_reg_n_0_[0] ;
wire \skid_buffer_reg_n_0_[10] ;
wire \skid_buffer_reg_n_0_[11] ;
wire \skid_buffer_reg_n_0_[12] ;
wire \skid_buffer_reg_n_0_[13] ;
wire \skid_buffer_reg_n_0_[14] ;
wire \skid_buffer_reg_n_0_[15] ;
wire \skid_buffer_reg_n_0_[16] ;
wire \skid_buffer_reg_n_0_[17] ;
wire \skid_buffer_reg_n_0_[18] ;
wire \skid_buffer_reg_n_0_[19] ;
wire \skid_buffer_reg_n_0_[1] ;
wire \skid_buffer_reg_n_0_[20] ;
wire \skid_buffer_reg_n_0_[21] ;
wire \skid_buffer_reg_n_0_[22] ;
wire \skid_buffer_reg_n_0_[23] ;
wire \skid_buffer_reg_n_0_[24] ;
wire \skid_buffer_reg_n_0_[25] ;
wire \skid_buffer_reg_n_0_[26] ;
wire \skid_buffer_reg_n_0_[27] ;
wire \skid_buffer_reg_n_0_[28] ;
wire \skid_buffer_reg_n_0_[29] ;
wire \skid_buffer_reg_n_0_[2] ;
wire \skid_buffer_reg_n_0_[30] ;
wire \skid_buffer_reg_n_0_[31] ;
wire \skid_buffer_reg_n_0_[32] ;
wire \skid_buffer_reg_n_0_[33] ;
wire \skid_buffer_reg_n_0_[34] ;
wire \skid_buffer_reg_n_0_[35] ;
wire \skid_buffer_reg_n_0_[36] ;
wire \skid_buffer_reg_n_0_[38] ;
wire \skid_buffer_reg_n_0_[39] ;
wire \skid_buffer_reg_n_0_[3] ;
wire \skid_buffer_reg_n_0_[44] ;
wire \skid_buffer_reg_n_0_[45] ;
wire \skid_buffer_reg_n_0_[46] ;
wire \skid_buffer_reg_n_0_[47] ;
wire \skid_buffer_reg_n_0_[48] ;
wire \skid_buffer_reg_n_0_[49] ;
wire \skid_buffer_reg_n_0_[4] ;
wire \skid_buffer_reg_n_0_[50] ;
wire \skid_buffer_reg_n_0_[51] ;
wire \skid_buffer_reg_n_0_[53] ;
wire \skid_buffer_reg_n_0_[54] ;
wire \skid_buffer_reg_n_0_[55] ;
wire \skid_buffer_reg_n_0_[56] ;
wire \skid_buffer_reg_n_0_[57] ;
wire \skid_buffer_reg_n_0_[58] ;
wire \skid_buffer_reg_n_0_[59] ;
wire \skid_buffer_reg_n_0_[5] ;
wire \skid_buffer_reg_n_0_[60] ;
wire \skid_buffer_reg_n_0_[61] ;
wire \skid_buffer_reg_n_0_[62] ;
wire \skid_buffer_reg_n_0_[63] ;
wire \skid_buffer_reg_n_0_[64] ;
wire \skid_buffer_reg_n_0_[6] ;
wire \skid_buffer_reg_n_0_[7] ;
wire \skid_buffer_reg_n_0_[8] ;
wire \skid_buffer_reg_n_0_[9] ;
wire \state_reg[0]_rep ;
wire [1:0]\state_reg[1] ;
wire \state_reg[1]_rep ;
wire \state_reg[1]_rep_0 ;
wire \wrap_boundary_axaddr_r[3]_i_2_n_0 ;
wire [6:0]\wrap_boundary_axaddr_r_reg[6] ;
wire \wrap_cnt_r[3]_i_3_n_0 ;
wire \wrap_cnt_r_reg[3] ;
wire [0:0]wrap_second_len;
wire \wrap_second_len_r[0]_i_2_n_0 ;
wire \wrap_second_len_r[0]_i_3_n_0 ;
wire \wrap_second_len_r[0]_i_4_n_0 ;
wire \wrap_second_len_r[3]_i_2_n_0 ;
wire [2:0]\wrap_second_len_r_reg[3] ;
wire [2:0]\wrap_second_len_r_reg[3]_0 ;
wire [3:3]\NLW_axaddr_incr_reg[8]_i_6_CO_UNCONNECTED ;
LUT2 #(
.INIT(4'h7))
\aresetn_d[1]_inv_i_1
(.I0(\aresetn_d_reg_n_0_[0] ),
.I1(aresetn),
.O(\aresetn_d_reg[1]_inv ));
FDRE #(
.INIT(1'b0))
\aresetn_d_reg[0]
(.C(aclk),
.CE(1'b1),
.D(aresetn),
.Q(\aresetn_d_reg_n_0_[0] ),
.R(1'b0));
LUT5 #(
.INIT(32'hFFE100E1))
\axaddr_incr[0]_i_10
(.I0(Q[36]),
.I1(Q[35]),
.I2(axaddr_incr_reg[0]),
.I3(sel_first),
.I4(C[0]),
.O(\axaddr_incr[0]_i_10_n_0 ));
LUT3 #(
.INIT(8'h2A))
\axaddr_incr[0]_i_12
(.I0(Q[2]),
.I1(Q[35]),
.I2(Q[36]),
.O(\axaddr_incr[0]_i_12_n_0 ));
LUT2 #(
.INIT(4'h2))
\axaddr_incr[0]_i_13
(.I0(Q[1]),
.I1(Q[36]),
.O(\axaddr_incr[0]_i_13_n_0 ));
LUT3 #(
.INIT(8'h02))
\axaddr_incr[0]_i_14
(.I0(Q[0]),
.I1(Q[35]),
.I2(Q[36]),
.O(\axaddr_incr[0]_i_14_n_0 ));
LUT3 #(
.INIT(8'h08))
\axaddr_incr[0]_i_3
(.I0(Q[35]),
.I1(Q[36]),
.I2(sel_first),
.O(\axaddr_incr[0]_i_3_n_0 ));
LUT3 #(
.INIT(8'h04))
\axaddr_incr[0]_i_4
(.I0(Q[35]),
.I1(Q[36]),
.I2(sel_first),
.O(\axaddr_incr[0]_i_4_n_0 ));
LUT3 #(
.INIT(8'h04))
\axaddr_incr[0]_i_5
(.I0(Q[36]),
.I1(Q[35]),
.I2(sel_first),
.O(\axaddr_incr[0]_i_5_n_0 ));
LUT3 #(
.INIT(8'h01))
\axaddr_incr[0]_i_6
(.I0(Q[35]),
.I1(Q[36]),
.I2(sel_first),
.O(\axaddr_incr[0]_i_6_n_0 ));
LUT5 #(
.INIT(32'hFF780078))
\axaddr_incr[0]_i_7
(.I0(Q[36]),
.I1(Q[35]),
.I2(axaddr_incr_reg[3]),
.I3(sel_first),
.I4(C[3]),
.O(\axaddr_incr[0]_i_7_n_0 ));
LUT5 #(
.INIT(32'hFFD200D2))
\axaddr_incr[0]_i_8
(.I0(Q[36]),
.I1(Q[35]),
.I2(axaddr_incr_reg[2]),
.I3(sel_first),
.I4(C[2]),
.O(\axaddr_incr[0]_i_8_n_0 ));
LUT5 #(
.INIT(32'hFFD200D2))
\axaddr_incr[0]_i_9
(.I0(Q[35]),
.I1(Q[36]),
.I2(axaddr_incr_reg[1]),
.I3(sel_first),
.I4(C[1]),
.O(\axaddr_incr[0]_i_9_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_incr[4]_i_10
(.I0(Q[4]),
.O(\axaddr_incr[4]_i_10_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_incr[4]_i_7
(.I0(Q[7]),
.O(\axaddr_incr[4]_i_7_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_incr[4]_i_8
(.I0(Q[6]),
.O(\axaddr_incr[4]_i_8_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_incr[4]_i_9
(.I0(Q[5]),
.O(\axaddr_incr[4]_i_9_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_incr[8]_i_10
(.I0(Q[8]),
.O(\axaddr_incr[8]_i_10_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_incr[8]_i_7
(.I0(Q[11]),
.O(\axaddr_incr[8]_i_7_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_incr[8]_i_8
(.I0(Q[10]),
.O(\axaddr_incr[8]_i_8_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_incr[8]_i_9
(.I0(Q[9]),
.O(\axaddr_incr[8]_i_9_n_0 ));
CARRY4 \axaddr_incr_reg[0]_i_11
(.CI(1'b0),
.CO({\axaddr_incr_reg[0]_i_11_n_0 ,\axaddr_incr_reg[0]_i_11_n_1 ,\axaddr_incr_reg[0]_i_11_n_2 ,\axaddr_incr_reg[0]_i_11_n_3 }),
.CYINIT(1'b0),
.DI({Q[3],\axaddr_incr[0]_i_12_n_0 ,\axaddr_incr[0]_i_13_n_0 ,\axaddr_incr[0]_i_14_n_0 }),
.O(C),
.S(S));
CARRY4 \axaddr_incr_reg[0]_i_2
(.CI(1'b0),
.CO({CO,\axaddr_incr_reg[0]_i_2_n_1 ,\axaddr_incr_reg[0]_i_2_n_2 ,\axaddr_incr_reg[0]_i_2_n_3 }),
.CYINIT(1'b0),
.DI({\axaddr_incr[0]_i_3_n_0 ,\axaddr_incr[0]_i_4_n_0 ,\axaddr_incr[0]_i_5_n_0 ,\axaddr_incr[0]_i_6_n_0 }),
.O(O),
.S({\axaddr_incr[0]_i_7_n_0 ,\axaddr_incr[0]_i_8_n_0 ,\axaddr_incr[0]_i_9_n_0 ,\axaddr_incr[0]_i_10_n_0 }));
CARRY4 \axaddr_incr_reg[4]_i_6
(.CI(\axaddr_incr_reg[0]_i_11_n_0 ),
.CO({\axaddr_incr_reg[4]_i_6_n_0 ,\axaddr_incr_reg[4]_i_6_n_1 ,\axaddr_incr_reg[4]_i_6_n_2 ,\axaddr_incr_reg[4]_i_6_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\axaddr_incr_reg[11] [3:0]),
.S({\axaddr_incr[4]_i_7_n_0 ,\axaddr_incr[4]_i_8_n_0 ,\axaddr_incr[4]_i_9_n_0 ,\axaddr_incr[4]_i_10_n_0 }));
CARRY4 \axaddr_incr_reg[8]_i_6
(.CI(\axaddr_incr_reg[4]_i_6_n_0 ),
.CO({\NLW_axaddr_incr_reg[8]_i_6_CO_UNCONNECTED [3],\axaddr_incr_reg[8]_i_6_n_1 ,\axaddr_incr_reg[8]_i_6_n_2 ,\axaddr_incr_reg[8]_i_6_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\axaddr_incr_reg[11] [7:4]),
.S({\axaddr_incr[8]_i_7_n_0 ,\axaddr_incr[8]_i_8_n_0 ,\axaddr_incr[8]_i_9_n_0 ,\axaddr_incr[8]_i_10_n_0 }));
LUT6 #(
.INIT(64'hF0F0F0F0F088F0F0))
\axaddr_offset_r[0]_i_1
(.I0(\axaddr_offset_r[0]_i_2_n_0 ),
.I1(Q[39]),
.I2(\axaddr_offset_r_reg[3]_1 [0]),
.I3(\state_reg[1] [1]),
.I4(m_valid_i_reg_0),
.I5(\state_reg[1] [0]),
.O(\axaddr_offset_r_reg[0] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\axaddr_offset_r[0]_i_2
(.I0(Q[3]),
.I1(Q[1]),
.I2(Q[35]),
.I3(Q[2]),
.I4(Q[36]),
.I5(Q[0]),
.O(\axaddr_offset_r[0]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAC00FFFFAC000000))
\axaddr_offset_r[1]_i_1
(.I0(\axaddr_offset_r[2]_i_3_n_0 ),
.I1(\axaddr_offset_r[1]_i_2_n_0 ),
.I2(Q[35]),
.I3(Q[40]),
.I4(\state_reg[1]_rep_0 ),
.I5(\axaddr_offset_r_reg[3]_1 [1]),
.O(\axaddr_offset_r_reg[1] ));
LUT3 #(
.INIT(8'hB8))
\axaddr_offset_r[1]_i_2
(.I0(Q[3]),
.I1(Q[36]),
.I2(Q[1]),
.O(\axaddr_offset_r[1]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAC00FFFFAC000000))
\axaddr_offset_r[2]_i_1
(.I0(\axaddr_offset_r[2]_i_2_n_0 ),
.I1(\axaddr_offset_r[2]_i_3_n_0 ),
.I2(Q[35]),
.I3(Q[41]),
.I4(\state_reg[1]_rep_0 ),
.I5(\axaddr_offset_r_reg[3]_1 [2]),
.O(\axaddr_offset_r_reg[2] ));
(* SOFT_HLUTNM = "soft_lutpair48" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_offset_r[2]_i_2
(.I0(Q[5]),
.I1(Q[36]),
.I2(Q[3]),
.O(\axaddr_offset_r[2]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair48" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_offset_r[2]_i_3
(.I0(Q[4]),
.I1(Q[36]),
.I2(Q[2]),
.O(\axaddr_offset_r[2]_i_3_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\axaddr_offset_r[3]_i_2
(.I0(Q[6]),
.I1(Q[4]),
.I2(Q[35]),
.I3(Q[5]),
.I4(Q[36]),
.I5(Q[3]),
.O(\axaddr_offset_r_reg[3] ));
(* SOFT_HLUTNM = "soft_lutpair46" *)
LUT4 #(
.INIT(16'hFFDF))
\axlen_cnt[3]_i_2
(.I0(Q[42]),
.I1(\state_reg[0]_rep ),
.I2(m_valid_i_reg_0),
.I3(\state_reg[1]_rep ),
.O(\axlen_cnt_reg[3] ));
LUT2 #(
.INIT(4'h2))
\m_axi_awaddr[11]_INST_0_i_1
(.I0(Q[37]),
.I1(sel_first),
.O(\m_axi_awaddr[10] ));
LUT3 #(
.INIT(8'hB8))
\m_payload_i[0]_i_1
(.I0(s_axi_awaddr[0]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[0] ),
.O(skid_buffer[0]));
(* SOFT_HLUTNM = "soft_lutpair73" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[10]_i_1
(.I0(s_axi_awaddr[10]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[10] ),
.O(skid_buffer[10]));
(* SOFT_HLUTNM = "soft_lutpair72" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[11]_i_1
(.I0(s_axi_awaddr[11]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[11] ),
.O(skid_buffer[11]));
(* SOFT_HLUTNM = "soft_lutpair72" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[12]_i_1
(.I0(s_axi_awaddr[12]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[12] ),
.O(skid_buffer[12]));
(* SOFT_HLUTNM = "soft_lutpair71" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[13]_i_1__0
(.I0(s_axi_awaddr[13]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[13] ),
.O(skid_buffer[13]));
(* SOFT_HLUTNM = "soft_lutpair71" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[14]_i_1
(.I0(s_axi_awaddr[14]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[14] ),
.O(skid_buffer[14]));
(* SOFT_HLUTNM = "soft_lutpair70" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[15]_i_1
(.I0(s_axi_awaddr[15]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[15] ),
.O(skid_buffer[15]));
(* SOFT_HLUTNM = "soft_lutpair70" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[16]_i_1
(.I0(s_axi_awaddr[16]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[16] ),
.O(skid_buffer[16]));
(* SOFT_HLUTNM = "soft_lutpair69" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[17]_i_1
(.I0(s_axi_awaddr[17]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[17] ),
.O(skid_buffer[17]));
(* SOFT_HLUTNM = "soft_lutpair69" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[18]_i_1
(.I0(s_axi_awaddr[18]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[18] ),
.O(skid_buffer[18]));
(* SOFT_HLUTNM = "soft_lutpair68" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[19]_i_1
(.I0(s_axi_awaddr[19]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[19] ),
.O(skid_buffer[19]));
(* SOFT_HLUTNM = "soft_lutpair77" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[1]_i_1
(.I0(s_axi_awaddr[1]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[1] ),
.O(skid_buffer[1]));
(* SOFT_HLUTNM = "soft_lutpair68" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[20]_i_1
(.I0(s_axi_awaddr[20]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[20] ),
.O(skid_buffer[20]));
(* SOFT_HLUTNM = "soft_lutpair67" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[21]_i_1
(.I0(s_axi_awaddr[21]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[21] ),
.O(skid_buffer[21]));
(* SOFT_HLUTNM = "soft_lutpair67" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[22]_i_1
(.I0(s_axi_awaddr[22]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[22] ),
.O(skid_buffer[22]));
(* SOFT_HLUTNM = "soft_lutpair66" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[23]_i_1
(.I0(s_axi_awaddr[23]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[23] ),
.O(skid_buffer[23]));
(* SOFT_HLUTNM = "soft_lutpair66" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[24]_i_1
(.I0(s_axi_awaddr[24]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[24] ),
.O(skid_buffer[24]));
(* SOFT_HLUTNM = "soft_lutpair65" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[25]_i_1
(.I0(s_axi_awaddr[25]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[25] ),
.O(skid_buffer[25]));
(* SOFT_HLUTNM = "soft_lutpair65" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[26]_i_1
(.I0(s_axi_awaddr[26]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[26] ),
.O(skid_buffer[26]));
(* SOFT_HLUTNM = "soft_lutpair64" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[27]_i_1
(.I0(s_axi_awaddr[27]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[27] ),
.O(skid_buffer[27]));
(* SOFT_HLUTNM = "soft_lutpair64" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[28]_i_1
(.I0(s_axi_awaddr[28]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[28] ),
.O(skid_buffer[28]));
(* SOFT_HLUTNM = "soft_lutpair63" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[29]_i_1
(.I0(s_axi_awaddr[29]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[29] ),
.O(skid_buffer[29]));
(* SOFT_HLUTNM = "soft_lutpair77" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[2]_i_1
(.I0(s_axi_awaddr[2]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[2] ),
.O(skid_buffer[2]));
(* SOFT_HLUTNM = "soft_lutpair63" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[30]_i_1
(.I0(s_axi_awaddr[30]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[30] ),
.O(skid_buffer[30]));
(* SOFT_HLUTNM = "soft_lutpair62" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[31]_i_2
(.I0(s_axi_awaddr[31]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[31] ),
.O(skid_buffer[31]));
(* SOFT_HLUTNM = "soft_lutpair62" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[32]_i_1
(.I0(s_axi_awprot[0]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[32] ),
.O(skid_buffer[32]));
(* SOFT_HLUTNM = "soft_lutpair61" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[33]_i_1
(.I0(s_axi_awprot[1]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[33] ),
.O(skid_buffer[33]));
(* SOFT_HLUTNM = "soft_lutpair61" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[34]_i_1
(.I0(s_axi_awprot[2]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[34] ),
.O(skid_buffer[34]));
(* SOFT_HLUTNM = "soft_lutpair60" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[35]_i_1
(.I0(s_axi_awsize[0]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[35] ),
.O(skid_buffer[35]));
(* SOFT_HLUTNM = "soft_lutpair60" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[36]_i_1
(.I0(s_axi_awsize[1]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[36] ),
.O(skid_buffer[36]));
(* SOFT_HLUTNM = "soft_lutpair59" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[38]_i_1
(.I0(s_axi_awburst[0]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[38] ),
.O(skid_buffer[38]));
(* SOFT_HLUTNM = "soft_lutpair59" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[39]_i_1
(.I0(s_axi_awburst[1]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[39] ),
.O(skid_buffer[39]));
(* SOFT_HLUTNM = "soft_lutpair76" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[3]_i_1
(.I0(s_axi_awaddr[3]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[3] ),
.O(skid_buffer[3]));
(* SOFT_HLUTNM = "soft_lutpair58" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[44]_i_1
(.I0(s_axi_awlen[0]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[44] ),
.O(skid_buffer[44]));
(* SOFT_HLUTNM = "soft_lutpair58" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[45]_i_1
(.I0(s_axi_awlen[1]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[45] ),
.O(skid_buffer[45]));
(* SOFT_HLUTNM = "soft_lutpair57" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[46]_i_1__0
(.I0(s_axi_awlen[2]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[46] ),
.O(skid_buffer[46]));
(* SOFT_HLUTNM = "soft_lutpair57" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[47]_i_1
(.I0(s_axi_awlen[3]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[47] ),
.O(skid_buffer[47]));
(* SOFT_HLUTNM = "soft_lutpair56" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[48]_i_1
(.I0(s_axi_awlen[4]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[48] ),
.O(skid_buffer[48]));
(* SOFT_HLUTNM = "soft_lutpair56" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[49]_i_1
(.I0(s_axi_awlen[5]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[49] ),
.O(skid_buffer[49]));
(* SOFT_HLUTNM = "soft_lutpair76" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[4]_i_1
(.I0(s_axi_awaddr[4]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[4] ),
.O(skid_buffer[4]));
(* SOFT_HLUTNM = "soft_lutpair55" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[50]_i_1
(.I0(s_axi_awlen[6]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[50] ),
.O(skid_buffer[50]));
(* SOFT_HLUTNM = "soft_lutpair55" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[51]_i_1
(.I0(s_axi_awlen[7]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[51] ),
.O(skid_buffer[51]));
(* SOFT_HLUTNM = "soft_lutpair54" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[53]_i_1
(.I0(s_axi_awid[0]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[53] ),
.O(skid_buffer[53]));
(* SOFT_HLUTNM = "soft_lutpair54" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[54]_i_1
(.I0(s_axi_awid[1]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[54] ),
.O(skid_buffer[54]));
(* SOFT_HLUTNM = "soft_lutpair53" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[55]_i_1
(.I0(s_axi_awid[2]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[55] ),
.O(skid_buffer[55]));
(* SOFT_HLUTNM = "soft_lutpair53" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[56]_i_1
(.I0(s_axi_awid[3]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[56] ),
.O(skid_buffer[56]));
(* SOFT_HLUTNM = "soft_lutpair52" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[57]_i_1
(.I0(s_axi_awid[4]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[57] ),
.O(skid_buffer[57]));
(* SOFT_HLUTNM = "soft_lutpair52" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[58]_i_1
(.I0(s_axi_awid[5]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[58] ),
.O(skid_buffer[58]));
(* SOFT_HLUTNM = "soft_lutpair51" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[59]_i_1
(.I0(s_axi_awid[6]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[59] ),
.O(skid_buffer[59]));
(* SOFT_HLUTNM = "soft_lutpair75" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[5]_i_1
(.I0(s_axi_awaddr[5]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[5] ),
.O(skid_buffer[5]));
(* SOFT_HLUTNM = "soft_lutpair51" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[60]_i_1
(.I0(s_axi_awid[7]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[60] ),
.O(skid_buffer[60]));
(* SOFT_HLUTNM = "soft_lutpair50" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[61]_i_1
(.I0(s_axi_awid[8]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[61] ),
.O(skid_buffer[61]));
(* SOFT_HLUTNM = "soft_lutpair50" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[62]_i_1
(.I0(s_axi_awid[9]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[62] ),
.O(skid_buffer[62]));
(* SOFT_HLUTNM = "soft_lutpair49" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[63]_i_1
(.I0(s_axi_awid[10]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[63] ),
.O(skid_buffer[63]));
(* SOFT_HLUTNM = "soft_lutpair49" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[64]_i_1
(.I0(s_axi_awid[11]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[64] ),
.O(skid_buffer[64]));
(* SOFT_HLUTNM = "soft_lutpair75" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[6]_i_1
(.I0(s_axi_awaddr[6]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[6] ),
.O(skid_buffer[6]));
(* SOFT_HLUTNM = "soft_lutpair74" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[7]_i_1
(.I0(s_axi_awaddr[7]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[7] ),
.O(skid_buffer[7]));
(* SOFT_HLUTNM = "soft_lutpair74" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[8]_i_1
(.I0(s_axi_awaddr[8]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[8] ),
.O(skid_buffer[8]));
(* SOFT_HLUTNM = "soft_lutpair73" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[9]_i_1
(.I0(s_axi_awaddr[9]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[9] ),
.O(skid_buffer[9]));
FDRE \m_payload_i_reg[0]
(.C(aclk),
.CE(E),
.D(skid_buffer[0]),
.Q(Q[0]),
.R(1'b0));
FDRE \m_payload_i_reg[10]
(.C(aclk),
.CE(E),
.D(skid_buffer[10]),
.Q(Q[10]),
.R(1'b0));
FDRE \m_payload_i_reg[11]
(.C(aclk),
.CE(E),
.D(skid_buffer[11]),
.Q(Q[11]),
.R(1'b0));
FDRE \m_payload_i_reg[12]
(.C(aclk),
.CE(E),
.D(skid_buffer[12]),
.Q(Q[12]),
.R(1'b0));
FDRE \m_payload_i_reg[13]
(.C(aclk),
.CE(E),
.D(skid_buffer[13]),
.Q(Q[13]),
.R(1'b0));
FDRE \m_payload_i_reg[14]
(.C(aclk),
.CE(E),
.D(skid_buffer[14]),
.Q(Q[14]),
.R(1'b0));
FDRE \m_payload_i_reg[15]
(.C(aclk),
.CE(E),
.D(skid_buffer[15]),
.Q(Q[15]),
.R(1'b0));
FDRE \m_payload_i_reg[16]
(.C(aclk),
.CE(E),
.D(skid_buffer[16]),
.Q(Q[16]),
.R(1'b0));
FDRE \m_payload_i_reg[17]
(.C(aclk),
.CE(E),
.D(skid_buffer[17]),
.Q(Q[17]),
.R(1'b0));
FDRE \m_payload_i_reg[18]
(.C(aclk),
.CE(E),
.D(skid_buffer[18]),
.Q(Q[18]),
.R(1'b0));
FDRE \m_payload_i_reg[19]
(.C(aclk),
.CE(E),
.D(skid_buffer[19]),
.Q(Q[19]),
.R(1'b0));
FDRE \m_payload_i_reg[1]
(.C(aclk),
.CE(E),
.D(skid_buffer[1]),
.Q(Q[1]),
.R(1'b0));
FDRE \m_payload_i_reg[20]
(.C(aclk),
.CE(E),
.D(skid_buffer[20]),
.Q(Q[20]),
.R(1'b0));
FDRE \m_payload_i_reg[21]
(.C(aclk),
.CE(E),
.D(skid_buffer[21]),
.Q(Q[21]),
.R(1'b0));
FDRE \m_payload_i_reg[22]
(.C(aclk),
.CE(E),
.D(skid_buffer[22]),
.Q(Q[22]),
.R(1'b0));
FDRE \m_payload_i_reg[23]
(.C(aclk),
.CE(E),
.D(skid_buffer[23]),
.Q(Q[23]),
.R(1'b0));
FDRE \m_payload_i_reg[24]
(.C(aclk),
.CE(E),
.D(skid_buffer[24]),
.Q(Q[24]),
.R(1'b0));
FDRE \m_payload_i_reg[25]
(.C(aclk),
.CE(E),
.D(skid_buffer[25]),
.Q(Q[25]),
.R(1'b0));
FDRE \m_payload_i_reg[26]
(.C(aclk),
.CE(E),
.D(skid_buffer[26]),
.Q(Q[26]),
.R(1'b0));
FDRE \m_payload_i_reg[27]
(.C(aclk),
.CE(E),
.D(skid_buffer[27]),
.Q(Q[27]),
.R(1'b0));
FDRE \m_payload_i_reg[28]
(.C(aclk),
.CE(E),
.D(skid_buffer[28]),
.Q(Q[28]),
.R(1'b0));
FDRE \m_payload_i_reg[29]
(.C(aclk),
.CE(E),
.D(skid_buffer[29]),
.Q(Q[29]),
.R(1'b0));
FDRE \m_payload_i_reg[2]
(.C(aclk),
.CE(E),
.D(skid_buffer[2]),
.Q(Q[2]),
.R(1'b0));
FDRE \m_payload_i_reg[30]
(.C(aclk),
.CE(E),
.D(skid_buffer[30]),
.Q(Q[30]),
.R(1'b0));
FDRE \m_payload_i_reg[31]
(.C(aclk),
.CE(E),
.D(skid_buffer[31]),
.Q(Q[31]),
.R(1'b0));
FDRE \m_payload_i_reg[32]
(.C(aclk),
.CE(E),
.D(skid_buffer[32]),
.Q(Q[32]),
.R(1'b0));
FDRE \m_payload_i_reg[33]
(.C(aclk),
.CE(E),
.D(skid_buffer[33]),
.Q(Q[33]),
.R(1'b0));
FDRE \m_payload_i_reg[34]
(.C(aclk),
.CE(E),
.D(skid_buffer[34]),
.Q(Q[34]),
.R(1'b0));
FDRE \m_payload_i_reg[35]
(.C(aclk),
.CE(E),
.D(skid_buffer[35]),
.Q(Q[35]),
.R(1'b0));
FDRE \m_payload_i_reg[36]
(.C(aclk),
.CE(E),
.D(skid_buffer[36]),
.Q(Q[36]),
.R(1'b0));
FDRE \m_payload_i_reg[38]
(.C(aclk),
.CE(E),
.D(skid_buffer[38]),
.Q(Q[37]),
.R(1'b0));
FDRE \m_payload_i_reg[39]
(.C(aclk),
.CE(E),
.D(skid_buffer[39]),
.Q(Q[38]),
.R(1'b0));
FDRE \m_payload_i_reg[3]
(.C(aclk),
.CE(E),
.D(skid_buffer[3]),
.Q(Q[3]),
.R(1'b0));
FDRE \m_payload_i_reg[44]
(.C(aclk),
.CE(E),
.D(skid_buffer[44]),
.Q(Q[39]),
.R(1'b0));
FDRE \m_payload_i_reg[45]
(.C(aclk),
.CE(E),
.D(skid_buffer[45]),
.Q(Q[40]),
.R(1'b0));
FDRE \m_payload_i_reg[46]
(.C(aclk),
.CE(E),
.D(skid_buffer[46]),
.Q(Q[41]),
.R(1'b0));
FDRE \m_payload_i_reg[47]
(.C(aclk),
.CE(E),
.D(skid_buffer[47]),
.Q(Q[42]),
.R(1'b0));
FDRE \m_payload_i_reg[48]
(.C(aclk),
.CE(E),
.D(skid_buffer[48]),
.Q(Q[43]),
.R(1'b0));
FDRE \m_payload_i_reg[49]
(.C(aclk),
.CE(E),
.D(skid_buffer[49]),
.Q(Q[44]),
.R(1'b0));
FDRE \m_payload_i_reg[4]
(.C(aclk),
.CE(E),
.D(skid_buffer[4]),
.Q(Q[4]),
.R(1'b0));
FDRE \m_payload_i_reg[50]
(.C(aclk),
.CE(E),
.D(skid_buffer[50]),
.Q(Q[45]),
.R(1'b0));
FDRE \m_payload_i_reg[51]
(.C(aclk),
.CE(E),
.D(skid_buffer[51]),
.Q(Q[46]),
.R(1'b0));
FDRE \m_payload_i_reg[53]
(.C(aclk),
.CE(E),
.D(skid_buffer[53]),
.Q(Q[47]),
.R(1'b0));
FDRE \m_payload_i_reg[54]
(.C(aclk),
.CE(E),
.D(skid_buffer[54]),
.Q(Q[48]),
.R(1'b0));
FDRE \m_payload_i_reg[55]
(.C(aclk),
.CE(E),
.D(skid_buffer[55]),
.Q(Q[49]),
.R(1'b0));
FDRE \m_payload_i_reg[56]
(.C(aclk),
.CE(E),
.D(skid_buffer[56]),
.Q(Q[50]),
.R(1'b0));
FDRE \m_payload_i_reg[57]
(.C(aclk),
.CE(E),
.D(skid_buffer[57]),
.Q(Q[51]),
.R(1'b0));
FDRE \m_payload_i_reg[58]
(.C(aclk),
.CE(E),
.D(skid_buffer[58]),
.Q(Q[52]),
.R(1'b0));
FDRE \m_payload_i_reg[59]
(.C(aclk),
.CE(E),
.D(skid_buffer[59]),
.Q(Q[53]),
.R(1'b0));
FDRE \m_payload_i_reg[5]
(.C(aclk),
.CE(E),
.D(skid_buffer[5]),
.Q(Q[5]),
.R(1'b0));
FDRE \m_payload_i_reg[60]
(.C(aclk),
.CE(E),
.D(skid_buffer[60]),
.Q(Q[54]),
.R(1'b0));
FDRE \m_payload_i_reg[61]
(.C(aclk),
.CE(E),
.D(skid_buffer[61]),
.Q(Q[55]),
.R(1'b0));
FDRE \m_payload_i_reg[62]
(.C(aclk),
.CE(E),
.D(skid_buffer[62]),
.Q(Q[56]),
.R(1'b0));
FDRE \m_payload_i_reg[63]
(.C(aclk),
.CE(E),
.D(skid_buffer[63]),
.Q(Q[57]),
.R(1'b0));
FDRE \m_payload_i_reg[64]
(.C(aclk),
.CE(E),
.D(skid_buffer[64]),
.Q(Q[58]),
.R(1'b0));
FDRE \m_payload_i_reg[6]
(.C(aclk),
.CE(E),
.D(skid_buffer[6]),
.Q(Q[6]),
.R(1'b0));
FDRE \m_payload_i_reg[7]
(.C(aclk),
.CE(E),
.D(skid_buffer[7]),
.Q(Q[7]),
.R(1'b0));
FDRE \m_payload_i_reg[8]
(.C(aclk),
.CE(E),
.D(skid_buffer[8]),
.Q(Q[8]),
.R(1'b0));
FDRE \m_payload_i_reg[9]
(.C(aclk),
.CE(E),
.D(skid_buffer[9]),
.Q(Q[9]),
.R(1'b0));
LUT4 #(
.INIT(16'hF4FF))
m_valid_i_i_1__2
(.I0(b_push),
.I1(m_valid_i_reg_0),
.I2(s_axi_awvalid),
.I3(s_axi_awready),
.O(m_valid_i0));
FDRE #(
.INIT(1'b0))
m_valid_i_reg
(.C(aclk),
.CE(1'b1),
.D(m_valid_i0),
.Q(m_valid_i_reg_0),
.R(\aresetn_d_reg[1]_inv_0 ));
LUT5 #(
.INIT(32'hFFFFFFFE))
next_pending_r_i_2
(.I0(next_pending_r_reg_0),
.I1(Q[43]),
.I2(Q[44]),
.I3(Q[46]),
.I4(Q[45]),
.O(next_pending_r_reg));
LUT4 #(
.INIT(16'hFFFE))
next_pending_r_i_2__0
(.I0(Q[41]),
.I1(Q[39]),
.I2(Q[40]),
.I3(Q[42]),
.O(next_pending_r_reg_0));
LUT1 #(
.INIT(2'h1))
s_ready_i_i_1__1
(.I0(\aresetn_d_reg_n_0_[0] ),
.O(s_ready_i_reg_0));
LUT4 #(
.INIT(16'hBFBB))
s_ready_i_i_2
(.I0(b_push),
.I1(m_valid_i_reg_0),
.I2(s_axi_awvalid),
.I3(s_axi_awready),
.O(s_ready_i0));
FDRE #(
.INIT(1'b0))
s_ready_i_reg
(.C(aclk),
.CE(1'b1),
.D(s_ready_i0),
.Q(s_axi_awready),
.R(s_ready_i_reg_0));
FDRE \skid_buffer_reg[0]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[0]),
.Q(\skid_buffer_reg_n_0_[0] ),
.R(1'b0));
FDRE \skid_buffer_reg[10]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[10]),
.Q(\skid_buffer_reg_n_0_[10] ),
.R(1'b0));
FDRE \skid_buffer_reg[11]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[11]),
.Q(\skid_buffer_reg_n_0_[11] ),
.R(1'b0));
FDRE \skid_buffer_reg[12]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[12]),
.Q(\skid_buffer_reg_n_0_[12] ),
.R(1'b0));
FDRE \skid_buffer_reg[13]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[13]),
.Q(\skid_buffer_reg_n_0_[13] ),
.R(1'b0));
FDRE \skid_buffer_reg[14]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[14]),
.Q(\skid_buffer_reg_n_0_[14] ),
.R(1'b0));
FDRE \skid_buffer_reg[15]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[15]),
.Q(\skid_buffer_reg_n_0_[15] ),
.R(1'b0));
FDRE \skid_buffer_reg[16]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[16]),
.Q(\skid_buffer_reg_n_0_[16] ),
.R(1'b0));
FDRE \skid_buffer_reg[17]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[17]),
.Q(\skid_buffer_reg_n_0_[17] ),
.R(1'b0));
FDRE \skid_buffer_reg[18]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[18]),
.Q(\skid_buffer_reg_n_0_[18] ),
.R(1'b0));
FDRE \skid_buffer_reg[19]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[19]),
.Q(\skid_buffer_reg_n_0_[19] ),
.R(1'b0));
FDRE \skid_buffer_reg[1]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[1]),
.Q(\skid_buffer_reg_n_0_[1] ),
.R(1'b0));
FDRE \skid_buffer_reg[20]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[20]),
.Q(\skid_buffer_reg_n_0_[20] ),
.R(1'b0));
FDRE \skid_buffer_reg[21]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[21]),
.Q(\skid_buffer_reg_n_0_[21] ),
.R(1'b0));
FDRE \skid_buffer_reg[22]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[22]),
.Q(\skid_buffer_reg_n_0_[22] ),
.R(1'b0));
FDRE \skid_buffer_reg[23]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[23]),
.Q(\skid_buffer_reg_n_0_[23] ),
.R(1'b0));
FDRE \skid_buffer_reg[24]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[24]),
.Q(\skid_buffer_reg_n_0_[24] ),
.R(1'b0));
FDRE \skid_buffer_reg[25]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[25]),
.Q(\skid_buffer_reg_n_0_[25] ),
.R(1'b0));
FDRE \skid_buffer_reg[26]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[26]),
.Q(\skid_buffer_reg_n_0_[26] ),
.R(1'b0));
FDRE \skid_buffer_reg[27]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[27]),
.Q(\skid_buffer_reg_n_0_[27] ),
.R(1'b0));
FDRE \skid_buffer_reg[28]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[28]),
.Q(\skid_buffer_reg_n_0_[28] ),
.R(1'b0));
FDRE \skid_buffer_reg[29]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[29]),
.Q(\skid_buffer_reg_n_0_[29] ),
.R(1'b0));
FDRE \skid_buffer_reg[2]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[2]),
.Q(\skid_buffer_reg_n_0_[2] ),
.R(1'b0));
FDRE \skid_buffer_reg[30]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[30]),
.Q(\skid_buffer_reg_n_0_[30] ),
.R(1'b0));
FDRE \skid_buffer_reg[31]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[31]),
.Q(\skid_buffer_reg_n_0_[31] ),
.R(1'b0));
FDRE \skid_buffer_reg[32]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awprot[0]),
.Q(\skid_buffer_reg_n_0_[32] ),
.R(1'b0));
FDRE \skid_buffer_reg[33]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awprot[1]),
.Q(\skid_buffer_reg_n_0_[33] ),
.R(1'b0));
FDRE \skid_buffer_reg[34]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awprot[2]),
.Q(\skid_buffer_reg_n_0_[34] ),
.R(1'b0));
FDRE \skid_buffer_reg[35]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awsize[0]),
.Q(\skid_buffer_reg_n_0_[35] ),
.R(1'b0));
FDRE \skid_buffer_reg[36]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awsize[1]),
.Q(\skid_buffer_reg_n_0_[36] ),
.R(1'b0));
FDRE \skid_buffer_reg[38]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awburst[0]),
.Q(\skid_buffer_reg_n_0_[38] ),
.R(1'b0));
FDRE \skid_buffer_reg[39]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awburst[1]),
.Q(\skid_buffer_reg_n_0_[39] ),
.R(1'b0));
FDRE \skid_buffer_reg[3]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[3]),
.Q(\skid_buffer_reg_n_0_[3] ),
.R(1'b0));
FDRE \skid_buffer_reg[44]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awlen[0]),
.Q(\skid_buffer_reg_n_0_[44] ),
.R(1'b0));
FDRE \skid_buffer_reg[45]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awlen[1]),
.Q(\skid_buffer_reg_n_0_[45] ),
.R(1'b0));
FDRE \skid_buffer_reg[46]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awlen[2]),
.Q(\skid_buffer_reg_n_0_[46] ),
.R(1'b0));
FDRE \skid_buffer_reg[47]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awlen[3]),
.Q(\skid_buffer_reg_n_0_[47] ),
.R(1'b0));
FDRE \skid_buffer_reg[48]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awlen[4]),
.Q(\skid_buffer_reg_n_0_[48] ),
.R(1'b0));
FDRE \skid_buffer_reg[49]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awlen[5]),
.Q(\skid_buffer_reg_n_0_[49] ),
.R(1'b0));
FDRE \skid_buffer_reg[4]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[4]),
.Q(\skid_buffer_reg_n_0_[4] ),
.R(1'b0));
FDRE \skid_buffer_reg[50]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awlen[6]),
.Q(\skid_buffer_reg_n_0_[50] ),
.R(1'b0));
FDRE \skid_buffer_reg[51]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awlen[7]),
.Q(\skid_buffer_reg_n_0_[51] ),
.R(1'b0));
FDRE \skid_buffer_reg[53]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[0]),
.Q(\skid_buffer_reg_n_0_[53] ),
.R(1'b0));
FDRE \skid_buffer_reg[54]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[1]),
.Q(\skid_buffer_reg_n_0_[54] ),
.R(1'b0));
FDRE \skid_buffer_reg[55]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[2]),
.Q(\skid_buffer_reg_n_0_[55] ),
.R(1'b0));
FDRE \skid_buffer_reg[56]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[3]),
.Q(\skid_buffer_reg_n_0_[56] ),
.R(1'b0));
FDRE \skid_buffer_reg[57]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[4]),
.Q(\skid_buffer_reg_n_0_[57] ),
.R(1'b0));
FDRE \skid_buffer_reg[58]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[5]),
.Q(\skid_buffer_reg_n_0_[58] ),
.R(1'b0));
FDRE \skid_buffer_reg[59]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[6]),
.Q(\skid_buffer_reg_n_0_[59] ),
.R(1'b0));
FDRE \skid_buffer_reg[5]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[5]),
.Q(\skid_buffer_reg_n_0_[5] ),
.R(1'b0));
FDRE \skid_buffer_reg[60]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[7]),
.Q(\skid_buffer_reg_n_0_[60] ),
.R(1'b0));
FDRE \skid_buffer_reg[61]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[8]),
.Q(\skid_buffer_reg_n_0_[61] ),
.R(1'b0));
FDRE \skid_buffer_reg[62]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[9]),
.Q(\skid_buffer_reg_n_0_[62] ),
.R(1'b0));
FDRE \skid_buffer_reg[63]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[10]),
.Q(\skid_buffer_reg_n_0_[63] ),
.R(1'b0));
FDRE \skid_buffer_reg[64]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[11]),
.Q(\skid_buffer_reg_n_0_[64] ),
.R(1'b0));
FDRE \skid_buffer_reg[6]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[6]),
.Q(\skid_buffer_reg_n_0_[6] ),
.R(1'b0));
FDRE \skid_buffer_reg[7]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[7]),
.Q(\skid_buffer_reg_n_0_[7] ),
.R(1'b0));
FDRE \skid_buffer_reg[8]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[8]),
.Q(\skid_buffer_reg_n_0_[8] ),
.R(1'b0));
FDRE \skid_buffer_reg[9]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[9]),
.Q(\skid_buffer_reg_n_0_[9] ),
.R(1'b0));
LUT4 #(
.INIT(16'hAA8A))
\wrap_boundary_axaddr_r[0]_i_1
(.I0(Q[0]),
.I1(Q[36]),
.I2(Q[39]),
.I3(Q[35]),
.O(\wrap_boundary_axaddr_r_reg[6] [0]));
LUT5 #(
.INIT(32'h8A888AAA))
\wrap_boundary_axaddr_r[1]_i_1
(.I0(Q[1]),
.I1(Q[36]),
.I2(Q[39]),
.I3(Q[35]),
.I4(Q[40]),
.O(\wrap_boundary_axaddr_r_reg[6] [1]));
LUT6 #(
.INIT(64'hA0A0202AAAAA202A))
\wrap_boundary_axaddr_r[2]_i_1
(.I0(Q[2]),
.I1(Q[40]),
.I2(Q[35]),
.I3(Q[41]),
.I4(Q[36]),
.I5(Q[39]),
.O(\wrap_boundary_axaddr_r_reg[6] [2]));
LUT6 #(
.INIT(64'h020202A2A2A202A2))
\wrap_boundary_axaddr_r[3]_i_1
(.I0(Q[3]),
.I1(\wrap_boundary_axaddr_r[3]_i_2_n_0 ),
.I2(Q[36]),
.I3(Q[40]),
.I4(Q[35]),
.I5(Q[39]),
.O(\wrap_boundary_axaddr_r_reg[6] [3]));
(* SOFT_HLUTNM = "soft_lutpair45" *)
LUT3 #(
.INIT(8'hB8))
\wrap_boundary_axaddr_r[3]_i_2
(.I0(Q[41]),
.I1(Q[35]),
.I2(Q[42]),
.O(\wrap_boundary_axaddr_r[3]_i_2_n_0 ));
LUT6 #(
.INIT(64'h002A882A222AAA2A))
\wrap_boundary_axaddr_r[4]_i_1
(.I0(Q[4]),
.I1(Q[35]),
.I2(Q[42]),
.I3(Q[36]),
.I4(Q[40]),
.I5(Q[41]),
.O(\wrap_boundary_axaddr_r_reg[6] [4]));
(* SOFT_HLUTNM = "soft_lutpair45" *)
LUT5 #(
.INIT(32'h2A222AAA))
\wrap_boundary_axaddr_r[5]_i_1
(.I0(Q[5]),
.I1(Q[36]),
.I2(Q[41]),
.I3(Q[35]),
.I4(Q[42]),
.O(\wrap_boundary_axaddr_r_reg[6] [5]));
LUT4 #(
.INIT(16'h2AAA))
\wrap_boundary_axaddr_r[6]_i_1
(.I0(Q[6]),
.I1(Q[36]),
.I2(Q[42]),
.I3(Q[35]),
.O(\wrap_boundary_axaddr_r_reg[6] [6]));
LUT6 #(
.INIT(64'hBBBBBABBCCCCC0CC))
\wrap_cnt_r[0]_i_1
(.I0(\wrap_second_len_r[0]_i_2_n_0 ),
.I1(\wrap_second_len_r_reg[3]_0 [0]),
.I2(\state_reg[1] [0]),
.I3(m_valid_i_reg_0),
.I4(\state_reg[1] [1]),
.I5(\wrap_second_len_r[0]_i_3_n_0 ),
.O(D[0]));
(* SOFT_HLUTNM = "soft_lutpair47" *)
LUT3 #(
.INIT(8'h9A))
\wrap_cnt_r[2]_i_1
(.I0(\wrap_second_len_r_reg[3] [1]),
.I1(\wrap_cnt_r_reg[3] ),
.I2(wrap_second_len),
.O(D[1]));
(* SOFT_HLUTNM = "soft_lutpair47" *)
LUT4 #(
.INIT(16'hA6AA))
\wrap_cnt_r[3]_i_1
(.I0(\wrap_second_len_r_reg[3] [2]),
.I1(wrap_second_len),
.I2(\wrap_cnt_r_reg[3] ),
.I3(\wrap_second_len_r_reg[3] [1]),
.O(D[2]));
LUT5 #(
.INIT(32'hAAAAAAAB))
\wrap_cnt_r[3]_i_2
(.I0(\wrap_cnt_r[3]_i_3_n_0 ),
.I1(\axaddr_offset_r_reg[1] ),
.I2(\axaddr_offset_r_reg[0] ),
.I3(\axaddr_offset_r_reg[3]_0 ),
.I4(\axaddr_offset_r_reg[2] ),
.O(\wrap_cnt_r_reg[3] ));
LUT6 #(
.INIT(64'h0F0F0F0F0F880F0F))
\wrap_cnt_r[3]_i_3
(.I0(\axaddr_offset_r[0]_i_2_n_0 ),
.I1(Q[39]),
.I2(\wrap_second_len_r_reg[3]_0 [0]),
.I3(\state_reg[1] [1]),
.I4(m_valid_i_reg_0),
.I5(\state_reg[1] [0]),
.O(\wrap_cnt_r[3]_i_3_n_0 ));
LUT6 #(
.INIT(64'h4444454444444044))
\wrap_second_len_r[0]_i_1
(.I0(\wrap_second_len_r[0]_i_2_n_0 ),
.I1(\wrap_second_len_r_reg[3]_0 [0]),
.I2(\state_reg[1] [0]),
.I3(m_valid_i_reg_0),
.I4(\state_reg[1] [1]),
.I5(\wrap_second_len_r[0]_i_3_n_0 ),
.O(\wrap_second_len_r_reg[3] [0]));
LUT6 #(
.INIT(64'hAAAAA8080000A808))
\wrap_second_len_r[0]_i_2
(.I0(\wrap_second_len_r[0]_i_4_n_0 ),
.I1(Q[0]),
.I2(Q[36]),
.I3(Q[2]),
.I4(Q[35]),
.I5(\axaddr_offset_r[1]_i_2_n_0 ),
.O(\wrap_second_len_r[0]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFBA))
\wrap_second_len_r[0]_i_3
(.I0(\axaddr_offset_r_reg[2] ),
.I1(\state_reg[1]_rep_0 ),
.I2(\axaddr_offset_r_reg[3]_1 [3]),
.I3(\wrap_second_len_r[3]_i_2_n_0 ),
.I4(\axaddr_offset_r_reg[0] ),
.I5(\axaddr_offset_r_reg[1] ),
.O(\wrap_second_len_r[0]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair46" *)
LUT4 #(
.INIT(16'h0020))
\wrap_second_len_r[0]_i_4
(.I0(Q[39]),
.I1(\state_reg[0]_rep ),
.I2(m_valid_i_reg_0),
.I3(\state_reg[1]_rep ),
.O(\wrap_second_len_r[0]_i_4_n_0 ));
LUT6 #(
.INIT(64'hEE10FFFFEE100000))
\wrap_second_len_r[2]_i_1
(.I0(\axaddr_offset_r_reg[1] ),
.I1(\axaddr_offset_r_reg[0] ),
.I2(\axaddr_offset_r_reg[3]_0 ),
.I3(\axaddr_offset_r_reg[2] ),
.I4(\state_reg[1]_rep_0 ),
.I5(\wrap_second_len_r_reg[3]_0 [1]),
.O(\wrap_second_len_r_reg[3] [1]));
LUT6 #(
.INIT(64'hFFFFFFF444444444))
\wrap_second_len_r[3]_i_1
(.I0(\state_reg[1]_rep_0 ),
.I1(\wrap_second_len_r_reg[3]_0 [2]),
.I2(\axaddr_offset_r_reg[0] ),
.I3(\axaddr_offset_r_reg[1] ),
.I4(\axaddr_offset_r_reg[2] ),
.I5(\wrap_second_len_r[3]_i_2_n_0 ),
.O(\wrap_second_len_r_reg[3] [2]));
LUT6 #(
.INIT(64'h00000000EEE222E2))
\wrap_second_len_r[3]_i_2
(.I0(\axaddr_offset_r[2]_i_2_n_0 ),
.I1(Q[35]),
.I2(Q[4]),
.I3(Q[36]),
.I4(Q[6]),
.I5(\axlen_cnt_reg[3] ),
.O(\wrap_second_len_r[3]_i_2_n_0 ));
endmodule
(* ORIG_REF_NAME = "axi_register_slice_v2_1_13_axic_register_slice" *)
module zqynq_lab_1_design_auto_pc_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1
(s_axi_bvalid,
\skid_buffer_reg[0]_0 ,
\s_axi_bid[11] ,
\aresetn_d_reg[1]_inv ,
aclk,
\aresetn_d_reg[0] ,
si_rs_bvalid,
s_axi_bready,
out,
\s_bresp_acc_reg[1] );
output s_axi_bvalid;
output \skid_buffer_reg[0]_0 ;
output [13:0]\s_axi_bid[11] ;
input \aresetn_d_reg[1]_inv ;
input aclk;
input \aresetn_d_reg[0] ;
input si_rs_bvalid;
input s_axi_bready;
input [11:0]out;
input [1:0]\s_bresp_acc_reg[1] ;
wire aclk;
wire \aresetn_d_reg[0] ;
wire \aresetn_d_reg[1]_inv ;
wire \m_payload_i[0]_i_1__1_n_0 ;
wire \m_payload_i[10]_i_1__1_n_0 ;
wire \m_payload_i[11]_i_1__1_n_0 ;
wire \m_payload_i[12]_i_1__1_n_0 ;
wire \m_payload_i[13]_i_2_n_0 ;
wire \m_payload_i[1]_i_1__1_n_0 ;
wire \m_payload_i[2]_i_1__1_n_0 ;
wire \m_payload_i[3]_i_1__1_n_0 ;
wire \m_payload_i[4]_i_1__1_n_0 ;
wire \m_payload_i[5]_i_1__1_n_0 ;
wire \m_payload_i[6]_i_1__1_n_0 ;
wire \m_payload_i[7]_i_1__1_n_0 ;
wire \m_payload_i[8]_i_1__1_n_0 ;
wire \m_payload_i[9]_i_1__1_n_0 ;
wire m_valid_i0;
wire [11:0]out;
wire p_1_in;
wire [13:0]\s_axi_bid[11] ;
wire s_axi_bready;
wire s_axi_bvalid;
wire [1:0]\s_bresp_acc_reg[1] ;
wire s_ready_i0;
wire si_rs_bvalid;
wire \skid_buffer_reg[0]_0 ;
wire \skid_buffer_reg_n_0_[0] ;
wire \skid_buffer_reg_n_0_[10] ;
wire \skid_buffer_reg_n_0_[11] ;
wire \skid_buffer_reg_n_0_[12] ;
wire \skid_buffer_reg_n_0_[13] ;
wire \skid_buffer_reg_n_0_[1] ;
wire \skid_buffer_reg_n_0_[2] ;
wire \skid_buffer_reg_n_0_[3] ;
wire \skid_buffer_reg_n_0_[4] ;
wire \skid_buffer_reg_n_0_[5] ;
wire \skid_buffer_reg_n_0_[6] ;
wire \skid_buffer_reg_n_0_[7] ;
wire \skid_buffer_reg_n_0_[8] ;
wire \skid_buffer_reg_n_0_[9] ;
(* SOFT_HLUTNM = "soft_lutpair84" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[0]_i_1__1
(.I0(\s_bresp_acc_reg[1] [0]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[0] ),
.O(\m_payload_i[0]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair79" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[10]_i_1__1
(.I0(out[8]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[10] ),
.O(\m_payload_i[10]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair78" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[11]_i_1__1
(.I0(out[9]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[11] ),
.O(\m_payload_i[11]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair79" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[12]_i_1__1
(.I0(out[10]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[12] ),
.O(\m_payload_i[12]_i_1__1_n_0 ));
LUT2 #(
.INIT(4'hB))
\m_payload_i[13]_i_1
(.I0(s_axi_bready),
.I1(s_axi_bvalid),
.O(p_1_in));
(* SOFT_HLUTNM = "soft_lutpair78" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[13]_i_2
(.I0(out[11]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[13] ),
.O(\m_payload_i[13]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair84" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[1]_i_1__1
(.I0(\s_bresp_acc_reg[1] [1]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[1] ),
.O(\m_payload_i[1]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair83" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[2]_i_1__1
(.I0(out[0]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[2] ),
.O(\m_payload_i[2]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair83" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[3]_i_1__1
(.I0(out[1]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[3] ),
.O(\m_payload_i[3]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair82" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[4]_i_1__1
(.I0(out[2]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[4] ),
.O(\m_payload_i[4]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair82" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[5]_i_1__1
(.I0(out[3]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[5] ),
.O(\m_payload_i[5]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair81" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[6]_i_1__1
(.I0(out[4]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[6] ),
.O(\m_payload_i[6]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair81" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[7]_i_1__1
(.I0(out[5]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[7] ),
.O(\m_payload_i[7]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair80" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[8]_i_1__1
(.I0(out[6]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[8] ),
.O(\m_payload_i[8]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair80" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[9]_i_1__1
(.I0(out[7]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[9] ),
.O(\m_payload_i[9]_i_1__1_n_0 ));
FDRE \m_payload_i_reg[0]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[0]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [0]),
.R(1'b0));
FDRE \m_payload_i_reg[10]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[10]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [10]),
.R(1'b0));
FDRE \m_payload_i_reg[11]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[11]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [11]),
.R(1'b0));
FDRE \m_payload_i_reg[12]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[12]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [12]),
.R(1'b0));
FDRE \m_payload_i_reg[13]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[13]_i_2_n_0 ),
.Q(\s_axi_bid[11] [13]),
.R(1'b0));
FDRE \m_payload_i_reg[1]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[1]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [1]),
.R(1'b0));
FDRE \m_payload_i_reg[2]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[2]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [2]),
.R(1'b0));
FDRE \m_payload_i_reg[3]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[3]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [3]),
.R(1'b0));
FDRE \m_payload_i_reg[4]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[4]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [4]),
.R(1'b0));
FDRE \m_payload_i_reg[5]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[5]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [5]),
.R(1'b0));
FDRE \m_payload_i_reg[6]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[6]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [6]),
.R(1'b0));
FDRE \m_payload_i_reg[7]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[7]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [7]),
.R(1'b0));
FDRE \m_payload_i_reg[8]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[8]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [8]),
.R(1'b0));
FDRE \m_payload_i_reg[9]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[9]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [9]),
.R(1'b0));
LUT4 #(
.INIT(16'hF4FF))
m_valid_i_i_1
(.I0(s_axi_bready),
.I1(s_axi_bvalid),
.I2(si_rs_bvalid),
.I3(\skid_buffer_reg[0]_0 ),
.O(m_valid_i0));
FDRE #(
.INIT(1'b0))
m_valid_i_reg
(.C(aclk),
.CE(1'b1),
.D(m_valid_i0),
.Q(s_axi_bvalid),
.R(\aresetn_d_reg[1]_inv ));
LUT4 #(
.INIT(16'hF4FF))
s_ready_i_i_1
(.I0(si_rs_bvalid),
.I1(\skid_buffer_reg[0]_0 ),
.I2(s_axi_bready),
.I3(s_axi_bvalid),
.O(s_ready_i0));
FDRE #(
.INIT(1'b0))
s_ready_i_reg
(.C(aclk),
.CE(1'b1),
.D(s_ready_i0),
.Q(\skid_buffer_reg[0]_0 ),
.R(\aresetn_d_reg[0] ));
FDRE \skid_buffer_reg[0]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\s_bresp_acc_reg[1] [0]),
.Q(\skid_buffer_reg_n_0_[0] ),
.R(1'b0));
FDRE \skid_buffer_reg[10]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[8]),
.Q(\skid_buffer_reg_n_0_[10] ),
.R(1'b0));
FDRE \skid_buffer_reg[11]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[9]),
.Q(\skid_buffer_reg_n_0_[11] ),
.R(1'b0));
FDRE \skid_buffer_reg[12]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[10]),
.Q(\skid_buffer_reg_n_0_[12] ),
.R(1'b0));
FDRE \skid_buffer_reg[13]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[11]),
.Q(\skid_buffer_reg_n_0_[13] ),
.R(1'b0));
FDRE \skid_buffer_reg[1]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\s_bresp_acc_reg[1] [1]),
.Q(\skid_buffer_reg_n_0_[1] ),
.R(1'b0));
FDRE \skid_buffer_reg[2]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[0]),
.Q(\skid_buffer_reg_n_0_[2] ),
.R(1'b0));
FDRE \skid_buffer_reg[3]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[1]),
.Q(\skid_buffer_reg_n_0_[3] ),
.R(1'b0));
FDRE \skid_buffer_reg[4]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[2]),
.Q(\skid_buffer_reg_n_0_[4] ),
.R(1'b0));
FDRE \skid_buffer_reg[5]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[3]),
.Q(\skid_buffer_reg_n_0_[5] ),
.R(1'b0));
FDRE \skid_buffer_reg[6]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[4]),
.Q(\skid_buffer_reg_n_0_[6] ),
.R(1'b0));
FDRE \skid_buffer_reg[7]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[5]),
.Q(\skid_buffer_reg_n_0_[7] ),
.R(1'b0));
FDRE \skid_buffer_reg[8]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[6]),
.Q(\skid_buffer_reg_n_0_[8] ),
.R(1'b0));
FDRE \skid_buffer_reg[9]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[7]),
.Q(\skid_buffer_reg_n_0_[9] ),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "axi_register_slice_v2_1_13_axic_register_slice" *)
module zqynq_lab_1_design_auto_pc_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2
(s_axi_rvalid,
\skid_buffer_reg[0]_0 ,
\cnt_read_reg[3]_rep__0 ,
\s_axi_rid[11] ,
\aresetn_d_reg[1]_inv ,
aclk,
\aresetn_d_reg[0] ,
\cnt_read_reg[4]_rep__0 ,
s_axi_rready,
r_push_r_reg,
\cnt_read_reg[4] );
output s_axi_rvalid;
output \skid_buffer_reg[0]_0 ;
output \cnt_read_reg[3]_rep__0 ;
output [46:0]\s_axi_rid[11] ;
input \aresetn_d_reg[1]_inv ;
input aclk;
input \aresetn_d_reg[0] ;
input \cnt_read_reg[4]_rep__0 ;
input s_axi_rready;
input [12:0]r_push_r_reg;
input [33:0]\cnt_read_reg[4] ;
wire aclk;
wire \aresetn_d_reg[0] ;
wire \aresetn_d_reg[1]_inv ;
wire \cnt_read_reg[3]_rep__0 ;
wire [33:0]\cnt_read_reg[4] ;
wire \cnt_read_reg[4]_rep__0 ;
wire \m_payload_i[0]_i_1__2_n_0 ;
wire \m_payload_i[10]_i_1__2_n_0 ;
wire \m_payload_i[11]_i_1__2_n_0 ;
wire \m_payload_i[12]_i_1__2_n_0 ;
wire \m_payload_i[13]_i_1__2_n_0 ;
wire \m_payload_i[14]_i_1__1_n_0 ;
wire \m_payload_i[15]_i_1__1_n_0 ;
wire \m_payload_i[16]_i_1__1_n_0 ;
wire \m_payload_i[17]_i_1__1_n_0 ;
wire \m_payload_i[18]_i_1__1_n_0 ;
wire \m_payload_i[19]_i_1__1_n_0 ;
wire \m_payload_i[1]_i_1__2_n_0 ;
wire \m_payload_i[20]_i_1__1_n_0 ;
wire \m_payload_i[21]_i_1__1_n_0 ;
wire \m_payload_i[22]_i_1__1_n_0 ;
wire \m_payload_i[23]_i_1__1_n_0 ;
wire \m_payload_i[24]_i_1__1_n_0 ;
wire \m_payload_i[25]_i_1__1_n_0 ;
wire \m_payload_i[26]_i_1__1_n_0 ;
wire \m_payload_i[27]_i_1__1_n_0 ;
wire \m_payload_i[28]_i_1__1_n_0 ;
wire \m_payload_i[29]_i_1__1_n_0 ;
wire \m_payload_i[2]_i_1__2_n_0 ;
wire \m_payload_i[30]_i_1__1_n_0 ;
wire \m_payload_i[31]_i_1__1_n_0 ;
wire \m_payload_i[32]_i_1__1_n_0 ;
wire \m_payload_i[33]_i_1__1_n_0 ;
wire \m_payload_i[34]_i_1__1_n_0 ;
wire \m_payload_i[35]_i_1__1_n_0 ;
wire \m_payload_i[36]_i_1__1_n_0 ;
wire \m_payload_i[37]_i_1_n_0 ;
wire \m_payload_i[38]_i_1__1_n_0 ;
wire \m_payload_i[39]_i_1__1_n_0 ;
wire \m_payload_i[3]_i_1__2_n_0 ;
wire \m_payload_i[40]_i_1_n_0 ;
wire \m_payload_i[41]_i_1_n_0 ;
wire \m_payload_i[42]_i_1_n_0 ;
wire \m_payload_i[43]_i_1_n_0 ;
wire \m_payload_i[44]_i_1__1_n_0 ;
wire \m_payload_i[45]_i_1__1_n_0 ;
wire \m_payload_i[46]_i_2_n_0 ;
wire \m_payload_i[4]_i_1__2_n_0 ;
wire \m_payload_i[5]_i_1__2_n_0 ;
wire \m_payload_i[6]_i_1__2_n_0 ;
wire \m_payload_i[7]_i_1__2_n_0 ;
wire \m_payload_i[8]_i_1__2_n_0 ;
wire \m_payload_i[9]_i_1__2_n_0 ;
wire m_valid_i_i_1__1_n_0;
wire p_1_in;
wire [12:0]r_push_r_reg;
wire [46:0]\s_axi_rid[11] ;
wire s_axi_rready;
wire s_axi_rvalid;
wire s_ready_i_i_1__2_n_0;
wire \skid_buffer_reg[0]_0 ;
wire \skid_buffer_reg_n_0_[0] ;
wire \skid_buffer_reg_n_0_[10] ;
wire \skid_buffer_reg_n_0_[11] ;
wire \skid_buffer_reg_n_0_[12] ;
wire \skid_buffer_reg_n_0_[13] ;
wire \skid_buffer_reg_n_0_[14] ;
wire \skid_buffer_reg_n_0_[15] ;
wire \skid_buffer_reg_n_0_[16] ;
wire \skid_buffer_reg_n_0_[17] ;
wire \skid_buffer_reg_n_0_[18] ;
wire \skid_buffer_reg_n_0_[19] ;
wire \skid_buffer_reg_n_0_[1] ;
wire \skid_buffer_reg_n_0_[20] ;
wire \skid_buffer_reg_n_0_[21] ;
wire \skid_buffer_reg_n_0_[22] ;
wire \skid_buffer_reg_n_0_[23] ;
wire \skid_buffer_reg_n_0_[24] ;
wire \skid_buffer_reg_n_0_[25] ;
wire \skid_buffer_reg_n_0_[26] ;
wire \skid_buffer_reg_n_0_[27] ;
wire \skid_buffer_reg_n_0_[28] ;
wire \skid_buffer_reg_n_0_[29] ;
wire \skid_buffer_reg_n_0_[2] ;
wire \skid_buffer_reg_n_0_[30] ;
wire \skid_buffer_reg_n_0_[31] ;
wire \skid_buffer_reg_n_0_[32] ;
wire \skid_buffer_reg_n_0_[33] ;
wire \skid_buffer_reg_n_0_[34] ;
wire \skid_buffer_reg_n_0_[35] ;
wire \skid_buffer_reg_n_0_[36] ;
wire \skid_buffer_reg_n_0_[37] ;
wire \skid_buffer_reg_n_0_[38] ;
wire \skid_buffer_reg_n_0_[39] ;
wire \skid_buffer_reg_n_0_[3] ;
wire \skid_buffer_reg_n_0_[40] ;
wire \skid_buffer_reg_n_0_[41] ;
wire \skid_buffer_reg_n_0_[42] ;
wire \skid_buffer_reg_n_0_[43] ;
wire \skid_buffer_reg_n_0_[44] ;
wire \skid_buffer_reg_n_0_[45] ;
wire \skid_buffer_reg_n_0_[46] ;
wire \skid_buffer_reg_n_0_[4] ;
wire \skid_buffer_reg_n_0_[5] ;
wire \skid_buffer_reg_n_0_[6] ;
wire \skid_buffer_reg_n_0_[7] ;
wire \skid_buffer_reg_n_0_[8] ;
wire \skid_buffer_reg_n_0_[9] ;
(* SOFT_HLUTNM = "soft_lutpair85" *)
LUT2 #(
.INIT(4'h2))
\cnt_read[3]_i_2
(.I0(\skid_buffer_reg[0]_0 ),
.I1(\cnt_read_reg[4]_rep__0 ),
.O(\cnt_read_reg[3]_rep__0 ));
LUT3 #(
.INIT(8'hB8))
\m_payload_i[0]_i_1__2
(.I0(\cnt_read_reg[4] [0]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[0] ),
.O(\m_payload_i[0]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair104" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[10]_i_1__2
(.I0(\cnt_read_reg[4] [10]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[10] ),
.O(\m_payload_i[10]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair103" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[11]_i_1__2
(.I0(\cnt_read_reg[4] [11]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[11] ),
.O(\m_payload_i[11]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair103" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[12]_i_1__2
(.I0(\cnt_read_reg[4] [12]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[12] ),
.O(\m_payload_i[12]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair102" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[13]_i_1__2
(.I0(\cnt_read_reg[4] [13]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[13] ),
.O(\m_payload_i[13]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair102" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[14]_i_1__1
(.I0(\cnt_read_reg[4] [14]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[14] ),
.O(\m_payload_i[14]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair101" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[15]_i_1__1
(.I0(\cnt_read_reg[4] [15]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[15] ),
.O(\m_payload_i[15]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair101" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[16]_i_1__1
(.I0(\cnt_read_reg[4] [16]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[16] ),
.O(\m_payload_i[16]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair100" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[17]_i_1__1
(.I0(\cnt_read_reg[4] [17]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[17] ),
.O(\m_payload_i[17]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair100" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[18]_i_1__1
(.I0(\cnt_read_reg[4] [18]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[18] ),
.O(\m_payload_i[18]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair99" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[19]_i_1__1
(.I0(\cnt_read_reg[4] [19]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[19] ),
.O(\m_payload_i[19]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair108" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[1]_i_1__2
(.I0(\cnt_read_reg[4] [1]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[1] ),
.O(\m_payload_i[1]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair99" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[20]_i_1__1
(.I0(\cnt_read_reg[4] [20]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[20] ),
.O(\m_payload_i[20]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair98" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[21]_i_1__1
(.I0(\cnt_read_reg[4] [21]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[21] ),
.O(\m_payload_i[21]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair98" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[22]_i_1__1
(.I0(\cnt_read_reg[4] [22]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[22] ),
.O(\m_payload_i[22]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair97" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[23]_i_1__1
(.I0(\cnt_read_reg[4] [23]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[23] ),
.O(\m_payload_i[23]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair97" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[24]_i_1__1
(.I0(\cnt_read_reg[4] [24]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[24] ),
.O(\m_payload_i[24]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair96" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[25]_i_1__1
(.I0(\cnt_read_reg[4] [25]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[25] ),
.O(\m_payload_i[25]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair96" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[26]_i_1__1
(.I0(\cnt_read_reg[4] [26]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[26] ),
.O(\m_payload_i[26]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair95" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[27]_i_1__1
(.I0(\cnt_read_reg[4] [27]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[27] ),
.O(\m_payload_i[27]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair95" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[28]_i_1__1
(.I0(\cnt_read_reg[4] [28]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[28] ),
.O(\m_payload_i[28]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair94" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[29]_i_1__1
(.I0(\cnt_read_reg[4] [29]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[29] ),
.O(\m_payload_i[29]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair108" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[2]_i_1__2
(.I0(\cnt_read_reg[4] [2]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[2] ),
.O(\m_payload_i[2]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair94" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[30]_i_1__1
(.I0(\cnt_read_reg[4] [30]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[30] ),
.O(\m_payload_i[30]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair93" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[31]_i_1__1
(.I0(\cnt_read_reg[4] [31]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[31] ),
.O(\m_payload_i[31]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair93" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[32]_i_1__1
(.I0(\cnt_read_reg[4] [32]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[32] ),
.O(\m_payload_i[32]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair92" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[33]_i_1__1
(.I0(\cnt_read_reg[4] [33]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[33] ),
.O(\m_payload_i[33]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair92" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[34]_i_1__1
(.I0(r_push_r_reg[0]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[34] ),
.O(\m_payload_i[34]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair91" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[35]_i_1__1
(.I0(r_push_r_reg[1]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[35] ),
.O(\m_payload_i[35]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair91" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[36]_i_1__1
(.I0(r_push_r_reg[2]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[36] ),
.O(\m_payload_i[36]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair90" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[37]_i_1
(.I0(r_push_r_reg[3]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[37] ),
.O(\m_payload_i[37]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair90" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[38]_i_1__1
(.I0(r_push_r_reg[4]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[38] ),
.O(\m_payload_i[38]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair89" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[39]_i_1__1
(.I0(r_push_r_reg[5]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[39] ),
.O(\m_payload_i[39]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair107" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[3]_i_1__2
(.I0(\cnt_read_reg[4] [3]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[3] ),
.O(\m_payload_i[3]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair89" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[40]_i_1
(.I0(r_push_r_reg[6]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[40] ),
.O(\m_payload_i[40]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair88" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[41]_i_1
(.I0(r_push_r_reg[7]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[41] ),
.O(\m_payload_i[41]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair88" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[42]_i_1
(.I0(r_push_r_reg[8]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[42] ),
.O(\m_payload_i[42]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair86" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[43]_i_1
(.I0(r_push_r_reg[9]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[43] ),
.O(\m_payload_i[43]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair87" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[44]_i_1__1
(.I0(r_push_r_reg[10]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[44] ),
.O(\m_payload_i[44]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair87" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[45]_i_1__1
(.I0(r_push_r_reg[11]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[45] ),
.O(\m_payload_i[45]_i_1__1_n_0 ));
LUT2 #(
.INIT(4'hB))
\m_payload_i[46]_i_1
(.I0(s_axi_rready),
.I1(s_axi_rvalid),
.O(p_1_in));
(* SOFT_HLUTNM = "soft_lutpair86" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[46]_i_2
(.I0(r_push_r_reg[12]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[46] ),
.O(\m_payload_i[46]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair107" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[4]_i_1__2
(.I0(\cnt_read_reg[4] [4]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[4] ),
.O(\m_payload_i[4]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair106" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[5]_i_1__2
(.I0(\cnt_read_reg[4] [5]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[5] ),
.O(\m_payload_i[5]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair106" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[6]_i_1__2
(.I0(\cnt_read_reg[4] [6]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[6] ),
.O(\m_payload_i[6]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair105" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[7]_i_1__2
(.I0(\cnt_read_reg[4] [7]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[7] ),
.O(\m_payload_i[7]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair105" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[8]_i_1__2
(.I0(\cnt_read_reg[4] [8]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[8] ),
.O(\m_payload_i[8]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair104" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[9]_i_1__2
(.I0(\cnt_read_reg[4] [9]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[9] ),
.O(\m_payload_i[9]_i_1__2_n_0 ));
FDRE \m_payload_i_reg[0]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[0]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [0]),
.R(1'b0));
FDRE \m_payload_i_reg[10]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[10]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [10]),
.R(1'b0));
FDRE \m_payload_i_reg[11]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[11]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [11]),
.R(1'b0));
FDRE \m_payload_i_reg[12]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[12]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [12]),
.R(1'b0));
FDRE \m_payload_i_reg[13]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[13]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [13]),
.R(1'b0));
FDRE \m_payload_i_reg[14]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[14]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [14]),
.R(1'b0));
FDRE \m_payload_i_reg[15]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[15]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [15]),
.R(1'b0));
FDRE \m_payload_i_reg[16]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[16]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [16]),
.R(1'b0));
FDRE \m_payload_i_reg[17]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[17]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [17]),
.R(1'b0));
FDRE \m_payload_i_reg[18]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[18]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [18]),
.R(1'b0));
FDRE \m_payload_i_reg[19]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[19]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [19]),
.R(1'b0));
FDRE \m_payload_i_reg[1]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[1]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [1]),
.R(1'b0));
FDRE \m_payload_i_reg[20]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[20]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [20]),
.R(1'b0));
FDRE \m_payload_i_reg[21]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[21]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [21]),
.R(1'b0));
FDRE \m_payload_i_reg[22]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[22]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [22]),
.R(1'b0));
FDRE \m_payload_i_reg[23]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[23]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [23]),
.R(1'b0));
FDRE \m_payload_i_reg[24]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[24]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [24]),
.R(1'b0));
FDRE \m_payload_i_reg[25]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[25]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [25]),
.R(1'b0));
FDRE \m_payload_i_reg[26]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[26]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [26]),
.R(1'b0));
FDRE \m_payload_i_reg[27]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[27]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [27]),
.R(1'b0));
FDRE \m_payload_i_reg[28]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[28]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [28]),
.R(1'b0));
FDRE \m_payload_i_reg[29]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[29]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [29]),
.R(1'b0));
FDRE \m_payload_i_reg[2]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[2]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [2]),
.R(1'b0));
FDRE \m_payload_i_reg[30]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[30]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [30]),
.R(1'b0));
FDRE \m_payload_i_reg[31]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[31]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [31]),
.R(1'b0));
FDRE \m_payload_i_reg[32]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[32]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [32]),
.R(1'b0));
FDRE \m_payload_i_reg[33]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[33]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [33]),
.R(1'b0));
FDRE \m_payload_i_reg[34]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[34]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [34]),
.R(1'b0));
FDRE \m_payload_i_reg[35]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[35]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [35]),
.R(1'b0));
FDRE \m_payload_i_reg[36]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[36]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [36]),
.R(1'b0));
FDRE \m_payload_i_reg[37]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[37]_i_1_n_0 ),
.Q(\s_axi_rid[11] [37]),
.R(1'b0));
FDRE \m_payload_i_reg[38]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[38]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [38]),
.R(1'b0));
FDRE \m_payload_i_reg[39]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[39]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [39]),
.R(1'b0));
FDRE \m_payload_i_reg[3]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[3]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [3]),
.R(1'b0));
FDRE \m_payload_i_reg[40]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[40]_i_1_n_0 ),
.Q(\s_axi_rid[11] [40]),
.R(1'b0));
FDRE \m_payload_i_reg[41]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[41]_i_1_n_0 ),
.Q(\s_axi_rid[11] [41]),
.R(1'b0));
FDRE \m_payload_i_reg[42]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[42]_i_1_n_0 ),
.Q(\s_axi_rid[11] [42]),
.R(1'b0));
FDRE \m_payload_i_reg[43]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[43]_i_1_n_0 ),
.Q(\s_axi_rid[11] [43]),
.R(1'b0));
FDRE \m_payload_i_reg[44]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[44]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [44]),
.R(1'b0));
FDRE \m_payload_i_reg[45]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[45]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [45]),
.R(1'b0));
FDRE \m_payload_i_reg[46]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[46]_i_2_n_0 ),
.Q(\s_axi_rid[11] [46]),
.R(1'b0));
FDRE \m_payload_i_reg[4]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[4]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [4]),
.R(1'b0));
FDRE \m_payload_i_reg[5]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[5]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [5]),
.R(1'b0));
FDRE \m_payload_i_reg[6]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[6]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [6]),
.R(1'b0));
FDRE \m_payload_i_reg[7]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[7]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [7]),
.R(1'b0));
FDRE \m_payload_i_reg[8]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[8]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [8]),
.R(1'b0));
FDRE \m_payload_i_reg[9]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[9]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [9]),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair85" *)
LUT4 #(
.INIT(16'h4FFF))
m_valid_i_i_1__1
(.I0(s_axi_rready),
.I1(s_axi_rvalid),
.I2(\cnt_read_reg[4]_rep__0 ),
.I3(\skid_buffer_reg[0]_0 ),
.O(m_valid_i_i_1__1_n_0));
FDRE #(
.INIT(1'b0))
m_valid_i_reg
(.C(aclk),
.CE(1'b1),
.D(m_valid_i_i_1__1_n_0),
.Q(s_axi_rvalid),
.R(\aresetn_d_reg[1]_inv ));
LUT4 #(
.INIT(16'hF8FF))
s_ready_i_i_1__2
(.I0(\cnt_read_reg[4]_rep__0 ),
.I1(\skid_buffer_reg[0]_0 ),
.I2(s_axi_rready),
.I3(s_axi_rvalid),
.O(s_ready_i_i_1__2_n_0));
FDRE #(
.INIT(1'b0))
s_ready_i_reg
(.C(aclk),
.CE(1'b1),
.D(s_ready_i_i_1__2_n_0),
.Q(\skid_buffer_reg[0]_0 ),
.R(\aresetn_d_reg[0] ));
FDRE \skid_buffer_reg[0]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [0]),
.Q(\skid_buffer_reg_n_0_[0] ),
.R(1'b0));
FDRE \skid_buffer_reg[10]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [10]),
.Q(\skid_buffer_reg_n_0_[10] ),
.R(1'b0));
FDRE \skid_buffer_reg[11]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [11]),
.Q(\skid_buffer_reg_n_0_[11] ),
.R(1'b0));
FDRE \skid_buffer_reg[12]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [12]),
.Q(\skid_buffer_reg_n_0_[12] ),
.R(1'b0));
FDRE \skid_buffer_reg[13]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [13]),
.Q(\skid_buffer_reg_n_0_[13] ),
.R(1'b0));
FDRE \skid_buffer_reg[14]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [14]),
.Q(\skid_buffer_reg_n_0_[14] ),
.R(1'b0));
FDRE \skid_buffer_reg[15]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [15]),
.Q(\skid_buffer_reg_n_0_[15] ),
.R(1'b0));
FDRE \skid_buffer_reg[16]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [16]),
.Q(\skid_buffer_reg_n_0_[16] ),
.R(1'b0));
FDRE \skid_buffer_reg[17]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [17]),
.Q(\skid_buffer_reg_n_0_[17] ),
.R(1'b0));
FDRE \skid_buffer_reg[18]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [18]),
.Q(\skid_buffer_reg_n_0_[18] ),
.R(1'b0));
FDRE \skid_buffer_reg[19]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [19]),
.Q(\skid_buffer_reg_n_0_[19] ),
.R(1'b0));
FDRE \skid_buffer_reg[1]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [1]),
.Q(\skid_buffer_reg_n_0_[1] ),
.R(1'b0));
FDRE \skid_buffer_reg[20]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [20]),
.Q(\skid_buffer_reg_n_0_[20] ),
.R(1'b0));
FDRE \skid_buffer_reg[21]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [21]),
.Q(\skid_buffer_reg_n_0_[21] ),
.R(1'b0));
FDRE \skid_buffer_reg[22]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [22]),
.Q(\skid_buffer_reg_n_0_[22] ),
.R(1'b0));
FDRE \skid_buffer_reg[23]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [23]),
.Q(\skid_buffer_reg_n_0_[23] ),
.R(1'b0));
FDRE \skid_buffer_reg[24]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [24]),
.Q(\skid_buffer_reg_n_0_[24] ),
.R(1'b0));
FDRE \skid_buffer_reg[25]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [25]),
.Q(\skid_buffer_reg_n_0_[25] ),
.R(1'b0));
FDRE \skid_buffer_reg[26]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [26]),
.Q(\skid_buffer_reg_n_0_[26] ),
.R(1'b0));
FDRE \skid_buffer_reg[27]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [27]),
.Q(\skid_buffer_reg_n_0_[27] ),
.R(1'b0));
FDRE \skid_buffer_reg[28]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [28]),
.Q(\skid_buffer_reg_n_0_[28] ),
.R(1'b0));
FDRE \skid_buffer_reg[29]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [29]),
.Q(\skid_buffer_reg_n_0_[29] ),
.R(1'b0));
FDRE \skid_buffer_reg[2]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [2]),
.Q(\skid_buffer_reg_n_0_[2] ),
.R(1'b0));
FDRE \skid_buffer_reg[30]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [30]),
.Q(\skid_buffer_reg_n_0_[30] ),
.R(1'b0));
FDRE \skid_buffer_reg[31]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [31]),
.Q(\skid_buffer_reg_n_0_[31] ),
.R(1'b0));
FDRE \skid_buffer_reg[32]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [32]),
.Q(\skid_buffer_reg_n_0_[32] ),
.R(1'b0));
FDRE \skid_buffer_reg[33]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [33]),
.Q(\skid_buffer_reg_n_0_[33] ),
.R(1'b0));
FDRE \skid_buffer_reg[34]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[0]),
.Q(\skid_buffer_reg_n_0_[34] ),
.R(1'b0));
FDRE \skid_buffer_reg[35]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[1]),
.Q(\skid_buffer_reg_n_0_[35] ),
.R(1'b0));
FDRE \skid_buffer_reg[36]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[2]),
.Q(\skid_buffer_reg_n_0_[36] ),
.R(1'b0));
FDRE \skid_buffer_reg[37]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[3]),
.Q(\skid_buffer_reg_n_0_[37] ),
.R(1'b0));
FDRE \skid_buffer_reg[38]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[4]),
.Q(\skid_buffer_reg_n_0_[38] ),
.R(1'b0));
FDRE \skid_buffer_reg[39]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[5]),
.Q(\skid_buffer_reg_n_0_[39] ),
.R(1'b0));
FDRE \skid_buffer_reg[3]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [3]),
.Q(\skid_buffer_reg_n_0_[3] ),
.R(1'b0));
FDRE \skid_buffer_reg[40]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[6]),
.Q(\skid_buffer_reg_n_0_[40] ),
.R(1'b0));
FDRE \skid_buffer_reg[41]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[7]),
.Q(\skid_buffer_reg_n_0_[41] ),
.R(1'b0));
FDRE \skid_buffer_reg[42]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[8]),
.Q(\skid_buffer_reg_n_0_[42] ),
.R(1'b0));
FDRE \skid_buffer_reg[43]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[9]),
.Q(\skid_buffer_reg_n_0_[43] ),
.R(1'b0));
FDRE \skid_buffer_reg[44]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[10]),
.Q(\skid_buffer_reg_n_0_[44] ),
.R(1'b0));
FDRE \skid_buffer_reg[45]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[11]),
.Q(\skid_buffer_reg_n_0_[45] ),
.R(1'b0));
FDRE \skid_buffer_reg[46]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[12]),
.Q(\skid_buffer_reg_n_0_[46] ),
.R(1'b0));
FDRE \skid_buffer_reg[4]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [4]),
.Q(\skid_buffer_reg_n_0_[4] ),
.R(1'b0));
FDRE \skid_buffer_reg[5]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [5]),
.Q(\skid_buffer_reg_n_0_[5] ),
.R(1'b0));
FDRE \skid_buffer_reg[6]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [6]),
.Q(\skid_buffer_reg_n_0_[6] ),
.R(1'b0));
FDRE \skid_buffer_reg[7]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [7]),
.Q(\skid_buffer_reg_n_0_[7] ),
.R(1'b0));
FDRE \skid_buffer_reg[8]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [8]),
.Q(\skid_buffer_reg_n_0_[8] ),
.R(1'b0));
FDRE \skid_buffer_reg[9]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [9]),
.Q(\skid_buffer_reg_n_0_[9] ),
.R(1'b0));
endmodule
(* CHECK_LICENSE_TYPE = "zqynq_lab_1_design_auto_pc_2,axi_protocol_converter_v2_1_13_axi_protocol_converter,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* X_CORE_INFO = "axi_protocol_converter_v2_1_13_axi_protocol_converter,Vivado 2017.2" *)
(* NotValidForBitStream *)
module zqynq_lab_1_design_auto_pc_0
(aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awregion,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arregion,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awprot,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arprot,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rvalid,
m_axi_rready);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *) input aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *) input aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *) input [11:0]s_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *) input [31:0]s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *) input [7:0]s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *) input [2:0]s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *) input [1:0]s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *) input [0:0]s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *) input [3:0]s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *) input [2:0]s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREGION" *) input [3:0]s_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *) input [3:0]s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *) input s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *) output s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *) input [31:0]s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *) input [3:0]s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *) input s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *) input s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *) output s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *) output [11:0]s_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *) output [1:0]s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *) output s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *) input s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *) input [11:0]s_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *) input [31:0]s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *) input [7:0]s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *) input [2:0]s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *) input [1:0]s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *) input [0:0]s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *) input [3:0]s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *) input [2:0]s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREGION" *) input [3:0]s_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *) input [3:0]s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *) input s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *) output s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *) output [11:0]s_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *) output [31:0]s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *) output [1:0]s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *) output s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *) output s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *) input s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *) output [31:0]m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *) output [2:0]m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *) output m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *) input m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *) output [31:0]m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *) output [3:0]m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *) output m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *) input m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *) input [1:0]m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *) input m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *) output m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *) output [31:0]m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *) output [2:0]m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *) output m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *) input m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *) input [31:0]m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *) input [1:0]m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *) input m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *) output m_axi_rready;
wire aclk;
wire aresetn;
wire [31:0]m_axi_araddr;
wire [2:0]m_axi_arprot;
wire m_axi_arready;
wire m_axi_arvalid;
wire [31:0]m_axi_awaddr;
wire [2:0]m_axi_awprot;
wire m_axi_awready;
wire m_axi_awvalid;
wire m_axi_bready;
wire [1:0]m_axi_bresp;
wire m_axi_bvalid;
wire [31:0]m_axi_rdata;
wire m_axi_rready;
wire [1:0]m_axi_rresp;
wire m_axi_rvalid;
wire [31:0]m_axi_wdata;
wire m_axi_wready;
wire [3:0]m_axi_wstrb;
wire m_axi_wvalid;
wire [31:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [3:0]s_axi_arcache;
wire [11:0]s_axi_arid;
wire [7:0]s_axi_arlen;
wire [0:0]s_axi_arlock;
wire [2:0]s_axi_arprot;
wire [3:0]s_axi_arqos;
wire s_axi_arready;
wire [3:0]s_axi_arregion;
wire [2:0]s_axi_arsize;
wire s_axi_arvalid;
wire [31:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [3:0]s_axi_awcache;
wire [11:0]s_axi_awid;
wire [7:0]s_axi_awlen;
wire [0:0]s_axi_awlock;
wire [2:0]s_axi_awprot;
wire [3:0]s_axi_awqos;
wire s_axi_awready;
wire [3:0]s_axi_awregion;
wire [2:0]s_axi_awsize;
wire s_axi_awvalid;
wire [11:0]s_axi_bid;
wire s_axi_bready;
wire [1:0]s_axi_bresp;
wire s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire [11:0]s_axi_rid;
wire s_axi_rlast;
wire s_axi_rready;
wire [1:0]s_axi_rresp;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire s_axi_wlast;
wire s_axi_wready;
wire [3:0]s_axi_wstrb;
wire s_axi_wvalid;
wire NLW_inst_m_axi_wlast_UNCONNECTED;
wire [1:0]NLW_inst_m_axi_arburst_UNCONNECTED;
wire [3:0]NLW_inst_m_axi_arcache_UNCONNECTED;
wire [11:0]NLW_inst_m_axi_arid_UNCONNECTED;
wire [7:0]NLW_inst_m_axi_arlen_UNCONNECTED;
wire [0:0]NLW_inst_m_axi_arlock_UNCONNECTED;
wire [3:0]NLW_inst_m_axi_arqos_UNCONNECTED;
wire [3:0]NLW_inst_m_axi_arregion_UNCONNECTED;
wire [2:0]NLW_inst_m_axi_arsize_UNCONNECTED;
wire [0:0]NLW_inst_m_axi_aruser_UNCONNECTED;
wire [1:0]NLW_inst_m_axi_awburst_UNCONNECTED;
wire [3:0]NLW_inst_m_axi_awcache_UNCONNECTED;
wire [11:0]NLW_inst_m_axi_awid_UNCONNECTED;
wire [7:0]NLW_inst_m_axi_awlen_UNCONNECTED;
wire [0:0]NLW_inst_m_axi_awlock_UNCONNECTED;
wire [3:0]NLW_inst_m_axi_awqos_UNCONNECTED;
wire [3:0]NLW_inst_m_axi_awregion_UNCONNECTED;
wire [2:0]NLW_inst_m_axi_awsize_UNCONNECTED;
wire [0:0]NLW_inst_m_axi_awuser_UNCONNECTED;
wire [11:0]NLW_inst_m_axi_wid_UNCONNECTED;
wire [0:0]NLW_inst_m_axi_wuser_UNCONNECTED;
wire [0:0]NLW_inst_s_axi_buser_UNCONNECTED;
wire [0:0]NLW_inst_s_axi_ruser_UNCONNECTED;
(* C_AXI_ADDR_WIDTH = "32" *)
(* C_AXI_ARUSER_WIDTH = "1" *)
(* C_AXI_AWUSER_WIDTH = "1" *)
(* C_AXI_BUSER_WIDTH = "1" *)
(* C_AXI_DATA_WIDTH = "32" *)
(* C_AXI_ID_WIDTH = "12" *)
(* C_AXI_RUSER_WIDTH = "1" *)
(* C_AXI_SUPPORTS_READ = "1" *)
(* C_AXI_SUPPORTS_USER_SIGNALS = "0" *)
(* C_AXI_SUPPORTS_WRITE = "1" *)
(* C_AXI_WUSER_WIDTH = "1" *)
(* C_FAMILY = "zynq" *)
(* C_IGNORE_ID = "0" *)
(* C_M_AXI_PROTOCOL = "2" *)
(* C_S_AXI_PROTOCOL = "0" *)
(* C_TRANSLATION_MODE = "2" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
(* P_AXI3 = "1" *)
(* P_AXI4 = "0" *)
(* P_AXILITE = "2" *)
(* P_AXILITE_SIZE = "3'b010" *)
(* P_CONVERSION = "2" *)
(* P_DECERR = "2'b11" *)
(* P_INCR = "2'b01" *)
(* P_PROTECTION = "1" *)
(* P_SLVERR = "2'b10" *)
zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter inst
(.aclk(aclk),
.aresetn(aresetn),
.m_axi_araddr(m_axi_araddr),
.m_axi_arburst(NLW_inst_m_axi_arburst_UNCONNECTED[1:0]),
.m_axi_arcache(NLW_inst_m_axi_arcache_UNCONNECTED[3:0]),
.m_axi_arid(NLW_inst_m_axi_arid_UNCONNECTED[11:0]),
.m_axi_arlen(NLW_inst_m_axi_arlen_UNCONNECTED[7:0]),
.m_axi_arlock(NLW_inst_m_axi_arlock_UNCONNECTED[0]),
.m_axi_arprot(m_axi_arprot),
.m_axi_arqos(NLW_inst_m_axi_arqos_UNCONNECTED[3:0]),
.m_axi_arready(m_axi_arready),
.m_axi_arregion(NLW_inst_m_axi_arregion_UNCONNECTED[3:0]),
.m_axi_arsize(NLW_inst_m_axi_arsize_UNCONNECTED[2:0]),
.m_axi_aruser(NLW_inst_m_axi_aruser_UNCONNECTED[0]),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awburst(NLW_inst_m_axi_awburst_UNCONNECTED[1:0]),
.m_axi_awcache(NLW_inst_m_axi_awcache_UNCONNECTED[3:0]),
.m_axi_awid(NLW_inst_m_axi_awid_UNCONNECTED[11:0]),
.m_axi_awlen(NLW_inst_m_axi_awlen_UNCONNECTED[7:0]),
.m_axi_awlock(NLW_inst_m_axi_awlock_UNCONNECTED[0]),
.m_axi_awprot(m_axi_awprot),
.m_axi_awqos(NLW_inst_m_axi_awqos_UNCONNECTED[3:0]),
.m_axi_awready(m_axi_awready),
.m_axi_awregion(NLW_inst_m_axi_awregion_UNCONNECTED[3:0]),
.m_axi_awsize(NLW_inst_m_axi_awsize_UNCONNECTED[2:0]),
.m_axi_awuser(NLW_inst_m_axi_awuser_UNCONNECTED[0]),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_bid({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.m_axi_bready(m_axi_bready),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'b0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_rdata(m_axi_rdata),
.m_axi_rid({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.m_axi_rlast(1'b1),
.m_axi_rready(m_axi_rready),
.m_axi_rresp(m_axi_rresp),
.m_axi_ruser(1'b0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_wdata(m_axi_wdata),
.m_axi_wid(NLW_inst_m_axi_wid_UNCONNECTED[11:0]),
.m_axi_wlast(NLW_inst_m_axi_wlast_UNCONNECTED),
.m_axi_wready(m_axi_wready),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wuser(NLW_inst_m_axi_wuser_UNCONNECTED[0]),
.m_axi_wvalid(m_axi_wvalid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arburst(s_axi_arburst),
.s_axi_arcache(s_axi_arcache),
.s_axi_arid(s_axi_arid),
.s_axi_arlen(s_axi_arlen),
.s_axi_arlock(s_axi_arlock),
.s_axi_arprot(s_axi_arprot),
.s_axi_arqos(s_axi_arqos),
.s_axi_arready(s_axi_arready),
.s_axi_arregion(s_axi_arregion),
.s_axi_arsize(s_axi_arsize),
.s_axi_aruser(1'b0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awburst(s_axi_awburst),
.s_axi_awcache(s_axi_awcache),
.s_axi_awid(s_axi_awid),
.s_axi_awlen(s_axi_awlen),
.s_axi_awlock(s_axi_awlock),
.s_axi_awprot(s_axi_awprot),
.s_axi_awqos(s_axi_awqos),
.s_axi_awready(s_axi_awready),
.s_axi_awregion(s_axi_awregion),
.s_axi_awsize(s_axi_awsize),
.s_axi_awuser(1'b0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bid(s_axi_bid),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(NLW_inst_s_axi_buser_UNCONNECTED[0]),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rid(s_axi_rid),
.s_axi_rlast(s_axi_rlast),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(s_axi_rresp),
.s_axi_ruser(NLW_inst_s_axi_ruser_UNCONNECTED[0]),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wid({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wlast(s_axi_wlast),
.s_axi_wready(s_axi_wready),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wuser(1'b0),
.s_axi_wvalid(s_axi_wvalid));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
//--------------------------------------------------------------------------------
// spi_receiver.v
//
// Copyright (C) 2006 Michael Poppitz
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
//
//--------------------------------------------------------------------------------
//
// Details: http://www.sump.org/projects/analyzer/
//
// Receives commands from the SPI interface. The first byte is the commands
// opcode, the following (optional) four byte are the command data.
// Commands that do not have the highest bit in their opcode set are
// considered short commands without data (1 byte long). All other commands are
// long commands which are 5 bytes long.
//
// After a full command has been received it will be kept available for 10 cycles
// on the op and data outputs. A valid command can be detected by checking if the
// execute output is set. After 10 cycles the registers will be cleared
// automatically and the receiver waits for new data from the serial port.
//
//--------------------------------------------------------------------------------
//
// 12/29/2010 - Verilog Version + cleanups created by Ian Davis (IED) - mygizmos.org
//
`timescale 1ns/100ps
module spi_receiver (
// system signals
input wire clk,
input wire rst,
// SPI signals
input wire spi_sclk,
input wire spi_mosi,
input wire spi_cs_n,
//
input wire transmitting,
output reg [7:0] opcode,
output reg [31:0] opdata,
output reg execute
);
localparam READOPCODE = 1'h0;
localparam READLONG = 1'h1;
reg state, next_state; // receiver state
reg [1:0] bytecount, next_bytecount; // count rxed bytes of current command
reg [7:0] next_opcode; // opcode byte
reg [31:0] next_opdata; // data dword
reg next_execute;
reg [2:0] bitcount, next_bitcount; // count rxed bits of current byte
reg [7:0] spiByte, next_spiByte;
reg byteready, next_byteready;
dly_signal mosi_reg (clk, spi_mosi, sampled_mosi);
dly_signal dly_sclk_reg (clk, spi_sclk, dly_sclk);
wire sclk_posedge = !dly_sclk && spi_sclk;
dly_signal dly_cs_reg (clk, spi_cs_n, dly_cs);
wire cs_negedge = dly_cs && !spi_cs_n;
//
// Accumulate byte from serial input...
//
initial bitcount = 0;
always @(posedge clk, posedge rst)
if (rst) bitcount <= 0;
else bitcount <= next_bitcount;
always @(posedge clk)
begin
spiByte <= next_spiByte;
byteready <= next_byteready;
end
always @*
begin
next_bitcount = bitcount;
next_spiByte = spiByte;
next_byteready = 1'b0;
if (cs_negedge)
next_bitcount = 0;
if (sclk_posedge) // detect rising edge of sclk
if (spi_cs_n)
begin
next_bitcount = 0;
next_spiByte = 0;
end
else
begin
next_bitcount = bitcount + 1'b1;
next_byteready = &bitcount;
next_spiByte = {spiByte[6:0],sampled_mosi};
end
end
//
// Command tracking...
//
initial state = READOPCODE;
always @(posedge clk, posedge rst)
if (rst) state <= READOPCODE;
else state <= next_state;
initial opcode = 0;
initial opdata = 0;
always @(posedge clk)
begin
bytecount <= next_bytecount;
opcode <= next_opcode;
opdata <= next_opdata;
execute <= next_execute;
end
always @*
begin
next_state = state;
next_bytecount = bytecount;
next_opcode = opcode;
next_opdata = opdata;
next_execute = 1'b0;
case (state)
READOPCODE : // receive byte
begin
next_bytecount = 0;
if (byteready)
begin
next_opcode = spiByte;
if (spiByte[7])
next_state = READLONG;
else // short command
begin
next_execute = 1'b1;
next_state = READOPCODE;
end
end
end
READLONG : // receive 4 word parameter
begin
if (byteready)
begin
next_bytecount = bytecount + 1'b1;
next_opdata = {spiByte,opdata[31:8]};
if (&bytecount) // execute long command
begin
next_execute = 1'b1;
next_state = READOPCODE;
end
end
end
endcase
end
endmodule
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
// Date : Tue Oct 17 19:49:39 2017
// Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
// Command : write_verilog -force -mode synth_stub
// /home/mark/Documents/Repos/FPGA_Sandbox/RecComp/Lab3/adventures_with_ip/adventures_with_ip.srcs/sources_1/bd/ip_design/ip/ip_design_lms_pcore_0_0/ip_design_lms_pcore_0_0_stub.v
// Design : ip_design_lms_pcore_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "lms_pcore,Vivado 2017.3" *)
module ip_design_lms_pcore_0_0(IPCORE_CLK, IPCORE_RESETN, AXI4_Lite_ACLK,
AXI4_Lite_ARESETN, AXI4_Lite_AWADDR, AXI4_Lite_AWVALID, AXI4_Lite_WDATA, AXI4_Lite_WSTRB,
AXI4_Lite_WVALID, AXI4_Lite_BREADY, AXI4_Lite_ARADDR, AXI4_Lite_ARVALID,
AXI4_Lite_RREADY, AXI4_Lite_AWREADY, AXI4_Lite_WREADY, AXI4_Lite_BRESP, AXI4_Lite_BVALID,
AXI4_Lite_ARREADY, AXI4_Lite_RDATA, AXI4_Lite_RRESP, AXI4_Lite_RVALID)
/* synthesis syn_black_box black_box_pad_pin="IPCORE_CLK,IPCORE_RESETN,AXI4_Lite_ACLK,AXI4_Lite_ARESETN,AXI4_Lite_AWADDR[15:0],AXI4_Lite_AWVALID,AXI4_Lite_WDATA[31:0],AXI4_Lite_WSTRB[3:0],AXI4_Lite_WVALID,AXI4_Lite_BREADY,AXI4_Lite_ARADDR[15:0],AXI4_Lite_ARVALID,AXI4_Lite_RREADY,AXI4_Lite_AWREADY,AXI4_Lite_WREADY,AXI4_Lite_BRESP[1:0],AXI4_Lite_BVALID,AXI4_Lite_ARREADY,AXI4_Lite_RDATA[31:0],AXI4_Lite_RRESP[1:0],AXI4_Lite_RVALID" */;
input IPCORE_CLK;
input IPCORE_RESETN;
input AXI4_Lite_ACLK;
input AXI4_Lite_ARESETN;
input [15:0]AXI4_Lite_AWADDR;
input AXI4_Lite_AWVALID;
input [31:0]AXI4_Lite_WDATA;
input [3:0]AXI4_Lite_WSTRB;
input AXI4_Lite_WVALID;
input AXI4_Lite_BREADY;
input [15:0]AXI4_Lite_ARADDR;
input AXI4_Lite_ARVALID;
input AXI4_Lite_RREADY;
output AXI4_Lite_AWREADY;
output AXI4_Lite_WREADY;
output [1:0]AXI4_Lite_BRESP;
output AXI4_Lite_BVALID;
output AXI4_Lite_ARREADY;
output [31:0]AXI4_Lite_RDATA;
output [1:0]AXI4_Lite_RRESP;
output AXI4_Lite_RVALID;
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Mon Feb 20 13:53:00 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// c:/ZyboIP/general_ip/affine_transform/affine_transform.srcs/sources_1/bd/affine_block/ip/affine_block_ieee754_fp_adder_subtractor_0_1/affine_block_ieee754_fp_adder_subtractor_0_1_sim_netlist.v
// Design : affine_block_ieee754_fp_adder_subtractor_0_1
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "affine_block_ieee754_fp_adder_subtractor_0_1,ieee754_fp_adder_subtractor,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "ieee754_fp_adder_subtractor,Vivado 2016.4" *)
(* NotValidForBitStream *)
module affine_block_ieee754_fp_adder_subtractor_0_1
(x,
y,
z);
input [31:0]x;
input [31:0]y;
output [31:0]z;
wire [31:0]x;
wire [31:0]y;
wire [31:0]z;
affine_block_ieee754_fp_adder_subtractor_0_1_ieee754_fp_adder_subtractor U0
(.x(x),
.y(y),
.z(z));
endmodule
(* ORIG_REF_NAME = "ieee754_fp_adder_subtractor" *)
module affine_block_ieee754_fp_adder_subtractor_0_1_ieee754_fp_adder_subtractor
(z,
y,
x);
output [31:0]z;
input [31:0]y;
input [31:0]x;
wire [19:0]A;
wire _carry__0_i_1_n_0;
wire _carry__0_i_2_n_0;
wire _carry__0_i_3_n_0;
wire _carry__0_i_4_n_0;
wire _carry__0_n_0;
wire _carry__0_n_1;
wire _carry__0_n_2;
wire _carry__0_n_3;
wire _carry__1_i_1_n_0;
wire _carry__1_i_2_n_0;
wire _carry__1_i_3_n_0;
wire _carry__1_i_4_n_0;
wire _carry__1_n_0;
wire _carry__1_n_1;
wire _carry__1_n_2;
wire _carry__1_n_3;
wire _carry__2_i_1_n_0;
wire _carry__2_i_2_n_0;
wire _carry__2_i_3_n_0;
wire _carry__2_i_4_n_0;
wire _carry__2_n_0;
wire _carry__2_n_1;
wire _carry__2_n_2;
wire _carry__2_n_3;
wire _carry__3_i_1_n_0;
wire _carry__3_i_2_n_0;
wire _carry__3_i_3_n_0;
wire _carry__3_i_4_n_0;
wire _carry__3_n_0;
wire _carry__3_n_1;
wire _carry__3_n_2;
wire _carry__3_n_3;
wire _carry__4_i_1_n_0;
wire _carry__4_i_2_n_0;
wire _carry__4_i_3_n_0;
wire _carry__4_i_4_n_0;
wire _carry__4_n_0;
wire _carry__4_n_1;
wire _carry__4_n_2;
wire _carry__4_n_3;
wire _carry__5_i_1_n_0;
wire _carry__5_i_2_n_0;
wire _carry__5_i_3_n_0;
wire _carry__5_i_4_n_0;
wire _carry__5_n_0;
wire _carry__5_n_1;
wire _carry__5_n_2;
wire _carry__5_n_3;
wire _carry__6_i_1_n_0;
wire _carry__6_i_2_n_0;
wire _carry__6_n_3;
wire _carry_i_10_n_0;
wire _carry_i_11_n_0;
wire _carry_i_12_n_0;
wire _carry_i_13_n_0;
wire _carry_i_14_n_0;
wire _carry_i_15_n_0;
wire _carry_i_16_n_0;
wire _carry_i_17_n_0;
wire _carry_i_18_n_0;
wire _carry_i_19_n_0;
wire _carry_i_1_n_0;
wire _carry_i_2_n_0;
wire _carry_i_3_n_0;
wire _carry_i_4_n_0;
wire _carry_i_5_n_0;
wire _carry_i_6_n_0;
wire _carry_i_7_n_0;
wire _carry_i_8_n_0;
wire _carry_i_9_n_0;
wire _carry_n_0;
wire _carry_n_1;
wire _carry_n_2;
wire _carry_n_3;
wire [7:0]large_exp;
wire large_mant1_carry_i_1_n_0;
wire large_mant1_carry_i_2_n_0;
wire large_mant1_carry_i_3_n_0;
wire large_mant1_carry_i_4_n_0;
wire large_mant1_carry_i_5_n_0;
wire large_mant1_carry_i_6_n_0;
wire large_mant1_carry_i_7_n_0;
wire large_mant1_carry_i_8_n_0;
wire large_mant1_carry_n_0;
wire large_mant1_carry_n_1;
wire large_mant1_carry_n_2;
wire large_mant1_carry_n_3;
wire [4:0]p_0_in;
wire [23:0]sel0;
wire sign00__0_carry__0_i_10_n_0;
wire sign00__0_carry__0_i_11_n_0;
wire sign00__0_carry__0_i_12_n_0;
wire sign00__0_carry__0_i_13_n_0;
wire sign00__0_carry__0_i_14_n_0;
wire sign00__0_carry__0_i_15_n_0;
wire sign00__0_carry__0_i_16_n_0;
wire sign00__0_carry__0_i_19_n_0;
wire sign00__0_carry__0_i_1_n_0;
wire sign00__0_carry__0_i_20_n_0;
wire sign00__0_carry__0_i_21_n_0;
wire sign00__0_carry__0_i_22_n_0;
wire sign00__0_carry__0_i_23_n_0;
wire sign00__0_carry__0_i_24_n_0;
wire sign00__0_carry__0_i_25_n_0;
wire sign00__0_carry__0_i_26_n_0;
wire sign00__0_carry__0_i_27_n_0;
wire sign00__0_carry__0_i_28_n_0;
wire sign00__0_carry__0_i_29_n_0;
wire sign00__0_carry__0_i_2_n_0;
wire sign00__0_carry__0_i_30_n_0;
wire sign00__0_carry__0_i_31_n_0;
wire sign00__0_carry__0_i_32_n_0;
wire sign00__0_carry__0_i_33_n_0;
wire sign00__0_carry__0_i_34_n_0;
wire sign00__0_carry__0_i_35_n_0;
wire sign00__0_carry__0_i_38_n_0;
wire sign00__0_carry__0_i_39_n_0;
wire sign00__0_carry__0_i_3_n_0;
wire sign00__0_carry__0_i_40_n_0;
wire sign00__0_carry__0_i_41_n_0;
wire sign00__0_carry__0_i_4_n_0;
wire sign00__0_carry__0_i_5_n_0;
wire sign00__0_carry__0_i_6_n_0;
wire sign00__0_carry__0_i_7_n_0;
wire sign00__0_carry__0_i_8_n_0;
wire sign00__0_carry__0_i_9_n_0;
wire sign00__0_carry__0_n_0;
wire sign00__0_carry__0_n_1;
wire sign00__0_carry__0_n_2;
wire sign00__0_carry__0_n_3;
wire sign00__0_carry__1_i_10_n_0;
wire sign00__0_carry__1_i_11_n_0;
wire sign00__0_carry__1_i_12_n_0;
wire sign00__0_carry__1_i_13_n_0;
wire sign00__0_carry__1_i_14_n_0;
wire sign00__0_carry__1_i_15_n_0;
wire sign00__0_carry__1_i_16_n_0;
wire sign00__0_carry__1_i_17_n_0;
wire sign00__0_carry__1_i_19_n_0;
wire sign00__0_carry__1_i_1_n_0;
wire sign00__0_carry__1_i_21_n_0;
wire sign00__0_carry__1_i_24_n_0;
wire sign00__0_carry__1_i_25_n_0;
wire sign00__0_carry__1_i_26_n_0;
wire sign00__0_carry__1_i_27_n_0;
wire sign00__0_carry__1_i_28_n_0;
wire sign00__0_carry__1_i_29_n_0;
wire sign00__0_carry__1_i_2_n_0;
wire sign00__0_carry__1_i_30_n_0;
wire sign00__0_carry__1_i_31_n_0;
wire sign00__0_carry__1_i_32_n_0;
wire sign00__0_carry__1_i_33_n_0;
wire sign00__0_carry__1_i_34_n_0;
wire sign00__0_carry__1_i_35_n_0;
wire sign00__0_carry__1_i_36_n_0;
wire sign00__0_carry__1_i_37_n_0;
wire sign00__0_carry__1_i_3_n_0;
wire sign00__0_carry__1_i_41_n_0;
wire sign00__0_carry__1_i_42_n_0;
wire sign00__0_carry__1_i_44_n_0;
wire sign00__0_carry__1_i_46_n_0;
wire sign00__0_carry__1_i_47_n_0;
wire sign00__0_carry__1_i_4_n_0;
wire sign00__0_carry__1_i_5_n_0;
wire sign00__0_carry__1_i_6_n_0;
wire sign00__0_carry__1_i_7_n_0;
wire sign00__0_carry__1_i_8_n_0;
wire sign00__0_carry__1_i_9_n_0;
wire sign00__0_carry__1_n_0;
wire sign00__0_carry__1_n_1;
wire sign00__0_carry__1_n_2;
wire sign00__0_carry__1_n_3;
wire sign00__0_carry__2_i_10_n_0;
wire sign00__0_carry__2_i_11_n_0;
wire sign00__0_carry__2_i_12_n_0;
wire sign00__0_carry__2_i_13_n_0;
wire sign00__0_carry__2_i_14_n_0;
wire sign00__0_carry__2_i_15_n_0;
wire sign00__0_carry__2_i_16_n_0;
wire sign00__0_carry__2_i_1_n_0;
wire sign00__0_carry__2_i_21_n_0;
wire sign00__0_carry__2_i_22_n_0;
wire sign00__0_carry__2_i_23_n_0;
wire sign00__0_carry__2_i_24_n_0;
wire sign00__0_carry__2_i_25_n_0;
wire sign00__0_carry__2_i_26_n_0;
wire sign00__0_carry__2_i_27_n_0;
wire sign00__0_carry__2_i_28_n_0;
wire sign00__0_carry__2_i_29_n_0;
wire sign00__0_carry__2_i_2_n_0;
wire sign00__0_carry__2_i_30_n_0;
wire sign00__0_carry__2_i_31_n_0;
wire sign00__0_carry__2_i_32_n_0;
wire sign00__0_carry__2_i_35_n_0;
wire sign00__0_carry__2_i_37_n_0;
wire sign00__0_carry__2_i_39_n_0;
wire sign00__0_carry__2_i_3_n_0;
wire sign00__0_carry__2_i_40_n_0;
wire sign00__0_carry__2_i_4_n_0;
wire sign00__0_carry__2_i_5_n_0;
wire sign00__0_carry__2_i_6_n_0;
wire sign00__0_carry__2_i_7_n_0;
wire sign00__0_carry__2_i_8_n_0;
wire sign00__0_carry__2_i_9_n_0;
wire sign00__0_carry__2_n_0;
wire sign00__0_carry__2_n_1;
wire sign00__0_carry__2_n_2;
wire sign00__0_carry__2_n_3;
wire sign00__0_carry__3_i_10_n_0;
wire sign00__0_carry__3_i_11_n_0;
wire sign00__0_carry__3_i_12_n_0;
wire sign00__0_carry__3_i_13_n_0;
wire sign00__0_carry__3_i_14_n_0;
wire sign00__0_carry__3_i_15_n_0;
wire sign00__0_carry__3_i_16_n_0;
wire sign00__0_carry__3_i_1_n_0;
wire sign00__0_carry__3_i_21_n_0;
wire sign00__0_carry__3_i_22_n_0;
wire sign00__0_carry__3_i_23_n_0;
wire sign00__0_carry__3_i_24_n_0;
wire sign00__0_carry__3_i_25_n_0;
wire sign00__0_carry__3_i_26_n_0;
wire sign00__0_carry__3_i_27_n_0;
wire sign00__0_carry__3_i_28_n_0;
wire sign00__0_carry__3_i_29_n_0;
wire sign00__0_carry__3_i_2_n_0;
wire sign00__0_carry__3_i_30_n_0;
wire sign00__0_carry__3_i_31_n_0;
wire sign00__0_carry__3_i_32_n_0;
wire sign00__0_carry__3_i_33_n_0;
wire sign00__0_carry__3_i_34_n_0;
wire sign00__0_carry__3_i_35_n_0;
wire sign00__0_carry__3_i_36_n_0;
wire sign00__0_carry__3_i_37_n_0;
wire sign00__0_carry__3_i_38_n_0;
wire sign00__0_carry__3_i_39_n_0;
wire sign00__0_carry__3_i_3_n_0;
wire sign00__0_carry__3_i_40_n_0;
wire sign00__0_carry__3_i_47_n_0;
wire sign00__0_carry__3_i_48_n_0;
wire sign00__0_carry__3_i_4_n_0;
wire sign00__0_carry__3_i_51_n_0;
wire sign00__0_carry__3_i_52_n_0;
wire sign00__0_carry__3_i_5_n_0;
wire sign00__0_carry__3_i_6_n_0;
wire sign00__0_carry__3_i_7_n_0;
wire sign00__0_carry__3_i_8_n_0;
wire sign00__0_carry__3_i_9_n_0;
wire sign00__0_carry__3_n_0;
wire sign00__0_carry__3_n_1;
wire sign00__0_carry__3_n_2;
wire sign00__0_carry__3_n_3;
wire sign00__0_carry__4_i_10_n_0;
wire sign00__0_carry__4_i_11_n_0;
wire sign00__0_carry__4_i_12_n_0;
wire sign00__0_carry__4_i_13_n_0;
wire sign00__0_carry__4_i_14_n_0;
wire sign00__0_carry__4_i_15_n_0;
wire sign00__0_carry__4_i_16_n_0;
wire sign00__0_carry__4_i_17_n_0;
wire sign00__0_carry__4_i_18_n_0;
wire sign00__0_carry__4_i_19_n_0;
wire sign00__0_carry__4_i_1_n_0;
wire sign00__0_carry__4_i_20_n_0;
wire sign00__0_carry__4_i_21_n_0;
wire sign00__0_carry__4_i_22_n_0;
wire sign00__0_carry__4_i_23_n_0;
wire sign00__0_carry__4_i_24_n_0;
wire sign00__0_carry__4_i_25_n_0;
wire sign00__0_carry__4_i_26_n_0;
wire sign00__0_carry__4_i_27_n_0;
wire sign00__0_carry__4_i_28_n_0;
wire sign00__0_carry__4_i_29_n_0;
wire sign00__0_carry__4_i_2_n_0;
wire sign00__0_carry__4_i_30_n_0;
wire sign00__0_carry__4_i_31_n_0;
wire sign00__0_carry__4_i_32_n_0;
wire sign00__0_carry__4_i_33_n_0;
wire sign00__0_carry__4_i_34_n_0;
wire sign00__0_carry__4_i_35_n_0;
wire sign00__0_carry__4_i_36_n_0;
wire sign00__0_carry__4_i_37_n_0;
wire sign00__0_carry__4_i_38_n_0;
wire sign00__0_carry__4_i_39_n_0;
wire sign00__0_carry__4_i_3_n_0;
wire sign00__0_carry__4_i_4_n_0;
wire sign00__0_carry__4_i_5_n_0;
wire sign00__0_carry__4_i_6_n_0;
wire sign00__0_carry__4_i_7_n_0;
wire sign00__0_carry__4_i_8_n_0;
wire sign00__0_carry__4_i_9_n_0;
wire sign00__0_carry__4_n_0;
wire sign00__0_carry__4_n_1;
wire sign00__0_carry__4_n_2;
wire sign00__0_carry__4_n_3;
wire sign00__0_carry__5_i_1_n_0;
wire sign00__0_carry__5_i_2_n_0;
wire sign00__0_carry__5_i_3_n_0;
wire sign00__0_carry_i_100_n_0;
wire sign00__0_carry_i_101_n_0;
wire sign00__0_carry_i_102_n_0;
wire sign00__0_carry_i_103_n_0;
wire sign00__0_carry_i_104_n_0;
wire sign00__0_carry_i_105_n_0;
wire sign00__0_carry_i_10_n_0;
wire sign00__0_carry_i_11_n_0;
wire sign00__0_carry_i_12_n_0;
wire sign00__0_carry_i_12_n_1;
wire sign00__0_carry_i_12_n_2;
wire sign00__0_carry_i_12_n_3;
wire sign00__0_carry_i_12_n_4;
wire sign00__0_carry_i_12_n_5;
wire sign00__0_carry_i_12_n_6;
wire sign00__0_carry_i_12_n_7;
wire sign00__0_carry_i_13_n_0;
wire sign00__0_carry_i_14_n_0;
wire sign00__0_carry_i_15_n_0;
wire sign00__0_carry_i_16_n_0;
wire sign00__0_carry_i_17_n_0;
wire sign00__0_carry_i_21_n_0;
wire sign00__0_carry_i_22_n_0;
wire sign00__0_carry_i_23_n_0;
wire sign00__0_carry_i_24_n_0;
wire sign00__0_carry_i_25_n_0;
wire sign00__0_carry_i_26_n_0;
wire sign00__0_carry_i_2_n_0;
wire sign00__0_carry_i_32_n_0;
wire sign00__0_carry_i_33_n_0;
wire sign00__0_carry_i_34_n_0;
wire sign00__0_carry_i_35_n_0;
wire sign00__0_carry_i_36_n_0;
wire sign00__0_carry_i_37_n_0;
wire sign00__0_carry_i_38_n_0;
wire sign00__0_carry_i_39_n_0;
wire sign00__0_carry_i_3_n_0;
wire sign00__0_carry_i_41_n_0;
wire sign00__0_carry_i_42_n_0;
wire sign00__0_carry_i_43_n_0;
wire sign00__0_carry_i_44_n_0;
wire sign00__0_carry_i_45_n_0;
wire sign00__0_carry_i_46_n_0;
wire sign00__0_carry_i_47_n_0;
wire sign00__0_carry_i_48_n_0;
wire sign00__0_carry_i_49_n_0;
wire sign00__0_carry_i_4_n_0;
wire sign00__0_carry_i_51_n_0;
wire sign00__0_carry_i_53_n_0;
wire sign00__0_carry_i_54_n_0;
wire sign00__0_carry_i_55_n_0;
wire sign00__0_carry_i_56_n_0;
wire sign00__0_carry_i_57_n_0;
wire sign00__0_carry_i_58_n_0;
wire sign00__0_carry_i_59_n_0;
wire sign00__0_carry_i_5_n_0;
wire sign00__0_carry_i_60_n_0;
wire sign00__0_carry_i_61_n_0;
wire sign00__0_carry_i_62_n_0;
wire sign00__0_carry_i_63_n_0;
wire sign00__0_carry_i_64_n_0;
wire sign00__0_carry_i_65_n_0;
wire sign00__0_carry_i_66_n_0;
wire sign00__0_carry_i_67_n_0;
wire sign00__0_carry_i_68_n_0;
wire sign00__0_carry_i_69_n_0;
wire sign00__0_carry_i_6_n_0;
wire sign00__0_carry_i_70_n_0;
wire sign00__0_carry_i_71_n_0;
wire sign00__0_carry_i_71_n_1;
wire sign00__0_carry_i_71_n_2;
wire sign00__0_carry_i_71_n_3;
wire sign00__0_carry_i_71_n_4;
wire sign00__0_carry_i_71_n_5;
wire sign00__0_carry_i_71_n_6;
wire sign00__0_carry_i_71_n_7;
wire sign00__0_carry_i_72_n_0;
wire sign00__0_carry_i_73_n_0;
wire sign00__0_carry_i_74_n_0;
wire sign00__0_carry_i_74_n_1;
wire sign00__0_carry_i_74_n_2;
wire sign00__0_carry_i_74_n_3;
wire sign00__0_carry_i_74_n_4;
wire sign00__0_carry_i_74_n_5;
wire sign00__0_carry_i_74_n_6;
wire sign00__0_carry_i_74_n_7;
wire sign00__0_carry_i_75_n_0;
wire sign00__0_carry_i_75_n_1;
wire sign00__0_carry_i_75_n_2;
wire sign00__0_carry_i_75_n_3;
wire sign00__0_carry_i_75_n_4;
wire sign00__0_carry_i_75_n_5;
wire sign00__0_carry_i_75_n_6;
wire sign00__0_carry_i_75_n_7;
wire sign00__0_carry_i_76_n_0;
wire sign00__0_carry_i_76_n_1;
wire sign00__0_carry_i_76_n_2;
wire sign00__0_carry_i_76_n_3;
wire sign00__0_carry_i_76_n_4;
wire sign00__0_carry_i_76_n_5;
wire sign00__0_carry_i_76_n_6;
wire sign00__0_carry_i_76_n_7;
wire sign00__0_carry_i_77_n_3;
wire sign00__0_carry_i_77_n_6;
wire sign00__0_carry_i_77_n_7;
wire sign00__0_carry_i_78_n_0;
wire sign00__0_carry_i_78_n_1;
wire sign00__0_carry_i_78_n_2;
wire sign00__0_carry_i_78_n_3;
wire sign00__0_carry_i_78_n_4;
wire sign00__0_carry_i_78_n_5;
wire sign00__0_carry_i_78_n_6;
wire sign00__0_carry_i_78_n_7;
wire sign00__0_carry_i_79_n_0;
wire sign00__0_carry_i_79_n_1;
wire sign00__0_carry_i_79_n_2;
wire sign00__0_carry_i_79_n_3;
wire sign00__0_carry_i_79_n_4;
wire sign00__0_carry_i_79_n_5;
wire sign00__0_carry_i_79_n_6;
wire sign00__0_carry_i_79_n_7;
wire sign00__0_carry_i_7_n_0;
wire sign00__0_carry_i_80_n_0;
wire sign00__0_carry_i_81_n_0;
wire sign00__0_carry_i_82_n_0;
wire sign00__0_carry_i_83_n_0;
wire sign00__0_carry_i_84_n_0;
wire sign00__0_carry_i_85_n_0;
wire sign00__0_carry_i_86_n_0;
wire sign00__0_carry_i_87_n_0;
wire sign00__0_carry_i_88_n_0;
wire sign00__0_carry_i_89_n_0;
wire sign00__0_carry_i_8_n_0;
wire sign00__0_carry_i_90_n_0;
wire sign00__0_carry_i_91_n_0;
wire sign00__0_carry_i_92_n_0;
wire sign00__0_carry_i_93_n_0;
wire sign00__0_carry_i_94_n_0;
wire sign00__0_carry_i_95_n_0;
wire sign00__0_carry_i_96_n_0;
wire sign00__0_carry_i_97_n_0;
wire sign00__0_carry_i_98_n_0;
wire sign00__0_carry_i_99_n_0;
wire sign00__0_carry_i_9_n_0;
wire sign00__0_carry_n_0;
wire sign00__0_carry_n_1;
wire sign00__0_carry_n_2;
wire sign00__0_carry_n_3;
wire sign00__0_carry_n_7;
wire [22:0]small_mant;
wire [19:18]sum2;
wire sum3;
wire sum3_carry__0_i_1_n_0;
wire sum3_carry__0_i_2_n_0;
wire sum3_carry__0_i_3_n_0;
wire sum3_carry__0_i_4_n_0;
wire sum3_carry__0_i_5_n_0;
wire sum3_carry__0_i_6_n_0;
wire sum3_carry__0_i_7_n_0;
wire sum3_carry__0_i_8_n_0;
wire sum3_carry__0_i_9_n_3;
wire sum3_carry__0_n_0;
wire sum3_carry__0_n_1;
wire sum3_carry__0_n_2;
wire sum3_carry__0_n_3;
wire sum3_carry__1_i_1_n_0;
wire sum3_carry__1_i_2_n_0;
wire sum3_carry__1_i_3_n_0;
wire sum3_carry__1_i_4_n_0;
wire sum3_carry__1_i_5_n_0;
wire sum3_carry__1_i_6_n_0;
wire sum3_carry__1_i_7_n_0;
wire sum3_carry__1_i_8_n_0;
wire sum3_carry__1_n_0;
wire sum3_carry__1_n_1;
wire sum3_carry__1_n_2;
wire sum3_carry__1_n_3;
wire sum3_carry__2_i_2_n_0;
wire sum3_carry__2_i_3_n_0;
wire sum3_carry__2_i_4_n_0;
wire sum3_carry__2_i_5_n_0;
wire sum3_carry__2_i_6_n_0;
wire sum3_carry__2_i_7_n_0;
wire sum3_carry__2_n_1;
wire sum3_carry__2_n_2;
wire sum3_carry__2_n_3;
wire sum3_carry_i_1_n_0;
wire sum3_carry_i_2_n_0;
wire sum3_carry_i_3_n_0;
wire sum3_carry_i_4_n_0;
wire sum3_carry_i_5_n_0;
wire sum3_carry_i_6_n_0;
wire sum3_carry_i_7_n_0;
wire sum3_carry_i_8_n_0;
wire sum3_carry_n_0;
wire sum3_carry_n_1;
wire sum3_carry_n_2;
wire sum3_carry_n_3;
wire [31:0]sum4;
wire sum4_carry__0_i_2_n_0;
wire sum4_carry__0_i_3_n_0;
wire sum4_carry__0_i_4_n_0;
wire sum4_carry__0_i_5_n_0;
wire sum4_carry__0_i_6_n_0;
wire sum4_carry__0_i_7_n_0;
wire sum4_carry__0_i_8_n_0;
wire sum4_carry__0_n_0;
wire sum4_carry__0_n_1;
wire sum4_carry__0_n_2;
wire sum4_carry__0_n_3;
wire sum4_carry_i_1_n_0;
wire sum4_carry_i_2_n_0;
wire sum4_carry_i_3_n_0;
wire sum4_carry_i_4_n_0;
wire sum4_carry_i_5_n_0;
wire sum4_carry_i_6_n_0;
wire sum4_carry_i_7_n_0;
wire sum4_carry_i_8_n_0;
wire sum4_carry_n_0;
wire sum4_carry_n_1;
wire sum4_carry_n_2;
wire sum4_carry_n_3;
wire [31:0]x;
wire [31:0]y;
wire [31:0]z;
wire z0_carry__0_n_1;
wire z0_carry__0_n_2;
wire z0_carry__0_n_3;
wire z0_carry_i_10_n_0;
wire z0_carry_i_11_n_0;
wire z0_carry_i_12_n_0;
wire z0_carry_i_4_n_0;
wire z0_carry_i_5__0_n_0;
wire z0_carry_i_5_n_0;
wire z0_carry_i_6__0_n_0;
wire z0_carry_i_6_n_0;
wire z0_carry_i_7__0_n_0;
wire z0_carry_i_7_n_0;
wire z0_carry_i_8__0_n_0;
wire z0_carry_i_8_n_0;
wire z0_carry_i_9_n_0;
wire z0_carry_n_0;
wire z0_carry_n_1;
wire z0_carry_n_2;
wire z0_carry_n_3;
wire [7:7]z1;
wire [22:4]z10_in;
wire z2;
wire z2_carry__0_i_1_n_0;
wire z2_carry__0_i_2_n_0;
wire z2_carry__0_i_3_n_0;
wire z2_carry__0_i_4_n_0;
wire z2_carry__0_i_5_n_0;
wire z2_carry__0_i_6_n_0;
wire z2_carry__0_i_7_n_0;
wire z2_carry__0_i_8_n_0;
wire z2_carry__0_n_0;
wire z2_carry__0_n_1;
wire z2_carry__0_n_2;
wire z2_carry__0_n_3;
wire z2_carry__1_i_1_n_0;
wire z2_carry__1_i_2_n_0;
wire z2_carry__1_i_3_n_0;
wire z2_carry__1_i_4_n_0;
wire z2_carry__1_i_5_n_0;
wire z2_carry__1_i_6_n_0;
wire z2_carry__1_i_7_n_0;
wire z2_carry__1_i_8_n_0;
wire z2_carry__1_n_0;
wire z2_carry__1_n_1;
wire z2_carry__1_n_2;
wire z2_carry__1_n_3;
wire z2_carry__2_i_2_n_0;
wire z2_carry__2_i_3_n_0;
wire z2_carry__2_i_4_n_0;
wire z2_carry__2_i_5_n_0;
wire z2_carry__2_i_6_n_0;
wire z2_carry__2_i_7_n_0;
wire z2_carry__2_n_1;
wire z2_carry__2_n_2;
wire z2_carry__2_n_3;
wire z2_carry_i_1_n_0;
wire z2_carry_i_2_n_0;
wire z2_carry_i_3_n_0;
wire z2_carry_i_4_n_0;
wire z2_carry_i_5_n_0;
wire z2_carry_i_6_n_0;
wire z2_carry_i_7_n_0;
wire z2_carry_i_8_n_0;
wire z2_carry_n_0;
wire z2_carry_n_1;
wire z2_carry_n_2;
wire z2_carry_n_3;
wire [30:1]z3;
wire \z[0]_INST_0_i_1_n_0 ;
wire \z[0]_INST_0_i_2_n_0 ;
wire \z[0]_INST_0_i_3_n_0 ;
wire \z[10]_INST_0_i_10_n_0 ;
wire \z[10]_INST_0_i_2_n_0 ;
wire \z[10]_INST_0_i_3_n_0 ;
wire \z[10]_INST_0_i_4_n_0 ;
wire \z[10]_INST_0_i_5_n_0 ;
wire \z[10]_INST_0_i_6_n_0 ;
wire \z[10]_INST_0_i_7_n_0 ;
wire \z[10]_INST_0_i_8_n_0 ;
wire \z[10]_INST_0_i_9_n_0 ;
wire \z[11]_INST_0_i_2_n_0 ;
wire \z[11]_INST_0_i_3_n_0 ;
wire \z[11]_INST_0_i_4_n_0 ;
wire \z[11]_INST_0_i_5_n_0 ;
wire \z[11]_INST_0_i_6_n_0 ;
wire \z[12]_INST_0_i_2_n_0 ;
wire \z[12]_INST_0_i_3_n_0 ;
wire \z[12]_INST_0_i_4_n_0 ;
wire \z[12]_INST_0_i_5_n_0 ;
wire \z[13]_INST_0_i_2_n_0 ;
wire \z[13]_INST_0_i_3_n_0 ;
wire \z[13]_INST_0_i_4_n_0 ;
wire \z[13]_INST_0_i_5_n_0 ;
wire \z[14]_INST_0_i_2_n_0 ;
wire \z[14]_INST_0_i_3_n_0 ;
wire \z[14]_INST_0_i_4_n_0 ;
wire \z[14]_INST_0_i_5_n_0 ;
wire \z[15]_INST_0_i_1_n_0 ;
wire \z[15]_INST_0_i_2_n_0 ;
wire \z[15]_INST_0_i_3_n_0 ;
wire \z[15]_INST_0_i_4_n_0 ;
wire \z[15]_INST_0_i_5_n_0 ;
wire \z[16]_INST_0_i_1_n_0 ;
wire \z[16]_INST_0_i_2_n_0 ;
wire \z[16]_INST_0_i_3_n_0 ;
wire \z[16]_INST_0_i_4_n_0 ;
wire \z[16]_INST_0_i_5_n_0 ;
wire \z[16]_INST_0_i_6_n_0 ;
wire \z[16]_INST_0_i_7_n_0 ;
wire \z[17]_INST_0_i_1_n_0 ;
wire \z[17]_INST_0_i_2_n_0 ;
wire \z[17]_INST_0_i_3_n_0 ;
wire \z[17]_INST_0_i_4_n_0 ;
wire \z[17]_INST_0_i_5_n_0 ;
wire \z[18]_INST_0_i_10_n_0 ;
wire \z[18]_INST_0_i_1_n_0 ;
wire \z[18]_INST_0_i_2_n_0 ;
wire \z[18]_INST_0_i_3_n_0 ;
wire \z[18]_INST_0_i_4_n_0 ;
wire \z[18]_INST_0_i_5_n_0 ;
wire \z[18]_INST_0_i_6_n_0 ;
wire \z[18]_INST_0_i_7_n_0 ;
wire \z[18]_INST_0_i_8_n_0 ;
wire \z[18]_INST_0_i_9_n_0 ;
wire \z[19]_INST_0_i_1_n_0 ;
wire \z[19]_INST_0_i_2_n_0 ;
wire \z[19]_INST_0_i_3_n_0 ;
wire \z[19]_INST_0_i_4_n_0 ;
wire \z[19]_INST_0_i_5_n_0 ;
wire \z[1]_INST_0_i_1_n_0 ;
wire \z[1]_INST_0_i_2_n_0 ;
wire \z[1]_INST_0_i_3_n_0 ;
wire \z[1]_INST_0_i_4_n_0 ;
wire \z[20]_INST_0_i_1_n_0 ;
wire \z[20]_INST_0_i_2_n_0 ;
wire \z[20]_INST_0_i_3_n_0 ;
wire \z[20]_INST_0_i_4_n_0 ;
wire \z[20]_INST_0_i_5_n_0 ;
wire \z[21]_INST_0_i_1_n_0 ;
wire \z[21]_INST_0_i_2_n_0 ;
wire \z[21]_INST_0_i_3_n_0 ;
wire \z[21]_INST_0_i_4_n_0 ;
wire \z[22]_INST_0_i_10_n_0 ;
wire \z[22]_INST_0_i_11_n_0 ;
wire \z[22]_INST_0_i_12_n_0 ;
wire \z[22]_INST_0_i_13_n_0 ;
wire \z[22]_INST_0_i_14_n_0 ;
wire \z[22]_INST_0_i_15_n_0 ;
wire \z[22]_INST_0_i_16_n_0 ;
wire \z[22]_INST_0_i_17_n_0 ;
wire \z[22]_INST_0_i_18_n_0 ;
wire \z[22]_INST_0_i_19_n_0 ;
wire \z[22]_INST_0_i_1_n_0 ;
wire \z[22]_INST_0_i_20_n_0 ;
wire \z[22]_INST_0_i_21_n_0 ;
wire \z[22]_INST_0_i_22_n_0 ;
wire \z[22]_INST_0_i_23_n_0 ;
wire \z[22]_INST_0_i_24_n_0 ;
wire \z[22]_INST_0_i_25_n_0 ;
wire \z[22]_INST_0_i_26_n_0 ;
wire \z[22]_INST_0_i_27_n_0 ;
wire \z[22]_INST_0_i_28_n_0 ;
wire \z[22]_INST_0_i_29_n_0 ;
wire \z[22]_INST_0_i_30_n_0 ;
wire \z[22]_INST_0_i_31_n_0 ;
wire \z[22]_INST_0_i_32_n_0 ;
wire \z[22]_INST_0_i_33_n_0 ;
wire \z[22]_INST_0_i_34_n_0 ;
wire \z[22]_INST_0_i_35_n_0 ;
wire \z[22]_INST_0_i_36_n_0 ;
wire \z[22]_INST_0_i_37_n_0 ;
wire \z[22]_INST_0_i_38_n_0 ;
wire \z[22]_INST_0_i_39_n_0 ;
wire \z[22]_INST_0_i_3_n_0 ;
wire \z[22]_INST_0_i_40_n_0 ;
wire \z[22]_INST_0_i_4_n_0 ;
wire \z[22]_INST_0_i_5_n_0 ;
wire \z[22]_INST_0_i_6_n_0 ;
wire \z[22]_INST_0_i_7_n_0 ;
wire \z[22]_INST_0_i_8_n_0 ;
wire \z[22]_INST_0_i_9_n_0 ;
wire \z[2]_INST_0_i_1_n_0 ;
wire \z[2]_INST_0_i_2_n_0 ;
wire \z[2]_INST_0_i_3_n_0 ;
wire \z[2]_INST_0_i_4_n_0 ;
wire \z[31]_INST_0_i_1_n_0 ;
wire \z[31]_INST_0_i_2_n_0 ;
wire \z[31]_INST_0_i_3_n_0 ;
wire \z[31]_INST_0_i_4_n_0 ;
wire \z[31]_INST_0_i_5_n_0 ;
wire \z[31]_INST_0_i_6_n_0 ;
wire \z[31]_INST_0_i_7_n_0 ;
wire \z[3]_INST_0_i_1_n_0 ;
wire \z[3]_INST_0_i_2_n_0 ;
wire \z[3]_INST_0_i_3_n_0 ;
wire \z[3]_INST_0_i_4_n_0 ;
wire \z[4]_INST_0_i_2_n_0 ;
wire \z[4]_INST_0_i_3_n_0 ;
wire \z[4]_INST_0_i_4_n_0 ;
wire \z[4]_INST_0_i_5_n_0 ;
wire \z[5]_INST_0_i_2_n_0 ;
wire \z[5]_INST_0_i_3_n_0 ;
wire \z[5]_INST_0_i_4_n_0 ;
wire \z[5]_INST_0_i_5_n_0 ;
wire \z[6]_INST_0_i_2_n_0 ;
wire \z[6]_INST_0_i_3_n_0 ;
wire \z[6]_INST_0_i_4_n_0 ;
wire \z[6]_INST_0_i_5_n_0 ;
wire \z[7]_INST_0_i_2_n_0 ;
wire \z[7]_INST_0_i_3_n_0 ;
wire \z[7]_INST_0_i_4_n_0 ;
wire \z[7]_INST_0_i_5_n_0 ;
wire \z[7]_INST_0_i_6_n_0 ;
wire \z[8]_INST_0_i_2_n_0 ;
wire \z[8]_INST_0_i_3_n_0 ;
wire \z[8]_INST_0_i_4_n_0 ;
wire \z[8]_INST_0_i_5_n_0 ;
wire \z[8]_INST_0_i_6_n_0 ;
wire \z[9]_INST_0_i_2_n_0 ;
wire \z[9]_INST_0_i_3_n_0 ;
wire \z[9]_INST_0_i_4_n_0 ;
wire \z[9]_INST_0_i_5_n_0 ;
wire \z[9]_INST_0_i_6_n_0 ;
wire \z[9]_INST_0_i_7_n_0 ;
wire [3:1]NLW__carry__6_CO_UNCONNECTED;
wire [3:2]NLW__carry__6_O_UNCONNECTED;
wire [3:0]NLW_large_mant1_carry_O_UNCONNECTED;
wire [3:0]NLW_sign00__0_carry__5_CO_UNCONNECTED;
wire [3:1]NLW_sign00__0_carry__5_O_UNCONNECTED;
wire [3:1]NLW_sign00__0_carry_i_77_CO_UNCONNECTED;
wire [3:2]NLW_sign00__0_carry_i_77_O_UNCONNECTED;
wire [3:0]NLW_sum3_carry_O_UNCONNECTED;
wire [3:0]NLW_sum3_carry__0_O_UNCONNECTED;
wire [3:1]NLW_sum3_carry__0_i_9_CO_UNCONNECTED;
wire [3:0]NLW_sum3_carry__0_i_9_O_UNCONNECTED;
wire [3:0]NLW_sum3_carry__1_O_UNCONNECTED;
wire [3:0]NLW_sum3_carry__2_O_UNCONNECTED;
wire [3:3]NLW_z0_carry__0_CO_UNCONNECTED;
wire [3:0]NLW_z2_carry_O_UNCONNECTED;
wire [3:0]NLW_z2_carry__0_O_UNCONNECTED;
wire [3:0]NLW_z2_carry__1_O_UNCONNECTED;
wire [3:0]NLW_z2_carry__2_O_UNCONNECTED;
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 _carry
(.CI(1'b0),
.CO({_carry_n_0,_carry_n_1,_carry_n_2,_carry_n_3}),
.CYINIT(\z[22]_INST_0_i_1_n_0 ),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(z3[4:1]),
.S({_carry_i_1_n_0,_carry_i_2_n_0,_carry_i_3_n_0,_carry_i_4_n_0}));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 _carry__0
(.CI(_carry_n_0),
.CO({_carry__0_n_0,_carry__0_n_1,_carry__0_n_2,_carry__0_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(z3[8:5]),
.S({_carry__0_i_1_n_0,_carry__0_i_2_n_0,_carry__0_i_3_n_0,_carry__0_i_4_n_0}));
LUT2 #(
.INIT(4'h7))
_carry__0_i_1
(.I0(z0_carry_i_9_n_0),
.I1(\z[31]_INST_0_i_2_n_0 ),
.O(_carry__0_i_1_n_0));
LUT2 #(
.INIT(4'h7))
_carry__0_i_2
(.I0(z0_carry_i_9_n_0),
.I1(\z[31]_INST_0_i_2_n_0 ),
.O(_carry__0_i_2_n_0));
LUT2 #(
.INIT(4'h7))
_carry__0_i_3
(.I0(z0_carry_i_9_n_0),
.I1(\z[31]_INST_0_i_2_n_0 ),
.O(_carry__0_i_3_n_0));
LUT2 #(
.INIT(4'h7))
_carry__0_i_4
(.I0(z0_carry_i_9_n_0),
.I1(\z[31]_INST_0_i_2_n_0 ),
.O(_carry__0_i_4_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 _carry__1
(.CI(_carry__0_n_0),
.CO({_carry__1_n_0,_carry__1_n_1,_carry__1_n_2,_carry__1_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(z3[12:9]),
.S({_carry__1_i_1_n_0,_carry__1_i_2_n_0,_carry__1_i_3_n_0,_carry__1_i_4_n_0}));
LUT2 #(
.INIT(4'h7))
_carry__1_i_1
(.I0(z0_carry_i_9_n_0),
.I1(\z[31]_INST_0_i_2_n_0 ),
.O(_carry__1_i_1_n_0));
LUT2 #(
.INIT(4'h7))
_carry__1_i_2
(.I0(z0_carry_i_9_n_0),
.I1(\z[31]_INST_0_i_2_n_0 ),
.O(_carry__1_i_2_n_0));
LUT2 #(
.INIT(4'h7))
_carry__1_i_3
(.I0(z0_carry_i_9_n_0),
.I1(\z[31]_INST_0_i_2_n_0 ),
.O(_carry__1_i_3_n_0));
LUT2 #(
.INIT(4'h7))
_carry__1_i_4
(.I0(z0_carry_i_9_n_0),
.I1(\z[31]_INST_0_i_2_n_0 ),
.O(_carry__1_i_4_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 _carry__2
(.CI(_carry__1_n_0),
.CO({_carry__2_n_0,_carry__2_n_1,_carry__2_n_2,_carry__2_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(z3[16:13]),
.S({_carry__2_i_1_n_0,_carry__2_i_2_n_0,_carry__2_i_3_n_0,_carry__2_i_4_n_0}));
LUT2 #(
.INIT(4'h7))
_carry__2_i_1
(.I0(z0_carry_i_9_n_0),
.I1(\z[31]_INST_0_i_2_n_0 ),
.O(_carry__2_i_1_n_0));
LUT2 #(
.INIT(4'h7))
_carry__2_i_2
(.I0(z0_carry_i_9_n_0),
.I1(\z[31]_INST_0_i_2_n_0 ),
.O(_carry__2_i_2_n_0));
LUT2 #(
.INIT(4'h7))
_carry__2_i_3
(.I0(z0_carry_i_9_n_0),
.I1(\z[31]_INST_0_i_2_n_0 ),
.O(_carry__2_i_3_n_0));
LUT2 #(
.INIT(4'h7))
_carry__2_i_4
(.I0(z0_carry_i_9_n_0),
.I1(\z[31]_INST_0_i_2_n_0 ),
.O(_carry__2_i_4_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 _carry__3
(.CI(_carry__2_n_0),
.CO({_carry__3_n_0,_carry__3_n_1,_carry__3_n_2,_carry__3_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(z3[20:17]),
.S({_carry__3_i_1_n_0,_carry__3_i_2_n_0,_carry__3_i_3_n_0,_carry__3_i_4_n_0}));
LUT2 #(
.INIT(4'h7))
_carry__3_i_1
(.I0(z0_carry_i_9_n_0),
.I1(\z[31]_INST_0_i_2_n_0 ),
.O(_carry__3_i_1_n_0));
LUT2 #(
.INIT(4'h7))
_carry__3_i_2
(.I0(z0_carry_i_9_n_0),
.I1(\z[31]_INST_0_i_2_n_0 ),
.O(_carry__3_i_2_n_0));
LUT2 #(
.INIT(4'h7))
_carry__3_i_3
(.I0(z0_carry_i_9_n_0),
.I1(\z[31]_INST_0_i_2_n_0 ),
.O(_carry__3_i_3_n_0));
LUT2 #(
.INIT(4'h7))
_carry__3_i_4
(.I0(z0_carry_i_9_n_0),
.I1(\z[31]_INST_0_i_2_n_0 ),
.O(_carry__3_i_4_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 _carry__4
(.CI(_carry__3_n_0),
.CO({_carry__4_n_0,_carry__4_n_1,_carry__4_n_2,_carry__4_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(z3[24:21]),
.S({_carry__4_i_1_n_0,_carry__4_i_2_n_0,_carry__4_i_3_n_0,_carry__4_i_4_n_0}));
LUT2 #(
.INIT(4'h7))
_carry__4_i_1
(.I0(z0_carry_i_9_n_0),
.I1(\z[31]_INST_0_i_2_n_0 ),
.O(_carry__4_i_1_n_0));
LUT2 #(
.INIT(4'h7))
_carry__4_i_2
(.I0(z0_carry_i_9_n_0),
.I1(\z[31]_INST_0_i_2_n_0 ),
.O(_carry__4_i_2_n_0));
LUT2 #(
.INIT(4'h7))
_carry__4_i_3
(.I0(z0_carry_i_9_n_0),
.I1(\z[31]_INST_0_i_2_n_0 ),
.O(_carry__4_i_3_n_0));
LUT2 #(
.INIT(4'h7))
_carry__4_i_4
(.I0(z0_carry_i_9_n_0),
.I1(\z[31]_INST_0_i_2_n_0 ),
.O(_carry__4_i_4_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 _carry__5
(.CI(_carry__4_n_0),
.CO({_carry__5_n_0,_carry__5_n_1,_carry__5_n_2,_carry__5_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(z3[28:25]),
.S({_carry__5_i_1_n_0,_carry__5_i_2_n_0,_carry__5_i_3_n_0,_carry__5_i_4_n_0}));
LUT2 #(
.INIT(4'h7))
_carry__5_i_1
(.I0(z0_carry_i_9_n_0),
.I1(\z[31]_INST_0_i_2_n_0 ),
.O(_carry__5_i_1_n_0));
LUT2 #(
.INIT(4'h7))
_carry__5_i_2
(.I0(z0_carry_i_9_n_0),
.I1(\z[31]_INST_0_i_2_n_0 ),
.O(_carry__5_i_2_n_0));
LUT2 #(
.INIT(4'h7))
_carry__5_i_3
(.I0(z0_carry_i_9_n_0),
.I1(\z[31]_INST_0_i_2_n_0 ),
.O(_carry__5_i_3_n_0));
LUT2 #(
.INIT(4'h7))
_carry__5_i_4
(.I0(z0_carry_i_9_n_0),
.I1(\z[31]_INST_0_i_2_n_0 ),
.O(_carry__5_i_4_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 _carry__6
(.CI(_carry__5_n_0),
.CO({NLW__carry__6_CO_UNCONNECTED[3:1],_carry__6_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({NLW__carry__6_O_UNCONNECTED[3:2],z3[30:29]}),
.S({1'b0,1'b0,_carry__6_i_1_n_0,_carry__6_i_2_n_0}));
LUT2 #(
.INIT(4'h7))
_carry__6_i_1
(.I0(z0_carry_i_9_n_0),
.I1(\z[31]_INST_0_i_2_n_0 ),
.O(_carry__6_i_1_n_0));
LUT2 #(
.INIT(4'h7))
_carry__6_i_2
(.I0(z0_carry_i_9_n_0),
.I1(\z[31]_INST_0_i_2_n_0 ),
.O(_carry__6_i_2_n_0));
LUT2 #(
.INIT(4'h6))
_carry_i_1
(.I0(z0_carry_i_9_n_0),
.I1(\z[31]_INST_0_i_2_n_0 ),
.O(_carry_i_1_n_0));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFAFAE))
_carry_i_10
(.I0(sel0[17]),
.I1(sel0[13]),
.I2(_carry_i_15_n_0),
.I3(sel0[14]),
.I4(sel0[18]),
.I5(_carry_i_16_n_0),
.O(_carry_i_10_n_0));
LUT6 #(
.INIT(64'hEEEF000000000000))
_carry_i_11
(.I0(sel0[9]),
.I1(sel0[10]),
.I2(sel0[8]),
.I3(sel0[7]),
.I4(_carry_i_17_n_0),
.I5(_carry_i_18_n_0),
.O(_carry_i_11_n_0));
LUT2 #(
.INIT(4'hE))
_carry_i_12
(.I0(sel0[18]),
.I1(sel0[17]),
.O(_carry_i_12_n_0));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
_carry_i_13
(.I0(_carry_i_19_n_0),
.I1(sel0[14]),
.I2(sel0[13]),
.I3(sel0[2]),
.I4(_carry_i_16_n_0),
.I5(\z[31]_INST_0_i_6_n_0 ),
.O(_carry_i_13_n_0));
LUT2 #(
.INIT(4'hE))
_carry_i_14
(.I0(sel0[8]),
.I1(sel0[7]),
.O(_carry_i_14_n_0));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT2 #(
.INIT(4'hE))
_carry_i_15
(.I0(sel0[16]),
.I1(sel0[15]),
.O(_carry_i_15_n_0));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT2 #(
.INIT(4'hE))
_carry_i_16
(.I0(sel0[21]),
.I1(sel0[22]),
.O(_carry_i_16_n_0));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFEEEF))
_carry_i_17
(.I0(sel0[10]),
.I1(sel0[9]),
.I2(sel0[3]),
.I3(sel0[4]),
.I4(sel0[5]),
.I5(sel0[6]),
.O(_carry_i_17_n_0));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT4 #(
.INIT(16'h0001))
_carry_i_18
(.I0(sel0[12]),
.I1(sel0[11]),
.I2(sel0[16]),
.I3(sel0[15]),
.O(_carry_i_18_n_0));
(* SOFT_HLUTNM = "soft_lutpair49" *)
LUT2 #(
.INIT(4'hE))
_carry_i_19
(.I0(sel0[10]),
.I1(sel0[9]),
.O(_carry_i_19_n_0));
LUT1 #(
.INIT(2'h1))
_carry_i_2
(.I0(z0_carry_i_9_n_0),
.O(_carry_i_2_n_0));
LUT6 #(
.INIT(64'h5554444400000000))
_carry_i_3
(.I0(sel0[23]),
.I1(_carry_i_5_n_0),
.I2(sel0[14]),
.I3(_carry_i_6_n_0),
.I4(_carry_i_7_n_0),
.I5(_carry_i_8_n_0),
.O(_carry_i_3_n_0));
LUT6 #(
.INIT(64'hA8A8A8A8A8A8A800))
_carry_i_4
(.I0(_carry_i_9_n_0),
.I1(_carry_i_10_n_0),
.I2(_carry_i_11_n_0),
.I3(_carry_i_12_n_0),
.I4(sel0[1]),
.I5(_carry_i_13_n_0),
.O(_carry_i_4_n_0));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT4 #(
.INIT(16'hFFFE))
_carry_i_5
(.I0(sel0[22]),
.I1(sel0[21]),
.I2(sel0[19]),
.I3(sel0[20]),
.O(_carry_i_5_n_0));
LUT6 #(
.INIT(64'hFFFFFFFFEEEEEEEF))
_carry_i_6
(.I0(sel0[12]),
.I1(sel0[13]),
.I2(sel0[10]),
.I3(sel0[9]),
.I4(_carry_i_14_n_0),
.I5(sel0[11]),
.O(_carry_i_6_n_0));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT4 #(
.INIT(16'h0001))
_carry_i_7
(.I0(sel0[18]),
.I1(sel0[17]),
.I2(sel0[15]),
.I3(sel0[16]),
.O(_carry_i_7_n_0));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
_carry_i_8
(.I0(sel0[3]),
.I1(sel0[5]),
.I2(sel0[6]),
.I3(_carry_i_5_n_0),
.I4(sel0[4]),
.I5(\z[31]_INST_0_i_4_n_0 ),
.O(_carry_i_8_n_0));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT5 #(
.INIT(32'h54545455))
_carry_i_9
(.I0(sel0[23]),
.I1(sel0[22]),
.I2(sel0[21]),
.I3(sel0[19]),
.I4(sel0[20]),
.O(_carry_i_9_n_0));
CARRY4 large_mant1_carry
(.CI(1'b0),
.CO({large_mant1_carry_n_0,large_mant1_carry_n_1,large_mant1_carry_n_2,large_mant1_carry_n_3}),
.CYINIT(1'b0),
.DI({large_mant1_carry_i_1_n_0,large_mant1_carry_i_2_n_0,large_mant1_carry_i_3_n_0,large_mant1_carry_i_4_n_0}),
.O(NLW_large_mant1_carry_O_UNCONNECTED[3:0]),
.S({large_mant1_carry_i_5_n_0,large_mant1_carry_i_6_n_0,large_mant1_carry_i_7_n_0,large_mant1_carry_i_8_n_0}));
LUT4 #(
.INIT(16'h2F02))
large_mant1_carry_i_1
(.I0(x[29]),
.I1(y[29]),
.I2(y[30]),
.I3(x[30]),
.O(large_mant1_carry_i_1_n_0));
LUT4 #(
.INIT(16'h2F02))
large_mant1_carry_i_2
(.I0(x[27]),
.I1(y[27]),
.I2(y[28]),
.I3(x[28]),
.O(large_mant1_carry_i_2_n_0));
LUT4 #(
.INIT(16'h2F02))
large_mant1_carry_i_3
(.I0(x[25]),
.I1(y[25]),
.I2(y[26]),
.I3(x[26]),
.O(large_mant1_carry_i_3_n_0));
LUT4 #(
.INIT(16'h2F02))
large_mant1_carry_i_4
(.I0(x[23]),
.I1(y[23]),
.I2(y[24]),
.I3(x[24]),
.O(large_mant1_carry_i_4_n_0));
LUT4 #(
.INIT(16'h9009))
large_mant1_carry_i_5
(.I0(x[29]),
.I1(y[29]),
.I2(x[30]),
.I3(y[30]),
.O(large_mant1_carry_i_5_n_0));
LUT4 #(
.INIT(16'h9009))
large_mant1_carry_i_6
(.I0(x[27]),
.I1(y[27]),
.I2(x[28]),
.I3(y[28]),
.O(large_mant1_carry_i_6_n_0));
LUT4 #(
.INIT(16'h9009))
large_mant1_carry_i_7
(.I0(x[25]),
.I1(y[25]),
.I2(x[26]),
.I3(y[26]),
.O(large_mant1_carry_i_7_n_0));
LUT4 #(
.INIT(16'h9009))
large_mant1_carry_i_8
(.I0(x[23]),
.I1(y[23]),
.I2(x[24]),
.I3(y[24]),
.O(large_mant1_carry_i_8_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 sign00__0_carry
(.CI(1'b0),
.CO({sign00__0_carry_n_0,sign00__0_carry_n_1,sign00__0_carry_n_2,sign00__0_carry_n_3}),
.CYINIT(A[0]),
.DI({sign00__0_carry_i_2_n_0,sign00__0_carry_i_3_n_0,sign00__0_carry_i_4_n_0,sign00__0_carry_i_5_n_0}),
.O({sel0[2:0],sign00__0_carry_n_7}),
.S({sign00__0_carry_i_6_n_0,sign00__0_carry_i_7_n_0,sign00__0_carry_i_8_n_0,sign00__0_carry_i_9_n_0}));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 sign00__0_carry__0
(.CI(sign00__0_carry_n_0),
.CO({sign00__0_carry__0_n_0,sign00__0_carry__0_n_1,sign00__0_carry__0_n_2,sign00__0_carry__0_n_3}),
.CYINIT(1'b0),
.DI({sign00__0_carry__0_i_1_n_0,sign00__0_carry__0_i_2_n_0,sign00__0_carry__0_i_3_n_0,sign00__0_carry__0_i_4_n_0}),
.O(sel0[6:3]),
.S({sign00__0_carry__0_i_5_n_0,sign00__0_carry__0_i_6_n_0,sign00__0_carry__0_i_7_n_0,sign00__0_carry__0_i_8_n_0}));
LUT1 #(
.INIT(2'h1))
sign00__0_carry__0_i_1
(.I0(sign00__0_carry__0_i_9_n_0),
.O(sign00__0_carry__0_i_1_n_0));
LUT5 #(
.INIT(32'h47FFFFFF))
sign00__0_carry__0_i_10
(.I0(sign00__0_carry__0_i_21_n_0),
.I1(sum4[0]),
.I2(sign00__0_carry__0_i_22_n_0),
.I3(sign00__0_carry_i_25_n_0),
.I4(sum3),
.O(sign00__0_carry__0_i_10_n_0));
LUT6 #(
.INIT(64'h00000000FEBA028A))
sign00__0_carry__0_i_11
(.I0(sign00__0_carry__0_i_23_n_0),
.I1(sum3),
.I2(sign00__0_carry_i_12_n_6),
.I3(sum4[2]),
.I4(sign00__0_carry_i_33_n_0),
.I5(sign00__0_carry_i_42_n_0),
.O(sign00__0_carry__0_i_11_n_0));
LUT5 #(
.INIT(32'h47FFFFFF))
sign00__0_carry__0_i_12
(.I0(sign00__0_carry__0_i_22_n_0),
.I1(sum4[0]),
.I2(sign00__0_carry__0_i_24_n_0),
.I3(sign00__0_carry_i_25_n_0),
.I4(sum3),
.O(sign00__0_carry__0_i_12_n_0));
LUT6 #(
.INIT(64'h00000000FEBA028A))
sign00__0_carry__0_i_13
(.I0(sign00__0_carry__0_i_25_n_0),
.I1(sum3),
.I2(sign00__0_carry_i_12_n_6),
.I3(sum4[2]),
.I4(sign00__0_carry_i_35_n_0),
.I5(sign00__0_carry_i_42_n_0),
.O(sign00__0_carry__0_i_13_n_0));
LUT5 #(
.INIT(32'h47FFFFFF))
sign00__0_carry__0_i_14
(.I0(sign00__0_carry__0_i_24_n_0),
.I1(sum4[0]),
.I2(sign00__0_carry_i_23_n_0),
.I3(sign00__0_carry_i_25_n_0),
.I4(sum3),
.O(sign00__0_carry__0_i_14_n_0));
LUT6 #(
.INIT(64'h00000000FEBA028A))
sign00__0_carry__0_i_15
(.I0(sign00__0_carry__0_i_26_n_0),
.I1(sum3),
.I2(sign00__0_carry_i_12_n_6),
.I3(sum4[2]),
.I4(sign00__0_carry__0_i_27_n_0),
.I5(sign00__0_carry_i_42_n_0),
.O(sign00__0_carry__0_i_15_n_0));
LUT6 #(
.INIT(64'h55555655AAAAAAAA))
sign00__0_carry__0_i_16
(.I0(sign00__0_carry_i_5_n_0),
.I1(sum3),
.I2(sign00__0_carry_i_17_n_0),
.I3(sign00__0_carry__0_i_28_n_0),
.I4(sign00__0_carry_i_42_n_0),
.I5(sign00__0_carry__0_i_10_n_0),
.O(sign00__0_carry__0_i_16_n_0));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT3 #(
.INIT(8'hAC))
sign00__0_carry__0_i_17
(.I0(x[5]),
.I1(y[5]),
.I2(large_mant1_carry_n_0),
.O(A[5]));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT3 #(
.INIT(8'hAC))
sign00__0_carry__0_i_18
(.I0(x[4]),
.I1(y[4]),
.I2(large_mant1_carry_n_0),
.O(A[4]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
sign00__0_carry__0_i_19
(.I0(sign00__0_carry__0_i_29_n_0),
.I1(sign00__0_carry_i_51_n_0),
.I2(sign00__0_carry_i_38_n_0),
.I3(sign00__0_carry__0_i_30_n_0),
.I4(sign00__0_carry_i_41_n_0),
.I5(sign00__0_carry__0_i_31_n_0),
.O(sign00__0_carry__0_i_19_n_0));
LUT5 #(
.INIT(32'hAAA2555D))
sign00__0_carry__0_i_2
(.I0(sign00__0_carry__0_i_10_n_0),
.I1(sign00__0_carry__0_i_11_n_0),
.I2(sum3),
.I3(sign00__0_carry_i_12_n_4),
.I4(sign00__0_carry_i_5_n_0),
.O(sign00__0_carry__0_i_2_n_0));
LUT5 #(
.INIT(32'h47FFFFFF))
sign00__0_carry__0_i_20
(.I0(sign00__0_carry__1_i_32_n_0),
.I1(sum4[0]),
.I2(sign00__0_carry__0_i_21_n_0),
.I3(sign00__0_carry_i_25_n_0),
.I4(sum3),
.O(sign00__0_carry__0_i_20_n_0));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
sign00__0_carry__0_i_21
(.I0(sign00__0_carry__0_i_32_n_0),
.I1(sign00__0_carry_i_47_n_0),
.I2(sum4[1]),
.I3(sign00__0_carry__0_i_33_n_0),
.I4(sum4[2]),
.I5(sign00__0_carry__0_i_34_n_0),
.O(sign00__0_carry__0_i_21_n_0));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
sign00__0_carry__0_i_22
(.I0(sign00__0_carry__0_i_35_n_0),
.I1(sign00__0_carry_i_45_n_0),
.I2(sum4[1]),
.I3(sign00__0_carry_i_43_n_0),
.I4(sum4[2]),
.I5(sign00__0_carry_i_44_n_0),
.O(sign00__0_carry__0_i_22_n_0));
LUT6 #(
.INIT(64'hD080FFFFD0800000))
sign00__0_carry__0_i_23
(.I0(sum4[0]),
.I1(small_mant[3]),
.I2(sign00__0_carry_i_39_n_0),
.I3(small_mant[4]),
.I4(sign00__0_carry_i_41_n_0),
.I5(sign00__0_carry__0_i_38_n_0),
.O(sign00__0_carry__0_i_23_n_0));
LUT6 #(
.INIT(64'hB8B8B8B8FF33CC00))
sign00__0_carry__0_i_24
(.I0(sign00__0_carry__0_i_33_n_0),
.I1(sum4[2]),
.I2(sign00__0_carry__0_i_34_n_0),
.I3(sign00__0_carry_i_47_n_0),
.I4(sign00__0_carry_i_48_n_0),
.I5(sum4[1]),
.O(sign00__0_carry__0_i_24_n_0));
LUT6 #(
.INIT(64'hD080FFFFD0800000))
sign00__0_carry__0_i_25
(.I0(sum4[0]),
.I1(small_mant[2]),
.I2(sign00__0_carry_i_39_n_0),
.I3(small_mant[3]),
.I4(sign00__0_carry_i_41_n_0),
.I5(sign00__0_carry__0_i_30_n_0),
.O(sign00__0_carry__0_i_25_n_0));
LUT6 #(
.INIT(64'hD080FFFFD0800000))
sign00__0_carry__0_i_26
(.I0(sum4[0]),
.I1(small_mant[1]),
.I2(sign00__0_carry_i_39_n_0),
.I3(small_mant[2]),
.I4(sign00__0_carry_i_41_n_0),
.I5(sign00__0_carry__0_i_39_n_0),
.O(sign00__0_carry__0_i_26_n_0));
LUT6 #(
.INIT(64'h0000000044400400))
sign00__0_carry__0_i_27
(.I0(sum4[0]),
.I1(sign00__0_carry_i_39_n_0),
.I2(large_mant1_carry_n_0),
.I3(x[0]),
.I4(y[0]),
.I5(sign00__0_carry_i_41_n_0),
.O(sign00__0_carry__0_i_27_n_0));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
sign00__0_carry__0_i_28
(.I0(sign00__0_carry__0_i_40_n_0),
.I1(sign00__0_carry__0_i_41_n_0),
.I2(sign00__0_carry_i_38_n_0),
.I3(sign00__0_carry__0_i_39_n_0),
.I4(sign00__0_carry_i_41_n_0),
.I5(sign00__0_carry__0_i_38_n_0),
.O(sign00__0_carry__0_i_28_n_0));
LUT6 #(
.INIT(64'h0000000D00000008))
sign00__0_carry__0_i_29
(.I0(sum4[0]),
.I1(small_mant[0]),
.I2(sign00__0_carry_i_69_n_0),
.I3(sign00__0_carry_i_59_n_0),
.I4(sign00__0_carry_i_58_n_0),
.I5(small_mant[1]),
.O(sign00__0_carry__0_i_29_n_0));
LUT5 #(
.INIT(32'hAAA2555D))
sign00__0_carry__0_i_3
(.I0(sign00__0_carry__0_i_12_n_0),
.I1(sign00__0_carry__0_i_13_n_0),
.I2(sum3),
.I3(sign00__0_carry_i_12_n_4),
.I4(sign00__0_carry_i_5_n_0),
.O(sign00__0_carry__0_i_3_n_0));
LUT6 #(
.INIT(64'h0000000D00000008))
sign00__0_carry__0_i_30
(.I0(sum4[0]),
.I1(small_mant[4]),
.I2(sign00__0_carry_i_69_n_0),
.I3(sign00__0_carry_i_59_n_0),
.I4(sign00__0_carry_i_58_n_0),
.I5(small_mant[5]),
.O(sign00__0_carry__0_i_30_n_0));
LUT6 #(
.INIT(64'h0000000D00000008))
sign00__0_carry__0_i_31
(.I0(sum4[0]),
.I1(small_mant[6]),
.I2(sign00__0_carry_i_69_n_0),
.I3(sign00__0_carry_i_59_n_0),
.I4(sign00__0_carry_i_58_n_0),
.I5(small_mant[7]),
.O(sign00__0_carry__0_i_31_n_0));
LUT6 #(
.INIT(64'h00000000BBB88B88))
sign00__0_carry__0_i_32
(.I0(small_mant[21]),
.I1(sum4[3]),
.I2(large_mant1_carry_n_0),
.I3(x[13]),
.I4(y[13]),
.I5(sum4[4]),
.O(sign00__0_carry__0_i_32_n_0));
LUT6 #(
.INIT(64'h00000000BBB88B88))
sign00__0_carry__0_i_33
(.I0(small_mant[19]),
.I1(sum4[3]),
.I2(large_mant1_carry_n_0),
.I3(x[11]),
.I4(y[11]),
.I5(sum4[4]),
.O(sign00__0_carry__0_i_33_n_0));
LUT6 #(
.INIT(64'h00FF00FFE4FFE400))
sign00__0_carry__0_i_34
(.I0(large_mant1_carry_n_0),
.I1(x[15]),
.I2(y[15]),
.I3(sum4[3]),
.I4(small_mant[7]),
.I5(sum4[4]),
.O(sign00__0_carry__0_i_34_n_0));
LUT6 #(
.INIT(64'h00000000BBB88B88))
sign00__0_carry__0_i_35
(.I0(small_mant[20]),
.I1(sum4[3]),
.I2(large_mant1_carry_n_0),
.I3(x[12]),
.I4(y[12]),
.I5(sum4[4]),
.O(sign00__0_carry__0_i_35_n_0));
(* SOFT_HLUTNM = "soft_lutpair34" *)
LUT3 #(
.INIT(8'hAC))
sign00__0_carry__0_i_36
(.I0(y[3]),
.I1(x[3]),
.I2(large_mant1_carry_n_0),
.O(small_mant[3]));
(* SOFT_HLUTNM = "soft_lutpair39" *)
LUT3 #(
.INIT(8'hAC))
sign00__0_carry__0_i_37
(.I0(y[4]),
.I1(x[4]),
.I2(large_mant1_carry_n_0),
.O(small_mant[4]));
LUT6 #(
.INIT(64'h0000000D00000008))
sign00__0_carry__0_i_38
(.I0(sum4[0]),
.I1(small_mant[5]),
.I2(sign00__0_carry_i_69_n_0),
.I3(sign00__0_carry_i_59_n_0),
.I4(sign00__0_carry_i_58_n_0),
.I5(small_mant[6]),
.O(sign00__0_carry__0_i_38_n_0));
LUT6 #(
.INIT(64'h0000000D00000008))
sign00__0_carry__0_i_39
(.I0(sum4[0]),
.I1(small_mant[3]),
.I2(sign00__0_carry_i_69_n_0),
.I3(sign00__0_carry_i_59_n_0),
.I4(sign00__0_carry_i_58_n_0),
.I5(small_mant[4]),
.O(sign00__0_carry__0_i_39_n_0));
LUT5 #(
.INIT(32'hAAA2555D))
sign00__0_carry__0_i_4
(.I0(sign00__0_carry__0_i_14_n_0),
.I1(sign00__0_carry__0_i_15_n_0),
.I2(sum3),
.I3(sign00__0_carry_i_12_n_4),
.I4(sign00__0_carry_i_5_n_0),
.O(sign00__0_carry__0_i_4_n_0));
LUT5 #(
.INIT(32'h00000002))
sign00__0_carry__0_i_40
(.I0(small_mant[0]),
.I1(sign00__0_carry_i_58_n_0),
.I2(sign00__0_carry_i_59_n_0),
.I3(sign00__0_carry_i_69_n_0),
.I4(sum4[0]),
.O(sign00__0_carry__0_i_40_n_0));
LUT6 #(
.INIT(64'h0000000D00000008))
sign00__0_carry__0_i_41
(.I0(sum4[0]),
.I1(small_mant[1]),
.I2(sign00__0_carry_i_69_n_0),
.I3(sign00__0_carry_i_59_n_0),
.I4(sign00__0_carry_i_58_n_0),
.I5(small_mant[2]),
.O(sign00__0_carry__0_i_41_n_0));
LUT4 #(
.INIT(16'hA965))
sign00__0_carry__0_i_5
(.I0(sign00__0_carry__0_i_9_n_0),
.I1(large_mant1_carry_n_0),
.I2(y[7]),
.I3(x[7]),
.O(sign00__0_carry__0_i_5_n_0));
LUT4 #(
.INIT(16'hA965))
sign00__0_carry__0_i_6
(.I0(sign00__0_carry__0_i_16_n_0),
.I1(large_mant1_carry_n_0),
.I2(y[6]),
.I3(x[6]),
.O(sign00__0_carry__0_i_6_n_0));
LUT6 #(
.INIT(64'h555DAAA2AAA2555D))
sign00__0_carry__0_i_7
(.I0(sign00__0_carry__0_i_12_n_0),
.I1(sign00__0_carry__0_i_13_n_0),
.I2(sign00__0_carry_i_17_n_0),
.I3(sum3),
.I4(sign00__0_carry_i_5_n_0),
.I5(A[5]),
.O(sign00__0_carry__0_i_7_n_0));
LUT6 #(
.INIT(64'h555DAAA2AAA2555D))
sign00__0_carry__0_i_8
(.I0(sign00__0_carry__0_i_14_n_0),
.I1(sign00__0_carry__0_i_15_n_0),
.I2(sign00__0_carry_i_17_n_0),
.I3(sum3),
.I4(sign00__0_carry_i_5_n_0),
.I5(A[4]),
.O(sign00__0_carry__0_i_8_n_0));
LUT6 #(
.INIT(64'h55555655AAAAAAAA))
sign00__0_carry__0_i_9
(.I0(sign00__0_carry_i_5_n_0),
.I1(sum3),
.I2(sign00__0_carry_i_17_n_0),
.I3(sign00__0_carry__0_i_19_n_0),
.I4(sign00__0_carry_i_42_n_0),
.I5(sign00__0_carry__0_i_20_n_0),
.O(sign00__0_carry__0_i_9_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 sign00__0_carry__1
(.CI(sign00__0_carry__0_n_0),
.CO({sign00__0_carry__1_n_0,sign00__0_carry__1_n_1,sign00__0_carry__1_n_2,sign00__0_carry__1_n_3}),
.CYINIT(1'b0),
.DI({sign00__0_carry__1_i_1_n_0,sign00__0_carry__1_i_2_n_0,sign00__0_carry__1_i_3_n_0,sign00__0_carry__1_i_4_n_0}),
.O(sel0[10:7]),
.S({sign00__0_carry__1_i_5_n_0,sign00__0_carry__1_i_6_n_0,sign00__0_carry__1_i_7_n_0,sign00__0_carry__1_i_8_n_0}));
LUT5 #(
.INIT(32'hAAA2555D))
sign00__0_carry__1_i_1
(.I0(sign00__0_carry__1_i_9_n_0),
.I1(sign00__0_carry__1_i_10_n_0),
.I2(sum3),
.I3(sign00__0_carry_i_12_n_4),
.I4(sign00__0_carry_i_5_n_0),
.O(sign00__0_carry__1_i_1_n_0));
LUT5 #(
.INIT(32'h30BB3088))
sign00__0_carry__1_i_10
(.I0(sign00__0_carry_i_26_n_0),
.I1(sign00__0_carry_i_42_n_0),
.I2(sign00__0_carry__1_i_26_n_0),
.I3(sign00__0_carry_i_38_n_0),
.I4(sign00__0_carry__1_i_27_n_0),
.O(sign00__0_carry__1_i_10_n_0));
LUT5 #(
.INIT(32'h47FFFFFF))
sign00__0_carry__1_i_11
(.I0(sign00__0_carry__1_i_25_n_0),
.I1(sum4[0]),
.I2(sign00__0_carry__1_i_28_n_0),
.I3(sign00__0_carry_i_25_n_0),
.I4(sum3),
.O(sign00__0_carry__1_i_11_n_0));
LUT5 #(
.INIT(32'h30BB3088))
sign00__0_carry__1_i_12
(.I0(sign00__0_carry_i_33_n_0),
.I1(sign00__0_carry_i_42_n_0),
.I2(sign00__0_carry__0_i_23_n_0),
.I3(sign00__0_carry_i_38_n_0),
.I4(sign00__0_carry__1_i_29_n_0),
.O(sign00__0_carry__1_i_12_n_0));
LUT5 #(
.INIT(32'h47FFFFFF))
sign00__0_carry__1_i_13
(.I0(sign00__0_carry__1_i_28_n_0),
.I1(sum4[0]),
.I2(sign00__0_carry__1_i_30_n_0),
.I3(sign00__0_carry_i_25_n_0),
.I4(sum3),
.O(sign00__0_carry__1_i_13_n_0));
LUT5 #(
.INIT(32'h30BB3088))
sign00__0_carry__1_i_14
(.I0(sign00__0_carry_i_35_n_0),
.I1(sign00__0_carry_i_42_n_0),
.I2(sign00__0_carry__0_i_25_n_0),
.I3(sign00__0_carry_i_38_n_0),
.I4(sign00__0_carry__1_i_31_n_0),
.O(sign00__0_carry__1_i_14_n_0));
LUT5 #(
.INIT(32'h47FFFFFF))
sign00__0_carry__1_i_15
(.I0(sign00__0_carry__1_i_30_n_0),
.I1(sum4[0]),
.I2(sign00__0_carry__1_i_32_n_0),
.I3(sign00__0_carry_i_25_n_0),
.I4(sum3),
.O(sign00__0_carry__1_i_15_n_0));
LUT5 #(
.INIT(32'h30BB3088))
sign00__0_carry__1_i_16
(.I0(sign00__0_carry__0_i_27_n_0),
.I1(sign00__0_carry_i_42_n_0),
.I2(sign00__0_carry__0_i_26_n_0),
.I3(sign00__0_carry_i_38_n_0),
.I4(sign00__0_carry__1_i_33_n_0),
.O(sign00__0_carry__1_i_16_n_0));
LUT6 #(
.INIT(64'h0000000033E200E2))
sign00__0_carry__1_i_17
(.I0(sign00__0_carry__1_i_27_n_0),
.I1(sign00__0_carry_i_38_n_0),
.I2(sign00__0_carry__1_i_26_n_0),
.I3(sign00__0_carry_i_42_n_0),
.I4(sign00__0_carry_i_26_n_0),
.I5(sign00__0_carry_i_17_n_0),
.O(sign00__0_carry__1_i_17_n_0));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT3 #(
.INIT(8'hAC))
sign00__0_carry__1_i_18
(.I0(x[11]),
.I1(y[11]),
.I2(large_mant1_carry_n_0),
.O(A[11]));
LUT6 #(
.INIT(64'h0000000033E200E2))
sign00__0_carry__1_i_19
(.I0(sign00__0_carry__1_i_29_n_0),
.I1(sign00__0_carry_i_38_n_0),
.I2(sign00__0_carry__0_i_23_n_0),
.I3(sign00__0_carry_i_42_n_0),
.I4(sign00__0_carry_i_33_n_0),
.I5(sign00__0_carry_i_17_n_0),
.O(sign00__0_carry__1_i_19_n_0));
LUT5 #(
.INIT(32'hAAA2555D))
sign00__0_carry__1_i_2
(.I0(sign00__0_carry__1_i_11_n_0),
.I1(sign00__0_carry__1_i_12_n_0),
.I2(sum3),
.I3(sign00__0_carry_i_12_n_4),
.I4(sign00__0_carry_i_5_n_0),
.O(sign00__0_carry__1_i_2_n_0));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT3 #(
.INIT(8'hAC))
sign00__0_carry__1_i_20
(.I0(x[10]),
.I1(y[10]),
.I2(large_mant1_carry_n_0),
.O(A[10]));
LUT6 #(
.INIT(64'h0000000033E200E2))
sign00__0_carry__1_i_21
(.I0(sign00__0_carry__1_i_31_n_0),
.I1(sign00__0_carry_i_38_n_0),
.I2(sign00__0_carry__0_i_25_n_0),
.I3(sign00__0_carry_i_42_n_0),
.I4(sign00__0_carry_i_35_n_0),
.I5(sign00__0_carry_i_17_n_0),
.O(sign00__0_carry__1_i_21_n_0));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT3 #(
.INIT(8'hAC))
sign00__0_carry__1_i_22
(.I0(x[9]),
.I1(y[9]),
.I2(large_mant1_carry_n_0),
.O(A[9]));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT3 #(
.INIT(8'hAC))
sign00__0_carry__1_i_23
(.I0(x[8]),
.I1(y[8]),
.I2(large_mant1_carry_n_0),
.O(A[8]));
(* SOFT_HLUTNM = "soft_lutpair35" *)
LUT3 #(
.INIT(8'hB8))
sign00__0_carry__1_i_24
(.I0(sign00__0_carry__1_i_34_n_0),
.I1(sum4[1]),
.I2(sign00__0_carry__1_i_35_n_0),
.O(sign00__0_carry__1_i_24_n_0));
LUT5 #(
.INIT(32'hFF00B8B8))
sign00__0_carry__1_i_25
(.I0(sign00__0_carry__1_i_36_n_0),
.I1(sum4[2]),
.I2(sign00__0_carry__0_i_33_n_0),
.I3(sign00__0_carry__1_i_37_n_0),
.I4(sum4[1]),
.O(sign00__0_carry__1_i_25_n_0));
LUT6 #(
.INIT(64'hD080FFFFD0800000))
sign00__0_carry__1_i_26
(.I0(sum4[0]),
.I1(small_mant[4]),
.I2(sign00__0_carry_i_39_n_0),
.I3(small_mant[5]),
.I4(sign00__0_carry_i_41_n_0),
.I5(sign00__0_carry__0_i_31_n_0),
.O(sign00__0_carry__1_i_26_n_0));
LUT6 #(
.INIT(64'hD080FFFFD0800000))
sign00__0_carry__1_i_27
(.I0(sum4[0]),
.I1(small_mant[8]),
.I2(sign00__0_carry_i_39_n_0),
.I3(small_mant[9]),
.I4(sign00__0_carry_i_41_n_0),
.I5(sign00__0_carry__1_i_41_n_0),
.O(sign00__0_carry__1_i_27_n_0));
LUT5 #(
.INIT(32'hFF00B8B8))
sign00__0_carry__1_i_28
(.I0(sign00__0_carry__1_i_42_n_0),
.I1(sum4[2]),
.I2(sign00__0_carry_i_43_n_0),
.I3(sign00__0_carry__1_i_35_n_0),
.I4(sum4[1]),
.O(sign00__0_carry__1_i_28_n_0));
LUT6 #(
.INIT(64'hD080FFFFD0800000))
sign00__0_carry__1_i_29
(.I0(sum4[0]),
.I1(small_mant[7]),
.I2(sign00__0_carry_i_39_n_0),
.I3(small_mant[8]),
.I4(sign00__0_carry_i_41_n_0),
.I5(sign00__0_carry__1_i_44_n_0),
.O(sign00__0_carry__1_i_29_n_0));
LUT5 #(
.INIT(32'hAAA2555D))
sign00__0_carry__1_i_3
(.I0(sign00__0_carry__1_i_13_n_0),
.I1(sign00__0_carry__1_i_14_n_0),
.I2(sum3),
.I3(sign00__0_carry_i_12_n_4),
.I4(sign00__0_carry_i_5_n_0),
.O(sign00__0_carry__1_i_3_n_0));
LUT6 #(
.INIT(64'hFF33CC00B8B8B8B8))
sign00__0_carry__1_i_30
(.I0(sign00__0_carry__0_i_32_n_0),
.I1(sum4[2]),
.I2(sign00__0_carry_i_47_n_0),
.I3(sign00__0_carry__1_i_36_n_0),
.I4(sign00__0_carry__0_i_33_n_0),
.I5(sum4[1]),
.O(sign00__0_carry__1_i_30_n_0));
LUT6 #(
.INIT(64'hD080FFFFD0800000))
sign00__0_carry__1_i_31
(.I0(sum4[0]),
.I1(small_mant[6]),
.I2(sign00__0_carry_i_39_n_0),
.I3(small_mant[7]),
.I4(sign00__0_carry_i_41_n_0),
.I5(sign00__0_carry__1_i_46_n_0),
.O(sign00__0_carry__1_i_31_n_0));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
sign00__0_carry__1_i_32
(.I0(sign00__0_carry__1_i_42_n_0),
.I1(sign00__0_carry_i_43_n_0),
.I2(sum4[1]),
.I3(sign00__0_carry__0_i_35_n_0),
.I4(sum4[2]),
.I5(sign00__0_carry_i_45_n_0),
.O(sign00__0_carry__1_i_32_n_0));
LUT6 #(
.INIT(64'hD080FFFFD0800000))
sign00__0_carry__1_i_33
(.I0(sum4[0]),
.I1(small_mant[5]),
.I2(sign00__0_carry_i_39_n_0),
.I3(small_mant[6]),
.I4(sign00__0_carry_i_41_n_0),
.I5(sign00__0_carry__1_i_47_n_0),
.O(sign00__0_carry__1_i_33_n_0));
LUT5 #(
.INIT(32'h04FF0400))
sign00__0_carry__1_i_34
(.I0(sum4[4]),
.I1(small_mant[18]),
.I2(sum4[3]),
.I3(sum4[2]),
.I4(sign00__0_carry__1_i_42_n_0),
.O(sign00__0_carry__1_i_34_n_0));
LUT5 #(
.INIT(32'h04FF0400))
sign00__0_carry__1_i_35
(.I0(sum4[4]),
.I1(small_mant[16]),
.I2(sum4[3]),
.I3(sum4[2]),
.I4(sign00__0_carry__0_i_35_n_0),
.O(sign00__0_carry__1_i_35_n_0));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT5 #(
.INIT(32'h0000FEBA))
sign00__0_carry__1_i_36
(.I0(sum4[3]),
.I1(large_mant1_carry_n_0),
.I2(x[15]),
.I3(y[15]),
.I4(sum4[4]),
.O(sign00__0_carry__1_i_36_n_0));
LUT5 #(
.INIT(32'h04FF0400))
sign00__0_carry__1_i_37
(.I0(sum4[4]),
.I1(small_mant[17]),
.I2(sum4[3]),
.I3(sum4[2]),
.I4(sign00__0_carry__0_i_32_n_0),
.O(sign00__0_carry__1_i_37_n_0));
(* SOFT_HLUTNM = "soft_lutpair40" *)
LUT3 #(
.INIT(8'hAC))
sign00__0_carry__1_i_38
(.I0(y[5]),
.I1(x[5]),
.I2(large_mant1_carry_n_0),
.O(small_mant[5]));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT3 #(
.INIT(8'hAC))
sign00__0_carry__1_i_39
(.I0(y[8]),
.I1(x[8]),
.I2(large_mant1_carry_n_0),
.O(small_mant[8]));
LUT5 #(
.INIT(32'hAAA2555D))
sign00__0_carry__1_i_4
(.I0(sign00__0_carry__1_i_15_n_0),
.I1(sign00__0_carry__1_i_16_n_0),
.I2(sum3),
.I3(sign00__0_carry_i_12_n_4),
.I4(sign00__0_carry_i_5_n_0),
.O(sign00__0_carry__1_i_4_n_0));
(* SOFT_HLUTNM = "soft_lutpair38" *)
LUT3 #(
.INIT(8'hAC))
sign00__0_carry__1_i_40
(.I0(y[9]),
.I1(x[9]),
.I2(large_mant1_carry_n_0),
.O(small_mant[9]));
LUT6 #(
.INIT(64'h0000000D00000008))
sign00__0_carry__1_i_41
(.I0(sum4[0]),
.I1(small_mant[10]),
.I2(sign00__0_carry_i_69_n_0),
.I3(sign00__0_carry_i_59_n_0),
.I4(sign00__0_carry_i_58_n_0),
.I5(small_mant[11]),
.O(sign00__0_carry__1_i_41_n_0));
LUT6 #(
.INIT(64'h00000000BBB88B88))
sign00__0_carry__1_i_42
(.I0(small_mant[22]),
.I1(sum4[3]),
.I2(large_mant1_carry_n_0),
.I3(x[14]),
.I4(y[14]),
.I5(sum4[4]),
.O(sign00__0_carry__1_i_42_n_0));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT3 #(
.INIT(8'hAC))
sign00__0_carry__1_i_43
(.I0(y[7]),
.I1(x[7]),
.I2(large_mant1_carry_n_0),
.O(small_mant[7]));
LUT6 #(
.INIT(64'h0000000D00000008))
sign00__0_carry__1_i_44
(.I0(sum4[0]),
.I1(small_mant[9]),
.I2(sign00__0_carry_i_69_n_0),
.I3(sign00__0_carry_i_59_n_0),
.I4(sign00__0_carry_i_58_n_0),
.I5(small_mant[10]),
.O(sign00__0_carry__1_i_44_n_0));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT3 #(
.INIT(8'hAC))
sign00__0_carry__1_i_45
(.I0(y[6]),
.I1(x[6]),
.I2(large_mant1_carry_n_0),
.O(small_mant[6]));
LUT6 #(
.INIT(64'h0000000D00000008))
sign00__0_carry__1_i_46
(.I0(sum4[0]),
.I1(small_mant[8]),
.I2(sign00__0_carry_i_69_n_0),
.I3(sign00__0_carry_i_59_n_0),
.I4(sign00__0_carry_i_58_n_0),
.I5(small_mant[9]),
.O(sign00__0_carry__1_i_46_n_0));
LUT6 #(
.INIT(64'h0000000D00000008))
sign00__0_carry__1_i_47
(.I0(sum4[0]),
.I1(small_mant[7]),
.I2(sign00__0_carry_i_69_n_0),
.I3(sign00__0_carry_i_59_n_0),
.I4(sign00__0_carry_i_58_n_0),
.I5(small_mant[8]),
.O(sign00__0_carry__1_i_47_n_0));
LUT6 #(
.INIT(64'hA25D5DA25DA2A25D))
sign00__0_carry__1_i_5
(.I0(sign00__0_carry__1_i_9_n_0),
.I1(sign00__0_carry__1_i_17_n_0),
.I2(sum3),
.I3(x[31]),
.I4(y[31]),
.I5(A[11]),
.O(sign00__0_carry__1_i_5_n_0));
LUT6 #(
.INIT(64'hA25D5DA25DA2A25D))
sign00__0_carry__1_i_6
(.I0(sign00__0_carry__1_i_11_n_0),
.I1(sign00__0_carry__1_i_19_n_0),
.I2(sum3),
.I3(x[31]),
.I4(y[31]),
.I5(A[10]),
.O(sign00__0_carry__1_i_6_n_0));
LUT6 #(
.INIT(64'hA25D5DA25DA2A25D))
sign00__0_carry__1_i_7
(.I0(sign00__0_carry__1_i_13_n_0),
.I1(sign00__0_carry__1_i_21_n_0),
.I2(sum3),
.I3(x[31]),
.I4(y[31]),
.I5(A[9]),
.O(sign00__0_carry__1_i_7_n_0));
LUT6 #(
.INIT(64'h555DAAA2AAA2555D))
sign00__0_carry__1_i_8
(.I0(sign00__0_carry__1_i_15_n_0),
.I1(sign00__0_carry__1_i_16_n_0),
.I2(sign00__0_carry_i_17_n_0),
.I3(sum3),
.I4(sign00__0_carry_i_5_n_0),
.I5(A[8]),
.O(sign00__0_carry__1_i_8_n_0));
LUT5 #(
.INIT(32'h47FFFFFF))
sign00__0_carry__1_i_9
(.I0(sign00__0_carry__1_i_24_n_0),
.I1(sum4[0]),
.I2(sign00__0_carry__1_i_25_n_0),
.I3(sign00__0_carry_i_25_n_0),
.I4(sum3),
.O(sign00__0_carry__1_i_9_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 sign00__0_carry__2
(.CI(sign00__0_carry__1_n_0),
.CO({sign00__0_carry__2_n_0,sign00__0_carry__2_n_1,sign00__0_carry__2_n_2,sign00__0_carry__2_n_3}),
.CYINIT(1'b0),
.DI({sign00__0_carry__2_i_1_n_0,sign00__0_carry__2_i_2_n_0,sign00__0_carry__2_i_3_n_0,sign00__0_carry__2_i_4_n_0}),
.O(sel0[14:11]),
.S({sign00__0_carry__2_i_5_n_0,sign00__0_carry__2_i_6_n_0,sign00__0_carry__2_i_7_n_0,sign00__0_carry__2_i_8_n_0}));
LUT5 #(
.INIT(32'hAAA2555D))
sign00__0_carry__2_i_1
(.I0(sign00__0_carry__2_i_9_n_0),
.I1(sign00__0_carry__2_i_10_n_0),
.I2(sum3),
.I3(sign00__0_carry_i_12_n_4),
.I4(sign00__0_carry_i_5_n_0),
.O(sign00__0_carry__2_i_1_n_0));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
sign00__0_carry__2_i_10
(.I0(sign00__0_carry_i_26_n_0),
.I1(sign00__0_carry__1_i_26_n_0),
.I2(sign00__0_carry_i_42_n_0),
.I3(sign00__0_carry__1_i_27_n_0),
.I4(sign00__0_carry_i_38_n_0),
.I5(sign00__0_carry__2_i_23_n_0),
.O(sign00__0_carry__2_i_10_n_0));
LUT5 #(
.INIT(32'h47FFFFFF))
sign00__0_carry__2_i_11
(.I0(sign00__0_carry__2_i_22_n_0),
.I1(sum4[0]),
.I2(sign00__0_carry__2_i_24_n_0),
.I3(sign00__0_carry_i_25_n_0),
.I4(sum3),
.O(sign00__0_carry__2_i_11_n_0));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
sign00__0_carry__2_i_12
(.I0(sign00__0_carry_i_33_n_0),
.I1(sign00__0_carry__0_i_23_n_0),
.I2(sign00__0_carry_i_42_n_0),
.I3(sign00__0_carry__1_i_29_n_0),
.I4(sign00__0_carry_i_38_n_0),
.I5(sign00__0_carry__2_i_25_n_0),
.O(sign00__0_carry__2_i_12_n_0));
LUT5 #(
.INIT(32'h47FFFFFF))
sign00__0_carry__2_i_13
(.I0(sign00__0_carry__2_i_24_n_0),
.I1(sum4[0]),
.I2(sign00__0_carry__2_i_26_n_0),
.I3(sign00__0_carry_i_25_n_0),
.I4(sum3),
.O(sign00__0_carry__2_i_13_n_0));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
sign00__0_carry__2_i_14
(.I0(sign00__0_carry_i_35_n_0),
.I1(sign00__0_carry__0_i_25_n_0),
.I2(sign00__0_carry_i_42_n_0),
.I3(sign00__0_carry__1_i_31_n_0),
.I4(sign00__0_carry_i_38_n_0),
.I5(sign00__0_carry__2_i_27_n_0),
.O(sign00__0_carry__2_i_14_n_0));
LUT5 #(
.INIT(32'h47FFFFFF))
sign00__0_carry__2_i_15
(.I0(sign00__0_carry__2_i_26_n_0),
.I1(sum4[0]),
.I2(sign00__0_carry__1_i_24_n_0),
.I3(sign00__0_carry_i_25_n_0),
.I4(sum3),
.O(sign00__0_carry__2_i_15_n_0));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
sign00__0_carry__2_i_16
(.I0(sign00__0_carry__0_i_27_n_0),
.I1(sign00__0_carry__0_i_26_n_0),
.I2(sign00__0_carry_i_42_n_0),
.I3(sign00__0_carry__1_i_33_n_0),
.I4(sign00__0_carry_i_38_n_0),
.I5(sign00__0_carry__2_i_28_n_0),
.O(sign00__0_carry__2_i_16_n_0));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT3 #(
.INIT(8'hAC))
sign00__0_carry__2_i_17
(.I0(x[15]),
.I1(y[15]),
.I2(large_mant1_carry_n_0),
.O(A[15]));
(* SOFT_HLUTNM = "soft_lutpair37" *)
LUT3 #(
.INIT(8'hAC))
sign00__0_carry__2_i_18
(.I0(x[14]),
.I1(y[14]),
.I2(large_mant1_carry_n_0),
.O(A[14]));
(* SOFT_HLUTNM = "soft_lutpair36" *)
LUT3 #(
.INIT(8'hAC))
sign00__0_carry__2_i_19
(.I0(x[13]),
.I1(y[13]),
.I2(large_mant1_carry_n_0),
.O(A[13]));
LUT5 #(
.INIT(32'hAAA2555D))
sign00__0_carry__2_i_2
(.I0(sign00__0_carry__2_i_11_n_0),
.I1(sign00__0_carry__2_i_12_n_0),
.I2(sum3),
.I3(sign00__0_carry_i_12_n_4),
.I4(sign00__0_carry_i_5_n_0),
.O(sign00__0_carry__2_i_2_n_0));
(* SOFT_HLUTNM = "soft_lutpair34" *)
LUT3 #(
.INIT(8'hAC))
sign00__0_carry__2_i_20
(.I0(x[12]),
.I1(y[12]),
.I2(large_mant1_carry_n_0),
.O(A[12]));
LUT3 #(
.INIT(8'hB8))
sign00__0_carry__2_i_21
(.I0(sign00__0_carry__2_i_29_n_0),
.I1(sum4[1]),
.I2(sign00__0_carry__2_i_30_n_0),
.O(sign00__0_carry__2_i_21_n_0));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT3 #(
.INIT(8'hB8))
sign00__0_carry__2_i_22
(.I0(sign00__0_carry__2_i_31_n_0),
.I1(sum4[1]),
.I2(sign00__0_carry__2_i_32_n_0),
.O(sign00__0_carry__2_i_22_n_0));
LUT6 #(
.INIT(64'hD080FFFFD0800000))
sign00__0_carry__2_i_23
(.I0(sum4[0]),
.I1(small_mant[12]),
.I2(sign00__0_carry_i_39_n_0),
.I3(small_mant[13]),
.I4(sign00__0_carry_i_41_n_0),
.I5(sign00__0_carry__2_i_35_n_0),
.O(sign00__0_carry__2_i_23_n_0));
(* SOFT_HLUTNM = "soft_lutpair35" *)
LUT3 #(
.INIT(8'hB8))
sign00__0_carry__2_i_24
(.I0(sign00__0_carry__2_i_30_n_0),
.I1(sum4[1]),
.I2(sign00__0_carry__1_i_34_n_0),
.O(sign00__0_carry__2_i_24_n_0));
LUT6 #(
.INIT(64'hD080FFFFD0800000))
sign00__0_carry__2_i_25
(.I0(sum4[0]),
.I1(small_mant[11]),
.I2(sign00__0_carry_i_39_n_0),
.I3(small_mant[12]),
.I4(sign00__0_carry_i_41_n_0),
.I5(sign00__0_carry__2_i_37_n_0),
.O(sign00__0_carry__2_i_25_n_0));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT3 #(
.INIT(8'hB8))
sign00__0_carry__2_i_26
(.I0(sign00__0_carry__2_i_32_n_0),
.I1(sum4[1]),
.I2(sign00__0_carry__1_i_37_n_0),
.O(sign00__0_carry__2_i_26_n_0));
LUT6 #(
.INIT(64'hD080FFFFD0800000))
sign00__0_carry__2_i_27
(.I0(sum4[0]),
.I1(small_mant[10]),
.I2(sign00__0_carry_i_39_n_0),
.I3(small_mant[11]),
.I4(sign00__0_carry_i_41_n_0),
.I5(sign00__0_carry__2_i_39_n_0),
.O(sign00__0_carry__2_i_27_n_0));
LUT6 #(
.INIT(64'hD080FFFFD0800000))
sign00__0_carry__2_i_28
(.I0(sum4[0]),
.I1(small_mant[9]),
.I2(sign00__0_carry_i_39_n_0),
.I3(small_mant[10]),
.I4(sign00__0_carry_i_41_n_0),
.I5(sign00__0_carry__2_i_40_n_0),
.O(sign00__0_carry__2_i_28_n_0));
LUT5 #(
.INIT(32'h00000B08))
sign00__0_carry__2_i_29
(.I0(small_mant[22]),
.I1(sum4[2]),
.I2(sum4[4]),
.I3(small_mant[18]),
.I4(sum4[3]),
.O(sign00__0_carry__2_i_29_n_0));
LUT5 #(
.INIT(32'hAAA2555D))
sign00__0_carry__2_i_3
(.I0(sign00__0_carry__2_i_13_n_0),
.I1(sign00__0_carry__2_i_14_n_0),
.I2(sum3),
.I3(sign00__0_carry_i_12_n_4),
.I4(sign00__0_carry_i_5_n_0),
.O(sign00__0_carry__2_i_3_n_0));
LUT5 #(
.INIT(32'h00000B08))
sign00__0_carry__2_i_30
(.I0(small_mant[20]),
.I1(sum4[2]),
.I2(sum4[4]),
.I3(small_mant[16]),
.I4(sum4[3]),
.O(sign00__0_carry__2_i_30_n_0));
LUT5 #(
.INIT(32'h00000B08))
sign00__0_carry__2_i_31
(.I0(small_mant[21]),
.I1(sum4[2]),
.I2(sum4[4]),
.I3(small_mant[17]),
.I4(sum4[3]),
.O(sign00__0_carry__2_i_31_n_0));
LUT5 #(
.INIT(32'h04FF0400))
sign00__0_carry__2_i_32
(.I0(sum4[4]),
.I1(small_mant[19]),
.I2(sum4[3]),
.I3(sum4[2]),
.I4(sign00__0_carry__1_i_36_n_0),
.O(sign00__0_carry__2_i_32_n_0));
(* SOFT_HLUTNM = "soft_lutpair36" *)
LUT3 #(
.INIT(8'hAC))
sign00__0_carry__2_i_33
(.I0(y[12]),
.I1(x[12]),
.I2(large_mant1_carry_n_0),
.O(small_mant[12]));
(* SOFT_HLUTNM = "soft_lutpair37" *)
LUT3 #(
.INIT(8'hAC))
sign00__0_carry__2_i_34
(.I0(y[13]),
.I1(x[13]),
.I2(large_mant1_carry_n_0),
.O(small_mant[13]));
LUT6 #(
.INIT(64'h0000000D00000008))
sign00__0_carry__2_i_35
(.I0(sum4[0]),
.I1(small_mant[14]),
.I2(sign00__0_carry_i_69_n_0),
.I3(sign00__0_carry_i_59_n_0),
.I4(sign00__0_carry_i_58_n_0),
.I5(small_mant[15]),
.O(sign00__0_carry__2_i_35_n_0));
(* SOFT_HLUTNM = "soft_lutpair42" *)
LUT3 #(
.INIT(8'hAC))
sign00__0_carry__2_i_36
(.I0(y[11]),
.I1(x[11]),
.I2(large_mant1_carry_n_0),
.O(small_mant[11]));
LUT6 #(
.INIT(64'h0000000D00000008))
sign00__0_carry__2_i_37
(.I0(sum4[0]),
.I1(small_mant[13]),
.I2(sign00__0_carry_i_69_n_0),
.I3(sign00__0_carry_i_59_n_0),
.I4(sign00__0_carry_i_58_n_0),
.I5(small_mant[14]),
.O(sign00__0_carry__2_i_37_n_0));
(* SOFT_HLUTNM = "soft_lutpair41" *)
LUT3 #(
.INIT(8'hAC))
sign00__0_carry__2_i_38
(.I0(y[10]),
.I1(x[10]),
.I2(large_mant1_carry_n_0),
.O(small_mant[10]));
LUT6 #(
.INIT(64'h0000000D00000008))
sign00__0_carry__2_i_39
(.I0(sum4[0]),
.I1(small_mant[12]),
.I2(sign00__0_carry_i_69_n_0),
.I3(sign00__0_carry_i_59_n_0),
.I4(sign00__0_carry_i_58_n_0),
.I5(small_mant[13]),
.O(sign00__0_carry__2_i_39_n_0));
LUT5 #(
.INIT(32'hAAA2555D))
sign00__0_carry__2_i_4
(.I0(sign00__0_carry__2_i_15_n_0),
.I1(sign00__0_carry__2_i_16_n_0),
.I2(sum3),
.I3(sign00__0_carry_i_12_n_4),
.I4(sign00__0_carry_i_5_n_0),
.O(sign00__0_carry__2_i_4_n_0));
LUT6 #(
.INIT(64'h0000000D00000008))
sign00__0_carry__2_i_40
(.I0(sum4[0]),
.I1(small_mant[11]),
.I2(sign00__0_carry_i_69_n_0),
.I3(sign00__0_carry_i_59_n_0),
.I4(sign00__0_carry_i_58_n_0),
.I5(small_mant[12]),
.O(sign00__0_carry__2_i_40_n_0));
(* SOFT_HLUTNM = "soft_lutpair39" *)
LUT3 #(
.INIT(8'hAC))
sign00__0_carry__2_i_41
(.I0(y[14]),
.I1(x[14]),
.I2(large_mant1_carry_n_0),
.O(small_mant[14]));
LUT6 #(
.INIT(64'h555DAAA2AAA2555D))
sign00__0_carry__2_i_5
(.I0(sign00__0_carry__2_i_9_n_0),
.I1(sign00__0_carry__2_i_10_n_0),
.I2(sign00__0_carry_i_17_n_0),
.I3(sum3),
.I4(sign00__0_carry_i_5_n_0),
.I5(A[15]),
.O(sign00__0_carry__2_i_5_n_0));
LUT6 #(
.INIT(64'h555DAAA2AAA2555D))
sign00__0_carry__2_i_6
(.I0(sign00__0_carry__2_i_11_n_0),
.I1(sign00__0_carry__2_i_12_n_0),
.I2(sign00__0_carry_i_17_n_0),
.I3(sum3),
.I4(sign00__0_carry_i_5_n_0),
.I5(A[14]),
.O(sign00__0_carry__2_i_6_n_0));
LUT6 #(
.INIT(64'h555DAAA2AAA2555D))
sign00__0_carry__2_i_7
(.I0(sign00__0_carry__2_i_13_n_0),
.I1(sign00__0_carry__2_i_14_n_0),
.I2(sign00__0_carry_i_17_n_0),
.I3(sum3),
.I4(sign00__0_carry_i_5_n_0),
.I5(A[13]),
.O(sign00__0_carry__2_i_7_n_0));
LUT6 #(
.INIT(64'h555DAAA2AAA2555D))
sign00__0_carry__2_i_8
(.I0(sign00__0_carry__2_i_15_n_0),
.I1(sign00__0_carry__2_i_16_n_0),
.I2(sign00__0_carry_i_17_n_0),
.I3(sum3),
.I4(sign00__0_carry_i_5_n_0),
.I5(A[12]),
.O(sign00__0_carry__2_i_8_n_0));
LUT5 #(
.INIT(32'h47FFFFFF))
sign00__0_carry__2_i_9
(.I0(sign00__0_carry__2_i_21_n_0),
.I1(sum4[0]),
.I2(sign00__0_carry__2_i_22_n_0),
.I3(sign00__0_carry_i_25_n_0),
.I4(sum3),
.O(sign00__0_carry__2_i_9_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 sign00__0_carry__3
(.CI(sign00__0_carry__2_n_0),
.CO({sign00__0_carry__3_n_0,sign00__0_carry__3_n_1,sign00__0_carry__3_n_2,sign00__0_carry__3_n_3}),
.CYINIT(1'b0),
.DI({sign00__0_carry__3_i_1_n_0,sign00__0_carry__3_i_2_n_0,sign00__0_carry__3_i_3_n_0,sign00__0_carry__3_i_4_n_0}),
.O(sel0[18:15]),
.S({sign00__0_carry__3_i_5_n_0,sign00__0_carry__3_i_6_n_0,sign00__0_carry__3_i_7_n_0,sign00__0_carry__3_i_8_n_0}));
LUT6 #(
.INIT(64'hAAAA202A5555DFD5))
sign00__0_carry__3_i_1
(.I0(sign00__0_carry__3_i_9_n_0),
.I1(sign00__0_carry_i_11_n_0),
.I2(sign00__0_carry_i_17_n_0),
.I3(sign00__0_carry__3_i_10_n_0),
.I4(sum3),
.I5(sign00__0_carry_i_5_n_0),
.O(sign00__0_carry__3_i_1_n_0));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
sign00__0_carry__3_i_10
(.I0(sign00__0_carry__1_i_26_n_0),
.I1(sign00__0_carry__1_i_27_n_0),
.I2(sign00__0_carry_i_42_n_0),
.I3(sign00__0_carry__2_i_23_n_0),
.I4(sign00__0_carry_i_38_n_0),
.I5(sign00__0_carry__3_i_25_n_0),
.O(sign00__0_carry__3_i_10_n_0));
LUT5 #(
.INIT(32'h47FFFFFF))
sign00__0_carry__3_i_11
(.I0(sign00__0_carry__3_i_24_n_0),
.I1(sum4[0]),
.I2(sign00__0_carry__3_i_26_n_0),
.I3(sign00__0_carry_i_25_n_0),
.I4(sum3),
.O(sign00__0_carry__3_i_11_n_0));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
sign00__0_carry__3_i_12
(.I0(sign00__0_carry__0_i_23_n_0),
.I1(sign00__0_carry__1_i_29_n_0),
.I2(sign00__0_carry_i_42_n_0),
.I3(sign00__0_carry__2_i_25_n_0),
.I4(sign00__0_carry_i_38_n_0),
.I5(sign00__0_carry__3_i_27_n_0),
.O(sign00__0_carry__3_i_12_n_0));
LUT5 #(
.INIT(32'h47FFFFFF))
sign00__0_carry__3_i_13
(.I0(sign00__0_carry__3_i_26_n_0),
.I1(sum4[0]),
.I2(sign00__0_carry__3_i_28_n_0),
.I3(sign00__0_carry_i_25_n_0),
.I4(sum3),
.O(sign00__0_carry__3_i_13_n_0));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
sign00__0_carry__3_i_14
(.I0(sign00__0_carry__0_i_25_n_0),
.I1(sign00__0_carry__1_i_31_n_0),
.I2(sign00__0_carry_i_42_n_0),
.I3(sign00__0_carry__2_i_27_n_0),
.I4(sign00__0_carry_i_38_n_0),
.I5(sign00__0_carry__3_i_29_n_0),
.O(sign00__0_carry__3_i_14_n_0));
LUT5 #(
.INIT(32'h47FFFFFF))
sign00__0_carry__3_i_15
(.I0(sign00__0_carry__3_i_28_n_0),
.I1(sum4[0]),
.I2(sign00__0_carry__2_i_21_n_0),
.I3(sign00__0_carry_i_25_n_0),
.I4(sum3),
.O(sign00__0_carry__3_i_15_n_0));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
sign00__0_carry__3_i_16
(.I0(sign00__0_carry__0_i_26_n_0),
.I1(sign00__0_carry__1_i_33_n_0),
.I2(sign00__0_carry_i_42_n_0),
.I3(sign00__0_carry__2_i_28_n_0),
.I4(sign00__0_carry_i_38_n_0),
.I5(sign00__0_carry__3_i_30_n_0),
.O(sign00__0_carry__3_i_16_n_0));
LUT6 #(
.INIT(64'h0F004F4F0F004040))
sign00__0_carry__3_i_17
(.I0(sign00__0_carry_i_38_n_0),
.I1(sign00__0_carry_i_26_n_0),
.I2(sign00__0_carry_i_17_n_0),
.I3(sign00__0_carry__3_i_31_n_0),
.I4(sign00__0_carry_i_42_n_0),
.I5(sign00__0_carry__3_i_32_n_0),
.O(sum2[19]));
(* SOFT_HLUTNM = "soft_lutpair38" *)
LUT3 #(
.INIT(8'hAC))
sign00__0_carry__3_i_18
(.I0(x[19]),
.I1(y[19]),
.I2(large_mant1_carry_n_0),
.O(A[19]));
LUT6 #(
.INIT(64'h0F004F4F0F004040))
sign00__0_carry__3_i_19
(.I0(sign00__0_carry_i_38_n_0),
.I1(sign00__0_carry_i_33_n_0),
.I2(sign00__0_carry_i_17_n_0),
.I3(sign00__0_carry__3_i_33_n_0),
.I4(sign00__0_carry_i_42_n_0),
.I5(sign00__0_carry__3_i_34_n_0),
.O(sum2[18]));
LUT6 #(
.INIT(64'hAAAA202A5555DFD5))
sign00__0_carry__3_i_2
(.I0(sign00__0_carry__3_i_11_n_0),
.I1(sign00__0_carry_i_14_n_0),
.I2(sign00__0_carry_i_17_n_0),
.I3(sign00__0_carry__3_i_12_n_0),
.I4(sum3),
.I5(sign00__0_carry_i_5_n_0),
.O(sign00__0_carry__3_i_2_n_0));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT3 #(
.INIT(8'hAC))
sign00__0_carry__3_i_20
(.I0(x[18]),
.I1(y[18]),
.I2(large_mant1_carry_n_0),
.O(A[18]));
LUT6 #(
.INIT(64'hFAFAABFBFFFFABFB))
sign00__0_carry__3_i_21
(.I0(sum3),
.I1(sign00__0_carry__3_i_35_n_0),
.I2(sign00__0_carry_i_42_n_0),
.I3(sign00__0_carry__3_i_36_n_0),
.I4(sign00__0_carry_i_17_n_0),
.I5(sign00__0_carry__3_i_37_n_0),
.O(sign00__0_carry__3_i_21_n_0));
LUT6 #(
.INIT(64'hFAFAABFBFFFFABFB))
sign00__0_carry__3_i_22
(.I0(sum3),
.I1(sign00__0_carry__3_i_38_n_0),
.I2(sign00__0_carry_i_42_n_0),
.I3(sign00__0_carry__3_i_39_n_0),
.I4(sign00__0_carry_i_17_n_0),
.I5(sign00__0_carry__3_i_40_n_0),
.O(sign00__0_carry__3_i_22_n_0));
LUT6 #(
.INIT(64'h0000000000000B08))
sign00__0_carry__3_i_23
(.I0(small_mant[22]),
.I1(sum4[1]),
.I2(sum4[3]),
.I3(small_mant[20]),
.I4(sum4[4]),
.I5(sum4[2]),
.O(sign00__0_carry__3_i_23_n_0));
LUT6 #(
.INIT(64'h00000000003B0038))
sign00__0_carry__3_i_24
(.I0(small_mant[21]),
.I1(sum4[1]),
.I2(sum4[2]),
.I3(sum4[4]),
.I4(small_mant[19]),
.I5(sum4[3]),
.O(sign00__0_carry__3_i_24_n_0));
LUT6 #(
.INIT(64'hD080FFFFD0800000))
sign00__0_carry__3_i_25
(.I0(sum4[0]),
.I1(small_mant[16]),
.I2(sign00__0_carry_i_39_n_0),
.I3(small_mant[17]),
.I4(sign00__0_carry_i_41_n_0),
.I5(sign00__0_carry__3_i_47_n_0),
.O(sign00__0_carry__3_i_25_n_0));
LUT6 #(
.INIT(64'h0004FFFF00040000))
sign00__0_carry__3_i_26
(.I0(sum4[3]),
.I1(small_mant[20]),
.I2(sum4[4]),
.I3(sum4[2]),
.I4(sum4[1]),
.I5(sign00__0_carry__2_i_29_n_0),
.O(sign00__0_carry__3_i_26_n_0));
LUT6 #(
.INIT(64'hCFC5C0C0CAC0C0C0))
sign00__0_carry__3_i_27
(.I0(sum4[0]),
.I1(sign00__0_carry__3_i_48_n_0),
.I2(sign00__0_carry_i_41_n_0),
.I3(small_mant[17]),
.I4(sign00__0_carry_i_39_n_0),
.I5(small_mant[18]),
.O(sign00__0_carry__3_i_27_n_0));
LUT6 #(
.INIT(64'h0032FFFF00320000))
sign00__0_carry__3_i_28
(.I0(sum4[2]),
.I1(sum4[4]),
.I2(small_mant[19]),
.I3(sum4[3]),
.I4(sum4[1]),
.I5(sign00__0_carry__2_i_31_n_0),
.O(sign00__0_carry__3_i_28_n_0));
LUT6 #(
.INIT(64'hCFC5C0C0CAC0C0C0))
sign00__0_carry__3_i_29
(.I0(sum4[0]),
.I1(sign00__0_carry__2_i_35_n_0),
.I2(sign00__0_carry_i_41_n_0),
.I3(small_mant[16]),
.I4(sign00__0_carry_i_39_n_0),
.I5(small_mant[17]),
.O(sign00__0_carry__3_i_29_n_0));
LUT6 #(
.INIT(64'hAAAA202A5555DFD5))
sign00__0_carry__3_i_3
(.I0(sign00__0_carry__3_i_13_n_0),
.I1(sign00__0_carry_i_16_n_0),
.I2(sign00__0_carry_i_17_n_0),
.I3(sign00__0_carry__3_i_14_n_0),
.I4(sum3),
.I5(sign00__0_carry_i_5_n_0),
.O(sign00__0_carry__3_i_3_n_0));
LUT6 #(
.INIT(64'hCFC5C0C0CAC0C0C0))
sign00__0_carry__3_i_30
(.I0(sum4[0]),
.I1(sign00__0_carry__2_i_37_n_0),
.I2(sign00__0_carry_i_41_n_0),
.I3(small_mant[15]),
.I4(sign00__0_carry_i_39_n_0),
.I5(small_mant[16]),
.O(sign00__0_carry__3_i_30_n_0));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
sign00__0_carry__3_i_31
(.I0(sign00__0_carry__0_i_30_n_0),
.I1(sign00__0_carry__0_i_31_n_0),
.I2(sign00__0_carry_i_38_n_0),
.I3(sign00__0_carry__1_i_46_n_0),
.I4(sign00__0_carry_i_41_n_0),
.I5(sign00__0_carry__1_i_41_n_0),
.O(sign00__0_carry__3_i_31_n_0));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
sign00__0_carry__3_i_32
(.I0(sign00__0_carry__2_i_39_n_0),
.I1(sign00__0_carry__2_i_35_n_0),
.I2(sign00__0_carry_i_38_n_0),
.I3(sign00__0_carry__3_i_51_n_0),
.I4(sign00__0_carry_i_41_n_0),
.I5(sign00__0_carry__3_i_47_n_0),
.O(sign00__0_carry__3_i_32_n_0));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
sign00__0_carry__3_i_33
(.I0(sign00__0_carry__0_i_39_n_0),
.I1(sign00__0_carry__0_i_38_n_0),
.I2(sign00__0_carry_i_38_n_0),
.I3(sign00__0_carry__1_i_47_n_0),
.I4(sign00__0_carry_i_41_n_0),
.I5(sign00__0_carry__1_i_44_n_0),
.O(sign00__0_carry__3_i_33_n_0));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
sign00__0_carry__3_i_34
(.I0(sign00__0_carry__2_i_40_n_0),
.I1(sign00__0_carry__2_i_37_n_0),
.I2(sign00__0_carry_i_38_n_0),
.I3(sign00__0_carry__3_i_48_n_0),
.I4(sign00__0_carry_i_41_n_0),
.I5(sign00__0_carry__3_i_52_n_0),
.O(sign00__0_carry__3_i_34_n_0));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
sign00__0_carry__3_i_35
(.I0(sign00__0_carry__1_i_41_n_0),
.I1(sign00__0_carry__2_i_39_n_0),
.I2(sign00__0_carry_i_38_n_0),
.I3(sign00__0_carry__2_i_35_n_0),
.I4(sign00__0_carry_i_41_n_0),
.I5(sign00__0_carry__3_i_51_n_0),
.O(sign00__0_carry__3_i_35_n_0));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
sign00__0_carry__3_i_36
(.I0(sign00__0_carry_i_51_n_0),
.I1(sign00__0_carry__0_i_30_n_0),
.I2(sign00__0_carry_i_38_n_0),
.I3(sign00__0_carry__0_i_31_n_0),
.I4(sign00__0_carry_i_41_n_0),
.I5(sign00__0_carry__1_i_46_n_0),
.O(sign00__0_carry__3_i_36_n_0));
LUT6 #(
.INIT(64'h0000000031002000))
sign00__0_carry__3_i_37
(.I0(sum4[0]),
.I1(sign00__0_carry_i_41_n_0),
.I2(small_mant[0]),
.I3(sign00__0_carry_i_39_n_0),
.I4(small_mant[1]),
.I5(sign00__0_carry_i_38_n_0),
.O(sign00__0_carry__3_i_37_n_0));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
sign00__0_carry__3_i_38
(.I0(sign00__0_carry__1_i_44_n_0),
.I1(sign00__0_carry__2_i_40_n_0),
.I2(sign00__0_carry_i_38_n_0),
.I3(sign00__0_carry__2_i_37_n_0),
.I4(sign00__0_carry_i_41_n_0),
.I5(sign00__0_carry__3_i_48_n_0),
.O(sign00__0_carry__3_i_38_n_0));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
sign00__0_carry__3_i_39
(.I0(sign00__0_carry__0_i_41_n_0),
.I1(sign00__0_carry__0_i_39_n_0),
.I2(sign00__0_carry_i_38_n_0),
.I3(sign00__0_carry__0_i_38_n_0),
.I4(sign00__0_carry_i_41_n_0),
.I5(sign00__0_carry__1_i_47_n_0),
.O(sign00__0_carry__3_i_39_n_0));
LUT6 #(
.INIT(64'hAAAA202A5555DFD5))
sign00__0_carry__3_i_4
(.I0(sign00__0_carry__3_i_15_n_0),
.I1(sign00__0_carry_i_22_n_0),
.I2(sign00__0_carry_i_17_n_0),
.I3(sign00__0_carry__3_i_16_n_0),
.I4(sum3),
.I5(sign00__0_carry_i_5_n_0),
.O(sign00__0_carry__3_i_4_n_0));
LUT5 #(
.INIT(32'h00000040))
sign00__0_carry__3_i_40
(.I0(sign00__0_carry_i_41_n_0),
.I1(small_mant[0]),
.I2(sign00__0_carry_i_39_n_0),
.I3(sum4[0]),
.I4(sign00__0_carry_i_38_n_0),
.O(sign00__0_carry__3_i_40_n_0));
(* SOFT_HLUTNM = "soft_lutpair47" *)
LUT3 #(
.INIT(8'hAC))
sign00__0_carry__3_i_41
(.I0(y[22]),
.I1(x[22]),
.I2(large_mant1_carry_n_0),
.O(small_mant[22]));
(* SOFT_HLUTNM = "soft_lutpair44" *)
LUT3 #(
.INIT(8'hAC))
sign00__0_carry__3_i_42
(.I0(y[20]),
.I1(x[20]),
.I2(large_mant1_carry_n_0),
.O(small_mant[20]));
(* SOFT_HLUTNM = "soft_lutpair47" *)
LUT3 #(
.INIT(8'hAC))
sign00__0_carry__3_i_43
(.I0(y[21]),
.I1(x[21]),
.I2(large_mant1_carry_n_0),
.O(small_mant[21]));
(* SOFT_HLUTNM = "soft_lutpair44" *)
LUT3 #(
.INIT(8'hAC))
sign00__0_carry__3_i_44
(.I0(y[19]),
.I1(x[19]),
.I2(large_mant1_carry_n_0),
.O(small_mant[19]));
(* SOFT_HLUTNM = "soft_lutpair41" *)
LUT3 #(
.INIT(8'hAC))
sign00__0_carry__3_i_45
(.I0(y[16]),
.I1(x[16]),
.I2(large_mant1_carry_n_0),
.O(small_mant[16]));
(* SOFT_HLUTNM = "soft_lutpair42" *)
LUT3 #(
.INIT(8'hAC))
sign00__0_carry__3_i_46
(.I0(y[17]),
.I1(x[17]),
.I2(large_mant1_carry_n_0),
.O(small_mant[17]));
LUT6 #(
.INIT(64'h0000000D00000008))
sign00__0_carry__3_i_47
(.I0(sum4[0]),
.I1(small_mant[18]),
.I2(sign00__0_carry_i_69_n_0),
.I3(sign00__0_carry_i_59_n_0),
.I4(sign00__0_carry_i_58_n_0),
.I5(small_mant[19]),
.O(sign00__0_carry__3_i_47_n_0));
LUT6 #(
.INIT(64'h0000000D00000008))
sign00__0_carry__3_i_48
(.I0(sum4[0]),
.I1(small_mant[15]),
.I2(sign00__0_carry_i_69_n_0),
.I3(sign00__0_carry_i_59_n_0),
.I4(sign00__0_carry_i_58_n_0),
.I5(small_mant[16]),
.O(sign00__0_carry__3_i_48_n_0));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT3 #(
.INIT(8'hAC))
sign00__0_carry__3_i_49
(.I0(y[18]),
.I1(x[18]),
.I2(large_mant1_carry_n_0),
.O(small_mant[18]));
LUT6 #(
.INIT(64'hA25D5DA25DA2A25D))
sign00__0_carry__3_i_5
(.I0(sign00__0_carry__3_i_9_n_0),
.I1(sum2[19]),
.I2(sum3),
.I3(x[31]),
.I4(y[31]),
.I5(A[19]),
.O(sign00__0_carry__3_i_5_n_0));
(* SOFT_HLUTNM = "soft_lutpair40" *)
LUT3 #(
.INIT(8'hAC))
sign00__0_carry__3_i_50
(.I0(y[15]),
.I1(x[15]),
.I2(large_mant1_carry_n_0),
.O(small_mant[15]));
LUT6 #(
.INIT(64'h0000000D00000008))
sign00__0_carry__3_i_51
(.I0(sum4[0]),
.I1(small_mant[16]),
.I2(sign00__0_carry_i_69_n_0),
.I3(sign00__0_carry_i_59_n_0),
.I4(sign00__0_carry_i_58_n_0),
.I5(small_mant[17]),
.O(sign00__0_carry__3_i_51_n_0));
LUT6 #(
.INIT(64'h0000000D00000008))
sign00__0_carry__3_i_52
(.I0(sum4[0]),
.I1(small_mant[17]),
.I2(sign00__0_carry_i_69_n_0),
.I3(sign00__0_carry_i_59_n_0),
.I4(sign00__0_carry_i_58_n_0),
.I5(small_mant[18]),
.O(sign00__0_carry__3_i_52_n_0));
LUT6 #(
.INIT(64'hA25D5DA25DA2A25D))
sign00__0_carry__3_i_6
(.I0(sign00__0_carry__3_i_11_n_0),
.I1(sum2[18]),
.I2(sum3),
.I3(x[31]),
.I4(y[31]),
.I5(A[18]),
.O(sign00__0_carry__3_i_6_n_0));
LUT6 #(
.INIT(64'h7878788787788787))
sign00__0_carry__3_i_7
(.I0(sign00__0_carry__3_i_13_n_0),
.I1(sign00__0_carry__3_i_21_n_0),
.I2(sign00__0_carry_i_5_n_0),
.I3(large_mant1_carry_n_0),
.I4(y[17]),
.I5(x[17]),
.O(sign00__0_carry__3_i_7_n_0));
LUT6 #(
.INIT(64'h7878788787788787))
sign00__0_carry__3_i_8
(.I0(sign00__0_carry__3_i_15_n_0),
.I1(sign00__0_carry__3_i_22_n_0),
.I2(sign00__0_carry_i_5_n_0),
.I3(large_mant1_carry_n_0),
.I4(y[16]),
.I5(x[16]),
.O(sign00__0_carry__3_i_8_n_0));
LUT5 #(
.INIT(32'h47FFFFFF))
sign00__0_carry__3_i_9
(.I0(sign00__0_carry__3_i_23_n_0),
.I1(sum4[0]),
.I2(sign00__0_carry__3_i_24_n_0),
.I3(sign00__0_carry_i_25_n_0),
.I4(sum3),
.O(sign00__0_carry__3_i_9_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 sign00__0_carry__4
(.CI(sign00__0_carry__3_n_0),
.CO({sign00__0_carry__4_n_0,sign00__0_carry__4_n_1,sign00__0_carry__4_n_2,sign00__0_carry__4_n_3}),
.CYINIT(1'b0),
.DI({sign00__0_carry__4_i_1_n_0,sign00__0_carry__4_i_2_n_0,sign00__0_carry__4_i_3_n_0,sign00__0_carry__4_i_4_n_0}),
.O(sel0[22:19]),
.S({sign00__0_carry__4_i_5_n_0,sign00__0_carry__4_i_6_n_0,sign00__0_carry__4_i_7_n_0,sign00__0_carry__4_i_8_n_0}));
LUT6 #(
.INIT(64'h5555303FAAAACFC0))
sign00__0_carry__4_i_1
(.I0(sign00__0_carry__4_i_9_n_0),
.I1(sign00__0_carry__4_i_10_n_0),
.I2(sign00__0_carry_i_17_n_0),
.I3(sign00__0_carry__4_i_11_n_0),
.I4(sum3),
.I5(sign00__0_carry_i_5_n_0),
.O(sign00__0_carry__4_i_1_n_0));
LUT6 #(
.INIT(64'h00000000FEBA028A))
sign00__0_carry__4_i_10
(.I0(sign00__0_carry__1_i_26_n_0),
.I1(sum3),
.I2(sign00__0_carry_i_12_n_6),
.I3(sum4[2]),
.I4(sign00__0_carry_i_26_n_0),
.I5(sign00__0_carry_i_42_n_0),
.O(sign00__0_carry__4_i_10_n_0));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
sign00__0_carry__4_i_11
(.I0(sign00__0_carry__1_i_27_n_0),
.I1(sign00__0_carry__2_i_23_n_0),
.I2(sign00__0_carry_i_42_n_0),
.I3(sign00__0_carry__3_i_25_n_0),
.I4(sign00__0_carry_i_38_n_0),
.I5(sign00__0_carry__4_i_21_n_0),
.O(sign00__0_carry__4_i_11_n_0));
LUT6 #(
.INIT(64'h7747FFFFFFFFFFFF))
sign00__0_carry__4_i_12
(.I0(sign00__0_carry__4_i_22_n_0),
.I1(sum4[0]),
.I2(sign00__0_carry__4_i_23_n_0),
.I3(sum4[1]),
.I4(sign00__0_carry_i_25_n_0),
.I5(sum3),
.O(sign00__0_carry__4_i_12_n_0));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
sign00__0_carry__4_i_13
(.I0(sign00__0_carry__1_i_29_n_0),
.I1(sign00__0_carry__2_i_25_n_0),
.I2(sign00__0_carry_i_42_n_0),
.I3(sign00__0_carry__3_i_27_n_0),
.I4(sign00__0_carry_i_38_n_0),
.I5(sign00__0_carry__4_i_24_n_0),
.O(sign00__0_carry__4_i_13_n_0));
LUT6 #(
.INIT(64'hD0DFFFFFFFFFFFFF))
sign00__0_carry__4_i_14
(.I0(sign00__0_carry__4_i_23_n_0),
.I1(sum4[1]),
.I2(sum4[0]),
.I3(sign00__0_carry__4_i_25_n_0),
.I4(sign00__0_carry_i_25_n_0),
.I5(sum3),
.O(sign00__0_carry__4_i_14_n_0));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
sign00__0_carry__4_i_15
(.I0(sign00__0_carry__1_i_31_n_0),
.I1(sign00__0_carry__2_i_27_n_0),
.I2(sign00__0_carry_i_42_n_0),
.I3(sign00__0_carry__3_i_29_n_0),
.I4(sign00__0_carry_i_38_n_0),
.I5(sign00__0_carry__4_i_26_n_0),
.O(sign00__0_carry__4_i_15_n_0));
LUT5 #(
.INIT(32'h47FFFFFF))
sign00__0_carry__4_i_16
(.I0(sign00__0_carry__4_i_25_n_0),
.I1(sum4[0]),
.I2(sign00__0_carry__3_i_23_n_0),
.I3(sign00__0_carry_i_25_n_0),
.I4(sum3),
.O(sign00__0_carry__4_i_16_n_0));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
sign00__0_carry__4_i_17
(.I0(sign00__0_carry__1_i_33_n_0),
.I1(sign00__0_carry__2_i_28_n_0),
.I2(sign00__0_carry_i_42_n_0),
.I3(sign00__0_carry__3_i_30_n_0),
.I4(sign00__0_carry_i_38_n_0),
.I5(sign00__0_carry__4_i_27_n_0),
.O(sign00__0_carry__4_i_17_n_0));
LUT6 #(
.INIT(64'hFAFAABFBFFFFABFB))
sign00__0_carry__4_i_18
(.I0(sum3),
.I1(sign00__0_carry__4_i_28_n_0),
.I2(sign00__0_carry_i_42_n_0),
.I3(sign00__0_carry__4_i_29_n_0),
.I4(sign00__0_carry_i_17_n_0),
.I5(sign00__0_carry__0_i_28_n_0),
.O(sign00__0_carry__4_i_18_n_0));
LUT6 #(
.INIT(64'hFAFAABFBFFFFABFB))
sign00__0_carry__4_i_19
(.I0(sum3),
.I1(sign00__0_carry__4_i_30_n_0),
.I2(sign00__0_carry_i_42_n_0),
.I3(sign00__0_carry__4_i_31_n_0),
.I4(sign00__0_carry_i_17_n_0),
.I5(sign00__0_carry__4_i_32_n_0),
.O(sign00__0_carry__4_i_19_n_0));
LUT6 #(
.INIT(64'hAAAA202A5555DFD5))
sign00__0_carry__4_i_2
(.I0(sign00__0_carry__4_i_12_n_0),
.I1(sign00__0_carry__0_i_11_n_0),
.I2(sign00__0_carry_i_17_n_0),
.I3(sign00__0_carry__4_i_13_n_0),
.I4(sum3),
.I5(sign00__0_carry_i_5_n_0),
.O(sign00__0_carry__4_i_2_n_0));
LUT6 #(
.INIT(64'hFAFAABFBFFFFABFB))
sign00__0_carry__4_i_20
(.I0(sum3),
.I1(sign00__0_carry__4_i_33_n_0),
.I2(sign00__0_carry_i_42_n_0),
.I3(sign00__0_carry__4_i_34_n_0),
.I4(sign00__0_carry_i_17_n_0),
.I5(sign00__0_carry__4_i_35_n_0),
.O(sign00__0_carry__4_i_20_n_0));
LUT6 #(
.INIT(64'hD8FFD85500000000))
sign00__0_carry__4_i_21
(.I0(sum4[0]),
.I1(small_mant[20]),
.I2(small_mant[21]),
.I3(sign00__0_carry_i_41_n_0),
.I4(small_mant[22]),
.I5(sign00__0_carry_i_39_n_0),
.O(sign00__0_carry__4_i_21_n_0));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT4 #(
.INIT(16'h0001))
sign00__0_carry__4_i_22
(.I0(sum4[2]),
.I1(sum4[4]),
.I2(sum4[3]),
.I3(sum4[1]),
.O(sign00__0_carry__4_i_22_n_0));
LUT6 #(
.INIT(64'h0000000000005410))
sign00__0_carry__4_i_23
(.I0(sum4[3]),
.I1(large_mant1_carry_n_0),
.I2(x[22]),
.I3(y[22]),
.I4(sum4[4]),
.I5(sum4[2]),
.O(sign00__0_carry__4_i_23_n_0));
LUT6 #(
.INIT(64'hD080FFFFD0800000))
sign00__0_carry__4_i_24
(.I0(sum4[0]),
.I1(small_mant[19]),
.I2(sign00__0_carry_i_39_n_0),
.I3(small_mant[20]),
.I4(sign00__0_carry_i_41_n_0),
.I5(sign00__0_carry__4_i_36_n_0),
.O(sign00__0_carry__4_i_24_n_0));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT5 #(
.INIT(32'h00000032))
sign00__0_carry__4_i_25
(.I0(sum4[1]),
.I1(sum4[3]),
.I2(small_mant[21]),
.I3(sum4[4]),
.I4(sum4[2]),
.O(sign00__0_carry__4_i_25_n_0));
LUT6 #(
.INIT(64'hD080FFFFD0800000))
sign00__0_carry__4_i_26
(.I0(sum4[0]),
.I1(small_mant[18]),
.I2(sign00__0_carry_i_39_n_0),
.I3(small_mant[19]),
.I4(sign00__0_carry_i_41_n_0),
.I5(sign00__0_carry__4_i_37_n_0),
.O(sign00__0_carry__4_i_26_n_0));
LUT6 #(
.INIT(64'hD080FFFFD0800000))
sign00__0_carry__4_i_27
(.I0(sum4[0]),
.I1(small_mant[17]),
.I2(sign00__0_carry_i_39_n_0),
.I3(small_mant[18]),
.I4(sign00__0_carry_i_41_n_0),
.I5(sign00__0_carry__4_i_38_n_0),
.O(sign00__0_carry__4_i_27_n_0));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
sign00__0_carry__4_i_28
(.I0(sign00__0_carry__3_i_48_n_0),
.I1(sign00__0_carry__3_i_52_n_0),
.I2(sign00__0_carry_i_38_n_0),
.I3(sign00__0_carry__4_i_38_n_0),
.I4(sign00__0_carry_i_41_n_0),
.I5(sign00__0_carry__4_i_36_n_0),
.O(sign00__0_carry__4_i_28_n_0));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
sign00__0_carry__4_i_29
(.I0(sign00__0_carry__1_i_47_n_0),
.I1(sign00__0_carry__1_i_44_n_0),
.I2(sign00__0_carry_i_38_n_0),
.I3(sign00__0_carry__2_i_40_n_0),
.I4(sign00__0_carry_i_41_n_0),
.I5(sign00__0_carry__2_i_37_n_0),
.O(sign00__0_carry__4_i_29_n_0));
LUT6 #(
.INIT(64'hAAAA202A5555DFD5))
sign00__0_carry__4_i_3
(.I0(sign00__0_carry__4_i_14_n_0),
.I1(sign00__0_carry__0_i_13_n_0),
.I2(sign00__0_carry_i_17_n_0),
.I3(sign00__0_carry__4_i_15_n_0),
.I4(sum3),
.I5(sign00__0_carry_i_5_n_0),
.O(sign00__0_carry__4_i_3_n_0));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
sign00__0_carry__4_i_30
(.I0(sign00__0_carry__2_i_35_n_0),
.I1(sign00__0_carry__3_i_51_n_0),
.I2(sign00__0_carry_i_38_n_0),
.I3(sign00__0_carry__3_i_47_n_0),
.I4(sign00__0_carry_i_41_n_0),
.I5(sign00__0_carry__4_i_37_n_0),
.O(sign00__0_carry__4_i_30_n_0));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
sign00__0_carry__4_i_31
(.I0(sign00__0_carry__0_i_31_n_0),
.I1(sign00__0_carry__1_i_46_n_0),
.I2(sign00__0_carry_i_38_n_0),
.I3(sign00__0_carry__1_i_41_n_0),
.I4(sign00__0_carry_i_41_n_0),
.I5(sign00__0_carry__2_i_39_n_0),
.O(sign00__0_carry__4_i_31_n_0));
LUT5 #(
.INIT(32'h30BB3088))
sign00__0_carry__4_i_32
(.I0(sign00__0_carry__0_i_29_n_0),
.I1(sign00__0_carry_i_38_n_0),
.I2(sign00__0_carry_i_51_n_0),
.I3(sign00__0_carry_i_41_n_0),
.I4(sign00__0_carry__0_i_30_n_0),
.O(sign00__0_carry__4_i_32_n_0));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
sign00__0_carry__4_i_33
(.I0(sign00__0_carry__2_i_37_n_0),
.I1(sign00__0_carry__3_i_48_n_0),
.I2(sign00__0_carry_i_38_n_0),
.I3(sign00__0_carry__3_i_52_n_0),
.I4(sign00__0_carry_i_41_n_0),
.I5(sign00__0_carry__4_i_38_n_0),
.O(sign00__0_carry__4_i_33_n_0));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
sign00__0_carry__4_i_34
(.I0(sign00__0_carry__0_i_38_n_0),
.I1(sign00__0_carry__1_i_47_n_0),
.I2(sign00__0_carry_i_38_n_0),
.I3(sign00__0_carry__1_i_44_n_0),
.I4(sign00__0_carry_i_41_n_0),
.I5(sign00__0_carry__2_i_40_n_0),
.O(sign00__0_carry__4_i_34_n_0));
LUT6 #(
.INIT(64'h0F004F4F0F004040))
sign00__0_carry__4_i_35
(.I0(sum4[0]),
.I1(sign00__0_carry__4_i_39_n_0),
.I2(sign00__0_carry_i_38_n_0),
.I3(sign00__0_carry__0_i_41_n_0),
.I4(sign00__0_carry_i_41_n_0),
.I5(sign00__0_carry__0_i_39_n_0),
.O(sign00__0_carry__4_i_35_n_0));
LUT6 #(
.INIT(64'h0000000D00000008))
sign00__0_carry__4_i_36
(.I0(sum4[0]),
.I1(small_mant[21]),
.I2(sign00__0_carry_i_69_n_0),
.I3(sign00__0_carry_i_59_n_0),
.I4(sign00__0_carry_i_58_n_0),
.I5(small_mant[22]),
.O(sign00__0_carry__4_i_36_n_0));
LUT6 #(
.INIT(64'h0000000D00000008))
sign00__0_carry__4_i_37
(.I0(sum4[0]),
.I1(small_mant[20]),
.I2(sign00__0_carry_i_69_n_0),
.I3(sign00__0_carry_i_59_n_0),
.I4(sign00__0_carry_i_58_n_0),
.I5(small_mant[21]),
.O(sign00__0_carry__4_i_37_n_0));
LUT6 #(
.INIT(64'h0000000D00000008))
sign00__0_carry__4_i_38
(.I0(sum4[0]),
.I1(small_mant[19]),
.I2(sign00__0_carry_i_69_n_0),
.I3(sign00__0_carry_i_59_n_0),
.I4(sign00__0_carry_i_58_n_0),
.I5(small_mant[20]),
.O(sign00__0_carry__4_i_38_n_0));
LUT6 #(
.INIT(64'h0101010000010000))
sign00__0_carry__4_i_39
(.I0(sign00__0_carry_i_69_n_0),
.I1(sign00__0_carry_i_59_n_0),
.I2(sign00__0_carry_i_58_n_0),
.I3(large_mant1_carry_n_0),
.I4(x[0]),
.I5(y[0]),
.O(sign00__0_carry__4_i_39_n_0));
LUT6 #(
.INIT(64'hAAAA202A5555DFD5))
sign00__0_carry__4_i_4
(.I0(sign00__0_carry__4_i_16_n_0),
.I1(sign00__0_carry__0_i_15_n_0),
.I2(sign00__0_carry_i_17_n_0),
.I3(sign00__0_carry__4_i_17_n_0),
.I4(sum3),
.I5(sign00__0_carry_i_5_n_0),
.O(sign00__0_carry__4_i_4_n_0));
LUT6 #(
.INIT(64'hAAA999A966655565))
sign00__0_carry__4_i_5
(.I0(sign00__0_carry_i_5_n_0),
.I1(sum3),
.I2(sign00__0_carry__4_i_11_n_0),
.I3(sign00__0_carry_i_17_n_0),
.I4(sign00__0_carry__4_i_10_n_0),
.I5(sign00__0_carry__4_i_9_n_0),
.O(sign00__0_carry__4_i_5_n_0));
LUT6 #(
.INIT(64'h7878788787788787))
sign00__0_carry__4_i_6
(.I0(sign00__0_carry__4_i_12_n_0),
.I1(sign00__0_carry__4_i_18_n_0),
.I2(sign00__0_carry_i_5_n_0),
.I3(large_mant1_carry_n_0),
.I4(y[22]),
.I5(x[22]),
.O(sign00__0_carry__4_i_6_n_0));
LUT6 #(
.INIT(64'h7878788787788787))
sign00__0_carry__4_i_7
(.I0(sign00__0_carry__4_i_14_n_0),
.I1(sign00__0_carry__4_i_19_n_0),
.I2(sign00__0_carry_i_5_n_0),
.I3(large_mant1_carry_n_0),
.I4(y[21]),
.I5(x[21]),
.O(sign00__0_carry__4_i_7_n_0));
LUT6 #(
.INIT(64'h7878788787788787))
sign00__0_carry__4_i_8
(.I0(sign00__0_carry__4_i_16_n_0),
.I1(sign00__0_carry__4_i_20_n_0),
.I2(sign00__0_carry_i_5_n_0),
.I3(large_mant1_carry_n_0),
.I4(y[20]),
.I5(x[20]),
.O(sign00__0_carry__4_i_8_n_0));
LUT6 #(
.INIT(64'h0000000000000002))
sign00__0_carry__4_i_9
(.I0(sign00__0_carry_i_25_n_0),
.I1(sum4[0]),
.I2(sum4[2]),
.I3(sum4[4]),
.I4(sum4[3]),
.I5(sum4[1]),
.O(sign00__0_carry__4_i_9_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 sign00__0_carry__5
(.CI(sign00__0_carry__4_n_0),
.CO(NLW_sign00__0_carry__5_CO_UNCONNECTED[3:0]),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({NLW_sign00__0_carry__5_O_UNCONNECTED[3:1],sel0[23]}),
.S({1'b0,1'b0,1'b0,sign00__0_carry__5_i_1_n_0}));
LUT5 #(
.INIT(32'h9A999AAA))
sign00__0_carry__5_i_1
(.I0(sign00__0_carry_i_5_n_0),
.I1(sum3),
.I2(sign00__0_carry__1_i_16_n_0),
.I3(sign00__0_carry_i_12_n_4),
.I4(sign00__0_carry__5_i_2_n_0),
.O(sign00__0_carry__5_i_1_n_0));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
sign00__0_carry__5_i_2
(.I0(sign00__0_carry__2_i_28_n_0),
.I1(sign00__0_carry__3_i_30_n_0),
.I2(sign00__0_carry_i_42_n_0),
.I3(sign00__0_carry__4_i_27_n_0),
.I4(sign00__0_carry_i_38_n_0),
.I5(sign00__0_carry__5_i_3_n_0),
.O(sign00__0_carry__5_i_2_n_0));
LUT5 #(
.INIT(32'hAFC00000))
sign00__0_carry__5_i_3
(.I0(small_mant[21]),
.I1(small_mant[22]),
.I2(sign00__0_carry_i_41_n_0),
.I3(sum4[0]),
.I4(sign00__0_carry_i_39_n_0),
.O(sign00__0_carry__5_i_3_n_0));
LUT3 #(
.INIT(8'hAC))
sign00__0_carry_i_1
(.I0(x[0]),
.I1(y[0]),
.I2(large_mant1_carry_n_0),
.O(A[0]));
LUT5 #(
.INIT(32'h47FFFFFF))
sign00__0_carry_i_10
(.I0(sign00__0_carry_i_23_n_0),
.I1(sum4[0]),
.I2(sign00__0_carry_i_24_n_0),
.I3(sign00__0_carry_i_25_n_0),
.I4(sum3),
.O(sign00__0_carry_i_10_n_0));
LUT1 #(
.INIT(2'h2))
sign00__0_carry_i_100
(.I0(sum3_carry__0_i_9_n_3),
.O(sign00__0_carry_i_100_n_0));
LUT1 #(
.INIT(2'h2))
sign00__0_carry_i_101
(.I0(sum3_carry__0_i_9_n_3),
.O(sign00__0_carry_i_101_n_0));
LUT1 #(
.INIT(2'h2))
sign00__0_carry_i_102
(.I0(sum3_carry__0_i_9_n_3),
.O(sign00__0_carry_i_102_n_0));
LUT1 #(
.INIT(2'h2))
sign00__0_carry_i_103
(.I0(sum3_carry__0_i_9_n_3),
.O(sign00__0_carry_i_103_n_0));
LUT1 #(
.INIT(2'h2))
sign00__0_carry_i_104
(.I0(sum3_carry__0_i_9_n_3),
.O(sign00__0_carry_i_104_n_0));
LUT1 #(
.INIT(2'h2))
sign00__0_carry_i_105
(.I0(sum3_carry__0_i_9_n_3),
.O(sign00__0_carry_i_105_n_0));
LUT6 #(
.INIT(64'h0000003050005030))
sign00__0_carry_i_11
(.I0(sum4[2]),
.I1(sign00__0_carry_i_12_n_6),
.I2(sign00__0_carry_i_26_n_0),
.I3(sum3),
.I4(sign00__0_carry_i_12_n_5),
.I5(sum4[3]),
.O(sign00__0_carry_i_11_n_0));
CARRY4 sign00__0_carry_i_12
(.CI(1'b0),
.CO({sign00__0_carry_i_12_n_0,sign00__0_carry_i_12_n_1,sign00__0_carry_i_12_n_2,sign00__0_carry_i_12_n_3}),
.CYINIT(p_0_in[0]),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({sign00__0_carry_i_12_n_4,sign00__0_carry_i_12_n_5,sign00__0_carry_i_12_n_6,sign00__0_carry_i_12_n_7}),
.S(p_0_in[4:1]));
LUT5 #(
.INIT(32'h47FFFFFF))
sign00__0_carry_i_13
(.I0(sign00__0_carry_i_24_n_0),
.I1(sum4[0]),
.I2(sign00__0_carry_i_32_n_0),
.I3(sign00__0_carry_i_25_n_0),
.I4(sum3),
.O(sign00__0_carry_i_13_n_0));
LUT6 #(
.INIT(64'h0000003050005030))
sign00__0_carry_i_14
(.I0(sum4[2]),
.I1(sign00__0_carry_i_12_n_6),
.I2(sign00__0_carry_i_33_n_0),
.I3(sum3),
.I4(sign00__0_carry_i_12_n_5),
.I5(sum4[3]),
.O(sign00__0_carry_i_14_n_0));
LUT5 #(
.INIT(32'h47FFFFFF))
sign00__0_carry_i_15
(.I0(sign00__0_carry_i_32_n_0),
.I1(sum4[0]),
.I2(sign00__0_carry_i_34_n_0),
.I3(sign00__0_carry_i_25_n_0),
.I4(sum3),
.O(sign00__0_carry_i_15_n_0));
LUT6 #(
.INIT(64'h0000003050005030))
sign00__0_carry_i_16
(.I0(sum4[2]),
.I1(sign00__0_carry_i_12_n_6),
.I2(sign00__0_carry_i_35_n_0),
.I3(sum3),
.I4(sign00__0_carry_i_12_n_5),
.I5(sum4[3]),
.O(sign00__0_carry_i_16_n_0));
LUT3 #(
.INIT(8'hAC))
sign00__0_carry_i_17
(.I0(sum4[4]),
.I1(sign00__0_carry_i_12_n_4),
.I2(sum3),
.O(sign00__0_carry_i_17_n_0));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT3 #(
.INIT(8'hAC))
sign00__0_carry_i_18
(.I0(x[3]),
.I1(y[3]),
.I2(large_mant1_carry_n_0),
.O(A[3]));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT3 #(
.INIT(8'hAC))
sign00__0_carry_i_19
(.I0(x[2]),
.I1(y[2]),
.I2(large_mant1_carry_n_0),
.O(A[2]));
LUT5 #(
.INIT(32'hAAA2555D))
sign00__0_carry_i_2
(.I0(sign00__0_carry_i_10_n_0),
.I1(sign00__0_carry_i_11_n_0),
.I2(sum3),
.I3(sign00__0_carry_i_12_n_4),
.I4(sign00__0_carry_i_5_n_0),
.O(sign00__0_carry_i_2_n_0));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT3 #(
.INIT(8'hAC))
sign00__0_carry_i_20
(.I0(x[1]),
.I1(y[1]),
.I2(large_mant1_carry_n_0),
.O(A[1]));
LUT6 #(
.INIT(64'hAAAAA8080000A808))
sign00__0_carry_i_21
(.I0(sign00__0_carry_i_25_n_0),
.I1(sign00__0_carry_i_36_n_0),
.I2(sum4[1]),
.I3(sign00__0_carry_i_37_n_0),
.I4(sum4[0]),
.I5(sign00__0_carry_i_34_n_0),
.O(sign00__0_carry_i_21_n_0));
LUT6 #(
.INIT(64'h0000000000001000))
sign00__0_carry_i_22
(.I0(sum4[0]),
.I1(sign00__0_carry_i_38_n_0),
.I2(sign00__0_carry_i_39_n_0),
.I3(small_mant[0]),
.I4(sign00__0_carry_i_41_n_0),
.I5(sign00__0_carry_i_42_n_0),
.O(sign00__0_carry_i_22_n_0));
LUT6 #(
.INIT(64'hB8B8B8B8FF33CC00))
sign00__0_carry_i_23
(.I0(sign00__0_carry_i_43_n_0),
.I1(sum4[2]),
.I2(sign00__0_carry_i_44_n_0),
.I3(sign00__0_carry_i_45_n_0),
.I4(sign00__0_carry_i_46_n_0),
.I5(sum4[1]),
.O(sign00__0_carry_i_23_n_0));
LUT5 #(
.INIT(32'hB8FFB800))
sign00__0_carry_i_24
(.I0(sign00__0_carry_i_47_n_0),
.I1(sum4[2]),
.I2(sign00__0_carry_i_48_n_0),
.I3(sum4[1]),
.I4(sign00__0_carry_i_49_n_0),
.O(sign00__0_carry_i_24_n_0));
LUT4 #(
.INIT(16'h0002))
sign00__0_carry_i_25
(.I0(sum3_carry__0_i_9_n_3),
.I1(sum4[6]),
.I2(sum4[5]),
.I3(sum4[7]),
.O(sign00__0_carry_i_25_n_0));
LUT6 #(
.INIT(64'hD080FFFFD0800000))
sign00__0_carry_i_26
(.I0(sum4[0]),
.I1(small_mant[0]),
.I2(sign00__0_carry_i_39_n_0),
.I3(small_mant[1]),
.I4(sign00__0_carry_i_41_n_0),
.I5(sign00__0_carry_i_51_n_0),
.O(sign00__0_carry_i_26_n_0));
LUT1 #(
.INIT(2'h1))
sign00__0_carry_i_27
(.I0(sum4[0]),
.O(p_0_in[0]));
LUT1 #(
.INIT(2'h1))
sign00__0_carry_i_28
(.I0(sum4[4]),
.O(p_0_in[4]));
LUT1 #(
.INIT(2'h1))
sign00__0_carry_i_29
(.I0(sum4[3]),
.O(p_0_in[3]));
LUT5 #(
.INIT(32'hAAA2555D))
sign00__0_carry_i_3
(.I0(sign00__0_carry_i_13_n_0),
.I1(sign00__0_carry_i_14_n_0),
.I2(sum3),
.I3(sign00__0_carry_i_12_n_4),
.I4(sign00__0_carry_i_5_n_0),
.O(sign00__0_carry_i_3_n_0));
LUT1 #(
.INIT(2'h1))
sign00__0_carry_i_30
(.I0(sum4[2]),
.O(p_0_in[2]));
LUT1 #(
.INIT(2'h1))
sign00__0_carry_i_31
(.I0(sum4[1]),
.O(p_0_in[1]));
LUT5 #(
.INIT(32'hB8FFB800))
sign00__0_carry_i_32
(.I0(sign00__0_carry_i_45_n_0),
.I1(sum4[2]),
.I2(sign00__0_carry_i_46_n_0),
.I3(sum4[1]),
.I4(sign00__0_carry_i_37_n_0),
.O(sign00__0_carry_i_32_n_0));
LUT6 #(
.INIT(64'h4F4500004A400000))
sign00__0_carry_i_33
(.I0(sum4[0]),
.I1(small_mant[0]),
.I2(sign00__0_carry_i_41_n_0),
.I3(small_mant[1]),
.I4(sign00__0_carry_i_39_n_0),
.I5(small_mant[2]),
.O(sign00__0_carry_i_33_n_0));
LUT5 #(
.INIT(32'hB8BBB888))
sign00__0_carry_i_34
(.I0(sign00__0_carry_i_49_n_0),
.I1(sum4[1]),
.I2(sign00__0_carry_i_48_n_0),
.I3(sum4[2]),
.I4(sign00__0_carry_i_53_n_0),
.O(sign00__0_carry_i_34_n_0));
LUT5 #(
.INIT(32'h0000C808))
sign00__0_carry_i_35
(.I0(small_mant[1]),
.I1(sign00__0_carry_i_39_n_0),
.I2(sum4[0]),
.I3(small_mant[0]),
.I4(sign00__0_carry_i_41_n_0),
.O(sign00__0_carry_i_35_n_0));
LUT5 #(
.INIT(32'hB8BBB888))
sign00__0_carry_i_36
(.I0(sign00__0_carry_i_46_n_0),
.I1(sum4[2]),
.I2(sign00__0_carry_i_54_n_0),
.I3(sum4[3]),
.I4(sign00__0_carry_i_55_n_0),
.O(sign00__0_carry_i_36_n_0));
LUT5 #(
.INIT(32'hB8BBB888))
sign00__0_carry_i_37
(.I0(sign00__0_carry_i_44_n_0),
.I1(sum4[2]),
.I2(sign00__0_carry_i_56_n_0),
.I3(sum4[3]),
.I4(sign00__0_carry_i_57_n_0),
.O(sign00__0_carry_i_37_n_0));
LUT3 #(
.INIT(8'hAC))
sign00__0_carry_i_38
(.I0(sum4[2]),
.I1(sign00__0_carry_i_12_n_6),
.I2(sum3),
.O(sign00__0_carry_i_38_n_0));
LUT6 #(
.INIT(64'h0000000000000001))
sign00__0_carry_i_39
(.I0(sign00__0_carry_i_58_n_0),
.I1(sign00__0_carry_i_59_n_0),
.I2(sign00__0_carry_i_60_n_0),
.I3(sign00__0_carry_i_61_n_0),
.I4(sign00__0_carry_i_62_n_0),
.I5(sign00__0_carry_i_63_n_0),
.O(sign00__0_carry_i_39_n_0));
LUT5 #(
.INIT(32'hAAA2555D))
sign00__0_carry_i_4
(.I0(sign00__0_carry_i_15_n_0),
.I1(sign00__0_carry_i_16_n_0),
.I2(sum3),
.I3(sign00__0_carry_i_12_n_4),
.I4(sign00__0_carry_i_5_n_0),
.O(sign00__0_carry_i_4_n_0));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT3 #(
.INIT(8'hAC))
sign00__0_carry_i_40
(.I0(y[0]),
.I1(x[0]),
.I2(large_mant1_carry_n_0),
.O(small_mant[0]));
LUT3 #(
.INIT(8'hAC))
sign00__0_carry_i_41
(.I0(sum4[1]),
.I1(sign00__0_carry_i_12_n_7),
.I2(sum3),
.O(sign00__0_carry_i_41_n_0));
LUT3 #(
.INIT(8'hAC))
sign00__0_carry_i_42
(.I0(sum4[3]),
.I1(sign00__0_carry_i_12_n_5),
.I2(sum3),
.O(sign00__0_carry_i_42_n_0));
LUT6 #(
.INIT(64'h00000000BBB88B88))
sign00__0_carry_i_43
(.I0(small_mant[18]),
.I1(sum4[3]),
.I2(large_mant1_carry_n_0),
.I3(x[10]),
.I4(y[10]),
.I5(sum4[4]),
.O(sign00__0_carry_i_43_n_0));
LUT6 #(
.INIT(64'h00E4FFFF00E40000))
sign00__0_carry_i_44
(.I0(large_mant1_carry_n_0),
.I1(x[14]),
.I2(y[14]),
.I3(sum4[4]),
.I4(sum4[3]),
.I5(sign00__0_carry_i_64_n_0),
.O(sign00__0_carry_i_44_n_0));
LUT6 #(
.INIT(64'h00000000BBB88B88))
sign00__0_carry_i_45
(.I0(small_mant[16]),
.I1(sum4[3]),
.I2(large_mant1_carry_n_0),
.I3(x[8]),
.I4(y[8]),
.I5(sum4[4]),
.O(sign00__0_carry_i_45_n_0));
LUT6 #(
.INIT(64'h00E4FFFF00E40000))
sign00__0_carry_i_46
(.I0(large_mant1_carry_n_0),
.I1(x[12]),
.I2(y[12]),
.I3(sum4[4]),
.I4(sum4[3]),
.I5(sign00__0_carry_i_65_n_0),
.O(sign00__0_carry_i_46_n_0));
LUT6 #(
.INIT(64'h00000000BBB88B88))
sign00__0_carry_i_47
(.I0(small_mant[17]),
.I1(sum4[3]),
.I2(large_mant1_carry_n_0),
.I3(x[9]),
.I4(y[9]),
.I5(sum4[4]),
.O(sign00__0_carry_i_47_n_0));
LUT6 #(
.INIT(64'h00E4FFFF00E40000))
sign00__0_carry_i_48
(.I0(large_mant1_carry_n_0),
.I1(x[13]),
.I2(y[13]),
.I3(sum4[4]),
.I4(sum4[3]),
.I5(sign00__0_carry_i_66_n_0),
.O(sign00__0_carry_i_48_n_0));
LUT5 #(
.INIT(32'hB8BBB888))
sign00__0_carry_i_49
(.I0(sign00__0_carry__0_i_34_n_0),
.I1(sum4[2]),
.I2(sign00__0_carry_i_67_n_0),
.I3(sum4[3]),
.I4(sign00__0_carry_i_68_n_0),
.O(sign00__0_carry_i_49_n_0));
LUT2 #(
.INIT(4'h6))
sign00__0_carry_i_5
(.I0(x[31]),
.I1(y[31]),
.O(sign00__0_carry_i_5_n_0));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT3 #(
.INIT(8'hAC))
sign00__0_carry_i_50
(.I0(y[1]),
.I1(x[1]),
.I2(large_mant1_carry_n_0),
.O(small_mant[1]));
LUT6 #(
.INIT(64'h0000000D00000008))
sign00__0_carry_i_51
(.I0(sum4[0]),
.I1(small_mant[2]),
.I2(sign00__0_carry_i_69_n_0),
.I3(sign00__0_carry_i_59_n_0),
.I4(sign00__0_carry_i_58_n_0),
.I5(small_mant[3]),
.O(sign00__0_carry_i_51_n_0));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT3 #(
.INIT(8'hAC))
sign00__0_carry_i_52
(.I0(y[2]),
.I1(x[2]),
.I2(large_mant1_carry_n_0),
.O(small_mant[2]));
LUT6 #(
.INIT(64'h00E4FFFF00E40000))
sign00__0_carry_i_53
(.I0(large_mant1_carry_n_0),
.I1(x[9]),
.I2(y[9]),
.I3(sum4[4]),
.I4(sum4[3]),
.I5(sign00__0_carry_i_70_n_0),
.O(sign00__0_carry_i_53_n_0));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT4 #(
.INIT(16'h00E4))
sign00__0_carry_i_54
(.I0(large_mant1_carry_n_0),
.I1(x[8]),
.I2(y[8]),
.I3(sum4[4]),
.O(sign00__0_carry_i_54_n_0));
LUT6 #(
.INIT(64'hAFA0AFA0CFCFC0C0))
sign00__0_carry_i_55
(.I0(y[16]),
.I1(x[16]),
.I2(sum4[4]),
.I3(y[0]),
.I4(x[0]),
.I5(large_mant1_carry_n_0),
.O(sign00__0_carry_i_55_n_0));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT4 #(
.INIT(16'h00E4))
sign00__0_carry_i_56
(.I0(large_mant1_carry_n_0),
.I1(x[10]),
.I2(y[10]),
.I3(sum4[4]),
.O(sign00__0_carry_i_56_n_0));
LUT6 #(
.INIT(64'hAFA0AFA0CFCFC0C0))
sign00__0_carry_i_57
(.I0(y[18]),
.I1(x[18]),
.I2(sum4[4]),
.I3(y[2]),
.I4(x[2]),
.I5(large_mant1_carry_n_0),
.O(sign00__0_carry_i_57_n_0));
LUT6 #(
.INIT(64'hFFFFFFFFFFFF32FE))
sign00__0_carry_i_58
(.I0(sign00__0_carry_i_71_n_7),
.I1(sum3),
.I2(sign00__0_carry_i_71_n_6),
.I3(sum3_carry__0_i_9_n_3),
.I4(sign00__0_carry_i_72_n_0),
.I5(sign00__0_carry_i_73_n_0),
.O(sign00__0_carry_i_58_n_0));
LUT5 #(
.INIT(32'hFFFACFCA))
sign00__0_carry_i_59
(.I0(sign00__0_carry_i_74_n_7),
.I1(sum4[5]),
.I2(sum3),
.I3(sign00__0_carry_i_74_n_6),
.I4(sum4[6]),
.O(sign00__0_carry_i_59_n_0));
LUT6 #(
.INIT(64'h555DAAA2AAA2555D))
sign00__0_carry_i_6
(.I0(sign00__0_carry_i_10_n_0),
.I1(sign00__0_carry_i_11_n_0),
.I2(sign00__0_carry_i_17_n_0),
.I3(sum3),
.I4(sign00__0_carry_i_5_n_0),
.I5(A[3]),
.O(sign00__0_carry_i_6_n_0));
LUT6 #(
.INIT(64'h0F0FFFFF0F0FFFEE))
sign00__0_carry_i_60
(.I0(sign00__0_carry_i_75_n_4),
.I1(sign00__0_carry_i_75_n_5),
.I2(sum3_carry__0_i_9_n_3),
.I3(sign00__0_carry_i_76_n_6),
.I4(sum3),
.I5(sign00__0_carry_i_76_n_7),
.O(sign00__0_carry_i_60_n_0));
LUT6 #(
.INIT(64'h0F0FFFFF0F0FFFEE))
sign00__0_carry_i_61
(.I0(sign00__0_carry_i_76_n_4),
.I1(sign00__0_carry_i_76_n_5),
.I2(sum3_carry__0_i_9_n_3),
.I3(sign00__0_carry_i_77_n_6),
.I4(sum3),
.I5(sign00__0_carry_i_77_n_7),
.O(sign00__0_carry_i_61_n_0));
LUT6 #(
.INIT(64'h0F0FFFFF0F0FFFEE))
sign00__0_carry_i_62
(.I0(sign00__0_carry_i_78_n_4),
.I1(sign00__0_carry_i_78_n_5),
.I2(sum3_carry__0_i_9_n_3),
.I3(sign00__0_carry_i_79_n_6),
.I4(sum3),
.I5(sign00__0_carry_i_79_n_7),
.O(sign00__0_carry_i_62_n_0));
LUT6 #(
.INIT(64'h0F0FFFFF0F0FFFEE))
sign00__0_carry_i_63
(.I0(sign00__0_carry_i_79_n_4),
.I1(sign00__0_carry_i_79_n_5),
.I2(sum3_carry__0_i_9_n_3),
.I3(sign00__0_carry_i_75_n_6),
.I4(sum3),
.I5(sign00__0_carry_i_75_n_7),
.O(sign00__0_carry_i_63_n_0));
LUT6 #(
.INIT(64'hAFA0AFA0CFCFC0C0))
sign00__0_carry_i_64
(.I0(y[22]),
.I1(x[22]),
.I2(sum4[4]),
.I3(y[6]),
.I4(x[6]),
.I5(large_mant1_carry_n_0),
.O(sign00__0_carry_i_64_n_0));
LUT6 #(
.INIT(64'hAFA0AFA0CFCFC0C0))
sign00__0_carry_i_65
(.I0(y[20]),
.I1(x[20]),
.I2(sum4[4]),
.I3(y[4]),
.I4(x[4]),
.I5(large_mant1_carry_n_0),
.O(sign00__0_carry_i_65_n_0));
LUT6 #(
.INIT(64'hAFA0AFA0CFCFC0C0))
sign00__0_carry_i_66
(.I0(y[21]),
.I1(x[21]),
.I2(sum4[4]),
.I3(y[5]),
.I4(x[5]),
.I5(large_mant1_carry_n_0),
.O(sign00__0_carry_i_66_n_0));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT4 #(
.INIT(16'h00E4))
sign00__0_carry_i_67
(.I0(large_mant1_carry_n_0),
.I1(x[11]),
.I2(y[11]),
.I3(sum4[4]),
.O(sign00__0_carry_i_67_n_0));
LUT6 #(
.INIT(64'hAFA0AFA0CFCFC0C0))
sign00__0_carry_i_68
(.I0(y[19]),
.I1(x[19]),
.I2(sum4[4]),
.I3(y[3]),
.I4(x[3]),
.I5(large_mant1_carry_n_0),
.O(sign00__0_carry_i_68_n_0));
LUT4 #(
.INIT(16'hFFFE))
sign00__0_carry_i_69
(.I0(sign00__0_carry_i_63_n_0),
.I1(sign00__0_carry_i_62_n_0),
.I2(sign00__0_carry_i_61_n_0),
.I3(sign00__0_carry_i_60_n_0),
.O(sign00__0_carry_i_69_n_0));
LUT6 #(
.INIT(64'h555DAAA2AAA2555D))
sign00__0_carry_i_7
(.I0(sign00__0_carry_i_13_n_0),
.I1(sign00__0_carry_i_14_n_0),
.I2(sign00__0_carry_i_17_n_0),
.I3(sum3),
.I4(sign00__0_carry_i_5_n_0),
.I5(A[2]),
.O(sign00__0_carry_i_7_n_0));
LUT6 #(
.INIT(64'hAFA0AFA0CFCFC0C0))
sign00__0_carry_i_70
(.I0(y[17]),
.I1(x[17]),
.I2(sum4[4]),
.I3(y[1]),
.I4(x[1]),
.I5(large_mant1_carry_n_0),
.O(sign00__0_carry_i_70_n_0));
CARRY4 sign00__0_carry_i_71
(.CI(sign00__0_carry_i_74_n_0),
.CO({sign00__0_carry_i_71_n_0,sign00__0_carry_i_71_n_1,sign00__0_carry_i_71_n_2,sign00__0_carry_i_71_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({sign00__0_carry_i_71_n_4,sign00__0_carry_i_71_n_5,sign00__0_carry_i_71_n_6,sign00__0_carry_i_71_n_7}),
.S({sign00__0_carry_i_80_n_0,sign00__0_carry_i_81_n_0,sign00__0_carry_i_82_n_0,sign00__0_carry_i_83_n_0}));
LUT5 #(
.INIT(32'hCFCAFFFA))
sign00__0_carry_i_72
(.I0(sign00__0_carry_i_74_n_5),
.I1(sum4[7]),
.I2(sum3),
.I3(sign00__0_carry_i_74_n_4),
.I4(sum3_carry__0_i_9_n_3),
.O(sign00__0_carry_i_72_n_0));
LUT6 #(
.INIT(64'h0F0FFFFF0F0FFFEE))
sign00__0_carry_i_73
(.I0(sign00__0_carry_i_71_n_4),
.I1(sign00__0_carry_i_71_n_5),
.I2(sum3_carry__0_i_9_n_3),
.I3(sign00__0_carry_i_78_n_6),
.I4(sum3),
.I5(sign00__0_carry_i_78_n_7),
.O(sign00__0_carry_i_73_n_0));
CARRY4 sign00__0_carry_i_74
(.CI(sign00__0_carry_i_12_n_0),
.CO({sign00__0_carry_i_74_n_0,sign00__0_carry_i_74_n_1,sign00__0_carry_i_74_n_2,sign00__0_carry_i_74_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({sign00__0_carry_i_74_n_4,sign00__0_carry_i_74_n_5,sign00__0_carry_i_74_n_6,sign00__0_carry_i_74_n_7}),
.S({sign00__0_carry_i_84_n_0,sign00__0_carry_i_85_n_0,sign00__0_carry_i_86_n_0,sign00__0_carry_i_87_n_0}));
CARRY4 sign00__0_carry_i_75
(.CI(sign00__0_carry_i_79_n_0),
.CO({sign00__0_carry_i_75_n_0,sign00__0_carry_i_75_n_1,sign00__0_carry_i_75_n_2,sign00__0_carry_i_75_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({sign00__0_carry_i_75_n_4,sign00__0_carry_i_75_n_5,sign00__0_carry_i_75_n_6,sign00__0_carry_i_75_n_7}),
.S({sign00__0_carry_i_88_n_0,sign00__0_carry_i_89_n_0,sign00__0_carry_i_90_n_0,sign00__0_carry_i_91_n_0}));
CARRY4 sign00__0_carry_i_76
(.CI(sign00__0_carry_i_75_n_0),
.CO({sign00__0_carry_i_76_n_0,sign00__0_carry_i_76_n_1,sign00__0_carry_i_76_n_2,sign00__0_carry_i_76_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({sign00__0_carry_i_76_n_4,sign00__0_carry_i_76_n_5,sign00__0_carry_i_76_n_6,sign00__0_carry_i_76_n_7}),
.S({sign00__0_carry_i_92_n_0,sign00__0_carry_i_93_n_0,sign00__0_carry_i_94_n_0,sign00__0_carry_i_95_n_0}));
CARRY4 sign00__0_carry_i_77
(.CI(sign00__0_carry_i_76_n_0),
.CO({NLW_sign00__0_carry_i_77_CO_UNCONNECTED[3:1],sign00__0_carry_i_77_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({NLW_sign00__0_carry_i_77_O_UNCONNECTED[3:2],sign00__0_carry_i_77_n_6,sign00__0_carry_i_77_n_7}),
.S({1'b0,1'b0,sign00__0_carry_i_96_n_0,sign00__0_carry_i_97_n_0}));
CARRY4 sign00__0_carry_i_78
(.CI(sign00__0_carry_i_71_n_0),
.CO({sign00__0_carry_i_78_n_0,sign00__0_carry_i_78_n_1,sign00__0_carry_i_78_n_2,sign00__0_carry_i_78_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({sign00__0_carry_i_78_n_4,sign00__0_carry_i_78_n_5,sign00__0_carry_i_78_n_6,sign00__0_carry_i_78_n_7}),
.S({sign00__0_carry_i_98_n_0,sign00__0_carry_i_99_n_0,sign00__0_carry_i_100_n_0,sign00__0_carry_i_101_n_0}));
CARRY4 sign00__0_carry_i_79
(.CI(sign00__0_carry_i_78_n_0),
.CO({sign00__0_carry_i_79_n_0,sign00__0_carry_i_79_n_1,sign00__0_carry_i_79_n_2,sign00__0_carry_i_79_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({sign00__0_carry_i_79_n_4,sign00__0_carry_i_79_n_5,sign00__0_carry_i_79_n_6,sign00__0_carry_i_79_n_7}),
.S({sign00__0_carry_i_102_n_0,sign00__0_carry_i_103_n_0,sign00__0_carry_i_104_n_0,sign00__0_carry_i_105_n_0}));
LUT6 #(
.INIT(64'h555DAAA2AAA2555D))
sign00__0_carry_i_8
(.I0(sign00__0_carry_i_15_n_0),
.I1(sign00__0_carry_i_16_n_0),
.I2(sign00__0_carry_i_17_n_0),
.I3(sum3),
.I4(sign00__0_carry_i_5_n_0),
.I5(A[1]),
.O(sign00__0_carry_i_8_n_0));
LUT1 #(
.INIT(2'h2))
sign00__0_carry_i_80
(.I0(sum3_carry__0_i_9_n_3),
.O(sign00__0_carry_i_80_n_0));
LUT1 #(
.INIT(2'h2))
sign00__0_carry_i_81
(.I0(sum3_carry__0_i_9_n_3),
.O(sign00__0_carry_i_81_n_0));
LUT1 #(
.INIT(2'h2))
sign00__0_carry_i_82
(.I0(sum3_carry__0_i_9_n_3),
.O(sign00__0_carry_i_82_n_0));
LUT1 #(
.INIT(2'h2))
sign00__0_carry_i_83
(.I0(sum3_carry__0_i_9_n_3),
.O(sign00__0_carry_i_83_n_0));
LUT1 #(
.INIT(2'h2))
sign00__0_carry_i_84
(.I0(sum3_carry__0_i_9_n_3),
.O(sign00__0_carry_i_84_n_0));
LUT1 #(
.INIT(2'h1))
sign00__0_carry_i_85
(.I0(sum4[7]),
.O(sign00__0_carry_i_85_n_0));
LUT1 #(
.INIT(2'h1))
sign00__0_carry_i_86
(.I0(sum4[6]),
.O(sign00__0_carry_i_86_n_0));
LUT1 #(
.INIT(2'h1))
sign00__0_carry_i_87
(.I0(sum4[5]),
.O(sign00__0_carry_i_87_n_0));
LUT1 #(
.INIT(2'h2))
sign00__0_carry_i_88
(.I0(sum3_carry__0_i_9_n_3),
.O(sign00__0_carry_i_88_n_0));
LUT1 #(
.INIT(2'h2))
sign00__0_carry_i_89
(.I0(sum3_carry__0_i_9_n_3),
.O(sign00__0_carry_i_89_n_0));
LUT4 #(
.INIT(16'hA0AC))
sign00__0_carry_i_9
(.I0(sign00__0_carry_i_21_n_0),
.I1(sign00__0_carry_i_22_n_0),
.I2(sum3),
.I3(sign00__0_carry_i_12_n_4),
.O(sign00__0_carry_i_9_n_0));
LUT1 #(
.INIT(2'h2))
sign00__0_carry_i_90
(.I0(sum3_carry__0_i_9_n_3),
.O(sign00__0_carry_i_90_n_0));
LUT1 #(
.INIT(2'h2))
sign00__0_carry_i_91
(.I0(sum3_carry__0_i_9_n_3),
.O(sign00__0_carry_i_91_n_0));
LUT1 #(
.INIT(2'h2))
sign00__0_carry_i_92
(.I0(sum3_carry__0_i_9_n_3),
.O(sign00__0_carry_i_92_n_0));
LUT1 #(
.INIT(2'h2))
sign00__0_carry_i_93
(.I0(sum3_carry__0_i_9_n_3),
.O(sign00__0_carry_i_93_n_0));
LUT1 #(
.INIT(2'h2))
sign00__0_carry_i_94
(.I0(sum3_carry__0_i_9_n_3),
.O(sign00__0_carry_i_94_n_0));
LUT1 #(
.INIT(2'h2))
sign00__0_carry_i_95
(.I0(sum3_carry__0_i_9_n_3),
.O(sign00__0_carry_i_95_n_0));
LUT1 #(
.INIT(2'h2))
sign00__0_carry_i_96
(.I0(sum3_carry__0_i_9_n_3),
.O(sign00__0_carry_i_96_n_0));
LUT1 #(
.INIT(2'h2))
sign00__0_carry_i_97
(.I0(sum3_carry__0_i_9_n_3),
.O(sign00__0_carry_i_97_n_0));
LUT1 #(
.INIT(2'h2))
sign00__0_carry_i_98
(.I0(sum3_carry__0_i_9_n_3),
.O(sign00__0_carry_i_98_n_0));
LUT1 #(
.INIT(2'h2))
sign00__0_carry_i_99
(.I0(sum3_carry__0_i_9_n_3),
.O(sign00__0_carry_i_99_n_0));
CARRY4 sum3_carry
(.CI(1'b0),
.CO({sum3_carry_n_0,sum3_carry_n_1,sum3_carry_n_2,sum3_carry_n_3}),
.CYINIT(1'b1),
.DI({sum3_carry_i_1_n_0,sum3_carry_i_2_n_0,sum3_carry_i_3_n_0,sum3_carry_i_4_n_0}),
.O(NLW_sum3_carry_O_UNCONNECTED[3:0]),
.S({sum3_carry_i_5_n_0,sum3_carry_i_6_n_0,sum3_carry_i_7_n_0,sum3_carry_i_8_n_0}));
CARRY4 sum3_carry__0
(.CI(sum3_carry_n_0),
.CO({sum3_carry__0_n_0,sum3_carry__0_n_1,sum3_carry__0_n_2,sum3_carry__0_n_3}),
.CYINIT(1'b0),
.DI({sum3_carry__0_i_1_n_0,sum3_carry__0_i_2_n_0,sum3_carry__0_i_3_n_0,sum3_carry__0_i_4_n_0}),
.O(NLW_sum3_carry__0_O_UNCONNECTED[3:0]),
.S({sum3_carry__0_i_5_n_0,sum3_carry__0_i_6_n_0,sum3_carry__0_i_7_n_0,sum3_carry__0_i_8_n_0}));
LUT1 #(
.INIT(2'h1))
sum3_carry__0_i_1
(.I0(sum3_carry__0_i_9_n_3),
.O(sum3_carry__0_i_1_n_0));
LUT1 #(
.INIT(2'h1))
sum3_carry__0_i_2
(.I0(sum3_carry__0_i_9_n_3),
.O(sum3_carry__0_i_2_n_0));
LUT1 #(
.INIT(2'h1))
sum3_carry__0_i_3
(.I0(sum3_carry__0_i_9_n_3),
.O(sum3_carry__0_i_3_n_0));
LUT1 #(
.INIT(2'h1))
sum3_carry__0_i_4
(.I0(sum3_carry__0_i_9_n_3),
.O(sum3_carry__0_i_4_n_0));
LUT1 #(
.INIT(2'h2))
sum3_carry__0_i_5
(.I0(sum3_carry__0_i_9_n_3),
.O(sum3_carry__0_i_5_n_0));
LUT1 #(
.INIT(2'h2))
sum3_carry__0_i_6
(.I0(sum3_carry__0_i_9_n_3),
.O(sum3_carry__0_i_6_n_0));
LUT1 #(
.INIT(2'h2))
sum3_carry__0_i_7
(.I0(sum3_carry__0_i_9_n_3),
.O(sum3_carry__0_i_7_n_0));
LUT1 #(
.INIT(2'h2))
sum3_carry__0_i_8
(.I0(sum3_carry__0_i_9_n_3),
.O(sum3_carry__0_i_8_n_0));
CARRY4 sum3_carry__0_i_9
(.CI(sum4_carry__0_n_0),
.CO({NLW_sum3_carry__0_i_9_CO_UNCONNECTED[3:1],sum3_carry__0_i_9_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_sum3_carry__0_i_9_O_UNCONNECTED[3:0]),
.S({1'b0,1'b0,1'b0,1'b1}));
CARRY4 sum3_carry__1
(.CI(sum3_carry__0_n_0),
.CO({sum3_carry__1_n_0,sum3_carry__1_n_1,sum3_carry__1_n_2,sum3_carry__1_n_3}),
.CYINIT(1'b0),
.DI({sum3_carry__1_i_1_n_0,sum3_carry__1_i_2_n_0,sum3_carry__1_i_3_n_0,sum3_carry__1_i_4_n_0}),
.O(NLW_sum3_carry__1_O_UNCONNECTED[3:0]),
.S({sum3_carry__1_i_5_n_0,sum3_carry__1_i_6_n_0,sum3_carry__1_i_7_n_0,sum3_carry__1_i_8_n_0}));
LUT1 #(
.INIT(2'h1))
sum3_carry__1_i_1
(.I0(sum3_carry__0_i_9_n_3),
.O(sum3_carry__1_i_1_n_0));
LUT1 #(
.INIT(2'h1))
sum3_carry__1_i_2
(.I0(sum3_carry__0_i_9_n_3),
.O(sum3_carry__1_i_2_n_0));
LUT1 #(
.INIT(2'h1))
sum3_carry__1_i_3
(.I0(sum3_carry__0_i_9_n_3),
.O(sum3_carry__1_i_3_n_0));
LUT1 #(
.INIT(2'h1))
sum3_carry__1_i_4
(.I0(sum3_carry__0_i_9_n_3),
.O(sum3_carry__1_i_4_n_0));
LUT1 #(
.INIT(2'h2))
sum3_carry__1_i_5
(.I0(sum3_carry__0_i_9_n_3),
.O(sum3_carry__1_i_5_n_0));
LUT1 #(
.INIT(2'h2))
sum3_carry__1_i_6
(.I0(sum3_carry__0_i_9_n_3),
.O(sum3_carry__1_i_6_n_0));
LUT1 #(
.INIT(2'h2))
sum3_carry__1_i_7
(.I0(sum3_carry__0_i_9_n_3),
.O(sum3_carry__1_i_7_n_0));
LUT1 #(
.INIT(2'h2))
sum3_carry__1_i_8
(.I0(sum3_carry__0_i_9_n_3),
.O(sum3_carry__1_i_8_n_0));
CARRY4 sum3_carry__2
(.CI(sum3_carry__1_n_0),
.CO({sum3,sum3_carry__2_n_1,sum3_carry__2_n_2,sum3_carry__2_n_3}),
.CYINIT(1'b0),
.DI({1'b0,sum4[31],sum3_carry__2_i_2_n_0,sum3_carry__2_i_3_n_0}),
.O(NLW_sum3_carry__2_O_UNCONNECTED[3:0]),
.S({sum3_carry__2_i_4_n_0,sum3_carry__2_i_5_n_0,sum3_carry__2_i_6_n_0,sum3_carry__2_i_7_n_0}));
LUT1 #(
.INIT(2'h1))
sum3_carry__2_i_1
(.I0(sum3_carry__0_i_9_n_3),
.O(sum4[31]));
LUT1 #(
.INIT(2'h1))
sum3_carry__2_i_2
(.I0(sum3_carry__0_i_9_n_3),
.O(sum3_carry__2_i_2_n_0));
LUT1 #(
.INIT(2'h1))
sum3_carry__2_i_3
(.I0(sum3_carry__0_i_9_n_3),
.O(sum3_carry__2_i_3_n_0));
LUT1 #(
.INIT(2'h2))
sum3_carry__2_i_4
(.I0(sum3_carry__0_i_9_n_3),
.O(sum3_carry__2_i_4_n_0));
LUT1 #(
.INIT(2'h2))
sum3_carry__2_i_5
(.I0(sum3_carry__0_i_9_n_3),
.O(sum3_carry__2_i_5_n_0));
LUT1 #(
.INIT(2'h2))
sum3_carry__2_i_6
(.I0(sum3_carry__0_i_9_n_3),
.O(sum3_carry__2_i_6_n_0));
LUT1 #(
.INIT(2'h2))
sum3_carry__2_i_7
(.I0(sum3_carry__0_i_9_n_3),
.O(sum3_carry__2_i_7_n_0));
LUT2 #(
.INIT(4'hE))
sum3_carry_i_1
(.I0(sum4[6]),
.I1(sum4[7]),
.O(sum3_carry_i_1_n_0));
LUT2 #(
.INIT(4'hE))
sum3_carry_i_2
(.I0(sum4[4]),
.I1(sum4[5]),
.O(sum3_carry_i_2_n_0));
LUT2 #(
.INIT(4'hE))
sum3_carry_i_3
(.I0(sum4[2]),
.I1(sum4[3]),
.O(sum3_carry_i_3_n_0));
LUT2 #(
.INIT(4'hE))
sum3_carry_i_4
(.I0(sum4[0]),
.I1(sum4[1]),
.O(sum3_carry_i_4_n_0));
LUT2 #(
.INIT(4'h1))
sum3_carry_i_5
(.I0(sum4[6]),
.I1(sum4[7]),
.O(sum3_carry_i_5_n_0));
LUT2 #(
.INIT(4'h1))
sum3_carry_i_6
(.I0(sum4[4]),
.I1(sum4[5]),
.O(sum3_carry_i_6_n_0));
LUT2 #(
.INIT(4'h1))
sum3_carry_i_7
(.I0(sum4[2]),
.I1(sum4[3]),
.O(sum3_carry_i_7_n_0));
LUT2 #(
.INIT(4'h1))
sum3_carry_i_8
(.I0(sum4[0]),
.I1(sum4[1]),
.O(sum3_carry_i_8_n_0));
CARRY4 sum4_carry
(.CI(1'b0),
.CO({sum4_carry_n_0,sum4_carry_n_1,sum4_carry_n_2,sum4_carry_n_3}),
.CYINIT(1'b1),
.DI({sum4_carry_i_1_n_0,sum4_carry_i_2_n_0,sum4_carry_i_3_n_0,sum4_carry_i_4_n_0}),
.O(sum4[3:0]),
.S({sum4_carry_i_5_n_0,sum4_carry_i_6_n_0,sum4_carry_i_7_n_0,sum4_carry_i_8_n_0}));
CARRY4 sum4_carry__0
(.CI(sum4_carry_n_0),
.CO({sum4_carry__0_n_0,sum4_carry__0_n_1,sum4_carry__0_n_2,sum4_carry__0_n_3}),
.CYINIT(1'b0),
.DI({large_exp[7],sum4_carry__0_i_2_n_0,sum4_carry__0_i_3_n_0,sum4_carry__0_i_4_n_0}),
.O(sum4[7:4]),
.S({sum4_carry__0_i_5_n_0,sum4_carry__0_i_6_n_0,sum4_carry__0_i_7_n_0,sum4_carry__0_i_8_n_0}));
LUT3 #(
.INIT(8'hAC))
sum4_carry__0_i_1
(.I0(x[30]),
.I1(y[30]),
.I2(large_mant1_carry_n_0),
.O(large_exp[7]));
LUT3 #(
.INIT(8'hAC))
sum4_carry__0_i_2
(.I0(x[29]),
.I1(y[29]),
.I2(large_mant1_carry_n_0),
.O(sum4_carry__0_i_2_n_0));
LUT3 #(
.INIT(8'hAC))
sum4_carry__0_i_3
(.I0(x[28]),
.I1(y[28]),
.I2(large_mant1_carry_n_0),
.O(sum4_carry__0_i_3_n_0));
LUT3 #(
.INIT(8'hAC))
sum4_carry__0_i_4
(.I0(x[27]),
.I1(y[27]),
.I2(large_mant1_carry_n_0),
.O(sum4_carry__0_i_4_n_0));
LUT2 #(
.INIT(4'h9))
sum4_carry__0_i_5
(.I0(x[30]),
.I1(y[30]),
.O(sum4_carry__0_i_5_n_0));
LUT2 #(
.INIT(4'h9))
sum4_carry__0_i_6
(.I0(x[29]),
.I1(y[29]),
.O(sum4_carry__0_i_6_n_0));
LUT2 #(
.INIT(4'h9))
sum4_carry__0_i_7
(.I0(x[28]),
.I1(y[28]),
.O(sum4_carry__0_i_7_n_0));
LUT2 #(
.INIT(4'h9))
sum4_carry__0_i_8
(.I0(x[27]),
.I1(y[27]),
.O(sum4_carry__0_i_8_n_0));
LUT3 #(
.INIT(8'hAC))
sum4_carry_i_1
(.I0(x[26]),
.I1(y[26]),
.I2(large_mant1_carry_n_0),
.O(sum4_carry_i_1_n_0));
LUT3 #(
.INIT(8'hAC))
sum4_carry_i_2
(.I0(x[25]),
.I1(y[25]),
.I2(large_mant1_carry_n_0),
.O(sum4_carry_i_2_n_0));
LUT3 #(
.INIT(8'hAC))
sum4_carry_i_3
(.I0(x[24]),
.I1(y[24]),
.I2(large_mant1_carry_n_0),
.O(sum4_carry_i_3_n_0));
LUT3 #(
.INIT(8'hAC))
sum4_carry_i_4
(.I0(x[23]),
.I1(y[23]),
.I2(large_mant1_carry_n_0),
.O(sum4_carry_i_4_n_0));
LUT2 #(
.INIT(4'h9))
sum4_carry_i_5
(.I0(x[26]),
.I1(y[26]),
.O(sum4_carry_i_5_n_0));
LUT2 #(
.INIT(4'h9))
sum4_carry_i_6
(.I0(x[25]),
.I1(y[25]),
.O(sum4_carry_i_6_n_0));
LUT2 #(
.INIT(4'h9))
sum4_carry_i_7
(.I0(x[24]),
.I1(y[24]),
.O(sum4_carry_i_7_n_0));
LUT2 #(
.INIT(4'h9))
sum4_carry_i_8
(.I0(x[23]),
.I1(y[23]),
.O(sum4_carry_i_8_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 z0_carry
(.CI(1'b0),
.CO({z0_carry_n_0,z0_carry_n_1,z0_carry_n_2,z0_carry_n_3}),
.CYINIT(1'b1),
.DI(large_exp[3:0]),
.O(z[26:23]),
.S({z0_carry_i_5__0_n_0,z0_carry_i_6_n_0,z0_carry_i_7_n_0,z0_carry_i_8_n_0}));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 z0_carry__0
(.CI(z0_carry_n_0),
.CO({NLW_z0_carry__0_CO_UNCONNECTED[3],z0_carry__0_n_1,z0_carry__0_n_2,z0_carry__0_n_3}),
.CYINIT(1'b0),
.DI({1'b0,large_exp[6:4]}),
.O(z[30:27]),
.S({z0_carry_i_4_n_0,z0_carry_i_5_n_0,z0_carry_i_6__0_n_0,z0_carry_i_7__0_n_0}));
LUT3 #(
.INIT(8'hAC))
z0_carry_i_1
(.I0(x[26]),
.I1(y[26]),
.I2(large_mant1_carry_n_0),
.O(large_exp[3]));
LUT6 #(
.INIT(64'h5554444400000000))
z0_carry_i_10
(.I0(sel0[23]),
.I1(_carry_i_5_n_0),
.I2(sel0[14]),
.I3(_carry_i_6_n_0),
.I4(_carry_i_7_n_0),
.I5(_carry_i_8_n_0),
.O(z0_carry_i_10_n_0));
LUT6 #(
.INIT(64'hA8A8A8A8A8A8A800))
z0_carry_i_11
(.I0(_carry_i_9_n_0),
.I1(_carry_i_10_n_0),
.I2(_carry_i_11_n_0),
.I3(_carry_i_12_n_0),
.I4(sel0[1]),
.I5(_carry_i_13_n_0),
.O(z0_carry_i_11_n_0));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT4 #(
.INIT(16'hFFFE))
z0_carry_i_12
(.I0(sel0[13]),
.I1(sel0[23]),
.I2(sel0[11]),
.I3(sel0[12]),
.O(z0_carry_i_12_n_0));
LUT3 #(
.INIT(8'hAC))
z0_carry_i_1__0
(.I0(x[29]),
.I1(y[29]),
.I2(large_mant1_carry_n_0),
.O(large_exp[6]));
LUT3 #(
.INIT(8'hAC))
z0_carry_i_2
(.I0(x[25]),
.I1(y[25]),
.I2(large_mant1_carry_n_0),
.O(large_exp[2]));
LUT3 #(
.INIT(8'hAC))
z0_carry_i_2__0
(.I0(x[28]),
.I1(y[28]),
.I2(large_mant1_carry_n_0),
.O(large_exp[5]));
LUT3 #(
.INIT(8'hAC))
z0_carry_i_3
(.I0(x[24]),
.I1(y[24]),
.I2(large_mant1_carry_n_0),
.O(large_exp[1]));
LUT3 #(
.INIT(8'hAC))
z0_carry_i_3__0
(.I0(x[27]),
.I1(y[27]),
.I2(large_mant1_carry_n_0),
.O(large_exp[4]));
LUT4 #(
.INIT(16'h1BE4))
z0_carry_i_4
(.I0(large_mant1_carry_n_0),
.I1(y[30]),
.I2(x[30]),
.I3(\z[18]_INST_0_i_1_n_0 ),
.O(z0_carry_i_4_n_0));
LUT3 #(
.INIT(8'hAC))
z0_carry_i_4__0
(.I0(x[23]),
.I1(y[23]),
.I2(large_mant1_carry_n_0),
.O(large_exp[0]));
LUT4 #(
.INIT(16'h1BE4))
z0_carry_i_5
(.I0(large_mant1_carry_n_0),
.I1(y[29]),
.I2(x[29]),
.I3(\z[18]_INST_0_i_1_n_0 ),
.O(z0_carry_i_5_n_0));
LUT4 #(
.INIT(16'hE41B))
z0_carry_i_5__0
(.I0(large_mant1_carry_n_0),
.I1(y[26]),
.I2(x[26]),
.I3(z0_carry_i_9_n_0),
.O(z0_carry_i_5__0_n_0));
LUT4 #(
.INIT(16'h1BE4))
z0_carry_i_6
(.I0(large_mant1_carry_n_0),
.I1(y[25]),
.I2(x[25]),
.I3(z0_carry_i_10_n_0),
.O(z0_carry_i_6_n_0));
LUT4 #(
.INIT(16'h1BE4))
z0_carry_i_6__0
(.I0(large_mant1_carry_n_0),
.I1(y[28]),
.I2(x[28]),
.I3(\z[18]_INST_0_i_1_n_0 ),
.O(z0_carry_i_6__0_n_0));
LUT4 #(
.INIT(16'h1BE4))
z0_carry_i_7
(.I0(large_mant1_carry_n_0),
.I1(y[24]),
.I2(x[24]),
.I3(z0_carry_i_11_n_0),
.O(z0_carry_i_7_n_0));
LUT4 #(
.INIT(16'h1BE4))
z0_carry_i_7__0
(.I0(large_mant1_carry_n_0),
.I1(y[27]),
.I2(x[27]),
.I3(z0_carry_i_8__0_n_0),
.O(z0_carry_i_7__0_n_0));
LUT4 #(
.INIT(16'h1BE4))
z0_carry_i_8
(.I0(large_mant1_carry_n_0),
.I1(y[23]),
.I2(x[23]),
.I3(\z[22]_INST_0_i_1_n_0 ),
.O(z0_carry_i_8_n_0));
LUT2 #(
.INIT(4'h6))
z0_carry_i_8__0
(.I0(z0_carry_i_9_n_0),
.I1(\z[31]_INST_0_i_2_n_0 ),
.O(z0_carry_i_8__0_n_0));
LUT6 #(
.INIT(64'hF1F1F1F1F1F1F100))
z0_carry_i_9
(.I0(_carry_i_5_n_0),
.I1(\z[31]_INST_0_i_7_n_0 ),
.I2(sel0[23]),
.I3(z0_carry_i_12_n_0),
.I4(\z[31]_INST_0_i_3_n_0 ),
.I5(sel0[14]),
.O(z0_carry_i_9_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 z2_carry
(.CI(1'b0),
.CO({z2_carry_n_0,z2_carry_n_1,z2_carry_n_2,z2_carry_n_3}),
.CYINIT(1'b1),
.DI({z2_carry_i_1_n_0,z2_carry_i_2_n_0,z2_carry_i_3_n_0,z2_carry_i_4_n_0}),
.O(NLW_z2_carry_O_UNCONNECTED[3:0]),
.S({z2_carry_i_5_n_0,z2_carry_i_6_n_0,z2_carry_i_7_n_0,z2_carry_i_8_n_0}));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 z2_carry__0
(.CI(z2_carry_n_0),
.CO({z2_carry__0_n_0,z2_carry__0_n_1,z2_carry__0_n_2,z2_carry__0_n_3}),
.CYINIT(1'b0),
.DI({z2_carry__0_i_1_n_0,z2_carry__0_i_2_n_0,z2_carry__0_i_3_n_0,z2_carry__0_i_4_n_0}),
.O(NLW_z2_carry__0_O_UNCONNECTED[3:0]),
.S({z2_carry__0_i_5_n_0,z2_carry__0_i_6_n_0,z2_carry__0_i_7_n_0,z2_carry__0_i_8_n_0}));
LUT1 #(
.INIT(2'h1))
z2_carry__0_i_1
(.I0(\z[18]_INST_0_i_1_n_0 ),
.O(z2_carry__0_i_1_n_0));
LUT1 #(
.INIT(2'h1))
z2_carry__0_i_2
(.I0(\z[18]_INST_0_i_1_n_0 ),
.O(z2_carry__0_i_2_n_0));
LUT1 #(
.INIT(2'h1))
z2_carry__0_i_3
(.I0(\z[18]_INST_0_i_1_n_0 ),
.O(z2_carry__0_i_3_n_0));
LUT1 #(
.INIT(2'h1))
z2_carry__0_i_4
(.I0(\z[18]_INST_0_i_1_n_0 ),
.O(z2_carry__0_i_4_n_0));
LUT2 #(
.INIT(4'h7))
z2_carry__0_i_5
(.I0(z0_carry_i_9_n_0),
.I1(\z[31]_INST_0_i_2_n_0 ),
.O(z2_carry__0_i_5_n_0));
LUT2 #(
.INIT(4'h7))
z2_carry__0_i_6
(.I0(z0_carry_i_9_n_0),
.I1(\z[31]_INST_0_i_2_n_0 ),
.O(z2_carry__0_i_6_n_0));
LUT2 #(
.INIT(4'h7))
z2_carry__0_i_7
(.I0(z0_carry_i_9_n_0),
.I1(\z[31]_INST_0_i_2_n_0 ),
.O(z2_carry__0_i_7_n_0));
LUT2 #(
.INIT(4'h7))
z2_carry__0_i_8
(.I0(z0_carry_i_9_n_0),
.I1(\z[31]_INST_0_i_2_n_0 ),
.O(z2_carry__0_i_8_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 z2_carry__1
(.CI(z2_carry__0_n_0),
.CO({z2_carry__1_n_0,z2_carry__1_n_1,z2_carry__1_n_2,z2_carry__1_n_3}),
.CYINIT(1'b0),
.DI({z2_carry__1_i_1_n_0,z2_carry__1_i_2_n_0,z2_carry__1_i_3_n_0,z2_carry__1_i_4_n_0}),
.O(NLW_z2_carry__1_O_UNCONNECTED[3:0]),
.S({z2_carry__1_i_5_n_0,z2_carry__1_i_6_n_0,z2_carry__1_i_7_n_0,z2_carry__1_i_8_n_0}));
LUT1 #(
.INIT(2'h1))
z2_carry__1_i_1
(.I0(\z[18]_INST_0_i_1_n_0 ),
.O(z2_carry__1_i_1_n_0));
LUT1 #(
.INIT(2'h1))
z2_carry__1_i_2
(.I0(\z[18]_INST_0_i_1_n_0 ),
.O(z2_carry__1_i_2_n_0));
LUT1 #(
.INIT(2'h1))
z2_carry__1_i_3
(.I0(\z[18]_INST_0_i_1_n_0 ),
.O(z2_carry__1_i_3_n_0));
LUT1 #(
.INIT(2'h1))
z2_carry__1_i_4
(.I0(\z[18]_INST_0_i_1_n_0 ),
.O(z2_carry__1_i_4_n_0));
LUT2 #(
.INIT(4'h7))
z2_carry__1_i_5
(.I0(z0_carry_i_9_n_0),
.I1(\z[31]_INST_0_i_2_n_0 ),
.O(z2_carry__1_i_5_n_0));
LUT2 #(
.INIT(4'h7))
z2_carry__1_i_6
(.I0(z0_carry_i_9_n_0),
.I1(\z[31]_INST_0_i_2_n_0 ),
.O(z2_carry__1_i_6_n_0));
LUT2 #(
.INIT(4'h7))
z2_carry__1_i_7
(.I0(z0_carry_i_9_n_0),
.I1(\z[31]_INST_0_i_2_n_0 ),
.O(z2_carry__1_i_7_n_0));
LUT2 #(
.INIT(4'h7))
z2_carry__1_i_8
(.I0(z0_carry_i_9_n_0),
.I1(\z[31]_INST_0_i_2_n_0 ),
.O(z2_carry__1_i_8_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 z2_carry__2
(.CI(z2_carry__1_n_0),
.CO({z2,z2_carry__2_n_1,z2_carry__2_n_2,z2_carry__2_n_3}),
.CYINIT(1'b0),
.DI({1'b0,z1,z2_carry__2_i_2_n_0,z2_carry__2_i_3_n_0}),
.O(NLW_z2_carry__2_O_UNCONNECTED[3:0]),
.S({z2_carry__2_i_4_n_0,z2_carry__2_i_5_n_0,z2_carry__2_i_6_n_0,z2_carry__2_i_7_n_0}));
LUT1 #(
.INIT(2'h1))
z2_carry__2_i_1
(.I0(\z[18]_INST_0_i_1_n_0 ),
.O(z1));
LUT1 #(
.INIT(2'h1))
z2_carry__2_i_2
(.I0(\z[18]_INST_0_i_1_n_0 ),
.O(z2_carry__2_i_2_n_0));
LUT1 #(
.INIT(2'h1))
z2_carry__2_i_3
(.I0(\z[18]_INST_0_i_1_n_0 ),
.O(z2_carry__2_i_3_n_0));
LUT2 #(
.INIT(4'h7))
z2_carry__2_i_4
(.I0(z0_carry_i_9_n_0),
.I1(\z[31]_INST_0_i_2_n_0 ),
.O(z2_carry__2_i_4_n_0));
LUT2 #(
.INIT(4'h7))
z2_carry__2_i_5
(.I0(z0_carry_i_9_n_0),
.I1(\z[31]_INST_0_i_2_n_0 ),
.O(z2_carry__2_i_5_n_0));
LUT2 #(
.INIT(4'h7))
z2_carry__2_i_6
(.I0(z0_carry_i_9_n_0),
.I1(\z[31]_INST_0_i_2_n_0 ),
.O(z2_carry__2_i_6_n_0));
LUT2 #(
.INIT(4'h7))
z2_carry__2_i_7
(.I0(z0_carry_i_9_n_0),
.I1(\z[31]_INST_0_i_2_n_0 ),
.O(z2_carry__2_i_7_n_0));
LUT1 #(
.INIT(2'h1))
z2_carry_i_1
(.I0(\z[18]_INST_0_i_1_n_0 ),
.O(z2_carry_i_1_n_0));
LUT2 #(
.INIT(4'h7))
z2_carry_i_2
(.I0(z0_carry_i_8__0_n_0),
.I1(\z[18]_INST_0_i_1_n_0 ),
.O(z2_carry_i_2_n_0));
LUT2 #(
.INIT(4'hD))
z2_carry_i_3
(.I0(z0_carry_i_10_n_0),
.I1(z0_carry_i_9_n_0),
.O(z2_carry_i_3_n_0));
LUT2 #(
.INIT(4'h7))
z2_carry_i_4
(.I0(\z[22]_INST_0_i_1_n_0 ),
.I1(z0_carry_i_11_n_0),
.O(z2_carry_i_4_n_0));
LUT2 #(
.INIT(4'h7))
z2_carry_i_5
(.I0(z0_carry_i_9_n_0),
.I1(\z[31]_INST_0_i_2_n_0 ),
.O(z2_carry_i_5_n_0));
LUT2 #(
.INIT(4'h8))
z2_carry_i_6
(.I0(z0_carry_i_8__0_n_0),
.I1(\z[18]_INST_0_i_1_n_0 ),
.O(z2_carry_i_6_n_0));
LUT2 #(
.INIT(4'h2))
z2_carry_i_7
(.I0(z0_carry_i_10_n_0),
.I1(z0_carry_i_9_n_0),
.O(z2_carry_i_7_n_0));
LUT2 #(
.INIT(4'h8))
z2_carry_i_8
(.I0(\z[22]_INST_0_i_1_n_0 ),
.I1(z0_carry_i_11_n_0),
.O(z2_carry_i_8_n_0));
LUT6 #(
.INIT(64'h33333333F373B333))
\z[0]_INST_0
(.I0(\z[22]_INST_0_i_1_n_0 ),
.I1(\z[0]_INST_0_i_1_n_0 ),
.I2(\z[22]_INST_0_i_3_n_0 ),
.I3(\z[0]_INST_0_i_2_n_0 ),
.I4(\z[1]_INST_0_i_2_n_0 ),
.I5(z2),
.O(z[0]));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT4 #(
.INIT(16'h7FFF))
\z[0]_INST_0_i_1
(.I0(\z[1]_INST_0_i_3_n_0 ),
.I1(\z[22]_INST_0_i_1_n_0 ),
.I2(\z[18]_INST_0_i_1_n_0 ),
.I3(z2),
.O(\z[0]_INST_0_i_1_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\z[0]_INST_0_i_2
(.I0(\z[6]_INST_0_i_5_n_0 ),
.I1(\z[2]_INST_0_i_4_n_0 ),
.I2(\z[22]_INST_0_i_18_n_0 ),
.I3(\z[4]_INST_0_i_5_n_0 ),
.I4(\z[22]_INST_0_i_21_n_0 ),
.I5(\z[0]_INST_0_i_3_n_0 ),
.O(\z[0]_INST_0_i_2_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\z[0]_INST_0_i_3
(.I0(sel0[23]),
.I1(sel0[7]),
.I2(\z[22]_INST_0_i_19_n_0 ),
.I3(sel0[15]),
.I4(\z[22]_INST_0_i_20_n_0 ),
.I5(sign00__0_carry_n_7),
.O(\z[0]_INST_0_i_3_n_0 ));
LUT6 #(
.INIT(64'hCCCCCCCCF050A000))
\z[10]_INST_0
(.I0(\z[22]_INST_0_i_1_n_0 ),
.I1(z10_in[10]),
.I2(\z[22]_INST_0_i_3_n_0 ),
.I3(\z[10]_INST_0_i_2_n_0 ),
.I4(\z[11]_INST_0_i_2_n_0 ),
.I5(z2),
.O(z[10]));
LUT6 #(
.INIT(64'hA8A8A8080808A808))
\z[10]_INST_0_i_1
(.I0(\z[18]_INST_0_i_1_n_0 ),
.I1(\z[10]_INST_0_i_3_n_0 ),
.I2(\z[22]_INST_0_i_1_n_0 ),
.I3(\z[10]_INST_0_i_4_n_0 ),
.I4(z0_carry_i_11_n_0),
.I5(\z[10]_INST_0_i_5_n_0 ),
.O(z10_in[10]));
(* SOFT_HLUTNM = "soft_lutpair46" *)
LUT3 #(
.INIT(8'h08))
\z[10]_INST_0_i_10
(.I0(\z[31]_INST_0_i_2_n_0 ),
.I1(sel0[2]),
.I2(z0_carry_i_9_n_0),
.O(\z[10]_INST_0_i_10_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\z[10]_INST_0_i_2
(.I0(\z[12]_INST_0_i_4_n_0 ),
.I1(\z[12]_INST_0_i_5_n_0 ),
.I2(\z[22]_INST_0_i_18_n_0 ),
.I3(\z[10]_INST_0_i_6_n_0 ),
.I4(\z[22]_INST_0_i_21_n_0 ),
.I5(\z[10]_INST_0_i_7_n_0 ),
.O(\z[10]_INST_0_i_2_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\z[10]_INST_0_i_3
(.I0(\z[16]_INST_0_i_7_n_0 ),
.I1(\z[10]_INST_0_i_8_n_0 ),
.I2(z0_carry_i_11_n_0),
.I3(\z[10]_INST_0_i_9_n_0 ),
.I4(z0_carry_i_10_n_0),
.I5(\z[10]_INST_0_i_10_n_0 ),
.O(\z[10]_INST_0_i_3_n_0 ));
LUT6 #(
.INIT(64'hA000A000CF00C000))
\z[10]_INST_0_i_4
(.I0(sign00__0_carry_n_7),
.I1(sel0[7]),
.I2(z0_carry_i_10_n_0),
.I3(z0_carry_i_8__0_n_0),
.I4(sel0[3]),
.I5(z0_carry_i_9_n_0),
.O(\z[10]_INST_0_i_4_n_0 ));
LUT6 #(
.INIT(64'hA000A000CF00C000))
\z[10]_INST_0_i_5
(.I0(sel0[1]),
.I1(sel0[9]),
.I2(z0_carry_i_10_n_0),
.I3(z0_carry_i_8__0_n_0),
.I4(sel0[5]),
.I5(z0_carry_i_9_n_0),
.O(\z[10]_INST_0_i_5_n_0 ));
LUT6 #(
.INIT(64'hB800B8B8000000B8))
\z[10]_INST_0_i_6
(.I0(sel0[21]),
.I1(\z[22]_INST_0_i_19_n_0 ),
.I2(sel0[13]),
.I3(z2),
.I4(z3[4]),
.I5(z0_carry_i_8__0_n_0),
.O(\z[10]_INST_0_i_6_n_0 ));
LUT6 #(
.INIT(64'hB800B8B8000000B8))
\z[10]_INST_0_i_7
(.I0(sel0[17]),
.I1(\z[22]_INST_0_i_19_n_0 ),
.I2(sel0[9]),
.I3(z2),
.I4(z3[4]),
.I5(z0_carry_i_8__0_n_0),
.O(\z[10]_INST_0_i_7_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair43" *)
LUT3 #(
.INIT(8'h08))
\z[10]_INST_0_i_8
(.I0(\z[31]_INST_0_i_2_n_0 ),
.I1(sel0[4]),
.I2(z0_carry_i_9_n_0),
.O(\z[10]_INST_0_i_8_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT3 #(
.INIT(8'h08))
\z[10]_INST_0_i_9
(.I0(\z[31]_INST_0_i_2_n_0 ),
.I1(sel0[6]),
.I2(z0_carry_i_9_n_0),
.O(\z[10]_INST_0_i_9_n_0 ));
LUT6 #(
.INIT(64'hCCCCCCCCF050A000))
\z[11]_INST_0
(.I0(\z[22]_INST_0_i_1_n_0 ),
.I1(z10_in[11]),
.I2(\z[22]_INST_0_i_3_n_0 ),
.I3(\z[11]_INST_0_i_2_n_0 ),
.I4(\z[12]_INST_0_i_2_n_0 ),
.I5(z2),
.O(z[11]));
LUT6 #(
.INIT(64'hA8A8A8080808A808))
\z[11]_INST_0_i_1
(.I0(\z[18]_INST_0_i_1_n_0 ),
.I1(\z[11]_INST_0_i_3_n_0 ),
.I2(\z[22]_INST_0_i_1_n_0 ),
.I3(\z[12]_INST_0_i_3_n_0 ),
.I4(z0_carry_i_11_n_0),
.I5(\z[14]_INST_0_i_3_n_0 ),
.O(z10_in[11]));
LUT5 #(
.INIT(32'hB8BBB888))
\z[11]_INST_0_i_2
(.I0(\z[13]_INST_0_i_4_n_0 ),
.I1(\z[22]_INST_0_i_18_n_0 ),
.I2(\z[11]_INST_0_i_4_n_0 ),
.I3(\z[22]_INST_0_i_21_n_0 ),
.I4(\z[11]_INST_0_i_5_n_0 ),
.O(\z[11]_INST_0_i_2_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\z[11]_INST_0_i_3
(.I0(\z[17]_INST_0_i_5_n_0 ),
.I1(\z[13]_INST_0_i_5_n_0 ),
.I2(z0_carry_i_11_n_0),
.I3(\z[15]_INST_0_i_5_n_0 ),
.I4(z0_carry_i_10_n_0),
.I5(\z[11]_INST_0_i_6_n_0 ),
.O(\z[11]_INST_0_i_3_n_0 ));
LUT6 #(
.INIT(64'hB800B8B8000000B8))
\z[11]_INST_0_i_4
(.I0(sel0[22]),
.I1(\z[22]_INST_0_i_19_n_0 ),
.I2(sel0[14]),
.I3(z2),
.I4(z3[4]),
.I5(z0_carry_i_8__0_n_0),
.O(\z[11]_INST_0_i_4_n_0 ));
LUT6 #(
.INIT(64'hB800B8B8000000B8))
\z[11]_INST_0_i_5
(.I0(sel0[18]),
.I1(\z[22]_INST_0_i_19_n_0 ),
.I2(sel0[10]),
.I3(z2),
.I4(z3[4]),
.I5(z0_carry_i_8__0_n_0),
.O(\z[11]_INST_0_i_5_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair45" *)
LUT3 #(
.INIT(8'h08))
\z[11]_INST_0_i_6
(.I0(\z[31]_INST_0_i_2_n_0 ),
.I1(sel0[3]),
.I2(z0_carry_i_9_n_0),
.O(\z[11]_INST_0_i_6_n_0 ));
LUT6 #(
.INIT(64'hCCCCCCCCF050A000))
\z[12]_INST_0
(.I0(\z[22]_INST_0_i_1_n_0 ),
.I1(z10_in[12]),
.I2(\z[22]_INST_0_i_3_n_0 ),
.I3(\z[12]_INST_0_i_2_n_0 ),
.I4(\z[13]_INST_0_i_2_n_0 ),
.I5(z2),
.O(z[12]));
LUT6 #(
.INIT(64'hAAAAA8080000A808))
\z[12]_INST_0_i_1
(.I0(\z[18]_INST_0_i_1_n_0 ),
.I1(\z[12]_INST_0_i_3_n_0 ),
.I2(z0_carry_i_11_n_0),
.I3(\z[14]_INST_0_i_3_n_0 ),
.I4(\z[22]_INST_0_i_1_n_0 ),
.I5(\z[13]_INST_0_i_3_n_0 ),
.O(z10_in[12]));
LUT5 #(
.INIT(32'hB8BBB888))
\z[12]_INST_0_i_2
(.I0(\z[14]_INST_0_i_5_n_0 ),
.I1(\z[22]_INST_0_i_18_n_0 ),
.I2(\z[12]_INST_0_i_4_n_0 ),
.I3(\z[22]_INST_0_i_21_n_0 ),
.I4(\z[12]_INST_0_i_5_n_0 ),
.O(\z[12]_INST_0_i_2_n_0 ));
LUT6 #(
.INIT(64'hA000A000CF00C000))
\z[12]_INST_0_i_3
(.I0(sel0[0]),
.I1(sel0[8]),
.I2(z0_carry_i_10_n_0),
.I3(z0_carry_i_8__0_n_0),
.I4(sel0[4]),
.I5(z0_carry_i_9_n_0),
.O(\z[12]_INST_0_i_3_n_0 ));
LUT6 #(
.INIT(64'hB800B8B8000000B8))
\z[12]_INST_0_i_4
(.I0(sel0[23]),
.I1(\z[22]_INST_0_i_19_n_0 ),
.I2(sel0[15]),
.I3(z2),
.I4(z3[4]),
.I5(z0_carry_i_8__0_n_0),
.O(\z[12]_INST_0_i_4_n_0 ));
LUT6 #(
.INIT(64'hB800B8B8000000B8))
\z[12]_INST_0_i_5
(.I0(sel0[19]),
.I1(\z[22]_INST_0_i_19_n_0 ),
.I2(sel0[11]),
.I3(z2),
.I4(z3[4]),
.I5(z0_carry_i_8__0_n_0),
.O(\z[12]_INST_0_i_5_n_0 ));
LUT6 #(
.INIT(64'hCCCCCCCCF050A000))
\z[13]_INST_0
(.I0(\z[22]_INST_0_i_1_n_0 ),
.I1(z10_in[13]),
.I2(\z[22]_INST_0_i_3_n_0 ),
.I3(\z[13]_INST_0_i_2_n_0 ),
.I4(\z[14]_INST_0_i_2_n_0 ),
.I5(z2),
.O(z[13]));
LUT6 #(
.INIT(64'hA8A8A8080808A808))
\z[13]_INST_0_i_1
(.I0(\z[18]_INST_0_i_1_n_0 ),
.I1(\z[13]_INST_0_i_3_n_0 ),
.I2(\z[22]_INST_0_i_1_n_0 ),
.I3(\z[14]_INST_0_i_3_n_0 ),
.I4(z0_carry_i_11_n_0),
.I5(\z[14]_INST_0_i_4_n_0 ),
.O(z10_in[13]));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT3 #(
.INIT(8'hB8))
\z[13]_INST_0_i_2
(.I0(\z[15]_INST_0_i_4_n_0 ),
.I1(\z[22]_INST_0_i_18_n_0 ),
.I2(\z[13]_INST_0_i_4_n_0 ),
.O(\z[13]_INST_0_i_2_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\z[13]_INST_0_i_3
(.I0(\z[19]_INST_0_i_5_n_0 ),
.I1(\z[15]_INST_0_i_5_n_0 ),
.I2(z0_carry_i_11_n_0),
.I3(\z[17]_INST_0_i_5_n_0 ),
.I4(z0_carry_i_10_n_0),
.I5(\z[13]_INST_0_i_5_n_0 ),
.O(\z[13]_INST_0_i_3_n_0 ));
LUT6 #(
.INIT(64'h0000000030BB3088))
\z[13]_INST_0_i_4
(.I0(sel0[16]),
.I1(\z[22]_INST_0_i_21_n_0 ),
.I2(sel0[20]),
.I3(\z[22]_INST_0_i_19_n_0 ),
.I4(sel0[12]),
.I5(\z[22]_INST_0_i_20_n_0 ),
.O(\z[13]_INST_0_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT3 #(
.INIT(8'h08))
\z[13]_INST_0_i_5
(.I0(\z[31]_INST_0_i_2_n_0 ),
.I1(sel0[5]),
.I2(z0_carry_i_9_n_0),
.O(\z[13]_INST_0_i_5_n_0 ));
LUT6 #(
.INIT(64'hCCCCCCCCF050A000))
\z[14]_INST_0
(.I0(\z[22]_INST_0_i_1_n_0 ),
.I1(z10_in[14]),
.I2(\z[22]_INST_0_i_3_n_0 ),
.I3(\z[14]_INST_0_i_2_n_0 ),
.I4(\z[15]_INST_0_i_2_n_0 ),
.I5(z2),
.O(z[14]));
LUT6 #(
.INIT(64'hAAAAA8080000A808))
\z[14]_INST_0_i_1
(.I0(\z[18]_INST_0_i_1_n_0 ),
.I1(\z[14]_INST_0_i_3_n_0 ),
.I2(z0_carry_i_11_n_0),
.I3(\z[14]_INST_0_i_4_n_0 ),
.I4(\z[22]_INST_0_i_1_n_0 ),
.I5(\z[15]_INST_0_i_3_n_0 ),
.O(z10_in[14]));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT3 #(
.INIT(8'hB8))
\z[14]_INST_0_i_2
(.I0(\z[16]_INST_0_i_6_n_0 ),
.I1(\z[22]_INST_0_i_18_n_0 ),
.I2(\z[14]_INST_0_i_5_n_0 ),
.O(\z[14]_INST_0_i_2_n_0 ));
LUT6 #(
.INIT(64'hA000A000CF00C000))
\z[14]_INST_0_i_3
(.I0(sel0[2]),
.I1(sel0[10]),
.I2(z0_carry_i_10_n_0),
.I3(z0_carry_i_8__0_n_0),
.I4(sel0[6]),
.I5(z0_carry_i_9_n_0),
.O(\z[14]_INST_0_i_3_n_0 ));
LUT6 #(
.INIT(64'hB800FFFFB8000000))
\z[14]_INST_0_i_4
(.I0(sel0[4]),
.I1(z0_carry_i_9_n_0),
.I2(sel0[12]),
.I3(z0_carry_i_8__0_n_0),
.I4(z0_carry_i_10_n_0),
.I5(\z[16]_INST_0_i_7_n_0 ),
.O(\z[14]_INST_0_i_4_n_0 ));
LUT6 #(
.INIT(64'h0000000030BB3088))
\z[14]_INST_0_i_5
(.I0(sel0[17]),
.I1(\z[22]_INST_0_i_21_n_0 ),
.I2(sel0[21]),
.I3(\z[22]_INST_0_i_19_n_0 ),
.I4(sel0[13]),
.I5(\z[22]_INST_0_i_20_n_0 ),
.O(\z[14]_INST_0_i_5_n_0 ));
LUT6 #(
.INIT(64'h33333333F373B333))
\z[15]_INST_0
(.I0(\z[22]_INST_0_i_1_n_0 ),
.I1(\z[15]_INST_0_i_1_n_0 ),
.I2(\z[22]_INST_0_i_3_n_0 ),
.I3(\z[15]_INST_0_i_2_n_0 ),
.I4(\z[16]_INST_0_i_2_n_0 ),
.I5(z2),
.O(z[15]));
LUT5 #(
.INIT(32'h47FFFFFF))
\z[15]_INST_0_i_1
(.I0(\z[16]_INST_0_i_5_n_0 ),
.I1(\z[22]_INST_0_i_1_n_0 ),
.I2(\z[15]_INST_0_i_3_n_0 ),
.I3(\z[18]_INST_0_i_1_n_0 ),
.I4(z2),
.O(\z[15]_INST_0_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT3 #(
.INIT(8'hB8))
\z[15]_INST_0_i_2
(.I0(\z[17]_INST_0_i_4_n_0 ),
.I1(\z[22]_INST_0_i_18_n_0 ),
.I2(\z[15]_INST_0_i_4_n_0 ),
.O(\z[15]_INST_0_i_2_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\z[15]_INST_0_i_3
(.I0(\z[21]_INST_0_i_4_n_0 ),
.I1(\z[17]_INST_0_i_5_n_0 ),
.I2(z0_carry_i_11_n_0),
.I3(\z[19]_INST_0_i_5_n_0 ),
.I4(z0_carry_i_10_n_0),
.I5(\z[15]_INST_0_i_5_n_0 ),
.O(\z[15]_INST_0_i_3_n_0 ));
LUT6 #(
.INIT(64'h0000000030BB3088))
\z[15]_INST_0_i_4
(.I0(sel0[18]),
.I1(\z[22]_INST_0_i_21_n_0 ),
.I2(sel0[22]),
.I3(\z[22]_INST_0_i_19_n_0 ),
.I4(sel0[14]),
.I5(\z[22]_INST_0_i_20_n_0 ),
.O(\z[15]_INST_0_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT4 #(
.INIT(16'h3088))
\z[15]_INST_0_i_5
(.I0(sign00__0_carry_n_7),
.I1(z0_carry_i_9_n_0),
.I2(sel0[7]),
.I3(\z[31]_INST_0_i_2_n_0 ),
.O(\z[15]_INST_0_i_5_n_0 ));
LUT6 #(
.INIT(64'h33333333F373B333))
\z[16]_INST_0
(.I0(\z[22]_INST_0_i_1_n_0 ),
.I1(\z[16]_INST_0_i_1_n_0 ),
.I2(\z[22]_INST_0_i_3_n_0 ),
.I3(\z[16]_INST_0_i_2_n_0 ),
.I4(\z[16]_INST_0_i_3_n_0 ),
.I5(z2),
.O(z[16]));
LUT5 #(
.INIT(32'h47FFFFFF))
\z[16]_INST_0_i_1
(.I0(\z[16]_INST_0_i_4_n_0 ),
.I1(\z[22]_INST_0_i_1_n_0 ),
.I2(\z[16]_INST_0_i_5_n_0 ),
.I3(\z[18]_INST_0_i_1_n_0 ),
.I4(z2),
.O(\z[16]_INST_0_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT3 #(
.INIT(8'hB8))
\z[16]_INST_0_i_2
(.I0(\z[18]_INST_0_i_9_n_0 ),
.I1(\z[22]_INST_0_i_18_n_0 ),
.I2(\z[16]_INST_0_i_6_n_0 ),
.O(\z[16]_INST_0_i_2_n_0 ));
LUT3 #(
.INIT(8'hB8))
\z[16]_INST_0_i_3
(.I0(\z[19]_INST_0_i_4_n_0 ),
.I1(\z[22]_INST_0_i_18_n_0 ),
.I2(\z[17]_INST_0_i_4_n_0 ),
.O(\z[16]_INST_0_i_3_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\z[16]_INST_0_i_4
(.I0(\z[22]_INST_0_i_31_n_0 ),
.I1(\z[19]_INST_0_i_5_n_0 ),
.I2(z0_carry_i_11_n_0),
.I3(\z[21]_INST_0_i_4_n_0 ),
.I4(z0_carry_i_10_n_0),
.I5(\z[17]_INST_0_i_5_n_0 ),
.O(\z[16]_INST_0_i_4_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\z[16]_INST_0_i_5
(.I0(\z[22]_INST_0_i_29_n_0 ),
.I1(\z[18]_INST_0_i_10_n_0 ),
.I2(z0_carry_i_11_n_0),
.I3(\z[20]_INST_0_i_5_n_0 ),
.I4(z0_carry_i_10_n_0),
.I5(\z[16]_INST_0_i_7_n_0 ),
.O(\z[16]_INST_0_i_5_n_0 ));
LUT6 #(
.INIT(64'h0000000030BB3088))
\z[16]_INST_0_i_6
(.I0(sel0[19]),
.I1(\z[22]_INST_0_i_21_n_0 ),
.I2(sel0[23]),
.I3(\z[22]_INST_0_i_19_n_0 ),
.I4(sel0[15]),
.I5(\z[22]_INST_0_i_20_n_0 ),
.O(\z[16]_INST_0_i_6_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT4 #(
.INIT(16'h3088))
\z[16]_INST_0_i_7
(.I0(sel0[0]),
.I1(z0_carry_i_9_n_0),
.I2(sel0[8]),
.I3(\z[31]_INST_0_i_2_n_0 ),
.O(\z[16]_INST_0_i_7_n_0 ));
LUT5 #(
.INIT(32'h8888F000))
\z[17]_INST_0
(.I0(\z[18]_INST_0_i_1_n_0 ),
.I1(\z[17]_INST_0_i_1_n_0 ),
.I2(\z[22]_INST_0_i_3_n_0 ),
.I3(\z[17]_INST_0_i_2_n_0 ),
.I4(z2),
.O(z[17]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\z[17]_INST_0_i_1
(.I0(\z[18]_INST_0_i_6_n_0 ),
.I1(\z[18]_INST_0_i_7_n_0 ),
.I2(\z[22]_INST_0_i_1_n_0 ),
.I3(\z[18]_INST_0_i_5_n_0 ),
.I4(z0_carry_i_11_n_0),
.I5(\z[17]_INST_0_i_3_n_0 ),
.O(\z[17]_INST_0_i_1_n_0 ));
LUT6 #(
.INIT(64'hEE44FAFAEE445050))
\z[17]_INST_0_i_2
(.I0(\z[22]_INST_0_i_1_n_0 ),
.I1(\z[20]_INST_0_i_4_n_0 ),
.I2(\z[18]_INST_0_i_9_n_0 ),
.I3(\z[19]_INST_0_i_4_n_0 ),
.I4(\z[22]_INST_0_i_18_n_0 ),
.I5(\z[17]_INST_0_i_4_n_0 ),
.O(\z[17]_INST_0_i_2_n_0 ));
LUT6 #(
.INIT(64'hB800FFFFB8000000))
\z[17]_INST_0_i_3
(.I0(sel0[5]),
.I1(z0_carry_i_9_n_0),
.I2(sel0[13]),
.I3(z0_carry_i_8__0_n_0),
.I4(z0_carry_i_10_n_0),
.I5(\z[17]_INST_0_i_5_n_0 ),
.O(\z[17]_INST_0_i_3_n_0 ));
LUT5 #(
.INIT(32'h00000B08))
\z[17]_INST_0_i_4
(.I0(sel0[20]),
.I1(\z[22]_INST_0_i_21_n_0 ),
.I2(\z[22]_INST_0_i_20_n_0 ),
.I3(sel0[16]),
.I4(\z[22]_INST_0_i_19_n_0 ),
.O(\z[17]_INST_0_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT4 #(
.INIT(16'h3088))
\z[17]_INST_0_i_5
(.I0(sel0[1]),
.I1(z0_carry_i_9_n_0),
.I2(sel0[9]),
.I3(\z[31]_INST_0_i_2_n_0 ),
.O(\z[17]_INST_0_i_5_n_0 ));
LUT5 #(
.INIT(32'h8888F000))
\z[18]_INST_0
(.I0(\z[18]_INST_0_i_1_n_0 ),
.I1(\z[18]_INST_0_i_2_n_0 ),
.I2(\z[22]_INST_0_i_3_n_0 ),
.I3(\z[18]_INST_0_i_3_n_0 ),
.I4(z2),
.O(z[18]));
LUT2 #(
.INIT(4'h7))
\z[18]_INST_0_i_1
(.I0(z0_carry_i_9_n_0),
.I1(\z[31]_INST_0_i_2_n_0 ),
.O(\z[18]_INST_0_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT4 #(
.INIT(16'h3088))
\z[18]_INST_0_i_10
(.I0(sel0[2]),
.I1(z0_carry_i_9_n_0),
.I2(sel0[10]),
.I3(\z[31]_INST_0_i_2_n_0 ),
.O(\z[18]_INST_0_i_10_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\z[18]_INST_0_i_2
(.I0(\z[18]_INST_0_i_4_n_0 ),
.I1(\z[18]_INST_0_i_5_n_0 ),
.I2(\z[22]_INST_0_i_1_n_0 ),
.I3(\z[18]_INST_0_i_6_n_0 ),
.I4(z0_carry_i_11_n_0),
.I5(\z[18]_INST_0_i_7_n_0 ),
.O(\z[18]_INST_0_i_2_n_0 ));
LUT6 #(
.INIT(64'hEE44FAFAEE445050))
\z[18]_INST_0_i_3
(.I0(\z[22]_INST_0_i_1_n_0 ),
.I1(\z[18]_INST_0_i_8_n_0 ),
.I2(\z[19]_INST_0_i_4_n_0 ),
.I3(\z[20]_INST_0_i_4_n_0 ),
.I4(\z[22]_INST_0_i_18_n_0 ),
.I5(\z[18]_INST_0_i_9_n_0 ),
.O(\z[18]_INST_0_i_3_n_0 ));
LUT6 #(
.INIT(64'hB8BBB88888888888))
\z[18]_INST_0_i_4
(.I0(\z[22]_INST_0_i_33_n_0 ),
.I1(z0_carry_i_10_n_0),
.I2(sel0[5]),
.I3(z0_carry_i_9_n_0),
.I4(sel0[13]),
.I5(z0_carry_i_8__0_n_0),
.O(\z[18]_INST_0_i_4_n_0 ));
LUT6 #(
.INIT(64'hB8BBB88888888888))
\z[18]_INST_0_i_5
(.I0(\z[22]_INST_0_i_31_n_0 ),
.I1(z0_carry_i_10_n_0),
.I2(sel0[3]),
.I3(z0_carry_i_9_n_0),
.I4(sel0[11]),
.I5(z0_carry_i_8__0_n_0),
.O(\z[18]_INST_0_i_5_n_0 ));
LUT6 #(
.INIT(64'hB8BBB88888888888))
\z[18]_INST_0_i_6
(.I0(\z[22]_INST_0_i_27_n_0 ),
.I1(z0_carry_i_10_n_0),
.I2(sel0[4]),
.I3(z0_carry_i_9_n_0),
.I4(sel0[12]),
.I5(z0_carry_i_8__0_n_0),
.O(\z[18]_INST_0_i_6_n_0 ));
LUT6 #(
.INIT(64'hB800FFFFB8000000))
\z[18]_INST_0_i_7
(.I0(sel0[6]),
.I1(z0_carry_i_9_n_0),
.I2(sel0[14]),
.I3(z0_carry_i_8__0_n_0),
.I4(z0_carry_i_10_n_0),
.I5(\z[18]_INST_0_i_10_n_0 ),
.O(\z[18]_INST_0_i_7_n_0 ));
LUT6 #(
.INIT(64'h0400040400000004))
\z[18]_INST_0_i_8
(.I0(\z[22]_INST_0_i_19_n_0 ),
.I1(sel0[20]),
.I2(\z[22]_INST_0_i_20_n_0 ),
.I3(z2),
.I4(z3[2]),
.I5(z0_carry_i_10_n_0),
.O(\z[18]_INST_0_i_8_n_0 ));
LUT5 #(
.INIT(32'h00000B08))
\z[18]_INST_0_i_9
(.I0(sel0[21]),
.I1(\z[22]_INST_0_i_21_n_0 ),
.I2(\z[22]_INST_0_i_20_n_0 ),
.I3(sel0[17]),
.I4(\z[22]_INST_0_i_19_n_0 ),
.O(\z[18]_INST_0_i_9_n_0 ));
LUT6 #(
.INIT(64'h33333333F373B333))
\z[19]_INST_0
(.I0(\z[22]_INST_0_i_1_n_0 ),
.I1(\z[19]_INST_0_i_1_n_0 ),
.I2(\z[22]_INST_0_i_3_n_0 ),
.I3(\z[19]_INST_0_i_2_n_0 ),
.I4(\z[20]_INST_0_i_2_n_0 ),
.I5(z2),
.O(z[19]));
LUT5 #(
.INIT(32'h47FFFFFF))
\z[19]_INST_0_i_1
(.I0(\z[20]_INST_0_i_3_n_0 ),
.I1(\z[22]_INST_0_i_1_n_0 ),
.I2(\z[19]_INST_0_i_3_n_0 ),
.I3(\z[18]_INST_0_i_1_n_0 ),
.I4(z2),
.O(\z[19]_INST_0_i_1_n_0 ));
LUT6 #(
.INIT(64'h0004FFFF00040000))
\z[19]_INST_0_i_2
(.I0(\z[22]_INST_0_i_19_n_0 ),
.I1(sel0[20]),
.I2(\z[22]_INST_0_i_20_n_0 ),
.I3(\z[22]_INST_0_i_21_n_0 ),
.I4(\z[22]_INST_0_i_18_n_0 ),
.I5(\z[19]_INST_0_i_4_n_0 ),
.O(\z[19]_INST_0_i_2_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\z[19]_INST_0_i_3
(.I0(\z[22]_INST_0_i_33_n_0 ),
.I1(\z[21]_INST_0_i_4_n_0 ),
.I2(z0_carry_i_11_n_0),
.I3(\z[22]_INST_0_i_31_n_0 ),
.I4(z0_carry_i_10_n_0),
.I5(\z[19]_INST_0_i_5_n_0 ),
.O(\z[19]_INST_0_i_3_n_0 ));
LUT5 #(
.INIT(32'h00000B08))
\z[19]_INST_0_i_4
(.I0(sel0[22]),
.I1(\z[22]_INST_0_i_21_n_0 ),
.I2(\z[22]_INST_0_i_20_n_0 ),
.I3(sel0[18]),
.I4(\z[22]_INST_0_i_19_n_0 ),
.O(\z[19]_INST_0_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT4 #(
.INIT(16'h3088))
\z[19]_INST_0_i_5
(.I0(sel0[3]),
.I1(z0_carry_i_9_n_0),
.I2(sel0[11]),
.I3(\z[31]_INST_0_i_2_n_0 ),
.O(\z[19]_INST_0_i_5_n_0 ));
LUT6 #(
.INIT(64'h33333333F373B333))
\z[1]_INST_0
(.I0(\z[22]_INST_0_i_1_n_0 ),
.I1(\z[1]_INST_0_i_1_n_0 ),
.I2(\z[22]_INST_0_i_3_n_0 ),
.I3(\z[1]_INST_0_i_2_n_0 ),
.I4(\z[2]_INST_0_i_2_n_0 ),
.I5(z2),
.O(z[1]));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT5 #(
.INIT(32'h47FFFFFF))
\z[1]_INST_0_i_1
(.I0(\z[2]_INST_0_i_3_n_0 ),
.I1(\z[22]_INST_0_i_1_n_0 ),
.I2(\z[1]_INST_0_i_3_n_0 ),
.I3(\z[18]_INST_0_i_1_n_0 ),
.I4(z2),
.O(\z[1]_INST_0_i_1_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\z[1]_INST_0_i_2
(.I0(\z[7]_INST_0_i_5_n_0 ),
.I1(\z[3]_INST_0_i_4_n_0 ),
.I2(\z[22]_INST_0_i_18_n_0 ),
.I3(\z[5]_INST_0_i_5_n_0 ),
.I4(\z[22]_INST_0_i_21_n_0 ),
.I5(\z[1]_INST_0_i_4_n_0 ),
.O(\z[1]_INST_0_i_2_n_0 ));
LUT5 #(
.INIT(32'h00800000))
\z[1]_INST_0_i_3
(.I0(z0_carry_i_10_n_0),
.I1(z0_carry_i_8__0_n_0),
.I2(sign00__0_carry_n_7),
.I3(z0_carry_i_9_n_0),
.I4(z0_carry_i_11_n_0),
.O(\z[1]_INST_0_i_3_n_0 ));
LUT5 #(
.INIT(32'h30BB3088))
\z[1]_INST_0_i_4
(.I0(sel0[8]),
.I1(\z[22]_INST_0_i_19_n_0 ),
.I2(sel0[16]),
.I3(\z[22]_INST_0_i_20_n_0 ),
.I4(sel0[0]),
.O(\z[1]_INST_0_i_4_n_0 ));
LUT6 #(
.INIT(64'h33333333F373B333))
\z[20]_INST_0
(.I0(\z[22]_INST_0_i_1_n_0 ),
.I1(\z[20]_INST_0_i_1_n_0 ),
.I2(\z[22]_INST_0_i_3_n_0 ),
.I3(\z[20]_INST_0_i_2_n_0 ),
.I4(\z[21]_INST_0_i_2_n_0 ),
.I5(z2),
.O(z[20]));
LUT5 #(
.INIT(32'h47FFFFFF))
\z[20]_INST_0_i_1
(.I0(\z[21]_INST_0_i_3_n_0 ),
.I1(\z[22]_INST_0_i_1_n_0 ),
.I2(\z[20]_INST_0_i_3_n_0 ),
.I3(\z[18]_INST_0_i_1_n_0 ),
.I4(z2),
.O(\z[20]_INST_0_i_1_n_0 ));
LUT6 #(
.INIT(64'h0004FFFF00040000))
\z[20]_INST_0_i_2
(.I0(\z[22]_INST_0_i_19_n_0 ),
.I1(sel0[21]),
.I2(\z[22]_INST_0_i_20_n_0 ),
.I3(\z[22]_INST_0_i_21_n_0 ),
.I4(\z[22]_INST_0_i_18_n_0 ),
.I5(\z[20]_INST_0_i_4_n_0 ),
.O(\z[20]_INST_0_i_2_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\z[20]_INST_0_i_3
(.I0(\z[22]_INST_0_i_28_n_0 ),
.I1(\z[22]_INST_0_i_29_n_0 ),
.I2(z0_carry_i_11_n_0),
.I3(\z[22]_INST_0_i_27_n_0 ),
.I4(z0_carry_i_10_n_0),
.I5(\z[20]_INST_0_i_5_n_0 ),
.O(\z[20]_INST_0_i_3_n_0 ));
LUT5 #(
.INIT(32'h00000B08))
\z[20]_INST_0_i_4
(.I0(sel0[23]),
.I1(\z[22]_INST_0_i_21_n_0 ),
.I2(\z[22]_INST_0_i_20_n_0 ),
.I3(sel0[19]),
.I4(\z[22]_INST_0_i_19_n_0 ),
.O(\z[20]_INST_0_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT4 #(
.INIT(16'h3088))
\z[20]_INST_0_i_5
(.I0(sel0[4]),
.I1(z0_carry_i_9_n_0),
.I2(sel0[12]),
.I3(\z[31]_INST_0_i_2_n_0 ),
.O(\z[20]_INST_0_i_5_n_0 ));
LUT6 #(
.INIT(64'h33333333F373B333))
\z[21]_INST_0
(.I0(\z[22]_INST_0_i_1_n_0 ),
.I1(\z[21]_INST_0_i_1_n_0 ),
.I2(\z[22]_INST_0_i_3_n_0 ),
.I3(\z[21]_INST_0_i_2_n_0 ),
.I4(\z[22]_INST_0_i_4_n_0 ),
.I5(z2),
.O(z[21]));
LUT5 #(
.INIT(32'h47FFFFFF))
\z[21]_INST_0_i_1
(.I0(\z[22]_INST_0_i_10_n_0 ),
.I1(\z[22]_INST_0_i_1_n_0 ),
.I2(\z[21]_INST_0_i_3_n_0 ),
.I3(\z[18]_INST_0_i_1_n_0 ),
.I4(z2),
.O(\z[21]_INST_0_i_1_n_0 ));
LUT6 #(
.INIT(64'h0000000000000B08))
\z[21]_INST_0_i_2
(.I0(sel0[22]),
.I1(\z[22]_INST_0_i_18_n_0 ),
.I2(\z[22]_INST_0_i_19_n_0 ),
.I3(sel0[20]),
.I4(\z[22]_INST_0_i_20_n_0 ),
.I5(\z[22]_INST_0_i_21_n_0 ),
.O(\z[21]_INST_0_i_2_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\z[21]_INST_0_i_3
(.I0(\z[22]_INST_0_i_30_n_0 ),
.I1(\z[22]_INST_0_i_31_n_0 ),
.I2(z0_carry_i_11_n_0),
.I3(\z[22]_INST_0_i_33_n_0 ),
.I4(z0_carry_i_10_n_0),
.I5(\z[21]_INST_0_i_4_n_0 ),
.O(\z[21]_INST_0_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'h3088))
\z[21]_INST_0_i_4
(.I0(sel0[5]),
.I1(z0_carry_i_9_n_0),
.I2(sel0[13]),
.I3(\z[31]_INST_0_i_2_n_0 ),
.O(\z[21]_INST_0_i_4_n_0 ));
LUT6 #(
.INIT(64'hCCCCCCCCF050A000))
\z[22]_INST_0
(.I0(\z[22]_INST_0_i_1_n_0 ),
.I1(z10_in[22]),
.I2(\z[22]_INST_0_i_3_n_0 ),
.I3(\z[22]_INST_0_i_4_n_0 ),
.I4(\z[22]_INST_0_i_5_n_0 ),
.I5(z2),
.O(z[22]));
LUT6 #(
.INIT(64'h5555555544444440))
\z[22]_INST_0_i_1
(.I0(sel0[23]),
.I1(\z[22]_INST_0_i_6_n_0 ),
.I2(sel0[14]),
.I3(\z[22]_INST_0_i_7_n_0 ),
.I4(\z[22]_INST_0_i_8_n_0 ),
.I5(\z[22]_INST_0_i_9_n_0 ),
.O(\z[22]_INST_0_i_1_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\z[22]_INST_0_i_10
(.I0(\z[22]_INST_0_i_26_n_0 ),
.I1(\z[22]_INST_0_i_27_n_0 ),
.I2(z0_carry_i_11_n_0),
.I3(\z[22]_INST_0_i_28_n_0 ),
.I4(z0_carry_i_10_n_0),
.I5(\z[22]_INST_0_i_29_n_0 ),
.O(\z[22]_INST_0_i_10_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT3 #(
.INIT(8'hB8))
\z[22]_INST_0_i_11
(.I0(\z[22]_INST_0_i_30_n_0 ),
.I1(z0_carry_i_10_n_0),
.I2(\z[22]_INST_0_i_31_n_0 ),
.O(\z[22]_INST_0_i_11_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT3 #(
.INIT(8'hB8))
\z[22]_INST_0_i_12
(.I0(\z[22]_INST_0_i_32_n_0 ),
.I1(z0_carry_i_10_n_0),
.I2(\z[22]_INST_0_i_33_n_0 ),
.O(\z[22]_INST_0_i_12_n_0 ));
LUT5 #(
.INIT(32'hFFFFFFFE))
\z[22]_INST_0_i_13
(.I0(\z[22]_INST_0_i_34_n_0 ),
.I1(\z[22]_INST_0_i_35_n_0 ),
.I2(\z[22]_INST_0_i_36_n_0 ),
.I3(\z[22]_INST_0_i_37_n_0 ),
.I4(\z[22]_INST_0_i_38_n_0 ),
.O(\z[22]_INST_0_i_13_n_0 ));
LUT6 #(
.INIT(64'h0F0FFFFF0F0FFFEE))
\z[22]_INST_0_i_14
(.I0(z3[11]),
.I1(z3[12]),
.I2(\z[18]_INST_0_i_1_n_0 ),
.I3(z3[9]),
.I4(z2),
.I5(z3[10]),
.O(\z[22]_INST_0_i_14_n_0 ));
LUT6 #(
.INIT(64'h0F0FFFFF0F0FFFEE))
\z[22]_INST_0_i_15
(.I0(z3[7]),
.I1(z3[8]),
.I2(\z[18]_INST_0_i_1_n_0 ),
.I3(z3[5]),
.I4(z2),
.I5(z3[6]),
.O(\z[22]_INST_0_i_15_n_0 ));
LUT6 #(
.INIT(64'h0F0FFFFF0F0FFFEE))
\z[22]_INST_0_i_16
(.I0(z3[19]),
.I1(z3[20]),
.I2(\z[18]_INST_0_i_1_n_0 ),
.I3(z3[17]),
.I4(z2),
.I5(z3[18]),
.O(\z[22]_INST_0_i_16_n_0 ));
LUT6 #(
.INIT(64'h0F0FFFFF0F0FFFEE))
\z[22]_INST_0_i_17
(.I0(z3[15]),
.I1(z3[16]),
.I2(\z[18]_INST_0_i_1_n_0 ),
.I3(z3[13]),
.I4(z2),
.I5(z3[14]),
.O(\z[22]_INST_0_i_17_n_0 ));
LUT3 #(
.INIT(8'h5C))
\z[22]_INST_0_i_18
(.I0(z0_carry_i_11_n_0),
.I1(z3[1]),
.I2(z2),
.O(\z[22]_INST_0_i_18_n_0 ));
LUT3 #(
.INIT(8'hAC))
\z[22]_INST_0_i_19
(.I0(z0_carry_i_9_n_0),
.I1(z3[3]),
.I2(z2),
.O(\z[22]_INST_0_i_19_n_0 ));
LUT6 #(
.INIT(64'hA8A8A8080808A808))
\z[22]_INST_0_i_2
(.I0(\z[18]_INST_0_i_1_n_0 ),
.I1(\z[22]_INST_0_i_10_n_0 ),
.I2(\z[22]_INST_0_i_1_n_0 ),
.I3(\z[22]_INST_0_i_11_n_0 ),
.I4(z0_carry_i_11_n_0),
.I5(\z[22]_INST_0_i_12_n_0 ),
.O(z10_in[22]));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT4 #(
.INIT(16'h99F0))
\z[22]_INST_0_i_20
(.I0(z0_carry_i_9_n_0),
.I1(\z[31]_INST_0_i_2_n_0 ),
.I2(z3[4]),
.I3(z2),
.O(\z[22]_INST_0_i_20_n_0 ));
LUT5 #(
.INIT(32'hBFBFFF00))
\z[22]_INST_0_i_21
(.I0(sel0[23]),
.I1(\z[22]_INST_0_i_39_n_0 ),
.I2(_carry_i_8_n_0),
.I3(z3[2]),
.I4(z2),
.O(\z[22]_INST_0_i_21_n_0 ));
LUT2 #(
.INIT(4'hE))
\z[22]_INST_0_i_22
(.I0(sel0[19]),
.I1(sel0[21]),
.O(\z[22]_INST_0_i_22_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair49" *)
LUT2 #(
.INIT(4'h1))
\z[22]_INST_0_i_23
(.I0(sel0[9]),
.I1(sel0[11]),
.O(\z[22]_INST_0_i_23_n_0 ));
LUT6 #(
.INIT(64'hEEFEEEFEFFFFEEFE))
\z[22]_INST_0_i_24
(.I0(sel0[6]),
.I1(sel0[2]),
.I2(sel0[4]),
.I3(sel0[5]),
.I4(sel0[0]),
.I5(sel0[1]),
.O(\z[22]_INST_0_i_24_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair48" *)
LUT3 #(
.INIT(8'h45))
\z[22]_INST_0_i_25
(.I0(sel0[6]),
.I1(sel0[5]),
.I2(sel0[4]),
.O(\z[22]_INST_0_i_25_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT5 #(
.INIT(32'h30BB3088))
\z[22]_INST_0_i_26
(.I0(sel0[12]),
.I1(z0_carry_i_9_n_0),
.I2(sel0[20]),
.I3(\z[31]_INST_0_i_2_n_0 ),
.I4(sel0[4]),
.O(\z[22]_INST_0_i_26_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'h30BB3088))
\z[22]_INST_0_i_27
(.I0(sel0[8]),
.I1(z0_carry_i_9_n_0),
.I2(sel0[16]),
.I3(\z[31]_INST_0_i_2_n_0 ),
.I4(sel0[0]),
.O(\z[22]_INST_0_i_27_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT5 #(
.INIT(32'h30BB3088))
\z[22]_INST_0_i_28
(.I0(sel0[10]),
.I1(z0_carry_i_9_n_0),
.I2(sel0[18]),
.I3(\z[31]_INST_0_i_2_n_0 ),
.I4(sel0[2]),
.O(\z[22]_INST_0_i_28_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT4 #(
.INIT(16'h3088))
\z[22]_INST_0_i_29
(.I0(sel0[6]),
.I1(z0_carry_i_9_n_0),
.I2(sel0[14]),
.I3(\z[31]_INST_0_i_2_n_0 ),
.O(\z[22]_INST_0_i_29_n_0 ));
LUT5 #(
.INIT(32'h00000001))
\z[22]_INST_0_i_3
(.I0(\z[22]_INST_0_i_13_n_0 ),
.I1(\z[22]_INST_0_i_14_n_0 ),
.I2(\z[22]_INST_0_i_15_n_0 ),
.I3(\z[22]_INST_0_i_16_n_0 ),
.I4(\z[22]_INST_0_i_17_n_0 ),
.O(\z[22]_INST_0_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h30BB3088))
\z[22]_INST_0_i_30
(.I0(sel0[11]),
.I1(z0_carry_i_9_n_0),
.I2(sel0[19]),
.I3(\z[31]_INST_0_i_2_n_0 ),
.I4(sel0[3]),
.O(\z[22]_INST_0_i_30_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT5 #(
.INIT(32'h30BB3088))
\z[22]_INST_0_i_31
(.I0(sel0[7]),
.I1(z0_carry_i_9_n_0),
.I2(sel0[15]),
.I3(\z[31]_INST_0_i_2_n_0 ),
.I4(sign00__0_carry_n_7),
.O(\z[22]_INST_0_i_31_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT5 #(
.INIT(32'h30BB3088))
\z[22]_INST_0_i_32
(.I0(sel0[13]),
.I1(z0_carry_i_9_n_0),
.I2(sel0[21]),
.I3(\z[31]_INST_0_i_2_n_0 ),
.I4(sel0[5]),
.O(\z[22]_INST_0_i_32_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT5 #(
.INIT(32'h30BB3088))
\z[22]_INST_0_i_33
(.I0(sel0[9]),
.I1(z0_carry_i_9_n_0),
.I2(sel0[17]),
.I3(\z[31]_INST_0_i_2_n_0 ),
.I4(sel0[1]),
.O(\z[22]_INST_0_i_33_n_0 ));
LUT5 #(
.INIT(32'hFE323232))
\z[22]_INST_0_i_34
(.I0(z3[30]),
.I1(z2),
.I2(z3[29]),
.I3(\z[31]_INST_0_i_2_n_0 ),
.I4(z0_carry_i_9_n_0),
.O(\z[22]_INST_0_i_34_n_0 ));
LUT5 #(
.INIT(32'hFE323232))
\z[22]_INST_0_i_35
(.I0(z3[24]),
.I1(z2),
.I2(z3[23]),
.I3(\z[31]_INST_0_i_2_n_0 ),
.I4(z0_carry_i_9_n_0),
.O(\z[22]_INST_0_i_35_n_0 ));
LUT5 #(
.INIT(32'hFE323232))
\z[22]_INST_0_i_36
(.I0(z3[22]),
.I1(z2),
.I2(z3[21]),
.I3(\z[31]_INST_0_i_2_n_0 ),
.I4(z0_carry_i_9_n_0),
.O(\z[22]_INST_0_i_36_n_0 ));
LUT5 #(
.INIT(32'hFE323232))
\z[22]_INST_0_i_37
(.I0(z3[28]),
.I1(z2),
.I2(z3[27]),
.I3(\z[31]_INST_0_i_2_n_0 ),
.I4(z0_carry_i_9_n_0),
.O(\z[22]_INST_0_i_37_n_0 ));
LUT5 #(
.INIT(32'hFE323232))
\z[22]_INST_0_i_38
(.I0(z3[26]),
.I1(z2),
.I2(z3[25]),
.I3(\z[31]_INST_0_i_2_n_0 ),
.I4(z0_carry_i_9_n_0),
.O(\z[22]_INST_0_i_38_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFEAAAAAAAA))
\z[22]_INST_0_i_39
(.I0(_carry_i_5_n_0),
.I1(sel0[14]),
.I2(\z[22]_INST_0_i_40_n_0 ),
.I3(sel0[13]),
.I4(sel0[12]),
.I5(_carry_i_7_n_0),
.O(\z[22]_INST_0_i_39_n_0 ));
LUT6 #(
.INIT(64'h0000000000000B08))
\z[22]_INST_0_i_4
(.I0(sel0[23]),
.I1(\z[22]_INST_0_i_18_n_0 ),
.I2(\z[22]_INST_0_i_19_n_0 ),
.I3(sel0[21]),
.I4(\z[22]_INST_0_i_20_n_0 ),
.I5(\z[22]_INST_0_i_21_n_0 ),
.O(\z[22]_INST_0_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT5 #(
.INIT(32'hAAAAAAAB))
\z[22]_INST_0_i_40
(.I0(sel0[11]),
.I1(sel0[8]),
.I2(sel0[7]),
.I3(sel0[9]),
.I4(sel0[10]),
.O(\z[22]_INST_0_i_40_n_0 ));
LUT5 #(
.INIT(32'h00000010))
\z[22]_INST_0_i_5
(.I0(\z[22]_INST_0_i_21_n_0 ),
.I1(\z[22]_INST_0_i_20_n_0 ),
.I2(sel0[22]),
.I3(\z[22]_INST_0_i_19_n_0 ),
.I4(\z[22]_INST_0_i_18_n_0 ),
.O(\z[22]_INST_0_i_5_n_0 ));
LUT6 #(
.INIT(64'h000000000F000F0B))
\z[22]_INST_0_i_6
(.I0(sel0[14]),
.I1(sel0[13]),
.I2(sel0[17]),
.I3(sel0[16]),
.I4(sel0[15]),
.I5(\z[22]_INST_0_i_22_n_0 ),
.O(\z[22]_INST_0_i_6_n_0 ));
LUT6 #(
.INIT(64'hEEFFEEFFEEEEEEFE))
\z[22]_INST_0_i_7
(.I0(sel0[12]),
.I1(sel0[16]),
.I2(sel0[8]),
.I3(sel0[11]),
.I4(sel0[9]),
.I5(sel0[10]),
.O(\z[22]_INST_0_i_7_n_0 ));
LUT6 #(
.INIT(64'h000004000C000C00))
\z[22]_INST_0_i_8
(.I0(sel0[5]),
.I1(\z[22]_INST_0_i_23_n_0 ),
.I2(sel0[7]),
.I3(\z[22]_INST_0_i_24_n_0 ),
.I4(sel0[3]),
.I5(\z[22]_INST_0_i_25_n_0 ),
.O(\z[22]_INST_0_i_8_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT5 #(
.INIT(32'hAFAFAAAE))
\z[22]_INST_0_i_9
(.I0(sel0[22]),
.I1(sel0[18]),
.I2(sel0[21]),
.I3(sel0[19]),
.I4(sel0[20]),
.O(\z[22]_INST_0_i_9_n_0 ));
LUT6 #(
.INIT(64'h33333333F373B333))
\z[2]_INST_0
(.I0(\z[22]_INST_0_i_1_n_0 ),
.I1(\z[2]_INST_0_i_1_n_0 ),
.I2(\z[22]_INST_0_i_3_n_0 ),
.I3(\z[2]_INST_0_i_2_n_0 ),
.I4(\z[3]_INST_0_i_2_n_0 ),
.I5(z2),
.O(z[2]));
LUT5 #(
.INIT(32'h47FFFFFF))
\z[2]_INST_0_i_1
(.I0(\z[3]_INST_0_i_3_n_0 ),
.I1(\z[22]_INST_0_i_1_n_0 ),
.I2(\z[2]_INST_0_i_3_n_0 ),
.I3(\z[18]_INST_0_i_1_n_0 ),
.I4(z2),
.O(\z[2]_INST_0_i_1_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\z[2]_INST_0_i_2
(.I0(\z[8]_INST_0_i_5_n_0 ),
.I1(\z[4]_INST_0_i_5_n_0 ),
.I2(\z[22]_INST_0_i_18_n_0 ),
.I3(\z[6]_INST_0_i_5_n_0 ),
.I4(\z[22]_INST_0_i_21_n_0 ),
.I5(\z[2]_INST_0_i_4_n_0 ),
.O(\z[2]_INST_0_i_2_n_0 ));
LUT5 #(
.INIT(32'h00800000))
\z[2]_INST_0_i_3
(.I0(z0_carry_i_10_n_0),
.I1(z0_carry_i_8__0_n_0),
.I2(sel0[0]),
.I3(z0_carry_i_9_n_0),
.I4(z0_carry_i_11_n_0),
.O(\z[2]_INST_0_i_3_n_0 ));
LUT5 #(
.INIT(32'h30BB3088))
\z[2]_INST_0_i_4
(.I0(sel0[9]),
.I1(\z[22]_INST_0_i_19_n_0 ),
.I2(sel0[17]),
.I3(\z[22]_INST_0_i_20_n_0 ),
.I4(sel0[1]),
.O(\z[2]_INST_0_i_4_n_0 ));
LUT5 #(
.INIT(32'hE2E2E200))
\z[31]_INST_0
(.I0(y[31]),
.I1(large_mant1_carry_n_0),
.I2(x[31]),
.I3(\z[31]_INST_0_i_1_n_0 ),
.I4(\z[31]_INST_0_i_2_n_0 ),
.O(z[31]));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\z[31]_INST_0_i_1
(.I0(\z[31]_INST_0_i_3_n_0 ),
.I1(\z[31]_INST_0_i_4_n_0 ),
.I2(\z[31]_INST_0_i_5_n_0 ),
.I3(\z[31]_INST_0_i_6_n_0 ),
.I4(sel0[3]),
.I5(sel0[4]),
.O(\z[31]_INST_0_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\z[31]_INST_0_i_2
(.I0(sel0[22]),
.I1(\z[31]_INST_0_i_7_n_0 ),
.I2(sel0[21]),
.I3(sel0[23]),
.I4(sel0[19]),
.I5(sel0[20]),
.O(\z[31]_INST_0_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT4 #(
.INIT(16'hFFFE))
\z[31]_INST_0_i_3
(.I0(sel0[9]),
.I1(sel0[10]),
.I2(sel0[7]),
.I3(sel0[8]),
.O(\z[31]_INST_0_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT4 #(
.INIT(16'hFFFE))
\z[31]_INST_0_i_4
(.I0(sel0[13]),
.I1(sel0[14]),
.I2(sel0[11]),
.I3(sel0[12]),
.O(\z[31]_INST_0_i_4_n_0 ));
LUT4 #(
.INIT(16'hFFFE))
\z[31]_INST_0_i_5
(.I0(sel0[1]),
.I1(sel0[2]),
.I2(sign00__0_carry_n_7),
.I3(sel0[0]),
.O(\z[31]_INST_0_i_5_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair48" *)
LUT2 #(
.INIT(4'hE))
\z[31]_INST_0_i_6
(.I0(sel0[6]),
.I1(sel0[5]),
.O(\z[31]_INST_0_i_6_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT4 #(
.INIT(16'hFFFE))
\z[31]_INST_0_i_7
(.I0(sel0[17]),
.I1(sel0[18]),
.I2(sel0[15]),
.I3(sel0[16]),
.O(\z[31]_INST_0_i_7_n_0 ));
LUT6 #(
.INIT(64'h33333333F373B333))
\z[3]_INST_0
(.I0(\z[22]_INST_0_i_1_n_0 ),
.I1(\z[3]_INST_0_i_1_n_0 ),
.I2(\z[22]_INST_0_i_3_n_0 ),
.I3(\z[3]_INST_0_i_2_n_0 ),
.I4(\z[4]_INST_0_i_2_n_0 ),
.I5(z2),
.O(z[3]));
LUT5 #(
.INIT(32'h47FFFFFF))
\z[3]_INST_0_i_1
(.I0(\z[4]_INST_0_i_3_n_0 ),
.I1(\z[22]_INST_0_i_1_n_0 ),
.I2(\z[3]_INST_0_i_3_n_0 ),
.I3(\z[18]_INST_0_i_1_n_0 ),
.I4(z2),
.O(\z[3]_INST_0_i_1_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\z[3]_INST_0_i_2
(.I0(\z[9]_INST_0_i_6_n_0 ),
.I1(\z[5]_INST_0_i_5_n_0 ),
.I2(\z[22]_INST_0_i_18_n_0 ),
.I3(\z[7]_INST_0_i_5_n_0 ),
.I4(\z[22]_INST_0_i_21_n_0 ),
.I5(\z[3]_INST_0_i_4_n_0 ),
.O(\z[3]_INST_0_i_2_n_0 ));
LUT6 #(
.INIT(64'h0B08000000000000))
\z[3]_INST_0_i_3
(.I0(sel0[1]),
.I1(z0_carry_i_11_n_0),
.I2(z0_carry_i_9_n_0),
.I3(sign00__0_carry_n_7),
.I4(z0_carry_i_8__0_n_0),
.I5(z0_carry_i_10_n_0),
.O(\z[3]_INST_0_i_3_n_0 ));
LUT5 #(
.INIT(32'h30BB3088))
\z[3]_INST_0_i_4
(.I0(sel0[10]),
.I1(\z[22]_INST_0_i_19_n_0 ),
.I2(sel0[18]),
.I3(\z[22]_INST_0_i_20_n_0 ),
.I4(sel0[2]),
.O(\z[3]_INST_0_i_4_n_0 ));
LUT6 #(
.INIT(64'hCCCCCCCCF050A000))
\z[4]_INST_0
(.I0(\z[22]_INST_0_i_1_n_0 ),
.I1(z10_in[4]),
.I2(\z[22]_INST_0_i_3_n_0 ),
.I3(\z[4]_INST_0_i_2_n_0 ),
.I4(\z[5]_INST_0_i_2_n_0 ),
.I5(z2),
.O(z[4]));
LUT6 #(
.INIT(64'hA8A8A8080808A808))
\z[4]_INST_0_i_1
(.I0(\z[18]_INST_0_i_1_n_0 ),
.I1(\z[4]_INST_0_i_3_n_0 ),
.I2(\z[22]_INST_0_i_1_n_0 ),
.I3(\z[4]_INST_0_i_4_n_0 ),
.I4(z0_carry_i_11_n_0),
.I5(\z[6]_INST_0_i_4_n_0 ),
.O(z10_in[4]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\z[4]_INST_0_i_2
(.I0(\z[10]_INST_0_i_7_n_0 ),
.I1(\z[6]_INST_0_i_5_n_0 ),
.I2(\z[22]_INST_0_i_18_n_0 ),
.I3(\z[8]_INST_0_i_5_n_0 ),
.I4(\z[22]_INST_0_i_21_n_0 ),
.I5(\z[4]_INST_0_i_5_n_0 ),
.O(\z[4]_INST_0_i_2_n_0 ));
LUT6 #(
.INIT(64'h0B08000000000000))
\z[4]_INST_0_i_3
(.I0(sel0[2]),
.I1(z0_carry_i_11_n_0),
.I2(z0_carry_i_9_n_0),
.I3(sel0[0]),
.I4(z0_carry_i_8__0_n_0),
.I5(z0_carry_i_10_n_0),
.O(\z[4]_INST_0_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT4 #(
.INIT(16'h4000))
\z[4]_INST_0_i_4
(.I0(z0_carry_i_9_n_0),
.I1(sel0[1]),
.I2(z0_carry_i_8__0_n_0),
.I3(z0_carry_i_10_n_0),
.O(\z[4]_INST_0_i_4_n_0 ));
LUT5 #(
.INIT(32'h30BB3088))
\z[4]_INST_0_i_5
(.I0(sel0[11]),
.I1(\z[22]_INST_0_i_19_n_0 ),
.I2(sel0[19]),
.I3(\z[22]_INST_0_i_20_n_0 ),
.I4(sel0[3]),
.O(\z[4]_INST_0_i_5_n_0 ));
LUT6 #(
.INIT(64'hCCCCCCCCF050A000))
\z[5]_INST_0
(.I0(\z[22]_INST_0_i_1_n_0 ),
.I1(z10_in[5]),
.I2(\z[22]_INST_0_i_3_n_0 ),
.I3(\z[5]_INST_0_i_2_n_0 ),
.I4(\z[6]_INST_0_i_2_n_0 ),
.I5(z2),
.O(z[5]));
LUT6 #(
.INIT(64'hA8A8A8080808A808))
\z[5]_INST_0_i_1
(.I0(\z[18]_INST_0_i_1_n_0 ),
.I1(\z[5]_INST_0_i_3_n_0 ),
.I2(\z[22]_INST_0_i_1_n_0 ),
.I3(\z[5]_INST_0_i_4_n_0 ),
.I4(z0_carry_i_11_n_0),
.I5(\z[7]_INST_0_i_4_n_0 ),
.O(z10_in[5]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\z[5]_INST_0_i_2
(.I0(\z[11]_INST_0_i_5_n_0 ),
.I1(\z[7]_INST_0_i_5_n_0 ),
.I2(\z[22]_INST_0_i_18_n_0 ),
.I3(\z[9]_INST_0_i_6_n_0 ),
.I4(\z[22]_INST_0_i_21_n_0 ),
.I5(\z[5]_INST_0_i_5_n_0 ),
.O(\z[5]_INST_0_i_2_n_0 ));
LUT5 #(
.INIT(32'hAFA0C0C0))
\z[5]_INST_0_i_3
(.I0(\z[11]_INST_0_i_6_n_0 ),
.I1(\z[7]_INST_0_i_6_n_0 ),
.I2(z0_carry_i_11_n_0),
.I3(\z[9]_INST_0_i_7_n_0 ),
.I4(z0_carry_i_10_n_0),
.O(\z[5]_INST_0_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT4 #(
.INIT(16'h4000))
\z[5]_INST_0_i_4
(.I0(z0_carry_i_9_n_0),
.I1(sel0[2]),
.I2(z0_carry_i_8__0_n_0),
.I3(z0_carry_i_10_n_0),
.O(\z[5]_INST_0_i_4_n_0 ));
LUT5 #(
.INIT(32'h30BB3088))
\z[5]_INST_0_i_5
(.I0(sel0[12]),
.I1(\z[22]_INST_0_i_19_n_0 ),
.I2(sel0[20]),
.I3(\z[22]_INST_0_i_20_n_0 ),
.I4(sel0[4]),
.O(\z[5]_INST_0_i_5_n_0 ));
LUT6 #(
.INIT(64'hCCCCCCCCF050A000))
\z[6]_INST_0
(.I0(\z[22]_INST_0_i_1_n_0 ),
.I1(z10_in[6]),
.I2(\z[22]_INST_0_i_3_n_0 ),
.I3(\z[6]_INST_0_i_2_n_0 ),
.I4(\z[7]_INST_0_i_2_n_0 ),
.I5(z2),
.O(z[6]));
LUT6 #(
.INIT(64'hA8A8A8080808A808))
\z[6]_INST_0_i_1
(.I0(\z[18]_INST_0_i_1_n_0 ),
.I1(\z[6]_INST_0_i_3_n_0 ),
.I2(\z[22]_INST_0_i_1_n_0 ),
.I3(\z[6]_INST_0_i_4_n_0 ),
.I4(z0_carry_i_11_n_0),
.I5(\z[8]_INST_0_i_4_n_0 ),
.O(z10_in[6]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\z[6]_INST_0_i_2
(.I0(\z[12]_INST_0_i_5_n_0 ),
.I1(\z[8]_INST_0_i_5_n_0 ),
.I2(\z[22]_INST_0_i_18_n_0 ),
.I3(\z[10]_INST_0_i_7_n_0 ),
.I4(\z[22]_INST_0_i_21_n_0 ),
.I5(\z[6]_INST_0_i_5_n_0 ),
.O(\z[6]_INST_0_i_2_n_0 ));
LUT5 #(
.INIT(32'hAFA0C0C0))
\z[6]_INST_0_i_3
(.I0(\z[10]_INST_0_i_8_n_0 ),
.I1(\z[8]_INST_0_i_6_n_0 ),
.I2(z0_carry_i_11_n_0),
.I3(\z[10]_INST_0_i_10_n_0 ),
.I4(z0_carry_i_10_n_0),
.O(\z[6]_INST_0_i_3_n_0 ));
LUT5 #(
.INIT(32'h0000B080))
\z[6]_INST_0_i_4
(.I0(sel0[3]),
.I1(z0_carry_i_10_n_0),
.I2(z0_carry_i_8__0_n_0),
.I3(sign00__0_carry_n_7),
.I4(z0_carry_i_9_n_0),
.O(\z[6]_INST_0_i_4_n_0 ));
LUT5 #(
.INIT(32'h30BB3088))
\z[6]_INST_0_i_5
(.I0(sel0[13]),
.I1(\z[22]_INST_0_i_19_n_0 ),
.I2(sel0[21]),
.I3(\z[22]_INST_0_i_20_n_0 ),
.I4(sel0[5]),
.O(\z[6]_INST_0_i_5_n_0 ));
LUT6 #(
.INIT(64'hCCCCCCCCF050A000))
\z[7]_INST_0
(.I0(\z[22]_INST_0_i_1_n_0 ),
.I1(z10_in[7]),
.I2(\z[22]_INST_0_i_3_n_0 ),
.I3(\z[7]_INST_0_i_2_n_0 ),
.I4(\z[8]_INST_0_i_2_n_0 ),
.I5(z2),
.O(z[7]));
LUT6 #(
.INIT(64'hA8A8A8080808A808))
\z[7]_INST_0_i_1
(.I0(\z[18]_INST_0_i_1_n_0 ),
.I1(\z[7]_INST_0_i_3_n_0 ),
.I2(\z[22]_INST_0_i_1_n_0 ),
.I3(\z[7]_INST_0_i_4_n_0 ),
.I4(z0_carry_i_11_n_0),
.I5(\z[9]_INST_0_i_4_n_0 ),
.O(z10_in[7]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\z[7]_INST_0_i_2
(.I0(\z[9]_INST_0_i_5_n_0 ),
.I1(\z[9]_INST_0_i_6_n_0 ),
.I2(\z[22]_INST_0_i_18_n_0 ),
.I3(\z[11]_INST_0_i_5_n_0 ),
.I4(\z[22]_INST_0_i_21_n_0 ),
.I5(\z[7]_INST_0_i_5_n_0 ),
.O(\z[7]_INST_0_i_2_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\z[7]_INST_0_i_3
(.I0(\z[13]_INST_0_i_5_n_0 ),
.I1(\z[9]_INST_0_i_7_n_0 ),
.I2(z0_carry_i_11_n_0),
.I3(\z[11]_INST_0_i_6_n_0 ),
.I4(z0_carry_i_10_n_0),
.I5(\z[7]_INST_0_i_6_n_0 ),
.O(\z[7]_INST_0_i_3_n_0 ));
LUT5 #(
.INIT(32'h0000B080))
\z[7]_INST_0_i_4
(.I0(sel0[4]),
.I1(z0_carry_i_10_n_0),
.I2(z0_carry_i_8__0_n_0),
.I3(sel0[0]),
.I4(z0_carry_i_9_n_0),
.O(\z[7]_INST_0_i_4_n_0 ));
LUT5 #(
.INIT(32'h30BB3088))
\z[7]_INST_0_i_5
(.I0(sel0[14]),
.I1(\z[22]_INST_0_i_19_n_0 ),
.I2(sel0[22]),
.I3(\z[22]_INST_0_i_20_n_0 ),
.I4(sel0[6]),
.O(\z[7]_INST_0_i_5_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair43" *)
LUT3 #(
.INIT(8'h08))
\z[7]_INST_0_i_6
(.I0(\z[31]_INST_0_i_2_n_0 ),
.I1(sign00__0_carry_n_7),
.I2(z0_carry_i_9_n_0),
.O(\z[7]_INST_0_i_6_n_0 ));
LUT6 #(
.INIT(64'hCCCCCCCCF050A000))
\z[8]_INST_0
(.I0(\z[22]_INST_0_i_1_n_0 ),
.I1(z10_in[8]),
.I2(\z[22]_INST_0_i_3_n_0 ),
.I3(\z[8]_INST_0_i_2_n_0 ),
.I4(\z[9]_INST_0_i_2_n_0 ),
.I5(z2),
.O(z[8]));
LUT6 #(
.INIT(64'hA8A8A8080808A808))
\z[8]_INST_0_i_1
(.I0(\z[18]_INST_0_i_1_n_0 ),
.I1(\z[8]_INST_0_i_3_n_0 ),
.I2(\z[22]_INST_0_i_1_n_0 ),
.I3(\z[8]_INST_0_i_4_n_0 ),
.I4(z0_carry_i_11_n_0),
.I5(\z[10]_INST_0_i_4_n_0 ),
.O(z10_in[8]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\z[8]_INST_0_i_2
(.I0(\z[10]_INST_0_i_6_n_0 ),
.I1(\z[10]_INST_0_i_7_n_0 ),
.I2(\z[22]_INST_0_i_18_n_0 ),
.I3(\z[12]_INST_0_i_5_n_0 ),
.I4(\z[22]_INST_0_i_21_n_0 ),
.I5(\z[8]_INST_0_i_5_n_0 ),
.O(\z[8]_INST_0_i_2_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\z[8]_INST_0_i_3
(.I0(\z[10]_INST_0_i_9_n_0 ),
.I1(\z[10]_INST_0_i_10_n_0 ),
.I2(z0_carry_i_11_n_0),
.I3(\z[10]_INST_0_i_8_n_0 ),
.I4(z0_carry_i_10_n_0),
.I5(\z[8]_INST_0_i_6_n_0 ),
.O(\z[8]_INST_0_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT5 #(
.INIT(32'h0000B080))
\z[8]_INST_0_i_4
(.I0(sel0[5]),
.I1(z0_carry_i_10_n_0),
.I2(z0_carry_i_8__0_n_0),
.I3(sel0[1]),
.I4(z0_carry_i_9_n_0),
.O(\z[8]_INST_0_i_4_n_0 ));
LUT5 #(
.INIT(32'h30BB3088))
\z[8]_INST_0_i_5
(.I0(sel0[15]),
.I1(\z[22]_INST_0_i_19_n_0 ),
.I2(sel0[23]),
.I3(\z[22]_INST_0_i_20_n_0 ),
.I4(sel0[7]),
.O(\z[8]_INST_0_i_5_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair45" *)
LUT3 #(
.INIT(8'h08))
\z[8]_INST_0_i_6
(.I0(\z[31]_INST_0_i_2_n_0 ),
.I1(sel0[0]),
.I2(z0_carry_i_9_n_0),
.O(\z[8]_INST_0_i_6_n_0 ));
LUT6 #(
.INIT(64'hCCCCCCCCF050A000))
\z[9]_INST_0
(.I0(\z[22]_INST_0_i_1_n_0 ),
.I1(z10_in[9]),
.I2(\z[22]_INST_0_i_3_n_0 ),
.I3(\z[9]_INST_0_i_2_n_0 ),
.I4(\z[10]_INST_0_i_2_n_0 ),
.I5(z2),
.O(z[9]));
LUT6 #(
.INIT(64'hA8A8A8080808A808))
\z[9]_INST_0_i_1
(.I0(\z[18]_INST_0_i_1_n_0 ),
.I1(\z[9]_INST_0_i_3_n_0 ),
.I2(\z[22]_INST_0_i_1_n_0 ),
.I3(\z[9]_INST_0_i_4_n_0 ),
.I4(z0_carry_i_11_n_0),
.I5(\z[12]_INST_0_i_3_n_0 ),
.O(z10_in[9]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\z[9]_INST_0_i_2
(.I0(\z[11]_INST_0_i_4_n_0 ),
.I1(\z[11]_INST_0_i_5_n_0 ),
.I2(\z[22]_INST_0_i_18_n_0 ),
.I3(\z[9]_INST_0_i_5_n_0 ),
.I4(\z[22]_INST_0_i_21_n_0 ),
.I5(\z[9]_INST_0_i_6_n_0 ),
.O(\z[9]_INST_0_i_2_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\z[9]_INST_0_i_3
(.I0(\z[15]_INST_0_i_5_n_0 ),
.I1(\z[11]_INST_0_i_6_n_0 ),
.I2(z0_carry_i_11_n_0),
.I3(\z[13]_INST_0_i_5_n_0 ),
.I4(z0_carry_i_10_n_0),
.I5(\z[9]_INST_0_i_7_n_0 ),
.O(\z[9]_INST_0_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT5 #(
.INIT(32'h0000B080))
\z[9]_INST_0_i_4
(.I0(sel0[6]),
.I1(z0_carry_i_10_n_0),
.I2(z0_carry_i_8__0_n_0),
.I3(sel0[2]),
.I4(z0_carry_i_9_n_0),
.O(\z[9]_INST_0_i_4_n_0 ));
LUT6 #(
.INIT(64'hB800B8B8000000B8))
\z[9]_INST_0_i_5
(.I0(sel0[20]),
.I1(\z[22]_INST_0_i_19_n_0 ),
.I2(sel0[12]),
.I3(z2),
.I4(z3[4]),
.I5(z0_carry_i_8__0_n_0),
.O(\z[9]_INST_0_i_5_n_0 ));
LUT6 #(
.INIT(64'hB800B8B8000000B8))
\z[9]_INST_0_i_6
(.I0(sel0[16]),
.I1(\z[22]_INST_0_i_19_n_0 ),
.I2(sel0[8]),
.I3(z2),
.I4(z3[4]),
.I5(z0_carry_i_8__0_n_0),
.O(\z[9]_INST_0_i_6_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair46" *)
LUT3 #(
.INIT(8'h08))
\z[9]_INST_0_i_7
(.I0(\z[31]_INST_0_i_2_n_0 ),
.I1(sel0[1]),
.I2(z0_carry_i_9_n_0),
.O(\z[9]_INST_0_i_7_n_0 ));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// soc_system.v
// Generated using ACDS version 16.0 211
`timescale 1 ps / 1 ps
module soc_system (
input wire alt_vip_itc_0_clocked_video_vid_clk, // alt_vip_itc_0_clocked_video.vid_clk
output wire [31:0] alt_vip_itc_0_clocked_video_vid_data, // .vid_data
output wire alt_vip_itc_0_clocked_video_underflow, // .underflow
output wire alt_vip_itc_0_clocked_video_vid_datavalid, // .vid_datavalid
output wire alt_vip_itc_0_clocked_video_vid_v_sync, // .vid_v_sync
output wire alt_vip_itc_0_clocked_video_vid_h_sync, // .vid_h_sync
output wire alt_vip_itc_0_clocked_video_vid_f, // .vid_f
output wire alt_vip_itc_0_clocked_video_vid_h, // .vid_h
output wire alt_vip_itc_0_clocked_video_vid_v, // .vid_v
input wire clk_clk, // clk.clk
input wire clk_130_clk, // clk_130.clk
input wire [31:0] ece453_0_gpio_in_export, // ece453_0_gpio_in.export
output wire [31:0] ece453_0_gpio_out_export, // ece453_0_gpio_out.export
input wire hps_0_f2h_cold_reset_req_reset_n, // hps_0_f2h_cold_reset_req.reset_n
input wire hps_0_f2h_debug_reset_req_reset_n, // hps_0_f2h_debug_reset_req.reset_n
input wire [27:0] hps_0_f2h_stm_hw_events_stm_hwevents, // hps_0_f2h_stm_hw_events.stm_hwevents
input wire hps_0_f2h_warm_reset_req_reset_n, // hps_0_f2h_warm_reset_req.reset_n
output wire hps_0_h2f_reset_reset_n, // hps_0_h2f_reset.reset_n
output wire hps_0_hps_io_hps_io_emac1_inst_TX_CLK, // hps_0_hps_io.hps_io_emac1_inst_TX_CLK
output wire hps_0_hps_io_hps_io_emac1_inst_TXD0, // .hps_io_emac1_inst_TXD0
output wire hps_0_hps_io_hps_io_emac1_inst_TXD1, // .hps_io_emac1_inst_TXD1
output wire hps_0_hps_io_hps_io_emac1_inst_TXD2, // .hps_io_emac1_inst_TXD2
output wire hps_0_hps_io_hps_io_emac1_inst_TXD3, // .hps_io_emac1_inst_TXD3
input wire hps_0_hps_io_hps_io_emac1_inst_RXD0, // .hps_io_emac1_inst_RXD0
inout wire hps_0_hps_io_hps_io_emac1_inst_MDIO, // .hps_io_emac1_inst_MDIO
output wire hps_0_hps_io_hps_io_emac1_inst_MDC, // .hps_io_emac1_inst_MDC
input wire hps_0_hps_io_hps_io_emac1_inst_RX_CTL, // .hps_io_emac1_inst_RX_CTL
output wire hps_0_hps_io_hps_io_emac1_inst_TX_CTL, // .hps_io_emac1_inst_TX_CTL
input wire hps_0_hps_io_hps_io_emac1_inst_RX_CLK, // .hps_io_emac1_inst_RX_CLK
input wire hps_0_hps_io_hps_io_emac1_inst_RXD1, // .hps_io_emac1_inst_RXD1
input wire hps_0_hps_io_hps_io_emac1_inst_RXD2, // .hps_io_emac1_inst_RXD2
input wire hps_0_hps_io_hps_io_emac1_inst_RXD3, // .hps_io_emac1_inst_RXD3
inout wire hps_0_hps_io_hps_io_qspi_inst_IO0, // .hps_io_qspi_inst_IO0
inout wire hps_0_hps_io_hps_io_qspi_inst_IO1, // .hps_io_qspi_inst_IO1
inout wire hps_0_hps_io_hps_io_qspi_inst_IO2, // .hps_io_qspi_inst_IO2
inout wire hps_0_hps_io_hps_io_qspi_inst_IO3, // .hps_io_qspi_inst_IO3
output wire hps_0_hps_io_hps_io_qspi_inst_SS0, // .hps_io_qspi_inst_SS0
output wire hps_0_hps_io_hps_io_qspi_inst_CLK, // .hps_io_qspi_inst_CLK
inout wire hps_0_hps_io_hps_io_sdio_inst_CMD, // .hps_io_sdio_inst_CMD
inout wire hps_0_hps_io_hps_io_sdio_inst_D0, // .hps_io_sdio_inst_D0
inout wire hps_0_hps_io_hps_io_sdio_inst_D1, // .hps_io_sdio_inst_D1
output wire hps_0_hps_io_hps_io_sdio_inst_CLK, // .hps_io_sdio_inst_CLK
inout wire hps_0_hps_io_hps_io_sdio_inst_D2, // .hps_io_sdio_inst_D2
inout wire hps_0_hps_io_hps_io_sdio_inst_D3, // .hps_io_sdio_inst_D3
inout wire hps_0_hps_io_hps_io_usb1_inst_D0, // .hps_io_usb1_inst_D0
inout wire hps_0_hps_io_hps_io_usb1_inst_D1, // .hps_io_usb1_inst_D1
inout wire hps_0_hps_io_hps_io_usb1_inst_D2, // .hps_io_usb1_inst_D2
inout wire hps_0_hps_io_hps_io_usb1_inst_D3, // .hps_io_usb1_inst_D3
inout wire hps_0_hps_io_hps_io_usb1_inst_D4, // .hps_io_usb1_inst_D4
inout wire hps_0_hps_io_hps_io_usb1_inst_D5, // .hps_io_usb1_inst_D5
inout wire hps_0_hps_io_hps_io_usb1_inst_D6, // .hps_io_usb1_inst_D6
inout wire hps_0_hps_io_hps_io_usb1_inst_D7, // .hps_io_usb1_inst_D7
input wire hps_0_hps_io_hps_io_usb1_inst_CLK, // .hps_io_usb1_inst_CLK
output wire hps_0_hps_io_hps_io_usb1_inst_STP, // .hps_io_usb1_inst_STP
input wire hps_0_hps_io_hps_io_usb1_inst_DIR, // .hps_io_usb1_inst_DIR
input wire hps_0_hps_io_hps_io_usb1_inst_NXT, // .hps_io_usb1_inst_NXT
output wire hps_0_hps_io_hps_io_spim1_inst_CLK, // .hps_io_spim1_inst_CLK
output wire hps_0_hps_io_hps_io_spim1_inst_MOSI, // .hps_io_spim1_inst_MOSI
input wire hps_0_hps_io_hps_io_spim1_inst_MISO, // .hps_io_spim1_inst_MISO
output wire hps_0_hps_io_hps_io_spim1_inst_SS0, // .hps_io_spim1_inst_SS0
input wire hps_0_hps_io_hps_io_uart0_inst_RX, // .hps_io_uart0_inst_RX
output wire hps_0_hps_io_hps_io_uart0_inst_TX, // .hps_io_uart0_inst_TX
inout wire hps_0_hps_io_hps_io_i2c0_inst_SDA, // .hps_io_i2c0_inst_SDA
inout wire hps_0_hps_io_hps_io_i2c0_inst_SCL, // .hps_io_i2c0_inst_SCL
inout wire hps_0_hps_io_hps_io_i2c1_inst_SDA, // .hps_io_i2c1_inst_SDA
inout wire hps_0_hps_io_hps_io_i2c1_inst_SCL, // .hps_io_i2c1_inst_SCL
inout wire hps_0_hps_io_hps_io_gpio_inst_GPIO09, // .hps_io_gpio_inst_GPIO09
inout wire hps_0_hps_io_hps_io_gpio_inst_GPIO35, // .hps_io_gpio_inst_GPIO35
inout wire hps_0_hps_io_hps_io_gpio_inst_GPIO40, // .hps_io_gpio_inst_GPIO40
inout wire hps_0_hps_io_hps_io_gpio_inst_GPIO48, // .hps_io_gpio_inst_GPIO48
inout wire hps_0_hps_io_hps_io_gpio_inst_GPIO53, // .hps_io_gpio_inst_GPIO53
inout wire hps_0_hps_io_hps_io_gpio_inst_GPIO54, // .hps_io_gpio_inst_GPIO54
inout wire hps_0_hps_io_hps_io_gpio_inst_GPIO61, // .hps_io_gpio_inst_GPIO61
output wire hps_0_i2c2_out_data, // hps_0_i2c2.out_data
input wire hps_0_i2c2_sda, // .sda
output wire hps_0_i2c2_clk_clk, // hps_0_i2c2_clk.clk
input wire hps_0_i2c2_scl_in_clk, // hps_0_i2c2_scl_in.clk
output wire hps_0_spim0_txd, // hps_0_spim0.txd
input wire hps_0_spim0_rxd, // .rxd
input wire hps_0_spim0_ss_in_n, // .ss_in_n
output wire hps_0_spim0_ssi_oe_n, // .ssi_oe_n
output wire hps_0_spim0_ss_0_n, // .ss_0_n
output wire hps_0_spim0_ss_1_n, // .ss_1_n
output wire hps_0_spim0_ss_2_n, // .ss_2_n
output wire hps_0_spim0_ss_3_n, // .ss_3_n
output wire hps_0_spim0_sclk_out_clk, // hps_0_spim0_sclk_out.clk
input wire hps_0_uart1_cts, // hps_0_uart1.cts
input wire hps_0_uart1_dsr, // .dsr
input wire hps_0_uart1_dcd, // .dcd
input wire hps_0_uart1_ri, // .ri
output wire hps_0_uart1_dtr, // .dtr
output wire hps_0_uart1_rts, // .rts
output wire hps_0_uart1_out1_n, // .out1_n
output wire hps_0_uart1_out2_n, // .out2_n
input wire hps_0_uart1_rxd, // .rxd
output wire hps_0_uart1_txd, // .txd
output wire [14:0] memory_mem_a, // memory.mem_a
output wire [2:0] memory_mem_ba, // .mem_ba
output wire memory_mem_ck, // .mem_ck
output wire memory_mem_ck_n, // .mem_ck_n
output wire memory_mem_cke, // .mem_cke
output wire memory_mem_cs_n, // .mem_cs_n
output wire memory_mem_ras_n, // .mem_ras_n
output wire memory_mem_cas_n, // .mem_cas_n
output wire memory_mem_we_n, // .mem_we_n
output wire memory_mem_reset_n, // .mem_reset_n
inout wire [31:0] memory_mem_dq, // .mem_dq
inout wire [3:0] memory_mem_dqs, // .mem_dqs
inout wire [3:0] memory_mem_dqs_n, // .mem_dqs_n
output wire memory_mem_odt, // .mem_odt
output wire [3:0] memory_mem_dm, // .mem_dm
input wire memory_oct_rzqin, // .oct_rzqin
input wire reset_reset_n // reset.reset_n
);
wire alt_vip_vfr_vga_avalon_streaming_source_valid; // alt_vip_vfr_vga:dout_valid -> alt_vip_itc_0:is_valid
wire [31:0] alt_vip_vfr_vga_avalon_streaming_source_data; // alt_vip_vfr_vga:dout_data -> alt_vip_itc_0:is_data
wire alt_vip_vfr_vga_avalon_streaming_source_ready; // alt_vip_itc_0:is_ready -> alt_vip_vfr_vga:dout_ready
wire alt_vip_vfr_vga_avalon_streaming_source_startofpacket; // alt_vip_vfr_vga:dout_startofpacket -> alt_vip_itc_0:is_sop
wire alt_vip_vfr_vga_avalon_streaming_source_endofpacket; // alt_vip_vfr_vga:dout_endofpacket -> alt_vip_itc_0:is_eop
wire [127:0] alt_vip_vfr_vga_avalon_master_readdata; // mm_interconnect_0:alt_vip_vfr_vga_avalon_master_readdata -> alt_vip_vfr_vga:master_readdata
wire alt_vip_vfr_vga_avalon_master_waitrequest; // mm_interconnect_0:alt_vip_vfr_vga_avalon_master_waitrequest -> alt_vip_vfr_vga:master_waitrequest
wire [31:0] alt_vip_vfr_vga_avalon_master_address; // alt_vip_vfr_vga:master_address -> mm_interconnect_0:alt_vip_vfr_vga_avalon_master_address
wire alt_vip_vfr_vga_avalon_master_read; // alt_vip_vfr_vga:master_read -> mm_interconnect_0:alt_vip_vfr_vga_avalon_master_read
wire alt_vip_vfr_vga_avalon_master_readdatavalid; // mm_interconnect_0:alt_vip_vfr_vga_avalon_master_readdatavalid -> alt_vip_vfr_vga:master_readdatavalid
wire [5:0] alt_vip_vfr_vga_avalon_master_burstcount; // alt_vip_vfr_vga:master_burstcount -> mm_interconnect_0:alt_vip_vfr_vga_avalon_master_burstcount
wire [31:0] master_secure_master_readdata; // mm_interconnect_0:master_secure_master_readdata -> master_secure:master_readdata
wire master_secure_master_waitrequest; // mm_interconnect_0:master_secure_master_waitrequest -> master_secure:master_waitrequest
wire [31:0] master_secure_master_address; // master_secure:master_address -> mm_interconnect_0:master_secure_master_address
wire master_secure_master_read; // master_secure:master_read -> mm_interconnect_0:master_secure_master_read
wire [3:0] master_secure_master_byteenable; // master_secure:master_byteenable -> mm_interconnect_0:master_secure_master_byteenable
wire master_secure_master_readdatavalid; // mm_interconnect_0:master_secure_master_readdatavalid -> master_secure:master_readdatavalid
wire master_secure_master_write; // master_secure:master_write -> mm_interconnect_0:master_secure_master_write
wire [31:0] master_secure_master_writedata; // master_secure:master_writedata -> mm_interconnect_0:master_secure_master_writedata
wire [1:0] mm_interconnect_0_hps_0_f2h_axi_slave_awburst; // mm_interconnect_0:hps_0_f2h_axi_slave_awburst -> hps_0:f2h_AWBURST
wire [4:0] mm_interconnect_0_hps_0_f2h_axi_slave_awuser; // mm_interconnect_0:hps_0_f2h_axi_slave_awuser -> hps_0:f2h_AWUSER
wire [3:0] mm_interconnect_0_hps_0_f2h_axi_slave_arlen; // mm_interconnect_0:hps_0_f2h_axi_slave_arlen -> hps_0:f2h_ARLEN
wire [15:0] mm_interconnect_0_hps_0_f2h_axi_slave_wstrb; // mm_interconnect_0:hps_0_f2h_axi_slave_wstrb -> hps_0:f2h_WSTRB
wire mm_interconnect_0_hps_0_f2h_axi_slave_wready; // hps_0:f2h_WREADY -> mm_interconnect_0:hps_0_f2h_axi_slave_wready
wire [7:0] mm_interconnect_0_hps_0_f2h_axi_slave_rid; // hps_0:f2h_RID -> mm_interconnect_0:hps_0_f2h_axi_slave_rid
wire mm_interconnect_0_hps_0_f2h_axi_slave_rready; // mm_interconnect_0:hps_0_f2h_axi_slave_rready -> hps_0:f2h_RREADY
wire [3:0] mm_interconnect_0_hps_0_f2h_axi_slave_awlen; // mm_interconnect_0:hps_0_f2h_axi_slave_awlen -> hps_0:f2h_AWLEN
wire [7:0] mm_interconnect_0_hps_0_f2h_axi_slave_wid; // mm_interconnect_0:hps_0_f2h_axi_slave_wid -> hps_0:f2h_WID
wire [3:0] mm_interconnect_0_hps_0_f2h_axi_slave_arcache; // mm_interconnect_0:hps_0_f2h_axi_slave_arcache -> hps_0:f2h_ARCACHE
wire mm_interconnect_0_hps_0_f2h_axi_slave_wvalid; // mm_interconnect_0:hps_0_f2h_axi_slave_wvalid -> hps_0:f2h_WVALID
wire [31:0] mm_interconnect_0_hps_0_f2h_axi_slave_araddr; // mm_interconnect_0:hps_0_f2h_axi_slave_araddr -> hps_0:f2h_ARADDR
wire [2:0] mm_interconnect_0_hps_0_f2h_axi_slave_arprot; // mm_interconnect_0:hps_0_f2h_axi_slave_arprot -> hps_0:f2h_ARPROT
wire [2:0] mm_interconnect_0_hps_0_f2h_axi_slave_awprot; // mm_interconnect_0:hps_0_f2h_axi_slave_awprot -> hps_0:f2h_AWPROT
wire [127:0] mm_interconnect_0_hps_0_f2h_axi_slave_wdata; // mm_interconnect_0:hps_0_f2h_axi_slave_wdata -> hps_0:f2h_WDATA
wire mm_interconnect_0_hps_0_f2h_axi_slave_arvalid; // mm_interconnect_0:hps_0_f2h_axi_slave_arvalid -> hps_0:f2h_ARVALID
wire [3:0] mm_interconnect_0_hps_0_f2h_axi_slave_awcache; // mm_interconnect_0:hps_0_f2h_axi_slave_awcache -> hps_0:f2h_AWCACHE
wire [7:0] mm_interconnect_0_hps_0_f2h_axi_slave_arid; // mm_interconnect_0:hps_0_f2h_axi_slave_arid -> hps_0:f2h_ARID
wire [1:0] mm_interconnect_0_hps_0_f2h_axi_slave_arlock; // mm_interconnect_0:hps_0_f2h_axi_slave_arlock -> hps_0:f2h_ARLOCK
wire [1:0] mm_interconnect_0_hps_0_f2h_axi_slave_awlock; // mm_interconnect_0:hps_0_f2h_axi_slave_awlock -> hps_0:f2h_AWLOCK
wire [31:0] mm_interconnect_0_hps_0_f2h_axi_slave_awaddr; // mm_interconnect_0:hps_0_f2h_axi_slave_awaddr -> hps_0:f2h_AWADDR
wire [1:0] mm_interconnect_0_hps_0_f2h_axi_slave_bresp; // hps_0:f2h_BRESP -> mm_interconnect_0:hps_0_f2h_axi_slave_bresp
wire mm_interconnect_0_hps_0_f2h_axi_slave_arready; // hps_0:f2h_ARREADY -> mm_interconnect_0:hps_0_f2h_axi_slave_arready
wire [127:0] mm_interconnect_0_hps_0_f2h_axi_slave_rdata; // hps_0:f2h_RDATA -> mm_interconnect_0:hps_0_f2h_axi_slave_rdata
wire mm_interconnect_0_hps_0_f2h_axi_slave_awready; // hps_0:f2h_AWREADY -> mm_interconnect_0:hps_0_f2h_axi_slave_awready
wire [1:0] mm_interconnect_0_hps_0_f2h_axi_slave_arburst; // mm_interconnect_0:hps_0_f2h_axi_slave_arburst -> hps_0:f2h_ARBURST
wire [2:0] mm_interconnect_0_hps_0_f2h_axi_slave_arsize; // mm_interconnect_0:hps_0_f2h_axi_slave_arsize -> hps_0:f2h_ARSIZE
wire mm_interconnect_0_hps_0_f2h_axi_slave_bready; // mm_interconnect_0:hps_0_f2h_axi_slave_bready -> hps_0:f2h_BREADY
wire mm_interconnect_0_hps_0_f2h_axi_slave_rlast; // hps_0:f2h_RLAST -> mm_interconnect_0:hps_0_f2h_axi_slave_rlast
wire mm_interconnect_0_hps_0_f2h_axi_slave_wlast; // mm_interconnect_0:hps_0_f2h_axi_slave_wlast -> hps_0:f2h_WLAST
wire [1:0] mm_interconnect_0_hps_0_f2h_axi_slave_rresp; // hps_0:f2h_RRESP -> mm_interconnect_0:hps_0_f2h_axi_slave_rresp
wire [7:0] mm_interconnect_0_hps_0_f2h_axi_slave_awid; // mm_interconnect_0:hps_0_f2h_axi_slave_awid -> hps_0:f2h_AWID
wire [7:0] mm_interconnect_0_hps_0_f2h_axi_slave_bid; // hps_0:f2h_BID -> mm_interconnect_0:hps_0_f2h_axi_slave_bid
wire mm_interconnect_0_hps_0_f2h_axi_slave_bvalid; // hps_0:f2h_BVALID -> mm_interconnect_0:hps_0_f2h_axi_slave_bvalid
wire [2:0] mm_interconnect_0_hps_0_f2h_axi_slave_awsize; // mm_interconnect_0:hps_0_f2h_axi_slave_awsize -> hps_0:f2h_AWSIZE
wire mm_interconnect_0_hps_0_f2h_axi_slave_awvalid; // mm_interconnect_0:hps_0_f2h_axi_slave_awvalid -> hps_0:f2h_AWVALID
wire [4:0] mm_interconnect_0_hps_0_f2h_axi_slave_aruser; // mm_interconnect_0:hps_0_f2h_axi_slave_aruser -> hps_0:f2h_ARUSER
wire mm_interconnect_0_hps_0_f2h_axi_slave_rvalid; // hps_0:f2h_RVALID -> mm_interconnect_0:hps_0_f2h_axi_slave_rvalid
wire [1:0] hps_0_h2f_lw_axi_master_awburst; // hps_0:h2f_lw_AWBURST -> mm_interconnect_1:hps_0_h2f_lw_axi_master_awburst
wire [3:0] hps_0_h2f_lw_axi_master_arlen; // hps_0:h2f_lw_ARLEN -> mm_interconnect_1:hps_0_h2f_lw_axi_master_arlen
wire [3:0] hps_0_h2f_lw_axi_master_wstrb; // hps_0:h2f_lw_WSTRB -> mm_interconnect_1:hps_0_h2f_lw_axi_master_wstrb
wire hps_0_h2f_lw_axi_master_wready; // mm_interconnect_1:hps_0_h2f_lw_axi_master_wready -> hps_0:h2f_lw_WREADY
wire [11:0] hps_0_h2f_lw_axi_master_rid; // mm_interconnect_1:hps_0_h2f_lw_axi_master_rid -> hps_0:h2f_lw_RID
wire hps_0_h2f_lw_axi_master_rready; // hps_0:h2f_lw_RREADY -> mm_interconnect_1:hps_0_h2f_lw_axi_master_rready
wire [3:0] hps_0_h2f_lw_axi_master_awlen; // hps_0:h2f_lw_AWLEN -> mm_interconnect_1:hps_0_h2f_lw_axi_master_awlen
wire [11:0] hps_0_h2f_lw_axi_master_wid; // hps_0:h2f_lw_WID -> mm_interconnect_1:hps_0_h2f_lw_axi_master_wid
wire [3:0] hps_0_h2f_lw_axi_master_arcache; // hps_0:h2f_lw_ARCACHE -> mm_interconnect_1:hps_0_h2f_lw_axi_master_arcache
wire hps_0_h2f_lw_axi_master_wvalid; // hps_0:h2f_lw_WVALID -> mm_interconnect_1:hps_0_h2f_lw_axi_master_wvalid
wire [20:0] hps_0_h2f_lw_axi_master_araddr; // hps_0:h2f_lw_ARADDR -> mm_interconnect_1:hps_0_h2f_lw_axi_master_araddr
wire [2:0] hps_0_h2f_lw_axi_master_arprot; // hps_0:h2f_lw_ARPROT -> mm_interconnect_1:hps_0_h2f_lw_axi_master_arprot
wire [2:0] hps_0_h2f_lw_axi_master_awprot; // hps_0:h2f_lw_AWPROT -> mm_interconnect_1:hps_0_h2f_lw_axi_master_awprot
wire [31:0] hps_0_h2f_lw_axi_master_wdata; // hps_0:h2f_lw_WDATA -> mm_interconnect_1:hps_0_h2f_lw_axi_master_wdata
wire hps_0_h2f_lw_axi_master_arvalid; // hps_0:h2f_lw_ARVALID -> mm_interconnect_1:hps_0_h2f_lw_axi_master_arvalid
wire [3:0] hps_0_h2f_lw_axi_master_awcache; // hps_0:h2f_lw_AWCACHE -> mm_interconnect_1:hps_0_h2f_lw_axi_master_awcache
wire [11:0] hps_0_h2f_lw_axi_master_arid; // hps_0:h2f_lw_ARID -> mm_interconnect_1:hps_0_h2f_lw_axi_master_arid
wire [1:0] hps_0_h2f_lw_axi_master_arlock; // hps_0:h2f_lw_ARLOCK -> mm_interconnect_1:hps_0_h2f_lw_axi_master_arlock
wire [1:0] hps_0_h2f_lw_axi_master_awlock; // hps_0:h2f_lw_AWLOCK -> mm_interconnect_1:hps_0_h2f_lw_axi_master_awlock
wire [20:0] hps_0_h2f_lw_axi_master_awaddr; // hps_0:h2f_lw_AWADDR -> mm_interconnect_1:hps_0_h2f_lw_axi_master_awaddr
wire [1:0] hps_0_h2f_lw_axi_master_bresp; // mm_interconnect_1:hps_0_h2f_lw_axi_master_bresp -> hps_0:h2f_lw_BRESP
wire hps_0_h2f_lw_axi_master_arready; // mm_interconnect_1:hps_0_h2f_lw_axi_master_arready -> hps_0:h2f_lw_ARREADY
wire [31:0] hps_0_h2f_lw_axi_master_rdata; // mm_interconnect_1:hps_0_h2f_lw_axi_master_rdata -> hps_0:h2f_lw_RDATA
wire hps_0_h2f_lw_axi_master_awready; // mm_interconnect_1:hps_0_h2f_lw_axi_master_awready -> hps_0:h2f_lw_AWREADY
wire [1:0] hps_0_h2f_lw_axi_master_arburst; // hps_0:h2f_lw_ARBURST -> mm_interconnect_1:hps_0_h2f_lw_axi_master_arburst
wire [2:0] hps_0_h2f_lw_axi_master_arsize; // hps_0:h2f_lw_ARSIZE -> mm_interconnect_1:hps_0_h2f_lw_axi_master_arsize
wire hps_0_h2f_lw_axi_master_bready; // hps_0:h2f_lw_BREADY -> mm_interconnect_1:hps_0_h2f_lw_axi_master_bready
wire hps_0_h2f_lw_axi_master_rlast; // mm_interconnect_1:hps_0_h2f_lw_axi_master_rlast -> hps_0:h2f_lw_RLAST
wire hps_0_h2f_lw_axi_master_wlast; // hps_0:h2f_lw_WLAST -> mm_interconnect_1:hps_0_h2f_lw_axi_master_wlast
wire [1:0] hps_0_h2f_lw_axi_master_rresp; // mm_interconnect_1:hps_0_h2f_lw_axi_master_rresp -> hps_0:h2f_lw_RRESP
wire [11:0] hps_0_h2f_lw_axi_master_awid; // hps_0:h2f_lw_AWID -> mm_interconnect_1:hps_0_h2f_lw_axi_master_awid
wire [11:0] hps_0_h2f_lw_axi_master_bid; // mm_interconnect_1:hps_0_h2f_lw_axi_master_bid -> hps_0:h2f_lw_BID
wire hps_0_h2f_lw_axi_master_bvalid; // mm_interconnect_1:hps_0_h2f_lw_axi_master_bvalid -> hps_0:h2f_lw_BVALID
wire [2:0] hps_0_h2f_lw_axi_master_awsize; // hps_0:h2f_lw_AWSIZE -> mm_interconnect_1:hps_0_h2f_lw_axi_master_awsize
wire hps_0_h2f_lw_axi_master_awvalid; // hps_0:h2f_lw_AWVALID -> mm_interconnect_1:hps_0_h2f_lw_axi_master_awvalid
wire hps_0_h2f_lw_axi_master_rvalid; // mm_interconnect_1:hps_0_h2f_lw_axi_master_rvalid -> hps_0:h2f_lw_RVALID
wire [31:0] master_non_sec_master_readdata; // mm_interconnect_1:master_non_sec_master_readdata -> master_non_sec:master_readdata
wire master_non_sec_master_waitrequest; // mm_interconnect_1:master_non_sec_master_waitrequest -> master_non_sec:master_waitrequest
wire [31:0] master_non_sec_master_address; // master_non_sec:master_address -> mm_interconnect_1:master_non_sec_master_address
wire master_non_sec_master_read; // master_non_sec:master_read -> mm_interconnect_1:master_non_sec_master_read
wire [3:0] master_non_sec_master_byteenable; // master_non_sec:master_byteenable -> mm_interconnect_1:master_non_sec_master_byteenable
wire master_non_sec_master_readdatavalid; // mm_interconnect_1:master_non_sec_master_readdatavalid -> master_non_sec:master_readdatavalid
wire master_non_sec_master_write; // master_non_sec:master_write -> mm_interconnect_1:master_non_sec_master_write
wire [31:0] master_non_sec_master_writedata; // master_non_sec:master_writedata -> mm_interconnect_1:master_non_sec_master_writedata
wire mm_interconnect_1_jtag_uart_avalon_jtag_slave_chipselect; // mm_interconnect_1:jtag_uart_avalon_jtag_slave_chipselect -> jtag_uart:av_chipselect
wire [31:0] mm_interconnect_1_jtag_uart_avalon_jtag_slave_readdata; // jtag_uart:av_readdata -> mm_interconnect_1:jtag_uart_avalon_jtag_slave_readdata
wire mm_interconnect_1_jtag_uart_avalon_jtag_slave_waitrequest; // jtag_uart:av_waitrequest -> mm_interconnect_1:jtag_uart_avalon_jtag_slave_waitrequest
wire [0:0] mm_interconnect_1_jtag_uart_avalon_jtag_slave_address; // mm_interconnect_1:jtag_uart_avalon_jtag_slave_address -> jtag_uart:av_address
wire mm_interconnect_1_jtag_uart_avalon_jtag_slave_read; // mm_interconnect_1:jtag_uart_avalon_jtag_slave_read -> jtag_uart:av_read_n
wire mm_interconnect_1_jtag_uart_avalon_jtag_slave_write; // mm_interconnect_1:jtag_uart_avalon_jtag_slave_write -> jtag_uart:av_write_n
wire [31:0] mm_interconnect_1_jtag_uart_avalon_jtag_slave_writedata; // mm_interconnect_1:jtag_uart_avalon_jtag_slave_writedata -> jtag_uart:av_writedata
wire [31:0] mm_interconnect_1_alt_vip_vfr_vga_avalon_slave_readdata; // alt_vip_vfr_vga:slave_readdata -> mm_interconnect_1:alt_vip_vfr_vga_avalon_slave_readdata
wire [4:0] mm_interconnect_1_alt_vip_vfr_vga_avalon_slave_address; // mm_interconnect_1:alt_vip_vfr_vga_avalon_slave_address -> alt_vip_vfr_vga:slave_address
wire mm_interconnect_1_alt_vip_vfr_vga_avalon_slave_read; // mm_interconnect_1:alt_vip_vfr_vga_avalon_slave_read -> alt_vip_vfr_vga:slave_read
wire mm_interconnect_1_alt_vip_vfr_vga_avalon_slave_write; // mm_interconnect_1:alt_vip_vfr_vga_avalon_slave_write -> alt_vip_vfr_vga:slave_write
wire [31:0] mm_interconnect_1_alt_vip_vfr_vga_avalon_slave_writedata; // mm_interconnect_1:alt_vip_vfr_vga_avalon_slave_writedata -> alt_vip_vfr_vga:slave_writedata
wire [31:0] mm_interconnect_1_ece453_0_avalon_slave_0_readdata; // ece453_0:slave_readdata -> mm_interconnect_1:ece453_0_avalon_slave_0_readdata
wire [3:0] mm_interconnect_1_ece453_0_avalon_slave_0_address; // mm_interconnect_1:ece453_0_avalon_slave_0_address -> ece453_0:slave_address
wire mm_interconnect_1_ece453_0_avalon_slave_0_read; // mm_interconnect_1:ece453_0_avalon_slave_0_read -> ece453_0:slave_read
wire [3:0] mm_interconnect_1_ece453_0_avalon_slave_0_byteenable; // mm_interconnect_1:ece453_0_avalon_slave_0_byteenable -> ece453_0:slave_byteenable
wire mm_interconnect_1_ece453_0_avalon_slave_0_write; // mm_interconnect_1:ece453_0_avalon_slave_0_write -> ece453_0:slave_write
wire [31:0] mm_interconnect_1_ece453_0_avalon_slave_0_writedata; // mm_interconnect_1:ece453_0_avalon_slave_0_writedata -> ece453_0:slave_writedata
wire [31:0] mm_interconnect_1_sysid_qsys_control_slave_readdata; // sysid_qsys:readdata -> mm_interconnect_1:sysid_qsys_control_slave_readdata
wire [0:0] mm_interconnect_1_sysid_qsys_control_slave_address; // mm_interconnect_1:sysid_qsys_control_slave_address -> sysid_qsys:address
wire [31:0] mm_interconnect_1_intr_capturer_0_avalon_slave_0_readdata; // intr_capturer_0:rddata -> mm_interconnect_1:intr_capturer_0_avalon_slave_0_readdata
wire [0:0] mm_interconnect_1_intr_capturer_0_avalon_slave_0_address; // mm_interconnect_1:intr_capturer_0_avalon_slave_0_address -> intr_capturer_0:addr
wire mm_interconnect_1_intr_capturer_0_avalon_slave_0_read; // mm_interconnect_1:intr_capturer_0_avalon_slave_0_read -> intr_capturer_0:read
wire [31:0] hps_0_f2h_irq0_irq; // irq_mapper:sender_irq -> hps_0:f2h_irq_p0
wire [31:0] hps_0_f2h_irq1_irq; // irq_mapper_001:sender_irq -> hps_0:f2h_irq_p1
wire [31:0] intr_capturer_0_interrupt_receiver_irq; // irq_mapper_002:sender_irq -> intr_capturer_0:interrupt_in
wire irq_mapper_receiver0_irq; // ece453_0:irq_out -> [irq_mapper:receiver0_irq, irq_mapper_002:receiver0_irq]
wire irq_mapper_receiver1_irq; // jtag_uart:av_irq -> [irq_mapper:receiver1_irq, irq_mapper_002:receiver1_irq]
wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [alt_vip_itc_0:rst, alt_vip_vfr_vga:reset, mm_interconnect_1:alt_vip_vfr_vga_clock_reset_reset_reset_bridge_in_reset_reset]
wire rst_controller_001_reset_out_reset; // rst_controller_001:reset_out -> [alt_vip_vfr_vga:master_reset, intr_capturer_0:rst_n, irq_mapper_002:reset, jtag_uart:rst_n, mm_interconnect_0:alt_vip_vfr_vga_clock_master_reset_reset_bridge_in_reset_reset, mm_interconnect_0:master_secure_clk_reset_reset_bridge_in_reset_reset, mm_interconnect_1:jtag_uart_reset_reset_bridge_in_reset_reset, mm_interconnect_1:master_non_sec_clk_reset_reset_bridge_in_reset_reset, sysid_qsys:reset_n]
wire rst_controller_002_reset_out_reset; // rst_controller_002:reset_out -> [ece453_0:reset, mm_interconnect_1:ece453_0_clock_reset_reset_bridge_in_reset_reset]
wire rst_controller_003_reset_out_reset; // rst_controller_003:reset_out -> [mm_interconnect_0:hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset_reset, mm_interconnect_1:hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset]
alt_vipitc131_IS2Vid #(
.NUMBER_OF_COLOUR_PLANES (4),
.COLOUR_PLANES_ARE_IN_PARALLEL (1),
.BPS (8),
.INTERLACED (0),
.H_ACTIVE_PIXELS (1024),
.V_ACTIVE_LINES (768),
.ACCEPT_COLOURS_IN_SEQ (0),
.FIFO_DEPTH (1920),
.CLOCKS_ARE_SAME (0),
.USE_CONTROL (0),
.NO_OF_MODES (1),
.THRESHOLD (1919),
.STD_WIDTH (1),
.GENERATE_SYNC (0),
.USE_EMBEDDED_SYNCS (0),
.AP_LINE (0),
.V_BLANK (0),
.H_BLANK (0),
.H_SYNC_LENGTH (136),
.H_FRONT_PORCH (24),
.H_BACK_PORCH (160),
.V_SYNC_LENGTH (6),
.V_FRONT_PORCH (3),
.V_BACK_PORCH (29),
.F_RISING_EDGE (0),
.F_FALLING_EDGE (0),
.FIELD0_V_RISING_EDGE (0),
.FIELD0_V_BLANK (0),
.FIELD0_V_SYNC_LENGTH (0),
.FIELD0_V_FRONT_PORCH (0),
.FIELD0_V_BACK_PORCH (0),
.ANC_LINE (0),
.FIELD0_ANC_LINE (0)
) alt_vip_itc_0 (
.is_clk (clk_130_clk), // is_clk_rst.clk
.rst (rst_controller_reset_out_reset), // is_clk_rst_reset.reset
.is_data (alt_vip_vfr_vga_avalon_streaming_source_data), // din.data
.is_valid (alt_vip_vfr_vga_avalon_streaming_source_valid), // .valid
.is_ready (alt_vip_vfr_vga_avalon_streaming_source_ready), // .ready
.is_sop (alt_vip_vfr_vga_avalon_streaming_source_startofpacket), // .startofpacket
.is_eop (alt_vip_vfr_vga_avalon_streaming_source_endofpacket), // .endofpacket
.vid_clk (alt_vip_itc_0_clocked_video_vid_clk), // clocked_video.export
.vid_data (alt_vip_itc_0_clocked_video_vid_data), // .export
.underflow (alt_vip_itc_0_clocked_video_underflow), // .export
.vid_datavalid (alt_vip_itc_0_clocked_video_vid_datavalid), // .export
.vid_v_sync (alt_vip_itc_0_clocked_video_vid_v_sync), // .export
.vid_h_sync (alt_vip_itc_0_clocked_video_vid_h_sync), // .export
.vid_f (alt_vip_itc_0_clocked_video_vid_f), // .export
.vid_h (alt_vip_itc_0_clocked_video_vid_h), // .export
.vid_v (alt_vip_itc_0_clocked_video_vid_v) // .export
);
alt_vipvfr131_vfr #(
.BITS_PER_PIXEL_PER_COLOR_PLANE (8),
.NUMBER_OF_CHANNELS_IN_PARALLEL (4),
.NUMBER_OF_CHANNELS_IN_SEQUENCE (1),
.MAX_IMAGE_WIDTH (1024),
.MAX_IMAGE_HEIGHT (768),
.MEM_PORT_WIDTH (128),
.RMASTER_FIFO_DEPTH (64),
.RMASTER_BURST_TARGET (32),
.CLOCKS_ARE_SEPARATE (1)
) alt_vip_vfr_vga (
.clock (clk_130_clk), // clock_reset.clk
.reset (rst_controller_reset_out_reset), // clock_reset_reset.reset
.master_clock (clk_clk), // clock_master.clk
.master_reset (rst_controller_001_reset_out_reset), // clock_master_reset.reset
.slave_address (mm_interconnect_1_alt_vip_vfr_vga_avalon_slave_address), // avalon_slave.address
.slave_write (mm_interconnect_1_alt_vip_vfr_vga_avalon_slave_write), // .write
.slave_writedata (mm_interconnect_1_alt_vip_vfr_vga_avalon_slave_writedata), // .writedata
.slave_read (mm_interconnect_1_alt_vip_vfr_vga_avalon_slave_read), // .read
.slave_readdata (mm_interconnect_1_alt_vip_vfr_vga_avalon_slave_readdata), // .readdata
.slave_irq (), // interrupt_sender.irq
.dout_data (alt_vip_vfr_vga_avalon_streaming_source_data), // avalon_streaming_source.data
.dout_valid (alt_vip_vfr_vga_avalon_streaming_source_valid), // .valid
.dout_ready (alt_vip_vfr_vga_avalon_streaming_source_ready), // .ready
.dout_startofpacket (alt_vip_vfr_vga_avalon_streaming_source_startofpacket), // .startofpacket
.dout_endofpacket (alt_vip_vfr_vga_avalon_streaming_source_endofpacket), // .endofpacket
.master_address (alt_vip_vfr_vga_avalon_master_address), // avalon_master.address
.master_burstcount (alt_vip_vfr_vga_avalon_master_burstcount), // .burstcount
.master_readdata (alt_vip_vfr_vga_avalon_master_readdata), // .readdata
.master_read (alt_vip_vfr_vga_avalon_master_read), // .read
.master_readdatavalid (alt_vip_vfr_vga_avalon_master_readdatavalid), // .readdatavalid
.master_waitrequest (alt_vip_vfr_vga_avalon_master_waitrequest) // .waitrequest
);
ece453 ece453_0 (
.slave_address (mm_interconnect_1_ece453_0_avalon_slave_0_address), // avalon_slave_0.address
.slave_byteenable (mm_interconnect_1_ece453_0_avalon_slave_0_byteenable), // .byteenable
.slave_read (mm_interconnect_1_ece453_0_avalon_slave_0_read), // .read
.slave_readdata (mm_interconnect_1_ece453_0_avalon_slave_0_readdata), // .readdata
.slave_write (mm_interconnect_1_ece453_0_avalon_slave_0_write), // .write
.slave_writedata (mm_interconnect_1_ece453_0_avalon_slave_0_writedata), // .writedata
.clk (clk_clk), // clock_sink.clk
.reset (rst_controller_002_reset_out_reset), // clock_reset.reset
.irq_out (irq_mapper_receiver0_irq), // interrupt_sender.irq
.gpio_inputs (ece453_0_gpio_in_export), // gpio_in.export
.gpio_outputs (ece453_0_gpio_out_export) // gpio_out.export
);
soc_system_hps_0 #(
.F2S_Width (3),
.S2F_Width (3)
) hps_0 (
.f2h_cold_rst_req_n (hps_0_f2h_cold_reset_req_reset_n), // f2h_cold_reset_req.reset_n
.f2h_dbg_rst_req_n (hps_0_f2h_debug_reset_req_reset_n), // f2h_debug_reset_req.reset_n
.f2h_warm_rst_req_n (hps_0_f2h_warm_reset_req_reset_n), // f2h_warm_reset_req.reset_n
.f2h_stm_hwevents (hps_0_f2h_stm_hw_events_stm_hwevents), // f2h_stm_hw_events.stm_hwevents
.spim0_txd (hps_0_spim0_txd), // spim0.txd
.spim0_rxd (hps_0_spim0_rxd), // .rxd
.spim0_ss_in_n (hps_0_spim0_ss_in_n), // .ss_in_n
.spim0_ssi_oe_n (hps_0_spim0_ssi_oe_n), // .ssi_oe_n
.spim0_ss_0_n (hps_0_spim0_ss_0_n), // .ss_0_n
.spim0_ss_1_n (hps_0_spim0_ss_1_n), // .ss_1_n
.spim0_ss_2_n (hps_0_spim0_ss_2_n), // .ss_2_n
.spim0_ss_3_n (hps_0_spim0_ss_3_n), // .ss_3_n
.spim0_sclk_out (hps_0_spim0_sclk_out_clk), // spim0_sclk_out.clk
.uart1_cts (hps_0_uart1_cts), // uart1.cts
.uart1_dsr (hps_0_uart1_dsr), // .dsr
.uart1_dcd (hps_0_uart1_dcd), // .dcd
.uart1_ri (hps_0_uart1_ri), // .ri
.uart1_dtr (hps_0_uart1_dtr), // .dtr
.uart1_rts (hps_0_uart1_rts), // .rts
.uart1_out1_n (hps_0_uart1_out1_n), // .out1_n
.uart1_out2_n (hps_0_uart1_out2_n), // .out2_n
.uart1_rxd (hps_0_uart1_rxd), // .rxd
.uart1_txd (hps_0_uart1_txd), // .txd
.i2c_emac0_scl (hps_0_i2c2_scl_in_clk), // i2c2_scl_in.clk
.i2c_emac0_out_clk (hps_0_i2c2_clk_clk), // i2c2_clk.clk
.i2c_emac0_out_data (hps_0_i2c2_out_data), // i2c2.out_data
.i2c_emac0_sda (hps_0_i2c2_sda), // .sda
.mem_a (memory_mem_a), // memory.mem_a
.mem_ba (memory_mem_ba), // .mem_ba
.mem_ck (memory_mem_ck), // .mem_ck
.mem_ck_n (memory_mem_ck_n), // .mem_ck_n
.mem_cke (memory_mem_cke), // .mem_cke
.mem_cs_n (memory_mem_cs_n), // .mem_cs_n
.mem_ras_n (memory_mem_ras_n), // .mem_ras_n
.mem_cas_n (memory_mem_cas_n), // .mem_cas_n
.mem_we_n (memory_mem_we_n), // .mem_we_n
.mem_reset_n (memory_mem_reset_n), // .mem_reset_n
.mem_dq (memory_mem_dq), // .mem_dq
.mem_dqs (memory_mem_dqs), // .mem_dqs
.mem_dqs_n (memory_mem_dqs_n), // .mem_dqs_n
.mem_odt (memory_mem_odt), // .mem_odt
.mem_dm (memory_mem_dm), // .mem_dm
.oct_rzqin (memory_oct_rzqin), // .oct_rzqin
.hps_io_emac1_inst_TX_CLK (hps_0_hps_io_hps_io_emac1_inst_TX_CLK), // hps_io.hps_io_emac1_inst_TX_CLK
.hps_io_emac1_inst_TXD0 (hps_0_hps_io_hps_io_emac1_inst_TXD0), // .hps_io_emac1_inst_TXD0
.hps_io_emac1_inst_TXD1 (hps_0_hps_io_hps_io_emac1_inst_TXD1), // .hps_io_emac1_inst_TXD1
.hps_io_emac1_inst_TXD2 (hps_0_hps_io_hps_io_emac1_inst_TXD2), // .hps_io_emac1_inst_TXD2
.hps_io_emac1_inst_TXD3 (hps_0_hps_io_hps_io_emac1_inst_TXD3), // .hps_io_emac1_inst_TXD3
.hps_io_emac1_inst_RXD0 (hps_0_hps_io_hps_io_emac1_inst_RXD0), // .hps_io_emac1_inst_RXD0
.hps_io_emac1_inst_MDIO (hps_0_hps_io_hps_io_emac1_inst_MDIO), // .hps_io_emac1_inst_MDIO
.hps_io_emac1_inst_MDC (hps_0_hps_io_hps_io_emac1_inst_MDC), // .hps_io_emac1_inst_MDC
.hps_io_emac1_inst_RX_CTL (hps_0_hps_io_hps_io_emac1_inst_RX_CTL), // .hps_io_emac1_inst_RX_CTL
.hps_io_emac1_inst_TX_CTL (hps_0_hps_io_hps_io_emac1_inst_TX_CTL), // .hps_io_emac1_inst_TX_CTL
.hps_io_emac1_inst_RX_CLK (hps_0_hps_io_hps_io_emac1_inst_RX_CLK), // .hps_io_emac1_inst_RX_CLK
.hps_io_emac1_inst_RXD1 (hps_0_hps_io_hps_io_emac1_inst_RXD1), // .hps_io_emac1_inst_RXD1
.hps_io_emac1_inst_RXD2 (hps_0_hps_io_hps_io_emac1_inst_RXD2), // .hps_io_emac1_inst_RXD2
.hps_io_emac1_inst_RXD3 (hps_0_hps_io_hps_io_emac1_inst_RXD3), // .hps_io_emac1_inst_RXD3
.hps_io_qspi_inst_IO0 (hps_0_hps_io_hps_io_qspi_inst_IO0), // .hps_io_qspi_inst_IO0
.hps_io_qspi_inst_IO1 (hps_0_hps_io_hps_io_qspi_inst_IO1), // .hps_io_qspi_inst_IO1
.hps_io_qspi_inst_IO2 (hps_0_hps_io_hps_io_qspi_inst_IO2), // .hps_io_qspi_inst_IO2
.hps_io_qspi_inst_IO3 (hps_0_hps_io_hps_io_qspi_inst_IO3), // .hps_io_qspi_inst_IO3
.hps_io_qspi_inst_SS0 (hps_0_hps_io_hps_io_qspi_inst_SS0), // .hps_io_qspi_inst_SS0
.hps_io_qspi_inst_CLK (hps_0_hps_io_hps_io_qspi_inst_CLK), // .hps_io_qspi_inst_CLK
.hps_io_sdio_inst_CMD (hps_0_hps_io_hps_io_sdio_inst_CMD), // .hps_io_sdio_inst_CMD
.hps_io_sdio_inst_D0 (hps_0_hps_io_hps_io_sdio_inst_D0), // .hps_io_sdio_inst_D0
.hps_io_sdio_inst_D1 (hps_0_hps_io_hps_io_sdio_inst_D1), // .hps_io_sdio_inst_D1
.hps_io_sdio_inst_CLK (hps_0_hps_io_hps_io_sdio_inst_CLK), // .hps_io_sdio_inst_CLK
.hps_io_sdio_inst_D2 (hps_0_hps_io_hps_io_sdio_inst_D2), // .hps_io_sdio_inst_D2
.hps_io_sdio_inst_D3 (hps_0_hps_io_hps_io_sdio_inst_D3), // .hps_io_sdio_inst_D3
.hps_io_usb1_inst_D0 (hps_0_hps_io_hps_io_usb1_inst_D0), // .hps_io_usb1_inst_D0
.hps_io_usb1_inst_D1 (hps_0_hps_io_hps_io_usb1_inst_D1), // .hps_io_usb1_inst_D1
.hps_io_usb1_inst_D2 (hps_0_hps_io_hps_io_usb1_inst_D2), // .hps_io_usb1_inst_D2
.hps_io_usb1_inst_D3 (hps_0_hps_io_hps_io_usb1_inst_D3), // .hps_io_usb1_inst_D3
.hps_io_usb1_inst_D4 (hps_0_hps_io_hps_io_usb1_inst_D4), // .hps_io_usb1_inst_D4
.hps_io_usb1_inst_D5 (hps_0_hps_io_hps_io_usb1_inst_D5), // .hps_io_usb1_inst_D5
.hps_io_usb1_inst_D6 (hps_0_hps_io_hps_io_usb1_inst_D6), // .hps_io_usb1_inst_D6
.hps_io_usb1_inst_D7 (hps_0_hps_io_hps_io_usb1_inst_D7), // .hps_io_usb1_inst_D7
.hps_io_usb1_inst_CLK (hps_0_hps_io_hps_io_usb1_inst_CLK), // .hps_io_usb1_inst_CLK
.hps_io_usb1_inst_STP (hps_0_hps_io_hps_io_usb1_inst_STP), // .hps_io_usb1_inst_STP
.hps_io_usb1_inst_DIR (hps_0_hps_io_hps_io_usb1_inst_DIR), // .hps_io_usb1_inst_DIR
.hps_io_usb1_inst_NXT (hps_0_hps_io_hps_io_usb1_inst_NXT), // .hps_io_usb1_inst_NXT
.hps_io_spim1_inst_CLK (hps_0_hps_io_hps_io_spim1_inst_CLK), // .hps_io_spim1_inst_CLK
.hps_io_spim1_inst_MOSI (hps_0_hps_io_hps_io_spim1_inst_MOSI), // .hps_io_spim1_inst_MOSI
.hps_io_spim1_inst_MISO (hps_0_hps_io_hps_io_spim1_inst_MISO), // .hps_io_spim1_inst_MISO
.hps_io_spim1_inst_SS0 (hps_0_hps_io_hps_io_spim1_inst_SS0), // .hps_io_spim1_inst_SS0
.hps_io_uart0_inst_RX (hps_0_hps_io_hps_io_uart0_inst_RX), // .hps_io_uart0_inst_RX
.hps_io_uart0_inst_TX (hps_0_hps_io_hps_io_uart0_inst_TX), // .hps_io_uart0_inst_TX
.hps_io_i2c0_inst_SDA (hps_0_hps_io_hps_io_i2c0_inst_SDA), // .hps_io_i2c0_inst_SDA
.hps_io_i2c0_inst_SCL (hps_0_hps_io_hps_io_i2c0_inst_SCL), // .hps_io_i2c0_inst_SCL
.hps_io_i2c1_inst_SDA (hps_0_hps_io_hps_io_i2c1_inst_SDA), // .hps_io_i2c1_inst_SDA
.hps_io_i2c1_inst_SCL (hps_0_hps_io_hps_io_i2c1_inst_SCL), // .hps_io_i2c1_inst_SCL
.hps_io_gpio_inst_GPIO09 (hps_0_hps_io_hps_io_gpio_inst_GPIO09), // .hps_io_gpio_inst_GPIO09
.hps_io_gpio_inst_GPIO35 (hps_0_hps_io_hps_io_gpio_inst_GPIO35), // .hps_io_gpio_inst_GPIO35
.hps_io_gpio_inst_GPIO40 (hps_0_hps_io_hps_io_gpio_inst_GPIO40), // .hps_io_gpio_inst_GPIO40
.hps_io_gpio_inst_GPIO48 (hps_0_hps_io_hps_io_gpio_inst_GPIO48), // .hps_io_gpio_inst_GPIO48
.hps_io_gpio_inst_GPIO53 (hps_0_hps_io_hps_io_gpio_inst_GPIO53), // .hps_io_gpio_inst_GPIO53
.hps_io_gpio_inst_GPIO54 (hps_0_hps_io_hps_io_gpio_inst_GPIO54), // .hps_io_gpio_inst_GPIO54
.hps_io_gpio_inst_GPIO61 (hps_0_hps_io_hps_io_gpio_inst_GPIO61), // .hps_io_gpio_inst_GPIO61
.h2f_rst_n (hps_0_h2f_reset_reset_n), // h2f_reset.reset_n
.h2f_axi_clk (clk_clk), // h2f_axi_clock.clk
.h2f_AWID (), // h2f_axi_master.awid
.h2f_AWADDR (), // .awaddr
.h2f_AWLEN (), // .awlen
.h2f_AWSIZE (), // .awsize
.h2f_AWBURST (), // .awburst
.h2f_AWLOCK (), // .awlock
.h2f_AWCACHE (), // .awcache
.h2f_AWPROT (), // .awprot
.h2f_AWVALID (), // .awvalid
.h2f_AWREADY (), // .awready
.h2f_WID (), // .wid
.h2f_WDATA (), // .wdata
.h2f_WSTRB (), // .wstrb
.h2f_WLAST (), // .wlast
.h2f_WVALID (), // .wvalid
.h2f_WREADY (), // .wready
.h2f_BID (), // .bid
.h2f_BRESP (), // .bresp
.h2f_BVALID (), // .bvalid
.h2f_BREADY (), // .bready
.h2f_ARID (), // .arid
.h2f_ARADDR (), // .araddr
.h2f_ARLEN (), // .arlen
.h2f_ARSIZE (), // .arsize
.h2f_ARBURST (), // .arburst
.h2f_ARLOCK (), // .arlock
.h2f_ARCACHE (), // .arcache
.h2f_ARPROT (), // .arprot
.h2f_ARVALID (), // .arvalid
.h2f_ARREADY (), // .arready
.h2f_RID (), // .rid
.h2f_RDATA (), // .rdata
.h2f_RRESP (), // .rresp
.h2f_RLAST (), // .rlast
.h2f_RVALID (), // .rvalid
.h2f_RREADY (), // .rready
.f2h_axi_clk (clk_clk), // f2h_axi_clock.clk
.f2h_AWID (mm_interconnect_0_hps_0_f2h_axi_slave_awid), // f2h_axi_slave.awid
.f2h_AWADDR (mm_interconnect_0_hps_0_f2h_axi_slave_awaddr), // .awaddr
.f2h_AWLEN (mm_interconnect_0_hps_0_f2h_axi_slave_awlen), // .awlen
.f2h_AWSIZE (mm_interconnect_0_hps_0_f2h_axi_slave_awsize), // .awsize
.f2h_AWBURST (mm_interconnect_0_hps_0_f2h_axi_slave_awburst), // .awburst
.f2h_AWLOCK (mm_interconnect_0_hps_0_f2h_axi_slave_awlock), // .awlock
.f2h_AWCACHE (mm_interconnect_0_hps_0_f2h_axi_slave_awcache), // .awcache
.f2h_AWPROT (mm_interconnect_0_hps_0_f2h_axi_slave_awprot), // .awprot
.f2h_AWVALID (mm_interconnect_0_hps_0_f2h_axi_slave_awvalid), // .awvalid
.f2h_AWREADY (mm_interconnect_0_hps_0_f2h_axi_slave_awready), // .awready
.f2h_AWUSER (mm_interconnect_0_hps_0_f2h_axi_slave_awuser), // .awuser
.f2h_WID (mm_interconnect_0_hps_0_f2h_axi_slave_wid), // .wid
.f2h_WDATA (mm_interconnect_0_hps_0_f2h_axi_slave_wdata), // .wdata
.f2h_WSTRB (mm_interconnect_0_hps_0_f2h_axi_slave_wstrb), // .wstrb
.f2h_WLAST (mm_interconnect_0_hps_0_f2h_axi_slave_wlast), // .wlast
.f2h_WVALID (mm_interconnect_0_hps_0_f2h_axi_slave_wvalid), // .wvalid
.f2h_WREADY (mm_interconnect_0_hps_0_f2h_axi_slave_wready), // .wready
.f2h_BID (mm_interconnect_0_hps_0_f2h_axi_slave_bid), // .bid
.f2h_BRESP (mm_interconnect_0_hps_0_f2h_axi_slave_bresp), // .bresp
.f2h_BVALID (mm_interconnect_0_hps_0_f2h_axi_slave_bvalid), // .bvalid
.f2h_BREADY (mm_interconnect_0_hps_0_f2h_axi_slave_bready), // .bready
.f2h_ARID (mm_interconnect_0_hps_0_f2h_axi_slave_arid), // .arid
.f2h_ARADDR (mm_interconnect_0_hps_0_f2h_axi_slave_araddr), // .araddr
.f2h_ARLEN (mm_interconnect_0_hps_0_f2h_axi_slave_arlen), // .arlen
.f2h_ARSIZE (mm_interconnect_0_hps_0_f2h_axi_slave_arsize), // .arsize
.f2h_ARBURST (mm_interconnect_0_hps_0_f2h_axi_slave_arburst), // .arburst
.f2h_ARLOCK (mm_interconnect_0_hps_0_f2h_axi_slave_arlock), // .arlock
.f2h_ARCACHE (mm_interconnect_0_hps_0_f2h_axi_slave_arcache), // .arcache
.f2h_ARPROT (mm_interconnect_0_hps_0_f2h_axi_slave_arprot), // .arprot
.f2h_ARVALID (mm_interconnect_0_hps_0_f2h_axi_slave_arvalid), // .arvalid
.f2h_ARREADY (mm_interconnect_0_hps_0_f2h_axi_slave_arready), // .arready
.f2h_ARUSER (mm_interconnect_0_hps_0_f2h_axi_slave_aruser), // .aruser
.f2h_RID (mm_interconnect_0_hps_0_f2h_axi_slave_rid), // .rid
.f2h_RDATA (mm_interconnect_0_hps_0_f2h_axi_slave_rdata), // .rdata
.f2h_RRESP (mm_interconnect_0_hps_0_f2h_axi_slave_rresp), // .rresp
.f2h_RLAST (mm_interconnect_0_hps_0_f2h_axi_slave_rlast), // .rlast
.f2h_RVALID (mm_interconnect_0_hps_0_f2h_axi_slave_rvalid), // .rvalid
.f2h_RREADY (mm_interconnect_0_hps_0_f2h_axi_slave_rready), // .rready
.h2f_lw_axi_clk (clk_clk), // h2f_lw_axi_clock.clk
.h2f_lw_AWID (hps_0_h2f_lw_axi_master_awid), // h2f_lw_axi_master.awid
.h2f_lw_AWADDR (hps_0_h2f_lw_axi_master_awaddr), // .awaddr
.h2f_lw_AWLEN (hps_0_h2f_lw_axi_master_awlen), // .awlen
.h2f_lw_AWSIZE (hps_0_h2f_lw_axi_master_awsize), // .awsize
.h2f_lw_AWBURST (hps_0_h2f_lw_axi_master_awburst), // .awburst
.h2f_lw_AWLOCK (hps_0_h2f_lw_axi_master_awlock), // .awlock
.h2f_lw_AWCACHE (hps_0_h2f_lw_axi_master_awcache), // .awcache
.h2f_lw_AWPROT (hps_0_h2f_lw_axi_master_awprot), // .awprot
.h2f_lw_AWVALID (hps_0_h2f_lw_axi_master_awvalid), // .awvalid
.h2f_lw_AWREADY (hps_0_h2f_lw_axi_master_awready), // .awready
.h2f_lw_WID (hps_0_h2f_lw_axi_master_wid), // .wid
.h2f_lw_WDATA (hps_0_h2f_lw_axi_master_wdata), // .wdata
.h2f_lw_WSTRB (hps_0_h2f_lw_axi_master_wstrb), // .wstrb
.h2f_lw_WLAST (hps_0_h2f_lw_axi_master_wlast), // .wlast
.h2f_lw_WVALID (hps_0_h2f_lw_axi_master_wvalid), // .wvalid
.h2f_lw_WREADY (hps_0_h2f_lw_axi_master_wready), // .wready
.h2f_lw_BID (hps_0_h2f_lw_axi_master_bid), // .bid
.h2f_lw_BRESP (hps_0_h2f_lw_axi_master_bresp), // .bresp
.h2f_lw_BVALID (hps_0_h2f_lw_axi_master_bvalid), // .bvalid
.h2f_lw_BREADY (hps_0_h2f_lw_axi_master_bready), // .bready
.h2f_lw_ARID (hps_0_h2f_lw_axi_master_arid), // .arid
.h2f_lw_ARADDR (hps_0_h2f_lw_axi_master_araddr), // .araddr
.h2f_lw_ARLEN (hps_0_h2f_lw_axi_master_arlen), // .arlen
.h2f_lw_ARSIZE (hps_0_h2f_lw_axi_master_arsize), // .arsize
.h2f_lw_ARBURST (hps_0_h2f_lw_axi_master_arburst), // .arburst
.h2f_lw_ARLOCK (hps_0_h2f_lw_axi_master_arlock), // .arlock
.h2f_lw_ARCACHE (hps_0_h2f_lw_axi_master_arcache), // .arcache
.h2f_lw_ARPROT (hps_0_h2f_lw_axi_master_arprot), // .arprot
.h2f_lw_ARVALID (hps_0_h2f_lw_axi_master_arvalid), // .arvalid
.h2f_lw_ARREADY (hps_0_h2f_lw_axi_master_arready), // .arready
.h2f_lw_RID (hps_0_h2f_lw_axi_master_rid), // .rid
.h2f_lw_RDATA (hps_0_h2f_lw_axi_master_rdata), // .rdata
.h2f_lw_RRESP (hps_0_h2f_lw_axi_master_rresp), // .rresp
.h2f_lw_RLAST (hps_0_h2f_lw_axi_master_rlast), // .rlast
.h2f_lw_RVALID (hps_0_h2f_lw_axi_master_rvalid), // .rvalid
.h2f_lw_RREADY (hps_0_h2f_lw_axi_master_rready), // .rready
.f2h_irq_p0 (hps_0_f2h_irq0_irq), // f2h_irq0.irq
.f2h_irq_p1 (hps_0_f2h_irq1_irq) // f2h_irq1.irq
);
intr_capturer #(
.NUM_INTR (32)
) intr_capturer_0 (
.clk (clk_clk), // clock.clk
.rst_n (~rst_controller_001_reset_out_reset), // reset_sink.reset_n
.addr (mm_interconnect_1_intr_capturer_0_avalon_slave_0_address), // avalon_slave_0.address
.read (mm_interconnect_1_intr_capturer_0_avalon_slave_0_read), // .read
.rddata (mm_interconnect_1_intr_capturer_0_avalon_slave_0_readdata), // .readdata
.interrupt_in (intr_capturer_0_interrupt_receiver_irq) // interrupt_receiver.irq
);
soc_system_jtag_uart jtag_uart (
.clk (clk_clk), // clk.clk
.rst_n (~rst_controller_001_reset_out_reset), // reset.reset_n
.av_chipselect (mm_interconnect_1_jtag_uart_avalon_jtag_slave_chipselect), // avalon_jtag_slave.chipselect
.av_address (mm_interconnect_1_jtag_uart_avalon_jtag_slave_address), // .address
.av_read_n (~mm_interconnect_1_jtag_uart_avalon_jtag_slave_read), // .read_n
.av_readdata (mm_interconnect_1_jtag_uart_avalon_jtag_slave_readdata), // .readdata
.av_write_n (~mm_interconnect_1_jtag_uart_avalon_jtag_slave_write), // .write_n
.av_writedata (mm_interconnect_1_jtag_uart_avalon_jtag_slave_writedata), // .writedata
.av_waitrequest (mm_interconnect_1_jtag_uart_avalon_jtag_slave_waitrequest), // .waitrequest
.av_irq (irq_mapper_receiver1_irq) // irq.irq
);
soc_system_master_non_sec #(
.USE_PLI (0),
.PLI_PORT (50000),
.FIFO_DEPTHS (2)
) master_non_sec (
.clk_clk (clk_clk), // clk.clk
.clk_reset_reset (~reset_reset_n), // clk_reset.reset
.master_address (master_non_sec_master_address), // master.address
.master_readdata (master_non_sec_master_readdata), // .readdata
.master_read (master_non_sec_master_read), // .read
.master_write (master_non_sec_master_write), // .write
.master_writedata (master_non_sec_master_writedata), // .writedata
.master_waitrequest (master_non_sec_master_waitrequest), // .waitrequest
.master_readdatavalid (master_non_sec_master_readdatavalid), // .readdatavalid
.master_byteenable (master_non_sec_master_byteenable), // .byteenable
.master_reset_reset () // master_reset.reset
);
soc_system_master_non_sec #(
.USE_PLI (0),
.PLI_PORT (50000),
.FIFO_DEPTHS (2)
) master_secure (
.clk_clk (clk_clk), // clk.clk
.clk_reset_reset (~reset_reset_n), // clk_reset.reset
.master_address (master_secure_master_address), // master.address
.master_readdata (master_secure_master_readdata), // .readdata
.master_read (master_secure_master_read), // .read
.master_write (master_secure_master_write), // .write
.master_writedata (master_secure_master_writedata), // .writedata
.master_waitrequest (master_secure_master_waitrequest), // .waitrequest
.master_readdatavalid (master_secure_master_readdatavalid), // .readdatavalid
.master_byteenable (master_secure_master_byteenable), // .byteenable
.master_reset_reset () // master_reset.reset
);
soc_system_sysid_qsys sysid_qsys (
.clock (clk_clk), // clk.clk
.reset_n (~rst_controller_001_reset_out_reset), // reset.reset_n
.readdata (mm_interconnect_1_sysid_qsys_control_slave_readdata), // control_slave.readdata
.address (mm_interconnect_1_sysid_qsys_control_slave_address) // .address
);
soc_system_mm_interconnect_0 mm_interconnect_0 (
.hps_0_f2h_axi_slave_awid (mm_interconnect_0_hps_0_f2h_axi_slave_awid), // hps_0_f2h_axi_slave.awid
.hps_0_f2h_axi_slave_awaddr (mm_interconnect_0_hps_0_f2h_axi_slave_awaddr), // .awaddr
.hps_0_f2h_axi_slave_awlen (mm_interconnect_0_hps_0_f2h_axi_slave_awlen), // .awlen
.hps_0_f2h_axi_slave_awsize (mm_interconnect_0_hps_0_f2h_axi_slave_awsize), // .awsize
.hps_0_f2h_axi_slave_awburst (mm_interconnect_0_hps_0_f2h_axi_slave_awburst), // .awburst
.hps_0_f2h_axi_slave_awlock (mm_interconnect_0_hps_0_f2h_axi_slave_awlock), // .awlock
.hps_0_f2h_axi_slave_awcache (mm_interconnect_0_hps_0_f2h_axi_slave_awcache), // .awcache
.hps_0_f2h_axi_slave_awprot (mm_interconnect_0_hps_0_f2h_axi_slave_awprot), // .awprot
.hps_0_f2h_axi_slave_awuser (mm_interconnect_0_hps_0_f2h_axi_slave_awuser), // .awuser
.hps_0_f2h_axi_slave_awvalid (mm_interconnect_0_hps_0_f2h_axi_slave_awvalid), // .awvalid
.hps_0_f2h_axi_slave_awready (mm_interconnect_0_hps_0_f2h_axi_slave_awready), // .awready
.hps_0_f2h_axi_slave_wid (mm_interconnect_0_hps_0_f2h_axi_slave_wid), // .wid
.hps_0_f2h_axi_slave_wdata (mm_interconnect_0_hps_0_f2h_axi_slave_wdata), // .wdata
.hps_0_f2h_axi_slave_wstrb (mm_interconnect_0_hps_0_f2h_axi_slave_wstrb), // .wstrb
.hps_0_f2h_axi_slave_wlast (mm_interconnect_0_hps_0_f2h_axi_slave_wlast), // .wlast
.hps_0_f2h_axi_slave_wvalid (mm_interconnect_0_hps_0_f2h_axi_slave_wvalid), // .wvalid
.hps_0_f2h_axi_slave_wready (mm_interconnect_0_hps_0_f2h_axi_slave_wready), // .wready
.hps_0_f2h_axi_slave_bid (mm_interconnect_0_hps_0_f2h_axi_slave_bid), // .bid
.hps_0_f2h_axi_slave_bresp (mm_interconnect_0_hps_0_f2h_axi_slave_bresp), // .bresp
.hps_0_f2h_axi_slave_bvalid (mm_interconnect_0_hps_0_f2h_axi_slave_bvalid), // .bvalid
.hps_0_f2h_axi_slave_bready (mm_interconnect_0_hps_0_f2h_axi_slave_bready), // .bready
.hps_0_f2h_axi_slave_arid (mm_interconnect_0_hps_0_f2h_axi_slave_arid), // .arid
.hps_0_f2h_axi_slave_araddr (mm_interconnect_0_hps_0_f2h_axi_slave_araddr), // .araddr
.hps_0_f2h_axi_slave_arlen (mm_interconnect_0_hps_0_f2h_axi_slave_arlen), // .arlen
.hps_0_f2h_axi_slave_arsize (mm_interconnect_0_hps_0_f2h_axi_slave_arsize), // .arsize
.hps_0_f2h_axi_slave_arburst (mm_interconnect_0_hps_0_f2h_axi_slave_arburst), // .arburst
.hps_0_f2h_axi_slave_arlock (mm_interconnect_0_hps_0_f2h_axi_slave_arlock), // .arlock
.hps_0_f2h_axi_slave_arcache (mm_interconnect_0_hps_0_f2h_axi_slave_arcache), // .arcache
.hps_0_f2h_axi_slave_arprot (mm_interconnect_0_hps_0_f2h_axi_slave_arprot), // .arprot
.hps_0_f2h_axi_slave_aruser (mm_interconnect_0_hps_0_f2h_axi_slave_aruser), // .aruser
.hps_0_f2h_axi_slave_arvalid (mm_interconnect_0_hps_0_f2h_axi_slave_arvalid), // .arvalid
.hps_0_f2h_axi_slave_arready (mm_interconnect_0_hps_0_f2h_axi_slave_arready), // .arready
.hps_0_f2h_axi_slave_rid (mm_interconnect_0_hps_0_f2h_axi_slave_rid), // .rid
.hps_0_f2h_axi_slave_rdata (mm_interconnect_0_hps_0_f2h_axi_slave_rdata), // .rdata
.hps_0_f2h_axi_slave_rresp (mm_interconnect_0_hps_0_f2h_axi_slave_rresp), // .rresp
.hps_0_f2h_axi_slave_rlast (mm_interconnect_0_hps_0_f2h_axi_slave_rlast), // .rlast
.hps_0_f2h_axi_slave_rvalid (mm_interconnect_0_hps_0_f2h_axi_slave_rvalid), // .rvalid
.hps_0_f2h_axi_slave_rready (mm_interconnect_0_hps_0_f2h_axi_slave_rready), // .rready
.clk_0_clk_clk (clk_clk), // clk_0_clk.clk
.alt_vip_vfr_vga_clock_master_reset_reset_bridge_in_reset_reset (rst_controller_001_reset_out_reset), // alt_vip_vfr_vga_clock_master_reset_reset_bridge_in_reset.reset
.hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset_reset (rst_controller_003_reset_out_reset), // hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset.reset
.master_secure_clk_reset_reset_bridge_in_reset_reset (rst_controller_001_reset_out_reset), // master_secure_clk_reset_reset_bridge_in_reset.reset
.alt_vip_vfr_vga_avalon_master_address (alt_vip_vfr_vga_avalon_master_address), // alt_vip_vfr_vga_avalon_master.address
.alt_vip_vfr_vga_avalon_master_waitrequest (alt_vip_vfr_vga_avalon_master_waitrequest), // .waitrequest
.alt_vip_vfr_vga_avalon_master_burstcount (alt_vip_vfr_vga_avalon_master_burstcount), // .burstcount
.alt_vip_vfr_vga_avalon_master_read (alt_vip_vfr_vga_avalon_master_read), // .read
.alt_vip_vfr_vga_avalon_master_readdata (alt_vip_vfr_vga_avalon_master_readdata), // .readdata
.alt_vip_vfr_vga_avalon_master_readdatavalid (alt_vip_vfr_vga_avalon_master_readdatavalid), // .readdatavalid
.master_secure_master_address (master_secure_master_address), // master_secure_master.address
.master_secure_master_waitrequest (master_secure_master_waitrequest), // .waitrequest
.master_secure_master_byteenable (master_secure_master_byteenable), // .byteenable
.master_secure_master_read (master_secure_master_read), // .read
.master_secure_master_readdata (master_secure_master_readdata), // .readdata
.master_secure_master_readdatavalid (master_secure_master_readdatavalid), // .readdatavalid
.master_secure_master_write (master_secure_master_write), // .write
.master_secure_master_writedata (master_secure_master_writedata) // .writedata
);
soc_system_mm_interconnect_1 mm_interconnect_1 (
.hps_0_h2f_lw_axi_master_awid (hps_0_h2f_lw_axi_master_awid), // hps_0_h2f_lw_axi_master.awid
.hps_0_h2f_lw_axi_master_awaddr (hps_0_h2f_lw_axi_master_awaddr), // .awaddr
.hps_0_h2f_lw_axi_master_awlen (hps_0_h2f_lw_axi_master_awlen), // .awlen
.hps_0_h2f_lw_axi_master_awsize (hps_0_h2f_lw_axi_master_awsize), // .awsize
.hps_0_h2f_lw_axi_master_awburst (hps_0_h2f_lw_axi_master_awburst), // .awburst
.hps_0_h2f_lw_axi_master_awlock (hps_0_h2f_lw_axi_master_awlock), // .awlock
.hps_0_h2f_lw_axi_master_awcache (hps_0_h2f_lw_axi_master_awcache), // .awcache
.hps_0_h2f_lw_axi_master_awprot (hps_0_h2f_lw_axi_master_awprot), // .awprot
.hps_0_h2f_lw_axi_master_awvalid (hps_0_h2f_lw_axi_master_awvalid), // .awvalid
.hps_0_h2f_lw_axi_master_awready (hps_0_h2f_lw_axi_master_awready), // .awready
.hps_0_h2f_lw_axi_master_wid (hps_0_h2f_lw_axi_master_wid), // .wid
.hps_0_h2f_lw_axi_master_wdata (hps_0_h2f_lw_axi_master_wdata), // .wdata
.hps_0_h2f_lw_axi_master_wstrb (hps_0_h2f_lw_axi_master_wstrb), // .wstrb
.hps_0_h2f_lw_axi_master_wlast (hps_0_h2f_lw_axi_master_wlast), // .wlast
.hps_0_h2f_lw_axi_master_wvalid (hps_0_h2f_lw_axi_master_wvalid), // .wvalid
.hps_0_h2f_lw_axi_master_wready (hps_0_h2f_lw_axi_master_wready), // .wready
.hps_0_h2f_lw_axi_master_bid (hps_0_h2f_lw_axi_master_bid), // .bid
.hps_0_h2f_lw_axi_master_bresp (hps_0_h2f_lw_axi_master_bresp), // .bresp
.hps_0_h2f_lw_axi_master_bvalid (hps_0_h2f_lw_axi_master_bvalid), // .bvalid
.hps_0_h2f_lw_axi_master_bready (hps_0_h2f_lw_axi_master_bready), // .bready
.hps_0_h2f_lw_axi_master_arid (hps_0_h2f_lw_axi_master_arid), // .arid
.hps_0_h2f_lw_axi_master_araddr (hps_0_h2f_lw_axi_master_araddr), // .araddr
.hps_0_h2f_lw_axi_master_arlen (hps_0_h2f_lw_axi_master_arlen), // .arlen
.hps_0_h2f_lw_axi_master_arsize (hps_0_h2f_lw_axi_master_arsize), // .arsize
.hps_0_h2f_lw_axi_master_arburst (hps_0_h2f_lw_axi_master_arburst), // .arburst
.hps_0_h2f_lw_axi_master_arlock (hps_0_h2f_lw_axi_master_arlock), // .arlock
.hps_0_h2f_lw_axi_master_arcache (hps_0_h2f_lw_axi_master_arcache), // .arcache
.hps_0_h2f_lw_axi_master_arprot (hps_0_h2f_lw_axi_master_arprot), // .arprot
.hps_0_h2f_lw_axi_master_arvalid (hps_0_h2f_lw_axi_master_arvalid), // .arvalid
.hps_0_h2f_lw_axi_master_arready (hps_0_h2f_lw_axi_master_arready), // .arready
.hps_0_h2f_lw_axi_master_rid (hps_0_h2f_lw_axi_master_rid), // .rid
.hps_0_h2f_lw_axi_master_rdata (hps_0_h2f_lw_axi_master_rdata), // .rdata
.hps_0_h2f_lw_axi_master_rresp (hps_0_h2f_lw_axi_master_rresp), // .rresp
.hps_0_h2f_lw_axi_master_rlast (hps_0_h2f_lw_axi_master_rlast), // .rlast
.hps_0_h2f_lw_axi_master_rvalid (hps_0_h2f_lw_axi_master_rvalid), // .rvalid
.hps_0_h2f_lw_axi_master_rready (hps_0_h2f_lw_axi_master_rready), // .rready
.clk_0_clk_clk (clk_clk), // clk_0_clk.clk
.clk_stream_clk_clk (clk_130_clk), // clk_stream_clk.clk
.alt_vip_vfr_vga_clock_reset_reset_reset_bridge_in_reset_reset (rst_controller_reset_out_reset), // alt_vip_vfr_vga_clock_reset_reset_reset_bridge_in_reset.reset
.ece453_0_clock_reset_reset_bridge_in_reset_reset (rst_controller_002_reset_out_reset), // ece453_0_clock_reset_reset_bridge_in_reset.reset
.hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset (rst_controller_003_reset_out_reset), // hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset.reset
.jtag_uart_reset_reset_bridge_in_reset_reset (rst_controller_001_reset_out_reset), // jtag_uart_reset_reset_bridge_in_reset.reset
.master_non_sec_clk_reset_reset_bridge_in_reset_reset (rst_controller_001_reset_out_reset), // master_non_sec_clk_reset_reset_bridge_in_reset.reset
.master_non_sec_master_address (master_non_sec_master_address), // master_non_sec_master.address
.master_non_sec_master_waitrequest (master_non_sec_master_waitrequest), // .waitrequest
.master_non_sec_master_byteenable (master_non_sec_master_byteenable), // .byteenable
.master_non_sec_master_read (master_non_sec_master_read), // .read
.master_non_sec_master_readdata (master_non_sec_master_readdata), // .readdata
.master_non_sec_master_readdatavalid (master_non_sec_master_readdatavalid), // .readdatavalid
.master_non_sec_master_write (master_non_sec_master_write), // .write
.master_non_sec_master_writedata (master_non_sec_master_writedata), // .writedata
.alt_vip_vfr_vga_avalon_slave_address (mm_interconnect_1_alt_vip_vfr_vga_avalon_slave_address), // alt_vip_vfr_vga_avalon_slave.address
.alt_vip_vfr_vga_avalon_slave_write (mm_interconnect_1_alt_vip_vfr_vga_avalon_slave_write), // .write
.alt_vip_vfr_vga_avalon_slave_read (mm_interconnect_1_alt_vip_vfr_vga_avalon_slave_read), // .read
.alt_vip_vfr_vga_avalon_slave_readdata (mm_interconnect_1_alt_vip_vfr_vga_avalon_slave_readdata), // .readdata
.alt_vip_vfr_vga_avalon_slave_writedata (mm_interconnect_1_alt_vip_vfr_vga_avalon_slave_writedata), // .writedata
.ece453_0_avalon_slave_0_address (mm_interconnect_1_ece453_0_avalon_slave_0_address), // ece453_0_avalon_slave_0.address
.ece453_0_avalon_slave_0_write (mm_interconnect_1_ece453_0_avalon_slave_0_write), // .write
.ece453_0_avalon_slave_0_read (mm_interconnect_1_ece453_0_avalon_slave_0_read), // .read
.ece453_0_avalon_slave_0_readdata (mm_interconnect_1_ece453_0_avalon_slave_0_readdata), // .readdata
.ece453_0_avalon_slave_0_writedata (mm_interconnect_1_ece453_0_avalon_slave_0_writedata), // .writedata
.ece453_0_avalon_slave_0_byteenable (mm_interconnect_1_ece453_0_avalon_slave_0_byteenable), // .byteenable
.intr_capturer_0_avalon_slave_0_address (mm_interconnect_1_intr_capturer_0_avalon_slave_0_address), // intr_capturer_0_avalon_slave_0.address
.intr_capturer_0_avalon_slave_0_read (mm_interconnect_1_intr_capturer_0_avalon_slave_0_read), // .read
.intr_capturer_0_avalon_slave_0_readdata (mm_interconnect_1_intr_capturer_0_avalon_slave_0_readdata), // .readdata
.jtag_uart_avalon_jtag_slave_address (mm_interconnect_1_jtag_uart_avalon_jtag_slave_address), // jtag_uart_avalon_jtag_slave.address
.jtag_uart_avalon_jtag_slave_write (mm_interconnect_1_jtag_uart_avalon_jtag_slave_write), // .write
.jtag_uart_avalon_jtag_slave_read (mm_interconnect_1_jtag_uart_avalon_jtag_slave_read), // .read
.jtag_uart_avalon_jtag_slave_readdata (mm_interconnect_1_jtag_uart_avalon_jtag_slave_readdata), // .readdata
.jtag_uart_avalon_jtag_slave_writedata (mm_interconnect_1_jtag_uart_avalon_jtag_slave_writedata), // .writedata
.jtag_uart_avalon_jtag_slave_waitrequest (mm_interconnect_1_jtag_uart_avalon_jtag_slave_waitrequest), // .waitrequest
.jtag_uart_avalon_jtag_slave_chipselect (mm_interconnect_1_jtag_uart_avalon_jtag_slave_chipselect), // .chipselect
.sysid_qsys_control_slave_address (mm_interconnect_1_sysid_qsys_control_slave_address), // sysid_qsys_control_slave.address
.sysid_qsys_control_slave_readdata (mm_interconnect_1_sysid_qsys_control_slave_readdata) // .readdata
);
soc_system_irq_mapper irq_mapper (
.clk (), // clk.clk
.reset (), // clk_reset.reset
.receiver0_irq (irq_mapper_receiver0_irq), // receiver0.irq
.receiver1_irq (irq_mapper_receiver1_irq), // receiver1.irq
.sender_irq (hps_0_f2h_irq0_irq) // sender.irq
);
soc_system_irq_mapper_001 irq_mapper_001 (
.clk (), // clk.clk
.reset (), // clk_reset.reset
.sender_irq (hps_0_f2h_irq1_irq) // sender.irq
);
soc_system_irq_mapper irq_mapper_002 (
.clk (clk_clk), // clk.clk
.reset (rst_controller_001_reset_out_reset), // clk_reset.reset
.receiver0_irq (irq_mapper_receiver0_irq), // receiver0.irq
.receiver1_irq (irq_mapper_receiver1_irq), // receiver1.irq
.sender_irq (intr_capturer_0_interrupt_receiver_irq) // sender.irq
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller (
.reset_in0 (~reset_reset_n), // reset_in0.reset
.clk (clk_130_clk), // clk.clk
.reset_out (rst_controller_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller_001 (
.reset_in0 (~reset_reset_n), // reset_in0.reset
.clk (clk_clk), // clk.clk
.reset_out (rst_controller_001_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller_002 (
.reset_in0 (~reset_reset_n), // reset_in0.reset
.clk (clk_clk), // clk.clk
.reset_out (rst_controller_002_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller_003 (
.reset_in0 (~hps_0_h2f_reset_reset_n), // reset_in0.reset
.clk (clk_clk), // clk.clk
.reset_out (rst_controller_003_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Wed Mar 01 09:52:04 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// C:/ZyboIP/examples/ov7670_fusion/ov7670_fusion.srcs/sources_1/bd/system/ip/system_ov7670_controller_0_0/system_ov7670_controller_0_0_sim_netlist.v
// Design : system_ov7670_controller_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "system_ov7670_controller_0_0,ov7670_controller,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "ov7670_controller,Vivado 2016.4" *)
(* NotValidForBitStream *)
module system_ov7670_controller_0_0
(clk,
resend,
config_finished,
sioc,
siod,
reset,
pwdn,
xclk);
(* x_interface_info = "xilinx.com:signal:clock:1.0 clk CLK" *) input clk;
input resend;
output config_finished;
output sioc;
inout siod;
(* x_interface_info = "xilinx.com:signal:reset:1.0 reset RST" *) output reset;
output pwdn;
output xclk;
wire \<const0> ;
wire \<const1> ;
wire clk;
wire config_finished;
wire resend;
wire sioc;
wire siod;
wire xclk;
assign pwdn = \<const0> ;
assign reset = \<const1> ;
GND GND
(.G(\<const0> ));
system_ov7670_controller_0_0_ov7670_controller U0
(.clk(clk),
.config_finished(config_finished),
.resend(resend),
.sioc(sioc),
.siod(siod),
.xclk(xclk));
VCC VCC
(.P(\<const1> ));
endmodule
(* ORIG_REF_NAME = "i2c_sender" *)
module system_ov7670_controller_0_0_i2c_sender
(E,
sioc,
p_0_in,
\busy_sr_reg[1]_0 ,
siod,
\busy_sr_reg[31]_0 ,
clk,
p_1_in,
DOADO,
\busy_sr_reg[31]_1 );
output [0:0]E;
output sioc;
output p_0_in;
output \busy_sr_reg[1]_0 ;
output siod;
input \busy_sr_reg[31]_0 ;
input clk;
input [0:0]p_1_in;
input [15:0]DOADO;
input [0:0]\busy_sr_reg[31]_1 ;
wire [15:0]DOADO;
wire [0:0]E;
wire busy_sr0;
wire \busy_sr[0]_i_3_n_0 ;
wire \busy_sr[0]_i_5_n_0 ;
wire \busy_sr[10]_i_1_n_0 ;
wire \busy_sr[11]_i_1_n_0 ;
wire \busy_sr[12]_i_1_n_0 ;
wire \busy_sr[13]_i_1_n_0 ;
wire \busy_sr[14]_i_1_n_0 ;
wire \busy_sr[15]_i_1_n_0 ;
wire \busy_sr[16]_i_1_n_0 ;
wire \busy_sr[17]_i_1_n_0 ;
wire \busy_sr[18]_i_1_n_0 ;
wire \busy_sr[19]_i_1_n_0 ;
wire \busy_sr[1]_i_1_n_0 ;
wire \busy_sr[20]_i_1_n_0 ;
wire \busy_sr[21]_i_1_n_0 ;
wire \busy_sr[22]_i_1_n_0 ;
wire \busy_sr[23]_i_1_n_0 ;
wire \busy_sr[24]_i_1_n_0 ;
wire \busy_sr[25]_i_1_n_0 ;
wire \busy_sr[26]_i_1_n_0 ;
wire \busy_sr[27]_i_1_n_0 ;
wire \busy_sr[28]_i_1_n_0 ;
wire \busy_sr[29]_i_1_n_0 ;
wire \busy_sr[2]_i_1_n_0 ;
wire \busy_sr[30]_i_1_n_0 ;
wire \busy_sr[31]_i_1_n_0 ;
wire \busy_sr[31]_i_2_n_0 ;
wire \busy_sr[3]_i_1_n_0 ;
wire \busy_sr[4]_i_1_n_0 ;
wire \busy_sr[5]_i_1_n_0 ;
wire \busy_sr[6]_i_1_n_0 ;
wire \busy_sr[7]_i_1_n_0 ;
wire \busy_sr[8]_i_1_n_0 ;
wire \busy_sr[9]_i_1_n_0 ;
wire \busy_sr_reg[1]_0 ;
wire \busy_sr_reg[31]_0 ;
wire [0:0]\busy_sr_reg[31]_1 ;
wire \busy_sr_reg_n_0_[0] ;
wire \busy_sr_reg_n_0_[10] ;
wire \busy_sr_reg_n_0_[11] ;
wire \busy_sr_reg_n_0_[12] ;
wire \busy_sr_reg_n_0_[13] ;
wire \busy_sr_reg_n_0_[14] ;
wire \busy_sr_reg_n_0_[15] ;
wire \busy_sr_reg_n_0_[16] ;
wire \busy_sr_reg_n_0_[17] ;
wire \busy_sr_reg_n_0_[18] ;
wire \busy_sr_reg_n_0_[1] ;
wire \busy_sr_reg_n_0_[21] ;
wire \busy_sr_reg_n_0_[22] ;
wire \busy_sr_reg_n_0_[23] ;
wire \busy_sr_reg_n_0_[24] ;
wire \busy_sr_reg_n_0_[25] ;
wire \busy_sr_reg_n_0_[26] ;
wire \busy_sr_reg_n_0_[27] ;
wire \busy_sr_reg_n_0_[28] ;
wire \busy_sr_reg_n_0_[29] ;
wire \busy_sr_reg_n_0_[2] ;
wire \busy_sr_reg_n_0_[30] ;
wire \busy_sr_reg_n_0_[3] ;
wire \busy_sr_reg_n_0_[4] ;
wire \busy_sr_reg_n_0_[5] ;
wire \busy_sr_reg_n_0_[6] ;
wire \busy_sr_reg_n_0_[7] ;
wire \busy_sr_reg_n_0_[8] ;
wire \busy_sr_reg_n_0_[9] ;
wire clk;
wire \data_sr[10]_i_1_n_0 ;
wire \data_sr[12]_i_1_n_0 ;
wire \data_sr[13]_i_1_n_0 ;
wire \data_sr[14]_i_1_n_0 ;
wire \data_sr[15]_i_1_n_0 ;
wire \data_sr[16]_i_1_n_0 ;
wire \data_sr[17]_i_1_n_0 ;
wire \data_sr[18]_i_1_n_0 ;
wire \data_sr[19]_i_1_n_0 ;
wire \data_sr[22]_i_1_n_0 ;
wire \data_sr[27]_i_1_n_0 ;
wire \data_sr[30]_i_1_n_0 ;
wire \data_sr[31]_i_1_n_0 ;
wire \data_sr[31]_i_2_n_0 ;
wire \data_sr[3]_i_1_n_0 ;
wire \data_sr[4]_i_1_n_0 ;
wire \data_sr[5]_i_1_n_0 ;
wire \data_sr[6]_i_1_n_0 ;
wire \data_sr[7]_i_1_n_0 ;
wire \data_sr[8]_i_1_n_0 ;
wire \data_sr[9]_i_1_n_0 ;
wire \data_sr_reg_n_0_[10] ;
wire \data_sr_reg_n_0_[11] ;
wire \data_sr_reg_n_0_[12] ;
wire \data_sr_reg_n_0_[13] ;
wire \data_sr_reg_n_0_[14] ;
wire \data_sr_reg_n_0_[15] ;
wire \data_sr_reg_n_0_[16] ;
wire \data_sr_reg_n_0_[17] ;
wire \data_sr_reg_n_0_[18] ;
wire \data_sr_reg_n_0_[19] ;
wire \data_sr_reg_n_0_[1] ;
wire \data_sr_reg_n_0_[20] ;
wire \data_sr_reg_n_0_[21] ;
wire \data_sr_reg_n_0_[22] ;
wire \data_sr_reg_n_0_[23] ;
wire \data_sr_reg_n_0_[24] ;
wire \data_sr_reg_n_0_[25] ;
wire \data_sr_reg_n_0_[26] ;
wire \data_sr_reg_n_0_[27] ;
wire \data_sr_reg_n_0_[28] ;
wire \data_sr_reg_n_0_[29] ;
wire \data_sr_reg_n_0_[2] ;
wire \data_sr_reg_n_0_[30] ;
wire \data_sr_reg_n_0_[31] ;
wire \data_sr_reg_n_0_[3] ;
wire \data_sr_reg_n_0_[4] ;
wire \data_sr_reg_n_0_[5] ;
wire \data_sr_reg_n_0_[6] ;
wire \data_sr_reg_n_0_[7] ;
wire \data_sr_reg_n_0_[8] ;
wire \data_sr_reg_n_0_[9] ;
wire [7:6]divider_reg__0;
wire [5:0]divider_reg__1;
wire p_0_in;
wire [7:0]p_0_in__0;
wire [0:0]p_1_in;
wire [1:0]p_1_in_0;
wire sioc;
wire sioc_i_1_n_0;
wire sioc_i_2_n_0;
wire sioc_i_3_n_0;
wire sioc_i_4_n_0;
wire sioc_i_5_n_0;
wire siod;
wire siod_INST_0_i_1_n_0;
LUT6 #(
.INIT(64'h4000FFFF40004000))
\busy_sr[0]_i_1
(.I0(\busy_sr[0]_i_3_n_0 ),
.I1(divider_reg__0[6]),
.I2(divider_reg__0[7]),
.I3(p_0_in),
.I4(\busy_sr_reg[1]_0 ),
.I5(p_1_in),
.O(busy_sr0));
LUT6 #(
.INIT(64'h7FFFFFFFFFFFFFFF))
\busy_sr[0]_i_3
(.I0(divider_reg__1[4]),
.I1(divider_reg__1[2]),
.I2(divider_reg__1[0]),
.I3(divider_reg__1[1]),
.I4(divider_reg__1[3]),
.I5(divider_reg__1[5]),
.O(\busy_sr[0]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'hFFFFFFFE))
\busy_sr[0]_i_4
(.I0(divider_reg__1[2]),
.I1(divider_reg__1[3]),
.I2(divider_reg__1[0]),
.I3(divider_reg__1[1]),
.I4(\busy_sr[0]_i_5_n_0 ),
.O(\busy_sr_reg[1]_0 ));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'hFFFE))
\busy_sr[0]_i_5
(.I0(divider_reg__1[5]),
.I1(divider_reg__1[4]),
.I2(divider_reg__0[7]),
.I3(divider_reg__0[6]),
.O(\busy_sr[0]_i_5_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[10]_i_1
(.I0(\busy_sr_reg_n_0_[9] ),
.I1(p_0_in),
.O(\busy_sr[10]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[11]_i_1
(.I0(\busy_sr_reg_n_0_[10] ),
.I1(p_0_in),
.O(\busy_sr[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[12]_i_1
(.I0(\busy_sr_reg_n_0_[11] ),
.I1(p_0_in),
.O(\busy_sr[12]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[13]_i_1
(.I0(\busy_sr_reg_n_0_[12] ),
.I1(p_0_in),
.O(\busy_sr[13]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[14]_i_1
(.I0(\busy_sr_reg_n_0_[13] ),
.I1(p_0_in),
.O(\busy_sr[14]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[15]_i_1
(.I0(\busy_sr_reg_n_0_[14] ),
.I1(p_0_in),
.O(\busy_sr[15]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[16]_i_1
(.I0(\busy_sr_reg_n_0_[15] ),
.I1(p_0_in),
.O(\busy_sr[16]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[17]_i_1
(.I0(\busy_sr_reg_n_0_[16] ),
.I1(p_0_in),
.O(\busy_sr[17]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[18]_i_1
(.I0(\busy_sr_reg_n_0_[17] ),
.I1(p_0_in),
.O(\busy_sr[18]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[19]_i_1
(.I0(\busy_sr_reg_n_0_[18] ),
.I1(p_0_in),
.O(\busy_sr[19]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[1]_i_1
(.I0(\busy_sr_reg_n_0_[0] ),
.I1(p_0_in),
.O(\busy_sr[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[20]_i_1
(.I0(p_1_in_0[0]),
.I1(p_0_in),
.O(\busy_sr[20]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[21]_i_1
(.I0(p_1_in_0[1]),
.I1(p_0_in),
.O(\busy_sr[21]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[22]_i_1
(.I0(\busy_sr_reg_n_0_[21] ),
.I1(p_0_in),
.O(\busy_sr[22]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[23]_i_1
(.I0(\busy_sr_reg_n_0_[22] ),
.I1(p_0_in),
.O(\busy_sr[23]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[24]_i_1
(.I0(\busy_sr_reg_n_0_[23] ),
.I1(p_0_in),
.O(\busy_sr[24]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[25]_i_1
(.I0(\busy_sr_reg_n_0_[24] ),
.I1(p_0_in),
.O(\busy_sr[25]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[26]_i_1
(.I0(\busy_sr_reg_n_0_[25] ),
.I1(p_0_in),
.O(\busy_sr[26]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[27]_i_1
(.I0(\busy_sr_reg_n_0_[26] ),
.I1(p_0_in),
.O(\busy_sr[27]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[28]_i_1
(.I0(\busy_sr_reg_n_0_[27] ),
.I1(p_0_in),
.O(\busy_sr[28]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[29]_i_1
(.I0(\busy_sr_reg_n_0_[28] ),
.I1(p_0_in),
.O(\busy_sr[29]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[2]_i_1
(.I0(\busy_sr_reg_n_0_[1] ),
.I1(p_0_in),
.O(\busy_sr[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[30]_i_1
(.I0(\busy_sr_reg_n_0_[29] ),
.I1(p_0_in),
.O(\busy_sr[30]_i_1_n_0 ));
LUT6 #(
.INIT(64'h22222222A2222222))
\busy_sr[31]_i_1
(.I0(p_1_in),
.I1(\busy_sr_reg[1]_0 ),
.I2(p_0_in),
.I3(divider_reg__0[7]),
.I4(divider_reg__0[6]),
.I5(\busy_sr[0]_i_3_n_0 ),
.O(\busy_sr[31]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[31]_i_2
(.I0(p_0_in),
.I1(\busy_sr_reg_n_0_[30] ),
.O(\busy_sr[31]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[3]_i_1
(.I0(\busy_sr_reg_n_0_[2] ),
.I1(p_0_in),
.O(\busy_sr[3]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[4]_i_1
(.I0(\busy_sr_reg_n_0_[3] ),
.I1(p_0_in),
.O(\busy_sr[4]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[5]_i_1
(.I0(\busy_sr_reg_n_0_[4] ),
.I1(p_0_in),
.O(\busy_sr[5]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[6]_i_1
(.I0(\busy_sr_reg_n_0_[5] ),
.I1(p_0_in),
.O(\busy_sr[6]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[7]_i_1
(.I0(\busy_sr_reg_n_0_[6] ),
.I1(p_0_in),
.O(\busy_sr[7]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[8]_i_1
(.I0(\busy_sr_reg_n_0_[7] ),
.I1(p_0_in),
.O(\busy_sr[8]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[9]_i_1
(.I0(\busy_sr_reg_n_0_[8] ),
.I1(p_0_in),
.O(\busy_sr[9]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\busy_sr_reg[0]
(.C(clk),
.CE(busy_sr0),
.D(p_1_in),
.Q(\busy_sr_reg_n_0_[0] ),
.R(1'b0));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[10]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[10]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[10] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[11]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[11]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[11] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[12]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[12]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[12] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[13]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[13]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[13] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[14]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[14]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[14] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[15]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[15]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[15] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[16]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[16]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[16] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[17]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[17]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[17] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[18]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[18]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[18] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[19]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[19]_i_1_n_0 ),
.Q(p_1_in_0[0]),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[1]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[1]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[1] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[20]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[20]_i_1_n_0 ),
.Q(p_1_in_0[1]),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[21]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[21]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[21] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[22]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[22]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[22] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[23]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[23]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[23] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[24]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[24]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[24] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[25]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[25]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[25] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[26]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[26]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[26] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[27]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[27]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[27] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[28]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[28]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[28] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[29]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[29]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[29] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[2]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[2]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[2] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[30]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[30]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[30] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[31]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[31]_i_2_n_0 ),
.Q(p_0_in),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[3]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[3]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[3] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[4]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[4]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[4] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[5]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[5]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[5] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[6]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[6]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[6] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[7]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[7]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[7] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[8]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[8]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[8] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[9]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[9]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[9] ),
.S(\busy_sr[31]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[10]_i_1
(.I0(\data_sr_reg_n_0_[9] ),
.I1(p_0_in),
.I2(DOADO[7]),
.O(\data_sr[10]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[12]_i_1
(.I0(\data_sr_reg_n_0_[11] ),
.I1(p_0_in),
.I2(DOADO[8]),
.O(\data_sr[12]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[13]_i_1
(.I0(\data_sr_reg_n_0_[12] ),
.I1(p_0_in),
.I2(DOADO[9]),
.O(\data_sr[13]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[14]_i_1
(.I0(\data_sr_reg_n_0_[13] ),
.I1(p_0_in),
.I2(DOADO[10]),
.O(\data_sr[14]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[15]_i_1
(.I0(\data_sr_reg_n_0_[14] ),
.I1(p_0_in),
.I2(DOADO[11]),
.O(\data_sr[15]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[16]_i_1
(.I0(\data_sr_reg_n_0_[15] ),
.I1(p_0_in),
.I2(DOADO[12]),
.O(\data_sr[16]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[17]_i_1
(.I0(\data_sr_reg_n_0_[16] ),
.I1(p_0_in),
.I2(DOADO[13]),
.O(\data_sr[17]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[18]_i_1
(.I0(\data_sr_reg_n_0_[17] ),
.I1(p_0_in),
.I2(DOADO[14]),
.O(\data_sr[18]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[19]_i_1
(.I0(\data_sr_reg_n_0_[18] ),
.I1(p_0_in),
.I2(DOADO[15]),
.O(\data_sr[19]_i_1_n_0 ));
LUT6 #(
.INIT(64'hCFCFCFCFAACAAAAA))
\data_sr[22]_i_1
(.I0(\data_sr_reg_n_0_[22] ),
.I1(\data_sr_reg_n_0_[21] ),
.I2(p_0_in),
.I3(\data_sr[31]_i_2_n_0 ),
.I4(divider_reg__0[7]),
.I5(\busy_sr_reg[31]_0 ),
.O(\data_sr[22]_i_1_n_0 ));
LUT6 #(
.INIT(64'hCFCFCFCFAACAAAAA))
\data_sr[27]_i_1
(.I0(\data_sr_reg_n_0_[27] ),
.I1(\data_sr_reg_n_0_[26] ),
.I2(p_0_in),
.I3(\data_sr[31]_i_2_n_0 ),
.I4(divider_reg__0[7]),
.I5(\busy_sr_reg[31]_0 ),
.O(\data_sr[27]_i_1_n_0 ));
LUT3 #(
.INIT(8'h02))
\data_sr[30]_i_1
(.I0(p_1_in),
.I1(\busy_sr_reg[1]_0 ),
.I2(p_0_in),
.O(\data_sr[30]_i_1_n_0 ));
LUT6 #(
.INIT(64'hCFCFCFCFAACAAAAA))
\data_sr[31]_i_1
(.I0(\data_sr_reg_n_0_[31] ),
.I1(\data_sr_reg_n_0_[30] ),
.I2(p_0_in),
.I3(\data_sr[31]_i_2_n_0 ),
.I4(divider_reg__0[7]),
.I5(\busy_sr_reg[31]_0 ),
.O(\data_sr[31]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT2 #(
.INIT(4'hB))
\data_sr[31]_i_2
(.I0(\busy_sr[0]_i_3_n_0 ),
.I1(divider_reg__0[6]),
.O(\data_sr[31]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[3]_i_1
(.I0(\data_sr_reg_n_0_[2] ),
.I1(p_0_in),
.I2(DOADO[0]),
.O(\data_sr[3]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[4]_i_1
(.I0(\data_sr_reg_n_0_[3] ),
.I1(p_0_in),
.I2(DOADO[1]),
.O(\data_sr[4]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[5]_i_1
(.I0(\data_sr_reg_n_0_[4] ),
.I1(p_0_in),
.I2(DOADO[2]),
.O(\data_sr[5]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[6]_i_1
(.I0(\data_sr_reg_n_0_[5] ),
.I1(p_0_in),
.I2(DOADO[3]),
.O(\data_sr[6]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[7]_i_1
(.I0(\data_sr_reg_n_0_[6] ),
.I1(p_0_in),
.I2(DOADO[4]),
.O(\data_sr[7]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[8]_i_1
(.I0(\data_sr_reg_n_0_[7] ),
.I1(p_0_in),
.I2(DOADO[5]),
.O(\data_sr[8]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[9]_i_1
(.I0(\data_sr_reg_n_0_[8] ),
.I1(p_0_in),
.I2(DOADO[6]),
.O(\data_sr[9]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[10]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[10]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[10] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[11]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[10] ),
.Q(\data_sr_reg_n_0_[11] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[12]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[12]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[12] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[13]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[13]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[13] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[14]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[14]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[14] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[15]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[15]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[15] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[16]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[16]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[16] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[17]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[17]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[17] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[18]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[18]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[18] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[19]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[19]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[19] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[1]
(.C(clk),
.CE(busy_sr0),
.D(p_0_in),
.Q(\data_sr_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[20]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[19] ),
.Q(\data_sr_reg_n_0_[20] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[21]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[20] ),
.Q(\data_sr_reg_n_0_[21] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[22]
(.C(clk),
.CE(1'b1),
.D(\data_sr[22]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[22] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[23]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[22] ),
.Q(\data_sr_reg_n_0_[23] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[24]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[23] ),
.Q(\data_sr_reg_n_0_[24] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[25]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[24] ),
.Q(\data_sr_reg_n_0_[25] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[26]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[25] ),
.Q(\data_sr_reg_n_0_[26] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[27]
(.C(clk),
.CE(1'b1),
.D(\data_sr[27]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[27] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[28]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[27] ),
.Q(\data_sr_reg_n_0_[28] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[29]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[28] ),
.Q(\data_sr_reg_n_0_[29] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[2]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[1] ),
.Q(\data_sr_reg_n_0_[2] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[30]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[29] ),
.Q(\data_sr_reg_n_0_[30] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[31]
(.C(clk),
.CE(1'b1),
.D(\data_sr[31]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[31] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[3]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[3]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[4]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[4]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[5]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[5]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[6]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[6]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[7]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[7]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[7] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[8]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[8]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[8] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[9]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[9]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[9] ),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT1 #(
.INIT(2'h1))
\divider[0]_i_1
(.I0(divider_reg__1[0]),
.O(p_0_in__0[0]));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT2 #(
.INIT(4'h6))
\divider[1]_i_1
(.I0(divider_reg__1[0]),
.I1(divider_reg__1[1]),
.O(p_0_in__0[1]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT3 #(
.INIT(8'h78))
\divider[2]_i_1
(.I0(divider_reg__1[1]),
.I1(divider_reg__1[0]),
.I2(divider_reg__1[2]),
.O(p_0_in__0[2]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT4 #(
.INIT(16'h7F80))
\divider[3]_i_1
(.I0(divider_reg__1[2]),
.I1(divider_reg__1[0]),
.I2(divider_reg__1[1]),
.I3(divider_reg__1[3]),
.O(p_0_in__0[3]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'h7FFF8000))
\divider[4]_i_1
(.I0(divider_reg__1[3]),
.I1(divider_reg__1[1]),
.I2(divider_reg__1[0]),
.I3(divider_reg__1[2]),
.I4(divider_reg__1[4]),
.O(p_0_in__0[4]));
LUT6 #(
.INIT(64'h7FFFFFFF80000000))
\divider[5]_i_1
(.I0(divider_reg__1[4]),
.I1(divider_reg__1[2]),
.I2(divider_reg__1[0]),
.I3(divider_reg__1[1]),
.I4(divider_reg__1[3]),
.I5(divider_reg__1[5]),
.O(p_0_in__0[5]));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT2 #(
.INIT(4'h9))
\divider[6]_i_1
(.I0(\busy_sr[0]_i_3_n_0 ),
.I1(divider_reg__0[6]),
.O(p_0_in__0[6]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT3 #(
.INIT(8'hD2))
\divider[7]_i_2
(.I0(divider_reg__0[6]),
.I1(\busy_sr[0]_i_3_n_0 ),
.I2(divider_reg__0[7]),
.O(p_0_in__0[7]));
FDRE #(
.INIT(1'b1))
\divider_reg[0]
(.C(clk),
.CE(\busy_sr_reg[31]_1 ),
.D(p_0_in__0[0]),
.Q(divider_reg__1[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\divider_reg[1]
(.C(clk),
.CE(\busy_sr_reg[31]_1 ),
.D(p_0_in__0[1]),
.Q(divider_reg__1[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\divider_reg[2]
(.C(clk),
.CE(\busy_sr_reg[31]_1 ),
.D(p_0_in__0[2]),
.Q(divider_reg__1[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\divider_reg[3]
(.C(clk),
.CE(\busy_sr_reg[31]_1 ),
.D(p_0_in__0[3]),
.Q(divider_reg__1[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\divider_reg[4]
(.C(clk),
.CE(\busy_sr_reg[31]_1 ),
.D(p_0_in__0[4]),
.Q(divider_reg__1[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\divider_reg[5]
(.C(clk),
.CE(\busy_sr_reg[31]_1 ),
.D(p_0_in__0[5]),
.Q(divider_reg__1[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\divider_reg[6]
(.C(clk),
.CE(\busy_sr_reg[31]_1 ),
.D(p_0_in__0[6]),
.Q(divider_reg__0[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\divider_reg[7]
(.C(clk),
.CE(\busy_sr_reg[31]_1 ),
.D(p_0_in__0[7]),
.Q(divider_reg__0[7]),
.R(1'b0));
LUT6 #(
.INIT(64'hFCFCFFF8FFFFFFFF))
sioc_i_1
(.I0(\busy_sr_reg_n_0_[0] ),
.I1(sioc_i_2_n_0),
.I2(sioc_i_3_n_0),
.I3(\busy_sr_reg_n_0_[1] ),
.I4(sioc_i_4_n_0),
.I5(p_0_in),
.O(sioc_i_1_n_0));
LUT2 #(
.INIT(4'h6))
sioc_i_2
(.I0(divider_reg__0[6]),
.I1(divider_reg__0[7]),
.O(sioc_i_2_n_0));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT4 #(
.INIT(16'hA222))
sioc_i_3
(.I0(sioc_i_5_n_0),
.I1(\busy_sr_reg_n_0_[30] ),
.I2(divider_reg__0[6]),
.I3(p_0_in),
.O(sioc_i_3_n_0));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT4 #(
.INIT(16'h7FFF))
sioc_i_4
(.I0(\busy_sr_reg_n_0_[29] ),
.I1(\busy_sr_reg_n_0_[2] ),
.I2(p_0_in),
.I3(\busy_sr_reg_n_0_[30] ),
.O(sioc_i_4_n_0));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT4 #(
.INIT(16'h0001))
sioc_i_5
(.I0(\busy_sr_reg_n_0_[0] ),
.I1(\busy_sr_reg_n_0_[1] ),
.I2(\busy_sr_reg_n_0_[29] ),
.I3(\busy_sr_reg_n_0_[2] ),
.O(sioc_i_5_n_0));
FDRE sioc_reg
(.C(clk),
.CE(1'b1),
.D(sioc_i_1_n_0),
.Q(sioc),
.R(1'b0));
LUT2 #(
.INIT(4'h8))
siod_INST_0
(.I0(\data_sr_reg_n_0_[31] ),
.I1(siod_INST_0_i_1_n_0),
.O(siod));
LUT6 #(
.INIT(64'hB0BBB0BB0000B0BB))
siod_INST_0_i_1
(.I0(\busy_sr_reg_n_0_[28] ),
.I1(\busy_sr_reg_n_0_[29] ),
.I2(p_1_in_0[0]),
.I3(p_1_in_0[1]),
.I4(\busy_sr_reg_n_0_[11] ),
.I5(\busy_sr_reg_n_0_[10] ),
.O(siod_INST_0_i_1_n_0));
FDRE taken_reg
(.C(clk),
.CE(1'b1),
.D(\busy_sr_reg[31]_0 ),
.Q(E),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "ov7670_controller" *)
module system_ov7670_controller_0_0_ov7670_controller
(config_finished,
siod,
xclk,
sioc,
resend,
clk);
output config_finished;
output siod;
output xclk;
output sioc;
input resend;
input clk;
wire Inst_i2c_sender_n_3;
wire Inst_ov7670_registers_n_16;
wire Inst_ov7670_registers_n_18;
wire clk;
wire config_finished;
wire p_0_in;
wire [0:0]p_1_in;
wire resend;
wire sioc;
wire siod;
wire [15:0]sreg_reg;
wire sys_clk_i_1_n_0;
wire taken;
wire xclk;
system_ov7670_controller_0_0_i2c_sender Inst_i2c_sender
(.DOADO(sreg_reg),
.E(taken),
.\busy_sr_reg[1]_0 (Inst_i2c_sender_n_3),
.\busy_sr_reg[31]_0 (Inst_ov7670_registers_n_18),
.\busy_sr_reg[31]_1 (Inst_ov7670_registers_n_16),
.clk(clk),
.p_0_in(p_0_in),
.p_1_in(p_1_in),
.sioc(sioc),
.siod(siod));
system_ov7670_controller_0_0_ov7670_registers Inst_ov7670_registers
(.DOADO(sreg_reg),
.E(taken),
.clk(clk),
.config_finished(config_finished),
.\divider_reg[2] (Inst_i2c_sender_n_3),
.\divider_reg[7] (Inst_ov7670_registers_n_16),
.p_0_in(p_0_in),
.p_1_in(p_1_in),
.resend(resend),
.taken_reg(Inst_ov7670_registers_n_18));
LUT1 #(
.INIT(2'h1))
sys_clk_i_1
(.I0(xclk),
.O(sys_clk_i_1_n_0));
FDRE #(
.INIT(1'b0))
sys_clk_reg
(.C(clk),
.CE(1'b1),
.D(sys_clk_i_1_n_0),
.Q(xclk),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "ov7670_registers" *)
module system_ov7670_controller_0_0_ov7670_registers
(DOADO,
\divider_reg[7] ,
config_finished,
taken_reg,
p_1_in,
clk,
\divider_reg[2] ,
p_0_in,
resend,
E);
output [15:0]DOADO;
output [0:0]\divider_reg[7] ;
output config_finished;
output taken_reg;
output [0:0]p_1_in;
input clk;
input \divider_reg[2] ;
input p_0_in;
input resend;
input [0:0]E;
wire [15:0]DOADO;
wire [0:0]E;
wire [7:0]address;
wire [7:0]address_reg__0;
wire \address_rep[0]_i_1_n_0 ;
wire \address_rep[1]_i_1_n_0 ;
wire \address_rep[2]_i_1_n_0 ;
wire \address_rep[3]_i_1_n_0 ;
wire \address_rep[4]_i_1_n_0 ;
wire \address_rep[5]_i_1_n_0 ;
wire \address_rep[6]_i_1_n_0 ;
wire \address_rep[7]_i_1_n_0 ;
wire \address_rep[7]_i_2_n_0 ;
wire clk;
wire config_finished;
wire config_finished_INST_0_i_1_n_0;
wire config_finished_INST_0_i_2_n_0;
wire config_finished_INST_0_i_3_n_0;
wire config_finished_INST_0_i_4_n_0;
wire \divider_reg[2] ;
wire [0:0]\divider_reg[7] ;
wire p_0_in;
wire [0:0]p_1_in;
wire resend;
wire taken_reg;
wire [15:0]NLW_sreg_reg_DOBDO_UNCONNECTED;
wire [1:0]NLW_sreg_reg_DOPADOP_UNCONNECTED;
wire [1:0]NLW_sreg_reg_DOPBDOP_UNCONNECTED;
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg[0]
(.C(clk),
.CE(E),
.D(\address_rep[0]_i_1_n_0 ),
.Q(address_reg__0[0]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg[1]
(.C(clk),
.CE(E),
.D(\address_rep[1]_i_1_n_0 ),
.Q(address_reg__0[1]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg[2]
(.C(clk),
.CE(E),
.D(\address_rep[2]_i_1_n_0 ),
.Q(address_reg__0[2]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg[3]
(.C(clk),
.CE(E),
.D(\address_rep[3]_i_1_n_0 ),
.Q(address_reg__0[3]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg[4]
(.C(clk),
.CE(E),
.D(\address_rep[4]_i_1_n_0 ),
.Q(address_reg__0[4]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg[5]
(.C(clk),
.CE(E),
.D(\address_rep[5]_i_1_n_0 ),
.Q(address_reg__0[5]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg[6]
(.C(clk),
.CE(E),
.D(\address_rep[6]_i_1_n_0 ),
.Q(address_reg__0[6]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg[7]
(.C(clk),
.CE(E),
.D(\address_rep[7]_i_1_n_0 ),
.Q(address_reg__0[7]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg_rep[0]
(.C(clk),
.CE(E),
.D(\address_rep[0]_i_1_n_0 ),
.Q(address[0]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg_rep[1]
(.C(clk),
.CE(E),
.D(\address_rep[1]_i_1_n_0 ),
.Q(address[1]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg_rep[2]
(.C(clk),
.CE(E),
.D(\address_rep[2]_i_1_n_0 ),
.Q(address[2]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg_rep[3]
(.C(clk),
.CE(E),
.D(\address_rep[3]_i_1_n_0 ),
.Q(address[3]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg_rep[4]
(.C(clk),
.CE(E),
.D(\address_rep[4]_i_1_n_0 ),
.Q(address[4]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg_rep[5]
(.C(clk),
.CE(E),
.D(\address_rep[5]_i_1_n_0 ),
.Q(address[5]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg_rep[6]
(.C(clk),
.CE(E),
.D(\address_rep[6]_i_1_n_0 ),
.Q(address[6]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg_rep[7]
(.C(clk),
.CE(E),
.D(\address_rep[7]_i_1_n_0 ),
.Q(address[7]),
.R(resend));
LUT1 #(
.INIT(2'h1))
\address_rep[0]_i_1
(.I0(address_reg__0[0]),
.O(\address_rep[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT2 #(
.INIT(4'h6))
\address_rep[1]_i_1
(.I0(address_reg__0[0]),
.I1(address_reg__0[1]),
.O(\address_rep[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT3 #(
.INIT(8'h78))
\address_rep[2]_i_1
(.I0(address_reg__0[1]),
.I1(address_reg__0[0]),
.I2(address_reg__0[2]),
.O(\address_rep[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT4 #(
.INIT(16'h7F80))
\address_rep[3]_i_1
(.I0(address_reg__0[2]),
.I1(address_reg__0[0]),
.I2(address_reg__0[1]),
.I3(address_reg__0[3]),
.O(\address_rep[3]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT5 #(
.INIT(32'h7FFF8000))
\address_rep[4]_i_1
(.I0(address_reg__0[3]),
.I1(address_reg__0[1]),
.I2(address_reg__0[0]),
.I3(address_reg__0[2]),
.I4(address_reg__0[4]),
.O(\address_rep[4]_i_1_n_0 ));
LUT6 #(
.INIT(64'h7FFFFFFF80000000))
\address_rep[5]_i_1
(.I0(address_reg__0[4]),
.I1(address_reg__0[2]),
.I2(address_reg__0[0]),
.I3(address_reg__0[1]),
.I4(address_reg__0[3]),
.I5(address_reg__0[5]),
.O(\address_rep[5]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT2 #(
.INIT(4'h9))
\address_rep[6]_i_1
(.I0(\address_rep[7]_i_2_n_0 ),
.I1(address_reg__0[6]),
.O(\address_rep[6]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT3 #(
.INIT(8'hD2))
\address_rep[7]_i_1
(.I0(address_reg__0[6]),
.I1(\address_rep[7]_i_2_n_0 ),
.I2(address_reg__0[7]),
.O(\address_rep[7]_i_1_n_0 ));
LUT6 #(
.INIT(64'h7FFFFFFFFFFFFFFF))
\address_rep[7]_i_2
(.I0(address_reg__0[4]),
.I1(address_reg__0[2]),
.I2(address_reg__0[0]),
.I3(address_reg__0[1]),
.I4(address_reg__0[3]),
.I5(address_reg__0[5]),
.O(\address_rep[7]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT5 #(
.INIT(32'h0000FFFE))
\busy_sr[0]_i_2
(.I0(config_finished_INST_0_i_4_n_0),
.I1(config_finished_INST_0_i_3_n_0),
.I2(config_finished_INST_0_i_2_n_0),
.I3(config_finished_INST_0_i_1_n_0),
.I4(p_0_in),
.O(p_1_in));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT4 #(
.INIT(16'h0001))
config_finished_INST_0
(.I0(config_finished_INST_0_i_1_n_0),
.I1(config_finished_INST_0_i_2_n_0),
.I2(config_finished_INST_0_i_3_n_0),
.I3(config_finished_INST_0_i_4_n_0),
.O(config_finished));
LUT4 #(
.INIT(16'h7FFF))
config_finished_INST_0_i_1
(.I0(DOADO[5]),
.I1(DOADO[4]),
.I2(DOADO[7]),
.I3(DOADO[6]),
.O(config_finished_INST_0_i_1_n_0));
LUT4 #(
.INIT(16'h7FFF))
config_finished_INST_0_i_2
(.I0(DOADO[1]),
.I1(DOADO[0]),
.I2(DOADO[3]),
.I3(DOADO[2]),
.O(config_finished_INST_0_i_2_n_0));
LUT4 #(
.INIT(16'h7FFF))
config_finished_INST_0_i_3
(.I0(DOADO[13]),
.I1(DOADO[12]),
.I2(DOADO[15]),
.I3(DOADO[14]),
.O(config_finished_INST_0_i_3_n_0));
LUT4 #(
.INIT(16'h7FFF))
config_finished_INST_0_i_4
(.I0(DOADO[9]),
.I1(DOADO[8]),
.I2(DOADO[11]),
.I3(DOADO[10]),
.O(config_finished_INST_0_i_4_n_0));
LUT6 #(
.INIT(64'hFFFFFFFFFFFE0000))
\divider[7]_i_1
(.I0(config_finished_INST_0_i_1_n_0),
.I1(config_finished_INST_0_i_2_n_0),
.I2(config_finished_INST_0_i_3_n_0),
.I3(config_finished_INST_0_i_4_n_0),
.I4(\divider_reg[2] ),
.I5(p_0_in),
.O(\divider_reg[7] ));
(* CLOCK_DOMAINS = "INDEPENDENT" *)
(* \MEM.PORTA.DATA_BIT_LAYOUT = "p0_d16" *)
(* METHODOLOGY_DRC_VIOS = "{SYNTH-6 {cell *THIS*}}" *)
(* RTL_RAM_BITS = "4096" *)
(* RTL_RAM_NAME = "U0/Inst_ov7670_registers/sreg" *)
(* bram_addr_begin = "0" *)
(* bram_addr_end = "1023" *)
(* bram_slice_begin = "0" *)
(* bram_slice_end = "15" *)
RAMB18E1 #(
.DOA_REG(0),
.DOB_REG(0),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h53295217510C50344F4014383A04401004008C003E000C001100120412801280),
.INIT_01(256'h229121021E3716020F4B0E61030A1A7B190332A41861171111003DC0581E5440),
.INIT_02(256'h90008F008E008D4F74106B4A69004E204D403C78392A3871371D350B330B2907),
.INIT_03(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFB80AB382B20EB10CB0849A0096009100),
.INIT_04(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_05(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_06(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_07(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_08(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_09(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_0A(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_0B(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_0C(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_0D(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_0E(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_0F(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(18'h00000),
.INIT_B(18'h00000),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(18),
.READ_WIDTH_B(0),
.RSTREG_PRIORITY_A("RSTREG"),
.RSTREG_PRIORITY_B("RSTREG"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(18'h00000),
.SRVAL_B(18'h00000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(18),
.WRITE_WIDTH_B(0))
sreg_reg
(.ADDRARDADDR({1'b0,1'b0,address,1'b0,1'b0,1'b0,1'b0}),
.ADDRBWRADDR({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CLKARDCLK(clk),
.CLKBWRCLK(1'b0),
.DIADI({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.DIBDI({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.DIPADIP({1'b0,1'b0}),
.DIPBDIP({1'b1,1'b1}),
.DOADO(DOADO),
.DOBDO(NLW_sreg_reg_DOBDO_UNCONNECTED[15:0]),
.DOPADOP(NLW_sreg_reg_DOPADOP_UNCONNECTED[1:0]),
.DOPBDOP(NLW_sreg_reg_DOPBDOP_UNCONNECTED[1:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.WEA({1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0}));
LUT6 #(
.INIT(64'h0000000055555554))
taken_i_1
(.I0(p_0_in),
.I1(config_finished_INST_0_i_1_n_0),
.I2(config_finished_INST_0_i_2_n_0),
.I3(config_finished_INST_0_i_3_n_0),
.I4(config_finished_INST_0_i_4_n_0),
.I5(\divider_reg[2] ),
.O(taken_reg));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Mon Feb 13 12:47:17 2017
// Host : WK117 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// C:/Users/aholzer/Documents/new/Arty-BSD/src/bd/system/ip/system_axi_iic_0_0/system_axi_iic_0_0_sim_netlist.v
// Design : system_axi_iic_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7a35ticsg324-1L
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "system_axi_iic_0_0,axi_iic,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "axi_iic,Vivado 2016.4" *)
(* NotValidForBitStream *)
module system_axi_iic_0_0
(s_axi_aclk,
s_axi_aresetn,
iic2intc_irpt,
s_axi_awaddr,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rvalid,
s_axi_rready,
sda_i,
sda_o,
sda_t,
scl_i,
scl_o,
scl_t,
gpo);
(* x_interface_info = "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK" *) input s_axi_aclk;
(* x_interface_info = "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST" *) input s_axi_aresetn;
(* x_interface_info = "xilinx.com:signal:interrupt:1.0 INTERRUPT INTERRUPT" *) output iic2intc_irpt;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *) input [8:0]s_axi_awaddr;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *) input s_axi_awvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *) output s_axi_awready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *) input [31:0]s_axi_wdata;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *) input [3:0]s_axi_wstrb;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *) input s_axi_wvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *) output s_axi_wready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *) output [1:0]s_axi_bresp;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *) output s_axi_bvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *) input s_axi_bready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *) input [8:0]s_axi_araddr;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *) input s_axi_arvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *) output s_axi_arready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *) output [31:0]s_axi_rdata;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *) output [1:0]s_axi_rresp;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *) output s_axi_rvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *) input s_axi_rready;
(* x_interface_info = "xilinx.com:interface:iic:1.0 IIC SDA_I" *) input sda_i;
(* x_interface_info = "xilinx.com:interface:iic:1.0 IIC SDA_O" *) output sda_o;
(* x_interface_info = "xilinx.com:interface:iic:1.0 IIC SDA_T" *) output sda_t;
(* x_interface_info = "xilinx.com:interface:iic:1.0 IIC SCL_I" *) input scl_i;
(* x_interface_info = "xilinx.com:interface:iic:1.0 IIC SCL_O" *) output scl_o;
(* x_interface_info = "xilinx.com:interface:iic:1.0 IIC SCL_T" *) output scl_t;
output [0:0]gpo;
wire [0:0]gpo;
wire iic2intc_irpt;
wire s_axi_aclk;
wire [8:0]s_axi_araddr;
wire s_axi_aresetn;
wire s_axi_arready;
wire s_axi_arvalid;
wire [8:0]s_axi_awaddr;
wire s_axi_awready;
wire s_axi_awvalid;
wire s_axi_bready;
wire [1:0]s_axi_bresp;
wire s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire s_axi_rready;
wire [1:0]s_axi_rresp;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire s_axi_wready;
wire [3:0]s_axi_wstrb;
wire s_axi_wvalid;
wire scl_i;
wire scl_o;
wire scl_t;
wire sda_i;
wire sda_o;
wire sda_t;
(* C_DEFAULT_VALUE = "8'b00000000" *)
(* C_FAMILY = "artix7" *)
(* C_GPO_WIDTH = "1" *)
(* C_IIC_FREQ = "100000" *)
(* C_SCL_INERTIAL_DELAY = "0" *)
(* C_SDA_INERTIAL_DELAY = "0" *)
(* C_SDA_LEVEL = "1" *)
(* C_SMBUS_PMBUS_HOST = "0" *)
(* C_S_AXI_ACLK_FREQ_HZ = "100000000" *)
(* C_S_AXI_ADDR_WIDTH = "9" *)
(* C_S_AXI_DATA_WIDTH = "32" *)
(* C_TEN_BIT_ADR = "0" *)
(* downgradeipidentifiedwarnings = "yes" *)
system_axi_iic_0_0_axi_iic U0
(.gpo(gpo),
.iic2intc_irpt(iic2intc_irpt),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr(s_axi_araddr),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awready(s_axi_awready),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(s_axi_bresp),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(s_axi_rresp),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wready(s_axi_wready),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wvalid(s_axi_wvalid),
.scl_i(scl_i),
.scl_o(scl_o),
.scl_t(scl_t),
.sda_i(sda_i),
.sda_o(sda_o),
.sda_t(sda_t));
endmodule
(* ORIG_REF_NAME = "SRL_FIFO" *)
module system_axi_iic_0_0_SRL_FIFO
(Rc_Data_Exists,
Rc_addr,
Rc_fifo_data,
p_6_out,
D,
Data_Exists_DFF_0,
Bus2IIC_Reset,
D_0,
s_axi_aclk,
\data_i2c_i_reg[7] ,
Q,
Msms_set,
\RD_FIFO_CNTRL.Rc_fifo_rd_reg ,
\RD_FIFO_CNTRL.Rc_fifo_wr_reg ,
Rc_fifo_rd,
Rc_fifo_rd_d,
Rc_fifo_wr_d,
Rc_fifo_wr);
output Rc_Data_Exists;
output [0:3]Rc_addr;
output [0:7]Rc_fifo_data;
output p_6_out;
output [1:0]D;
output Data_Exists_DFF_0;
input Bus2IIC_Reset;
input D_0;
input s_axi_aclk;
input [7:0]\data_i2c_i_reg[7] ;
input [3:0]Q;
input Msms_set;
input \RD_FIFO_CNTRL.Rc_fifo_rd_reg ;
input \RD_FIFO_CNTRL.Rc_fifo_wr_reg ;
input Rc_fifo_rd;
input Rc_fifo_rd_d;
input Rc_fifo_wr_d;
input Rc_fifo_wr;
wire \Addr_Counters[0].MUXCY_L_I_i_3__1_n_0 ;
wire \Addr_Counters[3].XORCY_I_i_1__1_n_0 ;
wire Bus2IIC_Reset;
wire CI;
wire [1:0]D;
wire D_0;
wire Data_Exists_DFF_0;
wire Msms_set;
wire [3:0]Q;
wire \RD_FIFO_CNTRL.Rc_fifo_rd_reg ;
wire \RD_FIFO_CNTRL.Rc_fifo_wr_reg ;
wire \RD_FIFO_CNTRL.ro_prev_i_i_2_n_0 ;
wire \RD_FIFO_CNTRL.ro_prev_i_i_3_n_0 ;
wire Rc_Data_Exists;
wire [0:3]Rc_addr;
wire [0:7]Rc_fifo_data;
wire Rc_fifo_rd;
wire Rc_fifo_rd_d;
wire Rc_fifo_wr;
wire Rc_fifo_wr_d;
wire S;
wire S0_out;
wire S1_out;
wire addr_cy_1;
wire addr_cy_2;
wire addr_cy_3;
wire [7:0]\data_i2c_i_reg[7] ;
wire p_6_out;
wire s_axi_aclk;
wire sum_A_0;
wire sum_A_1;
wire sum_A_2;
wire sum_A_3;
wire [3:3]\NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_CO_UNCONNECTED ;
wire [3:3]\NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_DI_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\Addr_Counters[0].FDRE_I
(.C(s_axi_aclk),
.CE(Rc_Data_Exists),
.D(sum_A_3),
.Q(Rc_addr[0]),
.R(Bus2IIC_Reset));
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* XILINX_TRANSFORM_PINMAP = "LO:O" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \Addr_Counters[0].MUXCY_L_I_CARRY4
(.CI(1'b0),
.CO({\NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_CO_UNCONNECTED [3],addr_cy_1,addr_cy_2,addr_cy_3}),
.CYINIT(CI),
.DI({\NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_DI_UNCONNECTED [3],Rc_addr[2],Rc_addr[1],Rc_addr[0]}),
.O({sum_A_0,sum_A_1,sum_A_2,sum_A_3}),
.S({\Addr_Counters[3].XORCY_I_i_1__1_n_0 ,S0_out,S1_out,S}));
LUT4 #(
.INIT(16'hA208))
\Addr_Counters[0].MUXCY_L_I_i_1__1
(.I0(\Addr_Counters[0].MUXCY_L_I_i_3__1_n_0 ),
.I1(Rc_fifo_rd),
.I2(Rc_fifo_rd_d),
.I3(Rc_addr[0]),
.O(S));
LUT6 #(
.INIT(64'hFFFF7FFF00000000))
\Addr_Counters[0].MUXCY_L_I_i_2__0
(.I0(Rc_addr[1]),
.I1(Rc_addr[2]),
.I2(Rc_addr[3]),
.I3(Rc_addr[0]),
.I4(\RD_FIFO_CNTRL.Rc_fifo_rd_reg ),
.I5(\RD_FIFO_CNTRL.Rc_fifo_wr_reg ),
.O(CI));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFF4))
\Addr_Counters[0].MUXCY_L_I_i_3__1
(.I0(Rc_fifo_wr_d),
.I1(Rc_fifo_wr),
.I2(Rc_addr[0]),
.I3(Rc_addr[3]),
.I4(Rc_addr[2]),
.I5(Rc_addr[1]),
.O(\Addr_Counters[0].MUXCY_L_I_i_3__1_n_0 ));
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\Addr_Counters[1].FDRE_I
(.C(s_axi_aclk),
.CE(Rc_Data_Exists),
.D(sum_A_2),
.Q(Rc_addr[1]),
.R(Bus2IIC_Reset));
LUT4 #(
.INIT(16'hA208))
\Addr_Counters[1].MUXCY_L_I_i_1__1
(.I0(\Addr_Counters[0].MUXCY_L_I_i_3__1_n_0 ),
.I1(Rc_fifo_rd),
.I2(Rc_fifo_rd_d),
.I3(Rc_addr[1]),
.O(S1_out));
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\Addr_Counters[2].FDRE_I
(.C(s_axi_aclk),
.CE(Rc_Data_Exists),
.D(sum_A_1),
.Q(Rc_addr[2]),
.R(Bus2IIC_Reset));
LUT4 #(
.INIT(16'hA208))
\Addr_Counters[2].MUXCY_L_I_i_1__1
(.I0(\Addr_Counters[0].MUXCY_L_I_i_3__1_n_0 ),
.I1(Rc_fifo_rd),
.I2(Rc_fifo_rd_d),
.I3(Rc_addr[2]),
.O(S0_out));
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\Addr_Counters[3].FDRE_I
(.C(s_axi_aclk),
.CE(Rc_Data_Exists),
.D(sum_A_0),
.Q(Rc_addr[3]),
.R(Bus2IIC_Reset));
LUT4 #(
.INIT(16'hA208))
\Addr_Counters[3].XORCY_I_i_1__1
(.I0(\Addr_Counters[0].MUXCY_L_I_i_3__1_n_0 ),
.I1(Rc_fifo_rd),
.I2(Rc_fifo_rd_d),
.I3(Rc_addr[3]),
.O(\Addr_Counters[3].XORCY_I_i_1__1_n_0 ));
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
Data_Exists_DFF
(.C(s_axi_aclk),
.CE(1'b1),
.D(D_0),
.Q(Rc_Data_Exists),
.R(Bus2IIC_Reset));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT4 #(
.INIT(16'hFFFE))
Data_Exists_DFF_i_2__1
(.I0(Rc_addr[1]),
.I1(Rc_addr[2]),
.I2(Rc_addr[3]),
.I3(Rc_addr[0]),
.O(Data_Exists_DFF_0));
(* box_type = "PRIMITIVE" *)
(* srl_bus_name = "U0/\X_IIC/READ_FIFO_I/FIFO_RAM " *)
(* srl_name = "U0/\X_IIC/READ_FIFO_I/FIFO_RAM[0].SRL16E_I " *)
SRL16E #(
.INIT(16'h0000),
.IS_CLK_INVERTED(1'b0))
\FIFO_RAM[0].SRL16E_I
(.A0(Rc_addr[0]),
.A1(Rc_addr[1]),
.A2(Rc_addr[2]),
.A3(Rc_addr[3]),
.CE(CI),
.CLK(s_axi_aclk),
.D(\data_i2c_i_reg[7] [7]),
.Q(Rc_fifo_data[0]));
(* box_type = "PRIMITIVE" *)
(* srl_bus_name = "U0/\X_IIC/READ_FIFO_I/FIFO_RAM " *)
(* srl_name = "U0/\X_IIC/READ_FIFO_I/FIFO_RAM[1].SRL16E_I " *)
SRL16E #(
.INIT(16'h0000),
.IS_CLK_INVERTED(1'b0))
\FIFO_RAM[1].SRL16E_I
(.A0(Rc_addr[0]),
.A1(Rc_addr[1]),
.A2(Rc_addr[2]),
.A3(Rc_addr[3]),
.CE(CI),
.CLK(s_axi_aclk),
.D(\data_i2c_i_reg[7] [6]),
.Q(Rc_fifo_data[1]));
(* box_type = "PRIMITIVE" *)
(* srl_bus_name = "U0/\X_IIC/READ_FIFO_I/FIFO_RAM " *)
(* srl_name = "U0/\X_IIC/READ_FIFO_I/FIFO_RAM[2].SRL16E_I " *)
SRL16E #(
.INIT(16'h0000),
.IS_CLK_INVERTED(1'b0))
\FIFO_RAM[2].SRL16E_I
(.A0(Rc_addr[0]),
.A1(Rc_addr[1]),
.A2(Rc_addr[2]),
.A3(Rc_addr[3]),
.CE(CI),
.CLK(s_axi_aclk),
.D(\data_i2c_i_reg[7] [5]),
.Q(Rc_fifo_data[2]));
(* box_type = "PRIMITIVE" *)
(* srl_bus_name = "U0/\X_IIC/READ_FIFO_I/FIFO_RAM " *)
(* srl_name = "U0/\X_IIC/READ_FIFO_I/FIFO_RAM[3].SRL16E_I " *)
SRL16E #(
.INIT(16'h0000),
.IS_CLK_INVERTED(1'b0))
\FIFO_RAM[3].SRL16E_I
(.A0(Rc_addr[0]),
.A1(Rc_addr[1]),
.A2(Rc_addr[2]),
.A3(Rc_addr[3]),
.CE(CI),
.CLK(s_axi_aclk),
.D(\data_i2c_i_reg[7] [4]),
.Q(Rc_fifo_data[3]));
(* box_type = "PRIMITIVE" *)
(* srl_bus_name = "U0/\X_IIC/READ_FIFO_I/FIFO_RAM " *)
(* srl_name = "U0/\X_IIC/READ_FIFO_I/FIFO_RAM[4].SRL16E_I " *)
SRL16E #(
.INIT(16'h0000),
.IS_CLK_INVERTED(1'b0))
\FIFO_RAM[4].SRL16E_I
(.A0(Rc_addr[0]),
.A1(Rc_addr[1]),
.A2(Rc_addr[2]),
.A3(Rc_addr[3]),
.CE(CI),
.CLK(s_axi_aclk),
.D(\data_i2c_i_reg[7] [3]),
.Q(Rc_fifo_data[4]));
(* box_type = "PRIMITIVE" *)
(* srl_bus_name = "U0/\X_IIC/READ_FIFO_I/FIFO_RAM " *)
(* srl_name = "U0/\X_IIC/READ_FIFO_I/FIFO_RAM[5].SRL16E_I " *)
SRL16E #(
.INIT(16'h0000),
.IS_CLK_INVERTED(1'b0))
\FIFO_RAM[5].SRL16E_I
(.A0(Rc_addr[0]),
.A1(Rc_addr[1]),
.A2(Rc_addr[2]),
.A3(Rc_addr[3]),
.CE(CI),
.CLK(s_axi_aclk),
.D(\data_i2c_i_reg[7] [2]),
.Q(Rc_fifo_data[5]));
(* box_type = "PRIMITIVE" *)
(* srl_bus_name = "U0/\X_IIC/READ_FIFO_I/FIFO_RAM " *)
(* srl_name = "U0/\X_IIC/READ_FIFO_I/FIFO_RAM[6].SRL16E_I " *)
SRL16E #(
.INIT(16'h0000),
.IS_CLK_INVERTED(1'b0))
\FIFO_RAM[6].SRL16E_I
(.A0(Rc_addr[0]),
.A1(Rc_addr[1]),
.A2(Rc_addr[2]),
.A3(Rc_addr[3]),
.CE(CI),
.CLK(s_axi_aclk),
.D(\data_i2c_i_reg[7] [1]),
.Q(Rc_fifo_data[6]));
(* box_type = "PRIMITIVE" *)
(* srl_bus_name = "U0/\X_IIC/READ_FIFO_I/FIFO_RAM " *)
(* srl_name = "U0/\X_IIC/READ_FIFO_I/FIFO_RAM[7].SRL16E_I " *)
SRL16E #(
.INIT(16'h0000),
.IS_CLK_INVERTED(1'b0))
\FIFO_RAM[7].SRL16E_I
(.A0(Rc_addr[0]),
.A1(Rc_addr[1]),
.A2(Rc_addr[2]),
.A3(Rc_addr[3]),
.CE(CI),
.CLK(s_axi_aclk),
.D(\data_i2c_i_reg[7] [0]),
.Q(Rc_fifo_data[7]));
LUT6 #(
.INIT(64'h0000000004000004))
\RD_FIFO_CNTRL.ro_prev_i_i_1
(.I0(\RD_FIFO_CNTRL.ro_prev_i_i_2_n_0 ),
.I1(\RD_FIFO_CNTRL.ro_prev_i_i_3_n_0 ),
.I2(Bus2IIC_Reset),
.I3(Rc_addr[2]),
.I4(Q[2]),
.I5(Msms_set),
.O(p_6_out));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT3 #(
.INIT(8'h6F))
\RD_FIFO_CNTRL.ro_prev_i_i_2
(.I0(Rc_addr[0]),
.I1(Q[0]),
.I2(Rc_Data_Exists),
.O(\RD_FIFO_CNTRL.ro_prev_i_i_2_n_0 ));
LUT4 #(
.INIT(16'h9009))
\RD_FIFO_CNTRL.ro_prev_i_i_3
(.I0(Rc_addr[3]),
.I1(Q[3]),
.I2(Rc_addr[1]),
.I3(Q[1]),
.O(\RD_FIFO_CNTRL.ro_prev_i_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT1 #(
.INIT(2'h1))
\sr_i[1]_i_1
(.I0(Rc_Data_Exists),
.O(D[1]));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT4 #(
.INIT(16'h8000))
\sr_i[2]_i_1
(.I0(Rc_addr[1]),
.I1(Rc_addr[2]),
.I2(Rc_addr[3]),
.I3(Rc_addr[0]),
.O(D[0]));
endmodule
(* ORIG_REF_NAME = "SRL_FIFO" *)
module system_axi_iic_0_0_SRL_FIFO_0
(Tx_data_exists,
Tx_addr,
Tx_fifo_data,
\sr_i_reg[3] ,
p_3_in,
\cr_i_reg[5] ,
\sr_i_reg[0] ,
\FIFO_GEN_DTR.IIC2Bus_IntrEvent_reg[7] ,
Data_Exists_DFF_0,
\data_int_reg[0] ,
Tx_fifo_rst,
D,
s_axi_aclk,
s_axi_wdata,
\FIFO_GEN_DTR.Tx_fifo_rd_reg ,
\FIFO_GEN_DTR.Tx_fifo_wr_reg ,
dynamic_MSMS,
Tx_fifo_rd_d,
Tx_fifo_rd,
rdCntrFrmTxFifo,
Tx_fifo_wr_d,
Tx_fifo_wr,
shift_reg_ld,
scndry_out);
output Tx_data_exists;
output [0:3]Tx_addr;
output [0:7]Tx_fifo_data;
output [0:0]\sr_i_reg[3] ;
output p_3_in;
output \cr_i_reg[5] ;
output \sr_i_reg[0] ;
output \FIFO_GEN_DTR.IIC2Bus_IntrEvent_reg[7] ;
output Data_Exists_DFF_0;
output [0:0]\data_int_reg[0] ;
input Tx_fifo_rst;
input D;
input s_axi_aclk;
input [7:0]s_axi_wdata;
input \FIFO_GEN_DTR.Tx_fifo_rd_reg ;
input \FIFO_GEN_DTR.Tx_fifo_wr_reg ;
input [0:0]dynamic_MSMS;
input Tx_fifo_rd_d;
input Tx_fifo_rd;
input rdCntrFrmTxFifo;
input Tx_fifo_wr_d;
input Tx_fifo_wr;
input shift_reg_ld;
input scndry_out;
wire \Addr_Counters[0].MUXCY_L_I_i_3__0_n_0 ;
wire \Addr_Counters[3].XORCY_I_i_1__0_n_0 ;
wire CI;
wire D;
wire Data_Exists_DFF_0;
wire \FIFO_GEN_DTR.IIC2Bus_IntrEvent_reg[7] ;
wire \FIFO_GEN_DTR.Tx_fifo_rd_reg ;
wire \FIFO_GEN_DTR.Tx_fifo_wr_reg ;
wire S;
wire S0_out;
wire S1_out;
wire [0:3]Tx_addr;
wire Tx_data_exists;
wire [0:7]Tx_fifo_data;
wire Tx_fifo_rd;
wire Tx_fifo_rd_d;
wire Tx_fifo_rst;
wire Tx_fifo_wr;
wire Tx_fifo_wr_d;
wire addr_cy_1;
wire addr_cy_2;
wire addr_cy_3;
wire \cr_i_reg[5] ;
wire [0:0]\data_int_reg[0] ;
wire [0:0]dynamic_MSMS;
wire p_3_in;
wire rdCntrFrmTxFifo;
wire s_axi_aclk;
wire [7:0]s_axi_wdata;
wire scndry_out;
wire shift_reg_ld;
wire \sr_i_reg[0] ;
wire [0:0]\sr_i_reg[3] ;
wire sum_A_0;
wire sum_A_1;
wire sum_A_2;
wire sum_A_3;
wire [3:3]\NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_CO_UNCONNECTED ;
wire [3:3]\NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_DI_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\Addr_Counters[0].FDRE_I
(.C(s_axi_aclk),
.CE(Tx_data_exists),
.D(sum_A_3),
.Q(Tx_addr[0]),
.R(Tx_fifo_rst));
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* XILINX_TRANSFORM_PINMAP = "LO:O" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \Addr_Counters[0].MUXCY_L_I_CARRY4
(.CI(1'b0),
.CO({\NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_CO_UNCONNECTED [3],addr_cy_1,addr_cy_2,addr_cy_3}),
.CYINIT(CI),
.DI({\NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_DI_UNCONNECTED [3],Tx_addr[2],Tx_addr[1],Tx_addr[0]}),
.O({sum_A_0,sum_A_1,sum_A_2,sum_A_3}),
.S({\Addr_Counters[3].XORCY_I_i_1__0_n_0 ,S0_out,S1_out,S}));
LUT5 #(
.INIT(32'h00A2AA08))
\Addr_Counters[0].MUXCY_L_I_i_1__0
(.I0(\Addr_Counters[0].MUXCY_L_I_i_3__0_n_0 ),
.I1(Tx_fifo_rd),
.I2(Tx_fifo_rd_d),
.I3(rdCntrFrmTxFifo),
.I4(Tx_addr[0]),
.O(S));
LUT6 #(
.INIT(64'h7FFFFFFF00000000))
\Addr_Counters[0].MUXCY_L_I_i_2__1
(.I0(\FIFO_GEN_DTR.Tx_fifo_rd_reg ),
.I1(Tx_addr[1]),
.I2(Tx_addr[3]),
.I3(Tx_addr[0]),
.I4(Tx_addr[2]),
.I5(\FIFO_GEN_DTR.Tx_fifo_wr_reg ),
.O(CI));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFF4))
\Addr_Counters[0].MUXCY_L_I_i_3__0
(.I0(Tx_fifo_wr_d),
.I1(Tx_fifo_wr),
.I2(Tx_addr[2]),
.I3(Tx_addr[0]),
.I4(Tx_addr[3]),
.I5(Tx_addr[1]),
.O(\Addr_Counters[0].MUXCY_L_I_i_3__0_n_0 ));
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\Addr_Counters[1].FDRE_I
(.C(s_axi_aclk),
.CE(Tx_data_exists),
.D(sum_A_2),
.Q(Tx_addr[1]),
.R(Tx_fifo_rst));
LUT5 #(
.INIT(32'h00A2AA08))
\Addr_Counters[1].MUXCY_L_I_i_1__0
(.I0(\Addr_Counters[0].MUXCY_L_I_i_3__0_n_0 ),
.I1(Tx_fifo_rd),
.I2(Tx_fifo_rd_d),
.I3(rdCntrFrmTxFifo),
.I4(Tx_addr[1]),
.O(S1_out));
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\Addr_Counters[2].FDRE_I
(.C(s_axi_aclk),
.CE(Tx_data_exists),
.D(sum_A_1),
.Q(Tx_addr[2]),
.R(Tx_fifo_rst));
LUT5 #(
.INIT(32'h00A2AA08))
\Addr_Counters[2].MUXCY_L_I_i_1__0
(.I0(\Addr_Counters[0].MUXCY_L_I_i_3__0_n_0 ),
.I1(Tx_fifo_rd),
.I2(Tx_fifo_rd_d),
.I3(rdCntrFrmTxFifo),
.I4(Tx_addr[2]),
.O(S0_out));
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\Addr_Counters[3].FDRE_I
(.C(s_axi_aclk),
.CE(Tx_data_exists),
.D(sum_A_0),
.Q(Tx_addr[3]),
.R(Tx_fifo_rst));
LUT5 #(
.INIT(32'h00A2AA08))
\Addr_Counters[3].XORCY_I_i_1__0
(.I0(\Addr_Counters[0].MUXCY_L_I_i_3__0_n_0 ),
.I1(Tx_fifo_rd),
.I2(Tx_fifo_rd_d),
.I3(rdCntrFrmTxFifo),
.I4(Tx_addr[3]),
.O(\Addr_Counters[3].XORCY_I_i_1__0_n_0 ));
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
Data_Exists_DFF
(.C(s_axi_aclk),
.CE(1'b1),
.D(D),
.Q(Tx_data_exists),
.R(Tx_fifo_rst));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT4 #(
.INIT(16'hFFFE))
Data_Exists_DFF_i_3
(.I0(Tx_addr[1]),
.I1(Tx_addr[3]),
.I2(Tx_addr[0]),
.I3(Tx_addr[2]),
.O(Data_Exists_DFF_0));
LUT1 #(
.INIT(2'h1))
\FIFO_GEN_DTR.IIC2Bus_IntrEvent[7]_i_1
(.I0(Tx_addr[3]),
.O(\FIFO_GEN_DTR.IIC2Bus_IntrEvent_reg[7] ));
(* box_type = "PRIMITIVE" *)
(* srl_bus_name = "U0/\X_IIC/WRITE_FIFO_I/FIFO_RAM " *)
(* srl_name = "U0/\X_IIC/WRITE_FIFO_I/FIFO_RAM[0].SRL16E_I " *)
SRL16E #(
.INIT(16'h0000),
.IS_CLK_INVERTED(1'b0))
\FIFO_RAM[0].SRL16E_I
(.A0(Tx_addr[0]),
.A1(Tx_addr[1]),
.A2(Tx_addr[2]),
.A3(Tx_addr[3]),
.CE(CI),
.CLK(s_axi_aclk),
.D(s_axi_wdata[7]),
.Q(Tx_fifo_data[0]));
(* box_type = "PRIMITIVE" *)
(* srl_bus_name = "U0/\X_IIC/WRITE_FIFO_I/FIFO_RAM " *)
(* srl_name = "U0/\X_IIC/WRITE_FIFO_I/FIFO_RAM[1].SRL16E_I " *)
SRL16E #(
.INIT(16'h0000),
.IS_CLK_INVERTED(1'b0))
\FIFO_RAM[1].SRL16E_I
(.A0(Tx_addr[0]),
.A1(Tx_addr[1]),
.A2(Tx_addr[2]),
.A3(Tx_addr[3]),
.CE(CI),
.CLK(s_axi_aclk),
.D(s_axi_wdata[6]),
.Q(Tx_fifo_data[1]));
(* box_type = "PRIMITIVE" *)
(* srl_bus_name = "U0/\X_IIC/WRITE_FIFO_I/FIFO_RAM " *)
(* srl_name = "U0/\X_IIC/WRITE_FIFO_I/FIFO_RAM[2].SRL16E_I " *)
SRL16E #(
.INIT(16'h0000),
.IS_CLK_INVERTED(1'b0))
\FIFO_RAM[2].SRL16E_I
(.A0(Tx_addr[0]),
.A1(Tx_addr[1]),
.A2(Tx_addr[2]),
.A3(Tx_addr[3]),
.CE(CI),
.CLK(s_axi_aclk),
.D(s_axi_wdata[5]),
.Q(Tx_fifo_data[2]));
(* box_type = "PRIMITIVE" *)
(* srl_bus_name = "U0/\X_IIC/WRITE_FIFO_I/FIFO_RAM " *)
(* srl_name = "U0/\X_IIC/WRITE_FIFO_I/FIFO_RAM[3].SRL16E_I " *)
SRL16E #(
.INIT(16'h0000),
.IS_CLK_INVERTED(1'b0))
\FIFO_RAM[3].SRL16E_I
(.A0(Tx_addr[0]),
.A1(Tx_addr[1]),
.A2(Tx_addr[2]),
.A3(Tx_addr[3]),
.CE(CI),
.CLK(s_axi_aclk),
.D(s_axi_wdata[4]),
.Q(Tx_fifo_data[3]));
(* box_type = "PRIMITIVE" *)
(* srl_bus_name = "U0/\X_IIC/WRITE_FIFO_I/FIFO_RAM " *)
(* srl_name = "U0/\X_IIC/WRITE_FIFO_I/FIFO_RAM[4].SRL16E_I " *)
SRL16E #(
.INIT(16'h0000),
.IS_CLK_INVERTED(1'b0))
\FIFO_RAM[4].SRL16E_I
(.A0(Tx_addr[0]),
.A1(Tx_addr[1]),
.A2(Tx_addr[2]),
.A3(Tx_addr[3]),
.CE(CI),
.CLK(s_axi_aclk),
.D(s_axi_wdata[3]),
.Q(Tx_fifo_data[4]));
(* box_type = "PRIMITIVE" *)
(* srl_bus_name = "U0/\X_IIC/WRITE_FIFO_I/FIFO_RAM " *)
(* srl_name = "U0/\X_IIC/WRITE_FIFO_I/FIFO_RAM[5].SRL16E_I " *)
SRL16E #(
.INIT(16'h0000),
.IS_CLK_INVERTED(1'b0))
\FIFO_RAM[5].SRL16E_I
(.A0(Tx_addr[0]),
.A1(Tx_addr[1]),
.A2(Tx_addr[2]),
.A3(Tx_addr[3]),
.CE(CI),
.CLK(s_axi_aclk),
.D(s_axi_wdata[2]),
.Q(Tx_fifo_data[5]));
(* box_type = "PRIMITIVE" *)
(* srl_bus_name = "U0/\X_IIC/WRITE_FIFO_I/FIFO_RAM " *)
(* srl_name = "U0/\X_IIC/WRITE_FIFO_I/FIFO_RAM[6].SRL16E_I " *)
SRL16E #(
.INIT(16'h0000),
.IS_CLK_INVERTED(1'b0))
\FIFO_RAM[6].SRL16E_I
(.A0(Tx_addr[0]),
.A1(Tx_addr[1]),
.A2(Tx_addr[2]),
.A3(Tx_addr[3]),
.CE(CI),
.CLK(s_axi_aclk),
.D(s_axi_wdata[1]),
.Q(Tx_fifo_data[6]));
(* box_type = "PRIMITIVE" *)
(* srl_bus_name = "U0/\X_IIC/WRITE_FIFO_I/FIFO_RAM " *)
(* srl_name = "U0/\X_IIC/WRITE_FIFO_I/FIFO_RAM[7].SRL16E_I " *)
SRL16E #(
.INIT(16'h0000),
.IS_CLK_INVERTED(1'b0))
\FIFO_RAM[7].SRL16E_I
(.A0(Tx_addr[0]),
.A1(Tx_addr[1]),
.A2(Tx_addr[2]),
.A3(Tx_addr[3]),
.CE(CI),
.CLK(s_axi_aclk),
.D(s_axi_wdata[0]),
.Q(Tx_fifo_data[7]));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT4 #(
.INIT(16'h0800))
callingReadAccess_i_1
(.I0(Tx_data_exists),
.I1(dynamic_MSMS),
.I2(Tx_fifo_rd_d),
.I3(Tx_fifo_rd),
.O(p_3_in));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT2 #(
.INIT(4'h7))
\cr_i[5]_i_2
(.I0(Tx_data_exists),
.I1(dynamic_MSMS),
.O(\cr_i_reg[5] ));
LUT3 #(
.INIT(8'hB8))
\data_int[0]_i_1
(.I0(Tx_fifo_data[7]),
.I1(shift_reg_ld),
.I2(scndry_out),
.O(\data_int_reg[0] ));
LUT1 #(
.INIT(2'h1))
\sr_i[0]_i_1
(.I0(Tx_data_exists),
.O(\sr_i_reg[0] ));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT4 #(
.INIT(16'h8000))
\sr_i[3]_i_1
(.I0(Tx_addr[1]),
.I1(Tx_addr[3]),
.I2(Tx_addr[0]),
.I3(Tx_addr[2]),
.O(\sr_i_reg[3] ));
endmodule
(* ORIG_REF_NAME = "SRL_FIFO" *)
module system_axi_iic_0_0_SRL_FIFO__parameterized0
(\Addr_Counters[0].FDRE_I_0 ,
dynamic_MSMS,
Data_Exists_DFF_0,
Tx_fifo_rst,
D,
s_axi_aclk,
ctrlFifoDin,
Tx_fifo_rd,
Tx_fifo_rd_d,
rdCntrFrmTxFifo,
Tx_fifo_wr_d_reg,
\FIFO_GEN_DTR.Tx_fifo_rd_reg );
output \Addr_Counters[0].FDRE_I_0 ;
output [0:1]dynamic_MSMS;
output Data_Exists_DFF_0;
input Tx_fifo_rst;
input D;
input s_axi_aclk;
input [0:1]ctrlFifoDin;
input Tx_fifo_rd;
input Tx_fifo_rd_d;
input rdCntrFrmTxFifo;
input Tx_fifo_wr_d_reg;
input \FIFO_GEN_DTR.Tx_fifo_rd_reg ;
wire \Addr_Counters[0].FDRE_I_0 ;
wire \Addr_Counters[0].FDRE_I_n_0 ;
wire \Addr_Counters[0].MUXCY_L_I_i_3_n_0 ;
wire \Addr_Counters[1].FDRE_I_n_0 ;
wire \Addr_Counters[2].FDRE_I_n_0 ;
wire \Addr_Counters[3].FDRE_I_n_0 ;
wire \Addr_Counters[3].XORCY_I_i_1_n_0 ;
wire CI;
wire D;
wire Data_Exists_DFF_0;
wire \FIFO_GEN_DTR.Tx_fifo_rd_reg ;
wire S;
wire S0_out;
wire S1_out;
wire Tx_fifo_rd;
wire Tx_fifo_rd_d;
wire Tx_fifo_rst;
wire Tx_fifo_wr_d_reg;
wire addr_cy_1;
wire addr_cy_2;
wire addr_cy_3;
wire [0:1]ctrlFifoDin;
wire [0:1]dynamic_MSMS;
wire rdCntrFrmTxFifo;
wire s_axi_aclk;
wire sum_A_0;
wire sum_A_1;
wire sum_A_2;
wire sum_A_3;
wire [3:3]\NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_CO_UNCONNECTED ;
wire [3:3]\NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_DI_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\Addr_Counters[0].FDRE_I
(.C(s_axi_aclk),
.CE(\Addr_Counters[0].FDRE_I_0 ),
.D(sum_A_3),
.Q(\Addr_Counters[0].FDRE_I_n_0 ),
.R(Tx_fifo_rst));
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* XILINX_TRANSFORM_PINMAP = "LO:O" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \Addr_Counters[0].MUXCY_L_I_CARRY4
(.CI(1'b0),
.CO({\NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_CO_UNCONNECTED [3],addr_cy_1,addr_cy_2,addr_cy_3}),
.CYINIT(CI),
.DI({\NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_DI_UNCONNECTED [3],\Addr_Counters[2].FDRE_I_n_0 ,\Addr_Counters[1].FDRE_I_n_0 ,\Addr_Counters[0].FDRE_I_n_0 }),
.O({sum_A_0,sum_A_1,sum_A_2,sum_A_3}),
.S({\Addr_Counters[3].XORCY_I_i_1_n_0 ,S0_out,S1_out,S}));
LUT5 #(
.INIT(32'h00A2AA08))
\Addr_Counters[0].MUXCY_L_I_i_1
(.I0(\Addr_Counters[0].MUXCY_L_I_i_3_n_0 ),
.I1(Tx_fifo_rd),
.I2(Tx_fifo_rd_d),
.I3(rdCntrFrmTxFifo),
.I4(\Addr_Counters[0].FDRE_I_n_0 ),
.O(S));
LUT6 #(
.INIT(64'h2AAAAAAAAAAAAAAA))
\Addr_Counters[0].MUXCY_L_I_i_2
(.I0(Tx_fifo_wr_d_reg),
.I1(\Addr_Counters[2].FDRE_I_n_0 ),
.I2(\Addr_Counters[3].FDRE_I_n_0 ),
.I3(\Addr_Counters[1].FDRE_I_n_0 ),
.I4(\Addr_Counters[0].FDRE_I_n_0 ),
.I5(\FIFO_GEN_DTR.Tx_fifo_rd_reg ),
.O(CI));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT5 #(
.INIT(32'hFFFFFFFE))
\Addr_Counters[0].MUXCY_L_I_i_3
(.I0(Tx_fifo_wr_d_reg),
.I1(\Addr_Counters[2].FDRE_I_n_0 ),
.I2(\Addr_Counters[0].FDRE_I_n_0 ),
.I3(\Addr_Counters[3].FDRE_I_n_0 ),
.I4(\Addr_Counters[1].FDRE_I_n_0 ),
.O(\Addr_Counters[0].MUXCY_L_I_i_3_n_0 ));
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\Addr_Counters[1].FDRE_I
(.C(s_axi_aclk),
.CE(\Addr_Counters[0].FDRE_I_0 ),
.D(sum_A_2),
.Q(\Addr_Counters[1].FDRE_I_n_0 ),
.R(Tx_fifo_rst));
LUT5 #(
.INIT(32'h00A2AA08))
\Addr_Counters[1].MUXCY_L_I_i_1
(.I0(\Addr_Counters[0].MUXCY_L_I_i_3_n_0 ),
.I1(Tx_fifo_rd),
.I2(Tx_fifo_rd_d),
.I3(rdCntrFrmTxFifo),
.I4(\Addr_Counters[1].FDRE_I_n_0 ),
.O(S1_out));
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\Addr_Counters[2].FDRE_I
(.C(s_axi_aclk),
.CE(\Addr_Counters[0].FDRE_I_0 ),
.D(sum_A_1),
.Q(\Addr_Counters[2].FDRE_I_n_0 ),
.R(Tx_fifo_rst));
LUT5 #(
.INIT(32'h00A2AA08))
\Addr_Counters[2].MUXCY_L_I_i_1
(.I0(\Addr_Counters[0].MUXCY_L_I_i_3_n_0 ),
.I1(Tx_fifo_rd),
.I2(Tx_fifo_rd_d),
.I3(rdCntrFrmTxFifo),
.I4(\Addr_Counters[2].FDRE_I_n_0 ),
.O(S0_out));
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\Addr_Counters[3].FDRE_I
(.C(s_axi_aclk),
.CE(\Addr_Counters[0].FDRE_I_0 ),
.D(sum_A_0),
.Q(\Addr_Counters[3].FDRE_I_n_0 ),
.R(Tx_fifo_rst));
LUT5 #(
.INIT(32'h00A2AA08))
\Addr_Counters[3].XORCY_I_i_1
(.I0(\Addr_Counters[0].MUXCY_L_I_i_3_n_0 ),
.I1(Tx_fifo_rd),
.I2(Tx_fifo_rd_d),
.I3(rdCntrFrmTxFifo),
.I4(\Addr_Counters[3].FDRE_I_n_0 ),
.O(\Addr_Counters[3].XORCY_I_i_1_n_0 ));
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
Data_Exists_DFF
(.C(s_axi_aclk),
.CE(1'b1),
.D(D),
.Q(\Addr_Counters[0].FDRE_I_0 ),
.R(Tx_fifo_rst));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT4 #(
.INIT(16'hFFFE))
Data_Exists_DFF_i_3__0
(.I0(\Addr_Counters[1].FDRE_I_n_0 ),
.I1(\Addr_Counters[3].FDRE_I_n_0 ),
.I2(\Addr_Counters[0].FDRE_I_n_0 ),
.I3(\Addr_Counters[2].FDRE_I_n_0 ),
.O(Data_Exists_DFF_0));
(* box_type = "PRIMITIVE" *)
(* srl_bus_name = "U0/\X_IIC/WRITE_FIFO_CTRL_I/FIFO_RAM " *)
(* srl_name = "U0/\X_IIC/WRITE_FIFO_CTRL_I/FIFO_RAM[0].SRL16E_I " *)
SRL16E #(
.INIT(16'h0000),
.IS_CLK_INVERTED(1'b0))
\FIFO_RAM[0].SRL16E_I
(.A0(\Addr_Counters[0].FDRE_I_n_0 ),
.A1(\Addr_Counters[1].FDRE_I_n_0 ),
.A2(\Addr_Counters[2].FDRE_I_n_0 ),
.A3(\Addr_Counters[3].FDRE_I_n_0 ),
.CE(CI),
.CLK(s_axi_aclk),
.D(ctrlFifoDin[0]),
.Q(dynamic_MSMS[0]));
(* box_type = "PRIMITIVE" *)
(* srl_bus_name = "U0/\X_IIC/WRITE_FIFO_CTRL_I/FIFO_RAM " *)
(* srl_name = "U0/\X_IIC/WRITE_FIFO_CTRL_I/FIFO_RAM[1].SRL16E_I " *)
SRL16E #(
.INIT(16'h0000),
.IS_CLK_INVERTED(1'b0))
\FIFO_RAM[1].SRL16E_I
(.A0(\Addr_Counters[0].FDRE_I_n_0 ),
.A1(\Addr_Counters[1].FDRE_I_n_0 ),
.A2(\Addr_Counters[2].FDRE_I_n_0 ),
.A3(\Addr_Counters[3].FDRE_I_n_0 ),
.CE(CI),
.CLK(s_axi_aclk),
.D(ctrlFifoDin[1]),
.Q(dynamic_MSMS[1]));
endmodule
(* ORIG_REF_NAME = "address_decoder" *)
module system_axi_iic_0_0_address_decoder
(\GEN_BKEND_CE_REGISTERS[23].ce_out_i_reg[23]_0 ,
\GEN_BKEND_CE_REGISTERS[21].ce_out_i_reg[21]_0 ,
AXI_IP2Bus_WrAck2_reg,
\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ,
s_axi_wready,
\GEN_BKEND_CE_REGISTERS[26].ce_out_i_reg[26]_0 ,
irpt_wrack,
\GEN_IP_IRPT_STATUS_REG[7].GEN_REG_STATUS.ip_irpt_status_reg_reg[7] ,
\GEN_IP_IRPT_STATUS_REG[6].GEN_REG_STATUS.ip_irpt_status_reg_reg[6] ,
\GEN_IP_IRPT_STATUS_REG[5].GEN_REG_STATUS.ip_irpt_status_reg_reg[5] ,
\GEN_IP_IRPT_STATUS_REG[4].GEN_REG_STATUS.ip_irpt_status_reg_reg[4] ,
\GEN_IP_IRPT_STATUS_REG[3].GEN_REG_STATUS.ip_irpt_status_reg_reg[3] ,
\GEN_IP_IRPT_STATUS_REG[2].GEN_REG_STATUS.ip_irpt_status_reg_reg[2] ,
\GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1] ,
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0] ,
reset_trig0,
sw_rst_cond,
AXI_IP2Bus_Error,
D,
Bus2IIC_RdCE,
E,
\cr_i_reg[4] ,
Bus2IIC_WrCE,
AXI_IP2Bus_RdAck20,
ipif_glbl_irpt_enable_reg_reg,
\GPO_GEN.gpo_i_reg[31] ,
\s_axi_bresp_i_reg[1] ,
Q,
s_axi_aclk,
\bus2ip_addr_i_reg[8] ,
bus2ip_rnw_i_reg,
is_read,
AXI_IP2Bus_RdAck1,
AXI_IP2Bus_RdAck2,
s_axi_aresetn,
is_write_reg,
AXI_IP2Bus_WrAck1,
AXI_IP2Bus_WrAck2,
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] ,
s_axi_wdata,
irpt_wrack_d1,
IIC2Bus_IntrEvent,
p_1_in,
p_1_in2_in,
p_1_in5_in,
p_1_in8_in,
p_1_in11_in,
p_1_in14_in,
p_1_in17_in,
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0 ,
sw_rst_cond_d1,
\ip_irpt_enable_reg_reg[7] ,
\bus2ip_addr_i_reg[6] ,
\timing_param_thdsta_i_reg[0] ,
\timing_param_thigh_i_reg[0] ,
\Addr_Counters[1].FDRE_I ,
\timing_param_thigh_i_reg[1] ,
\adr_i_reg[6] ,
\adr_i_reg[5] ,
\Addr_Counters[2].FDRE_I ,
\timing_param_thigh_i_reg[2] ,
\bus2ip_addr_i_reg[2] ,
\timing_param_tbuf_i_reg[3] ,
\adr_i_reg[4] ,
\bus2ip_addr_i_reg[5] ,
\adr_i_reg[3] ,
\bus2ip_addr_i_reg[5]_0 ,
\bus2ip_addr_i_reg[5]_1 ,
\adr_i_reg[2] ,
\bus2ip_addr_i_reg[5]_2 ,
\bus2ip_addr_i_reg[5]_3 ,
\adr_i_reg[1] ,
\timing_param_tsudat_i_reg[6] ,
\bus2ip_addr_i_reg[5]_4 ,
\adr_i_reg[0] ,
\timing_param_tsudat_i_reg[7] ,
\bus2ip_addr_i_reg[2]_0 ,
\bus2ip_addr_i_reg[2]_1 ,
\cr_i_reg[4]_0 ,
cr_txModeSelect_set,
cr_txModeSelect_clr,
ipif_glbl_irpt_enable_reg,
gpo,
\state_reg[1] ,
s_axi_bresp);
output \GEN_BKEND_CE_REGISTERS[23].ce_out_i_reg[23]_0 ;
output \GEN_BKEND_CE_REGISTERS[21].ce_out_i_reg[21]_0 ;
output AXI_IP2Bus_WrAck2_reg;
output \MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ;
output s_axi_wready;
output \GEN_BKEND_CE_REGISTERS[26].ce_out_i_reg[26]_0 ;
output irpt_wrack;
output \GEN_IP_IRPT_STATUS_REG[7].GEN_REG_STATUS.ip_irpt_status_reg_reg[7] ;
output \GEN_IP_IRPT_STATUS_REG[6].GEN_REG_STATUS.ip_irpt_status_reg_reg[6] ;
output \GEN_IP_IRPT_STATUS_REG[5].GEN_REG_STATUS.ip_irpt_status_reg_reg[5] ;
output \GEN_IP_IRPT_STATUS_REG[4].GEN_REG_STATUS.ip_irpt_status_reg_reg[4] ;
output \GEN_IP_IRPT_STATUS_REG[3].GEN_REG_STATUS.ip_irpt_status_reg_reg[3] ;
output \GEN_IP_IRPT_STATUS_REG[2].GEN_REG_STATUS.ip_irpt_status_reg_reg[2] ;
output \GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1] ;
output \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0] ;
output reset_trig0;
output sw_rst_cond;
output AXI_IP2Bus_Error;
output [10:0]D;
output [0:0]Bus2IIC_RdCE;
output [0:0]E;
output [0:0]\cr_i_reg[4] ;
output [11:0]Bus2IIC_WrCE;
output AXI_IP2Bus_RdAck20;
output ipif_glbl_irpt_enable_reg_reg;
output \GPO_GEN.gpo_i_reg[31] ;
output \s_axi_bresp_i_reg[1] ;
input Q;
input s_axi_aclk;
input [8:0]\bus2ip_addr_i_reg[8] ;
input bus2ip_rnw_i_reg;
input is_read;
input AXI_IP2Bus_RdAck1;
input AXI_IP2Bus_RdAck2;
input s_axi_aresetn;
input is_write_reg;
input AXI_IP2Bus_WrAck1;
input AXI_IP2Bus_WrAck2;
input [3:0]\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] ;
input [8:0]s_axi_wdata;
input irpt_wrack_d1;
input [0:7]IIC2Bus_IntrEvent;
input p_1_in;
input p_1_in2_in;
input p_1_in5_in;
input p_1_in8_in;
input p_1_in11_in;
input p_1_in14_in;
input p_1_in17_in;
input \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0 ;
input sw_rst_cond_d1;
input [7:0]\ip_irpt_enable_reg_reg[7] ;
input \bus2ip_addr_i_reg[6] ;
input \timing_param_thdsta_i_reg[0] ;
input \timing_param_thigh_i_reg[0] ;
input \Addr_Counters[1].FDRE_I ;
input \timing_param_thigh_i_reg[1] ;
input \adr_i_reg[6] ;
input \adr_i_reg[5] ;
input \Addr_Counters[2].FDRE_I ;
input \timing_param_thigh_i_reg[2] ;
input \bus2ip_addr_i_reg[2] ;
input \timing_param_tbuf_i_reg[3] ;
input \adr_i_reg[4] ;
input \bus2ip_addr_i_reg[5] ;
input \adr_i_reg[3] ;
input \bus2ip_addr_i_reg[5]_0 ;
input \bus2ip_addr_i_reg[5]_1 ;
input \adr_i_reg[2] ;
input \bus2ip_addr_i_reg[5]_2 ;
input \bus2ip_addr_i_reg[5]_3 ;
input \adr_i_reg[1] ;
input \timing_param_tsudat_i_reg[6] ;
input \bus2ip_addr_i_reg[5]_4 ;
input \adr_i_reg[0] ;
input \timing_param_tsudat_i_reg[7] ;
input \bus2ip_addr_i_reg[2]_0 ;
input \bus2ip_addr_i_reg[2]_1 ;
input [0:0]\cr_i_reg[4]_0 ;
input cr_txModeSelect_set;
input cr_txModeSelect_clr;
input ipif_glbl_irpt_enable_reg;
input [0:0]gpo;
input [1:0]\state_reg[1] ;
input [0:0]s_axi_bresp;
wire AXI_IP2Bus_Error;
wire AXI_IP2Bus_RdAck1;
wire AXI_IP2Bus_RdAck2;
wire AXI_IP2Bus_RdAck20;
wire AXI_IP2Bus_WrAck1;
wire AXI_IP2Bus_WrAck2;
wire AXI_IP2Bus_WrAck2_reg;
wire \Addr_Counters[1].FDRE_I ;
wire \Addr_Counters[2].FDRE_I ;
wire [0:0]Bus2IIC_RdCE;
wire [11:0]Bus2IIC_WrCE;
wire Bus_RNW_reg;
wire Bus_RNW_reg_i_1_n_0;
wire [10:0]D;
wire [0:0]E;
wire \GEN_BKEND_CE_REGISTERS[10].ce_out_i[10]_i_1_n_0 ;
wire \GEN_BKEND_CE_REGISTERS[10].ce_out_i[10]_i_2_n_0 ;
wire \GEN_BKEND_CE_REGISTERS[17].ce_out_i[17]_i_1_n_0 ;
wire \GEN_BKEND_CE_REGISTERS[18].ce_out_i[18]_i_2_n_0 ;
wire \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ;
wire \GEN_BKEND_CE_REGISTERS[20].ce_out_i[20]_i_1_n_0 ;
wire \GEN_BKEND_CE_REGISTERS[21].ce_out_i[21]_i_1_n_0 ;
wire \GEN_BKEND_CE_REGISTERS[21].ce_out_i_reg[21]_0 ;
wire \GEN_BKEND_CE_REGISTERS[22].ce_out_i[22]_i_1_n_0 ;
wire \GEN_BKEND_CE_REGISTERS[23].ce_out_i[23]_i_1_n_0 ;
wire \GEN_BKEND_CE_REGISTERS[23].ce_out_i_reg[23]_0 ;
wire \GEN_BKEND_CE_REGISTERS[24].ce_out_i[24]_i_1_n_0 ;
wire \GEN_BKEND_CE_REGISTERS[25].ce_out_i[25]_i_1_n_0 ;
wire \GEN_BKEND_CE_REGISTERS[26].ce_out_i[26]_i_1_n_0 ;
wire \GEN_BKEND_CE_REGISTERS[26].ce_out_i_reg[26]_0 ;
wire \GEN_BKEND_CE_REGISTERS[27].ce_out_i[27]_i_1_n_0 ;
wire \GEN_BKEND_CE_REGISTERS[28].ce_out_i[28]_i_1_n_0 ;
wire \GEN_BKEND_CE_REGISTERS[29].ce_out_i[29]_i_1_n_0 ;
wire \GEN_BKEND_CE_REGISTERS[29].ce_out_i[29]_i_2_n_0 ;
wire \GEN_BKEND_CE_REGISTERS[30].ce_out_i[30]_i_1_n_0 ;
wire \GEN_BKEND_CE_REGISTERS[30].ce_out_i[30]_i_2_n_0 ;
wire \GEN_BKEND_CE_REGISTERS[31].ce_out_i[31]_i_1_n_0 ;
wire \GEN_BKEND_CE_REGISTERS[31].ce_out_i[31]_i_2_n_0 ;
wire \GEN_BKEND_CE_REGISTERS[32].ce_out_i[32]_i_1_n_0 ;
wire \GEN_BKEND_CE_REGISTERS[33].ce_out_i[33]_i_1_n_0 ;
wire \GEN_BKEND_CE_REGISTERS[34].ce_out_i_reg_n_0_[34] ;
wire \GEN_BKEND_CE_REGISTERS[8].ce_out_i[8]_i_1_n_0 ;
wire \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0] ;
wire \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0 ;
wire \GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1] ;
wire \GEN_IP_IRPT_STATUS_REG[2].GEN_REG_STATUS.ip_irpt_status_reg_reg[2] ;
wire \GEN_IP_IRPT_STATUS_REG[3].GEN_REG_STATUS.ip_irpt_status_reg_reg[3] ;
wire \GEN_IP_IRPT_STATUS_REG[4].GEN_REG_STATUS.ip_irpt_status_reg_reg[4] ;
wire \GEN_IP_IRPT_STATUS_REG[5].GEN_REG_STATUS.ip_irpt_status_reg_reg[5] ;
wire \GEN_IP_IRPT_STATUS_REG[6].GEN_REG_STATUS.ip_irpt_status_reg_reg[6] ;
wire \GEN_IP_IRPT_STATUS_REG[7].GEN_REG_STATUS.ip_irpt_status_reg_reg[7] ;
wire \GPO_GEN.gpo_i_reg[31] ;
wire [0:7]IIC2Bus_IntrEvent;
wire [3:0]\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] ;
wire \MEM_DECODE_GEN[0].cs_out_i_reg ;
wire \MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ;
wire \MEM_DECODE_GEN[1].GEN_FOR_MULTI_CS.MEM_SELECT_I/CS ;
wire \MEM_DECODE_GEN[1].cs_out_i_reg ;
wire \MEM_DECODE_GEN[2].cs_out_i_reg ;
wire Q;
wire \adr_i_reg[0] ;
wire \adr_i_reg[1] ;
wire \adr_i_reg[2] ;
wire \adr_i_reg[3] ;
wire \adr_i_reg[4] ;
wire \adr_i_reg[5] ;
wire \adr_i_reg[6] ;
wire \bus2ip_addr_i_reg[2] ;
wire \bus2ip_addr_i_reg[2]_0 ;
wire \bus2ip_addr_i_reg[2]_1 ;
wire \bus2ip_addr_i_reg[5] ;
wire \bus2ip_addr_i_reg[5]_0 ;
wire \bus2ip_addr_i_reg[5]_1 ;
wire \bus2ip_addr_i_reg[5]_2 ;
wire \bus2ip_addr_i_reg[5]_3 ;
wire \bus2ip_addr_i_reg[5]_4 ;
wire \bus2ip_addr_i_reg[6] ;
wire [8:0]\bus2ip_addr_i_reg[8] ;
wire bus2ip_rnw_i_reg;
wire [0:0]\cr_i_reg[4] ;
wire [0:0]\cr_i_reg[4]_0 ;
wire cr_txModeSelect_clr;
wire cr_txModeSelect_set;
wire cs_ce_clr;
wire [0:0]gpo;
wire [7:0]\ip_irpt_enable_reg_reg[7] ;
wire ipif_glbl_irpt_enable_reg;
wire ipif_glbl_irpt_enable_reg_reg;
wire irpt_wrack;
wire irpt_wrack_d1;
wire is_read;
wire is_write_reg;
wire p_10_in;
wire p_11_in;
wire p_12_in;
wire p_13_in;
wire p_14_in;
wire p_15_in;
wire p_16_in;
wire p_16_out;
wire p_17_in;
wire p_17_out;
wire p_18_in;
wire p_1_in;
wire p_1_in11_in;
wire p_1_in14_in;
wire p_1_in17_in;
wire p_1_in2_in;
wire p_1_in5_in;
wire p_1_in8_in;
wire p_25_in;
wire p_27_in;
wire p_28_in;
wire p_2_in;
wire p_3_in;
wire p_4_in;
wire p_5_in;
wire p_6_in;
wire p_7_in;
wire p_8_in;
wire p_8_out;
wire p_9_in;
wire pselect_hit_i_0;
wire pselect_hit_i_2;
wire reset_trig0;
wire s_axi_aclk;
wire s_axi_aresetn;
wire [0:0]s_axi_bresp;
wire \s_axi_bresp_i_reg[1] ;
wire \s_axi_rdata_i[0]_i_2_n_0 ;
wire \s_axi_rdata_i[1]_i_2_n_0 ;
wire \s_axi_rdata_i[2]_i_2_n_0 ;
wire \s_axi_rdata_i[3]_i_2_n_0 ;
wire \s_axi_rdata_i[4]_i_2_n_0 ;
wire \s_axi_rdata_i[5]_i_2_n_0 ;
wire \s_axi_rdata_i[6]_i_2_n_0 ;
wire \s_axi_rdata_i[7]_i_2_n_0 ;
wire \s_axi_rdata_i[9]_i_3_n_0 ;
wire \s_axi_rdata_i[9]_i_6_n_0 ;
wire \s_axi_rdata_i[9]_i_7_n_0 ;
wire \s_axi_rdata_i[9]_i_8_n_0 ;
wire \s_axi_rdata_i[9]_i_9_n_0 ;
wire [8:0]s_axi_wdata;
wire s_axi_wready;
wire [1:0]\state_reg[1] ;
wire sw_rst_cond;
wire sw_rst_cond_d1;
wire \timing_param_tbuf_i_reg[3] ;
wire \timing_param_thdsta_i_reg[0] ;
wire \timing_param_thigh_i_reg[0] ;
wire \timing_param_thigh_i_reg[1] ;
wire \timing_param_thigh_i_reg[2] ;
wire \timing_param_tsudat_i_reg[6] ;
wire \timing_param_tsudat_i_reg[7] ;
(* SOFT_HLUTNM = "soft_lutpair37" *)
LUT4 #(
.INIT(16'hFE00))
AXI_IP2Bus_RdAck2_i_1
(.I0(\MEM_DECODE_GEN[2].cs_out_i_reg ),
.I1(\MEM_DECODE_GEN[0].cs_out_i_reg ),
.I2(\MEM_DECODE_GEN[1].cs_out_i_reg ),
.I3(bus2ip_rnw_i_reg),
.O(AXI_IP2Bus_RdAck20));
(* SOFT_HLUTNM = "soft_lutpair37" *)
LUT4 #(
.INIT(16'h00FE))
AXI_IP2Bus_WrAck2_i_1
(.I0(\MEM_DECODE_GEN[2].cs_out_i_reg ),
.I1(\MEM_DECODE_GEN[0].cs_out_i_reg ),
.I2(\MEM_DECODE_GEN[1].cs_out_i_reg ),
.I3(bus2ip_rnw_i_reg),
.O(AXI_IP2Bus_WrAck2_reg));
(* SOFT_HLUTNM = "soft_lutpair39" *)
LUT3 #(
.INIT(8'hB8))
Bus_RNW_reg_i_1
(.I0(bus2ip_rnw_i_reg),
.I1(Q),
.I2(Bus_RNW_reg),
.O(Bus_RNW_reg_i_1_n_0));
FDRE Bus_RNW_reg_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(Bus_RNW_reg_i_1_n_0),
.Q(Bus_RNW_reg),
.R(1'b0));
LUT2 #(
.INIT(4'h2))
\FIFO_GEN_DTR.Tx_fifo_wr_i_1
(.I0(p_16_in),
.I1(Bus_RNW_reg),
.O(Bus2IIC_WrCE[10]));
LUT6 #(
.INIT(64'h0000000200000000))
\GEN_BKEND_CE_REGISTERS[10].ce_out_i[10]_i_1
(.I0(Q),
.I1(\bus2ip_addr_i_reg[8] [7]),
.I2(\bus2ip_addr_i_reg[8] [8]),
.I3(\bus2ip_addr_i_reg[8] [6]),
.I4(\GEN_BKEND_CE_REGISTERS[10].ce_out_i[10]_i_2_n_0 ),
.I5(\GEN_BKEND_CE_REGISTERS[23].ce_out_i_reg[23]_0 ),
.O(\GEN_BKEND_CE_REGISTERS[10].ce_out_i[10]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair40" *)
LUT2 #(
.INIT(4'hB))
\GEN_BKEND_CE_REGISTERS[10].ce_out_i[10]_i_2
(.I0(\bus2ip_addr_i_reg[8] [4]),
.I1(\bus2ip_addr_i_reg[8] [5]),
.O(\GEN_BKEND_CE_REGISTERS[10].ce_out_i[10]_i_2_n_0 ));
FDRE \GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]
(.C(s_axi_aclk),
.CE(Q),
.D(\GEN_BKEND_CE_REGISTERS[10].ce_out_i[10]_i_1_n_0 ),
.Q(p_25_in),
.R(cs_ce_clr));
LUT6 #(
.INIT(64'h0000000000004000))
\GEN_BKEND_CE_REGISTERS[17].ce_out_i[17]_i_1
(.I0(\bus2ip_addr_i_reg[8] [3]),
.I1(Q),
.I2(\bus2ip_addr_i_reg[8] [8]),
.I3(\GEN_BKEND_CE_REGISTERS[18].ce_out_i[18]_i_2_n_0 ),
.I4(\bus2ip_addr_i_reg[8] [6]),
.I5(\bus2ip_addr_i_reg[8] [2]),
.O(\GEN_BKEND_CE_REGISTERS[17].ce_out_i[17]_i_1_n_0 ));
FDRE \GEN_BKEND_CE_REGISTERS[17].ce_out_i_reg[17]
(.C(s_axi_aclk),
.CE(Q),
.D(\GEN_BKEND_CE_REGISTERS[17].ce_out_i[17]_i_1_n_0 ),
.Q(p_18_in),
.R(cs_ce_clr));
LUT6 #(
.INIT(64'h0000008000000000))
\GEN_BKEND_CE_REGISTERS[18].ce_out_i[18]_i_1
(.I0(\bus2ip_addr_i_reg[8] [2]),
.I1(Q),
.I2(\bus2ip_addr_i_reg[8] [8]),
.I3(\bus2ip_addr_i_reg[8] [6]),
.I4(\bus2ip_addr_i_reg[8] [3]),
.I5(\GEN_BKEND_CE_REGISTERS[18].ce_out_i[18]_i_2_n_0 ),
.O(p_16_out));
(* SOFT_HLUTNM = "soft_lutpair40" *)
LUT2 #(
.INIT(4'h1))
\GEN_BKEND_CE_REGISTERS[18].ce_out_i[18]_i_2
(.I0(\bus2ip_addr_i_reg[8] [5]),
.I1(\bus2ip_addr_i_reg[8] [4]),
.O(\GEN_BKEND_CE_REGISTERS[18].ce_out_i[18]_i_2_n_0 ));
FDRE \GEN_BKEND_CE_REGISTERS[18].ce_out_i_reg[18]
(.C(s_axi_aclk),
.CE(Q),
.D(p_16_out),
.Q(p_17_in),
.R(cs_ce_clr));
LUT6 #(
.INIT(64'h0001000000000000))
\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1
(.I0(\bus2ip_addr_i_reg[8] [5]),
.I1(\bus2ip_addr_i_reg[8] [4]),
.I2(\bus2ip_addr_i_reg[8] [6]),
.I3(\bus2ip_addr_i_reg[8] [2]),
.I4(\bus2ip_addr_i_reg[8] [3]),
.I5(pselect_hit_i_0),
.O(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ));
FDRE \GEN_BKEND_CE_REGISTERS[19].ce_out_i_reg[19]
(.C(s_axi_aclk),
.CE(Q),
.D(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ),
.Q(p_16_in),
.R(cs_ce_clr));
LUT6 #(
.INIT(64'h4000000000000000))
\GEN_BKEND_CE_REGISTERS[20].ce_out_i[20]_i_1
(.I0(\bus2ip_addr_i_reg[8] [5]),
.I1(\GEN_BKEND_CE_REGISTERS[26].ce_out_i_reg[26]_0 ),
.I2(\bus2ip_addr_i_reg[8] [2]),
.I3(\bus2ip_addr_i_reg[8] [3]),
.I4(Q),
.I5(\bus2ip_addr_i_reg[8] [8]),
.O(\GEN_BKEND_CE_REGISTERS[20].ce_out_i[20]_i_1_n_0 ));
FDRE \GEN_BKEND_CE_REGISTERS[20].ce_out_i_reg[20]
(.C(s_axi_aclk),
.CE(Q),
.D(\GEN_BKEND_CE_REGISTERS[20].ce_out_i[20]_i_1_n_0 ),
.Q(p_15_in),
.R(cs_ce_clr));
LUT6 #(
.INIT(64'h0000000000008000))
\GEN_BKEND_CE_REGISTERS[21].ce_out_i[21]_i_1
(.I0(\GEN_BKEND_CE_REGISTERS[21].ce_out_i_reg[21]_0 ),
.I1(\bus2ip_addr_i_reg[8] [8]),
.I2(Q),
.I3(\bus2ip_addr_i_reg[8] [4]),
.I4(\bus2ip_addr_i_reg[8] [5]),
.I5(\bus2ip_addr_i_reg[8] [6]),
.O(\GEN_BKEND_CE_REGISTERS[21].ce_out_i[21]_i_1_n_0 ));
FDRE \GEN_BKEND_CE_REGISTERS[21].ce_out_i_reg[21]
(.C(s_axi_aclk),
.CE(Q),
.D(\GEN_BKEND_CE_REGISTERS[21].ce_out_i[21]_i_1_n_0 ),
.Q(p_14_in),
.R(cs_ce_clr));
LUT6 #(
.INIT(64'h0000000000008000))
\GEN_BKEND_CE_REGISTERS[22].ce_out_i[22]_i_1
(.I0(\GEN_BKEND_CE_REGISTERS[30].ce_out_i[30]_i_2_n_0 ),
.I1(\bus2ip_addr_i_reg[8] [8]),
.I2(Q),
.I3(\bus2ip_addr_i_reg[8] [4]),
.I4(\bus2ip_addr_i_reg[8] [6]),
.I5(\bus2ip_addr_i_reg[8] [5]),
.O(\GEN_BKEND_CE_REGISTERS[22].ce_out_i[22]_i_1_n_0 ));
FDRE \GEN_BKEND_CE_REGISTERS[22].ce_out_i_reg[22]
(.C(s_axi_aclk),
.CE(Q),
.D(\GEN_BKEND_CE_REGISTERS[22].ce_out_i[22]_i_1_n_0 ),
.Q(p_13_in),
.R(cs_ce_clr));
LUT6 #(
.INIT(64'h0000000000008000))
\GEN_BKEND_CE_REGISTERS[23].ce_out_i[23]_i_1
(.I0(\GEN_BKEND_CE_REGISTERS[23].ce_out_i_reg[23]_0 ),
.I1(\bus2ip_addr_i_reg[8] [8]),
.I2(Q),
.I3(\bus2ip_addr_i_reg[8] [4]),
.I4(\bus2ip_addr_i_reg[8] [6]),
.I5(\bus2ip_addr_i_reg[8] [5]),
.O(\GEN_BKEND_CE_REGISTERS[23].ce_out_i[23]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair41" *)
LUT2 #(
.INIT(4'h2))
\GEN_BKEND_CE_REGISTERS[23].ce_out_i[23]_i_2
(.I0(\bus2ip_addr_i_reg[8] [3]),
.I1(\bus2ip_addr_i_reg[8] [2]),
.O(\GEN_BKEND_CE_REGISTERS[23].ce_out_i_reg[23]_0 ));
FDRE \GEN_BKEND_CE_REGISTERS[23].ce_out_i_reg[23]
(.C(s_axi_aclk),
.CE(Q),
.D(\GEN_BKEND_CE_REGISTERS[23].ce_out_i[23]_i_1_n_0 ),
.Q(p_12_in),
.R(cs_ce_clr));
LUT6 #(
.INIT(64'h0000000000008000))
\GEN_BKEND_CE_REGISTERS[24].ce_out_i[24]_i_1
(.I0(\bus2ip_addr_i_reg[8] [3]),
.I1(\bus2ip_addr_i_reg[8] [2]),
.I2(pselect_hit_i_0),
.I3(\bus2ip_addr_i_reg[8] [4]),
.I4(\bus2ip_addr_i_reg[8] [5]),
.I5(\bus2ip_addr_i_reg[8] [6]),
.O(\GEN_BKEND_CE_REGISTERS[24].ce_out_i[24]_i_1_n_0 ));
FDRE \GEN_BKEND_CE_REGISTERS[24].ce_out_i_reg[24]
(.C(s_axi_aclk),
.CE(Q),
.D(\GEN_BKEND_CE_REGISTERS[24].ce_out_i[24]_i_1_n_0 ),
.Q(p_11_in),
.R(cs_ce_clr));
LUT6 #(
.INIT(64'h0000000000800000))
\GEN_BKEND_CE_REGISTERS[25].ce_out_i[25]_i_1
(.I0(\GEN_BKEND_CE_REGISTERS[21].ce_out_i_reg[21]_0 ),
.I1(Q),
.I2(\bus2ip_addr_i_reg[8] [8]),
.I3(\bus2ip_addr_i_reg[8] [6]),
.I4(\bus2ip_addr_i_reg[8] [5]),
.I5(\bus2ip_addr_i_reg[8] [4]),
.O(\GEN_BKEND_CE_REGISTERS[25].ce_out_i[25]_i_1_n_0 ));
FDRE \GEN_BKEND_CE_REGISTERS[25].ce_out_i_reg[25]
(.C(s_axi_aclk),
.CE(Q),
.D(\GEN_BKEND_CE_REGISTERS[25].ce_out_i[25]_i_1_n_0 ),
.Q(p_10_in),
.R(cs_ce_clr));
LUT6 #(
.INIT(64'h4000000000000000))
\GEN_BKEND_CE_REGISTERS[26].ce_out_i[26]_i_1
(.I0(\bus2ip_addr_i_reg[8] [3]),
.I1(Q),
.I2(\bus2ip_addr_i_reg[8] [8]),
.I3(\GEN_BKEND_CE_REGISTERS[26].ce_out_i_reg[26]_0 ),
.I4(\bus2ip_addr_i_reg[8] [5]),
.I5(\bus2ip_addr_i_reg[8] [2]),
.O(\GEN_BKEND_CE_REGISTERS[26].ce_out_i[26]_i_1_n_0 ));
LUT2 #(
.INIT(4'h1))
\GEN_BKEND_CE_REGISTERS[26].ce_out_i[26]_i_2
(.I0(\bus2ip_addr_i_reg[8] [6]),
.I1(\bus2ip_addr_i_reg[8] [4]),
.O(\GEN_BKEND_CE_REGISTERS[26].ce_out_i_reg[26]_0 ));
FDRE \GEN_BKEND_CE_REGISTERS[26].ce_out_i_reg[26]
(.C(s_axi_aclk),
.CE(Q),
.D(\GEN_BKEND_CE_REGISTERS[26].ce_out_i[26]_i_1_n_0 ),
.Q(p_9_in),
.R(cs_ce_clr));
LUT6 #(
.INIT(64'h0000000000400000))
\GEN_BKEND_CE_REGISTERS[27].ce_out_i[27]_i_1
(.I0(\bus2ip_addr_i_reg[8] [2]),
.I1(\bus2ip_addr_i_reg[8] [3]),
.I2(pselect_hit_i_0),
.I3(\bus2ip_addr_i_reg[8] [6]),
.I4(\bus2ip_addr_i_reg[8] [5]),
.I5(\bus2ip_addr_i_reg[8] [4]),
.O(\GEN_BKEND_CE_REGISTERS[27].ce_out_i[27]_i_1_n_0 ));
FDRE \GEN_BKEND_CE_REGISTERS[27].ce_out_i_reg[27]
(.C(s_axi_aclk),
.CE(Q),
.D(\GEN_BKEND_CE_REGISTERS[27].ce_out_i[27]_i_1_n_0 ),
.Q(p_8_in),
.R(cs_ce_clr));
LUT6 #(
.INIT(64'h0000000000800000))
\GEN_BKEND_CE_REGISTERS[28].ce_out_i[28]_i_1
(.I0(\bus2ip_addr_i_reg[8] [3]),
.I1(\bus2ip_addr_i_reg[8] [2]),
.I2(pselect_hit_i_0),
.I3(\bus2ip_addr_i_reg[8] [6]),
.I4(\bus2ip_addr_i_reg[8] [5]),
.I5(\bus2ip_addr_i_reg[8] [4]),
.O(\GEN_BKEND_CE_REGISTERS[28].ce_out_i[28]_i_1_n_0 ));
FDRE \GEN_BKEND_CE_REGISTERS[28].ce_out_i_reg[28]
(.C(s_axi_aclk),
.CE(Q),
.D(\GEN_BKEND_CE_REGISTERS[28].ce_out_i[28]_i_1_n_0 ),
.Q(p_7_in),
.R(cs_ce_clr));
LUT6 #(
.INIT(64'h0000000000000040))
\GEN_BKEND_CE_REGISTERS[29].ce_out_i[29]_i_1
(.I0(\bus2ip_addr_i_reg[8] [3]),
.I1(Q),
.I2(\bus2ip_addr_i_reg[8] [8]),
.I3(\bus2ip_addr_i_reg[8] [6]),
.I4(\bus2ip_addr_i_reg[8] [2]),
.I5(\GEN_BKEND_CE_REGISTERS[29].ce_out_i[29]_i_2_n_0 ),
.O(\GEN_BKEND_CE_REGISTERS[29].ce_out_i[29]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair42" *)
LUT2 #(
.INIT(4'h7))
\GEN_BKEND_CE_REGISTERS[29].ce_out_i[29]_i_2
(.I0(\bus2ip_addr_i_reg[8] [5]),
.I1(\bus2ip_addr_i_reg[8] [4]),
.O(\GEN_BKEND_CE_REGISTERS[29].ce_out_i[29]_i_2_n_0 ));
FDRE \GEN_BKEND_CE_REGISTERS[29].ce_out_i_reg[29]
(.C(s_axi_aclk),
.CE(Q),
.D(\GEN_BKEND_CE_REGISTERS[29].ce_out_i[29]_i_1_n_0 ),
.Q(p_6_in),
.R(cs_ce_clr));
LUT6 #(
.INIT(64'h0000000080000000))
\GEN_BKEND_CE_REGISTERS[30].ce_out_i[30]_i_1
(.I0(\GEN_BKEND_CE_REGISTERS[30].ce_out_i[30]_i_2_n_0 ),
.I1(\bus2ip_addr_i_reg[8] [8]),
.I2(Q),
.I3(\bus2ip_addr_i_reg[8] [4]),
.I4(\bus2ip_addr_i_reg[8] [5]),
.I5(\bus2ip_addr_i_reg[8] [6]),
.O(\GEN_BKEND_CE_REGISTERS[30].ce_out_i[30]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair41" *)
LUT2 #(
.INIT(4'h2))
\GEN_BKEND_CE_REGISTERS[30].ce_out_i[30]_i_2
(.I0(\bus2ip_addr_i_reg[8] [2]),
.I1(\bus2ip_addr_i_reg[8] [3]),
.O(\GEN_BKEND_CE_REGISTERS[30].ce_out_i[30]_i_2_n_0 ));
FDRE \GEN_BKEND_CE_REGISTERS[30].ce_out_i_reg[30]
(.C(s_axi_aclk),
.CE(Q),
.D(\GEN_BKEND_CE_REGISTERS[30].ce_out_i[30]_i_1_n_0 ),
.Q(p_5_in),
.R(cs_ce_clr));
LUT6 #(
.INIT(64'h0000000020000000))
\GEN_BKEND_CE_REGISTERS[31].ce_out_i[31]_i_1
(.I0(\bus2ip_addr_i_reg[8] [3]),
.I1(\bus2ip_addr_i_reg[8] [2]),
.I2(\bus2ip_addr_i_reg[8] [8]),
.I3(Q),
.I4(\bus2ip_addr_i_reg[8] [4]),
.I5(\GEN_BKEND_CE_REGISTERS[31].ce_out_i[31]_i_2_n_0 ),
.O(\GEN_BKEND_CE_REGISTERS[31].ce_out_i[31]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair42" *)
LUT2 #(
.INIT(4'hB))
\GEN_BKEND_CE_REGISTERS[31].ce_out_i[31]_i_2
(.I0(\bus2ip_addr_i_reg[8] [6]),
.I1(\bus2ip_addr_i_reg[8] [5]),
.O(\GEN_BKEND_CE_REGISTERS[31].ce_out_i[31]_i_2_n_0 ));
FDRE \GEN_BKEND_CE_REGISTERS[31].ce_out_i_reg[31]
(.C(s_axi_aclk),
.CE(Q),
.D(\GEN_BKEND_CE_REGISTERS[31].ce_out_i[31]_i_1_n_0 ),
.Q(p_4_in),
.R(cs_ce_clr));
LUT6 #(
.INIT(64'h0800000000000000))
\GEN_BKEND_CE_REGISTERS[32].ce_out_i[32]_i_1
(.I0(\bus2ip_addr_i_reg[8] [3]),
.I1(pselect_hit_i_0),
.I2(\bus2ip_addr_i_reg[8] [6]),
.I3(\bus2ip_addr_i_reg[8] [4]),
.I4(\bus2ip_addr_i_reg[8] [5]),
.I5(\bus2ip_addr_i_reg[8] [2]),
.O(\GEN_BKEND_CE_REGISTERS[32].ce_out_i[32]_i_1_n_0 ));
FDRE \GEN_BKEND_CE_REGISTERS[32].ce_out_i_reg[32]
(.C(s_axi_aclk),
.CE(Q),
.D(\GEN_BKEND_CE_REGISTERS[32].ce_out_i[32]_i_1_n_0 ),
.Q(p_3_in),
.R(cs_ce_clr));
LUT6 #(
.INIT(64'h0008000000000000))
\GEN_BKEND_CE_REGISTERS[33].ce_out_i[33]_i_1
(.I0(Q),
.I1(\bus2ip_addr_i_reg[8] [6]),
.I2(\bus2ip_addr_i_reg[8] [5]),
.I3(\bus2ip_addr_i_reg[8] [4]),
.I4(\GEN_BKEND_CE_REGISTERS[21].ce_out_i_reg[21]_0 ),
.I5(\bus2ip_addr_i_reg[8] [8]),
.O(\GEN_BKEND_CE_REGISTERS[33].ce_out_i[33]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT2 #(
.INIT(4'h1))
\GEN_BKEND_CE_REGISTERS[33].ce_out_i[33]_i_2
(.I0(\bus2ip_addr_i_reg[8] [2]),
.I1(\bus2ip_addr_i_reg[8] [3]),
.O(\GEN_BKEND_CE_REGISTERS[21].ce_out_i_reg[21]_0 ));
FDRE \GEN_BKEND_CE_REGISTERS[33].ce_out_i_reg[33]
(.C(s_axi_aclk),
.CE(Q),
.D(\GEN_BKEND_CE_REGISTERS[33].ce_out_i[33]_i_1_n_0 ),
.Q(p_2_in),
.R(cs_ce_clr));
LUT6 #(
.INIT(64'hFFFFFFFF4F44FFFF))
\GEN_BKEND_CE_REGISTERS[34].ce_out_i[34]_i_1
(.I0(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I1(is_read),
.I2(AXI_IP2Bus_RdAck1),
.I3(AXI_IP2Bus_RdAck2),
.I4(s_axi_aresetn),
.I5(s_axi_wready),
.O(cs_ce_clr));
LUT6 #(
.INIT(64'h0000000800000000))
\GEN_BKEND_CE_REGISTERS[34].ce_out_i[34]_i_2
(.I0(\bus2ip_addr_i_reg[8] [2]),
.I1(pselect_hit_i_0),
.I2(\bus2ip_addr_i_reg[8] [3]),
.I3(\bus2ip_addr_i_reg[8] [4]),
.I4(\bus2ip_addr_i_reg[8] [5]),
.I5(\bus2ip_addr_i_reg[8] [6]),
.O(p_17_out));
FDRE \GEN_BKEND_CE_REGISTERS[34].ce_out_i_reg[34]
(.C(s_axi_aclk),
.CE(Q),
.D(p_17_out),
.Q(\GEN_BKEND_CE_REGISTERS[34].ce_out_i_reg_n_0_[34] ),
.R(cs_ce_clr));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT5 #(
.INIT(32'h00008000))
\GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_1
(.I0(pselect_hit_i_2),
.I1(\bus2ip_addr_i_reg[8] [2]),
.I2(\bus2ip_addr_i_reg[8] [3]),
.I3(\bus2ip_addr_i_reg[8] [4]),
.I4(\bus2ip_addr_i_reg[8] [5]),
.O(p_8_out));
FDRE \GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg[7]
(.C(s_axi_aclk),
.CE(Q),
.D(p_8_out),
.Q(p_28_in),
.R(cs_ce_clr));
LUT6 #(
.INIT(64'h0000000200000000))
\GEN_BKEND_CE_REGISTERS[8].ce_out_i[8]_i_1
(.I0(Q),
.I1(\bus2ip_addr_i_reg[8] [7]),
.I2(\bus2ip_addr_i_reg[8] [8]),
.I3(\bus2ip_addr_i_reg[8] [6]),
.I4(\GEN_BKEND_CE_REGISTERS[10].ce_out_i[10]_i_2_n_0 ),
.I5(\GEN_BKEND_CE_REGISTERS[21].ce_out_i_reg[21]_0 ),
.O(\GEN_BKEND_CE_REGISTERS[8].ce_out_i[8]_i_1_n_0 ));
FDRE \GEN_BKEND_CE_REGISTERS[8].ce_out_i_reg[8]
(.C(s_axi_aclk),
.CE(Q),
.D(\GEN_BKEND_CE_REGISTERS[8].ce_out_i[8]_i_1_n_0 ),
.Q(p_27_in),
.R(cs_ce_clr));
LUT6 #(
.INIT(64'hFFFFFFDFFFFF0020))
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_1
(.I0(s_axi_wdata[0]),
.I1(Bus_RNW_reg),
.I2(p_27_in),
.I3(irpt_wrack_d1),
.I4(IIC2Bus_IntrEvent[0]),
.I5(\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0 ),
.O(\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0] ));
LUT6 #(
.INIT(64'hFFFFFFDFFFFF0020))
\GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg[1]_i_1
(.I0(s_axi_wdata[1]),
.I1(Bus_RNW_reg),
.I2(p_27_in),
.I3(irpt_wrack_d1),
.I4(IIC2Bus_IntrEvent[1]),
.I5(p_1_in17_in),
.O(\GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1] ));
LUT6 #(
.INIT(64'hFFFFFFDFFFFF0020))
\GEN_IP_IRPT_STATUS_REG[2].GEN_REG_STATUS.ip_irpt_status_reg[2]_i_1
(.I0(s_axi_wdata[2]),
.I1(Bus_RNW_reg),
.I2(p_27_in),
.I3(irpt_wrack_d1),
.I4(IIC2Bus_IntrEvent[2]),
.I5(p_1_in14_in),
.O(\GEN_IP_IRPT_STATUS_REG[2].GEN_REG_STATUS.ip_irpt_status_reg_reg[2] ));
LUT6 #(
.INIT(64'hFFFFFFDFFFFF0020))
\GEN_IP_IRPT_STATUS_REG[3].GEN_REG_STATUS.ip_irpt_status_reg[3]_i_1
(.I0(s_axi_wdata[3]),
.I1(Bus_RNW_reg),
.I2(p_27_in),
.I3(irpt_wrack_d1),
.I4(IIC2Bus_IntrEvent[3]),
.I5(p_1_in11_in),
.O(\GEN_IP_IRPT_STATUS_REG[3].GEN_REG_STATUS.ip_irpt_status_reg_reg[3] ));
LUT6 #(
.INIT(64'hFFFFFFDFFFFF0020))
\GEN_IP_IRPT_STATUS_REG[4].GEN_REG_STATUS.ip_irpt_status_reg[4]_i_1
(.I0(s_axi_wdata[4]),
.I1(Bus_RNW_reg),
.I2(p_27_in),
.I3(irpt_wrack_d1),
.I4(IIC2Bus_IntrEvent[4]),
.I5(p_1_in8_in),
.O(\GEN_IP_IRPT_STATUS_REG[4].GEN_REG_STATUS.ip_irpt_status_reg_reg[4] ));
LUT6 #(
.INIT(64'hFFFFFFDFFFFF0020))
\GEN_IP_IRPT_STATUS_REG[5].GEN_REG_STATUS.ip_irpt_status_reg[5]_i_1
(.I0(s_axi_wdata[5]),
.I1(Bus_RNW_reg),
.I2(p_27_in),
.I3(irpt_wrack_d1),
.I4(IIC2Bus_IntrEvent[5]),
.I5(p_1_in5_in),
.O(\GEN_IP_IRPT_STATUS_REG[5].GEN_REG_STATUS.ip_irpt_status_reg_reg[5] ));
LUT6 #(
.INIT(64'hFFFFFFDFFFFF0020))
\GEN_IP_IRPT_STATUS_REG[6].GEN_REG_STATUS.ip_irpt_status_reg[6]_i_1
(.I0(s_axi_wdata[6]),
.I1(Bus_RNW_reg),
.I2(p_27_in),
.I3(irpt_wrack_d1),
.I4(IIC2Bus_IntrEvent[6]),
.I5(p_1_in2_in),
.O(\GEN_IP_IRPT_STATUS_REG[6].GEN_REG_STATUS.ip_irpt_status_reg_reg[6] ));
LUT6 #(
.INIT(64'hFFFFFFDFFFFF0020))
\GEN_IP_IRPT_STATUS_REG[7].GEN_REG_STATUS.ip_irpt_status_reg[7]_i_1
(.I0(s_axi_wdata[7]),
.I1(Bus_RNW_reg),
.I2(p_27_in),
.I3(irpt_wrack_d1),
.I4(IIC2Bus_IntrEvent[7]),
.I5(p_1_in),
.O(\GEN_IP_IRPT_STATUS_REG[7].GEN_REG_STATUS.ip_irpt_status_reg_reg[7] ));
(* SOFT_HLUTNM = "soft_lutpair35" *)
LUT4 #(
.INIT(16'hFB08))
\GPO_GEN.gpo_i[31]_i_2
(.I0(s_axi_wdata[0]),
.I1(p_9_in),
.I2(Bus_RNW_reg),
.I3(gpo),
.O(\GPO_GEN.gpo_i_reg[31] ));
(* SOFT_HLUTNM = "soft_lutpair38" *)
LUT4 #(
.INIT(16'h0010))
\MEM_DECODE_GEN[0].cs_out_i[0]_i_1
(.I0(\bus2ip_addr_i_reg[8] [7]),
.I1(\bus2ip_addr_i_reg[8] [8]),
.I2(Q),
.I3(\bus2ip_addr_i_reg[8] [6]),
.O(pselect_hit_i_2));
FDRE \MEM_DECODE_GEN[0].cs_out_i_reg[0]
(.C(s_axi_aclk),
.CE(Q),
.D(pselect_hit_i_2),
.Q(\MEM_DECODE_GEN[0].cs_out_i_reg ),
.R(cs_ce_clr));
LUT6 #(
.INIT(64'h0000000000008000))
\MEM_DECODE_GEN[1].cs_out_i[1]_i_1
(.I0(Q),
.I1(\bus2ip_addr_i_reg[8] [6]),
.I2(\GEN_BKEND_CE_REGISTERS[18].ce_out_i[18]_i_2_n_0 ),
.I3(\GEN_BKEND_CE_REGISTERS[21].ce_out_i_reg[21]_0 ),
.I4(\bus2ip_addr_i_reg[8] [8]),
.I5(\bus2ip_addr_i_reg[8] [7]),
.O(\MEM_DECODE_GEN[1].GEN_FOR_MULTI_CS.MEM_SELECT_I/CS ));
FDRE \MEM_DECODE_GEN[1].cs_out_i_reg[1]
(.C(s_axi_aclk),
.CE(Q),
.D(\MEM_DECODE_GEN[1].GEN_FOR_MULTI_CS.MEM_SELECT_I/CS ),
.Q(\MEM_DECODE_GEN[1].cs_out_i_reg ),
.R(cs_ce_clr));
(* SOFT_HLUTNM = "soft_lutpair38" *)
LUT2 #(
.INIT(4'h8))
\MEM_DECODE_GEN[2].cs_out_i[2]_i_1
(.I0(Q),
.I1(\bus2ip_addr_i_reg[8] [8]),
.O(pselect_hit_i_0));
FDRE \MEM_DECODE_GEN[2].cs_out_i_reg[2]
(.C(s_axi_aclk),
.CE(Q),
.D(pselect_hit_i_0),
.Q(\MEM_DECODE_GEN[2].cs_out_i_reg ),
.R(cs_ce_clr));
(* SOFT_HLUTNM = "soft_lutpair46" *)
LUT2 #(
.INIT(4'h8))
\RD_FIFO_CNTRL.Rc_fifo_rd_i_1
(.I0(Bus_RNW_reg),
.I1(p_15_in),
.O(Bus2IIC_RdCE));
(* SOFT_HLUTNM = "soft_lutpair43" *)
LUT2 #(
.INIT(4'h2))
\RD_FIFO_CNTRL.rc_fifo_pirq_i[4]_i_1
(.I0(p_10_in),
.I1(Bus_RNW_reg),
.O(Bus2IIC_WrCE[8]));
(* SOFT_HLUTNM = "soft_lutpair39" *)
LUT2 #(
.INIT(4'h2))
\adr_i[0]_i_1
(.I0(p_14_in),
.I1(Bus_RNW_reg),
.O(Bus2IIC_WrCE[9]));
(* SOFT_HLUTNM = "soft_lutpair36" *)
LUT2 #(
.INIT(4'h2))
\cr_i[0]_i_1
(.I0(p_18_in),
.I1(Bus_RNW_reg),
.O(Bus2IIC_WrCE[11]));
LUT6 #(
.INIT(64'h08080808FBFBFB08))
\cr_i[4]_i_1
(.I0(s_axi_wdata[3]),
.I1(p_18_in),
.I2(Bus_RNW_reg),
.I3(\cr_i_reg[4]_0 ),
.I4(cr_txModeSelect_set),
.I5(cr_txModeSelect_clr),
.O(\cr_i_reg[4] ));
(* SOFT_HLUTNM = "soft_lutpair35" *)
LUT2 #(
.INIT(4'h2))
\ip_irpt_enable_reg[7]_i_1
(.I0(p_25_in),
.I1(Bus_RNW_reg),
.O(E));
(* SOFT_HLUTNM = "soft_lutpair36" *)
LUT4 #(
.INIT(16'hFB08))
ipif_glbl_irpt_enable_reg_i_1
(.I0(s_axi_wdata[8]),
.I1(p_28_in),
.I2(Bus_RNW_reg),
.I3(ipif_glbl_irpt_enable_reg),
.O(ipif_glbl_irpt_enable_reg_reg));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT4 #(
.INIT(16'h0F0E))
irpt_wrack_d1_i_1
(.I0(p_25_in),
.I1(p_28_in),
.I2(Bus_RNW_reg),
.I3(p_27_in),
.O(irpt_wrack));
LUT2 #(
.INIT(4'h2))
reset_trig_i_1
(.I0(sw_rst_cond),
.I1(sw_rst_cond_d1),
.O(reset_trig0));
LUT4 #(
.INIT(16'hFB08))
\s_axi_bresp_i[1]_i_1
(.I0(AXI_IP2Bus_Error),
.I1(\state_reg[1] [1]),
.I2(\state_reg[1] [0]),
.I3(s_axi_bresp),
.O(\s_axi_bresp_i_reg[1] ));
LUT6 #(
.INIT(64'hFFEAAAAAAAEAAAAA))
\s_axi_rdata_i[0]_i_1
(.I0(\s_axi_rdata_i[0]_i_2_n_0 ),
.I1(p_25_in),
.I2(\ip_irpt_enable_reg_reg[7] [0]),
.I3(p_27_in),
.I4(Bus_RNW_reg),
.I5(\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0 ),
.O(D[0]));
LUT6 #(
.INIT(64'h00000000000000DF))
\s_axi_rdata_i[0]_i_2
(.I0(\bus2ip_addr_i_reg[6] ),
.I1(\bus2ip_addr_i_reg[8] [3]),
.I2(\bus2ip_addr_i_reg[8] [2]),
.I3(\s_axi_rdata_i[9]_i_3_n_0 ),
.I4(\timing_param_thdsta_i_reg[0] ),
.I5(\timing_param_thigh_i_reg[0] ),
.O(\s_axi_rdata_i[0]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFEAAAAAAAEAAAAA))
\s_axi_rdata_i[1]_i_1
(.I0(\s_axi_rdata_i[1]_i_2_n_0 ),
.I1(p_25_in),
.I2(\ip_irpt_enable_reg_reg[7] [1]),
.I3(p_27_in),
.I4(Bus_RNW_reg),
.I5(p_1_in17_in),
.O(D[1]));
LUT6 #(
.INIT(64'h00000000C8CCC8C0))
\s_axi_rdata_i[1]_i_2
(.I0(\Addr_Counters[1].FDRE_I ),
.I1(\timing_param_thigh_i_reg[1] ),
.I2(\bus2ip_addr_i_reg[8] [3]),
.I3(\bus2ip_addr_i_reg[8] [2]),
.I4(\adr_i_reg[6] ),
.I5(\s_axi_rdata_i[9]_i_3_n_0 ),
.O(\s_axi_rdata_i[1]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFEAAAAAAAEAAAAA))
\s_axi_rdata_i[2]_i_1
(.I0(\s_axi_rdata_i[2]_i_2_n_0 ),
.I1(p_25_in),
.I2(\ip_irpt_enable_reg_reg[7] [2]),
.I3(p_27_in),
.I4(Bus_RNW_reg),
.I5(p_1_in14_in),
.O(D[2]));
LUT6 #(
.INIT(64'h000000000000FEBA))
\s_axi_rdata_i[2]_i_2
(.I0(\bus2ip_addr_i_reg[8] [3]),
.I1(\bus2ip_addr_i_reg[8] [2]),
.I2(\adr_i_reg[5] ),
.I3(\Addr_Counters[2].FDRE_I ),
.I4(\timing_param_thigh_i_reg[2] ),
.I5(\s_axi_rdata_i[9]_i_3_n_0 ),
.O(\s_axi_rdata_i[2]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT5 #(
.INIT(32'h00000080))
\s_axi_rdata_i[31]_i_2
(.I0(p_28_in),
.I1(ipif_glbl_irpt_enable_reg),
.I2(Bus_RNW_reg),
.I3(p_27_in),
.I4(p_25_in),
.O(D[10]));
LUT6 #(
.INIT(64'hFFEAAAAAAAEAAAAA))
\s_axi_rdata_i[3]_i_1
(.I0(\s_axi_rdata_i[3]_i_2_n_0 ),
.I1(p_25_in),
.I2(\ip_irpt_enable_reg_reg[7] [3]),
.I3(p_27_in),
.I4(Bus_RNW_reg),
.I5(p_1_in11_in),
.O(D[3]));
LUT6 #(
.INIT(64'h0000000055455540))
\s_axi_rdata_i[3]_i_2
(.I0(\bus2ip_addr_i_reg[2] ),
.I1(\timing_param_tbuf_i_reg[3] ),
.I2(\bus2ip_addr_i_reg[8] [3]),
.I3(\bus2ip_addr_i_reg[8] [2]),
.I4(\adr_i_reg[4] ),
.I5(\s_axi_rdata_i[9]_i_3_n_0 ),
.O(\s_axi_rdata_i[3]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFEAAAAAAAEAAAAA))
\s_axi_rdata_i[4]_i_1
(.I0(\s_axi_rdata_i[4]_i_2_n_0 ),
.I1(p_25_in),
.I2(\ip_irpt_enable_reg_reg[7] [4]),
.I3(p_27_in),
.I4(Bus_RNW_reg),
.I5(p_1_in8_in),
.O(D[4]));
LUT6 #(
.INIT(64'h000000000000AAFC))
\s_axi_rdata_i[4]_i_2
(.I0(\bus2ip_addr_i_reg[5] ),
.I1(\adr_i_reg[3] ),
.I2(\bus2ip_addr_i_reg[8] [2]),
.I3(\bus2ip_addr_i_reg[8] [3]),
.I4(\bus2ip_addr_i_reg[5]_0 ),
.I5(\s_axi_rdata_i[9]_i_3_n_0 ),
.O(\s_axi_rdata_i[4]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFEAAAAAAAEAAAAA))
\s_axi_rdata_i[5]_i_1
(.I0(\s_axi_rdata_i[5]_i_2_n_0 ),
.I1(p_25_in),
.I2(\ip_irpt_enable_reg_reg[7] [5]),
.I3(p_27_in),
.I4(Bus_RNW_reg),
.I5(p_1_in5_in),
.O(D[5]));
LUT6 #(
.INIT(64'h000000000000AAFC))
\s_axi_rdata_i[5]_i_2
(.I0(\bus2ip_addr_i_reg[5]_1 ),
.I1(\adr_i_reg[2] ),
.I2(\bus2ip_addr_i_reg[8] [2]),
.I3(\bus2ip_addr_i_reg[8] [3]),
.I4(\bus2ip_addr_i_reg[5]_2 ),
.I5(\s_axi_rdata_i[9]_i_3_n_0 ),
.O(\s_axi_rdata_i[5]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFEAAAAAAAEAAAAA))
\s_axi_rdata_i[6]_i_1
(.I0(\s_axi_rdata_i[6]_i_2_n_0 ),
.I1(p_25_in),
.I2(\ip_irpt_enable_reg_reg[7] [6]),
.I3(p_27_in),
.I4(Bus_RNW_reg),
.I5(p_1_in2_in),
.O(D[6]));
LUT6 #(
.INIT(64'h00000000AAAAF0CC))
\s_axi_rdata_i[6]_i_2
(.I0(\bus2ip_addr_i_reg[5]_3 ),
.I1(\adr_i_reg[1] ),
.I2(\timing_param_tsudat_i_reg[6] ),
.I3(\bus2ip_addr_i_reg[8] [2]),
.I4(\bus2ip_addr_i_reg[8] [3]),
.I5(\s_axi_rdata_i[9]_i_3_n_0 ),
.O(\s_axi_rdata_i[6]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFEAAAAAAAEAAAAA))
\s_axi_rdata_i[7]_i_1
(.I0(\s_axi_rdata_i[7]_i_2_n_0 ),
.I1(p_25_in),
.I2(\ip_irpt_enable_reg_reg[7] [7]),
.I3(p_27_in),
.I4(Bus_RNW_reg),
.I5(p_1_in),
.O(D[7]));
LUT6 #(
.INIT(64'h00000000AAAAF0CC))
\s_axi_rdata_i[7]_i_2
(.I0(\bus2ip_addr_i_reg[5]_4 ),
.I1(\adr_i_reg[0] ),
.I2(\timing_param_tsudat_i_reg[7] ),
.I3(\bus2ip_addr_i_reg[8] [2]),
.I4(\bus2ip_addr_i_reg[8] [3]),
.I5(\s_axi_rdata_i[9]_i_3_n_0 ),
.O(\s_axi_rdata_i[7]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0000000222200000))
\s_axi_rdata_i[8]_i_1
(.I0(\bus2ip_addr_i_reg[2]_0 ),
.I1(\s_axi_rdata_i[9]_i_3_n_0 ),
.I2(\bus2ip_addr_i_reg[8] [3]),
.I3(\bus2ip_addr_i_reg[8] [4]),
.I4(\bus2ip_addr_i_reg[8] [5]),
.I5(\bus2ip_addr_i_reg[8] [6]),
.O(D[8]));
LUT6 #(
.INIT(64'h0000000222200000))
\s_axi_rdata_i[9]_i_1
(.I0(\bus2ip_addr_i_reg[2]_1 ),
.I1(\s_axi_rdata_i[9]_i_3_n_0 ),
.I2(\bus2ip_addr_i_reg[8] [3]),
.I3(\bus2ip_addr_i_reg[8] [4]),
.I4(\bus2ip_addr_i_reg[8] [5]),
.I5(\bus2ip_addr_i_reg[8] [6]),
.O(D[9]));
LUT6 #(
.INIT(64'hFFFFFFF4FFFFFFFF))
\s_axi_rdata_i[9]_i_3
(.I0(\s_axi_rdata_i[9]_i_6_n_0 ),
.I1(\s_axi_rdata_i[9]_i_7_n_0 ),
.I2(\bus2ip_addr_i_reg[8] [7]),
.I3(\bus2ip_addr_i_reg[8] [0]),
.I4(\bus2ip_addr_i_reg[8] [1]),
.I5(Bus_RNW_reg),
.O(\s_axi_rdata_i[9]_i_3_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\s_axi_rdata_i[9]_i_6
(.I0(p_9_in),
.I1(p_12_in),
.I2(p_13_in),
.I3(p_14_in),
.I4(\s_axi_rdata_i[9]_i_8_n_0 ),
.I5(\s_axi_rdata_i[9]_i_9_n_0 ),
.O(\s_axi_rdata_i[9]_i_6_n_0 ));
LUT6 #(
.INIT(64'h0000000000000001))
\s_axi_rdata_i[9]_i_7
(.I0(p_17_in),
.I1(p_4_in),
.I2(p_10_in),
.I3(p_11_in),
.I4(p_6_in),
.I5(p_16_in),
.O(\s_axi_rdata_i[9]_i_7_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT4 #(
.INIT(16'hFFFE))
\s_axi_rdata_i[9]_i_8
(.I0(p_7_in),
.I1(p_5_in),
.I2(p_15_in),
.I3(p_3_in),
.O(\s_axi_rdata_i[9]_i_8_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair34" *)
LUT4 #(
.INIT(16'hFFFE))
\s_axi_rdata_i[9]_i_9
(.I0(p_8_in),
.I1(p_2_in),
.I2(p_18_in),
.I3(\GEN_BKEND_CE_REGISTERS[34].ce_out_i_reg_n_0_[34] ),
.O(\s_axi_rdata_i[9]_i_9_n_0 ));
LUT6 #(
.INIT(64'h4440444444444444))
\s_axi_rresp_i[1]_i_1
(.I0(Bus_RNW_reg),
.I1(\MEM_DECODE_GEN[1].cs_out_i_reg ),
.I2(s_axi_wdata[0]),
.I3(s_axi_wdata[2]),
.I4(s_axi_wdata[1]),
.I5(s_axi_wdata[3]),
.O(AXI_IP2Bus_Error));
LUT4 #(
.INIT(16'h4F44))
s_axi_wready_INST_0
(.I0(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I1(is_write_reg),
.I2(AXI_IP2Bus_WrAck1),
.I3(AXI_IP2Bus_WrAck2),
.O(s_axi_wready));
LUT4 #(
.INIT(16'hFFEF))
s_axi_wready_INST_0_i_1
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [1]),
.I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [0]),
.I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [3]),
.I3(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [2]),
.O(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ));
LUT6 #(
.INIT(64'h0004000000000000))
sw_rst_cond_d1_i_1
(.I0(Bus_RNW_reg),
.I1(\MEM_DECODE_GEN[1].cs_out_i_reg ),
.I2(s_axi_wdata[0]),
.I3(s_axi_wdata[2]),
.I4(s_axi_wdata[1]),
.I5(s_axi_wdata[3]),
.O(sw_rst_cond));
(* SOFT_HLUTNM = "soft_lutpair44" *)
LUT2 #(
.INIT(4'h2))
\timing_param_tbuf_i[9]_i_1
(.I0(p_4_in),
.I1(Bus_RNW_reg),
.O(Bus2IIC_WrCE[3]));
(* SOFT_HLUTNM = "soft_lutpair46" *)
LUT2 #(
.INIT(4'h2))
\timing_param_thddat_i[9]_i_1
(.I0(\GEN_BKEND_CE_REGISTERS[34].ce_out_i_reg_n_0_[34] ),
.I1(Bus_RNW_reg),
.O(Bus2IIC_WrCE[0]));
(* SOFT_HLUTNM = "soft_lutpair44" *)
LUT2 #(
.INIT(4'h2))
\timing_param_thdsta_i[9]_i_1
(.I0(p_6_in),
.I1(Bus_RNW_reg),
.O(Bus2IIC_WrCE[5]));
(* SOFT_HLUTNM = "soft_lutpair45" *)
LUT2 #(
.INIT(4'h2))
\timing_param_thigh_i[9]_i_1
(.I0(p_3_in),
.I1(Bus_RNW_reg),
.O(Bus2IIC_WrCE[2]));
(* SOFT_HLUTNM = "soft_lutpair45" *)
LUT2 #(
.INIT(4'h2))
\timing_param_tlow_i[9]_i_1
(.I0(p_2_in),
.I1(Bus_RNW_reg),
.O(Bus2IIC_WrCE[1]));
(* SOFT_HLUTNM = "soft_lutpair43" *)
LUT2 #(
.INIT(4'h2))
\timing_param_tsudat_i[9]_i_1
(.I0(p_5_in),
.I1(Bus_RNW_reg),
.O(Bus2IIC_WrCE[4]));
(* SOFT_HLUTNM = "soft_lutpair34" *)
LUT2 #(
.INIT(4'h2))
\timing_param_tsusta_i[9]_i_1
(.I0(p_8_in),
.I1(Bus_RNW_reg),
.O(Bus2IIC_WrCE[7]));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT2 #(
.INIT(4'h2))
\timing_param_tsusto_i[9]_i_1
(.I0(p_7_in),
.I1(Bus_RNW_reg),
.O(Bus2IIC_WrCE[6]));
endmodule
(* C_DEFAULT_VALUE = "8'b00000000" *) (* C_FAMILY = "artix7" *) (* C_GPO_WIDTH = "1" *)
(* C_IIC_FREQ = "100000" *) (* C_SCL_INERTIAL_DELAY = "0" *) (* C_SDA_INERTIAL_DELAY = "0" *)
(* C_SDA_LEVEL = "1" *) (* C_SMBUS_PMBUS_HOST = "0" *) (* C_S_AXI_ACLK_FREQ_HZ = "100000000" *)
(* C_S_AXI_ADDR_WIDTH = "9" *) (* C_S_AXI_DATA_WIDTH = "32" *) (* C_TEN_BIT_ADR = "0" *)
(* ORIG_REF_NAME = "axi_iic" *) (* downgradeipidentifiedwarnings = "yes" *)
module system_axi_iic_0_0_axi_iic
(s_axi_aclk,
s_axi_aresetn,
iic2intc_irpt,
s_axi_awaddr,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rvalid,
s_axi_rready,
sda_i,
sda_o,
sda_t,
scl_i,
scl_o,
scl_t,
gpo);
input s_axi_aclk;
input s_axi_aresetn;
output iic2intc_irpt;
input [8:0]s_axi_awaddr;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wvalid;
output s_axi_wready;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [8:0]s_axi_araddr;
input s_axi_arvalid;
output s_axi_arready;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rvalid;
input s_axi_rready;
input sda_i;
output sda_o;
output sda_t;
input scl_i;
output scl_o;
output scl_t;
output [0:0]gpo;
wire \<const0> ;
wire [0:0]gpo;
wire iic2intc_irpt;
wire s_axi_aclk;
wire [8:0]s_axi_araddr;
wire s_axi_aresetn;
wire s_axi_arready;
wire s_axi_arvalid;
wire [8:0]s_axi_awaddr;
wire s_axi_awvalid;
wire s_axi_bready;
wire [1:1]\^s_axi_bresp ;
wire s_axi_bvalid;
wire [31:0]\^s_axi_rdata ;
wire s_axi_rready;
wire [1:1]\^s_axi_rresp ;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire s_axi_wready;
wire s_axi_wvalid;
wire scl_i;
wire scl_t;
wire sda_i;
wire sda_t;
assign s_axi_awready = s_axi_wready;
assign s_axi_bresp[1] = \^s_axi_bresp [1];
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_rdata[31] = \^s_axi_rdata [31];
assign s_axi_rdata[30] = \<const0> ;
assign s_axi_rdata[29] = \<const0> ;
assign s_axi_rdata[28] = \<const0> ;
assign s_axi_rdata[27] = \<const0> ;
assign s_axi_rdata[26] = \<const0> ;
assign s_axi_rdata[25] = \<const0> ;
assign s_axi_rdata[24] = \<const0> ;
assign s_axi_rdata[23] = \<const0> ;
assign s_axi_rdata[22] = \<const0> ;
assign s_axi_rdata[21] = \<const0> ;
assign s_axi_rdata[20] = \<const0> ;
assign s_axi_rdata[19] = \<const0> ;
assign s_axi_rdata[18] = \<const0> ;
assign s_axi_rdata[17] = \<const0> ;
assign s_axi_rdata[16] = \<const0> ;
assign s_axi_rdata[15] = \<const0> ;
assign s_axi_rdata[14] = \<const0> ;
assign s_axi_rdata[13] = \<const0> ;
assign s_axi_rdata[12] = \<const0> ;
assign s_axi_rdata[11] = \<const0> ;
assign s_axi_rdata[10] = \<const0> ;
assign s_axi_rdata[9:0] = \^s_axi_rdata [9:0];
assign s_axi_rresp[1] = \^s_axi_rresp [1];
assign s_axi_rresp[0] = \<const0> ;
assign scl_o = \<const0> ;
assign sda_o = \<const0> ;
GND GND
(.G(\<const0> ));
system_axi_iic_0_0_iic X_IIC
(.gpo(gpo),
.iic2intc_irpt(iic2intc_irpt),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr(s_axi_araddr),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(\^s_axi_bresp ),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata({\^s_axi_rdata [31],\^s_axi_rdata [9:0]}),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(\^s_axi_rresp ),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata({s_axi_wdata[31],s_axi_wdata[9:0]}),
.s_axi_wready(s_axi_wready),
.s_axi_wvalid(s_axi_wvalid),
.scl_i(scl_i),
.scl_t(scl_t),
.sda_i(sda_i),
.sda_t(sda_t));
endmodule
(* ORIG_REF_NAME = "axi_ipif_ssp1" *)
module system_axi_iic_0_0_axi_ipif_ssp1
(s_axi_rresp,
Bus2IIC_Reset,
s_axi_rvalid,
s_axi_bvalid,
s_axi_bresp,
Q,
s_axi_wready,
s_axi_arready,
ctrlFifoDin,
Bus2IIC_RdCE,
\cr_i_reg[4] ,
Bus2IIC_WrCE,
iic2intc_irpt,
\GPO_GEN.gpo_i_reg[31] ,
s_axi_rdata,
s_axi_aclk,
\timing_param_tsudat_i_reg[5] ,
\cr_i_reg[4]_0 ,
\timing_param_tlow_i_reg[0] ,
\RD_FIFO_CNTRL.rc_fifo_pirq_i_reg[7] ,
s_axi_aresetn,
s_axi_arvalid,
s_axi_rready,
s_axi_bready,
s_axi_wvalid,
s_axi_awvalid,
s_axi_araddr,
s_axi_awaddr,
s_axi_wdata,
IIC2Bus_IntrEvent,
Tx_fifo_rst,
\timing_param_thdsta_i_reg[0] ,
\adr_i_reg[6] ,
\adr_i_reg[5] ,
\timing_param_tbuf_i_reg[3] ,
\adr_i_reg[4] ,
\adr_i_reg[3] ,
\adr_i_reg[2] ,
\adr_i_reg[1] ,
\timing_param_tsudat_i_reg[6] ,
\adr_i_reg[0] ,
\timing_param_tsudat_i_reg[7] ,
Tx_fifo_data,
\timing_param_tsusta_i_reg[7] ,
\timing_param_tsusto_i_reg[7] ,
Rc_fifo_data,
\timing_param_thigh_i_reg[7] ,
\timing_param_tbuf_i_reg[1] ,
\timing_param_tbuf_i_reg[0] ,
\timing_param_tbuf_i_reg[2] ,
\sr_i_reg[2] ,
\timing_param_thddat_i_reg[5] ,
\timing_param_tbuf_i_reg[7] ,
Tx_addr,
\GPO_GEN.gpo_i_reg[31]_0 ,
\bus2ip_addr_i_reg[2] ,
\bus2ip_addr_i_reg[2]_0 ,
cr_txModeSelect_set,
cr_txModeSelect_clr,
\sr_i_reg[4] ,
\sr_i_reg[5] ,
\IIC2Bus_IntrEvent_reg[5] ,
gpo);
output [0:0]s_axi_rresp;
output Bus2IIC_Reset;
output s_axi_rvalid;
output s_axi_bvalid;
output [0:0]s_axi_bresp;
output [4:0]Q;
output s_axi_wready;
output s_axi_arready;
output [0:1]ctrlFifoDin;
output [0:0]Bus2IIC_RdCE;
output [0:0]\cr_i_reg[4] ;
output [11:0]Bus2IIC_WrCE;
output iic2intc_irpt;
output \GPO_GEN.gpo_i_reg[31] ;
output [10:0]s_axi_rdata;
input s_axi_aclk;
input [5:0]\timing_param_tsudat_i_reg[5] ;
input [1:0]\cr_i_reg[4]_0 ;
input [0:0]\timing_param_tlow_i_reg[0] ;
input [0:0]\RD_FIFO_CNTRL.rc_fifo_pirq_i_reg[7] ;
input s_axi_aresetn;
input s_axi_arvalid;
input s_axi_rready;
input s_axi_bready;
input s_axi_wvalid;
input s_axi_awvalid;
input [8:0]s_axi_araddr;
input [8:0]s_axi_awaddr;
input [10:0]s_axi_wdata;
input [0:7]IIC2Bus_IntrEvent;
input Tx_fifo_rst;
input [0:0]\timing_param_thdsta_i_reg[0] ;
input \adr_i_reg[6] ;
input \adr_i_reg[5] ;
input \timing_param_tbuf_i_reg[3] ;
input \adr_i_reg[4] ;
input \adr_i_reg[3] ;
input \adr_i_reg[2] ;
input \adr_i_reg[1] ;
input \timing_param_tsudat_i_reg[6] ;
input \adr_i_reg[0] ;
input \timing_param_tsudat_i_reg[7] ;
input [3:0]Tx_fifo_data;
input [3:0]\timing_param_tsusta_i_reg[7] ;
input [7:0]\timing_param_tsusto_i_reg[7] ;
input [0:7]Rc_fifo_data;
input [7:0]\timing_param_thigh_i_reg[7] ;
input \timing_param_tbuf_i_reg[1] ;
input \timing_param_tbuf_i_reg[0] ;
input \timing_param_tbuf_i_reg[2] ;
input [1:0]\sr_i_reg[2] ;
input [1:0]\timing_param_thddat_i_reg[5] ;
input [3:0]\timing_param_tbuf_i_reg[7] ;
input [0:3]Tx_addr;
input \GPO_GEN.gpo_i_reg[31]_0 ;
input \bus2ip_addr_i_reg[2] ;
input \bus2ip_addr_i_reg[2]_0 ;
input cr_txModeSelect_set;
input cr_txModeSelect_clr;
input \sr_i_reg[4] ;
input \sr_i_reg[5] ;
input \IIC2Bus_IntrEvent_reg[5] ;
input [0:0]gpo;
wire AXI_Bus2IP_Reset;
wire [10:10]AXI_Bus2IP_WrCE;
wire AXI_IP2Bus_RdAck1;
wire AXI_IP2Bus_RdAck2;
wire AXI_IP2Bus_RdAck20;
wire AXI_IP2Bus_WrAck1;
wire AXI_IP2Bus_WrAck2;
wire AXI_LITE_IPIF_I_n_13;
wire AXI_LITE_IPIF_I_n_14;
wire AXI_LITE_IPIF_I_n_15;
wire AXI_LITE_IPIF_I_n_16;
wire AXI_LITE_IPIF_I_n_17;
wire AXI_LITE_IPIF_I_n_18;
wire AXI_LITE_IPIF_I_n_19;
wire AXI_LITE_IPIF_I_n_20;
wire AXI_LITE_IPIF_I_n_39;
wire AXI_LITE_IPIF_I_n_9;
wire [0:0]Bus2IIC_RdCE;
wire Bus2IIC_Reset;
wire [11:0]Bus2IIC_WrCE;
wire \GPO_GEN.gpo_i_reg[31] ;
wire \GPO_GEN.gpo_i_reg[31]_0 ;
wire [0:7]IIC2Bus_IntrEvent;
wire \IIC2Bus_IntrEvent_reg[5] ;
wire [4:0]Q;
wire [0:0]\RD_FIFO_CNTRL.rc_fifo_pirq_i_reg[7] ;
wire [0:7]Rc_fifo_data;
wire [0:3]Tx_addr;
wire [3:0]Tx_fifo_data;
wire Tx_fifo_rst;
wire X_INTERRUPT_CONTROL_n_1;
wire X_INTERRUPT_CONTROL_n_18;
wire \adr_i_reg[0] ;
wire \adr_i_reg[1] ;
wire \adr_i_reg[2] ;
wire \adr_i_reg[3] ;
wire \adr_i_reg[4] ;
wire \adr_i_reg[5] ;
wire \adr_i_reg[6] ;
wire \bus2ip_addr_i_reg[2] ;
wire \bus2ip_addr_i_reg[2]_0 ;
wire [0:0]\cr_i_reg[4] ;
wire [1:0]\cr_i_reg[4]_0 ;
wire cr_txModeSelect_clr;
wire cr_txModeSelect_set;
wire [0:1]ctrlFifoDin;
wire [0:0]gpo;
wire iic2intc_irpt;
wire ipif_glbl_irpt_enable_reg;
wire irpt_wrack;
wire irpt_wrack_d1;
wire p_0_in;
wire p_0_in10_in;
wire p_0_in13_in;
wire p_0_in16_in;
wire p_0_in1_in;
wire p_0_in4_in;
wire p_0_in7_in;
wire p_1_in;
wire p_1_in11_in;
wire p_1_in14_in;
wire p_1_in17_in;
wire p_1_in2_in;
wire p_1_in5_in;
wire p_1_in8_in;
wire reset_trig0;
wire s_axi_aclk;
wire [8:0]s_axi_araddr;
wire s_axi_aresetn;
wire s_axi_arready;
wire s_axi_arvalid;
wire [8:0]s_axi_awaddr;
wire s_axi_awvalid;
wire s_axi_bready;
wire [0:0]s_axi_bresp;
wire s_axi_bvalid;
wire [10:0]s_axi_rdata;
wire s_axi_rready;
wire [0:0]s_axi_rresp;
wire s_axi_rvalid;
wire [10:0]s_axi_wdata;
wire s_axi_wready;
wire s_axi_wvalid;
wire [1:0]\sr_i_reg[2] ;
wire \sr_i_reg[4] ;
wire \sr_i_reg[5] ;
wire sw_rst_cond;
wire sw_rst_cond_d1;
wire \timing_param_tbuf_i_reg[0] ;
wire \timing_param_tbuf_i_reg[1] ;
wire \timing_param_tbuf_i_reg[2] ;
wire \timing_param_tbuf_i_reg[3] ;
wire [3:0]\timing_param_tbuf_i_reg[7] ;
wire [1:0]\timing_param_thddat_i_reg[5] ;
wire [0:0]\timing_param_thdsta_i_reg[0] ;
wire [7:0]\timing_param_thigh_i_reg[7] ;
wire [0:0]\timing_param_tlow_i_reg[0] ;
wire [5:0]\timing_param_tsudat_i_reg[5] ;
wire \timing_param_tsudat_i_reg[6] ;
wire \timing_param_tsudat_i_reg[7] ;
wire [3:0]\timing_param_tsusta_i_reg[7] ;
wire [7:0]\timing_param_tsusto_i_reg[7] ;
FDRE AXI_IP2Bus_RdAck1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(AXI_IP2Bus_RdAck2),
.Q(AXI_IP2Bus_RdAck1),
.R(1'b0));
FDRE AXI_IP2Bus_RdAck2_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(AXI_IP2Bus_RdAck20),
.Q(AXI_IP2Bus_RdAck2),
.R(1'b0));
FDRE AXI_IP2Bus_WrAck1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(AXI_IP2Bus_WrAck2),
.Q(AXI_IP2Bus_WrAck1),
.R(1'b0));
FDRE AXI_IP2Bus_WrAck2_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(AXI_LITE_IPIF_I_n_9),
.Q(AXI_IP2Bus_WrAck2),
.R(1'b0));
system_axi_iic_0_0_axi_lite_ipif AXI_LITE_IPIF_I
(.AXI_Bus2IP_Reset(AXI_Bus2IP_Reset),
.AXI_IP2Bus_RdAck1(AXI_IP2Bus_RdAck1),
.AXI_IP2Bus_RdAck2(AXI_IP2Bus_RdAck2),
.AXI_IP2Bus_RdAck20(AXI_IP2Bus_RdAck20),
.AXI_IP2Bus_WrAck1(AXI_IP2Bus_WrAck1),
.AXI_IP2Bus_WrAck2(AXI_IP2Bus_WrAck2),
.AXI_IP2Bus_WrAck2_reg(AXI_LITE_IPIF_I_n_9),
.Bus2IIC_RdCE(Bus2IIC_RdCE),
.Bus2IIC_WrCE(Bus2IIC_WrCE),
.E(AXI_Bus2IP_WrCE),
.\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0] (AXI_LITE_IPIF_I_n_20),
.\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0 (X_INTERRUPT_CONTROL_n_1),
.\GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1] (AXI_LITE_IPIF_I_n_19),
.\GEN_IP_IRPT_STATUS_REG[2].GEN_REG_STATUS.ip_irpt_status_reg_reg[2] (AXI_LITE_IPIF_I_n_18),
.\GEN_IP_IRPT_STATUS_REG[3].GEN_REG_STATUS.ip_irpt_status_reg_reg[3] (AXI_LITE_IPIF_I_n_17),
.\GEN_IP_IRPT_STATUS_REG[4].GEN_REG_STATUS.ip_irpt_status_reg_reg[4] (AXI_LITE_IPIF_I_n_16),
.\GEN_IP_IRPT_STATUS_REG[5].GEN_REG_STATUS.ip_irpt_status_reg_reg[5] (AXI_LITE_IPIF_I_n_15),
.\GEN_IP_IRPT_STATUS_REG[6].GEN_REG_STATUS.ip_irpt_status_reg_reg[6] (AXI_LITE_IPIF_I_n_14),
.\GEN_IP_IRPT_STATUS_REG[7].GEN_REG_STATUS.ip_irpt_status_reg_reg[7] (AXI_LITE_IPIF_I_n_13),
.\GPO_GEN.gpo_i_reg[31] (\GPO_GEN.gpo_i_reg[31] ),
.\GPO_GEN.gpo_i_reg[31]_0 (\GPO_GEN.gpo_i_reg[31]_0 ),
.IIC2Bus_IntrEvent(IIC2Bus_IntrEvent),
.\IIC2Bus_IntrEvent_reg[5] (\IIC2Bus_IntrEvent_reg[5] ),
.Q(Q),
.\RD_FIFO_CNTRL.rc_fifo_pirq_i_reg[7] (\RD_FIFO_CNTRL.rc_fifo_pirq_i_reg[7] ),
.Rc_fifo_data(Rc_fifo_data),
.Tx_addr(Tx_addr),
.Tx_fifo_data(Tx_fifo_data),
.\adr_i_reg[0] (\adr_i_reg[0] ),
.\adr_i_reg[1] (\adr_i_reg[1] ),
.\adr_i_reg[2] (\adr_i_reg[2] ),
.\adr_i_reg[3] (\adr_i_reg[3] ),
.\adr_i_reg[4] (\adr_i_reg[4] ),
.\adr_i_reg[5] (\adr_i_reg[5] ),
.\adr_i_reg[6] (\adr_i_reg[6] ),
.\bus2ip_addr_i_reg[2] (\bus2ip_addr_i_reg[2] ),
.\bus2ip_addr_i_reg[2]_0 (\bus2ip_addr_i_reg[2]_0 ),
.\cr_i_reg[4] (\cr_i_reg[4] ),
.\cr_i_reg[4]_0 (\cr_i_reg[4]_0 ),
.cr_txModeSelect_clr(cr_txModeSelect_clr),
.cr_txModeSelect_set(cr_txModeSelect_set),
.gpo(gpo),
.\ip_irpt_enable_reg_reg[7] ({p_0_in16_in,p_0_in13_in,p_0_in10_in,p_0_in7_in,p_0_in4_in,p_0_in1_in,p_0_in,X_INTERRUPT_CONTROL_n_18}),
.ipif_glbl_irpt_enable_reg(ipif_glbl_irpt_enable_reg),
.ipif_glbl_irpt_enable_reg_reg(AXI_LITE_IPIF_I_n_39),
.irpt_wrack(irpt_wrack),
.irpt_wrack_d1(irpt_wrack_d1),
.p_1_in(p_1_in),
.p_1_in11_in(p_1_in11_in),
.p_1_in14_in(p_1_in14_in),
.p_1_in17_in(p_1_in17_in),
.p_1_in2_in(p_1_in2_in),
.p_1_in5_in(p_1_in5_in),
.p_1_in8_in(p_1_in8_in),
.reset_trig0(reset_trig0),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr(s_axi_araddr),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(s_axi_bresp),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(s_axi_rresp),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata({s_axi_wdata[10],s_axi_wdata[7:0]}),
.s_axi_wready(s_axi_wready),
.s_axi_wvalid(s_axi_wvalid),
.\sr_i_reg[2] (\sr_i_reg[2] ),
.\sr_i_reg[4] (\sr_i_reg[4] ),
.\sr_i_reg[5] (\sr_i_reg[5] ),
.sw_rst_cond(sw_rst_cond),
.sw_rst_cond_d1(sw_rst_cond_d1),
.\timing_param_tbuf_i_reg[0] (\timing_param_tbuf_i_reg[0] ),
.\timing_param_tbuf_i_reg[1] (\timing_param_tbuf_i_reg[1] ),
.\timing_param_tbuf_i_reg[2] (\timing_param_tbuf_i_reg[2] ),
.\timing_param_tbuf_i_reg[3] (\timing_param_tbuf_i_reg[3] ),
.\timing_param_tbuf_i_reg[7] (\timing_param_tbuf_i_reg[7] ),
.\timing_param_thddat_i_reg[5] (\timing_param_thddat_i_reg[5] ),
.\timing_param_thdsta_i_reg[0] (\timing_param_thdsta_i_reg[0] ),
.\timing_param_thigh_i_reg[7] (\timing_param_thigh_i_reg[7] ),
.\timing_param_tlow_i_reg[0] (\timing_param_tlow_i_reg[0] ),
.\timing_param_tsudat_i_reg[5] (\timing_param_tsudat_i_reg[5] ),
.\timing_param_tsudat_i_reg[6] (\timing_param_tsudat_i_reg[6] ),
.\timing_param_tsudat_i_reg[7] (\timing_param_tsudat_i_reg[7] ),
.\timing_param_tsusta_i_reg[7] (\timing_param_tsusta_i_reg[7] ),
.\timing_param_tsusto_i_reg[7] (\timing_param_tsusto_i_reg[7] ));
system_axi_iic_0_0_interrupt_control X_INTERRUPT_CONTROL
(.Bus_RNW_reg_reg(AXI_LITE_IPIF_I_n_20),
.Bus_RNW_reg_reg_0(AXI_LITE_IPIF_I_n_19),
.Bus_RNW_reg_reg_1(AXI_LITE_IPIF_I_n_18),
.Bus_RNW_reg_reg_2(AXI_LITE_IPIF_I_n_17),
.Bus_RNW_reg_reg_3(AXI_LITE_IPIF_I_n_16),
.Bus_RNW_reg_reg_4(AXI_LITE_IPIF_I_n_15),
.Bus_RNW_reg_reg_5(AXI_LITE_IPIF_I_n_14),
.Bus_RNW_reg_reg_6(AXI_LITE_IPIF_I_n_13),
.E(AXI_Bus2IP_WrCE),
.\GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg[7] (AXI_LITE_IPIF_I_n_39),
.\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0 (X_INTERRUPT_CONTROL_n_1),
.Q({p_0_in16_in,p_0_in13_in,p_0_in10_in,p_0_in7_in,p_0_in4_in,p_0_in1_in,p_0_in,X_INTERRUPT_CONTROL_n_18}),
.SR(Bus2IIC_Reset),
.iic2intc_irpt(iic2intc_irpt),
.ipif_glbl_irpt_enable_reg(ipif_glbl_irpt_enable_reg),
.irpt_wrack(irpt_wrack),
.irpt_wrack_d1(irpt_wrack_d1),
.p_1_in(p_1_in),
.p_1_in11_in(p_1_in11_in),
.p_1_in14_in(p_1_in14_in),
.p_1_in17_in(p_1_in17_in),
.p_1_in2_in(p_1_in2_in),
.p_1_in5_in(p_1_in5_in),
.p_1_in8_in(p_1_in8_in),
.s_axi_aclk(s_axi_aclk),
.s_axi_wdata(s_axi_wdata[7:0]));
system_axi_iic_0_0_soft_reset X_SOFT_RESET
(.AXI_Bus2IP_Reset(AXI_Bus2IP_Reset),
.SR(Bus2IIC_Reset),
.Tx_fifo_rst(Tx_fifo_rst),
.ctrlFifoDin(ctrlFifoDin),
.reset_trig0(reset_trig0),
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_wdata(s_axi_wdata[9:8]),
.sw_rst_cond(sw_rst_cond),
.sw_rst_cond_d1(sw_rst_cond_d1));
endmodule
(* ORIG_REF_NAME = "axi_lite_ipif" *)
module system_axi_iic_0_0_axi_lite_ipif
(s_axi_rresp,
s_axi_rvalid,
s_axi_bvalid,
s_axi_bresp,
Q,
AXI_IP2Bus_WrAck2_reg,
s_axi_wready,
s_axi_arready,
irpt_wrack,
\GEN_IP_IRPT_STATUS_REG[7].GEN_REG_STATUS.ip_irpt_status_reg_reg[7] ,
\GEN_IP_IRPT_STATUS_REG[6].GEN_REG_STATUS.ip_irpt_status_reg_reg[6] ,
\GEN_IP_IRPT_STATUS_REG[5].GEN_REG_STATUS.ip_irpt_status_reg_reg[5] ,
\GEN_IP_IRPT_STATUS_REG[4].GEN_REG_STATUS.ip_irpt_status_reg_reg[4] ,
\GEN_IP_IRPT_STATUS_REG[3].GEN_REG_STATUS.ip_irpt_status_reg_reg[3] ,
\GEN_IP_IRPT_STATUS_REG[2].GEN_REG_STATUS.ip_irpt_status_reg_reg[2] ,
\GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1] ,
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0] ,
reset_trig0,
sw_rst_cond,
Bus2IIC_RdCE,
E,
\cr_i_reg[4] ,
Bus2IIC_WrCE,
AXI_IP2Bus_RdAck20,
ipif_glbl_irpt_enable_reg_reg,
\GPO_GEN.gpo_i_reg[31] ,
s_axi_rdata,
AXI_Bus2IP_Reset,
s_axi_aclk,
\timing_param_tsudat_i_reg[5] ,
\cr_i_reg[4]_0 ,
\timing_param_tlow_i_reg[0] ,
\RD_FIFO_CNTRL.rc_fifo_pirq_i_reg[7] ,
AXI_IP2Bus_RdAck1,
AXI_IP2Bus_RdAck2,
s_axi_aresetn,
s_axi_arvalid,
AXI_IP2Bus_WrAck1,
AXI_IP2Bus_WrAck2,
s_axi_rready,
s_axi_bready,
s_axi_wvalid,
s_axi_awvalid,
s_axi_araddr,
s_axi_awaddr,
s_axi_wdata,
irpt_wrack_d1,
IIC2Bus_IntrEvent,
p_1_in,
p_1_in2_in,
p_1_in5_in,
p_1_in8_in,
p_1_in11_in,
p_1_in14_in,
p_1_in17_in,
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0 ,
sw_rst_cond_d1,
\ip_irpt_enable_reg_reg[7] ,
\timing_param_thdsta_i_reg[0] ,
\adr_i_reg[6] ,
\adr_i_reg[5] ,
\timing_param_tbuf_i_reg[3] ,
\adr_i_reg[4] ,
\adr_i_reg[3] ,
\adr_i_reg[2] ,
\adr_i_reg[1] ,
\timing_param_tsudat_i_reg[6] ,
\adr_i_reg[0] ,
\timing_param_tsudat_i_reg[7] ,
Tx_fifo_data,
\timing_param_tsusta_i_reg[7] ,
\timing_param_tsusto_i_reg[7] ,
Rc_fifo_data,
\timing_param_thigh_i_reg[7] ,
\timing_param_tbuf_i_reg[1] ,
\timing_param_tbuf_i_reg[0] ,
\timing_param_tbuf_i_reg[2] ,
\sr_i_reg[2] ,
\timing_param_thddat_i_reg[5] ,
\timing_param_tbuf_i_reg[7] ,
Tx_addr,
\GPO_GEN.gpo_i_reg[31]_0 ,
\bus2ip_addr_i_reg[2] ,
\bus2ip_addr_i_reg[2]_0 ,
cr_txModeSelect_set,
cr_txModeSelect_clr,
ipif_glbl_irpt_enable_reg,
\sr_i_reg[4] ,
\sr_i_reg[5] ,
\IIC2Bus_IntrEvent_reg[5] ,
gpo);
output [0:0]s_axi_rresp;
output s_axi_rvalid;
output s_axi_bvalid;
output [0:0]s_axi_bresp;
output [4:0]Q;
output AXI_IP2Bus_WrAck2_reg;
output s_axi_wready;
output s_axi_arready;
output irpt_wrack;
output \GEN_IP_IRPT_STATUS_REG[7].GEN_REG_STATUS.ip_irpt_status_reg_reg[7] ;
output \GEN_IP_IRPT_STATUS_REG[6].GEN_REG_STATUS.ip_irpt_status_reg_reg[6] ;
output \GEN_IP_IRPT_STATUS_REG[5].GEN_REG_STATUS.ip_irpt_status_reg_reg[5] ;
output \GEN_IP_IRPT_STATUS_REG[4].GEN_REG_STATUS.ip_irpt_status_reg_reg[4] ;
output \GEN_IP_IRPT_STATUS_REG[3].GEN_REG_STATUS.ip_irpt_status_reg_reg[3] ;
output \GEN_IP_IRPT_STATUS_REG[2].GEN_REG_STATUS.ip_irpt_status_reg_reg[2] ;
output \GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1] ;
output \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0] ;
output reset_trig0;
output sw_rst_cond;
output [0:0]Bus2IIC_RdCE;
output [0:0]E;
output [0:0]\cr_i_reg[4] ;
output [11:0]Bus2IIC_WrCE;
output AXI_IP2Bus_RdAck20;
output ipif_glbl_irpt_enable_reg_reg;
output \GPO_GEN.gpo_i_reg[31] ;
output [10:0]s_axi_rdata;
input AXI_Bus2IP_Reset;
input s_axi_aclk;
input [5:0]\timing_param_tsudat_i_reg[5] ;
input [1:0]\cr_i_reg[4]_0 ;
input [0:0]\timing_param_tlow_i_reg[0] ;
input [0:0]\RD_FIFO_CNTRL.rc_fifo_pirq_i_reg[7] ;
input AXI_IP2Bus_RdAck1;
input AXI_IP2Bus_RdAck2;
input s_axi_aresetn;
input s_axi_arvalid;
input AXI_IP2Bus_WrAck1;
input AXI_IP2Bus_WrAck2;
input s_axi_rready;
input s_axi_bready;
input s_axi_wvalid;
input s_axi_awvalid;
input [8:0]s_axi_araddr;
input [8:0]s_axi_awaddr;
input [8:0]s_axi_wdata;
input irpt_wrack_d1;
input [0:7]IIC2Bus_IntrEvent;
input p_1_in;
input p_1_in2_in;
input p_1_in5_in;
input p_1_in8_in;
input p_1_in11_in;
input p_1_in14_in;
input p_1_in17_in;
input \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0 ;
input sw_rst_cond_d1;
input [7:0]\ip_irpt_enable_reg_reg[7] ;
input [0:0]\timing_param_thdsta_i_reg[0] ;
input \adr_i_reg[6] ;
input \adr_i_reg[5] ;
input \timing_param_tbuf_i_reg[3] ;
input \adr_i_reg[4] ;
input \adr_i_reg[3] ;
input \adr_i_reg[2] ;
input \adr_i_reg[1] ;
input \timing_param_tsudat_i_reg[6] ;
input \adr_i_reg[0] ;
input \timing_param_tsudat_i_reg[7] ;
input [3:0]Tx_fifo_data;
input [3:0]\timing_param_tsusta_i_reg[7] ;
input [7:0]\timing_param_tsusto_i_reg[7] ;
input [0:7]Rc_fifo_data;
input [7:0]\timing_param_thigh_i_reg[7] ;
input \timing_param_tbuf_i_reg[1] ;
input \timing_param_tbuf_i_reg[0] ;
input \timing_param_tbuf_i_reg[2] ;
input [1:0]\sr_i_reg[2] ;
input [1:0]\timing_param_thddat_i_reg[5] ;
input [3:0]\timing_param_tbuf_i_reg[7] ;
input [0:3]Tx_addr;
input \GPO_GEN.gpo_i_reg[31]_0 ;
input \bus2ip_addr_i_reg[2] ;
input \bus2ip_addr_i_reg[2]_0 ;
input cr_txModeSelect_set;
input cr_txModeSelect_clr;
input ipif_glbl_irpt_enable_reg;
input \sr_i_reg[4] ;
input \sr_i_reg[5] ;
input \IIC2Bus_IntrEvent_reg[5] ;
input [0:0]gpo;
wire AXI_Bus2IP_Reset;
wire AXI_IP2Bus_RdAck1;
wire AXI_IP2Bus_RdAck2;
wire AXI_IP2Bus_RdAck20;
wire AXI_IP2Bus_WrAck1;
wire AXI_IP2Bus_WrAck2;
wire AXI_IP2Bus_WrAck2_reg;
wire [0:0]Bus2IIC_RdCE;
wire [11:0]Bus2IIC_WrCE;
wire [0:0]E;
wire \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0] ;
wire \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0 ;
wire \GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1] ;
wire \GEN_IP_IRPT_STATUS_REG[2].GEN_REG_STATUS.ip_irpt_status_reg_reg[2] ;
wire \GEN_IP_IRPT_STATUS_REG[3].GEN_REG_STATUS.ip_irpt_status_reg_reg[3] ;
wire \GEN_IP_IRPT_STATUS_REG[4].GEN_REG_STATUS.ip_irpt_status_reg_reg[4] ;
wire \GEN_IP_IRPT_STATUS_REG[5].GEN_REG_STATUS.ip_irpt_status_reg_reg[5] ;
wire \GEN_IP_IRPT_STATUS_REG[6].GEN_REG_STATUS.ip_irpt_status_reg_reg[6] ;
wire \GEN_IP_IRPT_STATUS_REG[7].GEN_REG_STATUS.ip_irpt_status_reg_reg[7] ;
wire \GPO_GEN.gpo_i_reg[31] ;
wire \GPO_GEN.gpo_i_reg[31]_0 ;
wire [0:7]IIC2Bus_IntrEvent;
wire \IIC2Bus_IntrEvent_reg[5] ;
wire [4:0]Q;
wire [0:0]\RD_FIFO_CNTRL.rc_fifo_pirq_i_reg[7] ;
wire [0:7]Rc_fifo_data;
wire [0:3]Tx_addr;
wire [3:0]Tx_fifo_data;
wire \adr_i_reg[0] ;
wire \adr_i_reg[1] ;
wire \adr_i_reg[2] ;
wire \adr_i_reg[3] ;
wire \adr_i_reg[4] ;
wire \adr_i_reg[5] ;
wire \adr_i_reg[6] ;
wire \bus2ip_addr_i_reg[2] ;
wire \bus2ip_addr_i_reg[2]_0 ;
wire [0:0]\cr_i_reg[4] ;
wire [1:0]\cr_i_reg[4]_0 ;
wire cr_txModeSelect_clr;
wire cr_txModeSelect_set;
wire [0:0]gpo;
wire [7:0]\ip_irpt_enable_reg_reg[7] ;
wire ipif_glbl_irpt_enable_reg;
wire ipif_glbl_irpt_enable_reg_reg;
wire irpt_wrack;
wire irpt_wrack_d1;
wire p_1_in;
wire p_1_in11_in;
wire p_1_in14_in;
wire p_1_in17_in;
wire p_1_in2_in;
wire p_1_in5_in;
wire p_1_in8_in;
wire reset_trig0;
wire s_axi_aclk;
wire [8:0]s_axi_araddr;
wire s_axi_aresetn;
wire s_axi_arready;
wire s_axi_arvalid;
wire [8:0]s_axi_awaddr;
wire s_axi_awvalid;
wire s_axi_bready;
wire [0:0]s_axi_bresp;
wire s_axi_bvalid;
wire [10:0]s_axi_rdata;
wire s_axi_rready;
wire [0:0]s_axi_rresp;
wire s_axi_rvalid;
wire [8:0]s_axi_wdata;
wire s_axi_wready;
wire s_axi_wvalid;
wire [1:0]\sr_i_reg[2] ;
wire \sr_i_reg[4] ;
wire \sr_i_reg[5] ;
wire sw_rst_cond;
wire sw_rst_cond_d1;
wire \timing_param_tbuf_i_reg[0] ;
wire \timing_param_tbuf_i_reg[1] ;
wire \timing_param_tbuf_i_reg[2] ;
wire \timing_param_tbuf_i_reg[3] ;
wire [3:0]\timing_param_tbuf_i_reg[7] ;
wire [1:0]\timing_param_thddat_i_reg[5] ;
wire [0:0]\timing_param_thdsta_i_reg[0] ;
wire [7:0]\timing_param_thigh_i_reg[7] ;
wire [0:0]\timing_param_tlow_i_reg[0] ;
wire [5:0]\timing_param_tsudat_i_reg[5] ;
wire \timing_param_tsudat_i_reg[6] ;
wire \timing_param_tsudat_i_reg[7] ;
wire [3:0]\timing_param_tsusta_i_reg[7] ;
wire [7:0]\timing_param_tsusto_i_reg[7] ;
system_axi_iic_0_0_slave_attachment I_SLAVE_ATTACHMENT
(.AXI_Bus2IP_Reset(AXI_Bus2IP_Reset),
.AXI_IP2Bus_RdAck1(AXI_IP2Bus_RdAck1),
.AXI_IP2Bus_RdAck2(AXI_IP2Bus_RdAck2),
.AXI_IP2Bus_RdAck20(AXI_IP2Bus_RdAck20),
.AXI_IP2Bus_WrAck1(AXI_IP2Bus_WrAck1),
.AXI_IP2Bus_WrAck2(AXI_IP2Bus_WrAck2),
.AXI_IP2Bus_WrAck2_reg(AXI_IP2Bus_WrAck2_reg),
.Bus2IIC_RdCE(Bus2IIC_RdCE),
.Bus2IIC_WrCE(Bus2IIC_WrCE),
.E(E),
.\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0] (\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0] ),
.\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0 (\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0 ),
.\GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1] (\GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1] ),
.\GEN_IP_IRPT_STATUS_REG[2].GEN_REG_STATUS.ip_irpt_status_reg_reg[2] (\GEN_IP_IRPT_STATUS_REG[2].GEN_REG_STATUS.ip_irpt_status_reg_reg[2] ),
.\GEN_IP_IRPT_STATUS_REG[3].GEN_REG_STATUS.ip_irpt_status_reg_reg[3] (\GEN_IP_IRPT_STATUS_REG[3].GEN_REG_STATUS.ip_irpt_status_reg_reg[3] ),
.\GEN_IP_IRPT_STATUS_REG[4].GEN_REG_STATUS.ip_irpt_status_reg_reg[4] (\GEN_IP_IRPT_STATUS_REG[4].GEN_REG_STATUS.ip_irpt_status_reg_reg[4] ),
.\GEN_IP_IRPT_STATUS_REG[5].GEN_REG_STATUS.ip_irpt_status_reg_reg[5] (\GEN_IP_IRPT_STATUS_REG[5].GEN_REG_STATUS.ip_irpt_status_reg_reg[5] ),
.\GEN_IP_IRPT_STATUS_REG[6].GEN_REG_STATUS.ip_irpt_status_reg_reg[6] (\GEN_IP_IRPT_STATUS_REG[6].GEN_REG_STATUS.ip_irpt_status_reg_reg[6] ),
.\GEN_IP_IRPT_STATUS_REG[7].GEN_REG_STATUS.ip_irpt_status_reg_reg[7] (\GEN_IP_IRPT_STATUS_REG[7].GEN_REG_STATUS.ip_irpt_status_reg_reg[7] ),
.\GPO_GEN.gpo_i_reg[31] (\GPO_GEN.gpo_i_reg[31] ),
.\GPO_GEN.gpo_i_reg[31]_0 (\GPO_GEN.gpo_i_reg[31]_0 ),
.IIC2Bus_IntrEvent(IIC2Bus_IntrEvent),
.\IIC2Bus_IntrEvent_reg[5] (\IIC2Bus_IntrEvent_reg[5] ),
.Q(Q),
.\RD_FIFO_CNTRL.rc_fifo_pirq_i_reg[7] (\RD_FIFO_CNTRL.rc_fifo_pirq_i_reg[7] ),
.Rc_fifo_data(Rc_fifo_data),
.Tx_addr(Tx_addr),
.Tx_fifo_data(Tx_fifo_data),
.\adr_i_reg[0] (\adr_i_reg[0] ),
.\adr_i_reg[1] (\adr_i_reg[1] ),
.\adr_i_reg[2] (\adr_i_reg[2] ),
.\adr_i_reg[3] (\adr_i_reg[3] ),
.\adr_i_reg[4] (\adr_i_reg[4] ),
.\adr_i_reg[5] (\adr_i_reg[5] ),
.\adr_i_reg[6] (\adr_i_reg[6] ),
.\bus2ip_addr_i_reg[2]_0 (\bus2ip_addr_i_reg[2] ),
.\bus2ip_addr_i_reg[2]_1 (\bus2ip_addr_i_reg[2]_0 ),
.\cr_i_reg[4] (\cr_i_reg[4] ),
.\cr_i_reg[4]_0 (\cr_i_reg[4]_0 ),
.cr_txModeSelect_clr(cr_txModeSelect_clr),
.cr_txModeSelect_set(cr_txModeSelect_set),
.gpo(gpo),
.\ip_irpt_enable_reg_reg[7] (\ip_irpt_enable_reg_reg[7] ),
.ipif_glbl_irpt_enable_reg(ipif_glbl_irpt_enable_reg),
.ipif_glbl_irpt_enable_reg_reg(ipif_glbl_irpt_enable_reg_reg),
.irpt_wrack(irpt_wrack),
.irpt_wrack_d1(irpt_wrack_d1),
.p_1_in(p_1_in),
.p_1_in11_in(p_1_in11_in),
.p_1_in14_in(p_1_in14_in),
.p_1_in17_in(p_1_in17_in),
.p_1_in2_in(p_1_in2_in),
.p_1_in5_in(p_1_in5_in),
.p_1_in8_in(p_1_in8_in),
.reset_trig0(reset_trig0),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr(s_axi_araddr),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(s_axi_bresp),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(s_axi_rresp),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wready(s_axi_wready),
.s_axi_wvalid(s_axi_wvalid),
.\sr_i_reg[2] (\sr_i_reg[2] ),
.\sr_i_reg[4] (\sr_i_reg[4] ),
.\sr_i_reg[5] (\sr_i_reg[5] ),
.sw_rst_cond(sw_rst_cond),
.sw_rst_cond_d1(sw_rst_cond_d1),
.\timing_param_tbuf_i_reg[0] (\timing_param_tbuf_i_reg[0] ),
.\timing_param_tbuf_i_reg[1] (\timing_param_tbuf_i_reg[1] ),
.\timing_param_tbuf_i_reg[2] (\timing_param_tbuf_i_reg[2] ),
.\timing_param_tbuf_i_reg[3] (\timing_param_tbuf_i_reg[3] ),
.\timing_param_tbuf_i_reg[7] (\timing_param_tbuf_i_reg[7] ),
.\timing_param_thddat_i_reg[5] (\timing_param_thddat_i_reg[5] ),
.\timing_param_thdsta_i_reg[0] (\timing_param_thdsta_i_reg[0] ),
.\timing_param_thigh_i_reg[7] (\timing_param_thigh_i_reg[7] ),
.\timing_param_tlow_i_reg[0] (\timing_param_tlow_i_reg[0] ),
.\timing_param_tsudat_i_reg[5] (\timing_param_tsudat_i_reg[5] ),
.\timing_param_tsudat_i_reg[6] (\timing_param_tsudat_i_reg[6] ),
.\timing_param_tsudat_i_reg[7] (\timing_param_tsudat_i_reg[7] ),
.\timing_param_tsusta_i_reg[7] (\timing_param_tsusta_i_reg[7] ),
.\timing_param_tsusto_i_reg[7] (\timing_param_tsusto_i_reg[7] ));
endmodule
(* ORIG_REF_NAME = "cdc_sync" *)
module system_axi_iic_0_0_cdc_sync
(detect_stop_b_reg,
scndry_out,
sda_rin_d1,
sda_i,
s_axi_aclk);
output detect_stop_b_reg;
output scndry_out;
input sda_rin_d1;
input sda_i;
input s_axi_aclk;
wire detect_stop_b_reg;
wire s_axi_aclk;
wire s_level_out_d1_cdc_to;
wire s_level_out_d2;
wire s_level_out_d3;
wire scndry_out;
wire sda_i;
wire sda_rin_d1;
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(sda_i),
.Q(s_level_out_d1_cdc_to),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_d1_cdc_to),
.Q(s_level_out_d2),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_d2),
.Q(s_level_out_d3),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_d3),
.Q(scndry_out),
.R(1'b0));
LUT2 #(
.INIT(4'h2))
detect_stop_b_i_2
(.I0(scndry_out),
.I1(sda_rin_d1),
.O(detect_stop_b_reg));
endmodule
(* ORIG_REF_NAME = "cdc_sync" *)
module system_axi_iic_0_0_cdc_sync_4
(scl_rising_edge0,
scl_rin_d1_reg,
scl_rin_d1,
scl_i,
s_axi_aclk);
output scl_rising_edge0;
output scl_rin_d1_reg;
input scl_rin_d1;
input scl_i;
input s_axi_aclk;
wire s_axi_aclk;
wire s_level_out_d1_cdc_to;
wire s_level_out_d2;
wire s_level_out_d3;
wire scl_i;
wire scl_rin_d1;
wire scl_rin_d1_reg;
wire scl_rising_edge0;
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(scl_i),
.Q(s_level_out_d1_cdc_to),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_d1_cdc_to),
.Q(s_level_out_d2),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_d2),
.Q(s_level_out_d3),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_d3),
.Q(scl_rin_d1_reg),
.R(1'b0));
LUT2 #(
.INIT(4'h2))
scl_rising_edge_i_1
(.I0(scl_rin_d1_reg),
.I1(scl_rin_d1),
.O(scl_rising_edge0));
endmodule
(* ORIG_REF_NAME = "debounce" *)
module system_axi_iic_0_0_debounce
(scl_rising_edge0,
scl_rin_d1_reg,
scl_rin_d1,
scl_i,
s_axi_aclk);
output scl_rising_edge0;
output scl_rin_d1_reg;
input scl_rin_d1;
input scl_i;
input s_axi_aclk;
wire s_axi_aclk;
wire scl_i;
wire scl_rin_d1;
wire scl_rin_d1_reg;
wire scl_rising_edge0;
system_axi_iic_0_0_cdc_sync_4 INPUT_DOUBLE_REGS
(.s_axi_aclk(s_axi_aclk),
.scl_i(scl_i),
.scl_rin_d1(scl_rin_d1),
.scl_rin_d1_reg(scl_rin_d1_reg),
.scl_rising_edge0(scl_rising_edge0));
endmodule
(* ORIG_REF_NAME = "debounce" *)
module system_axi_iic_0_0_debounce_3
(detect_stop_b_reg,
scndry_out,
sda_rin_d1,
sda_i,
s_axi_aclk);
output detect_stop_b_reg;
output scndry_out;
input sda_rin_d1;
input sda_i;
input s_axi_aclk;
wire detect_stop_b_reg;
wire s_axi_aclk;
wire scndry_out;
wire sda_i;
wire sda_rin_d1;
system_axi_iic_0_0_cdc_sync INPUT_DOUBLE_REGS
(.detect_stop_b_reg(detect_stop_b_reg),
.s_axi_aclk(s_axi_aclk),
.scndry_out(scndry_out),
.sda_i(sda_i),
.sda_rin_d1(sda_rin_d1));
endmodule
(* ORIG_REF_NAME = "dynamic_master" *)
module system_axi_iic_0_0_dynamic_master
(callingReadAccess,
rdCntrFrmTxFifo,
rxCntDone,
firstDynStartSeen,
cr_txModeSelect_set,
cr_txModeSelect_clr,
rxCntDone_reg_0,
Tx_fifo_rst,
ackDataState,
s_axi_aclk,
p_3_in,
Tx_fifo_data,
rdCntrFrmTxFifo0,
earlyAckDataState,
firstDynStartSeen_reg_0,
earlyAckHdr);
output callingReadAccess;
output rdCntrFrmTxFifo;
output rxCntDone;
output firstDynStartSeen;
output cr_txModeSelect_set;
output cr_txModeSelect_clr;
output rxCntDone_reg_0;
input Tx_fifo_rst;
input ackDataState;
input s_axi_aclk;
input p_3_in;
input [0:7]Tx_fifo_data;
input rdCntrFrmTxFifo0;
input earlyAckDataState;
input firstDynStartSeen_reg_0;
input earlyAckHdr;
wire Cr_txModeSelect_clr_i_1_n_0;
wire Cr_txModeSelect_set_i_1_n_0;
wire [0:7]Tx_fifo_data;
wire Tx_fifo_rst;
wire ackDataState;
wire ackDataState_d1;
wire callingReadAccess;
wire cr_txModeSelect_clr;
wire cr_txModeSelect_set;
wire earlyAckDataState;
wire earlyAckDataState_d1;
wire earlyAckHdr;
wire firstDynStartSeen;
wire firstDynStartSeen_reg_0;
wire [7:0]p_0_in__2;
wire p_3_in;
wire \rdByteCntr[0]_i_1_n_0 ;
wire \rdByteCntr[0]_i_3_n_0 ;
wire \rdByteCntr[0]_i_4_n_0 ;
wire \rdByteCntr[0]_i_5_n_0 ;
wire \rdByteCntr[2]_i_2_n_0 ;
wire [0:7]rdByteCntr_reg__0;
wire rdCntrFrmTxFifo;
wire rdCntrFrmTxFifo0;
wire rxCntDone;
wire rxCntDone0;
wire rxCntDone_reg_0;
wire s_axi_aclk;
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'h0080))
Cr_txModeSelect_clr_i_1
(.I0(callingReadAccess),
.I1(firstDynStartSeen),
.I2(earlyAckHdr),
.I3(Tx_fifo_rst),
.O(Cr_txModeSelect_clr_i_1_n_0));
FDRE Cr_txModeSelect_clr_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(Cr_txModeSelect_clr_i_1_n_0),
.Q(cr_txModeSelect_clr),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'h0040))
Cr_txModeSelect_set_i_1
(.I0(callingReadAccess),
.I1(firstDynStartSeen),
.I2(earlyAckHdr),
.I3(Tx_fifo_rst),
.O(Cr_txModeSelect_set_i_1_n_0));
FDRE Cr_txModeSelect_set_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(Cr_txModeSelect_set_i_1_n_0),
.Q(cr_txModeSelect_set),
.R(1'b0));
FDRE ackDataState_d1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(ackDataState),
.Q(ackDataState_d1),
.R(Tx_fifo_rst));
FDRE callingReadAccess_reg
(.C(s_axi_aclk),
.CE(p_3_in),
.D(Tx_fifo_data[7]),
.Q(callingReadAccess),
.R(Tx_fifo_rst));
FDRE earlyAckDataState_d1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(earlyAckDataState),
.Q(earlyAckDataState_d1),
.R(Tx_fifo_rst));
FDRE firstDynStartSeen_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(firstDynStartSeen_reg_0),
.Q(firstDynStartSeen),
.R(1'b0));
LUT5 #(
.INIT(32'hAABABABA))
\rdByteCntr[0]_i_1
(.I0(rdCntrFrmTxFifo),
.I1(earlyAckDataState_d1),
.I2(earlyAckDataState),
.I3(\rdByteCntr[0]_i_3_n_0 ),
.I4(\rdByteCntr[0]_i_4_n_0 ),
.O(\rdByteCntr[0]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8B8B88B))
\rdByteCntr[0]_i_2
(.I0(Tx_fifo_data[0]),
.I1(rdCntrFrmTxFifo),
.I2(rdByteCntr_reg__0[0]),
.I3(\rdByteCntr[0]_i_5_n_0 ),
.I4(rdByteCntr_reg__0[1]),
.O(p_0_in__2[7]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT4 #(
.INIT(16'h0001))
\rdByteCntr[0]_i_3
(.I0(rdByteCntr_reg__0[4]),
.I1(rdByteCntr_reg__0[5]),
.I2(rdByteCntr_reg__0[6]),
.I3(rdByteCntr_reg__0[7]),
.O(\rdByteCntr[0]_i_3_n_0 ));
LUT4 #(
.INIT(16'h0001))
\rdByteCntr[0]_i_4
(.I0(rdByteCntr_reg__0[0]),
.I1(rdByteCntr_reg__0[1]),
.I2(rdByteCntr_reg__0[2]),
.I3(rdByteCntr_reg__0[3]),
.O(\rdByteCntr[0]_i_4_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\rdByteCntr[0]_i_5
(.I0(rdByteCntr_reg__0[2]),
.I1(rdByteCntr_reg__0[3]),
.I2(rdByteCntr_reg__0[7]),
.I3(rdByteCntr_reg__0[6]),
.I4(rdByteCntr_reg__0[5]),
.I5(rdByteCntr_reg__0[4]),
.O(\rdByteCntr[0]_i_5_n_0 ));
LUT6 #(
.INIT(64'hBBB8BBBB888B8888))
\rdByteCntr[1]_i_1
(.I0(Tx_fifo_data[1]),
.I1(rdCntrFrmTxFifo),
.I2(rdByteCntr_reg__0[2]),
.I3(rdByteCntr_reg__0[3]),
.I4(\rdByteCntr[0]_i_3_n_0 ),
.I5(rdByteCntr_reg__0[1]),
.O(p_0_in__2[6]));
LUT5 #(
.INIT(32'hB8B88BB8))
\rdByteCntr[2]_i_1
(.I0(Tx_fifo_data[2]),
.I1(rdCntrFrmTxFifo),
.I2(rdByteCntr_reg__0[2]),
.I3(\rdByteCntr[2]_i_2_n_0 ),
.I4(rdByteCntr_reg__0[7]),
.O(p_0_in__2[5]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT4 #(
.INIT(16'h0001))
\rdByteCntr[2]_i_2
(.I0(rdByteCntr_reg__0[4]),
.I1(rdByteCntr_reg__0[5]),
.I2(rdByteCntr_reg__0[3]),
.I3(rdByteCntr_reg__0[6]),
.O(\rdByteCntr[2]_i_2_n_0 ));
LUT4 #(
.INIT(16'h8BB8))
\rdByteCntr[3]_i_1
(.I0(Tx_fifo_data[3]),
.I1(rdCntrFrmTxFifo),
.I2(rdByteCntr_reg__0[3]),
.I3(\rdByteCntr[0]_i_3_n_0 ),
.O(p_0_in__2[4]));
LUT6 #(
.INIT(64'hBBBBBBB88888888B))
\rdByteCntr[4]_i_1
(.I0(Tx_fifo_data[4]),
.I1(rdCntrFrmTxFifo),
.I2(rdByteCntr_reg__0[5]),
.I3(rdByteCntr_reg__0[6]),
.I4(rdByteCntr_reg__0[7]),
.I5(rdByteCntr_reg__0[4]),
.O(p_0_in__2[3]));
LUT5 #(
.INIT(32'hBBB8888B))
\rdByteCntr[5]_i_1
(.I0(Tx_fifo_data[5]),
.I1(rdCntrFrmTxFifo),
.I2(rdByteCntr_reg__0[7]),
.I3(rdByteCntr_reg__0[6]),
.I4(rdByteCntr_reg__0[5]),
.O(p_0_in__2[2]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT4 #(
.INIT(16'hB88B))
\rdByteCntr[6]_i_1
(.I0(Tx_fifo_data[6]),
.I1(rdCntrFrmTxFifo),
.I2(rdByteCntr_reg__0[7]),
.I3(rdByteCntr_reg__0[6]),
.O(p_0_in__2[1]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT3 #(
.INIT(8'h8B))
\rdByteCntr[7]_i_1
(.I0(Tx_fifo_data[7]),
.I1(rdCntrFrmTxFifo),
.I2(rdByteCntr_reg__0[7]),
.O(p_0_in__2[0]));
FDRE \rdByteCntr_reg[0]
(.C(s_axi_aclk),
.CE(\rdByteCntr[0]_i_1_n_0 ),
.D(p_0_in__2[7]),
.Q(rdByteCntr_reg__0[0]),
.R(Tx_fifo_rst));
FDRE \rdByteCntr_reg[1]
(.C(s_axi_aclk),
.CE(\rdByteCntr[0]_i_1_n_0 ),
.D(p_0_in__2[6]),
.Q(rdByteCntr_reg__0[1]),
.R(Tx_fifo_rst));
FDRE \rdByteCntr_reg[2]
(.C(s_axi_aclk),
.CE(\rdByteCntr[0]_i_1_n_0 ),
.D(p_0_in__2[5]),
.Q(rdByteCntr_reg__0[2]),
.R(Tx_fifo_rst));
FDRE \rdByteCntr_reg[3]
(.C(s_axi_aclk),
.CE(\rdByteCntr[0]_i_1_n_0 ),
.D(p_0_in__2[4]),
.Q(rdByteCntr_reg__0[3]),
.R(Tx_fifo_rst));
FDRE \rdByteCntr_reg[4]
(.C(s_axi_aclk),
.CE(\rdByteCntr[0]_i_1_n_0 ),
.D(p_0_in__2[3]),
.Q(rdByteCntr_reg__0[4]),
.R(Tx_fifo_rst));
FDRE \rdByteCntr_reg[5]
(.C(s_axi_aclk),
.CE(\rdByteCntr[0]_i_1_n_0 ),
.D(p_0_in__2[2]),
.Q(rdByteCntr_reg__0[5]),
.R(Tx_fifo_rst));
FDRE \rdByteCntr_reg[6]
(.C(s_axi_aclk),
.CE(\rdByteCntr[0]_i_1_n_0 ),
.D(p_0_in__2[1]),
.Q(rdByteCntr_reg__0[6]),
.R(Tx_fifo_rst));
FDRE \rdByteCntr_reg[7]
(.C(s_axi_aclk),
.CE(\rdByteCntr[0]_i_1_n_0 ),
.D(p_0_in__2[0]),
.Q(rdByteCntr_reg__0[7]),
.R(Tx_fifo_rst));
FDRE rdCntrFrmTxFifo_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(rdCntrFrmTxFifo0),
.Q(rdCntrFrmTxFifo),
.R(Tx_fifo_rst));
LUT3 #(
.INIT(8'h08))
rxCntDone_i_1
(.I0(rxCntDone_reg_0),
.I1(ackDataState),
.I2(ackDataState_d1),
.O(rxCntDone0));
LUT6 #(
.INIT(64'h0000000000000020))
rxCntDone_i_2
(.I0(\rdByteCntr[2]_i_2_n_0 ),
.I1(rdByteCntr_reg__0[2]),
.I2(callingReadAccess),
.I3(rdByteCntr_reg__0[7]),
.I4(rdByteCntr_reg__0[1]),
.I5(rdByteCntr_reg__0[0]),
.O(rxCntDone_reg_0));
FDRE rxCntDone_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(rxCntDone0),
.Q(rxCntDone),
.R(Tx_fifo_rst));
endmodule
(* ORIG_REF_NAME = "filter" *)
module system_axi_iic_0_0_filter
(detect_stop_b_reg,
scndry_out,
scl_rising_edge0,
scl_rin_d1_reg,
sda_rin_d1,
scl_rin_d1,
scl_i,
s_axi_aclk,
sda_i);
output detect_stop_b_reg;
output scndry_out;
output scl_rising_edge0;
output scl_rin_d1_reg;
input sda_rin_d1;
input scl_rin_d1;
input scl_i;
input s_axi_aclk;
input sda_i;
wire detect_stop_b_reg;
wire s_axi_aclk;
wire scl_i;
wire scl_rin_d1;
wire scl_rin_d1_reg;
wire scl_rising_edge0;
wire scndry_out;
wire sda_i;
wire sda_rin_d1;
system_axi_iic_0_0_debounce SCL_DEBOUNCE
(.s_axi_aclk(s_axi_aclk),
.scl_i(scl_i),
.scl_rin_d1(scl_rin_d1),
.scl_rin_d1_reg(scl_rin_d1_reg),
.scl_rising_edge0(scl_rising_edge0));
system_axi_iic_0_0_debounce_3 SDA_DEBOUNCE
(.detect_stop_b_reg(detect_stop_b_reg),
.s_axi_aclk(s_axi_aclk),
.scndry_out(scndry_out),
.sda_i(sda_i),
.sda_rin_d1(sda_rin_d1));
endmodule
(* ORIG_REF_NAME = "iic" *)
module system_axi_iic_0_0_iic
(s_axi_wready,
s_axi_rdata,
s_axi_rresp,
s_axi_arready,
s_axi_rvalid,
s_axi_bvalid,
sda_t,
gpo,
iic2intc_irpt,
scl_t,
s_axi_bresp,
s_axi_aresetn,
scl_i,
s_axi_aclk,
sda_i,
s_axi_wdata,
s_axi_wvalid,
s_axi_awvalid,
s_axi_arvalid,
s_axi_rready,
s_axi_bready,
s_axi_araddr,
s_axi_awaddr);
output s_axi_wready;
output [10:0]s_axi_rdata;
output [0:0]s_axi_rresp;
output s_axi_arready;
output s_axi_rvalid;
output s_axi_bvalid;
output sda_t;
output [0:0]gpo;
output iic2intc_irpt;
output scl_t;
output [0:0]s_axi_bresp;
input s_axi_aresetn;
input scl_i;
input s_axi_aclk;
input sda_i;
input [10:0]s_axi_wdata;
input s_axi_wvalid;
input s_axi_awvalid;
input s_axi_arvalid;
input s_axi_rready;
input s_axi_bready;
input [8:0]s_axi_araddr;
input [8:0]s_axi_awaddr;
wire Aas;
wire Abgc;
wire Al;
wire Bb;
wire [2:6]Bus2IIC_Addr;
wire [3:3]Bus2IIC_RdCE;
wire Bus2IIC_Reset;
wire [0:17]Bus2IIC_WrCE;
wire [0:9]\CLKCNT/q_int_reg__0 ;
wire [1:7]Cr;
wire D;
wire DYN_MASTER_I_n_6;
wire D_0;
wire D_1;
wire [0:7]Data_i2c;
wire FILTER_I_n_0;
wire [0:7]IIC2Bus_IntrEvent;
wire IIC_CONTROL_I_n_40;
wire IIC_CONTROL_I_n_50;
wire IIC_CONTROL_I_n_53;
wire IIC_CONTROL_I_n_62;
wire IIC_CONTROL_I_n_8;
wire Msms_set;
wire New_rcv_dta;
wire READ_FIFO_I_n_16;
wire REG_INTERFACE_I_n_101;
wire REG_INTERFACE_I_n_102;
wire REG_INTERFACE_I_n_103;
wire REG_INTERFACE_I_n_104;
wire REG_INTERFACE_I_n_105;
wire REG_INTERFACE_I_n_106;
wire REG_INTERFACE_I_n_107;
wire REG_INTERFACE_I_n_108;
wire REG_INTERFACE_I_n_109;
wire REG_INTERFACE_I_n_110;
wire REG_INTERFACE_I_n_111;
wire REG_INTERFACE_I_n_112;
wire REG_INTERFACE_I_n_113;
wire REG_INTERFACE_I_n_114;
wire REG_INTERFACE_I_n_118;
wire REG_INTERFACE_I_n_119;
wire REG_INTERFACE_I_n_120;
wire REG_INTERFACE_I_n_121;
wire REG_INTERFACE_I_n_122;
wire REG_INTERFACE_I_n_123;
wire REG_INTERFACE_I_n_124;
wire REG_INTERFACE_I_n_125;
wire REG_INTERFACE_I_n_126;
wire REG_INTERFACE_I_n_127;
wire REG_INTERFACE_I_n_128;
wire REG_INTERFACE_I_n_130;
wire REG_INTERFACE_I_n_131;
wire REG_INTERFACE_I_n_132;
wire REG_INTERFACE_I_n_26;
wire REG_INTERFACE_I_n_27;
wire REG_INTERFACE_I_n_28;
wire REG_INTERFACE_I_n_29;
wire REG_INTERFACE_I_n_30;
wire REG_INTERFACE_I_n_39;
wire REG_INTERFACE_I_n_40;
wire REG_INTERFACE_I_n_41;
wire REG_INTERFACE_I_n_42;
wire REG_INTERFACE_I_n_51;
wire REG_INTERFACE_I_n_52;
wire REG_INTERFACE_I_n_53;
wire REG_INTERFACE_I_n_54;
wire REG_INTERFACE_I_n_59;
wire REG_INTERFACE_I_n_60;
wire REG_INTERFACE_I_n_61;
wire REG_INTERFACE_I_n_62;
wire REG_INTERFACE_I_n_67;
wire REG_INTERFACE_I_n_68;
wire REG_INTERFACE_I_n_69;
wire REG_INTERFACE_I_n_70;
wire REG_INTERFACE_I_n_73;
wire REG_INTERFACE_I_n_74;
wire REG_INTERFACE_I_n_75;
wire REG_INTERFACE_I_n_76;
wire REG_INTERFACE_I_n_78;
wire REG_INTERFACE_I_n_79;
wire REG_INTERFACE_I_n_80;
wire REG_INTERFACE_I_n_81;
wire REG_INTERFACE_I_n_83;
wire REG_INTERFACE_I_n_84;
wire REG_INTERFACE_I_n_85;
wire REG_INTERFACE_I_n_95;
wire REG_INTERFACE_I_n_97;
wire REG_INTERFACE_I_n_98;
wire Rc_Data_Exists;
wire [0:3]Rc_addr;
wire [0:7]Rc_fifo_data;
wire Rc_fifo_full;
wire Rc_fifo_rd;
wire Rc_fifo_rd_d;
wire Rc_fifo_wr;
wire Rc_fifo_wr_d;
wire Ro_prev;
wire [0:9]\SETUP_CNT/q_int_reg__0 ;
wire Srw;
wire [0:3]Tx_addr;
wire Tx_data_exists;
wire [0:7]Tx_fifo_data;
wire Tx_fifo_full;
wire Tx_fifo_rd;
wire Tx_fifo_rd_d;
wire Tx_fifo_rst;
wire Tx_fifo_wr;
wire Tx_fifo_wr_d;
wire Tx_under_prev;
wire Txer;
wire WRITE_FIFO_CTRL_I_n_0;
wire WRITE_FIFO_CTRL_I_n_3;
wire WRITE_FIFO_I_n_15;
wire WRITE_FIFO_I_n_16;
wire WRITE_FIFO_I_n_17;
wire WRITE_FIFO_I_n_18;
wire WRITE_FIFO_I_n_19;
wire X_AXI_IPIF_SSP1_n_15;
wire X_AXI_IPIF_SSP1_n_29;
wire ackDataState;
wire arb_lost;
wire callingReadAccess;
wire clk_cnt_en1;
wire clk_cnt_en11_out;
wire clk_cnt_en12_out;
wire cr_txModeSelect_clr;
wire cr_txModeSelect_set;
wire [0:1]ctrlFifoDin;
wire [0:1]dynamic_MSMS;
wire earlyAckDataState;
wire earlyAckHdr;
wire firstDynStartSeen;
wire [0:0]gpo;
wire [7:0]i2c_header;
wire iic2intc_irpt;
wire master_slave;
wire new_rcv_dta_d1;
wire [0:0]p_0_out;
wire p_1_in;
wire p_1_in4_in;
wire p_1_in6_in;
wire [6:6]p_1_out;
wire p_3_in;
wire p_6_out;
wire rdCntrFrmTxFifo;
wire rdCntrFrmTxFifo0;
wire rdy_new_xmt_i;
wire rxCntDone;
wire s_axi_aclk;
wire [8:0]s_axi_araddr;
wire s_axi_aresetn;
wire s_axi_arready;
wire s_axi_arvalid;
wire [8:0]s_axi_awaddr;
wire s_axi_awvalid;
wire s_axi_bready;
wire [0:0]s_axi_bresp;
wire s_axi_bvalid;
wire [10:0]s_axi_rdata;
wire s_axi_rready;
wire [0:0]s_axi_rresp;
wire s_axi_rvalid;
wire [10:0]s_axi_wdata;
wire s_axi_wready;
wire s_axi_wvalid;
wire scl_clean;
wire scl_i;
wire scl_rin_d1;
wire scl_rising_edge0;
wire scl_t;
wire sda_clean;
wire sda_i;
wire sda_rin_d1;
wire sda_t;
wire shift_reg_ld;
wire [0:3]sr_i;
wire state122_out;
wire stop_scl_reg;
wire [7:4]timing_param_tbuf_i;
wire [5:4]timing_param_thddat_i;
wire [0:0]timing_param_thdsta_i;
wire [7:0]timing_param_thigh_i;
wire [0:0]timing_param_tlow_i;
wire [8:0]timing_param_tsudat_i;
wire [7:4]timing_param_tsusta_i;
wire [7:0]timing_param_tsusto_i;
wire txak;
system_axi_iic_0_0_dynamic_master DYN_MASTER_I
(.Tx_fifo_data(Tx_fifo_data),
.Tx_fifo_rst(Tx_fifo_rst),
.ackDataState(ackDataState),
.callingReadAccess(callingReadAccess),
.cr_txModeSelect_clr(cr_txModeSelect_clr),
.cr_txModeSelect_set(cr_txModeSelect_set),
.earlyAckDataState(earlyAckDataState),
.earlyAckHdr(earlyAckHdr),
.firstDynStartSeen(firstDynStartSeen),
.firstDynStartSeen_reg_0(REG_INTERFACE_I_n_132),
.p_3_in(p_3_in),
.rdCntrFrmTxFifo(rdCntrFrmTxFifo),
.rdCntrFrmTxFifo0(rdCntrFrmTxFifo0),
.rxCntDone(rxCntDone),
.rxCntDone_reg_0(DYN_MASTER_I_n_6),
.s_axi_aclk(s_axi_aclk));
system_axi_iic_0_0_filter FILTER_I
(.detect_stop_b_reg(FILTER_I_n_0),
.s_axi_aclk(s_axi_aclk),
.scl_i(scl_i),
.scl_rin_d1(scl_rin_d1),
.scl_rin_d1_reg(scl_clean),
.scl_rising_edge0(scl_rising_edge0),
.scndry_out(sda_clean),
.sda_i(sda_i),
.sda_rin_d1(sda_rin_d1));
system_axi_iic_0_0_iic_control IIC_CONTROL_I
(.Aas(Aas),
.Bb(Bb),
.CO(clk_cnt_en1),
.D({Al,Txer,IIC_CONTROL_I_n_8,p_0_out}),
.Data_Exists_DFF(WRITE_FIFO_I_n_15),
.E(Bus2IIC_WrCE[0]),
.\FSM_sequential_scl_state_reg[0]_0 (clk_cnt_en12_out),
.\FSM_sequential_scl_state_reg[2]_0 (IIC_CONTROL_I_n_62),
.\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 (scl_clean),
.\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 (FILTER_I_n_0),
.Msms_set(Msms_set),
.New_rcv_dta(New_rcv_dta),
.Q({Cr[1],Cr[2],Cr[4],Cr[5],Cr[7]}),
.\RD_FIFO_CNTRL.Rc_fifo_wr_reg (IIC_CONTROL_I_n_40),
.Ro_prev(Ro_prev),
.S({REG_INTERFACE_I_n_27,REG_INTERFACE_I_n_28,REG_INTERFACE_I_n_29,REG_INTERFACE_I_n_30}),
.SR(REG_INTERFACE_I_n_98),
.Tx_data_exists(Tx_data_exists),
.Tx_fifo_data({Tx_fifo_data[0],Tx_fifo_data[1],Tx_fifo_data[2],Tx_fifo_data[3],Tx_fifo_data[4],Tx_fifo_data[5],Tx_fifo_data[6]}),
.Tx_fifo_rd_d_reg(REG_INTERFACE_I_n_102),
.Tx_under_prev(Tx_under_prev),
.abgc_i_reg_0(i2c_header),
.abgc_i_reg_1(REG_INTERFACE_I_n_26),
.ackDataState(ackDataState),
.arb_lost(arb_lost),
.callingReadAccess(callingReadAccess),
.\cr_i_reg[2] (REG_INTERFACE_I_n_104),
.\cr_i_reg[4] (REG_INTERFACE_I_n_95),
.\cr_i_reg[5] (IIC_CONTROL_I_n_50),
.detect_stop_b_reg_0(IIC_CONTROL_I_n_53),
.dynamic_MSMS(dynamic_MSMS[0]),
.earlyAckDataState(earlyAckDataState),
.earlyAckHdr(earlyAckHdr),
.master_slave(master_slave),
.new_rcv_dta_d1(new_rcv_dta_d1),
.\q_int_reg[0] ({\CLKCNT/q_int_reg__0 [0],\CLKCNT/q_int_reg__0 [1],\CLKCNT/q_int_reg__0 [2],\CLKCNT/q_int_reg__0 [3],\CLKCNT/q_int_reg__0 [4],\CLKCNT/q_int_reg__0 [5],\CLKCNT/q_int_reg__0 [6],\CLKCNT/q_int_reg__0 [7],\CLKCNT/q_int_reg__0 [8],\CLKCNT/q_int_reg__0 [9]}),
.\q_int_reg[0]_0 ({\SETUP_CNT/q_int_reg__0 [0],\SETUP_CNT/q_int_reg__0 [4],\SETUP_CNT/q_int_reg__0 [5],\SETUP_CNT/q_int_reg__0 [6],\SETUP_CNT/q_int_reg__0 [7],\SETUP_CNT/q_int_reg__0 [8],\SETUP_CNT/q_int_reg__0 [9]}),
.rdCntrFrmTxFifo0(rdCntrFrmTxFifo0),
.rdy_new_xmt_i(rdy_new_xmt_i),
.rxCntDone(rxCntDone),
.s_axi_aclk(s_axi_aclk),
.\s_axi_rdata_i_reg[7] ({Data_i2c[0],Data_i2c[1],Data_i2c[2],Data_i2c[3],Data_i2c[4],Data_i2c[5],Data_i2c[6],Data_i2c[7]}),
.s_axi_wdata(s_axi_wdata[2]),
.scl_rin_d1(scl_rin_d1),
.scl_rising_edge0(scl_rising_edge0),
.scl_t(scl_t),
.scndry_out(sda_clean),
.sda_cout_reg_reg_0(clk_cnt_en11_out),
.sda_rin_d1(sda_rin_d1),
.sda_t(sda_t),
.shift_reg_ld(shift_reg_ld),
.shift_reg_ld_reg_0(WRITE_FIFO_I_n_19),
.sr_i(sr_i[0]),
.\sr_i_reg[4] ({Srw,Abgc}),
.state122_out(state122_out),
.stop_scl_reg(stop_scl_reg),
.stop_scl_reg_reg_0(REG_INTERFACE_I_n_103),
.\timing_param_tbuf_i_reg[9] ({REG_INTERFACE_I_n_59,REG_INTERFACE_I_n_60,REG_INTERFACE_I_n_61,REG_INTERFACE_I_n_62}),
.\timing_param_thddat_i_reg[9] ({REG_INTERFACE_I_n_67,REG_INTERFACE_I_n_68,REG_INTERFACE_I_n_69,REG_INTERFACE_I_n_70}),
.\timing_param_thdsta_i_reg[9] ({REG_INTERFACE_I_n_73,REG_INTERFACE_I_n_74,REG_INTERFACE_I_n_75,REG_INTERFACE_I_n_76}),
.\timing_param_tlow_i_reg[9] ({REG_INTERFACE_I_n_78,REG_INTERFACE_I_n_79,REG_INTERFACE_I_n_80,REG_INTERFACE_I_n_81}),
.\timing_param_tsudat_i_reg[8] (timing_param_tsudat_i[8:6]),
.\timing_param_tsudat_i_reg[9] ({REG_INTERFACE_I_n_83,REG_INTERFACE_I_n_84,REG_INTERFACE_I_n_85}),
.\timing_param_tsusta_i_reg[9] ({REG_INTERFACE_I_n_51,REG_INTERFACE_I_n_52,REG_INTERFACE_I_n_53,REG_INTERFACE_I_n_54}),
.\timing_param_tsusto_i_reg[9] ({REG_INTERFACE_I_n_39,REG_INTERFACE_I_n_40,REG_INTERFACE_I_n_41,REG_INTERFACE_I_n_42}),
.txak(txak));
system_axi_iic_0_0_SRL_FIFO READ_FIFO_I
(.Bus2IIC_Reset(Bus2IIC_Reset),
.D({p_1_out,Rc_fifo_full}),
.D_0(D),
.Data_Exists_DFF_0(READ_FIFO_I_n_16),
.Msms_set(Msms_set),
.Q({p_1_in6_in,p_1_in4_in,p_1_in,REG_INTERFACE_I_n_118}),
.\RD_FIFO_CNTRL.Rc_fifo_rd_reg (REG_INTERFACE_I_n_131),
.\RD_FIFO_CNTRL.Rc_fifo_wr_reg (REG_INTERFACE_I_n_130),
.Rc_Data_Exists(Rc_Data_Exists),
.Rc_addr(Rc_addr),
.Rc_fifo_data(Rc_fifo_data),
.Rc_fifo_rd(Rc_fifo_rd),
.Rc_fifo_rd_d(Rc_fifo_rd_d),
.Rc_fifo_wr(Rc_fifo_wr),
.Rc_fifo_wr_d(Rc_fifo_wr_d),
.\data_i2c_i_reg[7] ({Data_i2c[0],Data_i2c[1],Data_i2c[2],Data_i2c[3],Data_i2c[4],Data_i2c[5],Data_i2c[6],Data_i2c[7]}),
.p_6_out(p_6_out),
.s_axi_aclk(s_axi_aclk));
system_axi_iic_0_0_reg_interface REG_INTERFACE_I
(.Aas(Aas),
.\Addr_Counters[0].FDRE_I (REG_INTERFACE_I_n_128),
.\Addr_Counters[0].FDRE_I_0 (REG_INTERFACE_I_n_130),
.\Addr_Counters[0].FDRE_I_1 (REG_INTERFACE_I_n_131),
.\Addr_Counters[1].FDRE_I (WRITE_FIFO_CTRL_I_n_3),
.\Addr_Counters[1].FDRE_I_0 (WRITE_FIFO_I_n_18),
.\Addr_Counters[1].FDRE_I_1 (READ_FIFO_I_n_16),
.\Addr_Counters[3].FDRE_I (WRITE_FIFO_I_n_17),
.Bus2IIC_RdCE(Bus2IIC_RdCE),
.Bus2IIC_Reset(Bus2IIC_Reset),
.Bus2IIC_WrCE({Bus2IIC_WrCE[0],Bus2IIC_WrCE[2],Bus2IIC_WrCE[4],Bus2IIC_WrCE[8],Bus2IIC_WrCE[10],Bus2IIC_WrCE[11],Bus2IIC_WrCE[12],Bus2IIC_WrCE[13],Bus2IIC_WrCE[14],Bus2IIC_WrCE[15],Bus2IIC_WrCE[16],Bus2IIC_WrCE[17]}),
.CO(clk_cnt_en1),
.D(Ro_prev),
.D_0(D_1),
.D_1(D_0),
.D_2(D),
.Data_Exists_DFF(REG_INTERFACE_I_n_97),
.Data_Exists_DFF_0(REG_INTERFACE_I_n_101),
.Data_Exists_DFF_1(WRITE_FIFO_I_n_16),
.Data_Exists_DFF_2(WRITE_FIFO_CTRL_I_n_0),
.Data_Exists_DFF_3({p_1_out,Rc_fifo_full,Tx_fifo_full,Srw,Bb,Abgc}),
.\FSM_onehot_state_reg[4] (REG_INTERFACE_I_n_95),
.\FSM_sequential_scl_state_reg[0] (timing_param_thigh_i),
.\FSM_sequential_scl_state_reg[0]_0 ({REG_INTERFACE_I_n_51,REG_INTERFACE_I_n_52,REG_INTERFACE_I_n_53,REG_INTERFACE_I_n_54}),
.\FSM_sequential_scl_state_reg[0]_1 (REG_INTERFACE_I_n_104),
.\FSM_sequential_scl_state_reg[0]_2 (IIC_CONTROL_I_n_62),
.\FSM_sequential_scl_state_reg[1] ({REG_INTERFACE_I_n_78,REG_INTERFACE_I_n_79,REG_INTERFACE_I_n_80,REG_INTERFACE_I_n_81}),
.\FSM_sequential_scl_state_reg[1]_0 (timing_param_tlow_i),
.\FSM_sequential_scl_state_reg[2] ({REG_INTERFACE_I_n_73,REG_INTERFACE_I_n_74,REG_INTERFACE_I_n_75,REG_INTERFACE_I_n_76}),
.\FSM_sequential_scl_state_reg[2]_0 (timing_param_thdsta_i),
.\FSM_sequential_scl_state_reg[2]_1 (IIC_CONTROL_I_n_53),
.\FSM_sequential_scl_state_reg[3] ({REG_INTERFACE_I_n_59,REG_INTERFACE_I_n_60,REG_INTERFACE_I_n_61,REG_INTERFACE_I_n_62}),
.\FSM_sequential_scl_state_reg[3]_0 (timing_param_tbuf_i),
.\GEN_BKEND_CE_REGISTERS[17].ce_out_i_reg[17] ({X_AXI_IPIF_SSP1_n_15,IIC_CONTROL_I_n_50}),
.\GEN_BKEND_CE_REGISTERS[26].ce_out_i_reg[26] (X_AXI_IPIF_SSP1_n_29),
.IIC2Bus_IntrEvent(IIC2Bus_IntrEvent),
.Msms_set(Msms_set),
.New_rcv_dta(New_rcv_dta),
.Q({Cr[1],Cr[2],Cr[4],Cr[5],Cr[7]}),
.\RD_FIFO_CNTRL.ro_prev_i_reg_0 ({p_1_in6_in,p_1_in4_in,p_1_in,REG_INTERFACE_I_n_118}),
.Rc_Data_Exists(Rc_Data_Exists),
.Rc_addr(Rc_addr),
.Rc_fifo_rd(Rc_fifo_rd),
.Rc_fifo_rd_d(Rc_fifo_rd_d),
.Rc_fifo_wr(Rc_fifo_wr),
.Rc_fifo_wr_d(Rc_fifo_wr_d),
.S({REG_INTERFACE_I_n_27,REG_INTERFACE_I_n_28,REG_INTERFACE_I_n_29,REG_INTERFACE_I_n_30}),
.SR(REG_INTERFACE_I_n_98),
.Tx_data_exists(Tx_data_exists),
.Tx_fifo_data({Tx_fifo_data[4],Tx_fifo_data[5],Tx_fifo_data[6],Tx_fifo_data[7]}),
.Tx_fifo_rd(Tx_fifo_rd),
.Tx_fifo_rd_d(Tx_fifo_rd_d),
.Tx_fifo_rst(Tx_fifo_rst),
.Tx_fifo_wr(Tx_fifo_wr),
.Tx_fifo_wr_d(Tx_fifo_wr_d),
.al_i_reg({Al,Txer,Tx_under_prev,IIC_CONTROL_I_n_8,p_0_out}),
.arb_lost(arb_lost),
.\bus2ip_addr_i_reg[6] ({Bus2IIC_Addr[2],Bus2IIC_Addr[3],Bus2IIC_Addr[4],Bus2IIC_Addr[5],Bus2IIC_Addr[6]}),
.\cr_i_reg[5]_0 (REG_INTERFACE_I_n_102),
.\data_int_reg[7] (i2c_header),
.dtre_d1_reg({sr_i[0],sr_i[2],sr_i[3]}),
.dynamic_MSMS(dynamic_MSMS[1]),
.earlyAckDataState(earlyAckDataState),
.firstDynStartSeen(firstDynStartSeen),
.firstDynStartSeen_reg(REG_INTERFACE_I_n_132),
.gpo(gpo),
.master_slave(master_slave),
.new_rcv_dta_d1(new_rcv_dta_d1),
.new_rcv_dta_i_reg(IIC_CONTROL_I_n_40),
.p_6_out(p_6_out),
.\q_int_reg[0] ({REG_INTERFACE_I_n_67,REG_INTERFACE_I_n_68,REG_INTERFACE_I_n_69,REG_INTERFACE_I_n_70}),
.\q_int_reg[0]_0 ({\CLKCNT/q_int_reg__0 [0],\CLKCNT/q_int_reg__0 [1],\CLKCNT/q_int_reg__0 [2],\CLKCNT/q_int_reg__0 [3],\CLKCNT/q_int_reg__0 [4],\CLKCNT/q_int_reg__0 [5],\CLKCNT/q_int_reg__0 [6],\CLKCNT/q_int_reg__0 [7],\CLKCNT/q_int_reg__0 [8],\CLKCNT/q_int_reg__0 [9]}),
.\q_int_reg[0]_1 ({\SETUP_CNT/q_int_reg__0 [0],\SETUP_CNT/q_int_reg__0 [4],\SETUP_CNT/q_int_reg__0 [5],\SETUP_CNT/q_int_reg__0 [6],\SETUP_CNT/q_int_reg__0 [7],\SETUP_CNT/q_int_reg__0 [8],\SETUP_CNT/q_int_reg__0 [9]}),
.\q_int_reg[9] (REG_INTERFACE_I_n_103),
.\rdByteCntr_reg[2] (DYN_MASTER_I_n_6),
.rdCntrFrmTxFifo(rdCntrFrmTxFifo),
.rdy_new_xmt_i(rdy_new_xmt_i),
.s_axi_aclk(s_axi_aclk),
.\s_axi_rdata_i_reg[0] (REG_INTERFACE_I_n_105),
.\s_axi_rdata_i_reg[0]_0 (REG_INTERFACE_I_n_127),
.\s_axi_rdata_i_reg[1] (REG_INTERFACE_I_n_124),
.\s_axi_rdata_i_reg[1]_0 (REG_INTERFACE_I_n_125),
.\s_axi_rdata_i_reg[1]_1 (REG_INTERFACE_I_n_126),
.\s_axi_rdata_i_reg[2] (REG_INTERFACE_I_n_121),
.\s_axi_rdata_i_reg[2]_0 (REG_INTERFACE_I_n_122),
.\s_axi_rdata_i_reg[2]_1 (REG_INTERFACE_I_n_123),
.\s_axi_rdata_i_reg[3] (REG_INTERFACE_I_n_114),
.\s_axi_rdata_i_reg[3]_0 (REG_INTERFACE_I_n_119),
.\s_axi_rdata_i_reg[3]_1 (REG_INTERFACE_I_n_120),
.\s_axi_rdata_i_reg[4] (REG_INTERFACE_I_n_113),
.\s_axi_rdata_i_reg[5] (timing_param_thddat_i),
.\s_axi_rdata_i_reg[5]_0 (REG_INTERFACE_I_n_112),
.\s_axi_rdata_i_reg[6] (REG_INTERFACE_I_n_106),
.\s_axi_rdata_i_reg[6]_0 (REG_INTERFACE_I_n_111),
.\s_axi_rdata_i_reg[7] (timing_param_tsusta_i),
.\s_axi_rdata_i_reg[7]_0 (REG_INTERFACE_I_n_107),
.\s_axi_rdata_i_reg[7]_1 (REG_INTERFACE_I_n_110),
.\s_axi_rdata_i_reg[8] (timing_param_tsudat_i),
.\s_axi_rdata_i_reg[8]_0 (REG_INTERFACE_I_n_109),
.\s_axi_rdata_i_reg[9] (REG_INTERFACE_I_n_108),
.s_axi_wdata(s_axi_wdata[9:0]),
.sda_cout_reg_reg({REG_INTERFACE_I_n_39,REG_INTERFACE_I_n_40,REG_INTERFACE_I_n_41,REG_INTERFACE_I_n_42}),
.sda_cout_reg_reg_0(timing_param_tsusto_i),
.sda_setup_reg({REG_INTERFACE_I_n_83,REG_INTERFACE_I_n_84,REG_INTERFACE_I_n_85}),
.slave_sda_reg(REG_INTERFACE_I_n_26),
.state122_out(state122_out),
.stop_scl_reg(stop_scl_reg),
.\timing_param_tsusta_i_reg[9]_0 (clk_cnt_en12_out),
.\timing_param_tsusto_i_reg[9]_0 (clk_cnt_en11_out),
.txak(txak));
FDRE Rc_fifo_rd_d_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(Rc_fifo_rd),
.Q(Rc_fifo_rd_d),
.R(Bus2IIC_Reset));
FDRE Rc_fifo_wr_d_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(Rc_fifo_wr),
.Q(Rc_fifo_wr_d),
.R(Bus2IIC_Reset));
FDRE Tx_fifo_rd_d_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(Tx_fifo_rd),
.Q(Tx_fifo_rd_d),
.R(Bus2IIC_Reset));
FDRE Tx_fifo_wr_d_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(Tx_fifo_wr),
.Q(Tx_fifo_wr_d),
.R(Bus2IIC_Reset));
system_axi_iic_0_0_SRL_FIFO__parameterized0 WRITE_FIFO_CTRL_I
(.\Addr_Counters[0].FDRE_I_0 (WRITE_FIFO_CTRL_I_n_0),
.D(D_1),
.Data_Exists_DFF_0(WRITE_FIFO_CTRL_I_n_3),
.\FIFO_GEN_DTR.Tx_fifo_rd_reg (REG_INTERFACE_I_n_101),
.Tx_fifo_rd(Tx_fifo_rd),
.Tx_fifo_rd_d(Tx_fifo_rd_d),
.Tx_fifo_rst(Tx_fifo_rst),
.Tx_fifo_wr_d_reg(REG_INTERFACE_I_n_97),
.ctrlFifoDin(ctrlFifoDin),
.dynamic_MSMS(dynamic_MSMS),
.rdCntrFrmTxFifo(rdCntrFrmTxFifo),
.s_axi_aclk(s_axi_aclk));
system_axi_iic_0_0_SRL_FIFO_0 WRITE_FIFO_I
(.D(D_0),
.Data_Exists_DFF_0(WRITE_FIFO_I_n_18),
.\FIFO_GEN_DTR.IIC2Bus_IntrEvent_reg[7] (WRITE_FIFO_I_n_17),
.\FIFO_GEN_DTR.Tx_fifo_rd_reg (REG_INTERFACE_I_n_101),
.\FIFO_GEN_DTR.Tx_fifo_wr_reg (REG_INTERFACE_I_n_128),
.Tx_addr(Tx_addr),
.Tx_data_exists(Tx_data_exists),
.Tx_fifo_data(Tx_fifo_data),
.Tx_fifo_rd(Tx_fifo_rd),
.Tx_fifo_rd_d(Tx_fifo_rd_d),
.Tx_fifo_rst(Tx_fifo_rst),
.Tx_fifo_wr(Tx_fifo_wr),
.Tx_fifo_wr_d(Tx_fifo_wr_d),
.\cr_i_reg[5] (WRITE_FIFO_I_n_15),
.\data_int_reg[0] (WRITE_FIFO_I_n_19),
.dynamic_MSMS(dynamic_MSMS[1]),
.p_3_in(p_3_in),
.rdCntrFrmTxFifo(rdCntrFrmTxFifo),
.s_axi_aclk(s_axi_aclk),
.s_axi_wdata(s_axi_wdata[7:0]),
.scndry_out(sda_clean),
.shift_reg_ld(shift_reg_ld),
.\sr_i_reg[0] (WRITE_FIFO_I_n_16),
.\sr_i_reg[3] (Tx_fifo_full));
system_axi_iic_0_0_axi_ipif_ssp1 X_AXI_IPIF_SSP1
(.Bus2IIC_RdCE(Bus2IIC_RdCE),
.Bus2IIC_Reset(Bus2IIC_Reset),
.Bus2IIC_WrCE({Bus2IIC_WrCE[0],Bus2IIC_WrCE[2],Bus2IIC_WrCE[4],Bus2IIC_WrCE[8],Bus2IIC_WrCE[10],Bus2IIC_WrCE[11],Bus2IIC_WrCE[12],Bus2IIC_WrCE[13],Bus2IIC_WrCE[14],Bus2IIC_WrCE[15],Bus2IIC_WrCE[16],Bus2IIC_WrCE[17]}),
.\GPO_GEN.gpo_i_reg[31] (X_AXI_IPIF_SSP1_n_29),
.\GPO_GEN.gpo_i_reg[31]_0 (REG_INTERFACE_I_n_105),
.IIC2Bus_IntrEvent(IIC2Bus_IntrEvent),
.\IIC2Bus_IntrEvent_reg[5] (REG_INTERFACE_I_n_125),
.Q({Bus2IIC_Addr[2],Bus2IIC_Addr[3],Bus2IIC_Addr[4],Bus2IIC_Addr[5],Bus2IIC_Addr[6]}),
.\RD_FIFO_CNTRL.rc_fifo_pirq_i_reg[7] (REG_INTERFACE_I_n_118),
.Rc_fifo_data(Rc_fifo_data),
.Tx_addr(Tx_addr),
.Tx_fifo_data({Tx_fifo_data[0],Tx_fifo_data[1],Tx_fifo_data[2],Tx_fifo_data[3]}),
.Tx_fifo_rst(Tx_fifo_rst),
.\adr_i_reg[0] (REG_INTERFACE_I_n_110),
.\adr_i_reg[1] (REG_INTERFACE_I_n_111),
.\adr_i_reg[2] (REG_INTERFACE_I_n_112),
.\adr_i_reg[3] (REG_INTERFACE_I_n_113),
.\adr_i_reg[4] (REG_INTERFACE_I_n_114),
.\adr_i_reg[5] (REG_INTERFACE_I_n_122),
.\adr_i_reg[6] (REG_INTERFACE_I_n_124),
.\bus2ip_addr_i_reg[2] (REG_INTERFACE_I_n_109),
.\bus2ip_addr_i_reg[2]_0 (REG_INTERFACE_I_n_108),
.\cr_i_reg[4] (X_AXI_IPIF_SSP1_n_15),
.\cr_i_reg[4]_0 ({Cr[4],Cr[7]}),
.cr_txModeSelect_clr(cr_txModeSelect_clr),
.cr_txModeSelect_set(cr_txModeSelect_set),
.ctrlFifoDin(ctrlFifoDin),
.gpo(gpo),
.iic2intc_irpt(iic2intc_irpt),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr(s_axi_araddr),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(s_axi_bresp),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(s_axi_rresp),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wready(s_axi_wready),
.s_axi_wvalid(s_axi_wvalid),
.\sr_i_reg[2] ({sr_i[2],sr_i[3]}),
.\sr_i_reg[4] (REG_INTERFACE_I_n_119),
.\sr_i_reg[5] (REG_INTERFACE_I_n_123),
.\timing_param_tbuf_i_reg[0] (REG_INTERFACE_I_n_127),
.\timing_param_tbuf_i_reg[1] (REG_INTERFACE_I_n_126),
.\timing_param_tbuf_i_reg[2] (REG_INTERFACE_I_n_121),
.\timing_param_tbuf_i_reg[3] (REG_INTERFACE_I_n_120),
.\timing_param_tbuf_i_reg[7] (timing_param_tbuf_i),
.\timing_param_thddat_i_reg[5] (timing_param_thddat_i),
.\timing_param_thdsta_i_reg[0] (timing_param_thdsta_i),
.\timing_param_thigh_i_reg[7] (timing_param_thigh_i),
.\timing_param_tlow_i_reg[0] (timing_param_tlow_i),
.\timing_param_tsudat_i_reg[5] (timing_param_tsudat_i[5:0]),
.\timing_param_tsudat_i_reg[6] (REG_INTERFACE_I_n_106),
.\timing_param_tsudat_i_reg[7] (REG_INTERFACE_I_n_107),
.\timing_param_tsusta_i_reg[7] (timing_param_tsusta_i),
.\timing_param_tsusto_i_reg[7] (timing_param_tsusto_i));
endmodule
(* ORIG_REF_NAME = "iic_control" *)
module system_axi_iic_0_0_iic_control
(New_rcv_dta,
shift_reg_ld,
sda_rin_d1,
scl_rin_d1,
Tx_under_prev,
Bb,
D,
earlyAckHdr,
earlyAckDataState,
ackDataState,
CO,
sda_cout_reg_reg_0,
\FSM_sequential_scl_state_reg[0]_0 ,
rdy_new_xmt_i,
arb_lost,
stop_scl_reg,
master_slave,
Aas,
\sr_i_reg[4] ,
\q_int_reg[0] ,
\q_int_reg[0]_0 ,
\RD_FIFO_CNTRL.Rc_fifo_wr_reg ,
abgc_i_reg_0,
sda_t,
\cr_i_reg[5] ,
scl_t,
rdCntrFrmTxFifo0,
detect_stop_b_reg_0,
\s_axi_rdata_i_reg[7] ,
\FSM_sequential_scl_state_reg[2]_0 ,
SR,
s_axi_aclk,
scndry_out,
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 ,
scl_rising_edge0,
Ro_prev,
Q,
sr_i,
S,
\timing_param_tsusto_i_reg[9] ,
\timing_param_tsusta_i_reg[9] ,
\timing_param_tbuf_i_reg[9] ,
\timing_param_thddat_i_reg[9] ,
\timing_param_thdsta_i_reg[9] ,
\timing_param_tlow_i_reg[9] ,
\timing_param_tsudat_i_reg[9] ,
state122_out,
new_rcv_dta_d1,
\cr_i_reg[4] ,
abgc_i_reg_1,
txak,
s_axi_wdata,
E,
Data_Exists_DFF,
rxCntDone,
dynamic_MSMS,
Tx_data_exists,
Tx_fifo_rd_d_reg,
\timing_param_tsudat_i_reg[8] ,
Msms_set,
callingReadAccess,
Tx_fifo_data,
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 ,
shift_reg_ld_reg_0,
stop_scl_reg_reg_0,
\cr_i_reg[2] );
output New_rcv_dta;
output shift_reg_ld;
output sda_rin_d1;
output scl_rin_d1;
output Tx_under_prev;
output Bb;
output [3:0]D;
output earlyAckHdr;
output earlyAckDataState;
output ackDataState;
output [0:0]CO;
output [0:0]sda_cout_reg_reg_0;
output [0:0]\FSM_sequential_scl_state_reg[0]_0 ;
output rdy_new_xmt_i;
output arb_lost;
output stop_scl_reg;
output master_slave;
output Aas;
output [1:0]\sr_i_reg[4] ;
output [9:0]\q_int_reg[0] ;
output [6:0]\q_int_reg[0]_0 ;
output \RD_FIFO_CNTRL.Rc_fifo_wr_reg ;
output [7:0]abgc_i_reg_0;
output sda_t;
output [0:0]\cr_i_reg[5] ;
output scl_t;
output rdCntrFrmTxFifo0;
output detect_stop_b_reg_0;
output [7:0]\s_axi_rdata_i_reg[7] ;
output \FSM_sequential_scl_state_reg[2]_0 ;
input [0:0]SR;
input s_axi_aclk;
input scndry_out;
input \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 ;
input scl_rising_edge0;
input Ro_prev;
input [4:0]Q;
input [0:0]sr_i;
input [3:0]S;
input [3:0]\timing_param_tsusto_i_reg[9] ;
input [3:0]\timing_param_tsusta_i_reg[9] ;
input [3:0]\timing_param_tbuf_i_reg[9] ;
input [3:0]\timing_param_thddat_i_reg[9] ;
input [3:0]\timing_param_thdsta_i_reg[9] ;
input [3:0]\timing_param_tlow_i_reg[9] ;
input [2:0]\timing_param_tsudat_i_reg[9] ;
input state122_out;
input new_rcv_dta_d1;
input \cr_i_reg[4] ;
input abgc_i_reg_1;
input txak;
input [0:0]s_axi_wdata;
input [0:0]E;
input Data_Exists_DFF;
input rxCntDone;
input [0:0]dynamic_MSMS;
input Tx_data_exists;
input Tx_fifo_rd_d_reg;
input [2:0]\timing_param_tsudat_i_reg[8] ;
input Msms_set;
input callingReadAccess;
input [6:0]Tx_fifo_data;
input \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 ;
input [0:0]shift_reg_ld_reg_0;
input stop_scl_reg_reg_0;
input \cr_i_reg[2] ;
wire Aas;
wire BITCNT_n_0;
wire BITCNT_n_2;
wire Bb;
wire [0:0]CO;
wire [3:0]D;
wire Data_Exists_DFF;
wire [0:0]E;
wire EarlyAckDataState0;
wire EarlyAckHdr0;
wire \FSM_onehot_state[0]_i_1_n_0 ;
wire \FSM_onehot_state[0]_i_3_n_0 ;
wire \FSM_onehot_state[0]_i_4_n_0 ;
wire \FSM_onehot_state[0]_i_5_n_0 ;
wire \FSM_onehot_state[1]_i_1_n_0 ;
wire \FSM_onehot_state[2]_i_1_n_0 ;
wire \FSM_onehot_state[3]_i_2_n_0 ;
wire \FSM_onehot_state[4]_i_1_n_0 ;
wire \FSM_onehot_state[4]_i_2_n_0 ;
wire \FSM_onehot_state[4]_i_3_n_0 ;
wire \FSM_onehot_state[5]_i_1_n_0 ;
wire \FSM_onehot_state[5]_i_2_n_0 ;
wire \FSM_onehot_state[6]_i_3_n_0 ;
wire \FSM_onehot_state[6]_i_5_n_0 ;
wire \FSM_onehot_state[6]_i_6_n_0 ;
(* RTL_KEEP = "yes" *) wire \FSM_onehot_state_reg_n_0_[6] ;
wire \FSM_sequential_scl_state[0]_i_1_n_0 ;
wire \FSM_sequential_scl_state[0]_i_2_n_0 ;
wire \FSM_sequential_scl_state[0]_i_3_n_0 ;
wire \FSM_sequential_scl_state[0]_i_4_n_0 ;
wire \FSM_sequential_scl_state[0]_i_5_n_0 ;
wire \FSM_sequential_scl_state[0]_i_6_n_0 ;
wire \FSM_sequential_scl_state[0]_i_7_n_0 ;
wire \FSM_sequential_scl_state[0]_i_8_n_0 ;
wire \FSM_sequential_scl_state[1]_i_1_n_0 ;
wire \FSM_sequential_scl_state[1]_i_2_n_0 ;
wire \FSM_sequential_scl_state[1]_i_3_n_0 ;
wire \FSM_sequential_scl_state[1]_i_4_n_0 ;
wire \FSM_sequential_scl_state[1]_i_5_n_0 ;
wire \FSM_sequential_scl_state[1]_i_6_n_0 ;
wire \FSM_sequential_scl_state[2]_i_1_n_0 ;
wire \FSM_sequential_scl_state[2]_i_2_n_0 ;
wire \FSM_sequential_scl_state[3]_i_2_n_0 ;
wire \FSM_sequential_scl_state[3]_i_3_n_0 ;
wire \FSM_sequential_scl_state[3]_i_5_n_0 ;
wire [0:0]\FSM_sequential_scl_state_reg[0]_0 ;
wire \FSM_sequential_scl_state_reg[2]_0 ;
wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 ;
wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 ;
wire I2CDATA_REG_n_0;
wire I2CDATA_REG_n_2;
wire I2CDATA_REG_n_3;
wire I2CDATA_REG_n_4;
wire I2CDATA_REG_n_5;
wire I2CDATA_REG_n_6;
wire I2CDATA_REG_n_7;
wire I2CDATA_REG_n_8;
wire I2CDATA_REG_n_9;
wire I2CHEADER_REG_n_0;
wire I2CHEADER_REG_n_10;
wire I2CHEADER_REG_n_11;
wire \LEVEL_1_GEN.master_sda_reg_n_0 ;
wire Msms_set;
wire New_rcv_dta;
wire [4:0]Q;
wire \RD_FIFO_CNTRL.Rc_fifo_wr_reg ;
wire Ro_prev;
wire [3:0]S;
wire SETUP_CNT_n_0;
wire SETUP_CNT_n_8;
wire [0:0]SR;
wire Tx_data_exists;
wire [6:0]Tx_fifo_data;
wire Tx_fifo_rd_d_reg;
wire Tx_under_prev;
wire aas_i_i_1_n_0;
wire [7:0]abgc_i_reg_0;
wire abgc_i_reg_1;
wire ackDataState;
wire al_i_i_1_n_0;
wire al_i_i_2_n_0;
wire al_prevent;
wire al_prevent_i_1_n_0;
wire arb_lost;
wire arb_lost_i_1_n_0;
wire arb_lost_i_2_n_0;
wire arb_lost_i_3_n_0;
wire bit_cnt_en;
wire bit_cnt_en0;
wire bus_busy_d1;
wire bus_busy_i_1_n_0;
wire callingReadAccess;
wire clk_cnt_en13_out;
wire clk_cnt_en1_carry_n_1;
wire clk_cnt_en1_carry_n_2;
wire clk_cnt_en1_carry_n_3;
wire \clk_cnt_en1_inferred__0/i__carry_n_1 ;
wire \clk_cnt_en1_inferred__0/i__carry_n_2 ;
wire \clk_cnt_en1_inferred__0/i__carry_n_3 ;
wire \clk_cnt_en1_inferred__1/i__carry_n_1 ;
wire \clk_cnt_en1_inferred__1/i__carry_n_2 ;
wire \clk_cnt_en1_inferred__1/i__carry_n_3 ;
wire \clk_cnt_en1_inferred__2/i__carry_n_1 ;
wire \clk_cnt_en1_inferred__2/i__carry_n_2 ;
wire \clk_cnt_en1_inferred__2/i__carry_n_3 ;
wire clk_cnt_en2;
wire clk_cnt_en2_carry_n_1;
wire clk_cnt_en2_carry_n_2;
wire clk_cnt_en2_carry_n_3;
wire \cr_i[5]_i_3_n_0 ;
wire \cr_i_reg[2] ;
wire \cr_i_reg[4] ;
wire [0:0]\cr_i_reg[5] ;
wire data_i2c_i0;
wire detect_start;
wire detect_start_i_1_n_0;
wire detect_stop0;
wire detect_stop_b_i_1_n_0;
wire detect_stop_b_i_3_n_0;
wire detect_stop_b_reg_0;
wire detect_stop_b_reg_n_0;
wire detect_stop_i_1_n_0;
wire detect_stop_reg_n_0;
wire dtc_i;
wire dtc_i_d1;
wire dtc_i_d2;
wire dtre_d1;
wire [0:0]dynamic_MSMS;
wire earlyAckDataState;
wire earlyAckHdr;
wire gen_start;
wire gen_start_i_1_n_0;
wire gen_stop;
wire gen_stop_d1;
wire gen_stop_i_1_n_0;
wire i2c_header_en;
wire i2c_header_en0;
wire master_slave;
wire master_slave_i_1_n_0;
wire msms_d1;
wire msms_d10;
wire msms_d1_i_2_n_0;
wire msms_d2;
wire msms_rst_i;
wire msms_rst_i_i_1_n_0;
wire new_rcv_dta_d1;
wire next_scl_state10_out;
wire \next_scl_state1_inferred__0/i__carry_n_1 ;
wire \next_scl_state1_inferred__0/i__carry_n_2 ;
wire \next_scl_state1_inferred__0/i__carry_n_3 ;
wire \next_scl_state1_inferred__1/i__carry_n_0 ;
wire \next_scl_state1_inferred__1/i__carry_n_1 ;
wire \next_scl_state1_inferred__1/i__carry_n_2 ;
wire \next_scl_state1_inferred__1/i__carry_n_3 ;
(* RTL_KEEP = "yes" *) wire p_0_in_0;
(* RTL_KEEP = "yes" *) wire p_1_in;
(* RTL_KEEP = "yes" *) wire p_1_in0_in;
(* RTL_KEEP = "yes" *) wire p_1_in6_in;
(* RTL_KEEP = "yes" *) wire p_2_in;
(* RTL_KEEP = "yes" *) wire p_4_in;
wire [9:0]\q_int_reg[0] ;
wire [6:0]\q_int_reg[0]_0 ;
wire rdCntrFrmTxFifo0;
wire rdy_new_xmt_i;
wire rdy_new_xmt_i_i_1_n_0;
wire ro_prev_d1;
wire rsta_d1;
wire rsta_tx_under_prev;
wire rsta_tx_under_prev_i_1_n_0;
wire rxCntDone;
wire s_axi_aclk;
wire [7:0]\s_axi_rdata_i_reg[7] ;
wire [0:0]s_axi_wdata;
wire scl_cout_reg;
wire scl_cout_reg0;
wire scl_f_edg_d1;
wire scl_f_edg_d2;
wire scl_f_edg_d3;
wire scl_falling_edge;
wire scl_falling_edge0;
wire scl_rin_d1;
wire scl_rising_edge;
wire scl_rising_edge0;
(* RTL_KEEP = "yes" *) wire [3:0]scl_state;
wire scl_t;
wire scndry_out;
wire sda_cout;
wire sda_cout1;
wire sda_cout13_out;
wire sda_cout4_out;
wire sda_cout_reg;
wire sda_cout_reg_i_1_n_0;
wire sda_cout_reg_i_2_n_0;
wire [0:0]sda_cout_reg_reg_0;
wire sda_rin_d1;
wire sda_sample;
wire sda_sample_i_1_n_0;
wire sda_setup;
wire \sda_setup0_inferred__0/i__carry_n_0 ;
wire \sda_setup0_inferred__0/i__carry_n_1 ;
wire \sda_setup0_inferred__0/i__carry_n_2 ;
wire \sda_setup0_inferred__0/i__carry_n_3 ;
wire sda_setup_i_1_n_0;
wire sda_t;
wire [7:7]shift_reg;
wire shift_reg_en;
wire shift_reg_en0;
wire shift_reg_en_i_2_n_0;
wire shift_reg_ld;
wire shift_reg_ld0;
wire shift_reg_ld_d1;
wire shift_reg_ld_i_2_n_0;
wire [0:0]shift_reg_ld_reg_0;
wire slave_sda_reg_n_0;
wire sm_stop;
wire sm_stop_i_1_n_0;
wire sm_stop_reg_n_0;
wire [0:0]sr_i;
wire [1:0]\sr_i_reg[4] ;
wire state0;
wire state122_out;
wire stop_scl;
wire stop_scl_reg;
wire stop_scl_reg_i_1_n_0;
wire stop_scl_reg_i_3_n_0;
wire stop_scl_reg_reg_0;
wire [3:0]\timing_param_tbuf_i_reg[9] ;
wire [3:0]\timing_param_thddat_i_reg[9] ;
wire [3:0]\timing_param_thdsta_i_reg[9] ;
wire [3:0]\timing_param_tlow_i_reg[9] ;
wire [2:0]\timing_param_tsudat_i_reg[8] ;
wire [2:0]\timing_param_tsudat_i_reg[9] ;
wire [3:0]\timing_param_tsusta_i_reg[9] ;
wire [3:0]\timing_param_tsusto_i_reg[9] ;
wire tx_under_prev_d1;
wire tx_under_prev_i0;
wire tx_under_prev_i_i_1_n_0;
wire tx_under_prev_i_i_3_n_0;
wire txak;
wire txer_edge_i_1_n_0;
wire txer_i;
wire txer_i_i_1_n_0;
wire txer_i_reg_n_0;
wire [3:0]NLW_clk_cnt_en1_carry_O_UNCONNECTED;
wire [3:0]\NLW_clk_cnt_en1_inferred__0/i__carry_O_UNCONNECTED ;
wire [3:0]\NLW_clk_cnt_en1_inferred__1/i__carry_O_UNCONNECTED ;
wire [3:0]\NLW_clk_cnt_en1_inferred__2/i__carry_O_UNCONNECTED ;
wire [3:0]NLW_clk_cnt_en2_carry_O_UNCONNECTED;
wire [3:0]\NLW_next_scl_state1_inferred__0/i__carry_O_UNCONNECTED ;
wire [3:0]\NLW_next_scl_state1_inferred__1/i__carry_O_UNCONNECTED ;
wire [3:0]\NLW_sda_setup0_inferred__0/i__carry_O_UNCONNECTED ;
FDRE AckDataState_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(p_1_in),
.Q(ackDataState),
.R(SR));
system_axi_iic_0_0_upcnt_n__parameterized0 BITCNT
(.E(BITCNT_n_0),
.EarlyAckDataState0(EarlyAckDataState0),
.\FSM_onehot_state_reg[4] (\FSM_onehot_state[6]_i_6_n_0 ),
.SR(SR),
.bit_cnt_en(bit_cnt_en),
.detect_start(detect_start),
.dtc_i(dtc_i),
.dtc_i_reg(BITCNT_n_2),
.out({\FSM_onehot_state_reg_n_0_[6] ,p_1_in,p_1_in6_in,p_1_in0_in,p_2_in,p_4_in}),
.ro_prev_d1_reg(\FSM_onehot_state[6]_i_5_n_0 ),
.s_axi_aclk(s_axi_aclk),
.scl_falling_edge(scl_falling_edge));
system_axi_iic_0_0_upcnt_n CLKCNT
(.CO(clk_cnt_en13_out),
.\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 (\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 ),
.SR(SR),
.detect_stop_b_reg(detect_stop_b_reg_n_0),
.out(scl_state),
.\q_int_reg[0]_0 (\q_int_reg[0] ),
.s_axi_aclk(s_axi_aclk),
.stop_scl_reg_reg(stop_scl_reg_reg_0),
.\timing_param_thddat_i_reg[9] (clk_cnt_en2));
FDRE EarlyAckDataState_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(EarlyAckDataState0),
.Q(earlyAckDataState),
.R(SR));
LUT2 #(
.INIT(4'h8))
EarlyAckHdr_i_1
(.I0(p_1_in0_in),
.I1(scl_f_edg_d3),
.O(EarlyAckHdr0));
FDRE EarlyAckHdr_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(EarlyAckHdr0),
.Q(earlyAckHdr),
.R(SR));
LUT6 #(
.INIT(64'h00000000FFFFEFE0))
\FSM_onehot_state[0]_i_1
(.I0(state122_out),
.I1(\FSM_onehot_state[0]_i_3_n_0 ),
.I2(p_1_in0_in),
.I3(\FSM_onehot_state[0]_i_4_n_0 ),
.I4(\FSM_onehot_state[0]_i_5_n_0 ),
.I5(\FSM_onehot_state[4]_i_2_n_0 ),
.O(\FSM_onehot_state[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT2 #(
.INIT(4'hE))
\FSM_onehot_state[0]_i_3
(.I0(sda_sample),
.I1(arb_lost),
.O(\FSM_onehot_state[0]_i_3_n_0 ));
LUT6 #(
.INIT(64'h4400440044007703))
\FSM_onehot_state[0]_i_4
(.I0(detect_start),
.I1(p_1_in6_in),
.I2(\FSM_onehot_state_reg_n_0_[6] ),
.I3(state122_out),
.I4(p_1_in),
.I5(p_0_in_0),
.O(\FSM_onehot_state[0]_i_4_n_0 ));
LUT5 #(
.INIT(32'h00000054))
\FSM_onehot_state[0]_i_5
(.I0(p_1_in6_in),
.I1(sda_sample),
.I2(arb_lost),
.I3(p_0_in_0),
.I4(p_1_in),
.O(\FSM_onehot_state[0]_i_5_n_0 ));
LUT6 #(
.INIT(64'hAAAAAAAAAAAAEEEA))
\FSM_onehot_state[1]_i_1
(.I0(p_4_in),
.I1(detect_start),
.I2(p_1_in6_in),
.I3(p_0_in_0),
.I4(p_1_in0_in),
.I5(p_2_in),
.O(\FSM_onehot_state[1]_i_1_n_0 ));
LUT2 #(
.INIT(4'h2))
\FSM_onehot_state[2]_i_1
(.I0(p_2_in),
.I1(p_4_in),
.O(\FSM_onehot_state[2]_i_1_n_0 ));
LUT4 #(
.INIT(16'h0010))
\FSM_onehot_state[3]_i_2
(.I0(Ro_prev),
.I1(p_0_in_0),
.I2(p_1_in),
.I3(p_1_in6_in),
.O(\FSM_onehot_state[3]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0101010000000100))
\FSM_onehot_state[4]_i_1
(.I0(arb_lost),
.I1(sda_sample),
.I2(\FSM_onehot_state[4]_i_2_n_0 ),
.I3(\FSM_onehot_state[4]_i_3_n_0 ),
.I4(p_1_in0_in),
.I5(\cr_i_reg[4] ),
.O(\FSM_onehot_state[4]_i_1_n_0 ));
LUT2 #(
.INIT(4'hE))
\FSM_onehot_state[4]_i_2
(.I0(p_4_in),
.I1(p_2_in),
.O(\FSM_onehot_state[4]_i_2_n_0 ));
LUT5 #(
.INIT(32'h00000002))
\FSM_onehot_state[4]_i_3
(.I0(\FSM_onehot_state_reg_n_0_[6] ),
.I1(p_0_in_0),
.I2(p_1_in6_in),
.I3(p_1_in),
.I4(state122_out),
.O(\FSM_onehot_state[4]_i_3_n_0 ));
LUT4 #(
.INIT(16'h0100))
\FSM_onehot_state[5]_i_1
(.I0(p_1_in0_in),
.I1(p_4_in),
.I2(p_2_in),
.I3(\FSM_onehot_state[5]_i_2_n_0 ),
.O(\FSM_onehot_state[5]_i_1_n_0 ));
LUT6 #(
.INIT(64'h101F101010101010))
\FSM_onehot_state[5]_i_2
(.I0(state122_out),
.I1(detect_start),
.I2(p_1_in6_in),
.I3(p_0_in_0),
.I4(Ro_prev),
.I5(p_1_in),
.O(\FSM_onehot_state[5]_i_2_n_0 ));
LUT2 #(
.INIT(4'hB))
\FSM_onehot_state[6]_i_1
(.I0(detect_stop_reg_n_0),
.I1(Q[0]),
.O(state0));
LUT6 #(
.INIT(64'h0000000000000100))
\FSM_onehot_state[6]_i_3
(.I0(detect_start),
.I1(p_1_in6_in),
.I2(p_4_in),
.I3(p_0_in_0),
.I4(p_1_in0_in),
.I5(p_2_in),
.O(\FSM_onehot_state[6]_i_3_n_0 ));
LUT3 #(
.INIT(8'h0D))
\FSM_onehot_state[6]_i_5
(.I0(ro_prev_d1),
.I1(Ro_prev),
.I2(scl_f_edg_d2),
.O(\FSM_onehot_state[6]_i_5_n_0 ));
LUT2 #(
.INIT(4'hE))
\FSM_onehot_state[6]_i_6
(.I0(p_0_in_0),
.I1(p_1_in6_in),
.O(\FSM_onehot_state[6]_i_6_n_0 ));
(* KEEP = "yes" *)
FDSE #(
.INIT(1'b1))
\FSM_onehot_state_reg[0]
(.C(s_axi_aclk),
.CE(BITCNT_n_0),
.D(\FSM_onehot_state[0]_i_1_n_0 ),
.Q(p_4_in),
.S(state0));
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\FSM_onehot_state_reg[1]
(.C(s_axi_aclk),
.CE(BITCNT_n_0),
.D(\FSM_onehot_state[1]_i_1_n_0 ),
.Q(p_2_in),
.R(state0));
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\FSM_onehot_state_reg[2]
(.C(s_axi_aclk),
.CE(BITCNT_n_0),
.D(\FSM_onehot_state[2]_i_1_n_0 ),
.Q(p_1_in0_in),
.R(state0));
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\FSM_onehot_state_reg[3]
(.C(s_axi_aclk),
.CE(BITCNT_n_0),
.D(I2CHEADER_REG_n_0),
.Q(p_1_in6_in),
.R(state0));
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\FSM_onehot_state_reg[4]
(.C(s_axi_aclk),
.CE(BITCNT_n_0),
.D(\FSM_onehot_state[4]_i_1_n_0 ),
.Q(p_0_in_0),
.R(state0));
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\FSM_onehot_state_reg[5]
(.C(s_axi_aclk),
.CE(BITCNT_n_0),
.D(\FSM_onehot_state[5]_i_1_n_0 ),
.Q(p_1_in),
.R(state0));
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\FSM_onehot_state_reg[6]
(.C(s_axi_aclk),
.CE(BITCNT_n_0),
.D(\FSM_onehot_state[6]_i_3_n_0 ),
.Q(\FSM_onehot_state_reg_n_0_[6] ),
.R(state0));
LUT6 #(
.INIT(64'hFFFFFFFFEEEEEEFE))
\FSM_sequential_scl_state[0]_i_1
(.I0(\FSM_sequential_scl_state[0]_i_2_n_0 ),
.I1(\FSM_sequential_scl_state[0]_i_3_n_0 ),
.I2(\FSM_sequential_scl_state[0]_i_4_n_0 ),
.I3(clk_cnt_en13_out),
.I4(scl_state[2]),
.I5(\FSM_sequential_scl_state[0]_i_5_n_0 ),
.O(\FSM_sequential_scl_state[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFBAAAAAAA))
\FSM_sequential_scl_state[0]_i_2
(.I0(\FSM_sequential_scl_state[0]_i_6_n_0 ),
.I1(next_scl_state10_out),
.I2(scl_state[0]),
.I3(scl_state[1]),
.I4(detect_stop_b_reg_0),
.I5(\FSM_sequential_scl_state[0]_i_7_n_0 ),
.O(\FSM_sequential_scl_state[0]_i_2_n_0 ));
LUT5 #(
.INIT(32'h00000020))
\FSM_sequential_scl_state[0]_i_3
(.I0(scl_state[2]),
.I1(scl_state[3]),
.I2(scl_state[0]),
.I3(scl_state[1]),
.I4(\next_scl_state1_inferred__1/i__carry_n_0 ),
.O(\FSM_sequential_scl_state[0]_i_3_n_0 ));
LUT2 #(
.INIT(4'h2))
\FSM_sequential_scl_state[0]_i_4
(.I0(scl_state[0]),
.I1(scl_state[1]),
.O(\FSM_sequential_scl_state[0]_i_4_n_0 ));
LUT6 #(
.INIT(64'h000000004444C000))
\FSM_sequential_scl_state[0]_i_5
(.I0(scndry_out),
.I1(detect_stop_b_reg_0),
.I2(\FSM_sequential_scl_state[0]_i_8_n_0 ),
.I3(\FSM_sequential_scl_state[1]_i_6_n_0 ),
.I4(scl_state[1]),
.I5(scl_state[0]),
.O(\FSM_sequential_scl_state[0]_i_5_n_0 ));
LUT6 #(
.INIT(64'h000C020000000200))
\FSM_sequential_scl_state[0]_i_6
(.I0(scndry_out),
.I1(scl_state[1]),
.I2(scl_state[0]),
.I3(scl_state[3]),
.I4(scl_state[2]),
.I5(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 ),
.O(\FSM_sequential_scl_state[0]_i_6_n_0 ));
LUT6 #(
.INIT(64'h0000000000000020))
\FSM_sequential_scl_state[0]_i_7
(.I0(clk_cnt_en2),
.I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 ),
.I2(scl_state[2]),
.I3(scl_state[3]),
.I4(scl_state[1]),
.I5(scl_state[0]),
.O(\FSM_sequential_scl_state[0]_i_7_n_0 ));
LUT2 #(
.INIT(4'h2))
\FSM_sequential_scl_state[0]_i_8
(.I0(detect_stop_b_reg_n_0),
.I1(clk_cnt_en13_out),
.O(\FSM_sequential_scl_state[0]_i_8_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFF88F8))
\FSM_sequential_scl_state[1]_i_1
(.I0(\FSM_sequential_scl_state[1]_i_2_n_0 ),
.I1(\next_scl_state1_inferred__1/i__carry_n_0 ),
.I2(\FSM_sequential_scl_state[1]_i_3_n_0 ),
.I3(scl_state[3]),
.I4(\FSM_sequential_scl_state[1]_i_4_n_0 ),
.I5(\FSM_sequential_scl_state[1]_i_5_n_0 ),
.O(\FSM_sequential_scl_state[1]_i_1_n_0 ));
LUT4 #(
.INIT(16'h0400))
\FSM_sequential_scl_state[1]_i_2
(.I0(scl_state[1]),
.I1(scl_state[0]),
.I2(scl_state[3]),
.I3(scl_state[2]),
.O(\FSM_sequential_scl_state[1]_i_2_n_0 ));
LUT2 #(
.INIT(4'h2))
\FSM_sequential_scl_state[1]_i_3
(.I0(scl_state[1]),
.I1(scl_state[0]),
.O(\FSM_sequential_scl_state[1]_i_3_n_0 ));
LUT6 #(
.INIT(64'h4C4C000C40400000))
\FSM_sequential_scl_state[1]_i_4
(.I0(scl_state[1]),
.I1(detect_stop_b_reg_0),
.I2(scl_state[0]),
.I3(detect_stop_b_reg_n_0),
.I4(clk_cnt_en13_out),
.I5(\FSM_sequential_scl_state[1]_i_6_n_0 ),
.O(\FSM_sequential_scl_state[1]_i_4_n_0 ));
LUT6 #(
.INIT(64'h010D010100000000))
\FSM_sequential_scl_state[1]_i_5
(.I0(next_scl_state10_out),
.I1(scl_state[2]),
.I2(scl_state[3]),
.I3(arb_lost),
.I4(Q[3]),
.I5(scl_state[1]),
.O(\FSM_sequential_scl_state[1]_i_5_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT3 #(
.INIT(8'h40))
\FSM_sequential_scl_state[1]_i_6
(.I0(Bb),
.I1(gen_start),
.I2(master_slave),
.O(\FSM_sequential_scl_state[1]_i_6_n_0 ));
LUT6 #(
.INIT(64'h00FF0000003000AA))
\FSM_sequential_scl_state[2]_i_1
(.I0(next_scl_state10_out),
.I1(stop_scl_reg),
.I2(\FSM_sequential_scl_state[2]_i_2_n_0 ),
.I3(scl_state[3]),
.I4(scl_state[2]),
.I5(\FSM_sequential_scl_state_reg[2]_0 ),
.O(\FSM_sequential_scl_state[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT2 #(
.INIT(4'h1))
\FSM_sequential_scl_state[2]_i_2
(.I0(arb_lost),
.I1(Q[3]),
.O(\FSM_sequential_scl_state[2]_i_2_n_0 ));
LUT2 #(
.INIT(4'h7))
\FSM_sequential_scl_state[2]_i_3
(.I0(scl_state[0]),
.I1(scl_state[1]),
.O(\FSM_sequential_scl_state_reg[2]_0 ));
LUT6 #(
.INIT(64'h05FF05FF05FF057F))
\FSM_sequential_scl_state[3]_i_2
(.I0(scl_state[1]),
.I1(scl_state[0]),
.I2(scl_state[2]),
.I3(scl_state[3]),
.I4(\cr_i_reg[2] ),
.I5(arb_lost),
.O(\FSM_sequential_scl_state[3]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0A000000003000F0))
\FSM_sequential_scl_state[3]_i_3
(.I0(\FSM_sequential_scl_state[3]_i_5_n_0 ),
.I1(clk_cnt_en13_out),
.I2(scl_state[3]),
.I3(scl_state[2]),
.I4(scl_state[0]),
.I5(scl_state[1]),
.O(\FSM_sequential_scl_state[3]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT3 #(
.INIT(8'h10))
\FSM_sequential_scl_state[3]_i_5
(.I0(Q[3]),
.I1(arb_lost),
.I2(stop_scl_reg),
.O(\FSM_sequential_scl_state[3]_i_5_n_0 ));
(* KEEP = "yes" *)
FDRE \FSM_sequential_scl_state_reg[0]
(.C(s_axi_aclk),
.CE(\FSM_sequential_scl_state[3]_i_2_n_0 ),
.D(\FSM_sequential_scl_state[0]_i_1_n_0 ),
.Q(scl_state[0]),
.R(SR));
(* KEEP = "yes" *)
FDRE \FSM_sequential_scl_state_reg[1]
(.C(s_axi_aclk),
.CE(\FSM_sequential_scl_state[3]_i_2_n_0 ),
.D(\FSM_sequential_scl_state[1]_i_1_n_0 ),
.Q(scl_state[1]),
.R(SR));
(* KEEP = "yes" *)
FDRE \FSM_sequential_scl_state_reg[2]
(.C(s_axi_aclk),
.CE(\FSM_sequential_scl_state[3]_i_2_n_0 ),
.D(\FSM_sequential_scl_state[2]_i_1_n_0 ),
.Q(scl_state[2]),
.R(SR));
(* KEEP = "yes" *)
FDRE \FSM_sequential_scl_state_reg[3]
(.C(s_axi_aclk),
.CE(\FSM_sequential_scl_state[3]_i_2_n_0 ),
.D(\FSM_sequential_scl_state[3]_i_3_n_0 ),
.Q(scl_state[3]),
.R(SR));
system_axi_iic_0_0_shift8 I2CDATA_REG
(.\LEVEL_1_GEN.master_sda_reg (I2CDATA_REG_n_0),
.Q({shift_reg,I2CDATA_REG_n_2,I2CDATA_REG_n_3,I2CDATA_REG_n_4,I2CDATA_REG_n_5,I2CDATA_REG_n_6,I2CDATA_REG_n_7,I2CDATA_REG_n_8}),
.SR(SR),
.Tx_fifo_data(Tx_fifo_data),
.abgc_i_reg(abgc_i_reg_1),
.out({p_1_in,p_0_in_0,p_1_in0_in,p_2_in}),
.s_axi_aclk(s_axi_aclk),
.shift_reg_en(shift_reg_en),
.shift_reg_ld_reg(shift_reg_ld),
.shift_reg_ld_reg_0(shift_reg_ld_reg_0),
.slave_sda_reg(I2CDATA_REG_n_9),
.tx_under_prev_i_reg(Tx_under_prev),
.txak(txak));
system_axi_iic_0_0_shift8_1 I2CHEADER_REG
(.D(I2CHEADER_REG_n_0),
.E(i2c_header_en),
.\FSM_onehot_state_reg[6] (shift_reg_ld_i_2_n_0),
.Q(abgc_i_reg_0),
.\RD_FIFO_CNTRL.ro_prev_i_reg (\FSM_onehot_state[3]_i_2_n_0 ),
.SR(SR),
.abgc_i_reg(I2CHEADER_REG_n_10),
.abgc_i_reg_0(abgc_i_reg_1),
.arb_lost_reg(arb_lost),
.\cr_i_reg[1] ({Q[4],Q[2],Q[0]}),
.detect_start(detect_start),
.detect_stop_reg(detect_stop_reg_n_0),
.master_slave_reg(master_slave),
.out({p_1_in0_in,p_2_in,p_4_in}),
.s_axi_aclk(s_axi_aclk),
.scndry_out(scndry_out),
.sda_sample(sda_sample),
.shift_reg_ld0(shift_reg_ld0),
.srw_i_reg(I2CHEADER_REG_n_11),
.srw_i_reg_0(\sr_i_reg[4] ));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT1 #(
.INIT(2'h1))
\IIC2Bus_IntrEvent[4]_i_1
(.I0(Bb),
.O(D[1]));
LUT1 #(
.INIT(2'h1))
\IIC2Bus_IntrEvent[6]_i_1
(.I0(Aas),
.O(D[0]));
FDSE \LEVEL_1_GEN.master_sda_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(I2CDATA_REG_n_0),
.Q(\LEVEL_1_GEN.master_sda_reg_n_0 ),
.S(SR));
LUT2 #(
.INIT(4'h2))
\RD_FIFO_CNTRL.Rc_fifo_wr_i_1
(.I0(New_rcv_dta),
.I1(new_rcv_dta_d1),
.O(\RD_FIFO_CNTRL.Rc_fifo_wr_reg ));
system_axi_iic_0_0_upcnt_n_2 SETUP_CNT
(.Q(Q[3]),
.S(SETUP_CNT_n_8),
.SR(SR),
.gen_stop(gen_stop),
.gen_stop_d1(gen_stop_d1),
.\q_int_reg[0]_0 (\q_int_reg[0]_0 ),
.\q_int_reg[1]_0 (SETUP_CNT_n_0),
.rsta_d1(rsta_d1),
.s_axi_aclk(s_axi_aclk),
.scndry_out(scndry_out),
.sda_rin_d1_reg(sda_rin_d1),
.sda_setup(sda_setup),
.\timing_param_tsudat_i_reg[8] (\timing_param_tsudat_i_reg[8] ),
.tx_under_prev_d1(tx_under_prev_d1),
.tx_under_prev_i_reg(Tx_under_prev));
LUT5 #(
.INIT(32'h000E0000))
aas_i_i_1
(.I0(Aas),
.I1(p_1_in0_in),
.I2(abgc_i_reg_1),
.I3(detect_stop_reg_n_0),
.I4(Q[0]),
.O(aas_i_i_1_n_0));
FDRE aas_i_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(aas_i_i_1_n_0),
.Q(Aas),
.R(1'b0));
FDRE abgc_i_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(I2CHEADER_REG_n_10),
.Q(\sr_i_reg[4] [0]),
.R(1'b0));
LUT6 #(
.INIT(64'hE0E0E0E0E0EEE0E0))
al_i_i_1
(.I0(Q[3]),
.I1(master_slave),
.I2(al_i_i_2_n_0),
.I3(al_prevent),
.I4(detect_stop_reg_n_0),
.I5(sm_stop_reg_n_0),
.O(al_i_i_1_n_0));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT4 #(
.INIT(16'hFF8F))
al_i_i_2
(.I0(bus_busy_d1),
.I1(gen_start),
.I2(master_slave),
.I3(arb_lost),
.O(al_i_i_2_n_0));
FDRE al_i_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(al_i_i_1_n_0),
.Q(D[3]),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT4 #(
.INIT(16'h5554))
al_prevent_i_1
(.I0(detect_start),
.I1(gen_stop),
.I2(sm_stop_reg_n_0),
.I3(al_prevent),
.O(al_prevent_i_1_n_0));
FDRE al_prevent_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(al_prevent_i_1_n_0),
.Q(al_prevent),
.R(SR));
LUT6 #(
.INIT(64'h000000002AEA2A2A))
arb_lost_i_1
(.I0(arb_lost),
.I1(master_slave),
.I2(arb_lost_i_2_n_0),
.I3(scndry_out),
.I4(sda_cout_reg),
.I5(arb_lost_i_3_n_0),
.O(arb_lost_i_1_n_0));
LUT3 #(
.INIT(8'hA8))
arb_lost_i_2
(.I0(scl_rising_edge),
.I1(p_0_in_0),
.I2(p_2_in),
.O(arb_lost_i_2_n_0));
LUT5 #(
.INIT(32'h0401FFFF))
arb_lost_i_3
(.I0(scl_state[2]),
.I1(scl_state[3]),
.I2(scl_state[1]),
.I3(scl_state[0]),
.I4(Q[0]),
.O(arb_lost_i_3_n_0));
FDRE arb_lost_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(arb_lost_i_1_n_0),
.Q(arb_lost),
.R(1'b0));
LUT4 #(
.INIT(16'hAAA8))
bit_cnt_en_i_1
(.I0(scl_falling_edge),
.I1(p_1_in6_in),
.I2(p_2_in),
.I3(p_0_in_0),
.O(bit_cnt_en0));
FDRE bit_cnt_en_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(bit_cnt_en0),
.Q(bit_cnt_en),
.R(SR));
FDRE bus_busy_d1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(Bb),
.Q(bus_busy_d1),
.R(SR));
LUT4 #(
.INIT(16'h00E0))
bus_busy_i_1
(.I0(Bb),
.I1(detect_start),
.I2(Q[0]),
.I3(detect_stop_reg_n_0),
.O(bus_busy_i_1_n_0));
FDRE bus_busy_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(bus_busy_i_1_n_0),
.Q(Bb),
.R(1'b0));
CARRY4 clk_cnt_en1_carry
(.CI(1'b0),
.CO({CO,clk_cnt_en1_carry_n_1,clk_cnt_en1_carry_n_2,clk_cnt_en1_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_clk_cnt_en1_carry_O_UNCONNECTED[3:0]),
.S(S));
CARRY4 \clk_cnt_en1_inferred__0/i__carry
(.CI(1'b0),
.CO({sda_cout_reg_reg_0,\clk_cnt_en1_inferred__0/i__carry_n_1 ,\clk_cnt_en1_inferred__0/i__carry_n_2 ,\clk_cnt_en1_inferred__0/i__carry_n_3 }),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\NLW_clk_cnt_en1_inferred__0/i__carry_O_UNCONNECTED [3:0]),
.S(\timing_param_tsusto_i_reg[9] ));
CARRY4 \clk_cnt_en1_inferred__1/i__carry
(.CI(1'b0),
.CO({\FSM_sequential_scl_state_reg[0]_0 ,\clk_cnt_en1_inferred__1/i__carry_n_1 ,\clk_cnt_en1_inferred__1/i__carry_n_2 ,\clk_cnt_en1_inferred__1/i__carry_n_3 }),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\NLW_clk_cnt_en1_inferred__1/i__carry_O_UNCONNECTED [3:0]),
.S(\timing_param_tsusta_i_reg[9] ));
CARRY4 \clk_cnt_en1_inferred__2/i__carry
(.CI(1'b0),
.CO({clk_cnt_en13_out,\clk_cnt_en1_inferred__2/i__carry_n_1 ,\clk_cnt_en1_inferred__2/i__carry_n_2 ,\clk_cnt_en1_inferred__2/i__carry_n_3 }),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\NLW_clk_cnt_en1_inferred__2/i__carry_O_UNCONNECTED [3:0]),
.S(\timing_param_tbuf_i_reg[9] ));
CARRY4 clk_cnt_en2_carry
(.CI(1'b0),
.CO({clk_cnt_en2,clk_cnt_en2_carry_n_1,clk_cnt_en2_carry_n_2,clk_cnt_en2_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_clk_cnt_en2_carry_O_UNCONNECTED[3:0]),
.S(\timing_param_thddat_i_reg[9] ));
LUT2 #(
.INIT(4'h1))
\cr_i[2]_i_3
(.I0(scl_state[2]),
.I1(scl_state[3]),
.O(detect_stop_b_reg_0));
LUT6 #(
.INIT(64'h88888888BBBB888B))
\cr_i[5]_i_1
(.I0(s_axi_wdata),
.I1(E),
.I2(Bb),
.I3(Data_Exists_DFF),
.I4(Q[1]),
.I5(\cr_i[5]_i_3_n_0 ),
.O(\cr_i_reg[5] ));
LUT6 #(
.INIT(64'hFEFEFEFEFFFEFEFE))
\cr_i[5]_i_3
(.I0(rxCntDone),
.I1(msms_rst_i),
.I2(sm_stop_reg_n_0),
.I3(dynamic_MSMS),
.I4(Tx_data_exists),
.I5(Tx_fifo_rd_d_reg),
.O(\cr_i[5]_i_3_n_0 ));
FDRE \data_i2c_i_reg[0]
(.C(s_axi_aclk),
.CE(data_i2c_i0),
.D(I2CDATA_REG_n_8),
.Q(\s_axi_rdata_i_reg[7] [0]),
.R(SR));
FDRE \data_i2c_i_reg[1]
(.C(s_axi_aclk),
.CE(data_i2c_i0),
.D(I2CDATA_REG_n_7),
.Q(\s_axi_rdata_i_reg[7] [1]),
.R(SR));
FDRE \data_i2c_i_reg[2]
(.C(s_axi_aclk),
.CE(data_i2c_i0),
.D(I2CDATA_REG_n_6),
.Q(\s_axi_rdata_i_reg[7] [2]),
.R(SR));
FDRE \data_i2c_i_reg[3]
(.C(s_axi_aclk),
.CE(data_i2c_i0),
.D(I2CDATA_REG_n_5),
.Q(\s_axi_rdata_i_reg[7] [3]),
.R(SR));
FDRE \data_i2c_i_reg[4]
(.C(s_axi_aclk),
.CE(data_i2c_i0),
.D(I2CDATA_REG_n_4),
.Q(\s_axi_rdata_i_reg[7] [4]),
.R(SR));
FDRE \data_i2c_i_reg[5]
(.C(s_axi_aclk),
.CE(data_i2c_i0),
.D(I2CDATA_REG_n_3),
.Q(\s_axi_rdata_i_reg[7] [5]),
.R(SR));
FDRE \data_i2c_i_reg[6]
(.C(s_axi_aclk),
.CE(data_i2c_i0),
.D(I2CDATA_REG_n_2),
.Q(\s_axi_rdata_i_reg[7] [6]),
.R(SR));
FDRE \data_i2c_i_reg[7]
(.C(s_axi_aclk),
.CE(data_i2c_i0),
.D(shift_reg),
.Q(\s_axi_rdata_i_reg[7] [7]),
.R(SR));
LUT6 #(
.INIT(64'h00000000BA8A0000))
detect_start_i_1
(.I0(detect_start),
.I1(scndry_out),
.I2(sda_rin_d1),
.I3(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 ),
.I4(Q[0]),
.I5(p_2_in),
.O(detect_start_i_1_n_0));
FDRE detect_start_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(detect_start_i_1_n_0),
.Q(detect_start),
.R(1'b0));
LUT6 #(
.INIT(64'h00000000CEEE0222))
detect_stop_b_i_1
(.I0(detect_stop_b_reg_n_0),
.I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 ),
.I2(\FSM_sequential_scl_state[1]_i_3_n_0 ),
.I3(detect_stop_b_reg_0),
.I4(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 ),
.I5(detect_stop_b_i_3_n_0),
.O(detect_stop_b_i_1_n_0));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT2 #(
.INIT(4'hB))
detect_stop_b_i_3
(.I0(detect_start),
.I1(Q[0]),
.O(detect_stop_b_i_3_n_0));
FDRE detect_stop_b_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(detect_stop_b_i_1_n_0),
.Q(detect_stop_b_reg_n_0),
.R(1'b0));
LUT6 #(
.INIT(64'h0000000022F22202))
detect_stop_i_1
(.I0(detect_stop_reg_n_0),
.I1(detect_stop0),
.I2(scndry_out),
.I3(sda_rin_d1),
.I4(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 ),
.I5(detect_stop_b_i_3_n_0),
.O(detect_stop_i_1_n_0));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT2 #(
.INIT(4'h2))
detect_stop_i_2
(.I0(msms_d1),
.I1(msms_d2),
.O(detect_stop0));
FDRE detect_stop_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(detect_stop_i_1_n_0),
.Q(detect_stop_reg_n_0),
.R(1'b0));
FDRE dtc_i_d1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(dtc_i),
.Q(dtc_i_d1),
.R(SR));
FDRE dtc_i_d2_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(dtc_i_d1),
.Q(dtc_i_d2),
.R(SR));
FDRE dtc_i_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(BITCNT_n_2),
.Q(dtc_i),
.R(SR));
FDRE dtre_d1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(sr_i),
.Q(dtre_d1),
.R(SR));
LUT4 #(
.INIT(16'h7530))
gen_start_i_1
(.I0(detect_start),
.I1(msms_d2),
.I2(msms_d1),
.I3(gen_start),
.O(gen_start_i_1_n_0));
FDRE gen_start_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(gen_start_i_1_n_0),
.Q(gen_start),
.R(SR));
FDRE gen_stop_d1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(gen_stop),
.Q(gen_stop_d1),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT5 #(
.INIT(32'h55750030))
gen_stop_i_1
(.I0(detect_stop_reg_n_0),
.I1(arb_lost),
.I2(msms_d2),
.I3(msms_d1),
.I4(gen_stop),
.O(gen_stop_i_1_n_0));
FDRE gen_stop_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(gen_stop_i_1_n_0),
.Q(gen_stop),
.R(SR));
LUT2 #(
.INIT(4'h8))
i2c_header_en_i_1
(.I0(p_2_in),
.I1(scl_rising_edge),
.O(i2c_header_en0));
FDRE i2c_header_en_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(i2c_header_en0),
.Q(i2c_header_en),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT5 #(
.INIT(32'h00A0C0A0))
master_slave_i_1
(.I0(msms_d1),
.I1(master_slave),
.I2(Q[0]),
.I3(Bb),
.I4(arb_lost),
.O(master_slave_i_1_n_0));
FDRE master_slave_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(master_slave_i_1_n_0),
.Q(master_slave),
.R(1'b0));
LUT2 #(
.INIT(4'h2))
msms_d1_i_1
(.I0(msms_d1_i_2_n_0),
.I1(msms_rst_i),
.O(msms_d10));
LUT6 #(
.INIT(64'hAABAAAAAAABAAABA))
msms_d1_i_2
(.I0(Q[1]),
.I1(txer_i_reg_n_0),
.I2(msms_d1),
.I3(Msms_set),
.I4(dtc_i_d2),
.I5(dtc_i_d1),
.O(msms_d1_i_2_n_0));
FDRE msms_d1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(msms_d10),
.Q(msms_d1),
.R(SR));
FDRE msms_d2_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(msms_d1),
.Q(msms_d2),
.R(SR));
LUT6 #(
.INIT(64'h0000000030AA00AA))
msms_rst_i_i_1
(.I0(msms_rst_i),
.I1(scndry_out),
.I2(sda_cout_reg),
.I3(master_slave),
.I4(arb_lost_i_2_n_0),
.I5(arb_lost_i_3_n_0),
.O(msms_rst_i_i_1_n_0));
FDRE msms_rst_i_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(msms_rst_i_i_1_n_0),
.Q(msms_rst_i),
.R(1'b0));
LUT3 #(
.INIT(8'h08))
new_rcv_dta_i_i_1
(.I0(p_1_in),
.I1(scl_falling_edge),
.I2(Ro_prev),
.O(data_i2c_i0));
FDRE new_rcv_dta_i_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(data_i2c_i0),
.Q(New_rcv_dta),
.R(SR));
CARRY4 \next_scl_state1_inferred__0/i__carry
(.CI(1'b0),
.CO({next_scl_state10_out,\next_scl_state1_inferred__0/i__carry_n_1 ,\next_scl_state1_inferred__0/i__carry_n_2 ,\next_scl_state1_inferred__0/i__carry_n_3 }),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\NLW_next_scl_state1_inferred__0/i__carry_O_UNCONNECTED [3:0]),
.S(\timing_param_thdsta_i_reg[9] ));
CARRY4 \next_scl_state1_inferred__1/i__carry
(.CI(1'b0),
.CO({\next_scl_state1_inferred__1/i__carry_n_0 ,\next_scl_state1_inferred__1/i__carry_n_1 ,\next_scl_state1_inferred__1/i__carry_n_2 ,\next_scl_state1_inferred__1/i__carry_n_3 }),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\NLW_next_scl_state1_inferred__1/i__carry_O_UNCONNECTED [3:0]),
.S(\timing_param_tlow_i_reg[9] ));
LUT3 #(
.INIT(8'h80))
rdCntrFrmTxFifo_i_1
(.I0(earlyAckHdr),
.I1(callingReadAccess),
.I2(Tx_data_exists),
.O(rdCntrFrmTxFifo0));
LUT6 #(
.INIT(64'h222F2F2F22202020))
rdy_new_xmt_i_i_1
(.I0(shift_reg_ld_d1),
.I1(shift_reg_ld),
.I2(p_0_in_0),
.I3(Q[1]),
.I4(p_2_in),
.I5(rdy_new_xmt_i),
.O(rdy_new_xmt_i_i_1_n_0));
FDRE rdy_new_xmt_i_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(rdy_new_xmt_i_i_1_n_0),
.Q(rdy_new_xmt_i),
.R(SR));
FDRE ro_prev_d1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(Ro_prev),
.Q(ro_prev_d1),
.R(SR));
FDRE rsta_d1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(Q[3]),
.Q(rsta_d1),
.R(SR));
LUT5 #(
.INIT(32'hF0FF2020))
rsta_tx_under_prev_i_1
(.I0(Q[3]),
.I1(rsta_d1),
.I2(sr_i),
.I3(dtre_d1),
.I4(rsta_tx_under_prev),
.O(rsta_tx_under_prev_i_1_n_0));
FDRE rsta_tx_under_prev_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(rsta_tx_under_prev_i_1_n_0),
.Q(rsta_tx_under_prev),
.R(SR));
LUT4 #(
.INIT(16'h001D))
scl_cout_reg_i_1
(.I0(scl_state[2]),
.I1(scl_state[1]),
.I2(scl_state[3]),
.I3(Ro_prev),
.O(scl_cout_reg0));
FDSE scl_cout_reg_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(scl_cout_reg0),
.Q(scl_cout_reg),
.S(SR));
FDRE scl_f_edg_d1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(scl_falling_edge),
.Q(scl_f_edg_d1),
.R(SR));
FDRE scl_f_edg_d2_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(scl_f_edg_d1),
.Q(scl_f_edg_d2),
.R(SR));
FDRE scl_f_edg_d3_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(scl_f_edg_d2),
.Q(scl_f_edg_d3),
.R(SR));
LUT2 #(
.INIT(4'h2))
scl_falling_edge_i_1
(.I0(scl_rin_d1),
.I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 ),
.O(scl_falling_edge0));
FDRE scl_falling_edge_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(scl_falling_edge0),
.Q(scl_falling_edge),
.R(SR));
FDRE scl_rin_d1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 ),
.Q(scl_rin_d1),
.R(1'b0));
FDRE scl_rising_edge_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(scl_rising_edge0),
.Q(scl_rising_edge),
.R(SR));
LUT4 #(
.INIT(16'h0004))
scl_t_INST_0
(.I0(sda_setup),
.I1(scl_cout_reg),
.I2(rsta_tx_under_prev),
.I3(Ro_prev),
.O(scl_t));
LUT3 #(
.INIT(8'hB8))
sda_cout_reg_i_1
(.I0(sda_cout_reg_i_2_n_0),
.I1(sda_cout),
.I2(sda_cout_reg),
.O(sda_cout_reg_i_1_n_0));
LUT6 #(
.INIT(64'h00000000CAAA00FF))
sda_cout_reg_i_2
(.I0(sda_cout4_out),
.I1(sda_cout_reg_reg_0),
.I2(scl_state[0]),
.I3(scl_state[1]),
.I4(scl_state[2]),
.I5(scl_state[3]),
.O(sda_cout_reg_i_2_n_0));
LUT5 #(
.INIT(32'h45054141))
sda_cout_reg_i_3
(.I0(scl_state[3]),
.I1(scl_state[2]),
.I2(scl_state[0]),
.I3(sda_cout13_out),
.I4(scl_state[1]),
.O(sda_cout));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT3 #(
.INIT(8'h0E))
sda_cout_reg_i_4
(.I0(Q[3]),
.I1(\LEVEL_1_GEN.master_sda_reg_n_0 ),
.I2(sda_cout1),
.O(sda_cout4_out));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT4 #(
.INIT(16'h0040))
sda_cout_reg_i_5
(.I0(arb_lost),
.I1(stop_scl_reg),
.I2(sda_cout_reg_reg_0),
.I3(Q[3]),
.O(sda_cout13_out));
FDSE sda_cout_reg_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(sda_cout_reg_i_1_n_0),
.Q(sda_cout_reg),
.S(SR));
FDRE sda_rin_d1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(scndry_out),
.Q(sda_rin_d1),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT3 #(
.INIT(8'hB8))
sda_sample_i_1
(.I0(scndry_out),
.I1(scl_rising_edge),
.I2(sda_sample),
.O(sda_sample_i_1_n_0));
FDRE sda_sample_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(sda_sample_i_1_n_0),
.Q(sda_sample),
.R(SR));
CARRY4 \sda_setup0_inferred__0/i__carry
(.CI(1'b0),
.CO({\sda_setup0_inferred__0/i__carry_n_0 ,\sda_setup0_inferred__0/i__carry_n_1 ,\sda_setup0_inferred__0/i__carry_n_2 ,\sda_setup0_inferred__0/i__carry_n_3 }),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\NLW_sda_setup0_inferred__0/i__carry_O_UNCONNECTED [3:0]),
.S({\timing_param_tsudat_i_reg[9] [2],SETUP_CNT_n_8,\timing_param_tsudat_i_reg[9] [1:0]}));
LUT5 #(
.INIT(32'h55FD00FC))
sda_setup_i_1
(.I0(\sda_setup0_inferred__0/i__carry_n_0 ),
.I1(Tx_under_prev),
.I2(SETUP_CNT_n_0),
.I3(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 ),
.I4(sda_setup),
.O(sda_setup_i_1_n_0));
FDRE sda_setup_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(sda_setup_i_1_n_0),
.Q(sda_setup),
.R(SR));
LUT5 #(
.INIT(32'h0000EFE0))
sda_t_INST_0
(.I0(arb_lost),
.I1(sda_cout_reg),
.I2(master_slave),
.I3(slave_sda_reg_n_0),
.I4(stop_scl_reg),
.O(sda_t));
LUT4 #(
.INIT(16'hEAAA))
shift_reg_en_i_1
(.I0(shift_reg_en_i_2_n_0),
.I1(master_slave),
.I2(p_2_in),
.I3(scl_rising_edge),
.O(shift_reg_en0));
LUT5 #(
.INIT(32'h55404040))
shift_reg_en_i_2
(.I0(detect_start),
.I1(p_0_in_0),
.I2(scl_f_edg_d2),
.I3(scl_rising_edge),
.I4(p_1_in6_in),
.O(shift_reg_en_i_2_n_0));
FDRE shift_reg_en_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(shift_reg_en0),
.Q(shift_reg_en),
.R(SR));
FDRE shift_reg_ld_d1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(shift_reg_ld),
.Q(shift_reg_ld_d1),
.R(SR));
LUT6 #(
.INIT(64'hFFFFFEEEFEEEFEEE))
shift_reg_ld_i_2
(.I0(\FSM_onehot_state_reg_n_0_[6] ),
.I1(Tx_under_prev),
.I2(master_slave),
.I3(p_4_in),
.I4(p_1_in6_in),
.I5(detect_start),
.O(shift_reg_ld_i_2_n_0));
FDRE shift_reg_ld_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(shift_reg_ld0),
.Q(shift_reg_ld),
.R(SR));
FDSE slave_sda_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(I2CDATA_REG_n_9),
.Q(slave_sda_reg_n_0),
.S(SR));
LUT6 #(
.INIT(64'h00000000BA8A0000))
sm_stop_i_1
(.I0(sm_stop_reg_n_0),
.I1(\FSM_onehot_state[6]_i_5_n_0 ),
.I2(sm_stop),
.I3(master_slave),
.I4(Q[0]),
.I5(detect_stop_reg_n_0),
.O(sm_stop_i_1_n_0));
LUT5 #(
.INIT(32'h40404000))
sm_stop_i_2
(.I0(arb_lost),
.I1(master_slave),
.I2(sda_sample),
.I3(\FSM_onehot_state_reg_n_0_[6] ),
.I4(p_1_in0_in),
.O(sm_stop));
FDRE sm_stop_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(sm_stop_i_1_n_0),
.Q(sm_stop_reg_n_0),
.R(1'b0));
FDRE srw_i_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(I2CHEADER_REG_n_11),
.Q(\sr_i_reg[4] [1]),
.R(1'b0));
LUT6 #(
.INIT(64'h2800FFFF28000000))
stop_scl_reg_i_1
(.I0(sda_cout1),
.I1(scl_state[1]),
.I2(scl_state[0]),
.I3(stop_scl_reg_i_3_n_0),
.I4(stop_scl),
.I5(stop_scl_reg),
.O(stop_scl_reg_i_1_n_0));
LUT5 #(
.INIT(32'h0000000E))
stop_scl_reg_i_2
(.I0(gen_stop),
.I1(sm_stop_reg_n_0),
.I2(\FSM_onehot_state_reg_n_0_[6] ),
.I3(p_1_in0_in),
.I4(p_1_in),
.O(sda_cout1));
LUT2 #(
.INIT(4'h2))
stop_scl_reg_i_3
(.I0(scl_state[2]),
.I1(scl_state[3]),
.O(stop_scl_reg_i_3_n_0));
LUT5 #(
.INIT(32'h40555F55))
stop_scl_reg_i_4
(.I0(scl_state[3]),
.I1(sda_cout13_out),
.I2(scl_state[2]),
.I3(scl_state[0]),
.I4(scl_state[1]),
.O(stop_scl));
FDRE stop_scl_reg_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(stop_scl_reg_i_1_n_0),
.Q(stop_scl_reg),
.R(SR));
FDRE tx_under_prev_d1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(Tx_under_prev),
.Q(tx_under_prev_d1),
.R(SR));
LUT5 #(
.INIT(32'hAABAAAAA))
tx_under_prev_i_i_1
(.I0(tx_under_prev_i0),
.I1(p_4_in),
.I2(sr_i),
.I3(p_1_in6_in),
.I4(Tx_under_prev),
.O(tx_under_prev_i_i_1_n_0));
LUT6 #(
.INIT(64'h0000900000000000))
tx_under_prev_i_i_2
(.I0(Aas),
.I1(\sr_i_reg[4] [1]),
.I2(tx_under_prev_i_i_3_n_0),
.I3(sr_i),
.I4(gen_stop),
.I5(scl_falling_edge),
.O(tx_under_prev_i0));
LUT2 #(
.INIT(4'hE))
tx_under_prev_i_i_3
(.I0(p_1_in0_in),
.I1(\FSM_onehot_state_reg_n_0_[6] ),
.O(tx_under_prev_i_i_3_n_0));
FDRE tx_under_prev_i_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(tx_under_prev_i_i_1_n_0),
.Q(Tx_under_prev),
.R(SR));
LUT6 #(
.INIT(64'hE200E2000000E200))
txer_edge_i_1
(.I0(D[2]),
.I1(txer_i),
.I2(sda_sample),
.I3(Q[0]),
.I4(scl_f_edg_d2),
.I5(scl_falling_edge),
.O(txer_edge_i_1_n_0));
LUT4 #(
.INIT(16'hAAA8))
txer_edge_i_2
(.I0(scl_falling_edge),
.I1(p_1_in0_in),
.I2(\FSM_onehot_state_reg_n_0_[6] ),
.I3(p_1_in),
.O(txer_i));
FDRE txer_edge_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(txer_edge_i_1_n_0),
.Q(D[2]),
.R(1'b0));
LUT6 #(
.INIT(64'hBBBBBBBF88888880))
txer_i_i_1
(.I0(sda_sample),
.I1(scl_falling_edge),
.I2(p_1_in0_in),
.I3(\FSM_onehot_state_reg_n_0_[6] ),
.I4(p_1_in),
.I5(txer_i_reg_n_0),
.O(txer_i_i_1_n_0));
FDRE txer_i_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(txer_i_i_1_n_0),
.Q(txer_i_reg_n_0),
.R(SR));
endmodule
(* ORIG_REF_NAME = "interrupt_control" *)
module system_axi_iic_0_0_interrupt_control
(irpt_wrack_d1,
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0 ,
p_1_in17_in,
p_1_in14_in,
p_1_in11_in,
p_1_in8_in,
p_1_in5_in,
p_1_in2_in,
p_1_in,
ipif_glbl_irpt_enable_reg,
iic2intc_irpt,
Q,
SR,
irpt_wrack,
s_axi_aclk,
Bus_RNW_reg_reg,
Bus_RNW_reg_reg_0,
Bus_RNW_reg_reg_1,
Bus_RNW_reg_reg_2,
Bus_RNW_reg_reg_3,
Bus_RNW_reg_reg_4,
Bus_RNW_reg_reg_5,
Bus_RNW_reg_reg_6,
\GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg[7] ,
E,
s_axi_wdata);
output irpt_wrack_d1;
output \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0 ;
output p_1_in17_in;
output p_1_in14_in;
output p_1_in11_in;
output p_1_in8_in;
output p_1_in5_in;
output p_1_in2_in;
output p_1_in;
output ipif_glbl_irpt_enable_reg;
output iic2intc_irpt;
output [7:0]Q;
input [0:0]SR;
input irpt_wrack;
input s_axi_aclk;
input Bus_RNW_reg_reg;
input Bus_RNW_reg_reg_0;
input Bus_RNW_reg_reg_1;
input Bus_RNW_reg_reg_2;
input Bus_RNW_reg_reg_3;
input Bus_RNW_reg_reg_4;
input Bus_RNW_reg_reg_5;
input Bus_RNW_reg_reg_6;
input \GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg[7] ;
input [0:0]E;
input [7:0]s_axi_wdata;
wire Bus_RNW_reg_reg;
wire Bus_RNW_reg_reg_0;
wire Bus_RNW_reg_reg_1;
wire Bus_RNW_reg_reg_2;
wire Bus_RNW_reg_reg_3;
wire Bus_RNW_reg_reg_4;
wire Bus_RNW_reg_reg_5;
wire Bus_RNW_reg_reg_6;
wire [0:0]E;
wire \GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg[7] ;
wire \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0 ;
wire [7:0]Q;
wire [0:0]SR;
wire iic2intc_irpt;
wire iic2intc_irpt_INST_0_i_1_n_0;
wire iic2intc_irpt_INST_0_i_2_n_0;
wire iic2intc_irpt_INST_0_i_3_n_0;
wire iic2intc_irpt_INST_0_i_4_n_0;
wire ipif_glbl_irpt_enable_reg;
wire irpt_wrack;
wire irpt_wrack_d1;
wire p_1_in;
wire p_1_in11_in;
wire p_1_in14_in;
wire p_1_in17_in;
wire p_1_in2_in;
wire p_1_in5_in;
wire p_1_in8_in;
wire s_axi_aclk;
wire [7:0]s_axi_wdata;
FDRE \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Bus_RNW_reg_reg),
.Q(\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0 ),
.R(SR));
FDRE \GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Bus_RNW_reg_reg_0),
.Q(p_1_in17_in),
.R(SR));
FDRE \GEN_IP_IRPT_STATUS_REG[2].GEN_REG_STATUS.ip_irpt_status_reg_reg[2]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Bus_RNW_reg_reg_1),
.Q(p_1_in14_in),
.R(SR));
FDRE \GEN_IP_IRPT_STATUS_REG[3].GEN_REG_STATUS.ip_irpt_status_reg_reg[3]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Bus_RNW_reg_reg_2),
.Q(p_1_in11_in),
.R(SR));
FDRE \GEN_IP_IRPT_STATUS_REG[4].GEN_REG_STATUS.ip_irpt_status_reg_reg[4]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Bus_RNW_reg_reg_3),
.Q(p_1_in8_in),
.R(SR));
FDRE \GEN_IP_IRPT_STATUS_REG[5].GEN_REG_STATUS.ip_irpt_status_reg_reg[5]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Bus_RNW_reg_reg_4),
.Q(p_1_in5_in),
.R(SR));
FDRE \GEN_IP_IRPT_STATUS_REG[6].GEN_REG_STATUS.ip_irpt_status_reg_reg[6]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Bus_RNW_reg_reg_5),
.Q(p_1_in2_in),
.R(SR));
FDRE \GEN_IP_IRPT_STATUS_REG[7].GEN_REG_STATUS.ip_irpt_status_reg_reg[7]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Bus_RNW_reg_reg_6),
.Q(p_1_in),
.R(SR));
LUT5 #(
.INIT(32'hAAAAA8AA))
iic2intc_irpt_INST_0
(.I0(ipif_glbl_irpt_enable_reg),
.I1(iic2intc_irpt_INST_0_i_1_n_0),
.I2(iic2intc_irpt_INST_0_i_2_n_0),
.I3(iic2intc_irpt_INST_0_i_3_n_0),
.I4(iic2intc_irpt_INST_0_i_4_n_0),
.O(iic2intc_irpt));
LUT4 #(
.INIT(16'hF888))
iic2intc_irpt_INST_0_i_1
(.I0(Q[4]),
.I1(p_1_in8_in),
.I2(Q[2]),
.I3(p_1_in14_in),
.O(iic2intc_irpt_INST_0_i_1_n_0));
LUT4 #(
.INIT(16'hF888))
iic2intc_irpt_INST_0_i_2
(.I0(Q[3]),
.I1(p_1_in11_in),
.I2(Q[6]),
.I3(p_1_in2_in),
.O(iic2intc_irpt_INST_0_i_2_n_0));
LUT4 #(
.INIT(16'h0777))
iic2intc_irpt_INST_0_i_3
(.I0(Q[5]),
.I1(p_1_in5_in),
.I2(Q[7]),
.I3(p_1_in),
.O(iic2intc_irpt_INST_0_i_3_n_0));
LUT4 #(
.INIT(16'hF888))
iic2intc_irpt_INST_0_i_4
(.I0(Q[1]),
.I1(p_1_in17_in),
.I2(Q[0]),
.I3(\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0 ),
.O(iic2intc_irpt_INST_0_i_4_n_0));
FDRE \ip_irpt_enable_reg_reg[0]
(.C(s_axi_aclk),
.CE(E),
.D(s_axi_wdata[0]),
.Q(Q[0]),
.R(SR));
FDRE \ip_irpt_enable_reg_reg[1]
(.C(s_axi_aclk),
.CE(E),
.D(s_axi_wdata[1]),
.Q(Q[1]),
.R(SR));
FDRE \ip_irpt_enable_reg_reg[2]
(.C(s_axi_aclk),
.CE(E),
.D(s_axi_wdata[2]),
.Q(Q[2]),
.R(SR));
FDRE \ip_irpt_enable_reg_reg[3]
(.C(s_axi_aclk),
.CE(E),
.D(s_axi_wdata[3]),
.Q(Q[3]),
.R(SR));
FDRE \ip_irpt_enable_reg_reg[4]
(.C(s_axi_aclk),
.CE(E),
.D(s_axi_wdata[4]),
.Q(Q[4]),
.R(SR));
FDRE \ip_irpt_enable_reg_reg[5]
(.C(s_axi_aclk),
.CE(E),
.D(s_axi_wdata[5]),
.Q(Q[5]),
.R(SR));
FDRE \ip_irpt_enable_reg_reg[6]
(.C(s_axi_aclk),
.CE(E),
.D(s_axi_wdata[6]),
.Q(Q[6]),
.R(SR));
FDRE \ip_irpt_enable_reg_reg[7]
(.C(s_axi_aclk),
.CE(E),
.D(s_axi_wdata[7]),
.Q(Q[7]),
.R(SR));
FDRE ipif_glbl_irpt_enable_reg_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg[7] ),
.Q(ipif_glbl_irpt_enable_reg),
.R(SR));
FDRE irpt_wrack_d1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(irpt_wrack),
.Q(irpt_wrack_d1),
.R(SR));
endmodule
(* ORIG_REF_NAME = "reg_interface" *)
module system_axi_iic_0_0_reg_interface
(IIC2Bus_IntrEvent,
Q,
D,
Tx_fifo_wr,
Tx_fifo_rd,
Tx_fifo_rst,
new_rcv_dta_d1,
Rc_fifo_wr,
Rc_fifo_rd,
dtre_d1_reg,
gpo,
Msms_set,
state122_out,
slave_sda_reg,
S,
\FSM_sequential_scl_state_reg[0] ,
sda_cout_reg_reg,
sda_cout_reg_reg_0,
\FSM_sequential_scl_state_reg[0]_0 ,
\s_axi_rdata_i_reg[7] ,
\FSM_sequential_scl_state_reg[3] ,
\FSM_sequential_scl_state_reg[3]_0 ,
\q_int_reg[0] ,
\s_axi_rdata_i_reg[5] ,
\FSM_sequential_scl_state_reg[2] ,
\FSM_sequential_scl_state_reg[2]_0 ,
\FSM_sequential_scl_state_reg[1] ,
\FSM_sequential_scl_state_reg[1]_0 ,
sda_setup_reg,
\s_axi_rdata_i_reg[8] ,
\FSM_onehot_state_reg[4] ,
D_0,
Data_Exists_DFF,
SR,
txak,
D_1,
Data_Exists_DFF_0,
\cr_i_reg[5]_0 ,
\q_int_reg[9] ,
\FSM_sequential_scl_state_reg[0]_1 ,
\s_axi_rdata_i_reg[0] ,
\s_axi_rdata_i_reg[6] ,
\s_axi_rdata_i_reg[7]_0 ,
\s_axi_rdata_i_reg[9] ,
\s_axi_rdata_i_reg[8]_0 ,
\s_axi_rdata_i_reg[7]_1 ,
\s_axi_rdata_i_reg[6]_0 ,
\s_axi_rdata_i_reg[5]_0 ,
\s_axi_rdata_i_reg[4] ,
\s_axi_rdata_i_reg[3] ,
\RD_FIFO_CNTRL.ro_prev_i_reg_0 ,
\s_axi_rdata_i_reg[3]_0 ,
\s_axi_rdata_i_reg[3]_1 ,
\s_axi_rdata_i_reg[2] ,
\s_axi_rdata_i_reg[2]_0 ,
\s_axi_rdata_i_reg[2]_1 ,
\s_axi_rdata_i_reg[1] ,
\s_axi_rdata_i_reg[1]_0 ,
\s_axi_rdata_i_reg[1]_1 ,
\s_axi_rdata_i_reg[0]_0 ,
\Addr_Counters[0].FDRE_I ,
D_2,
\Addr_Counters[0].FDRE_I_0 ,
\Addr_Counters[0].FDRE_I_1 ,
firstDynStartSeen_reg,
Bus2IIC_Reset,
\Addr_Counters[3].FDRE_I ,
s_axi_aclk,
p_6_out,
Bus2IIC_WrCE,
rdy_new_xmt_i,
New_rcv_dta,
new_rcv_dta_i_reg,
Bus2IIC_RdCE,
Data_Exists_DFF_1,
Aas,
\GEN_BKEND_CE_REGISTERS[26].ce_out_i_reg[26] ,
master_slave,
\q_int_reg[0]_0 ,
\q_int_reg[0]_1 ,
\data_int_reg[7] ,
s_axi_wdata,
\FSM_sequential_scl_state_reg[2]_1 ,
\FSM_sequential_scl_state_reg[0]_2 ,
rdCntrFrmTxFifo,
Tx_fifo_rd_d,
\Addr_Counters[1].FDRE_I ,
Data_Exists_DFF_2,
Tx_fifo_wr_d,
Data_Exists_DFF_3,
\rdByteCntr_reg[2] ,
earlyAckDataState,
dynamic_MSMS,
Tx_data_exists,
firstDynStartSeen,
\Addr_Counters[1].FDRE_I_0 ,
CO,
stop_scl_reg,
\timing_param_tsusto_i_reg[9]_0 ,
\timing_param_tsusta_i_reg[9]_0 ,
arb_lost,
\bus2ip_addr_i_reg[6] ,
Rc_addr,
Tx_fifo_data,
Rc_fifo_wr_d,
Rc_fifo_rd_d,
\Addr_Counters[1].FDRE_I_1 ,
Rc_Data_Exists,
\GEN_BKEND_CE_REGISTERS[17].ce_out_i_reg[17] ,
al_i_reg);
output [0:7]IIC2Bus_IntrEvent;
output [4:0]Q;
output [0:0]D;
output Tx_fifo_wr;
output Tx_fifo_rd;
output Tx_fifo_rst;
output new_rcv_dta_d1;
output Rc_fifo_wr;
output Rc_fifo_rd;
output [2:0]dtre_d1_reg;
output [0:0]gpo;
output Msms_set;
output state122_out;
output slave_sda_reg;
output [3:0]S;
output [7:0]\FSM_sequential_scl_state_reg[0] ;
output [3:0]sda_cout_reg_reg;
output [7:0]sda_cout_reg_reg_0;
output [3:0]\FSM_sequential_scl_state_reg[0]_0 ;
output [3:0]\s_axi_rdata_i_reg[7] ;
output [3:0]\FSM_sequential_scl_state_reg[3] ;
output [3:0]\FSM_sequential_scl_state_reg[3]_0 ;
output [3:0]\q_int_reg[0] ;
output [1:0]\s_axi_rdata_i_reg[5] ;
output [3:0]\FSM_sequential_scl_state_reg[2] ;
output [0:0]\FSM_sequential_scl_state_reg[2]_0 ;
output [3:0]\FSM_sequential_scl_state_reg[1] ;
output [0:0]\FSM_sequential_scl_state_reg[1]_0 ;
output [2:0]sda_setup_reg;
output [8:0]\s_axi_rdata_i_reg[8] ;
output \FSM_onehot_state_reg[4] ;
output D_0;
output Data_Exists_DFF;
output [0:0]SR;
output txak;
output D_1;
output Data_Exists_DFF_0;
output \cr_i_reg[5]_0 ;
output \q_int_reg[9] ;
output \FSM_sequential_scl_state_reg[0]_1 ;
output \s_axi_rdata_i_reg[0] ;
output \s_axi_rdata_i_reg[6] ;
output \s_axi_rdata_i_reg[7]_0 ;
output \s_axi_rdata_i_reg[9] ;
output \s_axi_rdata_i_reg[8]_0 ;
output \s_axi_rdata_i_reg[7]_1 ;
output \s_axi_rdata_i_reg[6]_0 ;
output \s_axi_rdata_i_reg[5]_0 ;
output \s_axi_rdata_i_reg[4] ;
output \s_axi_rdata_i_reg[3] ;
output [3:0]\RD_FIFO_CNTRL.ro_prev_i_reg_0 ;
output \s_axi_rdata_i_reg[3]_0 ;
output \s_axi_rdata_i_reg[3]_1 ;
output \s_axi_rdata_i_reg[2] ;
output \s_axi_rdata_i_reg[2]_0 ;
output \s_axi_rdata_i_reg[2]_1 ;
output \s_axi_rdata_i_reg[1] ;
output \s_axi_rdata_i_reg[1]_0 ;
output \s_axi_rdata_i_reg[1]_1 ;
output \s_axi_rdata_i_reg[0]_0 ;
output \Addr_Counters[0].FDRE_I ;
output D_2;
output \Addr_Counters[0].FDRE_I_0 ;
output \Addr_Counters[0].FDRE_I_1 ;
output firstDynStartSeen_reg;
input Bus2IIC_Reset;
input \Addr_Counters[3].FDRE_I ;
input s_axi_aclk;
input p_6_out;
input [11:0]Bus2IIC_WrCE;
input rdy_new_xmt_i;
input New_rcv_dta;
input new_rcv_dta_i_reg;
input [0:0]Bus2IIC_RdCE;
input Data_Exists_DFF_1;
input Aas;
input \GEN_BKEND_CE_REGISTERS[26].ce_out_i_reg[26] ;
input master_slave;
input [9:0]\q_int_reg[0]_0 ;
input [6:0]\q_int_reg[0]_1 ;
input [7:0]\data_int_reg[7] ;
input [9:0]s_axi_wdata;
input \FSM_sequential_scl_state_reg[2]_1 ;
input \FSM_sequential_scl_state_reg[0]_2 ;
input rdCntrFrmTxFifo;
input Tx_fifo_rd_d;
input \Addr_Counters[1].FDRE_I ;
input Data_Exists_DFF_2;
input Tx_fifo_wr_d;
input [5:0]Data_Exists_DFF_3;
input \rdByteCntr_reg[2] ;
input earlyAckDataState;
input [0:0]dynamic_MSMS;
input Tx_data_exists;
input firstDynStartSeen;
input \Addr_Counters[1].FDRE_I_0 ;
input [0:0]CO;
input stop_scl_reg;
input [0:0]\timing_param_tsusto_i_reg[9]_0 ;
input [0:0]\timing_param_tsusta_i_reg[9]_0 ;
input arb_lost;
input [4:0]\bus2ip_addr_i_reg[6] ;
input [0:3]Rc_addr;
input [3:0]Tx_fifo_data;
input Rc_fifo_wr_d;
input Rc_fifo_rd_d;
input \Addr_Counters[1].FDRE_I_1 ;
input Rc_Data_Exists;
input [1:0]\GEN_BKEND_CE_REGISTERS[17].ce_out_i_reg[17] ;
input [4:0]al_i_reg;
wire Aas;
wire \Addr_Counters[0].FDRE_I ;
wire \Addr_Counters[0].FDRE_I_0 ;
wire \Addr_Counters[0].FDRE_I_1 ;
wire \Addr_Counters[1].FDRE_I ;
wire \Addr_Counters[1].FDRE_I_0 ;
wire \Addr_Counters[1].FDRE_I_1 ;
wire \Addr_Counters[3].FDRE_I ;
wire [0:0]Bus2IIC_RdCE;
wire Bus2IIC_Reset;
wire [11:0]Bus2IIC_WrCE;
wire [0:0]CO;
wire [0:6]Cr;
wire [0:0]D;
wire D_0;
wire D_1;
wire D_2;
wire Data_Exists_DFF;
wire Data_Exists_DFF_0;
wire Data_Exists_DFF_1;
wire Data_Exists_DFF_2;
wire [5:0]Data_Exists_DFF_3;
wire \FSM_onehot_state_reg[4] ;
wire [7:0]\FSM_sequential_scl_state_reg[0] ;
wire [3:0]\FSM_sequential_scl_state_reg[0]_0 ;
wire \FSM_sequential_scl_state_reg[0]_1 ;
wire \FSM_sequential_scl_state_reg[0]_2 ;
wire [3:0]\FSM_sequential_scl_state_reg[1] ;
wire [0:0]\FSM_sequential_scl_state_reg[1]_0 ;
wire [3:0]\FSM_sequential_scl_state_reg[2] ;
wire [0:0]\FSM_sequential_scl_state_reg[2]_0 ;
wire \FSM_sequential_scl_state_reg[2]_1 ;
wire [3:0]\FSM_sequential_scl_state_reg[3] ;
wire [3:0]\FSM_sequential_scl_state_reg[3]_0 ;
wire [1:0]\GEN_BKEND_CE_REGISTERS[17].ce_out_i_reg[17] ;
wire \GEN_BKEND_CE_REGISTERS[26].ce_out_i_reg[26] ;
wire [0:7]IIC2Bus_IntrEvent;
wire Msms_set;
wire New_rcv_dta;
wire [4:0]Q;
wire [3:0]\RD_FIFO_CNTRL.ro_prev_i_reg_0 ;
wire Rc_Data_Exists;
wire [0:3]Rc_addr;
wire Rc_fifo_rd;
wire Rc_fifo_rd_d;
wire Rc_fifo_wr;
wire Rc_fifo_wr_d;
wire [3:0]S;
wire [0:0]SR;
wire Tx_data_exists;
wire [3:0]Tx_fifo_data;
wire Tx_fifo_rd;
wire Tx_fifo_rd_d;
wire Tx_fifo_rst;
wire Tx_fifo_wr;
wire Tx_fifo_wr_d;
wire [7:1]adr_i;
wire [4:0]al_i_reg;
wire arb_lost;
wire [4:0]\bus2ip_addr_i_reg[6] ;
wire \cr_i[2]_i_1_n_0 ;
wire \cr_i[2]_i_2_n_0 ;
wire \cr_i_reg[5]_0 ;
wire [7:0]\data_int_reg[7] ;
wire [2:0]dtre_d1_reg;
wire [0:0]dynamic_MSMS;
wire earlyAckDataState;
wire firstDynStartSeen;
wire firstDynStartSeen_i_2_n_0;
wire firstDynStartSeen_reg;
wire [0:0]gpo;
wire master_slave;
wire msms_d1;
wire msms_set_i_i_1_n_0;
wire new_rcv_dta_d1;
wire new_rcv_dta_i_reg;
wire p_6_out;
wire [3:0]\q_int_reg[0] ;
wire [9:0]\q_int_reg[0]_0 ;
wire [6:0]\q_int_reg[0]_1 ;
wire \q_int_reg[9] ;
wire \rdByteCntr_reg[2] ;
wire rdCntrFrmTxFifo;
wire rdy_new_xmt_i;
wire s_axi_aclk;
wire \s_axi_rdata_i[1]_i_10_n_0 ;
wire \s_axi_rdata_i[2]_i_6_n_0 ;
wire \s_axi_rdata_i[3]_i_9_n_0 ;
wire \s_axi_rdata_i[4]_i_8_n_0 ;
wire \s_axi_rdata_i[5]_i_8_n_0 ;
wire \s_axi_rdata_i[6]_i_8_n_0 ;
wire \s_axi_rdata_i[7]_i_8_n_0 ;
wire \s_axi_rdata_i[8]_i_3_n_0 ;
wire \s_axi_rdata_i[8]_i_4_n_0 ;
wire \s_axi_rdata_i[9]_i_4_n_0 ;
wire \s_axi_rdata_i[9]_i_5_n_0 ;
wire \s_axi_rdata_i_reg[0] ;
wire \s_axi_rdata_i_reg[0]_0 ;
wire \s_axi_rdata_i_reg[1] ;
wire \s_axi_rdata_i_reg[1]_0 ;
wire \s_axi_rdata_i_reg[1]_1 ;
wire \s_axi_rdata_i_reg[2] ;
wire \s_axi_rdata_i_reg[2]_0 ;
wire \s_axi_rdata_i_reg[2]_1 ;
wire \s_axi_rdata_i_reg[3] ;
wire \s_axi_rdata_i_reg[3]_0 ;
wire \s_axi_rdata_i_reg[3]_1 ;
wire \s_axi_rdata_i_reg[4] ;
wire [1:0]\s_axi_rdata_i_reg[5] ;
wire \s_axi_rdata_i_reg[5]_0 ;
wire \s_axi_rdata_i_reg[6] ;
wire \s_axi_rdata_i_reg[6]_0 ;
wire [3:0]\s_axi_rdata_i_reg[7] ;
wire \s_axi_rdata_i_reg[7]_0 ;
wire \s_axi_rdata_i_reg[7]_1 ;
wire [8:0]\s_axi_rdata_i_reg[8] ;
wire \s_axi_rdata_i_reg[8]_0 ;
wire \s_axi_rdata_i_reg[9] ;
wire [9:0]s_axi_wdata;
wire [3:0]sda_cout_reg_reg;
wire [7:0]sda_cout_reg_reg_0;
wire [2:0]sda_setup_reg;
wire slave_sda_i_3_n_0;
wire slave_sda_i_4_n_0;
wire slave_sda_reg;
wire [1:7]sr_i;
wire state122_out;
wire stop_scl_reg;
wire [9:0]timing_param_tbuf_i;
wire [9:0]timing_param_thddat_i;
wire [9:1]timing_param_thdsta_i;
wire [9:8]timing_param_thigh_i;
wire [9:1]timing_param_tlow_i;
wire [9:9]timing_param_tsudat_i;
wire [9:0]timing_param_tsusta_i;
wire [0:0]\timing_param_tsusta_i_reg[9]_0 ;
wire [9:8]timing_param_tsusto_i;
wire [0:0]\timing_param_tsusto_i_reg[9]_0 ;
wire txak;
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT2 #(
.INIT(4'h2))
\Addr_Counters[0].MUXCY_L_I_i_4
(.I0(Tx_fifo_wr),
.I1(Tx_fifo_wr_d),
.O(\Addr_Counters[0].FDRE_I ));
LUT2 #(
.INIT(4'h2))
\Addr_Counters[0].MUXCY_L_I_i_4__0
(.I0(Rc_fifo_rd),
.I1(Rc_fifo_rd_d),
.O(\Addr_Counters[0].FDRE_I_1 ));
LUT2 #(
.INIT(4'h2))
\Addr_Counters[0].MUXCY_L_I_i_5
(.I0(Rc_fifo_wr),
.I1(Rc_fifo_wr_d),
.O(\Addr_Counters[0].FDRE_I_0 ));
LUT6 #(
.INIT(64'hFFFFBABB0000AAAA))
Data_Exists_DFF_i_1
(.I0(Data_Exists_DFF),
.I1(rdCntrFrmTxFifo),
.I2(Tx_fifo_rd_d),
.I3(Tx_fifo_rd),
.I4(\Addr_Counters[1].FDRE_I ),
.I5(Data_Exists_DFF_2),
.O(D_0));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT5 #(
.INIT(32'hFFF20022))
Data_Exists_DFF_i_1__0
(.I0(Tx_fifo_wr),
.I1(Tx_fifo_wr_d),
.I2(Data_Exists_DFF_0),
.I3(\Addr_Counters[1].FDRE_I_0 ),
.I4(Tx_data_exists),
.O(D_1));
LUT6 #(
.INIT(64'hFFFFF2FF00002222))
Data_Exists_DFF_i_1__1
(.I0(Rc_fifo_wr),
.I1(Rc_fifo_wr_d),
.I2(Rc_fifo_rd_d),
.I3(Rc_fifo_rd),
.I4(\Addr_Counters[1].FDRE_I_1 ),
.I5(Rc_Data_Exists),
.O(D_2));
LUT4 #(
.INIT(16'hFFF4))
Data_Exists_DFF_i_2
(.I0(Tx_fifo_wr_d),
.I1(Tx_fifo_wr),
.I2(Bus2IIC_Reset),
.I3(Tx_fifo_rst),
.O(Data_Exists_DFF));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT3 #(
.INIT(8'h0D))
Data_Exists_DFF_i_2__0
(.I0(Tx_fifo_rd),
.I1(Tx_fifo_rd_d),
.I2(rdCntrFrmTxFifo),
.O(Data_Exists_DFF_0));
FDRE \FIFO_GEN_DTR.IIC2Bus_IntrEvent_reg[7]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\Addr_Counters[3].FDRE_I ),
.Q(IIC2Bus_IntrEvent[7]),
.R(Bus2IIC_Reset));
FDRE \FIFO_GEN_DTR.Tx_fifo_rd_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(rdy_new_xmt_i),
.Q(Tx_fifo_rd),
.R(Bus2IIC_Reset));
FDSE \FIFO_GEN_DTR.Tx_fifo_rst_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(Cr[6]),
.Q(Tx_fifo_rst),
.S(Bus2IIC_Reset));
FDRE \FIFO_GEN_DTR.Tx_fifo_wr_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(Bus2IIC_WrCE[10]),
.Q(Tx_fifo_wr),
.R(Bus2IIC_Reset));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT2 #(
.INIT(4'h2))
\FSM_onehot_state[0]_i_2
(.I0(slave_sda_reg),
.I1(master_slave),
.O(state122_out));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT4 #(
.INIT(16'h88B8))
\FSM_onehot_state[4]_i_4
(.I0(Q[2]),
.I1(master_slave),
.I2(\data_int_reg[7] [0]),
.I3(slave_sda_reg),
.O(\FSM_onehot_state_reg[4] ));
LUT1 #(
.INIT(2'h1))
\FSM_sequential_scl_state[3]_i_1
(.I0(Q[0]),
.O(SR));
LUT5 #(
.INIT(32'hB8BBB888))
\FSM_sequential_scl_state[3]_i_4
(.I0(\timing_param_tsusta_i_reg[9]_0 ),
.I1(Q[3]),
.I2(\timing_param_tsusto_i_reg[9]_0 ),
.I3(stop_scl_reg),
.I4(CO),
.O(\FSM_sequential_scl_state_reg[0]_1 ));
FDRE \GPO_GEN.gpo_i_reg[31]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_BKEND_CE_REGISTERS[26].ce_out_i_reg[26] ),
.Q(gpo),
.R(Bus2IIC_Reset));
FDRE \IIC2Bus_IntrEvent_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(al_i_reg[4]),
.Q(IIC2Bus_IntrEvent[0]),
.R(Bus2IIC_Reset));
FDRE \IIC2Bus_IntrEvent_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(al_i_reg[3]),
.Q(IIC2Bus_IntrEvent[1]),
.R(Bus2IIC_Reset));
FDRE \IIC2Bus_IntrEvent_reg[2]
(.C(s_axi_aclk),
.CE(1'b1),
.D(al_i_reg[2]),
.Q(IIC2Bus_IntrEvent[2]),
.R(Bus2IIC_Reset));
FDRE \IIC2Bus_IntrEvent_reg[3]
(.C(s_axi_aclk),
.CE(1'b1),
.D(D),
.Q(IIC2Bus_IntrEvent[3]),
.R(Bus2IIC_Reset));
FDRE \IIC2Bus_IntrEvent_reg[4]
(.C(s_axi_aclk),
.CE(1'b1),
.D(al_i_reg[1]),
.Q(IIC2Bus_IntrEvent[4]),
.R(Bus2IIC_Reset));
FDRE \IIC2Bus_IntrEvent_reg[5]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Aas),
.Q(IIC2Bus_IntrEvent[5]),
.R(Bus2IIC_Reset));
FDRE \IIC2Bus_IntrEvent_reg[6]
(.C(s_axi_aclk),
.CE(1'b1),
.D(al_i_reg[0]),
.Q(IIC2Bus_IntrEvent[6]),
.R(Bus2IIC_Reset));
LUT3 #(
.INIT(8'hEA))
\LEVEL_1_GEN.master_sda_i_2
(.I0(Cr[3]),
.I1(\rdByteCntr_reg[2] ),
.I2(earlyAckDataState),
.O(txak));
FDRE \RD_FIFO_CNTRL.Rc_fifo_rd_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(Bus2IIC_RdCE),
.Q(Rc_fifo_rd),
.R(Bus2IIC_Reset));
FDRE \RD_FIFO_CNTRL.Rc_fifo_wr_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(new_rcv_dta_i_reg),
.Q(Rc_fifo_wr),
.R(Bus2IIC_Reset));
FDRE \RD_FIFO_CNTRL.rc_fifo_pirq_i_reg[4]
(.C(s_axi_aclk),
.CE(Bus2IIC_WrCE[8]),
.D(s_axi_wdata[3]),
.Q(\RD_FIFO_CNTRL.ro_prev_i_reg_0 [3]),
.R(Bus2IIC_Reset));
FDRE \RD_FIFO_CNTRL.rc_fifo_pirq_i_reg[5]
(.C(s_axi_aclk),
.CE(Bus2IIC_WrCE[8]),
.D(s_axi_wdata[2]),
.Q(\RD_FIFO_CNTRL.ro_prev_i_reg_0 [2]),
.R(Bus2IIC_Reset));
FDRE \RD_FIFO_CNTRL.rc_fifo_pirq_i_reg[6]
(.C(s_axi_aclk),
.CE(Bus2IIC_WrCE[8]),
.D(s_axi_wdata[1]),
.Q(\RD_FIFO_CNTRL.ro_prev_i_reg_0 [1]),
.R(Bus2IIC_Reset));
FDRE \RD_FIFO_CNTRL.rc_fifo_pirq_i_reg[7]
(.C(s_axi_aclk),
.CE(Bus2IIC_WrCE[8]),
.D(s_axi_wdata[0]),
.Q(\RD_FIFO_CNTRL.ro_prev_i_reg_0 [0]),
.R(Bus2IIC_Reset));
FDRE \RD_FIFO_CNTRL.ro_prev_i_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(p_6_out),
.Q(D),
.R(1'b0));
FDRE \adr_i_reg[0]
(.C(s_axi_aclk),
.CE(Bus2IIC_WrCE[9]),
.D(s_axi_wdata[7]),
.Q(adr_i[7]),
.R(Bus2IIC_Reset));
FDRE \adr_i_reg[1]
(.C(s_axi_aclk),
.CE(Bus2IIC_WrCE[9]),
.D(s_axi_wdata[6]),
.Q(adr_i[6]),
.R(Bus2IIC_Reset));
FDRE \adr_i_reg[2]
(.C(s_axi_aclk),
.CE(Bus2IIC_WrCE[9]),
.D(s_axi_wdata[5]),
.Q(adr_i[5]),
.R(Bus2IIC_Reset));
FDRE \adr_i_reg[3]
(.C(s_axi_aclk),
.CE(Bus2IIC_WrCE[9]),
.D(s_axi_wdata[4]),
.Q(adr_i[4]),
.R(Bus2IIC_Reset));
FDRE \adr_i_reg[4]
(.C(s_axi_aclk),
.CE(Bus2IIC_WrCE[9]),
.D(s_axi_wdata[3]),
.Q(adr_i[3]),
.R(Bus2IIC_Reset));
FDRE \adr_i_reg[5]
(.C(s_axi_aclk),
.CE(Bus2IIC_WrCE[9]),
.D(s_axi_wdata[2]),
.Q(adr_i[2]),
.R(Bus2IIC_Reset));
FDRE \adr_i_reg[6]
(.C(s_axi_aclk),
.CE(Bus2IIC_WrCE[9]),
.D(s_axi_wdata[1]),
.Q(adr_i[1]),
.R(Bus2IIC_Reset));
LUT2 #(
.INIT(4'h9))
clk_cnt_en1_carry_i_1
(.I0(timing_param_thigh_i[9]),
.I1(\q_int_reg[0]_0 [9]),
.O(S[3]));
LUT6 #(
.INIT(64'h9009000000009009))
clk_cnt_en1_carry_i_2
(.I0(\FSM_sequential_scl_state_reg[0] [7]),
.I1(\q_int_reg[0]_0 [7]),
.I2(\q_int_reg[0]_0 [8]),
.I3(timing_param_thigh_i[8]),
.I4(\q_int_reg[0]_0 [6]),
.I5(\FSM_sequential_scl_state_reg[0] [6]),
.O(S[2]));
LUT6 #(
.INIT(64'h9009000000009009))
clk_cnt_en1_carry_i_3
(.I0(\FSM_sequential_scl_state_reg[0] [4]),
.I1(\q_int_reg[0]_0 [4]),
.I2(\q_int_reg[0]_0 [5]),
.I3(\FSM_sequential_scl_state_reg[0] [5]),
.I4(\q_int_reg[0]_0 [3]),
.I5(\FSM_sequential_scl_state_reg[0] [3]),
.O(S[1]));
LUT6 #(
.INIT(64'h9009000000009009))
clk_cnt_en1_carry_i_4
(.I0(\FSM_sequential_scl_state_reg[0] [2]),
.I1(\q_int_reg[0]_0 [2]),
.I2(\q_int_reg[0]_0 [0]),
.I3(\FSM_sequential_scl_state_reg[0] [0]),
.I4(\q_int_reg[0]_0 [1]),
.I5(\FSM_sequential_scl_state_reg[0] [1]),
.O(S[0]));
LUT2 #(
.INIT(4'h9))
clk_cnt_en2_carry_i_1
(.I0(timing_param_thddat_i[9]),
.I1(\q_int_reg[0]_0 [9]),
.O(\q_int_reg[0] [3]));
LUT6 #(
.INIT(64'h9009000000009009))
clk_cnt_en2_carry_i_2
(.I0(timing_param_thddat_i[7]),
.I1(\q_int_reg[0]_0 [7]),
.I2(\q_int_reg[0]_0 [8]),
.I3(timing_param_thddat_i[8]),
.I4(\q_int_reg[0]_0 [6]),
.I5(timing_param_thddat_i[6]),
.O(\q_int_reg[0] [2]));
LUT6 #(
.INIT(64'h9009000000009009))
clk_cnt_en2_carry_i_3
(.I0(\s_axi_rdata_i_reg[5] [0]),
.I1(\q_int_reg[0]_0 [4]),
.I2(\q_int_reg[0]_0 [5]),
.I3(\s_axi_rdata_i_reg[5] [1]),
.I4(\q_int_reg[0]_0 [3]),
.I5(timing_param_thddat_i[3]),
.O(\q_int_reg[0] [1]));
LUT6 #(
.INIT(64'h9009000000009009))
clk_cnt_en2_carry_i_4
(.I0(timing_param_thddat_i[2]),
.I1(\q_int_reg[0]_0 [2]),
.I2(\q_int_reg[0]_0 [0]),
.I3(timing_param_thddat_i[0]),
.I4(\q_int_reg[0]_0 [1]),
.I5(timing_param_thddat_i[1]),
.O(\q_int_reg[0] [0]));
LUT6 #(
.INIT(64'hB8B8B8B888B8B8B8))
\cr_i[2]_i_1
(.I0(s_axi_wdata[5]),
.I1(Bus2IIC_WrCE[11]),
.I2(\cr_i[2]_i_2_n_0 ),
.I3(\FSM_sequential_scl_state_reg[2]_1 ),
.I4(Q[3]),
.I5(\FSM_sequential_scl_state_reg[0]_2 ),
.O(\cr_i[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAEAAAAAAAAAAAAAA))
\cr_i[2]_i_2
(.I0(Q[3]),
.I1(Tx_fifo_rd),
.I2(Tx_fifo_rd_d),
.I3(dynamic_MSMS),
.I4(Tx_data_exists),
.I5(firstDynStartSeen),
.O(\cr_i[2]_i_2_n_0 ));
LUT2 #(
.INIT(4'hB))
\cr_i[5]_i_4
(.I0(Tx_fifo_rd_d),
.I1(Tx_fifo_rd),
.O(\cr_i_reg[5]_0 ));
FDRE \cr_i_reg[0]
(.C(s_axi_aclk),
.CE(Bus2IIC_WrCE[11]),
.D(s_axi_wdata[7]),
.Q(Cr[0]),
.R(Bus2IIC_Reset));
FDRE \cr_i_reg[1]
(.C(s_axi_aclk),
.CE(Bus2IIC_WrCE[11]),
.D(s_axi_wdata[6]),
.Q(Q[4]),
.R(Bus2IIC_Reset));
FDRE \cr_i_reg[2]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\cr_i[2]_i_1_n_0 ),
.Q(Q[3]),
.R(Bus2IIC_Reset));
FDRE \cr_i_reg[3]
(.C(s_axi_aclk),
.CE(Bus2IIC_WrCE[11]),
.D(s_axi_wdata[4]),
.Q(Cr[3]),
.R(Bus2IIC_Reset));
FDRE \cr_i_reg[4]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_BKEND_CE_REGISTERS[17].ce_out_i_reg[17] [1]),
.Q(Q[2]),
.R(Bus2IIC_Reset));
FDRE \cr_i_reg[5]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_BKEND_CE_REGISTERS[17].ce_out_i_reg[17] [0]),
.Q(Q[1]),
.R(Bus2IIC_Reset));
FDRE \cr_i_reg[6]
(.C(s_axi_aclk),
.CE(Bus2IIC_WrCE[11]),
.D(s_axi_wdata[1]),
.Q(Cr[6]),
.R(Bus2IIC_Reset));
FDRE \cr_i_reg[7]
(.C(s_axi_aclk),
.CE(Bus2IIC_WrCE[11]),
.D(s_axi_wdata[0]),
.Q(Q[0]),
.R(Bus2IIC_Reset));
LUT4 #(
.INIT(16'h00B0))
firstDynStartSeen_i_1
(.I0(firstDynStartSeen),
.I1(firstDynStartSeen_i_2_n_0),
.I2(Q[1]),
.I3(Tx_fifo_rst),
.O(firstDynStartSeen_reg));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT4 #(
.INIT(16'hDFFF))
firstDynStartSeen_i_2
(.I0(Tx_fifo_rd),
.I1(Tx_fifo_rd_d),
.I2(dynamic_MSMS),
.I3(Tx_data_exists),
.O(firstDynStartSeen_i_2_n_0));
LUT2 #(
.INIT(4'h9))
i__carry_i_1
(.I0(timing_param_tsusto_i[9]),
.I1(\q_int_reg[0]_0 [9]),
.O(sda_cout_reg_reg[3]));
LUT2 #(
.INIT(4'h9))
i__carry_i_1__0
(.I0(timing_param_tsusta_i[9]),
.I1(\q_int_reg[0]_0 [9]),
.O(\FSM_sequential_scl_state_reg[0]_0 [3]));
LUT2 #(
.INIT(4'h9))
i__carry_i_1__1
(.I0(timing_param_tbuf_i[9]),
.I1(\q_int_reg[0]_0 [9]),
.O(\FSM_sequential_scl_state_reg[3] [3]));
LUT2 #(
.INIT(4'h9))
i__carry_i_1__2
(.I0(timing_param_thdsta_i[9]),
.I1(\q_int_reg[0]_0 [9]),
.O(\FSM_sequential_scl_state_reg[2] [3]));
LUT2 #(
.INIT(4'h9))
i__carry_i_1__3
(.I0(timing_param_tlow_i[9]),
.I1(\q_int_reg[0]_0 [9]),
.O(\FSM_sequential_scl_state_reg[1] [3]));
LUT2 #(
.INIT(4'h9))
i__carry_i_1__4
(.I0(timing_param_tsudat_i),
.I1(\q_int_reg[0]_1 [6]),
.O(sda_setup_reg[2]));
LUT6 #(
.INIT(64'h9009000000009009))
i__carry_i_2
(.I0(timing_param_tsusto_i[8]),
.I1(\q_int_reg[0]_0 [8]),
.I2(\q_int_reg[0]_0 [7]),
.I3(sda_cout_reg_reg_0[7]),
.I4(\q_int_reg[0]_0 [6]),
.I5(sda_cout_reg_reg_0[6]),
.O(sda_cout_reg_reg[2]));
LUT6 #(
.INIT(64'h9009000000009009))
i__carry_i_2__0
(.I0(\s_axi_rdata_i_reg[7] [3]),
.I1(\q_int_reg[0]_0 [7]),
.I2(\q_int_reg[0]_0 [8]),
.I3(timing_param_tsusta_i[8]),
.I4(\q_int_reg[0]_0 [6]),
.I5(\s_axi_rdata_i_reg[7] [2]),
.O(\FSM_sequential_scl_state_reg[0]_0 [2]));
LUT6 #(
.INIT(64'h9009000000009009))
i__carry_i_2__1
(.I0(\FSM_sequential_scl_state_reg[3]_0 [3]),
.I1(\q_int_reg[0]_0 [7]),
.I2(\q_int_reg[0]_0 [8]),
.I3(timing_param_tbuf_i[8]),
.I4(\q_int_reg[0]_0 [6]),
.I5(\FSM_sequential_scl_state_reg[3]_0 [2]),
.O(\FSM_sequential_scl_state_reg[3] [2]));
LUT6 #(
.INIT(64'h9009000000009009))
i__carry_i_2__2
(.I0(timing_param_thdsta_i[7]),
.I1(\q_int_reg[0]_0 [7]),
.I2(\q_int_reg[0]_0 [8]),
.I3(timing_param_thdsta_i[8]),
.I4(\q_int_reg[0]_0 [6]),
.I5(timing_param_thdsta_i[6]),
.O(\FSM_sequential_scl_state_reg[2] [2]));
LUT6 #(
.INIT(64'h9009000000009009))
i__carry_i_2__3
(.I0(timing_param_tlow_i[8]),
.I1(\q_int_reg[0]_0 [8]),
.I2(\q_int_reg[0]_0 [6]),
.I3(timing_param_tlow_i[6]),
.I4(\q_int_reg[0]_0 [7]),
.I5(timing_param_tlow_i[7]),
.O(\FSM_sequential_scl_state_reg[1] [2]));
LUT6 #(
.INIT(64'h9009000000009009))
i__carry_i_3
(.I0(sda_cout_reg_reg_0[5]),
.I1(\q_int_reg[0]_0 [5]),
.I2(\q_int_reg[0]_0 [4]),
.I3(sda_cout_reg_reg_0[4]),
.I4(\q_int_reg[0]_0 [3]),
.I5(sda_cout_reg_reg_0[3]),
.O(sda_cout_reg_reg[1]));
LUT6 #(
.INIT(64'h9009000000009009))
i__carry_i_3__0
(.I0(\s_axi_rdata_i_reg[7] [0]),
.I1(\q_int_reg[0]_0 [4]),
.I2(\q_int_reg[0]_0 [5]),
.I3(\s_axi_rdata_i_reg[7] [1]),
.I4(\q_int_reg[0]_0 [3]),
.I5(timing_param_tsusta_i[3]),
.O(\FSM_sequential_scl_state_reg[0]_0 [1]));
LUT6 #(
.INIT(64'h9009000000009009))
i__carry_i_3__1
(.I0(\FSM_sequential_scl_state_reg[3]_0 [1]),
.I1(\q_int_reg[0]_0 [5]),
.I2(\q_int_reg[0]_0 [3]),
.I3(timing_param_tbuf_i[3]),
.I4(\q_int_reg[0]_0 [4]),
.I5(\FSM_sequential_scl_state_reg[3]_0 [0]),
.O(\FSM_sequential_scl_state_reg[3] [1]));
LUT6 #(
.INIT(64'h9009000000009009))
i__carry_i_3__2
(.I0(timing_param_thdsta_i[4]),
.I1(\q_int_reg[0]_0 [4]),
.I2(\q_int_reg[0]_0 [5]),
.I3(timing_param_thdsta_i[5]),
.I4(\q_int_reg[0]_0 [3]),
.I5(timing_param_thdsta_i[3]),
.O(\FSM_sequential_scl_state_reg[2] [1]));
LUT6 #(
.INIT(64'h9009000000009009))
i__carry_i_3__3
(.I0(timing_param_tlow_i[5]),
.I1(\q_int_reg[0]_0 [5]),
.I2(\q_int_reg[0]_0 [4]),
.I3(timing_param_tlow_i[4]),
.I4(\q_int_reg[0]_0 [3]),
.I5(timing_param_tlow_i[3]),
.O(\FSM_sequential_scl_state_reg[1] [1]));
LUT6 #(
.INIT(64'h9009000000009009))
i__carry_i_3__4
(.I0(\s_axi_rdata_i_reg[8] [4]),
.I1(\q_int_reg[0]_1 [4]),
.I2(\q_int_reg[0]_1 [5]),
.I3(\s_axi_rdata_i_reg[8] [5]),
.I4(\q_int_reg[0]_1 [3]),
.I5(\s_axi_rdata_i_reg[8] [3]),
.O(sda_setup_reg[1]));
LUT6 #(
.INIT(64'h9009000000009009))
i__carry_i_4
(.I0(sda_cout_reg_reg_0[2]),
.I1(\q_int_reg[0]_0 [2]),
.I2(\q_int_reg[0]_0 [0]),
.I3(sda_cout_reg_reg_0[0]),
.I4(\q_int_reg[0]_0 [1]),
.I5(sda_cout_reg_reg_0[1]),
.O(sda_cout_reg_reg[0]));
LUT6 #(
.INIT(64'h9009000000009009))
i__carry_i_4__0
(.I0(timing_param_tsusta_i[1]),
.I1(\q_int_reg[0]_0 [1]),
.I2(\q_int_reg[0]_0 [2]),
.I3(timing_param_tsusta_i[2]),
.I4(\q_int_reg[0]_0 [0]),
.I5(timing_param_tsusta_i[0]),
.O(\FSM_sequential_scl_state_reg[0]_0 [0]));
LUT6 #(
.INIT(64'h9009000000009009))
i__carry_i_4__1
(.I0(timing_param_tbuf_i[2]),
.I1(\q_int_reg[0]_0 [2]),
.I2(\q_int_reg[0]_0 [0]),
.I3(timing_param_tbuf_i[0]),
.I4(\q_int_reg[0]_0 [1]),
.I5(timing_param_tbuf_i[1]),
.O(\FSM_sequential_scl_state_reg[3] [0]));
LUT6 #(
.INIT(64'h9009000000009009))
i__carry_i_4__2
(.I0(timing_param_thdsta_i[1]),
.I1(\q_int_reg[0]_0 [1]),
.I2(\q_int_reg[0]_0 [2]),
.I3(timing_param_thdsta_i[2]),
.I4(\q_int_reg[0]_0 [0]),
.I5(\FSM_sequential_scl_state_reg[2]_0 ),
.O(\FSM_sequential_scl_state_reg[2] [0]));
LUT6 #(
.INIT(64'h9009000000009009))
i__carry_i_4__3
(.I0(timing_param_tlow_i[2]),
.I1(\q_int_reg[0]_0 [2]),
.I2(\q_int_reg[0]_0 [0]),
.I3(\FSM_sequential_scl_state_reg[1]_0 ),
.I4(\q_int_reg[0]_0 [1]),
.I5(timing_param_tlow_i[1]),
.O(\FSM_sequential_scl_state_reg[1] [0]));
LUT6 #(
.INIT(64'h9009000000009009))
i__carry_i_4__4
(.I0(\s_axi_rdata_i_reg[8] [2]),
.I1(\q_int_reg[0]_1 [2]),
.I2(\q_int_reg[0]_1 [0]),
.I3(\s_axi_rdata_i_reg[8] [0]),
.I4(\q_int_reg[0]_1 [1]),
.I5(\s_axi_rdata_i_reg[8] [1]),
.O(sda_setup_reg[0]));
FDRE msms_d1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(Q[1]),
.Q(msms_d1),
.R(Bus2IIC_Reset));
LUT5 #(
.INIT(32'hCE0C0A00))
msms_set_i_i_1
(.I0(D),
.I1(Data_Exists_DFF_3[1]),
.I2(Q[1]),
.I3(msms_d1),
.I4(Msms_set),
.O(msms_set_i_i_1_n_0));
FDRE msms_set_i_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(msms_set_i_i_1_n_0),
.Q(Msms_set),
.R(Bus2IIC_Reset));
FDRE new_rcv_dta_d1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(New_rcv_dta),
.Q(new_rcv_dta_d1),
.R(Bus2IIC_Reset));
LUT6 #(
.INIT(64'h00000000FFE200E2))
\q_int[0]_i_6
(.I0(CO),
.I1(stop_scl_reg),
.I2(\timing_param_tsusto_i_reg[9]_0 ),
.I3(Q[3]),
.I4(\timing_param_tsusta_i_reg[9]_0 ),
.I5(arb_lost),
.O(\q_int_reg[9] ));
LUT5 #(
.INIT(32'hCF44CF77))
\s_axi_rdata_i[0]_i_6
(.I0(gpo),
.I1(\bus2ip_addr_i_reg[6] [3]),
.I2(timing_param_thddat_i[0]),
.I3(\bus2ip_addr_i_reg[6] [4]),
.I4(sr_i[7]),
.O(\s_axi_rdata_i_reg[0] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\s_axi_rdata_i[0]_i_8
(.I0(timing_param_tbuf_i[0]),
.I1(Rc_addr[0]),
.I2(\bus2ip_addr_i_reg[6] [2]),
.I3(timing_param_tsusta_i[0]),
.I4(\bus2ip_addr_i_reg[6] [3]),
.I5(Tx_fifo_data[0]),
.O(\s_axi_rdata_i_reg[0]_0 ));
LUT5 #(
.INIT(32'h30BB3088))
\s_axi_rdata_i[1]_i_10
(.I0(\RD_FIFO_CNTRL.ro_prev_i_reg_0 [1]),
.I1(\bus2ip_addr_i_reg[6] [3]),
.I2(timing_param_tlow_i[1]),
.I3(\bus2ip_addr_i_reg[6] [4]),
.I4(Cr[6]),
.O(\s_axi_rdata_i[1]_i_10_n_0 ));
LUT6 #(
.INIT(64'h00E2FFFF00E20000))
\s_axi_rdata_i[1]_i_5
(.I0(adr_i[1]),
.I1(\bus2ip_addr_i_reg[6] [3]),
.I2(timing_param_thdsta_i[1]),
.I3(\bus2ip_addr_i_reg[6] [4]),
.I4(\bus2ip_addr_i_reg[6] [2]),
.I5(\s_axi_rdata_i[1]_i_10_n_0 ),
.O(\s_axi_rdata_i_reg[1] ));
LUT4 #(
.INIT(16'h00E2))
\s_axi_rdata_i[1]_i_6
(.I0(IIC2Bus_IntrEvent[5]),
.I1(\bus2ip_addr_i_reg[6] [4]),
.I2(timing_param_thddat_i[1]),
.I3(\bus2ip_addr_i_reg[6] [3]),
.O(\s_axi_rdata_i_reg[1]_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\s_axi_rdata_i[1]_i_7
(.I0(timing_param_tbuf_i[1]),
.I1(Rc_addr[1]),
.I2(\bus2ip_addr_i_reg[6] [2]),
.I3(timing_param_tsusta_i[1]),
.I4(\bus2ip_addr_i_reg[6] [3]),
.I5(Tx_fifo_data[1]),
.O(\s_axi_rdata_i_reg[1]_1 ));
LUT6 #(
.INIT(64'h00E2FFFF00E20000))
\s_axi_rdata_i[2]_i_3
(.I0(adr_i[2]),
.I1(\bus2ip_addr_i_reg[6] [3]),
.I2(timing_param_thdsta_i[2]),
.I3(\bus2ip_addr_i_reg[6] [4]),
.I4(\bus2ip_addr_i_reg[6] [2]),
.I5(\s_axi_rdata_i[2]_i_6_n_0 ),
.O(\s_axi_rdata_i_reg[2]_0 ));
LUT5 #(
.INIT(32'h30BB3088))
\s_axi_rdata_i[2]_i_6
(.I0(\RD_FIFO_CNTRL.ro_prev_i_reg_0 [2]),
.I1(\bus2ip_addr_i_reg[6] [3]),
.I2(timing_param_tlow_i[2]),
.I3(\bus2ip_addr_i_reg[6] [4]),
.I4(Q[1]),
.O(\s_axi_rdata_i[2]_i_6_n_0 ));
LUT4 #(
.INIT(16'h00E2))
\s_axi_rdata_i[2]_i_7
(.I0(sr_i[5]),
.I1(\bus2ip_addr_i_reg[6] [4]),
.I2(timing_param_thddat_i[2]),
.I3(\bus2ip_addr_i_reg[6] [3]),
.O(\s_axi_rdata_i_reg[2]_1 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\s_axi_rdata_i[2]_i_9
(.I0(timing_param_tbuf_i[2]),
.I1(Rc_addr[2]),
.I2(\bus2ip_addr_i_reg[6] [2]),
.I3(timing_param_tsusta_i[2]),
.I4(\bus2ip_addr_i_reg[6] [3]),
.I5(Tx_fifo_data[2]),
.O(\s_axi_rdata_i_reg[2] ));
LUT4 #(
.INIT(16'h00E2))
\s_axi_rdata_i[3]_i_10
(.I0(sr_i[4]),
.I1(\bus2ip_addr_i_reg[6] [4]),
.I2(timing_param_thddat_i[3]),
.I3(\bus2ip_addr_i_reg[6] [3]),
.O(\s_axi_rdata_i_reg[3]_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\s_axi_rdata_i[3]_i_4
(.I0(timing_param_tbuf_i[3]),
.I1(Rc_addr[3]),
.I2(\bus2ip_addr_i_reg[6] [2]),
.I3(timing_param_tsusta_i[3]),
.I4(\bus2ip_addr_i_reg[6] [3]),
.I5(Tx_fifo_data[3]),
.O(\s_axi_rdata_i_reg[3]_1 ));
LUT6 #(
.INIT(64'h00E2FFFF00E20000))
\s_axi_rdata_i[3]_i_5
(.I0(adr_i[3]),
.I1(\bus2ip_addr_i_reg[6] [3]),
.I2(timing_param_thdsta_i[3]),
.I3(\bus2ip_addr_i_reg[6] [4]),
.I4(\bus2ip_addr_i_reg[6] [2]),
.I5(\s_axi_rdata_i[3]_i_9_n_0 ),
.O(\s_axi_rdata_i_reg[3] ));
LUT5 #(
.INIT(32'h30BB3088))
\s_axi_rdata_i[3]_i_9
(.I0(\RD_FIFO_CNTRL.ro_prev_i_reg_0 [3]),
.I1(\bus2ip_addr_i_reg[6] [3]),
.I2(timing_param_tlow_i[3]),
.I3(\bus2ip_addr_i_reg[6] [4]),
.I4(Q[2]),
.O(\s_axi_rdata_i[3]_i_9_n_0 ));
LUT6 #(
.INIT(64'h00E2FFFF00E20000))
\s_axi_rdata_i[4]_i_4
(.I0(adr_i[4]),
.I1(\bus2ip_addr_i_reg[6] [3]),
.I2(timing_param_thdsta_i[4]),
.I3(\bus2ip_addr_i_reg[6] [4]),
.I4(\bus2ip_addr_i_reg[6] [2]),
.I5(\s_axi_rdata_i[4]_i_8_n_0 ),
.O(\s_axi_rdata_i_reg[4] ));
LUT4 #(
.INIT(16'h00E2))
\s_axi_rdata_i[4]_i_8
(.I0(Cr[3]),
.I1(\bus2ip_addr_i_reg[6] [4]),
.I2(timing_param_tlow_i[4]),
.I3(\bus2ip_addr_i_reg[6] [3]),
.O(\s_axi_rdata_i[4]_i_8_n_0 ));
LUT6 #(
.INIT(64'h00E2FFFF00E20000))
\s_axi_rdata_i[5]_i_4
(.I0(adr_i[5]),
.I1(\bus2ip_addr_i_reg[6] [3]),
.I2(timing_param_thdsta_i[5]),
.I3(\bus2ip_addr_i_reg[6] [4]),
.I4(\bus2ip_addr_i_reg[6] [2]),
.I5(\s_axi_rdata_i[5]_i_8_n_0 ),
.O(\s_axi_rdata_i_reg[5]_0 ));
LUT4 #(
.INIT(16'h00E2))
\s_axi_rdata_i[5]_i_8
(.I0(Q[3]),
.I1(\bus2ip_addr_i_reg[6] [4]),
.I2(timing_param_tlow_i[5]),
.I3(\bus2ip_addr_i_reg[6] [3]),
.O(\s_axi_rdata_i[5]_i_8_n_0 ));
LUT6 #(
.INIT(64'h00E2FFFF00E20000))
\s_axi_rdata_i[6]_i_4
(.I0(adr_i[6]),
.I1(\bus2ip_addr_i_reg[6] [3]),
.I2(timing_param_thdsta_i[6]),
.I3(\bus2ip_addr_i_reg[6] [4]),
.I4(\bus2ip_addr_i_reg[6] [2]),
.I5(\s_axi_rdata_i[6]_i_8_n_0 ),
.O(\s_axi_rdata_i_reg[6]_0 ));
LUT6 #(
.INIT(64'h0088008833300030))
\s_axi_rdata_i[6]_i_5
(.I0(\s_axi_rdata_i_reg[8] [6]),
.I1(\bus2ip_addr_i_reg[6] [2]),
.I2(sr_i[1]),
.I3(\bus2ip_addr_i_reg[6] [4]),
.I4(timing_param_thddat_i[6]),
.I5(\bus2ip_addr_i_reg[6] [3]),
.O(\s_axi_rdata_i_reg[6] ));
LUT4 #(
.INIT(16'h00E2))
\s_axi_rdata_i[6]_i_8
(.I0(Q[4]),
.I1(\bus2ip_addr_i_reg[6] [4]),
.I2(timing_param_tlow_i[6]),
.I3(\bus2ip_addr_i_reg[6] [3]),
.O(\s_axi_rdata_i[6]_i_8_n_0 ));
LUT6 #(
.INIT(64'h00E2FFFF00E20000))
\s_axi_rdata_i[7]_i_4
(.I0(adr_i[7]),
.I1(\bus2ip_addr_i_reg[6] [3]),
.I2(timing_param_thdsta_i[7]),
.I3(\bus2ip_addr_i_reg[6] [4]),
.I4(\bus2ip_addr_i_reg[6] [2]),
.I5(\s_axi_rdata_i[7]_i_8_n_0 ),
.O(\s_axi_rdata_i_reg[7]_1 ));
LUT6 #(
.INIT(64'h0088008833300030))
\s_axi_rdata_i[7]_i_5
(.I0(\s_axi_rdata_i_reg[8] [7]),
.I1(\bus2ip_addr_i_reg[6] [2]),
.I2(dtre_d1_reg[2]),
.I3(\bus2ip_addr_i_reg[6] [4]),
.I4(timing_param_thddat_i[7]),
.I5(\bus2ip_addr_i_reg[6] [3]),
.O(\s_axi_rdata_i_reg[7]_0 ));
LUT4 #(
.INIT(16'h00E2))
\s_axi_rdata_i[7]_i_8
(.I0(Cr[0]),
.I1(\bus2ip_addr_i_reg[6] [4]),
.I2(timing_param_tlow_i[7]),
.I3(\bus2ip_addr_i_reg[6] [3]),
.O(\s_axi_rdata_i[7]_i_8_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\s_axi_rdata_i[8]_i_3
(.I0(timing_param_tbuf_i[8]),
.I1(timing_param_tsusta_i[8]),
.I2(\bus2ip_addr_i_reg[6] [1]),
.I3(timing_param_thdsta_i[8]),
.I4(\bus2ip_addr_i_reg[6] [2]),
.I5(timing_param_tlow_i[8]),
.O(\s_axi_rdata_i[8]_i_3_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\s_axi_rdata_i[8]_i_4
(.I0(timing_param_thigh_i[8]),
.I1(timing_param_tsusto_i[8]),
.I2(\bus2ip_addr_i_reg[6] [1]),
.I3(\s_axi_rdata_i_reg[8] [8]),
.I4(\bus2ip_addr_i_reg[6] [2]),
.I5(timing_param_thddat_i[8]),
.O(\s_axi_rdata_i[8]_i_4_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\s_axi_rdata_i[9]_i_4
(.I0(timing_param_tbuf_i[9]),
.I1(timing_param_tsusta_i[9]),
.I2(\bus2ip_addr_i_reg[6] [1]),
.I3(timing_param_thdsta_i[9]),
.I4(\bus2ip_addr_i_reg[6] [2]),
.I5(timing_param_tlow_i[9]),
.O(\s_axi_rdata_i[9]_i_4_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\s_axi_rdata_i[9]_i_5
(.I0(timing_param_thigh_i[9]),
.I1(timing_param_tsusto_i[9]),
.I2(\bus2ip_addr_i_reg[6] [1]),
.I3(timing_param_tsudat_i),
.I4(\bus2ip_addr_i_reg[6] [2]),
.I5(timing_param_thddat_i[9]),
.O(\s_axi_rdata_i[9]_i_5_n_0 ));
MUXF7 \s_axi_rdata_i_reg[8]_i_2
(.I0(\s_axi_rdata_i[8]_i_3_n_0 ),
.I1(\s_axi_rdata_i[8]_i_4_n_0 ),
.O(\s_axi_rdata_i_reg[8]_0 ),
.S(\bus2ip_addr_i_reg[6] [0]));
MUXF7 \s_axi_rdata_i_reg[9]_i_2
(.I0(\s_axi_rdata_i[9]_i_4_n_0 ),
.I1(\s_axi_rdata_i[9]_i_5_n_0 ),
.O(\s_axi_rdata_i_reg[9] ),
.S(\bus2ip_addr_i_reg[6] [0]));
LUT5 #(
.INIT(32'h55555514))
slave_sda_i_2
(.I0(Data_Exists_DFF_3[0]),
.I1(\data_int_reg[7] [7]),
.I2(adr_i[7]),
.I3(slave_sda_i_3_n_0),
.I4(slave_sda_i_4_n_0),
.O(slave_sda_reg));
LUT6 #(
.INIT(64'h6FF6FFFFFFFF6FF6))
slave_sda_i_3
(.I0(adr_i[4]),
.I1(\data_int_reg[7] [4]),
.I2(\data_int_reg[7] [5]),
.I3(adr_i[5]),
.I4(\data_int_reg[7] [6]),
.I5(adr_i[6]),
.O(slave_sda_i_3_n_0));
LUT6 #(
.INIT(64'h6FF6FFFFFFFF6FF6))
slave_sda_i_4
(.I0(adr_i[1]),
.I1(\data_int_reg[7] [1]),
.I2(\data_int_reg[7] [3]),
.I3(adr_i[3]),
.I4(\data_int_reg[7] [2]),
.I5(adr_i[2]),
.O(slave_sda_i_4_n_0));
FDRE \sr_i_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Data_Exists_DFF_1),
.Q(dtre_d1_reg[2]),
.R(Bus2IIC_Reset));
FDRE \sr_i_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Data_Exists_DFF_3[5]),
.Q(sr_i[1]),
.R(Bus2IIC_Reset));
FDRE \sr_i_reg[2]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Data_Exists_DFF_3[4]),
.Q(dtre_d1_reg[1]),
.R(Bus2IIC_Reset));
FDRE \sr_i_reg[3]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Data_Exists_DFF_3[3]),
.Q(dtre_d1_reg[0]),
.R(Bus2IIC_Reset));
FDRE \sr_i_reg[4]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Data_Exists_DFF_3[2]),
.Q(sr_i[4]),
.R(Bus2IIC_Reset));
FDRE \sr_i_reg[5]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Data_Exists_DFF_3[1]),
.Q(sr_i[5]),
.R(Bus2IIC_Reset));
FDRE \sr_i_reg[7]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Data_Exists_DFF_3[0]),
.Q(sr_i[7]),
.R(Bus2IIC_Reset));
FDRE \timing_param_tbuf_i_reg[0]
(.C(s_axi_aclk),
.CE(Bus2IIC_WrCE[3]),
.D(s_axi_wdata[0]),
.Q(timing_param_tbuf_i[0]),
.R(Bus2IIC_Reset));
FDRE \timing_param_tbuf_i_reg[1]
(.C(s_axi_aclk),
.CE(Bus2IIC_WrCE[3]),
.D(s_axi_wdata[1]),
.Q(timing_param_tbuf_i[1]),
.R(Bus2IIC_Reset));
FDSE \timing_param_tbuf_i_reg[2]
(.C(s_axi_aclk),
.CE(Bus2IIC_WrCE[3]),
.D(s_axi_wdata[2]),
.Q(timing_param_tbuf_i[2]),
.S(Bus2IIC_Reset));
FDRE \timing_param_tbuf_i_reg[3]
(.C(s_axi_aclk),
.CE(Bus2IIC_WrCE[3]),
.D(s_axi_wdata[3]),
.Q(timing_param_tbuf_i[3]),
.R(Bus2IIC_Reset));
FDSE \timing_param_tbuf_i_reg[4]
(.C(s_axi_aclk),
.CE(Bus2IIC_WrCE[3]),
.D(s_axi_wdata[4]),
.Q(\FSM_sequential_scl_state_reg[3]_0 [0]),
.S(Bus2IIC_Reset));
FDSE \timing_param_tbuf_i_reg[5]
(.C(s_axi_aclk),
.CE(Bus2IIC_WrCE[3]),
.D(s_axi_wdata[5]),
.Q(\FSM_sequential_scl_state_reg[3]_0 [1]),
.S(Bus2IIC_Reset));
FDSE \timing_param_tbuf_i_reg[6]
(.C(s_axi_aclk),
.CE(Bus2IIC_WrCE[3]),
.D(s_axi_wdata[6]),
.Q(\FSM_sequential_scl_state_reg[3]_0 [2]),
.S(Bus2IIC_Reset));
FDSE \timing_param_tbuf_i_reg[7]
(.C(s_axi_aclk),
.CE(Bus2IIC_WrCE[3]),
.D(s_axi_wdata[7]),
.Q(\FSM_sequential_scl_state_reg[3]_0 [3]),
.S(Bus2IIC_Reset));
FDSE \timing_param_tbuf_i_reg[8]
(.C(s_axi_aclk),
.CE(Bus2IIC_WrCE[3]),
.D(s_axi_wdata[8]),
.Q(timing_param_tbuf_i[8]),
.S(Bus2IIC_Reset));
FDRE \timing_param_tbuf_i_reg[9]
(.C(s_axi_aclk),
.CE(Bus2IIC_WrCE[3]),
.D(s_axi_wdata[9]),
.Q(timing_param_tbuf_i[9]),
.R(Bus2IIC_Reset));
FDSE \timing_param_thddat_i_reg[0]
(.C(s_axi_aclk),
.CE(Bus2IIC_WrCE[0]),
.D(s_axi_wdata[0]),
.Q(timing_param_thddat_i[0]),
.S(Bus2IIC_Reset));
FDRE \timing_param_thddat_i_reg[1]
(.C(s_axi_aclk),
.CE(Bus2IIC_WrCE[0]),
.D(s_axi_wdata[1]),
.Q(timing_param_thddat_i[1]),
.R(Bus2IIC_Reset));
FDRE \timing_param_thddat_i_reg[2]
(.C(s_axi_aclk),
.CE(Bus2IIC_WrCE[0]),
.D(s_axi_wdata[2]),
.Q(timing_param_thddat_i[2]),
.R(Bus2IIC_Reset));
FDRE \timing_param_thddat_i_reg[3]
(.C(s_axi_aclk),
.CE(Bus2IIC_WrCE[0]),
.D(s_axi_wdata[3]),
.Q(timing_param_thddat_i[3]),
.R(Bus2IIC_Reset));
FDRE \timing_param_thddat_i_reg[4]
(.C(s_axi_aclk),
.CE(Bus2IIC_WrCE[0]),
.D(s_axi_wdata[4]),
.Q(\s_axi_rdata_i_reg[5] [0]),
.R(Bus2IIC_Reset));
FDRE \timing_param_thddat_i_reg[5]
(.C(s_axi_aclk),
.CE(Bus2IIC_WrCE[0]),
.D(s_axi_wdata[5]),
.Q(\s_axi_rdata_i_reg[5] [1]),
.R(Bus2IIC_Reset));
FDRE \timing_param_thddat_i_reg[6]
(.C(s_axi_aclk),
.CE(Bus2IIC_WrCE[0]),
.D(s_axi_wdata[6]),
.Q(timing_param_thddat_i[6]),
.R(Bus2IIC_Reset));
FDRE \timing_param_thddat_i_reg[7]
(.C(s_axi_aclk),
.CE(Bus2IIC_WrCE[0]),
.D(s_axi_wdata[7]),
.Q(timing_param_thddat_i[7]),
.R(Bus2IIC_Reset));
FDRE \timing_param_thddat_i_reg[8]
(.C(s_axi_aclk),
.CE(Bus2IIC_WrCE[0]),
.D(s_axi_wdata[8]),
.Q(timing_param_thddat_i[8]),
.R(Bus2IIC_Reset));
FDRE \timing_param_thddat_i_reg[9]
(.C(s_axi_aclk),
.CE(Bus2IIC_WrCE[0]),
.D(s_axi_wdata[9]),
.Q(timing_param_thddat_i[9]),
.R(Bus2IIC_Reset));
FDRE \timing_param_thdsta_i_reg[0]
(.C(s_axi_aclk),
.CE(Bus2IIC_WrCE[5]),
.D(s_axi_wdata[0]),
.Q(\FSM_sequential_scl_state_reg[2]_0 ),
.R(Bus2IIC_Reset));
FDSE \timing_param_thdsta_i_reg[1]
(.C(s_axi_aclk),
.CE(Bus2IIC_WrCE[5]),
.D(s_axi_wdata[1]),
.Q(timing_param_thdsta_i[1]),
.S(Bus2IIC_Reset));
FDSE \timing_param_thdsta_i_reg[2]
(.C(s_axi_aclk),
.CE(Bus2IIC_WrCE[5]),
.D(s_axi_wdata[2]),
.Q(timing_param_thdsta_i[2]),
.S(Bus2IIC_Reset));
FDSE \timing_param_thdsta_i_reg[3]
(.C(s_axi_aclk),
.CE(Bus2IIC_WrCE[5]),
.D(s_axi_wdata[3]),
.Q(timing_param_thdsta_i[3]),
.S(Bus2IIC_Reset));
FDRE \timing_param_thdsta_i_reg[4]
(.C(s_axi_aclk),
.CE(Bus2IIC_WrCE[5]),
.D(s_axi_wdata[4]),
.Q(timing_param_thdsta_i[4]),
.R(Bus2IIC_Reset));
FDSE \timing_param_thdsta_i_reg[5]
(.C(s_axi_aclk),
.CE(Bus2IIC_WrCE[5]),
.D(s_axi_wdata[5]),
.Q(timing_param_thdsta_i[5]),
.S(Bus2IIC_Reset));
FDRE \timing_param_thdsta_i_reg[6]
(.C(s_axi_aclk),
.CE(Bus2IIC_WrCE[5]),
.D(s_axi_wdata[6]),
.Q(timing_param_thdsta_i[6]),
.R(Bus2IIC_Reset));
FDSE \timing_param_thdsta_i_reg[7]
(.C(s_axi_aclk),
.CE(Bus2IIC_WrCE[5]),
.D(s_axi_wdata[7]),
.Q(timing_param_thdsta_i[7]),
.S(Bus2IIC_Reset));
FDSE \timing_param_thdsta_i_reg[8]
(.C(s_axi_aclk),
.CE(Bus2IIC_WrCE[5]),
.D(s_axi_wdata[8]),
.Q(timing_param_thdsta_i[8]),
.S(Bus2IIC_Reset));
FDRE \timing_param_thdsta_i_reg[9]
(.C(s_axi_aclk),
.CE(Bus2IIC_WrCE[5]),
.D(s_axi_wdata[9]),
.Q(timing_param_thdsta_i[9]),
.R(Bus2IIC_Reset));
FDSE \timing_param_thigh_i_reg[0]
(.C(s_axi_aclk),
.CE(Bus2IIC_WrCE[2]),
.D(s_axi_wdata[0]),
.Q(\FSM_sequential_scl_state_reg[0] [0]),
.S(Bus2IIC_Reset));
FDRE \timing_param_thigh_i_reg[1]
(.C(s_axi_aclk),
.CE(Bus2IIC_WrCE[2]),
.D(s_axi_wdata[1]),
.Q(\FSM_sequential_scl_state_reg[0] [1]),
.R(Bus2IIC_Reset));
FDSE \timing_param_thigh_i_reg[2]
(.C(s_axi_aclk),
.CE(Bus2IIC_WrCE[2]),
.D(s_axi_wdata[2]),
.Q(\FSM_sequential_scl_state_reg[0] [2]),
.S(Bus2IIC_Reset));
FDSE \timing_param_thigh_i_reg[3]
(.C(s_axi_aclk),
.CE(Bus2IIC_WrCE[2]),
.D(s_axi_wdata[3]),
.Q(\FSM_sequential_scl_state_reg[0] [3]),
.S(Bus2IIC_Reset));
FDRE \timing_param_thigh_i_reg[4]
(.C(s_axi_aclk),
.CE(Bus2IIC_WrCE[2]),
.D(s_axi_wdata[4]),
.Q(\FSM_sequential_scl_state_reg[0] [4]),
.R(Bus2IIC_Reset));
FDSE \timing_param_thigh_i_reg[5]
(.C(s_axi_aclk),
.CE(Bus2IIC_WrCE[2]),
.D(s_axi_wdata[5]),
.Q(\FSM_sequential_scl_state_reg[0] [5]),
.S(Bus2IIC_Reset));
FDSE \timing_param_thigh_i_reg[6]
(.C(s_axi_aclk),
.CE(Bus2IIC_WrCE[2]),
.D(s_axi_wdata[6]),
.Q(\FSM_sequential_scl_state_reg[0] [6]),
.S(Bus2IIC_Reset));
FDSE \timing_param_thigh_i_reg[7]
(.C(s_axi_aclk),
.CE(Bus2IIC_WrCE[2]),
.D(s_axi_wdata[7]),
.Q(\FSM_sequential_scl_state_reg[0] [7]),
.S(Bus2IIC_Reset));
FDSE \timing_param_thigh_i_reg[8]
(.C(s_axi_aclk),
.CE(Bus2IIC_WrCE[2]),
.D(s_axi_wdata[8]),
.Q(timing_param_thigh_i[8]),
.S(Bus2IIC_Reset));
FDRE \timing_param_thigh_i_reg[9]
(.C(s_axi_aclk),
.CE(Bus2IIC_WrCE[2]),
.D(s_axi_wdata[9]),
.Q(timing_param_thigh_i[9]),
.R(Bus2IIC_Reset));
FDSE \timing_param_tlow_i_reg[0]
(.C(s_axi_aclk),
.CE(Bus2IIC_WrCE[1]),
.D(s_axi_wdata[0]),
.Q(\FSM_sequential_scl_state_reg[1]_0 ),
.S(Bus2IIC_Reset));
FDRE \timing_param_tlow_i_reg[1]
(.C(s_axi_aclk),
.CE(Bus2IIC_WrCE[1]),
.D(s_axi_wdata[1]),
.Q(timing_param_tlow_i[1]),
.R(Bus2IIC_Reset));
FDSE \timing_param_tlow_i_reg[2]
(.C(s_axi_aclk),
.CE(Bus2IIC_WrCE[1]),
.D(s_axi_wdata[2]),
.Q(timing_param_tlow_i[2]),
.S(Bus2IIC_Reset));
FDSE \timing_param_tlow_i_reg[3]
(.C(s_axi_aclk),
.CE(Bus2IIC_WrCE[1]),
.D(s_axi_wdata[3]),
.Q(timing_param_tlow_i[3]),
.S(Bus2IIC_Reset));
FDRE \timing_param_tlow_i_reg[4]
(.C(s_axi_aclk),
.CE(Bus2IIC_WrCE[1]),
.D(s_axi_wdata[4]),
.Q(timing_param_tlow_i[4]),
.R(Bus2IIC_Reset));
FDSE \timing_param_tlow_i_reg[5]
(.C(s_axi_aclk),
.CE(Bus2IIC_WrCE[1]),
.D(s_axi_wdata[5]),
.Q(timing_param_tlow_i[5]),
.S(Bus2IIC_Reset));
FDSE \timing_param_tlow_i_reg[6]
(.C(s_axi_aclk),
.CE(Bus2IIC_WrCE[1]),
.D(s_axi_wdata[6]),
.Q(timing_param_tlow_i[6]),
.S(Bus2IIC_Reset));
FDSE \timing_param_tlow_i_reg[7]
(.C(s_axi_aclk),
.CE(Bus2IIC_WrCE[1]),
.D(s_axi_wdata[7]),
.Q(timing_param_tlow_i[7]),
.S(Bus2IIC_Reset));
FDSE \timing_param_tlow_i_reg[8]
(.C(s_axi_aclk),
.CE(Bus2IIC_WrCE[1]),
.D(s_axi_wdata[8]),
.Q(timing_param_tlow_i[8]),
.S(Bus2IIC_Reset));
FDRE \timing_param_tlow_i_reg[9]
(.C(s_axi_aclk),
.CE(Bus2IIC_WrCE[1]),
.D(s_axi_wdata[9]),
.Q(timing_param_tlow_i[9]),
.R(Bus2IIC_Reset));
FDSE \timing_param_tsudat_i_reg[0]
(.C(s_axi_aclk),
.CE(Bus2IIC_WrCE[4]),
.D(s_axi_wdata[0]),
.Q(\s_axi_rdata_i_reg[8] [0]),
.S(Bus2IIC_Reset));
FDSE \timing_param_tsudat_i_reg[1]
(.C(s_axi_aclk),
.CE(Bus2IIC_WrCE[4]),
.D(s_axi_wdata[1]),
.Q(\s_axi_rdata_i_reg[8] [1]),
.S(Bus2IIC_Reset));
FDSE \timing_param_tsudat_i_reg[2]
(.C(s_axi_aclk),
.CE(Bus2IIC_WrCE[4]),
.D(s_axi_wdata[2]),
.Q(\s_axi_rdata_i_reg[8] [2]),
.S(Bus2IIC_Reset));
FDRE \timing_param_tsudat_i_reg[3]
(.C(s_axi_aclk),
.CE(Bus2IIC_WrCE[4]),
.D(s_axi_wdata[3]),
.Q(\s_axi_rdata_i_reg[8] [3]),
.R(Bus2IIC_Reset));
FDSE \timing_param_tsudat_i_reg[4]
(.C(s_axi_aclk),
.CE(Bus2IIC_WrCE[4]),
.D(s_axi_wdata[4]),
.Q(\s_axi_rdata_i_reg[8] [4]),
.S(Bus2IIC_Reset));
FDSE \timing_param_tsudat_i_reg[5]
(.C(s_axi_aclk),
.CE(Bus2IIC_WrCE[4]),
.D(s_axi_wdata[5]),
.Q(\s_axi_rdata_i_reg[8] [5]),
.S(Bus2IIC_Reset));
FDRE \timing_param_tsudat_i_reg[6]
(.C(s_axi_aclk),
.CE(Bus2IIC_WrCE[4]),
.D(s_axi_wdata[6]),
.Q(\s_axi_rdata_i_reg[8] [6]),
.R(Bus2IIC_Reset));
FDRE \timing_param_tsudat_i_reg[7]
(.C(s_axi_aclk),
.CE(Bus2IIC_WrCE[4]),
.D(s_axi_wdata[7]),
.Q(\s_axi_rdata_i_reg[8] [7]),
.R(Bus2IIC_Reset));
FDRE \timing_param_tsudat_i_reg[8]
(.C(s_axi_aclk),
.CE(Bus2IIC_WrCE[4]),
.D(s_axi_wdata[8]),
.Q(\s_axi_rdata_i_reg[8] [8]),
.R(Bus2IIC_Reset));
FDRE \timing_param_tsudat_i_reg[9]
(.C(s_axi_aclk),
.CE(Bus2IIC_WrCE[4]),
.D(s_axi_wdata[9]),
.Q(timing_param_tsudat_i),
.R(Bus2IIC_Reset));
FDRE \timing_param_tsusta_i_reg[0]
(.C(s_axi_aclk),
.CE(Bus2IIC_WrCE[7]),
.D(s_axi_wdata[0]),
.Q(timing_param_tsusta_i[0]),
.R(Bus2IIC_Reset));
FDSE \timing_param_tsusta_i_reg[1]
(.C(s_axi_aclk),
.CE(Bus2IIC_WrCE[7]),
.D(s_axi_wdata[1]),
.Q(timing_param_tsusta_i[1]),
.S(Bus2IIC_Reset));
FDRE \timing_param_tsusta_i_reg[2]
(.C(s_axi_aclk),
.CE(Bus2IIC_WrCE[7]),
.D(s_axi_wdata[2]),
.Q(timing_param_tsusta_i[2]),
.R(Bus2IIC_Reset));
FDSE \timing_param_tsusta_i_reg[3]
(.C(s_axi_aclk),
.CE(Bus2IIC_WrCE[7]),
.D(s_axi_wdata[3]),
.Q(timing_param_tsusta_i[3]),
.S(Bus2IIC_Reset));
FDSE \timing_param_tsusta_i_reg[4]
(.C(s_axi_aclk),
.CE(Bus2IIC_WrCE[7]),
.D(s_axi_wdata[4]),
.Q(\s_axi_rdata_i_reg[7] [0]),
.S(Bus2IIC_Reset));
FDSE \timing_param_tsusta_i_reg[5]
(.C(s_axi_aclk),
.CE(Bus2IIC_WrCE[7]),
.D(s_axi_wdata[5]),
.Q(\s_axi_rdata_i_reg[7] [1]),
.S(Bus2IIC_Reset));
FDRE \timing_param_tsusta_i_reg[6]
(.C(s_axi_aclk),
.CE(Bus2IIC_WrCE[7]),
.D(s_axi_wdata[6]),
.Q(\s_axi_rdata_i_reg[7] [2]),
.R(Bus2IIC_Reset));
FDRE \timing_param_tsusta_i_reg[7]
(.C(s_axi_aclk),
.CE(Bus2IIC_WrCE[7]),
.D(s_axi_wdata[7]),
.Q(\s_axi_rdata_i_reg[7] [3]),
.R(Bus2IIC_Reset));
FDRE \timing_param_tsusta_i_reg[8]
(.C(s_axi_aclk),
.CE(Bus2IIC_WrCE[7]),
.D(s_axi_wdata[8]),
.Q(timing_param_tsusta_i[8]),
.R(Bus2IIC_Reset));
FDSE \timing_param_tsusta_i_reg[9]
(.C(s_axi_aclk),
.CE(Bus2IIC_WrCE[7]),
.D(s_axi_wdata[9]),
.Q(timing_param_tsusta_i[9]),
.S(Bus2IIC_Reset));
FDRE \timing_param_tsusto_i_reg[0]
(.C(s_axi_aclk),
.CE(Bus2IIC_WrCE[6]),
.D(s_axi_wdata[0]),
.Q(sda_cout_reg_reg_0[0]),
.R(Bus2IIC_Reset));
FDRE \timing_param_tsusto_i_reg[1]
(.C(s_axi_aclk),
.CE(Bus2IIC_WrCE[6]),
.D(s_axi_wdata[1]),
.Q(sda_cout_reg_reg_0[1]),
.R(Bus2IIC_Reset));
FDSE \timing_param_tsusto_i_reg[2]
(.C(s_axi_aclk),
.CE(Bus2IIC_WrCE[6]),
.D(s_axi_wdata[2]),
.Q(sda_cout_reg_reg_0[2]),
.S(Bus2IIC_Reset));
FDRE \timing_param_tsusto_i_reg[3]
(.C(s_axi_aclk),
.CE(Bus2IIC_WrCE[6]),
.D(s_axi_wdata[3]),
.Q(sda_cout_reg_reg_0[3]),
.R(Bus2IIC_Reset));
FDSE \timing_param_tsusto_i_reg[4]
(.C(s_axi_aclk),
.CE(Bus2IIC_WrCE[6]),
.D(s_axi_wdata[4]),
.Q(sda_cout_reg_reg_0[4]),
.S(Bus2IIC_Reset));
FDSE \timing_param_tsusto_i_reg[5]
(.C(s_axi_aclk),
.CE(Bus2IIC_WrCE[6]),
.D(s_axi_wdata[5]),
.Q(sda_cout_reg_reg_0[5]),
.S(Bus2IIC_Reset));
FDSE \timing_param_tsusto_i_reg[6]
(.C(s_axi_aclk),
.CE(Bus2IIC_WrCE[6]),
.D(s_axi_wdata[6]),
.Q(sda_cout_reg_reg_0[6]),
.S(Bus2IIC_Reset));
FDSE \timing_param_tsusto_i_reg[7]
(.C(s_axi_aclk),
.CE(Bus2IIC_WrCE[6]),
.D(s_axi_wdata[7]),
.Q(sda_cout_reg_reg_0[7]),
.S(Bus2IIC_Reset));
FDSE \timing_param_tsusto_i_reg[8]
(.C(s_axi_aclk),
.CE(Bus2IIC_WrCE[6]),
.D(s_axi_wdata[8]),
.Q(timing_param_tsusto_i[8]),
.S(Bus2IIC_Reset));
FDRE \timing_param_tsusto_i_reg[9]
(.C(s_axi_aclk),
.CE(Bus2IIC_WrCE[6]),
.D(s_axi_wdata[9]),
.Q(timing_param_tsusto_i[9]),
.R(Bus2IIC_Reset));
endmodule
(* ORIG_REF_NAME = "shift8" *)
module system_axi_iic_0_0_shift8
(\LEVEL_1_GEN.master_sda_reg ,
Q,
slave_sda_reg,
shift_reg_en,
shift_reg_ld_reg,
txak,
out,
tx_under_prev_i_reg,
abgc_i_reg,
Tx_fifo_data,
SR,
s_axi_aclk,
shift_reg_ld_reg_0);
output \LEVEL_1_GEN.master_sda_reg ;
output [7:0]Q;
output slave_sda_reg;
input shift_reg_en;
input shift_reg_ld_reg;
input txak;
input [3:0]out;
input tx_under_prev_i_reg;
input abgc_i_reg;
input [6:0]Tx_fifo_data;
input [0:0]SR;
input s_axi_aclk;
input [0:0]shift_reg_ld_reg_0;
wire \LEVEL_1_GEN.master_sda_reg ;
wire [7:0]Q;
wire [0:0]SR;
wire [6:0]Tx_fifo_data;
wire abgc_i_reg;
wire \data_int[1]_i_1_n_0 ;
wire \data_int[2]_i_1_n_0 ;
wire \data_int[3]_i_1_n_0 ;
wire \data_int[4]_i_1_n_0 ;
wire \data_int[5]_i_1_n_0 ;
wire \data_int[6]_i_1_n_0 ;
wire \data_int[7]_i_1_n_0 ;
wire \data_int[7]_i_2_n_0 ;
wire [3:0]out;
wire s_axi_aclk;
wire shift_reg_en;
wire shift_reg_ld_reg;
wire [0:0]shift_reg_ld_reg_0;
wire slave_sda_reg;
wire tx_under_prev_i_reg;
wire txak;
LUT6 #(
.INIT(64'hFFFB0F0BFFFB000B))
\LEVEL_1_GEN.master_sda_i_1
(.I0(txak),
.I1(out[3]),
.I2(out[0]),
.I3(out[2]),
.I4(Q[7]),
.I5(tx_under_prev_i_reg),
.O(\LEVEL_1_GEN.master_sda_reg ));
LUT3 #(
.INIT(8'hB8))
\data_int[1]_i_1
(.I0(Tx_fifo_data[0]),
.I1(shift_reg_ld_reg),
.I2(Q[0]),
.O(\data_int[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT3 #(
.INIT(8'hB8))
\data_int[2]_i_1
(.I0(Tx_fifo_data[1]),
.I1(shift_reg_ld_reg),
.I2(Q[1]),
.O(\data_int[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT3 #(
.INIT(8'hB8))
\data_int[3]_i_1
(.I0(Tx_fifo_data[2]),
.I1(shift_reg_ld_reg),
.I2(Q[2]),
.O(\data_int[3]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT3 #(
.INIT(8'hB8))
\data_int[4]_i_1
(.I0(Tx_fifo_data[3]),
.I1(shift_reg_ld_reg),
.I2(Q[3]),
.O(\data_int[4]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT3 #(
.INIT(8'hB8))
\data_int[5]_i_1
(.I0(Tx_fifo_data[4]),
.I1(shift_reg_ld_reg),
.I2(Q[4]),
.O(\data_int[5]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT3 #(
.INIT(8'hB8))
\data_int[6]_i_1
(.I0(Tx_fifo_data[5]),
.I1(shift_reg_ld_reg),
.I2(Q[5]),
.O(\data_int[6]_i_1_n_0 ));
LUT2 #(
.INIT(4'hE))
\data_int[7]_i_1
(.I0(shift_reg_en),
.I1(shift_reg_ld_reg),
.O(\data_int[7]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT3 #(
.INIT(8'hB8))
\data_int[7]_i_2
(.I0(Tx_fifo_data[6]),
.I1(shift_reg_ld_reg),
.I2(Q[6]),
.O(\data_int[7]_i_2_n_0 ));
FDRE \data_int_reg[0]
(.C(s_axi_aclk),
.CE(\data_int[7]_i_1_n_0 ),
.D(shift_reg_ld_reg_0),
.Q(Q[0]),
.R(SR));
FDRE \data_int_reg[1]
(.C(s_axi_aclk),
.CE(\data_int[7]_i_1_n_0 ),
.D(\data_int[1]_i_1_n_0 ),
.Q(Q[1]),
.R(SR));
FDRE \data_int_reg[2]
(.C(s_axi_aclk),
.CE(\data_int[7]_i_1_n_0 ),
.D(\data_int[2]_i_1_n_0 ),
.Q(Q[2]),
.R(SR));
FDRE \data_int_reg[3]
(.C(s_axi_aclk),
.CE(\data_int[7]_i_1_n_0 ),
.D(\data_int[3]_i_1_n_0 ),
.Q(Q[3]),
.R(SR));
FDRE \data_int_reg[4]
(.C(s_axi_aclk),
.CE(\data_int[7]_i_1_n_0 ),
.D(\data_int[4]_i_1_n_0 ),
.Q(Q[4]),
.R(SR));
FDRE \data_int_reg[5]
(.C(s_axi_aclk),
.CE(\data_int[7]_i_1_n_0 ),
.D(\data_int[5]_i_1_n_0 ),
.Q(Q[5]),
.R(SR));
FDRE \data_int_reg[6]
(.C(s_axi_aclk),
.CE(\data_int[7]_i_1_n_0 ),
.D(\data_int[6]_i_1_n_0 ),
.Q(Q[6]),
.R(SR));
FDRE \data_int_reg[7]
(.C(s_axi_aclk),
.CE(\data_int[7]_i_1_n_0 ),
.D(\data_int[7]_i_2_n_0 ),
.Q(Q[7]),
.R(SR));
LUT6 #(
.INIT(64'hFBFFFBFB0B000B0B))
slave_sda_i_1
(.I0(Q[7]),
.I1(out[2]),
.I2(out[3]),
.I3(abgc_i_reg),
.I4(out[1]),
.I5(txak),
.O(slave_sda_reg));
endmodule
(* ORIG_REF_NAME = "shift8" *)
module system_axi_iic_0_0_shift8_1
(D,
Q,
shift_reg_ld0,
abgc_i_reg,
srw_i_reg,
\RD_FIFO_CNTRL.ro_prev_i_reg ,
out,
arb_lost_reg,
sda_sample,
abgc_i_reg_0,
master_slave_reg,
\cr_i_reg[1] ,
\FSM_onehot_state_reg[6] ,
srw_i_reg_0,
detect_start,
detect_stop_reg,
SR,
E,
s_axi_aclk,
scndry_out);
output [0:0]D;
output [7:0]Q;
output shift_reg_ld0;
output abgc_i_reg;
output srw_i_reg;
input \RD_FIFO_CNTRL.ro_prev_i_reg ;
input [2:0]out;
input arb_lost_reg;
input sda_sample;
input abgc_i_reg_0;
input master_slave_reg;
input [2:0]\cr_i_reg[1] ;
input \FSM_onehot_state_reg[6] ;
input [1:0]srw_i_reg_0;
input detect_start;
input detect_stop_reg;
input [0:0]SR;
input [0:0]E;
input s_axi_aclk;
input scndry_out;
wire [0:0]D;
wire [0:0]E;
wire \FSM_onehot_state[3]_i_3_n_0 ;
wire \FSM_onehot_state_reg[6] ;
wire [7:0]Q;
wire \RD_FIFO_CNTRL.ro_prev_i_reg ;
wire [0:0]SR;
wire abgc_i_i_2_n_0;
wire abgc_i_i_3_n_0;
wire abgc_i_reg;
wire abgc_i_reg_0;
wire arb_lost_reg;
wire [2:0]\cr_i_reg[1] ;
wire detect_start;
wire detect_stop_reg;
wire master_slave_reg;
wire [2:0]out;
wire s_axi_aclk;
wire scndry_out;
wire sda_sample;
wire shift_reg_ld0;
wire srw_i_reg;
wire [1:0]srw_i_reg_0;
LUT5 #(
.INIT(32'h000000E2))
\FSM_onehot_state[3]_i_1
(.I0(\RD_FIFO_CNTRL.ro_prev_i_reg ),
.I1(out[2]),
.I2(\FSM_onehot_state[3]_i_3_n_0 ),
.I3(out[1]),
.I4(out[0]),
.O(D));
LUT6 #(
.INIT(64'h0000000111110001))
\FSM_onehot_state[3]_i_3
(.I0(arb_lost_reg),
.I1(sda_sample),
.I2(abgc_i_reg_0),
.I3(Q[0]),
.I4(master_slave_reg),
.I5(\cr_i_reg[1] [1]),
.O(\FSM_onehot_state[3]_i_3_n_0 ));
LUT6 #(
.INIT(64'h0000000000AE0000))
abgc_i_i_1
(.I0(srw_i_reg_0[0]),
.I1(abgc_i_i_2_n_0),
.I2(abgc_i_i_3_n_0),
.I3(detect_start),
.I4(\cr_i_reg[1] [0]),
.I5(detect_stop_reg),
.O(abgc_i_reg));
LUT4 #(
.INIT(16'h0001))
abgc_i_i_2
(.I0(Q[7]),
.I1(Q[0]),
.I2(Q[6]),
.I3(Q[1]),
.O(abgc_i_i_2_n_0));
LUT6 #(
.INIT(64'hFFFFFFFDFFFFFFFF))
abgc_i_i_3
(.I0(out[2]),
.I1(Q[5]),
.I2(Q[2]),
.I3(Q[3]),
.I4(Q[4]),
.I5(\cr_i_reg[1] [2]),
.O(abgc_i_i_3_n_0));
FDRE \data_int_reg[0]
(.C(s_axi_aclk),
.CE(E),
.D(scndry_out),
.Q(Q[0]),
.R(SR));
FDRE \data_int_reg[1]
(.C(s_axi_aclk),
.CE(E),
.D(Q[0]),
.Q(Q[1]),
.R(SR));
FDRE \data_int_reg[2]
(.C(s_axi_aclk),
.CE(E),
.D(Q[1]),
.Q(Q[2]),
.R(SR));
FDRE \data_int_reg[3]
(.C(s_axi_aclk),
.CE(E),
.D(Q[2]),
.Q(Q[3]),
.R(SR));
FDRE \data_int_reg[4]
(.C(s_axi_aclk),
.CE(E),
.D(Q[3]),
.Q(Q[4]),
.R(SR));
FDRE \data_int_reg[5]
(.C(s_axi_aclk),
.CE(E),
.D(Q[4]),
.Q(Q[5]),
.R(SR));
FDRE \data_int_reg[6]
(.C(s_axi_aclk),
.CE(E),
.D(Q[5]),
.Q(Q[6]),
.R(SR));
FDRE \data_int_reg[7]
(.C(s_axi_aclk),
.CE(E),
.D(Q[6]),
.Q(Q[7]),
.R(SR));
LUT5 #(
.INIT(32'hFFFFB800))
shift_reg_ld_i_1
(.I0(\cr_i_reg[1] [1]),
.I1(master_slave_reg),
.I2(Q[0]),
.I3(out[2]),
.I4(\FSM_onehot_state_reg[6] ),
.O(shift_reg_ld0));
LUT4 #(
.INIT(16'hE200))
srw_i_i_1
(.I0(srw_i_reg_0[1]),
.I1(out[2]),
.I2(Q[0]),
.I3(\cr_i_reg[1] [0]),
.O(srw_i_reg));
endmodule
(* ORIG_REF_NAME = "slave_attachment" *)
module system_axi_iic_0_0_slave_attachment
(s_axi_rresp,
s_axi_rvalid,
s_axi_bvalid,
s_axi_bresp,
Q,
AXI_IP2Bus_WrAck2_reg,
s_axi_wready,
s_axi_arready,
irpt_wrack,
\GEN_IP_IRPT_STATUS_REG[7].GEN_REG_STATUS.ip_irpt_status_reg_reg[7] ,
\GEN_IP_IRPT_STATUS_REG[6].GEN_REG_STATUS.ip_irpt_status_reg_reg[6] ,
\GEN_IP_IRPT_STATUS_REG[5].GEN_REG_STATUS.ip_irpt_status_reg_reg[5] ,
\GEN_IP_IRPT_STATUS_REG[4].GEN_REG_STATUS.ip_irpt_status_reg_reg[4] ,
\GEN_IP_IRPT_STATUS_REG[3].GEN_REG_STATUS.ip_irpt_status_reg_reg[3] ,
\GEN_IP_IRPT_STATUS_REG[2].GEN_REG_STATUS.ip_irpt_status_reg_reg[2] ,
\GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1] ,
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0] ,
reset_trig0,
sw_rst_cond,
Bus2IIC_RdCE,
E,
\cr_i_reg[4] ,
Bus2IIC_WrCE,
AXI_IP2Bus_RdAck20,
ipif_glbl_irpt_enable_reg_reg,
\GPO_GEN.gpo_i_reg[31] ,
s_axi_rdata,
AXI_Bus2IP_Reset,
s_axi_aclk,
\timing_param_tsudat_i_reg[5] ,
\cr_i_reg[4]_0 ,
\timing_param_tlow_i_reg[0] ,
\RD_FIFO_CNTRL.rc_fifo_pirq_i_reg[7] ,
AXI_IP2Bus_RdAck1,
AXI_IP2Bus_RdAck2,
s_axi_aresetn,
s_axi_arvalid,
AXI_IP2Bus_WrAck1,
AXI_IP2Bus_WrAck2,
s_axi_rready,
s_axi_bready,
s_axi_wvalid,
s_axi_awvalid,
s_axi_araddr,
s_axi_awaddr,
s_axi_wdata,
irpt_wrack_d1,
IIC2Bus_IntrEvent,
p_1_in,
p_1_in2_in,
p_1_in5_in,
p_1_in8_in,
p_1_in11_in,
p_1_in14_in,
p_1_in17_in,
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0 ,
sw_rst_cond_d1,
\ip_irpt_enable_reg_reg[7] ,
\timing_param_thdsta_i_reg[0] ,
\adr_i_reg[6] ,
\adr_i_reg[5] ,
\timing_param_tbuf_i_reg[3] ,
\adr_i_reg[4] ,
\adr_i_reg[3] ,
\adr_i_reg[2] ,
\adr_i_reg[1] ,
\timing_param_tsudat_i_reg[6] ,
\adr_i_reg[0] ,
\timing_param_tsudat_i_reg[7] ,
Tx_fifo_data,
\timing_param_tsusta_i_reg[7] ,
\timing_param_tsusto_i_reg[7] ,
Rc_fifo_data,
\timing_param_thigh_i_reg[7] ,
\timing_param_tbuf_i_reg[1] ,
\timing_param_tbuf_i_reg[0] ,
\timing_param_tbuf_i_reg[2] ,
\sr_i_reg[2] ,
\timing_param_thddat_i_reg[5] ,
\timing_param_tbuf_i_reg[7] ,
Tx_addr,
\GPO_GEN.gpo_i_reg[31]_0 ,
\bus2ip_addr_i_reg[2]_0 ,
\bus2ip_addr_i_reg[2]_1 ,
cr_txModeSelect_set,
cr_txModeSelect_clr,
ipif_glbl_irpt_enable_reg,
\sr_i_reg[4] ,
\sr_i_reg[5] ,
\IIC2Bus_IntrEvent_reg[5] ,
gpo);
output [0:0]s_axi_rresp;
output s_axi_rvalid;
output s_axi_bvalid;
output [0:0]s_axi_bresp;
output [4:0]Q;
output AXI_IP2Bus_WrAck2_reg;
output s_axi_wready;
output s_axi_arready;
output irpt_wrack;
output \GEN_IP_IRPT_STATUS_REG[7].GEN_REG_STATUS.ip_irpt_status_reg_reg[7] ;
output \GEN_IP_IRPT_STATUS_REG[6].GEN_REG_STATUS.ip_irpt_status_reg_reg[6] ;
output \GEN_IP_IRPT_STATUS_REG[5].GEN_REG_STATUS.ip_irpt_status_reg_reg[5] ;
output \GEN_IP_IRPT_STATUS_REG[4].GEN_REG_STATUS.ip_irpt_status_reg_reg[4] ;
output \GEN_IP_IRPT_STATUS_REG[3].GEN_REG_STATUS.ip_irpt_status_reg_reg[3] ;
output \GEN_IP_IRPT_STATUS_REG[2].GEN_REG_STATUS.ip_irpt_status_reg_reg[2] ;
output \GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1] ;
output \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0] ;
output reset_trig0;
output sw_rst_cond;
output [0:0]Bus2IIC_RdCE;
output [0:0]E;
output [0:0]\cr_i_reg[4] ;
output [11:0]Bus2IIC_WrCE;
output AXI_IP2Bus_RdAck20;
output ipif_glbl_irpt_enable_reg_reg;
output \GPO_GEN.gpo_i_reg[31] ;
output [10:0]s_axi_rdata;
input AXI_Bus2IP_Reset;
input s_axi_aclk;
input [5:0]\timing_param_tsudat_i_reg[5] ;
input [1:0]\cr_i_reg[4]_0 ;
input [0:0]\timing_param_tlow_i_reg[0] ;
input [0:0]\RD_FIFO_CNTRL.rc_fifo_pirq_i_reg[7] ;
input AXI_IP2Bus_RdAck1;
input AXI_IP2Bus_RdAck2;
input s_axi_aresetn;
input s_axi_arvalid;
input AXI_IP2Bus_WrAck1;
input AXI_IP2Bus_WrAck2;
input s_axi_rready;
input s_axi_bready;
input s_axi_wvalid;
input s_axi_awvalid;
input [8:0]s_axi_araddr;
input [8:0]s_axi_awaddr;
input [8:0]s_axi_wdata;
input irpt_wrack_d1;
input [0:7]IIC2Bus_IntrEvent;
input p_1_in;
input p_1_in2_in;
input p_1_in5_in;
input p_1_in8_in;
input p_1_in11_in;
input p_1_in14_in;
input p_1_in17_in;
input \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0 ;
input sw_rst_cond_d1;
input [7:0]\ip_irpt_enable_reg_reg[7] ;
input [0:0]\timing_param_thdsta_i_reg[0] ;
input \adr_i_reg[6] ;
input \adr_i_reg[5] ;
input \timing_param_tbuf_i_reg[3] ;
input \adr_i_reg[4] ;
input \adr_i_reg[3] ;
input \adr_i_reg[2] ;
input \adr_i_reg[1] ;
input \timing_param_tsudat_i_reg[6] ;
input \adr_i_reg[0] ;
input \timing_param_tsudat_i_reg[7] ;
input [3:0]Tx_fifo_data;
input [3:0]\timing_param_tsusta_i_reg[7] ;
input [7:0]\timing_param_tsusto_i_reg[7] ;
input [0:7]Rc_fifo_data;
input [7:0]\timing_param_thigh_i_reg[7] ;
input \timing_param_tbuf_i_reg[1] ;
input \timing_param_tbuf_i_reg[0] ;
input \timing_param_tbuf_i_reg[2] ;
input [1:0]\sr_i_reg[2] ;
input [1:0]\timing_param_thddat_i_reg[5] ;
input [3:0]\timing_param_tbuf_i_reg[7] ;
input [0:3]Tx_addr;
input \GPO_GEN.gpo_i_reg[31]_0 ;
input \bus2ip_addr_i_reg[2]_0 ;
input \bus2ip_addr_i_reg[2]_1 ;
input cr_txModeSelect_set;
input cr_txModeSelect_clr;
input ipif_glbl_irpt_enable_reg;
input \sr_i_reg[4] ;
input \sr_i_reg[5] ;
input \IIC2Bus_IntrEvent_reg[5] ;
input [0:0]gpo;
wire AXI_Bus2IP_Reset;
wire [24:31]AXI_IP2Bus_Data;
wire AXI_IP2Bus_Error;
wire AXI_IP2Bus_RdAck1;
wire AXI_IP2Bus_RdAck2;
wire AXI_IP2Bus_RdAck20;
wire AXI_IP2Bus_WrAck1;
wire AXI_IP2Bus_WrAck2;
wire AXI_IP2Bus_WrAck2_reg;
wire [0:1]Bus2IIC_Addr;
wire [0:0]Bus2IIC_RdCE;
wire [11:0]Bus2IIC_WrCE;
wire [0:0]E;
wire \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0] ;
wire \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0 ;
wire \GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1] ;
wire \GEN_IP_IRPT_STATUS_REG[2].GEN_REG_STATUS.ip_irpt_status_reg_reg[2] ;
wire \GEN_IP_IRPT_STATUS_REG[3].GEN_REG_STATUS.ip_irpt_status_reg_reg[3] ;
wire \GEN_IP_IRPT_STATUS_REG[4].GEN_REG_STATUS.ip_irpt_status_reg_reg[4] ;
wire \GEN_IP_IRPT_STATUS_REG[5].GEN_REG_STATUS.ip_irpt_status_reg_reg[5] ;
wire \GEN_IP_IRPT_STATUS_REG[6].GEN_REG_STATUS.ip_irpt_status_reg_reg[6] ;
wire \GEN_IP_IRPT_STATUS_REG[7].GEN_REG_STATUS.ip_irpt_status_reg_reg[7] ;
wire \GPO_GEN.gpo_i_reg[31] ;
wire \GPO_GEN.gpo_i_reg[31]_0 ;
wire [22:23]IIC2Bus_Data;
wire [0:7]IIC2Bus_IntrEvent;
wire \IIC2Bus_IntrEvent_reg[5] ;
wire [3:0]\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 ;
wire I_DECODER_n_0;
wire I_DECODER_n_1;
wire I_DECODER_n_3;
wire I_DECODER_n_47;
wire I_DECODER_n_5;
wire [0:0]Intr2Bus_DBus;
wire [4:0]Q;
wire [0:0]\RD_FIFO_CNTRL.rc_fifo_pirq_i_reg[7] ;
wire [0:7]Rc_fifo_data;
wire [0:3]Tx_addr;
wire [3:0]Tx_fifo_data;
wire \adr_i_reg[0] ;
wire \adr_i_reg[1] ;
wire \adr_i_reg[2] ;
wire \adr_i_reg[3] ;
wire \adr_i_reg[4] ;
wire \adr_i_reg[5] ;
wire \adr_i_reg[6] ;
wire \bus2ip_addr_i[0]_i_1_n_0 ;
wire \bus2ip_addr_i[1]_i_1_n_0 ;
wire \bus2ip_addr_i[2]_i_1_n_0 ;
wire \bus2ip_addr_i[3]_i_1_n_0 ;
wire \bus2ip_addr_i[4]_i_1_n_0 ;
wire \bus2ip_addr_i[5]_i_1_n_0 ;
wire \bus2ip_addr_i[6]_i_1_n_0 ;
wire \bus2ip_addr_i[7]_i_1_n_0 ;
wire \bus2ip_addr_i[8]_i_1_n_0 ;
wire \bus2ip_addr_i[8]_i_2_n_0 ;
wire \bus2ip_addr_i_reg[2]_0 ;
wire \bus2ip_addr_i_reg[2]_1 ;
wire \bus2ip_addr_i_reg_n_0_[0] ;
wire \bus2ip_addr_i_reg_n_0_[1] ;
wire bus2ip_rnw_i06_out;
wire bus2ip_rnw_i_reg_n_0;
wire clear;
wire [0:0]\cr_i_reg[4] ;
wire [1:0]\cr_i_reg[4]_0 ;
wire cr_txModeSelect_clr;
wire cr_txModeSelect_set;
wire [0:0]gpo;
wire [7:0]\ip_irpt_enable_reg_reg[7] ;
wire ipif_glbl_irpt_enable_reg;
wire ipif_glbl_irpt_enable_reg_reg;
wire irpt_wrack;
wire irpt_wrack_d1;
wire is_read;
wire is_read_i_1_n_0;
wire is_write;
wire is_write_i_1_n_0;
wire is_write_reg_n_0;
wire p_1_in;
wire p_1_in11_in;
wire p_1_in14_in;
wire p_1_in17_in;
wire p_1_in2_in;
wire p_1_in5_in;
wire p_1_in8_in;
wire [3:0]plusOp;
wire reset_trig0;
wire rst;
wire s_axi_aclk;
wire [8:0]s_axi_araddr;
wire s_axi_aresetn;
wire s_axi_arready;
wire s_axi_arvalid;
wire [8:0]s_axi_awaddr;
wire s_axi_awvalid;
wire s_axi_bready;
wire [0:0]s_axi_bresp;
wire s_axi_bvalid;
wire s_axi_bvalid_i_i_1_n_0;
wire [10:0]s_axi_rdata;
wire s_axi_rdata_i;
wire \s_axi_rdata_i[0]_i_3_n_0 ;
wire \s_axi_rdata_i[0]_i_4_n_0 ;
wire \s_axi_rdata_i[0]_i_5_n_0 ;
wire \s_axi_rdata_i[0]_i_7_n_0 ;
wire \s_axi_rdata_i[0]_i_9_n_0 ;
wire \s_axi_rdata_i[1]_i_3_n_0 ;
wire \s_axi_rdata_i[1]_i_4_n_0 ;
wire \s_axi_rdata_i[1]_i_8_n_0 ;
wire \s_axi_rdata_i[1]_i_9_n_0 ;
wire \s_axi_rdata_i[2]_i_4_n_0 ;
wire \s_axi_rdata_i[2]_i_5_n_0 ;
wire \s_axi_rdata_i[2]_i_8_n_0 ;
wire \s_axi_rdata_i[3]_i_3_n_0 ;
wire \s_axi_rdata_i[3]_i_6_n_0 ;
wire \s_axi_rdata_i[3]_i_7_n_0 ;
wire \s_axi_rdata_i[3]_i_8_n_0 ;
wire \s_axi_rdata_i[4]_i_3_n_0 ;
wire \s_axi_rdata_i[4]_i_5_n_0 ;
wire \s_axi_rdata_i[4]_i_6_n_0 ;
wire \s_axi_rdata_i[4]_i_7_n_0 ;
wire \s_axi_rdata_i[4]_i_9_n_0 ;
wire \s_axi_rdata_i[5]_i_3_n_0 ;
wire \s_axi_rdata_i[5]_i_5_n_0 ;
wire \s_axi_rdata_i[5]_i_6_n_0 ;
wire \s_axi_rdata_i[5]_i_7_n_0 ;
wire \s_axi_rdata_i[5]_i_9_n_0 ;
wire \s_axi_rdata_i[6]_i_3_n_0 ;
wire \s_axi_rdata_i[6]_i_6_n_0 ;
wire \s_axi_rdata_i[6]_i_7_n_0 ;
wire \s_axi_rdata_i[7]_i_3_n_0 ;
wire \s_axi_rdata_i[7]_i_6_n_0 ;
wire \s_axi_rdata_i[7]_i_7_n_0 ;
wire s_axi_rready;
wire [0:0]s_axi_rresp;
wire s_axi_rvalid;
wire s_axi_rvalid_i0;
wire s_axi_rvalid_i_i_1_n_0;
wire [8:0]s_axi_wdata;
wire s_axi_wready;
wire s_axi_wvalid;
wire [1:0]\sr_i_reg[2] ;
wire \sr_i_reg[4] ;
wire \sr_i_reg[5] ;
wire start2;
wire start2_i_1_n_0;
wire [1:0]state;
wire \state[0]_i_1_n_0 ;
wire \state[0]_i_2_n_0 ;
wire \state[1]_i_1_n_0 ;
wire \state[1]_i_2_n_0 ;
wire \state[1]_i_3_n_0 ;
wire sw_rst_cond;
wire sw_rst_cond_d1;
wire \timing_param_tbuf_i_reg[0] ;
wire \timing_param_tbuf_i_reg[1] ;
wire \timing_param_tbuf_i_reg[2] ;
wire \timing_param_tbuf_i_reg[3] ;
wire [3:0]\timing_param_tbuf_i_reg[7] ;
wire [1:0]\timing_param_thddat_i_reg[5] ;
wire [0:0]\timing_param_thdsta_i_reg[0] ;
wire [7:0]\timing_param_thigh_i_reg[7] ;
wire [0:0]\timing_param_tlow_i_reg[0] ;
wire [5:0]\timing_param_tsudat_i_reg[5] ;
wire \timing_param_tsudat_i_reg[6] ;
wire \timing_param_tsudat_i_reg[7] ;
wire [3:0]\timing_param_tsusta_i_reg[7] ;
wire [7:0]\timing_param_tsusto_i_reg[7] ;
(* SOFT_HLUTNM = "soft_lutpair52" *)
LUT1 #(
.INIT(2'h1))
\INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.O(plusOp[0]));
(* SOFT_HLUTNM = "soft_lutpair52" *)
LUT2 #(
.INIT(4'h6))
\INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
.O(plusOp[1]));
(* SOFT_HLUTNM = "soft_lutpair51" *)
LUT3 #(
.INIT(8'h6A))
\INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]),
.I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
.I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.O(plusOp[2]));
LUT2 #(
.INIT(4'h9))
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1
(.I0(state[0]),
.I1(state[1]),
.O(clear));
(* SOFT_HLUTNM = "soft_lutpair51" *)
LUT4 #(
.INIT(16'h6AAA))
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [3]),
.I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
.I3(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]),
.O(plusOp[3]));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(plusOp[0]),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.R(clear));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(plusOp[1]),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
.R(clear));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[2]
(.C(s_axi_aclk),
.CE(1'b1),
.D(plusOp[2]),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]),
.R(clear));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]
(.C(s_axi_aclk),
.CE(1'b1),
.D(plusOp[3]),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [3]),
.R(clear));
system_axi_iic_0_0_address_decoder I_DECODER
(.AXI_IP2Bus_Error(AXI_IP2Bus_Error),
.AXI_IP2Bus_RdAck1(AXI_IP2Bus_RdAck1),
.AXI_IP2Bus_RdAck2(AXI_IP2Bus_RdAck2),
.AXI_IP2Bus_RdAck20(AXI_IP2Bus_RdAck20),
.AXI_IP2Bus_WrAck1(AXI_IP2Bus_WrAck1),
.AXI_IP2Bus_WrAck2(AXI_IP2Bus_WrAck2),
.AXI_IP2Bus_WrAck2_reg(AXI_IP2Bus_WrAck2_reg),
.\Addr_Counters[1].FDRE_I (\s_axi_rdata_i[1]_i_3_n_0 ),
.\Addr_Counters[2].FDRE_I (\s_axi_rdata_i[2]_i_4_n_0 ),
.Bus2IIC_RdCE(Bus2IIC_RdCE),
.Bus2IIC_WrCE(Bus2IIC_WrCE),
.D({Intr2Bus_DBus,IIC2Bus_Data[22],IIC2Bus_Data[23],AXI_IP2Bus_Data[24],AXI_IP2Bus_Data[25],AXI_IP2Bus_Data[26],AXI_IP2Bus_Data[27],AXI_IP2Bus_Data[28],AXI_IP2Bus_Data[29],AXI_IP2Bus_Data[30],AXI_IP2Bus_Data[31]}),
.E(E),
.\GEN_BKEND_CE_REGISTERS[21].ce_out_i_reg[21]_0 (I_DECODER_n_1),
.\GEN_BKEND_CE_REGISTERS[23].ce_out_i_reg[23]_0 (I_DECODER_n_0),
.\GEN_BKEND_CE_REGISTERS[26].ce_out_i_reg[26]_0 (I_DECODER_n_5),
.\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0] (\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0] ),
.\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0 (\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0 ),
.\GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1] (\GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1] ),
.\GEN_IP_IRPT_STATUS_REG[2].GEN_REG_STATUS.ip_irpt_status_reg_reg[2] (\GEN_IP_IRPT_STATUS_REG[2].GEN_REG_STATUS.ip_irpt_status_reg_reg[2] ),
.\GEN_IP_IRPT_STATUS_REG[3].GEN_REG_STATUS.ip_irpt_status_reg_reg[3] (\GEN_IP_IRPT_STATUS_REG[3].GEN_REG_STATUS.ip_irpt_status_reg_reg[3] ),
.\GEN_IP_IRPT_STATUS_REG[4].GEN_REG_STATUS.ip_irpt_status_reg_reg[4] (\GEN_IP_IRPT_STATUS_REG[4].GEN_REG_STATUS.ip_irpt_status_reg_reg[4] ),
.\GEN_IP_IRPT_STATUS_REG[5].GEN_REG_STATUS.ip_irpt_status_reg_reg[5] (\GEN_IP_IRPT_STATUS_REG[5].GEN_REG_STATUS.ip_irpt_status_reg_reg[5] ),
.\GEN_IP_IRPT_STATUS_REG[6].GEN_REG_STATUS.ip_irpt_status_reg_reg[6] (\GEN_IP_IRPT_STATUS_REG[6].GEN_REG_STATUS.ip_irpt_status_reg_reg[6] ),
.\GEN_IP_IRPT_STATUS_REG[7].GEN_REG_STATUS.ip_irpt_status_reg_reg[7] (\GEN_IP_IRPT_STATUS_REG[7].GEN_REG_STATUS.ip_irpt_status_reg_reg[7] ),
.\GPO_GEN.gpo_i_reg[31] (\GPO_GEN.gpo_i_reg[31] ),
.IIC2Bus_IntrEvent(IIC2Bus_IntrEvent),
.\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] (\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 ),
.\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 (I_DECODER_n_3),
.Q(start2),
.\adr_i_reg[0] (\adr_i_reg[0] ),
.\adr_i_reg[1] (\adr_i_reg[1] ),
.\adr_i_reg[2] (\adr_i_reg[2] ),
.\adr_i_reg[3] (\adr_i_reg[3] ),
.\adr_i_reg[4] (\adr_i_reg[4] ),
.\adr_i_reg[5] (\adr_i_reg[5] ),
.\adr_i_reg[6] (\adr_i_reg[6] ),
.\bus2ip_addr_i_reg[2] (\s_axi_rdata_i[3]_i_3_n_0 ),
.\bus2ip_addr_i_reg[2]_0 (\bus2ip_addr_i_reg[2]_0 ),
.\bus2ip_addr_i_reg[2]_1 (\bus2ip_addr_i_reg[2]_1 ),
.\bus2ip_addr_i_reg[5] (\s_axi_rdata_i[4]_i_3_n_0 ),
.\bus2ip_addr_i_reg[5]_0 (\s_axi_rdata_i[4]_i_5_n_0 ),
.\bus2ip_addr_i_reg[5]_1 (\s_axi_rdata_i[5]_i_3_n_0 ),
.\bus2ip_addr_i_reg[5]_2 (\s_axi_rdata_i[5]_i_5_n_0 ),
.\bus2ip_addr_i_reg[5]_3 (\s_axi_rdata_i[6]_i_3_n_0 ),
.\bus2ip_addr_i_reg[5]_4 (\s_axi_rdata_i[7]_i_3_n_0 ),
.\bus2ip_addr_i_reg[6] (\s_axi_rdata_i[0]_i_3_n_0 ),
.\bus2ip_addr_i_reg[8] ({Bus2IIC_Addr[0],Bus2IIC_Addr[1],Q,\bus2ip_addr_i_reg_n_0_[1] ,\bus2ip_addr_i_reg_n_0_[0] }),
.bus2ip_rnw_i_reg(bus2ip_rnw_i_reg_n_0),
.\cr_i_reg[4] (\cr_i_reg[4] ),
.\cr_i_reg[4]_0 (\cr_i_reg[4]_0 [1]),
.cr_txModeSelect_clr(cr_txModeSelect_clr),
.cr_txModeSelect_set(cr_txModeSelect_set),
.gpo(gpo),
.\ip_irpt_enable_reg_reg[7] (\ip_irpt_enable_reg_reg[7] ),
.ipif_glbl_irpt_enable_reg(ipif_glbl_irpt_enable_reg),
.ipif_glbl_irpt_enable_reg_reg(ipif_glbl_irpt_enable_reg_reg),
.irpt_wrack(irpt_wrack),
.irpt_wrack_d1(irpt_wrack_d1),
.is_read(is_read),
.is_write_reg(is_write_reg_n_0),
.p_1_in(p_1_in),
.p_1_in11_in(p_1_in11_in),
.p_1_in14_in(p_1_in14_in),
.p_1_in17_in(p_1_in17_in),
.p_1_in2_in(p_1_in2_in),
.p_1_in5_in(p_1_in5_in),
.p_1_in8_in(p_1_in8_in),
.reset_trig0(reset_trig0),
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_bresp(s_axi_bresp),
.\s_axi_bresp_i_reg[1] (I_DECODER_n_47),
.s_axi_wdata(s_axi_wdata),
.s_axi_wready(s_axi_wready),
.\state_reg[1] (state),
.sw_rst_cond(sw_rst_cond),
.sw_rst_cond_d1(sw_rst_cond_d1),
.\timing_param_tbuf_i_reg[3] (\timing_param_tbuf_i_reg[3] ),
.\timing_param_thdsta_i_reg[0] (\s_axi_rdata_i[0]_i_4_n_0 ),
.\timing_param_thigh_i_reg[0] (\s_axi_rdata_i[0]_i_5_n_0 ),
.\timing_param_thigh_i_reg[1] (\s_axi_rdata_i[1]_i_4_n_0 ),
.\timing_param_thigh_i_reg[2] (\s_axi_rdata_i[2]_i_5_n_0 ),
.\timing_param_tsudat_i_reg[6] (\timing_param_tsudat_i_reg[6] ),
.\timing_param_tsudat_i_reg[7] (\timing_param_tsudat_i_reg[7] ));
LUT5 #(
.INIT(32'hFFFB0008))
\bus2ip_addr_i[0]_i_1
(.I0(s_axi_araddr[0]),
.I1(s_axi_arvalid),
.I2(state[0]),
.I3(state[1]),
.I4(s_axi_awaddr[0]),
.O(\bus2ip_addr_i[0]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\bus2ip_addr_i[1]_i_1
(.I0(s_axi_araddr[1]),
.I1(s_axi_arvalid),
.I2(state[0]),
.I3(state[1]),
.I4(s_axi_awaddr[1]),
.O(\bus2ip_addr_i[1]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\bus2ip_addr_i[2]_i_1
(.I0(s_axi_araddr[2]),
.I1(s_axi_arvalid),
.I2(state[0]),
.I3(state[1]),
.I4(s_axi_awaddr[2]),
.O(\bus2ip_addr_i[2]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\bus2ip_addr_i[3]_i_1
(.I0(s_axi_araddr[3]),
.I1(s_axi_arvalid),
.I2(state[0]),
.I3(state[1]),
.I4(s_axi_awaddr[3]),
.O(\bus2ip_addr_i[3]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair48" *)
LUT5 #(
.INIT(32'hFFFB0008))
\bus2ip_addr_i[4]_i_1
(.I0(s_axi_araddr[4]),
.I1(s_axi_arvalid),
.I2(state[0]),
.I3(state[1]),
.I4(s_axi_awaddr[4]),
.O(\bus2ip_addr_i[4]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\bus2ip_addr_i[5]_i_1
(.I0(s_axi_araddr[5]),
.I1(s_axi_arvalid),
.I2(state[0]),
.I3(state[1]),
.I4(s_axi_awaddr[5]),
.O(\bus2ip_addr_i[5]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\bus2ip_addr_i[6]_i_1
(.I0(s_axi_araddr[6]),
.I1(s_axi_arvalid),
.I2(state[0]),
.I3(state[1]),
.I4(s_axi_awaddr[6]),
.O(\bus2ip_addr_i[6]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\bus2ip_addr_i[7]_i_1
(.I0(s_axi_araddr[7]),
.I1(s_axi_arvalid),
.I2(state[0]),
.I3(state[1]),
.I4(s_axi_awaddr[7]),
.O(\bus2ip_addr_i[7]_i_1_n_0 ));
LUT5 #(
.INIT(32'h000000EA))
\bus2ip_addr_i[8]_i_1
(.I0(s_axi_arvalid),
.I1(s_axi_wvalid),
.I2(s_axi_awvalid),
.I3(state[1]),
.I4(state[0]),
.O(\bus2ip_addr_i[8]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\bus2ip_addr_i[8]_i_2
(.I0(s_axi_araddr[8]),
.I1(s_axi_arvalid),
.I2(state[0]),
.I3(state[1]),
.I4(s_axi_awaddr[8]),
.O(\bus2ip_addr_i[8]_i_2_n_0 ));
FDRE \bus2ip_addr_i_reg[0]
(.C(s_axi_aclk),
.CE(\bus2ip_addr_i[8]_i_1_n_0 ),
.D(\bus2ip_addr_i[0]_i_1_n_0 ),
.Q(\bus2ip_addr_i_reg_n_0_[0] ),
.R(rst));
FDRE \bus2ip_addr_i_reg[1]
(.C(s_axi_aclk),
.CE(\bus2ip_addr_i[8]_i_1_n_0 ),
.D(\bus2ip_addr_i[1]_i_1_n_0 ),
.Q(\bus2ip_addr_i_reg_n_0_[1] ),
.R(rst));
FDRE \bus2ip_addr_i_reg[2]
(.C(s_axi_aclk),
.CE(\bus2ip_addr_i[8]_i_1_n_0 ),
.D(\bus2ip_addr_i[2]_i_1_n_0 ),
.Q(Q[0]),
.R(rst));
FDRE \bus2ip_addr_i_reg[3]
(.C(s_axi_aclk),
.CE(\bus2ip_addr_i[8]_i_1_n_0 ),
.D(\bus2ip_addr_i[3]_i_1_n_0 ),
.Q(Q[1]),
.R(rst));
FDRE \bus2ip_addr_i_reg[4]
(.C(s_axi_aclk),
.CE(\bus2ip_addr_i[8]_i_1_n_0 ),
.D(\bus2ip_addr_i[4]_i_1_n_0 ),
.Q(Q[2]),
.R(rst));
FDRE \bus2ip_addr_i_reg[5]
(.C(s_axi_aclk),
.CE(\bus2ip_addr_i[8]_i_1_n_0 ),
.D(\bus2ip_addr_i[5]_i_1_n_0 ),
.Q(Q[3]),
.R(rst));
FDRE \bus2ip_addr_i_reg[6]
(.C(s_axi_aclk),
.CE(\bus2ip_addr_i[8]_i_1_n_0 ),
.D(\bus2ip_addr_i[6]_i_1_n_0 ),
.Q(Q[4]),
.R(rst));
FDRE \bus2ip_addr_i_reg[7]
(.C(s_axi_aclk),
.CE(\bus2ip_addr_i[8]_i_1_n_0 ),
.D(\bus2ip_addr_i[7]_i_1_n_0 ),
.Q(Bus2IIC_Addr[1]),
.R(rst));
FDRE \bus2ip_addr_i_reg[8]
(.C(s_axi_aclk),
.CE(\bus2ip_addr_i[8]_i_1_n_0 ),
.D(\bus2ip_addr_i[8]_i_2_n_0 ),
.Q(Bus2IIC_Addr[0]),
.R(rst));
(* SOFT_HLUTNM = "soft_lutpair48" *)
LUT3 #(
.INIT(8'h02))
bus2ip_rnw_i_i_1
(.I0(s_axi_arvalid),
.I1(state[0]),
.I2(state[1]),
.O(bus2ip_rnw_i06_out));
FDRE bus2ip_rnw_i_reg
(.C(s_axi_aclk),
.CE(\bus2ip_addr_i[8]_i_1_n_0 ),
.D(bus2ip_rnw_i06_out),
.Q(bus2ip_rnw_i_reg_n_0),
.R(rst));
LUT4 #(
.INIT(16'h2F20))
is_read_i_1
(.I0(s_axi_arvalid),
.I1(state[1]),
.I2(is_write),
.I3(is_read),
.O(is_read_i_1_n_0));
LUT6 #(
.INIT(64'hAA80808055555555))
is_read_i_2
(.I0(state[0]),
.I1(s_axi_rvalid),
.I2(s_axi_rready),
.I3(s_axi_bvalid),
.I4(s_axi_bready),
.I5(state[1]),
.O(is_write));
FDRE is_read_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(is_read_i_1_n_0),
.Q(is_read),
.R(rst));
LUT6 #(
.INIT(64'h0008FFFF00080000))
is_write_i_1
(.I0(s_axi_wvalid),
.I1(s_axi_awvalid),
.I2(s_axi_arvalid),
.I3(state[1]),
.I4(is_write),
.I5(is_write_reg_n_0),
.O(is_write_i_1_n_0));
FDRE is_write_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(is_write_i_1_n_0),
.Q(is_write_reg_n_0),
.R(rst));
FDRE rst_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(AXI_Bus2IP_Reset),
.Q(rst),
.R(1'b0));
LUT4 #(
.INIT(16'h4F44))
s_axi_arready_INST_0
(.I0(I_DECODER_n_3),
.I1(is_read),
.I2(AXI_IP2Bus_RdAck1),
.I3(AXI_IP2Bus_RdAck2),
.O(s_axi_arready));
FDRE #(
.INIT(1'b0))
\s_axi_bresp_i_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(I_DECODER_n_47),
.Q(s_axi_bresp),
.R(rst));
LUT5 #(
.INIT(32'h5D550C00))
s_axi_bvalid_i_i_1
(.I0(s_axi_bready),
.I1(state[1]),
.I2(state[0]),
.I3(s_axi_wready),
.I4(s_axi_bvalid),
.O(s_axi_bvalid_i_i_1_n_0));
FDRE #(
.INIT(1'b0))
s_axi_bvalid_i_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_axi_bvalid_i_i_1_n_0),
.Q(s_axi_bvalid),
.R(rst));
LUT6 #(
.INIT(64'hABFBFFFFABFB0000))
\s_axi_rdata_i[0]_i_3
(.I0(Q[4]),
.I1(Tx_addr[0]),
.I2(Q[3]),
.I3(\timing_param_tsudat_i_reg[5] [0]),
.I4(Q[2]),
.I5(\GPO_GEN.gpo_i_reg[31]_0 ),
.O(\s_axi_rdata_i[0]_i_3_n_0 ));
LUT6 #(
.INIT(64'h8888088888888888))
\s_axi_rdata_i[0]_i_4
(.I0(\s_axi_rdata_i[0]_i_7_n_0 ),
.I1(I_DECODER_n_1),
.I2(\timing_param_thdsta_i_reg[0] ),
.I3(Q[2]),
.I4(Q[4]),
.I5(Q[3]),
.O(\s_axi_rdata_i[0]_i_4_n_0 ));
LUT6 #(
.INIT(64'h4F444F4F44444444))
\s_axi_rdata_i[0]_i_5
(.I0(\timing_param_tbuf_i_reg[0] ),
.I1(I_DECODER_n_0),
.I2(\s_axi_rdata_i[1]_i_8_n_0 ),
.I3(\s_axi_rdata_i[3]_i_8_n_0 ),
.I4(\timing_param_thigh_i_reg[7] [0]),
.I5(\s_axi_rdata_i[0]_i_9_n_0 ),
.O(\s_axi_rdata_i[0]_i_5_n_0 ));
LUT6 #(
.INIT(64'hFAFAABFBFFFFABFB))
\s_axi_rdata_i[0]_i_7
(.I0(Q[2]),
.I1(\cr_i_reg[4]_0 [0]),
.I2(Q[4]),
.I3(\timing_param_tlow_i_reg[0] ),
.I4(Q[3]),
.I5(\RD_FIFO_CNTRL.rc_fifo_pirq_i_reg[7] ),
.O(\s_axi_rdata_i[0]_i_7_n_0 ));
LUT5 #(
.INIT(32'hEEEFFFEF))
\s_axi_rdata_i[0]_i_9
(.I0(Q[2]),
.I1(Q[4]),
.I2(Rc_fifo_data[7]),
.I3(Q[3]),
.I4(\timing_param_tsusto_i_reg[7] [0]),
.O(\s_axi_rdata_i[0]_i_9_n_0 ));
LUT6 #(
.INIT(64'h00E2FFFF00E20000))
\s_axi_rdata_i[1]_i_3
(.I0(Tx_addr[1]),
.I1(Q[3]),
.I2(\timing_param_tsudat_i_reg[5] [1]),
.I3(Q[4]),
.I4(Q[2]),
.I5(\IIC2Bus_IntrEvent_reg[5] ),
.O(\s_axi_rdata_i[1]_i_3_n_0 ));
LUT6 #(
.INIT(64'hD0DDD0D0DDDDDDDD))
\s_axi_rdata_i[1]_i_4
(.I0(I_DECODER_n_0),
.I1(\timing_param_tbuf_i_reg[1] ),
.I2(\s_axi_rdata_i[1]_i_8_n_0 ),
.I3(\s_axi_rdata_i[3]_i_8_n_0 ),
.I4(\timing_param_thigh_i_reg[7] [1]),
.I5(\s_axi_rdata_i[1]_i_9_n_0 ),
.O(\s_axi_rdata_i[1]_i_4_n_0 ));
LUT3 #(
.INIT(8'h1F))
\s_axi_rdata_i[1]_i_8
(.I0(Q[0]),
.I1(Q[4]),
.I2(Q[1]),
.O(\s_axi_rdata_i[1]_i_8_n_0 ));
LUT5 #(
.INIT(32'hEEEFFFEF))
\s_axi_rdata_i[1]_i_9
(.I0(Q[2]),
.I1(Q[4]),
.I2(Rc_fifo_data[6]),
.I3(Q[3]),
.I4(\timing_param_tsusto_i_reg[7] [1]),
.O(\s_axi_rdata_i[1]_i_9_n_0 ));
LUT6 #(
.INIT(64'h00E2FFFF00E20000))
\s_axi_rdata_i[2]_i_4
(.I0(Tx_addr[2]),
.I1(Q[3]),
.I2(\timing_param_tsudat_i_reg[5] [2]),
.I3(Q[4]),
.I4(Q[2]),
.I5(\sr_i_reg[5] ),
.O(\s_axi_rdata_i[2]_i_4_n_0 ));
LUT6 #(
.INIT(64'h4545454545FF4545))
\s_axi_rdata_i[2]_i_5
(.I0(\s_axi_rdata_i[2]_i_8_n_0 ),
.I1(\s_axi_rdata_i[3]_i_8_n_0 ),
.I2(\timing_param_thigh_i_reg[7] [2]),
.I3(\timing_param_tbuf_i_reg[2] ),
.I4(Q[1]),
.I5(Q[0]),
.O(\s_axi_rdata_i[2]_i_5_n_0 ));
LUT6 #(
.INIT(64'hAAAAAAAAAAAAEFEA))
\s_axi_rdata_i[2]_i_8
(.I0(\s_axi_rdata_i[1]_i_8_n_0 ),
.I1(\timing_param_tsusto_i_reg[7] [2]),
.I2(Q[3]),
.I3(Rc_fifo_data[5]),
.I4(Q[4]),
.I5(Q[2]),
.O(\s_axi_rdata_i[2]_i_8_n_0 ));
LUT2 #(
.INIT(4'h2))
\s_axi_rdata_i[31]_i_1
(.I0(state[0]),
.I1(state[1]),
.O(s_axi_rdata_i));
LUT6 #(
.INIT(64'h04FF040404FF04FF))
\s_axi_rdata_i[3]_i_3
(.I0(\s_axi_rdata_i[3]_i_6_n_0 ),
.I1(Q[0]),
.I2(Q[1]),
.I3(\s_axi_rdata_i[3]_i_7_n_0 ),
.I4(\s_axi_rdata_i[3]_i_8_n_0 ),
.I5(\timing_param_thigh_i_reg[7] [3]),
.O(\s_axi_rdata_i[3]_i_3_n_0 ));
LUT6 #(
.INIT(64'h00E2FFFF00E20000))
\s_axi_rdata_i[3]_i_6
(.I0(Tx_addr[3]),
.I1(Q[3]),
.I2(\timing_param_tsudat_i_reg[5] [3]),
.I3(Q[4]),
.I4(Q[2]),
.I5(\sr_i_reg[4] ),
.O(\s_axi_rdata_i[3]_i_6_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF000000B8))
\s_axi_rdata_i[3]_i_7
(.I0(\timing_param_tsusto_i_reg[7] [3]),
.I1(Q[3]),
.I2(Rc_fifo_data[4]),
.I3(Q[4]),
.I4(Q[2]),
.I5(\s_axi_rdata_i[1]_i_8_n_0 ),
.O(\s_axi_rdata_i[3]_i_7_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair47" *)
LUT3 #(
.INIT(8'hDF))
\s_axi_rdata_i[3]_i_8
(.I0(Q[3]),
.I1(Q[4]),
.I2(Q[2]),
.O(\s_axi_rdata_i[3]_i_8_n_0 ));
LUT6 #(
.INIT(64'h88800080AAAAAAAA))
\s_axi_rdata_i[4]_i_3
(.I0(\s_axi_rdata_i[4]_i_6_n_0 ),
.I1(I_DECODER_n_5),
.I2(Tx_fifo_data[0]),
.I3(Q[3]),
.I4(\timing_param_tsusta_i_reg[7] [0]),
.I5(\s_axi_rdata_i[4]_i_7_n_0 ),
.O(\s_axi_rdata_i[4]_i_3_n_0 ));
LUT6 #(
.INIT(64'h00000000FFFFABFB))
\s_axi_rdata_i[4]_i_5
(.I0(Q[3]),
.I1(\sr_i_reg[2] [0]),
.I2(Q[4]),
.I3(\timing_param_thddat_i_reg[5] [0]),
.I4(Q[2]),
.I5(\s_axi_rdata_i[4]_i_9_n_0 ),
.O(\s_axi_rdata_i[4]_i_5_n_0 ));
LUT6 #(
.INIT(64'hFFDD55F555DD55F5))
\s_axi_rdata_i[4]_i_6
(.I0(Q[0]),
.I1(\timing_param_tsusto_i_reg[7] [4]),
.I2(Rc_fifo_data[3]),
.I3(Q[2]),
.I4(Q[3]),
.I5(\timing_param_thigh_i_reg[7] [4]),
.O(\s_axi_rdata_i[4]_i_6_n_0 ));
LUT5 #(
.INIT(32'hAAAABFFF))
\s_axi_rdata_i[4]_i_7
(.I0(Q[4]),
.I1(\timing_param_tbuf_i_reg[7] [0]),
.I2(Q[2]),
.I3(Q[3]),
.I4(Q[0]),
.O(\s_axi_rdata_i[4]_i_7_n_0 ));
LUT6 #(
.INIT(64'hFFFF2000FFFFFFFF))
\s_axi_rdata_i[4]_i_9
(.I0(Q[3]),
.I1(Q[4]),
.I2(Q[2]),
.I3(\timing_param_tsudat_i_reg[5] [4]),
.I4(Q[1]),
.I5(Q[0]),
.O(\s_axi_rdata_i[4]_i_9_n_0 ));
LUT6 #(
.INIT(64'h88800080AAAAAAAA))
\s_axi_rdata_i[5]_i_3
(.I0(\s_axi_rdata_i[5]_i_6_n_0 ),
.I1(I_DECODER_n_5),
.I2(Tx_fifo_data[1]),
.I3(Q[3]),
.I4(\timing_param_tsusta_i_reg[7] [1]),
.I5(\s_axi_rdata_i[5]_i_7_n_0 ),
.O(\s_axi_rdata_i[5]_i_3_n_0 ));
LUT6 #(
.INIT(64'h00000000FFFFABFB))
\s_axi_rdata_i[5]_i_5
(.I0(Q[3]),
.I1(\sr_i_reg[2] [1]),
.I2(Q[4]),
.I3(\timing_param_thddat_i_reg[5] [1]),
.I4(Q[2]),
.I5(\s_axi_rdata_i[5]_i_9_n_0 ),
.O(\s_axi_rdata_i[5]_i_5_n_0 ));
LUT6 #(
.INIT(64'hFFDD55F555DD55F5))
\s_axi_rdata_i[5]_i_6
(.I0(Q[0]),
.I1(\timing_param_tsusto_i_reg[7] [5]),
.I2(Rc_fifo_data[2]),
.I3(Q[2]),
.I4(Q[3]),
.I5(\timing_param_thigh_i_reg[7] [5]),
.O(\s_axi_rdata_i[5]_i_6_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair47" *)
LUT5 #(
.INIT(32'hAAAABFFF))
\s_axi_rdata_i[5]_i_7
(.I0(Q[4]),
.I1(\timing_param_tbuf_i_reg[7] [1]),
.I2(Q[2]),
.I3(Q[3]),
.I4(Q[0]),
.O(\s_axi_rdata_i[5]_i_7_n_0 ));
LUT6 #(
.INIT(64'hFFFF2000FFFFFFFF))
\s_axi_rdata_i[5]_i_9
(.I0(Q[3]),
.I1(Q[4]),
.I2(Q[2]),
.I3(\timing_param_tsudat_i_reg[5] [5]),
.I4(Q[1]),
.I5(Q[0]),
.O(\s_axi_rdata_i[5]_i_9_n_0 ));
LUT6 #(
.INIT(64'h88800080AAAAAAAA))
\s_axi_rdata_i[6]_i_3
(.I0(\s_axi_rdata_i[6]_i_6_n_0 ),
.I1(I_DECODER_n_5),
.I2(Tx_fifo_data[2]),
.I3(Q[3]),
.I4(\timing_param_tsusta_i_reg[7] [2]),
.I5(\s_axi_rdata_i[6]_i_7_n_0 ),
.O(\s_axi_rdata_i[6]_i_3_n_0 ));
LUT6 #(
.INIT(64'hFFDD55F555DD55F5))
\s_axi_rdata_i[6]_i_6
(.I0(Q[0]),
.I1(\timing_param_tsusto_i_reg[7] [6]),
.I2(Rc_fifo_data[1]),
.I3(Q[2]),
.I4(Q[3]),
.I5(\timing_param_thigh_i_reg[7] [6]),
.O(\s_axi_rdata_i[6]_i_6_n_0 ));
LUT5 #(
.INIT(32'hAAAABFFF))
\s_axi_rdata_i[6]_i_7
(.I0(Q[4]),
.I1(\timing_param_tbuf_i_reg[7] [2]),
.I2(Q[2]),
.I3(Q[3]),
.I4(Q[0]),
.O(\s_axi_rdata_i[6]_i_7_n_0 ));
LUT6 #(
.INIT(64'h88800080AAAAAAAA))
\s_axi_rdata_i[7]_i_3
(.I0(\s_axi_rdata_i[7]_i_6_n_0 ),
.I1(I_DECODER_n_5),
.I2(Tx_fifo_data[3]),
.I3(Q[3]),
.I4(\timing_param_tsusta_i_reg[7] [3]),
.I5(\s_axi_rdata_i[7]_i_7_n_0 ),
.O(\s_axi_rdata_i[7]_i_3_n_0 ));
LUT6 #(
.INIT(64'hFFDD55F555DD55F5))
\s_axi_rdata_i[7]_i_6
(.I0(Q[0]),
.I1(\timing_param_tsusto_i_reg[7] [7]),
.I2(Rc_fifo_data[0]),
.I3(Q[2]),
.I4(Q[3]),
.I5(\timing_param_thigh_i_reg[7] [7]),
.O(\s_axi_rdata_i[7]_i_6_n_0 ));
LUT5 #(
.INIT(32'hAAAABFFF))
\s_axi_rdata_i[7]_i_7
(.I0(Q[4]),
.I1(\timing_param_tbuf_i_reg[7] [3]),
.I2(Q[2]),
.I3(Q[3]),
.I4(Q[0]),
.O(\s_axi_rdata_i[7]_i_7_n_0 ));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[0]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(AXI_IP2Bus_Data[31]),
.Q(s_axi_rdata[0]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[1]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(AXI_IP2Bus_Data[30]),
.Q(s_axi_rdata[1]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[2]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(AXI_IP2Bus_Data[29]),
.Q(s_axi_rdata[2]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[31]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(Intr2Bus_DBus),
.Q(s_axi_rdata[10]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[3]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(AXI_IP2Bus_Data[28]),
.Q(s_axi_rdata[3]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[4]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(AXI_IP2Bus_Data[27]),
.Q(s_axi_rdata[4]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[5]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(AXI_IP2Bus_Data[26]),
.Q(s_axi_rdata[5]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[6]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(AXI_IP2Bus_Data[25]),
.Q(s_axi_rdata[6]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[7]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(AXI_IP2Bus_Data[24]),
.Q(s_axi_rdata[7]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[8]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(IIC2Bus_Data[23]),
.Q(s_axi_rdata[8]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[9]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(IIC2Bus_Data[22]),
.Q(s_axi_rdata[9]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rresp_i_reg[1]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(AXI_IP2Bus_Error),
.Q(s_axi_rresp),
.R(rst));
LUT3 #(
.INIT(8'hDC))
s_axi_rvalid_i_i_1
(.I0(s_axi_rready),
.I1(s_axi_rvalid_i0),
.I2(s_axi_rvalid),
.O(s_axi_rvalid_i_i_1_n_0));
LUT6 #(
.INIT(64'h000022F200000000))
s_axi_rvalid_i_i_2
(.I0(AXI_IP2Bus_RdAck2),
.I1(AXI_IP2Bus_RdAck1),
.I2(is_read),
.I3(I_DECODER_n_3),
.I4(state[1]),
.I5(state[0]),
.O(s_axi_rvalid_i0));
FDRE #(
.INIT(1'b0))
s_axi_rvalid_i_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_axi_rvalid_i_i_1_n_0),
.Q(s_axi_rvalid),
.R(rst));
(* SOFT_HLUTNM = "soft_lutpair50" *)
LUT5 #(
.INIT(32'h000F0008))
start2_i_1
(.I0(s_axi_wvalid),
.I1(s_axi_awvalid),
.I2(state[1]),
.I3(state[0]),
.I4(s_axi_arvalid),
.O(start2_i_1_n_0));
FDRE start2_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(start2_i_1_n_0),
.Q(start2),
.R(rst));
LUT5 #(
.INIT(32'h2F2CEFEC))
\state[0]_i_1
(.I0(s_axi_wready),
.I1(state[0]),
.I2(state[1]),
.I3(s_axi_arvalid),
.I4(\state[0]_i_2_n_0 ),
.O(\state[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair49" *)
LUT4 #(
.INIT(16'hF888))
\state[0]_i_2
(.I0(s_axi_rvalid),
.I1(s_axi_rready),
.I2(s_axi_bvalid),
.I3(s_axi_bready),
.O(\state[0]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFFFFAFAE))
\state[1]_i_1
(.I0(s_axi_rvalid_i0),
.I1(state[1]),
.I2(state[0]),
.I3(\state[1]_i_2_n_0 ),
.I4(\state[1]_i_3_n_0 ),
.O(\state[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair50" *)
LUT3 #(
.INIT(8'h40))
\state[1]_i_2
(.I0(s_axi_arvalid),
.I1(s_axi_awvalid),
.I2(s_axi_wvalid),
.O(\state[1]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair49" *)
LUT5 #(
.INIT(32'h002A2A2A))
\state[1]_i_3
(.I0(state[1]),
.I1(s_axi_bready),
.I2(s_axi_bvalid),
.I3(s_axi_rready),
.I4(s_axi_rvalid),
.O(\state[1]_i_3_n_0 ));
FDRE \state_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\state[0]_i_1_n_0 ),
.Q(state[0]),
.R(rst));
FDRE \state_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\state[1]_i_1_n_0 ),
.Q(state[1]),
.R(rst));
endmodule
(* ORIG_REF_NAME = "soft_reset" *)
module system_axi_iic_0_0_soft_reset
(sw_rst_cond_d1,
AXI_Bus2IP_Reset,
ctrlFifoDin,
SR,
sw_rst_cond,
s_axi_aclk,
reset_trig0,
s_axi_wdata,
Tx_fifo_rst,
s_axi_aresetn);
output sw_rst_cond_d1;
output AXI_Bus2IP_Reset;
output [0:1]ctrlFifoDin;
output [0:0]SR;
input sw_rst_cond;
input s_axi_aclk;
input reset_trig0;
input [1:0]s_axi_wdata;
input Tx_fifo_rst;
input s_axi_aresetn;
wire AXI_Bus2IP_Reset;
wire \RESET_FLOPS[1].RST_FLOPS_i_1_n_0 ;
wire \RESET_FLOPS[2].RST_FLOPS_i_1_n_0 ;
wire \RESET_FLOPS[3].RST_FLOPS_i_1_n_0 ;
wire \RESET_FLOPS[3].RST_FLOPS_n_0 ;
wire S;
wire [0:0]SR;
wire Tx_fifo_rst;
wire [0:1]ctrlFifoDin;
wire [1:3]flop_q_chain;
wire reset_trig0;
wire s_axi_aclk;
wire s_axi_aresetn;
wire [1:0]s_axi_wdata;
wire sw_rst_cond;
wire sw_rst_cond_d1;
(* SOFT_HLUTNM = "soft_lutpair53" *)
LUT3 #(
.INIT(8'h02))
\FIFO_RAM[0].SRL16E_I_i_1
(.I0(s_axi_wdata[1]),
.I1(SR),
.I2(Tx_fifo_rst),
.O(ctrlFifoDin[0]));
(* SOFT_HLUTNM = "soft_lutpair53" *)
LUT3 #(
.INIT(8'h02))
\FIFO_RAM[1].SRL16E_I_i_1
(.I0(s_axi_wdata[0]),
.I1(SR),
.I2(Tx_fifo_rst),
.O(ctrlFifoDin[1]));
LUT2 #(
.INIT(4'hB))
\GPO_GEN.gpo_i[31]_i_1
(.I0(\RESET_FLOPS[3].RST_FLOPS_n_0 ),
.I1(s_axi_aresetn),
.O(SR));
(* IS_CE_INVERTED = "1'b0" *)
(* IS_S_INVERTED = "1'b0" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\RESET_FLOPS[0].RST_FLOPS
(.C(s_axi_aclk),
.CE(1'b1),
.D(S),
.Q(flop_q_chain[1]),
.R(AXI_Bus2IP_Reset));
(* IS_CE_INVERTED = "1'b0" *)
(* IS_S_INVERTED = "1'b0" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\RESET_FLOPS[1].RST_FLOPS
(.C(s_axi_aclk),
.CE(1'b1),
.D(\RESET_FLOPS[1].RST_FLOPS_i_1_n_0 ),
.Q(flop_q_chain[2]),
.R(AXI_Bus2IP_Reset));
(* SOFT_HLUTNM = "soft_lutpair54" *)
LUT2 #(
.INIT(4'hE))
\RESET_FLOPS[1].RST_FLOPS_i_1
(.I0(S),
.I1(flop_q_chain[1]),
.O(\RESET_FLOPS[1].RST_FLOPS_i_1_n_0 ));
(* IS_CE_INVERTED = "1'b0" *)
(* IS_S_INVERTED = "1'b0" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\RESET_FLOPS[2].RST_FLOPS
(.C(s_axi_aclk),
.CE(1'b1),
.D(\RESET_FLOPS[2].RST_FLOPS_i_1_n_0 ),
.Q(flop_q_chain[3]),
.R(AXI_Bus2IP_Reset));
(* SOFT_HLUTNM = "soft_lutpair54" *)
LUT2 #(
.INIT(4'hE))
\RESET_FLOPS[2].RST_FLOPS_i_1
(.I0(S),
.I1(flop_q_chain[2]),
.O(\RESET_FLOPS[2].RST_FLOPS_i_1_n_0 ));
(* IS_CE_INVERTED = "1'b0" *)
(* IS_S_INVERTED = "1'b0" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\RESET_FLOPS[3].RST_FLOPS
(.C(s_axi_aclk),
.CE(1'b1),
.D(\RESET_FLOPS[3].RST_FLOPS_i_1_n_0 ),
.Q(\RESET_FLOPS[3].RST_FLOPS_n_0 ),
.R(AXI_Bus2IP_Reset));
LUT2 #(
.INIT(4'hE))
\RESET_FLOPS[3].RST_FLOPS_i_1
(.I0(S),
.I1(flop_q_chain[3]),
.O(\RESET_FLOPS[3].RST_FLOPS_i_1_n_0 ));
FDRE reset_trig_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(reset_trig0),
.Q(S),
.R(AXI_Bus2IP_Reset));
LUT1 #(
.INIT(2'h1))
rst_i_1
(.I0(s_axi_aresetn),
.O(AXI_Bus2IP_Reset));
FDRE sw_rst_cond_d1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(sw_rst_cond),
.Q(sw_rst_cond_d1),
.R(AXI_Bus2IP_Reset));
endmodule
(* ORIG_REF_NAME = "upcnt_n" *)
module system_axi_iic_0_0_upcnt_n
(\q_int_reg[0]_0 ,
out,
CO,
detect_stop_b_reg,
stop_scl_reg_reg,
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 ,
\timing_param_thddat_i_reg[9] ,
SR,
s_axi_aclk);
output [9:0]\q_int_reg[0]_0 ;
input [3:0]out;
input [0:0]CO;
input detect_stop_b_reg;
input stop_scl_reg_reg;
input \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 ;
input [0:0]\timing_param_thddat_i_reg[9] ;
input [0:0]SR;
input s_axi_aclk;
wire [0:0]CO;
wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 ;
wire [0:0]SR;
wire detect_stop_b_reg;
wire [3:0]out;
wire [9:0]p_0_in__0;
wire \q_int[0]_i_10_n_0 ;
wire \q_int[0]_i_1_n_0 ;
wire \q_int[0]_i_3_n_0 ;
wire \q_int[0]_i_4_n_0 ;
wire \q_int[0]_i_5__0_n_0 ;
wire \q_int[0]_i_7_n_0 ;
wire \q_int[0]_i_8_n_0 ;
wire \q_int[0]_i_9_n_0 ;
wire \q_int[1]_i_1__0_n_0 ;
wire \q_int[1]_i_2_n_0 ;
wire \q_int[1]_i_3_n_0 ;
wire \q_int[1]_i_4_n_0 ;
wire \q_int[1]_i_5_n_0 ;
wire \q_int[2]_i_1__0_n_0 ;
wire \q_int[2]_i_2_n_0 ;
wire \q_int[3]_i_1__0_n_0 ;
wire \q_int[3]_i_2_n_0 ;
wire \q_int[4]_i_1_n_0 ;
wire \q_int[4]_i_2_n_0 ;
wire \q_int[5]_i_1__0_n_0 ;
wire \q_int[5]_i_2_n_0 ;
wire \q_int[6]_i_1__0_n_0 ;
wire \q_int[6]_i_2_n_0 ;
wire \q_int[7]_i_1__0_n_0 ;
wire \q_int[7]_i_2_n_0 ;
wire [9:0]\q_int_reg[0]_0 ;
wire s_axi_aclk;
wire stop_scl_reg_reg;
wire [0:0]\timing_param_thddat_i_reg[9] ;
LUT6 #(
.INIT(64'hEEEFEFEEEEFFEFFE))
\q_int[0]_i_1
(.I0(\q_int[0]_i_3_n_0 ),
.I1(\q_int[0]_i_4_n_0 ),
.I2(out[3]),
.I3(out[1]),
.I4(out[0]),
.I5(out[2]),
.O(\q_int[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT3 #(
.INIT(8'h0B))
\q_int[0]_i_10
(.I0(CO),
.I1(detect_stop_b_reg),
.I2(out[0]),
.O(\q_int[0]_i_10_n_0 ));
LUT6 #(
.INIT(64'h2222202222222002))
\q_int[0]_i_2
(.I0(\q_int[0]_i_5__0_n_0 ),
.I1(\q_int[0]_i_4_n_0 ),
.I2(out[3]),
.I3(out[1]),
.I4(out[0]),
.I5(out[2]),
.O(p_0_in__0[9]));
LUT6 #(
.INIT(64'hFFFFFFFFFFFF040C))
\q_int[0]_i_3
(.I0(stop_scl_reg_reg),
.I1(out[0]),
.I2(out[3]),
.I3(out[2]),
.I4(\q_int[0]_i_7_n_0 ),
.I5(\q_int[0]_i_8_n_0 ),
.O(\q_int[0]_i_3_n_0 ));
LUT6 #(
.INIT(64'hAFAEAAAEAAAEAAAE))
\q_int[0]_i_4
(.I0(\q_int[0]_i_9_n_0 ),
.I1(\q_int[0]_i_10_n_0 ),
.I2(out[3]),
.I3(out[2]),
.I4(out[1]),
.I5(stop_scl_reg_reg),
.O(\q_int[0]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT5 #(
.INIT(32'hAAAA6AAA))
\q_int[0]_i_5__0
(.I0(\q_int_reg[0]_0 [9]),
.I1(\q_int_reg[0]_0 [8]),
.I2(\q_int_reg[0]_0 [7]),
.I3(\q_int_reg[0]_0 [6]),
.I4(\q_int[3]_i_2_n_0 ),
.O(\q_int[0]_i_5__0_n_0 ));
LUT5 #(
.INIT(32'h00010000))
\q_int[0]_i_7
(.I0(out[1]),
.I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 ),
.I2(\timing_param_thddat_i_reg[9] ),
.I3(out[3]),
.I4(out[2]),
.O(\q_int[0]_i_7_n_0 ));
LUT5 #(
.INIT(32'h00000004))
\q_int[0]_i_8
(.I0(out[1]),
.I1(detect_stop_b_reg),
.I2(CO),
.I3(out[3]),
.I4(out[2]),
.O(\q_int[0]_i_8_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT5 #(
.INIT(32'h00540000))
\q_int[0]_i_9
(.I0(out[0]),
.I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 ),
.I2(\timing_param_thddat_i_reg[9] ),
.I3(out[3]),
.I4(out[2]),
.O(\q_int[0]_i_9_n_0 ));
LUT6 #(
.INIT(64'h0000011101110000))
\q_int[1]_i_1__0
(.I0(\q_int[0]_i_4_n_0 ),
.I1(\q_int[1]_i_2_n_0 ),
.I2(\q_int[1]_i_3_n_0 ),
.I3(\q_int[1]_i_4_n_0 ),
.I4(\q_int[1]_i_5_n_0 ),
.I5(\q_int_reg[0]_0 [8]),
.O(\q_int[1]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT3 #(
.INIT(8'h04))
\q_int[1]_i_2
(.I0(out[0]),
.I1(out[1]),
.I2(out[3]),
.O(\q_int[1]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT2 #(
.INIT(4'h2))
\q_int[1]_i_3
(.I0(out[3]),
.I1(out[2]),
.O(\q_int[1]_i_3_n_0 ));
LUT2 #(
.INIT(4'h1))
\q_int[1]_i_4
(.I0(out[0]),
.I1(out[1]),
.O(\q_int[1]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT3 #(
.INIT(8'h08))
\q_int[1]_i_5
(.I0(\q_int_reg[0]_0 [7]),
.I1(\q_int_reg[0]_0 [6]),
.I2(\q_int[3]_i_2_n_0 ),
.O(\q_int[1]_i_5_n_0 ));
LUT6 #(
.INIT(64'h0111000000000111))
\q_int[2]_i_1__0
(.I0(\q_int[0]_i_4_n_0 ),
.I1(\q_int[1]_i_2_n_0 ),
.I2(\q_int[1]_i_3_n_0 ),
.I3(\q_int[1]_i_4_n_0 ),
.I4(\q_int[2]_i_2_n_0 ),
.I5(\q_int_reg[0]_0 [7]),
.O(\q_int[2]_i_1__0_n_0 ));
LUT2 #(
.INIT(4'hB))
\q_int[2]_i_2
(.I0(\q_int[3]_i_2_n_0 ),
.I1(\q_int_reg[0]_0 [6]),
.O(\q_int[2]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0111000000000111))
\q_int[3]_i_1__0
(.I0(\q_int[0]_i_4_n_0 ),
.I1(\q_int[1]_i_2_n_0 ),
.I2(\q_int[1]_i_3_n_0 ),
.I3(\q_int[1]_i_4_n_0 ),
.I4(\q_int[3]_i_2_n_0 ),
.I5(\q_int_reg[0]_0 [6]),
.O(\q_int[3]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'h7FFFFFFFFFFFFFFF))
\q_int[3]_i_2
(.I0(\q_int_reg[0]_0 [4]),
.I1(\q_int_reg[0]_0 [2]),
.I2(\q_int_reg[0]_0 [0]),
.I3(\q_int_reg[0]_0 [1]),
.I4(\q_int_reg[0]_0 [3]),
.I5(\q_int_reg[0]_0 [5]),
.O(\q_int[3]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0000000055455541))
\q_int[4]_i_1
(.I0(\q_int[0]_i_4_n_0 ),
.I1(out[3]),
.I2(out[1]),
.I3(out[0]),
.I4(out[2]),
.I5(\q_int[4]_i_2_n_0 ),
.O(\q_int[4]_i_1_n_0 ));
LUT6 #(
.INIT(64'h9555555555555555))
\q_int[4]_i_2
(.I0(\q_int_reg[0]_0 [5]),
.I1(\q_int_reg[0]_0 [4]),
.I2(\q_int_reg[0]_0 [2]),
.I3(\q_int_reg[0]_0 [0]),
.I4(\q_int_reg[0]_0 [1]),
.I5(\q_int_reg[0]_0 [3]),
.O(\q_int[4]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0000000055455541))
\q_int[5]_i_1__0
(.I0(\q_int[0]_i_4_n_0 ),
.I1(out[3]),
.I2(out[1]),
.I3(out[0]),
.I4(out[2]),
.I5(\q_int[5]_i_2_n_0 ),
.O(\q_int[5]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT5 #(
.INIT(32'h95555555))
\q_int[5]_i_2
(.I0(\q_int_reg[0]_0 [4]),
.I1(\q_int_reg[0]_0 [3]),
.I2(\q_int_reg[0]_0 [1]),
.I3(\q_int_reg[0]_0 [0]),
.I4(\q_int_reg[0]_0 [2]),
.O(\q_int[5]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0000000055455541))
\q_int[6]_i_1__0
(.I0(\q_int[0]_i_4_n_0 ),
.I1(out[3]),
.I2(out[1]),
.I3(out[0]),
.I4(out[2]),
.I5(\q_int[6]_i_2_n_0 ),
.O(\q_int[6]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT4 #(
.INIT(16'h9555))
\q_int[6]_i_2
(.I0(\q_int_reg[0]_0 [3]),
.I1(\q_int_reg[0]_0 [2]),
.I2(\q_int_reg[0]_0 [0]),
.I3(\q_int_reg[0]_0 [1]),
.O(\q_int[6]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0000000055455541))
\q_int[7]_i_1__0
(.I0(\q_int[0]_i_4_n_0 ),
.I1(out[3]),
.I2(out[1]),
.I3(out[0]),
.I4(out[2]),
.I5(\q_int[7]_i_2_n_0 ),
.O(\q_int[7]_i_1__0_n_0 ));
LUT3 #(
.INIT(8'h95))
\q_int[7]_i_2
(.I0(\q_int_reg[0]_0 [2]),
.I1(\q_int_reg[0]_0 [1]),
.I2(\q_int_reg[0]_0 [0]),
.O(\q_int[7]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0000000600060006))
\q_int[8]_i_1
(.I0(\q_int_reg[0]_0 [1]),
.I1(\q_int_reg[0]_0 [0]),
.I2(\q_int[0]_i_4_n_0 ),
.I3(\q_int[1]_i_2_n_0 ),
.I4(\q_int[1]_i_3_n_0 ),
.I5(\q_int[1]_i_4_n_0 ),
.O(p_0_in__0[1]));
LUT6 #(
.INIT(64'h0000000055455541))
\q_int[9]_i_1
(.I0(\q_int[0]_i_4_n_0 ),
.I1(out[3]),
.I2(out[1]),
.I3(out[0]),
.I4(out[2]),
.I5(\q_int_reg[0]_0 [0]),
.O(p_0_in__0[0]));
FDRE \q_int_reg[0]
(.C(s_axi_aclk),
.CE(\q_int[0]_i_1_n_0 ),
.D(p_0_in__0[9]),
.Q(\q_int_reg[0]_0 [9]),
.R(SR));
FDRE \q_int_reg[1]
(.C(s_axi_aclk),
.CE(\q_int[0]_i_1_n_0 ),
.D(\q_int[1]_i_1__0_n_0 ),
.Q(\q_int_reg[0]_0 [8]),
.R(SR));
FDRE \q_int_reg[2]
(.C(s_axi_aclk),
.CE(\q_int[0]_i_1_n_0 ),
.D(\q_int[2]_i_1__0_n_0 ),
.Q(\q_int_reg[0]_0 [7]),
.R(SR));
FDRE \q_int_reg[3]
(.C(s_axi_aclk),
.CE(\q_int[0]_i_1_n_0 ),
.D(\q_int[3]_i_1__0_n_0 ),
.Q(\q_int_reg[0]_0 [6]),
.R(SR));
FDRE \q_int_reg[4]
(.C(s_axi_aclk),
.CE(\q_int[0]_i_1_n_0 ),
.D(\q_int[4]_i_1_n_0 ),
.Q(\q_int_reg[0]_0 [5]),
.R(SR));
FDRE \q_int_reg[5]
(.C(s_axi_aclk),
.CE(\q_int[0]_i_1_n_0 ),
.D(\q_int[5]_i_1__0_n_0 ),
.Q(\q_int_reg[0]_0 [4]),
.R(SR));
FDRE \q_int_reg[6]
(.C(s_axi_aclk),
.CE(\q_int[0]_i_1_n_0 ),
.D(\q_int[6]_i_1__0_n_0 ),
.Q(\q_int_reg[0]_0 [3]),
.R(SR));
FDRE \q_int_reg[7]
(.C(s_axi_aclk),
.CE(\q_int[0]_i_1_n_0 ),
.D(\q_int[7]_i_1__0_n_0 ),
.Q(\q_int_reg[0]_0 [2]),
.R(SR));
FDRE \q_int_reg[8]
(.C(s_axi_aclk),
.CE(\q_int[0]_i_1_n_0 ),
.D(p_0_in__0[1]),
.Q(\q_int_reg[0]_0 [1]),
.R(SR));
FDRE \q_int_reg[9]
(.C(s_axi_aclk),
.CE(\q_int[0]_i_1_n_0 ),
.D(p_0_in__0[0]),
.Q(\q_int_reg[0]_0 [0]),
.R(SR));
endmodule
(* ORIG_REF_NAME = "upcnt_n" *)
module system_axi_iic_0_0_upcnt_n_2
(\q_int_reg[1]_0 ,
\q_int_reg[0]_0 ,
S,
sda_setup,
sda_rin_d1_reg,
scndry_out,
rsta_d1,
Q,
tx_under_prev_d1,
tx_under_prev_i_reg,
gen_stop,
gen_stop_d1,
\timing_param_tsudat_i_reg[8] ,
SR,
s_axi_aclk);
output \q_int_reg[1]_0 ;
output [6:0]\q_int_reg[0]_0 ;
output [0:0]S;
input sda_setup;
input sda_rin_d1_reg;
input scndry_out;
input rsta_d1;
input [0:0]Q;
input tx_under_prev_d1;
input tx_under_prev_i_reg;
input gen_stop;
input gen_stop_d1;
input [2:0]\timing_param_tsudat_i_reg[8] ;
input [0:0]SR;
input s_axi_aclk;
wire [0:0]Q;
wire [0:0]S;
wire [0:0]SR;
wire gen_stop;
wire gen_stop_d1;
wire [9:0]p_0_in__1;
wire \q_int[0]_i_1__0_n_0 ;
wire \q_int[0]_i_4__0_n_0 ;
wire \q_int[0]_i_5_n_0 ;
wire \q_int[1]_i_1__1_n_0 ;
wire \q_int[2]_i_1__1_n_0 ;
wire \q_int[3]_i_1__1_n_0 ;
wire \q_int[4]_i_1__0_n_0 ;
wire \q_int[4]_i_2__0_n_0 ;
wire [6:0]\q_int_reg[0]_0 ;
wire \q_int_reg[1]_0 ;
wire [1:3]q_int_reg__0;
wire rsta_d1;
wire s_axi_aclk;
wire scndry_out;
wire sda_rin_d1_reg;
wire sda_setup;
wire [2:0]\timing_param_tsudat_i_reg[8] ;
wire tx_under_prev_d1;
wire tx_under_prev_i_reg;
LUT6 #(
.INIT(64'h9009000000009009))
i__carry_i_2__4
(.I0(q_int_reg__0[1]),
.I1(\timing_param_tsudat_i_reg[8] [2]),
.I2(q_int_reg__0[3]),
.I3(\timing_param_tsudat_i_reg[8] [0]),
.I4(\timing_param_tsudat_i_reg[8] [1]),
.I5(q_int_reg__0[2]),
.O(S));
LUT2 #(
.INIT(4'hE))
\q_int[0]_i_1__0
(.I0(sda_setup),
.I1(\q_int_reg[1]_0 ),
.O(\q_int[0]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'h00000000BFFF4000))
\q_int[0]_i_2__0
(.I0(\q_int[0]_i_4__0_n_0 ),
.I1(q_int_reg__0[3]),
.I2(q_int_reg__0[2]),
.I3(q_int_reg__0[1]),
.I4(\q_int_reg[0]_0 [6]),
.I5(\q_int_reg[1]_0 ),
.O(p_0_in__1[9]));
LUT3 #(
.INIT(8'hF6))
\q_int[0]_i_3__0
(.I0(sda_rin_d1_reg),
.I1(scndry_out),
.I2(\q_int[0]_i_5_n_0 ),
.O(\q_int_reg[1]_0 ));
LUT6 #(
.INIT(64'h7FFFFFFFFFFFFFFF))
\q_int[0]_i_4__0
(.I0(\q_int_reg[0]_0 [4]),
.I1(\q_int_reg[0]_0 [2]),
.I2(\q_int_reg[0]_0 [0]),
.I3(\q_int_reg[0]_0 [1]),
.I4(\q_int_reg[0]_0 [3]),
.I5(\q_int_reg[0]_0 [5]),
.O(\q_int[0]_i_4__0_n_0 ));
LUT6 #(
.INIT(64'h44F444F4FFFF44F4))
\q_int[0]_i_5
(.I0(rsta_d1),
.I1(Q),
.I2(tx_under_prev_d1),
.I3(tx_under_prev_i_reg),
.I4(gen_stop),
.I5(gen_stop_d1),
.O(\q_int[0]_i_5_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT5 #(
.INIT(32'h55150040))
\q_int[1]_i_1__1
(.I0(\q_int_reg[1]_0 ),
.I1(q_int_reg__0[2]),
.I2(q_int_reg__0[3]),
.I3(\q_int[0]_i_4__0_n_0 ),
.I4(q_int_reg__0[1]),
.O(\q_int[1]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT4 #(
.INIT(16'h4510))
\q_int[2]_i_1__1
(.I0(\q_int_reg[1]_0 ),
.I1(\q_int[0]_i_4__0_n_0 ),
.I2(q_int_reg__0[3]),
.I3(q_int_reg__0[2]),
.O(\q_int[2]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT3 #(
.INIT(8'h41))
\q_int[3]_i_1__1
(.I0(\q_int_reg[1]_0 ),
.I1(\q_int[0]_i_4__0_n_0 ),
.I2(q_int_reg__0[3]),
.O(\q_int[3]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT3 #(
.INIT(8'h41))
\q_int[4]_i_1__0
(.I0(\q_int_reg[1]_0 ),
.I1(\q_int[4]_i_2__0_n_0 ),
.I2(\q_int_reg[0]_0 [5]),
.O(\q_int[4]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'h7FFFFFFF))
\q_int[4]_i_2__0
(.I0(\q_int_reg[0]_0 [3]),
.I1(\q_int_reg[0]_0 [1]),
.I2(\q_int_reg[0]_0 [0]),
.I3(\q_int_reg[0]_0 [2]),
.I4(\q_int_reg[0]_0 [4]),
.O(\q_int[4]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'h000000007FFF8000))
\q_int[5]_i_1
(.I0(\q_int_reg[0]_0 [2]),
.I1(\q_int_reg[0]_0 [0]),
.I2(\q_int_reg[0]_0 [1]),
.I3(\q_int_reg[0]_0 [3]),
.I4(\q_int_reg[0]_0 [4]),
.I5(\q_int_reg[1]_0 ),
.O(p_0_in__1[4]));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT5 #(
.INIT(32'h00007F80))
\q_int[6]_i_1
(.I0(\q_int_reg[0]_0 [1]),
.I1(\q_int_reg[0]_0 [0]),
.I2(\q_int_reg[0]_0 [2]),
.I3(\q_int_reg[0]_0 [3]),
.I4(\q_int_reg[1]_0 ),
.O(p_0_in__1[3]));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT4 #(
.INIT(16'h0078))
\q_int[7]_i_1
(.I0(\q_int_reg[0]_0 [0]),
.I1(\q_int_reg[0]_0 [1]),
.I2(\q_int_reg[0]_0 [2]),
.I3(\q_int_reg[1]_0 ),
.O(p_0_in__1[2]));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT3 #(
.INIT(8'h06))
\q_int[8]_i_1__0
(.I0(\q_int_reg[0]_0 [1]),
.I1(\q_int_reg[0]_0 [0]),
.I2(\q_int_reg[1]_0 ),
.O(p_0_in__1[1]));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT2 #(
.INIT(4'h1))
\q_int[9]_i_1__0
(.I0(\q_int_reg[0]_0 [0]),
.I1(\q_int_reg[1]_0 ),
.O(p_0_in__1[0]));
FDRE \q_int_reg[0]
(.C(s_axi_aclk),
.CE(\q_int[0]_i_1__0_n_0 ),
.D(p_0_in__1[9]),
.Q(\q_int_reg[0]_0 [6]),
.R(SR));
FDRE \q_int_reg[1]
(.C(s_axi_aclk),
.CE(\q_int[0]_i_1__0_n_0 ),
.D(\q_int[1]_i_1__1_n_0 ),
.Q(q_int_reg__0[1]),
.R(SR));
FDRE \q_int_reg[2]
(.C(s_axi_aclk),
.CE(\q_int[0]_i_1__0_n_0 ),
.D(\q_int[2]_i_1__1_n_0 ),
.Q(q_int_reg__0[2]),
.R(SR));
FDRE \q_int_reg[3]
(.C(s_axi_aclk),
.CE(\q_int[0]_i_1__0_n_0 ),
.D(\q_int[3]_i_1__1_n_0 ),
.Q(q_int_reg__0[3]),
.R(SR));
FDRE \q_int_reg[4]
(.C(s_axi_aclk),
.CE(\q_int[0]_i_1__0_n_0 ),
.D(\q_int[4]_i_1__0_n_0 ),
.Q(\q_int_reg[0]_0 [5]),
.R(SR));
FDRE \q_int_reg[5]
(.C(s_axi_aclk),
.CE(\q_int[0]_i_1__0_n_0 ),
.D(p_0_in__1[4]),
.Q(\q_int_reg[0]_0 [4]),
.R(SR));
FDRE \q_int_reg[6]
(.C(s_axi_aclk),
.CE(\q_int[0]_i_1__0_n_0 ),
.D(p_0_in__1[3]),
.Q(\q_int_reg[0]_0 [3]),
.R(SR));
FDRE \q_int_reg[7]
(.C(s_axi_aclk),
.CE(\q_int[0]_i_1__0_n_0 ),
.D(p_0_in__1[2]),
.Q(\q_int_reg[0]_0 [2]),
.R(SR));
FDRE \q_int_reg[8]
(.C(s_axi_aclk),
.CE(\q_int[0]_i_1__0_n_0 ),
.D(p_0_in__1[1]),
.Q(\q_int_reg[0]_0 [1]),
.R(SR));
FDRE \q_int_reg[9]
(.C(s_axi_aclk),
.CE(\q_int[0]_i_1__0_n_0 ),
.D(p_0_in__1[0]),
.Q(\q_int_reg[0]_0 [0]),
.R(SR));
endmodule
(* ORIG_REF_NAME = "upcnt_n" *)
module system_axi_iic_0_0_upcnt_n__parameterized0
(E,
EarlyAckDataState0,
dtc_i_reg,
out,
\FSM_onehot_state_reg[4] ,
detect_start,
ro_prev_d1_reg,
bit_cnt_en,
scl_falling_edge,
dtc_i,
SR,
s_axi_aclk);
output [0:0]E;
output EarlyAckDataState0;
output dtc_i_reg;
input [5:0]out;
input \FSM_onehot_state_reg[4] ;
input detect_start;
input ro_prev_d1_reg;
input bit_cnt_en;
input scl_falling_edge;
input dtc_i;
input [0:0]SR;
input s_axi_aclk;
wire [0:0]E;
wire EarlyAckDataState0;
wire \FSM_onehot_state[6]_i_4_n_0 ;
wire \FSM_onehot_state[6]_i_7_n_0 ;
wire \FSM_onehot_state_reg[4] ;
wire [0:0]SR;
wire [3:0]bit_cnt;
wire bit_cnt_en;
wire detect_start;
wire dtc_i;
wire dtc_i_reg;
wire [5:0]out;
wire [3:0]p_0_in;
wire \q_int[0]_i_1__1_n_0 ;
wire \q_int[0]_i_3__1_n_0 ;
wire ro_prev_d1_reg;
wire s_axi_aclk;
wire scl_falling_edge;
LUT6 #(
.INIT(64'hAEAAAAAAAAAAAAEA))
EarlyAckDataState_i_1
(.I0(out[4]),
.I1(out[3]),
.I2(bit_cnt[3]),
.I3(bit_cnt[2]),
.I4(bit_cnt[0]),
.I5(bit_cnt[1]),
.O(EarlyAckDataState0));
LUT5 #(
.INIT(32'h0000FEEE))
\FSM_onehot_state[6]_i_2
(.I0(\FSM_onehot_state[6]_i_4_n_0 ),
.I1(out[2]),
.I2(detect_start),
.I3(out[0]),
.I4(ro_prev_d1_reg),
.O(E));
LUT6 #(
.INIT(64'hFFFEFFFEFFFCFCFC))
\FSM_onehot_state[6]_i_4
(.I0(out[1]),
.I1(out[5]),
.I2(out[4]),
.I3(\FSM_onehot_state_reg[4] ),
.I4(detect_start),
.I5(\FSM_onehot_state[6]_i_7_n_0 ),
.O(\FSM_onehot_state[6]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT4 #(
.INIT(16'h0010))
\FSM_onehot_state[6]_i_7
(.I0(bit_cnt[1]),
.I1(bit_cnt[0]),
.I2(bit_cnt[3]),
.I3(bit_cnt[2]),
.O(\FSM_onehot_state[6]_i_7_n_0 ));
LUT6 #(
.INIT(64'h0080FFFF00800000))
dtc_i_i_1
(.I0(bit_cnt[2]),
.I1(bit_cnt[0]),
.I2(bit_cnt[1]),
.I3(bit_cnt[3]),
.I4(scl_falling_edge),
.I5(dtc_i),
.O(dtc_i_reg));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\q_int[0]_i_1__1
(.I0(bit_cnt_en),
.I1(detect_start),
.I2(out[0]),
.I3(out[4]),
.I4(out[5]),
.I5(out[2]),
.O(\q_int[0]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT5 #(
.INIT(32'h2AAA8000))
\q_int[0]_i_2__1
(.I0(\q_int[0]_i_3__1_n_0 ),
.I1(bit_cnt[1]),
.I2(bit_cnt[0]),
.I3(bit_cnt[2]),
.I4(bit_cnt[3]),
.O(p_0_in[3]));
LUT5 #(
.INIT(32'h00000001))
\q_int[0]_i_3__1
(.I0(out[2]),
.I1(out[5]),
.I2(out[4]),
.I3(out[0]),
.I4(detect_start),
.O(\q_int[0]_i_3__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT4 #(
.INIT(16'h2A80))
\q_int[1]_i_1
(.I0(\q_int[0]_i_3__1_n_0 ),
.I1(bit_cnt[0]),
.I2(bit_cnt[1]),
.I3(bit_cnt[2]),
.O(p_0_in[2]));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT3 #(
.INIT(8'h28))
\q_int[2]_i_1
(.I0(\q_int[0]_i_3__1_n_0 ),
.I1(bit_cnt[0]),
.I2(bit_cnt[1]),
.O(p_0_in[1]));
LUT6 #(
.INIT(64'h0000000000000001))
\q_int[3]_i_1
(.I0(detect_start),
.I1(out[0]),
.I2(out[4]),
.I3(out[5]),
.I4(out[2]),
.I5(bit_cnt[0]),
.O(p_0_in[0]));
FDRE \q_int_reg[0]
(.C(s_axi_aclk),
.CE(\q_int[0]_i_1__1_n_0 ),
.D(p_0_in[3]),
.Q(bit_cnt[3]),
.R(SR));
FDRE \q_int_reg[1]
(.C(s_axi_aclk),
.CE(\q_int[0]_i_1__1_n_0 ),
.D(p_0_in[2]),
.Q(bit_cnt[2]),
.R(SR));
FDRE \q_int_reg[2]
(.C(s_axi_aclk),
.CE(\q_int[0]_i_1__1_n_0 ),
.D(p_0_in[1]),
.Q(bit_cnt[1]),
.R(SR));
FDRE \q_int_reg[3]
(.C(s_axi_aclk),
.CE(\q_int[0]_i_1__1_n_0 ),
.D(p_0_in[0]),
.Q(bit_cnt[0]),
.R(SR));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O22AI_PP_SYMBOL_V
`define SKY130_FD_SC_LP__O22AI_PP_SYMBOL_V
/**
* o22ai: 2-input OR into both inputs of 2-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2))
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__o22ai (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
input B2 ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__O22AI_PP_SYMBOL_V
|
/////////////////////////////////////////////////////////////////////
//// ////
//// SPI Slave Model ////
//// ////
//// Authors: Richard Herveille ([email protected]) www.asics.ws ////
//// ////
//// http://www.opencores.org/projects/simple_spi/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2004 Richard Herveille ////
//// [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: spi_slave_model.v,v 1.1 2004-02-28 16:01:47 rherveille Exp $
//
// $Date: 2004-02-28 16:01:47 $
// $Revision: 1.1 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: not supported by cvs2svn $
//
//
//
// Requires: Verilog2001
`include "timescale.v"
module spi_slave_model (
input wire csn;
input wire sck
input wire di;
output wire do
);
//
// Variable declaration
//
wire debug = 1'b1;
wire cpol = 1'b0;
wire cpha = 1'b0;
reg [7:0] mem [7:0]; // initiate memory
reg [2:0] mem_adr; // memory address
reg [7:0] mem_do; // memory data output
reg [7:0] sri, sro; // 8bit shift register
reg [2:0] bit_cnt;
reg ld;
wire clk;
//
// module body
//
assign clk = cpol ^ cpha ^ sck;
// generate shift registers
always @(posedge clk)
sri <= #1 {sri[6:0],di};
always @(posedge clk)
if (&bit_cnt)
sro <= #1 mem[mem_adr];
else
sro <= #1 {sro[6:0],1'bx};
assign do = sro[7];
//generate bit-counter
always @(posedge clk, posedge csn)
if(csn)
bit_cnt <= #1 3'b111;
else
bit_cnt <= #1 bit_cnt - 3'h1;
//generate access done signal
always @(posedge clk)
ld <= #1 ~(|bit_cnt);
always @(negedge clk)
if (ld) begin
mem[mem_adr] <= #1 sri;
mem_adr <= #1 mem_adr + 1'b1;
end
initial
begin
bit_cnt=3'b111;
mem_adr = 0;
sro = mem[mem_adr];
end
endmodule
|
// file: clk_wiz_0.v
//
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// CLK_OUT1____50.000______0.000______50.0______167.017____114.212
// CLK_OUT2____25.000______0.000______50.0______191.696____114.212
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
//----------------------------------------------------------------------------
// __primary_________100.000____________0.010
`timescale 1ps/1ps
module clk_wiz_0_clk_wiz
(// Clock in ports
input clk_in1,
// Clock out ports
output clk_out1,
output clk_out2
);
// Input buffering
//------------------------------------
IBUF clkin1_ibufg
(.O (clk_in1_clk_wiz_0),
.I (clk_in1));
// Clocking PRIMITIVE
//------------------------------------
// Instantiation of the MMCM PRIMITIVE
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire [15:0] do_unused;
wire drdy_unused;
wire psdone_unused;
wire locked_int;
wire clkfbout_clk_wiz_0;
wire clkfbout_buf_clk_wiz_0;
wire clkfboutb_unused;
wire clkout2_unused;
wire clkout3_unused;
wire clkout4_unused;
wire clkout5_unused;
wire clkout6_unused;
wire clkfbstopped_unused;
wire clkinstopped_unused;
PLLE2_ADV
#(.BANDWIDTH ("OPTIMIZED"),
.COMPENSATION ("ZHOLD"),
.DIVCLK_DIVIDE (1),
.CLKFBOUT_MULT (8),
.CLKFBOUT_PHASE (0.000),
.CLKOUT0_DIVIDE (16),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT1_DIVIDE (32),
.CLKOUT1_PHASE (0.000),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKIN1_PERIOD (10.0),
.REF_JITTER1 (0.010))
plle2_adv_inst
// Output clocks
(
.CLKFBOUT (clkfbout_clk_wiz_0),
.CLKOUT0 (clk_out1_clk_wiz_0),
.CLKOUT1 (clk_out2_clk_wiz_0),
.CLKOUT2 (clkout2_unused),
.CLKOUT3 (clkout3_unused),
.CLKOUT4 (clkout4_unused),
.CLKOUT5 (clkout5_unused),
// Input clock control
.CLKFBIN (clkfbout_buf_clk_wiz_0),
.CLKIN1 (clk_in1_clk_wiz_0),
.CLKIN2 (1'b0),
// Tied to always select the primary input clock
.CLKINSEL (1'b1),
// Ports for dynamic reconfiguration
.DADDR (7'h0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'h0),
.DO (do_unused),
.DRDY (drdy_unused),
.DWE (1'b0),
// Other control and status signals
.LOCKED (locked_int),
.PWRDWN (1'b0),
.RST (1'b0));
// Output buffering
//-----------------------------------
BUFG clkf_buf
(.O (clkfbout_buf_clk_wiz_0),
.I (clkfbout_clk_wiz_0));
BUFG clkout1_buf
(.O (clk_out1),
.I (clk_out1_clk_wiz_0));
BUFG clkout2_buf
(.O (clk_out2),
.I (clk_out2_clk_wiz_0));
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module util_jesd_align (
// xcvr interface
rx_clk,
rx_ip_sof,
rx_ip_data,
rx_sof,
rx_data);
// parameters
parameter NUM_OF_LANES = 2;
// xcvr interface
input rx_clk;
input [ 3:0] rx_ip_sof;
input [((NUM_OF_LANES*32)-1):0] rx_ip_data;
output [((NUM_OF_LANES* 1)-1):0] rx_sof;
output [((NUM_OF_LANES*32)-1):0] rx_data;
// only for altera, xcvr+jesd do not frame align
genvar n;
generate
for (n = 0; n < NUM_OF_LANES; n = n + 1) begin: g_lane
ad_jesd_align i_jesd_align (
.rx_clk (rx_clk),
.rx_ip_sof (rx_ip_sof),
.rx_ip_data (rx_ip_data[n*32+31:n*32]),
.rx_sof (rx_sof[n]),
.rx_data (rx_data[n*32+31:n*32]));
end
endgenerate
endmodule
// ***************************************************************************
// ***************************************************************************
|
Require Import Iron.Language.SystemF.Preservation.
Require Export Iron.Language.SystemF.Step.
Require Export Iron.Language.SystemF.SubstExpExp.
Require Export Iron.Language.SystemF.SubstTypeExp.
Require Import Iron.Language.SystemF.TyJudge.
Require Export Iron.Language.SystemF.Exp.
(********************************************************************)
(* Big Step Evaluation
This is also called 'Natural Semantics'.
It provides a relation between the expression to be reduced
and its final value.
*)
Inductive EVAL : exp -> exp -> Prop :=
| EVDone
: forall v2
, wnfX v2
-> EVAL v2 v2
| EVLAMAPP
: forall x1 x12 t2 v3
, EVAL x1 (XLAM x12) -> EVAL (substTX 0 t2 x12) v3
-> EVAL (XAPP x1 t2) v3
| EVLamApp
: forall x1 t11 x12 x2 v2 v3
, EVAL x1 (XLam t11 x12) -> EVAL x2 v2 -> EVAL (substXX 0 v2 x12) v3
-> EVAL (XApp x1 x2) v3.
Hint Constructors EVAL.
(* A terminating big-step evaluation always produces a wnf.
The fact that the evaluation terminated is implied by the fact
that we have a finite proof of EVAL to pass to this lemma.
*)
Lemma eval_produces_wnfX
: forall x1 v1
, EVAL x1 v1
-> wnfX v1.
Proof.
intros. induction H; eauto.
Qed.
Hint Resolve eval_produces_wnfX.
(********************************************************************)
(* Convert a big-step evaluation into a list of small steps. *)
Lemma steps_of_eval
: forall x1 t1 x2
, TYPE nil nil x1 t1
-> EVAL x1 x2
-> STEPS x1 x2.
Proof.
intros x1 t1 v2 HT HE. gen t1.
(* Induction over the form of (EVAL x1 x2) *)
induction HE.
Case "EVDone".
intros. apply ESNone.
Case "EVLAMAPP".
intros. inverts HT.
lets E1: IHHE1 H3. clear IHHE1.
lets T1: preservation_steps H3 E1. inverts keep T1.
lets T2: subst_type_value H4 H5.
simpl in T2.
lets E2: IHHE2 T2.
eapply ESAppend.
apply steps_APP1. eauto.
eapply ESAppend.
eapply ESStep.
eapply ESLAMAPP. auto.
Case "EVLamApp".
intros. inverts HT.
lets E1: IHHE1 H3.
lets E2: IHHE2 H5.
lets T1: preservation_steps H3 E1. inverts keep T1.
lets T2: preservation_steps H5 E2.
lets T3: subst_value_value H8 T2.
lets E3: IHHE3 T3.
eapply ESAppend.
eapply steps_app1. eauto.
eapply ESAppend.
eapply steps_app2. eauto. eauto.
eapply ESAppend.
eapply ESStep.
eapply ESLamApp. eauto.
eauto.
Qed.
(********************************************************************)
(* Convert a list of small steps to a big-step evaluation. The main
part of this is the expansion lemma, which we use to build up the
overall big-step evaluation one small-step at a time. The other
lemmas are used to feed it small-steps.
*)
(* Given an existing big-step evalution, we can produce a new one
that does an extra step before returning the original value.
*)
Lemma eval_expansion
: forall ke te x1 t1 x2 v3
, TYPE ke te x1 t1
-> STEP x1 x2 -> EVAL x2 v3
-> EVAL x1 v3.
Proof.
intros. gen ke te t1 v3.
(* Induction over the form of (STEP x1 x2) *)
induction H0; intros.
Case "XApp".
SCase "value app".
eapply EVLamApp.
eauto.
inverts H.
apply EVDone. auto. auto.
SCase "x1 steps".
inverts H. inverts H1.
inverts H.
eapply EVLamApp; eauto.
SCase "x2 steps".
inverts H1. inverts H2.
inverts H1.
eapply EVLamApp; eauto.
Case "XAPP".
SCase "type app".
eapply EVLAMAPP.
eauto.
inverts H.
auto.
SCase "x1 steps".
inverts H. inverts H1.
inverts H.
eapply EVLAMAPP; eauto.
Qed.
(* Convert a list of small steps to a big-step evaluation. *)
Lemma eval_of_stepsl
: forall x1 t1 v2
, TYPE nil nil x1 t1
-> STEPSL x1 v2 -> value v2
-> EVAL x1 v2.
Proof.
intros.
induction H0.
Case "ESLNone".
apply EVDone. inverts H1. auto.
Case "ESLCons".
eapply eval_expansion.
eauto. eauto.
apply IHSTEPSL.
eapply preservation. eauto. auto. auto.
Qed.
(* Convert a multi-step evaluation to a big-step evaluation.
We use stepsl_of_steps to flatten out the append constructors
in the multi-step evaluation, leaving a list of individual
small-steps.
*)
Lemma eval_of_steps
: forall x1 t1 v2
, TYPE nil nil x1 t1
-> STEPS x1 v2 -> value v2
-> EVAL x1 v2.
Proof.
intros.
eapply eval_of_stepsl; eauto.
apply stepsl_of_steps; auto.
Qed.
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFHV2HV_HL_FUNCTIONAL_V
`define SKY130_FD_SC_HVL__LSBUFHV2HV_HL_FUNCTIONAL_V
/**
* lsbufhv2hv_hl: Level shifting buffer, High Voltage to High Voltage,
* Higher Voltage to Lower Voltage.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__lsbufhv2hv_hl (
X,
A
);
// Module ports
output X;
input A;
// Name Output Other arguments
buf buf0 (X , A );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFHV2HV_HL_FUNCTIONAL_V
|
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